blob: bf8e1a5cb44513c7a8dc22ac2fc43d0130dcb545 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
|
// SPDX-License-Identifier: GPL-2.0+
#include <asm/io.h>
#include <asm/arch/hardware.h>
#include <asm/arch/spl.h>
static u32 __get_backup_bootmedia(u32 main_devstat)
{
u32 bkup_bootmode =
(main_devstat & MAIN_DEVSTAT_BACKUP_BOOTMODE_MASK) >>
MAIN_DEVSTAT_BACKUP_BOOTMODE_SHIFT;
u32 bkup_bootmode_cfg =
(main_devstat & MAIN_DEVSTAT_BACKUP_BOOTMODE_CFG_MASK) >>
MAIN_DEVSTAT_BACKUP_BOOTMODE_CFG_SHIFT;
switch (bkup_bootmode) {
case BACKUP_BOOT_DEVICE_UART:
return BOOT_DEVICE_UART;
case BACKUP_BOOT_DEVICE_DFU:
if (bkup_bootmode_cfg & MAIN_DEVSTAT_BACKUP_USB_MODE_MASK)
return BOOT_DEVICE_USB;
return BOOT_DEVICE_DFU;
case BACKUP_BOOT_DEVICE_ETHERNET:
return BOOT_DEVICE_ETHERNET;
case BACKUP_BOOT_DEVICE_MMC:
if (bkup_bootmode_cfg)
return BOOT_DEVICE_MMC2;
return BOOT_DEVICE_MMC1;
case BACKUP_BOOT_DEVICE_SPI:
return BOOT_DEVICE_SPI;
case BACKUP_BOOT_DEVICE_I2C:
return BOOT_DEVICE_I2C;
};
return BOOT_DEVICE_RAM;
}
static u32 __get_primary_bootmedia(u32 main_devstat)
{
u32 bootmode = (main_devstat & MAIN_DEVSTAT_PRIMARY_BOOTMODE_MASK) >>
MAIN_DEVSTAT_PRIMARY_BOOTMODE_SHIFT;
u32 bootmode_cfg =
(main_devstat & MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_MASK) >>
MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_SHIFT;
switch (bootmode) {
case BOOT_DEVICE_OSPI:
fallthrough;
case BOOT_DEVICE_QSPI:
fallthrough;
case BOOT_DEVICE_XSPI:
fallthrough;
case BOOT_DEVICE_SPI:
return BOOT_DEVICE_SPI;
case BOOT_DEVICE_ETHERNET_RGMII:
fallthrough;
case BOOT_DEVICE_ETHERNET_RMII:
return BOOT_DEVICE_ETHERNET;
case BOOT_DEVICE_EMMC:
return BOOT_DEVICE_MMC1;
case BOOT_DEVICE_NAND:
return BOOT_DEVICE_NAND;
case BOOT_DEVICE_MMC:
if ((bootmode_cfg & MAIN_DEVSTAT_PRIMARY_MMC_PORT_MASK) >>
MAIN_DEVSTAT_PRIMARY_MMC_PORT_SHIFT)
return BOOT_DEVICE_MMC2;
return BOOT_DEVICE_MMC1;
case BOOT_DEVICE_DFU:
if ((bootmode_cfg & MAIN_DEVSTAT_PRIMARY_USB_MODE_MASK) >>
MAIN_DEVSTAT_PRIMARY_USB_MODE_SHIFT)
return BOOT_DEVICE_USB;
return BOOT_DEVICE_DFU;
case BOOT_DEVICE_NOBOOT:
return BOOT_DEVICE_RAM;
}
return bootmode;
}
u32 get_boot_device(void)
{
u32 devstat = readl(CTRLMMR_MAIN_DEVSTAT);
u32 bootmode = *(u32 *)(CONFIG_SYS_K3_BOOT_PARAM_TABLE_INDEX);
u32 bootmedia;
if (bootmode == K3_PRIMARY_BOOTMODE)
bootmedia = __get_primary_bootmedia(devstat);
else
bootmedia = __get_backup_bootmedia(devstat);
debug("%s: devstat = 0x%x bootmedia = 0x%x bootmode = %d\n",
__func__, devstat, bootmedia, bootmode);
return bootmedia;
}
const char *get_reset_reason(void)
{
u32 reset_reason = readl(CTRLMMR_MCU_RST_SRC);
/* After reading reset source register, software must clear it */
if (reset_reason)
writel(reset_reason, CTRLMMR_MCU_RST_SRC);
if (reset_reason == 0 ||
(reset_reason & (RST_SRC_SW_MAIN_POR_FROM_MAIN |
RST_SRC_SW_MAIN_POR_FROM_MCU)))
return "POR";
if (reset_reason & (RST_SRC_SAFETY_ERR | RST_SRC_MAIN_ESM_ERR))
return "ESM";
if (reset_reason & (RST_SRC_SW_MAIN_WARM_FROM_MAIN |
RST_SRC_SW_MAIN_WARM_FROM_MCU |
RST_SRC_SW_MCU_WARM_RST))
return "RST";
if (reset_reason & (RST_SRC_SMS_WARM_RST | RST_SRC_SMS_COLD_RST))
return "DMSC";
if (reset_reason & RST_SRC_DEBUG_RST)
return "JTAG";
if (reset_reason & RST_SRC_THERMAL_RST)
return "THERMAL";
if (reset_reason & (RST_SRC_MAIN_RESET_PIN | RST_SRC_MCU_RESET_PIN))
return "PIN";
return "UNKNOWN";
}
|
