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/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Keystone3 Quality of service endpoint definitions
* Auto generated by K3 Resource Partitioning Tool
*
* Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
*/
#define SMS_WKUP_0_TIFS_VBUSP_M 0x45D00000
#define SMS_WKUP_0_HSM_VBUSP_M 0x45D00400
#define PULSAR_SL_MCU_0_CPU0_RMST 0x45D10000
#define PULSAR_SL_MCU_0_CPU0_WMST 0x45D10400
#define PULSAR_SL_MCU_0_CPU0_PMST 0x45D10800
#define PULSAR_SL_MCU_0_CPU1_RMST 0x45D11000
#define PULSAR_SL_MCU_0_CPU1_WMST 0x45D11400
#define PULSAR_SL_MCU_0_CPU1_PMST 0x45D11800
#define SA3SS_AM62_MCU_0_CTXCACH_EXT_DMA 0x45D13000
#define PULSAR_SL_MAIN_0_PBDG_RMST0 0x45D78000
#define PULSAR_SL_MAIN_0_PBDG_WMST0 0x45D78400
#define PULSAR_SL_MAIN_0_PBDG_RMST1 0x45D78800
#define PULSAR_SL_MAIN_0_PBDG_WMST1 0x45D78C00
#define EMMCSD4SS_MAIN_0_EMMCSDSS_RD 0x45D82800
#define EMMCSD4SS_MAIN_0_EMMCSDSS_WR 0x45D82C00
#define COMPUTE_CLUSTER_J7AHP_MAIN_0_GIC_MEM_RD_VBUSM 0x45D86000
#define COMPUTE_CLUSTER_J7AHP_MAIN_0_GIC_MEM_WR_VBUSM 0x45D86400
#define PCIE_G3X4_128_MAIN_0_PCIE_MST_RD 0x45D98400
#define PCIE_G3X4_128_MAIN_0_PCIE_MST_WR 0x45D98C00
#define PCIE_G3X4_128_MAIN_1_PCIE_MST_RD 0x45D99400
#define PCIE_G3X4_128_MAIN_1_PCIE_MST_WR 0x45D99C00
#define USB3P0SS_16FFC_MAIN_0_MSTR0 0x45D9A000
#define USB3P0SS_16FFC_MAIN_0_MSTW0 0x45D9A400
#define UFSHCI2P1SS_16FFC_MAIN_0_UFSHCI_VBM_MST_RD 0x45D9AC00
#define UFSHCI2P1SS_16FFC_MAIN_0_UFSHCI_VBM_MST_WR 0x45D9B000
#define EMMC8SS_16FFC_MAIN_0_EMMCSS_WR 0x45D9B400
#define EMMC8SS_16FFC_MAIN_0_EMMCSS_RD 0x45D9B800
#define SA2_UL_MAIN_0_CTXCACH_EXT_DMA 0x45D9BC00
#define VUSR_DUAL_MAIN_0_V0_M 0x45D9C000
#define VUSR_DUAL_MAIN_0_V1_M 0x45D9C400
#define DEBUGSS_K3_WRAP_CV0_MAIN_0_VBUSMR 0x45DA0000
#define DEBUGSS_K3_WRAP_CV0_MAIN_0_VBUSMW 0x45DA0400
#define PULSAR_SL_MAIN_1_CPU0_RMST 0x45DA8000
#define PULSAR_SL_MAIN_1_CPU0_WMST 0x45DA8400
#define PULSAR_SL_MAIN_1_CPU1_RMST 0x45DA8800
#define PULSAR_SL_MAIN_1_CPU1_WMST 0x45DA8C00
#define PULSAR_SL_MAIN_2_CPU0_RMST 0x45DA9000
#define PULSAR_SL_MAIN_2_CPU0_WMST 0x45DA9400
#define PULSAR_SL_MAIN_2_CPU1_RMST 0x45DA9800
#define PULSAR_SL_MAIN_2_CPU1_WMST 0x45DA9C00
#define DMPAC_TOP_MAIN_0_DATA_MST 0x45DC0000
#define K3_VPU_WAVE521CL_MAIN_0_SEC_M_VBUSM_R_ASYNC 0x45DC0C00
#define K3_VPU_WAVE521CL_MAIN_0_SEC_M_VBUSM_W_ASYNC 0x45DC1000
#define VPAC_TOP_MAIN_0_DATA_MST_0 0x45DC1400
#define VPAC_TOP_MAIN_0_DATA_MST_1 0x45DC1800
#define VPAC_TOP_MAIN_0_LDC0_M_MST 0x45DC1C00
#define K3_DSS_MAIN_0_DSS_INST0_VBUSM_DMA 0x45DC2000
#define K3_DSS_MAIN_0_DSS_INST0_VBUSM_FBDC 0x45DC2400
#define VPAC_TOP_MAIN_1_LDC0_M_MST 0x45DC2800
#define VPAC_TOP_MAIN_1_DATA_MST_0 0x45DC2C00
#define VPAC_TOP_MAIN_1_DATA_MST_1 0x45DC3000
#define K3_VPU_WAVE521CL_MAIN_0_PRI_M_VBUSM_R_ASYNC 0x45DC3400
#define K3_VPU_WAVE521CL_MAIN_0_PRI_M_VBUSM_W_ASYNC 0x45DC3800
#define K3_VPU_WAVE521CL_MAIN_1_SEC_M_VBUSM_R_ASYNC 0x45DC3C00
#define K3_VPU_WAVE521CL_MAIN_1_SEC_M_VBUSM_W_ASYNC 0x45DC4000
#define K3_VPU_WAVE521CL_MAIN_1_PRI_M_VBUSM_R_ASYNC 0x45DC4400
#define K3_VPU_WAVE521CL_MAIN_1_PRI_M_VBUSM_W_ASYNC 0x45DC4800
#define J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_R_SYNC 0x45DC5000
#define J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_W_SYNC 0x45DC5800
#define PULSAR_SL_MAIN_0_CPU0_RMST 0x45DC8000
#define PULSAR_SL_MAIN_0_CPU0_WMST 0x45DC8400
#define PULSAR_SL_MAIN_0_CPU1_RMST 0x45DC8800
#define PULSAR_SL_MAIN_0_CPU1_WMST 0x45DC8C00
#define PULSAR_SL_MAIN_1_PBDG_RMST0 0x45DCA000
#define PULSAR_SL_MAIN_1_PBDG_WMST0 0x45DCA400
#define PULSAR_SL_MAIN_1_PBDG_RMST1 0x45DCA800
#define PULSAR_SL_MAIN_1_PBDG_WMST1 0x45DCAC00
#define PULSAR_SL_MAIN_2_PBDG_RMST0 0x45DCB000
#define PULSAR_SL_MAIN_2_PBDG_WMST0 0x45DCB400
#define PULSAR_SL_MAIN_2_PBDG_RMST1 0x45DCB800
#define PULSAR_SL_MAIN_2_PBDG_WMST1 0x45DCBC00
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