1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
|
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2024 Rockchip Electronics Co., Ltd
*/
#include <asm/armv8/mmu.h>
#include <asm/arch-rockchip/bootrom.h>
#include <asm/arch-rockchip/hardware.h>
#define SYS_GRF_BASE 0x2600A000
#define SYS_GRF_SOC_CON2 0x0008
#define SYS_GRF_SOC_CON7 0x001c
#define SYS_GRF_SOC_CON11 0x002c
#define SYS_GRF_SOC_CON12 0x0030
#define GPIO0_IOC_BASE 0x26040000
#define GPIO0B_PULL_L 0x0024
#define GPIO0B_IE_L 0x002C
#define SYS_SGRF_BASE 0x26004000
#define SYS_SGRF_SOC_CON14 0x0058
#define SYS_SGRF_SOC_CON15 0x005C
#define SYS_SGRF_SOC_CON20 0x0070
#define FW_SYS_SGRF_BASE 0x26005000
#define SGRF_DOMAIN_CON1 0x4
#define SGRF_DOMAIN_CON2 0x8
#define SGRF_DOMAIN_CON3 0xc
#define SGRF_DOMAIN_CON4 0x10
#define SGRF_DOMAIN_CON5 0x14
const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = {
[BROM_BOOTSOURCE_EMMC] = "/soc/mmc@2a330000",
[BROM_BOOTSOURCE_SD] = "/soc/mmc@2a310000",
};
static struct mm_region rk3576_mem_map[] = {
{
/* I/O area */
.virt = 0x20000000UL,
.phys = 0x20000000UL,
.size = 0xb080000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN
}, {
/* PMU_SRAM, CBUF, SYSTEM_SRAM */
.virt = 0x3fe70000UL,
.phys = 0x3fe70000UL,
.size = 0x190000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN
}, {
/* MSCH_DDR_PORT */
.virt = 0x40000000UL,
.phys = 0x40000000UL,
.size = 0x400000000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_INNER_SHARE
}, {
/* PCIe 0+1 */
.virt = 0x900000000UL,
.phys = 0x900000000UL,
.size = 0x100800000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN
}, {
/* List terminator */
0,
}
};
struct mm_region *mem_map = rk3576_mem_map;
void board_debug_uart_init(void)
{
}
#define HP_TIMER_BASE CONFIG_ROCKCHIP_STIMER_BASE
#define HP_CTRL_REG 0x04
#define TIMER_EN BIT(0)
#define HP_LOAD_COUNT0_REG 0x14
#define HP_LOAD_COUNT1_REG 0x18
void rockchip_stimer_init(void)
{
u32 reg;
if (!IS_ENABLED(CONFIG_XPL_BUILD))
return;
reg = readl(HP_TIMER_BASE + HP_CTRL_REG);
if (reg & TIMER_EN)
return;
asm volatile("msr cntfrq_el0, %0" : : "r" (CONFIG_COUNTER_FREQUENCY));
writel(0xffffffff, HP_TIMER_BASE + HP_LOAD_COUNT0_REG);
writel(0xffffffff, HP_TIMER_BASE + HP_LOAD_COUNT1_REG);
writel((TIMER_EN << 16) | TIMER_EN, HP_TIMER_BASE + HP_CTRL_REG);
}
int arch_cpu_init(void)
{
u32 val;
if (!IS_ENABLED(CONFIG_SPL_BUILD))
return 0;
/* Set the emmc to access ddr memory */
val = readl(FW_SYS_SGRF_BASE + SGRF_DOMAIN_CON2);
writel(val | 0x7, FW_SYS_SGRF_BASE + SGRF_DOMAIN_CON2);
/* Set the sdmmc0 to access ddr memory */
val = readl(FW_SYS_SGRF_BASE + SGRF_DOMAIN_CON5);
writel(val | 0x700, FW_SYS_SGRF_BASE + SGRF_DOMAIN_CON5);
/* Set the UFS to access ddr memory */
val = readl(FW_SYS_SGRF_BASE + SGRF_DOMAIN_CON3);
writel(val | 0x70000, FW_SYS_SGRF_BASE + SGRF_DOMAIN_CON3);
/* Set the fspi0 and fspi1 to access ddr memory */
val = readl(FW_SYS_SGRF_BASE + SGRF_DOMAIN_CON4);
writel(val | 0x7700, FW_SYS_SGRF_BASE + SGRF_DOMAIN_CON4);
/* Set the decom to access ddr memory */
val = readl(FW_SYS_SGRF_BASE + SGRF_DOMAIN_CON1);
writel(val | 0x700, FW_SYS_SGRF_BASE + SGRF_DOMAIN_CON1);
/*
* Set the GPIO0B0~B3 pull up and input enable.
* Keep consistent with other IO.
*/
writel(0x00ff00ff, GPIO0_IOC_BASE + GPIO0B_PULL_L);
writel(0x000f000f, GPIO0_IOC_BASE + GPIO0B_IE_L);
/*
* Set SYS_GRF_SOC_CON2[12](input of pwm2_ch0) as 0,
* keep consistent with other pwm.
*/
writel(0x10000000, SYS_GRF_BASE + SYS_GRF_SOC_CON2);
/* Enable noc slave response timeout */
writel(0x80008000, SYS_GRF_BASE + SYS_GRF_SOC_CON11);
writel(0xffffffe0, SYS_GRF_BASE + SYS_GRF_SOC_CON12);
/*
* Enable cci channels for below module AXI R/W
* Module: GMAC0/1, MMU0/1(PCIe, SATA, USB3)
*/
writel(0xffffff00, SYS_SGRF_BASE + SYS_SGRF_SOC_CON20);
return 0;
}
|
