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/*
* MCR3000 Device Tree Source
*
* Copyright 2017 CS Systemes d'Information
*
* SPDX-License-Identifier: GPL-2.0+
*/
/dts-v1/;
/ {
#address-cells = <1>;
#size-cells = <1>;
soc: immr@ff000000 {
#address-cells = <1>;
#size-cells = <1>;
device-type = "soc";
compatible = "simple-bus";
ranges = <0 0xff000000 0x4000>;
reg = <0xff000000 0x00000200>;
WDT: watchdog@0 {
compatible = "fsl,pq1-wdt";
reg = <0x0 0x10>;
timeout-sec = <2>;
hw_margin_ms = <1000>;
};
spi: spi@aa0 {
status = "okay";
#address-cells = <1>;
#size-cells = <0>;
cell-index = <0>;
compatible = "fsl,mpc8xx-spi";
gpios = <&csspi 2 0
&csspi 0 0>;
temp@0 {
reg = <0>;
compatible = "ti,lm74";
};
fpga@1 {
reg = <1>;
};
};
};
localbus@ff000100 {
compatible = "s3k,mcr3000-localbus", "fsl,pq1-localbus", "simple-bus";
#address-cells = <2>;
#size-cells = <1>;
reg = <0xff000100 0x40>; // ORx and BRx register
ranges = <0 0 0x04000000 0x04000000 // BOOT
1 0 0x00000000 0x04000000 // SDRAM
2 0 0x08000000 0x04000000 // RAMDP
3 0 0x0C000000 0x04000000 // NAND
4 0 0x10000000 0x04000000 // Periphs
5 0 0x14000000 0x04000000 // FPGA
6 0 0x18000000 0x04000000 // mezzanine
7 0 0x1c000000 0x04000000>; // DSP
csspi: gpio-controller@2 {
#gpio-cells = <2>;
compatible = "s3k,mcr3000-cpld-csspi";
reg = <4 0x802 2>;
gpio-controller;
};
};
SERIAL: smc@0 {
compatible = "fsl,pq1-smc";
};
FEC: fec@0 {
compatible = "fsl,pq1-fec1";
};
chosen {
stdout-path = &SERIAL;
};
};
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