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// SPDX-License-Identifier: GPL-2.0 OR MIT
/*
* Copyright (C) 2022 StarFive Technology Co., Ltd.
*/
#include <dt-bindings/reset/starfive,jh7110-crg.h>
/ {
timer {
compatible = "riscv,timer";
interrupts-extended = <&cpu0_intc 5>,
<&cpu1_intc 5>,
<&cpu2_intc 5>,
<&cpu3_intc 5>,
<&cpu4_intc 5>;
};
soc {
bootph-pre-ram;
dmc: dmc@15700000 {
bootph-pre-ram;
compatible = "starfive,jh7110-dmc";
reg = <0x0 0x15700000 0x0 0x10000>,
<0x0 0x13000000 0x0 0x10000>;
resets = <&syscrg JH7110_SYSRST_DDR_AXI>,
<&syscrg JH7110_SYSRST_DDR_OSC>,
<&syscrg JH7110_SYSRST_DDR_APB>;
reset-names = "axi", "osc", "apb";
clocks = <&syscrg JH7110_PLLCLK_PLL1_OUT>;
clock-names = "pll1_out";
clock-frequency = <2133>;
};
};
};
&clint {
bootph-pre-ram;
};
&cpu0_intc {
bootph-pre-ram;
};
&cpu1_intc {
bootph-pre-ram;
};
&cpu2_intc {
bootph-pre-ram;
};
&cpu3_intc {
bootph-pre-ram;
};
&cpu4_intc {
bootph-pre-ram;
};
&cpus {
bootph-pre-ram;
};
&osc {
bootph-pre-ram;
};
&gmac0_rgmii_rxin {
bootph-pre-ram;
};
&gmac0_rmii_refin {
bootph-pre-ram;
};
&gmac1_rgmii_rxin {
bootph-pre-ram;
};
&gmac1_rmii_refin {
bootph-pre-ram;
};
&aoncrg {
bootph-pre-ram;
};
&pllclk {
bootph-pre-ram;
};
&syscrg {
assigned-clock-rates = <0>; /* cpufreq not implemented, use defaults */
bootph-pre-ram;
};
&stgcrg {
bootph-pre-ram;
};
&sys_syscon {
bootph-pre-ram;
};
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