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// SPDX-License-Identifier: GPL-2.0 OR MIT
/*
* Copyright (C) 2024 Yangyu Chen <cyy@cyyself.name>
* Copyright (C) 2025 Junhui Liu <junhui.liu@pigmoral.tech>
*/
#include <dt-bindings/interrupt-controller/irq.h>
/ {
#address-cells = <2>;
#size-cells = <2>;
compatible = "canaan,kendryte-k230";
aliases {
serial0 = &uart0;
serial1 = &uart1;
serial2 = &uart2;
serial3 = &uart3;
serial4 = &uart4;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
timebase-frequency = <27000000>;
cpu@0 {
compatible = "thead,c908", "riscv";
device_type = "cpu";
reg = <0>;
riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zfh_zba_zbb_zbc_zbs_zvfh_svpbmt";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
"zicbop", "zicboz", "zicntr", "zicsr", "zifencei",
"zihpm", "zfh", "zba", "zbb", "zbc", "zbs", "zvfh",
"svpbmt";
riscv,cbom-block-size = <64>;
riscv,cbop-block-size = <64>;
riscv,cboz-block-size = <64>;
mmu-type = "riscv,sv39";
cpu0_intc: interrupt-controller {
compatible = "riscv,cpu-intc";
interrupt-controller;
#interrupt-cells = <1>;
};
};
};
apb_clk: apb-clk-clock {
compatible = "fixed-clock";
clock-frequency = <50000000>;
clock-output-names = "apb_clk";
#clock-cells = <0>;
};
clk_dummy: clock-dummy {
compatible = "fixed-clock";
clock-frequency = <0>;
clock-output-names = "clk_dummy";
#clock-cells = <0>;
};
reboot: syscon-reboot {
compatible = "syscon-reboot";
regmap = <&bootctl>;
offset = <0x60>;
mask = <0x10001>;
value = <0x10001>;
};
soc {
compatible = "simple-bus";
interrupt-parent = <&plic>;
#address-cells = <2>;
#size-cells = <2>;
dma-noncoherent;
ranges;
bootctl: syscon@0x91102000 {
compatible = "syscon";
reg = <0x0 0x91102000 0x0 0x1000>;
};
plic: interrupt-controller@f00000000 {
compatible = "canaan,k230-plic" ,"thead,c900-plic";
reg = <0xf 0x00000000 0x0 0x04000000>;
interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>;
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <2>;
riscv,ndev = <208>;
};
clint: timer@f04000000 {
compatible = "canaan,k230-clint", "thead,c900-clint";
reg = <0xf 0x04000000 0x0 0x00010000>;
interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>;
};
uart0: serial@91400000 {
compatible = "snps,dw-apb-uart";
reg = <0x0 0x91400000 0x0 0x1000>;
clocks = <&apb_clk>;
interrupts = <16 IRQ_TYPE_LEVEL_HIGH>;
reg-io-width = <4>;
reg-shift = <2>;
status = "disabled";
};
uart1: serial@91401000 {
compatible = "snps,dw-apb-uart";
reg = <0x0 0x91401000 0x0 0x1000>;
clocks = <&apb_clk>;
interrupts = <17 IRQ_TYPE_LEVEL_HIGH>;
reg-io-width = <4>;
reg-shift = <2>;
status = "disabled";
};
uart2: serial@91402000 {
compatible = "snps,dw-apb-uart";
reg = <0x0 0x91402000 0x0 0x1000>;
clocks = <&apb_clk>;
interrupts = <18 IRQ_TYPE_LEVEL_HIGH>;
reg-io-width = <4>;
reg-shift = <2>;
status = "disabled";
};
uart3: serial@91403000 {
compatible = "snps,dw-apb-uart";
reg = <0x0 0x91403000 0x0 0x1000>;
clocks = <&apb_clk>;
interrupts = <19 IRQ_TYPE_LEVEL_HIGH>;
reg-io-width = <4>;
reg-shift = <2>;
status = "disabled";
};
uart4: serial@91404000 {
compatible = "snps,dw-apb-uart";
reg = <0x0 0x91404000 0x0 0x1000>;
clocks = <&apb_clk>;
interrupts = <20 IRQ_TYPE_LEVEL_HIGH>;
reg-io-width = <4>;
reg-shift = <2>;
status = "disabled";
};
usb0: usb@91500000 {
compatible = "canaan,k230-otg", "snps,dwc2";
reg = <0x0 0x91500000 0x0 0x40000>;
interrupts = <173 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_dummy>;
clock-names = "otg";
g-rx-fifo-size = <512>;
g-np-tx-fifo-size = <64>;
g-tx-fifo-size = <512 1024 64 64 64 64>;
status = "disabled";
};
usb1: usb@91540000 {
compatible = "canaan,k230-otg", "snps,dwc2";
reg = <0x0 0x91540000 0x0 0x40000>;
interrupts = <174 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_dummy>;
clock-names = "otg";
g-rx-fifo-size = <512>;
g-np-tx-fifo-size = <64>;
g-tx-fifo-size = <512 1024 64 64 64 64>;
status = "disabled";
};
};
};
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