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// SPDX-License-Identifier: GPL-2.0 OR MIT
/*
* Copyright (C) 2022 StarFive Technology Co., Ltd.
*/
// BEGIN "riscv: dts: starfive: jh7110: bootph-pre-ram hinting needed by boot loader"
// From upstream Linux conor/riscv-dt-for-next commit 8181cc2f3f21
#include <dt-bindings/reset/starfive,jh7110-crg.h>
&clint {
bootph-pre-ram;
};
&cpu0_intc {
bootph-pre-ram;
};
&cpu1_intc {
bootph-pre-ram;
};
&cpu2_intc {
bootph-pre-ram;
};
&cpu3_intc {
bootph-pre-ram;
};
&cpu4_intc {
bootph-pre-ram;
};
&osc {
bootph-pre-ram;
};
&gmac1_rgmii_rxin {
bootph-pre-ram;
};
&gmac1_rmii_refin {
bootph-pre-ram;
};
/ {
soc {
memory-controller@15700000 {
compatible = "starfive,jh7110-dmc";
reg = <0x0 0x15700000 0x0 0x10000>,
<0x0 0x13000000 0x0 0x10000>;
bootph-pre-ram;
clocks = <&syscrg JH7110_PLLCLK_PLL1_OUT>;
clock-names = "pll";
resets = <&syscrg JH7110_SYSRST_DDR_AXI>,
<&syscrg JH7110_SYSRST_DDR_OSC>,
<&syscrg JH7110_SYSRST_DDR_APB>;
reset-names = "axi", "osc", "apb";
};
};
};
&syscrg {
bootph-pre-ram;
};
&pllclk {
bootph-pre-ram;
};
// END "riscv: dts: starfive: jh7110: bootph-pre-ram hinting needed by boot loader"
/ {
soc {
memory-controller@15700000 {
clock-frequency = <2133>; /* FIXME: delete property and implement CCF */
};
};
};
&syscrg {
assigned-clock-rates = <0>; /* FIXME: delete property and implement cpufreq */
};
#include "starfive-visionfive2-binman.dtsi"
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