blob: 75e8c9b0d92f09553c8d725719e33b701c7a6e27 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
|
// SPDX-License-Identifier: GPL-2.0+
/*
* Brian Sune <briansune@gmail.com>
*/
#include <vsprintf.h>
#include <command.h>
#include <asm/io.h>
#include <asm/arch/base_addr_ac5.h>
#define RSTMGR_PERMODRST 0x18 /* PERMODRST register offset */
static int do_dmareset(struct cmd_tbl *cmdtp, int flag, int argc,
char * const argv[])
{
u8 val;
int i, ch;
if (argc < 2) {
printf("Usage: dmareset <channel 0-7> [<channel 0-7> ...]\n");
return CMD_RET_USAGE;
}
/* Read current register value */
val = readb(SOCFPGA_RSTMGR_ADDRESS + RSTMGR_PERMODRST);
/* Iterate over all channels given as arguments */
for (i = 1; i < argc; i++) {
ch = simple_strtoul(argv[i], NULL, 0);
if (ch < 0 || ch > 7) {
printf("Error: channel must be 0-7\n");
return CMD_RET_USAGE;
}
val &= ~(1 << ch);
printf("PL330 DMA channel %d reset released\n", ch);
}
/* Write back */
writeb(val, (SOCFPGA_RSTMGR_ADDRESS + RSTMGR_PERMODRST));
return 0;
}
U_BOOT_CMD(
dmareset, 8, 0, do_dmareset,
"Release PL330 DMA channel reset(s) for SoCFPGA",
"dmareset <channel 0-7> [<channel 0-7> ...] - release reset for one or more DMA channels"
);
|
