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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Copyright (c) 2024 MediaTek Inc.
* Author: Lu Tang <Lu.Tang@mediatek.com>
* Author: Sam Shih <sam.shih@mediatek.com>
*/
#ifndef _DT_BINDINGS_CLK_MT7987_H
#define _DT_BINDINGS_CLK_MT7987_H
/* INFRACFG */
#define CLK_INFRA_MUX_UART0_SEL 0
#define CLK_INFRA_MUX_UART1_SEL 1
#define CLK_INFRA_MUX_UART2_SEL 2
#define CLK_INFRA_MUX_SPI0_SEL 3
#define CLK_INFRA_MUX_SPI1_SEL 4
#define CLK_INFRA_MUX_SPI2_BCK_SEL 5
#define CLK_INFRA_PWM_BCK_SEL 6
#define CLK_INFRA_PCIE_GFMUX_TL_O_P0_SEL 7
#define CLK_INFRA_PCIE_GFMUX_TL_O_P1_SEL 8
#define CLK_INFRA_66M_GPT_BCK 9
#define CLK_INFRA_66M_PWM_HCK 10
#define CLK_INFRA_66M_PWM_BCK 11
#define CLK_INFRA_133M_CQDMA_BCK 12
#define CLK_INFRA_66M_AUD_SLV_BCK 13
#define CLK_INFRA_AUD_26M 14
#define CLK_INFRA_AUD_L 15
#define CLK_INFRA_AUD_AUD 16
#define CLK_INFRA_AUD_EG2 17
#define CLK_INFRA_DRAMC_F26M 18
#define CLK_INFRA_133M_DBG_ACKM 19
#define CLK_INFRA_66M_AP_DMA_BCK 20
#define CLK_INFRA_MSDC200_SRC 21
#define CLK_INFRA_66M_SEJ_BCK 22
#define CLK_INFRA_PRE_CK_SEJ_F13M 23
#define CLK_INFRA_66M_TRNG 24
#define CLK_INFRA_26M_THERM_SYSTEM 25
#define CLK_INFRA_I2C_BCK 26
#define CLK_INFRA_66M_UART0_PCK 27
#define CLK_INFRA_66M_UART1_PCK 28
#define CLK_INFRA_66M_UART2_PCK 29
#define CLK_INFRA_52M_UART0_CK 30
#define CLK_INFRA_52M_UART1_CK 31
#define CLK_INFRA_52M_UART2_CK 32
#define CLK_INFRA_NFI 33
#define CLK_INFRA_66M_NFI_HCK 34
#define CLK_INFRA_104M_SPI0 35
#define CLK_INFRA_104M_SPI1 36
#define CLK_INFRA_104M_SPI2_BCK 37
#define CLK_INFRA_66M_SPI0_HCK 38
#define CLK_INFRA_66M_SPI1_HCK 39
#define CLK_INFRA_66M_SPI2_HCK 40
#define CLK_INFRA_66M_FLASHIF_AXI 41
#define CLK_INFRA_RTC 42
#define CLK_INFRA_26M_ADC_BCK 43
#define CLK_INFRA_RC_ADC 44
#define CLK_INFRA_MSDC400 45
#define CLK_INFRA_MSDC2_HCK 46
#define CLK_INFRA_133M_MSDC_0_HCK 47
#define CLK_INFRA_66M_MSDC_0_HCK 48
#define CLK_INFRA_133M_CPUM_BCK 49
#define CLK_INFRA_BIST2FPC 50
#define CLK_INFRA_I2C_X16W_MCK_CK_P1 51
#define CLK_INFRA_I2C_X16W_PCK_CK_P1 52
#define CLK_INFRA_133M_USB_HCK 53
#define CLK_INFRA_133M_USB_HCK_CK_P1 54
#define CLK_INFRA_66M_USB_HCK 55
#define CLK_INFRA_66M_USB_HCK_CK_P1 56
#define CLK_INFRA_USB_SYS_CK_P1 57
#define CLK_INFRA_USB_CK_P1 58
#define CLK_INFRA_USB_FRMCNT_CK_P1 59
#define CLK_INFRA_USB_PIPE_CK_P1 60
#define CLK_INFRA_USB_UTMI_CK_P1 61
#define CLK_INFRA_USB_XHCI_CK_P1 62
#define CLK_INFRA_PCIE_GFMUX_TL_P0 63
#define CLK_INFRA_PCIE_GFMUX_TL_P1 64
#define CLK_INFRA_PCIE_PIPE_P0 65
#define CLK_INFRA_PCIE_PIPE_P1 66
#define CLK_INFRA_133M_PCIE_CK_P0 67
#define CLK_INFRA_133M_PCIE_CK_P1 68
#define CLK_INFRA_PCIE_PERI_26M_CK_P0 69
#define CLK_INFRA_PCIE_PERI_26M_CK_P1 70
#define CLK_INFRA_NR_CLK 71
/* TOPCKGEN */
#define CLK_TOP_CB_M_D2 0
#define CLK_TOP_CB_M_D3 1
#define CLK_TOP_M_D3_D2 2
#define CLK_TOP_CB_M_D4 3
#define CLK_TOP_CB_M_D8 4
#define CLK_TOP_M_D8_D2 5
#define CLK_TOP_CB_APLL2_D4 6
#define CLK_TOP_CB_NET1_D3 7
#define CLK_TOP_CB_NET1_D4 8
#define CLK_TOP_CB_NET1_D5 9
#define CLK_TOP_NET1_D5_D2 10
#define CLK_TOP_NET1_D5_D4 11
#define CLK_TOP_CB_NET1_D7 12
#define CLK_TOP_NET1_D7_D2 13
#define CLK_TOP_NET1_D7_D4 14
#define CLK_TOP_NET1_D8_D2 15
#define CLK_TOP_NET1_D8_D4 16
#define CLK_TOP_NET1_D8_D8 17
#define CLK_TOP_NET1_D8_D16 18
#define CLK_TOP_CB_NET2_D2 19
#define CLK_TOP_CB_NET2_D4 20
#define CLK_TOP_NET2_D4_D4 21
#define CLK_TOP_NET2_D4_D8 22
#define CLK_TOP_CB_NET2_D6 23
#define CLK_TOP_NET2_D7_D2 24
#define CLK_TOP_CB_NET2_D8 25
#define CLK_TOP_MSDC_D2 26
#define CLK_TOP_CB_CKSQ_40M 27
#define CLK_TOP_CKSQ_40M_D2 28
#define CLK_TOP_CB_RTC_32K 29
#define CLK_TOP_CB_RTC_32P7K 30
#define CLK_TOP_NETSYS_SEL 31
#define CLK_TOP_NETSYS_500M_SEL 32
#define CLK_TOP_NETSYS_2X_SEL 33
#define CLK_TOP_ETH_GMII_SEL 34
#define CLK_TOP_EIP_SEL 35
#define CLK_TOP_AXI_INFRA_SEL 36
#define CLK_TOP_UART_SEL 37
#define CLK_TOP_EMMC_250M_SEL 38
#define CLK_TOP_EMMC_400M_SEL 39
#define CLK_TOP_SPI_SEL 40
#define CLK_TOP_SPIM_MST_SEL 41
#define CLK_TOP_NFI_SEL 42
#define CLK_TOP_PWM_SEL 43
#define CLK_TOP_I2C_SEL 44
#define CLK_TOP_PCIE_MBIST_250M_SEL 45
#define CLK_TOP_PEXTP_TL_SEL 46
#define CLK_TOP_PEXTP_TL_P1_SEL 47
#define CLK_TOP_USB_SYS_P1_SEL 48
#define CLK_TOP_USB_XHCI_P1_SEL 49
#define CLK_TOP_AUD_SEL 50
#define CLK_TOP_A1SYS_SEL 51
#define CLK_TOP_AUD_L_SEL 52
#define CLK_TOP_A_TUNER_SEL 53
#define CLK_TOP_USB_PHY_SEL 54
#define CLK_TOP_SGM_0_SEL 55
#define CLK_TOP_SGM_SBUS_0_SEL 56
#define CLK_TOP_SGM_1_SEL 57
#define CLK_TOP_SGM_SBUS_1_SEL 58
#define CLK_TOP_SYSAXI_SEL 59
#define CLK_TOP_SYSAPB_SEL 60
#define CLK_TOP_ETH_REFCK_50M_SEL 61
#define CLK_TOP_ETH_SYS_200M_SEL 62
#define CLK_TOP_ETH_SYS_SEL 63
#define CLK_TOP_ETH_XGMII_SEL 64
#define CLK_TOP_DRAMC_SEL 65
#define CLK_TOP_DRAMC_MD32_SEL 66
#define CLK_TOP_INFRA_F26M_SEL 67
#define CLK_TOP_PEXTP_P0_SEL 68
#define CLK_TOP_PEXTP_P1_SEL 69
#define CLK_TOP_DA_XTP_GLB_P0_SEL 70
#define CLK_TOP_DA_XTP_GLB_P1_SEL 71
#define CLK_TOP_CKM_SEL 72
#define CLK_TOP_DA_CKM_XTAL_SEL 73
#define CLK_TOP_PEXTP_SEL 74
#define CLK_TOP_ETH_MII_SEL 75
#define CLK_TOP_EMMC_200M_SEL 76
#define CLK_TOP_AUD_I2S_M 77
#define CLK_TOP_NR_CLK 78
/* APMIXEDSYS */
#define CLK_APMIXED_MPLL 0
#define CLK_APMIXED_APLL2 1
#define CLK_APMIXED_NET1PLL 2
#define CLK_APMIXED_NET2PLL 3
#define CLK_APMIXED_WEDMCUPLL 4
#define CLK_APMIXED_SGMPLL 5
#define CLK_APMIXED_ARM_LL 6
#define CLK_APMIXED_MSDCPLL 7
#define CLK_APMIXED_NR_CLK 8
/* MCUSYS */
#define CLK_MCU_BUS_DIV_SEL 0
#define CLK_MCU_NR_CLK 1
/* SGMIISYS_0 */
#define CLK_SGM0_TX_EN 0
#define CLK_SGM0_RX_EN 1
#define CLK_SGMII0_NR_CLK 2
/* SGMIISYS_1 */
#define CLK_SGM1_TX_EN 0
#define CLK_SGM1_RX_EN 1
#define CLK_SGMII1_NR_CLK 2
/* ETHDMA */
#define CLK_ETHDMA_FE_EN 0
#define CLK_ETHDMA_GP2_EN 1
#define CLK_ETHDMA_GP1_EN 2
#define CLK_ETHDMA_GP3_EN 3
#define CLK_ETHDMA_NR_CLK 4
#endif /* _DT_BINDINGS_CLK_MT7987_H */
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