blob: b6f85ca149aa1931556458c2e7545cbbfd58acda (
plain)
| 1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
 | /* SPDX-License-Identifier: GPL-2.0
 *
 * Copyright (C) 2018 Renesas Electronics Corp.
 *
 */
#ifndef __DT_BINDINGS_CLOCK_R7S9210_CPG_MSSR_H__
#define __DT_BINDINGS_CLOCK_R7S9210_CPG_MSSR_H__
#include <dt-bindings/clock/renesas-cpg-mssr.h>
/* R7S9210 CPG Core Clocks */
#define R7S9210_CLK_I			0
#define R7S9210_CLK_G			1
#define R7S9210_CLK_B			2
#define R7S9210_CLK_P1			3
#define R7S9210_CLK_P1C			4
#define R7S9210_CLK_P0			5
#endif /* __DT_BINDINGS_CLOCK_R7S9210_CPG_MSSR_H__ */
 |