1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
|
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (C) 2026 MediaTek Inc. All Rights Reserved.
* Author: Bo-Chen Chen <rex-bc.chen@mediatek.com>
*/
#ifndef __MT6359_H_
#define __MT6359_H_
#define MT6359_REGULATOR_DRIVER "mt6359_regulator"
enum {
MT6359_ID_VS1 = 0,
MT6359_ID_VGPU11,
MT6359_ID_VMODEM,
MT6359_ID_VPU,
MT6359_ID_VCORE,
MT6359_ID_VS2,
MT6359_ID_VPA,
MT6359_ID_VPROC2,
MT6359_ID_VPROC1,
MT6359_ID_VCORE_SSHUB,
MT6359_ID_VGPU11_SSHUB = MT6359_ID_VCORE_SSHUB,
MT6359_ID_VAUD18 = 10,
MT6359_ID_VSIM1,
MT6359_ID_VIBR,
MT6359_ID_VRF12,
MT6359_ID_VUSB,
MT6359_ID_VSRAM_PROC2,
MT6359_ID_VIO18,
MT6359_ID_VCAMIO,
MT6359_ID_VCN18,
MT6359_ID_VFE28,
MT6359_ID_VCN13,
MT6359_ID_VCN33_1_BT,
MT6359_ID_VCN33_1_WIFI,
MT6359_ID_VAUX18,
MT6359_ID_VSRAM_OTHERS,
MT6359_ID_VEFUSE,
MT6359_ID_VXO22,
MT6359_ID_VRFCK,
MT6359_ID_VBIF28,
MT6359_ID_VIO28,
MT6359_ID_VEMC,
MT6359_ID_VCN33_2_BT,
MT6359_ID_VCN33_2_WIFI,
MT6359_ID_VA12,
MT6359_ID_VA09,
MT6359_ID_VRF18,
MT6359_ID_VSRAM_MD,
MT6359_ID_VUFS,
MT6359_ID_VM18,
MT6359_ID_VBBCK,
MT6359_ID_VSRAM_PROC1,
MT6359_ID_VSIM2,
MT6359_ID_VSRAM_OTHERS_SSHUB,
MT6359_ID_RG_MAX,
};
/* PMIC Registers */
#define MT6359_BUCK_VPU_CON0 0x1488
#define MT6359_BUCK_VPU_DBG1 0x14a8
#define MT6359_BUCK_VPU_ELR0 0x14ac
#define MT6359_BUCK_VCORE_CON0 0x1508
#define MT6359_BUCK_VCORE_DBG1 0x1528
#define MT6359_BUCK_VGPU11_CON0 0x1588
#define MT6359_BUCK_VGPU11_DBG1 0x15a8
#define MT6359_BUCK_VMODEM_CON0 0x1688
#define MT6359_BUCK_VMODEM_DBG1 0x16a8
#define MT6359_BUCK_VMODEM_ELR0 0x16ae
#define MT6359_BUCK_VPROC1_CON0 0x1708
#define MT6359_BUCK_VPROC1_DBG1 0x1728
#define MT6359_BUCK_VPROC1_ELR0 0x172e
#define MT6359_BUCK_VPROC2_CON0 0x1788
#define MT6359_BUCK_VPROC2_DBG1 0x17a8
#define MT6359_BUCK_VPROC2_ELR0 0x17b2
#define MT6359_BUCK_VS1_CON0 0x1808
#define MT6359_BUCK_VS1_DBG1 0x1828
#define MT6359_BUCK_VS1_ELR0 0x1834
#define MT6359_BUCK_VS2_CON0 0x1888
#define MT6359_BUCK_VS2_DBG1 0x18a8
#define MT6359_BUCK_VS2_ELR0 0x18b4
#define MT6359_BUCK_VPA_CON0 0x1908
#define MT6359_BUCK_VPA_CON1 0x190e
#define MT6359_BUCK_VPA_DBG1 0x1916
#define MT6359_VGPUVCORE_ANA_CON2 0x198e
#define MT6359_VGPUVCORE_ANA_CON13 0x19a4
#define MT6359_VPROC1_ANA_CON3 0x19b2
#define MT6359_VPROC2_ANA_CON3 0x1a0e
#define MT6359_VMODEM_ANA_CON3 0x1a1a
#define MT6359_VPU_ANA_CON3 0x1a26
#define MT6359_VS1_ANA_CON0 0x1a2c
#define MT6359_VS2_ANA_CON0 0x1a34
#define MT6359_VPA_ANA_CON0 0x1a3c
#define MT6359_RG_BUCK_VPU_EN_ADDR MT6359_BUCK_VPU_CON0
#define MT6359_RG_BUCK_VPU_LP_ADDR MT6359_BUCK_VPU_CON0
#define MT6359_RG_BUCK_VPU_LP_SHIFT 1
#define MT6359_DA_VPU_EN_ADDR MT6359_BUCK_VPU_DBG1
#define MT6359_RG_BUCK_VPU_VOSEL_ADDR MT6359_BUCK_VPU_ELR0
#define MT6359_RG_BUCK_VPU_VOSEL_MASK 0x7F
#define MT6359_RG_BUCK_VPU_VOSEL_SHIFT 0
#define MT6359_RG_BUCK_VCORE_EN_ADDR MT6359_BUCK_VCORE_CON0
#define MT6359_RG_BUCK_VCORE_LP_ADDR MT6359_BUCK_VCORE_CON0
#define MT6359_RG_BUCK_VCORE_LP_SHIFT 1
#define MT6359_DA_VCORE_EN_ADDR MT6359_BUCK_VCORE_DBG1
#define MT6359_RG_BUCK_VCORE_VOSEL_MASK 0x7F
#define MT6359_RG_BUCK_VCORE_VOSEL_SHIFT 0
#define MT6359_RG_BUCK_VGPU11_EN_ADDR MT6359_BUCK_VGPU11_CON0
#define MT6359_RG_BUCK_VGPU11_LP_ADDR MT6359_BUCK_VGPU11_CON0
#define MT6359_RG_BUCK_VGPU11_LP_SHIFT 1
#define MT6359_DA_VGPU11_EN_ADDR MT6359_BUCK_VGPU11_DBG1
#define MT6359_RG_BUCK_VGPU11_VOSEL_MASK 0x7F
#define MT6359_RG_BUCK_VGPU11_VOSEL_SHIFT 0
#define MT6359_RG_BUCK_VMODEM_EN_ADDR MT6359_BUCK_VMODEM_CON0
#define MT6359_RG_BUCK_VMODEM_LP_ADDR MT6359_BUCK_VMODEM_CON0
#define MT6359_RG_BUCK_VMODEM_LP_SHIFT 1
#define MT6359_DA_VMODEM_EN_ADDR MT6359_BUCK_VMODEM_DBG1
#define MT6359_RG_BUCK_VMODEM_VOSEL_ADDR MT6359_BUCK_VMODEM_ELR0
#define MT6359_RG_BUCK_VMODEM_VOSEL_MASK 0x7F
#define MT6359_RG_BUCK_VMODEM_VOSEL_SHIFT 0
#define MT6359_RG_BUCK_VPROC1_EN_ADDR MT6359_BUCK_VPROC1_CON0
#define MT6359_RG_BUCK_VPROC1_LP_ADDR MT6359_BUCK_VPROC1_CON0
#define MT6359_RG_BUCK_VPROC1_LP_SHIFT 1
#define MT6359_DA_VPROC1_EN_ADDR MT6359_BUCK_VPROC1_DBG1
#define MT6359_RG_BUCK_VPROC1_VOSEL_ADDR MT6359_BUCK_VPROC1_ELR0
#define MT6359_RG_BUCK_VPROC1_VOSEL_MASK 0x7F
#define MT6359_RG_BUCK_VPROC1_VOSEL_SHIFT 0
#define MT6359_RG_BUCK_VPROC2_EN_ADDR MT6359_BUCK_VPROC2_CON0
#define MT6359_RG_BUCK_VPROC2_LP_ADDR MT6359_BUCK_VPROC2_CON0
#define MT6359_RG_BUCK_VPROC2_LP_SHIFT 1
#define MT6359_DA_VPROC2_EN_ADDR MT6359_BUCK_VPROC2_DBG1
#define MT6359_RG_BUCK_VPROC2_VOSEL_ADDR MT6359_BUCK_VPROC2_ELR0
#define MT6359_RG_BUCK_VPROC2_VOSEL_MASK 0x7F
#define MT6359_RG_BUCK_VPROC2_VOSEL_SHIFT 0
#define MT6359_RG_BUCK_VS1_EN_ADDR MT6359_BUCK_VS1_CON0
#define MT6359_RG_BUCK_VS1_LP_ADDR MT6359_BUCK_VS1_CON0
#define MT6359_RG_BUCK_VS1_LP_SHIFT 1
#define MT6359_DA_VS1_EN_ADDR MT6359_BUCK_VS1_DBG1
#define MT6359_RG_BUCK_VS1_VOSEL_ADDR MT6359_BUCK_VS1_ELR0
#define MT6359_RG_BUCK_VS1_VOSEL_MASK 0x7F
#define MT6359_RG_BUCK_VS1_VOSEL_SHIFT 0
#define MT6359_RG_BUCK_VS2_EN_ADDR MT6359_BUCK_VS2_CON0
#define MT6359_RG_BUCK_VS2_LP_ADDR MT6359_BUCK_VS2_CON0
#define MT6359_RG_BUCK_VS2_LP_SHIFT 1
#define MT6359_DA_VS2_EN_ADDR MT6359_BUCK_VS2_DBG1
#define MT6359_RG_BUCK_VS2_VOSEL_ADDR MT6359_BUCK_VS2_ELR0
#define MT6359_RG_BUCK_VS2_VOSEL_MASK 0x7F
#define MT6359_RG_BUCK_VS2_VOSEL_SHIFT 0
#define MT6359_RG_BUCK_VPA_EN_ADDR MT6359_BUCK_VPA_CON0
#define MT6359_RG_BUCK_VPA_LP_ADDR MT6359_BUCK_VPA_CON0
#define MT6359_RG_BUCK_VPA_LP_SHIFT 1
#define MT6359_RG_BUCK_VPA_VOSEL_ADDR MT6359_BUCK_VPA_CON1
#define MT6359_RG_BUCK_VPA_VOSEL_MASK 0x3F
#define MT6359_RG_BUCK_VPA_VOSEL_SHIFT 0
#define MT6359_DA_VPA_EN_ADDR MT6359_BUCK_VPA_DBG1
#define MT6359_RG_VGPU11_FCCM_ADDR MT6359_VGPUVCORE_ANA_CON2
#define MT6359_RG_VGPU11_FCCM_SHIFT 9
#define MT6359_RG_VCORE_FCCM_ADDR MT6359_VGPUVCORE_ANA_CON13
#define MT6359_RG_VCORE_FCCM_SHIFT 5
#define MT6359_RG_VPROC1_FCCM_ADDR MT6359_VPROC1_ANA_CON3
#define MT6359_RG_VPROC1_FCCM_SHIFT 1
#define MT6359_RG_VPROC2_FCCM_ADDR MT6359_VPROC2_ANA_CON3
#define MT6359_RG_VPROC2_FCCM_SHIFT 1
#define MT6359_RG_VMODEM_FCCM_ADDR MT6359_VMODEM_ANA_CON3
#define MT6359_RG_VMODEM_FCCM_SHIFT 1
#define MT6359_RG_VPU_FCCM_ADDR MT6359_VPU_ANA_CON3
#define MT6359_RG_VPU_FCCM_SHIFT 1
#define MT6359_RG_VS1_FPWM_ADDR MT6359_VS1_ANA_CON0
#define MT6359_RG_VS1_FPWM_SHIFT 3
#define MT6359_RG_VS2_FPWM_ADDR MT6359_VS2_ANA_CON0
#define MT6359_RG_VS2_FPWM_SHIFT 3
#define MT6359_RG_VPA_MODESET_ADDR MT6359_VPA_ANA_CON0
#define MT6359_RG_VPA_MODESET_SHIFT 1
#define MT6359_RG_LDO_VSRAM_PROC1_VOSEL_MASK 0x7F
#define MT6359_RG_LDO_VSRAM_PROC1_VOSEL_SHIFT 0
#define MT6359_RG_LDO_VSRAM_PROC2_VOSEL_MASK 0x7F
#define MT6359_RG_LDO_VSRAM_PROC2_VOSEL_SHIFT 0
#define MT6359_RG_LDO_VSRAM_OTHERS_VOSEL_MASK 0x7F
#define MT6359_RG_LDO_VSRAM_OTHERS_VOSEL_SHIFT 0
#define MT6359_RG_LDO_VSRAM_MD_VOSEL_MASK 0x7F
#define MT6359_RG_LDO_VSRAM_MD_VOSEL_SHIFT 0
#define MT6359_RG_LDO_VCN33_1_EN_0_SHIFT 0
#define MT6359_RG_LDO_VCN33_2_EN_1_SHIFT 15
#define MT6359_RG_LDO_VSRAM_OTHERS_SSHUB_VOSEL_MASK 0x7F
#define MT6359_RG_LDO_VSRAM_OTHERS_SSHUB_VOSEL_SHIFT 1
#define MT6359_RG_VCN33_1_VOSEL_MASK 0xF
#define MT6359_RG_VCN33_1_VOSEL_SHIFT 8
#define MT6359_RG_VCN33_2_VOSEL_MASK 0xF
#define MT6359_RG_VCN33_2_VOSEL_SHIFT 8
#define MT6359_RG_VSIM1_VOSEL_MASK 0xF
#define MT6359_RG_VSIM1_VOSEL_SHIFT 8
#define MT6359_RG_VSIM2_VOSEL_MASK 0xF
#define MT6359_RG_VSIM2_VOSEL_SHIFT 8
#define MT6359_RG_VIO28_VOSEL_MASK 0xF
#define MT6359_RG_VIO28_VOSEL_SHIFT 8
#define MT6359_RG_VIBR_VOSEL_MASK 0xF
#define MT6359_RG_VIBR_VOSEL_SHIFT 8
#define MT6359_RG_VRF18_VOSEL_MASK 0xF
#define MT6359_RG_VRF18_VOSEL_SHIFT 8
#define MT6359_RG_VEFUSE_VOSEL_MASK 0xF
#define MT6359_RG_VEFUSE_VOSEL_SHIFT 8
#define MT6359_RG_VCAMIO_VOSEL_MASK 0xF
#define MT6359_RG_VCAMIO_VOSEL_SHIFT 8
#define MT6359_RG_VIO18_VOSEL_MASK 0xF
#define MT6359_RG_VIO18_VOSEL_SHIFT 8
#define MT6359_RG_VM18_VOSEL_MASK 0xF
#define MT6359_RG_VM18_VOSEL_SHIFT 8
#define MT6359_RG_VUFS_VOSEL_MASK 0xF
#define MT6359_RG_VUFS_VOSEL_SHIFT 8
#define MT6359_RG_VRF12_VOSEL_MASK 0xF
#define MT6359_RG_VRF12_VOSEL_SHIFT 8
#define MT6359_RG_VCN13_VOSEL_MASK 0xF
#define MT6359_RG_VCN13_VOSEL_SHIFT 8
#define MT6359_RG_VA09_VOSEL_MASK 0xF
#define MT6359_RG_VA09_VOSEL_SHIFT 8
#define MT6359_RG_VA12_VOSEL_MASK 0xF
#define MT6359_RG_VA12_VOSEL_SHIFT 8
#define MT6359_RG_VXO22_VOSEL_MASK 0xF
#define MT6359_RG_VXO22_VOSEL_SHIFT 8
#define MT6359_RG_VRFCK_VOSEL_MASK 0xF
#define MT6359_RG_VRFCK_VOSEL_SHIFT 8
#endif
|
