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| author | Michael Gielda <mgielda@antmicro.com> | 2014-04-03 15:11:19 +0200 |
|---|---|---|
| committer | Michael Gielda <mgielda@antmicro.com> | 2014-04-03 15:11:19 +0200 |
| commit | a1ec8a1ed46349b7b98c17f3121a47c7a9a033a4 (patch) | |
| tree | fa72e5b1c6f3a4922293e78f86dd9e31d9fc8a8b | |
| parent | ae1e4e08a1005a0c487f03ba189d7536e7fdcba6 (diff) | |
Update introduction.rst
| -rw-r--r-- | doc/source/introduction.rst | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/doc/source/introduction.rst b/doc/source/introduction.rst index 9f77fa1..741f7de 100644 --- a/doc/source/introduction.rst +++ b/doc/source/introduction.rst @@ -220,7 +220,7 @@ Vybrid has three available memory regions: .. note:: - Out of the 16MB of the DRAM memory in the CPU, 6MB was reserved for enabling the passing of large data blocks between Cortex-A and Cortex-M. This setting can be changed in the ``ecos/packages/hal/ cortexm/vybrid/col_vf61/current/include/pkgconf`` file by modifying the ``DRAM LENGTH`` and ``hal_startup_stack`` values (currently ``0x9FFFF0``). + Out of the 16MB of the DRAM memory in the CPU, 6MB was reserved for enabling the passing of large data blocks between Cortex-A and Cortex-M. This setting can be changed in the ``ecos/packages/hal/cortexm/vybrid/col_vf61/current/include/pkgconf/mlt_vybrid_ext_dram.ldi`` file by modifying the ``DRAM LENGTH`` and ``hal_startup_stack`` values (currently ``0x9FFFF0``). U-Boot over TFTP ---------------- |