Added the OS files

20 files changed, 3508 insertions, 0 deletions

diff --git a/ecos/packages/hal/cortexm/lpc17xx/lpc1766stk/current/ChangeLog b/ecos/packages/hal/cortexm/lpc17xx/lpc1766stk/current/ChangeLog
new file mode 100644
index 0000000..81d7195
--- /dev/null
+++ b/ecos/packages/hal/cortexm/lpc17xx/lpc1766stk/current/ChangeLog
@@ -0,0 +1,43 @@
+2012-01-16  Ilija Kocho  <ilijak@siva.com.mk>
+
+	* cdl/hal_cortexm_lpc17xx_lpc1766stk.cdl:
+	* include/pkgconf/mlt_cortexm_lpc1766_rom.h:
+	* include/pkgconf/mlt_cortexm_lpc1766_rom.ldi:
+	Recognize In Application Programming (IAP) SRAM field
+	and Valid User Code and Code Read Protection FLASH fields
+	Reported by Bernard Fouché [ Bugzilla 1001395 ] [Bugzilla 1001443 ]
+
+2010-12-12  Ilija Kocho  <ilijak@siva.com.mk>
+
+	* cdl/hal_cortexm_lpc17xx_lpc1766stk.cdl:
+	* include/pkgconf/mlt_cortexm_lpc1766_rom.h:
+	* include/pkgconf/mlt_cortexm_lpc1766_rom.ldi:
+	* include/plf_arch.h:
+	* include/plf_intr.h:
+	* include/plf_io.h:
+	* src/lpc1766stk_misc.c:
+	New package -- Olimex LPC1766STK board.
+
+//===========================================================================
+// ####GPLCOPYRIGHTBEGIN####                                                
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2010 Free Software Foundation, Inc.                        
+//
+// This program is free software; you can redistribute it and/or modify     
+// it under the terms of the GNU General Public License as published by     
+// the Free Software Foundation; either version 2 or (at your option) any   
+// later version.                                                           
+//
+// This program is distributed in the hope that it will be useful, but      
+// WITHOUT ANY WARRANTY; without even the implied warranty of               
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU        
+// General Public License for more details.                                 
+//
+// You should have received a copy of the GNU General Public License        
+// along with this program; if not, write to the                            
+// Free Software Foundation, Inc., 51 Franklin Street,                      
+// Fifth Floor, Boston, MA  02110-1301, USA.                                
+// -------------------------------------------                              
+// ####GPLCOPYRIGHTEND####                                                  
+//===========================================================================
diff --git a/ecos/packages/hal/cortexm/lpc17xx/lpc1766stk/current/cdl/hal_cortexm_lpc17xx_lpc1766stk.cdl b/ecos/packages/hal/cortexm/lpc17xx/lpc1766stk/current/cdl/hal_cortexm_lpc17xx_lpc1766stk.cdl
new file mode 100644
index 0000000..8ed6ac6
--- /dev/null
+++ b/ecos/packages/hal/cortexm/lpc17xx/lpc1766stk/current/cdl/hal_cortexm_lpc17xx_lpc1766stk.cdl
@@ -0,0 +1,416 @@
+##==========================================================================
+##
+##      hal_cortexm_lpc17xx_lpc1766stk.cdl
+##
+##      Cortex-M Olimex LPC-1766STK platform HAL configuration data
+##
+##==========================================================================
+## ####ECOSGPLCOPYRIGHTBEGIN####                                            
+## -------------------------------------------                              
+## This file is part of eCos, the Embedded Configurable Operating System.   
+## Copyright (C) 2010 Free Software Foundation, Inc.                        
+##
+## eCos is free software; you can redistribute it and/or modify it under    
+## the terms of the GNU General Public License as published by the Free     
+## Software Foundation; either version 2 or (at your option) any later      
+## version.                                                                 
+##
+## eCos is distributed in the hope that it will be useful, but WITHOUT      
+## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+## FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+## for more details.                                                        
+##
+## You should have received a copy of the GNU General Public License        
+## along with eCos; if not, write to the Free Software Foundation, Inc.,    
+## 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+##
+## As a special exception, if other files instantiate templates or use      
+## macros or inline functions from this file, or you compile this file      
+## and link it with other works to produce a work based on this file,       
+## this file does not by itself cause the resulting work to be covered by   
+## the GNU General Public License. However the source code for this file    
+## must still be made available in accordance with section (3) of the GNU   
+## General Public License v2.                                               
+##
+## This exception does not invalidate any other reasons why a work based    
+## on this file might be covered by the GNU General Public License.         
+## -------------------------------------------                              
+## ####ECOSGPLCOPYRIGHTEND####                                              
+##==========================================================================
+#######DESCRIPTIONBEGIN####
+##
+## Author(s):    ilijak
+## Date:         2010-12-05
+##
+######DESCRIPTIONEND####
+##
+##==========================================================================
+
+cdl_package CYGPKG_HAL_CORTEXM_LPC17XX_LPC1766STK {
+    display       "Olimex LPC-1700STK Board HAL"
+    parent        CYGPKG_HAL_CORTEXM_LPC17XX
+    define_header hal_cortexm_lpc17xx_lpc1766stk.h
+    include_dir   cyg/hal
+    hardware
+    requires      { CYGHWR_HAL_CORTEXM_SYSTICK_CLK_SOURCE == "INTERNAL" }
+    implements    CYGINT_IO_SERIAL_LPC24XX_UART0
+    implements    CYGINT_IO_SERIAL_LPC24XX_UART1
+
+    description   "
+        The Olimex LPC-1766STK HAL package provides the support needed
+        to run eCos on the LPC-1766STK board. Also this package can be
+        used for other boards that employ a controller from LPC 176x
+        or LPC 175x families. Use 'LPC17xx member in use' to pick up
+        your device."
+
+    compile       lpc1766stk_misc.c
+
+    requires      { is_active(CYGPKG_DEVS_ETH_PHY) implies
+                   (1 == CYGHWR_DEVS_ETH_PHY_KS8721) }
+    define_proc {
+        puts $::cdl_system_header "#define CYGBLD_HAL_TARGET_H   <pkgconf/hal_cortexm.h>"
+        puts $::cdl_system_header "#define CYGBLD_HAL_VARIANT_H  <pkgconf/hal_cortexm_lpc17xx.h>"
+        puts $::cdl_system_header "#define CYGBLD_HAL_PLATFORM_H <pkgconf/hal_cortexm_lpc17xx_lpc1766stk.h>"
+        puts $::cdl_header "#define HAL_PLATFORM_CPU    \"Cortex-M3\""
+        puts $::cdl_header "#define HAL_PLATFORM_BOARD  \"Olimex LPC-1766STK\""
+        puts $::cdl_header "#define HAL_PLATFORM_EXTRA  \"\""
+    }
+
+    cdl_component CYG_HAL_STARTUP {
+        display       "Startup type"
+        flavor        data
+        default_value { "ROM" }
+        legal_values  { "ROM" }
+        no_define
+        define -file system.h CYG_HAL_STARTUP
+        description   "
+            'ROM' startup builds a stand-alone application which will
+            be put into internal flash."
+    }
+
+    cdl_option CYGHWR_HAL_CORTEXM_LPC17XX_IAP {
+        display "Reserve RAM for IAP (Bytes)"
+        flavor data
+        legal_values { 0 32 }
+        default_value 32
+    }
+
+    cdl_component CYGHWR_MEMORY_LAYOUT {
+        display       "Memory layout"
+        flavor        data
+        no_define
+        calculated    { (CYG_HAL_STARTUP == "ROM" ) ? "cortexm_lpc" . CYGHWR_HAL_CORTEXM_LPC17XX  . "_rom" :
+                        "undefined" }
+        description   "
+            Combination of 'Startup type' and 'LPC17xx member in use'
+            produces the memory layout."
+
+        cdl_option CYGHWR_MEMORY_LAYOUT_LDI {
+            display       "Memory layout linker script fragment"
+            flavor        data
+            no_define
+            define -file system.h CYGHWR_MEMORY_LAYOUT_LDI
+            calculated   { "<pkgconf/mlt_" . CYGHWR_MEMORY_LAYOUT . ".ldi>" }
+        }
+
+        cdl_option CYGHWR_MEMORY_LAYOUT_H {
+            display       "Memory layout header file"
+            flavor        data
+            no_define
+            define -file system.h CYGHWR_MEMORY_LAYOUT_H
+            calculated    { "<pkgconf/mlt_" . CYGHWR_MEMORY_LAYOUT . ".h>" }
+        }
+
+    }
+
+    cdl_option CYGHWR_HAL_CORTEXM_LPC17XX_XTAL_FREQ {
+        display       "CPU xtal frequency"
+        parent        CYGHWR_HAL_CORTEXM_LPC17XX_CLOCKING
+        flavor        data
+        default_value { 12000000 }
+    }
+
+    cdl_option CYGHWR_HAL_CORTEXM_LPC17XX_MAX_CLOCK_SPEED {
+        display       "Max. CPU clock speed"
+        parent        CYGHWR_HAL_CORTEXM_LPC17XX_CLOCKING
+        flavor        data
+        calculated    { (CYGHWR_HAL_CORTEXM_LPC17XX == "1759") ||
+            (CYGHWR_HAL_CORTEXM_LPC17XX == "1769") ?  120000000 :
+            100000000 }
+        requires      { CYGHWR_HAL_CORTEXM_LPC17XX_CLOCK_SPEED <=
+            ((CYGHWR_HAL_CORTEXM_LPC17XX == "1759") ||
+             (CYGHWR_HAL_CORTEXM_LPC17XX == "1769") ?  120000000 :
+             100000000) }
+        description   "
+            Highest internal core frequency is dependent on selected
+            chip. "
+    }
+
+    # Both UARTs 0 and 1 are available for diagnostic/debug use.
+    implements CYGINT_HAL_LPC17XX_UART0
+    implements CYGINT_HAL_LPC17XX_UART1
+
+    implements      CYGINT_IO_SERIAL_FLOW_CONTROL_HW
+    implements      CYGINT_IO_SERIAL_LINE_STATUS_HW
+
+    cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS {
+        display       "Number of communication channels on the board"
+        flavor        data
+        calculated    2
+    }
+
+    cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL {
+        display       "Debug serial port"
+        active_if     CYGPRI_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_CONFIGURABLE
+        flavor        data
+        legal_values  0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
+        default_value 0
+        description   "
+            The Olimex LPC1766STK board has two serial ports. This
+            option chooses which port will be used to connect to a host
+            running GDB."
+    }
+
+    cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL {
+        display       "Diagnostic serial port"
+        active_if     CYGPRI_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_CONFIGURABLE
+        flavor        data
+        legal_values  0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
+        default_value 0
+        description   "
+            The Olimex LPC1766STK has two serial ports. This option
+            chooses which port will be used for diagnostic output."
+    }
+
+    cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD {
+        display       "Console serial port baud rate"
+        flavor        data
+        legal_values  9600 19200 38400 57600 115200
+        default_value 38400
+        description   "
+            This option controls the default baud rate used for the
+            console connection.
+            Note: this should match the value chosen for the GDB port
+            if the diagnostic and GDB port are the same."
+    }
+
+    cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_BAUD {
+        display       "GDB serial port baud rate"
+        flavor        data
+        legal_values  9600 19200 38400 57600 115200
+        default_value 38400
+        description   "
+            This option controls the default baud rate used for the
+            GDB connection.
+            Note: this should match the value chosen for the console
+            port if the console and GDB port are the same."
+    }
+
+    cdl_component CYGHWR_HAL_LPC_EMAC_RAM_AHB {
+        display       "Ethernet controller AHB SRAM"
+        flavor        none
+        active_if     CYGPKG_DEVS_ETH_ARM_LPC2XXX
+        parent        CYGPKG_DEVS_ETH_ARM_LPC2XXX
+        description   "
+            AHB SRAM allocated for Ethernet controller."
+
+        cdl_option CYGHWR_HAL_LPC_EMAC_MEM_SECTION {
+            display       "Memory section for lwIP buffers."
+            flavor        data
+            default_value { "\".ahb_sram0\"" }
+            legal_values  { "\".ahb_sram0\"" "\".ahb_sram1\"" }
+            description   "
+                Select special section for lwIP p-buffers and heap and
+                provide section name."
+        }
+
+        cdl_option CYGHWR_HAL_LPC_EMAC_BLOCK_SIZE {
+            display       "Block size"
+            flavor        data
+            default_value 0x600
+        }
+    }
+
+    cdl_option CYGDAT_LWIP_MEM_SECTION_NAME {
+        display       "Memory section for lwIP buffers."
+        flavor        data
+        default_value { "\".ahb_sram0\"" }
+        legal_values  { "\".ahb_sram0\"" "\".ahb_sram1\"" }
+        active_if     CYGPKG_NET_LWIP
+        parent        CYGOPT_LWIP_MEM_PLF_SPEC
+        description   "
+            Select special section for lwIP p-buffers and heap and
+            provide section name."
+    }
+
+    cdl_component CYGOPT_LWIP_PLF_MEM_OPT {
+        display       "Platform related lwIP memory constrains"
+        flavor        none
+        no_define
+        active_if     CYGPKG_NET_LWIP
+        parent        CYGOPT_LWIP_MEM_PLF_SPEC
+        description   "
+            Some platform constrains, features and restrictions applied
+            to lwIP network stack."
+
+        cdl_option CYGOPT_LWIP_PLF_MEM_LIMIT_SS0 {
+            display       "lwIP uses the same section as the ethernet controller"
+            no_define
+            flavor        bool
+            default_value is_active(CYGOPT_LWIP_PLF_MEM_LIMIT_SS0)
+
+            active_if     CYGSEM_LWIP_MEM_SECTION
+            active_if     { CYGDAT_LWIP_MEM_SECTION_NAME == CYGHWR_HAL_LPC_EMAC_MEM_SECTION }
+
+            requires      { CYGNUM_LWIP_MEM_SIZE == 1544 }
+            requires      { CYGNUM_LWIP_MEMP_NUM_PBUF ==  4 }
+            requires      { CYGNUM_LWIP_MEMP_NUM_TCP_PCB == 6 }
+            requires      { CYGNUM_LWIP_MEMP_NUM_TCP_PCB_LISTEN == 2 }
+            requires      { CYGNUM_LWIP_MEMP_NUM_ARP_QUEUE == 5 }
+            requires      { CYGNUM_LWIP_PBUF_POOL_SIZE == 8 }
+
+            requires      { CYGNUM_DEVS_ETH_ARM_LPC2XXX_RX_BUFS == 3 }
+        }
+
+        cdl_option CYGOPT_LWIP_PLF_MEM_LIMIT_SS1 {
+            display       "lwIP uses different section than the ethernet controller"
+            no_define
+            flavor        bool
+            default_value is_active(CYGOPT_LWIP_PLF_MEM_LIMIT_SS1)
+
+            active_if     CYGSEM_LWIP_MEM_SECTION
+            active_if     { CYGDAT_LWIP_MEM_SECTION_NAME != CYGHWR_HAL_LPC_EMAC_MEM_SECTION }
+
+            requires      { CYGNUM_LWIP_MEM_SIZE == 1600 }
+            requires      { CYGNUM_LWIP_MEMP_NUM_PBUF ==  9 }
+            requires      { CYGNUM_LWIP_MEMP_NUM_TCP_PCB == 8 }
+            requires      { CYGNUM_LWIP_MEMP_NUM_TCP_PCB_LISTEN == 4 }
+            requires      { CYGNUM_LWIP_MEMP_NUM_ARP_QUEUE == 10 }
+            requires      { CYGNUM_LWIP_PBUF_POOL_SIZE == 13 }
+
+            requires      { CYGNUM_DEVS_ETH_ARM_LPC2XXX_RX_BUFS == 4 }
+        }
+
+        cdl_option CYGOPT_LWIP_PLF_MEM_LIMIT_NSS {
+            display       "lwIP does not use a special section"
+            no_define
+            flavor        bool
+            default_value is_active(CYGOPT_LWIP_PLF_MEM_LIMIT_NSS)
+
+            active_if     !CYGSEM_LWIP_MEM_SECTION
+
+            requires      { CYGNUM_KERNEL_THREADS_IDLE_STACK_SIZE == 1024 }
+
+            requires      { CYGNUM_LWIP_MEM_SIZE == 884 }
+            requires      { CYGNUM_LWIP_MEMP_NUM_PBUF ==  4 }
+            requires      { CYGNUM_LWIP_MEMP_NUM_TCP_PCB == 5 }
+            requires      { CYGNUM_LWIP_MEMP_NUM_TCP_PCB_LISTEN == 2 }
+            requires      { CYGNUM_LWIP_MEMP_NUM_ARP_QUEUE == 5 }
+            requires      { CYGNUM_LWIP_PBUF_POOL_SIZE == 7 }
+
+            requires { CYGNUM_DEVS_ETH_ARM_LPC2XXX_RX_BUFS == 4 }
+        }
+    }
+
+    cdl_component CYGBLD_GLOBAL_OPTIONS {
+        display       "Global build options"
+        flavor        none
+        parent        CYGPKG_NONE
+        description   "
+            Global build options including control over compiler flags,
+            linker flags and choice of toolchain."
+
+        cdl_option CYGBLD_GLOBAL_COMMAND_PREFIX {
+            display       "Global command prefix"
+            flavor        data
+            no_define
+            default_value { "arm-eabi" }
+            description   "
+                This option specifies the command prefix used when
+                invoking the build tools."
+        }
+
+        cdl_option CYGBLD_GLOBAL_CFLAGS {
+            display       "Global compiler flags"
+            flavor        data
+            no_define
+            default_value { CYGBLD_GLOBAL_WARNFLAGS . "-mcpu=cortex-m3 -mthumb -g -O2 -ffunction-sections -fdata-sections -fno-rtti -fno-exceptions" }
+            description   "
+                This option controls the global compiler flags which
+                are used to compile all packages by default. Individual
+                packages may define options which override these global
+                flags."
+        }
+
+        cdl_option CYGBLD_GLOBAL_LDFLAGS {
+            display       "Global linker flags"
+            flavor        data
+            no_define
+            default_value { "-mcpu=cortex-m3 -mthumb -Wl,--gc-sections -Wl,-static -Wl,-n -g -nostdlib" }
+            description   "
+                This option controls the global linker flags. Individual
+                packages may define options which override these global
+                flags."
+        }
+    }
+
+    cdl_option CYGSEM_HAL_ROM_MONITOR {
+        display       "Behave as a ROM monitor"
+        flavor        bool
+        default_value 0
+        parent        CYGPKG_HAL_ROM_MONITOR
+        requires      { CYG_HAL_STARTUP == "ROM" || CYG_HAL_STARTUP == "JTAG" }
+        requires      { CYGDBG_HAL_CRCTABLE_LOCATION == "ROM" }
+        description   "
+            Enable this option if this program is to be used as a
+            ROM monitor, i.e. applications will be loaded into RAM on
+            the board, and this ROM monitor may process exceptions or
+            interrupts generated from the application. This enables
+            features such as utilizing a separate interrupt stack when
+            exceptions are generated."
+    }
+
+    cdl_option CYGSEM_HAL_USE_ROM_MONITOR {
+        display       "Work with a ROM monitor"
+        flavor        booldata
+        legal_values  { "Generic" "GDB_stubs" }
+        default_value { CYG_HAL_STARTUP == "RAM" ? "GDB_stubs" : 0 }
+        parent        CYGPKG_HAL_ROM_MONITOR
+        requires      { CYG_HAL_STARTUP == "RAM" }
+        description   "
+            Support can be enabled for different varieties of ROM monitor.
+            This support changes various eCos semantics such as the
+            encoding of diagnostic output, or the overriding of hardware
+            interrupt vectors.
+            Firstly there is \"Generic\" support which prevents the HAL
+            from overriding the hardware vectors that it does not use, to
+            instead allow an installed ROM monitor to handle them. This
+            is the most basic support which is likely to be common to
+            most implementations of ROM monitor.
+            \"GDB_stubs\" provides support when GDB stubs are included
+            in the ROM monitor or boot ROM."
+    }
+
+    cdl_component CYGBLD_HAL_CORTEXM_LPC1766STK_GDB_STUBS {
+        display "Create StubROM SREC and binary files"
+        no_define
+        calculated    1
+        active_if     CYGBLD_BUILD_COMMON_GDB_STUBS
+        requires      { CYG_HAL_STARTUP == "ROM" }
+
+        make -priority 325 {
+            <PREFIX>/bin/stubrom.srec : <PREFIX>/bin/gdb_module.img
+            $(OBJCOPY) -O srec $< $@
+        }
+        make -priority 325 {
+            <PREFIX>/bin/stubrom.bin : <PREFIX>/bin/gdb_module.img
+            $(OBJCOPY) -O binary $< $@
+        }
+
+        description   "
+            This component causes the ELF image generated by the build
+            process to be converted to S-Record and binary files."
+    }
+}
+
+# EOF hal_cortexm_lpc17xx_lpc1766stk.cdl
diff --git a/ecos/packages/hal/cortexm/lpc17xx/lpc1766stk/current/include/pkgconf/mlt_cortexm_lpc1766_rom.h b/ecos/packages/hal/cortexm/lpc17xx/lpc1766stk/current/include/pkgconf/mlt_cortexm_lpc1766_rom.h
new file mode 100644
index 0000000..37c509c
--- /dev/null
+++ b/ecos/packages/hal/cortexm/lpc17xx/lpc1766stk/current/include/pkgconf/mlt_cortexm_lpc1766_rom.h
@@ -0,0 +1,30 @@
+// eCos memory layout
+
+#ifndef __ASSEMBLER__
+#include <cyg/infra/cyg_type.h>
+#include <stddef.h>
+
+#endif
+#define CYGMEM_REGION_ram (0x10000000)
+#define CYGMEM_REGION_ram_SIZE (0x00008000-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE-CYGHWR_HAL_CORTEXM_LPC17XX_IAP)
+#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+
+#define CYGMEM_REGION_ahb_sram_bank0 (0x2007C000)
+#define CYGMEM_REGION_ahb_sram_bank0_SIZE (0x00004000)
+#define CYGMEM_REGION_ahb_sram_bank0_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+
+#define CYGMEM_REGION_ahb_sram_bank1 (0x20080000)
+#define CYGMEM_REGION_ahb_sram_bank1_SIZE (0x00004000)
+#define CYGMEM_REGION_ahb_sram_bank1_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+
+#define CYGMEM_REGION_flash (0x00000000)
+#define CYGMEM_REGION_flash_SIZE (0x00040000)
+#define CYGMEM_REGION_flash_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+
+#ifndef __ASSEMBLER__
+extern char CYG_LABEL_NAME (__heap1) [];
+#endif
+#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1))
+#define CYGMEM_SECTION_heap1_SIZE (CYGMEM_REGION_ram+CYGMEM_REGION_ram_SIZE - (size_t) CYG_LABEL_NAME (__heap1))
+
+
diff --git a/ecos/packages/hal/cortexm/lpc17xx/lpc1766stk/current/include/pkgconf/mlt_cortexm_lpc1766_rom.ldi b/ecos/packages/hal/cortexm/lpc17xx/lpc1766stk/current/include/pkgconf/mlt_cortexm_lpc1766_rom.ldi
new file mode 100644
index 0000000..26c8376
--- /dev/null
+++ b/ecos/packages/hal/cortexm/lpc17xx/lpc1766stk/current/include/pkgconf/mlt_cortexm_lpc1766_rom.ldi
@@ -0,0 +1,49 @@
+// eCos memory layout
+
+#include <pkgconf/hal.h>
+#include <cyg/infra/cyg_type.inc>
+
+MEMORY
+{
+    ram  : ORIGIN = 0x10000000, LENGTH = 0x00008000-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE-CYGHWR_HAL_CORTEXM_LPC17XX_IAP
+    ahb_sram_bank0  : ORIGIN = 0x2007C000, LENGTH = 0x00004000
+    ahb_sram_bank1  : ORIGIN = 0x20080000, LENGTH = 0x00004000
+    flash : ORIGIN = 0x00000000, LENGTH = 0x00040000
+}
+
+SECTIONS
+{
+    SECTIONS_BEGIN
+    SECTION_rom_vectors (flash, 0x00000000, LMA_EQ_VMA)
+    USER_SECTION(lpc17xx_misc, flash, 0x00000020, LMA_EQ_VMA)
+    
+    // LPC17xx Code Read Protection field. Must be present at 0x000002FC
+    // Warning: Code Read Protection field or moving it to
+    //          other location may lock LPC17xx controller.
+    // See src/lpc17xx_mis.c for definition
+
+    .lpc17xxcrp 0x2FC : { KEEP (*(.lpc17xxcrp)) } > flash
+    
+    SECTION_RELOCS (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_text (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_fini (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_rodata (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_rodata1 (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_fixup (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_gcc_except_table (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_eh_frame (flash, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_got (flash, ALIGN (0x8), LMA_EQ_VMA)
+    USER_SECTION (ahb_sram0, ahb_sram_bank0, 0x2007C000 (NOLOAD), LMA_EQ_VMA)
+    USER_SECTION (ahb_sram1, ahb_sram_bank1, 0x20080000 (NOLOAD), LMA_EQ_VMA)
+    SECTION_data (ram, 0x10000400, FOLLOWING (.got))
+    SECTION_sram (ram, ALIGN (0x8), FOLLOWING (.data))
+    SECTION_bss (ram, ALIGN (0x8), LMA_EQ_VMA)
+    CYG_LABEL_DEFN(__heap1) = ALIGN (0x8);
+    SECTIONS_END
+}
+
+hal_vsr_table = 0x10000000;
+hal_virtual_vector_table = hal_vsr_table + 128*4;
+hal_startup_stack = 0x10000000 + 1024*32-CYGHWR_HAL_CORTEXM_LPC17XX_IAP;
+
+
diff --git a/ecos/packages/hal/cortexm/lpc17xx/lpc1766stk/current/include/plf_arch.h b/ecos/packages/hal/cortexm/lpc17xx/lpc1766stk/current/include/plf_arch.h
new file mode 100644
index 0000000..dc0c228
--- /dev/null
+++ b/ecos/packages/hal/cortexm/lpc17xx/lpc1766stk/current/include/plf_arch.h
@@ -0,0 +1,63 @@
+#ifndef CYGONCE_HAL_PLF_ARCH_H
+#define CYGONCE_HAL_PLF_ARCH_H
+//=============================================================================
+//
+//      plf_arch.h
+//
+//      Platform specific architecture overrides
+//
+//=============================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2010 Free Software Foundation, Inc.                        
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):   nickg
+// Contributor(s): ilijak
+// Date:        2010-12-29
+// Purpose:     LPC1766STK platform specific architecture overrides
+// Description: 
+// Usage:       #include <cyg/hal/plf_arch.h>
+//
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+#include <pkgconf/hal.h>
+#include <pkgconf/hal_cortexm_lpc17xx_lpc1766stk.h>
+
+
+//=============================================================================
+
+//-----------------------------------------------------------------------------
+#endif // CYGONCE_HAL_PLF_ARCH_H
+// End of plf_arch.h
diff --git a/ecos/packages/hal/cortexm/lpc17xx/lpc1766stk/current/include/plf_intr.h b/ecos/packages/hal/cortexm/lpc17xx/lpc1766stk/current/include/plf_intr.h
new file mode 100644
index 0000000..cbcc469
--- /dev/null
+++ b/ecos/packages/hal/cortexm/lpc17xx/lpc1766stk/current/include/plf_intr.h
@@ -0,0 +1,62 @@
+#ifndef CYGONCE_HAL_PLF_INTR_H
+#define CYGONCE_HAL_PLF_INTR_H
+//=============================================================================
+//
+//      plf_intr.h
+//
+//      Platform specific interrupt overrides
+//
+//=============================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2010 Free Software Foundation, Inc.                        
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):   nickg
+// Date:        2010-12-29
+// Purpose:     LPC1766STK platform specific interrupt overrides
+// Description: 
+// Usage:       #include <cyg/hal/plf_intr.h>
+//
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+#include <pkgconf/hal.h>
+#include <pkgconf/hal_cortexm_lpc17xx_lpc1766stk.h>
+
+
+//=============================================================================
+
+//-----------------------------------------------------------------------------
+#endif // CYGONCE_HAL_PLF_INTR_H
+// End of plf_intr.h
diff --git a/ecos/packages/hal/cortexm/lpc17xx/lpc1766stk/current/include/plf_io.h b/ecos/packages/hal/cortexm/lpc17xx/lpc1766stk/current/include/plf_io.h
new file mode 100644
index 0000000..a9f9794
--- /dev/null
+++ b/ecos/packages/hal/cortexm/lpc17xx/lpc1766stk/current/include/plf_io.h
@@ -0,0 +1,92 @@
+#ifndef CYGONCE_HAL_PLF_IO_H
+#define CYGONCE_HAL_PLF_IO_H
+//=============================================================================
+//
+//      plf_io.h
+//
+//      Platform specific registers
+//
+//=============================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2011 Free Software Foundation, Inc.                        
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):   ilijak
+// Date:        2011-01-02
+// Purpose:     LPC1766STK platform specific registers
+// Description: 
+// Usage:       #include <cyg/hal/plf_io.h>
+//
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+#include <pkgconf/hal.h>
+#include <pkgconf/hal_cortexm_lpc17xx_lpc1766stk.h>
+
+#if (CYGHWR_HAL_CORTEXM_LPC17XX_CLOCK_SPEED <= 20000000)
+#define CYGHWR_HAL_LPC17XX_REG_FLASHTIM CYGHWR_HAL_LPC17XX_REG_FLTSET(CYGHWR_HAL_LPC17XX_REG_FLTIM20MHZ)
+#elif (CYGHWR_HAL_CORTEXM_LPC17XX_CLOCK_SPEED <= 40000000)
+#define CYGHWR_HAL_LPC17XX_REG_FLASHTIM CYGHWR_HAL_LPC17XX_REG_FLTSET(CYGHWR_HAL_LPC17XX_REG_FLTIM40MHZ)
+#elif (CYGHWR_HAL_CORTEXM_LPC17XX_CLOCK_SPEED <= 60000000)
+#define CYGHWR_HAL_LPC17XX_REG_FLASHTIM CYGHWR_HAL_LPC17XX_REG_FLTSET(CYGHWR_HAL_LPC17XX_REG_FLTIM60MHZ)
+#elif (CYGHWR_HAL_CORTEXM_LPC17XX_CLOCK_SPEED <= 80000000)
+#define CYGHWR_HAL_LPC17XX_REG_FLASHTIM CYGHWR_HAL_LPC17XX_REG_FLTSET(CYGHWR_HAL_LPC17XX_REG_FLTIM80MHZ)
+#elif (CYGHWR_HAL_CORTEXM_LPC17XX_CLOCK_SPEED <= 100000000)
+#define CYGHWR_HAL_LPC17XX_REG_FLASHTIM CYGHWR_HAL_LPC17XX_REG_FLTSET(CYGHWR_HAL_LPC17XX_REG_FLTIM100MHZ)
+#elif (CYGHWR_HAL_CORTEXM_LPC17XX_CLOCK_SPEED <= 120000000)
+#define CYGHWR_HAL_LPC17XX_REG_FLASHTIM CYGHWR_HAL_LPC17XX_REG_FLTSET(CYGHWR_HAL_LPC17XX_REG_FLTIM120MHZ)
+#else
+#define CYGHWR_HAL_LPC17XX_REG_FLASHTIM CYGHWR_HAL_LPC17XX_REG_FLTSET(CYGHWR_HAL_LPC17XX_REG_FLTIMSAFE)
+#endif
+
+
+//=============================================================================
+// Memory access checks.
+//
+// Accesses to areas not backed by real devices or memory can cause
+// the CPU to hang. These macros allow the GDB stubs to avoid making
+// accidental accesses to these areas.
+
+__externC int cyg_hal_stub_permit_data_access( CYG_ADDRESS addr, cyg_uint32 count );
+
+#define CYG_HAL_STUB_PERMIT_DATA_READ(_addr_, _count_) cyg_hal_stub_permit_data_access( _addr_, _count_ )
+
+#define CYG_HAL_STUB_PERMIT_DATA_WRITE(_addr_, _count_ ) cyg_hal_stub_permit_data_access( _addr_, _count_ )
+
+//=============================================================================
+
+
+//-----------------------------------------------------------------------------
+#endif // CYGONCE_HAL_PLF_IO_H
+// End of plf_io.h
diff --git a/ecos/packages/hal/cortexm/lpc17xx/lpc1766stk/current/src/lpc1766stk_misc.c b/ecos/packages/hal/cortexm/lpc17xx/lpc1766stk/current/src/lpc1766stk_misc.c
new file mode 100644
index 0000000..1d8e105
--- /dev/null
+++ b/ecos/packages/hal/cortexm/lpc17xx/lpc1766stk/current/src/lpc1766stk_misc.c
@@ -0,0 +1,256 @@
+//==========================================================================
+//
+//      lpc1766stk_misc.c
+//
+//      Cortex-M3 LPC1766STK HAL functions
+//
+//==========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2008 Free Software Foundation, Inc.                        
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):      nickg
+// Contributor(s): ilijak
+// Date:           2010-12-22
+// Description:  
+//
+//####DESCRIPTIONEND####
+//
+//==========================================================================
+
+#include <pkgconf/hal.h>
+#include <pkgconf/hal_cortexm.h>
+#include <pkgconf/hal_cortexm_lpc17xx.h>
+#include <pkgconf/hal_cortexm_lpc17xx_lpc1766stk.h>
+#ifdef CYGPKG_KERNEL
+# include <pkgconf/kernel.h>
+#endif
+
+#include <cyg/infra/diag.h>
+#include <cyg/infra/cyg_type.h>
+#include <cyg/infra/cyg_trac.h>        // tracing macros
+#include <cyg/infra/cyg_ass.h>         // assertion macros
+
+#include <cyg/hal/hal_arch.h>          // HAL header
+#include <cyg/hal/hal_intr.h>          // HAL header
+static inline void hal_gpio_init(void);
+
+
+//==========================================================================
+// System init
+//
+// This is run to set up the basic system, including GPIO setting,
+// clock feeds, power supply, and memory initialization. This code
+// runs before the DATA is copied from ROM and the BSS cleared, hence
+// it cannot make use of static variables or data tables.
+
+__externC void
+hal_system_init(void)
+{
+#if defined(CYG_HAL_STARTUP_ROM) | defined(CYG_HAL_STARTUP_SRAM)
+    hal_gpio_init();
+#endif
+
+#if defined(CYG_HAL_STARTUP_ROM)
+    {
+        // Set flash accelerator according to CPU clock speed.
+        cyg_uint32      regval;
+        HAL_READ_UINT32(CYGHWR_HAL_LPC17XX_REG_SCB_BASE +
+                        CYGHWR_HAL_LPC17XX_REG_FLASHCFG, regval);
+        regval &= ~CYGHWR_HAL_LPC17XX_REG_FLTIM_MASK;
+        regval |= CYGHWR_HAL_LPC17XX_REG_FLASHTIM;
+        HAL_WRITE_UINT32(CYGHWR_HAL_LPC17XX_REG_SCB_BASE +
+                         CYGHWR_HAL_LPC17XX_REG_FLASHCFG, regval);
+    }
+#endif
+}
+
+
+//===========================================================================
+// hal_gpio_init
+//===========================================================================
+static inline void
+hal_gpio_init(void)
+{
+    // Enable UART0 and UART1 (has wired flow control and line status lines)
+    CYGHWR_HAL_LPC17XX_PIN_SET(CYGHWR_HAL_LPC17XX_REG_PINSEL0,
+                               (1 /* TXD0 */  << 4) |
+                               (1 /* RXD0 */  << 6) |
+                               (1 /* TXD1 */  << 30)
+        );
+    CYGHWR_HAL_LPC17XX_PIN_SET(CYGHWR_HAL_LPC17XX_REG_PINSEL1,
+                               (1 /* RXD1 */  << 0) |
+                               (1 /* CTS1 */  << 2) |
+                               (1 /* DCD1 */  << 4) |
+                               (1 /* DSR1 */  << 6) |
+                               (1 /* DTR1 */  << 8) |
+                               (1 /* RTS1 */  << 12)
+        );
+    CYGHWR_HAL_LPC17XX_PIN_SET(CYGHWR_HAL_LPC17XX_REG_PINSEL2, 0);
+    CYGHWR_HAL_LPC17XX_PIN_SET(CYGHWR_HAL_LPC17XX_REG_PINSEL3, 0);
+    CYGHWR_HAL_LPC17XX_PIN_SET(CYGHWR_HAL_LPC17XX_REG_PINSEL4, 0);
+#if 0 // not used
+    CYGHWR_HAL_LPC17XX_PIN_SET(CYGHWR_HAL_LPC17XX_REG_PINSEL5, 0);
+    CYGHWR_HAL_LPC17XX_PIN_SET(CYGHWR_HAL_LPC17XX_REG_PINSEL6, 0);
+#endif
+    CYGHWR_HAL_LPC17XX_PIN_SET(CYGHWR_HAL_LPC17XX_REG_PINSEL7, 0);
+#if 0 // not used
+    CYGHWR_HAL_LPC17XX_PIN_SET(CYGHWR_HAL_LPC17XX_REG_PINSEL8, 0);
+#endif
+    CYGHWR_HAL_LPC17XX_PIN_SET(CYGHWR_HAL_LPC17XX_REG_PINSEL9, 0);
+    CYGHWR_HAL_LPC17XX_PIN_SET(CYGHWR_HAL_LPC17XX_REG_PINSEL10, 0);
+}
+
+
+//==========================================================================
+
+__externC void
+hal_platform_init(void)
+{
+}
+
+//==========================================================================
+
+#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+
+#include CYGHWR_MEMORY_LAYOUT_H
+
+//--------------------------------------------------------------------------
+// Accesses to areas not backed by real devices or memory can cause
+// the CPU to hang.
+//
+// The following table defines the memory areas that GDB is allowed to
+// touch. All others are disallowed.
+// This table needs to be kept up to date with the set of memory areas
+// that are available on the board.
+
+static struct {
+    CYG_ADDRESS     start;             // Region start address
+    CYG_ADDRESS     end;               // End address (last byte)
+} hal_data_access[] = {
+    {
+    // Main RAM (On-chip SRAM in code area)
+    CYGMEM_REGION_ram, CYGMEM_REGION_ram + CYGMEM_REGION_ram_SIZE - 1},
+#ifdef CYGMEM_REGION_ahb_sram_bank0
+    {
+    // On-chip AHB SRAM bank 0
+    CYGMEM_REGION_ahb_sram_bank0, CYGMEM_REGION_ahb_sram_bank0 + CYGMEM_REGION_ahb_sram_bank0_SIZE - 1},
+#endif
+#ifdef CYGMEM_REGION_ahb_sram_bank1
+    {
+    // On-chip AHB SRAM bank 1
+    CYGMEM_REGION_ahb_sram_bank1, CYGMEM_REGION_ahb_sram_bank1 + CYGMEM_REGION_ahb_sram_bank1_SIZE - 1},
+#endif
+#ifdef CYGMEM_REGION_flash
+    {
+    // On-chip flash
+    CYGMEM_REGION_flash, CYGMEM_REGION_flash + CYGMEM_REGION_flash_SIZE - 1},
+#endif
+#ifdef CYGMEM_REGION_rom
+    {
+    // External flash
+    CYGMEM_REGION_rom, CYGMEM_REGION_rom + CYGMEM_REGION_rom_SIZE - 1},
+#endif
+    {
+    0xE0000000, 0x00000000 - 1},       // Cortex-M peripherals
+    {
+    0x40000000, 0x60000000 - 1},       // Chip specific peripherals
+};
+
+__externC int
+cyg_hal_stub_permit_data_access(CYG_ADDRESS addr, cyg_uint32 count)
+{
+    int             i;
+
+    for (i = 0; i < sizeof(hal_data_access) / sizeof(hal_data_access[0]); i++) {
+        if ((addr >= hal_data_access[i].start) &&
+            (addr + count) <= hal_data_access[i].end)
+            return true;
+    }
+
+    return false;
+}
+
+#endif // CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+
+//==========================================================================
+
+#ifdef CYGPKG_REDBOOT
+#include <redboot.h>
+#include CYGHWR_MEMORY_LAYOUT_H
+
+//--------------------------------------------------------------------------
+// Memory layout
+//
+// We report the main (S)RAM and peripheral (AHB) SRAM banks.
+
+
+void
+cyg_plf_memory_segment(int seg, unsigned char **start, unsigned char **end)
+{
+    switch (seg) {
+    case 0:
+        *start = (unsigned char *)CYGMEM_REGION_ram;
+        *end = (unsigned char *)(CYGMEM_REGION_ram + CYGMEM_REGION_ram_SIZE);
+        break;
+#ifdef CYGMEM_REGION_ahb_sram_bank0
+    case 1:
+        *start = (unsigned char *)CYGMEM_REGION_ahb_sram_bank0;
+        *end =
+            (unsigned char *)(CYGMEM_REGION_ahb_sram_bank0 +
+                              CYGMEM_REGION_ahb_sram_bank0_SIZE);
+        break;
+#endif
+#ifdef CYGMEM_REGION_ahb_sram_bank1
+# ifndef CYGMEM_REGION_ahb_sram_bank0
+    case 1:
+# else
+    case 2:
+# endif
+        *start = (unsigned char *)CYGMEM_REGION_ahb_sram_bank1;
+        *end =
+            (unsigned char *)(CYGMEM_REGION_ahb_sram_bank1 +
+                              CYGMEM_REGION_ahb_sram_bank1_SIZE);
+        break;
+#endif
+    default:
+        *start = *end = NO_MEMORY;
+        break;
+    }
+}
+
+#endif // CYGPKG_REDBOOT
+
+
+//==========================================================================
+// EOF lpc1766stk_misc.c
diff --git a/ecos/packages/hal/cortexm/lpc17xx/var/current/ChangeLog b/ecos/packages/hal/cortexm/lpc17xx/var/current/ChangeLog
new file mode 100644
index 0000000..dd49607
--- /dev/null
+++ b/ecos/packages/hal/cortexm/lpc17xx/var/current/ChangeLog
@@ -0,0 +1,61 @@
+2012-01-24  Ilija Kocho  <ilijak@siva.com.mk>
+
+	* cdl/hal_cortexm_lpc17xx.cdl:
+	Fix interrupt minimal priority calculation. [ Bugzilla 1001432 ]
+
+2012-01-16  Ilija Kocho  <ilijak@siva.com.mk>
+
+	* cdl/hal_cortexm_lpc17xx.cdl:
+	* include/var_io.h:
+	* src/lpc17xx_misc.c:
+	Recognize Code Read Protection FLASH field
+	Reported by Bernard Fouché [Bugzilla 1001443 ]
+
+2011-05-13  John Dallaway  <john@dallaway.org.uk>
+
+	* include/var_intr.h: Fix I2C interrupt definitions issue reported
+	by Pavel Glinskii. Also fix CYGNUM_HAL_INTERRUPT_NVIC_MAX from Ilija
+	Kocho.
+
+2011-03-14  John Dallaway  <john@dallaway.org.uk>
+
+	* cdl/hal_cortexm_lpc17xx.cdl: Do not implement the
+	CYGINT_PROFILE_HAL_TIMER interface at present.
+
+2010-12-10  Ilija Kocho  <ilijak@siva.com.mk>
+
+	* cdl/hal_cortexm_lpc17xx.cdl:
+	* include/hal_cache.h:
+	* include/hal_diag.h:
+	* include/plf_stub.h:
+	* include/var_arch.h:
+	* include/variant.inc:
+	* include/var_intr.h:
+	* include/var_io.h:
+	* src/hal_diag.c:
+	* src/lpc17xx_misc.c:
+	New package -- NXP LPC17XX variant HAL.
+
+//===========================================================================
+// ####GPLCOPYRIGHTBEGIN####                                                
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2010, 2011 Free Software Foundation, Inc.                        
+//
+// This program is free software; you can redistribute it and/or modify     
+// it under the terms of the GNU General Public License as published by     
+// the Free Software Foundation; either version 2 or (at your option) any   
+// later version.                                                           
+//
+// This program is distributed in the hope that it will be useful, but      
+// WITHOUT ANY WARRANTY; without even the implied warranty of               
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU        
+// General Public License for more details.                                 
+//
+// You should have received a copy of the GNU General Public License        
+// along with this program; if not, write to the                            
+// Free Software Foundation, Inc., 51 Franklin Street,                      
+// Fifth Floor, Boston, MA  02110-1301, USA.                                
+// -------------------------------------------                              
+// ####GPLCOPYRIGHTEND####                                                  
+//===========================================================================
diff --git a/ecos/packages/hal/cortexm/lpc17xx/var/current/cdl/hal_cortexm_lpc17xx.cdl b/ecos/packages/hal/cortexm/lpc17xx/var/current/cdl/hal_cortexm_lpc17xx.cdl
new file mode 100644
index 0000000..5baeb43
--- /dev/null
+++ b/ecos/packages/hal/cortexm/lpc17xx/var/current/cdl/hal_cortexm_lpc17xx.cdl
@@ -0,0 +1,468 @@
+##==========================================================================
+##
+##      hal_cortexm_lpc17xx.cdl
+##
+##      Cortex-M LPC 1700 variant HAL configuration data
+##
+##==========================================================================
+## ####ECOSGPLCOPYRIGHTBEGIN####                                            
+## -------------------------------------------                              
+## This file is part of eCos, the Embedded Configurable Operating System.   
+## Copyright (C) 2010, 2011 Free Software Foundation, Inc.                        
+##
+## eCos is free software; you can redistribute it and/or modify it under    
+## the terms of the GNU General Public License as published by the Free     
+## Software Foundation; either version 2 or (at your option) any later      
+## version.                                                                 
+##
+## eCos is distributed in the hope that it will be useful, but WITHOUT      
+## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+## FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+## for more details.                                                        
+##
+## You should have received a copy of the GNU General Public License        
+## along with eCos; if not, write to the Free Software Foundation, Inc.,    
+## 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+##
+## As a special exception, if other files instantiate templates or use      
+## macros or inline functions from this file, or you compile this file      
+## and link it with other works to produce a work based on this file,       
+## this file does not by itself cause the resulting work to be covered by   
+## the GNU General Public License. However the source code for this file    
+## must still be made available in accordance with section (3) of the GNU   
+## General Public License v2.                                               
+##
+## This exception does not invalidate any other reasons why a work based    
+## on this file might be covered by the GNU General Public License.         
+## -------------------------------------------                              
+## ####ECOSGPLCOPYRIGHTEND####                                              
+##==========================================================================
+#######DESCRIPTIONBEGIN####
+##
+## Author(s):    ilijak
+## Date:         2010-12-05
+##
+######DESCRIPTIONEND####
+##
+##==========================================================================
+
+cdl_package CYGPKG_HAL_CORTEXM_LPC17XX {
+    display       "Cortex-M3 LPC 17XX Variant"
+    parent        CYGPKG_HAL_CORTEXM
+    hardware
+    include_dir   cyg/hal
+    define_header hal_cortexm_lpc17xx.h
+    description   "
+       This package provides generic support for the NXP Cortex-M based
+       LPC17xx microcontroller family.  It is also necessary to select
+       a variant and platform HAL package."
+
+    compile       hal_diag.c lpc17xx_misc.c
+
+    implements    CYGINT_HAL_DEBUG_GDB_STUBS
+    implements    CYGINT_HAL_DEBUG_GDB_STUBS_BREAK
+    implements    CYGINT_HAL_VIRTUAL_VECTOR_SUPPORT
+    implements    CYGINT_HAL_VIRTUAL_VECTOR_COMM_BAUD_SUPPORT
+
+    requires      { CYGHWR_HAL_CORTEXM == "M3" }
+
+    cdl_option CYGHWR_HAL_CORTEXM_LPC17XX {
+        display       "LPC17xx member in use"
+        flavor        data
+        default_value { "1766" }
+        legal_values  {
+            "1751" "1752"  "1754" "1756" "1758" "1759" "1763" "1764"
+            "1765" "1766" "1767" "1768" "1769" }
+        description   "
+            The LPC17xx has several variants, the main differences being
+            in the size of on-chip FLASH and SRAM and numbers of some
+            peripherals. This option allows the platform HAL to select
+            the specific microcontroller fitted."
+    }
+
+    cdl_option CYGNUM_HAL_CORTEXM_PRIORITY_LEVEL_BITS {
+        display       "CPU priority levels"
+        flavor        data
+        calculated    5
+        description   "
+            This option defines the number of bits used to encode the
+            exception priority levels that this variant of the Cortex-M
+            CPU implements."
+    }
+
+    cdl_option CYGNUM_HAL_IRQ_PRIORITY_MIN {
+        display       "minimal interrupt priority"
+        flavor        data
+        no_define
+        calculated      0xFFFF&\
+              ((((1<<CYGNUM_HAL_CORTEXM_PRIORITY_LEVEL_BITS)-1)-1)\
+               <<8-CYGNUM_HAL_CORTEXM_PRIORITY_LEVEL_BITS)
+    }
+
+    cdl_component CYGHWR_HAL_CORTEXM_LPC17XX_CLOCKING {
+        display       "Clocking"
+        flavor        none
+
+        cdl_component CYGHWR_HAL_CORTEXM_LPC17XX_MAIN_CLOCK {
+            display       "Main clock"
+            flavor        none
+
+            cdl_option CYGHWR_HAL_CORTEXM_LPC17XX_PLL0_MUL {
+                display       "PLL multiplier"
+                flavor        data
+                legal_values  6 to 32767
+                default_value { 12 }
+            }
+
+            cdl_option CYGHWR_HAL_CORTEXM_LPC17XX_PLL0_DIV {
+                display       "PLL divider"
+                flavor        data
+                legal_values  1 to 32
+                default_value { 1 }
+            }
+
+            cdl_option CYGHWR_HAL_CORTEXM_LPC17XX_PLL0_OUTPUT {
+                display       "PLL output (MHz)"
+                flavor        data
+                legal_values  275000000 to 550000000
+                calculated    { 2 * CYGHWR_HAL_CORTEXM_LPC17XX_PLL0_MUL *
+                    CYGHWR_HAL_CORTEXM_LPC17XX_XTAL_FREQ /
+                    CYGHWR_HAL_CORTEXM_LPC17XX_PLL0_DIV }
+                description   "
+                    Normally the PLL output must be in the range of
+                    275MHz to 550MHz."
+            }
+
+            cdl_component CYGHWR_HAL_CORTEXM_LPC17XX_CLOCK_SPEED {
+                display       "CPU clock speed"
+                flavor        data
+                calculated    { 2 * CYGHWR_HAL_CORTEXM_LPC17XX_PLL0_MUL *
+                    CYGHWR_HAL_CORTEXM_LPC17XX_XTAL_FREQ /
+                    CYGHWR_HAL_CORTEXM_LPC17XX_PLL0_DIV /
+                    CYGHWR_HAL_CORTEXM_LPC17XX_CPU_CLK_DIV }
+                description   "
+                    The core CPU clock speed is the PLL output divided
+                    by the CPU clock divider."
+
+                cdl_option CYGHWR_HAL_CORTEXM_LPC17XX_CPU_CLK_DIV {
+                    display       "CPU clock divider"
+                    flavor        data
+                    legal_values  2 to 256
+                    default_value { 3 }
+                    description   "
+                        The CPU clock divider controls the division of
+                        the PLL output before it is used by the CPU. When
+                        the PLL is bypassed, the division may be by
+                        1. When the PLL is running, the output must be
+                        divided in order to bring the CPU clock frequency
+                        (CCLK) within operating limits. An 8 bit divider
+                        allows a range of options, including slowing
+                        CPU operation to a low rate for temporary power
+                        savings without turning off the PLL."
+                }
+            }
+        }
+
+        cdl_component CYGHWR_HAL_CORTEXM_LPC17XX_USB_CLOCK {
+            display       "USB clock"
+            flavor        none
+
+            cdl_option CYGHWR_HAL_CORTEXM_LPC17XX_PLL1_MUL {
+                display       "PLL multiplier"
+                flavor        data
+                calculated    { 48000000 / CYGHWR_HAL_CORTEXM_LPC17XX_XTAL_FREQ }
+            }
+
+            cdl_option CYGHWR_HAL_CORTEXM_LPC17XX_PLL1_DIV {
+                display       "PLL divider"
+                flavor         data
+                legal_values  1 2 3 4
+                default_value { 2 }
+            }
+
+            cdl_option CYGHWR_HAL_CORTEXM_LPC17XX_PLL1_OUTPUT {
+                display       "PLL output (MHz)"
+                flavor        data
+                legal_values  156000000 to 320000000
+                calculated    { 2 * 48000000 *  CYGHWR_HAL_CORTEXM_LPC17XX_PLL1_DIV }
+                description   "
+                    Normally the PLL output must be in the range of
+                    156MHz to 320MHz."
+            }
+
+            cdl_option CYGHWR_HAL_CORTEXM_LPC17XX_USB_CLOCK_SPEED {
+                display       "USB clock speed"
+                flavor        data
+                calculated    { 2 * CYGHWR_HAL_CORTEXM_LPC17XX_PLL1_MUL *
+                    CYGHWR_HAL_CORTEXM_LPC17XX_XTAL_FREQ /
+                    CYGHWR_HAL_CORTEXM_LPC17XX_PLL1_DIV }
+                description   "
+                    The USB clock speed is the PLL1 output."
+            }
+        }
+
+        cdl_component CYGHWR_HAL_CORTEXM_LPC17XX_CLKOUT {
+            display       "Clock-out option"
+            flavor        bool
+            default_value 0
+
+            description   "
+                This option enables clock output and selects clock source
+                and divider."
+
+            cdl_option CYGHWR_HAL_CORTEXM_LPC17XX_CLKOUT_SET {
+                display       "Clock out register setting"
+                flavor        data
+                calculated { (CYGHWR_HAL_CORTEXM_LPC17XX_CLKOUT_SRC |
+                              ((CYGHWR_HAL_CORTEXM_LPC17XX_CLKOUT_DIV
+                               - (1 && CYGHWR_HAL_CORTEXM_LPC17XX_CLKOUT)) << 4) |
+                              (CYGHWR_HAL_CORTEXM_LPC17XX_CLKOUT ? 0x100 : 0x0 ))
+                }
+            }
+
+            cdl_option CYGHWR_HAL_CORTEXM_LPC17XX_CLKOUT_SEL {
+                display       "Clock-out source selector"
+                flavor        data
+                legal_values  { "CPU clock" "Main osc." "RC osc." "USB clock" "RTC osc." }
+                default_value { "CPU clock" }
+                description   "
+                    Select clock out source."
+            }
+
+            cdl_option CYGHWR_HAL_CORTEXM_LPC17XX_CLKOUT_SRC {
+                display       "Clock-out source"
+                flavor        data
+                legal_values  0 1 2 3 4
+                calculated    { CYGHWR_HAL_CORTEXM_LPC17XX_CLKOUT_SEL == "CPU clock" ? 0 :
+                    CYGHWR_HAL_CORTEXM_LPC17XX_CLKOUT_SEL == "Main osc." ? 1 :
+                    CYGHWR_HAL_CORTEXM_LPC17XX_CLKOUT_SEL == "RC osc."   ? 2 :
+                    CYGHWR_HAL_CORTEXM_LPC17XX_CLKOUT_SEL == "USB clock" ? 3 :
+                    CYGHWR_HAL_CORTEXM_LPC17XX_CLKOUT_SEL == "RTC osc."  ? 4 :
+                    0
+                }
+                description   "
+                    Clock-out source index."
+            }
+
+            cdl_option CYGHWR_HAL_CORTEXM_LPC17XX_CLKOUT_DIV {
+                display       "Clock-out divider"
+                flavor        data
+                legal_values  1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
+                default_value { 10 }
+            }
+        }
+
+        cdl_component CYGHWR_HAL_CORTEXM_LPC17XX_PER_CLK {
+            display       "Peripherial clocking"
+            flavor        none
+
+            cdl_option CYGHWR_HAL_LPC_RTC_32768HZ {
+                display      "RTC uses 32768 Hz clock"
+                flavor       bool
+                calculated   1
+                description  "
+                    This option has to be defined for LPC microcontrollers
+                    which RTC clock has no other clocking option than
+                    RTC 32768 Hz oscilator."
+            }
+
+            cdl_component CYGHWR_HAL_CORTEXM_LPC17XX_CAN_CLK {
+                display       "CAN clock speed"
+                flavor        data
+                calculated    { CYGHWR_HAL_CORTEXM_LPC17XX_CLOCK_SPEED /
+                    CYGHWR_HAL_CORTEXM_LPC17XX_CAN_CLK_DIV }
+                description   "
+                    The CAN clock speed is the CPU clock output divided
+                    by the CAN clock divider."
+
+                cdl_option CYGHWR_HAL_CORTEXM_LPC17XX_CAN_CLK_DIV {
+                    display       "CAN clock divider"
+                    flavor        data
+                    legal_values  { 1 2 4 6 }
+                    default_value { 2 }
+                    description   "
+                        This divider selects the peripheral clock for
+                        both CAN channels. The divider divides the CPU
+                        clock to get the clock for the CAN peripherals."
+                }
+            }
+
+            cdl_component CYGHWR_HAL_CORTEXM_LPC17XX_ADC_CLK {
+                display       "ADC clock speed"
+                flavor        data
+                calculated    { CYGHWR_HAL_CORTEXM_LPC17XX_CLOCK_SPEED /
+                    CYGHWR_HAL_CORTEXM_LPC17XX_ADC_CLK_DIV }
+                description   "
+                    The ADC clock speed is the CPU clock output divided
+                    by the ADC clock divider."
+
+                cdl_option CYGHWR_HAL_CORTEXM_LPC17XX_ADC_CLK_DIV {
+                    display       "ADC clock divider"
+                    flavor        data
+                    legal_values  { 1 2 4 8 }
+                    default_value { 2 }
+                    description   "
+                        This divider selects the peripheral clock for
+                        on-chip ADC. The ADC clock is the input clock
+                        of the ADC peripheral."
+                }
+            }
+
+            for { set ::channel 0 } { $::channel < 3 } { incr ::channel } {
+                cdl_component CYGHWR_HAL_CORTEXM_LPC17XX_I2C[set ::channel]_CLK {
+                    display       "I2C channel [set ::channel] clock speed"
+                    flavor        data
+                    calculated    CYGHWR_HAL_CORTEXM_LPC17XX_CLOCK_SPEED / \
+                          CYGHWR_HAL_CORTEXM_LPC17XX_I2C[set ::channel]_CLK_DIV
+                    description   "
+                        The I2C clock speed is the CPU clock output
+                        divided by the I2C clock divider."
+
+                    cdl_option CYGHWR_HAL_CORTEXM_LPC17XX_I2C[set ::channel]_CLK_DIV {
+                        display       "I2C channel [set ::channel] clock divider"
+                        flavor        data
+                        legal_values  { 1 2 4 8 }
+                        default_value { 2 }
+                        description   "
+                            This divider selects the peripheral clock
+                            for I2C channel [set ::channel]. The divider
+                            divides the CPU clock to get the clock for
+                            the I2C peripheral."
+                    }
+                }
+            }
+        }
+    }
+
+    cdl_option CYGNUM_HAL_KERNEL_COUNTERS_CLOCK_ISR_DEFAULT_PRIORITY {
+        display       "Clock interrupt ISR priority"
+        flavor        data
+        calculated    CYGNUM_HAL_IRQ_PRIORITY_MIN
+        description   "
+            Set clock ISR priority to lowest priority."
+    }
+
+    cdl_component CYGNUM_HAL_RTC_CONSTANTS {
+        display       "Real-time clock constants"
+        flavor        none
+        no_define
+
+        cdl_option CYGNUM_HAL_RTC_NUMERATOR {
+            display       "Real-time clock numerator"
+            flavor        data
+            default_value 1000000000
+        }
+
+        cdl_option CYGNUM_HAL_RTC_DENOMINATOR {
+            display       "Real-time clock denominator"
+            flavor        data
+            default_value 100
+        }
+
+        cdl_option CYGNUM_HAL_RTC_PERIOD {
+            display       "Real-time clock period"
+            flavor        data
+            default_value 1000000 / CYGNUM_HAL_RTC_DENOMINATOR
+            description   "
+                The period defined here is something of a fake, it is
+                expressed in terms of a notional 1MHz clock. The value
+                actually installed in the hardware is calculated from
+                the current settings of the clock generation hardware."
+        }
+    }
+
+    cdl_option CYGOPT_HAL_LPC17XX_MISC_FLASH_SECTION {
+        display "Utilize \".lpc17xx_misc\" section for HAL"
+        flavor bool
+        default_value { CYG_HAL_STARTUP == "ROM" }
+        active_if { CYG_HAL_STARTUP == "ROM" }
+        description "
+        Kinetis use FLASH location  0x2fc for FLASH Code Read Protection.
+        This leaves FLASH area below 0x2fc
+            out of standard linker sections. Special section
+            \".lpc17xx_misc\" provides linker access to this area.
+            Setting this option instructs linker to place some HAL
+            (variant/platform) \"misc.\" functions in this area."
+    }
+
+    cdl_interface CYGINT_HAL_LPC17XX_UART0 {
+        display      "Platform has UART0 serial port"
+        description  "
+            The platform has a socket on UART0."
+    }
+
+    cdl_interface CYGINT_HAL_LPC17XX_UART1 {
+        display       "Platform has UART1 serial port"
+        description   "
+            The platform has a socket on UART1."
+    }
+
+    cdl_interface CYGINT_HAL_LPC17XX_UART2 {
+        display       "Platform has UART2 serial port"
+        description   "
+            The platform has a socket on UART2."
+    }
+
+    cdl_interface CYGINT_HAL_LPC17XX_UART3 {
+        display       "Platform has UART3 serial port"
+        description   "
+            The platform has a socket on UART3."
+    }
+
+    cdl_option CYGHWR_HAL_CORTEXM_LPC17XX_ENET {
+        display       "LPC 17xx Ethernet check"
+        flavor        bool
+        no_define
+        parent        CYGPKG_DEVS_ETH_ARM_LPC2XXX
+        calculated    {
+            (CYGHWR_HAL_CORTEXM_LPC17XX == "1766") ||
+            (CYGHWR_HAL_CORTEXM_LPC17XX == "1758") ||
+            (CYGHWR_HAL_CORTEXM_LPC17XX == "1764") ||
+            (CYGHWR_HAL_CORTEXM_LPC17XX == "1767") ||
+            (CYGHWR_HAL_CORTEXM_LPC17XX == "1768") ||
+            (CYGHWR_HAL_CORTEXM_LPC17XX == "1769")
+        }
+        requires {
+            (CYGHWR_HAL_CORTEXM_LPC17XX == "1766") ||
+            (CYGHWR_HAL_CORTEXM_LPC17XX == "1758") ||
+            (CYGHWR_HAL_CORTEXM_LPC17XX == "1764") ||
+            (CYGHWR_HAL_CORTEXM_LPC17XX == "1767") ||
+            (CYGHWR_HAL_CORTEXM_LPC17XX == "1768") ||
+            (CYGHWR_HAL_CORTEXM_LPC17XX == "1769")
+        }
+        description   "
+            Check whether the chip has Ethernet controler."
+    }
+
+    cdl_component CYGPKG_HAL_CORTEXM_LPC17XX_OPTIONS {
+        display       "Build options"
+        flavor        none
+        description   "
+              Package specific build options including control over
+              compiler flags used only in building this package."
+
+        cdl_option CYGPKG_HAL_CORTEXM_LPC17XX_CFLAGS_ADD {
+            display       "Additional compiler flags"
+            flavor        data
+            no_define
+            default_value { "" }
+            description   "
+                This option modifies the set of compiler flags for
+                building the LPC17xx variant HAL package. These flags
+                are used in addition to the set of global flags."
+        }
+
+        cdl_option CYGPKG_HAL_CORTEXM_LPC17XX_CFLAGS_REMOVE {
+            display       "Suppressed compiler flags"
+            flavor        data
+            no_define
+            default_value { "" }
+            description   "
+                This option modifies the set of compiler flags for
+                building the LPC17xx variant HAL package. These flags
+                are removed from the set of global flags if present."
+        }
+    }
+}
+
+# EOF hal_cortexm_lpc17xx.cdl
diff --git a/ecos/packages/hal/cortexm/lpc17xx/var/current/include/hal_cache.h b/ecos/packages/hal/cortexm/lpc17xx/var/current/include/hal_cache.h
new file mode 100644
index 0000000..169f109
--- /dev/null
+++ b/ecos/packages/hal/cortexm/lpc17xx/var/current/include/hal_cache.h
@@ -0,0 +1,110 @@
+#ifndef CYGONCE_HAL_CACHE_H
+#define CYGONCE_HAL_CACHE_H
+
+//=============================================================================
+//
+//      hal_cache.h
+//
+//      HAL cache control API
+//
+//=============================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2004, 2005, 2006, 2008 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):    jlarmour
+// Contributors: 
+// Date:         2004-07-23
+// Purpose:      Cache control API
+// Description:  The NXP LPC17XX CPU family does not require cache control.
+//               File is kept empty.
+//
+// Usage:
+//               #include <cyg/hal/hal_cache.h>
+//               ...
+//
+//
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+#include <cyg/infra/cyg_type.h>
+
+//-----------------------------------------------------------------------------
+// Global control of data cache
+
+// Enable the data cache
+#define HAL_DCACHE_ENABLE()
+
+// Disable the data cache
+#define HAL_DCACHE_DISABLE()
+
+// Invalidate the entire cache
+#define HAL_DCACHE_INVALIDATE_ALL()
+
+// Synchronize the contents of the cache with memory.
+#define HAL_DCACHE_SYNC()
+
+// Purge contents of data cache
+#define HAL_DCACHE_PURGE_ALL()
+
+// Query the state of the data cache (does not affect the caching)
+#define HAL_DCACHE_IS_ENABLED(_state_)          \
+    CYG_MACRO_START                             \
+    (_state_) = 0;                              \
+    CYG_MACRO_END
+
+//-----------------------------------------------------------------------------
+// Global control of Instruction cache
+
+// Enable the instruction cache
+#define HAL_ICACHE_ENABLE()
+
+// Disable the instruction cache
+#define HAL_ICACHE_DISABLE()
+
+// Invalidate the entire cache
+#define HAL_ICACHE_INVALIDATE_ALL()
+
+// Synchronize the contents of the cache with memory.
+#define HAL_ICACHE_SYNC()
+
+// Query the state of the instruction cache (does not affect the caching)
+#define HAL_ICACHE_IS_ENABLED(_state_)          \
+    CYG_MACRO_START                             \
+    (_state_) = 0;                              \
+    CYG_MACRO_END
+
+//-----------------------------------------------------------------------------
+#endif // ifndef CYGONCE_HAL_CACHE_H
+// End of hal_cache.h
diff --git a/ecos/packages/hal/cortexm/lpc17xx/var/current/include/hal_diag.h b/ecos/packages/hal/cortexm/lpc17xx/var/current/include/hal_diag.h
new file mode 100644
index 0000000..7d409aa
--- /dev/null
+++ b/ecos/packages/hal/cortexm/lpc17xx/var/current/include/hal_diag.h
@@ -0,0 +1,89 @@
+#ifndef CYGONCE_HAL_DIAG_H
+#define CYGONCE_HAL_DIAG_H
+//=============================================================================
+//
+//      hal_diag.h
+//
+//      HAL diagnostics
+//
+//=============================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2008, 2011 Free Software Foundation, Inc.                  
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):      nickg
+// Contributor(s): ilijak
+// Date:           2008-07-30
+// Purpose:        HAL diagnostics
+// Description: 
+// Usage:          #include <cyg/hal/var_io.h>
+//
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+#include <pkgconf/hal.h>
+#include <cyg/infra/cyg_type.h>
+#include <cyg/hal/hal_if.h>
+
+//-----------------------------------------------------------------------------
+
+#if defined(CYGSEM_HAL_VIRTUAL_VECTOR_DIAG)
+
+# define HAL_DIAG_INIT()          hal_if_diag_init()
+# define HAL_DIAG_WRITE_CHAR(_c_) hal_if_diag_write_char(_c_)
+# define HAL_DIAG_READ_CHAR(_c_)  hal_if_diag_read_char(&_c_)
+
+#else
+
+__externC void  hal_plf_diag_init(void);
+__externC void  hal_plf_diag_putc(char);
+__externC cyg_uint8 hal_plf_diag_getc(void);
+
+# ifndef HAL_DIAG_INIT
+#  define HAL_DIAG_INIT() hal_plf_diag_init()
+# endif
+
+# ifndef HAL_DIAG_WRITE_CHAR
+#  define HAL_DIAG_WRITE_CHAR(__c) hal_plf_diag_putc(__c)
+# endif
+
+# ifndef HAL_DIAG_READ_CHAR
+#  define HAL_DIAG_READ_CHAR(__c) (__c) = hal_plf_diag_getc()
+# endif
+
+#endif // CYGSEM_HAL_VIRTUAL_VECTOR_DIAG
+
+//-----------------------------------------------------------------------------
+#endif // CYGONCE_HAL_DIAG_H
+// End of hal_diag.h
diff --git a/ecos/packages/hal/cortexm/lpc17xx/var/current/include/lpc17xx_misc.h b/ecos/packages/hal/cortexm/lpc17xx/var/current/include/lpc17xx_misc.h
new file mode 100644
index 0000000..56a624a
--- /dev/null
+++ b/ecos/packages/hal/cortexm/lpc17xx/var/current/include/lpc17xx_misc.h
@@ -0,0 +1,204 @@
+#ifndef CYGONCE_HAL_CORTEXM_LPC17XX_VAR_LPC17XX_MISC_H
+#define CYGONCE_HAL_CORTEXM_LPC17XX_VAR_LPC17XX_MISC_H
+//=============================================================================
+//
+//      lpc17xx_misc.h
+//
+//      HAL misc variant support code for NCP LPC17xx header file
+//
+//=============================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2010 Free Software Foundation, Inc.                        
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):    andyj 
+// Contributors: jani, ilijak
+// Date:         2010-12-29
+// Purpose:      LPC17XX specific miscellaneous support header file
+// Description: 
+// Usage:        #include <cyg/hal/lpc17xx_misc.h>
+//
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+//-----------------------------------------------------------------------------
+// Function to obtain the current processor clock settings
+// Use PCLK identifiers below
+//
+externC cyg_uint32 hal_lpc_get_pclk(cyg_uint32 pclk_id);
+#define CYG_HAL_CORTEXM_LPC17XX_PCLK(_pclkid_) hal_lpc_get_pclk(_pclkid_)
+
+//-----------------------------------------------------------------------------
+// Identifiers for peripheral clock. Use these identifiers with the function
+// hal_get_pclk()
+//
+#define CYNUM_HAL_LPC17XX_PCLK_WDT    0
+#define CYNUM_HAL_LPC17XX_PCLK_TIMER0 1
+#define CYNUM_HAL_LPC17XX_PCLK_TIMER1 2
+#define CYNUM_HAL_LPC17XX_PCLK_UART0  3
+#define CYNUM_HAL_LPC17XX_PCLK_UART1  4
+#if 0 // Not implemented on LPC17xx
+# define CYNUM_HAL_LPC17XX_PCLK_PWM0   5
+#endif
+#define CYNUM_HAL_LPC17XX_PCLK_PWM1   6
+#define CYNUM_HAL_LPC17XX_PCLK_I2C0   7
+#define CYNUM_HAL_LPC17XX_PCLK_SPI    8
+#if 0 // Not implemented on LPC17xx
+# define CYNUM_HAL_LPC17XX_PCLK_RTC    9
+#endif
+#define CYNUM_HAL_LPC17XX_PCLK_SSP1   10
+#define CYNUM_HAL_LPC17XX_PCLK_DAC    11
+#define CYNUM_HAL_LPC17XX_PCLK_ADC    12
+#define CYNUM_HAL_LPC17XX_PCLK_CAN1   13
+#define CYNUM_HAL_LPC17XX_PCLK_CAN2   14
+#define CYNUM_HAL_LPC17XX_PCLK_ACF    15
+#define CYNUM_HAL_LPC17XX_PCLK_QEI    16
+#define CYNUM_HAL_LPC17XX_PCLK_GPIO   17
+#define CYNUM_HAL_LPC17XX_PCLK_PCB    18
+#define CYNUM_HAL_LPC17XX_PCLK_I2C1   19
+#if 0 // Not implemented on LPC17xx
+# define CYNUM_HAL_LPC17XX_PCLK_SSP0   21
+#endif
+#define CYNUM_HAL_LPC17XX_PCLK_TIMER2 22
+#define CYNUM_HAL_LPC17XX_PCLK_TIMER3 23
+#define CYNUM_HAL_LPC17XX_PCLK_UART2  24
+#define CYNUM_HAL_LPC17XX_PCLK_UART3  25
+#define CYNUM_HAL_LPC17XX_PCLK_I2C2   26
+#define CYNUM_HAL_LPC17XX_PCLK_I2S    27
+#if 0 // Not implemented on LPC17xx
+# define CYNUM_HAL_LPC17XX_PCLK_MCI    28
+#endif
+#define CYNUM_HAL_LPC17XX_PCLK_RIT    29
+#define CYNUM_HAL_LPC17XX_PCLK_SYSCON 30
+#define CYNUM_HAL_LPC17XX_PCLK_MC     31
+
+
+//-----------------------------------------------------------------------------
+// Function to enable/disable power for certain peripheral
+// Use PCONP identifiers from below
+//
+externC void hal_lpc_set_power(cyg_uint8 pconp_id, int on);
+#define CYG_HAL_CORTEXM_LPC17XX_SET_POWER(_pconp_id_, _on_) \
+        hal_lpc_set_power((_pconp_id_), (_on_))
+
+
+//-----------------------------------------------------------------------------
+// Identifiers for power control, hal_get_pclk()
+//
+#define CYNUM_HAL_LPC17XX_PCONP_TIMER0 1
+#define CYNUM_HAL_LPC17XX_PCONP_TIMER1 2
+#define CYNUM_HAL_LPC17XX_PCONP_UART0  3
+#define CYNUM_HAL_LPC17XX_PCONP_UART1  4
+#if 0 // Not implemented on LPC17xx
+# define CYNUM_HAL_LPC17XX_PCONP_PWM0   5
+#endif
+#define CYNUM_HAL_LPC17XX_PCONP_PWM1   6
+#define CYNUM_HAL_LPC17XX_PCONP_I2C0   7
+#define CYNUM_HAL_LPC17XX_PCONP_SPI    8
+#define CYNUM_HAL_LPC17XX_PCONP_RTC    9
+#define CYNUM_HAL_LPC17XX_PCONP_SSP1   10
+#if 0 // Not implemented on LPC17xx
+# define CYNUM_HAL_LPC17XX_PCONP_EMC    11
+#endif
+#define CYNUM_HAL_LPC17XX_PCONP_ADC    12
+#define CYNUM_HAL_LPC17XX_PCONP_CAN1   13
+#define CYNUM_HAL_LPC17XX_PCONP_CAN2   14
+#define CYNUM_HAL_LPC17XX_PCONP_GPIO   15
+#define CYNUM_HAL_LPC17XX_PCONP_RIT    16
+#define CYNUM_HAL_LPC17XX_PCONP_MCPWM  17
+#define CYNUM_HAL_LPC17XX_PCONP_QEI    18
+#define CYNUM_HAL_LPC17XX_PCONP_I2C1   19
+#if 0 // Not implemented on LPC17xx
+# define CYNUM_HAL_LPC17XX_PCONP_LCD    20
+#endif
+#define CYNUM_HAL_LPC17XX_PCONP_SSP0   21
+#define CYNUM_HAL_LPC17XX_PCONP_TIMER2 22
+#define CYNUM_HAL_LPC17XX_PCONP_TIMER3 23
+#define CYNUM_HAL_LPC17XX_PCONP_UART2  24
+#define CYNUM_HAL_LPC17XX_PCONP_UART3  25
+#define CYNUM_HAL_LPC17XX_PCONP_I2C2   26
+#define CYNUM_HAL_LPC17XX_PCONP_I2S    27
+#if 0 // Not implemented on LPC17xx
+# define CYNUM_HAL_LPC17XX_PCONP_SDC    28
+#endif
+#define CYNUM_HAL_LPC17XX_PCONP_GPDMA  29
+#define CYNUM_HAL_LPC17XX_PCONP_ENET   30
+#define CYNUM_HAL_LPC17XX_PCONP_USB    31
+
+
+//-----------------------------------------------------------------------------
+// Configure pin function
+//
+externC void hal_lpc_set_pin_function(cyg_uint8 port, cyg_uint8 pin,
+                                  cyg_uint8 function);
+#define CYG_HAL_CORTEXM_LPC17XX_PIN_CFG(_port_, _pin_, _func_) \
+                hal_lpc_set_pin_function((_port_), (_pin_), (_func_))
+
+
+//-----------------------------------------------------------------------------
+// Macros to derive the baudrate divider values for the internal UARTs
+// The LPC17xx family supports different baudrate clocks for each single
+// UART. So we need a way to calculate the baudrate for each single UART
+// Now we rely on the fact that we use the same baudrate clock for all
+// UARTs and we query only UART0
+//-----------------------------------------------------------------------------
+
+#define CYG_HAL_CORTEXM_LPC17XX_BAUD_GENERATOR(_pclkid_, baud) \
+                (CYG_HAL_CORTEXM_LPC17XX_PCLK(_pclkid_)/((baud)*16))
+
+//-----------------------------------------------------------------------------
+// LPC17XX platform reset (watchdog resets the board)
+//-----------------------------------------------------------------------------
+#if 0
+externC void hal_lpc_watchdog_reset(void);
+
+#define HAL_PLATFORM_RESET() hal_lpc_watchdog_reset()
+#define HAL_PLATFORM_RESET_ENTRY 0
+#endif
+
+
+//-----------------------------------------------------------------------------
+// Compatibility layer for LPC2xxx device drivers
+//-----------------------------------------------------------------------------
+#define CYNUM_HAL_LPC24XX_PCLK_UART0 CYNUM_HAL_LPC17XX_PCLK_UART0
+#define CYNUM_HAL_LPC24XX_PCLK_UART1 CYNUM_HAL_LPC17XX_PCLK_UART1
+#define CYNUM_HAL_LPC24XX_PCLK_UART2 CYNUM_HAL_LPC17XX_PCLK_UART2
+#define CYNUM_HAL_LPC24XX_PCLK_UART3 CYNUM_HAL_LPC17XX_PCLK_UART3
+
+#define CYG_HAL_ARM_LPC24XX_BAUD_GENERATOR(_pclkid_, baud) \
+            CYG_HAL_CORTEXM_LPC17XX_BAUD_GENERATOR(_pclkid_, baud)
+
+//-----------------------------------------------------------------------------
+#endif // CYGONCE_HAL_CORTEXM_LPC17XX_VAR_LPC17XX_MISC_H
+// End of lpc17xx_misc.h
diff --git a/ecos/packages/hal/cortexm/lpc17xx/var/current/include/plf_stub.h b/ecos/packages/hal/cortexm/lpc17xx/var/current/include/plf_stub.h
new file mode 100644
index 0000000..e30e1af
--- /dev/null
+++ b/ecos/packages/hal/cortexm/lpc17xx/var/current/include/plf_stub.h
@@ -0,0 +1,86 @@
+#ifndef CYGONCE_HAL_PLF_STUB_H
+#define CYGONCE_HAL_PLF_STUB_H
+
+//=============================================================================
+//
+//      plf_stub.h
+//
+//      Platform header for GDB stub support.
+//
+//=============================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2004, 2005, 2006, 2008 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):   nickg
+// Contributors:jskov, gthomas, jlarmour
+// Date:        2008-07-30
+// Purpose:     Platform HAL stub support for STM32 variant boards.
+// Usage:       #include <cyg/hal/plf_stub.h>
+//              
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+#include <pkgconf/hal.h>
+#include CYGBLD_HAL_PLATFORM_H
+
+#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+
+#include <cyg/infra/cyg_type.h>         // CYG_UNUSED_PARAM
+#include <cyg/hal/cortexm_stub.h>       // architecture stub support
+#include <cyg/hal/hal_io.h>
+
+//----------------------------------------------------------------------------
+// Define some platform specific communication details. This is mostly
+// handled by hal_if now, but we need to make sure the comms tables are
+// properly initialized.
+
+__externC void cyg_hal_plf_comms_init(void);
+
+#define HAL_STUB_PLATFORM_INIT_SERIAL()       cyg_hal_plf_comms_init()
+
+#define HAL_STUB_PLATFORM_SET_BAUD_RATE(baud) CYG_UNUSED_PARAM(int, (baud))
+#define HAL_STUB_PLATFORM_INTERRUPTIBLE       0
+#define HAL_STUB_PLATFORM_INIT_BREAK_IRQ()    CYG_EMPTY_STATEMENT
+
+//----------------------------------------------------------------------------
+// Stub initializer.
+
+#define HAL_STUB_PLATFORM_INIT()              CYG_EMPTY_STATEMENT
+
+#endif // CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+
+//-----------------------------------------------------------------------------
+#endif // CYGONCE_HAL_PLF_STUB_H
+// End of plf_stub.h
diff --git a/ecos/packages/hal/cortexm/lpc17xx/var/current/include/var_arch.h b/ecos/packages/hal/cortexm/lpc17xx/var/current/include/var_arch.h
new file mode 100644
index 0000000..cbf21e3
--- /dev/null
+++ b/ecos/packages/hal/cortexm/lpc17xx/var/current/include/var_arch.h
@@ -0,0 +1,61 @@
+#ifndef CYGONCE_HAL_VAR_ARCH_H
+#define CYGONCE_HAL_VAR_ARCH_H
+//=============================================================================
+//
+//      var_arch.h
+//
+//      STM32 variant architecture overrides
+//
+//=============================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2008 Free Software Foundation, Inc.                        
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):    nickg
+// Date:         2008-07-30
+// Purpose:      LPC17XX variant architecture overrides
+// Description: 
+// Usage:        #include <cyg/hal/hal_arch.h>
+//
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+#include <pkgconf/hal.h>
+#include <cyg/hal/hal_io.h>
+
+#include <cyg/hal/plf_arch.h>
+
+//-----------------------------------------------------------------------------
+#endif // CYGONCE_HAL_VAR_ARCH_H
+// End of var_arch.h
diff --git a/ecos/packages/hal/cortexm/lpc17xx/var/current/include/var_intr.h b/ecos/packages/hal/cortexm/lpc17xx/var/current/include/var_intr.h
new file mode 100644
index 0000000..b2ebe90
--- /dev/null
+++ b/ecos/packages/hal/cortexm/lpc17xx/var/current/include/var_intr.h
@@ -0,0 +1,120 @@
+#ifndef CYGONCE_HAL_VAR_INTR_H
+#define CYGONCE_HAL_VAR_INTR_H
+//==========================================================================
+//
+//      var_intr.h
+//
+//      HAL Interrupt and clock assignments for LPC17XX variants
+//
+//==========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2010, 2011 Free Software Foundation, Inc.                        
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):     ilijak
+// Date:          2010-12-29
+// Purpose:       Define Interrupt support
+// Description:   The interrupt specifics for NXP LPC17XX variants are
+//                defined here.
+//              
+// Usage:         #include <cyg/hal/var_intr.h>
+//                However applications should include using <cyg/hal/hal_intr.h>
+//                instead to allow for platform overrides.
+//
+//####DESCRIPTIONEND####
+//
+//==========================================================================
+
+#include <cyg/hal/plf_intr.h>
+
+//==========================================================================
+
+#define CYGNUM_HAL_INTERRUPT_WD      (0+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_TIMER0  (1+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_TIMER1  (2+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_TIMER2  (3+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_TIMER3  (4+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_UART0   (5+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_UART1   (6+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_UART2   (7+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_UART3   (8+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_PWM1    (9+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_I2C0    (10+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_I2C1    (11+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_I2C2    (12+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+
+#define CYGNUM_HAL_INTERRUPT_SPI     (13+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_SSP0    (14+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_SSP1    (15+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+
+#define CYGNUM_HAL_INTERRUPT_PLL0    (16+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_RTCDEV  (17+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+
+#define CYGNUM_HAL_INTERRUPT_EINT0   (18+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_EINT1   (19+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_EINT2   (20+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_EINT3   (21+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_AD      (22+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_BOD     (23+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_USB     (24+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_CAN     (25+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_DMA     (26+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_I2S     (27+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_ETH     (28+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_RITINT  (29+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_MCPWM   (30+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_QENC    (31+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_PLL1    (32+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_USBAI   (33+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+#define CYGNUM_HAL_INTERRUPT_CANWAKE (34+CYGNUM_HAL_INTERRUPT_EXTERNAL)
+
+#define CYGNUM_HAL_INTERRUPT_NVIC_MAX (CYGNUM_HAL_INTERRUPT_CANWAKE)
+
+#define CYGNUM_HAL_ISR_MIN            0
+#define CYGNUM_HAL_ISR_MAX            CYGNUM_HAL_INTERRUPT_CANWAKE
+#define CYGNUM_HAL_ISR_COUNT          (CYGNUM_HAL_ISR_MAX+1)
+
+#define CYGNUM_HAL_VSR_MIN            0
+
+#ifndef CYGNUM_HAL_VSR_MAX
+# define CYGNUM_HAL_VSR_MAX (CYGNUM_HAL_VECTOR_SYS_TICK+CYGNUM_HAL_INTERRUPT_NVIC_MAX)
+#endif
+
+#define CYGNUM_HAL_VSR_COUNT          (CYGNUM_HAL_VSR_MAX+1)
+
+//==========================================================================
+// Interrupt mask and config for variant-specific devices
+
+//----------------------------------------------------------------------------
+#endif // CYGONCE_HAL_VAR_INTR_H
+// EOF var_intr.h
diff --git a/ecos/packages/hal/cortexm/lpc17xx/var/current/include/var_io.h b/ecos/packages/hal/cortexm/lpc17xx/var/current/include/var_io.h
new file mode 100644
index 0000000..4e01dd3
--- /dev/null
+++ b/ecos/packages/hal/cortexm/lpc17xx/var/current/include/var_io.h
@@ -0,0 +1,413 @@
+#ifndef CYGONCE_HAL_VAR_IO_H
+#define CYGONCE_HAL_VAR_IO_H
+//=============================================================================
+//
+//      var_io.h
+//
+//      Variant specific registers
+//
+//=============================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2008, 2009 Free Software Foundation, Inc.                  
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):     ilijak
+// Original data: Uwe Kindler ( LPC24XX port )
+// Date:          2010-12-22
+// Purpose:       LPC17XX variant specific registers
+// Description:
+// Usage:         #include <cyg/hal/var_io.h>
+//
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+#include <pkgconf/hal_cortexm_lpc17xx.h>
+
+#include <cyg/hal/plf_io.h>
+
+//=============================================================================
+// Peripherals
+
+//=============================================================================
+// Cortex-M architecture register
+
+// VTOR setting
+#ifndef CYGARC_REG_NVIC_VTOR_TBLBASE_SRAM
+#define CYGARC_REG_NVIC_VTOR_TBLBASE_SRAM               BIT_(28)
+#endif
+
+//---------------------------------------------------------------------------
+// Utilize LPC17xx flash between startup vectors and 0x2fc
+// for misc funtions.
+#ifdef CYGOPT_HAL_LPC17XX_MISC_FLASH_SECTION
+# define CYGOPT_HAL_LPC17XX_MISC_FLASH_SECTION_ATTR \
+         CYGBLD_ATTRIB_SECTION(".lpc17xx_misc")
+#else
+# define CYGOPT_HAL_LPC17XX_MISC_FLASH_SECTION_ATTR
+#endif
+
+__externC const cyg_uint32* hal_lpc17xx_crp_p(void);
+
+// LPC System Control Block
+#define CYGHWR_HAL_LPC17XX_REG_SCB_BASE                 0x400FC000
+
+// Flash accelerator
+#define CYGHWR_HAL_LPC17XX_REG_FLASHCFG                 0x0000
+#define CYGHWR_HAL_LPC17XX_REG_FLTSET(__tim)            (__tim << 12)
+#define CYGHWR_HAL_LPC17XX_REG_FLTIM20MHZ               0x0
+#define CYGHWR_HAL_LPC17XX_REG_FLTIM40MHZ               0x1
+#define CYGHWR_HAL_LPC17XX_REG_FLTIM60MHZ               0x2
+#define CYGHWR_HAL_LPC17XX_REG_FLTIM80MHZ               0x3
+#define CYGHWR_HAL_LPC17XX_REG_FLTIM100MHZ              0x4
+#define CYGHWR_HAL_LPC17XX_REG_FLTIM120MHZ              0x4
+#define CYGHWR_HAL_LPC17XX_REG_FLTIMSAFE                0x5
+#define CYGHWR_HAL_LPC17XX_REG_FLTIM_MASK               CYGHWR_HAL_LPC17XX_REG_FLTSET(0x0f)
+
+// PLL. Registers are offsets from base of this subsystem
+#define CYGHWR_HAL_LPC17XX_REG_PLL0CON                  0x0080
+#define CYGHWR_HAL_LPC17XX_REG_PLLCON_PLLE              (1<<0)
+#define CYGHWR_HAL_LPC17XX_REG_PLLCON_PLLC              (1<<1)
+#define CYGHWR_HAL_LPC17XX_REG_PLL0CFG                  0x0084
+#define CYGHWR_HAL_LPC17XX_REG_PLL0STAT                 0x0088
+#define CYGHWR_HAL_LPC17XX_REG_PLL0STAT_PLLE            (1<<24)
+#define CYGHWR_HAL_LPC17XX_REG_PLL0STAT_PLLC            (1<<25)
+#define CYGHWR_HAL_LPC17XX_REG_PLL0STAT_PLOCK           (1<<26)
+#define CYGHWR_HAL_LPC17XX_REG_PLL0FEED                 0x008C
+
+#define CYGHWR_HAL_LPC17XX_REG_PLL1CON                  0x00A0
+#define CYGHWR_HAL_LPC17XX_REG_PLL1CFG                  0x00A4
+#define CYGHWR_HAL_LPC17XX_REG_PLL1STAT                 0x00A8
+#define CYGHWR_HAL_LPC17XX_REG_PLL1STAT_PLLE            (1<<8)
+#define CYGHWR_HAL_LPC17XX_REG_PLL1STAT_PLLC            (1<<9)
+#define CYGHWR_HAL_LPC17XX_REG_PLL1STAT_PLOCK           (1<<10)
+#define CYGHWR_HAL_LPC17XX_REG_PLL1FEED                 0x00AC
+
+// Clock source selection register
+#define CYGHWR_HAL_LPC17XX_REG_CLKSRCSEL                0x010C
+#define CYGHWR_HAL_LPC17XX_REG_CLKSRCSEL_IRC            0x00
+#define CYGHWR_HAL_LPC17XX_REG_CLKSRCSEL_MAIN           0x01
+#define CYGHWR_HAL_LPC17XX_REG_CLKSRCSEL_RTC            0x10
+
+#define CYGHWR_HAL_LPC17XX_REG_CCLKCFG                  0x0104
+#define CYGHWR_HAL_LPC17XX_REG_USBCLKCFG                0x0108
+/* #define CYGHWR_HAL_LPC17XX_REG_IRCTRIM                  0x01A4 */
+#define CYGHWR_HAL_LPC17XX_REG_PCLKSEL0                 0x01A8
+#define CYGHWR_HAL_LPC17XX_REG_PCLKSEL1                 0x01AC
+#define CYGHWR_HAL_LPC17XX_REG_INTWAKE                  0x0144
+
+// Power Control
+#define CYGHWR_HAL_LPC17XX_REG_PCON                     0x00C0
+#define CYGHWR_HAL_LPC17XX_REG_PCON_IDL                 (1<<0)
+#define CYGHWR_HAL_LPC17XX_REG_PCON_PD                  (1<<1)
+#define CYGHWR_HAL_LPC17XX_REG_PCONP                    0x00C4
+#define CYGHWR_HAL_LPC17XX_REG_PCONP_TIM0               (1<<1)
+#define CYGHWR_HAL_LPC17XX_REG_PCONP_TIM1               (1<<2)
+#define CYGHWR_HAL_LPC17XX_REG_PCONP_URT0               (1<<3)
+#define CYGHWR_HAL_LPC17XX_REG_PCONP_URT1               (1<<4)
+#define CYGHWR_HAL_LPC17XX_REG_PCONP_PWM0               (1<<5)
+#define CYGHWR_HAL_LPC17XX_REG_PCONP_PWM1               (1<<6)
+#define CYGHWR_HAL_LPC17XX_REG_PCONP_I2C0               (1<<7)
+#define CYGHWR_HAL_LPC17XX_REG_PCONP_SPI                (1<<8)
+#define CYGHWR_HAL_LPC17XX_REG_PCONP_RTC                (1<<9)
+#define CYGHWR_HAL_LPC17XX_REG_PCONP_SSP1               (1<<10)
+#define CYGHWR_HAL_LPC17XX_REG_PCONP_EMC                (1<<11)
+#define CYGHWR_HAL_LPC17XX_REG_PCONP_AD                 (1<<12)
+#define CYGHWR_HAL_LPC17XX_REG_PCONP_CAN1               (1<<13)
+#define CYGHWR_HAL_LPC17XX_REG_PCONP_CAN2               (1<<14)
+#define CYGHWR_HAL_LPC17XX_REG_PCONP_I2C1               (1<<19)
+#define CYGHWR_HAL_LPC17XX_REG_PCONP_LCD                (1<<20)
+#define CYGHWR_HAL_LPC17XX_REG_PCONP_SSP0               (1<<21)
+#define CYGHWR_HAL_LPC17XX_REG_PCONP_TIM2               (1<<22)
+#define CYGHWR_HAL_LPC17XX_REG_PCONP_TIM3               (1<<23)
+#define CYGHWR_HAL_LPC17XX_REG_PCONP_URT2               (1<<24)
+#define CYGHWR_HAL_LPC17XX_REG_PCONP_URT3               (1<<25)
+#define CYGHWR_HAL_LPC17XX_REG_PCONP_I2C2               (1<<26)
+#define CYGHWR_HAL_LPC17XX_REG_PCONP_I2S                (1<<27)
+#define CYGHWR_HAL_LPC17XX_REG_PCONP_SD                 (1<<28)
+#define CYGHWR_HAL_LPC17XX_REG_PCONP_DMA                (1<<29)
+#define CYGHWR_HAL_LPC17XX_REG_PCONP_ENET               (1<<30)
+#define CYGHWR_HAL_LPC17XX_REG_PCONP_USB                (1<<31)
+
+// Utility
+#define CYGHWR_HAL_LPC17XX_REG_CLKOUTCFG                0x01C8
+
+// System control and status register
+#define CYGHWR_HAL_LPC17XX_REG_SCS                      0x01A0
+#define CYGHWR_HAL_LPC17XX_REG_SCS_OSCEN                0x20
+#define CYGHWR_HAL_LPC17XX_REG_SCS_OSCSTAT              0x40
+
+
+//=============================================================================
+// Pin Connect Block (PIN)
+
+#define CYGHWR_HAL_LPC17XX_REG_PIN_BASE                  0x4002C000
+
+#define CYGHWR_HAL_LPC17XX_REG_PINSEL0                   0x000
+#define CYGHWR_HAL_LPC17XX_REG_PINSEL1                   0x004
+#define CYGHWR_HAL_LPC17XX_REG_PINSEL2                   0x008
+#define CYGHWR_HAL_LPC17XX_REG_PINSEL3                   0x00C
+#define CYGHWR_HAL_LPC17XX_REG_PINSEL4                   0x010
+#define CYGHWR_HAL_LPC17XX_REG_PINSEL5                   0x014
+#define CYGHWR_HAL_LPC17XX_REG_PINSEL6                   0x018
+#define CYGHWR_HAL_LPC17XX_REG_PINSEL7                   0x01C
+#define CYGHWR_HAL_LPC17XX_REG_PINSEL8                   0x020
+#define CYGHWR_HAL_LPC17XX_REG_PINSEL9                   0x024
+#define CYGHWR_HAL_LPC17XX_REG_PINSEL10                  0x028
+#define CYGHWR_HAL_LPC17XX_REG_PINSEL11                  0x02C
+
+#define CYGHWR_HAL_LPC17XX_REG_PINMODE0                  0x040
+#define CYGHWR_HAL_LPC17XX_REG_PINMODE1                  0x044
+#define CYGHWR_HAL_LPC17XX_REG_PINMODE2                  0x048
+#define CYGHWR_HAL_LPC17XX_REG_PINMODE3                  0x04C
+#define CYGHWR_HAL_LPC17XX_REG_PINMODE4                  0x050
+#define CYGHWR_HAL_LPC17XX_REG_PINMODE5                  0x054
+#define CYGHWR_HAL_LPC17XX_REG_PINMODE6                  0x058
+#define CYGHWR_HAL_LPC17XX_REG_PINMODE7                  0x05C
+#define CYGHWR_HAL_LPC17XX_REG_PINMODE8                  0x060
+#define CYGHWR_HAL_LPC17XX_REG_PINMODE9                  0x064
+
+#define CYGHWR_HAL_LPC17XX_PIN_SET(_reg, _func) \
+            HAL_WRITE_UINT32(CYGHWR_HAL_LPC17XX_REG_PIN_BASE + _reg, _func)
+
+#define CYGHWR_HAL_LPC17XX_PIN_GET(_reg, _dst) \
+            HAL_READ_UINT32(CYGHWR_HAL_LPC17XX_REG_PIN_BASE + _reg, _dst)
+
+//=============================================================================
+// UARTs (Ux)
+
+#define CYGHWR_HAL_LPC17XX_REG_UART0_BASE                0x4000C000
+#define CYGHWR_HAL_LPC17XX_REG_UART1_BASE                0x40010000
+#define CYGHWR_HAL_LPC17XX_REG_UART2_BASE                0x40098000
+#define CYGHWR_HAL_LPC17XX_REG_UART3_BASE                0x4009C000
+
+// Registers are offsets from base for each UART
+#define CYGHWR_HAL_LPC17XX_REG_UxRBR                     0x0000 // DLAB=0 read
+#define CYGHWR_HAL_LPC17XX_REG_UxTHR                     0x0000 // DLAB=0 write
+#define CYGHWR_HAL_LPC17XX_REG_UxDLL                     0x0000 // DLAB=1 r/w
+#define CYGHWR_HAL_LPC17XX_REG_UxIER                     0x0004 // DLAB=0
+#define CYGHWR_HAL_LPC17XX_REG_UxIER_RXDATA_INT          (1<<0)
+#define CYGHWR_HAL_LPC17XX_REG_UxIER_THRE_INT            (1<<1)
+#define CYGHWR_HAL_LPC17XX_REG_UxIER_RXLS_INT            (1<<2)
+#define CYGHWR_HAL_LPC17XX_REG_U1IER_RXMS_INT            (1<<3) // U1 only
+#define CYGHWR_HAL_LPC17XX_REG_UxDLM                     0x0004 // DLAB=1
+
+#define CYGHWR_HAL_LPC17XX_REG_UxIIR                     0x0008 // read
+#define CYGHWR_HAL_LPC17XX_REG_UxIIR_IIR0                (1<<0)
+#define CYGHWR_HAL_LPC17XX_REG_UxIIR_IIR1                (1<<1)
+#define CYGHWR_HAL_LPC17XX_REG_UxIIR_IIR2                (1<<2)
+#define CYGHWR_HAL_LPC17XX_REG_UxIIR_IIR3                (1<<3)
+#define CYGHWR_HAL_LPC17XX_REG_UxIIR_FIFOS               (0xB0)
+
+#define CYGHWR_HAL_LPC17XX_REG_UxFCR                     0x0008 // write
+#define CYGHWR_HAL_LPC17XX_REG_UxFCR_FIFO_ENA            (1<<0)
+#define CYGHWR_HAL_LPC17XX_REG_UxFCR_RX_FIFO_RESET       (1<<1)
+#define CYGHWR_HAL_LPC17XX_REG_UxFCR_TX_FIFO_RESET       (1<<2)
+#define CYGHWR_HAL_LPC17XX_REG_UxFCR_RX_TRIGGER_0        (0x00)
+#define CYGHWR_HAL_LPC17XX_REG_UxFCR_RX_TRIGGER_1        (0x40)
+#define CYGHWR_HAL_LPC17XX_REG_UxFCR_RX_TRIGGER_2        (0x80)
+#define CYGHWR_HAL_LPC17XX_REG_UxFCR_RX_TRIGGER_3        (0xB0)
+
+#define CYGHWR_HAL_LPC17XX_REG_UxLCR                     0x000C
+#define CYGHWR_HAL_LPC17XX_REG_UxLCR_WORD_LENGTH_5       (0x00)
+#define CYGHWR_HAL_LPC17XX_REG_UxLCR_WORD_LENGTH_6       (0x01)
+#define CYGHWR_HAL_LPC17XX_REG_UxLCR_WORD_LENGTH_7       (0x02)
+#define CYGHWR_HAL_LPC17XX_REG_UxLCR_WORD_LENGTH_8       (0x03)
+#define CYGHWR_HAL_LPC17XX_REG_UxLCR_STOP_1              (0x00)
+#define CYGHWR_HAL_LPC17XX_REG_UxLCR_STOP_2              (0x04)
+#define CYGHWR_HAL_LPC17XX_REG_UxLCR_PARITY_ENA          (0x08)
+#define CYGHWR_HAL_LPC17XX_REG_UxLCR_PARITY_ODD          (0x00)
+#define CYGHWR_HAL_LPC17XX_REG_UxLCR_PARITY_EVEN         (0x10)
+#define CYGHWR_HAL_LPC17XX_REG_UxLCR_PARITY_ONE          (0x20)
+#define CYGHWR_HAL_LPC17XX_REG_UxLCR_PARITY_ZERO         (0x30)
+#define CYGHWR_HAL_LPC17XX_REG_UxLCR_BREAK_ENA           (0x40)
+#define CYGHWR_HAL_LPC17XX_REG_UxLCR_DLAB                (0x80)
+
+// Modem Control Register is UART1 only
+#define CYGHWR_HAL_LPC17XX_REG_U1MCR                     0x0010
+#define CYGHWR_HAL_LPC17XX_REG_U1MCR_DTR                 (1<<0)
+#define CYGHWR_HAL_LPC17XX_REG_U1MCR_RTS                 (1<<1)
+#define CYGHWR_HAL_LPC17XX_REG_U1MCR_LOOPBACK            (1<<4)
+
+#define CYGHWR_HAL_LPC17XX_REG_UxLSR                     0x0014
+#define CYGHWR_HAL_LPC17XX_REG_UxLSR_RDR                 (1<<0)
+#define CYGHWR_HAL_LPC17XX_REG_UxLSR_OE                  (1<<1)
+#define CYGHWR_HAL_LPC17XX_REG_UxLSR_PE                  (1<<2)
+#define CYGHWR_HAL_LPC17XX_REG_UxLSR_FE                  (1<<3)
+#define CYGHWR_HAL_LPC17XX_REG_UxLSR_BI                  (1<<4)
+#define CYGHWR_HAL_LPC17XX_REG_UxLSR_THRE                (1<<5)
+#define CYGHWR_HAL_LPC17XX_REG_UxLSR_TEMT                (1<<6)
+#define CYGHWR_HAL_LPC17XX_REG_UxLSR_RX_FIFO_ERR         (1<<7)
+
+// Modem Status Register is UART1 only
+#define CYGHWR_HAL_LPC17XX_REG_U1MSR                     0x0018
+#define CYGHWR_HAL_LPC17XX_REG_U1MSR_DCTS                (1<<0)
+#define CYGHWR_HAL_LPC17XX_REG_U1MSR_DDSR                (1<<1)
+#define CYGHWR_HAL_LPC17XX_REG_U1MSR_RI_FALL             (1<<2)
+#define CYGHWR_HAL_LPC17XX_REG_U1MSR_DDCD                (1<<3)
+#define CYGHWR_HAL_LPC17XX_REG_U1MSR_CTS                 (1<<4)
+#define CYGHWR_HAL_LPC17XX_REG_U1MSR_DSR                 (1<<5)
+#define CYGHWR_HAL_LPC17XX_REG_U1MSR_RI                  (1<<6)
+#define CYGHWR_HAL_LPC17XX_REG_U1MSR_DCD                 (1<<7)
+
+#define CYGHWR_HAL_LPC17XX_REG_UxSCR                     0x001C
+#define CYGHWR_HAL_LPC17XX_REG_UxACR                     0x0020
+#define CYGHWR_HAL_LPC17XX_REG_U3ICR                     0x0024
+#define CYGHWR_HAL_LPC17XX_REG_UxFDR                     0x0028
+#define CYGHWR_HAL_LPC17XX_REG_UxTER                     0x0030
+
+// RTC
+#define CYGHWR_HAL_LPC17XX_REG_RTC_BASE                   0x40024000
+#define CYGARC_HAL_LPC2XXX_REG_RTC_BASE  CYGHWR_HAL_LPC17XX_REG_RTC_BASE
+
+// Registers are offsets from base of this subsystem
+#define CYGHWR_HAL_LPC17XX_REG_RTC_ILR                    0x0000
+#define CYGHWR_HAL_LPC17XX_REG_RTC_ILR_CIF                (1<<0)
+#define CYGHWR_HAL_LPC17XX_REG_RTC_ILR_ALF                (1<<1)
+#define CYGHWR_HAL_LPC17XX_REG_RTC_CTC                    0x0004
+#define CYGHWR_HAL_LPC17XX_REG_RTC_CCR                    0x0008
+#define CYGHWR_HAL_LPC17XX_REG_RTC_CCR_CLKEN              (1<<0)
+#define CYGHWR_HAL_LPC17XX_REG_RTC_CCR_CTCRST             (1<<1)
+#define CYGHWR_HAL_LPC17XX_REG_RTC_CIIR                   0x000C
+#define CYGHWR_HAL_LPC17XX_REG_RTC_AMR                    0x0010
+#define CYGHWR_HAL_LPC17XX_REG_RTC_CTIME0                 0x0014
+#define CYGHWR_HAL_LPC17XX_REG_RTC_CTIME1                 0x0018
+#define CYGHWR_HAL_LPC17XX_REG_RTC_CTIME2                 0x001C
+#define CYGHWR_HAL_LPC17XX_REG_RTC_SEC                    0x0020
+#define CYGHWR_HAL_LPC17XX_REG_RTC_MIN                    0x0024
+#define CYGHWR_HAL_LPC17XX_REG_RTC_HOUR                   0x0028
+#define CYGHWR_HAL_LPC17XX_REG_RTC_DOM                    0x002C
+#define CYGHWR_HAL_LPC17XX_REG_RTC_DOW                    0x0030
+#define CYGHWR_HAL_LPC17XX_REG_RTC_DOY                    0x0034
+#define CYGHWR_HAL_LPC17XX_REG_RTC_MONTH                  0x0038
+#define CYGHWR_HAL_LPC17XX_REG_RTC_YEAR                   0x003C
+#define CYGHWR_HAL_LPC17XX_REG_RTC_ALSEC                  0x0060
+#define CYGHWR_HAL_LPC17XX_REG_RTC_ALMIN                  0x0064
+#define CYGHWR_HAL_LPC17XX_REG_RTC_ALHOUR                 0x0068
+#define CYGHWR_HAL_LPC17XX_REG_RTC_ALDOM                  0x006C
+#define CYGHWR_HAL_LPC17XX_REG_RTC_ALDOW                  0x0070
+#define CYGHWR_HAL_LPC17XX_REG_RTC_ALDOY                  0x0074
+#define CYGHWR_HAL_LPC17XX_REG_RTC_ALMON                  0x0078
+#define CYGHWR_HAL_LPC17XX_REG_RTC_ALYEAR                 0x007C
+#define CYGHWR_HAL_LPC17XX_REG_RTC_PREINT                 0x0080
+#define CYGHWR_HAL_LPC17XX_REG_RTC_PREFRAC                0x0084
+
+// Ethernet (EMAC)
+#define CYGHWR_HAL_LPC17XX_REG_EMAC_BASE                0x50000000
+
+// End Peripherals
+
+#ifndef __ASSEMBLER__
+
+__externC void hal_plf_uart_setbaud( CYG_ADDRESS uart, cyg_uint32 baud );
+
+//-----------------------------------------------------------------------------
+// Configure pin function
+//
+__externC void  hal_set_pin_function(cyg_uint8 port, cyg_uint8 pin,
+                                     cyg_uint8 function);
+
+//-----------------------------------------------------------------------------
+// Function to enable/disable power for certain peripheral
+// Use PCONP identifiers from below
+//
+externC void hal_lpc_set_power(cyg_uint8 pconp_id, int on);
+
+
+//-----------------------------------------------------------------------------
+// Identifiers for power control, hal_get_pclk()
+//
+#define CYNUM_HAL_LPC17XX_PCONP_TIMER0 1
+#define CYNUM_HAL_LPC17XX_PCONP_TIMER1 2
+#define CYNUM_HAL_LPC17XX_PCONP_UART0  3
+#define CYNUM_HAL_LPC17XX_PCONP_UART1  4
+#define CYNUM_HAL_LPC17XX_PCONP_PWM0   5
+#define CYNUM_HAL_LPC17XX_PCONP_PWM1   6
+#define CYNUM_HAL_LPC17XX_PCONP_I2C0   7
+#define CYNUM_HAL_LPC17XX_PCONP_SPI    8
+#define CYNUM_HAL_LPC17XX_PCONP_RTC    9
+#define CYNUM_HAL_LPC17XX_PCONP_SSP1   10
+#define CYNUM_HAL_LPC17XX_PCONP_EMC    11
+#define CYNUM_HAL_LPC17XX_PCONP_ADC    12
+#define CYNUM_HAL_LPC17XX_PCONP_CAN1   13
+#define CYNUM_HAL_LPC17XX_PCONP_CAN2   14
+#define CYNUM_HAL_LPC17XX_PCONP_I2C1   19
+#define CYNUM_HAL_LPC17XX_PCONP_LCD    20
+#define CYNUM_HAL_LPC17XX_PCONP_SSP0   21
+#define CYNUM_HAL_LPC17XX_PCONP_TIMER2 22
+#define CYNUM_HAL_LPC17XX_PCONP_TIMER3 23
+#define CYNUM_HAL_LPC17XX_PCONP_UART2  24
+#define CYNUM_HAL_LPC17XX_PCONP_UART3  25
+#define CYNUM_HAL_LPC17XX_PCONP_I2C2   26
+#define CYNUM_HAL_LPC17XX_PCONP_I2S    27
+#define CYNUM_HAL_LPC17XX_PCONP_SDC    28
+#define CYNUM_HAL_LPC17XX_PCONP_GPDMA  29
+#define CYNUM_HAL_LPC17XX_PCONP_ENET   30
+#define CYNUM_HAL_LPC17XX_PCONP_USB    31
+
+#endif // ifndef __ASSEMBLER__
+
+
+//-----------------------------------------------------------------------------
+// LPC2xxx compatibility block
+// These definitions enable reusing of compatible LPC2xxx devs.
+
+// UART
+#define CYGARC_HAL_LPC24XX_REG_UART0_BASE CYGHWR_HAL_LPC17XX_REG_UART0_BASE
+#define CYGARC_HAL_LPC24XX_REG_UART1_BASE CYGHWR_HAL_LPC17XX_REG_UART1_BASE
+#define CYGARC_HAL_LPC24XX_REG_UART2_BASE CYGHWR_HAL_LPC17XX_REG_UART2_BASE
+#define CYGARC_HAL_LPC24XX_REG_UART3_BASE CYGHWR_HAL_LPC17XX_REG_UART3_BASE
+
+// RTC
+#define CYGARC_HAL_LPC2XXX_REG_RTC_BASE  CYGHWR_HAL_LPC17XX_REG_RTC_BASE
+
+// Ethernet (EMAC)
+#define CYGARC_HAL_LPC2XXX_REG_EMAC_BASE CYGHWR_HAL_LPC17XX_REG_EMAC_BASE
+
+// System Control Block
+#define CYGARC_HAL_LPC24XX_REG_SCB_BASE      CYGHWR_HAL_LPC17XX_REG_SCB_BASE
+
+// Power Control
+#define CYGARC_HAL_LPC24XX_REG_PCONP         CYGHWR_HAL_LPC17XX_REG_PCONP
+#define CYGARC_HAL_LPC24XX_REG_PCONP_ENET    CYGHWR_HAL_LPC17XX_REG_PCONP_ENET
+
+// Pin Connect Block (PIN)
+#define CYGARC_HAL_LPC24XX_REG_PIN_BASE      CYGHWR_HAL_LPC17XX_REG_PIN_BASE
+#define CYGARC_HAL_LPC24XX_REG_PINSEL2       CYGHWR_HAL_LPC17XX_REG_PINSEL2
+#define CYGARC_HAL_LPC24XX_REG_PINSEL3       CYGHWR_HAL_LPC17XX_REG_PINSEL3
+
+// End of LPC2xxx device compatibiliy block.
+
+//-----------------------------------------------------------------------------
+#endif // CYGONCE_HAL_VAR_IO_H
+// End of var_io.h
diff --git a/ecos/packages/hal/cortexm/lpc17xx/var/current/include/variant.inc b/ecos/packages/hal/cortexm/lpc17xx/var/current/include/variant.inc
new file mode 100644
index 0000000..d509d5c
--- /dev/null
+++ b/ecos/packages/hal/cortexm/lpc17xx/var/current/include/variant.inc
@@ -0,0 +1,53 @@
+/*==========================================================================
+//
+//      variant.inc
+//
+//      Variant specific asm definitions
+//
+//==========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2010 Free Software Foundation, Inc.                        
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):    nickg, ilijak
+// Date:         2010-12-25
+// Description:  
+//
+//####DESCRIPTIONEND####
+//
+//========================================================================*/
+
+#include <pkgconf/hal_cortexm_lpc17xx.h>
+
+//==========================================================================
+// EOF variant.inc
diff --git a/ecos/packages/hal/cortexm/lpc17xx/var/current/src/hal_diag.c b/ecos/packages/hal/cortexm/lpc17xx/var/current/src/hal_diag.c
new file mode 100644
index 0000000..5c8f144
--- /dev/null
+++ b/ecos/packages/hal/cortexm/lpc17xx/var/current/src/hal_diag.c
@@ -0,0 +1,402 @@
+//=============================================================================
+//
+//      hal_diag.c
+//
+//      HAL diagnostic output code
+//
+//=============================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2004, 2005, 2006, 2008, 2010  Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):    nickg, jani, ilijak
+// Contributors: jskov, gthomas
+// Date:         2010-12-15
+// Purpose:      HAL diagnostic output
+// Description:  Implementations of HAL diagnostic output support.
+//
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+
+#include <pkgconf/hal.h>
+#include CYGBLD_HAL_PLATFORM_H
+
+#include <cyg/infra/cyg_type.h>        // base types
+#include <cyg/infra/cyg_trac.h>        // tracing
+
+#include <cyg/hal/hal_arch.h>          // SAVE/RESTORE GP macros
+#include <cyg/hal/hal_io.h>            // IO macros
+#include <cyg/hal/hal_if.h>            // interface API
+#include <cyg/hal/hal_intr.h>          // HAL_ENABLE/MASK/UNMASK_INTERRUPTS
+#include <cyg/hal/hal_misc.h>          // Helper functions
+#include <cyg/hal/drv_api.h>           // CYG_ISR_HANDLED
+
+#include <cyg/hal/var_io.h>            // USART registers
+#include <cyg/hal/lpc17xx_misc.h>      // peripheral identifiers
+
+//-----------------------------------------------------------------------------
+
+typedef struct {
+    cyg_uint32      uart;
+    CYG_ADDRESS     base;
+    cyg_int32       msec_timeout;
+    int             isr_vector;
+    int             baud_rate;
+    cyg_uint8       periph_id;
+    int             irq_state;
+} channel_data_t;
+
+static channel_data_t lpc17xx_ser_channels[] = {
+#if CYGINT_HAL_LPC17XX_UART0>0
+    {0,
+     CYGHWR_HAL_LPC17XX_REG_UART0_BASE,
+     1000,
+     CYGNUM_HAL_INTERRUPT_UART0,
+     CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD,
+     CYNUM_HAL_LPC17XX_PCLK_UART0},
+#endif
+#if CYGINT_HAL_LPC17XX_UART1>0
+    {1,
+     CYGHWR_HAL_LPC17XX_REG_UART1_BASE,
+     1000,
+     CYGNUM_HAL_INTERRUPT_UART1,
+     CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD,
+     CYNUM_HAL_LPC17XX_PCLK_UART1}
+#endif
+};
+
+#define HAL_PLF_SER_CHANNELS lpc17xx_ser_channels
+
+
+//===========================================================================
+// Initialize diagnostic serial channel
+//===========================================================================
+static void
+hal_plf_serial_init_channel(void *__ch_data)
+{
+    channel_data_t *chan = (channel_data_t *) __ch_data;
+    CYG_ADDRESS     base = chan->base;
+
+    hal_plf_uart_setbaud(base, chan->baud_rate);
+
+    // 8-1-no parity.
+    HAL_WRITE_UINT32(base + CYGHWR_HAL_LPC17XX_REG_UxLCR,
+                     CYGHWR_HAL_LPC17XX_REG_UxLCR_WORD_LENGTH_8 |
+                     CYGHWR_HAL_LPC17XX_REG_UxLCR_STOP_1);
+
+    // Reset and enable FIFO
+    HAL_WRITE_UINT32(base + CYGHWR_HAL_LPC17XX_REG_UxFCR,
+                     CYGHWR_HAL_LPC17XX_REG_UxFCR_FIFO_ENA |
+                     CYGHWR_HAL_LPC17XX_REG_UxFCR_RX_FIFO_RESET |
+                     CYGHWR_HAL_LPC17XX_REG_UxFCR_TX_FIFO_RESET);
+}
+
+
+//===========================================================================
+// Write single character
+//===========================================================================
+void
+hal_plf_serial_putc(void *__ch_data, char c)
+{
+    CYG_ADDRESS     base = ((channel_data_t *) __ch_data)->base;
+    cyg_uint32      sr;
+
+    CYGARC_HAL_SAVE_GP();
+
+    do {
+        HAL_READ_UINT32(base + CYGHWR_HAL_LPC17XX_REG_UxLSR, sr);
+    } while ((sr & CYGHWR_HAL_LPC17XX_REG_UxLSR_THRE) == 0);
+
+    HAL_WRITE_UINT32(base + CYGHWR_HAL_LPC17XX_REG_UxTHR, c);
+
+    CYGARC_HAL_RESTORE_GP();
+}
+
+static cyg_bool
+hal_plf_serial_getc_nonblock(void *__ch_data, cyg_uint8 *ch)
+{
+    CYG_ADDRESS     base = ((channel_data_t *) __ch_data)->base;
+    cyg_uint32      sr;
+    cyg_uint32      c;
+
+    CYGARC_HAL_SAVE_GP();
+
+    HAL_READ_UINT32(base + CYGHWR_HAL_LPC17XX_REG_UxLSR, sr);
+
+    if ((sr & CYGHWR_HAL_LPC17XX_REG_UxLSR_RDR) == 0)
+        return false;
+
+    HAL_READ_UINT32(base + CYGHWR_HAL_LPC17XX_REG_UxRBR, c);
+
+    *ch = (cyg_uint8)c;
+
+    CYGARC_HAL_RESTORE_GP();
+
+    return true;
+}
+
+cyg_uint8
+hal_plf_serial_getc(void *__ch_data)
+{
+    cyg_uint8       ch;
+
+    CYGARC_HAL_SAVE_GP();
+
+    while (!hal_plf_serial_getc_nonblock(__ch_data, &ch));
+
+    CYGARC_HAL_RESTORE_GP();
+
+    return ch;
+}
+
+//=============================================================================
+// Virtual vector HAL diagnostics
+
+#if defined(CYGSEM_HAL_VIRTUAL_VECTOR_DIAG)
+
+static void
+hal_plf_serial_write(void *__ch_data, const cyg_uint8 *__buf,
+                     cyg_uint32 __len)
+{
+    CYGARC_HAL_SAVE_GP();
+
+    while (__len-- > 0)
+        hal_plf_serial_putc(__ch_data, *__buf++);
+
+    CYGARC_HAL_RESTORE_GP();
+}
+
+static void
+hal_plf_serial_read(void *__ch_data, cyg_uint8 *__buf, cyg_uint32 __len)
+{
+    CYGARC_HAL_SAVE_GP();
+
+    while (__len-- > 0)
+        *__buf++ = hal_plf_serial_getc(__ch_data);
+
+    CYGARC_HAL_RESTORE_GP();
+}
+
+cyg_bool
+hal_plf_serial_getc_timeout(void *__ch_data, cyg_uint8 *ch)
+{
+    int             delay_count;
+    channel_data_t *chan = (channel_data_t *) __ch_data;
+    cyg_bool        res;
+
+    CYGARC_HAL_SAVE_GP();
+
+    // Delay in 10 us steps
+    delay_count = chan->msec_timeout * 100;
+
+    while(true) {
+        res = hal_plf_serial_getc_nonblock(__ch_data, ch);
+        if (res || 0 == delay_count--)
+            break;
+
+        CYGACC_CALL_IF_DELAY_US(10);
+    }
+
+    CYGARC_HAL_RESTORE_GP();
+
+    return res;
+}
+
+static int
+hal_plf_serial_control(void *__ch_data, __comm_control_cmd_t __func, ...)
+{
+    channel_data_t *chan = (channel_data_t *) __ch_data;
+    CYG_ADDRESS     base = ((channel_data_t *) __ch_data)->base;
+    int             ret = 0;
+
+    va_list         ap;
+
+    CYGARC_HAL_SAVE_GP();
+
+    va_start(ap, __func);
+
+    switch (__func) {
+    case __COMMCTL_IRQ_ENABLE:
+        chan->irq_state = 1;
+        HAL_INTERRUPT_ACKNOWLEDGE(chan->isr_vector);
+        HAL_INTERRUPT_UNMASK(chan->isr_vector);
+        HAL_WRITE_UINT32(base + CYGHWR_HAL_LPC17XX_REG_UxIER,
+                         CYGHWR_HAL_LPC17XX_REG_UxIER_RXDATA_INT);
+        break;
+    case __COMMCTL_IRQ_DISABLE:
+        ret = chan->irq_state;
+        chan->irq_state = 0;
+        HAL_INTERRUPT_MASK(chan->isr_vector);
+        HAL_WRITE_UINT32(base + CYGHWR_HAL_LPC17XX_REG_UxIER,
+                         CYGHWR_HAL_LPC17XX_REG_UxIER_RXDATA_INT);
+        break;
+    case __COMMCTL_DBG_ISR_VECTOR:
+        ret = chan->isr_vector;
+        break;
+    case __COMMCTL_SET_TIMEOUT:
+        {
+            va_list         ap;
+
+            va_start(ap, __func);
+
+            ret = chan->msec_timeout;
+            chan->msec_timeout = va_arg(ap, cyg_uint32);
+
+            va_end(ap);
+        }
+    case __COMMCTL_GETBAUD:
+        ret = chan->baud_rate;
+        break;
+    case __COMMCTL_SETBAUD:
+        chan->baud_rate = va_arg(ap, cyg_int32);
+        // Should we verify this value here?
+        hal_plf_uart_setbaud(base, chan->baud_rate);
+        ret = 0;
+        break;
+    default:
+        break;
+    }
+    va_end(ap);
+    CYGARC_HAL_RESTORE_GP();
+    return ret;
+}
+
+static int
+hal_plf_serial_isr(void *__ch_data, int *__ctrlc,
+                   CYG_ADDRWORD __vector, CYG_ADDRWORD __data)
+{
+    channel_data_t *chan = (channel_data_t *) __ch_data;
+    cyg_uint8       ch;
+
+    CYGARC_HAL_SAVE_GP();
+
+    *__ctrlc = 0;
+
+    if (hal_plf_serial_getc_nonblock(__ch_data, &ch)) {
+        if (cyg_hal_is_break((char *)&ch, 1))
+            *__ctrlc = 1;
+    }
+
+    HAL_INTERRUPT_ACKNOWLEDGE(chan->isr_vector);
+
+    CYGARC_HAL_RESTORE_GP();
+
+    return 1;
+}
+
+static void
+hal_plf_serial_init(void)
+{
+    hal_virtual_comm_table_t *comm;
+    int             cur;
+    int             i;
+
+    cur =
+        CYGACC_CALL_IF_SET_CONSOLE_COMM
+        (CYGNUM_CALL_IF_SET_COMM_ID_QUERY_CURRENT);
+
+    for (i = 0; i < CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS; i++) {
+        hal_plf_serial_init_channel(&lpc17xx_ser_channels[i]);
+
+        CYGACC_CALL_IF_SET_CONSOLE_COMM(i);
+        comm = CYGACC_CALL_IF_CONSOLE_PROCS();
+        CYGACC_COMM_IF_CH_DATA_SET(*comm, &lpc17xx_ser_channels[i]);
+        CYGACC_COMM_IF_WRITE_SET(*comm, hal_plf_serial_write);
+        CYGACC_COMM_IF_READ_SET(*comm, hal_plf_serial_read);
+        CYGACC_COMM_IF_PUTC_SET(*comm, hal_plf_serial_putc);
+        CYGACC_COMM_IF_GETC_SET(*comm, hal_plf_serial_getc);
+        CYGACC_COMM_IF_CONTROL_SET(*comm, hal_plf_serial_control);
+        CYGACC_COMM_IF_DBG_ISR_SET(*comm, hal_plf_serial_isr);
+        CYGACC_COMM_IF_GETC_TIMEOUT_SET(*comm, hal_plf_serial_getc_timeout);
+    }
+
+    // Restore original console
+    CYGACC_CALL_IF_SET_CONSOLE_COMM(cur);
+
+    // Set debug channel baud rate if different
+#if (CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD != CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_BAUD)
+    lpc17xx_ser_channels[CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL]->baud_rate =
+        CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_BAUD;
+    update_baud_rate(&lpc17xx_ser_channels
+                     [CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL]);
+#endif
+
+}
+
+void
+cyg_hal_plf_comms_init(void)
+{
+    static int      initialized = 0;
+
+    if (initialized)
+        return;
+
+    initialized = 1;
+
+    hal_plf_serial_init();
+}
+
+#endif // CYGSEM_HAL_VIRTUAL_VECTOR_DIAG
+
+//=============================================================================
+// Non-Virtual vector HAL diagnostics
+
+#if !defined(CYGSEM_HAL_VIRTUAL_VECTOR_DIAG)
+
+void
+hal_plf_diag_init(void)
+{
+    hal_plf_serial_init(&lpc17xx_ser_channels
+                        [CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL]);
+}
+
+void
+hal_plf_diag_putc(char c)
+{
+    hal_plf_serial_putc(&lpc17xx_ser_channels
+                        [CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL], c);
+}
+
+cyg_uint8
+hal_plf_diag_getc(void)
+{
+    return
+        hal_plf_serial_getc(&lpc17xx_ser_channels
+                            [CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL]);
+}
+
+#endif // if !defined(CYGSEM_HAL_VIRTUAL_VECTOR_DIAG)
+
+//-----------------------------------------------------------------------------
+// End of hal_diag.c
diff --git a/ecos/packages/hal/cortexm/lpc17xx/var/current/src/lpc17xx_misc.c b/ecos/packages/hal/cortexm/lpc17xx/var/current/src/lpc17xx_misc.c
new file mode 100644
index 0000000..bb31257
--- /dev/null
+++ b/ecos/packages/hal/cortexm/lpc17xx/var/current/src/lpc17xx_misc.c
@@ -0,0 +1,430 @@
+//==========================================================================
+//
+//      lpc17xx_misc.c
+//
+//      Cortex-M LPC17XX HAL functions
+//
+//==========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####                                            
+// -------------------------------------------                              
+// This file is part of eCos, the Embedded Configurable Operating System.   
+// Copyright (C) 2010 Free Software Foundation, Inc.                        
+//
+// eCos is free software; you can redistribute it and/or modify it under    
+// the terms of the GNU General Public License as published by the Free     
+// Software Foundation; either version 2 or (at your option) any later      
+// version.                                                                 
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT      
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
+// for more details.                                                        
+//
+// You should have received a copy of the GNU General Public License        
+// along with eCos; if not, write to the Free Software Foundation, Inc.,    
+// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
+//
+// As a special exception, if other files instantiate templates or use      
+// macros or inline functions from this file, or you compile this file      
+// and link it with other works to produce a work based on this file,       
+// this file does not by itself cause the resulting work to be covered by   
+// the GNU General Public License. However the source code for this file    
+// must still be made available in accordance with section (3) of the GNU   
+// General Public License v2.                                               
+//
+// This exception does not invalidate any other reasons why a work based    
+// on this file might be covered by the GNU General Public License.         
+// -------------------------------------------                              
+// ####ECOSGPLCOPYRIGHTEND####                                              
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):    nickg, ilijak
+// Date:         2010-12-12
+// Description:  
+//
+//####DESCRIPTIONEND####
+//
+//========================================================================
+
+
+#include <pkgconf/hal.h>
+#include <pkgconf/hal_cortexm.h>
+#include <pkgconf/hal_cortexm_lpc17xx.h>
+#ifdef CYGPKG_KERNEL
+# include <pkgconf/kernel.h>
+#endif
+
+#include <cyg/infra/diag.h>
+#include <cyg/infra/cyg_type.h>
+#include <cyg/infra/cyg_trac.h>        // tracing macros
+#include <cyg/infra/cyg_ass.h>         // assertion macros
+
+#include <cyg/hal/hal_arch.h>          // HAL header
+#include <cyg/hal/hal_intr.h>          // HAL header
+#include <cyg/hal/hal_if.h>            // HAL header
+
+#include <cyg/hal/lpc17xx_misc.h>
+
+
+//===========================================================================
+//                               DEFINES
+//===========================================================================
+
+cyg_uint32      hal_lpc17xx_sysclk;
+cyg_uint32      hal_cortexm_systick_clock;
+
+cyg_uint32      hal_get_lpc_cpu_clock(void);
+
+void            hal_start_clocks(void);
+
+void            hal_lpc_start_main_clock(void);
+void            hal_lpc_start_usb_clock(void);
+#if defined(CYGHWR_HAL_CORTEXM_LPC17XX_CLKOUT)
+void            hal_lpc_clock_out(void);
+#endif
+//==========================================================================
+
+#ifdef CYG_HAL_STARTUP_ROM
+
+//===========================================================================
+// LPC17xx Code Read Protection field field
+//===========================================================================
+
+// Note: LPC17xx Code Read Protection field field must be present in
+//       LPC17xx flash image and ocupy a word at 0x000002FC
+
+// For ".lpc17xx_crp" section definition see MLT files.
+
+const cyg_uint32 LPC17XX_CRP __attribute__((section(".lpc17xxcrp"), used)) = 0xFFFFFFFF;
+
+#endif // CYG_HAL_STARTUP_ROM
+
+const cyg_uint32* hal_lpc17xx_crp_p(void)
+{
+    return &LPC17XX_CRP;
+}
+
+void
+hal_variant_init(void)
+{
+#if 1                                  /* !defined(CYG_HAL_STARTUP_RAM) */
+    hal_start_clocks();
+#endif
+
+#ifdef CYGSEM_HAL_VIRTUAL_VECTOR_SUPPORT
+    hal_if_init();
+#endif
+}
+
+//==========================================================================
+// Setup up system clocks
+//
+// Set up clocks from configuration. In the future this should be extended so
+// that clock rates can be changed at runtime.
+
+
+void CYGOPT_HAL_LPC17XX_MISC_FLASH_SECTION_ATTR
+hal_start_clocks(void)
+{
+    // Main clock - for everything except USB
+    hal_lpc_start_main_clock();
+
+    // USB clock
+    hal_lpc_start_usb_clock();
+
+#if defined CYGHWR_HAL_CORTEXM_LPC17XX_CLKOUT
+    hal_lpc_clock_out();
+#endif
+}
+
+
+void CYGOPT_HAL_LPC17XX_MISC_FLASH_SECTION_ATTR
+hal_lpc_start_main_clock(void)
+{
+    CYG_ADDRESS     scb_base_p;
+    cyg_uint32      regval;
+
+    scb_base_p = CYGHWR_HAL_LPC17XX_REG_SCB_BASE;
+
+    HAL_READ_UINT32(scb_base_p + CYGHWR_HAL_LPC17XX_REG_PLL0STAT, regval);
+    if (regval & CYGHWR_HAL_LPC17XX_REG_PLL0STAT_PLLC) {
+
+        // Enable PLL, disconnected
+        HAL_WRITE_UINT32(scb_base_p + CYGHWR_HAL_LPC17XX_REG_PLL0CON,
+                         CYGHWR_HAL_LPC17XX_REG_PLLCON_PLLE);
+        HAL_WRITE_UINT32(scb_base_p + CYGHWR_HAL_LPC17XX_REG_PLL0FEED, 0xaa);
+        HAL_WRITE_UINT32(scb_base_p + CYGHWR_HAL_LPC17XX_REG_PLL0FEED, 0x55);
+    }
+    // Disable PLL, disconnected
+    HAL_WRITE_UINT32(scb_base_p + CYGHWR_HAL_LPC17XX_REG_PLL0CON, 0x00);
+    HAL_WRITE_UINT32(scb_base_p + CYGHWR_HAL_LPC17XX_REG_PLL0FEED, 0xaa);
+    HAL_WRITE_UINT32(scb_base_p + CYGHWR_HAL_LPC17XX_REG_PLL0FEED, 0x55);
+
+    // Enables main oscillator and wait until it is usable
+    HAL_WRITE_UINT32(scb_base_p + CYGHWR_HAL_LPC17XX_REG_SCS,
+                     CYGHWR_HAL_LPC17XX_REG_SCS_OSCEN);
+    do {
+        HAL_READ_UINT32(scb_base_p + CYGHWR_HAL_LPC17XX_REG_SCS, regval);
+    } while (!(regval & CYGHWR_HAL_LPC17XX_REG_SCS_OSCSTAT));
+
+
+    // Select main OSC, 12MHz, as the PLL clock source
+    HAL_WRITE_UINT32(scb_base_p + CYGHWR_HAL_LPC17XX_REG_CLKSRCSEL,
+                     CYGHWR_HAL_LPC17XX_REG_CLKSRCSEL_MAIN);
+
+    // Configure PLL multiplier and pre divider according to configuration
+    // values
+    regval = ((CYGHWR_HAL_CORTEXM_LPC17XX_PLL0_MUL - 1) |
+              (CYGHWR_HAL_CORTEXM_LPC17XX_PLL0_DIV - 1) << 16);
+    HAL_WRITE_UINT32(scb_base_p + CYGHWR_HAL_LPC17XX_REG_PLL0CFG, regval);
+    HAL_WRITE_UINT32(scb_base_p + CYGHWR_HAL_LPC17XX_REG_PLL0FEED, 0xaa);
+    HAL_WRITE_UINT32(scb_base_p + CYGHWR_HAL_LPC17XX_REG_PLL0FEED, 0x55);
+
+    // Enable PLL, disconnected
+    HAL_WRITE_UINT32(scb_base_p + CYGHWR_HAL_LPC17XX_REG_PLL0CON,
+                     CYGHWR_HAL_LPC17XX_REG_PLLCON_PLLE);
+    HAL_WRITE_UINT32(scb_base_p + CYGHWR_HAL_LPC17XX_REG_PLL0FEED, 0xaa);
+    HAL_WRITE_UINT32(scb_base_p + CYGHWR_HAL_LPC17XX_REG_PLL0FEED, 0x55);
+
+    // Set CPU clock divider
+    regval = CYGHWR_HAL_CORTEXM_LPC17XX_CPU_CLK_DIV - 1;
+    HAL_WRITE_UINT32(scb_base_p + CYGHWR_HAL_LPC17XX_REG_CCLKCFG, regval);
+
+    // Check lock bit status
+    do {
+        HAL_READ_UINT32(scb_base_p + CYGHWR_HAL_LPC17XX_REG_PLL0STAT, regval);
+    } while (!(regval & CYGHWR_HAL_LPC17XX_REG_PLL0STAT_PLOCK));
+
+    // Connect CPU clock
+    HAL_WRITE_UINT32(scb_base_p + CYGHWR_HAL_LPC17XX_REG_PLL0CON,
+                     CYGHWR_HAL_LPC17XX_REG_PLLCON_PLLE |
+                     CYGHWR_HAL_LPC17XX_REG_PLLCON_PLLC);
+    HAL_WRITE_UINT32(scb_base_p + CYGHWR_HAL_LPC17XX_REG_PLL0FEED, 0xaa);
+    HAL_WRITE_UINT32(scb_base_p + CYGHWR_HAL_LPC17XX_REG_PLL0FEED, 0x55);
+
+    // Check connect bit status
+    do {
+        HAL_READ_UINT32(scb_base_p + CYGHWR_HAL_LPC17XX_REG_PLL0STAT, regval);
+    } while (!(regval & CYGHWR_HAL_LPC17XX_REG_PLL0STAT_PLLC));
+
+    // Calculate system clock from configuration
+    hal_lpc17xx_sysclk = CYGHWR_HAL_CORTEXM_LPC17XX_CLOCK_SPEED;
+    hal_cortexm_systick_clock = hal_lpc17xx_sysclk;
+}
+
+void CYGOPT_HAL_LPC17XX_MISC_FLASH_SECTION_ATTR
+hal_lpc_start_usb_clock(void)
+{
+    CYG_ADDRESS     scb_base_p;
+    cyg_uint32      regval;
+
+    scb_base_p = CYGHWR_HAL_LPC17XX_REG_SCB_BASE;
+
+    // Configure PLL multiplier and pre divider according to
+    // configuration values
+    regval = ((CYGHWR_HAL_CORTEXM_LPC17XX_PLL1_MUL - 1) |
+              (CYGHWR_HAL_CORTEXM_LPC17XX_PLL1_DIV - 1) << 5);
+    HAL_WRITE_UINT32(scb_base_p + CYGHWR_HAL_LPC17XX_REG_PLL1CFG, regval);
+    HAL_WRITE_UINT32(scb_base_p + CYGHWR_HAL_LPC17XX_REG_PLL1FEED, 0xaa);
+    HAL_WRITE_UINT32(scb_base_p + CYGHWR_HAL_LPC17XX_REG_PLL1FEED, 0x55);
+
+    // Enable PLL, disconnected
+    HAL_WRITE_UINT32(scb_base_p + CYGHWR_HAL_LPC17XX_REG_PLL1CON,
+                     CYGHWR_HAL_LPC17XX_REG_PLLCON_PLLE);
+    HAL_WRITE_UINT32(scb_base_p + CYGHWR_HAL_LPC17XX_REG_PLL1FEED, 0xaa);
+    HAL_WRITE_UINT32(scb_base_p + CYGHWR_HAL_LPC17XX_REG_PLL1FEED, 0x55);
+
+    do {
+        HAL_READ_UINT32(scb_base_p + CYGHWR_HAL_LPC17XX_REG_PLL1STAT, regval);
+    } while (!(regval & CYGHWR_HAL_LPC17XX_REG_PLL1STAT_PLOCK));
+
+    // Connect USB clock
+    HAL_WRITE_UINT32(scb_base_p + CYGHWR_HAL_LPC17XX_REG_PLL1CON,
+                     CYGHWR_HAL_LPC17XX_REG_PLLCON_PLLE |
+                     CYGHWR_HAL_LPC17XX_REG_PLLCON_PLLC);
+    HAL_WRITE_UINT32(scb_base_p + CYGHWR_HAL_LPC17XX_REG_PLL1FEED, 0xaa);
+    HAL_WRITE_UINT32(scb_base_p + CYGHWR_HAL_LPC17XX_REG_PLL1FEED, 0x55);
+
+    // Check connect bit status
+    do {
+        HAL_READ_UINT32(scb_base_p + CYGHWR_HAL_LPC17XX_REG_PLL1STAT, regval);
+    } while (!(regval & CYGHWR_HAL_LPC17XX_REG_PLL1STAT_PLLC));
+}
+
+#ifdef CYGHWR_HAL_CORTEXM_LPC17XX_CLKOUT
+void CYGOPT_HAL_LPC17XX_MISC_FLASH_SECTION_ATTR
+hal_lpc_clock_out(void)
+{
+    cyg_uint32      regval;
+
+    CYGHWR_HAL_LPC17XX_PIN_GET(CYGHWR_HAL_LPC17XX_REG_PINSEL3, regval);
+    regval &= ~0x00c00000;
+    regval |= 0x00400000;
+    CYGHWR_HAL_LPC17XX_PIN_SET(CYGHWR_HAL_LPC17XX_REG_PINSEL3, regval);
+
+    HAL_WRITE_UINT32(CYGHWR_HAL_LPC17XX_REG_SCB_BASE +
+                     CYGHWR_HAL_LPC17XX_REG_CLKOUTCFG,
+                     CYGHWR_HAL_CORTEXM_LPC17XX_CLKOUT_SET);
+}
+#endif // CYGHWR_HAL_CORTEXM_LPC17XX_CLKOUT
+
+
+cyg_uint32
+hal_lpc_get_cpu_clock(void)
+{
+    cyg_uint32      regval,
+                    pll0stat_div,
+                    pll0stat_mul,
+                    cclkcfg;
+
+    HAL_READ_UINT32(CYGHWR_HAL_LPC17XX_REG_SCB_BASE +
+                    CYGHWR_HAL_LPC17XX_REG_PLL0STAT, pll0stat_div);
+    pll0stat_mul = ((pll0stat_div >> 16) & 0xff) + 1;
+    pll0stat_div = 2 * ((pll0stat_div & 0x7fff) + 1);
+    HAL_READ_UINT32(CYGHWR_HAL_LPC17XX_REG_SCB_BASE +
+                    CYGHWR_HAL_LPC17XX_REG_CCLKCFG, cclkcfg);
+    cclkcfg = (cclkcfg & 0xff) + 1;
+
+    regval =
+        CYGHWR_HAL_CORTEXM_LPC17XX_XTAL_FREQ * pll0stat_div / pll0stat_mul /
+        cclkcfg;
+
+    return regval;
+}
+
+
+//===========================================================================
+// Get peripheral clock for a certain peripheral
+//===========================================================================
+cyg_uint32
+hal_lpc_get_pclk(cyg_uint32 pclk_id)
+{
+    static const cyg_uint8 divider_tbl[4] = {
+        4, 1, 2, 8
+    };
+    cyg_uint32      pclkselreg;
+    cyg_uint32      regval;
+    cyg_uint8       divider;
+
+    CYG_ASSERT(pclk_id >= CYNUM_HAL_LPC17XX_PCLK_WDT &&
+               pclk_id <= CYNUM_HAL_LPC17XX_PCLK_SYSCON,
+               "Invalid peripheral clock ID");
+
+    // Decide if we need PCLKSEL0 or PCLKSEL1
+    pclkselreg = ((pclk_id <= CYNUM_HAL_LPC17XX_PCLK_ACF) ?
+                  CYGHWR_HAL_LPC17XX_REG_PCLKSEL0 :
+                  CYGHWR_HAL_LPC17XX_REG_PCLKSEL1);
+    HAL_READ_UINT32(CYGHWR_HAL_LPC17XX_REG_SCB_BASE + pclkselreg, regval);
+    regval = (regval >> ((pclk_id & 0xF) << 1)) & 0x03;
+    divider = divider_tbl[regval];
+    if ((8 == divider) && (pclk_id >= CYNUM_HAL_LPC17XX_PCLK_CAN1)
+        && (pclk_id <= CYNUM_HAL_LPC17XX_PCLK_ACF)) {
+        divider = 6;
+    }
+    return CYGHWR_HAL_CORTEXM_LPC17XX_CLOCK_SPEED / divider;
+}
+
+
+//===========================================================================
+// Set peripheral clock
+//===========================================================================
+void
+hal_lpc_set_pclk(cyg_uint32 peripheral_id, cyg_uint8 divider)
+{
+    static const cyg_uint8 clock_tbl[5] = {
+        0x01,                          // divider 1
+        0x02,                          // divider 2
+        0x00,                          // divider 4
+        0x03,                          // divider 6
+        0x03                           // divider 8
+    };
+    cyg_uint32      clock;
+    cyg_uint32      pclkselreg;
+    cyg_uint32      regval;
+
+    CYG_ASSERT(peripheral_id >= CYNUM_HAL_LPC17XX_PCLK_WDT &&
+               peripheral_id <= CYNUM_HAL_LPC17XX_PCLK_SYSCON,
+               "Invalid peripheral clock ID");
+    CYG_ASSERT(divider <= 8, "Wrong peripheral clock divider value");
+
+    // Decide if we need PCLKSEL0 or PCLKSEL1
+    pclkselreg = (peripheral_id <= CYNUM_HAL_LPC17XX_PCLK_ACF) ?
+        CYGHWR_HAL_LPC17XX_REG_PCLKSEL0 : CYGHWR_HAL_LPC17XX_REG_PCLKSEL1;
+    HAL_READ_UINT32(CYGHWR_HAL_LPC17XX_REG_SCB_BASE + pclkselreg, regval);
+    clock = clock_tbl[divider >> 1];
+    regval &= ~(0x03 << ((peripheral_id & 0xF) << 1));
+    regval |= (clock << ((peripheral_id & 0xF) << 1));
+    HAL_WRITE_UINT32(CYGHWR_HAL_LPC17XX_REG_SCB_BASE + pclkselreg, regval);
+}
+
+
+//===========================================================================
+// Set pin function
+//===========================================================================
+void
+hal_lpc_set_pin_function(cyg_uint8 port, cyg_uint8 pin, cyg_uint8 function)
+{
+    cyg_uint32      regval;
+    cyg_uint8       pinsel_reg = port << 1;
+
+    CYG_ASSERT(port <= 4, "Port value out of bounds");
+    CYG_ASSERT(pin <= 31, "Pin value out of bounds");
+    CYG_ASSERT(function <= 3, "Invalid function value");
+
+    pinsel_reg += (pin > 15) ? 1 : 0;
+    pinsel_reg <<= 2;
+    HAL_READ_UINT32(CYGHWR_HAL_LPC17XX_REG_PIN_BASE + pinsel_reg, regval);
+    regval &= ~(0x03 << ((pin & 0xF) << 1));
+    regval |= (function << ((pin & 0xF) << 1));
+    HAL_WRITE_UINT32(CYGHWR_HAL_LPC17XX_REG_PIN_BASE + pinsel_reg, regval);
+}
+
+//===========================================================================
+// Enable/Disable power for certain peripheral
+//===========================================================================
+void
+hal_lpc_set_power(cyg_uint8 pconp_id, int on)
+{
+    cyg_uint32      regval;
+
+    CYG_ASSERT(pconp_id >= CYNUM_HAL_LPC17XX_PCONP_TIMER0 &&
+               pconp_id <= CYNUM_HAL_LPC17XX_PCONP_USB,
+               "Invalid peripheral power ID");
+    HAL_READ_UINT32(CYGHWR_HAL_LPC17XX_REG_SCB_BASE +
+                    CYGHWR_HAL_LPC17XX_REG_PCONP, regval);
+    if (on) {
+        regval |= (0x01 << pconp_id);
+    } else {
+        regval &= ~(0x01 << pconp_id);
+    }
+
+    HAL_WRITE_UINT32(CYGHWR_HAL_LPC17XX_REG_SCB_BASE +
+                     CYGHWR_HAL_LPC17XX_REG_PCONP, regval);
+}
+
+
+//==========================================================================
+// UART baud rate
+//
+// Set the baud rate divider of a UART based on the requested rate and
+// the current APB clock settings.
+
+void
+hal_plf_uart_setbaud(cyg_uint32 base, cyg_uint32 baud)
+{
+    cyg_uint32      periph_id = CYNUM_HAL_LPC17XX_PCLK_UART0;
+    cyg_uint16      divider;
+
+    if (CYGHWR_HAL_LPC17XX_REG_UART1_BASE == base)
+        periph_id = CYNUM_HAL_LPC17XX_PCLK_UART1;
+    divider = CYG_HAL_CORTEXM_LPC17XX_BAUD_GENERATOR(periph_id, baud);
+    // Set baudrate
+    HAL_WRITE_UINT32(base + CYGHWR_HAL_LPC17XX_REG_UxLCR,
+                     CYGHWR_HAL_LPC17XX_REG_UxLCR_DLAB);
+    HAL_WRITE_UINT32(base + CYGHWR_HAL_LPC17XX_REG_UxDLM, divider >> 8);
+    HAL_WRITE_UINT32(base + CYGHWR_HAL_LPC17XX_REG_UxDLL, divider & 0xFF);
+}
+
+//==========================================================================
+// EOF lpc17xx_misc.c