diff options
| author | Michael Gielda <mgielda@antmicro.com> | 2014-04-03 14:53:04 +0200 |
|---|---|---|
| committer | Michael Gielda <mgielda@antmicro.com> | 2014-04-03 14:53:04 +0200 |
| commit | ae1e4e08a1005a0c487f03ba189d7536e7fdcba6 (patch) | |
| tree | f1c296f8a966a9a39876b0e98e16d9c5da1776dd /ecos/packages/hal/cortexm/stm32 | |
| parent | f157da5337118d3c5cd464266796de4262ac9dbd (diff) | |
Added the OS files
Diffstat (limited to 'ecos/packages/hal/cortexm/stm32')
72 files changed, 12140 insertions, 0 deletions
diff --git a/ecos/packages/hal/cortexm/stm32/stm3210e_eval/current/ChangeLog b/ecos/packages/hal/cortexm/stm32/stm3210e_eval/current/ChangeLog new file mode 100644 index 0000000..3e7d64d --- /dev/null +++ b/ecos/packages/hal/cortexm/stm32/stm3210e_eval/current/ChangeLog @@ -0,0 +1,170 @@ +2012-04-20 Ilija Stanislevik <ilijas@siva.mk> + + * src/stm3210e_eval_eth_enc424j600.c: New file, initialization + of optional enc424j600 ethernet over SPI. + + * include/plf_io.h: Add macro for initialization of optional + enc424j600 ethernet over SPI. + + * cdl/hal_cortexm_stm32_stm3210e_eval.cdl: Add component + enc424j600 ethernet over SPI. + +2012-03-23 James Smith <jsmith@ecoscentric.com> + + * include/plf_io.h: Update GPIO pin definitions to use new PIN + wrapper macros. Update to use common SPEED_SPI name for SPI pin + speed selection. + +2012-02-29 James Smith <jsmith@ecoscentric.com> + + * src/stm3210e_eval_flash.c: Flash structure needs to be "const" + to match header. + +2012-01-12 Nick Garnett <nickg@ecoscentric.com> + + * include/plf_io.h: Add SPI and I2C pin and DMA definitions. + +2011-12-20 Jonathan Larmour <jifl@eCosCentric.com> + + * cdl/hal_cortexm_stm32_stm3210e_eval.cdl: Just set a requires on + RedBoot's number of memory segments to be 2 rather than using a + non-configurable option. + +2011-12-08 Jonathan Larmour <jifl@eCosCentric.com> + + * cdl/hal_cortexm_stm32_stm3210e_eval.cdl: Indicate to new STM32 variant + HAL CDL that this is an F103ZE processor. + +2011-01-27 Nick Garnett <nickg@ecoscentric.com> + + * misc/redboot_JTAG.ecm: + * misc/redboot_ROM.ecm: Define CYGNUM_REDBOOT_FLASH_RESERVED_DEVICES + to take on-chip flash out of FIS control. + +2011-01-01 Jonathan Larmour <jifl@eCosCentric.com> + + * cdl/hal_cortexm_stm32_stm3210e_eval.cdl + (CYGHWR_HAL_CORTEXM_STM32_FLASH): Should be on by default if generic flash + active in configuration. + +2010-08-29 John Dallaway <john@dallaway.org.uk> + + * misc/redboot_JTAG.ecm, misc/redbooot_ROM.ecm: + Inhibit the FIS directory entry for RedBoot and management of the + internal flash. Issues reported by Carlo Caione. + +2009-11-09 Ross Younger <wry@ecoscentric.com> + + * cdl/hal_cortexm_stm32_stm3210e_eval.cdl: Add + CYGPKG_HAL_CORTEXM_STM32_STM3210E_EVAL_CFLAGS_{ADD,REMOVE}, + default to -Werror. + +2009-07-02 Nick Garnett <nickg@ecoscentric.com> + + * src/stm3210e_eval_misc.c (hal_system_init): Adjust clock enables + in line with changes to bit definitions. + +2009-02-04 Nick Garnett <nickg@ecoscentric.com> + + * include/pkgconf/mlt_cortexm_stm3210e_eval_rom.ldi: + * include/pkgconf/mlt_cortexm_stm3210e_eval_ram.ldi: + * include/pkgconf/mlt_cortexm_stm3210e_eval_jtag.ldi: + * include/pkgconf/mlt_cortexm_stm3210e_eval_sram.ldi: + Add .sram section to linker scripts. + +2009-02-07 Chris Holgate <chris@zynaptic.com> + + * include/pkgconf/mlt_cortexm_stm3210e_eval_rom.ldi: + Modified SRAM section so that initialisation data is placed in ROM. + +2009-01-31 Bart Veer <bartv@ecoscentric.com> + + * cdl/hal_cortexm_stm32_stm3210e_eval.cdl: update compiler flags for gcc 4.x + +2008-12-10 Nick Garnett <nickg@ecoscentric.com> + + * cdl/hal_cortexm_stm32_stm3210e_eval.cdl: Switch value for + CYGHWR_MEMORY_LAYOUT to calculated, so that changes to startup + type are correctly propagated. + +2008-11-20 Jonathan Larmour <jifl@eCosCentric.com> + + * cdl/hal_cortexm_stm32_stm3210e_eval.cdl: Remove doc link + to doc that doesn't exist. + +2008-11-19 Nick Garnett <nickg@ecoscentric.com> + + * include/pkgconf/mlt_cortexm_stm3210e_eval_ram.ldi (hal_startup_stack): + Adjust initial stack to top of external SRAM. + +2008-10-28 Nick Garnett <nickg@ecoscentric.com> + + * include/pkgconf/mlt_cortexm_stm3210e_eval_rom.ldi: + * include/pkgconf/mlt_cortexm_stm3210e_eval_rom.h: + * include/pkgconf/mlt_cortexm_stm3210e_eval_ram.ldi: + * include/pkgconf/mlt_cortexm_stm3210e_eval_ram.h: + * include/pkgconf/mlt_cortexm_stm3210e_eval_jtag.ldi: + * include/pkgconf/mlt_cortexm_stm3210e_eval_jtag.h: + * include/pkgconf/mlt_cortexm_stm3210e_eval_sram.ldi: + * include/pkgconf/mlt_cortexm_stm3210e_eval_sram.h: Adjust top of + RAM to 1MB. + +2008-10-10 Nick Garnett <nickg@ecoscentric.com> + + * include/pkgconf/mlt_cortexm_stm3210e_eval_rom.ldi: + * include/pkgconf/mlt_cortexm_stm3210e_eval_rom.h: + * include/pkgconf/mlt_cortexm_stm3210e_eval_ram.ldi: + * include/pkgconf/mlt_cortexm_stm3210e_eval_ram.h: + * include/pkgconf/mlt_cortexm_stm3210e_eval_jtag.ldi: + * include/pkgconf/mlt_cortexm_stm3210e_eval_jtag.h: + * include/pkgconf/mlt_cortexm_stm3210e_eval_sram.ldi: + * include/pkgconf/mlt_cortexm_stm3210e_eval_sram.h: + Update RAM/SRAM upper limits to account for interrupt/init + stack. + + * src/stm3210e_eval_flash.c: Use generic null functions for + external flash lock operations. + +2008-10-06 Nick Garnett <nickg@ecoscentric.com> + + * cdl/hal_cortexm_stm32_stm3210e_eval.cdl: + * include/plf_arch.h: + * include/plf_intr.h: + * include/plf_io.h: + * src/stm3210e_eval_misc.c: + * src/stm3210e_eval_flash.c: + * misc/redboot_ROM.ecm: + * misc/redboot_JTAG.ecm: + * include/pkgconf/mlt_cortexm_stm3210e_eval_rom.ldi: + * include/pkgconf/mlt_cortexm_stm3210e_eval_rom.h: + * include/pkgconf/mlt_cortexm_stm3210e_eval_ram.ldi: + * include/pkgconf/mlt_cortexm_stm3210e_eval_ram.h: + * include/pkgconf/mlt_cortexm_stm3210e_eval_jtag.ldi: + * include/pkgconf/mlt_cortexm_stm3210e_eval_jtag.h: + * include/pkgconf/mlt_cortexm_stm3210e_eval_sram.ldi: + * include/pkgconf/mlt_cortexm_stm3210e_eval_sram.h: + New package -- ST STM3210E EVAL board HAL. + +//=========================================================================== +// ####GPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2008, 2009, 2010 Free Software Foundation, Inc. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 or (at your option) any +// later version. +// +// This program is distributed in the hope that it will be useful, but +// WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +// General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the +// Free Software Foundation, Inc., 51 Franklin Street, +// Fifth Floor, Boston, MA 02110-1301, USA. +// ------------------------------------------- +// ####GPLCOPYRIGHTEND#### +//=========================================================================== diff --git a/ecos/packages/hal/cortexm/stm32/stm3210e_eval/current/cdl/hal_cortexm_stm32_stm3210e_eval.cdl b/ecos/packages/hal/cortexm/stm32/stm3210e_eval/current/cdl/hal_cortexm_stm32_stm3210e_eval.cdl new file mode 100644 index 0000000..103c61d --- /dev/null +++ b/ecos/packages/hal/cortexm/stm32/stm3210e_eval/current/cdl/hal_cortexm_stm32_stm3210e_eval.cdl @@ -0,0 +1,485 @@ +##========================================================================== +## +## hal_cortexm_stm32_stm3210e_eval.cdl +## +## Cortex-M STM3210E EVAL platform HAL configuration data +## +##========================================================================== +## ####ECOSGPLCOPYRIGHTBEGIN#### +## ------------------------------------------- +## This file is part of eCos, the Embedded Configurable Operating System. +## Copyright (C) 2008, 2012 Free Software Foundation, Inc. +## +## eCos is free software; you can redistribute it and/or modify it under +## the terms of the GNU General Public License as published by the Free +## Software Foundation; either version 2 or (at your option) any later +## version. +## +## eCos is distributed in the hope that it will be useful, but WITHOUT +## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +## for more details. +## +## You should have received a copy of the GNU General Public License +## along with eCos; if not, write to the Free Software Foundation, Inc., +## 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +## +## As a special exception, if other files instantiate templates or use +## macros or inline functions from this file, or you compile this file +## and link it with other works to produce a work based on this file, +## this file does not by itself cause the resulting work to be covered by +## the GNU General Public License. However the source code for this file +## must still be made available in accordance with section (3) of the GNU +## General Public License v2. +## +## This exception does not invalidate any other reasons why a work based +## on this file might be covered by the GNU General Public License. +## ------------------------------------------- +## ####ECOSGPLCOPYRIGHTEND#### +##========================================================================== +#######DESCRIPTIONBEGIN#### +## +## Author(s): nickg +## Date: 2008-07-30 +## +######DESCRIPTIONEND#### +## +##========================================================================== + +cdl_package CYGPKG_HAL_CORTEXM_STM32_STM3210E_EVAL { + display "ST STM3210E EVAL Development Board HAL" + parent CYGPKG_HAL_CORTEXM_STM32 + requires { CYGHWR_HAL_CORTEXM_STM32_FAMILY == "F1" } + requires { CYGHWR_HAL_CORTEXM_STM32_F1 == "F103ZE" } + define_header hal_cortexm_stm32_stm3210e_eval.h + include_dir cyg/hal + hardware + description " + The STM3210E EVAL HAL package provides the support needed to run + eCos on the ST STM3210E EVAL board." + + compile stm3210e_eval_misc.c + + define_proc { + puts $::cdl_system_header "#define CYGBLD_HAL_TARGET_H <pkgconf/hal_cortexm.h>" + puts $::cdl_system_header "#define CYGBLD_HAL_VARIANT_H <pkgconf/hal_cortexm_stm32.h>" + puts $::cdl_system_header "#define CYGBLD_HAL_PLATFORM_H <pkgconf/hal_cortexm_stm32_stm3210e_eval.h>" + puts $::cdl_header "#define HAL_PLATFORM_CPU \"Cortex-M3\"" + puts $::cdl_header "#define HAL_PLATFORM_BOARD \"ST STM3210E EVAL\"" + puts $::cdl_header "#define HAL_PLATFORM_EXTRA \"\"" + } + + cdl_component CYG_HAL_STARTUP { + display "Startup type" + flavor data + default_value {"RAM"} + legal_values {"RAM" "SRAM" "ROM" "JTAG"} + no_define + define -file system.h CYG_HAL_STARTUP + description " + When targetting the ST STM3210E EVAL board it is possible to + build the system for either RAM bootstrap or ROM bootstrap. + Select 'RAM' when building programs to load into RAM using onboard + debug software such as RedBoot or eCos GDB stubs. Select 'ROM' + when building a stand-alone application which will be put + into ROM. The 'JTAG' type allows programs to be downloaded using a + JTAG debugger such as a BDI3000 or PEEDI. The 'SRAM' type allows + programs to be downloaded via a JTAG debugger into on-chip SRAM." + } + + cdl_component CYGHWR_MEMORY_LAYOUT { + display "Memory layout" + flavor data + no_define + calculated { (CYG_HAL_STARTUP == "RAM" ) ? + (CYGMEM_HAL_CORTEXM_STM32_STM3210E_EXTRA_BASE_RAM ? + "cortexm_stm3210e_eval_extrabaseram" : "cortexm_stm3210e_eval_ram") : + (CYG_HAL_STARTUP == "SRAM") ? "cortexm_stm3210e_eval_sram" : + (CYG_HAL_STARTUP == "ROM" ) ? "cortexm_stm3210e_eval_rom" : + (CYG_HAL_STARTUP == "JTAG") ? "cortexm_stm3210e_eval_jtag" : + "undefined" } + + cdl_option CYGMEM_HAL_CORTEXM_STM32_STM3210E_EXTRA_BASE_RAM { + display "Additional reserved space at base of RAM" + flavor booldata + default_value 0 + active_if {CYG_HAL_STARTUP == "RAM"} + legal_values 0 to 0x80000 + description " + If you are using a RedBoot with additional components enabled, + such as networking, RedBoot may be occupying additional RAM. + In such cases, an eCos application loaded by RedBoot must + reserve additional space at the base of RAM to accommodate + RedBoot's extra RAM requirements. This option, specified in + bytes, allows the amount of extra reserved space to be + increased beyond the default." + } + + cdl_option CYGHWR_MEMORY_LAYOUT_LDI { + display "Memory layout linker script fragment" + flavor data + no_define + define -file system.h CYGHWR_MEMORY_LAYOUT_LDI + calculated { "<pkgconf/mlt_" . CYGHWR_MEMORY_LAYOUT . ".ldi>" } + } + + cdl_option CYGHWR_MEMORY_LAYOUT_H { + display "Memory layout header file" + flavor data + no_define + define -file system.h CYGHWR_MEMORY_LAYOUT_H + calculated { "<pkgconf/mlt_" . CYGHWR_MEMORY_LAYOUT . ".h>" } + } + + } + + cdl_option CYGARC_HAL_CORTEXM_STM32_INPUT_CLOCK { + display "Input Clock frequency" + flavor data + default_value 8000000 + legal_values 0 to 1000000000 + description "Main clock input." + } + + cdl_component CYGHWR_HAL_CORTEXM_STM32_FLASH { + display "Flash support" + parent CYGPKG_IO_FLASH + active_if CYGPKG_IO_FLASH + compile -library=libextras.a stm3210e_eval_flash.c + default_value 1 + description "Control flash device support for STM3210E-EVAL board." + + cdl_option CYGHWR_HAL_CORTEXM_STM32_FLASH_INTERNAL { + display "Internal flash support" + default_value 1 + description "This option enables support for the internal flash device." + } + + cdl_option CYGHWR_HAL_CORTEXM_STM32_FLASH_NOR { + display "External NOR flash support" + default_value 1 + description "This option enables support for the external NOR flash device." + } + + } + + # Both UARTs 0 and 1 are available for diagnostic/debug use. + implements CYGINT_HAL_STM32_UART0 + implements CYGINT_HAL_STM32_UART1 + + implements CYGINT_IO_SERIAL_FLOW_CONTROL_HW + implements CYGINT_IO_SERIAL_LINE_STATUS_HW + + + cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS { + display "Number of communication channels on the board" + flavor data + calculated 2 + } + + cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL { + display "Debug serial port" + active_if CYGPRI_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_CONFIGURABLE + flavor data + legal_values 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1 + default_value 0 + description " + The ST STM3210E EVAL board has two serial ports. This option + chooses which port will be used to connect to a host + running GDB." + } + + cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL { + display "Diagnostic serial port" + active_if CYGPRI_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_CONFIGURABLE + flavor data + legal_values 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1 + default_value 0 + description " + The ST STM3210E EVAL has two serial ports. This option + chooses which port will be used for diagnostic output." + } + + cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD { + display "Console serial port baud rate" + flavor data + legal_values 9600 19200 38400 57600 115200 + default_value 38400 + description " + This option controls the default baud rate used for the + console connection. + RedBoot usess polling to transfer data over this port and + might not be able to keep up with baud rates above the + default, particularly when doing XYZmodem downloads. The + interrupt-driven device driver is able to handle these + baud rates, so any high speed application transfers should + use that instead. + Note: this should match the value chosen for the GDB port if the + diagnostic and GDB port are the same." + } + + cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_BAUD { + display "GDB serial port baud rate" + flavor data + legal_values 9600 19200 38400 57600 115200 + default_value 38400 + description " + This option controls the default baud rate used for the + GDB connection. + RedBoot usess polling to transfer data over this port and + might not be able to keep up with baud rates above the + default, particularly when doing XYZmodem downloads. The + interrupt-driven device driver is able to handle these + baud rates, so any high speed application transfers should + use that instead. + Note: this should match the value chosen for the console port if the + console and GDB port are the same." + } + + cdl_component CYGHWR_HAL_CORTEXM_STM32_SPIETH_CONTROLLER { + display "STM3210E support for ENC424J600 SPI ethernet" + parent CYGPKG_DEVS_ETH_ENC424J600 + active_if CYGPKG_DEVS_ETH_ENC424J600 + compile stm3210e_eval_eth_enc424j600.c + flavor none + no_define + + description " + Support for ENC424J600 with STM3210E EVAL board." + + cdl_option CYGNUM_ETH_SPIETH_HAL_INTERRUPT_VECTOR { + display "Interrupt vector calculated from pin" + parent CYGNUM_DEVS_ETH_ENC424J600_INTERRUPT_VECTOR + flavor data + no_define + calculated { "CYGNUM_HAL_INTERRUPT_EXTI" . CYGHWR_HAL_SPIETH_INTERRUPT_PIN } + active_if CYGINT_IO_ETH_INT_SUPPORT_REQUIRED + description " + Interrupt vector corresponding with external interrupt line used for + enc424j600. + This value is automatically calculated from CYGHWR_HAL_SPIETH_INTERRUPT_PIN. + " + } + + cdl_option CYGHWR_HAL_CORTEXM_STM32_SPIETH_SPI_BUS { + display "SPI bus" + flavor data + requires { (CYGHWR_HAL_CORTEXM_STM32_SPIETH_SPI_BUS == 1) implies CYGHWR_DEVS_SPI_CORTEXM_STM32_BUS1 } + requires { (CYGHWR_HAL_CORTEXM_STM32_SPIETH_SPI_BUS == 2) implies CYGHWR_DEVS_SPI_CORTEXM_STM32_BUS2 } + requires { (CYGHWR_HAL_CORTEXM_STM32_SPIETH_SPI_BUS == 3) implies CYGHWR_DEVS_SPI_CORTEXM_STM32_BUS3 } + requires (CYGNUM_DEVS_SPI_CORTEXM_STM32_PIN_TOGGLE_RATE==50) + legal_values { 1 2 3 } + default_value 1 + description " + Select which SPI bus of the STM32 the SPI Ethernet controller + is connected to." + } + + cdl_option CYGHWR_HAL_CORTEXM_STM32_SPIETH_SPI_CS { + display "Chip select index" + flavor data + default_value 0 + legal_values 0 to 99 + description " + Enter the index into the array of chip selects to be used as + the chip select for the external Ethernet + controller connected to the SPI bus. The list of possible chip + selects for the selected SPI bus is defined in the STM32 SPI + driver's configuration, for example for SPI bus 1: + CYGHWR_DEVS_SPI_CORTEXM_STM32_BUS1_CS_GPIOS." + } + + cdl_option CYGHWR_HAL_CORTEXM_STM32_SPIETH_INTERRUPT_PORT { + display "Interrupt pin port" + active_if CYGINT_IO_ETH_INT_SUPPORT_REQUIRED + flavor data + legal_values { "\'A\'" "\'B\'" "\'C\'" "\'D\'" "\'E\'" "\'F\'" "\'G\'" } + default_value {"\'G\'"} + description " + This selects the GPIO port associated with the interrupt pin + connected to the external Ethernet controller." + } + + cdl_option CYGHWR_HAL_SPIETH_INTERRUPT_PIN { + display "Interrupt pin number" + active_if CYGINT_IO_ETH_INT_SUPPORT_REQUIRED + flavor data + legal_values 0 to 15 + default_value 15 + description " + This selects the pin number within the GPIO port associated with + the interrupt pin connected to the external Ethernet controller." + } + + cdl_option CYGNUM_HAL_SPIETH_INTERRUPT_PRIORITY { + display "Interrupt priority" + active_if CYGINT_IO_ETH_INT_SUPPORT_REQUIRED + flavor data + legal_values { 0xe0 0xd0 0xc0 0xb0 0xa0 0x90 0x80 + 0x70 0x60 0x50 0x40 0x30 0x20 0x10 0x00} + default_value 0xe0 + description " + Enter the interrupt priority used for the interrupt + connected to the external Ethernet controller. A + lower number means a higher priority." + } + } + + cdl_component CYGBLD_GLOBAL_OPTIONS { + display "Global build options" + flavor none + parent CYGPKG_NONE + description " + Global build options including control over + compiler flags, linker flags and choice of toolchain." + + + cdl_option CYGBLD_GLOBAL_COMMAND_PREFIX { + display "Global command prefix" + flavor data + no_define + default_value { "arm-eabi" } + description " + This option specifies the command prefix used when + invoking the build tools." + } + + cdl_option CYGBLD_GLOBAL_CFLAGS { + display "Global compiler flags" + flavor data + no_define + default_value { CYGBLD_GLOBAL_WARNFLAGS . "-mcpu=cortex-m3 -mthumb -g -O2 -ffunction-sections -fdata-sections -fno-rtti -fno-exceptions" } + description " + This option controls the global compiler flags which are used to + compile all packages by default. Individual packages may define + options which override these global flags." + } + + cdl_option CYGBLD_GLOBAL_LDFLAGS { + display "Global linker flags" + flavor data + no_define + default_value { "-mcpu=cortex-m3 -mthumb -Wl,--gc-sections -Wl,-static -Wl,-n -g -nostdlib" } + description " + This option controls the global linker flags. Individual + packages may define options which override these global flags." + } + } + + cdl_component CYGPKG_HAL_CORTEXM_STM32_STM3210E_EVAL_OPTIONS { + display "stm3210e HAL build options" + flavor none + description " + Package specific build options including control over + compiler flags used only in building this HAL." + + cdl_option CYGPKG_HAL_CORTEXM_STM32_STM3210E_EVAL_CFLAGS_ADD { + display "Additional compiler flags" + flavor data + no_define + default_value { "-Werror" } + description " + This option modifies the set of compiler flags + for building this HAL. These flags are used + in addition to the set of global flags." + } + cdl_option CYGPKG_HAL_CORTEXM_STM32_STM3210E_EVAL_CFLAGS_REMOVE { + display "Suppressed compiler flags" + flavor data + no_define + default_value { "" } + description " + This option modifies the set of compiler flags + for building this HAL. These flags are + removed from the set of global flags if + present." + } + } + + cdl_option CYGSEM_HAL_ROM_MONITOR { + display "Behave as a ROM monitor" + flavor bool + default_value 0 + parent CYGPKG_HAL_ROM_MONITOR + requires { CYG_HAL_STARTUP == "ROM" || CYG_HAL_STARTUP == "JTAG" } + requires { CYGDBG_HAL_CRCTABLE_LOCATION == "ROM" } + description " + Enable this option if this program is to be used as a ROM monitor, + i.e. applications will be loaded into RAM on the board, and this + ROM monitor may process exceptions or interrupts generated from the + application. This enables features such as utilizing a separate + interrupt stack when exceptions are generated." + } + + cdl_option CYGSEM_HAL_USE_ROM_MONITOR { + display "Work with a ROM monitor" + flavor booldata + legal_values { "Generic" "GDB_stubs" } + default_value { CYG_HAL_STARTUP == "RAM" ? "GDB_stubs" : 0 } + parent CYGPKG_HAL_ROM_MONITOR + requires { CYG_HAL_STARTUP == "RAM" } + description " + Support can be enabled for different varieties of ROM monitor. + This support changes various eCos semantics such as the encoding + of diagnostic output, or the overriding of hardware interrupt + vectors. + Firstly there is \"Generic\" support which prevents the HAL + from overriding the hardware vectors that it does not use, to + instead allow an installed ROM monitor to handle them. This is + the most basic support which is likely to be common to most + implementations of ROM monitor. + \"GDB_stubs\" provides support when GDB stubs are included in + the ROM monitor or boot ROM." + } + + cdl_component CYGPKG_REDBOOT_HAL_OPTIONS { + display "Redboot HAL options" + flavor none + no_define + parent CYGPKG_REDBOOT + active_if CYGPKG_REDBOOT + description " + This option lists the target's requirements for a valid Redboot + configuration." + + requires { CYGNUM_REDBOOT_FLASH_BASE == 0x64000000 } + requires { CYGBLD_REDBOOT_MAX_MEM_SEGMENTS == 2 } + + cdl_option CYGBLD_BUILD_REDBOOT_BIN { + display "Build Redboot ROM binary images" + active_if CYGBLD_BUILD_REDBOOT + default_value 1 + no_define + description "This option enables the conversion of the Redboot ELF + image to binary image formats suitable for ROM programming." + + make -priority 325 { + <PREFIX>/bin/redboot.bin : <PREFIX>/bin/redboot.elf + $(OBJCOPY) --strip-debug $< $(@:.bin=.img) + $(OBJCOPY) -O srec $< $(@:.bin=.srec) + $(OBJCOPY) -O binary $< $@ + } + } + } + + cdl_component CYGBLD_HAL_CORTEXM_STM3210E_EVAL_GDB_STUBS { + display "Create StubROM SREC and binary files" + active_if CYGBLD_BUILD_COMMON_GDB_STUBS + no_define + calculated 1 + requires { CYG_HAL_STARTUP == "ROM" } + + make -priority 325 { + <PREFIX>/bin/stubrom.srec : <PREFIX>/bin/gdb_module.img + $(OBJCOPY) -O srec $< $@ + } + make -priority 325 { + <PREFIX>/bin/stubrom.bin : <PREFIX>/bin/gdb_module.img + $(OBJCOPY) -O binary $< $@ + } + + description "This component causes the ELF image generated by the + build process to be converted to S-Record and binary + files." + } +} diff --git a/ecos/packages/hal/cortexm/stm32/stm3210e_eval/current/include/pkgconf/mlt_cortexm_stm3210e_eval_extrabaseram.h b/ecos/packages/hal/cortexm/stm32/stm3210e_eval/current/include/pkgconf/mlt_cortexm_stm3210e_eval_extrabaseram.h new file mode 100644 index 0000000..cb67af0 --- /dev/null +++ b/ecos/packages/hal/cortexm/stm32/stm3210e_eval/current/include/pkgconf/mlt_cortexm_stm3210e_eval_extrabaseram.h @@ -0,0 +1,21 @@ +// eCos memory layout + +#ifndef __ASSEMBLER__ +#include <cyg/infra/cyg_type.h> +#include <stddef.h> + +#endif +#define CYGMEM_REGION_sram (0x20000000) +#define CYGMEM_REGION_sram_SIZE (0x00010000) +#define CYGMEM_REGION_sram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) + +#define CYGMEM_REGION_ram (0x68000000) +#define CYGMEM_REGION_ram_SIZE (0x00100000-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE) +#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) + +#ifndef __ASSEMBLER__ +extern char CYG_LABEL_NAME (__heap1) []; +#endif +#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1)) +#define CYGMEM_SECTION_heap1_SIZE (CYGMEM_REGION_ram+CYGMEM_REGION_ram_SIZE - (size_t) CYG_LABEL_NAME (__heap1)) + diff --git a/ecos/packages/hal/cortexm/stm32/stm3210e_eval/current/include/pkgconf/mlt_cortexm_stm3210e_eval_extrabaseram.ldi b/ecos/packages/hal/cortexm/stm32/stm3210e_eval/current/include/pkgconf/mlt_cortexm_stm3210e_eval_extrabaseram.ldi new file mode 100644 index 0000000..a1e5775 --- /dev/null +++ b/ecos/packages/hal/cortexm/stm32/stm3210e_eval/current/include/pkgconf/mlt_cortexm_stm3210e_eval_extrabaseram.ldi @@ -0,0 +1,36 @@ +// eCos memory layout + +#include <pkgconf/hal.h> +#include <cyg/infra/cyg_type.inc> + +MEMORY +{ + sram : ORIGIN = 0x20000000, LENGTH = 0x00010000 + flash : ORIGIN = 0x08000000, LENGTH = 0x00080000 + rom : ORIGIN = 0x64000000, LENGTH = 0x01000000 + ram : ORIGIN = 0x68000000, LENGTH = 0x00100000-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE +} + +SECTIONS +{ + SECTIONS_BEGIN + SECTION_sram (sram, 0x20000400, LMA_EQ_VMA) + SECTION_rom_vectors (ram, 0x68008000+CYGMEM_HAL_CORTEXM_STM32_STM3210E_EXTRA_BASE_RAM, LMA_EQ_VMA) + SECTION_RELOCS (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_text (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_fini (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_rodata (ram, ALIGN(0x8), LMA_EQ_VMA) + SECTION_rodata1 (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_fixup (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_gcc_except_table (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_eh_frame (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_got (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_data (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_bss (ram, ALIGN (0x8), LMA_EQ_VMA) + CYG_LABEL_DEFN(__heap1) = ALIGN (0x8); + SECTIONS_END +} + +hal_vsr_table = 0x20000000; +hal_virtual_vector_table = hal_vsr_table + 128*4; +hal_startup_stack = 0x68100000; diff --git a/ecos/packages/hal/cortexm/stm32/stm3210e_eval/current/include/pkgconf/mlt_cortexm_stm3210e_eval_jtag.h b/ecos/packages/hal/cortexm/stm32/stm3210e_eval/current/include/pkgconf/mlt_cortexm_stm3210e_eval_jtag.h new file mode 100644 index 0000000..62aa297 --- /dev/null +++ b/ecos/packages/hal/cortexm/stm32/stm3210e_eval/current/include/pkgconf/mlt_cortexm_stm3210e_eval_jtag.h @@ -0,0 +1,15 @@ +// eCos memory layout + +#ifndef __ASSEMBLER__ +#include <cyg/infra/cyg_type.h> +#include <stddef.h> + +#endif +#define CYGMEM_REGION_ram (0x68000000) +#define CYGMEM_REGION_ram_SIZE (0x00100000) +#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) +#ifndef __ASSEMBLER__ +extern char CYG_LABEL_NAME (__heap1) []; +#endif +#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1)) +#define CYGMEM_SECTION_heap1_SIZE (CYGMEM_REGION_ram+CYGMEM_REGION_ram_SIZE - (size_t) CYG_LABEL_NAME (__heap1)) diff --git a/ecos/packages/hal/cortexm/stm32/stm3210e_eval/current/include/pkgconf/mlt_cortexm_stm3210e_eval_jtag.ldi b/ecos/packages/hal/cortexm/stm32/stm3210e_eval/current/include/pkgconf/mlt_cortexm_stm3210e_eval_jtag.ldi new file mode 100644 index 0000000..d72db27 --- /dev/null +++ b/ecos/packages/hal/cortexm/stm32/stm3210e_eval/current/include/pkgconf/mlt_cortexm_stm3210e_eval_jtag.ldi @@ -0,0 +1,37 @@ +// eCos memory layout + +#include <pkgconf/hal.h> +#include <cyg/infra/cyg_type.inc> + +MEMORY +{ + sram : ORIGIN = 0x20000000, LENGTH = 0x00010000-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE + flash : ORIGIN = 0x08000000, LENGTH = 0x00080000 + rom : ORIGIN = 0x64000000, LENGTH = 0x01000000 + ram : ORIGIN = 0x68000000, LENGTH = 0x00100000 +} + +SECTIONS +{ + SECTIONS_BEGIN + SECTION_sram (sram, 0x20000400, LMA_EQ_VMA) + SECTION_rom_vectors (ram, 0x68000000, LMA_EQ_VMA) + SECTION_RELOCS (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_text (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_fini (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_rodata (ram, ALIGN(0x8), LMA_EQ_VMA) + SECTION_rodata1 (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_fixup (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_gcc_except_table (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_eh_frame (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_got (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_data (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_bss (ram, ALIGN (0x8), LMA_EQ_VMA) + CYG_LABEL_DEFN(__heap1) = ALIGN (0x8); + SECTIONS_END +} + +hal_vsr_table = 0x20000000; +hal_virtual_vector_table = hal_vsr_table + 128*4; +hal_startup_stack = 0x20000000 + 1024*64; + diff --git a/ecos/packages/hal/cortexm/stm32/stm3210e_eval/current/include/pkgconf/mlt_cortexm_stm3210e_eval_ram.h b/ecos/packages/hal/cortexm/stm32/stm3210e_eval/current/include/pkgconf/mlt_cortexm_stm3210e_eval_ram.h new file mode 100644 index 0000000..cb67af0 --- /dev/null +++ b/ecos/packages/hal/cortexm/stm32/stm3210e_eval/current/include/pkgconf/mlt_cortexm_stm3210e_eval_ram.h @@ -0,0 +1,21 @@ +// eCos memory layout + +#ifndef __ASSEMBLER__ +#include <cyg/infra/cyg_type.h> +#include <stddef.h> + +#endif +#define CYGMEM_REGION_sram (0x20000000) +#define CYGMEM_REGION_sram_SIZE (0x00010000) +#define CYGMEM_REGION_sram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) + +#define CYGMEM_REGION_ram (0x68000000) +#define CYGMEM_REGION_ram_SIZE (0x00100000-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE) +#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) + +#ifndef __ASSEMBLER__ +extern char CYG_LABEL_NAME (__heap1) []; +#endif +#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1)) +#define CYGMEM_SECTION_heap1_SIZE (CYGMEM_REGION_ram+CYGMEM_REGION_ram_SIZE - (size_t) CYG_LABEL_NAME (__heap1)) + diff --git a/ecos/packages/hal/cortexm/stm32/stm3210e_eval/current/include/pkgconf/mlt_cortexm_stm3210e_eval_ram.ldi b/ecos/packages/hal/cortexm/stm32/stm3210e_eval/current/include/pkgconf/mlt_cortexm_stm3210e_eval_ram.ldi new file mode 100644 index 0000000..11b1ab9 --- /dev/null +++ b/ecos/packages/hal/cortexm/stm32/stm3210e_eval/current/include/pkgconf/mlt_cortexm_stm3210e_eval_ram.ldi @@ -0,0 +1,36 @@ +// eCos memory layout + +#include <pkgconf/hal.h> +#include <cyg/infra/cyg_type.inc> + +MEMORY +{ + sram : ORIGIN = 0x20000000, LENGTH = 0x00010000 + flash : ORIGIN = 0x08000000, LENGTH = 0x00080000 + rom : ORIGIN = 0x64000000, LENGTH = 0x01000000 + ram : ORIGIN = 0x68000000, LENGTH = 0x00100000-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE +} + +SECTIONS +{ + SECTIONS_BEGIN + SECTION_sram (sram, 0x20000400, LMA_EQ_VMA) + SECTION_rom_vectors (ram, 0x68008000, LMA_EQ_VMA) + SECTION_RELOCS (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_text (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_fini (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_rodata (ram, ALIGN(0x8), LMA_EQ_VMA) + SECTION_rodata1 (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_fixup (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_gcc_except_table (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_eh_frame (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_got (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_data (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_bss (ram, ALIGN (0x8), LMA_EQ_VMA) + CYG_LABEL_DEFN(__heap1) = ALIGN (0x8); + SECTIONS_END +} + +hal_vsr_table = 0x20000000; +hal_virtual_vector_table = hal_vsr_table + 128*4; +hal_startup_stack = 0x68100000; diff --git a/ecos/packages/hal/cortexm/stm32/stm3210e_eval/current/include/pkgconf/mlt_cortexm_stm3210e_eval_rom.h b/ecos/packages/hal/cortexm/stm32/stm3210e_eval/current/include/pkgconf/mlt_cortexm_stm3210e_eval_rom.h new file mode 100644 index 0000000..93f4f59 --- /dev/null +++ b/ecos/packages/hal/cortexm/stm32/stm3210e_eval/current/include/pkgconf/mlt_cortexm_stm3210e_eval_rom.h @@ -0,0 +1,24 @@ +// eCos memory layout + +#ifndef __ASSEMBLER__ +#include <cyg/infra/cyg_type.h> +#include <stddef.h> + +#endif +#define CYGMEM_REGION_sram (0x20000000) +#define CYGMEM_REGION_sram_SIZE (0x00010000-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE) +#define CYGMEM_REGION_sram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) +#define CYGMEM_REGION_flash (0x08000000) +#define CYGMEM_REGION_flash_SIZE (0x00080000) +#define CYGMEM_REGION_flash_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) +#define CYGMEM_REGION_ram (0x68000000) +#define CYGMEM_REGION_ram_SIZE (0x00100000) +#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) +#define CYGMEM_REGION_rom (0x64000000) +#define CYGMEM_REGION_rom_SIZE (0x01000000) +#define CYGMEM_REGION_rom_ATTR (CYGMEM_REGION_ATTR_R) +#ifndef __ASSEMBLER__ +extern char CYG_LABEL_NAME (__heap1) []; +#endif +#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1)) +#define CYGMEM_SECTION_heap1_SIZE (CYGMEM_REGION_ram+CYGMEM_REGION_ram_SIZE - (size_t) CYG_LABEL_NAME (__heap1)) diff --git a/ecos/packages/hal/cortexm/stm32/stm3210e_eval/current/include/pkgconf/mlt_cortexm_stm3210e_eval_rom.ldi b/ecos/packages/hal/cortexm/stm32/stm3210e_eval/current/include/pkgconf/mlt_cortexm_stm3210e_eval_rom.ldi new file mode 100644 index 0000000..0a17ecc --- /dev/null +++ b/ecos/packages/hal/cortexm/stm32/stm3210e_eval/current/include/pkgconf/mlt_cortexm_stm3210e_eval_rom.ldi @@ -0,0 +1,38 @@ +// eCos memory layout + +#include <pkgconf/hal.h> +#include <cyg/infra/cyg_type.inc> + +MEMORY +{ + sram : ORIGIN = 0x20000000, LENGTH = 0x00010000-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE + flash : ORIGIN = 0x08000000, LENGTH = 0x00080000 + rom : ORIGIN = 0x64000000, LENGTH = 0x01000000 + ram : ORIGIN = 0x68000000, LENGTH = 0x00100000 +} + +SECTIONS +{ + SECTIONS_BEGIN + SECTION_rom_vectors (flash, 0x08000000, LMA_EQ_VMA) + SECTION_RELOCS (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_text (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_fini (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_rodata (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_rodata1 (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_fixup (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_gcc_except_table (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_eh_frame (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_got (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_sram (sram, 0x20000400, FOLLOWING (.got)) + SECTION_data (ram, 0x68000000, FOLLOWING (.sram)) + SECTION_bss (ram, ALIGN (0x8), LMA_EQ_VMA) + CYG_LABEL_DEFN(__heap1) = ALIGN (0x8); + SECTIONS_END +} + +hal_vsr_table = 0x20000000; +hal_virtual_vector_table = hal_vsr_table + 128*4; +hal_startup_stack = 0x20000000 + 1024*64; + + diff --git a/ecos/packages/hal/cortexm/stm32/stm3210e_eval/current/include/pkgconf/mlt_cortexm_stm3210e_eval_sram.h b/ecos/packages/hal/cortexm/stm32/stm3210e_eval/current/include/pkgconf/mlt_cortexm_stm3210e_eval_sram.h new file mode 100644 index 0000000..1ed517d --- /dev/null +++ b/ecos/packages/hal/cortexm/stm32/stm3210e_eval/current/include/pkgconf/mlt_cortexm_stm3210e_eval_sram.h @@ -0,0 +1,21 @@ +// eCos memory layout + +#ifndef __ASSEMBLER__ +#include <cyg/infra/cyg_type.h> +#include <stddef.h> + +#endif +#define CYGMEM_REGION_sram (0x20000000) +#define CYGMEM_REGION_sram_SIZE (0x00010000-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE) +#define CYGMEM_REGION_sram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) + +#define CYGMEM_REGION_ram (0x68000000) +#define CYGMEM_REGION_ram_SIZE (0x00100000) +#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) + +#ifndef __ASSEMBLER__ +extern char CYG_LABEL_NAME (__heap1) []; +#endif +#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1)) +#define CYGMEM_SECTION_heap1_SIZE (CYGMEM_REGION_sram+CYGMEM_REGION_sram_SIZE - (size_t) CYG_LABEL_NAME (__heap1)) + diff --git a/ecos/packages/hal/cortexm/stm32/stm3210e_eval/current/include/pkgconf/mlt_cortexm_stm3210e_eval_sram.ldi b/ecos/packages/hal/cortexm/stm32/stm3210e_eval/current/include/pkgconf/mlt_cortexm_stm3210e_eval_sram.ldi new file mode 100644 index 0000000..c533b38 --- /dev/null +++ b/ecos/packages/hal/cortexm/stm32/stm3210e_eval/current/include/pkgconf/mlt_cortexm_stm3210e_eval_sram.ldi @@ -0,0 +1,36 @@ +// eCos memory layout + +#include <pkgconf/hal.h> +#include <cyg/infra/cyg_type.inc> + +MEMORY +{ + sram : ORIGIN = 0x20000000, LENGTH = 0x00010000-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE + flash : ORIGIN = 0x08000000, LENGTH = 0x00080000 + rom : ORIGIN = 0x64000000, LENGTH = 0x01000000 + ram : ORIGIN = 0x68000000, LENGTH = 0x00100000 +} + +SECTIONS +{ + SECTIONS_BEGIN + SECTION_rom_vectors (sram, 0x20000400, LMA_EQ_VMA) + SECTION_RELOCS (sram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_text (sram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_fini (sram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_rodata (sram, ALIGN(0x8), LMA_EQ_VMA) + SECTION_rodata1 (sram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_fixup (sram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_gcc_except_table (sram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_eh_frame (sram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_got (sram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_data (sram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_bss (sram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_sram (sram, ALIGN (0x8), LMA_EQ_VMA) + CYG_LABEL_DEFN(__heap1) = ALIGN (0x8); + SECTIONS_END +} + +hal_vsr_table = 0x20000000; +hal_virtual_vector_table = hal_vsr_table + 128*4; +hal_startup_stack = 0x20010000; diff --git a/ecos/packages/hal/cortexm/stm32/stm3210e_eval/current/include/plf_arch.h b/ecos/packages/hal/cortexm/stm32/stm3210e_eval/current/include/plf_arch.h new file mode 100644 index 0000000..ab15b99 --- /dev/null +++ b/ecos/packages/hal/cortexm/stm32/stm3210e_eval/current/include/plf_arch.h @@ -0,0 +1,62 @@ +#ifndef CYGONCE_HAL_PLF_ARCH_H +#define CYGONCE_HAL_PLF_ARCH_H +//============================================================================= +// +// plf_arch.h +// +// Platform specific architecture overrides +// +//============================================================================= +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2008 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): nickg +// Date: 2008-07-30 +// Purpose: STM3210E EVAL platform specific architecture overrides +// Description: +// Usage: #include <cyg/hal/plf_arch.h> +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +#include <pkgconf/hal.h> +#include <pkgconf/hal_cortexm_stm32_stm3210e_eval.h> + + +//============================================================================= + +//----------------------------------------------------------------------------- +// end of plf_arch.h +#endif // CYGONCE_HAL_PLF_ARCH_H diff --git a/ecos/packages/hal/cortexm/stm32/stm3210e_eval/current/include/plf_intr.h b/ecos/packages/hal/cortexm/stm32/stm3210e_eval/current/include/plf_intr.h new file mode 100644 index 0000000..f447f8c --- /dev/null +++ b/ecos/packages/hal/cortexm/stm32/stm3210e_eval/current/include/plf_intr.h @@ -0,0 +1,62 @@ +#ifndef CYGONCE_HAL_PLF_INTR_H +#define CYGONCE_HAL_PLF_INTR_H +//============================================================================= +// +// plf_intr.h +// +// Platform specific interrupt overrides +// +//============================================================================= +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2008 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): nickg +// Date: 2008-07-30 +// Purpose: STM3210E EVAL platform specific interrupt overrides +// Description: +// Usage: #include <cyg/hal/plf_intr.h> +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +#include <pkgconf/hal.h> +#include <pkgconf/hal_cortexm_stm32_stm3210e_eval.h> + + +//============================================================================= + +//----------------------------------------------------------------------------- +// end of plf_intr.h +#endif // CYGONCE_HAL_PLF_INTR_H diff --git a/ecos/packages/hal/cortexm/stm32/stm3210e_eval/current/include/plf_io.h b/ecos/packages/hal/cortexm/stm32/stm3210e_eval/current/include/plf_io.h new file mode 100644 index 0000000..2cc5bb4 --- /dev/null +++ b/ecos/packages/hal/cortexm/stm32/stm3210e_eval/current/include/plf_io.h @@ -0,0 +1,165 @@ +#ifndef CYGONCE_HAL_PLF_IO_H +#define CYGONCE_HAL_PLF_IO_H +//============================================================================= +// +// plf_io.h +// +// Platform specific registers +// +//============================================================================= +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2008 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): nickg +// Date: 2008-07-30 +// Purpose: STM3210E EVAL platform specific registers +// Description: +// Usage: #include <cyg/hal/plf_io.h> +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +#include <pkgconf/hal.h> +#include <pkgconf/hal_cortexm_stm32_stm3210e_eval.h> + +//============================================================================= +// Memory access checks. +// +// Accesses to areas not backed by real devices or memory can cause +// the CPU to hang. These macros allow the GDB stubs to avoid making +// accidental accesses to these areas. + +__externC int cyg_hal_stub_permit_data_access( CYG_ADDRESS addr, cyg_uint32 count ); + +#define CYG_HAL_STUB_PERMIT_DATA_READ(_addr_, _count_) cyg_hal_stub_permit_data_access( _addr_, _count_ ) + +#define CYG_HAL_STUB_PERMIT_DATA_WRITE(_addr_, _count_ ) cyg_hal_stub_permit_data_access( _addr_, _count_ ) + +//============================================================================= + +#define HAL_AM29XXXXX_UNCACHED_ADDRESS(__addr) (__addr) + +//============================================================================= +// I2C busses and devices + +# define HAL_I2C_EXPORTED_DEVICES \ + __externC cyg_i2c_bus hal_stm32_i2c_bus1; \ + __externC cyg_i2c_device hal_stm32_i2c_temperature; + + +//============================================================================= +// I2C bus pin configurations + +#if defined(CYGHWR_HAL_STM32_I2C1_REMAP) +#define CYGHWR_HAL_STM32_I2C1_SCL CYGHWR_HAL_STM32_PIN_ALTFN_OUT( B, 8, NA, OPENDRAIN, NA, AT_LEAST(50) ) +#define CYGHWR_HAL_STM32_I2C1_SDA CYGHWR_HAL_STM32_PIN_ALTFN_OUT( B, 9, NA, OPENDRAIN, NA, AT_LEAST(50) ) +#else +#define CYGHWR_HAL_STM32_I2C1_SCL CYGHWR_HAL_STM32_PIN_ALTFN_OUT( B, 6, NA, OPENDRAIN, NA, AT_LEAST(50) ) +#define CYGHWR_HAL_STM32_I2C1_SDA CYGHWR_HAL_STM32_PIN_ALTFN_OUT( B, 7, NA, OPENDRAIN, NA, AT_LEAST(50) ) +#endif + +#define CYGHWR_HAL_STM32_I2C1_DMA_TX CYGHWR_HAL_STM32_DMA( 1, 6, 0, M2P ) +#define CYGHWR_HAL_STM32_I2C1_DMA_RX CYGHWR_HAL_STM32_DMA( 1, 7, 0, P2M ) + + +#define CYGHWR_HAL_STM32_I2C2_SCL CYGHWR_HAL_STM32_PIN_ALTFN_OUT( B, 10, NA, OPENDRAIN, NA, AT_LEAST(50) ) +#define CYGHWR_HAL_STM32_I2C2_SDA CYGHWR_HAL_STM32_PIN_ALTFN_OUT( B, 11, NA, OPENDRAIN, NA, AT_LEAST(50) ) + +#define CYGHWR_HAL_STM32_I2C2_DMA_TX CYGHWR_HAL_STM32_DMA( 1, 4, 0, M2P ) +#define CYGHWR_HAL_STM32_I2C2_DMA_RX CYGHWR_HAL_STM32_DMA( 1, 5, 0, P2M ) + +//============================================================================= +// SPI bus pin configurations + +// NOTE: The SPEED_SPI manifest is declared by the device driver +// (e.g. "devs/spi/cortexm/stm32/<vsn>/src/spi_stm32.c") and is not +// currently defined in a header. + +#ifndef CYGHWR_HAL_STM32_SPI1_REMAP +#define CYGHWR_HAL_STM32_SPI1_SCK CYGHWR_HAL_STM32_PIN_ALTFN_OUT( A, 5, NA, PUSHPULL, NONE, SPEED_SPI ) +#define CYGHWR_HAL_STM32_SPI1_MISO CYGHWR_HAL_STM32_PIN_ALTFN_IN( A, 6, NA, NA, PULLUP ) +#define CYGHWR_HAL_STM32_SPI1_MOSI CYGHWR_HAL_STM32_PIN_ALTFN_OUT( A, 7, NA, PUSHPULL, NONE, SPEED_SPI ) +#define CYGHWR_HAL_STM32_SPI1_REMAP_CONFIG 0 +#else +#define CYGHWR_HAL_STM32_SPI1_SCK CYGHWR_HAL_STM32_PIN_ALTFN_OUT( B, 3, NA, PUSHPULL, NONE, SPEED_SPI ) +#define CYGHWR_HAL_STM32_SPI1_MISO CYGHWR_HAL_STM32_PIN_ALTFN_IN( B, 4, NA, NA, PULLUP ) +#define CYGHWR_HAL_STM32_SPI1_MOSI CYGHWR_HAL_STM32_PIN_ALTFN_OUT( B, 5, NA, PUSHPULL, NONE, SPEED_SPI ) +#define CYGHWR_HAL_STM32_SPI1_REMAP_CONFIG CYGHWR_HAL_STM32_AFIO_MAPR_SPI1_RMP +#endif + +#define CYGHWR_HAL_STM32_SPI1_DMA_TX CYGHWR_HAL_STM32_DMA( 1, 3, 0, M2P ) +#define CYGHWR_HAL_STM32_SPI1_DMA_RX CYGHWR_HAL_STM32_DMA( 1, 2, 0, P2M ) + + +#define CYGHWR_HAL_STM32_SPI2_SCK CYGHWR_HAL_STM32_PIN_ALTFN_OUT( B, 13, NA, PUSHPULL, NONE, SPEED_SPI ) +#define CYGHWR_HAL_STM32_SPI2_MISO CYGHWR_HAL_STM32_PIN_ALTFN_IN( B, 14, NA, NA, PULLUP ) +#define CYGHWR_HAL_STM32_SPI2_MOSI CYGHWR_HAL_STM32_PIN_ALTFN_OUT( B, 15, NA, PUSHPULL, NONE, SPEED_SPI ) +#define CYGHWR_HAL_STM32_SPI2_REMAP_CONFIG 0 + +#define CYGHWR_HAL_STM32_SPI2_DMA_TX CYGHWR_HAL_STM32_DMA( 1, 5, 0, M2P ) +#define CYGHWR_HAL_STM32_SPI2_DMA_RX CYGHWR_HAL_STM32_DMA( 1, 4, 0, P2M ) + + + +#ifndef CYGHWR_HAL_STM32_SPI3_REMAP +#define CYGHWR_HAL_STM32_SPI3_SCK CYGHWR_HAL_STM32_PIN_ALTFN_OUT( B, 3, NA, PUSHPULL, NONE, SPEED_SPI ) +#define CYGHWR_HAL_STM32_SPI3_MISO CYGHWR_HAL_STM32_PIN_ALTFN_IN( B, 4, NA, NA, PULLUP ) +#define CYGHWR_HAL_STM32_SPI3_MOSI CYGHWR_HAL_STM32_PIN_ALTFN_OUT( B, 5, NA, PUSHPULL, NONE, SPEED_SPI ) +#define CYGHWR_HAL_STM32_SPI3_REMAP_CONFIG 0 +#else +#define CYGHWR_HAL_STM32_SPI3_SCK CYGHWR_HAL_STM32_PIN_ALTFN_OUT( C, 10, NA, PUSHPULL, NONE, SPEED_SPI ) +#define CYGHWR_HAL_STM32_SPI3_MISO CYGHWR_HAL_STM32_PIN_ALTFN_IN( C, 11, NA, NA, PULLUP ) +#define CYGHWR_HAL_STM32_SPI3_MOSI CYGHWR_HAL_STM32_PIN_ALTFN_OUT( C, 12, NA, PUSHPULL, NONE, SPEED_SPI ) +#define CYGHWR_HAL_STM32_SPI3_REMAP_CONFIG CYGHWR_HAL_STM32_AFIO_MAPR_SPI3_RMP +#endif + +#define CYGHWR_HAL_STM32_SPI3_DMA_TX CYGHWR_HAL_STM32_DMA( 2, 2, 0, M2P ) +#define CYGHWR_HAL_STM32_SPI3_DMA_RX CYGHWR_HAL_STM32_DMA( 2, 1, 0, P2M ) + + +//============================================================================= +// Optional enc424j600 Ethernet over SPI + +#ifdef CYGPKG_DEVS_ETH_ENC424J600 +struct cyg_netdevtab_entry; +__externC void cyg_devs_cortexm_stm3210e_enc424j600_init( struct cyg_netdevtab_entry * ); +#define CYG_DEVS_ETH_ENC424J600_PLF_INIT( _tab_ ) \ + cyg_devs_cortexm_stm3210e_enc424j600_init( _tab_ ) + +#endif + +//----------------------------------------------------------------------------- +// end of plf_io.h +#endif // CYGONCE_HAL_PLF_IO_H diff --git a/ecos/packages/hal/cortexm/stm32/stm3210e_eval/current/misc/redboot_JTAG.ecm b/ecos/packages/hal/cortexm/stm32/stm3210e_eval/current/misc/redboot_JTAG.ecm new file mode 100644 index 0000000..b7080cb --- /dev/null +++ b/ecos/packages/hal/cortexm/stm32/stm3210e_eval/current/misc/redboot_JTAG.ecm @@ -0,0 +1,99 @@ +cdl_savefile_version 1; +cdl_savefile_command cdl_savefile_version {}; +cdl_savefile_command cdl_savefile_command {}; +cdl_savefile_command cdl_configuration { description hardware template package }; +cdl_savefile_command cdl_package { value_source user_value wizard_value inferred_value }; +cdl_savefile_command cdl_component { value_source user_value wizard_value inferred_value }; +cdl_savefile_command cdl_option { value_source user_value wizard_value inferred_value }; +cdl_savefile_command cdl_interface { value_source user_value wizard_value inferred_value }; + +cdl_configuration eCos { + description "" ; + template redboot ; + + package CYGPKG_IO_FLASH current ; +}; + +cdl_option CYGFUN_LIBC_STRING_BSD_FUNCS { + inferred_value 0 +}; + +cdl_option CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE { + user_value 4096 +}; + +cdl_option CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT { + user_value 0 +}; + +cdl_option CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM { + inferred_value 0 +}; + +cdl_option CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS { + inferred_value 1 +}; + +cdl_option CYGSEM_HAL_ROM_MONITOR { + inferred_value 1 +}; + +cdl_option CYGSEM_HAL_USE_ROM_MONITOR { + inferred_value 0 0 +}; + +cdl_component CYG_HAL_STARTUP { + user_value JTAG +}; + +cdl_component CYGBLD_BUILD_REDBOOT { + user_value 1 +}; + +cdl_option CYGBLD_BUILD_REDBOOT_WITH_CACHES { + user_value 0 +}; + +cdl_option CYGSEM_REDBOOT_FLASH_COMBINED_FIS_AND_CONFIG { + user_value 1 +}; + +cdl_option CYGBLD_BUILD_REDBOOT_WITH_EXEC { + user_value 0 +}; + +cdl_option CYGOPT_REDBOOT_FIS_REDBOOT { + user_value 0 +}; + +cdl_component CYGOPT_REDBOOT_FIS_REDBOOT_POST { + user_value 0 +}; + +cdl_option CYGBLD_ISO_STRTOK_R_HEADER { + inferred_value 1 <cyg/libc/string/string.h> +}; + +cdl_option CYGBLD_ISO_STRING_LOCALE_FUNCS_HEADER { + inferred_value 1 <cyg/libc/string/string.h> +}; + +cdl_option CYGBLD_ISO_STRING_BSD_FUNCS_HEADER { + inferred_value 1 <cyg/libc/string/bsdstring.h> +}; + +cdl_option CYGBLD_ISO_STRING_MEMFUNCS_HEADER { + inferred_value 1 <cyg/libc/string/string.h> +}; + +cdl_option CYGBLD_ISO_STRING_STRFUNCS_HEADER { + inferred_value 1 <cyg/libc/string/string.h> +}; + + +cdl_option CYGNUM_REDBOOT_FLASH_RESERVED_DEVICES { + user_value 1 "0x08000000" +}; + + + diff --git a/ecos/packages/hal/cortexm/stm32/stm3210e_eval/current/misc/redboot_ROM.ecm b/ecos/packages/hal/cortexm/stm32/stm3210e_eval/current/misc/redboot_ROM.ecm new file mode 100644 index 0000000..a0e2f0f --- /dev/null +++ b/ecos/packages/hal/cortexm/stm32/stm3210e_eval/current/misc/redboot_ROM.ecm @@ -0,0 +1,98 @@ +cdl_savefile_version 1; +cdl_savefile_command cdl_savefile_version {}; +cdl_savefile_command cdl_savefile_command {}; +cdl_savefile_command cdl_configuration { description hardware template package }; +cdl_savefile_command cdl_package { value_source user_value wizard_value inferred_value }; +cdl_savefile_command cdl_component { value_source user_value wizard_value inferred_value }; +cdl_savefile_command cdl_option { value_source user_value wizard_value inferred_value }; +cdl_savefile_command cdl_interface { value_source user_value wizard_value inferred_value }; + +cdl_configuration eCos { + description "" ; + template redboot ; + + package CYGPKG_IO_FLASH current ; +}; + +cdl_option CYGFUN_LIBC_STRING_BSD_FUNCS { + inferred_value 0 +}; + +cdl_option CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE { + user_value 4096 +}; + +cdl_option CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT { + user_value 0 +}; + +cdl_option CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM { + inferred_value 0 +}; + +cdl_option CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS { + inferred_value 1 +}; + +cdl_option CYGSEM_HAL_ROM_MONITOR { + inferred_value 1 +}; + +cdl_option CYGSEM_HAL_USE_ROM_MONITOR { + inferred_value 0 0 +}; + +cdl_component CYG_HAL_STARTUP { + user_value ROM +}; + +cdl_component CYGBLD_BUILD_REDBOOT { + user_value 1 +}; + +cdl_option CYGBLD_BUILD_REDBOOT_WITH_CACHES { + user_value 0 +}; + +cdl_option CYGSEM_REDBOOT_FLASH_COMBINED_FIS_AND_CONFIG { + user_value 1 +}; + +cdl_option CYGBLD_BUILD_REDBOOT_WITH_EXEC { + user_value 0 +}; + +cdl_option CYGOPT_REDBOOT_FIS_REDBOOT { + user_value 0 +}; + +cdl_component CYGOPT_REDBOOT_FIS_REDBOOT_POST { + user_value 0 +}; + +cdl_option CYGBLD_ISO_STRTOK_R_HEADER { + inferred_value 1 <cyg/libc/string/string.h> +}; + +cdl_option CYGBLD_ISO_STRING_LOCALE_FUNCS_HEADER { + inferred_value 1 <cyg/libc/string/string.h> +}; + +cdl_option CYGBLD_ISO_STRING_BSD_FUNCS_HEADER { + inferred_value 1 <cyg/libc/string/bsdstring.h> +}; + +cdl_option CYGBLD_ISO_STRING_MEMFUNCS_HEADER { + inferred_value 1 <cyg/libc/string/string.h> +}; + +cdl_option CYGBLD_ISO_STRING_STRFUNCS_HEADER { + inferred_value 1 <cyg/libc/string/string.h> +}; + + +cdl_option CYGNUM_REDBOOT_FLASH_RESERVED_DEVICES { + user_value 1 "0x08000000" +}; + + diff --git a/ecos/packages/hal/cortexm/stm32/stm3210e_eval/current/src/stm3210e_eval_eth_enc424j600.c b/ecos/packages/hal/cortexm/stm32/stm3210e_eval/current/src/stm3210e_eval_eth_enc424j600.c new file mode 100644 index 0000000..85551e8 --- /dev/null +++ b/ecos/packages/hal/cortexm/stm32/stm3210e_eval/current/src/stm3210e_eval_eth_enc424j600.c @@ -0,0 +1,148 @@ +/*========================================================================== +// +// stm3210e_eval_eth_enc424j600.c +// +// Setup for optional enc424j600 Ethernet over SPI +// +//========================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2012 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): Ilija Stanislevik +// Date: 2012-04-05 +// Description: +// +//####DESCRIPTIONEND#### +// +//========================================================================*/ + +#include <cyg/hal/hal_io.h> + +#include <cyg/io/spi.h> +#include <cyg/io/spi_stm32.h> +#include <cyg/io/eth/netdev.h> +#include <cyg/io/eth/eth_drv.h> +#include <cyg/io/eth/enc424j600_eth.h> + +#include <cyg/infra/diag.h> +#include <cyg/infra/cyg_ass.h> // assertion macros + +// Set to: 1 for diagnostic printouts; 0 for no diagnostic printouts. +#define DEBUG_ENC424J600_PLATFORM_INIT 0 + +// SPI device for communication with enc424j600 Ethernet chip +#define TRANS8B false +#define CLK_IDLE_LOW 0 +#define CLK_PHASE_RISING 0 + +#define AUX_SPI_CORTEXM_STM32_DEVICE(_name_, _bus_) \ + CYG_DEVS_SPI_CORTEXM_STM32_DEVICE( \ + _name_##_spi, \ + _bus_, \ + CYGHWR_HAL_CORTEXM_STM32_SPIETH_SPI_CS, \ + TRANS8B, \ + CLK_IDLE_LOW, \ + CLK_PHASE_RISING, \ + 14000000, \ + 1, \ + 1, \ + 1 \ + ) + +AUX_SPI_CORTEXM_STM32_DEVICE +( + CYGDAT_IO_ETH_ENC424J600_NAME, + CYGHWR_HAL_CORTEXM_STM32_SPIETH_SPI_BUS +); + +// Code to initialize enc424j600 driver data structure. + +void cyg_devs_cortexm_stm3210e_enc424j600_init( struct cyg_netdevtab_entry * netdevtab_entry) +{ + struct eth_drv_sc *eth_inst = NULL; // pointer to device instance + enc424j600_priv_data_t *eth_inst_pd = NULL; // device's private data +#ifdef CYGINT_IO_ETH_INT_SUPPORT_REQUIRED + cyg_uint32 cr; + cyg_uint32 backupr; +#endif + +// Assign SPI device to Ethernet device. + eth_inst = netdevtab_entry->device_instance; + eth_inst_pd = (enc424j600_priv_data_t *)eth_inst->driver_private; + +#if DEBUG_ENC424J600_PLATFORM_INIT & 1 + diag_printf("%s(): Assigning SPI device to Ethernet device %s.\n",__FUNCTION__, netdevtab_entry->name); +#endif + eth_inst_pd->spi_service_device = (cyg_spi_device *) &CYGDAT_IO_ETH_ENC424J600_NAME_spi_stm32; + +#ifdef CYGINT_IO_ETH_INT_SUPPORT_REQUIRED + +// Interrupt output from enc424j600 is connected to one of the pins from ports A-G. +// Here this pin is marshaled to External Interrupt Controller (EXTI). + +#define ENC424J600_INTERRUPT_SOURCE_PIN CYGHWR_HAL_SPIETH_INTERRUPT_PIN +#define ENC424J600_EXTICR ((ENC424J600_INTERRUPT_SOURCE_PIN / 4) * 4 + 8) +#define ENC424J600_SHIFT_VALUE ((ENC424J600_INTERRUPT_SOURCE_PIN % 4) * 4) + +#if DEBUG_ENC424J600_PLATFORM_INIT & 1 + diag_printf("%s(): Mapping external interrupt from P%c%d.\n",__FUNCTION__, + CYGHWR_HAL_CORTEXM_STM32_SPIETH_INTERRUPT_PORT, + ENC424J600_INTERRUPT_SOURCE_PIN); +#endif + + // Is AFIO clock enabled? + HAL_READ_UINT32(CYGHWR_HAL_STM32_RCC + CYGHWR_HAL_STM32_RCC_APB2ENR , backupr ); + if (0 == (backupr & BIT_(CYGHWR_HAL_STM32_RCC_APB2ENR_AFIO))) + { + CYGHWR_HAL_STM32_CLOCK_ENABLE(CYGHWR_HAL_STM32_CLOCK(APB2,AFIO)); + } + + // Modify External Interrupt Control Register + HAL_READ_UINT32(CYGHWR_HAL_STM32_AFIO + ENC424J600_EXTICR , cr ); + cr |= ((cyg_uint32)0xf << ENC424J600_SHIFT_VALUE); + cr &= (((cyg_uint32)(CYGHWR_HAL_CORTEXM_STM32_SPIETH_INTERRUPT_PORT - 'A') + << ENC424J600_SHIFT_VALUE) & 0xffff); + HAL_WRITE_UINT32(CYGHWR_HAL_STM32_AFIO + ENC424J600_EXTICR , cr ); + + // Restore AFIO clock + if (0 == (backupr & BIT_(CYGHWR_HAL_STM32_RCC_APB2ENR_AFIO))) + { + CYGHWR_HAL_STM32_CLOCK_DISABLE(CYGHWR_HAL_STM32_CLOCK(APB2,AFIO)); + } + +#endif // #ifdef CYGINT_IO_ETH_INT_SUPPORT_REQUIRED +} + +//========================================================================== +// EOF stm3210e_eval_eth_enc424j600.c diff --git a/ecos/packages/hal/cortexm/stm32/stm3210e_eval/current/src/stm3210e_eval_flash.c b/ecos/packages/hal/cortexm/stm32/stm3210e_eval/current/src/stm3210e_eval_flash.c new file mode 100644 index 0000000..e0c244e --- /dev/null +++ b/ecos/packages/hal/cortexm/stm32/stm3210e_eval/current/src/stm3210e_eval_flash.c @@ -0,0 +1,115 @@ +/*========================================================================== +// +// stm3210e_eval_flash.c +// +// Cortex-M3 STM3210E EVAL Flash setup +// +//========================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2008 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): nickg +// Date: 2008-07-30 +// Description: +// +//####DESCRIPTIONEND#### +// +//========================================================================*/ + +#include <pkgconf/hal.h> +#include <pkgconf/hal_cortexm.h> +#include <pkgconf/hal_cortexm_stm32.h> +#include <pkgconf/hal_cortexm_stm32_stm3210e_eval.h> +#ifdef CYGPKG_KERNEL +#include <pkgconf/kernel.h> +#endif + +#include <cyg/io/flash.h> +#include <cyg/io/flash_dev.h> +#include <cyg/hal/hal_io.h> + + +#ifdef CYGHWR_HAL_CORTEXM_STM32_FLASH_INTERNAL +//-------------------------------------------------------------------------- +// Internal flash + +#include <cyg/io/stm32_flash.h> + +const cyg_stm32_flash_dev hal_stm32_flash_priv; + +CYG_FLASH_DRIVER(hal_stm32_flash, + &cyg_stm32_flash_funs, + 0, + 0x08000000, + 0, + 0, + 0, + &hal_stm32_flash_priv +); + +#endif // CYGHWR_HAL_CORTEXM_STM32_FLASH_INTERNAL + +#ifdef CYGHWR_HAL_CORTEXM_STM32_FLASH_NOR +//-------------------------------------------------------------------------- +// There is a Spansion S29GL128P90FFIR20 or a NUMONYX equivalent. +// These are AMD compatible and with CFI can all be handled by the AMD +// driver. + + +#include <cyg/io/am29xxxxx_dev.h> + +static const CYG_FLASH_FUNS(hal_stm3210e_flash_amd_funs, + &cyg_am29xxxxx_init_cfi_16, + &cyg_flash_devfn_query_nop, + &cyg_am29xxxxx_erase_16, + &cyg_am29xxxxx_program_16, + (int (*)(struct cyg_flash_dev*, const cyg_flashaddr_t, void*, size_t))0, + &cyg_flash_devfn_lock_nop, + &cyg_flash_devfn_unlock_nop); + +static const cyg_am29xxxxx_dev hal_stm3210e_flash_priv; + +CYG_FLASH_DRIVER(hal_stm3210e_flash, + &hal_stm3210e_flash_amd_funs, + 0, + 0x64000000, + 0, + 0, + hal_stm3210e_flash_priv.block_info, + &hal_stm3210e_flash_priv); + +#endif // CYGHWR_HAL_CORTEXM_STM32_FLASH_NOR + +//-------------------------------------------------------------------------- +// EOF stm3210e_eval_flash.c diff --git a/ecos/packages/hal/cortexm/stm32/stm3210e_eval/current/src/stm3210e_eval_misc.c b/ecos/packages/hal/cortexm/stm32/stm3210e_eval/current/src/stm3210e_eval_misc.c new file mode 100644 index 0000000..52fa886 --- /dev/null +++ b/ecos/packages/hal/cortexm/stm32/stm3210e_eval/current/src/stm3210e_eval_misc.c @@ -0,0 +1,256 @@ +/*========================================================================== +// +// stm3210e_eval_misc.c +// +// Cortex-M3 STM3210E EVAL HAL functions +// +//========================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2008 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): nickg +// Date: 2008-07-30 +// Description: +// +//####DESCRIPTIONEND#### +// +//========================================================================*/ + +#include <pkgconf/hal.h> +#include <pkgconf/hal_cortexm.h> +#include <pkgconf/hal_cortexm_stm32.h> +#include <pkgconf/hal_cortexm_stm32_stm3210e_eval.h> +#ifdef CYGPKG_KERNEL +#include <pkgconf/kernel.h> +#endif + +#include <cyg/infra/diag.h> +#include <cyg/infra/cyg_type.h> +#include <cyg/infra/cyg_trac.h> // tracing macros +#include <cyg/infra/cyg_ass.h> // assertion macros + +#include <cyg/hal/hal_arch.h> // HAL header +#include <cyg/hal/hal_intr.h> // HAL header + + +//========================================================================== +// System init +// +// This is run to set up the basic system, including GPIO setting, +// clock feeds, power supply, and memory initialization. This code +// runs before the DATA is copied from ROM and the BSS cleared, hence +// it cannot make use of static variables or data tables. + +__externC void hal_system_init( void ) +{ + CYG_ADDRESS base; + +#if defined(CYG_HAL_STARTUP_ROM) | defined(CYG_HAL_STARTUP_ROMINT) | defined(CYG_HAL_STARTUP_SRAM) + + // Enable peripheral clocks in RCC + + base = CYGHWR_HAL_STM32_RCC; + + HAL_WRITE_UINT32(base+CYGHWR_HAL_STM32_RCC_AHBENR, + BIT_(CYGHWR_HAL_STM32_RCC_AHBENR_FSMC) | + BIT_(CYGHWR_HAL_STM32_RCC_AHBENR_FLITF) | + BIT_(CYGHWR_HAL_STM32_RCC_AHBENR_SRAM) ); + + HAL_WRITE_UINT32(base+CYGHWR_HAL_STM32_RCC_APB2ENR, + BIT_(CYGHWR_HAL_STM32_RCC_APB2ENR_IOPA) | + BIT_(CYGHWR_HAL_STM32_RCC_APB2ENR_IOPB) | + BIT_(CYGHWR_HAL_STM32_RCC_APB2ENR_IOPC) | + BIT_(CYGHWR_HAL_STM32_RCC_APB2ENR_IOPD) | + BIT_(CYGHWR_HAL_STM32_RCC_APB2ENR_IOPE) | + BIT_(CYGHWR_HAL_STM32_RCC_APB2ENR_IOPF) | + BIT_(CYGHWR_HAL_STM32_RCC_APB2ENR_IOPG) ); + + // Set all unused GPIO lines to input with pull down to prevent + // them floating and annoying any external hardware. + + base = CYGHWR_HAL_STM32_GPIOA; + HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_GPIO_CRL, 0x88888888 ); + HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_GPIO_CRH, 0x88888888 ); + + base = CYGHWR_HAL_STM32_GPIOB; + HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_GPIO_CRL, 0x88888888 ); + HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_GPIO_CRH, 0x88888888 ); + + base = CYGHWR_HAL_STM32_GPIOC; + HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_GPIO_CRL, 0x88888888 ); + HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_GPIO_CRH, 0x88888888 ); + + // Set up GPIO lines for external bus + + base = CYGHWR_HAL_STM32_GPIOD; + HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_GPIO_CRL, 0x44bb44bb ); + HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_GPIO_CRH, 0xbbbbbbbb ); + + base = CYGHWR_HAL_STM32_GPIOE; + HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_GPIO_CRL, 0xbbbbb4bb ); + HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_GPIO_CRH, 0xbbbbbbbb ); + + base = CYGHWR_HAL_STM32_GPIOF; + HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_GPIO_CRL, 0x44bbbbbb ); + HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_GPIO_CRH, 0xbbbb4444 ); + + base = CYGHWR_HAL_STM32_GPIOG; + HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_GPIO_CRL, 0x44bbbbbb ); + HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_GPIO_CRH, 0x44444bb4 ); + + + // Set up FSMC NOR/SRAM bank 2 for NOR Flash + + base = CYGHWR_HAL_STM32_FSMC; + + HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_FSMC_BCR2, 0x00001059 ); + HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_FSMC_BTR2, 0x10000705 ); + + // Set up FSMC NOR/SRAM bank 3 for SRAM + + HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_FSMC_BCR3, 0x00001011 ); + HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_FSMC_BTR3, 0x00000200 ); + +#endif + + // Enable flash prefetch buffer and set latency to 2 wait states. + { + cyg_uint32 acr; + + base = CYGHWR_HAL_STM32_FLASH; + + HAL_READ_UINT32( base+CYGHWR_HAL_STM32_FLASH_ACR, acr ); + acr |= CYGHWR_HAL_STM32_FLASH_ACR_PRFTBE; + acr |= CYGHWR_HAL_STM32_FLASH_ACR_LATENCY(2); + HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_FLASH_ACR, acr ); + } +} + +//========================================================================== + +__externC void hal_platform_init( void ) +{ +} + +//========================================================================== + +#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS + +#include CYGHWR_MEMORY_LAYOUT_H + +//-------------------------------------------------------------------------- +// Accesses to areas not backed by real devices or memory can cause +// the CPU to hang. +// +// The following table defines the memory areas that GDB is allowed to +// touch. All others are disallowed. +// This table needs to be kept up to date with the set of memory areas +// that are available on the board. + +static struct +{ + CYG_ADDRESS start; // Region start address + CYG_ADDRESS end; // End address (last byte) +} hal_data_access[] = +{ + { CYGMEM_REGION_ram, CYGMEM_REGION_ram+CYGMEM_REGION_ram_SIZE-1 }, // External SRAM +#ifdef CYGMEM_REGION_sram + { CYGMEM_REGION_sram, CYGMEM_REGION_sram+CYGMEM_REGION_sram_SIZE-1 }, // On-chip SRAM +#endif +#ifdef CYGMEM_REGION_flash + { CYGMEM_REGION_flash, CYGMEM_REGION_flash+CYGMEM_REGION_flash_SIZE-1 }, // On-chip flash +#endif +#ifdef CYGMEM_REGION_rom + { CYGMEM_REGION_rom, CYGMEM_REGION_rom+CYGMEM_REGION_rom_SIZE-1 }, // External flash +#endif + { 0xE0000000, 0x00000000-1 }, // Cortex-M peripherals + { 0x40000000, 0x60000000-1 }, // STM32 peripherals +}; + +__externC int cyg_hal_stub_permit_data_access( CYG_ADDRESS addr, cyg_uint32 count ) +{ + int i; + for( i = 0; i < sizeof(hal_data_access)/sizeof(hal_data_access[0]); i++ ) + { + if( (addr >= hal_data_access[i].start) && + (addr+count) <= hal_data_access[i].end) + return true; + } + return false; +} + +#endif // CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS + +//========================================================================== + +#ifdef CYGPKG_REDBOOT +#include <redboot.h> +#include CYGHWR_MEMORY_LAYOUT_H + +//-------------------------------------------------------------------------- +// Memory layout +// +// We report the on-chip SRAM and external SRAM. + + +void +cyg_plf_memory_segment(int seg, unsigned char **start, unsigned char **end) +{ + switch (seg) { + case 0: + *start = (unsigned char *)CYGMEM_REGION_ram; + *end = (unsigned char *)(CYGMEM_REGION_ram + CYGMEM_REGION_ram_SIZE); + break; +#ifdef CYGMEM_REGION_sram + case 1: + *start = (unsigned char *)CYGMEM_REGION_sram; + *end = (unsigned char *)(CYGMEM_REGION_sram + CYGMEM_REGION_sram_SIZE); + break; +#elif defined(CYGMEM_REGION_xram) + case 1: + *start = (unsigned char *)CYGMEM_REGION_xram; + *end = (unsigned char *)(CYGMEM_REGION_xram + CYGMEM_REGION_xram_SIZE); + break; +#endif + default: + *start = *end = NO_MEMORY; + break; + } +} // cyg_plf_memory_segment() + +#endif // CYGPKG_REDBOOT + + +//========================================================================== +// EOF stm3210e_eval_misc.c diff --git a/ecos/packages/hal/cortexm/stm32/stm32f4discovery/current/ChangeLog b/ecos/packages/hal/cortexm/stm32/stm32f4discovery/current/ChangeLog new file mode 100644 index 0000000..9ccd105 --- /dev/null +++ b/ecos/packages/hal/cortexm/stm32/stm32f4discovery/current/ChangeLog @@ -0,0 +1,42 @@ +2013-08-09 John Dallaway <john@dallaway.org.uk> + + * cdl/hal_cortexm_stm32_stm32f4discovery.cdl: Merge CDL goal + expressions to avoid confusing the eCos Configuration Tool during + initial inference of STM32 variant HAL options. + +2013-06-09 John Dallaway <john@dallaway.org.uk> + + * cdl/hal_cortexm_stm32_stm32f4discovery.cdl, + include/plf_arch.h, include/plf_intr.h, include/plf_io.h, + include/pkgconf/mlt_cortexm_stm32f4discovery_jtag.h, + include/pkgconf/mlt_cortexm_stm32f4discovery_jtag.ldi, + include/pkgconf/mlt_cortexm_stm32f4discovery_rom.h, + include/pkgconf/mlt_cortexm_stm32f4discovery_rom.ldi, + src/stm32f4discovery_flash.c, src/stm32f4discovery_misc.c, + tests/gpio.c, misc/openocd-misc.cfg, doc/stm32f4discovery.sgml: + New STM32F4-Discovery platform HAL package. Derived from + STM32x0G-EVAL platform HAL package. + +//=========================================================================== +// ####GPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2013 Free Software Foundation, Inc. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 or (at your option) any +// later version. +// +// This program is distributed in the hope that it will be useful, but +// WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +// General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the +// Free Software Foundation, Inc., 51 Franklin Street, +// Fifth Floor, Boston, MA 02110-1301, USA. +// ------------------------------------------- +// ####GPLCOPYRIGHTEND#### +//=========================================================================== diff --git a/ecos/packages/hal/cortexm/stm32/stm32f4discovery/current/cdl/hal_cortexm_stm32_stm32f4discovery.cdl b/ecos/packages/hal/cortexm/stm32/stm32f4discovery/current/cdl/hal_cortexm_stm32_stm32f4discovery.cdl new file mode 100644 index 0000000..e367003 --- /dev/null +++ b/ecos/packages/hal/cortexm/stm32/stm32f4discovery/current/cdl/hal_cortexm_stm32_stm32f4discovery.cdl @@ -0,0 +1,289 @@ +##========================================================================== +## +## hal_cortexm_stm32_stm32f4discovery.cdl +## +## Cortex-M STM32F4-Discovery platform HAL configuration data +## +##========================================================================== +## ####ECOSGPLCOPYRIGHTBEGIN#### +## ------------------------------------------- +## This file is part of eCos, the Embedded Configurable Operating System. +## Copyright (C) 2013 Free Software Foundation, Inc. +## +## eCos is free software; you can redistribute it and/or modify it under +## the terms of the GNU General Public License as published by the Free +## Software Foundation; either version 2 or (at your option) any later +## version. +## +## eCos is distributed in the hope that it will be useful, but WITHOUT +## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +## for more details. +## +## You should have received a copy of the GNU General Public License +## along with eCos; if not, write to the Free Software Foundation, Inc., +## 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +## +## As a special exception, if other files instantiate templates or use +## macros or inline functions from this file, or you compile this file +## and link it with other works to produce a work based on this file, +## this file does not by itself cause the resulting work to be covered by +## the GNU General Public License. However the source code for this file +## must still be made available in accordance with section (3) of the GNU +## General Public License v2. +## +## This exception does not invalidate any other reasons why a work based +## on this file might be covered by the GNU General Public License. +## ------------------------------------------- +## ####ECOSGPLCOPYRIGHTEND#### +##========================================================================== +#######DESCRIPTIONBEGIN#### +## +## Author(s): jld +## Based on: stm32x0g_eval CDL by jlarmour +## Date: 2013-06-05 +## +######DESCRIPTIONEND#### +## +##========================================================================== + +cdl_package CYGPKG_HAL_CORTEXM_STM32_STM32F4DISCOVERY { + display "STMicroelectronics STM32F4-Discovery board HAL" + parent CYGPKG_HAL_CORTEXM_STM32 + + requires { CYGHWR_HAL_CORTEXM == "M4" } + requires { CYGHWR_HAL_CORTEXM_STM32_FAMILY == "F4" && + CYGHWR_HAL_CORTEXM_STM32_F4 == "F407VG" } + requires { CYGHWR_HAL_CORTEXM_STM32_CLOCK_PLL_SOURCE == "HSE" } + requires { CYGHWR_HAL_CORTEXM_STM32_CLOCK_PLL_PREDIV == 8 } + requires { CYGHWR_HAL_CORTEXM_STM32_CLOCK_PLL_MUL == 336 } + requires { CYGHWR_HAL_CORTEXM_STM32_CLOCK_SYSCLK_DIV == 2 } + requires { CYGHWR_HAL_CORTEXM_STM32_CLOCK_PLLQ_DIV == 7 } + requires { CYGHWR_HAL_CORTEXM_STM32_CLOCK_HCLK_DIV == 1 } + requires { CYGHWR_HAL_CORTEXM_STM32_CLOCK_PCLK1_DIV == 4 } + requires { CYGHWR_HAL_CORTEXM_STM32_CLOCK_PCLK2_DIV == 2 } + + include_dir cyg/hal + hardware + doc ref/hal-cortexm-stm32f4discovery-part.html + description " + The STM32F4-Discovery HAL package provides the support needed to run + eCos on the STMicroelectronics STM32F4-Discovery board." + + compile stm32f4discovery_misc.c + + define_proc { + puts $::cdl_system_header "#define CYGBLD_HAL_TARGET_H <pkgconf/hal_cortexm.h>" + puts $::cdl_system_header "#define CYGBLD_HAL_VARIANT_H <pkgconf/hal_cortexm_stm32.h>" + puts $::cdl_system_header "#define CYGBLD_HAL_PLATFORM_H <pkgconf/hal_cortexm_stm32_stm32f4discovery.h>" + puts $::cdl_header "#define HAL_PLATFORM_CPU \"Cortex-M4\"" + puts $::cdl_header "#define HAL_PLATFORM_BOARD \"STMicroelectronics STM32F4-Discovery\"" + puts $::cdl_header "#define HAL_PLATFORM_EXTRA \"\"" + } + + # use UART4 at PC10,11 for diagnostic I/O (named UART3 in the STM32 variant HAL) + implements CYGINT_HAL_STM32_UART3 + + implements CYGINT_HAL_FPV4_SP_D16 + + cdl_component CYG_HAL_STARTUP { + display "Startup type" + flavor data + default_value {"JTAG"} + legal_values {"JTAG" "ROM"} + no_define + define -file system.h CYG_HAL_STARTUP + description " + Select 'JTAG' when building applications to download into on-chip RAM + using the on-board ST-LINK/V2 serial wire debugging interface. Select + 'ROM' when building an application which will be written to on-chip + Flash memory for immediate execution on system reset." + } + + cdl_component CYGHWR_MEMORY_LAYOUT { + display "Memory layout" + flavor data + no_define + calculated { (CYG_HAL_STARTUP == "ROM" ) ? "cortexm_stm32f4discovery_rom" : + (CYG_HAL_STARTUP == "JTAG" ) ? "cortexm_stm32f4discovery_jtag" : + "undefined" } + + cdl_option CYGHWR_MEMORY_LAYOUT_LDI { + display "Memory layout linker script fragment" + flavor data + no_define + define -file system.h CYGHWR_MEMORY_LAYOUT_LDI + calculated { "<pkgconf/mlt_" . CYGHWR_MEMORY_LAYOUT . ".ldi>" } + } + + cdl_option CYGHWR_MEMORY_LAYOUT_H { + display "Memory layout header file" + flavor data + no_define + define -file system.h CYGHWR_MEMORY_LAYOUT_H + calculated { "<pkgconf/mlt_" . CYGHWR_MEMORY_LAYOUT . ".h>" } + } + + } + + cdl_option CYGARC_HAL_CORTEXM_STM32_INPUT_CLOCK { + display "Input clock frequency" + flavor data + default_value 8000000 + legal_values 0 to 1000000000 + description "Main clock input." + } + + cdl_option CYGNUM_HAL_CORTEXM_STM32_FLASH_WAIT_STATES { + display "Flash read wait states" + flavor data + default_value 5 + legal_values 0 to 7 + description " + This option gives the number of wait states to use for accessing + the flash for reads. The correct setting for this value depends + on both the CPU clock (HCLK) frequency and the voltage. Consult + the STM32 Flash programming manual (PM0059) for appropriate + values for different clock speeds or voltages. The default of + 5 reflects a supply voltage of 3.3V and HCLK of 168MHz." + } + + cdl_option CYGHWR_HAL_CORTEXM_STM32_FLASH { + display "Flash driver support" + parent CYGPKG_IO_FLASH + active_if CYGPKG_IO_FLASH + compile -library=libextras.a stm32f4discovery_flash.c + default_value 1 + description "Control flash device support for STM32F4-Discovery board." + } + + cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS { + display "Number of communication channels on the board" + flavor data + calculated 1 + } + + cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL { + display "Debug serial port" + active_if CYGPRI_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_CONFIGURABLE + flavor data + calculated 0 + description " + The STM32F4-Discovery board has one serial port enabled. This option + informs the rest of the system which port will be used to connect + to a host running GDB." + } + + cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL { + display "Diagnostic serial port" + active_if CYGPRI_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_CONFIGURABLE + flavor data + calculated 0 + description " + The STM32F4-Discovery board has one serial port enabled. This option + informs the rest of the system which port will be used for + diagnostic output." + } + + cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD { + display "Diagnostic serial port baud rate" + flavor data + legal_values 9600 19200 38400 57600 115200 + default_value 115200 + description " + This option controls the default baud rate used for the + console connection." + } + + cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_BAUD { + display "Debug serial port baud rate" + flavor data + calculated CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD + description " + This option controls the default baud rate used for the + GDB connection." + } + + cdl_component CYGBLD_GLOBAL_OPTIONS { + display "Global build options" + flavor none + parent CYGPKG_NONE + description " + Global build options including control over + compiler flags, linker flags and choice of toolchain." + + + cdl_option CYGBLD_GLOBAL_COMMAND_PREFIX { + display "Global command prefix" + flavor data + no_define + default_value { "arm-eabi" } + description " + This option specifies the command prefix used when + invoking the build tools." + } + + cdl_option CYGBLD_GLOBAL_CFLAGS { + display "Global compiler flags" + flavor data + no_define + default_value { CYGBLD_GLOBAL_WARNFLAGS . "-mcpu=cortex-m3 -mthumb -g -O2 -ffunction-sections -fdata-sections -fno-rtti -fno-exceptions" } + description " + This option controls the global compiler flags which are used to + compile all packages by default. Individual packages may define + options which override these global flags." + } + + cdl_option CYGBLD_GLOBAL_LDFLAGS { + display "Global linker flags" + flavor data + no_define + default_value { "-mcpu=cortex-m3 -mthumb -Wl,--gc-sections -Wl,-static -Wl,-n -g -nostdlib" } + description " + This option controls the global linker flags. Individual + packages may define options which override these global flags." + } + } + + cdl_component CYGPKG_HAL_CORTEXM_STM32_STM32F4DISCOVERY_OPTIONS { + display "STM32F4-Discovery HAL build options" + flavor none + description " + Package specific build options including control over + compiler flags used only in building this HAL package." + + cdl_option CYGPKG_HAL_CORTEXM_STM32_STM32F4DISCOVERY_CFLAGS_ADD { + display "Additional compiler flags" + flavor data + no_define + default_value { "-Werror" } + description " + This option modifies the set of compiler flags + for building this HAL. These flags are used + in addition to the set of global flags." + } + cdl_option CYGPKG_HAL_CORTEXM_STM32_STM32F4DISCOVERY_CFLAGS_REMOVE { + display "Suppressed compiler flags" + flavor data + no_define + default_value { "" } + description " + This option modifies the set of compiler flags + for building this HAL. These flags are + removed from the set of global flags if + present." + } + } + + cdl_option CYGPKG_HAL_CORTEXM_STM32_STM32F4DISCOVERY_TESTS { + display "STM32F4-Discovery tests" + flavor data + no_define + calculated { "tests/gpio" } + description " + This option specifies the set of tests for the STM32F4-Discovery HAL." + } + +} + +# EOF hal_cortexm_stm32_stm32f4discovery.cdl diff --git a/ecos/packages/hal/cortexm/stm32/stm32f4discovery/current/doc/stm32f4discovery.sgml b/ecos/packages/hal/cortexm/stm32/stm32f4discovery/current/doc/stm32f4discovery.sgml new file mode 100644 index 0000000..67295cb --- /dev/null +++ b/ecos/packages/hal/cortexm/stm32/stm32f4discovery/current/doc/stm32f4discovery.sgml @@ -0,0 +1,215 @@ +<!-- DOCTYPE part PUBLIC "-//OASIS//DTD DocBook V3.1//EN" --> + +<!-- =============================================================== --> +<!-- --> +<!-- stm32f4discovery.sgml --> +<!-- --> +<!-- STM32F4-Discovery platform HAL documentation --> +<!-- --> +<!-- =============================================================== --> +<!-- ####ECOSDOCCOPYRIGHTBEGIN#### --> +<!-- =============================================================== --> +<!-- Copyright (C) 2003, 2004, 2008, 2013 Free Software Foundation, Inc. --> +<!-- This material may be distributed only subject to the terms --> +<!-- and conditions set forth in the Open Publication License, v1.0 --> +<!-- or later (the latest version is presently available at --> +<!-- http://www.opencontent.org/openpub/) --> +<!-- Distribution of the work or derivative of the work in any --> +<!-- standard (paper) book form is prohibited unless prior --> +<!-- permission obtained from the copyright holder --> +<!-- =============================================================== --> +<!-- ####ECOSDOCCOPYRIGHTEND#### --> +<!-- =============================================================== --> +<!-- #####DESCRIPTIONBEGIN#### --> +<!-- --> +<!-- Author(s): jld --> +<!-- Based on: M5272C3 documentation by bartv --> +<!-- Date: 2013-06-07 --> +<!-- --> +<!-- ####DESCRIPTIONEND#### --> +<!-- =============================================================== --> + +<part id="hal-cortexm-stm32f4discovery-part"><title>STMicroelectronics STM32F4-Discovery Board Support</title> + +<refentry id="cortexm-stm32f4discovery"> + <refmeta> + <refentrytitle>Overview</refentrytitle> + </refmeta> + <refnamediv> + <refname>eCos Support for the STMicroelectronics STM32F4-Discovery Board</refname> + <refpurpose>Overview</refpurpose> + </refnamediv> + + <refsect1 id="cortexm-stm32f4discovery-description"><title>Description</title> + <para> +The STMicroelectronics STM32F4-Discovery board has an STM32F407VGT6 Cortex-M4F processor, +192KiB of on-chip SRAM, 1MiB of on-chip flash memory, plus motion and audio sensors, an +audio DAC and a connector for the on-chip USB peripheral. The board also +features an ST-LINK/V2 serial wire debug (SWD) interface. + </para> + <para> +For typical eCos development the ST-LINK/V2 interface is connected via USB to a host +computer running the OpenOCD on-chip debug tool. OpenOCD provides a GDB server enabling +the download and debuging of eCos applications via the GDB debugger. + </para> + </refsect1> + + <refsect1 id="cortexm-stm32f4discovery-hardware"><title>Supported Hardware</title> + <para> +By default, eCos will use the 128KiB of contiguous on-chip SRAM, accessible +at location 0x20000000. On-chip flash memory at 0x08000000 can be optionally +used for bootable application code. A further 64KiB of core coupled memory (CCM) +is mapped to location 0x10000000. This memory is not used by eCos but may be used +for application-defined static data structures such as thread stacks which require no +initialization other than that performed during eCos startup and application +execution. Data structures may be assigned to the <varname>.ccm</varname> section +within CCM memory using the eCos <varname>CYGBLD_ATTRIB_SECTION</varname> macro. For example: + </para> + <programlisting>char thread_stack[4096] CYGBLD_ATTRIB_SECTION(".ccm");</programlisting> + <para> +There is a serial driver <varname>CYGPKG_IO_SERIAL_CORTEXM_STM32</varname> +which supports all on-chip UARTs. However, there are no RS232 drivers or +serial connectors on the board. STM32 UART4 (named UART3 in the eCos serial driver) is +enabled for use as a diagnostics channel. + </para> + <para> +The GPIO ports are enabled and manipulated only as needed +to access UART4, the LEDs and the push button. eCos does not +enable the remaining on-chip peripherals. + </para> + </refsect1> + <refsect1 id="cortexm-stm32f4discovery-tools"><title>Tools</title> + <para> +The STM32F4-Discovery board port is intended to work with GNU tools +configured for an arm-eabi target. The original porting work was performed using +binutils 2.18.50.20080513, arm-eabi-gcc 4.3.2, arm-eabi-gdb 7.4.1 and OpenOCD 0.6.1. + </para> + </refsect1> +</refentry> + +<refentry id="cortexm-stm32f4discovery-setup"> + <refmeta> + <refentrytitle>Setup</refentrytitle> + </refmeta> + <refnamediv> + <refname>Setup</refname> + <refpurpose>Preparing for eCos Development with the STM32F4-Discovery board</refpurpose> + </refnamediv> + + <refsect1 id="cortexm-stm32f4discovery-overview"><title>Overview</title> + <para> +In a typical development environment the STM32F4-Discovery board is halted +on reset using OpenOCD communicating via the ST-LINK/V2 SWD interface. eCos +applications are configured for JTAG startup, then downloaded to the board +and executed via the arm-eabi-gdb debugger. + </para> + <para> +OpenOCD may be configured for use with the STM32F4-Discovery board using the +board configuration script <filename>stm32f4discovery.cfg</filename> provided with the tool. +It is also necessary to define a handler for GDB attach events which will halt the board. A +suitable OpenOCD script is provided at <filename>misc/openocd-misc.cfg</filename> in the +STM32F4-Discovery platform HAL package. Both scripts may be specified on the OpenOCD +command line. + </para> + </refsect1> + <refsect1 id="cortexm-stm32f4discovery-config-diagnostic"><title>Diagnostic output</title> + <para> +For diagnostic output, a SparkFun FTDI 3.3v Basic Breakout board or similar +may be connected to UART4 of the STM32F4-Discovery board using jumper wires as follows: + </para> + <informaltable frame="all"> + <tgroup cols="3" colsep="1" rowsep="1" align="left"> + <thead> + <row> + <entry>Function</entry> + <entry>STM32F4-Discovery header</entry> + <entry>SparkFun FTDI breakout board socket</entry> + </row> + </thead> + <tbody> + <row> + <entry>UART4 Tx</entry> + <entry>PC10</entry> + <entry>RXI</entry> + </row> + <row> + <entry>Ground</entry> + <entry>GND</entry> + <entry>GND</entry> + </row> + </tbody> + </tgroup> + </informaltable> + <para> +The UART is configured at 115200 baud by default and runs with 8 bits, +no parity, and 1 stop bit. The baud rate can be changed via the +configuration option <varname>CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD</varname>. + </para> + </refsect1> +</refentry> + +<refentry id="cortexm-stm32f4discovery-config"> + <refmeta> + <refentrytitle>Configuration</refentrytitle> + </refmeta> + <refnamediv> + <refname>Configuration</refname> + <refpurpose>Platform-specific Configuration Options</refpurpose> + </refnamediv> + + <refsect1 id="cortexm-stm32f4discovery-config-overview"><title>Overview</title> + <para> +The STM32F4-Discovery platform HAL package is loaded automatically when eCos is +configured for an STM32F4-Discovery target. It should never be necessary to load +this package explicitly. Unloading of the package should only occur as a result +of switching target hardware. + </para> + </refsect1> + + <refsect1 id="cortexm-stm32f4discovery-config-startup"><title>Startup</title> + <para> +The STM32F4-Discovery platform HAL package supports two startup types which may be +selected using the configuration option <varname>CYG_HAL_STARTUP</varname>: + </para> + <variablelist> + <varlistentry> + <term>JTAG</term> + <listitem><para> +This is the startup type which is normally used during application +development. <application>arm-eabi-gdb</application> is used to download a JTAG +startup application into memory via OpenOCD and the ST-LINK/V2 SWD debug interface. +eCos startup code will perform all necessary hardware initialization. + </para></listitem> + </varlistentry> + <varlistentry> + <term>ROM</term> + <listitem><para> +This startup type can be used for finished applications which will +be programmed into flash at location 0x08000000. It can also be used for +debugging larger applications which do not fit in available SRAM. The +application must be programmed to flash using the ST-LINK tool before debugging commences. +eCos startup code will perform all necessary hardware initialization. + </para></listitem> + </varlistentry> + </variablelist> + </refsect1> + + <refsect1 id="cortexm-stm32f4discovery-config-flash"><title>Flash Driver</title> + <para> +The platform HAL package contains flash driver support. This support may be +activated by loading the eCos flash I/O infrastructure package <varname>CYGPKG_IO_FLASH</varname>. + </para> + </refsect1> + + <refsect1 id="cortexm-stm32f4discovery-config-clock"><title>System Clock</title> + <para> +By default the system clock interrupts once every 10ms, corresponding +to a 100Hz clock. This period can be modified using the configuration option +<varname>CYGNUM_HAL_RTC_PERIOD</varname>. + </para> + </refsect1> +</refentry> + +</part> + +<!-- EOF stm32f4discovery.sgml --> diff --git a/ecos/packages/hal/cortexm/stm32/stm32f4discovery/current/include/pkgconf/mlt_cortexm_stm32f4discovery_jtag.h b/ecos/packages/hal/cortexm/stm32/stm32f4discovery/current/include/pkgconf/mlt_cortexm_stm32f4discovery_jtag.h new file mode 100644 index 0000000..63fb7bc --- /dev/null +++ b/ecos/packages/hal/cortexm/stm32/stm32f4discovery/current/include/pkgconf/mlt_cortexm_stm32f4discovery_jtag.h @@ -0,0 +1,21 @@ +// eCos memory layout + +#ifndef __ASSEMBLER__ +#include <cyg/infra/cyg_type.h> +#include <stddef.h> + +#endif +#define CYGMEM_REGION_ram (0x20000000) +#define CYGMEM_REGION_ram_SIZE (0x00020000-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE) +#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) +#define CYGMEM_REGION_ccm (0x10000000) +#define CYGMEM_REGION_ccm_SIZE (0x00010000) +#define CYGMEM_REGION_ccm_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) +#define CYGMEM_REGION_flash (0x08000000) +#define CYGMEM_REGION_flash_SIZE (0x00100000) +#define CYGMEM_REGION_flash_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) +#ifndef __ASSEMBLER__ +extern char CYG_LABEL_NAME (__heap1) []; +#endif +#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1)) +#define CYGMEM_SECTION_heap1_SIZE (CYGMEM_REGION_ram+CYGMEM_REGION_ram_SIZE - (size_t) CYG_LABEL_NAME (__heap1)) diff --git a/ecos/packages/hal/cortexm/stm32/stm32f4discovery/current/include/pkgconf/mlt_cortexm_stm32f4discovery_jtag.ldi b/ecos/packages/hal/cortexm/stm32/stm32f4discovery/current/include/pkgconf/mlt_cortexm_stm32f4discovery_jtag.ldi new file mode 100644 index 0000000..9b1c4eb --- /dev/null +++ b/ecos/packages/hal/cortexm/stm32/stm32f4discovery/current/include/pkgconf/mlt_cortexm_stm32f4discovery_jtag.ldi @@ -0,0 +1,43 @@ +// eCos memory layout + +#include <pkgconf/hal.h> +#include <cyg/infra/cyg_type.inc> + +MEMORY +{ + ram : ORIGIN = 0x20000000, LENGTH = 0x00020000-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE + flash : ORIGIN = 0x08000000, LENGTH = 0x00100000 + ccm : ORIGIN = 0x10000000, LENGTH = 0x00010000 +} + +hal_vsr_table = 0x20000000; +hal_virtual_vector_table = hal_vsr_table + 98*4; +#if defined(CYGSEM_HAL_VIRTUAL_VECTOR_SUPPORT) +hal_virtual_vector_table_end = hal_virtual_vector_table + 64*4; +#else // zero size virtual vector table +hal_virtual_vector_table_end = hal_virtual_vector_table; +#endif + +// SRAM is 128k. +hal_startup_stack = 0x20000000 + 1024*128; + +SECTIONS +{ + SECTIONS_BEGIN + USER_SECTION (ccm, ccm, 0x10000000, LMA_EQ_VMA) + SECTION_rom_vectors (ram, hal_virtual_vector_table_end, LMA_EQ_VMA) + SECTION_RELOCS (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_text (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_fini (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_rodata (ram, ALIGN(0x8), LMA_EQ_VMA) + SECTION_rodata1 (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_fixup (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_gcc_except_table (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_eh_frame (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_got (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_data (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_bss (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_sram (ram, ALIGN (0x8), LMA_EQ_VMA) + CYG_LABEL_DEFN(__heap1) = ALIGN (0x8); + SECTIONS_END +} diff --git a/ecos/packages/hal/cortexm/stm32/stm32f4discovery/current/include/pkgconf/mlt_cortexm_stm32f4discovery_rom.h b/ecos/packages/hal/cortexm/stm32/stm32f4discovery/current/include/pkgconf/mlt_cortexm_stm32f4discovery_rom.h new file mode 100644 index 0000000..63fb7bc --- /dev/null +++ b/ecos/packages/hal/cortexm/stm32/stm32f4discovery/current/include/pkgconf/mlt_cortexm_stm32f4discovery_rom.h @@ -0,0 +1,21 @@ +// eCos memory layout + +#ifndef __ASSEMBLER__ +#include <cyg/infra/cyg_type.h> +#include <stddef.h> + +#endif +#define CYGMEM_REGION_ram (0x20000000) +#define CYGMEM_REGION_ram_SIZE (0x00020000-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE) +#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) +#define CYGMEM_REGION_ccm (0x10000000) +#define CYGMEM_REGION_ccm_SIZE (0x00010000) +#define CYGMEM_REGION_ccm_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) +#define CYGMEM_REGION_flash (0x08000000) +#define CYGMEM_REGION_flash_SIZE (0x00100000) +#define CYGMEM_REGION_flash_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) +#ifndef __ASSEMBLER__ +extern char CYG_LABEL_NAME (__heap1) []; +#endif +#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1)) +#define CYGMEM_SECTION_heap1_SIZE (CYGMEM_REGION_ram+CYGMEM_REGION_ram_SIZE - (size_t) CYG_LABEL_NAME (__heap1)) diff --git a/ecos/packages/hal/cortexm/stm32/stm32f4discovery/current/include/pkgconf/mlt_cortexm_stm32f4discovery_rom.ldi b/ecos/packages/hal/cortexm/stm32/stm32f4discovery/current/include/pkgconf/mlt_cortexm_stm32f4discovery_rom.ldi new file mode 100644 index 0000000..fcf96e7 --- /dev/null +++ b/ecos/packages/hal/cortexm/stm32/stm32f4discovery/current/include/pkgconf/mlt_cortexm_stm32f4discovery_rom.ldi @@ -0,0 +1,43 @@ +// eCos memory layout + +#include <pkgconf/hal.h> +#include <cyg/infra/cyg_type.inc> + +MEMORY +{ + ram : ORIGIN = 0x20000000, LENGTH = 0x00020000-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE + flash : ORIGIN = 0x08000000, LENGTH = 0x00100000 + ccm : ORIGIN = 0x10000000, LENGTH = 0x00010000 +} + +hal_vsr_table = 0x20000000; +hal_virtual_vector_table = hal_vsr_table + 98*4; +#if defined(CYGSEM_HAL_VIRTUAL_VECTOR_SUPPORT) +hal_virtual_vector_table_end = hal_virtual_vector_table + 64*4; +#else // zero size virtual vector table +hal_virtual_vector_table_end = hal_virtual_vector_table; +#endif + +// SRAM is 128k. +hal_startup_stack = 0x20000000 + 1024*128; + +SECTIONS +{ + SECTIONS_BEGIN + USER_SECTION (ccm, ccm, 0x10000000, LMA_EQ_VMA) + SECTION_rom_vectors (flash, 0x08000000, LMA_EQ_VMA) + SECTION_RELOCS (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_text (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_fini (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_rodata (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_rodata1 (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_fixup (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_gcc_except_table (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_eh_frame (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_got (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_sram (ram, hal_virtual_vector_table_end, FOLLOWING (.got)) + SECTION_data (ram, ALIGN( 0x8), FOLLOWING (.sram)) + SECTION_bss (ram, ALIGN (0x8), LMA_EQ_VMA) + CYG_LABEL_DEFN(__heap1) = ALIGN (0x8); + SECTIONS_END +} diff --git a/ecos/packages/hal/cortexm/stm32/stm32f4discovery/current/include/plf_arch.h b/ecos/packages/hal/cortexm/stm32/stm32f4discovery/current/include/plf_arch.h new file mode 100644 index 0000000..c643a40 --- /dev/null +++ b/ecos/packages/hal/cortexm/stm32/stm32f4discovery/current/include/plf_arch.h @@ -0,0 +1,62 @@ +#ifndef CYGONCE_HAL_PLF_ARCH_H +#define CYGONCE_HAL_PLF_ARCH_H +//============================================================================= +// +// plf_arch.h +// +// Platform specific architecture overrides +// +//============================================================================= +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2013 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): jld +// Based on: stm32x0g_eval overrides by nickg +// Date: 2013-06-06 +// Purpose: STM32F4-Discovery platform specific architecture overrides +// Description: +// Usage: #include <cyg/hal/plf_arch.h> +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +#include <pkgconf/hal.h> +#include <pkgconf/hal_cortexm_stm32_stm32f4discovery.h> + +//============================================================================= + +//----------------------------------------------------------------------------- +// end of plf_arch.h +#endif // CYGONCE_HAL_PLF_ARCH_H diff --git a/ecos/packages/hal/cortexm/stm32/stm32f4discovery/current/include/plf_intr.h b/ecos/packages/hal/cortexm/stm32/stm32f4discovery/current/include/plf_intr.h new file mode 100644 index 0000000..48da0a8 --- /dev/null +++ b/ecos/packages/hal/cortexm/stm32/stm32f4discovery/current/include/plf_intr.h @@ -0,0 +1,62 @@ +#ifndef CYGONCE_HAL_PLF_INTR_H +#define CYGONCE_HAL_PLF_INTR_H +//============================================================================= +// +// plf_intr.h +// +// Platform specific interrupt overrides +// +//============================================================================= +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2013 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): jld +// Based on: stm32x0g_eval overrides by nickg +// Date: 2013-06-06 +// Purpose: STM32F4-Discovery platform specific interrupt overrides +// Description: +// Usage: #include <cyg/hal/plf_intr.h> +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +#include <pkgconf/hal.h> +#include <pkgconf/hal_cortexm_stm32_stm32f4discovery.h> + +//============================================================================= + +//----------------------------------------------------------------------------- +// end of plf_intr.h +#endif // CYGONCE_HAL_PLF_INTR_H diff --git a/ecos/packages/hal/cortexm/stm32/stm32f4discovery/current/include/plf_io.h b/ecos/packages/hal/cortexm/stm32/stm32f4discovery/current/include/plf_io.h new file mode 100644 index 0000000..8f5eb5a --- /dev/null +++ b/ecos/packages/hal/cortexm/stm32/stm32f4discovery/current/include/plf_io.h @@ -0,0 +1,67 @@ +#ifndef CYGONCE_HAL_PLF_IO_H +#define CYGONCE_HAL_PLF_IO_H +//============================================================================= +// +// plf_io.h +// +// Platform specific registers +// +//============================================================================= +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2013 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): jld +// Date: 2013-06-06 +// Purpose: STM32F4-Discovery platform specific registers +// Description: +// Usage: #include <cyg/hal/plf_io.h> +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +#include <pkgconf/hal.h> +#include <pkgconf/hal_cortexm_stm32_stm32f4discovery.h> + +// User LEDs and button + +#define CYGHWR_HAL_STM32F4DISCOVERY_LED1 CYGHWR_HAL_STM32_PIN_OUT( D, 12, PUSHPULL, NONE, LOW ) +#define CYGHWR_HAL_STM32F4DISCOVERY_LED2 CYGHWR_HAL_STM32_PIN_OUT( D, 13, PUSHPULL, NONE, LOW ) +#define CYGHWR_HAL_STM32F4DISCOVERY_LED3 CYGHWR_HAL_STM32_PIN_OUT( D, 14, PUSHPULL, NONE, LOW ) +#define CYGHWR_HAL_STM32F4DISCOVERY_LED4 CYGHWR_HAL_STM32_PIN_OUT( D, 15, PUSHPULL, NONE, LOW ) +#define CYGHWR_HAL_STM32F4DISCOVERY_BTN1 CYGHWR_HAL_STM32_PIN_IN( A, 0, NONE ) + +//----------------------------------------------------------------------------- +// end of plf_io.h +#endif // CYGONCE_HAL_PLF_IO_H diff --git a/ecos/packages/hal/cortexm/stm32/stm32f4discovery/current/misc/openocd-misc.cfg b/ecos/packages/hal/cortexm/stm32/stm32f4discovery/current/misc/openocd-misc.cfg new file mode 100644 index 0000000..a2d204b --- /dev/null +++ b/ecos/packages/hal/cortexm/stm32/stm32f4discovery/current/misc/openocd-misc.cfg @@ -0,0 +1,54 @@ +##========================================================================== +## +## openocd-misc.cfg +## +## Cortex-M STM32F4-Discovery OpenOCD miscellaneous definitions +## +##========================================================================== +## ####ECOSGPLCOPYRIGHTBEGIN#### +## ------------------------------------------- +## This file is part of eCos, the Embedded Configurable Operating System. +## Copyright (C) 2013 Free Software Foundation, Inc. +## +## eCos is free software; you can redistribute it and/or modify it under +## the terms of the GNU General Public License as published by the Free +## Software Foundation; either version 2 or (at your option) any later +## version. +## +## eCos is distributed in the hope that it will be useful, but WITHOUT +## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +## for more details. +## +## You should have received a copy of the GNU General Public License +## along with eCos; if not, write to the Free Software Foundation, Inc., +## 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +## +## As a special exception, if other files instantiate templates or use +## macros or inline functions from this file, or you compile this file +## and link it with other works to produce a work based on this file, +## this file does not by itself cause the resulting work to be covered by +## the GNU General Public License. However the source code for this file +## must still be made available in accordance with section (3) of the GNU +## General Public License v2. +## +## This exception does not invalidate any other reasons why a work based +## on this file might be covered by the GNU General Public License. +## ------------------------------------------- +## ####ECOSGPLCOPYRIGHTEND#### +##========================================================================== +#######DESCRIPTIONBEGIN#### +## +## Author(s): jld +## Date: 2013-06-09 +## +######DESCRIPTIONEND#### +## +##========================================================================== + +gdb_memory_map disable +stm32f4x.cpu configure -event gdb-attach { + reset init +} + +# EOF openocd-misc.cfg diff --git a/ecos/packages/hal/cortexm/stm32/stm32f4discovery/current/src/stm32f4discovery_flash.c b/ecos/packages/hal/cortexm/stm32/stm32f4discovery/current/src/stm32f4discovery_flash.c new file mode 100644 index 0000000..5c5a7a0 --- /dev/null +++ b/ecos/packages/hal/cortexm/stm32/stm32f4discovery/current/src/stm32f4discovery_flash.c @@ -0,0 +1,65 @@ +/*========================================================================== +// +// stm32f4discovery_flash.c +// +// Cortex-M4 STM32F4-Discovery Flash setup +// +//========================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2013 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): jld +// Based on: stm32x0g_eval flash setup by jlarmour +// Date: 2013-06-06 +// Description: +// +//####DESCRIPTIONEND#### +// +//========================================================================*/ + +#include <cyg/io/flash_dev.h> +#include <cyg/io/stm32_flash.h> + +CYG_FLASH_DRIVER(hal_stm32_flash, + &cyg_stm32_flash_funs, + 0, + 0x08000000, + 0, + 0, + 0, + &hal_stm32_flash_priv +); + +//-------------------------------------------------------------------------- +// EOF stm32f4discovery_flash.c diff --git a/ecos/packages/hal/cortexm/stm32/stm32f4discovery/current/src/stm32f4discovery_misc.c b/ecos/packages/hal/cortexm/stm32/stm32f4discovery/current/src/stm32f4discovery_misc.c new file mode 100644 index 0000000..8f3f5f0 --- /dev/null +++ b/ecos/packages/hal/cortexm/stm32/stm32f4discovery/current/src/stm32f4discovery_misc.c @@ -0,0 +1,147 @@ +/*========================================================================== +// +// stm32f4discovery_misc.c +// +// Cortex-M4 STM32F4-Discovery HAL functions +// +//========================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2008, 2011, 2012, 2013 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): jld +// Based on: stm32x0g_eval misc setup by jlarmour +// Date: 2013-06-05 +// Description: +// +//####DESCRIPTIONEND#### +// +//========================================================================*/ + +#include <pkgconf/hal.h> +#include <pkgconf/hal_cortexm.h> +#include <pkgconf/hal_cortexm_stm32.h> +#include <pkgconf/hal_cortexm_stm32_stm32f4discovery.h> + +#include <cyg/infra/cyg_ass.h> +#include <cyg/hal/hal_arch.h> +#include <cyg/hal/hal_intr.h> +#include <cyg/hal/hal_if.h> + +//========================================================================== + +#if defined(CYGSEM_HAL_VIRTUAL_VECTOR_SUPPORT) +#if (CYGNUM_CALL_IF_TABLE_SIZE > 64) +// We force a compilation error for this fatal condition since run-time asserts +// may not be enabled for the build. +#error "The CALL_IF_TABLE_SIZE pre-allocation in the linker scripts for this platform need to be updated" +#endif +#endif // CYGSEM_HAL_VIRTUAL_VECTOR_SUPPORT + +//========================================================================== +// System init +// +// This is run to set up the basic system, including GPIO setting, +// clock feeds, power supply, and memory initialization. This code +// runs before the DATA is copied from ROM and the BSS cleared, hence +// it cannot make use of static variables or data tables. + +__externC void hal_system_init( void ) +{ + CYG_ADDRESS base; + + // Enable CCM clock and any required GPIO ports in RCC + base = CYGHWR_HAL_STM32_RCC; + HAL_WRITE_UINT32(base+CYGHWR_HAL_STM32_RCC_AHB1ENR, + BIT_(CYGHWR_HAL_STM32_RCC_AHB1ENR_CCMDATARAMEN) | + BIT_(CYGHWR_HAL_STM32_RCC_AHB1ENR_GPIOA) | + BIT_(CYGHWR_HAL_STM32_RCC_AHB1ENR_GPIOC) | + BIT_(CYGHWR_HAL_STM32_RCC_AHB1ENR_GPIOD) ); + + // Set unused lines on enabled GPIO ports to input with pull down + + // GPIO Port A - setup PA0 for button, PA9 for LED, PA13,14 for SWD + base = CYGHWR_HAL_STM32_GPIOA; + HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_GPIO_PUPDR, 0x82A8AAA8 ); + HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_GPIO_MODER, 0x28040000 ); + + // GPIO Port C - setup PC10,11 for RS232 (UART4) + base = CYGHWR_HAL_STM32_GPIOC; + HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_GPIO_PUPDR, 0xAA0AAAAA ); + HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_GPIO_MODER, 0x00A00000 ); + + // GPIO Port D - setup PD5,12,13,14,15 for LEDs + base = CYGHWR_HAL_STM32_GPIOD; + HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_GPIO_PUPDR, 0x00AAA2AA ); + HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_GPIO_MODER, 0x55000400 ); + + // Enable flash prefetch buffer, cacheability and set latency to 2 wait states + // Latency has to be set before clock is switched to a higher speed + { + cyg_uint32 acr; + + base = CYGHWR_HAL_STM32_FLASH; + + HAL_READ_UINT32( base+CYGHWR_HAL_STM32_FLASH_ACR, acr ); + acr |= CYGHWR_HAL_STM32_FLASH_ACR_PRFTEN; + acr |= CYGHWR_HAL_STM32_FLASH_ACR_DCEN|CYGHWR_HAL_STM32_FLASH_ACR_ICEN; + acr |= CYGHWR_HAL_STM32_FLASH_ACR_LATENCY(CYGNUM_HAL_CORTEXM_STM32_FLASH_WAIT_STATES); + HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_FLASH_ACR, acr ); + } +} + +//========================================================================== + +__externC void hal_platform_init( void ) +{ +#ifdef CYGDBG_USE_ASSERTS + __externC char __sram_data_start[]; +#endif + +#ifdef CYGSEM_HAL_VIRTUAL_VECTOR_SUPPORT + // Check the number of VSRs matches the linker script. We can do this + // because we intend the VV table to follow the VSR table with no gaps. + CYG_ASSERT( (char*)&hal_virtual_vector_table[0] - (char*)&hal_vsr_table >= CYGNUM_HAL_VSR_COUNT*4, + "VSR table size does not match" ); + // Now check the declared start of SRAM data follows the VV table end + CYG_ASSERT( (__sram_data_start - (char*)&hal_virtual_vector_table[0]) >= CYGNUM_CALL_IF_TABLE_SIZE*4, + "VV table size does not match sram space" ); +#else + // Check the VSR table fits below declared start of SRAM data + CYG_ASSERT( (__sram_data_start - (char*)&hal_vsr_table[0]) >= CYGNUM_HAL_VSR_COUNT*4, + "VSR table size does not match" ); +#endif +} + +//========================================================================== +// EOF stm32f4discovery_misc.c diff --git a/ecos/packages/hal/cortexm/stm32/stm32f4discovery/current/tests/gpio.c b/ecos/packages/hal/cortexm/stm32/stm32f4discovery/current/tests/gpio.c new file mode 100644 index 0000000..766691b --- /dev/null +++ b/ecos/packages/hal/cortexm/stm32/stm32f4discovery/current/tests/gpio.c @@ -0,0 +1,73 @@ +/*============================================================================= +// +// gpio.c +// +// Test for STM32F4-Discovery GPIO +// +//============================================================================= +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2013 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): jld +// Date: 2013-06-07 +// +//####DESCRIPTIONEND#### +// +//===========================================================================*/ + +#include <cyg/infra/testcase.h> +#include <cyg/hal/hal_intr.h> +#include <cyg/hal/var_io.h> + +externC void cyg_start(void) { + int b, n; + CYG_TEST_INIT(); + CYG_TEST_INFO( "Starting STM32F4-Discovery GPIO test" ); + CYG_TEST_INFO( "Press and hold user button for slow LED count" ); + for ( n = 0; n < 0x100; n++ ) { + // display least significant 4 bits of count on user LEDs + CYGHWR_HAL_STM32_GPIO_OUT( CYGHWR_HAL_STM32F4DISCOVERY_LED1, 0 != (n & 0x1) ); + CYGHWR_HAL_STM32_GPIO_OUT( CYGHWR_HAL_STM32F4DISCOVERY_LED2, 0 != (n & 0x2) ); + CYGHWR_HAL_STM32_GPIO_OUT( CYGHWR_HAL_STM32F4DISCOVERY_LED3, 0 != (n & 0x4) ); + CYGHWR_HAL_STM32_GPIO_OUT( CYGHWR_HAL_STM32F4DISCOVERY_LED4, 0 != (n & 0x8) ); + // extend delay from 125ms to 500ms when user button pressed + CYGHWR_HAL_STM32_GPIO_IN( CYGHWR_HAL_STM32F4DISCOVERY_BTN1, &b ); + HAL_DELAY_US( 125000 * (1 + ( (b & 1) * 3) ) ); + } + CYG_TEST_PASS_FAIL( 1, "STM32F4-Discovery GPIO test" ); + CYG_TEST_FINISH( "STM32F4-Discovery GPIO test" ); +} + +//============================================================================= +// EOF gpio.c diff --git a/ecos/packages/hal/cortexm/stm32/stm32x0g_eval/current/ChangeLog b/ecos/packages/hal/cortexm/stm32/stm32x0g_eval/current/ChangeLog new file mode 100644 index 0000000..8683a0f --- /dev/null +++ b/ecos/packages/hal/cortexm/stm32/stm32x0g_eval/current/ChangeLog @@ -0,0 +1,199 @@ +2013-04-06 Jerzy Dyrda <jerzdy@gmail.com> + + * cdl/hal_cortexm_stm32_stm32x0g_eval.cdl: Fix PHY name and + added defualt Ethernet interface. + * src/stm32x0g_eval_misc.c: Enabled clock for PHY. [ Bugzilla 1001219 ] + +2013-03-09 Ilija Kocho <ilijak@siva.com.mk> + + * misc/redboot_ROM_FPU.ecm: Add ECM for RedBoot with FPU support. + +2012-12-01 Ilija Kocho <ilijak@siva.com.mk> + + * cdl/hal_cortexm_stm32_stm32x0g_eval.cdl: Implement CYGINT_HAL_FPV4_SP_D16. + [Bugzilla 1001607] + +2012-03-29 Jonathan Larmour <jifl@eCosCentric.com> + + * include/pkgconf/mlt_cortexm_stm32x0g_eval_sram.ldi: + * include/pkgconf/mlt_cortexm_stm32x0g_eval_romint.ldi: + * include/pkgconf/mlt_cortexm_stm32x0g_eval_rom.ldi: + * include/pkgconf/mlt_cortexm_stm32x0g_eval_jtag.ldi: + * include/pkgconf/mlt_cortexm_stm32x0g_eval_ram.ldi: + Correct number of VSR table entries. + * src/stm32x0g_eval_misc.c (hal_platform_init): Add assertion checks + that layout of vector tables at bottom of SRAM is what it should be. + +2012-03-29 James Smith <jsmith@ecoscentric.com> + + * include/pkgconf/mlt_cortexm_stm32x0g_eval_sram.ldi: + * include/pkgconf/mlt_cortexm_stm32x0g_eval_romint.ldi: + * include/pkgconf/mlt_cortexm_stm32x0g_eval_rom.ldi: + * include/pkgconf/mlt_cortexm_stm32x0g_eval_jtag.ldi: + * include/pkgconf/mlt_cortexm_stm32x0g_eval_ram.ldi: + Provide hal_virtual_vector_table_end symbol to allow the + SECTION_sram pre-allocation to be minimised to the actual platform + requirements. + + * src/stm32x0g_eval_misc.c: Provide #error check on linker script + hardwired CYGNUM_CALL_IF_TABLE_SIZE assumption. + +2012-03-23 James Smith <jsmith@ecoscentric.com> + + * include/plf_io.h: Update GPIO pin definitions to use new PIN + wrapper macros. Update the I2C lines to specify PULLUP. + +2012-03-22 James Smith <jsmith@ecoscentric.com> + + * include/plf_io.h (CYGHWR_HAL_STM32_ETH_MII_*): Platform specific + ethernet pin manifests updated to use new GPIO PIN macros. + +2012-03-15 James Smith <jsmith@ecoscentric.com> + + * cdl/hal_cortexm_stm32_stm32x0g_eval.cdl: + * include/pkgconf/mlt_cortexm_stm32x0g_eval_jtag.ldi: + * include/pkgconf/mlt_cortexm_stm32x0g_eval_jtag.ldi: + * include/pkgconf/mlt_cortexm_stm32x0g_eval_ram.ldi: + * include/pkgconf/mlt_cortexm_stm32x0g_eval_ram.ldi: + * include/pkgconf/mlt_cortexm_stm32x0g_eval_rom.ldi: + * include/pkgconf/mlt_cortexm_stm32x0g_eval_rom.ldi: + * include/pkgconf/mlt_cortexm_stm32x0g_eval_romint.ldi: + * include/pkgconf/mlt_cortexm_stm32x0g_eval_romint.ldi: + * include/pkgconf/mlt_cortexm_stm32x0g_eval_sram.h: + * include/pkgconf/mlt_cortexm_stm32x0g_eval_sram.ldi: + * src/stm32x0g_eval_flash.c: + * src/stm32x0g_eval_misc.c: + * src/stm32x0g_eval_spi.c: + Rename platform from the name "stm3220g_eval" to the generic name + "stm32x0g_eval". This is to make it clear that the platform + supports both the F2 (STM3220G-EVAL) and F4 (STM3240G-EVAL) + platforms. This rename includes renaming of the relevant support + source files. + + * include/plf_io.h (HAL_I2C_EXPORTED_DEVICES): Declare I2C bus1 + for on-board M24C64 device. + +2012-02-08 Jonathan Larmour <jifl@eCosCentric.com> + + * cdl/hal_cortexm_stm32_stm3220g_eval.cdl + (CYGPKG_HAL_CORTEXM_STM32_STM3220G_EVAL_SPI): This should now be a component + since it has no children. Also make description match configuration (Aardvark + expected to be on bus 2). + +2012-02-05 Jonathan Larmour <jifl@eCosCentric.com> + + * misc/redboot_JTAG.ecm, misc/redboot_ROM.ecm: Build in inferences + so there's no output on import. + * misc/redboot_RAM.ecm: New file. For completeness and to make it + easier for RedBoot to update itself. + * cdl/hal_cortexm_stm32_stm3220g_eval.cdl: Make comment description of + UART selection and naming clearer. + +2012-01-31 Jonathan Larmour <jifl@eCosCentric.com> + + * include/plf_io.h: Prototype hal_stm3220_led() for setting board LEDs. + * src/stm3220g_eval_misc.c: Choose correct board SRAM memory timings. + +2012-01-13 Nick Garnett <nickg@ecoscentric.com> + + * misc/redboot_ROM.ecm: + * misc/redboot_JTAG.ecm: Add CYGPKG_IO_WALLCLOCK package to enable + date command for setting on-chip RTC. + +2012-01-12 Nick Garnett <nickg@ecoscentric.com> + + * cdl/hal_cortexm_stm32_stm3220g_eval.cdl: Add SPI and I2C + configuration options. + + * include/plf_io.h: Add SPI and I2C pin and DMA stream definitions. + + * src/stm3220g_eval_spi.c: Add SPI device definition for aardvark + board. + +2011-12-20 Jonathan Larmour <jifl@eCosCentric.com> + + * cdl/hal_cortexm_stm32_stm3220g_eval.cdl: Just set a requires on + RedBoot's number of memory segments to be 2 rather than using a + non-configurable option. + +2011-12-15 Jonathan Larmour <jifl@eCosCentric.com> + + * cdl/hal_cortexm_stm32_stm3220g_eval.cdl + (CYGNUM_HAL_CORTEXM_STM32_FLASH_WAIT_STATES): New option. Configures + Flash wait states. + (CYGPKG_HAL_CORTEXM_STM32_STM3220G_EVAL_ETH0): New component. Holds + options and CDL to configure ethernet support. + Change default baud rate to 115200. + * include/pkgconf/mlt_cortexm_stm3220g_eval_jtag.h: Add definitions for + sram and flash regions. + * include/pkgconf/mlt_cortexm_stm3220g_eval_ram.h: Add definitions for + flash region. + * include/pkgconf/mlt_cortexm_stm3220g_eval_sram.h: Ditto. Also fix + external SRAM address. + * include/pkgconf/mlt_cortexm_stm3220g_eval_sram.ldi: Fix external SRAM + address. + * include/plf_io.h: Provide platform specific ethernet pin mappings. + (CYGHWR_HAL_STM32_ETH_CONFIGURE_MCO): New macro used to configure MCO1 + as PHY clock. + * misc/redboot_JTAG.ecm, misc/redboot_ROM.ecm: Don't disable + CYGOPT_REDBOOT_FIS_REDBOOT nor CYGOPT_REDBOOT_FIS_REDBOOT_POST - there + is only one flash here and it does contain RedBoot. + * src/stm3220g_eval_flash.c: No longer define private flash structure + here. Internal flash support is no longer an option in this file if this + file is used at all. + * src/stm3220g_eval_misc.c (hal_system_init): Clear FSMC reset bit after + reset otherwise it stays there. + Configure USART4 TX/RX on PC10/11 otherwise RedBoot can get confused. + Set Flash wait states as per configuration. + (cyg_plf_memory_segment): Allow for renaming of external SRAM region to + xram. + +2011-12-12 Jonathan Larmour <jifl@eCosCentric.com> + + * cdl/hal_cortexm_stm32_stm3220g_eval.cdl: Set PLLQ. + +2011-12-08 Jonathan Larmour <jifl@eCosCentric.com> + + * cdl/hal_cortexm_stm32_stm3220g_eval.cdl: + * include/plf_arch.h: + * include/plf_intr.h: + * include/plf_io.h: + * include/pkgconf/mlt_cortexm_stm3220g_eval_jtag.h: + * include/pkgconf/mlt_cortexm_stm3220g_eval_jtag.ldi: + * include/pkgconf/mlt_cortexm_stm3220g_eval_ram.h: + * include/pkgconf/mlt_cortexm_stm3220g_eval_ram.ldi: + * include/pkgconf/mlt_cortexm_stm3220g_eval_rom.h: + * include/pkgconf/mlt_cortexm_stm3220g_eval_romint.h: + * include/pkgconf/mlt_cortexm_stm3220g_eval_romint.ldi: + * include/pkgconf/mlt_cortexm_stm3220g_eval_rom.ldi: + * include/pkgconf/mlt_cortexm_stm3220g_eval_sram.h: + * include/pkgconf/mlt_cortexm_stm3220g_eval_sram.ldi: + * misc/redboot_JTAG.ecm: + * misc/redboot_ROM.ecm: + * src/stm3220g_eval_flash.c: + * src/stm3220g_eval_misc.c: + New package -- ST STM3220G EVAL board HAL. Derived from STM3210E HAL. + +//=========================================================================== +// ####GPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2011 Free Software Foundation, Inc. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 or (at your option) any +// later version. +// +// This program is distributed in the hope that it will be useful, but +// WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +// General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the +// Free Software Foundation, Inc., 51 Franklin Street, +// Fifth Floor, Boston, MA 02110-1301, USA. +// ------------------------------------------- +// ####GPLCOPYRIGHTEND#### +//=========================================================================== diff --git a/ecos/packages/hal/cortexm/stm32/stm32x0g_eval/current/cdl/hal_cortexm_stm32_stm32x0g_eval.cdl b/ecos/packages/hal/cortexm/stm32/stm32x0g_eval/current/cdl/hal_cortexm_stm32_stm32x0g_eval.cdl new file mode 100644 index 0000000..dcc2fd2 --- /dev/null +++ b/ecos/packages/hal/cortexm/stm32/stm32x0g_eval/current/cdl/hal_cortexm_stm32_stm32x0g_eval.cdl @@ -0,0 +1,473 @@ +##========================================================================== +## +## hal_cortexm_stm32_stm32x0g_eval.cdl +## +## Cortex-M STM32X0G EVAL platform HAL configuration data +## +##========================================================================== +## ####ECOSGPLCOPYRIGHTBEGIN#### +## ------------------------------------------- +## This file is part of eCos, the Embedded Configurable Operating System. +## Copyright (C) 2012 Free Software Foundation, Inc. +## +## eCos is free software; you can redistribute it and/or modify it under +## the terms of the GNU General Public License as published by the Free +## Software Foundation; either version 2 or (at your option) any later +## version. +## +## eCos is distributed in the hope that it will be useful, but WITHOUT +## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +## for more details. +## +## You should have received a copy of the GNU General Public License +## along with eCos; if not, write to the Free Software Foundation, Inc., +## 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +## +## As a special exception, if other files instantiate templates or use +## macros or inline functions from this file, or you compile this file +## and link it with other works to produce a work based on this file, +## this file does not by itself cause the resulting work to be covered by +## the GNU General Public License. However the source code for this file +## must still be made available in accordance with section (3) of the GNU +## General Public License v2. +## +## This exception does not invalidate any other reasons why a work based +## on this file might be covered by the GNU General Public License. +## ------------------------------------------- +## ####ECOSGPLCOPYRIGHTEND#### +##========================================================================== +#######DESCRIPTIONBEGIN#### +## +## Author(s): jlarmour +## Based on: stm3210e CDL by nickg +## Date: 2011-11-10 +## +######DESCRIPTIONEND#### +## +##========================================================================== + +cdl_package CYGPKG_HAL_CORTEXM_STM32_STM32X0G_EVAL { + display "ST STM32x0G-EVAL (STM32 20-21-45-46 G-EVAL) Development Board HAL" + parent CYGPKG_HAL_CORTEXM_STM32 + requires { ((CYGHWR_HAL_CORTEXM_STM32_FAMILY == "F2") || (CYGHWR_HAL_CORTEXM_STM32_FAMILY == "F4")) } + requires { (CYGHWR_HAL_CORTEXM_STM32_FAMILY == "F2") ? (CYGHWR_HAL_CORTEXM_STM32_F2 == "F207IG") : (CYGHWR_HAL_CORTEXM_STM32_F4 == "F407IG") } + requires { (CYGHWR_HAL_CORTEXM_STM32_FAMILY == "F2") implies (CYGHWR_HAL_CORTEXM == "M3") } + requires { (CYGHWR_HAL_CORTEXM_STM32_FAMILY == "F4") implies (CYGHWR_HAL_CORTEXM == "M4") } + # 25MHz crystal feeds HSE + # From STM32F4xx Rev A System Clock Configuration v1.0.1 + # SYSCLK 120MHz 168MHz + # ------ ------ ------ + # HSE 25MHz 25MHz fixed input crystal on board : CYGARC_HAL_CORTEXM_STM32_INPUT_CLOCK + # PLL_M 25 25 (6bits) main divisor + # PLL_N 240 336 (9bits) main multiplier + # PLL_P 2 2 (2bits) derived from PLL_N : used for SYSCLK (must not exceed F2:120 or F4:168) + # PLL_Q 5 7 (4bits) derived from PLL_N : used for USB OTG FS, SDIO and RNG (must be >= 2) + # AHB Prescaler 1 1 + # SYSCLK 120MHz 168MHz (((HSE / PLL_M) * PLL_N) / PLL_P) + # HCLK 120MHz 168MHz (SYSCLK / AHB Prescaler) + # APB1 Prescaler 4 4 + # PCLK1 30MHz 42MHz (HCLK / APB1 Prescaler) + # APB2 Prescaler 2 2 + # PCLK2 60MHz 84MHz (HCLK / APB2 Prescaler) + # + # Must use HSE for the PLL settings below + requires { CYGHWR_HAL_CORTEXM_STM32_CLOCK_PLL_SOURCE == "HSE" } + # F2: + requires { (CYGHWR_HAL_CORTEXM_STM32_FAMILY == "F2") implies (CYGHWR_HAL_CORTEXM_STM32_CLOCK_PLL_PREDIV == 15) } + requires { (CYGHWR_HAL_CORTEXM_STM32_FAMILY == "F2") implies (CYGHWR_HAL_CORTEXM_STM32_CLOCK_PLL_MUL == 288) } + requires { (CYGHWR_HAL_CORTEXM_STM32_FAMILY == "F2") implies (CYGHWR_HAL_CORTEXM_STM32_CLOCK_SYSCLK_DIV == 4) } + requires { (CYGHWR_HAL_CORTEXM_STM32_FAMILY == "F2") implies (CYGHWR_HAL_CORTEXM_STM32_CLOCK_PLLQ_DIV == 10) } + # F4: + requires { (CYGHWR_HAL_CORTEXM_STM32_FAMILY == "F4") implies (CYGHWR_HAL_CORTEXM_STM32_CLOCK_PLL_PREDIV == 25) } + requires { (CYGHWR_HAL_CORTEXM_STM32_FAMILY == "F4") implies (CYGHWR_HAL_CORTEXM_STM32_CLOCK_PLL_MUL == 336) } + requires { (CYGHWR_HAL_CORTEXM_STM32_FAMILY == "F4") implies (CYGHWR_HAL_CORTEXM_STM32_CLOCK_SYSCLK_DIV == 2) } + requires { (CYGHWR_HAL_CORTEXM_STM32_FAMILY == "F4") implies (CYGHWR_HAL_CORTEXM_STM32_CLOCK_PLLQ_DIV == 7) } + # Common: + requires { CYGHWR_HAL_CORTEXM_STM32_CLOCK_HCLK_DIV == 1 } + requires { CYGHWR_HAL_CORTEXM_STM32_CLOCK_PCLK1_DIV == 4 } + requires { CYGHWR_HAL_CORTEXM_STM32_CLOCK_PCLK2_DIV == 2 } + +# define_header hal_cortexm_stm32_stm32x0g_eval.h + include_dir cyg/hal + hardware + description " + The STM32x0G EVAL HAL package provides the support needed to run + eCos on the ST STM32 20-21-45-46 G-EVAL board." + + compile stm32x0g_eval_misc.c + + cdl_option CYGPKG_HAL_CORTEXM_STM32_STM3220G_EVAL { + display "Platform definitions for STM3220G-EVAL (F2) board." + active_if { CYGHWR_HAL_CORTEXM_STM32_FAMILY == "F2" } + no_define + calculated 1 + define_proc { + puts $::cdl_system_header "#define CYGBLD_HAL_TARGET_H <pkgconf/hal_cortexm.h>" + puts $::cdl_system_header "#define CYGBLD_HAL_VARIANT_H <pkgconf/hal_cortexm_stm32.h>" + puts $::cdl_system_header "#define CYGBLD_HAL_PLATFORM_H <pkgconf/hal_cortexm_stm32_stm32x0g_eval.h>" + puts $::cdl_header "#define HAL_PLATFORM_CPU \"Cortex-M3\"" + puts $::cdl_header "#define HAL_PLATFORM_BOARD \"ST STM3220G-EVAL\"" + puts $::cdl_header "#define HAL_PLATFORM_EXTRA \"\"" + } + } + + cdl_option CYGPKG_HAL_CORTEXM_STM32_STM3240G_EVAL { + display "Platform definitions for STM3240G-EVAL (F4) board." + active_if { CYGHWR_HAL_CORTEXM_STM32_FAMILY == "F4" } + no_define + calculated 1 + define_proc { + puts $::cdl_system_header "#define CYGBLD_HAL_TARGET_H <pkgconf/hal_cortexm.h>" + puts $::cdl_system_header "#define CYGBLD_HAL_VARIANT_H <pkgconf/hal_cortexm_stm32.h>" + puts $::cdl_system_header "#define CYGBLD_HAL_PLATFORM_H <pkgconf/hal_cortexm_stm32_stm32x0g_eval.h>" + puts $::cdl_header "#define HAL_PLATFORM_CPU \"Cortex-M4\"" + puts $::cdl_header "#define HAL_PLATFORM_BOARD \"ST STM3240G-EVAL\"" + puts $::cdl_header "#define HAL_PLATFORM_EXTRA \"\"" + } + implements CYGINT_HAL_FPV4_SP_D16 + } + + cdl_component CYG_HAL_STARTUP { + display "Startup type" + flavor data + default_value {"RAM"} + legal_values {"RAM" "SRAM" "ROM" "ROMINT" "JTAG"} + no_define + define -file system.h CYG_HAL_STARTUP + description " + When targetting the ST STM32X0G EVAL board it is possible to + build the system for either RAM bootstrap or ROM bootstrap. + Select 'RAM' when building programs to load into RAM using onboard + debug software such as RedBoot or eCos GDB stubs. Select 'ROM' + when building a stand-alone application which will be put + into ROM. The 'JTAG' type allows programs to be downloaded using a + JTAG debugger such as a BDI3000 or PEEDI. The 'SRAM' type allows + programs to be downloaded via a JTAG debugger into on-chip SRAM. + The 'ROMINT' type supports applications with code in on-chip flash + and data/bss in on-chip SRAM, ignoring the external SRAM." + } + + cdl_component CYGHWR_MEMORY_LAYOUT { + display "Memory layout" + flavor data + no_define + calculated { (CYG_HAL_STARTUP == "RAM" ) ? "cortexm_stm32x0g_eval_ram" : + (CYG_HAL_STARTUP == "SRAM" ) ? "cortexm_stm32x0g_eval_sram" : + (CYG_HAL_STARTUP == "ROM" ) ? "cortexm_stm32x0g_eval_rom" : + (CYG_HAL_STARTUP == "ROMINT" ) ? "cortexm_stm32x0g_eval_romint" : + (CYG_HAL_STARTUP == "JTAG" ) ? "cortexm_stm32x0g_eval_jtag" : + "undefined" } + + cdl_option CYGHWR_MEMORY_LAYOUT_LDI { + display "Memory layout linker script fragment" + flavor data + no_define + define -file system.h CYGHWR_MEMORY_LAYOUT_LDI + calculated { "<pkgconf/mlt_" . CYGHWR_MEMORY_LAYOUT . ".ldi>" } + } + + cdl_option CYGHWR_MEMORY_LAYOUT_H { + display "Memory layout header file" + flavor data + no_define + define -file system.h CYGHWR_MEMORY_LAYOUT_H + calculated { "<pkgconf/mlt_" . CYGHWR_MEMORY_LAYOUT . ".h>" } + } + + } + + cdl_option CYGARC_HAL_CORTEXM_STM32_INPUT_CLOCK { + display "Input Clock frequency" + flavor data + default_value 25000000 + legal_values 0 to 1000000000 + description "Main clock input." + } + + cdl_option CYGNUM_HAL_CORTEXM_STM32_FLASH_WAIT_STATES { + display "Flash read wait states" + flavor data + default_value { (CYGHWR_HAL_CORTEXM_STM32_FAMILY == "F2") ? 3 : 5 } + legal_values 0 to 7 + description " + This option gives the number of wait states to use for accessing + the flash for reads. The correct setting for this value depends + on both the CPU clock (HCLK) frequency and the voltage. Consult + the STM32 Flash programming manual (PM0059) for appropriate + values for different clock speeds or voltages. The default of + 3 reflects a supply voltage of 3.3V and HCLK of 120MHz." + } + + cdl_option CYGHWR_HAL_CORTEXM_STM32_FLASH { + display "Flash driver support" + parent CYGPKG_IO_FLASH + active_if CYGPKG_IO_FLASH + compile -library=libextras.a stm32x0g_eval_flash.c + default_value 1 + description "Control flash device support for STM32X0G-EVAL board." + } + + cdl_component CYGPKG_HAL_CORTEXM_STM32_STM32X0G_EVAL_ETH0 { + display "STM32 Ethernet support" + description " + Hardware specifics for the ethernet interface provided on the + STM32X0G-EVAL board." + parent CYGPKG_IO_ETH_DRIVERS + active_if CYGPKG_IO_ETH_DRIVERS + default_value 1 + requires CYGPKG_DEVS_ETH_CORTEXM_STM32 + requires { is_active(CYGPKG_DEVS_ETH_PHY) implies + (1 == CYGHWR_DEVS_ETH_PHY_DP8384X) } + requires { is_active(CYGHWR_HAL_CORTEXM_STM32X0G_ETH_PHY_CLOCK_MCO) implies \ + (CYGHWR_DEVS_ETH_CORTEXM_STM32_PHY_CLK_MCO == CYGHWR_HAL_CORTEXM_STM32X0G_ETH_PHY_CLOCK_MCO) } + requires { "MII" == CYGSEM_DEVS_ETH_CORTEXM_STM32_INTF } + + cdl_option CYGHWR_HAL_CORTEXM_STM32X0G_ETH_PHY_CLOCK_MCO { + display "Use MCO as PHY clock" + default_value 1 + description " + The STM32X0G can use the MCO clock signals as the 25MHz clock for + the PHY, or it can use the onboard 25MHz crystal at X1, depending + on the setting of jumper J5. This option should be set to reflect + the J5 setting." + } + } + + implements CYGINT_HAL_VIRTUAL_VECTOR_VPRINTF + + # The 9-pin D connector is connected to PC10 and PC11, which are connected to + # USART3 or UART4 depending on pin config. The main difference between these + # ports is that UART4 doesn't support hardware flow control. This board doesn't + # have the flow control lines hooked up anyway, so to save having to fiddle + # with ignoring the flow control lines on USART3, we choose to use UART4. + # Note that this is UART4 in STM32 speak (counting from 1), but the STM32 port + # uses the name UART3 for it (counting from 0). Hrm. + implements CYGINT_HAL_STM32_UART3 + + cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS { + display "Number of communication channels on the board" + flavor data + calculated 1 + } + + cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL { + display "Debug serial port" + active_if CYGPRI_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_CONFIGURABLE + flavor data + calculated 0 + description " + The ST STM32X0G EVAL board has one serial port. This option + informs the rest of the system which port will be used to connect + to a host running GDB." + } + + cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL { + display "Diagnostic serial port" + active_if CYGPRI_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_CONFIGURABLE + flavor data + calculated 0 + description " + The ST STM32X0G EVAL has one serial port. This option + informs the rest of the system which port will be used for + diagnostic output." + } + + cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD { + display "Console serial port baud rate" + flavor data + legal_values 9600 19200 38400 57600 115200 + default_value 115200 + description " + This option controls the default baud rate used for the + console connection. + RedBoot usess polling to transfer data over this port and + might not be able to keep up with baud rates above the + default, particularly when doing XYZmodem downloads. The + interrupt-driven device driver is able to handle these + baud rates, so any high speed application transfers should + use that instead. + Note: this should match the value chosen for the GDB port if the + diagnostic and GDB port are the same." + } + + cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_BAUD { + display "GDB serial port baud rate" + flavor data + legal_values 9600 19200 38400 57600 115200 + default_value 115200 + # Only one channel on this board so: + requires { CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_BAUD == CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD } + description " + This option controls the default baud rate used for the + GDB connection. + RedBoot usess polling to transfer data over this port and + might not be able to keep up with baud rates above the + default, particularly when doing XYZmodem downloads. The + interrupt-driven device driver is able to handle these + baud rates, so any high speed application transfers should + use that instead. + Note: this should match the value chosen for the console port if the + console and GDB port are the same." + } + + cdl_component CYGBLD_GLOBAL_OPTIONS { + display "Global build options" + flavor none + parent CYGPKG_NONE + description " + Global build options including control over + compiler flags, linker flags and choice of toolchain." + + + cdl_option CYGBLD_GLOBAL_COMMAND_PREFIX { + display "Global command prefix" + flavor data + no_define + default_value { "arm-eabi" } + description " + This option specifies the command prefix used when + invoking the build tools." + } + + cdl_option CYGBLD_GLOBAL_CFLAGS { + display "Global compiler flags" + flavor data + no_define + default_value { CYGBLD_GLOBAL_WARNFLAGS . "-mcpu=cortex-m3 -mthumb -g -O2 -ffunction-sections -fdata-sections -fno-rtti -fno-exceptions" } + description " + This option controls the global compiler flags which are used to + compile all packages by default. Individual packages may define + options which override these global flags." + } + + cdl_option CYGBLD_GLOBAL_LDFLAGS { + display "Global linker flags" + flavor data + no_define + default_value { "-mcpu=cortex-m3 -mthumb -Wl,--gc-sections -Wl,-static -Wl,-n -g -nostdlib" } + description " + This option controls the global linker flags. Individual + packages may define options which override these global flags." + } + } + + cdl_component CYGPKG_HAL_CORTEXM_STM32_STM32X0G_EVAL_OPTIONS { + display "STM32X0G HAL build options" + flavor none + description " + Package specific build options including control over + compiler flags used only in building this HAL." + + cdl_option CYGPKG_HAL_CORTEXM_STM32_STM32X0G_EVAL_CFLAGS_ADD { + display "Additional compiler flags" + flavor data + no_define + default_value { "-Werror" } + description " + This option modifies the set of compiler flags + for building this HAL. These flags are used + in addition to the set of global flags." + } + cdl_option CYGPKG_HAL_CORTEXM_STM32_STM32X0G_EVAL_CFLAGS_REMOVE { + display "Suppressed compiler flags" + flavor data + no_define + default_value { "" } + description " + This option modifies the set of compiler flags + for building this HAL. These flags are + removed from the set of global flags if + present." + } + } + + cdl_option CYGSEM_HAL_ROM_MONITOR { + display "Behave as a ROM monitor" + flavor bool + default_value 0 + parent CYGPKG_HAL_ROM_MONITOR + requires { CYG_HAL_STARTUP == "ROM" || CYG_HAL_STARTUP == "ROMINT" || CYG_HAL_STARTUP == "JTAG" } + requires { CYGDBG_HAL_CRCTABLE_LOCATION == "ROM" } + description " + Enable this option if this program is to be used as a ROM monitor, + i.e. applications will be loaded into RAM on the board, and this + ROM monitor may process exceptions or interrupts generated from the + application. This enables features such as utilizing a separate + interrupt stack when exceptions are generated." + } + + cdl_option CYGSEM_HAL_USE_ROM_MONITOR { + display "Work with a ROM monitor" + flavor booldata + legal_values { "Generic" "GDB_stubs" } + default_value { CYG_HAL_STARTUP == "RAM" ? "GDB_stubs" : 0 } + parent CYGPKG_HAL_ROM_MONITOR + requires { CYG_HAL_STARTUP == "RAM" } + description " + Support can be enabled for different varieties of ROM monitor. + This support changes various eCos semantics such as the encoding + of diagnostic output, or the overriding of hardware interrupt + vectors. + Firstly there is \"Generic\" support which prevents the HAL + from overriding the hardware vectors that it does not use, to + instead allow an installed ROM monitor to handle them. This is + the most basic support which is likely to be common to most + implementations of ROM monitor. + \"GDB_stubs\" provides support when GDB stubs are included in + the ROM monitor or boot ROM." + } + + cdl_component CYGPKG_REDBOOT_HAL_OPTIONS { + display "Redboot HAL options" + flavor none + no_define + parent CYGPKG_REDBOOT + active_if CYGPKG_REDBOOT + description " + This option lists the target's requirements for a valid Redboot + configuration." + + requires { (CYGHWR_HAL_CORTEXM_STM32_FAMILY == "F2") implies (CYGBLD_REDBOOT_MAX_MEM_SEGMENTS == 2) } + requires { (CYGHWR_HAL_CORTEXM_STM32_FAMILY == "F4") implies (CYGBLD_REDBOOT_MAX_MEM_SEGMENTS == 3) } + + cdl_option CYGBLD_BUILD_REDBOOT_BIN { + display "Build Redboot ROM binary images" + active_if CYGBLD_BUILD_REDBOOT + default_value 1 + no_define + description "This option enables the conversion of the Redboot ELF + image to binary image formats suitable for ROM programming." + + make -priority 325 { + <PREFIX>/bin/redboot.bin : <PREFIX>/bin/redboot.elf + $(OBJCOPY) --strip-debug $< $(@:.bin=.img) + $(OBJCOPY) -O srec $< $(@:.bin=.srec) + $(OBJCOPY) -O binary $< $@ + } + } + } + + cdl_component CYGBLD_HAL_CORTEXM_STM32X0G_EVAL_GDB_STUBS { + display "Create StubROM SREC and binary files" + active_if CYGBLD_BUILD_COMMON_GDB_STUBS + no_define + calculated 1 + requires { CYG_HAL_STARTUP == "ROM" || CYG_HAL_STARTUP == "ROMINT" } + + make -priority 325 { + <PREFIX>/bin/stubrom.srec : <PREFIX>/bin/gdb_module.img + $(OBJCOPY) -O srec $< $@ + } + make -priority 325 { + <PREFIX>/bin/stubrom.bin : <PREFIX>/bin/gdb_module.img + $(OBJCOPY) -O binary $< $@ + } + + description "This component causes the ELF image generated by the + build process to be converted to S-Record and binary + files." + } +} + +# EOF hal_cortexm_stm32_stm32x0g_eval.cdl diff --git a/ecos/packages/hal/cortexm/stm32/stm32x0g_eval/current/include/pkgconf/mlt_cortexm_stm32x0g_eval_jtag.h b/ecos/packages/hal/cortexm/stm32/stm32x0g_eval/current/include/pkgconf/mlt_cortexm_stm32x0g_eval_jtag.h new file mode 100644 index 0000000..e3f51d7 --- /dev/null +++ b/ecos/packages/hal/cortexm/stm32/stm32x0g_eval/current/include/pkgconf/mlt_cortexm_stm32x0g_eval_jtag.h @@ -0,0 +1,26 @@ +// eCos memory layout + +#ifndef __ASSEMBLER__ +#include <cyg/infra/cyg_type.h> +#include <stddef.h> + +#endif +#define CYGMEM_REGION_sram (0x20000000) +#define CYGMEM_REGION_sram_SIZE (0x00020000-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE) +#define CYGMEM_REGION_sram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) +#if defined(CYGHWR_HAL_CORTEXM_STM32_FAMILY_F4) +#define CYGMEM_REGION_ccm (0x10000000) +#define CYGMEM_REGION_ccm_SIZE (0x00010000) +#define CYGMEM_REGION_ccm_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) +#endif // CYGHWR_HAL_CORTEXM_STM32_FAMILY_F4 +#define CYGMEM_REGION_flash (0x08000000) +#define CYGMEM_REGION_flash_SIZE (0x00100000) +#define CYGMEM_REGION_flash_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) +#define CYGMEM_REGION_ram (0x64000000) +#define CYGMEM_REGION_ram_SIZE (0x00200000) +#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) +#ifndef __ASSEMBLER__ +extern char CYG_LABEL_NAME (__heap1) []; +#endif +#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1)) +#define CYGMEM_SECTION_heap1_SIZE (CYGMEM_REGION_ram+CYGMEM_REGION_ram_SIZE - (size_t) CYG_LABEL_NAME (__heap1)) diff --git a/ecos/packages/hal/cortexm/stm32/stm32x0g_eval/current/include/pkgconf/mlt_cortexm_stm32x0g_eval_jtag.ldi b/ecos/packages/hal/cortexm/stm32/stm32x0g_eval/current/include/pkgconf/mlt_cortexm_stm32x0g_eval_jtag.ldi new file mode 100644 index 0000000..03cbd9a --- /dev/null +++ b/ecos/packages/hal/cortexm/stm32/stm32x0g_eval/current/include/pkgconf/mlt_cortexm_stm32x0g_eval_jtag.ldi @@ -0,0 +1,50 @@ +// eCos memory layout + +#include <pkgconf/hal.h> +#include <cyg/infra/cyg_type.inc> + +MEMORY +{ + sram : ORIGIN = 0x20000000, LENGTH = 0x00020000-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE + flash : ORIGIN = 0x08000000, LENGTH = 0x00100000 + ram : ORIGIN = 0x64000000, LENGTH = 0x00200000 +#if defined(CYGHWR_HAL_CORTEXM_STM32_FAMILY_F4) + ccm : ORIGIN = 0x10000000, LENGTH = 0x00010000 +#endif // CYGHWR_HAL_CORTEXM_STM32_FAMILY_F4 +} + +hal_vsr_table = 0x20000000; +// 97 or 98 entries in this VSR table depending on the processor family +#if defined(CYGHWR_HAL_CORTEXM_STM32_FAMILY_F2) +hal_virtual_vector_table = hal_vsr_table + 97*4; +#elif defined(CYGHWR_HAL_CORTEXM_STM32_FAMILY_F4) +hal_virtual_vector_table = hal_vsr_table + 98*4; +#endif +#if defined(CYGSEM_HAL_VIRTUAL_VECTOR_SUPPORT) +hal_virtual_vector_table_end = hal_virtual_vector_table + 64*4; +#else // zero size virtual vector table +hal_virtual_vector_table_end = hal_virtual_vector_table; +#endif + +// SRAM is 128k. +hal_startup_stack = 0x20000000 + 1024*128; + +SECTIONS +{ + SECTIONS_BEGIN + SECTION_sram (sram, hal_virtual_vector_table_end, LMA_EQ_VMA) + SECTION_rom_vectors (ram, 0x64000000, LMA_EQ_VMA) + SECTION_RELOCS (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_text (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_fini (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_rodata (ram, ALIGN(0x8), LMA_EQ_VMA) + SECTION_rodata1 (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_fixup (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_gcc_except_table (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_eh_frame (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_got (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_data (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_bss (ram, ALIGN (0x8), LMA_EQ_VMA) + CYG_LABEL_DEFN(__heap1) = ALIGN (0x8); + SECTIONS_END +} diff --git a/ecos/packages/hal/cortexm/stm32/stm32x0g_eval/current/include/pkgconf/mlt_cortexm_stm32x0g_eval_ram.h b/ecos/packages/hal/cortexm/stm32/stm32x0g_eval/current/include/pkgconf/mlt_cortexm_stm32x0g_eval_ram.h new file mode 100644 index 0000000..1ce0565 --- /dev/null +++ b/ecos/packages/hal/cortexm/stm32/stm32x0g_eval/current/include/pkgconf/mlt_cortexm_stm32x0g_eval_ram.h @@ -0,0 +1,28 @@ +// eCos memory layout + +#ifndef __ASSEMBLER__ +#include <cyg/infra/cyg_type.h> +#include <stddef.h> + +#endif +#define CYGMEM_REGION_sram (0x20000000) +#define CYGMEM_REGION_sram_SIZE (0x00020000) +#define CYGMEM_REGION_sram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) +#if defined(CYGHWR_HAL_CORTEXM_STM32_FAMILY_F4) +#define CYGMEM_REGION_ccm (0x10000000) +#define CYGMEM_REGION_ccm_SIZE (0x00010000) +#define CYGMEM_REGION_ccm_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) +#endif // CYGHWR_HAL_CORTEXM_STM32_FAMILY_F4 +#define CYGMEM_REGION_flash (0x08000000) +#define CYGMEM_REGION_flash_SIZE (0x00100000) +#define CYGMEM_REGION_flash_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) +#define CYGMEM_REGION_ram (0x64000000) +#define CYGMEM_REGION_ram_SIZE (0x00200000-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE) +#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) + +#ifndef __ASSEMBLER__ +extern char CYG_LABEL_NAME (__heap1) []; +#endif +#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1)) +#define CYGMEM_SECTION_heap1_SIZE (CYGMEM_REGION_ram+CYGMEM_REGION_ram_SIZE - (size_t) CYG_LABEL_NAME (__heap1)) + diff --git a/ecos/packages/hal/cortexm/stm32/stm32x0g_eval/current/include/pkgconf/mlt_cortexm_stm32x0g_eval_ram.ldi b/ecos/packages/hal/cortexm/stm32/stm32x0g_eval/current/include/pkgconf/mlt_cortexm_stm32x0g_eval_ram.ldi new file mode 100644 index 0000000..ea212a1 --- /dev/null +++ b/ecos/packages/hal/cortexm/stm32/stm32x0g_eval/current/include/pkgconf/mlt_cortexm_stm32x0g_eval_ram.ldi @@ -0,0 +1,50 @@ +// eCos memory layout + +#include <pkgconf/hal.h> +#include <cyg/infra/cyg_type.inc> + +MEMORY +{ + sram : ORIGIN = 0x20000000, LENGTH = 0x00020000 + flash : ORIGIN = 0x08000000, LENGTH = 0x00100000 + ram : ORIGIN = 0x64000000, LENGTH = 0x00200000-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE +#if defined(CYGHWR_HAL_CORTEXM_STM32_FAMILY_F4) + ccm : ORIGIN = 0x10000000, LENGTH = 0x00010000 +#endif // CYGHWR_HAL_CORTEXM_STM32_FAMILY_F4 +} + +hal_vsr_table = 0x20000000; +// 97 or 98 entries in this VSR table depending on the processor family +#if defined(CYGHWR_HAL_CORTEXM_STM32_FAMILY_F2) +hal_virtual_vector_table = hal_vsr_table + 97*4; +#elif defined(CYGHWR_HAL_CORTEXM_STM32_FAMILY_F4) +hal_virtual_vector_table = hal_vsr_table + 98*4; +#endif +#if defined(CYGSEM_HAL_VIRTUAL_VECTOR_SUPPORT) +hal_virtual_vector_table_end = hal_virtual_vector_table + 64*4; +#else // zero size virtual vector table +hal_virtual_vector_table_end = hal_virtual_vector_table; +#endif + +// External SRAM is 2MB +hal_startup_stack = 0x64200000; + +SECTIONS +{ + SECTIONS_BEGIN + SECTION_sram (sram, hal_virtual_vector_table_end, LMA_EQ_VMA) + SECTION_rom_vectors (ram, 0x64008000, LMA_EQ_VMA) + SECTION_RELOCS (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_text (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_fini (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_rodata (ram, ALIGN(0x8), LMA_EQ_VMA) + SECTION_rodata1 (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_fixup (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_gcc_except_table (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_eh_frame (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_got (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_data (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_bss (ram, ALIGN (0x8), LMA_EQ_VMA) + CYG_LABEL_DEFN(__heap1) = ALIGN (0x8); + SECTIONS_END +} diff --git a/ecos/packages/hal/cortexm/stm32/stm32x0g_eval/current/include/pkgconf/mlt_cortexm_stm32x0g_eval_rom.h b/ecos/packages/hal/cortexm/stm32/stm32x0g_eval/current/include/pkgconf/mlt_cortexm_stm32x0g_eval_rom.h new file mode 100644 index 0000000..e3f51d7 --- /dev/null +++ b/ecos/packages/hal/cortexm/stm32/stm32x0g_eval/current/include/pkgconf/mlt_cortexm_stm32x0g_eval_rom.h @@ -0,0 +1,26 @@ +// eCos memory layout + +#ifndef __ASSEMBLER__ +#include <cyg/infra/cyg_type.h> +#include <stddef.h> + +#endif +#define CYGMEM_REGION_sram (0x20000000) +#define CYGMEM_REGION_sram_SIZE (0x00020000-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE) +#define CYGMEM_REGION_sram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) +#if defined(CYGHWR_HAL_CORTEXM_STM32_FAMILY_F4) +#define CYGMEM_REGION_ccm (0x10000000) +#define CYGMEM_REGION_ccm_SIZE (0x00010000) +#define CYGMEM_REGION_ccm_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) +#endif // CYGHWR_HAL_CORTEXM_STM32_FAMILY_F4 +#define CYGMEM_REGION_flash (0x08000000) +#define CYGMEM_REGION_flash_SIZE (0x00100000) +#define CYGMEM_REGION_flash_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) +#define CYGMEM_REGION_ram (0x64000000) +#define CYGMEM_REGION_ram_SIZE (0x00200000) +#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) +#ifndef __ASSEMBLER__ +extern char CYG_LABEL_NAME (__heap1) []; +#endif +#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1)) +#define CYGMEM_SECTION_heap1_SIZE (CYGMEM_REGION_ram+CYGMEM_REGION_ram_SIZE - (size_t) CYG_LABEL_NAME (__heap1)) diff --git a/ecos/packages/hal/cortexm/stm32/stm32x0g_eval/current/include/pkgconf/mlt_cortexm_stm32x0g_eval_rom.ldi b/ecos/packages/hal/cortexm/stm32/stm32x0g_eval/current/include/pkgconf/mlt_cortexm_stm32x0g_eval_rom.ldi new file mode 100644 index 0000000..c5c7c5f --- /dev/null +++ b/ecos/packages/hal/cortexm/stm32/stm32x0g_eval/current/include/pkgconf/mlt_cortexm_stm32x0g_eval_rom.ldi @@ -0,0 +1,51 @@ +// eCos memory layout + +#include <pkgconf/hal.h> +#include <cyg/infra/cyg_type.inc> + +MEMORY +{ + sram : ORIGIN = 0x20000000, LENGTH = 0x00020000-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE + flash : ORIGIN = 0x08000000, LENGTH = 0x00100000 + ram : ORIGIN = 0x64000000, LENGTH = 0x00200000 +#if defined(CYGHWR_HAL_CORTEXM_STM32_FAMILY_F4) + ccm : ORIGIN = 0x10000000, LENGTH = 0x00010000 +#endif // CYGHWR_HAL_CORTEXM_STM32_FAMILY_F4 +} + + +hal_vsr_table = 0x20000000; +// 97 or 98 entries in this VSR table depending on the processor family +#if defined(CYGHWR_HAL_CORTEXM_STM32_FAMILY_F2) +hal_virtual_vector_table = hal_vsr_table + 97*4; +#elif defined(CYGHWR_HAL_CORTEXM_STM32_FAMILY_F4) +hal_virtual_vector_table = hal_vsr_table + 98*4; +#endif +#if defined(CYGSEM_HAL_VIRTUAL_VECTOR_SUPPORT) +hal_virtual_vector_table_end = hal_virtual_vector_table + 64*4; +#else // zero size virtual vector table +hal_virtual_vector_table_end = hal_virtual_vector_table; +#endif + +// SRAM is 128k. +hal_startup_stack = 0x20000000 + 1024*128; + +SECTIONS +{ + SECTIONS_BEGIN + SECTION_rom_vectors (flash, 0x08000000, LMA_EQ_VMA) + SECTION_RELOCS (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_text (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_fini (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_rodata (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_rodata1 (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_fixup (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_gcc_except_table (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_eh_frame (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_got (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_sram (sram, hal_virtual_vector_table_end, FOLLOWING (.got)) + SECTION_data (ram, 0x64000000, FOLLOWING (.sram)) + SECTION_bss (ram, ALIGN (0x8), LMA_EQ_VMA) + CYG_LABEL_DEFN(__heap1) = ALIGN (0x8); + SECTIONS_END +} diff --git a/ecos/packages/hal/cortexm/stm32/stm32x0g_eval/current/include/pkgconf/mlt_cortexm_stm32x0g_eval_romint.h b/ecos/packages/hal/cortexm/stm32/stm32x0g_eval/current/include/pkgconf/mlt_cortexm_stm32x0g_eval_romint.h new file mode 100644 index 0000000..d265178 --- /dev/null +++ b/ecos/packages/hal/cortexm/stm32/stm32x0g_eval/current/include/pkgconf/mlt_cortexm_stm32x0g_eval_romint.h @@ -0,0 +1,26 @@ +// eCos memory layout + +#ifndef __ASSEMBLER__ +#include <cyg/infra/cyg_type.h> +#include <stddef.h> + +#endif +#define CYGMEM_REGION_ram (0x20000000) +#define CYGMEM_REGION_ram_SIZE (0x00020000-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE) +#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) +#if defined(CYGHWR_HAL_CORTEXM_STM32_FAMILY_F4) +#define CYGMEM_REGION_ccm (0x10000000) +#define CYGMEM_REGION_ccm_SIZE (0x00010000) +#define CYGMEM_REGION_ccm_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) +#endif // CYGHWR_HAL_CORTEXM_STM32_FAMILY_F4 +#define CYGMEM_REGION_flash (0x08000000) +#define CYGMEM_REGION_flash_SIZE (0x00100000) +#define CYGMEM_REGION_flash_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) +#define CYGMEM_REGION_xram (0x64000000) +#define CYGMEM_REGION_xram_SIZE (0x00200000) +#define CYGMEM_REGION_xram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) +#ifndef __ASSEMBLER__ +extern char CYG_LABEL_NAME (__heap1) []; +#endif +#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1)) +#define CYGMEM_SECTION_heap1_SIZE (CYGMEM_REGION_ram+CYGMEM_REGION_ram_SIZE - (size_t) CYG_LABEL_NAME (__heap1)) diff --git a/ecos/packages/hal/cortexm/stm32/stm32x0g_eval/current/include/pkgconf/mlt_cortexm_stm32x0g_eval_romint.ldi b/ecos/packages/hal/cortexm/stm32/stm32x0g_eval/current/include/pkgconf/mlt_cortexm_stm32x0g_eval_romint.ldi new file mode 100644 index 0000000..cdfa7eb --- /dev/null +++ b/ecos/packages/hal/cortexm/stm32/stm32x0g_eval/current/include/pkgconf/mlt_cortexm_stm32x0g_eval_romint.ldi @@ -0,0 +1,50 @@ +// eCos memory layout + +#include <pkgconf/hal.h> +#include <cyg/infra/cyg_type.inc> + +MEMORY +{ + ram : ORIGIN = 0x20000000, LENGTH = 0x00020000-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE + flash : ORIGIN = 0x08000000, LENGTH = 0x00100000 + xram : ORIGIN = 0x64000000, LENGTH = 0x00200000 +#if defined(CYGHWR_HAL_CORTEXM_STM32_FAMILY_F4) + ccm : ORIGIN = 0x10000000, LENGTH = 0x00010000 +#endif // CYGHWR_HAL_CORTEXM_STM32_FAMILY_F4 +} + +hal_vsr_table = 0x20000000; +// 97 or 98 entries in this VSR table depending on the processor family +#if defined(CYGHWR_HAL_CORTEXM_STM32_FAMILY_F2) +hal_virtual_vector_table = hal_vsr_table + 97*4; +#elif defined(CYGHWR_HAL_CORTEXM_STM32_FAMILY_F4) +hal_virtual_vector_table = hal_vsr_table + 98*4; +#endif +#if defined(CYGSEM_HAL_VIRTUAL_VECTOR_SUPPORT) +hal_virtual_vector_table_end = hal_virtual_vector_table + 64*4; +#else // zero size virtual vector table +hal_virtual_vector_table_end = hal_virtual_vector_table; +#endif + +// SRAM is 128k. +hal_startup_stack = 0x20000000 + 1024*128; + +SECTIONS +{ + SECTIONS_BEGIN + SECTION_rom_vectors (flash, 0x08000000, LMA_EQ_VMA) + SECTION_RELOCS (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_text (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_fini (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_rodata (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_rodata1 (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_fixup (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_gcc_except_table (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_eh_frame (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_got (flash, ALIGN (0x8), LMA_EQ_VMA) + SECTION_sram (ram, hal_virtual_vector_table_end, FOLLOWING (.got)) + SECTION_data (ram, ALIGN( 0x8), FOLLOWING (.sram)) + SECTION_bss (ram, ALIGN (0x8), LMA_EQ_VMA) + CYG_LABEL_DEFN(__heap1) = ALIGN (0x8); + SECTIONS_END +} diff --git a/ecos/packages/hal/cortexm/stm32/stm32x0g_eval/current/include/pkgconf/mlt_cortexm_stm32x0g_eval_sram.h b/ecos/packages/hal/cortexm/stm32/stm32x0g_eval/current/include/pkgconf/mlt_cortexm_stm32x0g_eval_sram.h new file mode 100644 index 0000000..99dcbe9 --- /dev/null +++ b/ecos/packages/hal/cortexm/stm32/stm32x0g_eval/current/include/pkgconf/mlt_cortexm_stm32x0g_eval_sram.h @@ -0,0 +1,28 @@ +// eCos memory layout + +#ifndef __ASSEMBLER__ +#include <cyg/infra/cyg_type.h> +#include <stddef.h> + +#endif +#define CYGMEM_REGION_sram (0x20000000) +#define CYGMEM_REGION_sram_SIZE (0x00010000-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE) +#define CYGMEM_REGION_sram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) +#if defined(CYGHWR_HAL_CORTEXM_STM32_FAMILY_F4) +#define CYGMEM_REGION_ccm (0x10000000) +#define CYGMEM_REGION_ccm_SIZE (0x00010000) +#define CYGMEM_REGION_ccm_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) +#endif // CYGHWR_HAL_CORTEXM_STM32_FAMILY_F4 +#define CYGMEM_REGION_flash (0x08000000) +#define CYGMEM_REGION_flash_SIZE (0x00100000) +#define CYGMEM_REGION_flash_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) +#define CYGMEM_REGION_ram (0x64000000) +#define CYGMEM_REGION_ram_SIZE (0x00100000) +#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) + +#ifndef __ASSEMBLER__ +extern char CYG_LABEL_NAME (__heap1) []; +#endif +#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1)) +#define CYGMEM_SECTION_heap1_SIZE (CYGMEM_REGION_sram+CYGMEM_REGION_sram_SIZE - (size_t) CYG_LABEL_NAME (__heap1)) + diff --git a/ecos/packages/hal/cortexm/stm32/stm32x0g_eval/current/include/pkgconf/mlt_cortexm_stm32x0g_eval_sram.ldi b/ecos/packages/hal/cortexm/stm32/stm32x0g_eval/current/include/pkgconf/mlt_cortexm_stm32x0g_eval_sram.ldi new file mode 100644 index 0000000..05d2bc3 --- /dev/null +++ b/ecos/packages/hal/cortexm/stm32/stm32x0g_eval/current/include/pkgconf/mlt_cortexm_stm32x0g_eval_sram.ldi @@ -0,0 +1,51 @@ +// eCos memory layout + +#include <pkgconf/hal.h> +#include <cyg/infra/cyg_type.inc> + +MEMORY +{ + sram : ORIGIN = 0x20000000, LENGTH = 0x00020000-CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE + flash : ORIGIN = 0x08000000, LENGTH = 0x00100000 + ram : ORIGIN = 0x64000000, LENGTH = 0x00200000 +#if defined(CYGHWR_HAL_CORTEXM_STM32_FAMILY_F4) + ccm : ORIGIN = 0x10000000, LENGTH = 0x00010000 +#endif // CYGHWR_HAL_CORTEXM_STM32_FAMILY_F4 +} + + +hal_vsr_table = 0x20000000; +// 97 or 98 entries in this VSR table depending on the processor family +#if defined(CYGHWR_HAL_CORTEXM_STM32_FAMILY_F2) +hal_virtual_vector_table = hal_vsr_table + 97*4; +#elif defined(CYGHWR_HAL_CORTEXM_STM32_FAMILY_F4) +hal_virtual_vector_table = hal_vsr_table + 98*4; +#endif +#if defined(CYGSEM_HAL_VIRTUAL_VECTOR_SUPPORT) +hal_virtual_vector_table_end = hal_virtual_vector_table + 64*4; +#else // zero size virtual vector table +hal_virtual_vector_table_end = hal_virtual_vector_table; +#endif + +// SRAM is 128k. +hal_startup_stack = 0x20000000 + 1024*128; + +SECTIONS +{ + SECTIONS_BEGIN + SECTION_rom_vectors (sram, hal_virtual_vector_table_end, LMA_EQ_VMA) + SECTION_RELOCS (sram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_text (sram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_fini (sram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_rodata (sram, ALIGN(0x8), LMA_EQ_VMA) + SECTION_rodata1 (sram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_fixup (sram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_gcc_except_table (sram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_eh_frame (sram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_got (sram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_data (sram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_bss (sram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_sram (sram, ALIGN (0x8), LMA_EQ_VMA) + CYG_LABEL_DEFN(__heap1) = ALIGN (0x8); + SECTIONS_END +} diff --git a/ecos/packages/hal/cortexm/stm32/stm32x0g_eval/current/include/plf_arch.h b/ecos/packages/hal/cortexm/stm32/stm32x0g_eval/current/include/plf_arch.h new file mode 100644 index 0000000..1800e7f --- /dev/null +++ b/ecos/packages/hal/cortexm/stm32/stm32x0g_eval/current/include/plf_arch.h @@ -0,0 +1,62 @@ +#ifndef CYGONCE_HAL_PLF_ARCH_H +#define CYGONCE_HAL_PLF_ARCH_H +//============================================================================= +// +// plf_arch.h +// +// Platform specific architecture overrides +// +//============================================================================= +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2008 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): nickg +// Date: 2008-07-30 +// Purpose: STM32X0G EVAL platform specific architecture overrides +// Description: +// Usage: #include <cyg/hal/plf_arch.h> +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +#include <pkgconf/hal.h> +#include <pkgconf/hal_cortexm_stm32_stm32x0g_eval.h> + + +//============================================================================= + +//----------------------------------------------------------------------------- +// end of plf_arch.h +#endif // CYGONCE_HAL_PLF_ARCH_H diff --git a/ecos/packages/hal/cortexm/stm32/stm32x0g_eval/current/include/plf_intr.h b/ecos/packages/hal/cortexm/stm32/stm32x0g_eval/current/include/plf_intr.h new file mode 100644 index 0000000..644590f --- /dev/null +++ b/ecos/packages/hal/cortexm/stm32/stm32x0g_eval/current/include/plf_intr.h @@ -0,0 +1,62 @@ +#ifndef CYGONCE_HAL_PLF_INTR_H +#define CYGONCE_HAL_PLF_INTR_H +//============================================================================= +// +// plf_intr.h +// +// Platform specific interrupt overrides +// +//============================================================================= +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2008 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): nickg +// Date: 2008-07-30 +// Purpose: STM32X0G EVAL platform specific interrupt overrides +// Description: +// Usage: #include <cyg/hal/plf_intr.h> +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +#include <pkgconf/hal.h> +#include <pkgconf/hal_cortexm_stm32_stm32x0g_eval.h> + + +//============================================================================= + +//----------------------------------------------------------------------------- +// end of plf_intr.h +#endif // CYGONCE_HAL_PLF_INTR_H diff --git a/ecos/packages/hal/cortexm/stm32/stm32x0g_eval/current/include/plf_io.h b/ecos/packages/hal/cortexm/stm32/stm32x0g_eval/current/include/plf_io.h new file mode 100644 index 0000000..3f15576 --- /dev/null +++ b/ecos/packages/hal/cortexm/stm32/stm32x0g_eval/current/include/plf_io.h @@ -0,0 +1,171 @@ +#ifndef CYGONCE_HAL_PLF_IO_H +#define CYGONCE_HAL_PLF_IO_H +//============================================================================= +// +// plf_io.h +// +// Platform specific registers +// +//============================================================================= +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2008, 2011 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): nickg +// Date: 2008-07-30 +// Purpose: STM32X0G EVAL platform specific registers +// Description: +// Usage: #include <cyg/hal/plf_io.h> +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +#include <pkgconf/hal.h> +#include <pkgconf/hal_cortexm_stm32_stm32x0g_eval.h> + +//============================================================================= +// Memory access checks. +// +// Accesses to areas not backed by real devices or memory can cause +// the CPU to hang. These macros allow the GDB stubs to avoid making +// accidental accesses to these areas. + +__externC int cyg_hal_stub_permit_data_access( CYG_ADDRESS addr, cyg_uint32 count ); + +#define CYG_HAL_STUB_PERMIT_DATA_READ(_addr_, _count_) cyg_hal_stub_permit_data_access( _addr_, _count_ ) + +#define CYG_HAL_STUB_PERMIT_DATA_WRITE(_addr_, _count_ ) cyg_hal_stub_permit_data_access( _addr_, _count_ ) + +//============================================================================= +// Board LEDs + +#define CYGHWR_HAL_STM32X0G_LED1 CYGHWR_HAL_STM32_PIN_OUT( G, 6, PUSHPULL, NONE, LOW ) +#define CYGHWR_HAL_STM32X0G_LED2 CYGHWR_HAL_STM32_PIN_OUT( G, 8, PUSHPULL, NONE, LOW ) +#define CYGHWR_HAL_STM32X0G_LED3 CYGHWR_HAL_STM32_PIN_OUT( I, 9, PUSHPULL, NONE, LOW ) +#define CYGHWR_HAL_STM32X0G_LED4 CYGHWR_HAL_STM32_PIN_OUT( C, 7, PUSHPULL, NONE, LOW ) + +// A convenience function to set LEDs. Lowest 4 bits of 'c' correspond to the 4 LEDs. +__externC void hal_stm32x0_led(char c); + +//============================================================================= +// Custom Ethernet pin mappings + +#define CYGHWR_HAL_STM32_ETH_MII_TX_CRS CYGHWR_HAL_STM32_PIN_ALTFN_IN( H, 2, 11, OPENDRAIN, NONE ) +#define CYGHWR_HAL_STM32_ETH_MII_COL CYGHWR_HAL_STM32_PIN_ALTFN_IN( H, 3, 11, OPENDRAIN, NONE ) +#define CYGHWR_HAL_STM32_ETH_MII_RXD2 CYGHWR_HAL_STM32_PIN_ALTFN_IN( H, 6, 11, OPENDRAIN, NONE ) +#define CYGHWR_HAL_STM32_ETH_MII_RXD3 CYGHWR_HAL_STM32_PIN_ALTFN_IN( H, 7, 11, OPENDRAIN, NONE ) +#define CYGHWR_HAL_STM32_ETH_MII_TXD3 CYGHWR_HAL_STM32_PIN_ALTFN_OUT( B, 8, 11, PUSHPULL, NONE, AT_LEAST(50) ) +#define CYGHWR_HAL_STM32_ETH_MII_RX_ER CYGHWR_HAL_STM32_PIN_ALTFN_IN( I, 10, 11, OPENDRAIN, NONE ) +#define CYGHWR_HAL_STM32_ETH_MII_TX_EN CYGHWR_HAL_STM32_PIN_ALTFN_OUT( G, 11, 11, PUSHPULL, NONE, AT_LEAST(50) ) +#define CYGHWR_HAL_STM32_ETH_MII_TXD0 CYGHWR_HAL_STM32_PIN_ALTFN_OUT( G, 13, 11, PUSHPULL, NONE, AT_LEAST(50) ) +#define CYGHWR_HAL_STM32_ETH_MII_TXD1 CYGHWR_HAL_STM32_PIN_ALTFN_OUT( G, 14, 11, PUSHPULL, NONE, AT_LEAST(50) ) +// NOTE: CYGHWR_HAL_STM32_ETH_MII_PPS_OUT not defined + +#define CYGHWR_HAL_STM32_ETH_CONFIGURE_MCO() \ + CYG_MACRO_START \ + cyg_uint32 cfgr; \ + HAL_READ_UINT32( CYGHWR_HAL_STM32_RCC + CYGHWR_HAL_STM32_RCC_CFGR, cfgr ); \ + cfgr &= ~CYGHWR_HAL_STM32_RCC_CFGR_MCO1_MASK; \ + cfgr |= CYGHWR_HAL_STM32_RCC_CFGR_MCO1_HSE; \ + cfgr &= ~CYGHWR_HAL_STM32_RCC_CFGR_MCO1PRE_MASK; \ + cfgr |= CYGHWR_HAL_STM32_RCC_CFGR_MCO1PRE_1; \ + HAL_WRITE_UINT32( CYGHWR_HAL_STM32_RCC + CYGHWR_HAL_STM32_RCC_CFGR, cfgr ); \ + CYG_MACRO_END + +//============================================================================= +// GPIO pin and DMA definitions for each SPI bus + +// NOTE: The SPEED_SPI manifest is declared by the device driver +// (e.g. "devs/spi/cortexm/stm32/<vsn>/src/spi_stm32.c") and is not +// currently defined in a header. + +#ifndef CYGHWR_HAL_STM32_SPI1_REMAP +#define CYGHWR_HAL_STM32_SPI1_SCK CYGHWR_HAL_STM32_PIN_ALTFN_OUT( A, 5, 5, PUSHPULL, NONE, SPEED_SPI ) +#define CYGHWR_HAL_STM32_SPI1_MISO CYGHWR_HAL_STM32_PIN_ALTFN_IN( A, 6, 5, NA, PULLUP ) +#define CYGHWR_HAL_STM32_SPI1_MOSI CYGHWR_HAL_STM32_PIN_ALTFN_OUT( A, 7, 5, PUSHPULL, NONE, SPEED_SPI ) +#else +#define CYGHWR_HAL_STM32_SPI1_SCK CYGHWR_HAL_STM32_PIN_ALTFN_OUT( B, 3, 5, PUSHPULL, NONE, SPEED_SPI ) +#define CYGHWR_HAL_STM32_SPI1_MISO CYGHWR_HAL_STM32_PIN_ALTFN_IN( B, 4, 5, NA, PULLUP ) +#define CYGHWR_HAL_STM32_SPI1_MOSI CYGHWR_HAL_STM32_PIN_ALTFN_OUT( B, 5, 5, PUSHPULL, NONE, SPEED_SPI ) +#endif +#define CYGHWR_HAL_STM32_SPI1_REMAP_CONFIG 0 + +#define CYGHWR_HAL_STM32_SPI1_DMA_TX CYGHWR_HAL_STM32_DMA( 2, 3, 3, M2P ) +#define CYGHWR_HAL_STM32_SPI1_DMA_RX CYGHWR_HAL_STM32_DMA( 2, 0, 3, P2M ) + + + +#define CYGHWR_HAL_STM32_SPI2_SCK CYGHWR_HAL_STM32_PIN_ALTFN_OUT( I, 1, 5, PUSHPULL, NONE, SPEED_SPI ) +#define CYGHWR_HAL_STM32_SPI2_MISO CYGHWR_HAL_STM32_PIN_ALTFN_IN( I, 2, 5, NA, PULLUP ) +#define CYGHWR_HAL_STM32_SPI2_MOSI CYGHWR_HAL_STM32_PIN_ALTFN_OUT( I, 3, 5, PUSHPULL, NONE, SPEED_SPI ) +#define CYGHWR_HAL_STM32_SPI2_REMAP_CONFIG 0 + +#define CYGHWR_HAL_STM32_SPI2_DMA_TX CYGHWR_HAL_STM32_DMA( 1, 4, 0, M2P ) +#define CYGHWR_HAL_STM32_SPI2_DMA_RX CYGHWR_HAL_STM32_DMA( 1, 3, 0, P2M ) + + + +#ifndef CYGHWR_HAL_STM32_SPI3_REMAP +#define CYGHWR_HAL_STM32_SPI3_SCK CYGHWR_HAL_STM32_PIN_ALTFN_OUT( B, 3, 6, PUSHPULL, NONE, SPEED_SPI ) +#define CYGHWR_HAL_STM32_SPI3_MISO CYGHWR_HAL_STM32_PIN_ALTFN_IN( B, 4, 6, NA, PULLUP ) +#define CYGHWR_HAL_STM32_SPI3_MOSI CYGHWR_HAL_STM32_PIN_ALTFN_OUT( B, 5, 6, PUSHPULL, NONE, SPEED_SPI ) +#else +#define CYGHWR_HAL_STM32_SPI3_SCK CYGHWR_HAL_STM32_PIN_ALTFN_OUT( C, 10, 6, PUSHPULL, NONE, SPEED_SPI ) +#define CYGHWR_HAL_STM32_SPI3_MISO CYGHWR_HAL_STM32_PIN_ALTFN_IN( C, 11, 6, NA, PULLUP ) +#define CYGHWR_HAL_STM32_SPI3_MOSI CYGHWR_HAL_STM32_PIN_ALTFN_OUT( C, 12, 6, PUSHPULL, NONE, SPEED_SPI ) +#endif +#define CYGHWR_HAL_STM32_SPI3_REMAP_CONFIG 0 + +#define CYGHWR_HAL_STM32_SPI3_DMA_TX CYGHWR_HAL_STM32_DMA( 1, 2, 0, M2P ) +#define CYGHWR_HAL_STM32_SPI3_DMA_RX CYGHWR_HAL_STM32_DMA( 1, 0, 0, P2M ) + + +//============================================================================= +// GPIO pin and DMA definitions for each I2C bus + +#define CYGHWR_HAL_STM32_I2C1_SCL CYGHWR_HAL_STM32_PIN_ALTFN_OUT( B, 6, 4, OPENDRAIN, PULLUP, AT_LEAST(50) ) +#define CYGHWR_HAL_STM32_I2C1_SDA CYGHWR_HAL_STM32_PIN_ALTFN_OUT( B, 9, 4, OPENDRAIN, PULLUP, AT_LEAST(50) ) + +#define CYGHWR_HAL_STM32_I2C1_DMA_TX CYGHWR_HAL_STM32_DMA( 1, 7, 1, M2P ) +#define CYGHWR_HAL_STM32_I2C1_DMA_RX CYGHWR_HAL_STM32_DMA( 1, 5, 1, P2M ) + +#define CYGHWR_HAL_STM32_I2C2_SCL CYGHWR_HAL_STM32_PIN_ALTFN_OUT( B, 10, 4, OPENDRAIN, PULLUP, AT_LEAST(50) ) +#define CYGHWR_HAL_STM32_I2C2_SDA CYGHWR_HAL_STM32_PIN_ALTFN_OUT( B, 11, 4, OPENDRAIN, PULLUP, AT_LEAST(50) ) + +#define CYGHWR_HAL_STM32_I2C2_DMA_TX CYGHWR_HAL_STM32_DMA( 1, 7, 7, M2P ) +#define CYGHWR_HAL_STM32_I2C2_DMA_RX CYGHWR_HAL_STM32_DMA( 1, 3, 7, P2M ) + +//----------------------------------------------------------------------------- +// end of plf_io.h +#endif // CYGONCE_HAL_PLF_IO_H diff --git a/ecos/packages/hal/cortexm/stm32/stm32x0g_eval/current/misc/redboot_JTAG.ecm b/ecos/packages/hal/cortexm/stm32/stm32x0g_eval/current/misc/redboot_JTAG.ecm new file mode 100644 index 0000000..fd2f9e5 --- /dev/null +++ b/ecos/packages/hal/cortexm/stm32/stm32x0g_eval/current/misc/redboot_JTAG.ecm @@ -0,0 +1,87 @@ +cdl_savefile_version 1; +cdl_savefile_command cdl_savefile_version {}; +cdl_savefile_command cdl_savefile_command {}; +cdl_savefile_command cdl_configuration { description hardware template package }; +cdl_savefile_command cdl_package { value_source user_value wizard_value inferred_value }; +cdl_savefile_command cdl_component { value_source user_value wizard_value inferred_value }; +cdl_savefile_command cdl_option { value_source user_value wizard_value inferred_value }; +cdl_savefile_command cdl_interface { value_source user_value wizard_value inferred_value }; + +cdl_configuration eCos { + description "" ; + template redboot ; + + package CYGPKG_IO_FLASH current ; +}; + +cdl_option CYGFUN_LIBC_STRING_BSD_FUNCS { + inferred_value 0 +}; + +cdl_option CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE { + user_value 4096 +}; + +cdl_option CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT { + user_value 0 +}; + +cdl_option CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM { + inferred_value 0 +}; + +cdl_option CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS { + inferred_value 1 +}; + +cdl_option CYGSEM_HAL_ROM_MONITOR { + inferred_value 1 +}; + +cdl_option CYGSEM_HAL_USE_ROM_MONITOR { + inferred_value 0 0 +}; + +cdl_component CYG_HAL_STARTUP { + user_value JTAG +}; + +cdl_component CYGBLD_BUILD_REDBOOT { + user_value 1 +}; + +cdl_option CYGBLD_BUILD_REDBOOT_WITH_CACHES { + user_value 0 +}; + +cdl_option CYGSEM_REDBOOT_FLASH_COMBINED_FIS_AND_CONFIG { + user_value 1 +}; + +cdl_option CYGBLD_BUILD_REDBOOT_WITH_EXEC { + user_value 0 +}; + +cdl_option CYGBLD_ISO_STRTOK_R_HEADER { + inferred_value 1 <cyg/libc/string/string.h> +}; + +cdl_option CYGBLD_ISO_STRING_LOCALE_FUNCS_HEADER { + inferred_value 1 <cyg/libc/string/string.h> +}; + +cdl_option CYGBLD_ISO_STRING_BSD_FUNCS_HEADER { + inferred_value 1 <cyg/libc/string/bsdstring.h> +}; + +cdl_option CYGBLD_ISO_STRING_MEMFUNCS_HEADER { + inferred_value 1 <cyg/libc/string/string.h> +}; + +cdl_option CYGBLD_ISO_STRING_STRFUNCS_HEADER { + inferred_value 1 <cyg/libc/string/string.h> +}; + +cdl_option CYGDBG_HAL_CRCTABLE_LOCATION { + inferred_value ROM +}; diff --git a/ecos/packages/hal/cortexm/stm32/stm32x0g_eval/current/misc/redboot_RAM.ecm b/ecos/packages/hal/cortexm/stm32/stm32x0g_eval/current/misc/redboot_RAM.ecm new file mode 100644 index 0000000..19a5583 --- /dev/null +++ b/ecos/packages/hal/cortexm/stm32/stm32x0g_eval/current/misc/redboot_RAM.ecm @@ -0,0 +1,83 @@ +cdl_savefile_version 1; +cdl_savefile_command cdl_savefile_version {}; +cdl_savefile_command cdl_savefile_command {}; +cdl_savefile_command cdl_configuration { description hardware template package }; +cdl_savefile_command cdl_package { value_source user_value wizard_value inferred_value }; +cdl_savefile_command cdl_component { value_source user_value wizard_value inferred_value }; +cdl_savefile_command cdl_option { value_source user_value wizard_value inferred_value }; +cdl_savefile_command cdl_interface { value_source user_value wizard_value inferred_value }; + +cdl_configuration eCos { + description "" ; + template redboot ; + + package CYGPKG_IO_FLASH current ; +}; + +cdl_option CYGFUN_LIBC_STRING_BSD_FUNCS { + inferred_value 0 +}; + +cdl_option CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE { + user_value 4096 +}; + +cdl_option CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT { + user_value 0 +}; + +cdl_option CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM { + inferred_value 0 +}; + +cdl_option CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS { + inferred_value 1 +}; + +cdl_option CYGSEM_HAL_ROM_MONITOR { + inferred_value 0 +}; + +cdl_option CYGSEM_HAL_USE_ROM_MONITOR { + inferred_value 0 0 +}; + +cdl_component CYG_HAL_STARTUP { + user_value RAM +}; + +cdl_component CYGBLD_BUILD_REDBOOT { + user_value 1 +}; + +cdl_option CYGBLD_BUILD_REDBOOT_WITH_CACHES { + user_value 0 +}; + +cdl_option CYGSEM_REDBOOT_FLASH_COMBINED_FIS_AND_CONFIG { + user_value 1 +}; + +cdl_option CYGBLD_BUILD_REDBOOT_WITH_EXEC { + user_value 0 +}; + +cdl_option CYGBLD_ISO_STRTOK_R_HEADER { + inferred_value 1 <cyg/libc/string/string.h> +}; + +cdl_option CYGBLD_ISO_STRING_LOCALE_FUNCS_HEADER { + inferred_value 1 <cyg/libc/string/string.h> +}; + +cdl_option CYGBLD_ISO_STRING_BSD_FUNCS_HEADER { + inferred_value 1 <cyg/libc/string/bsdstring.h> +}; + +cdl_option CYGBLD_ISO_STRING_MEMFUNCS_HEADER { + inferred_value 1 <cyg/libc/string/string.h> +}; + +cdl_option CYGBLD_ISO_STRING_STRFUNCS_HEADER { + inferred_value 1 <cyg/libc/string/string.h> +}; diff --git a/ecos/packages/hal/cortexm/stm32/stm32x0g_eval/current/misc/redboot_ROM.ecm b/ecos/packages/hal/cortexm/stm32/stm32x0g_eval/current/misc/redboot_ROM.ecm new file mode 100644 index 0000000..5c92419 --- /dev/null +++ b/ecos/packages/hal/cortexm/stm32/stm32x0g_eval/current/misc/redboot_ROM.ecm @@ -0,0 +1,87 @@ +cdl_savefile_version 1; +cdl_savefile_command cdl_savefile_version {}; +cdl_savefile_command cdl_savefile_command {}; +cdl_savefile_command cdl_configuration { description hardware template package }; +cdl_savefile_command cdl_package { value_source user_value wizard_value inferred_value }; +cdl_savefile_command cdl_component { value_source user_value wizard_value inferred_value }; +cdl_savefile_command cdl_option { value_source user_value wizard_value inferred_value }; +cdl_savefile_command cdl_interface { value_source user_value wizard_value inferred_value }; + +cdl_configuration eCos { + description "" ; + template redboot ; + + package CYGPKG_IO_FLASH current ; +}; + +cdl_option CYGFUN_LIBC_STRING_BSD_FUNCS { + inferred_value 0 +}; + +cdl_option CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE { + user_value 4096 +}; + +cdl_option CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT { + user_value 0 +}; + +cdl_option CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM { + inferred_value 0 +}; + +cdl_option CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS { + inferred_value 1 +}; + +cdl_option CYGSEM_HAL_ROM_MONITOR { + inferred_value 1 +}; + +cdl_option CYGSEM_HAL_USE_ROM_MONITOR { + inferred_value 0 0 +}; + +cdl_component CYG_HAL_STARTUP { + user_value ROM +}; + +cdl_component CYGBLD_BUILD_REDBOOT { + user_value 1 +}; + +cdl_option CYGBLD_BUILD_REDBOOT_WITH_CACHES { + user_value 0 +}; + +cdl_option CYGSEM_REDBOOT_FLASH_COMBINED_FIS_AND_CONFIG { + user_value 1 +}; + +cdl_option CYGBLD_BUILD_REDBOOT_WITH_EXEC { + user_value 0 +}; + +cdl_option CYGBLD_ISO_STRTOK_R_HEADER { + inferred_value 1 <cyg/libc/string/string.h> +}; + +cdl_option CYGBLD_ISO_STRING_LOCALE_FUNCS_HEADER { + inferred_value 1 <cyg/libc/string/string.h> +}; + +cdl_option CYGBLD_ISO_STRING_BSD_FUNCS_HEADER { + inferred_value 1 <cyg/libc/string/bsdstring.h> +}; + +cdl_option CYGBLD_ISO_STRING_MEMFUNCS_HEADER { + inferred_value 1 <cyg/libc/string/string.h> +}; + +cdl_option CYGBLD_ISO_STRING_STRFUNCS_HEADER { + inferred_value 1 <cyg/libc/string/string.h> +}; + +cdl_option CYGDBG_HAL_CRCTABLE_LOCATION { + inferred_value ROM +}; diff --git a/ecos/packages/hal/cortexm/stm32/stm32x0g_eval/current/misc/redboot_ROM_FPU.ecm b/ecos/packages/hal/cortexm/stm32/stm32x0g_eval/current/misc/redboot_ROM_FPU.ecm new file mode 100644 index 0000000..14652a8 --- /dev/null +++ b/ecos/packages/hal/cortexm/stm32/stm32x0g_eval/current/misc/redboot_ROM_FPU.ecm @@ -0,0 +1,95 @@ +cdl_savefile_version 1; +cdl_savefile_command cdl_savefile_version {}; +cdl_savefile_command cdl_savefile_command {}; +cdl_savefile_command cdl_configuration { description hardware template package }; +cdl_savefile_command cdl_package { value_source user_value wizard_value inferred_value }; +cdl_savefile_command cdl_component { value_source user_value wizard_value inferred_value }; +cdl_savefile_command cdl_option { value_source user_value wizard_value inferred_value }; +cdl_savefile_command cdl_interface { value_source user_value wizard_value inferred_value }; + +cdl_configuration eCos { + description "" ; + template redboot ; + + package CYGPKG_IO_FLASH current ; +}; + +cdl_component CYGHWR_HAL_CORTEXM_FPU { + user_value 1 +}; + +cdl_option CYGHWR_HAL_CORTEXM_FPU_SWITCH { + user_value ALL +}; + +cdl_option CYGFUN_LIBC_STRING_BSD_FUNCS { + inferred_value 0 +}; + +cdl_option CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE { + user_value 4096 +}; + +cdl_option CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT { + user_value 0 +}; + +cdl_option CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM { + inferred_value 0 +}; + +cdl_option CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS { + inferred_value 1 +}; + +cdl_option CYGSEM_HAL_ROM_MONITOR { + inferred_value 1 +}; + +cdl_option CYGSEM_HAL_USE_ROM_MONITOR { + inferred_value 0 0 +}; + +cdl_component CYG_HAL_STARTUP { + user_value ROM +}; + +cdl_component CYGBLD_BUILD_REDBOOT { + user_value 1 +}; + +cdl_option CYGBLD_BUILD_REDBOOT_WITH_CACHES { + user_value 0 +}; + +cdl_option CYGSEM_REDBOOT_FLASH_COMBINED_FIS_AND_CONFIG { + user_value 1 +}; + +cdl_option CYGBLD_BUILD_REDBOOT_WITH_EXEC { + user_value 0 +}; + +cdl_option CYGBLD_ISO_STRTOK_R_HEADER { + inferred_value 1 <cyg/libc/string/string.h> +}; + +cdl_option CYGBLD_ISO_STRING_LOCALE_FUNCS_HEADER { + inferred_value 1 <cyg/libc/string/string.h> +}; + +cdl_option CYGBLD_ISO_STRING_BSD_FUNCS_HEADER { + inferred_value 1 <cyg/libc/string/bsdstring.h> +}; + +cdl_option CYGBLD_ISO_STRING_MEMFUNCS_HEADER { + inferred_value 1 <cyg/libc/string/string.h> +}; + +cdl_option CYGBLD_ISO_STRING_STRFUNCS_HEADER { + inferred_value 1 <cyg/libc/string/string.h> +}; + +cdl_option CYGDBG_HAL_CRCTABLE_LOCATION { + inferred_value ROM +}; diff --git a/ecos/packages/hal/cortexm/stm32/stm32x0g_eval/current/src/stm32x0g_eval_flash.c b/ecos/packages/hal/cortexm/stm32/stm32x0g_eval/current/src/stm32x0g_eval_flash.c new file mode 100644 index 0000000..ed513c5 --- /dev/null +++ b/ecos/packages/hal/cortexm/stm32/stm32x0g_eval/current/src/stm32x0g_eval_flash.c @@ -0,0 +1,68 @@ +/*========================================================================== +// +// stm32x0g_eval_flash.c +// +// Cortex-M3 STM32X0G EVAL Flash setup +// +//========================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2008 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): jlarmour +// Date: 2011-12-12 +// Description: +// +//####DESCRIPTIONEND#### +// +//========================================================================*/ + +#include <cyg/io/flash_dev.h> + +//-------------------------------------------------------------------------- +// Internal flash + +#include <cyg/io/stm32_flash.h> + +CYG_FLASH_DRIVER(hal_stm32_flash, + &cyg_stm32_flash_funs, + 0, + 0x08000000, + 0, + 0, + 0, + &hal_stm32_flash_priv +); + +//-------------------------------------------------------------------------- +// EOF stm32x0g_eval_flash.c diff --git a/ecos/packages/hal/cortexm/stm32/stm32x0g_eval/current/src/stm32x0g_eval_misc.c b/ecos/packages/hal/cortexm/stm32/stm32x0g_eval/current/src/stm32x0g_eval_misc.c new file mode 100644 index 0000000..84a5a0a --- /dev/null +++ b/ecos/packages/hal/cortexm/stm32/stm32x0g_eval/current/src/stm32x0g_eval_misc.c @@ -0,0 +1,404 @@ +/*========================================================================== +// +// stm32x0g_eval_misc.c +// +// Cortex-M3/-M4 STM32X0G EVAL HAL functions +// +//========================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2008, 2011, 2012 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): jlarmour based on stm3210e by nickg +// Date: 2008-07-30 +// Description: +// +//####DESCRIPTIONEND#### +// +//========================================================================*/ + +#include <pkgconf/hal.h> +#include <pkgconf/hal_cortexm.h> +#include <pkgconf/hal_cortexm_stm32.h> +#include <pkgconf/hal_cortexm_stm32_stm32x0g_eval.h> +#ifdef CYGPKG_KERNEL +#include <pkgconf/kernel.h> +#endif + +#include CYGHWR_MEMORY_LAYOUT_H // Memory regions + +#include <cyg/infra/diag.h> +#include <cyg/infra/cyg_type.h> +#include <cyg/infra/cyg_trac.h> // tracing macros +#include <cyg/infra/cyg_ass.h> // assertion macros + +#include <cyg/hal/hal_arch.h> // HAL header +#include <cyg/hal/hal_intr.h> // HAL header +#include <cyg/hal/hal_if.h> // HAL header + +//========================================================================== + +#if defined(CYGSEM_HAL_VIRTUAL_VECTOR_SUPPORT) +#if (CYGNUM_CALL_IF_TABLE_SIZE > 64) +// We force a compilation error for this fatal condition since run-time asserts +// may not be enabled for the build. +#error "The CALL_IF_TABLE_SIZE pre-allocation in the linker scripts for this platform need to be updated" +#endif +#endif // CYGSEM_HAL_VIRTUAL_VECTOR_SUPPORT + +//========================================================================== +// System init +// +// This is run to set up the basic system, including GPIO setting, +// clock feeds, power supply, and memory initialization. This code +// runs before the DATA is copied from ROM and the BSS cleared, hence +// it cannot make use of static variables or data tables. + +__externC void hal_system_init( void ) +{ + CYG_ADDRESS base; + + // Enable peripheral clocks in RCC + + base = CYGHWR_HAL_STM32_RCC; + + // All GPIO ports + // FIXME: this should be done in variant HAL at point of gpio_set + HAL_WRITE_UINT32(base+CYGHWR_HAL_STM32_RCC_AHB1ENR, +#if defined(CYGHWR_HAL_CORTEXM_STM32_FAMILY_F4) // enable CCM clock + BIT_(CYGHWR_HAL_STM32_RCC_AHB1ENR_CCMDATARAMEN) | +#endif // CYGHWR_HAL_CORTEXM_STM32_FAMILY_F4 + BIT_(CYGHWR_HAL_STM32_RCC_AHB1ENR_GPIOA) | + BIT_(CYGHWR_HAL_STM32_RCC_AHB1ENR_GPIOB) | + BIT_(CYGHWR_HAL_STM32_RCC_AHB1ENR_GPIOC) | + BIT_(CYGHWR_HAL_STM32_RCC_AHB1ENR_GPIOD) | + BIT_(CYGHWR_HAL_STM32_RCC_AHB1ENR_GPIOE) | + BIT_(CYGHWR_HAL_STM32_RCC_AHB1ENR_GPIOF) | + BIT_(CYGHWR_HAL_STM32_RCC_AHB1ENR_GPIOG) | + BIT_(CYGHWR_HAL_STM32_RCC_AHB1ENR_GPIOH) | + BIT_(CYGHWR_HAL_STM32_RCC_AHB1ENR_GPIOI) ); + + // Enable FSMC + HAL_WRITE_UINT32(base+CYGHWR_HAL_STM32_RCC_AHB3ENR, + BIT_(CYGHWR_HAL_STM32_RCC_AHB3ENR_FSMC) ); + +#if defined(CYG_HAL_STARTUP_ROM) | defined(CYG_HAL_STARTUP_ROMINT) | defined(CYG_HAL_STARTUP_SRAM) + + // Reset FSMC in case it was already enabled. This should set + // all regs back to default documented values, so we don't need + // to do any precautionary resets. + HAL_WRITE_UINT32(base+CYGHWR_HAL_STM32_RCC_AHB3RSTR, + BIT_(CYGHWR_HAL_STM32_RCC_AHB3ENR_FSMC) ); + // Bring out of reset: + HAL_WRITE_UINT32(base+CYGHWR_HAL_STM32_RCC_AHB3RSTR, 0 ); +#endif + +#if defined(CYGHWR_HAL_CORTEXM_STM32X0G_ETH_PHY_CLOCK_MCO) + // Use HSE clock as the MCO1 clock signals for PHY + { + cyg_uint32 acr; + + HAL_READ_UINT32(base + CYGHWR_HAL_STM32_RCC_CFGR, acr); + acr |= CYGHWR_HAL_STM32_RCC_CFGR_MCO1_HSE | + CYGHWR_HAL_STM32_RCC_CFGR_MCO1PRE_1; + HAL_WRITE_UINT32(base + CYGHWR_HAL_STM32_RCC_CFGR, acr); + } +#endif + + // Set all unused GPIO lines to input with pull down to prevent + // them floating and annoying any external hardware. + + // GPIO Ports C..I reset GPIOx_MODER to 0x00000000 + // GPIO Ports A..I reset GPIOx_OTYPER to 0x00000000 + // CPIO Ports A,C..I reset GPIOx_OSPEEDR to 0x00000000 + // GPIO Ports C..I reset GPIOx_PUPDR to 0x00000000 + + // GPIO Port A resets GPIOA_MODER to 0xA8000000 + // GPIO Port A resets GPIOA_PUPDR to 0x64000000 + // GPIO Port A keeps the default JTAG pins on PA13,14,15 + base = CYGHWR_HAL_STM32_GPIOA; + HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_GPIO_PUPDR, 0x02AAAAAA ); + + // GPIO Port B resets GPIOB_MODER to 0x00000280 + // GPIO Port B resets GPIOB_OSPEEDR to 0x000000C0 + // GPIO Port B resets GPIOB_PUPDR to 0x00000100 + // GPIO Port B keeps the default JTAG pins on PB3,4 + base = CYGHWR_HAL_STM32_GPIOB; + HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_GPIO_PUPDR, 0xAAAAA82A ); + + // GPIO Port C - setup PC7 for LED4 as GPIO out, RS232 (USART4) on PC10,11. + // Rest stay default, with pulldowns on all except PC14,15 (OSC32) + // just in case that is important. + + base = CYGHWR_HAL_STM32_GPIOC; + HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_GPIO_AFRH, 0x00008800 ); + HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_GPIO_PUPDR, 0x0A0A2AAA ); + HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_GPIO_MODER, 0x00A04000 ); + + // GPIO Port D - setup FSMC for SRAM (PD0-1,3-15) and MicroSDcard (PD2) alternate functions + base = CYGHWR_HAL_STM32_GPIOD; + HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_GPIO_AFRL, 0xCCCCCCCC ); + HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_GPIO_AFRH, 0xCCCCCCCC ); + HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_GPIO_MODER, 0xAAAAAAAA ); + // TODO:CONSIDER: OSPEEDR for SRAM pins to 100MHz + + // GPIO Port E - setup FSMC alternate function. PE0-1,3-4,7-15. + // But not PE5 (A21), PE6(A22), PE2(A23) which are not connected to SRAM. + base = CYGHWR_HAL_STM32_GPIOE; + HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_GPIO_AFRL, 0xC00CC0CC ); + HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_GPIO_AFRH, 0xCCCCCCCC ); + HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_GPIO_PUPDR, 0x00002820 ); + HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_GPIO_MODER, 0xAAAA828A ); + // TODO:CONSIDER: OSPEEDR for SRAM pins to 100MHz + + // GPIO Port F - setup FSMC alternate function. PF0-5,12-15. + // But not PF6-11 which aren't connected to SRAM. + base = CYGHWR_HAL_STM32_GPIOF; + HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_GPIO_AFRL, 0x00CCCCCC ); + HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_GPIO_AFRH, 0xCCCC0000 ); + HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_GPIO_PUPDR, 0x00AAA000 ); + HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_GPIO_MODER, 0xAA000AAA ); + // TODO:CONSIDER: OSPEEDR for SRAM pins to 100MHz + + // GPIO Port G - setup FSMC alternate function. PG0-5,9,10. + // Other FSMC pins not connected to SRAM. + // LED1 is PG6, LED2 is PG8, so set as GPIO out. + base = CYGHWR_HAL_STM32_GPIOG; + HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_GPIO_AFRL, 0x00CCCCCC ); + HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_GPIO_AFRH, 0x00000CC0 ); + HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_GPIO_PUPDR, 0xAA808000 ); + HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_GPIO_MODER, 0x00291AAA ); + // TODO:CONSIDER: OSPEEDR for SRAM pins to 100MHz + + // GPIO Port H stays default, with pulldowns on all except PH0,1 (OSC) just in case that is important. + base = CYGHWR_HAL_STM32_GPIOH; + HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_GPIO_PUPDR, 0xAAAAAAA0 ); + + // GPIO Port I - setup PI9 for LED3 as GPIO out, rest stay default, with pulldowns + base = CYGHWR_HAL_STM32_GPIOI; + HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_GPIO_PUPDR, 0xAAA2AAAA ); + HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_GPIO_MODER, 0x00040000 ); + + + // Set up FSMC NOR/SRAM bank 2 for SRAM + + base = CYGHWR_HAL_STM32_FSMC; + + +#if defined(CYGHWR_HAL_CORTEXM_STM32_FAMILY_F4) + // NOTEs: + // - The "STM32 20-21-45-46 G-EVAL" boards we have are populated with the + // IS61WV102416BLL-10MLI part and not the Cypress CY7C1071DV33 part. + // - The F4[01][57]xx devices can operate upto 168MHz (or 144MHz) so maximum HCLK + // timing of 6ns (or 6.94444ns). + // + // NOTE: The code does NOT set BWTR2 for SRAM write-cycle timing (so will be + // the default reset value of 0x0FFFFFFF) since BCRx:EXTMOD bit is NOT set. + + // TODO:IMPROVE: Derive values based on CLK settings. The following "fixed" + // values are based on a 168MHz SYSCLK: + + // BCR2 = MBKEN | MWID=0b01 (16bits) | WREN + HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_FSMC_BCR2, 0x00001015 ); + + // BTR2: + // ADDSET=3 (3 HCLK cycles) + // ADDHLD=0 (SRAM:do not care) + // DATAST=6 (6 HCLK cycles) + // BUSTURN=1 (1 HCLK cycle) + // CLKDIV=0 (SRAM:do not care) + // DATLAT=0 (SRAM:do not care) + // ACCMOD=0 (access mode A) + HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_FSMC_BTR2, 0x00010603 ); +#else // CYGHWR_HAL_CORTEXM_STM32_FAMILY_F2 + HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_FSMC_BCR2, 0x00001011 ); + // SRAM timings for the fitted CY7C1071DV33-12BAXI async SRAM + // We could try and make this depend on hclk as it should, but that's + // probably overkill for now. With an hclk of 120MHz, each hclk period + // is 8.33ns, so we just use that. This might mean being slightly + // suboptimal at lower configured hclk speeds. + // It's tricky to get the waveforms in the STM32 FSMC docs and the SRAM + // datasheet, to match up, so there's a small amount of guess work involved + // here. From the SRAM datasheet, ADDSET should be at least 7ns (tHZWE), and + // DATAST should be at least 9ns (tPWE) plus one HCLK (from Fig 397 in FSMC + // docs showing Mode 1 write accesses). This gives ADDSET=1 and + // DATAST=3. + HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_FSMC_BTR2, 0x00000301 ); +#endif // CYGHWR_HAL_CORTEXM_STM32_FAMILY_F2 + + // Enable flash prefetch buffer, cacheability and set latency to 2 wait states. + // Latency has to be set before clock is switched to a higher speed. + { + cyg_uint32 acr; + + base = CYGHWR_HAL_STM32_FLASH; + + HAL_READ_UINT32( base+CYGHWR_HAL_STM32_FLASH_ACR, acr ); + acr |= CYGHWR_HAL_STM32_FLASH_ACR_PRFTEN; + acr |= CYGHWR_HAL_STM32_FLASH_ACR_DCEN|CYGHWR_HAL_STM32_FLASH_ACR_ICEN; + acr |= CYGHWR_HAL_STM32_FLASH_ACR_LATENCY(CYGNUM_HAL_CORTEXM_STM32_FLASH_WAIT_STATES); + HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_FLASH_ACR, acr ); + } +} + +//========================================================================== + +// Set LEDs 1-4 to lowest 4 bits of supplied char. +__externC void hal_stm32x0_led(char c) +{ + CYGHWR_HAL_STM32_GPIO_OUT( CYGHWR_HAL_STM32X0G_LED1, 0 != (c&1) ); + CYGHWR_HAL_STM32_GPIO_OUT( CYGHWR_HAL_STM32X0G_LED2, 0 != (c&2) ); + CYGHWR_HAL_STM32_GPIO_OUT( CYGHWR_HAL_STM32X0G_LED3, 0 != (c&4) ); + CYGHWR_HAL_STM32_GPIO_OUT( CYGHWR_HAL_STM32X0G_LED4, 0 != (c&8) ); +} + +//========================================================================== + +__externC void hal_platform_init( void ) +{ +#ifdef CYGDBG_USE_ASSERTS + __externC char __sram_data_start[]; +#endif + +#ifdef CYGSEM_HAL_VIRTUAL_VECTOR_SUPPORT + // Check the number of VSRs matches the linker script. We can do this + // because we intend the VV table to follow the VSR table with no gaps. + CYG_ASSERT( (char*)&hal_virtual_vector_table[0] - (char*)&hal_vsr_table >= CYGNUM_HAL_VSR_COUNT*4, + "VSR table size does not match" ); + // Now check the declared start of SRAM data follows the VV table end + CYG_ASSERT( (__sram_data_start - (char*)&hal_virtual_vector_table[0]) >= CYGNUM_CALL_IF_TABLE_SIZE*4, + "VV table size does not match sram space" ); +#else + // Check the VSR table fits below declared start of SRAM data + CYG_ASSERT( (__sram_data_start - (char*)&hal_vsr_table[0]) >= CYGNUM_HAL_VSR_COUNT*4, + "VSR table size does not match" ); +#endif + hal_stm32x0_led(1); +} + +//========================================================================== + +#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS + +//-------------------------------------------------------------------------- +// Accesses to areas not backed by real devices or memory can cause +// the CPU to hang. +// +// The following table defines the memory areas that GDB is allowed to +// touch. All others are disallowed. +// This table needs to be kept up to date with the set of memory areas +// that are available on the board. + +static struct +{ + CYG_ADDRESS start; // Region start address + CYG_ADDRESS end; // End address (last byte) +} hal_data_access[] = +{ + { CYGMEM_REGION_ram, CYGMEM_REGION_ram+CYGMEM_REGION_ram_SIZE-1 }, // External SRAM +#ifdef CYGMEM_REGION_sram + { CYGMEM_REGION_sram, CYGMEM_REGION_sram+CYGMEM_REGION_sram_SIZE-1 }, // On-chip SRAM +#endif +#ifdef CYGMEM_REGION_flash + { CYGMEM_REGION_flash, CYGMEM_REGION_flash+CYGMEM_REGION_flash_SIZE-1 }, // On-chip flash +#endif + { 0xE0000000, 0x00000000-1 }, // Cortex-M peripherals + { 0x40000000, 0x60000000-1 }, // STM32 peripherals + { 0xA0000000, 0xA0001000-1 }, // FSMC control +#ifdef CYGMEM_REGION_ccm + { CYGMEM_REGION_ccm, CYGMEM_REGION_ccm+CYGMEM_REGION_ccm_SIZE-1 }, // On-chip (close-coupled) SRAM +#endif +}; + +__externC int cyg_hal_stub_permit_data_access( CYG_ADDRESS addr, cyg_uint32 count ) +{ + int i; + for( i = 0; i < sizeof(hal_data_access)/sizeof(hal_data_access[0]); i++ ) + { + if( (addr >= hal_data_access[i].start) && + (addr+count) <= hal_data_access[i].end) + return true; + } + return false; +} + +#endif // CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS + +//========================================================================== + +#ifdef CYGPKG_REDBOOT +#include <redboot.h> +#include CYGHWR_MEMORY_LAYOUT_H + +//-------------------------------------------------------------------------- +// Memory layout +// +// We report the on-chip SRAM and external SRAM. + + +void +cyg_plf_memory_segment(int seg, unsigned char **start, unsigned char **end) +{ + switch (seg) { + case 0: + *start = (unsigned char *)CYGMEM_REGION_ram; + *end = (unsigned char *)(CYGMEM_REGION_ram + CYGMEM_REGION_ram_SIZE); + break; +#ifdef CYGMEM_REGION_sram + case 1: + *start = (unsigned char *)CYGMEM_REGION_sram; + *end = (unsigned char *)(CYGMEM_REGION_sram + CYGMEM_REGION_sram_SIZE); + break; +#elif defined(CYGMEM_REGION_xram) + case 1: + *start = (unsigned char *)CYGMEM_REGION_xram; + *end = (unsigned char *)(CYGMEM_REGION_xram + CYGMEM_REGION_xram_SIZE); + break; +#endif +#ifdef CYGMEM_REGION_ccm + case 2: + *start = (unsigned char *)CYGMEM_REGION_ccm; + *end = (unsigned char *)(CYGMEM_REGION_ccm + CYGMEM_REGION_ccm_SIZE); + break; +#endif + default: + *start = *end = NO_MEMORY; + break; + } +} // cyg_plf_memory_segment() + +#endif // CYGPKG_REDBOOT + + +//========================================================================== +// EOF stm32x0g_eval_misc.c diff --git a/ecos/packages/hal/cortexm/stm32/var/current/ChangeLog b/ecos/packages/hal/cortexm/stm32/var/current/ChangeLog new file mode 100644 index 0000000..acc15b3 --- /dev/null +++ b/ecos/packages/hal/cortexm/stm32/var/current/ChangeLog @@ -0,0 +1,406 @@ +2014-02-28 John Dallaway <john@dallaway.org.uk> + + * src/stm32_misc.c: Ensure TIM2 clock enabled when profiling. + [Bugzilla 1001953] + +2013-04-06 Jerzy Dyrda <jerzdy@gmail.com> + + * include/var_io_eth.h: + * include/var_io.h: Update ETH macros for F4 device. [ Bugzilla 1001219 ] + +2013-01-19 John Dallaway <john@dallaway.org.uk> + + * include/var_io.h: Fix CYGHWR_HAL_STM32_UART6 definition. + +2012-04-23 James Smith <jsmith@ecoscentric.com> + + * include/var_io_pins.h (CYGHWR_HAL_STM32_PIN_IN): Removed + spurious parameter since the API for this macro should match the + F2/F4 (HIPERFORMANCE) definition. + + * include/var_io_eth.h: Update F1 ETH_MII + CYGHWR_HAL_STM32_PIN_IN() usage to reflect correct API. + +2012-04-13 Christophe Coutand <ecos@hotmail.co.uk> + + * include/var_io.h: + Added definitions, CYGHWR_HAL_STM32_USB_CLOCK, + CYGHWR_HAL_STM32_CAN1_CLOCK and CYGHWR_HAL_STM32_CAN2_CLOCK + +2012-03-27 James Smith <jsmith@ecoscentric.com> + + * tests/timers.c (TIMER_PRI): Add macro and manifests to allow + easy manipulation of the base and delta between the timer + priorities being tested. + +2012-03-23 James Smith <jsmith@ecoscentric.com> + + * include/var_io_usart.h: Provide common/shared UART pin + definitions for F1, F2 and F4 devices using the new PIN wrapper + macros. The RTS pin definitions for all STM32F families now use + GPIO output since the driver uses software controlled + RTS. Previously the F2/F4 defined the RTS pins as ALTFN. + + * include/var_io.h: Provide common/shared ADC pin definitions for + F1, F2 and F4 devices using the new PIN_ANALOG() wrapper macro. + + * include/var_io_eth.h: Provide common MII pin definitions using + the new PIN wrapper macros. Also remove MII_REMAP which was + incorrectly using the wrong manifests (STM3210C-EVAL networking + would not work) since decision taken that "plf_io.h" should + contain board specific I/O pin mapping. + + * cdl/hal_cortexm_stm32.cdl: Remove CYGPKG_HAL_STM32_ETH and + sub-option CYGHWR_HAL_STM32_ETH_MII_REMAP since ethernet pin + mapping now present in platform specific "plf_io.h" header. + +2012-03-22 James Smith <jsmith@ecoscentric.com> + + * include/var_io_pins.h: Provide "common" wrapper macros + CYGHWR_HAL_STM32_PIN_OUT, CYGHWR_HAL_STM32_PIN_ALTFN_OUT, + CYGHWR_HAL_STM32_PIN_IN, CYGHWR_HAL_STM32_PIN_ALTFN_IN and + CYGHWR_HAL_STM32_PIN_ANALOG for defining I/O pins to allow the + same (where applicable) source calls to be used regardless of + whether the target is F1 or HIPERFORMANCE (F2/F4). + + * cdl/hal_cortexm_stm32.cdl: Remove CYGPKG_HAL_STM32_ETH and + sub-option CYGHWR_HAL_STM32_ETH_MII_REMAP since ethernet pin + mapping now present in platform specific "plf_io.h" header. + +2012-03-21 James Smith <jsmith@ecoscentric.com> + + * include/var_io_pins.h: Provide similar support for F1 family + devices as available for F2/F4 family devices by adding AT_LEAST + and AT_MOST macros for specifying OUTPUT pin speed limits, and + providing generic LOW, MED and FAST manifests to hide the actual + device speed. + + * src/stm32_misc.c (hal_stm32_gpio_set): Use + CYGHWR_HAL_STM32_GPIO_CNFMODE_SET macro instead of explicit + bitmask manipulation for seeting F1 CRL/CRH. + +2012-03-15 James Smith <jsmith@ecoscentric.com> + + * src/stm32_misc.c: + * src/stm32_dma.c: + * src/hal_diag.c: + * include/var_io_usart.h: + * include/var_io_pins.h: + * include/var_io_eth.h: + * include/var_io.h: + * include/var_intr.h: + * include/var_dma.h: Use HIPERFORMANCE manifest to add support for + F4 devices. + + * cdl/hal_cortexm_stm32.cdl: Many minor changes to support + Cortex-M4 and STM32F4 devices. + + * tests/timers.c (timers): Add TIM8_UP_TIM13 to the set of timers + tested for those platforms where it is defined. + +2012-03-13 James Smith <jsmith@ecoscentric.com> + + * include/var_io.h (HAL_AARDVARK_CHECK_I2C): Macro for specific + STM32 F1 devices that suffer from an I2C/FSMC errata to allow the + Aardvark test cases to operate. Added STM32F4 RTC manifests. + +2012-02-28 James Smith <jsmith@ecoscentric.com> + + * src/stm32_dma.c (hal_stm32_dma_disable): Add new function to + allow temporary disable of DMA stream for circular mode + configurations. + + * include/var_dma.h: Added prototype for newly added + hal_stm32_dma_disable() function. + +2012-02-28 James Smith <jsmith@ecoscentric.com> + + * src/stm32_dma.c (hal_stm32_dma_isr): Do not disable the stream + when configured for circular mode. + +2012-02-24 James Smith <jsmith@ecoscentric.com> + + * include/var_io.h: Provide manifests covering STM32F2 ADC + support. + + * include/var_intr.h: Provide explicit DMA2 CH4 and CH5 manifests + for non-connectivity devices (e.g. STM3210E-EVAL target). + + * include/var_dma.h: + * src/stm32_dma.c (hal_stm32_dma_configure_circular): Provide + function to enable/disable DMA circular mode, and provide + prototype in header and documentation. + +2012-02-17 James Smith <jsmith@ecoscentric.com> + + * include/var_io_pins.h: Fix F2 MODE_SET and OSPEED_SET macros to + correctly mask register field bits. + +2012-01-20 Nick Garnett <nickg@ecoscentric.com> + + * include/var_intr.h (CYGNUM_HAL_VSR_MAX): Reverse an earlier + change to this value. + +2012-01-13 Nick Garnett <nickg@ecoscentric.com> + + * include/var_io.h: Add shifts for RTC TR and DR register fields. + +2012-01-12 Nick Garnett <nickg@ecoscentric.com> + + * include/var_intr.h: Reorganize vectors 43-49 so they are defined + correctly for F2 devices. + + * include/var_io.h: Tidy up DMA defines. Move I2C and SPI pin and + DMA channel definitions out to platform HALs. + + * include/var_io_pins.h (CYGHWR_HAL_STM32_GPIO_PUPD_SET): Fix + buglet in register clear code. + + * cdl/hal_cortexm_stm32.cdl: + * include/var_dma.h: + * src/stm32_dma.c: Add DMA API. + +2011-12-15 Jonathan Larmour <jifl@eCosCentric.com> + + * cdl/hal_cortexm_stm32.cdl (CYGHWR_HAL_CORTEXM_STM32_CONNECTIVITY): + Rather than list every F2 part, just say all F2 since we don't yet know + of F2 parts that don't have connectivity. + (CYGHWR_HAL_STM32_ETH_MII_REMAP): Allow pin remapping to be configurable + as a standard setting, alternate mapping, or provided by the platform. + * include/var_io.h: Add MCO1_MASK/MCO2_MASK and + MCO1PRE_MASK/MCO2PRE_MASK defns. Add CYGHWR_HAL_STM32_FLASH_CR_PSIZE() + to make flash parallelism easier to set. + * include/var_io_eth.h: Fix MACMIIAR_CR_MASK define. + Allow specification (and checking) of MACMIIAR_CR to set MDC clock + according to defined MHz ranges - this allows it to vary between + processors. + Support above CYGHWR_HAL_STM32_ETH_MII_REMAP changes. + Add alternate mappings for F2 eth pins (although it's a different + subset to F1. + +2011-12-12 Jonathan Larmour <jifl@eCosCentric.com> + + * src/stm32_misc.c (hal_start_clocks): Remove unnecessary fiddling + after RCC reset. Avoid overflow from PLL multiplier. Handle PLLQ + and RTCPRE on F2. + + * include/var_io.h (CYGHWR_HAL_STM32_RCC_CFGR_RTCPRE): Add set macro + separate from mask. + + * cdl/hal_cortexm_stm32.cdl: Improve clock option descriptions. Add + CYGHWR_HAL_CORTEXM_STM32_CLOCK_PLLQ_DIV. + +2011-12-08 Jonathan Larmour <jifl@eCosCentric.com> + + * cdl/hal_cortexm_stm32.cdl: Add selections for processors in F2 + family, and allow discrimination between those and F1. + * include/var_intr.h: Modify and add to interrupt list for F2. + (HAL_VAR_INTERRUPT_{MASK,UNMASK,ACKNOWLEDGE,CONFIGURE ): Update + EXTI interrupts that need special mapping for F2. + * include/var_io.h: Many additions and changes for F2. To avoid + an unmanageable size, split out GPIO/pin config, USART and ETH + peripheral definitions into new files. + * include/var_io_pins.h: New file for GPIO and pin configuration. + * include/var_io_usart.h: New file for USART definitions. + * include/var_io_eth.h: New file for Ethernet peripheral definitions. + * src/hal_diag.c: Allow for new style pin remapping used by F2 + while still allowing F1 to work. + Support USART6 (which we call UART5). + (hal_stm32_serial_init_channel): Only use AFIO on F1. + * src/stm32_misc.c (hal_stm32_gpio_{set,out,in}): Support new GPIO + pin setting. + (hal_stm32_uart_setbaud): Support UART6 (called UART5 in CDL). + (hal_enable_profile_timer): Ensure timer peripheral (defaulting to TIM6) + has its clock enabled. + +2011-10-07 Nick Garnett <nickg@ecoscentric.com> + + * include/var_io.h: Separate FSMC and ETH register definitions, + which seem to have got a little mixed together at some point. + +2011-02-03 Alan Bowman <alan.bowman@datong.co.uk> + + * include/var_io.h: Fix CYGHWR_HAL_STM32_RCC_CFGR_PPRE2_* + definitions. [ Bugzilla 1001137 ] + +2011-01-21 Ilija Kocho <ilijak@siva.com.mk> + + * src/stm32_misc.c (hal_start_clocks): Added optional calculation of + hal_cortexm_systick_clock when 'internal' clock source is selected. + +2011-01-13 John Dallaway <john@dallaway.org.uk> + + * src/stm32_misc.c: Implement a profiling timer on TIM2. + * cdl/hal_cortexm_stm32.cdl: Add CDL option to enable the profiling + timer. + +2011-01-13 Nick Garnett <nickg@ecoscentric.com> + + * src/stm32_misc.c (hal_start_clocks): Correct bit clear operation + when disabling external clock. + +2009-10-26 Ross Younger <wry@ecoscentric.com> + + * include/var_io.h: Minor corrections to the FSMC register defs. + +2009-10-22 Nick Garnett <nickg@ecoscentric.com> + + * cdl/hal_cortexm_stm32.cdl: + * include/var_io.h: Add remap configuration for SPI busses. + +2009-08-10 Simon Kallweit <simon.kallweit@intefo.ch> + + * include/var_io.h: Added more register definitions for FSMC + +2009-07-02 Nick Garnett <nickg@ecoscentric.com> + + * cdl/hal_cortexm_stm32.cdl: Add remap configuration for UARTS. + + * include/var_io.h (CYGHWR_HAL_STM32_AFIO_CLOCK): Add AFIO clock control. + (CYGHWR_HAL_STM32_UART*_REMAP_CONFIG): Add remap support for UARTS. + + * src/hal_diag.c (channel_data_t, hal_stm32_serial_init_channel): + Add support for UART remapping. + +2009-06-29 Nick Garnett <nickg@ecoscentric.com> + + * include/var_io.h (CYGHWR_HAL_STM32_ETH): Add support for + ethernet device on connectivity line devices. + Add device clock control support. + + * include/var_intr.h: + * cdl/hal_cortexm_stm32.cdl: Add support for connectivity line + devices. + + * src/stm32_misc.c (hal_variant_init): Remove default enable of + all device clocks. + (hal_stm32_clock_enable, hal_stm32_clock_disable): Add routines to + enable individual device clocks. + + * src/hal_diag.c (stm32_ser_channels) + (hal_stm32_serial_init_channel): Add clock enable support. + +2009-04-17 Simon Kallweit <simon.kallweit@intefo.ch> + + * src/hal_diag.c (hal_stm32_serial_getc_timeout): Fix for higher + baudrates. The original version lost bytes due to the long + timeout. + +2009-03-23 Nick Garnett <nickg@ecoscentric.com> + + * src/stm32_misc.c (hal_variant_init): Add write to AHBENR + register to enable all AHB based devices. + + * include/var_io.h (CYGHWR_HAL_STM32_IWDG_*): Add defines for + independent watchdog. + +2009-02-27 Simon Kallweit <simon.kallweit@intefo.ch> + + * include/var_io.h: + Add mask for CYGHWR_HAL_STM32_RCC_CFGR_ADCPRE. + Fixed CYGHWR_HAL_STM32_RTC_CRL_ALRF. + Add register definitions for ADC. + Add additional timer registers. + * src/stm32_mis.c: + Moved system clock initialization into it's own function, so it can + be called after wakeup from sleep modes. + Added hal_stm32_timer_clock() to get current clock of timers. + +2009-02-10 Chris Holgate <chris@zynaptic.com> + + * include/var_io.h: Add mask for CYGHWR_HAL_STM32_AFIO_MAPR_SWJ. + +2009-02-04 Nick Garnett <nickg@ecoscentric.com> + + * include/var_intr.h: Various fixes to allow external interrupts + to work. + + * include/var_io.h: Add AFIO, DMA, SPI and USB definitions. + + * src/stm32_misc.c (hal_stm32_gpio_set): Refetch bit number for + setting pullup/down. + +2008-11-24 Nick Garnett <nickg@ecoscentric.com> + + * include/var_intr.h (CYGNUM_HAL_INTERRUPT_DMA1_CHX): Rename DMA0 + to DMA1 to match ST's numbering elsewhere. + + * include/var_io.h (CYGHWR_HAL_STM32_GPIO_CFG): Remove PULLUP bit + from mask. Previous addition was incorrect. + +2008-11-24 Simon Kallweit <simon.kallweit@intefo.ch> + + * include/var_io.h: Corrected capitalisation. + +2008-11-12 Simon Kallweit <simon.kallweit@intefo.ch> + + * include/var_io.h: Changed CYGHWR_HAL_STM32_BD_UNPROTECT to + CYGHWR_HAL_STM32_BD_PROTECT, inverting the argument. + * src/stm32_misc.c: Changed hal_stm32_bd_unprotect() to + hal_stm32_bd_protect(), inverting the argument. + +2008-11-11 Nick Garnett <nickg@ecoscentric.com> + + * include/var_io.h: Add power control definitions. + + * src/stm32_misc.c (hal_stm32_bd_unprotect): Add this function to + control backup domain write protection. + +2008-10-14 Nick Garnett <nickg@ecoscentric.com> + + * tests/timers.c: Add ifdefs to avoid compiling tests when not all + packages or components are present. + +2008-10-10 Nick Garnett <nickg@ecoscentric.com> + + * cdl/hal_cortexm_stm32.cdl: Only build tests if the kernel is present. + + * include/var_io.h (CYGHWR_HAL_STM32_GPIO_CFG): Add PULLUP bit to mask. + + * tests/timers.c (timers_test): Terminate with PASS_FINISH rather + than just FINISH. + +2008-10-08 Nick Garnett <nickg@ecoscentric.com> + + * include/var_intr.h (CYGNUM_HAL_ISR_MAX, CYGNUM_HAL_VSR_MAX): Fix + definition of these values. + + * tests/timers.c: Fix to run for maximum duration of 2 minutes. + +2008-10-06 Nick Garnett <nickg@ecoscentric.com> + + * cdl/hal_cortexm_stm32.cdl: + * include/variant.inc: + * include/var_arch.h: + * include/var_intr.h: + * include/var_io.h: + * include/hal_cache.h: + * include/hal_diag.h: + * include/plf_stub.h: + * src/hal_diag.c: + * src/stm32_misc.c: + New package -- ST STM32 variant HAL. + +//=========================================================================== +// ####GPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2008, 2009, 2011, 2013, 2014 Free Software Foundation, Inc. +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 or (at your option) any +// later version. +// +// This program is distributed in the hope that it will be useful, but +// WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +// General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the +// Free Software Foundation, Inc., 51 Franklin Street, +// Fifth Floor, Boston, MA 02110-1301, USA. +// ------------------------------------------- +// ####GPLCOPYRIGHTEND#### +//=========================================================================== diff --git a/ecos/packages/hal/cortexm/stm32/var/current/cdl/hal_cortexm_stm32.cdl b/ecos/packages/hal/cortexm/stm32/var/current/cdl/hal_cortexm_stm32.cdl new file mode 100644 index 0000000..97b2dee --- /dev/null +++ b/ecos/packages/hal/cortexm/stm32/var/current/cdl/hal_cortexm_stm32.cdl @@ -0,0 +1,480 @@ +##========================================================================== +## +## hal_cortexm_stm32.cdl +## +## Cortex-M STM32 variant HAL configuration data +## +##========================================================================== +## ####ECOSGPLCOPYRIGHTBEGIN#### +## ------------------------------------------- +## This file is part of eCos, the Embedded Configurable Operating System. +## Copyright (C) 2008, 2011 Free Software Foundation, Inc. +## +## eCos is free software; you can redistribute it and/or modify it under +## the terms of the GNU General Public License as published by the Free +## Software Foundation; either version 2 or (at your option) any later +## version. +## +## eCos is distributed in the hope that it will be useful, but WITHOUT +## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +## for more details. +## +## You should have received a copy of the GNU General Public License +## along with eCos; if not, write to the Free Software Foundation, Inc., +## 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +## +## As a special exception, if other files instantiate templates or use +## macros or inline functions from this file, or you compile this file +## and link it with other works to produce a work based on this file, +## this file does not by itself cause the resulting work to be covered by +## the GNU General Public License. However the source code for this file +## must still be made available in accordance with section (3) of the GNU +## General Public License v2. +## +## This exception does not invalidate any other reasons why a work based +## on this file might be covered by the GNU General Public License. +## ------------------------------------------- +## ####ECOSGPLCOPYRIGHTEND#### +##========================================================================== +#######DESCRIPTIONBEGIN#### +## +## Author(s): nickg +## Contributors: jld +## Date: 2008-07-30 +## +######DESCRIPTIONEND#### +## +##========================================================================== + +cdl_package CYGPKG_HAL_CORTEXM_STM32 { + display "Cortex-M3/-M4 STM32 Variant" + parent CYGPKG_HAL_CORTEXM + hardware + include_dir cyg/hal + define_header hal_cortexm_stm32.h + description " + This package provides generic support for the ST Cortex-M based STM32 + microcontroller family. + It is also necessary to select a variant and platform HAL package." + + compile hal_diag.c stm32_misc.c stm32_dma.c + + implements CYGINT_HAL_DEBUG_GDB_STUBS + implements CYGINT_HAL_DEBUG_GDB_STUBS_BREAK + implements CYGINT_HAL_VIRTUAL_VECTOR_SUPPORT + implements CYGINT_HAL_VIRTUAL_VECTOR_COMM_BAUD_SUPPORT + implements CYGINT_PROFILE_HAL_TIMER + + requires { (CYGHWR_HAL_CORTEXM == "M3") || (CYGHWR_HAL_CORTEXM == "M4") } + + cdl_component CYGHWR_HAL_CORTEXM_STM32_SELECTION { + display "STM32 processor selection" + no_define + flavor none + description " + The options within this component allow you to select which STM32 + processor is in use." + + + cdl_option CYGHWR_HAL_CORTEXM_STM32 { + display "STM32 processor variant in use" + flavor data + default_value { (CYGHWR_HAL_CORTEXM_STM32_FAMILY == "F1") ? CYGHWR_HAL_CORTEXM_STM32_F1 : \ + (CYGHWR_HAL_CORTEXM_STM32_FAMILY == "F2") ? CYGHWR_HAL_CORTEXM_STM32_F2 : \ + CYGHWR_HAL_CORTEXM_STM32_F4 } + # At some point we'll add the L1, etc. here. + description "The STM32 has several variants, the main differences + being in the size of on-chip FLASH and SRAM + and numbers of some peripherals. This option + allows the platform HAL to select the specific + microcontroller fitted." + } + + cdl_option CYGHWR_HAL_CORTEXM_STM32_FAMILY { + display "Processor family in use" + flavor data + default_value { "F1" } + legal_values { "F1" "F2" "F4" } + # NOTE: F1/F2 imply CYGHWR_HAL_CORTEXM_M3 and F4 implies CYGHWR_HAL_CORTEXM_M4 + description " + Which family of STM32 processors is in use. This will + usually be the leading part of the processor model name." + } + + # NOTE: This allows later L1 support to still select "FAMILY_HIPERFORMANCE" if the I/O is the same: + cdl_option CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE { + display "Part belongs to ST Hi-Performance family" + active_if { (CYGHWR_HAL_CORTEXM_STM32_FAMILY == "F2") || (CYGHWR_HAL_CORTEXM_STM32_FAMILY == "F4") } + calculated { (CYGHWR_HAL_CORTEXM_STM32_FAMILY == "F2") || (CYGHWR_HAL_CORTEXM_STM32_FAMILY == "F4") } + description " + Indicates that this part conforms to the I/O + definitions for the Hi-Performance family of + devices. Currently this includes the STM32 F2 and F4 + devices." + } + + cdl_option CYGHWR_HAL_CORTEXM_STM32_F1 { + display "F1 processor family selection" + flavor data + active_if { CYGHWR_HAL_CORTEXM_STM32_FAMILY == "F1" } + default_value {"F103ZE"} + legal_values {"F103RC" "F103VC" "F103ZC" + "F103RD" "F103VD" "F103ZD" + "F103RE" "F103VE" "F103ZE" + "F105R8" "F105V8" + "F105RB" "F105VB" + "F105RC" "F105VC" + "F107RB" "F107VB" + "F107RC" "F107VC" + } + requires { CYGHWR_HAL_CORTEXM_STM32 == CYGHWR_HAL_CORTEXM_STM32_F1 } + description " + This option specifies which member of the STM32F1 family is + in use." + } + + cdl_option CYGHWR_HAL_CORTEXM_STM32_F2 { + display "F2 processor family selection" + flavor data + active_if { CYGHWR_HAL_CORTEXM_STM32_FAMILY == "F2" } + default_value {"F207IG"} + legal_values {"F205RB" "F205RC" "F205RE" "F205RF" "F205RG" + "F205VB" "F205VC" "F205VE" "F205VF" "F205VG" + "F205ZB" "F205ZC" "F205ZE" "F205ZF" "F205ZG" + "F207VB" "F207VC" "F207VE" "F207VF" "F207VG" + "F207ZB" "F207ZC" "F207ZE" "F207ZF" "F207ZG" + "F207IB" "F207IC" "F207IE" "F207IF" "F207IG" + } + requires { CYGHWR_HAL_CORTEXM_STM32 == CYGHWR_HAL_CORTEXM_STM32_F2 } + description " + This option specifies which member of the STM32F2 family is + in use." + } + + cdl_option CYGHWR_HAL_CORTEXM_STM32_F4 { + display "F4 processor family selection" + flavor data + active_if { CYGHWR_HAL_CORTEXM_STM32_FAMILY == "F4" } + default_value {"F407IG"} + # NOTEs: The "F4xxxE" parts have 512MB on-chip flash and + # the "F4xxxG" parts have 1MB on-chip flash. The "F41xxx" + # parts have CRYPTO support. + legal_values {"F405RG" "F405VG" "F405ZG" + "F415RG" "F415VG" "F415ZG" + "F407IG" "F407VG" "F407ZG" + "F407IE" "F407VE" "F407ZE" + "F417IG" "F417VG" "F417ZG" + "F417IE" "F417VE" "F417ZE" + } + requires { CYGHWR_HAL_CORTEXM_STM32 == CYGHWR_HAL_CORTEXM_STM32_F4 } + description " + This option specifies which member of the STM32F4 family is + in use." + } + } + + cdl_option CYGHWR_HAL_CORTEXM_STM32_CONNECTIVITY { + display "Part belongs to connectivity family" + default_value { (CYGHWR_HAL_CORTEXM_STM32 == "F105R8") || (CYGHWR_HAL_CORTEXM_STM32 == "F105V8") || + (CYGHWR_HAL_CORTEXM_STM32 == "F105RB") || (CYGHWR_HAL_CORTEXM_STM32 == "F105VB") || + (CYGHWR_HAL_CORTEXM_STM32 == "F105RC") || (CYGHWR_HAL_CORTEXM_STM32 == "F105VC") || + (CYGHWR_HAL_CORTEXM_STM32 == "F107RB") || (CYGHWR_HAL_CORTEXM_STM32 == "F107VB") || + (CYGHWR_HAL_CORTEXM_STM32 == "F107RC") || (CYGHWR_HAL_CORTEXM_STM32 == "F107VC") || + (CYGHWR_HAL_CORTEXM_STM32_FAMILY == "F2") || (CYGHWR_HAL_CORTEXM_STM32_FAMILY == "F4") + } + description "Indicates that this part belongs to the connectivity + family of devices. These have slightly different interrupt + and GPIO layouts to the original STM32 F103 devices." + } + + cdl_option CYGNUM_HAL_CORTEXM_PRIORITY_LEVEL_BITS { + display "CPU priority levels" + flavor data + calculated 4 + description "This option defines the number of bits used to + encode the exception priority levels that this + variant of the Cortex-M CPU implements." + } + + + + cdl_component CYGHWR_HAL_CORTEXM_STM32_CLOCK { + display "Clock setup calculations" + flavor none + no_define + + cdl_option CYGHWR_HAL_CORTEXM_STM32_CLOCK_PLL_SOURCE { + display "PLL input source" + flavor data + default_value { "HSE" } + legal_values { "HSI" "HSE" } + description " + This sets whether the PLL will be driven by the external + high-speed clock (HSE), or internal high-speed clock (HSI)." + } + + cdl_option CYGHWR_HAL_CORTEXM_STM32_CLOCK_PLL_PREDIV { + display "PLL pre-divider" + flavor data + default_value 1 + legal_values 1 to 63 + requires { !CYGHWR_HAL_CORTEXM_STM32_CONNECTIVITY implies (CYGHWR_HAL_CORTEXM_STM32_CLOCK_PLL_PREDIV <= 2) } + requires { (CYGHWR_HAL_CORTEXM_STM32_FAMILY=="F1") implies (CYGHWR_HAL_CORTEXM_STM32_CLOCK_PLL_PREDIV <= 16) } + requires { ((CYGHWR_HAL_CORTEXM_STM32_FAMILY=="F1") && (CYGHWR_HAL_CORTEXM_STM32_CLOCK_PLL_SOURCE == "HSI")) implies \ + (CYGHWR_HAL_CORTEXM_STM32_CLOCK_PLL_PREDIV == 2) } + requires { ((CYGHWR_HAL_CORTEXM_STM32_FAMILY=="F2") || (CYGHWR_HAL_CORTEXM_STM32_FAMILY=="F4")) implies (CYGHWR_HAL_CORTEXM_STM32_CLOCK_PLL_PREDIV >= 2) } + description " + This option corresponds to the divider used before input to the PLL. + On non-connectivity parts, you can only divide by 2 or 1. On other + F1 parts, if using HSI as the clock source, then that is automatically + divided by 2. If using HSE as the clock source, then this value corresponds + to the PREDIV1 field of register RCC_CFGR2. On F2 and F4 parts, this value + corresponds to the PLLM field of RCC_PLLCFGR." + } + + + cdl_option CYGHWR_HAL_CORTEXM_STM32_CLOCK_PLL_MUL { + display "PLL multiplier" + flavor data + default_value 9 + legal_values 2 to 432 + requires { (CYGHWR_HAL_CORTEXM_STM32_FAMILY=="F1") implies (CYGHWR_HAL_CORTEXM_STM32_CLOCK_PLL_MUL <= 16) } + requires { ((CYGHWR_HAL_CORTEXM_STM32_FAMILY=="F2") || (CYGHWR_HAL_CORTEXM_STM32_FAMILY=="F4")) implies (CYGHWR_HAL_CORTEXM_STM32_CLOCK_PLL_MUL <= 432) } + description " + This value is used to multiply up the PLL input. On the F1 it corresponds + to the PLLMUL field of RCC_CFGR. On the F2 and F4 it corresponds to the PLLN + field of RCC_PLLCFGR." + } + + cdl_option CYGHWR_HAL_CORTEXM_STM32_CLOCK_SYSCLK_DIV { + display "SYSCLK divider" + flavor data + active_if { ((CYGHWR_HAL_CORTEXM_STM32_FAMILY=="F2") || (CYGHWR_HAL_CORTEXM_STM32_FAMILY=="F4")) } + default_value 4 + legal_values { 2 4 6 8 } + description " + This value is used to divide down the PLL output for use as + the SYSCLK clock. This corresponds to the PLLP field of + RCC_PLLCFGR" + } + + cdl_option CYGHWR_HAL_CORTEXM_STM32_CLOCK_HCLK_DIV { + display "HCLK divider" + flavor data + default_value 1 + legal_values { 1 2 4 8 16 64 128 256 512 } + description "Divider for AHB" + } + + cdl_option CYGHWR_HAL_CORTEXM_STM32_CLOCK_PCLK1_DIV { + display "PCLK1 divider" + flavor data + default_value 2 + legal_values { 1 2 4 8 16 } + description "Divider for APB1" + } + + cdl_option CYGHWR_HAL_CORTEXM_STM32_CLOCK_PCLK2_DIV { + display "PCLK2 divider" + flavor data + default_value 1 + legal_values { 1 2 4 8 16 } + description "Divider for APB2" + } + + cdl_option CYGHWR_HAL_CORTEXM_STM32_CLOCK_PLLQ_DIV { + display "PLLQ divider" + flavor data + active_if { ((CYGHWR_HAL_CORTEXM_STM32_FAMILY=="F2") || (CYGHWR_HAL_CORTEXM_STM32_FAMILY=="F4")) } + default_value 10 + legal_values 4 to 15 + description " + This PLL divider is used in the F2 and F4 families to divide down the + PLL output clock (VCO clock) for use by the USB OTG FS, SDIO + and RNG peripherals. USB OTG FS requires a 48MHz clock and + other peripherals require a clock no greater than 48MHz." + } + } + + cdl_option CYGNUM_HAL_KERNEL_COUNTERS_CLOCK_ISR_DEFAULT_PRIORITY { + display "Clock interrupt ISR priority" + flavor data + calculated 0xE0 + description "Set clock ISR priority to lowest priority." + } + + cdl_component CYGNUM_HAL_RTC_CONSTANTS { + display "Real-time clock constants" + flavor none + no_define + cdl_option CYGNUM_HAL_RTC_NUMERATOR { + display "Real-time clock numerator" + flavor data + default_value 1000000000 + } + cdl_option CYGNUM_HAL_RTC_DENOMINATOR { + display "Real-time clock denominator" + flavor data + default_value 100 + } + cdl_option CYGNUM_HAL_RTC_PERIOD { + display "Real-time clock period" + flavor data + default_value 1000000 / CYGNUM_HAL_RTC_DENOMINATOR + description "The period defined here is something of a fake, it is expressed + in terms of a notional 1MHz clock. The value actually installed + in the hardware is calculated from the current settings of the + clock generation hardware." + } + } + + + cdl_interface CYGINT_HAL_STM32_UART0 { + display "Platform has UART0 serial port" + description "The platform has a socket on UART0." + } + + cdl_interface CYGINT_HAL_STM32_UART1 { + display "Platform has UART1 serial port" + description "The platform has a socket on UART1." + } + + cdl_interface CYGINT_HAL_STM32_UART2 { + display "Platform has UART2 serial port" + description "The platform has a socket on UART2." + } + + cdl_interface CYGINT_HAL_STM32_UART3 { + display "Platform has UART3 serial port" + description "The platform has a socket on UART3." + } + + cdl_interface CYGINT_HAL_STM32_UART4 { + display "Platform has UART4 serial port" + description "The platform has a socket on UART4." + } + + cdl_interface CYGINT_HAL_STM32_UART5 { + display "Platform has UART5 serial port" + description "The platform has a socket on UART5." + } + + cdl_option CYGHWR_HAL_STM32_UART0_REMAP { + display "Remap UART0 (USART1) pins" + default_value 0 + + description "Remap UART0 (USART1) to alternate set of pins. + This will usually be set by the platform + HAL to reflect the configuration of the hardware." + } + + cdl_option CYGHWR_HAL_STM32_UART1_REMAP { + display "Remap UART1 (USART2) pins" + default_value 0 + + description "Remap UART1 (USART2) to alternate set of pins. + This will usually be set by the platform + HAL to reflect the configuration of the hardware." + } + + cdl_option CYGHWR_HAL_STM32_UART2_REMAP { + display "Remap UART2 (USART3) pins" + flavor data + default_value { "NONE" } + legal_values { "NONE" "PARTIAL" "FULL" } + + description "Remap UART2 (USART3) to alternate set of pins. + This will usually be set by the platform + HAL to reflect the configuration of the hardware." + } + + cdl_option CYGHWR_HAL_STM32_I2C1_REMAP { + display "Remap I2C bus 1 pins" + default_value 0 + + description "Remap I2C bus 1 to alternate set of pins. + This will usually be set by the platform + HAL to reflect the configuration of the hardware." + } + + cdl_option CYGHWR_HAL_STM32_SPI1_REMAP { + display "Remap SPI bus 1 pins" + active_if CYGHWR_HAL_CORTEXM_STM32_CONNECTIVITY + default_value 0 + + description "Remap SPI bus 1 to alternate set of pins. + This will usually be set by the platform + HAL to reflect the configuration of the hardware." + } + + cdl_option CYGHWR_HAL_STM32_SPI3_REMAP { + display "Remap SPI bus 3 pins" + active_if CYGHWR_HAL_CORTEXM_STM32_CONNECTIVITY + default_value 0 + + description "Remap SPI bus 3 to alternate set of pins. + This will usually be set by the platform + HAL to reflect the configuration of the hardware. + This option is only available on connectivity line + devices." + } + + cdl_option CYGFUN_HAL_CORTEXM_STM32_PROFILE_TIMER { + display "Use TIM2 for gprof profiling" + active_if CYGPKG_PROFILE_GPROF + flavor bool + default_value 1 + implements CYGINT_PROFILE_HAL_TIMER + implements CYGINT_HAL_COMMON_SAVED_INTERRUPT_STATE_REQUIRED + description " + The STM32 variant HAL can provide support for gprof-based + profiling. This uses timer TIM2 to generate regular interrupts, + and the interrupt handler records the PC at the time of the + interrupt. Disable this option if you wish to provide + an alternative profiling timer implementation." + } + + cdl_component CYGPKG_HAL_CORTEXM_STM32_OPTIONS { + display "Build options" + flavor none + description " + Package specific build options including control over + compiler flags used only in building this package." + + cdl_option CYGPKG_HAL_CORTEXM_STM32_CFLAGS_ADD { + display "Additional compiler flags" + flavor data + no_define + default_value { "" } + description " + This option modifies the set of compiler flags for + building the STM32 variant HAL package. These flags are used + in addition to the set of global flags." + } + + cdl_option CYGPKG_HAL_CORTEXM_STM32_CFLAGS_REMOVE { + display "Suppressed compiler flags" + flavor data + no_define + default_value { "" } + description " + This option modifies the set of compiler flags for + building the STM32 variant HAL package. These flags are removed from + the set of global flags if present." + } + } + + cdl_option CYGPKG_HAL_CORTEXM_STM32_TESTS { + display "STM32 tests" + active_if CYGPKG_KERNEL + flavor data + no_define + calculated { "tests/timers" } + description " + This option specifies the set of tests for the STM32 HAL." + } + +} + +# EOF hal_cortexm_stm32.cdl diff --git a/ecos/packages/hal/cortexm/stm32/var/current/include/hal_cache.h b/ecos/packages/hal/cortexm/stm32/var/current/include/hal_cache.h new file mode 100644 index 0000000..0a19bc9 --- /dev/null +++ b/ecos/packages/hal/cortexm/stm32/var/current/include/hal_cache.h @@ -0,0 +1,194 @@ +#ifndef CYGONCE_HAL_CACHE_H +#define CYGONCE_HAL_CACHE_H + +//============================================================================= +// +// hal_cache.h +// +// HAL cache control API +// +//============================================================================= +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2004, 2005, 2006, 2008 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): jlarmour +// Contributors: +// Date: 2004-07-23 +// Purpose: Cache control API +// Description: The macros defined here provide the HAL APIs for handling +// cache control operations. +// +// For the STM32, these are empty macros as there +// is no cache. +// Usage: +// #include <cyg/hal/hal_cache.h> +// ... +// +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +#include <cyg/infra/cyg_type.h> + +//----------------------------------------------------------------------------- +// Cache dimensions + +// Data cache +//#define HAL_DCACHE_SIZE 0 // Size of data cache in bytes +//#define HAL_DCACHE_LINE_SIZE 0 // Size of a data cache line +//#define HAL_DCACHE_WAYS 0 // Associativity of the cache + +// Instruction cache +//#define HAL_ICACHE_SIZE 0 // Size of cache in bytes +//#define HAL_ICACHE_LINE_SIZE 0 // Size of a cache line +//#define HAL_ICACHE_WAYS 0 // Associativity of the cache + +//#define HAL_DCACHE_SETS (HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS)) +//#define HAL_ICACHE_SETS (HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS)) + +//----------------------------------------------------------------------------- +// Global control of data cache + +// Enable the data cache +#define HAL_DCACHE_ENABLE() + +// Disable the data cache +#define HAL_DCACHE_DISABLE() + +// Invalidate the entire cache +#define HAL_DCACHE_INVALIDATE_ALL() + +// Synchronize the contents of the cache with memory. +#define HAL_DCACHE_SYNC() + +// Purge contents of data cache +#define HAL_DCACHE_PURGE_ALL() + +// Query the state of the data cache (does not affect the caching) +#define HAL_DCACHE_IS_ENABLED(_state_) \ + CYG_MACRO_START \ + (_state_) = 0; \ + CYG_MACRO_END + +// Set the data cache refill burst size +//#define HAL_DCACHE_BURST_SIZE(_size_) + +// Set the data cache write mode +//#define HAL_DCACHE_WRITE_MODE( _mode_ ) + +//#define HAL_DCACHE_WRITETHRU_MODE 0 +//#define HAL_DCACHE_WRITEBACK_MODE 1 + +// Load the contents of the given address range into the data cache +// and then lock the cache so that it stays there. +//#define HAL_DCACHE_LOCK(_base_, _size_) + +// Undo a previous lock operation +//#define HAL_DCACHE_UNLOCK(_base_, _size_) + +// Unlock entire cache +//#define HAL_DCACHE_UNLOCK_ALL() + +//----------------------------------------------------------------------------- +// Data cache line control + +// Allocate cache lines for the given address range without reading its +// contents from memory. +//#define HAL_DCACHE_ALLOCATE( _base_ , _size_ ) + +// Write dirty cache lines to memory and invalidate the cache entries +// for the given address range. +//#define HAL_DCACHE_FLUSH( _base_ , _size_ ) + +// Invalidate cache lines in the given range without writing to memory. +//#define HAL_DCACHE_INVALIDATE( _base_ , _size_ ) + +// Write dirty cache lines to memory for the given address range. +//#define HAL_DCACHE_STORE( _base_ , _size_ ) + +// Preread the given range into the cache with the intention of reading +// from it later. +//#define HAL_DCACHE_READ_HINT( _base_ , _size_ ) + +// Preread the given range into the cache with the intention of writing +// to it later. +//#define HAL_DCACHE_WRITE_HINT( _base_ , _size_ ) + +// Allocate and zero the cache lines associated with the given range. +//#define HAL_DCACHE_ZERO( _base_ , _size_ ) + +//----------------------------------------------------------------------------- +// Global control of Instruction cache + +// Enable the instruction cache +#define HAL_ICACHE_ENABLE() + +// Disable the instruction cache +#define HAL_ICACHE_DISABLE() + +// Invalidate the entire cache +#define HAL_ICACHE_INVALIDATE_ALL() + +// Synchronize the contents of the cache with memory. +#define HAL_ICACHE_SYNC() + +// Query the state of the instruction cache (does not affect the caching) +#define HAL_ICACHE_IS_ENABLED(_state_) \ + CYG_MACRO_START \ + (_state_) = 0; \ + CYG_MACRO_END + +// Set the instruction cache refill burst size +//#define HAL_ICACHE_BURST_SIZE(_size_) + +// Load the contents of the given address range into the instruction cache +// and then lock the cache so that it stays there. +//#define HAL_ICACHE_LOCK(_base_, _size_) + +// Undo a previous lock operation +//#define HAL_ICACHE_UNLOCK(_base_, _size_) + +// Unlock entire cache +//#define HAL_ICACHE_UNLOCK_ALL() + +//----------------------------------------------------------------------------- +// Instruction cache line control + +// Invalidate cache lines in the given range without writing to memory. +//#define HAL_ICACHE_INVALIDATE( _base_ , _size_ ) + +//----------------------------------------------------------------------------- +#endif // ifndef CYGONCE_HAL_CACHE_H +// End of hal_cache.h diff --git a/ecos/packages/hal/cortexm/stm32/var/current/include/hal_diag.h b/ecos/packages/hal/cortexm/stm32/var/current/include/hal_diag.h new file mode 100644 index 0000000..207930b --- /dev/null +++ b/ecos/packages/hal/cortexm/stm32/var/current/include/hal_diag.h @@ -0,0 +1,91 @@ +#ifndef CYGONCE_HAL_DIAG_H +#define CYGONCE_HAL_DIAG_H +//============================================================================= +// +// hal_diag.h +// +// HAL diagnostics +// +//============================================================================= +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2008 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): nickg +// Date: 2008-07-30 +// Purpose: HAL diagnostics +// Description: +// Usage: #include <cyg/hal/var_io.h> +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +#include <pkgconf/hal.h> + +#include <cyg/infra/cyg_type.h> + +#include <cyg/hal/hal_if.h> + +//----------------------------------------------------------------------------- + +#if defined(CYGSEM_HAL_VIRTUAL_VECTOR_DIAG) + +#define HAL_DIAG_INIT() hal_if_diag_init() +#define HAL_DIAG_WRITE_CHAR(_c_) hal_if_diag_write_char(_c_) +#define HAL_DIAG_READ_CHAR(_c_) hal_if_diag_read_char(&_c_) + +#else + +__externC void hal_stm32_diag_init(void); +__externC void hal_stm32_diag_putc(char); +__externC cyg_uint8 hal_stm32_diag_getc(void); + +# ifndef HAL_DIAG_INIT +# define HAL_DIAG_INIT() hal_stm32_diag_init() +# endif + +# ifndef HAL_DIAG_WRITE_CHAR +# define HAL_DIAG_WRITE_CHAR(__c) hal_stm32_diag_putc(__c) +# endif + +# ifndef HAL_DIAG_READ_CHAR +# define HAL_DIAG_READ_CHAR(__c) (__c) = hal_stm32_diag_getc() +# endif + +#endif + + +//----------------------------------------------------------------------------- +// end of hal_diag.h +#endif // CYGONCE_HAL_DIAG_H diff --git a/ecos/packages/hal/cortexm/stm32/var/current/include/plf_stub.h b/ecos/packages/hal/cortexm/stm32/var/current/include/plf_stub.h new file mode 100644 index 0000000..d1d9db3 --- /dev/null +++ b/ecos/packages/hal/cortexm/stm32/var/current/include/plf_stub.h @@ -0,0 +1,88 @@ +#ifndef CYGONCE_HAL_PLF_STUB_H +#define CYGONCE_HAL_PLF_STUB_H + +//============================================================================= +// +// plf_stub.h +// +// Platform header for GDB stub support. +// +//============================================================================= +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2004, 2005, 2006, 2008 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): nickg +// Contributors:jskov, gthomas, jlarmour +// Date: 2008-07-30 +// Purpose: Platform HAL stub support for STM32 variant boards. +// Usage: #include <cyg/hal/plf_stub.h> +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +#include <pkgconf/hal.h> +#include CYGBLD_HAL_PLATFORM_H + +#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS + +#include <cyg/infra/cyg_type.h> // CYG_UNUSED_PARAM + +#include <cyg/hal/cortexm_stub.h> // architecture stub support + +#include <cyg/hal/hal_io.h> + +//---------------------------------------------------------------------------- +// Define some platform specific communication details. This is mostly +// handled by hal_if now, but we need to make sure the comms tables are +// properly initialized. + +__externC void cyg_hal_plf_comms_init(void); + +#define HAL_STUB_PLATFORM_INIT_SERIAL() cyg_hal_plf_comms_init() + +#define HAL_STUB_PLATFORM_SET_BAUD_RATE(baud) CYG_UNUSED_PARAM(int, (baud)) +#define HAL_STUB_PLATFORM_INTERRUPTIBLE 0 +#define HAL_STUB_PLATFORM_INIT_BREAK_IRQ() CYG_EMPTY_STATEMENT + +//---------------------------------------------------------------------------- +// Stub initializer. + +#define HAL_STUB_PLATFORM_INIT() CYG_EMPTY_STATEMENT + +#endif // ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS + +//----------------------------------------------------------------------------- +#endif // CYGONCE_HAL_PLF_STUB_H +// End of plf_stub.h diff --git a/ecos/packages/hal/cortexm/stm32/var/current/include/var_arch.h b/ecos/packages/hal/cortexm/stm32/var/current/include/var_arch.h new file mode 100644 index 0000000..1bc50a2 --- /dev/null +++ b/ecos/packages/hal/cortexm/stm32/var/current/include/var_arch.h @@ -0,0 +1,61 @@ +#ifndef CYGONCE_HAL_VAR_ARCH_H +#define CYGONCE_HAL_VAR_ARCH_H +//============================================================================= +// +// var_arch.h +// +// STM32 variant architecture overrides +// +//============================================================================= +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2008 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): nickg +// Date: 2008-07-30 +// Purpose: STM32 variant architecture overrides +// Description: +// Usage: #include <cyg/hal/hal_arch.h> +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +#include <pkgconf/hal.h> +#include <cyg/hal/hal_io.h> + +#include <cyg/hal/plf_arch.h> + +//----------------------------------------------------------------------------- +// end of var_arch.h +#endif // CYGONCE_HAL_VAR_ARCH_H diff --git a/ecos/packages/hal/cortexm/stm32/var/current/include/var_dma.h b/ecos/packages/hal/cortexm/stm32/var/current/include/var_dma.h new file mode 100644 index 0000000..dc4089f --- /dev/null +++ b/ecos/packages/hal/cortexm/stm32/var/current/include/var_dma.h @@ -0,0 +1,146 @@ +#ifndef CYGONCE_HAL_VAR_DMA_H +#define CYGONCE_HAL_VAR_DMA_H +//============================================================================= +// +// var_dma.h +// +// STM32 DMA support +// +//============================================================================= +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2011 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): nickg +// Date: 2011-12-07 +// Purpose: STM32 DMA support +// Description: +// Usage: #include <cyg/hal/var_dma.h> +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +#include <pkgconf/hal_cortexm_stm32.h> + +#include <cyg/hal/drv_api.h> + +//============================================================================= +// DMA stream descriptors + +#define CYGHWR_HAL_STM32_DMA_MODE_P2M 0 +#define CYGHWR_HAL_STM32_DMA_MODE_M2P 1 +#define CYGHWR_HAL_STM32_DMA_MODE_M2M 2 + + +// DMA descriptor. Packs interrupt vector, controller, stream and +// channel IDs together with the mode into a 32 bit descriptor. + +#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1) +#define CYGHWR_HAL_STM32_DMA( __ctlr, __stream, __chan, __mode ) \ + (((CYGNUM_HAL_INTERRUPT_DMA##__ctlr##_CH##__stream)<<16) | \ + ((CYGHWR_HAL_STM32_DMA_MODE_##__mode)<<12) | \ + ((__chan)<<8) | ((__stream)<<4) | ((__ctlr)<<0)) +#elif defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE) +#define CYGHWR_HAL_STM32_DMA( __ctlr, __stream, __chan, __mode ) \ + (((CYGNUM_HAL_INTERRUPT_DMA##__ctlr##_STR##__stream)<<16) | \ + ((CYGHWR_HAL_STM32_DMA_MODE_##__mode)<<12) | \ + ((__chan)<<8) | ((__stream)<<4) | ((__ctlr)<<0)) +#else +#error "Undefined STM32 family" +#endif + +#define CYGHWR_HAL_STM32_DMA_INTERRUPT( __desc ) (((__desc)>>16)&0xFFFF) +#define CYGHWR_HAL_STM32_DMA_MODE( __desc ) (((__desc)>>12)&0xF) +#define CYGHWR_HAL_STM32_DMA_CHANNEL( __desc ) (((__desc)>>8)&0xF) +#define CYGHWR_HAL_STM32_DMA_STREAM( __desc ) (((__desc)>>4)&0xF) +#define CYGHWR_HAL_STM32_DMA_CONTROLLER( __desc ) (((__desc)>>0)&0xF) + +//============================================================================= +// API + +#ifndef __ASSEMBLER__ + +typedef struct hal_stm32_dma_stream hal_stm32_dma_stream; + +typedef void hal_stm32_dma_callback( hal_stm32_dma_stream *stream, cyg_uint32 count, CYG_ADDRWORD data ); + +struct hal_stm32_dma_stream +{ + // These fields need to be initialized before calling + // hal_stm32_dma_init(). This can usually be done statically, when + // defining an containing data structure. + + cyg_uint32 desc; // stream descriptor + hal_stm32_dma_callback *callback; // Callback function + CYG_ADDRWORD data; // Client private data + + + // Runtime data + + CYG_ADDRWORD ctlr; // Controller base address + CYG_ADDRWORD stream; // Stream/channel index + + cyg_uint32 ccr; // Channel control register value + cyg_bool active; // Channel active + cyg_uint32 count; // Bytes left to transfer + + cyg_interrupt interrupt; // DMA interrupt object + cyg_handle_t handle; // Interrupt handle +}; + + +__externC void hal_stm32_dma_init( hal_stm32_dma_stream *stream, int pri ); + +__externC void hal_stm32_dma_delete( hal_stm32_dma_stream *stream ); + +__externC void hal_stm32_dma_disable( hal_stm32_dma_stream *stream ); + +__externC void hal_stm32_dma_poll( hal_stm32_dma_stream *stream ); + +__externC void hal_stm32_dma_configure( hal_stm32_dma_stream *stream, int tfr_size, + cyg_bool no_minc, cyg_bool polled ); + +__externC void hal_stm32_dma_configure_circular( hal_stm32_dma_stream *stream, + cyg_bool enable); + +__externC void hal_stm32_dma_start( hal_stm32_dma_stream *stream, void *memory, + CYG_ADDRESS peripheral, cyg_uint32 size ); + +__externC void hal_stm32_dma_show( hal_stm32_dma_stream *stream ); + +#endif // __ASSEMBLER__ + +#endif // CYGONCE_HAL_VAR_DMA_H +//----------------------------------------------------------------------------- +// end of var_dma.h diff --git a/ecos/packages/hal/cortexm/stm32/var/current/include/var_intr.h b/ecos/packages/hal/cortexm/stm32/var/current/include/var_intr.h new file mode 100644 index 0000000..05835f9 --- /dev/null +++ b/ecos/packages/hal/cortexm/stm32/var/current/include/var_intr.h @@ -0,0 +1,427 @@ +#ifndef CYGONCE_HAL_VAR_INTR_H +#define CYGONCE_HAL_VAR_INTR_H +//========================================================================== +// +// var_intr.h +// +// HAL Interrupt and clock assignments for STM32 variants +// +//========================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2008, 2009 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): nickg +// Date: 2008-10-06 +// Purpose: Define Interrupt support +// Description: The interrupt specifics for ST STM32 variants are +// defined here. +// +// Usage: #include <cyg/hal/var_intr.h> +// However applications should include using <cyg/hal/hal_intr.h> +// instead to allow for platform overrides. +// +//####DESCRIPTIONEND#### +// +//========================================================================== + +#include <cyg/hal/plf_intr.h> + +//========================================================================== + + +#define CYGNUM_HAL_INTERRUPT_WWDG ( 0+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_PVD ( 1+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_TAMPER ( 2+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_TAMP_STAMP ( 2+CYGNUM_HAL_INTERRUPT_EXTERNAL) // F2/F4 name - also timestamps +#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1) +#define CYGNUM_HAL_INTERRUPT_RTC_GLOBAL ( 3+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#elif defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE) +#define CYGNUM_HAL_INTERRUPT_RTC_WKUP ( 3+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#endif +#define CYGNUM_HAL_INTERRUPT_FLASH ( 4+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_RCC ( 5+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_EXTI0 ( 6+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_EXTI1 ( 7+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_EXTI2 ( 8+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_EXTI3 ( 9+CYGNUM_HAL_INTERRUPT_EXTERNAL) + +#define CYGNUM_HAL_INTERRUPT_EXTI4 (10+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_DMA1_CH1 (11+CYGNUM_HAL_INTERRUPT_EXTERNAL) // F1 has channels +#define CYGNUM_HAL_INTERRUPT_DMA1_STR0 (11+CYGNUM_HAL_INTERRUPT_EXTERNAL) // F2/F4 has streams +#define CYGNUM_HAL_INTERRUPT_DMA1_CH2 (12+CYGNUM_HAL_INTERRUPT_EXTERNAL) // F1 has channels +#define CYGNUM_HAL_INTERRUPT_DMA1_STR1 (12+CYGNUM_HAL_INTERRUPT_EXTERNAL) // F2/F4 has streams +#define CYGNUM_HAL_INTERRUPT_DMA1_CH3 (13+CYGNUM_HAL_INTERRUPT_EXTERNAL) // F1 has channels +#define CYGNUM_HAL_INTERRUPT_DMA1_STR2 (13+CYGNUM_HAL_INTERRUPT_EXTERNAL) // F2/F4 has streams +#define CYGNUM_HAL_INTERRUPT_DMA1_CH4 (14+CYGNUM_HAL_INTERRUPT_EXTERNAL) // F1 has channels +#define CYGNUM_HAL_INTERRUPT_DMA1_STR3 (14+CYGNUM_HAL_INTERRUPT_EXTERNAL) // F2/F4 has streams +#define CYGNUM_HAL_INTERRUPT_DMA1_CH5 (15+CYGNUM_HAL_INTERRUPT_EXTERNAL) // F1 has channels +#define CYGNUM_HAL_INTERRUPT_DMA1_STR4 (15+CYGNUM_HAL_INTERRUPT_EXTERNAL) // F2/F4 has streams +#define CYGNUM_HAL_INTERRUPT_DMA1_CH6 (16+CYGNUM_HAL_INTERRUPT_EXTERNAL) // F1 has channels +#define CYGNUM_HAL_INTERRUPT_DMA1_STR5 (16+CYGNUM_HAL_INTERRUPT_EXTERNAL) // F2/F4 has streams +#define CYGNUM_HAL_INTERRUPT_DMA1_CH7 (17+CYGNUM_HAL_INTERRUPT_EXTERNAL) // F1 has channels +#define CYGNUM_HAL_INTERRUPT_DMA1_STR6 (17+CYGNUM_HAL_INTERRUPT_EXTERNAL) // F2/F4 has streams +#define CYGNUM_HAL_INTERRUPT_ADC1_2 (18+CYGNUM_HAL_INTERRUPT_EXTERNAL) // F1 only has ADC1+2 +#define CYGNUM_HAL_INTERRUPT_ADC1_2_3 (18+CYGNUM_HAL_INTERRUPT_EXTERNAL) // F2/F4 has ADC1+2+3 +#define CYGNUM_HAL_INTERRUPT_ADC (18+CYGNUM_HAL_INTERRUPT_EXTERNAL) // More generic name +#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1) +#define CYGNUM_HAL_INTERRUPT_USB_HP (19+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#endif +#define CYGNUM_HAL_INTERRUPT_CAN1_TX (19+CYGNUM_HAL_INTERRUPT_EXTERNAL) + +#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1) +#define CYGNUM_HAL_INTERRUPT_USB_LP (20+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#endif +#define CYGNUM_HAL_INTERRUPT_CAN1_RX0 (20+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_CAN1_RX1 (21+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_CAN1_SCE (22+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_EXTI9_5 (23+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_TIM1_BRK (24+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_TIM1_BRK_TIM9 (24+CYGNUM_HAL_INTERRUPT_EXTERNAL) // F2/F4 name because is also TIM9 +#define CYGNUM_HAL_INTERRUPT_TIM1_UP (25+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_TIM1_UP_TIM10 (25+CYGNUM_HAL_INTERRUPT_EXTERNAL) // F2/F4 name because is also TIM10 +#define CYGNUM_HAL_INTERRUPT_TIM1_TRG (26+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_TIM1_TRG_COM_TIM11 (26+CYGNUM_HAL_INTERRUPT_EXTERNAL) // F2/F4 name because is also TIM11 +#define CYGNUM_HAL_INTERRUPT_TIM1_CC (27+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_TIM2 (28+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_TIM3 (29+CYGNUM_HAL_INTERRUPT_EXTERNAL) + +#define CYGNUM_HAL_INTERRUPT_TIM4 (30+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_I2C1_EV (31+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_I2C1_EE (32+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_I2C2_EV (33+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_I2C2_EE (34+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_SPI1 (35+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_SPI2 (36+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_UART1 (37+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_UART2 (38+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_UART3 (39+CYGNUM_HAL_INTERRUPT_EXTERNAL) + +#define CYGNUM_HAL_INTERRUPT_EXTI15_10 (40+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_RTC_ALARM (41+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1) +#define CYGNUM_HAL_INTERRUPT_USB_WAKEUP (42+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#elif defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE) +#define CYGNUM_HAL_INTERRUPT_OTG_FS_WKUP (42+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#endif +#ifndef CYGHWR_HAL_CORTEXM_STM32_CONNECTIVITY +#define CYGNUM_HAL_INTERRUPT_TIM8_BRK (43+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_TIM8_UP (44+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_TIM8_TRG (45+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_TIM8_CC (46+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1) +#define CYGNUM_HAL_INTERRUPT_ADC3 (47+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#endif +#define CYGNUM_HAL_INTERRUPT_FSMC (48+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_SDIO (49+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#else +#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE) +#define CYGNUM_HAL_INTERRUPT_TIM8_BRK_TIM12 (43+CYGNUM_HAL_INTERRUPT_EXTERNAL) // F2/F4 name because is also TIM12 +#define CYGNUM_HAL_INTERRUPT_TIM8_UP_TIM13 (44+CYGNUM_HAL_INTERRUPT_EXTERNAL) // F2/F4 name because is also TIM13 +#define CYGNUM_HAL_INTERRUPT_TIM8_TRG_COM_TIM14 (45+CYGNUM_HAL_INTERRUPT_EXTERNAL) // F2/F4 name because is also TIM13 +#define CYGNUM_HAL_INTERRUPT_TIM8_CC (46+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_DMA1_STR7 (47+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_FSMC (48+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_SDIO (49+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#endif +#endif + +#define CYGNUM_HAL_INTERRUPT_TIM5 (50+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_SPI3 (51+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_UART4 (52+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_UART5 (53+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_TIM6 (54+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_TIM6_DAC (54+CYGNUM_HAL_INTERRUPT_EXTERNAL) // F2/F4 name because also DAC1+2 underrun +#define CYGNUM_HAL_INTERRUPT_TIM7 (55+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_DMA2_CH1 (56+CYGNUM_HAL_INTERRUPT_EXTERNAL) // F1 has channels +#define CYGNUM_HAL_INTERRUPT_DMA2_STR0 (56+CYGNUM_HAL_INTERRUPT_EXTERNAL) // F2/F4 has streams +#define CYGNUM_HAL_INTERRUPT_DMA2_CH2 (57+CYGNUM_HAL_INTERRUPT_EXTERNAL) // F1 has channels +#define CYGNUM_HAL_INTERRUPT_DMA2_STR1 (57+CYGNUM_HAL_INTERRUPT_EXTERNAL) // F2/F4 has streams +#define CYGNUM_HAL_INTERRUPT_DMA2_CH3 (58+CYGNUM_HAL_INTERRUPT_EXTERNAL) // F1 has channels +#define CYGNUM_HAL_INTERRUPT_DMA2_STR2 (58+CYGNUM_HAL_INTERRUPT_EXTERNAL) // F2/F4 has streams + +#ifndef CYGHWR_HAL_CORTEXM_STM32_CONNECTIVITY + +#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE) +# error Support does not yet exist for F2 or F4 without connectivity +#endif + +#define CYGNUM_HAL_INTERRUPT_DMA2_CH4 (59+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_DMA2_CH5 (CYGNUM_HAL_INTERRUPT_DMA2_CH4) // As per RM0008 datasheet 3.3.6 note + +#define CYGNUM_HAL_INTERRUPT_NVIC_MAX (59+CYGNUM_HAL_INTERRUPT_EXTERNAL) + +#else + +#define CYGNUM_HAL_INTERRUPT_DMA2_CH4 (59+CYGNUM_HAL_INTERRUPT_EXTERNAL) // F1 has channels +#define CYGNUM_HAL_INTERRUPT_DMA2_STR3 (59+CYGNUM_HAL_INTERRUPT_EXTERNAL) // F2/F4 has streams + +#define CYGNUM_HAL_INTERRUPT_DMA2_CH5 (60+CYGNUM_HAL_INTERRUPT_EXTERNAL) // F1 has channels +#define CYGNUM_HAL_INTERRUPT_DMA2_STR4 (60+CYGNUM_HAL_INTERRUPT_EXTERNAL) // F2/F4 has streams +#define CYGNUM_HAL_INTERRUPT_ETH (61+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_ETH_WAKEUP (62+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_CAN2_TX (63+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_CAN2_RX0 (64+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_CAN2_RX1 (65+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_CAN2_SCE (66+CYGNUM_HAL_INTERRUPT_EXTERNAL) + +#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1) +#define CYGNUM_HAL_INTERRUPT_USB_FS (67+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_NVIC_MAX (67+CYGNUM_HAL_INTERRUPT_EXTERNAL) + +#elif defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE) +#define CYGNUM_HAL_INTERRUPT_OTG_FS (67+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_DMA2_STR5 (68+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_DMA2_STR6 (69+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_DMA2_STR7 (70+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_UART6 (71+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_I2C3_EV (72+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_I2C3_ER (73+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_OTG_HS_EP1_OUT (74+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_OTG_HS_EP1_IN (75+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_OTG_HS_WKUP (76+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_OTG_HS (77+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_DCMI (78+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_CRYP (79+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#define CYGNUM_HAL_INTERRUPT_HASH_RNG (80+CYGNUM_HAL_INTERRUPT_EXTERNAL) + +#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F4) +# define CYGNUM_HAL_INTERRUPT_HASH_FPU (81+CYGNUM_HAL_INTERRUPT_EXTERNAL) + +# define CYGNUM_HAL_INTERRUPT_NVIC_MAX (81+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#elif defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F2) +# define CYGNUM_HAL_INTERRUPT_NVIC_MAX (80+CYGNUM_HAL_INTERRUPT_EXTERNAL) +#else +# error "Support does not yet exist for this FAMILY_HIPERFORMANCE configuration" +#endif +#endif // elif defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE) + +#endif // ifdef CYGHWR_HAL_CORTEXM_STM32_CONNECTIVITY + +#define CYGNUM_HAL_INTERRUPT_EXTI5 ( 1+CYGNUM_HAL_INTERRUPT_NVIC_MAX) +#define CYGNUM_HAL_INTERRUPT_EXTI6 ( 2+CYGNUM_HAL_INTERRUPT_NVIC_MAX) +#define CYGNUM_HAL_INTERRUPT_EXTI7 ( 3+CYGNUM_HAL_INTERRUPT_NVIC_MAX) +#define CYGNUM_HAL_INTERRUPT_EXTI8 ( 4+CYGNUM_HAL_INTERRUPT_NVIC_MAX) +#define CYGNUM_HAL_INTERRUPT_EXTI9 ( 5+CYGNUM_HAL_INTERRUPT_NVIC_MAX) +#define CYGNUM_HAL_INTERRUPT_EXTI10 ( 6+CYGNUM_HAL_INTERRUPT_NVIC_MAX) +#define CYGNUM_HAL_INTERRUPT_EXTI11 ( 7+CYGNUM_HAL_INTERRUPT_NVIC_MAX) +#define CYGNUM_HAL_INTERRUPT_EXTI12 ( 8+CYGNUM_HAL_INTERRUPT_NVIC_MAX) +#define CYGNUM_HAL_INTERRUPT_EXTI13 ( 9+CYGNUM_HAL_INTERRUPT_NVIC_MAX) +#define CYGNUM_HAL_INTERRUPT_EXTI14 (10+CYGNUM_HAL_INTERRUPT_NVIC_MAX) +#define CYGNUM_HAL_INTERRUPT_EXTI15 (11+CYGNUM_HAL_INTERRUPT_NVIC_MAX) + +#define CYGNUM_HAL_ISR_MIN 0 +#define CYGNUM_HAL_ISR_MAX CYGNUM_HAL_INTERRUPT_EXTI15 +#define CYGNUM_HAL_ISR_COUNT (CYGNUM_HAL_ISR_MAX + 1) + +#define CYGNUM_HAL_VSR_MIN 0 +#ifndef CYGNUM_HAL_VSR_MAX +#define CYGNUM_HAL_VSR_MAX (CYGNUM_HAL_VECTOR_SYS_TICK+CYGNUM_HAL_INTERRUPT_NVIC_MAX) +#endif +#define CYGNUM_HAL_VSR_COUNT (CYGNUM_HAL_VSR_MAX+1) + +//========================================================================== +// Interrupt mask and config for variant-specific devices + +#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1) +#define HAL_VAR_PERIPH_EXTI_MAP_FAMILY \ + case CYGNUM_HAL_INTERRUPT_PVD: \ + __v = 16; \ + break; \ + case CYGNUM_HAL_INTERRUPT_RTC_ALARM: \ + __v = 17; \ + break; \ + case CYGNUM_HAL_INTERRUPT_USB_WAKEUP: \ + __v = 18; \ + break; + +#elif defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE) + +#define HAL_VAR_PERIPH_EXTI_MAP_FAMILY \ + case CYGNUM_HAL_INTERRUPT_PVD: \ + __v = 16; \ + break; \ + case CYGNUM_HAL_INTERRUPT_RTC_ALARM: \ + __v = 17; \ + break; \ + case CYGNUM_HAL_INTERRUPT_OTG_FS_WKUP: \ + __v = 18; \ + break; \ + case CYGNUM_HAL_INTERRUPT_ETH_WAKEUP: \ + __v = 19; \ + break; \ + case CYGNUM_HAL_INTERRUPT_OTG_HS_WKUP: \ + __v = 20; \ + break; \ + case CYGNUM_HAL_INTERRUPT_TAMP_STAMP: \ + __v = 21; \ + break; \ + case CYGNUM_HAL_INTERRUPT_RTC_WKUP: \ + __v = 22; \ + break; + +#endif // elif defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE) + +#define HAL_VAR_INTERRUPT_MASK( __vector ) \ +{ \ + cyg_int32 __v = -1; \ + \ + switch( __vector ) \ + { \ + case CYGNUM_HAL_INTERRUPT_EXTI0...CYGNUM_HAL_INTERRUPT_EXTI4: \ + __v = __vector - CYGNUM_HAL_INTERRUPT_EXTI0; \ + break; \ + \ + case CYGNUM_HAL_INTERRUPT_EXTI5...CYGNUM_HAL_INTERRUPT_EXTI9: \ + __v = __vector - CYGNUM_HAL_INTERRUPT_EXTI5 + 5; \ + break; \ + \ + case CYGNUM_HAL_INTERRUPT_EXTI10...CYGNUM_HAL_INTERRUPT_EXTI15: \ + __v = __vector - CYGNUM_HAL_INTERRUPT_EXTI5 + 5; \ + break; \ + \ + HAL_VAR_PERIPH_EXTI_MAP_FAMILY \ + } \ + \ + if( __v >= 0 ) \ + { \ + cyg_uint32 __imr; \ + HAL_READ_UINT32( CYGHWR_HAL_STM32_EXTI+CYGHWR_HAL_STM32_EXTI_IMR, __imr ); \ + __imr &= ~CYGHWR_HAL_STM32_EXTI_BIT(__v); \ + HAL_WRITE_UINT32( CYGHWR_HAL_STM32_EXTI+CYGHWR_HAL_STM32_EXTI_IMR, __imr ); \ + } \ +} + +#define HAL_VAR_INTERRUPT_UNMASK( __vector ) \ +{ \ + cyg_int32 __v = -1; \ + \ + switch( __vector ) \ + { \ + case CYGNUM_HAL_INTERRUPT_EXTI0...CYGNUM_HAL_INTERRUPT_EXTI4: \ + __v = __vector - CYGNUM_HAL_INTERRUPT_EXTI0; \ + break; \ + \ + case CYGNUM_HAL_INTERRUPT_EXTI5...CYGNUM_HAL_INTERRUPT_EXTI9: \ + __v = __vector - CYGNUM_HAL_INTERRUPT_EXTI5 + 5; \ + HAL_WRITE_UINT32( CYGARC_REG_NVIC_BASE+CYGARC_REG_NVIC_SER(CYGNUM_HAL_INTERRUPT_EXTI9_5-CYGNUM_HAL_INTERRUPT_EXTERNAL), \ + CYGARC_REG_NVIC_IBIT(CYGNUM_HAL_INTERRUPT_EXTI9_5-CYGNUM_HAL_INTERRUPT_EXTERNAL) ); \ + break; \ + \ + case CYGNUM_HAL_INTERRUPT_EXTI10...CYGNUM_HAL_INTERRUPT_EXTI15: \ + __v = __vector - CYGNUM_HAL_INTERRUPT_EXTI5 + 5; \ + HAL_WRITE_UINT32( CYGARC_REG_NVIC_BASE+CYGARC_REG_NVIC_SER(CYGNUM_HAL_INTERRUPT_EXTI15_10-CYGNUM_HAL_INTERRUPT_EXTERNAL), \ + CYGARC_REG_NVIC_IBIT(CYGNUM_HAL_INTERRUPT_EXTI15_10-CYGNUM_HAL_INTERRUPT_EXTERNAL) ); \ + break; \ + \ + HAL_VAR_PERIPH_EXTI_MAP_FAMILY \ + } \ + \ + if( __v >= 0 ) \ + { \ + cyg_uint32 __imr; \ + HAL_READ_UINT32( CYGHWR_HAL_STM32_EXTI+CYGHWR_HAL_STM32_EXTI_IMR, __imr ); \ + __imr |= CYGHWR_HAL_STM32_EXTI_BIT(__v); \ + HAL_WRITE_UINT32( CYGHWR_HAL_STM32_EXTI+CYGHWR_HAL_STM32_EXTI_IMR, __imr ); \ + } \ +} + +#define HAL_VAR_INTERRUPT_SET_LEVEL( __vector, __level ) CYG_EMPTY_STATEMENT + +#define HAL_VAR_INTERRUPT_ACKNOWLEDGE( __vector ) \ +{ \ + cyg_int32 __v = -1; \ + \ + switch( __vector ) \ + { \ + case CYGNUM_HAL_INTERRUPT_EXTI0...CYGNUM_HAL_INTERRUPT_EXTI4: \ + __v = __vector - CYGNUM_HAL_INTERRUPT_EXTI0; \ + break; \ + \ + case CYGNUM_HAL_INTERRUPT_EXTI5...CYGNUM_HAL_INTERRUPT_EXTI9: \ + __v = __vector - CYGNUM_HAL_INTERRUPT_EXTI5 + 5; \ + break; \ + \ + case CYGNUM_HAL_INTERRUPT_EXTI10...CYGNUM_HAL_INTERRUPT_EXTI15: \ + __v = __vector - CYGNUM_HAL_INTERRUPT_EXTI5 + 5; \ + break; \ + \ + HAL_VAR_PERIPH_EXTI_MAP_FAMILY \ + } \ + \ + if( __v >= 0 ) \ + { \ + cyg_uint32 __bit = CYGHWR_HAL_STM32_EXTI_BIT(__v); \ + HAL_WRITE_UINT32( CYGHWR_HAL_STM32_EXTI+CYGHWR_HAL_STM32_EXTI_PR, __bit ); \ + } \ +} + +#define HAL_VAR_INTERRUPT_CONFIGURE( __vector, __level, __up ) \ +{ \ + cyg_int32 __v = -1; \ + \ + switch( __vector ) \ + { \ + case CYGNUM_HAL_INTERRUPT_EXTI0...CYGNUM_HAL_INTERRUPT_EXTI4: \ + __v = __vector - CYGNUM_HAL_INTERRUPT_EXTI0; \ + break; \ + \ + case CYGNUM_HAL_INTERRUPT_EXTI5...CYGNUM_HAL_INTERRUPT_EXTI9: \ + __v = __vector - CYGNUM_HAL_INTERRUPT_EXTI5 + 5; \ + break; \ + \ + case CYGNUM_HAL_INTERRUPT_EXTI10...CYGNUM_HAL_INTERRUPT_EXTI15: \ + __v = __vector - CYGNUM_HAL_INTERRUPT_EXTI5 + 5; \ + break; \ + \ + HAL_VAR_PERIPH_EXTI_MAP_FAMILY \ + } \ + \ + if(( __v >= 0 ) && !(__level) ) \ + { \ + cyg_uint32 __base = CYGHWR_HAL_STM32_EXTI; \ + cyg_uint32 __rtsr, __ftsr; \ + cyg_uint32 __bit = CYGHWR_HAL_STM32_EXTI_BIT(__v); \ + HAL_READ_UINT32( __base+CYGHWR_HAL_STM32_EXTI_RTSR, __rtsr ); \ + HAL_READ_UINT32( __base+CYGHWR_HAL_STM32_EXTI_FTSR, __ftsr ); \ + if( __up ) __rtsr |= __bit, __ftsr &= ~__bit; \ + else __ftsr |= __bit, __rtsr &= ~__bit; \ + HAL_WRITE_UINT32( __base+CYGHWR_HAL_STM32_EXTI_RTSR, __rtsr ); \ + HAL_WRITE_UINT32( __base+CYGHWR_HAL_STM32_EXTI_FTSR, __ftsr ); \ + } \ +} + + +//---------------------------------------------------------------------------- +#endif // CYGONCE_HAL_VAR_INTR_H +// EOF var_intr.h diff --git a/ecos/packages/hal/cortexm/stm32/var/current/include/var_io.h b/ecos/packages/hal/cortexm/stm32/var/current/include/var_io.h new file mode 100644 index 0000000..b947bf5 --- /dev/null +++ b/ecos/packages/hal/cortexm/stm32/var/current/include/var_io.h @@ -0,0 +1,1931 @@ +#ifndef CYGONCE_HAL_VAR_IO_H +#define CYGONCE_HAL_VAR_IO_H +//============================================================================= +// +// var_io.h +// +// Variant specific registers +// +//============================================================================= +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2008, 2009, 2013 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): nickg +// Date: 2008-07-30 +// Purpose: STM32 variant specific registers +// Description: +// Usage: #include <cyg/hal/var_io.h> +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +#include <pkgconf/hal_cortexm_stm32.h> + +#include <cyg/hal/plf_io.h> + +//============================================================================= +// Peripherals + +#define CYGHWR_HAL_STM32_TIM2 0x40000000 +#define CYGHWR_HAL_STM32_TIM3 0x40000400 +#define CYGHWR_HAL_STM32_TIM4 0x40000800 +#define CYGHWR_HAL_STM32_TIM5 0x40000C00 +#define CYGHWR_HAL_STM32_TIM6 0x40001000 +#define CYGHWR_HAL_STM32_TIM7 0x40001400 +#if defined(CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE) +#define CYGHWR_HAL_STM32_TIM12 0x40001800 +#define CYGHWR_HAL_STM32_TIM13 0x40001C00 +#define CYGHWR_HAL_STM32_TIM14 0x40002000 +#endif +#define CYGHWR_HAL_STM32_RTC 0x40002800 +#define CYGHWR_HAL_STM32_WWDG 0x40002C00 +#define CYGHWR_HAL_STM32_IWDG 0x40003000 +#define CYGHWR_HAL_STM32_SPI2 0x40003800 +#define CYGHWR_HAL_STM32_SPI3 0x40003C00 +#define CYGHWR_HAL_STM32_UART2 0x40004400 +#define CYGHWR_HAL_STM32_UART3 0x40004800 +#define CYGHWR_HAL_STM32_UART4 0x40004C00 +#define CYGHWR_HAL_STM32_UART5 0x40005000 +#define CYGHWR_HAL_STM32_I2C1 0x40005400 +#define CYGHWR_HAL_STM32_I2C2 0x40005800 +#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1) +#define CYGHWR_HAL_STM32_USB 0x40005C00 +#define CYGHWR_HAL_STM32_USB_CAN_SRAM 0x40006000 +#elif defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE) +#define CYGHWR_HAL_STM32_I2C3 0x40005C00 +#endif +#define CYGHWR_HAL_STM32_BXCAN1 0x40006400 +#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE) +#define CYGHWR_HAL_STM32_BXCAN2 0x40006800 +#endif +#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1) +#define CYGHWR_HAL_STM32_BKP 0x40006C00 +#endif +#define CYGHWR_HAL_STM32_PWR 0x40007000 +#define CYGHWR_HAL_STM32_DAC 0x40007400 +#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1) +#define CYGHWR_HAL_STM32_AFIO 0x40010000 +#define CYGHWR_HAL_STM32_EXTI 0x40010400 +#define CYGHWR_HAL_STM32_GPIOA 0x40010800 +#define CYGHWR_HAL_STM32_GPIOB 0x40010C00 +#define CYGHWR_HAL_STM32_GPIOC 0x40011000 +#define CYGHWR_HAL_STM32_GPIOD 0x40011400 +#define CYGHWR_HAL_STM32_GPIOE 0x40011800 +#define CYGHWR_HAL_STM32_GPIOF 0x40011C00 +#define CYGHWR_HAL_STM32_GPIOG 0x40012000 +#define CYGHWR_HAL_STM32_ADC1 0x40012400 +#define CYGHWR_HAL_STM32_ADC2 0x40012800 +#define CYGHWR_HAL_STM32_TIM1 0x40012C00 +#elif defined(CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE) +#define CYGHWR_HAL_STM32_TIM1 0x40010000 +#define CYGHWR_HAL_STM32_PWM1 0x40010000 +#define CYGHWR_HAL_STM32_TIM8 0x40010400 +#define CYGHWR_HAL_STM32_PWM2 0x40010400 +#define CYGHWR_HAL_STM32_UART1 0x40011000 +#define CYGHWR_HAL_STM32_UART6 0x40011400 +#define CYGHWR_HAL_STM32_ADC1 0x40012000 +#define CYGHWR_HAL_STM32_ADC2 CYGHWR_HAL_STM32_ADC1 + 0x0100 +#define CYGHWR_HAL_STM32_ADC3 CYGHWR_HAL_STM32_ADC1 + 0x0200 +#define CYGHWR_HAL_STM32_ADC_COMMON CYGHWR_HAL_STM32_ADC1 + 0x0300 +#define CYGHWR_HAL_STM32_SDIO 0x40012C00 +#endif +#define CYGHWR_HAL_STM32_SPI1 0x40013000 +#if defined(CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1) +#define CYGHWR_HAL_STM32_TIM8 0x40013400 +#define CYGHWR_HAL_STM32_UART1 0x40013800 +#define CYGHWR_HAL_STM32_ADC3 0x40013C00 +#define CYGHWR_HAL_STM32_SDIO 0x40018000 +#define CYGHWR_HAL_STM32_DMA1 0x40020000 +#define CYGHWR_HAL_STM32_DMA2 0x40020400 +#define CYGHWR_HAL_STM32_RCC 0x40021000 +#define CYGHWR_HAL_STM32_FLASH 0x40022000 +#elif defined(CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE) +#define CYGHWR_HAL_STM32_SYSCFG 0x40013800 +#define CYGHWR_HAL_STM32_EXTI 0x40013C00 +#define CYGHWR_HAL_STM32_TIM9 0x40014000 +#define CYGHWR_HAL_STM32_TIM10 0x40014400 +#define CYGHWR_HAL_STM32_TIM11 0x40014800 +#define CYGHWR_HAL_STM32_GPIOA 0x40020000 +#define CYGHWR_HAL_STM32_GPIOB 0x40020400 +#define CYGHWR_HAL_STM32_GPIOC 0x40020800 +#define CYGHWR_HAL_STM32_GPIOD 0x40020C00 +#define CYGHWR_HAL_STM32_GPIOE 0x40021000 +#define CYGHWR_HAL_STM32_GPIOF 0x40021400 +#define CYGHWR_HAL_STM32_GPIOG 0x40021800 +#define CYGHWR_HAL_STM32_GPIOH 0x40021C00 +#define CYGHWR_HAL_STM32_GPIOI 0x40022000 +#endif +#define CYGHWR_HAL_STM32_CRC 0x40023000 +#if defined(CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE) +#define CYGHWR_HAL_STM32_RCC 0x40023800 +#define CYGHWR_HAL_STM32_FLASH 0x40023C00 +#define CYGHWR_HAL_STM32_BKPSRAM 0x40024000 +#define CYGHWR_HAL_STM32_DMA1 0x40026000 +#define CYGHWR_HAL_STM32_DMA2 0x40026400 +#endif +#define CYGHWR_HAL_STM32_ETH 0x40028000 +#if defined(CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE) +#define CYGHWR_HAL_STM32_USB_OTG_HS 0x40040000 +#endif +#define CYGHWR_HAL_STM32_USB_OTG_FS 0x50000000 +#define CYGHWR_HAL_STM32_OTG CYGHWR_HAL_STM32_USB_OTG_FS // compatibility define. Deprecated. +#if defined(CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE) +#define CYGHWR_HAL_STM32_DCMI 0x50050000 +#define CYGHWR_HAL_STM32_CRYP 0x50060000 +#define CYGHWR_HAL_STM32_HASH 0x50060400 +#define CYGHWR_HAL_STM32_RNG 0x50060800 +#endif +#define CYGHWR_HAL_STM32_FSMC 0xA0000000 + +//============================================================================= +// Device signature and ID registers + +#define CYGHWR_HAL_STM32_DEV_SIG 0x1FFFF7E0 +#define CYGHWR_HAL_STM32_DEV_SIG_RSIZE(__s) (((__s)>>16)&0xFFFF) +#define CYGHWR_HAL_STM32_DEV_SIG_FSIZE(__s) ((__s)&0xFFFF) + +#define CYGHWR_HAL_STM32_MCU_ID 0xe0042000 +#define CYGHWR_HAL_STM32_MCU_ID_DEV(__x) ((__x)&0xFFF) +#define CYGHWR_HAL_STM32_MCU_ID_DEV_MEDIUM 0x410 +#define CYGHWR_HAL_STM32_MCU_ID_DEV_HIGH 0x414 +#define CYGHWR_HAL_STM32_MCU_ID_REV(__x) (((__x)>>16)&0xFFFF) + +//============================================================================= +// RCC +// +// Not all registers are described here + +#define CYGHWR_HAL_STM32_RCC_CR 0x00 +#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1) +#define CYGHWR_HAL_STM32_RCC_CFGR 0x04 +#define CYGHWR_HAL_STM32_RCC_CIR 0x08 +#define CYGHWR_HAL_STM32_RCC_APB2RSTR 0x0C +#define CYGHWR_HAL_STM32_RCC_APB1RSTR 0x10 +#define CYGHWR_HAL_STM32_RCC_AHBENR 0x14 +#define CYGHWR_HAL_STM32_RCC_APB2ENR 0x18 +#define CYGHWR_HAL_STM32_RCC_APB1ENR 0x1C +#define CYGHWR_HAL_STM32_RCC_BDCR 0x20 +#define CYGHWR_HAL_STM32_RCC_CSR 0x24 +# ifdef CYGHWR_HAL_CORTEXM_STM32_CONNECTIVITY +#define CYGHWR_HAL_STM32_RCC_AHBRSTR 0x28 +#define CYGHWR_HAL_STM32_RCC_CFGR2 0x2C +# endif +#elif defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE) +#define CYGHWR_HAL_STM32_RCC_PLLCFGR 0x04 +#define CYGHWR_HAL_STM32_RCC_CFGR 0x08 +#define CYGHWR_HAL_STM32_RCC_CIR 0x0C +#define CYGHWR_HAL_STM32_RCC_AHB1RSTR 0x10 +#define CYGHWR_HAL_STM32_RCC_AHB2RSTR 0x14 +#define CYGHWR_HAL_STM32_RCC_AHB3RSTR 0x18 +#define CYGHWR_HAL_STM32_RCC_APB1RSTR 0x20 +#define CYGHWR_HAL_STM32_RCC_APB2RSTR 0x24 +#define CYGHWR_HAL_STM32_RCC_AHB1ENR 0x30 +#define CYGHWR_HAL_STM32_RCC_AHB2ENR 0x34 +#define CYGHWR_HAL_STM32_RCC_AHB3ENR 0x38 +#define CYGHWR_HAL_STM32_RCC_APB1ENR 0x40 +#define CYGHWR_HAL_STM32_RCC_APB2ENR 0x44 +#define CYGHWR_HAL_STM32_RCC_AHB1LPENR 0x50 +#define CYGHWR_HAL_STM32_RCC_AHB2LPENR 0x54 +#define CYGHWR_HAL_STM32_RCC_AHB3LPENR 0x58 +#define CYGHWR_HAL_STM32_RCC_APB1LPENR 0x60 +#define CYGHWR_HAL_STM32_RCC_APB2LPENR 0x64 +#define CYGHWR_HAL_STM32_RCC_BDCR 0x70 +#define CYGHWR_HAL_STM32_RCC_CSR 0x74 +#endif + +#define CYGHWR_HAL_STM32_RCC_CR_HSION BIT_(0) +#define CYGHWR_HAL_STM32_RCC_CR_HSIRDY BIT_(1) +#define CYGHWR_HAL_STM32_RCC_CR_HSITRIM MASK_(3,5) +#define CYGHWR_HAL_STM32_RCC_CR_HSICAL MASK_(8,8) +#define CYGHWR_HAL_STM32_RCC_CR_HSEON BIT_(16) +#define CYGHWR_HAL_STM32_RCC_CR_HSERDY BIT_(17) +#define CYGHWR_HAL_STM32_RCC_CR_HSEBYP BIT_(18) +#define CYGHWR_HAL_STM32_RCC_CR_CSSON BIT_(19) +#define CYGHWR_HAL_STM32_RCC_CR_PLLON BIT_(24) +#define CYGHWR_HAL_STM32_RCC_CR_PLLRDY BIT_(25) +#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE) +#define CYGHWR_HAL_STM32_RCC_CR_PLLI2SON BIT_(26) +#define CYGHWR_HAL_STM32_RCC_CR_PLLI2SRDY BIT_(27) +#endif + +#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE) +#define CYGHWR_HAL_STM32_RCC_PLLCFGR_PLLM(__m) VALUE_(0,__m) +#define CYGHWR_HAL_STM32_RCC_PLLCFGR_PLLM_MASK MASK_(0,6) +#define CYGHWR_HAL_STM32_RCC_PLLCFGR_PLLN(__n) VALUE_(6,__n) +#define CYGHWR_HAL_STM32_RCC_PLLCFGR_PLLN_MASK MASK_(6,9) +#define CYGHWR_HAL_STM32_RCC_PLLCFGR_PLLP(__p) VALUE_(16,((__p)>>1)-1 ) +#define CYGHWR_HAL_STM32_RCC_PLLCFGR_PLLP_2 VALUE_(16,0) +#define CYGHWR_HAL_STM32_RCC_PLLCFGR_PLLP_4 VALUE_(16,1) +#define CYGHWR_HAL_STM32_RCC_PLLCFGR_PLLP_6 VALUE_(16,2) +#define CYGHWR_HAL_STM32_RCC_PLLCFGR_PLLP_8 VALUE_(16,3) +#define CYGHWR_HAL_STM32_RCC_PLLCFGR_PLLSRC_HSI VALUE_(22,0) +#define CYGHWR_HAL_STM32_RCC_PLLCFGR_PLLSRC_HSE VALUE_(22,1) +#define CYGHWR_HAL_STM32_RCC_PLLCFGR_PLLQ(__q) VALUE_(24,__q) +#define CYGHWR_HAL_STM32_RCC_PLLCFGR_PLLQ_MASK MASK_(24,4) +#endif + +#define CYGHWR_HAL_STM32_RCC_CFGR_SW_HSI VALUE_(0,0) +#define CYGHWR_HAL_STM32_RCC_CFGR_SW_HSE VALUE_(0,1) +#define CYGHWR_HAL_STM32_RCC_CFGR_SW_PLL VALUE_(0,2) +#define CYGHWR_HAL_STM32_RCC_CFGR_SW_XXX VALUE_(0,3) +#define CYGHWR_HAL_STM32_RCC_CFGR_SWS_HSI VALUE_(2,0) +#define CYGHWR_HAL_STM32_RCC_CFGR_SWS_HSE VALUE_(2,1) +#define CYGHWR_HAL_STM32_RCC_CFGR_SWS_PLL VALUE_(2,2) +#define CYGHWR_HAL_STM32_RCC_CFGR_SWS_XXX VALUE_(2,3) +#define CYGHWR_HAL_STM32_RCC_CFGR_HPRE_1 VALUE_(4,0) +#define CYGHWR_HAL_STM32_RCC_CFGR_HPRE_2 VALUE_(4,8) +#define CYGHWR_HAL_STM32_RCC_CFGR_HPRE_4 VALUE_(4,9) +#define CYGHWR_HAL_STM32_RCC_CFGR_HPRE_8 VALUE_(4,10) +#define CYGHWR_HAL_STM32_RCC_CFGR_HPRE_16 VALUE_(4,11) +#define CYGHWR_HAL_STM32_RCC_CFGR_HPRE_64 VALUE_(4,12) +#define CYGHWR_HAL_STM32_RCC_CFGR_HPRE_128 VALUE_(4,13) +#define CYGHWR_HAL_STM32_RCC_CFGR_HPRE_256 VALUE_(4,14) +#define CYGHWR_HAL_STM32_RCC_CFGR_HPRE_512 VALUE_(4,15) +#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1) +#define CYGHWR_HAL_STM32_RCC_CFGR_PPRE1_1 VALUE_(8,0) +#define CYGHWR_HAL_STM32_RCC_CFGR_PPRE1_2 VALUE_(8,4) +#define CYGHWR_HAL_STM32_RCC_CFGR_PPRE1_4 VALUE_(8,5) +#define CYGHWR_HAL_STM32_RCC_CFGR_PPRE1_8 VALUE_(8,6) +#define CYGHWR_HAL_STM32_RCC_CFGR_PPRE1_16 VALUE_(8,7) +#define CYGHWR_HAL_STM32_RCC_CFGR_PPRE2_1 VALUE_(11,0) +#define CYGHWR_HAL_STM32_RCC_CFGR_PPRE2_2 VALUE_(11,4) +#define CYGHWR_HAL_STM32_RCC_CFGR_PPRE2_4 VALUE_(11,5) +#define CYGHWR_HAL_STM32_RCC_CFGR_PPRE2_8 VALUE_(11,6) +#define CYGHWR_HAL_STM32_RCC_CFGR_PPRE2_16 VALUE_(11,7) +#define CYGHWR_HAL_STM32_RCC_CFGR_ADCPRE_2 VALUE_(14,0) +#define CYGHWR_HAL_STM32_RCC_CFGR_ADCPRE_4 VALUE_(14,1) +#define CYGHWR_HAL_STM32_RCC_CFGR_ADCPRE_6 VALUE_(14,2) +#define CYGHWR_HAL_STM32_RCC_CFGR_ADCPRE_8 VALUE_(14,3) +#define CYGHWR_HAL_STM32_RCC_CFGR_ADCPRE_XXX VALUE_(14,3) +#define CYGHWR_HAL_STM32_RCC_CFGR_PLLSRC_HSI 0 +#define CYGHWR_HAL_STM32_RCC_CFGR_PLLSRC_HSE BIT_(16) +#define CYGHWR_HAL_STM32_RCC_CFGR_PLLSRC_PREDIV1 BIT_(16) +#define CYGHWR_HAL_STM32_RCC_CFGR_PLLXTPRE BIT_(17) +#define CYGHWR_HAL_STM32_RCC_CFGR_PLLMUL(__x) VALUE_(18,(__x)-2) +#define CYGHWR_HAL_STM32_RCC_CFGR_USBPRE BIT_(22) +#define CYGHWR_HAL_STM32_RCC_CFGR_MCO_NONE VALUE_(24,0) +#define CYGHWR_HAL_STM32_RCC_CFGR_MCO_SYSCLK VALUE_(24,4) +#define CYGHWR_HAL_STM32_RCC_CFGR_MCO_HSI VALUE_(24,5) +#define CYGHWR_HAL_STM32_RCC_CFGR_MCO_HSE VALUE_(24,6) +#define CYGHWR_HAL_STM32_RCC_CFGR_MCO_PLL VALUE_(24,7) +# ifdef CYGHWR_HAL_CORTEXM_STM32_CONNECTIVITY +#define CYGHWR_HAL_STM32_RCC_CFGR_MCO_PLL2 VALUE_(24,8) +#define CYGHWR_HAL_STM32_RCC_CFGR_MCO_PLL3_HALF VALUE_(24,9) +#define CYGHWR_HAL_STM32_RCC_CFGR_MCO_XT1 VALUE_(24,10) +#define CYGHWR_HAL_STM32_RCC_CFGR_MCO_PLL3 VALUE_(24,11) +#define CYGHWR_HAL_STM32_RCC_CR_PLL2ON BIT_(26) +#define CYGHWR_HAL_STM32_RCC_CR_PLL2RDY BIT_(27) +# endif +#elif defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE) +#define CYGHWR_HAL_STM32_RCC_CFGR_PPRE1_1 VALUE_(10,0) +#define CYGHWR_HAL_STM32_RCC_CFGR_PPRE1_2 VALUE_(10,4) +#define CYGHWR_HAL_STM32_RCC_CFGR_PPRE1_4 VALUE_(10,5) +#define CYGHWR_HAL_STM32_RCC_CFGR_PPRE1_8 VALUE_(10,6) +#define CYGHWR_HAL_STM32_RCC_CFGR_PPRE1_16 VALUE_(10,7) +#define CYGHWR_HAL_STM32_RCC_CFGR_PPRE2_1 VALUE_(13,0) +#define CYGHWR_HAL_STM32_RCC_CFGR_PPRE2_2 VALUE_(13,4) +#define CYGHWR_HAL_STM32_RCC_CFGR_PPRE2_4 VALUE_(13,5) +#define CYGHWR_HAL_STM32_RCC_CFGR_PPRE2_8 VALUE_(13,6) +#define CYGHWR_HAL_STM32_RCC_CFGR_PPRE2_16 VALUE_(13,7) +#define CYGHWR_HAL_STM32_RCC_CFGR_RTCPRE(__x) VALUE_(16,__x) +#define CYGHWR_HAL_STM32_RCC_CFGR_RTCPRE_MASK MASK_(16,5) +#define CYGHWR_HAL_STM32_RCC_CFGR_MCO1_MASK MASK_(21,2) +#define CYGHWR_HAL_STM32_RCC_CFGR_MCO1_HSI VALUE_(21,0) +#define CYGHWR_HAL_STM32_RCC_CFGR_MCO1_LSE VALUE_(21,1) +#define CYGHWR_HAL_STM32_RCC_CFGR_MCO1_HSE VALUE_(21,2) +#define CYGHWR_HAL_STM32_RCC_CFGR_MCO1_PLL VALUE_(21,3) +#define CYGHWR_HAL_STM32_RCC_CFGR_I2SSRC_PLLI2S VALUE_(23,0) +#define CYGHWR_HAL_STM32_RCC_CFGR_I2SSRC_EXT VALUE_(23,1) +#define CYGHWR_HAL_STM32_RCC_CFGR_MCO1PRE_MASK MASK_(24,3) +#define CYGHWR_HAL_STM32_RCC_CFGR_MCO1PRE_1 VALUE_(24,0) +#define CYGHWR_HAL_STM32_RCC_CFGR_MCO1PRE_2 VALUE_(24,4) +#define CYGHWR_HAL_STM32_RCC_CFGR_MCO1PRE_3 VALUE_(24,5) +#define CYGHWR_HAL_STM32_RCC_CFGR_MCO1PRE_4 VALUE_(24,6) +#define CYGHWR_HAL_STM32_RCC_CFGR_MCO1PRE_5 VALUE_(24,7) +#define CYGHWR_HAL_STM32_RCC_CFGR_MCO2PRE_MASK MASK_(27,3) +#define CYGHWR_HAL_STM32_RCC_CFGR_MCO2PRE_1 VALUE_(27,0) +#define CYGHWR_HAL_STM32_RCC_CFGR_MCO2PRE_2 VALUE_(27,4) +#define CYGHWR_HAL_STM32_RCC_CFGR_MCO2PRE_3 VALUE_(27,5) +#define CYGHWR_HAL_STM32_RCC_CFGR_MCO2PRE_4 VALUE_(27,6) +#define CYGHWR_HAL_STM32_RCC_CFGR_MCO2PRE_5 VALUE_(27,7) +#define CYGHWR_HAL_STM32_RCC_CFGR_MCO2_MASK MASK_(30,2) +#define CYGHWR_HAL_STM32_RCC_CFGR_MCO2_SYSCLK VALUE_(30,0) +#define CYGHWR_HAL_STM32_RCC_CFGR_MCO2_PLLI2S VALUE_(30,1) +#define CYGHWR_HAL_STM32_RCC_CFGR_MCO2_HSE VALUE_(30,2) +#define CYGHWR_HAL_STM32_RCC_CFGR_MCO2_PLL VALUE_(30,3) +#endif + +#define CYGHWR_HAL_STM32_RCC_AHBENR_DMA1 (0) +#define CYGHWR_HAL_STM32_RCC_AHBENR_DMA2 (1) +#define CYGHWR_HAL_STM32_RCC_AHBENR_SRAM (2) +#define CYGHWR_HAL_STM32_RCC_AHBENR_FLITF (4) +#define CYGHWR_HAL_STM32_RCC_AHBENR_CRC (6) +#define CYGHWR_HAL_STM32_RCC_AHBENR_FSMC (8) +#define CYGHWR_HAL_STM32_RCC_AHBENR_SDIO (10) +#ifdef CYGHWR_HAL_CORTEXM_STM32_CONNECTIVITY +#define CYGHWR_HAL_STM32_RCC_AHBENR_OTGFS (12) +#define CYGHWR_HAL_STM32_RCC_AHBENR_ETHMAC (14) +#define CYGHWR_HAL_STM32_RCC_AHBENR_ETHMACTX (15) +#define CYGHWR_HAL_STM32_RCC_AHBENR_ETHMACRX (16) + +#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1) +#define CYGHWR_HAL_STM32_RCC_AHBRSTR_OTGFSRST BIT_(12) +#define CYGHWR_HAL_STM32_RCC_AHBRSTR_ETHMACRST BIT_(14) +#elif defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE) +#define CYGHWR_HAL_STM32_RCC_AHB1RSTR_ETHMACRST BIT_(25) +#endif +#endif + +// Note that the following are bit numbers, not masks. They should +// either be used with the CYGHWR_HAL_STM32_CLOCK() macro or used to +// shift a 1, perhaps using the BIT_() macro. +// +// Note that in the F2/F4 families, the bit positions in the LP registers are +// the same. + +#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1) + +#define CYGHWR_HAL_STM32_RCC_APB2ENR_AFIO (0) +#define CYGHWR_HAL_STM32_RCC_APB2ENR_IOPA (2) +#define CYGHWR_HAL_STM32_RCC_APB2ENR_IOPB (3) +#define CYGHWR_HAL_STM32_RCC_APB2ENR_IOPC (4) +#define CYGHWR_HAL_STM32_RCC_APB2ENR_IOPD (5) +#define CYGHWR_HAL_STM32_RCC_APB2ENR_IOPE (6) +#define CYGHWR_HAL_STM32_RCC_APB2ENR_IOPF (7) +#define CYGHWR_HAL_STM32_RCC_APB2ENR_IOPG (8) +#define CYGHWR_HAL_STM32_RCC_APB2ENR_ADC1 (9) +#define CYGHWR_HAL_STM32_RCC_APB2ENR_ADC2 (10) +#define CYGHWR_HAL_STM32_RCC_APB2ENR_TIM1 (11) +#define CYGHWR_HAL_STM32_RCC_APB2ENR_SPI1 (12) +#define CYGHWR_HAL_STM32_RCC_APB2ENR_TIM8 (13) +#define CYGHWR_HAL_STM32_RCC_APB2ENR_UART1 (14) +#define CYGHWR_HAL_STM32_RCC_APB2ENR_ADC3 (15) + + +#define CYGHWR_HAL_STM32_RCC_APB1ENR_TIM2 (0) +#define CYGHWR_HAL_STM32_RCC_APB1ENR_TIM3 (1) +#define CYGHWR_HAL_STM32_RCC_APB1ENR_TIM4 (2) +#define CYGHWR_HAL_STM32_RCC_APB1ENR_TIM5 (3) +#define CYGHWR_HAL_STM32_RCC_APB1ENR_TIM6 (4) +#define CYGHWR_HAL_STM32_RCC_APB1ENR_TIM7 (5) +#define CYGHWR_HAL_STM32_RCC_APB1ENR_WWDG (11) +#define CYGHWR_HAL_STM32_RCC_APB1ENR_SPI2 (14) +#define CYGHWR_HAL_STM32_RCC_APB1ENR_SPI3 (15) +#define CYGHWR_HAL_STM32_RCC_APB1ENR_UART2 (17) +#define CYGHWR_HAL_STM32_RCC_APB1ENR_UART3 (18) +#define CYGHWR_HAL_STM32_RCC_APB1ENR_UART4 (19) +#define CYGHWR_HAL_STM32_RCC_APB1ENR_UART5 (20) +#define CYGHWR_HAL_STM32_RCC_APB1ENR_I2C1 (21) +#define CYGHWR_HAL_STM32_RCC_APB1ENR_I2C2 (22) +#define CYGHWR_HAL_STM32_RCC_APB1ENR_USB (23) +#define CYGHWR_HAL_STM32_RCC_APB1ENR_CAN1 (25) +#ifdef CYGHWR_HAL_CORTEXM_STM32_CONNECTIVITY +#define CYGHWR_HAL_STM32_RCC_APB1ENR_CAN2 (26) +#endif +#define CYGHWR_HAL_STM32_RCC_APB1ENR_BKP (27) +#define CYGHWR_HAL_STM32_RCC_APB1ENR_PWR (28) +#define CYGHWR_HAL_STM32_RCC_APB1ENR_DAC (29) + +#ifdef CYGHWR_HAL_CORTEXM_STM32_CONNECTIVITY +#define CYGHWR_HAL_STM32_RCC_CFGR2_PREDIV1(__x) VALUE_(0,__x) +#define CYGHWR_HAL_STM32_RCC_CFGR2_PREDIV2(__x) VALUE_(4,__x) +#define CYGHWR_HAL_STM32_RCC_CFGR2_PLL2MUL(__x) VALUE_(8,__x) +#define CYGHWR_HAL_STM32_RCC_CFGR2_PLL3MUL(__x) VALUE_(12,__x) +#define CYGHWR_HAL_STM32_RCC_CFGR2_PREDIV1SRC_HSE 0 +#define CYGHWR_HAL_STM32_RCC_CFGR2_PREDIV1SRC_PLL2 BIT_(16) +#define CYGHWR_HAL_STM32_RCC_CFGR2_I2S2SRC_SYSCLK 0 +#define CYGHWR_HAL_STM32_RCC_CFGR2_I2S2SRC_PLL3 BIT_(17) +#define CYGHWR_HAL_STM32_RCC_CFGR2_I2S3SRC_SYSCLK 0 +#define CYGHWR_HAL_STM32_RCC_CFGR2_I2S3SRC_PLL3 BIT_(18) +#endif + +#elif defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE) + +#define CYGHWR_HAL_STM32_RCC_AHB1ENR_GPIOA (0) +#define CYGHWR_HAL_STM32_RCC_AHB1ENR_GPIOB (1) +#define CYGHWR_HAL_STM32_RCC_AHB1ENR_GPIOC (2) +#define CYGHWR_HAL_STM32_RCC_AHB1ENR_GPIOD (3) +#define CYGHWR_HAL_STM32_RCC_AHB1ENR_GPIOE (4) +#define CYGHWR_HAL_STM32_RCC_AHB1ENR_GPIOF (5) +#define CYGHWR_HAL_STM32_RCC_AHB1ENR_GPIOG (6) +#define CYGHWR_HAL_STM32_RCC_AHB1ENR_GPIOH (7) +#define CYGHWR_HAL_STM32_RCC_AHB1ENR_GPIOI (8) +#define CYGHWR_HAL_STM32_RCC_AHB1ENR_CRC (12) +#define CYGHWR_HAL_STM32_RCC_AHB1ENR_BKPSRAM (18) +#if defined(CYGHWR_HAL_CORTEXM_STM32_FAMILY_F4) +#define CYGHWR_HAL_STM32_RCC_AHB1ENR_CCMDATARAMEN (20) +#endif // CYGHWR_HAL_CORTEXM_STM32_FAMILY_F4 +#define CYGHWR_HAL_STM32_RCC_AHB1ENR_DMA1 (21) +#define CYGHWR_HAL_STM32_RCC_AHB1ENR_DMA2 (22) +#define CYGHWR_HAL_STM32_RCC_AHB1ENR_ETHMAC (25) +#define CYGHWR_HAL_STM32_RCC_AHB1ENR_ETHMACTX (26) +#define CYGHWR_HAL_STM32_RCC_AHB1ENR_ETHMACRX (27) +#define CYGHWR_HAL_STM32_RCC_AHB1ENR_ETHMACPTP (28) +#define CYGHWR_HAL_STM32_RCC_AHB1ENR_OTGHS (29) +#define CYGHWR_HAL_STM32_RCC_AHB1ENR_OTGHSULPI (30) + +#define CYGHWR_HAL_STM32_RCC_AHB2ENR_DCMI (0) +#define CYGHWR_HAL_STM32_RCC_AHB2ENR_CRYP (4) +#define CYGHWR_HAL_STM32_RCC_AHB2ENR_HASH (5) +#define CYGHWR_HAL_STM32_RCC_AHB2ENR_RNG (6) +#define CYGHWR_HAL_STM32_RCC_AHB2ENR_OTGFS (7) + +#define CYGHWR_HAL_STM32_RCC_AHB3ENR_FSMC (0) + +#define CYGHWR_HAL_STM32_RCC_APB1ENR_TIM2 (0) +#define CYGHWR_HAL_STM32_RCC_APB1ENR_TIM3 (1) +#define CYGHWR_HAL_STM32_RCC_APB1ENR_TIM4 (2) +#define CYGHWR_HAL_STM32_RCC_APB1ENR_TIM5 (3) +#define CYGHWR_HAL_STM32_RCC_APB1ENR_TIM6 (4) +#define CYGHWR_HAL_STM32_RCC_APB1ENR_TIM7 (5) +#define CYGHWR_HAL_STM32_RCC_APB1ENR_TIM12 (6) +#define CYGHWR_HAL_STM32_RCC_APB1ENR_TIM13 (7) +#define CYGHWR_HAL_STM32_RCC_APB1ENR_TIM14 (8) +#define CYGHWR_HAL_STM32_RCC_APB1ENR_WWDG (11) +#define CYGHWR_HAL_STM32_RCC_APB1ENR_SPI2 (14) +#define CYGHWR_HAL_STM32_RCC_APB1ENR_SPI3 (15) +#define CYGHWR_HAL_STM32_RCC_APB1ENR_UART2 (17) +#define CYGHWR_HAL_STM32_RCC_APB1ENR_UART3 (18) +#define CYGHWR_HAL_STM32_RCC_APB1ENR_UART4 (19) +#define CYGHWR_HAL_STM32_RCC_APB1ENR_UART5 (20) +#define CYGHWR_HAL_STM32_RCC_APB1ENR_I2C1 (21) +#define CYGHWR_HAL_STM32_RCC_APB1ENR_I2C2 (22) +#define CYGHWR_HAL_STM32_RCC_APB1ENR_I2C3 (23) +#define CYGHWR_HAL_STM32_RCC_APB1ENR_CAN1 (25) +#define CYGHWR_HAL_STM32_RCC_APB1ENR_CAN2 (26) +#define CYGHWR_HAL_STM32_RCC_APB1ENR_PWR (28) +#define CYGHWR_HAL_STM32_RCC_APB1ENR_DAC (29) + +#define CYGHWR_HAL_STM32_RCC_APB2ENR_TIM1 (0) +#define CYGHWR_HAL_STM32_RCC_APB2ENR_TIM8 (1) +#define CYGHWR_HAL_STM32_RCC_APB2ENR_UART1 (4) +#define CYGHWR_HAL_STM32_RCC_APB2ENR_UART6 (5) +#define CYGHWR_HAL_STM32_RCC_APB2ENR_ADC1 (8) +#define CYGHWR_HAL_STM32_RCC_APB2ENR_ADC2 (9) +#define CYGHWR_HAL_STM32_RCC_APB2ENR_ADC3 (10) +#define CYGHWR_HAL_STM32_RCC_APB2ENR_SDIO (11) +#define CYGHWR_HAL_STM32_RCC_APB2ENR_SPI1 (12) +#define CYGHWR_HAL_STM32_RCC_APB2ENR_SYSCFG (14) +#define CYGHWR_HAL_STM32_RCC_APB2ENR_TIM9 (16) +#define CYGHWR_HAL_STM32_RCC_APB2ENR_TIM10 (17) +#define CYGHWR_HAL_STM32_RCC_APB2ENR_TIM11 (18) + +#endif + +// The following encodes the control register and clock bit number +// into a 32 bit descriptor. +#define CYGHWR_HAL_STM32_CLOCK( __reg, __pin ) \ + ((CYGHWR_HAL_STM32_RCC_##__reg##ENR) | \ + ((CYGHWR_HAL_STM32_RCC_##__reg##ENR_##__pin)<<16)) + +// Macros to extract encoded values. +#define CYGHWR_HAL_STM32_CLOCK_REG( __desc ) ((__desc)&0xFF) +#define CYGHWR_HAL_STM32_CLOCK_PIN( __desc ) (((__desc)>>16)&0xFF) + +// Functions and macros to enable/disable clocks. + +__externC void hal_stm32_clock_enable( cyg_uint32 desc ); +__externC void hal_stm32_clock_disable( cyg_uint32 desc ); + +#define CYGHWR_HAL_STM32_CLOCK_ENABLE( __desc ) hal_stm32_clock_enable( __desc ) +#define CYGHWR_HAL_STM32_CLOCK_DISABLE( __desc ) hal_stm32_clock_disable( __desc ) + + +#define CYGHWR_HAL_STM32_RCC_BDCR_LSEON BIT_(0) +#define CYGHWR_HAL_STM32_RCC_BDCR_LSERDY BIT_(1) +#define CYGHWR_HAL_STM32_RCC_BDCR_LSEBYP BIT_(2) +#define CYGHWR_HAL_STM32_RCC_BDCR_RTCSEL_NO VALUE_(8,0) +#define CYGHWR_HAL_STM32_RCC_BDCR_RTCSEL_LSE VALUE_(8,1) +#define CYGHWR_HAL_STM32_RCC_BDCR_RTCSEL_LSI VALUE_(8,2) +#define CYGHWR_HAL_STM32_RCC_BDCR_RTCSEL_HSE VALUE_(8,3) +#define CYGHWR_HAL_STM32_RCC_BDCR_RTCSEL_XXX VALUE_(8,3) +#define CYGHWR_HAL_STM32_RCC_BDCR_RTCEN BIT_(15) +#define CYGHWR_HAL_STM32_RCC_BDCR_BDRST BIT_(16) + +#define CYGHWR_HAL_STM32_RCC_CSR_LSION BIT_(0) +#define CYGHWR_HAL_STM32_RCC_CSR_LSIRDY BIT_(1) +#define CYGHWR_HAL_STM32_RCC_CSR_RMVF BIT_(24) +#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE) +#define CYGHWR_HAL_STM32_RCC_CSR_BORRSTF BIT_(25) +#endif +#define CYGHWR_HAL_STM32_RCC_CSR_PINRSTF BIT_(26) +#define CYGHWR_HAL_STM32_RCC_CSR_PORRSTF BIT_(27) +#define CYGHWR_HAL_STM32_RCC_CSR_SFTRSTF BIT_(28) +#define CYGHWR_HAL_STM32_RCC_CSR_IWDGRSTF BIT_(29) +#define CYGHWR_HAL_STM32_RCC_CSR_WWDGRSTF BIT_(30) +#define CYGHWR_HAL_STM32_RCC_CSR_LPWRRSTF BIT_(31) + + +// Miscellaneous clock control bits + +#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1) +#define CYGHWR_HAL_STM32_CLOCK_BKP CYGHWR_HAL_STM32_CLOCK( APB1, BKP ) +#endif + +#define CYGHWR_HAL_STM32_CLOCK_PWR CYGHWR_HAL_STM32_CLOCK( APB1, PWR ) + +//============================================================================= +// Realtime Clock + +#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1) +#define CYGHWR_HAL_STM32_RTC_CRH 0x00 +#define CYGHWR_HAL_STM32_RTC_CRL 0x04 +#define CYGHWR_HAL_STM32_RTC_PRLH 0x08 +#define CYGHWR_HAL_STM32_RTC_PRLL 0x0C +#define CYGHWR_HAL_STM32_RTC_DIVH 0x10 +#define CYGHWR_HAL_STM32_RTC_DIVL 0x14 +#define CYGHWR_HAL_STM32_RTC_CNTH 0x18 +#define CYGHWR_HAL_STM32_RTC_CNTL 0x1C +#define CYGHWR_HAL_STM32_RTC_ALRH 0x20 +#define CYGHWR_HAL_STM32_RTC_ALRL 0x24 + +// CRH fields + +#define CYGHWR_HAL_STM32_RTC_CRH_SECIE BIT_(0) +#define CYGHWR_HAL_STM32_RTC_CRH_ALRIE BIT_(1) +#define CYGHWR_HAL_STM32_RTC_CRH_OWIE BIT_(2) + +// CRL fields + +#define CYGHWR_HAL_STM32_RTC_CRL_SECF BIT_(0) +#define CYGHWR_HAL_STM32_RTC_CRL_ALRF BIT_(1) +#define CYGHWR_HAL_STM32_RTC_CRL_OWF BIT_(2) +#define CYGHWR_HAL_STM32_RTC_CRL_RSF BIT_(3) +#define CYGHWR_HAL_STM32_RTC_CRL_CNF BIT_(4) +#define CYGHWR_HAL_STM32_RTC_CRL_RTOFF BIT_(5) + +#elif defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE) + +#define CYGHWR_HAL_STM32_RTC_TR 0x00 +#define CYGHWR_HAL_STM32_RTC_DR 0x04 +#define CYGHWR_HAL_STM32_RTC_CR 0x08 +#define CYGHWR_HAL_STM32_RTC_ISR 0x0C +#define CYGHWR_HAL_STM32_RTC_PRER 0x10 +#define CYGHWR_HAL_STM32_RTC_WUTR 0x14 +#define CYGHWR_HAL_STM32_RTC_CALIBR 0x18 +#define CYGHWR_HAL_STM32_RTC_ALRMAR 0x1C +#define CYGHWR_HAL_STM32_RTC_ALRMBR 0x20 +#define CYGHWR_HAL_STM32_RTC_WPR 0x24 +#define CYGHWR_HAL_STM32_RTC_TSTR 0x30 +#define CYGHWR_HAL_STM32_RTC_TSDR 0x34 +#define CYGHWR_HAL_STM32_RTC_TAFCR 0x40 +#define CYGHWR_HAL_STM32_RTC_BKxR(_x) (0x50 + 4*(_x)) + +#define CYGHWR_HAL_STM32_RTC_TR_SU MASK_(0,4) +#define CYGHWR_HAL_STM32_RTC_TR_SU_SHIFT 0 +#define CYGHWR_HAL_STM32_RTC_TR_ST MASK_(4,3) +#define CYGHWR_HAL_STM32_RTC_TR_ST_SHIFT 4 +#define CYGHWR_HAL_STM32_RTC_TR_MNU MASK_(8,4) +#define CYGHWR_HAL_STM32_RTC_TR_MNU_SHIFT 8 +#define CYGHWR_HAL_STM32_RTC_TR_MNT MASK_(12,3) +#define CYGHWR_HAL_STM32_RTC_TR_MNT_SHIFT 12 +#define CYGHWR_HAL_STM32_RTC_TR_HU MASK_(16,4) +#define CYGHWR_HAL_STM32_RTC_TR_HU_SHIFT 16 +#define CYGHWR_HAL_STM32_RTC_TR_HT MASK_(20,2) +#define CYGHWR_HAL_STM32_RTC_TR_HT_SHIFT 20 +#define CYGHWR_HAL_STM32_RTC_TR_AM VALUE_(22, 0) +#define CYGHWR_HAL_STM32_RTC_TR_PM VALUE_(22, 1) + +#define CYGHWR_HAL_STM32_RTC_DR_DU MASK_(0,4) +#define CYGHWR_HAL_STM32_RTC_DR_DU_SHIFT 0 +#define CYGHWR_HAL_STM32_RTC_DR_DT MASK_(4,2) +#define CYGHWR_HAL_STM32_RTC_DR_DT_SHIFT 4 +#define CYGHWR_HAL_STM32_RTC_DR_MU MASK_(8,4) +#define CYGHWR_HAL_STM32_RTC_DR_MU_SHIFT 8 +#define CYGHWR_HAL_STM32_RTC_DR_MT BIT_(12) +#define CYGHWR_HAL_STM32_RTC_DR_MT_SHIFT 12 +#define CYGHWR_HAL_STM32_RTC_DR_WDU_MON VALUE_(13,1) +#define CYGHWR_HAL_STM32_RTC_DR_WDU_TUE VALUE_(13,2) +#define CYGHWR_HAL_STM32_RTC_DR_WDU_WED VALUE_(13,3) +#define CYGHWR_HAL_STM32_RTC_DR_WDU_THU VALUE_(13,4) +#define CYGHWR_HAL_STM32_RTC_DR_WDU_FRI VALUE_(13,5) +#define CYGHWR_HAL_STM32_RTC_DR_WDU_SAT VALUE_(13,6) +#define CYGHWR_HAL_STM32_RTC_DR_WDU_SUN VALUE_(13,7) +#define CYGHWR_HAL_STM32_RTC_DR_YU MASK_(16,4) +#define CYGHWR_HAL_STM32_RTC_DR_YU_SHIFT 16 +#define CYGHWR_HAL_STM32_RTC_DR_YT MASK_(20,4) +#define CYGHWR_HAL_STM32_RTC_DR_YT_SHIFT 20 + +#define CYGHWR_HAL_STM32_RTC_CR_WUCKSEL_16 VALUE_(0,0) +#define CYGHWR_HAL_STM32_RTC_CR_WUCKSEL_8 VALUE_(0,1) +#define CYGHWR_HAL_STM32_RTC_CR_WUCKSEL_4 VALUE_(0,2) +#define CYGHWR_HAL_STM32_RTC_CR_WUCKSEL_2 VALUE_(0,3) +#define CYGHWR_HAL_STM32_RTC_CR_WUCKSEL_CK_SPRE VALUE_(0,4) +#define CYGHWR_HAL_STM32_RTC_CR_WUCKSEL_CK_SPRE_PLUS_216 VALUE_(0,6) +#define CYGHWR_HAL_STM32_RTC_CR_TSEDGE BIT_(3) +#define CYGHWR_HAL_STM32_RTC_CR_REFCKON BIT_(4) +#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F4) +#define CYGHWR_HAL_STM32_RTC_CR_BYPSHAD BIT_(5) +#endif // CYGHWR_HAL_CORTEXM_STM32_FAMILY_F4 +#define CYGHWR_HAL_STM32_RTC_CR_FMT BIT_(6) +#define CYGHWR_HAL_STM32_RTC_CR_DCE BIT_(7) +#define CYGHWR_HAL_STM32_RTC_CR_ALRAE BIT_(8) +#define CYGHWR_HAL_STM32_RTC_CR_ALRBE BIT_(9) +#define CYGHWR_HAL_STM32_RTC_CR_WUTE BIT_(10) +#define CYGHWR_HAL_STM32_RTC_CR_TSE BIT_(11) +#define CYGHWR_HAL_STM32_RTC_CR_ALRAIE BIT_(12) +#define CYGHWR_HAL_STM32_RTC_CR_ALRBIE BIT_(13) +#define CYGHWR_HAL_STM32_RTC_CR_WUTIE BIT_(14) +#define CYGHWR_HAL_STM32_RTC_CR_TSIE BIT_(15) +#define CYGHWR_HAL_STM32_RTC_CR_ADD1H BIT_(16) +#define CYGHWR_HAL_STM32_RTC_CR_SUB1H BIT_(17) +#define CYGHWR_HAL_STM32_RTC_CR_BKP BIT_(18) +#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F4) +#define CYGHWR_HAL_STM32_RTC_CR_COSEL BIT_(19) +#endif // CYGHWR_HAL_CORTEXM_STM32_FAMILY_F4 +#define CYGHWR_HAL_STM32_RTC_CR_POL BIT_(20) +#define CYGHWR_HAL_STM32_RTC_CR_OSEL_DISABLE VALUE_(21, 0) +#define CYGHWR_HAL_STM32_RTC_CR_OSEL_ALRAOE VALUE_(21, 1) +#define CYGHWR_HAL_STM32_RTC_CR_OSEL_ALRBOE VALUE_(21, 2) +#define CYGHWR_HAL_STM32_RTC_CR_OSEL_WUOE VALUE_(21, 3) +#define CYGHWR_HAL_STM32_RTC_CR_OSEL_COE BIT_(23) + +#define CYGHWR_HAL_STM32_RTC_ISR_ALRAWF BIT_(0) +#define CYGHWR_HAL_STM32_RTC_ISR_ALRBWF BIT_(1) +#define CYGHWR_HAL_STM32_RTC_ISR_WUTWF BIT_(2) +#define CYGHWR_HAL_STM32_RTC_ISR_INITS BIT_(4) +#define CYGHWR_HAL_STM32_RTC_ISR_RSF BIT_(5) +#define CYGHWR_HAL_STM32_RTC_ISR_INITF BIT_(6) +#define CYGHWR_HAL_STM32_RTC_ISR_INIT BIT_(7) +#define CYGHWR_HAL_STM32_RTC_ISR_ALRAF BIT_(8) +#define CYGHWR_HAL_STM32_RTC_ISR_ALRBF BIT_(9) +#define CYGHWR_HAL_STM32_RTC_ISR_WUTF BIT_(10) +#define CYGHWR_HAL_STM32_RTC_ISR_TSF BIT_(11) +#define CYGHWR_HAL_STM32_RTC_ISR_TSOVF BIT_(12) +#define CYGHWR_HAL_STM32_RTC_ISR_TAMP1F BIT_(13) + +#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F2) +#define CYGHWR_HAL_STM32_RTC_PRER_PREDIV_S MASK_(0,13) +#elif defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F4) +#define CYGHWR_HAL_STM32_RTC_ISR_SHPF BIT_(3) +#define CYGHWR_HAL_STM32_RTC_ISR_TAMP2F BIT_(14) +#define CYGHWR_HAL_STM32_RTC_ISR_RECALPF BIT_(16) +#define CYGHWR_HAL_STM32_RTC_PRER_PREDIV_S MASK_(0,15) +#endif +#define CYGHWR_HAL_STM32_RTC_PRER_PREDIV_A MASK_(16,7) + +// RTC_WUTR defines omitted +// RTC_CALIBR defines omitted +// RTC_ALRMAR defines omitted +// RTC_ALRMBR defines omitted + +#define CYGHWR_HAL_STM32_RTC_WPR_KEY MASK_(0,8) +#define CYGHWR_HAL_STM32_RTC_WPR_KEY1 0xCA +#define CYGHWR_HAL_STM32_RTC_WPR_KEY2 0x53 + +// RTC_TSTR defines omitted, but layout identical to RTC_TR +// RTC_TSDR defines omitted, but layout identical to RTC_DR except for omission of year fields +// RTC_TAFCR defines omitted +// No relevant RTC_BKPxR defines. + +// RCC clock is selected within wallclock driver, so no define here. + +#endif // elif defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE) + + +//============================================================================= +// System configuration controller - F2 and F4 only + +#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE) +// Register offsets +#define CYGHWR_HAL_STM32_SYSCFG_MEMRMP 0x00 +#define CYGHWR_HAL_STM32_SYSCFG_PMC 0x04 +#define CYGHWR_HAL_STM32_SYSCFG_EXTICR1 0x08 +#define CYGHWR_HAL_STM32_SYSCFG_EXTICR2 0x0C +#define CYGHWR_HAL_STM32_SYSCFG_EXTICR3 0x10 +#define CYGHWR_HAL_STM32_SYSCFG_EXTICR4 0x14 +#define CYGHWR_HAL_STM32_SYSCFG_CMPCR 0x20 + +// Register definitions + +#define CYGHWR_HAL_STM32_SYSCFG_MEMRMP_MAINFLASH VALUE_(0,0) +#define CYGHWR_HAL_STM32_SYSCFG_MEMRMP_SYSFLASH VALUE_(0,1) +#define CYGHWR_HAL_STM32_SYSCFG_MEMRMP_FSMC1 VALUE_(0,2) +#define CYGHWR_HAL_STM32_SYSCFG_MEMRMP_SRAM VALUE_(0,3) + +#define CYGHWR_HAL_STM32_SYSCFG_PMC_MII VALUE_(23,0) +#define CYGHWR_HAL_STM32_SYSCFG_PMC_RMII VALUE_(23,1) + +// FIXME: The below EXTI bits should be merged with the F1 defines in +// var_io_pins.h to provide a common interface + +// The following macro allows the four EXTICR registers to be indexed +// as CYGHWR_HAL_STM32_SYSCFG_EXTICR(1) to CYGHWR_HAL_STM32_SYSCFG_EXTICR(4) +#define CYGHWR_HAL_STM32_SYSCFG_EXTICR(__x) (4*((__x)-1)+0x08) + +// The following macros are used to generate the bitfields for setting up +// external interrupts. For example, CYGHWR_HAL_STM32_SYSCFG_EXTICRX_PORTC(12) +// will generate the bitfield which when ORed into the EXTICR4 register will +// set up C12 as the external interrupt pin for the EXTI12 interrupt. +#define CYGHWR_HAL_STM32_SYSCFG_EXTICRX_PORTA(__x) VALUE_(4*((__x)&3),0) +#define CYGHWR_HAL_STM32_SYSCFG_EXTICRX_PORTB(__x) VALUE_(4*((__x)&3),1) +#define CYGHWR_HAL_STM32_SYSCFG_EXTICRX_PORTC(__x) VALUE_(4*((__x)&3),2) +#define CYGHWR_HAL_STM32_SYSCFG_EXTICRX_PORTD(__x) VALUE_(4*((__x)&3),3) +#define CYGHWR_HAL_STM32_SYSCFG_EXTICRX_PORTE(__x) VALUE_(4*((__x)&3),4) +#define CYGHWR_HAL_STM32_SYSCFG_EXTICRX_PORTF(__x) VALUE_(4*((__x)&3),5) +#define CYGHWR_HAL_STM32_SYSCFG_EXTICRX_PORTG(__x) VALUE_(4*((__x)&3),6) +#define CYGHWR_HAL_STM32_SYSCFG_EXTICRX_PORTH(__x) VALUE_(4*((__x)&3),7) +#define CYGHWR_HAL_STM32_SYSCFG_EXTICRX_MASK(__x) VALUE_(4*((__x)&3),0xF) + +#define CYGHWR_HAL_STM32_SYSCFG_CMPCR_CMP_DIS VALUE_(0,0) +#define CYGHWR_HAL_STM32_SYSCFG_CMPCR_CMP_ENA VALUE_(0,1) +#define CYGHWR_HAL_STM32_SYSCFG_CMPCR_READY BIT_(8) + +// SYSCFG clock control + +#define CYGHWR_HAL_STM32_SYSCFG_CLOCK CYGHWR_HAL_STM32_CLOCK( APB2, SYSCFG ) + +#endif // if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE) + + +//============================================================================= +// External interrupt controller + +#define CYGHWR_HAL_STM32_EXTI_IMR 0x00 +#define CYGHWR_HAL_STM32_EXTI_EMR 0x04 +#define CYGHWR_HAL_STM32_EXTI_RTSR 0x08 +#define CYGHWR_HAL_STM32_EXTI_FTSR 0x0C +#define CYGHWR_HAL_STM32_EXTI_SWIER 0x10 +#define CYGHWR_HAL_STM32_EXTI_PR 0x14 + +#define CYGHWR_HAL_STM32_EXTI_BIT(__b) BIT_(__b) + +//============================================================================= +// GPIO ports and pin configuration. Include separate header file for this +// to avoid this header getting unmanageable. +#include <cyg/hal/var_io_pins.h> + +//============================================================================= +// DMA controller register definitions. + +#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1) + +#define CYGHWR_HAL_STM32_DMA_ISR 0x00 +#define CYGHWR_HAL_STM32_DMA_IFCR 0x04 + +#define CYGHWR_HAL_STM32_DMA_ISR_REG(__chan) CYGHWR_HAL_STM32_DMA_ISR +#define CYGHWR_HAL_STM32_DMA_IFCR_REG(__chan) CYGHWR_HAL_STM32_DMA_IFCR + +#elif defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE) + +#define CYGHWR_HAL_STM32_DMA_LISR 0x00 +#define CYGHWR_HAL_STM32_DMA_HISR 0x04 +#define CYGHWR_HAL_STM32_DMA_LIFCR 0x08 +#define CYGHWR_HAL_STM32_DMA_HIFCR 0x0C + +#define CYGHWR_HAL_STM32_DMA_ISR_REG(__stream) ((__stream)>3 ? \ + CYGHWR_HAL_STM32_DMA_HISR : \ + CYGHWR_HAL_STM32_DMA_LISR) +#define CYGHWR_HAL_STM32_DMA_IFCR_REG(__stream) ((__stream)>3 ? \ + CYGHWR_HAL_STM32_DMA_HIFCR : \ + CYGHWR_HAL_STM32_DMA_LIFCR) + +#endif // elif defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE) + + +// The following macros allow access to the per-channel DMA registers, indexed +// by channel number. For F1 parts there is no concept of a stream - each entry +// has a fixed relationship to the corresponding channel. +// Valid channel/stream numbers are 1 to 7 for DMA1 and 1 to 5 for DMA2 on F1 +// parts, 1 to 7 for DMA2 streams on F2/F4 parts. +#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1) +#define CYGHWR_HAL_STM32_DMA_CCR(__x) (0x14*(__x)-0x0C) +#define CYGHWR_HAL_STM32_DMA_CNDTR(__x) (0x14*(__x)-0x08) +#define CYGHWR_HAL_STM32_DMA_CPAR(__x) (0x14*(__x)-0x04) +#define CYGHWR_HAL_STM32_DMA_CMAR(__x) (0x14*(__x)) + +#define CYGHWR_HAL_STM32_DMA_ISR_GIF(__x) BIT_(4*(__x)-4) +#define CYGHWR_HAL_STM32_DMA_ISR_TCIF(__x) BIT_(4*(__x)-3) +#define CYGHWR_HAL_STM32_DMA_ISR_HTIF(__x) BIT_(4*(__x)-2) +#define CYGHWR_HAL_STM32_DMA_ISR_TEIF(__x) BIT_(4*(__x)-1) +#define CYGHWR_HAL_STM32_DMA_ISR_MASK(__x) VALUE_(4*(__x)-4,0xF) + +#define CYGHWR_HAL_STM32_DMA_IFCR_CGIF(__x) BIT_(4*(__x)-4) +#define CYGHWR_HAL_STM32_DMA_IFCR_CTCIF(__x) BIT_(4*(__x)-3) +#define CYGHWR_HAL_STM32_DMA_IFCR_CHTIF(__x) BIT_(4*(__x)-2) +#define CYGHWR_HAL_STM32_DMA_IFCR_CTEIF(__x) BIT_(4*(__x)-1) +#define CYGHWR_HAL_STM32_DMA_IFCR_MASK(__x) VALUE_(4*(__x)-4,0xF) +#elif defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE) +#define CYGHWR_HAL_STM32_DMA_SCR(__x) (0x18*(__x)+0x10) +#define CYGHWR_HAL_STM32_DMA_SNDTR(__x) (0x18*(__x)+0x14) +#define CYGHWR_HAL_STM32_DMA_SPAR(__x) (0x18*(__x)+0x18) +#define CYGHWR_HAL_STM32_DMA_SM0AR(__x) (0x18*(__x)+0x1C) +#define CYGHWR_HAL_STM32_DMA_SM1AR(__x) (0x18*(__x)+0x20) +#define CYGHWR_HAL_STM32_DMA_SFCR(__x) (0x18*(__x)+0x24) + +// For now at least we implement an identity mapping between +// streams and channels. +#define CYGHWR_HAL_STM32_DMA_CCR(__x) CYGHWR_HAL_STM32_DMA_SCR(__x) +#define CYGHWR_HAL_STM32_DMA_CNDTR(__x) CYGHWR_HAL_STM32_DMA_SNDTR(__x) +#define CYGHWR_HAL_STM32_DMA_CPAR(__x) CYGHWR_HAL_STM32_DMA_SPAR(__x) +#define CYGHWR_HAL_STM32_DMA_CMAR(__x) CYGHWR_HAL_STM32_DMA_SM0AR(__x) +#define CYGHWR_HAL_STM32_DMA_CM0AR(__x) CYGHWR_HAL_STM32_DMA_SM0AR(__x) +#define CYGHWR_HAL_STM32_DMA_CM1AR(__x) CYGHWR_HAL_STM32_DMA_SM1AR(__x) + +// This selects which region of an isr register to use for a stream +#define CYGHWR_HAL_STM32_DMA_ISR_SHIFT(__x) ( ((__x)&0x3) == 3 ? 22 : \ + ((__x)&0x3) == 2 ? 16 : \ + ((__x)&0x3) == 1 ? 6 : 0 ) + +#define CYGHWR_HAL_STM32_DMA_ISR_FEIF(__x) BIT_( CYGHWR_HAL_STM32_DMA_ISR_SHIFT(__x) ) +#define CYGHWR_HAL_STM32_DMA_ISR_DMEIF(__x) BIT_( CYGHWR_HAL_STM32_DMA_ISR_SHIFT(__x) + 2 ) +#define CYGHWR_HAL_STM32_DMA_ISR_TEIF(__x) BIT_( CYGHWR_HAL_STM32_DMA_ISR_SHIFT(__x) + 3 ) +#define CYGHWR_HAL_STM32_DMA_ISR_HTIF(__x) BIT_( CYGHWR_HAL_STM32_DMA_ISR_SHIFT(__x) + 4 ) +#define CYGHWR_HAL_STM32_DMA_ISR_TCIF(__x) BIT_( CYGHWR_HAL_STM32_DMA_ISR_SHIFT(__x) + 5 ) + +#define CYGHWR_HAL_STM32_DMA_ISR_MASK(__x) VALUE_( CYGHWR_HAL_STM32_DMA_ISR_SHIFT(__x), 0x3f ) + +// This selects which region of an ifcr register to use for a stream. +// Happens to be laid out the same as the isr, so reuse. +#define CYGHWR_HAL_STM32_DMA_IFCR_SHIFT(__x) CYGHWR_HAL_STM32_DMA_ISR_SHIFT(__x) + +#define CYGHWR_HAL_STM32_DMA_IFCR_CFEIF(__x) BIT_( CYGHWR_HAL_STM32_DMA_IFCR_SHIFT(__x) ) +#define CYGHWR_HAL_STM32_DMA_IFCR_CDMEIF(__x) BIT_( CYGHWR_HAL_STM32_DMA_IFCR_SHIFT(__x) + 2 ) +#define CYGHWR_HAL_STM32_DMA_IFCR_CTEIF(__x) BIT_( CYGHWR_HAL_STM32_DMA_IFCR_SHIFT(__x) + 3 ) +#define CYGHWR_HAL_STM32_DMA_IFCR_CHTIF(__x) BIT_( CYGHWR_HAL_STM32_DMA_IFCR_SHIFT(__x) + 4 ) +#define CYGHWR_HAL_STM32_DMA_IFCR_CTCIF(__x) BIT_( CYGHWR_HAL_STM32_DMA_IFCR_SHIFT(__x) + 5 ) +#define CYGHWR_HAL_STM32_DMA_IFCR_MASK(__x) VALUE_( CYGHWR_HAL_STM32_DMA_IFCR_SHIFT(__x), 0x3f ) + +#endif // elif defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE) + + +#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1) + +#define CYGHWR_HAL_STM32_DMA_CCR_EN BIT_(0) +#define CYGHWR_HAL_STM32_DMA_CCR_TCIE BIT_(1) +#define CYGHWR_HAL_STM32_DMA_CCR_HTIE BIT_(2) +#define CYGHWR_HAL_STM32_DMA_CCR_TEIE BIT_(3) +#define CYGHWR_HAL_STM32_DMA_CCR_DIR BIT_(4) +#define CYGHWR_HAL_STM32_DMA_CCR_CIRC BIT_(5) +#define CYGHWR_HAL_STM32_DMA_CCR_PINC BIT_(6) +#define CYGHWR_HAL_STM32_DMA_CCR_MINC BIT_(7) +#define CYGHWR_HAL_STM32_DMA_CCR_PSIZE8 VALUE_(8,0) +#define CYGHWR_HAL_STM32_DMA_CCR_PSIZE16 VALUE_(8,1) +#define CYGHWR_HAL_STM32_DMA_CCR_PSIZE32 VALUE_(8,2) +#define CYGHWR_HAL_STM32_DMA_CCR_MSIZE8 VALUE_(10,0) +#define CYGHWR_HAL_STM32_DMA_CCR_MSIZE16 VALUE_(10,1) +#define CYGHWR_HAL_STM32_DMA_CCR_MSIZE32 VALUE_(10,2) +#define CYGHWR_HAL_STM32_DMA_CCR_PL(__x) VALUE_(12,__x) +#define CYGHWR_HAL_STM32_DMA_CCR_PLLOW VALUE_(12,0) +#define CYGHWR_HAL_STM32_DMA_CCR_PLMEDIUM VALUE_(12,1) +#define CYGHWR_HAL_STM32_DMA_CCR_PLHIGH VALUE_(12,2) +#define CYGHWR_HAL_STM32_DMA_CCR_PLMAX VALUE_(12,3) +#define CYGHWR_HAL_STM32_DMA_CCR_MEM2MEM BIT_(14) + +// F2/F4 compatibility combinations to control transfer source/dest +#define CYGHWR_HAL_STM32_DMA_CCR_P2MEM 0 +#define CYGHWR_HAL_STM32_DMA_CCR_MEM2P CYGHWR_HAL_STM32_DMA_CCR_DIR + +// Clock enable bits + +#define CYGHWR_HAL_STM32_DMA1_CLOCK CYGHWR_HAL_STM32_CLOCK( AHB, DMA1 ) +#define CYGHWR_HAL_STM32_DMA2_CLOCK CYGHWR_HAL_STM32_CLOCK( AHB, DMA2 ) + +#elif defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE) + +#define CYGHWR_HAL_STM32_DMA_CCR_EN BIT_(0) +#define CYGHWR_HAL_STM32_DMA_CCR_DMEIE BIT_(1) +#define CYGHWR_HAL_STM32_DMA_CCR_TEIE BIT_(2) +#define CYGHWR_HAL_STM32_DMA_CCR_HTIE BIT_(3) +#define CYGHWR_HAL_STM32_DMA_CCR_TCIE BIT_(4) +#define CYGHWR_HAL_STM32_DMA_CCR_PFCTRL BIT_(5) +#define CYGHWR_HAL_STM32_DMA_CCR_P2MEM VALUE_(6,0) +#define CYGHWR_HAL_STM32_DMA_CCR_MEM2P VALUE_(6,1) +#define CYGHWR_HAL_STM32_DMA_CCR_MEM2MEM VALUE_(6,2) + +#define CYGHWR_HAL_STM32_DMA_CCR_CIRC BIT_(8) +#define CYGHWR_HAL_STM32_DMA_CCR_PINC BIT_(9) +#define CYGHWR_HAL_STM32_DMA_CCR_MINC BIT_(10) +#define CYGHWR_HAL_STM32_DMA_CCR_PSIZE8 VALUE_(11,0) +#define CYGHWR_HAL_STM32_DMA_CCR_PSIZE16 VALUE_(11,1) +#define CYGHWR_HAL_STM32_DMA_CCR_PSIZE32 VALUE_(11,2) +#define CYGHWR_HAL_STM32_DMA_CCR_MSIZE8 VALUE_(13,0) +#define CYGHWR_HAL_STM32_DMA_CCR_MSIZE16 VALUE_(13,1) +#define CYGHWR_HAL_STM32_DMA_CCR_MSIZE32 VALUE_(13,2) +#define CYGHWR_HAL_STM32_DMA_CCR_PINCOS BIT_(15) +#define CYGHWR_HAL_STM32_DMA_CCR_PL(__x) VALUE_(16,__x) +#define CYGHWR_HAL_STM32_DMA_CCR_PLLOW VALUE_(16,0) +#define CYGHWR_HAL_STM32_DMA_CCR_PLMEDIUM VALUE_(16,1) +#define CYGHWR_HAL_STM32_DMA_CCR_PLHIGH VALUE_(16,2) +#define CYGHWR_HAL_STM32_DMA_CCR_PLMAX VALUE_(16,3) +#define CYGHWR_HAL_STM32_DMA_CCR_DBM BIT_(18) +#define CYGHWR_HAL_STM32_DMA_CCR_CT BIT_(19) +#define CYGHWR_HAL_STM32_DMA_CCR_PBURST1 VALUE_(21,0) +#define CYGHWR_HAL_STM32_DMA_CCR_PBURST4 VALUE_(21,1) +#define CYGHWR_HAL_STM32_DMA_CCR_PBURST8 VALUE_(21,2) +#define CYGHWR_HAL_STM32_DMA_CCR_PBURST16 VALUE_(21,3) +#define CYGHWR_HAL_STM32_DMA_CCR_MBURST1 VALUE_(23,0) +#define CYGHWR_HAL_STM32_DMA_CCR_MBURST4 VALUE_(23,1) +#define CYGHWR_HAL_STM32_DMA_CCR_MBURST8 VALUE_(23,2) +#define CYGHWR_HAL_STM32_DMA_CCR_MBURST16 VALUE_(23,3) +#define CYGHWR_HAL_STM32_DMA_CCR_CHSEL(__x) VALUE_(25,__x) + +#define CYGHWR_HAL_STM32_DMA_FCR_FTH_QUARTER VALUE_(0,0) // FIFO threshold selection +#define CYGHWR_HAL_STM32_DMA_FCR_FTH_HALF VALUE_(0,1) +#define CYGHWR_HAL_STM32_DMA_FCR_FTH_3QUARTER VALUE_(0,2) +#define CYGHWR_HAL_STM32_DMA_FCR_FTH_FULL VALUE_(0,3) +#define CYGHWR_HAL_STM32_DMA_FCR_DMDIS BIT_(2) +#define CYGHWR_HAL_STM32_DMA_FCR_FS_LTQUARTER VALUE_(3,0) // LT==less than +#define CYGHWR_HAL_STM32_DMA_FCR_FS_LTHALF VALUE_(3,1) +#define CYGHWR_HAL_STM32_DMA_FCR_FS_LT3QUARTER VALUE_(3,2) +#define CYGHWR_HAL_STM32_DMA_FCR_FS_LTFULL VALUE_(3,3) +#define CYGHWR_HAL_STM32_DMA_FCR_FS_EMPTY VALUE_(3,4) +#define CYGHWR_HAL_STM32_DMA_FCR_FS_FULL VALUE_(3,5) +#define CYGHWR_HAL_STM32_DMA_FCR_FEIE BIT_(7) + +// Clock enable bits + +#define CYGHWR_HAL_STM32_DMA1_CLOCK CYGHWR_HAL_STM32_CLOCK( AHB1, DMA1 ) +#define CYGHWR_HAL_STM32_DMA2_CLOCK CYGHWR_HAL_STM32_CLOCK( AHB1, DMA2 ) + +#endif // elif defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE) + +//============================================================================= +// UARTs +// Include separate header file for this to avoid this header getting unmanageable. + +#include <cyg/hal/var_io_usart.h> + +//============================================================================= +// ADCs + +#define CYGHWR_HAL_STM32_ADC_SR 0x00 +#define CYGHWR_HAL_STM32_ADC_CR1 0x04 +#define CYGHWR_HAL_STM32_ADC_CR2 0x08 +#define CYGHWR_HAL_STM32_ADC_SMPR1 0x0C +#define CYGHWR_HAL_STM32_ADC_SMPR2 0x10 +#define CYGHWR_HAL_STM32_ADC_JOFR(__x) 0x14 + ((__x) << 2) +#define CYGHWR_HAL_STM32_ADC_HTR 0x24 +#define CYGHWR_HAL_STM32_ADC_LTR 0x28 +#define CYGHWR_HAL_STM32_ADC_SQR1 0x2C +#define CYGHWR_HAL_STM32_ADC_SQR2 0x30 +#define CYGHWR_HAL_STM32_ADC_SQR3 0x34 +#define CYGHWR_HAL_STM32_ADC_JSQR 0x38 +#define CYGHWR_HAL_STM32_ADC_JDR(__x) 0x3C + ((__x) << 2) +#define CYGHWR_HAL_STM32_ADC_DR 0x4C + +// SR fields + +#define CYGHWR_HAL_STM32_ADC_SR_AWD BIT_(0) +#define CYGHWR_HAL_STM32_ADC_SR_EOC BIT_(1) +#define CYGHWR_HAL_STM32_ADC_SR_JEOC BIT_(2) +#define CYGHWR_HAL_STM32_ADC_SR_JSTRT BIT_(3) +#define CYGHWR_HAL_STM32_ADC_SR_STRT BIT_(4) + +// CR1 fields + +#define CYGHWR_HAL_STM32_ADC_CR1_AWDCH(__x) VALUE_(0,(__x)) +#define CYGHWR_HAL_STM32_ADC_CR1_EOCIE BIT_(5) +#define CYGHWR_HAL_STM32_ADC_CR1_AWDIE BIT_(6) +#define CYGHWR_HAL_STM32_ADC_CR1_JEOCIE BIT_(7) +#define CYGHWR_HAL_STM32_ADC_CR1_SCAN BIT_(8) +#define CYGHWR_HAL_STM32_ADC_CR1_AWDSGL BIT_(9) +#define CYGHWR_HAL_STM32_ADC_CR1_JAUTO BIT_(10) +#define CYGHWR_HAL_STM32_ADC_CR1_DISCEN BIT_(11) +#define CYGHWR_HAL_STM32_ADC_CR1_JDISCEN BIT_(12) +#define CYGHWR_HAL_STM32_ADC_CR1_DISCNUM(__x) VALUE_(13,(__x)) +#if defined(CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1) +#define CYGHWR_HAL_STM32_ADC_CR1_DUALMODE(__x) VALUE_(16,(__x)) +#endif // CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1 +#define CYGHWR_HAL_STM32_ADC_CR1_JAWDEN BIT_(22) +#define CYGHWR_HAL_STM32_ADC_CR1_AWDEN BIT_(23) +#if defined(CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE) +#define CYGHWR_HAL_STM32_ADC_CR1_OVRIE BIT_(26) +#endif // CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE + + + +// CR2 fields + +#define CYGHWR_HAL_STM32_ADC_CR2_ADON BIT_(0) +#define CYGHWR_HAL_STM32_ADC_CR2_CONT BIT_(1) +#if defined(CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1) +#define CYGHWR_HAL_STM32_ADC_CR2_CAL BIT_(2) +#define CYGHWR_HAL_STM32_ADC_CR2_RSTCAL BIT_(3) +#endif // CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1 +#define CYGHWR_HAL_STM32_ADC_CR2_DMA BIT_(8) +#if defined(CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE) +#define CYGHWR_HAL_STM32_ADC_CR2_DDS BIT_(9) +#define CYGHWR_HAL_STM32_ADC_CR2_EOCS BIT_(10) +#endif // CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE + +#define CYGHWR_HAL_STM32_ADC_CR2_ALIGN BIT_(11) +#if defined(CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1) +#define CYGHWR_HAL_STM32_ADC_CR2_JEXTSEL(__x) VALUE_(12,(__x)) +#define CYGHWR_HAL_STM32_ADC_CR2_JEXTTRIG BIT_(15) +#define CYGHWR_HAL_STM32_ADC_CR2_EXTSEL(__x) VALUE_(17,(__x)) +#define CYGHWR_HAL_STM32_ADC_CR2_EXTTRIG BIT_(20) +#define CYGHWR_HAL_STM32_ADC_CR2_JSWSTART BIT_(21) +#define CYGHWR_HAL_STM32_ADC_CR2_SWSTART BIT_(22) +#define CYGHWR_HAL_STM32_ADC_CR2_TSVREFE BIT_(23) +#elif defined(CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE) +#define CYGHWR_HAL_STM32_ADC_CR2_JEXTSEL(__x) VALUE_(16,(__x)) +#define CYGHWR_HAL_STM32_ADC_CR2_JEXTEN(__x) VALUE_(20,(__x)) +#define CYGHWR_HAL_STM32_ADC_CR2_JSWSTART BIT_(22) +#define CYGHWR_HAL_STM32_ADC_CR2_EXTSEL(__x) VALUE_(24,(__x)) +#define CYGHWR_HAL_STM32_ADC_CR2_EXTEN(__x) VALUE_(28,(__x)) +#define CYGHWR_HAL_STM32_ADC_CR2_SWSTART BIT_(30) +#endif + +#if defined(CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1) +// On F1 devices ADC1 and ADC3 have different external event sets for regular groups +#define CYGHWR_HAL_STM32_ADC_EXTSEL_ADC1_TIM1_CC1 (0) +#define CYGHWR_HAL_STM32_ADC_EXTSEL_ADC1_TIM1_CC2 (1) +#define CYGHWR_HAL_STM32_ADC_EXTSEL_ADC1_TIM1_CC3 (2) +#define CYGHWR_HAL_STM32_ADC_EXTSEL_ADC1_TIM2_CC2 (3) +#define CYGHWR_HAL_STM32_ADC_EXTSEL_ADC1_TIM3_TRGO (4) +#define CYGHWR_HAL_STM32_ADC_EXTSEL_ADC1_TIM4_CC4 (5) +#define CYGHWR_HAL_STM32_ADC_EXTSEL_ADC1_TIM8_TRGO (6) // For high- and XL-density devices +#define CYGHWR_HAL_STM32_ADC_EXTSEL_ADC1_SWSTART (7) + +#define CYGHWR_HAL_STM32_ADC_EXTSEL_ADC3_TIM3_CC1 (0) +#define CYGHWR_HAL_STM32_ADC_EXTSEL_ADC3_TIM2_CC3 (1) +#define CYGHWR_HAL_STM32_ADC_EXTSEL_ADC3_TIM1_CC3 (2) +#define CYGHWR_HAL_STM32_ADC_EXTSEL_ADC3_TIM8_CC1 (3) +#define CYGHWR_HAL_STM32_ADC_EXTSEL_ADC3_TIM8_TRGO (4) +#define CYGHWR_HAL_STM32_ADC_EXTSEL_ADC3_TIM5_CC1 (5) +#define CYGHWR_HAL_STM32_ADC_EXTSEL_ADC3_TIM5_CC3 (6) +#define CYGHWR_HAL_STM32_ADC_EXTSEL_ADC3_SWSTART (7) +#endif // CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1 + +#if defined(CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE) +#define CYGHWR_HAL_STM32_ADC_EXTSEL_TIM1_CC1 (0) +#define CYGHWR_HAL_STM32_ADC_EXTSEL_TIM1_CC2 (1) +#define CYGHWR_HAL_STM32_ADC_EXTSEL_TIM1_CC3 (2) +#define CYGHWR_HAL_STM32_ADC_EXTSEL_TIM2_CC2 (3) +#define CYGHWR_HAL_STM32_ADC_EXTSEL_TIM2_CC3 (4) +#define CYGHWR_HAL_STM32_ADC_EXTSEL_TIM2_CC4 (5) +#define CYGHWR_HAL_STM32_ADC_EXTSEL_TIM2_TRGO (6) +#define CYGHWR_HAL_STM32_ADC_EXTSEL_TIM3_CC1 (7) +#define CYGHWR_HAL_STM32_ADC_EXTSEL_TIM3_TRGO (8) +#define CYGHWR_HAL_STM32_ADC_EXTSEL_TIM4_CC4 (9) +#define CYGHWR_HAL_STM32_ADC_EXTSEL_TIM5_CC1 (10) +#define CYGHWR_HAL_STM32_ADC_EXTSEL_TIM5_CC2 (11) +#define CYGHWR_HAL_STM32_ADC_EXTSEL_TIM5_CC3 (12) +#define CYGHWR_HAL_STM32_ADC_EXTSEL_TIM8_CC1 (13) +#define CYGHWR_HAL_STM32_ADC_EXTSEL_TIM8_TRGO (14) +#define CYGHWR_HAL_STM32_ADC_EXTSEL_EXTI (15) // line 11 + +#define CYGHWR_HAL_STM32_ADC_EXTEN_DISABLED (0) +#define CYGHWR_HAL_STM32_ADC_EXTEN_EDGE_RISE (1) +#define CYGHWR_HAL_STM32_ADC_EXTEN_EDGE_FALL (2) +#define CYGHWR_HAL_STM32_ADC_EXTEN_EDGE_BOTH (3) + +#endif // CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE + +// SMPRx fields + +#if defined(CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1) +// F1 : SMPR1 17..10 : SMPR2 9..0 +#define CYGHWR_HAL_STM32_ADC_SMPR1_NUM_CHANNELS (8) +#define CYGHWR_HAL_STM32_ADC_SMPR2_NUM_CHANNELS (10) +#endif // CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1 +#if defined(CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE) +// F2/F4 : SMPR1 18..10 : SMPR2 9..0 +#define CYGHWR_HAL_STM32_ADC_SMPR1_NUM_CHANNELS (9) +#define CYGHWR_HAL_STM32_ADC_SMPR2_NUM_CHANNELS (10) +#endif // CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE + +#define CYGHWR_HAL_STM32_ADC_SMPRx_SMP(__x, __y) VALUE_((__x) * 3, (__y)) + +// SQRx fields + +#define CYGHWR_HAL_STM32_ADC_SQR1_L(__x) VALUE_(20, (__x)) +#define CYGHWR_HAL_STM32_ADC_SQRx_SQ(__x, __y) VALUE_((__x) * 5, (__y)) + +// JSQR fields + +#define CYGHWR_HAL_STM32_ADC_JSQR_SQ(__x, __y) VALUE_((__x) * 5, (__y)) + +// ADC GPIO pins + +// F1/F2/F4 GPIO inputs have 16 channels (0..15). +// ADC1 has extra internal sources, which for F1 and HIPERFORMANCE (F2/F4) +// devices respectively have 18 (0..17) and 19 (0..18) available sources. + +// Internal (non-GPIO) channels (ADC1 only): +// - ADC1_IN16 temperature F1/F2/F4 +// - ADC1_IN17 Vrefint F1/F2/F4 +// - ADC1_IN18 Vbat F2/F4 + +#define CYGHWR_HAL_STM32_ADC123_IN0 CYGHWR_HAL_STM32_PIN_ANALOG( A, 0 ) +#define CYGHWR_HAL_STM32_ADC123_IN1 CYGHWR_HAL_STM32_PIN_ANALOG( A, 1 ) +#define CYGHWR_HAL_STM32_ADC123_IN2 CYGHWR_HAL_STM32_PIN_ANALOG( A, 2 ) +#define CYGHWR_HAL_STM32_ADC123_IN3 CYGHWR_HAL_STM32_PIN_ANALOG( A, 3 ) + +#define CYGHWR_HAL_STM32_ADC12_IN4 CYGHWR_HAL_STM32_PIN_ANALOG( A, 4 ) +#define CYGHWR_HAL_STM32_ADC12_IN5 CYGHWR_HAL_STM32_PIN_ANALOG( A, 5 ) +#define CYGHWR_HAL_STM32_ADC12_IN6 CYGHWR_HAL_STM32_PIN_ANALOG( A, 6 ) +#define CYGHWR_HAL_STM32_ADC12_IN7 CYGHWR_HAL_STM32_PIN_ANALOG( A, 7 ) + +#define CYGHWR_HAL_STM32_ADC12_IN8 CYGHWR_HAL_STM32_PIN_ANALOG( B, 0 ) +#define CYGHWR_HAL_STM32_ADC12_IN9 CYGHWR_HAL_STM32_PIN_ANALOG( B, 1 ) + +#define CYGHWR_HAL_STM32_ADC3_IN4 CYGHWR_HAL_STM32_PIN_ANALOG( F, 6 ) +#define CYGHWR_HAL_STM32_ADC3_IN5 CYGHWR_HAL_STM32_PIN_ANALOG( F, 7 ) +#define CYGHWR_HAL_STM32_ADC3_IN6 CYGHWR_HAL_STM32_PIN_ANALOG( F, 8 ) +#define CYGHWR_HAL_STM32_ADC3_IN7 CYGHWR_HAL_STM32_PIN_ANALOG( F, 9 ) +#define CYGHWR_HAL_STM32_ADC3_IN8 CYGHWR_HAL_STM32_PIN_ANALOG( F, 10 ) + +#define CYGHWR_HAL_STM32_ADC123_IN10 CYGHWR_HAL_STM32_PIN_ANALOG( C, 0 ) +#define CYGHWR_HAL_STM32_ADC123_IN11 CYGHWR_HAL_STM32_PIN_ANALOG( C, 1 ) +#define CYGHWR_HAL_STM32_ADC123_IN12 CYGHWR_HAL_STM32_PIN_ANALOG( C, 2 ) +#define CYGHWR_HAL_STM32_ADC123_IN13 CYGHWR_HAL_STM32_PIN_ANALOG( C, 3 ) + +#define CYGHWR_HAL_STM32_ADC12_IN14 CYGHWR_HAL_STM32_PIN_ANALOG( C, 4 ) +#define CYGHWR_HAL_STM32_ADC12_IN15 CYGHWR_HAL_STM32_PIN_ANALOG( C, 5) + +#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1) +// Following ADC3 channels not-mapped on F1 devices +#define CYGHWR_HAL_STM32_ADC3_IN9 CYGHWR_HAL_STM32_GPIO_NONE +#define CYGHWR_HAL_STM32_ADC3_IN14 CYGHWR_HAL_STM32_GPIO_NONE +#define CYGHWR_HAL_STM32_ADC3_IN15 CYGHWR_HAL_STM32_GPIO_NONE +#elif defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE) +#define CYGHWR_HAL_STM32_ADC3_IN9 CYGHWR_HAL_STM32_PIN_ANALOG( F, 3 ) +#define CYGHWR_HAL_STM32_ADC3_IN14 CYGHWR_HAL_STM32_PIN_ANALOG( F, 4 ) +#define CYGHWR_HAL_STM32_ADC3_IN15 CYGHWR_HAL_STM32_PIN_ANALOG( F, 5 ) +#endif + +// ADC1 GPIO pin aliases + +#define CYGHWR_HAL_STM32_ADC1_IN0 CYGHWR_HAL_STM32_ADC123_IN0 +#define CYGHWR_HAL_STM32_ADC1_IN1 CYGHWR_HAL_STM32_ADC123_IN1 +#define CYGHWR_HAL_STM32_ADC1_IN2 CYGHWR_HAL_STM32_ADC123_IN2 +#define CYGHWR_HAL_STM32_ADC1_IN3 CYGHWR_HAL_STM32_ADC123_IN3 +#define CYGHWR_HAL_STM32_ADC1_IN4 CYGHWR_HAL_STM32_ADC12_IN4 +#define CYGHWR_HAL_STM32_ADC1_IN5 CYGHWR_HAL_STM32_ADC12_IN5 +#define CYGHWR_HAL_STM32_ADC1_IN6 CYGHWR_HAL_STM32_ADC12_IN6 +#define CYGHWR_HAL_STM32_ADC1_IN7 CYGHWR_HAL_STM32_ADC12_IN7 +#define CYGHWR_HAL_STM32_ADC1_IN8 CYGHWR_HAL_STM32_ADC12_IN8 +#define CYGHWR_HAL_STM32_ADC1_IN9 CYGHWR_HAL_STM32_ADC12_IN9 +#define CYGHWR_HAL_STM32_ADC1_IN10 CYGHWR_HAL_STM32_ADC123_IN10 +#define CYGHWR_HAL_STM32_ADC1_IN11 CYGHWR_HAL_STM32_ADC123_IN11 +#define CYGHWR_HAL_STM32_ADC1_IN12 CYGHWR_HAL_STM32_ADC123_IN12 +#define CYGHWR_HAL_STM32_ADC1_IN13 CYGHWR_HAL_STM32_ADC123_IN13 +#define CYGHWR_HAL_STM32_ADC1_IN14 CYGHWR_HAL_STM32_ADC12_IN14 +#define CYGHWR_HAL_STM32_ADC1_IN15 CYGHWR_HAL_STM32_ADC12_IN15 + +// ADC2 GPIO pin aliases + +#define CYGHWR_HAL_STM32_ADC2_IN0 CYGHWR_HAL_STM32_ADC123_IN0 +#define CYGHWR_HAL_STM32_ADC2_IN1 CYGHWR_HAL_STM32_ADC123_IN1 +#define CYGHWR_HAL_STM32_ADC2_IN2 CYGHWR_HAL_STM32_ADC123_IN2 +#define CYGHWR_HAL_STM32_ADC2_IN3 CYGHWR_HAL_STM32_ADC123_IN3 +#define CYGHWR_HAL_STM32_ADC2_IN4 CYGHWR_HAL_STM32_ADC12_IN4 +#define CYGHWR_HAL_STM32_ADC2_IN5 CYGHWR_HAL_STM32_ADC12_IN5 +#define CYGHWR_HAL_STM32_ADC2_IN6 CYGHWR_HAL_STM32_ADC12_IN6 +#define CYGHWR_HAL_STM32_ADC2_IN7 CYGHWR_HAL_STM32_ADC12_IN7 +#define CYGHWR_HAL_STM32_ADC2_IN8 CYGHWR_HAL_STM32_ADC12_IN8 +#define CYGHWR_HAL_STM32_ADC2_IN9 CYGHWR_HAL_STM32_ADC12_IN9 +#define CYGHWR_HAL_STM32_ADC2_IN10 CYGHWR_HAL_STM32_ADC123_IN10 +#define CYGHWR_HAL_STM32_ADC2_IN11 CYGHWR_HAL_STM32_ADC123_IN11 +#define CYGHWR_HAL_STM32_ADC2_IN12 CYGHWR_HAL_STM32_ADC123_IN12 +#define CYGHWR_HAL_STM32_ADC2_IN13 CYGHWR_HAL_STM32_ADC123_IN13 +#define CYGHWR_HAL_STM32_ADC2_IN14 CYGHWR_HAL_STM32_ADC12_IN14 +#define CYGHWR_HAL_STM32_ADC2_IN15 CYGHWR_HAL_STM32_ADC12_IN15 + +// ADC3 GPIO pin aliases + +#define CYGHWR_HAL_STM32_ADC3_IN0 CYGHWR_HAL_STM32_ADC123_IN0 +#define CYGHWR_HAL_STM32_ADC3_IN1 CYGHWR_HAL_STM32_ADC123_IN1 +#define CYGHWR_HAL_STM32_ADC3_IN2 CYGHWR_HAL_STM32_ADC123_IN2 +#define CYGHWR_HAL_STM32_ADC3_IN3 CYGHWR_HAL_STM32_ADC123_IN3 +// Inputs 4 - 9 are already defined +#define CYGHWR_HAL_STM32_ADC3_IN10 CYGHWR_HAL_STM32_ADC123_IN10 +#define CYGHWR_HAL_STM32_ADC3_IN11 CYGHWR_HAL_STM32_ADC123_IN11 +#define CYGHWR_HAL_STM32_ADC3_IN12 CYGHWR_HAL_STM32_ADC123_IN12 +#define CYGHWR_HAL_STM32_ADC3_IN13 CYGHWR_HAL_STM32_ADC123_IN13 +// Inputs 14 - 15 are already defined + +// ADC Clock control pins + +#define CYGHWR_HAL_STM32_ADC1_CLOCK CYGHWR_HAL_STM32_CLOCK( APB2, ADC1 ) +#define CYGHWR_HAL_STM32_ADC2_CLOCK CYGHWR_HAL_STM32_CLOCK( APB2, ADC2 ) +#define CYGHWR_HAL_STM32_ADC3_CLOCK CYGHWR_HAL_STM32_CLOCK( APB2, ADC3 ) + +// F2/F4 only: Common configuration registers based from CYGHWR_HAL_STM32_ADC_COMMON +#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE) +#define CYGHWR_HAL_STM32_ADC_CSR 0x00 +#define CYGHWR_HAL_STM32_ADC_CCR 0x04 +#define CYGHWR_HAL_STM32_ADC_CDR 0x08 + +// CSR +#define CYGHWR_HAL_STM32_ADC_CSR_AWD BIT_(0) +#define CYGHWR_HAL_STM32_ADC_CSR_EOC BIT_(1) +#define CYGHWR_HAL_STM32_ADC_CSR_JEOC BIT_(2) +#define CYGHWR_HAL_STM32_ADC_CSR_JSTRT BIT_(3) +#define CYGHWR_HAL_STM32_ADC_CSR_STRT BIT_(4) +#define CYGHWR_HAL_STM32_ADC_CSR_OVR BIT_(5) + +#define CYGHWR_HAL_STM32_ADC1_CSR_AWD CYGHWR_HAL_STM32_ADC_CSR_AWD +#define CYGHWR_HAL_STM32_ADC1_CSR_EOC CYGHWR_HAL_STM32_ADC_CSR_EOC +#define CYGHWR_HAL_STM32_ADC1_CSR_JEOC CYGHWR_HAL_STM32_ADC_CSR_JEOC +#define CYGHWR_HAL_STM32_ADC1_CSR_JSTRT CYGHWR_HAL_STM32_ADC_CSR_JSTRT +#define CYGHWR_HAL_STM32_ADC1_CSR_STRT CYGHWR_HAL_STM32_ADC_CSR_STRT +#define CYGHWR_HAL_STM32_ADC1_CSR_OVR CYGHWR_HAL_STM32_ADC_CSR_OVR + +#define CYGHWR_HAL_STM32_ADC2_CSR_AWD (CYGHWR_HAL_STM32_ADC_CSR_AWD << 8) +#define CYGHWR_HAL_STM32_ADC2_CSR_EOC (CYGHWR_HAL_STM32_ADC_CSR_EOC << 8) +#define CYGHWR_HAL_STM32_ADC2_CSR_JEOC (CYGHWR_HAL_STM32_ADC_CSR_JEOC << 8) +#define CYGHWR_HAL_STM32_ADC2_CSR_JSTRT (CYGHWR_HAL_STM32_ADC_CSR_JSTRT << 8) +#define CYGHWR_HAL_STM32_ADC2_CSR_STRT (CYGHWR_HAL_STM32_ADC_CSR_STRT << 8) +#define CYGHWR_HAL_STM32_ADC2_CSR_OVR (CYGHWR_HAL_STM32_ADC_CSR_OVR << 8) + +#define CYGHWR_HAL_STM32_ADC3_CSR_AWD (CYGHWR_HAL_STM32_ADC_CSR_AWD << 16) +#define CYGHWR_HAL_STM32_ADC3_CSR_EOC (CYGHWR_HAL_STM32_ADC_CSR_EOC << 16) +#define CYGHWR_HAL_STM32_ADC3_CSR_JEOC (CYGHWR_HAL_STM32_ADC_CSR_JEOC << 16) +#define CYGHWR_HAL_STM32_ADC3_CSR_JSTRT (CYGHWR_HAL_STM32_ADC_CSR_JSTRT << 16) +#define CYGHWR_HAL_STM32_ADC3_CSR_STRT (CYGHWR_HAL_STM32_ADC_CSR_STRT << 16) +#define CYGHWR_HAL_STM32_ADC3_CSR_OVR (CYGHWR_HAL_STM32_ADC_CSR_OVR << 16) + +#define CYGHWR_HAL_STM32_ADC_CSR_ADC1(__csr) ((__csr) >> 0) +#define CYGHWR_HAL_STM32_ADC_CSR_ADC2(__csr) ((__csr) >> 8) +#define CYGHWR_HAL_STM32_ADC_CSR_ADC3(__csr) ((__csr) >> 16) + +// CCR +#define CYGHWR_HAL_STM32_ADC_CCR_MULTI_XXX VALUE_(0,0x1F) +#define CYGHWR_HAL_STM32_ADC_CCR_DELAY_XXX VALUE_(8,0xF) +#define CYGHWR_HAL_STM32_ADC_CCR_DDS BIT_(13) +#define CYGHWR_HAL_STM32_ADC_CCR_DMA_XXX VALUE_(14,0x3) +#define CYGHWR_HAL_STM32_ADC_CCR_ADCPRE_2 VALUE_(16,0x0) +#define CYGHWR_HAL_STM32_ADC_CCR_ADCPRE_4 VALUE_(16,0x1) +#define CYGHWR_HAL_STM32_ADC_CCR_ADCPRE_6 VALUE_(16,0x2) +#define CYGHWR_HAL_STM32_ADC_CCR_ADCPRE_8 VALUE_(16,0x3) +#define CYGHWR_HAL_STM32_ADC_CCR_ADCPRE_XXX VALUE_(16,0x3) +#define CYGHWR_HAL_STM32_ADC_CCR_VBATE BIT_(22) +#define CYGHWR_HAL_STM32_ADC_CCR_TSVREFE BIT_(23) + +// CDR +#define CYGHWR_HAL_STM32_ADC_CDR_DATA1_XXX VALUE_(0,0xFFFF) +#define CYGHWR_HAL_STM32_ADC_CDR_DATA2_XXX VALUE_(16,0xFFFF) +#endif + +//============================================================================= +// SPI interface register definitions. + +#define CYGHWR_HAL_STM32_SPI_CR1 0x00 +#define CYGHWR_HAL_STM32_SPI_CR2 0x04 +#define CYGHWR_HAL_STM32_SPI_SR 0x08 +#define CYGHWR_HAL_STM32_SPI_DR 0x0C +#define CYGHWR_HAL_STM32_SPI_CRCPR 0x10 +#define CYGHWR_HAL_STM32_SPI_RXCRCR 0x14 +#define CYGHWR_HAL_STM32_SPI_TXCRCR 0x18 +#define CYGHWR_HAL_STM32_SPI_I2SCFGR 0x1C +#define CYGHWR_HAL_STM32_SPI_I2SPR 0x20 + +#define CYGHWR_HAL_STM32_SPI_CR1_CPHA BIT_(0) +#define CYGHWR_HAL_STM32_SPI_CR1_CPOL BIT_(1) +#define CYGHWR_HAL_STM32_SPI_CR1_MSTR BIT_(2) +#define CYGHWR_HAL_STM32_SPI_CR1_BR(__x) VALUE_(3,(__x)) +#define CYGHWR_HAL_STM32_SPI_CR1_SPE BIT_(6) +#define CYGHWR_HAL_STM32_SPI_CR1_LSBFIRST BIT_(7) +#define CYGHWR_HAL_STM32_SPI_CR1_SSI BIT_(8) +#define CYGHWR_HAL_STM32_SPI_CR1_SSM BIT_(9) +#define CYGHWR_HAL_STM32_SPI_CR1_RXONLY BIT_(10) +#define CYGHWR_HAL_STM32_SPI_CR1_DFF BIT_(11) +#define CYGHWR_HAL_STM32_SPI_CR1_CRCNEXT BIT_(12) +#define CYGHWR_HAL_STM32_SPI_CR1_CRCEN BIT_(13) +#define CYGHWR_HAL_STM32_SPI_CR1_BIDIOE BIT_(14) +#define CYGHWR_HAL_STM32_SPI_CR1_BIDIMODE BIT_(15) + +#define CYGHWR_HAL_STM32_SPI_CR2_RXDMAEN BIT_(0) +#define CYGHWR_HAL_STM32_SPI_CR2_TXDMAEN BIT_(1) +#define CYGHWR_HAL_STM32_SPI_CR2_SSOE BIT_(2) +#define CYGHWR_HAL_STM32_SPI_CR2_ERRIE BIT_(5) +#define CYGHWR_HAL_STM32_SPI_CR2_RXNEIE BIT_(6) +#define CYGHWR_HAL_STM32_SPI_CR2_TXEIE BIT_(7) + +#define CYGHWR_HAL_STM32_SPI_SR_RXNE BIT_(0) +#define CYGHWR_HAL_STM32_SPI_SR_TXE BIT_(1) +#define CYGHWR_HAL_STM32_SPI_SR_CHSIDE BIT_(2) +#define CYGHWR_HAL_STM32_SPI_SR_UDR BIT_(3) +#define CYGHWR_HAL_STM32_SPI_SR_CRCERR BIT_(4) +#define CYGHWR_HAL_STM32_SPI_SR_MODF BIT_(5) +#define CYGHWR_HAL_STM32_SPI_SR_OVR BIT_(6) +#define CYGHWR_HAL_STM32_SPI_SR_BSY BIT_(7) + +#define CYGHWR_HAL_STM32_SPI_I2SCFGR_CHLEN BIT_(0) +#define CYGHWR_HAL_STM32_SPI_I2SCFGR_DATLEN16 VALUE_(1,0) +#define CYGHWR_HAL_STM32_SPI_I2SCFGR_DATLEN24 VALUE_(1,1) +#define CYGHWR_HAL_STM32_SPI_I2SCFGR_DATLEN32 VALUE_(1,2) +#define CYGHWR_HAL_STM32_SPI_I2SCFGR_CKPOL BIT_(3) +#define CYGHWR_HAL_STM32_SPI_I2SCFGR_I2SSTDPHL VALUE_(4,0) +#define CYGHWR_HAL_STM32_SPI_I2SCFGR_I2SSTDMSB VALUE_(4,1) +#define CYGHWR_HAL_STM32_SPI_I2SCFGR_I2SSTDLSB VALUE_(4,2) +#define CYGHWR_HAL_STM32_SPI_I2SCFGR_I2SSTDPCM VALUE_(4,3) +#define CYGHWR_HAL_STM32_SPI_I2SCFGR_PCMSYNC BIT_(7) +#define CYGHWR_HAL_STM32_SPI_I2SCFGR_I2SCFGST VALUE_(8,0) +#define CYGHWR_HAL_STM32_SPI_I2SCFGR_I2SCFGSR VALUE_(8,1) +#define CYGHWR_HAL_STM32_SPI_I2SCFGR_I2SCFGMT VALUE_(8,2) +#define CYGHWR_HAL_STM32_SPI_I2SCFGR_I2SCFGMR VALUE_(8,3) +#define CYGHWR_HAL_STM32_SPI_I2SCFGR_I2SE BIT_(10) +#define CYGHWR_HAL_STM32_SPI_I2SCFGR_I2MOD BIT_(11) + +#define CYGHWR_HAL_STM32_SPI_I2SPR_I2SDIV(__x) VALUE_(0,(__x)) +#define CYGHWR_HAL_STM32_SPI_I2SPR_ODD BIT_(8) +#define CYGHWR_HAL_STM32_SPI_I2SPR_MCKOE BIT_(9) + +// Clock control definitions for each SPI bus + +#define CYGHWR_HAL_STM32_SPI1_CLOCK CYGHWR_HAL_STM32_CLOCK( APB2, SPI1 ) +#define CYGHWR_HAL_STM32_SPI2_CLOCK CYGHWR_HAL_STM32_CLOCK( APB1, SPI2 ) +#define CYGHWR_HAL_STM32_SPI3_CLOCK CYGHWR_HAL_STM32_CLOCK( APB1, SPI3 ) + +//============================================================================= +// I2C busses + +#define CYGHWR_HAL_STM32_I2C_CR1 0x00 +#define CYGHWR_HAL_STM32_I2C_CR2 0x04 +#define CYGHWR_HAL_STM32_I2C_OAR1 0x08 +#define CYGHWR_HAL_STM32_I2C_OAR2 0x0C +#define CYGHWR_HAL_STM32_I2C_DR 0x10 +#define CYGHWR_HAL_STM32_I2C_SR1 0x14 +#define CYGHWR_HAL_STM32_I2C_SR2 0x18 +#define CYGHWR_HAL_STM32_I2C_CCR 0x1C +#define CYGHWR_HAL_STM32_I2C_TRISE 0x20 + +#define CYGHWR_HAL_STM32_I2C_CR1_PE BIT_(0) +#define CYGHWR_HAL_STM32_I2C_CR1_SMBUS BIT_(1) +#define CYGHWR_HAL_STM32_I2C_CR1_SMBTYPE BIT_(3) +#define CYGHWR_HAL_STM32_I2C_CR1_ENARP BIT_(4) +#define CYGHWR_HAL_STM32_I2C_CR1_ENPEC BIT_(5) +#define CYGHWR_HAL_STM32_I2C_CR1_ENGC BIT_(6) +#define CYGHWR_HAL_STM32_I2C_CR1_NOSTRETCH BIT_(7) +#define CYGHWR_HAL_STM32_I2C_CR1_START BIT_(8) +#define CYGHWR_HAL_STM32_I2C_CR1_STOP BIT_(9) +#define CYGHWR_HAL_STM32_I2C_CR1_ACK BIT_(10) +#define CYGHWR_HAL_STM32_I2C_CR1_POS BIT_(11) +#define CYGHWR_HAL_STM32_I2C_CR1_PEC BIT_(12) +#define CYGHWR_HAL_STM32_I2C_CR1_ALERT BIT_(13) +#define CYGHWR_HAL_STM32_I2C_CR1_SWRST BIT_(15) + + +#define CYGHWR_HAL_STM32_I2C_CR2_FREQ(__x) VALUE_(0,__x) +#define CYGHWR_HAL_STM32_I2C_CR2_FREQ_MASK MASK_(0,6) +#define CYGHWR_HAL_STM32_I2C_CR2_ITERREN BIT_(8) +#define CYGHWR_HAL_STM32_I2C_CR2_ITEVTEN BIT_(9) +#define CYGHWR_HAL_STM32_I2C_CR2_ITBUFEN BIT_(10) +#define CYGHWR_HAL_STM32_I2C_CR2_DMAEN BIT_(11) +#define CYGHWR_HAL_STM32_I2C_CR2_LAST BIT_(12) + +// OAR1 and OAR2 omitted, we only support master mode + +#define CYGHWR_HAL_STM32_I2C_SR1_SB BIT_(0) +#define CYGHWR_HAL_STM32_I2C_SR1_ADDR BIT_(1) +#define CYGHWR_HAL_STM32_I2C_SR1_BTF BIT_(2) +#define CYGHWR_HAL_STM32_I2C_SR1_ADD10 BIT_(3) +#define CYGHWR_HAL_STM32_I2C_SR1_STOPF BIT_(4) +#define CYGHWR_HAL_STM32_I2C_SR1_RxNE BIT_(6) +#define CYGHWR_HAL_STM32_I2C_SR1_TxE BIT_(7) +#define CYGHWR_HAL_STM32_I2C_SR1_BERR BIT_(8) +#define CYGHWR_HAL_STM32_I2C_SR1_ARLO BIT_(9) +#define CYGHWR_HAL_STM32_I2C_SR1_AF BIT_(10) +#define CYGHWR_HAL_STM32_I2C_SR1_OVR BIT_(11) +#define CYGHWR_HAL_STM32_I2C_SR1_PECERR BIT_(12) +#define CYGHWR_HAL_STM32_I2C_SR1_TIMEOUT BIT_(14) +#define CYGHWR_HAL_STM32_I2C_SR1_SMBALERT BIT_(15) + + +#define CYGHWR_HAL_STM32_I2C_SR2_MSL BIT_(0) +#define CYGHWR_HAL_STM32_I2C_SR2_BUSY BIT_(1) +#define CYGHWR_HAL_STM32_I2C_SR2_TRA BIT_(2) +#define CYGHWR_HAL_STM32_I2C_SR2_GENCALL BIT_(4) +#define CYGHWR_HAL_STM32_I2C_SR2_SMBDEFAULT BIT_(5) +#define CYGHWR_HAL_STM32_I2C_SR2_SMBHOST BIT_(6) +#define CYGHWR_HAL_STM32_I2C_SR2_DUALF BIT_(7) +#define CYGHWR_HAL_STM32_I2C_SR2_PEC MASK_(7,8) + +#define CYGHWR_HAL_STM32_I2C_CCR_CCR(__x) VALUE_(0,__x) +#define CYGHWR_HAL_STM32_I2C_CCR_CCR_MASK MASK_(0,12) +#define CYGHWR_HAL_STM32_I2C_CCR_DUTY_2 0 +#define CYGHWR_HAL_STM32_I2C_CCR_DUTY_16_9 BIT_(14) +#define CYGHWR_HAL_STM32_I2C_CCR_STD 0 +#define CYGHWR_HAL_STM32_I2C_CCR_FAST BIT_(15) + +#define CYGHWR_HAL_STM32_I2C_TRISE_VAL(__x) VALUE_(0,__x) +#define CYGHWR_HAL_STM32_I2C_TRISE_MASK MASK_(0,6) + +// Clock control definitions for each I2C bus + +#define CYGHWR_HAL_STM32_I2C1_CLOCK CYGHWR_HAL_STM32_CLOCK( APB1, I2C1 ) +#define CYGHWR_HAL_STM32_I2C2_CLOCK CYGHWR_HAL_STM32_CLOCK( APB1, I2C2 ) + + +//============================================================================= +// USB interface register definitions. + +#if defined(CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1) + +#define CYGHWR_HAL_STM32_USB_EP0R 0x00 +#define CYGHWR_HAL_STM32_USB_EP1R 0x04 +#define CYGHWR_HAL_STM32_USB_EP2R 0x08 +#define CYGHWR_HAL_STM32_USB_EP3R 0x0C +#define CYGHWR_HAL_STM32_USB_EP4R 0x10 +#define CYGHWR_HAL_STM32_USB_EP5R 0x14 +#define CYGHWR_HAL_STM32_USB_EP6R 0x18 +#define CYGHWR_HAL_STM32_USB_EP7R 0x1C + +#define CYGHWR_HAL_STM32_USB_CNTR 0x40 +#define CYGHWR_HAL_STM32_USB_ISTR 0x44 +#define CYGHWR_HAL_STM32_USB_FNR 0x48 +#define CYGHWR_HAL_STM32_USB_DADDR 0x4C +#define CYGHWR_HAL_STM32_USB_BTABLE 0x50 + +// The following macro allows the USB endpoint registers to be indexed as +// CYGHWR_HAL_STM32_USB_EPXR(0) to CYGHWR_HAL_STM32_USB_EPXR(7). +#define CYGHWR_HAL_STM32_USB_EPXR(__x) ((__x)*4) + +#define CYGHWR_HAL_STM32_USB_EPXR_EA(__x) VALUE_(0,(__x)) +#define CYGHWR_HAL_STM32_USB_EPXR_STATTX_DIS VALUE_(4,0) +#define CYGHWR_HAL_STM32_USB_EPXR_STATTX_STALL VALUE_(4,1) +#define CYGHWR_HAL_STM32_USB_EPXR_STATTX_NAK VALUE_(4,2) +#define CYGHWR_HAL_STM32_USB_EPXR_STATTX_VALID VALUE_(4,3) +#define CYGHWR_HAL_STM32_USB_EPXR_STATTX_MASK VALUE_(4,3) +#define CYGHWR_HAL_STM32_USB_EPXR_DTOGTX BIT_(6) +#define CYGHWR_HAL_STM32_USB_EPXR_SWBUFRX BIT_(6) +#define CYGHWR_HAL_STM32_USB_EPXR_CTRTX BIT_(7) +#define CYGHWR_HAL_STM32_USB_EPXR_EPKIND BIT_(8) +#define CYGHWR_HAL_STM32_USB_EPXR_EPTYPE_BULK VALUE_(9,0) +#define CYGHWR_HAL_STM32_USB_EPXR_EPTYPE_CTRL VALUE_(9,1) +#define CYGHWR_HAL_STM32_USB_EPXR_EPTYPE_ISO VALUE_(9,2) +#define CYGHWR_HAL_STM32_USB_EPXR_EPTYPE_INTR VALUE_(9,3) +#define CYGHWR_HAL_STM32_USB_EPXR_EPTYPE_MASK VALUE_(9,3) +#define CYGHWR_HAL_STM32_USB_EPXR_SETUP BIT_(11) +#define CYGHWR_HAL_STM32_USB_EPXR_STATRX_DIS VALUE_(12,0) +#define CYGHWR_HAL_STM32_USB_EPXR_STATRX_STALL VALUE_(12,1) +#define CYGHWR_HAL_STM32_USB_EPXR_STATRX_NAK VALUE_(12,2) +#define CYGHWR_HAL_STM32_USB_EPXR_STATRX_VALID VALUE_(12,3) +#define CYGHWR_HAL_STM32_USB_EPXR_STATRX_MASK VALUE_(12,3) +#define CYGHWR_HAL_STM32_USB_EPXR_DTOGRX BIT_(14) +#define CYGHWR_HAL_STM32_USB_EPXR_SWBUFTX BIT_(14) +#define CYGHWR_HAL_STM32_USB_EPXR_CTRRX BIT_(15) + +#define CYGHWR_HAL_STM32_USB_CNTR_FRES BIT_(0) +#define CYGHWR_HAL_STM32_USB_CNTR_PDWN BIT_(1) +#define CYGHWR_HAL_STM32_USB_CNTR_LPMODE BIT_(2) +#define CYGHWR_HAL_STM32_USB_CNTR_FSUSP BIT_(3) +#define CYGHWR_HAL_STM32_USB_CNTR_RESUME BIT_(4) +#define CYGHWR_HAL_STM32_USB_CNTR_ESOFM BIT_(8) +#define CYGHWR_HAL_STM32_USB_CNTR_SOFM BIT_(9) +#define CYGHWR_HAL_STM32_USB_CNTR_RESETM BIT_(10) +#define CYGHWR_HAL_STM32_USB_CNTR_SUSPM BIT_(11) +#define CYGHWR_HAL_STM32_USB_CNTR_WKUPM BIT_(12) +#define CYGHWR_HAL_STM32_USB_CNTR_ERRM BIT_(13) +#define CYGHWR_HAL_STM32_USB_CNTR_PMAOVRM BIT_(14) +#define CYGHWR_HAL_STM32_USB_CNTR_CTRM BIT_(15) + +#define CYGHWR_HAL_STM32_USB_ISTR_EPID(__x) VALUE_(0,(__x)) +#define CYGHWR_HAL_STM32_USB_ISTR_EPID_MASK MASK_(0,4) +#define CYGHWR_HAL_STM32_USB_ISTR_DIR BIT_(4) +#define CYGHWR_HAL_STM32_USB_ISTR_ESOF BIT_(8) +#define CYGHWR_HAL_STM32_USB_ISTR_SOF BIT_(9) +#define CYGHWR_HAL_STM32_USB_ISTR_RESET BIT_(10) +#define CYGHWR_HAL_STM32_USB_ISTR_SUSP BIT_(11) +#define CYGHWR_HAL_STM32_USB_ISTR_WKUP BIT_(12) +#define CYGHWR_HAL_STM32_USB_ISTR_ERR BIT_(13) +#define CYGHWR_HAL_STM32_USB_ISTR_PMAOVR BIT_(14) +#define CYGHWR_HAL_STM32_USB_ISTR_CTR BIT_(15) + +#define CYGHWR_HAL_STM32_USB_FNR_FN_MASK MASK_(0,11) +#define CYGHWR_HAL_STM32_USB_FNR_LSOF_LSOF0 VALUE_(11,0) +#define CYGHWR_HAL_STM32_USB_FNR_LSOF_LSOF1 VALUE_(11,1) +#define CYGHWR_HAL_STM32_USB_FNR_LSOF_LSOF2 VALUE_(11,2) +#define CYGHWR_HAL_STM32_USB_FNR_LSOF_LSOFN VALUE_(11,3) +#define CYGHWR_HAL_STM32_USB_FNR_LSOF_MASK MASK_(11,2) +#define CYGHWR_HAL_STM32_USB_FNR_LCK BIT_(13) +#define CYGHWR_HAL_STM32_USB_FNR_RXDM BIT_(14) +#define CYGHWR_HAL_STM32_USB_FNR_RXDP BIT_(15) + +#define CYGHWR_HAL_STM32_USB_DADDR_ADD(__x) VALUE_(0,(__x)) +#define CYGHWR_HAL_STM32_USB_DADDR_EF BIT_(7) + +#define CYGHWR_HAL_STM32_USB_CLOCK CYGHWR_HAL_STM32_CLOCK( APB1, USB ) + +#endif // if defined(CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1) + +// USB in F2/F4 parts is completely different. Definitions will be provided when implemented. + +//============================================================================= +// Timers +// +// This currently only defines the basic registers and functionality +// common to all timers. + +#define CYGHWR_HAL_STM32_TIM_CR1 0x00 +#define CYGHWR_HAL_STM32_TIM_CR2 0x04 +#define CYGHWR_HAL_STM32_TIM_DIER 0x0C +#define CYGHWR_HAL_STM32_TIM_SR 0x10 +#define CYGHWR_HAL_STM32_TIM_EGR 0x14 +#define CYGHWR_HAL_STM32_TIM_CCMR1 0x18 +#define CYGHWR_HAL_STM32_TIM_CCMR2 0x1C +#define CYGHWR_HAL_STM32_TIM_CCER 0x20 +#define CYGHWR_HAL_STM32_TIM_CNT 0x24 +#define CYGHWR_HAL_STM32_TIM_PSC 0x28 +#define CYGHWR_HAL_STM32_TIM_ARR 0x2C +#define CYGHWR_HAL_STM32_TIM_CCR1 0x34 +#define CYGHWR_HAL_STM32_TIM_CCR2 0x38 +#define CYGHWR_HAL_STM32_TIM_CCR3 0x3C +#define CYGHWR_HAL_STM32_TIM_CCR4 0x40 + +#define CYGHWR_HAL_STM32_TIM_CR1_CEN BIT_(0) +#define CYGHWR_HAL_STM32_TIM_CR1_UDIS BIT_(1) +#define CYGHWR_HAL_STM32_TIM_CR1_URS BIT_(2) +#define CYGHWR_HAL_STM32_TIM_CR1_OPM BIT_(3) +#define CYGHWR_HAL_STM32_TIM_CR1_DIR BIT_(4) +#define CYGHWR_HAL_STM32_TIM_CR1_ARPE BIT_(7) +#define CYGHWR_HAL_STM32_TIM_CR1_CKD_1 VALUE_(8,0) +#define CYGHWR_HAL_STM32_TIM_CR1_CKD_2 VALUE_(8,1) +#define CYGHWR_HAL_STM32_TIM_CR1_CKD_4 VALUE_(8,2) +#define CYGHWR_HAL_STM32_TIM_CR1_CKD_XXX VALUE_(8,3) + +#define CYGHWR_HAL_STM32_TIM_CR2_MMS_RESET VALUE_(4,0) +#define CYGHWR_HAL_STM32_TIM_CR2_MMS_ENABLE VALUE_(4,1) +#define CYGHWR_HAL_STM32_TIM_CR2_MMS_UPDATE VALUE_(4,2) + +#define CYGHWR_HAL_STM32_TIM_DIER_UIE BIT_(0) +#define CYGHWR_HAL_STM32_TIM_DIER_UDE BIT_(8) + +#define CYGHWR_HAL_STM32_TIM_SR_UIF BIT_(0) + +#define CYGHWR_HAL_STM32_TIM_EGR_UG BIT_(0) + +// Clock control pins +#define CYGHWR_HAL_STM32_TIM1_CLOCK CYGHWR_HAL_STM32_CLOCK( APB2, TIM1 ) +#define CYGHWR_HAL_STM32_TIM2_CLOCK CYGHWR_HAL_STM32_CLOCK( APB1, TIM2 ) +#define CYGHWR_HAL_STM32_TIM3_CLOCK CYGHWR_HAL_STM32_CLOCK( APB1, TIM3 ) +#define CYGHWR_HAL_STM32_TIM4_CLOCK CYGHWR_HAL_STM32_CLOCK( APB1, TIM4 ) +#define CYGHWR_HAL_STM32_TIM5_CLOCK CYGHWR_HAL_STM32_CLOCK( APB1, TIM5 ) +#define CYGHWR_HAL_STM32_TIM6_CLOCK CYGHWR_HAL_STM32_CLOCK( APB1, TIM6 ) +#define CYGHWR_HAL_STM32_TIM7_CLOCK CYGHWR_HAL_STM32_CLOCK( APB1, TIM7 ) +#define CYGHWR_HAL_STM32_TIM8_CLOCK CYGHWR_HAL_STM32_CLOCK( APB2, TIM8 ) +#if 0 +#define CYGHWR_HAL_STM32_TIM9_CLOCK CYGHWR_HAL_STM32_CLOCK( APB2, TIM9 ) +#define CYGHWR_HAL_STM32_TIM10_CLOCK CYGHWR_HAL_STM32_CLOCK( APB2, TIM10 ) +#define CYGHWR_HAL_STM32_TIM11_CLOCK CYGHWR_HAL_STM32_CLOCK( APB2, TIM11 ) +#define CYGHWR_HAL_STM32_TIM12_CLOCK CYGHWR_HAL_STM32_CLOCK( APB1, TIM12 ) +#define CYGHWR_HAL_STM32_TIM13_CLOCK CYGHWR_HAL_STM32_CLOCK( APB1, TIM13 ) +#define CYGHWR_HAL_STM32_TIM14_CLOCK CYGHWR_HAL_STM32_CLOCK( APB1, TIM14 ) +#endif + +#ifndef __ASSEMBLER__ + +__externC cyg_uint32 hal_stm32_timer_clock( CYG_ADDRESS base ); + +#endif + +//============================================================================= +// Independent Watchdog + +#define CYGHWR_HAL_STM32_IWDG_KR 0x00 +#define CYGHWR_HAL_STM32_IWDG_PR 0x04 +#define CYGHWR_HAL_STM32_IWDG_RLR 0x08 +#define CYGHWR_HAL_STM32_IWDG_SR 0x0C + +#define CYGHWR_HAL_STM32_IWDG_KR_RESET 0xAAAA +#define CYGHWR_HAL_STM32_IWDG_KR_ACCESS 0x5555 +#define CYGHWR_HAL_STM32_IWDG_KR_START 0xCCCC + +#define CYGHWR_HAL_STM32_IWDG_PR_4 0 +#define CYGHWR_HAL_STM32_IWDG_PR_8 1 +#define CYGHWR_HAL_STM32_IWDG_PR_16 2 +#define CYGHWR_HAL_STM32_IWDG_PR_32 3 +#define CYGHWR_HAL_STM32_IWDG_PR_64 4 +#define CYGHWR_HAL_STM32_IWDG_PR_128 5 +#define CYGHWR_HAL_STM32_IWDG_PR_256 6 + +#define CYGHWR_HAL_STM32_IWDG_SR_PVU BIT_(0) +#define CYGHWR_HAL_STM32_IWDG_SR_RVU BIT_(1) + +// Clock control + +//#define CYGHWR_HAL_STM32_IWDG_CLOCK CYGHWR_HAL_STM32_CLOCK( APB1, IWDG ) + + +//============================================================================= +// Flash controller + +#define CYGHWR_HAL_STM32_FLASH_ACR 0x00 +#define CYGHWR_HAL_STM32_FLASH_KEYR 0x04 +#define CYGHWR_HAL_STM32_FLASH_OPTKEYR 0x08 +#define CYGHWR_HAL_STM32_FLASH_SR 0x0C +#define CYGHWR_HAL_STM32_FLASH_CR 0x10 +#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1) +#define CYGHWR_HAL_STM32_FLASH_AR 0x14 +#define CYGHWR_HAL_STM32_FLASH_OBR 0x1C +#define CYGHWR_HAL_STM32_FLASH_WRPR 0x20 +#elif defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE) +#define CYGHWR_HAL_STM32_FLASH_OPTCR 0x14 +#endif // elif defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE) + +// Key values + +#define CYGHWR_HAL_STM32_FLASH_KEYR_KEY1 0x45670123 +#define CYGHWR_HAL_STM32_FLASH_KEYR_KEY2 0xCDEF89AB + +// ACR fields + +#define CYGHWR_HAL_STM32_FLASH_ACR_LATENCY(__x) VALUE_(0,__x) +#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1) + +#define CYGHWR_HAL_STM32_FLASH_ACR_HLFCYA BIT_(3) +#define CYGHWR_HAL_STM32_FLASH_ACR_PRFTBE BIT_(4) +#define CYGHWR_HAL_STM32_FLASH_ACR_PRFTBS BIT_(5) + +#elif defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE) + +#define CYGHWR_HAL_STM32_FLASH_ACR_PRFTEN BIT_(8) +#define CYGHWR_HAL_STM32_FLASH_ACR_ICEN BIT_(9) +#define CYGHWR_HAL_STM32_FLASH_ACR_DCEN BIT_(10) +#define CYGHWR_HAL_STM32_FLASH_ACR_ICRST BIT_(11) +#define CYGHWR_HAL_STM32_FLASH_ACR_DCRST BIT_(12) + +#endif // if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE) + +// SR fields + +#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1) + +#define CYGHWR_HAL_STM32_FLASH_SR_BSY BIT_(0) +#define CYGHWR_HAL_STM32_FLASH_SR_PGERR BIT_(2) +#define CYGHWR_HAL_STM32_FLASH_SR_WRPRTERR BIT_(4) +#define CYGHWR_HAL_STM32_FLASH_SR_EOP BIT_(5) + +#elif defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE) + +#define CYGHWR_HAL_STM32_FLASH_SR_EOP BIT_(0) +#define CYGHWR_HAL_STM32_FLASH_SR_OPERR BIT_(1) +#define CYGHWR_HAL_STM32_FLASH_SR_WRPERR BIT_(4) +#define CYGHWR_HAL_STM32_FLASH_SR_PGAERR BIT_(5) +#define CYGHWR_HAL_STM32_FLASH_SR_PGPERR BIT_(6) +#define CYGHWR_HAL_STM32_FLASH_SR_PGSERR BIT_(7) +#define CYGHWR_HAL_STM32_FLASH_SR_BSY BIT_(16) + +#endif // elif defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE) + +// CR fields + +#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1) + +#define CYGHWR_HAL_STM32_FLASH_CR_PG BIT_(0) +#define CYGHWR_HAL_STM32_FLASH_CR_PER BIT_(1) +#define CYGHWR_HAL_STM32_FLASH_CR_MER BIT_(2) +#define CYGHWR_HAL_STM32_FLASH_CR_OPTPG BIT_(4) +#define CYGHWR_HAL_STM32_FLASH_CR_OPTER BIT_(5) +#define CYGHWR_HAL_STM32_FLASH_CR_STRT BIT_(6) +#define CYGHWR_HAL_STM32_FLASH_CR_LOCK BIT_(7) +#define CYGHWR_HAL_STM32_FLASH_CR_OPTWRE BIT_(9) +#define CYGHWR_HAL_STM32_FLASH_CR_ERRIE BIT_(10) +#define CYGHWR_HAL_STM32_FLASH_CR_EOPIE BIT_(12) + +#elif defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE) + +#define CYGHWR_HAL_STM32_FLASH_CR_PG BIT_(0) +#define CYGHWR_HAL_STM32_FLASH_CR_SER BIT_(1) +#define CYGHWR_HAL_STM32_FLASH_CR_MER BIT_(2) +#define CYGHWR_HAL_STM32_FLASH_CR_SNB(__x) (((__x)&0xf) << 3) +#define CYGHWR_HAL_STM32_FLASH_CR_SNB_MASK MASK_(3,4) +#define CYGHWR_HAL_STM32_FLASH_CR_PSIZE(__x) ( (__x) == 8 ? VALUE_(8,0) : \ + (__x) == 16 ? VALUE_(8,1) : \ + (__x) == 32 ? VALUE_(8,2) : \ + VALUE_(8,3) ) +#define CYGHWR_HAL_STM32_FLASH_CR_PSIZE_8 VALUE_(8,0) +#define CYGHWR_HAL_STM32_FLASH_CR_PSIZE_16 VALUE_(8,1) +#define CYGHWR_HAL_STM32_FLASH_CR_PSIZE_32 VALUE_(8,2) +#define CYGHWR_HAL_STM32_FLASH_CR_PSIZE_64 VALUE_(8,3) +#define CYGHWR_HAL_STM32_FLASH_CR_STRT BIT_(16) +#define CYGHWR_HAL_STM32_FLASH_CR_EOPIE BIT_(24) +#define CYGHWR_HAL_STM32_FLASH_CR_ERRIE BIT_(25) +#define CYGHWR_HAL_STM32_FLASH_CR_LOCK BIT_(31) + +#endif // elif defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE) + +// OBR fields +#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1) +#define CYGHWR_HAL_STM32_FLASH_OBR_OPTERR BIT_(0) +#define CYGHWR_HAL_STM32_FLASH_OBR_RDPRT BIT_(1) +#define CYGHWR_HAL_STM32_FLASH_OBR_WDG_SW BIT_(2) +#define CYGHWR_HAL_STM32_FLASH_OBR_nRST_STOP BIT_(3) +#define CYGHWR_HAL_STM32_FLASH_OBR_nRST_STDBY BIT_(4) +#endif + +// F2/F4 FLASH_OPTCR not defined as our flash driver doesn't use it. + +//============================================================================= +// Power control + +#define CYGHWR_HAL_STM32_PWR_CR 0x00 +#define CYGHWR_HAL_STM32_PWR_CSR 0x04 + +// CR fields + +#define CYGHWR_HAL_STM32_PWR_CR_LPDS BIT_(0) +#define CYGHWR_HAL_STM32_PWR_CR_PDDS BIT_(1) +#define CYGHWR_HAL_STM32_PWR_CR_CWUF BIT_(2) +#define CYGHWR_HAL_STM32_PWR_CR_CSBF BIT_(3) +#define CYGHWR_HAL_STM32_PWR_CR_PVDE BIT_(4) +#define CYGHWR_HAL_STM32_PWR_CR_PLS_XXX VALUE_(5,7) +#define CYGHWR_HAL_STM32_PWR_CR_DBP BIT_(8) +#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE) +#define CYGHWR_HAL_STM32_PWR_CR_FPDS BIT_(9) +#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F4) +#define CYGHWR_HAL_STM32_PWR_CR_VOS BIT_(14) +#endif // (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F4 +#endif // CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE + +// CSR fields + +#define CYGHWR_HAL_STM32_PWR_CSR_WUF BIT_(0) +#define CYGHWR_HAL_STM32_PWR_CSR_SBF BIT_(1) +#define CYGHWR_HAL_STM32_PWR_CSR_PVDO BIT_(2) +#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE) +#define CYGHWR_HAL_STM32_PWR_CSR_BRR BIT_(3) +#endif +#define CYGHWR_HAL_STM32_PWR_CSR_EWUP BIT_(8) +#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE) +#define CYGHWR_HAL_STM32_PWR_CSR_BRE BIT_(9) +#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F4) +#define CYGHWR_HAL_STM32_PWR_CSR_VOSRDY BIT_(14) +#endif // CYGHWR_HAL_CORTEXM_STM32_FAMILY_F4 +#endif // CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE + +// Functions and macros to reset the backup domain as well as +// enable/disable backup domain write protection. + +#ifndef __ASSEMBLER__ + +__externC void hal_stm32_bd_protect( int protect ); + +#endif + +#define CYGHWR_HAL_STM32_BD_RESET() \ + CYG_MACRO_START \ + HAL_WRITE_UINT32(CYGHWR_HAL_STM32_RCC+CYGHWR_HAL_STM32_RCC_BDCR, \ + CYGHWR_HAL_STM32_RCC_BDCR_BDRST); \ + HAL_WRITE_UINT32(CYGHWR_HAL_STM32_RCC+CYGHWR_HAL_STM32_RCC_BDCR, 0); \ + CYG_MACRO_END + +#define CYGHWR_HAL_STM32_BD_PROTECT(__protect ) \ + hal_stm32_bd_protect( __protect ) + +//============================================================================= +// FSMC +// +// These registers are usually set up in hal_system_init() using direct +// binary values. Hence we don't define all the fields here (of which +// there are many). + +#define CYGHWR_HAL_STM32_FSMC_BCR1 0x00 +#define CYGHWR_HAL_STM32_FSMC_BTR1 0x04 +#define CYGHWR_HAL_STM32_FSMC_BCR2 0x08 +#define CYGHWR_HAL_STM32_FSMC_BTR2 0x0C +#define CYGHWR_HAL_STM32_FSMC_BCR3 0x10 +#define CYGHWR_HAL_STM32_FSMC_BTR3 0x14 +#define CYGHWR_HAL_STM32_FSMC_BCR4 0x18 +#define CYGHWR_HAL_STM32_FSMC_BTR4 0x1C + +#define CYGHWR_HAL_STM32_FSMC_BWTR1 0x104 +#define CYGHWR_HAL_STM32_FSMC_BWTR2 0x10C +#define CYGHWR_HAL_STM32_FSMC_BWTR3 0x114 +#define CYGHWR_HAL_STM32_FSMC_BWTR4 0x11C + +#define CYGHWR_HAL_STM32_FSMC_PCR2 0x60 +#define CYGHWR_HAL_STM32_FSMC_SR2 0x64 +#define CYGHWR_HAL_STM32_FSMC_PMEM2 0x68 +#define CYGHWR_HAL_STM32_FSMC_PATT2 0x6C +#define CYGHWR_HAL_STM32_FSMC_ECCR2 0x74 + +#define CYGHWR_HAL_STM32_FSMC_PCR3 0x80 +#define CYGHWR_HAL_STM32_FSMC_SR3 0x84 +#define CYGHWR_HAL_STM32_FSMC_PMEM3 0x88 +#define CYGHWR_HAL_STM32_FSMC_PATT3 0x8C +#define CYGHWR_HAL_STM32_FSMC_ECCR3 0x94 + +#define CYGHWR_HAL_STM32_FSMC_PCR4 0xA0 +#define CYGHWR_HAL_STM32_FSMC_SR4 0xA4 +#define CYGHWR_HAL_STM32_FSMC_PMEM4 0xA8 +#define CYGHWR_HAL_STM32_FSMC_PATT4 0xAC + +#define CYGHWR_HAL_STM32_FSMC_PIO4 0xB0 + +#define CYGHWR_HAL_STM32_FSMC_BANK1_BASE 0x60000000 +#define CYGHWR_HAL_STM32_FSMC_BANK2_BASE 0x70000000 +#define CYGHWR_HAL_STM32_FSMC_BANK3_BASE 0x80000000 +#define CYGHWR_HAL_STM32_FSMC_BANK4_BASE 0x90000000 + +#define CYGHWR_HAL_STM32_FSMC_BANK_CMD 0x10000 +#define CYGHWR_HAL_STM32_FSMC_BANK_ADDR 0x20000 + +// PCR fields + +#define CYGHWR_HAL_STM32_FSMC_PCR_PWAITEN BIT_(1) +#define CYGHWR_HAL_STM32_FSMC_PCR_PBKEN BIT_(2) +#define CYGHWR_HAL_STM32_FSMC_PCR_PTYP_NAND BIT_(3) +#define CYGHWR_HAL_STM32_FSMC_PCR_PWID_8 VALUE_(4,0) +#define CYGHWR_HAL_STM32_FSMC_PCR_PWID_16 VALUE_(4,1) +#define CYGHWR_HAL_STM32_FSMC_PCR_ECCEN BIT_(6) +// FIXME: I don't see where ADLOW comes from? It's not in F1, F2 or F4. -Jifl +#define CYGHWR_HAL_STM32_FSMC_PCR_ADLOW BIT_(8) +#define CYGHWR_HAL_STM32_FSMC_PCR_TCLR(__x) VALUE_(9,__x) +#define CYGHWR_HAL_STM32_FSMC_PCR_TAR(__x) VALUE_(13,__x) +#define CYGHWR_HAL_STM32_FSMC_PCR_ECCPS_256 VALUE_(17,0) +#define CYGHWR_HAL_STM32_FSMC_PCR_ECCPS_512 VALUE_(17,1) +#define CYGHWR_HAL_STM32_FSMC_PCR_ECCPS_1024 VALUE_(17,2) +#define CYGHWR_HAL_STM32_FSMC_PCR_ECCPS_2048 VALUE_(17,3) +#define CYGHWR_HAL_STM32_FSMC_PCR_ECCPS_4096 VALUE_(17,4) +#define CYGHWR_HAL_STM32_FSMC_PCR_ECCPS_8192 VALUE_(17,5) + +// SR fields + +#define CYGHWR_HAL_STM32_FSMC_SR_IRS BIT_(0) +#define CYGHWR_HAL_STM32_FSMC_SR_ILS BIT_(1) +#define CYGHWR_HAL_STM32_FSMC_SR_IFS BIT_(2) +#define CYGHWR_HAL_STM32_FSMC_SR_IREN BIT_(3) +#define CYGHWR_HAL_STM32_FSMC_SR_ILEN BIT_(4) +#define CYGHWR_HAL_STM32_FSMC_SR_IFEN BIT_(5) +#define CYGHWR_HAL_STM32_FSMC_SR_FEMPT BIT_(6) + +//============================================================================= +// CAN +// + +#define CYGHWR_HAL_STM32_CAN1_CLOCK CYGHWR_HAL_STM32_CLOCK( APB1, CAN1 ) +#define CYGHWR_HAL_STM32_CAN2_CLOCK CYGHWR_HAL_STM32_CLOCK( APB1, CAN2 ) + + +//============================================================================= +// Ethernet MAC +// Include separate header file for this to avoid this header getting unmanageable. + +#include <cyg/hal/var_io_eth.h> + +//========================================================================== + +#if (defined(CYGHWR_HAL_CORTEXM_STM32_F1_F103RC) || \ + defined(CYGHWR_HAL_CORTEXM_STM32_F1_F103VC) || \ + defined(CYGHWR_HAL_CORTEXM_STM32_F1_F103ZC) || \ + defined(CYGHWR_HAL_CORTEXM_STM32_F1_F103RD) || \ + defined(CYGHWR_HAL_CORTEXM_STM32_F1_F103VD) || \ + defined(CYGHWR_HAL_CORTEXM_STM32_F1_F103ZD) || \ + defined(CYGHWR_HAL_CORTEXM_STM32_F1_F103RE) || \ + defined(CYGHWR_HAL_CORTEXM_STM32_F1_F103VE) || \ + defined(CYGHWR_HAL_CORTEXM_STM32_F1_F103ZE)) +// NOTE: From ST document ES0104 (STM32F101xC/D/E and STM32F103xC/D/E) +// errata section 2.6.9 we cannot use FSMC and I2C1 at the same time. +// For I2C1 support we are limited to on-chip SRAM/Flash execution and +// must ensure that FSMC is disabled. +# if (defined(CYG_HAL_STARTUP_SRAM) || \ + defined(CYG_HAL_STARTUP_ROM) || \ + defined(CYG_HAL_STARTUP_JTAG)) +# define HAL_AARDVARK_CHECK_I2C( _i2cdev_ ) \ + CYG_MACRO_START \ + if ((_i2cdev_)->i2c_bus == &hal_stm32_i2c_bus1) { \ + CYGHWR_HAL_STM32_CLOCK_DISABLE( CYGHWR_HAL_STM32_CLOCK( AHB, FSMC) ); \ + } \ + CYG_MACRO_END +# else // on this CPU we cannot use I2C1 since FSMC needed for the CYG_HAL_STARTUP type +# define HAL_AARDVARK_CHECK_I2C( _i2cdev_ ) \ + CYG_MACRO_START \ + if ((_i2cdev_)->i2c_bus == &hal_stm32_i2c_bus1) { \ + CYG_TEST_FAIL_FINISH("Invalid CYG_HAL_STARTUP for I2C1 operations"); \ + } \ + CYG_MACRO_END +# endif +#endif + +//========================================================================== + +#endif // CYGONCE_HAL_VAR_IO_H +//----------------------------------------------------------------------------- +// end of var_io.h diff --git a/ecos/packages/hal/cortexm/stm32/var/current/include/var_io_eth.h b/ecos/packages/hal/cortexm/stm32/var/current/include/var_io_eth.h new file mode 100644 index 0000000..a5ab5fa --- /dev/null +++ b/ecos/packages/hal/cortexm/stm32/var/current/include/var_io_eth.h @@ -0,0 +1,490 @@ +#ifndef CYGONCE_HAL_VAR_IO_ETH_H +#define CYGONCE_HAL_VAR_IO_ETH_H +//============================================================================= +// +// var_io_eth.h +// +// Ethernet-specific variant definitions +// +//============================================================================= +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2008, 2009, 2011 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): nickg, jlarmour +// Date: 2008-07-30 +// Purpose: STM32 variant ETH specific registers +// Description: +// Usage: Do not include this header file directly. Instead: +// #include <cyg/hal/var_io.h> +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +#ifndef CYGONCE_HAL_VAR_IO_H +# error Do not include var_io_eth.h directly, use var_io.h +#endif + + +//============================================================================= +// Ethernet MAC +// +// Connectivity devices only + +#ifdef CYGHWR_HAL_CORTEXM_STM32_CONNECTIVITY + +#define CYGHWR_HAL_STM32_ETH_MACCR 0x0000 +#define CYGHWR_HAL_STM32_ETH_MACFFR 0x0004 +#define CYGHWR_HAL_STM32_ETH_MACHTHR 0x0008 +#define CYGHWR_HAL_STM32_ETH_MACHTLR 0x000C +#define CYGHWR_HAL_STM32_ETH_MACMIIAR 0x0010 +#define CYGHWR_HAL_STM32_ETH_MACMIIDR 0x0014 +#define CYGHWR_HAL_STM32_ETH_MACFCR 0x0018 +#define CYGHWR_HAL_STM32_ETH_MACVLANTR 0x001C +#define CYGHWR_HAL_STM32_ETH_MACRWUFFR 0x0028 +#define CYGHWR_HAL_STM32_ETH_MACPMTCSR 0x002C +#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE) +#define CYGHWR_HAL_STM32_ETH_MACDBGR 0x0034 +#endif +#define CYGHWR_HAL_STM32_ETH_MACSR 0x0038 +#define CYGHWR_HAL_STM32_ETH_MACIMR 0x003C +#define CYGHWR_HAL_STM32_ETH_MACA0HR 0x0040 +#define CYGHWR_HAL_STM32_ETH_MACA0LR 0x0044 +#define CYGHWR_HAL_STM32_ETH_MACA1HR 0x0048 +#define CYGHWR_HAL_STM32_ETH_MACA1LR 0x004C +#define CYGHWR_HAL_STM32_ETH_MACA2HR 0x0050 +#define CYGHWR_HAL_STM32_ETH_MACA2LR 0x0054 +#define CYGHWR_HAL_STM32_ETH_MACA3HR 0x0058 +#define CYGHWR_HAL_STM32_ETH_MACA3LR 0x005C + +#define CYGHWR_HAL_STM32_ETH_MMCCR 0x0100 +#define CYGHWR_HAL_STM32_ETH_MMCRIR 0x0104 +#define CYGHWR_HAL_STM32_ETH_MMCTIR 0x0108 +#define CYGHWR_HAL_STM32_ETH_MMCRIMR 0x010C +#define CYGHWR_HAL_STM32_ETH_MMCTIMR 0x0110 +#define CYGHWR_HAL_STM32_ETH_MMCTGFSCCR 0x014C +#define CYGHWR_HAL_STM32_ETH_MMCTGFMSCCR 0x0150 +#define CYGHWR_HAL_STM32_ETH_MMCTGFCR 0x0168 +#define CYGHWR_HAL_STM32_ETH_MMCRFCECR 0x0194 +#define CYGHWR_HAL_STM32_ETH_MMCRFAECR 0x0198 +#define CYGHWR_HAL_STM32_ETH_MMCRGUFCR 0x01C4 + +#define CYGHWR_HAL_STM32_ETH_PTPTSCR 0x0700 +#define CYGHWR_HAL_STM32_ETH_PTPSSIR 0x0704 +#define CYGHWR_HAL_STM32_ETH_PTPTSHR 0x0708 +#define CYGHWR_HAL_STM32_ETH_PTPTSLR 0x070C +#define CYGHWR_HAL_STM32_ETH_PTPTSHUR 0x0710 +#define CYGHWR_HAL_STM32_ETH_PTPTSLUR 0x0714 +#define CYGHWR_HAL_STM32_ETH_PTPTSAR 0x0718 +#define CYGHWR_HAL_STM32_ETH_PTPTTHR 0x071C +#define CYGHWR_HAL_STM32_ETH_PTPTTLR 0x0720 +#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE) +#define CYGHWR_HAL_STM32_ETH_PTPTSSR 0x0728 +#endif + +#define CYGHWR_HAL_STM32_ETH_DMABMR 0x1000 +#define CYGHWR_HAL_STM32_ETH_DMATPDR 0x1004 +#define CYGHWR_HAL_STM32_ETH_DMARPDR 0x1008 +#define CYGHWR_HAL_STM32_ETH_DMARDLAR 0x100C +#define CYGHWR_HAL_STM32_ETH_DMATDLAR 0x1010 +#define CYGHWR_HAL_STM32_ETH_DMASR 0x1014 +#define CYGHWR_HAL_STM32_ETH_DMAOMR 0x1018 +#define CYGHWR_HAL_STM32_ETH_DMAIER 0x101C +#define CYGHWR_HAL_STM32_ETH_DMAMFBOCR 0x1020 +#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE) +#define CYGHWR_HAL_STM32_ETH_DMARSWTR 0x1024 +#endif +#define CYGHWR_HAL_STM32_ETH_DMACHTDR 0x1048 +#define CYGHWR_HAL_STM32_ETH_DMACHRDR 0x104C +#define CYGHWR_HAL_STM32_ETH_DMACHTBAR 0x1050 +#define CYGHWR_HAL_STM32_ETH_DMACHRBAR 0x1054 + +// MACCR + +#define CYGHWR_HAL_STM32_ETH_MACCR_RE BIT_(2) +#define CYGHWR_HAL_STM32_ETH_MACCR_TE BIT_(3) +#define CYGHWR_HAL_STM32_ETH_MACCR_DC BIT_(4) +#define CYGHWR_HAL_STM32_ETH_MACCR_BL(__x) VALUE_(6, __x) +#define CYGHWR_HAL_STM32_ETH_MACCR_APCS BIT_(7) +#define CYGHWR_HAL_STM32_ETH_MACCR_RD BIT_(9) +#define CYGHWR_HAL_STM32_ETH_MACCR_IPCO BIT_(10) +#define CYGHWR_HAL_STM32_ETH_MACCR_DM BIT_(11) +#define CYGHWR_HAL_STM32_ETH_MACCR_LM BIT_(12) +#define CYGHWR_HAL_STM32_ETH_MACCR_ROD BIT_(13) +#define CYGHWR_HAL_STM32_ETH_MACCR_FES BIT_(14) +#define CYGHWR_HAL_STM32_ETH_MACCR_CSD BIT_(16) +#define CYGHWR_HAL_STM32_ETH_MACCR_IFG(__x) VALUE_(17, (96-(__x))/8 ) +#define CYGHWR_HAL_STM32_ETH_MACCR_JD BIT_(22) +#define CYGHWR_HAL_STM32_ETH_MACCR_WD BIT_(23) +#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE) +#define CYGHWR_HAL_STM32_ETH_MACCR_CSTF BIT_(25) +#endif + +// MACFFR + +#define CYGHWR_HAL_STM32_ETH_MACFFR_PM BIT_(0) +#define CYGHWR_HAL_STM32_ETH_MACFFR_HU BIT_(1) +#define CYGHWR_HAL_STM32_ETH_MACFFR_HM BIT_(2) +#define CYGHWR_HAL_STM32_ETH_MACFFR_DAIF BIT_(3) +#define CYGHWR_HAL_STM32_ETH_MACFFR_PAM BIT_(4) +#define CYGHWR_HAL_STM32_ETH_MACFFR_BFD BIT_(5) +#define CYGHWR_HAL_STM32_ETH_MACFFR_PCF_BLOCK VALUE_(6,0) +#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE) +#define CYGHWR_HAL_STM32_ETH_MACFFR_PCF_NOPAUSE VALUE_(6,1) +#endif +#define CYGHWR_HAL_STM32_ETH_MACFFR_PCF_ALL VALUE_(6,2) +#define CYGHWR_HAL_STM32_ETH_MACFFR_PCF_FILTER VALUE_(6,3) +#define CYGHWR_HAL_STM32_ETH_MACFFR_SAIF BIT_(8) +#define CYGHWR_HAL_STM32_ETH_MACFFR_SAF BIT_(9) +#define CYGHWR_HAL_STM32_ETH_MACFFR_HPF BIT_(10) +#define CYGHWR_HAL_STM32_ETH_MACFFR_RA BIT_(31) + +// MACHT* omitted + +// MACMIIAR + +#define CYGHWR_HAL_STM32_ETH_MACMIIAR_MB BIT_(0) +#define CYGHWR_HAL_STM32_ETH_MACMIIAR_MW BIT_(1) +#define CYGHWR_HAL_STM32_ETH_MACMIIAR_CR(__x) VALUE_(2,__x) +#define CYGHWR_HAL_STM32_ETH_MACMIIAR_CR_MASK MASK_(2,4) + +#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1) +# define CYGHWR_HAL_STM32_ETH_MACMIIAR_CR_MHZ_CHECK(_mhz) ((_mhz) >= 20 && (_mhz) <= 72) +#elif defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F2) +# define CYGHWR_HAL_STM32_ETH_MACMIIAR_CR_MHZ_CHECK(_mhz) ((_mhz) >= 20 && (_mhz) <= 120) +#elif defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F4) +# define CYGHWR_HAL_STM32_ETH_MACMIIAR_CR_MHZ_CHECK(_mhz) ((_mhz) >= 20 && (_mhz) <= 168) +#endif +// This macro is shared between F1/F2/F4 families for now (despite +// irrelevance for >72Mhz speed, but that's checked above) but it's +// foreseeable that this could change for future products. +# define CYGHWR_HAL_STM32_ETH_MACMIIAR_CR_MHZ(_mhz) ( \ + ((_mhz) >= 150) ? CYGHWR_HAL_STM32_ETH_MACMIIAR_CR(4) : \ + ((_mhz) >= 100) ? CYGHWR_HAL_STM32_ETH_MACMIIAR_CR(1) : \ + ((_mhz) >= 60) ? CYGHWR_HAL_STM32_ETH_MACMIIAR_CR(0) : \ + ((_mhz) >= 35) ? CYGHWR_HAL_STM32_ETH_MACMIIAR_CR(3) : \ + /*((_mhz) >= 20) ?*/ CYGHWR_HAL_STM32_ETH_MACMIIAR_CR(2)) + +#define CYGHWR_HAL_STM32_ETH_MACMIIAR_MR(__x) VALUE_(6,__x) +#define CYGHWR_HAL_STM32_ETH_MACMIIAR_PA(__x) VALUE_(11,__x) + +// MACFCR omitted +// MACVLANTR omitted +// MACRWUFFR omitted +// MACPMTCSR omitted +// MACDBGR (F2/F4 only) omitted + +// MACSR + +#define CYGHWR_HAL_STM32_ETH_MACSR_PMTS BIT_(3) +#define CYGHWR_HAL_STM32_ETH_MACSR_MMCS BIT_(4) +#define CYGHWR_HAL_STM32_ETH_MACSR_MMCRS BIT_(5) +#define CYGHWR_HAL_STM32_ETH_MACSR_MMCTS BIT_(6) +#define CYGHWR_HAL_STM32_ETH_MACSR_TSTS BIT_(9) + +// MACIMR + +#define CYGHWR_HAL_STM32_ETH_MACIMR_PMTIM BIT_(3) +#define CYGHWR_HAL_STM32_ETH_MACIMR_TSTIM BIT_(9) + +// MMCR + +#define CYGHWR_HAL_STM32_ETH_MMCCR_CR BIT_(0) +#define CYGHWR_HAL_STM32_ETH_MMCCR_CSR BIT_(1) +#define CYGHWR_HAL_STM32_ETH_MMCCR_ROR BIT_(2) +#define CYGHWR_HAL_STM32_ETH_MMCCR_MCF BIT_(3) +#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE) +#define CYGHWR_HAL_STM32_ETH_MMCCR_MCP BIT_(4) +#define CYGHWR_HAL_STM32_ETH_MMCCR_MCFHP BIT_(5) +#endif + +// MMCRIR & MMCRIMR + +#define CYGHWR_HAL_STM32_ETH_MMCRIR_RFCES BIT_(5) +#define CYGHWR_HAL_STM32_ETH_MMCRIR_RFAES BIT_(6) +#define CYGHWR_HAL_STM32_ETH_MMCRIR_RGUFS BIT_(17) + +// MMCTIR & MMCTIMR + +#define CYGHWR_HAL_STM32_ETH_MMCTIR_TGFSCS BIT_(14) +#define CYGHWR_HAL_STM32_ETH_MMCTIR_TGFMSCS BIT_(15) +#define CYGHWR_HAL_STM32_ETH_MMCTIR_TGFS BIT_(21) + +// PTP* omitted + +// DMABMR + +#define CYGHWR_HAL_STM32_ETH_DMABMR_SR BIT_(0) +#define CYGHWR_HAL_STM32_ETH_DMABMR_DA BIT_(1) +#define CYGHWR_HAL_STM32_ETH_DMABMR_DSL(__x) VALUE_(2,__x) +#define CYGHWR_HAL_STM32_ETH_DMABMR_PBL(__x) VALUE_(8,__x) +#define CYGHWR_HAL_STM32_ETH_DMABMR_RTPR(__x) VALUE_(14,(__x)-1) +#define CYGHWR_HAL_STM32_ETH_DMABMR_FB BIT_(16) +#define CYGHWR_HAL_STM32_ETH_DMABMR_RDP(__x) VALUE_(17,__x) +#define CYGHWR_HAL_STM32_ETH_DMABMR_USP BIT_(23) +#define CYGHWR_HAL_STM32_ETH_DMABMR_FPM BIT_(24) +#define CYGHWR_HAL_STM32_ETH_DMABMR_AAB BIT_(25) + +//DMASR + +#define CYGHWR_HAL_STM32_ETH_DMASR_TS BIT_(0) +#define CYGHWR_HAL_STM32_ETH_DMASR_TPSS BIT_(1) +#define CYGHWR_HAL_STM32_ETH_DMASR_TBUS BIT_(2) +#define CYGHWR_HAL_STM32_ETH_DMASR_TJTS BIT_(3) +#define CYGHWR_HAL_STM32_ETH_DMASR_ROS BIT_(4) +#define CYGHWR_HAL_STM32_ETH_DMASR_TUS BIT_(5) +#define CYGHWR_HAL_STM32_ETH_DMASR_RS BIT_(6) +#define CYGHWR_HAL_STM32_ETH_DMASR_RBUS BIT_(7) +#define CYGHWR_HAL_STM32_ETH_DMASR_RPSS BIT_(8) +#define CYGHWR_HAL_STM32_ETH_DMASR_RWTS BIT_(9) +#define CYGHWR_HAL_STM32_ETH_DMASR_ETS BIT_(10) +#define CYGHWR_HAL_STM32_ETH_DMASR_FBES BIT_(13) +#define CYGHWR_HAL_STM32_ETH_DMASR_ERS BIT_(14) +#define CYGHWR_HAL_STM32_ETH_DMASR_AIS BIT_(15) +#define CYGHWR_HAL_STM32_ETH_DMASR_NIS BIT_(16) +#define CYGHWR_HAL_STM32_ETH_DMASR_RPS MASK_(17,3) +#define CYGHWR_HAL_STM32_ETH_DMASR_TPS MASK_(20,3) +#define CYGHWR_HAL_STM32_ETH_DMASR_EBS MASK_(23,3) +#define CYGHWR_HAL_STM32_ETH_DMASR_MMCS BIT_(27) +#define CYGHWR_HAL_STM32_ETH_DMASR_PMTS BIT_(28) +#define CYGHWR_HAL_STM32_ETH_DMASR_TSTS BIT_(29) + +// DMAOMR + +#define CYGHWR_HAL_STM32_ETH_DMAOMR_SR BIT_(1) +#define CYGHWR_HAL_STM32_ETH_DMAOMR_OSF BIT_(2) +#define CYGHWR_HAL_STM32_ETH_DMAOMR_RTC(__x) VALUE_(3,__x) +#define CYGHWR_HAL_STM32_ETH_DMAOMR_FUGF BIT_(6) +#define CYGHWR_HAL_STM32_ETH_DMAOMR_FEF BIT_(7) +#define CYGHWR_HAL_STM32_ETH_DMAOMR_ST BIT_(13) +#define CYGHWR_HAL_STM32_ETH_DMAOMR_TTC(__x) VALUE_(14,__x) +#define CYGHWR_HAL_STM32_ETH_DMAOMR_FTF BIT_(20) +#define CYGHWR_HAL_STM32_ETH_DMAOMR_TSF BIT_(21) +#define CYGHWR_HAL_STM32_ETH_DMAOMR_DFRF BIT_(24) +#define CYGHWR_HAL_STM32_ETH_DMAOMR_RSF BIT_(25) +#define CYGHWR_HAL_STM32_ETH_DMAOMR_DTCEFD BIT_(26) + +// DMAIER + +#define CYGHWR_HAL_STM32_ETH_DMAIER_TIE BIT_(0) +#define CYGHWR_HAL_STM32_ETH_DMAIER_TPSIE BIT_(1) +#define CYGHWR_HAL_STM32_ETH_DMAIER_TBUIE BIT_(2) +#define CYGHWR_HAL_STM32_ETH_DMAIER_TJTIE BIT_(3) +#define CYGHWR_HAL_STM32_ETH_DMAIER_ROIE BIT_(4) +#define CYGHWR_HAL_STM32_ETH_DMAIER_TUIE BIT_(5) +#define CYGHWR_HAL_STM32_ETH_DMAIER_RIE BIT_(6) +#define CYGHWR_HAL_STM32_ETH_DMAIER_RBUIE BIT_(7) +#define CYGHWR_HAL_STM32_ETH_DMAIER_RPSIE BIT_(8) +#define CYGHWR_HAL_STM32_ETH_DMAIER_RWTIE BIT_(9) +#define CYGHWR_HAL_STM32_ETH_DMAIER_ETIE BIT_(10) +#define CYGHWR_HAL_STM32_ETH_DMAIER_FBEIE BIT_(13) +#define CYGHWR_HAL_STM32_ETH_DMAIER_ERIE BIT_(14) +#define CYGHWR_HAL_STM32_ETH_DMAIER_AISE BIT_(15) +#define CYGHWR_HAL_STM32_ETH_DMAIER_NISE BIT_(16) + +// DMAFBOCR omitted + +#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE) +#define CYGHWR_HAL_STM32_ETH_DMARSWTR_RSWTC_MASK MASK_(0,8) +#define CYGHWR_HAL_STM32_ETH_DMARSWTR_RSWTC(__x) ((__x)& CYGHWR_HAL_STM32_ETH_DMARSWTR_RSWTC_MASK) +#endif + +// Transmit descriptor fields + +/* +----------------------------------------------------------------------- +TDES0|OWN(31)|CTRL[30:26]|Res[25:24]|CTRL[23:20]|Res[19:17]|Stat[16:0]| +----------------------------------------------------------------------- +TDES1|Res[31:29]| Buffer2 Len[28:16] | Res[15:13] | Buffer1 Len[12:0] | +----------------------------------------------------------------------- +TDES2| Buffer1 Address [31:0] | +----------------------------------------------------------------------- +TDES3| Buffer2 Address [31:0] | +----------------------------------------------------------------------- +*/ + +// TDES0 register: DMA Tx descriptor status + +#define CYGHWR_HAL_STM32_ETH_TDES0_DB BIT_(0) +#define CYGHWR_HAL_STM32_ETH_TDES0_UF BIT_(1) +#define CYGHWR_HAL_STM32_ETH_TDES0_ED BIT_(2) +#define CYGHWR_HAL_STM32_ETH_TDES0_CC MASK_(3,4) +#define CYGHWR_HAL_STM32_ETH_TDES0_VF BIT_(7) +#define CYGHWR_HAL_STM32_ETH_TDES0_EC BIT_(8) +#define CYGHWR_HAL_STM32_ETH_TDES0_LCO BIT_(9) +#define CYGHWR_HAL_STM32_ETH_TDES0_NC BIT_(10) +#define CYGHWR_HAL_STM32_ETH_TDES0_LCA BIT_(11) +#define CYGHWR_HAL_STM32_ETH_TDES0_IPE BIT_(12) +#define CYGHWR_HAL_STM32_ETH_TDES0_FF BIT_(13) +#define CYGHWR_HAL_STM32_ETH_TDES0_JT BIT_(14) +#define CYGHWR_HAL_STM32_ETH_TDES0_ES BIT_(15) +#define CYGHWR_HAL_STM32_ETH_TDES0_IHE BIT_(16) +#define CYGHWR_HAL_STM32_ETH_TDES0_TTSS BIT_(17) +#define CYGHWR_HAL_STM32_ETH_TDES0_TCH BIT_(20) +#define CYGHWR_HAL_STM32_ETH_TDES0_TER BIT_(21) +#define CYGHWR_HAL_STM32_ETH_TDES0_CIC_DISA VALUE_(22,0) +#define CYGHWR_HAL_STM32_ETH_TDES0_CIC_H VALUE_(22,1) +#define CYGHWR_HAL_STM32_ETH_TDES0_CIC_HP VALUE_(22,2) +#define CYGHWR_HAL_STM32_ETH_TDES0_CIC_HPP VALUE_(22,3) +#define CYGHWR_HAL_STM32_ETH_TDES0_TTSE BIT_(25) +#define CYGHWR_HAL_STM32_ETH_TDES0_DP BIT_(26) +#define CYGHWR_HAL_STM32_ETH_TDES0_DC BIT_(27) +#define CYGHWR_HAL_STM32_ETH_TDES0_FS BIT_(28) +#define CYGHWR_HAL_STM32_ETH_TDES0_LS BIT_(29) +#define CYGHWR_HAL_STM32_ETH_TDES0_IC BIT_(30) +#define CYGHWR_HAL_STM32_ETH_TDES0_OWN BIT_(31) + +#define CYGHWR_HAL_STM32_ETH_TDES1_TBS1(__x) (VALUE_(0,__x)&0x00001FFF) +#define CYGHWR_HAL_STM32_ETH_TDES1_TBS2(__x) (VALUE_(16,__x)&0x1FFF0000) + +// Receive descriptor fields + +/* +----------------------------------------------------------------------- +RDES0| OWN(31) | Status [30:0] | +----------------------------------------------------------------------- +RDES1|DIC(31)|Res[30:29]|Not Used|CTRL[15:14]|Res(13)|Buffer Len[12:0]| +----------------------------------------------------------------------- +RDES2| Buffer1 Address [31:0] | +----------------------------------------------------------------------- +RDES3| Not Used | +----------------------------------------------------------------------- +*/ + +// RDES0 register: DMA Rx descriptor status + +#define CYGHWR_HAL_STM32_ETH_RDES0_PCE BIT_(0) +#define CYGHWR_HAL_STM32_ETH_RDES0_CE BIT_(1) +#define CYGHWR_HAL_STM32_ETH_RDES0_DE BIT_(2) +#define CYGHWR_HAL_STM32_ETH_RDES0_RE BIT_(3) +#define CYGHWR_HAL_STM32_ETH_RDES0_RWT BIT_(4) +#define CYGHWR_HAL_STM32_ETH_RDES0_FT BIT_(5) +#define CYGHWR_HAL_STM32_ETH_RDES0_LCO BIT_(6) +#define CYGHWR_HAL_STM32_ETH_RDES0_IPHCE BIT_(7) +#define CYGHWR_HAL_STM32_ETH_RDES0_LS BIT_(8) +#define CYGHWR_HAL_STM32_ETH_RDES0_FS BIT_(9) +#define CYGHWR_HAL_STM32_ETH_RDES0_VLAN BIT_(10) +#define CYGHWR_HAL_STM32_ETH_RDES0_OE BIT_(11) +#define CYGHWR_HAL_STM32_ETH_RDES0_LE BIT_(12) +#define CYGHWR_HAL_STM32_ETH_RDES0_SAF BIT_(13) +#define CYGHWR_HAL_STM32_ETH_RDES0_DESCE BIT_(14) +#define CYGHWR_HAL_STM32_ETH_RDES0_ES BIT_(15) +#define CYGHWR_HAL_STM32_ETH_RDES0_FL(__x) (((__x)>>16)&0x3FFF) +#define CYGHWR_HAL_STM32_ETH_RDES0_AFM BIT_(30) +#define CYGHWR_HAL_STM32_ETH_RDES0_OWN BIT_(31) + +// RDES1 register : DMA Rx descriptor control and buffer length + +#define CYGHWR_HAL_STM32_ETH_RDES1_RBS1(__x) VALUE_(0,__x) +#define CYGHWR_HAL_STM32_ETH_RDES1_RCH BIT_(14) +#define CYGHWR_HAL_STM32_ETH_RDES1_RER BIT_(15) +#define CYGHWR_HAL_STM32_ETH_RDES1_RBS2(__x) VALUE_(16,__x) + + +// GPIO pins + +// NOTE: The platform specific (re-)mapping of pins is provided in the relevant +// target specific "plf_io.h" header file. These definitions just cover the +// fixed mappings. + +// MCO1 clock to PHY +#define CYGHWR_HAL_STM32_ETH_MCO CYGHWR_HAL_STM32_PIN_ALTFN_OUT( A, 8, 0, PUSHPULL, NONE, AT_LEAST(50) ) + +// MII interface +#define CYGHWR_HAL_STM32_ETH_MII_MDC CYGHWR_HAL_STM32_PIN_ALTFN_OUT( C, 1, 11, PUSHPULL, NONE, AT_LEAST(50) ) +#define CYGHWR_HAL_STM32_ETH_MII_TXD2 CYGHWR_HAL_STM32_PIN_ALTFN_OUT( C, 2, 11, PUSHPULL, NONE, AT_LEAST(50) ) +#define CYGHWR_HAL_STM32_ETH_MII_MDIO CYGHWR_HAL_STM32_PIN_ALTFN_OUT( A, 2, 11, PUSHPULL, NONE, AT_LEAST(50) ) +#define CYGHWR_HAL_STM32_ETH_MII_TX_CLK CYGHWR_HAL_STM32_PIN_ALTFN_IN( C, 3, 11, OPENDRAIN, FLOATING ) +#define CYGHWR_HAL_STM32_ETH_MII_RX_CLK CYGHWR_HAL_STM32_PIN_ALTFN_IN( A, 1, 11, OPENDRAIN, FLOATING ) + +#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1) + +// MII interface +#define CYGHWR_HAL_STM32_ETH_MII_TX_CRS CYGHWR_HAL_STM32_PIN_IN( A, 0, FLOATING ) +#define CYGHWR_HAL_STM32_ETH_MII_COL CYGHWR_HAL_STM32_PIN_IN( A, 3, FLOATING ) +#define CYGHWR_HAL_STM32_ETH_MII_RX_ER CYGHWR_HAL_STM32_PIN_IN( B, 10, FLOATING ) + +#define CYGHWR_HAL_STM32_ETH_MII_TX_EN CYGHWR_HAL_STM32_PIN_ALTFN_OUT( B, 11, 11, PUSHPULL, NONE, AT_LEAST(50) ) +#define CYGHWR_HAL_STM32_ETH_MII_TXD0 CYGHWR_HAL_STM32_PIN_ALTFN_OUT( B, 12, 11, PUSHPULL, NONE, AT_LEAST(50) ) +#define CYGHWR_HAL_STM32_ETH_MII_TXD1 CYGHWR_HAL_STM32_PIN_ALTFN_OUT( B, 13, 11, PUSHPULL, NONE, AT_LEAST(50) ) +#define CYGHWR_HAL_STM32_ETH_MII_PPS_OUT CYGHWR_HAL_STM32_PIN_ALTFN_OUT( B, 5, 11, PUSHPULL, NONE, AT_LEAST(50) ) +#define CYGHWR_HAL_STM32_ETH_MII_TXD3 CYGHWR_HAL_STM32_PIN_ALTFN_OUT( B, 8, 11, PUSHPULL, NONE, AT_LEAST(50) ) + +// RMII interface +#define CYGHWR_HAL_STM32_ETH_RMII_MDC CYGHWR_HAL_STM32_ETH_MII_MDC +#define CYGHWR_HAL_STM32_ETH_RMII_REF_CLK CYGHWR_HAL_STM32_ETH_MII_RX_CLK +#define CYGHWR_HAL_STM32_ETH_RMII_MDIO CYGHWR_HAL_STM32_ETH_MII_MDIO +#define CYGHWR_HAL_STM32_ETH_RMII_TX_EN CYGHWR_HAL_STM32_ETH_MII_TX_EN +#define CYGHWR_HAL_STM32_ETH_RMII_TXD0 CYGHWR_HAL_STM32_ETH_MII_TXD0 +#define CYGHWR_HAL_STM32_ETH_RMII_TXD1 CYGHWR_HAL_STM32_ETH_MII_TXD1 +#define CYGHWR_HAL_STM32_ETH_RMII_PPS_OUT CYGHWR_HAL_STM32_ETH_MII_PPS_OUT + +// Clock controls + +#define CYGHWR_HAL_STM32_ETH_MAC_CLOCK CYGHWR_HAL_STM32_CLOCK( AHB, ETHMAC ) +#define CYGHWR_HAL_STM32_ETH_TX_CLOCK CYGHWR_HAL_STM32_CLOCK( AHB, ETHMACTX ) +#define CYGHWR_HAL_STM32_ETH_RX_CLOCK CYGHWR_HAL_STM32_CLOCK( AHB, ETHMACRX ) + +#elif defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE) + +// MII interface +#define CYGHWR_HAL_STM32_ETH_MII_RX_DV CYGHWR_HAL_STM32_PIN_ALTFN_IN( A, 7, 11, OPENDRAIN, NONE ) +#define CYGHWR_HAL_STM32_ETH_MII_RXD0 CYGHWR_HAL_STM32_PIN_ALTFN_IN( C, 4, 11, OPENDRAIN, NONE ) +#define CYGHWR_HAL_STM32_ETH_MII_RXD1 CYGHWR_HAL_STM32_PIN_ALTFN_IN( C, 5, 11, OPENDRAIN, NONE ) + +// RMII interface +#define CYGHWR_HAL_STM32_ETH_RMII_MDC CYGHWR_HAL_STM32_ETH_MII_MDC +#define CYGHWR_HAL_STM32_ETH_RMII_REF_CLK CYGHWR_HAL_STM32_ETH_MII_RX_CLK +#define CYGHWR_HAL_STM32_ETH_RMII_MDIO CYGHWR_HAL_STM32_ETH_MII_MDIO +#define CYGHWR_HAL_STM32_ETH_RMII_CRS_DV CYGHWR_HAL_STM32_ETH_MII_RX_DV +#define CYGHWR_HAL_STM32_ETH_RMII_RXD0 CYGHWR_HAL_STM32_ETH_MII_RXD0 +#define CYGHWR_HAL_STM32_ETH_RMII_RXD1 CYGHWR_HAL_STM32_ETH_MII_RXD1 +#define CYGHWR_HAL_STM32_ETH_RMII_TX_EN CYGHWR_HAL_STM32_ETH_MII_TX_EN +#define CYGHWR_HAL_STM32_ETH_RMII_TXD0 CYGHWR_HAL_STM32_ETH_MII_TXD0 +#define CYGHWR_HAL_STM32_ETH_RMII_TXD1 CYGHWR_HAL_STM32_ETH_MII_TXD1 +#define CYGHWR_HAL_STM32_ETH_RMII_PPS_OUT CYGHWR_HAL_STM32_ETH_MII_PPS_OUT + +// Clock controls + +#define CYGHWR_HAL_STM32_ETH_MAC_CLOCK CYGHWR_HAL_STM32_CLOCK( AHB1, ETHMAC ) +#define CYGHWR_HAL_STM32_ETH_TX_CLOCK CYGHWR_HAL_STM32_CLOCK( AHB1, ETHMACTX ) +#define CYGHWR_HAL_STM32_ETH_RX_CLOCK CYGHWR_HAL_STM32_CLOCK( AHB1, ETHMACRX ) + +#endif // elif defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE) + +#endif // CYGHWR_HAL_CORTEXM_STM32_CONNECTIVITY + +#endif // CYGONCE_HAL_VAR_IO_ETH_H +//----------------------------------------------------------------------------- +// end of var_io_eth.h diff --git a/ecos/packages/hal/cortexm/stm32/var/current/include/var_io_pins.h b/ecos/packages/hal/cortexm/stm32/var/current/include/var_io_pins.h new file mode 100644 index 0000000..5ec9986 --- /dev/null +++ b/ecos/packages/hal/cortexm/stm32/var/current/include/var_io_pins.h @@ -0,0 +1,502 @@ +#ifndef CYGONCE_HAL_VAR_IO_PINS_H +#define CYGONCE_HAL_VAR_IO_PINS_H +//============================================================================= +// +// var_io_pins.h +// +// Pin configuration and GPIO definitions +// +//============================================================================= +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2008, 2009, 2011 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): nickg, jlarmour +// Date: 2011-11-29 +// Purpose: STM32 variant GPIO and pin configuration specific registers +// Description: +// Usage: Do not include this header file directly. Instead: +// #include <cyg/hal/var_io.h> +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +#ifndef CYGONCE_HAL_VAR_IO_H +# error Do not include var_io_pins.h directly, use var_io.h +#endif + +//============================================================================= +// GPIO ports - common manifests + +#define CYGHWR_HAL_STM32_GPIO_OSPEED_NA (0) // Convenience define for ease of pin definitions (for F1 actually marks MODE as INPUT) + +//============================================================================= +// GPIO ports - F1 family + +#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1) +#define CYGHWR_HAL_STM32_GPIO_CRL 0x00 +#define CYGHWR_HAL_STM32_GPIO_CRH 0x04 +#define CYGHWR_HAL_STM32_GPIO_IDR 0x08 +#define CYGHWR_HAL_STM32_GPIO_ODR 0x0C +#define CYGHWR_HAL_STM32_GPIO_BSRR 0x10 +#define CYGHWR_HAL_STM32_GPIO_BRR 0x14 +#define CYGHWR_HAL_STM32_GPIO_LCKR 0x18 + +#define CYGHWR_HAL_STM32_GPIO_MODE_IN VALUE_(0,0) // Input mode +#define CYGHWR_HAL_STM32_GPIO_MODE_OUT_10MHZ VALUE_(0,1) // Output mode, max 10MHz +#define CYGHWR_HAL_STM32_GPIO_MODE_OUT_2MHZ VALUE_(0,2) // Output mode, max 2MHz +#define CYGHWR_HAL_STM32_GPIO_MODE_OUT_50MHZ VALUE_(0,3) // Output mode, max 50MHz + +#define CYGHWR_HAL_STM32_GPIO_MODE_OUT_LOW (CYGHWR_HAL_STM32_GPIO_MODE_OUT_2MHZ) +#define CYGHWR_HAL_STM32_GPIO_MODE_OUT_MED (CYGHWR_HAL_STM32_GPIO_MODE_OUT_10MHZ) +#define CYGHWR_HAL_STM32_GPIO_MODE_OUT_FAST (CYGHWR_HAL_STM32_GPIO_MODE_OUT_50MHZ) +#define CYGHWR_HAL_STM32_GPIO_MODE_OUT_HIGH (CYGHWR_HAL_STM32_GPIO_MODE_OUT_FAST) // F1 limited to 50MHz + +// The following allows compatible specification of speed with other parts +#define CYGHWR_HAL_STM32_GPIO_MODE_OUT_AT_LEAST(__mhz) ( ((__mhz) <= 2) ? CYGHWR_HAL_STM32_GPIO_MODE_OUT_2MHZ : \ + ((__mhz) <= 10) ? CYGHWR_HAL_STM32_GPIO_MODE_OUT_10MHZ : \ + ((__mhz) <= 50) ? CYGHWR_HAL_STM32_GPIO_MODE_OUT_50MHZ : \ + CYGHWR_HAL_STM32_GPIO_MODE_OUT_HIGH ) + +#define CYGHWR_HAL_STM32_GPIO_MODE_OUT_AT_MOST(__mhz) ( ((__mhz) < 10) ? CYGHWR_HAL_STM32_GPIO_MODE_OUT_2MHZ : \ + ((__mhz) < 50) ? CYGHWR_HAL_STM32_GPIO_MODE_OUT_10MHZ : \ + ((__mhz) < 100) ? CYGHWR_HAL_STM32_GPIO_MODE_OUT_50MHZ : \ + CYGHWR_HAL_STM32_GPIO_MODE_OUT_HIGH ) + +#define CYGHWR_HAL_STM32_GPIO_CNF_AIN VALUE_(2,0) // Analog input +#define CYGHWR_HAL_STM32_GPIO_CNF_FIN VALUE_(2,1) // Floating input +#define CYGHWR_HAL_STM32_GPIO_CNF_PULL VALUE_(2,2) // Input with pull up/down +#define CYGHWR_HAL_STM32_GPIO_CNF_RESV VALUE_(2,3) // Reserved + +#define CYGHWR_HAL_STM32_GPIO_CNF_GPOPP VALUE_(2,0) // GP output push/pull +#define CYGHWR_HAL_STM32_GPIO_CNF_GPOOD VALUE_(2,1) // GP output open drain +#define CYGHWR_HAL_STM32_GPIO_CNF_AOPP VALUE_(2,2) // Alt output push/pull +#define CYGHWR_HAL_STM32_GPIO_CNF_AOOD VALUE_(2,3) // Alt output open drain + + +// Alternative, more readable, config names +// Inputs +#define CYGHWR_HAL_STM32_GPIO_CNF_ANALOG CYGHWR_HAL_STM32_GPIO_CNF_AIN +#define CYGHWR_HAL_STM32_GPIO_CNF_FLOATING CYGHWR_HAL_STM32_GPIO_CNF_FIN +#define CYGHWR_HAL_STM32_GPIO_CNF_PULLDOWN (CYGHWR_HAL_STM32_GPIO_CNF_PULL) +#define CYGHWR_HAL_STM32_GPIO_CNF_PULLUP (CYGHWR_HAL_STM32_GPIO_CNF_PULL|CYGHWR_HAL_STM32_GPIO_PULLUP) +// Outputs +#define CYGHWR_HAL_STM32_GPIO_CNF_OUT_OPENDRAIN CYGHWR_HAL_STM32_GPIO_CNF_GPOOD +#define CYGHWR_HAL_STM32_GPIO_CNF_OUT_PUSHPULL CYGHWR_HAL_STM32_GPIO_CNF_GPOPP +#define CYGHWR_HAL_STM32_GPIO_CNF_ALT_OPENDRAIN CYGHWR_HAL_STM32_GPIO_CNF_AOOD +#define CYGHWR_HAL_STM32_GPIO_CNF_ALT_PUSHPULL CYGHWR_HAL_STM32_GPIO_CNF_AOPP + + +// This macro packs the port number, bit number, mode and +// configuration for a GPIO pin into a single word. The packing puts +// the mode and config in the ls 5 bits, the bit number in 16:20 and +// the offset of the GPIO port from GPIOA in bits 8:15. The port, mode +// and config are only specified using the last component of the names +// to keep definitions short. + +#define CYGHWR_HAL_STM32_GPIO(__port, __bit, __mode, __cnf ) \ + ((CYGHWR_HAL_STM32_GPIO##__port - CYGHWR_HAL_STM32_GPIOA) | \ + (__bit<<16) | \ + (CYGHWR_HAL_STM32_GPIO_MODE_##__mode) | \ + (CYGHWR_HAL_STM32_GPIO_CNF_##__cnf)) + +// We treat the CNF and MODE fields as a single field to simplify the hardware register access. The CNFMODE fields are split across +// two registers (CRL/CRH) so the passed __pin needs to be in the range 0..7 +#define CYGHWR_HAL_STM32_GPIO_CNFMODE_VAL(__pin, __cnfmode) ((__cnfmode) << ((__pin)<<2)) +#define CYGHWR_HAL_STM32_GPIO_CNFMODE_SET(__pin, __cnfmode, __reg) ((__reg) &= ~MASK_((__pin<<2),4), \ + (__reg) |= CYGHWR_HAL_STM32_GPIO_CNFMODE_VAL(__pin, __cnfmode)) + +// Macros to extract encoded values +#define CYGHWR_HAL_STM32_GPIO_PORT(__pin) (CYGHWR_HAL_STM32_GPIOA+((__pin)&0x0000FF00)) +#define CYGHWR_HAL_STM32_GPIO_BIT(__pin) (((__pin)>>16)&0x1F) +#define CYGHWR_HAL_STM32_GPIO_CFG(__pin) ((__pin)&0xF) +#define CYGHWR_HAL_STM32_GPIO_PULLUP BIT_(4) + +//============================================================================= +// Alternate I/O configuration registers. + +#define CYGHWR_HAL_STM32_AFIO_EVCR 0x00 +#define CYGHWR_HAL_STM32_AFIO_MAPR 0x04 +#define CYGHWR_HAL_STM32_AFIO_EXTICR1 0x08 +#define CYGHWR_HAL_STM32_AFIO_EXTICR2 0x0C +#define CYGHWR_HAL_STM32_AFIO_EXTICR3 0x10 +#define CYGHWR_HAL_STM32_AFIO_EXTICR4 0x14 + +// The following macro allows the four EXTICR registers to be indexed +// as CYGHWR_HAL_STM32_AFIO_EXTICR(1) to CYGHWR_HAL_STM32_AFIO_EXTICR(4) +#define CYGHWR_HAL_STM32_AFIO_EXTICR(__x) (4*((__x)-1)+0x08) + +#define CYGHWR_HAL_STM32_AFIO_EVCR_PIN(__x) VALUE_(0,(__x)) +#define CYGHWR_HAL_STM32_AFIO_EVCR_PORTA VALUE_(4,0) +#define CYGHWR_HAL_STM32_AFIO_EVCR_PORTB VALUE_(4,1) +#define CYGHWR_HAL_STM32_AFIO_EVCR_PORTC VALUE_(4,2) +#define CYGHWR_HAL_STM32_AFIO_EVCR_PORTD VALUE_(4,3) +#define CYGHWR_HAL_STM32_AFIO_EVCR_PORTE VALUE_(4,4) +#define CYGHWR_HAL_STM32_AFIO_EVCR_EVOE BIT_(7) + +#define CYGHWR_HAL_STM32_AFIO_MAPR_SPI1_RMP BIT_(0) +#define CYGHWR_HAL_STM32_AFIO_MAPR_I2C1_RMP BIT_(1) +#define CYGHWR_HAL_STM32_AFIO_MAPR_URT1_RMP BIT_(2) +#define CYGHWR_HAL_STM32_AFIO_MAPR_URT2_RMP BIT_(3) + +#define CYGHWR_HAL_STM32_AFIO_MAPR_URT3_NO_RMP VALUE_(4,0) +#define CYGHWR_HAL_STM32_AFIO_MAPR_URT3_P1_RMP VALUE_(4,1) +#define CYGHWR_HAL_STM32_AFIO_MAPR_URT3_FL_RMP VALUE_(4,3) + +#define CYGHWR_HAL_STM32_AFIO_MAPR_TIM1_NO_RMP VALUE_(6,0) +#define CYGHWR_HAL_STM32_AFIO_MAPR_TIM1_P1_RMP VALUE_(6,1) +#define CYGHWR_HAL_STM32_AFIO_MAPR_TIM1_FL_RMP VALUE_(6,3) + +#define CYGHWR_HAL_STM32_AFIO_MAPR_TIM2_NO_RMP VALUE_(8,0) +#define CYGHWR_HAL_STM32_AFIO_MAPR_TIM2_P1_RMP VALUE_(8,1) +#define CYGHWR_HAL_STM32_AFIO_MAPR_TIM2_P2_RMP VALUE_(8,2) +#define CYGHWR_HAL_STM32_AFIO_MAPR_TIM2_FL_RMP VALUE_(8,3) + +#define CYGHWR_HAL_STM32_AFIO_MAPR_TIM3_NO_RMP VALUE_(10,0) +#define CYGHWR_HAL_STM32_AFIO_MAPR_TIM3_P2_RMP VALUE_(10,2) +#define CYGHWR_HAL_STM32_AFIO_MAPR_TIM3_FL_RMP VALUE_(10,3) + +#define CYGHWR_HAL_STM32_AFIO_MAPR_TIM4_RMP BIT_(12) + +#define CYGHWR_HAL_STM32_AFIO_MAPR_CAN_NO_RMP VALUE_(13,0) +#define CYGHWR_HAL_STM32_AFIO_MAPR_CAN_FL1_RMP VALUE_(13,2) +#define CYGHWR_HAL_STM32_AFIO_MAPR_CAN_FL2_RMP VALUE_(13,3) + +#define CYGHWR_HAL_STM32_AFIO_MAPR_PD01_RMP BIT_(15) +#define CYGHWR_HAL_STM32_AFIO_MAPR_TIM5CH4_RMP BIT_(16) +#define CYGHWR_HAL_STM32_AFIO_MAPR_ADC1EINJ_RMP BIT_(17) +#define CYGHWR_HAL_STM32_AFIO_MAPR_ADC1EREG_RMP BIT_(18) +#define CYGHWR_HAL_STM32_AFIO_MAPR_ADC2EINJ_RMP BIT_(19) +#define CYGHWR_HAL_STM32_AFIO_MAPR_ADC2EREG_RMP BIT_(20) + +#ifdef CYGHWR_HAL_CORTEXM_STM32_CONNECTIVITY +#define CYGHWR_HAL_STM32_AFIO_MAPR_ETH_RMP BIT_(21) +#define CYGHWR_HAL_STM32_AFIO_MAPR_CAN2_RMP BIT_(22) +#define CYGHWR_HAL_STM32_AFIO_MAPR_ETH_RMII BIT_(23) +#endif + +#define CYGHWR_HAL_STM32_AFIO_MAPR_SWJ_FULL VALUE_(24,0) +#define CYGHWR_HAL_STM32_AFIO_MAPR_SWJ_NORST VALUE_(24,1) +#define CYGHWR_HAL_STM32_AFIO_MAPR_SWJ_SWDPEN VALUE_(24,2) +#define CYGHWR_HAL_STM32_AFIO_MAPR_SWJ_SWDPDIS VALUE_(24,4) +#define CYGHWR_HAL_STM32_AFIO_MAPR_SWJ_MASK VALUE_(24,7) + +#ifdef CYGHWR_HAL_CORTEXM_STM32_CONNECTIVITY +#define CYGHWR_HAL_STM32_AFIO_MAPR_SPI3_RMP BIT_(28) +#define CYGHWR_HAL_STM32_AFIO_MAPR_TIM2ITR1_RMP BIT_(29) +#define CYGHWR_HAL_STM32_AFIO_MAPR_PTP_PPS_RMP BIT_(30) +#endif + +// The following macros are used to generate the bitfields for setting up +// external interrupts. For example, CYGHWR_HAL_STM32_AFIO_EXTICRX_PORTC(12) +// will generate the bitfield which when ORed into the EXTICR4 register will +// set up C12 as the external interrupt pin for the EXTI12 interrupt. +#define CYGHWR_HAL_STM32_AFIO_EXTICRX_PORTA(__x) VALUE_(4*((__x)&3),0) +#define CYGHWR_HAL_STM32_AFIO_EXTICRX_PORTB(__x) VALUE_(4*((__x)&3),1) +#define CYGHWR_HAL_STM32_AFIO_EXTICRX_PORTC(__x) VALUE_(4*((__x)&3),2) +#define CYGHWR_HAL_STM32_AFIO_EXTICRX_PORTD(__x) VALUE_(4*((__x)&3),3) +#define CYGHWR_HAL_STM32_AFIO_EXTICRX_PORTE(__x) VALUE_(4*((__x)&3),4) +#define CYGHWR_HAL_STM32_AFIO_EXTICRX_PORTF(__x) VALUE_(4*((__x)&3),5) +#define CYGHWR_HAL_STM32_AFIO_EXTICRX_PORTG(__x) VALUE_(4*((__x)&3),6) +#define CYGHWR_HAL_STM32_AFIO_EXTICRX_MASK(__x) VALUE_(4*((__x)&3),0xF) + +// AFIO clock control + +#define CYGHWR_HAL_STM32_AFIO_CLOCK CYGHWR_HAL_STM32_CLOCK( APB2, AFIO ) + +#endif // if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1) +//============================================================================= +// GPIO ports - F2/F4 family + +#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE) + +// GPIO Register offsets. +#define CYGHWR_HAL_STM32_GPIO_MODER 0x00 +#define CYGHWR_HAL_STM32_GPIO_OTYPER 0x04 +#define CYGHWR_HAL_STM32_GPIO_OSPEEDR 0x08 +#define CYGHWR_HAL_STM32_GPIO_PUPDR 0x0C +#define CYGHWR_HAL_STM32_GPIO_IDR 0x10 +#define CYGHWR_HAL_STM32_GPIO_ODR 0x14 +#define CYGHWR_HAL_STM32_GPIO_BSRR 0x18 +#define CYGHWR_HAL_STM32_GPIO_LCKR 0x1C +#define CYGHWR_HAL_STM32_GPIO_AFRL 0x20 +#define CYGHWR_HAL_STM32_GPIO_AFRH 0x24 + +// A helper macro just to allow access to a particular register +#define CYGHWR_HAL_STM32_GPIO_REG(__portbaseaddr, __offset) ((volatile cyg_uint32 *)( ((char*)__portbaseaddr) + __offset )) + +// GPIO port mode register. +#define CYGHWR_HAL_STM32_GPIO_MODE_GPIO_IN (0) +#define CYGHWR_HAL_STM32_GPIO_MODE_GPIO_OUT (1) +#define CYGHWR_HAL_STM32_GPIO_MODE_ALTFN (2) +#define CYGHWR_HAL_STM32_GPIO_MODE_ANALOG (3) +#define CYGHWR_HAL_STM32_GPIO_MODE_VAL(__pin, __mode) ((__mode) << ((__pin)<<1)) +#define CYGHWR_HAL_STM32_GPIO_MODE_SET(__pin, __mode, __reg) ((__reg) &= ~MASK_((__pin<<1),2), \ + (__reg) |= CYGHWR_HAL_STM32_GPIO_MODE_VAL(__pin, __mode)) + +// GPIO port output type register. +#define CYGHWR_HAL_STM32_GPIO_OTYPE_PUSHPULL (0) +#define CYGHWR_HAL_STM32_GPIO_OTYPE_OPENDRAIN (1) +#define CYGHWR_HAL_STM32_GPIO_OTYPE_VAL(__pin, __otype) VALUE_(__pin,__otype) +#define CYGHWR_HAL_STM32_GPIO_OTYPE_SET(__pin, __otype, __reg) ((__reg) &= ~BIT_(__pin), \ + (__reg) |= CYGHWR_HAL_STM32_GPIO_OTYPE_VAL(__pin, __otype)) +#define CYGHWR_HAL_STM32_GPIO_OTYPE_NA (0) // Convenience define for ease of pin definitions + +// GPIO port output speed register. +#define CYGHWR_HAL_STM32_GPIO_OSPEED_LOW (0) // 2MHz +#define CYGHWR_HAL_STM32_GPIO_OSPEED_2MHZ (0) +#define CYGHWR_HAL_STM32_GPIO_OSPEED_MED (1) // 25MHz +#define CYGHWR_HAL_STM32_GPIO_OSPEED_25MHZ (1) +#define CYGHWR_HAL_STM32_GPIO_OSPEED_FAST (2) // 50MHz +#define CYGHWR_HAL_STM32_GPIO_OSPEED_50MHZ (2) +#define CYGHWR_HAL_STM32_GPIO_OSPEED_HIGH (3) // 100MHZ on 30pF, 80MHz on 15pF +#define CYGHWR_HAL_STM32_GPIO_OSPEED_BAL(__pin, __speed) ((__speed) << ((__pin)<<1)) +#define CYGHWR_HAL_STM32_GPIO_OSPEED_SET(__pin, __speed, __reg) ((__reg) &= ~MASK_((__pin<<1),2), \ + (__reg) |= CYGHWR_HAL_STM32_GPIO_OSPEED_BAL(__pin, __speed)) + +// The following allows compatible specification of speed with other parts +// which have different speed ranges e.g. F1 +#define CYGHWR_HAL_STM32_GPIO_OSPEED_AT_LEAST(__mhz) ( ((__mhz) <= 2) ? CYGHWR_HAL_STM32_GPIO_OSPEED_2MHZ : \ + ((__mhz) <= 25) ? CYGHWR_HAL_STM32_GPIO_OSPEED_25MHZ : \ + ((__mhz) <= 50) ? CYGHWR_HAL_STM32_GPIO_OSPEED_50MHZ : \ + CYGHWR_HAL_STM32_GPIO_OSPEED_HIGH ) + +#define CYGHWR_HAL_STM32_GPIO_OSPEED_AT_MOST(__mhz) ( ((__mhz) < 25) ? CYGHWR_HAL_STM32_GPIO_OSPEED_2MHZ : \ + ((__mhz) < 50) ? CYGHWR_HAL_STM32_GPIO_OSPEED_25MHZ : \ + ((__mhz) < 100) ? CYGHWR_HAL_STM32_GPIO_OSPEED_50MHZ : \ + CYGHWR_HAL_STM32_GPIO_OSPEED_HIGH ) + +// GPIO port pull-up/pull-down register. +#define CYGHWR_HAL_STM32_GPIO_PUPD_NONE (0) +#define CYGHWR_HAL_STM32_GPIO_PUPD_PULLUP (1) +#define CYGHWR_HAL_STM32_GPIO_PUPD_PULLDOWN (2) +#define CYGHWR_HAL_STM32_GPIO_PUPD_VAL(__pin, __pupd) ((__pupd) << ((__pin)<<1)) +#define CYGHWR_HAL_STM32_GPIO_PUPD_SET(__pin, __pupd, __reg) ((__reg) &= ~MASK_(((__pin)<<1),2), \ + (__reg) |= CYGHWR_HAL_STM32_GPIO_PUPD_VAL(__pin, __pupd)) + +// GPIO port input data register. +#define CYGHWR_HAL_STM32_GPIO_IDR_GET(__portbaseaddr, __pin, __val) \ + ((__val) = ( *CYGHWR_HAL_STM32_GPIO_REG(__portbaseaddr, CYGHWR_HAL_STM32_GPIO_IDR) >> (__pin)) & 1) + +// GPIO port output data register. +// Don't encourage setting it here. Use GPIO_BSRR instead for that. +#define CYGHWR_HAL_STM32_GPIO_ODR_GET(__portbaseaddr, __pin, __val) \ + ((__val) = ( *CYGHWR_HAL_STM32_GPIO_REG(__portbaseaddr, CYGHWR_HAL_STM32_GPIO_ODR) >> (__pin)) & 1) + +// GPIO port bit set/reset register. +#define CYGHWR_HAL_STM32_GPIO_BSRR_SET(__portbaseaddr, __pin, __val) \ + ( *CYGHWR_HAL_STM32_GPIO_REG(__portbaseaddr, CYGHWR_HAL_STM32_GPIO_BSRR) = (__val)?(1<<(__pin)):(1<<((__pin)+16))) + +// GPIO port configuration lock register. +#define CYGHWR_HAL_STM32_GPIO_LCKR_LCKK BIT_(16) +#define CYGHWR_HAL_STM32_GPIO_LCKR_LCK(__pin) BIT_((__pin)) + +// GPIO alternate function low register. +#define CYGHWR_HAL_STM32_GPIO_AFRL0 MASK_(0,4) +#define CYGHWR_HAL_STM32_GPIO_AFRL1 MASK_(4,4) +#define CYGHWR_HAL_STM32_GPIO_AFRL2 MASK_(8,4) +#define CYGHWR_HAL_STM32_GPIO_AFRL3 MASK_(12,4) +#define CYGHWR_HAL_STM32_GPIO_AFRL4 MASK_(16,4) +#define CYGHWR_HAL_STM32_GPIO_AFRL5 MASK_(20,4) +#define CYGHWR_HAL_STM32_GPIO_AFRL6 MASK_(24,4) +#define CYGHWR_HAL_STM32_GPIO_AFRL7 MASK_(28,4) +// GPIO alternate function high register. +#define CYGHWR_HAL_STM32_GPIO_AFRH8 MASK_(0,4) +#define CYGHWR_HAL_STM32_GPIO_AFRH9 MASK_(4,4) +#define CYGHWR_HAL_STM32_GPIO_AFRH10 MASK_(8,4) +#define CYGHWR_HAL_STM32_GPIO_AFRH11 MASK_(12,4) +#define CYGHWR_HAL_STM32_GPIO_AFRH12 MASK_(16,4) +#define CYGHWR_HAL_STM32_GPIO_AFRH13 MASK_(20,4) +#define CYGHWR_HAL_STM32_GPIO_AFRH14 MASK_(24,4) +#define CYGHWR_HAL_STM32_GPIO_AFRH15 MASK_(28,4) + +// Set alternate function. We try to keep this as a macro as most times the +// arguments will be constant so can easily be collapsed substantially by the +// compiler. +// Note, this is not interrupt-safe, unavoidably. Provide your own protection +// if that's needed, although in general this will happen at startup time. +#define CYGHWR_HAL_STM32_GPIO_AFR_SET(__portbaseaddr, __pin, __func) \ + CYG_MACRO_START \ + cyg_uint32 __cur_afr, __mask; \ + volatile cyg_uint32 *__reg; \ + cyg_uint8 __reg_pin = (__pin); \ + if (__pin < 8) { \ + __reg = CYGHWR_HAL_STM32_GPIO_REG(__portbaseaddr, CYGHWR_HAL_STM32_GPIO_AFRL); \ + } else { \ + __reg = CYGHWR_HAL_STM32_GPIO_REG(__portbaseaddr, CYGHWR_HAL_STM32_GPIO_AFRH); \ + __reg_pin -= 8; \ + } \ + HAL_READ_UINT32( __reg, __cur_afr ); \ + __mask = 0xf << (__reg_pin<<2); \ + __cur_afr &= ~__mask; \ + __mask = (__func) << (__reg_pin<<2); \ + __cur_afr |= __mask; \ + HAL_WRITE_UINT32( __reg, __cur_afr ); \ + CYG_MACRO_END + + +// This macro packs the port number, bit number, mode and +// configuration for a GPIO pin into a single word. The packing puts +// the GPIO bank at bits 16:19, the pin at bits 12:15, the mode (i.e. function) +// at bits 10:11, for ALTFN mode the specific mapping at bits 6:9, pushpull(0) +// or open drain(1) at bit 5, pull-up(1) pull-down (2) or neither(0) at +// bits 3:4, and speed at bits 0:2 (low, med, fast, high). +// To keep definitions short, we simplify most of the arguments so they +// can be passed in with only their last components. + +// FIXME: This should be renamed to something like CYGHWR_HAL_STM32_PIN(... when +// bringing F1 into line with this way of declaring pins. + +#define CYGHWR_HAL_STM32_GPIO(__port, __bit, __mode, __af, __ppod, __pupd, __speed) \ + ( ((CYGHWR_HAL_STM32_GPIO##__port - CYGHWR_HAL_STM32_GPIOA) << 6 ) | \ + (__bit << 12) | \ + (CYGHWR_HAL_STM32_GPIO_MODE_##__mode << 10) | \ + (__af << 6) | \ + (CYGHWR_HAL_STM32_GPIO_OTYPE_##__ppod << 5) | \ + (CYGHWR_HAL_STM32_GPIO_PUPD_##__pupd << 3) | \ + (CYGHWR_HAL_STM32_GPIO_OSPEED_##__speed) ) + +// Macros to extract encoded values +#define CYGHWR_HAL_STM32_GPIO_PORT(__pin) (CYGHWR_HAL_STM32_GPIOA+(((__pin)&0xF0000)>>6)) +#define CYGHWR_HAL_STM32_GPIO_BIT(__pin) (((__pin)>>12)&0xF) +#define CYGHWR_HAL_STM32_GPIO_MODE(__pin) (((__pin)>>10)&0x3) +#define CYGHWR_HAL_STM32_GPIO_AF(__pin) (((__pin)>>6)&0xF) +#define CYGHWR_HAL_STM32_GPIO_OPENDRAIN(__pin) (((__pin)>>5)&0x1) +#define CYGHWR_HAL_STM32_GPIO_PULLUPDOWN(__pin) (((__pin)>>3)&0x3) +#define CYGHWR_HAL_STM32_GPIO_SPEED(__pin) ((__pin)&0x7) + +#endif //if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE) + +//============================================================================= + +#define CYGHWR_HAL_STM32_GPIO_NONE (0xFFFFFFFF) + +// Functions and macros to configure GPIO ports. + +__externC void hal_stm32_gpio_set( cyg_uint32 pin ); +__externC void hal_stm32_gpio_out( cyg_uint32 pin, int val ); +__externC void hal_stm32_gpio_in ( cyg_uint32 pin, int *val ); + +#define CYGHWR_HAL_STM32_GPIO_SET(__pin ) hal_stm32_gpio_set( __pin ) +#define CYGHWR_HAL_STM32_GPIO_OUT(__pin, __val ) hal_stm32_gpio_out( __pin, __val ) +#define CYGHWR_HAL_STM32_GPIO_IN(__pin, __val ) hal_stm32_gpio_in( __pin, __val ) + +//----------------------------------------------------------------------------- + +// For the following pin definition macros where __speed is a parameter the +// actual rates available depend on the target family. The generic LOW, MED, +// FAST and HIGH manifests can be used instead of explicit values, or more +// usefully the AT_LEAST(__mhz) and AT_MOST(__mhz) macros can be used to specify +// an acceptable limit instead. + +// The CYGHWR_HAL_STM32_PIN_OUT() macro defines a GPIO output pin. The __ppod +// parameter can be one of PUSHPULL or OPENDRAIN. The __pupd parameter can be +// one of NONE, PULLUP or PULLDOWN. For F1 devices the __pupd parameter is +// not-relevant and is ignored. +// e.g. +// CYGHWR_HAL_STM32_PIN_OUT(B,8,OPENDRAIN,NONE,FAST); +// CYGHWR_HAL_STM32_PIN_OUT(B,9,OPENDRAIN,NONE.AT_LEAST(50)); + +// The CYGHWR_HAL_STM32_PIN_ALTFN_OUT() macro defines an alternative function +// output pin. For F1 family devices the __af field is not-relevant and is +// ignored. The __ppod should be PUSHPULL or OPENDRAIN. The __pupd parameter can +// be one of NONE, PULLUP or PULLDOWN. For F1 devices the __pupd parameter is +// not-relevant and is ignored. +// e.g. +// CYGHWR_HAL_STM32_PIN_ALTFN_OUT(B,6,4,OPENDRAIN,NONE,MED); +// CYGHWR_HAL_STM32_PIN_ALTFN_OUT(B,10,4,OPENDRAIN,NONE,AT_LEAST(10)); + +// The CYGHWR_HAL_STM32_PIN_IN() macro is used to define GPIO input pins. The +// __pupd should be one of NONE. FLOATING, PULLUP or PULLDOWN. +// e.g. +// CYGHWR_HAL_STM32_PIN_IN(B,4,PULLUP); + +// The CYGHWR_HAL_STM32_PIN_ALTFN_IN() macro is used to define alternate +// function input pins. The __ppod parameter can be one of PUSHPULL, +// OPENDRAIN or NA. The __pupd should be one of NONE. FLOATING, PULLUP or +// PULLDOWN. For F1 family devices the __af and _ppod fields are not relevant +// and are ignored, and in reality this macro peforms the same function as +// CYGHWR_HAL_STM32_PIN_IN() for F1 family devices since extra AFIO +// configuration is needed. +// e.g. +// CYGHWR_HAL_STM32_PIN_ALTFN_IN(B,4,6,OPENDRAIN,PULLUP); + +// The CYGHWR_HAL_STM32_PIN_ANALOG() macro defines an analog mode pin. For F1 +// family devices this is for input only, e.g. ADC. + +#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1) + +#define CYGHWR_HAL_STM32_GPIO_CNF_NONE (CYGHWR_HAL_STM32_GPIO_CNF_FLOATING) // Should not be needed for F1 family but ensure HIPERFORMANCE compatible name NONE exists + +#define CYGHWR_HAL_STM32_PIN_OUT(__port,__pin,__ppod,__pupd,__speed) \ + CYGHWR_HAL_STM32_GPIO(__port,__pin,OUT_##__speed,OUT_##__ppod) + +#define CYGHWR_HAL_STM32_PIN_ALTFN_OUT(__port,__pin,__af,__ppod,__pupd,__speed) \ + CYGHWR_HAL_STM32_GPIO(__port,__pin,OUT_##__speed,ALT_##__ppod) + +#define CYGHWR_HAL_STM32_PIN_IN(__port,__pin,__pupd) \ + CYGHWR_HAL_STM32_GPIO(__port,__pin,IN,__pupd) + +#define CYGHWR_HAL_STM32_PIN_ALTFN_IN(__port,__pin,__af,__ppod,__pupd) \ + CYGHWR_HAL_STM32_GPIO(__port,__pin,IN,__pupd) // NOTE: Identical to CYGHWR_HAL_STM32_PIN_IN() at the moment + +#define CYGHWR_HAL_STM32_PIN_ANALOG(__port,__pin) \ + CYGHWR_HAL_STM32_GPIO(__port,__pin,IN,ANALOG) + +#elif defined(CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE) + +#define CYGHWR_HAL_STM32_GPIO_PUPD_FLOATING (CYGHWR_HAL_STM32_GPIO_PUPD_NONE) // Should not be needed for HIPERFORMANCE family but ensure F1 compatible name FLOATING exists + +#define CYGHWR_HAL_STM32_PIN_OUT(__port,__pin,__ppod,__pupd,__speed) \ + CYGHWR_HAL_STM32_GPIO(__port,__pin,GPIO_OUT,0,__ppod,__pupd,__speed) + +#define CYGHWR_HAL_STM32_PIN_ALTFN_OUT(__port,__pin,__af,__ppod,__pupd,__speed) \ + CYGHWR_HAL_STM32_GPIO(__port,__pin,ALTFN,__af,__ppod,__pupd,__speed) + +#define CYGHWR_HAL_STM32_PIN_IN(__port,__pin,__pupd) \ + CYGHWR_HAL_STM32_GPIO(__port,__pin,GPIO_IN,0,NA,__pupd,NA) + +#define CYGHWR_HAL_STM32_PIN_ALTFN_IN(__port,__pin,__af,__ppod,__pupd) \ + CYGHWR_HAL_STM32_GPIO(__port,__pin,ALTFN,__af,__ppod,__pupd,NA) + +#define CYGHWR_HAL_STM32_PIN_ANALOG(__port,__pin) \ + CYGHWR_HAL_STM32_GPIO(__port,__pin,ANALOG,0,NA,NONE,NA) + +#else +#error "Unknown STM32 family for GPIO PIN macros" +#endif + +//----------------------------------------------------------------------------- +// end of var_io_pins.h +#endif // CYGONCE_HAL_VAR_IO_PINS_H diff --git a/ecos/packages/hal/cortexm/stm32/var/current/include/var_io_usart.h b/ecos/packages/hal/cortexm/stm32/var/current/include/var_io_usart.h new file mode 100644 index 0000000..2f00053 --- /dev/null +++ b/ecos/packages/hal/cortexm/stm32/var/current/include/var_io_usart.h @@ -0,0 +1,264 @@ +#ifndef CYGONCE_HAL_VAR_IO_USART_H +#define CYGONCE_HAL_VAR_IO_USART_H +//============================================================================= +// +// var_io_usart.h +// +// USART-specific variant definitions +// +//============================================================================= +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2008, 2009, 2011 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): nickg, jlarmour +// Date: 2008-07-30 +// Purpose: STM32 variant USART specific registers +// Description: +// Usage: Do not include this header file directly. Instead: +// #include <cyg/hal/var_io.h> +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +#ifndef CYGONCE_HAL_VAR_IO_H +# error Do not include var_io_usart.h directly, use var_io.h +#endif + +//============================================================================= +// UARTs + +#define CYGHWR_HAL_STM32_UART_SR 0x00 +#define CYGHWR_HAL_STM32_UART_DR 0x04 +#define CYGHWR_HAL_STM32_UART_BRR 0x08 +#define CYGHWR_HAL_STM32_UART_CR1 0x0C +#define CYGHWR_HAL_STM32_UART_CR2 0x10 +#define CYGHWR_HAL_STM32_UART_CR3 0x14 +#define CYGHWR_HAL_STM32_UART_GTPR 0x18 + +// SR Bits + +#define CYGHWR_HAL_STM32_UART_SR_PE BIT_(0) +#define CYGHWR_HAL_STM32_UART_SR_FE BIT_(1) +#define CYGHWR_HAL_STM32_UART_SR_NE BIT_(2) +#define CYGHWR_HAL_STM32_UART_SR_NF BIT_(2) +#define CYGHWR_HAL_STM32_UART_SR_ORE BIT_(3) +#define CYGHWR_HAL_STM32_UART_SR_IDLE BIT_(4) +#define CYGHWR_HAL_STM32_UART_SR_RXNE BIT_(5) +#define CYGHWR_HAL_STM32_UART_SR_TC BIT_(6) +#define CYGHWR_HAL_STM32_UART_SR_TXE BIT_(7) +#define CYGHWR_HAL_STM32_UART_SR_LBD BIT_(8) +#define CYGHWR_HAL_STM32_UART_SR_CTS BIT_(9) + +// BRR bits + +#define CYGHWR_HAL_STM32_UART_BRR_DIVF(__f) VALUE_(0,__f) +#define CYGHWR_HAL_STM32_UART_BRR_DIVM(__m) VALUE_(4,__m) + +// CR1 bits + +#define CYGHWR_HAL_STM32_UART_CR1_SBK BIT_(0) +#define CYGHWR_HAL_STM32_UART_CR1_RWU BIT_(1) +#define CYGHWR_HAL_STM32_UART_CR1_RE BIT_(2) +#define CYGHWR_HAL_STM32_UART_CR1_TE BIT_(3) +#define CYGHWR_HAL_STM32_UART_CR1_IDLEIE BIT_(4) +#define CYGHWR_HAL_STM32_UART_CR1_RXNEIE BIT_(5) +#define CYGHWR_HAL_STM32_UART_CR1_TCIE BIT_(6) +#define CYGHWR_HAL_STM32_UART_CR1_TXEIE BIT_(7) +#define CYGHWR_HAL_STM32_UART_CR1_PEIE BIT_(8) +#define CYGHWR_HAL_STM32_UART_CR1_PS_EVEN 0 +#define CYGHWR_HAL_STM32_UART_CR1_PS_ODD BIT_(9) +#define CYGHWR_HAL_STM32_UART_CR1_PCE BIT_(10) +#define CYGHWR_HAL_STM32_UART_CR1_WAKE BIT_(11) +#define CYGHWR_HAL_STM32_UART_CR1_M_8 0 +#define CYGHWR_HAL_STM32_UART_CR1_M_9 BIT_(12) +#define CYGHWR_HAL_STM32_UART_CR1_UE BIT_(13) +#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE) +#define CYGHWR_HAL_STM32_UART_CR1_OVER8 BIT_(15) +#endif + +// CR2 bits + +#define CYGHWR_HAL_STM32_UART_CR2_ADD(__a) VALUE_(0,__a) +#define CYGHWR_HAL_STM32_UART_CR2_LBDL BIT_(5) +#define CYGHWR_HAL_STM32_UART_CR2_LBDIE BIT_(6) +#define CYGHWR_HAL_STM32_UART_CR2_LBCL BIT_(8) +#define CYGHWR_HAL_STM32_UART_CR2_CPHA BIT_(9) +#define CYGHWR_HAL_STM32_UART_CR2_CPOL BIT_(10) +#define CYGHWR_HAL_STM32_UART_CR2_CLKEN BIT_(11) +#define CYGHWR_HAL_STM32_UART_CR2_STOP_1 VALUE_(12,0) +#define CYGHWR_HAL_STM32_UART_CR2_STOP_0_5 VALUE_(12,1) +#define CYGHWR_HAL_STM32_UART_CR2_STOP_2 VALUE_(12,2) +#define CYGHWR_HAL_STM32_UART_CR2_STOP_1_5 VALUE_(12,3) +#define CYGHWR_HAL_STM32_UART_CR2_LINEN BIT_(14) + +// CR3 bits + +#define CYGHWR_HAL_STM32_UART_CR3_EIE BIT_(0) +#define CYGHWR_HAL_STM32_UART_CR3_IREN BIT_(1) +#define CYGHWR_HAL_STM32_UART_CR3_IRLP BIT_(2) +#define CYGHWR_HAL_STM32_UART_CR3_HDSEL BIT_(3) +#define CYGHWR_HAL_STM32_UART_CR3_NACK BIT_(4) +#define CYGHWR_HAL_STM32_UART_CR3_SCEN BIT_(5) +#define CYGHWR_HAL_STM32_UART_CR3_DMAR BIT_(6) +#define CYGHWR_HAL_STM32_UART_CR3_DMAT BIT_(7) +#define CYGHWR_HAL_STM32_UART_CR3_RTSE BIT_(8) +#define CYGHWR_HAL_STM32_UART_CR3_CTSE BIT_(9) +#define CYGHWR_HAL_STM32_UART_CR3_CTSIE BIT_(10) + +// GTPR fields + +#define CYGHWR_HAL_STM32_UART_GTPR_PSC(__p) VALUE_(0,__p) +#define CYGHWR_HAL_STM32_UART_GTPR_GT(__g) VALUE_(8,__g) + +// UART GPIO pins + +// NOTE: For those UARTS providing a RTS pin the driver uses HW CTS control but +// manually controls the RTS as a GPIO. + +#ifndef CYGHWR_HAL_STM32_UART0_REMAP +#define CYGHWR_HAL_STM32_UART1_RX CYGHWR_HAL_STM32_PIN_ALTFN_IN( A, 10, 7, NA, FLOATING ) +#define CYGHWR_HAL_STM32_UART1_TX CYGHWR_HAL_STM32_PIN_ALTFN_OUT( A, 9, 7, PUSHPULL, NONE, 50MHZ ) +#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1) +#define CYGHWR_HAL_STM32_UART1_REMAP_CONFIG 0 +#endif // CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1 +#else // CYGHWR_HAL_STM32_UART0_REMAP +#define CYGHWR_HAL_STM32_UART1_RX CYGHWR_HAL_STM32_PIN_ALTFN_IN( B, 7, 7, NA , FLOATING ) +#define CYGHWR_HAL_STM32_UART1_TX CYGHWR_HAL_STM32_PIN_ALTFN_OUT( B, 6, 7, PUSHPULL, NONE, 50MHZ ) +#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1) +#define CYGHWR_HAL_STM32_UART1_REMAP_CONFIG CYGHWR_HAL_STM32_AFIO_MAPR_URT1_RMP +#endif // CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1 +#endif // else CYGHWR_HAL_STM32_UART0_REMAP + +#define CYGHWR_HAL_STM32_UART1_CTS CYGHWR_HAL_STM32_PIN_ALTFN_IN( A, 11, 7, NA, FLOATING ) +#define CYGHWR_HAL_STM32_UART1_RTS CYGHWR_HAL_STM32_PIN_OUT( A, 12, PUSHPULL, NONE, 50MHZ ) + +#define CYGHWR_HAL_STM32_UART1_CLOCK CYGHWR_HAL_STM32_CLOCK( APB2, UART1 ) + +#ifndef CYGHWR_HAL_STM32_UART1_REMAP +#define CYGHWR_HAL_STM32_UART2_RX CYGHWR_HAL_STM32_PIN_ALTFN_IN( A, 3, 7, NA, FLOATING ) +#define CYGHWR_HAL_STM32_UART2_TX CYGHWR_HAL_STM32_PIN_ALTFN_OUT( A, 2, 7, PUSHPULL, NONE, 50MHZ ) +#define CYGHWR_HAL_STM32_UART2_CTS CYGHWR_HAL_STM32_PIN_ALTFN_IN( A, 0, 7, NA, FLOATING ) +#define CYGHWR_HAL_STM32_UART2_RTS CYGHWR_HAL_STM32_PIN_OUT( A, 1, PUSHPULL, NONE, 50MHZ ) +#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1) +#define CYGHWR_HAL_STM32_UART2_REMAP_CONFIG 0 +#endif // CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1 +#else +#define CYGHWR_HAL_STM32_UART2_RX CYGHWR_HAL_STM32_PIN_ALTFN_IN( D, 6, 7, NA, FLOATING ) +#define CYGHWR_HAL_STM32_UART2_TX CYGHWR_HAL_STM32_PIN_ALTFN_OUT( D, 5, 7, PUSHPULL, NONE, 50MHZ ) +#define CYGHWR_HAL_STM32_UART2_CTS CYGHWR_HAL_STM32_PIN_ALTFN_IN( D, 3, 7, NA, FLOATING ) +#define CYGHWR_HAL_STM32_UART2_RTS CYGHWR_HAL_STM32_PIN_OUT( D, 4, PUSHPULL, NONE, 50MHZ ) +#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1) +#define CYGHWR_HAL_STM32_UART2_REMAP_CONFIG CYGHWR_HAL_STM32_AFIO_MAPR_URT2_RMP +#endif // CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1 +#endif + +#define CYGHWR_HAL_STM32_UART2_CLOCK CYGHWR_HAL_STM32_CLOCK( APB1, UART2 ) + +#if defined(CYGHWR_HAL_STM32_UART2_REMAP_PARTIAL) + +#define CYGHWR_HAL_STM32_UART3_RX CYGHWR_HAL_STM32_PIN_ALTFN_IN( C, 11, 7, NA, FLOATING ) +#define CYGHWR_HAL_STM32_UART3_TX CYGHWR_HAL_STM32_PIN_ALTFN_OUT( C, 10, 7, PUSHPULL, NONE, 50MHZ ) +#define CYGHWR_HAL_STM32_UART3_CTS CYGHWR_HAL_STM32_PIN_ALTFN_IN( B, 13, 7, NA, FLOATING ) +#define CYGHWR_HAL_STM32_UART3_RTS CYGHWR_HAL_STM32_PIN_OUT( B, 14, PUSHPULL, NONE, 50MHZ ) + +#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1) +#define CYGHWR_HAL_STM32_UART3_REMAP_CONFIG CYGHWR_HAL_STM32_AFIO_MAPR_URT3_P1_RMP +#endif // CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1 + +#elif defined(CYGHWR_HAL_STM32_UART2_REMAP_FULL) + +#define CYGHWR_HAL_STM32_UART3_RX CYGHWR_HAL_STM32_PIN_ALTFN_IN( D, 9, 7, NA, FLOATING ) +#define CYGHWR_HAL_STM32_UART3_TX CYGHWR_HAL_STM32_PIN_ALTFN_OUT( D, 8, 7, PUSHPULL, NONE, 50MHZ ) +#define CYGHWR_HAL_STM32_UART3_CTS CYGHWR_HAL_STM32_PIN_ALTFN_IN( D, 11, 7, NA, FLOATING ) +#define CYGHWR_HAL_STM32_UART3_RTS CYGHWR_HAL_STM32_PIN_OUT( D, 12, PUSHPULL, NONE, 50MHZ ) + +#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1) +#define CYGHWR_HAL_STM32_UART3_REMAP_CONFIG CYGHWR_HAL_STM32_AFIO_MAPR_URT3_FL_RMP +#endif // CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1 + +#else + +#define CYGHWR_HAL_STM32_UART3_RX CYGHWR_HAL_STM32_PIN_ALTFN_IN( B, 11, 7, NA, FLOATING ) +#define CYGHWR_HAL_STM32_UART3_TX CYGHWR_HAL_STM32_PIN_ALTFN_OUT( B, 10, 7, PUSHPULL, NONE, 50MHZ ) +#define CYGHWR_HAL_STM32_UART3_CTS CYGHWR_HAL_STM32_PIN_ALTFN_IN( B, 13, 7, NA, FLOATING ) +#define CYGHWR_HAL_STM32_UART3_RTS CYGHWR_HAL_STM32_PIN_OUT( B, 14, PUSHPULL, NONE, 50MHZ ) + +#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1) +#define CYGHWR_HAL_STM32_UART3_REMAP_CONFIG CYGHWR_HAL_STM32_AFIO_MAPR_URT3_NO_RMP +#endif // CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1 + +#endif + +#define CYGHWR_HAL_STM32_UART3_CLOCK CYGHWR_HAL_STM32_CLOCK( APB1, UART3 ) + +#define CYGHWR_HAL_STM32_UART4_RX CYGHWR_HAL_STM32_PIN_ALTFN_IN( C, 11, 8, NA, FLOATING ) +#define CYGHWR_HAL_STM32_UART4_TX CYGHWR_HAL_STM32_PIN_ALTFN_OUT( C, 10, 8, PUSHPULL, NONE, 50MHZ ) +#define CYGHWR_HAL_STM32_UART4_CTS CYGHWR_HAL_STM32_GPIO_NONE +#define CYGHWR_HAL_STM32_UART4_RTS CYGHWR_HAL_STM32_GPIO_NONE +#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1) +#define CYGHWR_HAL_STM32_UART4_REMAP_CONFIG 0 +#endif // CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1 + +#define CYGHWR_HAL_STM32_UART4_CLOCK CYGHWR_HAL_STM32_CLOCK( APB1, UART4 ) + +#define CYGHWR_HAL_STM32_UART5_RX CYGHWR_HAL_STM32_PIN_ALTFN_IN( D, 2, 8, NA, FLOATING ) +#define CYGHWR_HAL_STM32_UART5_TX CYGHWR_HAL_STM32_PIN_ALTFN_OUT( C, 12, 8, PUSHPULL, NONE, 50MHZ ) +#define CYGHWR_HAL_STM32_UART5_CTS CYGHWR_HAL_STM32_GPIO_NONE +#define CYGHWR_HAL_STM32_UART5_RTS CYGHWR_HAL_STM32_GPIO_NONE +#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1) +#define CYGHWR_HAL_STM32_UART5_REMAP_CONFIG 0 +#endif // CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1 + +#define CYGHWR_HAL_STM32_UART5_CLOCK CYGHWR_HAL_STM32_CLOCK( APB1, UART5 ) + +#if defined(CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE) + +#define CYGHWR_HAL_STM32_UART6_RX CYGHWR_HAL_STM32_PIN_ALTFN_IN( C, 7, 8, NA, NONE ) +#define CYGHWR_HAL_STM32_UART6_TX CYGHWR_HAL_STM32_PIN_ALTFN_OUT( C, 6, 8, PUSHPULL, NONE, 50MHZ ) +#define CYGHWR_HAL_STM32_UART6_CTS CYGHWR_HAL_STM32_PIN_ALTFN_IN( G, 15, 8, NA, NONE ) +#define CYGHWR_HAL_STM32_UART6_RTS CYGHWR_HAL_STM32_PIN_ALTFN_OUT( G, 8, 8, PUSHPULL, NONE, 50MHZ ) +#define CYGHWR_HAL_STM32_UART6_CLOCK CYGHWR_HAL_STM32_CLOCK( APB2, UART6 ) + +#endif // CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE + +#ifndef __ASSEMBLER__ + +__externC void hal_stm32_uart_setbaud( CYG_ADDRESS uart, cyg_uint32 baud ); + +#endif + +#endif // CYGONCE_HAL_VAR_IO_USART_H +//----------------------------------------------------------------------------- +// end of var_io_usart.h diff --git a/ecos/packages/hal/cortexm/stm32/var/current/include/variant.inc b/ecos/packages/hal/cortexm/stm32/var/current/include/variant.inc new file mode 100644 index 0000000..4c72d2e --- /dev/null +++ b/ecos/packages/hal/cortexm/stm32/var/current/include/variant.inc @@ -0,0 +1,54 @@ +/*========================================================================== +// +// variant.inc +// +// Variant specific asm definitions +// +//========================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2008 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): nickg +// Date: 2008-07-30 +// Description: +// +//####DESCRIPTIONEND#### +// +//========================================================================*/ + +#include <pkgconf/hal_cortexm_stm32.h> + +//========================================================================== +// EOF variant.inc + diff --git a/ecos/packages/hal/cortexm/stm32/var/current/src/hal_diag.c b/ecos/packages/hal/cortexm/stm32/var/current/src/hal_diag.c new file mode 100644 index 0000000..1049de1 --- /dev/null +++ b/ecos/packages/hal/cortexm/stm32/var/current/src/hal_diag.c @@ -0,0 +1,434 @@ +/*============================================================================= +// +// hal_diag.c +// +// HAL diagnostic output code +// +//============================================================================= +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2004, 2005, 2006, 2008 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): nickg +// Date: 2008-07-30 +// Purpose: HAL diagnostic output +// Description: Implementations of HAL diagnostic output support. +// +//####DESCRIPTIONEND#### +// +//===========================================================================*/ + +#include <pkgconf/hal.h> +#include CYGBLD_HAL_PLATFORM_H + +#include <cyg/infra/cyg_type.h> // base types +#include <cyg/infra/cyg_trac.h> // tracing + +#include <cyg/hal/hal_arch.h> // SAVE/RESTORE GP macros +#include <cyg/hal/hal_io.h> // IO macros +#include <cyg/hal/hal_if.h> // interface API +#include <cyg/hal/hal_intr.h> // HAL_ENABLE/MASK/UNMASK_INTERRUPTS +#include <cyg/hal/hal_misc.h> // Helper functions +#include <cyg/hal/drv_api.h> // CYG_ISR_HANDLED + +#include <cyg/hal/var_io.h> // USART registers + +//----------------------------------------------------------------------------- + +typedef struct { + cyg_uint32 uart; + CYG_ADDRESS base; + cyg_int32 msec_timeout; + int isr_vector; + cyg_uint32 rxpin; + cyg_uint32 txpin; + cyg_uint32 clkena; +#if defined(CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1) + cyg_uint32 remap; +#endif + cyg_uint32 baud_rate; + int irq_state; + +} channel_data_t; + +// If remap isn't supported (e.g. F2/F4 parts) just #define to nothing. The struct initialiser will still work. +#ifndef CYGHWR_HAL_STM32_UART1_REMAP_CONFIG +#define CYGHWR_HAL_STM32_UART1_REMAP_CONFIG +#endif +#ifndef CYGHWR_HAL_STM32_UART2_REMAP_CONFIG +#define CYGHWR_HAL_STM32_UART2_REMAP_CONFIG +#endif +#ifndef CYGHWR_HAL_STM32_UART3_REMAP_CONFIG +#define CYGHWR_HAL_STM32_UART3_REMAP_CONFIG +#endif +#ifndef CYGHWR_HAL_STM32_UART4_REMAP_CONFIG +#define CYGHWR_HAL_STM32_UART4_REMAP_CONFIG +#endif +#ifndef CYGHWR_HAL_STM32_UART5_REMAP_CONFIG +#define CYGHWR_HAL_STM32_UART5_REMAP_CONFIG +#endif + +static channel_data_t stm32_ser_channels[] = { +#if CYGINT_HAL_STM32_UART0>0 + { 0, CYGHWR_HAL_STM32_UART1, 1000, CYGNUM_HAL_INTERRUPT_UART1, CYGHWR_HAL_STM32_UART1_RX, CYGHWR_HAL_STM32_UART1_TX, + CYGHWR_HAL_STM32_UART1_CLOCK, CYGHWR_HAL_STM32_UART1_REMAP_CONFIG }, +#endif +#if CYGINT_HAL_STM32_UART1>0 + { 1, CYGHWR_HAL_STM32_UART2, 1000, CYGNUM_HAL_INTERRUPT_UART2, CYGHWR_HAL_STM32_UART2_RX, CYGHWR_HAL_STM32_UART2_TX, + CYGHWR_HAL_STM32_UART2_CLOCK, CYGHWR_HAL_STM32_UART2_REMAP_CONFIG }, +#endif +#if CYGINT_HAL_STM32_UART2>0 + { 2, CYGHWR_HAL_STM32_UART3, 1000, CYGNUM_HAL_INTERRUPT_UART3, CYGHWR_HAL_STM32_UART3_RX, CYGHWR_HAL_STM32_UART3_TX, + CYGHWR_HAL_STM32_UART3_CLOCK, CYGHWR_HAL_STM32_UART3_REMAP_CONFIG }, +#endif +#if CYGINT_HAL_STM32_UART3>0 + { 3, CYGHWR_HAL_STM32_UART4, 1000, CYGNUM_HAL_INTERRUPT_UART4, CYGHWR_HAL_STM32_UART4_RX, CYGHWR_HAL_STM32_UART4_TX, + CYGHWR_HAL_STM32_UART4_CLOCK, CYGHWR_HAL_STM32_UART4_REMAP_CONFIG }, +#endif +#if CYGINT_HAL_STM32_UART4>0 + { 4, CYGHWR_HAL_STM32_UART5, 1000, CYGNUM_HAL_INTERRUPT_UART5, CYGHWR_HAL_STM32_UART5_RX, CYGHWR_HAL_STM32_UART5_TX, + CYGHWR_HAL_STM32_UART5_CLOCK, CYGHWR_HAL_STM32_UART5_REMAP_CONFIG }, +#endif +#if CYGINT_HAL_STM32_UART5>0 + { 5, CYGHWR_HAL_STM32_UART6, 1000, CYGNUM_HAL_INTERRUPT_UART6, CYGHWR_HAL_STM32_UART6_RX, CYGHWR_HAL_STM32_UART6_TX, + CYGHWR_HAL_STM32_UART6_CLOCK }, // UART6 only supported on F2/F4 so no remap config needed. +#endif +}; + +//----------------------------------------------------------------------------- + +static void +hal_stm32_serial_init_channel(void* __ch_data) +{ + channel_data_t *chan = (channel_data_t*)__ch_data; + CYG_ADDRESS base = chan->base; + cyg_uint32 cr1, cr2; + + // Enable the PIO lines for the serial channel + + CYGHWR_HAL_STM32_GPIO_SET( chan->rxpin ); + CYGHWR_HAL_STM32_GPIO_SET( chan->txpin ); + CYGHWR_HAL_STM32_CLOCK_ENABLE( chan->clkena ); + +#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1) + if( chan->remap != 0 ) + { + CYG_ADDRESS afio = CYGHWR_HAL_STM32_AFIO; + cyg_uint32 mapr; + CYGHWR_HAL_STM32_CLOCK_ENABLE( CYGHWR_HAL_STM32_AFIO_CLOCK ); + HAL_READ_UINT32( afio+CYGHWR_HAL_STM32_AFIO_MAPR, mapr ); + mapr |= chan->remap; + HAL_WRITE_UINT32( afio+CYGHWR_HAL_STM32_AFIO_MAPR, mapr ); + } +#endif // if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1) + + cr2 = CYGHWR_HAL_STM32_UART_CR2_STOP_1; + HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_UART_CR2, cr2 ); + + cr1 = CYGHWR_HAL_STM32_UART_CR1_M_8; + cr1 |= CYGHWR_HAL_STM32_UART_CR1_TE | CYGHWR_HAL_STM32_UART_CR1_RE; + HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_UART_CR1, cr1 ); + + // Set up Baud rate + chan->baud_rate = CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD; + hal_stm32_uart_setbaud( base, chan->baud_rate ); + + // Enable the uart + cr1 |= CYGHWR_HAL_STM32_UART_CR1_UE; + HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_UART_CR1, cr1 ); + +} + +void +hal_stm32_serial_putc(void *__ch_data, char c) +{ + CYG_ADDRESS base = ((channel_data_t*)__ch_data)->base; + cyg_uint32 sr; + CYGARC_HAL_SAVE_GP(); + + do + { + HAL_READ_UINT32( base + CYGHWR_HAL_STM32_UART_SR, sr ); + } while ((sr & CYGHWR_HAL_STM32_UART_SR_TXE) == 0); + + HAL_WRITE_UINT32( base + CYGHWR_HAL_STM32_UART_DR, c ); + + CYGARC_HAL_RESTORE_GP(); +} + +static cyg_bool +hal_stm32_serial_getc_nonblock(void* __ch_data, cyg_uint8* ch) +{ + CYG_ADDRESS base = ((channel_data_t*)__ch_data)->base; + cyg_uint32 sr; + cyg_uint32 c; + CYGARC_HAL_SAVE_GP(); + + HAL_READ_UINT32( base + CYGHWR_HAL_STM32_UART_SR, sr ); + + if( (sr & CYGHWR_HAL_STM32_UART_SR_RXNE) == 0 ) + return false; + + HAL_READ_UINT32( base + CYGHWR_HAL_STM32_UART_DR, c ); + + *ch = (cyg_uint8)c; + + CYGARC_HAL_RESTORE_GP(); + + return true; +} + +cyg_uint8 +hal_stm32_serial_getc(void* __ch_data) +{ + cyg_uint8 ch; + CYGARC_HAL_SAVE_GP(); + + while(!hal_stm32_serial_getc_nonblock(__ch_data, &ch)); + + CYGARC_HAL_RESTORE_GP(); + return ch; +} + +//============================================================================= +// Virtual vector HAL diagnostics + +#if defined(CYGSEM_HAL_VIRTUAL_VECTOR_DIAG) + +static void +hal_stm32_serial_write(void* __ch_data, const cyg_uint8* __buf, + cyg_uint32 __len) +{ + CYGARC_HAL_SAVE_GP(); + + while(__len-- > 0) + hal_stm32_serial_putc(__ch_data, *__buf++); + + CYGARC_HAL_RESTORE_GP(); +} + +static void +hal_stm32_serial_read(void* __ch_data, cyg_uint8* __buf, cyg_uint32 __len) +{ + CYGARC_HAL_SAVE_GP(); + + while(__len-- > 0) + *__buf++ = hal_stm32_serial_getc(__ch_data); + + CYGARC_HAL_RESTORE_GP(); +} + +cyg_bool +hal_stm32_serial_getc_timeout(void* __ch_data, cyg_uint8* ch) +{ + int delay_count; + channel_data_t* chan = (channel_data_t*)__ch_data; + cyg_bool res; + CYGARC_HAL_SAVE_GP(); + + delay_count = chan->msec_timeout * 100; // delay in 10 us steps + + for(;;) { + res = hal_stm32_serial_getc_nonblock(__ch_data, ch); + if (res || 0 == delay_count--) + break; + + CYGACC_CALL_IF_DELAY_US(10); + } + + CYGARC_HAL_RESTORE_GP(); + return res; +} + +static int +hal_stm32_serial_control(void *__ch_data, __comm_control_cmd_t __func, ...) +{ + channel_data_t* chan = (channel_data_t*)__ch_data; + CYG_ADDRESS base = ((channel_data_t*)__ch_data)->base; + int ret = 0; + cyg_uint32 cr1; + + va_list ap; + + CYGARC_HAL_SAVE_GP(); + + va_start(ap, __func); + + switch (__func) { + case __COMMCTL_IRQ_ENABLE: + chan->irq_state = 1; + HAL_INTERRUPT_ACKNOWLEDGE( chan->isr_vector ); + HAL_INTERRUPT_UNMASK( chan->isr_vector ); + HAL_READ_UINT32( base+CYGHWR_HAL_STM32_UART_CR1, cr1 ); + cr1 |= CYGHWR_HAL_STM32_UART_CR1_RXNEIE; + HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_UART_CR1, cr1 ); + break; + case __COMMCTL_IRQ_DISABLE: + ret = chan->irq_state; + chan->irq_state = 0; + HAL_INTERRUPT_MASK( chan->isr_vector ); + HAL_READ_UINT32( base+CYGHWR_HAL_STM32_UART_CR1, cr1 ); + cr1 &= ~CYGHWR_HAL_STM32_UART_CR1_RXNEIE; + HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_UART_CR1, cr1 ); + break; + case __COMMCTL_DBG_ISR_VECTOR: + ret = chan->isr_vector; + break; + case __COMMCTL_SET_TIMEOUT: + { + va_list ap; + + va_start(ap, __func); + + ret = chan->msec_timeout; + chan->msec_timeout = va_arg(ap, cyg_uint32); + + va_end(ap); + } + case __COMMCTL_GETBAUD: + ret = chan->baud_rate; + break; + case __COMMCTL_SETBAUD: + chan->baud_rate = va_arg(ap, cyg_int32); + // Should we verify this value here? + hal_stm32_uart_setbaud( base, chan->baud_rate ); + ret = 0; + break; + default: + break; + } + va_end(ap); + CYGARC_HAL_RESTORE_GP(); + return ret; +} + +static int +hal_stm32_serial_isr(void *__ch_data, int* __ctrlc, + CYG_ADDRWORD __vector, CYG_ADDRWORD __data) +{ + channel_data_t* chan = (channel_data_t*)__ch_data; + cyg_uint8 ch; + + CYGARC_HAL_SAVE_GP(); + + *__ctrlc = 0; + + if( hal_stm32_serial_getc_nonblock(__ch_data, &ch) ) + { + if( cyg_hal_is_break( (char *)&ch , 1 ) ) + *__ctrlc = 1; + } + + HAL_INTERRUPT_ACKNOWLEDGE(chan->isr_vector); + + CYGARC_HAL_RESTORE_GP(); + return 1; +} + +static void +hal_stm32_serial_init(void) +{ + hal_virtual_comm_table_t* comm; + int cur; + int i; + + cur = CYGACC_CALL_IF_SET_CONSOLE_COMM(CYGNUM_CALL_IF_SET_COMM_ID_QUERY_CURRENT); + + for( i = 0; i < CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS ; i++ ) + { + hal_stm32_serial_init_channel(&stm32_ser_channels[i]); + + CYGACC_CALL_IF_SET_CONSOLE_COMM(i); + comm = CYGACC_CALL_IF_CONSOLE_PROCS(); + CYGACC_COMM_IF_CH_DATA_SET(*comm, &stm32_ser_channels[i]); + CYGACC_COMM_IF_WRITE_SET(*comm, hal_stm32_serial_write); + CYGACC_COMM_IF_READ_SET(*comm, hal_stm32_serial_read); + CYGACC_COMM_IF_PUTC_SET(*comm, hal_stm32_serial_putc); + CYGACC_COMM_IF_GETC_SET(*comm, hal_stm32_serial_getc); + CYGACC_COMM_IF_CONTROL_SET(*comm, hal_stm32_serial_control); + CYGACC_COMM_IF_DBG_ISR_SET(*comm, hal_stm32_serial_isr); + CYGACC_COMM_IF_GETC_TIMEOUT_SET(*comm, hal_stm32_serial_getc_timeout); + } + + // Restore original console + CYGACC_CALL_IF_SET_CONSOLE_COMM(cur); + + // set debug channel baud rate if different +#if (CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD != CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_BAUD) + stm32_ser_channels[CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL]->baud_rate = + CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_BAUD; + update_baud_rate( &stm32_ser_channels[CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL] ); +#endif + +} + +void +cyg_hal_plf_comms_init(void) +{ + static int initialized = 0; + + if (initialized) + return; + + initialized = 1; + + hal_stm32_serial_init(); +} + +#endif + +//============================================================================= +// Non-Virtual vector HAL diagnostics + +#if !defined(CYGSEM_HAL_VIRTUAL_VECTOR_DIAG) + +void hal_stm32_diag_init(void) +{ + hal_stm32_serial_init( &stm32_ser_channels[CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL] ); +} + +void hal_stm32_diag_putc(char c) +{ + hal_stm32_serial_putc( &stm32_ser_channels[CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL], c); +} + +cyg_uint8 hal_stm32_diag_getc(void) +{ + return hal_stm32_serial_getc( &stm32_ser_channels[CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL] ); +} + + +#endif + +//----------------------------------------------------------------------------- +// End of hal_diag.c diff --git a/ecos/packages/hal/cortexm/stm32/var/current/src/stm32_dma.c b/ecos/packages/hal/cortexm/stm32/var/current/src/stm32_dma.c new file mode 100644 index 0000000..78a869d --- /dev/null +++ b/ecos/packages/hal/cortexm/stm32/var/current/src/stm32_dma.c @@ -0,0 +1,308 @@ +/*============================================================================= +// +// stm32_dma.c +// +// STM32 DMA support +// +//============================================================================= +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2011 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): nickg +// Contributors: +// Date: 2009-10-11 +// Purpose: STM32 DMA support +// Description: This file provides the implementation for the STM32's +// on-chip DMA controllers. +// +//####DESCRIPTIONEND#### +// +//===========================================================================*/ + +#include <pkgconf/system.h> +#include <pkgconf/hal_cortexm_stm32.h> + +#include <cyg/hal/hal_io.h> +#include <cyg/hal/hal_intr.h> +#include <cyg/hal/var_dma.h> + +#include <cyg/infra/diag.h> +#include <cyg/infra/cyg_ass.h> + +//============================================================================= + +#if 0 +#define dma_diag( __fmt, ... ) diag_printf("DMA: %20s[%3d]: " __fmt, __FUNCTION__, __LINE__, ## __VA_ARGS__ ); +#define dma_dump_buf(__addr, __size ) diag_dump_buf( __addr, __size ) +#else +#define dma_diag( __fmt, ... ) +#define dma_dump_buf(__addr, __size ) +#endif + +//============================================================================= + +static const struct +{ + CYG_ADDRWORD base; + cyg_uint32 clock; +} hal_stm32_dma_controller[] = +{ + { 0, 0 }, + { CYGHWR_HAL_STM32_DMA1, CYGHWR_HAL_STM32_DMA1_CLOCK }, + { CYGHWR_HAL_STM32_DMA2, CYGHWR_HAL_STM32_DMA2_CLOCK }, +}; + +//----------------------------------------------------------------------------- + +static cyg_uint32 hal_stm32_dma_isr( cyg_vector_t vector, CYG_ADDRWORD data ) +{ + hal_stm32_dma_stream *stream = (hal_stm32_dma_stream *)data; + cyg_uint32 ret = CYG_ISR_HANDLED; + cyg_uint32 isr; + + HAL_READ_UINT32( stream->ctlr+CYGHWR_HAL_STM32_DMA_ISR_REG(stream->stream), isr ); + + dma_diag("ctlr %08x stream %d chan %d isr %08x\n", stream->ctlr, stream->stream, + CYGHWR_HAL_STM32_DMA_CHANNEL(stream->desc), isr ); + + if( isr & CYGHWR_HAL_STM32_DMA_ISR_TCIF(stream->stream) ) + { + // Clear all stream interrupt bits + HAL_WRITE_UINT32( stream->ctlr+CYGHWR_HAL_STM32_DMA_IFCR_REG(stream->stream), + CYGHWR_HAL_STM32_DMA_IFCR_MASK(stream->stream) ); + + if( (stream->ccr & CYGHWR_HAL_STM32_DMA_CCR_CIRC) == 0) + { + // Disable the stream + HAL_WRITE_UINT32( stream->ctlr+CYGHWR_HAL_STM32_DMA_CCR(stream->stream), 0 ); + } + + // Update the count + HAL_READ_UINT32( stream->ctlr+CYGHWR_HAL_STM32_DMA_CNDTR(stream->stream), stream->count ); + + ret = CYG_ISR_CALL_DSR; + } + + return ret; +} + +//----------------------------------------------------------------------------- + +static void hal_stm32_dma_dsr( cyg_vector_t vector, cyg_ucount32 count, CYG_ADDRWORD data ) +{ + hal_stm32_dma_stream *stream = (hal_stm32_dma_stream *)data; + + dma_diag("ctlr %08x stream %d chan %d\n", stream->ctlr, stream->stream, + CYGHWR_HAL_STM32_DMA_CHANNEL(stream->desc) ); + + stream->callback( stream, stream->count, stream->data ); + + stream->active = false; +} + +//----------------------------------------------------------------------------- + +void hal_stm32_dma_init( hal_stm32_dma_stream *stream, int pri ) +{ + stream->ctlr = hal_stm32_dma_controller[CYGHWR_HAL_STM32_DMA_CONTROLLER(stream->desc)].base; + stream->stream = CYGHWR_HAL_STM32_DMA_STREAM(stream->desc); + + dma_diag("ctlr %08x stream %d chan %d pri %d\n", stream->ctlr, stream->stream, + CYGHWR_HAL_STM32_DMA_CHANNEL(stream->desc), pri ); + + cyg_drv_interrupt_create( CYGHWR_HAL_STM32_DMA_INTERRUPT(stream->desc), + pri, + (CYG_ADDRWORD)stream, + hal_stm32_dma_isr, + hal_stm32_dma_dsr, + &stream->handle, + &stream->interrupt ); + cyg_drv_interrupt_attach( stream->handle ); + cyg_drv_interrupt_unmask( CYGHWR_HAL_STM32_DMA_INTERRUPT(stream->desc) ); + + // Enable DMA controller clock + CYGHWR_HAL_STM32_CLOCK_ENABLE( hal_stm32_dma_controller[CYGHWR_HAL_STM32_DMA_CONTROLLER(stream->desc)].clock ); + + + // Clear CCR, disable channel and put into known state + HAL_WRITE_UINT32(stream->ctlr+CYGHWR_HAL_STM32_DMA_CCR(stream->stream), 0 ); + + + // Initialize a private copy of the CCR, we don't write this to + // the hardware until we are ready to start the transfer. + + stream->ccr = CYGHWR_HAL_STM32_DMA_CCR_EN; + +#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE) + // Select channel number in F2/F4 variants. The F1 variants simply + // have the various device DMA request lines wire-ORed together. + stream->ccr |= CYGHWR_HAL_STM32_DMA_CCR_CHSEL(CYGHWR_HAL_STM32_DMA_CHANNEL(stream->desc)); +#endif + + // Set stream direction + if( CYGHWR_HAL_STM32_DMA_MODE(stream->desc) == CYGHWR_HAL_STM32_DMA_MODE_M2P ) + stream->ccr |= CYGHWR_HAL_STM32_DMA_CCR_MEM2P; + + // Set memory increment mode + stream->ccr |= CYGHWR_HAL_STM32_DMA_CCR_MINC; + + // Transfer end interrupt enable + stream->ccr |= CYGHWR_HAL_STM32_DMA_CCR_TCIE; + + // Use top 2 bits of priority to define DMA stream priority + stream->ccr |= CYGHWR_HAL_STM32_DMA_CCR_PL((pri>>6)&3); + + dma_diag("ccr %08x\n", stream->ccr); +} + +//----------------------------------------------------------------------------- + +void hal_stm32_dma_delete( hal_stm32_dma_stream *stream ) +{ + dma_diag("ctlr %08x stream %d chan %d\n", stream->ctlr, stream->stream, + CYGHWR_HAL_STM32_DMA_CHANNEL(stream->desc) ); + + // Clear CCR, disables stream + HAL_WRITE_UINT32(stream->ctlr+CYGHWR_HAL_STM32_DMA_CCR(stream->stream), 0 ); + + // Mask, detach and delete interrupt object + cyg_drv_interrupt_mask( CYGHWR_HAL_STM32_DMA_INTERRUPT(stream->desc) ); + cyg_drv_interrupt_detach( stream->handle ); + cyg_drv_interrupt_delete( stream->handle ); +} + +//----------------------------------------------------------------------------- + +void hal_stm32_dma_disable( hal_stm32_dma_stream *stream ) +{ + dma_diag("ctlr %08x stream %d chan %d\n", stream->ctlr, stream->stream, + CYGHWR_HAL_STM32_DMA_CHANNEL(stream->desc) ); + + // Clear CCR, disables stream + HAL_WRITE_UINT32(stream->ctlr+CYGHWR_HAL_STM32_DMA_CCR(stream->stream), 0 ); +} + +//----------------------------------------------------------------------------- + +void hal_stm32_dma_poll( hal_stm32_dma_stream *stream ) +{ +// dma_diag("ctlr %08x stream %d chan %d\n", stream->ctlr, stream->stream, +// CYGHWR_HAL_STM32_DMA_CHANNEL(stream->desc) ); + + if( stream->active ) + if( hal_stm32_dma_isr( CYGHWR_HAL_STM32_DMA_INTERRUPT(stream->desc), (CYG_ADDRWORD)stream ) & CYG_ISR_CALL_DSR ) + hal_stm32_dma_dsr( CYGHWR_HAL_STM32_DMA_INTERRUPT(stream->desc), 1, (CYG_ADDRWORD)stream ); +} + +//----------------------------------------------------------------------------- + +void hal_stm32_dma_configure( hal_stm32_dma_stream *stream, int tfr_size, cyg_bool no_minc, cyg_bool polled ) +{ + dma_diag("ctlr %08x stream %d chan %d tfr_size %d no_minc %d polled %d\n", stream->ctlr, stream->stream, + CYGHWR_HAL_STM32_DMA_CHANNEL(stream->desc), tfr_size, no_minc, polled ); + + if( tfr_size == 8 ) + stream->ccr |= CYGHWR_HAL_STM32_DMA_CCR_PSIZE8 | CYGHWR_HAL_STM32_DMA_CCR_MSIZE8; + else if( tfr_size == 16 ) + stream->ccr |= CYGHWR_HAL_STM32_DMA_CCR_PSIZE16 | CYGHWR_HAL_STM32_DMA_CCR_MSIZE16; + else + stream->ccr |= CYGHWR_HAL_STM32_DMA_CCR_PSIZE32 | CYGHWR_HAL_STM32_DMA_CCR_MSIZE32; + + // Clear MINC bit if not wanted + if( no_minc ) + stream->ccr &= ~CYGHWR_HAL_STM32_DMA_CCR_MINC; + else + stream->ccr |= CYGHWR_HAL_STM32_DMA_CCR_MINC; + + // Clear interrupt enables if polled mode, otherwise enable them + if( polled ) + stream->ccr &= ~(CYGHWR_HAL_STM32_DMA_CCR_TCIE | CYGHWR_HAL_STM32_DMA_CCR_TEIE); + else + stream->ccr |= CYGHWR_HAL_STM32_DMA_CCR_TCIE | CYGHWR_HAL_STM32_DMA_CCR_TEIE; +} + +//----------------------------------------------------------------------------- + +void hal_stm32_dma_configure_circular( hal_stm32_dma_stream *stream, cyg_bool enable) +{ + if (enable) { + stream->ccr |= CYGHWR_HAL_STM32_DMA_CCR_CIRC; + } else { + stream->ccr &= ~CYGHWR_HAL_STM32_DMA_CCR_CIRC; + } +} + +//----------------------------------------------------------------------------- + +void hal_stm32_dma_start( hal_stm32_dma_stream *stream, void *memory, CYG_ADDRESS peripheral, cyg_uint32 size ) +{ + dma_diag("ctlr %08x stream %d chan %d mem %08x peri %08x size %d\n", stream->ctlr, stream->stream, + CYGHWR_HAL_STM32_DMA_CHANNEL(stream->desc), memory, peripheral, size ); + + HAL_WRITE_UINT32(stream->ctlr+CYGHWR_HAL_STM32_DMA_CMAR(stream->stream), (cyg_uint32)memory ); + + HAL_WRITE_UINT32(stream->ctlr+CYGHWR_HAL_STM32_DMA_CPAR(stream->stream), peripheral ); + + HAL_WRITE_UINT32(stream->ctlr+CYGHWR_HAL_STM32_DMA_CNDTR(stream->stream), size ); + + HAL_WRITE_UINT32(stream->ctlr+CYGHWR_HAL_STM32_DMA_CCR(stream->stream), stream->ccr ); + + stream->active = true; +} + +//============================================================================= + +void hal_stm32_dma_show( hal_stm32_dma_stream *stream ) +{ + cyg_uint32 dma = stream->ctlr; + cyg_uint32 chan = stream->stream; + cyg_uint32 reg; + + dma_diag("ctlr %08x stream %d chan %d\n", stream->ctlr, stream->stream, + CYGHWR_HAL_STM32_DMA_CHANNEL(stream->desc) ); + dma_diag("vector %d stream->ccr %08x\n", CYGHWR_HAL_STM32_DMA_INTERRUPT(stream->desc), stream->ccr ); + + HAL_READ_UINT32( dma+CYGHWR_HAL_STM32_DMA_ISR_REG(chan), reg ); + dma_diag("DMA ISR: %08x\n", reg ); + + HAL_READ_UINT32( dma+CYGHWR_HAL_STM32_DMA_CCR(chan), reg ); dma_diag("DMA %d CCR: %08x\n", chan, reg ); + HAL_READ_UINT32( dma+CYGHWR_HAL_STM32_DMA_CNDTR(chan), reg ); dma_diag("DMA %d CNDTR: %08x\n", chan, reg ); + HAL_READ_UINT32( dma+CYGHWR_HAL_STM32_DMA_CPAR(chan), reg ); dma_diag("DMA %d CPAR: %08x\n", chan, reg ); + HAL_READ_UINT32( dma+CYGHWR_HAL_STM32_DMA_CMAR(chan), reg ); dma_diag("DMA %d CMAR: %08x\n", chan, reg ); + +} + + +//============================================================================= +/* EOF stm32_dma.c */ diff --git a/ecos/packages/hal/cortexm/stm32/var/current/src/stm32_misc.c b/ecos/packages/hal/cortexm/stm32/var/current/src/stm32_misc.c new file mode 100644 index 0000000..df624a3 --- /dev/null +++ b/ecos/packages/hal/cortexm/stm32/var/current/src/stm32_misc.c @@ -0,0 +1,574 @@ +/*========================================================================== +// +// stm32_misc.c +// +// Cortex-M STM32 HAL functions +// +//========================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2008, 2009, 2011, 2014 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): nickg +// Contributors: jld +// Date: 2008-07-30 +// Description: +// +//####DESCRIPTIONEND#### +// +//========================================================================*/ + +#include <pkgconf/hal.h> +#include <pkgconf/hal_cortexm.h> +#include <pkgconf/hal_cortexm_stm32.h> +#ifdef CYGPKG_KERNEL +#include <pkgconf/kernel.h> +#endif + +#include <cyg/infra/diag.h> +#include <cyg/infra/cyg_type.h> +#include <cyg/infra/cyg_trac.h> // tracing macros +#include <cyg/infra/cyg_ass.h> // assertion macros + +#include <cyg/hal/hal_arch.h> // HAL header +#include <cyg/hal/hal_intr.h> // HAL header +#include <cyg/hal/hal_if.h> // HAL header + +#ifdef CYGFUN_HAL_CORTEXM_STM32_PROFILE_TIMER +#include <cyg/hal/drv_api.h> // CYG_ISR_HANDLED +#include <cyg/profile/profile.h> // __profile_hit() +#endif + +//========================================================================== +// Clock Initialization values + +#if CYGHWR_HAL_CORTEXM_STM32_CLOCK_HCLK_DIV == 1 +# define CYGHWR_HAL_STM32_RCC_CFGR_HPRE CYGHWR_HAL_STM32_RCC_CFGR_HPRE_1 +#elif CYGHWR_HAL_CORTEXM_STM32_CLOCK_HCLK_DIV == 2 +# define CYGHWR_HAL_STM32_RCC_CFGR_HPRE CYGHWR_HAL_STM32_RCC_CFGR_HPRE_2 +#elif CYGHWR_HAL_CORTEXM_STM32_CLOCK_HCLK_DIV == 4 +# define CYGHWR_HAL_STM32_RCC_CFGR_HPRE CYGHWR_HAL_STM32_RCC_CFGR_HPRE_4 +#elif CYGHWR_HAL_CORTEXM_STM32_CLOCK_HCLK_DIV == 8 +# define CYGHWR_HAL_STM32_RCC_CFGR_HPRE CYGHWR_HAL_STM32_RCC_CFGR_HPRE_8 +#elif CYGHWR_HAL_CORTEXM_STM32_CLOCK_HCLK_DIV == 16 +# define CYGHWR_HAL_STM32_RCC_CFGR_HPRE CYGHWR_HAL_STM32_RCC_CFGR_HPRE_16 +#elif CYGHWR_HAL_CORTEXM_STM32_CLOCK_HCLK_DIV == 64 +# define CYGHWR_HAL_STM32_RCC_CFGR_HPRE CYGHWR_HAL_STM32_RCC_CFGR_HPRE_64 +#elif CYGHWR_HAL_CORTEXM_STM32_CLOCK_HCLK_DIV == 128 +# define CYGHWR_HAL_STM32_RCC_CFGR_HPRE CYGHWR_HAL_STM32_RCC_CFGR_HPRE_128 +#elif CYGHWR_HAL_CORTEXM_STM32_CLOCK_HCLK_DIV == 256 +# define CYGHWR_HAL_STM32_RCC_CFGR_HPRE CYGHWR_HAL_STM32_RCC_CFGR_HPRE_256 +#elif CYGHWR_HAL_CORTEXM_STM32_CLOCK_HCLK_DIV == 512 +# define CYGHWR_HAL_STM32_RCC_CFGR_HPRE CYGHWR_HAL_STM32_RCC_CFGR_HPRE_512 +#endif + +#if CYGHWR_HAL_CORTEXM_STM32_CLOCK_PCLK1_DIV == 1 +# define CYGHWR_HAL_STM32_RCC_CFGR_PPRE1 CYGHWR_HAL_STM32_RCC_CFGR_PPRE1_1 +#elif CYGHWR_HAL_CORTEXM_STM32_CLOCK_PCLK1_DIV == 2 +# define CYGHWR_HAL_STM32_RCC_CFGR_PPRE1 CYGHWR_HAL_STM32_RCC_CFGR_PPRE1_2 +#elif CYGHWR_HAL_CORTEXM_STM32_CLOCK_PCLK1_DIV == 4 +# define CYGHWR_HAL_STM32_RCC_CFGR_PPRE1 CYGHWR_HAL_STM32_RCC_CFGR_PPRE1_4 +#elif CYGHWR_HAL_CORTEXM_STM32_CLOCK_PCLK1_DIV == 8 +# define CYGHWR_HAL_STM32_RCC_CFGR_PPRE1 CYGHWR_HAL_STM32_RCC_CFGR_PPRE1_8 +#elif CYGHWR_HAL_CORTEXM_STM32_CLOCK_PCLK1_DIV == 16 +# define CYGHWR_HAL_STM32_RCC_CFGR_PPRE1 CYGHWR_HAL_STM32_RCC_CFGR_PPRE1_16 +#endif + +#if CYGHWR_HAL_CORTEXM_STM32_CLOCK_PCLK2_DIV == 1 +# define CYGHWR_HAL_STM32_RCC_CFGR_PPRE2 CYGHWR_HAL_STM32_RCC_CFGR_PPRE2_1 +#elif CYGHWR_HAL_CORTEXM_STM32_CLOCK_PCLK2_DIV == 2 +# define CYGHWR_HAL_STM32_RCC_CFGR_PPRE2 CYGHWR_HAL_STM32_RCC_CFGR_PPRE2_2 +#elif CYGHWR_HAL_CORTEXM_STM32_CLOCK_PCLK2_DIV == 4 +# define CYGHWR_HAL_STM32_RCC_CFGR_PPRE2 CYGHWR_HAL_STM32_RCC_CFGR_PPRE2_4 +#elif CYGHWR_HAL_CORTEXM_STM32_CLOCK_PCLK2_DIV == 8 +# define CYGHWR_HAL_STM32_RCC_CFGR_PPRE2 CYGHWR_HAL_STM32_RCC_CFGR_PPRE2_8 +#elif CYGHWR_HAL_CORTEXM_STM32_CLOCK_PCLK2_DIV == 16 +# define CYGHWR_HAL_STM32_RCC_CFGR_PPRE2 CYGHWR_HAL_STM32_RCC_CFGR_PPRE2_16 +#endif + + +//========================================================================== +// Clock frequencies +// +// These are set to the frequencies of the various system clocks. + +cyg_uint32 hal_stm32_sysclk; +cyg_uint32 hal_stm32_hclk; +cyg_uint32 hal_stm32_pclk1; +cyg_uint32 hal_stm32_pclk2; +cyg_uint32 hal_cortexm_systick_clock; +#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE) +cyg_uint32 hal_stm32_qclk; +#endif + +void hal_start_clocks( void ); +cyg_uint32 hal_exti_isr( cyg_uint32 vector, CYG_ADDRWORD data ); + +//========================================================================== + +void hal_variant_init( void ) +{ + +#if 1 //!defined(CYG_HAL_STARTUP_RAM) + hal_start_clocks(); +#endif + + // Attach EXTI springboard to interrupt vectors + HAL_INTERRUPT_ATTACH( CYGNUM_HAL_INTERRUPT_EXTI9_5, hal_exti_isr, 0, 0 ); + HAL_INTERRUPT_ATTACH( CYGNUM_HAL_INTERRUPT_EXTI15_10, hal_exti_isr, 0, 0 ); + +#ifdef CYGSEM_HAL_VIRTUAL_VECTOR_SUPPORT + hal_if_init(); +#endif +} + +//========================================================================== +// Setup up system clocks +// +// Set up clocks from configuration. In the future this should be extended so +// that clock rates can be changed at runtime. + +void hal_start_clocks( void ) +{ + CYG_ADDRESS rcc = CYGHWR_HAL_STM32_RCC; + cyg_uint32 cr, cfgr; + + // Reset RCC + + cr = CYGHWR_HAL_STM32_RCC_CR_HSION; + HAL_WRITE_UINT32( rcc+CYGHWR_HAL_STM32_RCC_CR, cr ); + + // Start up HSE clock + + cr |= CYGHWR_HAL_STM32_RCC_CR_HSEON; + HAL_WRITE_UINT32( rcc+CYGHWR_HAL_STM32_RCC_CR, cr ); + + // Wait for HSE clock to startup + + do + { + HAL_READ_UINT32( rcc+CYGHWR_HAL_STM32_RCC_CR, cr ); + } while( !(cr & CYGHWR_HAL_STM32_RCC_CR_HSERDY) ); + + // Configure clocks + + // Temporarily divide by 4 until we've dealt with potential large + // multiplications overflow. + hal_stm32_sysclk = CYGARC_HAL_CORTEXM_STM32_INPUT_CLOCK >> 2; + + cfgr = 0; + +#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1) + +#if defined(CYGHWR_HAL_CORTEXM_STM32_CLOCK_PLL_SOURCE_HSE) + cfgr |= CYGHWR_HAL_STM32_RCC_CFGR_PLLSRC_HSE; +#endif + + // Just a little sanity check. +#if defined(CYGHWR_HAL_CORTEXM_STM32_CLOCK_PLL_SOURCE_HSI) && (CYGHWR_HAL_CORTEXM_STM32_CLOCK_PLL_PREDIV != 2) +# error PLL PREDIV must be 2 +#endif + + // Ordering could be important if divisions below cause truncation, so multiply first. + hal_stm32_sysclk *= CYGHWR_HAL_CORTEXM_STM32_CLOCK_PLL_MUL; + +#ifdef CYGHWR_HAL_CORTEXM_STM32_CONNECTIVITY + HAL_WRITE_UINT32( rcc + CYGHWR_HAL_STM32_RCC_CFGR2, + CYGHWR_HAL_STM32_RCC_CFGR2_PREDIV1(CYGHWR_HAL_CORTEXM_STM32_CLOCK_PLL_PREDIV-1) ); + hal_stm32_sysclk /= CYGHWR_HAL_CORTEXM_STM32_CLOCK_PLL_PREDIV; +#else + // Non-connectivity parts can only use PLLXTPRE + if ( CYGHWR_HAL_CORTEXM_STM32_CLOCK_PLL_PREDIV == 2 ) + { + cfgr |= CYGHWR_HAL_STM32_RCC_CFGR_PLLXTPRE; // irrelevant if HSI used, so just set anyway. + hal_stm32_sysclk /= 2; + } +#endif + hal_stm32_sysclk <<= 2; // return to correct range now we've dealt with risk of overflow. + + cfgr |= CYGHWR_HAL_STM32_RCC_CFGR_PLLMUL(CYGHWR_HAL_CORTEXM_STM32_CLOCK_PLL_MUL); + cfgr |= CYGHWR_HAL_STM32_RCC_CFGR_HPRE; + cfgr |= CYGHWR_HAL_STM32_RCC_CFGR_PPRE1; + cfgr |= CYGHWR_HAL_STM32_RCC_CFGR_PPRE2; + +#elif defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE) + +#if defined(CYGHWR_HAL_CORTEXM_STM32_CLOCK_PLL_SOURCE_HSE) + cfgr |= CYGHWR_HAL_STM32_RCC_PLLCFGR_PLLSRC_HSE; +#endif + + cfgr |= CYGHWR_HAL_STM32_RCC_PLLCFGR_PLLM(CYGHWR_HAL_CORTEXM_STM32_CLOCK_PLL_PREDIV); + cfgr |= CYGHWR_HAL_STM32_RCC_PLLCFGR_PLLN(CYGHWR_HAL_CORTEXM_STM32_CLOCK_PLL_MUL); + // Ordering could be important if divisions below cause truncation, so multiply first. + hal_stm32_sysclk *= CYGHWR_HAL_CORTEXM_STM32_CLOCK_PLL_MUL; + hal_stm32_sysclk /= CYGHWR_HAL_CORTEXM_STM32_CLOCK_PLL_PREDIV; + + hal_stm32_sysclk <<= 2; // return to correct range now we've dealt with risk of overflow. + + cfgr |= CYGHWR_HAL_STM32_RCC_PLLCFGR_PLLP(CYGHWR_HAL_CORTEXM_STM32_CLOCK_SYSCLK_DIV); + cfgr |= CYGHWR_HAL_STM32_RCC_PLLCFGR_PLLQ(CYGHWR_HAL_CORTEXM_STM32_CLOCK_PLLQ_DIV); + + // qclk divides down VCO output, so calc it first before updating sysclk for PLLP + hal_stm32_qclk = hal_stm32_sysclk / CYGHWR_HAL_CORTEXM_STM32_CLOCK_PLLQ_DIV; + + hal_stm32_sysclk /= CYGHWR_HAL_CORTEXM_STM32_CLOCK_SYSCLK_DIV; + + HAL_WRITE_UINT32( rcc + CYGHWR_HAL_STM32_RCC_PLLCFGR, cfgr ); + + cfgr = CYGHWR_HAL_STM32_RCC_CFGR_HPRE; + cfgr |= CYGHWR_HAL_STM32_RCC_CFGR_PPRE1; + cfgr |= CYGHWR_HAL_STM32_RCC_CFGR_PPRE2; + + // RTCPRE divides down HSE, which is the input clock. Must be 1MHz. + cfgr |= CYGHWR_HAL_STM32_RCC_CFGR_RTCPRE( CYGARC_HAL_CORTEXM_STM32_INPUT_CLOCK/1000000 ); + +#endif // elif defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE) + + HAL_WRITE_UINT32( rcc+CYGHWR_HAL_STM32_RCC_CFGR, cfgr ); + + // Enable the PLL and wait for it to lock + + cr |= CYGHWR_HAL_STM32_RCC_CR_PLLON; + + HAL_WRITE_UINT32( rcc+CYGHWR_HAL_STM32_RCC_CR, cr ); + do + { + HAL_READ_UINT32( rcc+CYGHWR_HAL_STM32_RCC_CR, cr ); + } while( !(cr & CYGHWR_HAL_STM32_RCC_CR_PLLRDY) ); + + // Now switch to use PLL as SYSCLK + // TODO: make this configurable between HSI, HSE and PLL + + cfgr |= CYGHWR_HAL_STM32_RCC_CFGR_SW_PLL; + + HAL_WRITE_UINT32( rcc+CYGHWR_HAL_STM32_RCC_CFGR, cfgr ); + do + { + HAL_READ_UINT32( rcc+CYGHWR_HAL_STM32_RCC_CFGR, cfgr ); + } while( (cfgr & CYGHWR_HAL_STM32_RCC_CFGR_SWS_XXX) != + CYGHWR_HAL_STM32_RCC_CFGR_SWS_PLL ); + + // Calculate clocks from configuration + + hal_stm32_hclk = hal_stm32_sysclk / CYGHWR_HAL_CORTEXM_STM32_CLOCK_HCLK_DIV; + hal_stm32_pclk1 = hal_stm32_hclk / CYGHWR_HAL_CORTEXM_STM32_CLOCK_PCLK1_DIV; + hal_stm32_pclk2 = hal_stm32_hclk / CYGHWR_HAL_CORTEXM_STM32_CLOCK_PCLK2_DIV; +#ifdef CYGHWR_HAL_CORTEXM_SYSTICK_CLK_SOURCE_INTERNAL + hal_cortexm_systick_clock = hal_stm32_hclk; +#else + hal_cortexm_systick_clock = hal_stm32_hclk / 8; +#endif +} + +//========================================================================== +// ISR springboard +// +// This is attached to the ISR table entries for EXTI9_5 and EXTI15_10 +// to decode the contents of the EXTI registers and deliver the +// interrupt to the correct ISR. + +cyg_uint32 hal_exti_isr( cyg_uint32 vector, CYG_ADDRWORD data ) +{ + CYG_ADDRESS base = CYGHWR_HAL_STM32_EXTI; + cyg_uint32 imr, pr; + + // Get EXTI pending and interrupt mask registers + HAL_READ_UINT32( base+CYGHWR_HAL_STM32_EXTI_IMR, imr ); + HAL_READ_UINT32( base+CYGHWR_HAL_STM32_EXTI_PR, pr ); + + // Mask PR by IMR and lose ls 5 bits + pr &= imr; + pr &= 0xFFFFFFE0; + + // Isolate LS pending bit and translate into interrupt vector + // number. + HAL_LSBIT_INDEX( vector, pr ); + vector += CYGNUM_HAL_INTERRUPT_EXTI5 - 5; + + // Deliver it + hal_deliver_interrupt( vector ); + + return 0; +} + +//========================================================================== +// GPIO support +// +// These functions provide configuration and IO for GPIO pins. + +__externC void hal_stm32_gpio_set( cyg_uint32 pin ) +{ + // FIXME: Power on GPIO ports selectively here, rather than + // platform having to power them all on for boot. +#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1) + cyg_uint32 port = CYGHWR_HAL_STM32_GPIO_PORT(pin); + int bit = CYGHWR_HAL_STM32_GPIO_BIT(pin); + cyg_uint32 cm = CYGHWR_HAL_STM32_GPIO_CFG(pin); + cyg_uint32 cr; + + if( pin == CYGHWR_HAL_STM32_GPIO_NONE ) + return; + + if( bit > 7 ) port += 4, bit -= 8; + HAL_READ_UINT32( port, cr ); + CYGHWR_HAL_STM32_GPIO_CNFMODE_SET(bit,cm,cr); + HAL_WRITE_UINT32( port, cr ); + + // If this is a pullup/down input, set the ODR bit to switch on + // the appropriate pullup/down resistor. + if( cm == (CYGHWR_HAL_STM32_GPIO_MODE_IN|CYGHWR_HAL_STM32_GPIO_CNF_PULL) ) + { + cyg_uint32 odr; + port = CYGHWR_HAL_STM32_GPIO_PORT( pin ); + bit = CYGHWR_HAL_STM32_GPIO_BIT(pin); + HAL_READ_UINT32( port+CYGHWR_HAL_STM32_GPIO_ODR, odr ); + if( pin & CYGHWR_HAL_STM32_GPIO_PULLUP ) + odr |= (1<<bit); + else + odr &= ~(1<<bit); + HAL_WRITE_UINT32( port+CYGHWR_HAL_STM32_GPIO_ODR, odr ); + } +#elif defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE) + CYG_ADDRESS port = CYGHWR_HAL_STM32_GPIO_PORT(pin); + int bit = CYGHWR_HAL_STM32_GPIO_BIT(pin); + cyg_uint32 mode = CYGHWR_HAL_STM32_GPIO_MODE(pin); + cyg_uint32 af = CYGHWR_HAL_STM32_GPIO_AF(pin); + cyg_uint32 od = CYGHWR_HAL_STM32_GPIO_OPENDRAIN(pin); + cyg_uint32 pupd = CYGHWR_HAL_STM32_GPIO_PULLUPDOWN(pin); + cyg_uint32 speed = CYGHWR_HAL_STM32_GPIO_SPEED(pin); + cyg_uint32 reg; + + if( pin == CYGHWR_HAL_STM32_GPIO_NONE ) + return; + + + HAL_READ_UINT32( port+CYGHWR_HAL_STM32_GPIO_OTYPER, reg ); + CYGHWR_HAL_STM32_GPIO_OTYPE_SET( bit, od, reg ); + HAL_WRITE_UINT32( port+CYGHWR_HAL_STM32_GPIO_OTYPER, reg ); + + HAL_READ_UINT32( port+CYGHWR_HAL_STM32_GPIO_OSPEEDR, reg ); + CYGHWR_HAL_STM32_GPIO_OSPEED_SET( bit, speed, reg ); + HAL_WRITE_UINT32( port+CYGHWR_HAL_STM32_GPIO_OSPEEDR, reg ); + + HAL_READ_UINT32( port+CYGHWR_HAL_STM32_GPIO_PUPDR, reg ); + CYGHWR_HAL_STM32_GPIO_PUPD_SET( bit, pupd, reg ); + HAL_WRITE_UINT32( port+CYGHWR_HAL_STM32_GPIO_PUPDR, reg ); + + if ( CYGHWR_HAL_STM32_GPIO_MODE_ALTFN == mode ) + { + CYGHWR_HAL_STM32_GPIO_AFR_SET( port, bit, af ); + } + + HAL_READ_UINT32( port+CYGHWR_HAL_STM32_GPIO_MODER, reg ); + CYGHWR_HAL_STM32_GPIO_MODE_SET( bit, mode, reg ); + HAL_WRITE_UINT32( port+CYGHWR_HAL_STM32_GPIO_MODER, reg ); +#endif // if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE) +} + +__externC void hal_stm32_gpio_out( cyg_uint32 pin, int val ) +{ +#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1) + cyg_uint32 port = CYGHWR_HAL_STM32_GPIO_PORT(pin); + int bit = CYGHWR_HAL_STM32_GPIO_BIT(pin); + + port += CYGHWR_HAL_STM32_GPIO_BSRR; + if( (val&1) == 0 ) port += 4; + HAL_WRITE_UINT32( port, 1<<bit ); +#elif defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE) + CYG_ADDRESS port = CYGHWR_HAL_STM32_GPIO_PORT(pin); + int bit = CYGHWR_HAL_STM32_GPIO_BIT(pin); + + CYGHWR_HAL_STM32_GPIO_BSRR_SET( port, bit, val ); +#endif // if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE) +} + +__externC void hal_stm32_gpio_in ( cyg_uint32 pin, int *val ) +{ +#if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_F1) + cyg_uint32 port = CYGHWR_HAL_STM32_GPIO_PORT(pin); + int bit = CYGHWR_HAL_STM32_GPIO_BIT(pin); + cyg_uint32 pd; + + HAL_READ_UINT32( port+CYGHWR_HAL_STM32_GPIO_IDR, pd ); + *val = (pd>>bit)&1; +#elif defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE) + CYG_ADDRESS port = CYGHWR_HAL_STM32_GPIO_PORT(pin); + int bit = CYGHWR_HAL_STM32_GPIO_BIT(pin); + + CYGHWR_HAL_STM32_GPIO_IDR_GET( port, bit, *val ); +#endif // if defined (CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE) +} + +//========================================================================== +// Clock support. +// +// These functions provide support for enabling and disabling clock +// control bits. + +__externC void hal_stm32_clock_enable( cyg_uint32 desc ) +{ + cyg_uint32 r; + cyg_uint32 reg = CYGHWR_HAL_STM32_RCC+CYGHWR_HAL_STM32_CLOCK_REG(desc); + HAL_READ_UINT32( reg, r ); + r |= BIT_(CYGHWR_HAL_STM32_CLOCK_PIN(desc)); + HAL_WRITE_UINT32( reg, r ); +} + +__externC void hal_stm32_clock_disable( cyg_uint32 desc ) +{ + cyg_uint32 r; + cyg_uint32 reg = CYGHWR_HAL_STM32_RCC+CYGHWR_HAL_STM32_CLOCK_REG(desc); + HAL_READ_UINT32( reg, r ); + r &= ~BIT_(CYGHWR_HAL_STM32_CLOCK_PIN(desc)); + HAL_WRITE_UINT32( reg, r ); +} + +//========================================================================== +// Backup domain + +void hal_stm32_bd_protect( int protect ) +{ + CYG_ADDRESS pwr = CYGHWR_HAL_STM32_PWR; + cyg_uint32 cr; + + HAL_READ_UINT32( pwr+CYGHWR_HAL_STM32_PWR_CR, cr ); + if( protect ) + cr &= ~CYGHWR_HAL_STM32_PWR_CR_DBP; + else + cr |= CYGHWR_HAL_STM32_PWR_CR_DBP; + HAL_WRITE_UINT32( pwr+CYGHWR_HAL_STM32_PWR_CR, cr ); +} + +//========================================================================== +// UART baud rate +// +// Set the baud rate divider of a UART based on the requested rate and +// the current APB clock settings. + +void hal_stm32_uart_setbaud( cyg_uint32 base, cyg_uint32 baud ) +{ + cyg_uint32 apbclk = hal_stm32_pclk1; + cyg_uint32 int_div, frac_div; + cyg_uint32 brr; + + if( base == CYGHWR_HAL_STM32_UART1 || +#ifdef CYGHWR_HAL_STM32_UART6 + base == CYGHWR_HAL_STM32_UART6 || +#endif + 0) + { + apbclk = hal_stm32_pclk2; + } + + int_div = (25 * apbclk ) / (4 * baud ); + brr = ( int_div / 100 ) << 4; + frac_div = int_div - (( brr >> 4 ) * 100 ); + + brr |= (((frac_div * 16 ) + 50 ) / 100) & 0xF; + + HAL_WRITE_UINT32( base+CYGHWR_HAL_STM32_UART_BRR, brr ); +} + +//========================================================================== +// Timer clock rate +// +// Returns the current timer clock rate of a timer. + +cyg_uint32 hal_stm32_timer_clock( CYG_ADDRESS base ) +{ + if( base == CYGHWR_HAL_STM32_TIM1 || + base == CYGHWR_HAL_STM32_TIM8 ) + { +#if CYGHWR_HAL_CORTEXM_STM32_CLOCK_PCLK2_DIV == 1 + return hal_stm32_pclk2; +#else + return hal_stm32_pclk2 << 1; +#endif + } else { +#if CYGHWR_HAL_CORTEXM_STM32_CLOCK_PCLK1_DIV == 1 + return hal_stm32_pclk1; +#else + return hal_stm32_pclk1 << 1; +#endif + } +} + +//========================================================================== +// Profiling timer +// +// Implementation of profiling support using general-purpose timer TIM2. + +#ifdef CYGFUN_HAL_CORTEXM_STM32_PROFILE_TIMER +// Use TIM2 for profiling +#define STM32_TIMER_PROFILE CYGHWR_HAL_STM32_TIM2 +#define STM32_CLOCK_PROFILE CYGHWR_HAL_STM32_TIM2_CLOCK +#define HAL_INTERRUPT_PROFILE CYGNUM_HAL_INTERRUPT_TIM2 + +// Profiling timer ISR +static cyg_uint32 profile_isr(CYG_ADDRWORD vector, CYG_ADDRWORD data) +{ + extern HAL_SavedRegisters *hal_saved_interrupt_state; + + HAL_WRITE_UINT32(STM32_TIMER_PROFILE+CYGHWR_HAL_STM32_TIM_SR, 0); // clear interrupt pending flag + HAL_INTERRUPT_ACKNOWLEDGE(HAL_INTERRUPT_PROFILE); + __profile_hit(hal_saved_interrupt_state->u.interrupt.pc); + return CYG_ISR_HANDLED; +} + +// Profiling timer setup +int hal_enable_profile_timer(int resolution) +{ + CYG_ASSERT(resolution < 0x10000, "Invalid profile timer resolution"); // 16 bits only + + // Enable clock + CYGHWR_HAL_STM32_CLOCK_ENABLE(STM32_CLOCK_PROFILE); + + // Attach ISR + HAL_INTERRUPT_ATTACH(HAL_INTERRUPT_PROFILE, &profile_isr, 0x1111, 0); + HAL_INTERRUPT_UNMASK(HAL_INTERRUPT_PROFILE); + + // Setup timer + HAL_WRITE_UINT32(STM32_TIMER_PROFILE+CYGHWR_HAL_STM32_TIM_PSC, + (hal_stm32_timer_clock(STM32_TIMER_PROFILE) / 1000000) - 1); // prescale to microseconds + HAL_WRITE_UINT32(STM32_TIMER_PROFILE+CYGHWR_HAL_STM32_TIM_CR2, 0); + HAL_WRITE_UINT32(STM32_TIMER_PROFILE+CYGHWR_HAL_STM32_TIM_DIER, CYGHWR_HAL_STM32_TIM_DIER_UIE); + HAL_WRITE_UINT32(STM32_TIMER_PROFILE+CYGHWR_HAL_STM32_TIM_ARR, resolution); + HAL_WRITE_UINT32(STM32_TIMER_PROFILE+CYGHWR_HAL_STM32_TIM_CR1, CYGHWR_HAL_STM32_TIM_CR1_CEN); + + return resolution; +} + +#endif // CYGFUN_HAL_CORTEXM_STM32_PROFILE_TIMER + +//========================================================================== +// EOF stm32_misc.c diff --git a/ecos/packages/hal/cortexm/stm32/var/current/tests/timers.c b/ecos/packages/hal/cortexm/stm32/var/current/tests/timers.c new file mode 100644 index 0000000..7d5b823 --- /dev/null +++ b/ecos/packages/hal/cortexm/stm32/var/current/tests/timers.c @@ -0,0 +1,364 @@ +/*============================================================================= +// +// timers.c +// +// Test for STM32 Timers +// +//============================================================================= +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2008 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): nickg +// Date: 2008-09-11 +// +//####DESCRIPTIONEND#### +// +//===========================================================================*/ + +#include <pkgconf/system.h> +#include <pkgconf/hal.h> + +#if defined(CYGPKG_KERNEL) +#include <pkgconf/kernel.h> +#endif + +#include <cyg/infra/testcase.h> + +//============================================================================= +// Check all required packages and components are present + +#if !defined(CYGPKG_KERNEL) || !defined(CYGPKG_KERNEL_API) + +#define NA_MSG "Configuration insufficient" + +#endif + +//============================================================================= +// If everything is present, compile the full test. + +#ifndef NA_MSG + +#include <cyg/hal/hal_arch.h> +#include <cyg/hal/hal_io.h> +#include <cyg/hal/hal_if.h> + +#include <cyg/kernel/kapi.h> +#include <cyg/infra/diag.h> +#include <string.h> + +//============================================================================= + +#define LOOPS 24 // == 2 minutes + +#define STACK_SIZE 8000 + +static int test_stack[(STACK_SIZE/sizeof(int))]; +static cyg_thread test_thread; +static cyg_handle_t main_thread; + +//============================================================================= + +struct timer +{ + cyg_uint32 timer; + cyg_uint32 base; + cyg_uint32 vector; + cyg_uint32 priority; + cyg_uint32 interval; + + cyg_uint32 ticks; + + cyg_uint32 preempt[10]; + + cyg_uint32 preempt_dsr[10]; + cyg_uint32 dsr_count[10]; + + cyg_interrupt interrupt_object; + cyg_handle_t interrupt_handle; +}; + +struct timer timers[] = +{ +#if 0 + { 1, CYGHWR_HAL_STM32_TIM1, CYGNUM_HAL_INTERRUPT_TIM1_UP, 0x20, 1000 }, +#elif 1 + { 1, CYGHWR_HAL_STM32_TIM1, CYGNUM_HAL_INTERRUPT_TIM1_UP, 0x20, 127 }, + { 2, CYGHWR_HAL_STM32_TIM2, CYGNUM_HAL_INTERRUPT_TIM2, 0x30, 355 }, + { 3, CYGHWR_HAL_STM32_TIM3, CYGNUM_HAL_INTERRUPT_TIM3, 0x40, 731 }, + { 4, CYGHWR_HAL_STM32_TIM4, CYGNUM_HAL_INTERRUPT_TIM4, 0x50, 999 }, + { 5, CYGHWR_HAL_STM32_TIM5, CYGNUM_HAL_INTERRUPT_TIM5, 0x60, 1453 }, + { 6, CYGHWR_HAL_STM32_TIM6, CYGNUM_HAL_INTERRUPT_TIM6, 0x70, 1931 }, + { 7, CYGHWR_HAL_STM32_TIM7, CYGNUM_HAL_INTERRUPT_TIM7, 0x80, 2011 }, +#ifdef CYGNUM_HAL_INTERRUPT_TIM8_UP + { 8, CYGHWR_HAL_STM32_TIM8, CYGNUM_HAL_INTERRUPT_TIM8_UP, 0x90, 2345 }, +#elif defined(CYGNUM_HAL_INTERRUPT_TIM8_UP_TIM13) + { 8, CYGHWR_HAL_STM32_TIM8, CYGNUM_HAL_INTERRUPT_TIM8_UP_TIM13, 0x90, 2345 }, +#endif +#endif + { 0, 0, 0, 0 } +}; + +//============================================================================= + +volatile cyg_uint32 ticks = 0; +volatile cyg_uint32 nesting = 0; +volatile cyg_uint32 max_nesting = 0; +volatile cyg_uint32 max_nesting_seen = 0; +volatile cyg_uint32 current = 0; +volatile cyg_uint32 in_dsr = 0; + +//============================================================================= + +__externC cyg_uint32 hal_stm32_pclk1; +__externC cyg_uint32 hal_stm32_pclk2; + +void init_timer( cyg_uint32 base, cyg_uint32 interval ) +{ + cyg_uint32 period = hal_stm32_pclk1; + + if( base == CYGHWR_HAL_STM32_TIM1 || base == CYGHWR_HAL_STM32_TIM8 ) + { + period = hal_stm32_pclk2; + if( CYGHWR_HAL_CORTEXM_STM32_CLOCK_PCLK2_DIV != 1 ) + period *= 2; + } + else + { + if( CYGHWR_HAL_CORTEXM_STM32_CLOCK_PCLK1_DIV != 1 ) + period *= 2; + } + + period = period / 1000000; + + HAL_WRITE_UINT32(base+CYGHWR_HAL_STM32_TIM_PSC, period-1 ); + + HAL_WRITE_UINT32(base+CYGHWR_HAL_STM32_TIM_CR2, 0 ); + + HAL_WRITE_UINT32(base+CYGHWR_HAL_STM32_TIM_DIER, CYGHWR_HAL_STM32_TIM_DIER_UIE ); + + HAL_WRITE_UINT32(base+CYGHWR_HAL_STM32_TIM_ARR, interval ); + + HAL_WRITE_UINT32(base+CYGHWR_HAL_STM32_TIM_CR1, CYGHWR_HAL_STM32_TIM_CR1_CEN); +} + +//============================================================================= + +cyg_uint32 timer_isr( cyg_uint32 vector, CYG_ADDRWORD data ) +{ + struct timer *t = (struct timer *)data; + cyg_uint32 preempt = current; + CYG_ADDRWORD base = t->base; + cyg_uint32 cnt; + + current = t->timer; + t->ticks++; + ticks++; + t->preempt[preempt]++; + nesting++; + + // Count only first ISR to preempt a DSR + if( preempt == 0 ) + t->preempt_dsr[in_dsr]++; + + HAL_WRITE_UINT32(t->base+CYGHWR_HAL_STM32_TIM_SR, 0 ); + + if( nesting > max_nesting ) + max_nesting = nesting; + + // Loiter here for a proportion of the timer interval to give + // other timers the chance to preempt us. + do + { + HAL_READ_UINT32( base+CYGHWR_HAL_STM32_TIM_CNT, cnt ); + } while( cnt < t->interval/10 ); + + nesting--; + current = preempt; + + if( (t->ticks % 10) == 0 ) + return 3; + else + return 1; +} + +//============================================================================= + +void timer_dsr( cyg_uint32 vector, cyg_uint32 count, CYG_ADDRWORD data ) +{ + struct timer *t = (struct timer *)data; + int i; + + in_dsr = t->timer; + + if( count >= 8 ) + count = 8; + + t->dsr_count[count]++; + + // Loiter for a while + for( i = 0; i < t->interval/10; i++) + continue; + + in_dsr = 0; +} + +//============================================================================= + +void +timers_test(cyg_addrword_t data) +{ + int loops = LOOPS; + int i; + CYG_INTERRUPT_STATE istate; + + CYG_TEST_INIT(); + + CYG_TEST_INFO("Start Timers test"); + + for( i = 0; timers[i].timer != 0; i++ ) + { + struct timer *t = &timers[i]; + + init_timer( t->base, t->interval ); + + cyg_interrupt_create( t->vector, + t->priority, + (cyg_addrword_t)t, + timer_isr, + timer_dsr, + &t->interrupt_handle, + &t->interrupt_object + ); + + cyg_interrupt_attach( t->interrupt_handle ); + cyg_interrupt_unmask( t->vector ); + + } + + while( loops-- ) + { + int j; + + // 5 second delay + cyg_thread_delay( 5*100 ); + + // Disable interrupts while we print details, otherwise it + // comes out very slowly. + HAL_DISABLE_INTERRUPTS( istate ); + + if( max_nesting > max_nesting_seen ) + max_nesting_seen = max_nesting; + + diag_printf("\nISRs max_nesting %d max_nesting_seen %d\n", max_nesting, max_nesting_seen ); + max_nesting = 0; + + diag_printf(" T Ticks "); + + for( j = 0; j < 9; j++ ) + diag_printf("%9d ", j ); + diag_printf("\n"); + + for( i = 0; timers[i].timer != 0; i++ ) + { + struct timer *t = &timers[i]; + + diag_printf("%2d: %9d ", t->timer, t->ticks ); + + for( j = 0; j < 9; j++ ) + diag_printf("%9d ", t->preempt[j] ); + diag_printf("\n"); + + } + + diag_printf("DSRs\n"); + + diag_printf(" T: "); + + for( j = 0; j < 9; j++ ) + diag_printf("%9d ", j ); + diag_printf("\n"); + + for( i = 0; timers[i].timer != 0; i++ ) + { + struct timer *t = &timers[i]; + + diag_printf("%2d: preempt: ", t->timer); + + for( j = 0; j < 9; j++ ) + diag_printf("%9d ", t->preempt_dsr[j] ); + diag_printf("\n"); + + diag_printf(" count: "); + + for( j = 0; j < 9; j++ ) + diag_printf("%9d ", t->dsr_count[j] ); + diag_printf("\n"); + } + + HAL_RESTORE_INTERRUPTS( istate ); + } + + CYG_TEST_PASS_FINISH("Timers test"); +} + +//============================================================================= + +void cyg_user_start(void) +{ + cyg_thread_create(0, // Priority + timers_test, + 0, + "timers test", // Name + test_stack, // Stack + STACK_SIZE, // Size + &main_thread, // Handle + &test_thread // Thread data structure + ); + cyg_thread_resume( main_thread); +} + +//============================================================================= +// Print a message if we cannot run + +#else // NA_MSG + +void cyg_user_start(void) +{ + CYG_TEST_NA(NA_MSG); +} + +#endif // NA_MSG + +//============================================================================= +/* EOF timers.c */ |