diff options
| author | Michael Gielda <mgielda@antmicro.com> | 2014-04-03 14:53:04 +0200 |
|---|---|---|
| committer | Michael Gielda <mgielda@antmicro.com> | 2014-04-03 14:53:04 +0200 |
| commit | ae1e4e08a1005a0c487f03ba189d7536e7fdcba6 (patch) | |
| tree | f1c296f8a966a9a39876b0e98e16d9c5da1776dd /ecos/packages/hal/cortexm/vybrid/var | |
| parent | f157da5337118d3c5cd464266796de4262ac9dbd (diff) | |
Added the OS files
Diffstat (limited to 'ecos/packages/hal/cortexm/vybrid/var')
20 files changed, 3611 insertions, 0 deletions
diff --git a/ecos/packages/hal/cortexm/vybrid/var/current/cdl/hal_cortexm_vybrid.cdl b/ecos/packages/hal/cortexm/vybrid/var/current/cdl/hal_cortexm_vybrid.cdl new file mode 100644 index 0000000..dc0b08a --- /dev/null +++ b/ecos/packages/hal/cortexm/vybrid/var/current/cdl/hal_cortexm_vybrid.cdl @@ -0,0 +1,339 @@ +##========================================================================== +## +## hal_cortexm_vybrid.cdl +## +## Cortex-M Freescale Vybrid variant HAL configuration data +## +##========================================================================== +## ####ECOSGPLCOPYRIGHTBEGIN#### +## ------------------------------------------- +## This file is part of eCos, the Embedded Configurable Operating System. +## Copyright (C) 2010, 2011, 2012, 2013 Free Software Foundation, Inc. +## +## eCos is free software; you can redistribute it and/or modify it under +## the terms of the GNU General Public License as published by the Free +## Software Foundation; either version 2 or (at your option) any later +## version. +## +## eCos is distributed in the hope that it will be useful, but WITHOUT +## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +## for more details. +## +## You should have received a copy of the GNU General Public License +## along with eCos; if not, write to the Free Software Foundation, Inc., +## 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +## +## As a special exception, if other files instantiate templates or use +## macros or inline functions from this file, or you compile this file +## and link it with other works to produce a work based on this file, +## this file does not by itself cause the resulting work to be covered by +## the GNU General Public License. However the source code for this file +## must still be made available in accordance with section (3) of the GNU +## General Public License v2. +## +## This exception does not invalidate any other reasons why a work based +## on this file might be covered by the GNU General Public License. +## ------------------------------------------- +## ####ECOSGPLCOPYRIGHTEND#### +##========================================================================== +#######DESCRIPTIONBEGIN#### +## +## Author(s): Antmicro Ltd <contact@antmicro.com> +## Date: 2014-03-28 +## Based on respective definitions from /hal/cortexm/kinetis/var/current/cdl/hal_cortexm_kinetis.cdl +## +## +######DESCRIPTIONEND#### +## +##========================================================================== +######MODIFICATION##### +## +## CYG_HAL_STARTUP_VAR legal_values added "RAM" +## CYGHWR_MEMORY_LAYOUT addded new compute value (RAM) +##========================================================================== + +cdl_package CYGPKG_HAL_CORTEXM_VYBRID { + display "Freescale Vybrid Cortex-M4 Variant" + parent CYGPKG_HAL_CORTEXM + doc ref/hal-cortexm-vybrid-var.html + hardware + include_dir cyg/hal + define_header hal_cortexm_vybrid.h + description " + This package provides generic support for the Freescale Cortex-M4 + based Vybrid microcontroller family. + It is also necessary to select a variant and platform HAL package." + + compile hal_diag.c vybrid_misc.c vybrid_clocking.c + + #implements CYGINT_HAL_DEBUG_GDB_STUBS + #implements CYGINT_HAL_DEBUG_GDB_STUBS_BREAK + implements CYGINT_HAL_VIRTUAL_VECTOR_SUPPORT + implements CYGINT_HAL_VIRTUAL_VECTOR_COMM_BAUD_SUPPORT + + + + requires { CYGHWR_HAL_CORTEXM == "M4" } + + define_proc { + puts $::cdl_system_header "#define CYGBLD_HAL_TARGET_H <pkgconf/hal_cortexm.h>" + puts $::cdl_system_header "#define CYGBLD_HAL_VARIANT_H <pkgconf/hal_cortexm_vybrid.h>" + } + + cdl_option CYGNUM_HAL_CORTEXM_PRIORITY_LEVEL_BITS { + display "CPU exception priority level bits" + flavor data + default_value 4 + description " + This option defines the number of bits used to encode the + exception priority levels that this variant of the Cortex-M + CPU implements." + } + + + cdl_option CYGNUM_HAL_KERNEL_COUNTERS_CLOCK_ISR_DEFAULT_PRIORITY { + display "Clock interrupt ISR priority" + flavor data + calculated CYGNUM_HAL_KERNEL_COUNTERS_CLOCK_ISR_DEFAULT_PRIORITY_SP + description "Set clock ISR priority. Default setting is lowest priority." + } + + + cdl_component CYGNUM_HAL_RTC_CONSTANTS { + display "Real-time clock constants" + flavor none + no_define + cdl_option CYGNUM_HAL_RTC_NUMERATOR { + display "Real-time clock numerator" + flavor data + default_value 1000000000 + } + cdl_option CYGNUM_HAL_RTC_DENOMINATOR { + display "Real-time clock denominator" + flavor data + default_value 1000 + } + cdl_option CYGNUM_HAL_RTC_PERIOD { + display "Real-time clock period" + flavor data + default_value 1000000 / CYGNUM_HAL_RTC_DENOMINATOR + description " + The period defined here is something of a fake, it is + expressed in terms of a notional 1MHz clock. The value + actually installed in the hardware is calculated from + the current settings of the clock generation hardware." + } + } + + cdl_option CYG_HAL_STARTUP_VAR { + display "By variant" + flavor data + parent CYG_HAL_STARTUP_ENV + default_value { "OCRAM" } + legal_values { "TCML" "OCRAM" } + active_if ((!CYG_HAL_STARTUP_PLF) || (CYG_HAL_STARTUP_PLF=="ByVariant")) + description " + 'OCRAM' startup builds a stand-alone application hich will be placed into OnChipRAM. + This type of memory is intended to be written via bootloaders such like uBoot or + from Linux system running on the Cortex A5 core of Vybrid processor. + Note: Variant Startup Type can be overriden/overloaded by + Platform Startup Type." + } + + cdl_component CYG_HAL_STARTUP { + display "Startup type calculator" + flavor data + parent CYG_HAL_STARTUP_ENV + calculated { (CYG_HAL_STARTUP_PLF && (CYG_HAL_STARTUP_PLF!="ByVariant")) ? + CYG_HAL_STARTUP_PLF : CYG_HAL_STARTUP_VAR} + define -file system.h CYG_HAL_STARTUP + description " + Startup type defines what type of application shall be built. + Startup type can be defined by variant (CYG_HAL_STARTUP_VAR) + or platform (CYG_HAL_STARTUP_PLF). If CYG_HAL_STARTUP_PLF + is defined and not equal to 'ByVariant' then it shall + override CYG_HAL_STARTUP_VAR." + } + + cdl_component CYGHWR_MEMORY_LAYOUT { + display "Memory layout" + flavor data + no_define + parent CYG_HAL_STARTUP_ENV + calculated { + (CYGHWR_MEMORY_LAYOUT_PLF) ? CYGHWR_MEMORY_LAYOUT_PLF : + (CYG_HAL_STARTUP == "TCML") ? "vybrid_tcml" : + (CYG_HAL_STARTUP == "OCRAM") ? "vybrid_ocram" : + "undefined" } + description " + Combination of 'Startup type' and 'Vybrid part' + produces the memory layout." + + cdl_option CYGHWR_MEMORY_LAYOUT_LDI { + display "Memory layout linker script fragment" + flavor data + no_define + define -file system.h CYGHWR_MEMORY_LAYOUT_LDI + calculated { "<pkgconf/mlt_" . CYGHWR_MEMORY_LAYOUT . ".ldi>" } + } + + cdl_option CYGHWR_MEMORY_LAYOUT_H { + display "Memory layout header file" + flavor data + no_define + define -file system.h CYGHWR_MEMORY_LAYOUT_H + calculated { "<pkgconf/mlt_" . CYGHWR_MEMORY_LAYOUT . ".h>" } + } + } + + + cdl_component CYGHWR_HAL_VYBRID_MEMORY_RESOURCES { + display "On chip memory resources" + flavor none + no_define + description " + View and manage on-chip memory resources. + Output is used for naming of 'mlt' files." + + + cdl_option CYGHWR_HAL_CORTEXM_VYBRID_OCRAM_KIB { + display "Vybrid on chip SysRAM0 size \[KiB\]" + flavor data + calculated { 256 } + } + + cdl_option CYGHWR_HAL_CORTEXM_VYBRID_OCRAM { + display "Vybrid on chip SysRAM0 size" + flavor data + calculated { CYGHWR_HAL_CORTEXM_VYBRID_OCRAM_KIB * 0x400} + } + + cdl_option CYGHWR_HAL_CORTEXM_VYBRID_TCMU_KIB { + display "Vybrid on chip TCMU (data) size \[KiB\]" + flavor data + calculated { 32 } + } + + cdl_option CYGHWR_HAL_CORTEXM_VYBRID_TCMU { + display "Vybrid on chip TCMU (data) size" + flavor data + calculated { CYGHWR_HAL_CORTEXM_VYBRID_TCMU_KIB * 0x400 } + } + + cdl_option CYGHWR_HAL_CORTEXM_VYBRID_TCML_KIB { + display "Vybrid on chip TCML (data) size \[KiB\]" + flavor data + calculated { 32 } + } + + cdl_option CYGHWR_HAL_CORTEXM_VYBRID_TCML { + display "Vybrid on chip TCML (data) size" + flavor data + calculated { CYGHWR_HAL_CORTEXM_VYBRID_TCML_KIB * 0x400 } + } + + + } + + cdl_interface CYGINT_HAL_CACHE { + display "Platform has cache" + flavor bool + } + + cdl_interface CYGINT_HAL_HAS_NONCACHED { + display "Platform has non-cached regions" + flavor bool + } + + cdl_component CYGPKG_HAL_VYBRID_CACHE { + display "Cache memory" + flavor bool + + default_value false + active_if (CYGINT_HAL_CACHE) + } + + cdl_interface CYGINT_HAL_CORTEXM_VYBRID_DDRAM { + display "Platform uses DDRAM" + flavor bool + description " + This interface will be implemented if the specific + controller being used provides DDRAM and if DDRAM is + used on target hardware" + } + + + for { set ::channel 0 } { $::channel < 6 } { incr ::channel } { + + cdl_interface CYGINT_HAL_FREESCALE_UART[set ::channel] { + display "Platform provides UART [set ::channel] HAL" + flavor bool + description " + This interface will be implemented if the specific + controller being used has on-chip UART [set ::channel], + and if that UART is accessible on the target hardware." + } + + cdl_interface CYGINT_HAL_FREESCALE_UART[set ::channel]_RTSCTS { + display "Platform provides HAL for UART[set ::channel] hardware flow control." + flavor bool + description " + This interface will be implemented if the specific + on-chip UART [set ::channel] has RTS/CTS flow control + that is accessible on the target hardware." + } + } + + cdl_interface CYGINT_HAL_DMA { + display "Platform uses DMA" + flavor bool + description " + This interface will be implemented if the specific + controller being used provides DMA and if DMA is + used on target hardware" + } + + cdl_component CYGHWR_HAL_DEVS_IRQ_PRIO_SCHEME_VAR { + display "Variant IRQ priority defaults" + no_define + flavor none + parent CYGHWR_HAL_DEVS_IRQ_PRIO_SCHEME + description " + Interrupt priorities defined by Vybrid variant" + script vybrid_irq_scheme.cdl + } + + cdl_component CYGPKG_HAL_CORTEXM_VYBRID_OPTIONS { + display "Build options" + flavor none + no_define + description " + Package specific build options including control over + compiler flags used only in building this package." + + cdl_option CYGPKG_HAL_CORTEXM_VYBRID_CFLAGS_ADD { + display "Additional compiler flags" + flavor data + no_define + default_value { "" } + description " + This option modifies the set of compiler flags for + building the Vybrid variant HAL package. These flags + are used in addition to the set of global flags." + } + + cdl_option CYGPKG_HAL_CORTEXM_VYBRID_CFLAGS_REMOVE { + display "Suppressed compiler flags" + flavor data + no_define + default_value { "" } + description " + This option modifies the set of compiler flags for + building the Vybrid variant HAL package. These flags + are removed from the set of global flags if present." + } + } +} + +# EOF hal_cortexm_vybrid.cdl diff --git a/ecos/packages/hal/cortexm/vybrid/var/current/cdl/vybrid_irq_scheme.cdl b/ecos/packages/hal/cortexm/vybrid/var/current/cdl/vybrid_irq_scheme.cdl new file mode 100644 index 0000000..2e63a77 --- /dev/null +++ b/ecos/packages/hal/cortexm/vybrid/var/current/cdl/vybrid_irq_scheme.cdl @@ -0,0 +1,138 @@ +##========================================================================== +## +## vybrid_irq_scheme.cdl +## +## Cortex-M Freescale Vybrid IRQ configuration data +## +##========================================================================== +## ####ECOSGPLCOPYRIGHTBEGIN#### +## ------------------------------------------- +## This file is part of eCos, the Embedded Configurable Operating System. +## Copyright (C) 2010, 2011 Free Software Foundation, Inc. +## +## eCos is free software; you can redistribute it and/or modify it under +## the terms of the GNU General Public License as published by the Free +## Software Foundation; either version 2 or (at your option) any later +## version. +## +## eCos is distributed in the hope that it will be useful, but WITHOUT +## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +## for more details. +## +## You should have received a copy of the GNU General Public License +## along with eCos; if not, write to the Free Software Foundation, Inc., +## 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +## +## As a special exception, if other files instantiate templates or use +## macros or inline functions from this file, or you compile this file +## and link it with other works to produce a work based on this file, +## this file does not by itself cause the resulting work to be covered by +## the GNU General Public License. However the source code for this file +## must still be made available in accordance with section (3) of the GNU +## General Public License v2. +## +## This exception does not invalidate any other reasons why a work based +## on this file might be covered by the GNU General Public License. +## ------------------------------------------- +## ####ECOSGPLCOPYRIGHTEND#### +##========================================================================== +#######DESCRIPTIONBEGIN#### +## +## Author(s): Antmicro Ltd <contact@antmicro.com> +## Date: 2014-03-28 +## Based on respective definitions from /hal/cortexm/kinetis/var/current/cdl/kinetis_irq_scheme.cdl +## +######DESCRIPTIONEND#### +## +##========================================================================== + +# cdl_component CYGHWR_HAL_DEVS_IRQ_PRIO_SCHEME_VAR { +# display "Variant IRQ priority defaults" +# no_define +# flavor none +# parent CYGHWR_HAL_DEVS_IRQ_PRIO_SCHEME +# description " +# Interrupt priorities defined by Vybrid variant" + + cdl_option CYGNUM_HAL_KERNEL_COUNTERS_CLOCK_ISR_DEFAULT_PRIORITY_SP { + display "Clock IRQ priority" + flavor data + no_define + default_value 0xE0 + description "Set clock ISR priority. Default setting is lowest priority." + legal_values { 0 0x10 0x20 0x30 0x40 0x50 0x60 0x70 0x80 + 0x90 0xA0 0xB0 0xC0 0xD0 0xE0 } + + } + + cdl_component CYGHWR_HAL_DEVS_IRQ_PRIO_SCHEME_UART { + display "UART IRQ priorities" + flavor none + no_define + + cdl_option CYGNUM_IO_SERIAL_FREESCALE_UART0_INT_PRIORITY_SP { + display "UART0 interrupt priority" + flavor data + no_define + active_if CYGPKG_IO_SERIAL_FREESCALE_UART0 + legal_values { 0 0x10 0x20 0x30 0x40 0x50 0x60 0x70 0x80 + 0x90 0xA0 0xB0 0xC0 0xD0 0xE0 } + default_value 0x80 + } + + cdl_option CYGNUM_IO_SERIAL_FREESCALE_UART1_INT_PRIORITY_SP { + display "UART1 interrupt priority" + flavor data + no_define + active_if CYGPKG_IO_SERIAL_FREESCALE_UART1 + legal_values { 0 0x10 0x20 0x30 0x40 0x50 0x60 0x70 0x80 + 0x90 0xA0 0xB0 0xC0 0xD0 0xE0 } + default_value 0x80 + } + + cdl_option CYGNUM_IO_SERIAL_FREESCALE_UART2_INT_PRIORITY_SP { + display "UART2 interrupt priority" + flavor data + no_define + active_if CYGPKG_IO_SERIAL_FREESCALE_UART2 + legal_values { 0 0x10 0x20 0x30 0x40 0x50 0x60 0x70 0x80 + 0x90 0xA0 0xB0 0xC0 0xD0 0xE0 } + default_value 0x80 + } + + cdl_option CYGNUM_IO_SERIAL_FREESCALE_UART3_INT_PRIORITY_SP { + display "UART3 interrupt priority" + flavor data + no_define + active_if CYGPKG_IO_SERIAL_FREESCALE_UART3 + legal_values { 0 0x10 0x20 0x30 0x40 0x50 0x60 0x70 0x80 + 0x90 0xA0 0xB0 0xC0 0xD0 0xE0 } + default_value 0x80 + } + + cdl_option CYGNUM_IO_SERIAL_FREESCALE_UART4_INT_PRIORITY_SP { + display "UART4 interrupt priority" + flavor data + no_define + active_if CYGPKG_IO_SERIAL_FREESCALE_UART4 + legal_values { 0 0x10 0x20 0x30 0x40 0x50 0x60 0x70 0x80 + 0x90 0xA0 0xB0 0xC0 0xD0 0xE0 } + default_value 0x80 + } + + cdl_option CYGNUM_IO_SERIAL_FREESCALE_UART5_INT_PRIORITY_SP { + display "UART5 interrupt priority" + flavor data + no_define + active_if CYGPKG_IO_SERIAL_FREESCALE_UART5 + legal_values { 0 0x10 0x20 0x30 0x40 0x50 0x60 0x70 0x80 + 0x90 0xA0 0xB0 0xC0 0xD0 0xE0 } + default_value 0x80 + } + } + +# } + + +# EOF vybrid_irq_scheme.cdl diff --git a/ecos/packages/hal/cortexm/vybrid/var/current/include/hal_cache.h b/ecos/packages/hal/cortexm/vybrid/var/current/include/hal_cache.h new file mode 100644 index 0000000..4b007f2 --- /dev/null +++ b/ecos/packages/hal/cortexm/vybrid/var/current/include/hal_cache.h @@ -0,0 +1,211 @@ +#ifndef CYGONCE_HAL_CACHE_H +#define CYGONCE_HAL_CACHE_H +//============================================================================= +// +// hal_cache.h +// +// HAL cache control API +// +//============================================================================= +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2012 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): Antmicro Ltd <contact@antmicro.com> +// Based on: {...}/hal/packages/cortexm/kinetis/var/current/include/hal_cache.h +// Date: 2014-03-28 +// Purpose: Cache control API +// Description: The macros defined here provide the HAL APIs for handling +// cache control operations. +// +// Usage: +// #include <cyg/hal/hal_cache.h> +// ... +// +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +#include <cyg/infra/cyg_type.h> + +//----------------------------------------------------------------------------- +// Cache dimensions +#ifdef CYGINT_HAL_CACHE + +// Data cache +#define HAL_DCACHE_SIZE (1024 * 16) // Size of data cache in bytes +#define HAL_DCACHE_LINE_SIZE 32 // Size of a data cache line +#define HAL_DCACHE_WAYS 2 // Associativity of the cache + +// Instruction cache +#define HAL_ICACHE_SIZE (1024 * 16) // Size of cache in bytes +#define HAL_ICACHE_LINE_SIZE 32 // Size of a cache line +#define HAL_ICACHE_WAYS 2 // Associativity of the cache + +#define HAL_DCACHE_SETS (HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS)) +#define HAL_ICACHE_SETS (HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS)) + +#include <cyg/hal/var_io.h> +#include <cyg/hal/var_io_lmem.h> + +//----------------------------------------------------------------------------- +// Global control of data cache + +// Enable the data cache +#define HAL_DCACHE_ENABLE() HAL_CORTEXM_VYBRID_CACHE_PS_ENABLE() + +// Disable the data cache +#define HAL_DCACHE_DISABLE() HAL_CORTEXM_VYBRID_CACHE_PS_DISABLE() + +// Invalidate the entire cache +#define HAL_DCACHE_INVALIDATE_ALL() HAL_CORTEXM_VYBRID_CACHE_PS_INVALL() + +// Synchronize the contents of the cache with memory. +#define HAL_DCACHE_SYNC() HAL_CORTEXM_VYBRID_CACHE_PS_SYNC() + +// Purge contents of data cache +#define HAL_DCACHE_PURGE_ALL() HAL_CORTEXM_VYBRID_CACHE_PS_CLEAR() + +// Query the state of the data cache (does not affect the caching) +#define HAL_DCACHE_IS_ENABLED(_state_) \ + CYG_MACRO_START \ + (_state_) = HAL_CORTEXM_VYBRID_CACHE_PS_IS_ENABLED(); \ + CYG_MACRO_END + +// Invalidate cache lines in the given range without writing to memory. +#define HAL_DCACHE_INVALIDATE( _base_ , _size_ ) \ + HAL_CORTEXM_VYBRID_CACHE_PS_INVALIDATE(_base_, _size_) + +// Write dirty cache lines to memory and invalidate the cache entries +#define HAL_DCACHE_FLUSH( _base_ , _size_ ) \ + HAL_CORTEXM_VYBRID_CACHE_PS_CLR(_base_, _size_) + +//----------------------------------------------------------------------------- +// Global control of Instruction cache + +// Enable the instruction cache +#define HAL_ICACHE_ENABLE() HAL_CORTEXM_VYBRID_CACHE_PC_ENABLE() + +// Disable the instruction cache +#define HAL_ICACHE_DISABLE() HAL_CORTEXM_VYBRID_CACHE_PC_DISABLE() + +// Invalidate the entire cache +#define HAL_ICACHE_INVALIDATE_ALL() HAL_CORTEXM_VYBRID_CACHE_PC_INVALL() + +// Synchronize the contents of the cache with memory. +#define HAL_ICACHE_SYNC() HAL_CORTEXM_VYBRID_CACHE_PC_SYNC() + +// Purge contents of data cache +#define HAL_ICACHE_PURGE_ALL() HAL_CORTEXM_VYBRID_CACHE_PC_CLEAR() + +// Query the state of the instruction cache (does not affect the caching) +#define HAL_ICACHE_IS_ENABLED(_state_) \ + CYG_MACRO_START \ + (_state_) = HAL_CORTEXM_VYBRID_CACHE_PC_IS_ENABLED(); \ + CYG_MACRO_END + + +//----------------------------------------------------------------------------- +// Instruction cache line control + +// Invalidate cache lines in the given range without writing to memory. +#define HAL_ICACHE_INVALIDATE( _base_ , _size_ ) \ + HAL_CORTEXM_VYBRID_CACHE_PC_INVALIDATE(_base_, _size_) + +#else // CYGINT_HAL_CACHE + + +// Enable the data cache +#define HAL_DCACHE_ENABLE() + +// Disable the data cache +#define HAL_DCACHE_DISABLE() + +// Invalidate the entire cache +#define HAL_DCACHE_INVALIDATE_ALL() + +// Synchronize the contents of the cache with memory. +#define HAL_DCACHE_SYNC() + +// Purge contents of data cache +#define HAL_DCACHE_PURGE_ALL() + +// Query the state of the data cache (does not affect the caching) +#define HAL_DCACHE_IS_ENABLED(_state_) \ + CYG_MACRO_START \ + (_state_) = 0; \ + CYG_MACRO_END + + +//----------------------------------------------------------------------------- +// Data cache line control + +// Write dirty cache lines to memory and invalidate the cache entries +// for the given address range. +#define HAL_DCACHE_FLUSH( _base_ , _size_ ) + +// Invalidate cache lines in the given range without writing to memory. +#define HAL_DCACHE_INVALIDATE( _base_ , _size_ ) + +//----------------------------------------------------------------------------- +// Global control of Instruction cache + +// Enable the instruction cache +#define HAL_ICACHE_ENABLE() + +// Disable the instruction cache +#define HAL_ICACHE_DISABLE() + +// Invalidate the entire cache +#define HAL_ICACHE_INVALIDATE_ALL() + +// Synchronize the contents of the cache with memory. +#define HAL_ICACHE_SYNC() + +// Query the state of the instruction cache (does not affect the caching) +#define HAL_ICACHE_IS_ENABLED(_state_) \ + CYG_MACRO_START \ + (_state_) = 0; \ + CYG_MACRO_END + +//----------------------------------------------------------------------------- +// Instruction cache line control + +// Invalidate cache lines in the given range without writing to memory. +#define HAL_ICACHE_INVALIDATE( _base_ , _size_ ) + +#endif // CYGINT_HAL_CACHE + +// End of hal_cache.h +#endif // CYGONCE_HAL_CACHE_H diff --git a/ecos/packages/hal/cortexm/vybrid/var/current/include/hal_diag.h b/ecos/packages/hal/cortexm/vybrid/var/current/include/hal_diag.h new file mode 100644 index 0000000..c1f10df --- /dev/null +++ b/ecos/packages/hal/cortexm/vybrid/var/current/include/hal_diag.h @@ -0,0 +1,92 @@ +#ifndef CYGONCE_HAL_DIAG_H +#define CYGONCE_HAL_DIAG_H +//============================================================================= +// +// hal_diag.h +// +// HAL diagnostics +// +//============================================================================= +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2011 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): Antmicro Ltd <contact@antmicro.com> +// Based on: {...}/hal/packages/cortexm/kinetis/var/current/include/hal_diag.h +// Date: 2014-03-28 +// Purpose: HAL diagnostics +// Description: +// Usage: #include <cyg/hal/var_io.h> +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +#include <pkgconf/hal.h> + +#include <cyg/infra/cyg_type.h> + +#include <cyg/hal/hal_if.h> + +//----------------------------------------------------------------------------- + +#if defined(CYGSEM_HAL_VIRTUAL_VECTOR_DIAG) //VYBRID defined as 1 + +#define HAL_DIAG_INIT() hal_if_diag_init() +#define HAL_DIAG_WRITE_CHAR(_c_) hal_if_diag_write_char(_c_) +#define HAL_DIAG_READ_CHAR(_c_) hal_if_diag_read_char(&_c_) + +#else + +__externC void hal_plf_diag_init(void); +__externC void hal_plf_diag_putc(char); +__externC cyg_uint8 hal_plf_diag_getc(void); + +# ifndef HAL_DIAG_INIT +# define HAL_DIAG_INIT() hal_plf_diag_init() +# endif + +# ifndef HAL_DIAG_WRITE_CHAR +# define HAL_DIAG_WRITE_CHAR(__c) hal_plf_diag_putc(__c) +# endif + +# ifndef HAL_DIAG_READ_CHAR +# define HAL_DIAG_READ_CHAR(__c) (__c) = hal_plf_diag_getc() +# endif + +#endif + + +//----------------------------------------------------------------------------- +// end of hal_diag.h +#endif // CYGONCE_HAL_DIAG_H diff --git a/ecos/packages/hal/cortexm/vybrid/var/current/include/pkgconf/mlt_vybrid_ocram.h b/ecos/packages/hal/cortexm/vybrid/var/current/include/pkgconf/mlt_vybrid_ocram.h new file mode 100644 index 0000000..d10ccc2 --- /dev/null +++ b/ecos/packages/hal/cortexm/vybrid/var/current/include/pkgconf/mlt_vybrid_ocram.h @@ -0,0 +1,26 @@ +// eCos memory layout + +#ifndef __ASSEMBLER__ +#include <cyg/infra/cyg_type.h> +#include <stddef.h> +#endif + + +#define CYGMEM_REGION_sram_l (0x1f800000) +#define CYGMEM_REGION_sram_l_SIZE (CYGHWR_HAL_CORTEXM_VYBRID_TCML) +#define CYGMEM_REGION_sram_l_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) + +#define CYGMEM_REGION_sram (0x1f000000) +#define CYGMEM_REGION_sram_SIZE (CYGHWR_HAL_CORTEXM_VYBRID_OCRAM) +#define CYGMEM_REGION_sram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) + +#define CYGMEM_REGION_ram (0x3f800000) +#define CYGMEM_REGION_ram_SIZE (CYGHWR_HAL_CORTEXM_VYBRID_TCMU) +#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) + + +#ifndef __ASSEMBLER__ +extern char CYG_LABEL_NAME (__heap1) []; +#endif +#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1)) +#define CYGMEM_SECTION_heap1_SIZE (CYGMEM_REGION_sram+CYGMEM_REGION_sram_SIZE - (size_t) CYG_LABEL_NAME (__heap1)) diff --git a/ecos/packages/hal/cortexm/vybrid/var/current/include/pkgconf/mlt_vybrid_ocram.ldi b/ecos/packages/hal/cortexm/vybrid/var/current/include/pkgconf/mlt_vybrid_ocram.ldi new file mode 100644 index 0000000..d634d52 --- /dev/null +++ b/ecos/packages/hal/cortexm/vybrid/var/current/include/pkgconf/mlt_vybrid_ocram.ldi @@ -0,0 +1,37 @@ +// eCos memory layout +// modified for VYBRID +#include <pkgconf/hal.h> +#include <cyg/infra/cyg_type.inc> + +//------------CM4 OCRAM code + +MEMORY +{ + OCRAM : ORIGIN = 0x1f000000, LENGTH = CYGHWR_HAL_CORTEXM_VYBRID_OCRAM-(CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE) + TCML : ORIGIN = 0x1f800000, LENGTH = CYGHWR_HAL_CORTEXM_VYBRID_TCML-(CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE) + TCMU : ORIGIN = 0x3f800000, LENGTH = CYGHWR_HAL_CORTEXM_VYBRID_TCMU-(CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE) +} + + +SECTIONS +{ + SECTIONS_BEGIN + SECTION_rom_vectors (OCRAM, 0x1f000400, LMA_EQ_VMA) + SECTION_RELOCS (OCRAM, ALIGN (0x8), LMA_EQ_VMA) + SECTION_text (OCRAM, ALIGN (0x8), LMA_EQ_VMA) + SECTION_fini (OCRAM, ALIGN (0x8), LMA_EQ_VMA) + SECTION_rodata (OCRAM, ALIGN (0x8), LMA_EQ_VMA) + SECTION_fixup (OCRAM, ALIGN (0x8), LMA_EQ_VMA) + SECTION_gcc_except_table (OCRAM, ALIGN (0x8), LMA_EQ_VMA) + SECTION_eh_frame (OCRAM, ALIGN (0x8), LMA_EQ_VMA) + SECTION_got (OCRAM, ALIGN (0x8), LMA_EQ_VMA) + SECTION_data (OCRAM, ALIGN (0x8), LMA_EQ_VMA) + SECTION_bss (OCRAM, ALIGN (0x8), LMA_EQ_VMA) + SECTION_sram (OCRAM, ALIGN (0x8),LMA_EQ_VMA) + CYG_LABEL_DEFN(__heap1) = ALIGN (0x8); + SECTIONS_END +} + +hal_vsr_table = 0x1f000000; +hal_virtual_vector_table = hal_vsr_table + 128*4; +hal_startup_stack = (0x1f000000 + CYGHWR_HAL_CORTEXM_VYBRID_OCRAM); diff --git a/ecos/packages/hal/cortexm/vybrid/var/current/include/pkgconf/mlt_vybrid_tcml.h b/ecos/packages/hal/cortexm/vybrid/var/current/include/pkgconf/mlt_vybrid_tcml.h new file mode 100644 index 0000000..d10ccc2 --- /dev/null +++ b/ecos/packages/hal/cortexm/vybrid/var/current/include/pkgconf/mlt_vybrid_tcml.h @@ -0,0 +1,26 @@ +// eCos memory layout + +#ifndef __ASSEMBLER__ +#include <cyg/infra/cyg_type.h> +#include <stddef.h> +#endif + + +#define CYGMEM_REGION_sram_l (0x1f800000) +#define CYGMEM_REGION_sram_l_SIZE (CYGHWR_HAL_CORTEXM_VYBRID_TCML) +#define CYGMEM_REGION_sram_l_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) + +#define CYGMEM_REGION_sram (0x1f000000) +#define CYGMEM_REGION_sram_SIZE (CYGHWR_HAL_CORTEXM_VYBRID_OCRAM) +#define CYGMEM_REGION_sram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) + +#define CYGMEM_REGION_ram (0x3f800000) +#define CYGMEM_REGION_ram_SIZE (CYGHWR_HAL_CORTEXM_VYBRID_TCMU) +#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) + + +#ifndef __ASSEMBLER__ +extern char CYG_LABEL_NAME (__heap1) []; +#endif +#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1)) +#define CYGMEM_SECTION_heap1_SIZE (CYGMEM_REGION_sram+CYGMEM_REGION_sram_SIZE - (size_t) CYG_LABEL_NAME (__heap1)) diff --git a/ecos/packages/hal/cortexm/vybrid/var/current/include/pkgconf/mlt_vybrid_tcml.ldi b/ecos/packages/hal/cortexm/vybrid/var/current/include/pkgconf/mlt_vybrid_tcml.ldi new file mode 100644 index 0000000..01086a8 --- /dev/null +++ b/ecos/packages/hal/cortexm/vybrid/var/current/include/pkgconf/mlt_vybrid_tcml.ldi @@ -0,0 +1,39 @@ +// eCos memory layout +// modified for VYBRID +#include <pkgconf/hal.h> +#include <cyg/infra/cyg_type.inc> + +//------------CM4 TCML code + +MEMORY +{ + OCRAM : ORIGIN = 0x1f000000, LENGTH = CYGHWR_HAL_CORTEXM_VYBRID_OCRAM-(CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE) + TCML : ORIGIN = 0x1f800000, LENGTH = CYGHWR_HAL_CORTEXM_VYBRID_TCML-(CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE) + TCMU : ORIGIN = 0x3f800000, LENGTH = CYGHWR_HAL_CORTEXM_VYBRID_TCMU-(CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE) +} + +SECTIONS +{ + SECTIONS_BEGIN + SECTION_rom_vectors (TCML, 0x1f800400, LMA_EQ_VMA) + SECTION_RELOCS (TCML, ALIGN (0x8), LMA_EQ_VMA) + SECTION_text (TCML, ALIGN (0x8), LMA_EQ_VMA) + SECTION_fini (TCML, ALIGN (0x8), LMA_EQ_VMA) + SECTION_rodata (TCML, ALIGN (0x8), LMA_EQ_VMA) + SECTION_rodata1 (TCML, ALIGN (0x8), LMA_EQ_VMA) + SECTION_fixup (TCML, ALIGN (0x8), LMA_EQ_VMA) + SECTION_gcc_except_table (TCML, ALIGN (0x8), LMA_EQ_VMA) + SECTION_eh_frame (TCML, ALIGN (0x8), LMA_EQ_VMA) + SECTION_got (TCML, ALIGN (0x8), LMA_EQ_VMA) + SECTION_data (TCML, ALIGN(0x8), LMA_EQ_VMA) + SECTION_sram (TCMU, 0x3f800000, LMA_EQ_VMA) + SECTION_bss (TCMU, ALIGN (0x8), LMA_EQ_VMA) + CYG_LABEL_DEFN(__heap1) = ALIGN (0x8); + SECTIONS_END +} + +hal_vsr_table = 0x1f800000; +hal_virtual_vector_table = hal_vsr_table + 128*4; +hal_startup_stack = (0x3f800000 + 0x00007ff0); + + diff --git a/ecos/packages/hal/cortexm/vybrid/var/current/include/plf_stub.h b/ecos/packages/hal/cortexm/vybrid/var/current/include/plf_stub.h new file mode 100644 index 0000000..f42f1ab --- /dev/null +++ b/ecos/packages/hal/cortexm/vybrid/var/current/include/plf_stub.h @@ -0,0 +1,86 @@ +#ifndef CYGONCE_HAL_PLF_STUB_H +#define CYGONCE_HAL_PLF_STUB_H +//============================================================================= +// +// plf_stub.h +// +// Platform header for GDB stub support. +// +//============================================================================= +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2004, 2005, 2006, 2008, +// 2011 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): Antmicro Ltd <contact@antmicro.com> +// Based on: {...}/hal/packages/cortexm/kinetis/var/current/include/plf_stub.h +// Date: 2014-03-28 +// Purpose: Platform HAL stub support for Vybrid variant boards. +// Usage: #include <cyg/hal/plf_stub.h> +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +#include <pkgconf/hal.h> +#include CYGBLD_HAL_PLATFORM_H + +#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS + +#include <cyg/infra/cyg_type.h> // CYG_UNUSED_PARAM +#include <cyg/hal/cortexm_stub.h> // architecture stub support +#include <cyg/hal/hal_io.h> + +//---------------------------------------------------------------------------- +// Define some platform specific communication details. This is mostly +// handled by hal_if now, but we need to make sure the comms tables are +// properly initialized. + +__externC void cyg_hal_plf_comms_init(void); + +#define HAL_STUB_PLATFORM_INIT_SERIAL() cyg_hal_plf_comms_init() + +#define HAL_STUB_PLATFORM_SET_BAUD_RATE(baud) CYG_UNUSED_PARAM(int, (baud)) +#define HAL_STUB_PLATFORM_INTERRUPTIBLE 0 +#define HAL_STUB_PLATFORM_INIT_BREAK_IRQ() CYG_EMPTY_STATEMENT + +//---------------------------------------------------------------------------- +// Stub initializer. + +#define HAL_STUB_PLATFORM_INIT() CYG_EMPTY_STATEMENT + +#endif // ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS + +//----------------------------------------------------------------------------- +#endif // CYGONCE_HAL_PLF_STUB_H +// End of plf_stub.h diff --git a/ecos/packages/hal/cortexm/vybrid/var/current/include/var_arch.h b/ecos/packages/hal/cortexm/vybrid/var/current/include/var_arch.h new file mode 100644 index 0000000..8a81c94 --- /dev/null +++ b/ecos/packages/hal/cortexm/vybrid/var/current/include/var_arch.h @@ -0,0 +1,62 @@ +#ifndef CYGONCE_HAL_VAR_ARCH_H +#define CYGONCE_HAL_VAR_ARCH_H +//============================================================================= +// +// var_arch.h +// +// Vybrid variant architecture overrides +// +//============================================================================= +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2011 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): Antmicro Ltd <contact@antmicro.com> +// Based on: {...}/hal/packages/cortexm/kinetis/var/current/include/var_arch.h +// Date: 2014-03-28 +// Purpose: Vybrid variant architecture overrides +// Description: +// Usage: #include <cyg/hal/hal_arch.h> +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +#include <pkgconf/hal.h> +#include <cyg/hal/hal_io.h> +#include <cyg/hal/plf_arch.h> + + +//----------------------------------------------------------------------------- +// end of var_arch.h +#endif // CYGONCE_HAL_VAR_ARCH_H diff --git a/ecos/packages/hal/cortexm/vybrid/var/current/include/var_intr.h b/ecos/packages/hal/cortexm/vybrid/var/current/include/var_intr.h new file mode 100644 index 0000000..35938e5 --- /dev/null +++ b/ecos/packages/hal/cortexm/vybrid/var/current/include/var_intr.h @@ -0,0 +1,249 @@ +#ifndef CYGONCE_HAL_VAR_INTR_H +#define CYGONCE_HAL_VAR_INTR_H +//========================================================================== +// +// var_intr.h +// +// HAL Interrupt and clock assignments for Vybrid variants +// +//========================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2011 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): Antmicro Ltd <contact@antmicro.com> +// Based on: {...}/hal/packages/cortexm/kinetis/var/current/include/var_intr.h +// Date: 2014-03-28 +// Purpose: Define Interrupt support +// Description: The interrupt specifics for Freescale Vybrid variants are +// defined here. +// +// Usage: #include <cyg/hal/var_intr.h> +// However applications should include using <cyg/hal/hal_intr.h> +// instead to allow for platform overrides. +// +//####DESCRIPTIONEND#### +// +//========================================================================== + +#include <cyg/hal/plf_intr.h> + +//========================================================================== + +typedef enum { + CYGNUM_HAL_INTERRUPT_CPU2CPU_0 + = CYGNUM_HAL_INTERRUPT_EXTERNAL, // CPU to CPU int 0 + CYGNUM_HAL_INTERRUPT_CPU2CPU_1, // CPU to CPU int 1 + CYGNUM_HAL_INTERRUPT_CPU2CPU_2, // CPU to CPU int 2 + CYGNUM_HAL_INTERRUPT_CPU2CPU_3, // CPU to CPU int 3 + CYGNUM_HAL_INTERRUPT_SEMA4, // Directed Cortex-M4(= SEMA4) + CYGNUM_HAL_INTERRUPT_MCM, // Directed Cortex-M4(= MCM) + CYGNUM_HAL_INTERRUPT_DIRECTED1, // Directed Cortex-M4 + CYGNUM_HAL_INTERRUPT_DIRECTED2, // Directed Cortex-M4 + CYGNUM_HAL_INTERRUPT_DMA0, // DMA Channel 0 Transfer Complete + CYGNUM_HAL_INTERRUPT_DMA0_ERROR, // DMA Channel 0 Error int + CYGNUM_HAL_INTERRUPT_DMA1, // DMA Channel 1 Transfer Complete + CYGNUM_HAL_INTERRUPT_DMA1_ERROR, // DMA Channel 1 Error int + CYGNUM_HAL_INTERRUPT_RESERVED_00, + CYGNUM_HAL_INTERRUPT_RESERVED_01, + CYGNUM_HAL_INTERRUPT_MSCM_ECC0, // Error Correction and Control 0 + CYGNUM_HAL_INTERRUPT_MSCM_ECC1, // Error Correction and Control 1 + CYGNUM_HAL_INTERRUPT_CSU_ALARM, // CSU interrupt + CYGNUM_HAL_INTERRUPT_RESERVED_02, + CYGNUM_HAL_INTERRUPT_MSCM_ACTZS, // Miscellaneous System Control Module - TrustZone Security + CYGNUM_HAL_INTERRUPT_RESERVED_03, + CYGNUM_HAL_INTERRUPT_WDOG_A5, // WDOG A5 int + CYGNUM_HAL_INTERRUPT_WDOG_M4, // WDOG M4 int + CYGNUM_HAL_INTERRUPT_WDOG_SNVS, // TrustZone Watchdog + CYGNUM_HAL_INTERRUPT_CP1, // CP1 Boot Fail + CYGNUM_HAL_INTERRUPT_QSPI0, // QuadSPI0 int + CYGNUM_HAL_INTERRUPT_QSPI1, // QuadSPI1 int + CYGNUM_HAL_INTERRUPT_DDRMC, // SDRAM Memory Controller + CYGNUM_HAL_INTERRUPT_SDHC0, // Secure Digital Host Controller 0 + CYGNUM_HAL_INTERRUPT_SDHC1, // Secure Digital Host Controller 1 + CYGNUM_HAL_INTERRUPT_RESERVED_04, + CYGNUM_HAL_INTERRUPT_DCU0, // Display Control Unit 0 + CYGNUM_HAL_INTERRUPT_DCU1, // Display Control Unit 1 + CYGNUM_HAL_INTERRUPT_VIU, // Video In Unit + CYGNUM_HAL_INTERRUPT_RESERVED_05, + CYGNUM_HAL_INTERRUPT_RESERVED_06, + CYGNUM_HAL_INTERRUPT_RLE, // Run Length Encoding (Decoder unit) + CYGNUM_HAL_INTERRUPT_SEG_LCD, // LCD Controller + CYGNUM_HAL_INTERRUPT_RESERVED_07, + CYGNUM_HAL_INTERRUPT_RESERVED_08, + CYGNUM_HAL_INTERRUPT_PIT, // Periodic interrupt timer + CYGNUM_HAL_INTERRUPT_LPT0, // LPTimer0 + CYGNUM_HAL_INTERRUPT_RESERVED_09, + CYGNUM_HAL_INTERRUPT_FLXT0, // FlexTimer 0 + CYGNUM_HAL_INTERRUPT_FLXT1, // FlexTimer 1 + CYGNUM_HAL_INTERRUPT_FLXT2, // FlexTimer 2 + CYGNUM_HAL_INTERRUPT_FLXT3, // FlexTimer 3 + CYGNUM_HAL_INTERRUPT_RESERVED_10, + CYGNUM_HAL_INTERRUPT_RESERVED_11, + CYGNUM_HAL_INTERRUPT_RESERVED_12, + CYGNUM_HAL_INTERRUPT_RESERVED_13, + CYGNUM_HAL_INTERRUPT_USBPHY0, // USB PHY 0 + CYGNUM_HAL_INTERRUPT_USBPHY1, // USB PHY 1 + CYGNUM_HAL_INTERRUPT_RESERVED_14, + CYGNUM_HAL_INTERRUPT_ADC0, // AD Converter 0 + CYGNUM_HAL_INTERRUPT_ADC1, // AD Converter 1 + CYGNUM_HAL_INTERRUPT_DAC0, // DA Converter 0 + CYGNUM_HAL_INTERRUPT_DAC1, // DA Converter 1 + CYGNUM_HAL_INTERRUPT_RESERVED_15, + CYGNUM_HAL_INTERRUPT_FLXCAN0, // FlexCAN 0 + CYGNUM_HAL_INTERRUPT_FLXCAN1, // FlexCAN 1 + CYGNUM_HAL_INTERRUPT_RESERVED_16, + CYGNUM_HAL_INTERRUPT_UART0_RX_TX, // UART0 Controller + CYGNUM_HAL_INTERRUPT_UART1_RX_TX, // UART1 Controller + CYGNUM_HAL_INTERRUPT_UART2_RX_TX, // UART2 Controller + CYGNUM_HAL_INTERRUPT_UART3_RX_TX, // UART3 Controller + CYGNUM_HAL_INTERRUPT_UART4_RX_TX, // UART4 Controller + CYGNUM_HAL_INTERRUPT_UART5_RX_TX, // UART5 Controller + CYGNUM_HAL_INTERRUPT_SPI0, // SPI0 + CYGNUM_HAL_INTERRUPT_SPI1, // SPI1 + CYGNUM_HAL_INTERRUPT_SPI2, // SPI2 + CYGNUM_HAL_INTERRUPT_SPI3, // SPI3 + CYGNUM_HAL_INTERRUPT_I2C0, // I2C0 + CYGNUM_HAL_INTERRUPT_I2C1, // I2C1 + CYGNUM_HAL_INTERRUPT_I2C2, // I2C2 + CYGNUM_HAL_INTERRUPT_I2C3, // I2C3 + CYGNUM_HAL_INTERRUPT_USBC0, // USB 0 Controller + CYGNUM_HAL_INTERRUPT_USBC1, // USB 1 Controller + CYGNUM_HAL_INTERRUPT_RESERVED_17, + CYGNUM_HAL_INTERRUPT_ENET0, // Ethernet MAC 0 + CYGNUM_HAL_INTERRUPT_ENET1, // Ethernet MAC 1 + CYGNUM_HAL_INTERRUPT_1588_0, // IEEE 1588 T0 + CYGNUM_HAL_INTERRUPT_1588_1, // IEEE 1588 T1 + CYGNUM_HAL_INTERRUPT_ENET_SWI, // Ethernet L2 swich + CYGNUM_HAL_INTERRUPT_NFC, // Nand Flash Controller + CYGNUM_HAL_INTERRUPT_SAI0, // Synchronous Audio Interface 0 + CYGNUM_HAL_INTERRUPT_SAI1, // Synchronous Audio Interface 1 + CYGNUM_HAL_INTERRUPT_SAI2, // Synchronous Audio Interface 2 + CYGNUM_HAL_INTERRUPT_SAI3, // Synchronous Audio Interface 3 + CYGNUM_HAL_INTERRUPT_ESAI_BIFIFO, // Enhanced Serial Audio Interface Bus Interface and FIFO + CYGNUM_HAL_INTERRUPT_SPDIF, // Sony/Philips Digital Interface + CYGNUM_HAL_INTERRUPT_ASRC, // Audio Sample Rate Converter + CYGNUM_HAL_INTERRUPT_VREG, // HVD Int + CYGNUM_HAL_INTERRUPT_WKPU0, // Wake Up 0 + CYGNUM_HAL_INTERRUPT_RESERVED_18, + CYGNUM_HAL_INTERRUPT_CCM, // FXOSC ready int + CYGNUM_HAL_INTERRUPT_CCM_2, // Logical OR of LRF of PLL1, PLL2, PLL3, PLL4 + CYGNUM_HAL_INTERRUPT_SRC, // System Reset Controller + CYGNUM_HAL_INTERRUPT_PDB, // Programmable Delay Block + CYGNUM_HAL_INTERRUPT_EWM, // External Watchdog Monitor + CYGNUM_HAL_INTERRUPT_RESERVED_19, + CYGNUM_HAL_INTERRUPT_RESERVED_20, + CYGNUM_HAL_INTERRUPT_RESERVED_21, + CYGNUM_HAL_INTERRUPT_RESERVED_22, + CYGNUM_HAL_INTERRUPT_RESERVED_23, + CYGNUM_HAL_INTERRUPT_RESERVED_24, + CYGNUM_HAL_INTERRUPT_RESERVED_25, + CYGNUM_HAL_INTERRUPT_RESERVED_26, + CYGNUM_HAL_INTERRUPT_GPIO0, // GPIO PORT0 interrupts/ Wake-ups + CYGNUM_HAL_INTERRUPT_GPIO1, // GPIO PORT1 interrupts/ Wake-ups + CYGNUM_HAL_INTERRUPT_GPIO2, // GPIO PORT2 interrupts/ Wake-ups + CYGNUM_HAL_INTERRUPT_GPIO3, // GPIO PORT3 interrupts/ Wake-ups + CYGNUM_HAL_INTERRUPT_GPIO4 // GPIO PORT4 interrupts/ Wake-ups +} VybridExtInterrupt_e; + + +// Ranges of usable interrupt sources +#define CYGNUM_HAL_INTERRUPT_NVIC_MAX CYGNUM_HAL_INTERRUPT_GPIO4 +#define CYGNUM_HAL_ISR_MIN 0 +#define CYGNUM_HAL_ISR_MAX CYGNUM_HAL_INTERRUPT_GPIO4 +#define CYGNUM_HAL_ISR_COUNT (CYGNUM_HAL_ISR_MAX + 1) + +#define CYGNUM_HAL_VSR_MIN 0 +#ifndef CYGNUM_HAL_VSR_MAX +# define CYGNUM_HAL_VSR_MAX (CYGNUM_HAL_VECTOR_SYS_TICK+ \ + CYGNUM_HAL_INTERRUPT_NVIC_MAX) +#endif + +#define CYGNUM_HAL_VSR_COUNT (CYGNUM_HAL_VSR_MAX+1) + +//========================================================================== +// Interrupt mask and config for variant-specific devices + +// PORT Pin interrupts + +#define CYGHWR_HAL_VYBRID_PIN_IRQ_VECTOR(__pin) \ + (CYGNUM_HAL_INTERRUPT_PORTA + CYGHWR_HAL_VYBRID_PIN_PORT(__pin)) + +//=========================================================================== +// Interrupt resources exported by HAL to device drivers + +// Export Interrupt vectors to serial driver. + +#define CYGNUM_IO_SERIAL_FREESCALE_UART0_INT_VECTOR \ + CYGNUM_HAL_INTERRUPT_UART0_RX_TX +#define CYGNUM_IO_SERIAL_FREESCALE_UART1_INT_VECTOR \ + CYGNUM_HAL_INTERRUPT_UART1_RX_TX +#define CYGNUM_IO_SERIAL_FREESCALE_UART2_INT_VECTOR \ + CYGNUM_HAL_INTERRUPT_UART2_RX_TX +#define CYGNUM_IO_SERIAL_FREESCALE_UART3_INT_VECTOR \ + CYGNUM_HAL_INTERRUPT_UART3_RX_TX +#define CYGNUM_IO_SERIAL_FREESCALE_UART4_INT_VECTOR \ + CYGNUM_HAL_INTERRUPT_UART4_RX_TX +#define CYGNUM_IO_SERIAL_FREESCALE_UART5_INT_VECTOR \ + CYGNUM_HAL_INTERRUPT_UART5_RX_TX + +// Export Interrupt vectors to ENET driver. + +#define CYGNUM_FREESCALE_ENET0_1588_TIMER_INT_VECTOR \ + CYGNUM_HAL_INTERRUPT_ENET_1588_TIMER +#define CYGNUM_FREESCALE_ENET0_TRANSMIT_INT_VECTOR \ + CYGNUM_HAL_INTERRUPT_ENET_TRANSMIT +#define CYGNUM_FREESCALE_ENET0_RECEIVE_INT_VECTOR \ + CYGNUM_HAL_INTERRUPT_ENET_RECEIVE +#define CYGNUM_FREESCALE_ENET0_ERROR_INT_VECTOR \ + CYGNUM_HAL_INTERRUPT_ENET_ERROR + +#define HAL_VAR_INTERRUPT_MASK( __vector ) CYG_EMPTY_STATEMENT +#define HAL_VAR_INTERRUPT_UNMASK( __vector ) CYG_EMPTY_STATEMENT +#define HAL_VAR_INTERRUPT_CONFIGURE( __vector, __level, __up ) CYG_EMPTY_STATEMENT +#define HAL_VAR_INTERRUPT_ACKNOWLEDGE( __vector ) CYG_EMPTY_STATEMENT + +#define HAL_VAR_INTERRUPT_SET_LEVEL( __vector, __level ) \ +{ \ + cyg_uint16 reg; \ + if(__vector > 0 ) \ + { \ + HAL_READ_UINT16((CYGHWR_HAL_VYBRID_MSCM_IRSPRCn_BASE + ((__vector - 1 )*2)), reg);\ + reg |= (1 << CYGHWR_HAL_VYBRID_MSCM_IRSPRCn_CP1En_S); \ + HAL_WRITE_UINT16((CYGHWR_HAL_VYBRID_MSCM_IRSPRCn_BASE + ((__vector - 1 )*2)), reg);\ + } \ +} + +//---------------------------------------------------------------------------- +#endif // CYGONCE_HAL_VAR_INTR_H +// EOF var_intr.h diff --git a/ecos/packages/hal/cortexm/vybrid/var/current/include/var_io.h b/ecos/packages/hal/cortexm/vybrid/var/current/include/var_io.h new file mode 100644 index 0000000..4e01990 --- /dev/null +++ b/ecos/packages/hal/cortexm/vybrid/var/current/include/var_io.h @@ -0,0 +1,753 @@ +#ifndef CYGONCE_HAL_VAR_IO_H +#define CYGONCE_HAL_VAR_IO_H +//=========================================================================== +// +// var_io.h +// +// Variant specific registers +// +//=========================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2011, 2013 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//=========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): Antmicro Ltd <contact@antmicro.com> +// Based on: {...}/hal/packages/cortexm/kinetis/var/current/include/var_io.h +// Date: 2014-03-28 +// Purpose: Vybrid variant specific registers +// Description: +// Usage: #include <cyg/hal/var_io.h> +// +//####DESCRIPTIONEND#### +// +//=========================================================================== + +#include <pkgconf/hal_cortexm_vybrid.h> + +#include <cyg/hal/plf_io.h> + +//=========================================================================== +// Cortex-M architecture +//--------------------------------------------------------------------------- +//--------------------------------------------------------------------------- +// Cortex-M architecture overrides +//--------------------------------------------------------------------------- +// VTOR - Vector Table Offset Register + +#ifndef CYGARC_REG_NVIC_VTOR_TBLBASE_SRAM +#ifdef CYG_HAL_VTOR_ADRESS +#define CYGARC_REG_NVIC_VTOR_TBLBASE_SRAM CYG_HAL_VTOR_ADRESS +#else +#define CYGARC_REG_NVIC_VTOR_TBLBASE_SRAM 0x1f800000 +#endif +#endif + +//=========================================================================== +// Vybrid Memory layout +//--------------------------------------------------------------------------- +#define CYGHWR_HAL_VYBRID_OCRAM1_BASE 0x3f040000 +#define CYGHWR_HAL_VYBRID_OCRAM1_SIZE 0x0003ffff + +//=========================================================================== +// Vybrid Peripherals +//--------------------------------------------------------------------------- +//--------------------------------------------------------------------------- +// MSCM - Miscellaneous System Control Module +#define CYGHWR_HAL_VYBRID_MSCM_BASE 0x40001000 +#define CYGHWR_HAL_VYBRID_MSCM_CPxTYPE (CYGHWR_HAL_VYBRID_MSCM_BASE + 0x000) +#define CYGHWR_HAL_VYBRID_MSCM_CPxTYPE_PERSONALITY_M 0xFFFFFF00 +#define CYGHWR_HAL_VYBRID_MSCM_CPxTYPE_PERSONALITY_S 8 +#define CYGHWR_HAL_VYBRID_MSCM_CPxTYPE_RYPZ_M 0x000000FF +#define CYGHWR_HAL_VYBRID_MSCM_CPxTYPE_RYPZ_S 0 +#define CYGHWR_HAL_VYBRID_MSCM_CPxNUM (CYGHWR_HAL_VYBRID_MSCM_BASE + 0x004) +#define CYGHWR_HAL_VYBRID_MSCM_CPxNUM_CPN_M 0x00000001 +#define CYGHWR_HAL_VYBRID_MSCM_CPxNUM_CPN_S 0 +#define CYGHWR_HAL_VYBRID_MSCM_CPxMASTER (CYGHWR_HAL_VYBRID_MSCM_BASE + 0x008) +#define CYGHWR_HAL_VYBRID_MSCM_CPxMASTER_PPN_M 0x0000001f +#define CYGHWR_HAL_VYBRID_MSCM_CPxMASTER_PPN_S 0 +#define CYGHWR_HAL_VYBRID_MSCM_CPxCOUNT (CYGHWR_HAL_VYBRID_MSCM_BASE + 0x00c) +#define CYGHWR_HAL_VYBRID_MSCM_CPxNUM_PCNT_M 0x00000001 +#define CYGHWR_HAL_VYBRID_MSCM_CPxNUM_PCNT_S 0 +#define CYGHWR_HAL_VYBRID_MSCM_CPxCFG0 (CYGHWR_HAL_VYBRID_MSCM_BASE + 0x010) +#define CYGHWR_HAL_VYBRID_MSCM_CPxCFG1 (CYGHWR_HAL_VYBRID_MSCM_BASE + 0x014) +#define CYGHWR_HAL_VYBRID_MSCM_CPxCFG2 (CYGHWR_HAL_VYBRID_MSCM_BASE + 0x018) +#define CYGHWR_HAL_VYBRID_MSCM_CPxCFG3 (CYGHWR_HAL_VYBRID_MSCM_BASE + 0x01c) +#define CYGHWR_HAL_VYBRID_MSCM_IRCP0IR (CYGHWR_HAL_VYBRID_MSCM_BASE + 0x800) +#define CYGHWR_HAL_VYBRID_MSCM_IRCP0IR_INT0_M 0x00000001 +#define CYGHWR_HAL_VYBRID_MSCM_IRCP0IR_INT0_S 0 +#define CYGHWR_HAL_VYBRID_MSCM_IRCP0IR_INT1_M 0x00000002 +#define CYGHWR_HAL_VYBRID_MSCM_IRCP0IR_INT1_S 1 +#define CYGHWR_HAL_VYBRID_MSCM_IRCP0IR_INT2_M 0x00000004 +#define CYGHWR_HAL_VYBRID_MSCM_IRCP0IR_INT2_S 2 +#define CYGHWR_HAL_VYBRID_MSCM_IRCP0IR_INT3_M 0x00000008 +#define CYGHWR_HAL_VYBRID_MSCM_IRCP0IR_INT3_S 3 +#define CYGHWR_HAL_VYBRID_MSCM_IRCP1IR (CYGHWR_HAL_VYBRID_MSCM_BASE + 0x804) +#define CYGHWR_HAL_VYBRID_MSCM_IRCP1IR_INT0_M 0x00000001 +#define CYGHWR_HAL_VYBRID_MSCM_IRCP1IR_INT0_S 0 +#define CYGHWR_HAL_VYBRID_MSCM_IRCP1IR_INT1_M 0x00000002 +#define CYGHWR_HAL_VYBRID_MSCM_IRCP1IR_INT1_S 1 +#define CYGHWR_HAL_VYBRID_MSCM_IRCP1IR_INT2_M 0x00000004 +#define CYGHWR_HAL_VYBRID_MSCM_IRCP1IR_INT2_S 2 +#define CYGHWR_HAL_VYBRID_MSCM_IRCP1IR_INT3_M 0x00000008 +#define CYGHWR_HAL_VYBRID_MSCM_IRCP1IR_INT3_S 3 +#define CYGHWR_HAL_VYBRID_MSCM_IRCPGIR (CYGHWR_HAL_VYBRID_MSCM_BASE + 0x820) +#define CYGHWR_HAL_VYBRID_MSCM_IRCPGIR_INTID_M 0x00000003 +#define CYGHWR_HAL_VYBRID_MSCM_IRCPGIR_INTID_S 0 +#define CYGHWR_HAL_VYBRID_MSCM_IRCPGIR_CPUTL_M 0x00030000 +#define CYGHWR_HAL_VYBRID_MSCM_IRCPGIR_CPUTL_S 16 +#define CYGHWR_HAL_VYBRID_MSCM_IRCPGIR_TLF_M 0x03000000 +#define CYGHWR_HAL_VYBRID_MSCM_IRCPGIR_TLF_S 24 +#define CYGHWR_HAL_VYBRID_MSCM_IRSPRCn_BASE (CYGHWR_HAL_VYBRID_MSCM_BASE + 0x880) +#define CYGHWR_HAL_VYBRID_MSCM_IRSPRCn_CP1En_M 0x0002 +#define CYGHWR_HAL_VYBRID_MSCM_IRSPRCn_CP1En_S 0 +#define CYGHWR_HAL_VYBRID_MSCM_IRSPRCn_CP0En_M 0x0001 +#define CYGHWR_HAL_VYBRID_MSCM_IRSPRCn_CP0En_S 1 +#define CYGHWR_HAL_VYBRID_MSCM_IRSPRCn_RO_M 0x8000 +#define CYGHWR_HAL_VYBRID_MSCM_IRSPRCn_RO_S 15 + +__externC int hal_get_core_num(void); + +//--------------------------------------------------------------------------- +// SEMA4 - IPS Semaphores +// SEMA4 - Peripheral register structure +typedef volatile struct cyghwr_hal_vybrid_sema4_s +{ + cyg_uint8 gate[16]; + cyg_uint8 reserved0[50]; + cyg_uint16 cp0ine; + cyg_uint8 reserved1[6]; + cyg_uint16 cp1ine; + cyg_uint8 reserved2[54]; + cyg_uint16 cp0ntf; + cyg_uint8 reserved3[6]; + cyg_uint16 cp1ntf; + cyg_uint8 reserved4[118]; + cyg_uint16 rstgt; + cyg_uint8 reserved5[2]; + cyg_uint16 rstntf; +} cyghwr_hal_vybrid_sema4_t; + +#define CYGHWR_HAL_VYBRID_SEMA4_GATE_GTFSM_M 0x03 +#define CYGHWR_HAL_VYBRID_SEMA4_P ((cyghwr_hal_vybrid_sema4_t *) 0x4001d000) + +//--------------------------------------------------------------------------- +// CCM - Clock Controller Module +// CCM - Peripheral register structure +typedef volatile struct cyghwr_hal_vybrid_ccm_s { + cyg_uint32 ccr; // + cyg_uint32 csr; // + cyg_uint32 ccsr; // + cyg_uint32 cacrr; // + cyg_uint32 cscmr1; // + cyg_uint32 cscdr1; // + cyg_uint32 cscdr2; // + cyg_uint32 cscdr3; // + cyg_uint32 cscmr2; // + cyg_uint32 reserved0; // + cyg_uint32 ctor; // + cyg_uint32 clpcr; // + cyg_uint32 cisr; // + cyg_uint32 cimr; // + cyg_uint32 ccosr; // + cyg_uint32 cgpr; // + cyg_uint32 ccgr0; // + cyg_uint32 ccgr1; // + cyg_uint32 ccgr2; // + cyg_uint32 ccgr3; // + cyg_uint32 ccgr4; // + cyg_uint32 ccgr5; // + cyg_uint32 ccgr6; // + cyg_uint32 ccgr7; // + cyg_uint32 ccgr8; // + cyg_uint32 ccgr9; // + cyg_uint32 ccgr10; // + cyg_uint32 ccgr11; // + cyg_uint32 cmeor0; // + cyg_uint32 cmeor1; // + cyg_uint32 cmeor2; // + cyg_uint32 cmeor3; // + cyg_uint32 cmeor4; // + cyg_uint32 cmeor5; // + cyg_uint32 cppdsr; // + cyg_uint32 ccowr; // + cyg_uint32 ccpgr0; // + cyg_uint32 ccpgr1; // + cyg_uint32 ccpgr2; // + cyg_uint32 ccpgr3; // + +} cyghwr_hal_vybrid_ccm_t; + + +#define CYGHWR_HAL_VYBRID_CCM_P ((cyghwr_hal_vybrid_ccm_t *) 0x4006B000) + +// CCR Fields +#define CYGHWR_HAL_VYBRID_CCM_CCR_FIRC_M 0x00010000 +#define CYGHWR_HAL_VYBRID_CCM_CCR_FIRC_S 16 +#define CYGHWR_HAL_VYBRID_CCM_CCR_FXOSC_EN_M 0x00001000 +#define CYGHWR_HAL_VYBRID_CCM_CCR_FXOSC_EN_S 12 +#define CYGHWR_HAL_VYBRID_CCM_CCR_OSCNT_M 0x000000ff +#define CYGHWR_HAL_VYBRID_CCM_CCR_OSCNT_S 0 + +// CSR Fields +#define CYGHWR_HAL_VYBRID_CCM_CSR_FXOSC_RDY_M 0x00000020 +#define CYGHWR_HAL_VYBRID_CCM_CSR_FXOSC_RDY_S 5 + + +// CACRR Bit Fields +#define CYGHWR_HAL_VYBRID_CCM_CACRR_FLEX_CLK_DIV_M 0x1C00000 +#define CYGHWR_HAL_VYBRID_CCM_CACRR_FLEX_CLK_DIV_S 22 +#define CYGHWR_HAL_VYBRID_CCM_CACRR_PLL6_CLK_DIV_M 0x0200000 +#define CYGHWR_HAL_VYBRID_CCM_CACRR_PLL6_CLK_DIV_S 21 +#define CYGHWR_HAL_VYBRID_CCM_CACRR_PLL3_CLK_DIV_M 0x0100000 +#define CYGHWR_HAL_VYBRID_CCM_CACRR_PLL3_CLK_DIV_S 20 +#define CYGHWR_HAL_VYBRID_CCM_CACRR_PLL1_PFD_CLK_DIV_M 0x0030000 +#define CYGHWR_HAL_VYBRID_CCM_CACRR_PLL1_PFD_CLK_DIV_S 16 +#define CYGHWR_HAL_VYBRID_CCM_CACRR_IPG_CLK_DIV_M 0x0001800 +#define CYGHWR_HAL_VYBRID_CCM_CACRR_IPG_CLK_DIV_S 11 +#define CYGHWR_HAL_VYBRID_CCM_CACRR_PLL4_CLK_DIV_M 0x00001C0 +#define CYGHWR_HAL_VYBRID_CCM_CACRR_PLL4_CLK_DIV_S 6 +#define CYGHWR_HAL_VYBRID_CCM_CACRR_BUS_CLK_DIV_M 0x0000038 +#define CYGHWR_HAL_VYBRID_CCM_CACRR_BUS_CLK_DIV_S 3 +#define CYGHWR_HAL_VYBRID_CCM_CACRR_ARM_CLK_DIV_M 0x0000007 +#define CYGHWR_HAL_VYBRID_CCM_CACRR_ARM_CLK_DIV_S 0 + +// CCSR Bit Fields +#define CYGHWR_HAL_VYBRID_CCM_CCSR_PLL3_PFD4_EN_M 0x80000000 +#define CYGHWR_HAL_VYBRID_CCM_CCSR_PLL3_PFD4_EN_S 31 +#define CYGHWR_HAL_VYBRID_CCM_CCSR_PLL3_PFD3_EN_M 0x40000000 +#define CYGHWR_HAL_VYBRID_CCM_CCSR_PLL3_PFD3_EN_S 30 +#define CYGHWR_HAL_VYBRID_CCM_CCSR_PLL3_PFD2_EN_M 0x20000000 +#define CYGHWR_HAL_VYBRID_CCM_CCSR_PLL3_PFD2_EN_S 29 +#define CYGHWR_HAL_VYBRID_CCM_CCSR_PLL3_PFD1_EN_M 0x10000000 +#define CYGHWR_HAL_VYBRID_CCM_CCSR_PLL3_PFD1_EN_S 28 +#define CYGHWR_HAL_VYBRID_CCM_CCSR_DAP_EN_M 0x01000000 +#define CYGHWR_HAL_VYBRID_CCM_CCSR_DAP_EN_S 24 +#define CYGHWR_HAL_VYBRID_CCM_CCSR_PLL2_PFD_CLK_SEL_M 0x00380000 +#define CYGHWR_HAL_VYBRID_CCM_CCSR_PLL2_PFD_CLK_SEL_S 19 +#define CYGHWR_HAL_VYBRID_CCM_CCSR_PLL1_PFD_CLK_SEL_M 0x00070000 +#define CYGHWR_HAL_VYBRID_CCM_CCSR_PLL1_PFD_CLK_SEL_S 16 +#define CYGHWR_HAL_VYBRID_CCM_CCSR_PLL2_PFD4_EN_M 0x00008000 +#define CYGHWR_HAL_VYBRID_CCM_CCSR_PLL2_PFD4_EN_S 15 +#define CYGHWR_HAL_VYBRID_CCM_CCSR_PLL2_PFD3_EN_M 0x00004000 +#define CYGHWR_HAL_VYBRID_CCM_CCSR_PLL2_PFD3_EN_S 14 +#define CYGHWR_HAL_VYBRID_CCM_CCSR_PLL2_PFD2_EN_M 0x00002000 +#define CYGHWR_HAL_VYBRID_CCM_CCSR_PLL2_PFD2_EN_S 13 +#define CYGHWR_HAL_VYBRID_CCM_CCSR_PLL2_PFD1_EN_M 0x00001000 +#define CYGHWR_HAL_VYBRID_CCM_CCSR_PLL2_PFD1_EN_S 12 +#define CYGHWR_HAL_VYBRID_CCM_CCSR_PLL1_PFD4_EN_M 0x00000800 +#define CYGHWR_HAL_VYBRID_CCM_CCSR_PLL1_PFD4_EN_S 11 +#define CYGHWR_HAL_VYBRID_CCM_CCSR_PLL1_PFD3_EN_M 0x00000400 +#define CYGHWR_HAL_VYBRID_CCM_CCSR_PLL1_PFD3_EN_S 10 +#define CYGHWR_HAL_VYBRID_CCM_CCSR_PLL1_PFD2_EN_M 0x00000200 +#define CYGHWR_HAL_VYBRID_CCM_CCSR_PLL1_PFD2_EN_S 9 +#define CYGHWR_HAL_VYBRID_CCM_CCSR_PLL1_PFD1_EN_M 0x00000100 +#define CYGHWR_HAL_VYBRID_CCM_CCSR_PLL1_PFD1_EN_S 8 +#define CYGHWR_HAL_VYBRID_CCM_CCSR_DDRC_CLK_SEL_M 0x00000040 +#define CYGHWR_HAL_VYBRID_CCM_CCSR_DDRC_CLK_SEL_S 6 +#define CYGHWR_HAL_VYBRID_CCM_CCSR_FAST_CLK_SEL_M 0x00000020 +#define CYGHWR_HAL_VYBRID_CCM_CCSR_FAST_CLK_SEL_S 5 +#define CYGHWR_HAL_VYBRID_CCM_CCSR_SLOW_CLK_SEL_M 0x00000010 +#define CYGHWR_HAL_VYBRID_CCM_CCSR_SLOW_CLK_SEL_S 4 +#define CYGHWR_HAL_VYBRID_CCM_CCSR_SYS_CLK_SEL_M 0x00000007 +#define CYGHWR_HAL_VYBRID_CCM_CCSR_SYS_CLK_SEL_S 0 + + +// CSCMR1 Bit Fields +#define CYGHWR_HAL_VYBRID_CCM_CSCMR1_DCU1_CLK_SEL_M 0x20000000 +#define CYGHWR_HAL_VYBRID_CCM_CSCMR1_DCU1_CLK_SEL_S 29 +#define CYGHWR_HAL_VYBRID_CCM_CSCMR1_DCU0_CLK_SEL_M 0x10000000 +#define CYGHWR_HAL_VYBRID_CCM_CSCMR1_DCU0_CLK_SEL_S 28 +#define CYGHWR_HAL_VYBRID_CCM_CSCMR1_QSPI1_CLK_SEL_M 0x03000000 +#define CYGHWR_HAL_VYBRID_CCM_CSCMR1_QSPI1_CLK_SEL_S 24 +#define CYGHWR_HAL_VYBRID_CCM_CSCMR1_QSPIO_CLK_SEL_M 0x00C00000 +#define CYGHWR_HAL_VYBRID_CCM_CSCMR1_QSPIO_CLK_SEL_S 22 +#define CYGHWR_HAL_VYBRID_CCM_CSCMR1_ESAI_CLK_SEL_M 0x00300000 +#define CYGHWR_HAL_VYBRID_CCM_CSCMR1_ESAI_CLK_SEL_S 20 +#define CYGHWR_HAL_VYBRID_CCM_CSCMR1_ESDHC1_CLK_SEL_M 0x000C0000 +#define CYGHWR_HAL_VYBRID_CCM_CSCMR1_ESDHC1_CLK_SEL_S 18 +#define CYGHWR_HAL_VYBRID_CCM_CSCMR1_ESDHC0_CLK_SEL_M 0x00030000 +#define CYGHWR_HAL_VYBRID_CCM_CSCMR1_ESDHC0_CLK_SEL_S 16 +#define CYGHWR_HAL_VYBRID_CCM_CSCMR1_NFC_CLK_SEL_M 0x00003000 +#define CYGHWR_HAL_VYBRID_CCM_CSCMR1_NFC_CLK_SEL_S 12 +#define CYGHWR_HAL_VYBRID_CCM_CSCMR1_VADC_CLK_SEL_M 0x00000300 +#define CYGHWR_HAL_VYBRID_CCM_CSCMR1_VADC_CLK_SEL_S 8 +#define CYGHWR_HAL_VYBRID_CCM_CSCMR1_SAI3_CLK_SEL_M 0x000000C0 +#define CYGHWR_HAL_VYBRID_CCM_CSCMR1_SAI3_CLK_SEL_S 6 +#define CYGHWR_HAL_VYBRID_CCM_CSCMR1_SAI2_CLK_SEL_M 0x00000030 +#define CYGHWR_HAL_VYBRID_CCM_CSCMR1_SAI2_CLK_SEL_S 4 +#define CYGHWR_HAL_VYBRID_CCM_CSCMR1_SAI1_CLK_SEL_M 0x0000000C +#define CYGHWR_HAL_VYBRID_CCM_CSCMR1_SAI1_CLK_SEL_S 2 +#define CYGHWR_HAL_VYBRID_CCM_CSCMR1_SAI0_CLK_SEL_M 0x00000003 +#define CYGHWR_HAL_VYBRID_CCM_CSCMR1_SAI0_CLK_SEL_S 0 + +//--------------------------------------------------------------------------- +// FTM - Flex Timer Module +typedef volatile struct cyghwr_hal_vybrid_ftm_chnl_s { + cyg_uint32 sc; + cyg_uint32 v; +}cyghwr_hal_vybrid_ftm_chnl_t; + + +typedef volatile struct cyghwr_hal_vybrid_ftm_s { + cyg_uint32 sc; + cyg_uint32 cnt; + cyg_uint32 mod; + cyghwr_hal_vybrid_ftm_chnl_t c[8]; + cyg_uint32 cntin; + cyg_uint32 status; + cyg_uint32 mode; + cyg_uint32 sync; + cyg_uint32 outinit; + cyg_uint32 outmask; + cyg_uint32 combine; + cyg_uint32 deadtime; + cyg_uint32 exttrig; + cyg_uint32 pol; + cyg_uint32 fms; + cyg_uint32 filter; + cyg_uint32 fltctrl; + cyg_uint32 qdctrl; + cyg_uint32 conf; + cyg_uint32 fltpol; + cyg_uint32 synconf; + cyg_uint32 invctrl; + cyg_uint32 swoctrl; + cyg_uint32 pwmload; +} cyghwr_hal_vybrid_ftm_t; + + +#define CYGHWR_HAL_VYBRID_FTM0_P ((cyghwr_hal_vybrid_ftm_t *)0x40038000) +#define CYGHWR_HAL_VYBRID_FTM1_P ((cyghwr_hal_vybrid_ftm_t *)0x40039000) +#define CYGHWR_HAL_VYBRID_FTM2_P ((cyghwr_hal_vybrid_ftm_t *)0x400b8000) +#define CYGHWR_HAL_VYBRID_FTM3_P ((cyghwr_hal_vybrid_ftm_t *)0x400b9000) + + +//--------------------------------------------------------------------------- +// ANADIG - Analog components control digital interface +// ANADIG - Peripheral register structure + +// The ANADIG module has a very wide memory layout. +// Between each register is a 12 bytes free space. Therefore typical implementation +// of this module as structure is wasteful. + +#define CYGHWR_HAL_VYBRID_ANADIG_BASE_ADDR 0x40050000 +#define CYGHWR_HAL_VYBRID_ANADIG_PLL1_CTRL (CYGHWR_HAL_VYBRID_ANADIG_BASE_ADDR + 0x270) +#define CYGHWR_HAL_VYBRID_ANADIG_PLL1_SS (CYGHWR_HAL_VYBRID_ANADIG_BASE_ADDR + 0x280) +#define CYGHWR_HAL_VYBRID_ANADIG_PLL1_NUM (CYGHWR_HAL_VYBRID_ANADIG_BASE_ADDR + 0x290) +#define CYGHWR_HAL_VYBRID_ANADIG_PLL1_DENOM (CYGHWR_HAL_VYBRID_ANADIG_BASE_ADDR + 0x2a0) +#define CYGHWR_HAL_VYBRID_ANADIG_PLL1_PFD (CYGHWR_HAL_VYBRID_ANADIG_BASE_ADDR + 0x2b0) +#define CYGHWR_HAL_VYBRID_ANADIG_PLL2_CTRL (CYGHWR_HAL_VYBRID_ANADIG_BASE_ADDR + 0x30) +#define CYGHWR_HAL_VYBRID_ANADIG_PLL2_SS (CYGHWR_HAL_VYBRID_ANADIG_BASE_ADDR + 0x40) +#define CYGHWR_HAL_VYBRID_ANADIG_PLL2_NUM (CYGHWR_HAL_VYBRID_ANADIG_BASE_ADDR + 0x50) +#define CYGHWR_HAL_VYBRID_ANADIG_PLL2_DENOM (CYGHWR_HAL_VYBRID_ANADIG_BASE_ADDR + 0x60) +#define CYGHWR_HAL_VYBRID_ANADIG_PLL2_PFD (CYGHWR_HAL_VYBRID_ANADIG_BASE_ADDR + 0x100) +#define CYGHWR_HAL_VYBRID_ANADIG_PLL3_CTRL (CYGHWR_HAL_VYBRID_ANADIG_BASE_ADDR + 0x10) +#define CYGHWR_HAL_VYBRID_ANADIG_PLL3_PFD (CYGHWR_HAL_VYBRID_ANADIG_BASE_ADDR + 0x60) + +// PLL1_CTRL Bit Fields +#define CYGHWR_HAL_VYBRID_ANADIG_PLL1_CTRL_LOCK_M 0x80000000 +#define CYGHWR_HAL_VYBRID_ANADIG_PLL1_CTRL_LOCK_S 31 +#define CYGHWR_HAL_VYBRID_ANADIG_PLL1_CTRL_PFD_OFFSET_EN_M 0x00040000 +#define CYGHWR_HAL_VYBRID_ANADIG_PLL1_CTRL_PFD_OFFSET_EN_S 18 +#define CYGHWR_HAL_VYBRID_ANADIG_PLL1_CTRL_DITHER_ENABLE_M 0x00020000 +#define CYGHWR_HAL_VYBRID_ANADIG_PLL1_CTRL_DITHER_ENABLE_S 17 +#define CYGHWR_HAL_VYBRID_ANADIG_PLL1_CTRL_BYPASS_M 0x00010000 +#define CYGHWR_HAL_VYBRID_ANADIG_PLL1_CTRL_BYPASS_S 16 +#define CYGHWR_HAL_VYBRID_ANADIG_PLL1_CTRL_BYPASS_CLK_SRC_M 0x00004000 +#define CYGHWR_HAL_VYBRID_ANADIG_PLL1_CTRL_BYPASS_CLK_SRC_S 14 +#define CYGHWR_HAL_VYBRID_ANADIG_PLL1_CTRL_ENABLE_M 0x00002000 +#define CYGHWR_HAL_VYBRID_ANADIG_PLL1_CTRL_ENABLE_S 13 +#define CYGHWR_HAL_VYBRID_ANADIG_PLL1_CTRL_POWERDOWN_M 0x00001000 +#define CYGHWR_HAL_VYBRID_ANADIG_PLL1_CTRL_POWERDOWN_S 12 +#define CYGHWR_HAL_VYBRID_ANADIG_PLL1_CTRL_DIV_SELECT_M 0x00000002 +#define CYGHWR_HAL_VYBRID_ANADIG_PLL1_CTRL_DIV_SELECT_S 1 + +// PLL1_NUM Bit Fields +#define CYGHWR_HAL_VYBRID_ANADIG_PLL1_NUM_M 0x7FFFFFFF + +// PLL1_DENOM Bit Fields +#define CYGHWR_HAL_VYBRID_ANADIG_PLL1_DENOM_M 0x7FFFFFFF + +// PLL2_PFD Bit Fields +#define CYGHWR_HAL_VYBRID_ANADIG_PLL1_PFD_PFD4_CLKGATE_M 0x80000000 +#define CYGHWR_HAL_VYBRID_ANADIG_PLL1_PFD_PFD4_CLKGATE_S 31 +#define CYGHWR_HAL_VYBRID_ANADIG_PLL1_PFD_PFD4_STABLE_M 0x40000000 +#define CYGHWR_HAL_VYBRID_ANADIG_PLL1_PFD_PFD4_STABLE_S 30 +#define CYGHWR_HAL_VYBRID_ANADIG_PLL1_PFD_PFD4_FRAC_M 0x3F000000 +#define CYGHWR_HAL_VYBRID_ANADIG_PLL1_PFD_PFD4_FRAC_S 24 +#define CYGHWR_HAL_VYBRID_ANADIG_PLL1_PFD_PFD3_CLKGATE_M 0x00800000 +#define CYGHWR_HAL_VYBRID_ANADIG_PLL1_PFD_PFD3_CLKGATE_S 23 +#define CYGHWR_HAL_VYBRID_ANADIG_PLL1_PFD_PFD3_STABLE_M 0x00400000 +#define CYGHWR_HAL_VYBRID_ANADIG_PLL1_PFD_PFD3_STABLE_S 22 +#define CYGHWR_HAL_VYBRID_ANADIG_PLL1_PFD_PFD3_FRAC_M 0x003F0000 +#define CYGHWR_HAL_VYBRID_ANADIG_PLL1_PFD_PFD3_FRAC_S 16 +#define CYGHWR_HAL_VYBRID_ANADIG_PLL1_PFD_PFD2_CLKGATE_M 0x00008000 +#define CYGHWR_HAL_VYBRID_ANADIG_PLL1_PFD_PFD2_CLKGATE_S 15 +#define CYGHWR_HAL_VYBRID_ANADIG_PLL1_PFD_PFD2_STABLE_M 0x00004000 +#define CYGHWR_HAL_VYBRID_ANADIG_PLL1_PFD_PFD2_STABLE_S 14 +#define CYGHWR_HAL_VYBRID_ANADIG_PLL1_PFD_PFD2_FRAC_M 0x00003F00 +#define CYGHWR_HAL_VYBRID_ANADIG_PLL1_PFD_PFD2_FRAC_S 8 +#define CYGHWR_HAL_VYBRID_ANADIG_PLL1_PFD_PFD1_CLKGATE_M 0x00000080 +#define CYGHWR_HAL_VYBRID_ANADIG_PLL1_PFD_PFD1_CLKGATE_S 7 +#define CYGHWR_HAL_VYBRID_ANADIG_PLL1_PFD_PFD1_STABLE_M 0x00000040 +#define CYGHWR_HAL_VYBRID_ANADIG_PLL1_PFD_PFD1_STABLE_S 6 +#define CYGHWR_HAL_VYBRID_ANADIG_PLL1_PFD_PFD1_FRAC_M 0x0000003F +#define CYGHWR_HAL_VYBRID_ANADIG_PLL1_PFD_PFD1_FRAC_S 0 + +// PLL2_CTRL Bit Fields +#define CYGHWR_HAL_VYBRID_ANADIG_PLL2_CTRL_LOCK_M 0x80000000 +#define CYGHWR_HAL_VYBRID_ANADIG_PLL2_CTRL_LOCK_S 31 +#define CYGHWR_HAL_VYBRID_ANADIG_PLL2_CTRL_PFD_OFFSET_EN_M 0x00040000 +#define CYGHWR_HAL_VYBRID_ANADIG_PLL2_CTRL_PFD_OFFSET_EN_S 18 +#define CYGHWR_HAL_VYBRID_ANADIG_PLL2_CTRL_DITHER_ENABLE_M 0x00020000 +#define CYGHWR_HAL_VYBRID_ANADIG_PLL2_CTRL_DITHER_ENABLE_S 17 +#define CYGHWR_HAL_VYBRID_ANADIG_PLL2_CTRL_BYPASS_M 0x00010000 +#define CYGHWR_HAL_VYBRID_ANADIG_PLL2_CTRL_BYPASS_S 16 +#define CYGHWR_HAL_VYBRID_ANADIG_PLL2_CTRL_BYPASS_CLK_SRC_M 0x00004000 +#define CYGHWR_HAL_VYBRID_ANADIG_PLL2_CTRL_BYPASS_CLK_SRC_S 14 +#define CYGHWR_HAL_VYBRID_ANADIG_PLL2_CTRL_ENABLE_M 0x00002000 +#define CYGHWR_HAL_VYBRID_ANADIG_PLL2_CTRL_ENABLE_S 13 +#define CYGHWR_HAL_VYBRID_ANADIG_PLL2_CTRL_POWERDOWN_M 0x00001000 +#define CYGHWR_HAL_VYBRID_ANADIG_PLL2_CTRL_POWERDOWN_S 12 +#define CYGHWR_HAL_VYBRID_ANADIG_PLL2_CTRL_DIV_SELECT_M 0x00000002 +#define CYGHWR_HAL_VYBRID_ANADIG_PLL2_CTRL_DIV_SELECT_S 1 + +// PLL2_NUM Bit Fields +#define CYGHWR_HAL_VYBRID_ANADIG_PLL2_NUM_M 0x7FFFFFFF + +// PLL2_DENOM Bit Fields +#define CYGHWR_HAL_VYBRID_ANADIG_PLL2_DENOM_M 0x7FFFFFFF + +// PLL2_PFD Bit Fields +#define CYGHWR_HAL_VYBRID_ANADIG_PLL2_PFD_PFD4_CLKGATE_M 0x80000000 +#define CYGHWR_HAL_VYBRID_ANADIG_PLL2_PFD_PFD4_CLKGATE_S 31 +#define CYGHWR_HAL_VYBRID_ANADIG_PLL2_PFD_PFD4_STABLE_M 0x40000000 +#define CYGHWR_HAL_VYBRID_ANADIG_PLL2_PFD_PFD4_STABLE_S 30 +#define CYGHWR_HAL_VYBRID_ANADIG_PLL2_PFD_PFD4_FRAC_M 0x3F000000 +#define CYGHWR_HAL_VYBRID_ANADIG_PLL2_PFD_PFD4_FRAC_S 24 +#define CYGHWR_HAL_VYBRID_ANADIG_PLL2_PFD_PFD3_CLKGATE_M 0x00800000 +#define CYGHWR_HAL_VYBRID_ANADIG_PLL2_PFD_PFD3_CLKGATE_S 23 +#define CYGHWR_HAL_VYBRID_ANADIG_PLL2_PFD_PFD3_STABLE_M 0x00400000 +#define CYGHWR_HAL_VYBRID_ANADIG_PLL2_PFD_PFD3_STABLE_S 22 +#define CYGHWR_HAL_VYBRID_ANADIG_PLL2_PFD_PFD3_FRAC_M 0x003F0000 +#define CYGHWR_HAL_VYBRID_ANADIG_PLL2_PFD_PFD3_FRAC_S 16 +#define CYGHWR_HAL_VYBRID_ANADIG_PLL2_PFD_PFD2_CLKGATE_M 0x00008000 +#define CYGHWR_HAL_VYBRID_ANADIG_PLL2_PFD_PFD2_CLKGATE_S 15 +#define CYGHWR_HAL_VYBRID_ANADIG_PLL2_PFD_PFD2_STABLE_M 0x00004000 +#define CYGHWR_HAL_VYBRID_ANADIG_PLL2_PFD_PFD2_STABLE_S 14 +#define CYGHWR_HAL_VYBRID_ANADIG_PLL2_PFD_PFD2_FRAC_M 0x00003F00 +#define CYGHWR_HAL_VYBRID_ANADIG_PLL2_PFD_PFD2_FRAC_S 8 +#define CYGHWR_HAL_VYBRID_ANADIG_PLL2_PFD_PFD1_CLKGATE_M 0x00000080 +#define CYGHWR_HAL_VYBRID_ANADIG_PLL2_PFD_PFD1_CLKGATE_S 7 +#define CYGHWR_HAL_VYBRID_ANADIG_PLL2_PFD_PFD1_STABLE_M 0x00000040 +#define CYGHWR_HAL_VYBRID_ANADIG_PLL2_PFD_PFD1_STABLE_S 6 +#define CYGHWR_HAL_VYBRID_ANADIG_PLL2_PFD_PFD1_FRAC_M 0x0000003F +#define CYGHWR_HAL_VYBRID_ANADIG_PLL2_PFD_PFD1_FRAC_S 0 + +// PLL3_CTRL Bit Fields +#define CYGHWR_HAL_VYBRID_ANADIG_PLL3_CTRL_LOCK_M 0x80000000 +#define CYGHWR_HAL_VYBRID_ANADIG_PLL3_CTRL_LOCK_S 31 +#define CYGHWR_HAL_VYBRID_ANADIG_PLL3_CTRL_BYPASS_M 0x00010000 +#define CYGHWR_HAL_VYBRID_ANADIG_PLL3_CTRL_BYPASS_S 16 +#define CYGHWR_HAL_VYBRID_ANADIG_PLL3_CTRL_BYPASS_CLK_SRC_M 0x00004000 +#define CYGHWR_HAL_VYBRID_ANADIG_PLL3_CTRL_BYPASS_CLK_SRC_S 14 +#define CYGHWR_HAL_VYBRID_ANADIG_PLL3_CTRL_ENABLE_M 0x00002000 +#define CYGHWR_HAL_VYBRID_ANADIG_PLL3_CTRL_ENABLE_S 13 +#define CYGHWR_HAL_VYBRID_ANADIG_PLL3_CTRL_POWER_M 0x00001000 +#define CYGHWR_HAL_VYBRID_ANADIG_PLL3_CTRL_POWER_S 12 +#define CYGHWR_HAL_VYBRID_ANADIG_PLL3_CTRL_EN_USB_CLKS_M 0x00000040 +#define CYGHWR_HAL_VYBRID_ANADIG_PLL3_CTRL_EN_USB_CLKS_S 6 +#define CYGHWR_HAL_VYBRID_ANADIG_PLL3_CTRL_DIV_SELECT_M 0x00000002 +#define CYGHWR_HAL_VYBRID_ANADIG_PLL3_CTRL_DIV_SELECT_S 1 + +// PLL3_PFD Bit Fields +#define CYGHWR_HAL_VYBRID_ANADIG_PLL3_PFD_PFD4_CLKGATE_M 0x80000000 +#define CYGHWR_HAL_VYBRID_ANADIG_PLL3_PFD_PFD4_CLKGATE_S 31 +#define CYGHWR_HAL_VYBRID_ANADIG_PLL3_PFD_PFD4_STABLE_M 0x40000000 +#define CYGHWR_HAL_VYBRID_ANADIG_PLL3_PFD_PFD4_STABLE_S 30 +#define CYGHWR_HAL_VYBRID_ANADIG_PLL3_PFD_PFD4_FRAC_M 0x3F000000 +#define CYGHWR_HAL_VYBRID_ANADIG_PLL3_PFD_PFD4_FRAC_S 24 +#define CYGHWR_HAL_VYBRID_ANADIG_PLL3_PFD_PFD3_CLKGATE_M 0x00800000 +#define CYGHWR_HAL_VYBRID_ANADIG_PLL3_PFD_PFD3_CLKGATE_S 23 +#define CYGHWR_HAL_VYBRID_ANADIG_PLL3_PFD_PFD3_STABLE_M 0x00400000 +#define CYGHWR_HAL_VYBRID_ANADIG_PLL3_PFD_PFD3_STABLE_S 22 +#define CYGHWR_HAL_VYBRID_ANADIG_PLL3_PFD_PFD3_FRAC_M 0x003F0000 +#define CYGHWR_HAL_VYBRID_ANADIG_PLL3_PFD_PFD3_FRAC_S 16 +#define CYGHWR_HAL_VYBRID_ANADIG_PLL3_PFD_PFD2_CLKGATE_M 0x00008000 +#define CYGHWR_HAL_VYBRID_ANADIG_PLL3_PFD_PFD2_CLKGATE_S 15 +#define CYGHWR_HAL_VYBRID_ANADIG_PLL3_PFD_PFD2_STABLE_M 0x00004000 +#define CYGHWR_HAL_VYBRID_ANADIG_PLL3_PFD_PFD2_STABLE_S 14 +#define CYGHWR_HAL_VYBRID_ANADIG_PLL3_PFD_PFD2_FRAC_M 0x00003F00 +#define CYGHWR_HAL_VYBRID_ANADIG_PLL3_PFD_PFD2_FRAC_S 8 +#define CYGHWR_HAL_VYBRID_ANADIG_PLL3_PFD_PFD1_CLKGATE_M 0x00000080 +#define CYGHWR_HAL_VYBRID_ANADIG_PLL3_PFD_PFD1_CLKGATE_S 7 +#define CYGHWR_HAL_VYBRID_ANADIG_PLL3_PFD_PFD1_STABLE_M 0x00000040 +#define CYGHWR_HAL_VYBRID_ANADIG_PLL3_PFD_PFD1_STABLE_S 6 +#define CYGHWR_HAL_VYBRID_ANADIG_PLL3_PFD_PFD1_FRAC_M 0x0000003F +#define CYGHWR_HAL_VYBRID_ANADIG_PLL3_PFD_PFD1_FRAC_S 0 + +//--------------------------------------------------------------------------- +// Clock distribution +// The following encodes the control register and clock bit number +// into clock configuration descriptor (CLKCD). +#define CYGHWR_HAL_VYBRID_CCM_CCGR(__reg,__cg) (((__reg) & 0x0F) + ((((__cg - (__reg * 16)) * 2) << 8) & 0x1F00)) + +// Macros to extract encoded values. +#define CYGHWR_HAL_VYBRID_CCM_CCGR_REG(__val) (((__val) & 0x0F)) +#define CYGHWR_HAL_VYBRID_CCM_CCGR_BIT(__val) (((__val) >> 8) & 0x1F) + +// Functions and macros to enable/disable clocks. +#define CYGHWR_HAL_CCGR_NONE (0xFFFFFFFF) +__externC void hal_clock_enable(cyg_uint32 ccgr); +__externC void hal_clock_disable(cyg_uint32 ccgr); + +#define CYGHWR_HAL_CLOCK_ENABLE(__ccgr) hal_clock_enable(__ccgr) +#define CYGHWR_HAL_CLOCK_DISABLE(__ccgr) hal_clock_disable(__ccgr) +#include <cyg/hal/var_io_clkgat.h> + + +//--------------------------------------------------------------------------- +// PORT - Peripheral register structure + +typedef volatile struct cyghwr_hal_vybrid_port_s { + cyg_uint32 pcr[32]; // Pin Control Register n, array + cyg_uint8 reserved0[24]; + cyg_uint32 isfr; // Interrupt Status Flag Register + cyg_uint8 reserved1[28]; + cyg_uint32 dfer; // Digital Filter Enable Register + cyg_uint32 dfcr; // Digital Filter Clock Register + cyg_uint32 dfwr; // Digital Filter Width Register +} cyghwr_hal_vybrid_port_t; + + +// PORT - Peripheral instance base addresses +#define CYGHWR_HAL_VYBRID_PORTA_P ((cyghwr_hal_vybrid_port_t *)0x40049000) +#define CYGHWR_HAL_VYBRID_PORTB_P ((cyghwr_hal_vybrid_port_t *)0x4004A000) +#define CYGHWR_HAL_VYBRID_PORTC_P ((cyghwr_hal_vybrid_port_t *)0x4004B000) +#define CYGHWR_HAL_VYBRID_PORTD_P ((cyghwr_hal_vybrid_port_t *)0x4004C000) +#define CYGHWR_HAL_VYBRID_PORTE_P ((cyghwr_hal_vybrid_port_t *)0x4004D000) +#define CYGHWR_HAL_VYBRID_PORTF_P ((cyghwr_hal_vybrid_port_t *)0x4004E000) + +enum { + CYGHWR_HAL_VYBRID_PORTA, CYGHWR_HAL_VYBRID_PORTB, + CYGHWR_HAL_VYBRID_PORTC, CYGHWR_HAL_VYBRID_PORTD, + CYGHWR_HAL_VYBRID_PORTE, CYGHWR_HAL_VYBRID_PORTF +}; + +#define CYGHWR_HAL_VYBRID_PORT(__port, __reg) \ + (CYGHWR_HAL_VYBRID_PORT##__port##_P)->__reg + +// PCR Bit Fields TODO To remove +#define CYGHWR_HAL_VYBRID_PORT_PCR_PS_M 0x1 +#define CYGHWR_HAL_VYBRID_PORT_PCR_PS_S 0 +#define CYGHWR_HAL_VYBRID_PORT_PCR_PE_M 0x2 +#define CYGHWR_HAL_VYBRID_PORT_PCR_PE_S 1 +#define CYGHWR_HAL_VYBRID_PORT_PCR_SRE_M 0x4 +#define CYGHWR_HAL_VYBRID_PORT_PCR_SRE_S 2 +#define CYGHWR_HAL_VYBRID_PORT_PCR_PFE_M 0x10 +#define CYGHWR_HAL_VYBRID_PORT_PCR_PFE_S 4 +#define CYGHWR_HAL_VYBRID_PORT_PCR_ODE_M 0x20 +#define CYGHWR_HAL_VYBRID_PORT_PCR_ODE_S 5 +#define CYGHWR_HAL_VYBRID_PORT_PCR_DSE_M 0x40 +#define CYGHWR_HAL_VYBRID_PORT_PCR_DSE_S 6 +#define CYGHWR_HAL_VYBRID_PORT_PCR_MUX_M 0x700 +#define CYGHWR_HAL_VYBRID_PORT_PCR_MUX_S 8 // VYBRID +#define CYGHWR_HAL_VYBRID_PORT_PCR_MUX(__val) \ + VALUE_(CYGHWR_HAL_VYBRID_PORT_PCR_MUX_S, __val) +#define CYGHWR_HAL_VYBRID_PORT_PCR_LK_M 0x8000 +#define CYGHWR_HAL_VYBRID_PORT_PCR_LK_S 15 +#define CYGHWR_HAL_VYBRID_PORT_PCR_IRQC_M 0xF0000 +#define CYGHWR_HAL_VYBRID_PORT_PCR_IRQC_S 16 +#define CYGHWR_HAL_VYBRID_PORT_PCR_IRQC(__val) \ + VALUE_(CYGHWR_HAL_VYBRID_PORT_PCR_IRQC_S, __val) +#define CYGHWR_HAL_VYBRID_PORT_PCR_ISF_M 0x1000000 +#define CYGHWR_HAL_VYBRID_PORT_PCR_ISF_S 24 + +#define CYGHWR_HAL_VYBRID_PORT_PCR_MUX_ANALOG 0 +#define CYGHWR_HAL_VYBRID_PORT_PCR_MUX_DIS 0 +#define CYGHWR_HAL_VYBRID_PORT_PCR_MUX_GPIO 1 + +#define CYGHWR_HAL_VYBRID_PORT_PCR_ISFR_CLEAR(__port, __pin) \ + CYGHWR_HAL_VYBRID_PORT(__port, pcr[__pin]) |= BIT_(24) + +#define CYGHWR_HAL_VYBRID_PORT_ISFR_CLEAR(__port, __pin) \ + CYGHWR_HAL_VYBRID_PORT(__port, isfr) |= BIT_(__pin) + + + +#define CYGHWR_HAL_VYBRID_PIN_CFG(__port, __bit, __mux, __irqc, __cnf) \ + ((CYGHWR_HAL_VYBRID_PORT##__port << 20) | ((__bit) << 27) \ + | CYGHWR_HAL_VYBRID_PORT_PCR_IRQC(__irqc) \ + | CYGHWR_HAL_VYBRID_PORT_PCR_MUX(__mux) | (__cnf)) + +#define CYGHWR_HAL_VYBRID_PIN(__port, __bit, __mux, __cnf) \ + CYGHWR_HAL_VYBRID_PIN_CFG(__port, __bit, __mux, 0, __cnf) + +#define CYGHWR_HAL_VYBRID_PIN_PORT(__pin) (((__pin) >> 20) & 0x7) +#define CYGHWR_HAL_VYBRID_PIN_BIT(__pin) (((__pin) >> 27 ) & 0x1f) +#define CYGHWR_HAL_VYBRID_PIN_FUNC(__pin) ((__pin) & 0x010f8777) +#define CYGHWR_HAL_VYBRID_PIN_NONE (0xffffffff) + +// GPCLR Bit Fields +#define CYGHWR_HAL_VYBRID_PORT_GPCLR_GPWD_M 0xFFFF +#define CYGHWR_HAL_VYBRID_PORT_GPCLR_GPWD_S 0 +#define CYGHWR_HAL_VYBRID_PORT_GPCLR_GPWD(__val) \ + VALUE_(CYGHWR_HAL_VYBRID_PORT_GPCLR_GPWD_S, __val) +#define CYGHWR_HAL_VYBRID_PORT_GPCLR_GPWE_M 0xFFFF0000 +#define CYGHWR_HAL_VYBRID_PORT_GPCLR_GPWE_S 16 +#define CYGHWR_HAL_VYBRID_PORT_GPCLR_GPWE(__val) \ + VALUE_(CYGHWR_HAL_VYBRID_PORT_GPCLR_GPWE_S, __val) +// GPCHR Bit Fields +#define CYGHWR_HAL_VYBRID_PORT_GPCHR_GPWD_M 0xFFFF +#define CYGHWR_HAL_VYBRID_PORT_GPCHR_GPWD_S 0 +#define CYGHWR_HAL_VYBRID_PORT_GPCHR_GPWD(__val) \ + VALUE_(CYGHWR_HAL_VYBRID_PORT_GPCHR_GPWD_S, __val) +#define CYGHWR_HAL_VYBRID_PORT_GPCHR_GPWE_M 0xFFFF0000 +#define CYGHWR_HAL_VYBRID_PORT_GPCHR_GPWE_S 16 +#define CYGHWR_HAL_VYBRID_PORT_GPCHR_GPWE(__val) \ + VALUE_(CYGHWR_HAL_VYBRID_PORT_GPCHR_GPWE_S, __val) +// ISFR Bit Fields +#define CYGHWR_HAL_VYBRID_PORT_ISFR_ISF_M 0xFFFFFFFF +#define CYGHWR_HAL_VYBRID_PORT_ISFR_ISF_S 0 +#define CYGHWR_HAL_VYBRID_PORT_ISFR_ISF(__val) \ + VALUE_(CYGHWR_HAL_VYBRID_PORT_ISFR_ISF_S, __val) +// DFER Bit Fields +#define CYGHWR_HAL_VYBRID_PORT_DFER_DFE_M 0xFFFFFFFF +#define CYGHWR_HAL_VYBRID_PORT_DFER_DFE_S 0 +#define CYGHWR_HAL_VYBRID_PORT_DFER_DFE(__val) \ + VALUE_(CYGHWR_HAL_VYBRID_PORT_DFER_DFE_S, __val) +// DFCR Bit Fields +#define CYGHWR_HAL_VYBRID_PORT_DFCR_CS_M 0x1 +#define CYGHWR_HAL_VYBRID_PORT_DFCR_CS_S 0 +// DFWR Bit Fields +#define CYGHWR_HAL_VYBRID_PORT_DFWR_FILT_M 0x1F +#define CYGHWR_HAL_VYBRID_PORT_DFWR_FILT_S 0 +#define CYGHWR_HAL_VYBRID_PORT_DFWR_FILT(__val) \ + VALUE_(CYGHWR_HAL_VYBRID_PORT_DFWR_FILT_S, __val) + +#ifndef __ASSEMBLER__ + +// Pin configuration related functions +__externC void hal_set_pin_function(cyg_uint32 pin); +__externC void hal_dump_pin_function(cyg_uint32 pin); +__externC void hal_dump_pin_setting(cyg_uint32 pin); + +#endif + +#define HAL_SET_PINS(_pin_array) \ +CYG_MACRO_START \ + const cyg_uint32 *_pin_p; \ + for(_pin_p = &_pin_array[0]; \ + _pin_p < &_pin_array[0] + sizeof(_pin_array)/sizeof(_pin_array[0]); \ + hal_set_pin_function(*_pin_p++)); \ +CYG_MACRO_END + +//--------------------------------------------------------------------------- +// PMC Power Management Controller + +typedef volatile struct cyghwr_hal_vybrid_pmc_s { + cyg_uint8 lvdsc1; // Low Voltage Detect Status and Control 1 Register + cyg_uint8 lvdsc2; // Low Voltage Detect Status and Control 2 Register + cyg_uint8 regsc; // Regulator Status and Control Register +} cyghwr_hal_vybrid_pmc_t; + +// PMC base address +#define CYGHWR_HAL_VYBRID_PMC_P ((cyghwr_hal_vybrid_pmc_t *)0x4007D000) + +// LVDSC1 Bit Fields +#define CYGHWR_HAL_VYBRID_PMC_LVDSC1_LVDV_M 0x3 +#define CYGHWR_HAL_VYBRID_PMC_LVDSC1_LVDV(__val) \ + ((__val) & CYGHWR_HAL_VYBRID_PMC_LVDSC1_LVDV_M) +#define CYGHWR_HAL_VYBRID_PMC_LVDSC1_LVDRE_M 0x10 +#define CYGHWR_HAL_VYBRID_PMC_LVDSC1_LVDRE_S 4 +#define CYGHWR_HAL_VYBRID_PMC_LVDSC1_LVDIE_M 0x20 +#define CYGHWR_HAL_VYBRID_PMC_LVDSC1_LVDIE_S 5 +#define CYGHWR_HAL_VYBRID_PMC_LVDSC1_LVDACK_M 0x40 +#define CYGHWR_HAL_VYBRID_PMC_LVDSC1_LVDACK_S 6 +#define CYGHWR_HAL_VYBRID_PMC_LVDSC1_LVDF_M 0x80 +#define CYGHWR_HAL_VYBRID_PMC_LVDSC1_LVDF_S 7 +// LVDSC2 Bit Fields +#define CYGHWR_HAL_VYBRID_PMC_LVDSC2_LVWV_M 0x3 +#define CYGHWR_HAL_VYBRID_PMC_LVDSC2_LVWV(__val) \ + ((__val) & CYGHWR_HAL_VYBRID_PMC_LVDSC2_LVWV_M) +#define CYGHWR_HAL_VYBRID_PMC_LVDSC2_LVWIE_M 0x20 +#define CYGHWR_HAL_VYBRID_PMC_LVDSC2_LVWIE_S 5 +#define CYGHWR_HAL_VYBRID_PMC_LVDSC2_LVWACK_M 0x40 +#define CYGHWR_HAL_VYBRID_PMC_LVDSC2_LVWACK_S 6 +#define CYGHWR_HAL_VYBRID_PMC_LVDSC2_LVWF_M 0x80 +#define CYGHWR_HAL_VYBRID_PMC_LVDSC2_LVWF_S 7 +// REGSC Bit Fields +#define CYGHWR_HAL_VYBRID_PMC_REGSC_BGBE_M 0x1 +#define CYGHWR_HAL_VYBRID_PMC_REGSC_BGBE_S 0 +#define CYGHWR_HAL_VYBRID_PMC_REGSC_REGONS_M 0x4 +#define CYGHWR_HAL_VYBRID_PMC_REGSC_REGONS_S 2 +#define CYGHWR_HAL_VYBRID_PMC_REGSC_ACKISO_M 0x8 +#define CYGHWR_HAL_VYBRID_PMC_REGSC_ACKISO_S 3 +#define CYGHWR_HAL_VYBRID_PMC_REGSC_BGEN_M 0x10 +#define CYGHWR_HAL_VYBRID_PMC_REGSC_BGEN_S 4 + + +//--------------------------------------------------------------------------- +// FlexBus +#ifdef CYGPKG_HAL_CORTEXM_VYBRID_FLEXBUS +# include <cyg/hal/var_io_flexbus.h> +#endif + +//---------------------------------------------------------------------------- +// DDRMC - SDRAM controller +#ifdef CYGPKG_HAL_CORTEXM_VYBRID_DDRMC +# include <cyg/hal/var_io_ddrmc.h> +#endif + +//--------------------------------------------------------------------------- +// GPIO +#include <cyg/hal/var_io_gpio.h> + +//============================================================================= +// DEVS: +// Following macros may also be, and usually are borrowed by some device drivers. +//----------------------------------------------------------------------------- +#include <cyg/hal/var_io_devs.h> + +// End Peripherals + +// Some miscelaneous function prototypes +// Clock related functions are in vybrid_clocking.c +__externC void hal_start_clocks(void); +__externC void hal_update_clock_var(void); + +//----------------------------------------------------------------------------- +// end of var_io.h + +#endif // CYGONCE_HAL_VAR_IO_H + diff --git a/ecos/packages/hal/cortexm/vybrid/var/current/include/var_io_clkgat.h b/ecos/packages/hal/cortexm/vybrid/var/current/include/var_io_clkgat.h new file mode 100644 index 0000000..bd6348a --- /dev/null +++ b/ecos/packages/hal/cortexm/vybrid/var/current/include/var_io_clkgat.h @@ -0,0 +1,67 @@ +#ifndef CYGONCE_HAL_VAR_IOCLKGAT_H +#define CYGONCE_HAL_VAR_IOCLKGAT_H +//=========================================================================== +// +// var_io_clkgat.h +// +// Vybrid clock gating +// +//=========================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2013 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//=========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): Antmicro Ltd <contact@antmicro.com> +// Based on: {...}/hal/packages/cortexm/kinetis/var/current/include/var_io_clkgat.h +// Date: 2014-03-28 +// Purpose: Vybrid clock distribution macros +// Description: +// Usage: This file is included by <cyg/hal/var_io.h> +// +//####DESCRIPTIONEND#### +// +//=========================================================================== + +//--------------------------------------------------------------------------- +// Clock distribution + +// Clock gating definitions +#define CYGHWR_HAL_VYBRID_CCM_CCGR_UART0 CYGHWR_HAL_VYBRID_CCM_CCGR(0, 7) +#define CYGHWR_HAL_VYBRID_CCM_CCGR_UART1 CYGHWR_HAL_VYBRID_CCM_CCGR(0, 8) +#define CYGHWR_HAL_VYBRID_CCM_CCGR_UART2 CYGHWR_HAL_VYBRID_CCM_CCGR(0, 9) +#define CYGHWR_HAL_VYBRID_CCM_CCGR_UART3 CYGHWR_HAL_VYBRID_CCM_CCGR(0, 10) +#define CYGHWR_HAL_VYBRID_CCM_CCGR_UART4 CYGHWR_HAL_VYBRID_CCM_CCGR(6, 105) +#define CYGHWR_HAL_VYBRID_CCM_CCGR_UART5 CYGHWR_HAL_VYBRID_CCM_CCGR(6, 106) + + +#endif // CYGONCE_HAL_VAR_IOCLKGAT_H diff --git a/ecos/packages/hal/cortexm/vybrid/var/current/include/var_io_devs.h b/ecos/packages/hal/cortexm/vybrid/var/current/include/var_io_devs.h new file mode 100644 index 0000000..64aefcf --- /dev/null +++ b/ecos/packages/hal/cortexm/vybrid/var/current/include/var_io_devs.h @@ -0,0 +1,173 @@ +#ifndef CYGONCE_HAL_VAR_IO_DEVS_H +#define CYGONCE_HAL_VAR_IO_DEVS_H +//=========================================================================== +// +// var_io_devs.h +// +// Variant specific registers +// +//=========================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2011, 2013 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//=========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): Antmicro Ltd <contact@antmicro.com> +// Based on: {...}/hal/packages/cortexm/kinetis/var/current/include/var_io_devs.h +// Date: 2014-03-28 +// Purpose: Vybrid variant IO provided to various device drivers +// Description: +// Usage: #include <cyg/hal/var_io.h> //var_io.h includes this file +// +//####DESCRIPTIONEND#### +// +//=========================================================================== + + +//============================================================================= +// DEVS: +// Following macros may be, and usually are borrowed by some device drivers. + +// Peripheral clock [Hz]; +__externC cyg_uint32 hal_get_peripheral_clock(void); + +//----------------------------------------------------------------------------- +// Freescale UART +// Borrow some HAL resources to Freescale UART driver +// UART macros are used by both: +// src/hal_diag.c +// devs/serial/<version>/src/ser_freescale_uart.c + +#define CYGADDR_IO_SERIAL_FREESCALE_UART0_BASE 0x40027000 +#define CYGADDR_IO_SERIAL_FREESCALE_UART1_BASE 0x40028000 +#define CYGADDR_IO_SERIAL_FREESCALE_UART2_BASE 0x40029000 +#define CYGADDR_IO_SERIAL_FREESCALE_UART3_BASE 0x4002A000 +#define CYGADDR_IO_SERIAL_FREESCALE_UART4_BASE 0x400A9000 +#define CYGADDR_IO_SERIAL_FREESCALE_UART5_BASE 0x400AA000 + +// UART Clock gating +#define CYGHWR_IO_FREESCALE_UART0_CLOCK CYGHWR_HAL_VYBRID_CCM_CCGR_UART0 +#define CYGHWR_IO_FREESCALE_UART1_CLOCK CYGHWR_HAL_VYBRID_CCM_CCGR_UART1 +#define CYGHWR_IO_FREESCALE_UART2_CLOCK CYGHWR_HAL_VYBRID_CCM_CCGR_UART2 +#define CYGHWR_IO_FREESCALE_UART3_CLOCK CYGHWR_HAL_VYBRID_CCM_CCGR_UART3 +#define CYGHWR_IO_FREESCALE_UART4_CLOCK CYGHWR_HAL_VYBRID_CCM_CCGR_UART4 +#define CYGHWR_IO_FREESCALE_UART5_CLOCK CYGHWR_HAL_VYBRID_CCM_CCGR_UART5 + + +// UART PIN configuration +// Note: May be overriden by plf_io.h + +#define CYGHWR_HAL_VYBRID_PORT_PIN_NONE CYGHWR_HAL_VYBRID_PIN_NONE + +#ifndef CYGHWR_IO_FREESCALE_UART0_PIN_RX +# define CYGHWR_IO_FREESCALE_UART0_PIN_RX CYGHWR_HAL_VYBRID_PORT_PIN_NONE +# define CYGHWR_IO_FREESCALE_UART0_PIN_TX CYGHWR_HAL_VYBRID_PORT_PIN_NONE +# define CYGHWR_IO_FREESCALE_UART0_PIN_RTS CYGHWR_HAL_VYBRID_PORT_PIN_NONE +# define CYGHWR_IO_FREESCALE_UART0_PIN_CTS CYGHWR_HAL_VYBRID_PORT_PIN_NONE +#endif + +#ifndef CYGHWR_IO_FREESCALE_UART1_PIN_RX +# define CYGHWR_IO_FREESCALE_UART1_PIN_RX CYGHWR_HAL_VYBRID_PORT_PIN_NONE +# define CYGHWR_IO_FREESCALE_UART1_PIN_TX CYGHWR_HAL_VYBRID_PORT_PIN_NONE +# define CYGHWR_IO_FREESCALE_UART1_PIN_RTS CYGHWR_HAL_VYBRID_PORT_PIN_NONE +# define CYGHWR_IO_FREESCALE_UART1_PIN_CTS CYGHWR_HAL_VYBRID_PORT_PIN_NONE +#endif + +#ifndef CYGHWR_IO_FREESCALE_UART2_PIN_RX +# define CYGHWR_IO_FREESCALE_UART2_PIN_RX CYGHWR_HAL_VYBRID_PORT_PIN_NONE +# define CYGHWR_IO_FREESCALE_UART2_PIN_TX CYGHWR_HAL_VYBRID_PORT_PIN_NONE +# define CYGHWR_IO_FREESCALE_UART2_PIN_RTS CYGHWR_HAL_VYBRID_PORT_PIN_NONE +# define CYGHWR_IO_FREESCALE_UART2_PIN_CTS CYGHWR_HAL_VYBRID_PORT_PIN_NONE +#endif + +#ifndef CYGHWR_IO_FREESCALE_UART3_PIN_RX +# define CYGHWR_IO_FREESCALE_UART3_PIN_RX CYGHWR_HAL_VYBRID_PORT_PIN_NONE +# define CYGHWR_IO_FREESCALE_UART3_PIN_TX CYGHWR_HAL_VYBRID_PORT_PIN_NONE +# define CYGHWR_IO_FREESCALE_UART3_PIN_RTS CYGHWR_HAL_VYBRID_PORT_PIN_NONE +# define CYGHWR_IO_FREESCALE_UART3_PIN_CTS CYGHWR_HAL_VYBRID_PORT_PIN_NONE +#endif + +#ifndef CYGHWR_IO_FREESCALE_UART4_PIN_RX +# define CYGHWR_IO_FREESCALE_UART4_PIN_RX CYGHWR_HAL_VYBRID_PORT_PIN_NONE +# define CYGHWR_IO_FREESCALE_UART4_PIN_TX CYGHWR_HAL_VYBRID_PORT_PIN_NONE +# define CYGHWR_IO_FREESCALE_UART4_PIN_RTS CYGHWR_HAL_VYBRID_PORT_PIN_NONE +# define CYGHWR_IO_FREESCALE_UART4_PIN_CTS CYGHWR_HAL_VYBRID_PORT_PIN_NONE +#endif + +#ifndef CYGHWR_IO_FREESCALE_UART5_PIN_RX +# define CYGHWR_IO_FREESCALE_UART5_PIN_RX CYGHWR_HAL_VYBRID_PORT_PIN_NONE +# define CYGHWR_IO_FREESCALE_UART5_PIN_TX CYGHWR_HAL_VYBRID_PORT_PIN_NONE +# define CYGHWR_IO_FREESCALE_UART5_PIN_RTS CYGHWR_HAL_VYBRID_PORT_PIN_NONE +# define CYGHWR_IO_FREESCALE_UART5_PIN_CTS CYGHWR_HAL_VYBRID_PORT_PIN_NONE +#endif + +// Lend some HAL dependent functions to the UART serial device driver + +#ifndef __ASSEMBLER__ + +# define CYGHWR_IO_FREESCALE_UART_BAUD_SET(__uart_p, _baud_) \ + hal_freescale_uart_setbaud(__uart_p, _baud_) + +# define CYGHWR_IO_FREESCALE_UART_PIN(__pin) \ + hal_set_pin_function(__pin) + + +// Set baud rate +__externC void hal_freescale_uart_setbaud( CYG_ADDRESS uart, cyg_uint32 baud ); + +#endif +//---------------------------------------------------------------------------- +// eDMA +// Lend some eDMA macros to device driver that use DMA + +// Base address +#define CYGHWR_HAL_FREESCALE_EDMA0_P ((cyghwr_hal_freescale_edma_t *)0x40008000) +// DMAMUX base addresses +#define CYGHWR_HAL_FREESCALE_DMAMUX0_P ((cyghwr_hal_freescale_dmamux_t *) 0x40021000) +#define CYGHWR_HAL_FREESCALE_DMAMUX1_P ((cyghwr_hal_freescale_dmamux_t *) 0x40022000) + + +#define CYGHWR_IO_FREESCALE_EDMA0_P CYGHWR_HAL_FREESCALE_EDMA0_P +#define CYGHWR_IO_FREESCALE_DMAMUX0_P CYGHWR_HAL_FREESCALE_DMAMUX0_P +#define CYGHWR_IO_FREESCALE_DMAMUX1_P CYGHWR_HAL_FREESCALE_DMAMUX1_P + +//Clock distribution +#define CYGHWR_IO_CLOCK_ENABLE(__ccgr) hal_clock_enable(__ccgr) + + +#define CYGHWR_IO_FREESCALE_EDMA0_CLK CYGHWR_HAL_KINETIS_SIM_SCGC_DMA +#define CYGHWR_IO_FREESCALE_DMAMUX0_CLK CYGHWR_HAL_KINETIS_SIM_SCGC_DMAMUX0 +#define CYGHWR_IO_FREESCALE_DMAMUX0_CLK CYGHWR_HAL_KINETIS_SIM_SCGC_DMAMUX0 +#define CYGHWR_IO_FREESCALE_DMAMUX1_CLK CYGHWR_HAL_KINETIS_SIM_SCGC_DMAMUX1 +//----------------------------------------------------------------------------- +// end of var_io_devs.h +#endif // CYGONCE_HAL_VAR_IO_DEVS_H diff --git a/ecos/packages/hal/cortexm/vybrid/var/current/include/var_io_gpio.h b/ecos/packages/hal/cortexm/vybrid/var/current/include/var_io_gpio.h new file mode 100644 index 0000000..b5e26bd --- /dev/null +++ b/ecos/packages/hal/cortexm/vybrid/var/current/include/var_io_gpio.h @@ -0,0 +1,125 @@ +#ifndef CYGONCE_HAL_VAR_IO_GPIO_H +#define CYGONCE_HAL_VAR_IO_GPIO_H +//=========================================================================== +// +// var_io_gpio.h +// +// Vybrid GPIO +// +//=========================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2011 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//=========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): Antmicro Ltd <contact@antmicro.com> +// Based on: {...}/hal/packages/cortexm/kinetis/var/current/include/var_io_devs.h +// Date: 2014-03-28 +// Purpose: Vybrid variant specific registers +// Description: +// Usage: #include <cyg/hal/var_io.h> // var_io.h includes this file +// +//####DESCRIPTIONEND#### +// +//=========================================================================== + +//----------------------------------------------------------------------------- +// VYBRID section for GPIO handling per pin operations are covered +// as in VF61GS10 control of subsequent pins from ports e.g A,B,C is distributed between multiple registers +//----------------------------------------------------------------------------- + +// the complete maps of available pads arranged with ascending adresses of +// corresponding IOMUX registers +typedef enum vf61_rgpio_t{ +PTA6, PTA8, PTA9, PTA10,PTA11,PTA12,PTA16,PTA17,PTA18,PTA19,PTA20, +PTA21,PTA22,PTA23,PTA24,PTA25,PTA26,PTA27,PTA28,PTA29,PTA30,PTA31, +PTB0, PTB1, PTB2, PTB3, PTB4, PTB5, PTB6, PTB7, PTB8, PTB9, PTB10, +PTB11,PTB12,PTB13,PTB14,PTB15,PTB16,PTB17,PTB18,PTB19,PTB20,PTB21, +PTB22,PTC0, PTC1, PTC2, PTC3, PTC4, PTC5, PTC6, PTC7, PTC8, PTC9, +PTC10,PTC11,PTC12,PTC13,PTC14,PTC15,PTC16,PTC17,PTD31,PTD30,PTD29, +PTD28,PTD27,PTD26,PTD25,PTD24,PTD23,PTD22,PTD21,PTD20,PTD19,PTD18, +PTD17,PTD16,PTD0, PTD1, PTD2, PTD3, PTD4, PTD5, PTD6, PTD7, PTD8, +PTD9, PTD10,PTD11,PTD12,PTD13,PTB23,PTB24,PTB25,PTB26,PTB27,PTB28, +PTC26,PTC27,PTC28,PTC29,PTC30,PTC31,PTE0, PTE1, PTE2, PTE3, PTE4, +PTE5, PTE6, PTE7, PTE8, PTE9, PTE10,PTE11,PTE12,PTE13,PTE14,PTE15, +PTE16,PTE17,PTE18,PTE19,PTE20,PTE21,PTE22,PTE23,PTE24,PTE25,PTE26, +PTE27,PTE28,PTA7,NONE +} vf61_rgpio; + + +#define CYGHWR_HAL_VYBRID_RGPIO_BASE 0x40048000 //base for IOMUXC +#define CYGHWR_HAL_VYBRID_GPIO_BASE 0x400ff000 //base for GPIO ports + +// GPIO pin control registers offsets +#define CYGHWR_HAL_VYBRID_GPIO_PDOR 0x00 +#define CYGHWR_HAL_VYBRID_GPIO_PSOR 0x04 +#define CYGHWR_HAL_VYBRID_GPIO_PCOR 0x08 +#define CYGHWR_HAL_VYBRID_GPIO_PTOR 0x0c +#define CYGHWR_HAL_VYBRID_GPIO_PDIR 0x10 + + +// gets port numer (0,1,2,3) from pin name +#define CYGHWR_HAL_VYBRID_GET_PORT(__pin) (vf61_rgpio)__pin >> 5 + +// gets GPIO address from pin name +#define CYGHWR_HAL_VYBRID_GET_GPIO(__pin) (CYGHWR_HAL_VYBRID_GPIO_BASE + 0x40*((vf61_rgpio)__pin >> 5)) + +// gets bit location from pin name +#define CYGHWR_HAL_VYBRID_GET_PIN_LOC(__pin) (__pin-32*(__pin>>5)) + +// gets IOMUXC address from pin name +#define CYGHWR_HAL_VYBRID_GET_IOMUXC(__pin) CYGHWR_HAL_VYBRID_RGPIO_BASE+(__pin<<2) + +// get pin status based onto pin name (returns non zero if pin is '1') +#define CYGHWR_HAL_VYBRID_GPIO_GET_PIN(__pin) \ + (*((volatile cyg_uint32 *)(CYGHWR_HAL_VYBRID_GET_GPIO(__pin) + CYGHWR_HAL_VYBRID_GPIO_PDIR)) & (1 << CYGHWR_HAL_VYBRID_GET_PIN_LOC(__pin))) + +// set pin defined by name +#define CYGHWR_HAL_VYBRID_GPIO_SET_PIN(__pin) \ + HAL_WRITE_UINT32(CYGHWR_HAL_VYBRID_GET_GPIO(__pin) + CYGHWR_HAL_VYBRID_GPIO_PSOR, (1 << (CYGHWR_HAL_VYBRID_GET_PIN_LOC(__pin)))) + +// clear pin defined by name +#define CYGHWR_HAL_VYBRID_GPIO_CLEAR_PIN(__pin) \ + HAL_WRITE_UINT32(CYGHWR_HAL_VYBRID_GET_GPIO(__pin) + CYGHWR_HAL_VYBRID_GPIO_PCOR, (1 << (CYGHWR_HAL_VYBRID_GET_PIN_LOC(__pin)))) + +// toggle pin defined by name +#define CYGHWR_HAL_VYBRID_GPIO_TOGGLE_PIN(__pin) \ + HAL_WRITE_UINT32(CYGHWR_HAL_VYBRID_GET_GPIO(__pin) + CYGHWR_HAL_VYBRID_GPIO_PTOR, (1 << (CYGHWR_HAL_VYBRID_GET_PIN_LOC(__pin)))) + +// setup pin definition (mux, direction and so on_ +#define CYGHWR_HAL_VYBRID_PIN_SET_FUNCTION(__pin,__settings)\ + HAL_WRITE_UINT32(CYGHWR_HAL_VYBRID_GET_IOMUXC(__pin), __settings) + +// +//----------------------------------------------------------------------------- +// end of var_io_gpio.h +#endif // CYGONCE_HAL_VAR_IO_GPIO_H diff --git a/ecos/packages/hal/cortexm/vybrid/var/current/include/var_io_lmem.h b/ecos/packages/hal/cortexm/vybrid/var/current/include/var_io_lmem.h new file mode 100644 index 0000000..0f8f2d4 --- /dev/null +++ b/ecos/packages/hal/cortexm/vybrid/var/current/include/var_io_lmem.h @@ -0,0 +1,254 @@ +#ifndef CYGONCE_HAL_VAR_IO_LMEM_H +#define CYGONCE_HAL_VAR_IO_LMEM_H +//=========================================================================== +// +// var_io_lmem.h +// +// Vybrid Local memory controller specific registers +// +//=========================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2012 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//=========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): Antmicro Ltd <contact@antmicro.com> +// Based on: {...}/hal/packages/cortexm/kinetis/var/current/include/var_io_lmem.h +// Date: 2014-03-28 +// Purpose: Vybrid variant specific registers +// Description: +// Usage: #include <cyg/hal/var_io_lmem.h> // var_io.h includes this file +// +//####DESCRIPTIONEND#### +// +//=========================================================================== + +//---------------------------------------------------------------------------- +// LMEM - Local memory controller + +typedef volatile struct cyghwr_hal_vybrid_lmem_s { + cyg_uint32 ccr; // PC bus Cache control register + cyg_uint32 clcr; // PC bus Cache line control register + void *csar; // PC bus Cache search address register + cyg_uint32 cvr; // PC bus Cache read/write value register +} cyghwr_hal_vybrid_lmem_t; + +#define CYGHWR_HAL_VYBRID_LMEM_PC_P ((cyghwr_hal_vybrid_lmem_t *) 0xE0082000) +#define CYGHWR_HAL_VYBRID_LMEM_PS_P ((cyghwr_hal_vybrid_lmem_t *) 0xE0082800) + +// CCR Bit Fields +#define CYGHWR_HAL_VYBRID_LMEM_CCR_ENCACHE_M 0x00000001 +#define CYGHWR_HAL_VYBRID_LMEM_CCR_ENWRBUF_M 0x00000002 +#define CYGHWR_HAL_VYBRID_LMEM_CCR_PCCR2 0x00000004 +#define CYGHWR_HAL_VYBRID_LMEM_CCR_PCCR3 0x00000008 +#define CYGHWR_HAL_VYBRID_LMEM_CCR_INVW0_M 0x01000000 +#define CYGHWR_HAL_VYBRID_LMEM_CCR_PUSHW0_M 0x02000000 +#define CYGHWR_HAL_VYBRID_LMEM_CCR_INVW1_M 0x04000000 +#define CYGHWR_HAL_VYBRID_LMEM_CCR_PUSHW1_M 0x08000000 +#define CYGHWR_HAL_VYBRID_LMEM_CCR_GO_M 0x80000000 + +//CLCR Bit Fields +#define CYGHWR_HAL_VYBRID_LMEM_CLCR_LGO_M 0x00000001 +#define CYGHWR_HAL_VYBRID_LMEM_CLCR_CACHEADDR_M 0x00000FFC +#define CYGHWR_HAL_VYBRID_LMEM_CLCR_CACHEADDR_S 2 +#define CYGHWR_HAL_VYBRID_LMEM_CLCR_CACHEADDR(_ca_) ((_ca_) << CYGHWR_HAL_VYBRID_LMEM_CLCR_CACHEADDR_S) +#define CYGHWR_HAL_VYBRID_LMEM_CLCR_WSEL_M 0x00004000 +#define CYGHWR_HAL_VYBRID_LMEM_CLCR_TDSEL_M 0x00010000 +#define CYGHWR_HAL_VYBRID_LMEM_CLCR_LCIVB_M 0x00100000 +#define CYGHWR_HAL_VYBRID_LMEM_CLCR_LCIMB_M 0x00200000 +#define CYGHWR_HAL_VYBRID_LMEM_CLCR_LCWAY_M 0x00400000 +#define CYGHWR_HAL_VYBRID_LMEM_CLCR_LCMD_M 0x03000000 +#define CYGHWR_HAL_VYBRID_LMEM_CLCR_LCMD_S 24 +#define CYGHWR_HAL_VYBRID_LMEM_CLCR_LCMD(_cmd_) ((_cmd_) << CYGHWR_HAL_VYBRID_LMEM_CLCR_LCMD_S) +#define CYGHWR_HAL_VYBRID_LMEM_CLCR_LCMD_SRCH 0 +#define CYGHWR_HAL_VYBRID_LMEM_CLCR_LCMD_INVAL 1 +#define CYGHWR_HAL_VYBRID_LMEM_CLCR_LCMD_PUSH 2 +#define CYGHWR_HAL_VYBRID_LMEM_CLCR_LCMD_CLR 3 +#define CYGHWR_HAL_VYBRID_LMEM_CLCR_LADSEL_M 0x04000000 +#define CYGHWR_HAL_VYBRID_LMEM_CLCR_LACC_M 0x08000000 + +// CSAR Bit Fields +#define CYGHWR_HAL_VYBRID_LMEM_CSAR_LGO_M 0x00000001 +#define CYGHWR_HAL_VYBRID_LMEM_CSAR_PHYADDR_M 0xFFFFFFFC +#define CYGHWR_HAL_VYBRID_LMEM_CSAR_PHYADDR_S 2 +#define CYGHWR_HAL_VYBRID_LMEM_CSAR_PHYADDR(_adr_) ((_adr_) << CYGHWR_HAL_VYBRID_LMEM_CSAR_PHYADDR_S) + +// CCVR Bit Fields +#define CYGHWR_HAL_VYBRID_LMEM_CCVR_DATA_M 0xFFFFFFFF + +#define HAL_CORTEXM_VYBRID_CACHE_PC_ENABLE() \ + hal_cortexm_vybrid_cache_enable(CYGHWR_HAL_VYBRID_LMEM_PC_P) + +#define HAL_CORTEXM_VYBRID_CACHE_PS_ENABLE() \ + hal_cortexm_vybrid_cache_enable(CYGHWR_HAL_VYBRID_LMEM_PS_P) + +#define HAL_CORTEXM_VYBRID_CACHE_PC_DISABLE() \ + hal_cortexm_vybrid_cache_disable(CYGHWR_HAL_VYBRID_LMEM_PC_P) + +#define HAL_CORTEXM_VYBRID_CACHE_PS_DISABLE() \ + hal_cortexm_vybrid_cache_disable(CYGHWR_HAL_VYBRID_LMEM_PS_P) + +#define HAL_CORTEXM_VYBRID_CACHE_PC_INVALL() \ + hal_cortexm_vybrid_cache_inval(CYGHWR_HAL_VYBRID_LMEM_PC_P) + +#define HAL_CORTEXM_VYBRID_CACHE_PS_INVALL() \ + hal_cortexm_vybrid_cache_inval(CYGHWR_HAL_VYBRID_LMEM_PS_P) + +#define HAL_CORTEXM_VYBRID_CACHE_PC_SYNC() \ + hal_cortexm_vybrid_cache_sync(CYGHWR_HAL_VYBRID_LMEM_PC_P) + +#define HAL_CORTEXM_VYBRID_CACHE_PS_SYNC() \ + hal_cortexm_vybrid_cache_sync(CYGHWR_HAL_VYBRID_LMEM_PS_P) + +#define HAL_CORTEXM_VYBRID_CACHE_PC_CLEAR() \ + hal_cortexm_vybrid_cache_clear(CYGHWR_HAL_VYBRID_LMEM_PC_P) + +#define HAL_CORTEXM_VYBRID_CACHE_PS_CLEAR() \ + hal_cortexm_vybrid_cache_clear(CYGHWR_HAL_VYBRID_LMEM_PS_P) + +#define HAL_CORTEXM_VYBRID_CACHE_PC_IS_ENABLED() \ + hal_cortexm_vybrid_cache_is_enabled(CYGHWR_HAL_VYBRID_LMEM_PC_P) + +#define HAL_CORTEXM_VYBRID_CACHE_PS_IS_ENABLED() \ + hal_cortexm_vybrid_cache_is_enabled(CYGHWR_HAL_VYBRID_LMEM_PS_P) + +#define HAL_CORTEXM_VYBRID_CACHE_PS_SRCH(_base, _size_) \ + hal_cortexm_vybrid_cache_lines(CYGHWR_HAL_VYBRID_LMEM_PS_P, _base, _size_, \ + CYGHWR_HAL_VYBRID_LMEM_CLCR_LCMD_SRCH) + +#define HAL_CORTEXM_VYBRID_CACHE_PS_INVALIDATE(_base, _size_) \ + hal_cortexm_vybrid_cache_lines(CYGHWR_HAL_VYBRID_LMEM_PS_P, _base, _size_, \ + CYGHWR_HAL_VYBRID_LMEM_CLCR_LCMD_INVAL) + +#define HAL_CORTEXM_VYBRID_CACHE_PS_PUSH(_base, _size_) \ + hal_cortexm_vybrid_cache_lines(CYGHWR_HAL_VYBRID_LMEM_PS_P, _base, _size_, \ + CYGHWR_HAL_VYBRID_LMEM_CLCR_LCMD_PUSH) + +#define HAL_CORTEXM_VYBRID_CACHE_PS_CLR(_base, _size_) \ + hal_cortexm_vybrid_cache_lines(CYGHWR_HAL_VYBRID_LMEM_PS_P, _base, _size_, \ + CYGHWR_HAL_VYBRID_LMEM_CLCR_LCMD_CLR) + +#define HAL_CORTEXM_VYBRID_CACHE_PC_INVALIDATE(_base, _size_) \ + hal_cortexm_vybrid_cache_lines(CYGHWR_HAL_VYBRID_LMEM_PC_P, _base, _size_, \ + CYGHWR_HAL_VYBRID_LMEM_CLCR_LCMD_INVAL) + +#define CYGHWR_HAL_VYBRID_CACHE_WAIT(_lmem_p) \ + while((_lmem_p)->ccr & CYGHWR_HAL_VYBRID_LMEM_CCR_GO_M) + +CYGBLD_FORCE_INLINE void +hal_cortexm_vybrid_cache_enable(cyghwr_hal_vybrid_lmem_t* lmem_p) +{ + lmem_p->ccr = ( CYGHWR_HAL_VYBRID_LMEM_CCR_GO_M | + CYGHWR_HAL_VYBRID_LMEM_CCR_INVW0_M | + CYGHWR_HAL_VYBRID_LMEM_CCR_INVW1_M | + CYGHWR_HAL_VYBRID_LMEM_CCR_ENCACHE_M | + CYGHWR_HAL_VYBRID_LMEM_CCR_ENWRBUF_M + ); + CYGHWR_HAL_VYBRID_CACHE_WAIT(lmem_p); +} + +CYGBLD_FORCE_INLINE void +hal_cortexm_vybrid_cache_disable(cyghwr_hal_vybrid_lmem_t* lmem_p) +{ + lmem_p->ccr = 0; +} + +CYGBLD_FORCE_INLINE void +hal_cortexm_vybrid_cache_inval(cyghwr_hal_vybrid_lmem_t* lmem_p) +{ + lmem_p->ccr |= ( CYGHWR_HAL_VYBRID_LMEM_CCR_GO_M | + CYGHWR_HAL_VYBRID_LMEM_CCR_INVW0_M | + CYGHWR_HAL_VYBRID_LMEM_CCR_INVW1_M + ); + CYGHWR_HAL_VYBRID_CACHE_WAIT(lmem_p); +} + +CYGBLD_FORCE_INLINE void +hal_cortexm_vybrid_cache_store(cyghwr_hal_vybrid_lmem_t* lmem_p) +{ + lmem_p->ccr |= ( CYGHWR_HAL_VYBRID_LMEM_CCR_GO_M | + CYGHWR_HAL_VYBRID_LMEM_CCR_PUSHW0_M | + CYGHWR_HAL_VYBRID_LMEM_CCR_PUSHW1_M + ); + CYGHWR_HAL_VYBRID_CACHE_WAIT(lmem_p); +} + +CYGBLD_FORCE_INLINE void +hal_cortexm_vybrid_cache_clear(cyghwr_hal_vybrid_lmem_t* lmem_p) +{ + lmem_p->ccr |= ( CYGHWR_HAL_VYBRID_LMEM_CCR_GO_M | + CYGHWR_HAL_VYBRID_LMEM_CCR_INVW0_M | + CYGHWR_HAL_VYBRID_LMEM_CCR_INVW1_M | + CYGHWR_HAL_VYBRID_LMEM_CCR_PUSHW0_M | + CYGHWR_HAL_VYBRID_LMEM_CCR_PUSHW1_M + ); + CYGHWR_HAL_VYBRID_CACHE_WAIT(lmem_p); +} + +CYGBLD_FORCE_INLINE void +hal_cortexm_vybrid_cache_sync(cyghwr_hal_vybrid_lmem_t* lmem_p) +{ + hal_cortexm_vybrid_cache_store(lmem_p); + hal_cortexm_vybrid_cache_clear(lmem_p); +} + +CYGBLD_FORCE_INLINE bool +hal_cortexm_vybrid_cache_is_enabled(cyghwr_hal_vybrid_lmem_t* lmem_p) +{ + return lmem_p->ccr & CYGHWR_HAL_VYBRID_LMEM_CCR_ENCACHE_M; +} + + +CYGBLD_FORCE_INLINE void +hal_cortexm_vybrid_cache_lines(cyghwr_hal_vybrid_lmem_t* lmem_p, + void* addr_p, cyg_uint32 size, + const cyg_uint32 oper) +{ + cyg_uint32 line_k; + line_k = (((cyg_uint32)addr_p & (HAL_DCACHE_LINE_SIZE-1)) + size) / HAL_DCACHE_LINE_SIZE + 1; + + lmem_p->clcr = CYGHWR_HAL_VYBRID_LMEM_CLCR_LADSEL_M | + CYGHWR_HAL_VYBRID_LMEM_CLCR_TDSEL_M | + CYGHWR_HAL_VYBRID_LMEM_CLCR_LCMD(oper); + + addr_p = (void*)((((cyg_uint32) addr_p) & 0xfffffff0) | + CYGHWR_HAL_VYBRID_LMEM_CLCR_LGO_M); + do { + lmem_p->csar = addr_p; + while(lmem_p->clcr & CYGHWR_HAL_VYBRID_LMEM_CLCR_LGO_M); + addr_p = (void*)(((cyg_uint32)addr_p) + HAL_DCACHE_LINE_SIZE); + } while(--line_k); +} + +//----------------------------------------------------------------------------- +// end of var_io_lmem.h +#endif // CYGONCE_HAL_VAR_IO_LMEM_H diff --git a/ecos/packages/hal/cortexm/vybrid/var/current/include/variant.inc b/ecos/packages/hal/cortexm/vybrid/var/current/include/variant.inc new file mode 100644 index 0000000..c88a975 --- /dev/null +++ b/ecos/packages/hal/cortexm/vybrid/var/current/include/variant.inc @@ -0,0 +1,55 @@ +/*========================================================================== +// +// variant.inc +// +// Variant specific asm definitions +// +//========================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2011 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): Antmicro Ltd <contact@antmicro.com> +// Based on: {...}/hal/packages/cortexm/kinetis/var/current/include/variant.inc +// Date: 2014-03-28 + +// Description: +// +//####DESCRIPTIONEND#### +// +//========================================================================*/ + +#include <pkgconf/hal_cortexm_vybrid.h> + +//========================================================================== +// EOF variant.inc diff --git a/ecos/packages/hal/cortexm/vybrid/var/current/src/hal_diag.c b/ecos/packages/hal/cortexm/vybrid/var/current/src/hal_diag.c new file mode 100644 index 0000000..b4a3fd1 --- /dev/null +++ b/ecos/packages/hal/cortexm/vybrid/var/current/src/hal_diag.c @@ -0,0 +1,405 @@ +/*============================================================================= +// +// hal_diag.c +// +// HAL diagnostic output code +// +//============================================================================= +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2011, 2013 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): Antmicro Ltd <contact@antmicro.com> +// Based on: {...}/hal/packages/cortexm/kinetis/var/current/src/hal_diag.c +// Date: 2014-03-28 +// Purpose: HAL diagnostic input/output +// Description: Implementations of HAL diagnostic input/output support. +// +//####DESCRIPTIONEND#### +// +//=========================================================================== + */ + +#include <pkgconf/hal.h> +#include CYGBLD_HAL_PLATFORM_H + +#include <cyg/infra/cyg_type.h> // base types + +#include <cyg/hal/hal_arch.h> // SAVE/RESTORE GP macros +#include <cyg/hal/hal_io.h> // IO macros +#include <cyg/hal/hal_if.h> // interface API +#include <cyg/hal/hal_intr.h> // HAL_ENABLE/MASK/UNMASK_INTERRUPTS +#include <cyg/hal/hal_misc.h> // Helper functions +#include <cyg/hal/drv_api.h> // CYG_ISR_HANDLED +#include <cyg/hal/hal_diag.h> + +#include <cyg/hal/var_io.h> // +#include <cyg/io/ser_freescale_uart.h> // UART registers + +//----------------------------------------------------------------------------- + +typedef struct { + cyg_uint32 uart; + CYG_ADDRESS base; + cyg_int32 msec_timeout; + cyg_int32 isr_vector; + cyg_uint32 rx_pin; + cyg_uint32 tx_pin; + cyg_uint32 clock_gate; + cyg_int32 baud_rate; + cyg_int32 irq_state; +} channel_data_t; + +channel_data_t plf_ser_channels[] = { +#ifdef CYGINT_HAL_FREESCALE_UART0 + { 0, CYGADDR_IO_SERIAL_FREESCALE_UART0_BASE, 1000, + CYGNUM_HAL_INTERRUPT_UART0_RX_TX, + CYGHWR_HAL_FREESCALE_UART0_PIN_RX, CYGHWR_HAL_FREESCALE_UART0_PIN_TX, + CYGHWR_IO_FREESCALE_UART0_CLOCK, CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD }, +#endif +#ifdef CYGINT_HAL_FREESCALE_UART1 + { 1, CYGADDR_IO_SERIAL_FREESCALE_UART1_BASE, 1000, + CYGNUM_HAL_INTERRUPT_UART1_RX_TX, + CYGHWR_HAL_FREESCALE_UART1_PIN_RX, CYGHWR_HAL_FREESCALE_UART1_PIN_TX, + CYGHWR_IO_FREESCALE_UART1_CLOCK, CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD }, +#endif +#ifdef CYGINT_HAL_FREESCALE_UART2 + { 2, CYGADDR_IO_SERIAL_FREESCALE_UART2_BASE, 1000, + CYGNUM_HAL_INTERRUPT_UART2_RX_TX, + CYGHWR_HAL_FREESCALE_UART2_PIN_RX, CYGHWR_HAL_FREESCALE_UART2_PIN_TX, + CYGHWR_IO_FREESCALE_UART2_CLOCK, CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD }, +#endif +#ifdef CYGINT_HAL_FREESCALE_UART3 + { 3, CYGADDR_IO_SERIAL_FREESCALE_UART3_BASE, 1000, + CYGNUM_HAL_INTERRUPT_UART3_RX_TX, + CYGHWR_HAL_FREESCALE_UART3_PIN_RX, CYGHWR_HAL_FREESCALE_UART3_PIN_TX, + CYGHWR_IO_FREESCALE_UART3_CLOCK, CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD }, +#endif +#ifdef CYGINT_HAL_FREESCALE_UART4 + { 4, CYGADDR_IO_SERIAL_FREESCALE_UART4_BASE, 1000, + CYGNUM_HAL_INTERRUPT_UART4_RX_TX, + CYGHWR_HAL_FREESCALE_UART4_PIN_RX, CYGHWR_HAL_FREESCALE_UART4_PIN_TX, + CYGHWR_IO_FREESCALE_UART4_CLOCK, CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD }, +#endif +#ifdef CYGINT_HAL_FREESCALE_UART5 + { 5, CYGADDR_IO_SERIAL_FREESCALE_UART5_BASE, 1000, + CYGNUM_HAL_INTERRUPT_UART5_RX_TX, + CYGHWR_HAL_FREESCALE_UART5_PIN_RX, CYGHWR_HAL_FREESCALE_UART5_PIN_TX, + CYGHWR_IO_FREESCALE_UART5_CLOCK, CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD } +#endif +}; + +//----------------------------------------------------------------------------- + +void +cyg_hal_plf_serial_putc(void *__ch_data, char c); + +static void +cyg_hal_plf_serial_init_channel(void* __ch_data) +{ + channel_data_t* chan = (channel_data_t*)__ch_data; + CYG_ADDRESS uart_p = chan->base; + + // Bring clock to the device + CYGHWR_IO_CLOCK_ENABLE(chan->clock_gate); + + // Configure PORT pins + hal_set_pin_function(chan->rx_pin); + hal_set_pin_function(chan->tx_pin); + + // 8-1-no parity. + HAL_WRITE_UINT8(uart_p + CYGHWR_DEV_FREESCALE_UART_C1, 0); + + CYGHWR_IO_FREESCALE_UART_BAUD_SET(uart_p, chan->baud_rate); + + // Enable RX and TX + HAL_WRITE_UINT8(uart_p + CYGHWR_DEV_FREESCALE_UART_C2, + (CYGHWR_DEV_FREESCALE_UART_C2_TE | + CYGHWR_DEV_FREESCALE_UART_C2_RE)); +} + +void +cyg_hal_plf_serial_putc(void* __ch_data, char ch_out) +{ + channel_data_t* chan = (channel_data_t*)__ch_data; + CYG_ADDRESS uart_p = (CYG_ADDRESS) chan->base; + cyg_uint32 uart_s1; + + CYGARC_HAL_SAVE_GP(); + + do { + HAL_READ_UINT8(uart_p + CYGHWR_DEV_FREESCALE_UART_S1, uart_s1); + } while (!(uart_s1 & CYGHWR_DEV_FREESCALE_UART_S1_TDRE)); + + HAL_WRITE_UINT8(uart_p + CYGHWR_DEV_FREESCALE_UART_D, ch_out); + + CYGARC_HAL_RESTORE_GP(); +} + +static cyg_bool +cyg_hal_plf_serial_getc_nonblock(void* __ch_data, cyg_uint8* p_ch_in) +{ + channel_data_t* chan = (channel_data_t*)__ch_data; + CYG_ADDRESS uart_p = (CYG_ADDRESS) chan->base; + cyg_uint8 uart_s1; + cyg_uint8 ch_in; + + HAL_READ_UINT8(uart_p + CYGHWR_DEV_FREESCALE_UART_S1, uart_s1); + if (!(uart_s1 & CYGHWR_DEV_FREESCALE_UART_S1_RDRF)) + return false; + + HAL_READ_UINT8(uart_p + CYGHWR_DEV_FREESCALE_UART_D, ch_in); + *p_ch_in = ch_in; + + return true; +} + +cyg_uint8 +cyg_hal_plf_serial_getc(void* __ch_data) +{ + cyg_uint8 ch; + CYGARC_HAL_SAVE_GP(); + + while(!cyg_hal_plf_serial_getc_nonblock(__ch_data, &ch)); + + CYGARC_HAL_RESTORE_GP(); + return ch; +} + + +//============================================================================= +// Virtual vector HAL diagnostics + +#if defined(CYGSEM_HAL_VIRTUAL_VECTOR_DIAG) + +static void +cyg_hal_plf_serial_write(void* __ch_data, const cyg_uint8* __buf, + cyg_uint32 __len) +{ + CYGARC_HAL_SAVE_GP(); + + while(__len-- > 0) + cyg_hal_plf_serial_putc(__ch_data, *__buf++); + + CYGARC_HAL_RESTORE_GP(); +} + +static void +cyg_hal_plf_serial_read(void* __ch_data, cyg_uint8* __buf, cyg_uint32 __len) +{ + CYGARC_HAL_SAVE_GP(); + + while(__len-- > 0) + *__buf++ = cyg_hal_plf_serial_getc(__ch_data); + + CYGARC_HAL_RESTORE_GP(); +} + +cyg_bool +cyg_hal_plf_serial_getc_timeout(void* __ch_data, cyg_uint8* p_ch_in) +{ + int delay_count; + cyg_bool res; + CYGARC_HAL_SAVE_GP(); + + // delay in .1 ms steps + delay_count = ((channel_data_t*)__ch_data)->msec_timeout * 10; + + for(;;) { + res = cyg_hal_plf_serial_getc_nonblock(__ch_data, p_ch_in); + if (res || 0 == delay_count--) + break; + + CYGACC_CALL_IF_DELAY_US(100); + } + + CYGARC_HAL_RESTORE_GP(); + return res; +} + +static int +cyg_hal_plf_serial_control(void *__ch_data, __comm_control_cmd_t __func, ...) +{ + channel_data_t* chan = (channel_data_t*)__ch_data; + CYG_ADDRESS uart_p = ((channel_data_t*)__ch_data)->base; + cyg_uint8 ser_port_reg; + int ret = 0; + va_list ap; + + CYGARC_HAL_SAVE_GP(); + va_start(ap, __func); + + switch (__func) { + case __COMMCTL_IRQ_ENABLE: + chan->irq_state = 1; + HAL_INTERRUPT_ACKNOWLEDGE(chan->isr_vector); + HAL_INTERRUPT_UNMASK(chan->isr_vector); + + HAL_READ_UINT8(uart_p + CYGHWR_DEV_FREESCALE_UART_C2, ser_port_reg); + ser_port_reg |= CYGHWR_DEV_FREESCALE_UART_C2_RIE; + HAL_WRITE_UINT8(uart_p + CYGHWR_DEV_FREESCALE_UART_C2, ser_port_reg); + + break; + case __COMMCTL_IRQ_DISABLE: + ret = chan->irq_state; + chan->irq_state = 0; + HAL_INTERRUPT_MASK(chan->isr_vector); + + HAL_READ_UINT8(uart_p + CYGHWR_DEV_FREESCALE_UART_C2, ser_port_reg); + ser_port_reg &= ~(cyg_uint8)CYGHWR_DEV_FREESCALE_UART_C2_RIE; + HAL_WRITE_UINT8(uart_p + CYGHWR_DEV_FREESCALE_UART_C2, ser_port_reg); + break; + case __COMMCTL_DBG_ISR_VECTOR: + ret = chan->isr_vector; + break; + case __COMMCTL_SET_TIMEOUT: + ret = chan->msec_timeout; + chan->msec_timeout = va_arg(ap, cyg_uint32); + case __COMMCTL_GETBAUD: + ret = chan->baud_rate; + break; + case __COMMCTL_SETBAUD: + chan->baud_rate = va_arg(ap, cyg_int32); + // Should we verify this value here? + cyg_hal_plf_serial_init_channel(chan); + ret = 0; + break; + default: + break; + } + + va_end(ap); + CYGARC_HAL_RESTORE_GP(); + return ret; +} + +static int +cyg_hal_plf_serial_isr(void *__ch_data, int* __ctrlc, + CYG_ADDRWORD __vector, CYG_ADDRWORD __data) +{ + + channel_data_t* chan = (channel_data_t*)__ch_data; + CYG_ADDRESS uart_p = (CYG_ADDRESS) chan->base; + cyg_uint8 uart_s1; + int res = 0; + cyg_uint8 ch_in; + CYGARC_HAL_SAVE_GP(); + + *__ctrlc = 0; + + HAL_READ_UINT8(uart_p + CYGHWR_DEV_FREESCALE_UART_S1, uart_s1); + if (uart_s1 & CYGHWR_DEV_FREESCALE_UART_S1_RDRF) { + HAL_READ_UINT8(uart_p + CYGHWR_DEV_FREESCALE_UART_D, ch_in); + if( cyg_hal_is_break( (char *) &ch_in , 1 ) ) + *__ctrlc = 1; + + res = CYG_ISR_HANDLED; + } + + HAL_INTERRUPT_ACKNOWLEDGE(chan->isr_vector); + + CYGARC_HAL_RESTORE_GP(); + return res; +} + +static void +cyg_hal_plf_serial_init(void) +{ + hal_virtual_comm_table_t* comm; + int cur; + int chan_i; + + cur = CYGACC_CALL_IF_SET_CONSOLE_COMM(CYGNUM_CALL_IF_SET_COMM_ID_QUERY_CURRENT); + + // Init channels + for(chan_i=0; chan_i<CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS; chan_i++) { + cyg_hal_plf_serial_init_channel(&plf_ser_channels[chan_i]); + // Setup procs in the vector table + CYGACC_CALL_IF_SET_CONSOLE_COMM(chan_i); + comm = CYGACC_CALL_IF_CONSOLE_PROCS(); + + CYGACC_COMM_IF_CH_DATA_SET(*comm, &plf_ser_channels[chan_i]); + CYGACC_COMM_IF_WRITE_SET(*comm, cyg_hal_plf_serial_write); + CYGACC_COMM_IF_READ_SET(*comm, cyg_hal_plf_serial_read); + CYGACC_COMM_IF_PUTC_SET(*comm, cyg_hal_plf_serial_putc); + CYGACC_COMM_IF_GETC_SET(*comm, cyg_hal_plf_serial_getc); + CYGACC_COMM_IF_CONTROL_SET(*comm, cyg_hal_plf_serial_control); + CYGACC_COMM_IF_DBG_ISR_SET(*comm, cyg_hal_plf_serial_isr); + CYGACC_COMM_IF_GETC_TIMEOUT_SET(*comm, cyg_hal_plf_serial_getc_timeout); + } + // Restore original console + CYGACC_CALL_IF_SET_CONSOLE_COMM(cur); +#if (CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD != CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_BAUD) + plf_ser_channels[CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL]->baud_rate = + CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_BAUD; + update_baud_rate( &plf_ser_channels[CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL] ); +#endif + +} + +void +cyg_hal_plf_comms_init(void) +{ + static int initialized = 0; + + if (initialized) + return; + initialized = 1; + cyg_hal_plf_serial_init(); +} + +#else // !defined(CYGSEM_HAL_VIRTUAL_VECTOR_DIAG) +//============================================================================= +// Non-Virtual vector HAL diagnostics + +// #if !defined(CYGSEM_HAL_VIRTUAL_VECTOR_DIAG) + +void hal_plf_diag_init(void) +{ + cyg_hal_plf_serial_init( &plf_ser_channels[CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL] ); +} + +void hal_plf_diag_putc(char c) +{ + cyg_hal_plf_serial_putc( &plf_ser_channels[CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL], c); +} + +cyg_uint8 hal_plf_diag_getc(void) +{ + return cyg_hal_plf_serial_getc( &plf_ser_channels[CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL] ); +} + +#endif // defined(CYGSEM_HAL_VIRTUAL_VECTOR_DIAG) + +//----------------------------------------------------------------------------- +// End of hal_diag.c diff --git a/ecos/packages/hal/cortexm/vybrid/var/current/src/vybrid_clocking.c b/ecos/packages/hal/cortexm/vybrid/var/current/src/vybrid_clocking.c new file mode 100644 index 0000000..3aac8ed --- /dev/null +++ b/ecos/packages/hal/cortexm/vybrid/var/current/src/vybrid_clocking.c @@ -0,0 +1,236 @@ +//========================================================================== +// +// vybrid_clocking.c +// +// Cortex-M Vybrid HAL functions +// +//========================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2010 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): Antmicro Ltd <contact@antmicro.com> +// Based on: {...}/hal/packages/cortexm/kinetis/var/current/include/kinetis_clocking.h +// Date: 2014-03-28 +// Description: +// +//####DESCRIPTIONEND#### +// +//======================================================================== + +#include <pkgconf/hal.h> +#include <pkgconf/hal_cortexm.h> +#include <pkgconf/hal_cortexm_vybrid.h> +#ifdef CYGPKG_KERNEL +#include <pkgconf/kernel.h> +#endif + +#include <cyg/infra/diag.h> +#include <cyg/infra/cyg_type.h> +#include <cyg/infra/cyg_trac.h> // tracing macros +#include <cyg/infra/cyg_ass.h> // assertion macros + +#include <cyg/hal/cortexm_endian.h> +#include <cyg/hal/hal_arch.h> // HAL header +#include <cyg/hal/hal_intr.h> // HAL header +#include <cyg/hal/hal_if.h> // HAL header + +#include <cyg/io/ser_freescale_uart.h> + +//=========================================================================== +// Forward declarations +//=========================================================================== + +cyg_uint32 hal_cortexm_systick_clock; +cyg_uint32 hal_vybrid_sysclk; +cyg_uint32 hal_vybrid_busclk; + +cyg_uint32 hal_get_cpu_clock(void); + +cyg_uint32 +hal_get_cpu_clock(void) +{ + cyghwr_hal_vybrid_ccm_t *ccm = CYGHWR_HAL_VYBRID_CCM_P; + cyg_uint32 sys_clk_sel; + cyg_uint32 pfd_sel, pfd; + cyg_uint32 mfi, mfn, mfd; + cyg_uint32 freq = 0, arm_clk_div, bus_clk_div; + + sys_clk_sel = (ccm->ccsr & CYGHWR_HAL_VYBRID_CCM_CCSR_SYS_CLK_SEL_M); + switch(sys_clk_sel) { + case 0: // Fast clock o/p defined by CCM_CCSR[FAST_CLK_SEL] + /* 24MHz clock. It might be internal RC or external OSC*/ + freq = 24000000; + break; + case 1: // Slow clock o/p defined by CCM_CCSR[SLOW_CLK_SEL] + freq = 32000; + break; + case 2: // PLL2 PFD o/p clock defined by CCM_CCSR[PLL2_PFD_CLK_SEL] + pfd_sel = (ccm->ccsr & CYGHWR_HAL_VYBRID_CCM_CCSR_PLL2_PFD_CLK_SEL_M); + pfd_sel = (pfd_sel >> CYGHWR_HAL_VYBRID_CCM_CCSR_PLL2_PFD_CLK_SEL_S); + if(pfd_sel) { + HAL_READ_UINT32(CYGHWR_HAL_VYBRID_ANADIG_PLL2_NUM, mfn); + HAL_READ_UINT32(CYGHWR_HAL_VYBRID_ANADIG_PLL2_DENOM, mfd); + HAL_READ_UINT32(CYGHWR_HAL_VYBRID_ANADIG_PLL2_CTRL, mfi); + // check the value of frequency multiplier + mfi &= CYGHWR_HAL_VYBRID_ANADIG_PLL2_CTRL_DIV_SELECT_M; + // if CYGHWR_HAL_VYBRID_ANADIG_PLL2_CTRL_DIV_SELECT is set, then mfi is 22 + mfi = (mfi ? 22 : 20); + // calculate the PLL! frequency + freq = (24000000 * (mfi + (mfn / mfd))); + HAL_READ_UINT32(CYGHWR_HAL_VYBRID_ANADIG_PLL2_PFD, pfd); + pfd = pfd >> (8*(pfd_sel-1)); + pfd &= 0x3f; + //PFDout = PLLput * (18 / PFD_FRAC) + freq /= pfd; + freq *= 18; + } + break; + // Fall down as the pfd_sel == 0 selects PLL2 main clock + case 3: // PLL2 main clock + // check if PLL2 is bypassed + HAL_READ_UINT32(CYGHWR_HAL_VYBRID_ANADIG_PLL2_CTRL, mfi); + mfi &= CYGHWR_HAL_VYBRID_ANADIG_PLL2_CTRL_BYPASS_M; + if (mfi) { + freq = 24000000; + break; + } + // get pll2 coefficients + HAL_READ_UINT32(CYGHWR_HAL_VYBRID_ANADIG_PLL2_NUM, mfn); + HAL_READ_UINT32(CYGHWR_HAL_VYBRID_ANADIG_PLL2_DENOM, mfd); + HAL_READ_UINT32(CYGHWR_HAL_VYBRID_ANADIG_PLL2_CTRL, mfi); + // check the value of frequency multiplier + mfi &= CYGHWR_HAL_VYBRID_ANADIG_PLL2_CTRL_DIV_SELECT_M; + // if CYGHWR_HAL_VYBRID_ANADIG_PLL2_CTRL_DIV_SELECT is set, then mfi is 22 + mfi = (mfi ? 22 : 20); + // calculate the PLL! frequency + freq = (24000000 * (mfi + (mfn / mfd))); + break; + case 4: // PLL1 PFD o/p clock defined by CCM_CCSR[PLL1_PFD_CLK_SEL] + pfd_sel = (ccm->ccsr & CYGHWR_HAL_VYBRID_CCM_CCSR_PLL1_PFD_CLK_SEL_M); + pfd_sel = (pfd_sel >> CYGHWR_HAL_VYBRID_CCM_CCSR_PLL1_PFD_CLK_SEL_S); + HAL_READ_UINT32(CYGHWR_HAL_VYBRID_ANADIG_PLL1_NUM, mfn); + HAL_READ_UINT32(CYGHWR_HAL_VYBRID_ANADIG_PLL1_DENOM, mfd); + HAL_READ_UINT32(CYGHWR_HAL_VYBRID_ANADIG_PLL1_CTRL, mfi); + // check the value of frequency multiplier + mfi &= CYGHWR_HAL_VYBRID_ANADIG_PLL1_CTRL_DIV_SELECT_M; + // if CYGHWR_HAL_VYBRID_ANADIG_PLL1_CTRL_DIV_SELECT is set, then mfi is 22 + mfi = 22;//(mfi ? 22 : 20); -> uncertain in VRM p. 726 (11.21.26 ANADIG PLL1_PFD definition register (ANADIG_PLL1_PFD)) + // calculate the PLL1 frequency PLLout = Fref*(MFI + MFN/MFD) where Fref=24MHz + freq = (24000000 * (mfi + (mfn / mfd))); + if(pfd_sel) { + HAL_READ_UINT32(CYGHWR_HAL_VYBRID_ANADIG_PLL1_PFD, pfd); + pfd = pfd >> (8*(pfd_sel-1)); + pfd &= 0x3f; + freq /= pfd; + freq *= 18; + } + //TODO: handle the PLL1 main clk + break; + case 5: // PLL3 main clock + HAL_READ_UINT32(CYGHWR_HAL_VYBRID_ANADIG_PLL3_CTRL, mfi); + mfi &= CYGHWR_HAL_VYBRID_ANADIG_PLL3_CTRL_BYPASS_M; + if (mfi) { + freq = 24000000; + break; + } + HAL_READ_UINT32(CYGHWR_HAL_VYBRID_ANADIG_PLL3_CTRL, mfi); + // check the value of frequency multiplier + mfi &= CYGHWR_HAL_VYBRID_ANADIG_PLL2_CTRL_DIV_SELECT_M; + // if CYGHWR_HAL_VYBRID_ANADIG_PLL2_CTRL_DIV_SELECT is set, then mfi is 22 + // freq is fixed (MFN and MFD not available) and the only variable is MFI + freq = (mfi ? 480000000 : 440000000); + break; + default: // Other values are not allowed + freq = 0; + } + + arm_clk_div = ccm->cacrr & CYGHWR_HAL_VYBRID_CCM_CACRR_ARM_CLK_DIV_M; + arm_clk_div = (arm_clk_div >> CYGHWR_HAL_VYBRID_CCM_CACRR_ARM_CLK_DIV_S) + 1; + bus_clk_div = ccm->cacrr & CYGHWR_HAL_VYBRID_CCM_CACRR_BUS_CLK_DIV_M; + bus_clk_div = (bus_clk_div >> CYGHWR_HAL_VYBRID_CCM_CACRR_BUS_CLK_DIV_S) + 1; + + freq /= arm_clk_div; // now we have a CA5 clock + freq /= bus_clk_div; // and now we have a CM4 clock + + return freq; +} + +//========================================================================== +// UART baud rate +// +// Set the baud rate divider of a UART based on the requested rate and +// the current clock settings. + + +void +hal_freescale_uart_setbaud(cyg_uint32 uart_p, cyg_uint32 baud) +{ + cyg_uint32 sbr, brfa; + cyg_uint32 regval; + + sbr = hal_vybrid_busclk / (16 * baud); //VYBRID: only this is allowed as all uarts run on BUS Clock + + if(sbr) { + HAL_READ_UINT8(uart_p + CYGHWR_DEV_FREESCALE_UART_BDH, regval); + regval &= 0xE0; + regval |= sbr >> 8; + HAL_WRITE_UINT8(uart_p + CYGHWR_DEV_FREESCALE_UART_BDH, regval); + HAL_WRITE_UINT8(uart_p + CYGHWR_DEV_FREESCALE_UART_BDL, (sbr & 0xFF)); + brfa = (((32*hal_vybrid_busclk)/(16*baud))-(32*sbr)); + HAL_READ_UINT8(uart_p + CYGHWR_DEV_FREESCALE_UART_C4, regval); + regval &= 0xE0; + regval |= brfa & 0x1f; + HAL_WRITE_UINT8(uart_p + CYGHWR_DEV_FREESCALE_UART_C4, regval); + } +} + + +void +hal_update_clock_var(void) +{ + hal_vybrid_sysclk = hal_get_cpu_clock(); + hal_vybrid_busclk = hal_vybrid_sysclk / + 2; //TODO: place option for selecting CCM_CACRR[IPG_CLK_DIV] from CDL + hal_cortexm_systick_clock = hal_vybrid_sysclk; +} + + +cyg_uint32 +hal_get_peripheral_clock(void) +{ + return hal_vybrid_busclk; +} + +//========================================================================== +// EOF vybrid_clocking.c diff --git a/ecos/packages/hal/cortexm/vybrid/var/current/src/vybrid_misc.c b/ecos/packages/hal/cortexm/vybrid/var/current/src/vybrid_misc.c new file mode 100644 index 0000000..751b8c0 --- /dev/null +++ b/ecos/packages/hal/cortexm/vybrid/var/current/src/vybrid_misc.c @@ -0,0 +1,238 @@ +//========================================================================== +// +// vybrid_misc.c +// +// Cortex-M Vybrid HAL functions +// +//========================================================================== +// ####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2010, 2013 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later +// version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License +// along with eCos; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +// +// As a special exception, if other files instantiate templates or use +// macros or inline functions from this file, or you compile this file +// and link it with other works to produce a work based on this file, +// this file does not by itself cause the resulting work to be covered by +// the GNU General Public License. However the source code for this file +// must still be made available in accordance with section (3) of the GNU +// General Public License v2. +// +// This exception does not invalidate any other reasons why a work based +// on this file might be covered by the GNU General Public License. +// ------------------------------------------- +// ####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): Antmicro Ltd <contact@antmicro.com> +// Based on: {...}/hal/packages/cortexm/kinetis/var/current/include/kinetis_misc.h +// Date: 2014-03-28 +// Description: +// +//####DESCRIPTIONEND#### +// +//======================================================================== + + +#include <pkgconf/hal.h> +#include <pkgconf/hal_cortexm.h> +#include <pkgconf/hal_cortexm_vybrid.h> +#ifdef CYGPKG_KERNEL +#include <pkgconf/kernel.h> +#endif + +#include <cyg/infra/diag.h> +#include <cyg/infra/cyg_type.h> +#include <cyg/infra/cyg_trac.h> // tracing macros +#include <cyg/infra/cyg_ass.h> // assertion macros + +#include <cyg/hal/cortexm_endian.h> +#include <cyg/hal/hal_arch.h> // HAL header +#include <cyg/hal/hal_intr.h> // HAL header +#include <cyg/hal/hal_if.h> // HAL header + +#include <cyg/hal/hal_cache.h> + +#include <cyg/hal/var_io_gpio.h> +#include <assert.h> + +void sst25xx_freescale_dspi_reg(void); + +//========================================================================== +// Setup variant specific hardware +//========================================================================= + + +const char vf61_pads[] ={ +// port A +NONE, NONE, NONE, NONE, NONE, NONE, PTA6, PTA7, +PTA8, PTA9, PTA10,PTA11,PTA12,NONE, NONE, NONE, +PTA16,PTA17,PTA18,PTA19,PTA20,PTA21,PTA22,PTA23, +PTA24,PTA25,PTA26,PTA27,PTA28,PTA29,PTA30,PTA31, +// port B +PTB0, PTB1, PTB2, PTB3, PTB4, PTB5, PTB6, PTB7, +PTB8, PTB9, PTB10,PTB11,PTB12,PTB13,PTB14,PTB15, +PTB16,PTB17,PTB18,PTB19,PTB20,PTB21,PTB22,PTB23, +PTB24,PTB25,PTB26,PTB27,PTB28,NONE, NONE, NONE, +// port C +PTC0, PTC1, PTC2, PTC3, PTC4, PTC5, PTC6, PTC7, +PTC8, PTC9, PTC10,PTC11,PTC12,PTC13,PTC14,PTC15, +PTC16,PTC17,NONE, NONE, NONE, NONE, NONE, NONE, +NONE, NONE, PTC26,PTC27,PTC28,PTC29,PTC30,PTC31, +// port D +PTD0, PTD1, PTD2, PTD3, PTD4, PTD5, PTD6, PTD7, +PTD8, PTD9, PTD10,PTD11,PTD12,PTD13,NONE, NONE, +PTD16,PTD17,PTD18,PTD19,PTD20,PTD21,PTD22,PTD23, +PTD24,PTD25,PTD26,PTD27,PTD28,PTD29,PTD30,PTD31, +// port E +PTE0, PTE1, PTE2, PTE3, PTE4, PTE5, PTE6, PTE7, +PTE8, PTE9, PTE10,PTE11,PTE12,PTE13,PTE14,PTE15, +PTE16,PTE17,PTE18,PTE19,PTE20,PTE21,PTE22,PTE23, +PTE24,PTE25,PTE26,PTE27,PTE28,NONE, NONE, NONE +}; + +void hal_variant_init( void ) +{ +#if defined CYGPKG_HAL_VYBRID_CACHE +# if defined CYG_HAL_STARTUP_RAM + register CYG_INTERRUPT_STATE oldints; +# endif +#endif + + hal_update_clock_var(); //VYBRID + +#if defined CYGPKG_HAL_VYBRID_CACHE +# if defined CYG_HAL_STARTUP_RAM + HAL_DISABLE_INTERRUPTS(oldints); + HAL_DCACHE_SYNC(); + HAL_DCACHE_DISABLE(); + HAL_DCACHE_PURGE_ALL(); + HAL_ICACHE_DISABLE(); + HAL_ICACHE_INVALIDATE_ALL(); +# endif // defined CYG_HAL_STARTUP_RAM +# if defined CYG_HAL_STARTUP_RAM + HAL_RESTORE_INTERRUPTS(oldints); +# endif +# ifdef CYGSEM_HAL_ENABLE_ICACHE_ON_STARTUP + HAL_ICACHE_ENABLE(); +# endif +# ifdef CYGSEM_HAL_ENABLE_DCACHE_ON_STARTUP + HAL_DCACHE_ENABLE(); +# endif +#endif // defined CYGPKG_HAL_VYBRID_CACHE + +#ifdef CYGSEM_HAL_VIRTUAL_VECTOR_SUPPORT + hal_if_init(); +#endif +} + +//========================================================================== +// Pin configuration functions +//========================================================================== + +static cyghwr_hal_vybrid_port_t * const Ports[] = { + CYGHWR_HAL_VYBRID_PORTA_P, CYGHWR_HAL_VYBRID_PORTB_P, + CYGHWR_HAL_VYBRID_PORTC_P, CYGHWR_HAL_VYBRID_PORTD_P, + CYGHWR_HAL_VYBRID_PORTE_P, CYGHWR_HAL_VYBRID_PORTF_P +}; + + +void +hal_set_pin_function(cyg_uint32 pin) +{ + if (pin==CYGHWR_HAL_VYBRID_PORT_PIN_NONE) return; + + cyg_uint32 func = CYGHWR_HAL_VYBRID_PIN_FUNC(pin); + cyg_uint32 pad = vf61_pads[CYGHWR_HAL_VYBRID_PIN_PORT(pin)*32+CYGHWR_HAL_VYBRID_PIN_BIT(pin)]; + + // pad must exist in the device + assert(pad != NONE); + + cyg_uint32 mux_val, mux_cnf; + + HAL_READ_UINT32(CYGHWR_HAL_VYBRID_GET_IOMUXC(pad),mux_val); + + mux_val &= 0xff8fffff; // clear the MUX_MODE + + mux_val |= ((func & 0xf00) << 12); //assign new MUX_MODE + + mux_cnf = pin & 0x0000003f; // extract cnf from pin definition + + if (mux_cnf) // non zero cnf assigned + { + mux_val &= 0xffffffc0; + mux_val |= mux_cnf; + } + + HAL_WRITE_UINT32(CYGHWR_HAL_VYBRID_GET_IOMUXC(pad),mux_val); +} + +void +hal_dump_pin_function(cyg_uint32 pin) +{ + if(pin == CYGHWR_HAL_VYBRID_PIN_NONE) return; + + cyg_uint32 port = CYGHWR_HAL_VYBRID_PIN_PORT(pin); + cyg_uint32 bit = CYGHWR_HAL_VYBRID_PIN_BIT(pin); + + cyg_uint32 pad = vf61_pads[CYGHWR_HAL_VYBRID_PIN_PORT(pin)*32+CYGHWR_HAL_VYBRID_PIN_BIT(pin)]; + cyg_uint32 mux_val; + HAL_READ_UINT32(CYGHWR_HAL_VYBRID_GET_IOMUXC(pad),mux_val); + diag_printf("Pin PT%c%d: IOMUX=0x08%x\n",0x41+port,bit,mux_val); +} + +//========================================================================== +// VYBRID Clock distribution +//========================================================================== + +void +hal_clock_enable(cyg_uint32 ccgr) +{ + volatile cyg_uint32 *ccm_p; + + if(ccgr != CYGHWR_HAL_CCGR_NONE) { + ccm_p = &CYGHWR_HAL_VYBRID_CCM_P->ccgr0 + + CYGHWR_HAL_VYBRID_CCM_CCGR_REG(ccgr); + *ccm_p |= 3 << CYGHWR_HAL_VYBRID_CCM_CCGR_BIT(ccgr); + } +} + +void +hal_clock_disable(cyg_uint32 ccgr) +{ + volatile cyg_uint32 *ccm_p; + + if(ccgr != CYGHWR_HAL_CCGR_NONE) { + ccm_p = &CYGHWR_HAL_VYBRID_CCM_P->ccgr0 + + CYGHWR_HAL_VYBRID_CCM_CCGR_REG(ccgr); + *ccm_p &= ~(3 << CYGHWR_HAL_VYBRID_CCM_CCGR_BIT(ccgr)); + } +} + +//========================================================================== +// VYBRID Misc functions +//========================================================================== + +int +hal_get_core_num(void) +{ + return CYGHWR_HAL_VYBRID_MSCM_CPxNUM & CYGHWR_HAL_VYBRID_MSCM_CPxNUM_CPN_M; +} + +//========================================================================== +// EOF vybrid_misc.c |