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| author | Peter Griffin <peter.griffin@linaro.org> | 2026-09-11 21:21:05 +0000 |
|---|---|---|
| committer | Will Deacon <will@kernel.org> | 2026-10-02 15:24:08 +0000 |
| commit | 87098700b3cb953d0a2ccd1946ca01853b22e783 (patch) | |
| tree | b4d99ea9133f52438aa52b8abbfac601b8fa11ad | |
| parent | 93f51579e7df248780214094418f205253383cc5 (diff) | |
dt-bindings: iommu: arm,smmu-v3: Add arm,instdata-override property
arm,instdata-override DT property is intended to be used for SMMUs that
have a silicon integration issue with the AxPROT[2] signal always being 1
making all transactions appear as instructions.
Google Tensor G5 (Laguna) is an example of an SoC with this silicon
erratum. The DT property can be specified to enable a software
workaround which overrides the incoming attribute to data.
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Will Deacon <will@kernel.org>
| -rw-r--r-- | Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml b/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml index 82957334bea2..3c044e4f03d4 100644 --- a/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml +++ b/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml @@ -83,6 +83,16 @@ properties: register access with page 0 offsets. Set for Cavium ThunderX2 silicon that doesn't support SMMU page1 register space. + arm,instdata-override: + type: boolean + description: + Some SoCs like Google Tensor G5 (Laguna) have an SMMU integration + silicon erratum where AxPROT[2] signal is always 1, making all + transactions appear as instructions. + + This property enables a software workaround to override the + instruction/data attribute of incoming traffic to data. + allOf: - if: not: |