diff options
| author | Mukul Joshi <mukul.joshi@amd.com> | 2025-03-27 17:17:06 -0400 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2025-12-08 14:25:34 -0500 |
| commit | e3b8d8cc8c60db6c2be1251664da68b3e021a672 (patch) | |
| tree | a13e35d8dbfa0661e819bb26a0640249fff848ce /drivers/gpu/drm/amd/include | |
| parent | 3849efdc7888d537f09c3dcfaea4b3cd377a102e (diff) | |
drm/amdgpu: Fix SHMEM alignment mode for GFX 12.1.0
Alignment mode in SHMEM config register is only a single bit
value on GFX 12.1.0 instead of 2 bits in previous asics.
Add a new enum and use the correct value of SHMEM alignment mode
when programming the SHMEM config register.
Signed-off-by: Mukul Joshi <mukul.joshi@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/include')
| -rw-r--r-- | drivers/gpu/drm/amd/include/soc_v1_0_enum.h | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/include/soc_v1_0_enum.h b/drivers/gpu/drm/amd/include/soc_v1_0_enum.h index 5a0963eaf3b9..2a910785334d 100644 --- a/drivers/gpu/drm/amd/include/soc_v1_0_enum.h +++ b/drivers/gpu/drm/amd/include/soc_v1_0_enum.h @@ -30,4 +30,9 @@ typedef enum MTYPE { MTYPE_UC = 0x00000003, } MTYPE; +typedef enum SH_MEM_ALIGNMENT_MODE { + SH_MEM_ALIGNMENT_MODE_DWORD = 0x00000000, + SH_MEM_ALIGNMENT_MODE_UNALIGNED = 0x00000001, +} SH_MEM_ALIGNMENT_MODE; + #endif |