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authorOtavio Salvador <otavio@ossystems.com.br>2025-10-01 18:26:47 -0300
committerGitHub <noreply@github.com>2025-10-01 18:26:47 -0300
commit925d4ff9b529f1521bfb34f01c54dfe6d6f21dc9 (patch)
tree0bbc6b039eeea3bb41830ab730b53913a88e2419 /drivers/iio/adc/rockchip_saradc.c
parent49f4ca7b487f42e14af67a5235bd806fb93c27f8 (diff)
parent09c71a76accc2f1c288f79beb68939f897c20690 (diff)
Merge pull request #744 from angolini/lf-6.12.20-2.0.0_up_6.12.49toradex_6.12-2.0.x-imx
Lf 6.12.20 2.0.0 up 6.12.49
Diffstat (limited to 'drivers/iio/adc/rockchip_saradc.c')
-rw-r--r--drivers/iio/adc/rockchip_saradc.c17
1 files changed, 8 insertions, 9 deletions
diff --git a/drivers/iio/adc/rockchip_saradc.c b/drivers/iio/adc/rockchip_saradc.c
index dfd47a6e1f4a..e4dcd9e782af 100644
--- a/drivers/iio/adc/rockchip_saradc.c
+++ b/drivers/iio/adc/rockchip_saradc.c
@@ -480,15 +480,6 @@ static int rockchip_saradc_probe(struct platform_device *pdev)
if (info->reset)
rockchip_saradc_reset_controller(info->reset);
- /*
- * Use a default value for the converter clock.
- * This may become user-configurable in the future.
- */
- ret = clk_set_rate(info->clk, info->data->clk_rate);
- if (ret < 0)
- return dev_err_probe(&pdev->dev, ret,
- "failed to set adc clk rate\n");
-
ret = regulator_enable(info->vref);
if (ret < 0)
return dev_err_probe(&pdev->dev, ret,
@@ -515,6 +506,14 @@ static int rockchip_saradc_probe(struct platform_device *pdev)
if (IS_ERR(info->clk))
return dev_err_probe(&pdev->dev, PTR_ERR(info->clk),
"failed to get adc clock\n");
+ /*
+ * Use a default value for the converter clock.
+ * This may become user-configurable in the future.
+ */
+ ret = clk_set_rate(info->clk, info->data->clk_rate);
+ if (ret < 0)
+ return dev_err_probe(&pdev->dev, ret,
+ "failed to set adc clk rate\n");
platform_set_drvdata(pdev, indio_dev);