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| author | Dave Jiang <dave.jiang@intel.com> | 2026-01-23 14:13:16 -0700 |
|---|---|---|
| committer | Dave Jiang <dave.jiang@intel.com> | 2026-01-23 14:13:16 -0700 |
| commit | 3f7938b1aec7f06d5b23adca83e4542fcf027001 (patch) | |
| tree | 605f16cebb3c737fcd6ccd29669ad922489ee9b9 /scripts | |
| parent | 914c743509d56067eeeb2b5e341a44a68ef8377d (diff) | |
| parent | bc62f5b308cbdedf29132fe96e9d591e526527e1 (diff) | |
Merge branch 'for-7.0/cxl-init' into cxl-for-next
Merge in patches to support several patch series such as Soft Reserve
handling, type2 accelerator enabling, and LSA 2.1 labeling support.
Mainly addition of cxl_memdev_attach() to allow the memdev probe
to make a decision of proceed/fail depending success of CXL topology
enumeration.
dax/hmem, e820, resource: Defer Soft Reserved insertion until hmem is ready
cxl/mem: Introduce cxl_memdev_attach for CXL-dependent operation
cxl/mem: Drop @host argument to devm_cxl_add_memdev()
cxl/mem: Convert devm_cxl_add_memdev() to scope-based-cleanup
cxl/port: Arrange for always synchronous endpoint attach
cxl/mem: Arrange for always-synchronous memdev attach
cxl/mem: Fix devm_cxl_memdev_edac_release() confusion
Diffstat (limited to 'scripts')
0 files changed, 0 insertions, 0 deletions