drm/i915/cmtg: Disable CMTG after encoder disable in hsw_crtc_disable()

hsw_crtc_disable() disables CMTG at the very start of the CRTC disable
sequence, before intel_encoders_disable(). With this ordering, the wait
for CMTG_STATE to clear after CMTG_ENABLE is cleared intermittently
times out:

  xe 0000:00:02.0: [drm] CMTG: A disable timeout
  WARNING: drivers/gpu/drm/i915/display/intel_cmtg.c:205 intel_cmtg_disable+0x331/0x3d0 [xe]

This is seen with igt@kms_hdr@bpc-switch-suspend, which repeatedly
disables and re-enables the eDP across modesets and suspend/resume.

Move the CMTG disable after intel_encoders_disable(), so the eDP-side
teardown (panel unprepare, ALPM disable, backlight off) has completed,
but keep it before intel_encoders_post_disable() and
intel_dpll_disable(). The transcoder timing generator, DDI buffer and
port PLL are therefore still running while CMTG_STATE is polled, and
the requirement to disable CMTG before the transcoder and the port PLL
feeding it are turned off is preserved.

v2:
- Modify commit description regarding PSR exit. [Dibin]
- Add fixes tag. [Jani, Dibin]
v3:
- Add a cover letter with links to v1 and v2 for the review
  history. [Dibin]

Fixes: c588a324183b ("drm/i915/cmtg: Add trigger to enable/disable cmtg")
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
Reviewed-by: Dibin Moolakadan Subrahmanian <dibin.moolakadan.subrahmanian@intel.com>
Link: https://patch.msgid.link/20261026082906.802048-2-animesh.manna@intel.com
(cherry picked from commit f85fb6e8fd6cf7802285ccd2dbcb631efca8303f)
Signed-off-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>

0 files changed, 0 insertions, 0 deletions