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2026-03-10arm64: dts: exynos8895: Move I2C address/size-cells to DTSIKrzysztof Kozlowski
Convention followed in all other DTSI files is to define I2C controller address/size-cells in the DTSI thus reducing code needed in each DTS. It's also logical, since I2C is a bus and needs definition of addressing children, even if the bus is enabled without the nodes. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://patch.msgid.link/20260305-dts-exynos-i2c-v1-2-2c8d3df3b9ca@oss.qualcomm.com Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
2026-03-10arm64: dts: exynos7870: Move I2C address/size-cells to DTSIKrzysztof Kozlowski
Convention followed in all other DTSI files is to define I2C controller address/size-cells in the DTSI thus reducing code needed in each DTS. It's also logical, since I2C is a bus and needs definition of addressing children, even if the bus is enabled without the nodes. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://patch.msgid.link/20260305-dts-exynos-i2c-v1-1-2c8d3df3b9ca@oss.qualcomm.com Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
2026-03-07arm64: dts: exynos: gs101-pixel-common: add Maxim MAX77759 fuel gaugeAndré Draszik
On Pixel 6 (and Pro), a MAX77759 companion PMIC for USB Type-C applications is used, which contains four functional blocks (at distinct I2C addresses): * top (including GPIO & NVMEM) * charger * fuel gauge * TCPCi This change adds the fuel gauge. Reviewed-by: Peter Griffin <peter.griffin@linaro.org> Tested-by: Peter Griffin <peter.griffin@linaro.org> Signed-off-by: André Draszik <andre.draszik@linaro.org> Link: https://patch.msgid.link/20260302-max77759-fg-dts-v2-1-12f1109a6fee@linaro.org Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
2026-03-05arm64: dts: exynos: add initial support for Samsung Galaxy J5Andras Sebok
Add initial devicetree support for Samsung Galaxy J5 (2017) using Exynos7870 SoC. Signed-off-by: Andras Sebok <sebokandris2009@gmail.com> Signed-off-by: Kaustabh Chakraborty <kauschluss@disroot.org> Link: https://patch.msgid.link/20260304-exynos7870-j5y17lte-v1-2-eb25902c84c8@disroot.org [krzk: Rephrase commit msg] Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
2026-02-28arm64: dts: exynosautov920: add CMU_G3D clock DT nodesRaghav Sharma
Add required dt node for cmu_g3d block, which provides clocks for G3D IP Signed-off-by: Raghav Sharma <raghav.s@samsung.com> Link: https://patch.msgid.link/20260202103555.2089376-4-raghav.s@samsung.com Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
2026-02-28arm64: dts: exynos: gs101-pixel: add all S2MPG1x regulatorsAndré Draszik
Most rails are the same between Pixel 6 and Pro, with the following differences: * only Pro has UWB * Pro uses l2m, not l14m, for TCXO * Pro uses bucka, not l31m, for NFC Signed-off-by: André Draszik <andre.draszik@linaro.org> Link: https://patch.msgid.link/20260210-s2mpg1x-regulators-dts-v2-1-68783c9e0a32@linaro.org Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
2026-02-26arm64: dts: exynos: add initial support for Samsung Galaxy J7 (2016)Rayan Marzouk
Add initial devicetree support for Samsung Galaxy J7 (2016) (codename: j7xelte), an Exynos7870 device. Signed-off-by: Rayan Marzouk <rayanmarzouk743@gmail.com> Signed-off-by: Kaustabh Chakraborty <kauschluss@disroot.org> Link: https://patch.msgid.link/20260125-exynos7870-j7xelte-v1-2-5cacc3042c42@disroot.org Link: https://lore.kernel.org/r/DGNRDQ5886K7.3NSLKILM1GDWR@disroot.org/ Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
2026-02-24arm64: dts: axis: artpec9: Fix missing soc unit addressKrzysztof Kozlowski
Fix W=1 build warning to comply with Samsuung SoC maintainer profile: artpec9.dtsi:121.11-268.4: Warning (unit_address_vs_reg): /soc: node has a reg or ranges property, but no unit name Fixes: 3ae2b7442cb8 ("arm64: dts: exynos: axis: Add initial ARTPEC-9 SoC support") Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://patch.msgid.link/20260224122739.95168-2-krzysztof.kozlowski@oss.qualcomm.com Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
2026-02-24arm64: dts: axis: Add ARTPEC-9 Alfred board supportRavi Patel
Add initial devcie tree for the ARTPEC-9 Alfred board. The ARTPEC-9 Alfred is a board developed by Axis, based on the Axis ARTPEC-9 SoC. Signed-off-by: SungMin Park <smn1196@coasia.com> Signed-off-by: Ravi Patel <ravi.patel@samsung.com> Link: https://patch.msgid.link/20251119131302.79088-4-ravi.patel@samsung.com Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
2026-02-24arm64: dts: exynos: axis: Add initial ARTPEC-9 SoC supportSungMin Park
Add initial device tree support for Axis ARTPEC-9 SoC. This SoC contains 6 Cortex-A55 CPUs and several other peripheral IPs. Signed-off-by: SungMin Park <smn1196@coasia.com> Signed-off-by: Ravi Patel <ravi.patel@samsung.com> Link: https://patch.msgid.link/20251119131302.79088-3-ravi.patel@samsung.com Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
2026-01-17arm64: dts: exynos: gs101: add cmu_dpu and sysreg_dpu dt nodesPeter Griffin
Enable the cmu_dpu clock management unit. It feeds some of the display IPs. Additionally add the sysreg_dpu node which contains the BUSCOMPONENT_DRCG_EN and MEMCLK registers required by cmu_dpu to enable dynamic root clock gating of bus components. Reviewed-by: André Draszik <andre.draszik@linaro.org> Signed-off-by: Peter Griffin <peter.griffin@linaro.org> Link: https://patch.msgid.link/20260113-dpu-clocks-v3-5-cb85424f2c72@linaro.org Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
2025-12-28arm64: dts: exynos: gs101: add OTP nodeTudor Ambarus
Add the OTP controller node. Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org> Reviewed-by: André Draszik <andre.draszik@linaro.org> Link: https://patch.msgid.link/20251222-gs101-chipid-v4-5-aa8e20ce7bb3@linaro.org Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
2025-12-22arm64: dts: exynos: gs101: add samsung,sysreg property to CMU nodesPeter Griffin
With the exception of cmu_top, each CMU has a corresponding sysreg bank that contains the BUSCOMPONENT_DRCG_EN and optional MEMCLK registers. The BUSCOMPONENT_DRCG_EN register enables dynamic root clock gating of bus components and MEMCLK gates the sram clock. Now the clock driver supports automatic clock mode, provide the samsung,sysreg property so the driver can enable dynamic root clock gating of bus components and gate sram clock. Note without the property specified the driver simply falls back to previous behaviour of not configuring these registers so it is not an ABI break. Signed-off-by: Peter Griffin <peter.griffin@linaro.org> Link: https://patch.msgid.link/20251222-automatic-clocks-v7-2-fec86fa89874@linaro.org Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
2025-12-21arm64: dts: exynosautov920: add CMU_MFD clock DT nodesRaghav Sharma
Add required dt node for cmu_mfd block, which provides clocks for MFD IP Signed-off-by: Raghav Sharma <raghav.s@samsung.com> Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com> Link: https://patch.msgid.link/20251119114744.1914416-4-raghav.s@samsung.com Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
2025-12-16arm64: dts: exynos: gs101: remove syscon compatible from pmu nodePeter Griffin
Since commit ba5095ebbc7a ("mfd: syscon: Allow syscon nodes without a "syscon" compatible") it is possible to register a regmap without the syscon compatible in the node. As mentioned in that commit, it's not correct to claim we are compatible with syscon, as a MMIO regmap created by syscon won't work. Removing the syscon compatible means syscon driver won't ever create a mmio regmap. Note this isn't usually an issue today as exynos-pmu runs at an early initcall so the custom regmap will have been registered first. However changes proposed in [1] will bring -EPROBE_DEFER support to syscon allowing this mechanism to be more robust, especially in highly modularized systems. Technically this is a ABI break but no other platforms are affected. Additionally (with the benefit of hindsight) a MMIO syscon has never worked for PMU register writes, thus the ABI break is justified. Link: https://lore.kernel.org/lkml/aQdHmrchkmOr34r3@stanley.mountain/ [1] Signed-off-by: Peter Griffin <peter.griffin@linaro.org> Link: https://patch.msgid.link/20251114-remove-pmu-syscon-compat-v2-2-9496e8c496c7@linaro.org Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
2025-12-16arm64: dts: exynos: gs101: add TRNG nodeTudor Ambarus
Define the TRNG node. GS101 TRNG works well with the current Exynos850 TRNG support. Specify the Google specific compatible in front of the Exynos one. Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org> Link: https://patch.msgid.link/20251024-gs101-trng-v3-2-5d3403738f39@linaro.org Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
2025-11-05arm64: dts: exynos7870-j6lte: enable display panel supportKaustabh Chakraborty
Enable DECON and DSI nodes, and add the compatible display panel and appropriate panel timings for this device. Also, remove the simple-framebuffer node in favor of the panel. This device has a 720x1480 AMOLED Samsung AMS561RA01 panel with S6E8AA5X01 controller. Signed-off-by: Kaustabh Chakraborty <kauschluss@disroot.org> Link: https://patch.msgid.link/20251031-exynos7870-drm-dts-v4-5-c1f77fb16b87@disroot.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2025-11-05arm64: dts: exynos7870-a2corelte: enable display panel supportKaustabh Chakraborty
Enable DECON and DSI nodes, and add the compatible display panel and appropriate panel timings for this device. Also, remove the simple-framebuffer node in favor of the panel. This device has a 540x960 Synaptics TD4101 display panel. Signed-off-by: Kaustabh Chakraborty <kauschluss@disroot.org> Link: https://patch.msgid.link/20251031-exynos7870-drm-dts-v4-4-c1f77fb16b87@disroot.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2025-11-05arm64: dts: exynos7870-on7xelte: enable display panel supportKaustabh Chakraborty
Enable DECON and DSI nodes, and add the compatible display panel and appropriate panel timings for this device. Also, remove the simple-framebuffer node in favor of the panel. This device has a 1080x1920 Synaptics TD4300 display panel. Signed-off-by: Kaustabh Chakraborty <kauschluss@disroot.org> Link: https://patch.msgid.link/20251031-exynos7870-drm-dts-v4-3-c1f77fb16b87@disroot.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2025-11-05arm64: dts: exynos7870: add DSI supportKaustabh Chakraborty
Add devicetree nodes for MIPI PHYs, Samsung's DECON and DSIM blocks, and DECON IOMMU devicetree nodes. Enables SoC support for hardware to be able to drive a MIPI DSI display. Signed-off-by: Kaustabh Chakraborty <kauschluss@disroot.org> Link: https://patch.msgid.link/20251031-exynos7870-drm-dts-v4-2-c1f77fb16b87@disroot.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2025-10-21arm64: dts: exynos: gs101: fix sysreg_apm reg propertyPeter Griffin
Both the start address and size are incorrect for the apm_sysreg DT node. Update to match the TRM (rather than how it was defined downstream). Fixes: ea89fdf24fd9 ("arm64: dts: exynos: google: Add initial Google gs101 SoC support") Signed-off-by: Peter Griffin <peter.griffin@linaro.org> Reviewed-by: André Draszik <andre.draszik@linaro.org> Link: https://patch.msgid.link/20251013-automatic-clocks-v1-5-72851ee00300@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2025-10-21arm64: dts: exynos: gs101: fix clock module unit reg sizesPeter Griffin
The memory map lists each clock module unit as having a size of 0x10000. Additionally there are some undocumented registers in this region that need to be used for automatic clock gating mode. Some of those registers also need to be saved/restored on suspend & resume. Fixes: 86124c76683e ("arm64: dts: exynos: gs101: enable cmu-hsi2 clock controller") Fixes: 4982a4a2092e ("arm64: dts: exynos: gs101: enable cmu-hsi0 clock controller") Fixes: 7d66d98b5bf3 ("arm64: dts: exynos: gs101: enable cmu-peric1 clock controller") Fixes: e62c706f3aa0 ("arm64: dts: exynos: gs101: enable cmu-peric0 clock controller") Fixes: ea89fdf24fd9 ("arm64: dts: exynos: google: Add initial Google gs101 SoC support") Signed-off-by: Peter Griffin <peter.griffin@linaro.org> Reviewed-by: André Draszik <andre.draszik@linaro.org> Link: https://patch.msgid.link/20251013-automatic-clocks-v1-4-72851ee00300@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2025-10-21arm64: dts: exynos: gs101: add sysreg_misc and sysreg_hsi0 nodesPeter Griffin
Add syscon DT node for the hsi0 and misc sysreg controllers. These will be referenced by their respective CMU nodes in future patches. Signed-off-by: Peter Griffin <peter.griffin@linaro.org> Reviewed-by: André Draszik <andre.draszik@linaro.org> Link: https://patch.msgid.link/20251013-automatic-clocks-v1-3-72851ee00300@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2025-10-20arm64: dts: exynos: gs101: add OPPsTudor Ambarus
Add operating performance points (OPPs). Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org> Reviewed-by: Peter Griffin <peter.griffin@linaro.org> Tested-by: Peter Griffin <peter.griffin@linaro.org> # on gs101-oriole Link: https://patch.msgid.link/20250924-acpm-dvfs-dt-v4-3-3106d49e03f5@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2025-10-20arm64: dts: exynos: gs101: add CPU clocksTudor Ambarus
Add the GS101 CPU clocks exposed through the ACPM protocol. Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org> Reviewed-by: Peter Griffin <peter.griffin@linaro.org> Tested-by: Peter Griffin <peter.griffin@linaro.org> # on gs101-oriole Link: https://patch.msgid.link/20250924-acpm-dvfs-dt-v4-2-3106d49e03f5@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2025-10-20arm64: dts: exynos: gs101: add #clock-cells to the ACPM protocol nodeTudor Ambarus
Make the ACPM node a clock provider by adding the mandatory "#clock-cells" property, which allows devices to reference its clock outputs. Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org> Reviewed-by: Peter Griffin <peter.griffin@linaro.org> Tested-by: Peter Griffin <peter.griffin@linaro.org> # on gs101-oriole Link: https://patch.msgid.link/20250924-acpm-dvfs-dt-v4-1-3106d49e03f5@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2025-10-13arm64: dts: exynos: gs101-pixel-common: add node for s2mpg10 / clockAndré Draszik
On Pixel 6 (and Pro), a Samsung S2MPG10 is used as main PMIC, which contains the following functional blocks: * common / speedy interface * regulators * 3 clock outputs * RTC * power meters This change adds a node for the clock outputs which are used as inputs as follows: * RTC clock for AP * GNSS receiver, WLAN, Bluetooth * vibrator, modem The names have been chosen to match the schematic. Signed-off-by: André Draszik <andre.draszik@linaro.org> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2025-10-13arm64: dts: exynos990: Add sysreg nodes for PERIC0 and PERIC1Denzeel Oliva
Add syscon nodes for PERIC0 and PERIC1 blocks. These are required for configuring the USI, SPI and I2C controllers. Signed-off-by: Denzeel Oliva <wachiturroxd150@gmail.com> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2025-10-13arm64: dts: exynosautov920: add CMU_MFC clock DT nodesRaghav Sharma
Add required dt node for CMU_MFC block, which provides clocks for MFC IP Signed-off-by: Raghav Sharma <raghav.s@samsung.com> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2025-10-13arm64: dts: exynosautov920: add CMU_M2M clock DT nodesRaghav Sharma
Add required dt node for CMU_M2M block, which provides clocks for M2M IP Signed-off-by: Raghav Sharma <raghav.s@samsung.com> Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2025-10-13arm64: dts: exynos7870-on7xelte: add bus-width to mmc0 nodeKaustabh Chakraborty
Add the bus-width property in &mmc0 node. The Exynos DWMMC driver assumes bus width to be 8 if not present in devicetree, so at least with respect to the Linux kernel, this doesn't introduce any functional changes. But other drivers referring to it may not. Either way, without the bus-width property the hardware description remains incomplete. Signed-off-by: Kaustabh Chakraborty <kauschluss@disroot.org> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2025-10-13arm64: dts: exynos7870-j6lte: add bus-width to mmc0 nodeKaustabh Chakraborty
Add the bus-width property in &mmc0 node. The Exynos DWMMC driver assumes bus width to be 8 if not present in devicetree, so at least with respect to the Linux kernel, this doesn't introduce any functional changes. But other drivers referring to it may not. Either way, without the bus-width property the hardware description remains incomplete. Signed-off-by: Kaustabh Chakraborty <kauschluss@disroot.org> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2025-10-13arm64: dts: exynos7870-a2corelte: add bus-width to mmc0 nodeKaustabh Chakraborty
Add the bus-width property in &mmc0 node. The Exynos DWMMC driver assumes bus width to be 8 if not present in devicetree, so at least with respect to the Linux kernel, this doesn't introduce any functional changes. But other drivers referring to it may not. Either way, without the bus-width property the hardware description remains incomplete. Signed-off-by: Kaustabh Chakraborty <kauschluss@disroot.org> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2025-09-07arm64: dts: exynos990: Enable PERIC0 and PERIC1 clock controllersDenzeel Oliva
Add clock controller nodes for PERIC0 and PERIC1 blocks for USI nodes. Signed-off-by: Denzeel Oliva <wachiturroxd150@gmail.com> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2025-09-04arm64: dts: axis: Add ARTPEC-8 Grizzly dts supportSeonGu Kang
Add initial devcie tree for the ARTPEC-8 Grizzly board. The ARTPEC-8 Grizzly is a small board developed by Axis, based on the Axis ARTPEC-8 SoC. Signed-off-by: SeonGu Kang <ksk4725@coasia.com> Signed-off-by: Ravi Patel <ravi.patel@samsung.com> Link: https://lore.kernel.org/r/20250901051926.59970-6-ravi.patel@samsung.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2025-09-04arm64: dts: exynos: axis: Add initial ARTPEC-8 SoC supportSungMin Park
Add initial device tree support for Axis ARTPEC-8 SoC. This SoC contains 4 Cortex-A53 CPUs and several other peripheral IPs. Signed-off-by: SungMin Park <smn1196@coasia.com> Signed-off-by: SeonGu Kang <ksk4725@coasia.com> Signed-off-by: Ravi Patel <ravi.patel@samsung.com> Link: https://lore.kernel.org/r/20250901051926.59970-5-ravi.patel@samsung.com Acked-by: Jesper Nilsson <jesper.nilsson@axis.com> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2025-09-03arm64: dts: exynos8895: Minor whitespace cleanupKrzysztof Kozlowski
The DTS code coding style expects exactly one space around '=' character. Link: https://lore.kernel.org/r/20250819131641.86520-2-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2025-08-31arm64: dts: exynos2200: Add default GIC address cellsKrzysztof Kozlowski
Add missing address-cells 0 to GIC interrupt node. Value '0' is correct because GIC interrupt controller does not have children. Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com> Link: https://lore.kernel.org/r/20250830093918.24619-2-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2025-08-30arm64: dts: google: gs101: Add default GIC address cellsKrzysztof Kozlowski
Add missing address-cells 0 to GIC interrupt node. Value '0' is correct because GIC interrupt controller does not have children. Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com> Link: https://lore.kernel.org/r/20250822121423.228500-6-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2025-08-30arm64: dts: exynos5433: Add default GIC address cellsKrzysztof Kozlowski
Add missing address-cells 0 to GIC interrupt node to silence W=1 warning: exynos5433-tm2-common.dtsi:1000.2-41: Warning (interrupt_map): /soc@0/pcie@15700000:interrupt-map: Missing property '#address-cells' in node /soc@0/interrupt-controller@11001000, using 0 as fallbac Value '0' is correct because: 1. GIC interrupt controller does not have children, 2. interrupt-map property (in PCI node) consists of five components and the fourth component "parent unit address", which size is defined by '#address-cells' of the node pointed to by the interrupt-parent component, is not used (=0). Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com> Link: https://lore.kernel.org/r/20250822121423.228500-5-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2025-08-30arm64: dts: exynos2200: define all usi nodesIvaylo Ivanov
Universal Serial Interface (USI) supports three types of serial interfaces - uart, i2c and spi. Each protocol can work independently and configured using external configuration inputs. As each USI instance has access to 4 pins, there are multiple possible configurations: - the first 2 and the last 2 pins can be i2c (sda/scl) or uart (rx/tx) - the 4 pins can be used for 4 pin uart or spi For each group of 4 pins, there is one usi instance that can access all 4 pins, and a second usi instance that can be used to set the last 2 pins in i2c mode. Such configuration can be achieved by setting the mode property of usiX and usiX_i2c nodes correctly - if usiX is set to take up 2 pins, then usiX_i2c can be set to take the other 2. If usiX is set for 4 pins, then usiX_i2c should be left disabled. Define all the USI nodes from peric0 (usi4), peric1 (usi7-10), peric2 (usi0-6, usi11) and cmgp (usi0-6_cmgp, 2 pin usi7_cmgp) blocks, as well as their respective uart and i2c subnodes. Suffix labels for blocks in CMGP instances with _cmgpX, and follow the naming conventions from the vendor kernel to avoid confusion. Spi support will be added later on. Signed-off-by: Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com> Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org> Link: https://lore.kernel.org/r/20250815070500.3275491-5-ivo.ivanov.ivanov1@gmail.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2025-08-30arm64: dts: exynos2200: increase the size of all sysconsIvaylo Ivanov
As IP cores are aligned by 0x10000, increase the size of all system register instances to the maximum (0x10000) to allow using accessing registers over the currently set limit. Suggested-by: Sam Protsenko <semen.protsenko@linaro.org> Signed-off-by: Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com> Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org> Link: https://lore.kernel.org/r/20250815070500.3275491-4-ivo.ivanov.ivanov1@gmail.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2025-08-30arm64: dts: exynos2200: use 32-bit address space for /socIvaylo Ivanov
All peripherals on this SoC are mapped under the 32-bit address space (0x0 -> 0x20000000), so enforce that. Suggested-by: Sam Protsenko <semen.protsenko@linaro.org> Signed-off-by: Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com> Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org> Link: https://lore.kernel.org/r/20250815070500.3275491-3-ivo.ivanov.ivanov1@gmail.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2025-08-30arm64: dts: exynos2200: fix typo in hsi2c23 bus pins labelIvaylo Ivanov
The '2' in 'hsi2c23' was missed while making the device tree. Fix that so we can properly reference the node. Signed-off-by: Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com> Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org> Link: https://lore.kernel.org/r/20250815070500.3275491-2-ivo.ivanov.ivanov1@gmail.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2025-08-13arm64: dts: exynos990-r8s: Enable USBIgor Belwon
Enable both the USB PHY as well as the DWC3 controller nodes. Since we do not have any PMIC for USB implemented yet, use dummy regulators until we do. Signed-off-by: Igor Belwon <igor.belwon@mentallysanemainliners.org> Link: https://lore.kernel.org/r/20250710-resends-july-exynos990-dt-v2-5-55033f73d1b0@mentallysanemainliners.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2025-08-13arm64: dts: exynos990-c1s: Enable USBIgor Belwon
Enable both the USB PHY as well as the DWC3 controller nodes. Since we do not have any PMIC for USB implemented yet, use dummy regulators until we do. Signed-off-by: Igor Belwon <igor.belwon@mentallysanemainliners.org> Link: https://lore.kernel.org/r/20250710-resends-july-exynos990-dt-v2-4-55033f73d1b0@mentallysanemainliners.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2025-08-13arm64: dts: exynos990-x1s-common: Enable USBIgor Belwon
The x1s family uses a shared USB configuration. Enable both the USB PHY as well as the DWC3 controller. Since we do not have any PMIC for USB implemented yet, use dummy regulators until we do. Signed-off-by: Igor Belwon <igor.belwon@mentallysanemainliners.org> Link: https://lore.kernel.org/r/20250710-resends-july-exynos990-dt-v2-3-55033f73d1b0@mentallysanemainliners.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2025-08-13arm64: dts: exynos990: Add USB nodesIgor Belwon
Add USB controller and USB PHY controller nodes for use in the Exynos990 SoC. This SoC supports USB full-speed, high-speed and super-speed modes. Due to the inability to test PIPE3, USB super-speed is not enabled, and the USB PHY is only configured for UTMI+ operation for now. Signed-off-by: Igor Belwon <igor.belwon@mentallysanemainliners.org> Link: https://lore.kernel.org/r/20250710-resends-july-exynos990-dt-v2-2-55033f73d1b0@mentallysanemainliners.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2025-08-13arm64: dts: exynos990: Enable watchdog timerIgor Belwon
Enable the two watchdog timer clusters (cl0, cl2) present on the Exynos990 SoC. Signed-off-by: Igor Belwon <igor.belwon@mentallysanemainliners.org> Link: https://lore.kernel.org/r/20250710-resends-july-exynos990-dt-v2-1-55033f73d1b0@mentallysanemainliners.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2025-08-13arm64: dts: exynos: Add Ethernet node for E850-96 boardSam Protsenko
The E850-96 board has a hard-wired LAN9514 chip which acts as a USB hub and Ethernet bridge. It's being discovered dynamically when the USB bus gets enumerated, but the corresponding Ethernet device tree node is still needed for the bootloader to pass the MAC address through. Add LAN9514 nodes as described in [1]. 'local-mac-address' property (in the 'ethernet' node) is used for MAC address handover from the bootloader to Linux. [1] Documentation/devicetree/bindings/net/microchip,lan95xx.yaml Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> Link: https://lore.kernel.org/r/20250731234532.12903-1-semen.protsenko@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
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