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2026-01-23arm64: dts: a7k: add COM Express boardsElad Nachman
Add support for Armada 7020 Express Type 7 CPU module board by Marvell. Define this COM Express CPU module as dtsi and provide a dtsi file for the carrier board (Marvell DB-98CX85x0 COM Express type 7 carrier board). Since memory is soldered on CPU module, memory node is on CPU module dtsi file. This Carrier board only utilizes the PCIe link, hence no special device or driver support is provided by this dtsi file. Devise a dts file for the combined com express carrier and CPU module. The Aramda 7020 CPU COM Express board offers the following features: 1. Armada 7020 CPU, with dual ARM A72 cores 2. DDR4 memory, 8GB, on board soldered 3. 1Gbit Out of Band Ethernet via RGMII to PHY and RJ45 connector, all are present on A7K CPU module (none on the carrier) 4. Optional 10G KR Ethernet going via the COM Express type 7 connector 5. On-board 8 Gbit, 8-bit bus width NAND flash 6. On-board 512 Mbit SPI flash 7. PCIe Root Complex, 4 lanes PCIe gen3 connectivity, going via the COM Express type 7 connector 8. m.2 SATA connector 9. Micro-SD card connector 10. USB 2.0 via COM Express type 7 connector 11. Two i2c interfaces - one to the CPU module, and one to the carrier board via the COM Express type 7 connector 12. UART (mini USB connector by virtue of FT2232D UART to USB converter, connected to the Armada 7020 UART0) gc: 10gbase-kr is legacy, use "10gbase-r" instead in cp0_eth0 node Signed-off-by: Elad Nachman <enachman@marvell.com> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2026-01-22arm64: dts: marvell: Add SoC specific compatibles to SafeXcel cryptoAngeloGioacchino Del Regno
Following the changes in the binding for the SafeXcel crypto engine, add SoC specific compatibles to the existing nodes in Armada 37xx and CP11x. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2026-01-07arm64: dts: marvell: change regulator-gpio to regulator-fixedRob Herring (Arm)
A "regulator-gpio" must have a GPIO control, hence the name. There's no GPIO on a couple of Marvell platforms at least as far as the DT is defined, so change the regulator type from GPIO to fixed. Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2026-01-07arm64: dts: marvell: cn9131-cf-solidwan: Add missing GPIO properties on ↵Rob Herring (Arm)
"nxp,pca9536" The PCA9536 is always a GPIO provider, so add the missing properties. Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2026-01-07arm64: dts: marvell: Fix stray and typo "pinctrl-names" propertiesRob Herring (Arm)
There's several cases of "pinctrl-names" used without any "pinctrl-0" properties. Drop them. Fix the typo "pintrl-names" as well. Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2026-01-07arm64: dts: marvell: Add missing "#phy-cells" to "usb-nop-xceiv"Rob Herring (Arm)
The "usb-nop-xceiv" binding requires "#phy-cells" property with a value of 0 though it is not really used. Add it where missing from Marvell platforms. Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2025-11-21Merge tag 'mvebu-dt64-6.19-1' of ↵Arnd Bergmann
git://git.kernel.org/pub/scm/linux/kernel/git/gclement/mvebu into soc/dt mvebu dt64 for 6.19 (part 1) pinctrl node names cleanup from Rob on Marvell device tree files Proper fix for pci errors on armada cp11x based platforms * tag 'mvebu-dt64-6.19-1' of git://git.kernel.org/pub/scm/linux/kernel/git/gclement/mvebu: clk: mvebu: cp110 add CLK_IGNORE_UNUSED to pcie_x10, pcie_x11 & pcie_x4 Revert "arm64: dts: marvell: cn9132-clearfog: fix multi-lane pci x2 and x4 ports" arm64/arm: dts: marvell: Rename "nand-rb" pinctrl node names Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2025-11-10Revert "arm64: dts: marvell: cn9132-clearfog: fix multi-lane pci x2 and x4 ↵Josua Mayer
ports" This reverts commit 794a066688038df46c01e177cc6faebded0acba4 because it misunderstood interworking between arm trusted firmware and the common phy driver, and does not consistently resolve the issue it was intended to address. Further diagnostics have revealed the root cause for the reported system lock-up in a race condition between pci driver probe and clock core disabling unused clocks. Revert the wrong change restoring driver control over all pci lanes. As a temporary workaround for the original issue, users can boot with "clk_ignore_unused". Signed-off-by: Josua Mayer <josua@solid-run.com> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2025-11-10arm64/arm: dts: marvell: Rename "nand-rb" pinctrl node namesRob Herring (Arm)
Update the "nand-rb" pinctrl child node names to use the defined "-pins" suffix fixing DT schema warnings. Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2025-10-13arm64: dts: marvell: pxa1908: Add power domainsDuje Mihanović
Update the APMU clock controller's compatible to allow the new power domain driver to probe. Also add the first two power domain consumers: IOMMU (fixes probing) and framebuffer. Signed-off-by: Duje Mihanović <duje@dujemihanovic.xyz>
2025-10-13arm64: dts: marvell: samsung,coreprimevelte: Add USB connectorDuje Mihanović
Add a node for the micro-USB connector found on the board. Signed-off-by: Duje Mihanović <duje@dujemihanovic.xyz>
2025-10-13arm64: dts: marvell: samsung,coreprimevelte: Fill in memory nodeDuje Mihanović
The board is known to have 1 GiB of DRAM with the first 16 MiB unusable. Instead of relying on the bootloader to fill in the memory node, do it ourselves. Signed-off-by: Duje Mihanović <duje@dujemihanovic.xyz>
2025-10-13arm64: dts: marvell: samsung,coreprimevelte: Drop some reserved memoryDuje Mihanović
Most of the memory marked as reserved is actually usable. Delete its reserved-memory nodes so that the memory can be used. Signed-off-by: Duje Mihanović <duje@dujemihanovic.xyz>
2025-10-13arm64: dts: marvell: pxa1908: Move ramoops to SoC dtsiDuje Mihanović
The ramoops memory region is the same for all boards based on the SoC. Move its node to the appropriate dtsi. Signed-off-by: Duje Mihanović <duje@dujemihanovic.xyz>
2025-10-13arm64: dts: marvell: samsung,coreprimevelte: Add vibratorDuje Mihanović
The board has a vibrator hooked up to PWM3. Add a node for it and its associated pinctrl configuration. Signed-off-by: Duje Mihanović <duje@dujemihanovic.xyz>
2025-10-13arm64: dts: marvell: pxa1908: Add PWMsDuje Mihanović
The SoC has 4 onboard PWMs. Add a node for each of them. Signed-off-by: Duje Mihanović <duje@dujemihanovic.xyz>
2025-10-13arm64: dts: marvell: samsung,coreprimevelte: Enable eMMCDuje Mihanović
Commit a41fcca4b342 ("mmc: sdhci-pxav3: set NEED_RSP_BUSY capability") fixed eMMC probing on this board. Enable the eMMC and add its pinctrl. Signed-off-by: Duje Mihanović <duje@dujemihanovic.xyz>
2025-10-13arm64: dts: marvell: samsung,coreprimevelte: Correct CD GPIODuje Mihanović
Right now, the CD GPIO is defined as active high with a cd-inverted property. Just define the GPIO as active low instead. Signed-off-by: Duje Mihanović <duje@dujemihanovic.xyz>
2025-10-13arm64: dts: marvell: samsung,coreprimevelte: Add backlightDuje Mihanović
Add a node for the KTD2801 backlight chip found on the board. Signed-off-by: Duje Mihanović <duje@dujemihanovic.xyz>
2025-10-13arm64: dts: samsung,coreprimevelte: add SDIOKarel Balej
Set some basic properties of the SDIO card of the samsung,coreprimevelte smartphone. The SDIO is used as an interface for WiFi, Bluetooth and FM radio serviced by the Marvell 88W8777 (SD8777) chipset. Support for this chipset is currently not in-tree because the firmware is not available in linux-firmware, however it is possible to trivially run it out-of-tree using the mwifiex and Marvell Bluetooth drivers with some caveats. Link: https://lore.kernel.org/r/20231029111807.19261-1-balejk@matfyz.cz/ Signed-off-by: Karel Balej <balejk@matfyz.cz> Reviewed-by: Duje Mihanović <duje@dujemihanovic.xyz> [Duje: fix formatting of pins_0 and fast_pins_1 pin arrays] Signed-off-by: Duje Mihanović <duje@dujemihanovic.xyz>
2025-10-13arm64: dts: samsung,coreprimevelte: add touchscreenKarel Balej
Bind touchscreen for the samsung,coreprimevelte smartphone. The downstream code sets the VDD voltage to the exact value of 3.1 V, however it's been empirically verified that the lower bound used here sufficies for the proper operation of the chip and is thus used for power-saving purposes. Signed-off-by: Karel Balej <balejk@matfyz.cz> Reviewed-by: Duje Mihanović <duje@dujemihanovic.xyz> Signed-off-by: Duje Mihanović <duje@dujemihanovic.xyz>
2025-10-13arm64: dts: samsung,coreprimevelte: add PMICKarel Balej
Bind power management chip to the samsung,coreprimevelte smartphone. This enables support for onkey and RTC as well as for regulators two of which are explicitly bound here to the SD card. Signed-off-by: Karel Balej <balejk@matfyz.cz> Reviewed-by: Duje Mihanović <duje@dujemihanovic.xyz> Signed-off-by: Duje Mihanović <duje@dujemihanovic.xyz>
2025-10-01Merge tag 'soc-dt-6.18' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/socLinus Torvalds
Pull SoC dt updates from Arnd Bergmann: "There are five sets of new SoCs that get added in existing families, all of them being either upgrades or cut-down versions of the older chips: - Apple M2 Pro, M2 Max and M2 Ultra, used in the 2022/2023 generation of high-end workstations and laptops from Apple. Linux has been working on these for a while but stil requires patches. - Axis Artpec8 is an Armv8 chip based on Samsung Exynos design, unlike the earlier Armv7 Artpec6 from the same company that was part of a separate family of chips. - NXP i.MX91 is a cut-down version of i.MX93, using only a single Cortex-A55 core. - Qualcomm Lemans Auto is a variant of the Lemans SoC that was originally merged under the sa8775p name, the differences being mostly the firmware configuration of the platform. - Four new Renesas SoCs RZ/T2H (r9a09g077m44), RZ/N2H (r9a09g087m44), RZ/T2H (r9a09g077), and RZ/N2H (r9a09g087) are all industrial bedded SoCs based on Cortex-A55 cores In total, there are 65 new machines, including: - Industrial embedded system and single-board computers based on NXP, Allwinner, TI, Rockchips, Marvell, Xilinx Spacemit, Starfive chips. - Reference boards for the newly added Renesas, Qualcomm, NXP and Axis ARMv8 chips as well as Microchip's MPFS RISC-V SoC - Laptops and Workstations using Apple M2 and Qualcomm Snapdragon X1 chips. - Several Samsung phones using Qualcomm Snapdragon chips - Set-top boxes based on Allwinner H313 - Five BMC boards using 32-bit ASpeed SoCs - Three network routers using IXP4xx (ARMv5!) and Broadcom bcm4708 (ARMv7) SoCs Two machines get phased out because they were available only in small quantities but never made it into products: one STi407 based reference board, and a Snapdragon 845 based Chromebook. Aside from the newly added machines, a lot of work went into improving hardware support on the existing machines and cleaning up contents for validation" * tag 'soc-dt-6.18' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (931 commits) arm64: dts: apm-shadowcat: Drop "apm,xgene2-pcie" compatible arm64: dts: apm-shadowcat: Move slimpro nodes out of "simple-bus" node ARM: dts: microchip: sam9x7: Add qspi controller arm64: dts: qcom: Add MST pixel streams for displayport arm64: dts: qcom: sm6350: correct DP compatibility strings arm64: dts: qcom: monaco-evk: Enable Adreno 623 GPU arm64: dts: qcom: qcs8300-ride: Enable Adreno 623 GPU arm64: dts: qcom: qcs8300: Add gpu and gmu nodes arm64: dts: allwinner: h313: Add Amediatech X96Q dt-bindings: arm: sunxi: Add Amediatech X96Q arm64: dts: apple: t8015: Add SPMI node arm64: dts: apple: t8012: Add SPMI node arm64: dts: apple: Add J180d (Mac Pro, M2 Ultra, 2023) device tree arm64: dts: rockchip: Add devicetree for the ROC-RK3588-RT dt-bindings: arm: rockchip: Add Firefly ROC-RK3588-RT arm64: dts: rockchip: update pinctrl names for Radxa E52C arm64: dts: rockchip: remove vcc_3v3_pmu regulator for Radxa E52C arm64: dts: apple: Add J474s, J475c and J475d device trees arm64: dts: apple: Add J414 and J416 Macbook Pro device trees arm64: dts: apple: Add initial t6020/t6021/t6022 DTs ...
2025-09-12arm64: dts: marvell: cn9130-sr-som: add missing properties to emmcJosua Mayer
CN9130 System on Module connects an eMMC to ap_sdhci0, but the common properties indicating eMMC were not added to device-tree. Add no-sdio and non-removable as applicable to eMMC. Signed-off-by: Josua Mayer <josua@solid-run.com> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2025-09-12arm64: dts: marvell: cn9132-clearfog: fix multi-lane pci x2 and x4 portsJosua Mayer
The mvebu-comphy driver does not currently know how to pass correct lane-count to ATF while configuring the serdes lanes. This causes the system to hard reset during reconfiguration, if a pci card is present and has established a link during bootloader. Remove the comphy handles from the respective pci nodes to avoid runtime reconfiguration, relying solely on bootloader configuration - while avoiding the hard reset. When bootloader has configured the lanes correctly, the pci ports are functional under Linux. This issue may be addressed in the comphy driver at a future point. Fixes: e9ff907f4076 ("arm64: dts: add description for solidrun cn9132 cex7 module and clearfog board") Cc: stable@vger.kernel.org Signed-off-by: Josua Mayer <josua@solid-run.com> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2025-09-12arm64: dts: marvell: cn9132-clearfog: disable eMMC high-speed modesJosua Mayer
Similar to MacchiatoBIN the high-speed modes are unstable on the CN9132 CEX-7 module, leading to failed transactions under normal use. Disable all high-speed modes including UHS. Additionally add no-sdio and non-removable properties as appropriate for eMMC. Fixes: e9ff907f4076 ("arm64: dts: add description for solidrun cn9132 cex7 module and clearfog board") Cc: stable@vger.kernel.org Signed-off-by: Josua Mayer <josua@solid-run.com> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2025-09-12arm64: dts: marvell: cn913x-solidrun: fix sata ports statusJosua Mayer
Commit "arm64: dts: marvell: only enable complete sata nodes" changed armada-cp11x.dtsi disabling all sata ports status by default. The author missed some dts which relied on the dtsi enabling all ports, and just disabled unused ones instead. Update dts for SolidRun cn913x based boards to enable the available ports, rather than disabling the unvavailable one. Further according to dt bindings the serdes phys are to be specified in the port node, not the controller node. Move those phys properties accordingly in clearfog base/pro/solidwan. Fixes: 30023876aef4 ("arm64: dts: marvell: only enable complete sata nodes") Cc: stable@vger.kernel.org Signed-off-by: Josua Mayer <josua@solid-run.com> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2025-09-12arm64: dts: marvell: add dts for RIPE Atlas Probe v5Tomáš Macholda
internet measurement device based on Turris MOX Signed-off-by: Tomáš Macholda <tomas.macholda@nic.cz> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2025-09-12arm64: dts: marvell: armada-cp11x: Add default ICU address cellsKrzysztof Kozlowski
Add missing address-cells 0 to the ICU interrupt node to silence W=1 warning: armada-cp11x.dtsi:547.3-47: Warning (interrupt_map): /cp0-bus/pcie@f2600000:interrupt-map: Missing property '#address-cells' in node /cp0-bus/bus@f2000000/interrupt-controller@1e0000/interrupt-controller@10, using 0 as fallback Value '0' is correct because: 1. GIC interrupt controller does not have children, 2. interrupt-map property (in PCI node) consists of five components and the fourth component "parent unit address", which size is defined by '#address-cells' of the node pointed to by the interrupt-parent component, is not used (=0) Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2025-09-12arm64: dts: marvell: armada-37xx: Add default PCI interrup controller ↵Krzysztof Kozlowski
address cells Add missing address-cells 0 to the PCI interrupt node to silence W=1 warning: armada-37xx.dtsi:518.4-521.29: Warning (interrupt_map): /soc/pcie@d0070000:interrupt-map: Missing property '#address-cells' in node /soc/pcie@d0070000/interrupt-controller, using 0 as fallback Value '0' is correct because: 1. GIC interrupt controller does not have children, 2. interrupt-map property (in PCI node) consists of five components and the fourth component "parent unit address", which size is defined by '#address-cells' of the node pointed to by the interrupt-parent component, is not used (=0) Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2025-08-22arm64: dts: marvell: Minor whitespace cleanupKrzysztof Kozlowski
The DTS code coding style expects exactly one space around '=' character. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2025-08-22ARM64: dts: mcbin: fix SATA ports on MacchiatobinRussell King (Oracle)
Booting 6.16 on the Macchiatobin, I discover that I can no longer access my disks, and thus the userspace boot fails. The cause appears to be that one of the SATA controllers doesn't have any ports: [ 1.190312] ahci f4540000.sata: supply ahci not found, using dummy regulator [ 1.196255] ahci f4540000.sata: supply phy not found, using dummy regulator [ 1.202026] ahci f4540000.sata: No port enabled This is as a result of the blamed commit below which added a default disabled status to the .dtsi, but didn't properly update the mcbin dtsi file. Fix this regression. Fixes: 30023876aef4 ("arm64: dts: marvell: only enable complete sata nodes") Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2025-07-11arm64: dts: Add DTS for Marvell PXA1908 and samsung,coreprimevelteDuje Mihanović
Add DTS for Marvell PXA1908 SoC and Samsung Galaxy Core Prime Value Edition LTE, a smartphone based on said SoC. Signed-off-by: Duje Mihanović <duje@dujemihanovic.xyz> Link: https://lore.kernel.org/r/20250708-pxa1908-lkml-v16-4-b4392c484180@dujemihanovic.xyz Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2025-05-31Merge tag 'soc-dt-6.16' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/socLinus Torvalds
Pull SoC devicetree updates from Arnd Bergmann: "There are 11 newly supported SoCs, but these are all either new variants of existing designs, or straight reuses of the existing chip in a new package: - RK3562 is a new chip based on the old Cortex-A53 core, apparently a low-cost version of the Cortex-A55 based RK3568/RK3566. - NXP i.MX94 is a minor variation of i.MX93/i.MX95 with a different set of on-chip peripherals. - Renesas RZ/V2N (R9A09G056) is a new member of the larger RZ/V2 family - Amlogic S6/S7/S7D - Samsung Exynos7870 is an older chip similar to Exynos7885 - WonderMedia wm8950 is a minor variation on the wm8850 chip - Amlogic s805y is almost idential to s805x - Allwinner A523 is similar to A527 and T527 - Qualcomm MSM8926 is a variant of MSM8226 - Qualcomm Snapdragon X1P42100 is related to R1E80100 There are also 65 boards, including reference designs for the chips above, this includes - 12 new boards based on TI K3 series chips, most of them from Toradex - 10 devices using Rockchips RK35xx and PX30 chips - 2 phones and 2 laptops based on Qualcomm Snapdragon designs - 10 NXP i.MX8/i.MX9 boards, mostly for embedded/industrial uses - 3 Samsung Galaxy phones based on Exynos7870 - 5 Allwinner based boards using a variety of ARMv8 chips - 9 32-bit machines, each based on a different SoC family Aside from the new hardware, there is the usual set of cleanups and newly added hardware support on existing machines, for a total of 965 devicetree changesets" * tag 'soc-dt-6.16' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (956 commits) MAINTAINERS, mailmap: update Sven Peter's email address arm64: dts: renesas: rzg3e-smarc-som: Reduce I2C2 clock frequency arm64: dts: nuvoton: Add pinctrl ARM: dts: samsung: sp5v210-aries: Align wifi node name with bindings arm64: dts: blaize-blzp1600: Enable GPIO support dt-bindings: clock: socfpga: convert to yaml arm64: dts: rockchip: move rk3562 pinctrl node outside the soc node arm64: dts: rockchip: fix rk3562 pcie unit addresses arm64: dts: rockchip: move rk3528 pinctrl node outside the soc node arm64: dts: rockchip: remove a double-empty line from rk3576 core dtsi arm64: dts: rockchip: move rk3576 pinctrl node outside the soc node arm64: dts: rockchip: fix rk3576 pcie unit addresses arm64: dts: rockchip: Drop assigned-clock* from cpu nodes on rk3588 arm64: dts: rockchip: Add missing SFC power-domains to rk3576 Revert "arm64: dts: mediatek: mt8390-genio-common: Add firmware-name for scp0" arm64: dts: mediatek: mt8188: Address binding warnings for MDP3 nodes arm64: dts: mt6359: Rename RTC node to match binding expectations arm64: dts: mt8365-evk: Add goodix touchscreen support arm64: dts: mediatek: mt8188: Add missing #reset-cells property arm64: dts: airoha: en7581: Add PCIe nodes to EN7581 SoC evaluation board ...
2025-05-14arm64: dts: marvell: uDPU: define pinctrl state for alarm LEDsGabor Juhos
The two alarm LEDs of on the uDPU board are stopped working since commit 78efa53e715e ("leds: Init leds class earlier"). The LEDs are driven by the GPIO{15,16} pins of the North Bridge GPIO controller. These pins are part of the 'spi_quad' pin group for which the 'spi' function is selected via the default pinctrl state of the 'spi' node. This is wrong however, since in order to allow controlling the LEDs, the pins should use the 'gpio' function. Before the commit mentined above, the 'spi' function is selected first by the pinctrl core before probing the spi driver, but then it gets overridden to 'gpio' implicitly via the devm_gpiod_get_index_optional() call from the 'leds-gpio' driver. After the commit, the LED subsystem gets initialized before the SPI subsystem, so the function of the pin group remains 'spi' which in turn prevents controlling of the LEDs. Despite the change of the initialization order, the root cause is that the pinctrl state definition is wrong since its initial commit 0d45062cfc89 ("arm64: dts: marvell: Add device tree for uDPU board"), To fix the problem, override the function in the 'spi_quad_pins' node to 'gpio' and move the pinctrl state definition from the 'spi' node into the 'leds' node. Cc: stable@vger.kernel.org # needs adjustment for < 6.1 Fixes: 0d45062cfc89 ("arm64: dts: marvell: Add device tree for uDPU board") Signed-off-by: Gabor Juhos <j4g8y7@gmail.com> Signed-off-by: Imre Kaloz <kaloz@openwrt.org> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2025-04-14arm64: dts: marvell: Drop unused "pinctrl-names"Rob Herring (Arm)
"pinctrl-names" depends on "pinctrl-[0-9]" properties, but none are present for the pca9555 nodes. Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2025-03-15arm64: dts: marvell: Use preferred node names for "simple-bus"Rob Herring (Arm)
The "simple-bus" binding has preferred node names such as "bus", ".*-bus", or "soc". Rename the Marvell platforms to use these names. Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2025-03-15arm64: dts: marvell: Drop unused CP11X_TYPE defineRob Herring (Arm)
The CP11X_TYPE define is not used anywhere, remove it. Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2025-03-15arm64: dts: marvell: Move arch timer and pmu nodes to top-levelRob Herring (Arm)
The Arm arch timer and PMU are not memory-mapped peripherals, and therefore should not be under a "simple-bus" node. Move them to the top-level like other platforms. Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2025-03-07arm64: dts: marvell: armada-8040: Align GPIO hog name with bindingsKrzysztof Kozlowski
Bindings expect GPIO hog names to end with 'hog' suffix, so correct it to fix dtbs_check warning: armada-8040-clearfog-gt-8k.dtb: sata_reset: $nodename:0: 'sata_reset' does not match '^.+-hog(-[0-9]+)?$' Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2025-02-12arm64: dts: marvell: Add missing board compatible for IEI-Puzzle-M801Rob Herring (Arm)
The IEI-Puzzle-M801 board is missing a board compatible, so add one. Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Acked-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2025-02-12arm64: dts: marvell: Fix missing/incorrect "marvell,armada3710" compatibleRob Herring (Arm)
"marvell,armada3700" is not a documented compatible value. According to the schema, "marvell,armada3720" SoCs should have a "marvell,armada3710" fallback compatible. Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Acked-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2025-02-12arm64: dts: marvell: Drop incomplete root compatible/model propertiesRob Herring (Arm)
The Marvell .dtsi files define model and compatible properties which aren't complete. They are missing board compatible for example. This is mostly harmless as the properties will typically get overwritten. However, with these there will not be any warning should a board .dts forget to define its compatible and model. armada-371x.dtsi is not used anywhere, so it can be removed entirely since there is nothing left in it. Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Acked-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2025-01-08arm64: dts: marvell: drop additional phy-names for sataFrank Wunderlich
Commit facbe7092f8a ("arm64: dts: marvell: Drop undocumented SATA phy names") drops some phy-names from devicetrees but misses some. Drop them too. Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2025-01-08arm64: dts: marvell: only enable complete sata nodesFrank Wunderlich
The ahci-platform binding requires phys/target-supply property. After converting the binding to yaml the following files reporting "'anyOf' conditional failed" on sata@540000: sata-port@0 armada-7040-db.dts armada-8040-clearfog-gt-8k.dts armada-8040-mcbin.dts armada-8040-mcbin-singleshot.dts cn9130-db.dts cn9130-db-B.dts cn9131-db.dts cn9131-db-B.dts cn9132-db.dts cn9132-db-B.dts the following files reporting 'anyOf' conditional failed on sata@540000: sata-port@1 cn9132-db.dts cn9132-db-B.dts cn9130-crb-B.dts 'phys' is a required property 'target-supply' is a required property >From schema: Documentation/devicetree/bindings/ata/ahci-platform.yaml This is caused by defining sata-ports incomplete in armada-cp11x.dtsi and overriding only a subset of ports with the needed phys/target-supply property. Fix this by disabling the node-templates and enabling the needed nodes. Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2025-01-08arm64: dts: marvell: cn9131-cf-solidwan: fix cp1 comphy linksJosua Mayer
Marvell CN913x platforms use common phy framework for configuring and linking serdes lanes according to their usage. Each CP (X) features 5 serdes lanes (Y) represented by cpX_comphyY nodes. CN9131 SolidWAN uses CP1 serdes lanes 3 and 5 for eth1 and eth2 of CP1 respectively. Devicetree however wrongly links from these ports to the comphy of CP0. Replace the wrong links to cp0_comphy with cp1_comphy inside cp1_eth1, cp1_eth2. Fixes: 1280840d2030 ("arm64: dts: add description for solidrun cn9131 solidwan board") Signed-off-by: Josua Mayer <josua@solid-run.com> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2024-11-12Merge tag 'mvebu-dt64-6.13-1' of ↵Arnd Bergmann
https://git.kernel.org/pub/scm/linux/kernel/git/gclement/mvebu into soc/dt mvebu dt64 for 6.13 (part 1) armada-*: Drop undocumented SATA phy names * tag 'mvebu-dt64-6.13-1' of https://git.kernel.org/pub/scm/linux/kernel/git/gclement/mvebu: arm64: dts: marvell: Drop undocumented SATA phy names Link: https://lore.kernel.org/r/878qtu83vh.fsf@BLaptop.bootlin.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2024-11-05arm64: dts: marvell: Drop undocumented SATA phy namesRob Herring (Arm)
While "phy-names" is allowed for sata-port nodes, the names used aren't documented and are incorrect ("sata-phy" is what's documented). The name for a single entry is fairly useless, so just drop the property. Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2024-10-07arm64: dts: marvell: cn9130-sr-som: fix cp0 mdio pin numbersJosua Mayer
SolidRun CN9130 SoM actually uses CP_MPP[0:1] for mdio. CP_MPP[40] provides reference clock for dsa switch and ethernet phy on Clearfog Pro, wheras MPP[41] controls efuse programming voltage "VHV". Update the cp0 mdio pinctrl node to specify mpp0, mpp1. Fixes: 1c510c7d82e5 ("arm64: dts: add description for solidrun cn9130 som and clearfog boards") Cc: stable@vger.kernel.org # 6.11.x Signed-off-by: Josua Mayer <josua@solid-run.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Link: https://lore.kernel.org/stable/20241002-cn9130-som-mdio-v1-1-0942be4dc550%40solid-run.com Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2024-07-05arm64: dts: add description for solidrun cn9132 cex7 module and clearfog boardJosua Mayer
Add description for the SolidRun CN9132 COM-Express Type 7 module, and the Clearfog evaluation board. The COM-Express module includes: - CN9130 SoC - 2x 88F8215 Southbridges - eMMC - SPI Flash - DDR-4 SODIMM connector - 1GBase-T Ethernet PHY The Clearfog Evaluation board provides: - 1x 10Gbps SFP+ - 2x 5GBase-T RJ45 - 4x 1GBase-T RJ45 on DSA switch with 2.5Gbps cpu link - 1x full-size PCI-E x4 - 2x M.2 with PCI-E x1 - 1x M.2 with PCI-E x2 - 2x M.2 with PCI-E x1 and USB-2.0 - 1x M.2 with USB-2.0, USB-3.0 and 2x SIM slots - 1x mini-PCI-E x1 - 2x SATA (Laptop-Style connector with data and power) - 3x USB-3.0 Type-A - microSD slot Signed-off-by: Josua Mayer <josua@solid-run.com> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
generated by cgit v1.2.3 (git 2.0.4) at 2026-04-20 22:32:59 +0000