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2025-11-14arm64: dts: st: set RIFSC as an access controller on stm32mp21x platformsGatien Chevallier
Similarly to stm32mp23x/25x platforms, the RIFSC is a firewall controller. Declare it as an access controller, keep the "simple-bus" compatible in case CONFIG_STM32_FIREWALL is not set and update the child nodes. Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com> Link: https://lore.kernel.org/r/20251106-rifsc_debugfs-v2-2-f90e94ae756d@foss.st.com Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2025-11-14arm64: dts: st: Add I/O sync to eth pinctrl in stm32mp25-pinctrl.dtsiAntonio Borneo
On board stm32mp257f-ev1, the propagation delay between eth1/eth2 and the external PHY requires a compensation to guarantee that no packet get lost in all the working conditions. Add I/O synchronization properties in pinctrl on all the RGMII data pins, activating re-sampling on both edges of the clock. Co-developed-by: Christophe Roullier <christophe.roullier@foss.st.com> Signed-off-by: Christophe Roullier <christophe.roullier@foss.st.com> Signed-off-by: Antonio Borneo <antonio.borneo@foss.st.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/20251023132700.1199871-13-antonio.borneo@foss.st.com Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2025-11-14arm64: dts: st: Add memory-region-names property for stm32mp257f-ev1Patrice Chotard
In order to set the AMCR register, which configures the memory-region split between ospi1 and ospi2, we need to identify the ospi instance. By using memory-region-names, it allows to identify the ospi instance this memory-region belongs to. Fixes: cad2492de91c ("arm64: dts: st: Add SPI NOR flash support on stm32mp257f-ev1 board") Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Cc: stable@vger.kernel.org Link: https://lore.kernel.org/r/20251031-upstream_fix_dts_omm-v4-1-e4a059a50074@foss.st.com Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2025-09-15arm64: dts: st: fix memory region size on stm32mp235f-dkAmelie Delaunay
STM32MP23x SoCs provide a DDR controller supporting up to 4GB/16-bit. The control pin to properly configure 4GB/16-bit is not routed on stm32mp235f-dk, that's why the board only supports 2GB. Signed-off-by: Amelie Delaunay <amelie.delaunay@foss.st.com> Link: https://lore.kernel.org/r/20250910-stm32mp231_gpio_update-v2-2-8510efa2c5cf@foss.st.com Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2025-09-15arm64: dts: st: remove gpioj and gpiok banks from stm32mp231Amelie Delaunay
STM32MP23x supports AJ, AK and AL packages, where PI12 to PI15, PJ0 to PJ15 (whole J bank) and PK0 to PK7 (whole K bank) pins are not available. It means gpioj and gpiok nodes are useless in stm32mp231. Remove them. Signed-off-by: Amelie Delaunay <amelie.delaunay@foss.st.com> Link: https://lore.kernel.org/r/20250910-stm32mp231_gpio_update-v2-1-8510efa2c5cf@foss.st.com Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2025-09-15arm64: dts: st: enable ethernet1 controller on stm32mp235f-dkGatien Chevallier
ethernet1 controller is connected to the RTL8211F-CG Realtek PHY in RGMII mode. Enable this peripheral on the stm32mp235f-dk board. Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com> Link: https://lore.kernel.org/r/20250904-mp2_ethernet-v2-4-05a060157fb7@foss.st.com Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2025-09-15arm64: dts: st: enable ethernet1 controller on stm32mp257f-ev1Gatien Chevallier
ethernet1 controller is connected to the RTL8211F-CG Realtek PHY in RGMII mode. It can either be used as a standalone Ethernet controller or be connected to the internal TSN capable switch. For this board, keep the standalone setup. Also enable this peripheral on the stm32mp257f-ev1 board. Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com> Link: https://lore.kernel.org/r/20250904-mp2_ethernet-v2-3-05a060157fb7@foss.st.com Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2025-09-15arm64: dts: st: enable ethernet1 controller on stm32mp257f-dkGatien Chevallier
ethernet1 controller is connected to the RTL8211F-CG Realtek PHY in RGMII mode. Enable this peripheral on the stm32mp257f-dk board. Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com> Link: https://lore.kernel.org/r/20250904-mp2_ethernet-v2-2-05a060157fb7@foss.st.com Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2025-09-15arm64: dts: st: add eth1 pins for stm32mp2x platformsGatien Chevallier
Eth1 ethernet controller is present on every stm32mp2x vendor boards. Describe the pinctrl of eth1 for each of them. Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com> Link: https://lore.kernel.org/r/20250904-mp2_ethernet-v2-1-05a060157fb7@foss.st.com Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2025-09-15arm64: dts: st: enable display support on stm32mp257f-ev1 boardRaphael Gallais-Pou
Enable the following IPs on stm32mp257f-ev1 in order to get display: * LTDC * LVDS * WSVGA LVDS panel (1024x600) * Panel LVDS backlight as GPIO backlight * ILI2511 i2c touchscreen Signed-off-by: Raphael Gallais-Pou <raphael.gallais-pou@foss.st.com> Acked-by: Yannick Fertre <yannick.fertre@foss.st.com> Link: https://lore.kernel.org/r/20250822-drm-misc-next-v5-13-9c825e28f733@foss.st.com Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2025-09-15arm64: dts: st: add clock-cells to syscfg node on stm32mp251Raphael Gallais-Pou
Make the syscfg node a clock provider so clock consumers can reach child clocks through device-tree. Signed-off-by: Raphael Gallais-Pou <raphael.gallais-pou@foss.st.com> Acked-by: Yannick Fertre <yannick.fertre@foss.st.com> Link: https://lore.kernel.org/r/20250822-drm-misc-next-v5-12-9c825e28f733@foss.st.com Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2025-09-15arm64: dts: st: add lvds support on stm32mp255Raphael Gallais-Pou
The LVDS is used on STM32MP2 as a display interface. Add the LVDS node. Signed-off-by: Raphael Gallais-Pou <raphael.gallais-pou@foss.st.com> Acked-by: Yannick Fertre <yannick.fertre@foss.st.com> Link: https://lore.kernel.org/r/20250822-drm-misc-next-v5-11-9c825e28f733@foss.st.com Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2025-09-15arm64: dts: st: add ltdc support on stm32mp255Raphael Gallais-Pou
Add the LTDC node for stm32mp255 SoC and handle its loopback clocks. ck_ker_ltdc has the CLK_SET_RATE_PARENT flag. While having this flag is semantically correct, it for now leads to an improper setting of the clock rate. The ck_ker_ltdc parent clock is the flexgen 27, which does not support changing rates yet. To overcome this issue, a fixed clock can be used for the kernel clock. Signed-off-by: Raphael Gallais-Pou <raphael.gallais-pou@foss.st.com> Acked-by: Yannick Fertre <yannick.fertre@foss.st.com> Link: https://lore.kernel.org/r/20250822-drm-misc-next-v5-10-9c825e28f733@foss.st.com Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2025-09-15arm64: dts: st: add ltdc support on stm32mp251Raphael Gallais-Pou
The LCD-TFT Display Controller (LTDC) handles display composition, scaling and rotation. It provides a parallel digital RGB flow to be used by display interfaces. Add the LTDC node. Signed-off-by: Raphael Gallais-Pou <raphael.gallais-pou@foss.st.com> Acked-by: Yannick Fertre <yannick.fertre@foss.st.com> Link: https://lore.kernel.org/r/20250822-drm-misc-next-v5-9-9c825e28f733@foss.st.com Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2025-09-15arm64: dts: st: Enable PCIe on the stm32mp257f-ev1 boardChristian Bruel
Add PCIe RC and EP support on stm32mp257f-ev1 board. Default to RC mode. Signed-off-by: Christian Bruel <christian.bruel@foss.st.com> Link: https://lore.kernel.org/r/20250820075411.1178729-12-christian.bruel@foss.st.com Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2025-09-15arm64: dts: st: Add PCIe Endpoint mode on stm32mp251Christian Bruel
Add pcie_ep node to support STM32 MP25 PCIe driver based on the DesignWare PCIe core configured as Endpoint mode Signed-off-by: Christian Bruel <christian.bruel@foss.st.com> Acked-by: Manivannan Sadhasivam <mani@kernel.org> Link: https://lore.kernel.org/r/20250820075411.1178729-11-christian.bruel@foss.st.com Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2025-09-15arm64: dts: st: Add PCIe Root Complex mode on stm32mp251Christian Bruel
Add pcie_rc node to support STM32 MP25 PCIe driver based on the DesignWare PCIe core configured as Root Complex mode Supports Gen1/Gen2, single lane, MSI interrupts using the ARM GICv2m Signed-off-by: Christian Bruel <christian.bruel@foss.st.com> Acked-by: Manivannan Sadhasivam <mani@kernel.org> Link: https://lore.kernel.org/r/20250820075411.1178729-10-christian.bruel@foss.st.com Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2025-09-15arm64: dts: st: add PCIe pinctrl entries in stm32mp25-pinctrl.dtsiChristian Bruel
Add PCIe pinctrl entries in stm32mp25-pinctrl.dtsi init: forces GPIO to low while probing so CLKREQ is low for phy_init default: restore the AFMUX after controller probe Add Analog pins of PCIe to perform power cycle Signed-off-by: Christian Bruel <christian.bruel@foss.st.com> Link: https://lore.kernel.org/r/20250820075411.1178729-9-christian.bruel@foss.st.com Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2025-09-15arm64: dts: st: add Hardware debug port (HDP) on stm32mp25Clément Le Goffic
Add the hdp devicetree node for stm32mp25 SoC family Keep the node disabled as HDP needs the pinctrl SoC configuration to be able to output its mux output signal outside of the SoC, on the SoC pad. This configuration is provided in the board dtsi file through 'pinctrl-*' properties as well as HDP mux configuration. Thus, if needed, HDP should be enabled in board dtsi file. Signed-off-by: Clément Le Goffic <clement.legoffic@foss.st.com> Link: https://lore.kernel.org/r/20250711-hdp-upstream-v7-6-faeecf7aaee1@foss.st.com Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2025-09-03arm64: dts: stm32: Minor whitespace cleanupKrzysztof Kozlowski
The DTS code coding style expects exactly one space around '=' character. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20250819131707.86657-4-krzysztof.kozlowski@linaro.org Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2025-07-10arm64: dts: st: remove empty line in stm32mp251.dtsiPatrick Delaunay
Remove unnecessary empty line in stm32mp251.dtsi Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Link: https://lore.kernel.org/r/20250515151238.2.Ia426b4ef1d1200247a950ef9abd54a94dc520acb@changeid Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2025-07-10arm64: dts: st: fix timer used for ticksPatrick Delaunay
Remove always-on on generic ARM timer as the clock source provided by STGEN is deactivated in low power mode, STOP1 by example. Fixes: 5d30d03aaf78 ("arm64: dts: st: introduce stm32mp25 SoCs family") Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Link: https://lore.kernel.org/r/20250515151238.1.I85271ddb811a7cf73532fec90de7281cb24ce260@changeid Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2025-07-04arm64: dts: st: add timer nodes on stm32mp257f-ev1Fabrice Gasnier
Configure timer nodes on stm32mp257f-ev1: - Timer3 CH2 is available on mikroBUS connector for PWM - timer8 CH1, timer8 CH4, timer10 CH1 and timer12 CH2 are available on EXPANSION connector. Timers are kept disabled by default, so the pins can be used for any other purpose (and the timers can be assigned to any of the processors). Arbitrary choice is to use all these timers as PWM (or counter on internal clock signal), except for timer10 that is configured with CH1 as an input (for capture). Signed-off-by: Fabrice Gasnier <fabrice.gasnier@foss.st.com> Link: https://lore.kernel.org/r/20250110091922.980627-9-fabrice.gasnier@foss.st.com Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2025-07-04arm64: dts: st: add timer pins for stm32mp257f-ev1Fabrice Gasnier
Add timer pins available on stm32mp257f-ev1, configured for PWM: - timer3 CH2 is available on mikroBUS connector - timer8 CH1, timer8 CH4, timer10 CH1 and timer12 CH2 are available on EXPANSION connector Arbitrary define all these pins to be used as PWM (output) channels, except for timer10 CH1, to be used as counter input. Signed-off-by: Fabrice Gasnier <fabrice.gasnier@foss.st.com> Link: https://lore.kernel.org/r/20250110091922.980627-8-fabrice.gasnier@foss.st.com Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2025-07-04arm64: dts: st: add timer nodes on stm32mp251Fabrice Gasnier
Add timers support on STM32MP25 SoC. Use dedicated compatible to handle new features and instances introduced with this SoC. STM32MP25 SoC has various timer flavours, each group has its own specific feature list: - Advanced-control timers (TIM1/TIM8/TIM20) - General-purpose timers (TIM2/TIM3/TIM4/TIM5) - Basic timers (TIM6/TIM7) - General-purpose timers (TIM10/TIM11/TIM12/TIM13/TIM14) - General purpose timers (TIM15/TIM16/TIM17) Signed-off-by: Fabrice Gasnier <fabrice.gasnier@foss.st.com> Link: https://lore.kernel.org/r/20250110091922.980627-7-fabrice.gasnier@foss.st.com Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2025-05-31Merge tag 'soc-dt-6.16' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/socLinus Torvalds
Pull SoC devicetree updates from Arnd Bergmann: "There are 11 newly supported SoCs, but these are all either new variants of existing designs, or straight reuses of the existing chip in a new package: - RK3562 is a new chip based on the old Cortex-A53 core, apparently a low-cost version of the Cortex-A55 based RK3568/RK3566. - NXP i.MX94 is a minor variation of i.MX93/i.MX95 with a different set of on-chip peripherals. - Renesas RZ/V2N (R9A09G056) is a new member of the larger RZ/V2 family - Amlogic S6/S7/S7D - Samsung Exynos7870 is an older chip similar to Exynos7885 - WonderMedia wm8950 is a minor variation on the wm8850 chip - Amlogic s805y is almost idential to s805x - Allwinner A523 is similar to A527 and T527 - Qualcomm MSM8926 is a variant of MSM8226 - Qualcomm Snapdragon X1P42100 is related to R1E80100 There are also 65 boards, including reference designs for the chips above, this includes - 12 new boards based on TI K3 series chips, most of them from Toradex - 10 devices using Rockchips RK35xx and PX30 chips - 2 phones and 2 laptops based on Qualcomm Snapdragon designs - 10 NXP i.MX8/i.MX9 boards, mostly for embedded/industrial uses - 3 Samsung Galaxy phones based on Exynos7870 - 5 Allwinner based boards using a variety of ARMv8 chips - 9 32-bit machines, each based on a different SoC family Aside from the new hardware, there is the usual set of cleanups and newly added hardware support on existing machines, for a total of 965 devicetree changesets" * tag 'soc-dt-6.16' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (956 commits) MAINTAINERS, mailmap: update Sven Peter's email address arm64: dts: renesas: rzg3e-smarc-som: Reduce I2C2 clock frequency arm64: dts: nuvoton: Add pinctrl ARM: dts: samsung: sp5v210-aries: Align wifi node name with bindings arm64: dts: blaize-blzp1600: Enable GPIO support dt-bindings: clock: socfpga: convert to yaml arm64: dts: rockchip: move rk3562 pinctrl node outside the soc node arm64: dts: rockchip: fix rk3562 pcie unit addresses arm64: dts: rockchip: move rk3528 pinctrl node outside the soc node arm64: dts: rockchip: remove a double-empty line from rk3576 core dtsi arm64: dts: rockchip: move rk3576 pinctrl node outside the soc node arm64: dts: rockchip: fix rk3576 pcie unit addresses arm64: dts: rockchip: Drop assigned-clock* from cpu nodes on rk3588 arm64: dts: rockchip: Add missing SFC power-domains to rk3576 Revert "arm64: dts: mediatek: mt8390-genio-common: Add firmware-name for scp0" arm64: dts: mediatek: mt8188: Address binding warnings for MDP3 nodes arm64: dts: mt6359: Rename RTC node to match binding expectations arm64: dts: mt8365-evk: Add goodix touchscreen support arm64: dts: mediatek: mt8188: Add missing #reset-cells property arm64: dts: airoha: en7581: Add PCIe nodes to EN7581 SoC evaluation board ...
2025-05-14arm64: dts: st: use lptimer3 as tick broadcast source on stm32mp257f-ev1Fabrice Gasnier
During the low power modes the generic ARM timer is deactivated, so the the tick broadcast is used, based on LPTIMER3 which is clocked by LSE on STMicroelectronics boards. Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Signed-off-by: Fabrice Gasnier <fabrice.gasnier@foss.st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2025-05-14arm64: dts: st: add low-power timer nodes on stm32mp251Fabrice Gasnier
Add low-power timer (LPTimer) support on STM32MP25 SoC. The full feature set is implemented in LPTIM1/2/3/4. LPTIM5 supports a smaller set of features (no capture/compare) channel. Still, LPTIM5 can be used as single PWM, counter, trigger or timer. Signed-off-by: Fabrice Gasnier <fabrice.gasnier@foss.st.com> Link: https://lore.kernel.org/r/20250429125133.1574167-7-fabrice.gasnier@foss.st.com Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2025-05-14arm64: dts: st: Add SPI NOR flash support on stm32mp257f-ev1 boardPatrice Chotard
Add SPI NOR flash nor support on stm32mp257f-ev1 board. Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Link: https://lore.kernel.org/r/20250512-upstream_omm_ospi_dts-v10-3-fca0fbe6d10a@foss.st.com Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2025-05-14arm64: dts: st: Add ospi port1 pinctrl entries in stm32mp25-pinctrl.dtsiPatrice Chotard
Add pinctrl entry related to OSPI's port1 in stm32mp25-pinctrl.dtsi Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Link: https://lore.kernel.org/r/20250512-upstream_omm_ospi_dts-v10-2-fca0fbe6d10a@foss.st.com Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2025-05-14arm64: dts: st: Add OMM node on stm32mp251Patrice Chotard
Add Octo Memory Manager (OMM) entry on stm32mp251 and its two OSPI instance. Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Link: https://lore.kernel.org/r/20250512-upstream_omm_ospi_dts-v10-1-fca0fbe6d10a@foss.st.com Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2025-04-29arm64: dts: st: Use 128kB size for aliased GIC400 register access on ↵Christian Bruel
stm32mp23 SoCs Adjust the size of 8kB GIC regions to 128kB so that each 4kB is mapped 16 times over a 64kB region. The offset is then adjusted in the irq-gic driver. see commit 12e14066f4835 ("irqchip/GIC: Add workaround for aliased GIC400") Fixes: e9b03ef21386e ("arm64: dts: st: introduce stm32mp23 SoCs family") Suggested-by: Marc Zyngier <maz@kernel.org> Signed-off-by: Christian Bruel <christian.bruel@foss.st.com> Link: https://lore.kernel.org/r/20250415111654.2103767-7-christian.bruel@foss.st.com Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2025-04-29arm64: dts: st: Adjust interrupt-controller for stm32mp23 SoCsChristian Bruel
Use gic-400 compatible and remove address-cells = <1> for aarch64 Fixes: e9b03ef21386e ("arm64: dts: st: introduce stm32mp23 SoCs family") Signed-off-by: Christian Bruel <christian.bruel@foss.st.com> Link: https://lore.kernel.org/r/20250415111654.2103767-6-christian.bruel@foss.st.com Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2025-04-29arm64: dts: st: Use 128kB size for aliased GIC400 register access on ↵Christian Bruel
stm32mp21 SoCs Adjust the size of 8kB GIC regions to 128kB so that each 4kB is mapped 16 times over a 64kB region. The offset is then adjusted in the irq-gic driver. see commit 12e14066f4835 ("irqchip/GIC: Add workaround for aliased GIC400") Fixes: 7a57b1bb1afbf ("arm64: dts: st: introduce stm32mp21 SoCs family") Suggested-by: Marc Zyngier <maz@kernel.org> Signed-off-by: Christian Bruel <christian.bruel@foss.st.com> Link: https://lore.kernel.org/r/20250415111654.2103767-5-christian.bruel@foss.st.com Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2025-04-29arm64: dts: st: Adjust interrupt-controller for stm32mp21 SoCsChristian Bruel
Use gic-400 compatible for aarch64 Fixes: 7a57b1bb1afbf ("arm64: dts: st: introduce stm32mp21 SoCs family") Signed-off-by: Christian Bruel <christian.bruel@foss.st.com> Link: https://lore.kernel.org/r/20250415111654.2103767-4-christian.bruel@foss.st.com Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2025-04-29arm64: dts: st: Use 128kB size for aliased GIC400 register access on ↵Christian Bruel
stm32mp25 SoCs Adjust the size of 8kB GIC regions to 128kB so that each 4kB is mapped 16 times over a 64kB region. The offset is then adjusted in the irq-gic driver. see commit 12e14066f4835 ("irqchip/GIC: Add workaround for aliased GIC400") Fixes: 5d30d03aaf785 ("arm64: dts: st: introduce stm32mp25 SoCs family") Suggested-by: Marc Zyngier <maz@kernel.org> Signed-off-by: Christian Bruel <christian.bruel@foss.st.com> Acked-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20250415111654.2103767-3-christian.bruel@foss.st.com Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2025-04-29arm64: dts: st: Adjust interrupt-controller for stm32mp25 SoCsChristian Bruel
Use gic-400 compatible and remove address-cells = <1> on aarch64 Fixes: 5d30d03aaf785 ("arm64: dts: st: introduce stm32mp25 SoCs family") Signed-off-by: Christian Bruel <christian.bruel@foss.st.com> Link: https://lore.kernel.org/r/20250415111654.2103767-2-christian.bruel@foss.st.com Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2025-03-12arm64: dts: st: add stm32mp215f-dk board supportAmelie Delaunay
Add STM32MP215F Discovery Kit board support. It embeds a STM32MP235FAN SoC, with 2GB of LPDDR4, 1*USB2 peripheral bus powered typeC, 1*ETH, wifi/BT combo, LCD 18bit connector, CSI camera connector, ... Signed-off-by: Amelie Delaunay <amelie.delaunay@foss.st.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20250225-b4-stm32mp2_new_dts-v2-10-1a628c1580c7@foss.st.com Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2025-03-12arm64: dts: st: introduce stm32mp21 SoCs familyAlexandre Torgue
STM32MP21 family is composed of 3 SoCs defined as following: -STM32MP211: common part composed of 1*Cortex-A35, common peripherals like SDMMC, UART, SPI, I2C, parallel display, 1*ETH ... -STM32MP213: STM32MP211 + a second ETH, CAN-FD. -STM32MP215: STM32MP213 + Display and CSI2. A second diversity layer exists for security features/ A35 frequency: -STM32MP21xY, "Y" gives information: -Y = A means A35@1.2GHz + no cryp IP and no secure boot. -Y = C means A35@1.2GHz + cryp IP and secure boot. -Y = D means A35@1.5GHz + no cryp IP and no secure boot. -Y = F means A35@1.5GHz + cryp IP and secure boot. Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com> Signed-off-by: Amelie Delaunay <amelie.delaunay@foss.st.com> Link: https://lore.kernel.org/r/20250225-b4-stm32mp2_new_dts-v2-8-1a628c1580c7@foss.st.com Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2025-03-12arm64: dts: st: add stm32mp235f-dk board supportAmelie Delaunay
Add STM32MP235F Discovery Kit board support. It embeds a STM32MP235FAK SoC, with 4GB of LPDDR4, 2*USB typeA, 1*USB3 typeC, 1*ETH, wifi/BT combo, DSI HDMI, LVDS connector ... Signed-off-by: Amelie Delaunay <amelie.delaunay@foss.st.com> Link: https://lore.kernel.org/r/20250225-b4-stm32mp2_new_dts-v2-7-1a628c1580c7@foss.st.com Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2025-03-12arm64: dts: st: introduce stm32mp23 SoCs familyAlexandre Torgue
STM32MP23 family is composed of 3 SoCs defined as following: -STM32MP231: common part composed of 1*Cortex-A35, common peripherals like SDMMC, UART, SPI, I2C, parallel display, 1*ETH ... -STM32MP233: STM32MP231 + 1*Cortex-A35 (dual CPU), a second ETH, CAN-FD. -STM32MP235: STM32MP233 + GPU/AI and video encode/decode, DSI and LDVS display. A second diversity layer exists for security features/ A35 frequency: -STM32MP23xY, "Y" gives information: -Y = A means A35@1.2GHz + no cryp IP and no secure boot. -Y = C means A35@1.2GHz + cryp IP and secure boot. -Y = D means A35@1.5GHz + no cryp IP and no secure boot. -Y = F means A35@1.5GHz + cryp IP and secure boot. Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com> Signed-off-by: Amelie Delaunay <amelie.delaunay@foss.st.com> Link: https://lore.kernel.org/r/20250225-b4-stm32mp2_new_dts-v2-5-1a628c1580c7@foss.st.com Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2025-03-12arm64: dts: st: add stm32mp257f-dk board supportAlexandre Torgue
Add STM32MP257F Discovery board support. It embeds a STM32MP257FAL SoC, with 4GB of LPDDR4, 2*USB typeA, 1*USB3 typeC, 1*ETH, wifi/BT combo, DSI HDMI, LVDS connector ... Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com> Signed-off-by: Amelie Delaunay <amelie.delaunay@foss.st.com> Link: https://lore.kernel.org/r/20250225-b4-stm32mp2_new_dts-v2-2-1a628c1580c7@foss.st.com Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2024-12-20arm64: dts: st: enable imx335/csi/dcmipp pipeline on stm32mp257f-ev1Alain Volmat
Enable the camera pipeline with a imx335 sensor connected to the dcmipp via the csi interface. Signed-off-by: Alain Volmat <alain.volmat@foss.st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2024-12-20arm64: dts: st: add csi & dcmipp node in stm32mp25Alain Volmat
Add nodes describing the csi and dcmipp controllers handling the camera pipeline on the stm32mp25x. Signed-off-by: Alain Volmat <alain.volmat@foss.st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2024-12-09arm64: dts: st: Enable COMBOPHY on the stm32mp257f-ev1 boardChristian Bruel
Enable the COMBOPHY with external pad clock on stm32mp257f-ev1 board, to be used for the PCIe clock provider. Signed-off-by: Christian Bruel <christian.bruel@foss.st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2024-12-09arm64: dts: st: Add combophy node on stm32mp251Christian Bruel
Add support for COMBOPHY which is used either by the USB3 and PCIe controller. USB3 or PCIe mode is done with phy_set_mode(). PCIe internal reference clock can be generated from the internal clock source or optionnaly from an external 100Mhz pad. Signed-off-by: Christian Bruel <christian.bruel@foss.st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2024-12-09arm64: dts: st: add spdifrx support on stm32mp251Olivier Moysan
Add S/PDIFRX support to STM32MP25 SoC family. Signed-off-by: Olivier Moysan <olivier.moysan@foss.st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2024-12-09arm64: dts: st: add sai support on stm32mp251Olivier Moysan
Add SAI support to STM32MP25 SoC family. Signed-off-by: Olivier Moysan <olivier.moysan@foss.st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2024-12-09arm64: dts: st: add i2s support to stm32mp251Olivier Moysan
Add I2S support to STM32MP25 SoCs. Signed-off-by: Olivier Moysan <olivier.moysan@foss.st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2024-10-29arm64: dts: st: add DMA support on SPI instances of stm32mp25Amelie Delaunay
Add dmas and dma-names properties in spi nodes of stm32mp251.dtsi to enable DMA support. Signed-off-by: Amelie Delaunay <amelie.delaunay@foss.st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
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