diff options
| author | Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@intel.com> | 2025-02-18 16:34:51 +0800 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2025-02-25 10:53:42 -0600 |
| commit | 9288e0b44652c6d2dedfe65cdce5bbf062baa29f (patch) | |
| tree | e5b38b851c5e591e463cf505bf51457a05dfa380 | |
| parent | 58ef50ff9af1ac64fbfdc05188e8f053bef811c4 (diff) | |
arm: socfpga: agilex5: Add warm reset mask for Agilex5
There are 5 L4 watchdogs and one SDM triggered warm reset bit
in Agilex5 reset manager "stat" register where bit 16:20 for L4
watchdogs. Assigning value 1 to these bits in the register address
will initiate SDM to trigger warm reset.
Introducing new warm reset mask for Agilex5 to trigger warm reset
to all five L4 watchdogs.
Signed-off-by: Tien Fong Chee <tien.fong.chee@altera.com>
Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
| -rw-r--r-- | arch/arm/mach-socfpga/include/mach/reset_manager_soc64.h | 9 |
1 files changed, 8 insertions, 1 deletions
diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager_soc64.h b/arch/arm/mach-socfpga/include/mach/reset_manager_soc64.h index c8bb727aa2b..058fdd6e548 100644 --- a/arch/arm/mach-socfpga/include/mach/reset_manager_soc64.h +++ b/arch/arm/mach-socfpga/include/mach/reset_manager_soc64.h @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* * Copyright (C) 2016-2019 Intel Corporation <www.intel.com> + * Copyright (C) 2025 Altera Corporation <www.altera.com> */ #ifndef _RESET_MANAGER_SOC64_H_ @@ -23,14 +24,20 @@ void socfpga_bridges_reset(int enable); #define RSTMGR_BRGMODRST_FPGA2SOC_MASK 0x00000004 /* SDM, Watchdogs and MPU warm reset mask */ -#define RSTMGR_STAT_SDMWARMRST BIT(1) +#define RSTMGR_STAT_SDMWARMRST 0x2 #define RSTMGR_STAT_MPU0RST_BITPOS 8 #define RSTMGR_STAT_L4WD0RST_BITPOS 16 +#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) +#define RSTMGR_STAT_L4WD0RST_BIT 0x1F0000 +#define RSTMGR_L4WD_MPU_WARMRESET_MASK (RSTMGR_STAT_SDMWARMRST | \ + RSTMGR_STAT_L4WD0RST_BIT) +#else #define RSTMGR_L4WD_MPU_WARMRESET_MASK (RSTMGR_STAT_SDMWARMRST | \ GENMASK(RSTMGR_STAT_MPU0RST_BITPOS + 3, \ RSTMGR_STAT_MPU0RST_BITPOS) | \ GENMASK(RSTMGR_STAT_L4WD0RST_BITPOS + 3, \ RSTMGR_STAT_L4WD0RST_BITPOS)) +#endif /* * SocFPGA Stratix10 reset IDs, bank mapping is as follows: |