diff options
| author | Caleb Connolly <caleb.connolly@linaro.org> | 2024-04-15 16:03:39 +0100 |
|---|---|---|
| committer | Caleb Connolly <caleb.connolly@linaro.org> | 2024-04-23 13:29:15 +0200 |
| commit | 99e791746f318e308646b4831a0a9fc3ad9228c4 (patch) | |
| tree | d10264e1235732320b79e71958e14163e4ae4535 | |
| parent | 8a4e0433056abd07531e59b5fc5c2a8846bfc3b8 (diff) | |
clk/qcom: ipq4019: return valid rate when setting UART clock
clk_set_rate() should return the clock rate that was set. The IPQ4019
clock driver doesn't set any rates yet but it should still return the
expected value so that drivers can work properly.
For a baud rate of 115200 with an expected bit clock divisor of 16, the
clock rate should be 1843200 so return that frequency.
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
| -rw-r--r-- | drivers/clk/qcom/clock-ipq4019.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/clk/qcom/clock-ipq4019.c b/drivers/clk/qcom/clock-ipq4019.c index d693776d339..72f235eab21 100644 --- a/drivers/clk/qcom/clock-ipq4019.c +++ b/drivers/clk/qcom/clock-ipq4019.c @@ -21,7 +21,7 @@ static ulong ipq4019_clk_set_rate(struct clk *clk, ulong rate) switch (clk->id) { case GCC_BLSP1_UART1_APPS_CLK: /*UART1*/ /* This clock is already initialized by SBL1 */ - return 0; + return 1843200; default: return -EINVAL; } |