diff options
| author | Michal Simek <michal.simek@amd.com> | 2024-11-01 10:49:54 +0100 |
|---|---|---|
| committer | Leo Yu-Chi Liang <ycliang@andestech.com> | 2024-11-06 19:42:48 +0800 |
| commit | e4b8d8be4e1587369f447aef056a23c9de46575b (patch) | |
| tree | 0ffbde77f9a52a8c2ee0d1f3c0ea7af22e89d1b8 | |
| parent | d86ff34285fed658715b36639e3336f03038cc1c (diff) | |
xilinx: mbv: Align smode_defconfig with upstream QEMU
Align smode defconfig with upstream QEMU. It could be the part of commit
9d688e6da5c9 ("riscv: mbv: Align DT with QEMU").
Signed-off-by: Michal Simek <michal.simek@amd.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
| -rw-r--r-- | configs/xilinx_mbv32_smode_defconfig | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/configs/xilinx_mbv32_smode_defconfig b/configs/xilinx_mbv32_smode_defconfig index 741724f3bda..820681d505b 100644 --- a/configs/xilinx_mbv32_smode_defconfig +++ b/configs/xilinx_mbv32_smode_defconfig @@ -2,13 +2,13 @@ CONFIG_RISCV=y CONFIG_SYS_MALLOC_LEN=0xe00000 CONFIG_NR_DRAM_BANKS=1 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x21200000 +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x81200000 CONFIG_ENV_SIZE=0x20000 CONFIG_DEFAULT_DEVICE_TREE="xilinx-mbv32" -CONFIG_SPL_STACK=0x20200000 -CONFIG_SPL_BSS_START_ADDR=0x24000000 +CONFIG_SPL_STACK=0x80200000 +CONFIG_SPL_BSS_START_ADDR=0x84000000 CONFIG_SPL_BSS_MAX_SIZE=0x80000 -CONFIG_SYS_LOAD_ADDR=0x20200000 +CONFIG_SYS_LOAD_ADDR=0x80200000 CONFIG_SPL_SIZE_LIMIT=0x40000 CONFIG_SPL=y CONFIG_DEBUG_UART_BASE=0x40600000 @@ -16,12 +16,12 @@ CONFIG_DEBUG_UART_CLOCK=1000000 CONFIG_SYS_CLK_FREQ=100000000 CONFIG_BOOT_SCRIPT_OFFSET=0x0 CONFIG_TARGET_XILINX_MBV=y -CONFIG_SPL_OPENSBI_LOAD_ADDR=0x20100000 +CONFIG_SPL_OPENSBI_LOAD_ADDR=0x80100000 CONFIG_RISCV_SMODE=y # CONFIG_SPL_SMP is not set CONFIG_REMAKE_ELF=y CONFIG_FIT=y -CONFIG_SPL_LOAD_FIT_ADDRESS=0x20200000 +CONFIG_SPL_LOAD_FIT_ADDRESS=0x80200000 CONFIG_DISTRO_DEFAULTS=y CONFIG_DISPLAY_CPUINFO=y CONFIG_DISPLAY_BOARDINFO=y |