diff options
| author | Sébastien Szymanski <sebastien.szymanski@armadeus.com> | 2023-10-04 11:08:09 +0200 |
|---|---|---|
| committer | Stefano Babic <sbabic@denx.de> | 2023-10-17 23:55:09 +0200 |
| commit | fb2bdc4efcb99fab62051274ad2330aef07360f6 (patch) | |
| tree | 9df43422f42627e0cf745e910e6b86e1990e787e | |
| parent | e65b5d35c9116485366bb08138043d51220551da (diff) | |
arm: dts: imx93-11x11-evk: add bootph-some-ram property
i.MX93 11x11 EVK fails to boot:
U-Boot SPL 2023.10-00558-g65b9b3462bec-dirty (Oct 03 2023 - 17:40:10 +0200)
SOC: 0xa0009300
LC: 0x40010
M33 prepare ok
Normal Boot
Trying to boot from BOOTROM
Boot Stage: Primary boot
image offset 0x8000, pagesize 0x200, ivt offset 0x0
Load image from 0x44400 by ROM_API
NOTICE: BL31: v2.8(release):android-13.0.0_2.0.0-0-ge4b2dbfa52f5
NOTICE: BL31: Built : 17:52:46, Sep 28 2023
That's because commit 9e644284ab81 ("dm: core: Report
bootph-pre-ram/sram node as pre-reloc after relocation"):
"[This] changes behavior of what nodes are bound in the U-Boot
proper pre-relocation phase. Change to bootph-all or add
bootph-some-ram prop to restore prior behavior."
Fix this by adding bootph-some-ram prop as suggested by the commit
above.
Fixes: 9e644284ab81 ("dm: core: Report bootph-pre-ram/sram node as pre-reloc after relocation")
Signed-off-by: Sébastien Szymanski <sebastien.szymanski@armadeus.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
| -rw-r--r-- | arch/arm/dts/imx93-11x11-evk-u-boot.dtsi | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/arch/arm/dts/imx93-11x11-evk-u-boot.dtsi b/arch/arm/dts/imx93-11x11-evk-u-boot.dtsi index 93b4d91e4c3..a9dffa5a71e 100644 --- a/arch/arm/dts/imx93-11x11-evk-u-boot.dtsi +++ b/arch/arm/dts/imx93-11x11-evk-u-boot.dtsi @@ -8,6 +8,7 @@ compatible = "wdt-reboot"; wdt = <&wdog3>; bootph-pre-ram; + bootph-some-ram; }; firmware { @@ -30,19 +31,23 @@ &aips2 { bootph-pre-ram; + bootph-some-ram; }; &aips3 { bootph-pre-ram; + bootph-some-ram; }; &iomuxc { bootph-pre-ram; + bootph-some-ram; }; ®_usdhc2_vmmc { u-boot,off-on-delay-us = <20000>; bootph-pre-ram; + bootph-some-ram; }; &pinctrl_reg_usdhc2_vmmc { @@ -51,59 +56,73 @@ &pinctrl_uart1 { bootph-pre-ram; + bootph-some-ram; }; &pinctrl_usdhc2_gpio { bootph-pre-ram; + bootph-some-ram; }; &pinctrl_usdhc2 { bootph-pre-ram; + bootph-some-ram; }; &gpio1 { bootph-pre-ram; + bootph-some-ram; }; &gpio2 { bootph-pre-ram; + bootph-some-ram; }; &gpio3 { bootph-pre-ram; + bootph-some-ram; }; &gpio4 { bootph-pre-ram; + bootph-some-ram; }; &lpuart1 { bootph-pre-ram; + bootph-some-ram; }; &usdhc1 { bootph-pre-ram; + bootph-some-ram; }; &usdhc2 { bootph-pre-ram; + bootph-some-ram; fsl,signal-voltage-switch-extra-delay-ms = <8>; }; &lpi2c2 { bootph-pre-ram; + bootph-some-ram; }; &{/soc@0/bus@44000000/i2c@44350000/pmic@25} { bootph-pre-ram; + bootph-some-ram; }; &{/soc@0/bus@44000000/i2c@44350000/pmic@25/regulators} { bootph-pre-ram; + bootph-some-ram; }; &pinctrl_lpi2c2 { bootph-pre-ram; + bootph-some-ram; }; &fec { @@ -124,6 +143,7 @@ &s4muap { bootph-pre-ram; + bootph-some-ram; status = "okay"; }; |