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-rw-r--r--arch/arm/dts/imx93-11x11-evk-u-boot.dtsi20
1 files changed, 20 insertions, 0 deletions
diff --git a/arch/arm/dts/imx93-11x11-evk-u-boot.dtsi b/arch/arm/dts/imx93-11x11-evk-u-boot.dtsi
index 93b4d91e4c3..a9dffa5a71e 100644
--- a/arch/arm/dts/imx93-11x11-evk-u-boot.dtsi
+++ b/arch/arm/dts/imx93-11x11-evk-u-boot.dtsi
@@ -8,6 +8,7 @@
compatible = "wdt-reboot";
wdt = <&wdog3>;
bootph-pre-ram;
+ bootph-some-ram;
};
firmware {
@@ -30,19 +31,23 @@
&aips2 {
bootph-pre-ram;
+ bootph-some-ram;
};
&aips3 {
bootph-pre-ram;
+ bootph-some-ram;
};
&iomuxc {
bootph-pre-ram;
+ bootph-some-ram;
};
&reg_usdhc2_vmmc {
u-boot,off-on-delay-us = <20000>;
bootph-pre-ram;
+ bootph-some-ram;
};
&pinctrl_reg_usdhc2_vmmc {
@@ -51,59 +56,73 @@
&pinctrl_uart1 {
bootph-pre-ram;
+ bootph-some-ram;
};
&pinctrl_usdhc2_gpio {
bootph-pre-ram;
+ bootph-some-ram;
};
&pinctrl_usdhc2 {
bootph-pre-ram;
+ bootph-some-ram;
};
&gpio1 {
bootph-pre-ram;
+ bootph-some-ram;
};
&gpio2 {
bootph-pre-ram;
+ bootph-some-ram;
};
&gpio3 {
bootph-pre-ram;
+ bootph-some-ram;
};
&gpio4 {
bootph-pre-ram;
+ bootph-some-ram;
};
&lpuart1 {
bootph-pre-ram;
+ bootph-some-ram;
};
&usdhc1 {
bootph-pre-ram;
+ bootph-some-ram;
};
&usdhc2 {
bootph-pre-ram;
+ bootph-some-ram;
fsl,signal-voltage-switch-extra-delay-ms = <8>;
};
&lpi2c2 {
bootph-pre-ram;
+ bootph-some-ram;
};
&{/soc@0/bus@44000000/i2c@44350000/pmic@25} {
bootph-pre-ram;
+ bootph-some-ram;
};
&{/soc@0/bus@44000000/i2c@44350000/pmic@25/regulators} {
bootph-pre-ram;
+ bootph-some-ram;
};
&pinctrl_lpi2c2 {
bootph-pre-ram;
+ bootph-some-ram;
};
&fec {
@@ -124,6 +143,7 @@
&s4muap {
bootph-pre-ram;
+ bootph-some-ram;
status = "okay";
};