Merge commit '3c9bb8fbdc77f6bd56e97597d875d8965db3b96c' of https://github.com/tienfong/uboot_mainline

A few small SoCFPGA updates

1 files changed, 16 insertions, 1 deletions

diff --git a/arch/arm/mach-socfpga/clock_manager_s10.c b/arch/arm/mach-socfpga/clock_manager_s10.c
index 4b4f0749dbf..45300336d52 100644
--- a/arch/arm/mach-socfpga/clock_manager_s10.c
+++ b/arch/arm/mach-socfpga/clock_manager_s10.c
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0
 /*
- * Copyright (C) 2016-2018 Intel Corporation <www.intel.com>
+ * Copyright (C) 2016-2023 Intel Corporation <www.intel.com>
  *
  */
 
@@ -399,6 +399,21 @@ unsigned int cm_get_l4_sys_free_clk_hz(void)
 	return cm_get_l3_main_clk_hz() / 4;
 }
 
+/*
+ * Override weak dw_spi_get_clk implementation in designware_spi.c driver
+ */
+
+int dw_spi_get_clk(struct udevice *bus, ulong *rate)
+{
+	*rate = cm_get_spi_controller_clk_hz();
+	if (!*rate) {
+		printf("SPI: clock rate is zero");
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
 void cm_print_clock_quick_summary(void)
 {
 	printf("MPU         %d kHz\n", (u32)(cm_get_mpu_clk_hz() / 1000));