diff options
| author | Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com> | 2022-08-19 17:01:07 +0800 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2022-09-13 12:08:40 -0400 |
| commit | d37b4f37ea40243ad3a126a152920339189afb52 (patch) | |
| tree | 589ce43d293f65f0102ac5831c82596fde6393d4 /arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog_serial.c | |
| parent | 5150e908f54c3bd0fdd30eefdffaf49c826881ba (diff) | |
arm: dts: aspeed: Update SPI flash node settings
For both AST2500 and AST2600, there are three
SPI controllers, FMC(Firmware Memory Controller),
SPI1 and SPI2. The clock source is HCLK. Following
is the basic information for ASPEED SPI controller.
AST2500:
- FMC:
CS number: 3
controller reg: 0x1e620000 - 0x1e62ffff
decoded address: 0x20000000 - 0x2fffffff
- SPI1:
CS number: 2
controller reg: 0x1e630000 - 0x1e630fff
decoded address: 0x30000000 - 0x37ffffff
- SPI2:
CS number: 2
controller reg: 0x1e631000 - 0x1e631fff
decoded address: 0x38000000 - 0x3fffffff
AST2600:
- FMC:
CS number: 3
controller reg: 0x1e620000 - 0x1e62ffff
decoded address: 0x20000000 - 0x2fffffff
- SPI1:
CS number: 2
controller reg: 0x1e630000 - 0x1e630fff
decoded address: 0x30000000 - 0x3fffffff
- SPI2:
CS number: 3
controller reg: 0x1e631000 - 0x1e631fff
decoded address: 0x50000000 - 0x5fffffff
Signed-off-by: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>
Diffstat (limited to 'arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog_serial.c')
0 files changed, 0 insertions, 0 deletions