diff options
| author | Yu Chien Peter Lin <peterlin@andestech.com> | 2022-10-25 23:03:50 +0800 |
|---|---|---|
| committer | Leo Yu-Chi Liang <ycliang@andestech.com> | 2022-11-03 13:27:56 +0800 |
| commit | a5dfa3b8a0f7ad555495bad1386613d2de4ba619 (patch) | |
| tree | 74a91e18cd008f381c12d615587912630530bed3 /arch/riscv/dts/ae350_64.dts | |
| parent | c8d9ff634fc429db5acf2f5386ea937f0fef1ae7 (diff) | |
riscv: Rename Andes PLIC to PLICSW
As PLICSW is used to trigger the software interrupt, we should rename
Andes PLIC configuration and file name to reflect the usage. This patch
also updates PLMT and PLICSW compatible strings to be consistent with
OpenSBI fdt driver.
Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Rick Chen <rick@andestech.com>
Diffstat (limited to 'arch/riscv/dts/ae350_64.dts')
| -rw-r--r-- | arch/riscv/dts/ae350_64.dts | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/arch/riscv/dts/ae350_64.dts b/arch/riscv/dts/ae350_64.dts index 74cff9122d4..cddbaec98ad 100644 --- a/arch/riscv/dts/ae350_64.dts +++ b/arch/riscv/dts/ae350_64.dts @@ -146,8 +146,8 @@ &CPU3_intc 11 &CPU3_intc 9>; }; - plic1: interrupt-controller@e6400000 { - compatible = "riscv,plic1"; + plicsw: interrupt-controller@e6400000 { + compatible = "andestech,plicsw"; #interrupt-cells = <2>; interrupt-controller; reg = <0x0 0xe6400000 0x0 0x400000>; @@ -159,7 +159,7 @@ }; plmt0@e6000000 { - compatible = "riscv,plmt0"; + compatible = "andestech,plmt0"; interrupts-extended = <&CPU0_intc 7 &CPU1_intc 7 &CPU2_intc 7 |