Age | Commit message (Expand) | Author |
---|---|---|
2023-02-17 | riscv: ae350: dts: Update L2 cache compatible string | Yu Chien Peter Lin |
2022-11-03 | riscv: Rename Andes PLIC to PLICSW | Yu Chien Peter Lin |
2021-06-17 | riscv: ae350: dts: Add missing "u-boot, dm-spl" for SPL config | Bin Meng |
2021-06-17 | riscv: ae350: dts: Remove the unnecessary #address-cells in plic nodes | Bin Meng |
2021-06-17 | riscv: ae350: dts: Remove the unnecessary space in bootargs | Bin Meng |
2021-06-17 | riscv: ae350: dts: Add SPDX license header | Bin Meng |
2021-05-19 | riscv: ae350: Switch to use binman to generate u-boot.itb | Bin Meng |
2019-12-10 | riscv: dts: Add #address-cells and #size-cells in nor node | Rick Chen |
2019-12-10 | riscv: dts: Support four cores SMP | Rick Chen |
2019-09-03 | riscv: dts: move out AE350 L2 node from cpus node | Rick Chen |
2019-04-12 | dts: switch spi-flash to jedec, spi-nor compatible | Neil Armstrong |
2019-04-08 | riscv: dts: ae350 support SMP | Rick Chen |
2018-11-26 | riscv: dts: Add ae350_32.dts for RV32I | Rick Chen |