summaryrefslogtreecommitdiff
path: root/board/imgtec
diff options
context:
space:
mode:
authorTom Rini <trini@konsulko.com>2022-11-16 13:10:37 -0500
committerTom Rini <trini@konsulko.com>2022-12-05 16:06:07 -0500
commitaa6e94deabb45154cea07ad44c4a5c047bca078b (patch)
tree1131ae8e3635f3d0c91f8df892ab05e4d9595785 /board/imgtec
parentaec118ebe63f7f0ab60916f9906fb3cb680abf7a (diff)
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_*
The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'board/imgtec')
-rw-r--r--board/imgtec/boston/ddr.c2
-rw-r--r--board/imgtec/malta/lowlevel_init.S4
-rw-r--r--board/imgtec/malta/malta.c2
-rw-r--r--board/imgtec/xilfpga/xilfpga.c2
4 files changed, 5 insertions, 5 deletions
diff --git a/board/imgtec/boston/ddr.c b/board/imgtec/boston/ddr.c
index 5b245cb4473..8532225dc0d 100644
--- a/board/imgtec/boston/ddr.c
+++ b/board/imgtec/boston/ddr.c
@@ -27,7 +27,7 @@ phys_size_t board_get_usable_ram_top(phys_size_t total_size)
{
DECLARE_GLOBAL_DATA_PTR;
- if (gd->ram_top < CONFIG_SYS_SDRAM_BASE) {
+ if (gd->ram_top < CFG_SYS_SDRAM_BASE) {
/* 2GB wrapped around to 0 */
return CKSEG0ADDR(256 << 20);
}
diff --git a/board/imgtec/malta/lowlevel_init.S b/board/imgtec/malta/lowlevel_init.S
index bed24972f7a..aa910bf1ce1 100644
--- a/board/imgtec/malta/lowlevel_init.S
+++ b/board/imgtec/malta/lowlevel_init.S
@@ -118,7 +118,7 @@ _msc01:
/* setup basic address decode */
PTR_LI t0, CKSEG1ADDR(MALTA_MSC01_BIU_BASE)
li t1, 0x0
- li t2, -CONFIG_SYS_SDRAM_SIZE
+ li t2, -CFG_SYS_SDRAM_SIZE
sw t1, MSC01_BIU_MCBAS1L_OFS(t0)
sw t2, MSC01_BIU_MCMSK1L_OFS(t0)
sw t1, MSC01_BIU_MCBAS2L_OFS(t0)
@@ -168,7 +168,7 @@ _msc01:
sw t3, MSC01_PCI_SC2PIOMAPL_OFS(t0)
/* setup PCI_BAR0 memory window */
- li t1, -CONFIG_SYS_SDRAM_SIZE
+ li t1, -CFG_SYS_SDRAM_SIZE
sw t1, MSC01_PCI_BAR0_OFS(t0)
/* setup PCI to SysCon/CPU translation */
diff --git a/board/imgtec/malta/malta.c b/board/imgtec/malta/malta.c
index 9853a0ba82f..4a72ab5ceca 100644
--- a/board/imgtec/malta/malta.c
+++ b/board/imgtec/malta/malta.c
@@ -94,7 +94,7 @@ static enum sys_con malta_sys_con(void)
int dram_init(void)
{
- gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
+ gd->ram_size = CFG_SYS_SDRAM_SIZE;
return 0;
}
diff --git a/board/imgtec/xilfpga/xilfpga.c b/board/imgtec/xilfpga/xilfpga.c
index 6a836370e36..71226927211 100644
--- a/board/imgtec/xilfpga/xilfpga.c
+++ b/board/imgtec/xilfpga/xilfpga.c
@@ -19,7 +19,7 @@ int dram_init(void)
{
/* MIG IP block is smart and doesn't need SW
* to do any init */
- gd->ram_size = CONFIG_SYS_SDRAM_SIZE; /* in bytes */
+ gd->ram_size = CFG_SYS_SDRAM_SIZE; /* in bytes */
return 0;
}