diff options
| author | Andre Przywara <andre.przywara@arm.com> | 2022-05-04 22:10:28 +0100 |
|---|---|---|
| committer | Andre Przywara <andre.przywara@arm.com> | 2022-05-24 01:15:09 +0100 |
| commit | 444ab3569bae32daed9c05fb10f87d907cc180ff (patch) | |
| tree | c4fe6bd4cde195029c24cc3f1b464e11dedafd7e /drivers/clk/sunxi/clk_r40.c | |
| parent | 596247e54b6243c53921a936fe3ce5ef031a702d (diff) | |
clk: sunxi: add PIO bus gate clocks
The introduction of the DM pinctrl driver made its probe function enable
all clocks enumerated in the DT. This includes the "CLK_BUS_PIO" (and
variations) gate clock. Also CLK_PLL_PERIPH0 is used by the R_CCU device.
So far we didn't describe those clocks in our clock driver.
As we enable them already in the SPL, the devices happen to work, but
the clock driver still complains about not finding those clocks:
=========
sunxi_set_gate: (CLK#58) unhandled
=========
Add the one-liners that are needed to announce the gate bit for those
clocks, to silence that message on the console.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Samuel Holland <samuel@sholland.org>
Diffstat (limited to 'drivers/clk/sunxi/clk_r40.c')
| -rw-r--r-- | drivers/clk/sunxi/clk_r40.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/clk/sunxi/clk_r40.c b/drivers/clk/sunxi/clk_r40.c index 4d5b69a9765..45633a2a524 100644 --- a/drivers/clk/sunxi/clk_r40.c +++ b/drivers/clk/sunxi/clk_r40.c @@ -32,6 +32,8 @@ static struct ccu_clk_gate r40_gates[] = { [CLK_BUS_GMAC] = GATE(0x064, BIT(17)), + [CLK_BUS_PIO] = GATE(0x068, BIT(5)), + [CLK_BUS_I2C0] = GATE(0x06c, BIT(0)), [CLK_BUS_I2C1] = GATE(0x06c, BIT(1)), [CLK_BUS_I2C2] = GATE(0x06c, BIT(2)), |