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| author | Michal Simek <michal.simek@xilinx.com> | 2020-10-05 15:43:44 +0200 |
|---|---|---|
| committer | Michal Simek <michal.simek@xilinx.com> | 2020-10-27 08:13:31 +0100 |
| commit | e9284066958e906118b3fd71d7e81e9916b2c58a (patch) | |
| tree | 9e3d5223fc098f91a3c5563f06e7887ca11844d8 /drivers/core/lists.c | |
| parent | 0d76b71d93f6d7740b973dbb50010dc8f7b347f0 (diff) | |
arm64: zynqmp: Enable FPGA loading from SPL
fpga bitstream needs to be listed in config node in FIT image. Only tested
option is bitstream in BIN format.
Enabling this feature increase code size by almost 4k.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Diffstat (limited to 'drivers/core/lists.c')
0 files changed, 0 insertions, 0 deletions