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authorMichal Simek <michal.simek@amd.com>2024-05-29 16:48:00 +0200
committerMichal Simek <michal.simek@amd.com>2024-06-17 16:02:29 +0200
commit4950a98d14da12335c960c81a62754b667c11300 (patch)
tree9a91cad6f039d4623501831ff377dba5da7d729e /drivers/ddr/altera/sdram_agilex.c
parent96cec1bbc9ed108de3fab582bd8ae26775c01e0b (diff)
mmc: versal2: Update zynq_sdhci driver to support AMD Versal Gen 2
Enable tap delay programming for new SoC and also enable it via defconfig. Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/f07daded9704cbc393657b65a28933c34a8cec25.1716994063.git.michal.simek@amd.com
Diffstat (limited to 'drivers/ddr/altera/sdram_agilex.c')
0 files changed, 0 insertions, 0 deletions