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| author | Quentin Schulz <quentin.schulz@cherry.de> | 2024-06-06 10:45:36 +0200 |
|---|---|---|
| committer | Kever Yang <kever.yang@rock-chips.com> | 2024-06-14 17:11:29 +0800 |
| commit | 724d3c686c57b3ce50a39dceb3f3f1ebc9d3e32c (patch) | |
| tree | e147673c2ac5985f1a340eef0e2bee2d7e597cc5 /drivers/ddr/altera/sdram_agilex.c | |
| parent | 2ce40542e0ebc9b782954ae6df3a23885ff60cf1 (diff) | |
rockchip: ringneck-px30: fix TPL_MAX_SIZE
Ringneck was mistakenly set to allow up to 128KiB for the TPL code size
while PX30 SoC only has 16KiB of SRAM.
Therefore, let's use the default value of TPL_MAX_SIZE from the SoC
(which is 10KiB) so that the max code size is actually checked and
useful.
Fixes: c925be73a0a8 ("rockchip: add support for PX30 Ringneck SoM on Haikou Devkit")
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de>
Diffstat (limited to 'drivers/ddr/altera/sdram_agilex.c')
0 files changed, 0 insertions, 0 deletions