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| author | Christian Marangi <ansuelsmth@gmail.com> | 2024-08-03 10:43:25 +0200 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2024-08-19 16:15:26 -0600 |
| commit | 105c78844a6cf72eefbfd614fc52da92bc0341f1 (patch) | |
| tree | 0552b2d21de8843ede60460e97476ed57964a6fa /drivers/ddr/imx/phy/ddrphy_train.c | |
| parent | a776493f4b4b51515db456e635709a93e256dacd (diff) | |
clk: mediatek: mt7622: add missing clock PERIBUS_SEL clock
Add missing PERIBUS_SEL clock to match upstream linux clk ID order. Also
convert pericfg to mux + gate implementation as now we have also mux on
top of gates.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Diffstat (limited to 'drivers/ddr/imx/phy/ddrphy_train.c')
0 files changed, 0 insertions, 0 deletions