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author | Christian Marangi <ansuelsmth@gmail.com> | 2024-08-03 10:43:24 +0200 |
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committer | Tom Rini <trini@konsulko.com> | 2024-08-19 16:15:26 -0600 |
commit | a776493f4b4b51515db456e635709a93e256dacd (patch) | |
tree | 60e59679c43a4e54ab01040f9db15ba27fef74c6 /drivers/ddr/imx/phy/ddrphy_train.c | |
parent | a942c0c3f5d454241cf2c1d61d06a42dcd6a14cc (diff) |
clk: mediatek: mt7622: add missing clock PERI_UART4_PD
Add missing clock PERI_UART4_PD for peri clock gates. This is needed to
match upstream linux clk ID in preparation for OF_UPSTREAM.
Also convert infracfg to mux + gate implementation as now we have mux on
top of gates.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Diffstat (limited to 'drivers/ddr/imx/phy/ddrphy_train.c')
0 files changed, 0 insertions, 0 deletions