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author | Jernej Skrabec <jernej.skrabec@gmail.com> | 2024-12-29 21:13:13 +0100 |
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committer | Andre Przywara <andre.przywara@arm.com> | 2025-07-27 23:02:09 +0100 |
commit | 39a6a2a8a248cf42f068dae61c6d9a4c8ea4a172 (patch) | |
tree | 6f8032468b592d283ecc5cf0ba38120953f44925 /drivers/ddr/microchip/ddr2_timing.h | |
parent | d157dec118f8cf81bc60dcfd010cc30bde8e5e23 (diff) |
sunxi: A523: add DRAM initialisation routine
DRAM init code, as per reverse engineering and matching against
previous SoCs. As usual no real documentation, and the DRAM controller
is the usual mixture of close-to-previous IP and new inventions.
This version supports LPDDR4 for now only, as seen on the early boards.
This needs improvements, but it can be done later.
Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Diffstat (limited to 'drivers/ddr/microchip/ddr2_timing.h')
0 files changed, 0 insertions, 0 deletions