diff options
| author | Tom Rini <trini@konsulko.com> | 2025-04-07 16:40:02 -0600 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2025-04-08 11:43:23 -0600 |
| commit | ff61d6bfd1c9534d3fc2397846a5899639f2e55d (patch) | |
| tree | dcfe4bc52848a5637c975a3352b57885e5b8a06d /drivers/mtd/nand/raw/atmel/nand-controller.c | |
| parent | 34820924edbc4ec7803eb89d9852f4b870fa760a (diff) | |
| parent | f892a7f397a66d8d09f418d1e0e06dfb48bac27d (diff) | |
Merge branch 'next'
Note that this undoes the changes of commit cf6d4535cc4c ("x86:
emulation: Disable bloblist for now") as that was intended only for the
release due to time.
Diffstat (limited to 'drivers/mtd/nand/raw/atmel/nand-controller.c')
| -rw-r--r-- | drivers/mtd/nand/raw/atmel/nand-controller.c | 13 |
1 files changed, 9 insertions, 4 deletions
diff --git a/drivers/mtd/nand/raw/atmel/nand-controller.c b/drivers/mtd/nand/raw/atmel/nand-controller.c index 56fbd64ef68..c90a4eab8df 100644 --- a/drivers/mtd/nand/raw/atmel/nand-controller.c +++ b/drivers/mtd/nand/raw/atmel/nand-controller.c @@ -1127,7 +1127,7 @@ static int atmel_smc_nand_prepare_smcconf(struct atmel_nand *nand, const struct nand_data_interface *conf, struct atmel_smc_cs_conf *smcconf) { - u32 ncycles, totalcycles, timeps, mckperiodps; + u32 ncycles, totalcycles, timeps, mckperiodps, pulse; struct atmel_nand_controller *nc; int ret; @@ -1253,11 +1253,16 @@ static int atmel_smc_nand_prepare_smcconf(struct atmel_nand *nand, ATMEL_SMC_MODE_TDFMODE_OPTIMIZED; /* - * Read pulse timing directly matches tRP: + * Read pulse timing would directly match tRP, + * but some NAND flash chips (S34ML01G2 and W29N02KVxxAF) + * do not work properly in timing mode 3. + * The workaround is to extend the SMC NRD pulse to meet tREA + * timing. * - * NRD_PULSE = tRP + * NRD_PULSE = max(tRP, tREA) */ - ncycles = DIV_ROUND_UP(conf->timings.sdr.tRP_min, mckperiodps); + pulse = max(conf->timings.sdr.tRP_min, conf->timings.sdr.tREA_max); + ncycles = DIV_ROUND_UP(pulse, mckperiodps); totalcycles += ncycles; ret = atmel_smc_cs_conf_set_pulse(smcconf, ATMEL_SMC_NRD_SHIFT, ncycles); |