Merge branch 'next'

Note that this undoes the changes of commit cf6d4535cc4c ("x86:
emulation: Disable bloblist for now") as that was intended only for the
release due to time.

2220 files changed, 138419 insertions, 30016 deletions

diff --git a/.azure-pipelines.yml b/.azure-pipelines.yml
index bd197cd6e66..d5cfa59a8a6 100644
--- a/.azure-pipelines.yml
+++ b/.azure-pipelines.yml
@@ -134,8 +134,11 @@ stages:
           export USER=azure
           virtualenv -p /usr/bin/python3 /tmp/venv
           . /tmp/venv/bin/activate
-          pip install -r test/py/requirements.txt
-          pip install -r tools/buildman/requirements.txt
+          pip install -r test/py/requirements.txt \
+            -r tools/binman/requirements.txt \
+            -r tools/buildman/requirements.txt \
+            -r tools/patman/requirements.txt \
+            -r tools/u_boot_pylib/requirements.txt
           export UBOOT_TRAVIS_BUILD_DIR=/tmp/tools-only
           export PYTHONPATH=${UBOOT_TRAVIS_BUILD_DIR}/scripts/dtc/pylibfdt
           export PATH=${UBOOT_TRAVIS_BUILD_DIR}/scripts/dtc:${PATH}
@@ -163,9 +166,14 @@ stages:
       - script: |
           git config --global --add safe.directory $(work_dir)
           export USER=azure
-          pip install -r test/py/requirements.txt
-          pip install -r tools/buildman/requirements.txt
-          pip install asteval pylint==2.12.2 pyopenssl
+          virtualenv -p /usr/bin/python3 /tmp/venv
+          . /tmp/venv/bin/activate
+          pip install -r test/py/requirements.txt \
+            -r tools/binman/requirements.txt \
+            -r tools/buildman/requirements.txt \
+            -r tools/patman/requirements.txt \
+            -r tools/u_boot_pylib/requirements.txt \
+            asteval pylint==3.3.4 pyopenssl
           export PATH=${PATH}:~/.local/bin
           echo "[MASTER]" >> .pylintrc
           echo "load-plugins=pylint.extensions.docparams" >> .pylintrc
@@ -265,7 +273,13 @@ stages:
           if [ -n "\${BUILD_ENV}" ]; then
               export \${BUILD_ENV};
           fi
-          pip install -r tools/buildman/requirements.txt
+          virtualenv -p /usr/bin/python3 /tmp/venv
+          . /tmp/venv/bin/activate
+          pip install -r tools/binman/requirements.txt \
+            -r tools/buildman/requirements.txt \
+            -r test/py/requirements.txt \
+            -r tools/u_boot_pylib/requirements.txt \
+            pytest-azurepipelines
           tools/buildman/buildman -o \${UBOOT_TRAVIS_BUILD_DIR} -w -E -W -e --board \${TEST_PY_BD} \${OVERRIDE}
           cp /opt/grub/grub_x86.efi \${UBOOT_TRAVIS_BUILD_DIR}/
           cp /opt/grub/grub_x64.efi \${UBOOT_TRAVIS_BUILD_DIR}/
@@ -289,10 +303,6 @@ stages:
               /opt/coreboot/cbfstool \${UBOOT_TRAVIS_BUILD_DIR}/coreboot.rom remove -n fallback/payload;
               /opt/coreboot/cbfstool \${UBOOT_TRAVIS_BUILD_DIR}/coreboot.rom add-flat-binary -f \${UBOOT_TRAVIS_BUILD_DIR}/u-boot.bin -n fallback/payload -c LZMA -l 0x1110000 -e 0x1110000;
           fi
-          virtualenv -p /usr/bin/python3 /tmp/venv
-          . /tmp/venv/bin/activate
-          pip install -r test/py/requirements.txt
-          pip install pytest-azurepipelines
           export PATH=/opt/qemu/bin:/tmp/uboot-test-hooks/bin:\${PATH}
           export PYTHONPATH=/tmp/uboot-test-hooks/py/travis-ci
           # "\${var:+"-k \$var"}" expands to "" if \$var is empty, "-k \$var" if not
@@ -582,7 +592,10 @@ stages:
           # make environment variables available as tests are running inside a container
           export BUILDMAN="${BUILDMAN}"
           git config --global --add safe.directory ${WORK_DIR}
-          pip install -r tools/buildman/requirements.txt
+          virtualenv -p /usr/bin/python3 /tmp/venv
+          . /tmp/venv/bin/activate
+          pip install -r tools/binman/requirements.txt \
+            -r tools/buildman/requirements.txt
           EOF
           cat << "EOF" >> build.sh
           if [[ "${BUILDMAN}" != "" ]]; then
diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml
index 46226eb2fc1..0f27e67abb9 100644
--- a/.gitlab-ci.yml
+++ b/.gitlab-ci.yml
@@ -56,6 +56,11 @@ stages:
         wget -O /tmp/fip.bin https://artifacts.codelinaro.org/artifactory/linaro-419-sbsa-ref/latest/tf-a/fip.bin;
         export BINMAN_INDIRS=/tmp;
       fi
+    # Prepare python environment
+    - virtualenv -p /usr/bin/python3 /tmp/venv;
+      . /tmp/venv/bin/activate;
+      pip install -r test/py/requirements.txt -r tools/binman/requirements.txt
+        -r tools/buildman/requirements.txt -r tools/u_boot_pylib/requirements.txt
 
   after_script:
     - cp -v /tmp/${TEST_PY_BD}/*.{html,css,xml} .
@@ -91,9 +96,6 @@ stages:
         /opt/coreboot/cbfstool ${UBOOT_TRAVIS_BUILD_DIR}/coreboot.rom remove -n fallback/payload;
         /opt/coreboot/cbfstool ${UBOOT_TRAVIS_BUILD_DIR}/coreboot.rom add-flat-binary -f ${UBOOT_TRAVIS_BUILD_DIR}/u-boot.bin -n fallback/payload -c LZMA -l 0x1110000 -e 0x1110000;
       fi
-    - virtualenv -p /usr/bin/python3 /tmp/venv
-    - . /tmp/venv/bin/activate
-    - pip install -r test/py/requirements.txt
     # "${var:+"-k $var"}" expands to "" if $var is empty, "-k $var" if not
     - export PATH=/opt/qemu/bin:/tmp/uboot-test-hooks/bin:${PATH};
       export PYTHONPATH=/tmp/uboot-test-hooks/py/travis-ci;
@@ -121,9 +123,13 @@ build all platforms in a single job:
   tags:
     - ${HOST}
   script:
+    # Prepare python environment
+    - virtualenv -p /usr/bin/python3 /tmp/venv;
+      . /tmp/venv/bin/activate;
+      pip install -r tools/binman/requirements.txt
+        -r tools/buildman/requirements.txt
     - ret=0;
       git config --global --add safe.directory "${CI_PROJECT_DIR}";
-      pip install -r tools/buildman/requirements.txt;
       ./tools/buildman/buildman -o /tmp -PEWM -x xtensa || ret=$?;
       if [[ $ret -ne 0 ]]; then
         ./tools/buildman/buildman -o /tmp -seP;
@@ -180,8 +186,9 @@ Run binman, buildman, dtoc, Kconfig and patman testsuites:
       export USER=gitlab;
       virtualenv -p /usr/bin/python3 /tmp/venv;
       . /tmp/venv/bin/activate;
-      pip install -r test/py/requirements.txt;
-      pip install -r tools/buildman/requirements.txt;
+      pip install -r test/py/requirements.txt -r tools/binman/requirements.txt
+        -r tools/buildman/requirements.txt -r tools/patman/requirements.txt
+        -r tools/u_boot_pylib/requirements.txt;
       export UBOOT_TRAVIS_BUILD_DIR=/tmp/tools-only;
       export PYTHONPATH="${UBOOT_TRAVIS_BUILD_DIR}/scripts/dtc/pylibfdt";
       export PATH="${UBOOT_TRAVIS_BUILD_DIR}/scripts/dtc:${PATH}";
@@ -200,9 +207,11 @@ Run pylint:
   extends: .testsuites
   script:
     - git config --global --add safe.directory "${CI_PROJECT_DIR}"
-    - pip install -r test/py/requirements.txt
-    - pip install -r tools/buildman/requirements.txt
-    - pip install asteval pylint==2.12.2 pyopenssl
+    - virtualenv -p /usr/bin/python3 /tmp/venv
+    - . /tmp/venv/bin/activate
+    - pip install -r test/py/requirements.txt -r tools/binman/requirements.txt
+        -r tools/buildman/requirements.txt -r tools/patman/requirements.txt
+        -r tools/u_boot_pylib/requirements.txt asteval pylint==3.3.4 pyopenssl
     - export PATH=${PATH}:~/.local/bin
     - echo "[MASTER]" >> .pylintrc
     - echo "load-plugins=pylint.extensions.docparams" >> .pylintrc
@@ -556,7 +565,7 @@ coreboot test.py:
     - export USE_LABGRID_SJG=1
     # export verbose="-v"
     - ${SRC}/test/py/test.py --role ${ROLE} --build-dir "${OUT}"
-        --capture=tee-sys -k "not bootstd" || ret=$?
+        --capture=tee-sys -k "not bootstd ${TEST_PY_TEST_SPEC}" || ret=$?
     - U_BOOT_BOARD_IDENTITY="${ROLE}" u-boot-test-release || true
     - if [[ $ret -ne 0 ]]; then
         exit $ret;
@@ -693,3 +702,9 @@ vf2:
   variables:
     ROLE: vf2
   <<: *lab_dfn
+
+qemu-x86_64:
+  variables:
+    ROLE: qemu-x86_64
+    TEST_PY_TEST_SPEC: "and not sleep"
+  <<: *lab_dfn
diff --git a/Kconfig b/Kconfig
index 6379a454166..a508c5430f0 100644
--- a/Kconfig
+++ b/Kconfig
@@ -27,6 +27,17 @@ config DEPRECATED
 	  code that relies on deprecated features that will be removed and
 	  the conversion deadline has passed.
 
+config WERROR
+	bool "Compile U-Boot with warnings as errors"
+	help
+	  A U-Boot build should not cause any compiler warnings, and this
+	  enables the '-Werror' flag to enforce that rule.
+
+	  However, if you have a new (or very old) compiler or linker with odd
+	  and unusual warnings, or you have some architecture with problems,
+	  you may need to disable this config option in order to
+	  successfully build U-Boot.
+
 config LOCALVERSION
 	string "Local version - append to U-Boot release"
 	help
@@ -737,7 +748,7 @@ source "dts/Kconfig"
 
 source "env/Kconfig"
 
-menu Networking
+menu "Networking"
 
 choice
 	prompt "Networking stack"
diff --git a/MAINTAINERS b/MAINTAINERS
index 042d3f6160a..a0b06e9ee24 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -151,9 +151,11 @@ F:	cmd/arm/
 ARM ALTERA SOCFPGA
 M:	Marek Vasut <marex@denx.de>
 M:	Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
-M:	Tien Fong Chee <tien.fong.chee@intel.com>
+M:	Tien Fong Chee <tien.fong.chee@altera.com>
+M:	Tingting Meng <tingting.meng@altera.com>
 S:	Maintained
 T:	git https://source.denx.de/u-boot/custodians/u-boot-socfpga.git
+F:	drivers/ddr/altera/
 F:	arch/arm/mach-socfpga/
 F:	drivers/sysreset/sysreset_socfpga*
 
@@ -313,6 +315,7 @@ F:	board/freescale/*mx*/
 F:	board/freescale/common/
 F:	common/spl/spl_imx_container.c
 F:	doc/imx/
+F:	drivers/mailbox/imx-mailbox.c
 F:	drivers/serial/serial_mxc.c
 F:	include/imx_container.h
 
@@ -629,11 +632,24 @@ F:	arch/arm/mach-sc5xx/
 F:	board/adi/
 F:	doc/device-tree-bindings/arm/adi/adi,sc5xx.yaml
 F:	doc/device-tree-bindings/clock/adi,sc5xx-clocks.yaml
+F:	doc/device-tree-bindings/pinctrl/adi,adsp-pinctrl.yaml
 F:	doc/device-tree-bindings/timer/adi,sc5xx-gptimer.yaml
 F:	drivers/clk/adi/
+F:	drivers/dma/adi_dma.c
+F:	drivers/gpio/adp5588_gpio.c
+F:	drivers/gpio/gpio-adi-adsp.c
+F:	drivers/i2c/adi_i2c.c
+F:	drivers/mmc/adi_sdhci.c
+F:	drivers/net/dwc_eth_qos_adi.c
+F:	drivers/pinctrl/pinctrl-adi-adsp.c
+F:	drivers/remoteproc/adi_sc5xx_rproc.c
 F:	drivers/serial/serial_adi_uart4.c
+F:	drivers/spi/adi_spi3.c
 F:	drivers/timer/adi_sc5xx_timer.c
+F:	drivers/usb/musb-new/sc5xx.c
+F:	drivers/watchdog/adi_wdt.c
 F:	include/configs/sc5*
+F:	include/dt-bindings/pinctrl/adi-adsp.h
 F:	include/env/adi/
 
 ARM SNAPDRAGON
@@ -1265,6 +1281,13 @@ T:	git git://github.com/ARM-software/u-boot.git
 F:	drivers/video/mali_dp.c
 F:	drivers/i2c/i2c-versatile.c
 
+MEMBUF
+M:	Simon Glass <sjg@chromium.org>
+S:	Maintained
+T:	git https://source.denx.de/u-boot/u-boot.git
+F:	include/membuf.h
+F:	lib/membuf.c
+
 MICROBLAZE
 M:	Michal Simek <monstr@monstr.eu>
 S:	Maintained
diff --git a/Makefile b/Makefile
index a7593e8a168..e83672b1823 100644
--- a/Makefile
+++ b/Makefile
@@ -406,6 +406,7 @@ LDR		= $(CROSS_COMPILE)ldr
 STRIP		= $(CROSS_COMPILE)strip
 OBJCOPY		= $(CROSS_COMPILE)objcopy
 OBJDUMP		= $(CROSS_COMPILE)objdump
+READELF		= $(CROSS_COMPILE)readelf
 LEX		= flex
 YACC		= bison
 AWK		= awk
@@ -820,6 +821,7 @@ KBUILD_AFLAGS += $(KAFLAGS)
 KBUILD_CFLAGS += $(KCFLAGS)
 
 KBUILD_LDFLAGS  += -z noexecstack
+KBUILD_LDFLAGS  += -z norelro
 KBUILD_LDFLAGS  += $(call ld-option,--no-warn-rwx-segments)
 
 KBUILD_HOSTCFLAGS += $(if $(CONFIG_TOOLS_DEBUG),-g)
@@ -878,7 +880,6 @@ libs-y += drivers/usb/dwc3/
 libs-y += drivers/usb/common/
 libs-y += drivers/usb/emul/
 libs-y += drivers/usb/eth/
-libs-$(CONFIG_USB_DEVICE) += drivers/usb/gadget/
 libs-$(CONFIG_USB_GADGET) += drivers/usb/gadget/
 libs-$(CONFIG_USB_GADGET) += drivers/usb/gadget/udc/
 libs-y += drivers/usb/host/
@@ -893,9 +894,6 @@ ifdef CONFIG_POST
 libs-y += post/
 endif
 libs-$(CONFIG_$(PHASE_)UNIT_TEST) += test/
-libs-$(CONFIG_UT_ENV) += test/env/
-libs-$(CONFIG_UT_OPTEE) += test/optee/
-libs-$(CONFIG_UT_OVERLAY) += test/overlay/
 
 libs-y += $(if $(wildcard $(srctree)/board/$(BOARDDIR)/Makefile),board/$(BOARDDIR)/)
 
@@ -1019,8 +1017,10 @@ INPUTS-$(CONFIG_EFI_STUB) += u-boot-payload.efi
 
 # Generate this input file for binman
 ifeq ($(CONFIG_SPL),)
+ifneq ($(patsubst "%",%,$(CONFIG_MTK_BROM_HEADER_INFO)),)
 INPUTS-$(CONFIG_ARCH_MEDIATEK) += u-boot-mtk.bin
 endif
+endif
 
 # Add optional build target if defined in board/cpu/soc headers
 ifneq ($(CONFIG_BUILD_TARGET),)
@@ -1067,7 +1067,7 @@ quiet_cmd_objcopy = OBJCOPY $@
 cmd_objcopy = $(OBJCOPY) --gap-fill=0xff $(OBJCOPYFLAGS) \
 	$(OBJCOPYFLAGS_$(@F)) $< $@
 
-# Provide a version which does not do this, for use by EFI
+# Provide a version which does not do this, for use by EFI and hex/srec
 quiet_cmd_zobjcopy = OBJCOPY $@
 cmd_zobjcopy = $(OBJCOPY) $(OBJCOPYFLAGS) $(OBJCOPYFLAGS_$(@F)) $< $@
 
@@ -1282,7 +1282,7 @@ OBJCOPYFLAGS_u-boot.hex := -O ihex
 OBJCOPYFLAGS_u-boot.srec := -O srec
 
 u-boot.hex u-boot.srec: u-boot FORCE
-	$(call if_changed,objcopy)
+	$(call if_changed,zobjcopy)
 
 OBJCOPYFLAGS_u-boot-elf.srec := $(OBJCOPYFLAGS_u-boot.srec)
 
@@ -1296,12 +1296,12 @@ OBJCOPYFLAGS_u-boot-elf.srec += --change-addresses=0x50000000
 endif
 
 u-boot-elf.srec: u-boot.elf FORCE
-	$(call if_changed,objcopy)
+	$(call if_changed,zobjcopy)
 
 OBJCOPYFLAGS_u-boot-spl.srec = $(OBJCOPYFLAGS_u-boot.srec)
 
 spl/u-boot-spl.srec: spl/u-boot-spl FORCE
-	$(call if_changed,objcopy)
+	$(call if_changed,zobjcopy)
 
 %.scif: %.srec
 	$(Q)$(MAKE) $(build)=arch/arm/mach-renesas $@
@@ -1436,7 +1436,7 @@ OBJCOPYFLAGS_u-boot.ldr.hex := -I binary -O ihex
 OBJCOPYFLAGS_u-boot.ldr.srec := -I binary -O srec
 
 u-boot.ldr.hex u-boot.ldr.srec: u-boot.ldr FORCE
-	$(call if_changed,objcopy)
+	$(call if_changed,zobjcopy)
 
 ifdef CONFIG_SPL_LOAD_FIT
 MKIMAGEFLAGS_u-boot.img = -f auto -A $(ARCH) -T firmware -C none -O u-boot \
@@ -1865,6 +1865,7 @@ quiet_cmd_gen_envp = ENVP    $@
 		$(CPP) -P $(cpp_flags) -x assembler-with-cpp -undef \
 			-D__ASSEMBLY__ \
 			-D__UBOOT_CONFIG__ \
+			-DDEFAULT_DEVICE_TREE=$(subst ",,$(CONFIG_DEFAULT_DEVICE_TREE)) \
 			-I . -I include -I $(srctree)/include \
 			-include linux/kconfig.h -include include/config.h \
 			-I$(srctree)/arch/$(ARCH)/include \
@@ -2176,7 +2177,7 @@ System.map:	u-boot
 # ARM relocations should all be R_ARM_RELATIVE (32-bit) or
 # R_AARCH64_RELATIVE (64-bit).
 checkarmreloc: u-boot
-	@RELOC="`$(CROSS_COMPILE)readelf -r -W $< | cut -d ' ' -f 4 | \
+	@RELOC="`$(READELF) -r -W $< | cut -d ' ' -f 4 | \
 		grep R_A | sort -u`"; \
 	if test "$$RELOC" != "R_ARM_RELATIVE" -a \
 		 "$$RELOC" != "R_AARCH64_RELATIVE"; then \
@@ -2515,7 +2516,7 @@ cmd_genenv = \
 	sed -e '/^\s*$$/d' | \
 	sort -t '=' -k 1,1 -s -o $@
 
-u-boot-initial-env: scripts_basic $(env_h) FORCE
+u-boot-initial-env: scripts_basic $(version_h) $(env_h) include/config.h FORCE
 	$(Q)$(MAKE) $(build)=tools $(objtree)/tools/printinitialenv
 	$(call if_changed,genenv)
 
diff --git a/README b/README
index 067c1ee2b64..334bbcf0dd1 100644
--- a/README
+++ b/README
@@ -1,4 +1,4 @@
-# SPDX-License-Identifier: GPL-2.0+
+ # SPDX-License-Identifier: GPL-2.0+
 #
 # (C) Copyright 2000 - 2013
 # Wolfgang Denk, DENX Software Engineering, wd@denx.de.
diff --git a/arch/arc/lib/cache.c b/arch/arc/lib/cache.c
index 5169fc627fa..08f9e7dceac 100644
--- a/arch/arc/lib/cache.c
+++ b/arch/arc/lib/cache.c
@@ -8,6 +8,7 @@
 #include <asm/global_data.h>
 #include <linux/bitops.h>
 #include <linux/compiler.h>
+#include <linux/errno.h>
 #include <linux/kernel.h>
 #include <linux/log2.h>
 #include <asm/arcregs.h>
@@ -819,3 +820,8 @@ void sync_n_cleanup_cache_all(void)
 
 	__ic_entire_invalidate();
 }
+
+int __weak pgprot_set_attrs(phys_addr_t addr, size_t size, enum pgprot_attrs perm)
+{
+	return -ENOSYS;
+}
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index da6f1174934..b7311d3b754 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -600,6 +600,13 @@ choice
 	prompt "Target select"
 	default TARGET_HIKEY
 
+config ARCH_AIROHA
+	bool "Airoha SoCs"
+	select DM
+	select OF_CONTROL
+	help
+	  Support for the Airoha soc.
+
 config ARCH_AT91
 	bool "Atmel AT91"
 	select GPIO_EXTRA_HEADER
@@ -648,7 +655,6 @@ config ARCH_MVEBU
 	select SPL_TIMER if SPL
 	select TIMER if !ARM64
 	select OF_CONTROL
-	select OF_SEPARATE
 	select SPI
 	imply CMD_DM
 
@@ -1110,13 +1116,14 @@ config ARCH_SNAPDRAGON
 	select GPIO_EXTRA_HEADER
 	select MSM_SMEM
 	select OF_CONTROL
-	select OF_SEPARATE
 	select SMEM
 	select SPMI
 	select BOARD_LATE_INIT
 	select OF_BOARD
 	select SAVE_PREV_BL_FDT_ADDR
 	select LINUX_KERNEL_IMAGE_HEADER if !ENABLE_ARM_SOC_BOOT0_HOOK
+	select SYSRESET
+	select SYSRESET_PSCI
 	imply OF_UPSTREAM
 	imply CMD_DM
 
@@ -1128,7 +1135,6 @@ config ARCH_SOCFPGA
 	select CPU_V7A if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
 	select DM
 	select DM_SERIAL
-	select GICV2
 	select GPIO_EXTRA_HEADER
 	select ENABLE_ARM_SOC_BOOT0_HOOK if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
 	select OF_CONTROL
@@ -1150,6 +1156,7 @@ config ARCH_SOCFPGA
 	select SYSRESET_SOCFPGA if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
 	select SYSRESET_SOCFPGA_SOC64 if !TARGET_SOCFPGA_AGILEX5 && \
 	  TARGET_SOCFPGA_SOC64
+	select SYSRESET_PSCI if TARGET_SOCFPGA_AGILEX5
 	imply CMD_DM
 	imply CMD_MTDPARTS
 	imply CRC32_VERIFY
@@ -1185,7 +1192,6 @@ config ARCH_SUNXI
 	select DM_SERIAL
 	select OF_BOARD_SETUP
 	select OF_CONTROL
-	select OF_SEPARATE
 	select PINCTRL
 	select SPECIFY_CONSOLE_INDEX
 	select SPL_SEPARATE_BSS if SPL
@@ -2251,6 +2257,8 @@ config SYS_KWD_CONFIG
 	  Path within the source directory to the kwbimage.cfg file to use
 	  when packaging the U-Boot image for use.
 
+source "arch/arm/mach-airoha/Kconfig"
+
 source "arch/arm/mach-apple/Kconfig"
 
 source "arch/arm/mach-aspeed/Kconfig"
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 7334e79965f..5ecadb2ef1b 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -51,6 +51,7 @@ PLATFORM_CPPFLAGS += $(arch-y) $(tune-y)
 
 # Machine directory name.  This list is sorted alphanumerically
 # by CONFIG_* macro name.
+machine-$(CONFIG_ARCH_AIROHA)		+= airoha
 machine-$(CONFIG_ARCH_APPLE)		+= apple
 machine-$(CONFIG_ARCH_ASPEED)		+= aspeed
 machine-$(CONFIG_ARCH_AT91)		+= at91
diff --git a/arch/arm/cpu/arm926ejs/cache.c b/arch/arm/cpu/arm926ejs/cache.c
index 5b87a3af91b..71b8ad0f71d 100644
--- a/arch/arm/cpu/arm926ejs/cache.c
+++ b/arch/arm/cpu/arm926ejs/cache.c
@@ -5,6 +5,7 @@
  */
 #include <cpu_func.h>
 #include <asm/cache.h>
+#include <linux/errno.h>
 #include <linux/types.h>
 
 #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
@@ -88,3 +89,8 @@ void enable_caches(void)
 	dcache_enable();
 #endif
 }
+
+int __weak pgprot_set_attrs(phys_addr_t addr, size_t size, enum pgprot_attrs perm)
+{
+	return -ENOSYS;
+}
diff --git a/arch/arm/cpu/armv7/cache_v7.c b/arch/arm/cpu/armv7/cache_v7.c
index d11420d2fdd..371dc92cd46 100644
--- a/arch/arm/cpu/armv7/cache_v7.c
+++ b/arch/arm/cpu/armv7/cache_v7.c
@@ -6,6 +6,7 @@
  */
 #include <cpu_func.h>
 #include <asm/cache.h>
+#include <linux/errno.h>
 #include <linux/types.h>
 #include <asm/armv7.h>
 #include <asm/utils.h>
@@ -209,3 +210,8 @@ __weak void v7_outer_cache_flush_all(void) {}
 __weak void v7_outer_cache_inval_all(void) {}
 __weak void v7_outer_cache_flush_range(u32 start, u32 end) {}
 __weak void v7_outer_cache_inval_range(u32 start, u32 end) {}
+
+int __weak pgprot_set_attrs(phys_addr_t addr, size_t size, enum pgprot_attrs perm)
+{
+	return -ENOSYS;
+}
diff --git a/arch/arm/cpu/armv7/exception_level.c b/arch/arm/cpu/armv7/exception_level.c
index 7baade61b07..a55c158ce51 100644
--- a/arch/arm/cpu/armv7/exception_level.c
+++ b/arch/arm/cpu/armv7/exception_level.c
@@ -11,9 +11,9 @@
 #include <bootm.h>
 #include <cpu_func.h>
 #include <log.h>
+#include <setjmp.h>
 #include <asm/armv7.h>
 #include <asm/secure.h>
-#include <asm/setjmp.h>
 
 /**
  * entry_non_secure() - entry point when switching to non-secure mode
@@ -24,7 +24,7 @@
  *
  * @non_secure_jmp:	jump buffer for restoring stack and registers
  */
-static void entry_non_secure(struct jmp_buf_data *non_secure_jmp)
+static void entry_non_secure(jmp_buf non_secure_jmp)
 {
 	dcache_enable();
 	debug("Reached non-secure mode\n");
@@ -42,10 +42,10 @@ static void entry_non_secure(struct jmp_buf_data *non_secure_jmp)
 void switch_to_non_secure_mode(void)
 {
 	static bool is_nonsec;
-	struct jmp_buf_data non_secure_jmp;
+	jmp_buf non_secure_jmp;
 
 	if (armv7_boot_nonsec() && !is_nonsec) {
-		if (setjmp(&non_secure_jmp))
+		if (setjmp(non_secure_jmp))
 			return;
 		dcache_disable();	/* flush cache before switch to HYP */
 		armv7_init_nonsec();
diff --git a/arch/arm/cpu/armv7/lowlevel_init.S b/arch/arm/cpu/armv7/lowlevel_init.S
index a6c844b7e3d..72b7b7d082c 100644
--- a/arch/arm/cpu/armv7/lowlevel_init.S
+++ b/arch/arm/cpu/armv7/lowlevel_init.S
@@ -26,8 +26,8 @@ WEAK(lowlevel_init)
 	/*
 	 * Setup a temporary stack. Global data is not available yet.
 	 */
-#if defined(CONFIG_XPL_BUILD) && defined(CONFIG_SPL_STACK)
-	ldr	sp, =CONFIG_SPL_STACK
+#if CONFIG_IS_ENABLED(HAVE_INIT_STACK)
+	ldr	sp, =CONFIG_VAL(STACK)
 #else
 	ldr	sp, =SYS_INIT_SP_ADDR
 #endif
diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S
index b63481b43ca..959251957de 100644
--- a/arch/arm/cpu/armv7/start.S
+++ b/arch/arm/cpu/armv7/start.S
@@ -279,8 +279,8 @@ ENTRY(cpu_init_cp15)
 	orr	r2, r4, r2		@ r2 has combined CPU variant + revision
 
 /* Early stack for ERRATA that needs into call C code */
-#if defined(CONFIG_XPL_BUILD) && defined(CONFIG_SPL_STACK)
-	ldr	r0, =(CONFIG_SPL_STACK)
+#if CONFIG_IS_ENABLED(HAVE_INIT_STACK)
+	ldr	r0, =CONFIG_VAL(STACK)
 #else
 	ldr	r0, =(SYS_INIT_SP_ADDR)
 #endif
diff --git a/arch/arm/cpu/armv7m/cache.c b/arch/arm/cpu/armv7m/cache.c
index b6d08b7aad7..8e7db734055 100644
--- a/arch/arm/cpu/armv7m/cache.c
+++ b/arch/arm/cpu/armv7m/cache.c
@@ -11,6 +11,7 @@
 #include <asm/cache.h>
 #include <asm/io.h>
 #include <linux/bitops.h>
+#include <linux/errno.h>
 
 /* Cache maintenance operation registers */
 
@@ -370,3 +371,8 @@ void enable_caches(void)
 	dcache_enable();
 #endif
 }
+
+int __weak pgprot_set_attrs(phys_addr_t addr, size_t size, enum pgprot_attrs perm)
+{
+	return -ENOSYS;
+}
diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c
index 5d6953ffedd..1c1e33bec24 100644
--- a/arch/arm/cpu/armv8/cache_v8.c
+++ b/arch/arm/cpu/armv8/cache_v8.c
@@ -14,6 +14,7 @@
 #include <asm/global_data.h>
 #include <asm/system.h>
 #include <asm/armv8/mmu.h>
+#include <linux/errno.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -421,7 +422,7 @@ static int count_ranges(void)
 	return count;
 }
 
-#define ALL_ATTRS (3 << 8 | PMD_ATTRINDX_MASK)
+#define ALL_ATTRS (3 << 8 | PMD_ATTRMASK)
 #define PTE_IS_TABLE(pte, level) (pte_type(&(pte)) == PTE_TYPE_TABLE && (level) < 3)
 
 enum walker_state {
@@ -568,6 +569,24 @@ static void pretty_print_table_attrs(u64 pte)
 static void pretty_print_block_attrs(u64 pte)
 {
 	u64 attrs = pte & PMD_ATTRINDX_MASK;
+	u64 perm_attrs = pte & PMD_ATTRMASK;
+	char mem_attrs[16] = { 0 };
+	int cnt = 0;
+
+	if (perm_attrs & PTE_BLOCK_PXN)
+		cnt += snprintf(mem_attrs + cnt, sizeof(mem_attrs) - cnt, "PXN ");
+	if (perm_attrs & PTE_BLOCK_UXN) {
+		if (get_effective_el() == 1)
+			cnt += snprintf(mem_attrs + cnt, sizeof(mem_attrs) - cnt, "UXN ");
+		else
+			cnt += snprintf(mem_attrs + cnt, sizeof(mem_attrs) - cnt, "XN ");
+	}
+	if (perm_attrs & PTE_BLOCK_RO)
+		cnt += snprintf(mem_attrs + cnt, sizeof(mem_attrs) - cnt, "RO");
+	if (!mem_attrs[0])
+		snprintf(mem_attrs, sizeof(mem_attrs), "RWX ");
+
+	printf(" | %-10s", mem_attrs);
 
 	switch (attrs) {
 	case PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE):
@@ -613,6 +632,7 @@ static void print_pte(u64 pte, int level)
 {
 	if (PTE_IS_TABLE(pte, level)) {
 		printf(" %-5s", "Table");
+		printf(" %-12s", "|");
 		pretty_print_table_attrs(pte);
 	} else {
 		pretty_print_pte_type(pte);
@@ -642,9 +662,9 @@ static bool pagetable_print_entry(u64 start_attrs, u64 end, int va_bits, int lev
 
 	printf("%*s", indent * 2, "");
 	if (PTE_IS_TABLE(start_attrs, level))
-		printf("[%#011llx]%14s", _addr, "");
+		printf("[%#016llx]%19s", _addr, "");
 	else
-		printf("[%#011llx - %#011llx]", _addr, end);
+		printf("[%#016llx - %#016llx]", _addr, end);
 
 	printf("%*s | ", (3 - level) * 2, "");
 	print_pte(start_attrs, level);
@@ -952,61 +972,109 @@ void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
 	flush_dcache_range(real_start, real_start + real_size);
 }
 
-/*
- * Modify MMU table for a region with updated PXN/UXN/Memory type/valid bits.
- * The procecess is break-before-make. The target region will be marked as
- * invalid during the process of changing.
- */
-void mmu_change_region_attr(phys_addr_t addr, size_t siz, u64 attrs)
+void mmu_change_region_attr_nobreak(phys_addr_t addr, size_t siz, u64 attrs)
 {
 	int level;
 	u64 r, size, start;
 
-	start = addr;
-	size = siz;
 	/*
 	 * Loop through the address range until we find a page granule that fits
-	 * our alignment constraints, then set it to "invalid".
+	 * our alignment constraints and set the new permissions
 	 */
+	start = addr;
+	size = siz;
 	while (size > 0) {
 		for (level = 1; level < 4; level++) {
-			/* Set PTE to fault */
-			r = set_one_region(start, size, PTE_TYPE_FAULT, true,
-					   level);
+			/* Set PTE to new attributes */
+			r = set_one_region(start, size, attrs, true, level);
 			if (r) {
-				/* PTE successfully invalidated */
+				/* PTE successfully updated */
 				size -= r;
 				start += r;
 				break;
 			}
 		}
 	}
-
 	flush_dcache_range(gd->arch.tlb_addr,
 			   gd->arch.tlb_addr + gd->arch.tlb_size);
 	__asm_invalidate_tlb_all();
+}
+
+/*
+ * Modify MMU table for a region with updated PXN/UXN/Memory type/valid bits.
+ * The procecess is break-before-make. The target region will be marked as
+ * invalid during the process of changing.
+ */
+void mmu_change_region_attr(phys_addr_t addr, size_t siz, u64 attrs)
+{
+	int level;
+	u64 r, size, start;
 
+	start = addr;
+	size = siz;
 	/*
 	 * Loop through the address range until we find a page granule that fits
-	 * our alignment constraints, then set it to the new cache attributes
+	 * our alignment constraints, then set it to "invalid".
 	 */
-	start = addr;
-	size = siz;
 	while (size > 0) {
 		for (level = 1; level < 4; level++) {
-			/* Set PTE to new attributes */
-			r = set_one_region(start, size, attrs, true, level);
+			/* Set PTE to fault */
+			r = set_one_region(start, size, PTE_TYPE_FAULT, true,
+					   level);
 			if (r) {
-				/* PTE successfully updated */
+				/* PTE successfully invalidated */
 				size -= r;
 				start += r;
 				break;
 			}
 		}
 	}
+
 	flush_dcache_range(gd->arch.tlb_addr,
 			   gd->arch.tlb_addr + gd->arch.tlb_size);
 	__asm_invalidate_tlb_all();
+
+	mmu_change_region_attr_nobreak(addr, siz, attrs);
+}
+
+int pgprot_set_attrs(phys_addr_t addr, size_t size, enum pgprot_attrs perm)
+{
+	u64 attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_INNER_SHARE | PTE_TYPE_VALID;
+
+	switch (perm) {
+	case MMU_ATTR_RO:
+		/*
+		 * get_effective_el() will return 1 if
+		 * - Running in EL1 so we assume an EL1 translation regime
+		 *   with HCR_EL2.{NV, NV1} != {1,1}
+		 * - Running in EL2 with HCR_EL2.E2H = 1 so we assume an
+		 *   EL2&0 translation regime. Since we don't have accesses
+		 *   from EL0 we don't have to check HCR_EL2.TGE
+		 *
+		 * Both of these requires PXN to be set
+		 */
+		if (get_effective_el() == 1)
+			attrs |= PTE_BLOCK_PXN | PTE_BLOCK_UXN | PTE_BLOCK_RO;
+		else
+			attrs |= PTE_BLOCK_UXN | PTE_BLOCK_RO;
+		break;
+	case MMU_ATTR_RX:
+		attrs |= PTE_BLOCK_RO;
+		break;
+	case MMU_ATTR_RW:
+		if (get_effective_el() == 1)
+			attrs |= PTE_BLOCK_PXN | PTE_BLOCK_UXN;
+		else
+			attrs |= PTE_BLOCK_UXN;
+		break;
+	default:
+		log_err("Unknown attribute %d\n", perm);
+		return -EINVAL;
+	}
+
+	mmu_change_region_attr_nobreak(addr, size, attrs);
+
+	return 0;
 }
 
 #else	/* !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */
@@ -1112,3 +1180,8 @@ void __weak enable_caches(void)
 	icache_enable();
 	dcache_enable();
 }
+
+void arch_dump_mem_attrs(void)
+{
+	dump_pagetable(gd->arch.tlb_addr, get_tcr(NULL, NULL));
+}
diff --git a/arch/arm/cpu/armv8/exception_level.c b/arch/arm/cpu/armv8/exception_level.c
index 85c78f55789..746737861e7 100644
--- a/arch/arm/cpu/armv8/exception_level.c
+++ b/arch/arm/cpu/armv8/exception_level.c
@@ -11,8 +11,8 @@
 #include <bootm.h>
 #include <cpu_func.h>
 #include <log.h>
+#include <setjmp.h>
 #include <asm/cache.h>
-#include <asm/setjmp.h>
 
 /**
  * entry_non_secure() - entry point when switching to non-secure mode
@@ -23,7 +23,7 @@
  *
  * @non_secure_jmp:	jump buffer for restoring stack and registers
  */
-static void entry_non_secure(struct jmp_buf_data *non_secure_jmp)
+static void entry_non_secure(jmp_buf non_secure_jmp)
 {
 	dcache_enable();
 	debug("Reached non-secure mode\n");
@@ -42,11 +42,11 @@ static void entry_non_secure(struct jmp_buf_data *non_secure_jmp)
  */
 void switch_to_non_secure_mode(void)
 {
-	struct jmp_buf_data non_secure_jmp;
+	jmp_buf non_secure_jmp;
 
 	/* On AArch64 we need to make sure we call our payload in < EL3 */
 	if (current_el() == 3) {
-		if (setjmp(&non_secure_jmp))
+		if (setjmp(non_secure_jmp))
 			return;
 		dcache_disable();	/* flush cache before switch to EL2 */
 
diff --git a/arch/arm/cpu/armv8/fel_utils.S b/arch/arm/cpu/armv8/fel_utils.S
index 939869b9ffa..f7707acdf1a 100644
--- a/arch/arm/cpu/armv8/fel_utils.S
+++ b/arch/arm/cpu/armv8/fel_utils.S
@@ -63,9 +63,12 @@ ENTRY(return_to_fel)
 1:	wfi
 	b	1b
 
+fel_stash_addr:			// must immediately precede back_in_32:
+	.word   0x00000000	// receives fel_stash addr, by AA64 code above
+
 /* AArch32 code to restore the state from fel_stash and return back to FEL. */
 back_in_32:
-	.word	0xe59f0028	// ldr	r0, [pc, #40]	; load fel_stash address
+	.word	0xe51f000c	// ldr	r0, [pc, #-12]  ; load fel_stash address
 	.word	0xe5901008	// ldr	r1, [r0, #8]
 	.word	0xe129f001	// msr	CPSR_fc, r1
 	.word	0xf57ff06f	// isb
@@ -77,6 +80,4 @@ back_in_32:
 	.word	0xee011f10	// mcr	15, 0, r1, cr1, cr0, {0}  ; SCTLR
 	.word	0xf57ff06f	// isb
 	.word	0xe12fff1e	// bx	lr		; return to FEL
-fel_stash_addr:
-	.word   0x00000000	// receives fel_stash addr, by AA64 code above
 ENDPROC(return_to_fel)
diff --git a/arch/arm/cpu/armv8/spl_data.c b/arch/arm/cpu/armv8/spl_data.c
index 259b49ff364..492353c93df 100644
--- a/arch/arm/cpu/armv8/spl_data.c
+++ b/arch/arm/cpu/armv8/spl_data.c
@@ -5,23 +5,28 @@
 
 #include <spl.h>
 
+char __data_start[0] __section(".__data_start");
 char __data_save_start[0] __section(".__data_save_start");
 char __data_save_end[0] __section(".__data_save_end");
 
 u32 cold_reboot_flag = 1;
 
+u32 __weak reset_flag(void)
+{
+	return 1;
+}
+
 void spl_save_restore_data(void)
 {
 	u32 data_size = __data_save_end - __data_save_start;
+	cold_reboot_flag = reset_flag();
 
 	if (cold_reboot_flag == 1) {
 		/* Save data section to data_save section */
-		memcpy(__data_save_start, __data_save_start - data_size,
-		       data_size);
+		memcpy(__data_save_start, __data_start, data_size);
 	} else {
 		/* Restore the data_save section to data section */
-		memcpy(__data_save_start - data_size, __data_save_start,
-		       data_size);
+		memcpy(__data_start, __data_save_start, data_size);
 	}
 
 	cold_reboot_flag++;
diff --git a/arch/arm/cpu/armv8/u-boot-spl.lds b/arch/arm/cpu/armv8/u-boot-spl.lds
index fed69644b55..c4f83ec9cfc 100644
--- a/arch/arm/cpu/armv8/u-boot-spl.lds
+++ b/arch/arm/cpu/armv8/u-boot-spl.lds
@@ -37,6 +37,7 @@ SECTIONS
 
 	.data : {
 		. = ALIGN(8);
+		*(.__data_start)
 		*(.data*)
 	} >.sram
 
diff --git a/arch/arm/cpu/armv8/u-boot.lds b/arch/arm/cpu/armv8/u-boot.lds
index 857f44412e0..f4ce98c82c8 100644
--- a/arch/arm/cpu/armv8/u-boot.lds
+++ b/arch/arm/cpu/armv8/u-boot.lds
@@ -36,9 +36,18 @@ SECTIONS
                 __efi_runtime_stop = .;
 	}
 
+#ifdef CONFIG_MMU_PGPROT
+	.text_rest ALIGN(CONSTANT(COMMONPAGESIZE)) :
+#else
 	.text_rest :
+#endif
 	{
+		__text_start = .;
 		*(.text*)
+#ifdef CONFIG_MMU_PGPROT
+		. = ALIGN(CONSTANT(COMMONPAGESIZE));
+#endif
+		__text_end = .;
 	}
 
 #ifdef CONFIG_ARMV8_PSCI
@@ -97,35 +106,43 @@ SECTIONS
 		LONG(0x1d1071c);	/* Must output something to reset LMA */
 	}
 #endif
-
-	. = ALIGN(8);
-	.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
-
-	. = ALIGN(8);
-	.data : {
-		*(.data*)
+	.efi_runtime_rel : {
+                __efi_runtime_rel_start = .;
+		*(.rel*.efi_runtime)
+		*(.rel*.efi_runtime.*)
+                __efi_runtime_rel_stop = .;
 	}
 
-	. = ALIGN(8);
-
-	. = .;
+#ifdef CONFIG_MMU_PGPROT
+	.rodata ALIGN(CONSTANT(COMMONPAGESIZE)): {
+#else
+	.rodata ALIGN(8) : {
+#endif
+		__start_rodata = .;
+		*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+	}
 
-	. = ALIGN(8);
-	__u_boot_list : {
+	__u_boot_list ALIGN(8) : {
 		KEEP(*(SORT(__u_boot_list*)));
+#ifdef CONFIG_MMU_PGPROT
+		. = ALIGN(CONSTANT(COMMONPAGESIZE));
+#endif
+		__end_rodata = .;
 	}
 
-	.efi_runtime_rel : {
-                __efi_runtime_rel_start = .;
-		*(.rel*.efi_runtime)
-		*(.rel*.efi_runtime.*)
-                __efi_runtime_rel_stop = .;
+#ifdef CONFIG_MMU_PGPROT
+	.data ALIGN(CONSTANT(COMMONPAGESIZE)) : {
+#else
+	.data ALIGN(8) : {
+#endif
+	    __start_data = .;
+		*(.data*)
 	}
 
 	. = ALIGN(8);
 	__image_copy_end = .;
 
-	.rela.dyn : {
+	.rela.dyn ALIGN(8) : {
 		__rel_dyn_start = .;
 		*(.rela*)
 		__rel_dyn_end = .;
@@ -136,11 +153,15 @@ SECTIONS
 	/*
 	 * arch/arm/lib/crt0_64.S assumes __bss_start - __bss_end % 8 == 0
 	 */
-	.bss ALIGN(8) : {
+	.bss ADDR(.rela.dyn) (OVERLAY) : {
 		__bss_start = .;
 		*(.bss*)
 		. = ALIGN(8);
 		__bss_end = .;
+#ifdef CONFIG_MMU_PGPROT
+		. = ALIGN(CONSTANT(COMMONPAGESIZE));
+#endif
+		__end_data = .;
 	}
 
 	/DISCARD/ : { *(.dynsym) }
diff --git a/arch/arm/cpu/u-boot.lds b/arch/arm/cpu/u-boot.lds
index 2f50087f57a..817e7a983ae 100644
--- a/arch/arm/cpu/u-boot.lds
+++ b/arch/arm/cpu/u-boot.lds
@@ -169,15 +169,6 @@ SECTIONS
 	_end = .;
 	_image_binary_end = .;
 
-	/*
-	 * Deprecated: this MMU section is used by pxa at present but
-	 * should not be used by new boards/CPUs.
-	 */
-	. = ALIGN(4096);
-	.mmutable : {
-		*(.mmutable)
-	}
-
 /*
  * These sections occupy the same memory, but their lifetimes do
  * not overlap: U-Boot initializes .bss only after applying dynamic
@@ -190,14 +181,14 @@ SECTIONS
 		__bss_end = .;
 	}
 
-	.dynsym _image_binary_end : { *(.dynsym) }
-	.dynbss : { *(.dynbss) }
-	.dynstr : { *(.dynstr*) }
-	.dynamic : { *(.dynamic*) }
-	.plt : { *(.plt*) }
-	.interp : { *(.interp*) }
-	.gnu.hash : { *(.gnu.hash) }
-	.gnu : { *(.gnu*) }
-	.ARM.exidx : { *(.ARM.exidx*) }
-	.gnu.linkonce.armexidx : { *(.gnu.linkonce.armexidx.*) }
+	/DISCARD/ : { *(.dynsym) }
+	/DISCARD/ : { *(.dynbss) }
+	/DISCARD/ : { *(.dynstr*) }
+	/DISCARD/ : { *(.dynamic*) }
+	/DISCARD/ : { *(.plt*) }
+	/DISCARD/ : { *(.interp*) }
+	/DISCARD/ : { *(.gnu.hash) }
+	/DISCARD/ : { *(.gnu*) }
+	/DISCARD/ : { *(.ARM.exidx*) }
+	/DISCARD/ : { *(.gnu.linkonce.armexidx.*) }
 }
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 267b0179a5f..080ea522ed5 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -113,6 +113,7 @@ dtb-$(CONFIG_ARCH_TEGRA) += \
 	tegra30-lg-p880.dtb \
 	tegra30-lg-p895.dtb \
 	tegra30-microsoft-surface-rt.dtb \
+	tegra30-ouya.dtb \
 	tegra30-tec-ng.dtb \
 	tegra30-wexler-qc750.dtb \
 	tegra114-dalmore.dtb \
@@ -121,6 +122,7 @@ dtb-$(CONFIG_ARCH_TEGRA) += \
 	tegra124-nyan-big.dtb \
 	tegra124-cei-tk1-som.dtb \
 	tegra124-venice2.dtb \
+	tegra124-xiaomi-mocha.dtb \
 	tegra186-p2771-0000-000.dtb \
 	tegra186-p2771-0000-500.dtb \
 	tegra210-p2371-0000.dtb \
@@ -795,7 +797,6 @@ dtb-y += \
 	imx6q-icore-rqs.dtb \
 	imx6q-kp.dtb \
 	imx6q-logicpd.dtb \
-	imx6q-lxr.dtb \
 	imx6q-marsboard.dtb \
 	imx6q-mccmon6.dtb\
 	imx6q-nitrogen6x.dtb \
@@ -918,8 +919,7 @@ dtb-$(CONFIG_ARCH_IMX9) += \
 	imx93-var-som-symphony.dtb \
 	imx93-phyboard-segin.dtb
 
-dtb-$(CONFIG_ARCH_IMXRT) += imxrt1050-evk.dtb \
-	imxrt1020-evk.dtb \
+dtb-$(CONFIG_ARCH_IMXRT) += imxrt1020-evk.dtb \
 	imxrt1170-evk.dtb \
 
 dtb-$(CONFIG_RZA1) += \
@@ -1103,17 +1103,19 @@ dtb-$(CONFIG_SOC_K3_AM654) += \
 	k3-am654-r5-base-board.dtb
 
 dtb-$(CONFIG_SOC_K3_J721E) += k3-j721e-r5-common-proc-board.dtb \
-			      k3-j7200-r5-common-proc-board.dtb \
 			      k3-j721e-r5-sk.dtb \
 			      k3-j721e-r5-beagleboneai64.dtb
 
+dtb-$(CONFIG_SOC_K3_J7200) += k3-j7200-r5-common-proc-board.dtb
+
 dtb-$(CONFIG_SOC_K3_J721S2) += k3-am68-sk-r5-base-board.dtb\
 			       k3-j721s2-r5-common-proc-board.dtb
 
 dtb-$(CONFIG_SOC_K3_J784S4) += k3-am69-r5-sk.dtb \
 			       k3-j784s4-r5-evm.dtb
 
-dtb-$(CONFIG_SOC_K3_J722S) += k3-j722s-r5-evm.dtb
+dtb-$(CONFIG_SOC_K3_J722S) += k3-j722s-r5-evm.dtb \
+			      k3-am67a-r5-beagley-ai.dtb
 
 dtb-$(CONFIG_SOC_K3_AM642) += k3-am642-r5-evm.dtb \
 			      k3-am642-r5-sk.dtb \
diff --git a/arch/arm/dts/an7581-u-boot.dtsi b/arch/arm/dts/an7581-u-boot.dtsi
new file mode 100644
index 00000000000..0316b73f3a5
--- /dev/null
+++ b/arch/arm/dts/an7581-u-boot.dtsi
@@ -0,0 +1,18 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+/ {
+	reserved-memory {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		atf-reserved-memory@80000000 {
+			no-map;
+			reg = <0x0 0x80000000 0x0 0x40000>;
+		};
+	};
+};
+
+&uart1 {
+	bootph-all;
+};
diff --git a/arch/arm/dts/at91-sam9x60_curiosity.dts b/arch/arm/dts/at91-sam9x60_curiosity.dts
index 99867d2bf8e..7f00014f13c 100644
--- a/arch/arm/dts/at91-sam9x60_curiosity.dts
+++ b/arch/arm/dts/at91-sam9x60_curiosity.dts
@@ -82,6 +82,11 @@
 	};
 };
 
+&dbgu {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_dbgu>;
+};
+
 &ebi {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_ebi_addr_nand &pinctrl_ebi_data_0_7>;
@@ -171,10 +176,20 @@
 
 &macb0 {
 	phy-mode = "rmii";
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_macb0_rmii>;
 	status = "okay";
 };
 
 &pinctrl {
+	dbgu {
+		pinctrl_dbgu: dbgu-0 {
+			atmel,pins =
+				<AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_PULL_UP
+				 AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+		};
+	};
+
 	ebi {
 		pinctrl_ebi_data_0_7: ebi-data-lsb-0 {
 			atmel,pins =
@@ -217,6 +232,22 @@
 		};
 	};
 
+	macb0 {
+		pinctrl_macb0_rmii: macb0_rmii-0 {
+			atmel,pins =
+				<AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB0 periph A */
+				 AT91_PIOB 1 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB1 periph A */
+				 AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB2 periph A */
+				 AT91_PIOB 3 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB3 periph A */
+				 AT91_PIOB 4 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB4 periph A */
+				 AT91_PIOB 5 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB5 periph A */
+				 AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB6 periph A */
+				 AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB7 periph A */
+				 AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB9 periph A */
+				 AT91_PIOB 10 AT91_PERIPH_A AT91_PINCTRL_NONE>;	/* PB10 periph A */
+		};
+	};
+
 	nand {
 		pinctrl_nand_oe_we: nand-oe-we-0 {
 			atmel,pins =
@@ -240,6 +271,36 @@
 			<AT91_PIOD 14 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>;
 	};
 
+	sdhci0 {
+		pinctrl_sdhci0: sdhci0 {
+			atmel,pins =
+				<AT91_PIOA 17 AT91_PERIPH_A
+				 (AT91_PINCTRL_DRIVE_STRENGTH_HI | AT91_PINCTRL_SLEWRATE_ENA)	/* PA17 CK  periph A with pullup */
+				 AT91_PIOA 16 AT91_PERIPH_A
+				 (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI | AT91_PINCTRL_SLEWRATE_ENA)	/* PA16 CMD periph A with pullup */
+				 AT91_PIOA 15 AT91_PERIPH_A
+				 (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI | AT91_PINCTRL_SLEWRATE_ENA)	/* PA15 DAT0 periph A */
+				 AT91_PIOA 18 AT91_PERIPH_A
+				 (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI | AT91_PINCTRL_SLEWRATE_ENA)	/* PA18 DAT1 periph A with pullup */
+				 AT91_PIOA 19 AT91_PERIPH_A
+				 (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI | AT91_PINCTRL_SLEWRATE_ENA)	/* PA19 DAT2 periph A with pullup */
+				 AT91_PIOA 20 AT91_PERIPH_A
+				 (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI | AT91_PINCTRL_SLEWRATE_ENA)>;	/* PA20 DAT3 periph A with pullup */
+		};
+	};
+
+	sdhci1 {
+		pinctrl_sdhci1: sdhci1 {
+			atmel,pins =
+				<AT91_PIOA 13 AT91_PERIPH_B (AT91_PINCTRL_DRIVE_STRENGTH_HI)				/* PA13 CK periph B */
+				 AT91_PIOA 12 AT91_PERIPH_B (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI)	/* PA12 CMD periph B with pullup */
+				 AT91_PIOA 11 AT91_PERIPH_B (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI)	/* PA11 DAT0 periph B with pullup */
+				 AT91_PIOA 2 AT91_PERIPH_B (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI)	/* PA2 DAT1 periph B with pullup */
+				 AT91_PIOA 3 AT91_PERIPH_B (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI)	/* PA3 DAT2 periph B with pullup */
+				 AT91_PIOA 4 AT91_PERIPH_B (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI)>;	/* PA4 DAT3 periph B with pullup */
+		};
+	};
+
 	usb1 {
 		pinctrl_usb_default: usb_default {
 			atmel,pins = <AT91_PIOD 15 AT91_PERIPH_GPIO AT91_PINCTRL_NONE
@@ -248,6 +309,16 @@
 	};
 };
 
+&sdhci0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_sdhci0>;
+};
+
+&sdhci1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_sdhci1>;
+};
+
 &usb1 {
 	num-ports = <3>;
 	atmel,vbus-gpio = <0
diff --git a/arch/arm/dts/at91sam9260.dtsi b/arch/arm/dts/at91sam9260.dtsi
index 4ea4202737c..8d496205523 100644
--- a/arch/arm/dts/at91sam9260.dtsi
+++ b/arch/arm/dts/at91sam9260.dtsi
@@ -401,51 +401,11 @@
 				clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk";
 			};
 
-			pioA: gpio@fffff400 {
-				compatible = "atmel,at91rm9200-gpio";
-				reg = <0xfffff400 0x200>;
-				interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
-				#gpio-cells = <2>;
-				gpio-controller;
-				interrupt-controller;
-				#interrupt-cells = <2>;
-				clocks = <&pioA_clk>;
-				bootph-all;
-			};
-
-			pioB: gpio@fffff600 {
-				compatible = "atmel,at91rm9200-gpio";
-				reg = <0xfffff600 0x200>;
-				interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
-				#gpio-cells = <2>;
-				gpio-controller;
-				interrupt-controller;
-				#interrupt-cells = <2>;
-				clocks = <&pioB_clk>;
-				bootph-all;
-			};
-
-			pioC: gpio@fffff800 {
-				compatible = "atmel,at91rm9200-gpio";
-				reg = <0xfffff800 0x200>;
-				interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>;
-				#gpio-cells = <2>;
-				gpio-controller;
-				interrupt-controller;
-				#interrupt-cells = <2>;
-				clocks = <&pioC_clk>;
-				bootph-all;
-			};
-
 			pinctrl: pinctrl@fffff400 {
 				#address-cells = <1>;
 				#size-cells = <1>;
 				compatible = "atmel,at91rm9200-pinctrl", "simple-bus";
 				ranges = <0xfffff400 0xfffff400 0x600>;
-				reg = <0xfffff400 0x200		/* pioA */
-				       0xfffff600 0x200		/* pioB */
-				       0xfffff800 0x200		/* pioC */
-				      >;
 
 				atmel,mux-mask = <
 				      /*    A         B     */
@@ -767,6 +727,42 @@
 						atmel,pins = <AT91_PIOB 19 AT91_PERIPH_B AT91_PINCTRL_NONE>;
 					};
 				};
+
+				pioA: gpio@fffff400 {
+					compatible = "atmel,at91rm9200-gpio";
+					reg = <0xfffff400 0x200>;
+					interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
+					#gpio-cells = <2>;
+					gpio-controller;
+					interrupt-controller;
+					#interrupt-cells = <2>;
+					clocks = <&pioA_clk>;
+					bootph-all;
+				};
+
+				pioB: gpio@fffff600 {
+					compatible = "atmel,at91rm9200-gpio";
+					reg = <0xfffff600 0x200>;
+					interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
+					#gpio-cells = <2>;
+					gpio-controller;
+					interrupt-controller;
+					#interrupt-cells = <2>;
+					clocks = <&pioB_clk>;
+					bootph-all;
+				};
+
+				pioC: gpio@fffff800 {
+					compatible = "atmel,at91rm9200-gpio";
+					reg = <0xfffff800 0x200>;
+					interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>;
+					#gpio-cells = <2>;
+					gpio-controller;
+					interrupt-controller;
+					#interrupt-cells = <2>;
+					clocks = <&pioC_clk>;
+					bootph-all;
+				};
 			};
 
 			dbgu: serial@fffff200 {
diff --git a/arch/arm/dts/at91sam9261.dtsi b/arch/arm/dts/at91sam9261.dtsi
index 804340e75d9..65e0e4f0de0 100644
--- a/arch/arm/dts/at91sam9261.dtsi
+++ b/arch/arm/dts/at91sam9261.dtsi
@@ -286,51 +286,12 @@
 				status = "disabled";
 			};
 
-			pioA: gpio@fffff400 {
-				compatible = "atmel,at91rm9200-gpio";
-				reg = <0xfffff400 0x200>;
-				interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
-				#gpio-cells = <2>;
-				gpio-controller;
-				interrupt-controller;
-				#interrupt-cells = <2>;
-				clocks = <&pioA_clk>;
-				bootph-all;
-			};
-
-			pioB: gpio@fffff600 {
-				compatible = "atmel,at91rm9200-gpio";
-				reg = <0xfffff600 0x200>;
-				interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
-				#gpio-cells = <2>;
-				gpio-controller;
-				interrupt-controller;
-				#interrupt-cells = <2>;
-				clocks = <&pioB_clk>;
-				bootph-all;
-			};
-
-			pioC: gpio@fffff800 {
-				compatible = "atmel,at91rm9200-gpio";
-				reg = <0xfffff800 0x200>;
-				interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>;
-				#gpio-cells = <2>;
-				gpio-controller;
-				interrupt-controller;
-				#interrupt-cells = <2>;
-				clocks = <&pioC_clk>;
-				bootph-all;
-			};
-
 			pinctrl@fffff400 {
 				#address-cells = <1>;
 				#size-cells = <1>;
 				compatible = "atmel,at91rm9200-pinctrl", "simple-bus";
 				ranges = <0xfffff400 0xfffff400 0x600>;
-				reg = <0xfffff400 0x200		/* pioA */
-				       0xfffff600 0x200		/* pioB */
-				       0xfffff800 0x200		/* pioC */
-				      >;
+
 				atmel,mux-mask =
 				      /*    A         B     */
 				      <0xffffffff 0xfffffff7>,  /* pioA */
@@ -573,6 +534,42 @@
 							<AT91_PIOB 28 AT91_PERIPH_B AT91_PINCTRL_NONE>;
 					};
 				};
+
+				pioA: gpio@fffff400 {
+					compatible = "atmel,at91rm9200-gpio";
+					reg = <0xfffff400 0x200>;
+					interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
+					#gpio-cells = <2>;
+					gpio-controller;
+					interrupt-controller;
+					#interrupt-cells = <2>;
+					clocks = <&pioA_clk>;
+					bootph-all;
+				};
+
+				pioB: gpio@fffff600 {
+					compatible = "atmel,at91rm9200-gpio";
+					reg = <0xfffff600 0x200>;
+					interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
+					#gpio-cells = <2>;
+					gpio-controller;
+					interrupt-controller;
+					#interrupt-cells = <2>;
+					clocks = <&pioB_clk>;
+					bootph-all;
+				};
+
+				pioC: gpio@fffff800 {
+					compatible = "atmel,at91rm9200-gpio";
+					reg = <0xfffff800 0x200>;
+					interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>;
+					#gpio-cells = <2>;
+					gpio-controller;
+					interrupt-controller;
+					#interrupt-cells = <2>;
+					clocks = <&pioC_clk>;
+					bootph-all;
+				};
 			};
 
 			pmc: pmc@fffffc00 {
diff --git a/arch/arm/dts/at91sam9263.dtsi b/arch/arm/dts/at91sam9263.dtsi
index 98cdd8ebcca..55b79667564 100644
--- a/arch/arm/dts/at91sam9263.dtsi
+++ b/arch/arm/dts/at91sam9263.dtsi
@@ -404,12 +404,6 @@
 				#size-cells = <1>;
 				compatible = "atmel,at91rm9200-pinctrl", "simple-bus";
 				ranges = <0xfffff200 0xfffff200 0xa00>;
-				reg = <0xfffff200 0x200
-				       0xfffff400 0x200
-				       0xfffff600 0x200
-				       0xfffff800 0x200
-				       0xfffffa00 0x200
-				      >;
 
 				atmel,mux-mask = <
 				      /*    A         B     */
@@ -719,66 +713,65 @@
 					};
 				};
 
-			};
-
-			pioA: gpio@fffff200 {
-				compatible = "atmel,at91rm9200-gpio";
-				reg = <0xfffff200 0x200>;
-				interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
-				#gpio-cells = <2>;
-				gpio-controller;
-				interrupt-controller;
-				#interrupt-cells = <2>;
-				clocks = <&pioA_clk>;
-				bootph-all;
-			};
+				pioA: gpio@fffff200 {
+					compatible = "atmel,at91rm9200-gpio";
+					reg = <0xfffff200 0x200>;
+					interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
+					#gpio-cells = <2>;
+					gpio-controller;
+					interrupt-controller;
+					#interrupt-cells = <2>;
+					clocks = <&pioA_clk>;
+					bootph-all;
+				};
 
-			pioB: gpio@fffff400 {
-				compatible = "atmel,at91rm9200-gpio";
-				reg = <0xfffff400 0x200>;
-				interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
-				#gpio-cells = <2>;
-				gpio-controller;
-				interrupt-controller;
-				#interrupt-cells = <2>;
-				clocks = <&pioB_clk>;
-				bootph-all;
-			};
+				pioB: gpio@fffff400 {
+					compatible = "atmel,at91rm9200-gpio";
+					reg = <0xfffff400 0x200>;
+					interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
+					#gpio-cells = <2>;
+					gpio-controller;
+					interrupt-controller;
+					#interrupt-cells = <2>;
+					clocks = <&pioB_clk>;
+					bootph-all;
+				};
 
-			pioC: gpio@fffff600 {
-				compatible = "atmel,at91rm9200-gpio";
-				reg = <0xfffff600 0x200>;
-				interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>;
-				#gpio-cells = <2>;
-				gpio-controller;
-				interrupt-controller;
-				#interrupt-cells = <2>;
-				clocks = <&pioCDE_clk>;
-				bootph-all;
-			};
+				pioC: gpio@fffff600 {
+					compatible = "atmel,at91rm9200-gpio";
+					reg = <0xfffff600 0x200>;
+					interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>;
+					#gpio-cells = <2>;
+					gpio-controller;
+					interrupt-controller;
+					#interrupt-cells = <2>;
+					clocks = <&pioCDE_clk>;
+					bootph-all;
+				};
 
-			pioD: gpio@fffff800 {
-				compatible = "atmel,at91rm9200-gpio";
-				reg = <0xfffff800 0x200>;
-				interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>;
-				#gpio-cells = <2>;
-				gpio-controller;
-				interrupt-controller;
-				#interrupt-cells = <2>;
-				clocks = <&pioCDE_clk>;
-				bootph-all;
-			};
+				pioD: gpio@fffff800 {
+					compatible = "atmel,at91rm9200-gpio";
+					reg = <0xfffff800 0x200>;
+					interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>;
+					#gpio-cells = <2>;
+					gpio-controller;
+					interrupt-controller;
+					#interrupt-cells = <2>;
+					clocks = <&pioCDE_clk>;
+					bootph-all;
+				};
 
-			pioE: gpio@fffffa00 {
-				compatible = "atmel,at91rm9200-gpio";
-				reg = <0xfffffa00 0x200>;
-				interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>;
-				#gpio-cells = <2>;
-				gpio-controller;
-				interrupt-controller;
-				#interrupt-cells = <2>;
-				clocks = <&pioCDE_clk>;
-				bootph-all;
+				pioE: gpio@fffffa00 {
+					compatible = "atmel,at91rm9200-gpio";
+					reg = <0xfffffa00 0x200>;
+					interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>;
+					#gpio-cells = <2>;
+					gpio-controller;
+					interrupt-controller;
+					#interrupt-cells = <2>;
+					clocks = <&pioCDE_clk>;
+					bootph-all;
+				};
 			};
 
 			dbgu: serial@ffffee00 {
diff --git a/arch/arm/dts/at91sam9g45.dtsi b/arch/arm/dts/at91sam9g45.dtsi
index d0bcd797359..63a061354e4 100644
--- a/arch/arm/dts/at91sam9g45.dtsi
+++ b/arch/arm/dts/at91sam9g45.dtsi
@@ -435,12 +435,6 @@
 				#size-cells = <1>;
 				compatible = "atmel,at91rm9200-pinctrl", "simple-bus";
 				ranges = <0xfffff200 0xfffff200 0xa00>;
-				reg = <0xfffff200 0x200
-				       0xfffff400 0x200
-				       0xfffff600 0x200
-				       0xfffff800 0x200
-				       0xfffffa00 0x200
-				      >;
 				bootph-all;
 
 				atmel,mux-mask = <
@@ -854,61 +848,61 @@
 							 AT91_PIOE 30 AT91_PERIPH_A AT91_PINCTRL_NONE>;	/* PE30 periph A */
 					};
 				};
-			};
 
-			pioA: gpio@fffff200 {
-				compatible = "atmel,at91rm9200-gpio";
-				reg = <0xfffff200 0x200>;
-				interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
-				#gpio-cells = <2>;
-				gpio-controller;
-				interrupt-controller;
-				#interrupt-cells = <2>;
-				clocks = <&pioA_clk>;
-			};
+				pioA: gpio@fffff200 {
+					compatible = "atmel,at91rm9200-gpio";
+					reg = <0xfffff200 0x200>;
+					interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
+					#gpio-cells = <2>;
+					gpio-controller;
+					interrupt-controller;
+					#interrupt-cells = <2>;
+					clocks = <&pioA_clk>;
+				};
 
-			pioB: gpio@fffff400 {
-				compatible = "atmel,at91rm9200-gpio";
-				reg = <0xfffff400 0x200>;
-				interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
-				#gpio-cells = <2>;
-				gpio-controller;
-				interrupt-controller;
-				#interrupt-cells = <2>;
-				clocks = <&pioB_clk>;
-			};
+				pioB: gpio@fffff400 {
+					compatible = "atmel,at91rm9200-gpio";
+					reg = <0xfffff400 0x200>;
+					interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
+					#gpio-cells = <2>;
+					gpio-controller;
+					interrupt-controller;
+					#interrupt-cells = <2>;
+					clocks = <&pioB_clk>;
+				};
 
-			pioC: gpio@fffff600 {
-				compatible = "atmel,at91rm9200-gpio";
-				reg = <0xfffff600 0x200>;
-				interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>;
-				#gpio-cells = <2>;
-				gpio-controller;
-				interrupt-controller;
-				#interrupt-cells = <2>;
-				clocks = <&pioC_clk>;
-			};
+				pioC: gpio@fffff600 {
+					compatible = "atmel,at91rm9200-gpio";
+					reg = <0xfffff600 0x200>;
+					interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>;
+					#gpio-cells = <2>;
+					gpio-controller;
+					interrupt-controller;
+					#interrupt-cells = <2>;
+					clocks = <&pioC_clk>;
+				};
 
-			pioD: gpio@fffff800 {
-				compatible = "atmel,at91rm9200-gpio";
-				reg = <0xfffff800 0x200>;
-				interrupts = <5 IRQ_TYPE_LEVEL_HIGH 1>;
-				#gpio-cells = <2>;
-				gpio-controller;
-				interrupt-controller;
-				#interrupt-cells = <2>;
-				clocks = <&pioDE_clk>;
-			};
+				pioD: gpio@fffff800 {
+					compatible = "atmel,at91rm9200-gpio";
+					reg = <0xfffff800 0x200>;
+					interrupts = <5 IRQ_TYPE_LEVEL_HIGH 1>;
+					#gpio-cells = <2>;
+					gpio-controller;
+					interrupt-controller;
+					#interrupt-cells = <2>;
+					clocks = <&pioDE_clk>;
+				};
 
-			pioE: gpio@fffffa00 {
-				compatible = "atmel,at91rm9200-gpio";
-				reg = <0xfffffa00 0x200>;
-				interrupts = <5 IRQ_TYPE_LEVEL_HIGH 1>;
-				#gpio-cells = <2>;
-				gpio-controller;
-				interrupt-controller;
-				#interrupt-cells = <2>;
-				clocks = <&pioDE_clk>;
+				pioE: gpio@fffffa00 {
+					compatible = "atmel,at91rm9200-gpio";
+					reg = <0xfffffa00 0x200>;
+					interrupts = <5 IRQ_TYPE_LEVEL_HIGH 1>;
+					#gpio-cells = <2>;
+					gpio-controller;
+					interrupt-controller;
+					#interrupt-cells = <2>;
+					clocks = <&pioDE_clk>;
+				};
 			};
 
 			dbgu: serial@ffffee00 {
diff --git a/arch/arm/dts/at91sam9n12.dtsi b/arch/arm/dts/at91sam9n12.dtsi
index cb3a0370b86..84089837013 100644
--- a/arch/arm/dts/at91sam9n12.dtsi
+++ b/arch/arm/dts/at91sam9n12.dtsi
@@ -492,11 +492,6 @@
 				#size-cells = <1>;
 				compatible = "atmel,at91sam9x5-pinctrl", "atmel,at91rm9200-pinctrl", "simple-bus";
 				ranges = <0xfffff400 0xfffff400 0x800>;
-				reg = <0xfffff400 0x200
-				       0xfffff600 0x200
-				       0xfffff800 0x200
-				       0xfffffa00 0x200
-				      >;
 
 				atmel,mux-mask = <
 				      /*    A         B          C     */
@@ -795,54 +790,54 @@
 						atmel,pins = <AT91_PIOC 13 AT91_PERIPH_C AT91_PINCTRL_NONE>;
 					};
 				};
-			};
 
-			pioA: gpio@fffff400 {
-				compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
-				reg = <0xfffff400 0x200>;
-				interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
-				#gpio-cells = <2>;
-				gpio-controller;
-				interrupt-controller;
-				#interrupt-cells = <2>;
-				clocks = <&pioAB_clk>;
-				bootph-all;
-			};
+				pioA: gpio@fffff400 {
+					compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
+					reg = <0xfffff400 0x200>;
+					interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
+					#gpio-cells = <2>;
+					gpio-controller;
+					interrupt-controller;
+					#interrupt-cells = <2>;
+					clocks = <&pioAB_clk>;
+					bootph-all;
+				};
 
-			pioB: gpio@fffff600 {
-				compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
-				reg = <0xfffff600 0x200>;
-				interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
-				#gpio-cells = <2>;
-				gpio-controller;
-				interrupt-controller;
-				#interrupt-cells = <2>;
-				clocks = <&pioAB_clk>;
-				bootph-all;
-			};
+				pioB: gpio@fffff600 {
+					compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
+					reg = <0xfffff600 0x200>;
+					interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
+					#gpio-cells = <2>;
+					gpio-controller;
+					interrupt-controller;
+					#interrupt-cells = <2>;
+					clocks = <&pioAB_clk>;
+					bootph-all;
+				};
 
-			pioC: gpio@fffff800 {
-				compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
-				reg = <0xfffff800 0x200>;
-				interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
-				#gpio-cells = <2>;
-				gpio-controller;
-				interrupt-controller;
-				#interrupt-cells = <2>;
-				clocks = <&pioCD_clk>;
-				bootph-all;
-			};
+				pioC: gpio@fffff800 {
+					compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
+					reg = <0xfffff800 0x200>;
+					interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
+					#gpio-cells = <2>;
+					gpio-controller;
+					interrupt-controller;
+					#interrupt-cells = <2>;
+					clocks = <&pioCD_clk>;
+					bootph-all;
+				};
 
-			pioD: gpio@fffffa00 {
-				compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
-				reg = <0xfffffa00 0x200>;
-				interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
-				#gpio-cells = <2>;
-				gpio-controller;
-				interrupt-controller;
-				#interrupt-cells = <2>;
-				clocks = <&pioCD_clk>;
-				bootph-all;
+				pioD: gpio@fffffa00 {
+					compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
+					reg = <0xfffffa00 0x200>;
+					interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
+					#gpio-cells = <2>;
+					gpio-controller;
+					interrupt-controller;
+					#interrupt-cells = <2>;
+					clocks = <&pioCD_clk>;
+					bootph-all;
+				};
 			};
 
 			dbgu: serial@fffff200 {
diff --git a/arch/arm/dts/at91sam9rl.dtsi b/arch/arm/dts/at91sam9rl.dtsi
index b855c8fe0fe..3b99de21058 100644
--- a/arch/arm/dts/at91sam9rl.dtsi
+++ b/arch/arm/dts/at91sam9rl.dtsi
@@ -386,11 +386,6 @@
 				#size-cells = <1>;
 				compatible = "atmel,at91rm9200-pinctrl", "simple-bus";
 				ranges = <0xfffff400 0xfffff400 0x800>;
-				reg = <0xfffff400 0x200
-				       0xfffff600 0x200
-				       0xfffff800 0x200
-				       0xfffffa00 0x200
-				      >;
 
 				atmel,mux-mask =
 					/*    A         B     */
@@ -768,54 +763,54 @@
 							<AT91_PIOA 20 AT91_PERIPH_B AT91_PINCTRL_NONE>;
 					};
 				};
-			};
 
-			pioA: gpio@fffff400 {
-				compatible = "atmel,at91rm9200-gpio";
-				reg = <0xfffff400 0x200>;
-				interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
-				#gpio-cells = <2>;
-				gpio-controller;
-				interrupt-controller;
-				#interrupt-cells = <2>;
-				clocks = <&pioA_clk>;
-				bootph-all;
-			};
+				pioA: gpio@fffff400 {
+					compatible = "atmel,at91rm9200-gpio";
+					reg = <0xfffff400 0x200>;
+					interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
+					#gpio-cells = <2>;
+					gpio-controller;
+					interrupt-controller;
+					#interrupt-cells = <2>;
+					clocks = <&pioA_clk>;
+					bootph-all;
+				};
 
-			pioB: gpio@fffff600 {
-				compatible = "atmel,at91rm9200-gpio";
-				reg = <0xfffff600 0x200>;
-				interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
-				#gpio-cells = <2>;
-				gpio-controller;
-				interrupt-controller;
-				#interrupt-cells = <2>;
-				clocks = <&pioB_clk>;
-				bootph-all;
-			};
+				pioB: gpio@fffff600 {
+					compatible = "atmel,at91rm9200-gpio";
+					reg = <0xfffff600 0x200>;
+					interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
+					#gpio-cells = <2>;
+					gpio-controller;
+					interrupt-controller;
+					#interrupt-cells = <2>;
+					clocks = <&pioB_clk>;
+					bootph-all;
+				};
 
-			pioC: gpio@fffff800 {
-				compatible = "atmel,at91rm9200-gpio";
-				reg = <0xfffff800 0x200>;
-				interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>;
-				#gpio-cells = <2>;
-				gpio-controller;
-				interrupt-controller;
-				#interrupt-cells = <2>;
-				clocks = <&pioC_clk>;
-				bootph-all;
-			};
+				pioC: gpio@fffff800 {
+					compatible = "atmel,at91rm9200-gpio";
+					reg = <0xfffff800 0x200>;
+					interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>;
+					#gpio-cells = <2>;
+					gpio-controller;
+					interrupt-controller;
+					#interrupt-cells = <2>;
+					clocks = <&pioC_clk>;
+					bootph-all;
+				};
 
-			pioD: gpio@fffffa00 {
-				compatible = "atmel,at91rm9200-gpio";
-				reg = <0xfffffa00 0x200>;
-				interrupts = <5 IRQ_TYPE_LEVEL_HIGH 1>;
-				#gpio-cells = <2>;
-				gpio-controller;
-				interrupt-controller;
-				#interrupt-cells = <2>;
-				clocks = <&pioD_clk>;
-				bootph-all;
+				pioD: gpio@fffffa00 {
+					compatible = "atmel,at91rm9200-gpio";
+					reg = <0xfffffa00 0x200>;
+					interrupts = <5 IRQ_TYPE_LEVEL_HIGH 1>;
+					#gpio-cells = <2>;
+					gpio-controller;
+					interrupt-controller;
+					#interrupt-cells = <2>;
+					clocks = <&pioD_clk>;
+					bootph-all;
+				};
 			};
 
 			pmc: pmc@fffffc00 {
diff --git a/arch/arm/dts/at91sam9x5.dtsi b/arch/arm/dts/at91sam9x5.dtsi
index 5fca9b13c27..4c6d8b9bb65 100644
--- a/arch/arm/dts/at91sam9x5.dtsi
+++ b/arch/arm/dts/at91sam9x5.dtsi
@@ -461,14 +461,8 @@
 				#size-cells = <1>;
 				compatible = "atmel,at91sam9x5-pinctrl", "atmel,at91rm9200-pinctrl", "simple-bus";
 				ranges = <0xfffff400 0xfffff400 0x800>;
-				reg = <0xfffff400 0x200		/* pioA */
-				       0xfffff600 0x200		/* pioB */
-				       0xfffff800 0x200		/* pioC */
-				       0xfffffa00 0x200		/* pioD */
-				       >;
 				bootph-all;
 
-
 				/* shared pinctrl settings */
 				dbgu {
 					bootph-all;
@@ -831,52 +825,52 @@
 						atmel,pins = <AT91_PIOC 13 AT91_PERIPH_C AT91_PINCTRL_NONE>;
 					};
 				};
-			};
 
-			pioA: gpio@fffff400 {
-				compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
-				reg = <0xfffff400 0x200>;
-				interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
-				#gpio-cells = <2>;
-				gpio-controller;
-				interrupt-controller;
-				#interrupt-cells = <2>;
-				clocks = <&pioAB_clk>;
-			};
+				pioA: gpio@fffff400 {
+					compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
+					reg = <0xfffff400 0x200>;
+					interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
+					#gpio-cells = <2>;
+					gpio-controller;
+					interrupt-controller;
+					#interrupt-cells = <2>;
+					clocks = <&pioAB_clk>;
+				};
 
-			pioB: gpio@fffff600 {
-				compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
-				reg = <0xfffff600 0x200>;
-				interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
-				#gpio-cells = <2>;
-				gpio-controller;
-				#gpio-lines = <19>;
-				interrupt-controller;
-				#interrupt-cells = <2>;
-				clocks = <&pioAB_clk>;
-			};
+				pioB: gpio@fffff600 {
+					compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
+					reg = <0xfffff600 0x200>;
+					interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
+					#gpio-cells = <2>;
+					gpio-controller;
+					#gpio-lines = <19>;
+					interrupt-controller;
+					#interrupt-cells = <2>;
+					clocks = <&pioAB_clk>;
+				};
 
-			pioC: gpio@fffff800 {
-				compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
-				reg = <0xfffff800 0x200>;
-				interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
-				#gpio-cells = <2>;
-				gpio-controller;
-				interrupt-controller;
-				#interrupt-cells = <2>;
-				clocks = <&pioCD_clk>;
-			};
+				pioC: gpio@fffff800 {
+					compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
+					reg = <0xfffff800 0x200>;
+					interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
+					#gpio-cells = <2>;
+					gpio-controller;
+					interrupt-controller;
+					#interrupt-cells = <2>;
+					clocks = <&pioCD_clk>;
+				};
 
-			pioD: gpio@fffffa00 {
-				compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
-				reg = <0xfffffa00 0x200>;
-				interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
-				#gpio-cells = <2>;
-				gpio-controller;
-				#gpio-lines = <22>;
-				interrupt-controller;
-				#interrupt-cells = <2>;
-				clocks = <&pioCD_clk>;
+				pioD: gpio@fffffa00 {
+					compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
+					reg = <0xfffffa00 0x200>;
+					interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
+					#gpio-cells = <2>;
+					gpio-controller;
+					#gpio-lines = <22>;
+					interrupt-controller;
+					#interrupt-cells = <2>;
+					clocks = <&pioCD_clk>;
+				};
 			};
 
 			ssc0: ssc@f0010000 {
diff --git a/arch/arm/dts/en7581-evb-u-boot.dtsi b/arch/arm/dts/en7581-evb-u-boot.dtsi
new file mode 100644
index 00000000000..ebd3b8b4958
--- /dev/null
+++ b/arch/arm/dts/en7581-evb-u-boot.dtsi
@@ -0,0 +1,11 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+/ {
+	/* When running as a first-stage bootloader this isn't filled in automatically */
+	memory@80000000 {
+		device_type = "memory";
+		reg = <0x0 0x80000000 0x0 0x20000000>;
+	};
+};
+
+#include "an7581-u-boot.dtsi"
diff --git a/arch/arm/dts/imx6q-lxr.dts b/arch/arm/dts/imx6q-lxr.dts
deleted file mode 100644
index ae4f8eeb105..00000000000
--- a/arch/arm/dts/imx6q-lxr.dts
+++ /dev/null
@@ -1,87 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-//
-// Copyright 2024 Comvetia AG
-
-/dts-v1/;
-#include "imx6q-phytec-pfla02.dtsi"
-
-/ {
-	model = "COMVETIA QSoIP LXR-2";
-	compatible = "comvetia,imx6q-lxr", "phytec,imx6q-pfla02", "fsl,imx6q";
-
-	chosen {
-		stdout-path = &uart4;
-	};
-
-	spi {
-		compatible = "spi-gpio";
-		pinctrl-names = "default";
-		pinctrl-0 = <&pinctrl_spi_gpio>;
-		sck-gpios = <&gpio5 8 GPIO_ACTIVE_HIGH>;
-		mosi-gpios = <&gpio5 7 GPIO_ACTIVE_HIGH>;
-		num-chipselects = <0>;
-		#address-cells = <1>;
-		#size-cells = <0>;
-
-		fpga@0 {
-			compatible = "altr,fpga-passive-serial";
-			reg = <0>;
-			pinctrl-names = "default";
-			pinctrl-0 = <&pinctrl_fpga>;
-			nconfig-gpios = <&gpio4 18 GPIO_ACTIVE_LOW>;
-			nstat-gpios = <&gpio4 19 GPIO_ACTIVE_LOW>;
-			confd-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>;
-		};
-	};
-};
-
-&ecspi3 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_ecspi3>;
-	cs-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>;
-	status = "okay";
-
-	flash@0 {
-		compatible = "jedec,spi-nor";
-		reg = <0>;
-		spi-max-frequency = <20000000>;
-	};
-};
-
-&fec {
-	status = "okay";
-};
-
-&i2c3 {
-	status = "okay";
-};
-
-&uart3 {
-	status = "okay";
-};
-
-&uart4 {
-	status = "okay";
-};
-
-&usdhc3 {
-	no-1-8-v;
-	status = "okay";
-};
-
-&iomuxc {
-	pinctrl_fpga: fpgagrp {
-		fsl,pins = <
-			MX6QDL_PAD_GPIO_6__GPIO1_IO06       0x1b0b0
-			MX6QDL_PAD_DI0_PIN2__GPIO4_IO18     0x1b0b0
-			MX6QDL_PAD_DI0_PIN3__GPIO4_IO19     0x1b0b0
-		>;
-	};
-
-	pinctrl_spi_gpio: spigpiogrp {
-		fsl,pins = <
-			MX6QDL_PAD_DISP0_DAT14__GPIO5_IO08  0x1b0b0
-			MX6QDL_PAD_DISP0_DAT13__GPIO5_IO07  0x1b0b0
-		>;
-	};
-};
diff --git a/arch/arm/dts/imx6q-phytec-pfla02.dtsi b/arch/arm/dts/imx6q-phytec-pfla02.dtsi
deleted file mode 100644
index 500944bd2a0..00000000000
--- a/arch/arm/dts/imx6q-phytec-pfla02.dtsi
+++ /dev/null
@@ -1,17 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-/*
- * Copyright 2013 Christian Hemp, Phytec Messtechnik GmbH
- */
-
-#include "imx6q.dtsi"
-#include "imx6qdl-phytec-pfla02.dtsi"
-
-/ {
-	model = "Phytec phyFLEX-i.MX6 Quad";
-	compatible = "phytec,imx6q-pfla02", "fsl,imx6q";
-
-	memory@10000000 {
-		device_type = "memory";
-		reg = <0x10000000 0x80000000>;
-	};
-};
diff --git a/arch/arm/dts/imx6qdl-phytec-pfla02.dtsi b/arch/arm/dts/imx6qdl-phytec-pfla02.dtsi
deleted file mode 100644
index c0c47adc586..00000000000
--- a/arch/arm/dts/imx6qdl-phytec-pfla02.dtsi
+++ /dev/null
@@ -1,467 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-/*
- * Copyright 2013 Christian Hemp, Phytec Messtechnik GmbH
- */
-
-#include <dt-bindings/gpio/gpio.h>
-
-/ {
-	model = "Phytec phyFLEX-i.MX6 Quad";
-	compatible = "phytec,imx6q-pfla02", "fsl,imx6q";
-
-	memory@10000000 {
-		device_type = "memory";
-		reg = <0x10000000 0x80000000>;
-	};
-
-	reg_usb_otg_vbus: regulator-usb-otg-vbus {
-		compatible = "regulator-fixed";
-		regulator-name = "usb_otg_vbus";
-		regulator-min-microvolt = <5000000>;
-		regulator-max-microvolt = <5000000>;
-		gpio = <&gpio4 15 0>;
-		enable-active-high;
-	};
-
-	reg_usb_h1_vbus: regulator-usb-h1-vbus {
-		compatible = "regulator-fixed";
-		pinctrl-names = "default";
-		pinctrl-0 = <&pinctrl_usbh1_vbus>;
-		regulator-name = "usb_h1_vbus";
-		regulator-min-microvolt = <5000000>;
-		regulator-max-microvolt = <5000000>;
-		gpio = <&gpio1 0 0>;
-		enable-active-high;
-	};
-
-	gpio_leds: leds {
-		pinctrl-names = "default";
-		pinctrl-0 = <&pinctrl_leds>;
-		compatible = "gpio-leds";
-
-		led_green: led-green {
-			label = "phyflex:green";
-			gpios = <&gpio1 30 0>;
-		};
-
-		led_red: led-red {
-			label = "phyflex:red";
-			gpios = <&gpio2 31 0>;
-		};
-	};
-};
-
-&audmux {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_audmux>;
-	status = "disabled";
-};
-
-&can1 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_flexcan1>;
-	status = "disabled";
-};
-
-&ecspi3 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_ecspi3>;
-	status = "okay";
-	cs-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>;
-
-	som_flash: flash@0 {
-		compatible = "m25p80", "jedec,spi-nor";
-		spi-max-frequency = <20000000>;
-		reg = <0>;
-	};
-};
-
-&fec {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_enet>;
-	phy-handle = <&ethphy>;
-	phy-mode = "rgmii";
-	phy-reset-duration = <10>; /* in msecs */
-	phy-reset-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>;
-	phy-supply = <&vdd_eth_io_reg>;
-	status = "disabled";
-
-	fec_mdio: mdio {
-		#address-cells = <1>;
-		#size-cells = <0>;
-
-		ethphy: ethernet-phy@0 {
-			compatible = "ethernet-phy-ieee802.3-c22";
-			reg = <0>;
-			txc-skew-ps = <1680>;
-			rxc-skew-ps = <1860>;
-		};
-	};
-};
-
-&gpmi {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_gpmi_nand>;
-	nand-on-flash-bbt;
-	status = "okay";
-};
-
-&i2c1 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_i2c1>;
-	status = "okay";
-
-	som_eeprom: eeprom@50 {
-		compatible = "catalyst,24c32", "atmel,24c32";
-		pagesize = <32>;
-		reg = <0x50>;
-	};
-
-	pmic@58 {
-		pinctrl-names = "default";
-		pinctrl-0 = <&pinctrl_pmic>;
-		compatible = "dlg,da9063";
-		reg = <0x58>;
-		interrupt-parent = <&gpio2>;
-		interrupts = <9 IRQ_TYPE_LEVEL_LOW>; /* active-low GPIO2_9 */
-		#interrupt-cells = <2>;
-		interrupt-controller;
-
-		regulators {
-			vddcore_reg: bcore1 {
-				regulator-min-microvolt = <730000>;
-				regulator-max-microvolt = <1380000>;
-				regulator-always-on;
-			};
-
-			vddsoc_reg: bcore2 {
-				regulator-min-microvolt = <730000>;
-				regulator-max-microvolt = <1380000>;
-				regulator-always-on;
-			};
-
-			vdd_ddr3_reg: bpro {
-				regulator-min-microvolt = <1500000>;
-				regulator-max-microvolt = <1500000>;
-				regulator-always-on;
-			};
-
-			vdd_3v3_reg: bperi {
-				regulator-min-microvolt = <3300000>;
-				regulator-max-microvolt = <3300000>;
-				regulator-always-on;
-			};
-
-			vdd_buckmem_reg: bmem {
-				regulator-min-microvolt = <3300000>;
-				regulator-max-microvolt = <3300000>;
-				regulator-always-on;
-			};
-
-			vdd_eth_reg: bio {
-				regulator-min-microvolt = <1200000>;
-				regulator-max-microvolt = <1200000>;
-				regulator-always-on;
-			};
-
-			vdd_eth_io_reg: ldo4 {
-				regulator-min-microvolt = <2500000>;
-				regulator-max-microvolt = <2500000>;
-				regulator-always-on;
-			};
-
-			vdd_mx6_snvs_reg: ldo5 {
-				regulator-min-microvolt = <3000000>;
-				regulator-max-microvolt = <3000000>;
-				regulator-always-on;
-			};
-
-			vdd_3v3_pmic_io_reg: ldo6 {
-				regulator-min-microvolt = <3300000>;
-				regulator-max-microvolt = <3300000>;
-				regulator-always-on;
-			};
-
-			vdd_sd0_reg: ldo9 {
-				regulator-min-microvolt = <3300000>;
-				regulator-max-microvolt = <3300000>;
-			};
-
-			vdd_sd1_reg: ldo10 {
-				regulator-min-microvolt = <3300000>;
-				regulator-max-microvolt = <3300000>;
-			};
-
-			vdd_mx6_high_reg: ldo11 {
-				regulator-min-microvolt = <3000000>;
-				regulator-max-microvolt = <3000000>;
-				regulator-always-on;
-			};
-		};
-
-		da9063_rtc: rtc {
-			compatible = "dlg,da9063-rtc";
-		};
-
-		da9063_wdog: watchdog {
-			compatible = "dlg,da9063-watchdog";
-		};
-
-		onkey {
-			compatible = "dlg,da9063-onkey";
-			status = "disabled";
-		};
-	};
-};
-
-&i2c2 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_i2c2>;
-	clock-frequency = <100000>;
-};
-
-&i2c3 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_i2c3>;
-	clock-frequency = <100000>;
-};
-
-&iomuxc {
-	imx6q-phytec-pfla02 {
-		pinctrl_ecspi3: ecspi3grp {
-			fsl,pins = <
-				MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO	0x100b1
-				MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI	0x100b1
-				MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK	0x100b1
-				MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24	0x80000000 /* CS0 */
-			>;
-		};
-
-		pinctrl_enet: enetgrp {
-			fsl,pins = <
-				MX6QDL_PAD_ENET_MDIO__ENET_MDIO		0x1b0b0
-				MX6QDL_PAD_ENET_MDC__ENET_MDC		0x1b0b0
-				MX6QDL_PAD_RGMII_TXC__RGMII_TXC		0x1b030
-				MX6QDL_PAD_RGMII_TD0__RGMII_TD0		0x1b030
-				MX6QDL_PAD_RGMII_TD1__RGMII_TD1		0x1b030
-				MX6QDL_PAD_RGMII_TD2__RGMII_TD2		0x1b030
-				MX6QDL_PAD_RGMII_TD3__RGMII_TD3		0x1b030
-				MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL	0x1b030
-				MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK	0x1b0b0
-				MX6QDL_PAD_RGMII_RXC__RGMII_RXC		0x1b030
-				MX6QDL_PAD_RGMII_RD0__RGMII_RD0		0x1b030
-				MX6QDL_PAD_RGMII_RD1__RGMII_RD1		0x1b030
-				MX6QDL_PAD_RGMII_RD2__RGMII_RD2		0x1b030
-				MX6QDL_PAD_RGMII_RD3__RGMII_RD3		0x1b030
-				MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL	0x1b030
-				MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN	0x1b0b0
-				MX6QDL_PAD_EIM_D23__GPIO3_IO23		0x80000000 /* Reset GPIO */
-			>;
-		};
-
-		pinctrl_flexcan1: flexcan1grp {
-			fsl,pins = <
-				MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX	0x1b0b0
-				MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX	0x1b0b0
-			>;
-		};
-
-		pinctrl_gpmi_nand: gpminandgrp {
-			fsl,pins = <
-				MX6QDL_PAD_NANDF_CLE__NAND_CLE		0xb0b1
-				MX6QDL_PAD_NANDF_ALE__NAND_ALE		0xb0b1
-				MX6QDL_PAD_NANDF_WP_B__NAND_WP_B	0xb0b1
-				MX6QDL_PAD_NANDF_RB0__NAND_READY_B	0xb000
-				MX6QDL_PAD_NANDF_CS0__NAND_CE0_B	0xb0b1
-				MX6QDL_PAD_NANDF_CS1__NAND_CE1_B	0xb0b1
-				MX6QDL_PAD_SD4_CMD__NAND_RE_B		0xb0b1
-				MX6QDL_PAD_SD4_CLK__NAND_WE_B		0xb0b1
-				MX6QDL_PAD_NANDF_D0__NAND_DATA00	0xb0b1
-				MX6QDL_PAD_NANDF_D1__NAND_DATA01	0xb0b1
-				MX6QDL_PAD_NANDF_D2__NAND_DATA02	0xb0b1
-				MX6QDL_PAD_NANDF_D3__NAND_DATA03	0xb0b1
-				MX6QDL_PAD_NANDF_D4__NAND_DATA04	0xb0b1
-				MX6QDL_PAD_NANDF_D5__NAND_DATA05	0xb0b1
-				MX6QDL_PAD_NANDF_D6__NAND_DATA06	0xb0b1
-				MX6QDL_PAD_NANDF_D7__NAND_DATA07	0xb0b1
-				MX6QDL_PAD_SD4_DAT0__NAND_DQS		0x00b1
-			>;
-		};
-
-		pinctrl_i2c1: i2c1grp {
-			fsl,pins = <
-				MX6QDL_PAD_EIM_D21__I2C1_SCL		0x4001b8b1
-				MX6QDL_PAD_EIM_D28__I2C1_SDA		0x4001b8b1
-			>;
-		};
-
-		pinctrl_i2c2: i2c2grp {
-			fsl,pins = <
-				MX6QDL_PAD_EIM_EB2__I2C2_SCL		0x4001b8b1
-				MX6QDL_PAD_EIM_D16__I2C2_SDA		0x4001b8b1
-			>;
-		};
-
-		pinctrl_i2c3: i2c3grp {
-			fsl,pins = <
-				MX6QDL_PAD_EIM_D17__I2C3_SCL		0x4001b8b1
-				MX6QDL_PAD_EIM_D18__I2C3_SDA		0x4001b8b1
-			>;
-		};
-
-		pinctrl_leds: ledsgrp {
-			fsl,pins = <
-				MX6QDL_PAD_ENET_TXD0__GPIO1_IO30	0x80000000 /* Green LED */
-				MX6QDL_PAD_EIM_EB3__GPIO2_IO31		0x80000000 /* Red LED */
-			>;
-		};
-
-		pinctrl_pcie: pciegrp {
-			fsl,pins = <MX6QDL_PAD_DI0_PIN15__GPIO4_IO17  0x80000000>;
-		};
-
-		pinctrl_pmic: pmicgrp {
-			fsl,pins = <MX6QDL_PAD_SD4_DAT1__GPIO2_IO09	0x80000000>; /* PMIC interrupt */
-		};
-
-		pinctrl_uart3: uart3grp {
-			fsl,pins = <
-				MX6QDL_PAD_EIM_D24__UART3_TX_DATA	0x1b0b1
-				MX6QDL_PAD_EIM_D25__UART3_RX_DATA	0x1b0b1
-				MX6QDL_PAD_EIM_D31__UART3_RTS_B		0x1b0b1
-				MX6QDL_PAD_EIM_D30__UART3_CTS_B		0x1b0b1
-			>;
-		};
-
-		pinctrl_uart4: uart4grp {
-			fsl,pins = <
-				MX6QDL_PAD_KEY_COL0__UART4_TX_DATA	0x1b0b1
-				MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA	0x1b0b1
-			>;
-		};
-
-		pinctrl_usbh1_vbus: usbh1vbusgrp {
-			fsl,pins = <
-				MX6QDL_PAD_GPIO_0__GPIO1_IO00		0x1b0b0
-			>;
-		};
-
-		pinctrl_usbotg: usbotggrp {
-			fsl,pins = <
-				MX6QDL_PAD_GPIO_1__USB_OTG_ID		0x17059
-				MX6QDL_PAD_KEY_COL4__USB_OTG_OC		0x1b0b0
-				MX6QDL_PAD_KEY_ROW4__GPIO4_IO15		0x80000000
-			>;
-		};
-
-		pinctrl_usdhc2: usdhc2grp {
-			fsl,pins = <
-				MX6QDL_PAD_SD2_CMD__SD2_CMD		0x17059
-				MX6QDL_PAD_SD2_CLK__SD2_CLK		0x10059
-				MX6QDL_PAD_SD2_DAT0__SD2_DATA0		0x17059
-				MX6QDL_PAD_SD2_DAT1__SD2_DATA1		0x17059
-				MX6QDL_PAD_SD2_DAT2__SD2_DATA2		0x17059
-				MX6QDL_PAD_SD2_DAT3__SD2_DATA3		0x17059
-			>;
-		};
-
-		pinctrl_usdhc3: usdhc3grp {
-			fsl,pins = <
-				MX6QDL_PAD_SD3_CMD__SD3_CMD		0x17059
-				MX6QDL_PAD_SD3_CLK__SD3_CLK		0x10059
-				MX6QDL_PAD_SD3_DAT0__SD3_DATA0		0x17059
-				MX6QDL_PAD_SD3_DAT1__SD3_DATA1		0x17059
-				MX6QDL_PAD_SD3_DAT2__SD3_DATA2		0x17059
-				MX6QDL_PAD_SD3_DAT3__SD3_DATA3		0x17059
-			>;
-		};
-
-		pinctrl_usdhc3_cdwp: usdhc3cdwp {
-			fsl,pins = <
-				MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x80000000
-				MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000
-			>;
-		};
-
-		pinctrl_audmux: audmuxgrp {
-			fsl,pins = <
-				MX6QDL_PAD_DISP0_DAT16__AUD5_TXC	0x130b0
-				MX6QDL_PAD_DISP0_DAT17__AUD5_TXD	0x110b0
-				MX6QDL_PAD_DISP0_DAT18__AUD5_TXFS	0x130b0
-				MX6QDL_PAD_DISP0_DAT19__AUD5_RXD	0x130b0
-			>;
-		};
-	};
-};
-
-&pcie {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_pcie>;
-	reset-gpio = <&gpio4 17 GPIO_ACTIVE_LOW>;
-	status = "disabled";
-};
-
-&reg_arm {
-	vin-supply = <&vddcore_reg>;
-};
-
-&reg_pu {
-	vin-supply = <&vddsoc_reg>;
-};
-
-&reg_soc {
-	vin-supply = <&vddsoc_reg>;
-};
-
-&uart3 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_uart3>;
-	uart-has-rtscts;
-	status = "disabled";
-};
-
-&uart4 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_uart4>;
-	status = "disabled";
-};
-
-&usbh1 {
-	vbus-supply = <&reg_usb_h1_vbus>;
-	status = "disabled";
-};
-
-&usbotg {
-	vbus-supply = <&reg_usb_otg_vbus>;
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_usbotg>;
-	disable-over-current;
-	status = "disabled";
-};
-
-&usdhc2 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_usdhc2>;
-	cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
-	wp-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
-	vmmc-supply = <&vdd_sd1_reg>;
-	status = "disabled";
-};
-
-&usdhc3 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_usdhc3
-		     &pinctrl_usdhc3_cdwp>;
-	cd-gpios = <&gpio1 27 GPIO_ACTIVE_LOW>;
-	wp-gpios = <&gpio1 29 GPIO_ACTIVE_HIGH>;
-	vmmc-supply = <&vdd_sd0_reg>;
-	status = "disabled";
-};
-
-&wdog1 {
-	/*
-	 * Rely on PMIC reboot handler. Internal i.MX6 watchdog, that is also
-	 * used for reboot, does not reset all external PMIC voltages on reset.
-	 */
-	status = "disabled";
-};
diff --git a/arch/arm/dts/imxrt1050-evk.dts b/arch/arm/dts/imxrt1050-evk.dts
deleted file mode 100644
index 6a9c10decf5..00000000000
--- a/arch/arm/dts/imxrt1050-evk.dts
+++ /dev/null
@@ -1,72 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (C) 2019
- * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
- */
-
-/dts-v1/;
-#include "imxrt1050.dtsi"
-#include "imxrt1050-pinfunc.h"
-
-/ {
-	model = "NXP IMXRT1050-evk board";
-	compatible = "fsl,imxrt1050-evk", "fsl,imxrt1050";
-
-	chosen {
-		stdout-path = &lpuart1;
-	};
-
-	aliases {
-		gpio0 = &gpio1;
-		gpio1 = &gpio2;
-		gpio2 = &gpio3;
-		gpio3 = &gpio4;
-		gpio4 = &gpio5;
-		mmc0 = &usdhc1;
-		serial0 = &lpuart1;
-	};
-
-	memory@80000000 {
-		device_type = "memory";
-		reg = <0x80000000 0x2000000>;
-	};
-};
-
-&lpuart1 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_lpuart1>;
-	status = "okay";
-};
-
-&iomuxc {
-	pinctrl-names = "default";
-	pinctrl_lpuart1: lpuart1grp {
-		fsl,pins = <
-			MXRT1050_IOMUXC_GPIO_AD_B0_12_LPUART1_TXD	0xf1
-			MXRT1050_IOMUXC_GPIO_AD_B0_13_LPUART1_RXD	0xf1
-		>;
-	};
-
-	pinctrl_usdhc0: usdhc0grp {
-		fsl,pins = <
-			MXRT1050_IOMUXC_GPIO_B1_12_USDHC1_CD_B		0x1B000
-			MXRT1050_IOMUXC_GPIO_B1_14_USDHC1_VSELECT	0xB069
-			MXRT1050_IOMUXC_GPIO_SD_B0_00_USDHC1_CMD	0x17061
-			MXRT1050_IOMUXC_GPIO_SD_B0_01_USDHC1_CLK	0x17061
-			MXRT1050_IOMUXC_GPIO_SD_B0_05_USDHC1_DATA3	0x17061
-			MXRT1050_IOMUXC_GPIO_SD_B0_04_USDHC1_DATA2	0x17061
-			MXRT1050_IOMUXC_GPIO_SD_B0_03_USDHC1_DATA1	0x17061
-			MXRT1050_IOMUXC_GPIO_SD_B0_02_USDHC1_DATA0	0x17061
-		>;
-	};
-};
-
-&usdhc1 {
-	pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
-	pinctrl-0 = <&pinctrl_usdhc0>;
-	pinctrl-1 = <&pinctrl_usdhc0>;
-	pinctrl-2 = <&pinctrl_usdhc0>;
-	pinctrl-3 = <&pinctrl_usdhc0>;
-	cd-gpios = <&gpio2 28 GPIO_ACTIVE_LOW>;
-	status = "okay";
-};
diff --git a/arch/arm/dts/imxrt1050-pinfunc.h b/arch/arm/dts/imxrt1050-pinfunc.h
deleted file mode 100644
index 22c14a3262a..00000000000
--- a/arch/arm/dts/imxrt1050-pinfunc.h
+++ /dev/null
@@ -1,993 +0,0 @@
-/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
-/*
- * Copyright (C) 2019
- * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
- */
-
-#ifndef _DT_BINDINGS_PINCTRL_IMXRT1050_PINFUNC_H
-#define _DT_BINDINGS_PINCTRL_IMXRT1050_PINFUNC_H
-
-#define IMX_PAD_SION	0x40000000
-
-/*
- * The pin function ID is a tuple of
- * <mux_reg conf_reg input_reg mux_mode input_val>
- */
-
-#define MXRT1050_IOMUXC_GPIO_EMC_00_SEMC_DA00				0x014 0x204 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_00_FLEXPWM4_PWM0_A			0x014 0x204 0x494 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_00_LPSPI2_SCK				0x014 0x204 0x500 0x2 0x1
-#define MXRT1050_IOMUXC_GPIO_EMC_00_XBAR_INOUT2				0x014 0x204 0x60C 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_00_FLEXIO1_D00				0x014 0x204 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_00_GPIO4_IO00				0x014 0x204 0x000 0x5 0x0
-
-#define MXRT1050_IOMUXC_GPIO_EMC_01_SEMC_DA01				0x018 0x208 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_01_FLEXPWM4_PWM0_B			0x018 0x208 0x000 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_01_LPSPI2_PCS0				0x018 0x208 0x4FC 0x2 0x1
-#define MXRT1050_IOMUXC_GPIO_EMC_01_XBAR_INOUT3				0x018 0x208 0x610 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_01_FLEXIO1_D01				0x018 0x208 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_01_GPIO4_IO01				0x018 0x208 0x000 0x5 0x0
-
-#define MXRT1050_IOMUXC_GPIO_EMC_02_SEMC_DA02				0x01C 0x20C 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_02_FLEXPWM4_PWM1_A			0x01C 0x20C 0x498 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_02_LPSPI2_SDO				0x01C 0x20C 0x508 0x2 0x1
-#define MXRT1050_IOMUXC_GPIO_EMC_02_XBAR_INOUT4				0x01C 0x20C 0x614 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_02_FLEXIO1_D02				0x01C 0x20C 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_02_GPIO4_IO02				0x01C 0x20C 0x000 0x5 0x0
-
-#define MXRT1050_IOMUXC_GPIO_EMC_03_SEMC_DA03				0x020 0x210 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_03_FLEXPWM4_PWM1_B			0x020 0x210 0x000 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_03_LPSPI2_SDI				0x020 0x210 0x504 0x2 0x1
-#define MXRT1050_IOMUXC_GPIO_EMC_03_XBAR_INOUT5				0x020 0x210 0x618 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_03_FLEXIO1_D03				0x020 0x210 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_03_GPIO4_IO03				0x020 0x210 0x000 0x5 0x0
-
-#define MXRT1050_IOMUXC_GPIO_EMC_04_SEMC_DA04				0x024 0x214 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_04_FLEXPWM4_PWM2_A			0x024 0x214 0x49C 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_04_SAI2_TX_DATA			0x024 0x214 0x000 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_04_XBAR_INOUT6				0x024 0x214 0x61C 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_04_FLEXIO1_D04				0x024 0x214 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_04_GPIO4_IO04				0x024 0x214 0x000 0x5 0x0
-
-#define MXRT1050_IOMUXC_GPIO_EMC_05_SEMC_DA05				0x028 0x218 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_05_FLEXPWM4_PWM2_B			0x028 0x218 0x000 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_05_SAI2_TX_SYNC			0x028 0x218 0x5C4 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_05_XBAR_INOUT7				0x028 0x218 0x620 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_05_FLEXIO1_D05				0x028 0x218 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_05_GPIO4_IO05				0x028 0x218 0x000 0x5 0x0
-
-#define MXRT1050_IOMUXC_GPIO_EMC_06_SEMC_DA06				0x02C 0x21C 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_06_FLEXPWM2_PWM0_A			0x02C 0x21C 0x478 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_06_SAI2_TX_BCLK			0x02C 0x21C 0x5C0 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_06_XBAR_INOUT8				0x02C 0x21C 0x624 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_06_FLEXIO1_D06				0x02C 0x21C 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_06_GPIO4_IO06				0x02C 0x21C 0x000 0x5 0x0
-
-#define MXRT1050_IOMUXC_GPIO_EMC_07_SEMC_DA07				0x030 0x220 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_07_FLEXPWM2_PWM0_B			0x030 0x220 0x488 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_07_SAI2_MCLK				0x030 0x220 0x5B0 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_07_XBAR_INOUT9				0x030 0x220 0x628 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_07_FLEXIO1_D07				0x030 0x220 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_07_GPIO4_IO07				0x030 0x220 0x000 0x5 0x0
-
-#define MXRT1050_IOMUXC_GPIO_EMC_08_SEMC_DM00				0x034 0x224 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_08_FLEXPWM2_PWM1_A			0x034 0x224 0x47C 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_08_SAI2_RX_DATA			0x034 0x224 0x5B8 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_08_XBAR_INOUT17			0x034 0x224 0x62C 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_08_FLEXIO1_D08				0x034 0x224 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_08_GPIO4_IO08				0x034 0x224 0x000 0x5 0x0
-
-#define MXRT1050_IOMUXC_GPIO_EMC_09_SEMC_ADDR00				0x038 0x228 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_09_FLEXPWM2_PWM1_B			0x038 0x228 0x48C 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_09_SAI2_RX_SYNC			0x038 0x228 0x5BC 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_09_FLEXCAN2_TX				0x038 0x228 0x000 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_09_FLEXIO1_D09				0x038 0x228 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_09_GPIO4_IO09				0x038 0x228 0x000 0x5 0x0
-
-#define MXRT1050_IOMUXC_GPIO_EMC_10_SEMC_ADDR01				0x03C 0x22C 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_10_FLEXPWM2_PWM2_A			0x03C 0x22C 0x480 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_10_SAI2_RX_BCLK			0x03C 0x22C 0x5B4 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_10_FLEXCAN2_RX				0x03C 0x22C 0x450 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_10_FLEXIO1_D10				0x03C 0x22C 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_10_GPIO4_IO10				0x03C 0x22C 0x000 0x5 0x0
-
-#define MXRT1050_IOMUXC_GPIO_EMC_11_SEMC_ADDR02				0x040 0x230 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_11_FLEXPWM2_PWM2_B			0x040 0x230 0x490 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_11_LPI2C4_SDA				0x040 0x230 0x4E8 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_11_USDHC2_RESET_B			0x040 0x230 0x000 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_11_FLEXIO1_D11				0x040 0x230 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_11_GPIO4_IO11				0x040 0x230 0x000 0x5 0x0
-
-#define MXRT1050_IOMUXC_GPIO_EMC_12_SEMC_ADDR03				0x044 0x234 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_12_XBAR_INOUT24			0x044 0x234 0x640 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_12_LPI2C4_SCL				0x044 0x234 0x4E4 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_12_USDHC2_WP				0x044 0x234 0x5D8 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_12_FLEXPWM1_PWM3_A			0x044 0x234 0x454 0x4 0x1
-#define MXRT1050_IOMUXC_GPIO_EMC_12_GPIO4_IO12				0x044 0x234 0x000 0x5 0x0
-
-#define MXRT1050_IOMUXC_GPIO_EMC_13_SEMC_ADDR04				0x048 0x238 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_13_XBAR_INOUT25			0x048 0x238 0x650 0x1 0x1
-#define MXRT1050_IOMUXC_GPIO_EMC_13_LPUART3_TXD				0x048 0x238 0x53C 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_13_MQS_RIGHT				0x048 0x238 0x000 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_13_FLEXPWM1_PWM3_B			0x048 0x238 0x464 0x4 0x1
-#define MXRT1050_IOMUXC_GPIO_EMC_13_GPIO4_IO13				0x048 0x238 0x000 0x5 0x0
-
-#define MXRT1050_IOMUXC_GPIO_EMC_14_SEMC_ADDR05				0x04C 0x23C 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_14_XBAR_INOUT19			0x04C 0x23C 0x654 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_14_LPUART3_RXD				0x04C 0x23C 0x538 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_14_MQS_LEFT				0x04C 0x23C 0x000 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_14_LPSPI2_PCS1				0x04C 0x23C 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_14_GPIO4_IO14				0x04C 0x23C 0x000 0x5 0x0
-
-#define MXRT1050_IOMUXC_GPIO_EMC_15_SEMC_ADDR06				0x050 0x240 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_15_XBAR_INOUT20			0x050 0x240 0x634 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_15_LPUART3_CTS_B			0x050 0x240 0x534 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_15_SPDIF_OUT				0x050 0x240 0x000 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_15_TMR3_TIMER0				0x050 0x240 0x57C 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_15_GPIO4_IO15				0x050 0x240 0x000 0x5 0x0
-
-#define MXRT1050_IOMUXC_GPIO_EMC_16_SEMC_ADDR07				0x054 0x244 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_16_XBAR_INOUT21			0x054 0x244 0x658 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_16_LPUART3_RTS_B			0x054 0x244 0x000 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_16_SPDIF_IN				0x054 0x244 0x5C8 0x3 0x1
-#define MXRT1050_IOMUXC_GPIO_EMC_16_TMR3_TIMER1				0x054 0x244 0x580 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_16_GPIO4_IO16				0x054 0x244 0x000 0x5 0x0
-
-#define MXRT1050_IOMUXC_GPIO_EMC_17_SEMC_ADDR08				0x058 0x248 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_17_FLEXPWM4_PWM3_A			0x058 0x248 0x4A0 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_17_LPUART4_CTS_B			0x058 0x248 0x000 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_17_FLEXCAN1_TX				0x058 0x248 0x000 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_17_TMR3_TIMER2				0x058 0x248 0x584 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_17_GPIO4_IO17				0x058 0x248 0x000 0x5 0x0
-
-#define MXRT1050_IOMUXC_GPIO_EMC_18_SEMC_ADDR09				0x05C 0x24C 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_18_FLEXPWM4_PWM3_B			0x05C 0x24C 0x000 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_18_LPUART4_RTS_B			0x05C 0x24C 0x000 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_18_FLEXCAN1_RX				0x05C 0x24C 0x44C 0x3 0x1
-#define MXRT1050_IOMUXC_GPIO_EMC_18_TMR3_TIMER3				0x05C 0x24C 0x588 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_18_GPIO4_IO18				0x05C 0x24C 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_18_SNVS_VIO_5_CTL			0x05C 0x24C 0x000 0x6 0x0
-
-#define MXRT1050_IOMUXC_GPIO_EMC_19_SEMC_ADDR11				0x060 0x250 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_19_FLEXPWM2_PWM3_A			0x060 0x250 0x000 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_19_LPUART4_TXD				0x060 0x250 0x544 0x2 0x1
-#define MXRT1050_IOMUXC_GPIO_EMC_19_ENET_RX_DATA01			0x060 0x250 0x438 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_19_TMR2_TIMER0				0x060 0x250 0x56C 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_19_GPIO4_IO19				0x060 0x250 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_19_SNVS_VIO_5				0x060 0x250 0x000 0x6 0x0
-
-#define MXRT1050_IOMUXC_GPIO_EMC_20_SEMC_ADDR12				0x064 0x254 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_20_FLEXPWM2_PWM3_B			0x064 0x254 0x484 0x1 0x1
-#define MXRT1050_IOMUXC_GPIO_EMC_20_LPUART4_RXD				0x064 0x254 0x540 0x2 0x1
-#define MXRT1050_IOMUXC_GPIO_EMC_20_ENET_RX_DATA00			0x064 0x254 0x434 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_20_TMR2_TIMER0				0x064 0x254 0x570 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_20_GPIO4_IO20				0x064 0x254 0x000 0x5 0x0
-
-#define MXRT1050_IOMUXC_GPIO_EMC_21_SEMC_BA0				0x068 0x258 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_21_FLEXPWM3_PWM3_A			0x068 0x258 0x000 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_21_LPI2C3_SDA				0x068 0x258 0x4E0 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_21_ENET_TX_DATA01			0x068 0x258 0x000 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_21_TMR2_TIMER2				0x068 0x258 0x574 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_21_GPIO4_IO21				0x068 0x258 0x000 0x5 0x0
-
-#define MXRT1050_IOMUXC_GPIO_EMC_22_SEMC_BA1				0x06C 0x25C 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_22_FLEXPWM3_PWM3_B			0x06C 0x25C 0x000 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_22_LPI2C3_SCL				0x06C 0x25C 0x4DC 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_22_ENET_TX_DATA00			0x06C 0x25C 0x000 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_22_TMR2_TIMER3				0x06C 0x25C 0x578 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_22_GPIO4_IO22				0x06C 0x25C 0x000 0x5 0x0
-
-#define MXRT1050_IOMUXC_GPIO_EMC_23_SEMC_ADDR10				0x070 0x260 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_23_FLEXPWM1_PWM0_A			0x070 0x260 0x458 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_23_LPUART5_TXD				0x070 0x260 0x54C 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_23_ENET_RX_EN				0x070 0x260 0x43C 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_23_GPT1_CAPTURE2			0x070 0x260 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_23_GPIO4_IO23				0x070 0x260 0x000 0x5 0x0
-
-#define MXRT1050_IOMUXC_GPIO_EMC_24_SEMC_CAS				0x074 0x264 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_24_FLEXPWM1_PWM0_B			0x074 0x264 0x000 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_24_LPUART5_RXD				0x074 0x264 0x548 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_24_ENET_TX_EN				0x074 0x264 0x000 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_24_GPT1_CAPTURE1			0x074 0x264 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_24_GPIO4_IO24				0x074 0x264 0x000 0x5 0x0
-
-#define MXRT1050_IOMUXC_GPIO_EMC_25_SEMC_RAS				0x078 0x268 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_25_FLEXPWM1_PWM1_A			0x078 0x268 0x45C 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_25_LPUART6_TXD				0x078 0x268 0x554 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_25_ENET_TX_CLK				0x078 0x268 0x448 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_25_ENET_REF_CLK			0x078 0x268 0x42C 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_25_GPIO4_IO25				0x078 0x268 0x000 0x5 0x0
-
-#define MXRT1050_IOMUXC_GPIO_EMC_26_SEMC_CLK				0x07C 0x26C 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_26_FLEXPWM1_PWM1_B			0x07C 0x26C 0x46C 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_26_LPUART6_RXD				0x07C 0x26C 0x550 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_26_ENET_RX_ER				0x07C 0x26C 0x440 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_26_FLEXIO1_D12				0x07C 0x26C 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_26_GPIO4_IO26				0x07C 0x26C 0x000 0x5 0x0
-
-#define MXRT1050_IOMUXC_GPIO_EMC_27_SEMC_CKE				0x080 0x270 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_27_FLEXPWM1_PWM2_A			0x080 0x270 0x460 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_27_LPUART5_RTS_B			0x080 0x270 0x000 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_27_LPSPI1_SCK				0x080 0x270 0x4F0 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_27_FLEXIO1_D13				0x080 0x270 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_27_GPIO4_IO27				0x080 0x270 0x000 0x5 0x0
-
-#define MXRT1050_IOMUXC_GPIO_EMC_28_SEMC_WE				0x084 0x274 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_28_FLEXPWM1_PWM2_B			0x084 0x274 0x470 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_28_LPUART5_CTS_B			0x084 0x274 0x000 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_28_LPSPI1_SDO				0x084 0x274 0x4F8 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_28_FLEXIO1_D14				0x084 0x274 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_28_GPIO4_IO28				0x084 0x274 0x000 0x5 0x0
-
-#define MXRT1050_IOMUXC_GPIO_EMC_29_SEMC_CS0				0x088 0x278 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_29_FLEXPWM3_PWM0_A			0x088 0x278 0x000 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_29_LPUART6_RTS_B			0x088 0x278 0x000 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_29_LPSPI1_SDI				0x088 0x278 0x4F4 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_29_FLEXIO1_D15				0x088 0x278 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_29_GPIO4_IO29				0x088 0x278 0x000 0x5 0x0
-
-#define MXRT1050_IOMUXC_GPIO_EMC_30_SEMC_DA08				0x08C 0x27C 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_30_FLEXPWM3_PWM0_B			0x08C 0x27C 0x000 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_30_LPUART6_CTS_B			0x08C 0x27C 0x000 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_30_LPSPI1_PCS0				0x08C 0x27C 0x4EC 0x3 0x1
-#define MXRT1050_IOMUXC_GPIO_EMC_30_CSI_DATA23				0x08C 0x27C 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_30_GPIO4_IO30				0x08C 0x27C 0x000 0x5 0x0
-
-#define MXRT1050_IOMUXC_GPIO_EMC_31_SEMC_DA09				0x090 0x280 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_31_FLEXPWM3_PWM1_A			0x090 0x280 0x000 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_31_LPUART7_TXD				0x090 0x280 0x55C 0x2 0x1
-#define MXRT1050_IOMUXC_GPIO_EMC_31_LPSPI1_PCS1				0x090 0x280 0x000 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_31_CSI_DATA22				0x090 0x280 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_31_GPIO4_IO31				0x090 0x280 0x000 0x5 0x0
-
-#define MXRT1050_IOMUXC_GPIO_EMC_32_SEMC_DA10				0x094 0x284 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_32_FLEXPWM3_PWM1_B			0x094 0x284 0x000 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_32_LPUART7_RXD				0x094 0x284 0x558 0x2 0x1
-#define MXRT1050_IOMUXC_GPIO_EMC_32_CCM_PMIC_READY			0x094 0x284 0x3FC 0x3 0x4
-#define MXRT1050_IOMUXC_GPIO_EMC_32_CSI_DATA21				0x094 0x284 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_32_GPIO3_IO18				0x094 0x284 0x000 0x5 0x0
-
-#define MXRT1050_IOMUXC_GPIO_EMC_33_SEMC_DA11				0x098 0x288 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_33_FLEXPWM3_PWM2_A			0x098 0x288 0x000 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_33_USDHC1_RESET_B			0x098 0x288 0x000 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_33_SAI3_RX_DATA			0x098 0x288 0x000 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_33_CSI_DATA20				0x098 0x288 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_33_GPIO3_IO19				0x098 0x288 0x000 0x5 0x0
-
-#define MXRT1050_IOMUXC_GPIO_EMC_34_SEMC_DA12				0x09C 0x28C 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_34_FLEXPWM3_PWM2_B			0x09C 0x28C 0x000 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_34_USDHC1_VSELECT			0x09C 0x28C 0x000 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_34_SAI3_RX_SYNC			0x09C 0x28C 0x000 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_34_CSI_DATA19				0x09C 0x28C 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_34_GPIO3_IO20				0x09C 0x28C 0x000 0x5 0x0
-
-#define MXRT1050_IOMUXC_GPIO_EMC_35_SEMC_DA13				0x0A0 0x290 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_35_XBAR_INOUT18			0x0A0 0x290 0x630 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_35_GPT1_COMPARE1			0x0A0 0x290 0x000 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_35_SAI3_RX_BCLK			0x0A0 0x290 0x000 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_35_CSI_DATA18				0x0A0 0x290 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_35_GPIO3_IO21				0x0A0 0x290 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_35_USDHC1_CD_B				0x0A0 0x290 0x5D4 0x6 0x0
-
-#define MXRT1050_IOMUXC_GPIO_EMC_36_SEMC_DA14				0x0A4 0x294 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_36_XBAR_INOUT22			0x0A4 0x294 0x638 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_36_GPT1_COMPARE2			0x0A4 0x294 0x000 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_36_SAI3_TX_DATA			0x0A4 0x294 0x000 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_36_CSI_DATA17				0x0A4 0x294 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_36_GPIO3_IO22				0x0A4 0x294 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_36_USDHC1_WP				0x0A4 0x294 0x5D8 0x6 0x1
-
-#define MXRT1050_IOMUXC_GPIO_EMC_37_SEMC_DA15				0x0A8 0x298 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_37_XBAR_INOUT23			0x0A8 0x298 0x63C 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_37_GPT1_COMPARE3			0x0A8 0x298 0x000 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_37_SAI3_MCLK				0x0A8 0x298 0x000 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_37_CSI_DATA16				0x0A8 0x298 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_37_GPIO3_IO23				0x0A8 0x298 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_37_USDHC2_WP				0x0A8 0x298 0x608 0x6 0x0
-
-#define MXRT1050_IOMUXC_GPIO_EMC_38_SEMC_DM01				0x0AC 0x29C 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_38_FLEXPWM1_PWM3_A			0x0AC 0x29C 0x454 0x1 0x2
-#define MXRT1050_IOMUXC_GPIO_EMC_38_LPUART8_TXD				0x0AC 0x29C 0x564 0x2 0x2
-#define MXRT1050_IOMUXC_GPIO_EMC_38_SAI3_TX_BCLK			0x0AC 0x29C 0x000 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_38_CSI_FIELD				0x0AC 0x29C 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_38_GPIO3_IO24				0x0AC 0x29C 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_38_USDHC2_VSELECT			0x0AC 0x29C 0x000 0x6 0x0
-
-#define MXRT1050_IOMUXC_GPIO_EMC_39_SEMC_DQS				0x0B0 0x2A0 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_39_FLEXPWM1_PWM3_B			0x0B0 0x2A0 0x464 0x1 0x2
-#define MXRT1050_IOMUXC_GPIO_EMC_39_LPUART8_RXD				0x0B0 0x2A0 0x560 0x2 0x2
-#define MXRT1050_IOMUXC_GPIO_EMC_39_SAI3_TX_SYNC			0x0B0 0x2A0 0x000 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_39_WDOG1_B				0x0B0 0x2A0 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_39_GPIO3_IO25				0x0B0 0x2A0 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_39_USDHC2_CD_B				0x0B0 0x2A0 0x5E0 0x6 0x1
-
-#define MXRT1050_IOMUXC_GPIO_EMC_40_SEMC_RDY				0x0B4 0x2A4 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_40_GPT2_CAPTURE2			0x0B4 0x2A4 0x000 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_40_LPSPI1_PCS2				0x0B4 0x2A4 0x000 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_40_USB_OTG2_OC				0x0B4 0x2A4 0x5CC 0x3 0x1
-#define MXRT1050_IOMUXC_GPIO_EMC_40_ENET_MDC				0x0B4 0x2A4 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_40_GPIO3_IO26				0x0B4 0x2A4 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_40_USDHC2_RESET_B			0x0B4 0x2A4 0x000 0x6 0x0
-
-#define MXRT1050_IOMUXC_GPIO_EMC_41_SEMC_CSX0				0x0B8 0x2A8 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_41_GPT2_CAPTURE1			0x0B8 0x2A8 0x000 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_41_LPSPI1_PCS3				0x0B8 0x2A8 0x000 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_41_USB_OTG2_PWR			0x0B8 0x2A8 0x000 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_41_ENET_MDIO				0x0B8 0x2A8 0x430 0x4 0x1
-#define MXRT1050_IOMUXC_GPIO_EMC_41_GPIO3_IO27				0x0B8 0x2A8 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_EMC_41_USDHC2_VSELECT			0x0B8 0x2A8 0x000 0x6 0x0
-
-#define MXRT1050_IOMUXC_GPIO_AD_B0_00_FLEXPWM2_PWM3_A			0x0BC 0x2AC 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_00_XBAR_INOUT14			0x0BC 0x2AC 0x644 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_00_REF_CLK_32K			0x0BC 0x2AC 0x000 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_00_USB_OTG2_ID			0x0BC 0x2AC 0x3F8 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_00_LPI2C1_SCLS			0x0BC 0x2AC 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_00_GPIO1_IO00			0x0BC 0x2AC 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_00_USDHC1_RESET_B			0x0BC 0x2AC 0x000 0x6 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_00_LPSPI3_SCK			0x0BC 0x2AC 0x510 0x7 0x0
-
-#define MXRT1050_IOMUXC_GPIO_AD_B0_01_FLEXPWM2_PWM3_B			0x0C0 0x2B0 0x484 0x0 0x2
-#define MXRT1050_IOMUXC_GPIO_AD_B0_01_XBAR_INOUT15			0x0C0 0x2B0 0x648 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_01_REF_CLK_24M			0x0C0 0x2B0 0x000 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_01_USB_OTG1_ID			0x0C0 0x2B0 0x3F4 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_01_LPI2C1_SDAS			0x0C0 0x2B0 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_01_GPIO1_IO01			0x0C0 0x2B0 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_01_EWM_OUT_B				0x0C0 0x2B0 0x000 0x6 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_01_LPSPI3_SDO			0x0C0 0x2B0 0x518 0x7 0x1
-
-#define MXRT1050_IOMUXC_GPIO_AD_B0_02_FLEXCAN2_TX			0x0C4 0x2B4 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_02_XBAR_INOUT16			0x0C4 0x2B4 0x64C 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_02_LPUART6_TXD			0x0C4 0x2B4 0x554 0x2 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B0_02_USB_OTG1_PWR			0x0C4 0x2B4 0x000 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_02_FLEXPWM1_PWM0_X			0x0C4 0x2B4 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_02_GPIO1_IO02			0x0C4 0x2B4 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_02_LPI2C1_HREQ			0x0C4 0x2B4 0x000 0x6 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_02_LPSPI3_SDI			0x0C4 0x2B4 0x514 0x7 0x1
-
-#define MXRT1050_IOMUXC_GPIO_AD_B0_03_FLEXCAN2_RX			0x0C8 0x2B8 0x450 0x0 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B0_03_XBAR_INOUT17			0x0C8 0x2B8 0x62C 0x1 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B0_03_LPUART6_RXD			0x0C8 0x2B8 0x550 0x2 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B0_03_USB_OTG1_OC			0x0C8 0x2B8 0x5D0 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_03_FLEXPWM1_PWM1_X			0x0C8 0x2B8 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_03_GPIO1_IO03			0x0C8 0x2B8 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_03_REF_CLK_24M			0x0C8 0x2B8 0x000 0x6 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_03_LPSPI3_PCS0			0x0C8 0x2B8 0x50C 0x7 0x0
-
-#define MXRT1050_IOMUXC_GPIO_AD_B0_04_SRC_BOOT_MODE00			0x0CC 0x2BC 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_04_MQS_RIGHT				0x0CC 0x2BC 0x000 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_04_ENET_TX_DATA03			0x0CC 0x2BC 0x000 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_04_SAI2_TX_SYNC			0x0CC 0x2BC 0x5C4 0x3 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B0_04_CSI_DATA09			0x0CC 0x2BC 0x41C 0x4 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B0_04_GPIO1_IO04			0x0CC 0x2BC 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_04_PIT_TRIGGER00			0x0CC 0x2BC 0x000 0x6 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_04_LPSPI3_PCS1			0x0CC 0x2BC 0x000 0x7 0x0
-
-#define MXRT1050_IOMUXC_GPIO_AD_B0_05_SRC_BOOT_MODE01			0x0D0 0x2C0 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_05_MQS_LEFT				0x0D0 0x2C0 0x000 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_05_ENET_TX_DATA02			0x0D0 0x2C0 0x000 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_05_SAI2_TX_BCLK			0x0D0 0x2C0 0x5C0 0x3 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B0_05_CSI_DATA08			0x0D0 0x2C0 0x418 0x4 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B0_05_GPIO1_IO05			0x0D0 0x2C0 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_05_XBAR_INOUT17			0x0D0 0x2C0 0x62C 0x6 0x2
-#define MXRT1050_IOMUXC_GPIO_AD_B0_05_LPSPI3_PCS2			0x0D0 0x2C0 0x000 0x7 0x0
-
-#define MXRT1050_IOMUXC_GPIO_AD_B0_06_JTAG_TMS				0x0D4 0x2C4 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_06_GPT2_COMPARE1			0x0D4 0x2C4 0x000 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_06_ENET_RX_CLK			0x0D4 0x2C4 0x000 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_06_SAI2_RX_BCLK			0x0D4 0x2C4 0x5B4 0x3 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B0_06_CSI_DATA07			0x0D4 0x2C4 0x414 0x4 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B0_06_GPIO1_IO06			0x0D4 0x2C4 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_06_XBAR_INOUT18			0x0D4 0x2C4 0x630 0x6 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B0_06_LPSPI3_PCS3			0x0D4 0x2C4 0x000 0x7 0x0
-
-#define MXRT1050_IOMUXC_GPIO_AD_B0_07_JTAG_TCK				0x0D8 0x2C8 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_07_GPT2_COMPARE2			0x0D8 0x2C8 0x000 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_07_ENET_TX_ER			0x0D8 0x2C8 0x000 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_07_SAI2_RX_SYNC			0x0D8 0x2C8 0x5BC 0x3 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B0_07_CSI_DATA06			0x0D8 0x2C8 0x410 0x4 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B0_07_GPIO1_IO07			0x0D8 0x2C8 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_07_XBAR_INOUT19			0x0D8 0x2C8 0x654 0x6 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B0_07_ENET_1588_EVENT3_OUT		0x0D8 0x2C8 0x000 0x7 0x0
-
-#define MXRT1050_IOMUXC_GPIO_AD_B0_08_JTAG_MOD				0x0DC 0x2CC 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_08_GPT2_COMPARE3			0x0DC 0x2CC 0x000 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_08_ENET_RX_DATA03			0x0DC 0x2CC 0x000 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_08_SAI2_RX_DATA			0x0DC 0x2CC 0x5B8 0x3 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B0_08_CSI_DATA05			0x0DC 0x2CC 0x40C 0x4 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B0_08_GPIO1_IO08			0x0DC 0x2CC 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_08_XBAR_INOUT20			0x0DC 0x2CC 0x634 0x6 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B0_08_ENET_1588_EVENT3_IN		0x0DC 0x2CC 0x000 0x7 0x0
-
-#define MXRT1050_IOMUXC_GPIO_AD_B0_09_JTAG_TDI				0x0E0 0x2D0 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_09_FLEXPWM2_PWM3_A			0x0E0 0x2D0 0x000 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_09_ENET_RX_DATA02			0x0E0 0x2D0 0x000 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_09_SAI2_TX_DATA			0x0E0 0x2D0 0x000 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_09_CSI_DATA04			0x0E0 0x2D0 0x408 0x4 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B0_09_GPIO1_IO09			0x0E0 0x2D0 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_09_XBAR_INOUT21			0x0E0 0x2D0 0x658 0x6 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B0_09_GPT2_CLK				0x0E0 0x2D0 0x000 0x7 0x0
-
-#define MXRT1050_IOMUXC_GPIO_AD_B0_10_JTAG_TDO				0x0E4 0x2D4 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_10_FLEXPWM1_PWM3_A			0x0E4 0x2D4 0x454 0x1 0x3
-#define MXRT1050_IOMUXC_GPIO_AD_B0_10_ENET_CRS				0x0E4 0x2D4 0x000 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_10_SAI2_MCLK				0x0E4 0x2D4 0x5B0 0x3 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B0_10_CSI_DATA03			0x0E4 0x2D4 0x404 0x4 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B0_10_GPIO1_IO10			0x0E4 0x2D4 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_10_XBAR_INOUT22			0x0E4 0x2D4 0x638 0x6 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B0_10_ENET_1588_EVENT0_OUT		0x0E4 0x2D4 0x000 0x7 0x0
-
-#define MXRT1050_IOMUXC_GPIO_AD_B0_11_JTAG_TRSTB			0x0E8 0x2D8 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_11_FLEXPWM1_PWM3_B			0x0E8 0x2D8 0x464 0x1 0x3
-#define MXRT1050_IOMUXC_GPIO_AD_B0_11_ENET_COL				0x0E8 0x2D8 0x000 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_11_WDOG1_B				0x0E8 0x2D8 0x000 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_11_CSI_DATA02			0x0E8 0x2D8 0x400 0x4 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B0_11_GPIO1_IO11			0x0E8 0x2D8 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_11_XBAR_INOUT23			0x0E8 0x2D8 0x63C 0x6 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B0_11_ENET_1588_EVENT0_IN		0x0E8 0x2D8 0x444 0x7 0x1
-
-#define MXRT1050_IOMUXC_GPIO_AD_B0_12_LPI2C4_SCL			0x0EC 0x2DC 0x4E4 0x0 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B0_12_CCM_PMIC_READY			0x0EC 0x2DC 0x3FC 0x1 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B0_12_LPUART1_TXD			0x0EC 0x2DC 0x000 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_12_WDOG2_B				0x0EC 0x2DC 0x000 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_12_FLEXPWM1_PWM2_X			0x0EC 0x2DC 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_12_GPIO1_IO12			0x0EC 0x2DC 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_12_ENET_1588_EVENT1_OUT		0x0EC 0x2DC 0x000 0x6 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_12_NMI				0x0EC 0x2DC 0x568 0x7 0x0
-
-#define MXRT1050_IOMUXC_GPIO_AD_B0_13_LPI2C4_SDA			0x0F0 0x2E0 0x4E8 0x0 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B0_13_GPT1_CLK				0x0F0 0x2E0 0x000 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_13_LPUART1_RXD			0x0F0 0x2E0 0x000 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_13_EWM_OUT_B				0x0F0 0x2E0 0x000 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_13_FLEXPWM1_PWM3_X			0x0F0 0x2E0 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_13_GPIO1_IO13			0x0F0 0x2E0 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_13_ENET_1588_EVENT1_IN		0x0F0 0x2E0 0x000 0x6 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_13_REF_CLK_24M			0x0F0 0x2E0 0x000 0x7 0x0
-
-#define MXRT1050_IOMUXC_GPIO_AD_B0_14_USB_OTG2_OC			0x0F4 0x2E4 0x5CC 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_14_XBAR_INOUT24			0x0F4 0x2E4 0x640 0x1 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B0_14_LPUART1_CTS_B			0x0F4 0x2E4 0x000 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_14_ENET_1588_EVENT0_OUT		0x0F4 0x2E4 0x000 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_14_CSI_VSYNC				0x0F4 0x2E4 0x428 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_14_GPIO1_IO14			0x0F4 0x2E4 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_14_FLEXCAN2_TX			0x0F4 0x2E4 0x000 0x6 0x0
-
-#define MXRT1050_IOMUXC_GPIO_AD_B0_15_USB_OTG2_PWR			0x0F8 0x2E8 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_15_XBAR_INOUT25			0x0F8 0x2E8 0x650 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_15_LPUART1_RTS_B			0x0F8 0x2E8 0x000 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_15_ENET_1588_EVENT0_IN		0x0F8 0x2E8 0x444 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_15_CSI_HSYNC				0x0F8 0x2E8 0x420 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_15_GPIO1_IO15			0x0F8 0x2E8 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B0_15_FLEXCAN2_RX			0x0F8 0x2E8 0x450 0x6 0x2
-#define MXRT1050_IOMUXC_GPIO_AD_B0_15_WDOG1_WDOG_RST_B_DEB		0x0F8 0x2E8 0x000 0x7 0x0
-
-#define MXRT1050_IOMUXC_GPIO_AD_B1_00_USB_OTG2_ID			0x0FC 0x2EC 0x3F8 0x0 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B1_00_TMR3_TIMER0			0x0FC 0x2EC 0x57C 0x1 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B1_00_LPUART2_CTS_B			0x0FC 0x2EC 0x000 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B1_00_LPI2C1_SCL			0x0FC 0x2EC 0x4CC 0x3 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B1_00_WDOG1_B				0x0FC 0x2EC 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B1_00_GPIO1_IO16			0x0FC 0x2EC 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B1_00_USDHC1_WP				0x0FC 0x2EC 0x5D8 0x6 0x2
-#define MXRT1050_IOMUXC_GPIO_AD_B1_00_KPP_ROW07				0x0FC 0x2EC 0x000 0x7 0x0
-
-#define MXRT1050_IOMUXC_GPIO_AD_B1_01_USB_OTG1_PWR			0x100 0x2F0 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B1_01_TMR3_TIMER1			0x100 0x2F0 0x580 0x1 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B1_01_LPUART2_RTS_B			0x100 0x2F0 0x000 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B1_01_LPI2C1_SDA			0x100 0x2F0 0x4D0 0x3 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B1_01_CCM_PMIC_READY			0x100 0x2F0 0x3FC 0x4 0x2
-#define MXRT1050_IOMUXC_GPIO_AD_B1_01_GPIO1_IO17			0x100 0x2F0 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B1_01_USDHC1_VSELECT			0x100 0x2F0 0x000 0x6 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B1_01_KPP_COL07				0x100 0x2F0 0x000 0x7 0x0
-
-#define MXRT1050_IOMUXC_GPIO_AD_B1_02_USB_OTG1_ID			0x104 0x2F4 0x3F4 0x0 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B1_02_TMR3_TIMER2			0x104 0x2F4 0x584 0x1 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B1_02_LPUART2_TXD			0x104 0x2F4 0x530 0x2 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B1_02_SPDIF_OUT				0x104 0x2F4 0x000 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B1_02_ENET_1588_EVENT2_OUT		0x104 0x2F4 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B1_02_GPIO1_IO18			0x104 0x2F4 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B1_02_USDHC1_CD_B			0x104 0x2F4 0x5D4 0x6 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B1_02_KPP_ROW06				0x104 0x2F4 0x000 0x7 0x0
-
-#define MXRT1050_IOMUXC_GPIO_AD_B1_03_USB_OTG1_OC			0x108 0x2F8 0x5D0 0x0 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B1_03_TMR3_TIMER3			0x108 0x2F8 0x588 0x1 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B1_03_LPUART2_RXD			0x108 0x2F8 0x52C 0x2 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B1_03_SPDIF_IN				0x108 0x2F8 0x5C8 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B1_03_ENET_1588_EVENT2_IN		0x108 0x2F8 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B1_03_GPIO1_IO19			0x108 0x2F8 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B1_03_USDHC2_CD_B			0x108 0x2F8 0x5E0 0x6 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B1_03_KPP_COL06				0x108 0x2F8 0x000 0x7 0x0
-
-#define MXRT1050_IOMUXC_GPIO_AD_B1_04_FLEXSPI_B_DATA3			0x10C 0x2FC 0x4C4 0x0 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B1_04_ENET_MDC				0x10C 0x2FC 0x000 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B1_04_LPUART3_CTS_B			0x10C 0x2FC 0x534 0x2 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B1_04_SPDIF_SR_CLK			0x10C 0x2FC 0x000 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B1_04_CSI_PIXCLK			0x10C 0x2FC 0x424 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B1_04_GPIO1_IO20			0x10C 0x2FC 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B1_04_USDHC2_DATA0			0x10C 0x2FC 0x5E8 0x6 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B1_04_KPP_ROW05				0x10C 0x2FC 0x000 0x7 0x0
-
-#define MXRT1050_IOMUXC_GPIO_AD_B1_05_FLEXSPI_B_DATA2			0x110 0x300 0x4C0 0x0 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B1_05_ENET_MDIO				0x110 0x300 0x430 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B1_05_LPUART3_RTS_B			0x110 0x300 0x000 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B1_05_SPDIF_OUT				0x110 0x300 0x000 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B1_05_CSI_MCLK				0x110 0x300 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B1_05_GPIO1_IO21			0x110 0x300 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B1_05_USDHC2_DATA1			0x110 0x300 0x5EC 0x6 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B1_05_KPP_COL05				0x110 0x300 0x000 0x7 0x0
-
-#define MXRT1050_IOMUXC_GPIO_AD_B1_06_FLEXSPI_B_DATA1			0x114 0x304 0x4BC 0x0 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B1_06_LPI2C3_SDA			0x114 0x304 0x4E0 0x1 0x2
-#define MXRT1050_IOMUXC_GPIO_AD_B1_06_LPUART3_TXD			0x114 0x304 0x53C 0x2 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B1_06_SPDIF_LOCK			0x114 0x304 0x000 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B1_06_CSI_VSYNC				0x114 0x304 0x428 0x4 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B1_06_GPIO1_IO22			0x114 0x304 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B1_06_USDHC2_DATA2			0x114 0x304 0x5F0 0x6 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B1_06_KPP_ROW04				0x114 0x304 0x000 0x7 0x0
-
-#define MXRT1050_IOMUXC_GPIO_AD_B1_07_FLEXSPI_B_DATA0			0x118 0x308 0x4B8 0x0 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B1_07_LPI2C3_SCL			0x118 0x308 0x4DC 0x1 0x2
-#define MXRT1050_IOMUXC_GPIO_AD_B1_07_LPUART3_RXD			0x118 0x308 0x538 0x2 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B1_07_SPDIF_EXT_CLK			0x118 0x308 0x000 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B1_07_CSI_HSYNC				0x118 0x308 0x420 0x4 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B1_07_GPIO1_IO23			0x118 0x308 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B1_07_USDHC2_DATA3			0x118 0x308 0x5F4 0x6 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B1_07_KPP_COL04				0x118 0x308 0x000 0x7 0x0
-
-#define MXRT1050_IOMUXC_GPIO_AD_B1_08_FLEXSPI_A_SS1_B			0x11C 0x30C 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B1_08_FLEXPWM4_PWM0_A			0x11C 0x30C 0x494 0x1 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B1_08_FLEXCAN1_TX			0x11C 0x30C 0x000 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B1_08_CCM_PMIC_READY			0x11C 0x30C 0x3FC 0x3 0x3
-#define MXRT1050_IOMUXC_GPIO_AD_B1_08_CSI_DATA09			0x11C 0x30C 0x41C 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B1_08_GPIO1_IO24			0x11C 0x30C 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B1_08_USDHC2_CMD			0x11C 0x30C 0x5E4 0x6 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B1_08_KPP_ROW03				0x11C 0x30C 0x000 0x7 0x0
-
-#define MXRT1050_IOMUXC_GPIO_AD_B1_09_FLEXSPI_A_DQS			0x120 0x310 0x4A4 0x0 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B1_09_FLEXPWM4_PWM1_A			0x120 0x310 0x498 0x1 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B1_09_FLEXCAN1_RX			0x120 0x310 0x44C 0x2 0x2
-#define MXRT1050_IOMUXC_GPIO_AD_B1_09_SAI1_MCLK				0x120 0x310 0x58C 0x3 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B1_09_CSI_DATA08			0x120 0x310 0x418 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B1_09_GPIO1_IO25			0x120 0x310 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B1_09_USDHC2_CLK			0x120 0x310 0x5DC 0x6 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B1_09_KPP_COL03				0x120 0x310 0x000 0x7 0x0
-
-#define MXRT1050_IOMUXC_GPIO_AD_B1_10_FLEXSPI_A_DATA3			0x124 0x314 0x4B4 0x0 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B1_10_WDOG1_B				0x124 0x314 0x000 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B1_10_LPUART8_TXD			0x124 0x314 0x564 0x2 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B1_10_SAI1_RX_SYNC			0x124 0x314 0x5A4 0x3 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B1_10_CSI_DATA07			0x124 0x314 0x414 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B1_10_GPIO1_IO26			0x124 0x314 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B1_10_USDHC2_WP				0x124 0x314 0x608 0x6 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B1_10_KPP_ROW02				0x124 0x314 0x000 0x7 0x0
-
-#define MXRT1050_IOMUXC_GPIO_AD_B1_11_FLEXSPI_A_DATA2			0x128 0x318 0x4B0 0x0 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B1_11_EWM_OUT_B				0x128 0x318 0x000 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B1_11_LPUART8_RXD			0x128 0x318 0x560 0x2 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B1_11_SAI1_RX_BCLK			0x128 0x318 0x590 0x3 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B1_11_CSI_DATA06			0x128 0x318 0x410 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B1_11_GPIO1_IO27			0x128 0x318 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B1_11_USDHC2_RESET_B			0x128 0x318 0x000 0x6 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B1_11_KPP_COL02				0x128 0x318 0x000 0x7 0x0
-
-#define MXRT1050_IOMUXC_GPIO_AD_B1_12_FLEXSPI_A_DATA1			0x12C 0x31C 0x4AC 0x0 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B1_12_ACMP1_OUT				0x12C 0x31C 0x000 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B1_12_LPSPI3_PCS0			0x12C 0x31C 0x50C 0x2 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B1_12_SAI1_RX_DATA00			0x12C 0x31C 0x594 0x3 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B1_12_CSI_DATA05			0x12C 0x31C 0x40C 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B1_12_GPIO1_IO28			0x12C 0x31C 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B1_12_USDHC2_DATA4			0x12C 0x31C 0x5F8 0x6 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B1_12_KPP_ROW01				0x12C 0x31C 0x000 0x7 0x0
-
-#define MXRT1050_IOMUXC_GPIO_AD_B1_13_FLEXSPI_A_DATA0			0x130 0x320 0x4A8 0x0 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B1_13_ACMP2_OUT				0x130 0x320 0x000 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B1_13_LPSPI3_SDI			0x130 0x320 0x514 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B1_13_SAI1_TX_DATA00			0x130 0x320 0x000 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B1_13_CSI_DATA04			0x130 0x320 0x408 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B1_13_GPIO1_IO29			0x130 0x320 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B1_13_USDHC2_DATA5			0x130 0x320 0x5FC 0x6 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B1_13_KPP_COL01				0x130 0x320 0x000 0x7 0x0
-
-#define MXRT1050_IOMUXC_GPIO_AD_B1_14_FLEXSPI_A_SCLK			0x134 0x324 0x4C8 0x0 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B1_14_ACMP3_OUT				0x134 0x324 0x000 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B1_14_LPSPI3_SDO			0x134 0x324 0x518 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B1_14_SAI1_TX_BCLK			0x134 0x324 0x5A8 0x3 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B1_14_CSI_DATA03			0x134 0x324 0x404 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B1_14_GPIO1_IO30			0x134 0x324 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B1_14_USDHC2_DATA6			0x134 0x324 0x600 0x6 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B1_14_KPP_ROW00				0x134 0x324 0x000 0x7 0x0
-
-#define MXRT1050_IOMUXC_GPIO_AD_B1_15_FLEXSPI_A_SS0_B			0x138 0x328 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B1_15_ACMP4_OUT				0x138 0x328 0x000 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B1_15_LPSPI3_SCK			0x138 0x328 0x510 0x2 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B1_15_SAI1_TX_SYNC			0x138 0x328 0x5AC 0x3 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B1_15_CSI_DATA02			0x138 0x328 0x400 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B1_15_GPIO1_IO31			0x138 0x328 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_AD_B1_15_USDHC2_DATA7			0x138 0x328 0x604 0x6 0x1
-#define MXRT1050_IOMUXC_GPIO_AD_B1_15_KPP_COL00				0x138 0x328 0x000 0x7 0x0
-
-#define MXRT1050_IOMUXC_GPIO_B0_00_LCD_CLK				0x13C 0x32C 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_00_TMR1_TIMER0				0x13C 0x32C 0x000 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_00_MQS_RIGHT				0x13C 0x32C 0x000 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_00_LPSPI4_PCS0				0x13C 0x32C 0x51C 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_00_FLEXIO2_D00				0x13C 0x32C 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_00_GPIO2_IO00				0x13C 0x32C 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_00_SEMC_CSX1				0x13C 0x32C 0x000 0x6 0x0
-
-#define MXRT1050_IOMUXC_GPIO_B0_01_LCD_ENABLE				0x140 0x330 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_01_TMR1_TIMER1				0x140 0x330 0x000 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_01_MQS_LEFT				0x140 0x330 0x000 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_01_LPSPI4_SDI				0x140 0x330 0x524 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_01_FLEXIO2_D01				0x140 0x330 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_01_GPIO2_IO01				0x140 0x330 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_01_SEMC_CSX2				0x140 0x330 0x000 0x6 0x0
-
-#define MXRT1050_IOMUXC_GPIO_B0_02_LCD_HSYNC				0x144 0x334 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_02_TMR1_TIMER2				0x144 0x334 0x000 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_02_FLEXCAN1_TX				0x144 0x334 0x000 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_02_LPSPI4_SDO				0x144 0x334 0x528 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_02_FLEXIO2_D02				0x144 0x334 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_02_GPIO2_IO02				0x144 0x334 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_02_SEMC_CSX3				0x144 0x334 0x000 0x6 0x0
-
-#define MXRT1050_IOMUXC_GPIO_B0_03_LCD_VSYNC				0x148 0x338 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_03_TMR2_TIMER0				0x148 0x338 0x56C 0x1 0x1
-#define MXRT1050_IOMUXC_GPIO_B0_03_FLEXCAN1_RX				0x148 0x338 0x44C 0x2 0x3
-#define MXRT1050_IOMUXC_GPIO_B0_03_LPSPI4_SCK				0x148 0x338 0x520 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_03_FLEXIO2_D03				0x148 0x338 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_03_GPIO2_IO03				0x148 0x338 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_03_WDOG2_RESET_B_DEB			0x148 0x338 0x000 0x6 0x0
-
-#define MXRT1050_IOMUXC_GPIO_B0_04_LCD_DATA00				0x14C 0x33C 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_04_TMR2_TIMER1				0x14C 0x33C 0x570 0x1 0x1
-#define MXRT1050_IOMUXC_GPIO_B0_04_LPI2C2_SCL				0x14C 0x33C 0x4D4 0x2 0x1
-#define MXRT1050_IOMUXC_GPIO_B0_04_ARM_TRACE00				0x14C 0x33C 0x000 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_04_FLEXIO2_D04				0x14C 0x33C 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_04_GPIO2_IO04				0x14C 0x33C 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_04_SRC_BT_CFG00				0x14C 0x33C 0x000 0x6 0x0
-
-#define MXRT1050_IOMUXC_GPIO_B0_05_LCD_DATA01				0x150 0x340 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_05_TMR2_TIMER2				0x150 0x340 0x574 0x1 0x1
-#define MXRT1050_IOMUXC_GPIO_B0_05_LPI2C2_SDA				0x150 0x340 0x4D8 0x2 0x1
-#define MXRT1050_IOMUXC_GPIO_B0_05_ARM_TRACE01				0x150 0x340 0x000 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_05_FLEXIO2_D05				0x150 0x340 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_05_GPIO2_IO05				0x150 0x340 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_05_SRC_BT_CFG01				0x150 0x340 0x000 0x6 0x0
-
-#define MXRT1050_IOMUXC_GPIO_B0_06_LCD_DATA02				0x154 0x344 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_06_TMR3_TIMER0				0x154 0x344 0x57C 0x1 0x2
-#define MXRT1050_IOMUXC_GPIO_B0_06_FLEXPWM2_PWM0_A			0x154 0x344 0x478 0x2 0x1
-#define MXRT1050_IOMUXC_GPIO_B0_06_ARM_TRACE02				0x154 0x344 0x000 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_06_FLEXIO2_D06				0x154 0x344 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_06_GPIO2_IO06				0x154 0x344 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_06_SRC_BT_CFG02				0x154 0x344 0x000 0x6 0x0
-
-#define MXRT1050_IOMUXC_GPIO_B0_07_LCD_DATA03				0x158 0x348 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_07_TMR3_TIMER1				0x158 0x348 0x580 0x1 0x2
-#define MXRT1050_IOMUXC_GPIO_B0_07_FLEXPWM2_PWM0_B			0x158 0x348 0x488 0x2 0x1
-#define MXRT1050_IOMUXC_GPIO_B0_07_ARM_TRACE03				0x158 0x348 0x000 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_07_FLEXIO2_D07				0x158 0x348 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_07_GPIO2_IO07				0x158 0x348 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_07_SRC_BT_CFG03				0x158 0x348 0x000 0x6 0x0
-
-#define MXRT1050_IOMUXC_GPIO_B0_08_LCD_DATA04				0x15C 0x34C 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_08_TMR3_TIMER2				0x15C 0x34C 0x584 0x1 0x2
-#define MXRT1050_IOMUXC_GPIO_B0_08_FLEXPWM2_PWM1_A			0x15C 0x34C 0x47C 0x2 0x1
-#define MXRT1050_IOMUXC_GPIO_B0_08_LPUART3_TXD				0x15C 0x34C 0x53C 0x3 0x2
-#define MXRT1050_IOMUXC_GPIO_B0_08_FLEXIO2_D08				0x15C 0x34C 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_08_GPIO2_IO08				0x15C 0x34C 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_08_SRC_BT_CFG04				0x15C 0x34C 0x000 0x6 0x0
-
-#define MXRT1050_IOMUXC_GPIO_B0_09_LCD_DATA05				0x160 0x350 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_09_TMR4_TIMER0				0x160 0x350 0x000 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_09_FLEXPWM2_PWM1_B			0x160 0x350 0x48C 0x2 0x1
-#define MXRT1050_IOMUXC_GPIO_B0_09_LPUART3_RXD				0x160 0x350 0x538 0x3 0x2
-#define MXRT1050_IOMUXC_GPIO_B0_09_FLEXIO2_D09				0x160 0x350 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_09_GPIO2_IO09				0x160 0x350 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_09_SRC_BT_CFG05				0x160 0x350 0x000 0x6 0x0
-
-#define MXRT1050_IOMUXC_GPIO_B0_10_LCD_DATA06				0x164 0x354 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_10_TMR4_TIMER1				0x164 0x354 0x000 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_10_FLEXPWM2_PWM2_A			0x164 0x354 0x480 0x2 0x1
-#define MXRT1050_IOMUXC_GPIO_B0_10_SAI1_TX_DATA03			0x164 0x354 0x598 0x3 0x1
-#define MXRT1050_IOMUXC_GPIO_B0_10_FLEXIO2_D10				0x164 0x354 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_10_GPIO2_IO10				0x164 0x354 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_10_SRC_BT_CFG06				0x164 0x354 0x000 0x6 0x0
-
-#define MXRT1050_IOMUXC_GPIO_B0_11_LCD_DATA07				0x168 0x358 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_11_TMR4_TIMER2				0x168 0x358 0x000 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_11_FLEXPWM2_PWM2_B			0x168 0x358 0x490 0x2 0x1
-#define MXRT1050_IOMUXC_GPIO_B0_11_SAI1_TX_DATA02			0x168 0x358 0x59C 0x3 0x1
-#define MXRT1050_IOMUXC_GPIO_B0_11_FLEXIO2_D11				0x168 0x358 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_11_GPIO2_IO11				0x168 0x358 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_11_SRC_BT_CFG07				0x168 0x358 0x000 0x6 0x0
-
-#define MXRT1050_IOMUXC_GPIO_B0_12_LCD_DATA08				0x16C 0x35C 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_12_XBAR_INOUT10				0x16C 0x35C 0x000 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_12_ARM_TRACE_CLK			0x16C 0x35C 0x000 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_12_SAI1_TX_DATA01			0x16C 0x35C 0x5A0 0x3 0x1
-#define MXRT1050_IOMUXC_GPIO_B0_12_FLEXIO2_D12				0x16C 0x35C 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_12_GPIO2_IO12				0x16C 0x35C 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_12_SRC_BT_CFG08				0x16C 0x35C 0x000 0x6 0x0
-
-#define MXRT1050_IOMUXC_GPIO_B0_13_LCD_DATA09				0x170 0x360 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_13_XBAR_INOUT11				0x170 0x360 0x000 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_13_ARM_TRACE_SWO			0x170 0x360 0x000 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_13_SAI1_MCLK				0x170 0x360 0x58C 0x3 0x2
-#define MXRT1050_IOMUXC_GPIO_B0_13_FLEXIO2_D13				0x170 0x360 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_13_GPIO2_IO13				0x170 0x360 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_13_SRC_BT_CFG09				0x170 0x360 0x000 0x6 0x0
-
-#define MXRT1050_IOMUXC_GPIO_B0_14_LCD_DATA10				0x174 0x364 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_14_XBAR_INOUT12				0x174 0x364 0x000 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_14_ARM_CM7_TXEV				0x174 0x364 0x000 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_14_SAI1_RX_SYNC				0x174 0x364 0x5A4 0x3 0x2
-#define MXRT1050_IOMUXC_GPIO_B0_14_FLEXIO2_D14				0x174 0x364 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_14_GPIO2_IO14				0x174 0x364 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_14_SRC_BT_CFG10				0x174 0x364 0x000 0x6 0x0
-
-#define MXRT1050_IOMUXC_GPIO_B0_15_LCD_DATA11				0x178 0x368 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_15_XBAR_INOUT13				0x178 0x368 0x000 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_15_ARM_CM7_RXEV				0x178 0x368 0x000 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_15_SAI1_RX_BCLK				0x178 0x368 0x590 0x3 0x2
-#define MXRT1050_IOMUXC_GPIO_B0_15_FLEXIO2_D15				0x178 0x368 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_15_GPIO2_IO15				0x178 0x368 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_B0_15_SRC_BT_CFG11				0x178 0x368 0x000 0x6 0x0
-
-#define MXRT1050_IOMUXC_GPIO_B1_00_LCD_DATA12				0x17C 0x36C 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_00_XBAR_INOUT14				0x17C 0x36C 0x644 0x1 0x1
-#define MXRT1050_IOMUXC_GPIO_B1_00_LPUART4_TXD				0x17C 0x36C 0x544 0x2 0x2
-#define MXRT1050_IOMUXC_GPIO_B1_00_SAI1_RX_DATA00			0x17C 0x36C 0x594 0x3 0x2
-#define MXRT1050_IOMUXC_GPIO_B1_00_FLEXIO2_D16				0x17C 0x36C 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_00_GPIO2_IO16				0x17C 0x36C 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_00_FLEXPWM1_PWM3_A			0x17C 0x36C 0x454 0x6 0x4
-
-#define MXRT1050_IOMUXC_GPIO_B1_01_LCD_DATA13				0x180 0x370 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_01_XBAR_INOUT15				0x180 0x370 0x648 0x1 0x1
-#define MXRT1050_IOMUXC_GPIO_B1_01_LPUART4_RXD				0x180 0x370 0x540 0x2 0x2
-#define MXRT1050_IOMUXC_GPIO_B1_01_SAI1_TX_DATA00			0x180 0x370 0x000 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_01_FLEXIO2_D17				0x180 0x370 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_01_GPIO2_IO17				0x180 0x370 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_01_FLEXPWM1_PWM3_B			0x180 0x370 0x464 0x6 0x4
-
-#define MXRT1050_IOMUXC_GPIO_B1_02_LCD_DATA14				0x184 0x374 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_02_XBAR_INOUT16				0x184 0x374 0x64C 0x1 0x1
-#define MXRT1050_IOMUXC_GPIO_B1_02_LPSPI4_PCS2				0x184 0x374 0x000 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_02_SAI1_TX_BCLK				0x184 0x374 0x5A8 0x3 0x2
-#define MXRT1050_IOMUXC_GPIO_B1_02_FLEXIO2_D18				0x184 0x374 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_02_GPIO2_IO18				0x184 0x374 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_02_FLEXPWM2_PWM3_A			0x184 0x374 0x000 0x6 0x0
-
-#define MXRT1050_IOMUXC_GPIO_B1_03_LCD_DATA15				0x188 0x378 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_03_XBAR_INOUT17				0x188 0x378 0x62C 0x1 0x3
-#define MXRT1050_IOMUXC_GPIO_B1_03_LPSPI4_PCS1				0x188 0x378 0x000 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_03_SAI1_TX_SYNC				0x188 0x378 0x5AC 0x3 0x2
-#define MXRT1050_IOMUXC_GPIO_B1_03_FLEXIO2_D19				0x188 0x378 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_03_GPIO2_IO19				0x188 0x378 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_03_FLEXPWM2_PWM3_B			0x188 0x378 0x484 0x6 0x3
-
-#define MXRT1050_IOMUXC_GPIO_B1_04_LCD_DATA16				0x18C 0x37C 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_04_LPSPI4_PCS0				0x18C 0x37C 0x51C 0x1 0x1
-#define MXRT1050_IOMUXC_GPIO_B1_04_CSI_DATA15				0x18C 0x37C 0x000 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_04_ENET_RX_DATA00			0x18C 0x37C 0x434 0x3 0x1
-#define MXRT1050_IOMUXC_GPIO_B1_04_FLEXIO2_D20				0x18C 0x37C 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_04_GPIO2_IO20				0x18C 0x37C 0x000 0x5 0x0
-
-#define MXRT1050_IOMUXC_GPIO_B1_05_LCD_DATA17				0x190 0x380 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_05_LPSPI4_SDI				0x190 0x380 0x524 0x1 0x1
-#define MXRT1050_IOMUXC_GPIO_B1_05_CSI_DATA14				0x190 0x380 0x000 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_05_ENET_RX_DATA01			0x190 0x380 0x438 0x3 0x1
-#define MXRT1050_IOMUXC_GPIO_B1_05_FLEXIO2_D21				0x190 0x380 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_05_GPIO2_IO21				0x190 0x380 0x000 0x5 0x0
-
-#define MXRT1050_IOMUXC_GPIO_B1_06_LCD_DATA18				0x194 0x384 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_06_LPSPI4_SDO				0x194 0x384 0x528 0x1 0x1
-#define MXRT1050_IOMUXC_GPIO_B1_06_CSI_DATA13				0x194 0x384 0x000 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_06_ENET_RX_EN				0x194 0x384 0x43C 0x3 0x1
-#define MXRT1050_IOMUXC_GPIO_B1_06_FLEXIO2_D22				0x194 0x384 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_06_GPIO2_IO22				0x194 0x384 0x000 0x5 0x0
-
-#define MXRT1050_IOMUXC_GPIO_B1_07_LCD_DATA19				0x198 0x388 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_07_LPSPI4_SCK				0x198 0x388 0x520 0x1 0x1
-#define MXRT1050_IOMUXC_GPIO_B1_07_CSI_DATA12				0x198 0x388 0x000 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_07_ENET_TX_DATA00			0x198 0x388 0x000 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_07_FLEXIO2_D23				0x198 0x388 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_07_GPIO2_IO23				0x198 0x388 0x000 0x5 0x0
-
-#define MXRT1050_IOMUXC_GPIO_B1_08_LCD_DATA20				0x19C 0x38C 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_08_TMR1_TIMER3				0x19C 0x38C 0x000 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_08_CSI_DATA11				0x19C 0x38C 0x000 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_08_ENET_TX_DATA01			0x19C 0x38C 0x000 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_08_FLEXIO2_D24				0x19C 0x38C 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_08_GPIO2_IO24				0x19C 0x38C 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_08_FLEXCAN2_TX				0x19C 0x38C 0x000 0x6 0x0
-
-#define MXRT1050_IOMUXC_GPIO_B1_09_LCD_DATA21				0x1A0 0x390 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_09_TMR2_TIMER3				0x1A0 0x390 0x578 0x1 0x1
-#define MXRT1050_IOMUXC_GPIO_B1_09_CSI_DATA10				0x1A0 0x390 0x000 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_09_ENET_TX_EN				0x1A0 0x390 0x000 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_09_FLEXIO2_D25				0x1A0 0x390 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_09_GPIO2_IO25				0x1A0 0x390 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_09_FLEXCAN2_RX				0x1A0 0x390 0x450 0x6 0x3
-
-#define MXRT1050_IOMUXC_GPIO_B1_10_LCD_DATA22				0x1A4 0x394 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_10_TMR3_TIMER3				0x1A4 0x394 0x588 0x1 0x2
-#define MXRT1050_IOMUXC_GPIO_B1_10_CSI_DATA00				0x1A4 0x394 0x000 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_10_ENET_TX_CLK				0x1A4 0x394 0x448 0x3 0x1
-#define MXRT1050_IOMUXC_GPIO_B1_10_FLEXIO2_D26				0x1A4 0x394 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_10_GPIO2_IO26				0x1A4 0x394 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_10_ENET_REF_CLK				0x1A4 0x394 0x42C 0x6 0x1
-
-#define MXRT1050_IOMUXC_GPIO_B1_11_LCD_DATA23				0x1A8 0x398 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_11_TMR4_TIMER3				0x1A8 0x398 0x000 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_11_CSI_DATA01				0x1A8 0x398 0x000 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_11_ENET_RX_ER				0x1A8 0x398 0x440 0x3 0x1
-#define MXRT1050_IOMUXC_GPIO_B1_11_FLEXIO2_D27				0x1A8 0x398 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_11_GPIO2_IO27				0x1A8 0x398 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_11_LPSPI4_PCS3				0x1A8 0x398 0x000 0x6 0x0
-
-#define MXRT1050_IOMUXC_GPIO_B1_12_LPUART5_TXD				0x1AC 0x39C 0x54C 0x1 0x1
-#define MXRT1050_IOMUXC_GPIO_B1_12_CSI_PIXCLK				0x1AC 0x39C 0x424 0x2 0x1
-#define MXRT1050_IOMUXC_GPIO_B1_12_ENET_1588_EVENT0_IN			0x1AC 0x39C 0x444 0x3 0x2
-#define MXRT1050_IOMUXC_GPIO_B1_12_FLEXIO2_D28				0x1AC 0x39C 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_12_GPIO2_IO28				0x1AC 0x39C 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_12_USDHC1_CD_B				0x1AC 0x39C 0x5D4 0x6 0x2
-
-#define MXRT1050_IOMUXC_GPIO_B1_13_WDOG1_B				0x1B0 0x3A0 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_13_LPUART5_RXD				0x1B0 0x3A0 0x548 0x1 0x1
-#define MXRT1050_IOMUXC_GPIO_B1_13_CSI_VSYNC				0x1B0 0x3A0 0x428 0x2 0x2
-#define MXRT1050_IOMUXC_GPIO_B1_13_ENET_1588_EVENT0_OUT			0x1B0 0x3A0 0x000 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_13_FLEXIO2_D29				0x1B0 0x3A0 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_13_GPIO2_IO29				0x1B0 0x3A0 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_13_USDHC1_WP				0x1B0 0x3A0 0x5D8 0x6 0x3
-
-#define MXRT1050_IOMUXC_GPIO_B1_14_ENET_MDC				0x1B4 0x3A4 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_14_FLEXPWM4_PWM2_A			0x1B4 0x3A4 0x49C 0x1 0x1
-#define MXRT1050_IOMUXC_GPIO_B1_14_CSI_HSYNC				0x1B4 0x3A4 0x420 0x2 0x2
-#define MXRT1050_IOMUXC_GPIO_B1_14_XBAR_INOUT02				0x1B4 0x3A4 0x60C 0x3 0x1
-#define MXRT1050_IOMUXC_GPIO_B1_14_FLEXIO2_D30				0x1B4 0x3A4 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_14_GPIO2_IO30				0x1B4 0x3A4 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_14_USDHC1_VSELECT			0x1B4 0x3A4 0x000 0x6 0x0
-
-#define MXRT1050_IOMUXC_GPIO_B1_15_ENET_MDIO				0x1B8 0x3A8 0x430 0x0 0x2
-#define MXRT1050_IOMUXC_GPIO_B1_15_FLEXPWM4_PWM3_A			0x1B8 0x3A8 0x4A0 0x1 0x1
-#define MXRT1050_IOMUXC_GPIO_B1_15_CSI_MCLK				0x1B8 0x3A8 0x000 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_15_XBAR_INOUT03				0x1B8 0x3A8 0x610 0x3 0x1
-#define MXRT1050_IOMUXC_GPIO_B1_15_FLEXIO2_D31				0x1B8 0x3A8 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_15_GPIO2_IO31				0x1B8 0x3A8 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_B1_15_USDHC1_RESET_B			0x1B8 0x3A8 0x000 0x6 0x0
-
-#define MXRT1050_IOMUXC_GPIO_SD_B0_00_USDHC1_CMD			0x1BC 0x3AC 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B0_00_FLEXPWM1_PWM0_A			0x1BC 0x3AC 0x458 0x1 0x1
-#define MXRT1050_IOMUXC_GPIO_SD_B0_00_LPI2C3_SCL			0x1BC 0x3AC 0x4DC 0x2 0x1
-#define MXRT1050_IOMUXC_GPIO_SD_B0_00_XBAR_INOUT04			0x1BC 0x3AC 0x614 0x3 0x1
-#define MXRT1050_IOMUXC_GPIO_SD_B0_00_LPSPI1_SCK			0x1BC 0x3AC 0x4F0 0x4 0x1
-#define MXRT1050_IOMUXC_GPIO_SD_B0_00_GPIO3_IO12			0x1BC 0x3AC 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B0_00_FLEXSPI_A_SS1_B			0x1BC 0x3AC 0x000 0x6 0x0
-
-#define MXRT1050_IOMUXC_GPIO_SD_B0_01_USDHC1_CLK			0x1C0 0x3B0 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B0_01_FLEXPWM1_PWM0_B			0x1C0 0x3B0 0x000 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B0_01_LPI2C3_SDA			0x1C0 0x3B0 0x4E0 0x2 0x1
-#define MXRT1050_IOMUXC_GPIO_SD_B0_01_XBAR_INOUT05			0x1C0 0x3B0 0x618 0x3 0x1
-#define MXRT1050_IOMUXC_GPIO_SD_B0_01_LPSPI1_PCS0			0x1C0 0x3B0 0x4EC 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B0_01_GPIO3_IO13			0x1C0 0x3B0 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B0_01_FLEXSPI_B_SS1_B			0x1C0 0x3B0 0x000 0x6 0x0
-
-#define MXRT1050_IOMUXC_GPIO_SD_B0_02_USDHC1_DATA0			0x1C4 0x3B4 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B0_02_FLEXPWM1_PWM1_A			0x1C4 0x3B4 0x45C 0x1 0x1
-#define MXRT1050_IOMUXC_GPIO_SD_B0_02_LPUART8_CTS_B			0x1C4 0x3B4 0x000 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B0_02_XBAR_INOUT06			0x1C4 0x3B4 0x61C 0x3 0x1
-#define MXRT1050_IOMUXC_GPIO_SD_B0_02_LPSPI1_SDO			0x1C4 0x3B4 0x4F8 0x4 0x1
-#define MXRT1050_IOMUXC_GPIO_SD_B0_02_GPIO3_IO14			0x1C4 0x3B4 0x000 0x5 0x0
-
-#define MXRT1050_IOMUXC_GPIO_SD_B0_03_USDHC1_DATA1			0x1C8 0x3B8 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B0_03_FLEXPWM1_PWM1_B			0x1C8 0x3B8 0x46C 0x1 0x1
-#define MXRT1050_IOMUXC_GPIO_SD_B0_03_LPUART8_RTS_B			0x1C8 0x3B8 0x000 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B0_03_XBAR_INOUT07			0x1C8 0x3B8 0x620 0x3 0x1
-#define MXRT1050_IOMUXC_GPIO_SD_B0_03_LPSPI1_SDI			0x1C8 0x3B8 0x4F4 0x4 0x1
-#define MXRT1050_IOMUXC_GPIO_SD_B0_03_GPIO3_IO15			0x1C8 0x3B8 0x000 0x5 0x0
-
-#define MXRT1050_IOMUXC_GPIO_SD_B0_04_USDHC1_DATA2			0x1CC 0x3BC 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B0_04_FLEXPWM1_PWM2_A			0x1CC 0x3BC 0x460 0x1 0x1
-#define MXRT1050_IOMUXC_GPIO_SD_B0_04_LPUART8_TXD			0x1CC 0x3BC 0x564 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B0_04_XBAR_INOUT08			0x1CC 0x3BC 0x624 0x3 0x1
-#define MXRT1050_IOMUXC_GPIO_SD_B0_04_FLEXSPI_B_SS0_B			0x1CC 0x3BC 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B0_04_GPIO3_IO16			0x1CC 0x3BC 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B0_04_CCM_CLKO1				0x1CC 0x3BC 0x000 0x6 0x0
-
-#define MXRT1050_IOMUXC_GPIO_SD_B0_05_USDHC1_DATA3			0x1D0 0x3C0 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B0_05_FLEXPWM1_PWM2_B			0x1D0 0x3C0 0x470 0x1 0x1
-#define MXRT1050_IOMUXC_GPIO_SD_B0_05_LPUART8_RXD			0x1D0 0x3C0 0x560 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B0_05_XBAR_INOUT09			0x1D0 0x3C0 0x628 0x3 0x1
-#define MXRT1050_IOMUXC_GPIO_SD_B0_05_FLEXSPI_B_DQS			0x1D0 0x3C0 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B0_05_GPIO3_IO17			0x1D0 0x3C0 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B0_05_CCM_CLKO2				0x1D0 0x3C0 0x000 0x6 0x0
-
-#define MXRT1050_IOMUXC_GPIO_SD_B1_00_USDHC2_DATA3			0x1D4 0x3C4 0x5F4 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_00_FLEXSPI_B_DATA3			0x1D4 0x3C4 0x4C4 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_00_FLEXPWM1_PWM3_A			0x1D4 0x3C4 0x454 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_00_SAI1_TX_DATA03			0x1D4 0x3C4 0x598 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_00_LPUART4_TXD			0x1D4 0x3C4 0x544 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_00_GPIO3_IO00			0x1D4 0x3C4 0x000 0x5 0x0
-
-#define MXRT1050_IOMUXC_GPIO_SD_B1_01_USDHC2_DATA2			0x1D8 0x3C8 0x5F0 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_01_FLEXSPI_B_DATA2			0x1D8 0x3C8 0x4C0 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_01_FLEXPWM1_PWM3_B			0x1D8 0x3C8 0x464 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_01_SAI1_TX_DATA02			0x1D8 0x3C8 0x59C 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_01_LPUART4_RXD			0x1D8 0x3C8 0x540 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_01_GPIO3_IO01			0x1D8 0x3C8 0x000 0x5 0x0
-
-#define MXRT1050_IOMUXC_GPIO_SD_B1_02_USDHC2_DATA1			0x1DC 0x3CC 0x5EC 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_02_FLEXSPI_B_DATA1			0x1DC 0x3CC 0x4BC 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_02_FLEXPWM2_PWM3_A			0x1DC 0x3CC 0x000 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_02_SAI1_TX_DATA01			0x1DC 0x3CC 0x5A0 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_02_FLEXCAN1_TX			0x1DC 0x3CC 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_02_GPIO3_IO02			0x1DC 0x3CC 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_02_CCM_WAIT				0x1DC 0x3CC 0x000 0x6 0x0
-
-#define MXRT1050_IOMUXC_GPIO_SD_B1_03_USDHC2_DATA0			0x1E0 0x3D0 0x5E8 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_03_FLEXSPI_B_DATA0			0x1E0 0x3D0 0x4B8 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_03_FLEXPWM2_PWM3_B			0x1E0 0x3D0 0x484 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_03_SAI1_MCLK				0x1E0 0x3D0 0x58C 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_03_FLEXCAN1_RX			0x1E0 0x3D0 0x44C 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_03_GPIO3_IO03			0x1E0 0x3D0 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_03_CCM_PMIC_READY			0x1E0 0x3D0 0x3FC 0x6 0x0
-
-#define MXRT1050_IOMUXC_GPIO_SD_B1_04_USDHC2_CLK			0x1E4 0x3D4 0x5DC 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_04_FLEXSPI_B_SCLK			0x1E4 0x3D4 0x000 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_04_LPI2C1_SCL			0x1E4 0x3D4 0x4CC 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_04_SAI1_RX_SYNC			0x1E4 0x3D4 0x5A4 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_04_FLEXCAN1_A_SS1_B			0x1E4 0x3D4 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_04_GPIO3_IO04			0x1E4 0x3D4 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_04_CCM_STOP				0x1E4 0x3D4 0x000 0x6 0x0
-
-#define MXRT1050_IOMUXC_GPIO_SD_B1_05_USDHC2_CMD			0x1E8 0x3D8 0x5E4 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_05_FLEXSPI_A_DQS			0x1E8 0x3D8 0x4A4 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_05_LPI2C1_SDA			0x1E8 0x3D8 0x4D0 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_05_SAI1_RX_BCLK			0x1E8 0x3D8 0x590 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_05_FLEXCAN1_B_SS0_B			0x1E8 0x3D8 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_05_GPIO3_IO05			0x1E8 0x3D8 0x000 0x5 0x0
-
-#define MXRT1050_IOMUXC_GPIO_SD_B1_06_USDHC2_RESET_B			0x1EC 0x3DC 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_06_FLEXSPI_A_SS0_B			0x1EC 0x3DC 0x000 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_06_LPUART7_CTS_B			0x1EC 0x3DC 0x000 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_06_SAI1_RX_DATA00			0x1EC 0x3DC 0x594 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_06_LPSPI2_PCS0			0x1EC 0x3DC 0x4FC 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_06_GPIO3_IO06			0x1EC 0x3DC 0x000 0x5 0x0
-
-#define MXRT1050_IOMUXC_GPIO_SD_B1_07_SEMC_CSX1				0x1F0 0x3E0 0x000 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_07_FLEXSPI_A_SCLK			0x1F0 0x3E0 0x4C8 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_07_LPUART7_RTS_B			0x1F0 0x3E0 0x000 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_07_SAI1_TX_DATA00			0x1F0 0x3E0 0x000 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_07_LPSPI2_SCK			0x1F0 0x3E0 0x500 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_07_GPIO3_IO07			0x1F0 0x3E0 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_07_CCM_REF_EN_B			0x1F0 0x3E0 0x000 0x6 0x0
-
-#define MXRT1050_IOMUXC_GPIO_SD_B1_08_USDHC2_DATA4			0x1F4 0x3E4 0x5F8 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_08_FLEXSPI_A_DATA0			0x1F4 0x3E4 0x4A8 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_08_LPUART7_TXD			0x1F4 0x3E4 0x55C 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_08_SAI1_TX_BLCK			0x1F4 0x3E4 0x5A8 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_08_LPSPI2_SDO			0x1F4 0x3E4 0x508 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_08_GPIO3_IO08			0x1F4 0x3E4 0x000 0x5 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_08_SEMC_CSX2				0x1F4 0x3E4 0x000 0x6 0x0
-
-#define MXRT1050_IOMUXC_GPIO_SD_B1_09_USDHC2_DATA5			0x1F8 0x3E8 0x5FC 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_09_FLEXSPI_A_DATA1			0x1F8 0x3E8 0x4AC 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_09_LPUART7_RXD			0x1F8 0x3E8 0x558 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_09_SAI1_TX_SYNC			0x1F8 0x3E8 0x5AC 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_09_LPSPI2_SDI			0x1F8 0x3E8 0x504 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_09_GPIO3_IO09			0x1F8 0x3E8 0x000 0x5 0x0
-
-#define MXRT1050_IOMUXC_GPIO_SD_B1_10_USDHC2_DATA6			0x1FC 0x3EC 0x600 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_10_FLEXSPI_A_DATA2			0x1FC 0x3EC 0x4B0 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_10_LPUART2_RXD			0x1FC 0x3EC 0x52C 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_10_LPI2C2_SDA			0x1FC 0x3EC 0x4D8 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_10_LPSPI2_PCS2			0x1FC 0x3EC 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_10_GPIO3_IO10			0x1FC 0x3EC 0x000 0x5 0x0
-
-#define MXRT1050_IOMUXC_GPIO_SD_B1_11_USDHC2_DATA7			0x200 0x3F0 0x604 0x0 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_11_FLEXSPI_A_DATA3			0x200 0x3F0 0x4B4 0x1 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_11_LPUART2_TXD			0x200 0x3F0 0x530 0x2 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_11_LPI2C2_SCL			0x200 0x3F0 0x4D4 0x3 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_11_LPSPI2_PCS3			0x200 0x3F0 0x000 0x4 0x0
-#define MXRT1050_IOMUXC_GPIO_SD_B1_11_GPIO3_IO11			0x200 0x3F0 0x000 0x5 0x0
-
-#endif /* _DT_BINDINGS_PINCTRL_IMXRT1050_PINFUNC_H */
diff --git a/arch/arm/dts/imxrt1050.dtsi b/arch/arm/dts/imxrt1050.dtsi
deleted file mode 100644
index a25eae9bd38..00000000000
--- a/arch/arm/dts/imxrt1050.dtsi
+++ /dev/null
@@ -1,160 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (C) 2019
- * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
- */
-
-#include "armv7-m.dtsi"
-#include <dt-bindings/interrupt-controller/arm-gic.h>
-#include <dt-bindings/clock/imxrt1050-clock.h>
-#include <dt-bindings/gpio/gpio.h>
-
-/ {
-	#address-cells = <1>;
-	#size-cells = <1>;
-
-	clocks {
-		osc: osc {
-			compatible = "fixed-clock";
-			#clock-cells = <0>;
-			clock-frequency = <24000000>;
-		};
-
-		osc3M: osc3M {
-			compatible = "fixed-clock";
-			#clock-cells = <0>;
-			clock-frequency = <3000000>;
-		};
-	};
-
-	soc {
-		lpuart1: serial@40184000 {
-			compatible = "fsl,imxrt1050-lpuart", "fsl,imx7ulp-lpuart";
-			reg = <0x40184000 0x4000>;
-			interrupts = <20>;
-			clocks = <&clks IMXRT1050_CLK_LPUART1>;
-			clock-names = "ipg";
-			status = "disabled";
-		};
-
-		iomuxc: pinctrl@401f8000 {
-			compatible = "fsl,imxrt1050-iomuxc";
-			reg = <0x401f8000 0x4000>;
-			fsl,mux_mask = <0x7>;
-		};
-
-		anatop: anatop@400d8000 {
-			compatible = "fsl,imxrt-anatop";
-			reg = <0x400d8000 0x4000>;
-		};
-
-		clks: clock-controller@400fc000 {
-			compatible = "fsl,imxrt1050-ccm";
-			reg = <0x400fc000 0x4000>;
-			interrupts = <95>, <96>;
-			clocks = <&osc>;
-			clock-names = "osc";
-			#clock-cells = <1>;
-			assigned-clocks = <&clks IMXRT1050_CLK_PLL1_BYPASS>,
-				<&clks IMXRT1050_CLK_PLL1_BYPASS>,
-				<&clks IMXRT1050_CLK_PLL2_BYPASS>,
-				<&clks IMXRT1050_CLK_PLL3_BYPASS>,
-				<&clks IMXRT1050_CLK_PLL3_PFD1_664_62M>,
-				<&clks IMXRT1050_CLK_PLL2_PFD2_396M>;
-			assigned-clock-parents = <&clks IMXRT1050_CLK_PLL1_REF_SEL>,
-				<&clks IMXRT1050_CLK_PLL1_ARM>,
-				<&clks IMXRT1050_CLK_PLL2_SYS>,
-				<&clks IMXRT1050_CLK_PLL3_USB_OTG>,
-				<&clks IMXRT1050_CLK_PLL3_USB_OTG>,
-				<&clks IMXRT1050_CLK_PLL2_SYS>;
-		};
-
-		edma1: dma-controller@400e8000 {
-			#dma-cells = <2>;
-			compatible = "fsl,imx7ulp-edma";
-			reg = <0x400e8000 0x4000>,
-				<0x400ec000 0x4000>;
-			dma-channels = <32>;
-			interrupts = <0>, <1>, <2>, <3>, <4>, <5>, <6>, <7>, <8>,
-				<9>, <10>, <11>, <12>, <13>, <14>, <15>, <16>;
-			clock-names = "dma", "dmamux0";
-			clocks = <&clks IMXRT1050_CLK_DMA>,
-				 <&clks IMXRT1050_CLK_DMA_MUX>;
-		};
-
-		usdhc1: mmc@402c0000 {
-			compatible = "fsl,imxrt1050-usdhc", "fsl,imx6sl-usdhc";
-			reg = <0x402c0000 0x4000>;
-			interrupts = <110>;
-			clocks = <&clks IMXRT1050_CLK_IPG_PDOF>,
-				<&clks IMXRT1050_CLK_AHB_PODF>,
-				<&clks IMXRT1050_CLK_USDHC1>;
-			clock-names = "ipg", "ahb", "per";
-			bus-width = <4>;
-			fsl,wp-controller;
-			no-1-8-v;
-			max-frequency = <4000000>;
-			fsl,tuning-start-tap = <20>;
-			fsl,tuning-step = <2>;
-			status = "disabled";
-		};
-
-		gpio1: gpio@401b8000 {
-			compatible = "fsl,imxrt1050-gpio", "fsl,imx35-gpio";
-			reg = <0x401b8000 0x4000>;
-			interrupts = <80>, <81>;
-			gpio-controller;
-			#gpio-cells = <2>;
-			interrupt-controller;
-			#interrupt-cells = <2>;
-		};
-
-		gpio2: gpio@401bc000 {
-			compatible = "fsl,imxrt1050-gpio", "fsl,imx35-gpio";
-			reg = <0x401bc000 0x4000>;
-			interrupts = <82>, <83>;
-			gpio-controller;
-			#gpio-cells = <2>;
-			interrupt-controller;
-			#interrupt-cells = <2>;
-		};
-
-		gpio3: gpio@401c0000 {
-			compatible = "fsl,imxrt1050-gpio", "fsl,imx35-gpio";
-			reg = <0x401c0000 0x4000>;
-			interrupts = <84>, <85>;
-			gpio-controller;
-			#gpio-cells = <2>;
-			interrupt-controller;
-			#interrupt-cells = <2>;
-		};
-
-		gpio4: gpio@401c4000 {
-			compatible = "fsl,imxrt1050-gpio", "fsl,imx35-gpio";
-			reg = <0x401c4000 0x4000>;
-			interrupts = <86>, <87>;
-			gpio-controller;
-			#gpio-cells = <2>;
-			interrupt-controller;
-			#interrupt-cells = <2>;
-		};
-
-		gpio5: gpio@400c0000 {
-			compatible = "fsl,imxrt1050-gpio", "fsl,imx35-gpio";
-			reg = <0x400c0000 0x4000>;
-			interrupts = <88>, <89>;
-			gpio-controller;
-			#gpio-cells = <2>;
-			interrupt-controller;
-			#interrupt-cells = <2>;
-		};
-
-		gpt: timer@401ec000 {
-			compatible = "fsl,imxrt1050-gpt", "fsl,imx6dl-gpt", "fsl,imx6sl-gpt";
-			reg = <0x401ec000 0x4000>;
-			interrupts = <100>;
-			clocks = <&osc3M>;
-			clock-names = "per";
-		};
-	};
-};
diff --git a/arch/arm/dts/ipq9574-rdp433-u-boot.dtsi b/arch/arm/dts/ipq9574-rdp433-u-boot.dtsi
new file mode 100644
index 00000000000..390e2338d65
--- /dev/null
+++ b/arch/arm/dts/ipq9574-rdp433-u-boot.dtsi
@@ -0,0 +1,25 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2025, Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+/ {
+	/* Will be removed when SMEM parsing is updated */
+	memory@40000000 {
+		device_type = "memory";
+		reg = <0x0 0x40000000 0x0 0x40000000>,
+		      <0x0 0x4a500000 0x0 0x00100000>;
+	};
+};
+
+&sdhc_1 {
+	sdhci-caps-mask = <0x0 0x04000000>;
+	sdhci-caps = <0x0 0x04000000>;	/* SDHCI_CAN_VDD_180 */
+
+	/*
+	 * This reset is needed to clear out the settings done by
+	 * previous boot loader. Without this the SDHCI_RESET_ALL
+	 * reset done sdhci_init() times out.
+	 */
+	resets = <&gcc GCC_SDCC_BCR>;
+};
diff --git a/arch/arm/dts/k3-am62-lp4-50-800-800.dtsi b/arch/arm/dts/k3-am62-lp4-50-800-800.dtsi
index c255ae6530f..ee9e213be84 100644
--- a/arch/arm/dts/k3-am62-lp4-50-800-800.dtsi
+++ b/arch/arm/dts/k3-am62-lp4-50-800-800.dtsi
@@ -1,8 +1,8 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
  * This file was generated with the
- * AM62x SysConfig DDR Subsystem Register Configuration Tool v0.09.07
- * Wed Mar 01 2023 17:52:11 GMT-0600 (Central Standard Time)
+ * AM623/AM625 SysConfig DDR Configuration Tool for AM64x, AM625, AM623, AM62Ax, AM62Px v0.10.02
+ * Tue Sep 17 2024 13:07:19 GMT+0530 (India Standard Time)
  * DDR Type: LPDDR4
  * F0 = 50MHz    F1 = NA     F2 = 800MHz
  * Density (per channel): 16Gb
@@ -13,6 +13,8 @@
 #define DDRSS_PLL_FHS_CNT 3
 #define DDRSS_PLL_FREQUENCY_1 400000000
 #define DDRSS_PLL_FREQUENCY_2 400000000
+#define DDRSS_SDRAM_IDX 15
+#define DDRSS_REGION_IDX 16
 
 #define DDRSS_CTL_0_DATA 0x00000B00
 #define DDRSS_CTL_1_DATA 0x00000000
@@ -847,7 +849,7 @@
 #define DDRSS_PHY_62_DATA 0x00000000
 #define DDRSS_PHY_63_DATA 0x00000000
 #define DDRSS_PHY_64_DATA 0x00000000
-#define DDRSS_PHY_65_DATA 0x00000004
+#define DDRSS_PHY_65_DATA 0x00000104
 #define DDRSS_PHY_66_DATA 0x00000000
 #define DDRSS_PHY_67_DATA 0x00000000
 #define DDRSS_PHY_68_DATA 0x00000000
@@ -869,7 +871,7 @@
 #define DDRSS_PHY_84_DATA 0x00100010
 #define DDRSS_PHY_85_DATA 0x00100010
 #define DDRSS_PHY_86_DATA 0x00100010
-#define DDRSS_PHY_87_DATA 0x02020010
+#define DDRSS_PHY_87_DATA 0x02000010
 #define DDRSS_PHY_88_DATA 0x51516041
 #define DDRSS_PHY_89_DATA 0x31C06000
 #define DDRSS_PHY_90_DATA 0x07AB0340
@@ -1103,7 +1105,7 @@
 #define DDRSS_PHY_318_DATA 0x00000000
 #define DDRSS_PHY_319_DATA 0x00000000
 #define DDRSS_PHY_320_DATA 0x00000000
-#define DDRSS_PHY_321_DATA 0x00000004
+#define DDRSS_PHY_321_DATA 0x00000104
 #define DDRSS_PHY_322_DATA 0x00000000
 #define DDRSS_PHY_323_DATA 0x00000000
 #define DDRSS_PHY_324_DATA 0x00000000
@@ -1125,7 +1127,7 @@
 #define DDRSS_PHY_340_DATA 0x00100010
 #define DDRSS_PHY_341_DATA 0x00100010
 #define DDRSS_PHY_342_DATA 0x00100010
-#define DDRSS_PHY_343_DATA 0x02020010
+#define DDRSS_PHY_343_DATA 0x02000010
 #define DDRSS_PHY_344_DATA 0x51516041
 #define DDRSS_PHY_345_DATA 0x31C06000
 #define DDRSS_PHY_346_DATA 0x07AB0340
@@ -2181,7 +2183,7 @@
 #define DDRSS_PHY_1396_DATA 0x0089FF00
 #define DDRSS_PHY_1397_DATA 0x000C3F11
 #define DDRSS_PHY_1398_DATA 0x01990000
-#define DDRSS_PHY_1399_DATA 0x000C3F11
+#define DDRSS_PHY_1399_DATA 0x000C3F91
 #define DDRSS_PHY_1400_DATA 0x01990000
 #define DDRSS_PHY_1401_DATA 0x3F0DFF11
 #define DDRSS_PHY_1402_DATA 0x01990000
diff --git a/arch/arm/dts/k3-am625-phyboard-lyra-rdk-u-boot.dtsi b/arch/arm/dts/k3-am625-phyboard-lyra-rdk-u-boot.dtsi
index 2bc5acbec23..52c9cafe992 100644
--- a/arch/arm/dts/k3-am625-phyboard-lyra-rdk-u-boot.dtsi
+++ b/arch/arm/dts/k3-am625-phyboard-lyra-rdk-u-boot.dtsi
@@ -177,6 +177,10 @@
 	bootph-all;
 };
 
+&usb0_phy_ctrl {
+	bootph-all;
+};
+
 &vcc_3v3_mmc {
 	bootph-all;
 };
diff --git a/arch/arm/dts/k3-am62a-ddr-1866mhz-32bit.dtsi b/arch/arm/dts/k3-am62a-ddr-1866mhz-32bit.dtsi
index 9f50d7eae69..35202651221 100644
--- a/arch/arm/dts/k3-am62a-ddr-1866mhz-32bit.dtsi
+++ b/arch/arm/dts/k3-am62a-ddr-1866mhz-32bit.dtsi
@@ -1,8 +1,8 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
  * This file was generated with the
- * AM62A SysConfig DDR Subsystem Register Configuration Tool v0.09.01
- * Wed Aug 10 2022 17:34:54 GMT-0500 (Central Daylight Time)
+ * AM62Ax SysConfig DDR Configuration Tool for AM64x, AM625, AM623, AM62Ax, AM62Px v0.10.02
+ * Tue Sep 17 2024 10:55:17 GMT+0530 (India Standard Time)
  * DDR Type: LPDDR4
  * F0 = 50MHz    F1 = NA     F2 = 1866MHz
  * Density (per channel): 8Gb
@@ -12,6 +12,8 @@
 #define DDRSS_PLL_FHS_CNT 5
 #define DDRSS_PLL_FREQUENCY_1 933000000
 #define DDRSS_PLL_FREQUENCY_2 933000000
+#define DDRSS_SDRAM_IDX 16
+#define DDRSS_REGION_IDX 17
 
 #define DDRSS_CTL_0_DATA 0x00000B00
 #define DDRSS_CTL_1_DATA 0x00000000
@@ -402,10 +404,10 @@
 #define DDRSS_CTL_386_DATA 0x01090903
 #define DDRSS_CTL_387_DATA 0x05020201
 #define DDRSS_CTL_388_DATA 0x0E081B1B
-#define DDRSS_CTL_389_DATA 0x0008030E
-#define DDRSS_CTL_390_DATA 0x0B12030E
-#define DDRSS_CTL_391_DATA 0x0B120314
-#define DDRSS_CTL_392_DATA 0x12120814
+#define DDRSS_CTL_389_DATA 0x0008040E
+#define DDRSS_CTL_390_DATA 0x0B120406
+#define DDRSS_CTL_391_DATA 0x0B120406
+#define DDRSS_CTL_392_DATA 0x12120806
 #define DDRSS_CTL_393_DATA 0x01000000
 #define DDRSS_CTL_394_DATA 0x07030701
 #define DDRSS_CTL_395_DATA 0x04000103
@@ -417,8 +419,8 @@
 #define DDRSS_CTL_401_DATA 0x00000200
 #define DDRSS_CTL_402_DATA 0x00000693
 #define DDRSS_CTL_403_DATA 0x00000E9C
-#define DDRSS_CTL_404_DATA 0x03050202
-#define DDRSS_CTL_405_DATA 0x37200201
+#define DDRSS_CTL_404_DATA 0x03000202
+#define DDRSS_CTL_405_DATA 0x37200404
 #define DDRSS_CTL_406_DATA 0x000038C8
 #define DDRSS_CTL_407_DATA 0x00000200
 #define DDRSS_CTL_408_DATA 0x00000200
@@ -426,8 +428,8 @@
 #define DDRSS_CTL_410_DATA 0x00000200
 #define DDRSS_CTL_411_DATA 0x0000FF84
 #define DDRSS_CTL_412_DATA 0x000237D0
-#define DDRSS_CTL_413_DATA 0x111F0402
-#define DDRSS_CTL_414_DATA 0x37200C0D
+#define DDRSS_CTL_413_DATA 0x111A0402
+#define DDRSS_CTL_414_DATA 0x37200C09
 #define DDRSS_CTL_415_DATA 0x000038C8
 #define DDRSS_CTL_416_DATA 0x00000200
 #define DDRSS_CTL_417_DATA 0x00000200
@@ -435,8 +437,8 @@
 #define DDRSS_CTL_419_DATA 0x00000200
 #define DDRSS_CTL_420_DATA 0x0000FF84
 #define DDRSS_CTL_421_DATA 0x000237D0
-#define DDRSS_CTL_422_DATA 0x111F0402
-#define DDRSS_CTL_423_DATA 0x00200C0D
+#define DDRSS_CTL_422_DATA 0x111A0402
+#define DDRSS_CTL_423_DATA 0x00200C09
 #define DDRSS_CTL_424_DATA 0x00000000
 #define DDRSS_CTL_425_DATA 0x02000A00
 #define DDRSS_CTL_426_DATA 0x00050003
@@ -939,7 +941,7 @@
 #define DDRSS_PHY_64_DATA 0x00000000
 #define DDRSS_PHY_65_DATA 0x00000000
 #define DDRSS_PHY_66_DATA 0x00000000
-#define DDRSS_PHY_67_DATA 0x00000004
+#define DDRSS_PHY_67_DATA 0x00000104
 #define DDRSS_PHY_68_DATA 0x00000000
 #define DDRSS_PHY_69_DATA 0x00000000
 #define DDRSS_PHY_70_DATA 0x00000000
@@ -964,7 +966,7 @@
 #define DDRSS_PHY_89_DATA 0x00100010
 #define DDRSS_PHY_90_DATA 0x00100010
 #define DDRSS_PHY_91_DATA 0x00100010
-#define DDRSS_PHY_92_DATA 0x02040010
+#define DDRSS_PHY_92_DATA 0x02000010
 #define DDRSS_PHY_93_DATA 0x00000005
 #define DDRSS_PHY_94_DATA 0x51516042
 #define DDRSS_PHY_95_DATA 0x31C06000
@@ -1195,7 +1197,7 @@
 #define DDRSS_PHY_320_DATA 0x00000000
 #define DDRSS_PHY_321_DATA 0x00000000
 #define DDRSS_PHY_322_DATA 0x00000000
-#define DDRSS_PHY_323_DATA 0x00000004
+#define DDRSS_PHY_323_DATA 0x00000104
 #define DDRSS_PHY_324_DATA 0x00000000
 #define DDRSS_PHY_325_DATA 0x00000000
 #define DDRSS_PHY_326_DATA 0x00000000
@@ -1220,7 +1222,7 @@
 #define DDRSS_PHY_345_DATA 0x00100010
 #define DDRSS_PHY_346_DATA 0x00100010
 #define DDRSS_PHY_347_DATA 0x00100010
-#define DDRSS_PHY_348_DATA 0x02040010
+#define DDRSS_PHY_348_DATA 0x02000010
 #define DDRSS_PHY_349_DATA 0x00000005
 #define DDRSS_PHY_350_DATA 0x51516042
 #define DDRSS_PHY_351_DATA 0x31C06000
@@ -1451,7 +1453,7 @@
 #define DDRSS_PHY_576_DATA 0x00000000
 #define DDRSS_PHY_577_DATA 0x00000000
 #define DDRSS_PHY_578_DATA 0x00000000
-#define DDRSS_PHY_579_DATA 0x00000004
+#define DDRSS_PHY_579_DATA 0x00000104
 #define DDRSS_PHY_580_DATA 0x00000000
 #define DDRSS_PHY_581_DATA 0x00000000
 #define DDRSS_PHY_582_DATA 0x00000000
@@ -1476,7 +1478,7 @@
 #define DDRSS_PHY_601_DATA 0x00100010
 #define DDRSS_PHY_602_DATA 0x00100010
 #define DDRSS_PHY_603_DATA 0x00100010
-#define DDRSS_PHY_604_DATA 0x02040010
+#define DDRSS_PHY_604_DATA 0x02000010
 #define DDRSS_PHY_605_DATA 0x00000005
 #define DDRSS_PHY_606_DATA 0x51516042
 #define DDRSS_PHY_607_DATA 0x31C06000
@@ -1707,7 +1709,7 @@
 #define DDRSS_PHY_832_DATA 0x00000000
 #define DDRSS_PHY_833_DATA 0x00000000
 #define DDRSS_PHY_834_DATA 0x00000000
-#define DDRSS_PHY_835_DATA 0x00000004
+#define DDRSS_PHY_835_DATA 0x00000104
 #define DDRSS_PHY_836_DATA 0x00000000
 #define DDRSS_PHY_837_DATA 0x00000000
 #define DDRSS_PHY_838_DATA 0x00000000
@@ -1732,7 +1734,7 @@
 #define DDRSS_PHY_857_DATA 0x00100010
 #define DDRSS_PHY_858_DATA 0x00100010
 #define DDRSS_PHY_859_DATA 0x00100010
-#define DDRSS_PHY_860_DATA 0x02040010
+#define DDRSS_PHY_860_DATA 0x02000010
 #define DDRSS_PHY_861_DATA 0x00000005
 #define DDRSS_PHY_862_DATA 0x51516042
 #define DDRSS_PHY_863_DATA 0x31C06000
@@ -2699,7 +2701,7 @@
 #define DDRSS_PHY_1824_DATA 0x0F0F0804
 #define DDRSS_PHY_1825_DATA 0x00800120
 #define DDRSS_PHY_1826_DATA 0x00041B42
-#define DDRSS_PHY_1827_DATA 0x00005201
+#define DDRSS_PHY_1827_DATA 0x00004201
 #define DDRSS_PHY_1828_DATA 0x00000000
 #define DDRSS_PHY_1829_DATA 0x00000000
 #define DDRSS_PHY_1830_DATA 0x00000000
@@ -2760,7 +2762,7 @@
 #define DDRSS_PHY_1885_DATA 0x00000002
 #define DDRSS_PHY_1886_DATA 0x00000000
 #define DDRSS_PHY_1887_DATA 0x00000000
-#define DDRSS_PHY_1888_DATA 0x00000AC4
+#define DDRSS_PHY_1888_DATA 0x0001F7C4
 #define DDRSS_PHY_1889_DATA 0x04000004
 #define DDRSS_PHY_1890_DATA 0x00000000
 #define DDRSS_PHY_1891_DATA 0x00001142
@@ -2789,10 +2791,10 @@
 #define DDRSS_PHY_1914_DATA 0x0089FF00
 #define DDRSS_PHY_1915_DATA 0x000C3F11
 #define DDRSS_PHY_1916_DATA 0x01990000
-#define DDRSS_PHY_1917_DATA 0x000C3F11
+#define DDRSS_PHY_1917_DATA 0x000C3F91
 #define DDRSS_PHY_1918_DATA 0x01990000
 #define DDRSS_PHY_1919_DATA 0x3F0DFF11
 #define DDRSS_PHY_1920_DATA 0x00EF0000
 #define DDRSS_PHY_1921_DATA 0x00018011
 #define DDRSS_PHY_1922_DATA 0x0089FF00
-#define DDRSS_PHY_1923_DATA 0x20040004
+#define DDRSS_PHY_1923_DATA 0x20040006
diff --git a/arch/arm/dts/k3-am62a-phycore-som-binman.dtsi b/arch/arm/dts/k3-am62a-phycore-som-binman.dtsi
index 640361e0fd1..325702ed6e0 100644
--- a/arch/arm/dts/k3-am62a-phycore-som-binman.dtsi
+++ b/arch/arm/dts/k3-am62a-phycore-som-binman.dtsi
@@ -142,7 +142,21 @@
 		};
 	};
 };
-#endif
+
+#include "k3-binman-capsule-r5.dtsi"
+
+&capsule_tiboot3 {
+	efi-capsule {
+		/*
+		 * The GUID is generated dynamically by taking a namespace UUID and hashing
+		 * it with the board compatible and fw_image name:
+		 * mkeficapsule guidgen k3-am62a7-r5-phycore-som-2gb.dtb PHYCORE_AM62AX_TIBOOT3
+		 */
+		image-guid = "07CA7DD0-85FF-597E-A485-B2423D3AE6C1";
+	};
+};
+
+#endif /* CONFIG_TARGET_PHYCORE_AM62AX_R5 */
 
 #ifdef CONFIG_TARGET_PHYCORE_AM62AX_A53
 
@@ -306,6 +320,66 @@
 					description = "U-Boot for AM62Ax board";
 				};
 
+				som-no-rtc {
+					description = "k3-am6xx-phycore-disable-rtc";
+					type = "flat_dt";
+					compression = "none";
+					load = <0x8F000000>;
+					arch = "arm";
+					ti-secure {
+						content = <&am6xx_phycore_disable_rtc_dtbo>;
+						keyfile = "custMpk.pem";
+					};
+					am6xx_phycore_disable_rtc_dtbo: blob-ext {
+						filename = "dts/upstream/src/arm64/ti/k3-am6xx-phycore-disable-rtc.dtbo";
+					};
+				};
+
+				som-no-spi {
+					description = "k3-am6xx-phycore-disable-spi-nor";
+					type = "flat_dt";
+					compression = "none";
+					load = <0x8F001000>;
+					arch = "arm";
+					ti-secure {
+						content = <&am6xx_phycore_disable_spi_not_dtbo>;
+						keyfile = "custMpk.pem";
+					};
+					am6xx_phycore_disable_spi_not_dtbo: blob-ext {
+						filename = "dts/upstream/src/arm64/ti/k3-am6xx-phycore-disable-spi-nor.dtbo";
+					};
+				};
+
+				som-no-eth {
+					description = "k3-am6xx-phycore-disable-eth-phy";
+					type = "flat_dt";
+					compression = "none";
+					load = <0x8F002000>;
+					arch = "arm";
+					ti-secure {
+						content = <&am6xx_phycore_disable_eth_phy_dtbo>;
+						keyfile = "custMpk.pem";
+					};
+					am6xx_phycore_disable_eth_phy_dtbo: blob-ext {
+						filename = "dts/upstream/src/arm64/ti/k3-am6xx-phycore-disable-eth-phy.dtbo";
+					};
+				};
+
+				som-qspi {
+					description = "k3-am6xx-phycore-qspi-nor";
+					type = "flat_dt";
+					compression = "none";
+					load = <0x8F003000>;
+					arch = "arm";
+					ti-secure {
+						content = <&am6xx_phycore_disable_qspi_nor_dtbo>;
+						keyfile = "custMpk.pem";
+					};
+					am6xx_phycore_disable_qspi_nor_dtbo: blob-ext {
+						filename = "dts/upstream/src/arm64/ti/k3-am6xx-phycore-qspi-nor.dtbo";
+					};
+				};
+
 				fdt-0 {
 					description = "k3-am62a7-phyboard-lyra-rdk";
 					type = "flat_dt";
@@ -330,7 +404,11 @@
 				conf-0 {
 					description = "k3-am62a7-phyboard-lyra-rdk";
 					firmware = "uboot";
-					loadables = "uboot";
+					loadables = "uboot",
+						    "som-no-rtc",
+						    "som-no-spi",
+						    "som-no-eth",
+						    "som-qspi";
 					fdt = "fdt-0";
 				};
 			};
@@ -451,4 +529,29 @@
 		};
 	};
 };
-#endif
+
+#include "k3-binman-capsule.dtsi"
+
+&capsule_tispl {
+	efi-capsule {
+		/*
+		 * The GUID is generated dynamically by taking a namespace UUID and hashing
+		 * it with the board compatible and fw_image name:
+		 * mkeficapsule guidgen k3-am62a7-phyboard-lyra-rdk.dtb PHYCORE_AM62AX_SPL
+		 */
+		image-guid = "14F968A2-7C3A-50AD-9356-192F07AD2A9C";
+	};
+};
+
+&capsule_uboot {
+	efi-capsule {
+		/*
+		 * The GUID is generated dynamically by taking a namespace UUID and hashing
+		 * it with the board compatible and fw_image name:
+		 * mkeficapsule guidgen k3-am62a7-phyboard-lyra-rdk.dtb PHYCORE_AM62AX_UBOOT
+		 */
+		image-guid = "1F1148C5-2785-5E7C-9C58-C5B1EC0DC80C";
+	};
+};
+
+#endif /* CONFIG_TARGET_PHYCORE_AM62AX_A53 */
diff --git a/arch/arm/dts/k3-am62a7-phyboard-lyra-rdk-u-boot.dtsi b/arch/arm/dts/k3-am62a7-phyboard-lyra-rdk-u-boot.dtsi
index 41692c8f670..5a52f3d19c0 100644
--- a/arch/arm/dts/k3-am62a7-phyboard-lyra-rdk-u-boot.dtsi
+++ b/arch/arm/dts/k3-am62a7-phyboard-lyra-rdk-u-boot.dtsi
@@ -239,6 +239,10 @@
 	bootph-all;
 };
 
+&usb0_phy_ctrl {
+	bootph-all;
+};
+
 &vcc_3v3_mmc {
 	bootph-all;
 };
diff --git a/arch/arm/dts/k3-am62a7.dtsi b/arch/arm/dts/k3-am62a7.dtsi
deleted file mode 100644
index f86a23404e6..00000000000
--- a/arch/arm/dts/k3-am62a7.dtsi
+++ /dev/null
@@ -1,104 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only OR MIT
-/*
- * Device Tree Source for AM62A7 SoC family in Quad core configuration
- *
- * TRM: https://www.ti.com/lit/zip/spruj16
- *
- * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/
- */
-
-/dts-v1/;
-
-#include "k3-am62a.dtsi"
-
-/ {
-	cpus {
-		#address-cells = <1>;
-		#size-cells = <0>;
-
-		cpu-map {
-			cluster0: cluster0 {
-				core0 {
-					cpu = <&cpu0>;
-				};
-
-				core1 {
-					cpu = <&cpu1>;
-				};
-
-				core2 {
-					cpu = <&cpu2>;
-				};
-
-				core3 {
-					cpu = <&cpu3>;
-				};
-			};
-		};
-
-		cpu0: cpu@0 {
-			compatible = "arm,cortex-a53";
-			reg = <0x000>;
-			device_type = "cpu";
-			enable-method = "psci";
-			i-cache-size = <0x8000>;
-			i-cache-line-size = <64>;
-			i-cache-sets = <256>;
-			d-cache-size = <0x8000>;
-			d-cache-line-size = <64>;
-			d-cache-sets = <128>;
-			next-level-cache = <&L2_0>;
-		};
-
-		cpu1: cpu@1 {
-			compatible = "arm,cortex-a53";
-			reg = <0x001>;
-			device_type = "cpu";
-			enable-method = "psci";
-			i-cache-size = <0x8000>;
-			i-cache-line-size = <64>;
-			i-cache-sets = <256>;
-			d-cache-size = <0x8000>;
-			d-cache-line-size = <64>;
-			d-cache-sets = <128>;
-			next-level-cache = <&L2_0>;
-		};
-
-		cpu2: cpu@2 {
-			compatible = "arm,cortex-a53";
-			reg = <0x002>;
-			device_type = "cpu";
-			enable-method = "psci";
-			i-cache-size = <0x8000>;
-			i-cache-line-size = <64>;
-			i-cache-sets = <256>;
-			d-cache-size = <0x8000>;
-			d-cache-line-size = <64>;
-			d-cache-sets = <128>;
-			next-level-cache = <&L2_0>;
-		};
-
-		cpu3: cpu@3 {
-			compatible = "arm,cortex-a53";
-			reg = <0x003>;
-			device_type = "cpu";
-			enable-method = "psci";
-			i-cache-size = <0x8000>;
-			i-cache-line-size = <64>;
-			i-cache-sets = <256>;
-			d-cache-size = <0x8000>;
-			d-cache-line-size = <64>;
-			d-cache-sets = <128>;
-			next-level-cache = <&L2_0>;
-		};
-	};
-
-	L2_0: l2-cache0 {
-		compatible = "cache";
-		cache-unified;
-		cache-level = <2>;
-		cache-size = <0x80000>;
-		cache-line-size = <64>;
-		cache-sets = <512>;
-	};
-};
diff --git a/arch/arm/dts/k3-am62p-ddr-lp4-50-1600.dtsi b/arch/arm/dts/k3-am62p-ddr-lp4-50-1600.dtsi
index f6643520153..c7e33ba50b9 100644
--- a/arch/arm/dts/k3-am62p-ddr-lp4-50-1600.dtsi
+++ b/arch/arm/dts/k3-am62p-ddr-lp4-50-1600.dtsi
@@ -1,8 +1,8 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
  * This file was generated with the
- * AM62Px SysConfig DDR Subsystem Register Configuration Tool v0.10.02
- * Thu Jan 25 2024 10:43:46 GMT-0600 (Central Standard Time)
+ * AM62Px SysConfig DDR Configuration Tool for AM64x, AM625, AM623, AM62Ax, AM62Px v0.10.02
+ * Tue Sep 17 2024 11:03:07 GMT+0530 (India Standard Time)
  * DDR Type: LPDDR4
  * F0 = 50MHz    F1 = NA     F2 = 1600MHz
  * Density (per channel): 16Gb
@@ -941,7 +941,7 @@
 #define DDRSS_PHY_64_DATA 0x00000000
 #define DDRSS_PHY_65_DATA 0x00000000
 #define DDRSS_PHY_66_DATA 0x00000000
-#define DDRSS_PHY_67_DATA 0x00000004
+#define DDRSS_PHY_67_DATA 0x00000104
 #define DDRSS_PHY_68_DATA 0x00000000
 #define DDRSS_PHY_69_DATA 0x00000000
 #define DDRSS_PHY_70_DATA 0x00000000
@@ -1197,7 +1197,7 @@
 #define DDRSS_PHY_320_DATA 0x00000000
 #define DDRSS_PHY_321_DATA 0x00000000
 #define DDRSS_PHY_322_DATA 0x00000000
-#define DDRSS_PHY_323_DATA 0x00000004
+#define DDRSS_PHY_323_DATA 0x00000104
 #define DDRSS_PHY_324_DATA 0x00000000
 #define DDRSS_PHY_325_DATA 0x00000000
 #define DDRSS_PHY_326_DATA 0x00000000
@@ -1453,7 +1453,7 @@
 #define DDRSS_PHY_576_DATA 0x00000000
 #define DDRSS_PHY_577_DATA 0x00000000
 #define DDRSS_PHY_578_DATA 0x00000000
-#define DDRSS_PHY_579_DATA 0x00000004
+#define DDRSS_PHY_579_DATA 0x00000104
 #define DDRSS_PHY_580_DATA 0x00000000
 #define DDRSS_PHY_581_DATA 0x00000000
 #define DDRSS_PHY_582_DATA 0x00000000
@@ -1709,7 +1709,7 @@
 #define DDRSS_PHY_832_DATA 0x00000000
 #define DDRSS_PHY_833_DATA 0x00000000
 #define DDRSS_PHY_834_DATA 0x00000000
-#define DDRSS_PHY_835_DATA 0x00000004
+#define DDRSS_PHY_835_DATA 0x00000104
 #define DDRSS_PHY_836_DATA 0x00000000
 #define DDRSS_PHY_837_DATA 0x00000000
 #define DDRSS_PHY_838_DATA 0x00000000
diff --git a/arch/arm/dts/k3-am62x-sk-ddr4-1600MTs.dtsi b/arch/arm/dts/k3-am62x-sk-ddr4-1600MTs.dtsi
index d92e3ce048b..8def52b07f4 100644
--- a/arch/arm/dts/k3-am62x-sk-ddr4-1600MTs.dtsi
+++ b/arch/arm/dts/k3-am62x-sk-ddr4-1600MTs.dtsi
@@ -1,8 +1,8 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
  * This file was generated with the
- * AM62x SysConfig DDR Subsystem Register Configuration Tool v0.08.60
- * Wed Mar 16 2022 17:41:20 GMT-0500 (Central Daylight Time)
+ * AM623/AM625 SysConfig DDR Configuration Tool for AM64x, AM625, AM623, AM62Ax, AM62Px v0.10.02
+ * Tue Sep 17 2024 11:00:17 GMT+0530 (India Standard Time)
  * DDR Type: DDR4
  * Frequency = 800MHz (1600MTs)
  * Density: 16Gb
@@ -12,6 +12,8 @@
 #define DDRSS_PLL_FHS_CNT 6
 #define DDRSS_PLL_FREQUENCY_1 400000000
 #define DDRSS_PLL_FREQUENCY_2 400000000
+#define DDRSS_SDRAM_IDX 15
+#define DDRSS_REGION_IDX 17
 
 #define DDRSS_CTL_0_DATA 0x00000A00
 #define DDRSS_CTL_1_DATA 0x00000000
@@ -334,7 +336,7 @@
 #define DDRSS_CTL_318_DATA 0x3FFF0000
 #define DDRSS_CTL_319_DATA 0x000FFF00
 #define DDRSS_CTL_320_DATA 0xFFFFFFFF
-#define DDRSS_CTL_321_DATA 0x000FFF00
+#define DDRSS_CTL_321_DATA 0x00FFFF00
 #define DDRSS_CTL_322_DATA 0x0A000000
 #define DDRSS_CTL_323_DATA 0x0001FFFF
 #define DDRSS_CTL_324_DATA 0x01010101
@@ -901,7 +903,7 @@
 #define DDRSS_PHY_117_DATA 0x00800080
 #define DDRSS_PHY_118_DATA 0x00800080
 #define DDRSS_PHY_119_DATA 0x01000080
-#define DDRSS_PHY_120_DATA 0x01A00000
+#define DDRSS_PHY_120_DATA 0x01000000
 #define DDRSS_PHY_121_DATA 0x00000000
 #define DDRSS_PHY_122_DATA 0x00000000
 #define DDRSS_PHY_123_DATA 0x00080200
@@ -1157,7 +1159,7 @@
 #define DDRSS_PHY_373_DATA 0x00800080
 #define DDRSS_PHY_374_DATA 0x00800080
 #define DDRSS_PHY_375_DATA 0x01000080
-#define DDRSS_PHY_376_DATA 0x01A00000
+#define DDRSS_PHY_376_DATA 0x01000000
 #define DDRSS_PHY_377_DATA 0x00000000
 #define DDRSS_PHY_378_DATA 0x00000000
 #define DDRSS_PHY_379_DATA 0x00080200
@@ -2152,7 +2154,7 @@
 #define DDRSS_PHY_1368_DATA 0x00000002
 #define DDRSS_PHY_1369_DATA 0x00000100
 #define DDRSS_PHY_1370_DATA 0x00000000
-#define DDRSS_PHY_1371_DATA 0x0001F7C0
+#define DDRSS_PHY_1371_DATA 0x0001F7C2
 #define DDRSS_PHY_1372_DATA 0x00020002
 #define DDRSS_PHY_1373_DATA 0x00000000
 #define DDRSS_PHY_1374_DATA 0x00001142
diff --git a/arch/arm/dts/k3-am64-evm-ddr4-1600MTs.dtsi b/arch/arm/dts/k3-am64-evm-ddr4-1600MTs.dtsi
index 491412119b1..1b5fabc3dd1 100644
--- a/arch/arm/dts/k3-am64-evm-ddr4-1600MTs.dtsi
+++ b/arch/arm/dts/k3-am64-evm-ddr4-1600MTs.dtsi
@@ -1,8 +1,8 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
  * This file was generated with the
- * AM64x SysConfig DDR Subsystem Register Configuration Tool v0.08.40
- * Wed Feb 02 2022 16:24:50 GMT-0600 (Central Standard Time)
+ * AM64x SysConfig DDR Configuration Tool for AM64x, AM625, AM623, AM62Ax, AM62Px v0.10.02
+ * Tue Sep 17 2024 11:01:31 GMT+0530 (India Standard Time)
  * DDR Type: DDR4
  * Frequency = 800MHz (1600MTs)
  * Density: 16Gb
@@ -12,6 +12,8 @@
 #define DDRSS_PLL_FHS_CNT 6
 #define DDRSS_PLL_FREQUENCY_1 400000000
 #define DDRSS_PLL_FREQUENCY_2 400000000
+#define DDRSS_SDRAM_IDX 15
+#define DDRSS_REGION_IDX 15
 
 #define DDRSS_CTL_0_DATA 0x00000A00
 #define DDRSS_CTL_1_DATA 0x00000000
@@ -178,7 +180,7 @@
 #define DDRSS_CTL_162_DATA 0x0E0A0907
 #define DDRSS_CTL_163_DATA 0x0A090000
 #define DDRSS_CTL_164_DATA 0x0A090701
-#define DDRSS_CTL_165_DATA 0x0000000E
+#define DDRSS_CTL_165_DATA 0x0000080E
 #define DDRSS_CTL_166_DATA 0x00040003
 #define DDRSS_CTL_167_DATA 0x00000007
 #define DDRSS_CTL_168_DATA 0x00000000
@@ -334,7 +336,7 @@
 #define DDRSS_CTL_318_DATA 0x3FFF0000
 #define DDRSS_CTL_319_DATA 0x000FFF00
 #define DDRSS_CTL_320_DATA 0xFFFFFFFF
-#define DDRSS_CTL_321_DATA 0x000FFF00
+#define DDRSS_CTL_321_DATA 0x00FFFF00
 #define DDRSS_CTL_322_DATA 0x0A000000
 #define DDRSS_CTL_323_DATA 0x0001FFFF
 #define DDRSS_CTL_324_DATA 0x01010101
@@ -901,7 +903,7 @@
 #define DDRSS_PHY_117_DATA 0x00800080
 #define DDRSS_PHY_118_DATA 0x00800080
 #define DDRSS_PHY_119_DATA 0x01000080
-#define DDRSS_PHY_120_DATA 0x01A00000
+#define DDRSS_PHY_120_DATA 0x01000000
 #define DDRSS_PHY_121_DATA 0x00000000
 #define DDRSS_PHY_122_DATA 0x00000000
 #define DDRSS_PHY_123_DATA 0x00080200
@@ -1157,7 +1159,7 @@
 #define DDRSS_PHY_373_DATA 0x00800080
 #define DDRSS_PHY_374_DATA 0x00800080
 #define DDRSS_PHY_375_DATA 0x01000080
-#define DDRSS_PHY_376_DATA 0x01A00000
+#define DDRSS_PHY_376_DATA 0x01000000
 #define DDRSS_PHY_377_DATA 0x00000000
 #define DDRSS_PHY_378_DATA 0x00000000
 #define DDRSS_PHY_379_DATA 0x00080200
@@ -2152,7 +2154,7 @@
 #define DDRSS_PHY_1368_DATA 0x00000002
 #define DDRSS_PHY_1369_DATA 0x00000100
 #define DDRSS_PHY_1370_DATA 0x00000000
-#define DDRSS_PHY_1371_DATA 0x0001F7C0
+#define DDRSS_PHY_1371_DATA 0x0001F7C2
 #define DDRSS_PHY_1372_DATA 0x00020002
 #define DDRSS_PHY_1373_DATA 0x00000000
 #define DDRSS_PHY_1374_DATA 0x00001142
diff --git a/arch/arm/dts/k3-am65-iot2050-common-u-boot.dtsi b/arch/arm/dts/k3-am65-iot2050-common-u-boot.dtsi
index b6d2c816acc..55337179f9f 100644
--- a/arch/arm/dts/k3-am65-iot2050-common-u-boot.dtsi
+++ b/arch/arm/dts/k3-am65-iot2050-common-u-boot.dtsi
@@ -14,6 +14,24 @@
 		spi0 = &ospi0;
 	};
 
+	sysinfo {
+		compatible = "siemens,sysinfo-iot2050";
+		/* TI_SRAM_SCRATCH_BOARD_EEPROM_START */
+		offset = <0x40280000>;
+		bootph-all;
+
+		smbios {
+			system {
+				manufacturer = "SIEMENS AG";
+				product = "SIMATIC IOT2050";
+			};
+
+			baseboard {
+				manufacturer = "SIEMENS AG";
+			};
+		};
+	};
+
 	leds {
 		bootph-all;
 		status-led-red {
diff --git a/arch/arm/dts/k3-am67a-beagley-ai-u-boot.dtsi b/arch/arm/dts/k3-am67a-beagley-ai-u-boot.dtsi
new file mode 100644
index 00000000000..6c52038cdca
--- /dev/null
+++ b/arch/arm/dts/k3-am67a-beagley-ai-u-boot.dtsi
@@ -0,0 +1,270 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Common AM67A BeagleY-AI dts file for SPLs
+ *
+ * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2024 Robert Nelson, BeagleBoard.org Foundation
+ */
+
+#include "k3-binman.dtsi"
+
+/ {
+	chosen {
+		stdout-path = "serial2:115200n8";
+		tick-timer = &main_timer0;
+	};
+};
+
+&main_pktdma {
+	reg = <0x00 0x485c0000 0x00 0x100>,
+	      <0x00 0x4a800000 0x00 0x20000>,
+	      <0x00 0x4aa00000 0x00 0x40000>,
+	      <0x00 0x4b800000 0x00 0x400000>,
+	      <0x00 0x485e0000 0x00 0x20000>,
+	      <0x00 0x484a0000 0x00 0x4000>,
+	      <0x00 0x484c0000 0x00 0x2000>,
+	      <0x00 0x48430000 0x00 0x4000>;
+	reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt",
+		    "cfg", "tchan", "rchan", "rflow";
+};
+
+&dmsc {
+	bootph-pre-ram;
+	k3_sysreset: sysreset-controller {
+		compatible = "ti,sci-sysreset";
+		bootph-pre-ram;
+	};
+};
+
+&usbss0 {
+	bootph-pre-ram;
+};
+
+&usb0 {
+	dr_mode = "peripheral";
+	bootph-pre-ram;
+};
+
+&usbss1 {
+	status = "disabled";
+};
+
+&usb1 {
+	status = "disabled";
+};
+
+#if IS_ENABLED(CONFIG_TARGET_J722S_R5_BEAGLEY_AI)
+
+&binman {
+	tiboot3-j722s-hs-evm.bin {
+		filename = "tiboot3-j722s-hs-evm.bin";
+		ti-secure-rom {
+			content = <&u_boot_spl>, <&ti_fs_enc>, <&combined_tifs_cfg>,
+				  <&combined_dm_cfg>, <&sysfw_inner_cert>;
+			combined;
+			dm-data;
+			sysfw-inner-cert;
+			keyfile = "custMpk.pem";
+			sw-rev = <1>;
+			content-sbl = <&u_boot_spl>;
+			content-sysfw = <&ti_fs_enc>;
+			content-sysfw-data = <&combined_tifs_cfg>;
+			content-sysfw-inner-cert = <&sysfw_inner_cert>;
+			content-dm-data = <&combined_dm_cfg>;
+			load = <0x43c00000>;
+			load-sysfw = <0x40000>;
+			load-sysfw-data = <0x67000>;
+			load-dm-data = <0x43c7a800>;
+		};
+
+		u_boot_spl: u-boot-spl {
+			no-expanded;
+		};
+
+		ti_fs_enc: ti-fs-enc.bin {
+			filename = "ti-sysfw/ti-fs-firmware-j722s-hs-enc.bin";
+			type = "blob-ext";
+			optional;
+		};
+
+		combined_tifs_cfg: combined-tifs-cfg.bin {
+			filename = "combined-tifs-cfg.bin";
+			type = "blob-ext";
+		};
+
+		sysfw_inner_cert: sysfw-inner-cert {
+			filename = "ti-sysfw/ti-fs-firmware-j722s-hs-cert.bin";
+			type = "blob-ext";
+			optional;
+		};
+
+		combined_dm_cfg: combined-dm-cfg.bin {
+			filename = "combined-dm-cfg.bin";
+			type = "blob-ext";
+		};
+	};
+};
+
+&binman {
+	tiboot3-j722s-hs-fs-evm.bin {
+		filename = "tiboot3-j722s-hs-fs-evm.bin";
+		symlink = "tiboot3.bin";
+
+		ti-secure-rom {
+			content = <&u_boot_spl_fs>, <&ti_fs_enc_fs>, <&combined_tifs_cfg_fs>,
+				  <&combined_dm_cfg_fs>, <&sysfw_inner_cert_fs>;
+			combined;
+			dm-data;
+			sysfw-inner-cert;
+			keyfile = "custMpk.pem";
+			sw-rev = <1>;
+			content-sbl = <&u_boot_spl_fs>;
+			content-sysfw = <&ti_fs_enc_fs>;
+			content-sysfw-data = <&combined_tifs_cfg_fs>;
+			content-sysfw-inner-cert = <&sysfw_inner_cert_fs>;
+			content-dm-data = <&combined_dm_cfg_fs>;
+			load = <0x43c00000>;
+			load-sysfw = <0x40000>;
+			load-sysfw-data = <0x67000>;
+			load-dm-data = <0x43c7a800>;
+		};
+
+		u_boot_spl_fs: u-boot-spl {
+			no-expanded;
+		};
+
+		ti_fs_enc_fs: ti-fs-enc.bin {
+			filename = "ti-sysfw/ti-fs-firmware-j722s-hs-fs-enc.bin";
+			type = "blob-ext";
+			optional;
+		};
+
+		combined_tifs_cfg_fs: combined-tifs-cfg.bin {
+			filename = "combined-tifs-cfg.bin";
+			type = "blob-ext";
+		};
+
+		sysfw_inner_cert_fs: sysfw-inner-cert {
+			filename = "ti-sysfw/ti-fs-firmware-j722s-hs-fs-cert.bin";
+			type = "blob-ext";
+			optional;
+		};
+
+		combined_dm_cfg_fs: combined-dm-cfg.bin {
+			filename = "combined-dm-cfg.bin";
+			type = "blob-ext";
+		};
+	};
+};
+#endif /* CONFIG_TARGET_J722S_R5_BEAGLEY_AI */
+
+#if IS_ENABLED(CONFIG_TARGET_J722S_A53_BEAGLEY_AI)
+
+#define SPL_BEAGLEY_AI_DTB "spl/dts/ti/k3-am67a-beagley-ai.dtb"
+#define BEAGLEY_AI_DTB "u-boot.dtb"
+
+&binman {
+	ti-dm {
+		filename = "ti-dm.bin";
+
+		blob-ext {
+			filename = "ti-dm/j722s/ipc_echo_testb_mcu1_0_release_strip.xer5f";
+			optional;
+		};
+	};
+
+	ti-spl {
+		insert-template = <&ti_spl_template>;
+
+		fit {
+			images {
+				dm {
+					ti-secure {
+						content = <&dm>;
+						keyfile = "custMpk.pem";
+					};
+
+					dm: ti-dm {
+						filename = "ti-dm.bin";
+					};
+				};
+
+				fdt-0 {
+					description = "k3-am67a-beagley-ai";
+					type = "flat_dt";
+					arch = "arm";
+					compression = "none";
+
+					ti-secure {
+						content = <&spl_beagley_ai_dtb>;
+						keyfile = "custMpk.pem";
+					};
+
+					spl_beagley_ai_dtb: blob-ext {
+						filename = "spl/dts/ti/k3-am67a-beagley-ai.dtb";
+					};
+
+				};
+
+			};
+
+			configurations {
+				default = "conf-0";
+
+				conf-0 {
+					description = "k3-am67a-beagley-ai";
+					firmware = "atf";
+					loadables = "tee", "dm", "spl";
+					fdt = "fdt-0";
+				};
+			};
+		};
+	};
+};
+
+&binman {
+	u-boot {
+		insert-template = <&u_boot_template>;
+
+		fit {
+			images {
+				uboot {
+					description = "U-Boot for BeagleY-AI";
+				};
+
+				fdt-0 {
+					description = "k3-am67a-beagley-ai";
+					type = "flat_dt";
+					arch = "arm";
+					compression = "none";
+
+					ti-secure {
+						content = <&beagley_ai_dtb>;
+						keyfile = "custMpk.pem";
+					};
+
+					beagley_ai_dtb: blob-ext {
+						filename = "u-boot.dtb";
+					};
+
+					hash {
+						algo = "crc32";
+					};
+				};
+			};
+
+			configurations {
+				default = "conf-0";
+
+				conf-0 {
+					description = "k3-k3-am67a-beagley-ai";
+					firmware = "uboot";
+					loadables = "uboot";
+					fdt = "fdt-0";
+				};
+
+			};
+		};
+	};
+};
+#endif /* CONFIG_TARGET_J722S_A53_BEAGLEY_AI */
diff --git a/arch/arm/dts/k3-am67a-beagley-ddr-lp4.dtsi b/arch/arm/dts/k3-am67a-beagley-ddr-lp4.dtsi
new file mode 100644
index 00000000000..6949a3a0f07
--- /dev/null
+++ b/arch/arm/dts/k3-am67a-beagley-ddr-lp4.dtsi
@@ -0,0 +1,2801 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * DDR Configuration file
+ * DDR: Kingston_B3221PM3BDGUI-U
+ *
+ * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2024 Robert Nelson, BeagleBoard.org Foundation
+ *
+ * This file was generated with the Jacinto7_DDRSS_RegConfigTool, Revision: J722S - v0.0.1
+ * This file was generated on Tue Mar 12 2024 14:14:02 GMT+0800
+*/
+
+
+#define DDRSS_PLL_FHS_CNT 3
+#define DDRSS_PLL_FREQUENCY_0 25000000
+#define DDRSS_PLL_FREQUENCY_1 933000000
+#define DDRSS_PLL_FREQUENCY_2 933000000
+
+#define DDRSS_CTL_0_DATA 0x00000B00
+#define DDRSS_CTL_1_DATA 0x00000000
+#define DDRSS_CTL_2_DATA 0x00000000
+#define DDRSS_CTL_3_DATA 0x00000000
+#define DDRSS_CTL_4_DATA 0x00000000
+#define DDRSS_CTL_5_DATA 0x00000000
+#define DDRSS_CTL_6_DATA 0x00000000
+#define DDRSS_CTL_7_DATA 0x00002710
+#define DDRSS_CTL_8_DATA 0x000186A0
+#define DDRSS_CTL_9_DATA 0x00000005
+#define DDRSS_CTL_10_DATA 0x00000064
+#define DDRSS_CTL_11_DATA 0x0005B18F
+#define DDRSS_CTL_12_DATA 0x0038EF90
+#define DDRSS_CTL_13_DATA 0x00000005
+#define DDRSS_CTL_14_DATA 0x00000E94
+#define DDRSS_CTL_15_DATA 0x0005B18F
+#define DDRSS_CTL_16_DATA 0x0038EF90
+#define DDRSS_CTL_17_DATA 0x00000005
+#define DDRSS_CTL_18_DATA 0x00000E94
+#define DDRSS_CTL_19_DATA 0x01010100
+#define DDRSS_CTL_20_DATA 0x01010100
+#define DDRSS_CTL_21_DATA 0x01000110
+#define DDRSS_CTL_22_DATA 0x02010002
+#define DDRSS_CTL_23_DATA 0x0000000A
+#define DDRSS_CTL_24_DATA 0x000186A0
+#define DDRSS_CTL_25_DATA 0x00000000
+#define DDRSS_CTL_26_DATA 0x00000000
+#define DDRSS_CTL_27_DATA 0x00000000
+#define DDRSS_CTL_28_DATA 0x00000000
+#define DDRSS_CTL_29_DATA 0x00020200
+#define DDRSS_CTL_30_DATA 0x00000000
+#define DDRSS_CTL_31_DATA 0x00000000
+#define DDRSS_CTL_32_DATA 0x00000000
+#define DDRSS_CTL_33_DATA 0x00000000
+#define DDRSS_CTL_34_DATA 0x08000010
+#define DDRSS_CTL_35_DATA 0x00004B4B
+#define DDRSS_CTL_36_DATA 0x00000000
+#define DDRSS_CTL_37_DATA 0x00000000
+#define DDRSS_CTL_38_DATA 0x00000000
+#define DDRSS_CTL_39_DATA 0x00000000
+#define DDRSS_CTL_40_DATA 0x0000040C
+#define DDRSS_CTL_41_DATA 0x00000000
+#define DDRSS_CTL_42_DATA 0x00001040
+#define DDRSS_CTL_43_DATA 0x00000000
+#define DDRSS_CTL_44_DATA 0x00001040
+#define DDRSS_CTL_45_DATA 0x00000000
+#define DDRSS_CTL_46_DATA 0x05000804
+#define DDRSS_CTL_47_DATA 0x00000800
+#define DDRSS_CTL_48_DATA 0x09090004
+#define DDRSS_CTL_49_DATA 0x00000204
+#define DDRSS_CTL_50_DATA 0x007A0012
+#define DDRSS_CTL_51_DATA 0x09140054
+#define DDRSS_CTL_52_DATA 0x00003A26
+#define DDRSS_CTL_53_DATA 0x007A0012
+#define DDRSS_CTL_54_DATA 0x09140054
+#define DDRSS_CTL_55_DATA 0x09003A26
+#define DDRSS_CTL_56_DATA 0x000A0A09
+#define DDRSS_CTL_57_DATA 0x0400036D
+#define DDRSS_CTL_58_DATA 0x090F2005
+#define DDRSS_CTL_59_DATA 0x00001B13
+#define DDRSS_CTL_60_DATA 0x0E007FE6
+#define DDRSS_CTL_61_DATA 0x090F200F
+#define DDRSS_CTL_62_DATA 0x00001B13
+#define DDRSS_CTL_63_DATA 0x0E007FE6
+#define DDRSS_CTL_64_DATA 0x0304200F
+#define DDRSS_CTL_65_DATA 0x04050002
+#define DDRSS_CTL_66_DATA 0x24262426
+#define DDRSS_CTL_67_DATA 0x01010008
+#define DDRSS_CTL_68_DATA 0x044A4A08
+#define DDRSS_CTL_69_DATA 0x042B2B04
+#define DDRSS_CTL_70_DATA 0x00002B2B
+#define DDRSS_CTL_71_DATA 0x00000101
+#define DDRSS_CTL_72_DATA 0x00000000
+#define DDRSS_CTL_73_DATA 0x01000000
+#define DDRSS_CTL_74_DATA 0x00130803
+#define DDRSS_CTL_75_DATA 0x00000059
+#define DDRSS_CTL_76_DATA 0x000002C5
+#define DDRSS_CTL_77_DATA 0x00000E2E
+#define DDRSS_CTL_78_DATA 0x000002C5
+#define DDRSS_CTL_79_DATA 0x00000E2E
+#define DDRSS_CTL_80_DATA 0x00000005
+#define DDRSS_CTL_81_DATA 0x0000000A
+#define DDRSS_CTL_82_DATA 0x00000010
+#define DDRSS_CTL_83_DATA 0x00000163
+#define DDRSS_CTL_84_DATA 0x00000386
+#define DDRSS_CTL_85_DATA 0x00000163
+#define DDRSS_CTL_86_DATA 0x00000386
+#define DDRSS_CTL_87_DATA 0x03004000
+#define DDRSS_CTL_88_DATA 0x00001201
+#define DDRSS_CTL_89_DATA 0x000E0005
+#define DDRSS_CTL_90_DATA 0x2908000E
+#define DDRSS_CTL_91_DATA 0x0A050529
+#define DDRSS_CTL_92_DATA 0x1B0E0A03
+#define DDRSS_CTL_93_DATA 0x1B0E0A04
+#define DDRSS_CTL_94_DATA 0x04010104
+#define DDRSS_CTL_95_DATA 0x00010401
+#define DDRSS_CTL_96_DATA 0x00140014
+#define DDRSS_CTL_97_DATA 0x02D302D3
+#define DDRSS_CTL_98_DATA 0x02D302D3
+#define DDRSS_CTL_99_DATA 0x00000000
+#define DDRSS_CTL_100_DATA 0x03030000
+#define DDRSS_CTL_101_DATA 0x05050501
+#define DDRSS_CTL_102_DATA 0x04041C04
+#define DDRSS_CTL_103_DATA 0x0E0A0E0A
+#define DDRSS_CTL_104_DATA 0x0A04041C
+#define DDRSS_CTL_105_DATA 0x030E0A0E
+#define DDRSS_CTL_106_DATA 0x00000404
+#define DDRSS_CTL_107_DATA 0x00000301
+#define DDRSS_CTL_108_DATA 0x00000001
+#define DDRSS_CTL_109_DATA 0x00000000
+#define DDRSS_CTL_110_DATA 0x40020100
+#define DDRSS_CTL_111_DATA 0x00038010
+#define DDRSS_CTL_112_DATA 0x00050004
+#define DDRSS_CTL_113_DATA 0x00000004
+#define DDRSS_CTL_114_DATA 0x00040003
+#define DDRSS_CTL_115_DATA 0x00040005
+#define DDRSS_CTL_116_DATA 0x00030000
+#define DDRSS_CTL_117_DATA 0x00050004
+#define DDRSS_CTL_118_DATA 0x00000004
+#define DDRSS_CTL_119_DATA 0x00001640
+#define DDRSS_CTL_120_DATA 0x00001640
+#define DDRSS_CTL_121_DATA 0x00001640
+#define DDRSS_CTL_122_DATA 0x00001640
+#define DDRSS_CTL_123_DATA 0x00001640
+#define DDRSS_CTL_124_DATA 0x00000000
+#define DDRSS_CTL_125_DATA 0x0000026F
+#define DDRSS_CTL_126_DATA 0x00038B80
+#define DDRSS_CTL_127_DATA 0x00038B80
+#define DDRSS_CTL_128_DATA 0x00038B80
+#define DDRSS_CTL_129_DATA 0x00038B80
+#define DDRSS_CTL_130_DATA 0x00038B80
+#define DDRSS_CTL_131_DATA 0x00000000
+#define DDRSS_CTL_132_DATA 0x00006342
+#define DDRSS_CTL_133_DATA 0x00038B80
+#define DDRSS_CTL_134_DATA 0x00038B80
+#define DDRSS_CTL_135_DATA 0x00038B80
+#define DDRSS_CTL_136_DATA 0x00038B80
+#define DDRSS_CTL_137_DATA 0x00038B80
+#define DDRSS_CTL_138_DATA 0x00000000
+#define DDRSS_CTL_139_DATA 0x00006342
+#define DDRSS_CTL_140_DATA 0x00000000
+#define DDRSS_CTL_141_DATA 0x00000000
+#define DDRSS_CTL_142_DATA 0x00000000
+#define DDRSS_CTL_143_DATA 0x00000000
+#define DDRSS_CTL_144_DATA 0x00000000
+#define DDRSS_CTL_145_DATA 0x00000000
+#define DDRSS_CTL_146_DATA 0x00000000
+#define DDRSS_CTL_147_DATA 0x00000000
+#define DDRSS_CTL_148_DATA 0x00000000
+#define DDRSS_CTL_149_DATA 0x00000000
+#define DDRSS_CTL_150_DATA 0x00000000
+#define DDRSS_CTL_151_DATA 0x00000000
+#define DDRSS_CTL_152_DATA 0x00000000
+#define DDRSS_CTL_153_DATA 0x00000000
+#define DDRSS_CTL_154_DATA 0x00000000
+#define DDRSS_CTL_155_DATA 0x00000000
+#define DDRSS_CTL_156_DATA 0x00000000
+#define DDRSS_CTL_157_DATA 0x00000000
+#define DDRSS_CTL_158_DATA 0x03050000
+#define DDRSS_CTL_159_DATA 0x040A040A
+#define DDRSS_CTL_160_DATA 0x00000000
+#define DDRSS_CTL_161_DATA 0x07010A09
+#define DDRSS_CTL_162_DATA 0x000E0A09
+#define DDRSS_CTL_163_DATA 0x010A0900
+#define DDRSS_CTL_164_DATA 0x0E0A0907
+#define DDRSS_CTL_165_DATA 0x0A090000
+#define DDRSS_CTL_166_DATA 0x0A090701
+#define DDRSS_CTL_167_DATA 0x0000000E
+#define DDRSS_CTL_168_DATA 0x00040003
+#define DDRSS_CTL_169_DATA 0x00000007
+#define DDRSS_CTL_170_DATA 0x00000000
+#define DDRSS_CTL_171_DATA 0x00000000
+#define DDRSS_CTL_172_DATA 0x00000000
+#define DDRSS_CTL_173_DATA 0x00000000
+#define DDRSS_CTL_174_DATA 0x00000000
+#define DDRSS_CTL_175_DATA 0x00000000
+#define DDRSS_CTL_176_DATA 0x01000000
+#define DDRSS_CTL_177_DATA 0x00000000
+#define DDRSS_CTL_178_DATA 0x00001700
+#define DDRSS_CTL_179_DATA 0x0000100E
+#define DDRSS_CTL_180_DATA 0x00000002
+#define DDRSS_CTL_181_DATA 0x00000000
+#define DDRSS_CTL_182_DATA 0x00000001
+#define DDRSS_CTL_183_DATA 0x00000002
+#define DDRSS_CTL_184_DATA 0x00000C00
+#define DDRSS_CTL_185_DATA 0x00008000
+#define DDRSS_CTL_186_DATA 0x00000C00
+#define DDRSS_CTL_187_DATA 0x00008000
+#define DDRSS_CTL_188_DATA 0x00000C00
+#define DDRSS_CTL_189_DATA 0x00008000
+#define DDRSS_CTL_190_DATA 0x00000000
+#define DDRSS_CTL_191_DATA 0x00000000
+#define DDRSS_CTL_192_DATA 0x00000000
+#define DDRSS_CTL_193_DATA 0x00000000
+#define DDRSS_CTL_194_DATA 0x00000000
+#define DDRSS_CTL_195_DATA 0x0005000A
+#define DDRSS_CTL_196_DATA 0x0404000D
+#define DDRSS_CTL_197_DATA 0x0000000D
+#define DDRSS_CTL_198_DATA 0x00BB0176
+#define DDRSS_CTL_199_DATA 0x0E0E01D3
+#define DDRSS_CTL_200_DATA 0x000001D3
+#define DDRSS_CTL_201_DATA 0x00BB0176
+#define DDRSS_CTL_202_DATA 0x0E0E01D3
+#define DDRSS_CTL_203_DATA 0x000001D3
+#define DDRSS_CTL_204_DATA 0x00000000
+#define DDRSS_CTL_205_DATA 0x00000000
+#define DDRSS_CTL_206_DATA 0x00000000
+#define DDRSS_CTL_207_DATA 0x00000000
+#define DDRSS_CTL_208_DATA 0x00000084
+#define DDRSS_CTL_209_DATA 0x00000000
+#define DDRSS_CTL_210_DATA 0x00000000
+#define DDRSS_CTL_211_DATA 0x000000E4
+#define DDRSS_CTL_212_DATA 0x00000036
+#define DDRSS_CTL_213_DATA 0x00000000
+#define DDRSS_CTL_214_DATA 0x000000E4
+#define DDRSS_CTL_215_DATA 0x00000036
+#define DDRSS_CTL_216_DATA 0x00000000
+#define DDRSS_CTL_217_DATA 0x00000084
+#define DDRSS_CTL_218_DATA 0x00000000
+#define DDRSS_CTL_219_DATA 0x00000000
+#define DDRSS_CTL_220_DATA 0x000000E4
+#define DDRSS_CTL_221_DATA 0x00000036
+#define DDRSS_CTL_222_DATA 0x00000000
+#define DDRSS_CTL_223_DATA 0x000000E4
+#define DDRSS_CTL_224_DATA 0x00000036
+#define DDRSS_CTL_225_DATA 0x00000000
+#define DDRSS_CTL_226_DATA 0x00000000
+#define DDRSS_CTL_227_DATA 0x00000033
+#define DDRSS_CTL_228_DATA 0x00000033
+#define DDRSS_CTL_229_DATA 0x00000033
+#define DDRSS_CTL_230_DATA 0x00000033
+#define DDRSS_CTL_231_DATA 0x00000033
+#define DDRSS_CTL_232_DATA 0x00000033
+#define DDRSS_CTL_233_DATA 0x00000000
+#define DDRSS_CTL_234_DATA 0x00000000
+#define DDRSS_CTL_235_DATA 0x00000000
+#define DDRSS_CTL_236_DATA 0x00000000
+#define DDRSS_CTL_237_DATA 0x00000000
+#define DDRSS_CTL_238_DATA 0x00000000
+#define DDRSS_CTL_239_DATA 0x00000000
+#define DDRSS_CTL_240_DATA 0x00000000
+#define DDRSS_CTL_241_DATA 0x00000000
+#define DDRSS_CTL_242_DATA 0x00000000
+#define DDRSS_CTL_243_DATA 0x00000000
+#define DDRSS_CTL_244_DATA 0x00000000
+#define DDRSS_CTL_245_DATA 0x00000000
+#define DDRSS_CTL_246_DATA 0x00000000
+#define DDRSS_CTL_247_DATA 0x00000000
+#define DDRSS_CTL_248_DATA 0x00000000
+#define DDRSS_CTL_249_DATA 0x00000000
+#define DDRSS_CTL_250_DATA 0x00000000
+#define DDRSS_CTL_251_DATA 0x00000000
+#define DDRSS_CTL_252_DATA 0x00000000
+#define DDRSS_CTL_253_DATA 0x00000000
+#define DDRSS_CTL_254_DATA 0x00000000
+#define DDRSS_CTL_255_DATA 0x00000000
+#define DDRSS_CTL_256_DATA 0x35000000
+#define DDRSS_CTL_257_DATA 0x35353535
+#define DDRSS_CTL_258_DATA 0x00002735
+#define DDRSS_CTL_259_DATA 0x00000027
+#define DDRSS_CTL_260_DATA 0x00000027
+#define DDRSS_CTL_261_DATA 0x00000027
+#define DDRSS_CTL_262_DATA 0x00000027
+#define DDRSS_CTL_263_DATA 0x00000027
+#define DDRSS_CTL_264_DATA 0x00000000
+#define DDRSS_CTL_265_DATA 0x00000000
+#define DDRSS_CTL_266_DATA 0x0000000F
+#define DDRSS_CTL_267_DATA 0x0000000F
+#define DDRSS_CTL_268_DATA 0x0000000F
+#define DDRSS_CTL_269_DATA 0x0000000F
+#define DDRSS_CTL_270_DATA 0x0000000F
+#define DDRSS_CTL_271_DATA 0x0000000F
+#define DDRSS_CTL_272_DATA 0x00000000
+#define DDRSS_CTL_273_DATA 0x00001600
+#define DDRSS_CTL_274_DATA 0x00000016
+#define DDRSS_CTL_275_DATA 0x00000016
+#define DDRSS_CTL_276_DATA 0x00000016
+#define DDRSS_CTL_277_DATA 0x00000016
+#define DDRSS_CTL_278_DATA 0x00000016
+#define DDRSS_CTL_279_DATA 0x00000020
+#define DDRSS_CTL_280_DATA 0x00010000
+#define DDRSS_CTL_281_DATA 0x00000100
+#define DDRSS_CTL_282_DATA 0x00000000
+#define DDRSS_CTL_283_DATA 0x00000000
+#define DDRSS_CTL_284_DATA 0x00000101
+#define DDRSS_CTL_285_DATA 0x00000000
+#define DDRSS_CTL_286_DATA 0x00000000
+#define DDRSS_CTL_287_DATA 0x00000000
+#define DDRSS_CTL_288_DATA 0x00000000
+#define DDRSS_CTL_289_DATA 0x00000000
+#define DDRSS_CTL_290_DATA 0x00000000
+#define DDRSS_CTL_291_DATA 0x00000000
+#define DDRSS_CTL_292_DATA 0x00000000
+#define DDRSS_CTL_293_DATA 0x00000000
+#define DDRSS_CTL_294_DATA 0x00000000
+#define DDRSS_CTL_295_DATA 0x00000000
+#define DDRSS_CTL_296_DATA 0x0C181511
+#define DDRSS_CTL_297_DATA 0x00000304
+#define DDRSS_CTL_298_DATA 0x00000000
+#define DDRSS_CTL_299_DATA 0x00000000
+#define DDRSS_CTL_300_DATA 0x00000000
+#define DDRSS_CTL_301_DATA 0x00000000
+#define DDRSS_CTL_302_DATA 0x00000000
+#define DDRSS_CTL_303_DATA 0x00000000
+#define DDRSS_CTL_304_DATA 0x00000000
+#define DDRSS_CTL_305_DATA 0x00000000
+#define DDRSS_CTL_306_DATA 0x00000000
+#define DDRSS_CTL_307_DATA 0x00000000
+#define DDRSS_CTL_308_DATA 0x00000000
+#define DDRSS_CTL_309_DATA 0x00000000
+#define DDRSS_CTL_310_DATA 0x00000000
+#define DDRSS_CTL_311_DATA 0x00020000
+#define DDRSS_CTL_312_DATA 0x00400100
+#define DDRSS_CTL_313_DATA 0x00080032
+#define DDRSS_CTL_314_DATA 0x01000200
+#define DDRSS_CTL_315_DATA 0x074A0040
+#define DDRSS_CTL_316_DATA 0x00020038
+#define DDRSS_CTL_317_DATA 0x00400100
+#define DDRSS_CTL_318_DATA 0x0038074A
+#define DDRSS_CTL_319_DATA 0x00030000
+#define DDRSS_CTL_320_DATA 0x005E005E
+#define DDRSS_CTL_321_DATA 0x00000100
+#define DDRSS_CTL_322_DATA 0x01010000
+#define DDRSS_CTL_323_DATA 0x00000000
+#define DDRSS_CTL_324_DATA 0x3FFF0000
+#define DDRSS_CTL_325_DATA 0x000FFF00
+#define DDRSS_CTL_326_DATA 0xFFFFFFFF
+#define DDRSS_CTL_327_DATA 0x00FFFF00
+#define DDRSS_CTL_328_DATA 0x0B000000
+#define DDRSS_CTL_329_DATA 0x0001FFFF
+#define DDRSS_CTL_330_DATA 0x01010101
+#define DDRSS_CTL_331_DATA 0x01010101
+#define DDRSS_CTL_332_DATA 0x00000118
+#define DDRSS_CTL_333_DATA 0x00000C01
+#define DDRSS_CTL_334_DATA 0x00040100
+#define DDRSS_CTL_335_DATA 0x00040100
+#define DDRSS_CTL_336_DATA 0x00000000
+#define DDRSS_CTL_337_DATA 0x00000000
+#define DDRSS_CTL_338_DATA 0x01030303
+#define DDRSS_CTL_339_DATA 0x00000000
+#define DDRSS_CTL_340_DATA 0x00000000
+#define DDRSS_CTL_341_DATA 0x00000000
+#define DDRSS_CTL_342_DATA 0x00000000
+#define DDRSS_CTL_343_DATA 0x00000000
+#define DDRSS_CTL_344_DATA 0x00000000
+#define DDRSS_CTL_345_DATA 0x00000000
+#define DDRSS_CTL_346_DATA 0x00000000
+#define DDRSS_CTL_347_DATA 0x00000000
+#define DDRSS_CTL_348_DATA 0x00000000
+#define DDRSS_CTL_349_DATA 0x00000000
+#define DDRSS_CTL_350_DATA 0x00000000
+#define DDRSS_CTL_351_DATA 0x00000000
+#define DDRSS_CTL_352_DATA 0x00000000
+#define DDRSS_CTL_353_DATA 0x00000000
+#define DDRSS_CTL_354_DATA 0x00000000
+#define DDRSS_CTL_355_DATA 0x00000000
+#define DDRSS_CTL_356_DATA 0x00000000
+#define DDRSS_CTL_357_DATA 0x00000000
+#define DDRSS_CTL_358_DATA 0x00000000
+#define DDRSS_CTL_359_DATA 0x00000000
+#define DDRSS_CTL_360_DATA 0x00000000
+#define DDRSS_CTL_361_DATA 0x00000000
+#define DDRSS_CTL_362_DATA 0x00000000
+#define DDRSS_CTL_363_DATA 0x00000000
+#define DDRSS_CTL_364_DATA 0x00000000
+#define DDRSS_CTL_365_DATA 0x00000000
+#define DDRSS_CTL_366_DATA 0x00000000
+#define DDRSS_CTL_367_DATA 0x00000000
+#define DDRSS_CTL_368_DATA 0x00000000
+#define DDRSS_CTL_369_DATA 0x00000000
+#define DDRSS_CTL_370_DATA 0x00000000
+#define DDRSS_CTL_371_DATA 0x00000000
+#define DDRSS_CTL_372_DATA 0x00000000
+#define DDRSS_CTL_373_DATA 0x00000000
+#define DDRSS_CTL_374_DATA 0x00000000
+#define DDRSS_CTL_375_DATA 0x00000000
+#define DDRSS_CTL_376_DATA 0x00000000
+#define DDRSS_CTL_377_DATA 0x00000000
+#define DDRSS_CTL_378_DATA 0x00000000
+#define DDRSS_CTL_379_DATA 0x00000000
+#define DDRSS_CTL_380_DATA 0x00000000
+#define DDRSS_CTL_381_DATA 0x00000000
+#define DDRSS_CTL_382_DATA 0x00000000
+#define DDRSS_CTL_383_DATA 0x01000101
+#define DDRSS_CTL_384_DATA 0x01010001
+#define DDRSS_CTL_385_DATA 0x00010101
+#define DDRSS_CTL_386_DATA 0x01090903
+#define DDRSS_CTL_387_DATA 0x05020201
+#define DDRSS_CTL_388_DATA 0x0E081B1B
+#define DDRSS_CTL_389_DATA 0x0009040E
+#define DDRSS_CTL_390_DATA 0x0B0D040F
+#define DDRSS_CTL_391_DATA 0x0B0D0406
+#define DDRSS_CTL_392_DATA 0x0D0D0906
+#define DDRSS_CTL_393_DATA 0x01000000
+#define DDRSS_CTL_394_DATA 0x07030701
+#define DDRSS_CTL_395_DATA 0x04000103
+#define DDRSS_CTL_396_DATA 0x1B000004
+#define DDRSS_CTL_397_DATA 0x000000B2
+#define DDRSS_CTL_398_DATA 0x00000200
+#define DDRSS_CTL_399_DATA 0x00000200
+#define DDRSS_CTL_400_DATA 0x00000200
+#define DDRSS_CTL_401_DATA 0x00000200
+#define DDRSS_CTL_402_DATA 0x00000321
+#define DDRSS_CTL_403_DATA 0x000006F4
+#define DDRSS_CTL_404_DATA 0x03000202
+#define DDRSS_CTL_405_DATA 0x37200201
+#define DDRSS_CTL_406_DATA 0x00001C5C
+#define DDRSS_CTL_407_DATA 0x00000200
+#define DDRSS_CTL_408_DATA 0x00000200
+#define DDRSS_CTL_409_DATA 0x00000200
+#define DDRSS_CTL_410_DATA 0x00000200
+#define DDRSS_CTL_411_DATA 0x00007F9E
+#define DDRSS_CTL_412_DATA 0x00011B98
+#define DDRSS_CTL_413_DATA 0x111A0402
+#define DDRSS_CTL_414_DATA 0x37200C09
+#define DDRSS_CTL_415_DATA 0x00001C5C
+#define DDRSS_CTL_416_DATA 0x00000200
+#define DDRSS_CTL_417_DATA 0x00000200
+#define DDRSS_CTL_418_DATA 0x00000200
+#define DDRSS_CTL_419_DATA 0x00000200
+#define DDRSS_CTL_420_DATA 0x00007F9E
+#define DDRSS_CTL_421_DATA 0x00011B98
+#define DDRSS_CTL_422_DATA 0x111A0402
+#define DDRSS_CTL_423_DATA 0x00200C09
+#define DDRSS_CTL_424_DATA 0x00000000
+#define DDRSS_CTL_425_DATA 0x02000A00
+#define DDRSS_CTL_426_DATA 0x00050003
+#define DDRSS_CTL_427_DATA 0x00010101
+#define DDRSS_CTL_428_DATA 0x00010101
+#define DDRSS_CTL_429_DATA 0x00010001
+#define DDRSS_CTL_430_DATA 0x00000101
+#define DDRSS_CTL_431_DATA 0x02000201
+#define DDRSS_CTL_432_DATA 0x02010000
+#define DDRSS_CTL_433_DATA 0x06000200
+#define DDRSS_CTL_434_DATA 0x00002222
+#define DDRSS_PI_0_DATA 0x00000B00
+#define DDRSS_PI_1_DATA 0x00000000
+#define DDRSS_PI_2_DATA 0x00000000
+#define DDRSS_PI_3_DATA 0x01000000
+#define DDRSS_PI_4_DATA 0x00000001
+#define DDRSS_PI_5_DATA 0x00010064
+#define DDRSS_PI_6_DATA 0x00000000
+#define DDRSS_PI_7_DATA 0x00000000
+#define DDRSS_PI_8_DATA 0x00000000
+#define DDRSS_PI_9_DATA 0x00000000
+#define DDRSS_PI_10_DATA 0x00000000
+#define DDRSS_PI_11_DATA 0x00000002
+#define DDRSS_PI_12_DATA 0x00000005
+#define DDRSS_PI_13_DATA 0x00050001
+#define DDRSS_PI_14_DATA 0x08000000
+#define DDRSS_PI_15_DATA 0x00010300
+#define DDRSS_PI_16_DATA 0x00000005
+#define DDRSS_PI_17_DATA 0x00000000
+#define DDRSS_PI_18_DATA 0x00000000
+#define DDRSS_PI_19_DATA 0x00000000
+#define DDRSS_PI_20_DATA 0x00000000
+#define DDRSS_PI_21_DATA 0x00000000
+#define DDRSS_PI_22_DATA 0x00000000
+#define DDRSS_PI_23_DATA 0x00000000
+#define DDRSS_PI_24_DATA 0x00000000
+#define DDRSS_PI_25_DATA 0x00000000
+#define DDRSS_PI_26_DATA 0x01010000
+#define DDRSS_PI_27_DATA 0x0A000100
+#define DDRSS_PI_28_DATA 0x00000028
+#define DDRSS_PI_29_DATA 0x05000000
+#define DDRSS_PI_30_DATA 0x00320000
+#define DDRSS_PI_31_DATA 0x00000000
+#define DDRSS_PI_32_DATA 0x00000000
+#define DDRSS_PI_33_DATA 0x01010102
+#define DDRSS_PI_34_DATA 0x00000000
+#define DDRSS_PI_35_DATA 0x00000000
+#define DDRSS_PI_36_DATA 0x00000000
+#define DDRSS_PI_37_DATA 0x00000001
+#define DDRSS_PI_38_DATA 0x000000AA
+#define DDRSS_PI_39_DATA 0x00000055
+#define DDRSS_PI_40_DATA 0x000000B5
+#define DDRSS_PI_41_DATA 0x0000004A
+#define DDRSS_PI_42_DATA 0x00000056
+#define DDRSS_PI_43_DATA 0x000000A9
+#define DDRSS_PI_44_DATA 0x000000A9
+#define DDRSS_PI_45_DATA 0x000000B5
+#define DDRSS_PI_46_DATA 0x00000000
+#define DDRSS_PI_47_DATA 0x00000000
+#define DDRSS_PI_48_DATA 0x00050500
+#define DDRSS_PI_49_DATA 0x0000001A
+#define DDRSS_PI_50_DATA 0x000007D0
+#define DDRSS_PI_51_DATA 0x00000300
+#define DDRSS_PI_52_DATA 0x00000000
+#define DDRSS_PI_53_DATA 0x00000000
+#define DDRSS_PI_54_DATA 0x01000000
+#define DDRSS_PI_55_DATA 0x00010101
+#define DDRSS_PI_56_DATA 0x01000000
+#define DDRSS_PI_57_DATA 0x03000000
+#define DDRSS_PI_58_DATA 0x00000000
+#define DDRSS_PI_59_DATA 0x00001705
+#define DDRSS_PI_60_DATA 0x00000000
+#define DDRSS_PI_61_DATA 0x00000000
+#define DDRSS_PI_62_DATA 0x00000000
+#define DDRSS_PI_63_DATA 0x0A0A140A
+#define DDRSS_PI_64_DATA 0x10020101
+#define DDRSS_PI_65_DATA 0x01000210
+#define DDRSS_PI_66_DATA 0x05000404
+#define DDRSS_PI_67_DATA 0x00010001
+#define DDRSS_PI_68_DATA 0x0001000E
+#define DDRSS_PI_69_DATA 0x01010500
+#define DDRSS_PI_70_DATA 0x00010000
+#define DDRSS_PI_71_DATA 0x00000034
+#define DDRSS_PI_72_DATA 0x00000000
+#define DDRSS_PI_73_DATA 0x00000000
+#define DDRSS_PI_74_DATA 0x0000FFFF
+#define DDRSS_PI_75_DATA 0x00000000
+#define DDRSS_PI_76_DATA 0x00000000
+#define DDRSS_PI_77_DATA 0x00000000
+#define DDRSS_PI_78_DATA 0x00000000
+#define DDRSS_PI_79_DATA 0x01000000
+#define DDRSS_PI_80_DATA 0x00010001
+#define DDRSS_PI_81_DATA 0x02000008
+#define DDRSS_PI_82_DATA 0x01000200
+#define DDRSS_PI_83_DATA 0x00000100
+#define DDRSS_PI_84_DATA 0x02000100
+#define DDRSS_PI_85_DATA 0x02000200
+#define DDRSS_PI_86_DATA 0x00000000
+#define DDRSS_PI_87_DATA 0x00000000
+#define DDRSS_PI_88_DATA 0x00000000
+#define DDRSS_PI_89_DATA 0x00000000
+#define DDRSS_PI_90_DATA 0x00000000
+#define DDRSS_PI_91_DATA 0x00000000
+#define DDRSS_PI_92_DATA 0x00000000
+#define DDRSS_PI_93_DATA 0x00000000
+#define DDRSS_PI_94_DATA 0x00000000
+#define DDRSS_PI_95_DATA 0x00000000
+#define DDRSS_PI_96_DATA 0x00000000
+#define DDRSS_PI_97_DATA 0x00000000
+#define DDRSS_PI_98_DATA 0x00000000
+#define DDRSS_PI_99_DATA 0x01000400
+#define DDRSS_PI_100_DATA 0x0E0D0F12
+#define DDRSS_PI_101_DATA 0x08111413
+#define DDRSS_PI_102_DATA 0x01000009
+#define DDRSS_PI_103_DATA 0x00000302
+#define DDRSS_PI_104_DATA 0x00000008
+#define DDRSS_PI_105_DATA 0x08000000
+#define DDRSS_PI_106_DATA 0x00000100
+#define DDRSS_PI_107_DATA 0x00000000
+#define DDRSS_PI_108_DATA 0x0000AA00
+#define DDRSS_PI_109_DATA 0x00000000
+#define DDRSS_PI_110_DATA 0x00000000
+#define DDRSS_PI_111_DATA 0x00010000
+#define DDRSS_PI_112_DATA 0x00000000
+#define DDRSS_PI_113_DATA 0x00000000
+#define DDRSS_PI_114_DATA 0x00000000
+#define DDRSS_PI_115_DATA 0x00000000
+#define DDRSS_PI_116_DATA 0x00000000
+#define DDRSS_PI_117_DATA 0x00000000
+#define DDRSS_PI_118_DATA 0x00000000
+#define DDRSS_PI_119_DATA 0x00000000
+#define DDRSS_PI_120_DATA 0x00000000
+#define DDRSS_PI_121_DATA 0x00000000
+#define DDRSS_PI_122_DATA 0x00000000
+#define DDRSS_PI_123_DATA 0x00000000
+#define DDRSS_PI_124_DATA 0x00000000
+#define DDRSS_PI_125_DATA 0x00000000
+#define DDRSS_PI_126_DATA 0x00000000
+#define DDRSS_PI_127_DATA 0x00000000
+#define DDRSS_PI_128_DATA 0x00000000
+#define DDRSS_PI_129_DATA 0x00000000
+#define DDRSS_PI_130_DATA 0x00000000
+#define DDRSS_PI_131_DATA 0x00000000
+#define DDRSS_PI_132_DATA 0x00000000
+#define DDRSS_PI_133_DATA 0x00000000
+#define DDRSS_PI_134_DATA 0x00000000
+#define DDRSS_PI_135_DATA 0x00000000
+#define DDRSS_PI_136_DATA 0x00000008
+#define DDRSS_PI_137_DATA 0x00000000
+#define DDRSS_PI_138_DATA 0x00000000
+#define DDRSS_PI_139_DATA 0x00000000
+#define DDRSS_PI_140_DATA 0x00000000
+#define DDRSS_PI_141_DATA 0x00000000
+#define DDRSS_PI_142_DATA 0x00000000
+#define DDRSS_PI_143_DATA 0x00000000
+#define DDRSS_PI_144_DATA 0x00000000
+#define DDRSS_PI_145_DATA 0x00010000
+#define DDRSS_PI_146_DATA 0x00000000
+#define DDRSS_PI_147_DATA 0x00000000
+#define DDRSS_PI_148_DATA 0x0000000A
+#define DDRSS_PI_149_DATA 0x000186A0
+#define DDRSS_PI_150_DATA 0x00000100
+#define DDRSS_PI_151_DATA 0x00000000
+#define DDRSS_PI_152_DATA 0x00000000
+#define DDRSS_PI_153_DATA 0x00000000
+#define DDRSS_PI_154_DATA 0x00000000
+#define DDRSS_PI_155_DATA 0x00000000
+#define DDRSS_PI_156_DATA 0x01000000
+#define DDRSS_PI_157_DATA 0x00010003
+#define DDRSS_PI_158_DATA 0x02000101
+#define DDRSS_PI_159_DATA 0x01030001
+#define DDRSS_PI_160_DATA 0x00010400
+#define DDRSS_PI_161_DATA 0x06000105
+#define DDRSS_PI_162_DATA 0x01070001
+#define DDRSS_PI_163_DATA 0x00000000
+#define DDRSS_PI_164_DATA 0x00000000
+#define DDRSS_PI_165_DATA 0x00000000
+#define DDRSS_PI_166_DATA 0x00010001
+#define DDRSS_PI_167_DATA 0x00000000
+#define DDRSS_PI_168_DATA 0x00000000
+#define DDRSS_PI_169_DATA 0x00000000
+#define DDRSS_PI_170_DATA 0x00000000
+#define DDRSS_PI_171_DATA 0x00010000
+#define DDRSS_PI_172_DATA 0x00000004
+#define DDRSS_PI_173_DATA 0x00000000
+#define DDRSS_PI_174_DATA 0x00010000
+#define DDRSS_PI_175_DATA 0x00000000
+#define DDRSS_PI_176_DATA 0x00080000
+#define DDRSS_PI_177_DATA 0x01180118
+#define DDRSS_PI_178_DATA 0x00262601
+#define DDRSS_PI_179_DATA 0x00000034
+#define DDRSS_PI_180_DATA 0x0000005E
+#define DDRSS_PI_181_DATA 0x0002005E
+#define DDRSS_PI_182_DATA 0x02000200
+#define DDRSS_PI_183_DATA 0x00000004
+#define DDRSS_PI_184_DATA 0x0000100C
+#define DDRSS_PI_185_DATA 0x00104000
+#define DDRSS_PI_186_DATA 0x00400000
+#define DDRSS_PI_187_DATA 0x00000013
+#define DDRSS_PI_188_DATA 0x00000059
+#define DDRSS_PI_189_DATA 0x000002C5
+#define DDRSS_PI_190_DATA 0x00000E2E
+#define DDRSS_PI_191_DATA 0x000002C5
+#define DDRSS_PI_192_DATA 0x04000E2E
+#define DDRSS_PI_193_DATA 0x01010404
+#define DDRSS_PI_194_DATA 0x00001501
+#define DDRSS_PI_195_DATA 0x00270027
+#define DDRSS_PI_196_DATA 0x01000100
+#define DDRSS_PI_197_DATA 0x00000100
+#define DDRSS_PI_198_DATA 0x00000000
+#define DDRSS_PI_199_DATA 0x05090903
+#define DDRSS_PI_200_DATA 0x01011B1B
+#define DDRSS_PI_201_DATA 0x01010101
+#define DDRSS_PI_202_DATA 0x000C0C0A
+#define DDRSS_PI_203_DATA 0x00000000
+#define DDRSS_PI_204_DATA 0x00000000
+#define DDRSS_PI_205_DATA 0x04000000
+#define DDRSS_PI_206_DATA 0x0C021212
+#define DDRSS_PI_207_DATA 0x0404020C
+#define DDRSS_PI_208_DATA 0x00090031
+#define DDRSS_PI_209_DATA 0x001B0043
+#define DDRSS_PI_210_DATA 0x001B0043
+#define DDRSS_PI_211_DATA 0x01010101
+#define DDRSS_PI_212_DATA 0x0003000D
+#define DDRSS_PI_213_DATA 0x000301D3
+#define DDRSS_PI_214_DATA 0x010001D3
+#define DDRSS_PI_215_DATA 0x000E000E
+#define DDRSS_PI_216_DATA 0x01D40100
+#define DDRSS_PI_217_DATA 0x010001D4
+#define DDRSS_PI_218_DATA 0x01D401D4
+#define DDRSS_PI_219_DATA 0x32103200
+#define DDRSS_PI_220_DATA 0x01013210
+#define DDRSS_PI_221_DATA 0x0A070601
+#define DDRSS_PI_222_DATA 0x1C11090D
+#define DDRSS_PI_223_DATA 0x1C110913
+#define DDRSS_PI_224_DATA 0x000C0013
+#define DDRSS_PI_225_DATA 0x00001000
+#define DDRSS_PI_226_DATA 0x00000C00
+#define DDRSS_PI_227_DATA 0x00001000
+#define DDRSS_PI_228_DATA 0x00000C00
+#define DDRSS_PI_229_DATA 0x02001000
+#define DDRSS_PI_230_DATA 0x0021000D
+#define DDRSS_PI_231_DATA 0x002101D3
+#define DDRSS_PI_232_DATA 0x000001D3
+#define DDRSS_PI_233_DATA 0x00001900
+#define DDRSS_PI_234_DATA 0x32000056
+#define DDRSS_PI_235_DATA 0x06000301
+#define DDRSS_PI_236_DATA 0x00300204
+#define DDRSS_PI_237_DATA 0x3212005A
+#define DDRSS_PI_238_DATA 0x17000301
+#define DDRSS_PI_239_DATA 0x00300C12
+#define DDRSS_PI_240_DATA 0x3212005A
+#define DDRSS_PI_241_DATA 0x17000301
+#define DDRSS_PI_242_DATA 0x00000C12
+#define DDRSS_PI_243_DATA 0x05040900
+#define DDRSS_PI_244_DATA 0x00040900
+#define DDRSS_PI_245_DATA 0x00000315
+#define DDRSS_PI_246_DATA 0x20010004
+#define DDRSS_PI_247_DATA 0x0A0A0A03
+#define DDRSS_PI_248_DATA 0x2B0F0000
+#define DDRSS_PI_249_DATA 0x24140026
+#define DDRSS_PI_250_DATA 0x0000731B
+#define DDRSS_PI_251_DATA 0x20070054
+#define DDRSS_PI_252_DATA 0x1B131B1C
+#define DDRSS_PI_253_DATA 0x2B0F0000
+#define DDRSS_PI_254_DATA 0x24140026
+#define DDRSS_PI_255_DATA 0x0000731B
+#define DDRSS_PI_256_DATA 0x20070054
+#define DDRSS_PI_257_DATA 0x1B131B1C
+#define DDRSS_PI_258_DATA 0x00000000
+#define DDRSS_PI_259_DATA 0x000000B2
+#define DDRSS_PI_260_DATA 0x000006F4
+#define DDRSS_PI_261_DATA 0x00001C5C
+#define DDRSS_PI_262_DATA 0x00011B98
+#define DDRSS_PI_263_DATA 0x00001C5C
+#define DDRSS_PI_264_DATA 0x00011B98
+#define DDRSS_PI_265_DATA 0x02D30014
+#define DDRSS_PI_266_DATA 0x030302D3
+#define DDRSS_PI_267_DATA 0x00000003
+#define DDRSS_PI_268_DATA 0x00000000
+#define DDRSS_PI_269_DATA 0x0A040503
+#define DDRSS_PI_270_DATA 0x00000A04
+#define DDRSS_PI_271_DATA 0x00002710
+#define DDRSS_PI_272_DATA 0x000186A0
+#define DDRSS_PI_273_DATA 0x00000005
+#define DDRSS_PI_274_DATA 0x00000064
+#define DDRSS_PI_275_DATA 0x00000014
+#define DDRSS_PI_276_DATA 0x0005B18F
+#define DDRSS_PI_277_DATA 0x000186A0
+#define DDRSS_PI_278_DATA 0x00000005
+#define DDRSS_PI_279_DATA 0x00000E94
+#define DDRSS_PI_280_DATA 0x000002D3
+#define DDRSS_PI_281_DATA 0x0005B18F
+#define DDRSS_PI_282_DATA 0x000186A0
+#define DDRSS_PI_283_DATA 0x00000005
+#define DDRSS_PI_284_DATA 0x00000E94
+#define DDRSS_PI_285_DATA 0x010002D3
+#define DDRSS_PI_286_DATA 0x00320040
+#define DDRSS_PI_287_DATA 0x00010008
+#define DDRSS_PI_288_DATA 0x074A0040
+#define DDRSS_PI_289_DATA 0x00010038
+#define DDRSS_PI_290_DATA 0x074A0040
+#define DDRSS_PI_291_DATA 0x00000338
+#define DDRSS_PI_292_DATA 0x0028005D
+#define DDRSS_PI_293_DATA 0x03040404
+#define DDRSS_PI_294_DATA 0x00000303
+#define DDRSS_PI_295_DATA 0x01010000
+#define DDRSS_PI_296_DATA 0x04040202
+#define DDRSS_PI_297_DATA 0x67670808
+#define DDRSS_PI_298_DATA 0x67676767
+#define DDRSS_PI_299_DATA 0x67676767
+#define DDRSS_PI_300_DATA 0x67676767
+#define DDRSS_PI_301_DATA 0x00006767
+#define DDRSS_PI_302_DATA 0x00000000
+#define DDRSS_PI_303_DATA 0x00000000
+#define DDRSS_PI_304_DATA 0x00000000
+#define DDRSS_PI_305_DATA 0x00000000
+#define DDRSS_PI_306_DATA 0x55000000
+#define DDRSS_PI_307_DATA 0x00000000
+#define DDRSS_PI_308_DATA 0x3C00005A
+#define DDRSS_PI_309_DATA 0x00005500
+#define DDRSS_PI_310_DATA 0x00005A00
+#define DDRSS_PI_311_DATA 0x0055003C
+#define DDRSS_PI_312_DATA 0x00000000
+#define DDRSS_PI_313_DATA 0x3C00005A
+#define DDRSS_PI_314_DATA 0x00005500
+#define DDRSS_PI_315_DATA 0x00005A00
+#define DDRSS_PI_316_DATA 0x1716153C
+#define DDRSS_PI_317_DATA 0x13100A18
+#define DDRSS_PI_318_DATA 0x06050414
+#define DDRSS_PI_319_DATA 0x02010007
+#define DDRSS_PI_320_DATA 0x00000003
+#define DDRSS_PI_321_DATA 0x00000000
+#define DDRSS_PI_322_DATA 0x00000000
+#define DDRSS_PI_323_DATA 0x01000000
+#define DDRSS_PI_324_DATA 0x04020201
+#define DDRSS_PI_325_DATA 0x00080804
+#define DDRSS_PI_326_DATA 0x00000000
+#define DDRSS_PI_327_DATA 0x00000000
+#define DDRSS_PI_328_DATA 0x00000000
+#define DDRSS_PI_329_DATA 0x00000084
+#define DDRSS_PI_330_DATA 0x00000000
+#define DDRSS_PI_331_DATA 0x00000033
+#define DDRSS_PI_332_DATA 0x00000000
+#define DDRSS_PI_333_DATA 0x00000000
+#define DDRSS_PI_334_DATA 0x35000000
+#define DDRSS_PI_335_DATA 0x20160F27
+#define DDRSS_PI_336_DATA 0x00000000
+#define DDRSS_PI_337_DATA 0x000000E4
+#define DDRSS_PI_338_DATA 0x00000036
+#define DDRSS_PI_339_DATA 0x00000033
+#define DDRSS_PI_340_DATA 0x00000000
+#define DDRSS_PI_341_DATA 0x00000000
+#define DDRSS_PI_342_DATA 0x35000000
+#define DDRSS_PI_343_DATA 0x20160F27
+#define DDRSS_PI_344_DATA 0x00000000
+#define DDRSS_PI_345_DATA 0x000000E4
+#define DDRSS_PI_346_DATA 0x00000036
+#define DDRSS_PI_347_DATA 0x00000033
+#define DDRSS_PI_348_DATA 0x00000000
+#define DDRSS_PI_349_DATA 0x00000000
+#define DDRSS_PI_350_DATA 0x35000000
+#define DDRSS_PI_351_DATA 0x20160F27
+#define DDRSS_PI_352_DATA 0x00000000
+#define DDRSS_PI_353_DATA 0x00000084
+#define DDRSS_PI_354_DATA 0x00000000
+#define DDRSS_PI_355_DATA 0x00000033
+#define DDRSS_PI_356_DATA 0x00000000
+#define DDRSS_PI_357_DATA 0x00000000
+#define DDRSS_PI_358_DATA 0x35000000
+#define DDRSS_PI_359_DATA 0x20160F27
+#define DDRSS_PI_360_DATA 0x00000000
+#define DDRSS_PI_361_DATA 0x000000E4
+#define DDRSS_PI_362_DATA 0x00000036
+#define DDRSS_PI_363_DATA 0x00000033
+#define DDRSS_PI_364_DATA 0x00000000
+#define DDRSS_PI_365_DATA 0x00000000
+#define DDRSS_PI_366_DATA 0x35000000
+#define DDRSS_PI_367_DATA 0x20160F27
+#define DDRSS_PI_368_DATA 0x00000000
+#define DDRSS_PI_369_DATA 0x000000E4
+#define DDRSS_PI_370_DATA 0x00000036
+#define DDRSS_PI_371_DATA 0x00000033
+#define DDRSS_PI_372_DATA 0x00000000
+#define DDRSS_PI_373_DATA 0x00000000
+#define DDRSS_PI_374_DATA 0x35000000
+#define DDRSS_PI_375_DATA 0x20160F27
+#define DDRSS_PI_376_DATA 0x00000000
+#define DDRSS_PI_377_DATA 0x00000084
+#define DDRSS_PI_378_DATA 0x00000000
+#define DDRSS_PI_379_DATA 0x00000033
+#define DDRSS_PI_380_DATA 0x00000000
+#define DDRSS_PI_381_DATA 0x00000000
+#define DDRSS_PI_382_DATA 0x35000000
+#define DDRSS_PI_383_DATA 0x20160F27
+#define DDRSS_PI_384_DATA 0x00000000
+#define DDRSS_PI_385_DATA 0x000000E4
+#define DDRSS_PI_386_DATA 0x00000036
+#define DDRSS_PI_387_DATA 0x00000033
+#define DDRSS_PI_388_DATA 0x00000000
+#define DDRSS_PI_389_DATA 0x00000000
+#define DDRSS_PI_390_DATA 0x35000000
+#define DDRSS_PI_391_DATA 0x20160F27
+#define DDRSS_PI_392_DATA 0x00000000
+#define DDRSS_PI_393_DATA 0x000000E4
+#define DDRSS_PI_394_DATA 0x00000036
+#define DDRSS_PI_395_DATA 0x00000033
+#define DDRSS_PI_396_DATA 0x00000000
+#define DDRSS_PI_397_DATA 0x00000000
+#define DDRSS_PI_398_DATA 0x35000000
+#define DDRSS_PI_399_DATA 0x20160F27
+#define DDRSS_PI_400_DATA 0x00000000
+#define DDRSS_PI_401_DATA 0x00000084
+#define DDRSS_PI_402_DATA 0x00000000
+#define DDRSS_PI_403_DATA 0x00000033
+#define DDRSS_PI_404_DATA 0x00000000
+#define DDRSS_PI_405_DATA 0x00000000
+#define DDRSS_PI_406_DATA 0x35000000
+#define DDRSS_PI_407_DATA 0x20160F27
+#define DDRSS_PI_408_DATA 0x00000000
+#define DDRSS_PI_409_DATA 0x000000E4
+#define DDRSS_PI_410_DATA 0x00000036
+#define DDRSS_PI_411_DATA 0x00000033
+#define DDRSS_PI_412_DATA 0x00000000
+#define DDRSS_PI_413_DATA 0x00000000
+#define DDRSS_PI_414_DATA 0x35000000
+#define DDRSS_PI_415_DATA 0x20160F27
+#define DDRSS_PI_416_DATA 0x00000000
+#define DDRSS_PI_417_DATA 0x000000E4
+#define DDRSS_PI_418_DATA 0x00000036
+#define DDRSS_PI_419_DATA 0x00000033
+#define DDRSS_PI_420_DATA 0x00000000
+#define DDRSS_PI_421_DATA 0x00000000
+#define DDRSS_PI_422_DATA 0x35000000
+#define DDRSS_PI_423_DATA 0x20160F27
+#define DDRSS_PHY_0_DATA 0x04F00000
+#define DDRSS_PHY_1_DATA 0x00000000
+#define DDRSS_PHY_2_DATA 0x00030200
+#define DDRSS_PHY_3_DATA 0x00000000
+#define DDRSS_PHY_4_DATA 0x00000000
+#define DDRSS_PHY_5_DATA 0x01030000
+#define DDRSS_PHY_6_DATA 0x00010000
+#define DDRSS_PHY_7_DATA 0x01030004
+#define DDRSS_PHY_8_DATA 0x01000000
+#define DDRSS_PHY_9_DATA 0x00000000
+#define DDRSS_PHY_10_DATA 0x00000000
+#define DDRSS_PHY_11_DATA 0x00000000
+#define DDRSS_PHY_12_DATA 0x01010000
+#define DDRSS_PHY_13_DATA 0x00010000
+#define DDRSS_PHY_14_DATA 0x00C00001
+#define DDRSS_PHY_15_DATA 0x00CC0008
+#define DDRSS_PHY_16_DATA 0x00660601
+#define DDRSS_PHY_17_DATA 0x00000003
+#define DDRSS_PHY_18_DATA 0x00000000
+#define DDRSS_PHY_19_DATA 0x00000301
+#define DDRSS_PHY_20_DATA 0x0000AAAA
+#define DDRSS_PHY_21_DATA 0x00005555
+#define DDRSS_PHY_22_DATA 0x0000B5B5
+#define DDRSS_PHY_23_DATA 0x00004A4A
+#define DDRSS_PHY_24_DATA 0x00005656
+#define DDRSS_PHY_25_DATA 0x0000A9A9
+#define DDRSS_PHY_26_DATA 0x0000B7B7
+#define DDRSS_PHY_27_DATA 0x00004848
+#define DDRSS_PHY_28_DATA 0x00000000
+#define DDRSS_PHY_29_DATA 0x00000000
+#define DDRSS_PHY_30_DATA 0x08000000
+#define DDRSS_PHY_31_DATA 0x0F000008
+#define DDRSS_PHY_32_DATA 0x00000F0F
+#define DDRSS_PHY_33_DATA 0x00E4E400
+#define DDRSS_PHY_34_DATA 0x00071040
+#define DDRSS_PHY_35_DATA 0x000C0020
+#define DDRSS_PHY_36_DATA 0x00062000
+#define DDRSS_PHY_37_DATA 0x00000000
+#define DDRSS_PHY_38_DATA 0x55555555
+#define DDRSS_PHY_39_DATA 0xAAAAAAAA
+#define DDRSS_PHY_40_DATA 0x55555555
+#define DDRSS_PHY_41_DATA 0xAAAAAAAA
+#define DDRSS_PHY_42_DATA 0x00005555
+#define DDRSS_PHY_43_DATA 0x01000100
+#define DDRSS_PHY_44_DATA 0x00800180
+#define DDRSS_PHY_45_DATA 0x00000001
+#define DDRSS_PHY_46_DATA 0x00000000
+#define DDRSS_PHY_47_DATA 0x00000000
+#define DDRSS_PHY_48_DATA 0x00000000
+#define DDRSS_PHY_49_DATA 0x00000000
+#define DDRSS_PHY_50_DATA 0x00000000
+#define DDRSS_PHY_51_DATA 0x00000000
+#define DDRSS_PHY_52_DATA 0x00000000
+#define DDRSS_PHY_53_DATA 0x00000000
+#define DDRSS_PHY_54_DATA 0x00000000
+#define DDRSS_PHY_55_DATA 0x00000000
+#define DDRSS_PHY_56_DATA 0x00000000
+#define DDRSS_PHY_57_DATA 0x00000000
+#define DDRSS_PHY_58_DATA 0x00000000
+#define DDRSS_PHY_59_DATA 0x00000000
+#define DDRSS_PHY_60_DATA 0x00000000
+#define DDRSS_PHY_61_DATA 0x00000000
+#define DDRSS_PHY_62_DATA 0x00000000
+#define DDRSS_PHY_63_DATA 0x00000000
+#define DDRSS_PHY_64_DATA 0x00000000
+#define DDRSS_PHY_65_DATA 0x00000000
+#define DDRSS_PHY_66_DATA 0x00000000
+#define DDRSS_PHY_67_DATA 0x00000004
+#define DDRSS_PHY_68_DATA 0x00000000
+#define DDRSS_PHY_69_DATA 0x00000000
+#define DDRSS_PHY_70_DATA 0x00000000
+#define DDRSS_PHY_71_DATA 0x00000000
+#define DDRSS_PHY_72_DATA 0x00000000
+#define DDRSS_PHY_73_DATA 0x00000000
+#define DDRSS_PHY_74_DATA 0x081F07FF
+#define DDRSS_PHY_75_DATA 0x10200080
+#define DDRSS_PHY_76_DATA 0x00000008
+#define DDRSS_PHY_77_DATA 0x00000401
+#define DDRSS_PHY_78_DATA 0x00000000
+#define DDRSS_PHY_79_DATA 0x01CC0C01
+#define DDRSS_PHY_80_DATA 0x1003CC0C
+#define DDRSS_PHY_81_DATA 0x20000140
+#define DDRSS_PHY_82_DATA 0x07FF0200
+#define DDRSS_PHY_83_DATA 0x0000DD01
+#define DDRSS_PHY_84_DATA 0x00100303
+#define DDRSS_PHY_85_DATA 0x00000000
+#define DDRSS_PHY_86_DATA 0x00000000
+#define DDRSS_PHY_87_DATA 0x00041000
+#define DDRSS_PHY_88_DATA 0x00100010
+#define DDRSS_PHY_89_DATA 0x00100010
+#define DDRSS_PHY_90_DATA 0x00100010
+#define DDRSS_PHY_91_DATA 0x00100010
+#define DDRSS_PHY_92_DATA 0x02000010
+#define DDRSS_PHY_93_DATA 0x00000005
+#define DDRSS_PHY_94_DATA 0x51516042
+#define DDRSS_PHY_95_DATA 0x31C06000
+#define DDRSS_PHY_96_DATA 0x07AB0340
+#define DDRSS_PHY_97_DATA 0x00C0C001
+#define DDRSS_PHY_98_DATA 0x0D000000
+#define DDRSS_PHY_99_DATA 0x000D0C0C
+#define DDRSS_PHY_100_DATA 0x42100010
+#define DDRSS_PHY_101_DATA 0x010C073E
+#define DDRSS_PHY_102_DATA 0x000F0C32
+#define DDRSS_PHY_103_DATA 0x01000140
+#define DDRSS_PHY_104_DATA 0x011E0120
+#define DDRSS_PHY_105_DATA 0x00000C00
+#define DDRSS_PHY_106_DATA 0x000002DD
+#define DDRSS_PHY_107_DATA 0x00030200
+#define DDRSS_PHY_108_DATA 0x02800000
+#define DDRSS_PHY_109_DATA 0x80800000
+#define DDRSS_PHY_110_DATA 0x000D2010
+#define DDRSS_PHY_111_DATA 0x76543210
+#define DDRSS_PHY_112_DATA 0x00000008
+#define DDRSS_PHY_113_DATA 0x045D045D
+#define DDRSS_PHY_114_DATA 0x045D045D
+#define DDRSS_PHY_115_DATA 0x045D045D
+#define DDRSS_PHY_116_DATA 0x045D045D
+#define DDRSS_PHY_117_DATA 0x0000045D
+#define DDRSS_PHY_118_DATA 0x0000A000
+#define DDRSS_PHY_119_DATA 0x00A000A0
+#define DDRSS_PHY_120_DATA 0x00A000A0
+#define DDRSS_PHY_121_DATA 0x00A000A0
+#define DDRSS_PHY_122_DATA 0x00A000A0
+#define DDRSS_PHY_123_DATA 0x00A000A0
+#define DDRSS_PHY_124_DATA 0x00A000A0
+#define DDRSS_PHY_125_DATA 0x00A000A0
+#define DDRSS_PHY_126_DATA 0x00A000A0
+#define DDRSS_PHY_127_DATA 0x00B200A0
+#define DDRSS_PHY_128_DATA 0x01000000
+#define DDRSS_PHY_129_DATA 0x00000000
+#define DDRSS_PHY_130_DATA 0x00000000
+#define DDRSS_PHY_131_DATA 0x00080200
+#define DDRSS_PHY_132_DATA 0x00000000
+#define DDRSS_PHY_133_DATA 0x20202020
+#define DDRSS_PHY_134_DATA 0x20202020
+#define DDRSS_PHY_135_DATA 0xF0F02020
+#define DDRSS_PHY_136_DATA 0x00000000
+#define DDRSS_PHY_137_DATA 0x00000000
+#define DDRSS_PHY_138_DATA 0x00000000
+#define DDRSS_PHY_139_DATA 0x00000000
+#define DDRSS_PHY_140_DATA 0x00000000
+#define DDRSS_PHY_141_DATA 0x00000000
+#define DDRSS_PHY_142_DATA 0x00000000
+#define DDRSS_PHY_143_DATA 0x00000000
+#define DDRSS_PHY_144_DATA 0x00000000
+#define DDRSS_PHY_145_DATA 0x00000000
+#define DDRSS_PHY_146_DATA 0x00000000
+#define DDRSS_PHY_147_DATA 0x00000000
+#define DDRSS_PHY_148_DATA 0x00000000
+#define DDRSS_PHY_149_DATA 0x00000000
+#define DDRSS_PHY_150_DATA 0x00000000
+#define DDRSS_PHY_151_DATA 0x00000000
+#define DDRSS_PHY_152_DATA 0x00000000
+#define DDRSS_PHY_153_DATA 0x00000000
+#define DDRSS_PHY_154_DATA 0x00000000
+#define DDRSS_PHY_155_DATA 0x00000000
+#define DDRSS_PHY_156_DATA 0x00000000
+#define DDRSS_PHY_157_DATA 0x00000000
+#define DDRSS_PHY_158_DATA 0x00000000
+#define DDRSS_PHY_159_DATA 0x00000000
+#define DDRSS_PHY_160_DATA 0x00000000
+#define DDRSS_PHY_161_DATA 0x00000000
+#define DDRSS_PHY_162_DATA 0x00000000
+#define DDRSS_PHY_163_DATA 0x00000000
+#define DDRSS_PHY_164_DATA 0x00000000
+#define DDRSS_PHY_165_DATA 0x00000000
+#define DDRSS_PHY_166_DATA 0x00000000
+#define DDRSS_PHY_167_DATA 0x00000000
+#define DDRSS_PHY_168_DATA 0x00000000
+#define DDRSS_PHY_169_DATA 0x00000000
+#define DDRSS_PHY_170_DATA 0x00000000
+#define DDRSS_PHY_171_DATA 0x00000000
+#define DDRSS_PHY_172_DATA 0x00000000
+#define DDRSS_PHY_173_DATA 0x00000000
+#define DDRSS_PHY_174_DATA 0x00000000
+#define DDRSS_PHY_175_DATA 0x00000000
+#define DDRSS_PHY_176_DATA 0x00000000
+#define DDRSS_PHY_177_DATA 0x00000000
+#define DDRSS_PHY_178_DATA 0x00000000
+#define DDRSS_PHY_179_DATA 0x00000000
+#define DDRSS_PHY_180_DATA 0x00000000
+#define DDRSS_PHY_181_DATA 0x00000000
+#define DDRSS_PHY_182_DATA 0x00000000
+#define DDRSS_PHY_183_DATA 0x00000000
+#define DDRSS_PHY_184_DATA 0x00000000
+#define DDRSS_PHY_185_DATA 0x00000000
+#define DDRSS_PHY_186_DATA 0x00000000
+#define DDRSS_PHY_187_DATA 0x00000000
+#define DDRSS_PHY_188_DATA 0x00000000
+#define DDRSS_PHY_189_DATA 0x00000000
+#define DDRSS_PHY_190_DATA 0x00000000
+#define DDRSS_PHY_191_DATA 0x00000000
+#define DDRSS_PHY_192_DATA 0x00000000
+#define DDRSS_PHY_193_DATA 0x00000000
+#define DDRSS_PHY_194_DATA 0x00000000
+#define DDRSS_PHY_195_DATA 0x00000000
+#define DDRSS_PHY_196_DATA 0x00000000
+#define DDRSS_PHY_197_DATA 0x00000000
+#define DDRSS_PHY_198_DATA 0x00000000
+#define DDRSS_PHY_199_DATA 0x00000000
+#define DDRSS_PHY_200_DATA 0x00000000
+#define DDRSS_PHY_201_DATA 0x00000000
+#define DDRSS_PHY_202_DATA 0x00000000
+#define DDRSS_PHY_203_DATA 0x00000000
+#define DDRSS_PHY_204_DATA 0x00000000
+#define DDRSS_PHY_205_DATA 0x00000000
+#define DDRSS_PHY_206_DATA 0x00000000
+#define DDRSS_PHY_207_DATA 0x00000000
+#define DDRSS_PHY_208_DATA 0x00000000
+#define DDRSS_PHY_209_DATA 0x00000000
+#define DDRSS_PHY_210_DATA 0x00000000
+#define DDRSS_PHY_211_DATA 0x00000000
+#define DDRSS_PHY_212_DATA 0x00000000
+#define DDRSS_PHY_213_DATA 0x00000000
+#define DDRSS_PHY_214_DATA 0x00000000
+#define DDRSS_PHY_215_DATA 0x00000000
+#define DDRSS_PHY_216_DATA 0x00000000
+#define DDRSS_PHY_217_DATA 0x00000000
+#define DDRSS_PHY_218_DATA 0x00000000
+#define DDRSS_PHY_219_DATA 0x00000000
+#define DDRSS_PHY_220_DATA 0x00000000
+#define DDRSS_PHY_221_DATA 0x00000000
+#define DDRSS_PHY_222_DATA 0x00000000
+#define DDRSS_PHY_223_DATA 0x00000000
+#define DDRSS_PHY_224_DATA 0x00000000
+#define DDRSS_PHY_225_DATA 0x00000000
+#define DDRSS_PHY_226_DATA 0x00000000
+#define DDRSS_PHY_227_DATA 0x00000000
+#define DDRSS_PHY_228_DATA 0x00000000
+#define DDRSS_PHY_229_DATA 0x00000000
+#define DDRSS_PHY_230_DATA 0x00000000
+#define DDRSS_PHY_231_DATA 0x00000000
+#define DDRSS_PHY_232_DATA 0x00000000
+#define DDRSS_PHY_233_DATA 0x00000000
+#define DDRSS_PHY_234_DATA 0x00000000
+#define DDRSS_PHY_235_DATA 0x00000000
+#define DDRSS_PHY_236_DATA 0x00000000
+#define DDRSS_PHY_237_DATA 0x00000000
+#define DDRSS_PHY_238_DATA 0x00000000
+#define DDRSS_PHY_239_DATA 0x00000000
+#define DDRSS_PHY_240_DATA 0x00000000
+#define DDRSS_PHY_241_DATA 0x00000000
+#define DDRSS_PHY_242_DATA 0x00000000
+#define DDRSS_PHY_243_DATA 0x00000000
+#define DDRSS_PHY_244_DATA 0x00000000
+#define DDRSS_PHY_245_DATA 0x00000000
+#define DDRSS_PHY_246_DATA 0x00000000
+#define DDRSS_PHY_247_DATA 0x00000000
+#define DDRSS_PHY_248_DATA 0x00000000
+#define DDRSS_PHY_249_DATA 0x00000000
+#define DDRSS_PHY_250_DATA 0x00000000
+#define DDRSS_PHY_251_DATA 0x00000000
+#define DDRSS_PHY_252_DATA 0x00000000
+#define DDRSS_PHY_253_DATA 0x00000000
+#define DDRSS_PHY_254_DATA 0x00000000
+#define DDRSS_PHY_255_DATA 0x00000000
+#define DDRSS_PHY_256_DATA 0x04F00000
+#define DDRSS_PHY_257_DATA 0x00000000
+#define DDRSS_PHY_258_DATA 0x00030200
+#define DDRSS_PHY_259_DATA 0x00000000
+#define DDRSS_PHY_260_DATA 0x00000000
+#define DDRSS_PHY_261_DATA 0x01030000
+#define DDRSS_PHY_262_DATA 0x00010000
+#define DDRSS_PHY_263_DATA 0x01030004
+#define DDRSS_PHY_264_DATA 0x01000000
+#define DDRSS_PHY_265_DATA 0x00000000
+#define DDRSS_PHY_266_DATA 0x00000000
+#define DDRSS_PHY_267_DATA 0x00000000
+#define DDRSS_PHY_268_DATA 0x01010000
+#define DDRSS_PHY_269_DATA 0x00010000
+#define DDRSS_PHY_270_DATA 0x00C00001
+#define DDRSS_PHY_271_DATA 0x00CC0008
+#define DDRSS_PHY_272_DATA 0x00660601
+#define DDRSS_PHY_273_DATA 0x00000003
+#define DDRSS_PHY_274_DATA 0x00000000
+#define DDRSS_PHY_275_DATA 0x00000301
+#define DDRSS_PHY_276_DATA 0x0000AAAA
+#define DDRSS_PHY_277_DATA 0x00005555
+#define DDRSS_PHY_278_DATA 0x0000B5B5
+#define DDRSS_PHY_279_DATA 0x00004A4A
+#define DDRSS_PHY_280_DATA 0x00005656
+#define DDRSS_PHY_281_DATA 0x0000A9A9
+#define DDRSS_PHY_282_DATA 0x0000B7B7
+#define DDRSS_PHY_283_DATA 0x00004848
+#define DDRSS_PHY_284_DATA 0x00000000
+#define DDRSS_PHY_285_DATA 0x00000000
+#define DDRSS_PHY_286_DATA 0x08000000
+#define DDRSS_PHY_287_DATA 0x0F000008
+#define DDRSS_PHY_288_DATA 0x00000F0F
+#define DDRSS_PHY_289_DATA 0x00E4E400
+#define DDRSS_PHY_290_DATA 0x00071040
+#define DDRSS_PHY_291_DATA 0x000C0020
+#define DDRSS_PHY_292_DATA 0x00062000
+#define DDRSS_PHY_293_DATA 0x00000000
+#define DDRSS_PHY_294_DATA 0x55555555
+#define DDRSS_PHY_295_DATA 0xAAAAAAAA
+#define DDRSS_PHY_296_DATA 0x55555555
+#define DDRSS_PHY_297_DATA 0xAAAAAAAA
+#define DDRSS_PHY_298_DATA 0x00005555
+#define DDRSS_PHY_299_DATA 0x01000100
+#define DDRSS_PHY_300_DATA 0x00800180
+#define DDRSS_PHY_301_DATA 0x00000000
+#define DDRSS_PHY_302_DATA 0x00000000
+#define DDRSS_PHY_303_DATA 0x00000000
+#define DDRSS_PHY_304_DATA 0x00000000
+#define DDRSS_PHY_305_DATA 0x00000000
+#define DDRSS_PHY_306_DATA 0x00000000
+#define DDRSS_PHY_307_DATA 0x00000000
+#define DDRSS_PHY_308_DATA 0x00000000
+#define DDRSS_PHY_309_DATA 0x00000000
+#define DDRSS_PHY_310_DATA 0x00000000
+#define DDRSS_PHY_311_DATA 0x00000000
+#define DDRSS_PHY_312_DATA 0x00000000
+#define DDRSS_PHY_313_DATA 0x00000000
+#define DDRSS_PHY_314_DATA 0x00000000
+#define DDRSS_PHY_315_DATA 0x00000000
+#define DDRSS_PHY_316_DATA 0x00000000
+#define DDRSS_PHY_317_DATA 0x00000000
+#define DDRSS_PHY_318_DATA 0x00000000
+#define DDRSS_PHY_319_DATA 0x00000000
+#define DDRSS_PHY_320_DATA 0x00000000
+#define DDRSS_PHY_321_DATA 0x00000000
+#define DDRSS_PHY_322_DATA 0x00000000
+#define DDRSS_PHY_323_DATA 0x00000004
+#define DDRSS_PHY_324_DATA 0x00000000
+#define DDRSS_PHY_325_DATA 0x00000000
+#define DDRSS_PHY_326_DATA 0x00000000
+#define DDRSS_PHY_327_DATA 0x00000000
+#define DDRSS_PHY_328_DATA 0x00000000
+#define DDRSS_PHY_329_DATA 0x00000000
+#define DDRSS_PHY_330_DATA 0x081F07FF
+#define DDRSS_PHY_331_DATA 0x10200080
+#define DDRSS_PHY_332_DATA 0x00000008
+#define DDRSS_PHY_333_DATA 0x00000401
+#define DDRSS_PHY_334_DATA 0x00000000
+#define DDRSS_PHY_335_DATA 0x01CC0C01
+#define DDRSS_PHY_336_DATA 0x1003CC0C
+#define DDRSS_PHY_337_DATA 0x20000140
+#define DDRSS_PHY_338_DATA 0x07FF0200
+#define DDRSS_PHY_339_DATA 0x0000DD01
+#define DDRSS_PHY_340_DATA 0x00100303
+#define DDRSS_PHY_341_DATA 0x00000000
+#define DDRSS_PHY_342_DATA 0x00000000
+#define DDRSS_PHY_343_DATA 0x00041000
+#define DDRSS_PHY_344_DATA 0x00100010
+#define DDRSS_PHY_345_DATA 0x00100010
+#define DDRSS_PHY_346_DATA 0x00100010
+#define DDRSS_PHY_347_DATA 0x00100010
+#define DDRSS_PHY_348_DATA 0x02000010
+#define DDRSS_PHY_349_DATA 0x00000005
+#define DDRSS_PHY_350_DATA 0x51516042
+#define DDRSS_PHY_351_DATA 0x31C06000
+#define DDRSS_PHY_352_DATA 0x07AB0340
+#define DDRSS_PHY_353_DATA 0x00C0C001
+#define DDRSS_PHY_354_DATA 0x0D000000
+#define DDRSS_PHY_355_DATA 0x000D0C0C
+#define DDRSS_PHY_356_DATA 0x42100010
+#define DDRSS_PHY_357_DATA 0x010C073E
+#define DDRSS_PHY_358_DATA 0x000F0C32
+#define DDRSS_PHY_359_DATA 0x01000140
+#define DDRSS_PHY_360_DATA 0x011E0120
+#define DDRSS_PHY_361_DATA 0x00000C00
+#define DDRSS_PHY_362_DATA 0x000002DD
+#define DDRSS_PHY_363_DATA 0x00030200
+#define DDRSS_PHY_364_DATA 0x02800000
+#define DDRSS_PHY_365_DATA 0x80800000
+#define DDRSS_PHY_366_DATA 0x000D2010
+#define DDRSS_PHY_367_DATA 0x76543210
+#define DDRSS_PHY_368_DATA 0x00000008
+#define DDRSS_PHY_369_DATA 0x045D045D
+#define DDRSS_PHY_370_DATA 0x045D045D
+#define DDRSS_PHY_371_DATA 0x045D045D
+#define DDRSS_PHY_372_DATA 0x045D045D
+#define DDRSS_PHY_373_DATA 0x0000045D
+#define DDRSS_PHY_374_DATA 0x0000A000
+#define DDRSS_PHY_375_DATA 0x00A000A0
+#define DDRSS_PHY_376_DATA 0x00A000A0
+#define DDRSS_PHY_377_DATA 0x00A000A0
+#define DDRSS_PHY_378_DATA 0x00A000A0
+#define DDRSS_PHY_379_DATA 0x00A000A0
+#define DDRSS_PHY_380_DATA 0x00A000A0
+#define DDRSS_PHY_381_DATA 0x00A000A0
+#define DDRSS_PHY_382_DATA 0x00A000A0
+#define DDRSS_PHY_383_DATA 0x00B200A0
+#define DDRSS_PHY_384_DATA 0x01000000
+#define DDRSS_PHY_385_DATA 0x00000000
+#define DDRSS_PHY_386_DATA 0x00000000
+#define DDRSS_PHY_387_DATA 0x00080200
+#define DDRSS_PHY_388_DATA 0x00000000
+#define DDRSS_PHY_389_DATA 0x20202020
+#define DDRSS_PHY_390_DATA 0x20202020
+#define DDRSS_PHY_391_DATA 0xF0F02020
+#define DDRSS_PHY_392_DATA 0x00000000
+#define DDRSS_PHY_393_DATA 0x00000000
+#define DDRSS_PHY_394_DATA 0x00000000
+#define DDRSS_PHY_395_DATA 0x00000000
+#define DDRSS_PHY_396_DATA 0x00000000
+#define DDRSS_PHY_397_DATA 0x00000000
+#define DDRSS_PHY_398_DATA 0x00000000
+#define DDRSS_PHY_399_DATA 0x00000000
+#define DDRSS_PHY_400_DATA 0x00000000
+#define DDRSS_PHY_401_DATA 0x00000000
+#define DDRSS_PHY_402_DATA 0x00000000
+#define DDRSS_PHY_403_DATA 0x00000000
+#define DDRSS_PHY_404_DATA 0x00000000
+#define DDRSS_PHY_405_DATA 0x00000000
+#define DDRSS_PHY_406_DATA 0x00000000
+#define DDRSS_PHY_407_DATA 0x00000000
+#define DDRSS_PHY_408_DATA 0x00000000
+#define DDRSS_PHY_409_DATA 0x00000000
+#define DDRSS_PHY_410_DATA 0x00000000
+#define DDRSS_PHY_411_DATA 0x00000000
+#define DDRSS_PHY_412_DATA 0x00000000
+#define DDRSS_PHY_413_DATA 0x00000000
+#define DDRSS_PHY_414_DATA 0x00000000
+#define DDRSS_PHY_415_DATA 0x00000000
+#define DDRSS_PHY_416_DATA 0x00000000
+#define DDRSS_PHY_417_DATA 0x00000000
+#define DDRSS_PHY_418_DATA 0x00000000
+#define DDRSS_PHY_419_DATA 0x00000000
+#define DDRSS_PHY_420_DATA 0x00000000
+#define DDRSS_PHY_421_DATA 0x00000000
+#define DDRSS_PHY_422_DATA 0x00000000
+#define DDRSS_PHY_423_DATA 0x00000000
+#define DDRSS_PHY_424_DATA 0x00000000
+#define DDRSS_PHY_425_DATA 0x00000000
+#define DDRSS_PHY_426_DATA 0x00000000
+#define DDRSS_PHY_427_DATA 0x00000000
+#define DDRSS_PHY_428_DATA 0x00000000
+#define DDRSS_PHY_429_DATA 0x00000000
+#define DDRSS_PHY_430_DATA 0x00000000
+#define DDRSS_PHY_431_DATA 0x00000000
+#define DDRSS_PHY_432_DATA 0x00000000
+#define DDRSS_PHY_433_DATA 0x00000000
+#define DDRSS_PHY_434_DATA 0x00000000
+#define DDRSS_PHY_435_DATA 0x00000000
+#define DDRSS_PHY_436_DATA 0x00000000
+#define DDRSS_PHY_437_DATA 0x00000000
+#define DDRSS_PHY_438_DATA 0x00000000
+#define DDRSS_PHY_439_DATA 0x00000000
+#define DDRSS_PHY_440_DATA 0x00000000
+#define DDRSS_PHY_441_DATA 0x00000000
+#define DDRSS_PHY_442_DATA 0x00000000
+#define DDRSS_PHY_443_DATA 0x00000000
+#define DDRSS_PHY_444_DATA 0x00000000
+#define DDRSS_PHY_445_DATA 0x00000000
+#define DDRSS_PHY_446_DATA 0x00000000
+#define DDRSS_PHY_447_DATA 0x00000000
+#define DDRSS_PHY_448_DATA 0x00000000
+#define DDRSS_PHY_449_DATA 0x00000000
+#define DDRSS_PHY_450_DATA 0x00000000
+#define DDRSS_PHY_451_DATA 0x00000000
+#define DDRSS_PHY_452_DATA 0x00000000
+#define DDRSS_PHY_453_DATA 0x00000000
+#define DDRSS_PHY_454_DATA 0x00000000
+#define DDRSS_PHY_455_DATA 0x00000000
+#define DDRSS_PHY_456_DATA 0x00000000
+#define DDRSS_PHY_457_DATA 0x00000000
+#define DDRSS_PHY_458_DATA 0x00000000
+#define DDRSS_PHY_459_DATA 0x00000000
+#define DDRSS_PHY_460_DATA 0x00000000
+#define DDRSS_PHY_461_DATA 0x00000000
+#define DDRSS_PHY_462_DATA 0x00000000
+#define DDRSS_PHY_463_DATA 0x00000000
+#define DDRSS_PHY_464_DATA 0x00000000
+#define DDRSS_PHY_465_DATA 0x00000000
+#define DDRSS_PHY_466_DATA 0x00000000
+#define DDRSS_PHY_467_DATA 0x00000000
+#define DDRSS_PHY_468_DATA 0x00000000
+#define DDRSS_PHY_469_DATA 0x00000000
+#define DDRSS_PHY_470_DATA 0x00000000
+#define DDRSS_PHY_471_DATA 0x00000000
+#define DDRSS_PHY_472_DATA 0x00000000
+#define DDRSS_PHY_473_DATA 0x00000000
+#define DDRSS_PHY_474_DATA 0x00000000
+#define DDRSS_PHY_475_DATA 0x00000000
+#define DDRSS_PHY_476_DATA 0x00000000
+#define DDRSS_PHY_477_DATA 0x00000000
+#define DDRSS_PHY_478_DATA 0x00000000
+#define DDRSS_PHY_479_DATA 0x00000000
+#define DDRSS_PHY_480_DATA 0x00000000
+#define DDRSS_PHY_481_DATA 0x00000000
+#define DDRSS_PHY_482_DATA 0x00000000
+#define DDRSS_PHY_483_DATA 0x00000000
+#define DDRSS_PHY_484_DATA 0x00000000
+#define DDRSS_PHY_485_DATA 0x00000000
+#define DDRSS_PHY_486_DATA 0x00000000
+#define DDRSS_PHY_487_DATA 0x00000000
+#define DDRSS_PHY_488_DATA 0x00000000
+#define DDRSS_PHY_489_DATA 0x00000000
+#define DDRSS_PHY_490_DATA 0x00000000
+#define DDRSS_PHY_491_DATA 0x00000000
+#define DDRSS_PHY_492_DATA 0x00000000
+#define DDRSS_PHY_493_DATA 0x00000000
+#define DDRSS_PHY_494_DATA 0x00000000
+#define DDRSS_PHY_495_DATA 0x00000000
+#define DDRSS_PHY_496_DATA 0x00000000
+#define DDRSS_PHY_497_DATA 0x00000000
+#define DDRSS_PHY_498_DATA 0x00000000
+#define DDRSS_PHY_499_DATA 0x00000000
+#define DDRSS_PHY_500_DATA 0x00000000
+#define DDRSS_PHY_501_DATA 0x00000000
+#define DDRSS_PHY_502_DATA 0x00000000
+#define DDRSS_PHY_503_DATA 0x00000000
+#define DDRSS_PHY_504_DATA 0x00000000
+#define DDRSS_PHY_505_DATA 0x00000000
+#define DDRSS_PHY_506_DATA 0x00000000
+#define DDRSS_PHY_507_DATA 0x00000000
+#define DDRSS_PHY_508_DATA 0x00000000
+#define DDRSS_PHY_509_DATA 0x00000000
+#define DDRSS_PHY_510_DATA 0x00000000
+#define DDRSS_PHY_511_DATA 0x00000000
+#define DDRSS_PHY_512_DATA 0x04F00000
+#define DDRSS_PHY_513_DATA 0x00000000
+#define DDRSS_PHY_514_DATA 0x00030200
+#define DDRSS_PHY_515_DATA 0x00000000
+#define DDRSS_PHY_516_DATA 0x00000000
+#define DDRSS_PHY_517_DATA 0x01030000
+#define DDRSS_PHY_518_DATA 0x00010000
+#define DDRSS_PHY_519_DATA 0x01030004
+#define DDRSS_PHY_520_DATA 0x01000000
+#define DDRSS_PHY_521_DATA 0x00000000
+#define DDRSS_PHY_522_DATA 0x00000000
+#define DDRSS_PHY_523_DATA 0x00000000
+#define DDRSS_PHY_524_DATA 0x01010000
+#define DDRSS_PHY_525_DATA 0x00010000
+#define DDRSS_PHY_526_DATA 0x00C00001
+#define DDRSS_PHY_527_DATA 0x00CC0008
+#define DDRSS_PHY_528_DATA 0x00660601
+#define DDRSS_PHY_529_DATA 0x00000003
+#define DDRSS_PHY_530_DATA 0x00000000
+#define DDRSS_PHY_531_DATA 0x00000301
+#define DDRSS_PHY_532_DATA 0x0000AAAA
+#define DDRSS_PHY_533_DATA 0x00005555
+#define DDRSS_PHY_534_DATA 0x0000B5B5
+#define DDRSS_PHY_535_DATA 0x00004A4A
+#define DDRSS_PHY_536_DATA 0x00005656
+#define DDRSS_PHY_537_DATA 0x0000A9A9
+#define DDRSS_PHY_538_DATA 0x0000B7B7
+#define DDRSS_PHY_539_DATA 0x00004848
+#define DDRSS_PHY_540_DATA 0x00000000
+#define DDRSS_PHY_541_DATA 0x00000000
+#define DDRSS_PHY_542_DATA 0x08000000
+#define DDRSS_PHY_543_DATA 0x0F000008
+#define DDRSS_PHY_544_DATA 0x00000F0F
+#define DDRSS_PHY_545_DATA 0x00E4E400
+#define DDRSS_PHY_546_DATA 0x00071040
+#define DDRSS_PHY_547_DATA 0x000C0020
+#define DDRSS_PHY_548_DATA 0x00062000
+#define DDRSS_PHY_549_DATA 0x00000000
+#define DDRSS_PHY_550_DATA 0x55555555
+#define DDRSS_PHY_551_DATA 0xAAAAAAAA
+#define DDRSS_PHY_552_DATA 0x55555555
+#define DDRSS_PHY_553_DATA 0xAAAAAAAA
+#define DDRSS_PHY_554_DATA 0x00005555
+#define DDRSS_PHY_555_DATA 0x01000100
+#define DDRSS_PHY_556_DATA 0x00800180
+#define DDRSS_PHY_557_DATA 0x00000001
+#define DDRSS_PHY_558_DATA 0x00000000
+#define DDRSS_PHY_559_DATA 0x00000000
+#define DDRSS_PHY_560_DATA 0x00000000
+#define DDRSS_PHY_561_DATA 0x00000000
+#define DDRSS_PHY_562_DATA 0x00000000
+#define DDRSS_PHY_563_DATA 0x00000000
+#define DDRSS_PHY_564_DATA 0x00000000
+#define DDRSS_PHY_565_DATA 0x00000000
+#define DDRSS_PHY_566_DATA 0x00000000
+#define DDRSS_PHY_567_DATA 0x00000000
+#define DDRSS_PHY_568_DATA 0x00000000
+#define DDRSS_PHY_569_DATA 0x00000000
+#define DDRSS_PHY_570_DATA 0x00000000
+#define DDRSS_PHY_571_DATA 0x00000000
+#define DDRSS_PHY_572_DATA 0x00000000
+#define DDRSS_PHY_573_DATA 0x00000000
+#define DDRSS_PHY_574_DATA 0x00000000
+#define DDRSS_PHY_575_DATA 0x00000000
+#define DDRSS_PHY_576_DATA 0x00000000
+#define DDRSS_PHY_577_DATA 0x00000000
+#define DDRSS_PHY_578_DATA 0x00000000
+#define DDRSS_PHY_579_DATA 0x00000004
+#define DDRSS_PHY_580_DATA 0x00000000
+#define DDRSS_PHY_581_DATA 0x00000000
+#define DDRSS_PHY_582_DATA 0x00000000
+#define DDRSS_PHY_583_DATA 0x00000000
+#define DDRSS_PHY_584_DATA 0x00000000
+#define DDRSS_PHY_585_DATA 0x00000000
+#define DDRSS_PHY_586_DATA 0x081F07FF
+#define DDRSS_PHY_587_DATA 0x10200080
+#define DDRSS_PHY_588_DATA 0x00000008
+#define DDRSS_PHY_589_DATA 0x00000401
+#define DDRSS_PHY_590_DATA 0x00000000
+#define DDRSS_PHY_591_DATA 0x01CC0C01
+#define DDRSS_PHY_592_DATA 0x1003CC0C
+#define DDRSS_PHY_593_DATA 0x20000140
+#define DDRSS_PHY_594_DATA 0x07FF0200
+#define DDRSS_PHY_595_DATA 0x0000DD01
+#define DDRSS_PHY_596_DATA 0x00100303
+#define DDRSS_PHY_597_DATA 0x00000000
+#define DDRSS_PHY_598_DATA 0x00000000
+#define DDRSS_PHY_599_DATA 0x00041000
+#define DDRSS_PHY_600_DATA 0x00100010
+#define DDRSS_PHY_601_DATA 0x00100010
+#define DDRSS_PHY_602_DATA 0x00100010
+#define DDRSS_PHY_603_DATA 0x00100010
+#define DDRSS_PHY_604_DATA 0x02000010
+#define DDRSS_PHY_605_DATA 0x00000005
+#define DDRSS_PHY_606_DATA 0x51516042
+#define DDRSS_PHY_607_DATA 0x31C06000
+#define DDRSS_PHY_608_DATA 0x07AB0340
+#define DDRSS_PHY_609_DATA 0x00C0C001
+#define DDRSS_PHY_610_DATA 0x0D000000
+#define DDRSS_PHY_611_DATA 0x000D0C0C
+#define DDRSS_PHY_612_DATA 0x42100010
+#define DDRSS_PHY_613_DATA 0x010C073E
+#define DDRSS_PHY_614_DATA 0x000F0C32
+#define DDRSS_PHY_615_DATA 0x01000140
+#define DDRSS_PHY_616_DATA 0x011E0120
+#define DDRSS_PHY_617_DATA 0x00000C00
+#define DDRSS_PHY_618_DATA 0x000002DD
+#define DDRSS_PHY_619_DATA 0x00030200
+#define DDRSS_PHY_620_DATA 0x02800000
+#define DDRSS_PHY_621_DATA 0x80800000
+#define DDRSS_PHY_622_DATA 0x000D2010
+#define DDRSS_PHY_623_DATA 0x76543210
+#define DDRSS_PHY_624_DATA 0x00000008
+#define DDRSS_PHY_625_DATA 0x045D045D
+#define DDRSS_PHY_626_DATA 0x045D045D
+#define DDRSS_PHY_627_DATA 0x045D045D
+#define DDRSS_PHY_628_DATA 0x045D045D
+#define DDRSS_PHY_629_DATA 0x0000045D
+#define DDRSS_PHY_630_DATA 0x0000A000
+#define DDRSS_PHY_631_DATA 0x00A000A0
+#define DDRSS_PHY_632_DATA 0x00A000A0
+#define DDRSS_PHY_633_DATA 0x00A000A0
+#define DDRSS_PHY_634_DATA 0x00A000A0
+#define DDRSS_PHY_635_DATA 0x00A000A0
+#define DDRSS_PHY_636_DATA 0x00A000A0
+#define DDRSS_PHY_637_DATA 0x00A000A0
+#define DDRSS_PHY_638_DATA 0x00A000A0
+#define DDRSS_PHY_639_DATA 0x00B200A0
+#define DDRSS_PHY_640_DATA 0x01000000
+#define DDRSS_PHY_641_DATA 0x00000000
+#define DDRSS_PHY_642_DATA 0x00000000
+#define DDRSS_PHY_643_DATA 0x00080200
+#define DDRSS_PHY_644_DATA 0x00000000
+#define DDRSS_PHY_645_DATA 0x20202020
+#define DDRSS_PHY_646_DATA 0x20202020
+#define DDRSS_PHY_647_DATA 0xF0F02020
+#define DDRSS_PHY_648_DATA 0x00000000
+#define DDRSS_PHY_649_DATA 0x00000000
+#define DDRSS_PHY_650_DATA 0x00000000
+#define DDRSS_PHY_651_DATA 0x00000000
+#define DDRSS_PHY_652_DATA 0x00000000
+#define DDRSS_PHY_653_DATA 0x00000000
+#define DDRSS_PHY_654_DATA 0x00000000
+#define DDRSS_PHY_655_DATA 0x00000000
+#define DDRSS_PHY_656_DATA 0x00000000
+#define DDRSS_PHY_657_DATA 0x00000000
+#define DDRSS_PHY_658_DATA 0x00000000
+#define DDRSS_PHY_659_DATA 0x00000000
+#define DDRSS_PHY_660_DATA 0x00000000
+#define DDRSS_PHY_661_DATA 0x00000000
+#define DDRSS_PHY_662_DATA 0x00000000
+#define DDRSS_PHY_663_DATA 0x00000000
+#define DDRSS_PHY_664_DATA 0x00000000
+#define DDRSS_PHY_665_DATA 0x00000000
+#define DDRSS_PHY_666_DATA 0x00000000
+#define DDRSS_PHY_667_DATA 0x00000000
+#define DDRSS_PHY_668_DATA 0x00000000
+#define DDRSS_PHY_669_DATA 0x00000000
+#define DDRSS_PHY_670_DATA 0x00000000
+#define DDRSS_PHY_671_DATA 0x00000000
+#define DDRSS_PHY_672_DATA 0x00000000
+#define DDRSS_PHY_673_DATA 0x00000000
+#define DDRSS_PHY_674_DATA 0x00000000
+#define DDRSS_PHY_675_DATA 0x00000000
+#define DDRSS_PHY_676_DATA 0x00000000
+#define DDRSS_PHY_677_DATA 0x00000000
+#define DDRSS_PHY_678_DATA 0x00000000
+#define DDRSS_PHY_679_DATA 0x00000000
+#define DDRSS_PHY_680_DATA 0x00000000
+#define DDRSS_PHY_681_DATA 0x00000000
+#define DDRSS_PHY_682_DATA 0x00000000
+#define DDRSS_PHY_683_DATA 0x00000000
+#define DDRSS_PHY_684_DATA 0x00000000
+#define DDRSS_PHY_685_DATA 0x00000000
+#define DDRSS_PHY_686_DATA 0x00000000
+#define DDRSS_PHY_687_DATA 0x00000000
+#define DDRSS_PHY_688_DATA 0x00000000
+#define DDRSS_PHY_689_DATA 0x00000000
+#define DDRSS_PHY_690_DATA 0x00000000
+#define DDRSS_PHY_691_DATA 0x00000000
+#define DDRSS_PHY_692_DATA 0x00000000
+#define DDRSS_PHY_693_DATA 0x00000000
+#define DDRSS_PHY_694_DATA 0x00000000
+#define DDRSS_PHY_695_DATA 0x00000000
+#define DDRSS_PHY_696_DATA 0x00000000
+#define DDRSS_PHY_697_DATA 0x00000000
+#define DDRSS_PHY_698_DATA 0x00000000
+#define DDRSS_PHY_699_DATA 0x00000000
+#define DDRSS_PHY_700_DATA 0x00000000
+#define DDRSS_PHY_701_DATA 0x00000000
+#define DDRSS_PHY_702_DATA 0x00000000
+#define DDRSS_PHY_703_DATA 0x00000000
+#define DDRSS_PHY_704_DATA 0x00000000
+#define DDRSS_PHY_705_DATA 0x00000000
+#define DDRSS_PHY_706_DATA 0x00000000
+#define DDRSS_PHY_707_DATA 0x00000000
+#define DDRSS_PHY_708_DATA 0x00000000
+#define DDRSS_PHY_709_DATA 0x00000000
+#define DDRSS_PHY_710_DATA 0x00000000
+#define DDRSS_PHY_711_DATA 0x00000000
+#define DDRSS_PHY_712_DATA 0x00000000
+#define DDRSS_PHY_713_DATA 0x00000000
+#define DDRSS_PHY_714_DATA 0x00000000
+#define DDRSS_PHY_715_DATA 0x00000000
+#define DDRSS_PHY_716_DATA 0x00000000
+#define DDRSS_PHY_717_DATA 0x00000000
+#define DDRSS_PHY_718_DATA 0x00000000
+#define DDRSS_PHY_719_DATA 0x00000000
+#define DDRSS_PHY_720_DATA 0x00000000
+#define DDRSS_PHY_721_DATA 0x00000000
+#define DDRSS_PHY_722_DATA 0x00000000
+#define DDRSS_PHY_723_DATA 0x00000000
+#define DDRSS_PHY_724_DATA 0x00000000
+#define DDRSS_PHY_725_DATA 0x00000000
+#define DDRSS_PHY_726_DATA 0x00000000
+#define DDRSS_PHY_727_DATA 0x00000000
+#define DDRSS_PHY_728_DATA 0x00000000
+#define DDRSS_PHY_729_DATA 0x00000000
+#define DDRSS_PHY_730_DATA 0x00000000
+#define DDRSS_PHY_731_DATA 0x00000000
+#define DDRSS_PHY_732_DATA 0x00000000
+#define DDRSS_PHY_733_DATA 0x00000000
+#define DDRSS_PHY_734_DATA 0x00000000
+#define DDRSS_PHY_735_DATA 0x00000000
+#define DDRSS_PHY_736_DATA 0x00000000
+#define DDRSS_PHY_737_DATA 0x00000000
+#define DDRSS_PHY_738_DATA 0x00000000
+#define DDRSS_PHY_739_DATA 0x00000000
+#define DDRSS_PHY_740_DATA 0x00000000
+#define DDRSS_PHY_741_DATA 0x00000000
+#define DDRSS_PHY_742_DATA 0x00000000
+#define DDRSS_PHY_743_DATA 0x00000000
+#define DDRSS_PHY_744_DATA 0x00000000
+#define DDRSS_PHY_745_DATA 0x00000000
+#define DDRSS_PHY_746_DATA 0x00000000
+#define DDRSS_PHY_747_DATA 0x00000000
+#define DDRSS_PHY_748_DATA 0x00000000
+#define DDRSS_PHY_749_DATA 0x00000000
+#define DDRSS_PHY_750_DATA 0x00000000
+#define DDRSS_PHY_751_DATA 0x00000000
+#define DDRSS_PHY_752_DATA 0x00000000
+#define DDRSS_PHY_753_DATA 0x00000000
+#define DDRSS_PHY_754_DATA 0x00000000
+#define DDRSS_PHY_755_DATA 0x00000000
+#define DDRSS_PHY_756_DATA 0x00000000
+#define DDRSS_PHY_757_DATA 0x00000000
+#define DDRSS_PHY_758_DATA 0x00000000
+#define DDRSS_PHY_759_DATA 0x00000000
+#define DDRSS_PHY_760_DATA 0x00000000
+#define DDRSS_PHY_761_DATA 0x00000000
+#define DDRSS_PHY_762_DATA 0x00000000
+#define DDRSS_PHY_763_DATA 0x00000000
+#define DDRSS_PHY_764_DATA 0x00000000
+#define DDRSS_PHY_765_DATA 0x00000000
+#define DDRSS_PHY_766_DATA 0x00000000
+#define DDRSS_PHY_767_DATA 0x00000000
+#define DDRSS_PHY_768_DATA 0x04F00000
+#define DDRSS_PHY_769_DATA 0x00000000
+#define DDRSS_PHY_770_DATA 0x00030200
+#define DDRSS_PHY_771_DATA 0x00000000
+#define DDRSS_PHY_772_DATA 0x00000000
+#define DDRSS_PHY_773_DATA 0x01030000
+#define DDRSS_PHY_774_DATA 0x00010000
+#define DDRSS_PHY_775_DATA 0x01030004
+#define DDRSS_PHY_776_DATA 0x01000000
+#define DDRSS_PHY_777_DATA 0x00000000
+#define DDRSS_PHY_778_DATA 0x00000000
+#define DDRSS_PHY_779_DATA 0x00000000
+#define DDRSS_PHY_780_DATA 0x01010000
+#define DDRSS_PHY_781_DATA 0x00010000
+#define DDRSS_PHY_782_DATA 0x00C00001
+#define DDRSS_PHY_783_DATA 0x00CC0008
+#define DDRSS_PHY_784_DATA 0x00660601
+#define DDRSS_PHY_785_DATA 0x00000003
+#define DDRSS_PHY_786_DATA 0x00000000
+#define DDRSS_PHY_787_DATA 0x00000301
+#define DDRSS_PHY_788_DATA 0x0000AAAA
+#define DDRSS_PHY_789_DATA 0x00005555
+#define DDRSS_PHY_790_DATA 0x0000B5B5
+#define DDRSS_PHY_791_DATA 0x00004A4A
+#define DDRSS_PHY_792_DATA 0x00005656
+#define DDRSS_PHY_793_DATA 0x0000A9A9
+#define DDRSS_PHY_794_DATA 0x0000B7B7
+#define DDRSS_PHY_795_DATA 0x00004848
+#define DDRSS_PHY_796_DATA 0x00000000
+#define DDRSS_PHY_797_DATA 0x00000000
+#define DDRSS_PHY_798_DATA 0x08000000
+#define DDRSS_PHY_799_DATA 0x0F000008
+#define DDRSS_PHY_800_DATA 0x00000F0F
+#define DDRSS_PHY_801_DATA 0x00E4E400
+#define DDRSS_PHY_802_DATA 0x00071040
+#define DDRSS_PHY_803_DATA 0x000C0020
+#define DDRSS_PHY_804_DATA 0x00062000
+#define DDRSS_PHY_805_DATA 0x00000000
+#define DDRSS_PHY_806_DATA 0x55555555
+#define DDRSS_PHY_807_DATA 0xAAAAAAAA
+#define DDRSS_PHY_808_DATA 0x55555555
+#define DDRSS_PHY_809_DATA 0xAAAAAAAA
+#define DDRSS_PHY_810_DATA 0x00005555
+#define DDRSS_PHY_811_DATA 0x01000100
+#define DDRSS_PHY_812_DATA 0x00800180
+#define DDRSS_PHY_813_DATA 0x00000000
+#define DDRSS_PHY_814_DATA 0x00000000
+#define DDRSS_PHY_815_DATA 0x00000000
+#define DDRSS_PHY_816_DATA 0x00000000
+#define DDRSS_PHY_817_DATA 0x00000000
+#define DDRSS_PHY_818_DATA 0x00000000
+#define DDRSS_PHY_819_DATA 0x00000000
+#define DDRSS_PHY_820_DATA 0x00000000
+#define DDRSS_PHY_821_DATA 0x00000000
+#define DDRSS_PHY_822_DATA 0x00000000
+#define DDRSS_PHY_823_DATA 0x00000000
+#define DDRSS_PHY_824_DATA 0x00000000
+#define DDRSS_PHY_825_DATA 0x00000000
+#define DDRSS_PHY_826_DATA 0x00000000
+#define DDRSS_PHY_827_DATA 0x00000000
+#define DDRSS_PHY_828_DATA 0x00000000
+#define DDRSS_PHY_829_DATA 0x00000000
+#define DDRSS_PHY_830_DATA 0x00000000
+#define DDRSS_PHY_831_DATA 0x00000000
+#define DDRSS_PHY_832_DATA 0x00000000
+#define DDRSS_PHY_833_DATA 0x00000000
+#define DDRSS_PHY_834_DATA 0x00000000
+#define DDRSS_PHY_835_DATA 0x00000004
+#define DDRSS_PHY_836_DATA 0x00000000
+#define DDRSS_PHY_837_DATA 0x00000000
+#define DDRSS_PHY_838_DATA 0x00000000
+#define DDRSS_PHY_839_DATA 0x00000000
+#define DDRSS_PHY_840_DATA 0x00000000
+#define DDRSS_PHY_841_DATA 0x00000000
+#define DDRSS_PHY_842_DATA 0x081F07FF
+#define DDRSS_PHY_843_DATA 0x10200080
+#define DDRSS_PHY_844_DATA 0x00000008
+#define DDRSS_PHY_845_DATA 0x00000401
+#define DDRSS_PHY_846_DATA 0x00000000
+#define DDRSS_PHY_847_DATA 0x01CC0C01
+#define DDRSS_PHY_848_DATA 0x1003CC0C
+#define DDRSS_PHY_849_DATA 0x20000140
+#define DDRSS_PHY_850_DATA 0x07FF0200
+#define DDRSS_PHY_851_DATA 0x0000DD01
+#define DDRSS_PHY_852_DATA 0x00100303
+#define DDRSS_PHY_853_DATA 0x00000000
+#define DDRSS_PHY_854_DATA 0x00000000
+#define DDRSS_PHY_855_DATA 0x00041000
+#define DDRSS_PHY_856_DATA 0x00100010
+#define DDRSS_PHY_857_DATA 0x00100010
+#define DDRSS_PHY_858_DATA 0x00100010
+#define DDRSS_PHY_859_DATA 0x00100010
+#define DDRSS_PHY_860_DATA 0x02000010
+#define DDRSS_PHY_861_DATA 0x00000005
+#define DDRSS_PHY_862_DATA 0x51516042
+#define DDRSS_PHY_863_DATA 0x31C06000
+#define DDRSS_PHY_864_DATA 0x07AB0340
+#define DDRSS_PHY_865_DATA 0x00C0C001
+#define DDRSS_PHY_866_DATA 0x0D000000
+#define DDRSS_PHY_867_DATA 0x000D0C0C
+#define DDRSS_PHY_868_DATA 0x42100010
+#define DDRSS_PHY_869_DATA 0x010C073E
+#define DDRSS_PHY_870_DATA 0x000F0C32
+#define DDRSS_PHY_871_DATA 0x01000140
+#define DDRSS_PHY_872_DATA 0x011E0120
+#define DDRSS_PHY_873_DATA 0x00000C00
+#define DDRSS_PHY_874_DATA 0x000002DD
+#define DDRSS_PHY_875_DATA 0x00030200
+#define DDRSS_PHY_876_DATA 0x02800000
+#define DDRSS_PHY_877_DATA 0x80800000
+#define DDRSS_PHY_878_DATA 0x000D2010
+#define DDRSS_PHY_879_DATA 0x76543210
+#define DDRSS_PHY_880_DATA 0x00000008
+#define DDRSS_PHY_881_DATA 0x045D045D
+#define DDRSS_PHY_882_DATA 0x045D045D
+#define DDRSS_PHY_883_DATA 0x045D045D
+#define DDRSS_PHY_884_DATA 0x045D045D
+#define DDRSS_PHY_885_DATA 0x0000045D
+#define DDRSS_PHY_886_DATA 0x0000A000
+#define DDRSS_PHY_887_DATA 0x00A000A0
+#define DDRSS_PHY_888_DATA 0x00A000A0
+#define DDRSS_PHY_889_DATA 0x00A000A0
+#define DDRSS_PHY_890_DATA 0x00A000A0
+#define DDRSS_PHY_891_DATA 0x00A000A0
+#define DDRSS_PHY_892_DATA 0x00A000A0
+#define DDRSS_PHY_893_DATA 0x00A000A0
+#define DDRSS_PHY_894_DATA 0x00A000A0
+#define DDRSS_PHY_895_DATA 0x00B200A0
+#define DDRSS_PHY_896_DATA 0x01000000
+#define DDRSS_PHY_897_DATA 0x00000000
+#define DDRSS_PHY_898_DATA 0x00000000
+#define DDRSS_PHY_899_DATA 0x00080200
+#define DDRSS_PHY_900_DATA 0x00000000
+#define DDRSS_PHY_901_DATA 0x20202020
+#define DDRSS_PHY_902_DATA 0x20202020
+#define DDRSS_PHY_903_DATA 0xF0F02020
+#define DDRSS_PHY_904_DATA 0x00000000
+#define DDRSS_PHY_905_DATA 0x00000000
+#define DDRSS_PHY_906_DATA 0x00000000
+#define DDRSS_PHY_907_DATA 0x00000000
+#define DDRSS_PHY_908_DATA 0x00000000
+#define DDRSS_PHY_909_DATA 0x00000000
+#define DDRSS_PHY_910_DATA 0x00000000
+#define DDRSS_PHY_911_DATA 0x00000000
+#define DDRSS_PHY_912_DATA 0x00000000
+#define DDRSS_PHY_913_DATA 0x00000000
+#define DDRSS_PHY_914_DATA 0x00000000
+#define DDRSS_PHY_915_DATA 0x00000000
+#define DDRSS_PHY_916_DATA 0x00000000
+#define DDRSS_PHY_917_DATA 0x00000000
+#define DDRSS_PHY_918_DATA 0x00000000
+#define DDRSS_PHY_919_DATA 0x00000000
+#define DDRSS_PHY_920_DATA 0x00000000
+#define DDRSS_PHY_921_DATA 0x00000000
+#define DDRSS_PHY_922_DATA 0x00000000
+#define DDRSS_PHY_923_DATA 0x00000000
+#define DDRSS_PHY_924_DATA 0x00000000
+#define DDRSS_PHY_925_DATA 0x00000000
+#define DDRSS_PHY_926_DATA 0x00000000
+#define DDRSS_PHY_927_DATA 0x00000000
+#define DDRSS_PHY_928_DATA 0x00000000
+#define DDRSS_PHY_929_DATA 0x00000000
+#define DDRSS_PHY_930_DATA 0x00000000
+#define DDRSS_PHY_931_DATA 0x00000000
+#define DDRSS_PHY_932_DATA 0x00000000
+#define DDRSS_PHY_933_DATA 0x00000000
+#define DDRSS_PHY_934_DATA 0x00000000
+#define DDRSS_PHY_935_DATA 0x00000000
+#define DDRSS_PHY_936_DATA 0x00000000
+#define DDRSS_PHY_937_DATA 0x00000000
+#define DDRSS_PHY_938_DATA 0x00000000
+#define DDRSS_PHY_939_DATA 0x00000000
+#define DDRSS_PHY_940_DATA 0x00000000
+#define DDRSS_PHY_941_DATA 0x00000000
+#define DDRSS_PHY_942_DATA 0x00000000
+#define DDRSS_PHY_943_DATA 0x00000000
+#define DDRSS_PHY_944_DATA 0x00000000
+#define DDRSS_PHY_945_DATA 0x00000000
+#define DDRSS_PHY_946_DATA 0x00000000
+#define DDRSS_PHY_947_DATA 0x00000000
+#define DDRSS_PHY_948_DATA 0x00000000
+#define DDRSS_PHY_949_DATA 0x00000000
+#define DDRSS_PHY_950_DATA 0x00000000
+#define DDRSS_PHY_951_DATA 0x00000000
+#define DDRSS_PHY_952_DATA 0x00000000
+#define DDRSS_PHY_953_DATA 0x00000000
+#define DDRSS_PHY_954_DATA 0x00000000
+#define DDRSS_PHY_955_DATA 0x00000000
+#define DDRSS_PHY_956_DATA 0x00000000
+#define DDRSS_PHY_957_DATA 0x00000000
+#define DDRSS_PHY_958_DATA 0x00000000
+#define DDRSS_PHY_959_DATA 0x00000000
+#define DDRSS_PHY_960_DATA 0x00000000
+#define DDRSS_PHY_961_DATA 0x00000000
+#define DDRSS_PHY_962_DATA 0x00000000
+#define DDRSS_PHY_963_DATA 0x00000000
+#define DDRSS_PHY_964_DATA 0x00000000
+#define DDRSS_PHY_965_DATA 0x00000000
+#define DDRSS_PHY_966_DATA 0x00000000
+#define DDRSS_PHY_967_DATA 0x00000000
+#define DDRSS_PHY_968_DATA 0x00000000
+#define DDRSS_PHY_969_DATA 0x00000000
+#define DDRSS_PHY_970_DATA 0x00000000
+#define DDRSS_PHY_971_DATA 0x00000000
+#define DDRSS_PHY_972_DATA 0x00000000
+#define DDRSS_PHY_973_DATA 0x00000000
+#define DDRSS_PHY_974_DATA 0x00000000
+#define DDRSS_PHY_975_DATA 0x00000000
+#define DDRSS_PHY_976_DATA 0x00000000
+#define DDRSS_PHY_977_DATA 0x00000000
+#define DDRSS_PHY_978_DATA 0x00000000
+#define DDRSS_PHY_979_DATA 0x00000000
+#define DDRSS_PHY_980_DATA 0x00000000
+#define DDRSS_PHY_981_DATA 0x00000000
+#define DDRSS_PHY_982_DATA 0x00000000
+#define DDRSS_PHY_983_DATA 0x00000000
+#define DDRSS_PHY_984_DATA 0x00000000
+#define DDRSS_PHY_985_DATA 0x00000000
+#define DDRSS_PHY_986_DATA 0x00000000
+#define DDRSS_PHY_987_DATA 0x00000000
+#define DDRSS_PHY_988_DATA 0x00000000
+#define DDRSS_PHY_989_DATA 0x00000000
+#define DDRSS_PHY_990_DATA 0x00000000
+#define DDRSS_PHY_991_DATA 0x00000000
+#define DDRSS_PHY_992_DATA 0x00000000
+#define DDRSS_PHY_993_DATA 0x00000000
+#define DDRSS_PHY_994_DATA 0x00000000
+#define DDRSS_PHY_995_DATA 0x00000000
+#define DDRSS_PHY_996_DATA 0x00000000
+#define DDRSS_PHY_997_DATA 0x00000000
+#define DDRSS_PHY_998_DATA 0x00000000
+#define DDRSS_PHY_999_DATA 0x00000000
+#define DDRSS_PHY_1000_DATA 0x00000000
+#define DDRSS_PHY_1001_DATA 0x00000000
+#define DDRSS_PHY_1002_DATA 0x00000000
+#define DDRSS_PHY_1003_DATA 0x00000000
+#define DDRSS_PHY_1004_DATA 0x00000000
+#define DDRSS_PHY_1005_DATA 0x00000000
+#define DDRSS_PHY_1006_DATA 0x00000000
+#define DDRSS_PHY_1007_DATA 0x00000000
+#define DDRSS_PHY_1008_DATA 0x00000000
+#define DDRSS_PHY_1009_DATA 0x00000000
+#define DDRSS_PHY_1010_DATA 0x00000000
+#define DDRSS_PHY_1011_DATA 0x00000000
+#define DDRSS_PHY_1012_DATA 0x00000000
+#define DDRSS_PHY_1013_DATA 0x00000000
+#define DDRSS_PHY_1014_DATA 0x00000000
+#define DDRSS_PHY_1015_DATA 0x00000000
+#define DDRSS_PHY_1016_DATA 0x00000000
+#define DDRSS_PHY_1017_DATA 0x00000000
+#define DDRSS_PHY_1018_DATA 0x00000000
+#define DDRSS_PHY_1019_DATA 0x00000000
+#define DDRSS_PHY_1020_DATA 0x00000000
+#define DDRSS_PHY_1021_DATA 0x00000000
+#define DDRSS_PHY_1022_DATA 0x00000000
+#define DDRSS_PHY_1023_DATA 0x00000000
+#define DDRSS_PHY_1024_DATA 0x00000000
+#define DDRSS_PHY_1025_DATA 0x00000000
+#define DDRSS_PHY_1026_DATA 0x00000000
+#define DDRSS_PHY_1027_DATA 0x00000000
+#define DDRSS_PHY_1028_DATA 0x00000000
+#define DDRSS_PHY_1029_DATA 0x00000100
+#define DDRSS_PHY_1030_DATA 0x00000200
+#define DDRSS_PHY_1031_DATA 0x00000000
+#define DDRSS_PHY_1032_DATA 0x00000000
+#define DDRSS_PHY_1033_DATA 0x00000000
+#define DDRSS_PHY_1034_DATA 0x00000000
+#define DDRSS_PHY_1035_DATA 0x00400000
+#define DDRSS_PHY_1036_DATA 0x00000080
+#define DDRSS_PHY_1037_DATA 0x00DCBA98
+#define DDRSS_PHY_1038_DATA 0x03000000
+#define DDRSS_PHY_1039_DATA 0x00200000
+#define DDRSS_PHY_1040_DATA 0x00000000
+#define DDRSS_PHY_1041_DATA 0x00000000
+#define DDRSS_PHY_1042_DATA 0x00000000
+#define DDRSS_PHY_1043_DATA 0x00000000
+#define DDRSS_PHY_1044_DATA 0x00000000
+#define DDRSS_PHY_1045_DATA 0x0000002A
+#define DDRSS_PHY_1046_DATA 0x00000015
+#define DDRSS_PHY_1047_DATA 0x00000015
+#define DDRSS_PHY_1048_DATA 0x0000002A
+#define DDRSS_PHY_1049_DATA 0x00000033
+#define DDRSS_PHY_1050_DATA 0x0000000C
+#define DDRSS_PHY_1051_DATA 0x0000000C
+#define DDRSS_PHY_1052_DATA 0x00000033
+#define DDRSS_PHY_1053_DATA 0x0A418820
+#define DDRSS_PHY_1054_DATA 0x003F0000
+#define DDRSS_PHY_1055_DATA 0x000F013F
+#define DDRSS_PHY_1056_DATA 0x20202003
+#define DDRSS_PHY_1057_DATA 0x00202020
+#define DDRSS_PHY_1058_DATA 0x20008008
+#define DDRSS_PHY_1059_DATA 0x00000810
+#define DDRSS_PHY_1060_DATA 0x00000F00
+#define DDRSS_PHY_1061_DATA 0x000405CC
+#define DDRSS_PHY_1062_DATA 0x03000004
+#define DDRSS_PHY_1063_DATA 0x00030000
+#define DDRSS_PHY_1064_DATA 0x00000300
+#define DDRSS_PHY_1065_DATA 0x00000300
+#define DDRSS_PHY_1066_DATA 0x00000300
+#define DDRSS_PHY_1067_DATA 0x00000300
+#define DDRSS_PHY_1068_DATA 0x42080010
+#define DDRSS_PHY_1069_DATA 0x0000803E
+#define DDRSS_PHY_1070_DATA 0x00000001
+#define DDRSS_PHY_1071_DATA 0x01000002
+#define DDRSS_PHY_1072_DATA 0x00008000
+#define DDRSS_PHY_1073_DATA 0x00000000
+#define DDRSS_PHY_1074_DATA 0x00000000
+#define DDRSS_PHY_1075_DATA 0x00000000
+#define DDRSS_PHY_1076_DATA 0x00000000
+#define DDRSS_PHY_1077_DATA 0x00000000
+#define DDRSS_PHY_1078_DATA 0x00000000
+#define DDRSS_PHY_1079_DATA 0x00000000
+#define DDRSS_PHY_1080_DATA 0x00000000
+#define DDRSS_PHY_1081_DATA 0x00000000
+#define DDRSS_PHY_1082_DATA 0x00000000
+#define DDRSS_PHY_1083_DATA 0x00000000
+#define DDRSS_PHY_1084_DATA 0x00000000
+#define DDRSS_PHY_1085_DATA 0x00000000
+#define DDRSS_PHY_1086_DATA 0x00000000
+#define DDRSS_PHY_1087_DATA 0x00000000
+#define DDRSS_PHY_1088_DATA 0x00000000
+#define DDRSS_PHY_1089_DATA 0x00000000
+#define DDRSS_PHY_1090_DATA 0x00000000
+#define DDRSS_PHY_1091_DATA 0x00000000
+#define DDRSS_PHY_1092_DATA 0x00000000
+#define DDRSS_PHY_1093_DATA 0x00000000
+#define DDRSS_PHY_1094_DATA 0x00000000
+#define DDRSS_PHY_1095_DATA 0x00000000
+#define DDRSS_PHY_1096_DATA 0x00000000
+#define DDRSS_PHY_1097_DATA 0x00000000
+#define DDRSS_PHY_1098_DATA 0x00000000
+#define DDRSS_PHY_1099_DATA 0x00000000
+#define DDRSS_PHY_1100_DATA 0x00000000
+#define DDRSS_PHY_1101_DATA 0x00000000
+#define DDRSS_PHY_1102_DATA 0x00000000
+#define DDRSS_PHY_1103_DATA 0x00000000
+#define DDRSS_PHY_1104_DATA 0x00000000
+#define DDRSS_PHY_1105_DATA 0x00000000
+#define DDRSS_PHY_1106_DATA 0x00000000
+#define DDRSS_PHY_1107_DATA 0x00000000
+#define DDRSS_PHY_1108_DATA 0x00000000
+#define DDRSS_PHY_1109_DATA 0x00000000
+#define DDRSS_PHY_1110_DATA 0x00000000
+#define DDRSS_PHY_1111_DATA 0x00000000
+#define DDRSS_PHY_1112_DATA 0x00000000
+#define DDRSS_PHY_1113_DATA 0x00000000
+#define DDRSS_PHY_1114_DATA 0x00000000
+#define DDRSS_PHY_1115_DATA 0x00000000
+#define DDRSS_PHY_1116_DATA 0x00000000
+#define DDRSS_PHY_1117_DATA 0x00000000
+#define DDRSS_PHY_1118_DATA 0x00000000
+#define DDRSS_PHY_1119_DATA 0x00000000
+#define DDRSS_PHY_1120_DATA 0x00000000
+#define DDRSS_PHY_1121_DATA 0x00000000
+#define DDRSS_PHY_1122_DATA 0x00000000
+#define DDRSS_PHY_1123_DATA 0x00000000
+#define DDRSS_PHY_1124_DATA 0x00000000
+#define DDRSS_PHY_1125_DATA 0x00000000
+#define DDRSS_PHY_1126_DATA 0x00000000
+#define DDRSS_PHY_1127_DATA 0x00000000
+#define DDRSS_PHY_1128_DATA 0x00000000
+#define DDRSS_PHY_1129_DATA 0x00000000
+#define DDRSS_PHY_1130_DATA 0x00000000
+#define DDRSS_PHY_1131_DATA 0x00000000
+#define DDRSS_PHY_1132_DATA 0x00000000
+#define DDRSS_PHY_1133_DATA 0x00000000
+#define DDRSS_PHY_1134_DATA 0x00000000
+#define DDRSS_PHY_1135_DATA 0x00000000
+#define DDRSS_PHY_1136_DATA 0x00000000
+#define DDRSS_PHY_1137_DATA 0x00000000
+#define DDRSS_PHY_1138_DATA 0x00000000
+#define DDRSS_PHY_1139_DATA 0x00000000
+#define DDRSS_PHY_1140_DATA 0x00000000
+#define DDRSS_PHY_1141_DATA 0x00000000
+#define DDRSS_PHY_1142_DATA 0x00000000
+#define DDRSS_PHY_1143_DATA 0x00000000
+#define DDRSS_PHY_1144_DATA 0x00000000
+#define DDRSS_PHY_1145_DATA 0x00000000
+#define DDRSS_PHY_1146_DATA 0x00000000
+#define DDRSS_PHY_1147_DATA 0x00000000
+#define DDRSS_PHY_1148_DATA 0x00000000
+#define DDRSS_PHY_1149_DATA 0x00000000
+#define DDRSS_PHY_1150_DATA 0x00000000
+#define DDRSS_PHY_1151_DATA 0x00000000
+#define DDRSS_PHY_1152_DATA 0x00000000
+#define DDRSS_PHY_1153_DATA 0x00000000
+#define DDRSS_PHY_1154_DATA 0x00000000
+#define DDRSS_PHY_1155_DATA 0x00000000
+#define DDRSS_PHY_1156_DATA 0x00000000
+#define DDRSS_PHY_1157_DATA 0x00000000
+#define DDRSS_PHY_1158_DATA 0x00000000
+#define DDRSS_PHY_1159_DATA 0x00000000
+#define DDRSS_PHY_1160_DATA 0x00000000
+#define DDRSS_PHY_1161_DATA 0x00000000
+#define DDRSS_PHY_1162_DATA 0x00000000
+#define DDRSS_PHY_1163_DATA 0x00000000
+#define DDRSS_PHY_1164_DATA 0x00000000
+#define DDRSS_PHY_1165_DATA 0x00000000
+#define DDRSS_PHY_1166_DATA 0x00000000
+#define DDRSS_PHY_1167_DATA 0x00000000
+#define DDRSS_PHY_1168_DATA 0x00000000
+#define DDRSS_PHY_1169_DATA 0x00000000
+#define DDRSS_PHY_1170_DATA 0x00000000
+#define DDRSS_PHY_1171_DATA 0x00000000
+#define DDRSS_PHY_1172_DATA 0x00000000
+#define DDRSS_PHY_1173_DATA 0x00000000
+#define DDRSS_PHY_1174_DATA 0x00000000
+#define DDRSS_PHY_1175_DATA 0x00000000
+#define DDRSS_PHY_1176_DATA 0x00000000
+#define DDRSS_PHY_1177_DATA 0x00000000
+#define DDRSS_PHY_1178_DATA 0x00000000
+#define DDRSS_PHY_1179_DATA 0x00000000
+#define DDRSS_PHY_1180_DATA 0x00000000
+#define DDRSS_PHY_1181_DATA 0x00000000
+#define DDRSS_PHY_1182_DATA 0x00000000
+#define DDRSS_PHY_1183_DATA 0x00000000
+#define DDRSS_PHY_1184_DATA 0x00000000
+#define DDRSS_PHY_1185_DATA 0x00000000
+#define DDRSS_PHY_1186_DATA 0x00000000
+#define DDRSS_PHY_1187_DATA 0x00000000
+#define DDRSS_PHY_1188_DATA 0x00000000
+#define DDRSS_PHY_1189_DATA 0x00000000
+#define DDRSS_PHY_1190_DATA 0x00000000
+#define DDRSS_PHY_1191_DATA 0x00000000
+#define DDRSS_PHY_1192_DATA 0x00000000
+#define DDRSS_PHY_1193_DATA 0x00000000
+#define DDRSS_PHY_1194_DATA 0x00000000
+#define DDRSS_PHY_1195_DATA 0x00000000
+#define DDRSS_PHY_1196_DATA 0x00000000
+#define DDRSS_PHY_1197_DATA 0x00000000
+#define DDRSS_PHY_1198_DATA 0x00000000
+#define DDRSS_PHY_1199_DATA 0x00000000
+#define DDRSS_PHY_1200_DATA 0x00000000
+#define DDRSS_PHY_1201_DATA 0x00000000
+#define DDRSS_PHY_1202_DATA 0x00000000
+#define DDRSS_PHY_1203_DATA 0x00000000
+#define DDRSS_PHY_1204_DATA 0x00000000
+#define DDRSS_PHY_1205_DATA 0x00000000
+#define DDRSS_PHY_1206_DATA 0x00000000
+#define DDRSS_PHY_1207_DATA 0x00000000
+#define DDRSS_PHY_1208_DATA 0x00000000
+#define DDRSS_PHY_1209_DATA 0x00000000
+#define DDRSS_PHY_1210_DATA 0x00000000
+#define DDRSS_PHY_1211_DATA 0x00000000
+#define DDRSS_PHY_1212_DATA 0x00000000
+#define DDRSS_PHY_1213_DATA 0x00000000
+#define DDRSS_PHY_1214_DATA 0x00000000
+#define DDRSS_PHY_1215_DATA 0x00000000
+#define DDRSS_PHY_1216_DATA 0x00000000
+#define DDRSS_PHY_1217_DATA 0x00000000
+#define DDRSS_PHY_1218_DATA 0x00000000
+#define DDRSS_PHY_1219_DATA 0x00000000
+#define DDRSS_PHY_1220_DATA 0x00000000
+#define DDRSS_PHY_1221_DATA 0x00000000
+#define DDRSS_PHY_1222_DATA 0x00000000
+#define DDRSS_PHY_1223_DATA 0x00000000
+#define DDRSS_PHY_1224_DATA 0x00000000
+#define DDRSS_PHY_1225_DATA 0x00000000
+#define DDRSS_PHY_1226_DATA 0x00000000
+#define DDRSS_PHY_1227_DATA 0x00000000
+#define DDRSS_PHY_1228_DATA 0x00000000
+#define DDRSS_PHY_1229_DATA 0x00000000
+#define DDRSS_PHY_1230_DATA 0x00000000
+#define DDRSS_PHY_1231_DATA 0x00000000
+#define DDRSS_PHY_1232_DATA 0x00000000
+#define DDRSS_PHY_1233_DATA 0x00000000
+#define DDRSS_PHY_1234_DATA 0x00000000
+#define DDRSS_PHY_1235_DATA 0x00000000
+#define DDRSS_PHY_1236_DATA 0x00000000
+#define DDRSS_PHY_1237_DATA 0x00000000
+#define DDRSS_PHY_1238_DATA 0x00000000
+#define DDRSS_PHY_1239_DATA 0x00000000
+#define DDRSS_PHY_1240_DATA 0x00000000
+#define DDRSS_PHY_1241_DATA 0x00000000
+#define DDRSS_PHY_1242_DATA 0x00000000
+#define DDRSS_PHY_1243_DATA 0x00000000
+#define DDRSS_PHY_1244_DATA 0x00000000
+#define DDRSS_PHY_1245_DATA 0x00000000
+#define DDRSS_PHY_1246_DATA 0x00000000
+#define DDRSS_PHY_1247_DATA 0x00000000
+#define DDRSS_PHY_1248_DATA 0x00000000
+#define DDRSS_PHY_1249_DATA 0x00000000
+#define DDRSS_PHY_1250_DATA 0x00000000
+#define DDRSS_PHY_1251_DATA 0x00000000
+#define DDRSS_PHY_1252_DATA 0x00000000
+#define DDRSS_PHY_1253_DATA 0x00000000
+#define DDRSS_PHY_1254_DATA 0x00000000
+#define DDRSS_PHY_1255_DATA 0x00000000
+#define DDRSS_PHY_1256_DATA 0x00000000
+#define DDRSS_PHY_1257_DATA 0x00000000
+#define DDRSS_PHY_1258_DATA 0x00000000
+#define DDRSS_PHY_1259_DATA 0x00000000
+#define DDRSS_PHY_1260_DATA 0x00000000
+#define DDRSS_PHY_1261_DATA 0x00000000
+#define DDRSS_PHY_1262_DATA 0x00000000
+#define DDRSS_PHY_1263_DATA 0x00000000
+#define DDRSS_PHY_1264_DATA 0x00000000
+#define DDRSS_PHY_1265_DATA 0x00000000
+#define DDRSS_PHY_1266_DATA 0x00000000
+#define DDRSS_PHY_1267_DATA 0x00000000
+#define DDRSS_PHY_1268_DATA 0x00000000
+#define DDRSS_PHY_1269_DATA 0x00000000
+#define DDRSS_PHY_1270_DATA 0x00000000
+#define DDRSS_PHY_1271_DATA 0x00000000
+#define DDRSS_PHY_1272_DATA 0x00000000
+#define DDRSS_PHY_1273_DATA 0x00000000
+#define DDRSS_PHY_1274_DATA 0x00000000
+#define DDRSS_PHY_1275_DATA 0x00000000
+#define DDRSS_PHY_1276_DATA 0x00000000
+#define DDRSS_PHY_1277_DATA 0x00000000
+#define DDRSS_PHY_1278_DATA 0x00000000
+#define DDRSS_PHY_1279_DATA 0x00000000
+#define DDRSS_PHY_1280_DATA 0x00000000
+#define DDRSS_PHY_1281_DATA 0x00000000
+#define DDRSS_PHY_1282_DATA 0x00000000
+#define DDRSS_PHY_1283_DATA 0x00000000
+#define DDRSS_PHY_1284_DATA 0x00000000
+#define DDRSS_PHY_1285_DATA 0x00000100
+#define DDRSS_PHY_1286_DATA 0x00000200
+#define DDRSS_PHY_1287_DATA 0x00000000
+#define DDRSS_PHY_1288_DATA 0x00000000
+#define DDRSS_PHY_1289_DATA 0x00000000
+#define DDRSS_PHY_1290_DATA 0x00000000
+#define DDRSS_PHY_1291_DATA 0x00400000
+#define DDRSS_PHY_1292_DATA 0x00000080
+#define DDRSS_PHY_1293_DATA 0x00DCBA98
+#define DDRSS_PHY_1294_DATA 0x03000000
+#define DDRSS_PHY_1295_DATA 0x00200000
+#define DDRSS_PHY_1296_DATA 0x00000000
+#define DDRSS_PHY_1297_DATA 0x00000000
+#define DDRSS_PHY_1298_DATA 0x00000000
+#define DDRSS_PHY_1299_DATA 0x00000000
+#define DDRSS_PHY_1300_DATA 0x00000000
+#define DDRSS_PHY_1301_DATA 0x0000002A
+#define DDRSS_PHY_1302_DATA 0x00000015
+#define DDRSS_PHY_1303_DATA 0x00000015
+#define DDRSS_PHY_1304_DATA 0x0000002A
+#define DDRSS_PHY_1305_DATA 0x00000033
+#define DDRSS_PHY_1306_DATA 0x0000000C
+#define DDRSS_PHY_1307_DATA 0x0000000C
+#define DDRSS_PHY_1308_DATA 0x00000033
+#define DDRSS_PHY_1309_DATA 0x0A418820
+#define DDRSS_PHY_1310_DATA 0x00000000
+#define DDRSS_PHY_1311_DATA 0x000F0000
+#define DDRSS_PHY_1312_DATA 0x20202003
+#define DDRSS_PHY_1313_DATA 0x00202020
+#define DDRSS_PHY_1314_DATA 0x20008008
+#define DDRSS_PHY_1315_DATA 0x00000810
+#define DDRSS_PHY_1316_DATA 0x00000F00
+#define DDRSS_PHY_1317_DATA 0x000405CC
+#define DDRSS_PHY_1318_DATA 0x03000004
+#define DDRSS_PHY_1319_DATA 0x00030000
+#define DDRSS_PHY_1320_DATA 0x00000300
+#define DDRSS_PHY_1321_DATA 0x00000300
+#define DDRSS_PHY_1322_DATA 0x00000300
+#define DDRSS_PHY_1323_DATA 0x00000300
+#define DDRSS_PHY_1324_DATA 0x42080010
+#define DDRSS_PHY_1325_DATA 0x0000803E
+#define DDRSS_PHY_1326_DATA 0x00000001
+#define DDRSS_PHY_1327_DATA 0x01000002
+#define DDRSS_PHY_1328_DATA 0x00008000
+#define DDRSS_PHY_1329_DATA 0x00000000
+#define DDRSS_PHY_1330_DATA 0x00000000
+#define DDRSS_PHY_1331_DATA 0x00000000
+#define DDRSS_PHY_1332_DATA 0x00000000
+#define DDRSS_PHY_1333_DATA 0x00000000
+#define DDRSS_PHY_1334_DATA 0x00000000
+#define DDRSS_PHY_1335_DATA 0x00000000
+#define DDRSS_PHY_1336_DATA 0x00000000
+#define DDRSS_PHY_1337_DATA 0x00000000
+#define DDRSS_PHY_1338_DATA 0x00000000
+#define DDRSS_PHY_1339_DATA 0x00000000
+#define DDRSS_PHY_1340_DATA 0x00000000
+#define DDRSS_PHY_1341_DATA 0x00000000
+#define DDRSS_PHY_1342_DATA 0x00000000
+#define DDRSS_PHY_1343_DATA 0x00000000
+#define DDRSS_PHY_1344_DATA 0x00000000
+#define DDRSS_PHY_1345_DATA 0x00000000
+#define DDRSS_PHY_1346_DATA 0x00000000
+#define DDRSS_PHY_1347_DATA 0x00000000
+#define DDRSS_PHY_1348_DATA 0x00000000
+#define DDRSS_PHY_1349_DATA 0x00000000
+#define DDRSS_PHY_1350_DATA 0x00000000
+#define DDRSS_PHY_1351_DATA 0x00000000
+#define DDRSS_PHY_1352_DATA 0x00000000
+#define DDRSS_PHY_1353_DATA 0x00000000
+#define DDRSS_PHY_1354_DATA 0x00000000
+#define DDRSS_PHY_1355_DATA 0x00000000
+#define DDRSS_PHY_1356_DATA 0x00000000
+#define DDRSS_PHY_1357_DATA 0x00000000
+#define DDRSS_PHY_1358_DATA 0x00000000
+#define DDRSS_PHY_1359_DATA 0x00000000
+#define DDRSS_PHY_1360_DATA 0x00000000
+#define DDRSS_PHY_1361_DATA 0x00000000
+#define DDRSS_PHY_1362_DATA 0x00000000
+#define DDRSS_PHY_1363_DATA 0x00000000
+#define DDRSS_PHY_1364_DATA 0x00000000
+#define DDRSS_PHY_1365_DATA 0x00000000
+#define DDRSS_PHY_1366_DATA 0x00000000
+#define DDRSS_PHY_1367_DATA 0x00000000
+#define DDRSS_PHY_1368_DATA 0x00000000
+#define DDRSS_PHY_1369_DATA 0x00000000
+#define DDRSS_PHY_1370_DATA 0x00000000
+#define DDRSS_PHY_1371_DATA 0x00000000
+#define DDRSS_PHY_1372_DATA 0x00000000
+#define DDRSS_PHY_1373_DATA 0x00000000
+#define DDRSS_PHY_1374_DATA 0x00000000
+#define DDRSS_PHY_1375_DATA 0x00000000
+#define DDRSS_PHY_1376_DATA 0x00000000
+#define DDRSS_PHY_1377_DATA 0x00000000
+#define DDRSS_PHY_1378_DATA 0x00000000
+#define DDRSS_PHY_1379_DATA 0x00000000
+#define DDRSS_PHY_1380_DATA 0x00000000
+#define DDRSS_PHY_1381_DATA 0x00000000
+#define DDRSS_PHY_1382_DATA 0x00000000
+#define DDRSS_PHY_1383_DATA 0x00000000
+#define DDRSS_PHY_1384_DATA 0x00000000
+#define DDRSS_PHY_1385_DATA 0x00000000
+#define DDRSS_PHY_1386_DATA 0x00000000
+#define DDRSS_PHY_1387_DATA 0x00000000
+#define DDRSS_PHY_1388_DATA 0x00000000
+#define DDRSS_PHY_1389_DATA 0x00000000
+#define DDRSS_PHY_1390_DATA 0x00000000
+#define DDRSS_PHY_1391_DATA 0x00000000
+#define DDRSS_PHY_1392_DATA 0x00000000
+#define DDRSS_PHY_1393_DATA 0x00000000
+#define DDRSS_PHY_1394_DATA 0x00000000
+#define DDRSS_PHY_1395_DATA 0x00000000
+#define DDRSS_PHY_1396_DATA 0x00000000
+#define DDRSS_PHY_1397_DATA 0x00000000
+#define DDRSS_PHY_1398_DATA 0x00000000
+#define DDRSS_PHY_1399_DATA 0x00000000
+#define DDRSS_PHY_1400_DATA 0x00000000
+#define DDRSS_PHY_1401_DATA 0x00000000
+#define DDRSS_PHY_1402_DATA 0x00000000
+#define DDRSS_PHY_1403_DATA 0x00000000
+#define DDRSS_PHY_1404_DATA 0x00000000
+#define DDRSS_PHY_1405_DATA 0x00000000
+#define DDRSS_PHY_1406_DATA 0x00000000
+#define DDRSS_PHY_1407_DATA 0x00000000
+#define DDRSS_PHY_1408_DATA 0x00000000
+#define DDRSS_PHY_1409_DATA 0x00000000
+#define DDRSS_PHY_1410_DATA 0x00000000
+#define DDRSS_PHY_1411_DATA 0x00000000
+#define DDRSS_PHY_1412_DATA 0x00000000
+#define DDRSS_PHY_1413_DATA 0x00000000
+#define DDRSS_PHY_1414_DATA 0x00000000
+#define DDRSS_PHY_1415_DATA 0x00000000
+#define DDRSS_PHY_1416_DATA 0x00000000
+#define DDRSS_PHY_1417_DATA 0x00000000
+#define DDRSS_PHY_1418_DATA 0x00000000
+#define DDRSS_PHY_1419_DATA 0x00000000
+#define DDRSS_PHY_1420_DATA 0x00000000
+#define DDRSS_PHY_1421_DATA 0x00000000
+#define DDRSS_PHY_1422_DATA 0x00000000
+#define DDRSS_PHY_1423_DATA 0x00000000
+#define DDRSS_PHY_1424_DATA 0x00000000
+#define DDRSS_PHY_1425_DATA 0x00000000
+#define DDRSS_PHY_1426_DATA 0x00000000
+#define DDRSS_PHY_1427_DATA 0x00000000
+#define DDRSS_PHY_1428_DATA 0x00000000
+#define DDRSS_PHY_1429_DATA 0x00000000
+#define DDRSS_PHY_1430_DATA 0x00000000
+#define DDRSS_PHY_1431_DATA 0x00000000
+#define DDRSS_PHY_1432_DATA 0x00000000
+#define DDRSS_PHY_1433_DATA 0x00000000
+#define DDRSS_PHY_1434_DATA 0x00000000
+#define DDRSS_PHY_1435_DATA 0x00000000
+#define DDRSS_PHY_1436_DATA 0x00000000
+#define DDRSS_PHY_1437_DATA 0x00000000
+#define DDRSS_PHY_1438_DATA 0x00000000
+#define DDRSS_PHY_1439_DATA 0x00000000
+#define DDRSS_PHY_1440_DATA 0x00000000
+#define DDRSS_PHY_1441_DATA 0x00000000
+#define DDRSS_PHY_1442_DATA 0x00000000
+#define DDRSS_PHY_1443_DATA 0x00000000
+#define DDRSS_PHY_1444_DATA 0x00000000
+#define DDRSS_PHY_1445_DATA 0x00000000
+#define DDRSS_PHY_1446_DATA 0x00000000
+#define DDRSS_PHY_1447_DATA 0x00000000
+#define DDRSS_PHY_1448_DATA 0x00000000
+#define DDRSS_PHY_1449_DATA 0x00000000
+#define DDRSS_PHY_1450_DATA 0x00000000
+#define DDRSS_PHY_1451_DATA 0x00000000
+#define DDRSS_PHY_1452_DATA 0x00000000
+#define DDRSS_PHY_1453_DATA 0x00000000
+#define DDRSS_PHY_1454_DATA 0x00000000
+#define DDRSS_PHY_1455_DATA 0x00000000
+#define DDRSS_PHY_1456_DATA 0x00000000
+#define DDRSS_PHY_1457_DATA 0x00000000
+#define DDRSS_PHY_1458_DATA 0x00000000
+#define DDRSS_PHY_1459_DATA 0x00000000
+#define DDRSS_PHY_1460_DATA 0x00000000
+#define DDRSS_PHY_1461_DATA 0x00000000
+#define DDRSS_PHY_1462_DATA 0x00000000
+#define DDRSS_PHY_1463_DATA 0x00000000
+#define DDRSS_PHY_1464_DATA 0x00000000
+#define DDRSS_PHY_1465_DATA 0x00000000
+#define DDRSS_PHY_1466_DATA 0x00000000
+#define DDRSS_PHY_1467_DATA 0x00000000
+#define DDRSS_PHY_1468_DATA 0x00000000
+#define DDRSS_PHY_1469_DATA 0x00000000
+#define DDRSS_PHY_1470_DATA 0x00000000
+#define DDRSS_PHY_1471_DATA 0x00000000
+#define DDRSS_PHY_1472_DATA 0x00000000
+#define DDRSS_PHY_1473_DATA 0x00000000
+#define DDRSS_PHY_1474_DATA 0x00000000
+#define DDRSS_PHY_1475_DATA 0x00000000
+#define DDRSS_PHY_1476_DATA 0x00000000
+#define DDRSS_PHY_1477_DATA 0x00000000
+#define DDRSS_PHY_1478_DATA 0x00000000
+#define DDRSS_PHY_1479_DATA 0x00000000
+#define DDRSS_PHY_1480_DATA 0x00000000
+#define DDRSS_PHY_1481_DATA 0x00000000
+#define DDRSS_PHY_1482_DATA 0x00000000
+#define DDRSS_PHY_1483_DATA 0x00000000
+#define DDRSS_PHY_1484_DATA 0x00000000
+#define DDRSS_PHY_1485_DATA 0x00000000
+#define DDRSS_PHY_1486_DATA 0x00000000
+#define DDRSS_PHY_1487_DATA 0x00000000
+#define DDRSS_PHY_1488_DATA 0x00000000
+#define DDRSS_PHY_1489_DATA 0x00000000
+#define DDRSS_PHY_1490_DATA 0x00000000
+#define DDRSS_PHY_1491_DATA 0x00000000
+#define DDRSS_PHY_1492_DATA 0x00000000
+#define DDRSS_PHY_1493_DATA 0x00000000
+#define DDRSS_PHY_1494_DATA 0x00000000
+#define DDRSS_PHY_1495_DATA 0x00000000
+#define DDRSS_PHY_1496_DATA 0x00000000
+#define DDRSS_PHY_1497_DATA 0x00000000
+#define DDRSS_PHY_1498_DATA 0x00000000
+#define DDRSS_PHY_1499_DATA 0x00000000
+#define DDRSS_PHY_1500_DATA 0x00000000
+#define DDRSS_PHY_1501_DATA 0x00000000
+#define DDRSS_PHY_1502_DATA 0x00000000
+#define DDRSS_PHY_1503_DATA 0x00000000
+#define DDRSS_PHY_1504_DATA 0x00000000
+#define DDRSS_PHY_1505_DATA 0x00000000
+#define DDRSS_PHY_1506_DATA 0x00000000
+#define DDRSS_PHY_1507_DATA 0x00000000
+#define DDRSS_PHY_1508_DATA 0x00000000
+#define DDRSS_PHY_1509_DATA 0x00000000
+#define DDRSS_PHY_1510_DATA 0x00000000
+#define DDRSS_PHY_1511_DATA 0x00000000
+#define DDRSS_PHY_1512_DATA 0x00000000
+#define DDRSS_PHY_1513_DATA 0x00000000
+#define DDRSS_PHY_1514_DATA 0x00000000
+#define DDRSS_PHY_1515_DATA 0x00000000
+#define DDRSS_PHY_1516_DATA 0x00000000
+#define DDRSS_PHY_1517_DATA 0x00000000
+#define DDRSS_PHY_1518_DATA 0x00000000
+#define DDRSS_PHY_1519_DATA 0x00000000
+#define DDRSS_PHY_1520_DATA 0x00000000
+#define DDRSS_PHY_1521_DATA 0x00000000
+#define DDRSS_PHY_1522_DATA 0x00000000
+#define DDRSS_PHY_1523_DATA 0x00000000
+#define DDRSS_PHY_1524_DATA 0x00000000
+#define DDRSS_PHY_1525_DATA 0x00000000
+#define DDRSS_PHY_1526_DATA 0x00000000
+#define DDRSS_PHY_1527_DATA 0x00000000
+#define DDRSS_PHY_1528_DATA 0x00000000
+#define DDRSS_PHY_1529_DATA 0x00000000
+#define DDRSS_PHY_1530_DATA 0x00000000
+#define DDRSS_PHY_1531_DATA 0x00000000
+#define DDRSS_PHY_1532_DATA 0x00000000
+#define DDRSS_PHY_1533_DATA 0x00000000
+#define DDRSS_PHY_1534_DATA 0x00000000
+#define DDRSS_PHY_1535_DATA 0x00000000
+#define DDRSS_PHY_1536_DATA 0x00000000
+#define DDRSS_PHY_1537_DATA 0x00000000
+#define DDRSS_PHY_1538_DATA 0x00000000
+#define DDRSS_PHY_1539_DATA 0x00000000
+#define DDRSS_PHY_1540_DATA 0x00000000
+#define DDRSS_PHY_1541_DATA 0x00000100
+#define DDRSS_PHY_1542_DATA 0x00000200
+#define DDRSS_PHY_1543_DATA 0x00000000
+#define DDRSS_PHY_1544_DATA 0x00000000
+#define DDRSS_PHY_1545_DATA 0x00000000
+#define DDRSS_PHY_1546_DATA 0x00000000
+#define DDRSS_PHY_1547_DATA 0x00400000
+#define DDRSS_PHY_1548_DATA 0x00000080
+#define DDRSS_PHY_1549_DATA 0x00DCBA98
+#define DDRSS_PHY_1550_DATA 0x03000000
+#define DDRSS_PHY_1551_DATA 0x00200000
+#define DDRSS_PHY_1552_DATA 0x00000000
+#define DDRSS_PHY_1553_DATA 0x00000000
+#define DDRSS_PHY_1554_DATA 0x00000000
+#define DDRSS_PHY_1555_DATA 0x00000000
+#define DDRSS_PHY_1556_DATA 0x00000000
+#define DDRSS_PHY_1557_DATA 0x0000002A
+#define DDRSS_PHY_1558_DATA 0x00000015
+#define DDRSS_PHY_1559_DATA 0x00000015
+#define DDRSS_PHY_1560_DATA 0x0000002A
+#define DDRSS_PHY_1561_DATA 0x00000033
+#define DDRSS_PHY_1562_DATA 0x0000000C
+#define DDRSS_PHY_1563_DATA 0x0000000C
+#define DDRSS_PHY_1564_DATA 0x00000033
+#define DDRSS_PHY_1565_DATA 0x0A418820
+#define DDRSS_PHY_1566_DATA 0x10000000
+#define DDRSS_PHY_1567_DATA 0x000F0000
+#define DDRSS_PHY_1568_DATA 0x20202003
+#define DDRSS_PHY_1569_DATA 0x00202020
+#define DDRSS_PHY_1570_DATA 0x20008008
+#define DDRSS_PHY_1571_DATA 0x00000810
+#define DDRSS_PHY_1572_DATA 0x00000F00
+#define DDRSS_PHY_1573_DATA 0x000405CC
+#define DDRSS_PHY_1574_DATA 0x03000004
+#define DDRSS_PHY_1575_DATA 0x00030000
+#define DDRSS_PHY_1576_DATA 0x00000300
+#define DDRSS_PHY_1577_DATA 0x00000300
+#define DDRSS_PHY_1578_DATA 0x00000300
+#define DDRSS_PHY_1579_DATA 0x00000300
+#define DDRSS_PHY_1580_DATA 0x42080010
+#define DDRSS_PHY_1581_DATA 0x0000803E
+#define DDRSS_PHY_1582_DATA 0x00000001
+#define DDRSS_PHY_1583_DATA 0x01000002
+#define DDRSS_PHY_1584_DATA 0x00008000
+#define DDRSS_PHY_1585_DATA 0x00000000
+#define DDRSS_PHY_1586_DATA 0x00000000
+#define DDRSS_PHY_1587_DATA 0x00000000
+#define DDRSS_PHY_1588_DATA 0x00000000
+#define DDRSS_PHY_1589_DATA 0x00000000
+#define DDRSS_PHY_1590_DATA 0x00000000
+#define DDRSS_PHY_1591_DATA 0x00000000
+#define DDRSS_PHY_1592_DATA 0x00000000
+#define DDRSS_PHY_1593_DATA 0x00000000
+#define DDRSS_PHY_1594_DATA 0x00000000
+#define DDRSS_PHY_1595_DATA 0x00000000
+#define DDRSS_PHY_1596_DATA 0x00000000
+#define DDRSS_PHY_1597_DATA 0x00000000
+#define DDRSS_PHY_1598_DATA 0x00000000
+#define DDRSS_PHY_1599_DATA 0x00000000
+#define DDRSS_PHY_1600_DATA 0x00000000
+#define DDRSS_PHY_1601_DATA 0x00000000
+#define DDRSS_PHY_1602_DATA 0x00000000
+#define DDRSS_PHY_1603_DATA 0x00000000
+#define DDRSS_PHY_1604_DATA 0x00000000
+#define DDRSS_PHY_1605_DATA 0x00000000
+#define DDRSS_PHY_1606_DATA 0x00000000
+#define DDRSS_PHY_1607_DATA 0x00000000
+#define DDRSS_PHY_1608_DATA 0x00000000
+#define DDRSS_PHY_1609_DATA 0x00000000
+#define DDRSS_PHY_1610_DATA 0x00000000
+#define DDRSS_PHY_1611_DATA 0x00000000
+#define DDRSS_PHY_1612_DATA 0x00000000
+#define DDRSS_PHY_1613_DATA 0x00000000
+#define DDRSS_PHY_1614_DATA 0x00000000
+#define DDRSS_PHY_1615_DATA 0x00000000
+#define DDRSS_PHY_1616_DATA 0x00000000
+#define DDRSS_PHY_1617_DATA 0x00000000
+#define DDRSS_PHY_1618_DATA 0x00000000
+#define DDRSS_PHY_1619_DATA 0x00000000
+#define DDRSS_PHY_1620_DATA 0x00000000
+#define DDRSS_PHY_1621_DATA 0x00000000
+#define DDRSS_PHY_1622_DATA 0x00000000
+#define DDRSS_PHY_1623_DATA 0x00000000
+#define DDRSS_PHY_1624_DATA 0x00000000
+#define DDRSS_PHY_1625_DATA 0x00000000
+#define DDRSS_PHY_1626_DATA 0x00000000
+#define DDRSS_PHY_1627_DATA 0x00000000
+#define DDRSS_PHY_1628_DATA 0x00000000
+#define DDRSS_PHY_1629_DATA 0x00000000
+#define DDRSS_PHY_1630_DATA 0x00000000
+#define DDRSS_PHY_1631_DATA 0x00000000
+#define DDRSS_PHY_1632_DATA 0x00000000
+#define DDRSS_PHY_1633_DATA 0x00000000
+#define DDRSS_PHY_1634_DATA 0x00000000
+#define DDRSS_PHY_1635_DATA 0x00000000
+#define DDRSS_PHY_1636_DATA 0x00000000
+#define DDRSS_PHY_1637_DATA 0x00000000
+#define DDRSS_PHY_1638_DATA 0x00000000
+#define DDRSS_PHY_1639_DATA 0x00000000
+#define DDRSS_PHY_1640_DATA 0x00000000
+#define DDRSS_PHY_1641_DATA 0x00000000
+#define DDRSS_PHY_1642_DATA 0x00000000
+#define DDRSS_PHY_1643_DATA 0x00000000
+#define DDRSS_PHY_1644_DATA 0x00000000
+#define DDRSS_PHY_1645_DATA 0x00000000
+#define DDRSS_PHY_1646_DATA 0x00000000
+#define DDRSS_PHY_1647_DATA 0x00000000
+#define DDRSS_PHY_1648_DATA 0x00000000
+#define DDRSS_PHY_1649_DATA 0x00000000
+#define DDRSS_PHY_1650_DATA 0x00000000
+#define DDRSS_PHY_1651_DATA 0x00000000
+#define DDRSS_PHY_1652_DATA 0x00000000
+#define DDRSS_PHY_1653_DATA 0x00000000
+#define DDRSS_PHY_1654_DATA 0x00000000
+#define DDRSS_PHY_1655_DATA 0x00000000
+#define DDRSS_PHY_1656_DATA 0x00000000
+#define DDRSS_PHY_1657_DATA 0x00000000
+#define DDRSS_PHY_1658_DATA 0x00000000
+#define DDRSS_PHY_1659_DATA 0x00000000
+#define DDRSS_PHY_1660_DATA 0x00000000
+#define DDRSS_PHY_1661_DATA 0x00000000
+#define DDRSS_PHY_1662_DATA 0x00000000
+#define DDRSS_PHY_1663_DATA 0x00000000
+#define DDRSS_PHY_1664_DATA 0x00000000
+#define DDRSS_PHY_1665_DATA 0x00000000
+#define DDRSS_PHY_1666_DATA 0x00000000
+#define DDRSS_PHY_1667_DATA 0x00000000
+#define DDRSS_PHY_1668_DATA 0x00000000
+#define DDRSS_PHY_1669_DATA 0x00000000
+#define DDRSS_PHY_1670_DATA 0x00000000
+#define DDRSS_PHY_1671_DATA 0x00000000
+#define DDRSS_PHY_1672_DATA 0x00000000
+#define DDRSS_PHY_1673_DATA 0x00000000
+#define DDRSS_PHY_1674_DATA 0x00000000
+#define DDRSS_PHY_1675_DATA 0x00000000
+#define DDRSS_PHY_1676_DATA 0x00000000
+#define DDRSS_PHY_1677_DATA 0x00000000
+#define DDRSS_PHY_1678_DATA 0x00000000
+#define DDRSS_PHY_1679_DATA 0x00000000
+#define DDRSS_PHY_1680_DATA 0x00000000
+#define DDRSS_PHY_1681_DATA 0x00000000
+#define DDRSS_PHY_1682_DATA 0x00000000
+#define DDRSS_PHY_1683_DATA 0x00000000
+#define DDRSS_PHY_1684_DATA 0x00000000
+#define DDRSS_PHY_1685_DATA 0x00000000
+#define DDRSS_PHY_1686_DATA 0x00000000
+#define DDRSS_PHY_1687_DATA 0x00000000
+#define DDRSS_PHY_1688_DATA 0x00000000
+#define DDRSS_PHY_1689_DATA 0x00000000
+#define DDRSS_PHY_1690_DATA 0x00000000
+#define DDRSS_PHY_1691_DATA 0x00000000
+#define DDRSS_PHY_1692_DATA 0x00000000
+#define DDRSS_PHY_1693_DATA 0x00000000
+#define DDRSS_PHY_1694_DATA 0x00000000
+#define DDRSS_PHY_1695_DATA 0x00000000
+#define DDRSS_PHY_1696_DATA 0x00000000
+#define DDRSS_PHY_1697_DATA 0x00000000
+#define DDRSS_PHY_1698_DATA 0x00000000
+#define DDRSS_PHY_1699_DATA 0x00000000
+#define DDRSS_PHY_1700_DATA 0x00000000
+#define DDRSS_PHY_1701_DATA 0x00000000
+#define DDRSS_PHY_1702_DATA 0x00000000
+#define DDRSS_PHY_1703_DATA 0x00000000
+#define DDRSS_PHY_1704_DATA 0x00000000
+#define DDRSS_PHY_1705_DATA 0x00000000
+#define DDRSS_PHY_1706_DATA 0x00000000
+#define DDRSS_PHY_1707_DATA 0x00000000
+#define DDRSS_PHY_1708_DATA 0x00000000
+#define DDRSS_PHY_1709_DATA 0x00000000
+#define DDRSS_PHY_1710_DATA 0x00000000
+#define DDRSS_PHY_1711_DATA 0x00000000
+#define DDRSS_PHY_1712_DATA 0x00000000
+#define DDRSS_PHY_1713_DATA 0x00000000
+#define DDRSS_PHY_1714_DATA 0x00000000
+#define DDRSS_PHY_1715_DATA 0x00000000
+#define DDRSS_PHY_1716_DATA 0x00000000
+#define DDRSS_PHY_1717_DATA 0x00000000
+#define DDRSS_PHY_1718_DATA 0x00000000
+#define DDRSS_PHY_1719_DATA 0x00000000
+#define DDRSS_PHY_1720_DATA 0x00000000
+#define DDRSS_PHY_1721_DATA 0x00000000
+#define DDRSS_PHY_1722_DATA 0x00000000
+#define DDRSS_PHY_1723_DATA 0x00000000
+#define DDRSS_PHY_1724_DATA 0x00000000
+#define DDRSS_PHY_1725_DATA 0x00000000
+#define DDRSS_PHY_1726_DATA 0x00000000
+#define DDRSS_PHY_1727_DATA 0x00000000
+#define DDRSS_PHY_1728_DATA 0x00000000
+#define DDRSS_PHY_1729_DATA 0x00000000
+#define DDRSS_PHY_1730_DATA 0x00000000
+#define DDRSS_PHY_1731_DATA 0x00000000
+#define DDRSS_PHY_1732_DATA 0x00000000
+#define DDRSS_PHY_1733_DATA 0x00000000
+#define DDRSS_PHY_1734_DATA 0x00000000
+#define DDRSS_PHY_1735_DATA 0x00000000
+#define DDRSS_PHY_1736_DATA 0x00000000
+#define DDRSS_PHY_1737_DATA 0x00000000
+#define DDRSS_PHY_1738_DATA 0x00000000
+#define DDRSS_PHY_1739_DATA 0x00000000
+#define DDRSS_PHY_1740_DATA 0x00000000
+#define DDRSS_PHY_1741_DATA 0x00000000
+#define DDRSS_PHY_1742_DATA 0x00000000
+#define DDRSS_PHY_1743_DATA 0x00000000
+#define DDRSS_PHY_1744_DATA 0x00000000
+#define DDRSS_PHY_1745_DATA 0x00000000
+#define DDRSS_PHY_1746_DATA 0x00000000
+#define DDRSS_PHY_1747_DATA 0x00000000
+#define DDRSS_PHY_1748_DATA 0x00000000
+#define DDRSS_PHY_1749_DATA 0x00000000
+#define DDRSS_PHY_1750_DATA 0x00000000
+#define DDRSS_PHY_1751_DATA 0x00000000
+#define DDRSS_PHY_1752_DATA 0x00000000
+#define DDRSS_PHY_1753_DATA 0x00000000
+#define DDRSS_PHY_1754_DATA 0x00000000
+#define DDRSS_PHY_1755_DATA 0x00000000
+#define DDRSS_PHY_1756_DATA 0x00000000
+#define DDRSS_PHY_1757_DATA 0x00000000
+#define DDRSS_PHY_1758_DATA 0x00000000
+#define DDRSS_PHY_1759_DATA 0x00000000
+#define DDRSS_PHY_1760_DATA 0x00000000
+#define DDRSS_PHY_1761_DATA 0x00000000
+#define DDRSS_PHY_1762_DATA 0x00000000
+#define DDRSS_PHY_1763_DATA 0x00000000
+#define DDRSS_PHY_1764_DATA 0x00000000
+#define DDRSS_PHY_1765_DATA 0x00000000
+#define DDRSS_PHY_1766_DATA 0x00000000
+#define DDRSS_PHY_1767_DATA 0x00000000
+#define DDRSS_PHY_1768_DATA 0x00000000
+#define DDRSS_PHY_1769_DATA 0x00000000
+#define DDRSS_PHY_1770_DATA 0x00000000
+#define DDRSS_PHY_1771_DATA 0x00000000
+#define DDRSS_PHY_1772_DATA 0x00000000
+#define DDRSS_PHY_1773_DATA 0x00000000
+#define DDRSS_PHY_1774_DATA 0x00000000
+#define DDRSS_PHY_1775_DATA 0x00000000
+#define DDRSS_PHY_1776_DATA 0x00000000
+#define DDRSS_PHY_1777_DATA 0x00000000
+#define DDRSS_PHY_1778_DATA 0x00000000
+#define DDRSS_PHY_1779_DATA 0x00000000
+#define DDRSS_PHY_1780_DATA 0x00000000
+#define DDRSS_PHY_1781_DATA 0x00000000
+#define DDRSS_PHY_1782_DATA 0x00000000
+#define DDRSS_PHY_1783_DATA 0x00000000
+#define DDRSS_PHY_1784_DATA 0x00000000
+#define DDRSS_PHY_1785_DATA 0x00000000
+#define DDRSS_PHY_1786_DATA 0x00000000
+#define DDRSS_PHY_1787_DATA 0x00000000
+#define DDRSS_PHY_1788_DATA 0x00000000
+#define DDRSS_PHY_1789_DATA 0x00000000
+#define DDRSS_PHY_1790_DATA 0x00000000
+#define DDRSS_PHY_1791_DATA 0x00000000
+#define DDRSS_PHY_1792_DATA 0x00000000
+#define DDRSS_PHY_1793_DATA 0x00010100
+#define DDRSS_PHY_1794_DATA 0x00000000
+#define DDRSS_PHY_1795_DATA 0x00000000
+#define DDRSS_PHY_1796_DATA 0x00000000
+#define DDRSS_PHY_1797_DATA 0x00000000
+#define DDRSS_PHY_1798_DATA 0x00050000
+#define DDRSS_PHY_1799_DATA 0x04000000
+#define DDRSS_PHY_1800_DATA 0x00000055
+#define DDRSS_PHY_1801_DATA 0x00000000
+#define DDRSS_PHY_1802_DATA 0x00000000
+#define DDRSS_PHY_1803_DATA 0x00000000
+#define DDRSS_PHY_1804_DATA 0x00000000
+#define DDRSS_PHY_1805_DATA 0x00002001
+#define DDRSS_PHY_1806_DATA 0x00004003
+#define DDRSS_PHY_1807_DATA 0x50020028
+#define DDRSS_PHY_1808_DATA 0x01010000
+#define DDRSS_PHY_1809_DATA 0x80080001
+#define DDRSS_PHY_1810_DATA 0x10200000
+#define DDRSS_PHY_1811_DATA 0x00000008
+#define DDRSS_PHY_1812_DATA 0x00000000
+#define DDRSS_PHY_1813_DATA 0x06000000
+#define DDRSS_PHY_1814_DATA 0x010F0F0E
+#define DDRSS_PHY_1815_DATA 0x00040101
+#define DDRSS_PHY_1816_DATA 0x0000010F
+#define DDRSS_PHY_1817_DATA 0x00000000
+#define DDRSS_PHY_1818_DATA 0x00000064
+#define DDRSS_PHY_1819_DATA 0x00000000
+#define DDRSS_PHY_1820_DATA 0x00000000
+#define DDRSS_PHY_1821_DATA 0x0F0F0F0F
+#define DDRSS_PHY_1822_DATA 0x0F0F0F0F
+#define DDRSS_PHY_1823_DATA 0x0F0F0F0F
+#define DDRSS_PHY_1824_DATA 0x02010804
+#define DDRSS_PHY_1825_DATA 0x00800120
+#define DDRSS_PHY_1826_DATA 0x00041B42
+#define DDRSS_PHY_1827_DATA 0x00004201
+#define DDRSS_PHY_1828_DATA 0x00000000
+#define DDRSS_PHY_1829_DATA 0x00000000
+#define DDRSS_PHY_1830_DATA 0x00000000
+#define DDRSS_PHY_1831_DATA 0x00000000
+#define DDRSS_PHY_1832_DATA 0x00000000
+#define DDRSS_PHY_1833_DATA 0x00000000
+#define DDRSS_PHY_1834_DATA 0x03010100
+#define DDRSS_PHY_1835_DATA 0x00540007
+#define DDRSS_PHY_1836_DATA 0x000040A2
+#define DDRSS_PHY_1837_DATA 0x00024410
+#define DDRSS_PHY_1838_DATA 0x00004410
+#define DDRSS_PHY_1839_DATA 0x00004410
+#define DDRSS_PHY_1840_DATA 0x00004410
+#define DDRSS_PHY_1841_DATA 0x00004410
+#define DDRSS_PHY_1842_DATA 0x00004410
+#define DDRSS_PHY_1843_DATA 0x00004410
+#define DDRSS_PHY_1844_DATA 0x00004410
+#define DDRSS_PHY_1845_DATA 0x00004410
+#define DDRSS_PHY_1846_DATA 0x00004410
+#define DDRSS_PHY_1847_DATA 0x00000000
+#define DDRSS_PHY_1848_DATA 0x00000076
+#define DDRSS_PHY_1849_DATA 0x00000400
+#define DDRSS_PHY_1850_DATA 0x00000008
+#define DDRSS_PHY_1851_DATA 0x00000000
+#define DDRSS_PHY_1852_DATA 0x00000000
+#define DDRSS_PHY_1853_DATA 0x00000000
+#define DDRSS_PHY_1854_DATA 0x00000000
+#define DDRSS_PHY_1855_DATA 0x00000000
+#define DDRSS_PHY_1856_DATA 0x03000000
+#define DDRSS_PHY_1857_DATA 0x00000000
+#define DDRSS_PHY_1858_DATA 0x00000000
+#define DDRSS_PHY_1859_DATA 0x00000000
+#define DDRSS_PHY_1860_DATA 0x04102006
+#define DDRSS_PHY_1861_DATA 0x00041020
+#define DDRSS_PHY_1862_DATA 0x01C98C98
+#define DDRSS_PHY_1863_DATA 0x3F400000
+#define DDRSS_PHY_1864_DATA 0x3F3F1F3F
+#define DDRSS_PHY_1865_DATA 0x0000001F
+#define DDRSS_PHY_1866_DATA 0x00000000
+#define DDRSS_PHY_1867_DATA 0x00000000
+#define DDRSS_PHY_1868_DATA 0x00000000
+#define DDRSS_PHY_1869_DATA 0x00000001
+#define DDRSS_PHY_1870_DATA 0x00000000
+#define DDRSS_PHY_1871_DATA 0x00000000
+#define DDRSS_PHY_1872_DATA 0x00000000
+#define DDRSS_PHY_1873_DATA 0x00000000
+#define DDRSS_PHY_1874_DATA 0x76543210
+#define DDRSS_PHY_1875_DATA 0x06010198
+#define DDRSS_PHY_1876_DATA 0x00000000
+#define DDRSS_PHY_1877_DATA 0x00000000
+#define DDRSS_PHY_1878_DATA 0x00000000
+#define DDRSS_PHY_1879_DATA 0x00040700
+#define DDRSS_PHY_1880_DATA 0x00000000
+#define DDRSS_PHY_1881_DATA 0x00000000
+#define DDRSS_PHY_1882_DATA 0x00000000
+#define DDRSS_PHY_1883_DATA 0x00000000
+#define DDRSS_PHY_1884_DATA 0x00000000
+#define DDRSS_PHY_1885_DATA 0x00000002
+#define DDRSS_PHY_1886_DATA 0x00000000
+#define DDRSS_PHY_1887_DATA 0x00000000
+#define DDRSS_PHY_1888_DATA 0x0001F7C4
+#define DDRSS_PHY_1889_DATA 0x04000004
+#define DDRSS_PHY_1890_DATA 0x00000000
+#define DDRSS_PHY_1891_DATA 0x00001142
+#define DDRSS_PHY_1892_DATA 0x01020000
+#define DDRSS_PHY_1893_DATA 0x00000080
+#define DDRSS_PHY_1894_DATA 0x03900390
+#define DDRSS_PHY_1895_DATA 0x03900390
+#define DDRSS_PHY_1896_DATA 0x03900390
+#define DDRSS_PHY_1897_DATA 0x03900390
+#define DDRSS_PHY_1898_DATA 0x03000300
+#define DDRSS_PHY_1899_DATA 0x03000300
+#define DDRSS_PHY_1900_DATA 0x00000300
+#define DDRSS_PHY_1901_DATA 0x00000300
+#define DDRSS_PHY_1902_DATA 0x00000300
+#define DDRSS_PHY_1903_DATA 0x00000300
+#define DDRSS_PHY_1904_DATA 0x00000005
+#define DDRSS_PHY_1905_DATA 0x3183BF77
+#define DDRSS_PHY_1906_DATA 0x00000000
+#define DDRSS_PHY_1907_DATA 0x0C000DFF
+#define DDRSS_PHY_1908_DATA 0x30000DFF
+#define DDRSS_PHY_1909_DATA 0x3F0DFF11
+#define DDRSS_PHY_1910_DATA 0x00EF0000
+#define DDRSS_PHY_1911_DATA 0x780DFFCC
+#define DDRSS_PHY_1912_DATA 0x00000C11
+#define DDRSS_PHY_1913_DATA 0x00018011
+#define DDRSS_PHY_1914_DATA 0x0089FF00
+#define DDRSS_PHY_1915_DATA 0x000C3F11
+#define DDRSS_PHY_1916_DATA 0x01990000
+#define DDRSS_PHY_1917_DATA 0x000C3F11
+#define DDRSS_PHY_1918_DATA 0x01990000
+#define DDRSS_PHY_1919_DATA 0x3F0DFF11
+#define DDRSS_PHY_1920_DATA 0x00EF0000
+#define DDRSS_PHY_1921_DATA 0x00018011
+#define DDRSS_PHY_1922_DATA 0x0089FF00
+#define DDRSS_PHY_1923_DATA 0x20040006
diff --git a/arch/arm/dts/k3-am67a-r5-beagley-ai.dts b/arch/arm/dts/k3-am67a-r5-beagley-ai.dts
new file mode 100644
index 00000000000..664be358a97
--- /dev/null
+++ b/arch/arm/dts/k3-am67a-r5-beagley-ai.dts
@@ -0,0 +1,84 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * AM67A BeagleY-AI dts file for R5 SPL
+ *
+ * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2024 Robert Nelson, BeagleBoard.org Foundation
+ */
+
+#include "k3-am67a-beagley-ai.dts"
+#include "k3-am67a-beagley-ai-u-boot.dtsi"
+
+#include "k3-am67a-beagley-ddr-lp4.dtsi"
+#include "k3-am62a-ddr.dtsi"
+
+/ {
+	aliases {
+		remoteproc0 = &sysctrler;
+		remoteproc1 = &a53_0;
+		serial0 = &wkup_uart0;
+		serial2 = &main_uart0;
+	};
+
+	a53_0: a53@0 {
+		compatible = "ti,am654-rproc";
+		reg = <0x00 0x00a90000 0x00 0x10>;
+		power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>,
+			<&k3_pds 135 TI_SCI_PD_EXCLUSIVE>,
+			<&k3_pds 166 TI_SCI_PD_EXCLUSIVE>;
+		resets = <&k3_reset 135 0>;
+		clocks = <&k3_clks 61 0>;
+		assigned-clocks = <&k3_clks 61 0>, <&k3_clks 135 0>;
+		assigned-clock-parents = <&k3_clks 61 2>;
+		assigned-clock-rates = <200000000>, <1200000000>;
+		ti,sci = <&dmsc>;
+		ti,sci-proc-id = <32>;
+		ti,sci-host-id = <10>;
+		bootph-all;
+	};
+
+	dm_tifs: dm-tifs {
+		compatible = "ti,j721e-dm-sci";
+		ti,host-id = <36>;
+		ti,secure-host;
+		mbox-names = "rx", "tx";
+		mboxes= <&secure_proxy_main 22>,
+			<&secure_proxy_main 23>;
+		bootph-all;
+	};
+};
+
+&dmsc {
+	mboxes= <&secure_proxy_main 0>,
+		<&secure_proxy_main 1>,
+		<&secure_proxy_main 0>;
+	mbox-names = "rx", "tx", "notify";
+	ti,host-id = <35>;
+	ti,secure-host;
+};
+
+&cbass_main {
+	sa3_secproxy: secproxy@44880000 {
+		compatible = "ti,am654-secure-proxy";
+		#mbox-cells = <1>;
+		reg = <0x00 0x44880000 0x00 0x20000>,
+		      <0x00 0x44860000 0x00 0x20000>,
+		      <0x00 0x43600000 0x00 0x10000>;
+		reg-names = "rt", "scfg", "target_data";
+		bootph-all;
+	};
+
+	sysctrler: sysctrler {
+		compatible = "ti,am654-system-controller";
+		mboxes= <&secure_proxy_main 1>,
+			<&secure_proxy_main 0>,
+			<&sa3_secproxy 0>;
+		mbox-names = "tx", "rx", "boot_notify";
+		bootph-all;
+	};
+};
+
+/* WKUP UART0 is used for DM firmware logs */
+&wkup_uart0 {
+	status = "okay";
+};
diff --git a/arch/arm/dts/k3-am69-sk-u-boot.dtsi b/arch/arm/dts/k3-am69-sk-u-boot.dtsi
index 4a82d2fd222..2f119508e18 100644
--- a/arch/arm/dts/k3-am69-sk-u-boot.dtsi
+++ b/arch/arm/dts/k3-am69-sk-u-boot.dtsi
@@ -1,10 +1,109 @@
 // SPDX-License-Identifier: GPL-2.0-only
 /*
- * Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/
  */
 
+#define SPL_BOARD_DTB "spl/dts/ti/k3-am69-sk.dtb"
+#define BOARD_DESCRIPTION "k3-am69-sk"
+#define UBOOT_BOARD_DESCRIPTION "U-Boot for AM69 board"
+
 #include "k3-j784s4-binman.dtsi"
 
+#if defined(CONFIG_CPU_V7R)
+
+&binman {
+	tiboot3-am69-hs {
+		insert-template = <&tiboot3_j784s4_hs>;
+		filename = "tiboot3-j784s4-hs-evm.bin";
+	};
+
+	tiboot3-am69-hs-fs {
+		insert-template = <&tiboot3_j784s4_hs_fs>;
+		filename = "tiboot3-j784s4-hs-fs-evm.bin";
+		symlink = "tiboot3.bin";
+	};
+};
+
+&ti_fs_enc {
+	filename = "ti-sysfw/ti-fs-firmware-j784s4-hs-enc.bin";
+};
+
+&sysfw_inner_cert {
+	filename = "ti-sysfw/ti-fs-firmware-j784s4-hs-cert.bin";
+};
+
+&ti_fs_enc_fs {
+	filename = "ti-sysfw/ti-fs-firmware-j784s4-hs-fs-enc.bin";
+};
+
+&sysfw_inner_cert_fs {
+	filename = "ti-sysfw/ti-fs-firmware-j784s4-hs-fs-cert.bin";
+};
+
+#include "k3-binman-capsule-r5.dtsi"
+
+// Capsule update GUIDs in string form.  See j784s4_evm.h
+#define AM69_SK_TIBOOT3_IMAGE_GUID_STR "adf49ec5-61bb-4dbe-8b8d-39df4d7ebf46"
+
+&capsule_tiboot3 {
+	efi-capsule {
+		image-guid = AM69_SK_TIBOOT3_IMAGE_GUID_STR;
+
+		blob {
+			filename = "tiboot3-j784s4-hs-fs-evm.bin";
+		};
+	};
+};
+
+#else // CONFIG_ARM64
+
+&binman {
+	ti-dm {
+		filename = "ti-dm.bin";
+
+		blob-ext {
+			filename = "ti-dm/j784s4/ipc_echo_testb_mcu1_0_release_strip.xer5f";
+			optional;
+		};
+	};
+
+	tispl {
+		insert-template = <&ti_spl>;
+	};
+
+	u-boot {
+		insert-template = <&u_boot>;
+	};
+
+	tispl-unsigned {
+		insert-template = <&ti_spl_unsigned>;
+	};
+
+	u-boot-unsigned {
+		insert-template = <&u_boot_unsigned>;
+	};
+};
+
+#include "k3-binman-capsule.dtsi"
+
+// Capsule update GUIDs in string form.  See j784s4_evm.h
+#define AM69_SK_SPL_IMAGE_GUID_STR "787f0059-63a1-461c-a18e-9d838345fe8e"
+#define AM69_SK_UBOOT_IMAGE_GUID_STR "9300505d-6ec5-4ff8-99e4-5459a04be617"
+
+&capsule_tispl {
+	efi-capsule {
+		image-guid = AM69_SK_SPL_IMAGE_GUID_STR;
+	};
+};
+
+&capsule_uboot {
+	efi-capsule {
+		image-guid = AM69_SK_UBOOT_IMAGE_GUID_STR;
+	};
+};
+
+#endif
+
 / {
 	memory@80000000 {
 		bootph-all;
@@ -23,25 +122,3 @@
 	bootph-pre-ram;
 };
 
-#ifdef CONFIG_TARGET_J784S4_A72_EVM
-
-#define SPL_AM69_SK_DTB "spl/dts/ti/k3-am69-sk.dtb"
-#define AM69_SK_DTB "u-boot.dtb"
-
-&spl_j784s4_evm_dtb {
-	filename = SPL_AM69_SK_DTB;
-};
-
-&j784s4_evm_dtb {
-	filename = AM69_SK_DTB;
-};
-
-&spl_j784s4_evm_dtb_unsigned {
-	filename = SPL_AM69_SK_DTB;
-};
-
-&j784s4_evm_dtb_unsigned {
-	filename = AM69_SK_DTB;
-};
-
-#endif
diff --git a/arch/arm/dts/k3-j7200-binman.dtsi b/arch/arm/dts/k3-j7200-binman.dtsi
index ef7d4594f69..423badd7cb5 100644
--- a/arch/arm/dts/k3-j7200-binman.dtsi
+++ b/arch/arm/dts/k3-j7200-binman.dtsi
@@ -7,46 +7,6 @@
 
 #ifdef CONFIG_TARGET_J7200_R5_EVM
 
-&bcfg_yaml {
-	config = "board-cfg_j7200.yaml";
-};
-
-&rcfg_yaml {
-	config = "rm-cfg_j7200.yaml";
-};
-
-&pcfg_yaml {
-	config = "pm-cfg_j7200.yaml";
-};
-
-&scfg_yaml {
-	config = "sec-cfg_j7200.yaml";
-};
-
-&bcfg_yaml_tifs {
-	config = "board-cfg_j7200.yaml";
-};
-
-&rcfg_yaml_tifs {
-	config = "rm-cfg_j7200.yaml";
-};
-
-&pcfg_yaml_tifs {
-	config = "pm-cfg_j7200.yaml";
-};
-
-&scfg_yaml_tifs {
-	config = "sec-cfg_j7200.yaml";
-};
-
-&rcfg_yaml_dm {
-	config = "rm-cfg_j7200.yaml";
-};
-
-&pcfg_yaml_dm {
-	config = "pm-cfg_j7200.yaml";
-};
-
 &binman {
 	tiboot3-j7200-hs-evm.bin {
 		filename = "tiboot3-j7200-hs-evm.bin";
diff --git a/arch/arm/dts/k3-j7200-r5-common-proc-board.dts b/arch/arm/dts/k3-j7200-r5-common-proc-board.dts
index ecb1dd49c64..9ac29110324 100644
--- a/arch/arm/dts/k3-j7200-r5-common-proc-board.dts
+++ b/arch/arm/dts/k3-j7200-r5-common-proc-board.dts
@@ -120,3 +120,10 @@
 	vdd-supply-2 = <&buckb1>;
 	bootph-pre-ram;
 };
+
+&tps659414 {
+	esm: esm {
+		compatible = "ti,tps659413-esm";
+		bootph-pre-ram;
+	};
+};
diff --git a/arch/arm/dts/k3-j742s2-ddr-evm-lp4-4266.dtsi b/arch/arm/dts/k3-j742s2-ddr-evm-lp4-4266.dtsi
new file mode 100644
index 00000000000..a64d19b05f3
--- /dev/null
+++ b/arch/arm/dts/k3-j742s2-ddr-evm-lp4-4266.dtsi
@@ -0,0 +1,8756 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com/
+ * This file was generated by the Jacinto7_DDRSS_RegConfigTool, Revision: 0.9.0
+ */
+
+#define DDRSS_PLL_FHS_CNT 10
+#define DDRSS_PLL_FREQUENCY_0 27500000
+#define DDRSS_PLL_FREQUENCY_1 1066500000
+#define DDRSS_PLL_FREQUENCY_2 1066500000
+
+#define MULTI_DDR_CFG_INTRLV_GRAN 0
+#define MULTI_DDR_CFG_INTRLV_SIZE 11
+#define MULTI_DDR_CFG_ECC_ENABLE 0
+#define MULTI_DDR_CFG_HYBRID_SELECT 0
+#define MULTI_DDR_CFG_EMIFS_ACTIVE 3
+
+#define DDRSS0_CTL_00_DATA 0x00000B00
+#define DDRSS0_CTL_01_DATA 0x00000000
+#define DDRSS0_CTL_02_DATA 0x00000000
+#define DDRSS0_CTL_03_DATA 0x00000000
+#define DDRSS0_CTL_04_DATA 0x00000000
+#define DDRSS0_CTL_05_DATA 0x00000000
+#define DDRSS0_CTL_06_DATA 0x00000000
+#define DDRSS0_CTL_07_DATA 0x00002AF8
+#define DDRSS0_CTL_08_DATA 0x0001ADAF
+#define DDRSS0_CTL_09_DATA 0x00000005
+#define DDRSS0_CTL_10_DATA 0x0000006E
+#define DDRSS0_CTL_11_DATA 0x000681C8
+#define DDRSS0_CTL_12_DATA 0x004111C9
+#define DDRSS0_CTL_13_DATA 0x00000005
+#define DDRSS0_CTL_14_DATA 0x000010A9
+#define DDRSS0_CTL_15_DATA 0x000681C8
+#define DDRSS0_CTL_16_DATA 0x004111C9
+#define DDRSS0_CTL_17_DATA 0x00000005
+#define DDRSS0_CTL_18_DATA 0x000010A9
+#define DDRSS0_CTL_19_DATA 0x01010000
+#define DDRSS0_CTL_20_DATA 0x02011001
+#define DDRSS0_CTL_21_DATA 0x02010000
+#define DDRSS0_CTL_22_DATA 0x00020100
+#define DDRSS0_CTL_23_DATA 0x0000000B
+#define DDRSS0_CTL_24_DATA 0x0000001C
+#define DDRSS0_CTL_25_DATA 0x00000000
+#define DDRSS0_CTL_26_DATA 0x00000000
+#define DDRSS0_CTL_27_DATA 0x03020200
+#define DDRSS0_CTL_28_DATA 0x00005656
+#define DDRSS0_CTL_29_DATA 0x00100000
+#define DDRSS0_CTL_30_DATA 0x00000000
+#define DDRSS0_CTL_31_DATA 0x00000000
+#define DDRSS0_CTL_32_DATA 0x00000000
+#define DDRSS0_CTL_33_DATA 0x00000000
+#define DDRSS0_CTL_34_DATA 0x040C0000
+#define DDRSS0_CTL_35_DATA 0x12481248
+#define DDRSS0_CTL_36_DATA 0x00050804
+#define DDRSS0_CTL_37_DATA 0x09040008
+#define DDRSS0_CTL_38_DATA 0x15000204
+#define DDRSS0_CTL_39_DATA 0x1760008B
+#define DDRSS0_CTL_40_DATA 0x1500422B
+#define DDRSS0_CTL_41_DATA 0x1760008B
+#define DDRSS0_CTL_42_DATA 0x2000422B
+#define DDRSS0_CTL_43_DATA 0x000A0A09
+#define DDRSS0_CTL_44_DATA 0x0400078A
+#define DDRSS0_CTL_45_DATA 0x1E161104
+#define DDRSS0_CTL_46_DATA 0x10012458
+#define DDRSS0_CTL_47_DATA 0x1E161110
+#define DDRSS0_CTL_48_DATA 0x10012458
+#define DDRSS0_CTL_49_DATA 0x02030410
+#define DDRSS0_CTL_50_DATA 0x2C040500
+#define DDRSS0_CTL_51_DATA 0x08292C29
+#define DDRSS0_CTL_52_DATA 0x14000E0A
+#define DDRSS0_CTL_53_DATA 0x04010A0A
+#define DDRSS0_CTL_54_DATA 0x01010004
+#define DDRSS0_CTL_55_DATA 0x04545408
+#define DDRSS0_CTL_56_DATA 0x04313104
+#define DDRSS0_CTL_57_DATA 0x00003131
+#define DDRSS0_CTL_58_DATA 0x00010100
+#define DDRSS0_CTL_59_DATA 0x03010000
+#define DDRSS0_CTL_60_DATA 0x00001508
+#define DDRSS0_CTL_61_DATA 0x000000CE
+#define DDRSS0_CTL_62_DATA 0x0000032B
+#define DDRSS0_CTL_63_DATA 0x00002073
+#define DDRSS0_CTL_64_DATA 0x0000032B
+#define DDRSS0_CTL_65_DATA 0x00002073
+#define DDRSS0_CTL_66_DATA 0x00000005
+#define DDRSS0_CTL_67_DATA 0x00050000
+#define DDRSS0_CTL_68_DATA 0x00CB0012
+#define DDRSS0_CTL_69_DATA 0x00CB0408
+#define DDRSS0_CTL_70_DATA 0x00400408
+#define DDRSS0_CTL_71_DATA 0x00120103
+#define DDRSS0_CTL_72_DATA 0x00100005
+#define DDRSS0_CTL_73_DATA 0x2F080010
+#define DDRSS0_CTL_74_DATA 0x0505012F
+#define DDRSS0_CTL_75_DATA 0x0401030A
+#define DDRSS0_CTL_76_DATA 0x041E100B
+#define DDRSS0_CTL_77_DATA 0x100B0401
+#define DDRSS0_CTL_78_DATA 0x0001041E
+#define DDRSS0_CTL_79_DATA 0x00160016
+#define DDRSS0_CTL_80_DATA 0x033B033B
+#define DDRSS0_CTL_81_DATA 0x033B033B
+#define DDRSS0_CTL_82_DATA 0x03050505
+#define DDRSS0_CTL_83_DATA 0x03010303
+#define DDRSS0_CTL_84_DATA 0x200B100B
+#define DDRSS0_CTL_85_DATA 0x04041004
+#define DDRSS0_CTL_86_DATA 0x200B100B
+#define DDRSS0_CTL_87_DATA 0x04041004
+#define DDRSS0_CTL_88_DATA 0x03010000
+#define DDRSS0_CTL_89_DATA 0x00010000
+#define DDRSS0_CTL_90_DATA 0x00000000
+#define DDRSS0_CTL_91_DATA 0x00000000
+#define DDRSS0_CTL_92_DATA 0x01000000
+#define DDRSS0_CTL_93_DATA 0x80104002
+#define DDRSS0_CTL_94_DATA 0x00000000
+#define DDRSS0_CTL_95_DATA 0x00040005
+#define DDRSS0_CTL_96_DATA 0x00000000
+#define DDRSS0_CTL_97_DATA 0x00050000
+#define DDRSS0_CTL_98_DATA 0x00000004
+#define DDRSS0_CTL_99_DATA 0x00000000
+#define DDRSS0_CTL_100_DATA 0x00040005
+#define DDRSS0_CTL_101_DATA 0x00000000
+#define DDRSS0_CTL_102_DATA 0x00003380
+#define DDRSS0_CTL_103_DATA 0x00003380
+#define DDRSS0_CTL_104_DATA 0x00003380
+#define DDRSS0_CTL_105_DATA 0x00003380
+#define DDRSS0_CTL_106_DATA 0x00003380
+#define DDRSS0_CTL_107_DATA 0x00000000
+#define DDRSS0_CTL_108_DATA 0x000005A2
+#define DDRSS0_CTL_109_DATA 0x00081CC0
+#define DDRSS0_CTL_110_DATA 0x00081CC0
+#define DDRSS0_CTL_111_DATA 0x00081CC0
+#define DDRSS0_CTL_112_DATA 0x00081CC0
+#define DDRSS0_CTL_113_DATA 0x00081CC0
+#define DDRSS0_CTL_114_DATA 0x00000000
+#define DDRSS0_CTL_115_DATA 0x0000E325
+#define DDRSS0_CTL_116_DATA 0x00081CC0
+#define DDRSS0_CTL_117_DATA 0x00081CC0
+#define DDRSS0_CTL_118_DATA 0x00081CC0
+#define DDRSS0_CTL_119_DATA 0x00081CC0
+#define DDRSS0_CTL_120_DATA 0x00081CC0
+#define DDRSS0_CTL_121_DATA 0x00000000
+#define DDRSS0_CTL_122_DATA 0x0000E325
+#define DDRSS0_CTL_123_DATA 0x00000000
+#define DDRSS0_CTL_124_DATA 0x00000000
+#define DDRSS0_CTL_125_DATA 0x00000000
+#define DDRSS0_CTL_126_DATA 0x00000000
+#define DDRSS0_CTL_127_DATA 0x00000000
+#define DDRSS0_CTL_128_DATA 0x00000000
+#define DDRSS0_CTL_129_DATA 0x00000000
+#define DDRSS0_CTL_130_DATA 0x00000000
+#define DDRSS0_CTL_131_DATA 0x0B030500
+#define DDRSS0_CTL_132_DATA 0x00040B04
+#define DDRSS0_CTL_133_DATA 0x0A090000
+#define DDRSS0_CTL_134_DATA 0x0A090701
+#define DDRSS0_CTL_135_DATA 0x0900000E
+#define DDRSS0_CTL_136_DATA 0x0907010A
+#define DDRSS0_CTL_137_DATA 0x00000E0A
+#define DDRSS0_CTL_138_DATA 0x07010A09
+#define DDRSS0_CTL_139_DATA 0x000E0A09
+#define DDRSS0_CTL_140_DATA 0x07000401
+#define DDRSS0_CTL_141_DATA 0x00000000
+#define DDRSS0_CTL_142_DATA 0x00000000
+#define DDRSS0_CTL_143_DATA 0x00000000
+#define DDRSS0_CTL_144_DATA 0x00000000
+#define DDRSS0_CTL_145_DATA 0x00000000
+#define DDRSS0_CTL_146_DATA 0x00000000
+#define DDRSS0_CTL_147_DATA 0x00000000
+#define DDRSS0_CTL_148_DATA 0x08080000
+#define DDRSS0_CTL_149_DATA 0x01000000
+#define DDRSS0_CTL_150_DATA 0x800000C0
+#define DDRSS0_CTL_151_DATA 0x800000C0
+#define DDRSS0_CTL_152_DATA 0x800000C0
+#define DDRSS0_CTL_153_DATA 0x00000000
+#define DDRSS0_CTL_154_DATA 0x00001500
+#define DDRSS0_CTL_155_DATA 0x00000000
+#define DDRSS0_CTL_156_DATA 0x00000001
+#define DDRSS0_CTL_157_DATA 0x00000002
+#define DDRSS0_CTL_158_DATA 0x0000100E
+#define DDRSS0_CTL_159_DATA 0x00000000
+#define DDRSS0_CTL_160_DATA 0x00000000
+#define DDRSS0_CTL_161_DATA 0x00000000
+#define DDRSS0_CTL_162_DATA 0x00000000
+#define DDRSS0_CTL_163_DATA 0x00000000
+#define DDRSS0_CTL_164_DATA 0x000B0000
+#define DDRSS0_CTL_165_DATA 0x000E0006
+#define DDRSS0_CTL_166_DATA 0x000E0404
+#define DDRSS0_CTL_167_DATA 0x00D601AB
+#define DDRSS0_CTL_168_DATA 0x10100216
+#define DDRSS0_CTL_169_DATA 0x01AB0216
+#define DDRSS0_CTL_170_DATA 0x021600D6
+#define DDRSS0_CTL_171_DATA 0x02161010
+#define DDRSS0_CTL_172_DATA 0x00000000
+#define DDRSS0_CTL_173_DATA 0x00000000
+#define DDRSS0_CTL_174_DATA 0x00000000
+#define DDRSS0_CTL_175_DATA 0x3FF40084
+#define DDRSS0_CTL_176_DATA 0x33003FF4
+#define DDRSS0_CTL_177_DATA 0x00003333
+#define DDRSS0_CTL_178_DATA 0x35000000
+#define DDRSS0_CTL_179_DATA 0x27270035
+#define DDRSS0_CTL_180_DATA 0x0F0F0000
+#define DDRSS0_CTL_181_DATA 0x16000000
+#define DDRSS0_CTL_182_DATA 0x00841616
+#define DDRSS0_CTL_183_DATA 0x3FF43FF4
+#define DDRSS0_CTL_184_DATA 0x33333300
+#define DDRSS0_CTL_185_DATA 0x00000000
+#define DDRSS0_CTL_186_DATA 0x00353500
+#define DDRSS0_CTL_187_DATA 0x00002727
+#define DDRSS0_CTL_188_DATA 0x00000F0F
+#define DDRSS0_CTL_189_DATA 0x16161600
+#define DDRSS0_CTL_190_DATA 0x00000020
+#define DDRSS0_CTL_191_DATA 0x00000000
+#define DDRSS0_CTL_192_DATA 0x00000001
+#define DDRSS0_CTL_193_DATA 0x00000000
+#define DDRSS0_CTL_194_DATA 0x01000000
+#define DDRSS0_CTL_195_DATA 0x00000001
+#define DDRSS0_CTL_196_DATA 0x00000000
+#define DDRSS0_CTL_197_DATA 0x00000000
+#define DDRSS0_CTL_198_DATA 0x00000000
+#define DDRSS0_CTL_199_DATA 0x00000000
+#define DDRSS0_CTL_200_DATA 0x00000000
+#define DDRSS0_CTL_201_DATA 0x00000000
+#define DDRSS0_CTL_202_DATA 0x00000000
+#define DDRSS0_CTL_203_DATA 0x00000000
+#define DDRSS0_CTL_204_DATA 0x00000000
+#define DDRSS0_CTL_205_DATA 0x00000000
+#define DDRSS0_CTL_206_DATA 0x02000000
+#define DDRSS0_CTL_207_DATA 0x01080101
+#define DDRSS0_CTL_208_DATA 0x00000000
+#define DDRSS0_CTL_209_DATA 0x00000000
+#define DDRSS0_CTL_210_DATA 0x00000000
+#define DDRSS0_CTL_211_DATA 0x00000000
+#define DDRSS0_CTL_212_DATA 0x00000000
+#define DDRSS0_CTL_213_DATA 0x00000000
+#define DDRSS0_CTL_214_DATA 0x00000000
+#define DDRSS0_CTL_215_DATA 0x00000000
+#define DDRSS0_CTL_216_DATA 0x00000000
+#define DDRSS0_CTL_217_DATA 0x00000000
+#define DDRSS0_CTL_218_DATA 0x00000000
+#define DDRSS0_CTL_219_DATA 0x00000000
+#define DDRSS0_CTL_220_DATA 0x00000000
+#define DDRSS0_CTL_221_DATA 0x00000000
+#define DDRSS0_CTL_222_DATA 0x00001000
+#define DDRSS0_CTL_223_DATA 0x006403E8
+#define DDRSS0_CTL_224_DATA 0x00000000
+#define DDRSS0_CTL_225_DATA 0x00000000
+#define DDRSS0_CTL_226_DATA 0x00000000
+#define DDRSS0_CTL_227_DATA 0x15110000
+#define DDRSS0_CTL_228_DATA 0x00040C18
+#define DDRSS0_CTL_229_DATA 0xF000C000
+#define DDRSS0_CTL_230_DATA 0x0000F000
+#define DDRSS0_CTL_231_DATA 0x00000000
+#define DDRSS0_CTL_232_DATA 0x00000000
+#define DDRSS0_CTL_233_DATA 0xC0000000
+#define DDRSS0_CTL_234_DATA 0xF000F000
+#define DDRSS0_CTL_235_DATA 0x00000000
+#define DDRSS0_CTL_236_DATA 0x00000000
+#define DDRSS0_CTL_237_DATA 0x00000000
+#define DDRSS0_CTL_238_DATA 0xF000C000
+#define DDRSS0_CTL_239_DATA 0x0000F000
+#define DDRSS0_CTL_240_DATA 0x00000000
+#define DDRSS0_CTL_241_DATA 0x00000000
+#define DDRSS0_CTL_242_DATA 0x00030000
+#define DDRSS0_CTL_243_DATA 0x00000000
+#define DDRSS0_CTL_244_DATA 0x00000000
+#define DDRSS0_CTL_245_DATA 0x00000000
+#define DDRSS0_CTL_246_DATA 0x00000000
+#define DDRSS0_CTL_247_DATA 0x00000000
+#define DDRSS0_CTL_248_DATA 0x00000000
+#define DDRSS0_CTL_249_DATA 0x00000000
+#define DDRSS0_CTL_250_DATA 0x00000000
+#define DDRSS0_CTL_251_DATA 0x00000000
+#define DDRSS0_CTL_252_DATA 0x00000000
+#define DDRSS0_CTL_253_DATA 0x00000000
+#define DDRSS0_CTL_254_DATA 0x00000000
+#define DDRSS0_CTL_255_DATA 0x00000000
+#define DDRSS0_CTL_256_DATA 0x00000000
+#define DDRSS0_CTL_257_DATA 0x01000200
+#define DDRSS0_CTL_258_DATA 0x00370040
+#define DDRSS0_CTL_259_DATA 0x00020008
+#define DDRSS0_CTL_260_DATA 0x00400100
+#define DDRSS0_CTL_261_DATA 0x00400855
+#define DDRSS0_CTL_262_DATA 0x01000200
+#define DDRSS0_CTL_263_DATA 0x08550040
+#define DDRSS0_CTL_264_DATA 0x00000040
+#define DDRSS0_CTL_265_DATA 0x006B0003
+#define DDRSS0_CTL_266_DATA 0x0100006B
+#define DDRSS0_CTL_267_DATA 0x03030303
+#define DDRSS0_CTL_268_DATA 0x00000000
+#define DDRSS0_CTL_269_DATA 0x00000202
+#define DDRSS0_CTL_270_DATA 0x00001FFF
+#define DDRSS0_CTL_271_DATA 0x3FFF2000
+#define DDRSS0_CTL_272_DATA 0x03FF0000
+#define DDRSS0_CTL_273_DATA 0x000103FF
+#define DDRSS0_CTL_274_DATA 0x0FFF0B00
+#define DDRSS0_CTL_275_DATA 0x01010001
+#define DDRSS0_CTL_276_DATA 0x01010101
+#define DDRSS0_CTL_277_DATA 0x01180101
+#define DDRSS0_CTL_278_DATA 0x00030000
+#define DDRSS0_CTL_279_DATA 0x00000000
+#define DDRSS0_CTL_280_DATA 0x00000000
+#define DDRSS0_CTL_281_DATA 0x00000000
+#define DDRSS0_CTL_282_DATA 0x00000000
+#define DDRSS0_CTL_283_DATA 0x00000000
+#define DDRSS0_CTL_284_DATA 0x00000000
+#define DDRSS0_CTL_285_DATA 0x00000000
+#define DDRSS0_CTL_286_DATA 0x00040101
+#define DDRSS0_CTL_287_DATA 0x04010100
+#define DDRSS0_CTL_288_DATA 0x00000000
+#define DDRSS0_CTL_289_DATA 0x00000000
+#define DDRSS0_CTL_290_DATA 0x03030300
+#define DDRSS0_CTL_291_DATA 0x00000001
+#define DDRSS0_CTL_292_DATA 0x00000000
+#define DDRSS0_CTL_293_DATA 0x00000000
+#define DDRSS0_CTL_294_DATA 0x00000000
+#define DDRSS0_CTL_295_DATA 0x00000000
+#define DDRSS0_CTL_296_DATA 0x00000000
+#define DDRSS0_CTL_297_DATA 0x00000000
+#define DDRSS0_CTL_298_DATA 0x00000000
+#define DDRSS0_CTL_299_DATA 0x00000000
+#define DDRSS0_CTL_300_DATA 0x00000000
+#define DDRSS0_CTL_301_DATA 0x00000000
+#define DDRSS0_CTL_302_DATA 0x00000000
+#define DDRSS0_CTL_303_DATA 0x00000000
+#define DDRSS0_CTL_304_DATA 0x00000000
+#define DDRSS0_CTL_305_DATA 0x00000000
+#define DDRSS0_CTL_306_DATA 0x00000000
+#define DDRSS0_CTL_307_DATA 0x00000000
+#define DDRSS0_CTL_308_DATA 0x00000000
+#define DDRSS0_CTL_309_DATA 0x00000000
+#define DDRSS0_CTL_310_DATA 0x00000000
+#define DDRSS0_CTL_311_DATA 0x00000000
+#define DDRSS0_CTL_312_DATA 0x00000000
+#define DDRSS0_CTL_313_DATA 0x01000000
+#define DDRSS0_CTL_314_DATA 0x00020201
+#define DDRSS0_CTL_315_DATA 0x01000101
+#define DDRSS0_CTL_316_DATA 0x01010001
+#define DDRSS0_CTL_317_DATA 0x00010101
+#define DDRSS0_CTL_318_DATA 0x050A0A03
+#define DDRSS0_CTL_319_DATA 0x10081F1F
+#define DDRSS0_CTL_320_DATA 0x00090310
+#define DDRSS0_CTL_321_DATA 0x0B0C030F
+#define DDRSS0_CTL_322_DATA 0x0B0C0306
+#define DDRSS0_CTL_323_DATA 0x0C090006
+#define DDRSS0_CTL_324_DATA 0x0100000C
+#define DDRSS0_CTL_325_DATA 0x08040801
+#define DDRSS0_CTL_326_DATA 0x00000004
+#define DDRSS0_CTL_327_DATA 0x00000000
+#define DDRSS0_CTL_328_DATA 0x00010000
+#define DDRSS0_CTL_329_DATA 0x00280D00
+#define DDRSS0_CTL_330_DATA 0x00000001
+#define DDRSS0_CTL_331_DATA 0x00030001
+#define DDRSS0_CTL_332_DATA 0x00000000
+#define DDRSS0_CTL_333_DATA 0x00000000
+#define DDRSS0_CTL_334_DATA 0x00000000
+#define DDRSS0_CTL_335_DATA 0x00000000
+#define DDRSS0_CTL_336_DATA 0x00000000
+#define DDRSS0_CTL_337_DATA 0x00000000
+#define DDRSS0_CTL_338_DATA 0x00000000
+#define DDRSS0_CTL_339_DATA 0x00000000
+#define DDRSS0_CTL_340_DATA 0x01000000
+#define DDRSS0_CTL_341_DATA 0x00000001
+#define DDRSS0_CTL_342_DATA 0x00010100
+#define DDRSS0_CTL_343_DATA 0x03030000
+#define DDRSS0_CTL_344_DATA 0x00000000
+#define DDRSS0_CTL_345_DATA 0x00000000
+#define DDRSS0_CTL_346_DATA 0x00000000
+#define DDRSS0_CTL_347_DATA 0x00000000
+#define DDRSS0_CTL_348_DATA 0x00000000
+#define DDRSS0_CTL_349_DATA 0x00000000
+#define DDRSS0_CTL_350_DATA 0x00000000
+#define DDRSS0_CTL_351_DATA 0x00000000
+#define DDRSS0_CTL_352_DATA 0x00000000
+#define DDRSS0_CTL_353_DATA 0x00000000
+#define DDRSS0_CTL_354_DATA 0x00000000
+#define DDRSS0_CTL_355_DATA 0x00000000
+#define DDRSS0_CTL_356_DATA 0x00000000
+#define DDRSS0_CTL_357_DATA 0x00000000
+#define DDRSS0_CTL_358_DATA 0x00000000
+#define DDRSS0_CTL_359_DATA 0x00000000
+#define DDRSS0_CTL_360_DATA 0x000556AA
+#define DDRSS0_CTL_361_DATA 0x000AAAAA
+#define DDRSS0_CTL_362_DATA 0x000AA955
+#define DDRSS0_CTL_363_DATA 0x00055555
+#define DDRSS0_CTL_364_DATA 0x000B3133
+#define DDRSS0_CTL_365_DATA 0x0004CD33
+#define DDRSS0_CTL_366_DATA 0x0004CECC
+#define DDRSS0_CTL_367_DATA 0x000B32CC
+#define DDRSS0_CTL_368_DATA 0x00010300
+#define DDRSS0_CTL_369_DATA 0x03000100
+#define DDRSS0_CTL_370_DATA 0x00000000
+#define DDRSS0_CTL_371_DATA 0x00000000
+#define DDRSS0_CTL_372_DATA 0x00000000
+#define DDRSS0_CTL_373_DATA 0x00000000
+#define DDRSS0_CTL_374_DATA 0x00000000
+#define DDRSS0_CTL_375_DATA 0x00000000
+#define DDRSS0_CTL_376_DATA 0x00000000
+#define DDRSS0_CTL_377_DATA 0x00010000
+#define DDRSS0_CTL_378_DATA 0x00000404
+#define DDRSS0_CTL_379_DATA 0x00000000
+#define DDRSS0_CTL_380_DATA 0x00000000
+#define DDRSS0_CTL_381_DATA 0x00000000
+#define DDRSS0_CTL_382_DATA 0x00000000
+#define DDRSS0_CTL_383_DATA 0x00000000
+#define DDRSS0_CTL_384_DATA 0x00000000
+#define DDRSS0_CTL_385_DATA 0x00000000
+#define DDRSS0_CTL_386_DATA 0x00000000
+#define DDRSS0_CTL_387_DATA 0x3A3A1B00
+#define DDRSS0_CTL_388_DATA 0x000A0000
+#define DDRSS0_CTL_389_DATA 0x0000019C
+#define DDRSS0_CTL_390_DATA 0x00000200
+#define DDRSS0_CTL_391_DATA 0x00000200
+#define DDRSS0_CTL_392_DATA 0x00000200
+#define DDRSS0_CTL_393_DATA 0x00000200
+#define DDRSS0_CTL_394_DATA 0x000004D4
+#define DDRSS0_CTL_395_DATA 0x00001018
+#define DDRSS0_CTL_396_DATA 0x00000204
+#define DDRSS0_CTL_397_DATA 0x000040E6
+#define DDRSS0_CTL_398_DATA 0x00000200
+#define DDRSS0_CTL_399_DATA 0x00000200
+#define DDRSS0_CTL_400_DATA 0x00000200
+#define DDRSS0_CTL_401_DATA 0x00000200
+#define DDRSS0_CTL_402_DATA 0x0000C2B2
+#define DDRSS0_CTL_403_DATA 0x000288FC
+#define DDRSS0_CTL_404_DATA 0x00000E15
+#define DDRSS0_CTL_405_DATA 0x000040E6
+#define DDRSS0_CTL_406_DATA 0x00000200
+#define DDRSS0_CTL_407_DATA 0x00000200
+#define DDRSS0_CTL_408_DATA 0x00000200
+#define DDRSS0_CTL_409_DATA 0x00000200
+#define DDRSS0_CTL_410_DATA 0x0000C2B2
+#define DDRSS0_CTL_411_DATA 0x000288FC
+#define DDRSS0_CTL_412_DATA 0x02020E15
+#define DDRSS0_CTL_413_DATA 0x03030202
+#define DDRSS0_CTL_414_DATA 0x00000022
+#define DDRSS0_CTL_415_DATA 0x00000000
+#define DDRSS0_CTL_416_DATA 0x00000000
+#define DDRSS0_CTL_417_DATA 0x00001403
+#define DDRSS0_CTL_418_DATA 0x000007D0
+#define DDRSS0_CTL_419_DATA 0x00000000
+#define DDRSS0_CTL_420_DATA 0x00000000
+#define DDRSS0_CTL_421_DATA 0x00030000
+#define DDRSS0_CTL_422_DATA 0x0007001F
+#define DDRSS0_CTL_423_DATA 0x001B0033
+#define DDRSS0_CTL_424_DATA 0x001B0033
+#define DDRSS0_CTL_425_DATA 0x00000000
+#define DDRSS0_CTL_426_DATA 0x00000000
+#define DDRSS0_CTL_427_DATA 0x02000000
+#define DDRSS0_CTL_428_DATA 0x01000404
+#define DDRSS0_CTL_429_DATA 0x0B1E0B1E
+#define DDRSS0_CTL_430_DATA 0x00000105
+#define DDRSS0_CTL_431_DATA 0x00010101
+#define DDRSS0_CTL_432_DATA 0x00010101
+#define DDRSS0_CTL_433_DATA 0x00010001
+#define DDRSS0_CTL_434_DATA 0x00000101
+#define DDRSS0_CTL_435_DATA 0x02000201
+#define DDRSS0_CTL_436_DATA 0x02010000
+#define DDRSS0_CTL_437_DATA 0x00000200
+#define DDRSS0_CTL_438_DATA 0x28060000
+#define DDRSS0_CTL_439_DATA 0x00000128
+#define DDRSS0_CTL_440_DATA 0xFFFFFFFF
+#define DDRSS0_CTL_441_DATA 0xFFFFFFFF
+#define DDRSS0_CTL_442_DATA 0x00000000
+#define DDRSS0_CTL_443_DATA 0x00000000
+#define DDRSS0_CTL_444_DATA 0x00000000
+#define DDRSS0_CTL_445_DATA 0x00000000
+#define DDRSS0_CTL_446_DATA 0x00000000
+#define DDRSS0_CTL_447_DATA 0x00000000
+#define DDRSS0_CTL_448_DATA 0x00000000
+#define DDRSS0_CTL_449_DATA 0x00000000
+#define DDRSS0_CTL_450_DATA 0x00000000
+#define DDRSS0_CTL_451_DATA 0x00000000
+#define DDRSS0_CTL_452_DATA 0x00000000
+#define DDRSS0_CTL_453_DATA 0x00000000
+#define DDRSS0_CTL_454_DATA 0x00000000
+#define DDRSS0_CTL_455_DATA 0x00000000
+#define DDRSS0_CTL_456_DATA 0x00000000
+#define DDRSS0_CTL_457_DATA 0x00000000
+#define DDRSS0_CTL_458_DATA 0x00000000
+
+#define DDRSS0_PI_00_DATA 0x00000B00
+#define DDRSS0_PI_01_DATA 0x00000000
+#define DDRSS0_PI_02_DATA 0x00000000
+#define DDRSS0_PI_03_DATA 0x00000000
+#define DDRSS0_PI_04_DATA 0x00000000
+#define DDRSS0_PI_05_DATA 0x00000101
+#define DDRSS0_PI_06_DATA 0x00640000
+#define DDRSS0_PI_07_DATA 0x00000001
+#define DDRSS0_PI_08_DATA 0x00000000
+#define DDRSS0_PI_09_DATA 0x00000000
+#define DDRSS0_PI_10_DATA 0x00000000
+#define DDRSS0_PI_11_DATA 0x00000000
+#define DDRSS0_PI_12_DATA 0x00000007
+#define DDRSS0_PI_13_DATA 0x00010002
+#define DDRSS0_PI_14_DATA 0x0800000F
+#define DDRSS0_PI_15_DATA 0x00000103
+#define DDRSS0_PI_16_DATA 0x00000005
+#define DDRSS0_PI_17_DATA 0x00000000
+#define DDRSS0_PI_18_DATA 0x00000000
+#define DDRSS0_PI_19_DATA 0x00000000
+#define DDRSS0_PI_20_DATA 0x00000000
+#define DDRSS0_PI_21_DATA 0x00000000
+#define DDRSS0_PI_22_DATA 0x00000000
+#define DDRSS0_PI_23_DATA 0x00000000
+#define DDRSS0_PI_24_DATA 0x00000000
+#define DDRSS0_PI_25_DATA 0x00000000
+#define DDRSS0_PI_26_DATA 0x00010100
+#define DDRSS0_PI_27_DATA 0x00280A00
+#define DDRSS0_PI_28_DATA 0x00000000
+#define DDRSS0_PI_29_DATA 0x0F000000
+#define DDRSS0_PI_30_DATA 0x00003200
+#define DDRSS0_PI_31_DATA 0x00000000
+#define DDRSS0_PI_32_DATA 0x00000000
+#define DDRSS0_PI_33_DATA 0x01010102
+#define DDRSS0_PI_34_DATA 0x00000000
+#define DDRSS0_PI_35_DATA 0x000000AA
+#define DDRSS0_PI_36_DATA 0x00000055
+#define DDRSS0_PI_37_DATA 0x000000B5
+#define DDRSS0_PI_38_DATA 0x0000004A
+#define DDRSS0_PI_39_DATA 0x00000056
+#define DDRSS0_PI_40_DATA 0x000000A9
+#define DDRSS0_PI_41_DATA 0x000000A9
+#define DDRSS0_PI_42_DATA 0x000000B5
+#define DDRSS0_PI_43_DATA 0x00000000
+#define DDRSS0_PI_44_DATA 0x00000000
+#define DDRSS0_PI_45_DATA 0x000F0F00
+#define DDRSS0_PI_46_DATA 0x0000001B
+#define DDRSS0_PI_47_DATA 0x000007D0
+#define DDRSS0_PI_48_DATA 0x00000300
+#define DDRSS0_PI_49_DATA 0x00000000
+#define DDRSS0_PI_50_DATA 0x00000000
+#define DDRSS0_PI_51_DATA 0x01000000
+#define DDRSS0_PI_52_DATA 0x00010101
+#define DDRSS0_PI_53_DATA 0x00000000
+#define DDRSS0_PI_54_DATA 0x00030000
+#define DDRSS0_PI_55_DATA 0x0F000000
+#define DDRSS0_PI_56_DATA 0x00000017
+#define DDRSS0_PI_57_DATA 0x00000000
+#define DDRSS0_PI_58_DATA 0x00000000
+#define DDRSS0_PI_59_DATA 0x00000000
+#define DDRSS0_PI_60_DATA 0x0A0A140A
+#define DDRSS0_PI_61_DATA 0x10020101
+#define DDRSS0_PI_62_DATA 0x00020805
+#define DDRSS0_PI_63_DATA 0x01000404
+#define DDRSS0_PI_64_DATA 0x00000000
+#define DDRSS0_PI_65_DATA 0x00000000
+#define DDRSS0_PI_66_DATA 0x00000100
+#define DDRSS0_PI_67_DATA 0x0001010F
+#define DDRSS0_PI_68_DATA 0x00340000
+#define DDRSS0_PI_69_DATA 0x00000000
+#define DDRSS0_PI_70_DATA 0x00000000
+#define DDRSS0_PI_71_DATA 0x0000FFFF
+#define DDRSS0_PI_72_DATA 0x00000000
+#define DDRSS0_PI_73_DATA 0x00080000
+#define DDRSS0_PI_74_DATA 0x02000200
+#define DDRSS0_PI_75_DATA 0x01000100
+#define DDRSS0_PI_76_DATA 0x01000000
+#define DDRSS0_PI_77_DATA 0x02000200
+#define DDRSS0_PI_78_DATA 0x00000200
+#define DDRSS0_PI_79_DATA 0x00000000
+#define DDRSS0_PI_80_DATA 0x00000000
+#define DDRSS0_PI_81_DATA 0x00000000
+#define DDRSS0_PI_82_DATA 0x00000000
+#define DDRSS0_PI_83_DATA 0x00000000
+#define DDRSS0_PI_84_DATA 0x00000000
+#define DDRSS0_PI_85_DATA 0x00000000
+#define DDRSS0_PI_86_DATA 0x00000000
+#define DDRSS0_PI_87_DATA 0x00000000
+#define DDRSS0_PI_88_DATA 0x00000000
+#define DDRSS0_PI_89_DATA 0x00000000
+#define DDRSS0_PI_90_DATA 0x00000000
+#define DDRSS0_PI_91_DATA 0x00000400
+#define DDRSS0_PI_92_DATA 0x02010000
+#define DDRSS0_PI_93_DATA 0x00080003
+#define DDRSS0_PI_94_DATA 0x00080000
+#define DDRSS0_PI_95_DATA 0x00000001
+#define DDRSS0_PI_96_DATA 0x00000000
+#define DDRSS0_PI_97_DATA 0x0000AA00
+#define DDRSS0_PI_98_DATA 0x00000000
+#define DDRSS0_PI_99_DATA 0x00000000
+#define DDRSS0_PI_100_DATA 0x00010000
+#define DDRSS0_PI_101_DATA 0x00000000
+#define DDRSS0_PI_102_DATA 0x00000000
+#define DDRSS0_PI_103_DATA 0x00000000
+#define DDRSS0_PI_104_DATA 0x00000000
+#define DDRSS0_PI_105_DATA 0x00000000
+#define DDRSS0_PI_106_DATA 0x00000000
+#define DDRSS0_PI_107_DATA 0x00000000
+#define DDRSS0_PI_108_DATA 0x00000000
+#define DDRSS0_PI_109_DATA 0x00000000
+#define DDRSS0_PI_110_DATA 0x00000000
+#define DDRSS0_PI_111_DATA 0x00000000
+#define DDRSS0_PI_112_DATA 0x00000000
+#define DDRSS0_PI_113_DATA 0x00000000
+#define DDRSS0_PI_114_DATA 0x00000000
+#define DDRSS0_PI_115_DATA 0x00000000
+#define DDRSS0_PI_116_DATA 0x00000000
+#define DDRSS0_PI_117_DATA 0x00000000
+#define DDRSS0_PI_118_DATA 0x00000000
+#define DDRSS0_PI_119_DATA 0x00000000
+#define DDRSS0_PI_120_DATA 0x00000000
+#define DDRSS0_PI_121_DATA 0x00000000
+#define DDRSS0_PI_122_DATA 0x00000000
+#define DDRSS0_PI_123_DATA 0x00000000
+#define DDRSS0_PI_124_DATA 0x00000000
+#define DDRSS0_PI_125_DATA 0x00000008
+#define DDRSS0_PI_126_DATA 0x00000000
+#define DDRSS0_PI_127_DATA 0x00000000
+#define DDRSS0_PI_128_DATA 0x00000000
+#define DDRSS0_PI_129_DATA 0x00000000
+#define DDRSS0_PI_130_DATA 0x00000000
+#define DDRSS0_PI_131_DATA 0x00000000
+#define DDRSS0_PI_132_DATA 0x00000000
+#define DDRSS0_PI_133_DATA 0x00000000
+#define DDRSS0_PI_134_DATA 0x00000002
+#define DDRSS0_PI_135_DATA 0x00000000
+#define DDRSS0_PI_136_DATA 0x00000000
+#define DDRSS0_PI_137_DATA 0x0000000A
+#define DDRSS0_PI_138_DATA 0x00000019
+#define DDRSS0_PI_139_DATA 0x00000100
+#define DDRSS0_PI_140_DATA 0x00000000
+#define DDRSS0_PI_141_DATA 0x00000000
+#define DDRSS0_PI_142_DATA 0x00000000
+#define DDRSS0_PI_143_DATA 0x00000000
+#define DDRSS0_PI_144_DATA 0x01000000
+#define DDRSS0_PI_145_DATA 0x00010003
+#define DDRSS0_PI_146_DATA 0x02000101
+#define DDRSS0_PI_147_DATA 0x01030001
+#define DDRSS0_PI_148_DATA 0x00010400
+#define DDRSS0_PI_149_DATA 0x06000105
+#define DDRSS0_PI_150_DATA 0x01070001
+#define DDRSS0_PI_151_DATA 0x00000000
+#define DDRSS0_PI_152_DATA 0x00000000
+#define DDRSS0_PI_153_DATA 0x00000000
+#define DDRSS0_PI_154_DATA 0x00010001
+#define DDRSS0_PI_155_DATA 0x00000000
+#define DDRSS0_PI_156_DATA 0x00000000
+#define DDRSS0_PI_157_DATA 0x00000000
+#define DDRSS0_PI_158_DATA 0x00000000
+#define DDRSS0_PI_159_DATA 0x00000401
+#define DDRSS0_PI_160_DATA 0x00000000
+#define DDRSS0_PI_161_DATA 0x00010000
+#define DDRSS0_PI_162_DATA 0x00000000
+#define DDRSS0_PI_163_DATA 0x2B2B0200
+#define DDRSS0_PI_164_DATA 0x00000034
+#define DDRSS0_PI_165_DATA 0x00000064
+#define DDRSS0_PI_166_DATA 0x00020064
+#define DDRSS0_PI_167_DATA 0x02000200
+#define DDRSS0_PI_168_DATA 0x48120C04
+#define DDRSS0_PI_169_DATA 0x00154812
+#define DDRSS0_PI_170_DATA 0x000000CE
+#define DDRSS0_PI_171_DATA 0x0000032B
+#define DDRSS0_PI_172_DATA 0x00002073
+#define DDRSS0_PI_173_DATA 0x0000032B
+#define DDRSS0_PI_174_DATA 0x04002073
+#define DDRSS0_PI_175_DATA 0x01010404
+#define DDRSS0_PI_176_DATA 0x00001501
+#define DDRSS0_PI_177_DATA 0x00150015
+#define DDRSS0_PI_178_DATA 0x01000100
+#define DDRSS0_PI_179_DATA 0x00000100
+#define DDRSS0_PI_180_DATA 0x00000000
+#define DDRSS0_PI_181_DATA 0x01010101
+#define DDRSS0_PI_182_DATA 0x00000101
+#define DDRSS0_PI_183_DATA 0x00000000
+#define DDRSS0_PI_184_DATA 0x00000000
+#define DDRSS0_PI_185_DATA 0x15040000
+#define DDRSS0_PI_186_DATA 0x0E0E0215
+#define DDRSS0_PI_187_DATA 0x00040402
+#define DDRSS0_PI_188_DATA 0x000D0035
+#define DDRSS0_PI_189_DATA 0x00218049
+#define DDRSS0_PI_190_DATA 0x00218049
+#define DDRSS0_PI_191_DATA 0x01010101
+#define DDRSS0_PI_192_DATA 0x0004000E
+#define DDRSS0_PI_193_DATA 0x00040216
+#define DDRSS0_PI_194_DATA 0x01000216
+#define DDRSS0_PI_195_DATA 0x000F000F
+#define DDRSS0_PI_196_DATA 0x02170100
+#define DDRSS0_PI_197_DATA 0x01000217
+#define DDRSS0_PI_198_DATA 0x02170217
+#define DDRSS0_PI_199_DATA 0x32103200
+#define DDRSS0_PI_200_DATA 0x01013210
+#define DDRSS0_PI_201_DATA 0x0A070601
+#define DDRSS0_PI_202_DATA 0x1F130A0D
+#define DDRSS0_PI_203_DATA 0x1F130A14
+#define DDRSS0_PI_204_DATA 0x0000C014
+#define DDRSS0_PI_205_DATA 0x00C01000
+#define DDRSS0_PI_206_DATA 0x00C01000
+#define DDRSS0_PI_207_DATA 0x00021000
+#define DDRSS0_PI_208_DATA 0x0024000E
+#define DDRSS0_PI_209_DATA 0x00240216
+#define DDRSS0_PI_210_DATA 0x00110216
+#define DDRSS0_PI_211_DATA 0x32000056
+#define DDRSS0_PI_212_DATA 0x00000301
+#define DDRSS0_PI_213_DATA 0x005B0036
+#define DDRSS0_PI_214_DATA 0x03013212
+#define DDRSS0_PI_215_DATA 0x00003600
+#define DDRSS0_PI_216_DATA 0x3212005B
+#define DDRSS0_PI_217_DATA 0x09000301
+#define DDRSS0_PI_218_DATA 0x04010504
+#define DDRSS0_PI_219_DATA 0x040006C9
+#define DDRSS0_PI_220_DATA 0x0A032001
+#define DDRSS0_PI_221_DATA 0x2C31110A
+#define DDRSS0_PI_222_DATA 0x00002918
+#define DDRSS0_PI_223_DATA 0x6001071C
+#define DDRSS0_PI_224_DATA 0x1E202008
+#define DDRSS0_PI_225_DATA 0x2C311116
+#define DDRSS0_PI_226_DATA 0x00002918
+#define DDRSS0_PI_227_DATA 0x6001071C
+#define DDRSS0_PI_228_DATA 0x1E202008
+#define DDRSS0_PI_229_DATA 0x00019C16
+#define DDRSS0_PI_230_DATA 0x00001018
+#define DDRSS0_PI_231_DATA 0x000040E6
+#define DDRSS0_PI_232_DATA 0x000288FC
+#define DDRSS0_PI_233_DATA 0x000040E6
+#define DDRSS0_PI_234_DATA 0x000288FC
+#define DDRSS0_PI_235_DATA 0x033B0016
+#define DDRSS0_PI_236_DATA 0x0303033B
+#define DDRSS0_PI_237_DATA 0x002AF803
+#define DDRSS0_PI_238_DATA 0x0001ADAF
+#define DDRSS0_PI_239_DATA 0x00000005
+#define DDRSS0_PI_240_DATA 0x0000006E
+#define DDRSS0_PI_241_DATA 0x00000016
+#define DDRSS0_PI_242_DATA 0x000681C8
+#define DDRSS0_PI_243_DATA 0x0001ADAF
+#define DDRSS0_PI_244_DATA 0x00000005
+#define DDRSS0_PI_245_DATA 0x000010A9
+#define DDRSS0_PI_246_DATA 0x0000033B
+#define DDRSS0_PI_247_DATA 0x000681C8
+#define DDRSS0_PI_248_DATA 0x0001ADAF
+#define DDRSS0_PI_249_DATA 0x00000005
+#define DDRSS0_PI_250_DATA 0x000010A9
+#define DDRSS0_PI_251_DATA 0x0100033B
+#define DDRSS0_PI_252_DATA 0x00370040
+#define DDRSS0_PI_253_DATA 0x00010008
+#define DDRSS0_PI_254_DATA 0x08550040
+#define DDRSS0_PI_255_DATA 0x00010040
+#define DDRSS0_PI_256_DATA 0x08550040
+#define DDRSS0_PI_257_DATA 0x00000340
+#define DDRSS0_PI_258_DATA 0x006B006B
+#define DDRSS0_PI_259_DATA 0x08040404
+#define DDRSS0_PI_260_DATA 0x00000055
+#define DDRSS0_PI_261_DATA 0x55083C5A
+#define DDRSS0_PI_262_DATA 0x5A000000
+#define DDRSS0_PI_263_DATA 0x0055083C
+#define DDRSS0_PI_264_DATA 0x3C5A0000
+#define DDRSS0_PI_265_DATA 0x00005508
+#define DDRSS0_PI_266_DATA 0x0C3C5A00
+#define DDRSS0_PI_267_DATA 0x080F0E0D
+#define DDRSS0_PI_268_DATA 0x000B0A09
+#define DDRSS0_PI_269_DATA 0x00030201
+#define DDRSS0_PI_270_DATA 0x01000000
+#define DDRSS0_PI_271_DATA 0x04020201
+#define DDRSS0_PI_272_DATA 0x00080804
+#define DDRSS0_PI_273_DATA 0x00000000
+#define DDRSS0_PI_274_DATA 0x00000000
+#define DDRSS0_PI_275_DATA 0x00330084
+#define DDRSS0_PI_276_DATA 0x00160000
+#define DDRSS0_PI_277_DATA 0x35333FF4
+#define DDRSS0_PI_278_DATA 0x00160F27
+#define DDRSS0_PI_279_DATA 0x35333FF4
+#define DDRSS0_PI_280_DATA 0x00160F27
+#define DDRSS0_PI_281_DATA 0x00330084
+#define DDRSS0_PI_282_DATA 0x00160000
+#define DDRSS0_PI_283_DATA 0x35333FF4
+#define DDRSS0_PI_284_DATA 0x00160F27
+#define DDRSS0_PI_285_DATA 0x35333FF4
+#define DDRSS0_PI_286_DATA 0x00160F27
+#define DDRSS0_PI_287_DATA 0x00330084
+#define DDRSS0_PI_288_DATA 0x00160000
+#define DDRSS0_PI_289_DATA 0x35333FF4
+#define DDRSS0_PI_290_DATA 0x00160F27
+#define DDRSS0_PI_291_DATA 0x35333FF4
+#define DDRSS0_PI_292_DATA 0x00160F27
+#define DDRSS0_PI_293_DATA 0x00330084
+#define DDRSS0_PI_294_DATA 0x00160000
+#define DDRSS0_PI_295_DATA 0x35333FF4
+#define DDRSS0_PI_296_DATA 0x00160F27
+#define DDRSS0_PI_297_DATA 0x35333FF4
+#define DDRSS0_PI_298_DATA 0x00160F27
+#define DDRSS0_PI_299_DATA 0x00000000
+
+#define DDRSS0_PHY_00_DATA 0x000004F0
+#define DDRSS0_PHY_01_DATA 0x00000000
+#define DDRSS0_PHY_02_DATA 0x00030200
+#define DDRSS0_PHY_03_DATA 0x00000000
+#define DDRSS0_PHY_04_DATA 0x00000000
+#define DDRSS0_PHY_05_DATA 0x01030000
+#define DDRSS0_PHY_06_DATA 0x00010000
+#define DDRSS0_PHY_07_DATA 0x01030004
+#define DDRSS0_PHY_08_DATA 0x01000000
+#define DDRSS0_PHY_09_DATA 0x00000000
+#define DDRSS0_PHY_10_DATA 0x00000000
+#define DDRSS0_PHY_11_DATA 0x01000001
+#define DDRSS0_PHY_12_DATA 0x00000100
+#define DDRSS0_PHY_13_DATA 0x000800C0
+#define DDRSS0_PHY_14_DATA 0x060100CC
+#define DDRSS0_PHY_15_DATA 0x00030066
+#define DDRSS0_PHY_16_DATA 0x00000000
+#define DDRSS0_PHY_17_DATA 0x00000301
+#define DDRSS0_PHY_18_DATA 0x0000AAAA
+#define DDRSS0_PHY_19_DATA 0x00005555
+#define DDRSS0_PHY_20_DATA 0x0000B5B5
+#define DDRSS0_PHY_21_DATA 0x00004A4A
+#define DDRSS0_PHY_22_DATA 0x00005656
+#define DDRSS0_PHY_23_DATA 0x0000A9A9
+#define DDRSS0_PHY_24_DATA 0x0000A9A9
+#define DDRSS0_PHY_25_DATA 0x0000B5B5
+#define DDRSS0_PHY_26_DATA 0x00000000
+#define DDRSS0_PHY_27_DATA 0x00000000
+#define DDRSS0_PHY_28_DATA 0x2A000000
+#define DDRSS0_PHY_29_DATA 0x00000808
+#define DDRSS0_PHY_30_DATA 0x0F000000
+#define DDRSS0_PHY_31_DATA 0x00000F0F
+#define DDRSS0_PHY_32_DATA 0x10400000
+#define DDRSS0_PHY_33_DATA 0x0C002006
+#define DDRSS0_PHY_34_DATA 0x00000000
+#define DDRSS0_PHY_35_DATA 0x00000000
+#define DDRSS0_PHY_36_DATA 0x55555555
+#define DDRSS0_PHY_37_DATA 0xAAAAAAAA
+#define DDRSS0_PHY_38_DATA 0x55555555
+#define DDRSS0_PHY_39_DATA 0xAAAAAAAA
+#define DDRSS0_PHY_40_DATA 0x00005555
+#define DDRSS0_PHY_41_DATA 0x01000100
+#define DDRSS0_PHY_42_DATA 0x00800180
+#define DDRSS0_PHY_43_DATA 0x00000001
+#define DDRSS0_PHY_44_DATA 0x00000000
+#define DDRSS0_PHY_45_DATA 0x00000000
+#define DDRSS0_PHY_46_DATA 0x00000000
+#define DDRSS0_PHY_47_DATA 0x00000000
+#define DDRSS0_PHY_48_DATA 0x00000000
+#define DDRSS0_PHY_49_DATA 0x00000000
+#define DDRSS0_PHY_50_DATA 0x00000000
+#define DDRSS0_PHY_51_DATA 0x00000000
+#define DDRSS0_PHY_52_DATA 0x00000000
+#define DDRSS0_PHY_53_DATA 0x00000000
+#define DDRSS0_PHY_54_DATA 0x00000000
+#define DDRSS0_PHY_55_DATA 0x00000000
+#define DDRSS0_PHY_56_DATA 0x00000000
+#define DDRSS0_PHY_57_DATA 0x00000000
+#define DDRSS0_PHY_58_DATA 0x00000000
+#define DDRSS0_PHY_59_DATA 0x00000000
+#define DDRSS0_PHY_60_DATA 0x00000000
+#define DDRSS0_PHY_61_DATA 0x00000000
+#define DDRSS0_PHY_62_DATA 0x00000000
+#define DDRSS0_PHY_63_DATA 0x00000000
+#define DDRSS0_PHY_64_DATA 0x00000000
+#define DDRSS0_PHY_65_DATA 0x00000000
+#define DDRSS0_PHY_66_DATA 0x00000104
+#define DDRSS0_PHY_67_DATA 0x00000120
+#define DDRSS0_PHY_68_DATA 0x00000000
+#define DDRSS0_PHY_69_DATA 0x00000000
+#define DDRSS0_PHY_70_DATA 0x00000000
+#define DDRSS0_PHY_71_DATA 0x00000000
+#define DDRSS0_PHY_72_DATA 0x00000000
+#define DDRSS0_PHY_73_DATA 0x00000000
+#define DDRSS0_PHY_74_DATA 0x00000000
+#define DDRSS0_PHY_75_DATA 0x00000001
+#define DDRSS0_PHY_76_DATA 0x07FF0000
+#define DDRSS0_PHY_77_DATA 0x0080081F
+#define DDRSS0_PHY_78_DATA 0x00081020
+#define DDRSS0_PHY_79_DATA 0x04010000
+#define DDRSS0_PHY_80_DATA 0x00000000
+#define DDRSS0_PHY_81_DATA 0x00000000
+#define DDRSS0_PHY_82_DATA 0x00000000
+#define DDRSS0_PHY_83_DATA 0x00000100
+#define DDRSS0_PHY_84_DATA 0x01CC0C01
+#define DDRSS0_PHY_85_DATA 0x1003CC0C
+#define DDRSS0_PHY_86_DATA 0x20000140
+#define DDRSS0_PHY_87_DATA 0x07FF0200
+#define DDRSS0_PHY_88_DATA 0x0000DD01
+#define DDRSS0_PHY_89_DATA 0x10100303
+#define DDRSS0_PHY_90_DATA 0x10101010
+#define DDRSS0_PHY_91_DATA 0x10101010
+#define DDRSS0_PHY_92_DATA 0x00021010
+#define DDRSS0_PHY_93_DATA 0x00100010
+#define DDRSS0_PHY_94_DATA 0x00100010
+#define DDRSS0_PHY_95_DATA 0x00100010
+#define DDRSS0_PHY_96_DATA 0x00100010
+#define DDRSS0_PHY_97_DATA 0x00050010
+#define DDRSS0_PHY_98_DATA 0x51517041
+#define DDRSS0_PHY_99_DATA 0x31C06001
+#define DDRSS0_PHY_100_DATA 0x07AB0340
+#define DDRSS0_PHY_101_DATA 0x00C0C001
+#define DDRSS0_PHY_102_DATA 0x0E0D0001
+#define DDRSS0_PHY_103_DATA 0x10001000
+#define DDRSS0_PHY_104_DATA 0x0C083E42
+#define DDRSS0_PHY_105_DATA 0x0F0C3701
+#define DDRSS0_PHY_106_DATA 0x01000140
+#define DDRSS0_PHY_107_DATA 0x0C000420
+#define DDRSS0_PHY_108_DATA 0x00000198
+#define DDRSS0_PHY_109_DATA 0x0A0000D0
+#define DDRSS0_PHY_110_DATA 0x00030200
+#define DDRSS0_PHY_111_DATA 0x02800000
+#define DDRSS0_PHY_112_DATA 0x80800000
+#define DDRSS0_PHY_113_DATA 0x000E2010
+#define DDRSS0_PHY_114_DATA 0x76543210
+#define DDRSS0_PHY_115_DATA 0x00000008
+#define DDRSS0_PHY_116_DATA 0x02800280
+#define DDRSS0_PHY_117_DATA 0x02800280
+#define DDRSS0_PHY_118_DATA 0x02800280
+#define DDRSS0_PHY_119_DATA 0x02800280
+#define DDRSS0_PHY_120_DATA 0x00000280
+#define DDRSS0_PHY_121_DATA 0x0000A000
+#define DDRSS0_PHY_122_DATA 0x00A000A0
+#define DDRSS0_PHY_123_DATA 0x00A000A0
+#define DDRSS0_PHY_124_DATA 0x00A000A0
+#define DDRSS0_PHY_125_DATA 0x00A000A0
+#define DDRSS0_PHY_126_DATA 0x00A000A0
+#define DDRSS0_PHY_127_DATA 0x00A000A0
+#define DDRSS0_PHY_128_DATA 0x00A000A0
+#define DDRSS0_PHY_129_DATA 0x00A000A0
+#define DDRSS0_PHY_130_DATA 0x01C200A0
+#define DDRSS0_PHY_131_DATA 0x01A00005
+#define DDRSS0_PHY_132_DATA 0x00000000
+#define DDRSS0_PHY_133_DATA 0x00000000
+#define DDRSS0_PHY_134_DATA 0x00080200
+#define DDRSS0_PHY_135_DATA 0x00000000
+#define DDRSS0_PHY_136_DATA 0x20202000
+#define DDRSS0_PHY_137_DATA 0x20202020
+#define DDRSS0_PHY_138_DATA 0xF0F02020
+#define DDRSS0_PHY_139_DATA 0x00000000
+#define DDRSS0_PHY_140_DATA 0x00000000
+#define DDRSS0_PHY_141_DATA 0x00000000
+#define DDRSS0_PHY_142_DATA 0x00000000
+#define DDRSS0_PHY_143_DATA 0x00000000
+#define DDRSS0_PHY_144_DATA 0x00000000
+#define DDRSS0_PHY_145_DATA 0x00000000
+#define DDRSS0_PHY_146_DATA 0x00000000
+#define DDRSS0_PHY_147_DATA 0x00000000
+#define DDRSS0_PHY_148_DATA 0x00000000
+#define DDRSS0_PHY_149_DATA 0x00000000
+#define DDRSS0_PHY_150_DATA 0x00000000
+#define DDRSS0_PHY_151_DATA 0x00000000
+#define DDRSS0_PHY_152_DATA 0x00000000
+#define DDRSS0_PHY_153_DATA 0x00000000
+#define DDRSS0_PHY_154_DATA 0x00000000
+#define DDRSS0_PHY_155_DATA 0x00000000
+#define DDRSS0_PHY_156_DATA 0x00000000
+#define DDRSS0_PHY_157_DATA 0x00000000
+#define DDRSS0_PHY_158_DATA 0x00000000
+#define DDRSS0_PHY_159_DATA 0x00000000
+#define DDRSS0_PHY_160_DATA 0x00000000
+#define DDRSS0_PHY_161_DATA 0x00000000
+#define DDRSS0_PHY_162_DATA 0x00000000
+#define DDRSS0_PHY_163_DATA 0x00000000
+#define DDRSS0_PHY_164_DATA 0x00000000
+#define DDRSS0_PHY_165_DATA 0x00000000
+#define DDRSS0_PHY_166_DATA 0x00000000
+#define DDRSS0_PHY_167_DATA 0x00000000
+#define DDRSS0_PHY_168_DATA 0x00000000
+#define DDRSS0_PHY_169_DATA 0x00000000
+#define DDRSS0_PHY_170_DATA 0x00000000
+#define DDRSS0_PHY_171_DATA 0x00000000
+#define DDRSS0_PHY_172_DATA 0x00000000
+#define DDRSS0_PHY_173_DATA 0x00000000
+#define DDRSS0_PHY_174_DATA 0x00000000
+#define DDRSS0_PHY_175_DATA 0x00000000
+#define DDRSS0_PHY_176_DATA 0x00000000
+#define DDRSS0_PHY_177_DATA 0x00000000
+#define DDRSS0_PHY_178_DATA 0x00000000
+#define DDRSS0_PHY_179_DATA 0x00000000
+#define DDRSS0_PHY_180_DATA 0x00000000
+#define DDRSS0_PHY_181_DATA 0x00000000
+#define DDRSS0_PHY_182_DATA 0x00000000
+#define DDRSS0_PHY_183_DATA 0x00000000
+#define DDRSS0_PHY_184_DATA 0x00000000
+#define DDRSS0_PHY_185_DATA 0x00000000
+#define DDRSS0_PHY_186_DATA 0x00000000
+#define DDRSS0_PHY_187_DATA 0x00000000
+#define DDRSS0_PHY_188_DATA 0x00000000
+#define DDRSS0_PHY_189_DATA 0x00000000
+#define DDRSS0_PHY_190_DATA 0x00000000
+#define DDRSS0_PHY_191_DATA 0x00000000
+#define DDRSS0_PHY_192_DATA 0x00000000
+#define DDRSS0_PHY_193_DATA 0x00000000
+#define DDRSS0_PHY_194_DATA 0x00000000
+#define DDRSS0_PHY_195_DATA 0x00000000
+#define DDRSS0_PHY_196_DATA 0x00000000
+#define DDRSS0_PHY_197_DATA 0x00000000
+#define DDRSS0_PHY_198_DATA 0x00000000
+#define DDRSS0_PHY_199_DATA 0x00000000
+#define DDRSS0_PHY_200_DATA 0x00000000
+#define DDRSS0_PHY_201_DATA 0x00000000
+#define DDRSS0_PHY_202_DATA 0x00000000
+#define DDRSS0_PHY_203_DATA 0x00000000
+#define DDRSS0_PHY_204_DATA 0x00000000
+#define DDRSS0_PHY_205_DATA 0x00000000
+#define DDRSS0_PHY_206_DATA 0x00000000
+#define DDRSS0_PHY_207_DATA 0x00000000
+#define DDRSS0_PHY_208_DATA 0x00000000
+#define DDRSS0_PHY_209_DATA 0x00000000
+#define DDRSS0_PHY_210_DATA 0x00000000
+#define DDRSS0_PHY_211_DATA 0x00000000
+#define DDRSS0_PHY_212_DATA 0x00000000
+#define DDRSS0_PHY_213_DATA 0x00000000
+#define DDRSS0_PHY_214_DATA 0x00000000
+#define DDRSS0_PHY_215_DATA 0x00000000
+#define DDRSS0_PHY_216_DATA 0x00000000
+#define DDRSS0_PHY_217_DATA 0x00000000
+#define DDRSS0_PHY_218_DATA 0x00000000
+#define DDRSS0_PHY_219_DATA 0x00000000
+#define DDRSS0_PHY_220_DATA 0x00000000
+#define DDRSS0_PHY_221_DATA 0x00000000
+#define DDRSS0_PHY_222_DATA 0x00000000
+#define DDRSS0_PHY_223_DATA 0x00000000
+#define DDRSS0_PHY_224_DATA 0x00000000
+#define DDRSS0_PHY_225_DATA 0x00000000
+#define DDRSS0_PHY_226_DATA 0x00000000
+#define DDRSS0_PHY_227_DATA 0x00000000
+#define DDRSS0_PHY_228_DATA 0x00000000
+#define DDRSS0_PHY_229_DATA 0x00000000
+#define DDRSS0_PHY_230_DATA 0x00000000
+#define DDRSS0_PHY_231_DATA 0x00000000
+#define DDRSS0_PHY_232_DATA 0x00000000
+#define DDRSS0_PHY_233_DATA 0x00000000
+#define DDRSS0_PHY_234_DATA 0x00000000
+#define DDRSS0_PHY_235_DATA 0x00000000
+#define DDRSS0_PHY_236_DATA 0x00000000
+#define DDRSS0_PHY_237_DATA 0x00000000
+#define DDRSS0_PHY_238_DATA 0x00000000
+#define DDRSS0_PHY_239_DATA 0x00000000
+#define DDRSS0_PHY_240_DATA 0x00000000
+#define DDRSS0_PHY_241_DATA 0x00000000
+#define DDRSS0_PHY_242_DATA 0x00000000
+#define DDRSS0_PHY_243_DATA 0x00000000
+#define DDRSS0_PHY_244_DATA 0x00000000
+#define DDRSS0_PHY_245_DATA 0x00000000
+#define DDRSS0_PHY_246_DATA 0x00000000
+#define DDRSS0_PHY_247_DATA 0x00000000
+#define DDRSS0_PHY_248_DATA 0x00000000
+#define DDRSS0_PHY_249_DATA 0x00000000
+#define DDRSS0_PHY_250_DATA 0x00000000
+#define DDRSS0_PHY_251_DATA 0x00000000
+#define DDRSS0_PHY_252_DATA 0x00000000
+#define DDRSS0_PHY_253_DATA 0x00000000
+#define DDRSS0_PHY_254_DATA 0x00000000
+#define DDRSS0_PHY_255_DATA 0x00000000
+#define DDRSS0_PHY_256_DATA 0x000004F0
+#define DDRSS0_PHY_257_DATA 0x00000000
+#define DDRSS0_PHY_258_DATA 0x00030200
+#define DDRSS0_PHY_259_DATA 0x00000000
+#define DDRSS0_PHY_260_DATA 0x00000000
+#define DDRSS0_PHY_261_DATA 0x01030000
+#define DDRSS0_PHY_262_DATA 0x00010000
+#define DDRSS0_PHY_263_DATA 0x01030004
+#define DDRSS0_PHY_264_DATA 0x01000000
+#define DDRSS0_PHY_265_DATA 0x00000000
+#define DDRSS0_PHY_266_DATA 0x00000000
+#define DDRSS0_PHY_267_DATA 0x01000001
+#define DDRSS0_PHY_268_DATA 0x00000100
+#define DDRSS0_PHY_269_DATA 0x000800C0
+#define DDRSS0_PHY_270_DATA 0x060100CC
+#define DDRSS0_PHY_271_DATA 0x00030066
+#define DDRSS0_PHY_272_DATA 0x00000000
+#define DDRSS0_PHY_273_DATA 0x00000301
+#define DDRSS0_PHY_274_DATA 0x0000AAAA
+#define DDRSS0_PHY_275_DATA 0x00005555
+#define DDRSS0_PHY_276_DATA 0x0000B5B5
+#define DDRSS0_PHY_277_DATA 0x00004A4A
+#define DDRSS0_PHY_278_DATA 0x00005656
+#define DDRSS0_PHY_279_DATA 0x0000A9A9
+#define DDRSS0_PHY_280_DATA 0x0000A9A9
+#define DDRSS0_PHY_281_DATA 0x0000B5B5
+#define DDRSS0_PHY_282_DATA 0x00000000
+#define DDRSS0_PHY_283_DATA 0x00000000
+#define DDRSS0_PHY_284_DATA 0x2A000000
+#define DDRSS0_PHY_285_DATA 0x00000808
+#define DDRSS0_PHY_286_DATA 0x0F000000
+#define DDRSS0_PHY_287_DATA 0x00000F0F
+#define DDRSS0_PHY_288_DATA 0x10400000
+#define DDRSS0_PHY_289_DATA 0x0C002006
+#define DDRSS0_PHY_290_DATA 0x00000000
+#define DDRSS0_PHY_291_DATA 0x00000000
+#define DDRSS0_PHY_292_DATA 0x55555555
+#define DDRSS0_PHY_293_DATA 0xAAAAAAAA
+#define DDRSS0_PHY_294_DATA 0x55555555
+#define DDRSS0_PHY_295_DATA 0xAAAAAAAA
+#define DDRSS0_PHY_296_DATA 0x00005555
+#define DDRSS0_PHY_297_DATA 0x01000100
+#define DDRSS0_PHY_298_DATA 0x00800180
+#define DDRSS0_PHY_299_DATA 0x00000000
+#define DDRSS0_PHY_300_DATA 0x00000000
+#define DDRSS0_PHY_301_DATA 0x00000000
+#define DDRSS0_PHY_302_DATA 0x00000000
+#define DDRSS0_PHY_303_DATA 0x00000000
+#define DDRSS0_PHY_304_DATA 0x00000000
+#define DDRSS0_PHY_305_DATA 0x00000000
+#define DDRSS0_PHY_306_DATA 0x00000000
+#define DDRSS0_PHY_307_DATA 0x00000000
+#define DDRSS0_PHY_308_DATA 0x00000000
+#define DDRSS0_PHY_309_DATA 0x00000000
+#define DDRSS0_PHY_310_DATA 0x00000000
+#define DDRSS0_PHY_311_DATA 0x00000000
+#define DDRSS0_PHY_312_DATA 0x00000000
+#define DDRSS0_PHY_313_DATA 0x00000000
+#define DDRSS0_PHY_314_DATA 0x00000000
+#define DDRSS0_PHY_315_DATA 0x00000000
+#define DDRSS0_PHY_316_DATA 0x00000000
+#define DDRSS0_PHY_317_DATA 0x00000000
+#define DDRSS0_PHY_318_DATA 0x00000000
+#define DDRSS0_PHY_319_DATA 0x00000000
+#define DDRSS0_PHY_320_DATA 0x00000000
+#define DDRSS0_PHY_321_DATA 0x00000000
+#define DDRSS0_PHY_322_DATA 0x00000104
+#define DDRSS0_PHY_323_DATA 0x00000120
+#define DDRSS0_PHY_324_DATA 0x00000000
+#define DDRSS0_PHY_325_DATA 0x00000000
+#define DDRSS0_PHY_326_DATA 0x00000000
+#define DDRSS0_PHY_327_DATA 0x00000000
+#define DDRSS0_PHY_328_DATA 0x00000000
+#define DDRSS0_PHY_329_DATA 0x00000000
+#define DDRSS0_PHY_330_DATA 0x00000000
+#define DDRSS0_PHY_331_DATA 0x00000001
+#define DDRSS0_PHY_332_DATA 0x07FF0000
+#define DDRSS0_PHY_333_DATA 0x0080081F
+#define DDRSS0_PHY_334_DATA 0x00081020
+#define DDRSS0_PHY_335_DATA 0x04010000
+#define DDRSS0_PHY_336_DATA 0x00000000
+#define DDRSS0_PHY_337_DATA 0x00000000
+#define DDRSS0_PHY_338_DATA 0x00000000
+#define DDRSS0_PHY_339_DATA 0x00000100
+#define DDRSS0_PHY_340_DATA 0x01CC0C01
+#define DDRSS0_PHY_341_DATA 0x1003CC0C
+#define DDRSS0_PHY_342_DATA 0x20000140
+#define DDRSS0_PHY_343_DATA 0x07FF0200
+#define DDRSS0_PHY_344_DATA 0x0000DD01
+#define DDRSS0_PHY_345_DATA 0x10100303
+#define DDRSS0_PHY_346_DATA 0x10101010
+#define DDRSS0_PHY_347_DATA 0x10101010
+#define DDRSS0_PHY_348_DATA 0x00021010
+#define DDRSS0_PHY_349_DATA 0x00100010
+#define DDRSS0_PHY_350_DATA 0x00100010
+#define DDRSS0_PHY_351_DATA 0x00100010
+#define DDRSS0_PHY_352_DATA 0x00100010
+#define DDRSS0_PHY_353_DATA 0x00050010
+#define DDRSS0_PHY_354_DATA 0x51517041
+#define DDRSS0_PHY_355_DATA 0x31C06001
+#define DDRSS0_PHY_356_DATA 0x07AB0340
+#define DDRSS0_PHY_357_DATA 0x00C0C001
+#define DDRSS0_PHY_358_DATA 0x0E0D0001
+#define DDRSS0_PHY_359_DATA 0x10001000
+#define DDRSS0_PHY_360_DATA 0x0C083E42
+#define DDRSS0_PHY_361_DATA 0x0F0C3701
+#define DDRSS0_PHY_362_DATA 0x01000140
+#define DDRSS0_PHY_363_DATA 0x0C000420
+#define DDRSS0_PHY_364_DATA 0x00000198
+#define DDRSS0_PHY_365_DATA 0x0A0000D0
+#define DDRSS0_PHY_366_DATA 0x00030200
+#define DDRSS0_PHY_367_DATA 0x02800000
+#define DDRSS0_PHY_368_DATA 0x80800000
+#define DDRSS0_PHY_369_DATA 0x000E2010
+#define DDRSS0_PHY_370_DATA 0x76543210
+#define DDRSS0_PHY_371_DATA 0x00000008
+#define DDRSS0_PHY_372_DATA 0x02800280
+#define DDRSS0_PHY_373_DATA 0x02800280
+#define DDRSS0_PHY_374_DATA 0x02800280
+#define DDRSS0_PHY_375_DATA 0x02800280
+#define DDRSS0_PHY_376_DATA 0x00000280
+#define DDRSS0_PHY_377_DATA 0x0000A000
+#define DDRSS0_PHY_378_DATA 0x00A000A0
+#define DDRSS0_PHY_379_DATA 0x00A000A0
+#define DDRSS0_PHY_380_DATA 0x00A000A0
+#define DDRSS0_PHY_381_DATA 0x00A000A0
+#define DDRSS0_PHY_382_DATA 0x00A000A0
+#define DDRSS0_PHY_383_DATA 0x00A000A0
+#define DDRSS0_PHY_384_DATA 0x00A000A0
+#define DDRSS0_PHY_385_DATA 0x00A000A0
+#define DDRSS0_PHY_386_DATA 0x01C200A0
+#define DDRSS0_PHY_387_DATA 0x01A00005
+#define DDRSS0_PHY_388_DATA 0x00000000
+#define DDRSS0_PHY_389_DATA 0x00000000
+#define DDRSS0_PHY_390_DATA 0x00080200
+#define DDRSS0_PHY_391_DATA 0x00000000
+#define DDRSS0_PHY_392_DATA 0x20202000
+#define DDRSS0_PHY_393_DATA 0x20202020
+#define DDRSS0_PHY_394_DATA 0xF0F02020
+#define DDRSS0_PHY_395_DATA 0x00000000
+#define DDRSS0_PHY_396_DATA 0x00000000
+#define DDRSS0_PHY_397_DATA 0x00000000
+#define DDRSS0_PHY_398_DATA 0x00000000
+#define DDRSS0_PHY_399_DATA 0x00000000
+#define DDRSS0_PHY_400_DATA 0x00000000
+#define DDRSS0_PHY_401_DATA 0x00000000
+#define DDRSS0_PHY_402_DATA 0x00000000
+#define DDRSS0_PHY_403_DATA 0x00000000
+#define DDRSS0_PHY_404_DATA 0x00000000
+#define DDRSS0_PHY_405_DATA 0x00000000
+#define DDRSS0_PHY_406_DATA 0x00000000
+#define DDRSS0_PHY_407_DATA 0x00000000
+#define DDRSS0_PHY_408_DATA 0x00000000
+#define DDRSS0_PHY_409_DATA 0x00000000
+#define DDRSS0_PHY_410_DATA 0x00000000
+#define DDRSS0_PHY_411_DATA 0x00000000
+#define DDRSS0_PHY_412_DATA 0x00000000
+#define DDRSS0_PHY_413_DATA 0x00000000
+#define DDRSS0_PHY_414_DATA 0x00000000
+#define DDRSS0_PHY_415_DATA 0x00000000
+#define DDRSS0_PHY_416_DATA 0x00000000
+#define DDRSS0_PHY_417_DATA 0x00000000
+#define DDRSS0_PHY_418_DATA 0x00000000
+#define DDRSS0_PHY_419_DATA 0x00000000
+#define DDRSS0_PHY_420_DATA 0x00000000
+#define DDRSS0_PHY_421_DATA 0x00000000
+#define DDRSS0_PHY_422_DATA 0x00000000
+#define DDRSS0_PHY_423_DATA 0x00000000
+#define DDRSS0_PHY_424_DATA 0x00000000
+#define DDRSS0_PHY_425_DATA 0x00000000
+#define DDRSS0_PHY_426_DATA 0x00000000
+#define DDRSS0_PHY_427_DATA 0x00000000
+#define DDRSS0_PHY_428_DATA 0x00000000
+#define DDRSS0_PHY_429_DATA 0x00000000
+#define DDRSS0_PHY_430_DATA 0x00000000
+#define DDRSS0_PHY_431_DATA 0x00000000
+#define DDRSS0_PHY_432_DATA 0x00000000
+#define DDRSS0_PHY_433_DATA 0x00000000
+#define DDRSS0_PHY_434_DATA 0x00000000
+#define DDRSS0_PHY_435_DATA 0x00000000
+#define DDRSS0_PHY_436_DATA 0x00000000
+#define DDRSS0_PHY_437_DATA 0x00000000
+#define DDRSS0_PHY_438_DATA 0x00000000
+#define DDRSS0_PHY_439_DATA 0x00000000
+#define DDRSS0_PHY_440_DATA 0x00000000
+#define DDRSS0_PHY_441_DATA 0x00000000
+#define DDRSS0_PHY_442_DATA 0x00000000
+#define DDRSS0_PHY_443_DATA 0x00000000
+#define DDRSS0_PHY_444_DATA 0x00000000
+#define DDRSS0_PHY_445_DATA 0x00000000
+#define DDRSS0_PHY_446_DATA 0x00000000
+#define DDRSS0_PHY_447_DATA 0x00000000
+#define DDRSS0_PHY_448_DATA 0x00000000
+#define DDRSS0_PHY_449_DATA 0x00000000
+#define DDRSS0_PHY_450_DATA 0x00000000
+#define DDRSS0_PHY_451_DATA 0x00000000
+#define DDRSS0_PHY_452_DATA 0x00000000
+#define DDRSS0_PHY_453_DATA 0x00000000
+#define DDRSS0_PHY_454_DATA 0x00000000
+#define DDRSS0_PHY_455_DATA 0x00000000
+#define DDRSS0_PHY_456_DATA 0x00000000
+#define DDRSS0_PHY_457_DATA 0x00000000
+#define DDRSS0_PHY_458_DATA 0x00000000
+#define DDRSS0_PHY_459_DATA 0x00000000
+#define DDRSS0_PHY_460_DATA 0x00000000
+#define DDRSS0_PHY_461_DATA 0x00000000
+#define DDRSS0_PHY_462_DATA 0x00000000
+#define DDRSS0_PHY_463_DATA 0x00000000
+#define DDRSS0_PHY_464_DATA 0x00000000
+#define DDRSS0_PHY_465_DATA 0x00000000
+#define DDRSS0_PHY_466_DATA 0x00000000
+#define DDRSS0_PHY_467_DATA 0x00000000
+#define DDRSS0_PHY_468_DATA 0x00000000
+#define DDRSS0_PHY_469_DATA 0x00000000
+#define DDRSS0_PHY_470_DATA 0x00000000
+#define DDRSS0_PHY_471_DATA 0x00000000
+#define DDRSS0_PHY_472_DATA 0x00000000
+#define DDRSS0_PHY_473_DATA 0x00000000
+#define DDRSS0_PHY_474_DATA 0x00000000
+#define DDRSS0_PHY_475_DATA 0x00000000
+#define DDRSS0_PHY_476_DATA 0x00000000
+#define DDRSS0_PHY_477_DATA 0x00000000
+#define DDRSS0_PHY_478_DATA 0x00000000
+#define DDRSS0_PHY_479_DATA 0x00000000
+#define DDRSS0_PHY_480_DATA 0x00000000
+#define DDRSS0_PHY_481_DATA 0x00000000
+#define DDRSS0_PHY_482_DATA 0x00000000
+#define DDRSS0_PHY_483_DATA 0x00000000
+#define DDRSS0_PHY_484_DATA 0x00000000
+#define DDRSS0_PHY_485_DATA 0x00000000
+#define DDRSS0_PHY_486_DATA 0x00000000
+#define DDRSS0_PHY_487_DATA 0x00000000
+#define DDRSS0_PHY_488_DATA 0x00000000
+#define DDRSS0_PHY_489_DATA 0x00000000
+#define DDRSS0_PHY_490_DATA 0x00000000
+#define DDRSS0_PHY_491_DATA 0x00000000
+#define DDRSS0_PHY_492_DATA 0x00000000
+#define DDRSS0_PHY_493_DATA 0x00000000
+#define DDRSS0_PHY_494_DATA 0x00000000
+#define DDRSS0_PHY_495_DATA 0x00000000
+#define DDRSS0_PHY_496_DATA 0x00000000
+#define DDRSS0_PHY_497_DATA 0x00000000
+#define DDRSS0_PHY_498_DATA 0x00000000
+#define DDRSS0_PHY_499_DATA 0x00000000
+#define DDRSS0_PHY_500_DATA 0x00000000
+#define DDRSS0_PHY_501_DATA 0x00000000
+#define DDRSS0_PHY_502_DATA 0x00000000
+#define DDRSS0_PHY_503_DATA 0x00000000
+#define DDRSS0_PHY_504_DATA 0x00000000
+#define DDRSS0_PHY_505_DATA 0x00000000
+#define DDRSS0_PHY_506_DATA 0x00000000
+#define DDRSS0_PHY_507_DATA 0x00000000
+#define DDRSS0_PHY_508_DATA 0x00000000
+#define DDRSS0_PHY_509_DATA 0x00000000
+#define DDRSS0_PHY_510_DATA 0x00000000
+#define DDRSS0_PHY_511_DATA 0x00000000
+#define DDRSS0_PHY_512_DATA 0x000004F0
+#define DDRSS0_PHY_513_DATA 0x00000000
+#define DDRSS0_PHY_514_DATA 0x00030200
+#define DDRSS0_PHY_515_DATA 0x00000000
+#define DDRSS0_PHY_516_DATA 0x00000000
+#define DDRSS0_PHY_517_DATA 0x01030000
+#define DDRSS0_PHY_518_DATA 0x00010000
+#define DDRSS0_PHY_519_DATA 0x01030004
+#define DDRSS0_PHY_520_DATA 0x01000000
+#define DDRSS0_PHY_521_DATA 0x00000000
+#define DDRSS0_PHY_522_DATA 0x00000000
+#define DDRSS0_PHY_523_DATA 0x01000001
+#define DDRSS0_PHY_524_DATA 0x00000100
+#define DDRSS0_PHY_525_DATA 0x000800C0
+#define DDRSS0_PHY_526_DATA 0x060100CC
+#define DDRSS0_PHY_527_DATA 0x00030066
+#define DDRSS0_PHY_528_DATA 0x00000000
+#define DDRSS0_PHY_529_DATA 0x00000301
+#define DDRSS0_PHY_530_DATA 0x0000AAAA
+#define DDRSS0_PHY_531_DATA 0x00005555
+#define DDRSS0_PHY_532_DATA 0x0000B5B5
+#define DDRSS0_PHY_533_DATA 0x00004A4A
+#define DDRSS0_PHY_534_DATA 0x00005656
+#define DDRSS0_PHY_535_DATA 0x0000A9A9
+#define DDRSS0_PHY_536_DATA 0x0000A9A9
+#define DDRSS0_PHY_537_DATA 0x0000B5B5
+#define DDRSS0_PHY_538_DATA 0x00000000
+#define DDRSS0_PHY_539_DATA 0x00000000
+#define DDRSS0_PHY_540_DATA 0x2A000000
+#define DDRSS0_PHY_541_DATA 0x00000808
+#define DDRSS0_PHY_542_DATA 0x0F000000
+#define DDRSS0_PHY_543_DATA 0x00000F0F
+#define DDRSS0_PHY_544_DATA 0x10400000
+#define DDRSS0_PHY_545_DATA 0x0C002006
+#define DDRSS0_PHY_546_DATA 0x00000000
+#define DDRSS0_PHY_547_DATA 0x00000000
+#define DDRSS0_PHY_548_DATA 0x55555555
+#define DDRSS0_PHY_549_DATA 0xAAAAAAAA
+#define DDRSS0_PHY_550_DATA 0x55555555
+#define DDRSS0_PHY_551_DATA 0xAAAAAAAA
+#define DDRSS0_PHY_552_DATA 0x00005555
+#define DDRSS0_PHY_553_DATA 0x01000100
+#define DDRSS0_PHY_554_DATA 0x00800180
+#define DDRSS0_PHY_555_DATA 0x00000001
+#define DDRSS0_PHY_556_DATA 0x00000000
+#define DDRSS0_PHY_557_DATA 0x00000000
+#define DDRSS0_PHY_558_DATA 0x00000000
+#define DDRSS0_PHY_559_DATA 0x00000000
+#define DDRSS0_PHY_560_DATA 0x00000000
+#define DDRSS0_PHY_561_DATA 0x00000000
+#define DDRSS0_PHY_562_DATA 0x00000000
+#define DDRSS0_PHY_563_DATA 0x00000000
+#define DDRSS0_PHY_564_DATA 0x00000000
+#define DDRSS0_PHY_565_DATA 0x00000000
+#define DDRSS0_PHY_566_DATA 0x00000000
+#define DDRSS0_PHY_567_DATA 0x00000000
+#define DDRSS0_PHY_568_DATA 0x00000000
+#define DDRSS0_PHY_569_DATA 0x00000000
+#define DDRSS0_PHY_570_DATA 0x00000000
+#define DDRSS0_PHY_571_DATA 0x00000000
+#define DDRSS0_PHY_572_DATA 0x00000000
+#define DDRSS0_PHY_573_DATA 0x00000000
+#define DDRSS0_PHY_574_DATA 0x00000000
+#define DDRSS0_PHY_575_DATA 0x00000000
+#define DDRSS0_PHY_576_DATA 0x00000000
+#define DDRSS0_PHY_577_DATA 0x00000000
+#define DDRSS0_PHY_578_DATA 0x00000104
+#define DDRSS0_PHY_579_DATA 0x00000120
+#define DDRSS0_PHY_580_DATA 0x00000000
+#define DDRSS0_PHY_581_DATA 0x00000000
+#define DDRSS0_PHY_582_DATA 0x00000000
+#define DDRSS0_PHY_583_DATA 0x00000000
+#define DDRSS0_PHY_584_DATA 0x00000000
+#define DDRSS0_PHY_585_DATA 0x00000000
+#define DDRSS0_PHY_586_DATA 0x00000000
+#define DDRSS0_PHY_587_DATA 0x00000001
+#define DDRSS0_PHY_588_DATA 0x07FF0000
+#define DDRSS0_PHY_589_DATA 0x0080081F
+#define DDRSS0_PHY_590_DATA 0x00081020
+#define DDRSS0_PHY_591_DATA 0x04010000
+#define DDRSS0_PHY_592_DATA 0x00000000
+#define DDRSS0_PHY_593_DATA 0x00000000
+#define DDRSS0_PHY_594_DATA 0x00000000
+#define DDRSS0_PHY_595_DATA 0x00000100
+#define DDRSS0_PHY_596_DATA 0x01CC0C01
+#define DDRSS0_PHY_597_DATA 0x1003CC0C
+#define DDRSS0_PHY_598_DATA 0x20000140
+#define DDRSS0_PHY_599_DATA 0x07FF0200
+#define DDRSS0_PHY_600_DATA 0x0000DD01
+#define DDRSS0_PHY_601_DATA 0x10100303
+#define DDRSS0_PHY_602_DATA 0x10101010
+#define DDRSS0_PHY_603_DATA 0x10101010
+#define DDRSS0_PHY_604_DATA 0x00021010
+#define DDRSS0_PHY_605_DATA 0x00100010
+#define DDRSS0_PHY_606_DATA 0x00100010
+#define DDRSS0_PHY_607_DATA 0x00100010
+#define DDRSS0_PHY_608_DATA 0x00100010
+#define DDRSS0_PHY_609_DATA 0x00050010
+#define DDRSS0_PHY_610_DATA 0x51517041
+#define DDRSS0_PHY_611_DATA 0x31C06001
+#define DDRSS0_PHY_612_DATA 0x07AB0340
+#define DDRSS0_PHY_613_DATA 0x00C0C001
+#define DDRSS0_PHY_614_DATA 0x0E0D0001
+#define DDRSS0_PHY_615_DATA 0x10001000
+#define DDRSS0_PHY_616_DATA 0x0C083E42
+#define DDRSS0_PHY_617_DATA 0x0F0C3701
+#define DDRSS0_PHY_618_DATA 0x01000140
+#define DDRSS0_PHY_619_DATA 0x0C000420
+#define DDRSS0_PHY_620_DATA 0x00000198
+#define DDRSS0_PHY_621_DATA 0x0A0000D0
+#define DDRSS0_PHY_622_DATA 0x00030200
+#define DDRSS0_PHY_623_DATA 0x02800000
+#define DDRSS0_PHY_624_DATA 0x80800000
+#define DDRSS0_PHY_625_DATA 0x000E2010
+#define DDRSS0_PHY_626_DATA 0x76543210
+#define DDRSS0_PHY_627_DATA 0x00000008
+#define DDRSS0_PHY_628_DATA 0x02800280
+#define DDRSS0_PHY_629_DATA 0x02800280
+#define DDRSS0_PHY_630_DATA 0x02800280
+#define DDRSS0_PHY_631_DATA 0x02800280
+#define DDRSS0_PHY_632_DATA 0x00000280
+#define DDRSS0_PHY_633_DATA 0x0000A000
+#define DDRSS0_PHY_634_DATA 0x00A000A0
+#define DDRSS0_PHY_635_DATA 0x00A000A0
+#define DDRSS0_PHY_636_DATA 0x00A000A0
+#define DDRSS0_PHY_637_DATA 0x00A000A0
+#define DDRSS0_PHY_638_DATA 0x00A000A0
+#define DDRSS0_PHY_639_DATA 0x00A000A0
+#define DDRSS0_PHY_640_DATA 0x00A000A0
+#define DDRSS0_PHY_641_DATA 0x00A000A0
+#define DDRSS0_PHY_642_DATA 0x01C200A0
+#define DDRSS0_PHY_643_DATA 0x01A00005
+#define DDRSS0_PHY_644_DATA 0x00000000
+#define DDRSS0_PHY_645_DATA 0x00000000
+#define DDRSS0_PHY_646_DATA 0x00080200
+#define DDRSS0_PHY_647_DATA 0x00000000
+#define DDRSS0_PHY_648_DATA 0x20202000
+#define DDRSS0_PHY_649_DATA 0x20202020
+#define DDRSS0_PHY_650_DATA 0xF0F02020
+#define DDRSS0_PHY_651_DATA 0x00000000
+#define DDRSS0_PHY_652_DATA 0x00000000
+#define DDRSS0_PHY_653_DATA 0x00000000
+#define DDRSS0_PHY_654_DATA 0x00000000
+#define DDRSS0_PHY_655_DATA 0x00000000
+#define DDRSS0_PHY_656_DATA 0x00000000
+#define DDRSS0_PHY_657_DATA 0x00000000
+#define DDRSS0_PHY_658_DATA 0x00000000
+#define DDRSS0_PHY_659_DATA 0x00000000
+#define DDRSS0_PHY_660_DATA 0x00000000
+#define DDRSS0_PHY_661_DATA 0x00000000
+#define DDRSS0_PHY_662_DATA 0x00000000
+#define DDRSS0_PHY_663_DATA 0x00000000
+#define DDRSS0_PHY_664_DATA 0x00000000
+#define DDRSS0_PHY_665_DATA 0x00000000
+#define DDRSS0_PHY_666_DATA 0x00000000
+#define DDRSS0_PHY_667_DATA 0x00000000
+#define DDRSS0_PHY_668_DATA 0x00000000
+#define DDRSS0_PHY_669_DATA 0x00000000
+#define DDRSS0_PHY_670_DATA 0x00000000
+#define DDRSS0_PHY_671_DATA 0x00000000
+#define DDRSS0_PHY_672_DATA 0x00000000
+#define DDRSS0_PHY_673_DATA 0x00000000
+#define DDRSS0_PHY_674_DATA 0x00000000
+#define DDRSS0_PHY_675_DATA 0x00000000
+#define DDRSS0_PHY_676_DATA 0x00000000
+#define DDRSS0_PHY_677_DATA 0x00000000
+#define DDRSS0_PHY_678_DATA 0x00000000
+#define DDRSS0_PHY_679_DATA 0x00000000
+#define DDRSS0_PHY_680_DATA 0x00000000
+#define DDRSS0_PHY_681_DATA 0x00000000
+#define DDRSS0_PHY_682_DATA 0x00000000
+#define DDRSS0_PHY_683_DATA 0x00000000
+#define DDRSS0_PHY_684_DATA 0x00000000
+#define DDRSS0_PHY_685_DATA 0x00000000
+#define DDRSS0_PHY_686_DATA 0x00000000
+#define DDRSS0_PHY_687_DATA 0x00000000
+#define DDRSS0_PHY_688_DATA 0x00000000
+#define DDRSS0_PHY_689_DATA 0x00000000
+#define DDRSS0_PHY_690_DATA 0x00000000
+#define DDRSS0_PHY_691_DATA 0x00000000
+#define DDRSS0_PHY_692_DATA 0x00000000
+#define DDRSS0_PHY_693_DATA 0x00000000
+#define DDRSS0_PHY_694_DATA 0x00000000
+#define DDRSS0_PHY_695_DATA 0x00000000
+#define DDRSS0_PHY_696_DATA 0x00000000
+#define DDRSS0_PHY_697_DATA 0x00000000
+#define DDRSS0_PHY_698_DATA 0x00000000
+#define DDRSS0_PHY_699_DATA 0x00000000
+#define DDRSS0_PHY_700_DATA 0x00000000
+#define DDRSS0_PHY_701_DATA 0x00000000
+#define DDRSS0_PHY_702_DATA 0x00000000
+#define DDRSS0_PHY_703_DATA 0x00000000
+#define DDRSS0_PHY_704_DATA 0x00000000
+#define DDRSS0_PHY_705_DATA 0x00000000
+#define DDRSS0_PHY_706_DATA 0x00000000
+#define DDRSS0_PHY_707_DATA 0x00000000
+#define DDRSS0_PHY_708_DATA 0x00000000
+#define DDRSS0_PHY_709_DATA 0x00000000
+#define DDRSS0_PHY_710_DATA 0x00000000
+#define DDRSS0_PHY_711_DATA 0x00000000
+#define DDRSS0_PHY_712_DATA 0x00000000
+#define DDRSS0_PHY_713_DATA 0x00000000
+#define DDRSS0_PHY_714_DATA 0x00000000
+#define DDRSS0_PHY_715_DATA 0x00000000
+#define DDRSS0_PHY_716_DATA 0x00000000
+#define DDRSS0_PHY_717_DATA 0x00000000
+#define DDRSS0_PHY_718_DATA 0x00000000
+#define DDRSS0_PHY_719_DATA 0x00000000
+#define DDRSS0_PHY_720_DATA 0x00000000
+#define DDRSS0_PHY_721_DATA 0x00000000
+#define DDRSS0_PHY_722_DATA 0x00000000
+#define DDRSS0_PHY_723_DATA 0x00000000
+#define DDRSS0_PHY_724_DATA 0x00000000
+#define DDRSS0_PHY_725_DATA 0x00000000
+#define DDRSS0_PHY_726_DATA 0x00000000
+#define DDRSS0_PHY_727_DATA 0x00000000
+#define DDRSS0_PHY_728_DATA 0x00000000
+#define DDRSS0_PHY_729_DATA 0x00000000
+#define DDRSS0_PHY_730_DATA 0x00000000
+#define DDRSS0_PHY_731_DATA 0x00000000
+#define DDRSS0_PHY_732_DATA 0x00000000
+#define DDRSS0_PHY_733_DATA 0x00000000
+#define DDRSS0_PHY_734_DATA 0x00000000
+#define DDRSS0_PHY_735_DATA 0x00000000
+#define DDRSS0_PHY_736_DATA 0x00000000
+#define DDRSS0_PHY_737_DATA 0x00000000
+#define DDRSS0_PHY_738_DATA 0x00000000
+#define DDRSS0_PHY_739_DATA 0x00000000
+#define DDRSS0_PHY_740_DATA 0x00000000
+#define DDRSS0_PHY_741_DATA 0x00000000
+#define DDRSS0_PHY_742_DATA 0x00000000
+#define DDRSS0_PHY_743_DATA 0x00000000
+#define DDRSS0_PHY_744_DATA 0x00000000
+#define DDRSS0_PHY_745_DATA 0x00000000
+#define DDRSS0_PHY_746_DATA 0x00000000
+#define DDRSS0_PHY_747_DATA 0x00000000
+#define DDRSS0_PHY_748_DATA 0x00000000
+#define DDRSS0_PHY_749_DATA 0x00000000
+#define DDRSS0_PHY_750_DATA 0x00000000
+#define DDRSS0_PHY_751_DATA 0x00000000
+#define DDRSS0_PHY_752_DATA 0x00000000
+#define DDRSS0_PHY_753_DATA 0x00000000
+#define DDRSS0_PHY_754_DATA 0x00000000
+#define DDRSS0_PHY_755_DATA 0x00000000
+#define DDRSS0_PHY_756_DATA 0x00000000
+#define DDRSS0_PHY_757_DATA 0x00000000
+#define DDRSS0_PHY_758_DATA 0x00000000
+#define DDRSS0_PHY_759_DATA 0x00000000
+#define DDRSS0_PHY_760_DATA 0x00000000
+#define DDRSS0_PHY_761_DATA 0x00000000
+#define DDRSS0_PHY_762_DATA 0x00000000
+#define DDRSS0_PHY_763_DATA 0x00000000
+#define DDRSS0_PHY_764_DATA 0x00000000
+#define DDRSS0_PHY_765_DATA 0x00000000
+#define DDRSS0_PHY_766_DATA 0x00000000
+#define DDRSS0_PHY_767_DATA 0x00000000
+#define DDRSS0_PHY_768_DATA 0x000004F0
+#define DDRSS0_PHY_769_DATA 0x00000000
+#define DDRSS0_PHY_770_DATA 0x00030200
+#define DDRSS0_PHY_771_DATA 0x00000000
+#define DDRSS0_PHY_772_DATA 0x00000000
+#define DDRSS0_PHY_773_DATA 0x01030000
+#define DDRSS0_PHY_774_DATA 0x00010000
+#define DDRSS0_PHY_775_DATA 0x01030004
+#define DDRSS0_PHY_776_DATA 0x01000000
+#define DDRSS0_PHY_777_DATA 0x00000000
+#define DDRSS0_PHY_778_DATA 0x00000000
+#define DDRSS0_PHY_779_DATA 0x01000001
+#define DDRSS0_PHY_780_DATA 0x00000100
+#define DDRSS0_PHY_781_DATA 0x000800C0
+#define DDRSS0_PHY_782_DATA 0x060100CC
+#define DDRSS0_PHY_783_DATA 0x00030066
+#define DDRSS0_PHY_784_DATA 0x00000000
+#define DDRSS0_PHY_785_DATA 0x00000301
+#define DDRSS0_PHY_786_DATA 0x0000AAAA
+#define DDRSS0_PHY_787_DATA 0x00005555
+#define DDRSS0_PHY_788_DATA 0x0000B5B5
+#define DDRSS0_PHY_789_DATA 0x00004A4A
+#define DDRSS0_PHY_790_DATA 0x00005656
+#define DDRSS0_PHY_791_DATA 0x0000A9A9
+#define DDRSS0_PHY_792_DATA 0x0000A9A9
+#define DDRSS0_PHY_793_DATA 0x0000B5B5
+#define DDRSS0_PHY_794_DATA 0x00000000
+#define DDRSS0_PHY_795_DATA 0x00000000
+#define DDRSS0_PHY_796_DATA 0x2A000000
+#define DDRSS0_PHY_797_DATA 0x00000808
+#define DDRSS0_PHY_798_DATA 0x0F000000
+#define DDRSS0_PHY_799_DATA 0x00000F0F
+#define DDRSS0_PHY_800_DATA 0x10400000
+#define DDRSS0_PHY_801_DATA 0x0C002006
+#define DDRSS0_PHY_802_DATA 0x00000000
+#define DDRSS0_PHY_803_DATA 0x00000000
+#define DDRSS0_PHY_804_DATA 0x55555555
+#define DDRSS0_PHY_805_DATA 0xAAAAAAAA
+#define DDRSS0_PHY_806_DATA 0x55555555
+#define DDRSS0_PHY_807_DATA 0xAAAAAAAA
+#define DDRSS0_PHY_808_DATA 0x00005555
+#define DDRSS0_PHY_809_DATA 0x01000100
+#define DDRSS0_PHY_810_DATA 0x00800180
+#define DDRSS0_PHY_811_DATA 0x00000000
+#define DDRSS0_PHY_812_DATA 0x00000000
+#define DDRSS0_PHY_813_DATA 0x00000000
+#define DDRSS0_PHY_814_DATA 0x00000000
+#define DDRSS0_PHY_815_DATA 0x00000000
+#define DDRSS0_PHY_816_DATA 0x00000000
+#define DDRSS0_PHY_817_DATA 0x00000000
+#define DDRSS0_PHY_818_DATA 0x00000000
+#define DDRSS0_PHY_819_DATA 0x00000000
+#define DDRSS0_PHY_820_DATA 0x00000000
+#define DDRSS0_PHY_821_DATA 0x00000000
+#define DDRSS0_PHY_822_DATA 0x00000000
+#define DDRSS0_PHY_823_DATA 0x00000000
+#define DDRSS0_PHY_824_DATA 0x00000000
+#define DDRSS0_PHY_825_DATA 0x00000000
+#define DDRSS0_PHY_826_DATA 0x00000000
+#define DDRSS0_PHY_827_DATA 0x00000000
+#define DDRSS0_PHY_828_DATA 0x00000000
+#define DDRSS0_PHY_829_DATA 0x00000000
+#define DDRSS0_PHY_830_DATA 0x00000000
+#define DDRSS0_PHY_831_DATA 0x00000000
+#define DDRSS0_PHY_832_DATA 0x00000000
+#define DDRSS0_PHY_833_DATA 0x00000000
+#define DDRSS0_PHY_834_DATA 0x00000104
+#define DDRSS0_PHY_835_DATA 0x00000120
+#define DDRSS0_PHY_836_DATA 0x00000000
+#define DDRSS0_PHY_837_DATA 0x00000000
+#define DDRSS0_PHY_838_DATA 0x00000000
+#define DDRSS0_PHY_839_DATA 0x00000000
+#define DDRSS0_PHY_840_DATA 0x00000000
+#define DDRSS0_PHY_841_DATA 0x00000000
+#define DDRSS0_PHY_842_DATA 0x00000000
+#define DDRSS0_PHY_843_DATA 0x00000001
+#define DDRSS0_PHY_844_DATA 0x07FF0000
+#define DDRSS0_PHY_845_DATA 0x0080081F
+#define DDRSS0_PHY_846_DATA 0x00081020
+#define DDRSS0_PHY_847_DATA 0x04010000
+#define DDRSS0_PHY_848_DATA 0x00000000
+#define DDRSS0_PHY_849_DATA 0x00000000
+#define DDRSS0_PHY_850_DATA 0x00000000
+#define DDRSS0_PHY_851_DATA 0x00000100
+#define DDRSS0_PHY_852_DATA 0x01CC0C01
+#define DDRSS0_PHY_853_DATA 0x1003CC0C
+#define DDRSS0_PHY_854_DATA 0x20000140
+#define DDRSS0_PHY_855_DATA 0x07FF0200
+#define DDRSS0_PHY_856_DATA 0x0000DD01
+#define DDRSS0_PHY_857_DATA 0x10100303
+#define DDRSS0_PHY_858_DATA 0x10101010
+#define DDRSS0_PHY_859_DATA 0x10101010
+#define DDRSS0_PHY_860_DATA 0x00021010
+#define DDRSS0_PHY_861_DATA 0x00100010
+#define DDRSS0_PHY_862_DATA 0x00100010
+#define DDRSS0_PHY_863_DATA 0x00100010
+#define DDRSS0_PHY_864_DATA 0x00100010
+#define DDRSS0_PHY_865_DATA 0x00050010
+#define DDRSS0_PHY_866_DATA 0x51517041
+#define DDRSS0_PHY_867_DATA 0x31C06001
+#define DDRSS0_PHY_868_DATA 0x07AB0340
+#define DDRSS0_PHY_869_DATA 0x00C0C001
+#define DDRSS0_PHY_870_DATA 0x0E0D0001
+#define DDRSS0_PHY_871_DATA 0x10001000
+#define DDRSS0_PHY_872_DATA 0x0C083E42
+#define DDRSS0_PHY_873_DATA 0x0F0C3701
+#define DDRSS0_PHY_874_DATA 0x01000140
+#define DDRSS0_PHY_875_DATA 0x0C000420
+#define DDRSS0_PHY_876_DATA 0x00000198
+#define DDRSS0_PHY_877_DATA 0x0A0000D0
+#define DDRSS0_PHY_878_DATA 0x00030200
+#define DDRSS0_PHY_879_DATA 0x02800000
+#define DDRSS0_PHY_880_DATA 0x80800000
+#define DDRSS0_PHY_881_DATA 0x000E2010
+#define DDRSS0_PHY_882_DATA 0x76543210
+#define DDRSS0_PHY_883_DATA 0x00000008
+#define DDRSS0_PHY_884_DATA 0x02800280
+#define DDRSS0_PHY_885_DATA 0x02800280
+#define DDRSS0_PHY_886_DATA 0x02800280
+#define DDRSS0_PHY_887_DATA 0x02800280
+#define DDRSS0_PHY_888_DATA 0x00000280
+#define DDRSS0_PHY_889_DATA 0x0000A000
+#define DDRSS0_PHY_890_DATA 0x00A000A0
+#define DDRSS0_PHY_891_DATA 0x00A000A0
+#define DDRSS0_PHY_892_DATA 0x00A000A0
+#define DDRSS0_PHY_893_DATA 0x00A000A0
+#define DDRSS0_PHY_894_DATA 0x00A000A0
+#define DDRSS0_PHY_895_DATA 0x00A000A0
+#define DDRSS0_PHY_896_DATA 0x00A000A0
+#define DDRSS0_PHY_897_DATA 0x00A000A0
+#define DDRSS0_PHY_898_DATA 0x01C200A0
+#define DDRSS0_PHY_899_DATA 0x01A00005
+#define DDRSS0_PHY_900_DATA 0x00000000
+#define DDRSS0_PHY_901_DATA 0x00000000
+#define DDRSS0_PHY_902_DATA 0x00080200
+#define DDRSS0_PHY_903_DATA 0x00000000
+#define DDRSS0_PHY_904_DATA 0x20202000
+#define DDRSS0_PHY_905_DATA 0x20202020
+#define DDRSS0_PHY_906_DATA 0xF0F02020
+#define DDRSS0_PHY_907_DATA 0x00000000
+#define DDRSS0_PHY_908_DATA 0x00000000
+#define DDRSS0_PHY_909_DATA 0x00000000
+#define DDRSS0_PHY_910_DATA 0x00000000
+#define DDRSS0_PHY_911_DATA 0x00000000
+#define DDRSS0_PHY_912_DATA 0x00000000
+#define DDRSS0_PHY_913_DATA 0x00000000
+#define DDRSS0_PHY_914_DATA 0x00000000
+#define DDRSS0_PHY_915_DATA 0x00000000
+#define DDRSS0_PHY_916_DATA 0x00000000
+#define DDRSS0_PHY_917_DATA 0x00000000
+#define DDRSS0_PHY_918_DATA 0x00000000
+#define DDRSS0_PHY_919_DATA 0x00000000
+#define DDRSS0_PHY_920_DATA 0x00000000
+#define DDRSS0_PHY_921_DATA 0x00000000
+#define DDRSS0_PHY_922_DATA 0x00000000
+#define DDRSS0_PHY_923_DATA 0x00000000
+#define DDRSS0_PHY_924_DATA 0x00000000
+#define DDRSS0_PHY_925_DATA 0x00000000
+#define DDRSS0_PHY_926_DATA 0x00000000
+#define DDRSS0_PHY_927_DATA 0x00000000
+#define DDRSS0_PHY_928_DATA 0x00000000
+#define DDRSS0_PHY_929_DATA 0x00000000
+#define DDRSS0_PHY_930_DATA 0x00000000
+#define DDRSS0_PHY_931_DATA 0x00000000
+#define DDRSS0_PHY_932_DATA 0x00000000
+#define DDRSS0_PHY_933_DATA 0x00000000
+#define DDRSS0_PHY_934_DATA 0x00000000
+#define DDRSS0_PHY_935_DATA 0x00000000
+#define DDRSS0_PHY_936_DATA 0x00000000
+#define DDRSS0_PHY_937_DATA 0x00000000
+#define DDRSS0_PHY_938_DATA 0x00000000
+#define DDRSS0_PHY_939_DATA 0x00000000
+#define DDRSS0_PHY_940_DATA 0x00000000
+#define DDRSS0_PHY_941_DATA 0x00000000
+#define DDRSS0_PHY_942_DATA 0x00000000
+#define DDRSS0_PHY_943_DATA 0x00000000
+#define DDRSS0_PHY_944_DATA 0x00000000
+#define DDRSS0_PHY_945_DATA 0x00000000
+#define DDRSS0_PHY_946_DATA 0x00000000
+#define DDRSS0_PHY_947_DATA 0x00000000
+#define DDRSS0_PHY_948_DATA 0x00000000
+#define DDRSS0_PHY_949_DATA 0x00000000
+#define DDRSS0_PHY_950_DATA 0x00000000
+#define DDRSS0_PHY_951_DATA 0x00000000
+#define DDRSS0_PHY_952_DATA 0x00000000
+#define DDRSS0_PHY_953_DATA 0x00000000
+#define DDRSS0_PHY_954_DATA 0x00000000
+#define DDRSS0_PHY_955_DATA 0x00000000
+#define DDRSS0_PHY_956_DATA 0x00000000
+#define DDRSS0_PHY_957_DATA 0x00000000
+#define DDRSS0_PHY_958_DATA 0x00000000
+#define DDRSS0_PHY_959_DATA 0x00000000
+#define DDRSS0_PHY_960_DATA 0x00000000
+#define DDRSS0_PHY_961_DATA 0x00000000
+#define DDRSS0_PHY_962_DATA 0x00000000
+#define DDRSS0_PHY_963_DATA 0x00000000
+#define DDRSS0_PHY_964_DATA 0x00000000
+#define DDRSS0_PHY_965_DATA 0x00000000
+#define DDRSS0_PHY_966_DATA 0x00000000
+#define DDRSS0_PHY_967_DATA 0x00000000
+#define DDRSS0_PHY_968_DATA 0x00000000
+#define DDRSS0_PHY_969_DATA 0x00000000
+#define DDRSS0_PHY_970_DATA 0x00000000
+#define DDRSS0_PHY_971_DATA 0x00000000
+#define DDRSS0_PHY_972_DATA 0x00000000
+#define DDRSS0_PHY_973_DATA 0x00000000
+#define DDRSS0_PHY_974_DATA 0x00000000
+#define DDRSS0_PHY_975_DATA 0x00000000
+#define DDRSS0_PHY_976_DATA 0x00000000
+#define DDRSS0_PHY_977_DATA 0x00000000
+#define DDRSS0_PHY_978_DATA 0x00000000
+#define DDRSS0_PHY_979_DATA 0x00000000
+#define DDRSS0_PHY_980_DATA 0x00000000
+#define DDRSS0_PHY_981_DATA 0x00000000
+#define DDRSS0_PHY_982_DATA 0x00000000
+#define DDRSS0_PHY_983_DATA 0x00000000
+#define DDRSS0_PHY_984_DATA 0x00000000
+#define DDRSS0_PHY_985_DATA 0x00000000
+#define DDRSS0_PHY_986_DATA 0x00000000
+#define DDRSS0_PHY_987_DATA 0x00000000
+#define DDRSS0_PHY_988_DATA 0x00000000
+#define DDRSS0_PHY_989_DATA 0x00000000
+#define DDRSS0_PHY_990_DATA 0x00000000
+#define DDRSS0_PHY_991_DATA 0x00000000
+#define DDRSS0_PHY_992_DATA 0x00000000
+#define DDRSS0_PHY_993_DATA 0x00000000
+#define DDRSS0_PHY_994_DATA 0x00000000
+#define DDRSS0_PHY_995_DATA 0x00000000
+#define DDRSS0_PHY_996_DATA 0x00000000
+#define DDRSS0_PHY_997_DATA 0x00000000
+#define DDRSS0_PHY_998_DATA 0x00000000
+#define DDRSS0_PHY_999_DATA 0x00000000
+#define DDRSS0_PHY_1000_DATA 0x00000000
+#define DDRSS0_PHY_1001_DATA 0x00000000
+#define DDRSS0_PHY_1002_DATA 0x00000000
+#define DDRSS0_PHY_1003_DATA 0x00000000
+#define DDRSS0_PHY_1004_DATA 0x00000000
+#define DDRSS0_PHY_1005_DATA 0x00000000
+#define DDRSS0_PHY_1006_DATA 0x00000000
+#define DDRSS0_PHY_1007_DATA 0x00000000
+#define DDRSS0_PHY_1008_DATA 0x00000000
+#define DDRSS0_PHY_1009_DATA 0x00000000
+#define DDRSS0_PHY_1010_DATA 0x00000000
+#define DDRSS0_PHY_1011_DATA 0x00000000
+#define DDRSS0_PHY_1012_DATA 0x00000000
+#define DDRSS0_PHY_1013_DATA 0x00000000
+#define DDRSS0_PHY_1014_DATA 0x00000000
+#define DDRSS0_PHY_1015_DATA 0x00000000
+#define DDRSS0_PHY_1016_DATA 0x00000000
+#define DDRSS0_PHY_1017_DATA 0x00000000
+#define DDRSS0_PHY_1018_DATA 0x00000000
+#define DDRSS0_PHY_1019_DATA 0x00000000
+#define DDRSS0_PHY_1020_DATA 0x00000000
+#define DDRSS0_PHY_1021_DATA 0x00000000
+#define DDRSS0_PHY_1022_DATA 0x00000000
+#define DDRSS0_PHY_1023_DATA 0x00000000
+#define DDRSS0_PHY_1024_DATA 0x00000000
+#define DDRSS0_PHY_1025_DATA 0x00000000
+#define DDRSS0_PHY_1026_DATA 0x00000000
+#define DDRSS0_PHY_1027_DATA 0x00000000
+#define DDRSS0_PHY_1028_DATA 0x00000000
+#define DDRSS0_PHY_1029_DATA 0x00000100
+#define DDRSS0_PHY_1030_DATA 0x00000200
+#define DDRSS0_PHY_1031_DATA 0x00000000
+#define DDRSS0_PHY_1032_DATA 0x00000000
+#define DDRSS0_PHY_1033_DATA 0x00000000
+#define DDRSS0_PHY_1034_DATA 0x00000000
+#define DDRSS0_PHY_1035_DATA 0x00400000
+#define DDRSS0_PHY_1036_DATA 0x00000080
+#define DDRSS0_PHY_1037_DATA 0x00DCBA98
+#define DDRSS0_PHY_1038_DATA 0x03000000
+#define DDRSS0_PHY_1039_DATA 0x00200000
+#define DDRSS0_PHY_1040_DATA 0x00000000
+#define DDRSS0_PHY_1041_DATA 0x00000000
+#define DDRSS0_PHY_1042_DATA 0x00000000
+#define DDRSS0_PHY_1043_DATA 0x00000000
+#define DDRSS0_PHY_1044_DATA 0x00000000
+#define DDRSS0_PHY_1045_DATA 0x0000002A
+#define DDRSS0_PHY_1046_DATA 0x00000015
+#define DDRSS0_PHY_1047_DATA 0x00000015
+#define DDRSS0_PHY_1048_DATA 0x0000002A
+#define DDRSS0_PHY_1049_DATA 0x00000033
+#define DDRSS0_PHY_1050_DATA 0x0000000C
+#define DDRSS0_PHY_1051_DATA 0x0000000C
+#define DDRSS0_PHY_1052_DATA 0x00000033
+#define DDRSS0_PHY_1053_DATA 0x00543210
+#define DDRSS0_PHY_1054_DATA 0x003F0000
+#define DDRSS0_PHY_1055_DATA 0x000F013F
+#define DDRSS0_PHY_1056_DATA 0x20202003
+#define DDRSS0_PHY_1057_DATA 0x00202020
+#define DDRSS0_PHY_1058_DATA 0x20008008
+#define DDRSS0_PHY_1059_DATA 0x00000810
+#define DDRSS0_PHY_1060_DATA 0x00000F00
+#define DDRSS0_PHY_1061_DATA 0x00000000
+#define DDRSS0_PHY_1062_DATA 0x00000000
+#define DDRSS0_PHY_1063_DATA 0x00000000
+#define DDRSS0_PHY_1064_DATA 0x000305CC
+#define DDRSS0_PHY_1065_DATA 0x00030000
+#define DDRSS0_PHY_1066_DATA 0x00000300
+#define DDRSS0_PHY_1067_DATA 0x00000300
+#define DDRSS0_PHY_1068_DATA 0x00000300
+#define DDRSS0_PHY_1069_DATA 0x00000300
+#define DDRSS0_PHY_1070_DATA 0x00000300
+#define DDRSS0_PHY_1071_DATA 0x42080010
+#define DDRSS0_PHY_1072_DATA 0x0000803E
+#define DDRSS0_PHY_1073_DATA 0x00000001
+#define DDRSS0_PHY_1074_DATA 0x01000102
+#define DDRSS0_PHY_1075_DATA 0x00008000
+#define DDRSS0_PHY_1076_DATA 0x00000000
+#define DDRSS0_PHY_1077_DATA 0x00000000
+#define DDRSS0_PHY_1078_DATA 0x00000000
+#define DDRSS0_PHY_1079_DATA 0x00000000
+#define DDRSS0_PHY_1080_DATA 0x00000000
+#define DDRSS0_PHY_1081_DATA 0x00000000
+#define DDRSS0_PHY_1082_DATA 0x00000000
+#define DDRSS0_PHY_1083_DATA 0x00000000
+#define DDRSS0_PHY_1084_DATA 0x00000000
+#define DDRSS0_PHY_1085_DATA 0x00000000
+#define DDRSS0_PHY_1086_DATA 0x00000000
+#define DDRSS0_PHY_1087_DATA 0x00000000
+#define DDRSS0_PHY_1088_DATA 0x00000000
+#define DDRSS0_PHY_1089_DATA 0x00000000
+#define DDRSS0_PHY_1090_DATA 0x00000000
+#define DDRSS0_PHY_1091_DATA 0x00000000
+#define DDRSS0_PHY_1092_DATA 0x00000000
+#define DDRSS0_PHY_1093_DATA 0x00000000
+#define DDRSS0_PHY_1094_DATA 0x00000000
+#define DDRSS0_PHY_1095_DATA 0x00000000
+#define DDRSS0_PHY_1096_DATA 0x00000000
+#define DDRSS0_PHY_1097_DATA 0x00000000
+#define DDRSS0_PHY_1098_DATA 0x00000000
+#define DDRSS0_PHY_1099_DATA 0x00000000
+#define DDRSS0_PHY_1100_DATA 0x00000000
+#define DDRSS0_PHY_1101_DATA 0x00000000
+#define DDRSS0_PHY_1102_DATA 0x00000000
+#define DDRSS0_PHY_1103_DATA 0x00000000
+#define DDRSS0_PHY_1104_DATA 0x00000000
+#define DDRSS0_PHY_1105_DATA 0x00000000
+#define DDRSS0_PHY_1106_DATA 0x00000000
+#define DDRSS0_PHY_1107_DATA 0x00000000
+#define DDRSS0_PHY_1108_DATA 0x00000000
+#define DDRSS0_PHY_1109_DATA 0x00000000
+#define DDRSS0_PHY_1110_DATA 0x00000000
+#define DDRSS0_PHY_1111_DATA 0x00000000
+#define DDRSS0_PHY_1112_DATA 0x00000000
+#define DDRSS0_PHY_1113_DATA 0x00000000
+#define DDRSS0_PHY_1114_DATA 0x00000000
+#define DDRSS0_PHY_1115_DATA 0x00000000
+#define DDRSS0_PHY_1116_DATA 0x00000000
+#define DDRSS0_PHY_1117_DATA 0x00000000
+#define DDRSS0_PHY_1118_DATA 0x00000000
+#define DDRSS0_PHY_1119_DATA 0x00000000
+#define DDRSS0_PHY_1120_DATA 0x00000000
+#define DDRSS0_PHY_1121_DATA 0x00000000
+#define DDRSS0_PHY_1122_DATA 0x00000000
+#define DDRSS0_PHY_1123_DATA 0x00000000
+#define DDRSS0_PHY_1124_DATA 0x00000000
+#define DDRSS0_PHY_1125_DATA 0x00000000
+#define DDRSS0_PHY_1126_DATA 0x00000000
+#define DDRSS0_PHY_1127_DATA 0x00000000
+#define DDRSS0_PHY_1128_DATA 0x00000000
+#define DDRSS0_PHY_1129_DATA 0x00000000
+#define DDRSS0_PHY_1130_DATA 0x00000000
+#define DDRSS0_PHY_1131_DATA 0x00000000
+#define DDRSS0_PHY_1132_DATA 0x00000000
+#define DDRSS0_PHY_1133_DATA 0x00000000
+#define DDRSS0_PHY_1134_DATA 0x00000000
+#define DDRSS0_PHY_1135_DATA 0x00000000
+#define DDRSS0_PHY_1136_DATA 0x00000000
+#define DDRSS0_PHY_1137_DATA 0x00000000
+#define DDRSS0_PHY_1138_DATA 0x00000000
+#define DDRSS0_PHY_1139_DATA 0x00000000
+#define DDRSS0_PHY_1140_DATA 0x00000000
+#define DDRSS0_PHY_1141_DATA 0x00000000
+#define DDRSS0_PHY_1142_DATA 0x00000000
+#define DDRSS0_PHY_1143_DATA 0x00000000
+#define DDRSS0_PHY_1144_DATA 0x00000000
+#define DDRSS0_PHY_1145_DATA 0x00000000
+#define DDRSS0_PHY_1146_DATA 0x00000000
+#define DDRSS0_PHY_1147_DATA 0x00000000
+#define DDRSS0_PHY_1148_DATA 0x00000000
+#define DDRSS0_PHY_1149_DATA 0x00000000
+#define DDRSS0_PHY_1150_DATA 0x00000000
+#define DDRSS0_PHY_1151_DATA 0x00000000
+#define DDRSS0_PHY_1152_DATA 0x00000000
+#define DDRSS0_PHY_1153_DATA 0x00000000
+#define DDRSS0_PHY_1154_DATA 0x00000000
+#define DDRSS0_PHY_1155_DATA 0x00000000
+#define DDRSS0_PHY_1156_DATA 0x00000000
+#define DDRSS0_PHY_1157_DATA 0x00000000
+#define DDRSS0_PHY_1158_DATA 0x00000000
+#define DDRSS0_PHY_1159_DATA 0x00000000
+#define DDRSS0_PHY_1160_DATA 0x00000000
+#define DDRSS0_PHY_1161_DATA 0x00000000
+#define DDRSS0_PHY_1162_DATA 0x00000000
+#define DDRSS0_PHY_1163_DATA 0x00000000
+#define DDRSS0_PHY_1164_DATA 0x00000000
+#define DDRSS0_PHY_1165_DATA 0x00000000
+#define DDRSS0_PHY_1166_DATA 0x00000000
+#define DDRSS0_PHY_1167_DATA 0x00000000
+#define DDRSS0_PHY_1168_DATA 0x00000000
+#define DDRSS0_PHY_1169_DATA 0x00000000
+#define DDRSS0_PHY_1170_DATA 0x00000000
+#define DDRSS0_PHY_1171_DATA 0x00000000
+#define DDRSS0_PHY_1172_DATA 0x00000000
+#define DDRSS0_PHY_1173_DATA 0x00000000
+#define DDRSS0_PHY_1174_DATA 0x00000000
+#define DDRSS0_PHY_1175_DATA 0x00000000
+#define DDRSS0_PHY_1176_DATA 0x00000000
+#define DDRSS0_PHY_1177_DATA 0x00000000
+#define DDRSS0_PHY_1178_DATA 0x00000000
+#define DDRSS0_PHY_1179_DATA 0x00000000
+#define DDRSS0_PHY_1180_DATA 0x00000000
+#define DDRSS0_PHY_1181_DATA 0x00000000
+#define DDRSS0_PHY_1182_DATA 0x00000000
+#define DDRSS0_PHY_1183_DATA 0x00000000
+#define DDRSS0_PHY_1184_DATA 0x00000000
+#define DDRSS0_PHY_1185_DATA 0x00000000
+#define DDRSS0_PHY_1186_DATA 0x00000000
+#define DDRSS0_PHY_1187_DATA 0x00000000
+#define DDRSS0_PHY_1188_DATA 0x00000000
+#define DDRSS0_PHY_1189_DATA 0x00000000
+#define DDRSS0_PHY_1190_DATA 0x00000000
+#define DDRSS0_PHY_1191_DATA 0x00000000
+#define DDRSS0_PHY_1192_DATA 0x00000000
+#define DDRSS0_PHY_1193_DATA 0x00000000
+#define DDRSS0_PHY_1194_DATA 0x00000000
+#define DDRSS0_PHY_1195_DATA 0x00000000
+#define DDRSS0_PHY_1196_DATA 0x00000000
+#define DDRSS0_PHY_1197_DATA 0x00000000
+#define DDRSS0_PHY_1198_DATA 0x00000000
+#define DDRSS0_PHY_1199_DATA 0x00000000
+#define DDRSS0_PHY_1200_DATA 0x00000000
+#define DDRSS0_PHY_1201_DATA 0x00000000
+#define DDRSS0_PHY_1202_DATA 0x00000000
+#define DDRSS0_PHY_1203_DATA 0x00000000
+#define DDRSS0_PHY_1204_DATA 0x00000000
+#define DDRSS0_PHY_1205_DATA 0x00000000
+#define DDRSS0_PHY_1206_DATA 0x00000000
+#define DDRSS0_PHY_1207_DATA 0x00000000
+#define DDRSS0_PHY_1208_DATA 0x00000000
+#define DDRSS0_PHY_1209_DATA 0x00000000
+#define DDRSS0_PHY_1210_DATA 0x00000000
+#define DDRSS0_PHY_1211_DATA 0x00000000
+#define DDRSS0_PHY_1212_DATA 0x00000000
+#define DDRSS0_PHY_1213_DATA 0x00000000
+#define DDRSS0_PHY_1214_DATA 0x00000000
+#define DDRSS0_PHY_1215_DATA 0x00000000
+#define DDRSS0_PHY_1216_DATA 0x00000000
+#define DDRSS0_PHY_1217_DATA 0x00000000
+#define DDRSS0_PHY_1218_DATA 0x00000000
+#define DDRSS0_PHY_1219_DATA 0x00000000
+#define DDRSS0_PHY_1220_DATA 0x00000000
+#define DDRSS0_PHY_1221_DATA 0x00000000
+#define DDRSS0_PHY_1222_DATA 0x00000000
+#define DDRSS0_PHY_1223_DATA 0x00000000
+#define DDRSS0_PHY_1224_DATA 0x00000000
+#define DDRSS0_PHY_1225_DATA 0x00000000
+#define DDRSS0_PHY_1226_DATA 0x00000000
+#define DDRSS0_PHY_1227_DATA 0x00000000
+#define DDRSS0_PHY_1228_DATA 0x00000000
+#define DDRSS0_PHY_1229_DATA 0x00000000
+#define DDRSS0_PHY_1230_DATA 0x00000000
+#define DDRSS0_PHY_1231_DATA 0x00000000
+#define DDRSS0_PHY_1232_DATA 0x00000000
+#define DDRSS0_PHY_1233_DATA 0x00000000
+#define DDRSS0_PHY_1234_DATA 0x00000000
+#define DDRSS0_PHY_1235_DATA 0x00000000
+#define DDRSS0_PHY_1236_DATA 0x00000000
+#define DDRSS0_PHY_1237_DATA 0x00000000
+#define DDRSS0_PHY_1238_DATA 0x00000000
+#define DDRSS0_PHY_1239_DATA 0x00000000
+#define DDRSS0_PHY_1240_DATA 0x00000000
+#define DDRSS0_PHY_1241_DATA 0x00000000
+#define DDRSS0_PHY_1242_DATA 0x00000000
+#define DDRSS0_PHY_1243_DATA 0x00000000
+#define DDRSS0_PHY_1244_DATA 0x00000000
+#define DDRSS0_PHY_1245_DATA 0x00000000
+#define DDRSS0_PHY_1246_DATA 0x00000000
+#define DDRSS0_PHY_1247_DATA 0x00000000
+#define DDRSS0_PHY_1248_DATA 0x00000000
+#define DDRSS0_PHY_1249_DATA 0x00000000
+#define DDRSS0_PHY_1250_DATA 0x00000000
+#define DDRSS0_PHY_1251_DATA 0x00000000
+#define DDRSS0_PHY_1252_DATA 0x00000000
+#define DDRSS0_PHY_1253_DATA 0x00000000
+#define DDRSS0_PHY_1254_DATA 0x00000000
+#define DDRSS0_PHY_1255_DATA 0x00000000
+#define DDRSS0_PHY_1256_DATA 0x00000000
+#define DDRSS0_PHY_1257_DATA 0x00000000
+#define DDRSS0_PHY_1258_DATA 0x00000000
+#define DDRSS0_PHY_1259_DATA 0x00000000
+#define DDRSS0_PHY_1260_DATA 0x00000000
+#define DDRSS0_PHY_1261_DATA 0x00000000
+#define DDRSS0_PHY_1262_DATA 0x00000000
+#define DDRSS0_PHY_1263_DATA 0x00000000
+#define DDRSS0_PHY_1264_DATA 0x00000000
+#define DDRSS0_PHY_1265_DATA 0x00000000
+#define DDRSS0_PHY_1266_DATA 0x00000000
+#define DDRSS0_PHY_1267_DATA 0x00000000
+#define DDRSS0_PHY_1268_DATA 0x00000000
+#define DDRSS0_PHY_1269_DATA 0x00000000
+#define DDRSS0_PHY_1270_DATA 0x00000000
+#define DDRSS0_PHY_1271_DATA 0x00000000
+#define DDRSS0_PHY_1272_DATA 0x00000000
+#define DDRSS0_PHY_1273_DATA 0x00000000
+#define DDRSS0_PHY_1274_DATA 0x00000000
+#define DDRSS0_PHY_1275_DATA 0x00000000
+#define DDRSS0_PHY_1276_DATA 0x00000000
+#define DDRSS0_PHY_1277_DATA 0x00000000
+#define DDRSS0_PHY_1278_DATA 0x00000000
+#define DDRSS0_PHY_1279_DATA 0x00000000
+#define DDRSS0_PHY_1280_DATA 0x00000000
+#define DDRSS0_PHY_1281_DATA 0x00010100
+#define DDRSS0_PHY_1282_DATA 0x00000000
+#define DDRSS0_PHY_1283_DATA 0x00000000
+#define DDRSS0_PHY_1284_DATA 0x00050000
+#define DDRSS0_PHY_1285_DATA 0x04000000
+#define DDRSS0_PHY_1286_DATA 0x00000055
+#define DDRSS0_PHY_1287_DATA 0x00000000
+#define DDRSS0_PHY_1288_DATA 0x00000000
+#define DDRSS0_PHY_1289_DATA 0x00000000
+#define DDRSS0_PHY_1290_DATA 0x00000000
+#define DDRSS0_PHY_1291_DATA 0x00002001
+#define DDRSS0_PHY_1292_DATA 0x0000400F
+#define DDRSS0_PHY_1293_DATA 0x50020028
+#define DDRSS0_PHY_1294_DATA 0x01010000
+#define DDRSS0_PHY_1295_DATA 0x80080001
+#define DDRSS0_PHY_1296_DATA 0x10200000
+#define DDRSS0_PHY_1297_DATA 0x00000008
+#define DDRSS0_PHY_1298_DATA 0x00000000
+#define DDRSS0_PHY_1299_DATA 0x01090E00
+#define DDRSS0_PHY_1300_DATA 0x00040101
+#define DDRSS0_PHY_1301_DATA 0x0000010F
+#define DDRSS0_PHY_1302_DATA 0x00000000
+#define DDRSS0_PHY_1303_DATA 0x0000FFFF
+#define DDRSS0_PHY_1304_DATA 0x00000000
+#define DDRSS0_PHY_1305_DATA 0x01010000
+#define DDRSS0_PHY_1306_DATA 0x01080402
+#define DDRSS0_PHY_1307_DATA 0x01200F02
+#define DDRSS0_PHY_1308_DATA 0x00194280
+#define DDRSS0_PHY_1309_DATA 0x00000004
+#define DDRSS0_PHY_1310_DATA 0x00042000
+#define DDRSS0_PHY_1311_DATA 0x00000000
+#define DDRSS0_PHY_1312_DATA 0x00000000
+#define DDRSS0_PHY_1313_DATA 0x00000000
+#define DDRSS0_PHY_1314_DATA 0x00000000
+#define DDRSS0_PHY_1315_DATA 0x00000000
+#define DDRSS0_PHY_1316_DATA 0x00000000
+#define DDRSS0_PHY_1317_DATA 0x01000000
+#define DDRSS0_PHY_1318_DATA 0x00000705
+#define DDRSS0_PHY_1319_DATA 0x00000054
+#define DDRSS0_PHY_1320_DATA 0x00030820
+#define DDRSS0_PHY_1321_DATA 0x00010820
+#define DDRSS0_PHY_1322_DATA 0x00010820
+#define DDRSS0_PHY_1323_DATA 0x00010820
+#define DDRSS0_PHY_1324_DATA 0x00010820
+#define DDRSS0_PHY_1325_DATA 0x00010820
+#define DDRSS0_PHY_1326_DATA 0x00010820
+#define DDRSS0_PHY_1327_DATA 0x00010820
+#define DDRSS0_PHY_1328_DATA 0x00010820
+#define DDRSS0_PHY_1329_DATA 0x00000000
+#define DDRSS0_PHY_1330_DATA 0x00000074
+#define DDRSS0_PHY_1331_DATA 0x00000400
+#define DDRSS0_PHY_1332_DATA 0x00000108
+#define DDRSS0_PHY_1333_DATA 0x00000000
+#define DDRSS0_PHY_1334_DATA 0x00000000
+#define DDRSS0_PHY_1335_DATA 0x00000000
+#define DDRSS0_PHY_1336_DATA 0x00000000
+#define DDRSS0_PHY_1337_DATA 0x00000000
+#define DDRSS0_PHY_1338_DATA 0x03000000
+#define DDRSS0_PHY_1339_DATA 0x00000000
+#define DDRSS0_PHY_1340_DATA 0x00000000
+#define DDRSS0_PHY_1341_DATA 0x00000000
+#define DDRSS0_PHY_1342_DATA 0x04102006
+#define DDRSS0_PHY_1343_DATA 0x00041020
+#define DDRSS0_PHY_1344_DATA 0x01C98C98
+#define DDRSS0_PHY_1345_DATA 0x3F400000
+#define DDRSS0_PHY_1346_DATA 0x3F3F1F3F
+#define DDRSS0_PHY_1347_DATA 0x0000001F
+#define DDRSS0_PHY_1348_DATA 0x00000000
+#define DDRSS0_PHY_1349_DATA 0x00000000
+#define DDRSS0_PHY_1350_DATA 0x00000000
+#define DDRSS0_PHY_1351_DATA 0x00010000
+#define DDRSS0_PHY_1352_DATA 0x00000000
+#define DDRSS0_PHY_1353_DATA 0x00000000
+#define DDRSS0_PHY_1354_DATA 0x00000000
+#define DDRSS0_PHY_1355_DATA 0x00000000
+#define DDRSS0_PHY_1356_DATA 0x76543210
+#define DDRSS0_PHY_1357_DATA 0x00010198
+#define DDRSS0_PHY_1358_DATA 0x00000000
+#define DDRSS0_PHY_1359_DATA 0x00000000
+#define DDRSS0_PHY_1360_DATA 0x00000000
+#define DDRSS0_PHY_1361_DATA 0x00040700
+#define DDRSS0_PHY_1362_DATA 0x00000000
+#define DDRSS0_PHY_1363_DATA 0x00000000
+#define DDRSS0_PHY_1364_DATA 0x00000000
+#define DDRSS0_PHY_1365_DATA 0x00000000
+#define DDRSS0_PHY_1366_DATA 0x00000000
+#define DDRSS0_PHY_1367_DATA 0x00000002
+#define DDRSS0_PHY_1368_DATA 0x00000000
+#define DDRSS0_PHY_1369_DATA 0x00000000
+#define DDRSS0_PHY_1370_DATA 0x00000000
+#define DDRSS0_PHY_1371_DATA 0x00000000
+#define DDRSS0_PHY_1372_DATA 0x00000000
+#define DDRSS0_PHY_1373_DATA 0x00000000
+#define DDRSS0_PHY_1374_DATA 0x00080000
+#define DDRSS0_PHY_1375_DATA 0x000007FF
+#define DDRSS0_PHY_1376_DATA 0x00000000
+#define DDRSS0_PHY_1377_DATA 0x00000000
+#define DDRSS0_PHY_1378_DATA 0x00000000
+#define DDRSS0_PHY_1379_DATA 0x00000000
+#define DDRSS0_PHY_1380_DATA 0x00000000
+#define DDRSS0_PHY_1381_DATA 0x00000000
+#define DDRSS0_PHY_1382_DATA 0x000FFFFF
+#define DDRSS0_PHY_1383_DATA 0x000FFFFF
+#define DDRSS0_PHY_1384_DATA 0x0000FFFF
+#define DDRSS0_PHY_1385_DATA 0xFFFFFFF0
+#define DDRSS0_PHY_1386_DATA 0x030FFFFF
+#define DDRSS0_PHY_1387_DATA 0x01FFFFFF
+#define DDRSS0_PHY_1388_DATA 0x0000FFFF
+#define DDRSS0_PHY_1389_DATA 0x00000000
+#define DDRSS0_PHY_1390_DATA 0x00000000
+#define DDRSS0_PHY_1391_DATA 0x00000000
+#define DDRSS0_PHY_1392_DATA 0x00000000
+#define DDRSS0_PHY_1393_DATA 0x0001F7C0
+#define DDRSS0_PHY_1394_DATA 0x00000003
+#define DDRSS0_PHY_1395_DATA 0x00000000
+#define DDRSS0_PHY_1396_DATA 0x00001142
+#define DDRSS0_PHY_1397_DATA 0x010207AB
+#define DDRSS0_PHY_1398_DATA 0x01000080
+#define DDRSS0_PHY_1399_DATA 0x03900390
+#define DDRSS0_PHY_1400_DATA 0x03900390
+#define DDRSS0_PHY_1401_DATA 0x00000390
+#define DDRSS0_PHY_1402_DATA 0x00000390
+#define DDRSS0_PHY_1403_DATA 0x00000390
+#define DDRSS0_PHY_1404_DATA 0x00000390
+#define DDRSS0_PHY_1405_DATA 0x00000005
+#define DDRSS0_PHY_1406_DATA 0x01813FCC
+#define DDRSS0_PHY_1407_DATA 0x000000CC
+#define DDRSS0_PHY_1408_DATA 0x0C000DFF
+#define DDRSS0_PHY_1409_DATA 0x30000DFF
+#define DDRSS0_PHY_1410_DATA 0x3F0DFF11
+#define DDRSS0_PHY_1411_DATA 0x000100F0
+#define DDRSS0_PHY_1412_DATA 0x780DFFCC
+#define DDRSS0_PHY_1413_DATA 0x00007E31
+#define DDRSS0_PHY_1414_DATA 0x000CBF11
+#define DDRSS0_PHY_1415_DATA 0x01990010
+#define DDRSS0_PHY_1416_DATA 0x000CBF11
+#define DDRSS0_PHY_1417_DATA 0x01990010
+#define DDRSS0_PHY_1418_DATA 0x3F0DFF11
+#define DDRSS0_PHY_1419_DATA 0x00EF00F0
+#define DDRSS0_PHY_1420_DATA 0x3F0DFF11
+#define DDRSS0_PHY_1421_DATA 0x01FF00F0
+#define DDRSS0_PHY_1422_DATA 0x20040006
+
+#define DDRSS1_CTL_00_DATA 0x00000B00
+#define DDRSS1_CTL_01_DATA 0x00000000
+#define DDRSS1_CTL_02_DATA 0x00000000
+#define DDRSS1_CTL_03_DATA 0x00000000
+#define DDRSS1_CTL_04_DATA 0x00000000
+#define DDRSS1_CTL_05_DATA 0x00000000
+#define DDRSS1_CTL_06_DATA 0x00000000
+#define DDRSS1_CTL_07_DATA 0x00002AF8
+#define DDRSS1_CTL_08_DATA 0x0001ADAF
+#define DDRSS1_CTL_09_DATA 0x00000005
+#define DDRSS1_CTL_10_DATA 0x0000006E
+#define DDRSS1_CTL_11_DATA 0x000681C8
+#define DDRSS1_CTL_12_DATA 0x004111C9
+#define DDRSS1_CTL_13_DATA 0x00000005
+#define DDRSS1_CTL_14_DATA 0x000010A9
+#define DDRSS1_CTL_15_DATA 0x000681C8
+#define DDRSS1_CTL_16_DATA 0x004111C9
+#define DDRSS1_CTL_17_DATA 0x00000005
+#define DDRSS1_CTL_18_DATA 0x000010A9
+#define DDRSS1_CTL_19_DATA 0x01010000
+#define DDRSS1_CTL_20_DATA 0x02011001
+#define DDRSS1_CTL_21_DATA 0x02010000
+#define DDRSS1_CTL_22_DATA 0x00020100
+#define DDRSS1_CTL_23_DATA 0x0000000B
+#define DDRSS1_CTL_24_DATA 0x0000001C
+#define DDRSS1_CTL_25_DATA 0x00000000
+#define DDRSS1_CTL_26_DATA 0x00000000
+#define DDRSS1_CTL_27_DATA 0x03020200
+#define DDRSS1_CTL_28_DATA 0x00005656
+#define DDRSS1_CTL_29_DATA 0x00100000
+#define DDRSS1_CTL_30_DATA 0x00000000
+#define DDRSS1_CTL_31_DATA 0x00000000
+#define DDRSS1_CTL_32_DATA 0x00000000
+#define DDRSS1_CTL_33_DATA 0x00000000
+#define DDRSS1_CTL_34_DATA 0x040C0000
+#define DDRSS1_CTL_35_DATA 0x12481248
+#define DDRSS1_CTL_36_DATA 0x00050804
+#define DDRSS1_CTL_37_DATA 0x09040008
+#define DDRSS1_CTL_38_DATA 0x15000204
+#define DDRSS1_CTL_39_DATA 0x1760008B
+#define DDRSS1_CTL_40_DATA 0x1500422B
+#define DDRSS1_CTL_41_DATA 0x1760008B
+#define DDRSS1_CTL_42_DATA 0x2000422B
+#define DDRSS1_CTL_43_DATA 0x000A0A09
+#define DDRSS1_CTL_44_DATA 0x0400078A
+#define DDRSS1_CTL_45_DATA 0x1E161104
+#define DDRSS1_CTL_46_DATA 0x10012458
+#define DDRSS1_CTL_47_DATA 0x1E161110
+#define DDRSS1_CTL_48_DATA 0x10012458
+#define DDRSS1_CTL_49_DATA 0x02030410
+#define DDRSS1_CTL_50_DATA 0x2C040500
+#define DDRSS1_CTL_51_DATA 0x08292C29
+#define DDRSS1_CTL_52_DATA 0x14000E0A
+#define DDRSS1_CTL_53_DATA 0x04010A0A
+#define DDRSS1_CTL_54_DATA 0x01010004
+#define DDRSS1_CTL_55_DATA 0x04545408
+#define DDRSS1_CTL_56_DATA 0x04313104
+#define DDRSS1_CTL_57_DATA 0x00003131
+#define DDRSS1_CTL_58_DATA 0x00010100
+#define DDRSS1_CTL_59_DATA 0x03010000
+#define DDRSS1_CTL_60_DATA 0x00001508
+#define DDRSS1_CTL_61_DATA 0x000000CE
+#define DDRSS1_CTL_62_DATA 0x0000032B
+#define DDRSS1_CTL_63_DATA 0x00002073
+#define DDRSS1_CTL_64_DATA 0x0000032B
+#define DDRSS1_CTL_65_DATA 0x00002073
+#define DDRSS1_CTL_66_DATA 0x00000005
+#define DDRSS1_CTL_67_DATA 0x00050000
+#define DDRSS1_CTL_68_DATA 0x00CB0012
+#define DDRSS1_CTL_69_DATA 0x00CB0408
+#define DDRSS1_CTL_70_DATA 0x00400408
+#define DDRSS1_CTL_71_DATA 0x00120103
+#define DDRSS1_CTL_72_DATA 0x00100005
+#define DDRSS1_CTL_73_DATA 0x2F080010
+#define DDRSS1_CTL_74_DATA 0x0505012F
+#define DDRSS1_CTL_75_DATA 0x0401030A
+#define DDRSS1_CTL_76_DATA 0x041E100B
+#define DDRSS1_CTL_77_DATA 0x100B0401
+#define DDRSS1_CTL_78_DATA 0x0001041E
+#define DDRSS1_CTL_79_DATA 0x00160016
+#define DDRSS1_CTL_80_DATA 0x033B033B
+#define DDRSS1_CTL_81_DATA 0x033B033B
+#define DDRSS1_CTL_82_DATA 0x03050505
+#define DDRSS1_CTL_83_DATA 0x03010303
+#define DDRSS1_CTL_84_DATA 0x200B100B
+#define DDRSS1_CTL_85_DATA 0x04041004
+#define DDRSS1_CTL_86_DATA 0x200B100B
+#define DDRSS1_CTL_87_DATA 0x04041004
+#define DDRSS1_CTL_88_DATA 0x03010000
+#define DDRSS1_CTL_89_DATA 0x00010000
+#define DDRSS1_CTL_90_DATA 0x00000000
+#define DDRSS1_CTL_91_DATA 0x00000000
+#define DDRSS1_CTL_92_DATA 0x01000000
+#define DDRSS1_CTL_93_DATA 0x80104002
+#define DDRSS1_CTL_94_DATA 0x00000000
+#define DDRSS1_CTL_95_DATA 0x00040005
+#define DDRSS1_CTL_96_DATA 0x00000000
+#define DDRSS1_CTL_97_DATA 0x00050000
+#define DDRSS1_CTL_98_DATA 0x00000004
+#define DDRSS1_CTL_99_DATA 0x00000000
+#define DDRSS1_CTL_100_DATA 0x00040005
+#define DDRSS1_CTL_101_DATA 0x00000000
+#define DDRSS1_CTL_102_DATA 0x00003380
+#define DDRSS1_CTL_103_DATA 0x00003380
+#define DDRSS1_CTL_104_DATA 0x00003380
+#define DDRSS1_CTL_105_DATA 0x00003380
+#define DDRSS1_CTL_106_DATA 0x00003380
+#define DDRSS1_CTL_107_DATA 0x00000000
+#define DDRSS1_CTL_108_DATA 0x000005A2
+#define DDRSS1_CTL_109_DATA 0x00081CC0
+#define DDRSS1_CTL_110_DATA 0x00081CC0
+#define DDRSS1_CTL_111_DATA 0x00081CC0
+#define DDRSS1_CTL_112_DATA 0x00081CC0
+#define DDRSS1_CTL_113_DATA 0x00081CC0
+#define DDRSS1_CTL_114_DATA 0x00000000
+#define DDRSS1_CTL_115_DATA 0x0000E325
+#define DDRSS1_CTL_116_DATA 0x00081CC0
+#define DDRSS1_CTL_117_DATA 0x00081CC0
+#define DDRSS1_CTL_118_DATA 0x00081CC0
+#define DDRSS1_CTL_119_DATA 0x00081CC0
+#define DDRSS1_CTL_120_DATA 0x00081CC0
+#define DDRSS1_CTL_121_DATA 0x00000000
+#define DDRSS1_CTL_122_DATA 0x0000E325
+#define DDRSS1_CTL_123_DATA 0x00000000
+#define DDRSS1_CTL_124_DATA 0x00000000
+#define DDRSS1_CTL_125_DATA 0x00000000
+#define DDRSS1_CTL_126_DATA 0x00000000
+#define DDRSS1_CTL_127_DATA 0x00000000
+#define DDRSS1_CTL_128_DATA 0x00000000
+#define DDRSS1_CTL_129_DATA 0x00000000
+#define DDRSS1_CTL_130_DATA 0x00000000
+#define DDRSS1_CTL_131_DATA 0x0B030500
+#define DDRSS1_CTL_132_DATA 0x00040B04
+#define DDRSS1_CTL_133_DATA 0x0A090000
+#define DDRSS1_CTL_134_DATA 0x0A090701
+#define DDRSS1_CTL_135_DATA 0x0900000E
+#define DDRSS1_CTL_136_DATA 0x0907010A
+#define DDRSS1_CTL_137_DATA 0x00000E0A
+#define DDRSS1_CTL_138_DATA 0x07010A09
+#define DDRSS1_CTL_139_DATA 0x000E0A09
+#define DDRSS1_CTL_140_DATA 0x07000401
+#define DDRSS1_CTL_141_DATA 0x00000000
+#define DDRSS1_CTL_142_DATA 0x00000000
+#define DDRSS1_CTL_143_DATA 0x00000000
+#define DDRSS1_CTL_144_DATA 0x00000000
+#define DDRSS1_CTL_145_DATA 0x00000000
+#define DDRSS1_CTL_146_DATA 0x00000000
+#define DDRSS1_CTL_147_DATA 0x00000000
+#define DDRSS1_CTL_148_DATA 0x08080000
+#define DDRSS1_CTL_149_DATA 0x01000000
+#define DDRSS1_CTL_150_DATA 0x800000C0
+#define DDRSS1_CTL_151_DATA 0x800000C0
+#define DDRSS1_CTL_152_DATA 0x800000C0
+#define DDRSS1_CTL_153_DATA 0x00000000
+#define DDRSS1_CTL_154_DATA 0x00001500
+#define DDRSS1_CTL_155_DATA 0x00000000
+#define DDRSS1_CTL_156_DATA 0x00000001
+#define DDRSS1_CTL_157_DATA 0x00000002
+#define DDRSS1_CTL_158_DATA 0x0000100E
+#define DDRSS1_CTL_159_DATA 0x00000000
+#define DDRSS1_CTL_160_DATA 0x00000000
+#define DDRSS1_CTL_161_DATA 0x00000000
+#define DDRSS1_CTL_162_DATA 0x00000000
+#define DDRSS1_CTL_163_DATA 0x00000000
+#define DDRSS1_CTL_164_DATA 0x000B0000
+#define DDRSS1_CTL_165_DATA 0x000E0006
+#define DDRSS1_CTL_166_DATA 0x000E0404
+#define DDRSS1_CTL_167_DATA 0x00D601AB
+#define DDRSS1_CTL_168_DATA 0x10100216
+#define DDRSS1_CTL_169_DATA 0x01AB0216
+#define DDRSS1_CTL_170_DATA 0x021600D6
+#define DDRSS1_CTL_171_DATA 0x02161010
+#define DDRSS1_CTL_172_DATA 0x00000000
+#define DDRSS1_CTL_173_DATA 0x00000000
+#define DDRSS1_CTL_174_DATA 0x00000000
+#define DDRSS1_CTL_175_DATA 0x3FF40084
+#define DDRSS1_CTL_176_DATA 0x33003FF4
+#define DDRSS1_CTL_177_DATA 0x00003333
+#define DDRSS1_CTL_178_DATA 0x35000000
+#define DDRSS1_CTL_179_DATA 0x27270035
+#define DDRSS1_CTL_180_DATA 0x0F0F0000
+#define DDRSS1_CTL_181_DATA 0x16000000
+#define DDRSS1_CTL_182_DATA 0x00841616
+#define DDRSS1_CTL_183_DATA 0x3FF43FF4
+#define DDRSS1_CTL_184_DATA 0x33333300
+#define DDRSS1_CTL_185_DATA 0x00000000
+#define DDRSS1_CTL_186_DATA 0x00353500
+#define DDRSS1_CTL_187_DATA 0x00002727
+#define DDRSS1_CTL_188_DATA 0x00000F0F
+#define DDRSS1_CTL_189_DATA 0x16161600
+#define DDRSS1_CTL_190_DATA 0x00000020
+#define DDRSS1_CTL_191_DATA 0x00000000
+#define DDRSS1_CTL_192_DATA 0x00000001
+#define DDRSS1_CTL_193_DATA 0x00000000
+#define DDRSS1_CTL_194_DATA 0x01000000
+#define DDRSS1_CTL_195_DATA 0x00000001
+#define DDRSS1_CTL_196_DATA 0x00000000
+#define DDRSS1_CTL_197_DATA 0x00000000
+#define DDRSS1_CTL_198_DATA 0x00000000
+#define DDRSS1_CTL_199_DATA 0x00000000
+#define DDRSS1_CTL_200_DATA 0x00000000
+#define DDRSS1_CTL_201_DATA 0x00000000
+#define DDRSS1_CTL_202_DATA 0x00000000
+#define DDRSS1_CTL_203_DATA 0x00000000
+#define DDRSS1_CTL_204_DATA 0x00000000
+#define DDRSS1_CTL_205_DATA 0x00000000
+#define DDRSS1_CTL_206_DATA 0x02000000
+#define DDRSS1_CTL_207_DATA 0x01080101
+#define DDRSS1_CTL_208_DATA 0x00000000
+#define DDRSS1_CTL_209_DATA 0x00000000
+#define DDRSS1_CTL_210_DATA 0x00000000
+#define DDRSS1_CTL_211_DATA 0x00000000
+#define DDRSS1_CTL_212_DATA 0x00000000
+#define DDRSS1_CTL_213_DATA 0x00000000
+#define DDRSS1_CTL_214_DATA 0x00000000
+#define DDRSS1_CTL_215_DATA 0x00000000
+#define DDRSS1_CTL_216_DATA 0x00000000
+#define DDRSS1_CTL_217_DATA 0x00000000
+#define DDRSS1_CTL_218_DATA 0x00000000
+#define DDRSS1_CTL_219_DATA 0x00000000
+#define DDRSS1_CTL_220_DATA 0x00000000
+#define DDRSS1_CTL_221_DATA 0x00000000
+#define DDRSS1_CTL_222_DATA 0x00001000
+#define DDRSS1_CTL_223_DATA 0x006403E8
+#define DDRSS1_CTL_224_DATA 0x00000000
+#define DDRSS1_CTL_225_DATA 0x00000000
+#define DDRSS1_CTL_226_DATA 0x00000000
+#define DDRSS1_CTL_227_DATA 0x15110000
+#define DDRSS1_CTL_228_DATA 0x00040C18
+#define DDRSS1_CTL_229_DATA 0xF000C000
+#define DDRSS1_CTL_230_DATA 0x0000F000
+#define DDRSS1_CTL_231_DATA 0x00000000
+#define DDRSS1_CTL_232_DATA 0x00000000
+#define DDRSS1_CTL_233_DATA 0xC0000000
+#define DDRSS1_CTL_234_DATA 0xF000F000
+#define DDRSS1_CTL_235_DATA 0x00000000
+#define DDRSS1_CTL_236_DATA 0x00000000
+#define DDRSS1_CTL_237_DATA 0x00000000
+#define DDRSS1_CTL_238_DATA 0xF000C000
+#define DDRSS1_CTL_239_DATA 0x0000F000
+#define DDRSS1_CTL_240_DATA 0x00000000
+#define DDRSS1_CTL_241_DATA 0x00000000
+#define DDRSS1_CTL_242_DATA 0x00030000
+#define DDRSS1_CTL_243_DATA 0x00000000
+#define DDRSS1_CTL_244_DATA 0x00000000
+#define DDRSS1_CTL_245_DATA 0x00000000
+#define DDRSS1_CTL_246_DATA 0x00000000
+#define DDRSS1_CTL_247_DATA 0x00000000
+#define DDRSS1_CTL_248_DATA 0x00000000
+#define DDRSS1_CTL_249_DATA 0x00000000
+#define DDRSS1_CTL_250_DATA 0x00000000
+#define DDRSS1_CTL_251_DATA 0x00000000
+#define DDRSS1_CTL_252_DATA 0x00000000
+#define DDRSS1_CTL_253_DATA 0x00000000
+#define DDRSS1_CTL_254_DATA 0x00000000
+#define DDRSS1_CTL_255_DATA 0x00000000
+#define DDRSS1_CTL_256_DATA 0x00000000
+#define DDRSS1_CTL_257_DATA 0x01000200
+#define DDRSS1_CTL_258_DATA 0x00370040
+#define DDRSS1_CTL_259_DATA 0x00020008
+#define DDRSS1_CTL_260_DATA 0x00400100
+#define DDRSS1_CTL_261_DATA 0x00400855
+#define DDRSS1_CTL_262_DATA 0x01000200
+#define DDRSS1_CTL_263_DATA 0x08550040
+#define DDRSS1_CTL_264_DATA 0x00000040
+#define DDRSS1_CTL_265_DATA 0x006B0003
+#define DDRSS1_CTL_266_DATA 0x0100006B
+#define DDRSS1_CTL_267_DATA 0x03030303
+#define DDRSS1_CTL_268_DATA 0x00000000
+#define DDRSS1_CTL_269_DATA 0x00000202
+#define DDRSS1_CTL_270_DATA 0x00001FFF
+#define DDRSS1_CTL_271_DATA 0x3FFF2000
+#define DDRSS1_CTL_272_DATA 0x03FF0000
+#define DDRSS1_CTL_273_DATA 0x000103FF
+#define DDRSS1_CTL_274_DATA 0x0FFF0B00
+#define DDRSS1_CTL_275_DATA 0x01010001
+#define DDRSS1_CTL_276_DATA 0x01010101
+#define DDRSS1_CTL_277_DATA 0x01180101
+#define DDRSS1_CTL_278_DATA 0x00030000
+#define DDRSS1_CTL_279_DATA 0x00000000
+#define DDRSS1_CTL_280_DATA 0x00000000
+#define DDRSS1_CTL_281_DATA 0x00000000
+#define DDRSS1_CTL_282_DATA 0x00000000
+#define DDRSS1_CTL_283_DATA 0x00000000
+#define DDRSS1_CTL_284_DATA 0x00000000
+#define DDRSS1_CTL_285_DATA 0x00000000
+#define DDRSS1_CTL_286_DATA 0x00040101
+#define DDRSS1_CTL_287_DATA 0x04010100
+#define DDRSS1_CTL_288_DATA 0x00000000
+#define DDRSS1_CTL_289_DATA 0x00000000
+#define DDRSS1_CTL_290_DATA 0x03030300
+#define DDRSS1_CTL_291_DATA 0x00000001
+#define DDRSS1_CTL_292_DATA 0x00000000
+#define DDRSS1_CTL_293_DATA 0x00000000
+#define DDRSS1_CTL_294_DATA 0x00000000
+#define DDRSS1_CTL_295_DATA 0x00000000
+#define DDRSS1_CTL_296_DATA 0x00000000
+#define DDRSS1_CTL_297_DATA 0x00000000
+#define DDRSS1_CTL_298_DATA 0x00000000
+#define DDRSS1_CTL_299_DATA 0x00000000
+#define DDRSS1_CTL_300_DATA 0x00000000
+#define DDRSS1_CTL_301_DATA 0x00000000
+#define DDRSS1_CTL_302_DATA 0x00000000
+#define DDRSS1_CTL_303_DATA 0x00000000
+#define DDRSS1_CTL_304_DATA 0x00000000
+#define DDRSS1_CTL_305_DATA 0x00000000
+#define DDRSS1_CTL_306_DATA 0x00000000
+#define DDRSS1_CTL_307_DATA 0x00000000
+#define DDRSS1_CTL_308_DATA 0x00000000
+#define DDRSS1_CTL_309_DATA 0x00000000
+#define DDRSS1_CTL_310_DATA 0x00000000
+#define DDRSS1_CTL_311_DATA 0x00000000
+#define DDRSS1_CTL_312_DATA 0x00000000
+#define DDRSS1_CTL_313_DATA 0x01000000
+#define DDRSS1_CTL_314_DATA 0x00020201
+#define DDRSS1_CTL_315_DATA 0x01000101
+#define DDRSS1_CTL_316_DATA 0x01010001
+#define DDRSS1_CTL_317_DATA 0x00010101
+#define DDRSS1_CTL_318_DATA 0x050A0A03
+#define DDRSS1_CTL_319_DATA 0x10081F1F
+#define DDRSS1_CTL_320_DATA 0x00090310
+#define DDRSS1_CTL_321_DATA 0x0B0C030F
+#define DDRSS1_CTL_322_DATA 0x0B0C0306
+#define DDRSS1_CTL_323_DATA 0x0C090006
+#define DDRSS1_CTL_324_DATA 0x0100000C
+#define DDRSS1_CTL_325_DATA 0x08040801
+#define DDRSS1_CTL_326_DATA 0x00000004
+#define DDRSS1_CTL_327_DATA 0x00000000
+#define DDRSS1_CTL_328_DATA 0x00010000
+#define DDRSS1_CTL_329_DATA 0x00280D00
+#define DDRSS1_CTL_330_DATA 0x00000001
+#define DDRSS1_CTL_331_DATA 0x00030001
+#define DDRSS1_CTL_332_DATA 0x00000000
+#define DDRSS1_CTL_333_DATA 0x00000000
+#define DDRSS1_CTL_334_DATA 0x00000000
+#define DDRSS1_CTL_335_DATA 0x00000000
+#define DDRSS1_CTL_336_DATA 0x00000000
+#define DDRSS1_CTL_337_DATA 0x00000000
+#define DDRSS1_CTL_338_DATA 0x00000000
+#define DDRSS1_CTL_339_DATA 0x00000000
+#define DDRSS1_CTL_340_DATA 0x01000000
+#define DDRSS1_CTL_341_DATA 0x00000001
+#define DDRSS1_CTL_342_DATA 0x00010100
+#define DDRSS1_CTL_343_DATA 0x03030000
+#define DDRSS1_CTL_344_DATA 0x00000000
+#define DDRSS1_CTL_345_DATA 0x00000000
+#define DDRSS1_CTL_346_DATA 0x00000000
+#define DDRSS1_CTL_347_DATA 0x00000000
+#define DDRSS1_CTL_348_DATA 0x00000000
+#define DDRSS1_CTL_349_DATA 0x00000000
+#define DDRSS1_CTL_350_DATA 0x00000000
+#define DDRSS1_CTL_351_DATA 0x00000000
+#define DDRSS1_CTL_352_DATA 0x00000000
+#define DDRSS1_CTL_353_DATA 0x00000000
+#define DDRSS1_CTL_354_DATA 0x00000000
+#define DDRSS1_CTL_355_DATA 0x00000000
+#define DDRSS1_CTL_356_DATA 0x00000000
+#define DDRSS1_CTL_357_DATA 0x00000000
+#define DDRSS1_CTL_358_DATA 0x00000000
+#define DDRSS1_CTL_359_DATA 0x00000000
+#define DDRSS1_CTL_360_DATA 0x000556AA
+#define DDRSS1_CTL_361_DATA 0x000AAAAA
+#define DDRSS1_CTL_362_DATA 0x000AA955
+#define DDRSS1_CTL_363_DATA 0x00055555
+#define DDRSS1_CTL_364_DATA 0x000B3133
+#define DDRSS1_CTL_365_DATA 0x0004CD33
+#define DDRSS1_CTL_366_DATA 0x0004CECC
+#define DDRSS1_CTL_367_DATA 0x000B32CC
+#define DDRSS1_CTL_368_DATA 0x00010300
+#define DDRSS1_CTL_369_DATA 0x03000100
+#define DDRSS1_CTL_370_DATA 0x00000000
+#define DDRSS1_CTL_371_DATA 0x00000000
+#define DDRSS1_CTL_372_DATA 0x00000000
+#define DDRSS1_CTL_373_DATA 0x00000000
+#define DDRSS1_CTL_374_DATA 0x00000000
+#define DDRSS1_CTL_375_DATA 0x00000000
+#define DDRSS1_CTL_376_DATA 0x00000000
+#define DDRSS1_CTL_377_DATA 0x00010000
+#define DDRSS1_CTL_378_DATA 0x00000404
+#define DDRSS1_CTL_379_DATA 0x00000000
+#define DDRSS1_CTL_380_DATA 0x00000000
+#define DDRSS1_CTL_381_DATA 0x00000000
+#define DDRSS1_CTL_382_DATA 0x00000000
+#define DDRSS1_CTL_383_DATA 0x00000000
+#define DDRSS1_CTL_384_DATA 0x00000000
+#define DDRSS1_CTL_385_DATA 0x00000000
+#define DDRSS1_CTL_386_DATA 0x00000000
+#define DDRSS1_CTL_387_DATA 0x3A3A1B00
+#define DDRSS1_CTL_388_DATA 0x000A0000
+#define DDRSS1_CTL_389_DATA 0x0000019C
+#define DDRSS1_CTL_390_DATA 0x00000200
+#define DDRSS1_CTL_391_DATA 0x00000200
+#define DDRSS1_CTL_392_DATA 0x00000200
+#define DDRSS1_CTL_393_DATA 0x00000200
+#define DDRSS1_CTL_394_DATA 0x000004D4
+#define DDRSS1_CTL_395_DATA 0x00001018
+#define DDRSS1_CTL_396_DATA 0x00000204
+#define DDRSS1_CTL_397_DATA 0x000040E6
+#define DDRSS1_CTL_398_DATA 0x00000200
+#define DDRSS1_CTL_399_DATA 0x00000200
+#define DDRSS1_CTL_400_DATA 0x00000200
+#define DDRSS1_CTL_401_DATA 0x00000200
+#define DDRSS1_CTL_402_DATA 0x0000C2B2
+#define DDRSS1_CTL_403_DATA 0x000288FC
+#define DDRSS1_CTL_404_DATA 0x00000E15
+#define DDRSS1_CTL_405_DATA 0x000040E6
+#define DDRSS1_CTL_406_DATA 0x00000200
+#define DDRSS1_CTL_407_DATA 0x00000200
+#define DDRSS1_CTL_408_DATA 0x00000200
+#define DDRSS1_CTL_409_DATA 0x00000200
+#define DDRSS1_CTL_410_DATA 0x0000C2B2
+#define DDRSS1_CTL_411_DATA 0x000288FC
+#define DDRSS1_CTL_412_DATA 0x02020E15
+#define DDRSS1_CTL_413_DATA 0x03030202
+#define DDRSS1_CTL_414_DATA 0x00000022
+#define DDRSS1_CTL_415_DATA 0x00000000
+#define DDRSS1_CTL_416_DATA 0x00000000
+#define DDRSS1_CTL_417_DATA 0x00001403
+#define DDRSS1_CTL_418_DATA 0x000007D0
+#define DDRSS1_CTL_419_DATA 0x00000000
+#define DDRSS1_CTL_420_DATA 0x00000000
+#define DDRSS1_CTL_421_DATA 0x00030000
+#define DDRSS1_CTL_422_DATA 0x0007001F
+#define DDRSS1_CTL_423_DATA 0x001B0033
+#define DDRSS1_CTL_424_DATA 0x001B0033
+#define DDRSS1_CTL_425_DATA 0x00000000
+#define DDRSS1_CTL_426_DATA 0x00000000
+#define DDRSS1_CTL_427_DATA 0x02000000
+#define DDRSS1_CTL_428_DATA 0x01000404
+#define DDRSS1_CTL_429_DATA 0x0B1E0B1E
+#define DDRSS1_CTL_430_DATA 0x00000105
+#define DDRSS1_CTL_431_DATA 0x00010101
+#define DDRSS1_CTL_432_DATA 0x00010101
+#define DDRSS1_CTL_433_DATA 0x00010001
+#define DDRSS1_CTL_434_DATA 0x00000101
+#define DDRSS1_CTL_435_DATA 0x02000201
+#define DDRSS1_CTL_436_DATA 0x02010000
+#define DDRSS1_CTL_437_DATA 0x00000200
+#define DDRSS1_CTL_438_DATA 0x28060000
+#define DDRSS1_CTL_439_DATA 0x00000128
+#define DDRSS1_CTL_440_DATA 0xFFFFFFFF
+#define DDRSS1_CTL_441_DATA 0xFFFFFFFF
+#define DDRSS1_CTL_442_DATA 0x00000000
+#define DDRSS1_CTL_443_DATA 0x00000000
+#define DDRSS1_CTL_444_DATA 0x00000000
+#define DDRSS1_CTL_445_DATA 0x00000000
+#define DDRSS1_CTL_446_DATA 0x00000000
+#define DDRSS1_CTL_447_DATA 0x00000000
+#define DDRSS1_CTL_448_DATA 0x00000000
+#define DDRSS1_CTL_449_DATA 0x00000000
+#define DDRSS1_CTL_450_DATA 0x00000000
+#define DDRSS1_CTL_451_DATA 0x00000000
+#define DDRSS1_CTL_452_DATA 0x00000000
+#define DDRSS1_CTL_453_DATA 0x00000000
+#define DDRSS1_CTL_454_DATA 0x00000000
+#define DDRSS1_CTL_455_DATA 0x00000000
+#define DDRSS1_CTL_456_DATA 0x00000000
+#define DDRSS1_CTL_457_DATA 0x00000000
+#define DDRSS1_CTL_458_DATA 0x00000000
+
+#define DDRSS1_PI_00_DATA 0x00000B00
+#define DDRSS1_PI_01_DATA 0x00000000
+#define DDRSS1_PI_02_DATA 0x00000000
+#define DDRSS1_PI_03_DATA 0x00000000
+#define DDRSS1_PI_04_DATA 0x00000000
+#define DDRSS1_PI_05_DATA 0x00000101
+#define DDRSS1_PI_06_DATA 0x00640000
+#define DDRSS1_PI_07_DATA 0x00000001
+#define DDRSS1_PI_08_DATA 0x00000000
+#define DDRSS1_PI_09_DATA 0x00000000
+#define DDRSS1_PI_10_DATA 0x00000000
+#define DDRSS1_PI_11_DATA 0x00000000
+#define DDRSS1_PI_12_DATA 0x00000007
+#define DDRSS1_PI_13_DATA 0x00010002
+#define DDRSS1_PI_14_DATA 0x0800000F
+#define DDRSS1_PI_15_DATA 0x00000103
+#define DDRSS1_PI_16_DATA 0x00000005
+#define DDRSS1_PI_17_DATA 0x00000000
+#define DDRSS1_PI_18_DATA 0x00000000
+#define DDRSS1_PI_19_DATA 0x00000000
+#define DDRSS1_PI_20_DATA 0x00000000
+#define DDRSS1_PI_21_DATA 0x00000000
+#define DDRSS1_PI_22_DATA 0x00000000
+#define DDRSS1_PI_23_DATA 0x00000000
+#define DDRSS1_PI_24_DATA 0x00000000
+#define DDRSS1_PI_25_DATA 0x00000000
+#define DDRSS1_PI_26_DATA 0x00010100
+#define DDRSS1_PI_27_DATA 0x00280A00
+#define DDRSS1_PI_28_DATA 0x00000000
+#define DDRSS1_PI_29_DATA 0x0F000000
+#define DDRSS1_PI_30_DATA 0x00003200
+#define DDRSS1_PI_31_DATA 0x00000000
+#define DDRSS1_PI_32_DATA 0x00000000
+#define DDRSS1_PI_33_DATA 0x01010102
+#define DDRSS1_PI_34_DATA 0x00000000
+#define DDRSS1_PI_35_DATA 0x000000AA
+#define DDRSS1_PI_36_DATA 0x00000055
+#define DDRSS1_PI_37_DATA 0x000000B5
+#define DDRSS1_PI_38_DATA 0x0000004A
+#define DDRSS1_PI_39_DATA 0x00000056
+#define DDRSS1_PI_40_DATA 0x000000A9
+#define DDRSS1_PI_41_DATA 0x000000A9
+#define DDRSS1_PI_42_DATA 0x000000B5
+#define DDRSS1_PI_43_DATA 0x00000000
+#define DDRSS1_PI_44_DATA 0x00000000
+#define DDRSS1_PI_45_DATA 0x000F0F00
+#define DDRSS1_PI_46_DATA 0x0000001B
+#define DDRSS1_PI_47_DATA 0x000007D0
+#define DDRSS1_PI_48_DATA 0x00000300
+#define DDRSS1_PI_49_DATA 0x00000000
+#define DDRSS1_PI_50_DATA 0x00000000
+#define DDRSS1_PI_51_DATA 0x01000000
+#define DDRSS1_PI_52_DATA 0x00010101
+#define DDRSS1_PI_53_DATA 0x00000000
+#define DDRSS1_PI_54_DATA 0x00030000
+#define DDRSS1_PI_55_DATA 0x0F000000
+#define DDRSS1_PI_56_DATA 0x00000017
+#define DDRSS1_PI_57_DATA 0x00000000
+#define DDRSS1_PI_58_DATA 0x00000000
+#define DDRSS1_PI_59_DATA 0x00000000
+#define DDRSS1_PI_60_DATA 0x0A0A140A
+#define DDRSS1_PI_61_DATA 0x10020101
+#define DDRSS1_PI_62_DATA 0x00020805
+#define DDRSS1_PI_63_DATA 0x01000404
+#define DDRSS1_PI_64_DATA 0x00000000
+#define DDRSS1_PI_65_DATA 0x00000000
+#define DDRSS1_PI_66_DATA 0x00000100
+#define DDRSS1_PI_67_DATA 0x0001010F
+#define DDRSS1_PI_68_DATA 0x00340000
+#define DDRSS1_PI_69_DATA 0x00000000
+#define DDRSS1_PI_70_DATA 0x00000000
+#define DDRSS1_PI_71_DATA 0x0000FFFF
+#define DDRSS1_PI_72_DATA 0x00000000
+#define DDRSS1_PI_73_DATA 0x00080000
+#define DDRSS1_PI_74_DATA 0x02000200
+#define DDRSS1_PI_75_DATA 0x01000100
+#define DDRSS1_PI_76_DATA 0x01000000
+#define DDRSS1_PI_77_DATA 0x02000200
+#define DDRSS1_PI_78_DATA 0x00000200
+#define DDRSS1_PI_79_DATA 0x00000000
+#define DDRSS1_PI_80_DATA 0x00000000
+#define DDRSS1_PI_81_DATA 0x00000000
+#define DDRSS1_PI_82_DATA 0x00000000
+#define DDRSS1_PI_83_DATA 0x00000000
+#define DDRSS1_PI_84_DATA 0x00000000
+#define DDRSS1_PI_85_DATA 0x00000000
+#define DDRSS1_PI_86_DATA 0x00000000
+#define DDRSS1_PI_87_DATA 0x00000000
+#define DDRSS1_PI_88_DATA 0x00000000
+#define DDRSS1_PI_89_DATA 0x00000000
+#define DDRSS1_PI_90_DATA 0x00000000
+#define DDRSS1_PI_91_DATA 0x00000400
+#define DDRSS1_PI_92_DATA 0x02010000
+#define DDRSS1_PI_93_DATA 0x00080003
+#define DDRSS1_PI_94_DATA 0x00080000
+#define DDRSS1_PI_95_DATA 0x00000001
+#define DDRSS1_PI_96_DATA 0x00000000
+#define DDRSS1_PI_97_DATA 0x0000AA00
+#define DDRSS1_PI_98_DATA 0x00000000
+#define DDRSS1_PI_99_DATA 0x00000000
+#define DDRSS1_PI_100_DATA 0x00010000
+#define DDRSS1_PI_101_DATA 0x00000000
+#define DDRSS1_PI_102_DATA 0x00000000
+#define DDRSS1_PI_103_DATA 0x00000000
+#define DDRSS1_PI_104_DATA 0x00000000
+#define DDRSS1_PI_105_DATA 0x00000000
+#define DDRSS1_PI_106_DATA 0x00000000
+#define DDRSS1_PI_107_DATA 0x00000000
+#define DDRSS1_PI_108_DATA 0x00000000
+#define DDRSS1_PI_109_DATA 0x00000000
+#define DDRSS1_PI_110_DATA 0x00000000
+#define DDRSS1_PI_111_DATA 0x00000000
+#define DDRSS1_PI_112_DATA 0x00000000
+#define DDRSS1_PI_113_DATA 0x00000000
+#define DDRSS1_PI_114_DATA 0x00000000
+#define DDRSS1_PI_115_DATA 0x00000000
+#define DDRSS1_PI_116_DATA 0x00000000
+#define DDRSS1_PI_117_DATA 0x00000000
+#define DDRSS1_PI_118_DATA 0x00000000
+#define DDRSS1_PI_119_DATA 0x00000000
+#define DDRSS1_PI_120_DATA 0x00000000
+#define DDRSS1_PI_121_DATA 0x00000000
+#define DDRSS1_PI_122_DATA 0x00000000
+#define DDRSS1_PI_123_DATA 0x00000000
+#define DDRSS1_PI_124_DATA 0x00000000
+#define DDRSS1_PI_125_DATA 0x00000008
+#define DDRSS1_PI_126_DATA 0x00000000
+#define DDRSS1_PI_127_DATA 0x00000000
+#define DDRSS1_PI_128_DATA 0x00000000
+#define DDRSS1_PI_129_DATA 0x00000000
+#define DDRSS1_PI_130_DATA 0x00000000
+#define DDRSS1_PI_131_DATA 0x00000000
+#define DDRSS1_PI_132_DATA 0x00000000
+#define DDRSS1_PI_133_DATA 0x00000000
+#define DDRSS1_PI_134_DATA 0x00000002
+#define DDRSS1_PI_135_DATA 0x00000000
+#define DDRSS1_PI_136_DATA 0x00000000
+#define DDRSS1_PI_137_DATA 0x0000000A
+#define DDRSS1_PI_138_DATA 0x00000019
+#define DDRSS1_PI_139_DATA 0x00000100
+#define DDRSS1_PI_140_DATA 0x00000000
+#define DDRSS1_PI_141_DATA 0x00000000
+#define DDRSS1_PI_142_DATA 0x00000000
+#define DDRSS1_PI_143_DATA 0x00000000
+#define DDRSS1_PI_144_DATA 0x01000000
+#define DDRSS1_PI_145_DATA 0x00010003
+#define DDRSS1_PI_146_DATA 0x02000101
+#define DDRSS1_PI_147_DATA 0x01030001
+#define DDRSS1_PI_148_DATA 0x00010400
+#define DDRSS1_PI_149_DATA 0x06000105
+#define DDRSS1_PI_150_DATA 0x01070001
+#define DDRSS1_PI_151_DATA 0x00000000
+#define DDRSS1_PI_152_DATA 0x00000000
+#define DDRSS1_PI_153_DATA 0x00000000
+#define DDRSS1_PI_154_DATA 0x00010001
+#define DDRSS1_PI_155_DATA 0x00000000
+#define DDRSS1_PI_156_DATA 0x00000000
+#define DDRSS1_PI_157_DATA 0x00000000
+#define DDRSS1_PI_158_DATA 0x00000000
+#define DDRSS1_PI_159_DATA 0x00000401
+#define DDRSS1_PI_160_DATA 0x00000000
+#define DDRSS1_PI_161_DATA 0x00010000
+#define DDRSS1_PI_162_DATA 0x00000000
+#define DDRSS1_PI_163_DATA 0x2B2B0200
+#define DDRSS1_PI_164_DATA 0x00000034
+#define DDRSS1_PI_165_DATA 0x00000064
+#define DDRSS1_PI_166_DATA 0x00020064
+#define DDRSS1_PI_167_DATA 0x02000200
+#define DDRSS1_PI_168_DATA 0x48120C04
+#define DDRSS1_PI_169_DATA 0x00154812
+#define DDRSS1_PI_170_DATA 0x000000CE
+#define DDRSS1_PI_171_DATA 0x0000032B
+#define DDRSS1_PI_172_DATA 0x00002073
+#define DDRSS1_PI_173_DATA 0x0000032B
+#define DDRSS1_PI_174_DATA 0x04002073
+#define DDRSS1_PI_175_DATA 0x01010404
+#define DDRSS1_PI_176_DATA 0x00001501
+#define DDRSS1_PI_177_DATA 0x00150015
+#define DDRSS1_PI_178_DATA 0x01000100
+#define DDRSS1_PI_179_DATA 0x00000100
+#define DDRSS1_PI_180_DATA 0x00000000
+#define DDRSS1_PI_181_DATA 0x01010101
+#define DDRSS1_PI_182_DATA 0x00000101
+#define DDRSS1_PI_183_DATA 0x00000000
+#define DDRSS1_PI_184_DATA 0x00000000
+#define DDRSS1_PI_185_DATA 0x15040000
+#define DDRSS1_PI_186_DATA 0x0E0E0215
+#define DDRSS1_PI_187_DATA 0x00040402
+#define DDRSS1_PI_188_DATA 0x000D0035
+#define DDRSS1_PI_189_DATA 0x00218049
+#define DDRSS1_PI_190_DATA 0x00218049
+#define DDRSS1_PI_191_DATA 0x01010101
+#define DDRSS1_PI_192_DATA 0x0004000E
+#define DDRSS1_PI_193_DATA 0x00040216
+#define DDRSS1_PI_194_DATA 0x01000216
+#define DDRSS1_PI_195_DATA 0x000F000F
+#define DDRSS1_PI_196_DATA 0x02170100
+#define DDRSS1_PI_197_DATA 0x01000217
+#define DDRSS1_PI_198_DATA 0x02170217
+#define DDRSS1_PI_199_DATA 0x32103200
+#define DDRSS1_PI_200_DATA 0x01013210
+#define DDRSS1_PI_201_DATA 0x0A070601
+#define DDRSS1_PI_202_DATA 0x1F130A0D
+#define DDRSS1_PI_203_DATA 0x1F130A14
+#define DDRSS1_PI_204_DATA 0x0000C014
+#define DDRSS1_PI_205_DATA 0x00C01000
+#define DDRSS1_PI_206_DATA 0x00C01000
+#define DDRSS1_PI_207_DATA 0x00021000
+#define DDRSS1_PI_208_DATA 0x0024000E
+#define DDRSS1_PI_209_DATA 0x00240216
+#define DDRSS1_PI_210_DATA 0x00110216
+#define DDRSS1_PI_211_DATA 0x32000056
+#define DDRSS1_PI_212_DATA 0x00000301
+#define DDRSS1_PI_213_DATA 0x005B0036
+#define DDRSS1_PI_214_DATA 0x03013212
+#define DDRSS1_PI_215_DATA 0x00003600
+#define DDRSS1_PI_216_DATA 0x3212005B
+#define DDRSS1_PI_217_DATA 0x09000301
+#define DDRSS1_PI_218_DATA 0x04010504
+#define DDRSS1_PI_219_DATA 0x040006C9
+#define DDRSS1_PI_220_DATA 0x0A032001
+#define DDRSS1_PI_221_DATA 0x2C31110A
+#define DDRSS1_PI_222_DATA 0x00002918
+#define DDRSS1_PI_223_DATA 0x6001071C
+#define DDRSS1_PI_224_DATA 0x1E202008
+#define DDRSS1_PI_225_DATA 0x2C311116
+#define DDRSS1_PI_226_DATA 0x00002918
+#define DDRSS1_PI_227_DATA 0x6001071C
+#define DDRSS1_PI_228_DATA 0x1E202008
+#define DDRSS1_PI_229_DATA 0x00019C16
+#define DDRSS1_PI_230_DATA 0x00001018
+#define DDRSS1_PI_231_DATA 0x000040E6
+#define DDRSS1_PI_232_DATA 0x000288FC
+#define DDRSS1_PI_233_DATA 0x000040E6
+#define DDRSS1_PI_234_DATA 0x000288FC
+#define DDRSS1_PI_235_DATA 0x033B0016
+#define DDRSS1_PI_236_DATA 0x0303033B
+#define DDRSS1_PI_237_DATA 0x002AF803
+#define DDRSS1_PI_238_DATA 0x0001ADAF
+#define DDRSS1_PI_239_DATA 0x00000005
+#define DDRSS1_PI_240_DATA 0x0000006E
+#define DDRSS1_PI_241_DATA 0x00000016
+#define DDRSS1_PI_242_DATA 0x000681C8
+#define DDRSS1_PI_243_DATA 0x0001ADAF
+#define DDRSS1_PI_244_DATA 0x00000005
+#define DDRSS1_PI_245_DATA 0x000010A9
+#define DDRSS1_PI_246_DATA 0x0000033B
+#define DDRSS1_PI_247_DATA 0x000681C8
+#define DDRSS1_PI_248_DATA 0x0001ADAF
+#define DDRSS1_PI_249_DATA 0x00000005
+#define DDRSS1_PI_250_DATA 0x000010A9
+#define DDRSS1_PI_251_DATA 0x0100033B
+#define DDRSS1_PI_252_DATA 0x00370040
+#define DDRSS1_PI_253_DATA 0x00010008
+#define DDRSS1_PI_254_DATA 0x08550040
+#define DDRSS1_PI_255_DATA 0x00010040
+#define DDRSS1_PI_256_DATA 0x08550040
+#define DDRSS1_PI_257_DATA 0x00000340
+#define DDRSS1_PI_258_DATA 0x006B006B
+#define DDRSS1_PI_259_DATA 0x08040404
+#define DDRSS1_PI_260_DATA 0x00000055
+#define DDRSS1_PI_261_DATA 0x55083C5A
+#define DDRSS1_PI_262_DATA 0x5A000000
+#define DDRSS1_PI_263_DATA 0x0055083C
+#define DDRSS1_PI_264_DATA 0x3C5A0000
+#define DDRSS1_PI_265_DATA 0x00005508
+#define DDRSS1_PI_266_DATA 0x0C3C5A00
+#define DDRSS1_PI_267_DATA 0x080F0E0D
+#define DDRSS1_PI_268_DATA 0x000B0A09
+#define DDRSS1_PI_269_DATA 0x00030201
+#define DDRSS1_PI_270_DATA 0x01000000
+#define DDRSS1_PI_271_DATA 0x04020201
+#define DDRSS1_PI_272_DATA 0x00080804
+#define DDRSS1_PI_273_DATA 0x00000000
+#define DDRSS1_PI_274_DATA 0x00000000
+#define DDRSS1_PI_275_DATA 0x00330084
+#define DDRSS1_PI_276_DATA 0x00160000
+#define DDRSS1_PI_277_DATA 0x35333FF4
+#define DDRSS1_PI_278_DATA 0x00160F27
+#define DDRSS1_PI_279_DATA 0x35333FF4
+#define DDRSS1_PI_280_DATA 0x00160F27
+#define DDRSS1_PI_281_DATA 0x00330084
+#define DDRSS1_PI_282_DATA 0x00160000
+#define DDRSS1_PI_283_DATA 0x35333FF4
+#define DDRSS1_PI_284_DATA 0x00160F27
+#define DDRSS1_PI_285_DATA 0x35333FF4
+#define DDRSS1_PI_286_DATA 0x00160F27
+#define DDRSS1_PI_287_DATA 0x00330084
+#define DDRSS1_PI_288_DATA 0x00160000
+#define DDRSS1_PI_289_DATA 0x35333FF4
+#define DDRSS1_PI_290_DATA 0x00160F27
+#define DDRSS1_PI_291_DATA 0x35333FF4
+#define DDRSS1_PI_292_DATA 0x00160F27
+#define DDRSS1_PI_293_DATA 0x00330084
+#define DDRSS1_PI_294_DATA 0x00160000
+#define DDRSS1_PI_295_DATA 0x35333FF4
+#define DDRSS1_PI_296_DATA 0x00160F27
+#define DDRSS1_PI_297_DATA 0x35333FF4
+#define DDRSS1_PI_298_DATA 0x00160F27
+#define DDRSS1_PI_299_DATA 0x00000000
+
+#define DDRSS1_PHY_00_DATA 0x000004F0
+#define DDRSS1_PHY_01_DATA 0x00000000
+#define DDRSS1_PHY_02_DATA 0x00030200
+#define DDRSS1_PHY_03_DATA 0x00000000
+#define DDRSS1_PHY_04_DATA 0x00000000
+#define DDRSS1_PHY_05_DATA 0x01030000
+#define DDRSS1_PHY_06_DATA 0x00010000
+#define DDRSS1_PHY_07_DATA 0x01030004
+#define DDRSS1_PHY_08_DATA 0x01000000
+#define DDRSS1_PHY_09_DATA 0x00000000
+#define DDRSS1_PHY_10_DATA 0x00000000
+#define DDRSS1_PHY_11_DATA 0x01000001
+#define DDRSS1_PHY_12_DATA 0x00000100
+#define DDRSS1_PHY_13_DATA 0x000800C0
+#define DDRSS1_PHY_14_DATA 0x060100CC
+#define DDRSS1_PHY_15_DATA 0x00030066
+#define DDRSS1_PHY_16_DATA 0x00000000
+#define DDRSS1_PHY_17_DATA 0x00000301
+#define DDRSS1_PHY_18_DATA 0x0000AAAA
+#define DDRSS1_PHY_19_DATA 0x00005555
+#define DDRSS1_PHY_20_DATA 0x0000B5B5
+#define DDRSS1_PHY_21_DATA 0x00004A4A
+#define DDRSS1_PHY_22_DATA 0x00005656
+#define DDRSS1_PHY_23_DATA 0x0000A9A9
+#define DDRSS1_PHY_24_DATA 0x0000A9A9
+#define DDRSS1_PHY_25_DATA 0x0000B5B5
+#define DDRSS1_PHY_26_DATA 0x00000000
+#define DDRSS1_PHY_27_DATA 0x00000000
+#define DDRSS1_PHY_28_DATA 0x2A000000
+#define DDRSS1_PHY_29_DATA 0x00000808
+#define DDRSS1_PHY_30_DATA 0x0F000000
+#define DDRSS1_PHY_31_DATA 0x00000F0F
+#define DDRSS1_PHY_32_DATA 0x10400000
+#define DDRSS1_PHY_33_DATA 0x0C002006
+#define DDRSS1_PHY_34_DATA 0x00000000
+#define DDRSS1_PHY_35_DATA 0x00000000
+#define DDRSS1_PHY_36_DATA 0x55555555
+#define DDRSS1_PHY_37_DATA 0xAAAAAAAA
+#define DDRSS1_PHY_38_DATA 0x55555555
+#define DDRSS1_PHY_39_DATA 0xAAAAAAAA
+#define DDRSS1_PHY_40_DATA 0x00005555
+#define DDRSS1_PHY_41_DATA 0x01000100
+#define DDRSS1_PHY_42_DATA 0x00800180
+#define DDRSS1_PHY_43_DATA 0x00000001
+#define DDRSS1_PHY_44_DATA 0x00000000
+#define DDRSS1_PHY_45_DATA 0x00000000
+#define DDRSS1_PHY_46_DATA 0x00000000
+#define DDRSS1_PHY_47_DATA 0x00000000
+#define DDRSS1_PHY_48_DATA 0x00000000
+#define DDRSS1_PHY_49_DATA 0x00000000
+#define DDRSS1_PHY_50_DATA 0x00000000
+#define DDRSS1_PHY_51_DATA 0x00000000
+#define DDRSS1_PHY_52_DATA 0x00000000
+#define DDRSS1_PHY_53_DATA 0x00000000
+#define DDRSS1_PHY_54_DATA 0x00000000
+#define DDRSS1_PHY_55_DATA 0x00000000
+#define DDRSS1_PHY_56_DATA 0x00000000
+#define DDRSS1_PHY_57_DATA 0x00000000
+#define DDRSS1_PHY_58_DATA 0x00000000
+#define DDRSS1_PHY_59_DATA 0x00000000
+#define DDRSS1_PHY_60_DATA 0x00000000
+#define DDRSS1_PHY_61_DATA 0x00000000
+#define DDRSS1_PHY_62_DATA 0x00000000
+#define DDRSS1_PHY_63_DATA 0x00000000
+#define DDRSS1_PHY_64_DATA 0x00000000
+#define DDRSS1_PHY_65_DATA 0x00000000
+#define DDRSS1_PHY_66_DATA 0x00000104
+#define DDRSS1_PHY_67_DATA 0x00000120
+#define DDRSS1_PHY_68_DATA 0x00000000
+#define DDRSS1_PHY_69_DATA 0x00000000
+#define DDRSS1_PHY_70_DATA 0x00000000
+#define DDRSS1_PHY_71_DATA 0x00000000
+#define DDRSS1_PHY_72_DATA 0x00000000
+#define DDRSS1_PHY_73_DATA 0x00000000
+#define DDRSS1_PHY_74_DATA 0x00000000
+#define DDRSS1_PHY_75_DATA 0x00000001
+#define DDRSS1_PHY_76_DATA 0x07FF0000
+#define DDRSS1_PHY_77_DATA 0x0080081F
+#define DDRSS1_PHY_78_DATA 0x00081020
+#define DDRSS1_PHY_79_DATA 0x04010000
+#define DDRSS1_PHY_80_DATA 0x00000000
+#define DDRSS1_PHY_81_DATA 0x00000000
+#define DDRSS1_PHY_82_DATA 0x00000000
+#define DDRSS1_PHY_83_DATA 0x00000100
+#define DDRSS1_PHY_84_DATA 0x01CC0C01
+#define DDRSS1_PHY_85_DATA 0x1003CC0C
+#define DDRSS1_PHY_86_DATA 0x20000140
+#define DDRSS1_PHY_87_DATA 0x07FF0200
+#define DDRSS1_PHY_88_DATA 0x0000DD01
+#define DDRSS1_PHY_89_DATA 0x10100303
+#define DDRSS1_PHY_90_DATA 0x10101010
+#define DDRSS1_PHY_91_DATA 0x10101010
+#define DDRSS1_PHY_92_DATA 0x00021010
+#define DDRSS1_PHY_93_DATA 0x00100010
+#define DDRSS1_PHY_94_DATA 0x00100010
+#define DDRSS1_PHY_95_DATA 0x00100010
+#define DDRSS1_PHY_96_DATA 0x00100010
+#define DDRSS1_PHY_97_DATA 0x00050010
+#define DDRSS1_PHY_98_DATA 0x51517041
+#define DDRSS1_PHY_99_DATA 0x31C06001
+#define DDRSS1_PHY_100_DATA 0x07AB0340
+#define DDRSS1_PHY_101_DATA 0x00C0C001
+#define DDRSS1_PHY_102_DATA 0x0E0D0001
+#define DDRSS1_PHY_103_DATA 0x10001000
+#define DDRSS1_PHY_104_DATA 0x0C083E42
+#define DDRSS1_PHY_105_DATA 0x0F0C3701
+#define DDRSS1_PHY_106_DATA 0x01000140
+#define DDRSS1_PHY_107_DATA 0x0C000420
+#define DDRSS1_PHY_108_DATA 0x00000198
+#define DDRSS1_PHY_109_DATA 0x0A0000D0
+#define DDRSS1_PHY_110_DATA 0x00030200
+#define DDRSS1_PHY_111_DATA 0x02800000
+#define DDRSS1_PHY_112_DATA 0x80800000
+#define DDRSS1_PHY_113_DATA 0x000E2010
+#define DDRSS1_PHY_114_DATA 0x76543210
+#define DDRSS1_PHY_115_DATA 0x00000008
+#define DDRSS1_PHY_116_DATA 0x02800280
+#define DDRSS1_PHY_117_DATA 0x02800280
+#define DDRSS1_PHY_118_DATA 0x02800280
+#define DDRSS1_PHY_119_DATA 0x02800280
+#define DDRSS1_PHY_120_DATA 0x00000280
+#define DDRSS1_PHY_121_DATA 0x0000A000
+#define DDRSS1_PHY_122_DATA 0x00A000A0
+#define DDRSS1_PHY_123_DATA 0x00A000A0
+#define DDRSS1_PHY_124_DATA 0x00A000A0
+#define DDRSS1_PHY_125_DATA 0x00A000A0
+#define DDRSS1_PHY_126_DATA 0x00A000A0
+#define DDRSS1_PHY_127_DATA 0x00A000A0
+#define DDRSS1_PHY_128_DATA 0x00A000A0
+#define DDRSS1_PHY_129_DATA 0x00A000A0
+#define DDRSS1_PHY_130_DATA 0x01C200A0
+#define DDRSS1_PHY_131_DATA 0x01A00005
+#define DDRSS1_PHY_132_DATA 0x00000000
+#define DDRSS1_PHY_133_DATA 0x00000000
+#define DDRSS1_PHY_134_DATA 0x00080200
+#define DDRSS1_PHY_135_DATA 0x00000000
+#define DDRSS1_PHY_136_DATA 0x20202000
+#define DDRSS1_PHY_137_DATA 0x20202020
+#define DDRSS1_PHY_138_DATA 0xF0F02020
+#define DDRSS1_PHY_139_DATA 0x00000000
+#define DDRSS1_PHY_140_DATA 0x00000000
+#define DDRSS1_PHY_141_DATA 0x00000000
+#define DDRSS1_PHY_142_DATA 0x00000000
+#define DDRSS1_PHY_143_DATA 0x00000000
+#define DDRSS1_PHY_144_DATA 0x00000000
+#define DDRSS1_PHY_145_DATA 0x00000000
+#define DDRSS1_PHY_146_DATA 0x00000000
+#define DDRSS1_PHY_147_DATA 0x00000000
+#define DDRSS1_PHY_148_DATA 0x00000000
+#define DDRSS1_PHY_149_DATA 0x00000000
+#define DDRSS1_PHY_150_DATA 0x00000000
+#define DDRSS1_PHY_151_DATA 0x00000000
+#define DDRSS1_PHY_152_DATA 0x00000000
+#define DDRSS1_PHY_153_DATA 0x00000000
+#define DDRSS1_PHY_154_DATA 0x00000000
+#define DDRSS1_PHY_155_DATA 0x00000000
+#define DDRSS1_PHY_156_DATA 0x00000000
+#define DDRSS1_PHY_157_DATA 0x00000000
+#define DDRSS1_PHY_158_DATA 0x00000000
+#define DDRSS1_PHY_159_DATA 0x00000000
+#define DDRSS1_PHY_160_DATA 0x00000000
+#define DDRSS1_PHY_161_DATA 0x00000000
+#define DDRSS1_PHY_162_DATA 0x00000000
+#define DDRSS1_PHY_163_DATA 0x00000000
+#define DDRSS1_PHY_164_DATA 0x00000000
+#define DDRSS1_PHY_165_DATA 0x00000000
+#define DDRSS1_PHY_166_DATA 0x00000000
+#define DDRSS1_PHY_167_DATA 0x00000000
+#define DDRSS1_PHY_168_DATA 0x00000000
+#define DDRSS1_PHY_169_DATA 0x00000000
+#define DDRSS1_PHY_170_DATA 0x00000000
+#define DDRSS1_PHY_171_DATA 0x00000000
+#define DDRSS1_PHY_172_DATA 0x00000000
+#define DDRSS1_PHY_173_DATA 0x00000000
+#define DDRSS1_PHY_174_DATA 0x00000000
+#define DDRSS1_PHY_175_DATA 0x00000000
+#define DDRSS1_PHY_176_DATA 0x00000000
+#define DDRSS1_PHY_177_DATA 0x00000000
+#define DDRSS1_PHY_178_DATA 0x00000000
+#define DDRSS1_PHY_179_DATA 0x00000000
+#define DDRSS1_PHY_180_DATA 0x00000000
+#define DDRSS1_PHY_181_DATA 0x00000000
+#define DDRSS1_PHY_182_DATA 0x00000000
+#define DDRSS1_PHY_183_DATA 0x00000000
+#define DDRSS1_PHY_184_DATA 0x00000000
+#define DDRSS1_PHY_185_DATA 0x00000000
+#define DDRSS1_PHY_186_DATA 0x00000000
+#define DDRSS1_PHY_187_DATA 0x00000000
+#define DDRSS1_PHY_188_DATA 0x00000000
+#define DDRSS1_PHY_189_DATA 0x00000000
+#define DDRSS1_PHY_190_DATA 0x00000000
+#define DDRSS1_PHY_191_DATA 0x00000000
+#define DDRSS1_PHY_192_DATA 0x00000000
+#define DDRSS1_PHY_193_DATA 0x00000000
+#define DDRSS1_PHY_194_DATA 0x00000000
+#define DDRSS1_PHY_195_DATA 0x00000000
+#define DDRSS1_PHY_196_DATA 0x00000000
+#define DDRSS1_PHY_197_DATA 0x00000000
+#define DDRSS1_PHY_198_DATA 0x00000000
+#define DDRSS1_PHY_199_DATA 0x00000000
+#define DDRSS1_PHY_200_DATA 0x00000000
+#define DDRSS1_PHY_201_DATA 0x00000000
+#define DDRSS1_PHY_202_DATA 0x00000000
+#define DDRSS1_PHY_203_DATA 0x00000000
+#define DDRSS1_PHY_204_DATA 0x00000000
+#define DDRSS1_PHY_205_DATA 0x00000000
+#define DDRSS1_PHY_206_DATA 0x00000000
+#define DDRSS1_PHY_207_DATA 0x00000000
+#define DDRSS1_PHY_208_DATA 0x00000000
+#define DDRSS1_PHY_209_DATA 0x00000000
+#define DDRSS1_PHY_210_DATA 0x00000000
+#define DDRSS1_PHY_211_DATA 0x00000000
+#define DDRSS1_PHY_212_DATA 0x00000000
+#define DDRSS1_PHY_213_DATA 0x00000000
+#define DDRSS1_PHY_214_DATA 0x00000000
+#define DDRSS1_PHY_215_DATA 0x00000000
+#define DDRSS1_PHY_216_DATA 0x00000000
+#define DDRSS1_PHY_217_DATA 0x00000000
+#define DDRSS1_PHY_218_DATA 0x00000000
+#define DDRSS1_PHY_219_DATA 0x00000000
+#define DDRSS1_PHY_220_DATA 0x00000000
+#define DDRSS1_PHY_221_DATA 0x00000000
+#define DDRSS1_PHY_222_DATA 0x00000000
+#define DDRSS1_PHY_223_DATA 0x00000000
+#define DDRSS1_PHY_224_DATA 0x00000000
+#define DDRSS1_PHY_225_DATA 0x00000000
+#define DDRSS1_PHY_226_DATA 0x00000000
+#define DDRSS1_PHY_227_DATA 0x00000000
+#define DDRSS1_PHY_228_DATA 0x00000000
+#define DDRSS1_PHY_229_DATA 0x00000000
+#define DDRSS1_PHY_230_DATA 0x00000000
+#define DDRSS1_PHY_231_DATA 0x00000000
+#define DDRSS1_PHY_232_DATA 0x00000000
+#define DDRSS1_PHY_233_DATA 0x00000000
+#define DDRSS1_PHY_234_DATA 0x00000000
+#define DDRSS1_PHY_235_DATA 0x00000000
+#define DDRSS1_PHY_236_DATA 0x00000000
+#define DDRSS1_PHY_237_DATA 0x00000000
+#define DDRSS1_PHY_238_DATA 0x00000000
+#define DDRSS1_PHY_239_DATA 0x00000000
+#define DDRSS1_PHY_240_DATA 0x00000000
+#define DDRSS1_PHY_241_DATA 0x00000000
+#define DDRSS1_PHY_242_DATA 0x00000000
+#define DDRSS1_PHY_243_DATA 0x00000000
+#define DDRSS1_PHY_244_DATA 0x00000000
+#define DDRSS1_PHY_245_DATA 0x00000000
+#define DDRSS1_PHY_246_DATA 0x00000000
+#define DDRSS1_PHY_247_DATA 0x00000000
+#define DDRSS1_PHY_248_DATA 0x00000000
+#define DDRSS1_PHY_249_DATA 0x00000000
+#define DDRSS1_PHY_250_DATA 0x00000000
+#define DDRSS1_PHY_251_DATA 0x00000000
+#define DDRSS1_PHY_252_DATA 0x00000000
+#define DDRSS1_PHY_253_DATA 0x00000000
+#define DDRSS1_PHY_254_DATA 0x00000000
+#define DDRSS1_PHY_255_DATA 0x00000000
+#define DDRSS1_PHY_256_DATA 0x000004F0
+#define DDRSS1_PHY_257_DATA 0x00000000
+#define DDRSS1_PHY_258_DATA 0x00030200
+#define DDRSS1_PHY_259_DATA 0x00000000
+#define DDRSS1_PHY_260_DATA 0x00000000
+#define DDRSS1_PHY_261_DATA 0x01030000
+#define DDRSS1_PHY_262_DATA 0x00010000
+#define DDRSS1_PHY_263_DATA 0x01030004
+#define DDRSS1_PHY_264_DATA 0x01000000
+#define DDRSS1_PHY_265_DATA 0x00000000
+#define DDRSS1_PHY_266_DATA 0x00000000
+#define DDRSS1_PHY_267_DATA 0x01000001
+#define DDRSS1_PHY_268_DATA 0x00000100
+#define DDRSS1_PHY_269_DATA 0x000800C0
+#define DDRSS1_PHY_270_DATA 0x060100CC
+#define DDRSS1_PHY_271_DATA 0x00030066
+#define DDRSS1_PHY_272_DATA 0x00000000
+#define DDRSS1_PHY_273_DATA 0x00000301
+#define DDRSS1_PHY_274_DATA 0x0000AAAA
+#define DDRSS1_PHY_275_DATA 0x00005555
+#define DDRSS1_PHY_276_DATA 0x0000B5B5
+#define DDRSS1_PHY_277_DATA 0x00004A4A
+#define DDRSS1_PHY_278_DATA 0x00005656
+#define DDRSS1_PHY_279_DATA 0x0000A9A9
+#define DDRSS1_PHY_280_DATA 0x0000A9A9
+#define DDRSS1_PHY_281_DATA 0x0000B5B5
+#define DDRSS1_PHY_282_DATA 0x00000000
+#define DDRSS1_PHY_283_DATA 0x00000000
+#define DDRSS1_PHY_284_DATA 0x2A000000
+#define DDRSS1_PHY_285_DATA 0x00000808
+#define DDRSS1_PHY_286_DATA 0x0F000000
+#define DDRSS1_PHY_287_DATA 0x00000F0F
+#define DDRSS1_PHY_288_DATA 0x10400000
+#define DDRSS1_PHY_289_DATA 0x0C002006
+#define DDRSS1_PHY_290_DATA 0x00000000
+#define DDRSS1_PHY_291_DATA 0x00000000
+#define DDRSS1_PHY_292_DATA 0x55555555
+#define DDRSS1_PHY_293_DATA 0xAAAAAAAA
+#define DDRSS1_PHY_294_DATA 0x55555555
+#define DDRSS1_PHY_295_DATA 0xAAAAAAAA
+#define DDRSS1_PHY_296_DATA 0x00005555
+#define DDRSS1_PHY_297_DATA 0x01000100
+#define DDRSS1_PHY_298_DATA 0x00800180
+#define DDRSS1_PHY_299_DATA 0x00000000
+#define DDRSS1_PHY_300_DATA 0x00000000
+#define DDRSS1_PHY_301_DATA 0x00000000
+#define DDRSS1_PHY_302_DATA 0x00000000
+#define DDRSS1_PHY_303_DATA 0x00000000
+#define DDRSS1_PHY_304_DATA 0x00000000
+#define DDRSS1_PHY_305_DATA 0x00000000
+#define DDRSS1_PHY_306_DATA 0x00000000
+#define DDRSS1_PHY_307_DATA 0x00000000
+#define DDRSS1_PHY_308_DATA 0x00000000
+#define DDRSS1_PHY_309_DATA 0x00000000
+#define DDRSS1_PHY_310_DATA 0x00000000
+#define DDRSS1_PHY_311_DATA 0x00000000
+#define DDRSS1_PHY_312_DATA 0x00000000
+#define DDRSS1_PHY_313_DATA 0x00000000
+#define DDRSS1_PHY_314_DATA 0x00000000
+#define DDRSS1_PHY_315_DATA 0x00000000
+#define DDRSS1_PHY_316_DATA 0x00000000
+#define DDRSS1_PHY_317_DATA 0x00000000
+#define DDRSS1_PHY_318_DATA 0x00000000
+#define DDRSS1_PHY_319_DATA 0x00000000
+#define DDRSS1_PHY_320_DATA 0x00000000
+#define DDRSS1_PHY_321_DATA 0x00000000
+#define DDRSS1_PHY_322_DATA 0x00000104
+#define DDRSS1_PHY_323_DATA 0x00000120
+#define DDRSS1_PHY_324_DATA 0x00000000
+#define DDRSS1_PHY_325_DATA 0x00000000
+#define DDRSS1_PHY_326_DATA 0x00000000
+#define DDRSS1_PHY_327_DATA 0x00000000
+#define DDRSS1_PHY_328_DATA 0x00000000
+#define DDRSS1_PHY_329_DATA 0x00000000
+#define DDRSS1_PHY_330_DATA 0x00000000
+#define DDRSS1_PHY_331_DATA 0x00000001
+#define DDRSS1_PHY_332_DATA 0x07FF0000
+#define DDRSS1_PHY_333_DATA 0x0080081F
+#define DDRSS1_PHY_334_DATA 0x00081020
+#define DDRSS1_PHY_335_DATA 0x04010000
+#define DDRSS1_PHY_336_DATA 0x00000000
+#define DDRSS1_PHY_337_DATA 0x00000000
+#define DDRSS1_PHY_338_DATA 0x00000000
+#define DDRSS1_PHY_339_DATA 0x00000100
+#define DDRSS1_PHY_340_DATA 0x01CC0C01
+#define DDRSS1_PHY_341_DATA 0x1003CC0C
+#define DDRSS1_PHY_342_DATA 0x20000140
+#define DDRSS1_PHY_343_DATA 0x07FF0200
+#define DDRSS1_PHY_344_DATA 0x0000DD01
+#define DDRSS1_PHY_345_DATA 0x10100303
+#define DDRSS1_PHY_346_DATA 0x10101010
+#define DDRSS1_PHY_347_DATA 0x10101010
+#define DDRSS1_PHY_348_DATA 0x00021010
+#define DDRSS1_PHY_349_DATA 0x00100010
+#define DDRSS1_PHY_350_DATA 0x00100010
+#define DDRSS1_PHY_351_DATA 0x00100010
+#define DDRSS1_PHY_352_DATA 0x00100010
+#define DDRSS1_PHY_353_DATA 0x00050010
+#define DDRSS1_PHY_354_DATA 0x51517041
+#define DDRSS1_PHY_355_DATA 0x31C06001
+#define DDRSS1_PHY_356_DATA 0x07AB0340
+#define DDRSS1_PHY_357_DATA 0x00C0C001
+#define DDRSS1_PHY_358_DATA 0x0E0D0001
+#define DDRSS1_PHY_359_DATA 0x10001000
+#define DDRSS1_PHY_360_DATA 0x0C083E42
+#define DDRSS1_PHY_361_DATA 0x0F0C3701
+#define DDRSS1_PHY_362_DATA 0x01000140
+#define DDRSS1_PHY_363_DATA 0x0C000420
+#define DDRSS1_PHY_364_DATA 0x00000198
+#define DDRSS1_PHY_365_DATA 0x0A0000D0
+#define DDRSS1_PHY_366_DATA 0x00030200
+#define DDRSS1_PHY_367_DATA 0x02800000
+#define DDRSS1_PHY_368_DATA 0x80800000
+#define DDRSS1_PHY_369_DATA 0x000E2010
+#define DDRSS1_PHY_370_DATA 0x76543210
+#define DDRSS1_PHY_371_DATA 0x00000008
+#define DDRSS1_PHY_372_DATA 0x02800280
+#define DDRSS1_PHY_373_DATA 0x02800280
+#define DDRSS1_PHY_374_DATA 0x02800280
+#define DDRSS1_PHY_375_DATA 0x02800280
+#define DDRSS1_PHY_376_DATA 0x00000280
+#define DDRSS1_PHY_377_DATA 0x0000A000
+#define DDRSS1_PHY_378_DATA 0x00A000A0
+#define DDRSS1_PHY_379_DATA 0x00A000A0
+#define DDRSS1_PHY_380_DATA 0x00A000A0
+#define DDRSS1_PHY_381_DATA 0x00A000A0
+#define DDRSS1_PHY_382_DATA 0x00A000A0
+#define DDRSS1_PHY_383_DATA 0x00A000A0
+#define DDRSS1_PHY_384_DATA 0x00A000A0
+#define DDRSS1_PHY_385_DATA 0x00A000A0
+#define DDRSS1_PHY_386_DATA 0x01C200A0
+#define DDRSS1_PHY_387_DATA 0x01A00005
+#define DDRSS1_PHY_388_DATA 0x00000000
+#define DDRSS1_PHY_389_DATA 0x00000000
+#define DDRSS1_PHY_390_DATA 0x00080200
+#define DDRSS1_PHY_391_DATA 0x00000000
+#define DDRSS1_PHY_392_DATA 0x20202000
+#define DDRSS1_PHY_393_DATA 0x20202020
+#define DDRSS1_PHY_394_DATA 0xF0F02020
+#define DDRSS1_PHY_395_DATA 0x00000000
+#define DDRSS1_PHY_396_DATA 0x00000000
+#define DDRSS1_PHY_397_DATA 0x00000000
+#define DDRSS1_PHY_398_DATA 0x00000000
+#define DDRSS1_PHY_399_DATA 0x00000000
+#define DDRSS1_PHY_400_DATA 0x00000000
+#define DDRSS1_PHY_401_DATA 0x00000000
+#define DDRSS1_PHY_402_DATA 0x00000000
+#define DDRSS1_PHY_403_DATA 0x00000000
+#define DDRSS1_PHY_404_DATA 0x00000000
+#define DDRSS1_PHY_405_DATA 0x00000000
+#define DDRSS1_PHY_406_DATA 0x00000000
+#define DDRSS1_PHY_407_DATA 0x00000000
+#define DDRSS1_PHY_408_DATA 0x00000000
+#define DDRSS1_PHY_409_DATA 0x00000000
+#define DDRSS1_PHY_410_DATA 0x00000000
+#define DDRSS1_PHY_411_DATA 0x00000000
+#define DDRSS1_PHY_412_DATA 0x00000000
+#define DDRSS1_PHY_413_DATA 0x00000000
+#define DDRSS1_PHY_414_DATA 0x00000000
+#define DDRSS1_PHY_415_DATA 0x00000000
+#define DDRSS1_PHY_416_DATA 0x00000000
+#define DDRSS1_PHY_417_DATA 0x00000000
+#define DDRSS1_PHY_418_DATA 0x00000000
+#define DDRSS1_PHY_419_DATA 0x00000000
+#define DDRSS1_PHY_420_DATA 0x00000000
+#define DDRSS1_PHY_421_DATA 0x00000000
+#define DDRSS1_PHY_422_DATA 0x00000000
+#define DDRSS1_PHY_423_DATA 0x00000000
+#define DDRSS1_PHY_424_DATA 0x00000000
+#define DDRSS1_PHY_425_DATA 0x00000000
+#define DDRSS1_PHY_426_DATA 0x00000000
+#define DDRSS1_PHY_427_DATA 0x00000000
+#define DDRSS1_PHY_428_DATA 0x00000000
+#define DDRSS1_PHY_429_DATA 0x00000000
+#define DDRSS1_PHY_430_DATA 0x00000000
+#define DDRSS1_PHY_431_DATA 0x00000000
+#define DDRSS1_PHY_432_DATA 0x00000000
+#define DDRSS1_PHY_433_DATA 0x00000000
+#define DDRSS1_PHY_434_DATA 0x00000000
+#define DDRSS1_PHY_435_DATA 0x00000000
+#define DDRSS1_PHY_436_DATA 0x00000000
+#define DDRSS1_PHY_437_DATA 0x00000000
+#define DDRSS1_PHY_438_DATA 0x00000000
+#define DDRSS1_PHY_439_DATA 0x00000000
+#define DDRSS1_PHY_440_DATA 0x00000000
+#define DDRSS1_PHY_441_DATA 0x00000000
+#define DDRSS1_PHY_442_DATA 0x00000000
+#define DDRSS1_PHY_443_DATA 0x00000000
+#define DDRSS1_PHY_444_DATA 0x00000000
+#define DDRSS1_PHY_445_DATA 0x00000000
+#define DDRSS1_PHY_446_DATA 0x00000000
+#define DDRSS1_PHY_447_DATA 0x00000000
+#define DDRSS1_PHY_448_DATA 0x00000000
+#define DDRSS1_PHY_449_DATA 0x00000000
+#define DDRSS1_PHY_450_DATA 0x00000000
+#define DDRSS1_PHY_451_DATA 0x00000000
+#define DDRSS1_PHY_452_DATA 0x00000000
+#define DDRSS1_PHY_453_DATA 0x00000000
+#define DDRSS1_PHY_454_DATA 0x00000000
+#define DDRSS1_PHY_455_DATA 0x00000000
+#define DDRSS1_PHY_456_DATA 0x00000000
+#define DDRSS1_PHY_457_DATA 0x00000000
+#define DDRSS1_PHY_458_DATA 0x00000000
+#define DDRSS1_PHY_459_DATA 0x00000000
+#define DDRSS1_PHY_460_DATA 0x00000000
+#define DDRSS1_PHY_461_DATA 0x00000000
+#define DDRSS1_PHY_462_DATA 0x00000000
+#define DDRSS1_PHY_463_DATA 0x00000000
+#define DDRSS1_PHY_464_DATA 0x00000000
+#define DDRSS1_PHY_465_DATA 0x00000000
+#define DDRSS1_PHY_466_DATA 0x00000000
+#define DDRSS1_PHY_467_DATA 0x00000000
+#define DDRSS1_PHY_468_DATA 0x00000000
+#define DDRSS1_PHY_469_DATA 0x00000000
+#define DDRSS1_PHY_470_DATA 0x00000000
+#define DDRSS1_PHY_471_DATA 0x00000000
+#define DDRSS1_PHY_472_DATA 0x00000000
+#define DDRSS1_PHY_473_DATA 0x00000000
+#define DDRSS1_PHY_474_DATA 0x00000000
+#define DDRSS1_PHY_475_DATA 0x00000000
+#define DDRSS1_PHY_476_DATA 0x00000000
+#define DDRSS1_PHY_477_DATA 0x00000000
+#define DDRSS1_PHY_478_DATA 0x00000000
+#define DDRSS1_PHY_479_DATA 0x00000000
+#define DDRSS1_PHY_480_DATA 0x00000000
+#define DDRSS1_PHY_481_DATA 0x00000000
+#define DDRSS1_PHY_482_DATA 0x00000000
+#define DDRSS1_PHY_483_DATA 0x00000000
+#define DDRSS1_PHY_484_DATA 0x00000000
+#define DDRSS1_PHY_485_DATA 0x00000000
+#define DDRSS1_PHY_486_DATA 0x00000000
+#define DDRSS1_PHY_487_DATA 0x00000000
+#define DDRSS1_PHY_488_DATA 0x00000000
+#define DDRSS1_PHY_489_DATA 0x00000000
+#define DDRSS1_PHY_490_DATA 0x00000000
+#define DDRSS1_PHY_491_DATA 0x00000000
+#define DDRSS1_PHY_492_DATA 0x00000000
+#define DDRSS1_PHY_493_DATA 0x00000000
+#define DDRSS1_PHY_494_DATA 0x00000000
+#define DDRSS1_PHY_495_DATA 0x00000000
+#define DDRSS1_PHY_496_DATA 0x00000000
+#define DDRSS1_PHY_497_DATA 0x00000000
+#define DDRSS1_PHY_498_DATA 0x00000000
+#define DDRSS1_PHY_499_DATA 0x00000000
+#define DDRSS1_PHY_500_DATA 0x00000000
+#define DDRSS1_PHY_501_DATA 0x00000000
+#define DDRSS1_PHY_502_DATA 0x00000000
+#define DDRSS1_PHY_503_DATA 0x00000000
+#define DDRSS1_PHY_504_DATA 0x00000000
+#define DDRSS1_PHY_505_DATA 0x00000000
+#define DDRSS1_PHY_506_DATA 0x00000000
+#define DDRSS1_PHY_507_DATA 0x00000000
+#define DDRSS1_PHY_508_DATA 0x00000000
+#define DDRSS1_PHY_509_DATA 0x00000000
+#define DDRSS1_PHY_510_DATA 0x00000000
+#define DDRSS1_PHY_511_DATA 0x00000000
+#define DDRSS1_PHY_512_DATA 0x000004F0
+#define DDRSS1_PHY_513_DATA 0x00000000
+#define DDRSS1_PHY_514_DATA 0x00030200
+#define DDRSS1_PHY_515_DATA 0x00000000
+#define DDRSS1_PHY_516_DATA 0x00000000
+#define DDRSS1_PHY_517_DATA 0x01030000
+#define DDRSS1_PHY_518_DATA 0x00010000
+#define DDRSS1_PHY_519_DATA 0x01030004
+#define DDRSS1_PHY_520_DATA 0x01000000
+#define DDRSS1_PHY_521_DATA 0x00000000
+#define DDRSS1_PHY_522_DATA 0x00000000
+#define DDRSS1_PHY_523_DATA 0x01000001
+#define DDRSS1_PHY_524_DATA 0x00000100
+#define DDRSS1_PHY_525_DATA 0x000800C0
+#define DDRSS1_PHY_526_DATA 0x060100CC
+#define DDRSS1_PHY_527_DATA 0x00030066
+#define DDRSS1_PHY_528_DATA 0x00000000
+#define DDRSS1_PHY_529_DATA 0x00000301
+#define DDRSS1_PHY_530_DATA 0x0000AAAA
+#define DDRSS1_PHY_531_DATA 0x00005555
+#define DDRSS1_PHY_532_DATA 0x0000B5B5
+#define DDRSS1_PHY_533_DATA 0x00004A4A
+#define DDRSS1_PHY_534_DATA 0x00005656
+#define DDRSS1_PHY_535_DATA 0x0000A9A9
+#define DDRSS1_PHY_536_DATA 0x0000A9A9
+#define DDRSS1_PHY_537_DATA 0x0000B5B5
+#define DDRSS1_PHY_538_DATA 0x00000000
+#define DDRSS1_PHY_539_DATA 0x00000000
+#define DDRSS1_PHY_540_DATA 0x2A000000
+#define DDRSS1_PHY_541_DATA 0x00000808
+#define DDRSS1_PHY_542_DATA 0x0F000000
+#define DDRSS1_PHY_543_DATA 0x00000F0F
+#define DDRSS1_PHY_544_DATA 0x10400000
+#define DDRSS1_PHY_545_DATA 0x0C002006
+#define DDRSS1_PHY_546_DATA 0x00000000
+#define DDRSS1_PHY_547_DATA 0x00000000
+#define DDRSS1_PHY_548_DATA 0x55555555
+#define DDRSS1_PHY_549_DATA 0xAAAAAAAA
+#define DDRSS1_PHY_550_DATA 0x55555555
+#define DDRSS1_PHY_551_DATA 0xAAAAAAAA
+#define DDRSS1_PHY_552_DATA 0x00005555
+#define DDRSS1_PHY_553_DATA 0x01000100
+#define DDRSS1_PHY_554_DATA 0x00800180
+#define DDRSS1_PHY_555_DATA 0x00000001
+#define DDRSS1_PHY_556_DATA 0x00000000
+#define DDRSS1_PHY_557_DATA 0x00000000
+#define DDRSS1_PHY_558_DATA 0x00000000
+#define DDRSS1_PHY_559_DATA 0x00000000
+#define DDRSS1_PHY_560_DATA 0x00000000
+#define DDRSS1_PHY_561_DATA 0x00000000
+#define DDRSS1_PHY_562_DATA 0x00000000
+#define DDRSS1_PHY_563_DATA 0x00000000
+#define DDRSS1_PHY_564_DATA 0x00000000
+#define DDRSS1_PHY_565_DATA 0x00000000
+#define DDRSS1_PHY_566_DATA 0x00000000
+#define DDRSS1_PHY_567_DATA 0x00000000
+#define DDRSS1_PHY_568_DATA 0x00000000
+#define DDRSS1_PHY_569_DATA 0x00000000
+#define DDRSS1_PHY_570_DATA 0x00000000
+#define DDRSS1_PHY_571_DATA 0x00000000
+#define DDRSS1_PHY_572_DATA 0x00000000
+#define DDRSS1_PHY_573_DATA 0x00000000
+#define DDRSS1_PHY_574_DATA 0x00000000
+#define DDRSS1_PHY_575_DATA 0x00000000
+#define DDRSS1_PHY_576_DATA 0x00000000
+#define DDRSS1_PHY_577_DATA 0x00000000
+#define DDRSS1_PHY_578_DATA 0x00000104
+#define DDRSS1_PHY_579_DATA 0x00000120
+#define DDRSS1_PHY_580_DATA 0x00000000
+#define DDRSS1_PHY_581_DATA 0x00000000
+#define DDRSS1_PHY_582_DATA 0x00000000
+#define DDRSS1_PHY_583_DATA 0x00000000
+#define DDRSS1_PHY_584_DATA 0x00000000
+#define DDRSS1_PHY_585_DATA 0x00000000
+#define DDRSS1_PHY_586_DATA 0x00000000
+#define DDRSS1_PHY_587_DATA 0x00000001
+#define DDRSS1_PHY_588_DATA 0x07FF0000
+#define DDRSS1_PHY_589_DATA 0x0080081F
+#define DDRSS1_PHY_590_DATA 0x00081020
+#define DDRSS1_PHY_591_DATA 0x04010000
+#define DDRSS1_PHY_592_DATA 0x00000000
+#define DDRSS1_PHY_593_DATA 0x00000000
+#define DDRSS1_PHY_594_DATA 0x00000000
+#define DDRSS1_PHY_595_DATA 0x00000100
+#define DDRSS1_PHY_596_DATA 0x01CC0C01
+#define DDRSS1_PHY_597_DATA 0x1003CC0C
+#define DDRSS1_PHY_598_DATA 0x20000140
+#define DDRSS1_PHY_599_DATA 0x07FF0200
+#define DDRSS1_PHY_600_DATA 0x0000DD01
+#define DDRSS1_PHY_601_DATA 0x10100303
+#define DDRSS1_PHY_602_DATA 0x10101010
+#define DDRSS1_PHY_603_DATA 0x10101010
+#define DDRSS1_PHY_604_DATA 0x00021010
+#define DDRSS1_PHY_605_DATA 0x00100010
+#define DDRSS1_PHY_606_DATA 0x00100010
+#define DDRSS1_PHY_607_DATA 0x00100010
+#define DDRSS1_PHY_608_DATA 0x00100010
+#define DDRSS1_PHY_609_DATA 0x00050010
+#define DDRSS1_PHY_610_DATA 0x51517041
+#define DDRSS1_PHY_611_DATA 0x31C06001
+#define DDRSS1_PHY_612_DATA 0x07AB0340
+#define DDRSS1_PHY_613_DATA 0x00C0C001
+#define DDRSS1_PHY_614_DATA 0x0E0D0001
+#define DDRSS1_PHY_615_DATA 0x10001000
+#define DDRSS1_PHY_616_DATA 0x0C083E42
+#define DDRSS1_PHY_617_DATA 0x0F0C3701
+#define DDRSS1_PHY_618_DATA 0x01000140
+#define DDRSS1_PHY_619_DATA 0x0C000420
+#define DDRSS1_PHY_620_DATA 0x00000198
+#define DDRSS1_PHY_621_DATA 0x0A0000D0
+#define DDRSS1_PHY_622_DATA 0x00030200
+#define DDRSS1_PHY_623_DATA 0x02800000
+#define DDRSS1_PHY_624_DATA 0x80800000
+#define DDRSS1_PHY_625_DATA 0x000E2010
+#define DDRSS1_PHY_626_DATA 0x76543210
+#define DDRSS1_PHY_627_DATA 0x00000008
+#define DDRSS1_PHY_628_DATA 0x02800280
+#define DDRSS1_PHY_629_DATA 0x02800280
+#define DDRSS1_PHY_630_DATA 0x02800280
+#define DDRSS1_PHY_631_DATA 0x02800280
+#define DDRSS1_PHY_632_DATA 0x00000280
+#define DDRSS1_PHY_633_DATA 0x0000A000
+#define DDRSS1_PHY_634_DATA 0x00A000A0
+#define DDRSS1_PHY_635_DATA 0x00A000A0
+#define DDRSS1_PHY_636_DATA 0x00A000A0
+#define DDRSS1_PHY_637_DATA 0x00A000A0
+#define DDRSS1_PHY_638_DATA 0x00A000A0
+#define DDRSS1_PHY_639_DATA 0x00A000A0
+#define DDRSS1_PHY_640_DATA 0x00A000A0
+#define DDRSS1_PHY_641_DATA 0x00A000A0
+#define DDRSS1_PHY_642_DATA 0x01C200A0
+#define DDRSS1_PHY_643_DATA 0x01A00005
+#define DDRSS1_PHY_644_DATA 0x00000000
+#define DDRSS1_PHY_645_DATA 0x00000000
+#define DDRSS1_PHY_646_DATA 0x00080200
+#define DDRSS1_PHY_647_DATA 0x00000000
+#define DDRSS1_PHY_648_DATA 0x20202000
+#define DDRSS1_PHY_649_DATA 0x20202020
+#define DDRSS1_PHY_650_DATA 0xF0F02020
+#define DDRSS1_PHY_651_DATA 0x00000000
+#define DDRSS1_PHY_652_DATA 0x00000000
+#define DDRSS1_PHY_653_DATA 0x00000000
+#define DDRSS1_PHY_654_DATA 0x00000000
+#define DDRSS1_PHY_655_DATA 0x00000000
+#define DDRSS1_PHY_656_DATA 0x00000000
+#define DDRSS1_PHY_657_DATA 0x00000000
+#define DDRSS1_PHY_658_DATA 0x00000000
+#define DDRSS1_PHY_659_DATA 0x00000000
+#define DDRSS1_PHY_660_DATA 0x00000000
+#define DDRSS1_PHY_661_DATA 0x00000000
+#define DDRSS1_PHY_662_DATA 0x00000000
+#define DDRSS1_PHY_663_DATA 0x00000000
+#define DDRSS1_PHY_664_DATA 0x00000000
+#define DDRSS1_PHY_665_DATA 0x00000000
+#define DDRSS1_PHY_666_DATA 0x00000000
+#define DDRSS1_PHY_667_DATA 0x00000000
+#define DDRSS1_PHY_668_DATA 0x00000000
+#define DDRSS1_PHY_669_DATA 0x00000000
+#define DDRSS1_PHY_670_DATA 0x00000000
+#define DDRSS1_PHY_671_DATA 0x00000000
+#define DDRSS1_PHY_672_DATA 0x00000000
+#define DDRSS1_PHY_673_DATA 0x00000000
+#define DDRSS1_PHY_674_DATA 0x00000000
+#define DDRSS1_PHY_675_DATA 0x00000000
+#define DDRSS1_PHY_676_DATA 0x00000000
+#define DDRSS1_PHY_677_DATA 0x00000000
+#define DDRSS1_PHY_678_DATA 0x00000000
+#define DDRSS1_PHY_679_DATA 0x00000000
+#define DDRSS1_PHY_680_DATA 0x00000000
+#define DDRSS1_PHY_681_DATA 0x00000000
+#define DDRSS1_PHY_682_DATA 0x00000000
+#define DDRSS1_PHY_683_DATA 0x00000000
+#define DDRSS1_PHY_684_DATA 0x00000000
+#define DDRSS1_PHY_685_DATA 0x00000000
+#define DDRSS1_PHY_686_DATA 0x00000000
+#define DDRSS1_PHY_687_DATA 0x00000000
+#define DDRSS1_PHY_688_DATA 0x00000000
+#define DDRSS1_PHY_689_DATA 0x00000000
+#define DDRSS1_PHY_690_DATA 0x00000000
+#define DDRSS1_PHY_691_DATA 0x00000000
+#define DDRSS1_PHY_692_DATA 0x00000000
+#define DDRSS1_PHY_693_DATA 0x00000000
+#define DDRSS1_PHY_694_DATA 0x00000000
+#define DDRSS1_PHY_695_DATA 0x00000000
+#define DDRSS1_PHY_696_DATA 0x00000000
+#define DDRSS1_PHY_697_DATA 0x00000000
+#define DDRSS1_PHY_698_DATA 0x00000000
+#define DDRSS1_PHY_699_DATA 0x00000000
+#define DDRSS1_PHY_700_DATA 0x00000000
+#define DDRSS1_PHY_701_DATA 0x00000000
+#define DDRSS1_PHY_702_DATA 0x00000000
+#define DDRSS1_PHY_703_DATA 0x00000000
+#define DDRSS1_PHY_704_DATA 0x00000000
+#define DDRSS1_PHY_705_DATA 0x00000000
+#define DDRSS1_PHY_706_DATA 0x00000000
+#define DDRSS1_PHY_707_DATA 0x00000000
+#define DDRSS1_PHY_708_DATA 0x00000000
+#define DDRSS1_PHY_709_DATA 0x00000000
+#define DDRSS1_PHY_710_DATA 0x00000000
+#define DDRSS1_PHY_711_DATA 0x00000000
+#define DDRSS1_PHY_712_DATA 0x00000000
+#define DDRSS1_PHY_713_DATA 0x00000000
+#define DDRSS1_PHY_714_DATA 0x00000000
+#define DDRSS1_PHY_715_DATA 0x00000000
+#define DDRSS1_PHY_716_DATA 0x00000000
+#define DDRSS1_PHY_717_DATA 0x00000000
+#define DDRSS1_PHY_718_DATA 0x00000000
+#define DDRSS1_PHY_719_DATA 0x00000000
+#define DDRSS1_PHY_720_DATA 0x00000000
+#define DDRSS1_PHY_721_DATA 0x00000000
+#define DDRSS1_PHY_722_DATA 0x00000000
+#define DDRSS1_PHY_723_DATA 0x00000000
+#define DDRSS1_PHY_724_DATA 0x00000000
+#define DDRSS1_PHY_725_DATA 0x00000000
+#define DDRSS1_PHY_726_DATA 0x00000000
+#define DDRSS1_PHY_727_DATA 0x00000000
+#define DDRSS1_PHY_728_DATA 0x00000000
+#define DDRSS1_PHY_729_DATA 0x00000000
+#define DDRSS1_PHY_730_DATA 0x00000000
+#define DDRSS1_PHY_731_DATA 0x00000000
+#define DDRSS1_PHY_732_DATA 0x00000000
+#define DDRSS1_PHY_733_DATA 0x00000000
+#define DDRSS1_PHY_734_DATA 0x00000000
+#define DDRSS1_PHY_735_DATA 0x00000000
+#define DDRSS1_PHY_736_DATA 0x00000000
+#define DDRSS1_PHY_737_DATA 0x00000000
+#define DDRSS1_PHY_738_DATA 0x00000000
+#define DDRSS1_PHY_739_DATA 0x00000000
+#define DDRSS1_PHY_740_DATA 0x00000000
+#define DDRSS1_PHY_741_DATA 0x00000000
+#define DDRSS1_PHY_742_DATA 0x00000000
+#define DDRSS1_PHY_743_DATA 0x00000000
+#define DDRSS1_PHY_744_DATA 0x00000000
+#define DDRSS1_PHY_745_DATA 0x00000000
+#define DDRSS1_PHY_746_DATA 0x00000000
+#define DDRSS1_PHY_747_DATA 0x00000000
+#define DDRSS1_PHY_748_DATA 0x00000000
+#define DDRSS1_PHY_749_DATA 0x00000000
+#define DDRSS1_PHY_750_DATA 0x00000000
+#define DDRSS1_PHY_751_DATA 0x00000000
+#define DDRSS1_PHY_752_DATA 0x00000000
+#define DDRSS1_PHY_753_DATA 0x00000000
+#define DDRSS1_PHY_754_DATA 0x00000000
+#define DDRSS1_PHY_755_DATA 0x00000000
+#define DDRSS1_PHY_756_DATA 0x00000000
+#define DDRSS1_PHY_757_DATA 0x00000000
+#define DDRSS1_PHY_758_DATA 0x00000000
+#define DDRSS1_PHY_759_DATA 0x00000000
+#define DDRSS1_PHY_760_DATA 0x00000000
+#define DDRSS1_PHY_761_DATA 0x00000000
+#define DDRSS1_PHY_762_DATA 0x00000000
+#define DDRSS1_PHY_763_DATA 0x00000000
+#define DDRSS1_PHY_764_DATA 0x00000000
+#define DDRSS1_PHY_765_DATA 0x00000000
+#define DDRSS1_PHY_766_DATA 0x00000000
+#define DDRSS1_PHY_767_DATA 0x00000000
+#define DDRSS1_PHY_768_DATA 0x000004F0
+#define DDRSS1_PHY_769_DATA 0x00000000
+#define DDRSS1_PHY_770_DATA 0x00030200
+#define DDRSS1_PHY_771_DATA 0x00000000
+#define DDRSS1_PHY_772_DATA 0x00000000
+#define DDRSS1_PHY_773_DATA 0x01030000
+#define DDRSS1_PHY_774_DATA 0x00010000
+#define DDRSS1_PHY_775_DATA 0x01030004
+#define DDRSS1_PHY_776_DATA 0x01000000
+#define DDRSS1_PHY_777_DATA 0x00000000
+#define DDRSS1_PHY_778_DATA 0x00000000
+#define DDRSS1_PHY_779_DATA 0x01000001
+#define DDRSS1_PHY_780_DATA 0x00000100
+#define DDRSS1_PHY_781_DATA 0x000800C0
+#define DDRSS1_PHY_782_DATA 0x060100CC
+#define DDRSS1_PHY_783_DATA 0x00030066
+#define DDRSS1_PHY_784_DATA 0x00000000
+#define DDRSS1_PHY_785_DATA 0x00000301
+#define DDRSS1_PHY_786_DATA 0x0000AAAA
+#define DDRSS1_PHY_787_DATA 0x00005555
+#define DDRSS1_PHY_788_DATA 0x0000B5B5
+#define DDRSS1_PHY_789_DATA 0x00004A4A
+#define DDRSS1_PHY_790_DATA 0x00005656
+#define DDRSS1_PHY_791_DATA 0x0000A9A9
+#define DDRSS1_PHY_792_DATA 0x0000A9A9
+#define DDRSS1_PHY_793_DATA 0x0000B5B5
+#define DDRSS1_PHY_794_DATA 0x00000000
+#define DDRSS1_PHY_795_DATA 0x00000000
+#define DDRSS1_PHY_796_DATA 0x2A000000
+#define DDRSS1_PHY_797_DATA 0x00000808
+#define DDRSS1_PHY_798_DATA 0x0F000000
+#define DDRSS1_PHY_799_DATA 0x00000F0F
+#define DDRSS1_PHY_800_DATA 0x10400000
+#define DDRSS1_PHY_801_DATA 0x0C002006
+#define DDRSS1_PHY_802_DATA 0x00000000
+#define DDRSS1_PHY_803_DATA 0x00000000
+#define DDRSS1_PHY_804_DATA 0x55555555
+#define DDRSS1_PHY_805_DATA 0xAAAAAAAA
+#define DDRSS1_PHY_806_DATA 0x55555555
+#define DDRSS1_PHY_807_DATA 0xAAAAAAAA
+#define DDRSS1_PHY_808_DATA 0x00005555
+#define DDRSS1_PHY_809_DATA 0x01000100
+#define DDRSS1_PHY_810_DATA 0x00800180
+#define DDRSS1_PHY_811_DATA 0x00000000
+#define DDRSS1_PHY_812_DATA 0x00000000
+#define DDRSS1_PHY_813_DATA 0x00000000
+#define DDRSS1_PHY_814_DATA 0x00000000
+#define DDRSS1_PHY_815_DATA 0x00000000
+#define DDRSS1_PHY_816_DATA 0x00000000
+#define DDRSS1_PHY_817_DATA 0x00000000
+#define DDRSS1_PHY_818_DATA 0x00000000
+#define DDRSS1_PHY_819_DATA 0x00000000
+#define DDRSS1_PHY_820_DATA 0x00000000
+#define DDRSS1_PHY_821_DATA 0x00000000
+#define DDRSS1_PHY_822_DATA 0x00000000
+#define DDRSS1_PHY_823_DATA 0x00000000
+#define DDRSS1_PHY_824_DATA 0x00000000
+#define DDRSS1_PHY_825_DATA 0x00000000
+#define DDRSS1_PHY_826_DATA 0x00000000
+#define DDRSS1_PHY_827_DATA 0x00000000
+#define DDRSS1_PHY_828_DATA 0x00000000
+#define DDRSS1_PHY_829_DATA 0x00000000
+#define DDRSS1_PHY_830_DATA 0x00000000
+#define DDRSS1_PHY_831_DATA 0x00000000
+#define DDRSS1_PHY_832_DATA 0x00000000
+#define DDRSS1_PHY_833_DATA 0x00000000
+#define DDRSS1_PHY_834_DATA 0x00000104
+#define DDRSS1_PHY_835_DATA 0x00000120
+#define DDRSS1_PHY_836_DATA 0x00000000
+#define DDRSS1_PHY_837_DATA 0x00000000
+#define DDRSS1_PHY_838_DATA 0x00000000
+#define DDRSS1_PHY_839_DATA 0x00000000
+#define DDRSS1_PHY_840_DATA 0x00000000
+#define DDRSS1_PHY_841_DATA 0x00000000
+#define DDRSS1_PHY_842_DATA 0x00000000
+#define DDRSS1_PHY_843_DATA 0x00000001
+#define DDRSS1_PHY_844_DATA 0x07FF0000
+#define DDRSS1_PHY_845_DATA 0x0080081F
+#define DDRSS1_PHY_846_DATA 0x00081020
+#define DDRSS1_PHY_847_DATA 0x04010000
+#define DDRSS1_PHY_848_DATA 0x00000000
+#define DDRSS1_PHY_849_DATA 0x00000000
+#define DDRSS1_PHY_850_DATA 0x00000000
+#define DDRSS1_PHY_851_DATA 0x00000100
+#define DDRSS1_PHY_852_DATA 0x01CC0C01
+#define DDRSS1_PHY_853_DATA 0x1003CC0C
+#define DDRSS1_PHY_854_DATA 0x20000140
+#define DDRSS1_PHY_855_DATA 0x07FF0200
+#define DDRSS1_PHY_856_DATA 0x0000DD01
+#define DDRSS1_PHY_857_DATA 0x10100303
+#define DDRSS1_PHY_858_DATA 0x10101010
+#define DDRSS1_PHY_859_DATA 0x10101010
+#define DDRSS1_PHY_860_DATA 0x00021010
+#define DDRSS1_PHY_861_DATA 0x00100010
+#define DDRSS1_PHY_862_DATA 0x00100010
+#define DDRSS1_PHY_863_DATA 0x00100010
+#define DDRSS1_PHY_864_DATA 0x00100010
+#define DDRSS1_PHY_865_DATA 0x00050010
+#define DDRSS1_PHY_866_DATA 0x51517041
+#define DDRSS1_PHY_867_DATA 0x31C06001
+#define DDRSS1_PHY_868_DATA 0x07AB0340
+#define DDRSS1_PHY_869_DATA 0x00C0C001
+#define DDRSS1_PHY_870_DATA 0x0E0D0001
+#define DDRSS1_PHY_871_DATA 0x10001000
+#define DDRSS1_PHY_872_DATA 0x0C083E42
+#define DDRSS1_PHY_873_DATA 0x0F0C3701
+#define DDRSS1_PHY_874_DATA 0x01000140
+#define DDRSS1_PHY_875_DATA 0x0C000420
+#define DDRSS1_PHY_876_DATA 0x00000198
+#define DDRSS1_PHY_877_DATA 0x0A0000D0
+#define DDRSS1_PHY_878_DATA 0x00030200
+#define DDRSS1_PHY_879_DATA 0x02800000
+#define DDRSS1_PHY_880_DATA 0x80800000
+#define DDRSS1_PHY_881_DATA 0x000E2010
+#define DDRSS1_PHY_882_DATA 0x76543210
+#define DDRSS1_PHY_883_DATA 0x00000008
+#define DDRSS1_PHY_884_DATA 0x02800280
+#define DDRSS1_PHY_885_DATA 0x02800280
+#define DDRSS1_PHY_886_DATA 0x02800280
+#define DDRSS1_PHY_887_DATA 0x02800280
+#define DDRSS1_PHY_888_DATA 0x00000280
+#define DDRSS1_PHY_889_DATA 0x0000A000
+#define DDRSS1_PHY_890_DATA 0x00A000A0
+#define DDRSS1_PHY_891_DATA 0x00A000A0
+#define DDRSS1_PHY_892_DATA 0x00A000A0
+#define DDRSS1_PHY_893_DATA 0x00A000A0
+#define DDRSS1_PHY_894_DATA 0x00A000A0
+#define DDRSS1_PHY_895_DATA 0x00A000A0
+#define DDRSS1_PHY_896_DATA 0x00A000A0
+#define DDRSS1_PHY_897_DATA 0x00A000A0
+#define DDRSS1_PHY_898_DATA 0x01C200A0
+#define DDRSS1_PHY_899_DATA 0x01A00005
+#define DDRSS1_PHY_900_DATA 0x00000000
+#define DDRSS1_PHY_901_DATA 0x00000000
+#define DDRSS1_PHY_902_DATA 0x00080200
+#define DDRSS1_PHY_903_DATA 0x00000000
+#define DDRSS1_PHY_904_DATA 0x20202000
+#define DDRSS1_PHY_905_DATA 0x20202020
+#define DDRSS1_PHY_906_DATA 0xF0F02020
+#define DDRSS1_PHY_907_DATA 0x00000000
+#define DDRSS1_PHY_908_DATA 0x00000000
+#define DDRSS1_PHY_909_DATA 0x00000000
+#define DDRSS1_PHY_910_DATA 0x00000000
+#define DDRSS1_PHY_911_DATA 0x00000000
+#define DDRSS1_PHY_912_DATA 0x00000000
+#define DDRSS1_PHY_913_DATA 0x00000000
+#define DDRSS1_PHY_914_DATA 0x00000000
+#define DDRSS1_PHY_915_DATA 0x00000000
+#define DDRSS1_PHY_916_DATA 0x00000000
+#define DDRSS1_PHY_917_DATA 0x00000000
+#define DDRSS1_PHY_918_DATA 0x00000000
+#define DDRSS1_PHY_919_DATA 0x00000000
+#define DDRSS1_PHY_920_DATA 0x00000000
+#define DDRSS1_PHY_921_DATA 0x00000000
+#define DDRSS1_PHY_922_DATA 0x00000000
+#define DDRSS1_PHY_923_DATA 0x00000000
+#define DDRSS1_PHY_924_DATA 0x00000000
+#define DDRSS1_PHY_925_DATA 0x00000000
+#define DDRSS1_PHY_926_DATA 0x00000000
+#define DDRSS1_PHY_927_DATA 0x00000000
+#define DDRSS1_PHY_928_DATA 0x00000000
+#define DDRSS1_PHY_929_DATA 0x00000000
+#define DDRSS1_PHY_930_DATA 0x00000000
+#define DDRSS1_PHY_931_DATA 0x00000000
+#define DDRSS1_PHY_932_DATA 0x00000000
+#define DDRSS1_PHY_933_DATA 0x00000000
+#define DDRSS1_PHY_934_DATA 0x00000000
+#define DDRSS1_PHY_935_DATA 0x00000000
+#define DDRSS1_PHY_936_DATA 0x00000000
+#define DDRSS1_PHY_937_DATA 0x00000000
+#define DDRSS1_PHY_938_DATA 0x00000000
+#define DDRSS1_PHY_939_DATA 0x00000000
+#define DDRSS1_PHY_940_DATA 0x00000000
+#define DDRSS1_PHY_941_DATA 0x00000000
+#define DDRSS1_PHY_942_DATA 0x00000000
+#define DDRSS1_PHY_943_DATA 0x00000000
+#define DDRSS1_PHY_944_DATA 0x00000000
+#define DDRSS1_PHY_945_DATA 0x00000000
+#define DDRSS1_PHY_946_DATA 0x00000000
+#define DDRSS1_PHY_947_DATA 0x00000000
+#define DDRSS1_PHY_948_DATA 0x00000000
+#define DDRSS1_PHY_949_DATA 0x00000000
+#define DDRSS1_PHY_950_DATA 0x00000000
+#define DDRSS1_PHY_951_DATA 0x00000000
+#define DDRSS1_PHY_952_DATA 0x00000000
+#define DDRSS1_PHY_953_DATA 0x00000000
+#define DDRSS1_PHY_954_DATA 0x00000000
+#define DDRSS1_PHY_955_DATA 0x00000000
+#define DDRSS1_PHY_956_DATA 0x00000000
+#define DDRSS1_PHY_957_DATA 0x00000000
+#define DDRSS1_PHY_958_DATA 0x00000000
+#define DDRSS1_PHY_959_DATA 0x00000000
+#define DDRSS1_PHY_960_DATA 0x00000000
+#define DDRSS1_PHY_961_DATA 0x00000000
+#define DDRSS1_PHY_962_DATA 0x00000000
+#define DDRSS1_PHY_963_DATA 0x00000000
+#define DDRSS1_PHY_964_DATA 0x00000000
+#define DDRSS1_PHY_965_DATA 0x00000000
+#define DDRSS1_PHY_966_DATA 0x00000000
+#define DDRSS1_PHY_967_DATA 0x00000000
+#define DDRSS1_PHY_968_DATA 0x00000000
+#define DDRSS1_PHY_969_DATA 0x00000000
+#define DDRSS1_PHY_970_DATA 0x00000000
+#define DDRSS1_PHY_971_DATA 0x00000000
+#define DDRSS1_PHY_972_DATA 0x00000000
+#define DDRSS1_PHY_973_DATA 0x00000000
+#define DDRSS1_PHY_974_DATA 0x00000000
+#define DDRSS1_PHY_975_DATA 0x00000000
+#define DDRSS1_PHY_976_DATA 0x00000000
+#define DDRSS1_PHY_977_DATA 0x00000000
+#define DDRSS1_PHY_978_DATA 0x00000000
+#define DDRSS1_PHY_979_DATA 0x00000000
+#define DDRSS1_PHY_980_DATA 0x00000000
+#define DDRSS1_PHY_981_DATA 0x00000000
+#define DDRSS1_PHY_982_DATA 0x00000000
+#define DDRSS1_PHY_983_DATA 0x00000000
+#define DDRSS1_PHY_984_DATA 0x00000000
+#define DDRSS1_PHY_985_DATA 0x00000000
+#define DDRSS1_PHY_986_DATA 0x00000000
+#define DDRSS1_PHY_987_DATA 0x00000000
+#define DDRSS1_PHY_988_DATA 0x00000000
+#define DDRSS1_PHY_989_DATA 0x00000000
+#define DDRSS1_PHY_990_DATA 0x00000000
+#define DDRSS1_PHY_991_DATA 0x00000000
+#define DDRSS1_PHY_992_DATA 0x00000000
+#define DDRSS1_PHY_993_DATA 0x00000000
+#define DDRSS1_PHY_994_DATA 0x00000000
+#define DDRSS1_PHY_995_DATA 0x00000000
+#define DDRSS1_PHY_996_DATA 0x00000000
+#define DDRSS1_PHY_997_DATA 0x00000000
+#define DDRSS1_PHY_998_DATA 0x00000000
+#define DDRSS1_PHY_999_DATA 0x00000000
+#define DDRSS1_PHY_1000_DATA 0x00000000
+#define DDRSS1_PHY_1001_DATA 0x00000000
+#define DDRSS1_PHY_1002_DATA 0x00000000
+#define DDRSS1_PHY_1003_DATA 0x00000000
+#define DDRSS1_PHY_1004_DATA 0x00000000
+#define DDRSS1_PHY_1005_DATA 0x00000000
+#define DDRSS1_PHY_1006_DATA 0x00000000
+#define DDRSS1_PHY_1007_DATA 0x00000000
+#define DDRSS1_PHY_1008_DATA 0x00000000
+#define DDRSS1_PHY_1009_DATA 0x00000000
+#define DDRSS1_PHY_1010_DATA 0x00000000
+#define DDRSS1_PHY_1011_DATA 0x00000000
+#define DDRSS1_PHY_1012_DATA 0x00000000
+#define DDRSS1_PHY_1013_DATA 0x00000000
+#define DDRSS1_PHY_1014_DATA 0x00000000
+#define DDRSS1_PHY_1015_DATA 0x00000000
+#define DDRSS1_PHY_1016_DATA 0x00000000
+#define DDRSS1_PHY_1017_DATA 0x00000000
+#define DDRSS1_PHY_1018_DATA 0x00000000
+#define DDRSS1_PHY_1019_DATA 0x00000000
+#define DDRSS1_PHY_1020_DATA 0x00000000
+#define DDRSS1_PHY_1021_DATA 0x00000000
+#define DDRSS1_PHY_1022_DATA 0x00000000
+#define DDRSS1_PHY_1023_DATA 0x00000000
+#define DDRSS1_PHY_1024_DATA 0x00000000
+#define DDRSS1_PHY_1025_DATA 0x00000000
+#define DDRSS1_PHY_1026_DATA 0x00000000
+#define DDRSS1_PHY_1027_DATA 0x00000000
+#define DDRSS1_PHY_1028_DATA 0x00000000
+#define DDRSS1_PHY_1029_DATA 0x00000100
+#define DDRSS1_PHY_1030_DATA 0x00000200
+#define DDRSS1_PHY_1031_DATA 0x00000000
+#define DDRSS1_PHY_1032_DATA 0x00000000
+#define DDRSS1_PHY_1033_DATA 0x00000000
+#define DDRSS1_PHY_1034_DATA 0x00000000
+#define DDRSS1_PHY_1035_DATA 0x00400000
+#define DDRSS1_PHY_1036_DATA 0x00000080
+#define DDRSS1_PHY_1037_DATA 0x00DCBA98
+#define DDRSS1_PHY_1038_DATA 0x03000000
+#define DDRSS1_PHY_1039_DATA 0x00200000
+#define DDRSS1_PHY_1040_DATA 0x00000000
+#define DDRSS1_PHY_1041_DATA 0x00000000
+#define DDRSS1_PHY_1042_DATA 0x00000000
+#define DDRSS1_PHY_1043_DATA 0x00000000
+#define DDRSS1_PHY_1044_DATA 0x00000000
+#define DDRSS1_PHY_1045_DATA 0x0000002A
+#define DDRSS1_PHY_1046_DATA 0x00000015
+#define DDRSS1_PHY_1047_DATA 0x00000015
+#define DDRSS1_PHY_1048_DATA 0x0000002A
+#define DDRSS1_PHY_1049_DATA 0x00000033
+#define DDRSS1_PHY_1050_DATA 0x0000000C
+#define DDRSS1_PHY_1051_DATA 0x0000000C
+#define DDRSS1_PHY_1052_DATA 0x00000033
+#define DDRSS1_PHY_1053_DATA 0x00543210
+#define DDRSS1_PHY_1054_DATA 0x003F0000
+#define DDRSS1_PHY_1055_DATA 0x000F013F
+#define DDRSS1_PHY_1056_DATA 0x20202003
+#define DDRSS1_PHY_1057_DATA 0x00202020
+#define DDRSS1_PHY_1058_DATA 0x20008008
+#define DDRSS1_PHY_1059_DATA 0x00000810
+#define DDRSS1_PHY_1060_DATA 0x00000F00
+#define DDRSS1_PHY_1061_DATA 0x00000000
+#define DDRSS1_PHY_1062_DATA 0x00000000
+#define DDRSS1_PHY_1063_DATA 0x00000000
+#define DDRSS1_PHY_1064_DATA 0x000305CC
+#define DDRSS1_PHY_1065_DATA 0x00030000
+#define DDRSS1_PHY_1066_DATA 0x00000300
+#define DDRSS1_PHY_1067_DATA 0x00000300
+#define DDRSS1_PHY_1068_DATA 0x00000300
+#define DDRSS1_PHY_1069_DATA 0x00000300
+#define DDRSS1_PHY_1070_DATA 0x00000300
+#define DDRSS1_PHY_1071_DATA 0x42080010
+#define DDRSS1_PHY_1072_DATA 0x0000803E
+#define DDRSS1_PHY_1073_DATA 0x00000001
+#define DDRSS1_PHY_1074_DATA 0x01000102
+#define DDRSS1_PHY_1075_DATA 0x00008000
+#define DDRSS1_PHY_1076_DATA 0x00000000
+#define DDRSS1_PHY_1077_DATA 0x00000000
+#define DDRSS1_PHY_1078_DATA 0x00000000
+#define DDRSS1_PHY_1079_DATA 0x00000000
+#define DDRSS1_PHY_1080_DATA 0x00000000
+#define DDRSS1_PHY_1081_DATA 0x00000000
+#define DDRSS1_PHY_1082_DATA 0x00000000
+#define DDRSS1_PHY_1083_DATA 0x00000000
+#define DDRSS1_PHY_1084_DATA 0x00000000
+#define DDRSS1_PHY_1085_DATA 0x00000000
+#define DDRSS1_PHY_1086_DATA 0x00000000
+#define DDRSS1_PHY_1087_DATA 0x00000000
+#define DDRSS1_PHY_1088_DATA 0x00000000
+#define DDRSS1_PHY_1089_DATA 0x00000000
+#define DDRSS1_PHY_1090_DATA 0x00000000
+#define DDRSS1_PHY_1091_DATA 0x00000000
+#define DDRSS1_PHY_1092_DATA 0x00000000
+#define DDRSS1_PHY_1093_DATA 0x00000000
+#define DDRSS1_PHY_1094_DATA 0x00000000
+#define DDRSS1_PHY_1095_DATA 0x00000000
+#define DDRSS1_PHY_1096_DATA 0x00000000
+#define DDRSS1_PHY_1097_DATA 0x00000000
+#define DDRSS1_PHY_1098_DATA 0x00000000
+#define DDRSS1_PHY_1099_DATA 0x00000000
+#define DDRSS1_PHY_1100_DATA 0x00000000
+#define DDRSS1_PHY_1101_DATA 0x00000000
+#define DDRSS1_PHY_1102_DATA 0x00000000
+#define DDRSS1_PHY_1103_DATA 0x00000000
+#define DDRSS1_PHY_1104_DATA 0x00000000
+#define DDRSS1_PHY_1105_DATA 0x00000000
+#define DDRSS1_PHY_1106_DATA 0x00000000
+#define DDRSS1_PHY_1107_DATA 0x00000000
+#define DDRSS1_PHY_1108_DATA 0x00000000
+#define DDRSS1_PHY_1109_DATA 0x00000000
+#define DDRSS1_PHY_1110_DATA 0x00000000
+#define DDRSS1_PHY_1111_DATA 0x00000000
+#define DDRSS1_PHY_1112_DATA 0x00000000
+#define DDRSS1_PHY_1113_DATA 0x00000000
+#define DDRSS1_PHY_1114_DATA 0x00000000
+#define DDRSS1_PHY_1115_DATA 0x00000000
+#define DDRSS1_PHY_1116_DATA 0x00000000
+#define DDRSS1_PHY_1117_DATA 0x00000000
+#define DDRSS1_PHY_1118_DATA 0x00000000
+#define DDRSS1_PHY_1119_DATA 0x00000000
+#define DDRSS1_PHY_1120_DATA 0x00000000
+#define DDRSS1_PHY_1121_DATA 0x00000000
+#define DDRSS1_PHY_1122_DATA 0x00000000
+#define DDRSS1_PHY_1123_DATA 0x00000000
+#define DDRSS1_PHY_1124_DATA 0x00000000
+#define DDRSS1_PHY_1125_DATA 0x00000000
+#define DDRSS1_PHY_1126_DATA 0x00000000
+#define DDRSS1_PHY_1127_DATA 0x00000000
+#define DDRSS1_PHY_1128_DATA 0x00000000
+#define DDRSS1_PHY_1129_DATA 0x00000000
+#define DDRSS1_PHY_1130_DATA 0x00000000
+#define DDRSS1_PHY_1131_DATA 0x00000000
+#define DDRSS1_PHY_1132_DATA 0x00000000
+#define DDRSS1_PHY_1133_DATA 0x00000000
+#define DDRSS1_PHY_1134_DATA 0x00000000
+#define DDRSS1_PHY_1135_DATA 0x00000000
+#define DDRSS1_PHY_1136_DATA 0x00000000
+#define DDRSS1_PHY_1137_DATA 0x00000000
+#define DDRSS1_PHY_1138_DATA 0x00000000
+#define DDRSS1_PHY_1139_DATA 0x00000000
+#define DDRSS1_PHY_1140_DATA 0x00000000
+#define DDRSS1_PHY_1141_DATA 0x00000000
+#define DDRSS1_PHY_1142_DATA 0x00000000
+#define DDRSS1_PHY_1143_DATA 0x00000000
+#define DDRSS1_PHY_1144_DATA 0x00000000
+#define DDRSS1_PHY_1145_DATA 0x00000000
+#define DDRSS1_PHY_1146_DATA 0x00000000
+#define DDRSS1_PHY_1147_DATA 0x00000000
+#define DDRSS1_PHY_1148_DATA 0x00000000
+#define DDRSS1_PHY_1149_DATA 0x00000000
+#define DDRSS1_PHY_1150_DATA 0x00000000
+#define DDRSS1_PHY_1151_DATA 0x00000000
+#define DDRSS1_PHY_1152_DATA 0x00000000
+#define DDRSS1_PHY_1153_DATA 0x00000000
+#define DDRSS1_PHY_1154_DATA 0x00000000
+#define DDRSS1_PHY_1155_DATA 0x00000000
+#define DDRSS1_PHY_1156_DATA 0x00000000
+#define DDRSS1_PHY_1157_DATA 0x00000000
+#define DDRSS1_PHY_1158_DATA 0x00000000
+#define DDRSS1_PHY_1159_DATA 0x00000000
+#define DDRSS1_PHY_1160_DATA 0x00000000
+#define DDRSS1_PHY_1161_DATA 0x00000000
+#define DDRSS1_PHY_1162_DATA 0x00000000
+#define DDRSS1_PHY_1163_DATA 0x00000000
+#define DDRSS1_PHY_1164_DATA 0x00000000
+#define DDRSS1_PHY_1165_DATA 0x00000000
+#define DDRSS1_PHY_1166_DATA 0x00000000
+#define DDRSS1_PHY_1167_DATA 0x00000000
+#define DDRSS1_PHY_1168_DATA 0x00000000
+#define DDRSS1_PHY_1169_DATA 0x00000000
+#define DDRSS1_PHY_1170_DATA 0x00000000
+#define DDRSS1_PHY_1171_DATA 0x00000000
+#define DDRSS1_PHY_1172_DATA 0x00000000
+#define DDRSS1_PHY_1173_DATA 0x00000000
+#define DDRSS1_PHY_1174_DATA 0x00000000
+#define DDRSS1_PHY_1175_DATA 0x00000000
+#define DDRSS1_PHY_1176_DATA 0x00000000
+#define DDRSS1_PHY_1177_DATA 0x00000000
+#define DDRSS1_PHY_1178_DATA 0x00000000
+#define DDRSS1_PHY_1179_DATA 0x00000000
+#define DDRSS1_PHY_1180_DATA 0x00000000
+#define DDRSS1_PHY_1181_DATA 0x00000000
+#define DDRSS1_PHY_1182_DATA 0x00000000
+#define DDRSS1_PHY_1183_DATA 0x00000000
+#define DDRSS1_PHY_1184_DATA 0x00000000
+#define DDRSS1_PHY_1185_DATA 0x00000000
+#define DDRSS1_PHY_1186_DATA 0x00000000
+#define DDRSS1_PHY_1187_DATA 0x00000000
+#define DDRSS1_PHY_1188_DATA 0x00000000
+#define DDRSS1_PHY_1189_DATA 0x00000000
+#define DDRSS1_PHY_1190_DATA 0x00000000
+#define DDRSS1_PHY_1191_DATA 0x00000000
+#define DDRSS1_PHY_1192_DATA 0x00000000
+#define DDRSS1_PHY_1193_DATA 0x00000000
+#define DDRSS1_PHY_1194_DATA 0x00000000
+#define DDRSS1_PHY_1195_DATA 0x00000000
+#define DDRSS1_PHY_1196_DATA 0x00000000
+#define DDRSS1_PHY_1197_DATA 0x00000000
+#define DDRSS1_PHY_1198_DATA 0x00000000
+#define DDRSS1_PHY_1199_DATA 0x00000000
+#define DDRSS1_PHY_1200_DATA 0x00000000
+#define DDRSS1_PHY_1201_DATA 0x00000000
+#define DDRSS1_PHY_1202_DATA 0x00000000
+#define DDRSS1_PHY_1203_DATA 0x00000000
+#define DDRSS1_PHY_1204_DATA 0x00000000
+#define DDRSS1_PHY_1205_DATA 0x00000000
+#define DDRSS1_PHY_1206_DATA 0x00000000
+#define DDRSS1_PHY_1207_DATA 0x00000000
+#define DDRSS1_PHY_1208_DATA 0x00000000
+#define DDRSS1_PHY_1209_DATA 0x00000000
+#define DDRSS1_PHY_1210_DATA 0x00000000
+#define DDRSS1_PHY_1211_DATA 0x00000000
+#define DDRSS1_PHY_1212_DATA 0x00000000
+#define DDRSS1_PHY_1213_DATA 0x00000000
+#define DDRSS1_PHY_1214_DATA 0x00000000
+#define DDRSS1_PHY_1215_DATA 0x00000000
+#define DDRSS1_PHY_1216_DATA 0x00000000
+#define DDRSS1_PHY_1217_DATA 0x00000000
+#define DDRSS1_PHY_1218_DATA 0x00000000
+#define DDRSS1_PHY_1219_DATA 0x00000000
+#define DDRSS1_PHY_1220_DATA 0x00000000
+#define DDRSS1_PHY_1221_DATA 0x00000000
+#define DDRSS1_PHY_1222_DATA 0x00000000
+#define DDRSS1_PHY_1223_DATA 0x00000000
+#define DDRSS1_PHY_1224_DATA 0x00000000
+#define DDRSS1_PHY_1225_DATA 0x00000000
+#define DDRSS1_PHY_1226_DATA 0x00000000
+#define DDRSS1_PHY_1227_DATA 0x00000000
+#define DDRSS1_PHY_1228_DATA 0x00000000
+#define DDRSS1_PHY_1229_DATA 0x00000000
+#define DDRSS1_PHY_1230_DATA 0x00000000
+#define DDRSS1_PHY_1231_DATA 0x00000000
+#define DDRSS1_PHY_1232_DATA 0x00000000
+#define DDRSS1_PHY_1233_DATA 0x00000000
+#define DDRSS1_PHY_1234_DATA 0x00000000
+#define DDRSS1_PHY_1235_DATA 0x00000000
+#define DDRSS1_PHY_1236_DATA 0x00000000
+#define DDRSS1_PHY_1237_DATA 0x00000000
+#define DDRSS1_PHY_1238_DATA 0x00000000
+#define DDRSS1_PHY_1239_DATA 0x00000000
+#define DDRSS1_PHY_1240_DATA 0x00000000
+#define DDRSS1_PHY_1241_DATA 0x00000000
+#define DDRSS1_PHY_1242_DATA 0x00000000
+#define DDRSS1_PHY_1243_DATA 0x00000000
+#define DDRSS1_PHY_1244_DATA 0x00000000
+#define DDRSS1_PHY_1245_DATA 0x00000000
+#define DDRSS1_PHY_1246_DATA 0x00000000
+#define DDRSS1_PHY_1247_DATA 0x00000000
+#define DDRSS1_PHY_1248_DATA 0x00000000
+#define DDRSS1_PHY_1249_DATA 0x00000000
+#define DDRSS1_PHY_1250_DATA 0x00000000
+#define DDRSS1_PHY_1251_DATA 0x00000000
+#define DDRSS1_PHY_1252_DATA 0x00000000
+#define DDRSS1_PHY_1253_DATA 0x00000000
+#define DDRSS1_PHY_1254_DATA 0x00000000
+#define DDRSS1_PHY_1255_DATA 0x00000000
+#define DDRSS1_PHY_1256_DATA 0x00000000
+#define DDRSS1_PHY_1257_DATA 0x00000000
+#define DDRSS1_PHY_1258_DATA 0x00000000
+#define DDRSS1_PHY_1259_DATA 0x00000000
+#define DDRSS1_PHY_1260_DATA 0x00000000
+#define DDRSS1_PHY_1261_DATA 0x00000000
+#define DDRSS1_PHY_1262_DATA 0x00000000
+#define DDRSS1_PHY_1263_DATA 0x00000000
+#define DDRSS1_PHY_1264_DATA 0x00000000
+#define DDRSS1_PHY_1265_DATA 0x00000000
+#define DDRSS1_PHY_1266_DATA 0x00000000
+#define DDRSS1_PHY_1267_DATA 0x00000000
+#define DDRSS1_PHY_1268_DATA 0x00000000
+#define DDRSS1_PHY_1269_DATA 0x00000000
+#define DDRSS1_PHY_1270_DATA 0x00000000
+#define DDRSS1_PHY_1271_DATA 0x00000000
+#define DDRSS1_PHY_1272_DATA 0x00000000
+#define DDRSS1_PHY_1273_DATA 0x00000000
+#define DDRSS1_PHY_1274_DATA 0x00000000
+#define DDRSS1_PHY_1275_DATA 0x00000000
+#define DDRSS1_PHY_1276_DATA 0x00000000
+#define DDRSS1_PHY_1277_DATA 0x00000000
+#define DDRSS1_PHY_1278_DATA 0x00000000
+#define DDRSS1_PHY_1279_DATA 0x00000000
+#define DDRSS1_PHY_1280_DATA 0x00000000
+#define DDRSS1_PHY_1281_DATA 0x00010100
+#define DDRSS1_PHY_1282_DATA 0x00000000
+#define DDRSS1_PHY_1283_DATA 0x00000000
+#define DDRSS1_PHY_1284_DATA 0x00050000
+#define DDRSS1_PHY_1285_DATA 0x04000000
+#define DDRSS1_PHY_1286_DATA 0x00000055
+#define DDRSS1_PHY_1287_DATA 0x00000000
+#define DDRSS1_PHY_1288_DATA 0x00000000
+#define DDRSS1_PHY_1289_DATA 0x00000000
+#define DDRSS1_PHY_1290_DATA 0x00000000
+#define DDRSS1_PHY_1291_DATA 0x00002001
+#define DDRSS1_PHY_1292_DATA 0x0000400F
+#define DDRSS1_PHY_1293_DATA 0x50020028
+#define DDRSS1_PHY_1294_DATA 0x01010000
+#define DDRSS1_PHY_1295_DATA 0x80080001
+#define DDRSS1_PHY_1296_DATA 0x10200000
+#define DDRSS1_PHY_1297_DATA 0x00000008
+#define DDRSS1_PHY_1298_DATA 0x00000000
+#define DDRSS1_PHY_1299_DATA 0x01090E00
+#define DDRSS1_PHY_1300_DATA 0x00040101
+#define DDRSS1_PHY_1301_DATA 0x0000010F
+#define DDRSS1_PHY_1302_DATA 0x00000000
+#define DDRSS1_PHY_1303_DATA 0x0000FFFF
+#define DDRSS1_PHY_1304_DATA 0x00000000
+#define DDRSS1_PHY_1305_DATA 0x01010000
+#define DDRSS1_PHY_1306_DATA 0x01080402
+#define DDRSS1_PHY_1307_DATA 0x01200F02
+#define DDRSS1_PHY_1308_DATA 0x00194280
+#define DDRSS1_PHY_1309_DATA 0x00000004
+#define DDRSS1_PHY_1310_DATA 0x00042000
+#define DDRSS1_PHY_1311_DATA 0x00000000
+#define DDRSS1_PHY_1312_DATA 0x00000000
+#define DDRSS1_PHY_1313_DATA 0x00000000
+#define DDRSS1_PHY_1314_DATA 0x00000000
+#define DDRSS1_PHY_1315_DATA 0x00000000
+#define DDRSS1_PHY_1316_DATA 0x00000000
+#define DDRSS1_PHY_1317_DATA 0x01000000
+#define DDRSS1_PHY_1318_DATA 0x00000705
+#define DDRSS1_PHY_1319_DATA 0x00000054
+#define DDRSS1_PHY_1320_DATA 0x00030820
+#define DDRSS1_PHY_1321_DATA 0x00010820
+#define DDRSS1_PHY_1322_DATA 0x00010820
+#define DDRSS1_PHY_1323_DATA 0x00010820
+#define DDRSS1_PHY_1324_DATA 0x00010820
+#define DDRSS1_PHY_1325_DATA 0x00010820
+#define DDRSS1_PHY_1326_DATA 0x00010820
+#define DDRSS1_PHY_1327_DATA 0x00010820
+#define DDRSS1_PHY_1328_DATA 0x00010820
+#define DDRSS1_PHY_1329_DATA 0x00000000
+#define DDRSS1_PHY_1330_DATA 0x00000074
+#define DDRSS1_PHY_1331_DATA 0x00000400
+#define DDRSS1_PHY_1332_DATA 0x00000108
+#define DDRSS1_PHY_1333_DATA 0x00000000
+#define DDRSS1_PHY_1334_DATA 0x00000000
+#define DDRSS1_PHY_1335_DATA 0x00000000
+#define DDRSS1_PHY_1336_DATA 0x00000000
+#define DDRSS1_PHY_1337_DATA 0x00000000
+#define DDRSS1_PHY_1338_DATA 0x03000000
+#define DDRSS1_PHY_1339_DATA 0x00000000
+#define DDRSS1_PHY_1340_DATA 0x00000000
+#define DDRSS1_PHY_1341_DATA 0x00000000
+#define DDRSS1_PHY_1342_DATA 0x04102006
+#define DDRSS1_PHY_1343_DATA 0x00041020
+#define DDRSS1_PHY_1344_DATA 0x01C98C98
+#define DDRSS1_PHY_1345_DATA 0x3F400000
+#define DDRSS1_PHY_1346_DATA 0x3F3F1F3F
+#define DDRSS1_PHY_1347_DATA 0x0000001F
+#define DDRSS1_PHY_1348_DATA 0x00000000
+#define DDRSS1_PHY_1349_DATA 0x00000000
+#define DDRSS1_PHY_1350_DATA 0x00000000
+#define DDRSS1_PHY_1351_DATA 0x00010000
+#define DDRSS1_PHY_1352_DATA 0x00000000
+#define DDRSS1_PHY_1353_DATA 0x00000000
+#define DDRSS1_PHY_1354_DATA 0x00000000
+#define DDRSS1_PHY_1355_DATA 0x00000000
+#define DDRSS1_PHY_1356_DATA 0x76543210
+#define DDRSS1_PHY_1357_DATA 0x00010198
+#define DDRSS1_PHY_1358_DATA 0x00000000
+#define DDRSS1_PHY_1359_DATA 0x00000000
+#define DDRSS1_PHY_1360_DATA 0x00000000
+#define DDRSS1_PHY_1361_DATA 0x00040700
+#define DDRSS1_PHY_1362_DATA 0x00000000
+#define DDRSS1_PHY_1363_DATA 0x00000000
+#define DDRSS1_PHY_1364_DATA 0x00000000
+#define DDRSS1_PHY_1365_DATA 0x00000000
+#define DDRSS1_PHY_1366_DATA 0x00000000
+#define DDRSS1_PHY_1367_DATA 0x00000002
+#define DDRSS1_PHY_1368_DATA 0x00000000
+#define DDRSS1_PHY_1369_DATA 0x00000000
+#define DDRSS1_PHY_1370_DATA 0x00000000
+#define DDRSS1_PHY_1371_DATA 0x00000000
+#define DDRSS1_PHY_1372_DATA 0x00000000
+#define DDRSS1_PHY_1373_DATA 0x00000000
+#define DDRSS1_PHY_1374_DATA 0x00080000
+#define DDRSS1_PHY_1375_DATA 0x000007FF
+#define DDRSS1_PHY_1376_DATA 0x00000000
+#define DDRSS1_PHY_1377_DATA 0x00000000
+#define DDRSS1_PHY_1378_DATA 0x00000000
+#define DDRSS1_PHY_1379_DATA 0x00000000
+#define DDRSS1_PHY_1380_DATA 0x00000000
+#define DDRSS1_PHY_1381_DATA 0x00000000
+#define DDRSS1_PHY_1382_DATA 0x000FFFFF
+#define DDRSS1_PHY_1383_DATA 0x000FFFFF
+#define DDRSS1_PHY_1384_DATA 0x0000FFFF
+#define DDRSS1_PHY_1385_DATA 0xFFFFFFF0
+#define DDRSS1_PHY_1386_DATA 0x030FFFFF
+#define DDRSS1_PHY_1387_DATA 0x01FFFFFF
+#define DDRSS1_PHY_1388_DATA 0x0000FFFF
+#define DDRSS1_PHY_1389_DATA 0x00000000
+#define DDRSS1_PHY_1390_DATA 0x00000000
+#define DDRSS1_PHY_1391_DATA 0x00000000
+#define DDRSS1_PHY_1392_DATA 0x00000000
+#define DDRSS1_PHY_1393_DATA 0x0001F7C0
+#define DDRSS1_PHY_1394_DATA 0x00000003
+#define DDRSS1_PHY_1395_DATA 0x00000000
+#define DDRSS1_PHY_1396_DATA 0x00001142
+#define DDRSS1_PHY_1397_DATA 0x010207AB
+#define DDRSS1_PHY_1398_DATA 0x01000080
+#define DDRSS1_PHY_1399_DATA 0x03900390
+#define DDRSS1_PHY_1400_DATA 0x03900390
+#define DDRSS1_PHY_1401_DATA 0x00000390
+#define DDRSS1_PHY_1402_DATA 0x00000390
+#define DDRSS1_PHY_1403_DATA 0x00000390
+#define DDRSS1_PHY_1404_DATA 0x00000390
+#define DDRSS1_PHY_1405_DATA 0x00000005
+#define DDRSS1_PHY_1406_DATA 0x01813FCC
+#define DDRSS1_PHY_1407_DATA 0x000000CC
+#define DDRSS1_PHY_1408_DATA 0x0C000DFF
+#define DDRSS1_PHY_1409_DATA 0x30000DFF
+#define DDRSS1_PHY_1410_DATA 0x3F0DFF11
+#define DDRSS1_PHY_1411_DATA 0x000100F0
+#define DDRSS1_PHY_1412_DATA 0x780DFFCC
+#define DDRSS1_PHY_1413_DATA 0x00007E31
+#define DDRSS1_PHY_1414_DATA 0x000CBF11
+#define DDRSS1_PHY_1415_DATA 0x01990010
+#define DDRSS1_PHY_1416_DATA 0x000CBF11
+#define DDRSS1_PHY_1417_DATA 0x01990010
+#define DDRSS1_PHY_1418_DATA 0x3F0DFF11
+#define DDRSS1_PHY_1419_DATA 0x00EF00F0
+#define DDRSS1_PHY_1420_DATA 0x3F0DFF11
+#define DDRSS1_PHY_1421_DATA 0x01FF00F0
+#define DDRSS1_PHY_1422_DATA 0x20040006
+
+#define DDRSS2_CTL_00_DATA 0x00000B00
+#define DDRSS2_CTL_01_DATA 0x00000000
+#define DDRSS2_CTL_02_DATA 0x00000000
+#define DDRSS2_CTL_03_DATA 0x00000000
+#define DDRSS2_CTL_04_DATA 0x00000000
+#define DDRSS2_CTL_05_DATA 0x00000000
+#define DDRSS2_CTL_06_DATA 0x00000000
+#define DDRSS2_CTL_07_DATA 0x00002AF8
+#define DDRSS2_CTL_08_DATA 0x0001ADAF
+#define DDRSS2_CTL_09_DATA 0x00000005
+#define DDRSS2_CTL_10_DATA 0x0000006E
+#define DDRSS2_CTL_11_DATA 0x000681C8
+#define DDRSS2_CTL_12_DATA 0x004111C9
+#define DDRSS2_CTL_13_DATA 0x00000005
+#define DDRSS2_CTL_14_DATA 0x000010A9
+#define DDRSS2_CTL_15_DATA 0x000681C8
+#define DDRSS2_CTL_16_DATA 0x004111C9
+#define DDRSS2_CTL_17_DATA 0x00000005
+#define DDRSS2_CTL_18_DATA 0x000010A9
+#define DDRSS2_CTL_19_DATA 0x01010000
+#define DDRSS2_CTL_20_DATA 0x02011001
+#define DDRSS2_CTL_21_DATA 0x02010000
+#define DDRSS2_CTL_22_DATA 0x00020100
+#define DDRSS2_CTL_23_DATA 0x0000000B
+#define DDRSS2_CTL_24_DATA 0x0000001C
+#define DDRSS2_CTL_25_DATA 0x00000000
+#define DDRSS2_CTL_26_DATA 0x00000000
+#define DDRSS2_CTL_27_DATA 0x03020200
+#define DDRSS2_CTL_28_DATA 0x00005656
+#define DDRSS2_CTL_29_DATA 0x00100000
+#define DDRSS2_CTL_30_DATA 0x00000000
+#define DDRSS2_CTL_31_DATA 0x00000000
+#define DDRSS2_CTL_32_DATA 0x00000000
+#define DDRSS2_CTL_33_DATA 0x00000000
+#define DDRSS2_CTL_34_DATA 0x040C0000
+#define DDRSS2_CTL_35_DATA 0x12481248
+#define DDRSS2_CTL_36_DATA 0x00050804
+#define DDRSS2_CTL_37_DATA 0x09040008
+#define DDRSS2_CTL_38_DATA 0x15000204
+#define DDRSS2_CTL_39_DATA 0x1760008B
+#define DDRSS2_CTL_40_DATA 0x1500422B
+#define DDRSS2_CTL_41_DATA 0x1760008B
+#define DDRSS2_CTL_42_DATA 0x2000422B
+#define DDRSS2_CTL_43_DATA 0x000A0A09
+#define DDRSS2_CTL_44_DATA 0x0400078A
+#define DDRSS2_CTL_45_DATA 0x1E161104
+#define DDRSS2_CTL_46_DATA 0x10012458
+#define DDRSS2_CTL_47_DATA 0x1E161110
+#define DDRSS2_CTL_48_DATA 0x10012458
+#define DDRSS2_CTL_49_DATA 0x02030410
+#define DDRSS2_CTL_50_DATA 0x2C040500
+#define DDRSS2_CTL_51_DATA 0x08292C29
+#define DDRSS2_CTL_52_DATA 0x14000E0A
+#define DDRSS2_CTL_53_DATA 0x04010A0A
+#define DDRSS2_CTL_54_DATA 0x01010004
+#define DDRSS2_CTL_55_DATA 0x04545408
+#define DDRSS2_CTL_56_DATA 0x04313104
+#define DDRSS2_CTL_57_DATA 0x00003131
+#define DDRSS2_CTL_58_DATA 0x00010100
+#define DDRSS2_CTL_59_DATA 0x03010000
+#define DDRSS2_CTL_60_DATA 0x00001508
+#define DDRSS2_CTL_61_DATA 0x000000CE
+#define DDRSS2_CTL_62_DATA 0x0000032B
+#define DDRSS2_CTL_63_DATA 0x00002073
+#define DDRSS2_CTL_64_DATA 0x0000032B
+#define DDRSS2_CTL_65_DATA 0x00002073
+#define DDRSS2_CTL_66_DATA 0x00000005
+#define DDRSS2_CTL_67_DATA 0x00050000
+#define DDRSS2_CTL_68_DATA 0x00CB0012
+#define DDRSS2_CTL_69_DATA 0x00CB0408
+#define DDRSS2_CTL_70_DATA 0x00400408
+#define DDRSS2_CTL_71_DATA 0x00120103
+#define DDRSS2_CTL_72_DATA 0x00100005
+#define DDRSS2_CTL_73_DATA 0x2F080010
+#define DDRSS2_CTL_74_DATA 0x0505012F
+#define DDRSS2_CTL_75_DATA 0x0401030A
+#define DDRSS2_CTL_76_DATA 0x041E100B
+#define DDRSS2_CTL_77_DATA 0x100B0401
+#define DDRSS2_CTL_78_DATA 0x0001041E
+#define DDRSS2_CTL_79_DATA 0x00160016
+#define DDRSS2_CTL_80_DATA 0x033B033B
+#define DDRSS2_CTL_81_DATA 0x033B033B
+#define DDRSS2_CTL_82_DATA 0x03050505
+#define DDRSS2_CTL_83_DATA 0x03010303
+#define DDRSS2_CTL_84_DATA 0x200B100B
+#define DDRSS2_CTL_85_DATA 0x04041004
+#define DDRSS2_CTL_86_DATA 0x200B100B
+#define DDRSS2_CTL_87_DATA 0x04041004
+#define DDRSS2_CTL_88_DATA 0x03010000
+#define DDRSS2_CTL_89_DATA 0x00010000
+#define DDRSS2_CTL_90_DATA 0x00000000
+#define DDRSS2_CTL_91_DATA 0x00000000
+#define DDRSS2_CTL_92_DATA 0x01000000
+#define DDRSS2_CTL_93_DATA 0x80104002
+#define DDRSS2_CTL_94_DATA 0x00000000
+#define DDRSS2_CTL_95_DATA 0x00040005
+#define DDRSS2_CTL_96_DATA 0x00000000
+#define DDRSS2_CTL_97_DATA 0x00050000
+#define DDRSS2_CTL_98_DATA 0x00000004
+#define DDRSS2_CTL_99_DATA 0x00000000
+#define DDRSS2_CTL_100_DATA 0x00040005
+#define DDRSS2_CTL_101_DATA 0x00000000
+#define DDRSS2_CTL_102_DATA 0x00003380
+#define DDRSS2_CTL_103_DATA 0x00003380
+#define DDRSS2_CTL_104_DATA 0x00003380
+#define DDRSS2_CTL_105_DATA 0x00003380
+#define DDRSS2_CTL_106_DATA 0x00003380
+#define DDRSS2_CTL_107_DATA 0x00000000
+#define DDRSS2_CTL_108_DATA 0x000005A2
+#define DDRSS2_CTL_109_DATA 0x00081CC0
+#define DDRSS2_CTL_110_DATA 0x00081CC0
+#define DDRSS2_CTL_111_DATA 0x00081CC0
+#define DDRSS2_CTL_112_DATA 0x00081CC0
+#define DDRSS2_CTL_113_DATA 0x00081CC0
+#define DDRSS2_CTL_114_DATA 0x00000000
+#define DDRSS2_CTL_115_DATA 0x0000E325
+#define DDRSS2_CTL_116_DATA 0x00081CC0
+#define DDRSS2_CTL_117_DATA 0x00081CC0
+#define DDRSS2_CTL_118_DATA 0x00081CC0
+#define DDRSS2_CTL_119_DATA 0x00081CC0
+#define DDRSS2_CTL_120_DATA 0x00081CC0
+#define DDRSS2_CTL_121_DATA 0x00000000
+#define DDRSS2_CTL_122_DATA 0x0000E325
+#define DDRSS2_CTL_123_DATA 0x00000000
+#define DDRSS2_CTL_124_DATA 0x00000000
+#define DDRSS2_CTL_125_DATA 0x00000000
+#define DDRSS2_CTL_126_DATA 0x00000000
+#define DDRSS2_CTL_127_DATA 0x00000000
+#define DDRSS2_CTL_128_DATA 0x00000000
+#define DDRSS2_CTL_129_DATA 0x00000000
+#define DDRSS2_CTL_130_DATA 0x00000000
+#define DDRSS2_CTL_131_DATA 0x0B030500
+#define DDRSS2_CTL_132_DATA 0x00040B04
+#define DDRSS2_CTL_133_DATA 0x0A090000
+#define DDRSS2_CTL_134_DATA 0x0A090701
+#define DDRSS2_CTL_135_DATA 0x0900000E
+#define DDRSS2_CTL_136_DATA 0x0907010A
+#define DDRSS2_CTL_137_DATA 0x00000E0A
+#define DDRSS2_CTL_138_DATA 0x07010A09
+#define DDRSS2_CTL_139_DATA 0x000E0A09
+#define DDRSS2_CTL_140_DATA 0x07000401
+#define DDRSS2_CTL_141_DATA 0x00000000
+#define DDRSS2_CTL_142_DATA 0x00000000
+#define DDRSS2_CTL_143_DATA 0x00000000
+#define DDRSS2_CTL_144_DATA 0x00000000
+#define DDRSS2_CTL_145_DATA 0x00000000
+#define DDRSS2_CTL_146_DATA 0x00000000
+#define DDRSS2_CTL_147_DATA 0x00000000
+#define DDRSS2_CTL_148_DATA 0x08080000
+#define DDRSS2_CTL_149_DATA 0x01000000
+#define DDRSS2_CTL_150_DATA 0x800000C0
+#define DDRSS2_CTL_151_DATA 0x800000C0
+#define DDRSS2_CTL_152_DATA 0x800000C0
+#define DDRSS2_CTL_153_DATA 0x00000000
+#define DDRSS2_CTL_154_DATA 0x00001500
+#define DDRSS2_CTL_155_DATA 0x00000000
+#define DDRSS2_CTL_156_DATA 0x00000001
+#define DDRSS2_CTL_157_DATA 0x00000002
+#define DDRSS2_CTL_158_DATA 0x0000100E
+#define DDRSS2_CTL_159_DATA 0x00000000
+#define DDRSS2_CTL_160_DATA 0x00000000
+#define DDRSS2_CTL_161_DATA 0x00000000
+#define DDRSS2_CTL_162_DATA 0x00000000
+#define DDRSS2_CTL_163_DATA 0x00000000
+#define DDRSS2_CTL_164_DATA 0x000B0000
+#define DDRSS2_CTL_165_DATA 0x000E0006
+#define DDRSS2_CTL_166_DATA 0x000E0404
+#define DDRSS2_CTL_167_DATA 0x00D601AB
+#define DDRSS2_CTL_168_DATA 0x10100216
+#define DDRSS2_CTL_169_DATA 0x01AB0216
+#define DDRSS2_CTL_170_DATA 0x021600D6
+#define DDRSS2_CTL_171_DATA 0x02161010
+#define DDRSS2_CTL_172_DATA 0x00000000
+#define DDRSS2_CTL_173_DATA 0x00000000
+#define DDRSS2_CTL_174_DATA 0x00000000
+#define DDRSS2_CTL_175_DATA 0x3FF40084
+#define DDRSS2_CTL_176_DATA 0x33003FF4
+#define DDRSS2_CTL_177_DATA 0x00003333
+#define DDRSS2_CTL_178_DATA 0x35000000
+#define DDRSS2_CTL_179_DATA 0x27270035
+#define DDRSS2_CTL_180_DATA 0x0F0F0000
+#define DDRSS2_CTL_181_DATA 0x16000000
+#define DDRSS2_CTL_182_DATA 0x00841616
+#define DDRSS2_CTL_183_DATA 0x3FF43FF4
+#define DDRSS2_CTL_184_DATA 0x33333300
+#define DDRSS2_CTL_185_DATA 0x00000000
+#define DDRSS2_CTL_186_DATA 0x00353500
+#define DDRSS2_CTL_187_DATA 0x00002727
+#define DDRSS2_CTL_188_DATA 0x00000F0F
+#define DDRSS2_CTL_189_DATA 0x16161600
+#define DDRSS2_CTL_190_DATA 0x00000020
+#define DDRSS2_CTL_191_DATA 0x00000000
+#define DDRSS2_CTL_192_DATA 0x00000001
+#define DDRSS2_CTL_193_DATA 0x00000000
+#define DDRSS2_CTL_194_DATA 0x01000000
+#define DDRSS2_CTL_195_DATA 0x00000001
+#define DDRSS2_CTL_196_DATA 0x00000000
+#define DDRSS2_CTL_197_DATA 0x00000000
+#define DDRSS2_CTL_198_DATA 0x00000000
+#define DDRSS2_CTL_199_DATA 0x00000000
+#define DDRSS2_CTL_200_DATA 0x00000000
+#define DDRSS2_CTL_201_DATA 0x00000000
+#define DDRSS2_CTL_202_DATA 0x00000000
+#define DDRSS2_CTL_203_DATA 0x00000000
+#define DDRSS2_CTL_204_DATA 0x00000000
+#define DDRSS2_CTL_205_DATA 0x00000000
+#define DDRSS2_CTL_206_DATA 0x02000000
+#define DDRSS2_CTL_207_DATA 0x01080101
+#define DDRSS2_CTL_208_DATA 0x00000000
+#define DDRSS2_CTL_209_DATA 0x00000000
+#define DDRSS2_CTL_210_DATA 0x00000000
+#define DDRSS2_CTL_211_DATA 0x00000000
+#define DDRSS2_CTL_212_DATA 0x00000000
+#define DDRSS2_CTL_213_DATA 0x00000000
+#define DDRSS2_CTL_214_DATA 0x00000000
+#define DDRSS2_CTL_215_DATA 0x00000000
+#define DDRSS2_CTL_216_DATA 0x00000000
+#define DDRSS2_CTL_217_DATA 0x00000000
+#define DDRSS2_CTL_218_DATA 0x00000000
+#define DDRSS2_CTL_219_DATA 0x00000000
+#define DDRSS2_CTL_220_DATA 0x00000000
+#define DDRSS2_CTL_221_DATA 0x00000000
+#define DDRSS2_CTL_222_DATA 0x00001000
+#define DDRSS2_CTL_223_DATA 0x006403E8
+#define DDRSS2_CTL_224_DATA 0x00000000
+#define DDRSS2_CTL_225_DATA 0x00000000
+#define DDRSS2_CTL_226_DATA 0x00000000
+#define DDRSS2_CTL_227_DATA 0x15110000
+#define DDRSS2_CTL_228_DATA 0x00040C18
+#define DDRSS2_CTL_229_DATA 0xF000C000
+#define DDRSS2_CTL_230_DATA 0x0000F000
+#define DDRSS2_CTL_231_DATA 0x00000000
+#define DDRSS2_CTL_232_DATA 0x00000000
+#define DDRSS2_CTL_233_DATA 0xC0000000
+#define DDRSS2_CTL_234_DATA 0xF000F000
+#define DDRSS2_CTL_235_DATA 0x00000000
+#define DDRSS2_CTL_236_DATA 0x00000000
+#define DDRSS2_CTL_237_DATA 0x00000000
+#define DDRSS2_CTL_238_DATA 0xF000C000
+#define DDRSS2_CTL_239_DATA 0x0000F000
+#define DDRSS2_CTL_240_DATA 0x00000000
+#define DDRSS2_CTL_241_DATA 0x00000000
+#define DDRSS2_CTL_242_DATA 0x00030000
+#define DDRSS2_CTL_243_DATA 0x00000000
+#define DDRSS2_CTL_244_DATA 0x00000000
+#define DDRSS2_CTL_245_DATA 0x00000000
+#define DDRSS2_CTL_246_DATA 0x00000000
+#define DDRSS2_CTL_247_DATA 0x00000000
+#define DDRSS2_CTL_248_DATA 0x00000000
+#define DDRSS2_CTL_249_DATA 0x00000000
+#define DDRSS2_CTL_250_DATA 0x00000000
+#define DDRSS2_CTL_251_DATA 0x00000000
+#define DDRSS2_CTL_252_DATA 0x00000000
+#define DDRSS2_CTL_253_DATA 0x00000000
+#define DDRSS2_CTL_254_DATA 0x00000000
+#define DDRSS2_CTL_255_DATA 0x00000000
+#define DDRSS2_CTL_256_DATA 0x00000000
+#define DDRSS2_CTL_257_DATA 0x01000200
+#define DDRSS2_CTL_258_DATA 0x00370040
+#define DDRSS2_CTL_259_DATA 0x00020008
+#define DDRSS2_CTL_260_DATA 0x00400100
+#define DDRSS2_CTL_261_DATA 0x00400855
+#define DDRSS2_CTL_262_DATA 0x01000200
+#define DDRSS2_CTL_263_DATA 0x08550040
+#define DDRSS2_CTL_264_DATA 0x00000040
+#define DDRSS2_CTL_265_DATA 0x006B0003
+#define DDRSS2_CTL_266_DATA 0x0100006B
+#define DDRSS2_CTL_267_DATA 0x03030303
+#define DDRSS2_CTL_268_DATA 0x00000000
+#define DDRSS2_CTL_269_DATA 0x00000202
+#define DDRSS2_CTL_270_DATA 0x00001FFF
+#define DDRSS2_CTL_271_DATA 0x3FFF2000
+#define DDRSS2_CTL_272_DATA 0x03FF0000
+#define DDRSS2_CTL_273_DATA 0x000103FF
+#define DDRSS2_CTL_274_DATA 0x0FFF0B00
+#define DDRSS2_CTL_275_DATA 0x01010001
+#define DDRSS2_CTL_276_DATA 0x01010101
+#define DDRSS2_CTL_277_DATA 0x01180101
+#define DDRSS2_CTL_278_DATA 0x00030000
+#define DDRSS2_CTL_279_DATA 0x00000000
+#define DDRSS2_CTL_280_DATA 0x00000000
+#define DDRSS2_CTL_281_DATA 0x00000000
+#define DDRSS2_CTL_282_DATA 0x00000000
+#define DDRSS2_CTL_283_DATA 0x00000000
+#define DDRSS2_CTL_284_DATA 0x00000000
+#define DDRSS2_CTL_285_DATA 0x00000000
+#define DDRSS2_CTL_286_DATA 0x00040101
+#define DDRSS2_CTL_287_DATA 0x04010100
+#define DDRSS2_CTL_288_DATA 0x00000000
+#define DDRSS2_CTL_289_DATA 0x00000000
+#define DDRSS2_CTL_290_DATA 0x03030300
+#define DDRSS2_CTL_291_DATA 0x00000001
+#define DDRSS2_CTL_292_DATA 0x00000000
+#define DDRSS2_CTL_293_DATA 0x00000000
+#define DDRSS2_CTL_294_DATA 0x00000000
+#define DDRSS2_CTL_295_DATA 0x00000000
+#define DDRSS2_CTL_296_DATA 0x00000000
+#define DDRSS2_CTL_297_DATA 0x00000000
+#define DDRSS2_CTL_298_DATA 0x00000000
+#define DDRSS2_CTL_299_DATA 0x00000000
+#define DDRSS2_CTL_300_DATA 0x00000000
+#define DDRSS2_CTL_301_DATA 0x00000000
+#define DDRSS2_CTL_302_DATA 0x00000000
+#define DDRSS2_CTL_303_DATA 0x00000000
+#define DDRSS2_CTL_304_DATA 0x00000000
+#define DDRSS2_CTL_305_DATA 0x00000000
+#define DDRSS2_CTL_306_DATA 0x00000000
+#define DDRSS2_CTL_307_DATA 0x00000000
+#define DDRSS2_CTL_308_DATA 0x00000000
+#define DDRSS2_CTL_309_DATA 0x00000000
+#define DDRSS2_CTL_310_DATA 0x00000000
+#define DDRSS2_CTL_311_DATA 0x00000000
+#define DDRSS2_CTL_312_DATA 0x00000000
+#define DDRSS2_CTL_313_DATA 0x01000000
+#define DDRSS2_CTL_314_DATA 0x00020201
+#define DDRSS2_CTL_315_DATA 0x01000101
+#define DDRSS2_CTL_316_DATA 0x01010001
+#define DDRSS2_CTL_317_DATA 0x00010101
+#define DDRSS2_CTL_318_DATA 0x050A0A03
+#define DDRSS2_CTL_319_DATA 0x10081F1F
+#define DDRSS2_CTL_320_DATA 0x00090310
+#define DDRSS2_CTL_321_DATA 0x0B0C030F
+#define DDRSS2_CTL_322_DATA 0x0B0C0306
+#define DDRSS2_CTL_323_DATA 0x0C090006
+#define DDRSS2_CTL_324_DATA 0x0100000C
+#define DDRSS2_CTL_325_DATA 0x08040801
+#define DDRSS2_CTL_326_DATA 0x00000004
+#define DDRSS2_CTL_327_DATA 0x00000000
+#define DDRSS2_CTL_328_DATA 0x00010000
+#define DDRSS2_CTL_329_DATA 0x00280D00
+#define DDRSS2_CTL_330_DATA 0x00000001
+#define DDRSS2_CTL_331_DATA 0x00030001
+#define DDRSS2_CTL_332_DATA 0x00000000
+#define DDRSS2_CTL_333_DATA 0x00000000
+#define DDRSS2_CTL_334_DATA 0x00000000
+#define DDRSS2_CTL_335_DATA 0x00000000
+#define DDRSS2_CTL_336_DATA 0x00000000
+#define DDRSS2_CTL_337_DATA 0x00000000
+#define DDRSS2_CTL_338_DATA 0x00000000
+#define DDRSS2_CTL_339_DATA 0x00000000
+#define DDRSS2_CTL_340_DATA 0x01000000
+#define DDRSS2_CTL_341_DATA 0x00000001
+#define DDRSS2_CTL_342_DATA 0x00010100
+#define DDRSS2_CTL_343_DATA 0x03030000
+#define DDRSS2_CTL_344_DATA 0x00000000
+#define DDRSS2_CTL_345_DATA 0x00000000
+#define DDRSS2_CTL_346_DATA 0x00000000
+#define DDRSS2_CTL_347_DATA 0x00000000
+#define DDRSS2_CTL_348_DATA 0x00000000
+#define DDRSS2_CTL_349_DATA 0x00000000
+#define DDRSS2_CTL_350_DATA 0x00000000
+#define DDRSS2_CTL_351_DATA 0x00000000
+#define DDRSS2_CTL_352_DATA 0x00000000
+#define DDRSS2_CTL_353_DATA 0x00000000
+#define DDRSS2_CTL_354_DATA 0x00000000
+#define DDRSS2_CTL_355_DATA 0x00000000
+#define DDRSS2_CTL_356_DATA 0x00000000
+#define DDRSS2_CTL_357_DATA 0x00000000
+#define DDRSS2_CTL_358_DATA 0x00000000
+#define DDRSS2_CTL_359_DATA 0x00000000
+#define DDRSS2_CTL_360_DATA 0x000556AA
+#define DDRSS2_CTL_361_DATA 0x000AAAAA
+#define DDRSS2_CTL_362_DATA 0x000AA955
+#define DDRSS2_CTL_363_DATA 0x00055555
+#define DDRSS2_CTL_364_DATA 0x000B3133
+#define DDRSS2_CTL_365_DATA 0x0004CD33
+#define DDRSS2_CTL_366_DATA 0x0004CECC
+#define DDRSS2_CTL_367_DATA 0x000B32CC
+#define DDRSS2_CTL_368_DATA 0x00010300
+#define DDRSS2_CTL_369_DATA 0x03000100
+#define DDRSS2_CTL_370_DATA 0x00000000
+#define DDRSS2_CTL_371_DATA 0x00000000
+#define DDRSS2_CTL_372_DATA 0x00000000
+#define DDRSS2_CTL_373_DATA 0x00000000
+#define DDRSS2_CTL_374_DATA 0x00000000
+#define DDRSS2_CTL_375_DATA 0x00000000
+#define DDRSS2_CTL_376_DATA 0x00000000
+#define DDRSS2_CTL_377_DATA 0x00010000
+#define DDRSS2_CTL_378_DATA 0x00000404
+#define DDRSS2_CTL_379_DATA 0x00000000
+#define DDRSS2_CTL_380_DATA 0x00000000
+#define DDRSS2_CTL_381_DATA 0x00000000
+#define DDRSS2_CTL_382_DATA 0x00000000
+#define DDRSS2_CTL_383_DATA 0x00000000
+#define DDRSS2_CTL_384_DATA 0x00000000
+#define DDRSS2_CTL_385_DATA 0x00000000
+#define DDRSS2_CTL_386_DATA 0x00000000
+#define DDRSS2_CTL_387_DATA 0x3A3A1B00
+#define DDRSS2_CTL_388_DATA 0x000A0000
+#define DDRSS2_CTL_389_DATA 0x0000019C
+#define DDRSS2_CTL_390_DATA 0x00000200
+#define DDRSS2_CTL_391_DATA 0x00000200
+#define DDRSS2_CTL_392_DATA 0x00000200
+#define DDRSS2_CTL_393_DATA 0x00000200
+#define DDRSS2_CTL_394_DATA 0x000004D4
+#define DDRSS2_CTL_395_DATA 0x00001018
+#define DDRSS2_CTL_396_DATA 0x00000204
+#define DDRSS2_CTL_397_DATA 0x000040E6
+#define DDRSS2_CTL_398_DATA 0x00000200
+#define DDRSS2_CTL_399_DATA 0x00000200
+#define DDRSS2_CTL_400_DATA 0x00000200
+#define DDRSS2_CTL_401_DATA 0x00000200
+#define DDRSS2_CTL_402_DATA 0x0000C2B2
+#define DDRSS2_CTL_403_DATA 0x000288FC
+#define DDRSS2_CTL_404_DATA 0x00000E15
+#define DDRSS2_CTL_405_DATA 0x000040E6
+#define DDRSS2_CTL_406_DATA 0x00000200
+#define DDRSS2_CTL_407_DATA 0x00000200
+#define DDRSS2_CTL_408_DATA 0x00000200
+#define DDRSS2_CTL_409_DATA 0x00000200
+#define DDRSS2_CTL_410_DATA 0x0000C2B2
+#define DDRSS2_CTL_411_DATA 0x000288FC
+#define DDRSS2_CTL_412_DATA 0x02020E15
+#define DDRSS2_CTL_413_DATA 0x03030202
+#define DDRSS2_CTL_414_DATA 0x00000022
+#define DDRSS2_CTL_415_DATA 0x00000000
+#define DDRSS2_CTL_416_DATA 0x00000000
+#define DDRSS2_CTL_417_DATA 0x00001403
+#define DDRSS2_CTL_418_DATA 0x000007D0
+#define DDRSS2_CTL_419_DATA 0x00000000
+#define DDRSS2_CTL_420_DATA 0x00000000
+#define DDRSS2_CTL_421_DATA 0x00030000
+#define DDRSS2_CTL_422_DATA 0x0007001F
+#define DDRSS2_CTL_423_DATA 0x001B0033
+#define DDRSS2_CTL_424_DATA 0x001B0033
+#define DDRSS2_CTL_425_DATA 0x00000000
+#define DDRSS2_CTL_426_DATA 0x00000000
+#define DDRSS2_CTL_427_DATA 0x02000000
+#define DDRSS2_CTL_428_DATA 0x01000404
+#define DDRSS2_CTL_429_DATA 0x0B1E0B1E
+#define DDRSS2_CTL_430_DATA 0x00000105
+#define DDRSS2_CTL_431_DATA 0x00010101
+#define DDRSS2_CTL_432_DATA 0x00010101
+#define DDRSS2_CTL_433_DATA 0x00010001
+#define DDRSS2_CTL_434_DATA 0x00000101
+#define DDRSS2_CTL_435_DATA 0x02000201
+#define DDRSS2_CTL_436_DATA 0x02010000
+#define DDRSS2_CTL_437_DATA 0x00000200
+#define DDRSS2_CTL_438_DATA 0x28060000
+#define DDRSS2_CTL_439_DATA 0x00000128
+#define DDRSS2_CTL_440_DATA 0xFFFFFFFF
+#define DDRSS2_CTL_441_DATA 0xFFFFFFFF
+#define DDRSS2_CTL_442_DATA 0x00000000
+#define DDRSS2_CTL_443_DATA 0x00000000
+#define DDRSS2_CTL_444_DATA 0x00000000
+#define DDRSS2_CTL_445_DATA 0x00000000
+#define DDRSS2_CTL_446_DATA 0x00000000
+#define DDRSS2_CTL_447_DATA 0x00000000
+#define DDRSS2_CTL_448_DATA 0x00000000
+#define DDRSS2_CTL_449_DATA 0x00000000
+#define DDRSS2_CTL_450_DATA 0x00000000
+#define DDRSS2_CTL_451_DATA 0x00000000
+#define DDRSS2_CTL_452_DATA 0x00000000
+#define DDRSS2_CTL_453_DATA 0x00000000
+#define DDRSS2_CTL_454_DATA 0x00000000
+#define DDRSS2_CTL_455_DATA 0x00000000
+#define DDRSS2_CTL_456_DATA 0x00000000
+#define DDRSS2_CTL_457_DATA 0x00000000
+#define DDRSS2_CTL_458_DATA 0x00000000
+
+#define DDRSS2_PI_00_DATA 0x00000B00
+#define DDRSS2_PI_01_DATA 0x00000000
+#define DDRSS2_PI_02_DATA 0x00000000
+#define DDRSS2_PI_03_DATA 0x00000000
+#define DDRSS2_PI_04_DATA 0x00000000
+#define DDRSS2_PI_05_DATA 0x00000101
+#define DDRSS2_PI_06_DATA 0x00640000
+#define DDRSS2_PI_07_DATA 0x00000001
+#define DDRSS2_PI_08_DATA 0x00000000
+#define DDRSS2_PI_09_DATA 0x00000000
+#define DDRSS2_PI_10_DATA 0x00000000
+#define DDRSS2_PI_11_DATA 0x00000000
+#define DDRSS2_PI_12_DATA 0x00000007
+#define DDRSS2_PI_13_DATA 0x00010002
+#define DDRSS2_PI_14_DATA 0x0800000F
+#define DDRSS2_PI_15_DATA 0x00000103
+#define DDRSS2_PI_16_DATA 0x00000005
+#define DDRSS2_PI_17_DATA 0x00000000
+#define DDRSS2_PI_18_DATA 0x00000000
+#define DDRSS2_PI_19_DATA 0x00000000
+#define DDRSS2_PI_20_DATA 0x00000000
+#define DDRSS2_PI_21_DATA 0x00000000
+#define DDRSS2_PI_22_DATA 0x00000000
+#define DDRSS2_PI_23_DATA 0x00000000
+#define DDRSS2_PI_24_DATA 0x00000000
+#define DDRSS2_PI_25_DATA 0x00000000
+#define DDRSS2_PI_26_DATA 0x00010100
+#define DDRSS2_PI_27_DATA 0x00280A00
+#define DDRSS2_PI_28_DATA 0x00000000
+#define DDRSS2_PI_29_DATA 0x0F000000
+#define DDRSS2_PI_30_DATA 0x00003200
+#define DDRSS2_PI_31_DATA 0x00000000
+#define DDRSS2_PI_32_DATA 0x00000000
+#define DDRSS2_PI_33_DATA 0x01010102
+#define DDRSS2_PI_34_DATA 0x00000000
+#define DDRSS2_PI_35_DATA 0x000000AA
+#define DDRSS2_PI_36_DATA 0x00000055
+#define DDRSS2_PI_37_DATA 0x000000B5
+#define DDRSS2_PI_38_DATA 0x0000004A
+#define DDRSS2_PI_39_DATA 0x00000056
+#define DDRSS2_PI_40_DATA 0x000000A9
+#define DDRSS2_PI_41_DATA 0x000000A9
+#define DDRSS2_PI_42_DATA 0x000000B5
+#define DDRSS2_PI_43_DATA 0x00000000
+#define DDRSS2_PI_44_DATA 0x00000000
+#define DDRSS2_PI_45_DATA 0x000F0F00
+#define DDRSS2_PI_46_DATA 0x0000001B
+#define DDRSS2_PI_47_DATA 0x000007D0
+#define DDRSS2_PI_48_DATA 0x00000300
+#define DDRSS2_PI_49_DATA 0x00000000
+#define DDRSS2_PI_50_DATA 0x00000000
+#define DDRSS2_PI_51_DATA 0x01000000
+#define DDRSS2_PI_52_DATA 0x00010101
+#define DDRSS2_PI_53_DATA 0x00000000
+#define DDRSS2_PI_54_DATA 0x00030000
+#define DDRSS2_PI_55_DATA 0x0F000000
+#define DDRSS2_PI_56_DATA 0x00000017
+#define DDRSS2_PI_57_DATA 0x00000000
+#define DDRSS2_PI_58_DATA 0x00000000
+#define DDRSS2_PI_59_DATA 0x00000000
+#define DDRSS2_PI_60_DATA 0x0A0A140A
+#define DDRSS2_PI_61_DATA 0x10020101
+#define DDRSS2_PI_62_DATA 0x00020805
+#define DDRSS2_PI_63_DATA 0x01000404
+#define DDRSS2_PI_64_DATA 0x00000000
+#define DDRSS2_PI_65_DATA 0x00000000
+#define DDRSS2_PI_66_DATA 0x00000100
+#define DDRSS2_PI_67_DATA 0x0001010F
+#define DDRSS2_PI_68_DATA 0x00340000
+#define DDRSS2_PI_69_DATA 0x00000000
+#define DDRSS2_PI_70_DATA 0x00000000
+#define DDRSS2_PI_71_DATA 0x0000FFFF
+#define DDRSS2_PI_72_DATA 0x00000000
+#define DDRSS2_PI_73_DATA 0x00080000
+#define DDRSS2_PI_74_DATA 0x02000200
+#define DDRSS2_PI_75_DATA 0x01000100
+#define DDRSS2_PI_76_DATA 0x01000000
+#define DDRSS2_PI_77_DATA 0x02000200
+#define DDRSS2_PI_78_DATA 0x00000200
+#define DDRSS2_PI_79_DATA 0x00000000
+#define DDRSS2_PI_80_DATA 0x00000000
+#define DDRSS2_PI_81_DATA 0x00000000
+#define DDRSS2_PI_82_DATA 0x00000000
+#define DDRSS2_PI_83_DATA 0x00000000
+#define DDRSS2_PI_84_DATA 0x00000000
+#define DDRSS2_PI_85_DATA 0x00000000
+#define DDRSS2_PI_86_DATA 0x00000000
+#define DDRSS2_PI_87_DATA 0x00000000
+#define DDRSS2_PI_88_DATA 0x00000000
+#define DDRSS2_PI_89_DATA 0x00000000
+#define DDRSS2_PI_90_DATA 0x00000000
+#define DDRSS2_PI_91_DATA 0x00000400
+#define DDRSS2_PI_92_DATA 0x02010000
+#define DDRSS2_PI_93_DATA 0x00080003
+#define DDRSS2_PI_94_DATA 0x00080000
+#define DDRSS2_PI_95_DATA 0x00000001
+#define DDRSS2_PI_96_DATA 0x00000000
+#define DDRSS2_PI_97_DATA 0x0000AA00
+#define DDRSS2_PI_98_DATA 0x00000000
+#define DDRSS2_PI_99_DATA 0x00000000
+#define DDRSS2_PI_100_DATA 0x00010000
+#define DDRSS2_PI_101_DATA 0x00000000
+#define DDRSS2_PI_102_DATA 0x00000000
+#define DDRSS2_PI_103_DATA 0x00000000
+#define DDRSS2_PI_104_DATA 0x00000000
+#define DDRSS2_PI_105_DATA 0x00000000
+#define DDRSS2_PI_106_DATA 0x00000000
+#define DDRSS2_PI_107_DATA 0x00000000
+#define DDRSS2_PI_108_DATA 0x00000000
+#define DDRSS2_PI_109_DATA 0x00000000
+#define DDRSS2_PI_110_DATA 0x00000000
+#define DDRSS2_PI_111_DATA 0x00000000
+#define DDRSS2_PI_112_DATA 0x00000000
+#define DDRSS2_PI_113_DATA 0x00000000
+#define DDRSS2_PI_114_DATA 0x00000000
+#define DDRSS2_PI_115_DATA 0x00000000
+#define DDRSS2_PI_116_DATA 0x00000000
+#define DDRSS2_PI_117_DATA 0x00000000
+#define DDRSS2_PI_118_DATA 0x00000000
+#define DDRSS2_PI_119_DATA 0x00000000
+#define DDRSS2_PI_120_DATA 0x00000000
+#define DDRSS2_PI_121_DATA 0x00000000
+#define DDRSS2_PI_122_DATA 0x00000000
+#define DDRSS2_PI_123_DATA 0x00000000
+#define DDRSS2_PI_124_DATA 0x00000000
+#define DDRSS2_PI_125_DATA 0x00000008
+#define DDRSS2_PI_126_DATA 0x00000000
+#define DDRSS2_PI_127_DATA 0x00000000
+#define DDRSS2_PI_128_DATA 0x00000000
+#define DDRSS2_PI_129_DATA 0x00000000
+#define DDRSS2_PI_130_DATA 0x00000000
+#define DDRSS2_PI_131_DATA 0x00000000
+#define DDRSS2_PI_132_DATA 0x00000000
+#define DDRSS2_PI_133_DATA 0x00000000
+#define DDRSS2_PI_134_DATA 0x00000002
+#define DDRSS2_PI_135_DATA 0x00000000
+#define DDRSS2_PI_136_DATA 0x00000000
+#define DDRSS2_PI_137_DATA 0x0000000A
+#define DDRSS2_PI_138_DATA 0x00000019
+#define DDRSS2_PI_139_DATA 0x00000100
+#define DDRSS2_PI_140_DATA 0x00000000
+#define DDRSS2_PI_141_DATA 0x00000000
+#define DDRSS2_PI_142_DATA 0x00000000
+#define DDRSS2_PI_143_DATA 0x00000000
+#define DDRSS2_PI_144_DATA 0x01000000
+#define DDRSS2_PI_145_DATA 0x00010003
+#define DDRSS2_PI_146_DATA 0x02000101
+#define DDRSS2_PI_147_DATA 0x01030001
+#define DDRSS2_PI_148_DATA 0x00010400
+#define DDRSS2_PI_149_DATA 0x06000105
+#define DDRSS2_PI_150_DATA 0x01070001
+#define DDRSS2_PI_151_DATA 0x00000000
+#define DDRSS2_PI_152_DATA 0x00000000
+#define DDRSS2_PI_153_DATA 0x00000000
+#define DDRSS2_PI_154_DATA 0x00010001
+#define DDRSS2_PI_155_DATA 0x00000000
+#define DDRSS2_PI_156_DATA 0x00000000
+#define DDRSS2_PI_157_DATA 0x00000000
+#define DDRSS2_PI_158_DATA 0x00000000
+#define DDRSS2_PI_159_DATA 0x00000401
+#define DDRSS2_PI_160_DATA 0x00000000
+#define DDRSS2_PI_161_DATA 0x00010000
+#define DDRSS2_PI_162_DATA 0x00000000
+#define DDRSS2_PI_163_DATA 0x2B2B0200
+#define DDRSS2_PI_164_DATA 0x00000034
+#define DDRSS2_PI_165_DATA 0x00000064
+#define DDRSS2_PI_166_DATA 0x00020064
+#define DDRSS2_PI_167_DATA 0x02000200
+#define DDRSS2_PI_168_DATA 0x48120C04
+#define DDRSS2_PI_169_DATA 0x00154812
+#define DDRSS2_PI_170_DATA 0x000000CE
+#define DDRSS2_PI_171_DATA 0x0000032B
+#define DDRSS2_PI_172_DATA 0x00002073
+#define DDRSS2_PI_173_DATA 0x0000032B
+#define DDRSS2_PI_174_DATA 0x04002073
+#define DDRSS2_PI_175_DATA 0x01010404
+#define DDRSS2_PI_176_DATA 0x00001501
+#define DDRSS2_PI_177_DATA 0x00150015
+#define DDRSS2_PI_178_DATA 0x01000100
+#define DDRSS2_PI_179_DATA 0x00000100
+#define DDRSS2_PI_180_DATA 0x00000000
+#define DDRSS2_PI_181_DATA 0x01010101
+#define DDRSS2_PI_182_DATA 0x00000101
+#define DDRSS2_PI_183_DATA 0x00000000
+#define DDRSS2_PI_184_DATA 0x00000000
+#define DDRSS2_PI_185_DATA 0x15040000
+#define DDRSS2_PI_186_DATA 0x0E0E0215
+#define DDRSS2_PI_187_DATA 0x00040402
+#define DDRSS2_PI_188_DATA 0x000D0035
+#define DDRSS2_PI_189_DATA 0x00218049
+#define DDRSS2_PI_190_DATA 0x00218049
+#define DDRSS2_PI_191_DATA 0x01010101
+#define DDRSS2_PI_192_DATA 0x0004000E
+#define DDRSS2_PI_193_DATA 0x00040216
+#define DDRSS2_PI_194_DATA 0x01000216
+#define DDRSS2_PI_195_DATA 0x000F000F
+#define DDRSS2_PI_196_DATA 0x02170100
+#define DDRSS2_PI_197_DATA 0x01000217
+#define DDRSS2_PI_198_DATA 0x02170217
+#define DDRSS2_PI_199_DATA 0x32103200
+#define DDRSS2_PI_200_DATA 0x01013210
+#define DDRSS2_PI_201_DATA 0x0A070601
+#define DDRSS2_PI_202_DATA 0x1F130A0D
+#define DDRSS2_PI_203_DATA 0x1F130A14
+#define DDRSS2_PI_204_DATA 0x0000C014
+#define DDRSS2_PI_205_DATA 0x00C01000
+#define DDRSS2_PI_206_DATA 0x00C01000
+#define DDRSS2_PI_207_DATA 0x00021000
+#define DDRSS2_PI_208_DATA 0x0024000E
+#define DDRSS2_PI_209_DATA 0x00240216
+#define DDRSS2_PI_210_DATA 0x00110216
+#define DDRSS2_PI_211_DATA 0x32000056
+#define DDRSS2_PI_212_DATA 0x00000301
+#define DDRSS2_PI_213_DATA 0x005B0036
+#define DDRSS2_PI_214_DATA 0x03013212
+#define DDRSS2_PI_215_DATA 0x00003600
+#define DDRSS2_PI_216_DATA 0x3212005B
+#define DDRSS2_PI_217_DATA 0x09000301
+#define DDRSS2_PI_218_DATA 0x04010504
+#define DDRSS2_PI_219_DATA 0x040006C9
+#define DDRSS2_PI_220_DATA 0x0A032001
+#define DDRSS2_PI_221_DATA 0x2C31110A
+#define DDRSS2_PI_222_DATA 0x00002918
+#define DDRSS2_PI_223_DATA 0x6001071C
+#define DDRSS2_PI_224_DATA 0x1E202008
+#define DDRSS2_PI_225_DATA 0x2C311116
+#define DDRSS2_PI_226_DATA 0x00002918
+#define DDRSS2_PI_227_DATA 0x6001071C
+#define DDRSS2_PI_228_DATA 0x1E202008
+#define DDRSS2_PI_229_DATA 0x00019C16
+#define DDRSS2_PI_230_DATA 0x00001018
+#define DDRSS2_PI_231_DATA 0x000040E6
+#define DDRSS2_PI_232_DATA 0x000288FC
+#define DDRSS2_PI_233_DATA 0x000040E6
+#define DDRSS2_PI_234_DATA 0x000288FC
+#define DDRSS2_PI_235_DATA 0x033B0016
+#define DDRSS2_PI_236_DATA 0x0303033B
+#define DDRSS2_PI_237_DATA 0x002AF803
+#define DDRSS2_PI_238_DATA 0x0001ADAF
+#define DDRSS2_PI_239_DATA 0x00000005
+#define DDRSS2_PI_240_DATA 0x0000006E
+#define DDRSS2_PI_241_DATA 0x00000016
+#define DDRSS2_PI_242_DATA 0x000681C8
+#define DDRSS2_PI_243_DATA 0x0001ADAF
+#define DDRSS2_PI_244_DATA 0x00000005
+#define DDRSS2_PI_245_DATA 0x000010A9
+#define DDRSS2_PI_246_DATA 0x0000033B
+#define DDRSS2_PI_247_DATA 0x000681C8
+#define DDRSS2_PI_248_DATA 0x0001ADAF
+#define DDRSS2_PI_249_DATA 0x00000005
+#define DDRSS2_PI_250_DATA 0x000010A9
+#define DDRSS2_PI_251_DATA 0x0100033B
+#define DDRSS2_PI_252_DATA 0x00370040
+#define DDRSS2_PI_253_DATA 0x00010008
+#define DDRSS2_PI_254_DATA 0x08550040
+#define DDRSS2_PI_255_DATA 0x00010040
+#define DDRSS2_PI_256_DATA 0x08550040
+#define DDRSS2_PI_257_DATA 0x00000340
+#define DDRSS2_PI_258_DATA 0x006B006B
+#define DDRSS2_PI_259_DATA 0x08040404
+#define DDRSS2_PI_260_DATA 0x00000055
+#define DDRSS2_PI_261_DATA 0x55083C5A
+#define DDRSS2_PI_262_DATA 0x5A000000
+#define DDRSS2_PI_263_DATA 0x0055083C
+#define DDRSS2_PI_264_DATA 0x3C5A0000
+#define DDRSS2_PI_265_DATA 0x00005508
+#define DDRSS2_PI_266_DATA 0x0C3C5A00
+#define DDRSS2_PI_267_DATA 0x080F0E0D
+#define DDRSS2_PI_268_DATA 0x000B0A09
+#define DDRSS2_PI_269_DATA 0x00030201
+#define DDRSS2_PI_270_DATA 0x01000000
+#define DDRSS2_PI_271_DATA 0x04020201
+#define DDRSS2_PI_272_DATA 0x00080804
+#define DDRSS2_PI_273_DATA 0x00000000
+#define DDRSS2_PI_274_DATA 0x00000000
+#define DDRSS2_PI_275_DATA 0x00330084
+#define DDRSS2_PI_276_DATA 0x00160000
+#define DDRSS2_PI_277_DATA 0x35333FF4
+#define DDRSS2_PI_278_DATA 0x00160F27
+#define DDRSS2_PI_279_DATA 0x35333FF4
+#define DDRSS2_PI_280_DATA 0x00160F27
+#define DDRSS2_PI_281_DATA 0x00330084
+#define DDRSS2_PI_282_DATA 0x00160000
+#define DDRSS2_PI_283_DATA 0x35333FF4
+#define DDRSS2_PI_284_DATA 0x00160F27
+#define DDRSS2_PI_285_DATA 0x35333FF4
+#define DDRSS2_PI_286_DATA 0x00160F27
+#define DDRSS2_PI_287_DATA 0x00330084
+#define DDRSS2_PI_288_DATA 0x00160000
+#define DDRSS2_PI_289_DATA 0x35333FF4
+#define DDRSS2_PI_290_DATA 0x00160F27
+#define DDRSS2_PI_291_DATA 0x35333FF4
+#define DDRSS2_PI_292_DATA 0x00160F27
+#define DDRSS2_PI_293_DATA 0x00330084
+#define DDRSS2_PI_294_DATA 0x00160000
+#define DDRSS2_PI_295_DATA 0x35333FF4
+#define DDRSS2_PI_296_DATA 0x00160F27
+#define DDRSS2_PI_297_DATA 0x35333FF4
+#define DDRSS2_PI_298_DATA 0x00160F27
+#define DDRSS2_PI_299_DATA 0x00000000
+
+#define DDRSS2_PHY_00_DATA 0x000004F0
+#define DDRSS2_PHY_01_DATA 0x00000000
+#define DDRSS2_PHY_02_DATA 0x00030200
+#define DDRSS2_PHY_03_DATA 0x00000000
+#define DDRSS2_PHY_04_DATA 0x00000000
+#define DDRSS2_PHY_05_DATA 0x01030000
+#define DDRSS2_PHY_06_DATA 0x00010000
+#define DDRSS2_PHY_07_DATA 0x01030004
+#define DDRSS2_PHY_08_DATA 0x01000000
+#define DDRSS2_PHY_09_DATA 0x00000000
+#define DDRSS2_PHY_10_DATA 0x00000000
+#define DDRSS2_PHY_11_DATA 0x01000001
+#define DDRSS2_PHY_12_DATA 0x00000100
+#define DDRSS2_PHY_13_DATA 0x000800C0
+#define DDRSS2_PHY_14_DATA 0x060100CC
+#define DDRSS2_PHY_15_DATA 0x00030066
+#define DDRSS2_PHY_16_DATA 0x00000000
+#define DDRSS2_PHY_17_DATA 0x00000301
+#define DDRSS2_PHY_18_DATA 0x0000AAAA
+#define DDRSS2_PHY_19_DATA 0x00005555
+#define DDRSS2_PHY_20_DATA 0x0000B5B5
+#define DDRSS2_PHY_21_DATA 0x00004A4A
+#define DDRSS2_PHY_22_DATA 0x00005656
+#define DDRSS2_PHY_23_DATA 0x0000A9A9
+#define DDRSS2_PHY_24_DATA 0x0000A9A9
+#define DDRSS2_PHY_25_DATA 0x0000B5B5
+#define DDRSS2_PHY_26_DATA 0x00000000
+#define DDRSS2_PHY_27_DATA 0x00000000
+#define DDRSS2_PHY_28_DATA 0x2A000000
+#define DDRSS2_PHY_29_DATA 0x00000808
+#define DDRSS2_PHY_30_DATA 0x0F000000
+#define DDRSS2_PHY_31_DATA 0x00000F0F
+#define DDRSS2_PHY_32_DATA 0x10400000
+#define DDRSS2_PHY_33_DATA 0x0C002006
+#define DDRSS2_PHY_34_DATA 0x00000000
+#define DDRSS2_PHY_35_DATA 0x00000000
+#define DDRSS2_PHY_36_DATA 0x55555555
+#define DDRSS2_PHY_37_DATA 0xAAAAAAAA
+#define DDRSS2_PHY_38_DATA 0x55555555
+#define DDRSS2_PHY_39_DATA 0xAAAAAAAA
+#define DDRSS2_PHY_40_DATA 0x00005555
+#define DDRSS2_PHY_41_DATA 0x01000100
+#define DDRSS2_PHY_42_DATA 0x00800180
+#define DDRSS2_PHY_43_DATA 0x00000001
+#define DDRSS2_PHY_44_DATA 0x00000000
+#define DDRSS2_PHY_45_DATA 0x00000000
+#define DDRSS2_PHY_46_DATA 0x00000000
+#define DDRSS2_PHY_47_DATA 0x00000000
+#define DDRSS2_PHY_48_DATA 0x00000000
+#define DDRSS2_PHY_49_DATA 0x00000000
+#define DDRSS2_PHY_50_DATA 0x00000000
+#define DDRSS2_PHY_51_DATA 0x00000000
+#define DDRSS2_PHY_52_DATA 0x00000000
+#define DDRSS2_PHY_53_DATA 0x00000000
+#define DDRSS2_PHY_54_DATA 0x00000000
+#define DDRSS2_PHY_55_DATA 0x00000000
+#define DDRSS2_PHY_56_DATA 0x00000000
+#define DDRSS2_PHY_57_DATA 0x00000000
+#define DDRSS2_PHY_58_DATA 0x00000000
+#define DDRSS2_PHY_59_DATA 0x00000000
+#define DDRSS2_PHY_60_DATA 0x00000000
+#define DDRSS2_PHY_61_DATA 0x00000000
+#define DDRSS2_PHY_62_DATA 0x00000000
+#define DDRSS2_PHY_63_DATA 0x00000000
+#define DDRSS2_PHY_64_DATA 0x00000000
+#define DDRSS2_PHY_65_DATA 0x00000000
+#define DDRSS2_PHY_66_DATA 0x00000104
+#define DDRSS2_PHY_67_DATA 0x00000120
+#define DDRSS2_PHY_68_DATA 0x00000000
+#define DDRSS2_PHY_69_DATA 0x00000000
+#define DDRSS2_PHY_70_DATA 0x00000000
+#define DDRSS2_PHY_71_DATA 0x00000000
+#define DDRSS2_PHY_72_DATA 0x00000000
+#define DDRSS2_PHY_73_DATA 0x00000000
+#define DDRSS2_PHY_74_DATA 0x00000000
+#define DDRSS2_PHY_75_DATA 0x00000001
+#define DDRSS2_PHY_76_DATA 0x07FF0000
+#define DDRSS2_PHY_77_DATA 0x0080081F
+#define DDRSS2_PHY_78_DATA 0x00081020
+#define DDRSS2_PHY_79_DATA 0x04010000
+#define DDRSS2_PHY_80_DATA 0x00000000
+#define DDRSS2_PHY_81_DATA 0x00000000
+#define DDRSS2_PHY_82_DATA 0x00000000
+#define DDRSS2_PHY_83_DATA 0x00000100
+#define DDRSS2_PHY_84_DATA 0x01CC0C01
+#define DDRSS2_PHY_85_DATA 0x1003CC0C
+#define DDRSS2_PHY_86_DATA 0x20000140
+#define DDRSS2_PHY_87_DATA 0x07FF0200
+#define DDRSS2_PHY_88_DATA 0x0000DD01
+#define DDRSS2_PHY_89_DATA 0x10100303
+#define DDRSS2_PHY_90_DATA 0x10101010
+#define DDRSS2_PHY_91_DATA 0x10101010
+#define DDRSS2_PHY_92_DATA 0x00021010
+#define DDRSS2_PHY_93_DATA 0x00100010
+#define DDRSS2_PHY_94_DATA 0x00100010
+#define DDRSS2_PHY_95_DATA 0x00100010
+#define DDRSS2_PHY_96_DATA 0x00100010
+#define DDRSS2_PHY_97_DATA 0x00050010
+#define DDRSS2_PHY_98_DATA 0x51517041
+#define DDRSS2_PHY_99_DATA 0x31C06001
+#define DDRSS2_PHY_100_DATA 0x07AB0340
+#define DDRSS2_PHY_101_DATA 0x00C0C001
+#define DDRSS2_PHY_102_DATA 0x0E0D0001
+#define DDRSS2_PHY_103_DATA 0x10001000
+#define DDRSS2_PHY_104_DATA 0x0C083E42
+#define DDRSS2_PHY_105_DATA 0x0F0C3701
+#define DDRSS2_PHY_106_DATA 0x01000140
+#define DDRSS2_PHY_107_DATA 0x0C000420
+#define DDRSS2_PHY_108_DATA 0x00000198
+#define DDRSS2_PHY_109_DATA 0x0A0000D0
+#define DDRSS2_PHY_110_DATA 0x00030200
+#define DDRSS2_PHY_111_DATA 0x02800000
+#define DDRSS2_PHY_112_DATA 0x80800000
+#define DDRSS2_PHY_113_DATA 0x000E2010
+#define DDRSS2_PHY_114_DATA 0x76543210
+#define DDRSS2_PHY_115_DATA 0x00000008
+#define DDRSS2_PHY_116_DATA 0x02800280
+#define DDRSS2_PHY_117_DATA 0x02800280
+#define DDRSS2_PHY_118_DATA 0x02800280
+#define DDRSS2_PHY_119_DATA 0x02800280
+#define DDRSS2_PHY_120_DATA 0x00000280
+#define DDRSS2_PHY_121_DATA 0x0000A000
+#define DDRSS2_PHY_122_DATA 0x00A000A0
+#define DDRSS2_PHY_123_DATA 0x00A000A0
+#define DDRSS2_PHY_124_DATA 0x00A000A0
+#define DDRSS2_PHY_125_DATA 0x00A000A0
+#define DDRSS2_PHY_126_DATA 0x00A000A0
+#define DDRSS2_PHY_127_DATA 0x00A000A0
+#define DDRSS2_PHY_128_DATA 0x00A000A0
+#define DDRSS2_PHY_129_DATA 0x00A000A0
+#define DDRSS2_PHY_130_DATA 0x01C200A0
+#define DDRSS2_PHY_131_DATA 0x01A00005
+#define DDRSS2_PHY_132_DATA 0x00000000
+#define DDRSS2_PHY_133_DATA 0x00000000
+#define DDRSS2_PHY_134_DATA 0x00080200
+#define DDRSS2_PHY_135_DATA 0x00000000
+#define DDRSS2_PHY_136_DATA 0x20202000
+#define DDRSS2_PHY_137_DATA 0x20202020
+#define DDRSS2_PHY_138_DATA 0xF0F02020
+#define DDRSS2_PHY_139_DATA 0x00000000
+#define DDRSS2_PHY_140_DATA 0x00000000
+#define DDRSS2_PHY_141_DATA 0x00000000
+#define DDRSS2_PHY_142_DATA 0x00000000
+#define DDRSS2_PHY_143_DATA 0x00000000
+#define DDRSS2_PHY_144_DATA 0x00000000
+#define DDRSS2_PHY_145_DATA 0x00000000
+#define DDRSS2_PHY_146_DATA 0x00000000
+#define DDRSS2_PHY_147_DATA 0x00000000
+#define DDRSS2_PHY_148_DATA 0x00000000
+#define DDRSS2_PHY_149_DATA 0x00000000
+#define DDRSS2_PHY_150_DATA 0x00000000
+#define DDRSS2_PHY_151_DATA 0x00000000
+#define DDRSS2_PHY_152_DATA 0x00000000
+#define DDRSS2_PHY_153_DATA 0x00000000
+#define DDRSS2_PHY_154_DATA 0x00000000
+#define DDRSS2_PHY_155_DATA 0x00000000
+#define DDRSS2_PHY_156_DATA 0x00000000
+#define DDRSS2_PHY_157_DATA 0x00000000
+#define DDRSS2_PHY_158_DATA 0x00000000
+#define DDRSS2_PHY_159_DATA 0x00000000
+#define DDRSS2_PHY_160_DATA 0x00000000
+#define DDRSS2_PHY_161_DATA 0x00000000
+#define DDRSS2_PHY_162_DATA 0x00000000
+#define DDRSS2_PHY_163_DATA 0x00000000
+#define DDRSS2_PHY_164_DATA 0x00000000
+#define DDRSS2_PHY_165_DATA 0x00000000
+#define DDRSS2_PHY_166_DATA 0x00000000
+#define DDRSS2_PHY_167_DATA 0x00000000
+#define DDRSS2_PHY_168_DATA 0x00000000
+#define DDRSS2_PHY_169_DATA 0x00000000
+#define DDRSS2_PHY_170_DATA 0x00000000
+#define DDRSS2_PHY_171_DATA 0x00000000
+#define DDRSS2_PHY_172_DATA 0x00000000
+#define DDRSS2_PHY_173_DATA 0x00000000
+#define DDRSS2_PHY_174_DATA 0x00000000
+#define DDRSS2_PHY_175_DATA 0x00000000
+#define DDRSS2_PHY_176_DATA 0x00000000
+#define DDRSS2_PHY_177_DATA 0x00000000
+#define DDRSS2_PHY_178_DATA 0x00000000
+#define DDRSS2_PHY_179_DATA 0x00000000
+#define DDRSS2_PHY_180_DATA 0x00000000
+#define DDRSS2_PHY_181_DATA 0x00000000
+#define DDRSS2_PHY_182_DATA 0x00000000
+#define DDRSS2_PHY_183_DATA 0x00000000
+#define DDRSS2_PHY_184_DATA 0x00000000
+#define DDRSS2_PHY_185_DATA 0x00000000
+#define DDRSS2_PHY_186_DATA 0x00000000
+#define DDRSS2_PHY_187_DATA 0x00000000
+#define DDRSS2_PHY_188_DATA 0x00000000
+#define DDRSS2_PHY_189_DATA 0x00000000
+#define DDRSS2_PHY_190_DATA 0x00000000
+#define DDRSS2_PHY_191_DATA 0x00000000
+#define DDRSS2_PHY_192_DATA 0x00000000
+#define DDRSS2_PHY_193_DATA 0x00000000
+#define DDRSS2_PHY_194_DATA 0x00000000
+#define DDRSS2_PHY_195_DATA 0x00000000
+#define DDRSS2_PHY_196_DATA 0x00000000
+#define DDRSS2_PHY_197_DATA 0x00000000
+#define DDRSS2_PHY_198_DATA 0x00000000
+#define DDRSS2_PHY_199_DATA 0x00000000
+#define DDRSS2_PHY_200_DATA 0x00000000
+#define DDRSS2_PHY_201_DATA 0x00000000
+#define DDRSS2_PHY_202_DATA 0x00000000
+#define DDRSS2_PHY_203_DATA 0x00000000
+#define DDRSS2_PHY_204_DATA 0x00000000
+#define DDRSS2_PHY_205_DATA 0x00000000
+#define DDRSS2_PHY_206_DATA 0x00000000
+#define DDRSS2_PHY_207_DATA 0x00000000
+#define DDRSS2_PHY_208_DATA 0x00000000
+#define DDRSS2_PHY_209_DATA 0x00000000
+#define DDRSS2_PHY_210_DATA 0x00000000
+#define DDRSS2_PHY_211_DATA 0x00000000
+#define DDRSS2_PHY_212_DATA 0x00000000
+#define DDRSS2_PHY_213_DATA 0x00000000
+#define DDRSS2_PHY_214_DATA 0x00000000
+#define DDRSS2_PHY_215_DATA 0x00000000
+#define DDRSS2_PHY_216_DATA 0x00000000
+#define DDRSS2_PHY_217_DATA 0x00000000
+#define DDRSS2_PHY_218_DATA 0x00000000
+#define DDRSS2_PHY_219_DATA 0x00000000
+#define DDRSS2_PHY_220_DATA 0x00000000
+#define DDRSS2_PHY_221_DATA 0x00000000
+#define DDRSS2_PHY_222_DATA 0x00000000
+#define DDRSS2_PHY_223_DATA 0x00000000
+#define DDRSS2_PHY_224_DATA 0x00000000
+#define DDRSS2_PHY_225_DATA 0x00000000
+#define DDRSS2_PHY_226_DATA 0x00000000
+#define DDRSS2_PHY_227_DATA 0x00000000
+#define DDRSS2_PHY_228_DATA 0x00000000
+#define DDRSS2_PHY_229_DATA 0x00000000
+#define DDRSS2_PHY_230_DATA 0x00000000
+#define DDRSS2_PHY_231_DATA 0x00000000
+#define DDRSS2_PHY_232_DATA 0x00000000
+#define DDRSS2_PHY_233_DATA 0x00000000
+#define DDRSS2_PHY_234_DATA 0x00000000
+#define DDRSS2_PHY_235_DATA 0x00000000
+#define DDRSS2_PHY_236_DATA 0x00000000
+#define DDRSS2_PHY_237_DATA 0x00000000
+#define DDRSS2_PHY_238_DATA 0x00000000
+#define DDRSS2_PHY_239_DATA 0x00000000
+#define DDRSS2_PHY_240_DATA 0x00000000
+#define DDRSS2_PHY_241_DATA 0x00000000
+#define DDRSS2_PHY_242_DATA 0x00000000
+#define DDRSS2_PHY_243_DATA 0x00000000
+#define DDRSS2_PHY_244_DATA 0x00000000
+#define DDRSS2_PHY_245_DATA 0x00000000
+#define DDRSS2_PHY_246_DATA 0x00000000
+#define DDRSS2_PHY_247_DATA 0x00000000
+#define DDRSS2_PHY_248_DATA 0x00000000
+#define DDRSS2_PHY_249_DATA 0x00000000
+#define DDRSS2_PHY_250_DATA 0x00000000
+#define DDRSS2_PHY_251_DATA 0x00000000
+#define DDRSS2_PHY_252_DATA 0x00000000
+#define DDRSS2_PHY_253_DATA 0x00000000
+#define DDRSS2_PHY_254_DATA 0x00000000
+#define DDRSS2_PHY_255_DATA 0x00000000
+#define DDRSS2_PHY_256_DATA 0x000004F0
+#define DDRSS2_PHY_257_DATA 0x00000000
+#define DDRSS2_PHY_258_DATA 0x00030200
+#define DDRSS2_PHY_259_DATA 0x00000000
+#define DDRSS2_PHY_260_DATA 0x00000000
+#define DDRSS2_PHY_261_DATA 0x01030000
+#define DDRSS2_PHY_262_DATA 0x00010000
+#define DDRSS2_PHY_263_DATA 0x01030004
+#define DDRSS2_PHY_264_DATA 0x01000000
+#define DDRSS2_PHY_265_DATA 0x00000000
+#define DDRSS2_PHY_266_DATA 0x00000000
+#define DDRSS2_PHY_267_DATA 0x01000001
+#define DDRSS2_PHY_268_DATA 0x00000100
+#define DDRSS2_PHY_269_DATA 0x000800C0
+#define DDRSS2_PHY_270_DATA 0x060100CC
+#define DDRSS2_PHY_271_DATA 0x00030066
+#define DDRSS2_PHY_272_DATA 0x00000000
+#define DDRSS2_PHY_273_DATA 0x00000301
+#define DDRSS2_PHY_274_DATA 0x0000AAAA
+#define DDRSS2_PHY_275_DATA 0x00005555
+#define DDRSS2_PHY_276_DATA 0x0000B5B5
+#define DDRSS2_PHY_277_DATA 0x00004A4A
+#define DDRSS2_PHY_278_DATA 0x00005656
+#define DDRSS2_PHY_279_DATA 0x0000A9A9
+#define DDRSS2_PHY_280_DATA 0x0000A9A9
+#define DDRSS2_PHY_281_DATA 0x0000B5B5
+#define DDRSS2_PHY_282_DATA 0x00000000
+#define DDRSS2_PHY_283_DATA 0x00000000
+#define DDRSS2_PHY_284_DATA 0x2A000000
+#define DDRSS2_PHY_285_DATA 0x00000808
+#define DDRSS2_PHY_286_DATA 0x0F000000
+#define DDRSS2_PHY_287_DATA 0x00000F0F
+#define DDRSS2_PHY_288_DATA 0x10400000
+#define DDRSS2_PHY_289_DATA 0x0C002006
+#define DDRSS2_PHY_290_DATA 0x00000000
+#define DDRSS2_PHY_291_DATA 0x00000000
+#define DDRSS2_PHY_292_DATA 0x55555555
+#define DDRSS2_PHY_293_DATA 0xAAAAAAAA
+#define DDRSS2_PHY_294_DATA 0x55555555
+#define DDRSS2_PHY_295_DATA 0xAAAAAAAA
+#define DDRSS2_PHY_296_DATA 0x00005555
+#define DDRSS2_PHY_297_DATA 0x01000100
+#define DDRSS2_PHY_298_DATA 0x00800180
+#define DDRSS2_PHY_299_DATA 0x00000000
+#define DDRSS2_PHY_300_DATA 0x00000000
+#define DDRSS2_PHY_301_DATA 0x00000000
+#define DDRSS2_PHY_302_DATA 0x00000000
+#define DDRSS2_PHY_303_DATA 0x00000000
+#define DDRSS2_PHY_304_DATA 0x00000000
+#define DDRSS2_PHY_305_DATA 0x00000000
+#define DDRSS2_PHY_306_DATA 0x00000000
+#define DDRSS2_PHY_307_DATA 0x00000000
+#define DDRSS2_PHY_308_DATA 0x00000000
+#define DDRSS2_PHY_309_DATA 0x00000000
+#define DDRSS2_PHY_310_DATA 0x00000000
+#define DDRSS2_PHY_311_DATA 0x00000000
+#define DDRSS2_PHY_312_DATA 0x00000000
+#define DDRSS2_PHY_313_DATA 0x00000000
+#define DDRSS2_PHY_314_DATA 0x00000000
+#define DDRSS2_PHY_315_DATA 0x00000000
+#define DDRSS2_PHY_316_DATA 0x00000000
+#define DDRSS2_PHY_317_DATA 0x00000000
+#define DDRSS2_PHY_318_DATA 0x00000000
+#define DDRSS2_PHY_319_DATA 0x00000000
+#define DDRSS2_PHY_320_DATA 0x00000000
+#define DDRSS2_PHY_321_DATA 0x00000000
+#define DDRSS2_PHY_322_DATA 0x00000104
+#define DDRSS2_PHY_323_DATA 0x00000120
+#define DDRSS2_PHY_324_DATA 0x00000000
+#define DDRSS2_PHY_325_DATA 0x00000000
+#define DDRSS2_PHY_326_DATA 0x00000000
+#define DDRSS2_PHY_327_DATA 0x00000000
+#define DDRSS2_PHY_328_DATA 0x00000000
+#define DDRSS2_PHY_329_DATA 0x00000000
+#define DDRSS2_PHY_330_DATA 0x00000000
+#define DDRSS2_PHY_331_DATA 0x00000001
+#define DDRSS2_PHY_332_DATA 0x07FF0000
+#define DDRSS2_PHY_333_DATA 0x0080081F
+#define DDRSS2_PHY_334_DATA 0x00081020
+#define DDRSS2_PHY_335_DATA 0x04010000
+#define DDRSS2_PHY_336_DATA 0x00000000
+#define DDRSS2_PHY_337_DATA 0x00000000
+#define DDRSS2_PHY_338_DATA 0x00000000
+#define DDRSS2_PHY_339_DATA 0x00000100
+#define DDRSS2_PHY_340_DATA 0x01CC0C01
+#define DDRSS2_PHY_341_DATA 0x1003CC0C
+#define DDRSS2_PHY_342_DATA 0x20000140
+#define DDRSS2_PHY_343_DATA 0x07FF0200
+#define DDRSS2_PHY_344_DATA 0x0000DD01
+#define DDRSS2_PHY_345_DATA 0x10100303
+#define DDRSS2_PHY_346_DATA 0x10101010
+#define DDRSS2_PHY_347_DATA 0x10101010
+#define DDRSS2_PHY_348_DATA 0x00021010
+#define DDRSS2_PHY_349_DATA 0x00100010
+#define DDRSS2_PHY_350_DATA 0x00100010
+#define DDRSS2_PHY_351_DATA 0x00100010
+#define DDRSS2_PHY_352_DATA 0x00100010
+#define DDRSS2_PHY_353_DATA 0x00050010
+#define DDRSS2_PHY_354_DATA 0x51517041
+#define DDRSS2_PHY_355_DATA 0x31C06001
+#define DDRSS2_PHY_356_DATA 0x07AB0340
+#define DDRSS2_PHY_357_DATA 0x00C0C001
+#define DDRSS2_PHY_358_DATA 0x0E0D0001
+#define DDRSS2_PHY_359_DATA 0x10001000
+#define DDRSS2_PHY_360_DATA 0x0C083E42
+#define DDRSS2_PHY_361_DATA 0x0F0C3701
+#define DDRSS2_PHY_362_DATA 0x01000140
+#define DDRSS2_PHY_363_DATA 0x0C000420
+#define DDRSS2_PHY_364_DATA 0x00000198
+#define DDRSS2_PHY_365_DATA 0x0A0000D0
+#define DDRSS2_PHY_366_DATA 0x00030200
+#define DDRSS2_PHY_367_DATA 0x02800000
+#define DDRSS2_PHY_368_DATA 0x80800000
+#define DDRSS2_PHY_369_DATA 0x000E2010
+#define DDRSS2_PHY_370_DATA 0x76543210
+#define DDRSS2_PHY_371_DATA 0x00000008
+#define DDRSS2_PHY_372_DATA 0x02800280
+#define DDRSS2_PHY_373_DATA 0x02800280
+#define DDRSS2_PHY_374_DATA 0x02800280
+#define DDRSS2_PHY_375_DATA 0x02800280
+#define DDRSS2_PHY_376_DATA 0x00000280
+#define DDRSS2_PHY_377_DATA 0x0000A000
+#define DDRSS2_PHY_378_DATA 0x00A000A0
+#define DDRSS2_PHY_379_DATA 0x00A000A0
+#define DDRSS2_PHY_380_DATA 0x00A000A0
+#define DDRSS2_PHY_381_DATA 0x00A000A0
+#define DDRSS2_PHY_382_DATA 0x00A000A0
+#define DDRSS2_PHY_383_DATA 0x00A000A0
+#define DDRSS2_PHY_384_DATA 0x00A000A0
+#define DDRSS2_PHY_385_DATA 0x00A000A0
+#define DDRSS2_PHY_386_DATA 0x01C200A0
+#define DDRSS2_PHY_387_DATA 0x01A00005
+#define DDRSS2_PHY_388_DATA 0x00000000
+#define DDRSS2_PHY_389_DATA 0x00000000
+#define DDRSS2_PHY_390_DATA 0x00080200
+#define DDRSS2_PHY_391_DATA 0x00000000
+#define DDRSS2_PHY_392_DATA 0x20202000
+#define DDRSS2_PHY_393_DATA 0x20202020
+#define DDRSS2_PHY_394_DATA 0xF0F02020
+#define DDRSS2_PHY_395_DATA 0x00000000
+#define DDRSS2_PHY_396_DATA 0x00000000
+#define DDRSS2_PHY_397_DATA 0x00000000
+#define DDRSS2_PHY_398_DATA 0x00000000
+#define DDRSS2_PHY_399_DATA 0x00000000
+#define DDRSS2_PHY_400_DATA 0x00000000
+#define DDRSS2_PHY_401_DATA 0x00000000
+#define DDRSS2_PHY_402_DATA 0x00000000
+#define DDRSS2_PHY_403_DATA 0x00000000
+#define DDRSS2_PHY_404_DATA 0x00000000
+#define DDRSS2_PHY_405_DATA 0x00000000
+#define DDRSS2_PHY_406_DATA 0x00000000
+#define DDRSS2_PHY_407_DATA 0x00000000
+#define DDRSS2_PHY_408_DATA 0x00000000
+#define DDRSS2_PHY_409_DATA 0x00000000
+#define DDRSS2_PHY_410_DATA 0x00000000
+#define DDRSS2_PHY_411_DATA 0x00000000
+#define DDRSS2_PHY_412_DATA 0x00000000
+#define DDRSS2_PHY_413_DATA 0x00000000
+#define DDRSS2_PHY_414_DATA 0x00000000
+#define DDRSS2_PHY_415_DATA 0x00000000
+#define DDRSS2_PHY_416_DATA 0x00000000
+#define DDRSS2_PHY_417_DATA 0x00000000
+#define DDRSS2_PHY_418_DATA 0x00000000
+#define DDRSS2_PHY_419_DATA 0x00000000
+#define DDRSS2_PHY_420_DATA 0x00000000
+#define DDRSS2_PHY_421_DATA 0x00000000
+#define DDRSS2_PHY_422_DATA 0x00000000
+#define DDRSS2_PHY_423_DATA 0x00000000
+#define DDRSS2_PHY_424_DATA 0x00000000
+#define DDRSS2_PHY_425_DATA 0x00000000
+#define DDRSS2_PHY_426_DATA 0x00000000
+#define DDRSS2_PHY_427_DATA 0x00000000
+#define DDRSS2_PHY_428_DATA 0x00000000
+#define DDRSS2_PHY_429_DATA 0x00000000
+#define DDRSS2_PHY_430_DATA 0x00000000
+#define DDRSS2_PHY_431_DATA 0x00000000
+#define DDRSS2_PHY_432_DATA 0x00000000
+#define DDRSS2_PHY_433_DATA 0x00000000
+#define DDRSS2_PHY_434_DATA 0x00000000
+#define DDRSS2_PHY_435_DATA 0x00000000
+#define DDRSS2_PHY_436_DATA 0x00000000
+#define DDRSS2_PHY_437_DATA 0x00000000
+#define DDRSS2_PHY_438_DATA 0x00000000
+#define DDRSS2_PHY_439_DATA 0x00000000
+#define DDRSS2_PHY_440_DATA 0x00000000
+#define DDRSS2_PHY_441_DATA 0x00000000
+#define DDRSS2_PHY_442_DATA 0x00000000
+#define DDRSS2_PHY_443_DATA 0x00000000
+#define DDRSS2_PHY_444_DATA 0x00000000
+#define DDRSS2_PHY_445_DATA 0x00000000
+#define DDRSS2_PHY_446_DATA 0x00000000
+#define DDRSS2_PHY_447_DATA 0x00000000
+#define DDRSS2_PHY_448_DATA 0x00000000
+#define DDRSS2_PHY_449_DATA 0x00000000
+#define DDRSS2_PHY_450_DATA 0x00000000
+#define DDRSS2_PHY_451_DATA 0x00000000
+#define DDRSS2_PHY_452_DATA 0x00000000
+#define DDRSS2_PHY_453_DATA 0x00000000
+#define DDRSS2_PHY_454_DATA 0x00000000
+#define DDRSS2_PHY_455_DATA 0x00000000
+#define DDRSS2_PHY_456_DATA 0x00000000
+#define DDRSS2_PHY_457_DATA 0x00000000
+#define DDRSS2_PHY_458_DATA 0x00000000
+#define DDRSS2_PHY_459_DATA 0x00000000
+#define DDRSS2_PHY_460_DATA 0x00000000
+#define DDRSS2_PHY_461_DATA 0x00000000
+#define DDRSS2_PHY_462_DATA 0x00000000
+#define DDRSS2_PHY_463_DATA 0x00000000
+#define DDRSS2_PHY_464_DATA 0x00000000
+#define DDRSS2_PHY_465_DATA 0x00000000
+#define DDRSS2_PHY_466_DATA 0x00000000
+#define DDRSS2_PHY_467_DATA 0x00000000
+#define DDRSS2_PHY_468_DATA 0x00000000
+#define DDRSS2_PHY_469_DATA 0x00000000
+#define DDRSS2_PHY_470_DATA 0x00000000
+#define DDRSS2_PHY_471_DATA 0x00000000
+#define DDRSS2_PHY_472_DATA 0x00000000
+#define DDRSS2_PHY_473_DATA 0x00000000
+#define DDRSS2_PHY_474_DATA 0x00000000
+#define DDRSS2_PHY_475_DATA 0x00000000
+#define DDRSS2_PHY_476_DATA 0x00000000
+#define DDRSS2_PHY_477_DATA 0x00000000
+#define DDRSS2_PHY_478_DATA 0x00000000
+#define DDRSS2_PHY_479_DATA 0x00000000
+#define DDRSS2_PHY_480_DATA 0x00000000
+#define DDRSS2_PHY_481_DATA 0x00000000
+#define DDRSS2_PHY_482_DATA 0x00000000
+#define DDRSS2_PHY_483_DATA 0x00000000
+#define DDRSS2_PHY_484_DATA 0x00000000
+#define DDRSS2_PHY_485_DATA 0x00000000
+#define DDRSS2_PHY_486_DATA 0x00000000
+#define DDRSS2_PHY_487_DATA 0x00000000
+#define DDRSS2_PHY_488_DATA 0x00000000
+#define DDRSS2_PHY_489_DATA 0x00000000
+#define DDRSS2_PHY_490_DATA 0x00000000
+#define DDRSS2_PHY_491_DATA 0x00000000
+#define DDRSS2_PHY_492_DATA 0x00000000
+#define DDRSS2_PHY_493_DATA 0x00000000
+#define DDRSS2_PHY_494_DATA 0x00000000
+#define DDRSS2_PHY_495_DATA 0x00000000
+#define DDRSS2_PHY_496_DATA 0x00000000
+#define DDRSS2_PHY_497_DATA 0x00000000
+#define DDRSS2_PHY_498_DATA 0x00000000
+#define DDRSS2_PHY_499_DATA 0x00000000
+#define DDRSS2_PHY_500_DATA 0x00000000
+#define DDRSS2_PHY_501_DATA 0x00000000
+#define DDRSS2_PHY_502_DATA 0x00000000
+#define DDRSS2_PHY_503_DATA 0x00000000
+#define DDRSS2_PHY_504_DATA 0x00000000
+#define DDRSS2_PHY_505_DATA 0x00000000
+#define DDRSS2_PHY_506_DATA 0x00000000
+#define DDRSS2_PHY_507_DATA 0x00000000
+#define DDRSS2_PHY_508_DATA 0x00000000
+#define DDRSS2_PHY_509_DATA 0x00000000
+#define DDRSS2_PHY_510_DATA 0x00000000
+#define DDRSS2_PHY_511_DATA 0x00000000
+#define DDRSS2_PHY_512_DATA 0x000004F0
+#define DDRSS2_PHY_513_DATA 0x00000000
+#define DDRSS2_PHY_514_DATA 0x00030200
+#define DDRSS2_PHY_515_DATA 0x00000000
+#define DDRSS2_PHY_516_DATA 0x00000000
+#define DDRSS2_PHY_517_DATA 0x01030000
+#define DDRSS2_PHY_518_DATA 0x00010000
+#define DDRSS2_PHY_519_DATA 0x01030004
+#define DDRSS2_PHY_520_DATA 0x01000000
+#define DDRSS2_PHY_521_DATA 0x00000000
+#define DDRSS2_PHY_522_DATA 0x00000000
+#define DDRSS2_PHY_523_DATA 0x01000001
+#define DDRSS2_PHY_524_DATA 0x00000100
+#define DDRSS2_PHY_525_DATA 0x000800C0
+#define DDRSS2_PHY_526_DATA 0x060100CC
+#define DDRSS2_PHY_527_DATA 0x00030066
+#define DDRSS2_PHY_528_DATA 0x00000000
+#define DDRSS2_PHY_529_DATA 0x00000301
+#define DDRSS2_PHY_530_DATA 0x0000AAAA
+#define DDRSS2_PHY_531_DATA 0x00005555
+#define DDRSS2_PHY_532_DATA 0x0000B5B5
+#define DDRSS2_PHY_533_DATA 0x00004A4A
+#define DDRSS2_PHY_534_DATA 0x00005656
+#define DDRSS2_PHY_535_DATA 0x0000A9A9
+#define DDRSS2_PHY_536_DATA 0x0000A9A9
+#define DDRSS2_PHY_537_DATA 0x0000B5B5
+#define DDRSS2_PHY_538_DATA 0x00000000
+#define DDRSS2_PHY_539_DATA 0x00000000
+#define DDRSS2_PHY_540_DATA 0x2A000000
+#define DDRSS2_PHY_541_DATA 0x00000808
+#define DDRSS2_PHY_542_DATA 0x0F000000
+#define DDRSS2_PHY_543_DATA 0x00000F0F
+#define DDRSS2_PHY_544_DATA 0x10400000
+#define DDRSS2_PHY_545_DATA 0x0C002006
+#define DDRSS2_PHY_546_DATA 0x00000000
+#define DDRSS2_PHY_547_DATA 0x00000000
+#define DDRSS2_PHY_548_DATA 0x55555555
+#define DDRSS2_PHY_549_DATA 0xAAAAAAAA
+#define DDRSS2_PHY_550_DATA 0x55555555
+#define DDRSS2_PHY_551_DATA 0xAAAAAAAA
+#define DDRSS2_PHY_552_DATA 0x00005555
+#define DDRSS2_PHY_553_DATA 0x01000100
+#define DDRSS2_PHY_554_DATA 0x00800180
+#define DDRSS2_PHY_555_DATA 0x00000001
+#define DDRSS2_PHY_556_DATA 0x00000000
+#define DDRSS2_PHY_557_DATA 0x00000000
+#define DDRSS2_PHY_558_DATA 0x00000000
+#define DDRSS2_PHY_559_DATA 0x00000000
+#define DDRSS2_PHY_560_DATA 0x00000000
+#define DDRSS2_PHY_561_DATA 0x00000000
+#define DDRSS2_PHY_562_DATA 0x00000000
+#define DDRSS2_PHY_563_DATA 0x00000000
+#define DDRSS2_PHY_564_DATA 0x00000000
+#define DDRSS2_PHY_565_DATA 0x00000000
+#define DDRSS2_PHY_566_DATA 0x00000000
+#define DDRSS2_PHY_567_DATA 0x00000000
+#define DDRSS2_PHY_568_DATA 0x00000000
+#define DDRSS2_PHY_569_DATA 0x00000000
+#define DDRSS2_PHY_570_DATA 0x00000000
+#define DDRSS2_PHY_571_DATA 0x00000000
+#define DDRSS2_PHY_572_DATA 0x00000000
+#define DDRSS2_PHY_573_DATA 0x00000000
+#define DDRSS2_PHY_574_DATA 0x00000000
+#define DDRSS2_PHY_575_DATA 0x00000000
+#define DDRSS2_PHY_576_DATA 0x00000000
+#define DDRSS2_PHY_577_DATA 0x00000000
+#define DDRSS2_PHY_578_DATA 0x00000104
+#define DDRSS2_PHY_579_DATA 0x00000120
+#define DDRSS2_PHY_580_DATA 0x00000000
+#define DDRSS2_PHY_581_DATA 0x00000000
+#define DDRSS2_PHY_582_DATA 0x00000000
+#define DDRSS2_PHY_583_DATA 0x00000000
+#define DDRSS2_PHY_584_DATA 0x00000000
+#define DDRSS2_PHY_585_DATA 0x00000000
+#define DDRSS2_PHY_586_DATA 0x00000000
+#define DDRSS2_PHY_587_DATA 0x00000001
+#define DDRSS2_PHY_588_DATA 0x07FF0000
+#define DDRSS2_PHY_589_DATA 0x0080081F
+#define DDRSS2_PHY_590_DATA 0x00081020
+#define DDRSS2_PHY_591_DATA 0x04010000
+#define DDRSS2_PHY_592_DATA 0x00000000
+#define DDRSS2_PHY_593_DATA 0x00000000
+#define DDRSS2_PHY_594_DATA 0x00000000
+#define DDRSS2_PHY_595_DATA 0x00000100
+#define DDRSS2_PHY_596_DATA 0x01CC0C01
+#define DDRSS2_PHY_597_DATA 0x1003CC0C
+#define DDRSS2_PHY_598_DATA 0x20000140
+#define DDRSS2_PHY_599_DATA 0x07FF0200
+#define DDRSS2_PHY_600_DATA 0x0000DD01
+#define DDRSS2_PHY_601_DATA 0x10100303
+#define DDRSS2_PHY_602_DATA 0x10101010
+#define DDRSS2_PHY_603_DATA 0x10101010
+#define DDRSS2_PHY_604_DATA 0x00021010
+#define DDRSS2_PHY_605_DATA 0x00100010
+#define DDRSS2_PHY_606_DATA 0x00100010
+#define DDRSS2_PHY_607_DATA 0x00100010
+#define DDRSS2_PHY_608_DATA 0x00100010
+#define DDRSS2_PHY_609_DATA 0x00050010
+#define DDRSS2_PHY_610_DATA 0x51517041
+#define DDRSS2_PHY_611_DATA 0x31C06001
+#define DDRSS2_PHY_612_DATA 0x07AB0340
+#define DDRSS2_PHY_613_DATA 0x00C0C001
+#define DDRSS2_PHY_614_DATA 0x0E0D0001
+#define DDRSS2_PHY_615_DATA 0x10001000
+#define DDRSS2_PHY_616_DATA 0x0C083E42
+#define DDRSS2_PHY_617_DATA 0x0F0C3701
+#define DDRSS2_PHY_618_DATA 0x01000140
+#define DDRSS2_PHY_619_DATA 0x0C000420
+#define DDRSS2_PHY_620_DATA 0x00000198
+#define DDRSS2_PHY_621_DATA 0x0A0000D0
+#define DDRSS2_PHY_622_DATA 0x00030200
+#define DDRSS2_PHY_623_DATA 0x02800000
+#define DDRSS2_PHY_624_DATA 0x80800000
+#define DDRSS2_PHY_625_DATA 0x000E2010
+#define DDRSS2_PHY_626_DATA 0x76543210
+#define DDRSS2_PHY_627_DATA 0x00000008
+#define DDRSS2_PHY_628_DATA 0x02800280
+#define DDRSS2_PHY_629_DATA 0x02800280
+#define DDRSS2_PHY_630_DATA 0x02800280
+#define DDRSS2_PHY_631_DATA 0x02800280
+#define DDRSS2_PHY_632_DATA 0x00000280
+#define DDRSS2_PHY_633_DATA 0x0000A000
+#define DDRSS2_PHY_634_DATA 0x00A000A0
+#define DDRSS2_PHY_635_DATA 0x00A000A0
+#define DDRSS2_PHY_636_DATA 0x00A000A0
+#define DDRSS2_PHY_637_DATA 0x00A000A0
+#define DDRSS2_PHY_638_DATA 0x00A000A0
+#define DDRSS2_PHY_639_DATA 0x00A000A0
+#define DDRSS2_PHY_640_DATA 0x00A000A0
+#define DDRSS2_PHY_641_DATA 0x00A000A0
+#define DDRSS2_PHY_642_DATA 0x01C200A0
+#define DDRSS2_PHY_643_DATA 0x01A00005
+#define DDRSS2_PHY_644_DATA 0x00000000
+#define DDRSS2_PHY_645_DATA 0x00000000
+#define DDRSS2_PHY_646_DATA 0x00080200
+#define DDRSS2_PHY_647_DATA 0x00000000
+#define DDRSS2_PHY_648_DATA 0x20202000
+#define DDRSS2_PHY_649_DATA 0x20202020
+#define DDRSS2_PHY_650_DATA 0xF0F02020
+#define DDRSS2_PHY_651_DATA 0x00000000
+#define DDRSS2_PHY_652_DATA 0x00000000
+#define DDRSS2_PHY_653_DATA 0x00000000
+#define DDRSS2_PHY_654_DATA 0x00000000
+#define DDRSS2_PHY_655_DATA 0x00000000
+#define DDRSS2_PHY_656_DATA 0x00000000
+#define DDRSS2_PHY_657_DATA 0x00000000
+#define DDRSS2_PHY_658_DATA 0x00000000
+#define DDRSS2_PHY_659_DATA 0x00000000
+#define DDRSS2_PHY_660_DATA 0x00000000
+#define DDRSS2_PHY_661_DATA 0x00000000
+#define DDRSS2_PHY_662_DATA 0x00000000
+#define DDRSS2_PHY_663_DATA 0x00000000
+#define DDRSS2_PHY_664_DATA 0x00000000
+#define DDRSS2_PHY_665_DATA 0x00000000
+#define DDRSS2_PHY_666_DATA 0x00000000
+#define DDRSS2_PHY_667_DATA 0x00000000
+#define DDRSS2_PHY_668_DATA 0x00000000
+#define DDRSS2_PHY_669_DATA 0x00000000
+#define DDRSS2_PHY_670_DATA 0x00000000
+#define DDRSS2_PHY_671_DATA 0x00000000
+#define DDRSS2_PHY_672_DATA 0x00000000
+#define DDRSS2_PHY_673_DATA 0x00000000
+#define DDRSS2_PHY_674_DATA 0x00000000
+#define DDRSS2_PHY_675_DATA 0x00000000
+#define DDRSS2_PHY_676_DATA 0x00000000
+#define DDRSS2_PHY_677_DATA 0x00000000
+#define DDRSS2_PHY_678_DATA 0x00000000
+#define DDRSS2_PHY_679_DATA 0x00000000
+#define DDRSS2_PHY_680_DATA 0x00000000
+#define DDRSS2_PHY_681_DATA 0x00000000
+#define DDRSS2_PHY_682_DATA 0x00000000
+#define DDRSS2_PHY_683_DATA 0x00000000
+#define DDRSS2_PHY_684_DATA 0x00000000
+#define DDRSS2_PHY_685_DATA 0x00000000
+#define DDRSS2_PHY_686_DATA 0x00000000
+#define DDRSS2_PHY_687_DATA 0x00000000
+#define DDRSS2_PHY_688_DATA 0x00000000
+#define DDRSS2_PHY_689_DATA 0x00000000
+#define DDRSS2_PHY_690_DATA 0x00000000
+#define DDRSS2_PHY_691_DATA 0x00000000
+#define DDRSS2_PHY_692_DATA 0x00000000
+#define DDRSS2_PHY_693_DATA 0x00000000
+#define DDRSS2_PHY_694_DATA 0x00000000
+#define DDRSS2_PHY_695_DATA 0x00000000
+#define DDRSS2_PHY_696_DATA 0x00000000
+#define DDRSS2_PHY_697_DATA 0x00000000
+#define DDRSS2_PHY_698_DATA 0x00000000
+#define DDRSS2_PHY_699_DATA 0x00000000
+#define DDRSS2_PHY_700_DATA 0x00000000
+#define DDRSS2_PHY_701_DATA 0x00000000
+#define DDRSS2_PHY_702_DATA 0x00000000
+#define DDRSS2_PHY_703_DATA 0x00000000
+#define DDRSS2_PHY_704_DATA 0x00000000
+#define DDRSS2_PHY_705_DATA 0x00000000
+#define DDRSS2_PHY_706_DATA 0x00000000
+#define DDRSS2_PHY_707_DATA 0x00000000
+#define DDRSS2_PHY_708_DATA 0x00000000
+#define DDRSS2_PHY_709_DATA 0x00000000
+#define DDRSS2_PHY_710_DATA 0x00000000
+#define DDRSS2_PHY_711_DATA 0x00000000
+#define DDRSS2_PHY_712_DATA 0x00000000
+#define DDRSS2_PHY_713_DATA 0x00000000
+#define DDRSS2_PHY_714_DATA 0x00000000
+#define DDRSS2_PHY_715_DATA 0x00000000
+#define DDRSS2_PHY_716_DATA 0x00000000
+#define DDRSS2_PHY_717_DATA 0x00000000
+#define DDRSS2_PHY_718_DATA 0x00000000
+#define DDRSS2_PHY_719_DATA 0x00000000
+#define DDRSS2_PHY_720_DATA 0x00000000
+#define DDRSS2_PHY_721_DATA 0x00000000
+#define DDRSS2_PHY_722_DATA 0x00000000
+#define DDRSS2_PHY_723_DATA 0x00000000
+#define DDRSS2_PHY_724_DATA 0x00000000
+#define DDRSS2_PHY_725_DATA 0x00000000
+#define DDRSS2_PHY_726_DATA 0x00000000
+#define DDRSS2_PHY_727_DATA 0x00000000
+#define DDRSS2_PHY_728_DATA 0x00000000
+#define DDRSS2_PHY_729_DATA 0x00000000
+#define DDRSS2_PHY_730_DATA 0x00000000
+#define DDRSS2_PHY_731_DATA 0x00000000
+#define DDRSS2_PHY_732_DATA 0x00000000
+#define DDRSS2_PHY_733_DATA 0x00000000
+#define DDRSS2_PHY_734_DATA 0x00000000
+#define DDRSS2_PHY_735_DATA 0x00000000
+#define DDRSS2_PHY_736_DATA 0x00000000
+#define DDRSS2_PHY_737_DATA 0x00000000
+#define DDRSS2_PHY_738_DATA 0x00000000
+#define DDRSS2_PHY_739_DATA 0x00000000
+#define DDRSS2_PHY_740_DATA 0x00000000
+#define DDRSS2_PHY_741_DATA 0x00000000
+#define DDRSS2_PHY_742_DATA 0x00000000
+#define DDRSS2_PHY_743_DATA 0x00000000
+#define DDRSS2_PHY_744_DATA 0x00000000
+#define DDRSS2_PHY_745_DATA 0x00000000
+#define DDRSS2_PHY_746_DATA 0x00000000
+#define DDRSS2_PHY_747_DATA 0x00000000
+#define DDRSS2_PHY_748_DATA 0x00000000
+#define DDRSS2_PHY_749_DATA 0x00000000
+#define DDRSS2_PHY_750_DATA 0x00000000
+#define DDRSS2_PHY_751_DATA 0x00000000
+#define DDRSS2_PHY_752_DATA 0x00000000
+#define DDRSS2_PHY_753_DATA 0x00000000
+#define DDRSS2_PHY_754_DATA 0x00000000
+#define DDRSS2_PHY_755_DATA 0x00000000
+#define DDRSS2_PHY_756_DATA 0x00000000
+#define DDRSS2_PHY_757_DATA 0x00000000
+#define DDRSS2_PHY_758_DATA 0x00000000
+#define DDRSS2_PHY_759_DATA 0x00000000
+#define DDRSS2_PHY_760_DATA 0x00000000
+#define DDRSS2_PHY_761_DATA 0x00000000
+#define DDRSS2_PHY_762_DATA 0x00000000
+#define DDRSS2_PHY_763_DATA 0x00000000
+#define DDRSS2_PHY_764_DATA 0x00000000
+#define DDRSS2_PHY_765_DATA 0x00000000
+#define DDRSS2_PHY_766_DATA 0x00000000
+#define DDRSS2_PHY_767_DATA 0x00000000
+#define DDRSS2_PHY_768_DATA 0x000004F0
+#define DDRSS2_PHY_769_DATA 0x00000000
+#define DDRSS2_PHY_770_DATA 0x00030200
+#define DDRSS2_PHY_771_DATA 0x00000000
+#define DDRSS2_PHY_772_DATA 0x00000000
+#define DDRSS2_PHY_773_DATA 0x01030000
+#define DDRSS2_PHY_774_DATA 0x00010000
+#define DDRSS2_PHY_775_DATA 0x01030004
+#define DDRSS2_PHY_776_DATA 0x01000000
+#define DDRSS2_PHY_777_DATA 0x00000000
+#define DDRSS2_PHY_778_DATA 0x00000000
+#define DDRSS2_PHY_779_DATA 0x01000001
+#define DDRSS2_PHY_780_DATA 0x00000100
+#define DDRSS2_PHY_781_DATA 0x000800C0
+#define DDRSS2_PHY_782_DATA 0x060100CC
+#define DDRSS2_PHY_783_DATA 0x00030066
+#define DDRSS2_PHY_784_DATA 0x00000000
+#define DDRSS2_PHY_785_DATA 0x00000301
+#define DDRSS2_PHY_786_DATA 0x0000AAAA
+#define DDRSS2_PHY_787_DATA 0x00005555
+#define DDRSS2_PHY_788_DATA 0x0000B5B5
+#define DDRSS2_PHY_789_DATA 0x00004A4A
+#define DDRSS2_PHY_790_DATA 0x00005656
+#define DDRSS2_PHY_791_DATA 0x0000A9A9
+#define DDRSS2_PHY_792_DATA 0x0000A9A9
+#define DDRSS2_PHY_793_DATA 0x0000B5B5
+#define DDRSS2_PHY_794_DATA 0x00000000
+#define DDRSS2_PHY_795_DATA 0x00000000
+#define DDRSS2_PHY_796_DATA 0x2A000000
+#define DDRSS2_PHY_797_DATA 0x00000808
+#define DDRSS2_PHY_798_DATA 0x0F000000
+#define DDRSS2_PHY_799_DATA 0x00000F0F
+#define DDRSS2_PHY_800_DATA 0x10400000
+#define DDRSS2_PHY_801_DATA 0x0C002006
+#define DDRSS2_PHY_802_DATA 0x00000000
+#define DDRSS2_PHY_803_DATA 0x00000000
+#define DDRSS2_PHY_804_DATA 0x55555555
+#define DDRSS2_PHY_805_DATA 0xAAAAAAAA
+#define DDRSS2_PHY_806_DATA 0x55555555
+#define DDRSS2_PHY_807_DATA 0xAAAAAAAA
+#define DDRSS2_PHY_808_DATA 0x00005555
+#define DDRSS2_PHY_809_DATA 0x01000100
+#define DDRSS2_PHY_810_DATA 0x00800180
+#define DDRSS2_PHY_811_DATA 0x00000000
+#define DDRSS2_PHY_812_DATA 0x00000000
+#define DDRSS2_PHY_813_DATA 0x00000000
+#define DDRSS2_PHY_814_DATA 0x00000000
+#define DDRSS2_PHY_815_DATA 0x00000000
+#define DDRSS2_PHY_816_DATA 0x00000000
+#define DDRSS2_PHY_817_DATA 0x00000000
+#define DDRSS2_PHY_818_DATA 0x00000000
+#define DDRSS2_PHY_819_DATA 0x00000000
+#define DDRSS2_PHY_820_DATA 0x00000000
+#define DDRSS2_PHY_821_DATA 0x00000000
+#define DDRSS2_PHY_822_DATA 0x00000000
+#define DDRSS2_PHY_823_DATA 0x00000000
+#define DDRSS2_PHY_824_DATA 0x00000000
+#define DDRSS2_PHY_825_DATA 0x00000000
+#define DDRSS2_PHY_826_DATA 0x00000000
+#define DDRSS2_PHY_827_DATA 0x00000000
+#define DDRSS2_PHY_828_DATA 0x00000000
+#define DDRSS2_PHY_829_DATA 0x00000000
+#define DDRSS2_PHY_830_DATA 0x00000000
+#define DDRSS2_PHY_831_DATA 0x00000000
+#define DDRSS2_PHY_832_DATA 0x00000000
+#define DDRSS2_PHY_833_DATA 0x00000000
+#define DDRSS2_PHY_834_DATA 0x00000104
+#define DDRSS2_PHY_835_DATA 0x00000120
+#define DDRSS2_PHY_836_DATA 0x00000000
+#define DDRSS2_PHY_837_DATA 0x00000000
+#define DDRSS2_PHY_838_DATA 0x00000000
+#define DDRSS2_PHY_839_DATA 0x00000000
+#define DDRSS2_PHY_840_DATA 0x00000000
+#define DDRSS2_PHY_841_DATA 0x00000000
+#define DDRSS2_PHY_842_DATA 0x00000000
+#define DDRSS2_PHY_843_DATA 0x00000001
+#define DDRSS2_PHY_844_DATA 0x07FF0000
+#define DDRSS2_PHY_845_DATA 0x0080081F
+#define DDRSS2_PHY_846_DATA 0x00081020
+#define DDRSS2_PHY_847_DATA 0x04010000
+#define DDRSS2_PHY_848_DATA 0x00000000
+#define DDRSS2_PHY_849_DATA 0x00000000
+#define DDRSS2_PHY_850_DATA 0x00000000
+#define DDRSS2_PHY_851_DATA 0x00000100
+#define DDRSS2_PHY_852_DATA 0x01CC0C01
+#define DDRSS2_PHY_853_DATA 0x1003CC0C
+#define DDRSS2_PHY_854_DATA 0x20000140
+#define DDRSS2_PHY_855_DATA 0x07FF0200
+#define DDRSS2_PHY_856_DATA 0x0000DD01
+#define DDRSS2_PHY_857_DATA 0x10100303
+#define DDRSS2_PHY_858_DATA 0x10101010
+#define DDRSS2_PHY_859_DATA 0x10101010
+#define DDRSS2_PHY_860_DATA 0x00021010
+#define DDRSS2_PHY_861_DATA 0x00100010
+#define DDRSS2_PHY_862_DATA 0x00100010
+#define DDRSS2_PHY_863_DATA 0x00100010
+#define DDRSS2_PHY_864_DATA 0x00100010
+#define DDRSS2_PHY_865_DATA 0x00050010
+#define DDRSS2_PHY_866_DATA 0x51517041
+#define DDRSS2_PHY_867_DATA 0x31C06001
+#define DDRSS2_PHY_868_DATA 0x07AB0340
+#define DDRSS2_PHY_869_DATA 0x00C0C001
+#define DDRSS2_PHY_870_DATA 0x0E0D0001
+#define DDRSS2_PHY_871_DATA 0x10001000
+#define DDRSS2_PHY_872_DATA 0x0C083E42
+#define DDRSS2_PHY_873_DATA 0x0F0C3701
+#define DDRSS2_PHY_874_DATA 0x01000140
+#define DDRSS2_PHY_875_DATA 0x0C000420
+#define DDRSS2_PHY_876_DATA 0x00000198
+#define DDRSS2_PHY_877_DATA 0x0A0000D0
+#define DDRSS2_PHY_878_DATA 0x00030200
+#define DDRSS2_PHY_879_DATA 0x02800000
+#define DDRSS2_PHY_880_DATA 0x80800000
+#define DDRSS2_PHY_881_DATA 0x000E2010
+#define DDRSS2_PHY_882_DATA 0x76543210
+#define DDRSS2_PHY_883_DATA 0x00000008
+#define DDRSS2_PHY_884_DATA 0x02800280
+#define DDRSS2_PHY_885_DATA 0x02800280
+#define DDRSS2_PHY_886_DATA 0x02800280
+#define DDRSS2_PHY_887_DATA 0x02800280
+#define DDRSS2_PHY_888_DATA 0x00000280
+#define DDRSS2_PHY_889_DATA 0x0000A000
+#define DDRSS2_PHY_890_DATA 0x00A000A0
+#define DDRSS2_PHY_891_DATA 0x00A000A0
+#define DDRSS2_PHY_892_DATA 0x00A000A0
+#define DDRSS2_PHY_893_DATA 0x00A000A0
+#define DDRSS2_PHY_894_DATA 0x00A000A0
+#define DDRSS2_PHY_895_DATA 0x00A000A0
+#define DDRSS2_PHY_896_DATA 0x00A000A0
+#define DDRSS2_PHY_897_DATA 0x00A000A0
+#define DDRSS2_PHY_898_DATA 0x01C200A0
+#define DDRSS2_PHY_899_DATA 0x01A00005
+#define DDRSS2_PHY_900_DATA 0x00000000
+#define DDRSS2_PHY_901_DATA 0x00000000
+#define DDRSS2_PHY_902_DATA 0x00080200
+#define DDRSS2_PHY_903_DATA 0x00000000
+#define DDRSS2_PHY_904_DATA 0x20202000
+#define DDRSS2_PHY_905_DATA 0x20202020
+#define DDRSS2_PHY_906_DATA 0xF0F02020
+#define DDRSS2_PHY_907_DATA 0x00000000
+#define DDRSS2_PHY_908_DATA 0x00000000
+#define DDRSS2_PHY_909_DATA 0x00000000
+#define DDRSS2_PHY_910_DATA 0x00000000
+#define DDRSS2_PHY_911_DATA 0x00000000
+#define DDRSS2_PHY_912_DATA 0x00000000
+#define DDRSS2_PHY_913_DATA 0x00000000
+#define DDRSS2_PHY_914_DATA 0x00000000
+#define DDRSS2_PHY_915_DATA 0x00000000
+#define DDRSS2_PHY_916_DATA 0x00000000
+#define DDRSS2_PHY_917_DATA 0x00000000
+#define DDRSS2_PHY_918_DATA 0x00000000
+#define DDRSS2_PHY_919_DATA 0x00000000
+#define DDRSS2_PHY_920_DATA 0x00000000
+#define DDRSS2_PHY_921_DATA 0x00000000
+#define DDRSS2_PHY_922_DATA 0x00000000
+#define DDRSS2_PHY_923_DATA 0x00000000
+#define DDRSS2_PHY_924_DATA 0x00000000
+#define DDRSS2_PHY_925_DATA 0x00000000
+#define DDRSS2_PHY_926_DATA 0x00000000
+#define DDRSS2_PHY_927_DATA 0x00000000
+#define DDRSS2_PHY_928_DATA 0x00000000
+#define DDRSS2_PHY_929_DATA 0x00000000
+#define DDRSS2_PHY_930_DATA 0x00000000
+#define DDRSS2_PHY_931_DATA 0x00000000
+#define DDRSS2_PHY_932_DATA 0x00000000
+#define DDRSS2_PHY_933_DATA 0x00000000
+#define DDRSS2_PHY_934_DATA 0x00000000
+#define DDRSS2_PHY_935_DATA 0x00000000
+#define DDRSS2_PHY_936_DATA 0x00000000
+#define DDRSS2_PHY_937_DATA 0x00000000
+#define DDRSS2_PHY_938_DATA 0x00000000
+#define DDRSS2_PHY_939_DATA 0x00000000
+#define DDRSS2_PHY_940_DATA 0x00000000
+#define DDRSS2_PHY_941_DATA 0x00000000
+#define DDRSS2_PHY_942_DATA 0x00000000
+#define DDRSS2_PHY_943_DATA 0x00000000
+#define DDRSS2_PHY_944_DATA 0x00000000
+#define DDRSS2_PHY_945_DATA 0x00000000
+#define DDRSS2_PHY_946_DATA 0x00000000
+#define DDRSS2_PHY_947_DATA 0x00000000
+#define DDRSS2_PHY_948_DATA 0x00000000
+#define DDRSS2_PHY_949_DATA 0x00000000
+#define DDRSS2_PHY_950_DATA 0x00000000
+#define DDRSS2_PHY_951_DATA 0x00000000
+#define DDRSS2_PHY_952_DATA 0x00000000
+#define DDRSS2_PHY_953_DATA 0x00000000
+#define DDRSS2_PHY_954_DATA 0x00000000
+#define DDRSS2_PHY_955_DATA 0x00000000
+#define DDRSS2_PHY_956_DATA 0x00000000
+#define DDRSS2_PHY_957_DATA 0x00000000
+#define DDRSS2_PHY_958_DATA 0x00000000
+#define DDRSS2_PHY_959_DATA 0x00000000
+#define DDRSS2_PHY_960_DATA 0x00000000
+#define DDRSS2_PHY_961_DATA 0x00000000
+#define DDRSS2_PHY_962_DATA 0x00000000
+#define DDRSS2_PHY_963_DATA 0x00000000
+#define DDRSS2_PHY_964_DATA 0x00000000
+#define DDRSS2_PHY_965_DATA 0x00000000
+#define DDRSS2_PHY_966_DATA 0x00000000
+#define DDRSS2_PHY_967_DATA 0x00000000
+#define DDRSS2_PHY_968_DATA 0x00000000
+#define DDRSS2_PHY_969_DATA 0x00000000
+#define DDRSS2_PHY_970_DATA 0x00000000
+#define DDRSS2_PHY_971_DATA 0x00000000
+#define DDRSS2_PHY_972_DATA 0x00000000
+#define DDRSS2_PHY_973_DATA 0x00000000
+#define DDRSS2_PHY_974_DATA 0x00000000
+#define DDRSS2_PHY_975_DATA 0x00000000
+#define DDRSS2_PHY_976_DATA 0x00000000
+#define DDRSS2_PHY_977_DATA 0x00000000
+#define DDRSS2_PHY_978_DATA 0x00000000
+#define DDRSS2_PHY_979_DATA 0x00000000
+#define DDRSS2_PHY_980_DATA 0x00000000
+#define DDRSS2_PHY_981_DATA 0x00000000
+#define DDRSS2_PHY_982_DATA 0x00000000
+#define DDRSS2_PHY_983_DATA 0x00000000
+#define DDRSS2_PHY_984_DATA 0x00000000
+#define DDRSS2_PHY_985_DATA 0x00000000
+#define DDRSS2_PHY_986_DATA 0x00000000
+#define DDRSS2_PHY_987_DATA 0x00000000
+#define DDRSS2_PHY_988_DATA 0x00000000
+#define DDRSS2_PHY_989_DATA 0x00000000
+#define DDRSS2_PHY_990_DATA 0x00000000
+#define DDRSS2_PHY_991_DATA 0x00000000
+#define DDRSS2_PHY_992_DATA 0x00000000
+#define DDRSS2_PHY_993_DATA 0x00000000
+#define DDRSS2_PHY_994_DATA 0x00000000
+#define DDRSS2_PHY_995_DATA 0x00000000
+#define DDRSS2_PHY_996_DATA 0x00000000
+#define DDRSS2_PHY_997_DATA 0x00000000
+#define DDRSS2_PHY_998_DATA 0x00000000
+#define DDRSS2_PHY_999_DATA 0x00000000
+#define DDRSS2_PHY_1000_DATA 0x00000000
+#define DDRSS2_PHY_1001_DATA 0x00000000
+#define DDRSS2_PHY_1002_DATA 0x00000000
+#define DDRSS2_PHY_1003_DATA 0x00000000
+#define DDRSS2_PHY_1004_DATA 0x00000000
+#define DDRSS2_PHY_1005_DATA 0x00000000
+#define DDRSS2_PHY_1006_DATA 0x00000000
+#define DDRSS2_PHY_1007_DATA 0x00000000
+#define DDRSS2_PHY_1008_DATA 0x00000000
+#define DDRSS2_PHY_1009_DATA 0x00000000
+#define DDRSS2_PHY_1010_DATA 0x00000000
+#define DDRSS2_PHY_1011_DATA 0x00000000
+#define DDRSS2_PHY_1012_DATA 0x00000000
+#define DDRSS2_PHY_1013_DATA 0x00000000
+#define DDRSS2_PHY_1014_DATA 0x00000000
+#define DDRSS2_PHY_1015_DATA 0x00000000
+#define DDRSS2_PHY_1016_DATA 0x00000000
+#define DDRSS2_PHY_1017_DATA 0x00000000
+#define DDRSS2_PHY_1018_DATA 0x00000000
+#define DDRSS2_PHY_1019_DATA 0x00000000
+#define DDRSS2_PHY_1020_DATA 0x00000000
+#define DDRSS2_PHY_1021_DATA 0x00000000
+#define DDRSS2_PHY_1022_DATA 0x00000000
+#define DDRSS2_PHY_1023_DATA 0x00000000
+#define DDRSS2_PHY_1024_DATA 0x00000000
+#define DDRSS2_PHY_1025_DATA 0x00000000
+#define DDRSS2_PHY_1026_DATA 0x00000000
+#define DDRSS2_PHY_1027_DATA 0x00000000
+#define DDRSS2_PHY_1028_DATA 0x00000000
+#define DDRSS2_PHY_1029_DATA 0x00000100
+#define DDRSS2_PHY_1030_DATA 0x00000200
+#define DDRSS2_PHY_1031_DATA 0x00000000
+#define DDRSS2_PHY_1032_DATA 0x00000000
+#define DDRSS2_PHY_1033_DATA 0x00000000
+#define DDRSS2_PHY_1034_DATA 0x00000000
+#define DDRSS2_PHY_1035_DATA 0x00400000
+#define DDRSS2_PHY_1036_DATA 0x00000080
+#define DDRSS2_PHY_1037_DATA 0x00DCBA98
+#define DDRSS2_PHY_1038_DATA 0x03000000
+#define DDRSS2_PHY_1039_DATA 0x00200000
+#define DDRSS2_PHY_1040_DATA 0x00000000
+#define DDRSS2_PHY_1041_DATA 0x00000000
+#define DDRSS2_PHY_1042_DATA 0x00000000
+#define DDRSS2_PHY_1043_DATA 0x00000000
+#define DDRSS2_PHY_1044_DATA 0x00000000
+#define DDRSS2_PHY_1045_DATA 0x0000002A
+#define DDRSS2_PHY_1046_DATA 0x00000015
+#define DDRSS2_PHY_1047_DATA 0x00000015
+#define DDRSS2_PHY_1048_DATA 0x0000002A
+#define DDRSS2_PHY_1049_DATA 0x00000033
+#define DDRSS2_PHY_1050_DATA 0x0000000C
+#define DDRSS2_PHY_1051_DATA 0x0000000C
+#define DDRSS2_PHY_1052_DATA 0x00000033
+#define DDRSS2_PHY_1053_DATA 0x00543210
+#define DDRSS2_PHY_1054_DATA 0x003F0000
+#define DDRSS2_PHY_1055_DATA 0x000F013F
+#define DDRSS2_PHY_1056_DATA 0x20202003
+#define DDRSS2_PHY_1057_DATA 0x00202020
+#define DDRSS2_PHY_1058_DATA 0x20008008
+#define DDRSS2_PHY_1059_DATA 0x00000810
+#define DDRSS2_PHY_1060_DATA 0x00000F00
+#define DDRSS2_PHY_1061_DATA 0x00000000
+#define DDRSS2_PHY_1062_DATA 0x00000000
+#define DDRSS2_PHY_1063_DATA 0x00000000
+#define DDRSS2_PHY_1064_DATA 0x000305CC
+#define DDRSS2_PHY_1065_DATA 0x00030000
+#define DDRSS2_PHY_1066_DATA 0x00000300
+#define DDRSS2_PHY_1067_DATA 0x00000300
+#define DDRSS2_PHY_1068_DATA 0x00000300
+#define DDRSS2_PHY_1069_DATA 0x00000300
+#define DDRSS2_PHY_1070_DATA 0x00000300
+#define DDRSS2_PHY_1071_DATA 0x42080010
+#define DDRSS2_PHY_1072_DATA 0x0000803E
+#define DDRSS2_PHY_1073_DATA 0x00000001
+#define DDRSS2_PHY_1074_DATA 0x01000102
+#define DDRSS2_PHY_1075_DATA 0x00008000
+#define DDRSS2_PHY_1076_DATA 0x00000000
+#define DDRSS2_PHY_1077_DATA 0x00000000
+#define DDRSS2_PHY_1078_DATA 0x00000000
+#define DDRSS2_PHY_1079_DATA 0x00000000
+#define DDRSS2_PHY_1080_DATA 0x00000000
+#define DDRSS2_PHY_1081_DATA 0x00000000
+#define DDRSS2_PHY_1082_DATA 0x00000000
+#define DDRSS2_PHY_1083_DATA 0x00000000
+#define DDRSS2_PHY_1084_DATA 0x00000000
+#define DDRSS2_PHY_1085_DATA 0x00000000
+#define DDRSS2_PHY_1086_DATA 0x00000000
+#define DDRSS2_PHY_1087_DATA 0x00000000
+#define DDRSS2_PHY_1088_DATA 0x00000000
+#define DDRSS2_PHY_1089_DATA 0x00000000
+#define DDRSS2_PHY_1090_DATA 0x00000000
+#define DDRSS2_PHY_1091_DATA 0x00000000
+#define DDRSS2_PHY_1092_DATA 0x00000000
+#define DDRSS2_PHY_1093_DATA 0x00000000
+#define DDRSS2_PHY_1094_DATA 0x00000000
+#define DDRSS2_PHY_1095_DATA 0x00000000
+#define DDRSS2_PHY_1096_DATA 0x00000000
+#define DDRSS2_PHY_1097_DATA 0x00000000
+#define DDRSS2_PHY_1098_DATA 0x00000000
+#define DDRSS2_PHY_1099_DATA 0x00000000
+#define DDRSS2_PHY_1100_DATA 0x00000000
+#define DDRSS2_PHY_1101_DATA 0x00000000
+#define DDRSS2_PHY_1102_DATA 0x00000000
+#define DDRSS2_PHY_1103_DATA 0x00000000
+#define DDRSS2_PHY_1104_DATA 0x00000000
+#define DDRSS2_PHY_1105_DATA 0x00000000
+#define DDRSS2_PHY_1106_DATA 0x00000000
+#define DDRSS2_PHY_1107_DATA 0x00000000
+#define DDRSS2_PHY_1108_DATA 0x00000000
+#define DDRSS2_PHY_1109_DATA 0x00000000
+#define DDRSS2_PHY_1110_DATA 0x00000000
+#define DDRSS2_PHY_1111_DATA 0x00000000
+#define DDRSS2_PHY_1112_DATA 0x00000000
+#define DDRSS2_PHY_1113_DATA 0x00000000
+#define DDRSS2_PHY_1114_DATA 0x00000000
+#define DDRSS2_PHY_1115_DATA 0x00000000
+#define DDRSS2_PHY_1116_DATA 0x00000000
+#define DDRSS2_PHY_1117_DATA 0x00000000
+#define DDRSS2_PHY_1118_DATA 0x00000000
+#define DDRSS2_PHY_1119_DATA 0x00000000
+#define DDRSS2_PHY_1120_DATA 0x00000000
+#define DDRSS2_PHY_1121_DATA 0x00000000
+#define DDRSS2_PHY_1122_DATA 0x00000000
+#define DDRSS2_PHY_1123_DATA 0x00000000
+#define DDRSS2_PHY_1124_DATA 0x00000000
+#define DDRSS2_PHY_1125_DATA 0x00000000
+#define DDRSS2_PHY_1126_DATA 0x00000000
+#define DDRSS2_PHY_1127_DATA 0x00000000
+#define DDRSS2_PHY_1128_DATA 0x00000000
+#define DDRSS2_PHY_1129_DATA 0x00000000
+#define DDRSS2_PHY_1130_DATA 0x00000000
+#define DDRSS2_PHY_1131_DATA 0x00000000
+#define DDRSS2_PHY_1132_DATA 0x00000000
+#define DDRSS2_PHY_1133_DATA 0x00000000
+#define DDRSS2_PHY_1134_DATA 0x00000000
+#define DDRSS2_PHY_1135_DATA 0x00000000
+#define DDRSS2_PHY_1136_DATA 0x00000000
+#define DDRSS2_PHY_1137_DATA 0x00000000
+#define DDRSS2_PHY_1138_DATA 0x00000000
+#define DDRSS2_PHY_1139_DATA 0x00000000
+#define DDRSS2_PHY_1140_DATA 0x00000000
+#define DDRSS2_PHY_1141_DATA 0x00000000
+#define DDRSS2_PHY_1142_DATA 0x00000000
+#define DDRSS2_PHY_1143_DATA 0x00000000
+#define DDRSS2_PHY_1144_DATA 0x00000000
+#define DDRSS2_PHY_1145_DATA 0x00000000
+#define DDRSS2_PHY_1146_DATA 0x00000000
+#define DDRSS2_PHY_1147_DATA 0x00000000
+#define DDRSS2_PHY_1148_DATA 0x00000000
+#define DDRSS2_PHY_1149_DATA 0x00000000
+#define DDRSS2_PHY_1150_DATA 0x00000000
+#define DDRSS2_PHY_1151_DATA 0x00000000
+#define DDRSS2_PHY_1152_DATA 0x00000000
+#define DDRSS2_PHY_1153_DATA 0x00000000
+#define DDRSS2_PHY_1154_DATA 0x00000000
+#define DDRSS2_PHY_1155_DATA 0x00000000
+#define DDRSS2_PHY_1156_DATA 0x00000000
+#define DDRSS2_PHY_1157_DATA 0x00000000
+#define DDRSS2_PHY_1158_DATA 0x00000000
+#define DDRSS2_PHY_1159_DATA 0x00000000
+#define DDRSS2_PHY_1160_DATA 0x00000000
+#define DDRSS2_PHY_1161_DATA 0x00000000
+#define DDRSS2_PHY_1162_DATA 0x00000000
+#define DDRSS2_PHY_1163_DATA 0x00000000
+#define DDRSS2_PHY_1164_DATA 0x00000000
+#define DDRSS2_PHY_1165_DATA 0x00000000
+#define DDRSS2_PHY_1166_DATA 0x00000000
+#define DDRSS2_PHY_1167_DATA 0x00000000
+#define DDRSS2_PHY_1168_DATA 0x00000000
+#define DDRSS2_PHY_1169_DATA 0x00000000
+#define DDRSS2_PHY_1170_DATA 0x00000000
+#define DDRSS2_PHY_1171_DATA 0x00000000
+#define DDRSS2_PHY_1172_DATA 0x00000000
+#define DDRSS2_PHY_1173_DATA 0x00000000
+#define DDRSS2_PHY_1174_DATA 0x00000000
+#define DDRSS2_PHY_1175_DATA 0x00000000
+#define DDRSS2_PHY_1176_DATA 0x00000000
+#define DDRSS2_PHY_1177_DATA 0x00000000
+#define DDRSS2_PHY_1178_DATA 0x00000000
+#define DDRSS2_PHY_1179_DATA 0x00000000
+#define DDRSS2_PHY_1180_DATA 0x00000000
+#define DDRSS2_PHY_1181_DATA 0x00000000
+#define DDRSS2_PHY_1182_DATA 0x00000000
+#define DDRSS2_PHY_1183_DATA 0x00000000
+#define DDRSS2_PHY_1184_DATA 0x00000000
+#define DDRSS2_PHY_1185_DATA 0x00000000
+#define DDRSS2_PHY_1186_DATA 0x00000000
+#define DDRSS2_PHY_1187_DATA 0x00000000
+#define DDRSS2_PHY_1188_DATA 0x00000000
+#define DDRSS2_PHY_1189_DATA 0x00000000
+#define DDRSS2_PHY_1190_DATA 0x00000000
+#define DDRSS2_PHY_1191_DATA 0x00000000
+#define DDRSS2_PHY_1192_DATA 0x00000000
+#define DDRSS2_PHY_1193_DATA 0x00000000
+#define DDRSS2_PHY_1194_DATA 0x00000000
+#define DDRSS2_PHY_1195_DATA 0x00000000
+#define DDRSS2_PHY_1196_DATA 0x00000000
+#define DDRSS2_PHY_1197_DATA 0x00000000
+#define DDRSS2_PHY_1198_DATA 0x00000000
+#define DDRSS2_PHY_1199_DATA 0x00000000
+#define DDRSS2_PHY_1200_DATA 0x00000000
+#define DDRSS2_PHY_1201_DATA 0x00000000
+#define DDRSS2_PHY_1202_DATA 0x00000000
+#define DDRSS2_PHY_1203_DATA 0x00000000
+#define DDRSS2_PHY_1204_DATA 0x00000000
+#define DDRSS2_PHY_1205_DATA 0x00000000
+#define DDRSS2_PHY_1206_DATA 0x00000000
+#define DDRSS2_PHY_1207_DATA 0x00000000
+#define DDRSS2_PHY_1208_DATA 0x00000000
+#define DDRSS2_PHY_1209_DATA 0x00000000
+#define DDRSS2_PHY_1210_DATA 0x00000000
+#define DDRSS2_PHY_1211_DATA 0x00000000
+#define DDRSS2_PHY_1212_DATA 0x00000000
+#define DDRSS2_PHY_1213_DATA 0x00000000
+#define DDRSS2_PHY_1214_DATA 0x00000000
+#define DDRSS2_PHY_1215_DATA 0x00000000
+#define DDRSS2_PHY_1216_DATA 0x00000000
+#define DDRSS2_PHY_1217_DATA 0x00000000
+#define DDRSS2_PHY_1218_DATA 0x00000000
+#define DDRSS2_PHY_1219_DATA 0x00000000
+#define DDRSS2_PHY_1220_DATA 0x00000000
+#define DDRSS2_PHY_1221_DATA 0x00000000
+#define DDRSS2_PHY_1222_DATA 0x00000000
+#define DDRSS2_PHY_1223_DATA 0x00000000
+#define DDRSS2_PHY_1224_DATA 0x00000000
+#define DDRSS2_PHY_1225_DATA 0x00000000
+#define DDRSS2_PHY_1226_DATA 0x00000000
+#define DDRSS2_PHY_1227_DATA 0x00000000
+#define DDRSS2_PHY_1228_DATA 0x00000000
+#define DDRSS2_PHY_1229_DATA 0x00000000
+#define DDRSS2_PHY_1230_DATA 0x00000000
+#define DDRSS2_PHY_1231_DATA 0x00000000
+#define DDRSS2_PHY_1232_DATA 0x00000000
+#define DDRSS2_PHY_1233_DATA 0x00000000
+#define DDRSS2_PHY_1234_DATA 0x00000000
+#define DDRSS2_PHY_1235_DATA 0x00000000
+#define DDRSS2_PHY_1236_DATA 0x00000000
+#define DDRSS2_PHY_1237_DATA 0x00000000
+#define DDRSS2_PHY_1238_DATA 0x00000000
+#define DDRSS2_PHY_1239_DATA 0x00000000
+#define DDRSS2_PHY_1240_DATA 0x00000000
+#define DDRSS2_PHY_1241_DATA 0x00000000
+#define DDRSS2_PHY_1242_DATA 0x00000000
+#define DDRSS2_PHY_1243_DATA 0x00000000
+#define DDRSS2_PHY_1244_DATA 0x00000000
+#define DDRSS2_PHY_1245_DATA 0x00000000
+#define DDRSS2_PHY_1246_DATA 0x00000000
+#define DDRSS2_PHY_1247_DATA 0x00000000
+#define DDRSS2_PHY_1248_DATA 0x00000000
+#define DDRSS2_PHY_1249_DATA 0x00000000
+#define DDRSS2_PHY_1250_DATA 0x00000000
+#define DDRSS2_PHY_1251_DATA 0x00000000
+#define DDRSS2_PHY_1252_DATA 0x00000000
+#define DDRSS2_PHY_1253_DATA 0x00000000
+#define DDRSS2_PHY_1254_DATA 0x00000000
+#define DDRSS2_PHY_1255_DATA 0x00000000
+#define DDRSS2_PHY_1256_DATA 0x00000000
+#define DDRSS2_PHY_1257_DATA 0x00000000
+#define DDRSS2_PHY_1258_DATA 0x00000000
+#define DDRSS2_PHY_1259_DATA 0x00000000
+#define DDRSS2_PHY_1260_DATA 0x00000000
+#define DDRSS2_PHY_1261_DATA 0x00000000
+#define DDRSS2_PHY_1262_DATA 0x00000000
+#define DDRSS2_PHY_1263_DATA 0x00000000
+#define DDRSS2_PHY_1264_DATA 0x00000000
+#define DDRSS2_PHY_1265_DATA 0x00000000
+#define DDRSS2_PHY_1266_DATA 0x00000000
+#define DDRSS2_PHY_1267_DATA 0x00000000
+#define DDRSS2_PHY_1268_DATA 0x00000000
+#define DDRSS2_PHY_1269_DATA 0x00000000
+#define DDRSS2_PHY_1270_DATA 0x00000000
+#define DDRSS2_PHY_1271_DATA 0x00000000
+#define DDRSS2_PHY_1272_DATA 0x00000000
+#define DDRSS2_PHY_1273_DATA 0x00000000
+#define DDRSS2_PHY_1274_DATA 0x00000000
+#define DDRSS2_PHY_1275_DATA 0x00000000
+#define DDRSS2_PHY_1276_DATA 0x00000000
+#define DDRSS2_PHY_1277_DATA 0x00000000
+#define DDRSS2_PHY_1278_DATA 0x00000000
+#define DDRSS2_PHY_1279_DATA 0x00000000
+#define DDRSS2_PHY_1280_DATA 0x00000000
+#define DDRSS2_PHY_1281_DATA 0x00010100
+#define DDRSS2_PHY_1282_DATA 0x00000000
+#define DDRSS2_PHY_1283_DATA 0x00000000
+#define DDRSS2_PHY_1284_DATA 0x00050000
+#define DDRSS2_PHY_1285_DATA 0x04000000
+#define DDRSS2_PHY_1286_DATA 0x00000055
+#define DDRSS2_PHY_1287_DATA 0x00000000
+#define DDRSS2_PHY_1288_DATA 0x00000000
+#define DDRSS2_PHY_1289_DATA 0x00000000
+#define DDRSS2_PHY_1290_DATA 0x00000000
+#define DDRSS2_PHY_1291_DATA 0x00002001
+#define DDRSS2_PHY_1292_DATA 0x0000400F
+#define DDRSS2_PHY_1293_DATA 0x50020028
+#define DDRSS2_PHY_1294_DATA 0x01010000
+#define DDRSS2_PHY_1295_DATA 0x80080001
+#define DDRSS2_PHY_1296_DATA 0x10200000
+#define DDRSS2_PHY_1297_DATA 0x00000008
+#define DDRSS2_PHY_1298_DATA 0x00000000
+#define DDRSS2_PHY_1299_DATA 0x01090E00
+#define DDRSS2_PHY_1300_DATA 0x00040101
+#define DDRSS2_PHY_1301_DATA 0x0000010F
+#define DDRSS2_PHY_1302_DATA 0x00000000
+#define DDRSS2_PHY_1303_DATA 0x0000FFFF
+#define DDRSS2_PHY_1304_DATA 0x00000000
+#define DDRSS2_PHY_1305_DATA 0x01010000
+#define DDRSS2_PHY_1306_DATA 0x01080402
+#define DDRSS2_PHY_1307_DATA 0x01200F02
+#define DDRSS2_PHY_1308_DATA 0x00194280
+#define DDRSS2_PHY_1309_DATA 0x00000004
+#define DDRSS2_PHY_1310_DATA 0x00042000
+#define DDRSS2_PHY_1311_DATA 0x00000000
+#define DDRSS2_PHY_1312_DATA 0x00000000
+#define DDRSS2_PHY_1313_DATA 0x00000000
+#define DDRSS2_PHY_1314_DATA 0x00000000
+#define DDRSS2_PHY_1315_DATA 0x00000000
+#define DDRSS2_PHY_1316_DATA 0x00000000
+#define DDRSS2_PHY_1317_DATA 0x01000000
+#define DDRSS2_PHY_1318_DATA 0x00000705
+#define DDRSS2_PHY_1319_DATA 0x00000054
+#define DDRSS2_PHY_1320_DATA 0x00030820
+#define DDRSS2_PHY_1321_DATA 0x00010820
+#define DDRSS2_PHY_1322_DATA 0x00010820
+#define DDRSS2_PHY_1323_DATA 0x00010820
+#define DDRSS2_PHY_1324_DATA 0x00010820
+#define DDRSS2_PHY_1325_DATA 0x00010820
+#define DDRSS2_PHY_1326_DATA 0x00010820
+#define DDRSS2_PHY_1327_DATA 0x00010820
+#define DDRSS2_PHY_1328_DATA 0x00010820
+#define DDRSS2_PHY_1329_DATA 0x00000000
+#define DDRSS2_PHY_1330_DATA 0x00000074
+#define DDRSS2_PHY_1331_DATA 0x00000400
+#define DDRSS2_PHY_1332_DATA 0x00000108
+#define DDRSS2_PHY_1333_DATA 0x00000000
+#define DDRSS2_PHY_1334_DATA 0x00000000
+#define DDRSS2_PHY_1335_DATA 0x00000000
+#define DDRSS2_PHY_1336_DATA 0x00000000
+#define DDRSS2_PHY_1337_DATA 0x00000000
+#define DDRSS2_PHY_1338_DATA 0x03000000
+#define DDRSS2_PHY_1339_DATA 0x00000000
+#define DDRSS2_PHY_1340_DATA 0x00000000
+#define DDRSS2_PHY_1341_DATA 0x00000000
+#define DDRSS2_PHY_1342_DATA 0x04102006
+#define DDRSS2_PHY_1343_DATA 0x00041020
+#define DDRSS2_PHY_1344_DATA 0x01C98C98
+#define DDRSS2_PHY_1345_DATA 0x3F400000
+#define DDRSS2_PHY_1346_DATA 0x3F3F1F3F
+#define DDRSS2_PHY_1347_DATA 0x0000001F
+#define DDRSS2_PHY_1348_DATA 0x00000000
+#define DDRSS2_PHY_1349_DATA 0x00000000
+#define DDRSS2_PHY_1350_DATA 0x00000000
+#define DDRSS2_PHY_1351_DATA 0x00010000
+#define DDRSS2_PHY_1352_DATA 0x00000000
+#define DDRSS2_PHY_1353_DATA 0x00000000
+#define DDRSS2_PHY_1354_DATA 0x00000000
+#define DDRSS2_PHY_1355_DATA 0x00000000
+#define DDRSS2_PHY_1356_DATA 0x76543210
+#define DDRSS2_PHY_1357_DATA 0x00010198
+#define DDRSS2_PHY_1358_DATA 0x00000000
+#define DDRSS2_PHY_1359_DATA 0x00000000
+#define DDRSS2_PHY_1360_DATA 0x00000000
+#define DDRSS2_PHY_1361_DATA 0x00040700
+#define DDRSS2_PHY_1362_DATA 0x00000000
+#define DDRSS2_PHY_1363_DATA 0x00000000
+#define DDRSS2_PHY_1364_DATA 0x00000000
+#define DDRSS2_PHY_1365_DATA 0x00000000
+#define DDRSS2_PHY_1366_DATA 0x00000000
+#define DDRSS2_PHY_1367_DATA 0x00000002
+#define DDRSS2_PHY_1368_DATA 0x00000000
+#define DDRSS2_PHY_1369_DATA 0x00000000
+#define DDRSS2_PHY_1370_DATA 0x00000000
+#define DDRSS2_PHY_1371_DATA 0x00000000
+#define DDRSS2_PHY_1372_DATA 0x00000000
+#define DDRSS2_PHY_1373_DATA 0x00000000
+#define DDRSS2_PHY_1374_DATA 0x00080000
+#define DDRSS2_PHY_1375_DATA 0x000007FF
+#define DDRSS2_PHY_1376_DATA 0x00000000
+#define DDRSS2_PHY_1377_DATA 0x00000000
+#define DDRSS2_PHY_1378_DATA 0x00000000
+#define DDRSS2_PHY_1379_DATA 0x00000000
+#define DDRSS2_PHY_1380_DATA 0x00000000
+#define DDRSS2_PHY_1381_DATA 0x00000000
+#define DDRSS2_PHY_1382_DATA 0x000FFFFF
+#define DDRSS2_PHY_1383_DATA 0x000FFFFF
+#define DDRSS2_PHY_1384_DATA 0x0000FFFF
+#define DDRSS2_PHY_1385_DATA 0xFFFFFFF0
+#define DDRSS2_PHY_1386_DATA 0x030FFFFF
+#define DDRSS2_PHY_1387_DATA 0x01FFFFFF
+#define DDRSS2_PHY_1388_DATA 0x0000FFFF
+#define DDRSS2_PHY_1389_DATA 0x00000000
+#define DDRSS2_PHY_1390_DATA 0x00000000
+#define DDRSS2_PHY_1391_DATA 0x00000000
+#define DDRSS2_PHY_1392_DATA 0x00000000
+#define DDRSS2_PHY_1393_DATA 0x0001F7C0
+#define DDRSS2_PHY_1394_DATA 0x00000003
+#define DDRSS2_PHY_1395_DATA 0x00000000
+#define DDRSS2_PHY_1396_DATA 0x00001142
+#define DDRSS2_PHY_1397_DATA 0x010207AB
+#define DDRSS2_PHY_1398_DATA 0x01000080
+#define DDRSS2_PHY_1399_DATA 0x03900390
+#define DDRSS2_PHY_1400_DATA 0x03900390
+#define DDRSS2_PHY_1401_DATA 0x00000390
+#define DDRSS2_PHY_1402_DATA 0x00000390
+#define DDRSS2_PHY_1403_DATA 0x00000390
+#define DDRSS2_PHY_1404_DATA 0x00000390
+#define DDRSS2_PHY_1405_DATA 0x00000005
+#define DDRSS2_PHY_1406_DATA 0x01813FCC
+#define DDRSS2_PHY_1407_DATA 0x000000CC
+#define DDRSS2_PHY_1408_DATA 0x0C000DFF
+#define DDRSS2_PHY_1409_DATA 0x30000DFF
+#define DDRSS2_PHY_1410_DATA 0x3F0DFF11
+#define DDRSS2_PHY_1411_DATA 0x000100F0
+#define DDRSS2_PHY_1412_DATA 0x780DFFCC
+#define DDRSS2_PHY_1413_DATA 0x00007E31
+#define DDRSS2_PHY_1414_DATA 0x000CBF11
+#define DDRSS2_PHY_1415_DATA 0x01990010
+#define DDRSS2_PHY_1416_DATA 0x000CBF11
+#define DDRSS2_PHY_1417_DATA 0x01990010
+#define DDRSS2_PHY_1418_DATA 0x3F0DFF11
+#define DDRSS2_PHY_1419_DATA 0x00EF00F0
+#define DDRSS2_PHY_1420_DATA 0x3F0DFF11
+#define DDRSS2_PHY_1421_DATA 0x01FF00F0
+#define DDRSS2_PHY_1422_DATA 0x20040006
+
+#define DDRSS3_CTL_00_DATA 0x00000B00
+#define DDRSS3_CTL_01_DATA 0x00000000
+#define DDRSS3_CTL_02_DATA 0x00000000
+#define DDRSS3_CTL_03_DATA 0x00000000
+#define DDRSS3_CTL_04_DATA 0x00000000
+#define DDRSS3_CTL_05_DATA 0x00000000
+#define DDRSS3_CTL_06_DATA 0x00000000
+#define DDRSS3_CTL_07_DATA 0x00002AF8
+#define DDRSS3_CTL_08_DATA 0x0001ADAF
+#define DDRSS3_CTL_09_DATA 0x00000005
+#define DDRSS3_CTL_10_DATA 0x0000006E
+#define DDRSS3_CTL_11_DATA 0x000681C8
+#define DDRSS3_CTL_12_DATA 0x004111C9
+#define DDRSS3_CTL_13_DATA 0x00000005
+#define DDRSS3_CTL_14_DATA 0x000010A9
+#define DDRSS3_CTL_15_DATA 0x000681C8
+#define DDRSS3_CTL_16_DATA 0x004111C9
+#define DDRSS3_CTL_17_DATA 0x00000005
+#define DDRSS3_CTL_18_DATA 0x000010A9
+#define DDRSS3_CTL_19_DATA 0x01010000
+#define DDRSS3_CTL_20_DATA 0x02011001
+#define DDRSS3_CTL_21_DATA 0x02010000
+#define DDRSS3_CTL_22_DATA 0x00020100
+#define DDRSS3_CTL_23_DATA 0x0000000B
+#define DDRSS3_CTL_24_DATA 0x0000001C
+#define DDRSS3_CTL_25_DATA 0x00000000
+#define DDRSS3_CTL_26_DATA 0x00000000
+#define DDRSS3_CTL_27_DATA 0x03020200
+#define DDRSS3_CTL_28_DATA 0x00005656
+#define DDRSS3_CTL_29_DATA 0x00100000
+#define DDRSS3_CTL_30_DATA 0x00000000
+#define DDRSS3_CTL_31_DATA 0x00000000
+#define DDRSS3_CTL_32_DATA 0x00000000
+#define DDRSS3_CTL_33_DATA 0x00000000
+#define DDRSS3_CTL_34_DATA 0x040C0000
+#define DDRSS3_CTL_35_DATA 0x12481248
+#define DDRSS3_CTL_36_DATA 0x00050804
+#define DDRSS3_CTL_37_DATA 0x09040008
+#define DDRSS3_CTL_38_DATA 0x15000204
+#define DDRSS3_CTL_39_DATA 0x1760008B
+#define DDRSS3_CTL_40_DATA 0x1500422B
+#define DDRSS3_CTL_41_DATA 0x1760008B
+#define DDRSS3_CTL_42_DATA 0x2000422B
+#define DDRSS3_CTL_43_DATA 0x000A0A09
+#define DDRSS3_CTL_44_DATA 0x0400078A
+#define DDRSS3_CTL_45_DATA 0x1E161104
+#define DDRSS3_CTL_46_DATA 0x10012458
+#define DDRSS3_CTL_47_DATA 0x1E161110
+#define DDRSS3_CTL_48_DATA 0x10012458
+#define DDRSS3_CTL_49_DATA 0x02030410
+#define DDRSS3_CTL_50_DATA 0x2C040500
+#define DDRSS3_CTL_51_DATA 0x08292C29
+#define DDRSS3_CTL_52_DATA 0x14000E0A
+#define DDRSS3_CTL_53_DATA 0x04010A0A
+#define DDRSS3_CTL_54_DATA 0x01010004
+#define DDRSS3_CTL_55_DATA 0x04545408
+#define DDRSS3_CTL_56_DATA 0x04313104
+#define DDRSS3_CTL_57_DATA 0x00003131
+#define DDRSS3_CTL_58_DATA 0x00010100
+#define DDRSS3_CTL_59_DATA 0x03010000
+#define DDRSS3_CTL_60_DATA 0x00001508
+#define DDRSS3_CTL_61_DATA 0x000000CE
+#define DDRSS3_CTL_62_DATA 0x0000032B
+#define DDRSS3_CTL_63_DATA 0x00002073
+#define DDRSS3_CTL_64_DATA 0x0000032B
+#define DDRSS3_CTL_65_DATA 0x00002073
+#define DDRSS3_CTL_66_DATA 0x00000005
+#define DDRSS3_CTL_67_DATA 0x00050000
+#define DDRSS3_CTL_68_DATA 0x00CB0012
+#define DDRSS3_CTL_69_DATA 0x00CB0408
+#define DDRSS3_CTL_70_DATA 0x00400408
+#define DDRSS3_CTL_71_DATA 0x00120103
+#define DDRSS3_CTL_72_DATA 0x00100005
+#define DDRSS3_CTL_73_DATA 0x2F080010
+#define DDRSS3_CTL_74_DATA 0x0505012F
+#define DDRSS3_CTL_75_DATA 0x0401030A
+#define DDRSS3_CTL_76_DATA 0x041E100B
+#define DDRSS3_CTL_77_DATA 0x100B0401
+#define DDRSS3_CTL_78_DATA 0x0001041E
+#define DDRSS3_CTL_79_DATA 0x00160016
+#define DDRSS3_CTL_80_DATA 0x033B033B
+#define DDRSS3_CTL_81_DATA 0x033B033B
+#define DDRSS3_CTL_82_DATA 0x03050505
+#define DDRSS3_CTL_83_DATA 0x03010303
+#define DDRSS3_CTL_84_DATA 0x200B100B
+#define DDRSS3_CTL_85_DATA 0x04041004
+#define DDRSS3_CTL_86_DATA 0x200B100B
+#define DDRSS3_CTL_87_DATA 0x04041004
+#define DDRSS3_CTL_88_DATA 0x03010000
+#define DDRSS3_CTL_89_DATA 0x00010000
+#define DDRSS3_CTL_90_DATA 0x00000000
+#define DDRSS3_CTL_91_DATA 0x00000000
+#define DDRSS3_CTL_92_DATA 0x01000000
+#define DDRSS3_CTL_93_DATA 0x80104002
+#define DDRSS3_CTL_94_DATA 0x00000000
+#define DDRSS3_CTL_95_DATA 0x00040005
+#define DDRSS3_CTL_96_DATA 0x00000000
+#define DDRSS3_CTL_97_DATA 0x00050000
+#define DDRSS3_CTL_98_DATA 0x00000004
+#define DDRSS3_CTL_99_DATA 0x00000000
+#define DDRSS3_CTL_100_DATA 0x00040005
+#define DDRSS3_CTL_101_DATA 0x00000000
+#define DDRSS3_CTL_102_DATA 0x00003380
+#define DDRSS3_CTL_103_DATA 0x00003380
+#define DDRSS3_CTL_104_DATA 0x00003380
+#define DDRSS3_CTL_105_DATA 0x00003380
+#define DDRSS3_CTL_106_DATA 0x00003380
+#define DDRSS3_CTL_107_DATA 0x00000000
+#define DDRSS3_CTL_108_DATA 0x000005A2
+#define DDRSS3_CTL_109_DATA 0x00081CC0
+#define DDRSS3_CTL_110_DATA 0x00081CC0
+#define DDRSS3_CTL_111_DATA 0x00081CC0
+#define DDRSS3_CTL_112_DATA 0x00081CC0
+#define DDRSS3_CTL_113_DATA 0x00081CC0
+#define DDRSS3_CTL_114_DATA 0x00000000
+#define DDRSS3_CTL_115_DATA 0x0000E325
+#define DDRSS3_CTL_116_DATA 0x00081CC0
+#define DDRSS3_CTL_117_DATA 0x00081CC0
+#define DDRSS3_CTL_118_DATA 0x00081CC0
+#define DDRSS3_CTL_119_DATA 0x00081CC0
+#define DDRSS3_CTL_120_DATA 0x00081CC0
+#define DDRSS3_CTL_121_DATA 0x00000000
+#define DDRSS3_CTL_122_DATA 0x0000E325
+#define DDRSS3_CTL_123_DATA 0x00000000
+#define DDRSS3_CTL_124_DATA 0x00000000
+#define DDRSS3_CTL_125_DATA 0x00000000
+#define DDRSS3_CTL_126_DATA 0x00000000
+#define DDRSS3_CTL_127_DATA 0x00000000
+#define DDRSS3_CTL_128_DATA 0x00000000
+#define DDRSS3_CTL_129_DATA 0x00000000
+#define DDRSS3_CTL_130_DATA 0x00000000
+#define DDRSS3_CTL_131_DATA 0x0B030500
+#define DDRSS3_CTL_132_DATA 0x00040B04
+#define DDRSS3_CTL_133_DATA 0x0A090000
+#define DDRSS3_CTL_134_DATA 0x0A090701
+#define DDRSS3_CTL_135_DATA 0x0900000E
+#define DDRSS3_CTL_136_DATA 0x0907010A
+#define DDRSS3_CTL_137_DATA 0x00000E0A
+#define DDRSS3_CTL_138_DATA 0x07010A09
+#define DDRSS3_CTL_139_DATA 0x000E0A09
+#define DDRSS3_CTL_140_DATA 0x07000401
+#define DDRSS3_CTL_141_DATA 0x00000000
+#define DDRSS3_CTL_142_DATA 0x00000000
+#define DDRSS3_CTL_143_DATA 0x00000000
+#define DDRSS3_CTL_144_DATA 0x00000000
+#define DDRSS3_CTL_145_DATA 0x00000000
+#define DDRSS3_CTL_146_DATA 0x00000000
+#define DDRSS3_CTL_147_DATA 0x00000000
+#define DDRSS3_CTL_148_DATA 0x08080000
+#define DDRSS3_CTL_149_DATA 0x01000000
+#define DDRSS3_CTL_150_DATA 0x800000C0
+#define DDRSS3_CTL_151_DATA 0x800000C0
+#define DDRSS3_CTL_152_DATA 0x800000C0
+#define DDRSS3_CTL_153_DATA 0x00000000
+#define DDRSS3_CTL_154_DATA 0x00001500
+#define DDRSS3_CTL_155_DATA 0x00000000
+#define DDRSS3_CTL_156_DATA 0x00000001
+#define DDRSS3_CTL_157_DATA 0x00000002
+#define DDRSS3_CTL_158_DATA 0x0000100E
+#define DDRSS3_CTL_159_DATA 0x00000000
+#define DDRSS3_CTL_160_DATA 0x00000000
+#define DDRSS3_CTL_161_DATA 0x00000000
+#define DDRSS3_CTL_162_DATA 0x00000000
+#define DDRSS3_CTL_163_DATA 0x00000000
+#define DDRSS3_CTL_164_DATA 0x000B0000
+#define DDRSS3_CTL_165_DATA 0x000E0006
+#define DDRSS3_CTL_166_DATA 0x000E0404
+#define DDRSS3_CTL_167_DATA 0x00D601AB
+#define DDRSS3_CTL_168_DATA 0x10100216
+#define DDRSS3_CTL_169_DATA 0x01AB0216
+#define DDRSS3_CTL_170_DATA 0x021600D6
+#define DDRSS3_CTL_171_DATA 0x02161010
+#define DDRSS3_CTL_172_DATA 0x00000000
+#define DDRSS3_CTL_173_DATA 0x00000000
+#define DDRSS3_CTL_174_DATA 0x00000000
+#define DDRSS3_CTL_175_DATA 0x3FF40084
+#define DDRSS3_CTL_176_DATA 0x33003FF4
+#define DDRSS3_CTL_177_DATA 0x00003333
+#define DDRSS3_CTL_178_DATA 0x35000000
+#define DDRSS3_CTL_179_DATA 0x27270035
+#define DDRSS3_CTL_180_DATA 0x0F0F0000
+#define DDRSS3_CTL_181_DATA 0x16000000
+#define DDRSS3_CTL_182_DATA 0x00841616
+#define DDRSS3_CTL_183_DATA 0x3FF43FF4
+#define DDRSS3_CTL_184_DATA 0x33333300
+#define DDRSS3_CTL_185_DATA 0x00000000
+#define DDRSS3_CTL_186_DATA 0x00353500
+#define DDRSS3_CTL_187_DATA 0x00002727
+#define DDRSS3_CTL_188_DATA 0x00000F0F
+#define DDRSS3_CTL_189_DATA 0x16161600
+#define DDRSS3_CTL_190_DATA 0x00000020
+#define DDRSS3_CTL_191_DATA 0x00000000
+#define DDRSS3_CTL_192_DATA 0x00000001
+#define DDRSS3_CTL_193_DATA 0x00000000
+#define DDRSS3_CTL_194_DATA 0x01000000
+#define DDRSS3_CTL_195_DATA 0x00000001
+#define DDRSS3_CTL_196_DATA 0x00000000
+#define DDRSS3_CTL_197_DATA 0x00000000
+#define DDRSS3_CTL_198_DATA 0x00000000
+#define DDRSS3_CTL_199_DATA 0x00000000
+#define DDRSS3_CTL_200_DATA 0x00000000
+#define DDRSS3_CTL_201_DATA 0x00000000
+#define DDRSS3_CTL_202_DATA 0x00000000
+#define DDRSS3_CTL_203_DATA 0x00000000
+#define DDRSS3_CTL_204_DATA 0x00000000
+#define DDRSS3_CTL_205_DATA 0x00000000
+#define DDRSS3_CTL_206_DATA 0x02000000
+#define DDRSS3_CTL_207_DATA 0x01080101
+#define DDRSS3_CTL_208_DATA 0x00000000
+#define DDRSS3_CTL_209_DATA 0x00000000
+#define DDRSS3_CTL_210_DATA 0x00000000
+#define DDRSS3_CTL_211_DATA 0x00000000
+#define DDRSS3_CTL_212_DATA 0x00000000
+#define DDRSS3_CTL_213_DATA 0x00000000
+#define DDRSS3_CTL_214_DATA 0x00000000
+#define DDRSS3_CTL_215_DATA 0x00000000
+#define DDRSS3_CTL_216_DATA 0x00000000
+#define DDRSS3_CTL_217_DATA 0x00000000
+#define DDRSS3_CTL_218_DATA 0x00000000
+#define DDRSS3_CTL_219_DATA 0x00000000
+#define DDRSS3_CTL_220_DATA 0x00000000
+#define DDRSS3_CTL_221_DATA 0x00000000
+#define DDRSS3_CTL_222_DATA 0x00001000
+#define DDRSS3_CTL_223_DATA 0x006403E8
+#define DDRSS3_CTL_224_DATA 0x00000000
+#define DDRSS3_CTL_225_DATA 0x00000000
+#define DDRSS3_CTL_226_DATA 0x00000000
+#define DDRSS3_CTL_227_DATA 0x15110000
+#define DDRSS3_CTL_228_DATA 0x00040C18
+#define DDRSS3_CTL_229_DATA 0xF000C000
+#define DDRSS3_CTL_230_DATA 0x0000F000
+#define DDRSS3_CTL_231_DATA 0x00000000
+#define DDRSS3_CTL_232_DATA 0x00000000
+#define DDRSS3_CTL_233_DATA 0xC0000000
+#define DDRSS3_CTL_234_DATA 0xF000F000
+#define DDRSS3_CTL_235_DATA 0x00000000
+#define DDRSS3_CTL_236_DATA 0x00000000
+#define DDRSS3_CTL_237_DATA 0x00000000
+#define DDRSS3_CTL_238_DATA 0xF000C000
+#define DDRSS3_CTL_239_DATA 0x0000F000
+#define DDRSS3_CTL_240_DATA 0x00000000
+#define DDRSS3_CTL_241_DATA 0x00000000
+#define DDRSS3_CTL_242_DATA 0x00030000
+#define DDRSS3_CTL_243_DATA 0x00000000
+#define DDRSS3_CTL_244_DATA 0x00000000
+#define DDRSS3_CTL_245_DATA 0x00000000
+#define DDRSS3_CTL_246_DATA 0x00000000
+#define DDRSS3_CTL_247_DATA 0x00000000
+#define DDRSS3_CTL_248_DATA 0x00000000
+#define DDRSS3_CTL_249_DATA 0x00000000
+#define DDRSS3_CTL_250_DATA 0x00000000
+#define DDRSS3_CTL_251_DATA 0x00000000
+#define DDRSS3_CTL_252_DATA 0x00000000
+#define DDRSS3_CTL_253_DATA 0x00000000
+#define DDRSS3_CTL_254_DATA 0x00000000
+#define DDRSS3_CTL_255_DATA 0x00000000
+#define DDRSS3_CTL_256_DATA 0x00000000
+#define DDRSS3_CTL_257_DATA 0x01000200
+#define DDRSS3_CTL_258_DATA 0x00370040
+#define DDRSS3_CTL_259_DATA 0x00020008
+#define DDRSS3_CTL_260_DATA 0x00400100
+#define DDRSS3_CTL_261_DATA 0x00400855
+#define DDRSS3_CTL_262_DATA 0x01000200
+#define DDRSS3_CTL_263_DATA 0x08550040
+#define DDRSS3_CTL_264_DATA 0x00000040
+#define DDRSS3_CTL_265_DATA 0x006B0003
+#define DDRSS3_CTL_266_DATA 0x0100006B
+#define DDRSS3_CTL_267_DATA 0x03030303
+#define DDRSS3_CTL_268_DATA 0x00000000
+#define DDRSS3_CTL_269_DATA 0x00000202
+#define DDRSS3_CTL_270_DATA 0x00001FFF
+#define DDRSS3_CTL_271_DATA 0x3FFF2000
+#define DDRSS3_CTL_272_DATA 0x03FF0000
+#define DDRSS3_CTL_273_DATA 0x000103FF
+#define DDRSS3_CTL_274_DATA 0x0FFF0B00
+#define DDRSS3_CTL_275_DATA 0x01010001
+#define DDRSS3_CTL_276_DATA 0x01010101
+#define DDRSS3_CTL_277_DATA 0x01180101
+#define DDRSS3_CTL_278_DATA 0x00030000
+#define DDRSS3_CTL_279_DATA 0x00000000
+#define DDRSS3_CTL_280_DATA 0x00000000
+#define DDRSS3_CTL_281_DATA 0x00000000
+#define DDRSS3_CTL_282_DATA 0x00000000
+#define DDRSS3_CTL_283_DATA 0x00000000
+#define DDRSS3_CTL_284_DATA 0x00000000
+#define DDRSS3_CTL_285_DATA 0x00000000
+#define DDRSS3_CTL_286_DATA 0x00040101
+#define DDRSS3_CTL_287_DATA 0x04010100
+#define DDRSS3_CTL_288_DATA 0x00000000
+#define DDRSS3_CTL_289_DATA 0x00000000
+#define DDRSS3_CTL_290_DATA 0x03030300
+#define DDRSS3_CTL_291_DATA 0x00000001
+#define DDRSS3_CTL_292_DATA 0x00000000
+#define DDRSS3_CTL_293_DATA 0x00000000
+#define DDRSS3_CTL_294_DATA 0x00000000
+#define DDRSS3_CTL_295_DATA 0x00000000
+#define DDRSS3_CTL_296_DATA 0x00000000
+#define DDRSS3_CTL_297_DATA 0x00000000
+#define DDRSS3_CTL_298_DATA 0x00000000
+#define DDRSS3_CTL_299_DATA 0x00000000
+#define DDRSS3_CTL_300_DATA 0x00000000
+#define DDRSS3_CTL_301_DATA 0x00000000
+#define DDRSS3_CTL_302_DATA 0x00000000
+#define DDRSS3_CTL_303_DATA 0x00000000
+#define DDRSS3_CTL_304_DATA 0x00000000
+#define DDRSS3_CTL_305_DATA 0x00000000
+#define DDRSS3_CTL_306_DATA 0x00000000
+#define DDRSS3_CTL_307_DATA 0x00000000
+#define DDRSS3_CTL_308_DATA 0x00000000
+#define DDRSS3_CTL_309_DATA 0x00000000
+#define DDRSS3_CTL_310_DATA 0x00000000
+#define DDRSS3_CTL_311_DATA 0x00000000
+#define DDRSS3_CTL_312_DATA 0x00000000
+#define DDRSS3_CTL_313_DATA 0x01000000
+#define DDRSS3_CTL_314_DATA 0x00020201
+#define DDRSS3_CTL_315_DATA 0x01000101
+#define DDRSS3_CTL_316_DATA 0x01010001
+#define DDRSS3_CTL_317_DATA 0x00010101
+#define DDRSS3_CTL_318_DATA 0x050A0A03
+#define DDRSS3_CTL_319_DATA 0x10081F1F
+#define DDRSS3_CTL_320_DATA 0x00090310
+#define DDRSS3_CTL_321_DATA 0x0B0C030F
+#define DDRSS3_CTL_322_DATA 0x0B0C0306
+#define DDRSS3_CTL_323_DATA 0x0C090006
+#define DDRSS3_CTL_324_DATA 0x0100000C
+#define DDRSS3_CTL_325_DATA 0x08040801
+#define DDRSS3_CTL_326_DATA 0x00000004
+#define DDRSS3_CTL_327_DATA 0x00000000
+#define DDRSS3_CTL_328_DATA 0x00010000
+#define DDRSS3_CTL_329_DATA 0x00280D00
+#define DDRSS3_CTL_330_DATA 0x00000001
+#define DDRSS3_CTL_331_DATA 0x00030001
+#define DDRSS3_CTL_332_DATA 0x00000000
+#define DDRSS3_CTL_333_DATA 0x00000000
+#define DDRSS3_CTL_334_DATA 0x00000000
+#define DDRSS3_CTL_335_DATA 0x00000000
+#define DDRSS3_CTL_336_DATA 0x00000000
+#define DDRSS3_CTL_337_DATA 0x00000000
+#define DDRSS3_CTL_338_DATA 0x00000000
+#define DDRSS3_CTL_339_DATA 0x00000000
+#define DDRSS3_CTL_340_DATA 0x01000000
+#define DDRSS3_CTL_341_DATA 0x00000001
+#define DDRSS3_CTL_342_DATA 0x00010100
+#define DDRSS3_CTL_343_DATA 0x03030000
+#define DDRSS3_CTL_344_DATA 0x00000000
+#define DDRSS3_CTL_345_DATA 0x00000000
+#define DDRSS3_CTL_346_DATA 0x00000000
+#define DDRSS3_CTL_347_DATA 0x00000000
+#define DDRSS3_CTL_348_DATA 0x00000000
+#define DDRSS3_CTL_349_DATA 0x00000000
+#define DDRSS3_CTL_350_DATA 0x00000000
+#define DDRSS3_CTL_351_DATA 0x00000000
+#define DDRSS3_CTL_352_DATA 0x00000000
+#define DDRSS3_CTL_353_DATA 0x00000000
+#define DDRSS3_CTL_354_DATA 0x00000000
+#define DDRSS3_CTL_355_DATA 0x00000000
+#define DDRSS3_CTL_356_DATA 0x00000000
+#define DDRSS3_CTL_357_DATA 0x00000000
+#define DDRSS3_CTL_358_DATA 0x00000000
+#define DDRSS3_CTL_359_DATA 0x00000000
+#define DDRSS3_CTL_360_DATA 0x000556AA
+#define DDRSS3_CTL_361_DATA 0x000AAAAA
+#define DDRSS3_CTL_362_DATA 0x000AA955
+#define DDRSS3_CTL_363_DATA 0x00055555
+#define DDRSS3_CTL_364_DATA 0x000B3133
+#define DDRSS3_CTL_365_DATA 0x0004CD33
+#define DDRSS3_CTL_366_DATA 0x0004CECC
+#define DDRSS3_CTL_367_DATA 0x000B32CC
+#define DDRSS3_CTL_368_DATA 0x00010300
+#define DDRSS3_CTL_369_DATA 0x03000100
+#define DDRSS3_CTL_370_DATA 0x00000000
+#define DDRSS3_CTL_371_DATA 0x00000000
+#define DDRSS3_CTL_372_DATA 0x00000000
+#define DDRSS3_CTL_373_DATA 0x00000000
+#define DDRSS3_CTL_374_DATA 0x00000000
+#define DDRSS3_CTL_375_DATA 0x00000000
+#define DDRSS3_CTL_376_DATA 0x00000000
+#define DDRSS3_CTL_377_DATA 0x00010000
+#define DDRSS3_CTL_378_DATA 0x00000404
+#define DDRSS3_CTL_379_DATA 0x00000000
+#define DDRSS3_CTL_380_DATA 0x00000000
+#define DDRSS3_CTL_381_DATA 0x00000000
+#define DDRSS3_CTL_382_DATA 0x00000000
+#define DDRSS3_CTL_383_DATA 0x00000000
+#define DDRSS3_CTL_384_DATA 0x00000000
+#define DDRSS3_CTL_385_DATA 0x00000000
+#define DDRSS3_CTL_386_DATA 0x00000000
+#define DDRSS3_CTL_387_DATA 0x3A3A1B00
+#define DDRSS3_CTL_388_DATA 0x000A0000
+#define DDRSS3_CTL_389_DATA 0x0000019C
+#define DDRSS3_CTL_390_DATA 0x00000200
+#define DDRSS3_CTL_391_DATA 0x00000200
+#define DDRSS3_CTL_392_DATA 0x00000200
+#define DDRSS3_CTL_393_DATA 0x00000200
+#define DDRSS3_CTL_394_DATA 0x000004D4
+#define DDRSS3_CTL_395_DATA 0x00001018
+#define DDRSS3_CTL_396_DATA 0x00000204
+#define DDRSS3_CTL_397_DATA 0x000040E6
+#define DDRSS3_CTL_398_DATA 0x00000200
+#define DDRSS3_CTL_399_DATA 0x00000200
+#define DDRSS3_CTL_400_DATA 0x00000200
+#define DDRSS3_CTL_401_DATA 0x00000200
+#define DDRSS3_CTL_402_DATA 0x0000C2B2
+#define DDRSS3_CTL_403_DATA 0x000288FC
+#define DDRSS3_CTL_404_DATA 0x00000E15
+#define DDRSS3_CTL_405_DATA 0x000040E6
+#define DDRSS3_CTL_406_DATA 0x00000200
+#define DDRSS3_CTL_407_DATA 0x00000200
+#define DDRSS3_CTL_408_DATA 0x00000200
+#define DDRSS3_CTL_409_DATA 0x00000200
+#define DDRSS3_CTL_410_DATA 0x0000C2B2
+#define DDRSS3_CTL_411_DATA 0x000288FC
+#define DDRSS3_CTL_412_DATA 0x02020E15
+#define DDRSS3_CTL_413_DATA 0x03030202
+#define DDRSS3_CTL_414_DATA 0x00000022
+#define DDRSS3_CTL_415_DATA 0x00000000
+#define DDRSS3_CTL_416_DATA 0x00000000
+#define DDRSS3_CTL_417_DATA 0x00001403
+#define DDRSS3_CTL_418_DATA 0x000007D0
+#define DDRSS3_CTL_419_DATA 0x00000000
+#define DDRSS3_CTL_420_DATA 0x00000000
+#define DDRSS3_CTL_421_DATA 0x00030000
+#define DDRSS3_CTL_422_DATA 0x0007001F
+#define DDRSS3_CTL_423_DATA 0x001B0033
+#define DDRSS3_CTL_424_DATA 0x001B0033
+#define DDRSS3_CTL_425_DATA 0x00000000
+#define DDRSS3_CTL_426_DATA 0x00000000
+#define DDRSS3_CTL_427_DATA 0x02000000
+#define DDRSS3_CTL_428_DATA 0x01000404
+#define DDRSS3_CTL_429_DATA 0x0B1E0B1E
+#define DDRSS3_CTL_430_DATA 0x00000105
+#define DDRSS3_CTL_431_DATA 0x00010101
+#define DDRSS3_CTL_432_DATA 0x00010101
+#define DDRSS3_CTL_433_DATA 0x00010001
+#define DDRSS3_CTL_434_DATA 0x00000101
+#define DDRSS3_CTL_435_DATA 0x02000201
+#define DDRSS3_CTL_436_DATA 0x02010000
+#define DDRSS3_CTL_437_DATA 0x00000200
+#define DDRSS3_CTL_438_DATA 0x28060000
+#define DDRSS3_CTL_439_DATA 0x00000128
+#define DDRSS3_CTL_440_DATA 0xFFFFFFFF
+#define DDRSS3_CTL_441_DATA 0xFFFFFFFF
+#define DDRSS3_CTL_442_DATA 0x00000000
+#define DDRSS3_CTL_443_DATA 0x00000000
+#define DDRSS3_CTL_444_DATA 0x00000000
+#define DDRSS3_CTL_445_DATA 0x00000000
+#define DDRSS3_CTL_446_DATA 0x00000000
+#define DDRSS3_CTL_447_DATA 0x00000000
+#define DDRSS3_CTL_448_DATA 0x00000000
+#define DDRSS3_CTL_449_DATA 0x00000000
+#define DDRSS3_CTL_450_DATA 0x00000000
+#define DDRSS3_CTL_451_DATA 0x00000000
+#define DDRSS3_CTL_452_DATA 0x00000000
+#define DDRSS3_CTL_453_DATA 0x00000000
+#define DDRSS3_CTL_454_DATA 0x00000000
+#define DDRSS3_CTL_455_DATA 0x00000000
+#define DDRSS3_CTL_456_DATA 0x00000000
+#define DDRSS3_CTL_457_DATA 0x00000000
+#define DDRSS3_CTL_458_DATA 0x00000000
+
+#define DDRSS3_PI_00_DATA 0x00000B00
+#define DDRSS3_PI_01_DATA 0x00000000
+#define DDRSS3_PI_02_DATA 0x00000000
+#define DDRSS3_PI_03_DATA 0x00000000
+#define DDRSS3_PI_04_DATA 0x00000000
+#define DDRSS3_PI_05_DATA 0x00000101
+#define DDRSS3_PI_06_DATA 0x00640000
+#define DDRSS3_PI_07_DATA 0x00000001
+#define DDRSS3_PI_08_DATA 0x00000000
+#define DDRSS3_PI_09_DATA 0x00000000
+#define DDRSS3_PI_10_DATA 0x00000000
+#define DDRSS3_PI_11_DATA 0x00000000
+#define DDRSS3_PI_12_DATA 0x00000007
+#define DDRSS3_PI_13_DATA 0x00010002
+#define DDRSS3_PI_14_DATA 0x0800000F
+#define DDRSS3_PI_15_DATA 0x00000103
+#define DDRSS3_PI_16_DATA 0x00000005
+#define DDRSS3_PI_17_DATA 0x00000000
+#define DDRSS3_PI_18_DATA 0x00000000
+#define DDRSS3_PI_19_DATA 0x00000000
+#define DDRSS3_PI_20_DATA 0x00000000
+#define DDRSS3_PI_21_DATA 0x00000000
+#define DDRSS3_PI_22_DATA 0x00000000
+#define DDRSS3_PI_23_DATA 0x00000000
+#define DDRSS3_PI_24_DATA 0x00000000
+#define DDRSS3_PI_25_DATA 0x00000000
+#define DDRSS3_PI_26_DATA 0x00010100
+#define DDRSS3_PI_27_DATA 0x00280A00
+#define DDRSS3_PI_28_DATA 0x00000000
+#define DDRSS3_PI_29_DATA 0x0F000000
+#define DDRSS3_PI_30_DATA 0x00003200
+#define DDRSS3_PI_31_DATA 0x00000000
+#define DDRSS3_PI_32_DATA 0x00000000
+#define DDRSS3_PI_33_DATA 0x01010102
+#define DDRSS3_PI_34_DATA 0x00000000
+#define DDRSS3_PI_35_DATA 0x000000AA
+#define DDRSS3_PI_36_DATA 0x00000055
+#define DDRSS3_PI_37_DATA 0x000000B5
+#define DDRSS3_PI_38_DATA 0x0000004A
+#define DDRSS3_PI_39_DATA 0x00000056
+#define DDRSS3_PI_40_DATA 0x000000A9
+#define DDRSS3_PI_41_DATA 0x000000A9
+#define DDRSS3_PI_42_DATA 0x000000B5
+#define DDRSS3_PI_43_DATA 0x00000000
+#define DDRSS3_PI_44_DATA 0x00000000
+#define DDRSS3_PI_45_DATA 0x000F0F00
+#define DDRSS3_PI_46_DATA 0x0000001B
+#define DDRSS3_PI_47_DATA 0x000007D0
+#define DDRSS3_PI_48_DATA 0x00000300
+#define DDRSS3_PI_49_DATA 0x00000000
+#define DDRSS3_PI_50_DATA 0x00000000
+#define DDRSS3_PI_51_DATA 0x01000000
+#define DDRSS3_PI_52_DATA 0x00010101
+#define DDRSS3_PI_53_DATA 0x00000000
+#define DDRSS3_PI_54_DATA 0x00030000
+#define DDRSS3_PI_55_DATA 0x0F000000
+#define DDRSS3_PI_56_DATA 0x00000017
+#define DDRSS3_PI_57_DATA 0x00000000
+#define DDRSS3_PI_58_DATA 0x00000000
+#define DDRSS3_PI_59_DATA 0x00000000
+#define DDRSS3_PI_60_DATA 0x0A0A140A
+#define DDRSS3_PI_61_DATA 0x10020101
+#define DDRSS3_PI_62_DATA 0x00020805
+#define DDRSS3_PI_63_DATA 0x01000404
+#define DDRSS3_PI_64_DATA 0x00000000
+#define DDRSS3_PI_65_DATA 0x00000000
+#define DDRSS3_PI_66_DATA 0x00000100
+#define DDRSS3_PI_67_DATA 0x0001010F
+#define DDRSS3_PI_68_DATA 0x00340000
+#define DDRSS3_PI_69_DATA 0x00000000
+#define DDRSS3_PI_70_DATA 0x00000000
+#define DDRSS3_PI_71_DATA 0x0000FFFF
+#define DDRSS3_PI_72_DATA 0x00000000
+#define DDRSS3_PI_73_DATA 0x00080000
+#define DDRSS3_PI_74_DATA 0x02000200
+#define DDRSS3_PI_75_DATA 0x01000100
+#define DDRSS3_PI_76_DATA 0x01000000
+#define DDRSS3_PI_77_DATA 0x02000200
+#define DDRSS3_PI_78_DATA 0x00000200
+#define DDRSS3_PI_79_DATA 0x00000000
+#define DDRSS3_PI_80_DATA 0x00000000
+#define DDRSS3_PI_81_DATA 0x00000000
+#define DDRSS3_PI_82_DATA 0x00000000
+#define DDRSS3_PI_83_DATA 0x00000000
+#define DDRSS3_PI_84_DATA 0x00000000
+#define DDRSS3_PI_85_DATA 0x00000000
+#define DDRSS3_PI_86_DATA 0x00000000
+#define DDRSS3_PI_87_DATA 0x00000000
+#define DDRSS3_PI_88_DATA 0x00000000
+#define DDRSS3_PI_89_DATA 0x00000000
+#define DDRSS3_PI_90_DATA 0x00000000
+#define DDRSS3_PI_91_DATA 0x00000400
+#define DDRSS3_PI_92_DATA 0x02010000
+#define DDRSS3_PI_93_DATA 0x00080003
+#define DDRSS3_PI_94_DATA 0x00080000
+#define DDRSS3_PI_95_DATA 0x00000001
+#define DDRSS3_PI_96_DATA 0x00000000
+#define DDRSS3_PI_97_DATA 0x0000AA00
+#define DDRSS3_PI_98_DATA 0x00000000
+#define DDRSS3_PI_99_DATA 0x00000000
+#define DDRSS3_PI_100_DATA 0x00010000
+#define DDRSS3_PI_101_DATA 0x00000000
+#define DDRSS3_PI_102_DATA 0x00000000
+#define DDRSS3_PI_103_DATA 0x00000000
+#define DDRSS3_PI_104_DATA 0x00000000
+#define DDRSS3_PI_105_DATA 0x00000000
+#define DDRSS3_PI_106_DATA 0x00000000
+#define DDRSS3_PI_107_DATA 0x00000000
+#define DDRSS3_PI_108_DATA 0x00000000
+#define DDRSS3_PI_109_DATA 0x00000000
+#define DDRSS3_PI_110_DATA 0x00000000
+#define DDRSS3_PI_111_DATA 0x00000000
+#define DDRSS3_PI_112_DATA 0x00000000
+#define DDRSS3_PI_113_DATA 0x00000000
+#define DDRSS3_PI_114_DATA 0x00000000
+#define DDRSS3_PI_115_DATA 0x00000000
+#define DDRSS3_PI_116_DATA 0x00000000
+#define DDRSS3_PI_117_DATA 0x00000000
+#define DDRSS3_PI_118_DATA 0x00000000
+#define DDRSS3_PI_119_DATA 0x00000000
+#define DDRSS3_PI_120_DATA 0x00000000
+#define DDRSS3_PI_121_DATA 0x00000000
+#define DDRSS3_PI_122_DATA 0x00000000
+#define DDRSS3_PI_123_DATA 0x00000000
+#define DDRSS3_PI_124_DATA 0x00000000
+#define DDRSS3_PI_125_DATA 0x00000008
+#define DDRSS3_PI_126_DATA 0x00000000
+#define DDRSS3_PI_127_DATA 0x00000000
+#define DDRSS3_PI_128_DATA 0x00000000
+#define DDRSS3_PI_129_DATA 0x00000000
+#define DDRSS3_PI_130_DATA 0x00000000
+#define DDRSS3_PI_131_DATA 0x00000000
+#define DDRSS3_PI_132_DATA 0x00000000
+#define DDRSS3_PI_133_DATA 0x00000000
+#define DDRSS3_PI_134_DATA 0x00000002
+#define DDRSS3_PI_135_DATA 0x00000000
+#define DDRSS3_PI_136_DATA 0x00000000
+#define DDRSS3_PI_137_DATA 0x0000000A
+#define DDRSS3_PI_138_DATA 0x00000019
+#define DDRSS3_PI_139_DATA 0x00000100
+#define DDRSS3_PI_140_DATA 0x00000000
+#define DDRSS3_PI_141_DATA 0x00000000
+#define DDRSS3_PI_142_DATA 0x00000000
+#define DDRSS3_PI_143_DATA 0x00000000
+#define DDRSS3_PI_144_DATA 0x01000000
+#define DDRSS3_PI_145_DATA 0x00010003
+#define DDRSS3_PI_146_DATA 0x02000101
+#define DDRSS3_PI_147_DATA 0x01030001
+#define DDRSS3_PI_148_DATA 0x00010400
+#define DDRSS3_PI_149_DATA 0x06000105
+#define DDRSS3_PI_150_DATA 0x01070001
+#define DDRSS3_PI_151_DATA 0x00000000
+#define DDRSS3_PI_152_DATA 0x00000000
+#define DDRSS3_PI_153_DATA 0x00000000
+#define DDRSS3_PI_154_DATA 0x00010001
+#define DDRSS3_PI_155_DATA 0x00000000
+#define DDRSS3_PI_156_DATA 0x00000000
+#define DDRSS3_PI_157_DATA 0x00000000
+#define DDRSS3_PI_158_DATA 0x00000000
+#define DDRSS3_PI_159_DATA 0x00000401
+#define DDRSS3_PI_160_DATA 0x00000000
+#define DDRSS3_PI_161_DATA 0x00010000
+#define DDRSS3_PI_162_DATA 0x00000000
+#define DDRSS3_PI_163_DATA 0x2B2B0200
+#define DDRSS3_PI_164_DATA 0x00000034
+#define DDRSS3_PI_165_DATA 0x00000064
+#define DDRSS3_PI_166_DATA 0x00020064
+#define DDRSS3_PI_167_DATA 0x02000200
+#define DDRSS3_PI_168_DATA 0x48120C04
+#define DDRSS3_PI_169_DATA 0x00154812
+#define DDRSS3_PI_170_DATA 0x000000CE
+#define DDRSS3_PI_171_DATA 0x0000032B
+#define DDRSS3_PI_172_DATA 0x00002073
+#define DDRSS3_PI_173_DATA 0x0000032B
+#define DDRSS3_PI_174_DATA 0x04002073
+#define DDRSS3_PI_175_DATA 0x01010404
+#define DDRSS3_PI_176_DATA 0x00001501
+#define DDRSS3_PI_177_DATA 0x00150015
+#define DDRSS3_PI_178_DATA 0x01000100
+#define DDRSS3_PI_179_DATA 0x00000100
+#define DDRSS3_PI_180_DATA 0x00000000
+#define DDRSS3_PI_181_DATA 0x01010101
+#define DDRSS3_PI_182_DATA 0x00000101
+#define DDRSS3_PI_183_DATA 0x00000000
+#define DDRSS3_PI_184_DATA 0x00000000
+#define DDRSS3_PI_185_DATA 0x15040000
+#define DDRSS3_PI_186_DATA 0x0E0E0215
+#define DDRSS3_PI_187_DATA 0x00040402
+#define DDRSS3_PI_188_DATA 0x000D0035
+#define DDRSS3_PI_189_DATA 0x00218049
+#define DDRSS3_PI_190_DATA 0x00218049
+#define DDRSS3_PI_191_DATA 0x01010101
+#define DDRSS3_PI_192_DATA 0x0004000E
+#define DDRSS3_PI_193_DATA 0x00040216
+#define DDRSS3_PI_194_DATA 0x01000216
+#define DDRSS3_PI_195_DATA 0x000F000F
+#define DDRSS3_PI_196_DATA 0x02170100
+#define DDRSS3_PI_197_DATA 0x01000217
+#define DDRSS3_PI_198_DATA 0x02170217
+#define DDRSS3_PI_199_DATA 0x32103200
+#define DDRSS3_PI_200_DATA 0x01013210
+#define DDRSS3_PI_201_DATA 0x0A070601
+#define DDRSS3_PI_202_DATA 0x1F130A0D
+#define DDRSS3_PI_203_DATA 0x1F130A14
+#define DDRSS3_PI_204_DATA 0x0000C014
+#define DDRSS3_PI_205_DATA 0x00C01000
+#define DDRSS3_PI_206_DATA 0x00C01000
+#define DDRSS3_PI_207_DATA 0x00021000
+#define DDRSS3_PI_208_DATA 0x0024000E
+#define DDRSS3_PI_209_DATA 0x00240216
+#define DDRSS3_PI_210_DATA 0x00110216
+#define DDRSS3_PI_211_DATA 0x32000056
+#define DDRSS3_PI_212_DATA 0x00000301
+#define DDRSS3_PI_213_DATA 0x005B0036
+#define DDRSS3_PI_214_DATA 0x03013212
+#define DDRSS3_PI_215_DATA 0x00003600
+#define DDRSS3_PI_216_DATA 0x3212005B
+#define DDRSS3_PI_217_DATA 0x09000301
+#define DDRSS3_PI_218_DATA 0x04010504
+#define DDRSS3_PI_219_DATA 0x040006C9
+#define DDRSS3_PI_220_DATA 0x0A032001
+#define DDRSS3_PI_221_DATA 0x2C31110A
+#define DDRSS3_PI_222_DATA 0x00002918
+#define DDRSS3_PI_223_DATA 0x6001071C
+#define DDRSS3_PI_224_DATA 0x1E202008
+#define DDRSS3_PI_225_DATA 0x2C311116
+#define DDRSS3_PI_226_DATA 0x00002918
+#define DDRSS3_PI_227_DATA 0x6001071C
+#define DDRSS3_PI_228_DATA 0x1E202008
+#define DDRSS3_PI_229_DATA 0x00019C16
+#define DDRSS3_PI_230_DATA 0x00001018
+#define DDRSS3_PI_231_DATA 0x000040E6
+#define DDRSS3_PI_232_DATA 0x000288FC
+#define DDRSS3_PI_233_DATA 0x000040E6
+#define DDRSS3_PI_234_DATA 0x000288FC
+#define DDRSS3_PI_235_DATA 0x033B0016
+#define DDRSS3_PI_236_DATA 0x0303033B
+#define DDRSS3_PI_237_DATA 0x002AF803
+#define DDRSS3_PI_238_DATA 0x0001ADAF
+#define DDRSS3_PI_239_DATA 0x00000005
+#define DDRSS3_PI_240_DATA 0x0000006E
+#define DDRSS3_PI_241_DATA 0x00000016
+#define DDRSS3_PI_242_DATA 0x000681C8
+#define DDRSS3_PI_243_DATA 0x0001ADAF
+#define DDRSS3_PI_244_DATA 0x00000005
+#define DDRSS3_PI_245_DATA 0x000010A9
+#define DDRSS3_PI_246_DATA 0x0000033B
+#define DDRSS3_PI_247_DATA 0x000681C8
+#define DDRSS3_PI_248_DATA 0x0001ADAF
+#define DDRSS3_PI_249_DATA 0x00000005
+#define DDRSS3_PI_250_DATA 0x000010A9
+#define DDRSS3_PI_251_DATA 0x0100033B
+#define DDRSS3_PI_252_DATA 0x00370040
+#define DDRSS3_PI_253_DATA 0x00010008
+#define DDRSS3_PI_254_DATA 0x08550040
+#define DDRSS3_PI_255_DATA 0x00010040
+#define DDRSS3_PI_256_DATA 0x08550040
+#define DDRSS3_PI_257_DATA 0x00000340
+#define DDRSS3_PI_258_DATA 0x006B006B
+#define DDRSS3_PI_259_DATA 0x08040404
+#define DDRSS3_PI_260_DATA 0x00000055
+#define DDRSS3_PI_261_DATA 0x55083C5A
+#define DDRSS3_PI_262_DATA 0x5A000000
+#define DDRSS3_PI_263_DATA 0x0055083C
+#define DDRSS3_PI_264_DATA 0x3C5A0000
+#define DDRSS3_PI_265_DATA 0x00005508
+#define DDRSS3_PI_266_DATA 0x0C3C5A00
+#define DDRSS3_PI_267_DATA 0x080F0E0D
+#define DDRSS3_PI_268_DATA 0x000B0A09
+#define DDRSS3_PI_269_DATA 0x00030201
+#define DDRSS3_PI_270_DATA 0x01000000
+#define DDRSS3_PI_271_DATA 0x04020201
+#define DDRSS3_PI_272_DATA 0x00080804
+#define DDRSS3_PI_273_DATA 0x00000000
+#define DDRSS3_PI_274_DATA 0x00000000
+#define DDRSS3_PI_275_DATA 0x00330084
+#define DDRSS3_PI_276_DATA 0x00160000
+#define DDRSS3_PI_277_DATA 0x35333FF4
+#define DDRSS3_PI_278_DATA 0x00160F27
+#define DDRSS3_PI_279_DATA 0x35333FF4
+#define DDRSS3_PI_280_DATA 0x00160F27
+#define DDRSS3_PI_281_DATA 0x00330084
+#define DDRSS3_PI_282_DATA 0x00160000
+#define DDRSS3_PI_283_DATA 0x35333FF4
+#define DDRSS3_PI_284_DATA 0x00160F27
+#define DDRSS3_PI_285_DATA 0x35333FF4
+#define DDRSS3_PI_286_DATA 0x00160F27
+#define DDRSS3_PI_287_DATA 0x00330084
+#define DDRSS3_PI_288_DATA 0x00160000
+#define DDRSS3_PI_289_DATA 0x35333FF4
+#define DDRSS3_PI_290_DATA 0x00160F27
+#define DDRSS3_PI_291_DATA 0x35333FF4
+#define DDRSS3_PI_292_DATA 0x00160F27
+#define DDRSS3_PI_293_DATA 0x00330084
+#define DDRSS3_PI_294_DATA 0x00160000
+#define DDRSS3_PI_295_DATA 0x35333FF4
+#define DDRSS3_PI_296_DATA 0x00160F27
+#define DDRSS3_PI_297_DATA 0x35333FF4
+#define DDRSS3_PI_298_DATA 0x00160F27
+#define DDRSS3_PI_299_DATA 0x00000000
+
+#define DDRSS3_PHY_00_DATA 0x000004F0
+#define DDRSS3_PHY_01_DATA 0x00000000
+#define DDRSS3_PHY_02_DATA 0x00030200
+#define DDRSS3_PHY_03_DATA 0x00000000
+#define DDRSS3_PHY_04_DATA 0x00000000
+#define DDRSS3_PHY_05_DATA 0x01030000
+#define DDRSS3_PHY_06_DATA 0x00010000
+#define DDRSS3_PHY_07_DATA 0x01030004
+#define DDRSS3_PHY_08_DATA 0x01000000
+#define DDRSS3_PHY_09_DATA 0x00000000
+#define DDRSS3_PHY_10_DATA 0x00000000
+#define DDRSS3_PHY_11_DATA 0x01000001
+#define DDRSS3_PHY_12_DATA 0x00000100
+#define DDRSS3_PHY_13_DATA 0x000800C0
+#define DDRSS3_PHY_14_DATA 0x060100CC
+#define DDRSS3_PHY_15_DATA 0x00030066
+#define DDRSS3_PHY_16_DATA 0x00000000
+#define DDRSS3_PHY_17_DATA 0x00000301
+#define DDRSS3_PHY_18_DATA 0x0000AAAA
+#define DDRSS3_PHY_19_DATA 0x00005555
+#define DDRSS3_PHY_20_DATA 0x0000B5B5
+#define DDRSS3_PHY_21_DATA 0x00004A4A
+#define DDRSS3_PHY_22_DATA 0x00005656
+#define DDRSS3_PHY_23_DATA 0x0000A9A9
+#define DDRSS3_PHY_24_DATA 0x0000A9A9
+#define DDRSS3_PHY_25_DATA 0x0000B5B5
+#define DDRSS3_PHY_26_DATA 0x00000000
+#define DDRSS3_PHY_27_DATA 0x00000000
+#define DDRSS3_PHY_28_DATA 0x2A000000
+#define DDRSS3_PHY_29_DATA 0x00000808
+#define DDRSS3_PHY_30_DATA 0x0F000000
+#define DDRSS3_PHY_31_DATA 0x00000F0F
+#define DDRSS3_PHY_32_DATA 0x10400000
+#define DDRSS3_PHY_33_DATA 0x0C002006
+#define DDRSS3_PHY_34_DATA 0x00000000
+#define DDRSS3_PHY_35_DATA 0x00000000
+#define DDRSS3_PHY_36_DATA 0x55555555
+#define DDRSS3_PHY_37_DATA 0xAAAAAAAA
+#define DDRSS3_PHY_38_DATA 0x55555555
+#define DDRSS3_PHY_39_DATA 0xAAAAAAAA
+#define DDRSS3_PHY_40_DATA 0x00005555
+#define DDRSS3_PHY_41_DATA 0x01000100
+#define DDRSS3_PHY_42_DATA 0x00800180
+#define DDRSS3_PHY_43_DATA 0x00000001
+#define DDRSS3_PHY_44_DATA 0x00000000
+#define DDRSS3_PHY_45_DATA 0x00000000
+#define DDRSS3_PHY_46_DATA 0x00000000
+#define DDRSS3_PHY_47_DATA 0x00000000
+#define DDRSS3_PHY_48_DATA 0x00000000
+#define DDRSS3_PHY_49_DATA 0x00000000
+#define DDRSS3_PHY_50_DATA 0x00000000
+#define DDRSS3_PHY_51_DATA 0x00000000
+#define DDRSS3_PHY_52_DATA 0x00000000
+#define DDRSS3_PHY_53_DATA 0x00000000
+#define DDRSS3_PHY_54_DATA 0x00000000
+#define DDRSS3_PHY_55_DATA 0x00000000
+#define DDRSS3_PHY_56_DATA 0x00000000
+#define DDRSS3_PHY_57_DATA 0x00000000
+#define DDRSS3_PHY_58_DATA 0x00000000
+#define DDRSS3_PHY_59_DATA 0x00000000
+#define DDRSS3_PHY_60_DATA 0x00000000
+#define DDRSS3_PHY_61_DATA 0x00000000
+#define DDRSS3_PHY_62_DATA 0x00000000
+#define DDRSS3_PHY_63_DATA 0x00000000
+#define DDRSS3_PHY_64_DATA 0x00000000
+#define DDRSS3_PHY_65_DATA 0x00000000
+#define DDRSS3_PHY_66_DATA 0x00000104
+#define DDRSS3_PHY_67_DATA 0x00000120
+#define DDRSS3_PHY_68_DATA 0x00000000
+#define DDRSS3_PHY_69_DATA 0x00000000
+#define DDRSS3_PHY_70_DATA 0x00000000
+#define DDRSS3_PHY_71_DATA 0x00000000
+#define DDRSS3_PHY_72_DATA 0x00000000
+#define DDRSS3_PHY_73_DATA 0x00000000
+#define DDRSS3_PHY_74_DATA 0x00000000
+#define DDRSS3_PHY_75_DATA 0x00000001
+#define DDRSS3_PHY_76_DATA 0x07FF0000
+#define DDRSS3_PHY_77_DATA 0x0080081F
+#define DDRSS3_PHY_78_DATA 0x00081020
+#define DDRSS3_PHY_79_DATA 0x04010000
+#define DDRSS3_PHY_80_DATA 0x00000000
+#define DDRSS3_PHY_81_DATA 0x00000000
+#define DDRSS3_PHY_82_DATA 0x00000000
+#define DDRSS3_PHY_83_DATA 0x00000100
+#define DDRSS3_PHY_84_DATA 0x01CC0C01
+#define DDRSS3_PHY_85_DATA 0x1003CC0C
+#define DDRSS3_PHY_86_DATA 0x20000140
+#define DDRSS3_PHY_87_DATA 0x07FF0200
+#define DDRSS3_PHY_88_DATA 0x0000DD01
+#define DDRSS3_PHY_89_DATA 0x10100303
+#define DDRSS3_PHY_90_DATA 0x10101010
+#define DDRSS3_PHY_91_DATA 0x10101010
+#define DDRSS3_PHY_92_DATA 0x00021010
+#define DDRSS3_PHY_93_DATA 0x00100010
+#define DDRSS3_PHY_94_DATA 0x00100010
+#define DDRSS3_PHY_95_DATA 0x00100010
+#define DDRSS3_PHY_96_DATA 0x00100010
+#define DDRSS3_PHY_97_DATA 0x00050010
+#define DDRSS3_PHY_98_DATA 0x51517041
+#define DDRSS3_PHY_99_DATA 0x31C06001
+#define DDRSS3_PHY_100_DATA 0x07AB0340
+#define DDRSS3_PHY_101_DATA 0x00C0C001
+#define DDRSS3_PHY_102_DATA 0x0E0D0001
+#define DDRSS3_PHY_103_DATA 0x10001000
+#define DDRSS3_PHY_104_DATA 0x0C083E42
+#define DDRSS3_PHY_105_DATA 0x0F0C3701
+#define DDRSS3_PHY_106_DATA 0x01000140
+#define DDRSS3_PHY_107_DATA 0x0C000420
+#define DDRSS3_PHY_108_DATA 0x00000198
+#define DDRSS3_PHY_109_DATA 0x0A0000D0
+#define DDRSS3_PHY_110_DATA 0x00030200
+#define DDRSS3_PHY_111_DATA 0x02800000
+#define DDRSS3_PHY_112_DATA 0x80800000
+#define DDRSS3_PHY_113_DATA 0x000E2010
+#define DDRSS3_PHY_114_DATA 0x76543210
+#define DDRSS3_PHY_115_DATA 0x00000008
+#define DDRSS3_PHY_116_DATA 0x02800280
+#define DDRSS3_PHY_117_DATA 0x02800280
+#define DDRSS3_PHY_118_DATA 0x02800280
+#define DDRSS3_PHY_119_DATA 0x02800280
+#define DDRSS3_PHY_120_DATA 0x00000280
+#define DDRSS3_PHY_121_DATA 0x0000A000
+#define DDRSS3_PHY_122_DATA 0x00A000A0
+#define DDRSS3_PHY_123_DATA 0x00A000A0
+#define DDRSS3_PHY_124_DATA 0x00A000A0
+#define DDRSS3_PHY_125_DATA 0x00A000A0
+#define DDRSS3_PHY_126_DATA 0x00A000A0
+#define DDRSS3_PHY_127_DATA 0x00A000A0
+#define DDRSS3_PHY_128_DATA 0x00A000A0
+#define DDRSS3_PHY_129_DATA 0x00A000A0
+#define DDRSS3_PHY_130_DATA 0x01C200A0
+#define DDRSS3_PHY_131_DATA 0x01A00005
+#define DDRSS3_PHY_132_DATA 0x00000000
+#define DDRSS3_PHY_133_DATA 0x00000000
+#define DDRSS3_PHY_134_DATA 0x00080200
+#define DDRSS3_PHY_135_DATA 0x00000000
+#define DDRSS3_PHY_136_DATA 0x20202000
+#define DDRSS3_PHY_137_DATA 0x20202020
+#define DDRSS3_PHY_138_DATA 0xF0F02020
+#define DDRSS3_PHY_139_DATA 0x00000000
+#define DDRSS3_PHY_140_DATA 0x00000000
+#define DDRSS3_PHY_141_DATA 0x00000000
+#define DDRSS3_PHY_142_DATA 0x00000000
+#define DDRSS3_PHY_143_DATA 0x00000000
+#define DDRSS3_PHY_144_DATA 0x00000000
+#define DDRSS3_PHY_145_DATA 0x00000000
+#define DDRSS3_PHY_146_DATA 0x00000000
+#define DDRSS3_PHY_147_DATA 0x00000000
+#define DDRSS3_PHY_148_DATA 0x00000000
+#define DDRSS3_PHY_149_DATA 0x00000000
+#define DDRSS3_PHY_150_DATA 0x00000000
+#define DDRSS3_PHY_151_DATA 0x00000000
+#define DDRSS3_PHY_152_DATA 0x00000000
+#define DDRSS3_PHY_153_DATA 0x00000000
+#define DDRSS3_PHY_154_DATA 0x00000000
+#define DDRSS3_PHY_155_DATA 0x00000000
+#define DDRSS3_PHY_156_DATA 0x00000000
+#define DDRSS3_PHY_157_DATA 0x00000000
+#define DDRSS3_PHY_158_DATA 0x00000000
+#define DDRSS3_PHY_159_DATA 0x00000000
+#define DDRSS3_PHY_160_DATA 0x00000000
+#define DDRSS3_PHY_161_DATA 0x00000000
+#define DDRSS3_PHY_162_DATA 0x00000000
+#define DDRSS3_PHY_163_DATA 0x00000000
+#define DDRSS3_PHY_164_DATA 0x00000000
+#define DDRSS3_PHY_165_DATA 0x00000000
+#define DDRSS3_PHY_166_DATA 0x00000000
+#define DDRSS3_PHY_167_DATA 0x00000000
+#define DDRSS3_PHY_168_DATA 0x00000000
+#define DDRSS3_PHY_169_DATA 0x00000000
+#define DDRSS3_PHY_170_DATA 0x00000000
+#define DDRSS3_PHY_171_DATA 0x00000000
+#define DDRSS3_PHY_172_DATA 0x00000000
+#define DDRSS3_PHY_173_DATA 0x00000000
+#define DDRSS3_PHY_174_DATA 0x00000000
+#define DDRSS3_PHY_175_DATA 0x00000000
+#define DDRSS3_PHY_176_DATA 0x00000000
+#define DDRSS3_PHY_177_DATA 0x00000000
+#define DDRSS3_PHY_178_DATA 0x00000000
+#define DDRSS3_PHY_179_DATA 0x00000000
+#define DDRSS3_PHY_180_DATA 0x00000000
+#define DDRSS3_PHY_181_DATA 0x00000000
+#define DDRSS3_PHY_182_DATA 0x00000000
+#define DDRSS3_PHY_183_DATA 0x00000000
+#define DDRSS3_PHY_184_DATA 0x00000000
+#define DDRSS3_PHY_185_DATA 0x00000000
+#define DDRSS3_PHY_186_DATA 0x00000000
+#define DDRSS3_PHY_187_DATA 0x00000000
+#define DDRSS3_PHY_188_DATA 0x00000000
+#define DDRSS3_PHY_189_DATA 0x00000000
+#define DDRSS3_PHY_190_DATA 0x00000000
+#define DDRSS3_PHY_191_DATA 0x00000000
+#define DDRSS3_PHY_192_DATA 0x00000000
+#define DDRSS3_PHY_193_DATA 0x00000000
+#define DDRSS3_PHY_194_DATA 0x00000000
+#define DDRSS3_PHY_195_DATA 0x00000000
+#define DDRSS3_PHY_196_DATA 0x00000000
+#define DDRSS3_PHY_197_DATA 0x00000000
+#define DDRSS3_PHY_198_DATA 0x00000000
+#define DDRSS3_PHY_199_DATA 0x00000000
+#define DDRSS3_PHY_200_DATA 0x00000000
+#define DDRSS3_PHY_201_DATA 0x00000000
+#define DDRSS3_PHY_202_DATA 0x00000000
+#define DDRSS3_PHY_203_DATA 0x00000000
+#define DDRSS3_PHY_204_DATA 0x00000000
+#define DDRSS3_PHY_205_DATA 0x00000000
+#define DDRSS3_PHY_206_DATA 0x00000000
+#define DDRSS3_PHY_207_DATA 0x00000000
+#define DDRSS3_PHY_208_DATA 0x00000000
+#define DDRSS3_PHY_209_DATA 0x00000000
+#define DDRSS3_PHY_210_DATA 0x00000000
+#define DDRSS3_PHY_211_DATA 0x00000000
+#define DDRSS3_PHY_212_DATA 0x00000000
+#define DDRSS3_PHY_213_DATA 0x00000000
+#define DDRSS3_PHY_214_DATA 0x00000000
+#define DDRSS3_PHY_215_DATA 0x00000000
+#define DDRSS3_PHY_216_DATA 0x00000000
+#define DDRSS3_PHY_217_DATA 0x00000000
+#define DDRSS3_PHY_218_DATA 0x00000000
+#define DDRSS3_PHY_219_DATA 0x00000000
+#define DDRSS3_PHY_220_DATA 0x00000000
+#define DDRSS3_PHY_221_DATA 0x00000000
+#define DDRSS3_PHY_222_DATA 0x00000000
+#define DDRSS3_PHY_223_DATA 0x00000000
+#define DDRSS3_PHY_224_DATA 0x00000000
+#define DDRSS3_PHY_225_DATA 0x00000000
+#define DDRSS3_PHY_226_DATA 0x00000000
+#define DDRSS3_PHY_227_DATA 0x00000000
+#define DDRSS3_PHY_228_DATA 0x00000000
+#define DDRSS3_PHY_229_DATA 0x00000000
+#define DDRSS3_PHY_230_DATA 0x00000000
+#define DDRSS3_PHY_231_DATA 0x00000000
+#define DDRSS3_PHY_232_DATA 0x00000000
+#define DDRSS3_PHY_233_DATA 0x00000000
+#define DDRSS3_PHY_234_DATA 0x00000000
+#define DDRSS3_PHY_235_DATA 0x00000000
+#define DDRSS3_PHY_236_DATA 0x00000000
+#define DDRSS3_PHY_237_DATA 0x00000000
+#define DDRSS3_PHY_238_DATA 0x00000000
+#define DDRSS3_PHY_239_DATA 0x00000000
+#define DDRSS3_PHY_240_DATA 0x00000000
+#define DDRSS3_PHY_241_DATA 0x00000000
+#define DDRSS3_PHY_242_DATA 0x00000000
+#define DDRSS3_PHY_243_DATA 0x00000000
+#define DDRSS3_PHY_244_DATA 0x00000000
+#define DDRSS3_PHY_245_DATA 0x00000000
+#define DDRSS3_PHY_246_DATA 0x00000000
+#define DDRSS3_PHY_247_DATA 0x00000000
+#define DDRSS3_PHY_248_DATA 0x00000000
+#define DDRSS3_PHY_249_DATA 0x00000000
+#define DDRSS3_PHY_250_DATA 0x00000000
+#define DDRSS3_PHY_251_DATA 0x00000000
+#define DDRSS3_PHY_252_DATA 0x00000000
+#define DDRSS3_PHY_253_DATA 0x00000000
+#define DDRSS3_PHY_254_DATA 0x00000000
+#define DDRSS3_PHY_255_DATA 0x00000000
+#define DDRSS3_PHY_256_DATA 0x000004F0
+#define DDRSS3_PHY_257_DATA 0x00000000
+#define DDRSS3_PHY_258_DATA 0x00030200
+#define DDRSS3_PHY_259_DATA 0x00000000
+#define DDRSS3_PHY_260_DATA 0x00000000
+#define DDRSS3_PHY_261_DATA 0x01030000
+#define DDRSS3_PHY_262_DATA 0x00010000
+#define DDRSS3_PHY_263_DATA 0x01030004
+#define DDRSS3_PHY_264_DATA 0x01000000
+#define DDRSS3_PHY_265_DATA 0x00000000
+#define DDRSS3_PHY_266_DATA 0x00000000
+#define DDRSS3_PHY_267_DATA 0x01000001
+#define DDRSS3_PHY_268_DATA 0x00000100
+#define DDRSS3_PHY_269_DATA 0x000800C0
+#define DDRSS3_PHY_270_DATA 0x060100CC
+#define DDRSS3_PHY_271_DATA 0x00030066
+#define DDRSS3_PHY_272_DATA 0x00000000
+#define DDRSS3_PHY_273_DATA 0x00000301
+#define DDRSS3_PHY_274_DATA 0x0000AAAA
+#define DDRSS3_PHY_275_DATA 0x00005555
+#define DDRSS3_PHY_276_DATA 0x0000B5B5
+#define DDRSS3_PHY_277_DATA 0x00004A4A
+#define DDRSS3_PHY_278_DATA 0x00005656
+#define DDRSS3_PHY_279_DATA 0x0000A9A9
+#define DDRSS3_PHY_280_DATA 0x0000A9A9
+#define DDRSS3_PHY_281_DATA 0x0000B5B5
+#define DDRSS3_PHY_282_DATA 0x00000000
+#define DDRSS3_PHY_283_DATA 0x00000000
+#define DDRSS3_PHY_284_DATA 0x2A000000
+#define DDRSS3_PHY_285_DATA 0x00000808
+#define DDRSS3_PHY_286_DATA 0x0F000000
+#define DDRSS3_PHY_287_DATA 0x00000F0F
+#define DDRSS3_PHY_288_DATA 0x10400000
+#define DDRSS3_PHY_289_DATA 0x0C002006
+#define DDRSS3_PHY_290_DATA 0x00000000
+#define DDRSS3_PHY_291_DATA 0x00000000
+#define DDRSS3_PHY_292_DATA 0x55555555
+#define DDRSS3_PHY_293_DATA 0xAAAAAAAA
+#define DDRSS3_PHY_294_DATA 0x55555555
+#define DDRSS3_PHY_295_DATA 0xAAAAAAAA
+#define DDRSS3_PHY_296_DATA 0x00005555
+#define DDRSS3_PHY_297_DATA 0x01000100
+#define DDRSS3_PHY_298_DATA 0x00800180
+#define DDRSS3_PHY_299_DATA 0x00000000
+#define DDRSS3_PHY_300_DATA 0x00000000
+#define DDRSS3_PHY_301_DATA 0x00000000
+#define DDRSS3_PHY_302_DATA 0x00000000
+#define DDRSS3_PHY_303_DATA 0x00000000
+#define DDRSS3_PHY_304_DATA 0x00000000
+#define DDRSS3_PHY_305_DATA 0x00000000
+#define DDRSS3_PHY_306_DATA 0x00000000
+#define DDRSS3_PHY_307_DATA 0x00000000
+#define DDRSS3_PHY_308_DATA 0x00000000
+#define DDRSS3_PHY_309_DATA 0x00000000
+#define DDRSS3_PHY_310_DATA 0x00000000
+#define DDRSS3_PHY_311_DATA 0x00000000
+#define DDRSS3_PHY_312_DATA 0x00000000
+#define DDRSS3_PHY_313_DATA 0x00000000
+#define DDRSS3_PHY_314_DATA 0x00000000
+#define DDRSS3_PHY_315_DATA 0x00000000
+#define DDRSS3_PHY_316_DATA 0x00000000
+#define DDRSS3_PHY_317_DATA 0x00000000
+#define DDRSS3_PHY_318_DATA 0x00000000
+#define DDRSS3_PHY_319_DATA 0x00000000
+#define DDRSS3_PHY_320_DATA 0x00000000
+#define DDRSS3_PHY_321_DATA 0x00000000
+#define DDRSS3_PHY_322_DATA 0x00000104
+#define DDRSS3_PHY_323_DATA 0x00000120
+#define DDRSS3_PHY_324_DATA 0x00000000
+#define DDRSS3_PHY_325_DATA 0x00000000
+#define DDRSS3_PHY_326_DATA 0x00000000
+#define DDRSS3_PHY_327_DATA 0x00000000
+#define DDRSS3_PHY_328_DATA 0x00000000
+#define DDRSS3_PHY_329_DATA 0x00000000
+#define DDRSS3_PHY_330_DATA 0x00000000
+#define DDRSS3_PHY_331_DATA 0x00000001
+#define DDRSS3_PHY_332_DATA 0x07FF0000
+#define DDRSS3_PHY_333_DATA 0x0080081F
+#define DDRSS3_PHY_334_DATA 0x00081020
+#define DDRSS3_PHY_335_DATA 0x04010000
+#define DDRSS3_PHY_336_DATA 0x00000000
+#define DDRSS3_PHY_337_DATA 0x00000000
+#define DDRSS3_PHY_338_DATA 0x00000000
+#define DDRSS3_PHY_339_DATA 0x00000100
+#define DDRSS3_PHY_340_DATA 0x01CC0C01
+#define DDRSS3_PHY_341_DATA 0x1003CC0C
+#define DDRSS3_PHY_342_DATA 0x20000140
+#define DDRSS3_PHY_343_DATA 0x07FF0200
+#define DDRSS3_PHY_344_DATA 0x0000DD01
+#define DDRSS3_PHY_345_DATA 0x10100303
+#define DDRSS3_PHY_346_DATA 0x10101010
+#define DDRSS3_PHY_347_DATA 0x10101010
+#define DDRSS3_PHY_348_DATA 0x00021010
+#define DDRSS3_PHY_349_DATA 0x00100010
+#define DDRSS3_PHY_350_DATA 0x00100010
+#define DDRSS3_PHY_351_DATA 0x00100010
+#define DDRSS3_PHY_352_DATA 0x00100010
+#define DDRSS3_PHY_353_DATA 0x00050010
+#define DDRSS3_PHY_354_DATA 0x51517041
+#define DDRSS3_PHY_355_DATA 0x31C06001
+#define DDRSS3_PHY_356_DATA 0x07AB0340
+#define DDRSS3_PHY_357_DATA 0x00C0C001
+#define DDRSS3_PHY_358_DATA 0x0E0D0001
+#define DDRSS3_PHY_359_DATA 0x10001000
+#define DDRSS3_PHY_360_DATA 0x0C083E42
+#define DDRSS3_PHY_361_DATA 0x0F0C3701
+#define DDRSS3_PHY_362_DATA 0x01000140
+#define DDRSS3_PHY_363_DATA 0x0C000420
+#define DDRSS3_PHY_364_DATA 0x00000198
+#define DDRSS3_PHY_365_DATA 0x0A0000D0
+#define DDRSS3_PHY_366_DATA 0x00030200
+#define DDRSS3_PHY_367_DATA 0x02800000
+#define DDRSS3_PHY_368_DATA 0x80800000
+#define DDRSS3_PHY_369_DATA 0x000E2010
+#define DDRSS3_PHY_370_DATA 0x76543210
+#define DDRSS3_PHY_371_DATA 0x00000008
+#define DDRSS3_PHY_372_DATA 0x02800280
+#define DDRSS3_PHY_373_DATA 0x02800280
+#define DDRSS3_PHY_374_DATA 0x02800280
+#define DDRSS3_PHY_375_DATA 0x02800280
+#define DDRSS3_PHY_376_DATA 0x00000280
+#define DDRSS3_PHY_377_DATA 0x0000A000
+#define DDRSS3_PHY_378_DATA 0x00A000A0
+#define DDRSS3_PHY_379_DATA 0x00A000A0
+#define DDRSS3_PHY_380_DATA 0x00A000A0
+#define DDRSS3_PHY_381_DATA 0x00A000A0
+#define DDRSS3_PHY_382_DATA 0x00A000A0
+#define DDRSS3_PHY_383_DATA 0x00A000A0
+#define DDRSS3_PHY_384_DATA 0x00A000A0
+#define DDRSS3_PHY_385_DATA 0x00A000A0
+#define DDRSS3_PHY_386_DATA 0x01C200A0
+#define DDRSS3_PHY_387_DATA 0x01A00005
+#define DDRSS3_PHY_388_DATA 0x00000000
+#define DDRSS3_PHY_389_DATA 0x00000000
+#define DDRSS3_PHY_390_DATA 0x00080200
+#define DDRSS3_PHY_391_DATA 0x00000000
+#define DDRSS3_PHY_392_DATA 0x20202000
+#define DDRSS3_PHY_393_DATA 0x20202020
+#define DDRSS3_PHY_394_DATA 0xF0F02020
+#define DDRSS3_PHY_395_DATA 0x00000000
+#define DDRSS3_PHY_396_DATA 0x00000000
+#define DDRSS3_PHY_397_DATA 0x00000000
+#define DDRSS3_PHY_398_DATA 0x00000000
+#define DDRSS3_PHY_399_DATA 0x00000000
+#define DDRSS3_PHY_400_DATA 0x00000000
+#define DDRSS3_PHY_401_DATA 0x00000000
+#define DDRSS3_PHY_402_DATA 0x00000000
+#define DDRSS3_PHY_403_DATA 0x00000000
+#define DDRSS3_PHY_404_DATA 0x00000000
+#define DDRSS3_PHY_405_DATA 0x00000000
+#define DDRSS3_PHY_406_DATA 0x00000000
+#define DDRSS3_PHY_407_DATA 0x00000000
+#define DDRSS3_PHY_408_DATA 0x00000000
+#define DDRSS3_PHY_409_DATA 0x00000000
+#define DDRSS3_PHY_410_DATA 0x00000000
+#define DDRSS3_PHY_411_DATA 0x00000000
+#define DDRSS3_PHY_412_DATA 0x00000000
+#define DDRSS3_PHY_413_DATA 0x00000000
+#define DDRSS3_PHY_414_DATA 0x00000000
+#define DDRSS3_PHY_415_DATA 0x00000000
+#define DDRSS3_PHY_416_DATA 0x00000000
+#define DDRSS3_PHY_417_DATA 0x00000000
+#define DDRSS3_PHY_418_DATA 0x00000000
+#define DDRSS3_PHY_419_DATA 0x00000000
+#define DDRSS3_PHY_420_DATA 0x00000000
+#define DDRSS3_PHY_421_DATA 0x00000000
+#define DDRSS3_PHY_422_DATA 0x00000000
+#define DDRSS3_PHY_423_DATA 0x00000000
+#define DDRSS3_PHY_424_DATA 0x00000000
+#define DDRSS3_PHY_425_DATA 0x00000000
+#define DDRSS3_PHY_426_DATA 0x00000000
+#define DDRSS3_PHY_427_DATA 0x00000000
+#define DDRSS3_PHY_428_DATA 0x00000000
+#define DDRSS3_PHY_429_DATA 0x00000000
+#define DDRSS3_PHY_430_DATA 0x00000000
+#define DDRSS3_PHY_431_DATA 0x00000000
+#define DDRSS3_PHY_432_DATA 0x00000000
+#define DDRSS3_PHY_433_DATA 0x00000000
+#define DDRSS3_PHY_434_DATA 0x00000000
+#define DDRSS3_PHY_435_DATA 0x00000000
+#define DDRSS3_PHY_436_DATA 0x00000000
+#define DDRSS3_PHY_437_DATA 0x00000000
+#define DDRSS3_PHY_438_DATA 0x00000000
+#define DDRSS3_PHY_439_DATA 0x00000000
+#define DDRSS3_PHY_440_DATA 0x00000000
+#define DDRSS3_PHY_441_DATA 0x00000000
+#define DDRSS3_PHY_442_DATA 0x00000000
+#define DDRSS3_PHY_443_DATA 0x00000000
+#define DDRSS3_PHY_444_DATA 0x00000000
+#define DDRSS3_PHY_445_DATA 0x00000000
+#define DDRSS3_PHY_446_DATA 0x00000000
+#define DDRSS3_PHY_447_DATA 0x00000000
+#define DDRSS3_PHY_448_DATA 0x00000000
+#define DDRSS3_PHY_449_DATA 0x00000000
+#define DDRSS3_PHY_450_DATA 0x00000000
+#define DDRSS3_PHY_451_DATA 0x00000000
+#define DDRSS3_PHY_452_DATA 0x00000000
+#define DDRSS3_PHY_453_DATA 0x00000000
+#define DDRSS3_PHY_454_DATA 0x00000000
+#define DDRSS3_PHY_455_DATA 0x00000000
+#define DDRSS3_PHY_456_DATA 0x00000000
+#define DDRSS3_PHY_457_DATA 0x00000000
+#define DDRSS3_PHY_458_DATA 0x00000000
+#define DDRSS3_PHY_459_DATA 0x00000000
+#define DDRSS3_PHY_460_DATA 0x00000000
+#define DDRSS3_PHY_461_DATA 0x00000000
+#define DDRSS3_PHY_462_DATA 0x00000000
+#define DDRSS3_PHY_463_DATA 0x00000000
+#define DDRSS3_PHY_464_DATA 0x00000000
+#define DDRSS3_PHY_465_DATA 0x00000000
+#define DDRSS3_PHY_466_DATA 0x00000000
+#define DDRSS3_PHY_467_DATA 0x00000000
+#define DDRSS3_PHY_468_DATA 0x00000000
+#define DDRSS3_PHY_469_DATA 0x00000000
+#define DDRSS3_PHY_470_DATA 0x00000000
+#define DDRSS3_PHY_471_DATA 0x00000000
+#define DDRSS3_PHY_472_DATA 0x00000000
+#define DDRSS3_PHY_473_DATA 0x00000000
+#define DDRSS3_PHY_474_DATA 0x00000000
+#define DDRSS3_PHY_475_DATA 0x00000000
+#define DDRSS3_PHY_476_DATA 0x00000000
+#define DDRSS3_PHY_477_DATA 0x00000000
+#define DDRSS3_PHY_478_DATA 0x00000000
+#define DDRSS3_PHY_479_DATA 0x00000000
+#define DDRSS3_PHY_480_DATA 0x00000000
+#define DDRSS3_PHY_481_DATA 0x00000000
+#define DDRSS3_PHY_482_DATA 0x00000000
+#define DDRSS3_PHY_483_DATA 0x00000000
+#define DDRSS3_PHY_484_DATA 0x00000000
+#define DDRSS3_PHY_485_DATA 0x00000000
+#define DDRSS3_PHY_486_DATA 0x00000000
+#define DDRSS3_PHY_487_DATA 0x00000000
+#define DDRSS3_PHY_488_DATA 0x00000000
+#define DDRSS3_PHY_489_DATA 0x00000000
+#define DDRSS3_PHY_490_DATA 0x00000000
+#define DDRSS3_PHY_491_DATA 0x00000000
+#define DDRSS3_PHY_492_DATA 0x00000000
+#define DDRSS3_PHY_493_DATA 0x00000000
+#define DDRSS3_PHY_494_DATA 0x00000000
+#define DDRSS3_PHY_495_DATA 0x00000000
+#define DDRSS3_PHY_496_DATA 0x00000000
+#define DDRSS3_PHY_497_DATA 0x00000000
+#define DDRSS3_PHY_498_DATA 0x00000000
+#define DDRSS3_PHY_499_DATA 0x00000000
+#define DDRSS3_PHY_500_DATA 0x00000000
+#define DDRSS3_PHY_501_DATA 0x00000000
+#define DDRSS3_PHY_502_DATA 0x00000000
+#define DDRSS3_PHY_503_DATA 0x00000000
+#define DDRSS3_PHY_504_DATA 0x00000000
+#define DDRSS3_PHY_505_DATA 0x00000000
+#define DDRSS3_PHY_506_DATA 0x00000000
+#define DDRSS3_PHY_507_DATA 0x00000000
+#define DDRSS3_PHY_508_DATA 0x00000000
+#define DDRSS3_PHY_509_DATA 0x00000000
+#define DDRSS3_PHY_510_DATA 0x00000000
+#define DDRSS3_PHY_511_DATA 0x00000000
+#define DDRSS3_PHY_512_DATA 0x000004F0
+#define DDRSS3_PHY_513_DATA 0x00000000
+#define DDRSS3_PHY_514_DATA 0x00030200
+#define DDRSS3_PHY_515_DATA 0x00000000
+#define DDRSS3_PHY_516_DATA 0x00000000
+#define DDRSS3_PHY_517_DATA 0x01030000
+#define DDRSS3_PHY_518_DATA 0x00010000
+#define DDRSS3_PHY_519_DATA 0x01030004
+#define DDRSS3_PHY_520_DATA 0x01000000
+#define DDRSS3_PHY_521_DATA 0x00000000
+#define DDRSS3_PHY_522_DATA 0x00000000
+#define DDRSS3_PHY_523_DATA 0x01000001
+#define DDRSS3_PHY_524_DATA 0x00000100
+#define DDRSS3_PHY_525_DATA 0x000800C0
+#define DDRSS3_PHY_526_DATA 0x060100CC
+#define DDRSS3_PHY_527_DATA 0x00030066
+#define DDRSS3_PHY_528_DATA 0x00000000
+#define DDRSS3_PHY_529_DATA 0x00000301
+#define DDRSS3_PHY_530_DATA 0x0000AAAA
+#define DDRSS3_PHY_531_DATA 0x00005555
+#define DDRSS3_PHY_532_DATA 0x0000B5B5
+#define DDRSS3_PHY_533_DATA 0x00004A4A
+#define DDRSS3_PHY_534_DATA 0x00005656
+#define DDRSS3_PHY_535_DATA 0x0000A9A9
+#define DDRSS3_PHY_536_DATA 0x0000A9A9
+#define DDRSS3_PHY_537_DATA 0x0000B5B5
+#define DDRSS3_PHY_538_DATA 0x00000000
+#define DDRSS3_PHY_539_DATA 0x00000000
+#define DDRSS3_PHY_540_DATA 0x2A000000
+#define DDRSS3_PHY_541_DATA 0x00000808
+#define DDRSS3_PHY_542_DATA 0x0F000000
+#define DDRSS3_PHY_543_DATA 0x00000F0F
+#define DDRSS3_PHY_544_DATA 0x10400000
+#define DDRSS3_PHY_545_DATA 0x0C002006
+#define DDRSS3_PHY_546_DATA 0x00000000
+#define DDRSS3_PHY_547_DATA 0x00000000
+#define DDRSS3_PHY_548_DATA 0x55555555
+#define DDRSS3_PHY_549_DATA 0xAAAAAAAA
+#define DDRSS3_PHY_550_DATA 0x55555555
+#define DDRSS3_PHY_551_DATA 0xAAAAAAAA
+#define DDRSS3_PHY_552_DATA 0x00005555
+#define DDRSS3_PHY_553_DATA 0x01000100
+#define DDRSS3_PHY_554_DATA 0x00800180
+#define DDRSS3_PHY_555_DATA 0x00000001
+#define DDRSS3_PHY_556_DATA 0x00000000
+#define DDRSS3_PHY_557_DATA 0x00000000
+#define DDRSS3_PHY_558_DATA 0x00000000
+#define DDRSS3_PHY_559_DATA 0x00000000
+#define DDRSS3_PHY_560_DATA 0x00000000
+#define DDRSS3_PHY_561_DATA 0x00000000
+#define DDRSS3_PHY_562_DATA 0x00000000
+#define DDRSS3_PHY_563_DATA 0x00000000
+#define DDRSS3_PHY_564_DATA 0x00000000
+#define DDRSS3_PHY_565_DATA 0x00000000
+#define DDRSS3_PHY_566_DATA 0x00000000
+#define DDRSS3_PHY_567_DATA 0x00000000
+#define DDRSS3_PHY_568_DATA 0x00000000
+#define DDRSS3_PHY_569_DATA 0x00000000
+#define DDRSS3_PHY_570_DATA 0x00000000
+#define DDRSS3_PHY_571_DATA 0x00000000
+#define DDRSS3_PHY_572_DATA 0x00000000
+#define DDRSS3_PHY_573_DATA 0x00000000
+#define DDRSS3_PHY_574_DATA 0x00000000
+#define DDRSS3_PHY_575_DATA 0x00000000
+#define DDRSS3_PHY_576_DATA 0x00000000
+#define DDRSS3_PHY_577_DATA 0x00000000
+#define DDRSS3_PHY_578_DATA 0x00000104
+#define DDRSS3_PHY_579_DATA 0x00000120
+#define DDRSS3_PHY_580_DATA 0x00000000
+#define DDRSS3_PHY_581_DATA 0x00000000
+#define DDRSS3_PHY_582_DATA 0x00000000
+#define DDRSS3_PHY_583_DATA 0x00000000
+#define DDRSS3_PHY_584_DATA 0x00000000
+#define DDRSS3_PHY_585_DATA 0x00000000
+#define DDRSS3_PHY_586_DATA 0x00000000
+#define DDRSS3_PHY_587_DATA 0x00000001
+#define DDRSS3_PHY_588_DATA 0x07FF0000
+#define DDRSS3_PHY_589_DATA 0x0080081F
+#define DDRSS3_PHY_590_DATA 0x00081020
+#define DDRSS3_PHY_591_DATA 0x04010000
+#define DDRSS3_PHY_592_DATA 0x00000000
+#define DDRSS3_PHY_593_DATA 0x00000000
+#define DDRSS3_PHY_594_DATA 0x00000000
+#define DDRSS3_PHY_595_DATA 0x00000100
+#define DDRSS3_PHY_596_DATA 0x01CC0C01
+#define DDRSS3_PHY_597_DATA 0x1003CC0C
+#define DDRSS3_PHY_598_DATA 0x20000140
+#define DDRSS3_PHY_599_DATA 0x07FF0200
+#define DDRSS3_PHY_600_DATA 0x0000DD01
+#define DDRSS3_PHY_601_DATA 0x10100303
+#define DDRSS3_PHY_602_DATA 0x10101010
+#define DDRSS3_PHY_603_DATA 0x10101010
+#define DDRSS3_PHY_604_DATA 0x00021010
+#define DDRSS3_PHY_605_DATA 0x00100010
+#define DDRSS3_PHY_606_DATA 0x00100010
+#define DDRSS3_PHY_607_DATA 0x00100010
+#define DDRSS3_PHY_608_DATA 0x00100010
+#define DDRSS3_PHY_609_DATA 0x00050010
+#define DDRSS3_PHY_610_DATA 0x51517041
+#define DDRSS3_PHY_611_DATA 0x31C06001
+#define DDRSS3_PHY_612_DATA 0x07AB0340
+#define DDRSS3_PHY_613_DATA 0x00C0C001
+#define DDRSS3_PHY_614_DATA 0x0E0D0001
+#define DDRSS3_PHY_615_DATA 0x10001000
+#define DDRSS3_PHY_616_DATA 0x0C083E42
+#define DDRSS3_PHY_617_DATA 0x0F0C3701
+#define DDRSS3_PHY_618_DATA 0x01000140
+#define DDRSS3_PHY_619_DATA 0x0C000420
+#define DDRSS3_PHY_620_DATA 0x00000198
+#define DDRSS3_PHY_621_DATA 0x0A0000D0
+#define DDRSS3_PHY_622_DATA 0x00030200
+#define DDRSS3_PHY_623_DATA 0x02800000
+#define DDRSS3_PHY_624_DATA 0x80800000
+#define DDRSS3_PHY_625_DATA 0x000E2010
+#define DDRSS3_PHY_626_DATA 0x76543210
+#define DDRSS3_PHY_627_DATA 0x00000008
+#define DDRSS3_PHY_628_DATA 0x02800280
+#define DDRSS3_PHY_629_DATA 0x02800280
+#define DDRSS3_PHY_630_DATA 0x02800280
+#define DDRSS3_PHY_631_DATA 0x02800280
+#define DDRSS3_PHY_632_DATA 0x00000280
+#define DDRSS3_PHY_633_DATA 0x0000A000
+#define DDRSS3_PHY_634_DATA 0x00A000A0
+#define DDRSS3_PHY_635_DATA 0x00A000A0
+#define DDRSS3_PHY_636_DATA 0x00A000A0
+#define DDRSS3_PHY_637_DATA 0x00A000A0
+#define DDRSS3_PHY_638_DATA 0x00A000A0
+#define DDRSS3_PHY_639_DATA 0x00A000A0
+#define DDRSS3_PHY_640_DATA 0x00A000A0
+#define DDRSS3_PHY_641_DATA 0x00A000A0
+#define DDRSS3_PHY_642_DATA 0x01C200A0
+#define DDRSS3_PHY_643_DATA 0x01A00005
+#define DDRSS3_PHY_644_DATA 0x00000000
+#define DDRSS3_PHY_645_DATA 0x00000000
+#define DDRSS3_PHY_646_DATA 0x00080200
+#define DDRSS3_PHY_647_DATA 0x00000000
+#define DDRSS3_PHY_648_DATA 0x20202000
+#define DDRSS3_PHY_649_DATA 0x20202020
+#define DDRSS3_PHY_650_DATA 0xF0F02020
+#define DDRSS3_PHY_651_DATA 0x00000000
+#define DDRSS3_PHY_652_DATA 0x00000000
+#define DDRSS3_PHY_653_DATA 0x00000000
+#define DDRSS3_PHY_654_DATA 0x00000000
+#define DDRSS3_PHY_655_DATA 0x00000000
+#define DDRSS3_PHY_656_DATA 0x00000000
+#define DDRSS3_PHY_657_DATA 0x00000000
+#define DDRSS3_PHY_658_DATA 0x00000000
+#define DDRSS3_PHY_659_DATA 0x00000000
+#define DDRSS3_PHY_660_DATA 0x00000000
+#define DDRSS3_PHY_661_DATA 0x00000000
+#define DDRSS3_PHY_662_DATA 0x00000000
+#define DDRSS3_PHY_663_DATA 0x00000000
+#define DDRSS3_PHY_664_DATA 0x00000000
+#define DDRSS3_PHY_665_DATA 0x00000000
+#define DDRSS3_PHY_666_DATA 0x00000000
+#define DDRSS3_PHY_667_DATA 0x00000000
+#define DDRSS3_PHY_668_DATA 0x00000000
+#define DDRSS3_PHY_669_DATA 0x00000000
+#define DDRSS3_PHY_670_DATA 0x00000000
+#define DDRSS3_PHY_671_DATA 0x00000000
+#define DDRSS3_PHY_672_DATA 0x00000000
+#define DDRSS3_PHY_673_DATA 0x00000000
+#define DDRSS3_PHY_674_DATA 0x00000000
+#define DDRSS3_PHY_675_DATA 0x00000000
+#define DDRSS3_PHY_676_DATA 0x00000000
+#define DDRSS3_PHY_677_DATA 0x00000000
+#define DDRSS3_PHY_678_DATA 0x00000000
+#define DDRSS3_PHY_679_DATA 0x00000000
+#define DDRSS3_PHY_680_DATA 0x00000000
+#define DDRSS3_PHY_681_DATA 0x00000000
+#define DDRSS3_PHY_682_DATA 0x00000000
+#define DDRSS3_PHY_683_DATA 0x00000000
+#define DDRSS3_PHY_684_DATA 0x00000000
+#define DDRSS3_PHY_685_DATA 0x00000000
+#define DDRSS3_PHY_686_DATA 0x00000000
+#define DDRSS3_PHY_687_DATA 0x00000000
+#define DDRSS3_PHY_688_DATA 0x00000000
+#define DDRSS3_PHY_689_DATA 0x00000000
+#define DDRSS3_PHY_690_DATA 0x00000000
+#define DDRSS3_PHY_691_DATA 0x00000000
+#define DDRSS3_PHY_692_DATA 0x00000000
+#define DDRSS3_PHY_693_DATA 0x00000000
+#define DDRSS3_PHY_694_DATA 0x00000000
+#define DDRSS3_PHY_695_DATA 0x00000000
+#define DDRSS3_PHY_696_DATA 0x00000000
+#define DDRSS3_PHY_697_DATA 0x00000000
+#define DDRSS3_PHY_698_DATA 0x00000000
+#define DDRSS3_PHY_699_DATA 0x00000000
+#define DDRSS3_PHY_700_DATA 0x00000000
+#define DDRSS3_PHY_701_DATA 0x00000000
+#define DDRSS3_PHY_702_DATA 0x00000000
+#define DDRSS3_PHY_703_DATA 0x00000000
+#define DDRSS3_PHY_704_DATA 0x00000000
+#define DDRSS3_PHY_705_DATA 0x00000000
+#define DDRSS3_PHY_706_DATA 0x00000000
+#define DDRSS3_PHY_707_DATA 0x00000000
+#define DDRSS3_PHY_708_DATA 0x00000000
+#define DDRSS3_PHY_709_DATA 0x00000000
+#define DDRSS3_PHY_710_DATA 0x00000000
+#define DDRSS3_PHY_711_DATA 0x00000000
+#define DDRSS3_PHY_712_DATA 0x00000000
+#define DDRSS3_PHY_713_DATA 0x00000000
+#define DDRSS3_PHY_714_DATA 0x00000000
+#define DDRSS3_PHY_715_DATA 0x00000000
+#define DDRSS3_PHY_716_DATA 0x00000000
+#define DDRSS3_PHY_717_DATA 0x00000000
+#define DDRSS3_PHY_718_DATA 0x00000000
+#define DDRSS3_PHY_719_DATA 0x00000000
+#define DDRSS3_PHY_720_DATA 0x00000000
+#define DDRSS3_PHY_721_DATA 0x00000000
+#define DDRSS3_PHY_722_DATA 0x00000000
+#define DDRSS3_PHY_723_DATA 0x00000000
+#define DDRSS3_PHY_724_DATA 0x00000000
+#define DDRSS3_PHY_725_DATA 0x00000000
+#define DDRSS3_PHY_726_DATA 0x00000000
+#define DDRSS3_PHY_727_DATA 0x00000000
+#define DDRSS3_PHY_728_DATA 0x00000000
+#define DDRSS3_PHY_729_DATA 0x00000000
+#define DDRSS3_PHY_730_DATA 0x00000000
+#define DDRSS3_PHY_731_DATA 0x00000000
+#define DDRSS3_PHY_732_DATA 0x00000000
+#define DDRSS3_PHY_733_DATA 0x00000000
+#define DDRSS3_PHY_734_DATA 0x00000000
+#define DDRSS3_PHY_735_DATA 0x00000000
+#define DDRSS3_PHY_736_DATA 0x00000000
+#define DDRSS3_PHY_737_DATA 0x00000000
+#define DDRSS3_PHY_738_DATA 0x00000000
+#define DDRSS3_PHY_739_DATA 0x00000000
+#define DDRSS3_PHY_740_DATA 0x00000000
+#define DDRSS3_PHY_741_DATA 0x00000000
+#define DDRSS3_PHY_742_DATA 0x00000000
+#define DDRSS3_PHY_743_DATA 0x00000000
+#define DDRSS3_PHY_744_DATA 0x00000000
+#define DDRSS3_PHY_745_DATA 0x00000000
+#define DDRSS3_PHY_746_DATA 0x00000000
+#define DDRSS3_PHY_747_DATA 0x00000000
+#define DDRSS3_PHY_748_DATA 0x00000000
+#define DDRSS3_PHY_749_DATA 0x00000000
+#define DDRSS3_PHY_750_DATA 0x00000000
+#define DDRSS3_PHY_751_DATA 0x00000000
+#define DDRSS3_PHY_752_DATA 0x00000000
+#define DDRSS3_PHY_753_DATA 0x00000000
+#define DDRSS3_PHY_754_DATA 0x00000000
+#define DDRSS3_PHY_755_DATA 0x00000000
+#define DDRSS3_PHY_756_DATA 0x00000000
+#define DDRSS3_PHY_757_DATA 0x00000000
+#define DDRSS3_PHY_758_DATA 0x00000000
+#define DDRSS3_PHY_759_DATA 0x00000000
+#define DDRSS3_PHY_760_DATA 0x00000000
+#define DDRSS3_PHY_761_DATA 0x00000000
+#define DDRSS3_PHY_762_DATA 0x00000000
+#define DDRSS3_PHY_763_DATA 0x00000000
+#define DDRSS3_PHY_764_DATA 0x00000000
+#define DDRSS3_PHY_765_DATA 0x00000000
+#define DDRSS3_PHY_766_DATA 0x00000000
+#define DDRSS3_PHY_767_DATA 0x00000000
+#define DDRSS3_PHY_768_DATA 0x000004F0
+#define DDRSS3_PHY_769_DATA 0x00000000
+#define DDRSS3_PHY_770_DATA 0x00030200
+#define DDRSS3_PHY_771_DATA 0x00000000
+#define DDRSS3_PHY_772_DATA 0x00000000
+#define DDRSS3_PHY_773_DATA 0x01030000
+#define DDRSS3_PHY_774_DATA 0x00010000
+#define DDRSS3_PHY_775_DATA 0x01030004
+#define DDRSS3_PHY_776_DATA 0x01000000
+#define DDRSS3_PHY_777_DATA 0x00000000
+#define DDRSS3_PHY_778_DATA 0x00000000
+#define DDRSS3_PHY_779_DATA 0x01000001
+#define DDRSS3_PHY_780_DATA 0x00000100
+#define DDRSS3_PHY_781_DATA 0x000800C0
+#define DDRSS3_PHY_782_DATA 0x060100CC
+#define DDRSS3_PHY_783_DATA 0x00030066
+#define DDRSS3_PHY_784_DATA 0x00000000
+#define DDRSS3_PHY_785_DATA 0x00000301
+#define DDRSS3_PHY_786_DATA 0x0000AAAA
+#define DDRSS3_PHY_787_DATA 0x00005555
+#define DDRSS3_PHY_788_DATA 0x0000B5B5
+#define DDRSS3_PHY_789_DATA 0x00004A4A
+#define DDRSS3_PHY_790_DATA 0x00005656
+#define DDRSS3_PHY_791_DATA 0x0000A9A9
+#define DDRSS3_PHY_792_DATA 0x0000A9A9
+#define DDRSS3_PHY_793_DATA 0x0000B5B5
+#define DDRSS3_PHY_794_DATA 0x00000000
+#define DDRSS3_PHY_795_DATA 0x00000000
+#define DDRSS3_PHY_796_DATA 0x2A000000
+#define DDRSS3_PHY_797_DATA 0x00000808
+#define DDRSS3_PHY_798_DATA 0x0F000000
+#define DDRSS3_PHY_799_DATA 0x00000F0F
+#define DDRSS3_PHY_800_DATA 0x10400000
+#define DDRSS3_PHY_801_DATA 0x0C002006
+#define DDRSS3_PHY_802_DATA 0x00000000
+#define DDRSS3_PHY_803_DATA 0x00000000
+#define DDRSS3_PHY_804_DATA 0x55555555
+#define DDRSS3_PHY_805_DATA 0xAAAAAAAA
+#define DDRSS3_PHY_806_DATA 0x55555555
+#define DDRSS3_PHY_807_DATA 0xAAAAAAAA
+#define DDRSS3_PHY_808_DATA 0x00005555
+#define DDRSS3_PHY_809_DATA 0x01000100
+#define DDRSS3_PHY_810_DATA 0x00800180
+#define DDRSS3_PHY_811_DATA 0x00000000
+#define DDRSS3_PHY_812_DATA 0x00000000
+#define DDRSS3_PHY_813_DATA 0x00000000
+#define DDRSS3_PHY_814_DATA 0x00000000
+#define DDRSS3_PHY_815_DATA 0x00000000
+#define DDRSS3_PHY_816_DATA 0x00000000
+#define DDRSS3_PHY_817_DATA 0x00000000
+#define DDRSS3_PHY_818_DATA 0x00000000
+#define DDRSS3_PHY_819_DATA 0x00000000
+#define DDRSS3_PHY_820_DATA 0x00000000
+#define DDRSS3_PHY_821_DATA 0x00000000
+#define DDRSS3_PHY_822_DATA 0x00000000
+#define DDRSS3_PHY_823_DATA 0x00000000
+#define DDRSS3_PHY_824_DATA 0x00000000
+#define DDRSS3_PHY_825_DATA 0x00000000
+#define DDRSS3_PHY_826_DATA 0x00000000
+#define DDRSS3_PHY_827_DATA 0x00000000
+#define DDRSS3_PHY_828_DATA 0x00000000
+#define DDRSS3_PHY_829_DATA 0x00000000
+#define DDRSS3_PHY_830_DATA 0x00000000
+#define DDRSS3_PHY_831_DATA 0x00000000
+#define DDRSS3_PHY_832_DATA 0x00000000
+#define DDRSS3_PHY_833_DATA 0x00000000
+#define DDRSS3_PHY_834_DATA 0x00000104
+#define DDRSS3_PHY_835_DATA 0x00000120
+#define DDRSS3_PHY_836_DATA 0x00000000
+#define DDRSS3_PHY_837_DATA 0x00000000
+#define DDRSS3_PHY_838_DATA 0x00000000
+#define DDRSS3_PHY_839_DATA 0x00000000
+#define DDRSS3_PHY_840_DATA 0x00000000
+#define DDRSS3_PHY_841_DATA 0x00000000
+#define DDRSS3_PHY_842_DATA 0x00000000
+#define DDRSS3_PHY_843_DATA 0x00000001
+#define DDRSS3_PHY_844_DATA 0x07FF0000
+#define DDRSS3_PHY_845_DATA 0x0080081F
+#define DDRSS3_PHY_846_DATA 0x00081020
+#define DDRSS3_PHY_847_DATA 0x04010000
+#define DDRSS3_PHY_848_DATA 0x00000000
+#define DDRSS3_PHY_849_DATA 0x00000000
+#define DDRSS3_PHY_850_DATA 0x00000000
+#define DDRSS3_PHY_851_DATA 0x00000100
+#define DDRSS3_PHY_852_DATA 0x01CC0C01
+#define DDRSS3_PHY_853_DATA 0x1003CC0C
+#define DDRSS3_PHY_854_DATA 0x20000140
+#define DDRSS3_PHY_855_DATA 0x07FF0200
+#define DDRSS3_PHY_856_DATA 0x0000DD01
+#define DDRSS3_PHY_857_DATA 0x10100303
+#define DDRSS3_PHY_858_DATA 0x10101010
+#define DDRSS3_PHY_859_DATA 0x10101010
+#define DDRSS3_PHY_860_DATA 0x00021010
+#define DDRSS3_PHY_861_DATA 0x00100010
+#define DDRSS3_PHY_862_DATA 0x00100010
+#define DDRSS3_PHY_863_DATA 0x00100010
+#define DDRSS3_PHY_864_DATA 0x00100010
+#define DDRSS3_PHY_865_DATA 0x00050010
+#define DDRSS3_PHY_866_DATA 0x51517041
+#define DDRSS3_PHY_867_DATA 0x31C06001
+#define DDRSS3_PHY_868_DATA 0x07AB0340
+#define DDRSS3_PHY_869_DATA 0x00C0C001
+#define DDRSS3_PHY_870_DATA 0x0E0D0001
+#define DDRSS3_PHY_871_DATA 0x10001000
+#define DDRSS3_PHY_872_DATA 0x0C083E42
+#define DDRSS3_PHY_873_DATA 0x0F0C3701
+#define DDRSS3_PHY_874_DATA 0x01000140
+#define DDRSS3_PHY_875_DATA 0x0C000420
+#define DDRSS3_PHY_876_DATA 0x00000198
+#define DDRSS3_PHY_877_DATA 0x0A0000D0
+#define DDRSS3_PHY_878_DATA 0x00030200
+#define DDRSS3_PHY_879_DATA 0x02800000
+#define DDRSS3_PHY_880_DATA 0x80800000
+#define DDRSS3_PHY_881_DATA 0x000E2010
+#define DDRSS3_PHY_882_DATA 0x76543210
+#define DDRSS3_PHY_883_DATA 0x00000008
+#define DDRSS3_PHY_884_DATA 0x02800280
+#define DDRSS3_PHY_885_DATA 0x02800280
+#define DDRSS3_PHY_886_DATA 0x02800280
+#define DDRSS3_PHY_887_DATA 0x02800280
+#define DDRSS3_PHY_888_DATA 0x00000280
+#define DDRSS3_PHY_889_DATA 0x0000A000
+#define DDRSS3_PHY_890_DATA 0x00A000A0
+#define DDRSS3_PHY_891_DATA 0x00A000A0
+#define DDRSS3_PHY_892_DATA 0x00A000A0
+#define DDRSS3_PHY_893_DATA 0x00A000A0
+#define DDRSS3_PHY_894_DATA 0x00A000A0
+#define DDRSS3_PHY_895_DATA 0x00A000A0
+#define DDRSS3_PHY_896_DATA 0x00A000A0
+#define DDRSS3_PHY_897_DATA 0x00A000A0
+#define DDRSS3_PHY_898_DATA 0x01C200A0
+#define DDRSS3_PHY_899_DATA 0x01A00005
+#define DDRSS3_PHY_900_DATA 0x00000000
+#define DDRSS3_PHY_901_DATA 0x00000000
+#define DDRSS3_PHY_902_DATA 0x00080200
+#define DDRSS3_PHY_903_DATA 0x00000000
+#define DDRSS3_PHY_904_DATA 0x20202000
+#define DDRSS3_PHY_905_DATA 0x20202020
+#define DDRSS3_PHY_906_DATA 0xF0F02020
+#define DDRSS3_PHY_907_DATA 0x00000000
+#define DDRSS3_PHY_908_DATA 0x00000000
+#define DDRSS3_PHY_909_DATA 0x00000000
+#define DDRSS3_PHY_910_DATA 0x00000000
+#define DDRSS3_PHY_911_DATA 0x00000000
+#define DDRSS3_PHY_912_DATA 0x00000000
+#define DDRSS3_PHY_913_DATA 0x00000000
+#define DDRSS3_PHY_914_DATA 0x00000000
+#define DDRSS3_PHY_915_DATA 0x00000000
+#define DDRSS3_PHY_916_DATA 0x00000000
+#define DDRSS3_PHY_917_DATA 0x00000000
+#define DDRSS3_PHY_918_DATA 0x00000000
+#define DDRSS3_PHY_919_DATA 0x00000000
+#define DDRSS3_PHY_920_DATA 0x00000000
+#define DDRSS3_PHY_921_DATA 0x00000000
+#define DDRSS3_PHY_922_DATA 0x00000000
+#define DDRSS3_PHY_923_DATA 0x00000000
+#define DDRSS3_PHY_924_DATA 0x00000000
+#define DDRSS3_PHY_925_DATA 0x00000000
+#define DDRSS3_PHY_926_DATA 0x00000000
+#define DDRSS3_PHY_927_DATA 0x00000000
+#define DDRSS3_PHY_928_DATA 0x00000000
+#define DDRSS3_PHY_929_DATA 0x00000000
+#define DDRSS3_PHY_930_DATA 0x00000000
+#define DDRSS3_PHY_931_DATA 0x00000000
+#define DDRSS3_PHY_932_DATA 0x00000000
+#define DDRSS3_PHY_933_DATA 0x00000000
+#define DDRSS3_PHY_934_DATA 0x00000000
+#define DDRSS3_PHY_935_DATA 0x00000000
+#define DDRSS3_PHY_936_DATA 0x00000000
+#define DDRSS3_PHY_937_DATA 0x00000000
+#define DDRSS3_PHY_938_DATA 0x00000000
+#define DDRSS3_PHY_939_DATA 0x00000000
+#define DDRSS3_PHY_940_DATA 0x00000000
+#define DDRSS3_PHY_941_DATA 0x00000000
+#define DDRSS3_PHY_942_DATA 0x00000000
+#define DDRSS3_PHY_943_DATA 0x00000000
+#define DDRSS3_PHY_944_DATA 0x00000000
+#define DDRSS3_PHY_945_DATA 0x00000000
+#define DDRSS3_PHY_946_DATA 0x00000000
+#define DDRSS3_PHY_947_DATA 0x00000000
+#define DDRSS3_PHY_948_DATA 0x00000000
+#define DDRSS3_PHY_949_DATA 0x00000000
+#define DDRSS3_PHY_950_DATA 0x00000000
+#define DDRSS3_PHY_951_DATA 0x00000000
+#define DDRSS3_PHY_952_DATA 0x00000000
+#define DDRSS3_PHY_953_DATA 0x00000000
+#define DDRSS3_PHY_954_DATA 0x00000000
+#define DDRSS3_PHY_955_DATA 0x00000000
+#define DDRSS3_PHY_956_DATA 0x00000000
+#define DDRSS3_PHY_957_DATA 0x00000000
+#define DDRSS3_PHY_958_DATA 0x00000000
+#define DDRSS3_PHY_959_DATA 0x00000000
+#define DDRSS3_PHY_960_DATA 0x00000000
+#define DDRSS3_PHY_961_DATA 0x00000000
+#define DDRSS3_PHY_962_DATA 0x00000000
+#define DDRSS3_PHY_963_DATA 0x00000000
+#define DDRSS3_PHY_964_DATA 0x00000000
+#define DDRSS3_PHY_965_DATA 0x00000000
+#define DDRSS3_PHY_966_DATA 0x00000000
+#define DDRSS3_PHY_967_DATA 0x00000000
+#define DDRSS3_PHY_968_DATA 0x00000000
+#define DDRSS3_PHY_969_DATA 0x00000000
+#define DDRSS3_PHY_970_DATA 0x00000000
+#define DDRSS3_PHY_971_DATA 0x00000000
+#define DDRSS3_PHY_972_DATA 0x00000000
+#define DDRSS3_PHY_973_DATA 0x00000000
+#define DDRSS3_PHY_974_DATA 0x00000000
+#define DDRSS3_PHY_975_DATA 0x00000000
+#define DDRSS3_PHY_976_DATA 0x00000000
+#define DDRSS3_PHY_977_DATA 0x00000000
+#define DDRSS3_PHY_978_DATA 0x00000000
+#define DDRSS3_PHY_979_DATA 0x00000000
+#define DDRSS3_PHY_980_DATA 0x00000000
+#define DDRSS3_PHY_981_DATA 0x00000000
+#define DDRSS3_PHY_982_DATA 0x00000000
+#define DDRSS3_PHY_983_DATA 0x00000000
+#define DDRSS3_PHY_984_DATA 0x00000000
+#define DDRSS3_PHY_985_DATA 0x00000000
+#define DDRSS3_PHY_986_DATA 0x00000000
+#define DDRSS3_PHY_987_DATA 0x00000000
+#define DDRSS3_PHY_988_DATA 0x00000000
+#define DDRSS3_PHY_989_DATA 0x00000000
+#define DDRSS3_PHY_990_DATA 0x00000000
+#define DDRSS3_PHY_991_DATA 0x00000000
+#define DDRSS3_PHY_992_DATA 0x00000000
+#define DDRSS3_PHY_993_DATA 0x00000000
+#define DDRSS3_PHY_994_DATA 0x00000000
+#define DDRSS3_PHY_995_DATA 0x00000000
+#define DDRSS3_PHY_996_DATA 0x00000000
+#define DDRSS3_PHY_997_DATA 0x00000000
+#define DDRSS3_PHY_998_DATA 0x00000000
+#define DDRSS3_PHY_999_DATA 0x00000000
+#define DDRSS3_PHY_1000_DATA 0x00000000
+#define DDRSS3_PHY_1001_DATA 0x00000000
+#define DDRSS3_PHY_1002_DATA 0x00000000
+#define DDRSS3_PHY_1003_DATA 0x00000000
+#define DDRSS3_PHY_1004_DATA 0x00000000
+#define DDRSS3_PHY_1005_DATA 0x00000000
+#define DDRSS3_PHY_1006_DATA 0x00000000
+#define DDRSS3_PHY_1007_DATA 0x00000000
+#define DDRSS3_PHY_1008_DATA 0x00000000
+#define DDRSS3_PHY_1009_DATA 0x00000000
+#define DDRSS3_PHY_1010_DATA 0x00000000
+#define DDRSS3_PHY_1011_DATA 0x00000000
+#define DDRSS3_PHY_1012_DATA 0x00000000
+#define DDRSS3_PHY_1013_DATA 0x00000000
+#define DDRSS3_PHY_1014_DATA 0x00000000
+#define DDRSS3_PHY_1015_DATA 0x00000000
+#define DDRSS3_PHY_1016_DATA 0x00000000
+#define DDRSS3_PHY_1017_DATA 0x00000000
+#define DDRSS3_PHY_1018_DATA 0x00000000
+#define DDRSS3_PHY_1019_DATA 0x00000000
+#define DDRSS3_PHY_1020_DATA 0x00000000
+#define DDRSS3_PHY_1021_DATA 0x00000000
+#define DDRSS3_PHY_1022_DATA 0x00000000
+#define DDRSS3_PHY_1023_DATA 0x00000000
+#define DDRSS3_PHY_1024_DATA 0x00000000
+#define DDRSS3_PHY_1025_DATA 0x00000000
+#define DDRSS3_PHY_1026_DATA 0x00000000
+#define DDRSS3_PHY_1027_DATA 0x00000000
+#define DDRSS3_PHY_1028_DATA 0x00000000
+#define DDRSS3_PHY_1029_DATA 0x00000100
+#define DDRSS3_PHY_1030_DATA 0x00000200
+#define DDRSS3_PHY_1031_DATA 0x00000000
+#define DDRSS3_PHY_1032_DATA 0x00000000
+#define DDRSS3_PHY_1033_DATA 0x00000000
+#define DDRSS3_PHY_1034_DATA 0x00000000
+#define DDRSS3_PHY_1035_DATA 0x00400000
+#define DDRSS3_PHY_1036_DATA 0x00000080
+#define DDRSS3_PHY_1037_DATA 0x00DCBA98
+#define DDRSS3_PHY_1038_DATA 0x03000000
+#define DDRSS3_PHY_1039_DATA 0x00200000
+#define DDRSS3_PHY_1040_DATA 0x00000000
+#define DDRSS3_PHY_1041_DATA 0x00000000
+#define DDRSS3_PHY_1042_DATA 0x00000000
+#define DDRSS3_PHY_1043_DATA 0x00000000
+#define DDRSS3_PHY_1044_DATA 0x00000000
+#define DDRSS3_PHY_1045_DATA 0x0000002A
+#define DDRSS3_PHY_1046_DATA 0x00000015
+#define DDRSS3_PHY_1047_DATA 0x00000015
+#define DDRSS3_PHY_1048_DATA 0x0000002A
+#define DDRSS3_PHY_1049_DATA 0x00000033
+#define DDRSS3_PHY_1050_DATA 0x0000000C
+#define DDRSS3_PHY_1051_DATA 0x0000000C
+#define DDRSS3_PHY_1052_DATA 0x00000033
+#define DDRSS3_PHY_1053_DATA 0x00543210
+#define DDRSS3_PHY_1054_DATA 0x003F0000
+#define DDRSS3_PHY_1055_DATA 0x000F013F
+#define DDRSS3_PHY_1056_DATA 0x20202003
+#define DDRSS3_PHY_1057_DATA 0x00202020
+#define DDRSS3_PHY_1058_DATA 0x20008008
+#define DDRSS3_PHY_1059_DATA 0x00000810
+#define DDRSS3_PHY_1060_DATA 0x00000F00
+#define DDRSS3_PHY_1061_DATA 0x00000000
+#define DDRSS3_PHY_1062_DATA 0x00000000
+#define DDRSS3_PHY_1063_DATA 0x00000000
+#define DDRSS3_PHY_1064_DATA 0x000305CC
+#define DDRSS3_PHY_1065_DATA 0x00030000
+#define DDRSS3_PHY_1066_DATA 0x00000300
+#define DDRSS3_PHY_1067_DATA 0x00000300
+#define DDRSS3_PHY_1068_DATA 0x00000300
+#define DDRSS3_PHY_1069_DATA 0x00000300
+#define DDRSS3_PHY_1070_DATA 0x00000300
+#define DDRSS3_PHY_1071_DATA 0x42080010
+#define DDRSS3_PHY_1072_DATA 0x0000803E
+#define DDRSS3_PHY_1073_DATA 0x00000001
+#define DDRSS3_PHY_1074_DATA 0x01000102
+#define DDRSS3_PHY_1075_DATA 0x00008000
+#define DDRSS3_PHY_1076_DATA 0x00000000
+#define DDRSS3_PHY_1077_DATA 0x00000000
+#define DDRSS3_PHY_1078_DATA 0x00000000
+#define DDRSS3_PHY_1079_DATA 0x00000000
+#define DDRSS3_PHY_1080_DATA 0x00000000
+#define DDRSS3_PHY_1081_DATA 0x00000000
+#define DDRSS3_PHY_1082_DATA 0x00000000
+#define DDRSS3_PHY_1083_DATA 0x00000000
+#define DDRSS3_PHY_1084_DATA 0x00000000
+#define DDRSS3_PHY_1085_DATA 0x00000000
+#define DDRSS3_PHY_1086_DATA 0x00000000
+#define DDRSS3_PHY_1087_DATA 0x00000000
+#define DDRSS3_PHY_1088_DATA 0x00000000
+#define DDRSS3_PHY_1089_DATA 0x00000000
+#define DDRSS3_PHY_1090_DATA 0x00000000
+#define DDRSS3_PHY_1091_DATA 0x00000000
+#define DDRSS3_PHY_1092_DATA 0x00000000
+#define DDRSS3_PHY_1093_DATA 0x00000000
+#define DDRSS3_PHY_1094_DATA 0x00000000
+#define DDRSS3_PHY_1095_DATA 0x00000000
+#define DDRSS3_PHY_1096_DATA 0x00000000
+#define DDRSS3_PHY_1097_DATA 0x00000000
+#define DDRSS3_PHY_1098_DATA 0x00000000
+#define DDRSS3_PHY_1099_DATA 0x00000000
+#define DDRSS3_PHY_1100_DATA 0x00000000
+#define DDRSS3_PHY_1101_DATA 0x00000000
+#define DDRSS3_PHY_1102_DATA 0x00000000
+#define DDRSS3_PHY_1103_DATA 0x00000000
+#define DDRSS3_PHY_1104_DATA 0x00000000
+#define DDRSS3_PHY_1105_DATA 0x00000000
+#define DDRSS3_PHY_1106_DATA 0x00000000
+#define DDRSS3_PHY_1107_DATA 0x00000000
+#define DDRSS3_PHY_1108_DATA 0x00000000
+#define DDRSS3_PHY_1109_DATA 0x00000000
+#define DDRSS3_PHY_1110_DATA 0x00000000
+#define DDRSS3_PHY_1111_DATA 0x00000000
+#define DDRSS3_PHY_1112_DATA 0x00000000
+#define DDRSS3_PHY_1113_DATA 0x00000000
+#define DDRSS3_PHY_1114_DATA 0x00000000
+#define DDRSS3_PHY_1115_DATA 0x00000000
+#define DDRSS3_PHY_1116_DATA 0x00000000
+#define DDRSS3_PHY_1117_DATA 0x00000000
+#define DDRSS3_PHY_1118_DATA 0x00000000
+#define DDRSS3_PHY_1119_DATA 0x00000000
+#define DDRSS3_PHY_1120_DATA 0x00000000
+#define DDRSS3_PHY_1121_DATA 0x00000000
+#define DDRSS3_PHY_1122_DATA 0x00000000
+#define DDRSS3_PHY_1123_DATA 0x00000000
+#define DDRSS3_PHY_1124_DATA 0x00000000
+#define DDRSS3_PHY_1125_DATA 0x00000000
+#define DDRSS3_PHY_1126_DATA 0x00000000
+#define DDRSS3_PHY_1127_DATA 0x00000000
+#define DDRSS3_PHY_1128_DATA 0x00000000
+#define DDRSS3_PHY_1129_DATA 0x00000000
+#define DDRSS3_PHY_1130_DATA 0x00000000
+#define DDRSS3_PHY_1131_DATA 0x00000000
+#define DDRSS3_PHY_1132_DATA 0x00000000
+#define DDRSS3_PHY_1133_DATA 0x00000000
+#define DDRSS3_PHY_1134_DATA 0x00000000
+#define DDRSS3_PHY_1135_DATA 0x00000000
+#define DDRSS3_PHY_1136_DATA 0x00000000
+#define DDRSS3_PHY_1137_DATA 0x00000000
+#define DDRSS3_PHY_1138_DATA 0x00000000
+#define DDRSS3_PHY_1139_DATA 0x00000000
+#define DDRSS3_PHY_1140_DATA 0x00000000
+#define DDRSS3_PHY_1141_DATA 0x00000000
+#define DDRSS3_PHY_1142_DATA 0x00000000
+#define DDRSS3_PHY_1143_DATA 0x00000000
+#define DDRSS3_PHY_1144_DATA 0x00000000
+#define DDRSS3_PHY_1145_DATA 0x00000000
+#define DDRSS3_PHY_1146_DATA 0x00000000
+#define DDRSS3_PHY_1147_DATA 0x00000000
+#define DDRSS3_PHY_1148_DATA 0x00000000
+#define DDRSS3_PHY_1149_DATA 0x00000000
+#define DDRSS3_PHY_1150_DATA 0x00000000
+#define DDRSS3_PHY_1151_DATA 0x00000000
+#define DDRSS3_PHY_1152_DATA 0x00000000
+#define DDRSS3_PHY_1153_DATA 0x00000000
+#define DDRSS3_PHY_1154_DATA 0x00000000
+#define DDRSS3_PHY_1155_DATA 0x00000000
+#define DDRSS3_PHY_1156_DATA 0x00000000
+#define DDRSS3_PHY_1157_DATA 0x00000000
+#define DDRSS3_PHY_1158_DATA 0x00000000
+#define DDRSS3_PHY_1159_DATA 0x00000000
+#define DDRSS3_PHY_1160_DATA 0x00000000
+#define DDRSS3_PHY_1161_DATA 0x00000000
+#define DDRSS3_PHY_1162_DATA 0x00000000
+#define DDRSS3_PHY_1163_DATA 0x00000000
+#define DDRSS3_PHY_1164_DATA 0x00000000
+#define DDRSS3_PHY_1165_DATA 0x00000000
+#define DDRSS3_PHY_1166_DATA 0x00000000
+#define DDRSS3_PHY_1167_DATA 0x00000000
+#define DDRSS3_PHY_1168_DATA 0x00000000
+#define DDRSS3_PHY_1169_DATA 0x00000000
+#define DDRSS3_PHY_1170_DATA 0x00000000
+#define DDRSS3_PHY_1171_DATA 0x00000000
+#define DDRSS3_PHY_1172_DATA 0x00000000
+#define DDRSS3_PHY_1173_DATA 0x00000000
+#define DDRSS3_PHY_1174_DATA 0x00000000
+#define DDRSS3_PHY_1175_DATA 0x00000000
+#define DDRSS3_PHY_1176_DATA 0x00000000
+#define DDRSS3_PHY_1177_DATA 0x00000000
+#define DDRSS3_PHY_1178_DATA 0x00000000
+#define DDRSS3_PHY_1179_DATA 0x00000000
+#define DDRSS3_PHY_1180_DATA 0x00000000
+#define DDRSS3_PHY_1181_DATA 0x00000000
+#define DDRSS3_PHY_1182_DATA 0x00000000
+#define DDRSS3_PHY_1183_DATA 0x00000000
+#define DDRSS3_PHY_1184_DATA 0x00000000
+#define DDRSS3_PHY_1185_DATA 0x00000000
+#define DDRSS3_PHY_1186_DATA 0x00000000
+#define DDRSS3_PHY_1187_DATA 0x00000000
+#define DDRSS3_PHY_1188_DATA 0x00000000
+#define DDRSS3_PHY_1189_DATA 0x00000000
+#define DDRSS3_PHY_1190_DATA 0x00000000
+#define DDRSS3_PHY_1191_DATA 0x00000000
+#define DDRSS3_PHY_1192_DATA 0x00000000
+#define DDRSS3_PHY_1193_DATA 0x00000000
+#define DDRSS3_PHY_1194_DATA 0x00000000
+#define DDRSS3_PHY_1195_DATA 0x00000000
+#define DDRSS3_PHY_1196_DATA 0x00000000
+#define DDRSS3_PHY_1197_DATA 0x00000000
+#define DDRSS3_PHY_1198_DATA 0x00000000
+#define DDRSS3_PHY_1199_DATA 0x00000000
+#define DDRSS3_PHY_1200_DATA 0x00000000
+#define DDRSS3_PHY_1201_DATA 0x00000000
+#define DDRSS3_PHY_1202_DATA 0x00000000
+#define DDRSS3_PHY_1203_DATA 0x00000000
+#define DDRSS3_PHY_1204_DATA 0x00000000
+#define DDRSS3_PHY_1205_DATA 0x00000000
+#define DDRSS3_PHY_1206_DATA 0x00000000
+#define DDRSS3_PHY_1207_DATA 0x00000000
+#define DDRSS3_PHY_1208_DATA 0x00000000
+#define DDRSS3_PHY_1209_DATA 0x00000000
+#define DDRSS3_PHY_1210_DATA 0x00000000
+#define DDRSS3_PHY_1211_DATA 0x00000000
+#define DDRSS3_PHY_1212_DATA 0x00000000
+#define DDRSS3_PHY_1213_DATA 0x00000000
+#define DDRSS3_PHY_1214_DATA 0x00000000
+#define DDRSS3_PHY_1215_DATA 0x00000000
+#define DDRSS3_PHY_1216_DATA 0x00000000
+#define DDRSS3_PHY_1217_DATA 0x00000000
+#define DDRSS3_PHY_1218_DATA 0x00000000
+#define DDRSS3_PHY_1219_DATA 0x00000000
+#define DDRSS3_PHY_1220_DATA 0x00000000
+#define DDRSS3_PHY_1221_DATA 0x00000000
+#define DDRSS3_PHY_1222_DATA 0x00000000
+#define DDRSS3_PHY_1223_DATA 0x00000000
+#define DDRSS3_PHY_1224_DATA 0x00000000
+#define DDRSS3_PHY_1225_DATA 0x00000000
+#define DDRSS3_PHY_1226_DATA 0x00000000
+#define DDRSS3_PHY_1227_DATA 0x00000000
+#define DDRSS3_PHY_1228_DATA 0x00000000
+#define DDRSS3_PHY_1229_DATA 0x00000000
+#define DDRSS3_PHY_1230_DATA 0x00000000
+#define DDRSS3_PHY_1231_DATA 0x00000000
+#define DDRSS3_PHY_1232_DATA 0x00000000
+#define DDRSS3_PHY_1233_DATA 0x00000000
+#define DDRSS3_PHY_1234_DATA 0x00000000
+#define DDRSS3_PHY_1235_DATA 0x00000000
+#define DDRSS3_PHY_1236_DATA 0x00000000
+#define DDRSS3_PHY_1237_DATA 0x00000000
+#define DDRSS3_PHY_1238_DATA 0x00000000
+#define DDRSS3_PHY_1239_DATA 0x00000000
+#define DDRSS3_PHY_1240_DATA 0x00000000
+#define DDRSS3_PHY_1241_DATA 0x00000000
+#define DDRSS3_PHY_1242_DATA 0x00000000
+#define DDRSS3_PHY_1243_DATA 0x00000000
+#define DDRSS3_PHY_1244_DATA 0x00000000
+#define DDRSS3_PHY_1245_DATA 0x00000000
+#define DDRSS3_PHY_1246_DATA 0x00000000
+#define DDRSS3_PHY_1247_DATA 0x00000000
+#define DDRSS3_PHY_1248_DATA 0x00000000
+#define DDRSS3_PHY_1249_DATA 0x00000000
+#define DDRSS3_PHY_1250_DATA 0x00000000
+#define DDRSS3_PHY_1251_DATA 0x00000000
+#define DDRSS3_PHY_1252_DATA 0x00000000
+#define DDRSS3_PHY_1253_DATA 0x00000000
+#define DDRSS3_PHY_1254_DATA 0x00000000
+#define DDRSS3_PHY_1255_DATA 0x00000000
+#define DDRSS3_PHY_1256_DATA 0x00000000
+#define DDRSS3_PHY_1257_DATA 0x00000000
+#define DDRSS3_PHY_1258_DATA 0x00000000
+#define DDRSS3_PHY_1259_DATA 0x00000000
+#define DDRSS3_PHY_1260_DATA 0x00000000
+#define DDRSS3_PHY_1261_DATA 0x00000000
+#define DDRSS3_PHY_1262_DATA 0x00000000
+#define DDRSS3_PHY_1263_DATA 0x00000000
+#define DDRSS3_PHY_1264_DATA 0x00000000
+#define DDRSS3_PHY_1265_DATA 0x00000000
+#define DDRSS3_PHY_1266_DATA 0x00000000
+#define DDRSS3_PHY_1267_DATA 0x00000000
+#define DDRSS3_PHY_1268_DATA 0x00000000
+#define DDRSS3_PHY_1269_DATA 0x00000000
+#define DDRSS3_PHY_1270_DATA 0x00000000
+#define DDRSS3_PHY_1271_DATA 0x00000000
+#define DDRSS3_PHY_1272_DATA 0x00000000
+#define DDRSS3_PHY_1273_DATA 0x00000000
+#define DDRSS3_PHY_1274_DATA 0x00000000
+#define DDRSS3_PHY_1275_DATA 0x00000000
+#define DDRSS3_PHY_1276_DATA 0x00000000
+#define DDRSS3_PHY_1277_DATA 0x00000000
+#define DDRSS3_PHY_1278_DATA 0x00000000
+#define DDRSS3_PHY_1279_DATA 0x00000000
+#define DDRSS3_PHY_1280_DATA 0x00000000
+#define DDRSS3_PHY_1281_DATA 0x00010100
+#define DDRSS3_PHY_1282_DATA 0x00000000
+#define DDRSS3_PHY_1283_DATA 0x00000000
+#define DDRSS3_PHY_1284_DATA 0x00050000
+#define DDRSS3_PHY_1285_DATA 0x04000000
+#define DDRSS3_PHY_1286_DATA 0x00000055
+#define DDRSS3_PHY_1287_DATA 0x00000000
+#define DDRSS3_PHY_1288_DATA 0x00000000
+#define DDRSS3_PHY_1289_DATA 0x00000000
+#define DDRSS3_PHY_1290_DATA 0x00000000
+#define DDRSS3_PHY_1291_DATA 0x00002001
+#define DDRSS3_PHY_1292_DATA 0x0000400F
+#define DDRSS3_PHY_1293_DATA 0x50020028
+#define DDRSS3_PHY_1294_DATA 0x01010000
+#define DDRSS3_PHY_1295_DATA 0x80080001
+#define DDRSS3_PHY_1296_DATA 0x10200000
+#define DDRSS3_PHY_1297_DATA 0x00000008
+#define DDRSS3_PHY_1298_DATA 0x00000000
+#define DDRSS3_PHY_1299_DATA 0x01090E00
+#define DDRSS3_PHY_1300_DATA 0x00040101
+#define DDRSS3_PHY_1301_DATA 0x0000010F
+#define DDRSS3_PHY_1302_DATA 0x00000000
+#define DDRSS3_PHY_1303_DATA 0x0000FFFF
+#define DDRSS3_PHY_1304_DATA 0x00000000
+#define DDRSS3_PHY_1305_DATA 0x01010000
+#define DDRSS3_PHY_1306_DATA 0x01080402
+#define DDRSS3_PHY_1307_DATA 0x01200F02
+#define DDRSS3_PHY_1308_DATA 0x00194280
+#define DDRSS3_PHY_1309_DATA 0x00000004
+#define DDRSS3_PHY_1310_DATA 0x00042000
+#define DDRSS3_PHY_1311_DATA 0x00000000
+#define DDRSS3_PHY_1312_DATA 0x00000000
+#define DDRSS3_PHY_1313_DATA 0x00000000
+#define DDRSS3_PHY_1314_DATA 0x00000000
+#define DDRSS3_PHY_1315_DATA 0x00000000
+#define DDRSS3_PHY_1316_DATA 0x00000000
+#define DDRSS3_PHY_1317_DATA 0x01000000
+#define DDRSS3_PHY_1318_DATA 0x00000705
+#define DDRSS3_PHY_1319_DATA 0x00000054
+#define DDRSS3_PHY_1320_DATA 0x00030820
+#define DDRSS3_PHY_1321_DATA 0x00010820
+#define DDRSS3_PHY_1322_DATA 0x00010820
+#define DDRSS3_PHY_1323_DATA 0x00010820
+#define DDRSS3_PHY_1324_DATA 0x00010820
+#define DDRSS3_PHY_1325_DATA 0x00010820
+#define DDRSS3_PHY_1326_DATA 0x00010820
+#define DDRSS3_PHY_1327_DATA 0x00010820
+#define DDRSS3_PHY_1328_DATA 0x00010820
+#define DDRSS3_PHY_1329_DATA 0x00000000
+#define DDRSS3_PHY_1330_DATA 0x00000074
+#define DDRSS3_PHY_1331_DATA 0x00000400
+#define DDRSS3_PHY_1332_DATA 0x00000108
+#define DDRSS3_PHY_1333_DATA 0x00000000
+#define DDRSS3_PHY_1334_DATA 0x00000000
+#define DDRSS3_PHY_1335_DATA 0x00000000
+#define DDRSS3_PHY_1336_DATA 0x00000000
+#define DDRSS3_PHY_1337_DATA 0x00000000
+#define DDRSS3_PHY_1338_DATA 0x03000000
+#define DDRSS3_PHY_1339_DATA 0x00000000
+#define DDRSS3_PHY_1340_DATA 0x00000000
+#define DDRSS3_PHY_1341_DATA 0x00000000
+#define DDRSS3_PHY_1342_DATA 0x04102006
+#define DDRSS3_PHY_1343_DATA 0x00041020
+#define DDRSS3_PHY_1344_DATA 0x01C98C98
+#define DDRSS3_PHY_1345_DATA 0x3F400000
+#define DDRSS3_PHY_1346_DATA 0x3F3F1F3F
+#define DDRSS3_PHY_1347_DATA 0x0000001F
+#define DDRSS3_PHY_1348_DATA 0x00000000
+#define DDRSS3_PHY_1349_DATA 0x00000000
+#define DDRSS3_PHY_1350_DATA 0x00000000
+#define DDRSS3_PHY_1351_DATA 0x00010000
+#define DDRSS3_PHY_1352_DATA 0x00000000
+#define DDRSS3_PHY_1353_DATA 0x00000000
+#define DDRSS3_PHY_1354_DATA 0x00000000
+#define DDRSS3_PHY_1355_DATA 0x00000000
+#define DDRSS3_PHY_1356_DATA 0x76543210
+#define DDRSS3_PHY_1357_DATA 0x00010198
+#define DDRSS3_PHY_1358_DATA 0x00000000
+#define DDRSS3_PHY_1359_DATA 0x00000000
+#define DDRSS3_PHY_1360_DATA 0x00000000
+#define DDRSS3_PHY_1361_DATA 0x00040700
+#define DDRSS3_PHY_1362_DATA 0x00000000
+#define DDRSS3_PHY_1363_DATA 0x00000000
+#define DDRSS3_PHY_1364_DATA 0x00000000
+#define DDRSS3_PHY_1365_DATA 0x00000000
+#define DDRSS3_PHY_1366_DATA 0x00000000
+#define DDRSS3_PHY_1367_DATA 0x00000002
+#define DDRSS3_PHY_1368_DATA 0x00000000
+#define DDRSS3_PHY_1369_DATA 0x00000000
+#define DDRSS3_PHY_1370_DATA 0x00000000
+#define DDRSS3_PHY_1371_DATA 0x00000000
+#define DDRSS3_PHY_1372_DATA 0x00000000
+#define DDRSS3_PHY_1373_DATA 0x00000000
+#define DDRSS3_PHY_1374_DATA 0x00080000
+#define DDRSS3_PHY_1375_DATA 0x000007FF
+#define DDRSS3_PHY_1376_DATA 0x00000000
+#define DDRSS3_PHY_1377_DATA 0x00000000
+#define DDRSS3_PHY_1378_DATA 0x00000000
+#define DDRSS3_PHY_1379_DATA 0x00000000
+#define DDRSS3_PHY_1380_DATA 0x00000000
+#define DDRSS3_PHY_1381_DATA 0x00000000
+#define DDRSS3_PHY_1382_DATA 0x000FFFFF
+#define DDRSS3_PHY_1383_DATA 0x000FFFFF
+#define DDRSS3_PHY_1384_DATA 0x0000FFFF
+#define DDRSS3_PHY_1385_DATA 0xFFFFFFF0
+#define DDRSS3_PHY_1386_DATA 0x030FFFFF
+#define DDRSS3_PHY_1387_DATA 0x01FFFFFF
+#define DDRSS3_PHY_1388_DATA 0x0000FFFF
+#define DDRSS3_PHY_1389_DATA 0x00000000
+#define DDRSS3_PHY_1390_DATA 0x00000000
+#define DDRSS3_PHY_1391_DATA 0x00000000
+#define DDRSS3_PHY_1392_DATA 0x00000000
+#define DDRSS3_PHY_1393_DATA 0x0001F7C0
+#define DDRSS3_PHY_1394_DATA 0x00000003
+#define DDRSS3_PHY_1395_DATA 0x00000000
+#define DDRSS3_PHY_1396_DATA 0x00001142
+#define DDRSS3_PHY_1397_DATA 0x010207AB
+#define DDRSS3_PHY_1398_DATA 0x01000080
+#define DDRSS3_PHY_1399_DATA 0x03900390
+#define DDRSS3_PHY_1400_DATA 0x03900390
+#define DDRSS3_PHY_1401_DATA 0x00000390
+#define DDRSS3_PHY_1402_DATA 0x00000390
+#define DDRSS3_PHY_1403_DATA 0x00000390
+#define DDRSS3_PHY_1404_DATA 0x00000390
+#define DDRSS3_PHY_1405_DATA 0x00000005
+#define DDRSS3_PHY_1406_DATA 0x01813FCC
+#define DDRSS3_PHY_1407_DATA 0x000000CC
+#define DDRSS3_PHY_1408_DATA 0x0C000DFF
+#define DDRSS3_PHY_1409_DATA 0x30000DFF
+#define DDRSS3_PHY_1410_DATA 0x3F0DFF11
+#define DDRSS3_PHY_1411_DATA 0x000100F0
+#define DDRSS3_PHY_1412_DATA 0x780DFFCC
+#define DDRSS3_PHY_1413_DATA 0x00007E31
+#define DDRSS3_PHY_1414_DATA 0x000CBF11
+#define DDRSS3_PHY_1415_DATA 0x01990010
+#define DDRSS3_PHY_1416_DATA 0x000CBF11
+#define DDRSS3_PHY_1417_DATA 0x01990010
+#define DDRSS3_PHY_1418_DATA 0x3F0DFF11
+#define DDRSS3_PHY_1419_DATA 0x00EF00F0
+#define DDRSS3_PHY_1420_DATA 0x3F0DFF11
+#define DDRSS3_PHY_1421_DATA 0x01FF00F0
+#define DDRSS3_PHY_1422_DATA 0x20040006
diff --git a/arch/arm/dts/k3-j742s2-evm-u-boot.dtsi b/arch/arm/dts/k3-j742s2-evm-u-boot.dtsi
new file mode 100644
index 00000000000..ede5d6e58f5
--- /dev/null
+++ b/arch/arm/dts/k3-j742s2-evm-u-boot.dtsi
@@ -0,0 +1,72 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#define SPL_BOARD_DTB "spl/dts/ti/k3-j742s2-evm.dtb"
+#define BOARD_DESCRIPTION "k3-j742s2-evm"
+#define UBOOT_BOARD_DESCRIPTION "U-Boot for J742S2 board"
+
+#include "k3-j784s4-binman.dtsi"
+
+#if !defined(CONFIG_ARM64)
+
+&binman {
+	tiboot3-j742s2-hs-fs {
+		insert-template = <&tiboot3_j784s4_hs_fs>;
+		filename = "tiboot3-j742s2-hs-fs-evm.bin";
+		symlink = "tiboot3.bin";
+	};
+
+	tiboot3-j742s2-hs {
+		insert-template = <&tiboot3_j784s4_hs>;
+		filename = "tiboot3-j742s2-hs-evm.bin";
+	};
+};
+
+&ti_fs_enc_fs {
+	filename = "ti-sysfw/ti-fs-firmware-j742s2-hs-fs-enc.bin";
+};
+
+&sysfw_inner_cert_fs {
+	filename = "ti-sysfw/ti-fs-firmware-j742s2-hs-fs-cert.bin";
+};
+
+&ti_fs_enc {
+	filename = "ti-sysfw/ti-fs-firmware-j742s2-hs-enc.bin";
+};
+
+&sysfw_inner_cert {
+	filename = "ti-sysfw/ti-fs-firmware-j742s2-hs-cert.bin";
+};
+
+#else // CONFIG_ARM64
+
+&binman {
+	ti-dm {
+		filename = "ti-dm.bin";
+
+		blob-ext {
+			filename = "ti-dm/j742s2/ipc_echo_testb_mcu1_0_release_strip.xer5f";
+			optional;
+		};
+	};
+
+	tispl {
+		insert-template = <&ti_spl>;
+	};
+
+	u-boot {
+		insert-template = <&u_boot>;
+	};
+
+	tispl-unsigned {
+		insert-template = <&ti_spl_unsigned>;
+	};
+
+	u-boot-unsigned {
+		insert-template = <&u_boot_unsigned>;
+	};
+};
+
+#endif
diff --git a/arch/arm/dts/k3-j742s2-r5-evm.dts b/arch/arm/dts/k3-j742s2-r5-evm.dts
new file mode 100644
index 00000000000..6dde13c4e75
--- /dev/null
+++ b/arch/arm/dts/k3-j742s2-r5-evm.dts
@@ -0,0 +1,18 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
+ */
+/dts-v1/;
+
+#include "k3-j742s2-evm.dts"
+#include "k3-j742s2-ddr-evm-lp4-4266.dtsi"
+#include "k3-j784s4-j742s2-ddr.dtsi"
+#include "k3-j742s2-evm-u-boot.dtsi"
+#include "k3-j784s4-r5.dtsi"
+
+&tps659413 {
+	esm: esm {
+		compatible = "ti,tps659413-esm";
+		bootph-pre-ram;
+	};
+};
diff --git a/arch/arm/dts/k3-j784s4-binman.dtsi b/arch/arm/dts/k3-j784s4-binman.dtsi
index 85bdd1f5b6c..0553825b383 100644
--- a/arch/arm/dts/k3-j784s4-binman.dtsi
+++ b/arch/arm/dts/k3-j784s4-binman.dtsi
@@ -5,16 +5,15 @@
 
 #include "k3-binman.dtsi"
 
-#ifdef CONFIG_TARGET_J784S4_R5_EVM
+#if defined(CONFIG_CPU_V7R)
 
 &rcfg_yaml_tifs {
 	config = "tifs-rm-cfg.yaml";
 };
 
 &binman {
-	tiboot3-j784s4-hs-evm.bin {
-		filename = "tiboot3-j784s4-hs-evm.bin";
-
+	tiboot3_j784s4_hs: template-9 {
+		section {
 		ti-secure-rom {
 			content = <&u_boot_spl>, <&ti_fs_enc>, <&combined_tifs_cfg>,
 				<&combined_dm_cfg>, <&sysfw_inner_cert>;
@@ -39,7 +38,6 @@
 		};
 
 		ti_fs_enc: ti-fs-enc.bin {
-			filename = "ti-sysfw/ti-fs-firmware-j784s4-hs-enc.bin";
 			type = "blob-ext";
 			optional;
 		};
@@ -50,7 +48,6 @@
 		};
 
 		sysfw_inner_cert: sysfw-inner-cert {
-			filename = "ti-sysfw/ti-fs-firmware-j784s4-hs-cert.bin";
 			type = "blob-ext";
 			optional;
 		};
@@ -59,13 +56,13 @@
 			filename = "combined-dm-cfg.bin";
 			type = "blob-ext";
 		};
+		};
 	};
 };
 
 &binman {
-	tiboot3-j784s4-hs-fs-evm.bin {
-		filename = "tiboot3-j784s4-hs-fs-evm.bin";
-
+	tiboot3_j784s4_hs_fs: template-10 {
+		section {
 		ti-secure-rom {
 			content = <&u_boot_spl_fs>, <&ti_fs_enc_fs>, <&combined_tifs_cfg_fs>,
 				<&combined_dm_cfg_fs>, <&sysfw_inner_cert_fs>;
@@ -90,7 +87,6 @@
 		};
 
 		ti_fs_enc_fs: ti-fs-enc.bin {
-			filename = "ti-sysfw/ti-fs-firmware-j784s4-hs-fs-enc.bin";
 			type = "blob-ext";
 			optional;
 		};
@@ -101,7 +97,6 @@
 		};
 
 		sysfw_inner_cert_fs: sysfw-inner-cert {
-			filename = "ti-sysfw/ti-fs-firmware-j784s4-hs-fs-cert.bin";
 			type = "blob-ext";
 			optional;
 		};
@@ -110,14 +105,13 @@
 			filename = "combined-dm-cfg.bin";
 			type = "blob-ext";
 		};
+		};
 	};
 };
 
 &binman {
-	tiboot3-j784s4-gp-evm.bin {
-		filename = "tiboot3-j784s4-gp-evm.bin";
-		symlink = "tiboot3.bin";
-
+	tiboot3_j784s4_gp: template-11 {
+		section {
 		ti-secure-rom {
 			content = <&u_boot_spl_unsigned>, <&ti_fs_gp>,
 				<&combined_tifs_cfg_gp>, <&combined_dm_cfg_gp>;
@@ -140,7 +134,6 @@
 		};
 
 		ti_fs_gp: ti-fs-gp.bin {
-			filename = "ti-sysfw/ti-fs-firmware-j784s4-gp.bin";
 			type = "blob-ext";
 			optional;
 		};
@@ -154,43 +147,14 @@
 			filename = "combined-dm-cfg.bin";
 			type = "blob-ext";
 		};
-
-	};
-};
-
-#include "k3-binman-capsule-r5.dtsi"
-
-// Capsule update GUIDs in string form.  See j784s4_evm.h
-#define AM69_SK_TIBOOT3_IMAGE_GUID_STR "adf49ec5-61bb-4dbe-8b8d-39df4d7ebf46"
-
-&capsule_tiboot3 {
-	efi-capsule {
-		image-guid = AM69_SK_TIBOOT3_IMAGE_GUID_STR;
-
-		blob {
-			filename = "tiboot3-j784s4-hs-fs-evm.bin";
 		};
 	};
 };
 
-#endif
-
-#ifdef CONFIG_TARGET_J784S4_A72_EVM
-
-#define SPL_J784S4_EVM_DTB "spl/dts/ti/k3-j784s4-evm.dtb"
-#define J784S4_EVM_DTB "u-boot.dtb"
+#else
 
 &binman {
-	ti-dm {
-		filename = "ti-dm.bin";
-
-		blob-ext {
-			filename = "ti-dm/j784s4/ipc_echo_testb_mcu1_0_release_strip.xer5f";
-			optional;
-		};
-	};
-
-	ti-spl {
+	ti_spl: template-12 {
 		insert-template = <&ti_spl_template>;
 
 		fit {
@@ -207,19 +171,20 @@
 				};
 
 				fdt-0 {
-					description = "k3-j784s4-evm";
+					description = BOARD_DESCRIPTION;
 					type = "flat_dt";
 					arch = "arm";
 					compression = "none";
 
 					ti-secure {
-						content = <&spl_j784s4_evm_dtb>;
+						content = <&spl_board_dtb>;
 						keyfile = "custMpk.pem";
 					};
 
-					spl_j784s4_evm_dtb: blob-ext {
-						filename = SPL_J784S4_EVM_DTB;
+					spl_board_dtb: blob-ext {
+						filename = SPL_BOARD_DTB;
 					};
+
 				};
 			};
 
@@ -227,7 +192,7 @@
 				default = "conf-0";
 
 				conf-0 {
-					description = "k3-j784s4-evm";
+					description = BOARD_DESCRIPTION;
 					firmware = "atf";
 					loadables = "tee", "dm", "spl";
 					fdt = "fdt-0";
@@ -238,17 +203,17 @@
 };
 
 &binman {
-	u-boot {
+	u_boot: template-13 {
 		insert-template = <&u_boot_template>;
 
 		fit {
 			images {
 				uboot {
-					description = "U-Boot for J784S4 board";
+					description = UBOOT_BOARD_DESCRIPTION;
 				};
 
 				fdt-0 {
-					description = "k3-j784s4-evm";
+					description = BOARD_DESCRIPTION;
 					type = "flat_dt";
 					arch = "arm";
 					compression = "none";
@@ -259,7 +224,7 @@
 					};
 
 					j784s4_evm_dtb: blob-ext {
-						filename = J784S4_EVM_DTB;
+						filename = "u-boot.dtb";
 					};
 
 					hash {
@@ -272,7 +237,7 @@
 				default = "conf-0";
 
 				conf-0 {
-					description = "k3-j784s4-evm";
+					description = BOARD_DESCRIPTION;
 					firmware = "uboot";
 					loadables = "uboot";
 					fdt = "fdt-0";
@@ -283,7 +248,7 @@
 };
 
 &binman {
-	ti-spl_unsigned {
+	ti_spl_unsigned: template-14 {
 		insert-template = <&ti_spl_unsigned_template>;
 
 		fit {
@@ -295,13 +260,13 @@
 				};
 
 				fdt-0 {
-					description = "k3-j784s4-evm";
+					description = BOARD_DESCRIPTION;
 					type = "flat_dt";
 					arch = "arm";
 					compression = "none";
 
 					spl_j784s4_evm_dtb_unsigned: blob {
-						filename = SPL_J784S4_EVM_DTB;
+						filename = SPL_BOARD_DTB;
 					};
 				};
 			};
@@ -310,7 +275,7 @@
 				default = "conf-0";
 
 				conf-0 {
-					description = "k3-j784s4-evm";
+					description = BOARD_DESCRIPTION;
 					firmware = "atf";
 					loadables = "tee", "dm", "spl";
 					fdt = "fdt-0";
@@ -321,23 +286,23 @@
 };
 
 &binman {
-	u-boot_unsigned {
+	u_boot_unsigned: template-15 {
 		insert-template = <&u_boot_unsigned_template>;
 
 		fit {
 			images {
 				uboot {
-					description = "U-Boot for J784S4 board";
+					description = UBOOT_BOARD_DESCRIPTION;
 				};
 
 				fdt-0 {
-					description = "k3-j784s4-evm";
+					description = BOARD_DESCRIPTION;
 					type = "flat_dt";
 					arch = "arm";
 					compression = "none";
 
 					j784s4_evm_dtb_unsigned: blob {
-						filename = J784S4_EVM_DTB;
+						filename = "u-boot.dtb";
 					};
 
 					hash {
@@ -350,7 +315,7 @@
 				default = "conf-0";
 
 				conf-0 {
-					description = "k3-j784s4-evm";
+					description = BOARD_DESCRIPTION;
 					firmware = "uboot";
 					loadables = "uboot";
 					fdt = "fdt-0";
@@ -359,23 +324,4 @@
 		};
 	};
 };
-
-#include "k3-binman-capsule.dtsi"
-
-// Capsule update GUIDs in string form.  See j784s4_evm.h
-#define AM69_SK_SPL_IMAGE_GUID_STR "787f0059-63a1-461c-a18e-9d838345fe8e"
-#define AM69_SK_UBOOT_IMAGE_GUID_STR "9300505d-6ec5-4ff8-99e4-5459a04be617"
-
-&capsule_tispl {
-	efi-capsule {
-		image-guid = AM69_SK_SPL_IMAGE_GUID_STR;
-	};
-};
-
-&capsule_uboot {
-	efi-capsule {
-		image-guid = AM69_SK_UBOOT_IMAGE_GUID_STR;
-	};
-};
-
 #endif
diff --git a/arch/arm/dts/k3-j784s4-ddr.dtsi b/arch/arm/dts/k3-j784s4-ddr.dtsi
index fc74c539331..47ed3f05eb2 100644
--- a/arch/arm/dts/k3-j784s4-ddr.dtsi
+++ b/arch/arm/dts/k3-j784s4-ddr.dtsi
@@ -3,8864 +3,4424 @@
  * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/
  */
 
-&main_navss {
-	ranges = <0x00 0x00114000 0x00 0x00114000 0x00 0x00000100>, // ctrl_mmr_lpr
-		 <0x00 0x02990000 0x00 0x02990000 0x00 0x00004000>, // ddr0 cfg
-		 <0x00 0x029b0000 0x00 0x029b0000 0x00 0x00004000>, // ddr1 cfg
-		 <0x00 0x029d0000 0x00 0x029d0000 0x00 0x00004000>, // ddr2 cfg
-		 <0x00 0x029f0000 0x00 0x029f0000 0x00 0x00004000>, // ddr3 cfg
-		 <0x00 0x02980000 0x00 0x02980000 0x00 0x00000200>, // ss cfg 0
-		 <0x00 0x029a0000 0x00 0x029a0000 0x00 0x00000200>, // ss cfg 1
-		 <0x00 0x029c0000 0x00 0x029c0000 0x00 0x00000200>, // ss cfg 2
-		 <0x00 0x029e0000 0x00 0x029e0000 0x00 0x00000200>, // ss cfg 3
-		 <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>;
+#include "k3-j784s4-j742s2-ddr.dtsi"
 
-	msmc0: msmc {
-		compatible = "ti,j721s2-msmc";
-		intrlv-gran = <MULTI_DDR_CFG_INTRLV_GRAN>;
-		intrlv-size = <MULTI_DDR_CFG_INTRLV_SIZE>;
-		ecc-enable = <MULTI_DDR_CFG_ECC_ENABLE>;
-		emif-config = <MULTI_DDR_CFG_HYBRID_SELECT>;
-		emif-active = <MULTI_DDR_CFG_EMIFS_ACTIVE>;
-		#address-cells = <2>;
-		#size-cells = <2>;
+&msmc0 {
+	memorycontroller2: memorycontroller@29d0000 {
+		compatible = "ti,j721s2-ddrss";
+		reg = <0x0 0x029d0000 0x0 0x4000>,
+			  <0x0 0x0114000 0x0 0x100>,
+			  <0x0 0x029c0000 0x0 0x200>;
+		reg-names = "cfg", "ctrl_mmr_lp4", "ss_cfg";
+		power-domains = <&k3_pds 193 TI_SCI_PD_SHARED>,
+			<&k3_pds 133 TI_SCI_PD_SHARED>;
+		clocks = <&k3_clks 193 1>, <&k3_clks 78 2>;
+		ti,ddr-freq0 = <DDRSS_PLL_FREQUENCY_0>;
+		ti,ddr-freq1 = <DDRSS_PLL_FREQUENCY_1>;
+		ti,ddr-freq2 = <DDRSS_PLL_FREQUENCY_2>;
+		ti,ddr-fhs-cnt = <DDRSS_PLL_FHS_CNT>;
+		instance = <2>;
 
 		bootph-pre-ram;
 
-		memorycontroller0: memorycontroller@2990000 {
-			compatible = "ti,j721s2-ddrss";
-			reg = <0x0 0x02990000 0x0 0x4000>,
-			      <0x0 0x0114000 0x0 0x100>,
-			      <0x0 0x02980000 0x0 0x200>;
-			reg-names = "cfg", "ctrl_mmr_lp4", "ss_cfg";
-			power-domains = <&k3_pds 191 TI_SCI_PD_SHARED>,
-				<&k3_pds 131 TI_SCI_PD_SHARED>;
-			clocks = <&k3_clks 191 1>, <&k3_clks 78 2>;
-			ti,ddr-freq0 = <DDRSS_PLL_FREQUENCY_0>;
-			ti,ddr-freq1 = <DDRSS_PLL_FREQUENCY_1>;
-			ti,ddr-freq2 = <DDRSS_PLL_FREQUENCY_2>;
-			ti,ddr-fhs-cnt = <DDRSS_PLL_FHS_CNT>;
-			instance = <0>;
+		ti,ctl-data = <
+			DDRSS2_CTL_00_DATA
+			DDRSS2_CTL_01_DATA
+			DDRSS2_CTL_02_DATA
+			DDRSS2_CTL_03_DATA
+			DDRSS2_CTL_04_DATA
+			DDRSS2_CTL_05_DATA
+			DDRSS2_CTL_06_DATA
+			DDRSS2_CTL_07_DATA
+			DDRSS2_CTL_08_DATA
+			DDRSS2_CTL_09_DATA
+			DDRSS2_CTL_10_DATA
+			DDRSS2_CTL_11_DATA
+			DDRSS2_CTL_12_DATA
+			DDRSS2_CTL_13_DATA
+			DDRSS2_CTL_14_DATA
+			DDRSS2_CTL_15_DATA
+			DDRSS2_CTL_16_DATA
+			DDRSS2_CTL_17_DATA
+			DDRSS2_CTL_18_DATA
+			DDRSS2_CTL_19_DATA
+			DDRSS2_CTL_20_DATA
+			DDRSS2_CTL_21_DATA
+			DDRSS2_CTL_22_DATA
+			DDRSS2_CTL_23_DATA
+			DDRSS2_CTL_24_DATA
+			DDRSS2_CTL_25_DATA
+			DDRSS2_CTL_26_DATA
+			DDRSS2_CTL_27_DATA
+			DDRSS2_CTL_28_DATA
+			DDRSS2_CTL_29_DATA
+			DDRSS2_CTL_30_DATA
+			DDRSS2_CTL_31_DATA
+			DDRSS2_CTL_32_DATA
+			DDRSS2_CTL_33_DATA
+			DDRSS2_CTL_34_DATA
+			DDRSS2_CTL_35_DATA
+			DDRSS2_CTL_36_DATA
+			DDRSS2_CTL_37_DATA
+			DDRSS2_CTL_38_DATA
+			DDRSS2_CTL_39_DATA
+			DDRSS2_CTL_40_DATA
+			DDRSS2_CTL_41_DATA
+			DDRSS2_CTL_42_DATA
+			DDRSS2_CTL_43_DATA
+			DDRSS2_CTL_44_DATA
+			DDRSS2_CTL_45_DATA
+			DDRSS2_CTL_46_DATA
+			DDRSS2_CTL_47_DATA
+			DDRSS2_CTL_48_DATA
+			DDRSS2_CTL_49_DATA
+			DDRSS2_CTL_50_DATA
+			DDRSS2_CTL_51_DATA
+			DDRSS2_CTL_52_DATA
+			DDRSS2_CTL_53_DATA
+			DDRSS2_CTL_54_DATA
+			DDRSS2_CTL_55_DATA
+			DDRSS2_CTL_56_DATA
+			DDRSS2_CTL_57_DATA
+			DDRSS2_CTL_58_DATA
+			DDRSS2_CTL_59_DATA
+			DDRSS2_CTL_60_DATA
+			DDRSS2_CTL_61_DATA
+			DDRSS2_CTL_62_DATA
+			DDRSS2_CTL_63_DATA
+			DDRSS2_CTL_64_DATA
+			DDRSS2_CTL_65_DATA
+			DDRSS2_CTL_66_DATA
+			DDRSS2_CTL_67_DATA
+			DDRSS2_CTL_68_DATA
+			DDRSS2_CTL_69_DATA
+			DDRSS2_CTL_70_DATA
+			DDRSS2_CTL_71_DATA
+			DDRSS2_CTL_72_DATA
+			DDRSS2_CTL_73_DATA
+			DDRSS2_CTL_74_DATA
+			DDRSS2_CTL_75_DATA
+			DDRSS2_CTL_76_DATA
+			DDRSS2_CTL_77_DATA
+			DDRSS2_CTL_78_DATA
+			DDRSS2_CTL_79_DATA
+			DDRSS2_CTL_80_DATA
+			DDRSS2_CTL_81_DATA
+			DDRSS2_CTL_82_DATA
+			DDRSS2_CTL_83_DATA
+			DDRSS2_CTL_84_DATA
+			DDRSS2_CTL_85_DATA
+			DDRSS2_CTL_86_DATA
+			DDRSS2_CTL_87_DATA
+			DDRSS2_CTL_88_DATA
+			DDRSS2_CTL_89_DATA
+			DDRSS2_CTL_90_DATA
+			DDRSS2_CTL_91_DATA
+			DDRSS2_CTL_92_DATA
+			DDRSS2_CTL_93_DATA
+			DDRSS2_CTL_94_DATA
+			DDRSS2_CTL_95_DATA
+			DDRSS2_CTL_96_DATA
+			DDRSS2_CTL_97_DATA
+			DDRSS2_CTL_98_DATA
+			DDRSS2_CTL_99_DATA
+			DDRSS2_CTL_100_DATA
+			DDRSS2_CTL_101_DATA
+			DDRSS2_CTL_102_DATA
+			DDRSS2_CTL_103_DATA
+			DDRSS2_CTL_104_DATA
+			DDRSS2_CTL_105_DATA
+			DDRSS2_CTL_106_DATA
+			DDRSS2_CTL_107_DATA
+			DDRSS2_CTL_108_DATA
+			DDRSS2_CTL_109_DATA
+			DDRSS2_CTL_110_DATA
+			DDRSS2_CTL_111_DATA
+			DDRSS2_CTL_112_DATA
+			DDRSS2_CTL_113_DATA
+			DDRSS2_CTL_114_DATA
+			DDRSS2_CTL_115_DATA
+			DDRSS2_CTL_116_DATA
+			DDRSS2_CTL_117_DATA
+			DDRSS2_CTL_118_DATA
+			DDRSS2_CTL_119_DATA
+			DDRSS2_CTL_120_DATA
+			DDRSS2_CTL_121_DATA
+			DDRSS2_CTL_122_DATA
+			DDRSS2_CTL_123_DATA
+			DDRSS2_CTL_124_DATA
+			DDRSS2_CTL_125_DATA
+			DDRSS2_CTL_126_DATA
+			DDRSS2_CTL_127_DATA
+			DDRSS2_CTL_128_DATA
+			DDRSS2_CTL_129_DATA
+			DDRSS2_CTL_130_DATA
+			DDRSS2_CTL_131_DATA
+			DDRSS2_CTL_132_DATA
+			DDRSS2_CTL_133_DATA
+			DDRSS2_CTL_134_DATA
+			DDRSS2_CTL_135_DATA
+			DDRSS2_CTL_136_DATA
+			DDRSS2_CTL_137_DATA
+			DDRSS2_CTL_138_DATA
+			DDRSS2_CTL_139_DATA
+			DDRSS2_CTL_140_DATA
+			DDRSS2_CTL_141_DATA
+			DDRSS2_CTL_142_DATA
+			DDRSS2_CTL_143_DATA
+			DDRSS2_CTL_144_DATA
+			DDRSS2_CTL_145_DATA
+			DDRSS2_CTL_146_DATA
+			DDRSS2_CTL_147_DATA
+			DDRSS2_CTL_148_DATA
+			DDRSS2_CTL_149_DATA
+			DDRSS2_CTL_150_DATA
+			DDRSS2_CTL_151_DATA
+			DDRSS2_CTL_152_DATA
+			DDRSS2_CTL_153_DATA
+			DDRSS2_CTL_154_DATA
+			DDRSS2_CTL_155_DATA
+			DDRSS2_CTL_156_DATA
+			DDRSS2_CTL_157_DATA
+			DDRSS2_CTL_158_DATA
+			DDRSS2_CTL_159_DATA
+			DDRSS2_CTL_160_DATA
+			DDRSS2_CTL_161_DATA
+			DDRSS2_CTL_162_DATA
+			DDRSS2_CTL_163_DATA
+			DDRSS2_CTL_164_DATA
+			DDRSS2_CTL_165_DATA
+			DDRSS2_CTL_166_DATA
+			DDRSS2_CTL_167_DATA
+			DDRSS2_CTL_168_DATA
+			DDRSS2_CTL_169_DATA
+			DDRSS2_CTL_170_DATA
+			DDRSS2_CTL_171_DATA
+			DDRSS2_CTL_172_DATA
+			DDRSS2_CTL_173_DATA
+			DDRSS2_CTL_174_DATA
+			DDRSS2_CTL_175_DATA
+			DDRSS2_CTL_176_DATA
+			DDRSS2_CTL_177_DATA
+			DDRSS2_CTL_178_DATA
+			DDRSS2_CTL_179_DATA
+			DDRSS2_CTL_180_DATA
+			DDRSS2_CTL_181_DATA
+			DDRSS2_CTL_182_DATA
+			DDRSS2_CTL_183_DATA
+			DDRSS2_CTL_184_DATA
+			DDRSS2_CTL_185_DATA
+			DDRSS2_CTL_186_DATA
+			DDRSS2_CTL_187_DATA
+			DDRSS2_CTL_188_DATA
+			DDRSS2_CTL_189_DATA
+			DDRSS2_CTL_190_DATA
+			DDRSS2_CTL_191_DATA
+			DDRSS2_CTL_192_DATA
+			DDRSS2_CTL_193_DATA
+			DDRSS2_CTL_194_DATA
+			DDRSS2_CTL_195_DATA
+			DDRSS2_CTL_196_DATA
+			DDRSS2_CTL_197_DATA
+			DDRSS2_CTL_198_DATA
+			DDRSS2_CTL_199_DATA
+			DDRSS2_CTL_200_DATA
+			DDRSS2_CTL_201_DATA
+			DDRSS2_CTL_202_DATA
+			DDRSS2_CTL_203_DATA
+			DDRSS2_CTL_204_DATA
+			DDRSS2_CTL_205_DATA
+			DDRSS2_CTL_206_DATA
+			DDRSS2_CTL_207_DATA
+			DDRSS2_CTL_208_DATA
+			DDRSS2_CTL_209_DATA
+			DDRSS2_CTL_210_DATA
+			DDRSS2_CTL_211_DATA
+			DDRSS2_CTL_212_DATA
+			DDRSS2_CTL_213_DATA
+			DDRSS2_CTL_214_DATA
+			DDRSS2_CTL_215_DATA
+			DDRSS2_CTL_216_DATA
+			DDRSS2_CTL_217_DATA
+			DDRSS2_CTL_218_DATA
+			DDRSS2_CTL_219_DATA
+			DDRSS2_CTL_220_DATA
+			DDRSS2_CTL_221_DATA
+			DDRSS2_CTL_222_DATA
+			DDRSS2_CTL_223_DATA
+			DDRSS2_CTL_224_DATA
+			DDRSS2_CTL_225_DATA
+			DDRSS2_CTL_226_DATA
+			DDRSS2_CTL_227_DATA
+			DDRSS2_CTL_228_DATA
+			DDRSS2_CTL_229_DATA
+			DDRSS2_CTL_230_DATA
+			DDRSS2_CTL_231_DATA
+			DDRSS2_CTL_232_DATA
+			DDRSS2_CTL_233_DATA
+			DDRSS2_CTL_234_DATA
+			DDRSS2_CTL_235_DATA
+			DDRSS2_CTL_236_DATA
+			DDRSS2_CTL_237_DATA
+			DDRSS2_CTL_238_DATA
+			DDRSS2_CTL_239_DATA
+			DDRSS2_CTL_240_DATA
+			DDRSS2_CTL_241_DATA
+			DDRSS2_CTL_242_DATA
+			DDRSS2_CTL_243_DATA
+			DDRSS2_CTL_244_DATA
+			DDRSS2_CTL_245_DATA
+			DDRSS2_CTL_246_DATA
+			DDRSS2_CTL_247_DATA
+			DDRSS2_CTL_248_DATA
+			DDRSS2_CTL_249_DATA
+			DDRSS2_CTL_250_DATA
+			DDRSS2_CTL_251_DATA
+			DDRSS2_CTL_252_DATA
+			DDRSS2_CTL_253_DATA
+			DDRSS2_CTL_254_DATA
+			DDRSS2_CTL_255_DATA
+			DDRSS2_CTL_256_DATA
+			DDRSS2_CTL_257_DATA
+			DDRSS2_CTL_258_DATA
+			DDRSS2_CTL_259_DATA
+			DDRSS2_CTL_260_DATA
+			DDRSS2_CTL_261_DATA
+			DDRSS2_CTL_262_DATA
+			DDRSS2_CTL_263_DATA
+			DDRSS2_CTL_264_DATA
+			DDRSS2_CTL_265_DATA
+			DDRSS2_CTL_266_DATA
+			DDRSS2_CTL_267_DATA
+			DDRSS2_CTL_268_DATA
+			DDRSS2_CTL_269_DATA
+			DDRSS2_CTL_270_DATA
+			DDRSS2_CTL_271_DATA
+			DDRSS2_CTL_272_DATA
+			DDRSS2_CTL_273_DATA
+			DDRSS2_CTL_274_DATA
+			DDRSS2_CTL_275_DATA
+			DDRSS2_CTL_276_DATA
+			DDRSS2_CTL_277_DATA
+			DDRSS2_CTL_278_DATA
+			DDRSS2_CTL_279_DATA
+			DDRSS2_CTL_280_DATA
+			DDRSS2_CTL_281_DATA
+			DDRSS2_CTL_282_DATA
+			DDRSS2_CTL_283_DATA
+			DDRSS2_CTL_284_DATA
+			DDRSS2_CTL_285_DATA
+			DDRSS2_CTL_286_DATA
+			DDRSS2_CTL_287_DATA
+			DDRSS2_CTL_288_DATA
+			DDRSS2_CTL_289_DATA
+			DDRSS2_CTL_290_DATA
+			DDRSS2_CTL_291_DATA
+			DDRSS2_CTL_292_DATA
+			DDRSS2_CTL_293_DATA
+			DDRSS2_CTL_294_DATA
+			DDRSS2_CTL_295_DATA
+			DDRSS2_CTL_296_DATA
+			DDRSS2_CTL_297_DATA
+			DDRSS2_CTL_298_DATA
+			DDRSS2_CTL_299_DATA
+			DDRSS2_CTL_300_DATA
+			DDRSS2_CTL_301_DATA
+			DDRSS2_CTL_302_DATA
+			DDRSS2_CTL_303_DATA
+			DDRSS2_CTL_304_DATA
+			DDRSS2_CTL_305_DATA
+			DDRSS2_CTL_306_DATA
+			DDRSS2_CTL_307_DATA
+			DDRSS2_CTL_308_DATA
+			DDRSS2_CTL_309_DATA
+			DDRSS2_CTL_310_DATA
+			DDRSS2_CTL_311_DATA
+			DDRSS2_CTL_312_DATA
+			DDRSS2_CTL_313_DATA
+			DDRSS2_CTL_314_DATA
+			DDRSS2_CTL_315_DATA
+			DDRSS2_CTL_316_DATA
+			DDRSS2_CTL_317_DATA
+			DDRSS2_CTL_318_DATA
+			DDRSS2_CTL_319_DATA
+			DDRSS2_CTL_320_DATA
+			DDRSS2_CTL_321_DATA
+			DDRSS2_CTL_322_DATA
+			DDRSS2_CTL_323_DATA
+			DDRSS2_CTL_324_DATA
+			DDRSS2_CTL_325_DATA
+			DDRSS2_CTL_326_DATA
+			DDRSS2_CTL_327_DATA
+			DDRSS2_CTL_328_DATA
+			DDRSS2_CTL_329_DATA
+			DDRSS2_CTL_330_DATA
+			DDRSS2_CTL_331_DATA
+			DDRSS2_CTL_332_DATA
+			DDRSS2_CTL_333_DATA
+			DDRSS2_CTL_334_DATA
+			DDRSS2_CTL_335_DATA
+			DDRSS2_CTL_336_DATA
+			DDRSS2_CTL_337_DATA
+			DDRSS2_CTL_338_DATA
+			DDRSS2_CTL_339_DATA
+			DDRSS2_CTL_340_DATA
+			DDRSS2_CTL_341_DATA
+			DDRSS2_CTL_342_DATA
+			DDRSS2_CTL_343_DATA
+			DDRSS2_CTL_344_DATA
+			DDRSS2_CTL_345_DATA
+			DDRSS2_CTL_346_DATA
+			DDRSS2_CTL_347_DATA
+			DDRSS2_CTL_348_DATA
+			DDRSS2_CTL_349_DATA
+			DDRSS2_CTL_350_DATA
+			DDRSS2_CTL_351_DATA
+			DDRSS2_CTL_352_DATA
+			DDRSS2_CTL_353_DATA
+			DDRSS2_CTL_354_DATA
+			DDRSS2_CTL_355_DATA
+			DDRSS2_CTL_356_DATA
+			DDRSS2_CTL_357_DATA
+			DDRSS2_CTL_358_DATA
+			DDRSS2_CTL_359_DATA
+			DDRSS2_CTL_360_DATA
+			DDRSS2_CTL_361_DATA
+			DDRSS2_CTL_362_DATA
+			DDRSS2_CTL_363_DATA
+			DDRSS2_CTL_364_DATA
+			DDRSS2_CTL_365_DATA
+			DDRSS2_CTL_366_DATA
+			DDRSS2_CTL_367_DATA
+			DDRSS2_CTL_368_DATA
+			DDRSS2_CTL_369_DATA
+			DDRSS2_CTL_370_DATA
+			DDRSS2_CTL_371_DATA
+			DDRSS2_CTL_372_DATA
+			DDRSS2_CTL_373_DATA
+			DDRSS2_CTL_374_DATA
+			DDRSS2_CTL_375_DATA
+			DDRSS2_CTL_376_DATA
+			DDRSS2_CTL_377_DATA
+			DDRSS2_CTL_378_DATA
+			DDRSS2_CTL_379_DATA
+			DDRSS2_CTL_380_DATA
+			DDRSS2_CTL_381_DATA
+			DDRSS2_CTL_382_DATA
+			DDRSS2_CTL_383_DATA
+			DDRSS2_CTL_384_DATA
+			DDRSS2_CTL_385_DATA
+			DDRSS2_CTL_386_DATA
+			DDRSS2_CTL_387_DATA
+			DDRSS2_CTL_388_DATA
+			DDRSS2_CTL_389_DATA
+			DDRSS2_CTL_390_DATA
+			DDRSS2_CTL_391_DATA
+			DDRSS2_CTL_392_DATA
+			DDRSS2_CTL_393_DATA
+			DDRSS2_CTL_394_DATA
+			DDRSS2_CTL_395_DATA
+			DDRSS2_CTL_396_DATA
+			DDRSS2_CTL_397_DATA
+			DDRSS2_CTL_398_DATA
+			DDRSS2_CTL_399_DATA
+			DDRSS2_CTL_400_DATA
+			DDRSS2_CTL_401_DATA
+			DDRSS2_CTL_402_DATA
+			DDRSS2_CTL_403_DATA
+			DDRSS2_CTL_404_DATA
+			DDRSS2_CTL_405_DATA
+			DDRSS2_CTL_406_DATA
+			DDRSS2_CTL_407_DATA
+			DDRSS2_CTL_408_DATA
+			DDRSS2_CTL_409_DATA
+			DDRSS2_CTL_410_DATA
+			DDRSS2_CTL_411_DATA
+			DDRSS2_CTL_412_DATA
+			DDRSS2_CTL_413_DATA
+			DDRSS2_CTL_414_DATA
+			DDRSS2_CTL_415_DATA
+			DDRSS2_CTL_416_DATA
+			DDRSS2_CTL_417_DATA
+			DDRSS2_CTL_418_DATA
+			DDRSS2_CTL_419_DATA
+			DDRSS2_CTL_420_DATA
+			DDRSS2_CTL_421_DATA
+			DDRSS2_CTL_422_DATA
+			DDRSS2_CTL_423_DATA
+			DDRSS2_CTL_424_DATA
+			DDRSS2_CTL_425_DATA
+			DDRSS2_CTL_426_DATA
+			DDRSS2_CTL_427_DATA
+			DDRSS2_CTL_428_DATA
+			DDRSS2_CTL_429_DATA
+			DDRSS2_CTL_430_DATA
+			DDRSS2_CTL_431_DATA
+			DDRSS2_CTL_432_DATA
+			DDRSS2_CTL_433_DATA
+			DDRSS2_CTL_434_DATA
+			DDRSS2_CTL_435_DATA
+			DDRSS2_CTL_436_DATA
+			DDRSS2_CTL_437_DATA
+			DDRSS2_CTL_438_DATA
+			DDRSS2_CTL_439_DATA
+			DDRSS2_CTL_440_DATA
+			DDRSS2_CTL_441_DATA
+			DDRSS2_CTL_442_DATA
+			DDRSS2_CTL_443_DATA
+			DDRSS2_CTL_444_DATA
+			DDRSS2_CTL_445_DATA
+			DDRSS2_CTL_446_DATA
+			DDRSS2_CTL_447_DATA
+			DDRSS2_CTL_448_DATA
+			DDRSS2_CTL_449_DATA
+			DDRSS2_CTL_450_DATA
+			DDRSS2_CTL_451_DATA
+			DDRSS2_CTL_452_DATA
+			DDRSS2_CTL_453_DATA
+			DDRSS2_CTL_454_DATA
+			DDRSS2_CTL_455_DATA
+			DDRSS2_CTL_456_DATA
+			DDRSS2_CTL_457_DATA
+			DDRSS2_CTL_458_DATA
+		>;
 
-			bootph-pre-ram;
+		ti,pi-data = <
+			DDRSS2_PI_00_DATA
+			DDRSS2_PI_01_DATA
+			DDRSS2_PI_02_DATA
+			DDRSS2_PI_03_DATA
+			DDRSS2_PI_04_DATA
+			DDRSS2_PI_05_DATA
+			DDRSS2_PI_06_DATA
+			DDRSS2_PI_07_DATA
+			DDRSS2_PI_08_DATA
+			DDRSS2_PI_09_DATA
+			DDRSS2_PI_10_DATA
+			DDRSS2_PI_11_DATA
+			DDRSS2_PI_12_DATA
+			DDRSS2_PI_13_DATA
+			DDRSS2_PI_14_DATA
+			DDRSS2_PI_15_DATA
+			DDRSS2_PI_16_DATA
+			DDRSS2_PI_17_DATA
+			DDRSS2_PI_18_DATA
+			DDRSS2_PI_19_DATA
+			DDRSS2_PI_20_DATA
+			DDRSS2_PI_21_DATA
+			DDRSS2_PI_22_DATA
+			DDRSS2_PI_23_DATA
+			DDRSS2_PI_24_DATA
+			DDRSS2_PI_25_DATA
+			DDRSS2_PI_26_DATA
+			DDRSS2_PI_27_DATA
+			DDRSS2_PI_28_DATA
+			DDRSS2_PI_29_DATA
+			DDRSS2_PI_30_DATA
+			DDRSS2_PI_31_DATA
+			DDRSS2_PI_32_DATA
+			DDRSS2_PI_33_DATA
+			DDRSS2_PI_34_DATA
+			DDRSS2_PI_35_DATA
+			DDRSS2_PI_36_DATA
+			DDRSS2_PI_37_DATA
+			DDRSS2_PI_38_DATA
+			DDRSS2_PI_39_DATA
+			DDRSS2_PI_40_DATA
+			DDRSS2_PI_41_DATA
+			DDRSS2_PI_42_DATA
+			DDRSS2_PI_43_DATA
+			DDRSS2_PI_44_DATA
+			DDRSS2_PI_45_DATA
+			DDRSS2_PI_46_DATA
+			DDRSS2_PI_47_DATA
+			DDRSS2_PI_48_DATA
+			DDRSS2_PI_49_DATA
+			DDRSS2_PI_50_DATA
+			DDRSS2_PI_51_DATA
+			DDRSS2_PI_52_DATA
+			DDRSS2_PI_53_DATA
+			DDRSS2_PI_54_DATA
+			DDRSS2_PI_55_DATA
+			DDRSS2_PI_56_DATA
+			DDRSS2_PI_57_DATA
+			DDRSS2_PI_58_DATA
+			DDRSS2_PI_59_DATA
+			DDRSS2_PI_60_DATA
+			DDRSS2_PI_61_DATA
+			DDRSS2_PI_62_DATA
+			DDRSS2_PI_63_DATA
+			DDRSS2_PI_64_DATA
+			DDRSS2_PI_65_DATA
+			DDRSS2_PI_66_DATA
+			DDRSS2_PI_67_DATA
+			DDRSS2_PI_68_DATA
+			DDRSS2_PI_69_DATA
+			DDRSS2_PI_70_DATA
+			DDRSS2_PI_71_DATA
+			DDRSS2_PI_72_DATA
+			DDRSS2_PI_73_DATA
+			DDRSS2_PI_74_DATA
+			DDRSS2_PI_75_DATA
+			DDRSS2_PI_76_DATA
+			DDRSS2_PI_77_DATA
+			DDRSS2_PI_78_DATA
+			DDRSS2_PI_79_DATA
+			DDRSS2_PI_80_DATA
+			DDRSS2_PI_81_DATA
+			DDRSS2_PI_82_DATA
+			DDRSS2_PI_83_DATA
+			DDRSS2_PI_84_DATA
+			DDRSS2_PI_85_DATA
+			DDRSS2_PI_86_DATA
+			DDRSS2_PI_87_DATA
+			DDRSS2_PI_88_DATA
+			DDRSS2_PI_89_DATA
+			DDRSS2_PI_90_DATA
+			DDRSS2_PI_91_DATA
+			DDRSS2_PI_92_DATA
+			DDRSS2_PI_93_DATA
+			DDRSS2_PI_94_DATA
+			DDRSS2_PI_95_DATA
+			DDRSS2_PI_96_DATA
+			DDRSS2_PI_97_DATA
+			DDRSS2_PI_98_DATA
+			DDRSS2_PI_99_DATA
+			DDRSS2_PI_100_DATA
+			DDRSS2_PI_101_DATA
+			DDRSS2_PI_102_DATA
+			DDRSS2_PI_103_DATA
+			DDRSS2_PI_104_DATA
+			DDRSS2_PI_105_DATA
+			DDRSS2_PI_106_DATA
+			DDRSS2_PI_107_DATA
+			DDRSS2_PI_108_DATA
+			DDRSS2_PI_109_DATA
+			DDRSS2_PI_110_DATA
+			DDRSS2_PI_111_DATA
+			DDRSS2_PI_112_DATA
+			DDRSS2_PI_113_DATA
+			DDRSS2_PI_114_DATA
+			DDRSS2_PI_115_DATA
+			DDRSS2_PI_116_DATA
+			DDRSS2_PI_117_DATA
+			DDRSS2_PI_118_DATA
+			DDRSS2_PI_119_DATA
+			DDRSS2_PI_120_DATA
+			DDRSS2_PI_121_DATA
+			DDRSS2_PI_122_DATA
+			DDRSS2_PI_123_DATA
+			DDRSS2_PI_124_DATA
+			DDRSS2_PI_125_DATA
+			DDRSS2_PI_126_DATA
+			DDRSS2_PI_127_DATA
+			DDRSS2_PI_128_DATA
+			DDRSS2_PI_129_DATA
+			DDRSS2_PI_130_DATA
+			DDRSS2_PI_131_DATA
+			DDRSS2_PI_132_DATA
+			DDRSS2_PI_133_DATA
+			DDRSS2_PI_134_DATA
+			DDRSS2_PI_135_DATA
+			DDRSS2_PI_136_DATA
+			DDRSS2_PI_137_DATA
+			DDRSS2_PI_138_DATA
+			DDRSS2_PI_139_DATA
+			DDRSS2_PI_140_DATA
+			DDRSS2_PI_141_DATA
+			DDRSS2_PI_142_DATA
+			DDRSS2_PI_143_DATA
+			DDRSS2_PI_144_DATA
+			DDRSS2_PI_145_DATA
+			DDRSS2_PI_146_DATA
+			DDRSS2_PI_147_DATA
+			DDRSS2_PI_148_DATA
+			DDRSS2_PI_149_DATA
+			DDRSS2_PI_150_DATA
+			DDRSS2_PI_151_DATA
+			DDRSS2_PI_152_DATA
+			DDRSS2_PI_153_DATA
+			DDRSS2_PI_154_DATA
+			DDRSS2_PI_155_DATA
+			DDRSS2_PI_156_DATA
+			DDRSS2_PI_157_DATA
+			DDRSS2_PI_158_DATA
+			DDRSS2_PI_159_DATA
+			DDRSS2_PI_160_DATA
+			DDRSS2_PI_161_DATA
+			DDRSS2_PI_162_DATA
+			DDRSS2_PI_163_DATA
+			DDRSS2_PI_164_DATA
+			DDRSS2_PI_165_DATA
+			DDRSS2_PI_166_DATA
+			DDRSS2_PI_167_DATA
+			DDRSS2_PI_168_DATA
+			DDRSS2_PI_169_DATA
+			DDRSS2_PI_170_DATA
+			DDRSS2_PI_171_DATA
+			DDRSS2_PI_172_DATA
+			DDRSS2_PI_173_DATA
+			DDRSS2_PI_174_DATA
+			DDRSS2_PI_175_DATA
+			DDRSS2_PI_176_DATA
+			DDRSS2_PI_177_DATA
+			DDRSS2_PI_178_DATA
+			DDRSS2_PI_179_DATA
+			DDRSS2_PI_180_DATA
+			DDRSS2_PI_181_DATA
+			DDRSS2_PI_182_DATA
+			DDRSS2_PI_183_DATA
+			DDRSS2_PI_184_DATA
+			DDRSS2_PI_185_DATA
+			DDRSS2_PI_186_DATA
+			DDRSS2_PI_187_DATA
+			DDRSS2_PI_188_DATA
+			DDRSS2_PI_189_DATA
+			DDRSS2_PI_190_DATA
+			DDRSS2_PI_191_DATA
+			DDRSS2_PI_192_DATA
+			DDRSS2_PI_193_DATA
+			DDRSS2_PI_194_DATA
+			DDRSS2_PI_195_DATA
+			DDRSS2_PI_196_DATA
+			DDRSS2_PI_197_DATA
+			DDRSS2_PI_198_DATA
+			DDRSS2_PI_199_DATA
+			DDRSS2_PI_200_DATA
+			DDRSS2_PI_201_DATA
+			DDRSS2_PI_202_DATA
+			DDRSS2_PI_203_DATA
+			DDRSS2_PI_204_DATA
+			DDRSS2_PI_205_DATA
+			DDRSS2_PI_206_DATA
+			DDRSS2_PI_207_DATA
+			DDRSS2_PI_208_DATA
+			DDRSS2_PI_209_DATA
+			DDRSS2_PI_210_DATA
+			DDRSS2_PI_211_DATA
+			DDRSS2_PI_212_DATA
+			DDRSS2_PI_213_DATA
+			DDRSS2_PI_214_DATA
+			DDRSS2_PI_215_DATA
+			DDRSS2_PI_216_DATA
+			DDRSS2_PI_217_DATA
+			DDRSS2_PI_218_DATA
+			DDRSS2_PI_219_DATA
+			DDRSS2_PI_220_DATA
+			DDRSS2_PI_221_DATA
+			DDRSS2_PI_222_DATA
+			DDRSS2_PI_223_DATA
+			DDRSS2_PI_224_DATA
+			DDRSS2_PI_225_DATA
+			DDRSS2_PI_226_DATA
+			DDRSS2_PI_227_DATA
+			DDRSS2_PI_228_DATA
+			DDRSS2_PI_229_DATA
+			DDRSS2_PI_230_DATA
+			DDRSS2_PI_231_DATA
+			DDRSS2_PI_232_DATA
+			DDRSS2_PI_233_DATA
+			DDRSS2_PI_234_DATA
+			DDRSS2_PI_235_DATA
+			DDRSS2_PI_236_DATA
+			DDRSS2_PI_237_DATA
+			DDRSS2_PI_238_DATA
+			DDRSS2_PI_239_DATA
+			DDRSS2_PI_240_DATA
+			DDRSS2_PI_241_DATA
+			DDRSS2_PI_242_DATA
+			DDRSS2_PI_243_DATA
+			DDRSS2_PI_244_DATA
+			DDRSS2_PI_245_DATA
+			DDRSS2_PI_246_DATA
+			DDRSS2_PI_247_DATA
+			DDRSS2_PI_248_DATA
+			DDRSS2_PI_249_DATA
+			DDRSS2_PI_250_DATA
+			DDRSS2_PI_251_DATA
+			DDRSS2_PI_252_DATA
+			DDRSS2_PI_253_DATA
+			DDRSS2_PI_254_DATA
+			DDRSS2_PI_255_DATA
+			DDRSS2_PI_256_DATA
+			DDRSS2_PI_257_DATA
+			DDRSS2_PI_258_DATA
+			DDRSS2_PI_259_DATA
+			DDRSS2_PI_260_DATA
+			DDRSS2_PI_261_DATA
+			DDRSS2_PI_262_DATA
+			DDRSS2_PI_263_DATA
+			DDRSS2_PI_264_DATA
+			DDRSS2_PI_265_DATA
+			DDRSS2_PI_266_DATA
+			DDRSS2_PI_267_DATA
+			DDRSS2_PI_268_DATA
+			DDRSS2_PI_269_DATA
+			DDRSS2_PI_270_DATA
+			DDRSS2_PI_271_DATA
+			DDRSS2_PI_272_DATA
+			DDRSS2_PI_273_DATA
+			DDRSS2_PI_274_DATA
+			DDRSS2_PI_275_DATA
+			DDRSS2_PI_276_DATA
+			DDRSS2_PI_277_DATA
+			DDRSS2_PI_278_DATA
+			DDRSS2_PI_279_DATA
+			DDRSS2_PI_280_DATA
+			DDRSS2_PI_281_DATA
+			DDRSS2_PI_282_DATA
+			DDRSS2_PI_283_DATA
+			DDRSS2_PI_284_DATA
+			DDRSS2_PI_285_DATA
+			DDRSS2_PI_286_DATA
+			DDRSS2_PI_287_DATA
+			DDRSS2_PI_288_DATA
+			DDRSS2_PI_289_DATA
+			DDRSS2_PI_290_DATA
+			DDRSS2_PI_291_DATA
+			DDRSS2_PI_292_DATA
+			DDRSS2_PI_293_DATA
+			DDRSS2_PI_294_DATA
+			DDRSS2_PI_295_DATA
+			DDRSS2_PI_296_DATA
+			DDRSS2_PI_297_DATA
+			DDRSS2_PI_298_DATA
+			DDRSS2_PI_299_DATA
+		>;
 
-			ti,ctl-data = <
-				DDRSS0_CTL_00_DATA
-				DDRSS0_CTL_01_DATA
-				DDRSS0_CTL_02_DATA
-				DDRSS0_CTL_03_DATA
-				DDRSS0_CTL_04_DATA
-				DDRSS0_CTL_05_DATA
-				DDRSS0_CTL_06_DATA
-				DDRSS0_CTL_07_DATA
-				DDRSS0_CTL_08_DATA
-				DDRSS0_CTL_09_DATA
-				DDRSS0_CTL_10_DATA
-				DDRSS0_CTL_11_DATA
-				DDRSS0_CTL_12_DATA
-				DDRSS0_CTL_13_DATA
-				DDRSS0_CTL_14_DATA
-				DDRSS0_CTL_15_DATA
-				DDRSS0_CTL_16_DATA
-				DDRSS0_CTL_17_DATA
-				DDRSS0_CTL_18_DATA
-				DDRSS0_CTL_19_DATA
-				DDRSS0_CTL_20_DATA
-				DDRSS0_CTL_21_DATA
-				DDRSS0_CTL_22_DATA
-				DDRSS0_CTL_23_DATA
-				DDRSS0_CTL_24_DATA
-				DDRSS0_CTL_25_DATA
-				DDRSS0_CTL_26_DATA
-				DDRSS0_CTL_27_DATA
-				DDRSS0_CTL_28_DATA
-				DDRSS0_CTL_29_DATA
-				DDRSS0_CTL_30_DATA
-				DDRSS0_CTL_31_DATA
-				DDRSS0_CTL_32_DATA
-				DDRSS0_CTL_33_DATA
-				DDRSS0_CTL_34_DATA
-				DDRSS0_CTL_35_DATA
-				DDRSS0_CTL_36_DATA
-				DDRSS0_CTL_37_DATA
-				DDRSS0_CTL_38_DATA
-				DDRSS0_CTL_39_DATA
-				DDRSS0_CTL_40_DATA
-				DDRSS0_CTL_41_DATA
-				DDRSS0_CTL_42_DATA
-				DDRSS0_CTL_43_DATA
-				DDRSS0_CTL_44_DATA
-				DDRSS0_CTL_45_DATA
-				DDRSS0_CTL_46_DATA
-				DDRSS0_CTL_47_DATA
-				DDRSS0_CTL_48_DATA
-				DDRSS0_CTL_49_DATA
-				DDRSS0_CTL_50_DATA
-				DDRSS0_CTL_51_DATA
-				DDRSS0_CTL_52_DATA
-				DDRSS0_CTL_53_DATA
-				DDRSS0_CTL_54_DATA
-				DDRSS0_CTL_55_DATA
-				DDRSS0_CTL_56_DATA
-				DDRSS0_CTL_57_DATA
-				DDRSS0_CTL_58_DATA
-				DDRSS0_CTL_59_DATA
-				DDRSS0_CTL_60_DATA
-				DDRSS0_CTL_61_DATA
-				DDRSS0_CTL_62_DATA
-				DDRSS0_CTL_63_DATA
-				DDRSS0_CTL_64_DATA
-				DDRSS0_CTL_65_DATA
-				DDRSS0_CTL_66_DATA
-				DDRSS0_CTL_67_DATA
-				DDRSS0_CTL_68_DATA
-				DDRSS0_CTL_69_DATA
-				DDRSS0_CTL_70_DATA
-				DDRSS0_CTL_71_DATA
-				DDRSS0_CTL_72_DATA
-				DDRSS0_CTL_73_DATA
-				DDRSS0_CTL_74_DATA
-				DDRSS0_CTL_75_DATA
-				DDRSS0_CTL_76_DATA
-				DDRSS0_CTL_77_DATA
-				DDRSS0_CTL_78_DATA
-				DDRSS0_CTL_79_DATA
-				DDRSS0_CTL_80_DATA
-				DDRSS0_CTL_81_DATA
-				DDRSS0_CTL_82_DATA
-				DDRSS0_CTL_83_DATA
-				DDRSS0_CTL_84_DATA
-				DDRSS0_CTL_85_DATA
-				DDRSS0_CTL_86_DATA
-				DDRSS0_CTL_87_DATA
-				DDRSS0_CTL_88_DATA
-				DDRSS0_CTL_89_DATA
-				DDRSS0_CTL_90_DATA
-				DDRSS0_CTL_91_DATA
-				DDRSS0_CTL_92_DATA
-				DDRSS0_CTL_93_DATA
-				DDRSS0_CTL_94_DATA
-				DDRSS0_CTL_95_DATA
-				DDRSS0_CTL_96_DATA
-				DDRSS0_CTL_97_DATA
-				DDRSS0_CTL_98_DATA
-				DDRSS0_CTL_99_DATA
-				DDRSS0_CTL_100_DATA
-				DDRSS0_CTL_101_DATA
-				DDRSS0_CTL_102_DATA
-				DDRSS0_CTL_103_DATA
-				DDRSS0_CTL_104_DATA
-				DDRSS0_CTL_105_DATA
-				DDRSS0_CTL_106_DATA
-				DDRSS0_CTL_107_DATA
-				DDRSS0_CTL_108_DATA
-				DDRSS0_CTL_109_DATA
-				DDRSS0_CTL_110_DATA
-				DDRSS0_CTL_111_DATA
-				DDRSS0_CTL_112_DATA
-				DDRSS0_CTL_113_DATA
-				DDRSS0_CTL_114_DATA
-				DDRSS0_CTL_115_DATA
-				DDRSS0_CTL_116_DATA
-				DDRSS0_CTL_117_DATA
-				DDRSS0_CTL_118_DATA
-				DDRSS0_CTL_119_DATA
-				DDRSS0_CTL_120_DATA
-				DDRSS0_CTL_121_DATA
-				DDRSS0_CTL_122_DATA
-				DDRSS0_CTL_123_DATA
-				DDRSS0_CTL_124_DATA
-				DDRSS0_CTL_125_DATA
-				DDRSS0_CTL_126_DATA
-				DDRSS0_CTL_127_DATA
-				DDRSS0_CTL_128_DATA
-				DDRSS0_CTL_129_DATA
-				DDRSS0_CTL_130_DATA
-				DDRSS0_CTL_131_DATA
-				DDRSS0_CTL_132_DATA
-				DDRSS0_CTL_133_DATA
-				DDRSS0_CTL_134_DATA
-				DDRSS0_CTL_135_DATA
-				DDRSS0_CTL_136_DATA
-				DDRSS0_CTL_137_DATA
-				DDRSS0_CTL_138_DATA
-				DDRSS0_CTL_139_DATA
-				DDRSS0_CTL_140_DATA
-				DDRSS0_CTL_141_DATA
-				DDRSS0_CTL_142_DATA
-				DDRSS0_CTL_143_DATA
-				DDRSS0_CTL_144_DATA
-				DDRSS0_CTL_145_DATA
-				DDRSS0_CTL_146_DATA
-				DDRSS0_CTL_147_DATA
-				DDRSS0_CTL_148_DATA
-				DDRSS0_CTL_149_DATA
-				DDRSS0_CTL_150_DATA
-				DDRSS0_CTL_151_DATA
-				DDRSS0_CTL_152_DATA
-				DDRSS0_CTL_153_DATA
-				DDRSS0_CTL_154_DATA
-				DDRSS0_CTL_155_DATA
-				DDRSS0_CTL_156_DATA
-				DDRSS0_CTL_157_DATA
-				DDRSS0_CTL_158_DATA
-				DDRSS0_CTL_159_DATA
-				DDRSS0_CTL_160_DATA
-				DDRSS0_CTL_161_DATA
-				DDRSS0_CTL_162_DATA
-				DDRSS0_CTL_163_DATA
-				DDRSS0_CTL_164_DATA
-				DDRSS0_CTL_165_DATA
-				DDRSS0_CTL_166_DATA
-				DDRSS0_CTL_167_DATA
-				DDRSS0_CTL_168_DATA
-				DDRSS0_CTL_169_DATA
-				DDRSS0_CTL_170_DATA
-				DDRSS0_CTL_171_DATA
-				DDRSS0_CTL_172_DATA
-				DDRSS0_CTL_173_DATA
-				DDRSS0_CTL_174_DATA
-				DDRSS0_CTL_175_DATA
-				DDRSS0_CTL_176_DATA
-				DDRSS0_CTL_177_DATA
-				DDRSS0_CTL_178_DATA
-				DDRSS0_CTL_179_DATA
-				DDRSS0_CTL_180_DATA
-				DDRSS0_CTL_181_DATA
-				DDRSS0_CTL_182_DATA
-				DDRSS0_CTL_183_DATA
-				DDRSS0_CTL_184_DATA
-				DDRSS0_CTL_185_DATA
-				DDRSS0_CTL_186_DATA
-				DDRSS0_CTL_187_DATA
-				DDRSS0_CTL_188_DATA
-				DDRSS0_CTL_189_DATA
-				DDRSS0_CTL_190_DATA
-				DDRSS0_CTL_191_DATA
-				DDRSS0_CTL_192_DATA
-				DDRSS0_CTL_193_DATA
-				DDRSS0_CTL_194_DATA
-				DDRSS0_CTL_195_DATA
-				DDRSS0_CTL_196_DATA
-				DDRSS0_CTL_197_DATA
-				DDRSS0_CTL_198_DATA
-				DDRSS0_CTL_199_DATA
-				DDRSS0_CTL_200_DATA
-				DDRSS0_CTL_201_DATA
-				DDRSS0_CTL_202_DATA
-				DDRSS0_CTL_203_DATA
-				DDRSS0_CTL_204_DATA
-				DDRSS0_CTL_205_DATA
-				DDRSS0_CTL_206_DATA
-				DDRSS0_CTL_207_DATA
-				DDRSS0_CTL_208_DATA
-				DDRSS0_CTL_209_DATA
-				DDRSS0_CTL_210_DATA
-				DDRSS0_CTL_211_DATA
-				DDRSS0_CTL_212_DATA
-				DDRSS0_CTL_213_DATA
-				DDRSS0_CTL_214_DATA
-				DDRSS0_CTL_215_DATA
-				DDRSS0_CTL_216_DATA
-				DDRSS0_CTL_217_DATA
-				DDRSS0_CTL_218_DATA
-				DDRSS0_CTL_219_DATA
-				DDRSS0_CTL_220_DATA
-				DDRSS0_CTL_221_DATA
-				DDRSS0_CTL_222_DATA
-				DDRSS0_CTL_223_DATA
-				DDRSS0_CTL_224_DATA
-				DDRSS0_CTL_225_DATA
-				DDRSS0_CTL_226_DATA
-				DDRSS0_CTL_227_DATA
-				DDRSS0_CTL_228_DATA
-				DDRSS0_CTL_229_DATA
-				DDRSS0_CTL_230_DATA
-				DDRSS0_CTL_231_DATA
-				DDRSS0_CTL_232_DATA
-				DDRSS0_CTL_233_DATA
-				DDRSS0_CTL_234_DATA
-				DDRSS0_CTL_235_DATA
-				DDRSS0_CTL_236_DATA
-				DDRSS0_CTL_237_DATA
-				DDRSS0_CTL_238_DATA
-				DDRSS0_CTL_239_DATA
-				DDRSS0_CTL_240_DATA
-				DDRSS0_CTL_241_DATA
-				DDRSS0_CTL_242_DATA
-				DDRSS0_CTL_243_DATA
-				DDRSS0_CTL_244_DATA
-				DDRSS0_CTL_245_DATA
-				DDRSS0_CTL_246_DATA
-				DDRSS0_CTL_247_DATA
-				DDRSS0_CTL_248_DATA
-				DDRSS0_CTL_249_DATA
-				DDRSS0_CTL_250_DATA
-				DDRSS0_CTL_251_DATA
-				DDRSS0_CTL_252_DATA
-				DDRSS0_CTL_253_DATA
-				DDRSS0_CTL_254_DATA
-				DDRSS0_CTL_255_DATA
-				DDRSS0_CTL_256_DATA
-				DDRSS0_CTL_257_DATA
-				DDRSS0_CTL_258_DATA
-				DDRSS0_CTL_259_DATA
-				DDRSS0_CTL_260_DATA
-				DDRSS0_CTL_261_DATA
-				DDRSS0_CTL_262_DATA
-				DDRSS0_CTL_263_DATA
-				DDRSS0_CTL_264_DATA
-				DDRSS0_CTL_265_DATA
-				DDRSS0_CTL_266_DATA
-				DDRSS0_CTL_267_DATA
-				DDRSS0_CTL_268_DATA
-				DDRSS0_CTL_269_DATA
-				DDRSS0_CTL_270_DATA
-				DDRSS0_CTL_271_DATA
-				DDRSS0_CTL_272_DATA
-				DDRSS0_CTL_273_DATA
-				DDRSS0_CTL_274_DATA
-				DDRSS0_CTL_275_DATA
-				DDRSS0_CTL_276_DATA
-				DDRSS0_CTL_277_DATA
-				DDRSS0_CTL_278_DATA
-				DDRSS0_CTL_279_DATA
-				DDRSS0_CTL_280_DATA
-				DDRSS0_CTL_281_DATA
-				DDRSS0_CTL_282_DATA
-				DDRSS0_CTL_283_DATA
-				DDRSS0_CTL_284_DATA
-				DDRSS0_CTL_285_DATA
-				DDRSS0_CTL_286_DATA
-				DDRSS0_CTL_287_DATA
-				DDRSS0_CTL_288_DATA
-				DDRSS0_CTL_289_DATA
-				DDRSS0_CTL_290_DATA
-				DDRSS0_CTL_291_DATA
-				DDRSS0_CTL_292_DATA
-				DDRSS0_CTL_293_DATA
-				DDRSS0_CTL_294_DATA
-				DDRSS0_CTL_295_DATA
-				DDRSS0_CTL_296_DATA
-				DDRSS0_CTL_297_DATA
-				DDRSS0_CTL_298_DATA
-				DDRSS0_CTL_299_DATA
-				DDRSS0_CTL_300_DATA
-				DDRSS0_CTL_301_DATA
-				DDRSS0_CTL_302_DATA
-				DDRSS0_CTL_303_DATA
-				DDRSS0_CTL_304_DATA
-				DDRSS0_CTL_305_DATA
-				DDRSS0_CTL_306_DATA
-				DDRSS0_CTL_307_DATA
-				DDRSS0_CTL_308_DATA
-				DDRSS0_CTL_309_DATA
-				DDRSS0_CTL_310_DATA
-				DDRSS0_CTL_311_DATA
-				DDRSS0_CTL_312_DATA
-				DDRSS0_CTL_313_DATA
-				DDRSS0_CTL_314_DATA
-				DDRSS0_CTL_315_DATA
-				DDRSS0_CTL_316_DATA
-				DDRSS0_CTL_317_DATA
-				DDRSS0_CTL_318_DATA
-				DDRSS0_CTL_319_DATA
-				DDRSS0_CTL_320_DATA
-				DDRSS0_CTL_321_DATA
-				DDRSS0_CTL_322_DATA
-				DDRSS0_CTL_323_DATA
-				DDRSS0_CTL_324_DATA
-				DDRSS0_CTL_325_DATA
-				DDRSS0_CTL_326_DATA
-				DDRSS0_CTL_327_DATA
-				DDRSS0_CTL_328_DATA
-				DDRSS0_CTL_329_DATA
-				DDRSS0_CTL_330_DATA
-				DDRSS0_CTL_331_DATA
-				DDRSS0_CTL_332_DATA
-				DDRSS0_CTL_333_DATA
-				DDRSS0_CTL_334_DATA
-				DDRSS0_CTL_335_DATA
-				DDRSS0_CTL_336_DATA
-				DDRSS0_CTL_337_DATA
-				DDRSS0_CTL_338_DATA
-				DDRSS0_CTL_339_DATA
-				DDRSS0_CTL_340_DATA
-				DDRSS0_CTL_341_DATA
-				DDRSS0_CTL_342_DATA
-				DDRSS0_CTL_343_DATA
-				DDRSS0_CTL_344_DATA
-				DDRSS0_CTL_345_DATA
-				DDRSS0_CTL_346_DATA
-				DDRSS0_CTL_347_DATA
-				DDRSS0_CTL_348_DATA
-				DDRSS0_CTL_349_DATA
-				DDRSS0_CTL_350_DATA
-				DDRSS0_CTL_351_DATA
-				DDRSS0_CTL_352_DATA
-				DDRSS0_CTL_353_DATA
-				DDRSS0_CTL_354_DATA
-				DDRSS0_CTL_355_DATA
-				DDRSS0_CTL_356_DATA
-				DDRSS0_CTL_357_DATA
-				DDRSS0_CTL_358_DATA
-				DDRSS0_CTL_359_DATA
-				DDRSS0_CTL_360_DATA
-				DDRSS0_CTL_361_DATA
-				DDRSS0_CTL_362_DATA
-				DDRSS0_CTL_363_DATA
-				DDRSS0_CTL_364_DATA
-				DDRSS0_CTL_365_DATA
-				DDRSS0_CTL_366_DATA
-				DDRSS0_CTL_367_DATA
-				DDRSS0_CTL_368_DATA
-				DDRSS0_CTL_369_DATA
-				DDRSS0_CTL_370_DATA
-				DDRSS0_CTL_371_DATA
-				DDRSS0_CTL_372_DATA
-				DDRSS0_CTL_373_DATA
-				DDRSS0_CTL_374_DATA
-				DDRSS0_CTL_375_DATA
-				DDRSS0_CTL_376_DATA
-				DDRSS0_CTL_377_DATA
-				DDRSS0_CTL_378_DATA
-				DDRSS0_CTL_379_DATA
-				DDRSS0_CTL_380_DATA
-				DDRSS0_CTL_381_DATA
-				DDRSS0_CTL_382_DATA
-				DDRSS0_CTL_383_DATA
-				DDRSS0_CTL_384_DATA
-				DDRSS0_CTL_385_DATA
-				DDRSS0_CTL_386_DATA
-				DDRSS0_CTL_387_DATA
-				DDRSS0_CTL_388_DATA
-				DDRSS0_CTL_389_DATA
-				DDRSS0_CTL_390_DATA
-				DDRSS0_CTL_391_DATA
-				DDRSS0_CTL_392_DATA
-				DDRSS0_CTL_393_DATA
-				DDRSS0_CTL_394_DATA
-				DDRSS0_CTL_395_DATA
-				DDRSS0_CTL_396_DATA
-				DDRSS0_CTL_397_DATA
-				DDRSS0_CTL_398_DATA
-				DDRSS0_CTL_399_DATA
-				DDRSS0_CTL_400_DATA
-				DDRSS0_CTL_401_DATA
-				DDRSS0_CTL_402_DATA
-				DDRSS0_CTL_403_DATA
-				DDRSS0_CTL_404_DATA
-				DDRSS0_CTL_405_DATA
-				DDRSS0_CTL_406_DATA
-				DDRSS0_CTL_407_DATA
-				DDRSS0_CTL_408_DATA
-				DDRSS0_CTL_409_DATA
-				DDRSS0_CTL_410_DATA
-				DDRSS0_CTL_411_DATA
-				DDRSS0_CTL_412_DATA
-				DDRSS0_CTL_413_DATA
-				DDRSS0_CTL_414_DATA
-				DDRSS0_CTL_415_DATA
-				DDRSS0_CTL_416_DATA
-				DDRSS0_CTL_417_DATA
-				DDRSS0_CTL_418_DATA
-				DDRSS0_CTL_419_DATA
-				DDRSS0_CTL_420_DATA
-				DDRSS0_CTL_421_DATA
-				DDRSS0_CTL_422_DATA
-				DDRSS0_CTL_423_DATA
-				DDRSS0_CTL_424_DATA
-				DDRSS0_CTL_425_DATA
-				DDRSS0_CTL_426_DATA
-				DDRSS0_CTL_427_DATA
-				DDRSS0_CTL_428_DATA
-				DDRSS0_CTL_429_DATA
-				DDRSS0_CTL_430_DATA
-				DDRSS0_CTL_431_DATA
-				DDRSS0_CTL_432_DATA
-				DDRSS0_CTL_433_DATA
-				DDRSS0_CTL_434_DATA
-				DDRSS0_CTL_435_DATA
-				DDRSS0_CTL_436_DATA
-				DDRSS0_CTL_437_DATA
-				DDRSS0_CTL_438_DATA
-				DDRSS0_CTL_439_DATA
-				DDRSS0_CTL_440_DATA
-				DDRSS0_CTL_441_DATA
-				DDRSS0_CTL_442_DATA
-				DDRSS0_CTL_443_DATA
-				DDRSS0_CTL_444_DATA
-				DDRSS0_CTL_445_DATA
-				DDRSS0_CTL_446_DATA
-				DDRSS0_CTL_447_DATA
-				DDRSS0_CTL_448_DATA
-				DDRSS0_CTL_449_DATA
-				DDRSS0_CTL_450_DATA
-				DDRSS0_CTL_451_DATA
-				DDRSS0_CTL_452_DATA
-				DDRSS0_CTL_453_DATA
-				DDRSS0_CTL_454_DATA
-				DDRSS0_CTL_455_DATA
-				DDRSS0_CTL_456_DATA
-				DDRSS0_CTL_457_DATA
-				DDRSS0_CTL_458_DATA
-			>;
-
-			ti,pi-data = <
-				DDRSS0_PI_00_DATA
-				DDRSS0_PI_01_DATA
-				DDRSS0_PI_02_DATA
-				DDRSS0_PI_03_DATA
-				DDRSS0_PI_04_DATA
-				DDRSS0_PI_05_DATA
-				DDRSS0_PI_06_DATA
-				DDRSS0_PI_07_DATA
-				DDRSS0_PI_08_DATA
-				DDRSS0_PI_09_DATA
-				DDRSS0_PI_10_DATA
-				DDRSS0_PI_11_DATA
-				DDRSS0_PI_12_DATA
-				DDRSS0_PI_13_DATA
-				DDRSS0_PI_14_DATA
-				DDRSS0_PI_15_DATA
-				DDRSS0_PI_16_DATA
-				DDRSS0_PI_17_DATA
-				DDRSS0_PI_18_DATA
-				DDRSS0_PI_19_DATA
-				DDRSS0_PI_20_DATA
-				DDRSS0_PI_21_DATA
-				DDRSS0_PI_22_DATA
-				DDRSS0_PI_23_DATA
-				DDRSS0_PI_24_DATA
-				DDRSS0_PI_25_DATA
-				DDRSS0_PI_26_DATA
-				DDRSS0_PI_27_DATA
-				DDRSS0_PI_28_DATA
-				DDRSS0_PI_29_DATA
-				DDRSS0_PI_30_DATA
-				DDRSS0_PI_31_DATA
-				DDRSS0_PI_32_DATA
-				DDRSS0_PI_33_DATA
-				DDRSS0_PI_34_DATA
-				DDRSS0_PI_35_DATA
-				DDRSS0_PI_36_DATA
-				DDRSS0_PI_37_DATA
-				DDRSS0_PI_38_DATA
-				DDRSS0_PI_39_DATA
-				DDRSS0_PI_40_DATA
-				DDRSS0_PI_41_DATA
-				DDRSS0_PI_42_DATA
-				DDRSS0_PI_43_DATA
-				DDRSS0_PI_44_DATA
-				DDRSS0_PI_45_DATA
-				DDRSS0_PI_46_DATA
-				DDRSS0_PI_47_DATA
-				DDRSS0_PI_48_DATA
-				DDRSS0_PI_49_DATA
-				DDRSS0_PI_50_DATA
-				DDRSS0_PI_51_DATA
-				DDRSS0_PI_52_DATA
-				DDRSS0_PI_53_DATA
-				DDRSS0_PI_54_DATA
-				DDRSS0_PI_55_DATA
-				DDRSS0_PI_56_DATA
-				DDRSS0_PI_57_DATA
-				DDRSS0_PI_58_DATA
-				DDRSS0_PI_59_DATA
-				DDRSS0_PI_60_DATA
-				DDRSS0_PI_61_DATA
-				DDRSS0_PI_62_DATA
-				DDRSS0_PI_63_DATA
-				DDRSS0_PI_64_DATA
-				DDRSS0_PI_65_DATA
-				DDRSS0_PI_66_DATA
-				DDRSS0_PI_67_DATA
-				DDRSS0_PI_68_DATA
-				DDRSS0_PI_69_DATA
-				DDRSS0_PI_70_DATA
-				DDRSS0_PI_71_DATA
-				DDRSS0_PI_72_DATA
-				DDRSS0_PI_73_DATA
-				DDRSS0_PI_74_DATA
-				DDRSS0_PI_75_DATA
-				DDRSS0_PI_76_DATA
-				DDRSS0_PI_77_DATA
-				DDRSS0_PI_78_DATA
-				DDRSS0_PI_79_DATA
-				DDRSS0_PI_80_DATA
-				DDRSS0_PI_81_DATA
-				DDRSS0_PI_82_DATA
-				DDRSS0_PI_83_DATA
-				DDRSS0_PI_84_DATA
-				DDRSS0_PI_85_DATA
-				DDRSS0_PI_86_DATA
-				DDRSS0_PI_87_DATA
-				DDRSS0_PI_88_DATA
-				DDRSS0_PI_89_DATA
-				DDRSS0_PI_90_DATA
-				DDRSS0_PI_91_DATA
-				DDRSS0_PI_92_DATA
-				DDRSS0_PI_93_DATA
-				DDRSS0_PI_94_DATA
-				DDRSS0_PI_95_DATA
-				DDRSS0_PI_96_DATA
-				DDRSS0_PI_97_DATA
-				DDRSS0_PI_98_DATA
-				DDRSS0_PI_99_DATA
-				DDRSS0_PI_100_DATA
-				DDRSS0_PI_101_DATA
-				DDRSS0_PI_102_DATA
-				DDRSS0_PI_103_DATA
-				DDRSS0_PI_104_DATA
-				DDRSS0_PI_105_DATA
-				DDRSS0_PI_106_DATA
-				DDRSS0_PI_107_DATA
-				DDRSS0_PI_108_DATA
-				DDRSS0_PI_109_DATA
-				DDRSS0_PI_110_DATA
-				DDRSS0_PI_111_DATA
-				DDRSS0_PI_112_DATA
-				DDRSS0_PI_113_DATA
-				DDRSS0_PI_114_DATA
-				DDRSS0_PI_115_DATA
-				DDRSS0_PI_116_DATA
-				DDRSS0_PI_117_DATA
-				DDRSS0_PI_118_DATA
-				DDRSS0_PI_119_DATA
-				DDRSS0_PI_120_DATA
-				DDRSS0_PI_121_DATA
-				DDRSS0_PI_122_DATA
-				DDRSS0_PI_123_DATA
-				DDRSS0_PI_124_DATA
-				DDRSS0_PI_125_DATA
-				DDRSS0_PI_126_DATA
-				DDRSS0_PI_127_DATA
-				DDRSS0_PI_128_DATA
-				DDRSS0_PI_129_DATA
-				DDRSS0_PI_130_DATA
-				DDRSS0_PI_131_DATA
-				DDRSS0_PI_132_DATA
-				DDRSS0_PI_133_DATA
-				DDRSS0_PI_134_DATA
-				DDRSS0_PI_135_DATA
-				DDRSS0_PI_136_DATA
-				DDRSS0_PI_137_DATA
-				DDRSS0_PI_138_DATA
-				DDRSS0_PI_139_DATA
-				DDRSS0_PI_140_DATA
-				DDRSS0_PI_141_DATA
-				DDRSS0_PI_142_DATA
-				DDRSS0_PI_143_DATA
-				DDRSS0_PI_144_DATA
-				DDRSS0_PI_145_DATA
-				DDRSS0_PI_146_DATA
-				DDRSS0_PI_147_DATA
-				DDRSS0_PI_148_DATA
-				DDRSS0_PI_149_DATA
-				DDRSS0_PI_150_DATA
-				DDRSS0_PI_151_DATA
-				DDRSS0_PI_152_DATA
-				DDRSS0_PI_153_DATA
-				DDRSS0_PI_154_DATA
-				DDRSS0_PI_155_DATA
-				DDRSS0_PI_156_DATA
-				DDRSS0_PI_157_DATA
-				DDRSS0_PI_158_DATA
-				DDRSS0_PI_159_DATA
-				DDRSS0_PI_160_DATA
-				DDRSS0_PI_161_DATA
-				DDRSS0_PI_162_DATA
-				DDRSS0_PI_163_DATA
-				DDRSS0_PI_164_DATA
-				DDRSS0_PI_165_DATA
-				DDRSS0_PI_166_DATA
-				DDRSS0_PI_167_DATA
-				DDRSS0_PI_168_DATA
-				DDRSS0_PI_169_DATA
-				DDRSS0_PI_170_DATA
-				DDRSS0_PI_171_DATA
-				DDRSS0_PI_172_DATA
-				DDRSS0_PI_173_DATA
-				DDRSS0_PI_174_DATA
-				DDRSS0_PI_175_DATA
-				DDRSS0_PI_176_DATA
-				DDRSS0_PI_177_DATA
-				DDRSS0_PI_178_DATA
-				DDRSS0_PI_179_DATA
-				DDRSS0_PI_180_DATA
-				DDRSS0_PI_181_DATA
-				DDRSS0_PI_182_DATA
-				DDRSS0_PI_183_DATA
-				DDRSS0_PI_184_DATA
-				DDRSS0_PI_185_DATA
-				DDRSS0_PI_186_DATA
-				DDRSS0_PI_187_DATA
-				DDRSS0_PI_188_DATA
-				DDRSS0_PI_189_DATA
-				DDRSS0_PI_190_DATA
-				DDRSS0_PI_191_DATA
-				DDRSS0_PI_192_DATA
-				DDRSS0_PI_193_DATA
-				DDRSS0_PI_194_DATA
-				DDRSS0_PI_195_DATA
-				DDRSS0_PI_196_DATA
-				DDRSS0_PI_197_DATA
-				DDRSS0_PI_198_DATA
-				DDRSS0_PI_199_DATA
-				DDRSS0_PI_200_DATA
-				DDRSS0_PI_201_DATA
-				DDRSS0_PI_202_DATA
-				DDRSS0_PI_203_DATA
-				DDRSS0_PI_204_DATA
-				DDRSS0_PI_205_DATA
-				DDRSS0_PI_206_DATA
-				DDRSS0_PI_207_DATA
-				DDRSS0_PI_208_DATA
-				DDRSS0_PI_209_DATA
-				DDRSS0_PI_210_DATA
-				DDRSS0_PI_211_DATA
-				DDRSS0_PI_212_DATA
-				DDRSS0_PI_213_DATA
-				DDRSS0_PI_214_DATA
-				DDRSS0_PI_215_DATA
-				DDRSS0_PI_216_DATA
-				DDRSS0_PI_217_DATA
-				DDRSS0_PI_218_DATA
-				DDRSS0_PI_219_DATA
-				DDRSS0_PI_220_DATA
-				DDRSS0_PI_221_DATA
-				DDRSS0_PI_222_DATA
-				DDRSS0_PI_223_DATA
-				DDRSS0_PI_224_DATA
-				DDRSS0_PI_225_DATA
-				DDRSS0_PI_226_DATA
-				DDRSS0_PI_227_DATA
-				DDRSS0_PI_228_DATA
-				DDRSS0_PI_229_DATA
-				DDRSS0_PI_230_DATA
-				DDRSS0_PI_231_DATA
-				DDRSS0_PI_232_DATA
-				DDRSS0_PI_233_DATA
-				DDRSS0_PI_234_DATA
-				DDRSS0_PI_235_DATA
-				DDRSS0_PI_236_DATA
-				DDRSS0_PI_237_DATA
-				DDRSS0_PI_238_DATA
-				DDRSS0_PI_239_DATA
-				DDRSS0_PI_240_DATA
-				DDRSS0_PI_241_DATA
-				DDRSS0_PI_242_DATA
-				DDRSS0_PI_243_DATA
-				DDRSS0_PI_244_DATA
-				DDRSS0_PI_245_DATA
-				DDRSS0_PI_246_DATA
-				DDRSS0_PI_247_DATA
-				DDRSS0_PI_248_DATA
-				DDRSS0_PI_249_DATA
-				DDRSS0_PI_250_DATA
-				DDRSS0_PI_251_DATA
-				DDRSS0_PI_252_DATA
-				DDRSS0_PI_253_DATA
-				DDRSS0_PI_254_DATA
-				DDRSS0_PI_255_DATA
-				DDRSS0_PI_256_DATA
-				DDRSS0_PI_257_DATA
-				DDRSS0_PI_258_DATA
-				DDRSS0_PI_259_DATA
-				DDRSS0_PI_260_DATA
-				DDRSS0_PI_261_DATA
-				DDRSS0_PI_262_DATA
-				DDRSS0_PI_263_DATA
-				DDRSS0_PI_264_DATA
-				DDRSS0_PI_265_DATA
-				DDRSS0_PI_266_DATA
-				DDRSS0_PI_267_DATA
-				DDRSS0_PI_268_DATA
-				DDRSS0_PI_269_DATA
-				DDRSS0_PI_270_DATA
-				DDRSS0_PI_271_DATA
-				DDRSS0_PI_272_DATA
-				DDRSS0_PI_273_DATA
-				DDRSS0_PI_274_DATA
-				DDRSS0_PI_275_DATA
-				DDRSS0_PI_276_DATA
-				DDRSS0_PI_277_DATA
-				DDRSS0_PI_278_DATA
-				DDRSS0_PI_279_DATA
-				DDRSS0_PI_280_DATA
-				DDRSS0_PI_281_DATA
-				DDRSS0_PI_282_DATA
-				DDRSS0_PI_283_DATA
-				DDRSS0_PI_284_DATA
-				DDRSS0_PI_285_DATA
-				DDRSS0_PI_286_DATA
-				DDRSS0_PI_287_DATA
-				DDRSS0_PI_288_DATA
-				DDRSS0_PI_289_DATA
-				DDRSS0_PI_290_DATA
-				DDRSS0_PI_291_DATA
-				DDRSS0_PI_292_DATA
-				DDRSS0_PI_293_DATA
-				DDRSS0_PI_294_DATA
-				DDRSS0_PI_295_DATA
-				DDRSS0_PI_296_DATA
-				DDRSS0_PI_297_DATA
-				DDRSS0_PI_298_DATA
-				DDRSS0_PI_299_DATA
-			>;
-
-			ti,phy-data = <
-				DDRSS0_PHY_00_DATA
-				DDRSS0_PHY_01_DATA
-				DDRSS0_PHY_02_DATA
-				DDRSS0_PHY_03_DATA
-				DDRSS0_PHY_04_DATA
-				DDRSS0_PHY_05_DATA
-				DDRSS0_PHY_06_DATA
-				DDRSS0_PHY_07_DATA
-				DDRSS0_PHY_08_DATA
-				DDRSS0_PHY_09_DATA
-				DDRSS0_PHY_10_DATA
-				DDRSS0_PHY_11_DATA
-				DDRSS0_PHY_12_DATA
-				DDRSS0_PHY_13_DATA
-				DDRSS0_PHY_14_DATA
-				DDRSS0_PHY_15_DATA
-				DDRSS0_PHY_16_DATA
-				DDRSS0_PHY_17_DATA
-				DDRSS0_PHY_18_DATA
-				DDRSS0_PHY_19_DATA
-				DDRSS0_PHY_20_DATA
-				DDRSS0_PHY_21_DATA
-				DDRSS0_PHY_22_DATA
-				DDRSS0_PHY_23_DATA
-				DDRSS0_PHY_24_DATA
-				DDRSS0_PHY_25_DATA
-				DDRSS0_PHY_26_DATA
-				DDRSS0_PHY_27_DATA
-				DDRSS0_PHY_28_DATA
-				DDRSS0_PHY_29_DATA
-				DDRSS0_PHY_30_DATA
-				DDRSS0_PHY_31_DATA
-				DDRSS0_PHY_32_DATA
-				DDRSS0_PHY_33_DATA
-				DDRSS0_PHY_34_DATA
-				DDRSS0_PHY_35_DATA
-				DDRSS0_PHY_36_DATA
-				DDRSS0_PHY_37_DATA
-				DDRSS0_PHY_38_DATA
-				DDRSS0_PHY_39_DATA
-				DDRSS0_PHY_40_DATA
-				DDRSS0_PHY_41_DATA
-				DDRSS0_PHY_42_DATA
-				DDRSS0_PHY_43_DATA
-				DDRSS0_PHY_44_DATA
-				DDRSS0_PHY_45_DATA
-				DDRSS0_PHY_46_DATA
-				DDRSS0_PHY_47_DATA
-				DDRSS0_PHY_48_DATA
-				DDRSS0_PHY_49_DATA
-				DDRSS0_PHY_50_DATA
-				DDRSS0_PHY_51_DATA
-				DDRSS0_PHY_52_DATA
-				DDRSS0_PHY_53_DATA
-				DDRSS0_PHY_54_DATA
-				DDRSS0_PHY_55_DATA
-				DDRSS0_PHY_56_DATA
-				DDRSS0_PHY_57_DATA
-				DDRSS0_PHY_58_DATA
-				DDRSS0_PHY_59_DATA
-				DDRSS0_PHY_60_DATA
-				DDRSS0_PHY_61_DATA
-				DDRSS0_PHY_62_DATA
-				DDRSS0_PHY_63_DATA
-				DDRSS0_PHY_64_DATA
-				DDRSS0_PHY_65_DATA
-				DDRSS0_PHY_66_DATA
-				DDRSS0_PHY_67_DATA
-				DDRSS0_PHY_68_DATA
-				DDRSS0_PHY_69_DATA
-				DDRSS0_PHY_70_DATA
-				DDRSS0_PHY_71_DATA
-				DDRSS0_PHY_72_DATA
-				DDRSS0_PHY_73_DATA
-				DDRSS0_PHY_74_DATA
-				DDRSS0_PHY_75_DATA
-				DDRSS0_PHY_76_DATA
-				DDRSS0_PHY_77_DATA
-				DDRSS0_PHY_78_DATA
-				DDRSS0_PHY_79_DATA
-				DDRSS0_PHY_80_DATA
-				DDRSS0_PHY_81_DATA
-				DDRSS0_PHY_82_DATA
-				DDRSS0_PHY_83_DATA
-				DDRSS0_PHY_84_DATA
-				DDRSS0_PHY_85_DATA
-				DDRSS0_PHY_86_DATA
-				DDRSS0_PHY_87_DATA
-				DDRSS0_PHY_88_DATA
-				DDRSS0_PHY_89_DATA
-				DDRSS0_PHY_90_DATA
-				DDRSS0_PHY_91_DATA
-				DDRSS0_PHY_92_DATA
-				DDRSS0_PHY_93_DATA
-				DDRSS0_PHY_94_DATA
-				DDRSS0_PHY_95_DATA
-				DDRSS0_PHY_96_DATA
-				DDRSS0_PHY_97_DATA
-				DDRSS0_PHY_98_DATA
-				DDRSS0_PHY_99_DATA
-				DDRSS0_PHY_100_DATA
-				DDRSS0_PHY_101_DATA
-				DDRSS0_PHY_102_DATA
-				DDRSS0_PHY_103_DATA
-				DDRSS0_PHY_104_DATA
-				DDRSS0_PHY_105_DATA
-				DDRSS0_PHY_106_DATA
-				DDRSS0_PHY_107_DATA
-				DDRSS0_PHY_108_DATA
-				DDRSS0_PHY_109_DATA
-				DDRSS0_PHY_110_DATA
-				DDRSS0_PHY_111_DATA
-				DDRSS0_PHY_112_DATA
-				DDRSS0_PHY_113_DATA
-				DDRSS0_PHY_114_DATA
-				DDRSS0_PHY_115_DATA
-				DDRSS0_PHY_116_DATA
-				DDRSS0_PHY_117_DATA
-				DDRSS0_PHY_118_DATA
-				DDRSS0_PHY_119_DATA
-				DDRSS0_PHY_120_DATA
-				DDRSS0_PHY_121_DATA
-				DDRSS0_PHY_122_DATA
-				DDRSS0_PHY_123_DATA
-				DDRSS0_PHY_124_DATA
-				DDRSS0_PHY_125_DATA
-				DDRSS0_PHY_126_DATA
-				DDRSS0_PHY_127_DATA
-				DDRSS0_PHY_128_DATA
-				DDRSS0_PHY_129_DATA
-				DDRSS0_PHY_130_DATA
-				DDRSS0_PHY_131_DATA
-				DDRSS0_PHY_132_DATA
-				DDRSS0_PHY_133_DATA
-				DDRSS0_PHY_134_DATA
-				DDRSS0_PHY_135_DATA
-				DDRSS0_PHY_136_DATA
-				DDRSS0_PHY_137_DATA
-				DDRSS0_PHY_138_DATA
-				DDRSS0_PHY_139_DATA
-				DDRSS0_PHY_140_DATA
-				DDRSS0_PHY_141_DATA
-				DDRSS0_PHY_142_DATA
-				DDRSS0_PHY_143_DATA
-				DDRSS0_PHY_144_DATA
-				DDRSS0_PHY_145_DATA
-				DDRSS0_PHY_146_DATA
-				DDRSS0_PHY_147_DATA
-				DDRSS0_PHY_148_DATA
-				DDRSS0_PHY_149_DATA
-				DDRSS0_PHY_150_DATA
-				DDRSS0_PHY_151_DATA
-				DDRSS0_PHY_152_DATA
-				DDRSS0_PHY_153_DATA
-				DDRSS0_PHY_154_DATA
-				DDRSS0_PHY_155_DATA
-				DDRSS0_PHY_156_DATA
-				DDRSS0_PHY_157_DATA
-				DDRSS0_PHY_158_DATA
-				DDRSS0_PHY_159_DATA
-				DDRSS0_PHY_160_DATA
-				DDRSS0_PHY_161_DATA
-				DDRSS0_PHY_162_DATA
-				DDRSS0_PHY_163_DATA
-				DDRSS0_PHY_164_DATA
-				DDRSS0_PHY_165_DATA
-				DDRSS0_PHY_166_DATA
-				DDRSS0_PHY_167_DATA
-				DDRSS0_PHY_168_DATA
-				DDRSS0_PHY_169_DATA
-				DDRSS0_PHY_170_DATA
-				DDRSS0_PHY_171_DATA
-				DDRSS0_PHY_172_DATA
-				DDRSS0_PHY_173_DATA
-				DDRSS0_PHY_174_DATA
-				DDRSS0_PHY_175_DATA
-				DDRSS0_PHY_176_DATA
-				DDRSS0_PHY_177_DATA
-				DDRSS0_PHY_178_DATA
-				DDRSS0_PHY_179_DATA
-				DDRSS0_PHY_180_DATA
-				DDRSS0_PHY_181_DATA
-				DDRSS0_PHY_182_DATA
-				DDRSS0_PHY_183_DATA
-				DDRSS0_PHY_184_DATA
-				DDRSS0_PHY_185_DATA
-				DDRSS0_PHY_186_DATA
-				DDRSS0_PHY_187_DATA
-				DDRSS0_PHY_188_DATA
-				DDRSS0_PHY_189_DATA
-				DDRSS0_PHY_190_DATA
-				DDRSS0_PHY_191_DATA
-				DDRSS0_PHY_192_DATA
-				DDRSS0_PHY_193_DATA
-				DDRSS0_PHY_194_DATA
-				DDRSS0_PHY_195_DATA
-				DDRSS0_PHY_196_DATA
-				DDRSS0_PHY_197_DATA
-				DDRSS0_PHY_198_DATA
-				DDRSS0_PHY_199_DATA
-				DDRSS0_PHY_200_DATA
-				DDRSS0_PHY_201_DATA
-				DDRSS0_PHY_202_DATA
-				DDRSS0_PHY_203_DATA
-				DDRSS0_PHY_204_DATA
-				DDRSS0_PHY_205_DATA
-				DDRSS0_PHY_206_DATA
-				DDRSS0_PHY_207_DATA
-				DDRSS0_PHY_208_DATA
-				DDRSS0_PHY_209_DATA
-				DDRSS0_PHY_210_DATA
-				DDRSS0_PHY_211_DATA
-				DDRSS0_PHY_212_DATA
-				DDRSS0_PHY_213_DATA
-				DDRSS0_PHY_214_DATA
-				DDRSS0_PHY_215_DATA
-				DDRSS0_PHY_216_DATA
-				DDRSS0_PHY_217_DATA
-				DDRSS0_PHY_218_DATA
-				DDRSS0_PHY_219_DATA
-				DDRSS0_PHY_220_DATA
-				DDRSS0_PHY_221_DATA
-				DDRSS0_PHY_222_DATA
-				DDRSS0_PHY_223_DATA
-				DDRSS0_PHY_224_DATA
-				DDRSS0_PHY_225_DATA
-				DDRSS0_PHY_226_DATA
-				DDRSS0_PHY_227_DATA
-				DDRSS0_PHY_228_DATA
-				DDRSS0_PHY_229_DATA
-				DDRSS0_PHY_230_DATA
-				DDRSS0_PHY_231_DATA
-				DDRSS0_PHY_232_DATA
-				DDRSS0_PHY_233_DATA
-				DDRSS0_PHY_234_DATA
-				DDRSS0_PHY_235_DATA
-				DDRSS0_PHY_236_DATA
-				DDRSS0_PHY_237_DATA
-				DDRSS0_PHY_238_DATA
-				DDRSS0_PHY_239_DATA
-				DDRSS0_PHY_240_DATA
-				DDRSS0_PHY_241_DATA
-				DDRSS0_PHY_242_DATA
-				DDRSS0_PHY_243_DATA
-				DDRSS0_PHY_244_DATA
-				DDRSS0_PHY_245_DATA
-				DDRSS0_PHY_246_DATA
-				DDRSS0_PHY_247_DATA
-				DDRSS0_PHY_248_DATA
-				DDRSS0_PHY_249_DATA
-				DDRSS0_PHY_250_DATA
-				DDRSS0_PHY_251_DATA
-				DDRSS0_PHY_252_DATA
-				DDRSS0_PHY_253_DATA
-				DDRSS0_PHY_254_DATA
-				DDRSS0_PHY_255_DATA
-				DDRSS0_PHY_256_DATA
-				DDRSS0_PHY_257_DATA
-				DDRSS0_PHY_258_DATA
-				DDRSS0_PHY_259_DATA
-				DDRSS0_PHY_260_DATA
-				DDRSS0_PHY_261_DATA
-				DDRSS0_PHY_262_DATA
-				DDRSS0_PHY_263_DATA
-				DDRSS0_PHY_264_DATA
-				DDRSS0_PHY_265_DATA
-				DDRSS0_PHY_266_DATA
-				DDRSS0_PHY_267_DATA
-				DDRSS0_PHY_268_DATA
-				DDRSS0_PHY_269_DATA
-				DDRSS0_PHY_270_DATA
-				DDRSS0_PHY_271_DATA
-				DDRSS0_PHY_272_DATA
-				DDRSS0_PHY_273_DATA
-				DDRSS0_PHY_274_DATA
-				DDRSS0_PHY_275_DATA
-				DDRSS0_PHY_276_DATA
-				DDRSS0_PHY_277_DATA
-				DDRSS0_PHY_278_DATA
-				DDRSS0_PHY_279_DATA
-				DDRSS0_PHY_280_DATA
-				DDRSS0_PHY_281_DATA
-				DDRSS0_PHY_282_DATA
-				DDRSS0_PHY_283_DATA
-				DDRSS0_PHY_284_DATA
-				DDRSS0_PHY_285_DATA
-				DDRSS0_PHY_286_DATA
-				DDRSS0_PHY_287_DATA
-				DDRSS0_PHY_288_DATA
-				DDRSS0_PHY_289_DATA
-				DDRSS0_PHY_290_DATA
-				DDRSS0_PHY_291_DATA
-				DDRSS0_PHY_292_DATA
-				DDRSS0_PHY_293_DATA
-				DDRSS0_PHY_294_DATA
-				DDRSS0_PHY_295_DATA
-				DDRSS0_PHY_296_DATA
-				DDRSS0_PHY_297_DATA
-				DDRSS0_PHY_298_DATA
-				DDRSS0_PHY_299_DATA
-				DDRSS0_PHY_300_DATA
-				DDRSS0_PHY_301_DATA
-				DDRSS0_PHY_302_DATA
-				DDRSS0_PHY_303_DATA
-				DDRSS0_PHY_304_DATA
-				DDRSS0_PHY_305_DATA
-				DDRSS0_PHY_306_DATA
-				DDRSS0_PHY_307_DATA
-				DDRSS0_PHY_308_DATA
-				DDRSS0_PHY_309_DATA
-				DDRSS0_PHY_310_DATA
-				DDRSS0_PHY_311_DATA
-				DDRSS0_PHY_312_DATA
-				DDRSS0_PHY_313_DATA
-				DDRSS0_PHY_314_DATA
-				DDRSS0_PHY_315_DATA
-				DDRSS0_PHY_316_DATA
-				DDRSS0_PHY_317_DATA
-				DDRSS0_PHY_318_DATA
-				DDRSS0_PHY_319_DATA
-				DDRSS0_PHY_320_DATA
-				DDRSS0_PHY_321_DATA
-				DDRSS0_PHY_322_DATA
-				DDRSS0_PHY_323_DATA
-				DDRSS0_PHY_324_DATA
-				DDRSS0_PHY_325_DATA
-				DDRSS0_PHY_326_DATA
-				DDRSS0_PHY_327_DATA
-				DDRSS0_PHY_328_DATA
-				DDRSS0_PHY_329_DATA
-				DDRSS0_PHY_330_DATA
-				DDRSS0_PHY_331_DATA
-				DDRSS0_PHY_332_DATA
-				DDRSS0_PHY_333_DATA
-				DDRSS0_PHY_334_DATA
-				DDRSS0_PHY_335_DATA
-				DDRSS0_PHY_336_DATA
-				DDRSS0_PHY_337_DATA
-				DDRSS0_PHY_338_DATA
-				DDRSS0_PHY_339_DATA
-				DDRSS0_PHY_340_DATA
-				DDRSS0_PHY_341_DATA
-				DDRSS0_PHY_342_DATA
-				DDRSS0_PHY_343_DATA
-				DDRSS0_PHY_344_DATA
-				DDRSS0_PHY_345_DATA
-				DDRSS0_PHY_346_DATA
-				DDRSS0_PHY_347_DATA
-				DDRSS0_PHY_348_DATA
-				DDRSS0_PHY_349_DATA
-				DDRSS0_PHY_350_DATA
-				DDRSS0_PHY_351_DATA
-				DDRSS0_PHY_352_DATA
-				DDRSS0_PHY_353_DATA
-				DDRSS0_PHY_354_DATA
-				DDRSS0_PHY_355_DATA
-				DDRSS0_PHY_356_DATA
-				DDRSS0_PHY_357_DATA
-				DDRSS0_PHY_358_DATA
-				DDRSS0_PHY_359_DATA
-				DDRSS0_PHY_360_DATA
-				DDRSS0_PHY_361_DATA
-				DDRSS0_PHY_362_DATA
-				DDRSS0_PHY_363_DATA
-				DDRSS0_PHY_364_DATA
-				DDRSS0_PHY_365_DATA
-				DDRSS0_PHY_366_DATA
-				DDRSS0_PHY_367_DATA
-				DDRSS0_PHY_368_DATA
-				DDRSS0_PHY_369_DATA
-				DDRSS0_PHY_370_DATA
-				DDRSS0_PHY_371_DATA
-				DDRSS0_PHY_372_DATA
-				DDRSS0_PHY_373_DATA
-				DDRSS0_PHY_374_DATA
-				DDRSS0_PHY_375_DATA
-				DDRSS0_PHY_376_DATA
-				DDRSS0_PHY_377_DATA
-				DDRSS0_PHY_378_DATA
-				DDRSS0_PHY_379_DATA
-				DDRSS0_PHY_380_DATA
-				DDRSS0_PHY_381_DATA
-				DDRSS0_PHY_382_DATA
-				DDRSS0_PHY_383_DATA
-				DDRSS0_PHY_384_DATA
-				DDRSS0_PHY_385_DATA
-				DDRSS0_PHY_386_DATA
-				DDRSS0_PHY_387_DATA
-				DDRSS0_PHY_388_DATA
-				DDRSS0_PHY_389_DATA
-				DDRSS0_PHY_390_DATA
-				DDRSS0_PHY_391_DATA
-				DDRSS0_PHY_392_DATA
-				DDRSS0_PHY_393_DATA
-				DDRSS0_PHY_394_DATA
-				DDRSS0_PHY_395_DATA
-				DDRSS0_PHY_396_DATA
-				DDRSS0_PHY_397_DATA
-				DDRSS0_PHY_398_DATA
-				DDRSS0_PHY_399_DATA
-				DDRSS0_PHY_400_DATA
-				DDRSS0_PHY_401_DATA
-				DDRSS0_PHY_402_DATA
-				DDRSS0_PHY_403_DATA
-				DDRSS0_PHY_404_DATA
-				DDRSS0_PHY_405_DATA
-				DDRSS0_PHY_406_DATA
-				DDRSS0_PHY_407_DATA
-				DDRSS0_PHY_408_DATA
-				DDRSS0_PHY_409_DATA
-				DDRSS0_PHY_410_DATA
-				DDRSS0_PHY_411_DATA
-				DDRSS0_PHY_412_DATA
-				DDRSS0_PHY_413_DATA
-				DDRSS0_PHY_414_DATA
-				DDRSS0_PHY_415_DATA
-				DDRSS0_PHY_416_DATA
-				DDRSS0_PHY_417_DATA
-				DDRSS0_PHY_418_DATA
-				DDRSS0_PHY_419_DATA
-				DDRSS0_PHY_420_DATA
-				DDRSS0_PHY_421_DATA
-				DDRSS0_PHY_422_DATA
-				DDRSS0_PHY_423_DATA
-				DDRSS0_PHY_424_DATA
-				DDRSS0_PHY_425_DATA
-				DDRSS0_PHY_426_DATA
-				DDRSS0_PHY_427_DATA
-				DDRSS0_PHY_428_DATA
-				DDRSS0_PHY_429_DATA
-				DDRSS0_PHY_430_DATA
-				DDRSS0_PHY_431_DATA
-				DDRSS0_PHY_432_DATA
-				DDRSS0_PHY_433_DATA
-				DDRSS0_PHY_434_DATA
-				DDRSS0_PHY_435_DATA
-				DDRSS0_PHY_436_DATA
-				DDRSS0_PHY_437_DATA
-				DDRSS0_PHY_438_DATA
-				DDRSS0_PHY_439_DATA
-				DDRSS0_PHY_440_DATA
-				DDRSS0_PHY_441_DATA
-				DDRSS0_PHY_442_DATA
-				DDRSS0_PHY_443_DATA
-				DDRSS0_PHY_444_DATA
-				DDRSS0_PHY_445_DATA
-				DDRSS0_PHY_446_DATA
-				DDRSS0_PHY_447_DATA
-				DDRSS0_PHY_448_DATA
-				DDRSS0_PHY_449_DATA
-				DDRSS0_PHY_450_DATA
-				DDRSS0_PHY_451_DATA
-				DDRSS0_PHY_452_DATA
-				DDRSS0_PHY_453_DATA
-				DDRSS0_PHY_454_DATA
-				DDRSS0_PHY_455_DATA
-				DDRSS0_PHY_456_DATA
-				DDRSS0_PHY_457_DATA
-				DDRSS0_PHY_458_DATA
-				DDRSS0_PHY_459_DATA
-				DDRSS0_PHY_460_DATA
-				DDRSS0_PHY_461_DATA
-				DDRSS0_PHY_462_DATA
-				DDRSS0_PHY_463_DATA
-				DDRSS0_PHY_464_DATA
-				DDRSS0_PHY_465_DATA
-				DDRSS0_PHY_466_DATA
-				DDRSS0_PHY_467_DATA
-				DDRSS0_PHY_468_DATA
-				DDRSS0_PHY_469_DATA
-				DDRSS0_PHY_470_DATA
-				DDRSS0_PHY_471_DATA
-				DDRSS0_PHY_472_DATA
-				DDRSS0_PHY_473_DATA
-				DDRSS0_PHY_474_DATA
-				DDRSS0_PHY_475_DATA
-				DDRSS0_PHY_476_DATA
-				DDRSS0_PHY_477_DATA
-				DDRSS0_PHY_478_DATA
-				DDRSS0_PHY_479_DATA
-				DDRSS0_PHY_480_DATA
-				DDRSS0_PHY_481_DATA
-				DDRSS0_PHY_482_DATA
-				DDRSS0_PHY_483_DATA
-				DDRSS0_PHY_484_DATA
-				DDRSS0_PHY_485_DATA
-				DDRSS0_PHY_486_DATA
-				DDRSS0_PHY_487_DATA
-				DDRSS0_PHY_488_DATA
-				DDRSS0_PHY_489_DATA
-				DDRSS0_PHY_490_DATA
-				DDRSS0_PHY_491_DATA
-				DDRSS0_PHY_492_DATA
-				DDRSS0_PHY_493_DATA
-				DDRSS0_PHY_494_DATA
-				DDRSS0_PHY_495_DATA
-				DDRSS0_PHY_496_DATA
-				DDRSS0_PHY_497_DATA
-				DDRSS0_PHY_498_DATA
-				DDRSS0_PHY_499_DATA
-				DDRSS0_PHY_500_DATA
-				DDRSS0_PHY_501_DATA
-				DDRSS0_PHY_502_DATA
-				DDRSS0_PHY_503_DATA
-				DDRSS0_PHY_504_DATA
-				DDRSS0_PHY_505_DATA
-				DDRSS0_PHY_506_DATA
-				DDRSS0_PHY_507_DATA
-				DDRSS0_PHY_508_DATA
-				DDRSS0_PHY_509_DATA
-				DDRSS0_PHY_510_DATA
-				DDRSS0_PHY_511_DATA
-				DDRSS0_PHY_512_DATA
-				DDRSS0_PHY_513_DATA
-				DDRSS0_PHY_514_DATA
-				DDRSS0_PHY_515_DATA
-				DDRSS0_PHY_516_DATA
-				DDRSS0_PHY_517_DATA
-				DDRSS0_PHY_518_DATA
-				DDRSS0_PHY_519_DATA
-				DDRSS0_PHY_520_DATA
-				DDRSS0_PHY_521_DATA
-				DDRSS0_PHY_522_DATA
-				DDRSS0_PHY_523_DATA
-				DDRSS0_PHY_524_DATA
-				DDRSS0_PHY_525_DATA
-				DDRSS0_PHY_526_DATA
-				DDRSS0_PHY_527_DATA
-				DDRSS0_PHY_528_DATA
-				DDRSS0_PHY_529_DATA
-				DDRSS0_PHY_530_DATA
-				DDRSS0_PHY_531_DATA
-				DDRSS0_PHY_532_DATA
-				DDRSS0_PHY_533_DATA
-				DDRSS0_PHY_534_DATA
-				DDRSS0_PHY_535_DATA
-				DDRSS0_PHY_536_DATA
-				DDRSS0_PHY_537_DATA
-				DDRSS0_PHY_538_DATA
-				DDRSS0_PHY_539_DATA
-				DDRSS0_PHY_540_DATA
-				DDRSS0_PHY_541_DATA
-				DDRSS0_PHY_542_DATA
-				DDRSS0_PHY_543_DATA
-				DDRSS0_PHY_544_DATA
-				DDRSS0_PHY_545_DATA
-				DDRSS0_PHY_546_DATA
-				DDRSS0_PHY_547_DATA
-				DDRSS0_PHY_548_DATA
-				DDRSS0_PHY_549_DATA
-				DDRSS0_PHY_550_DATA
-				DDRSS0_PHY_551_DATA
-				DDRSS0_PHY_552_DATA
-				DDRSS0_PHY_553_DATA
-				DDRSS0_PHY_554_DATA
-				DDRSS0_PHY_555_DATA
-				DDRSS0_PHY_556_DATA
-				DDRSS0_PHY_557_DATA
-				DDRSS0_PHY_558_DATA
-				DDRSS0_PHY_559_DATA
-				DDRSS0_PHY_560_DATA
-				DDRSS0_PHY_561_DATA
-				DDRSS0_PHY_562_DATA
-				DDRSS0_PHY_563_DATA
-				DDRSS0_PHY_564_DATA
-				DDRSS0_PHY_565_DATA
-				DDRSS0_PHY_566_DATA
-				DDRSS0_PHY_567_DATA
-				DDRSS0_PHY_568_DATA
-				DDRSS0_PHY_569_DATA
-				DDRSS0_PHY_570_DATA
-				DDRSS0_PHY_571_DATA
-				DDRSS0_PHY_572_DATA
-				DDRSS0_PHY_573_DATA
-				DDRSS0_PHY_574_DATA
-				DDRSS0_PHY_575_DATA
-				DDRSS0_PHY_576_DATA
-				DDRSS0_PHY_577_DATA
-				DDRSS0_PHY_578_DATA
-				DDRSS0_PHY_579_DATA
-				DDRSS0_PHY_580_DATA
-				DDRSS0_PHY_581_DATA
-				DDRSS0_PHY_582_DATA
-				DDRSS0_PHY_583_DATA
-				DDRSS0_PHY_584_DATA
-				DDRSS0_PHY_585_DATA
-				DDRSS0_PHY_586_DATA
-				DDRSS0_PHY_587_DATA
-				DDRSS0_PHY_588_DATA
-				DDRSS0_PHY_589_DATA
-				DDRSS0_PHY_590_DATA
-				DDRSS0_PHY_591_DATA
-				DDRSS0_PHY_592_DATA
-				DDRSS0_PHY_593_DATA
-				DDRSS0_PHY_594_DATA
-				DDRSS0_PHY_595_DATA
-				DDRSS0_PHY_596_DATA
-				DDRSS0_PHY_597_DATA
-				DDRSS0_PHY_598_DATA
-				DDRSS0_PHY_599_DATA
-				DDRSS0_PHY_600_DATA
-				DDRSS0_PHY_601_DATA
-				DDRSS0_PHY_602_DATA
-				DDRSS0_PHY_603_DATA
-				DDRSS0_PHY_604_DATA
-				DDRSS0_PHY_605_DATA
-				DDRSS0_PHY_606_DATA
-				DDRSS0_PHY_607_DATA
-				DDRSS0_PHY_608_DATA
-				DDRSS0_PHY_609_DATA
-				DDRSS0_PHY_610_DATA
-				DDRSS0_PHY_611_DATA
-				DDRSS0_PHY_612_DATA
-				DDRSS0_PHY_613_DATA
-				DDRSS0_PHY_614_DATA
-				DDRSS0_PHY_615_DATA
-				DDRSS0_PHY_616_DATA
-				DDRSS0_PHY_617_DATA
-				DDRSS0_PHY_618_DATA
-				DDRSS0_PHY_619_DATA
-				DDRSS0_PHY_620_DATA
-				DDRSS0_PHY_621_DATA
-				DDRSS0_PHY_622_DATA
-				DDRSS0_PHY_623_DATA
-				DDRSS0_PHY_624_DATA
-				DDRSS0_PHY_625_DATA
-				DDRSS0_PHY_626_DATA
-				DDRSS0_PHY_627_DATA
-				DDRSS0_PHY_628_DATA
-				DDRSS0_PHY_629_DATA
-				DDRSS0_PHY_630_DATA
-				DDRSS0_PHY_631_DATA
-				DDRSS0_PHY_632_DATA
-				DDRSS0_PHY_633_DATA
-				DDRSS0_PHY_634_DATA
-				DDRSS0_PHY_635_DATA
-				DDRSS0_PHY_636_DATA
-				DDRSS0_PHY_637_DATA
-				DDRSS0_PHY_638_DATA
-				DDRSS0_PHY_639_DATA
-				DDRSS0_PHY_640_DATA
-				DDRSS0_PHY_641_DATA
-				DDRSS0_PHY_642_DATA
-				DDRSS0_PHY_643_DATA
-				DDRSS0_PHY_644_DATA
-				DDRSS0_PHY_645_DATA
-				DDRSS0_PHY_646_DATA
-				DDRSS0_PHY_647_DATA
-				DDRSS0_PHY_648_DATA
-				DDRSS0_PHY_649_DATA
-				DDRSS0_PHY_650_DATA
-				DDRSS0_PHY_651_DATA
-				DDRSS0_PHY_652_DATA
-				DDRSS0_PHY_653_DATA
-				DDRSS0_PHY_654_DATA
-				DDRSS0_PHY_655_DATA
-				DDRSS0_PHY_656_DATA
-				DDRSS0_PHY_657_DATA
-				DDRSS0_PHY_658_DATA
-				DDRSS0_PHY_659_DATA
-				DDRSS0_PHY_660_DATA
-				DDRSS0_PHY_661_DATA
-				DDRSS0_PHY_662_DATA
-				DDRSS0_PHY_663_DATA
-				DDRSS0_PHY_664_DATA
-				DDRSS0_PHY_665_DATA
-				DDRSS0_PHY_666_DATA
-				DDRSS0_PHY_667_DATA
-				DDRSS0_PHY_668_DATA
-				DDRSS0_PHY_669_DATA
-				DDRSS0_PHY_670_DATA
-				DDRSS0_PHY_671_DATA
-				DDRSS0_PHY_672_DATA
-				DDRSS0_PHY_673_DATA
-				DDRSS0_PHY_674_DATA
-				DDRSS0_PHY_675_DATA
-				DDRSS0_PHY_676_DATA
-				DDRSS0_PHY_677_DATA
-				DDRSS0_PHY_678_DATA
-				DDRSS0_PHY_679_DATA
-				DDRSS0_PHY_680_DATA
-				DDRSS0_PHY_681_DATA
-				DDRSS0_PHY_682_DATA
-				DDRSS0_PHY_683_DATA
-				DDRSS0_PHY_684_DATA
-				DDRSS0_PHY_685_DATA
-				DDRSS0_PHY_686_DATA
-				DDRSS0_PHY_687_DATA
-				DDRSS0_PHY_688_DATA
-				DDRSS0_PHY_689_DATA
-				DDRSS0_PHY_690_DATA
-				DDRSS0_PHY_691_DATA
-				DDRSS0_PHY_692_DATA
-				DDRSS0_PHY_693_DATA
-				DDRSS0_PHY_694_DATA
-				DDRSS0_PHY_695_DATA
-				DDRSS0_PHY_696_DATA
-				DDRSS0_PHY_697_DATA
-				DDRSS0_PHY_698_DATA
-				DDRSS0_PHY_699_DATA
-				DDRSS0_PHY_700_DATA
-				DDRSS0_PHY_701_DATA
-				DDRSS0_PHY_702_DATA
-				DDRSS0_PHY_703_DATA
-				DDRSS0_PHY_704_DATA
-				DDRSS0_PHY_705_DATA
-				DDRSS0_PHY_706_DATA
-				DDRSS0_PHY_707_DATA
-				DDRSS0_PHY_708_DATA
-				DDRSS0_PHY_709_DATA
-				DDRSS0_PHY_710_DATA
-				DDRSS0_PHY_711_DATA
-				DDRSS0_PHY_712_DATA
-				DDRSS0_PHY_713_DATA
-				DDRSS0_PHY_714_DATA
-				DDRSS0_PHY_715_DATA
-				DDRSS0_PHY_716_DATA
-				DDRSS0_PHY_717_DATA
-				DDRSS0_PHY_718_DATA
-				DDRSS0_PHY_719_DATA
-				DDRSS0_PHY_720_DATA
-				DDRSS0_PHY_721_DATA
-				DDRSS0_PHY_722_DATA
-				DDRSS0_PHY_723_DATA
-				DDRSS0_PHY_724_DATA
-				DDRSS0_PHY_725_DATA
-				DDRSS0_PHY_726_DATA
-				DDRSS0_PHY_727_DATA
-				DDRSS0_PHY_728_DATA
-				DDRSS0_PHY_729_DATA
-				DDRSS0_PHY_730_DATA
-				DDRSS0_PHY_731_DATA
-				DDRSS0_PHY_732_DATA
-				DDRSS0_PHY_733_DATA
-				DDRSS0_PHY_734_DATA
-				DDRSS0_PHY_735_DATA
-				DDRSS0_PHY_736_DATA
-				DDRSS0_PHY_737_DATA
-				DDRSS0_PHY_738_DATA
-				DDRSS0_PHY_739_DATA
-				DDRSS0_PHY_740_DATA
-				DDRSS0_PHY_741_DATA
-				DDRSS0_PHY_742_DATA
-				DDRSS0_PHY_743_DATA
-				DDRSS0_PHY_744_DATA
-				DDRSS0_PHY_745_DATA
-				DDRSS0_PHY_746_DATA
-				DDRSS0_PHY_747_DATA
-				DDRSS0_PHY_748_DATA
-				DDRSS0_PHY_749_DATA
-				DDRSS0_PHY_750_DATA
-				DDRSS0_PHY_751_DATA
-				DDRSS0_PHY_752_DATA
-				DDRSS0_PHY_753_DATA
-				DDRSS0_PHY_754_DATA
-				DDRSS0_PHY_755_DATA
-				DDRSS0_PHY_756_DATA
-				DDRSS0_PHY_757_DATA
-				DDRSS0_PHY_758_DATA
-				DDRSS0_PHY_759_DATA
-				DDRSS0_PHY_760_DATA
-				DDRSS0_PHY_761_DATA
-				DDRSS0_PHY_762_DATA
-				DDRSS0_PHY_763_DATA
-				DDRSS0_PHY_764_DATA
-				DDRSS0_PHY_765_DATA
-				DDRSS0_PHY_766_DATA
-				DDRSS0_PHY_767_DATA
-				DDRSS0_PHY_768_DATA
-				DDRSS0_PHY_769_DATA
-				DDRSS0_PHY_770_DATA
-				DDRSS0_PHY_771_DATA
-				DDRSS0_PHY_772_DATA
-				DDRSS0_PHY_773_DATA
-				DDRSS0_PHY_774_DATA
-				DDRSS0_PHY_775_DATA
-				DDRSS0_PHY_776_DATA
-				DDRSS0_PHY_777_DATA
-				DDRSS0_PHY_778_DATA
-				DDRSS0_PHY_779_DATA
-				DDRSS0_PHY_780_DATA
-				DDRSS0_PHY_781_DATA
-				DDRSS0_PHY_782_DATA
-				DDRSS0_PHY_783_DATA
-				DDRSS0_PHY_784_DATA
-				DDRSS0_PHY_785_DATA
-				DDRSS0_PHY_786_DATA
-				DDRSS0_PHY_787_DATA
-				DDRSS0_PHY_788_DATA
-				DDRSS0_PHY_789_DATA
-				DDRSS0_PHY_790_DATA
-				DDRSS0_PHY_791_DATA
-				DDRSS0_PHY_792_DATA
-				DDRSS0_PHY_793_DATA
-				DDRSS0_PHY_794_DATA
-				DDRSS0_PHY_795_DATA
-				DDRSS0_PHY_796_DATA
-				DDRSS0_PHY_797_DATA
-				DDRSS0_PHY_798_DATA
-				DDRSS0_PHY_799_DATA
-				DDRSS0_PHY_800_DATA
-				DDRSS0_PHY_801_DATA
-				DDRSS0_PHY_802_DATA
-				DDRSS0_PHY_803_DATA
-				DDRSS0_PHY_804_DATA
-				DDRSS0_PHY_805_DATA
-				DDRSS0_PHY_806_DATA
-				DDRSS0_PHY_807_DATA
-				DDRSS0_PHY_808_DATA
-				DDRSS0_PHY_809_DATA
-				DDRSS0_PHY_810_DATA
-				DDRSS0_PHY_811_DATA
-				DDRSS0_PHY_812_DATA
-				DDRSS0_PHY_813_DATA
-				DDRSS0_PHY_814_DATA
-				DDRSS0_PHY_815_DATA
-				DDRSS0_PHY_816_DATA
-				DDRSS0_PHY_817_DATA
-				DDRSS0_PHY_818_DATA
-				DDRSS0_PHY_819_DATA
-				DDRSS0_PHY_820_DATA
-				DDRSS0_PHY_821_DATA
-				DDRSS0_PHY_822_DATA
-				DDRSS0_PHY_823_DATA
-				DDRSS0_PHY_824_DATA
-				DDRSS0_PHY_825_DATA
-				DDRSS0_PHY_826_DATA
-				DDRSS0_PHY_827_DATA
-				DDRSS0_PHY_828_DATA
-				DDRSS0_PHY_829_DATA
-				DDRSS0_PHY_830_DATA
-				DDRSS0_PHY_831_DATA
-				DDRSS0_PHY_832_DATA
-				DDRSS0_PHY_833_DATA
-				DDRSS0_PHY_834_DATA
-				DDRSS0_PHY_835_DATA
-				DDRSS0_PHY_836_DATA
-				DDRSS0_PHY_837_DATA
-				DDRSS0_PHY_838_DATA
-				DDRSS0_PHY_839_DATA
-				DDRSS0_PHY_840_DATA
-				DDRSS0_PHY_841_DATA
-				DDRSS0_PHY_842_DATA
-				DDRSS0_PHY_843_DATA
-				DDRSS0_PHY_844_DATA
-				DDRSS0_PHY_845_DATA
-				DDRSS0_PHY_846_DATA
-				DDRSS0_PHY_847_DATA
-				DDRSS0_PHY_848_DATA
-				DDRSS0_PHY_849_DATA
-				DDRSS0_PHY_850_DATA
-				DDRSS0_PHY_851_DATA
-				DDRSS0_PHY_852_DATA
-				DDRSS0_PHY_853_DATA
-				DDRSS0_PHY_854_DATA
-				DDRSS0_PHY_855_DATA
-				DDRSS0_PHY_856_DATA
-				DDRSS0_PHY_857_DATA
-				DDRSS0_PHY_858_DATA
-				DDRSS0_PHY_859_DATA
-				DDRSS0_PHY_860_DATA
-				DDRSS0_PHY_861_DATA
-				DDRSS0_PHY_862_DATA
-				DDRSS0_PHY_863_DATA
-				DDRSS0_PHY_864_DATA
-				DDRSS0_PHY_865_DATA
-				DDRSS0_PHY_866_DATA
-				DDRSS0_PHY_867_DATA
-				DDRSS0_PHY_868_DATA
-				DDRSS0_PHY_869_DATA
-				DDRSS0_PHY_870_DATA
-				DDRSS0_PHY_871_DATA
-				DDRSS0_PHY_872_DATA
-				DDRSS0_PHY_873_DATA
-				DDRSS0_PHY_874_DATA
-				DDRSS0_PHY_875_DATA
-				DDRSS0_PHY_876_DATA
-				DDRSS0_PHY_877_DATA
-				DDRSS0_PHY_878_DATA
-				DDRSS0_PHY_879_DATA
-				DDRSS0_PHY_880_DATA
-				DDRSS0_PHY_881_DATA
-				DDRSS0_PHY_882_DATA
-				DDRSS0_PHY_883_DATA
-				DDRSS0_PHY_884_DATA
-				DDRSS0_PHY_885_DATA
-				DDRSS0_PHY_886_DATA
-				DDRSS0_PHY_887_DATA
-				DDRSS0_PHY_888_DATA
-				DDRSS0_PHY_889_DATA
-				DDRSS0_PHY_890_DATA
-				DDRSS0_PHY_891_DATA
-				DDRSS0_PHY_892_DATA
-				DDRSS0_PHY_893_DATA
-				DDRSS0_PHY_894_DATA
-				DDRSS0_PHY_895_DATA
-				DDRSS0_PHY_896_DATA
-				DDRSS0_PHY_897_DATA
-				DDRSS0_PHY_898_DATA
-				DDRSS0_PHY_899_DATA
-				DDRSS0_PHY_900_DATA
-				DDRSS0_PHY_901_DATA
-				DDRSS0_PHY_902_DATA
-				DDRSS0_PHY_903_DATA
-				DDRSS0_PHY_904_DATA
-				DDRSS0_PHY_905_DATA
-				DDRSS0_PHY_906_DATA
-				DDRSS0_PHY_907_DATA
-				DDRSS0_PHY_908_DATA
-				DDRSS0_PHY_909_DATA
-				DDRSS0_PHY_910_DATA
-				DDRSS0_PHY_911_DATA
-				DDRSS0_PHY_912_DATA
-				DDRSS0_PHY_913_DATA
-				DDRSS0_PHY_914_DATA
-				DDRSS0_PHY_915_DATA
-				DDRSS0_PHY_916_DATA
-				DDRSS0_PHY_917_DATA
-				DDRSS0_PHY_918_DATA
-				DDRSS0_PHY_919_DATA
-				DDRSS0_PHY_920_DATA
-				DDRSS0_PHY_921_DATA
-				DDRSS0_PHY_922_DATA
-				DDRSS0_PHY_923_DATA
-				DDRSS0_PHY_924_DATA
-				DDRSS0_PHY_925_DATA
-				DDRSS0_PHY_926_DATA
-				DDRSS0_PHY_927_DATA
-				DDRSS0_PHY_928_DATA
-				DDRSS0_PHY_929_DATA
-				DDRSS0_PHY_930_DATA
-				DDRSS0_PHY_931_DATA
-				DDRSS0_PHY_932_DATA
-				DDRSS0_PHY_933_DATA
-				DDRSS0_PHY_934_DATA
-				DDRSS0_PHY_935_DATA
-				DDRSS0_PHY_936_DATA
-				DDRSS0_PHY_937_DATA
-				DDRSS0_PHY_938_DATA
-				DDRSS0_PHY_939_DATA
-				DDRSS0_PHY_940_DATA
-				DDRSS0_PHY_941_DATA
-				DDRSS0_PHY_942_DATA
-				DDRSS0_PHY_943_DATA
-				DDRSS0_PHY_944_DATA
-				DDRSS0_PHY_945_DATA
-				DDRSS0_PHY_946_DATA
-				DDRSS0_PHY_947_DATA
-				DDRSS0_PHY_948_DATA
-				DDRSS0_PHY_949_DATA
-				DDRSS0_PHY_950_DATA
-				DDRSS0_PHY_951_DATA
-				DDRSS0_PHY_952_DATA
-				DDRSS0_PHY_953_DATA
-				DDRSS0_PHY_954_DATA
-				DDRSS0_PHY_955_DATA
-				DDRSS0_PHY_956_DATA
-				DDRSS0_PHY_957_DATA
-				DDRSS0_PHY_958_DATA
-				DDRSS0_PHY_959_DATA
-				DDRSS0_PHY_960_DATA
-				DDRSS0_PHY_961_DATA
-				DDRSS0_PHY_962_DATA
-				DDRSS0_PHY_963_DATA
-				DDRSS0_PHY_964_DATA
-				DDRSS0_PHY_965_DATA
-				DDRSS0_PHY_966_DATA
-				DDRSS0_PHY_967_DATA
-				DDRSS0_PHY_968_DATA
-				DDRSS0_PHY_969_DATA
-				DDRSS0_PHY_970_DATA
-				DDRSS0_PHY_971_DATA
-				DDRSS0_PHY_972_DATA
-				DDRSS0_PHY_973_DATA
-				DDRSS0_PHY_974_DATA
-				DDRSS0_PHY_975_DATA
-				DDRSS0_PHY_976_DATA
-				DDRSS0_PHY_977_DATA
-				DDRSS0_PHY_978_DATA
-				DDRSS0_PHY_979_DATA
-				DDRSS0_PHY_980_DATA
-				DDRSS0_PHY_981_DATA
-				DDRSS0_PHY_982_DATA
-				DDRSS0_PHY_983_DATA
-				DDRSS0_PHY_984_DATA
-				DDRSS0_PHY_985_DATA
-				DDRSS0_PHY_986_DATA
-				DDRSS0_PHY_987_DATA
-				DDRSS0_PHY_988_DATA
-				DDRSS0_PHY_989_DATA
-				DDRSS0_PHY_990_DATA
-				DDRSS0_PHY_991_DATA
-				DDRSS0_PHY_992_DATA
-				DDRSS0_PHY_993_DATA
-				DDRSS0_PHY_994_DATA
-				DDRSS0_PHY_995_DATA
-				DDRSS0_PHY_996_DATA
-				DDRSS0_PHY_997_DATA
-				DDRSS0_PHY_998_DATA
-				DDRSS0_PHY_999_DATA
-				DDRSS0_PHY_1000_DATA
-				DDRSS0_PHY_1001_DATA
-				DDRSS0_PHY_1002_DATA
-				DDRSS0_PHY_1003_DATA
-				DDRSS0_PHY_1004_DATA
-				DDRSS0_PHY_1005_DATA
-				DDRSS0_PHY_1006_DATA
-				DDRSS0_PHY_1007_DATA
-				DDRSS0_PHY_1008_DATA
-				DDRSS0_PHY_1009_DATA
-				DDRSS0_PHY_1010_DATA
-				DDRSS0_PHY_1011_DATA
-				DDRSS0_PHY_1012_DATA
-				DDRSS0_PHY_1013_DATA
-				DDRSS0_PHY_1014_DATA
-				DDRSS0_PHY_1015_DATA
-				DDRSS0_PHY_1016_DATA
-				DDRSS0_PHY_1017_DATA
-				DDRSS0_PHY_1018_DATA
-				DDRSS0_PHY_1019_DATA
-				DDRSS0_PHY_1020_DATA
-				DDRSS0_PHY_1021_DATA
-				DDRSS0_PHY_1022_DATA
-				DDRSS0_PHY_1023_DATA
-				DDRSS0_PHY_1024_DATA
-				DDRSS0_PHY_1025_DATA
-				DDRSS0_PHY_1026_DATA
-				DDRSS0_PHY_1027_DATA
-				DDRSS0_PHY_1028_DATA
-				DDRSS0_PHY_1029_DATA
-				DDRSS0_PHY_1030_DATA
-				DDRSS0_PHY_1031_DATA
-				DDRSS0_PHY_1032_DATA
-				DDRSS0_PHY_1033_DATA
-				DDRSS0_PHY_1034_DATA
-				DDRSS0_PHY_1035_DATA
-				DDRSS0_PHY_1036_DATA
-				DDRSS0_PHY_1037_DATA
-				DDRSS0_PHY_1038_DATA
-				DDRSS0_PHY_1039_DATA
-				DDRSS0_PHY_1040_DATA
-				DDRSS0_PHY_1041_DATA
-				DDRSS0_PHY_1042_DATA
-				DDRSS0_PHY_1043_DATA
-				DDRSS0_PHY_1044_DATA
-				DDRSS0_PHY_1045_DATA
-				DDRSS0_PHY_1046_DATA
-				DDRSS0_PHY_1047_DATA
-				DDRSS0_PHY_1048_DATA
-				DDRSS0_PHY_1049_DATA
-				DDRSS0_PHY_1050_DATA
-				DDRSS0_PHY_1051_DATA
-				DDRSS0_PHY_1052_DATA
-				DDRSS0_PHY_1053_DATA
-				DDRSS0_PHY_1054_DATA
-				DDRSS0_PHY_1055_DATA
-				DDRSS0_PHY_1056_DATA
-				DDRSS0_PHY_1057_DATA
-				DDRSS0_PHY_1058_DATA
-				DDRSS0_PHY_1059_DATA
-				DDRSS0_PHY_1060_DATA
-				DDRSS0_PHY_1061_DATA
-				DDRSS0_PHY_1062_DATA
-				DDRSS0_PHY_1063_DATA
-				DDRSS0_PHY_1064_DATA
-				DDRSS0_PHY_1065_DATA
-				DDRSS0_PHY_1066_DATA
-				DDRSS0_PHY_1067_DATA
-				DDRSS0_PHY_1068_DATA
-				DDRSS0_PHY_1069_DATA
-				DDRSS0_PHY_1070_DATA
-				DDRSS0_PHY_1071_DATA
-				DDRSS0_PHY_1072_DATA
-				DDRSS0_PHY_1073_DATA
-				DDRSS0_PHY_1074_DATA
-				DDRSS0_PHY_1075_DATA
-				DDRSS0_PHY_1076_DATA
-				DDRSS0_PHY_1077_DATA
-				DDRSS0_PHY_1078_DATA
-				DDRSS0_PHY_1079_DATA
-				DDRSS0_PHY_1080_DATA
-				DDRSS0_PHY_1081_DATA
-				DDRSS0_PHY_1082_DATA
-				DDRSS0_PHY_1083_DATA
-				DDRSS0_PHY_1084_DATA
-				DDRSS0_PHY_1085_DATA
-				DDRSS0_PHY_1086_DATA
-				DDRSS0_PHY_1087_DATA
-				DDRSS0_PHY_1088_DATA
-				DDRSS0_PHY_1089_DATA
-				DDRSS0_PHY_1090_DATA
-				DDRSS0_PHY_1091_DATA
-				DDRSS0_PHY_1092_DATA
-				DDRSS0_PHY_1093_DATA
-				DDRSS0_PHY_1094_DATA
-				DDRSS0_PHY_1095_DATA
-				DDRSS0_PHY_1096_DATA
-				DDRSS0_PHY_1097_DATA
-				DDRSS0_PHY_1098_DATA
-				DDRSS0_PHY_1099_DATA
-				DDRSS0_PHY_1100_DATA
-				DDRSS0_PHY_1101_DATA
-				DDRSS0_PHY_1102_DATA
-				DDRSS0_PHY_1103_DATA
-				DDRSS0_PHY_1104_DATA
-				DDRSS0_PHY_1105_DATA
-				DDRSS0_PHY_1106_DATA
-				DDRSS0_PHY_1107_DATA
-				DDRSS0_PHY_1108_DATA
-				DDRSS0_PHY_1109_DATA
-				DDRSS0_PHY_1110_DATA
-				DDRSS0_PHY_1111_DATA
-				DDRSS0_PHY_1112_DATA
-				DDRSS0_PHY_1113_DATA
-				DDRSS0_PHY_1114_DATA
-				DDRSS0_PHY_1115_DATA
-				DDRSS0_PHY_1116_DATA
-				DDRSS0_PHY_1117_DATA
-				DDRSS0_PHY_1118_DATA
-				DDRSS0_PHY_1119_DATA
-				DDRSS0_PHY_1120_DATA
-				DDRSS0_PHY_1121_DATA
-				DDRSS0_PHY_1122_DATA
-				DDRSS0_PHY_1123_DATA
-				DDRSS0_PHY_1124_DATA
-				DDRSS0_PHY_1125_DATA
-				DDRSS0_PHY_1126_DATA
-				DDRSS0_PHY_1127_DATA
-				DDRSS0_PHY_1128_DATA
-				DDRSS0_PHY_1129_DATA
-				DDRSS0_PHY_1130_DATA
-				DDRSS0_PHY_1131_DATA
-				DDRSS0_PHY_1132_DATA
-				DDRSS0_PHY_1133_DATA
-				DDRSS0_PHY_1134_DATA
-				DDRSS0_PHY_1135_DATA
-				DDRSS0_PHY_1136_DATA
-				DDRSS0_PHY_1137_DATA
-				DDRSS0_PHY_1138_DATA
-				DDRSS0_PHY_1139_DATA
-				DDRSS0_PHY_1140_DATA
-				DDRSS0_PHY_1141_DATA
-				DDRSS0_PHY_1142_DATA
-				DDRSS0_PHY_1143_DATA
-				DDRSS0_PHY_1144_DATA
-				DDRSS0_PHY_1145_DATA
-				DDRSS0_PHY_1146_DATA
-				DDRSS0_PHY_1147_DATA
-				DDRSS0_PHY_1148_DATA
-				DDRSS0_PHY_1149_DATA
-				DDRSS0_PHY_1150_DATA
-				DDRSS0_PHY_1151_DATA
-				DDRSS0_PHY_1152_DATA
-				DDRSS0_PHY_1153_DATA
-				DDRSS0_PHY_1154_DATA
-				DDRSS0_PHY_1155_DATA
-				DDRSS0_PHY_1156_DATA
-				DDRSS0_PHY_1157_DATA
-				DDRSS0_PHY_1158_DATA
-				DDRSS0_PHY_1159_DATA
-				DDRSS0_PHY_1160_DATA
-				DDRSS0_PHY_1161_DATA
-				DDRSS0_PHY_1162_DATA
-				DDRSS0_PHY_1163_DATA
-				DDRSS0_PHY_1164_DATA
-				DDRSS0_PHY_1165_DATA
-				DDRSS0_PHY_1166_DATA
-				DDRSS0_PHY_1167_DATA
-				DDRSS0_PHY_1168_DATA
-				DDRSS0_PHY_1169_DATA
-				DDRSS0_PHY_1170_DATA
-				DDRSS0_PHY_1171_DATA
-				DDRSS0_PHY_1172_DATA
-				DDRSS0_PHY_1173_DATA
-				DDRSS0_PHY_1174_DATA
-				DDRSS0_PHY_1175_DATA
-				DDRSS0_PHY_1176_DATA
-				DDRSS0_PHY_1177_DATA
-				DDRSS0_PHY_1178_DATA
-				DDRSS0_PHY_1179_DATA
-				DDRSS0_PHY_1180_DATA
-				DDRSS0_PHY_1181_DATA
-				DDRSS0_PHY_1182_DATA
-				DDRSS0_PHY_1183_DATA
-				DDRSS0_PHY_1184_DATA
-				DDRSS0_PHY_1185_DATA
-				DDRSS0_PHY_1186_DATA
-				DDRSS0_PHY_1187_DATA
-				DDRSS0_PHY_1188_DATA
-				DDRSS0_PHY_1189_DATA
-				DDRSS0_PHY_1190_DATA
-				DDRSS0_PHY_1191_DATA
-				DDRSS0_PHY_1192_DATA
-				DDRSS0_PHY_1193_DATA
-				DDRSS0_PHY_1194_DATA
-				DDRSS0_PHY_1195_DATA
-				DDRSS0_PHY_1196_DATA
-				DDRSS0_PHY_1197_DATA
-				DDRSS0_PHY_1198_DATA
-				DDRSS0_PHY_1199_DATA
-				DDRSS0_PHY_1200_DATA
-				DDRSS0_PHY_1201_DATA
-				DDRSS0_PHY_1202_DATA
-				DDRSS0_PHY_1203_DATA
-				DDRSS0_PHY_1204_DATA
-				DDRSS0_PHY_1205_DATA
-				DDRSS0_PHY_1206_DATA
-				DDRSS0_PHY_1207_DATA
-				DDRSS0_PHY_1208_DATA
-				DDRSS0_PHY_1209_DATA
-				DDRSS0_PHY_1210_DATA
-				DDRSS0_PHY_1211_DATA
-				DDRSS0_PHY_1212_DATA
-				DDRSS0_PHY_1213_DATA
-				DDRSS0_PHY_1214_DATA
-				DDRSS0_PHY_1215_DATA
-				DDRSS0_PHY_1216_DATA
-				DDRSS0_PHY_1217_DATA
-				DDRSS0_PHY_1218_DATA
-				DDRSS0_PHY_1219_DATA
-				DDRSS0_PHY_1220_DATA
-				DDRSS0_PHY_1221_DATA
-				DDRSS0_PHY_1222_DATA
-				DDRSS0_PHY_1223_DATA
-				DDRSS0_PHY_1224_DATA
-				DDRSS0_PHY_1225_DATA
-				DDRSS0_PHY_1226_DATA
-				DDRSS0_PHY_1227_DATA
-				DDRSS0_PHY_1228_DATA
-				DDRSS0_PHY_1229_DATA
-				DDRSS0_PHY_1230_DATA
-				DDRSS0_PHY_1231_DATA
-				DDRSS0_PHY_1232_DATA
-				DDRSS0_PHY_1233_DATA
-				DDRSS0_PHY_1234_DATA
-				DDRSS0_PHY_1235_DATA
-				DDRSS0_PHY_1236_DATA
-				DDRSS0_PHY_1237_DATA
-				DDRSS0_PHY_1238_DATA
-				DDRSS0_PHY_1239_DATA
-				DDRSS0_PHY_1240_DATA
-				DDRSS0_PHY_1241_DATA
-				DDRSS0_PHY_1242_DATA
-				DDRSS0_PHY_1243_DATA
-				DDRSS0_PHY_1244_DATA
-				DDRSS0_PHY_1245_DATA
-				DDRSS0_PHY_1246_DATA
-				DDRSS0_PHY_1247_DATA
-				DDRSS0_PHY_1248_DATA
-				DDRSS0_PHY_1249_DATA
-				DDRSS0_PHY_1250_DATA
-				DDRSS0_PHY_1251_DATA
-				DDRSS0_PHY_1252_DATA
-				DDRSS0_PHY_1253_DATA
-				DDRSS0_PHY_1254_DATA
-				DDRSS0_PHY_1255_DATA
-				DDRSS0_PHY_1256_DATA
-				DDRSS0_PHY_1257_DATA
-				DDRSS0_PHY_1258_DATA
-				DDRSS0_PHY_1259_DATA
-				DDRSS0_PHY_1260_DATA
-				DDRSS0_PHY_1261_DATA
-				DDRSS0_PHY_1262_DATA
-				DDRSS0_PHY_1263_DATA
-				DDRSS0_PHY_1264_DATA
-				DDRSS0_PHY_1265_DATA
-				DDRSS0_PHY_1266_DATA
-				DDRSS0_PHY_1267_DATA
-				DDRSS0_PHY_1268_DATA
-				DDRSS0_PHY_1269_DATA
-				DDRSS0_PHY_1270_DATA
-				DDRSS0_PHY_1271_DATA
-				DDRSS0_PHY_1272_DATA
-				DDRSS0_PHY_1273_DATA
-				DDRSS0_PHY_1274_DATA
-				DDRSS0_PHY_1275_DATA
-				DDRSS0_PHY_1276_DATA
-				DDRSS0_PHY_1277_DATA
-				DDRSS0_PHY_1278_DATA
-				DDRSS0_PHY_1279_DATA
-				DDRSS0_PHY_1280_DATA
-				DDRSS0_PHY_1281_DATA
-				DDRSS0_PHY_1282_DATA
-				DDRSS0_PHY_1283_DATA
-				DDRSS0_PHY_1284_DATA
-				DDRSS0_PHY_1285_DATA
-				DDRSS0_PHY_1286_DATA
-				DDRSS0_PHY_1287_DATA
-				DDRSS0_PHY_1288_DATA
-				DDRSS0_PHY_1289_DATA
-				DDRSS0_PHY_1290_DATA
-				DDRSS0_PHY_1291_DATA
-				DDRSS0_PHY_1292_DATA
-				DDRSS0_PHY_1293_DATA
-				DDRSS0_PHY_1294_DATA
-				DDRSS0_PHY_1295_DATA
-				DDRSS0_PHY_1296_DATA
-				DDRSS0_PHY_1297_DATA
-				DDRSS0_PHY_1298_DATA
-				DDRSS0_PHY_1299_DATA
-				DDRSS0_PHY_1300_DATA
-				DDRSS0_PHY_1301_DATA
-				DDRSS0_PHY_1302_DATA
-				DDRSS0_PHY_1303_DATA
-				DDRSS0_PHY_1304_DATA
-				DDRSS0_PHY_1305_DATA
-				DDRSS0_PHY_1306_DATA
-				DDRSS0_PHY_1307_DATA
-				DDRSS0_PHY_1308_DATA
-				DDRSS0_PHY_1309_DATA
-				DDRSS0_PHY_1310_DATA
-				DDRSS0_PHY_1311_DATA
-				DDRSS0_PHY_1312_DATA
-				DDRSS0_PHY_1313_DATA
-				DDRSS0_PHY_1314_DATA
-				DDRSS0_PHY_1315_DATA
-				DDRSS0_PHY_1316_DATA
-				DDRSS0_PHY_1317_DATA
-				DDRSS0_PHY_1318_DATA
-				DDRSS0_PHY_1319_DATA
-				DDRSS0_PHY_1320_DATA
-				DDRSS0_PHY_1321_DATA
-				DDRSS0_PHY_1322_DATA
-				DDRSS0_PHY_1323_DATA
-				DDRSS0_PHY_1324_DATA
-				DDRSS0_PHY_1325_DATA
-				DDRSS0_PHY_1326_DATA
-				DDRSS0_PHY_1327_DATA
-				DDRSS0_PHY_1328_DATA
-				DDRSS0_PHY_1329_DATA
-				DDRSS0_PHY_1330_DATA
-				DDRSS0_PHY_1331_DATA
-				DDRSS0_PHY_1332_DATA
-				DDRSS0_PHY_1333_DATA
-				DDRSS0_PHY_1334_DATA
-				DDRSS0_PHY_1335_DATA
-				DDRSS0_PHY_1336_DATA
-				DDRSS0_PHY_1337_DATA
-				DDRSS0_PHY_1338_DATA
-				DDRSS0_PHY_1339_DATA
-				DDRSS0_PHY_1340_DATA
-				DDRSS0_PHY_1341_DATA
-				DDRSS0_PHY_1342_DATA
-				DDRSS0_PHY_1343_DATA
-				DDRSS0_PHY_1344_DATA
-				DDRSS0_PHY_1345_DATA
-				DDRSS0_PHY_1346_DATA
-				DDRSS0_PHY_1347_DATA
-				DDRSS0_PHY_1348_DATA
-				DDRSS0_PHY_1349_DATA
-				DDRSS0_PHY_1350_DATA
-				DDRSS0_PHY_1351_DATA
-				DDRSS0_PHY_1352_DATA
-				DDRSS0_PHY_1353_DATA
-				DDRSS0_PHY_1354_DATA
-				DDRSS0_PHY_1355_DATA
-				DDRSS0_PHY_1356_DATA
-				DDRSS0_PHY_1357_DATA
-				DDRSS0_PHY_1358_DATA
-				DDRSS0_PHY_1359_DATA
-				DDRSS0_PHY_1360_DATA
-				DDRSS0_PHY_1361_DATA
-				DDRSS0_PHY_1362_DATA
-				DDRSS0_PHY_1363_DATA
-				DDRSS0_PHY_1364_DATA
-				DDRSS0_PHY_1365_DATA
-				DDRSS0_PHY_1366_DATA
-				DDRSS0_PHY_1367_DATA
-				DDRSS0_PHY_1368_DATA
-				DDRSS0_PHY_1369_DATA
-				DDRSS0_PHY_1370_DATA
-				DDRSS0_PHY_1371_DATA
-				DDRSS0_PHY_1372_DATA
-				DDRSS0_PHY_1373_DATA
-				DDRSS0_PHY_1374_DATA
-				DDRSS0_PHY_1375_DATA
-				DDRSS0_PHY_1376_DATA
-				DDRSS0_PHY_1377_DATA
-				DDRSS0_PHY_1378_DATA
-				DDRSS0_PHY_1379_DATA
-				DDRSS0_PHY_1380_DATA
-				DDRSS0_PHY_1381_DATA
-				DDRSS0_PHY_1382_DATA
-				DDRSS0_PHY_1383_DATA
-				DDRSS0_PHY_1384_DATA
-				DDRSS0_PHY_1385_DATA
-				DDRSS0_PHY_1386_DATA
-				DDRSS0_PHY_1387_DATA
-				DDRSS0_PHY_1388_DATA
-				DDRSS0_PHY_1389_DATA
-				DDRSS0_PHY_1390_DATA
-				DDRSS0_PHY_1391_DATA
-				DDRSS0_PHY_1392_DATA
-				DDRSS0_PHY_1393_DATA
-				DDRSS0_PHY_1394_DATA
-				DDRSS0_PHY_1395_DATA
-				DDRSS0_PHY_1396_DATA
-				DDRSS0_PHY_1397_DATA
-				DDRSS0_PHY_1398_DATA
-				DDRSS0_PHY_1399_DATA
-				DDRSS0_PHY_1400_DATA
-				DDRSS0_PHY_1401_DATA
-				DDRSS0_PHY_1402_DATA
-				DDRSS0_PHY_1403_DATA
-				DDRSS0_PHY_1404_DATA
-				DDRSS0_PHY_1405_DATA
-				DDRSS0_PHY_1406_DATA
-				DDRSS0_PHY_1407_DATA
-				DDRSS0_PHY_1408_DATA
-				DDRSS0_PHY_1409_DATA
-				DDRSS0_PHY_1410_DATA
-				DDRSS0_PHY_1411_DATA
-				DDRSS0_PHY_1412_DATA
-				DDRSS0_PHY_1413_DATA
-				DDRSS0_PHY_1414_DATA
-				DDRSS0_PHY_1415_DATA
-				DDRSS0_PHY_1416_DATA
-				DDRSS0_PHY_1417_DATA
-				DDRSS0_PHY_1418_DATA
-				DDRSS0_PHY_1419_DATA
-				DDRSS0_PHY_1420_DATA
-				DDRSS0_PHY_1421_DATA
-				DDRSS0_PHY_1422_DATA
-			>;
-		};
-
-		memorycontroller1: memorycontroller@29b0000 {
-			compatible = "ti,j721s2-ddrss";
-			reg = <0x0 0x029b0000 0x0 0x4000>,
-			      <0x0 0x0114000 0x0 0x100>,
-			      <0x0 0x029a0000 0x0 0x200>;
-			reg-names = "cfg", "ctrl_mmr_lp4", "ss_cfg";
-			power-domains = <&k3_pds 192 TI_SCI_PD_SHARED>,
-				<&k3_pds 132 TI_SCI_PD_SHARED>;
-			clocks = <&k3_clks 192 1>, <&k3_clks 78 2>;
-			ti,ddr-freq0 = <DDRSS_PLL_FREQUENCY_0>;
-			ti,ddr-freq1 = <DDRSS_PLL_FREQUENCY_1>;
-			ti,ddr-freq2 = <DDRSS_PLL_FREQUENCY_2>;
-			ti,ddr-fhs-cnt = <DDRSS_PLL_FHS_CNT>;
-			instance = <1>;
-
-			bootph-pre-ram;
-
-			ti,ctl-data = <
-				DDRSS1_CTL_00_DATA
-				DDRSS1_CTL_01_DATA
-				DDRSS1_CTL_02_DATA
-				DDRSS1_CTL_03_DATA
-				DDRSS1_CTL_04_DATA
-				DDRSS1_CTL_05_DATA
-				DDRSS1_CTL_06_DATA
-				DDRSS1_CTL_07_DATA
-				DDRSS1_CTL_08_DATA
-				DDRSS1_CTL_09_DATA
-				DDRSS1_CTL_10_DATA
-				DDRSS1_CTL_11_DATA
-				DDRSS1_CTL_12_DATA
-				DDRSS1_CTL_13_DATA
-				DDRSS1_CTL_14_DATA
-				DDRSS1_CTL_15_DATA
-				DDRSS1_CTL_16_DATA
-				DDRSS1_CTL_17_DATA
-				DDRSS1_CTL_18_DATA
-				DDRSS1_CTL_19_DATA
-				DDRSS1_CTL_20_DATA
-				DDRSS1_CTL_21_DATA
-				DDRSS1_CTL_22_DATA
-				DDRSS1_CTL_23_DATA
-				DDRSS1_CTL_24_DATA
-				DDRSS1_CTL_25_DATA
-				DDRSS1_CTL_26_DATA
-				DDRSS1_CTL_27_DATA
-				DDRSS1_CTL_28_DATA
-				DDRSS1_CTL_29_DATA
-				DDRSS1_CTL_30_DATA
-				DDRSS1_CTL_31_DATA
-				DDRSS1_CTL_32_DATA
-				DDRSS1_CTL_33_DATA
-				DDRSS1_CTL_34_DATA
-				DDRSS1_CTL_35_DATA
-				DDRSS1_CTL_36_DATA
-				DDRSS1_CTL_37_DATA
-				DDRSS1_CTL_38_DATA
-				DDRSS1_CTL_39_DATA
-				DDRSS1_CTL_40_DATA
-				DDRSS1_CTL_41_DATA
-				DDRSS1_CTL_42_DATA
-				DDRSS1_CTL_43_DATA
-				DDRSS1_CTL_44_DATA
-				DDRSS1_CTL_45_DATA
-				DDRSS1_CTL_46_DATA
-				DDRSS1_CTL_47_DATA
-				DDRSS1_CTL_48_DATA
-				DDRSS1_CTL_49_DATA
-				DDRSS1_CTL_50_DATA
-				DDRSS1_CTL_51_DATA
-				DDRSS1_CTL_52_DATA
-				DDRSS1_CTL_53_DATA
-				DDRSS1_CTL_54_DATA
-				DDRSS1_CTL_55_DATA
-				DDRSS1_CTL_56_DATA
-				DDRSS1_CTL_57_DATA
-				DDRSS1_CTL_58_DATA
-				DDRSS1_CTL_59_DATA
-				DDRSS1_CTL_60_DATA
-				DDRSS1_CTL_61_DATA
-				DDRSS1_CTL_62_DATA
-				DDRSS1_CTL_63_DATA
-				DDRSS1_CTL_64_DATA
-				DDRSS1_CTL_65_DATA
-				DDRSS1_CTL_66_DATA
-				DDRSS1_CTL_67_DATA
-				DDRSS1_CTL_68_DATA
-				DDRSS1_CTL_69_DATA
-				DDRSS1_CTL_70_DATA
-				DDRSS1_CTL_71_DATA
-				DDRSS1_CTL_72_DATA
-				DDRSS1_CTL_73_DATA
-				DDRSS1_CTL_74_DATA
-				DDRSS1_CTL_75_DATA
-				DDRSS1_CTL_76_DATA
-				DDRSS1_CTL_77_DATA
-				DDRSS1_CTL_78_DATA
-				DDRSS1_CTL_79_DATA
-				DDRSS1_CTL_80_DATA
-				DDRSS1_CTL_81_DATA
-				DDRSS1_CTL_82_DATA
-				DDRSS1_CTL_83_DATA
-				DDRSS1_CTL_84_DATA
-				DDRSS1_CTL_85_DATA
-				DDRSS1_CTL_86_DATA
-				DDRSS1_CTL_87_DATA
-				DDRSS1_CTL_88_DATA
-				DDRSS1_CTL_89_DATA
-				DDRSS1_CTL_90_DATA
-				DDRSS1_CTL_91_DATA
-				DDRSS1_CTL_92_DATA
-				DDRSS1_CTL_93_DATA
-				DDRSS1_CTL_94_DATA
-				DDRSS1_CTL_95_DATA
-				DDRSS1_CTL_96_DATA
-				DDRSS1_CTL_97_DATA
-				DDRSS1_CTL_98_DATA
-				DDRSS1_CTL_99_DATA
-				DDRSS1_CTL_100_DATA
-				DDRSS1_CTL_101_DATA
-				DDRSS1_CTL_102_DATA
-				DDRSS1_CTL_103_DATA
-				DDRSS1_CTL_104_DATA
-				DDRSS1_CTL_105_DATA
-				DDRSS1_CTL_106_DATA
-				DDRSS1_CTL_107_DATA
-				DDRSS1_CTL_108_DATA
-				DDRSS1_CTL_109_DATA
-				DDRSS1_CTL_110_DATA
-				DDRSS1_CTL_111_DATA
-				DDRSS1_CTL_112_DATA
-				DDRSS1_CTL_113_DATA
-				DDRSS1_CTL_114_DATA
-				DDRSS1_CTL_115_DATA
-				DDRSS1_CTL_116_DATA
-				DDRSS1_CTL_117_DATA
-				DDRSS1_CTL_118_DATA
-				DDRSS1_CTL_119_DATA
-				DDRSS1_CTL_120_DATA
-				DDRSS1_CTL_121_DATA
-				DDRSS1_CTL_122_DATA
-				DDRSS1_CTL_123_DATA
-				DDRSS1_CTL_124_DATA
-				DDRSS1_CTL_125_DATA
-				DDRSS1_CTL_126_DATA
-				DDRSS1_CTL_127_DATA
-				DDRSS1_CTL_128_DATA
-				DDRSS1_CTL_129_DATA
-				DDRSS1_CTL_130_DATA
-				DDRSS1_CTL_131_DATA
-				DDRSS1_CTL_132_DATA
-				DDRSS1_CTL_133_DATA
-				DDRSS1_CTL_134_DATA
-				DDRSS1_CTL_135_DATA
-				DDRSS1_CTL_136_DATA
-				DDRSS1_CTL_137_DATA
-				DDRSS1_CTL_138_DATA
-				DDRSS1_CTL_139_DATA
-				DDRSS1_CTL_140_DATA
-				DDRSS1_CTL_141_DATA
-				DDRSS1_CTL_142_DATA
-				DDRSS1_CTL_143_DATA
-				DDRSS1_CTL_144_DATA
-				DDRSS1_CTL_145_DATA
-				DDRSS1_CTL_146_DATA
-				DDRSS1_CTL_147_DATA
-				DDRSS1_CTL_148_DATA
-				DDRSS1_CTL_149_DATA
-				DDRSS1_CTL_150_DATA
-				DDRSS1_CTL_151_DATA
-				DDRSS1_CTL_152_DATA
-				DDRSS1_CTL_153_DATA
-				DDRSS1_CTL_154_DATA
-				DDRSS1_CTL_155_DATA
-				DDRSS1_CTL_156_DATA
-				DDRSS1_CTL_157_DATA
-				DDRSS1_CTL_158_DATA
-				DDRSS1_CTL_159_DATA
-				DDRSS1_CTL_160_DATA
-				DDRSS1_CTL_161_DATA
-				DDRSS1_CTL_162_DATA
-				DDRSS1_CTL_163_DATA
-				DDRSS1_CTL_164_DATA
-				DDRSS1_CTL_165_DATA
-				DDRSS1_CTL_166_DATA
-				DDRSS1_CTL_167_DATA
-				DDRSS1_CTL_168_DATA
-				DDRSS1_CTL_169_DATA
-				DDRSS1_CTL_170_DATA
-				DDRSS1_CTL_171_DATA
-				DDRSS1_CTL_172_DATA
-				DDRSS1_CTL_173_DATA
-				DDRSS1_CTL_174_DATA
-				DDRSS1_CTL_175_DATA
-				DDRSS1_CTL_176_DATA
-				DDRSS1_CTL_177_DATA
-				DDRSS1_CTL_178_DATA
-				DDRSS1_CTL_179_DATA
-				DDRSS1_CTL_180_DATA
-				DDRSS1_CTL_181_DATA
-				DDRSS1_CTL_182_DATA
-				DDRSS1_CTL_183_DATA
-				DDRSS1_CTL_184_DATA
-				DDRSS1_CTL_185_DATA
-				DDRSS1_CTL_186_DATA
-				DDRSS1_CTL_187_DATA
-				DDRSS1_CTL_188_DATA
-				DDRSS1_CTL_189_DATA
-				DDRSS1_CTL_190_DATA
-				DDRSS1_CTL_191_DATA
-				DDRSS1_CTL_192_DATA
-				DDRSS1_CTL_193_DATA
-				DDRSS1_CTL_194_DATA
-				DDRSS1_CTL_195_DATA
-				DDRSS1_CTL_196_DATA
-				DDRSS1_CTL_197_DATA
-				DDRSS1_CTL_198_DATA
-				DDRSS1_CTL_199_DATA
-				DDRSS1_CTL_200_DATA
-				DDRSS1_CTL_201_DATA
-				DDRSS1_CTL_202_DATA
-				DDRSS1_CTL_203_DATA
-				DDRSS1_CTL_204_DATA
-				DDRSS1_CTL_205_DATA
-				DDRSS1_CTL_206_DATA
-				DDRSS1_CTL_207_DATA
-				DDRSS1_CTL_208_DATA
-				DDRSS1_CTL_209_DATA
-				DDRSS1_CTL_210_DATA
-				DDRSS1_CTL_211_DATA
-				DDRSS1_CTL_212_DATA
-				DDRSS1_CTL_213_DATA
-				DDRSS1_CTL_214_DATA
-				DDRSS1_CTL_215_DATA
-				DDRSS1_CTL_216_DATA
-				DDRSS1_CTL_217_DATA
-				DDRSS1_CTL_218_DATA
-				DDRSS1_CTL_219_DATA
-				DDRSS1_CTL_220_DATA
-				DDRSS1_CTL_221_DATA
-				DDRSS1_CTL_222_DATA
-				DDRSS1_CTL_223_DATA
-				DDRSS1_CTL_224_DATA
-				DDRSS1_CTL_225_DATA
-				DDRSS1_CTL_226_DATA
-				DDRSS1_CTL_227_DATA
-				DDRSS1_CTL_228_DATA
-				DDRSS1_CTL_229_DATA
-				DDRSS1_CTL_230_DATA
-				DDRSS1_CTL_231_DATA
-				DDRSS1_CTL_232_DATA
-				DDRSS1_CTL_233_DATA
-				DDRSS1_CTL_234_DATA
-				DDRSS1_CTL_235_DATA
-				DDRSS1_CTL_236_DATA
-				DDRSS1_CTL_237_DATA
-				DDRSS1_CTL_238_DATA
-				DDRSS1_CTL_239_DATA
-				DDRSS1_CTL_240_DATA
-				DDRSS1_CTL_241_DATA
-				DDRSS1_CTL_242_DATA
-				DDRSS1_CTL_243_DATA
-				DDRSS1_CTL_244_DATA
-				DDRSS1_CTL_245_DATA
-				DDRSS1_CTL_246_DATA
-				DDRSS1_CTL_247_DATA
-				DDRSS1_CTL_248_DATA
-				DDRSS1_CTL_249_DATA
-				DDRSS1_CTL_250_DATA
-				DDRSS1_CTL_251_DATA
-				DDRSS1_CTL_252_DATA
-				DDRSS1_CTL_253_DATA
-				DDRSS1_CTL_254_DATA
-				DDRSS1_CTL_255_DATA
-				DDRSS1_CTL_256_DATA
-				DDRSS1_CTL_257_DATA
-				DDRSS1_CTL_258_DATA
-				DDRSS1_CTL_259_DATA
-				DDRSS1_CTL_260_DATA
-				DDRSS1_CTL_261_DATA
-				DDRSS1_CTL_262_DATA
-				DDRSS1_CTL_263_DATA
-				DDRSS1_CTL_264_DATA
-				DDRSS1_CTL_265_DATA
-				DDRSS1_CTL_266_DATA
-				DDRSS1_CTL_267_DATA
-				DDRSS1_CTL_268_DATA
-				DDRSS1_CTL_269_DATA
-				DDRSS1_CTL_270_DATA
-				DDRSS1_CTL_271_DATA
-				DDRSS1_CTL_272_DATA
-				DDRSS1_CTL_273_DATA
-				DDRSS1_CTL_274_DATA
-				DDRSS1_CTL_275_DATA
-				DDRSS1_CTL_276_DATA
-				DDRSS1_CTL_277_DATA
-				DDRSS1_CTL_278_DATA
-				DDRSS1_CTL_279_DATA
-				DDRSS1_CTL_280_DATA
-				DDRSS1_CTL_281_DATA
-				DDRSS1_CTL_282_DATA
-				DDRSS1_CTL_283_DATA
-				DDRSS1_CTL_284_DATA
-				DDRSS1_CTL_285_DATA
-				DDRSS1_CTL_286_DATA
-				DDRSS1_CTL_287_DATA
-				DDRSS1_CTL_288_DATA
-				DDRSS1_CTL_289_DATA
-				DDRSS1_CTL_290_DATA
-				DDRSS1_CTL_291_DATA
-				DDRSS1_CTL_292_DATA
-				DDRSS1_CTL_293_DATA
-				DDRSS1_CTL_294_DATA
-				DDRSS1_CTL_295_DATA
-				DDRSS1_CTL_296_DATA
-				DDRSS1_CTL_297_DATA
-				DDRSS1_CTL_298_DATA
-				DDRSS1_CTL_299_DATA
-				DDRSS1_CTL_300_DATA
-				DDRSS1_CTL_301_DATA
-				DDRSS1_CTL_302_DATA
-				DDRSS1_CTL_303_DATA
-				DDRSS1_CTL_304_DATA
-				DDRSS1_CTL_305_DATA
-				DDRSS1_CTL_306_DATA
-				DDRSS1_CTL_307_DATA
-				DDRSS1_CTL_308_DATA
-				DDRSS1_CTL_309_DATA
-				DDRSS1_CTL_310_DATA
-				DDRSS1_CTL_311_DATA
-				DDRSS1_CTL_312_DATA
-				DDRSS1_CTL_313_DATA
-				DDRSS1_CTL_314_DATA
-				DDRSS1_CTL_315_DATA
-				DDRSS1_CTL_316_DATA
-				DDRSS1_CTL_317_DATA
-				DDRSS1_CTL_318_DATA
-				DDRSS1_CTL_319_DATA
-				DDRSS1_CTL_320_DATA
-				DDRSS1_CTL_321_DATA
-				DDRSS1_CTL_322_DATA
-				DDRSS1_CTL_323_DATA
-				DDRSS1_CTL_324_DATA
-				DDRSS1_CTL_325_DATA
-				DDRSS1_CTL_326_DATA
-				DDRSS1_CTL_327_DATA
-				DDRSS1_CTL_328_DATA
-				DDRSS1_CTL_329_DATA
-				DDRSS1_CTL_330_DATA
-				DDRSS1_CTL_331_DATA
-				DDRSS1_CTL_332_DATA
-				DDRSS1_CTL_333_DATA
-				DDRSS1_CTL_334_DATA
-				DDRSS1_CTL_335_DATA
-				DDRSS1_CTL_336_DATA
-				DDRSS1_CTL_337_DATA
-				DDRSS1_CTL_338_DATA
-				DDRSS1_CTL_339_DATA
-				DDRSS1_CTL_340_DATA
-				DDRSS1_CTL_341_DATA
-				DDRSS1_CTL_342_DATA
-				DDRSS1_CTL_343_DATA
-				DDRSS1_CTL_344_DATA
-				DDRSS1_CTL_345_DATA
-				DDRSS1_CTL_346_DATA
-				DDRSS1_CTL_347_DATA
-				DDRSS1_CTL_348_DATA
-				DDRSS1_CTL_349_DATA
-				DDRSS1_CTL_350_DATA
-				DDRSS1_CTL_351_DATA
-				DDRSS1_CTL_352_DATA
-				DDRSS1_CTL_353_DATA
-				DDRSS1_CTL_354_DATA
-				DDRSS1_CTL_355_DATA
-				DDRSS1_CTL_356_DATA
-				DDRSS1_CTL_357_DATA
-				DDRSS1_CTL_358_DATA
-				DDRSS1_CTL_359_DATA
-				DDRSS1_CTL_360_DATA
-				DDRSS1_CTL_361_DATA
-				DDRSS1_CTL_362_DATA
-				DDRSS1_CTL_363_DATA
-				DDRSS1_CTL_364_DATA
-				DDRSS1_CTL_365_DATA
-				DDRSS1_CTL_366_DATA
-				DDRSS1_CTL_367_DATA
-				DDRSS1_CTL_368_DATA
-				DDRSS1_CTL_369_DATA
-				DDRSS1_CTL_370_DATA
-				DDRSS1_CTL_371_DATA
-				DDRSS1_CTL_372_DATA
-				DDRSS1_CTL_373_DATA
-				DDRSS1_CTL_374_DATA
-				DDRSS1_CTL_375_DATA
-				DDRSS1_CTL_376_DATA
-				DDRSS1_CTL_377_DATA
-				DDRSS1_CTL_378_DATA
-				DDRSS1_CTL_379_DATA
-				DDRSS1_CTL_380_DATA
-				DDRSS1_CTL_381_DATA
-				DDRSS1_CTL_382_DATA
-				DDRSS1_CTL_383_DATA
-				DDRSS1_CTL_384_DATA
-				DDRSS1_CTL_385_DATA
-				DDRSS1_CTL_386_DATA
-				DDRSS1_CTL_387_DATA
-				DDRSS1_CTL_388_DATA
-				DDRSS1_CTL_389_DATA
-				DDRSS1_CTL_390_DATA
-				DDRSS1_CTL_391_DATA
-				DDRSS1_CTL_392_DATA
-				DDRSS1_CTL_393_DATA
-				DDRSS1_CTL_394_DATA
-				DDRSS1_CTL_395_DATA
-				DDRSS1_CTL_396_DATA
-				DDRSS1_CTL_397_DATA
-				DDRSS1_CTL_398_DATA
-				DDRSS1_CTL_399_DATA
-				DDRSS1_CTL_400_DATA
-				DDRSS1_CTL_401_DATA
-				DDRSS1_CTL_402_DATA
-				DDRSS1_CTL_403_DATA
-				DDRSS1_CTL_404_DATA
-				DDRSS1_CTL_405_DATA
-				DDRSS1_CTL_406_DATA
-				DDRSS1_CTL_407_DATA
-				DDRSS1_CTL_408_DATA
-				DDRSS1_CTL_409_DATA
-				DDRSS1_CTL_410_DATA
-				DDRSS1_CTL_411_DATA
-				DDRSS1_CTL_412_DATA
-				DDRSS1_CTL_413_DATA
-				DDRSS1_CTL_414_DATA
-				DDRSS1_CTL_415_DATA
-				DDRSS1_CTL_416_DATA
-				DDRSS1_CTL_417_DATA
-				DDRSS1_CTL_418_DATA
-				DDRSS1_CTL_419_DATA
-				DDRSS1_CTL_420_DATA
-				DDRSS1_CTL_421_DATA
-				DDRSS1_CTL_422_DATA
-				DDRSS1_CTL_423_DATA
-				DDRSS1_CTL_424_DATA
-				DDRSS1_CTL_425_DATA
-				DDRSS1_CTL_426_DATA
-				DDRSS1_CTL_427_DATA
-				DDRSS1_CTL_428_DATA
-				DDRSS1_CTL_429_DATA
-				DDRSS1_CTL_430_DATA
-				DDRSS1_CTL_431_DATA
-				DDRSS1_CTL_432_DATA
-				DDRSS1_CTL_433_DATA
-				DDRSS1_CTL_434_DATA
-				DDRSS1_CTL_435_DATA
-				DDRSS1_CTL_436_DATA
-				DDRSS1_CTL_437_DATA
-				DDRSS1_CTL_438_DATA
-				DDRSS1_CTL_439_DATA
-				DDRSS1_CTL_440_DATA
-				DDRSS1_CTL_441_DATA
-				DDRSS1_CTL_442_DATA
-				DDRSS1_CTL_443_DATA
-				DDRSS1_CTL_444_DATA
-				DDRSS1_CTL_445_DATA
-				DDRSS1_CTL_446_DATA
-				DDRSS1_CTL_447_DATA
-				DDRSS1_CTL_448_DATA
-				DDRSS1_CTL_449_DATA
-				DDRSS1_CTL_450_DATA
-				DDRSS1_CTL_451_DATA
-				DDRSS1_CTL_452_DATA
-				DDRSS1_CTL_453_DATA
-				DDRSS1_CTL_454_DATA
-				DDRSS1_CTL_455_DATA
-				DDRSS1_CTL_456_DATA
-				DDRSS1_CTL_457_DATA
-				DDRSS1_CTL_458_DATA
-			>;
-
-			ti,pi-data = <
-				DDRSS1_PI_00_DATA
-				DDRSS1_PI_01_DATA
-				DDRSS1_PI_02_DATA
-				DDRSS1_PI_03_DATA
-				DDRSS1_PI_04_DATA
-				DDRSS1_PI_05_DATA
-				DDRSS1_PI_06_DATA
-				DDRSS1_PI_07_DATA
-				DDRSS1_PI_08_DATA
-				DDRSS1_PI_09_DATA
-				DDRSS1_PI_10_DATA
-				DDRSS1_PI_11_DATA
-				DDRSS1_PI_12_DATA
-				DDRSS1_PI_13_DATA
-				DDRSS1_PI_14_DATA
-				DDRSS1_PI_15_DATA
-				DDRSS1_PI_16_DATA
-				DDRSS1_PI_17_DATA
-				DDRSS1_PI_18_DATA
-				DDRSS1_PI_19_DATA
-				DDRSS1_PI_20_DATA
-				DDRSS1_PI_21_DATA
-				DDRSS1_PI_22_DATA
-				DDRSS1_PI_23_DATA
-				DDRSS1_PI_24_DATA
-				DDRSS1_PI_25_DATA
-				DDRSS1_PI_26_DATA
-				DDRSS1_PI_27_DATA
-				DDRSS1_PI_28_DATA
-				DDRSS1_PI_29_DATA
-				DDRSS1_PI_30_DATA
-				DDRSS1_PI_31_DATA
-				DDRSS1_PI_32_DATA
-				DDRSS1_PI_33_DATA
-				DDRSS1_PI_34_DATA
-				DDRSS1_PI_35_DATA
-				DDRSS1_PI_36_DATA
-				DDRSS1_PI_37_DATA
-				DDRSS1_PI_38_DATA
-				DDRSS1_PI_39_DATA
-				DDRSS1_PI_40_DATA
-				DDRSS1_PI_41_DATA
-				DDRSS1_PI_42_DATA
-				DDRSS1_PI_43_DATA
-				DDRSS1_PI_44_DATA
-				DDRSS1_PI_45_DATA
-				DDRSS1_PI_46_DATA
-				DDRSS1_PI_47_DATA
-				DDRSS1_PI_48_DATA
-				DDRSS1_PI_49_DATA
-				DDRSS1_PI_50_DATA
-				DDRSS1_PI_51_DATA
-				DDRSS1_PI_52_DATA
-				DDRSS1_PI_53_DATA
-				DDRSS1_PI_54_DATA
-				DDRSS1_PI_55_DATA
-				DDRSS1_PI_56_DATA
-				DDRSS1_PI_57_DATA
-				DDRSS1_PI_58_DATA
-				DDRSS1_PI_59_DATA
-				DDRSS1_PI_60_DATA
-				DDRSS1_PI_61_DATA
-				DDRSS1_PI_62_DATA
-				DDRSS1_PI_63_DATA
-				DDRSS1_PI_64_DATA
-				DDRSS1_PI_65_DATA
-				DDRSS1_PI_66_DATA
-				DDRSS1_PI_67_DATA
-				DDRSS1_PI_68_DATA
-				DDRSS1_PI_69_DATA
-				DDRSS1_PI_70_DATA
-				DDRSS1_PI_71_DATA
-				DDRSS1_PI_72_DATA
-				DDRSS1_PI_73_DATA
-				DDRSS1_PI_74_DATA
-				DDRSS1_PI_75_DATA
-				DDRSS1_PI_76_DATA
-				DDRSS1_PI_77_DATA
-				DDRSS1_PI_78_DATA
-				DDRSS1_PI_79_DATA
-				DDRSS1_PI_80_DATA
-				DDRSS1_PI_81_DATA
-				DDRSS1_PI_82_DATA
-				DDRSS1_PI_83_DATA
-				DDRSS1_PI_84_DATA
-				DDRSS1_PI_85_DATA
-				DDRSS1_PI_86_DATA
-				DDRSS1_PI_87_DATA
-				DDRSS1_PI_88_DATA
-				DDRSS1_PI_89_DATA
-				DDRSS1_PI_90_DATA
-				DDRSS1_PI_91_DATA
-				DDRSS1_PI_92_DATA
-				DDRSS1_PI_93_DATA
-				DDRSS1_PI_94_DATA
-				DDRSS1_PI_95_DATA
-				DDRSS1_PI_96_DATA
-				DDRSS1_PI_97_DATA
-				DDRSS1_PI_98_DATA
-				DDRSS1_PI_99_DATA
-				DDRSS1_PI_100_DATA
-				DDRSS1_PI_101_DATA
-				DDRSS1_PI_102_DATA
-				DDRSS1_PI_103_DATA
-				DDRSS1_PI_104_DATA
-				DDRSS1_PI_105_DATA
-				DDRSS1_PI_106_DATA
-				DDRSS1_PI_107_DATA
-				DDRSS1_PI_108_DATA
-				DDRSS1_PI_109_DATA
-				DDRSS1_PI_110_DATA
-				DDRSS1_PI_111_DATA
-				DDRSS1_PI_112_DATA
-				DDRSS1_PI_113_DATA
-				DDRSS1_PI_114_DATA
-				DDRSS1_PI_115_DATA
-				DDRSS1_PI_116_DATA
-				DDRSS1_PI_117_DATA
-				DDRSS1_PI_118_DATA
-				DDRSS1_PI_119_DATA
-				DDRSS1_PI_120_DATA
-				DDRSS1_PI_121_DATA
-				DDRSS1_PI_122_DATA
-				DDRSS1_PI_123_DATA
-				DDRSS1_PI_124_DATA
-				DDRSS1_PI_125_DATA
-				DDRSS1_PI_126_DATA
-				DDRSS1_PI_127_DATA
-				DDRSS1_PI_128_DATA
-				DDRSS1_PI_129_DATA
-				DDRSS1_PI_130_DATA
-				DDRSS1_PI_131_DATA
-				DDRSS1_PI_132_DATA
-				DDRSS1_PI_133_DATA
-				DDRSS1_PI_134_DATA
-				DDRSS1_PI_135_DATA
-				DDRSS1_PI_136_DATA
-				DDRSS1_PI_137_DATA
-				DDRSS1_PI_138_DATA
-				DDRSS1_PI_139_DATA
-				DDRSS1_PI_140_DATA
-				DDRSS1_PI_141_DATA
-				DDRSS1_PI_142_DATA
-				DDRSS1_PI_143_DATA
-				DDRSS1_PI_144_DATA
-				DDRSS1_PI_145_DATA
-				DDRSS1_PI_146_DATA
-				DDRSS1_PI_147_DATA
-				DDRSS1_PI_148_DATA
-				DDRSS1_PI_149_DATA
-				DDRSS1_PI_150_DATA
-				DDRSS1_PI_151_DATA
-				DDRSS1_PI_152_DATA
-				DDRSS1_PI_153_DATA
-				DDRSS1_PI_154_DATA
-				DDRSS1_PI_155_DATA
-				DDRSS1_PI_156_DATA
-				DDRSS1_PI_157_DATA
-				DDRSS1_PI_158_DATA
-				DDRSS1_PI_159_DATA
-				DDRSS1_PI_160_DATA
-				DDRSS1_PI_161_DATA
-				DDRSS1_PI_162_DATA
-				DDRSS1_PI_163_DATA
-				DDRSS1_PI_164_DATA
-				DDRSS1_PI_165_DATA
-				DDRSS1_PI_166_DATA
-				DDRSS1_PI_167_DATA
-				DDRSS1_PI_168_DATA
-				DDRSS1_PI_169_DATA
-				DDRSS1_PI_170_DATA
-				DDRSS1_PI_171_DATA
-				DDRSS1_PI_172_DATA
-				DDRSS1_PI_173_DATA
-				DDRSS1_PI_174_DATA
-				DDRSS1_PI_175_DATA
-				DDRSS1_PI_176_DATA
-				DDRSS1_PI_177_DATA
-				DDRSS1_PI_178_DATA
-				DDRSS1_PI_179_DATA
-				DDRSS1_PI_180_DATA
-				DDRSS1_PI_181_DATA
-				DDRSS1_PI_182_DATA
-				DDRSS1_PI_183_DATA
-				DDRSS1_PI_184_DATA
-				DDRSS1_PI_185_DATA
-				DDRSS1_PI_186_DATA
-				DDRSS1_PI_187_DATA
-				DDRSS1_PI_188_DATA
-				DDRSS1_PI_189_DATA
-				DDRSS1_PI_190_DATA
-				DDRSS1_PI_191_DATA
-				DDRSS1_PI_192_DATA
-				DDRSS1_PI_193_DATA
-				DDRSS1_PI_194_DATA
-				DDRSS1_PI_195_DATA
-				DDRSS1_PI_196_DATA
-				DDRSS1_PI_197_DATA
-				DDRSS1_PI_198_DATA
-				DDRSS1_PI_199_DATA
-				DDRSS1_PI_200_DATA
-				DDRSS1_PI_201_DATA
-				DDRSS1_PI_202_DATA
-				DDRSS1_PI_203_DATA
-				DDRSS1_PI_204_DATA
-				DDRSS1_PI_205_DATA
-				DDRSS1_PI_206_DATA
-				DDRSS1_PI_207_DATA
-				DDRSS1_PI_208_DATA
-				DDRSS1_PI_209_DATA
-				DDRSS1_PI_210_DATA
-				DDRSS1_PI_211_DATA
-				DDRSS1_PI_212_DATA
-				DDRSS1_PI_213_DATA
-				DDRSS1_PI_214_DATA
-				DDRSS1_PI_215_DATA
-				DDRSS1_PI_216_DATA
-				DDRSS1_PI_217_DATA
-				DDRSS1_PI_218_DATA
-				DDRSS1_PI_219_DATA
-				DDRSS1_PI_220_DATA
-				DDRSS1_PI_221_DATA
-				DDRSS1_PI_222_DATA
-				DDRSS1_PI_223_DATA
-				DDRSS1_PI_224_DATA
-				DDRSS1_PI_225_DATA
-				DDRSS1_PI_226_DATA
-				DDRSS1_PI_227_DATA
-				DDRSS1_PI_228_DATA
-				DDRSS1_PI_229_DATA
-				DDRSS1_PI_230_DATA
-				DDRSS1_PI_231_DATA
-				DDRSS1_PI_232_DATA
-				DDRSS1_PI_233_DATA
-				DDRSS1_PI_234_DATA
-				DDRSS1_PI_235_DATA
-				DDRSS1_PI_236_DATA
-				DDRSS1_PI_237_DATA
-				DDRSS1_PI_238_DATA
-				DDRSS1_PI_239_DATA
-				DDRSS1_PI_240_DATA
-				DDRSS1_PI_241_DATA
-				DDRSS1_PI_242_DATA
-				DDRSS1_PI_243_DATA
-				DDRSS1_PI_244_DATA
-				DDRSS1_PI_245_DATA
-				DDRSS1_PI_246_DATA
-				DDRSS1_PI_247_DATA
-				DDRSS1_PI_248_DATA
-				DDRSS1_PI_249_DATA
-				DDRSS1_PI_250_DATA
-				DDRSS1_PI_251_DATA
-				DDRSS1_PI_252_DATA
-				DDRSS1_PI_253_DATA
-				DDRSS1_PI_254_DATA
-				DDRSS1_PI_255_DATA
-				DDRSS1_PI_256_DATA
-				DDRSS1_PI_257_DATA
-				DDRSS1_PI_258_DATA
-				DDRSS1_PI_259_DATA
-				DDRSS1_PI_260_DATA
-				DDRSS1_PI_261_DATA
-				DDRSS1_PI_262_DATA
-				DDRSS1_PI_263_DATA
-				DDRSS1_PI_264_DATA
-				DDRSS1_PI_265_DATA
-				DDRSS1_PI_266_DATA
-				DDRSS1_PI_267_DATA
-				DDRSS1_PI_268_DATA
-				DDRSS1_PI_269_DATA
-				DDRSS1_PI_270_DATA
-				DDRSS1_PI_271_DATA
-				DDRSS1_PI_272_DATA
-				DDRSS1_PI_273_DATA
-				DDRSS1_PI_274_DATA
-				DDRSS1_PI_275_DATA
-				DDRSS1_PI_276_DATA
-				DDRSS1_PI_277_DATA
-				DDRSS1_PI_278_DATA
-				DDRSS1_PI_279_DATA
-				DDRSS1_PI_280_DATA
-				DDRSS1_PI_281_DATA
-				DDRSS1_PI_282_DATA
-				DDRSS1_PI_283_DATA
-				DDRSS1_PI_284_DATA
-				DDRSS1_PI_285_DATA
-				DDRSS1_PI_286_DATA
-				DDRSS1_PI_287_DATA
-				DDRSS1_PI_288_DATA
-				DDRSS1_PI_289_DATA
-				DDRSS1_PI_290_DATA
-				DDRSS1_PI_291_DATA
-				DDRSS1_PI_292_DATA
-				DDRSS1_PI_293_DATA
-				DDRSS1_PI_294_DATA
-				DDRSS1_PI_295_DATA
-				DDRSS1_PI_296_DATA
-				DDRSS1_PI_297_DATA
-				DDRSS1_PI_298_DATA
-				DDRSS1_PI_299_DATA
-			>;
-
-			ti,phy-data = <
-				DDRSS1_PHY_00_DATA
-				DDRSS1_PHY_01_DATA
-				DDRSS1_PHY_02_DATA
-				DDRSS1_PHY_03_DATA
-				DDRSS1_PHY_04_DATA
-				DDRSS1_PHY_05_DATA
-				DDRSS1_PHY_06_DATA
-				DDRSS1_PHY_07_DATA
-				DDRSS1_PHY_08_DATA
-				DDRSS1_PHY_09_DATA
-				DDRSS1_PHY_10_DATA
-				DDRSS1_PHY_11_DATA
-				DDRSS1_PHY_12_DATA
-				DDRSS1_PHY_13_DATA
-				DDRSS1_PHY_14_DATA
-				DDRSS1_PHY_15_DATA
-				DDRSS1_PHY_16_DATA
-				DDRSS1_PHY_17_DATA
-				DDRSS1_PHY_18_DATA
-				DDRSS1_PHY_19_DATA
-				DDRSS1_PHY_20_DATA
-				DDRSS1_PHY_21_DATA
-				DDRSS1_PHY_22_DATA
-				DDRSS1_PHY_23_DATA
-				DDRSS1_PHY_24_DATA
-				DDRSS1_PHY_25_DATA
-				DDRSS1_PHY_26_DATA
-				DDRSS1_PHY_27_DATA
-				DDRSS1_PHY_28_DATA
-				DDRSS1_PHY_29_DATA
-				DDRSS1_PHY_30_DATA
-				DDRSS1_PHY_31_DATA
-				DDRSS1_PHY_32_DATA
-				DDRSS1_PHY_33_DATA
-				DDRSS1_PHY_34_DATA
-				DDRSS1_PHY_35_DATA
-				DDRSS1_PHY_36_DATA
-				DDRSS1_PHY_37_DATA
-				DDRSS1_PHY_38_DATA
-				DDRSS1_PHY_39_DATA
-				DDRSS1_PHY_40_DATA
-				DDRSS1_PHY_41_DATA
-				DDRSS1_PHY_42_DATA
-				DDRSS1_PHY_43_DATA
-				DDRSS1_PHY_44_DATA
-				DDRSS1_PHY_45_DATA
-				DDRSS1_PHY_46_DATA
-				DDRSS1_PHY_47_DATA
-				DDRSS1_PHY_48_DATA
-				DDRSS1_PHY_49_DATA
-				DDRSS1_PHY_50_DATA
-				DDRSS1_PHY_51_DATA
-				DDRSS1_PHY_52_DATA
-				DDRSS1_PHY_53_DATA
-				DDRSS1_PHY_54_DATA
-				DDRSS1_PHY_55_DATA
-				DDRSS1_PHY_56_DATA
-				DDRSS1_PHY_57_DATA
-				DDRSS1_PHY_58_DATA
-				DDRSS1_PHY_59_DATA
-				DDRSS1_PHY_60_DATA
-				DDRSS1_PHY_61_DATA
-				DDRSS1_PHY_62_DATA
-				DDRSS1_PHY_63_DATA
-				DDRSS1_PHY_64_DATA
-				DDRSS1_PHY_65_DATA
-				DDRSS1_PHY_66_DATA
-				DDRSS1_PHY_67_DATA
-				DDRSS1_PHY_68_DATA
-				DDRSS1_PHY_69_DATA
-				DDRSS1_PHY_70_DATA
-				DDRSS1_PHY_71_DATA
-				DDRSS1_PHY_72_DATA
-				DDRSS1_PHY_73_DATA
-				DDRSS1_PHY_74_DATA
-				DDRSS1_PHY_75_DATA
-				DDRSS1_PHY_76_DATA
-				DDRSS1_PHY_77_DATA
-				DDRSS1_PHY_78_DATA
-				DDRSS1_PHY_79_DATA
-				DDRSS1_PHY_80_DATA
-				DDRSS1_PHY_81_DATA
-				DDRSS1_PHY_82_DATA
-				DDRSS1_PHY_83_DATA
-				DDRSS1_PHY_84_DATA
-				DDRSS1_PHY_85_DATA
-				DDRSS1_PHY_86_DATA
-				DDRSS1_PHY_87_DATA
-				DDRSS1_PHY_88_DATA
-				DDRSS1_PHY_89_DATA
-				DDRSS1_PHY_90_DATA
-				DDRSS1_PHY_91_DATA
-				DDRSS1_PHY_92_DATA
-				DDRSS1_PHY_93_DATA
-				DDRSS1_PHY_94_DATA
-				DDRSS1_PHY_95_DATA
-				DDRSS1_PHY_96_DATA
-				DDRSS1_PHY_97_DATA
-				DDRSS1_PHY_98_DATA
-				DDRSS1_PHY_99_DATA
-				DDRSS1_PHY_100_DATA
-				DDRSS1_PHY_101_DATA
-				DDRSS1_PHY_102_DATA
-				DDRSS1_PHY_103_DATA
-				DDRSS1_PHY_104_DATA
-				DDRSS1_PHY_105_DATA
-				DDRSS1_PHY_106_DATA
-				DDRSS1_PHY_107_DATA
-				DDRSS1_PHY_108_DATA
-				DDRSS1_PHY_109_DATA
-				DDRSS1_PHY_110_DATA
-				DDRSS1_PHY_111_DATA
-				DDRSS1_PHY_112_DATA
-				DDRSS1_PHY_113_DATA
-				DDRSS1_PHY_114_DATA
-				DDRSS1_PHY_115_DATA
-				DDRSS1_PHY_116_DATA
-				DDRSS1_PHY_117_DATA
-				DDRSS1_PHY_118_DATA
-				DDRSS1_PHY_119_DATA
-				DDRSS1_PHY_120_DATA
-				DDRSS1_PHY_121_DATA
-				DDRSS1_PHY_122_DATA
-				DDRSS1_PHY_123_DATA
-				DDRSS1_PHY_124_DATA
-				DDRSS1_PHY_125_DATA
-				DDRSS1_PHY_126_DATA
-				DDRSS1_PHY_127_DATA
-				DDRSS1_PHY_128_DATA
-				DDRSS1_PHY_129_DATA
-				DDRSS1_PHY_130_DATA
-				DDRSS1_PHY_131_DATA
-				DDRSS1_PHY_132_DATA
-				DDRSS1_PHY_133_DATA
-				DDRSS1_PHY_134_DATA
-				DDRSS1_PHY_135_DATA
-				DDRSS1_PHY_136_DATA
-				DDRSS1_PHY_137_DATA
-				DDRSS1_PHY_138_DATA
-				DDRSS1_PHY_139_DATA
-				DDRSS1_PHY_140_DATA
-				DDRSS1_PHY_141_DATA
-				DDRSS1_PHY_142_DATA
-				DDRSS1_PHY_143_DATA
-				DDRSS1_PHY_144_DATA
-				DDRSS1_PHY_145_DATA
-				DDRSS1_PHY_146_DATA
-				DDRSS1_PHY_147_DATA
-				DDRSS1_PHY_148_DATA
-				DDRSS1_PHY_149_DATA
-				DDRSS1_PHY_150_DATA
-				DDRSS1_PHY_151_DATA
-				DDRSS1_PHY_152_DATA
-				DDRSS1_PHY_153_DATA
-				DDRSS1_PHY_154_DATA
-				DDRSS1_PHY_155_DATA
-				DDRSS1_PHY_156_DATA
-				DDRSS1_PHY_157_DATA
-				DDRSS1_PHY_158_DATA
-				DDRSS1_PHY_159_DATA
-				DDRSS1_PHY_160_DATA
-				DDRSS1_PHY_161_DATA
-				DDRSS1_PHY_162_DATA
-				DDRSS1_PHY_163_DATA
-				DDRSS1_PHY_164_DATA
-				DDRSS1_PHY_165_DATA
-				DDRSS1_PHY_166_DATA
-				DDRSS1_PHY_167_DATA
-				DDRSS1_PHY_168_DATA
-				DDRSS1_PHY_169_DATA
-				DDRSS1_PHY_170_DATA
-				DDRSS1_PHY_171_DATA
-				DDRSS1_PHY_172_DATA
-				DDRSS1_PHY_173_DATA
-				DDRSS1_PHY_174_DATA
-				DDRSS1_PHY_175_DATA
-				DDRSS1_PHY_176_DATA
-				DDRSS1_PHY_177_DATA
-				DDRSS1_PHY_178_DATA
-				DDRSS1_PHY_179_DATA
-				DDRSS1_PHY_180_DATA
-				DDRSS1_PHY_181_DATA
-				DDRSS1_PHY_182_DATA
-				DDRSS1_PHY_183_DATA
-				DDRSS1_PHY_184_DATA
-				DDRSS1_PHY_185_DATA
-				DDRSS1_PHY_186_DATA
-				DDRSS1_PHY_187_DATA
-				DDRSS1_PHY_188_DATA
-				DDRSS1_PHY_189_DATA
-				DDRSS1_PHY_190_DATA
-				DDRSS1_PHY_191_DATA
-				DDRSS1_PHY_192_DATA
-				DDRSS1_PHY_193_DATA
-				DDRSS1_PHY_194_DATA
-				DDRSS1_PHY_195_DATA
-				DDRSS1_PHY_196_DATA
-				DDRSS1_PHY_197_DATA
-				DDRSS1_PHY_198_DATA
-				DDRSS1_PHY_199_DATA
-				DDRSS1_PHY_200_DATA
-				DDRSS1_PHY_201_DATA
-				DDRSS1_PHY_202_DATA
-				DDRSS1_PHY_203_DATA
-				DDRSS1_PHY_204_DATA
-				DDRSS1_PHY_205_DATA
-				DDRSS1_PHY_206_DATA
-				DDRSS1_PHY_207_DATA
-				DDRSS1_PHY_208_DATA
-				DDRSS1_PHY_209_DATA
-				DDRSS1_PHY_210_DATA
-				DDRSS1_PHY_211_DATA
-				DDRSS1_PHY_212_DATA
-				DDRSS1_PHY_213_DATA
-				DDRSS1_PHY_214_DATA
-				DDRSS1_PHY_215_DATA
-				DDRSS1_PHY_216_DATA
-				DDRSS1_PHY_217_DATA
-				DDRSS1_PHY_218_DATA
-				DDRSS1_PHY_219_DATA
-				DDRSS1_PHY_220_DATA
-				DDRSS1_PHY_221_DATA
-				DDRSS1_PHY_222_DATA
-				DDRSS1_PHY_223_DATA
-				DDRSS1_PHY_224_DATA
-				DDRSS1_PHY_225_DATA
-				DDRSS1_PHY_226_DATA
-				DDRSS1_PHY_227_DATA
-				DDRSS1_PHY_228_DATA
-				DDRSS1_PHY_229_DATA
-				DDRSS1_PHY_230_DATA
-				DDRSS1_PHY_231_DATA
-				DDRSS1_PHY_232_DATA
-				DDRSS1_PHY_233_DATA
-				DDRSS1_PHY_234_DATA
-				DDRSS1_PHY_235_DATA
-				DDRSS1_PHY_236_DATA
-				DDRSS1_PHY_237_DATA
-				DDRSS1_PHY_238_DATA
-				DDRSS1_PHY_239_DATA
-				DDRSS1_PHY_240_DATA
-				DDRSS1_PHY_241_DATA
-				DDRSS1_PHY_242_DATA
-				DDRSS1_PHY_243_DATA
-				DDRSS1_PHY_244_DATA
-				DDRSS1_PHY_245_DATA
-				DDRSS1_PHY_246_DATA
-				DDRSS1_PHY_247_DATA
-				DDRSS1_PHY_248_DATA
-				DDRSS1_PHY_249_DATA
-				DDRSS1_PHY_250_DATA
-				DDRSS1_PHY_251_DATA
-				DDRSS1_PHY_252_DATA
-				DDRSS1_PHY_253_DATA
-				DDRSS1_PHY_254_DATA
-				DDRSS1_PHY_255_DATA
-				DDRSS1_PHY_256_DATA
-				DDRSS1_PHY_257_DATA
-				DDRSS1_PHY_258_DATA
-				DDRSS1_PHY_259_DATA
-				DDRSS1_PHY_260_DATA
-				DDRSS1_PHY_261_DATA
-				DDRSS1_PHY_262_DATA
-				DDRSS1_PHY_263_DATA
-				DDRSS1_PHY_264_DATA
-				DDRSS1_PHY_265_DATA
-				DDRSS1_PHY_266_DATA
-				DDRSS1_PHY_267_DATA
-				DDRSS1_PHY_268_DATA
-				DDRSS1_PHY_269_DATA
-				DDRSS1_PHY_270_DATA
-				DDRSS1_PHY_271_DATA
-				DDRSS1_PHY_272_DATA
-				DDRSS1_PHY_273_DATA
-				DDRSS1_PHY_274_DATA
-				DDRSS1_PHY_275_DATA
-				DDRSS1_PHY_276_DATA
-				DDRSS1_PHY_277_DATA
-				DDRSS1_PHY_278_DATA
-				DDRSS1_PHY_279_DATA
-				DDRSS1_PHY_280_DATA
-				DDRSS1_PHY_281_DATA
-				DDRSS1_PHY_282_DATA
-				DDRSS1_PHY_283_DATA
-				DDRSS1_PHY_284_DATA
-				DDRSS1_PHY_285_DATA
-				DDRSS1_PHY_286_DATA
-				DDRSS1_PHY_287_DATA
-				DDRSS1_PHY_288_DATA
-				DDRSS1_PHY_289_DATA
-				DDRSS1_PHY_290_DATA
-				DDRSS1_PHY_291_DATA
-				DDRSS1_PHY_292_DATA
-				DDRSS1_PHY_293_DATA
-				DDRSS1_PHY_294_DATA
-				DDRSS1_PHY_295_DATA
-				DDRSS1_PHY_296_DATA
-				DDRSS1_PHY_297_DATA
-				DDRSS1_PHY_298_DATA
-				DDRSS1_PHY_299_DATA
-				DDRSS1_PHY_300_DATA
-				DDRSS1_PHY_301_DATA
-				DDRSS1_PHY_302_DATA
-				DDRSS1_PHY_303_DATA
-				DDRSS1_PHY_304_DATA
-				DDRSS1_PHY_305_DATA
-				DDRSS1_PHY_306_DATA
-				DDRSS1_PHY_307_DATA
-				DDRSS1_PHY_308_DATA
-				DDRSS1_PHY_309_DATA
-				DDRSS1_PHY_310_DATA
-				DDRSS1_PHY_311_DATA
-				DDRSS1_PHY_312_DATA
-				DDRSS1_PHY_313_DATA
-				DDRSS1_PHY_314_DATA
-				DDRSS1_PHY_315_DATA
-				DDRSS1_PHY_316_DATA
-				DDRSS1_PHY_317_DATA
-				DDRSS1_PHY_318_DATA
-				DDRSS1_PHY_319_DATA
-				DDRSS1_PHY_320_DATA
-				DDRSS1_PHY_321_DATA
-				DDRSS1_PHY_322_DATA
-				DDRSS1_PHY_323_DATA
-				DDRSS1_PHY_324_DATA
-				DDRSS1_PHY_325_DATA
-				DDRSS1_PHY_326_DATA
-				DDRSS1_PHY_327_DATA
-				DDRSS1_PHY_328_DATA
-				DDRSS1_PHY_329_DATA
-				DDRSS1_PHY_330_DATA
-				DDRSS1_PHY_331_DATA
-				DDRSS1_PHY_332_DATA
-				DDRSS1_PHY_333_DATA
-				DDRSS1_PHY_334_DATA
-				DDRSS1_PHY_335_DATA
-				DDRSS1_PHY_336_DATA
-				DDRSS1_PHY_337_DATA
-				DDRSS1_PHY_338_DATA
-				DDRSS1_PHY_339_DATA
-				DDRSS1_PHY_340_DATA
-				DDRSS1_PHY_341_DATA
-				DDRSS1_PHY_342_DATA
-				DDRSS1_PHY_343_DATA
-				DDRSS1_PHY_344_DATA
-				DDRSS1_PHY_345_DATA
-				DDRSS1_PHY_346_DATA
-				DDRSS1_PHY_347_DATA
-				DDRSS1_PHY_348_DATA
-				DDRSS1_PHY_349_DATA
-				DDRSS1_PHY_350_DATA
-				DDRSS1_PHY_351_DATA
-				DDRSS1_PHY_352_DATA
-				DDRSS1_PHY_353_DATA
-				DDRSS1_PHY_354_DATA
-				DDRSS1_PHY_355_DATA
-				DDRSS1_PHY_356_DATA
-				DDRSS1_PHY_357_DATA
-				DDRSS1_PHY_358_DATA
-				DDRSS1_PHY_359_DATA
-				DDRSS1_PHY_360_DATA
-				DDRSS1_PHY_361_DATA
-				DDRSS1_PHY_362_DATA
-				DDRSS1_PHY_363_DATA
-				DDRSS1_PHY_364_DATA
-				DDRSS1_PHY_365_DATA
-				DDRSS1_PHY_366_DATA
-				DDRSS1_PHY_367_DATA
-				DDRSS1_PHY_368_DATA
-				DDRSS1_PHY_369_DATA
-				DDRSS1_PHY_370_DATA
-				DDRSS1_PHY_371_DATA
-				DDRSS1_PHY_372_DATA
-				DDRSS1_PHY_373_DATA
-				DDRSS1_PHY_374_DATA
-				DDRSS1_PHY_375_DATA
-				DDRSS1_PHY_376_DATA
-				DDRSS1_PHY_377_DATA
-				DDRSS1_PHY_378_DATA
-				DDRSS1_PHY_379_DATA
-				DDRSS1_PHY_380_DATA
-				DDRSS1_PHY_381_DATA
-				DDRSS1_PHY_382_DATA
-				DDRSS1_PHY_383_DATA
-				DDRSS1_PHY_384_DATA
-				DDRSS1_PHY_385_DATA
-				DDRSS1_PHY_386_DATA
-				DDRSS1_PHY_387_DATA
-				DDRSS1_PHY_388_DATA
-				DDRSS1_PHY_389_DATA
-				DDRSS1_PHY_390_DATA
-				DDRSS1_PHY_391_DATA
-				DDRSS1_PHY_392_DATA
-				DDRSS1_PHY_393_DATA
-				DDRSS1_PHY_394_DATA
-				DDRSS1_PHY_395_DATA
-				DDRSS1_PHY_396_DATA
-				DDRSS1_PHY_397_DATA
-				DDRSS1_PHY_398_DATA
-				DDRSS1_PHY_399_DATA
-				DDRSS1_PHY_400_DATA
-				DDRSS1_PHY_401_DATA
-				DDRSS1_PHY_402_DATA
-				DDRSS1_PHY_403_DATA
-				DDRSS1_PHY_404_DATA
-				DDRSS1_PHY_405_DATA
-				DDRSS1_PHY_406_DATA
-				DDRSS1_PHY_407_DATA
-				DDRSS1_PHY_408_DATA
-				DDRSS1_PHY_409_DATA
-				DDRSS1_PHY_410_DATA
-				DDRSS1_PHY_411_DATA
-				DDRSS1_PHY_412_DATA
-				DDRSS1_PHY_413_DATA
-				DDRSS1_PHY_414_DATA
-				DDRSS1_PHY_415_DATA
-				DDRSS1_PHY_416_DATA
-				DDRSS1_PHY_417_DATA
-				DDRSS1_PHY_418_DATA
-				DDRSS1_PHY_419_DATA
-				DDRSS1_PHY_420_DATA
-				DDRSS1_PHY_421_DATA
-				DDRSS1_PHY_422_DATA
-				DDRSS1_PHY_423_DATA
-				DDRSS1_PHY_424_DATA
-				DDRSS1_PHY_425_DATA
-				DDRSS1_PHY_426_DATA
-				DDRSS1_PHY_427_DATA
-				DDRSS1_PHY_428_DATA
-				DDRSS1_PHY_429_DATA
-				DDRSS1_PHY_430_DATA
-				DDRSS1_PHY_431_DATA
-				DDRSS1_PHY_432_DATA
-				DDRSS1_PHY_433_DATA
-				DDRSS1_PHY_434_DATA
-				DDRSS1_PHY_435_DATA
-				DDRSS1_PHY_436_DATA
-				DDRSS1_PHY_437_DATA
-				DDRSS1_PHY_438_DATA
-				DDRSS1_PHY_439_DATA
-				DDRSS1_PHY_440_DATA
-				DDRSS1_PHY_441_DATA
-				DDRSS1_PHY_442_DATA
-				DDRSS1_PHY_443_DATA
-				DDRSS1_PHY_444_DATA
-				DDRSS1_PHY_445_DATA
-				DDRSS1_PHY_446_DATA
-				DDRSS1_PHY_447_DATA
-				DDRSS1_PHY_448_DATA
-				DDRSS1_PHY_449_DATA
-				DDRSS1_PHY_450_DATA
-				DDRSS1_PHY_451_DATA
-				DDRSS1_PHY_452_DATA
-				DDRSS1_PHY_453_DATA
-				DDRSS1_PHY_454_DATA
-				DDRSS1_PHY_455_DATA
-				DDRSS1_PHY_456_DATA
-				DDRSS1_PHY_457_DATA
-				DDRSS1_PHY_458_DATA
-				DDRSS1_PHY_459_DATA
-				DDRSS1_PHY_460_DATA
-				DDRSS1_PHY_461_DATA
-				DDRSS1_PHY_462_DATA
-				DDRSS1_PHY_463_DATA
-				DDRSS1_PHY_464_DATA
-				DDRSS1_PHY_465_DATA
-				DDRSS1_PHY_466_DATA
-				DDRSS1_PHY_467_DATA
-				DDRSS1_PHY_468_DATA
-				DDRSS1_PHY_469_DATA
-				DDRSS1_PHY_470_DATA
-				DDRSS1_PHY_471_DATA
-				DDRSS1_PHY_472_DATA
-				DDRSS1_PHY_473_DATA
-				DDRSS1_PHY_474_DATA
-				DDRSS1_PHY_475_DATA
-				DDRSS1_PHY_476_DATA
-				DDRSS1_PHY_477_DATA
-				DDRSS1_PHY_478_DATA
-				DDRSS1_PHY_479_DATA
-				DDRSS1_PHY_480_DATA
-				DDRSS1_PHY_481_DATA
-				DDRSS1_PHY_482_DATA
-				DDRSS1_PHY_483_DATA
-				DDRSS1_PHY_484_DATA
-				DDRSS1_PHY_485_DATA
-				DDRSS1_PHY_486_DATA
-				DDRSS1_PHY_487_DATA
-				DDRSS1_PHY_488_DATA
-				DDRSS1_PHY_489_DATA
-				DDRSS1_PHY_490_DATA
-				DDRSS1_PHY_491_DATA
-				DDRSS1_PHY_492_DATA
-				DDRSS1_PHY_493_DATA
-				DDRSS1_PHY_494_DATA
-				DDRSS1_PHY_495_DATA
-				DDRSS1_PHY_496_DATA
-				DDRSS1_PHY_497_DATA
-				DDRSS1_PHY_498_DATA
-				DDRSS1_PHY_499_DATA
-				DDRSS1_PHY_500_DATA
-				DDRSS1_PHY_501_DATA
-				DDRSS1_PHY_502_DATA
-				DDRSS1_PHY_503_DATA
-				DDRSS1_PHY_504_DATA
-				DDRSS1_PHY_505_DATA
-				DDRSS1_PHY_506_DATA
-				DDRSS1_PHY_507_DATA
-				DDRSS1_PHY_508_DATA
-				DDRSS1_PHY_509_DATA
-				DDRSS1_PHY_510_DATA
-				DDRSS1_PHY_511_DATA
-				DDRSS1_PHY_512_DATA
-				DDRSS1_PHY_513_DATA
-				DDRSS1_PHY_514_DATA
-				DDRSS1_PHY_515_DATA
-				DDRSS1_PHY_516_DATA
-				DDRSS1_PHY_517_DATA
-				DDRSS1_PHY_518_DATA
-				DDRSS1_PHY_519_DATA
-				DDRSS1_PHY_520_DATA
-				DDRSS1_PHY_521_DATA
-				DDRSS1_PHY_522_DATA
-				DDRSS1_PHY_523_DATA
-				DDRSS1_PHY_524_DATA
-				DDRSS1_PHY_525_DATA
-				DDRSS1_PHY_526_DATA
-				DDRSS1_PHY_527_DATA
-				DDRSS1_PHY_528_DATA
-				DDRSS1_PHY_529_DATA
-				DDRSS1_PHY_530_DATA
-				DDRSS1_PHY_531_DATA
-				DDRSS1_PHY_532_DATA
-				DDRSS1_PHY_533_DATA
-				DDRSS1_PHY_534_DATA
-				DDRSS1_PHY_535_DATA
-				DDRSS1_PHY_536_DATA
-				DDRSS1_PHY_537_DATA
-				DDRSS1_PHY_538_DATA
-				DDRSS1_PHY_539_DATA
-				DDRSS1_PHY_540_DATA
-				DDRSS1_PHY_541_DATA
-				DDRSS1_PHY_542_DATA
-				DDRSS1_PHY_543_DATA
-				DDRSS1_PHY_544_DATA
-				DDRSS1_PHY_545_DATA
-				DDRSS1_PHY_546_DATA
-				DDRSS1_PHY_547_DATA
-				DDRSS1_PHY_548_DATA
-				DDRSS1_PHY_549_DATA
-				DDRSS1_PHY_550_DATA
-				DDRSS1_PHY_551_DATA
-				DDRSS1_PHY_552_DATA
-				DDRSS1_PHY_553_DATA
-				DDRSS1_PHY_554_DATA
-				DDRSS1_PHY_555_DATA
-				DDRSS1_PHY_556_DATA
-				DDRSS1_PHY_557_DATA
-				DDRSS1_PHY_558_DATA
-				DDRSS1_PHY_559_DATA
-				DDRSS1_PHY_560_DATA
-				DDRSS1_PHY_561_DATA
-				DDRSS1_PHY_562_DATA
-				DDRSS1_PHY_563_DATA
-				DDRSS1_PHY_564_DATA
-				DDRSS1_PHY_565_DATA
-				DDRSS1_PHY_566_DATA
-				DDRSS1_PHY_567_DATA
-				DDRSS1_PHY_568_DATA
-				DDRSS1_PHY_569_DATA
-				DDRSS1_PHY_570_DATA
-				DDRSS1_PHY_571_DATA
-				DDRSS1_PHY_572_DATA
-				DDRSS1_PHY_573_DATA
-				DDRSS1_PHY_574_DATA
-				DDRSS1_PHY_575_DATA
-				DDRSS1_PHY_576_DATA
-				DDRSS1_PHY_577_DATA
-				DDRSS1_PHY_578_DATA
-				DDRSS1_PHY_579_DATA
-				DDRSS1_PHY_580_DATA
-				DDRSS1_PHY_581_DATA
-				DDRSS1_PHY_582_DATA
-				DDRSS1_PHY_583_DATA
-				DDRSS1_PHY_584_DATA
-				DDRSS1_PHY_585_DATA
-				DDRSS1_PHY_586_DATA
-				DDRSS1_PHY_587_DATA
-				DDRSS1_PHY_588_DATA
-				DDRSS1_PHY_589_DATA
-				DDRSS1_PHY_590_DATA
-				DDRSS1_PHY_591_DATA
-				DDRSS1_PHY_592_DATA
-				DDRSS1_PHY_593_DATA
-				DDRSS1_PHY_594_DATA
-				DDRSS1_PHY_595_DATA
-				DDRSS1_PHY_596_DATA
-				DDRSS1_PHY_597_DATA
-				DDRSS1_PHY_598_DATA
-				DDRSS1_PHY_599_DATA
-				DDRSS1_PHY_600_DATA
-				DDRSS1_PHY_601_DATA
-				DDRSS1_PHY_602_DATA
-				DDRSS1_PHY_603_DATA
-				DDRSS1_PHY_604_DATA
-				DDRSS1_PHY_605_DATA
-				DDRSS1_PHY_606_DATA
-				DDRSS1_PHY_607_DATA
-				DDRSS1_PHY_608_DATA
-				DDRSS1_PHY_609_DATA
-				DDRSS1_PHY_610_DATA
-				DDRSS1_PHY_611_DATA
-				DDRSS1_PHY_612_DATA
-				DDRSS1_PHY_613_DATA
-				DDRSS1_PHY_614_DATA
-				DDRSS1_PHY_615_DATA
-				DDRSS1_PHY_616_DATA
-				DDRSS1_PHY_617_DATA
-				DDRSS1_PHY_618_DATA
-				DDRSS1_PHY_619_DATA
-				DDRSS1_PHY_620_DATA
-				DDRSS1_PHY_621_DATA
-				DDRSS1_PHY_622_DATA
-				DDRSS1_PHY_623_DATA
-				DDRSS1_PHY_624_DATA
-				DDRSS1_PHY_625_DATA
-				DDRSS1_PHY_626_DATA
-				DDRSS1_PHY_627_DATA
-				DDRSS1_PHY_628_DATA
-				DDRSS1_PHY_629_DATA
-				DDRSS1_PHY_630_DATA
-				DDRSS1_PHY_631_DATA
-				DDRSS1_PHY_632_DATA
-				DDRSS1_PHY_633_DATA
-				DDRSS1_PHY_634_DATA
-				DDRSS1_PHY_635_DATA
-				DDRSS1_PHY_636_DATA
-				DDRSS1_PHY_637_DATA
-				DDRSS1_PHY_638_DATA
-				DDRSS1_PHY_639_DATA
-				DDRSS1_PHY_640_DATA
-				DDRSS1_PHY_641_DATA
-				DDRSS1_PHY_642_DATA
-				DDRSS1_PHY_643_DATA
-				DDRSS1_PHY_644_DATA
-				DDRSS1_PHY_645_DATA
-				DDRSS1_PHY_646_DATA
-				DDRSS1_PHY_647_DATA
-				DDRSS1_PHY_648_DATA
-				DDRSS1_PHY_649_DATA
-				DDRSS1_PHY_650_DATA
-				DDRSS1_PHY_651_DATA
-				DDRSS1_PHY_652_DATA
-				DDRSS1_PHY_653_DATA
-				DDRSS1_PHY_654_DATA
-				DDRSS1_PHY_655_DATA
-				DDRSS1_PHY_656_DATA
-				DDRSS1_PHY_657_DATA
-				DDRSS1_PHY_658_DATA
-				DDRSS1_PHY_659_DATA
-				DDRSS1_PHY_660_DATA
-				DDRSS1_PHY_661_DATA
-				DDRSS1_PHY_662_DATA
-				DDRSS1_PHY_663_DATA
-				DDRSS1_PHY_664_DATA
-				DDRSS1_PHY_665_DATA
-				DDRSS1_PHY_666_DATA
-				DDRSS1_PHY_667_DATA
-				DDRSS1_PHY_668_DATA
-				DDRSS1_PHY_669_DATA
-				DDRSS1_PHY_670_DATA
-				DDRSS1_PHY_671_DATA
-				DDRSS1_PHY_672_DATA
-				DDRSS1_PHY_673_DATA
-				DDRSS1_PHY_674_DATA
-				DDRSS1_PHY_675_DATA
-				DDRSS1_PHY_676_DATA
-				DDRSS1_PHY_677_DATA
-				DDRSS1_PHY_678_DATA
-				DDRSS1_PHY_679_DATA
-				DDRSS1_PHY_680_DATA
-				DDRSS1_PHY_681_DATA
-				DDRSS1_PHY_682_DATA
-				DDRSS1_PHY_683_DATA
-				DDRSS1_PHY_684_DATA
-				DDRSS1_PHY_685_DATA
-				DDRSS1_PHY_686_DATA
-				DDRSS1_PHY_687_DATA
-				DDRSS1_PHY_688_DATA
-				DDRSS1_PHY_689_DATA
-				DDRSS1_PHY_690_DATA
-				DDRSS1_PHY_691_DATA
-				DDRSS1_PHY_692_DATA
-				DDRSS1_PHY_693_DATA
-				DDRSS1_PHY_694_DATA
-				DDRSS1_PHY_695_DATA
-				DDRSS1_PHY_696_DATA
-				DDRSS1_PHY_697_DATA
-				DDRSS1_PHY_698_DATA
-				DDRSS1_PHY_699_DATA
-				DDRSS1_PHY_700_DATA
-				DDRSS1_PHY_701_DATA
-				DDRSS1_PHY_702_DATA
-				DDRSS1_PHY_703_DATA
-				DDRSS1_PHY_704_DATA
-				DDRSS1_PHY_705_DATA
-				DDRSS1_PHY_706_DATA
-				DDRSS1_PHY_707_DATA
-				DDRSS1_PHY_708_DATA
-				DDRSS1_PHY_709_DATA
-				DDRSS1_PHY_710_DATA
-				DDRSS1_PHY_711_DATA
-				DDRSS1_PHY_712_DATA
-				DDRSS1_PHY_713_DATA
-				DDRSS1_PHY_714_DATA
-				DDRSS1_PHY_715_DATA
-				DDRSS1_PHY_716_DATA
-				DDRSS1_PHY_717_DATA
-				DDRSS1_PHY_718_DATA
-				DDRSS1_PHY_719_DATA
-				DDRSS1_PHY_720_DATA
-				DDRSS1_PHY_721_DATA
-				DDRSS1_PHY_722_DATA
-				DDRSS1_PHY_723_DATA
-				DDRSS1_PHY_724_DATA
-				DDRSS1_PHY_725_DATA
-				DDRSS1_PHY_726_DATA
-				DDRSS1_PHY_727_DATA
-				DDRSS1_PHY_728_DATA
-				DDRSS1_PHY_729_DATA
-				DDRSS1_PHY_730_DATA
-				DDRSS1_PHY_731_DATA
-				DDRSS1_PHY_732_DATA
-				DDRSS1_PHY_733_DATA
-				DDRSS1_PHY_734_DATA
-				DDRSS1_PHY_735_DATA
-				DDRSS1_PHY_736_DATA
-				DDRSS1_PHY_737_DATA
-				DDRSS1_PHY_738_DATA
-				DDRSS1_PHY_739_DATA
-				DDRSS1_PHY_740_DATA
-				DDRSS1_PHY_741_DATA
-				DDRSS1_PHY_742_DATA
-				DDRSS1_PHY_743_DATA
-				DDRSS1_PHY_744_DATA
-				DDRSS1_PHY_745_DATA
-				DDRSS1_PHY_746_DATA
-				DDRSS1_PHY_747_DATA
-				DDRSS1_PHY_748_DATA
-				DDRSS1_PHY_749_DATA
-				DDRSS1_PHY_750_DATA
-				DDRSS1_PHY_751_DATA
-				DDRSS1_PHY_752_DATA
-				DDRSS1_PHY_753_DATA
-				DDRSS1_PHY_754_DATA
-				DDRSS1_PHY_755_DATA
-				DDRSS1_PHY_756_DATA
-				DDRSS1_PHY_757_DATA
-				DDRSS1_PHY_758_DATA
-				DDRSS1_PHY_759_DATA
-				DDRSS1_PHY_760_DATA
-				DDRSS1_PHY_761_DATA
-				DDRSS1_PHY_762_DATA
-				DDRSS1_PHY_763_DATA
-				DDRSS1_PHY_764_DATA
-				DDRSS1_PHY_765_DATA
-				DDRSS1_PHY_766_DATA
-				DDRSS1_PHY_767_DATA
-				DDRSS1_PHY_768_DATA
-				DDRSS1_PHY_769_DATA
-				DDRSS1_PHY_770_DATA
-				DDRSS1_PHY_771_DATA
-				DDRSS1_PHY_772_DATA
-				DDRSS1_PHY_773_DATA
-				DDRSS1_PHY_774_DATA
-				DDRSS1_PHY_775_DATA
-				DDRSS1_PHY_776_DATA
-				DDRSS1_PHY_777_DATA
-				DDRSS1_PHY_778_DATA
-				DDRSS1_PHY_779_DATA
-				DDRSS1_PHY_780_DATA
-				DDRSS1_PHY_781_DATA
-				DDRSS1_PHY_782_DATA
-				DDRSS1_PHY_783_DATA
-				DDRSS1_PHY_784_DATA
-				DDRSS1_PHY_785_DATA
-				DDRSS1_PHY_786_DATA
-				DDRSS1_PHY_787_DATA
-				DDRSS1_PHY_788_DATA
-				DDRSS1_PHY_789_DATA
-				DDRSS1_PHY_790_DATA
-				DDRSS1_PHY_791_DATA
-				DDRSS1_PHY_792_DATA
-				DDRSS1_PHY_793_DATA
-				DDRSS1_PHY_794_DATA
-				DDRSS1_PHY_795_DATA
-				DDRSS1_PHY_796_DATA
-				DDRSS1_PHY_797_DATA
-				DDRSS1_PHY_798_DATA
-				DDRSS1_PHY_799_DATA
-				DDRSS1_PHY_800_DATA
-				DDRSS1_PHY_801_DATA
-				DDRSS1_PHY_802_DATA
-				DDRSS1_PHY_803_DATA
-				DDRSS1_PHY_804_DATA
-				DDRSS1_PHY_805_DATA
-				DDRSS1_PHY_806_DATA
-				DDRSS1_PHY_807_DATA
-				DDRSS1_PHY_808_DATA
-				DDRSS1_PHY_809_DATA
-				DDRSS1_PHY_810_DATA
-				DDRSS1_PHY_811_DATA
-				DDRSS1_PHY_812_DATA
-				DDRSS1_PHY_813_DATA
-				DDRSS1_PHY_814_DATA
-				DDRSS1_PHY_815_DATA
-				DDRSS1_PHY_816_DATA
-				DDRSS1_PHY_817_DATA
-				DDRSS1_PHY_818_DATA
-				DDRSS1_PHY_819_DATA
-				DDRSS1_PHY_820_DATA
-				DDRSS1_PHY_821_DATA
-				DDRSS1_PHY_822_DATA
-				DDRSS1_PHY_823_DATA
-				DDRSS1_PHY_824_DATA
-				DDRSS1_PHY_825_DATA
-				DDRSS1_PHY_826_DATA
-				DDRSS1_PHY_827_DATA
-				DDRSS1_PHY_828_DATA
-				DDRSS1_PHY_829_DATA
-				DDRSS1_PHY_830_DATA
-				DDRSS1_PHY_831_DATA
-				DDRSS1_PHY_832_DATA
-				DDRSS1_PHY_833_DATA
-				DDRSS1_PHY_834_DATA
-				DDRSS1_PHY_835_DATA
-				DDRSS1_PHY_836_DATA
-				DDRSS1_PHY_837_DATA
-				DDRSS1_PHY_838_DATA
-				DDRSS1_PHY_839_DATA
-				DDRSS1_PHY_840_DATA
-				DDRSS1_PHY_841_DATA
-				DDRSS1_PHY_842_DATA
-				DDRSS1_PHY_843_DATA
-				DDRSS1_PHY_844_DATA
-				DDRSS1_PHY_845_DATA
-				DDRSS1_PHY_846_DATA
-				DDRSS1_PHY_847_DATA
-				DDRSS1_PHY_848_DATA
-				DDRSS1_PHY_849_DATA
-				DDRSS1_PHY_850_DATA
-				DDRSS1_PHY_851_DATA
-				DDRSS1_PHY_852_DATA
-				DDRSS1_PHY_853_DATA
-				DDRSS1_PHY_854_DATA
-				DDRSS1_PHY_855_DATA
-				DDRSS1_PHY_856_DATA
-				DDRSS1_PHY_857_DATA
-				DDRSS1_PHY_858_DATA
-				DDRSS1_PHY_859_DATA
-				DDRSS1_PHY_860_DATA
-				DDRSS1_PHY_861_DATA
-				DDRSS1_PHY_862_DATA
-				DDRSS1_PHY_863_DATA
-				DDRSS1_PHY_864_DATA
-				DDRSS1_PHY_865_DATA
-				DDRSS1_PHY_866_DATA
-				DDRSS1_PHY_867_DATA
-				DDRSS1_PHY_868_DATA
-				DDRSS1_PHY_869_DATA
-				DDRSS1_PHY_870_DATA
-				DDRSS1_PHY_871_DATA
-				DDRSS1_PHY_872_DATA
-				DDRSS1_PHY_873_DATA
-				DDRSS1_PHY_874_DATA
-				DDRSS1_PHY_875_DATA
-				DDRSS1_PHY_876_DATA
-				DDRSS1_PHY_877_DATA
-				DDRSS1_PHY_878_DATA
-				DDRSS1_PHY_879_DATA
-				DDRSS1_PHY_880_DATA
-				DDRSS1_PHY_881_DATA
-				DDRSS1_PHY_882_DATA
-				DDRSS1_PHY_883_DATA
-				DDRSS1_PHY_884_DATA
-				DDRSS1_PHY_885_DATA
-				DDRSS1_PHY_886_DATA
-				DDRSS1_PHY_887_DATA
-				DDRSS1_PHY_888_DATA
-				DDRSS1_PHY_889_DATA
-				DDRSS1_PHY_890_DATA
-				DDRSS1_PHY_891_DATA
-				DDRSS1_PHY_892_DATA
-				DDRSS1_PHY_893_DATA
-				DDRSS1_PHY_894_DATA
-				DDRSS1_PHY_895_DATA
-				DDRSS1_PHY_896_DATA
-				DDRSS1_PHY_897_DATA
-				DDRSS1_PHY_898_DATA
-				DDRSS1_PHY_899_DATA
-				DDRSS1_PHY_900_DATA
-				DDRSS1_PHY_901_DATA
-				DDRSS1_PHY_902_DATA
-				DDRSS1_PHY_903_DATA
-				DDRSS1_PHY_904_DATA
-				DDRSS1_PHY_905_DATA
-				DDRSS1_PHY_906_DATA
-				DDRSS1_PHY_907_DATA
-				DDRSS1_PHY_908_DATA
-				DDRSS1_PHY_909_DATA
-				DDRSS1_PHY_910_DATA
-				DDRSS1_PHY_911_DATA
-				DDRSS1_PHY_912_DATA
-				DDRSS1_PHY_913_DATA
-				DDRSS1_PHY_914_DATA
-				DDRSS1_PHY_915_DATA
-				DDRSS1_PHY_916_DATA
-				DDRSS1_PHY_917_DATA
-				DDRSS1_PHY_918_DATA
-				DDRSS1_PHY_919_DATA
-				DDRSS1_PHY_920_DATA
-				DDRSS1_PHY_921_DATA
-				DDRSS1_PHY_922_DATA
-				DDRSS1_PHY_923_DATA
-				DDRSS1_PHY_924_DATA
-				DDRSS1_PHY_925_DATA
-				DDRSS1_PHY_926_DATA
-				DDRSS1_PHY_927_DATA
-				DDRSS1_PHY_928_DATA
-				DDRSS1_PHY_929_DATA
-				DDRSS1_PHY_930_DATA
-				DDRSS1_PHY_931_DATA
-				DDRSS1_PHY_932_DATA
-				DDRSS1_PHY_933_DATA
-				DDRSS1_PHY_934_DATA
-				DDRSS1_PHY_935_DATA
-				DDRSS1_PHY_936_DATA
-				DDRSS1_PHY_937_DATA
-				DDRSS1_PHY_938_DATA
-				DDRSS1_PHY_939_DATA
-				DDRSS1_PHY_940_DATA
-				DDRSS1_PHY_941_DATA
-				DDRSS1_PHY_942_DATA
-				DDRSS1_PHY_943_DATA
-				DDRSS1_PHY_944_DATA
-				DDRSS1_PHY_945_DATA
-				DDRSS1_PHY_946_DATA
-				DDRSS1_PHY_947_DATA
-				DDRSS1_PHY_948_DATA
-				DDRSS1_PHY_949_DATA
-				DDRSS1_PHY_950_DATA
-				DDRSS1_PHY_951_DATA
-				DDRSS1_PHY_952_DATA
-				DDRSS1_PHY_953_DATA
-				DDRSS1_PHY_954_DATA
-				DDRSS1_PHY_955_DATA
-				DDRSS1_PHY_956_DATA
-				DDRSS1_PHY_957_DATA
-				DDRSS1_PHY_958_DATA
-				DDRSS1_PHY_959_DATA
-				DDRSS1_PHY_960_DATA
-				DDRSS1_PHY_961_DATA
-				DDRSS1_PHY_962_DATA
-				DDRSS1_PHY_963_DATA
-				DDRSS1_PHY_964_DATA
-				DDRSS1_PHY_965_DATA
-				DDRSS1_PHY_966_DATA
-				DDRSS1_PHY_967_DATA
-				DDRSS1_PHY_968_DATA
-				DDRSS1_PHY_969_DATA
-				DDRSS1_PHY_970_DATA
-				DDRSS1_PHY_971_DATA
-				DDRSS1_PHY_972_DATA
-				DDRSS1_PHY_973_DATA
-				DDRSS1_PHY_974_DATA
-				DDRSS1_PHY_975_DATA
-				DDRSS1_PHY_976_DATA
-				DDRSS1_PHY_977_DATA
-				DDRSS1_PHY_978_DATA
-				DDRSS1_PHY_979_DATA
-				DDRSS1_PHY_980_DATA
-				DDRSS1_PHY_981_DATA
-				DDRSS1_PHY_982_DATA
-				DDRSS1_PHY_983_DATA
-				DDRSS1_PHY_984_DATA
-				DDRSS1_PHY_985_DATA
-				DDRSS1_PHY_986_DATA
-				DDRSS1_PHY_987_DATA
-				DDRSS1_PHY_988_DATA
-				DDRSS1_PHY_989_DATA
-				DDRSS1_PHY_990_DATA
-				DDRSS1_PHY_991_DATA
-				DDRSS1_PHY_992_DATA
-				DDRSS1_PHY_993_DATA
-				DDRSS1_PHY_994_DATA
-				DDRSS1_PHY_995_DATA
-				DDRSS1_PHY_996_DATA
-				DDRSS1_PHY_997_DATA
-				DDRSS1_PHY_998_DATA
-				DDRSS1_PHY_999_DATA
-				DDRSS1_PHY_1000_DATA
-				DDRSS1_PHY_1001_DATA
-				DDRSS1_PHY_1002_DATA
-				DDRSS1_PHY_1003_DATA
-				DDRSS1_PHY_1004_DATA
-				DDRSS1_PHY_1005_DATA
-				DDRSS1_PHY_1006_DATA
-				DDRSS1_PHY_1007_DATA
-				DDRSS1_PHY_1008_DATA
-				DDRSS1_PHY_1009_DATA
-				DDRSS1_PHY_1010_DATA
-				DDRSS1_PHY_1011_DATA
-				DDRSS1_PHY_1012_DATA
-				DDRSS1_PHY_1013_DATA
-				DDRSS1_PHY_1014_DATA
-				DDRSS1_PHY_1015_DATA
-				DDRSS1_PHY_1016_DATA
-				DDRSS1_PHY_1017_DATA
-				DDRSS1_PHY_1018_DATA
-				DDRSS1_PHY_1019_DATA
-				DDRSS1_PHY_1020_DATA
-				DDRSS1_PHY_1021_DATA
-				DDRSS1_PHY_1022_DATA
-				DDRSS1_PHY_1023_DATA
-				DDRSS1_PHY_1024_DATA
-				DDRSS1_PHY_1025_DATA
-				DDRSS1_PHY_1026_DATA
-				DDRSS1_PHY_1027_DATA
-				DDRSS1_PHY_1028_DATA
-				DDRSS1_PHY_1029_DATA
-				DDRSS1_PHY_1030_DATA
-				DDRSS1_PHY_1031_DATA
-				DDRSS1_PHY_1032_DATA
-				DDRSS1_PHY_1033_DATA
-				DDRSS1_PHY_1034_DATA
-				DDRSS1_PHY_1035_DATA
-				DDRSS1_PHY_1036_DATA
-				DDRSS1_PHY_1037_DATA
-				DDRSS1_PHY_1038_DATA
-				DDRSS1_PHY_1039_DATA
-				DDRSS1_PHY_1040_DATA
-				DDRSS1_PHY_1041_DATA
-				DDRSS1_PHY_1042_DATA
-				DDRSS1_PHY_1043_DATA
-				DDRSS1_PHY_1044_DATA
-				DDRSS1_PHY_1045_DATA
-				DDRSS1_PHY_1046_DATA
-				DDRSS1_PHY_1047_DATA
-				DDRSS1_PHY_1048_DATA
-				DDRSS1_PHY_1049_DATA
-				DDRSS1_PHY_1050_DATA
-				DDRSS1_PHY_1051_DATA
-				DDRSS1_PHY_1052_DATA
-				DDRSS1_PHY_1053_DATA
-				DDRSS1_PHY_1054_DATA
-				DDRSS1_PHY_1055_DATA
-				DDRSS1_PHY_1056_DATA
-				DDRSS1_PHY_1057_DATA
-				DDRSS1_PHY_1058_DATA
-				DDRSS1_PHY_1059_DATA
-				DDRSS1_PHY_1060_DATA
-				DDRSS1_PHY_1061_DATA
-				DDRSS1_PHY_1062_DATA
-				DDRSS1_PHY_1063_DATA
-				DDRSS1_PHY_1064_DATA
-				DDRSS1_PHY_1065_DATA
-				DDRSS1_PHY_1066_DATA
-				DDRSS1_PHY_1067_DATA
-				DDRSS1_PHY_1068_DATA
-				DDRSS1_PHY_1069_DATA
-				DDRSS1_PHY_1070_DATA
-				DDRSS1_PHY_1071_DATA
-				DDRSS1_PHY_1072_DATA
-				DDRSS1_PHY_1073_DATA
-				DDRSS1_PHY_1074_DATA
-				DDRSS1_PHY_1075_DATA
-				DDRSS1_PHY_1076_DATA
-				DDRSS1_PHY_1077_DATA
-				DDRSS1_PHY_1078_DATA
-				DDRSS1_PHY_1079_DATA
-				DDRSS1_PHY_1080_DATA
-				DDRSS1_PHY_1081_DATA
-				DDRSS1_PHY_1082_DATA
-				DDRSS1_PHY_1083_DATA
-				DDRSS1_PHY_1084_DATA
-				DDRSS1_PHY_1085_DATA
-				DDRSS1_PHY_1086_DATA
-				DDRSS1_PHY_1087_DATA
-				DDRSS1_PHY_1088_DATA
-				DDRSS1_PHY_1089_DATA
-				DDRSS1_PHY_1090_DATA
-				DDRSS1_PHY_1091_DATA
-				DDRSS1_PHY_1092_DATA
-				DDRSS1_PHY_1093_DATA
-				DDRSS1_PHY_1094_DATA
-				DDRSS1_PHY_1095_DATA
-				DDRSS1_PHY_1096_DATA
-				DDRSS1_PHY_1097_DATA
-				DDRSS1_PHY_1098_DATA
-				DDRSS1_PHY_1099_DATA
-				DDRSS1_PHY_1100_DATA
-				DDRSS1_PHY_1101_DATA
-				DDRSS1_PHY_1102_DATA
-				DDRSS1_PHY_1103_DATA
-				DDRSS1_PHY_1104_DATA
-				DDRSS1_PHY_1105_DATA
-				DDRSS1_PHY_1106_DATA
-				DDRSS1_PHY_1107_DATA
-				DDRSS1_PHY_1108_DATA
-				DDRSS1_PHY_1109_DATA
-				DDRSS1_PHY_1110_DATA
-				DDRSS1_PHY_1111_DATA
-				DDRSS1_PHY_1112_DATA
-				DDRSS1_PHY_1113_DATA
-				DDRSS1_PHY_1114_DATA
-				DDRSS1_PHY_1115_DATA
-				DDRSS1_PHY_1116_DATA
-				DDRSS1_PHY_1117_DATA
-				DDRSS1_PHY_1118_DATA
-				DDRSS1_PHY_1119_DATA
-				DDRSS1_PHY_1120_DATA
-				DDRSS1_PHY_1121_DATA
-				DDRSS1_PHY_1122_DATA
-				DDRSS1_PHY_1123_DATA
-				DDRSS1_PHY_1124_DATA
-				DDRSS1_PHY_1125_DATA
-				DDRSS1_PHY_1126_DATA
-				DDRSS1_PHY_1127_DATA
-				DDRSS1_PHY_1128_DATA
-				DDRSS1_PHY_1129_DATA
-				DDRSS1_PHY_1130_DATA
-				DDRSS1_PHY_1131_DATA
-				DDRSS1_PHY_1132_DATA
-				DDRSS1_PHY_1133_DATA
-				DDRSS1_PHY_1134_DATA
-				DDRSS1_PHY_1135_DATA
-				DDRSS1_PHY_1136_DATA
-				DDRSS1_PHY_1137_DATA
-				DDRSS1_PHY_1138_DATA
-				DDRSS1_PHY_1139_DATA
-				DDRSS1_PHY_1140_DATA
-				DDRSS1_PHY_1141_DATA
-				DDRSS1_PHY_1142_DATA
-				DDRSS1_PHY_1143_DATA
-				DDRSS1_PHY_1144_DATA
-				DDRSS1_PHY_1145_DATA
-				DDRSS1_PHY_1146_DATA
-				DDRSS1_PHY_1147_DATA
-				DDRSS1_PHY_1148_DATA
-				DDRSS1_PHY_1149_DATA
-				DDRSS1_PHY_1150_DATA
-				DDRSS1_PHY_1151_DATA
-				DDRSS1_PHY_1152_DATA
-				DDRSS1_PHY_1153_DATA
-				DDRSS1_PHY_1154_DATA
-				DDRSS1_PHY_1155_DATA
-				DDRSS1_PHY_1156_DATA
-				DDRSS1_PHY_1157_DATA
-				DDRSS1_PHY_1158_DATA
-				DDRSS1_PHY_1159_DATA
-				DDRSS1_PHY_1160_DATA
-				DDRSS1_PHY_1161_DATA
-				DDRSS1_PHY_1162_DATA
-				DDRSS1_PHY_1163_DATA
-				DDRSS1_PHY_1164_DATA
-				DDRSS1_PHY_1165_DATA
-				DDRSS1_PHY_1166_DATA
-				DDRSS1_PHY_1167_DATA
-				DDRSS1_PHY_1168_DATA
-				DDRSS1_PHY_1169_DATA
-				DDRSS1_PHY_1170_DATA
-				DDRSS1_PHY_1171_DATA
-				DDRSS1_PHY_1172_DATA
-				DDRSS1_PHY_1173_DATA
-				DDRSS1_PHY_1174_DATA
-				DDRSS1_PHY_1175_DATA
-				DDRSS1_PHY_1176_DATA
-				DDRSS1_PHY_1177_DATA
-				DDRSS1_PHY_1178_DATA
-				DDRSS1_PHY_1179_DATA
-				DDRSS1_PHY_1180_DATA
-				DDRSS1_PHY_1181_DATA
-				DDRSS1_PHY_1182_DATA
-				DDRSS1_PHY_1183_DATA
-				DDRSS1_PHY_1184_DATA
-				DDRSS1_PHY_1185_DATA
-				DDRSS1_PHY_1186_DATA
-				DDRSS1_PHY_1187_DATA
-				DDRSS1_PHY_1188_DATA
-				DDRSS1_PHY_1189_DATA
-				DDRSS1_PHY_1190_DATA
-				DDRSS1_PHY_1191_DATA
-				DDRSS1_PHY_1192_DATA
-				DDRSS1_PHY_1193_DATA
-				DDRSS1_PHY_1194_DATA
-				DDRSS1_PHY_1195_DATA
-				DDRSS1_PHY_1196_DATA
-				DDRSS1_PHY_1197_DATA
-				DDRSS1_PHY_1198_DATA
-				DDRSS1_PHY_1199_DATA
-				DDRSS1_PHY_1200_DATA
-				DDRSS1_PHY_1201_DATA
-				DDRSS1_PHY_1202_DATA
-				DDRSS1_PHY_1203_DATA
-				DDRSS1_PHY_1204_DATA
-				DDRSS1_PHY_1205_DATA
-				DDRSS1_PHY_1206_DATA
-				DDRSS1_PHY_1207_DATA
-				DDRSS1_PHY_1208_DATA
-				DDRSS1_PHY_1209_DATA
-				DDRSS1_PHY_1210_DATA
-				DDRSS1_PHY_1211_DATA
-				DDRSS1_PHY_1212_DATA
-				DDRSS1_PHY_1213_DATA
-				DDRSS1_PHY_1214_DATA
-				DDRSS1_PHY_1215_DATA
-				DDRSS1_PHY_1216_DATA
-				DDRSS1_PHY_1217_DATA
-				DDRSS1_PHY_1218_DATA
-				DDRSS1_PHY_1219_DATA
-				DDRSS1_PHY_1220_DATA
-				DDRSS1_PHY_1221_DATA
-				DDRSS1_PHY_1222_DATA
-				DDRSS1_PHY_1223_DATA
-				DDRSS1_PHY_1224_DATA
-				DDRSS1_PHY_1225_DATA
-				DDRSS1_PHY_1226_DATA
-				DDRSS1_PHY_1227_DATA
-				DDRSS1_PHY_1228_DATA
-				DDRSS1_PHY_1229_DATA
-				DDRSS1_PHY_1230_DATA
-				DDRSS1_PHY_1231_DATA
-				DDRSS1_PHY_1232_DATA
-				DDRSS1_PHY_1233_DATA
-				DDRSS1_PHY_1234_DATA
-				DDRSS1_PHY_1235_DATA
-				DDRSS1_PHY_1236_DATA
-				DDRSS1_PHY_1237_DATA
-				DDRSS1_PHY_1238_DATA
-				DDRSS1_PHY_1239_DATA
-				DDRSS1_PHY_1240_DATA
-				DDRSS1_PHY_1241_DATA
-				DDRSS1_PHY_1242_DATA
-				DDRSS1_PHY_1243_DATA
-				DDRSS1_PHY_1244_DATA
-				DDRSS1_PHY_1245_DATA
-				DDRSS1_PHY_1246_DATA
-				DDRSS1_PHY_1247_DATA
-				DDRSS1_PHY_1248_DATA
-				DDRSS1_PHY_1249_DATA
-				DDRSS1_PHY_1250_DATA
-				DDRSS1_PHY_1251_DATA
-				DDRSS1_PHY_1252_DATA
-				DDRSS1_PHY_1253_DATA
-				DDRSS1_PHY_1254_DATA
-				DDRSS1_PHY_1255_DATA
-				DDRSS1_PHY_1256_DATA
-				DDRSS1_PHY_1257_DATA
-				DDRSS1_PHY_1258_DATA
-				DDRSS1_PHY_1259_DATA
-				DDRSS1_PHY_1260_DATA
-				DDRSS1_PHY_1261_DATA
-				DDRSS1_PHY_1262_DATA
-				DDRSS1_PHY_1263_DATA
-				DDRSS1_PHY_1264_DATA
-				DDRSS1_PHY_1265_DATA
-				DDRSS1_PHY_1266_DATA
-				DDRSS1_PHY_1267_DATA
-				DDRSS1_PHY_1268_DATA
-				DDRSS1_PHY_1269_DATA
-				DDRSS1_PHY_1270_DATA
-				DDRSS1_PHY_1271_DATA
-				DDRSS1_PHY_1272_DATA
-				DDRSS1_PHY_1273_DATA
-				DDRSS1_PHY_1274_DATA
-				DDRSS1_PHY_1275_DATA
-				DDRSS1_PHY_1276_DATA
-				DDRSS1_PHY_1277_DATA
-				DDRSS1_PHY_1278_DATA
-				DDRSS1_PHY_1279_DATA
-				DDRSS1_PHY_1280_DATA
-				DDRSS1_PHY_1281_DATA
-				DDRSS1_PHY_1282_DATA
-				DDRSS1_PHY_1283_DATA
-				DDRSS1_PHY_1284_DATA
-				DDRSS1_PHY_1285_DATA
-				DDRSS1_PHY_1286_DATA
-				DDRSS1_PHY_1287_DATA
-				DDRSS1_PHY_1288_DATA
-				DDRSS1_PHY_1289_DATA
-				DDRSS1_PHY_1290_DATA
-				DDRSS1_PHY_1291_DATA
-				DDRSS1_PHY_1292_DATA
-				DDRSS1_PHY_1293_DATA
-				DDRSS1_PHY_1294_DATA
-				DDRSS1_PHY_1295_DATA
-				DDRSS1_PHY_1296_DATA
-				DDRSS1_PHY_1297_DATA
-				DDRSS1_PHY_1298_DATA
-				DDRSS1_PHY_1299_DATA
-				DDRSS1_PHY_1300_DATA
-				DDRSS1_PHY_1301_DATA
-				DDRSS1_PHY_1302_DATA
-				DDRSS1_PHY_1303_DATA
-				DDRSS1_PHY_1304_DATA
-				DDRSS1_PHY_1305_DATA
-				DDRSS1_PHY_1306_DATA
-				DDRSS1_PHY_1307_DATA
-				DDRSS1_PHY_1308_DATA
-				DDRSS1_PHY_1309_DATA
-				DDRSS1_PHY_1310_DATA
-				DDRSS1_PHY_1311_DATA
-				DDRSS1_PHY_1312_DATA
-				DDRSS1_PHY_1313_DATA
-				DDRSS1_PHY_1314_DATA
-				DDRSS1_PHY_1315_DATA
-				DDRSS1_PHY_1316_DATA
-				DDRSS1_PHY_1317_DATA
-				DDRSS1_PHY_1318_DATA
-				DDRSS1_PHY_1319_DATA
-				DDRSS1_PHY_1320_DATA
-				DDRSS1_PHY_1321_DATA
-				DDRSS1_PHY_1322_DATA
-				DDRSS1_PHY_1323_DATA
-				DDRSS1_PHY_1324_DATA
-				DDRSS1_PHY_1325_DATA
-				DDRSS1_PHY_1326_DATA
-				DDRSS1_PHY_1327_DATA
-				DDRSS1_PHY_1328_DATA
-				DDRSS1_PHY_1329_DATA
-				DDRSS1_PHY_1330_DATA
-				DDRSS1_PHY_1331_DATA
-				DDRSS1_PHY_1332_DATA
-				DDRSS1_PHY_1333_DATA
-				DDRSS1_PHY_1334_DATA
-				DDRSS1_PHY_1335_DATA
-				DDRSS1_PHY_1336_DATA
-				DDRSS1_PHY_1337_DATA
-				DDRSS1_PHY_1338_DATA
-				DDRSS1_PHY_1339_DATA
-				DDRSS1_PHY_1340_DATA
-				DDRSS1_PHY_1341_DATA
-				DDRSS1_PHY_1342_DATA
-				DDRSS1_PHY_1343_DATA
-				DDRSS1_PHY_1344_DATA
-				DDRSS1_PHY_1345_DATA
-				DDRSS1_PHY_1346_DATA
-				DDRSS1_PHY_1347_DATA
-				DDRSS1_PHY_1348_DATA
-				DDRSS1_PHY_1349_DATA
-				DDRSS1_PHY_1350_DATA
-				DDRSS1_PHY_1351_DATA
-				DDRSS1_PHY_1352_DATA
-				DDRSS1_PHY_1353_DATA
-				DDRSS1_PHY_1354_DATA
-				DDRSS1_PHY_1355_DATA
-				DDRSS1_PHY_1356_DATA
-				DDRSS1_PHY_1357_DATA
-				DDRSS1_PHY_1358_DATA
-				DDRSS1_PHY_1359_DATA
-				DDRSS1_PHY_1360_DATA
-				DDRSS1_PHY_1361_DATA
-				DDRSS1_PHY_1362_DATA
-				DDRSS1_PHY_1363_DATA
-				DDRSS1_PHY_1364_DATA
-				DDRSS1_PHY_1365_DATA
-				DDRSS1_PHY_1366_DATA
-				DDRSS1_PHY_1367_DATA
-				DDRSS1_PHY_1368_DATA
-				DDRSS1_PHY_1369_DATA
-				DDRSS1_PHY_1370_DATA
-				DDRSS1_PHY_1371_DATA
-				DDRSS1_PHY_1372_DATA
-				DDRSS1_PHY_1373_DATA
-				DDRSS1_PHY_1374_DATA
-				DDRSS1_PHY_1375_DATA
-				DDRSS1_PHY_1376_DATA
-				DDRSS1_PHY_1377_DATA
-				DDRSS1_PHY_1378_DATA
-				DDRSS1_PHY_1379_DATA
-				DDRSS1_PHY_1380_DATA
-				DDRSS1_PHY_1381_DATA
-				DDRSS1_PHY_1382_DATA
-				DDRSS1_PHY_1383_DATA
-				DDRSS1_PHY_1384_DATA
-				DDRSS1_PHY_1385_DATA
-				DDRSS1_PHY_1386_DATA
-				DDRSS1_PHY_1387_DATA
-				DDRSS1_PHY_1388_DATA
-				DDRSS1_PHY_1389_DATA
-				DDRSS1_PHY_1390_DATA
-				DDRSS1_PHY_1391_DATA
-				DDRSS1_PHY_1392_DATA
-				DDRSS1_PHY_1393_DATA
-				DDRSS1_PHY_1394_DATA
-				DDRSS1_PHY_1395_DATA
-				DDRSS1_PHY_1396_DATA
-				DDRSS1_PHY_1397_DATA
-				DDRSS1_PHY_1398_DATA
-				DDRSS1_PHY_1399_DATA
-				DDRSS1_PHY_1400_DATA
-				DDRSS1_PHY_1401_DATA
-				DDRSS1_PHY_1402_DATA
-				DDRSS1_PHY_1403_DATA
-				DDRSS1_PHY_1404_DATA
-				DDRSS1_PHY_1405_DATA
-				DDRSS1_PHY_1406_DATA
-				DDRSS1_PHY_1407_DATA
-				DDRSS1_PHY_1408_DATA
-				DDRSS1_PHY_1409_DATA
-				DDRSS1_PHY_1410_DATA
-				DDRSS1_PHY_1411_DATA
-				DDRSS1_PHY_1412_DATA
-				DDRSS1_PHY_1413_DATA
-				DDRSS1_PHY_1414_DATA
-				DDRSS1_PHY_1415_DATA
-				DDRSS1_PHY_1416_DATA
-				DDRSS1_PHY_1417_DATA
-				DDRSS1_PHY_1418_DATA
-				DDRSS1_PHY_1419_DATA
-				DDRSS1_PHY_1420_DATA
-				DDRSS1_PHY_1421_DATA
-				DDRSS1_PHY_1422_DATA
-			>;
-		};
-
-		memorycontroller2: memorycontroller@29d0000 {
-			compatible = "ti,j721s2-ddrss";
-			reg = <0x0 0x029d0000 0x0 0x4000>,
-			      <0x0 0x0114000 0x0 0x100>,
-			      <0x0 0x029c0000 0x0 0x200>;
-			reg-names = "cfg", "ctrl_mmr_lp4", "ss_cfg";
-			power-domains = <&k3_pds 193 TI_SCI_PD_SHARED>,
-				<&k3_pds 133 TI_SCI_PD_SHARED>;
-			clocks = <&k3_clks 193 1>, <&k3_clks 78 2>;
-			ti,ddr-freq0 = <DDRSS_PLL_FREQUENCY_0>;
-			ti,ddr-freq1 = <DDRSS_PLL_FREQUENCY_1>;
-			ti,ddr-freq2 = <DDRSS_PLL_FREQUENCY_2>;
-			ti,ddr-fhs-cnt = <DDRSS_PLL_FHS_CNT>;
-			instance = <2>;
-
-			bootph-pre-ram;
-
-			ti,ctl-data = <
-				DDRSS2_CTL_00_DATA
-				DDRSS2_CTL_01_DATA
-				DDRSS2_CTL_02_DATA
-				DDRSS2_CTL_03_DATA
-				DDRSS2_CTL_04_DATA
-				DDRSS2_CTL_05_DATA
-				DDRSS2_CTL_06_DATA
-				DDRSS2_CTL_07_DATA
-				DDRSS2_CTL_08_DATA
-				DDRSS2_CTL_09_DATA
-				DDRSS2_CTL_10_DATA
-				DDRSS2_CTL_11_DATA
-				DDRSS2_CTL_12_DATA
-				DDRSS2_CTL_13_DATA
-				DDRSS2_CTL_14_DATA
-				DDRSS2_CTL_15_DATA
-				DDRSS2_CTL_16_DATA
-				DDRSS2_CTL_17_DATA
-				DDRSS2_CTL_18_DATA
-				DDRSS2_CTL_19_DATA
-				DDRSS2_CTL_20_DATA
-				DDRSS2_CTL_21_DATA
-				DDRSS2_CTL_22_DATA
-				DDRSS2_CTL_23_DATA
-				DDRSS2_CTL_24_DATA
-				DDRSS2_CTL_25_DATA
-				DDRSS2_CTL_26_DATA
-				DDRSS2_CTL_27_DATA
-				DDRSS2_CTL_28_DATA
-				DDRSS2_CTL_29_DATA
-				DDRSS2_CTL_30_DATA
-				DDRSS2_CTL_31_DATA
-				DDRSS2_CTL_32_DATA
-				DDRSS2_CTL_33_DATA
-				DDRSS2_CTL_34_DATA
-				DDRSS2_CTL_35_DATA
-				DDRSS2_CTL_36_DATA
-				DDRSS2_CTL_37_DATA
-				DDRSS2_CTL_38_DATA
-				DDRSS2_CTL_39_DATA
-				DDRSS2_CTL_40_DATA
-				DDRSS2_CTL_41_DATA
-				DDRSS2_CTL_42_DATA
-				DDRSS2_CTL_43_DATA
-				DDRSS2_CTL_44_DATA
-				DDRSS2_CTL_45_DATA
-				DDRSS2_CTL_46_DATA
-				DDRSS2_CTL_47_DATA
-				DDRSS2_CTL_48_DATA
-				DDRSS2_CTL_49_DATA
-				DDRSS2_CTL_50_DATA
-				DDRSS2_CTL_51_DATA
-				DDRSS2_CTL_52_DATA
-				DDRSS2_CTL_53_DATA
-				DDRSS2_CTL_54_DATA
-				DDRSS2_CTL_55_DATA
-				DDRSS2_CTL_56_DATA
-				DDRSS2_CTL_57_DATA
-				DDRSS2_CTL_58_DATA
-				DDRSS2_CTL_59_DATA
-				DDRSS2_CTL_60_DATA
-				DDRSS2_CTL_61_DATA
-				DDRSS2_CTL_62_DATA
-				DDRSS2_CTL_63_DATA
-				DDRSS2_CTL_64_DATA
-				DDRSS2_CTL_65_DATA
-				DDRSS2_CTL_66_DATA
-				DDRSS2_CTL_67_DATA
-				DDRSS2_CTL_68_DATA
-				DDRSS2_CTL_69_DATA
-				DDRSS2_CTL_70_DATA
-				DDRSS2_CTL_71_DATA
-				DDRSS2_CTL_72_DATA
-				DDRSS2_CTL_73_DATA
-				DDRSS2_CTL_74_DATA
-				DDRSS2_CTL_75_DATA
-				DDRSS2_CTL_76_DATA
-				DDRSS2_CTL_77_DATA
-				DDRSS2_CTL_78_DATA
-				DDRSS2_CTL_79_DATA
-				DDRSS2_CTL_80_DATA
-				DDRSS2_CTL_81_DATA
-				DDRSS2_CTL_82_DATA
-				DDRSS2_CTL_83_DATA
-				DDRSS2_CTL_84_DATA
-				DDRSS2_CTL_85_DATA
-				DDRSS2_CTL_86_DATA
-				DDRSS2_CTL_87_DATA
-				DDRSS2_CTL_88_DATA
-				DDRSS2_CTL_89_DATA
-				DDRSS2_CTL_90_DATA
-				DDRSS2_CTL_91_DATA
-				DDRSS2_CTL_92_DATA
-				DDRSS2_CTL_93_DATA
-				DDRSS2_CTL_94_DATA
-				DDRSS2_CTL_95_DATA
-				DDRSS2_CTL_96_DATA
-				DDRSS2_CTL_97_DATA
-				DDRSS2_CTL_98_DATA
-				DDRSS2_CTL_99_DATA
-				DDRSS2_CTL_100_DATA
-				DDRSS2_CTL_101_DATA
-				DDRSS2_CTL_102_DATA
-				DDRSS2_CTL_103_DATA
-				DDRSS2_CTL_104_DATA
-				DDRSS2_CTL_105_DATA
-				DDRSS2_CTL_106_DATA
-				DDRSS2_CTL_107_DATA
-				DDRSS2_CTL_108_DATA
-				DDRSS2_CTL_109_DATA
-				DDRSS2_CTL_110_DATA
-				DDRSS2_CTL_111_DATA
-				DDRSS2_CTL_112_DATA
-				DDRSS2_CTL_113_DATA
-				DDRSS2_CTL_114_DATA
-				DDRSS2_CTL_115_DATA
-				DDRSS2_CTL_116_DATA
-				DDRSS2_CTL_117_DATA
-				DDRSS2_CTL_118_DATA
-				DDRSS2_CTL_119_DATA
-				DDRSS2_CTL_120_DATA
-				DDRSS2_CTL_121_DATA
-				DDRSS2_CTL_122_DATA
-				DDRSS2_CTL_123_DATA
-				DDRSS2_CTL_124_DATA
-				DDRSS2_CTL_125_DATA
-				DDRSS2_CTL_126_DATA
-				DDRSS2_CTL_127_DATA
-				DDRSS2_CTL_128_DATA
-				DDRSS2_CTL_129_DATA
-				DDRSS2_CTL_130_DATA
-				DDRSS2_CTL_131_DATA
-				DDRSS2_CTL_132_DATA
-				DDRSS2_CTL_133_DATA
-				DDRSS2_CTL_134_DATA
-				DDRSS2_CTL_135_DATA
-				DDRSS2_CTL_136_DATA
-				DDRSS2_CTL_137_DATA
-				DDRSS2_CTL_138_DATA
-				DDRSS2_CTL_139_DATA
-				DDRSS2_CTL_140_DATA
-				DDRSS2_CTL_141_DATA
-				DDRSS2_CTL_142_DATA
-				DDRSS2_CTL_143_DATA
-				DDRSS2_CTL_144_DATA
-				DDRSS2_CTL_145_DATA
-				DDRSS2_CTL_146_DATA
-				DDRSS2_CTL_147_DATA
-				DDRSS2_CTL_148_DATA
-				DDRSS2_CTL_149_DATA
-				DDRSS2_CTL_150_DATA
-				DDRSS2_CTL_151_DATA
-				DDRSS2_CTL_152_DATA
-				DDRSS2_CTL_153_DATA
-				DDRSS2_CTL_154_DATA
-				DDRSS2_CTL_155_DATA
-				DDRSS2_CTL_156_DATA
-				DDRSS2_CTL_157_DATA
-				DDRSS2_CTL_158_DATA
-				DDRSS2_CTL_159_DATA
-				DDRSS2_CTL_160_DATA
-				DDRSS2_CTL_161_DATA
-				DDRSS2_CTL_162_DATA
-				DDRSS2_CTL_163_DATA
-				DDRSS2_CTL_164_DATA
-				DDRSS2_CTL_165_DATA
-				DDRSS2_CTL_166_DATA
-				DDRSS2_CTL_167_DATA
-				DDRSS2_CTL_168_DATA
-				DDRSS2_CTL_169_DATA
-				DDRSS2_CTL_170_DATA
-				DDRSS2_CTL_171_DATA
-				DDRSS2_CTL_172_DATA
-				DDRSS2_CTL_173_DATA
-				DDRSS2_CTL_174_DATA
-				DDRSS2_CTL_175_DATA
-				DDRSS2_CTL_176_DATA
-				DDRSS2_CTL_177_DATA
-				DDRSS2_CTL_178_DATA
-				DDRSS2_CTL_179_DATA
-				DDRSS2_CTL_180_DATA
-				DDRSS2_CTL_181_DATA
-				DDRSS2_CTL_182_DATA
-				DDRSS2_CTL_183_DATA
-				DDRSS2_CTL_184_DATA
-				DDRSS2_CTL_185_DATA
-				DDRSS2_CTL_186_DATA
-				DDRSS2_CTL_187_DATA
-				DDRSS2_CTL_188_DATA
-				DDRSS2_CTL_189_DATA
-				DDRSS2_CTL_190_DATA
-				DDRSS2_CTL_191_DATA
-				DDRSS2_CTL_192_DATA
-				DDRSS2_CTL_193_DATA
-				DDRSS2_CTL_194_DATA
-				DDRSS2_CTL_195_DATA
-				DDRSS2_CTL_196_DATA
-				DDRSS2_CTL_197_DATA
-				DDRSS2_CTL_198_DATA
-				DDRSS2_CTL_199_DATA
-				DDRSS2_CTL_200_DATA
-				DDRSS2_CTL_201_DATA
-				DDRSS2_CTL_202_DATA
-				DDRSS2_CTL_203_DATA
-				DDRSS2_CTL_204_DATA
-				DDRSS2_CTL_205_DATA
-				DDRSS2_CTL_206_DATA
-				DDRSS2_CTL_207_DATA
-				DDRSS2_CTL_208_DATA
-				DDRSS2_CTL_209_DATA
-				DDRSS2_CTL_210_DATA
-				DDRSS2_CTL_211_DATA
-				DDRSS2_CTL_212_DATA
-				DDRSS2_CTL_213_DATA
-				DDRSS2_CTL_214_DATA
-				DDRSS2_CTL_215_DATA
-				DDRSS2_CTL_216_DATA
-				DDRSS2_CTL_217_DATA
-				DDRSS2_CTL_218_DATA
-				DDRSS2_CTL_219_DATA
-				DDRSS2_CTL_220_DATA
-				DDRSS2_CTL_221_DATA
-				DDRSS2_CTL_222_DATA
-				DDRSS2_CTL_223_DATA
-				DDRSS2_CTL_224_DATA
-				DDRSS2_CTL_225_DATA
-				DDRSS2_CTL_226_DATA
-				DDRSS2_CTL_227_DATA
-				DDRSS2_CTL_228_DATA
-				DDRSS2_CTL_229_DATA
-				DDRSS2_CTL_230_DATA
-				DDRSS2_CTL_231_DATA
-				DDRSS2_CTL_232_DATA
-				DDRSS2_CTL_233_DATA
-				DDRSS2_CTL_234_DATA
-				DDRSS2_CTL_235_DATA
-				DDRSS2_CTL_236_DATA
-				DDRSS2_CTL_237_DATA
-				DDRSS2_CTL_238_DATA
-				DDRSS2_CTL_239_DATA
-				DDRSS2_CTL_240_DATA
-				DDRSS2_CTL_241_DATA
-				DDRSS2_CTL_242_DATA
-				DDRSS2_CTL_243_DATA
-				DDRSS2_CTL_244_DATA
-				DDRSS2_CTL_245_DATA
-				DDRSS2_CTL_246_DATA
-				DDRSS2_CTL_247_DATA
-				DDRSS2_CTL_248_DATA
-				DDRSS2_CTL_249_DATA
-				DDRSS2_CTL_250_DATA
-				DDRSS2_CTL_251_DATA
-				DDRSS2_CTL_252_DATA
-				DDRSS2_CTL_253_DATA
-				DDRSS2_CTL_254_DATA
-				DDRSS2_CTL_255_DATA
-				DDRSS2_CTL_256_DATA
-				DDRSS2_CTL_257_DATA
-				DDRSS2_CTL_258_DATA
-				DDRSS2_CTL_259_DATA
-				DDRSS2_CTL_260_DATA
-				DDRSS2_CTL_261_DATA
-				DDRSS2_CTL_262_DATA
-				DDRSS2_CTL_263_DATA
-				DDRSS2_CTL_264_DATA
-				DDRSS2_CTL_265_DATA
-				DDRSS2_CTL_266_DATA
-				DDRSS2_CTL_267_DATA
-				DDRSS2_CTL_268_DATA
-				DDRSS2_CTL_269_DATA
-				DDRSS2_CTL_270_DATA
-				DDRSS2_CTL_271_DATA
-				DDRSS2_CTL_272_DATA
-				DDRSS2_CTL_273_DATA
-				DDRSS2_CTL_274_DATA
-				DDRSS2_CTL_275_DATA
-				DDRSS2_CTL_276_DATA
-				DDRSS2_CTL_277_DATA
-				DDRSS2_CTL_278_DATA
-				DDRSS2_CTL_279_DATA
-				DDRSS2_CTL_280_DATA
-				DDRSS2_CTL_281_DATA
-				DDRSS2_CTL_282_DATA
-				DDRSS2_CTL_283_DATA
-				DDRSS2_CTL_284_DATA
-				DDRSS2_CTL_285_DATA
-				DDRSS2_CTL_286_DATA
-				DDRSS2_CTL_287_DATA
-				DDRSS2_CTL_288_DATA
-				DDRSS2_CTL_289_DATA
-				DDRSS2_CTL_290_DATA
-				DDRSS2_CTL_291_DATA
-				DDRSS2_CTL_292_DATA
-				DDRSS2_CTL_293_DATA
-				DDRSS2_CTL_294_DATA
-				DDRSS2_CTL_295_DATA
-				DDRSS2_CTL_296_DATA
-				DDRSS2_CTL_297_DATA
-				DDRSS2_CTL_298_DATA
-				DDRSS2_CTL_299_DATA
-				DDRSS2_CTL_300_DATA
-				DDRSS2_CTL_301_DATA
-				DDRSS2_CTL_302_DATA
-				DDRSS2_CTL_303_DATA
-				DDRSS2_CTL_304_DATA
-				DDRSS2_CTL_305_DATA
-				DDRSS2_CTL_306_DATA
-				DDRSS2_CTL_307_DATA
-				DDRSS2_CTL_308_DATA
-				DDRSS2_CTL_309_DATA
-				DDRSS2_CTL_310_DATA
-				DDRSS2_CTL_311_DATA
-				DDRSS2_CTL_312_DATA
-				DDRSS2_CTL_313_DATA
-				DDRSS2_CTL_314_DATA
-				DDRSS2_CTL_315_DATA
-				DDRSS2_CTL_316_DATA
-				DDRSS2_CTL_317_DATA
-				DDRSS2_CTL_318_DATA
-				DDRSS2_CTL_319_DATA
-				DDRSS2_CTL_320_DATA
-				DDRSS2_CTL_321_DATA
-				DDRSS2_CTL_322_DATA
-				DDRSS2_CTL_323_DATA
-				DDRSS2_CTL_324_DATA
-				DDRSS2_CTL_325_DATA
-				DDRSS2_CTL_326_DATA
-				DDRSS2_CTL_327_DATA
-				DDRSS2_CTL_328_DATA
-				DDRSS2_CTL_329_DATA
-				DDRSS2_CTL_330_DATA
-				DDRSS2_CTL_331_DATA
-				DDRSS2_CTL_332_DATA
-				DDRSS2_CTL_333_DATA
-				DDRSS2_CTL_334_DATA
-				DDRSS2_CTL_335_DATA
-				DDRSS2_CTL_336_DATA
-				DDRSS2_CTL_337_DATA
-				DDRSS2_CTL_338_DATA
-				DDRSS2_CTL_339_DATA
-				DDRSS2_CTL_340_DATA
-				DDRSS2_CTL_341_DATA
-				DDRSS2_CTL_342_DATA
-				DDRSS2_CTL_343_DATA
-				DDRSS2_CTL_344_DATA
-				DDRSS2_CTL_345_DATA
-				DDRSS2_CTL_346_DATA
-				DDRSS2_CTL_347_DATA
-				DDRSS2_CTL_348_DATA
-				DDRSS2_CTL_349_DATA
-				DDRSS2_CTL_350_DATA
-				DDRSS2_CTL_351_DATA
-				DDRSS2_CTL_352_DATA
-				DDRSS2_CTL_353_DATA
-				DDRSS2_CTL_354_DATA
-				DDRSS2_CTL_355_DATA
-				DDRSS2_CTL_356_DATA
-				DDRSS2_CTL_357_DATA
-				DDRSS2_CTL_358_DATA
-				DDRSS2_CTL_359_DATA
-				DDRSS2_CTL_360_DATA
-				DDRSS2_CTL_361_DATA
-				DDRSS2_CTL_362_DATA
-				DDRSS2_CTL_363_DATA
-				DDRSS2_CTL_364_DATA
-				DDRSS2_CTL_365_DATA
-				DDRSS2_CTL_366_DATA
-				DDRSS2_CTL_367_DATA
-				DDRSS2_CTL_368_DATA
-				DDRSS2_CTL_369_DATA
-				DDRSS2_CTL_370_DATA
-				DDRSS2_CTL_371_DATA
-				DDRSS2_CTL_372_DATA
-				DDRSS2_CTL_373_DATA
-				DDRSS2_CTL_374_DATA
-				DDRSS2_CTL_375_DATA
-				DDRSS2_CTL_376_DATA
-				DDRSS2_CTL_377_DATA
-				DDRSS2_CTL_378_DATA
-				DDRSS2_CTL_379_DATA
-				DDRSS2_CTL_380_DATA
-				DDRSS2_CTL_381_DATA
-				DDRSS2_CTL_382_DATA
-				DDRSS2_CTL_383_DATA
-				DDRSS2_CTL_384_DATA
-				DDRSS2_CTL_385_DATA
-				DDRSS2_CTL_386_DATA
-				DDRSS2_CTL_387_DATA
-				DDRSS2_CTL_388_DATA
-				DDRSS2_CTL_389_DATA
-				DDRSS2_CTL_390_DATA
-				DDRSS2_CTL_391_DATA
-				DDRSS2_CTL_392_DATA
-				DDRSS2_CTL_393_DATA
-				DDRSS2_CTL_394_DATA
-				DDRSS2_CTL_395_DATA
-				DDRSS2_CTL_396_DATA
-				DDRSS2_CTL_397_DATA
-				DDRSS2_CTL_398_DATA
-				DDRSS2_CTL_399_DATA
-				DDRSS2_CTL_400_DATA
-				DDRSS2_CTL_401_DATA
-				DDRSS2_CTL_402_DATA
-				DDRSS2_CTL_403_DATA
-				DDRSS2_CTL_404_DATA
-				DDRSS2_CTL_405_DATA
-				DDRSS2_CTL_406_DATA
-				DDRSS2_CTL_407_DATA
-				DDRSS2_CTL_408_DATA
-				DDRSS2_CTL_409_DATA
-				DDRSS2_CTL_410_DATA
-				DDRSS2_CTL_411_DATA
-				DDRSS2_CTL_412_DATA
-				DDRSS2_CTL_413_DATA
-				DDRSS2_CTL_414_DATA
-				DDRSS2_CTL_415_DATA
-				DDRSS2_CTL_416_DATA
-				DDRSS2_CTL_417_DATA
-				DDRSS2_CTL_418_DATA
-				DDRSS2_CTL_419_DATA
-				DDRSS2_CTL_420_DATA
-				DDRSS2_CTL_421_DATA
-				DDRSS2_CTL_422_DATA
-				DDRSS2_CTL_423_DATA
-				DDRSS2_CTL_424_DATA
-				DDRSS2_CTL_425_DATA
-				DDRSS2_CTL_426_DATA
-				DDRSS2_CTL_427_DATA
-				DDRSS2_CTL_428_DATA
-				DDRSS2_CTL_429_DATA
-				DDRSS2_CTL_430_DATA
-				DDRSS2_CTL_431_DATA
-				DDRSS2_CTL_432_DATA
-				DDRSS2_CTL_433_DATA
-				DDRSS2_CTL_434_DATA
-				DDRSS2_CTL_435_DATA
-				DDRSS2_CTL_436_DATA
-				DDRSS2_CTL_437_DATA
-				DDRSS2_CTL_438_DATA
-				DDRSS2_CTL_439_DATA
-				DDRSS2_CTL_440_DATA
-				DDRSS2_CTL_441_DATA
-				DDRSS2_CTL_442_DATA
-				DDRSS2_CTL_443_DATA
-				DDRSS2_CTL_444_DATA
-				DDRSS2_CTL_445_DATA
-				DDRSS2_CTL_446_DATA
-				DDRSS2_CTL_447_DATA
-				DDRSS2_CTL_448_DATA
-				DDRSS2_CTL_449_DATA
-				DDRSS2_CTL_450_DATA
-				DDRSS2_CTL_451_DATA
-				DDRSS2_CTL_452_DATA
-				DDRSS2_CTL_453_DATA
-				DDRSS2_CTL_454_DATA
-				DDRSS2_CTL_455_DATA
-				DDRSS2_CTL_456_DATA
-				DDRSS2_CTL_457_DATA
-				DDRSS2_CTL_458_DATA
-			>;
-
-			ti,pi-data = <
-				DDRSS2_PI_00_DATA
-				DDRSS2_PI_01_DATA
-				DDRSS2_PI_02_DATA
-				DDRSS2_PI_03_DATA
-				DDRSS2_PI_04_DATA
-				DDRSS2_PI_05_DATA
-				DDRSS2_PI_06_DATA
-				DDRSS2_PI_07_DATA
-				DDRSS2_PI_08_DATA
-				DDRSS2_PI_09_DATA
-				DDRSS2_PI_10_DATA
-				DDRSS2_PI_11_DATA
-				DDRSS2_PI_12_DATA
-				DDRSS2_PI_13_DATA
-				DDRSS2_PI_14_DATA
-				DDRSS2_PI_15_DATA
-				DDRSS2_PI_16_DATA
-				DDRSS2_PI_17_DATA
-				DDRSS2_PI_18_DATA
-				DDRSS2_PI_19_DATA
-				DDRSS2_PI_20_DATA
-				DDRSS2_PI_21_DATA
-				DDRSS2_PI_22_DATA
-				DDRSS2_PI_23_DATA
-				DDRSS2_PI_24_DATA
-				DDRSS2_PI_25_DATA
-				DDRSS2_PI_26_DATA
-				DDRSS2_PI_27_DATA
-				DDRSS2_PI_28_DATA
-				DDRSS2_PI_29_DATA
-				DDRSS2_PI_30_DATA
-				DDRSS2_PI_31_DATA
-				DDRSS2_PI_32_DATA
-				DDRSS2_PI_33_DATA
-				DDRSS2_PI_34_DATA
-				DDRSS2_PI_35_DATA
-				DDRSS2_PI_36_DATA
-				DDRSS2_PI_37_DATA
-				DDRSS2_PI_38_DATA
-				DDRSS2_PI_39_DATA
-				DDRSS2_PI_40_DATA
-				DDRSS2_PI_41_DATA
-				DDRSS2_PI_42_DATA
-				DDRSS2_PI_43_DATA
-				DDRSS2_PI_44_DATA
-				DDRSS2_PI_45_DATA
-				DDRSS2_PI_46_DATA
-				DDRSS2_PI_47_DATA
-				DDRSS2_PI_48_DATA
-				DDRSS2_PI_49_DATA
-				DDRSS2_PI_50_DATA
-				DDRSS2_PI_51_DATA
-				DDRSS2_PI_52_DATA
-				DDRSS2_PI_53_DATA
-				DDRSS2_PI_54_DATA
-				DDRSS2_PI_55_DATA
-				DDRSS2_PI_56_DATA
-				DDRSS2_PI_57_DATA
-				DDRSS2_PI_58_DATA
-				DDRSS2_PI_59_DATA
-				DDRSS2_PI_60_DATA
-				DDRSS2_PI_61_DATA
-				DDRSS2_PI_62_DATA
-				DDRSS2_PI_63_DATA
-				DDRSS2_PI_64_DATA
-				DDRSS2_PI_65_DATA
-				DDRSS2_PI_66_DATA
-				DDRSS2_PI_67_DATA
-				DDRSS2_PI_68_DATA
-				DDRSS2_PI_69_DATA
-				DDRSS2_PI_70_DATA
-				DDRSS2_PI_71_DATA
-				DDRSS2_PI_72_DATA
-				DDRSS2_PI_73_DATA
-				DDRSS2_PI_74_DATA
-				DDRSS2_PI_75_DATA
-				DDRSS2_PI_76_DATA
-				DDRSS2_PI_77_DATA
-				DDRSS2_PI_78_DATA
-				DDRSS2_PI_79_DATA
-				DDRSS2_PI_80_DATA
-				DDRSS2_PI_81_DATA
-				DDRSS2_PI_82_DATA
-				DDRSS2_PI_83_DATA
-				DDRSS2_PI_84_DATA
-				DDRSS2_PI_85_DATA
-				DDRSS2_PI_86_DATA
-				DDRSS2_PI_87_DATA
-				DDRSS2_PI_88_DATA
-				DDRSS2_PI_89_DATA
-				DDRSS2_PI_90_DATA
-				DDRSS2_PI_91_DATA
-				DDRSS2_PI_92_DATA
-				DDRSS2_PI_93_DATA
-				DDRSS2_PI_94_DATA
-				DDRSS2_PI_95_DATA
-				DDRSS2_PI_96_DATA
-				DDRSS2_PI_97_DATA
-				DDRSS2_PI_98_DATA
-				DDRSS2_PI_99_DATA
-				DDRSS2_PI_100_DATA
-				DDRSS2_PI_101_DATA
-				DDRSS2_PI_102_DATA
-				DDRSS2_PI_103_DATA
-				DDRSS2_PI_104_DATA
-				DDRSS2_PI_105_DATA
-				DDRSS2_PI_106_DATA
-				DDRSS2_PI_107_DATA
-				DDRSS2_PI_108_DATA
-				DDRSS2_PI_109_DATA
-				DDRSS2_PI_110_DATA
-				DDRSS2_PI_111_DATA
-				DDRSS2_PI_112_DATA
-				DDRSS2_PI_113_DATA
-				DDRSS2_PI_114_DATA
-				DDRSS2_PI_115_DATA
-				DDRSS2_PI_116_DATA
-				DDRSS2_PI_117_DATA
-				DDRSS2_PI_118_DATA
-				DDRSS2_PI_119_DATA
-				DDRSS2_PI_120_DATA
-				DDRSS2_PI_121_DATA
-				DDRSS2_PI_122_DATA
-				DDRSS2_PI_123_DATA
-				DDRSS2_PI_124_DATA
-				DDRSS2_PI_125_DATA
-				DDRSS2_PI_126_DATA
-				DDRSS2_PI_127_DATA
-				DDRSS2_PI_128_DATA
-				DDRSS2_PI_129_DATA
-				DDRSS2_PI_130_DATA
-				DDRSS2_PI_131_DATA
-				DDRSS2_PI_132_DATA
-				DDRSS2_PI_133_DATA
-				DDRSS2_PI_134_DATA
-				DDRSS2_PI_135_DATA
-				DDRSS2_PI_136_DATA
-				DDRSS2_PI_137_DATA
-				DDRSS2_PI_138_DATA
-				DDRSS2_PI_139_DATA
-				DDRSS2_PI_140_DATA
-				DDRSS2_PI_141_DATA
-				DDRSS2_PI_142_DATA
-				DDRSS2_PI_143_DATA
-				DDRSS2_PI_144_DATA
-				DDRSS2_PI_145_DATA
-				DDRSS2_PI_146_DATA
-				DDRSS2_PI_147_DATA
-				DDRSS2_PI_148_DATA
-				DDRSS2_PI_149_DATA
-				DDRSS2_PI_150_DATA
-				DDRSS2_PI_151_DATA
-				DDRSS2_PI_152_DATA
-				DDRSS2_PI_153_DATA
-				DDRSS2_PI_154_DATA
-				DDRSS2_PI_155_DATA
-				DDRSS2_PI_156_DATA
-				DDRSS2_PI_157_DATA
-				DDRSS2_PI_158_DATA
-				DDRSS2_PI_159_DATA
-				DDRSS2_PI_160_DATA
-				DDRSS2_PI_161_DATA
-				DDRSS2_PI_162_DATA
-				DDRSS2_PI_163_DATA
-				DDRSS2_PI_164_DATA
-				DDRSS2_PI_165_DATA
-				DDRSS2_PI_166_DATA
-				DDRSS2_PI_167_DATA
-				DDRSS2_PI_168_DATA
-				DDRSS2_PI_169_DATA
-				DDRSS2_PI_170_DATA
-				DDRSS2_PI_171_DATA
-				DDRSS2_PI_172_DATA
-				DDRSS2_PI_173_DATA
-				DDRSS2_PI_174_DATA
-				DDRSS2_PI_175_DATA
-				DDRSS2_PI_176_DATA
-				DDRSS2_PI_177_DATA
-				DDRSS2_PI_178_DATA
-				DDRSS2_PI_179_DATA
-				DDRSS2_PI_180_DATA
-				DDRSS2_PI_181_DATA
-				DDRSS2_PI_182_DATA
-				DDRSS2_PI_183_DATA
-				DDRSS2_PI_184_DATA
-				DDRSS2_PI_185_DATA
-				DDRSS2_PI_186_DATA
-				DDRSS2_PI_187_DATA
-				DDRSS2_PI_188_DATA
-				DDRSS2_PI_189_DATA
-				DDRSS2_PI_190_DATA
-				DDRSS2_PI_191_DATA
-				DDRSS2_PI_192_DATA
-				DDRSS2_PI_193_DATA
-				DDRSS2_PI_194_DATA
-				DDRSS2_PI_195_DATA
-				DDRSS2_PI_196_DATA
-				DDRSS2_PI_197_DATA
-				DDRSS2_PI_198_DATA
-				DDRSS2_PI_199_DATA
-				DDRSS2_PI_200_DATA
-				DDRSS2_PI_201_DATA
-				DDRSS2_PI_202_DATA
-				DDRSS2_PI_203_DATA
-				DDRSS2_PI_204_DATA
-				DDRSS2_PI_205_DATA
-				DDRSS2_PI_206_DATA
-				DDRSS2_PI_207_DATA
-				DDRSS2_PI_208_DATA
-				DDRSS2_PI_209_DATA
-				DDRSS2_PI_210_DATA
-				DDRSS2_PI_211_DATA
-				DDRSS2_PI_212_DATA
-				DDRSS2_PI_213_DATA
-				DDRSS2_PI_214_DATA
-				DDRSS2_PI_215_DATA
-				DDRSS2_PI_216_DATA
-				DDRSS2_PI_217_DATA
-				DDRSS2_PI_218_DATA
-				DDRSS2_PI_219_DATA
-				DDRSS2_PI_220_DATA
-				DDRSS2_PI_221_DATA
-				DDRSS2_PI_222_DATA
-				DDRSS2_PI_223_DATA
-				DDRSS2_PI_224_DATA
-				DDRSS2_PI_225_DATA
-				DDRSS2_PI_226_DATA
-				DDRSS2_PI_227_DATA
-				DDRSS2_PI_228_DATA
-				DDRSS2_PI_229_DATA
-				DDRSS2_PI_230_DATA
-				DDRSS2_PI_231_DATA
-				DDRSS2_PI_232_DATA
-				DDRSS2_PI_233_DATA
-				DDRSS2_PI_234_DATA
-				DDRSS2_PI_235_DATA
-				DDRSS2_PI_236_DATA
-				DDRSS2_PI_237_DATA
-				DDRSS2_PI_238_DATA
-				DDRSS2_PI_239_DATA
-				DDRSS2_PI_240_DATA
-				DDRSS2_PI_241_DATA
-				DDRSS2_PI_242_DATA
-				DDRSS2_PI_243_DATA
-				DDRSS2_PI_244_DATA
-				DDRSS2_PI_245_DATA
-				DDRSS2_PI_246_DATA
-				DDRSS2_PI_247_DATA
-				DDRSS2_PI_248_DATA
-				DDRSS2_PI_249_DATA
-				DDRSS2_PI_250_DATA
-				DDRSS2_PI_251_DATA
-				DDRSS2_PI_252_DATA
-				DDRSS2_PI_253_DATA
-				DDRSS2_PI_254_DATA
-				DDRSS2_PI_255_DATA
-				DDRSS2_PI_256_DATA
-				DDRSS2_PI_257_DATA
-				DDRSS2_PI_258_DATA
-				DDRSS2_PI_259_DATA
-				DDRSS2_PI_260_DATA
-				DDRSS2_PI_261_DATA
-				DDRSS2_PI_262_DATA
-				DDRSS2_PI_263_DATA
-				DDRSS2_PI_264_DATA
-				DDRSS2_PI_265_DATA
-				DDRSS2_PI_266_DATA
-				DDRSS2_PI_267_DATA
-				DDRSS2_PI_268_DATA
-				DDRSS2_PI_269_DATA
-				DDRSS2_PI_270_DATA
-				DDRSS2_PI_271_DATA
-				DDRSS2_PI_272_DATA
-				DDRSS2_PI_273_DATA
-				DDRSS2_PI_274_DATA
-				DDRSS2_PI_275_DATA
-				DDRSS2_PI_276_DATA
-				DDRSS2_PI_277_DATA
-				DDRSS2_PI_278_DATA
-				DDRSS2_PI_279_DATA
-				DDRSS2_PI_280_DATA
-				DDRSS2_PI_281_DATA
-				DDRSS2_PI_282_DATA
-				DDRSS2_PI_283_DATA
-				DDRSS2_PI_284_DATA
-				DDRSS2_PI_285_DATA
-				DDRSS2_PI_286_DATA
-				DDRSS2_PI_287_DATA
-				DDRSS2_PI_288_DATA
-				DDRSS2_PI_289_DATA
-				DDRSS2_PI_290_DATA
-				DDRSS2_PI_291_DATA
-				DDRSS2_PI_292_DATA
-				DDRSS2_PI_293_DATA
-				DDRSS2_PI_294_DATA
-				DDRSS2_PI_295_DATA
-				DDRSS2_PI_296_DATA
-				DDRSS2_PI_297_DATA
-				DDRSS2_PI_298_DATA
-				DDRSS2_PI_299_DATA
-			>;
-
-			ti,phy-data = <
-				DDRSS2_PHY_00_DATA
-				DDRSS2_PHY_01_DATA
-				DDRSS2_PHY_02_DATA
-				DDRSS2_PHY_03_DATA
-				DDRSS2_PHY_04_DATA
-				DDRSS2_PHY_05_DATA
-				DDRSS2_PHY_06_DATA
-				DDRSS2_PHY_07_DATA
-				DDRSS2_PHY_08_DATA
-				DDRSS2_PHY_09_DATA
-				DDRSS2_PHY_10_DATA
-				DDRSS2_PHY_11_DATA
-				DDRSS2_PHY_12_DATA
-				DDRSS2_PHY_13_DATA
-				DDRSS2_PHY_14_DATA
-				DDRSS2_PHY_15_DATA
-				DDRSS2_PHY_16_DATA
-				DDRSS2_PHY_17_DATA
-				DDRSS2_PHY_18_DATA
-				DDRSS2_PHY_19_DATA
-				DDRSS2_PHY_20_DATA
-				DDRSS2_PHY_21_DATA
-				DDRSS2_PHY_22_DATA
-				DDRSS2_PHY_23_DATA
-				DDRSS2_PHY_24_DATA
-				DDRSS2_PHY_25_DATA
-				DDRSS2_PHY_26_DATA
-				DDRSS2_PHY_27_DATA
-				DDRSS2_PHY_28_DATA
-				DDRSS2_PHY_29_DATA
-				DDRSS2_PHY_30_DATA
-				DDRSS2_PHY_31_DATA
-				DDRSS2_PHY_32_DATA
-				DDRSS2_PHY_33_DATA
-				DDRSS2_PHY_34_DATA
-				DDRSS2_PHY_35_DATA
-				DDRSS2_PHY_36_DATA
-				DDRSS2_PHY_37_DATA
-				DDRSS2_PHY_38_DATA
-				DDRSS2_PHY_39_DATA
-				DDRSS2_PHY_40_DATA
-				DDRSS2_PHY_41_DATA
-				DDRSS2_PHY_42_DATA
-				DDRSS2_PHY_43_DATA
-				DDRSS2_PHY_44_DATA
-				DDRSS2_PHY_45_DATA
-				DDRSS2_PHY_46_DATA
-				DDRSS2_PHY_47_DATA
-				DDRSS2_PHY_48_DATA
-				DDRSS2_PHY_49_DATA
-				DDRSS2_PHY_50_DATA
-				DDRSS2_PHY_51_DATA
-				DDRSS2_PHY_52_DATA
-				DDRSS2_PHY_53_DATA
-				DDRSS2_PHY_54_DATA
-				DDRSS2_PHY_55_DATA
-				DDRSS2_PHY_56_DATA
-				DDRSS2_PHY_57_DATA
-				DDRSS2_PHY_58_DATA
-				DDRSS2_PHY_59_DATA
-				DDRSS2_PHY_60_DATA
-				DDRSS2_PHY_61_DATA
-				DDRSS2_PHY_62_DATA
-				DDRSS2_PHY_63_DATA
-				DDRSS2_PHY_64_DATA
-				DDRSS2_PHY_65_DATA
-				DDRSS2_PHY_66_DATA
-				DDRSS2_PHY_67_DATA
-				DDRSS2_PHY_68_DATA
-				DDRSS2_PHY_69_DATA
-				DDRSS2_PHY_70_DATA
-				DDRSS2_PHY_71_DATA
-				DDRSS2_PHY_72_DATA
-				DDRSS2_PHY_73_DATA
-				DDRSS2_PHY_74_DATA
-				DDRSS2_PHY_75_DATA
-				DDRSS2_PHY_76_DATA
-				DDRSS2_PHY_77_DATA
-				DDRSS2_PHY_78_DATA
-				DDRSS2_PHY_79_DATA
-				DDRSS2_PHY_80_DATA
-				DDRSS2_PHY_81_DATA
-				DDRSS2_PHY_82_DATA
-				DDRSS2_PHY_83_DATA
-				DDRSS2_PHY_84_DATA
-				DDRSS2_PHY_85_DATA
-				DDRSS2_PHY_86_DATA
-				DDRSS2_PHY_87_DATA
-				DDRSS2_PHY_88_DATA
-				DDRSS2_PHY_89_DATA
-				DDRSS2_PHY_90_DATA
-				DDRSS2_PHY_91_DATA
-				DDRSS2_PHY_92_DATA
-				DDRSS2_PHY_93_DATA
-				DDRSS2_PHY_94_DATA
-				DDRSS2_PHY_95_DATA
-				DDRSS2_PHY_96_DATA
-				DDRSS2_PHY_97_DATA
-				DDRSS2_PHY_98_DATA
-				DDRSS2_PHY_99_DATA
-				DDRSS2_PHY_100_DATA
-				DDRSS2_PHY_101_DATA
-				DDRSS2_PHY_102_DATA
-				DDRSS2_PHY_103_DATA
-				DDRSS2_PHY_104_DATA
-				DDRSS2_PHY_105_DATA
-				DDRSS2_PHY_106_DATA
-				DDRSS2_PHY_107_DATA
-				DDRSS2_PHY_108_DATA
-				DDRSS2_PHY_109_DATA
-				DDRSS2_PHY_110_DATA
-				DDRSS2_PHY_111_DATA
-				DDRSS2_PHY_112_DATA
-				DDRSS2_PHY_113_DATA
-				DDRSS2_PHY_114_DATA
-				DDRSS2_PHY_115_DATA
-				DDRSS2_PHY_116_DATA
-				DDRSS2_PHY_117_DATA
-				DDRSS2_PHY_118_DATA
-				DDRSS2_PHY_119_DATA
-				DDRSS2_PHY_120_DATA
-				DDRSS2_PHY_121_DATA
-				DDRSS2_PHY_122_DATA
-				DDRSS2_PHY_123_DATA
-				DDRSS2_PHY_124_DATA
-				DDRSS2_PHY_125_DATA
-				DDRSS2_PHY_126_DATA
-				DDRSS2_PHY_127_DATA
-				DDRSS2_PHY_128_DATA
-				DDRSS2_PHY_129_DATA
-				DDRSS2_PHY_130_DATA
-				DDRSS2_PHY_131_DATA
-				DDRSS2_PHY_132_DATA
-				DDRSS2_PHY_133_DATA
-				DDRSS2_PHY_134_DATA
-				DDRSS2_PHY_135_DATA
-				DDRSS2_PHY_136_DATA
-				DDRSS2_PHY_137_DATA
-				DDRSS2_PHY_138_DATA
-				DDRSS2_PHY_139_DATA
-				DDRSS2_PHY_140_DATA
-				DDRSS2_PHY_141_DATA
-				DDRSS2_PHY_142_DATA
-				DDRSS2_PHY_143_DATA
-				DDRSS2_PHY_144_DATA
-				DDRSS2_PHY_145_DATA
-				DDRSS2_PHY_146_DATA
-				DDRSS2_PHY_147_DATA
-				DDRSS2_PHY_148_DATA
-				DDRSS2_PHY_149_DATA
-				DDRSS2_PHY_150_DATA
-				DDRSS2_PHY_151_DATA
-				DDRSS2_PHY_152_DATA
-				DDRSS2_PHY_153_DATA
-				DDRSS2_PHY_154_DATA
-				DDRSS2_PHY_155_DATA
-				DDRSS2_PHY_156_DATA
-				DDRSS2_PHY_157_DATA
-				DDRSS2_PHY_158_DATA
-				DDRSS2_PHY_159_DATA
-				DDRSS2_PHY_160_DATA
-				DDRSS2_PHY_161_DATA
-				DDRSS2_PHY_162_DATA
-				DDRSS2_PHY_163_DATA
-				DDRSS2_PHY_164_DATA
-				DDRSS2_PHY_165_DATA
-				DDRSS2_PHY_166_DATA
-				DDRSS2_PHY_167_DATA
-				DDRSS2_PHY_168_DATA
-				DDRSS2_PHY_169_DATA
-				DDRSS2_PHY_170_DATA
-				DDRSS2_PHY_171_DATA
-				DDRSS2_PHY_172_DATA
-				DDRSS2_PHY_173_DATA
-				DDRSS2_PHY_174_DATA
-				DDRSS2_PHY_175_DATA
-				DDRSS2_PHY_176_DATA
-				DDRSS2_PHY_177_DATA
-				DDRSS2_PHY_178_DATA
-				DDRSS2_PHY_179_DATA
-				DDRSS2_PHY_180_DATA
-				DDRSS2_PHY_181_DATA
-				DDRSS2_PHY_182_DATA
-				DDRSS2_PHY_183_DATA
-				DDRSS2_PHY_184_DATA
-				DDRSS2_PHY_185_DATA
-				DDRSS2_PHY_186_DATA
-				DDRSS2_PHY_187_DATA
-				DDRSS2_PHY_188_DATA
-				DDRSS2_PHY_189_DATA
-				DDRSS2_PHY_190_DATA
-				DDRSS2_PHY_191_DATA
-				DDRSS2_PHY_192_DATA
-				DDRSS2_PHY_193_DATA
-				DDRSS2_PHY_194_DATA
-				DDRSS2_PHY_195_DATA
-				DDRSS2_PHY_196_DATA
-				DDRSS2_PHY_197_DATA
-				DDRSS2_PHY_198_DATA
-				DDRSS2_PHY_199_DATA
-				DDRSS2_PHY_200_DATA
-				DDRSS2_PHY_201_DATA
-				DDRSS2_PHY_202_DATA
-				DDRSS2_PHY_203_DATA
-				DDRSS2_PHY_204_DATA
-				DDRSS2_PHY_205_DATA
-				DDRSS2_PHY_206_DATA
-				DDRSS2_PHY_207_DATA
-				DDRSS2_PHY_208_DATA
-				DDRSS2_PHY_209_DATA
-				DDRSS2_PHY_210_DATA
-				DDRSS2_PHY_211_DATA
-				DDRSS2_PHY_212_DATA
-				DDRSS2_PHY_213_DATA
-				DDRSS2_PHY_214_DATA
-				DDRSS2_PHY_215_DATA
-				DDRSS2_PHY_216_DATA
-				DDRSS2_PHY_217_DATA
-				DDRSS2_PHY_218_DATA
-				DDRSS2_PHY_219_DATA
-				DDRSS2_PHY_220_DATA
-				DDRSS2_PHY_221_DATA
-				DDRSS2_PHY_222_DATA
-				DDRSS2_PHY_223_DATA
-				DDRSS2_PHY_224_DATA
-				DDRSS2_PHY_225_DATA
-				DDRSS2_PHY_226_DATA
-				DDRSS2_PHY_227_DATA
-				DDRSS2_PHY_228_DATA
-				DDRSS2_PHY_229_DATA
-				DDRSS2_PHY_230_DATA
-				DDRSS2_PHY_231_DATA
-				DDRSS2_PHY_232_DATA
-				DDRSS2_PHY_233_DATA
-				DDRSS2_PHY_234_DATA
-				DDRSS2_PHY_235_DATA
-				DDRSS2_PHY_236_DATA
-				DDRSS2_PHY_237_DATA
-				DDRSS2_PHY_238_DATA
-				DDRSS2_PHY_239_DATA
-				DDRSS2_PHY_240_DATA
-				DDRSS2_PHY_241_DATA
-				DDRSS2_PHY_242_DATA
-				DDRSS2_PHY_243_DATA
-				DDRSS2_PHY_244_DATA
-				DDRSS2_PHY_245_DATA
-				DDRSS2_PHY_246_DATA
-				DDRSS2_PHY_247_DATA
-				DDRSS2_PHY_248_DATA
-				DDRSS2_PHY_249_DATA
-				DDRSS2_PHY_250_DATA
-				DDRSS2_PHY_251_DATA
-				DDRSS2_PHY_252_DATA
-				DDRSS2_PHY_253_DATA
-				DDRSS2_PHY_254_DATA
-				DDRSS2_PHY_255_DATA
-				DDRSS2_PHY_256_DATA
-				DDRSS2_PHY_257_DATA
-				DDRSS2_PHY_258_DATA
-				DDRSS2_PHY_259_DATA
-				DDRSS2_PHY_260_DATA
-				DDRSS2_PHY_261_DATA
-				DDRSS2_PHY_262_DATA
-				DDRSS2_PHY_263_DATA
-				DDRSS2_PHY_264_DATA
-				DDRSS2_PHY_265_DATA
-				DDRSS2_PHY_266_DATA
-				DDRSS2_PHY_267_DATA
-				DDRSS2_PHY_268_DATA
-				DDRSS2_PHY_269_DATA
-				DDRSS2_PHY_270_DATA
-				DDRSS2_PHY_271_DATA
-				DDRSS2_PHY_272_DATA
-				DDRSS2_PHY_273_DATA
-				DDRSS2_PHY_274_DATA
-				DDRSS2_PHY_275_DATA
-				DDRSS2_PHY_276_DATA
-				DDRSS2_PHY_277_DATA
-				DDRSS2_PHY_278_DATA
-				DDRSS2_PHY_279_DATA
-				DDRSS2_PHY_280_DATA
-				DDRSS2_PHY_281_DATA
-				DDRSS2_PHY_282_DATA
-				DDRSS2_PHY_283_DATA
-				DDRSS2_PHY_284_DATA
-				DDRSS2_PHY_285_DATA
-				DDRSS2_PHY_286_DATA
-				DDRSS2_PHY_287_DATA
-				DDRSS2_PHY_288_DATA
-				DDRSS2_PHY_289_DATA
-				DDRSS2_PHY_290_DATA
-				DDRSS2_PHY_291_DATA
-				DDRSS2_PHY_292_DATA
-				DDRSS2_PHY_293_DATA
-				DDRSS2_PHY_294_DATA
-				DDRSS2_PHY_295_DATA
-				DDRSS2_PHY_296_DATA
-				DDRSS2_PHY_297_DATA
-				DDRSS2_PHY_298_DATA
-				DDRSS2_PHY_299_DATA
-				DDRSS2_PHY_300_DATA
-				DDRSS2_PHY_301_DATA
-				DDRSS2_PHY_302_DATA
-				DDRSS2_PHY_303_DATA
-				DDRSS2_PHY_304_DATA
-				DDRSS2_PHY_305_DATA
-				DDRSS2_PHY_306_DATA
-				DDRSS2_PHY_307_DATA
-				DDRSS2_PHY_308_DATA
-				DDRSS2_PHY_309_DATA
-				DDRSS2_PHY_310_DATA
-				DDRSS2_PHY_311_DATA
-				DDRSS2_PHY_312_DATA
-				DDRSS2_PHY_313_DATA
-				DDRSS2_PHY_314_DATA
-				DDRSS2_PHY_315_DATA
-				DDRSS2_PHY_316_DATA
-				DDRSS2_PHY_317_DATA
-				DDRSS2_PHY_318_DATA
-				DDRSS2_PHY_319_DATA
-				DDRSS2_PHY_320_DATA
-				DDRSS2_PHY_321_DATA
-				DDRSS2_PHY_322_DATA
-				DDRSS2_PHY_323_DATA
-				DDRSS2_PHY_324_DATA
-				DDRSS2_PHY_325_DATA
-				DDRSS2_PHY_326_DATA
-				DDRSS2_PHY_327_DATA
-				DDRSS2_PHY_328_DATA
-				DDRSS2_PHY_329_DATA
-				DDRSS2_PHY_330_DATA
-				DDRSS2_PHY_331_DATA
-				DDRSS2_PHY_332_DATA
-				DDRSS2_PHY_333_DATA
-				DDRSS2_PHY_334_DATA
-				DDRSS2_PHY_335_DATA
-				DDRSS2_PHY_336_DATA
-				DDRSS2_PHY_337_DATA
-				DDRSS2_PHY_338_DATA
-				DDRSS2_PHY_339_DATA
-				DDRSS2_PHY_340_DATA
-				DDRSS2_PHY_341_DATA
-				DDRSS2_PHY_342_DATA
-				DDRSS2_PHY_343_DATA
-				DDRSS2_PHY_344_DATA
-				DDRSS2_PHY_345_DATA
-				DDRSS2_PHY_346_DATA
-				DDRSS2_PHY_347_DATA
-				DDRSS2_PHY_348_DATA
-				DDRSS2_PHY_349_DATA
-				DDRSS2_PHY_350_DATA
-				DDRSS2_PHY_351_DATA
-				DDRSS2_PHY_352_DATA
-				DDRSS2_PHY_353_DATA
-				DDRSS2_PHY_354_DATA
-				DDRSS2_PHY_355_DATA
-				DDRSS2_PHY_356_DATA
-				DDRSS2_PHY_357_DATA
-				DDRSS2_PHY_358_DATA
-				DDRSS2_PHY_359_DATA
-				DDRSS2_PHY_360_DATA
-				DDRSS2_PHY_361_DATA
-				DDRSS2_PHY_362_DATA
-				DDRSS2_PHY_363_DATA
-				DDRSS2_PHY_364_DATA
-				DDRSS2_PHY_365_DATA
-				DDRSS2_PHY_366_DATA
-				DDRSS2_PHY_367_DATA
-				DDRSS2_PHY_368_DATA
-				DDRSS2_PHY_369_DATA
-				DDRSS2_PHY_370_DATA
-				DDRSS2_PHY_371_DATA
-				DDRSS2_PHY_372_DATA
-				DDRSS2_PHY_373_DATA
-				DDRSS2_PHY_374_DATA
-				DDRSS2_PHY_375_DATA
-				DDRSS2_PHY_376_DATA
-				DDRSS2_PHY_377_DATA
-				DDRSS2_PHY_378_DATA
-				DDRSS2_PHY_379_DATA
-				DDRSS2_PHY_380_DATA
-				DDRSS2_PHY_381_DATA
-				DDRSS2_PHY_382_DATA
-				DDRSS2_PHY_383_DATA
-				DDRSS2_PHY_384_DATA
-				DDRSS2_PHY_385_DATA
-				DDRSS2_PHY_386_DATA
-				DDRSS2_PHY_387_DATA
-				DDRSS2_PHY_388_DATA
-				DDRSS2_PHY_389_DATA
-				DDRSS2_PHY_390_DATA
-				DDRSS2_PHY_391_DATA
-				DDRSS2_PHY_392_DATA
-				DDRSS2_PHY_393_DATA
-				DDRSS2_PHY_394_DATA
-				DDRSS2_PHY_395_DATA
-				DDRSS2_PHY_396_DATA
-				DDRSS2_PHY_397_DATA
-				DDRSS2_PHY_398_DATA
-				DDRSS2_PHY_399_DATA
-				DDRSS2_PHY_400_DATA
-				DDRSS2_PHY_401_DATA
-				DDRSS2_PHY_402_DATA
-				DDRSS2_PHY_403_DATA
-				DDRSS2_PHY_404_DATA
-				DDRSS2_PHY_405_DATA
-				DDRSS2_PHY_406_DATA
-				DDRSS2_PHY_407_DATA
-				DDRSS2_PHY_408_DATA
-				DDRSS2_PHY_409_DATA
-				DDRSS2_PHY_410_DATA
-				DDRSS2_PHY_411_DATA
-				DDRSS2_PHY_412_DATA
-				DDRSS2_PHY_413_DATA
-				DDRSS2_PHY_414_DATA
-				DDRSS2_PHY_415_DATA
-				DDRSS2_PHY_416_DATA
-				DDRSS2_PHY_417_DATA
-				DDRSS2_PHY_418_DATA
-				DDRSS2_PHY_419_DATA
-				DDRSS2_PHY_420_DATA
-				DDRSS2_PHY_421_DATA
-				DDRSS2_PHY_422_DATA
-				DDRSS2_PHY_423_DATA
-				DDRSS2_PHY_424_DATA
-				DDRSS2_PHY_425_DATA
-				DDRSS2_PHY_426_DATA
-				DDRSS2_PHY_427_DATA
-				DDRSS2_PHY_428_DATA
-				DDRSS2_PHY_429_DATA
-				DDRSS2_PHY_430_DATA
-				DDRSS2_PHY_431_DATA
-				DDRSS2_PHY_432_DATA
-				DDRSS2_PHY_433_DATA
-				DDRSS2_PHY_434_DATA
-				DDRSS2_PHY_435_DATA
-				DDRSS2_PHY_436_DATA
-				DDRSS2_PHY_437_DATA
-				DDRSS2_PHY_438_DATA
-				DDRSS2_PHY_439_DATA
-				DDRSS2_PHY_440_DATA
-				DDRSS2_PHY_441_DATA
-				DDRSS2_PHY_442_DATA
-				DDRSS2_PHY_443_DATA
-				DDRSS2_PHY_444_DATA
-				DDRSS2_PHY_445_DATA
-				DDRSS2_PHY_446_DATA
-				DDRSS2_PHY_447_DATA
-				DDRSS2_PHY_448_DATA
-				DDRSS2_PHY_449_DATA
-				DDRSS2_PHY_450_DATA
-				DDRSS2_PHY_451_DATA
-				DDRSS2_PHY_452_DATA
-				DDRSS2_PHY_453_DATA
-				DDRSS2_PHY_454_DATA
-				DDRSS2_PHY_455_DATA
-				DDRSS2_PHY_456_DATA
-				DDRSS2_PHY_457_DATA
-				DDRSS2_PHY_458_DATA
-				DDRSS2_PHY_459_DATA
-				DDRSS2_PHY_460_DATA
-				DDRSS2_PHY_461_DATA
-				DDRSS2_PHY_462_DATA
-				DDRSS2_PHY_463_DATA
-				DDRSS2_PHY_464_DATA
-				DDRSS2_PHY_465_DATA
-				DDRSS2_PHY_466_DATA
-				DDRSS2_PHY_467_DATA
-				DDRSS2_PHY_468_DATA
-				DDRSS2_PHY_469_DATA
-				DDRSS2_PHY_470_DATA
-				DDRSS2_PHY_471_DATA
-				DDRSS2_PHY_472_DATA
-				DDRSS2_PHY_473_DATA
-				DDRSS2_PHY_474_DATA
-				DDRSS2_PHY_475_DATA
-				DDRSS2_PHY_476_DATA
-				DDRSS2_PHY_477_DATA
-				DDRSS2_PHY_478_DATA
-				DDRSS2_PHY_479_DATA
-				DDRSS2_PHY_480_DATA
-				DDRSS2_PHY_481_DATA
-				DDRSS2_PHY_482_DATA
-				DDRSS2_PHY_483_DATA
-				DDRSS2_PHY_484_DATA
-				DDRSS2_PHY_485_DATA
-				DDRSS2_PHY_486_DATA
-				DDRSS2_PHY_487_DATA
-				DDRSS2_PHY_488_DATA
-				DDRSS2_PHY_489_DATA
-				DDRSS2_PHY_490_DATA
-				DDRSS2_PHY_491_DATA
-				DDRSS2_PHY_492_DATA
-				DDRSS2_PHY_493_DATA
-				DDRSS2_PHY_494_DATA
-				DDRSS2_PHY_495_DATA
-				DDRSS2_PHY_496_DATA
-				DDRSS2_PHY_497_DATA
-				DDRSS2_PHY_498_DATA
-				DDRSS2_PHY_499_DATA
-				DDRSS2_PHY_500_DATA
-				DDRSS2_PHY_501_DATA
-				DDRSS2_PHY_502_DATA
-				DDRSS2_PHY_503_DATA
-				DDRSS2_PHY_504_DATA
-				DDRSS2_PHY_505_DATA
-				DDRSS2_PHY_506_DATA
-				DDRSS2_PHY_507_DATA
-				DDRSS2_PHY_508_DATA
-				DDRSS2_PHY_509_DATA
-				DDRSS2_PHY_510_DATA
-				DDRSS2_PHY_511_DATA
-				DDRSS2_PHY_512_DATA
-				DDRSS2_PHY_513_DATA
-				DDRSS2_PHY_514_DATA
-				DDRSS2_PHY_515_DATA
-				DDRSS2_PHY_516_DATA
-				DDRSS2_PHY_517_DATA
-				DDRSS2_PHY_518_DATA
-				DDRSS2_PHY_519_DATA
-				DDRSS2_PHY_520_DATA
-				DDRSS2_PHY_521_DATA
-				DDRSS2_PHY_522_DATA
-				DDRSS2_PHY_523_DATA
-				DDRSS2_PHY_524_DATA
-				DDRSS2_PHY_525_DATA
-				DDRSS2_PHY_526_DATA
-				DDRSS2_PHY_527_DATA
-				DDRSS2_PHY_528_DATA
-				DDRSS2_PHY_529_DATA
-				DDRSS2_PHY_530_DATA
-				DDRSS2_PHY_531_DATA
-				DDRSS2_PHY_532_DATA
-				DDRSS2_PHY_533_DATA
-				DDRSS2_PHY_534_DATA
-				DDRSS2_PHY_535_DATA
-				DDRSS2_PHY_536_DATA
-				DDRSS2_PHY_537_DATA
-				DDRSS2_PHY_538_DATA
-				DDRSS2_PHY_539_DATA
-				DDRSS2_PHY_540_DATA
-				DDRSS2_PHY_541_DATA
-				DDRSS2_PHY_542_DATA
-				DDRSS2_PHY_543_DATA
-				DDRSS2_PHY_544_DATA
-				DDRSS2_PHY_545_DATA
-				DDRSS2_PHY_546_DATA
-				DDRSS2_PHY_547_DATA
-				DDRSS2_PHY_548_DATA
-				DDRSS2_PHY_549_DATA
-				DDRSS2_PHY_550_DATA
-				DDRSS2_PHY_551_DATA
-				DDRSS2_PHY_552_DATA
-				DDRSS2_PHY_553_DATA
-				DDRSS2_PHY_554_DATA
-				DDRSS2_PHY_555_DATA
-				DDRSS2_PHY_556_DATA
-				DDRSS2_PHY_557_DATA
-				DDRSS2_PHY_558_DATA
-				DDRSS2_PHY_559_DATA
-				DDRSS2_PHY_560_DATA
-				DDRSS2_PHY_561_DATA
-				DDRSS2_PHY_562_DATA
-				DDRSS2_PHY_563_DATA
-				DDRSS2_PHY_564_DATA
-				DDRSS2_PHY_565_DATA
-				DDRSS2_PHY_566_DATA
-				DDRSS2_PHY_567_DATA
-				DDRSS2_PHY_568_DATA
-				DDRSS2_PHY_569_DATA
-				DDRSS2_PHY_570_DATA
-				DDRSS2_PHY_571_DATA
-				DDRSS2_PHY_572_DATA
-				DDRSS2_PHY_573_DATA
-				DDRSS2_PHY_574_DATA
-				DDRSS2_PHY_575_DATA
-				DDRSS2_PHY_576_DATA
-				DDRSS2_PHY_577_DATA
-				DDRSS2_PHY_578_DATA
-				DDRSS2_PHY_579_DATA
-				DDRSS2_PHY_580_DATA
-				DDRSS2_PHY_581_DATA
-				DDRSS2_PHY_582_DATA
-				DDRSS2_PHY_583_DATA
-				DDRSS2_PHY_584_DATA
-				DDRSS2_PHY_585_DATA
-				DDRSS2_PHY_586_DATA
-				DDRSS2_PHY_587_DATA
-				DDRSS2_PHY_588_DATA
-				DDRSS2_PHY_589_DATA
-				DDRSS2_PHY_590_DATA
-				DDRSS2_PHY_591_DATA
-				DDRSS2_PHY_592_DATA
-				DDRSS2_PHY_593_DATA
-				DDRSS2_PHY_594_DATA
-				DDRSS2_PHY_595_DATA
-				DDRSS2_PHY_596_DATA
-				DDRSS2_PHY_597_DATA
-				DDRSS2_PHY_598_DATA
-				DDRSS2_PHY_599_DATA
-				DDRSS2_PHY_600_DATA
-				DDRSS2_PHY_601_DATA
-				DDRSS2_PHY_602_DATA
-				DDRSS2_PHY_603_DATA
-				DDRSS2_PHY_604_DATA
-				DDRSS2_PHY_605_DATA
-				DDRSS2_PHY_606_DATA
-				DDRSS2_PHY_607_DATA
-				DDRSS2_PHY_608_DATA
-				DDRSS2_PHY_609_DATA
-				DDRSS2_PHY_610_DATA
-				DDRSS2_PHY_611_DATA
-				DDRSS2_PHY_612_DATA
-				DDRSS2_PHY_613_DATA
-				DDRSS2_PHY_614_DATA
-				DDRSS2_PHY_615_DATA
-				DDRSS2_PHY_616_DATA
-				DDRSS2_PHY_617_DATA
-				DDRSS2_PHY_618_DATA
-				DDRSS2_PHY_619_DATA
-				DDRSS2_PHY_620_DATA
-				DDRSS2_PHY_621_DATA
-				DDRSS2_PHY_622_DATA
-				DDRSS2_PHY_623_DATA
-				DDRSS2_PHY_624_DATA
-				DDRSS2_PHY_625_DATA
-				DDRSS2_PHY_626_DATA
-				DDRSS2_PHY_627_DATA
-				DDRSS2_PHY_628_DATA
-				DDRSS2_PHY_629_DATA
-				DDRSS2_PHY_630_DATA
-				DDRSS2_PHY_631_DATA
-				DDRSS2_PHY_632_DATA
-				DDRSS2_PHY_633_DATA
-				DDRSS2_PHY_634_DATA
-				DDRSS2_PHY_635_DATA
-				DDRSS2_PHY_636_DATA
-				DDRSS2_PHY_637_DATA
-				DDRSS2_PHY_638_DATA
-				DDRSS2_PHY_639_DATA
-				DDRSS2_PHY_640_DATA
-				DDRSS2_PHY_641_DATA
-				DDRSS2_PHY_642_DATA
-				DDRSS2_PHY_643_DATA
-				DDRSS2_PHY_644_DATA
-				DDRSS2_PHY_645_DATA
-				DDRSS2_PHY_646_DATA
-				DDRSS2_PHY_647_DATA
-				DDRSS2_PHY_648_DATA
-				DDRSS2_PHY_649_DATA
-				DDRSS2_PHY_650_DATA
-				DDRSS2_PHY_651_DATA
-				DDRSS2_PHY_652_DATA
-				DDRSS2_PHY_653_DATA
-				DDRSS2_PHY_654_DATA
-				DDRSS2_PHY_655_DATA
-				DDRSS2_PHY_656_DATA
-				DDRSS2_PHY_657_DATA
-				DDRSS2_PHY_658_DATA
-				DDRSS2_PHY_659_DATA
-				DDRSS2_PHY_660_DATA
-				DDRSS2_PHY_661_DATA
-				DDRSS2_PHY_662_DATA
-				DDRSS2_PHY_663_DATA
-				DDRSS2_PHY_664_DATA
-				DDRSS2_PHY_665_DATA
-				DDRSS2_PHY_666_DATA
-				DDRSS2_PHY_667_DATA
-				DDRSS2_PHY_668_DATA
-				DDRSS2_PHY_669_DATA
-				DDRSS2_PHY_670_DATA
-				DDRSS2_PHY_671_DATA
-				DDRSS2_PHY_672_DATA
-				DDRSS2_PHY_673_DATA
-				DDRSS2_PHY_674_DATA
-				DDRSS2_PHY_675_DATA
-				DDRSS2_PHY_676_DATA
-				DDRSS2_PHY_677_DATA
-				DDRSS2_PHY_678_DATA
-				DDRSS2_PHY_679_DATA
-				DDRSS2_PHY_680_DATA
-				DDRSS2_PHY_681_DATA
-				DDRSS2_PHY_682_DATA
-				DDRSS2_PHY_683_DATA
-				DDRSS2_PHY_684_DATA
-				DDRSS2_PHY_685_DATA
-				DDRSS2_PHY_686_DATA
-				DDRSS2_PHY_687_DATA
-				DDRSS2_PHY_688_DATA
-				DDRSS2_PHY_689_DATA
-				DDRSS2_PHY_690_DATA
-				DDRSS2_PHY_691_DATA
-				DDRSS2_PHY_692_DATA
-				DDRSS2_PHY_693_DATA
-				DDRSS2_PHY_694_DATA
-				DDRSS2_PHY_695_DATA
-				DDRSS2_PHY_696_DATA
-				DDRSS2_PHY_697_DATA
-				DDRSS2_PHY_698_DATA
-				DDRSS2_PHY_699_DATA
-				DDRSS2_PHY_700_DATA
-				DDRSS2_PHY_701_DATA
-				DDRSS2_PHY_702_DATA
-				DDRSS2_PHY_703_DATA
-				DDRSS2_PHY_704_DATA
-				DDRSS2_PHY_705_DATA
-				DDRSS2_PHY_706_DATA
-				DDRSS2_PHY_707_DATA
-				DDRSS2_PHY_708_DATA
-				DDRSS2_PHY_709_DATA
-				DDRSS2_PHY_710_DATA
-				DDRSS2_PHY_711_DATA
-				DDRSS2_PHY_712_DATA
-				DDRSS2_PHY_713_DATA
-				DDRSS2_PHY_714_DATA
-				DDRSS2_PHY_715_DATA
-				DDRSS2_PHY_716_DATA
-				DDRSS2_PHY_717_DATA
-				DDRSS2_PHY_718_DATA
-				DDRSS2_PHY_719_DATA
-				DDRSS2_PHY_720_DATA
-				DDRSS2_PHY_721_DATA
-				DDRSS2_PHY_722_DATA
-				DDRSS2_PHY_723_DATA
-				DDRSS2_PHY_724_DATA
-				DDRSS2_PHY_725_DATA
-				DDRSS2_PHY_726_DATA
-				DDRSS2_PHY_727_DATA
-				DDRSS2_PHY_728_DATA
-				DDRSS2_PHY_729_DATA
-				DDRSS2_PHY_730_DATA
-				DDRSS2_PHY_731_DATA
-				DDRSS2_PHY_732_DATA
-				DDRSS2_PHY_733_DATA
-				DDRSS2_PHY_734_DATA
-				DDRSS2_PHY_735_DATA
-				DDRSS2_PHY_736_DATA
-				DDRSS2_PHY_737_DATA
-				DDRSS2_PHY_738_DATA
-				DDRSS2_PHY_739_DATA
-				DDRSS2_PHY_740_DATA
-				DDRSS2_PHY_741_DATA
-				DDRSS2_PHY_742_DATA
-				DDRSS2_PHY_743_DATA
-				DDRSS2_PHY_744_DATA
-				DDRSS2_PHY_745_DATA
-				DDRSS2_PHY_746_DATA
-				DDRSS2_PHY_747_DATA
-				DDRSS2_PHY_748_DATA
-				DDRSS2_PHY_749_DATA
-				DDRSS2_PHY_750_DATA
-				DDRSS2_PHY_751_DATA
-				DDRSS2_PHY_752_DATA
-				DDRSS2_PHY_753_DATA
-				DDRSS2_PHY_754_DATA
-				DDRSS2_PHY_755_DATA
-				DDRSS2_PHY_756_DATA
-				DDRSS2_PHY_757_DATA
-				DDRSS2_PHY_758_DATA
-				DDRSS2_PHY_759_DATA
-				DDRSS2_PHY_760_DATA
-				DDRSS2_PHY_761_DATA
-				DDRSS2_PHY_762_DATA
-				DDRSS2_PHY_763_DATA
-				DDRSS2_PHY_764_DATA
-				DDRSS2_PHY_765_DATA
-				DDRSS2_PHY_766_DATA
-				DDRSS2_PHY_767_DATA
-				DDRSS2_PHY_768_DATA
-				DDRSS2_PHY_769_DATA
-				DDRSS2_PHY_770_DATA
-				DDRSS2_PHY_771_DATA
-				DDRSS2_PHY_772_DATA
-				DDRSS2_PHY_773_DATA
-				DDRSS2_PHY_774_DATA
-				DDRSS2_PHY_775_DATA
-				DDRSS2_PHY_776_DATA
-				DDRSS2_PHY_777_DATA
-				DDRSS2_PHY_778_DATA
-				DDRSS2_PHY_779_DATA
-				DDRSS2_PHY_780_DATA
-				DDRSS2_PHY_781_DATA
-				DDRSS2_PHY_782_DATA
-				DDRSS2_PHY_783_DATA
-				DDRSS2_PHY_784_DATA
-				DDRSS2_PHY_785_DATA
-				DDRSS2_PHY_786_DATA
-				DDRSS2_PHY_787_DATA
-				DDRSS2_PHY_788_DATA
-				DDRSS2_PHY_789_DATA
-				DDRSS2_PHY_790_DATA
-				DDRSS2_PHY_791_DATA
-				DDRSS2_PHY_792_DATA
-				DDRSS2_PHY_793_DATA
-				DDRSS2_PHY_794_DATA
-				DDRSS2_PHY_795_DATA
-				DDRSS2_PHY_796_DATA
-				DDRSS2_PHY_797_DATA
-				DDRSS2_PHY_798_DATA
-				DDRSS2_PHY_799_DATA
-				DDRSS2_PHY_800_DATA
-				DDRSS2_PHY_801_DATA
-				DDRSS2_PHY_802_DATA
-				DDRSS2_PHY_803_DATA
-				DDRSS2_PHY_804_DATA
-				DDRSS2_PHY_805_DATA
-				DDRSS2_PHY_806_DATA
-				DDRSS2_PHY_807_DATA
-				DDRSS2_PHY_808_DATA
-				DDRSS2_PHY_809_DATA
-				DDRSS2_PHY_810_DATA
-				DDRSS2_PHY_811_DATA
-				DDRSS2_PHY_812_DATA
-				DDRSS2_PHY_813_DATA
-				DDRSS2_PHY_814_DATA
-				DDRSS2_PHY_815_DATA
-				DDRSS2_PHY_816_DATA
-				DDRSS2_PHY_817_DATA
-				DDRSS2_PHY_818_DATA
-				DDRSS2_PHY_819_DATA
-				DDRSS2_PHY_820_DATA
-				DDRSS2_PHY_821_DATA
-				DDRSS2_PHY_822_DATA
-				DDRSS2_PHY_823_DATA
-				DDRSS2_PHY_824_DATA
-				DDRSS2_PHY_825_DATA
-				DDRSS2_PHY_826_DATA
-				DDRSS2_PHY_827_DATA
-				DDRSS2_PHY_828_DATA
-				DDRSS2_PHY_829_DATA
-				DDRSS2_PHY_830_DATA
-				DDRSS2_PHY_831_DATA
-				DDRSS2_PHY_832_DATA
-				DDRSS2_PHY_833_DATA
-				DDRSS2_PHY_834_DATA
-				DDRSS2_PHY_835_DATA
-				DDRSS2_PHY_836_DATA
-				DDRSS2_PHY_837_DATA
-				DDRSS2_PHY_838_DATA
-				DDRSS2_PHY_839_DATA
-				DDRSS2_PHY_840_DATA
-				DDRSS2_PHY_841_DATA
-				DDRSS2_PHY_842_DATA
-				DDRSS2_PHY_843_DATA
-				DDRSS2_PHY_844_DATA
-				DDRSS2_PHY_845_DATA
-				DDRSS2_PHY_846_DATA
-				DDRSS2_PHY_847_DATA
-				DDRSS2_PHY_848_DATA
-				DDRSS2_PHY_849_DATA
-				DDRSS2_PHY_850_DATA
-				DDRSS2_PHY_851_DATA
-				DDRSS2_PHY_852_DATA
-				DDRSS2_PHY_853_DATA
-				DDRSS2_PHY_854_DATA
-				DDRSS2_PHY_855_DATA
-				DDRSS2_PHY_856_DATA
-				DDRSS2_PHY_857_DATA
-				DDRSS2_PHY_858_DATA
-				DDRSS2_PHY_859_DATA
-				DDRSS2_PHY_860_DATA
-				DDRSS2_PHY_861_DATA
-				DDRSS2_PHY_862_DATA
-				DDRSS2_PHY_863_DATA
-				DDRSS2_PHY_864_DATA
-				DDRSS2_PHY_865_DATA
-				DDRSS2_PHY_866_DATA
-				DDRSS2_PHY_867_DATA
-				DDRSS2_PHY_868_DATA
-				DDRSS2_PHY_869_DATA
-				DDRSS2_PHY_870_DATA
-				DDRSS2_PHY_871_DATA
-				DDRSS2_PHY_872_DATA
-				DDRSS2_PHY_873_DATA
-				DDRSS2_PHY_874_DATA
-				DDRSS2_PHY_875_DATA
-				DDRSS2_PHY_876_DATA
-				DDRSS2_PHY_877_DATA
-				DDRSS2_PHY_878_DATA
-				DDRSS2_PHY_879_DATA
-				DDRSS2_PHY_880_DATA
-				DDRSS2_PHY_881_DATA
-				DDRSS2_PHY_882_DATA
-				DDRSS2_PHY_883_DATA
-				DDRSS2_PHY_884_DATA
-				DDRSS2_PHY_885_DATA
-				DDRSS2_PHY_886_DATA
-				DDRSS2_PHY_887_DATA
-				DDRSS2_PHY_888_DATA
-				DDRSS2_PHY_889_DATA
-				DDRSS2_PHY_890_DATA
-				DDRSS2_PHY_891_DATA
-				DDRSS2_PHY_892_DATA
-				DDRSS2_PHY_893_DATA
-				DDRSS2_PHY_894_DATA
-				DDRSS2_PHY_895_DATA
-				DDRSS2_PHY_896_DATA
-				DDRSS2_PHY_897_DATA
-				DDRSS2_PHY_898_DATA
-				DDRSS2_PHY_899_DATA
-				DDRSS2_PHY_900_DATA
-				DDRSS2_PHY_901_DATA
-				DDRSS2_PHY_902_DATA
-				DDRSS2_PHY_903_DATA
-				DDRSS2_PHY_904_DATA
-				DDRSS2_PHY_905_DATA
-				DDRSS2_PHY_906_DATA
-				DDRSS2_PHY_907_DATA
-				DDRSS2_PHY_908_DATA
-				DDRSS2_PHY_909_DATA
-				DDRSS2_PHY_910_DATA
-				DDRSS2_PHY_911_DATA
-				DDRSS2_PHY_912_DATA
-				DDRSS2_PHY_913_DATA
-				DDRSS2_PHY_914_DATA
-				DDRSS2_PHY_915_DATA
-				DDRSS2_PHY_916_DATA
-				DDRSS2_PHY_917_DATA
-				DDRSS2_PHY_918_DATA
-				DDRSS2_PHY_919_DATA
-				DDRSS2_PHY_920_DATA
-				DDRSS2_PHY_921_DATA
-				DDRSS2_PHY_922_DATA
-				DDRSS2_PHY_923_DATA
-				DDRSS2_PHY_924_DATA
-				DDRSS2_PHY_925_DATA
-				DDRSS2_PHY_926_DATA
-				DDRSS2_PHY_927_DATA
-				DDRSS2_PHY_928_DATA
-				DDRSS2_PHY_929_DATA
-				DDRSS2_PHY_930_DATA
-				DDRSS2_PHY_931_DATA
-				DDRSS2_PHY_932_DATA
-				DDRSS2_PHY_933_DATA
-				DDRSS2_PHY_934_DATA
-				DDRSS2_PHY_935_DATA
-				DDRSS2_PHY_936_DATA
-				DDRSS2_PHY_937_DATA
-				DDRSS2_PHY_938_DATA
-				DDRSS2_PHY_939_DATA
-				DDRSS2_PHY_940_DATA
-				DDRSS2_PHY_941_DATA
-				DDRSS2_PHY_942_DATA
-				DDRSS2_PHY_943_DATA
-				DDRSS2_PHY_944_DATA
-				DDRSS2_PHY_945_DATA
-				DDRSS2_PHY_946_DATA
-				DDRSS2_PHY_947_DATA
-				DDRSS2_PHY_948_DATA
-				DDRSS2_PHY_949_DATA
-				DDRSS2_PHY_950_DATA
-				DDRSS2_PHY_951_DATA
-				DDRSS2_PHY_952_DATA
-				DDRSS2_PHY_953_DATA
-				DDRSS2_PHY_954_DATA
-				DDRSS2_PHY_955_DATA
-				DDRSS2_PHY_956_DATA
-				DDRSS2_PHY_957_DATA
-				DDRSS2_PHY_958_DATA
-				DDRSS2_PHY_959_DATA
-				DDRSS2_PHY_960_DATA
-				DDRSS2_PHY_961_DATA
-				DDRSS2_PHY_962_DATA
-				DDRSS2_PHY_963_DATA
-				DDRSS2_PHY_964_DATA
-				DDRSS2_PHY_965_DATA
-				DDRSS2_PHY_966_DATA
-				DDRSS2_PHY_967_DATA
-				DDRSS2_PHY_968_DATA
-				DDRSS2_PHY_969_DATA
-				DDRSS2_PHY_970_DATA
-				DDRSS2_PHY_971_DATA
-				DDRSS2_PHY_972_DATA
-				DDRSS2_PHY_973_DATA
-				DDRSS2_PHY_974_DATA
-				DDRSS2_PHY_975_DATA
-				DDRSS2_PHY_976_DATA
-				DDRSS2_PHY_977_DATA
-				DDRSS2_PHY_978_DATA
-				DDRSS2_PHY_979_DATA
-				DDRSS2_PHY_980_DATA
-				DDRSS2_PHY_981_DATA
-				DDRSS2_PHY_982_DATA
-				DDRSS2_PHY_983_DATA
-				DDRSS2_PHY_984_DATA
-				DDRSS2_PHY_985_DATA
-				DDRSS2_PHY_986_DATA
-				DDRSS2_PHY_987_DATA
-				DDRSS2_PHY_988_DATA
-				DDRSS2_PHY_989_DATA
-				DDRSS2_PHY_990_DATA
-				DDRSS2_PHY_991_DATA
-				DDRSS2_PHY_992_DATA
-				DDRSS2_PHY_993_DATA
-				DDRSS2_PHY_994_DATA
-				DDRSS2_PHY_995_DATA
-				DDRSS2_PHY_996_DATA
-				DDRSS2_PHY_997_DATA
-				DDRSS2_PHY_998_DATA
-				DDRSS2_PHY_999_DATA
-				DDRSS2_PHY_1000_DATA
-				DDRSS2_PHY_1001_DATA
-				DDRSS2_PHY_1002_DATA
-				DDRSS2_PHY_1003_DATA
-				DDRSS2_PHY_1004_DATA
-				DDRSS2_PHY_1005_DATA
-				DDRSS2_PHY_1006_DATA
-				DDRSS2_PHY_1007_DATA
-				DDRSS2_PHY_1008_DATA
-				DDRSS2_PHY_1009_DATA
-				DDRSS2_PHY_1010_DATA
-				DDRSS2_PHY_1011_DATA
-				DDRSS2_PHY_1012_DATA
-				DDRSS2_PHY_1013_DATA
-				DDRSS2_PHY_1014_DATA
-				DDRSS2_PHY_1015_DATA
-				DDRSS2_PHY_1016_DATA
-				DDRSS2_PHY_1017_DATA
-				DDRSS2_PHY_1018_DATA
-				DDRSS2_PHY_1019_DATA
-				DDRSS2_PHY_1020_DATA
-				DDRSS2_PHY_1021_DATA
-				DDRSS2_PHY_1022_DATA
-				DDRSS2_PHY_1023_DATA
-				DDRSS2_PHY_1024_DATA
-				DDRSS2_PHY_1025_DATA
-				DDRSS2_PHY_1026_DATA
-				DDRSS2_PHY_1027_DATA
-				DDRSS2_PHY_1028_DATA
-				DDRSS2_PHY_1029_DATA
-				DDRSS2_PHY_1030_DATA
-				DDRSS2_PHY_1031_DATA
-				DDRSS2_PHY_1032_DATA
-				DDRSS2_PHY_1033_DATA
-				DDRSS2_PHY_1034_DATA
-				DDRSS2_PHY_1035_DATA
-				DDRSS2_PHY_1036_DATA
-				DDRSS2_PHY_1037_DATA
-				DDRSS2_PHY_1038_DATA
-				DDRSS2_PHY_1039_DATA
-				DDRSS2_PHY_1040_DATA
-				DDRSS2_PHY_1041_DATA
-				DDRSS2_PHY_1042_DATA
-				DDRSS2_PHY_1043_DATA
-				DDRSS2_PHY_1044_DATA
-				DDRSS2_PHY_1045_DATA
-				DDRSS2_PHY_1046_DATA
-				DDRSS2_PHY_1047_DATA
-				DDRSS2_PHY_1048_DATA
-				DDRSS2_PHY_1049_DATA
-				DDRSS2_PHY_1050_DATA
-				DDRSS2_PHY_1051_DATA
-				DDRSS2_PHY_1052_DATA
-				DDRSS2_PHY_1053_DATA
-				DDRSS2_PHY_1054_DATA
-				DDRSS2_PHY_1055_DATA
-				DDRSS2_PHY_1056_DATA
-				DDRSS2_PHY_1057_DATA
-				DDRSS2_PHY_1058_DATA
-				DDRSS2_PHY_1059_DATA
-				DDRSS2_PHY_1060_DATA
-				DDRSS2_PHY_1061_DATA
-				DDRSS2_PHY_1062_DATA
-				DDRSS2_PHY_1063_DATA
-				DDRSS2_PHY_1064_DATA
-				DDRSS2_PHY_1065_DATA
-				DDRSS2_PHY_1066_DATA
-				DDRSS2_PHY_1067_DATA
-				DDRSS2_PHY_1068_DATA
-				DDRSS2_PHY_1069_DATA
-				DDRSS2_PHY_1070_DATA
-				DDRSS2_PHY_1071_DATA
-				DDRSS2_PHY_1072_DATA
-				DDRSS2_PHY_1073_DATA
-				DDRSS2_PHY_1074_DATA
-				DDRSS2_PHY_1075_DATA
-				DDRSS2_PHY_1076_DATA
-				DDRSS2_PHY_1077_DATA
-				DDRSS2_PHY_1078_DATA
-				DDRSS2_PHY_1079_DATA
-				DDRSS2_PHY_1080_DATA
-				DDRSS2_PHY_1081_DATA
-				DDRSS2_PHY_1082_DATA
-				DDRSS2_PHY_1083_DATA
-				DDRSS2_PHY_1084_DATA
-				DDRSS2_PHY_1085_DATA
-				DDRSS2_PHY_1086_DATA
-				DDRSS2_PHY_1087_DATA
-				DDRSS2_PHY_1088_DATA
-				DDRSS2_PHY_1089_DATA
-				DDRSS2_PHY_1090_DATA
-				DDRSS2_PHY_1091_DATA
-				DDRSS2_PHY_1092_DATA
-				DDRSS2_PHY_1093_DATA
-				DDRSS2_PHY_1094_DATA
-				DDRSS2_PHY_1095_DATA
-				DDRSS2_PHY_1096_DATA
-				DDRSS2_PHY_1097_DATA
-				DDRSS2_PHY_1098_DATA
-				DDRSS2_PHY_1099_DATA
-				DDRSS2_PHY_1100_DATA
-				DDRSS2_PHY_1101_DATA
-				DDRSS2_PHY_1102_DATA
-				DDRSS2_PHY_1103_DATA
-				DDRSS2_PHY_1104_DATA
-				DDRSS2_PHY_1105_DATA
-				DDRSS2_PHY_1106_DATA
-				DDRSS2_PHY_1107_DATA
-				DDRSS2_PHY_1108_DATA
-				DDRSS2_PHY_1109_DATA
-				DDRSS2_PHY_1110_DATA
-				DDRSS2_PHY_1111_DATA
-				DDRSS2_PHY_1112_DATA
-				DDRSS2_PHY_1113_DATA
-				DDRSS2_PHY_1114_DATA
-				DDRSS2_PHY_1115_DATA
-				DDRSS2_PHY_1116_DATA
-				DDRSS2_PHY_1117_DATA
-				DDRSS2_PHY_1118_DATA
-				DDRSS2_PHY_1119_DATA
-				DDRSS2_PHY_1120_DATA
-				DDRSS2_PHY_1121_DATA
-				DDRSS2_PHY_1122_DATA
-				DDRSS2_PHY_1123_DATA
-				DDRSS2_PHY_1124_DATA
-				DDRSS2_PHY_1125_DATA
-				DDRSS2_PHY_1126_DATA
-				DDRSS2_PHY_1127_DATA
-				DDRSS2_PHY_1128_DATA
-				DDRSS2_PHY_1129_DATA
-				DDRSS2_PHY_1130_DATA
-				DDRSS2_PHY_1131_DATA
-				DDRSS2_PHY_1132_DATA
-				DDRSS2_PHY_1133_DATA
-				DDRSS2_PHY_1134_DATA
-				DDRSS2_PHY_1135_DATA
-				DDRSS2_PHY_1136_DATA
-				DDRSS2_PHY_1137_DATA
-				DDRSS2_PHY_1138_DATA
-				DDRSS2_PHY_1139_DATA
-				DDRSS2_PHY_1140_DATA
-				DDRSS2_PHY_1141_DATA
-				DDRSS2_PHY_1142_DATA
-				DDRSS2_PHY_1143_DATA
-				DDRSS2_PHY_1144_DATA
-				DDRSS2_PHY_1145_DATA
-				DDRSS2_PHY_1146_DATA
-				DDRSS2_PHY_1147_DATA
-				DDRSS2_PHY_1148_DATA
-				DDRSS2_PHY_1149_DATA
-				DDRSS2_PHY_1150_DATA
-				DDRSS2_PHY_1151_DATA
-				DDRSS2_PHY_1152_DATA
-				DDRSS2_PHY_1153_DATA
-				DDRSS2_PHY_1154_DATA
-				DDRSS2_PHY_1155_DATA
-				DDRSS2_PHY_1156_DATA
-				DDRSS2_PHY_1157_DATA
-				DDRSS2_PHY_1158_DATA
-				DDRSS2_PHY_1159_DATA
-				DDRSS2_PHY_1160_DATA
-				DDRSS2_PHY_1161_DATA
-				DDRSS2_PHY_1162_DATA
-				DDRSS2_PHY_1163_DATA
-				DDRSS2_PHY_1164_DATA
-				DDRSS2_PHY_1165_DATA
-				DDRSS2_PHY_1166_DATA
-				DDRSS2_PHY_1167_DATA
-				DDRSS2_PHY_1168_DATA
-				DDRSS2_PHY_1169_DATA
-				DDRSS2_PHY_1170_DATA
-				DDRSS2_PHY_1171_DATA
-				DDRSS2_PHY_1172_DATA
-				DDRSS2_PHY_1173_DATA
-				DDRSS2_PHY_1174_DATA
-				DDRSS2_PHY_1175_DATA
-				DDRSS2_PHY_1176_DATA
-				DDRSS2_PHY_1177_DATA
-				DDRSS2_PHY_1178_DATA
-				DDRSS2_PHY_1179_DATA
-				DDRSS2_PHY_1180_DATA
-				DDRSS2_PHY_1181_DATA
-				DDRSS2_PHY_1182_DATA
-				DDRSS2_PHY_1183_DATA
-				DDRSS2_PHY_1184_DATA
-				DDRSS2_PHY_1185_DATA
-				DDRSS2_PHY_1186_DATA
-				DDRSS2_PHY_1187_DATA
-				DDRSS2_PHY_1188_DATA
-				DDRSS2_PHY_1189_DATA
-				DDRSS2_PHY_1190_DATA
-				DDRSS2_PHY_1191_DATA
-				DDRSS2_PHY_1192_DATA
-				DDRSS2_PHY_1193_DATA
-				DDRSS2_PHY_1194_DATA
-				DDRSS2_PHY_1195_DATA
-				DDRSS2_PHY_1196_DATA
-				DDRSS2_PHY_1197_DATA
-				DDRSS2_PHY_1198_DATA
-				DDRSS2_PHY_1199_DATA
-				DDRSS2_PHY_1200_DATA
-				DDRSS2_PHY_1201_DATA
-				DDRSS2_PHY_1202_DATA
-				DDRSS2_PHY_1203_DATA
-				DDRSS2_PHY_1204_DATA
-				DDRSS2_PHY_1205_DATA
-				DDRSS2_PHY_1206_DATA
-				DDRSS2_PHY_1207_DATA
-				DDRSS2_PHY_1208_DATA
-				DDRSS2_PHY_1209_DATA
-				DDRSS2_PHY_1210_DATA
-				DDRSS2_PHY_1211_DATA
-				DDRSS2_PHY_1212_DATA
-				DDRSS2_PHY_1213_DATA
-				DDRSS2_PHY_1214_DATA
-				DDRSS2_PHY_1215_DATA
-				DDRSS2_PHY_1216_DATA
-				DDRSS2_PHY_1217_DATA
-				DDRSS2_PHY_1218_DATA
-				DDRSS2_PHY_1219_DATA
-				DDRSS2_PHY_1220_DATA
-				DDRSS2_PHY_1221_DATA
-				DDRSS2_PHY_1222_DATA
-				DDRSS2_PHY_1223_DATA
-				DDRSS2_PHY_1224_DATA
-				DDRSS2_PHY_1225_DATA
-				DDRSS2_PHY_1226_DATA
-				DDRSS2_PHY_1227_DATA
-				DDRSS2_PHY_1228_DATA
-				DDRSS2_PHY_1229_DATA
-				DDRSS2_PHY_1230_DATA
-				DDRSS2_PHY_1231_DATA
-				DDRSS2_PHY_1232_DATA
-				DDRSS2_PHY_1233_DATA
-				DDRSS2_PHY_1234_DATA
-				DDRSS2_PHY_1235_DATA
-				DDRSS2_PHY_1236_DATA
-				DDRSS2_PHY_1237_DATA
-				DDRSS2_PHY_1238_DATA
-				DDRSS2_PHY_1239_DATA
-				DDRSS2_PHY_1240_DATA
-				DDRSS2_PHY_1241_DATA
-				DDRSS2_PHY_1242_DATA
-				DDRSS2_PHY_1243_DATA
-				DDRSS2_PHY_1244_DATA
-				DDRSS2_PHY_1245_DATA
-				DDRSS2_PHY_1246_DATA
-				DDRSS2_PHY_1247_DATA
-				DDRSS2_PHY_1248_DATA
-				DDRSS2_PHY_1249_DATA
-				DDRSS2_PHY_1250_DATA
-				DDRSS2_PHY_1251_DATA
-				DDRSS2_PHY_1252_DATA
-				DDRSS2_PHY_1253_DATA
-				DDRSS2_PHY_1254_DATA
-				DDRSS2_PHY_1255_DATA
-				DDRSS2_PHY_1256_DATA
-				DDRSS2_PHY_1257_DATA
-				DDRSS2_PHY_1258_DATA
-				DDRSS2_PHY_1259_DATA
-				DDRSS2_PHY_1260_DATA
-				DDRSS2_PHY_1261_DATA
-				DDRSS2_PHY_1262_DATA
-				DDRSS2_PHY_1263_DATA
-				DDRSS2_PHY_1264_DATA
-				DDRSS2_PHY_1265_DATA
-				DDRSS2_PHY_1266_DATA
-				DDRSS2_PHY_1267_DATA
-				DDRSS2_PHY_1268_DATA
-				DDRSS2_PHY_1269_DATA
-				DDRSS2_PHY_1270_DATA
-				DDRSS2_PHY_1271_DATA
-				DDRSS2_PHY_1272_DATA
-				DDRSS2_PHY_1273_DATA
-				DDRSS2_PHY_1274_DATA
-				DDRSS2_PHY_1275_DATA
-				DDRSS2_PHY_1276_DATA
-				DDRSS2_PHY_1277_DATA
-				DDRSS2_PHY_1278_DATA
-				DDRSS2_PHY_1279_DATA
-				DDRSS2_PHY_1280_DATA
-				DDRSS2_PHY_1281_DATA
-				DDRSS2_PHY_1282_DATA
-				DDRSS2_PHY_1283_DATA
-				DDRSS2_PHY_1284_DATA
-				DDRSS2_PHY_1285_DATA
-				DDRSS2_PHY_1286_DATA
-				DDRSS2_PHY_1287_DATA
-				DDRSS2_PHY_1288_DATA
-				DDRSS2_PHY_1289_DATA
-				DDRSS2_PHY_1290_DATA
-				DDRSS2_PHY_1291_DATA
-				DDRSS2_PHY_1292_DATA
-				DDRSS2_PHY_1293_DATA
-				DDRSS2_PHY_1294_DATA
-				DDRSS2_PHY_1295_DATA
-				DDRSS2_PHY_1296_DATA
-				DDRSS2_PHY_1297_DATA
-				DDRSS2_PHY_1298_DATA
-				DDRSS2_PHY_1299_DATA
-				DDRSS2_PHY_1300_DATA
-				DDRSS2_PHY_1301_DATA
-				DDRSS2_PHY_1302_DATA
-				DDRSS2_PHY_1303_DATA
-				DDRSS2_PHY_1304_DATA
-				DDRSS2_PHY_1305_DATA
-				DDRSS2_PHY_1306_DATA
-				DDRSS2_PHY_1307_DATA
-				DDRSS2_PHY_1308_DATA
-				DDRSS2_PHY_1309_DATA
-				DDRSS2_PHY_1310_DATA
-				DDRSS2_PHY_1311_DATA
-				DDRSS2_PHY_1312_DATA
-				DDRSS2_PHY_1313_DATA
-				DDRSS2_PHY_1314_DATA
-				DDRSS2_PHY_1315_DATA
-				DDRSS2_PHY_1316_DATA
-				DDRSS2_PHY_1317_DATA
-				DDRSS2_PHY_1318_DATA
-				DDRSS2_PHY_1319_DATA
-				DDRSS2_PHY_1320_DATA
-				DDRSS2_PHY_1321_DATA
-				DDRSS2_PHY_1322_DATA
-				DDRSS2_PHY_1323_DATA
-				DDRSS2_PHY_1324_DATA
-				DDRSS2_PHY_1325_DATA
-				DDRSS2_PHY_1326_DATA
-				DDRSS2_PHY_1327_DATA
-				DDRSS2_PHY_1328_DATA
-				DDRSS2_PHY_1329_DATA
-				DDRSS2_PHY_1330_DATA
-				DDRSS2_PHY_1331_DATA
-				DDRSS2_PHY_1332_DATA
-				DDRSS2_PHY_1333_DATA
-				DDRSS2_PHY_1334_DATA
-				DDRSS2_PHY_1335_DATA
-				DDRSS2_PHY_1336_DATA
-				DDRSS2_PHY_1337_DATA
-				DDRSS2_PHY_1338_DATA
-				DDRSS2_PHY_1339_DATA
-				DDRSS2_PHY_1340_DATA
-				DDRSS2_PHY_1341_DATA
-				DDRSS2_PHY_1342_DATA
-				DDRSS2_PHY_1343_DATA
-				DDRSS2_PHY_1344_DATA
-				DDRSS2_PHY_1345_DATA
-				DDRSS2_PHY_1346_DATA
-				DDRSS2_PHY_1347_DATA
-				DDRSS2_PHY_1348_DATA
-				DDRSS2_PHY_1349_DATA
-				DDRSS2_PHY_1350_DATA
-				DDRSS2_PHY_1351_DATA
-				DDRSS2_PHY_1352_DATA
-				DDRSS2_PHY_1353_DATA
-				DDRSS2_PHY_1354_DATA
-				DDRSS2_PHY_1355_DATA
-				DDRSS2_PHY_1356_DATA
-				DDRSS2_PHY_1357_DATA
-				DDRSS2_PHY_1358_DATA
-				DDRSS2_PHY_1359_DATA
-				DDRSS2_PHY_1360_DATA
-				DDRSS2_PHY_1361_DATA
-				DDRSS2_PHY_1362_DATA
-				DDRSS2_PHY_1363_DATA
-				DDRSS2_PHY_1364_DATA
-				DDRSS2_PHY_1365_DATA
-				DDRSS2_PHY_1366_DATA
-				DDRSS2_PHY_1367_DATA
-				DDRSS2_PHY_1368_DATA
-				DDRSS2_PHY_1369_DATA
-				DDRSS2_PHY_1370_DATA
-				DDRSS2_PHY_1371_DATA
-				DDRSS2_PHY_1372_DATA
-				DDRSS2_PHY_1373_DATA
-				DDRSS2_PHY_1374_DATA
-				DDRSS2_PHY_1375_DATA
-				DDRSS2_PHY_1376_DATA
-				DDRSS2_PHY_1377_DATA
-				DDRSS2_PHY_1378_DATA
-				DDRSS2_PHY_1379_DATA
-				DDRSS2_PHY_1380_DATA
-				DDRSS2_PHY_1381_DATA
-				DDRSS2_PHY_1382_DATA
-				DDRSS2_PHY_1383_DATA
-				DDRSS2_PHY_1384_DATA
-				DDRSS2_PHY_1385_DATA
-				DDRSS2_PHY_1386_DATA
-				DDRSS2_PHY_1387_DATA
-				DDRSS2_PHY_1388_DATA
-				DDRSS2_PHY_1389_DATA
-				DDRSS2_PHY_1390_DATA
-				DDRSS2_PHY_1391_DATA
-				DDRSS2_PHY_1392_DATA
-				DDRSS2_PHY_1393_DATA
-				DDRSS2_PHY_1394_DATA
-				DDRSS2_PHY_1395_DATA
-				DDRSS2_PHY_1396_DATA
-				DDRSS2_PHY_1397_DATA
-				DDRSS2_PHY_1398_DATA
-				DDRSS2_PHY_1399_DATA
-				DDRSS2_PHY_1400_DATA
-				DDRSS2_PHY_1401_DATA
-				DDRSS2_PHY_1402_DATA
-				DDRSS2_PHY_1403_DATA
-				DDRSS2_PHY_1404_DATA
-				DDRSS2_PHY_1405_DATA
-				DDRSS2_PHY_1406_DATA
-				DDRSS2_PHY_1407_DATA
-				DDRSS2_PHY_1408_DATA
-				DDRSS2_PHY_1409_DATA
-				DDRSS2_PHY_1410_DATA
-				DDRSS2_PHY_1411_DATA
-				DDRSS2_PHY_1412_DATA
-				DDRSS2_PHY_1413_DATA
-				DDRSS2_PHY_1414_DATA
-				DDRSS2_PHY_1415_DATA
-				DDRSS2_PHY_1416_DATA
-				DDRSS2_PHY_1417_DATA
-				DDRSS2_PHY_1418_DATA
-				DDRSS2_PHY_1419_DATA
-				DDRSS2_PHY_1420_DATA
-				DDRSS2_PHY_1421_DATA
-				DDRSS2_PHY_1422_DATA
-			>;
-		};
+		ti,phy-data = <
+			DDRSS2_PHY_00_DATA
+			DDRSS2_PHY_01_DATA
+			DDRSS2_PHY_02_DATA
+			DDRSS2_PHY_03_DATA
+			DDRSS2_PHY_04_DATA
+			DDRSS2_PHY_05_DATA
+			DDRSS2_PHY_06_DATA
+			DDRSS2_PHY_07_DATA
+			DDRSS2_PHY_08_DATA
+			DDRSS2_PHY_09_DATA
+			DDRSS2_PHY_10_DATA
+			DDRSS2_PHY_11_DATA
+			DDRSS2_PHY_12_DATA
+			DDRSS2_PHY_13_DATA
+			DDRSS2_PHY_14_DATA
+			DDRSS2_PHY_15_DATA
+			DDRSS2_PHY_16_DATA
+			DDRSS2_PHY_17_DATA
+			DDRSS2_PHY_18_DATA
+			DDRSS2_PHY_19_DATA
+			DDRSS2_PHY_20_DATA
+			DDRSS2_PHY_21_DATA
+			DDRSS2_PHY_22_DATA
+			DDRSS2_PHY_23_DATA
+			DDRSS2_PHY_24_DATA
+			DDRSS2_PHY_25_DATA
+			DDRSS2_PHY_26_DATA
+			DDRSS2_PHY_27_DATA
+			DDRSS2_PHY_28_DATA
+			DDRSS2_PHY_29_DATA
+			DDRSS2_PHY_30_DATA
+			DDRSS2_PHY_31_DATA
+			DDRSS2_PHY_32_DATA
+			DDRSS2_PHY_33_DATA
+			DDRSS2_PHY_34_DATA
+			DDRSS2_PHY_35_DATA
+			DDRSS2_PHY_36_DATA
+			DDRSS2_PHY_37_DATA
+			DDRSS2_PHY_38_DATA
+			DDRSS2_PHY_39_DATA
+			DDRSS2_PHY_40_DATA
+			DDRSS2_PHY_41_DATA
+			DDRSS2_PHY_42_DATA
+			DDRSS2_PHY_43_DATA
+			DDRSS2_PHY_44_DATA
+			DDRSS2_PHY_45_DATA
+			DDRSS2_PHY_46_DATA
+			DDRSS2_PHY_47_DATA
+			DDRSS2_PHY_48_DATA
+			DDRSS2_PHY_49_DATA
+			DDRSS2_PHY_50_DATA
+			DDRSS2_PHY_51_DATA
+			DDRSS2_PHY_52_DATA
+			DDRSS2_PHY_53_DATA
+			DDRSS2_PHY_54_DATA
+			DDRSS2_PHY_55_DATA
+			DDRSS2_PHY_56_DATA
+			DDRSS2_PHY_57_DATA
+			DDRSS2_PHY_58_DATA
+			DDRSS2_PHY_59_DATA
+			DDRSS2_PHY_60_DATA
+			DDRSS2_PHY_61_DATA
+			DDRSS2_PHY_62_DATA
+			DDRSS2_PHY_63_DATA
+			DDRSS2_PHY_64_DATA
+			DDRSS2_PHY_65_DATA
+			DDRSS2_PHY_66_DATA
+			DDRSS2_PHY_67_DATA
+			DDRSS2_PHY_68_DATA
+			DDRSS2_PHY_69_DATA
+			DDRSS2_PHY_70_DATA
+			DDRSS2_PHY_71_DATA
+			DDRSS2_PHY_72_DATA
+			DDRSS2_PHY_73_DATA
+			DDRSS2_PHY_74_DATA
+			DDRSS2_PHY_75_DATA
+			DDRSS2_PHY_76_DATA
+			DDRSS2_PHY_77_DATA
+			DDRSS2_PHY_78_DATA
+			DDRSS2_PHY_79_DATA
+			DDRSS2_PHY_80_DATA
+			DDRSS2_PHY_81_DATA
+			DDRSS2_PHY_82_DATA
+			DDRSS2_PHY_83_DATA
+			DDRSS2_PHY_84_DATA
+			DDRSS2_PHY_85_DATA
+			DDRSS2_PHY_86_DATA
+			DDRSS2_PHY_87_DATA
+			DDRSS2_PHY_88_DATA
+			DDRSS2_PHY_89_DATA
+			DDRSS2_PHY_90_DATA
+			DDRSS2_PHY_91_DATA
+			DDRSS2_PHY_92_DATA
+			DDRSS2_PHY_93_DATA
+			DDRSS2_PHY_94_DATA
+			DDRSS2_PHY_95_DATA
+			DDRSS2_PHY_96_DATA
+			DDRSS2_PHY_97_DATA
+			DDRSS2_PHY_98_DATA
+			DDRSS2_PHY_99_DATA
+			DDRSS2_PHY_100_DATA
+			DDRSS2_PHY_101_DATA
+			DDRSS2_PHY_102_DATA
+			DDRSS2_PHY_103_DATA
+			DDRSS2_PHY_104_DATA
+			DDRSS2_PHY_105_DATA
+			DDRSS2_PHY_106_DATA
+			DDRSS2_PHY_107_DATA
+			DDRSS2_PHY_108_DATA
+			DDRSS2_PHY_109_DATA
+			DDRSS2_PHY_110_DATA
+			DDRSS2_PHY_111_DATA
+			DDRSS2_PHY_112_DATA
+			DDRSS2_PHY_113_DATA
+			DDRSS2_PHY_114_DATA
+			DDRSS2_PHY_115_DATA
+			DDRSS2_PHY_116_DATA
+			DDRSS2_PHY_117_DATA
+			DDRSS2_PHY_118_DATA
+			DDRSS2_PHY_119_DATA
+			DDRSS2_PHY_120_DATA
+			DDRSS2_PHY_121_DATA
+			DDRSS2_PHY_122_DATA
+			DDRSS2_PHY_123_DATA
+			DDRSS2_PHY_124_DATA
+			DDRSS2_PHY_125_DATA
+			DDRSS2_PHY_126_DATA
+			DDRSS2_PHY_127_DATA
+			DDRSS2_PHY_128_DATA
+			DDRSS2_PHY_129_DATA
+			DDRSS2_PHY_130_DATA
+			DDRSS2_PHY_131_DATA
+			DDRSS2_PHY_132_DATA
+			DDRSS2_PHY_133_DATA
+			DDRSS2_PHY_134_DATA
+			DDRSS2_PHY_135_DATA
+			DDRSS2_PHY_136_DATA
+			DDRSS2_PHY_137_DATA
+			DDRSS2_PHY_138_DATA
+			DDRSS2_PHY_139_DATA
+			DDRSS2_PHY_140_DATA
+			DDRSS2_PHY_141_DATA
+			DDRSS2_PHY_142_DATA
+			DDRSS2_PHY_143_DATA
+			DDRSS2_PHY_144_DATA
+			DDRSS2_PHY_145_DATA
+			DDRSS2_PHY_146_DATA
+			DDRSS2_PHY_147_DATA
+			DDRSS2_PHY_148_DATA
+			DDRSS2_PHY_149_DATA
+			DDRSS2_PHY_150_DATA
+			DDRSS2_PHY_151_DATA
+			DDRSS2_PHY_152_DATA
+			DDRSS2_PHY_153_DATA
+			DDRSS2_PHY_154_DATA
+			DDRSS2_PHY_155_DATA
+			DDRSS2_PHY_156_DATA
+			DDRSS2_PHY_157_DATA
+			DDRSS2_PHY_158_DATA
+			DDRSS2_PHY_159_DATA
+			DDRSS2_PHY_160_DATA
+			DDRSS2_PHY_161_DATA
+			DDRSS2_PHY_162_DATA
+			DDRSS2_PHY_163_DATA
+			DDRSS2_PHY_164_DATA
+			DDRSS2_PHY_165_DATA
+			DDRSS2_PHY_166_DATA
+			DDRSS2_PHY_167_DATA
+			DDRSS2_PHY_168_DATA
+			DDRSS2_PHY_169_DATA
+			DDRSS2_PHY_170_DATA
+			DDRSS2_PHY_171_DATA
+			DDRSS2_PHY_172_DATA
+			DDRSS2_PHY_173_DATA
+			DDRSS2_PHY_174_DATA
+			DDRSS2_PHY_175_DATA
+			DDRSS2_PHY_176_DATA
+			DDRSS2_PHY_177_DATA
+			DDRSS2_PHY_178_DATA
+			DDRSS2_PHY_179_DATA
+			DDRSS2_PHY_180_DATA
+			DDRSS2_PHY_181_DATA
+			DDRSS2_PHY_182_DATA
+			DDRSS2_PHY_183_DATA
+			DDRSS2_PHY_184_DATA
+			DDRSS2_PHY_185_DATA
+			DDRSS2_PHY_186_DATA
+			DDRSS2_PHY_187_DATA
+			DDRSS2_PHY_188_DATA
+			DDRSS2_PHY_189_DATA
+			DDRSS2_PHY_190_DATA
+			DDRSS2_PHY_191_DATA
+			DDRSS2_PHY_192_DATA
+			DDRSS2_PHY_193_DATA
+			DDRSS2_PHY_194_DATA
+			DDRSS2_PHY_195_DATA
+			DDRSS2_PHY_196_DATA
+			DDRSS2_PHY_197_DATA
+			DDRSS2_PHY_198_DATA
+			DDRSS2_PHY_199_DATA
+			DDRSS2_PHY_200_DATA
+			DDRSS2_PHY_201_DATA
+			DDRSS2_PHY_202_DATA
+			DDRSS2_PHY_203_DATA
+			DDRSS2_PHY_204_DATA
+			DDRSS2_PHY_205_DATA
+			DDRSS2_PHY_206_DATA
+			DDRSS2_PHY_207_DATA
+			DDRSS2_PHY_208_DATA
+			DDRSS2_PHY_209_DATA
+			DDRSS2_PHY_210_DATA
+			DDRSS2_PHY_211_DATA
+			DDRSS2_PHY_212_DATA
+			DDRSS2_PHY_213_DATA
+			DDRSS2_PHY_214_DATA
+			DDRSS2_PHY_215_DATA
+			DDRSS2_PHY_216_DATA
+			DDRSS2_PHY_217_DATA
+			DDRSS2_PHY_218_DATA
+			DDRSS2_PHY_219_DATA
+			DDRSS2_PHY_220_DATA
+			DDRSS2_PHY_221_DATA
+			DDRSS2_PHY_222_DATA
+			DDRSS2_PHY_223_DATA
+			DDRSS2_PHY_224_DATA
+			DDRSS2_PHY_225_DATA
+			DDRSS2_PHY_226_DATA
+			DDRSS2_PHY_227_DATA
+			DDRSS2_PHY_228_DATA
+			DDRSS2_PHY_229_DATA
+			DDRSS2_PHY_230_DATA
+			DDRSS2_PHY_231_DATA
+			DDRSS2_PHY_232_DATA
+			DDRSS2_PHY_233_DATA
+			DDRSS2_PHY_234_DATA
+			DDRSS2_PHY_235_DATA
+			DDRSS2_PHY_236_DATA
+			DDRSS2_PHY_237_DATA
+			DDRSS2_PHY_238_DATA
+			DDRSS2_PHY_239_DATA
+			DDRSS2_PHY_240_DATA
+			DDRSS2_PHY_241_DATA
+			DDRSS2_PHY_242_DATA
+			DDRSS2_PHY_243_DATA
+			DDRSS2_PHY_244_DATA
+			DDRSS2_PHY_245_DATA
+			DDRSS2_PHY_246_DATA
+			DDRSS2_PHY_247_DATA
+			DDRSS2_PHY_248_DATA
+			DDRSS2_PHY_249_DATA
+			DDRSS2_PHY_250_DATA
+			DDRSS2_PHY_251_DATA
+			DDRSS2_PHY_252_DATA
+			DDRSS2_PHY_253_DATA
+			DDRSS2_PHY_254_DATA
+			DDRSS2_PHY_255_DATA
+			DDRSS2_PHY_256_DATA
+			DDRSS2_PHY_257_DATA
+			DDRSS2_PHY_258_DATA
+			DDRSS2_PHY_259_DATA
+			DDRSS2_PHY_260_DATA
+			DDRSS2_PHY_261_DATA
+			DDRSS2_PHY_262_DATA
+			DDRSS2_PHY_263_DATA
+			DDRSS2_PHY_264_DATA
+			DDRSS2_PHY_265_DATA
+			DDRSS2_PHY_266_DATA
+			DDRSS2_PHY_267_DATA
+			DDRSS2_PHY_268_DATA
+			DDRSS2_PHY_269_DATA
+			DDRSS2_PHY_270_DATA
+			DDRSS2_PHY_271_DATA
+			DDRSS2_PHY_272_DATA
+			DDRSS2_PHY_273_DATA
+			DDRSS2_PHY_274_DATA
+			DDRSS2_PHY_275_DATA
+			DDRSS2_PHY_276_DATA
+			DDRSS2_PHY_277_DATA
+			DDRSS2_PHY_278_DATA
+			DDRSS2_PHY_279_DATA
+			DDRSS2_PHY_280_DATA
+			DDRSS2_PHY_281_DATA
+			DDRSS2_PHY_282_DATA
+			DDRSS2_PHY_283_DATA
+			DDRSS2_PHY_284_DATA
+			DDRSS2_PHY_285_DATA
+			DDRSS2_PHY_286_DATA
+			DDRSS2_PHY_287_DATA
+			DDRSS2_PHY_288_DATA
+			DDRSS2_PHY_289_DATA
+			DDRSS2_PHY_290_DATA
+			DDRSS2_PHY_291_DATA
+			DDRSS2_PHY_292_DATA
+			DDRSS2_PHY_293_DATA
+			DDRSS2_PHY_294_DATA
+			DDRSS2_PHY_295_DATA
+			DDRSS2_PHY_296_DATA
+			DDRSS2_PHY_297_DATA
+			DDRSS2_PHY_298_DATA
+			DDRSS2_PHY_299_DATA
+			DDRSS2_PHY_300_DATA
+			DDRSS2_PHY_301_DATA
+			DDRSS2_PHY_302_DATA
+			DDRSS2_PHY_303_DATA
+			DDRSS2_PHY_304_DATA
+			DDRSS2_PHY_305_DATA
+			DDRSS2_PHY_306_DATA
+			DDRSS2_PHY_307_DATA
+			DDRSS2_PHY_308_DATA
+			DDRSS2_PHY_309_DATA
+			DDRSS2_PHY_310_DATA
+			DDRSS2_PHY_311_DATA
+			DDRSS2_PHY_312_DATA
+			DDRSS2_PHY_313_DATA
+			DDRSS2_PHY_314_DATA
+			DDRSS2_PHY_315_DATA
+			DDRSS2_PHY_316_DATA
+			DDRSS2_PHY_317_DATA
+			DDRSS2_PHY_318_DATA
+			DDRSS2_PHY_319_DATA
+			DDRSS2_PHY_320_DATA
+			DDRSS2_PHY_321_DATA
+			DDRSS2_PHY_322_DATA
+			DDRSS2_PHY_323_DATA
+			DDRSS2_PHY_324_DATA
+			DDRSS2_PHY_325_DATA
+			DDRSS2_PHY_326_DATA
+			DDRSS2_PHY_327_DATA
+			DDRSS2_PHY_328_DATA
+			DDRSS2_PHY_329_DATA
+			DDRSS2_PHY_330_DATA
+			DDRSS2_PHY_331_DATA
+			DDRSS2_PHY_332_DATA
+			DDRSS2_PHY_333_DATA
+			DDRSS2_PHY_334_DATA
+			DDRSS2_PHY_335_DATA
+			DDRSS2_PHY_336_DATA
+			DDRSS2_PHY_337_DATA
+			DDRSS2_PHY_338_DATA
+			DDRSS2_PHY_339_DATA
+			DDRSS2_PHY_340_DATA
+			DDRSS2_PHY_341_DATA
+			DDRSS2_PHY_342_DATA
+			DDRSS2_PHY_343_DATA
+			DDRSS2_PHY_344_DATA
+			DDRSS2_PHY_345_DATA
+			DDRSS2_PHY_346_DATA
+			DDRSS2_PHY_347_DATA
+			DDRSS2_PHY_348_DATA
+			DDRSS2_PHY_349_DATA
+			DDRSS2_PHY_350_DATA
+			DDRSS2_PHY_351_DATA
+			DDRSS2_PHY_352_DATA
+			DDRSS2_PHY_353_DATA
+			DDRSS2_PHY_354_DATA
+			DDRSS2_PHY_355_DATA
+			DDRSS2_PHY_356_DATA
+			DDRSS2_PHY_357_DATA
+			DDRSS2_PHY_358_DATA
+			DDRSS2_PHY_359_DATA
+			DDRSS2_PHY_360_DATA
+			DDRSS2_PHY_361_DATA
+			DDRSS2_PHY_362_DATA
+			DDRSS2_PHY_363_DATA
+			DDRSS2_PHY_364_DATA
+			DDRSS2_PHY_365_DATA
+			DDRSS2_PHY_366_DATA
+			DDRSS2_PHY_367_DATA
+			DDRSS2_PHY_368_DATA
+			DDRSS2_PHY_369_DATA
+			DDRSS2_PHY_370_DATA
+			DDRSS2_PHY_371_DATA
+			DDRSS2_PHY_372_DATA
+			DDRSS2_PHY_373_DATA
+			DDRSS2_PHY_374_DATA
+			DDRSS2_PHY_375_DATA
+			DDRSS2_PHY_376_DATA
+			DDRSS2_PHY_377_DATA
+			DDRSS2_PHY_378_DATA
+			DDRSS2_PHY_379_DATA
+			DDRSS2_PHY_380_DATA
+			DDRSS2_PHY_381_DATA
+			DDRSS2_PHY_382_DATA
+			DDRSS2_PHY_383_DATA
+			DDRSS2_PHY_384_DATA
+			DDRSS2_PHY_385_DATA
+			DDRSS2_PHY_386_DATA
+			DDRSS2_PHY_387_DATA
+			DDRSS2_PHY_388_DATA
+			DDRSS2_PHY_389_DATA
+			DDRSS2_PHY_390_DATA
+			DDRSS2_PHY_391_DATA
+			DDRSS2_PHY_392_DATA
+			DDRSS2_PHY_393_DATA
+			DDRSS2_PHY_394_DATA
+			DDRSS2_PHY_395_DATA
+			DDRSS2_PHY_396_DATA
+			DDRSS2_PHY_397_DATA
+			DDRSS2_PHY_398_DATA
+			DDRSS2_PHY_399_DATA
+			DDRSS2_PHY_400_DATA
+			DDRSS2_PHY_401_DATA
+			DDRSS2_PHY_402_DATA
+			DDRSS2_PHY_403_DATA
+			DDRSS2_PHY_404_DATA
+			DDRSS2_PHY_405_DATA
+			DDRSS2_PHY_406_DATA
+			DDRSS2_PHY_407_DATA
+			DDRSS2_PHY_408_DATA
+			DDRSS2_PHY_409_DATA
+			DDRSS2_PHY_410_DATA
+			DDRSS2_PHY_411_DATA
+			DDRSS2_PHY_412_DATA
+			DDRSS2_PHY_413_DATA
+			DDRSS2_PHY_414_DATA
+			DDRSS2_PHY_415_DATA
+			DDRSS2_PHY_416_DATA
+			DDRSS2_PHY_417_DATA
+			DDRSS2_PHY_418_DATA
+			DDRSS2_PHY_419_DATA
+			DDRSS2_PHY_420_DATA
+			DDRSS2_PHY_421_DATA
+			DDRSS2_PHY_422_DATA
+			DDRSS2_PHY_423_DATA
+			DDRSS2_PHY_424_DATA
+			DDRSS2_PHY_425_DATA
+			DDRSS2_PHY_426_DATA
+			DDRSS2_PHY_427_DATA
+			DDRSS2_PHY_428_DATA
+			DDRSS2_PHY_429_DATA
+			DDRSS2_PHY_430_DATA
+			DDRSS2_PHY_431_DATA
+			DDRSS2_PHY_432_DATA
+			DDRSS2_PHY_433_DATA
+			DDRSS2_PHY_434_DATA
+			DDRSS2_PHY_435_DATA
+			DDRSS2_PHY_436_DATA
+			DDRSS2_PHY_437_DATA
+			DDRSS2_PHY_438_DATA
+			DDRSS2_PHY_439_DATA
+			DDRSS2_PHY_440_DATA
+			DDRSS2_PHY_441_DATA
+			DDRSS2_PHY_442_DATA
+			DDRSS2_PHY_443_DATA
+			DDRSS2_PHY_444_DATA
+			DDRSS2_PHY_445_DATA
+			DDRSS2_PHY_446_DATA
+			DDRSS2_PHY_447_DATA
+			DDRSS2_PHY_448_DATA
+			DDRSS2_PHY_449_DATA
+			DDRSS2_PHY_450_DATA
+			DDRSS2_PHY_451_DATA
+			DDRSS2_PHY_452_DATA
+			DDRSS2_PHY_453_DATA
+			DDRSS2_PHY_454_DATA
+			DDRSS2_PHY_455_DATA
+			DDRSS2_PHY_456_DATA
+			DDRSS2_PHY_457_DATA
+			DDRSS2_PHY_458_DATA
+			DDRSS2_PHY_459_DATA
+			DDRSS2_PHY_460_DATA
+			DDRSS2_PHY_461_DATA
+			DDRSS2_PHY_462_DATA
+			DDRSS2_PHY_463_DATA
+			DDRSS2_PHY_464_DATA
+			DDRSS2_PHY_465_DATA
+			DDRSS2_PHY_466_DATA
+			DDRSS2_PHY_467_DATA
+			DDRSS2_PHY_468_DATA
+			DDRSS2_PHY_469_DATA
+			DDRSS2_PHY_470_DATA
+			DDRSS2_PHY_471_DATA
+			DDRSS2_PHY_472_DATA
+			DDRSS2_PHY_473_DATA
+			DDRSS2_PHY_474_DATA
+			DDRSS2_PHY_475_DATA
+			DDRSS2_PHY_476_DATA
+			DDRSS2_PHY_477_DATA
+			DDRSS2_PHY_478_DATA
+			DDRSS2_PHY_479_DATA
+			DDRSS2_PHY_480_DATA
+			DDRSS2_PHY_481_DATA
+			DDRSS2_PHY_482_DATA
+			DDRSS2_PHY_483_DATA
+			DDRSS2_PHY_484_DATA
+			DDRSS2_PHY_485_DATA
+			DDRSS2_PHY_486_DATA
+			DDRSS2_PHY_487_DATA
+			DDRSS2_PHY_488_DATA
+			DDRSS2_PHY_489_DATA
+			DDRSS2_PHY_490_DATA
+			DDRSS2_PHY_491_DATA
+			DDRSS2_PHY_492_DATA
+			DDRSS2_PHY_493_DATA
+			DDRSS2_PHY_494_DATA
+			DDRSS2_PHY_495_DATA
+			DDRSS2_PHY_496_DATA
+			DDRSS2_PHY_497_DATA
+			DDRSS2_PHY_498_DATA
+			DDRSS2_PHY_499_DATA
+			DDRSS2_PHY_500_DATA
+			DDRSS2_PHY_501_DATA
+			DDRSS2_PHY_502_DATA
+			DDRSS2_PHY_503_DATA
+			DDRSS2_PHY_504_DATA
+			DDRSS2_PHY_505_DATA
+			DDRSS2_PHY_506_DATA
+			DDRSS2_PHY_507_DATA
+			DDRSS2_PHY_508_DATA
+			DDRSS2_PHY_509_DATA
+			DDRSS2_PHY_510_DATA
+			DDRSS2_PHY_511_DATA
+			DDRSS2_PHY_512_DATA
+			DDRSS2_PHY_513_DATA
+			DDRSS2_PHY_514_DATA
+			DDRSS2_PHY_515_DATA
+			DDRSS2_PHY_516_DATA
+			DDRSS2_PHY_517_DATA
+			DDRSS2_PHY_518_DATA
+			DDRSS2_PHY_519_DATA
+			DDRSS2_PHY_520_DATA
+			DDRSS2_PHY_521_DATA
+			DDRSS2_PHY_522_DATA
+			DDRSS2_PHY_523_DATA
+			DDRSS2_PHY_524_DATA
+			DDRSS2_PHY_525_DATA
+			DDRSS2_PHY_526_DATA
+			DDRSS2_PHY_527_DATA
+			DDRSS2_PHY_528_DATA
+			DDRSS2_PHY_529_DATA
+			DDRSS2_PHY_530_DATA
+			DDRSS2_PHY_531_DATA
+			DDRSS2_PHY_532_DATA
+			DDRSS2_PHY_533_DATA
+			DDRSS2_PHY_534_DATA
+			DDRSS2_PHY_535_DATA
+			DDRSS2_PHY_536_DATA
+			DDRSS2_PHY_537_DATA
+			DDRSS2_PHY_538_DATA
+			DDRSS2_PHY_539_DATA
+			DDRSS2_PHY_540_DATA
+			DDRSS2_PHY_541_DATA
+			DDRSS2_PHY_542_DATA
+			DDRSS2_PHY_543_DATA
+			DDRSS2_PHY_544_DATA
+			DDRSS2_PHY_545_DATA
+			DDRSS2_PHY_546_DATA
+			DDRSS2_PHY_547_DATA
+			DDRSS2_PHY_548_DATA
+			DDRSS2_PHY_549_DATA
+			DDRSS2_PHY_550_DATA
+			DDRSS2_PHY_551_DATA
+			DDRSS2_PHY_552_DATA
+			DDRSS2_PHY_553_DATA
+			DDRSS2_PHY_554_DATA
+			DDRSS2_PHY_555_DATA
+			DDRSS2_PHY_556_DATA
+			DDRSS2_PHY_557_DATA
+			DDRSS2_PHY_558_DATA
+			DDRSS2_PHY_559_DATA
+			DDRSS2_PHY_560_DATA
+			DDRSS2_PHY_561_DATA
+			DDRSS2_PHY_562_DATA
+			DDRSS2_PHY_563_DATA
+			DDRSS2_PHY_564_DATA
+			DDRSS2_PHY_565_DATA
+			DDRSS2_PHY_566_DATA
+			DDRSS2_PHY_567_DATA
+			DDRSS2_PHY_568_DATA
+			DDRSS2_PHY_569_DATA
+			DDRSS2_PHY_570_DATA
+			DDRSS2_PHY_571_DATA
+			DDRSS2_PHY_572_DATA
+			DDRSS2_PHY_573_DATA
+			DDRSS2_PHY_574_DATA
+			DDRSS2_PHY_575_DATA
+			DDRSS2_PHY_576_DATA
+			DDRSS2_PHY_577_DATA
+			DDRSS2_PHY_578_DATA
+			DDRSS2_PHY_579_DATA
+			DDRSS2_PHY_580_DATA
+			DDRSS2_PHY_581_DATA
+			DDRSS2_PHY_582_DATA
+			DDRSS2_PHY_583_DATA
+			DDRSS2_PHY_584_DATA
+			DDRSS2_PHY_585_DATA
+			DDRSS2_PHY_586_DATA
+			DDRSS2_PHY_587_DATA
+			DDRSS2_PHY_588_DATA
+			DDRSS2_PHY_589_DATA
+			DDRSS2_PHY_590_DATA
+			DDRSS2_PHY_591_DATA
+			DDRSS2_PHY_592_DATA
+			DDRSS2_PHY_593_DATA
+			DDRSS2_PHY_594_DATA
+			DDRSS2_PHY_595_DATA
+			DDRSS2_PHY_596_DATA
+			DDRSS2_PHY_597_DATA
+			DDRSS2_PHY_598_DATA
+			DDRSS2_PHY_599_DATA
+			DDRSS2_PHY_600_DATA
+			DDRSS2_PHY_601_DATA
+			DDRSS2_PHY_602_DATA
+			DDRSS2_PHY_603_DATA
+			DDRSS2_PHY_604_DATA
+			DDRSS2_PHY_605_DATA
+			DDRSS2_PHY_606_DATA
+			DDRSS2_PHY_607_DATA
+			DDRSS2_PHY_608_DATA
+			DDRSS2_PHY_609_DATA
+			DDRSS2_PHY_610_DATA
+			DDRSS2_PHY_611_DATA
+			DDRSS2_PHY_612_DATA
+			DDRSS2_PHY_613_DATA
+			DDRSS2_PHY_614_DATA
+			DDRSS2_PHY_615_DATA
+			DDRSS2_PHY_616_DATA
+			DDRSS2_PHY_617_DATA
+			DDRSS2_PHY_618_DATA
+			DDRSS2_PHY_619_DATA
+			DDRSS2_PHY_620_DATA
+			DDRSS2_PHY_621_DATA
+			DDRSS2_PHY_622_DATA
+			DDRSS2_PHY_623_DATA
+			DDRSS2_PHY_624_DATA
+			DDRSS2_PHY_625_DATA
+			DDRSS2_PHY_626_DATA
+			DDRSS2_PHY_627_DATA
+			DDRSS2_PHY_628_DATA
+			DDRSS2_PHY_629_DATA
+			DDRSS2_PHY_630_DATA
+			DDRSS2_PHY_631_DATA
+			DDRSS2_PHY_632_DATA
+			DDRSS2_PHY_633_DATA
+			DDRSS2_PHY_634_DATA
+			DDRSS2_PHY_635_DATA
+			DDRSS2_PHY_636_DATA
+			DDRSS2_PHY_637_DATA
+			DDRSS2_PHY_638_DATA
+			DDRSS2_PHY_639_DATA
+			DDRSS2_PHY_640_DATA
+			DDRSS2_PHY_641_DATA
+			DDRSS2_PHY_642_DATA
+			DDRSS2_PHY_643_DATA
+			DDRSS2_PHY_644_DATA
+			DDRSS2_PHY_645_DATA
+			DDRSS2_PHY_646_DATA
+			DDRSS2_PHY_647_DATA
+			DDRSS2_PHY_648_DATA
+			DDRSS2_PHY_649_DATA
+			DDRSS2_PHY_650_DATA
+			DDRSS2_PHY_651_DATA
+			DDRSS2_PHY_652_DATA
+			DDRSS2_PHY_653_DATA
+			DDRSS2_PHY_654_DATA
+			DDRSS2_PHY_655_DATA
+			DDRSS2_PHY_656_DATA
+			DDRSS2_PHY_657_DATA
+			DDRSS2_PHY_658_DATA
+			DDRSS2_PHY_659_DATA
+			DDRSS2_PHY_660_DATA
+			DDRSS2_PHY_661_DATA
+			DDRSS2_PHY_662_DATA
+			DDRSS2_PHY_663_DATA
+			DDRSS2_PHY_664_DATA
+			DDRSS2_PHY_665_DATA
+			DDRSS2_PHY_666_DATA
+			DDRSS2_PHY_667_DATA
+			DDRSS2_PHY_668_DATA
+			DDRSS2_PHY_669_DATA
+			DDRSS2_PHY_670_DATA
+			DDRSS2_PHY_671_DATA
+			DDRSS2_PHY_672_DATA
+			DDRSS2_PHY_673_DATA
+			DDRSS2_PHY_674_DATA
+			DDRSS2_PHY_675_DATA
+			DDRSS2_PHY_676_DATA
+			DDRSS2_PHY_677_DATA
+			DDRSS2_PHY_678_DATA
+			DDRSS2_PHY_679_DATA
+			DDRSS2_PHY_680_DATA
+			DDRSS2_PHY_681_DATA
+			DDRSS2_PHY_682_DATA
+			DDRSS2_PHY_683_DATA
+			DDRSS2_PHY_684_DATA
+			DDRSS2_PHY_685_DATA
+			DDRSS2_PHY_686_DATA
+			DDRSS2_PHY_687_DATA
+			DDRSS2_PHY_688_DATA
+			DDRSS2_PHY_689_DATA
+			DDRSS2_PHY_690_DATA
+			DDRSS2_PHY_691_DATA
+			DDRSS2_PHY_692_DATA
+			DDRSS2_PHY_693_DATA
+			DDRSS2_PHY_694_DATA
+			DDRSS2_PHY_695_DATA
+			DDRSS2_PHY_696_DATA
+			DDRSS2_PHY_697_DATA
+			DDRSS2_PHY_698_DATA
+			DDRSS2_PHY_699_DATA
+			DDRSS2_PHY_700_DATA
+			DDRSS2_PHY_701_DATA
+			DDRSS2_PHY_702_DATA
+			DDRSS2_PHY_703_DATA
+			DDRSS2_PHY_704_DATA
+			DDRSS2_PHY_705_DATA
+			DDRSS2_PHY_706_DATA
+			DDRSS2_PHY_707_DATA
+			DDRSS2_PHY_708_DATA
+			DDRSS2_PHY_709_DATA
+			DDRSS2_PHY_710_DATA
+			DDRSS2_PHY_711_DATA
+			DDRSS2_PHY_712_DATA
+			DDRSS2_PHY_713_DATA
+			DDRSS2_PHY_714_DATA
+			DDRSS2_PHY_715_DATA
+			DDRSS2_PHY_716_DATA
+			DDRSS2_PHY_717_DATA
+			DDRSS2_PHY_718_DATA
+			DDRSS2_PHY_719_DATA
+			DDRSS2_PHY_720_DATA
+			DDRSS2_PHY_721_DATA
+			DDRSS2_PHY_722_DATA
+			DDRSS2_PHY_723_DATA
+			DDRSS2_PHY_724_DATA
+			DDRSS2_PHY_725_DATA
+			DDRSS2_PHY_726_DATA
+			DDRSS2_PHY_727_DATA
+			DDRSS2_PHY_728_DATA
+			DDRSS2_PHY_729_DATA
+			DDRSS2_PHY_730_DATA
+			DDRSS2_PHY_731_DATA
+			DDRSS2_PHY_732_DATA
+			DDRSS2_PHY_733_DATA
+			DDRSS2_PHY_734_DATA
+			DDRSS2_PHY_735_DATA
+			DDRSS2_PHY_736_DATA
+			DDRSS2_PHY_737_DATA
+			DDRSS2_PHY_738_DATA
+			DDRSS2_PHY_739_DATA
+			DDRSS2_PHY_740_DATA
+			DDRSS2_PHY_741_DATA
+			DDRSS2_PHY_742_DATA
+			DDRSS2_PHY_743_DATA
+			DDRSS2_PHY_744_DATA
+			DDRSS2_PHY_745_DATA
+			DDRSS2_PHY_746_DATA
+			DDRSS2_PHY_747_DATA
+			DDRSS2_PHY_748_DATA
+			DDRSS2_PHY_749_DATA
+			DDRSS2_PHY_750_DATA
+			DDRSS2_PHY_751_DATA
+			DDRSS2_PHY_752_DATA
+			DDRSS2_PHY_753_DATA
+			DDRSS2_PHY_754_DATA
+			DDRSS2_PHY_755_DATA
+			DDRSS2_PHY_756_DATA
+			DDRSS2_PHY_757_DATA
+			DDRSS2_PHY_758_DATA
+			DDRSS2_PHY_759_DATA
+			DDRSS2_PHY_760_DATA
+			DDRSS2_PHY_761_DATA
+			DDRSS2_PHY_762_DATA
+			DDRSS2_PHY_763_DATA
+			DDRSS2_PHY_764_DATA
+			DDRSS2_PHY_765_DATA
+			DDRSS2_PHY_766_DATA
+			DDRSS2_PHY_767_DATA
+			DDRSS2_PHY_768_DATA
+			DDRSS2_PHY_769_DATA
+			DDRSS2_PHY_770_DATA
+			DDRSS2_PHY_771_DATA
+			DDRSS2_PHY_772_DATA
+			DDRSS2_PHY_773_DATA
+			DDRSS2_PHY_774_DATA
+			DDRSS2_PHY_775_DATA
+			DDRSS2_PHY_776_DATA
+			DDRSS2_PHY_777_DATA
+			DDRSS2_PHY_778_DATA
+			DDRSS2_PHY_779_DATA
+			DDRSS2_PHY_780_DATA
+			DDRSS2_PHY_781_DATA
+			DDRSS2_PHY_782_DATA
+			DDRSS2_PHY_783_DATA
+			DDRSS2_PHY_784_DATA
+			DDRSS2_PHY_785_DATA
+			DDRSS2_PHY_786_DATA
+			DDRSS2_PHY_787_DATA
+			DDRSS2_PHY_788_DATA
+			DDRSS2_PHY_789_DATA
+			DDRSS2_PHY_790_DATA
+			DDRSS2_PHY_791_DATA
+			DDRSS2_PHY_792_DATA
+			DDRSS2_PHY_793_DATA
+			DDRSS2_PHY_794_DATA
+			DDRSS2_PHY_795_DATA
+			DDRSS2_PHY_796_DATA
+			DDRSS2_PHY_797_DATA
+			DDRSS2_PHY_798_DATA
+			DDRSS2_PHY_799_DATA
+			DDRSS2_PHY_800_DATA
+			DDRSS2_PHY_801_DATA
+			DDRSS2_PHY_802_DATA
+			DDRSS2_PHY_803_DATA
+			DDRSS2_PHY_804_DATA
+			DDRSS2_PHY_805_DATA
+			DDRSS2_PHY_806_DATA
+			DDRSS2_PHY_807_DATA
+			DDRSS2_PHY_808_DATA
+			DDRSS2_PHY_809_DATA
+			DDRSS2_PHY_810_DATA
+			DDRSS2_PHY_811_DATA
+			DDRSS2_PHY_812_DATA
+			DDRSS2_PHY_813_DATA
+			DDRSS2_PHY_814_DATA
+			DDRSS2_PHY_815_DATA
+			DDRSS2_PHY_816_DATA
+			DDRSS2_PHY_817_DATA
+			DDRSS2_PHY_818_DATA
+			DDRSS2_PHY_819_DATA
+			DDRSS2_PHY_820_DATA
+			DDRSS2_PHY_821_DATA
+			DDRSS2_PHY_822_DATA
+			DDRSS2_PHY_823_DATA
+			DDRSS2_PHY_824_DATA
+			DDRSS2_PHY_825_DATA
+			DDRSS2_PHY_826_DATA
+			DDRSS2_PHY_827_DATA
+			DDRSS2_PHY_828_DATA
+			DDRSS2_PHY_829_DATA
+			DDRSS2_PHY_830_DATA
+			DDRSS2_PHY_831_DATA
+			DDRSS2_PHY_832_DATA
+			DDRSS2_PHY_833_DATA
+			DDRSS2_PHY_834_DATA
+			DDRSS2_PHY_835_DATA
+			DDRSS2_PHY_836_DATA
+			DDRSS2_PHY_837_DATA
+			DDRSS2_PHY_838_DATA
+			DDRSS2_PHY_839_DATA
+			DDRSS2_PHY_840_DATA
+			DDRSS2_PHY_841_DATA
+			DDRSS2_PHY_842_DATA
+			DDRSS2_PHY_843_DATA
+			DDRSS2_PHY_844_DATA
+			DDRSS2_PHY_845_DATA
+			DDRSS2_PHY_846_DATA
+			DDRSS2_PHY_847_DATA
+			DDRSS2_PHY_848_DATA
+			DDRSS2_PHY_849_DATA
+			DDRSS2_PHY_850_DATA
+			DDRSS2_PHY_851_DATA
+			DDRSS2_PHY_852_DATA
+			DDRSS2_PHY_853_DATA
+			DDRSS2_PHY_854_DATA
+			DDRSS2_PHY_855_DATA
+			DDRSS2_PHY_856_DATA
+			DDRSS2_PHY_857_DATA
+			DDRSS2_PHY_858_DATA
+			DDRSS2_PHY_859_DATA
+			DDRSS2_PHY_860_DATA
+			DDRSS2_PHY_861_DATA
+			DDRSS2_PHY_862_DATA
+			DDRSS2_PHY_863_DATA
+			DDRSS2_PHY_864_DATA
+			DDRSS2_PHY_865_DATA
+			DDRSS2_PHY_866_DATA
+			DDRSS2_PHY_867_DATA
+			DDRSS2_PHY_868_DATA
+			DDRSS2_PHY_869_DATA
+			DDRSS2_PHY_870_DATA
+			DDRSS2_PHY_871_DATA
+			DDRSS2_PHY_872_DATA
+			DDRSS2_PHY_873_DATA
+			DDRSS2_PHY_874_DATA
+			DDRSS2_PHY_875_DATA
+			DDRSS2_PHY_876_DATA
+			DDRSS2_PHY_877_DATA
+			DDRSS2_PHY_878_DATA
+			DDRSS2_PHY_879_DATA
+			DDRSS2_PHY_880_DATA
+			DDRSS2_PHY_881_DATA
+			DDRSS2_PHY_882_DATA
+			DDRSS2_PHY_883_DATA
+			DDRSS2_PHY_884_DATA
+			DDRSS2_PHY_885_DATA
+			DDRSS2_PHY_886_DATA
+			DDRSS2_PHY_887_DATA
+			DDRSS2_PHY_888_DATA
+			DDRSS2_PHY_889_DATA
+			DDRSS2_PHY_890_DATA
+			DDRSS2_PHY_891_DATA
+			DDRSS2_PHY_892_DATA
+			DDRSS2_PHY_893_DATA
+			DDRSS2_PHY_894_DATA
+			DDRSS2_PHY_895_DATA
+			DDRSS2_PHY_896_DATA
+			DDRSS2_PHY_897_DATA
+			DDRSS2_PHY_898_DATA
+			DDRSS2_PHY_899_DATA
+			DDRSS2_PHY_900_DATA
+			DDRSS2_PHY_901_DATA
+			DDRSS2_PHY_902_DATA
+			DDRSS2_PHY_903_DATA
+			DDRSS2_PHY_904_DATA
+			DDRSS2_PHY_905_DATA
+			DDRSS2_PHY_906_DATA
+			DDRSS2_PHY_907_DATA
+			DDRSS2_PHY_908_DATA
+			DDRSS2_PHY_909_DATA
+			DDRSS2_PHY_910_DATA
+			DDRSS2_PHY_911_DATA
+			DDRSS2_PHY_912_DATA
+			DDRSS2_PHY_913_DATA
+			DDRSS2_PHY_914_DATA
+			DDRSS2_PHY_915_DATA
+			DDRSS2_PHY_916_DATA
+			DDRSS2_PHY_917_DATA
+			DDRSS2_PHY_918_DATA
+			DDRSS2_PHY_919_DATA
+			DDRSS2_PHY_920_DATA
+			DDRSS2_PHY_921_DATA
+			DDRSS2_PHY_922_DATA
+			DDRSS2_PHY_923_DATA
+			DDRSS2_PHY_924_DATA
+			DDRSS2_PHY_925_DATA
+			DDRSS2_PHY_926_DATA
+			DDRSS2_PHY_927_DATA
+			DDRSS2_PHY_928_DATA
+			DDRSS2_PHY_929_DATA
+			DDRSS2_PHY_930_DATA
+			DDRSS2_PHY_931_DATA
+			DDRSS2_PHY_932_DATA
+			DDRSS2_PHY_933_DATA
+			DDRSS2_PHY_934_DATA
+			DDRSS2_PHY_935_DATA
+			DDRSS2_PHY_936_DATA
+			DDRSS2_PHY_937_DATA
+			DDRSS2_PHY_938_DATA
+			DDRSS2_PHY_939_DATA
+			DDRSS2_PHY_940_DATA
+			DDRSS2_PHY_941_DATA
+			DDRSS2_PHY_942_DATA
+			DDRSS2_PHY_943_DATA
+			DDRSS2_PHY_944_DATA
+			DDRSS2_PHY_945_DATA
+			DDRSS2_PHY_946_DATA
+			DDRSS2_PHY_947_DATA
+			DDRSS2_PHY_948_DATA
+			DDRSS2_PHY_949_DATA
+			DDRSS2_PHY_950_DATA
+			DDRSS2_PHY_951_DATA
+			DDRSS2_PHY_952_DATA
+			DDRSS2_PHY_953_DATA
+			DDRSS2_PHY_954_DATA
+			DDRSS2_PHY_955_DATA
+			DDRSS2_PHY_956_DATA
+			DDRSS2_PHY_957_DATA
+			DDRSS2_PHY_958_DATA
+			DDRSS2_PHY_959_DATA
+			DDRSS2_PHY_960_DATA
+			DDRSS2_PHY_961_DATA
+			DDRSS2_PHY_962_DATA
+			DDRSS2_PHY_963_DATA
+			DDRSS2_PHY_964_DATA
+			DDRSS2_PHY_965_DATA
+			DDRSS2_PHY_966_DATA
+			DDRSS2_PHY_967_DATA
+			DDRSS2_PHY_968_DATA
+			DDRSS2_PHY_969_DATA
+			DDRSS2_PHY_970_DATA
+			DDRSS2_PHY_971_DATA
+			DDRSS2_PHY_972_DATA
+			DDRSS2_PHY_973_DATA
+			DDRSS2_PHY_974_DATA
+			DDRSS2_PHY_975_DATA
+			DDRSS2_PHY_976_DATA
+			DDRSS2_PHY_977_DATA
+			DDRSS2_PHY_978_DATA
+			DDRSS2_PHY_979_DATA
+			DDRSS2_PHY_980_DATA
+			DDRSS2_PHY_981_DATA
+			DDRSS2_PHY_982_DATA
+			DDRSS2_PHY_983_DATA
+			DDRSS2_PHY_984_DATA
+			DDRSS2_PHY_985_DATA
+			DDRSS2_PHY_986_DATA
+			DDRSS2_PHY_987_DATA
+			DDRSS2_PHY_988_DATA
+			DDRSS2_PHY_989_DATA
+			DDRSS2_PHY_990_DATA
+			DDRSS2_PHY_991_DATA
+			DDRSS2_PHY_992_DATA
+			DDRSS2_PHY_993_DATA
+			DDRSS2_PHY_994_DATA
+			DDRSS2_PHY_995_DATA
+			DDRSS2_PHY_996_DATA
+			DDRSS2_PHY_997_DATA
+			DDRSS2_PHY_998_DATA
+			DDRSS2_PHY_999_DATA
+			DDRSS2_PHY_1000_DATA
+			DDRSS2_PHY_1001_DATA
+			DDRSS2_PHY_1002_DATA
+			DDRSS2_PHY_1003_DATA
+			DDRSS2_PHY_1004_DATA
+			DDRSS2_PHY_1005_DATA
+			DDRSS2_PHY_1006_DATA
+			DDRSS2_PHY_1007_DATA
+			DDRSS2_PHY_1008_DATA
+			DDRSS2_PHY_1009_DATA
+			DDRSS2_PHY_1010_DATA
+			DDRSS2_PHY_1011_DATA
+			DDRSS2_PHY_1012_DATA
+			DDRSS2_PHY_1013_DATA
+			DDRSS2_PHY_1014_DATA
+			DDRSS2_PHY_1015_DATA
+			DDRSS2_PHY_1016_DATA
+			DDRSS2_PHY_1017_DATA
+			DDRSS2_PHY_1018_DATA
+			DDRSS2_PHY_1019_DATA
+			DDRSS2_PHY_1020_DATA
+			DDRSS2_PHY_1021_DATA
+			DDRSS2_PHY_1022_DATA
+			DDRSS2_PHY_1023_DATA
+			DDRSS2_PHY_1024_DATA
+			DDRSS2_PHY_1025_DATA
+			DDRSS2_PHY_1026_DATA
+			DDRSS2_PHY_1027_DATA
+			DDRSS2_PHY_1028_DATA
+			DDRSS2_PHY_1029_DATA
+			DDRSS2_PHY_1030_DATA
+			DDRSS2_PHY_1031_DATA
+			DDRSS2_PHY_1032_DATA
+			DDRSS2_PHY_1033_DATA
+			DDRSS2_PHY_1034_DATA
+			DDRSS2_PHY_1035_DATA
+			DDRSS2_PHY_1036_DATA
+			DDRSS2_PHY_1037_DATA
+			DDRSS2_PHY_1038_DATA
+			DDRSS2_PHY_1039_DATA
+			DDRSS2_PHY_1040_DATA
+			DDRSS2_PHY_1041_DATA
+			DDRSS2_PHY_1042_DATA
+			DDRSS2_PHY_1043_DATA
+			DDRSS2_PHY_1044_DATA
+			DDRSS2_PHY_1045_DATA
+			DDRSS2_PHY_1046_DATA
+			DDRSS2_PHY_1047_DATA
+			DDRSS2_PHY_1048_DATA
+			DDRSS2_PHY_1049_DATA
+			DDRSS2_PHY_1050_DATA
+			DDRSS2_PHY_1051_DATA
+			DDRSS2_PHY_1052_DATA
+			DDRSS2_PHY_1053_DATA
+			DDRSS2_PHY_1054_DATA
+			DDRSS2_PHY_1055_DATA
+			DDRSS2_PHY_1056_DATA
+			DDRSS2_PHY_1057_DATA
+			DDRSS2_PHY_1058_DATA
+			DDRSS2_PHY_1059_DATA
+			DDRSS2_PHY_1060_DATA
+			DDRSS2_PHY_1061_DATA
+			DDRSS2_PHY_1062_DATA
+			DDRSS2_PHY_1063_DATA
+			DDRSS2_PHY_1064_DATA
+			DDRSS2_PHY_1065_DATA
+			DDRSS2_PHY_1066_DATA
+			DDRSS2_PHY_1067_DATA
+			DDRSS2_PHY_1068_DATA
+			DDRSS2_PHY_1069_DATA
+			DDRSS2_PHY_1070_DATA
+			DDRSS2_PHY_1071_DATA
+			DDRSS2_PHY_1072_DATA
+			DDRSS2_PHY_1073_DATA
+			DDRSS2_PHY_1074_DATA
+			DDRSS2_PHY_1075_DATA
+			DDRSS2_PHY_1076_DATA
+			DDRSS2_PHY_1077_DATA
+			DDRSS2_PHY_1078_DATA
+			DDRSS2_PHY_1079_DATA
+			DDRSS2_PHY_1080_DATA
+			DDRSS2_PHY_1081_DATA
+			DDRSS2_PHY_1082_DATA
+			DDRSS2_PHY_1083_DATA
+			DDRSS2_PHY_1084_DATA
+			DDRSS2_PHY_1085_DATA
+			DDRSS2_PHY_1086_DATA
+			DDRSS2_PHY_1087_DATA
+			DDRSS2_PHY_1088_DATA
+			DDRSS2_PHY_1089_DATA
+			DDRSS2_PHY_1090_DATA
+			DDRSS2_PHY_1091_DATA
+			DDRSS2_PHY_1092_DATA
+			DDRSS2_PHY_1093_DATA
+			DDRSS2_PHY_1094_DATA
+			DDRSS2_PHY_1095_DATA
+			DDRSS2_PHY_1096_DATA
+			DDRSS2_PHY_1097_DATA
+			DDRSS2_PHY_1098_DATA
+			DDRSS2_PHY_1099_DATA
+			DDRSS2_PHY_1100_DATA
+			DDRSS2_PHY_1101_DATA
+			DDRSS2_PHY_1102_DATA
+			DDRSS2_PHY_1103_DATA
+			DDRSS2_PHY_1104_DATA
+			DDRSS2_PHY_1105_DATA
+			DDRSS2_PHY_1106_DATA
+			DDRSS2_PHY_1107_DATA
+			DDRSS2_PHY_1108_DATA
+			DDRSS2_PHY_1109_DATA
+			DDRSS2_PHY_1110_DATA
+			DDRSS2_PHY_1111_DATA
+			DDRSS2_PHY_1112_DATA
+			DDRSS2_PHY_1113_DATA
+			DDRSS2_PHY_1114_DATA
+			DDRSS2_PHY_1115_DATA
+			DDRSS2_PHY_1116_DATA
+			DDRSS2_PHY_1117_DATA
+			DDRSS2_PHY_1118_DATA
+			DDRSS2_PHY_1119_DATA
+			DDRSS2_PHY_1120_DATA
+			DDRSS2_PHY_1121_DATA
+			DDRSS2_PHY_1122_DATA
+			DDRSS2_PHY_1123_DATA
+			DDRSS2_PHY_1124_DATA
+			DDRSS2_PHY_1125_DATA
+			DDRSS2_PHY_1126_DATA
+			DDRSS2_PHY_1127_DATA
+			DDRSS2_PHY_1128_DATA
+			DDRSS2_PHY_1129_DATA
+			DDRSS2_PHY_1130_DATA
+			DDRSS2_PHY_1131_DATA
+			DDRSS2_PHY_1132_DATA
+			DDRSS2_PHY_1133_DATA
+			DDRSS2_PHY_1134_DATA
+			DDRSS2_PHY_1135_DATA
+			DDRSS2_PHY_1136_DATA
+			DDRSS2_PHY_1137_DATA
+			DDRSS2_PHY_1138_DATA
+			DDRSS2_PHY_1139_DATA
+			DDRSS2_PHY_1140_DATA
+			DDRSS2_PHY_1141_DATA
+			DDRSS2_PHY_1142_DATA
+			DDRSS2_PHY_1143_DATA
+			DDRSS2_PHY_1144_DATA
+			DDRSS2_PHY_1145_DATA
+			DDRSS2_PHY_1146_DATA
+			DDRSS2_PHY_1147_DATA
+			DDRSS2_PHY_1148_DATA
+			DDRSS2_PHY_1149_DATA
+			DDRSS2_PHY_1150_DATA
+			DDRSS2_PHY_1151_DATA
+			DDRSS2_PHY_1152_DATA
+			DDRSS2_PHY_1153_DATA
+			DDRSS2_PHY_1154_DATA
+			DDRSS2_PHY_1155_DATA
+			DDRSS2_PHY_1156_DATA
+			DDRSS2_PHY_1157_DATA
+			DDRSS2_PHY_1158_DATA
+			DDRSS2_PHY_1159_DATA
+			DDRSS2_PHY_1160_DATA
+			DDRSS2_PHY_1161_DATA
+			DDRSS2_PHY_1162_DATA
+			DDRSS2_PHY_1163_DATA
+			DDRSS2_PHY_1164_DATA
+			DDRSS2_PHY_1165_DATA
+			DDRSS2_PHY_1166_DATA
+			DDRSS2_PHY_1167_DATA
+			DDRSS2_PHY_1168_DATA
+			DDRSS2_PHY_1169_DATA
+			DDRSS2_PHY_1170_DATA
+			DDRSS2_PHY_1171_DATA
+			DDRSS2_PHY_1172_DATA
+			DDRSS2_PHY_1173_DATA
+			DDRSS2_PHY_1174_DATA
+			DDRSS2_PHY_1175_DATA
+			DDRSS2_PHY_1176_DATA
+			DDRSS2_PHY_1177_DATA
+			DDRSS2_PHY_1178_DATA
+			DDRSS2_PHY_1179_DATA
+			DDRSS2_PHY_1180_DATA
+			DDRSS2_PHY_1181_DATA
+			DDRSS2_PHY_1182_DATA
+			DDRSS2_PHY_1183_DATA
+			DDRSS2_PHY_1184_DATA
+			DDRSS2_PHY_1185_DATA
+			DDRSS2_PHY_1186_DATA
+			DDRSS2_PHY_1187_DATA
+			DDRSS2_PHY_1188_DATA
+			DDRSS2_PHY_1189_DATA
+			DDRSS2_PHY_1190_DATA
+			DDRSS2_PHY_1191_DATA
+			DDRSS2_PHY_1192_DATA
+			DDRSS2_PHY_1193_DATA
+			DDRSS2_PHY_1194_DATA
+			DDRSS2_PHY_1195_DATA
+			DDRSS2_PHY_1196_DATA
+			DDRSS2_PHY_1197_DATA
+			DDRSS2_PHY_1198_DATA
+			DDRSS2_PHY_1199_DATA
+			DDRSS2_PHY_1200_DATA
+			DDRSS2_PHY_1201_DATA
+			DDRSS2_PHY_1202_DATA
+			DDRSS2_PHY_1203_DATA
+			DDRSS2_PHY_1204_DATA
+			DDRSS2_PHY_1205_DATA
+			DDRSS2_PHY_1206_DATA
+			DDRSS2_PHY_1207_DATA
+			DDRSS2_PHY_1208_DATA
+			DDRSS2_PHY_1209_DATA
+			DDRSS2_PHY_1210_DATA
+			DDRSS2_PHY_1211_DATA
+			DDRSS2_PHY_1212_DATA
+			DDRSS2_PHY_1213_DATA
+			DDRSS2_PHY_1214_DATA
+			DDRSS2_PHY_1215_DATA
+			DDRSS2_PHY_1216_DATA
+			DDRSS2_PHY_1217_DATA
+			DDRSS2_PHY_1218_DATA
+			DDRSS2_PHY_1219_DATA
+			DDRSS2_PHY_1220_DATA
+			DDRSS2_PHY_1221_DATA
+			DDRSS2_PHY_1222_DATA
+			DDRSS2_PHY_1223_DATA
+			DDRSS2_PHY_1224_DATA
+			DDRSS2_PHY_1225_DATA
+			DDRSS2_PHY_1226_DATA
+			DDRSS2_PHY_1227_DATA
+			DDRSS2_PHY_1228_DATA
+			DDRSS2_PHY_1229_DATA
+			DDRSS2_PHY_1230_DATA
+			DDRSS2_PHY_1231_DATA
+			DDRSS2_PHY_1232_DATA
+			DDRSS2_PHY_1233_DATA
+			DDRSS2_PHY_1234_DATA
+			DDRSS2_PHY_1235_DATA
+			DDRSS2_PHY_1236_DATA
+			DDRSS2_PHY_1237_DATA
+			DDRSS2_PHY_1238_DATA
+			DDRSS2_PHY_1239_DATA
+			DDRSS2_PHY_1240_DATA
+			DDRSS2_PHY_1241_DATA
+			DDRSS2_PHY_1242_DATA
+			DDRSS2_PHY_1243_DATA
+			DDRSS2_PHY_1244_DATA
+			DDRSS2_PHY_1245_DATA
+			DDRSS2_PHY_1246_DATA
+			DDRSS2_PHY_1247_DATA
+			DDRSS2_PHY_1248_DATA
+			DDRSS2_PHY_1249_DATA
+			DDRSS2_PHY_1250_DATA
+			DDRSS2_PHY_1251_DATA
+			DDRSS2_PHY_1252_DATA
+			DDRSS2_PHY_1253_DATA
+			DDRSS2_PHY_1254_DATA
+			DDRSS2_PHY_1255_DATA
+			DDRSS2_PHY_1256_DATA
+			DDRSS2_PHY_1257_DATA
+			DDRSS2_PHY_1258_DATA
+			DDRSS2_PHY_1259_DATA
+			DDRSS2_PHY_1260_DATA
+			DDRSS2_PHY_1261_DATA
+			DDRSS2_PHY_1262_DATA
+			DDRSS2_PHY_1263_DATA
+			DDRSS2_PHY_1264_DATA
+			DDRSS2_PHY_1265_DATA
+			DDRSS2_PHY_1266_DATA
+			DDRSS2_PHY_1267_DATA
+			DDRSS2_PHY_1268_DATA
+			DDRSS2_PHY_1269_DATA
+			DDRSS2_PHY_1270_DATA
+			DDRSS2_PHY_1271_DATA
+			DDRSS2_PHY_1272_DATA
+			DDRSS2_PHY_1273_DATA
+			DDRSS2_PHY_1274_DATA
+			DDRSS2_PHY_1275_DATA
+			DDRSS2_PHY_1276_DATA
+			DDRSS2_PHY_1277_DATA
+			DDRSS2_PHY_1278_DATA
+			DDRSS2_PHY_1279_DATA
+			DDRSS2_PHY_1280_DATA
+			DDRSS2_PHY_1281_DATA
+			DDRSS2_PHY_1282_DATA
+			DDRSS2_PHY_1283_DATA
+			DDRSS2_PHY_1284_DATA
+			DDRSS2_PHY_1285_DATA
+			DDRSS2_PHY_1286_DATA
+			DDRSS2_PHY_1287_DATA
+			DDRSS2_PHY_1288_DATA
+			DDRSS2_PHY_1289_DATA
+			DDRSS2_PHY_1290_DATA
+			DDRSS2_PHY_1291_DATA
+			DDRSS2_PHY_1292_DATA
+			DDRSS2_PHY_1293_DATA
+			DDRSS2_PHY_1294_DATA
+			DDRSS2_PHY_1295_DATA
+			DDRSS2_PHY_1296_DATA
+			DDRSS2_PHY_1297_DATA
+			DDRSS2_PHY_1298_DATA
+			DDRSS2_PHY_1299_DATA
+			DDRSS2_PHY_1300_DATA
+			DDRSS2_PHY_1301_DATA
+			DDRSS2_PHY_1302_DATA
+			DDRSS2_PHY_1303_DATA
+			DDRSS2_PHY_1304_DATA
+			DDRSS2_PHY_1305_DATA
+			DDRSS2_PHY_1306_DATA
+			DDRSS2_PHY_1307_DATA
+			DDRSS2_PHY_1308_DATA
+			DDRSS2_PHY_1309_DATA
+			DDRSS2_PHY_1310_DATA
+			DDRSS2_PHY_1311_DATA
+			DDRSS2_PHY_1312_DATA
+			DDRSS2_PHY_1313_DATA
+			DDRSS2_PHY_1314_DATA
+			DDRSS2_PHY_1315_DATA
+			DDRSS2_PHY_1316_DATA
+			DDRSS2_PHY_1317_DATA
+			DDRSS2_PHY_1318_DATA
+			DDRSS2_PHY_1319_DATA
+			DDRSS2_PHY_1320_DATA
+			DDRSS2_PHY_1321_DATA
+			DDRSS2_PHY_1322_DATA
+			DDRSS2_PHY_1323_DATA
+			DDRSS2_PHY_1324_DATA
+			DDRSS2_PHY_1325_DATA
+			DDRSS2_PHY_1326_DATA
+			DDRSS2_PHY_1327_DATA
+			DDRSS2_PHY_1328_DATA
+			DDRSS2_PHY_1329_DATA
+			DDRSS2_PHY_1330_DATA
+			DDRSS2_PHY_1331_DATA
+			DDRSS2_PHY_1332_DATA
+			DDRSS2_PHY_1333_DATA
+			DDRSS2_PHY_1334_DATA
+			DDRSS2_PHY_1335_DATA
+			DDRSS2_PHY_1336_DATA
+			DDRSS2_PHY_1337_DATA
+			DDRSS2_PHY_1338_DATA
+			DDRSS2_PHY_1339_DATA
+			DDRSS2_PHY_1340_DATA
+			DDRSS2_PHY_1341_DATA
+			DDRSS2_PHY_1342_DATA
+			DDRSS2_PHY_1343_DATA
+			DDRSS2_PHY_1344_DATA
+			DDRSS2_PHY_1345_DATA
+			DDRSS2_PHY_1346_DATA
+			DDRSS2_PHY_1347_DATA
+			DDRSS2_PHY_1348_DATA
+			DDRSS2_PHY_1349_DATA
+			DDRSS2_PHY_1350_DATA
+			DDRSS2_PHY_1351_DATA
+			DDRSS2_PHY_1352_DATA
+			DDRSS2_PHY_1353_DATA
+			DDRSS2_PHY_1354_DATA
+			DDRSS2_PHY_1355_DATA
+			DDRSS2_PHY_1356_DATA
+			DDRSS2_PHY_1357_DATA
+			DDRSS2_PHY_1358_DATA
+			DDRSS2_PHY_1359_DATA
+			DDRSS2_PHY_1360_DATA
+			DDRSS2_PHY_1361_DATA
+			DDRSS2_PHY_1362_DATA
+			DDRSS2_PHY_1363_DATA
+			DDRSS2_PHY_1364_DATA
+			DDRSS2_PHY_1365_DATA
+			DDRSS2_PHY_1366_DATA
+			DDRSS2_PHY_1367_DATA
+			DDRSS2_PHY_1368_DATA
+			DDRSS2_PHY_1369_DATA
+			DDRSS2_PHY_1370_DATA
+			DDRSS2_PHY_1371_DATA
+			DDRSS2_PHY_1372_DATA
+			DDRSS2_PHY_1373_DATA
+			DDRSS2_PHY_1374_DATA
+			DDRSS2_PHY_1375_DATA
+			DDRSS2_PHY_1376_DATA
+			DDRSS2_PHY_1377_DATA
+			DDRSS2_PHY_1378_DATA
+			DDRSS2_PHY_1379_DATA
+			DDRSS2_PHY_1380_DATA
+			DDRSS2_PHY_1381_DATA
+			DDRSS2_PHY_1382_DATA
+			DDRSS2_PHY_1383_DATA
+			DDRSS2_PHY_1384_DATA
+			DDRSS2_PHY_1385_DATA
+			DDRSS2_PHY_1386_DATA
+			DDRSS2_PHY_1387_DATA
+			DDRSS2_PHY_1388_DATA
+			DDRSS2_PHY_1389_DATA
+			DDRSS2_PHY_1390_DATA
+			DDRSS2_PHY_1391_DATA
+			DDRSS2_PHY_1392_DATA
+			DDRSS2_PHY_1393_DATA
+			DDRSS2_PHY_1394_DATA
+			DDRSS2_PHY_1395_DATA
+			DDRSS2_PHY_1396_DATA
+			DDRSS2_PHY_1397_DATA
+			DDRSS2_PHY_1398_DATA
+			DDRSS2_PHY_1399_DATA
+			DDRSS2_PHY_1400_DATA
+			DDRSS2_PHY_1401_DATA
+			DDRSS2_PHY_1402_DATA
+			DDRSS2_PHY_1403_DATA
+			DDRSS2_PHY_1404_DATA
+			DDRSS2_PHY_1405_DATA
+			DDRSS2_PHY_1406_DATA
+			DDRSS2_PHY_1407_DATA
+			DDRSS2_PHY_1408_DATA
+			DDRSS2_PHY_1409_DATA
+			DDRSS2_PHY_1410_DATA
+			DDRSS2_PHY_1411_DATA
+			DDRSS2_PHY_1412_DATA
+			DDRSS2_PHY_1413_DATA
+			DDRSS2_PHY_1414_DATA
+			DDRSS2_PHY_1415_DATA
+			DDRSS2_PHY_1416_DATA
+			DDRSS2_PHY_1417_DATA
+			DDRSS2_PHY_1418_DATA
+			DDRSS2_PHY_1419_DATA
+			DDRSS2_PHY_1420_DATA
+			DDRSS2_PHY_1421_DATA
+			DDRSS2_PHY_1422_DATA
+		>;
+	};
 
-		memorycontroller3: memorycontroller@29f0000 {
-			compatible = "ti,j721s2-ddrss";
-			reg = <0x0 0x029f0000 0x0 0x4000>,
-			      <0x0 0x0114000 0x0 0x100>,
-			      <0x0 0x29e0000 0x0 0x200>;
-			reg-names = "cfg", "ctrl_mmr_lp4", "ss_cfg";
-			power-domains = <&k3_pds 194 TI_SCI_PD_SHARED>,
-				<&k3_pds 139 TI_SCI_PD_SHARED>;
-			clocks = <&k3_clks 194 1>, <&k3_clks 78 2>;
-			ti,ddr-freq0 = <DDRSS_PLL_FREQUENCY_0>;
-			ti,ddr-freq1 = <DDRSS_PLL_FREQUENCY_1>;
-			ti,ddr-freq2 = <DDRSS_PLL_FREQUENCY_2>;
-			ti,ddr-fhs-cnt = <DDRSS_PLL_FHS_CNT>;
-			instance = <3>;
+	memorycontroller3: memorycontroller@29f0000 {
+		compatible = "ti,j721s2-ddrss";
+		reg = <0x0 0x029f0000 0x0 0x4000>,
+			  <0x0 0x0114000 0x0 0x100>,
+			  <0x0 0x29e0000 0x0 0x200>;
+		reg-names = "cfg", "ctrl_mmr_lp4", "ss_cfg";
+		power-domains = <&k3_pds 194 TI_SCI_PD_SHARED>,
+			<&k3_pds 139 TI_SCI_PD_SHARED>;
+		clocks = <&k3_clks 194 1>, <&k3_clks 78 2>;
+		ti,ddr-freq0 = <DDRSS_PLL_FREQUENCY_0>;
+		ti,ddr-freq1 = <DDRSS_PLL_FREQUENCY_1>;
+		ti,ddr-freq2 = <DDRSS_PLL_FREQUENCY_2>;
+		ti,ddr-fhs-cnt = <DDRSS_PLL_FHS_CNT>;
+		instance = <3>;
 
-			bootph-pre-ram;
+		bootph-pre-ram;
 
-			ti,ctl-data = <
-				DDRSS3_CTL_00_DATA
-				DDRSS3_CTL_01_DATA
-				DDRSS3_CTL_02_DATA
-				DDRSS3_CTL_03_DATA
-				DDRSS3_CTL_04_DATA
-				DDRSS3_CTL_05_DATA
-				DDRSS3_CTL_06_DATA
-				DDRSS3_CTL_07_DATA
-				DDRSS3_CTL_08_DATA
-				DDRSS3_CTL_09_DATA
-				DDRSS3_CTL_10_DATA
-				DDRSS3_CTL_11_DATA
-				DDRSS3_CTL_12_DATA
-				DDRSS3_CTL_13_DATA
-				DDRSS3_CTL_14_DATA
-				DDRSS3_CTL_15_DATA
-				DDRSS3_CTL_16_DATA
-				DDRSS3_CTL_17_DATA
-				DDRSS3_CTL_18_DATA
-				DDRSS3_CTL_19_DATA
-				DDRSS3_CTL_20_DATA
-				DDRSS3_CTL_21_DATA
-				DDRSS3_CTL_22_DATA
-				DDRSS3_CTL_23_DATA
-				DDRSS3_CTL_24_DATA
-				DDRSS3_CTL_25_DATA
-				DDRSS3_CTL_26_DATA
-				DDRSS3_CTL_27_DATA
-				DDRSS3_CTL_28_DATA
-				DDRSS3_CTL_29_DATA
-				DDRSS3_CTL_30_DATA
-				DDRSS3_CTL_31_DATA
-				DDRSS3_CTL_32_DATA
-				DDRSS3_CTL_33_DATA
-				DDRSS3_CTL_34_DATA
-				DDRSS3_CTL_35_DATA
-				DDRSS3_CTL_36_DATA
-				DDRSS3_CTL_37_DATA
-				DDRSS3_CTL_38_DATA
-				DDRSS3_CTL_39_DATA
-				DDRSS3_CTL_40_DATA
-				DDRSS3_CTL_41_DATA
-				DDRSS3_CTL_42_DATA
-				DDRSS3_CTL_43_DATA
-				DDRSS3_CTL_44_DATA
-				DDRSS3_CTL_45_DATA
-				DDRSS3_CTL_46_DATA
-				DDRSS3_CTL_47_DATA
-				DDRSS3_CTL_48_DATA
-				DDRSS3_CTL_49_DATA
-				DDRSS3_CTL_50_DATA
-				DDRSS3_CTL_51_DATA
-				DDRSS3_CTL_52_DATA
-				DDRSS3_CTL_53_DATA
-				DDRSS3_CTL_54_DATA
-				DDRSS3_CTL_55_DATA
-				DDRSS3_CTL_56_DATA
-				DDRSS3_CTL_57_DATA
-				DDRSS3_CTL_58_DATA
-				DDRSS3_CTL_59_DATA
-				DDRSS3_CTL_60_DATA
-				DDRSS3_CTL_61_DATA
-				DDRSS3_CTL_62_DATA
-				DDRSS3_CTL_63_DATA
-				DDRSS3_CTL_64_DATA
-				DDRSS3_CTL_65_DATA
-				DDRSS3_CTL_66_DATA
-				DDRSS3_CTL_67_DATA
-				DDRSS3_CTL_68_DATA
-				DDRSS3_CTL_69_DATA
-				DDRSS3_CTL_70_DATA
-				DDRSS3_CTL_71_DATA
-				DDRSS3_CTL_72_DATA
-				DDRSS3_CTL_73_DATA
-				DDRSS3_CTL_74_DATA
-				DDRSS3_CTL_75_DATA
-				DDRSS3_CTL_76_DATA
-				DDRSS3_CTL_77_DATA
-				DDRSS3_CTL_78_DATA
-				DDRSS3_CTL_79_DATA
-				DDRSS3_CTL_80_DATA
-				DDRSS3_CTL_81_DATA
-				DDRSS3_CTL_82_DATA
-				DDRSS3_CTL_83_DATA
-				DDRSS3_CTL_84_DATA
-				DDRSS3_CTL_85_DATA
-				DDRSS3_CTL_86_DATA
-				DDRSS3_CTL_87_DATA
-				DDRSS3_CTL_88_DATA
-				DDRSS3_CTL_89_DATA
-				DDRSS3_CTL_90_DATA
-				DDRSS3_CTL_91_DATA
-				DDRSS3_CTL_92_DATA
-				DDRSS3_CTL_93_DATA
-				DDRSS3_CTL_94_DATA
-				DDRSS3_CTL_95_DATA
-				DDRSS3_CTL_96_DATA
-				DDRSS3_CTL_97_DATA
-				DDRSS3_CTL_98_DATA
-				DDRSS3_CTL_99_DATA
-				DDRSS3_CTL_100_DATA
-				DDRSS3_CTL_101_DATA
-				DDRSS3_CTL_102_DATA
-				DDRSS3_CTL_103_DATA
-				DDRSS3_CTL_104_DATA
-				DDRSS3_CTL_105_DATA
-				DDRSS3_CTL_106_DATA
-				DDRSS3_CTL_107_DATA
-				DDRSS3_CTL_108_DATA
-				DDRSS3_CTL_109_DATA
-				DDRSS3_CTL_110_DATA
-				DDRSS3_CTL_111_DATA
-				DDRSS3_CTL_112_DATA
-				DDRSS3_CTL_113_DATA
-				DDRSS3_CTL_114_DATA
-				DDRSS3_CTL_115_DATA
-				DDRSS3_CTL_116_DATA
-				DDRSS3_CTL_117_DATA
-				DDRSS3_CTL_118_DATA
-				DDRSS3_CTL_119_DATA
-				DDRSS3_CTL_120_DATA
-				DDRSS3_CTL_121_DATA
-				DDRSS3_CTL_122_DATA
-				DDRSS3_CTL_123_DATA
-				DDRSS3_CTL_124_DATA
-				DDRSS3_CTL_125_DATA
-				DDRSS3_CTL_126_DATA
-				DDRSS3_CTL_127_DATA
-				DDRSS3_CTL_128_DATA
-				DDRSS3_CTL_129_DATA
-				DDRSS3_CTL_130_DATA
-				DDRSS3_CTL_131_DATA
-				DDRSS3_CTL_132_DATA
-				DDRSS3_CTL_133_DATA
-				DDRSS3_CTL_134_DATA
-				DDRSS3_CTL_135_DATA
-				DDRSS3_CTL_136_DATA
-				DDRSS3_CTL_137_DATA
-				DDRSS3_CTL_138_DATA
-				DDRSS3_CTL_139_DATA
-				DDRSS3_CTL_140_DATA
-				DDRSS3_CTL_141_DATA
-				DDRSS3_CTL_142_DATA
-				DDRSS3_CTL_143_DATA
-				DDRSS3_CTL_144_DATA
-				DDRSS3_CTL_145_DATA
-				DDRSS3_CTL_146_DATA
-				DDRSS3_CTL_147_DATA
-				DDRSS3_CTL_148_DATA
-				DDRSS3_CTL_149_DATA
-				DDRSS3_CTL_150_DATA
-				DDRSS3_CTL_151_DATA
-				DDRSS3_CTL_152_DATA
-				DDRSS3_CTL_153_DATA
-				DDRSS3_CTL_154_DATA
-				DDRSS3_CTL_155_DATA
-				DDRSS3_CTL_156_DATA
-				DDRSS3_CTL_157_DATA
-				DDRSS3_CTL_158_DATA
-				DDRSS3_CTL_159_DATA
-				DDRSS3_CTL_160_DATA
-				DDRSS3_CTL_161_DATA
-				DDRSS3_CTL_162_DATA
-				DDRSS3_CTL_163_DATA
-				DDRSS3_CTL_164_DATA
-				DDRSS3_CTL_165_DATA
-				DDRSS3_CTL_166_DATA
-				DDRSS3_CTL_167_DATA
-				DDRSS3_CTL_168_DATA
-				DDRSS3_CTL_169_DATA
-				DDRSS3_CTL_170_DATA
-				DDRSS3_CTL_171_DATA
-				DDRSS3_CTL_172_DATA
-				DDRSS3_CTL_173_DATA
-				DDRSS3_CTL_174_DATA
-				DDRSS3_CTL_175_DATA
-				DDRSS3_CTL_176_DATA
-				DDRSS3_CTL_177_DATA
-				DDRSS3_CTL_178_DATA
-				DDRSS3_CTL_179_DATA
-				DDRSS3_CTL_180_DATA
-				DDRSS3_CTL_181_DATA
-				DDRSS3_CTL_182_DATA
-				DDRSS3_CTL_183_DATA
-				DDRSS3_CTL_184_DATA
-				DDRSS3_CTL_185_DATA
-				DDRSS3_CTL_186_DATA
-				DDRSS3_CTL_187_DATA
-				DDRSS3_CTL_188_DATA
-				DDRSS3_CTL_189_DATA
-				DDRSS3_CTL_190_DATA
-				DDRSS3_CTL_191_DATA
-				DDRSS3_CTL_192_DATA
-				DDRSS3_CTL_193_DATA
-				DDRSS3_CTL_194_DATA
-				DDRSS3_CTL_195_DATA
-				DDRSS3_CTL_196_DATA
-				DDRSS3_CTL_197_DATA
-				DDRSS3_CTL_198_DATA
-				DDRSS3_CTL_199_DATA
-				DDRSS3_CTL_200_DATA
-				DDRSS3_CTL_201_DATA
-				DDRSS3_CTL_202_DATA
-				DDRSS3_CTL_203_DATA
-				DDRSS3_CTL_204_DATA
-				DDRSS3_CTL_205_DATA
-				DDRSS3_CTL_206_DATA
-				DDRSS3_CTL_207_DATA
-				DDRSS3_CTL_208_DATA
-				DDRSS3_CTL_209_DATA
-				DDRSS3_CTL_210_DATA
-				DDRSS3_CTL_211_DATA
-				DDRSS3_CTL_212_DATA
-				DDRSS3_CTL_213_DATA
-				DDRSS3_CTL_214_DATA
-				DDRSS3_CTL_215_DATA
-				DDRSS3_CTL_216_DATA
-				DDRSS3_CTL_217_DATA
-				DDRSS3_CTL_218_DATA
-				DDRSS3_CTL_219_DATA
-				DDRSS3_CTL_220_DATA
-				DDRSS3_CTL_221_DATA
-				DDRSS3_CTL_222_DATA
-				DDRSS3_CTL_223_DATA
-				DDRSS3_CTL_224_DATA
-				DDRSS3_CTL_225_DATA
-				DDRSS3_CTL_226_DATA
-				DDRSS3_CTL_227_DATA
-				DDRSS3_CTL_228_DATA
-				DDRSS3_CTL_229_DATA
-				DDRSS3_CTL_230_DATA
-				DDRSS3_CTL_231_DATA
-				DDRSS3_CTL_232_DATA
-				DDRSS3_CTL_233_DATA
-				DDRSS3_CTL_234_DATA
-				DDRSS3_CTL_235_DATA
-				DDRSS3_CTL_236_DATA
-				DDRSS3_CTL_237_DATA
-				DDRSS3_CTL_238_DATA
-				DDRSS3_CTL_239_DATA
-				DDRSS3_CTL_240_DATA
-				DDRSS3_CTL_241_DATA
-				DDRSS3_CTL_242_DATA
-				DDRSS3_CTL_243_DATA
-				DDRSS3_CTL_244_DATA
-				DDRSS3_CTL_245_DATA
-				DDRSS3_CTL_246_DATA
-				DDRSS3_CTL_247_DATA
-				DDRSS3_CTL_248_DATA
-				DDRSS3_CTL_249_DATA
-				DDRSS3_CTL_250_DATA
-				DDRSS3_CTL_251_DATA
-				DDRSS3_CTL_252_DATA
-				DDRSS3_CTL_253_DATA
-				DDRSS3_CTL_254_DATA
-				DDRSS3_CTL_255_DATA
-				DDRSS3_CTL_256_DATA
-				DDRSS3_CTL_257_DATA
-				DDRSS3_CTL_258_DATA
-				DDRSS3_CTL_259_DATA
-				DDRSS3_CTL_260_DATA
-				DDRSS3_CTL_261_DATA
-				DDRSS3_CTL_262_DATA
-				DDRSS3_CTL_263_DATA
-				DDRSS3_CTL_264_DATA
-				DDRSS3_CTL_265_DATA
-				DDRSS3_CTL_266_DATA
-				DDRSS3_CTL_267_DATA
-				DDRSS3_CTL_268_DATA
-				DDRSS3_CTL_269_DATA
-				DDRSS3_CTL_270_DATA
-				DDRSS3_CTL_271_DATA
-				DDRSS3_CTL_272_DATA
-				DDRSS3_CTL_273_DATA
-				DDRSS3_CTL_274_DATA
-				DDRSS3_CTL_275_DATA
-				DDRSS3_CTL_276_DATA
-				DDRSS3_CTL_277_DATA
-				DDRSS3_CTL_278_DATA
-				DDRSS3_CTL_279_DATA
-				DDRSS3_CTL_280_DATA
-				DDRSS3_CTL_281_DATA
-				DDRSS3_CTL_282_DATA
-				DDRSS3_CTL_283_DATA
-				DDRSS3_CTL_284_DATA
-				DDRSS3_CTL_285_DATA
-				DDRSS3_CTL_286_DATA
-				DDRSS3_CTL_287_DATA
-				DDRSS3_CTL_288_DATA
-				DDRSS3_CTL_289_DATA
-				DDRSS3_CTL_290_DATA
-				DDRSS3_CTL_291_DATA
-				DDRSS3_CTL_292_DATA
-				DDRSS3_CTL_293_DATA
-				DDRSS3_CTL_294_DATA
-				DDRSS3_CTL_295_DATA
-				DDRSS3_CTL_296_DATA
-				DDRSS3_CTL_297_DATA
-				DDRSS3_CTL_298_DATA
-				DDRSS3_CTL_299_DATA
-				DDRSS3_CTL_300_DATA
-				DDRSS3_CTL_301_DATA
-				DDRSS3_CTL_302_DATA
-				DDRSS3_CTL_303_DATA
-				DDRSS3_CTL_304_DATA
-				DDRSS3_CTL_305_DATA
-				DDRSS3_CTL_306_DATA
-				DDRSS3_CTL_307_DATA
-				DDRSS3_CTL_308_DATA
-				DDRSS3_CTL_309_DATA
-				DDRSS3_CTL_310_DATA
-				DDRSS3_CTL_311_DATA
-				DDRSS3_CTL_312_DATA
-				DDRSS3_CTL_313_DATA
-				DDRSS3_CTL_314_DATA
-				DDRSS3_CTL_315_DATA
-				DDRSS3_CTL_316_DATA
-				DDRSS3_CTL_317_DATA
-				DDRSS3_CTL_318_DATA
-				DDRSS3_CTL_319_DATA
-				DDRSS3_CTL_320_DATA
-				DDRSS3_CTL_321_DATA
-				DDRSS3_CTL_322_DATA
-				DDRSS3_CTL_323_DATA
-				DDRSS3_CTL_324_DATA
-				DDRSS3_CTL_325_DATA
-				DDRSS3_CTL_326_DATA
-				DDRSS3_CTL_327_DATA
-				DDRSS3_CTL_328_DATA
-				DDRSS3_CTL_329_DATA
-				DDRSS3_CTL_330_DATA
-				DDRSS3_CTL_331_DATA
-				DDRSS3_CTL_332_DATA
-				DDRSS3_CTL_333_DATA
-				DDRSS3_CTL_334_DATA
-				DDRSS3_CTL_335_DATA
-				DDRSS3_CTL_336_DATA
-				DDRSS3_CTL_337_DATA
-				DDRSS3_CTL_338_DATA
-				DDRSS3_CTL_339_DATA
-				DDRSS3_CTL_340_DATA
-				DDRSS3_CTL_341_DATA
-				DDRSS3_CTL_342_DATA
-				DDRSS3_CTL_343_DATA
-				DDRSS3_CTL_344_DATA
-				DDRSS3_CTL_345_DATA
-				DDRSS3_CTL_346_DATA
-				DDRSS3_CTL_347_DATA
-				DDRSS3_CTL_348_DATA
-				DDRSS3_CTL_349_DATA
-				DDRSS3_CTL_350_DATA
-				DDRSS3_CTL_351_DATA
-				DDRSS3_CTL_352_DATA
-				DDRSS3_CTL_353_DATA
-				DDRSS3_CTL_354_DATA
-				DDRSS3_CTL_355_DATA
-				DDRSS3_CTL_356_DATA
-				DDRSS3_CTL_357_DATA
-				DDRSS3_CTL_358_DATA
-				DDRSS3_CTL_359_DATA
-				DDRSS3_CTL_360_DATA
-				DDRSS3_CTL_361_DATA
-				DDRSS3_CTL_362_DATA
-				DDRSS3_CTL_363_DATA
-				DDRSS3_CTL_364_DATA
-				DDRSS3_CTL_365_DATA
-				DDRSS3_CTL_366_DATA
-				DDRSS3_CTL_367_DATA
-				DDRSS3_CTL_368_DATA
-				DDRSS3_CTL_369_DATA
-				DDRSS3_CTL_370_DATA
-				DDRSS3_CTL_371_DATA
-				DDRSS3_CTL_372_DATA
-				DDRSS3_CTL_373_DATA
-				DDRSS3_CTL_374_DATA
-				DDRSS3_CTL_375_DATA
-				DDRSS3_CTL_376_DATA
-				DDRSS3_CTL_377_DATA
-				DDRSS3_CTL_378_DATA
-				DDRSS3_CTL_379_DATA
-				DDRSS3_CTL_380_DATA
-				DDRSS3_CTL_381_DATA
-				DDRSS3_CTL_382_DATA
-				DDRSS3_CTL_383_DATA
-				DDRSS3_CTL_384_DATA
-				DDRSS3_CTL_385_DATA
-				DDRSS3_CTL_386_DATA
-				DDRSS3_CTL_387_DATA
-				DDRSS3_CTL_388_DATA
-				DDRSS3_CTL_389_DATA
-				DDRSS3_CTL_390_DATA
-				DDRSS3_CTL_391_DATA
-				DDRSS3_CTL_392_DATA
-				DDRSS3_CTL_393_DATA
-				DDRSS3_CTL_394_DATA
-				DDRSS3_CTL_395_DATA
-				DDRSS3_CTL_396_DATA
-				DDRSS3_CTL_397_DATA
-				DDRSS3_CTL_398_DATA
-				DDRSS3_CTL_399_DATA
-				DDRSS3_CTL_400_DATA
-				DDRSS3_CTL_401_DATA
-				DDRSS3_CTL_402_DATA
-				DDRSS3_CTL_403_DATA
-				DDRSS3_CTL_404_DATA
-				DDRSS3_CTL_405_DATA
-				DDRSS3_CTL_406_DATA
-				DDRSS3_CTL_407_DATA
-				DDRSS3_CTL_408_DATA
-				DDRSS3_CTL_409_DATA
-				DDRSS3_CTL_410_DATA
-				DDRSS3_CTL_411_DATA
-				DDRSS3_CTL_412_DATA
-				DDRSS3_CTL_413_DATA
-				DDRSS3_CTL_414_DATA
-				DDRSS3_CTL_415_DATA
-				DDRSS3_CTL_416_DATA
-				DDRSS3_CTL_417_DATA
-				DDRSS3_CTL_418_DATA
-				DDRSS3_CTL_419_DATA
-				DDRSS3_CTL_420_DATA
-				DDRSS3_CTL_421_DATA
-				DDRSS3_CTL_422_DATA
-				DDRSS3_CTL_423_DATA
-				DDRSS3_CTL_424_DATA
-				DDRSS3_CTL_425_DATA
-				DDRSS3_CTL_426_DATA
-				DDRSS3_CTL_427_DATA
-				DDRSS3_CTL_428_DATA
-				DDRSS3_CTL_429_DATA
-				DDRSS3_CTL_430_DATA
-				DDRSS3_CTL_431_DATA
-				DDRSS3_CTL_432_DATA
-				DDRSS3_CTL_433_DATA
-				DDRSS3_CTL_434_DATA
-				DDRSS3_CTL_435_DATA
-				DDRSS3_CTL_436_DATA
-				DDRSS3_CTL_437_DATA
-				DDRSS3_CTL_438_DATA
-				DDRSS3_CTL_439_DATA
-				DDRSS3_CTL_440_DATA
-				DDRSS3_CTL_441_DATA
-				DDRSS3_CTL_442_DATA
-				DDRSS3_CTL_443_DATA
-				DDRSS3_CTL_444_DATA
-				DDRSS3_CTL_445_DATA
-				DDRSS3_CTL_446_DATA
-				DDRSS3_CTL_447_DATA
-				DDRSS3_CTL_448_DATA
-				DDRSS3_CTL_449_DATA
-				DDRSS3_CTL_450_DATA
-				DDRSS3_CTL_451_DATA
-				DDRSS3_CTL_452_DATA
-				DDRSS3_CTL_453_DATA
-				DDRSS3_CTL_454_DATA
-				DDRSS3_CTL_455_DATA
-				DDRSS3_CTL_456_DATA
-				DDRSS3_CTL_457_DATA
-				DDRSS3_CTL_458_DATA
-			>;
+		ti,ctl-data = <
+			DDRSS3_CTL_00_DATA
+			DDRSS3_CTL_01_DATA
+			DDRSS3_CTL_02_DATA
+			DDRSS3_CTL_03_DATA
+			DDRSS3_CTL_04_DATA
+			DDRSS3_CTL_05_DATA
+			DDRSS3_CTL_06_DATA
+			DDRSS3_CTL_07_DATA
+			DDRSS3_CTL_08_DATA
+			DDRSS3_CTL_09_DATA
+			DDRSS3_CTL_10_DATA
+			DDRSS3_CTL_11_DATA
+			DDRSS3_CTL_12_DATA
+			DDRSS3_CTL_13_DATA
+			DDRSS3_CTL_14_DATA
+			DDRSS3_CTL_15_DATA
+			DDRSS3_CTL_16_DATA
+			DDRSS3_CTL_17_DATA
+			DDRSS3_CTL_18_DATA
+			DDRSS3_CTL_19_DATA
+			DDRSS3_CTL_20_DATA
+			DDRSS3_CTL_21_DATA
+			DDRSS3_CTL_22_DATA
+			DDRSS3_CTL_23_DATA
+			DDRSS3_CTL_24_DATA
+			DDRSS3_CTL_25_DATA
+			DDRSS3_CTL_26_DATA
+			DDRSS3_CTL_27_DATA
+			DDRSS3_CTL_28_DATA
+			DDRSS3_CTL_29_DATA
+			DDRSS3_CTL_30_DATA
+			DDRSS3_CTL_31_DATA
+			DDRSS3_CTL_32_DATA
+			DDRSS3_CTL_33_DATA
+			DDRSS3_CTL_34_DATA
+			DDRSS3_CTL_35_DATA
+			DDRSS3_CTL_36_DATA
+			DDRSS3_CTL_37_DATA
+			DDRSS3_CTL_38_DATA
+			DDRSS3_CTL_39_DATA
+			DDRSS3_CTL_40_DATA
+			DDRSS3_CTL_41_DATA
+			DDRSS3_CTL_42_DATA
+			DDRSS3_CTL_43_DATA
+			DDRSS3_CTL_44_DATA
+			DDRSS3_CTL_45_DATA
+			DDRSS3_CTL_46_DATA
+			DDRSS3_CTL_47_DATA
+			DDRSS3_CTL_48_DATA
+			DDRSS3_CTL_49_DATA
+			DDRSS3_CTL_50_DATA
+			DDRSS3_CTL_51_DATA
+			DDRSS3_CTL_52_DATA
+			DDRSS3_CTL_53_DATA
+			DDRSS3_CTL_54_DATA
+			DDRSS3_CTL_55_DATA
+			DDRSS3_CTL_56_DATA
+			DDRSS3_CTL_57_DATA
+			DDRSS3_CTL_58_DATA
+			DDRSS3_CTL_59_DATA
+			DDRSS3_CTL_60_DATA
+			DDRSS3_CTL_61_DATA
+			DDRSS3_CTL_62_DATA
+			DDRSS3_CTL_63_DATA
+			DDRSS3_CTL_64_DATA
+			DDRSS3_CTL_65_DATA
+			DDRSS3_CTL_66_DATA
+			DDRSS3_CTL_67_DATA
+			DDRSS3_CTL_68_DATA
+			DDRSS3_CTL_69_DATA
+			DDRSS3_CTL_70_DATA
+			DDRSS3_CTL_71_DATA
+			DDRSS3_CTL_72_DATA
+			DDRSS3_CTL_73_DATA
+			DDRSS3_CTL_74_DATA
+			DDRSS3_CTL_75_DATA
+			DDRSS3_CTL_76_DATA
+			DDRSS3_CTL_77_DATA
+			DDRSS3_CTL_78_DATA
+			DDRSS3_CTL_79_DATA
+			DDRSS3_CTL_80_DATA
+			DDRSS3_CTL_81_DATA
+			DDRSS3_CTL_82_DATA
+			DDRSS3_CTL_83_DATA
+			DDRSS3_CTL_84_DATA
+			DDRSS3_CTL_85_DATA
+			DDRSS3_CTL_86_DATA
+			DDRSS3_CTL_87_DATA
+			DDRSS3_CTL_88_DATA
+			DDRSS3_CTL_89_DATA
+			DDRSS3_CTL_90_DATA
+			DDRSS3_CTL_91_DATA
+			DDRSS3_CTL_92_DATA
+			DDRSS3_CTL_93_DATA
+			DDRSS3_CTL_94_DATA
+			DDRSS3_CTL_95_DATA
+			DDRSS3_CTL_96_DATA
+			DDRSS3_CTL_97_DATA
+			DDRSS3_CTL_98_DATA
+			DDRSS3_CTL_99_DATA
+			DDRSS3_CTL_100_DATA
+			DDRSS3_CTL_101_DATA
+			DDRSS3_CTL_102_DATA
+			DDRSS3_CTL_103_DATA
+			DDRSS3_CTL_104_DATA
+			DDRSS3_CTL_105_DATA
+			DDRSS3_CTL_106_DATA
+			DDRSS3_CTL_107_DATA
+			DDRSS3_CTL_108_DATA
+			DDRSS3_CTL_109_DATA
+			DDRSS3_CTL_110_DATA
+			DDRSS3_CTL_111_DATA
+			DDRSS3_CTL_112_DATA
+			DDRSS3_CTL_113_DATA
+			DDRSS3_CTL_114_DATA
+			DDRSS3_CTL_115_DATA
+			DDRSS3_CTL_116_DATA
+			DDRSS3_CTL_117_DATA
+			DDRSS3_CTL_118_DATA
+			DDRSS3_CTL_119_DATA
+			DDRSS3_CTL_120_DATA
+			DDRSS3_CTL_121_DATA
+			DDRSS3_CTL_122_DATA
+			DDRSS3_CTL_123_DATA
+			DDRSS3_CTL_124_DATA
+			DDRSS3_CTL_125_DATA
+			DDRSS3_CTL_126_DATA
+			DDRSS3_CTL_127_DATA
+			DDRSS3_CTL_128_DATA
+			DDRSS3_CTL_129_DATA
+			DDRSS3_CTL_130_DATA
+			DDRSS3_CTL_131_DATA
+			DDRSS3_CTL_132_DATA
+			DDRSS3_CTL_133_DATA
+			DDRSS3_CTL_134_DATA
+			DDRSS3_CTL_135_DATA
+			DDRSS3_CTL_136_DATA
+			DDRSS3_CTL_137_DATA
+			DDRSS3_CTL_138_DATA
+			DDRSS3_CTL_139_DATA
+			DDRSS3_CTL_140_DATA
+			DDRSS3_CTL_141_DATA
+			DDRSS3_CTL_142_DATA
+			DDRSS3_CTL_143_DATA
+			DDRSS3_CTL_144_DATA
+			DDRSS3_CTL_145_DATA
+			DDRSS3_CTL_146_DATA
+			DDRSS3_CTL_147_DATA
+			DDRSS3_CTL_148_DATA
+			DDRSS3_CTL_149_DATA
+			DDRSS3_CTL_150_DATA
+			DDRSS3_CTL_151_DATA
+			DDRSS3_CTL_152_DATA
+			DDRSS3_CTL_153_DATA
+			DDRSS3_CTL_154_DATA
+			DDRSS3_CTL_155_DATA
+			DDRSS3_CTL_156_DATA
+			DDRSS3_CTL_157_DATA
+			DDRSS3_CTL_158_DATA
+			DDRSS3_CTL_159_DATA
+			DDRSS3_CTL_160_DATA
+			DDRSS3_CTL_161_DATA
+			DDRSS3_CTL_162_DATA
+			DDRSS3_CTL_163_DATA
+			DDRSS3_CTL_164_DATA
+			DDRSS3_CTL_165_DATA
+			DDRSS3_CTL_166_DATA
+			DDRSS3_CTL_167_DATA
+			DDRSS3_CTL_168_DATA
+			DDRSS3_CTL_169_DATA
+			DDRSS3_CTL_170_DATA
+			DDRSS3_CTL_171_DATA
+			DDRSS3_CTL_172_DATA
+			DDRSS3_CTL_173_DATA
+			DDRSS3_CTL_174_DATA
+			DDRSS3_CTL_175_DATA
+			DDRSS3_CTL_176_DATA
+			DDRSS3_CTL_177_DATA
+			DDRSS3_CTL_178_DATA
+			DDRSS3_CTL_179_DATA
+			DDRSS3_CTL_180_DATA
+			DDRSS3_CTL_181_DATA
+			DDRSS3_CTL_182_DATA
+			DDRSS3_CTL_183_DATA
+			DDRSS3_CTL_184_DATA
+			DDRSS3_CTL_185_DATA
+			DDRSS3_CTL_186_DATA
+			DDRSS3_CTL_187_DATA
+			DDRSS3_CTL_188_DATA
+			DDRSS3_CTL_189_DATA
+			DDRSS3_CTL_190_DATA
+			DDRSS3_CTL_191_DATA
+			DDRSS3_CTL_192_DATA
+			DDRSS3_CTL_193_DATA
+			DDRSS3_CTL_194_DATA
+			DDRSS3_CTL_195_DATA
+			DDRSS3_CTL_196_DATA
+			DDRSS3_CTL_197_DATA
+			DDRSS3_CTL_198_DATA
+			DDRSS3_CTL_199_DATA
+			DDRSS3_CTL_200_DATA
+			DDRSS3_CTL_201_DATA
+			DDRSS3_CTL_202_DATA
+			DDRSS3_CTL_203_DATA
+			DDRSS3_CTL_204_DATA
+			DDRSS3_CTL_205_DATA
+			DDRSS3_CTL_206_DATA
+			DDRSS3_CTL_207_DATA
+			DDRSS3_CTL_208_DATA
+			DDRSS3_CTL_209_DATA
+			DDRSS3_CTL_210_DATA
+			DDRSS3_CTL_211_DATA
+			DDRSS3_CTL_212_DATA
+			DDRSS3_CTL_213_DATA
+			DDRSS3_CTL_214_DATA
+			DDRSS3_CTL_215_DATA
+			DDRSS3_CTL_216_DATA
+			DDRSS3_CTL_217_DATA
+			DDRSS3_CTL_218_DATA
+			DDRSS3_CTL_219_DATA
+			DDRSS3_CTL_220_DATA
+			DDRSS3_CTL_221_DATA
+			DDRSS3_CTL_222_DATA
+			DDRSS3_CTL_223_DATA
+			DDRSS3_CTL_224_DATA
+			DDRSS3_CTL_225_DATA
+			DDRSS3_CTL_226_DATA
+			DDRSS3_CTL_227_DATA
+			DDRSS3_CTL_228_DATA
+			DDRSS3_CTL_229_DATA
+			DDRSS3_CTL_230_DATA
+			DDRSS3_CTL_231_DATA
+			DDRSS3_CTL_232_DATA
+			DDRSS3_CTL_233_DATA
+			DDRSS3_CTL_234_DATA
+			DDRSS3_CTL_235_DATA
+			DDRSS3_CTL_236_DATA
+			DDRSS3_CTL_237_DATA
+			DDRSS3_CTL_238_DATA
+			DDRSS3_CTL_239_DATA
+			DDRSS3_CTL_240_DATA
+			DDRSS3_CTL_241_DATA
+			DDRSS3_CTL_242_DATA
+			DDRSS3_CTL_243_DATA
+			DDRSS3_CTL_244_DATA
+			DDRSS3_CTL_245_DATA
+			DDRSS3_CTL_246_DATA
+			DDRSS3_CTL_247_DATA
+			DDRSS3_CTL_248_DATA
+			DDRSS3_CTL_249_DATA
+			DDRSS3_CTL_250_DATA
+			DDRSS3_CTL_251_DATA
+			DDRSS3_CTL_252_DATA
+			DDRSS3_CTL_253_DATA
+			DDRSS3_CTL_254_DATA
+			DDRSS3_CTL_255_DATA
+			DDRSS3_CTL_256_DATA
+			DDRSS3_CTL_257_DATA
+			DDRSS3_CTL_258_DATA
+			DDRSS3_CTL_259_DATA
+			DDRSS3_CTL_260_DATA
+			DDRSS3_CTL_261_DATA
+			DDRSS3_CTL_262_DATA
+			DDRSS3_CTL_263_DATA
+			DDRSS3_CTL_264_DATA
+			DDRSS3_CTL_265_DATA
+			DDRSS3_CTL_266_DATA
+			DDRSS3_CTL_267_DATA
+			DDRSS3_CTL_268_DATA
+			DDRSS3_CTL_269_DATA
+			DDRSS3_CTL_270_DATA
+			DDRSS3_CTL_271_DATA
+			DDRSS3_CTL_272_DATA
+			DDRSS3_CTL_273_DATA
+			DDRSS3_CTL_274_DATA
+			DDRSS3_CTL_275_DATA
+			DDRSS3_CTL_276_DATA
+			DDRSS3_CTL_277_DATA
+			DDRSS3_CTL_278_DATA
+			DDRSS3_CTL_279_DATA
+			DDRSS3_CTL_280_DATA
+			DDRSS3_CTL_281_DATA
+			DDRSS3_CTL_282_DATA
+			DDRSS3_CTL_283_DATA
+			DDRSS3_CTL_284_DATA
+			DDRSS3_CTL_285_DATA
+			DDRSS3_CTL_286_DATA
+			DDRSS3_CTL_287_DATA
+			DDRSS3_CTL_288_DATA
+			DDRSS3_CTL_289_DATA
+			DDRSS3_CTL_290_DATA
+			DDRSS3_CTL_291_DATA
+			DDRSS3_CTL_292_DATA
+			DDRSS3_CTL_293_DATA
+			DDRSS3_CTL_294_DATA
+			DDRSS3_CTL_295_DATA
+			DDRSS3_CTL_296_DATA
+			DDRSS3_CTL_297_DATA
+			DDRSS3_CTL_298_DATA
+			DDRSS3_CTL_299_DATA
+			DDRSS3_CTL_300_DATA
+			DDRSS3_CTL_301_DATA
+			DDRSS3_CTL_302_DATA
+			DDRSS3_CTL_303_DATA
+			DDRSS3_CTL_304_DATA
+			DDRSS3_CTL_305_DATA
+			DDRSS3_CTL_306_DATA
+			DDRSS3_CTL_307_DATA
+			DDRSS3_CTL_308_DATA
+			DDRSS3_CTL_309_DATA
+			DDRSS3_CTL_310_DATA
+			DDRSS3_CTL_311_DATA
+			DDRSS3_CTL_312_DATA
+			DDRSS3_CTL_313_DATA
+			DDRSS3_CTL_314_DATA
+			DDRSS3_CTL_315_DATA
+			DDRSS3_CTL_316_DATA
+			DDRSS3_CTL_317_DATA
+			DDRSS3_CTL_318_DATA
+			DDRSS3_CTL_319_DATA
+			DDRSS3_CTL_320_DATA
+			DDRSS3_CTL_321_DATA
+			DDRSS3_CTL_322_DATA
+			DDRSS3_CTL_323_DATA
+			DDRSS3_CTL_324_DATA
+			DDRSS3_CTL_325_DATA
+			DDRSS3_CTL_326_DATA
+			DDRSS3_CTL_327_DATA
+			DDRSS3_CTL_328_DATA
+			DDRSS3_CTL_329_DATA
+			DDRSS3_CTL_330_DATA
+			DDRSS3_CTL_331_DATA
+			DDRSS3_CTL_332_DATA
+			DDRSS3_CTL_333_DATA
+			DDRSS3_CTL_334_DATA
+			DDRSS3_CTL_335_DATA
+			DDRSS3_CTL_336_DATA
+			DDRSS3_CTL_337_DATA
+			DDRSS3_CTL_338_DATA
+			DDRSS3_CTL_339_DATA
+			DDRSS3_CTL_340_DATA
+			DDRSS3_CTL_341_DATA
+			DDRSS3_CTL_342_DATA
+			DDRSS3_CTL_343_DATA
+			DDRSS3_CTL_344_DATA
+			DDRSS3_CTL_345_DATA
+			DDRSS3_CTL_346_DATA
+			DDRSS3_CTL_347_DATA
+			DDRSS3_CTL_348_DATA
+			DDRSS3_CTL_349_DATA
+			DDRSS3_CTL_350_DATA
+			DDRSS3_CTL_351_DATA
+			DDRSS3_CTL_352_DATA
+			DDRSS3_CTL_353_DATA
+			DDRSS3_CTL_354_DATA
+			DDRSS3_CTL_355_DATA
+			DDRSS3_CTL_356_DATA
+			DDRSS3_CTL_357_DATA
+			DDRSS3_CTL_358_DATA
+			DDRSS3_CTL_359_DATA
+			DDRSS3_CTL_360_DATA
+			DDRSS3_CTL_361_DATA
+			DDRSS3_CTL_362_DATA
+			DDRSS3_CTL_363_DATA
+			DDRSS3_CTL_364_DATA
+			DDRSS3_CTL_365_DATA
+			DDRSS3_CTL_366_DATA
+			DDRSS3_CTL_367_DATA
+			DDRSS3_CTL_368_DATA
+			DDRSS3_CTL_369_DATA
+			DDRSS3_CTL_370_DATA
+			DDRSS3_CTL_371_DATA
+			DDRSS3_CTL_372_DATA
+			DDRSS3_CTL_373_DATA
+			DDRSS3_CTL_374_DATA
+			DDRSS3_CTL_375_DATA
+			DDRSS3_CTL_376_DATA
+			DDRSS3_CTL_377_DATA
+			DDRSS3_CTL_378_DATA
+			DDRSS3_CTL_379_DATA
+			DDRSS3_CTL_380_DATA
+			DDRSS3_CTL_381_DATA
+			DDRSS3_CTL_382_DATA
+			DDRSS3_CTL_383_DATA
+			DDRSS3_CTL_384_DATA
+			DDRSS3_CTL_385_DATA
+			DDRSS3_CTL_386_DATA
+			DDRSS3_CTL_387_DATA
+			DDRSS3_CTL_388_DATA
+			DDRSS3_CTL_389_DATA
+			DDRSS3_CTL_390_DATA
+			DDRSS3_CTL_391_DATA
+			DDRSS3_CTL_392_DATA
+			DDRSS3_CTL_393_DATA
+			DDRSS3_CTL_394_DATA
+			DDRSS3_CTL_395_DATA
+			DDRSS3_CTL_396_DATA
+			DDRSS3_CTL_397_DATA
+			DDRSS3_CTL_398_DATA
+			DDRSS3_CTL_399_DATA
+			DDRSS3_CTL_400_DATA
+			DDRSS3_CTL_401_DATA
+			DDRSS3_CTL_402_DATA
+			DDRSS3_CTL_403_DATA
+			DDRSS3_CTL_404_DATA
+			DDRSS3_CTL_405_DATA
+			DDRSS3_CTL_406_DATA
+			DDRSS3_CTL_407_DATA
+			DDRSS3_CTL_408_DATA
+			DDRSS3_CTL_409_DATA
+			DDRSS3_CTL_410_DATA
+			DDRSS3_CTL_411_DATA
+			DDRSS3_CTL_412_DATA
+			DDRSS3_CTL_413_DATA
+			DDRSS3_CTL_414_DATA
+			DDRSS3_CTL_415_DATA
+			DDRSS3_CTL_416_DATA
+			DDRSS3_CTL_417_DATA
+			DDRSS3_CTL_418_DATA
+			DDRSS3_CTL_419_DATA
+			DDRSS3_CTL_420_DATA
+			DDRSS3_CTL_421_DATA
+			DDRSS3_CTL_422_DATA
+			DDRSS3_CTL_423_DATA
+			DDRSS3_CTL_424_DATA
+			DDRSS3_CTL_425_DATA
+			DDRSS3_CTL_426_DATA
+			DDRSS3_CTL_427_DATA
+			DDRSS3_CTL_428_DATA
+			DDRSS3_CTL_429_DATA
+			DDRSS3_CTL_430_DATA
+			DDRSS3_CTL_431_DATA
+			DDRSS3_CTL_432_DATA
+			DDRSS3_CTL_433_DATA
+			DDRSS3_CTL_434_DATA
+			DDRSS3_CTL_435_DATA
+			DDRSS3_CTL_436_DATA
+			DDRSS3_CTL_437_DATA
+			DDRSS3_CTL_438_DATA
+			DDRSS3_CTL_439_DATA
+			DDRSS3_CTL_440_DATA
+			DDRSS3_CTL_441_DATA
+			DDRSS3_CTL_442_DATA
+			DDRSS3_CTL_443_DATA
+			DDRSS3_CTL_444_DATA
+			DDRSS3_CTL_445_DATA
+			DDRSS3_CTL_446_DATA
+			DDRSS3_CTL_447_DATA
+			DDRSS3_CTL_448_DATA
+			DDRSS3_CTL_449_DATA
+			DDRSS3_CTL_450_DATA
+			DDRSS3_CTL_451_DATA
+			DDRSS3_CTL_452_DATA
+			DDRSS3_CTL_453_DATA
+			DDRSS3_CTL_454_DATA
+			DDRSS3_CTL_455_DATA
+			DDRSS3_CTL_456_DATA
+			DDRSS3_CTL_457_DATA
+			DDRSS3_CTL_458_DATA
+		>;
 
-			ti,pi-data = <
-				DDRSS3_PI_00_DATA
-				DDRSS3_PI_01_DATA
-				DDRSS3_PI_02_DATA
-				DDRSS3_PI_03_DATA
-				DDRSS3_PI_04_DATA
-				DDRSS3_PI_05_DATA
-				DDRSS3_PI_06_DATA
-				DDRSS3_PI_07_DATA
-				DDRSS3_PI_08_DATA
-				DDRSS3_PI_09_DATA
-				DDRSS3_PI_10_DATA
-				DDRSS3_PI_11_DATA
-				DDRSS3_PI_12_DATA
-				DDRSS3_PI_13_DATA
-				DDRSS3_PI_14_DATA
-				DDRSS3_PI_15_DATA
-				DDRSS3_PI_16_DATA
-				DDRSS3_PI_17_DATA
-				DDRSS3_PI_18_DATA
-				DDRSS3_PI_19_DATA
-				DDRSS3_PI_20_DATA
-				DDRSS3_PI_21_DATA
-				DDRSS3_PI_22_DATA
-				DDRSS3_PI_23_DATA
-				DDRSS3_PI_24_DATA
-				DDRSS3_PI_25_DATA
-				DDRSS3_PI_26_DATA
-				DDRSS3_PI_27_DATA
-				DDRSS3_PI_28_DATA
-				DDRSS3_PI_29_DATA
-				DDRSS3_PI_30_DATA
-				DDRSS3_PI_31_DATA
-				DDRSS3_PI_32_DATA
-				DDRSS3_PI_33_DATA
-				DDRSS3_PI_34_DATA
-				DDRSS3_PI_35_DATA
-				DDRSS3_PI_36_DATA
-				DDRSS3_PI_37_DATA
-				DDRSS3_PI_38_DATA
-				DDRSS3_PI_39_DATA
-				DDRSS3_PI_40_DATA
-				DDRSS3_PI_41_DATA
-				DDRSS3_PI_42_DATA
-				DDRSS3_PI_43_DATA
-				DDRSS3_PI_44_DATA
-				DDRSS3_PI_45_DATA
-				DDRSS3_PI_46_DATA
-				DDRSS3_PI_47_DATA
-				DDRSS3_PI_48_DATA
-				DDRSS3_PI_49_DATA
-				DDRSS3_PI_50_DATA
-				DDRSS3_PI_51_DATA
-				DDRSS3_PI_52_DATA
-				DDRSS3_PI_53_DATA
-				DDRSS3_PI_54_DATA
-				DDRSS3_PI_55_DATA
-				DDRSS3_PI_56_DATA
-				DDRSS3_PI_57_DATA
-				DDRSS3_PI_58_DATA
-				DDRSS3_PI_59_DATA
-				DDRSS3_PI_60_DATA
-				DDRSS3_PI_61_DATA
-				DDRSS3_PI_62_DATA
-				DDRSS3_PI_63_DATA
-				DDRSS3_PI_64_DATA
-				DDRSS3_PI_65_DATA
-				DDRSS3_PI_66_DATA
-				DDRSS3_PI_67_DATA
-				DDRSS3_PI_68_DATA
-				DDRSS3_PI_69_DATA
-				DDRSS3_PI_70_DATA
-				DDRSS3_PI_71_DATA
-				DDRSS3_PI_72_DATA
-				DDRSS3_PI_73_DATA
-				DDRSS3_PI_74_DATA
-				DDRSS3_PI_75_DATA
-				DDRSS3_PI_76_DATA
-				DDRSS3_PI_77_DATA
-				DDRSS3_PI_78_DATA
-				DDRSS3_PI_79_DATA
-				DDRSS3_PI_80_DATA
-				DDRSS3_PI_81_DATA
-				DDRSS3_PI_82_DATA
-				DDRSS3_PI_83_DATA
-				DDRSS3_PI_84_DATA
-				DDRSS3_PI_85_DATA
-				DDRSS3_PI_86_DATA
-				DDRSS3_PI_87_DATA
-				DDRSS3_PI_88_DATA
-				DDRSS3_PI_89_DATA
-				DDRSS3_PI_90_DATA
-				DDRSS3_PI_91_DATA
-				DDRSS3_PI_92_DATA
-				DDRSS3_PI_93_DATA
-				DDRSS3_PI_94_DATA
-				DDRSS3_PI_95_DATA
-				DDRSS3_PI_96_DATA
-				DDRSS3_PI_97_DATA
-				DDRSS3_PI_98_DATA
-				DDRSS3_PI_99_DATA
-				DDRSS3_PI_100_DATA
-				DDRSS3_PI_101_DATA
-				DDRSS3_PI_102_DATA
-				DDRSS3_PI_103_DATA
-				DDRSS3_PI_104_DATA
-				DDRSS3_PI_105_DATA
-				DDRSS3_PI_106_DATA
-				DDRSS3_PI_107_DATA
-				DDRSS3_PI_108_DATA
-				DDRSS3_PI_109_DATA
-				DDRSS3_PI_110_DATA
-				DDRSS3_PI_111_DATA
-				DDRSS3_PI_112_DATA
-				DDRSS3_PI_113_DATA
-				DDRSS3_PI_114_DATA
-				DDRSS3_PI_115_DATA
-				DDRSS3_PI_116_DATA
-				DDRSS3_PI_117_DATA
-				DDRSS3_PI_118_DATA
-				DDRSS3_PI_119_DATA
-				DDRSS3_PI_120_DATA
-				DDRSS3_PI_121_DATA
-				DDRSS3_PI_122_DATA
-				DDRSS3_PI_123_DATA
-				DDRSS3_PI_124_DATA
-				DDRSS3_PI_125_DATA
-				DDRSS3_PI_126_DATA
-				DDRSS3_PI_127_DATA
-				DDRSS3_PI_128_DATA
-				DDRSS3_PI_129_DATA
-				DDRSS3_PI_130_DATA
-				DDRSS3_PI_131_DATA
-				DDRSS3_PI_132_DATA
-				DDRSS3_PI_133_DATA
-				DDRSS3_PI_134_DATA
-				DDRSS3_PI_135_DATA
-				DDRSS3_PI_136_DATA
-				DDRSS3_PI_137_DATA
-				DDRSS3_PI_138_DATA
-				DDRSS3_PI_139_DATA
-				DDRSS3_PI_140_DATA
-				DDRSS3_PI_141_DATA
-				DDRSS3_PI_142_DATA
-				DDRSS3_PI_143_DATA
-				DDRSS3_PI_144_DATA
-				DDRSS3_PI_145_DATA
-				DDRSS3_PI_146_DATA
-				DDRSS3_PI_147_DATA
-				DDRSS3_PI_148_DATA
-				DDRSS3_PI_149_DATA
-				DDRSS3_PI_150_DATA
-				DDRSS3_PI_151_DATA
-				DDRSS3_PI_152_DATA
-				DDRSS3_PI_153_DATA
-				DDRSS3_PI_154_DATA
-				DDRSS3_PI_155_DATA
-				DDRSS3_PI_156_DATA
-				DDRSS3_PI_157_DATA
-				DDRSS3_PI_158_DATA
-				DDRSS3_PI_159_DATA
-				DDRSS3_PI_160_DATA
-				DDRSS3_PI_161_DATA
-				DDRSS3_PI_162_DATA
-				DDRSS3_PI_163_DATA
-				DDRSS3_PI_164_DATA
-				DDRSS3_PI_165_DATA
-				DDRSS3_PI_166_DATA
-				DDRSS3_PI_167_DATA
-				DDRSS3_PI_168_DATA
-				DDRSS3_PI_169_DATA
-				DDRSS3_PI_170_DATA
-				DDRSS3_PI_171_DATA
-				DDRSS3_PI_172_DATA
-				DDRSS3_PI_173_DATA
-				DDRSS3_PI_174_DATA
-				DDRSS3_PI_175_DATA
-				DDRSS3_PI_176_DATA
-				DDRSS3_PI_177_DATA
-				DDRSS3_PI_178_DATA
-				DDRSS3_PI_179_DATA
-				DDRSS3_PI_180_DATA
-				DDRSS3_PI_181_DATA
-				DDRSS3_PI_182_DATA
-				DDRSS3_PI_183_DATA
-				DDRSS3_PI_184_DATA
-				DDRSS3_PI_185_DATA
-				DDRSS3_PI_186_DATA
-				DDRSS3_PI_187_DATA
-				DDRSS3_PI_188_DATA
-				DDRSS3_PI_189_DATA
-				DDRSS3_PI_190_DATA
-				DDRSS3_PI_191_DATA
-				DDRSS3_PI_192_DATA
-				DDRSS3_PI_193_DATA
-				DDRSS3_PI_194_DATA
-				DDRSS3_PI_195_DATA
-				DDRSS3_PI_196_DATA
-				DDRSS3_PI_197_DATA
-				DDRSS3_PI_198_DATA
-				DDRSS3_PI_199_DATA
-				DDRSS3_PI_200_DATA
-				DDRSS3_PI_201_DATA
-				DDRSS3_PI_202_DATA
-				DDRSS3_PI_203_DATA
-				DDRSS3_PI_204_DATA
-				DDRSS3_PI_205_DATA
-				DDRSS3_PI_206_DATA
-				DDRSS3_PI_207_DATA
-				DDRSS3_PI_208_DATA
-				DDRSS3_PI_209_DATA
-				DDRSS3_PI_210_DATA
-				DDRSS3_PI_211_DATA
-				DDRSS3_PI_212_DATA
-				DDRSS3_PI_213_DATA
-				DDRSS3_PI_214_DATA
-				DDRSS3_PI_215_DATA
-				DDRSS3_PI_216_DATA
-				DDRSS3_PI_217_DATA
-				DDRSS3_PI_218_DATA
-				DDRSS3_PI_219_DATA
-				DDRSS3_PI_220_DATA
-				DDRSS3_PI_221_DATA
-				DDRSS3_PI_222_DATA
-				DDRSS3_PI_223_DATA
-				DDRSS3_PI_224_DATA
-				DDRSS3_PI_225_DATA
-				DDRSS3_PI_226_DATA
-				DDRSS3_PI_227_DATA
-				DDRSS3_PI_228_DATA
-				DDRSS3_PI_229_DATA
-				DDRSS3_PI_230_DATA
-				DDRSS3_PI_231_DATA
-				DDRSS3_PI_232_DATA
-				DDRSS3_PI_233_DATA
-				DDRSS3_PI_234_DATA
-				DDRSS3_PI_235_DATA
-				DDRSS3_PI_236_DATA
-				DDRSS3_PI_237_DATA
-				DDRSS3_PI_238_DATA
-				DDRSS3_PI_239_DATA
-				DDRSS3_PI_240_DATA
-				DDRSS3_PI_241_DATA
-				DDRSS3_PI_242_DATA
-				DDRSS3_PI_243_DATA
-				DDRSS3_PI_244_DATA
-				DDRSS3_PI_245_DATA
-				DDRSS3_PI_246_DATA
-				DDRSS3_PI_247_DATA
-				DDRSS3_PI_248_DATA
-				DDRSS3_PI_249_DATA
-				DDRSS3_PI_250_DATA
-				DDRSS3_PI_251_DATA
-				DDRSS3_PI_252_DATA
-				DDRSS3_PI_253_DATA
-				DDRSS3_PI_254_DATA
-				DDRSS3_PI_255_DATA
-				DDRSS3_PI_256_DATA
-				DDRSS3_PI_257_DATA
-				DDRSS3_PI_258_DATA
-				DDRSS3_PI_259_DATA
-				DDRSS3_PI_260_DATA
-				DDRSS3_PI_261_DATA
-				DDRSS3_PI_262_DATA
-				DDRSS3_PI_263_DATA
-				DDRSS3_PI_264_DATA
-				DDRSS3_PI_265_DATA
-				DDRSS3_PI_266_DATA
-				DDRSS3_PI_267_DATA
-				DDRSS3_PI_268_DATA
-				DDRSS3_PI_269_DATA
-				DDRSS3_PI_270_DATA
-				DDRSS3_PI_271_DATA
-				DDRSS3_PI_272_DATA
-				DDRSS3_PI_273_DATA
-				DDRSS3_PI_274_DATA
-				DDRSS3_PI_275_DATA
-				DDRSS3_PI_276_DATA
-				DDRSS3_PI_277_DATA
-				DDRSS3_PI_278_DATA
-				DDRSS3_PI_279_DATA
-				DDRSS3_PI_280_DATA
-				DDRSS3_PI_281_DATA
-				DDRSS3_PI_282_DATA
-				DDRSS3_PI_283_DATA
-				DDRSS3_PI_284_DATA
-				DDRSS3_PI_285_DATA
-				DDRSS3_PI_286_DATA
-				DDRSS3_PI_287_DATA
-				DDRSS3_PI_288_DATA
-				DDRSS3_PI_289_DATA
-				DDRSS3_PI_290_DATA
-				DDRSS3_PI_291_DATA
-				DDRSS3_PI_292_DATA
-				DDRSS3_PI_293_DATA
-				DDRSS3_PI_294_DATA
-				DDRSS3_PI_295_DATA
-				DDRSS3_PI_296_DATA
-				DDRSS3_PI_297_DATA
-				DDRSS3_PI_298_DATA
-				DDRSS3_PI_299_DATA
-			>;
+		ti,pi-data = <
+			DDRSS3_PI_00_DATA
+			DDRSS3_PI_01_DATA
+			DDRSS3_PI_02_DATA
+			DDRSS3_PI_03_DATA
+			DDRSS3_PI_04_DATA
+			DDRSS3_PI_05_DATA
+			DDRSS3_PI_06_DATA
+			DDRSS3_PI_07_DATA
+			DDRSS3_PI_08_DATA
+			DDRSS3_PI_09_DATA
+			DDRSS3_PI_10_DATA
+			DDRSS3_PI_11_DATA
+			DDRSS3_PI_12_DATA
+			DDRSS3_PI_13_DATA
+			DDRSS3_PI_14_DATA
+			DDRSS3_PI_15_DATA
+			DDRSS3_PI_16_DATA
+			DDRSS3_PI_17_DATA
+			DDRSS3_PI_18_DATA
+			DDRSS3_PI_19_DATA
+			DDRSS3_PI_20_DATA
+			DDRSS3_PI_21_DATA
+			DDRSS3_PI_22_DATA
+			DDRSS3_PI_23_DATA
+			DDRSS3_PI_24_DATA
+			DDRSS3_PI_25_DATA
+			DDRSS3_PI_26_DATA
+			DDRSS3_PI_27_DATA
+			DDRSS3_PI_28_DATA
+			DDRSS3_PI_29_DATA
+			DDRSS3_PI_30_DATA
+			DDRSS3_PI_31_DATA
+			DDRSS3_PI_32_DATA
+			DDRSS3_PI_33_DATA
+			DDRSS3_PI_34_DATA
+			DDRSS3_PI_35_DATA
+			DDRSS3_PI_36_DATA
+			DDRSS3_PI_37_DATA
+			DDRSS3_PI_38_DATA
+			DDRSS3_PI_39_DATA
+			DDRSS3_PI_40_DATA
+			DDRSS3_PI_41_DATA
+			DDRSS3_PI_42_DATA
+			DDRSS3_PI_43_DATA
+			DDRSS3_PI_44_DATA
+			DDRSS3_PI_45_DATA
+			DDRSS3_PI_46_DATA
+			DDRSS3_PI_47_DATA
+			DDRSS3_PI_48_DATA
+			DDRSS3_PI_49_DATA
+			DDRSS3_PI_50_DATA
+			DDRSS3_PI_51_DATA
+			DDRSS3_PI_52_DATA
+			DDRSS3_PI_53_DATA
+			DDRSS3_PI_54_DATA
+			DDRSS3_PI_55_DATA
+			DDRSS3_PI_56_DATA
+			DDRSS3_PI_57_DATA
+			DDRSS3_PI_58_DATA
+			DDRSS3_PI_59_DATA
+			DDRSS3_PI_60_DATA
+			DDRSS3_PI_61_DATA
+			DDRSS3_PI_62_DATA
+			DDRSS3_PI_63_DATA
+			DDRSS3_PI_64_DATA
+			DDRSS3_PI_65_DATA
+			DDRSS3_PI_66_DATA
+			DDRSS3_PI_67_DATA
+			DDRSS3_PI_68_DATA
+			DDRSS3_PI_69_DATA
+			DDRSS3_PI_70_DATA
+			DDRSS3_PI_71_DATA
+			DDRSS3_PI_72_DATA
+			DDRSS3_PI_73_DATA
+			DDRSS3_PI_74_DATA
+			DDRSS3_PI_75_DATA
+			DDRSS3_PI_76_DATA
+			DDRSS3_PI_77_DATA
+			DDRSS3_PI_78_DATA
+			DDRSS3_PI_79_DATA
+			DDRSS3_PI_80_DATA
+			DDRSS3_PI_81_DATA
+			DDRSS3_PI_82_DATA
+			DDRSS3_PI_83_DATA
+			DDRSS3_PI_84_DATA
+			DDRSS3_PI_85_DATA
+			DDRSS3_PI_86_DATA
+			DDRSS3_PI_87_DATA
+			DDRSS3_PI_88_DATA
+			DDRSS3_PI_89_DATA
+			DDRSS3_PI_90_DATA
+			DDRSS3_PI_91_DATA
+			DDRSS3_PI_92_DATA
+			DDRSS3_PI_93_DATA
+			DDRSS3_PI_94_DATA
+			DDRSS3_PI_95_DATA
+			DDRSS3_PI_96_DATA
+			DDRSS3_PI_97_DATA
+			DDRSS3_PI_98_DATA
+			DDRSS3_PI_99_DATA
+			DDRSS3_PI_100_DATA
+			DDRSS3_PI_101_DATA
+			DDRSS3_PI_102_DATA
+			DDRSS3_PI_103_DATA
+			DDRSS3_PI_104_DATA
+			DDRSS3_PI_105_DATA
+			DDRSS3_PI_106_DATA
+			DDRSS3_PI_107_DATA
+			DDRSS3_PI_108_DATA
+			DDRSS3_PI_109_DATA
+			DDRSS3_PI_110_DATA
+			DDRSS3_PI_111_DATA
+			DDRSS3_PI_112_DATA
+			DDRSS3_PI_113_DATA
+			DDRSS3_PI_114_DATA
+			DDRSS3_PI_115_DATA
+			DDRSS3_PI_116_DATA
+			DDRSS3_PI_117_DATA
+			DDRSS3_PI_118_DATA
+			DDRSS3_PI_119_DATA
+			DDRSS3_PI_120_DATA
+			DDRSS3_PI_121_DATA
+			DDRSS3_PI_122_DATA
+			DDRSS3_PI_123_DATA
+			DDRSS3_PI_124_DATA
+			DDRSS3_PI_125_DATA
+			DDRSS3_PI_126_DATA
+			DDRSS3_PI_127_DATA
+			DDRSS3_PI_128_DATA
+			DDRSS3_PI_129_DATA
+			DDRSS3_PI_130_DATA
+			DDRSS3_PI_131_DATA
+			DDRSS3_PI_132_DATA
+			DDRSS3_PI_133_DATA
+			DDRSS3_PI_134_DATA
+			DDRSS3_PI_135_DATA
+			DDRSS3_PI_136_DATA
+			DDRSS3_PI_137_DATA
+			DDRSS3_PI_138_DATA
+			DDRSS3_PI_139_DATA
+			DDRSS3_PI_140_DATA
+			DDRSS3_PI_141_DATA
+			DDRSS3_PI_142_DATA
+			DDRSS3_PI_143_DATA
+			DDRSS3_PI_144_DATA
+			DDRSS3_PI_145_DATA
+			DDRSS3_PI_146_DATA
+			DDRSS3_PI_147_DATA
+			DDRSS3_PI_148_DATA
+			DDRSS3_PI_149_DATA
+			DDRSS3_PI_150_DATA
+			DDRSS3_PI_151_DATA
+			DDRSS3_PI_152_DATA
+			DDRSS3_PI_153_DATA
+			DDRSS3_PI_154_DATA
+			DDRSS3_PI_155_DATA
+			DDRSS3_PI_156_DATA
+			DDRSS3_PI_157_DATA
+			DDRSS3_PI_158_DATA
+			DDRSS3_PI_159_DATA
+			DDRSS3_PI_160_DATA
+			DDRSS3_PI_161_DATA
+			DDRSS3_PI_162_DATA
+			DDRSS3_PI_163_DATA
+			DDRSS3_PI_164_DATA
+			DDRSS3_PI_165_DATA
+			DDRSS3_PI_166_DATA
+			DDRSS3_PI_167_DATA
+			DDRSS3_PI_168_DATA
+			DDRSS3_PI_169_DATA
+			DDRSS3_PI_170_DATA
+			DDRSS3_PI_171_DATA
+			DDRSS3_PI_172_DATA
+			DDRSS3_PI_173_DATA
+			DDRSS3_PI_174_DATA
+			DDRSS3_PI_175_DATA
+			DDRSS3_PI_176_DATA
+			DDRSS3_PI_177_DATA
+			DDRSS3_PI_178_DATA
+			DDRSS3_PI_179_DATA
+			DDRSS3_PI_180_DATA
+			DDRSS3_PI_181_DATA
+			DDRSS3_PI_182_DATA
+			DDRSS3_PI_183_DATA
+			DDRSS3_PI_184_DATA
+			DDRSS3_PI_185_DATA
+			DDRSS3_PI_186_DATA
+			DDRSS3_PI_187_DATA
+			DDRSS3_PI_188_DATA
+			DDRSS3_PI_189_DATA
+			DDRSS3_PI_190_DATA
+			DDRSS3_PI_191_DATA
+			DDRSS3_PI_192_DATA
+			DDRSS3_PI_193_DATA
+			DDRSS3_PI_194_DATA
+			DDRSS3_PI_195_DATA
+			DDRSS3_PI_196_DATA
+			DDRSS3_PI_197_DATA
+			DDRSS3_PI_198_DATA
+			DDRSS3_PI_199_DATA
+			DDRSS3_PI_200_DATA
+			DDRSS3_PI_201_DATA
+			DDRSS3_PI_202_DATA
+			DDRSS3_PI_203_DATA
+			DDRSS3_PI_204_DATA
+			DDRSS3_PI_205_DATA
+			DDRSS3_PI_206_DATA
+			DDRSS3_PI_207_DATA
+			DDRSS3_PI_208_DATA
+			DDRSS3_PI_209_DATA
+			DDRSS3_PI_210_DATA
+			DDRSS3_PI_211_DATA
+			DDRSS3_PI_212_DATA
+			DDRSS3_PI_213_DATA
+			DDRSS3_PI_214_DATA
+			DDRSS3_PI_215_DATA
+			DDRSS3_PI_216_DATA
+			DDRSS3_PI_217_DATA
+			DDRSS3_PI_218_DATA
+			DDRSS3_PI_219_DATA
+			DDRSS3_PI_220_DATA
+			DDRSS3_PI_221_DATA
+			DDRSS3_PI_222_DATA
+			DDRSS3_PI_223_DATA
+			DDRSS3_PI_224_DATA
+			DDRSS3_PI_225_DATA
+			DDRSS3_PI_226_DATA
+			DDRSS3_PI_227_DATA
+			DDRSS3_PI_228_DATA
+			DDRSS3_PI_229_DATA
+			DDRSS3_PI_230_DATA
+			DDRSS3_PI_231_DATA
+			DDRSS3_PI_232_DATA
+			DDRSS3_PI_233_DATA
+			DDRSS3_PI_234_DATA
+			DDRSS3_PI_235_DATA
+			DDRSS3_PI_236_DATA
+			DDRSS3_PI_237_DATA
+			DDRSS3_PI_238_DATA
+			DDRSS3_PI_239_DATA
+			DDRSS3_PI_240_DATA
+			DDRSS3_PI_241_DATA
+			DDRSS3_PI_242_DATA
+			DDRSS3_PI_243_DATA
+			DDRSS3_PI_244_DATA
+			DDRSS3_PI_245_DATA
+			DDRSS3_PI_246_DATA
+			DDRSS3_PI_247_DATA
+			DDRSS3_PI_248_DATA
+			DDRSS3_PI_249_DATA
+			DDRSS3_PI_250_DATA
+			DDRSS3_PI_251_DATA
+			DDRSS3_PI_252_DATA
+			DDRSS3_PI_253_DATA
+			DDRSS3_PI_254_DATA
+			DDRSS3_PI_255_DATA
+			DDRSS3_PI_256_DATA
+			DDRSS3_PI_257_DATA
+			DDRSS3_PI_258_DATA
+			DDRSS3_PI_259_DATA
+			DDRSS3_PI_260_DATA
+			DDRSS3_PI_261_DATA
+			DDRSS3_PI_262_DATA
+			DDRSS3_PI_263_DATA
+			DDRSS3_PI_264_DATA
+			DDRSS3_PI_265_DATA
+			DDRSS3_PI_266_DATA
+			DDRSS3_PI_267_DATA
+			DDRSS3_PI_268_DATA
+			DDRSS3_PI_269_DATA
+			DDRSS3_PI_270_DATA
+			DDRSS3_PI_271_DATA
+			DDRSS3_PI_272_DATA
+			DDRSS3_PI_273_DATA
+			DDRSS3_PI_274_DATA
+			DDRSS3_PI_275_DATA
+			DDRSS3_PI_276_DATA
+			DDRSS3_PI_277_DATA
+			DDRSS3_PI_278_DATA
+			DDRSS3_PI_279_DATA
+			DDRSS3_PI_280_DATA
+			DDRSS3_PI_281_DATA
+			DDRSS3_PI_282_DATA
+			DDRSS3_PI_283_DATA
+			DDRSS3_PI_284_DATA
+			DDRSS3_PI_285_DATA
+			DDRSS3_PI_286_DATA
+			DDRSS3_PI_287_DATA
+			DDRSS3_PI_288_DATA
+			DDRSS3_PI_289_DATA
+			DDRSS3_PI_290_DATA
+			DDRSS3_PI_291_DATA
+			DDRSS3_PI_292_DATA
+			DDRSS3_PI_293_DATA
+			DDRSS3_PI_294_DATA
+			DDRSS3_PI_295_DATA
+			DDRSS3_PI_296_DATA
+			DDRSS3_PI_297_DATA
+			DDRSS3_PI_298_DATA
+			DDRSS3_PI_299_DATA
+		>;
 
-			ti,phy-data = <
-				DDRSS3_PHY_00_DATA
-				DDRSS3_PHY_01_DATA
-				DDRSS3_PHY_02_DATA
-				DDRSS3_PHY_03_DATA
-				DDRSS3_PHY_04_DATA
-				DDRSS3_PHY_05_DATA
-				DDRSS3_PHY_06_DATA
-				DDRSS3_PHY_07_DATA
-				DDRSS3_PHY_08_DATA
-				DDRSS3_PHY_09_DATA
-				DDRSS3_PHY_10_DATA
-				DDRSS3_PHY_11_DATA
-				DDRSS3_PHY_12_DATA
-				DDRSS3_PHY_13_DATA
-				DDRSS3_PHY_14_DATA
-				DDRSS3_PHY_15_DATA
-				DDRSS3_PHY_16_DATA
-				DDRSS3_PHY_17_DATA
-				DDRSS3_PHY_18_DATA
-				DDRSS3_PHY_19_DATA
-				DDRSS3_PHY_20_DATA
-				DDRSS3_PHY_21_DATA
-				DDRSS3_PHY_22_DATA
-				DDRSS3_PHY_23_DATA
-				DDRSS3_PHY_24_DATA
-				DDRSS3_PHY_25_DATA
-				DDRSS3_PHY_26_DATA
-				DDRSS3_PHY_27_DATA
-				DDRSS3_PHY_28_DATA
-				DDRSS3_PHY_29_DATA
-				DDRSS3_PHY_30_DATA
-				DDRSS3_PHY_31_DATA
-				DDRSS3_PHY_32_DATA
-				DDRSS3_PHY_33_DATA
-				DDRSS3_PHY_34_DATA
-				DDRSS3_PHY_35_DATA
-				DDRSS3_PHY_36_DATA
-				DDRSS3_PHY_37_DATA
-				DDRSS3_PHY_38_DATA
-				DDRSS3_PHY_39_DATA
-				DDRSS3_PHY_40_DATA
-				DDRSS3_PHY_41_DATA
-				DDRSS3_PHY_42_DATA
-				DDRSS3_PHY_43_DATA
-				DDRSS3_PHY_44_DATA
-				DDRSS3_PHY_45_DATA
-				DDRSS3_PHY_46_DATA
-				DDRSS3_PHY_47_DATA
-				DDRSS3_PHY_48_DATA
-				DDRSS3_PHY_49_DATA
-				DDRSS3_PHY_50_DATA
-				DDRSS3_PHY_51_DATA
-				DDRSS3_PHY_52_DATA
-				DDRSS3_PHY_53_DATA
-				DDRSS3_PHY_54_DATA
-				DDRSS3_PHY_55_DATA
-				DDRSS3_PHY_56_DATA
-				DDRSS3_PHY_57_DATA
-				DDRSS3_PHY_58_DATA
-				DDRSS3_PHY_59_DATA
-				DDRSS3_PHY_60_DATA
-				DDRSS3_PHY_61_DATA
-				DDRSS3_PHY_62_DATA
-				DDRSS3_PHY_63_DATA
-				DDRSS3_PHY_64_DATA
-				DDRSS3_PHY_65_DATA
-				DDRSS3_PHY_66_DATA
-				DDRSS3_PHY_67_DATA
-				DDRSS3_PHY_68_DATA
-				DDRSS3_PHY_69_DATA
-				DDRSS3_PHY_70_DATA
-				DDRSS3_PHY_71_DATA
-				DDRSS3_PHY_72_DATA
-				DDRSS3_PHY_73_DATA
-				DDRSS3_PHY_74_DATA
-				DDRSS3_PHY_75_DATA
-				DDRSS3_PHY_76_DATA
-				DDRSS3_PHY_77_DATA
-				DDRSS3_PHY_78_DATA
-				DDRSS3_PHY_79_DATA
-				DDRSS3_PHY_80_DATA
-				DDRSS3_PHY_81_DATA
-				DDRSS3_PHY_82_DATA
-				DDRSS3_PHY_83_DATA
-				DDRSS3_PHY_84_DATA
-				DDRSS3_PHY_85_DATA
-				DDRSS3_PHY_86_DATA
-				DDRSS3_PHY_87_DATA
-				DDRSS3_PHY_88_DATA
-				DDRSS3_PHY_89_DATA
-				DDRSS3_PHY_90_DATA
-				DDRSS3_PHY_91_DATA
-				DDRSS3_PHY_92_DATA
-				DDRSS3_PHY_93_DATA
-				DDRSS3_PHY_94_DATA
-				DDRSS3_PHY_95_DATA
-				DDRSS3_PHY_96_DATA
-				DDRSS3_PHY_97_DATA
-				DDRSS3_PHY_98_DATA
-				DDRSS3_PHY_99_DATA
-				DDRSS3_PHY_100_DATA
-				DDRSS3_PHY_101_DATA
-				DDRSS3_PHY_102_DATA
-				DDRSS3_PHY_103_DATA
-				DDRSS3_PHY_104_DATA
-				DDRSS3_PHY_105_DATA
-				DDRSS3_PHY_106_DATA
-				DDRSS3_PHY_107_DATA
-				DDRSS3_PHY_108_DATA
-				DDRSS3_PHY_109_DATA
-				DDRSS3_PHY_110_DATA
-				DDRSS3_PHY_111_DATA
-				DDRSS3_PHY_112_DATA
-				DDRSS3_PHY_113_DATA
-				DDRSS3_PHY_114_DATA
-				DDRSS3_PHY_115_DATA
-				DDRSS3_PHY_116_DATA
-				DDRSS3_PHY_117_DATA
-				DDRSS3_PHY_118_DATA
-				DDRSS3_PHY_119_DATA
-				DDRSS3_PHY_120_DATA
-				DDRSS3_PHY_121_DATA
-				DDRSS3_PHY_122_DATA
-				DDRSS3_PHY_123_DATA
-				DDRSS3_PHY_124_DATA
-				DDRSS3_PHY_125_DATA
-				DDRSS3_PHY_126_DATA
-				DDRSS3_PHY_127_DATA
-				DDRSS3_PHY_128_DATA
-				DDRSS3_PHY_129_DATA
-				DDRSS3_PHY_130_DATA
-				DDRSS3_PHY_131_DATA
-				DDRSS3_PHY_132_DATA
-				DDRSS3_PHY_133_DATA
-				DDRSS3_PHY_134_DATA
-				DDRSS3_PHY_135_DATA
-				DDRSS3_PHY_136_DATA
-				DDRSS3_PHY_137_DATA
-				DDRSS3_PHY_138_DATA
-				DDRSS3_PHY_139_DATA
-				DDRSS3_PHY_140_DATA
-				DDRSS3_PHY_141_DATA
-				DDRSS3_PHY_142_DATA
-				DDRSS3_PHY_143_DATA
-				DDRSS3_PHY_144_DATA
-				DDRSS3_PHY_145_DATA
-				DDRSS3_PHY_146_DATA
-				DDRSS3_PHY_147_DATA
-				DDRSS3_PHY_148_DATA
-				DDRSS3_PHY_149_DATA
-				DDRSS3_PHY_150_DATA
-				DDRSS3_PHY_151_DATA
-				DDRSS3_PHY_152_DATA
-				DDRSS3_PHY_153_DATA
-				DDRSS3_PHY_154_DATA
-				DDRSS3_PHY_155_DATA
-				DDRSS3_PHY_156_DATA
-				DDRSS3_PHY_157_DATA
-				DDRSS3_PHY_158_DATA
-				DDRSS3_PHY_159_DATA
-				DDRSS3_PHY_160_DATA
-				DDRSS3_PHY_161_DATA
-				DDRSS3_PHY_162_DATA
-				DDRSS3_PHY_163_DATA
-				DDRSS3_PHY_164_DATA
-				DDRSS3_PHY_165_DATA
-				DDRSS3_PHY_166_DATA
-				DDRSS3_PHY_167_DATA
-				DDRSS3_PHY_168_DATA
-				DDRSS3_PHY_169_DATA
-				DDRSS3_PHY_170_DATA
-				DDRSS3_PHY_171_DATA
-				DDRSS3_PHY_172_DATA
-				DDRSS3_PHY_173_DATA
-				DDRSS3_PHY_174_DATA
-				DDRSS3_PHY_175_DATA
-				DDRSS3_PHY_176_DATA
-				DDRSS3_PHY_177_DATA
-				DDRSS3_PHY_178_DATA
-				DDRSS3_PHY_179_DATA
-				DDRSS3_PHY_180_DATA
-				DDRSS3_PHY_181_DATA
-				DDRSS3_PHY_182_DATA
-				DDRSS3_PHY_183_DATA
-				DDRSS3_PHY_184_DATA
-				DDRSS3_PHY_185_DATA
-				DDRSS3_PHY_186_DATA
-				DDRSS3_PHY_187_DATA
-				DDRSS3_PHY_188_DATA
-				DDRSS3_PHY_189_DATA
-				DDRSS3_PHY_190_DATA
-				DDRSS3_PHY_191_DATA
-				DDRSS3_PHY_192_DATA
-				DDRSS3_PHY_193_DATA
-				DDRSS3_PHY_194_DATA
-				DDRSS3_PHY_195_DATA
-				DDRSS3_PHY_196_DATA
-				DDRSS3_PHY_197_DATA
-				DDRSS3_PHY_198_DATA
-				DDRSS3_PHY_199_DATA
-				DDRSS3_PHY_200_DATA
-				DDRSS3_PHY_201_DATA
-				DDRSS3_PHY_202_DATA
-				DDRSS3_PHY_203_DATA
-				DDRSS3_PHY_204_DATA
-				DDRSS3_PHY_205_DATA
-				DDRSS3_PHY_206_DATA
-				DDRSS3_PHY_207_DATA
-				DDRSS3_PHY_208_DATA
-				DDRSS3_PHY_209_DATA
-				DDRSS3_PHY_210_DATA
-				DDRSS3_PHY_211_DATA
-				DDRSS3_PHY_212_DATA
-				DDRSS3_PHY_213_DATA
-				DDRSS3_PHY_214_DATA
-				DDRSS3_PHY_215_DATA
-				DDRSS3_PHY_216_DATA
-				DDRSS3_PHY_217_DATA
-				DDRSS3_PHY_218_DATA
-				DDRSS3_PHY_219_DATA
-				DDRSS3_PHY_220_DATA
-				DDRSS3_PHY_221_DATA
-				DDRSS3_PHY_222_DATA
-				DDRSS3_PHY_223_DATA
-				DDRSS3_PHY_224_DATA
-				DDRSS3_PHY_225_DATA
-				DDRSS3_PHY_226_DATA
-				DDRSS3_PHY_227_DATA
-				DDRSS3_PHY_228_DATA
-				DDRSS3_PHY_229_DATA
-				DDRSS3_PHY_230_DATA
-				DDRSS3_PHY_231_DATA
-				DDRSS3_PHY_232_DATA
-				DDRSS3_PHY_233_DATA
-				DDRSS3_PHY_234_DATA
-				DDRSS3_PHY_235_DATA
-				DDRSS3_PHY_236_DATA
-				DDRSS3_PHY_237_DATA
-				DDRSS3_PHY_238_DATA
-				DDRSS3_PHY_239_DATA
-				DDRSS3_PHY_240_DATA
-				DDRSS3_PHY_241_DATA
-				DDRSS3_PHY_242_DATA
-				DDRSS3_PHY_243_DATA
-				DDRSS3_PHY_244_DATA
-				DDRSS3_PHY_245_DATA
-				DDRSS3_PHY_246_DATA
-				DDRSS3_PHY_247_DATA
-				DDRSS3_PHY_248_DATA
-				DDRSS3_PHY_249_DATA
-				DDRSS3_PHY_250_DATA
-				DDRSS3_PHY_251_DATA
-				DDRSS3_PHY_252_DATA
-				DDRSS3_PHY_253_DATA
-				DDRSS3_PHY_254_DATA
-				DDRSS3_PHY_255_DATA
-				DDRSS3_PHY_256_DATA
-				DDRSS3_PHY_257_DATA
-				DDRSS3_PHY_258_DATA
-				DDRSS3_PHY_259_DATA
-				DDRSS3_PHY_260_DATA
-				DDRSS3_PHY_261_DATA
-				DDRSS3_PHY_262_DATA
-				DDRSS3_PHY_263_DATA
-				DDRSS3_PHY_264_DATA
-				DDRSS3_PHY_265_DATA
-				DDRSS3_PHY_266_DATA
-				DDRSS3_PHY_267_DATA
-				DDRSS3_PHY_268_DATA
-				DDRSS3_PHY_269_DATA
-				DDRSS3_PHY_270_DATA
-				DDRSS3_PHY_271_DATA
-				DDRSS3_PHY_272_DATA
-				DDRSS3_PHY_273_DATA
-				DDRSS3_PHY_274_DATA
-				DDRSS3_PHY_275_DATA
-				DDRSS3_PHY_276_DATA
-				DDRSS3_PHY_277_DATA
-				DDRSS3_PHY_278_DATA
-				DDRSS3_PHY_279_DATA
-				DDRSS3_PHY_280_DATA
-				DDRSS3_PHY_281_DATA
-				DDRSS3_PHY_282_DATA
-				DDRSS3_PHY_283_DATA
-				DDRSS3_PHY_284_DATA
-				DDRSS3_PHY_285_DATA
-				DDRSS3_PHY_286_DATA
-				DDRSS3_PHY_287_DATA
-				DDRSS3_PHY_288_DATA
-				DDRSS3_PHY_289_DATA
-				DDRSS3_PHY_290_DATA
-				DDRSS3_PHY_291_DATA
-				DDRSS3_PHY_292_DATA
-				DDRSS3_PHY_293_DATA
-				DDRSS3_PHY_294_DATA
-				DDRSS3_PHY_295_DATA
-				DDRSS3_PHY_296_DATA
-				DDRSS3_PHY_297_DATA
-				DDRSS3_PHY_298_DATA
-				DDRSS3_PHY_299_DATA
-				DDRSS3_PHY_300_DATA
-				DDRSS3_PHY_301_DATA
-				DDRSS3_PHY_302_DATA
-				DDRSS3_PHY_303_DATA
-				DDRSS3_PHY_304_DATA
-				DDRSS3_PHY_305_DATA
-				DDRSS3_PHY_306_DATA
-				DDRSS3_PHY_307_DATA
-				DDRSS3_PHY_308_DATA
-				DDRSS3_PHY_309_DATA
-				DDRSS3_PHY_310_DATA
-				DDRSS3_PHY_311_DATA
-				DDRSS3_PHY_312_DATA
-				DDRSS3_PHY_313_DATA
-				DDRSS3_PHY_314_DATA
-				DDRSS3_PHY_315_DATA
-				DDRSS3_PHY_316_DATA
-				DDRSS3_PHY_317_DATA
-				DDRSS3_PHY_318_DATA
-				DDRSS3_PHY_319_DATA
-				DDRSS3_PHY_320_DATA
-				DDRSS3_PHY_321_DATA
-				DDRSS3_PHY_322_DATA
-				DDRSS3_PHY_323_DATA
-				DDRSS3_PHY_324_DATA
-				DDRSS3_PHY_325_DATA
-				DDRSS3_PHY_326_DATA
-				DDRSS3_PHY_327_DATA
-				DDRSS3_PHY_328_DATA
-				DDRSS3_PHY_329_DATA
-				DDRSS3_PHY_330_DATA
-				DDRSS3_PHY_331_DATA
-				DDRSS3_PHY_332_DATA
-				DDRSS3_PHY_333_DATA
-				DDRSS3_PHY_334_DATA
-				DDRSS3_PHY_335_DATA
-				DDRSS3_PHY_336_DATA
-				DDRSS3_PHY_337_DATA
-				DDRSS3_PHY_338_DATA
-				DDRSS3_PHY_339_DATA
-				DDRSS3_PHY_340_DATA
-				DDRSS3_PHY_341_DATA
-				DDRSS3_PHY_342_DATA
-				DDRSS3_PHY_343_DATA
-				DDRSS3_PHY_344_DATA
-				DDRSS3_PHY_345_DATA
-				DDRSS3_PHY_346_DATA
-				DDRSS3_PHY_347_DATA
-				DDRSS3_PHY_348_DATA
-				DDRSS3_PHY_349_DATA
-				DDRSS3_PHY_350_DATA
-				DDRSS3_PHY_351_DATA
-				DDRSS3_PHY_352_DATA
-				DDRSS3_PHY_353_DATA
-				DDRSS3_PHY_354_DATA
-				DDRSS3_PHY_355_DATA
-				DDRSS3_PHY_356_DATA
-				DDRSS3_PHY_357_DATA
-				DDRSS3_PHY_358_DATA
-				DDRSS3_PHY_359_DATA
-				DDRSS3_PHY_360_DATA
-				DDRSS3_PHY_361_DATA
-				DDRSS3_PHY_362_DATA
-				DDRSS3_PHY_363_DATA
-				DDRSS3_PHY_364_DATA
-				DDRSS3_PHY_365_DATA
-				DDRSS3_PHY_366_DATA
-				DDRSS3_PHY_367_DATA
-				DDRSS3_PHY_368_DATA
-				DDRSS3_PHY_369_DATA
-				DDRSS3_PHY_370_DATA
-				DDRSS3_PHY_371_DATA
-				DDRSS3_PHY_372_DATA
-				DDRSS3_PHY_373_DATA
-				DDRSS3_PHY_374_DATA
-				DDRSS3_PHY_375_DATA
-				DDRSS3_PHY_376_DATA
-				DDRSS3_PHY_377_DATA
-				DDRSS3_PHY_378_DATA
-				DDRSS3_PHY_379_DATA
-				DDRSS3_PHY_380_DATA
-				DDRSS3_PHY_381_DATA
-				DDRSS3_PHY_382_DATA
-				DDRSS3_PHY_383_DATA
-				DDRSS3_PHY_384_DATA
-				DDRSS3_PHY_385_DATA
-				DDRSS3_PHY_386_DATA
-				DDRSS3_PHY_387_DATA
-				DDRSS3_PHY_388_DATA
-				DDRSS3_PHY_389_DATA
-				DDRSS3_PHY_390_DATA
-				DDRSS3_PHY_391_DATA
-				DDRSS3_PHY_392_DATA
-				DDRSS3_PHY_393_DATA
-				DDRSS3_PHY_394_DATA
-				DDRSS3_PHY_395_DATA
-				DDRSS3_PHY_396_DATA
-				DDRSS3_PHY_397_DATA
-				DDRSS3_PHY_398_DATA
-				DDRSS3_PHY_399_DATA
-				DDRSS3_PHY_400_DATA
-				DDRSS3_PHY_401_DATA
-				DDRSS3_PHY_402_DATA
-				DDRSS3_PHY_403_DATA
-				DDRSS3_PHY_404_DATA
-				DDRSS3_PHY_405_DATA
-				DDRSS3_PHY_406_DATA
-				DDRSS3_PHY_407_DATA
-				DDRSS3_PHY_408_DATA
-				DDRSS3_PHY_409_DATA
-				DDRSS3_PHY_410_DATA
-				DDRSS3_PHY_411_DATA
-				DDRSS3_PHY_412_DATA
-				DDRSS3_PHY_413_DATA
-				DDRSS3_PHY_414_DATA
-				DDRSS3_PHY_415_DATA
-				DDRSS3_PHY_416_DATA
-				DDRSS3_PHY_417_DATA
-				DDRSS3_PHY_418_DATA
-				DDRSS3_PHY_419_DATA
-				DDRSS3_PHY_420_DATA
-				DDRSS3_PHY_421_DATA
-				DDRSS3_PHY_422_DATA
-				DDRSS3_PHY_423_DATA
-				DDRSS3_PHY_424_DATA
-				DDRSS3_PHY_425_DATA
-				DDRSS3_PHY_426_DATA
-				DDRSS3_PHY_427_DATA
-				DDRSS3_PHY_428_DATA
-				DDRSS3_PHY_429_DATA
-				DDRSS3_PHY_430_DATA
-				DDRSS3_PHY_431_DATA
-				DDRSS3_PHY_432_DATA
-				DDRSS3_PHY_433_DATA
-				DDRSS3_PHY_434_DATA
-				DDRSS3_PHY_435_DATA
-				DDRSS3_PHY_436_DATA
-				DDRSS3_PHY_437_DATA
-				DDRSS3_PHY_438_DATA
-				DDRSS3_PHY_439_DATA
-				DDRSS3_PHY_440_DATA
-				DDRSS3_PHY_441_DATA
-				DDRSS3_PHY_442_DATA
-				DDRSS3_PHY_443_DATA
-				DDRSS3_PHY_444_DATA
-				DDRSS3_PHY_445_DATA
-				DDRSS3_PHY_446_DATA
-				DDRSS3_PHY_447_DATA
-				DDRSS3_PHY_448_DATA
-				DDRSS3_PHY_449_DATA
-				DDRSS3_PHY_450_DATA
-				DDRSS3_PHY_451_DATA
-				DDRSS3_PHY_452_DATA
-				DDRSS3_PHY_453_DATA
-				DDRSS3_PHY_454_DATA
-				DDRSS3_PHY_455_DATA
-				DDRSS3_PHY_456_DATA
-				DDRSS3_PHY_457_DATA
-				DDRSS3_PHY_458_DATA
-				DDRSS3_PHY_459_DATA
-				DDRSS3_PHY_460_DATA
-				DDRSS3_PHY_461_DATA
-				DDRSS3_PHY_462_DATA
-				DDRSS3_PHY_463_DATA
-				DDRSS3_PHY_464_DATA
-				DDRSS3_PHY_465_DATA
-				DDRSS3_PHY_466_DATA
-				DDRSS3_PHY_467_DATA
-				DDRSS3_PHY_468_DATA
-				DDRSS3_PHY_469_DATA
-				DDRSS3_PHY_470_DATA
-				DDRSS3_PHY_471_DATA
-				DDRSS3_PHY_472_DATA
-				DDRSS3_PHY_473_DATA
-				DDRSS3_PHY_474_DATA
-				DDRSS3_PHY_475_DATA
-				DDRSS3_PHY_476_DATA
-				DDRSS3_PHY_477_DATA
-				DDRSS3_PHY_478_DATA
-				DDRSS3_PHY_479_DATA
-				DDRSS3_PHY_480_DATA
-				DDRSS3_PHY_481_DATA
-				DDRSS3_PHY_482_DATA
-				DDRSS3_PHY_483_DATA
-				DDRSS3_PHY_484_DATA
-				DDRSS3_PHY_485_DATA
-				DDRSS3_PHY_486_DATA
-				DDRSS3_PHY_487_DATA
-				DDRSS3_PHY_488_DATA
-				DDRSS3_PHY_489_DATA
-				DDRSS3_PHY_490_DATA
-				DDRSS3_PHY_491_DATA
-				DDRSS3_PHY_492_DATA
-				DDRSS3_PHY_493_DATA
-				DDRSS3_PHY_494_DATA
-				DDRSS3_PHY_495_DATA
-				DDRSS3_PHY_496_DATA
-				DDRSS3_PHY_497_DATA
-				DDRSS3_PHY_498_DATA
-				DDRSS3_PHY_499_DATA
-				DDRSS3_PHY_500_DATA
-				DDRSS3_PHY_501_DATA
-				DDRSS3_PHY_502_DATA
-				DDRSS3_PHY_503_DATA
-				DDRSS3_PHY_504_DATA
-				DDRSS3_PHY_505_DATA
-				DDRSS3_PHY_506_DATA
-				DDRSS3_PHY_507_DATA
-				DDRSS3_PHY_508_DATA
-				DDRSS3_PHY_509_DATA
-				DDRSS3_PHY_510_DATA
-				DDRSS3_PHY_511_DATA
-				DDRSS3_PHY_512_DATA
-				DDRSS3_PHY_513_DATA
-				DDRSS3_PHY_514_DATA
-				DDRSS3_PHY_515_DATA
-				DDRSS3_PHY_516_DATA
-				DDRSS3_PHY_517_DATA
-				DDRSS3_PHY_518_DATA
-				DDRSS3_PHY_519_DATA
-				DDRSS3_PHY_520_DATA
-				DDRSS3_PHY_521_DATA
-				DDRSS3_PHY_522_DATA
-				DDRSS3_PHY_523_DATA
-				DDRSS3_PHY_524_DATA
-				DDRSS3_PHY_525_DATA
-				DDRSS3_PHY_526_DATA
-				DDRSS3_PHY_527_DATA
-				DDRSS3_PHY_528_DATA
-				DDRSS3_PHY_529_DATA
-				DDRSS3_PHY_530_DATA
-				DDRSS3_PHY_531_DATA
-				DDRSS3_PHY_532_DATA
-				DDRSS3_PHY_533_DATA
-				DDRSS3_PHY_534_DATA
-				DDRSS3_PHY_535_DATA
-				DDRSS3_PHY_536_DATA
-				DDRSS3_PHY_537_DATA
-				DDRSS3_PHY_538_DATA
-				DDRSS3_PHY_539_DATA
-				DDRSS3_PHY_540_DATA
-				DDRSS3_PHY_541_DATA
-				DDRSS3_PHY_542_DATA
-				DDRSS3_PHY_543_DATA
-				DDRSS3_PHY_544_DATA
-				DDRSS3_PHY_545_DATA
-				DDRSS3_PHY_546_DATA
-				DDRSS3_PHY_547_DATA
-				DDRSS3_PHY_548_DATA
-				DDRSS3_PHY_549_DATA
-				DDRSS3_PHY_550_DATA
-				DDRSS3_PHY_551_DATA
-				DDRSS3_PHY_552_DATA
-				DDRSS3_PHY_553_DATA
-				DDRSS3_PHY_554_DATA
-				DDRSS3_PHY_555_DATA
-				DDRSS3_PHY_556_DATA
-				DDRSS3_PHY_557_DATA
-				DDRSS3_PHY_558_DATA
-				DDRSS3_PHY_559_DATA
-				DDRSS3_PHY_560_DATA
-				DDRSS3_PHY_561_DATA
-				DDRSS3_PHY_562_DATA
-				DDRSS3_PHY_563_DATA
-				DDRSS3_PHY_564_DATA
-				DDRSS3_PHY_565_DATA
-				DDRSS3_PHY_566_DATA
-				DDRSS3_PHY_567_DATA
-				DDRSS3_PHY_568_DATA
-				DDRSS3_PHY_569_DATA
-				DDRSS3_PHY_570_DATA
-				DDRSS3_PHY_571_DATA
-				DDRSS3_PHY_572_DATA
-				DDRSS3_PHY_573_DATA
-				DDRSS3_PHY_574_DATA
-				DDRSS3_PHY_575_DATA
-				DDRSS3_PHY_576_DATA
-				DDRSS3_PHY_577_DATA
-				DDRSS3_PHY_578_DATA
-				DDRSS3_PHY_579_DATA
-				DDRSS3_PHY_580_DATA
-				DDRSS3_PHY_581_DATA
-				DDRSS3_PHY_582_DATA
-				DDRSS3_PHY_583_DATA
-				DDRSS3_PHY_584_DATA
-				DDRSS3_PHY_585_DATA
-				DDRSS3_PHY_586_DATA
-				DDRSS3_PHY_587_DATA
-				DDRSS3_PHY_588_DATA
-				DDRSS3_PHY_589_DATA
-				DDRSS3_PHY_590_DATA
-				DDRSS3_PHY_591_DATA
-				DDRSS3_PHY_592_DATA
-				DDRSS3_PHY_593_DATA
-				DDRSS3_PHY_594_DATA
-				DDRSS3_PHY_595_DATA
-				DDRSS3_PHY_596_DATA
-				DDRSS3_PHY_597_DATA
-				DDRSS3_PHY_598_DATA
-				DDRSS3_PHY_599_DATA
-				DDRSS3_PHY_600_DATA
-				DDRSS3_PHY_601_DATA
-				DDRSS3_PHY_602_DATA
-				DDRSS3_PHY_603_DATA
-				DDRSS3_PHY_604_DATA
-				DDRSS3_PHY_605_DATA
-				DDRSS3_PHY_606_DATA
-				DDRSS3_PHY_607_DATA
-				DDRSS3_PHY_608_DATA
-				DDRSS3_PHY_609_DATA
-				DDRSS3_PHY_610_DATA
-				DDRSS3_PHY_611_DATA
-				DDRSS3_PHY_612_DATA
-				DDRSS3_PHY_613_DATA
-				DDRSS3_PHY_614_DATA
-				DDRSS3_PHY_615_DATA
-				DDRSS3_PHY_616_DATA
-				DDRSS3_PHY_617_DATA
-				DDRSS3_PHY_618_DATA
-				DDRSS3_PHY_619_DATA
-				DDRSS3_PHY_620_DATA
-				DDRSS3_PHY_621_DATA
-				DDRSS3_PHY_622_DATA
-				DDRSS3_PHY_623_DATA
-				DDRSS3_PHY_624_DATA
-				DDRSS3_PHY_625_DATA
-				DDRSS3_PHY_626_DATA
-				DDRSS3_PHY_627_DATA
-				DDRSS3_PHY_628_DATA
-				DDRSS3_PHY_629_DATA
-				DDRSS3_PHY_630_DATA
-				DDRSS3_PHY_631_DATA
-				DDRSS3_PHY_632_DATA
-				DDRSS3_PHY_633_DATA
-				DDRSS3_PHY_634_DATA
-				DDRSS3_PHY_635_DATA
-				DDRSS3_PHY_636_DATA
-				DDRSS3_PHY_637_DATA
-				DDRSS3_PHY_638_DATA
-				DDRSS3_PHY_639_DATA
-				DDRSS3_PHY_640_DATA
-				DDRSS3_PHY_641_DATA
-				DDRSS3_PHY_642_DATA
-				DDRSS3_PHY_643_DATA
-				DDRSS3_PHY_644_DATA
-				DDRSS3_PHY_645_DATA
-				DDRSS3_PHY_646_DATA
-				DDRSS3_PHY_647_DATA
-				DDRSS3_PHY_648_DATA
-				DDRSS3_PHY_649_DATA
-				DDRSS3_PHY_650_DATA
-				DDRSS3_PHY_651_DATA
-				DDRSS3_PHY_652_DATA
-				DDRSS3_PHY_653_DATA
-				DDRSS3_PHY_654_DATA
-				DDRSS3_PHY_655_DATA
-				DDRSS3_PHY_656_DATA
-				DDRSS3_PHY_657_DATA
-				DDRSS3_PHY_658_DATA
-				DDRSS3_PHY_659_DATA
-				DDRSS3_PHY_660_DATA
-				DDRSS3_PHY_661_DATA
-				DDRSS3_PHY_662_DATA
-				DDRSS3_PHY_663_DATA
-				DDRSS3_PHY_664_DATA
-				DDRSS3_PHY_665_DATA
-				DDRSS3_PHY_666_DATA
-				DDRSS3_PHY_667_DATA
-				DDRSS3_PHY_668_DATA
-				DDRSS3_PHY_669_DATA
-				DDRSS3_PHY_670_DATA
-				DDRSS3_PHY_671_DATA
-				DDRSS3_PHY_672_DATA
-				DDRSS3_PHY_673_DATA
-				DDRSS3_PHY_674_DATA
-				DDRSS3_PHY_675_DATA
-				DDRSS3_PHY_676_DATA
-				DDRSS3_PHY_677_DATA
-				DDRSS3_PHY_678_DATA
-				DDRSS3_PHY_679_DATA
-				DDRSS3_PHY_680_DATA
-				DDRSS3_PHY_681_DATA
-				DDRSS3_PHY_682_DATA
-				DDRSS3_PHY_683_DATA
-				DDRSS3_PHY_684_DATA
-				DDRSS3_PHY_685_DATA
-				DDRSS3_PHY_686_DATA
-				DDRSS3_PHY_687_DATA
-				DDRSS3_PHY_688_DATA
-				DDRSS3_PHY_689_DATA
-				DDRSS3_PHY_690_DATA
-				DDRSS3_PHY_691_DATA
-				DDRSS3_PHY_692_DATA
-				DDRSS3_PHY_693_DATA
-				DDRSS3_PHY_694_DATA
-				DDRSS3_PHY_695_DATA
-				DDRSS3_PHY_696_DATA
-				DDRSS3_PHY_697_DATA
-				DDRSS3_PHY_698_DATA
-				DDRSS3_PHY_699_DATA
-				DDRSS3_PHY_700_DATA
-				DDRSS3_PHY_701_DATA
-				DDRSS3_PHY_702_DATA
-				DDRSS3_PHY_703_DATA
-				DDRSS3_PHY_704_DATA
-				DDRSS3_PHY_705_DATA
-				DDRSS3_PHY_706_DATA
-				DDRSS3_PHY_707_DATA
-				DDRSS3_PHY_708_DATA
-				DDRSS3_PHY_709_DATA
-				DDRSS3_PHY_710_DATA
-				DDRSS3_PHY_711_DATA
-				DDRSS3_PHY_712_DATA
-				DDRSS3_PHY_713_DATA
-				DDRSS3_PHY_714_DATA
-				DDRSS3_PHY_715_DATA
-				DDRSS3_PHY_716_DATA
-				DDRSS3_PHY_717_DATA
-				DDRSS3_PHY_718_DATA
-				DDRSS3_PHY_719_DATA
-				DDRSS3_PHY_720_DATA
-				DDRSS3_PHY_721_DATA
-				DDRSS3_PHY_722_DATA
-				DDRSS3_PHY_723_DATA
-				DDRSS3_PHY_724_DATA
-				DDRSS3_PHY_725_DATA
-				DDRSS3_PHY_726_DATA
-				DDRSS3_PHY_727_DATA
-				DDRSS3_PHY_728_DATA
-				DDRSS3_PHY_729_DATA
-				DDRSS3_PHY_730_DATA
-				DDRSS3_PHY_731_DATA
-				DDRSS3_PHY_732_DATA
-				DDRSS3_PHY_733_DATA
-				DDRSS3_PHY_734_DATA
-				DDRSS3_PHY_735_DATA
-				DDRSS3_PHY_736_DATA
-				DDRSS3_PHY_737_DATA
-				DDRSS3_PHY_738_DATA
-				DDRSS3_PHY_739_DATA
-				DDRSS3_PHY_740_DATA
-				DDRSS3_PHY_741_DATA
-				DDRSS3_PHY_742_DATA
-				DDRSS3_PHY_743_DATA
-				DDRSS3_PHY_744_DATA
-				DDRSS3_PHY_745_DATA
-				DDRSS3_PHY_746_DATA
-				DDRSS3_PHY_747_DATA
-				DDRSS3_PHY_748_DATA
-				DDRSS3_PHY_749_DATA
-				DDRSS3_PHY_750_DATA
-				DDRSS3_PHY_751_DATA
-				DDRSS3_PHY_752_DATA
-				DDRSS3_PHY_753_DATA
-				DDRSS3_PHY_754_DATA
-				DDRSS3_PHY_755_DATA
-				DDRSS3_PHY_756_DATA
-				DDRSS3_PHY_757_DATA
-				DDRSS3_PHY_758_DATA
-				DDRSS3_PHY_759_DATA
-				DDRSS3_PHY_760_DATA
-				DDRSS3_PHY_761_DATA
-				DDRSS3_PHY_762_DATA
-				DDRSS3_PHY_763_DATA
-				DDRSS3_PHY_764_DATA
-				DDRSS3_PHY_765_DATA
-				DDRSS3_PHY_766_DATA
-				DDRSS3_PHY_767_DATA
-				DDRSS3_PHY_768_DATA
-				DDRSS3_PHY_769_DATA
-				DDRSS3_PHY_770_DATA
-				DDRSS3_PHY_771_DATA
-				DDRSS3_PHY_772_DATA
-				DDRSS3_PHY_773_DATA
-				DDRSS3_PHY_774_DATA
-				DDRSS3_PHY_775_DATA
-				DDRSS3_PHY_776_DATA
-				DDRSS3_PHY_777_DATA
-				DDRSS3_PHY_778_DATA
-				DDRSS3_PHY_779_DATA
-				DDRSS3_PHY_780_DATA
-				DDRSS3_PHY_781_DATA
-				DDRSS3_PHY_782_DATA
-				DDRSS3_PHY_783_DATA
-				DDRSS3_PHY_784_DATA
-				DDRSS3_PHY_785_DATA
-				DDRSS3_PHY_786_DATA
-				DDRSS3_PHY_787_DATA
-				DDRSS3_PHY_788_DATA
-				DDRSS3_PHY_789_DATA
-				DDRSS3_PHY_790_DATA
-				DDRSS3_PHY_791_DATA
-				DDRSS3_PHY_792_DATA
-				DDRSS3_PHY_793_DATA
-				DDRSS3_PHY_794_DATA
-				DDRSS3_PHY_795_DATA
-				DDRSS3_PHY_796_DATA
-				DDRSS3_PHY_797_DATA
-				DDRSS3_PHY_798_DATA
-				DDRSS3_PHY_799_DATA
-				DDRSS3_PHY_800_DATA
-				DDRSS3_PHY_801_DATA
-				DDRSS3_PHY_802_DATA
-				DDRSS3_PHY_803_DATA
-				DDRSS3_PHY_804_DATA
-				DDRSS3_PHY_805_DATA
-				DDRSS3_PHY_806_DATA
-				DDRSS3_PHY_807_DATA
-				DDRSS3_PHY_808_DATA
-				DDRSS3_PHY_809_DATA
-				DDRSS3_PHY_810_DATA
-				DDRSS3_PHY_811_DATA
-				DDRSS3_PHY_812_DATA
-				DDRSS3_PHY_813_DATA
-				DDRSS3_PHY_814_DATA
-				DDRSS3_PHY_815_DATA
-				DDRSS3_PHY_816_DATA
-				DDRSS3_PHY_817_DATA
-				DDRSS3_PHY_818_DATA
-				DDRSS3_PHY_819_DATA
-				DDRSS3_PHY_820_DATA
-				DDRSS3_PHY_821_DATA
-				DDRSS3_PHY_822_DATA
-				DDRSS3_PHY_823_DATA
-				DDRSS3_PHY_824_DATA
-				DDRSS3_PHY_825_DATA
-				DDRSS3_PHY_826_DATA
-				DDRSS3_PHY_827_DATA
-				DDRSS3_PHY_828_DATA
-				DDRSS3_PHY_829_DATA
-				DDRSS3_PHY_830_DATA
-				DDRSS3_PHY_831_DATA
-				DDRSS3_PHY_832_DATA
-				DDRSS3_PHY_833_DATA
-				DDRSS3_PHY_834_DATA
-				DDRSS3_PHY_835_DATA
-				DDRSS3_PHY_836_DATA
-				DDRSS3_PHY_837_DATA
-				DDRSS3_PHY_838_DATA
-				DDRSS3_PHY_839_DATA
-				DDRSS3_PHY_840_DATA
-				DDRSS3_PHY_841_DATA
-				DDRSS3_PHY_842_DATA
-				DDRSS3_PHY_843_DATA
-				DDRSS3_PHY_844_DATA
-				DDRSS3_PHY_845_DATA
-				DDRSS3_PHY_846_DATA
-				DDRSS3_PHY_847_DATA
-				DDRSS3_PHY_848_DATA
-				DDRSS3_PHY_849_DATA
-				DDRSS3_PHY_850_DATA
-				DDRSS3_PHY_851_DATA
-				DDRSS3_PHY_852_DATA
-				DDRSS3_PHY_853_DATA
-				DDRSS3_PHY_854_DATA
-				DDRSS3_PHY_855_DATA
-				DDRSS3_PHY_856_DATA
-				DDRSS3_PHY_857_DATA
-				DDRSS3_PHY_858_DATA
-				DDRSS3_PHY_859_DATA
-				DDRSS3_PHY_860_DATA
-				DDRSS3_PHY_861_DATA
-				DDRSS3_PHY_862_DATA
-				DDRSS3_PHY_863_DATA
-				DDRSS3_PHY_864_DATA
-				DDRSS3_PHY_865_DATA
-				DDRSS3_PHY_866_DATA
-				DDRSS3_PHY_867_DATA
-				DDRSS3_PHY_868_DATA
-				DDRSS3_PHY_869_DATA
-				DDRSS3_PHY_870_DATA
-				DDRSS3_PHY_871_DATA
-				DDRSS3_PHY_872_DATA
-				DDRSS3_PHY_873_DATA
-				DDRSS3_PHY_874_DATA
-				DDRSS3_PHY_875_DATA
-				DDRSS3_PHY_876_DATA
-				DDRSS3_PHY_877_DATA
-				DDRSS3_PHY_878_DATA
-				DDRSS3_PHY_879_DATA
-				DDRSS3_PHY_880_DATA
-				DDRSS3_PHY_881_DATA
-				DDRSS3_PHY_882_DATA
-				DDRSS3_PHY_883_DATA
-				DDRSS3_PHY_884_DATA
-				DDRSS3_PHY_885_DATA
-				DDRSS3_PHY_886_DATA
-				DDRSS3_PHY_887_DATA
-				DDRSS3_PHY_888_DATA
-				DDRSS3_PHY_889_DATA
-				DDRSS3_PHY_890_DATA
-				DDRSS3_PHY_891_DATA
-				DDRSS3_PHY_892_DATA
-				DDRSS3_PHY_893_DATA
-				DDRSS3_PHY_894_DATA
-				DDRSS3_PHY_895_DATA
-				DDRSS3_PHY_896_DATA
-				DDRSS3_PHY_897_DATA
-				DDRSS3_PHY_898_DATA
-				DDRSS3_PHY_899_DATA
-				DDRSS3_PHY_900_DATA
-				DDRSS3_PHY_901_DATA
-				DDRSS3_PHY_902_DATA
-				DDRSS3_PHY_903_DATA
-				DDRSS3_PHY_904_DATA
-				DDRSS3_PHY_905_DATA
-				DDRSS3_PHY_906_DATA
-				DDRSS3_PHY_907_DATA
-				DDRSS3_PHY_908_DATA
-				DDRSS3_PHY_909_DATA
-				DDRSS3_PHY_910_DATA
-				DDRSS3_PHY_911_DATA
-				DDRSS3_PHY_912_DATA
-				DDRSS3_PHY_913_DATA
-				DDRSS3_PHY_914_DATA
-				DDRSS3_PHY_915_DATA
-				DDRSS3_PHY_916_DATA
-				DDRSS3_PHY_917_DATA
-				DDRSS3_PHY_918_DATA
-				DDRSS3_PHY_919_DATA
-				DDRSS3_PHY_920_DATA
-				DDRSS3_PHY_921_DATA
-				DDRSS3_PHY_922_DATA
-				DDRSS3_PHY_923_DATA
-				DDRSS3_PHY_924_DATA
-				DDRSS3_PHY_925_DATA
-				DDRSS3_PHY_926_DATA
-				DDRSS3_PHY_927_DATA
-				DDRSS3_PHY_928_DATA
-				DDRSS3_PHY_929_DATA
-				DDRSS3_PHY_930_DATA
-				DDRSS3_PHY_931_DATA
-				DDRSS3_PHY_932_DATA
-				DDRSS3_PHY_933_DATA
-				DDRSS3_PHY_934_DATA
-				DDRSS3_PHY_935_DATA
-				DDRSS3_PHY_936_DATA
-				DDRSS3_PHY_937_DATA
-				DDRSS3_PHY_938_DATA
-				DDRSS3_PHY_939_DATA
-				DDRSS3_PHY_940_DATA
-				DDRSS3_PHY_941_DATA
-				DDRSS3_PHY_942_DATA
-				DDRSS3_PHY_943_DATA
-				DDRSS3_PHY_944_DATA
-				DDRSS3_PHY_945_DATA
-				DDRSS3_PHY_946_DATA
-				DDRSS3_PHY_947_DATA
-				DDRSS3_PHY_948_DATA
-				DDRSS3_PHY_949_DATA
-				DDRSS3_PHY_950_DATA
-				DDRSS3_PHY_951_DATA
-				DDRSS3_PHY_952_DATA
-				DDRSS3_PHY_953_DATA
-				DDRSS3_PHY_954_DATA
-				DDRSS3_PHY_955_DATA
-				DDRSS3_PHY_956_DATA
-				DDRSS3_PHY_957_DATA
-				DDRSS3_PHY_958_DATA
-				DDRSS3_PHY_959_DATA
-				DDRSS3_PHY_960_DATA
-				DDRSS3_PHY_961_DATA
-				DDRSS3_PHY_962_DATA
-				DDRSS3_PHY_963_DATA
-				DDRSS3_PHY_964_DATA
-				DDRSS3_PHY_965_DATA
-				DDRSS3_PHY_966_DATA
-				DDRSS3_PHY_967_DATA
-				DDRSS3_PHY_968_DATA
-				DDRSS3_PHY_969_DATA
-				DDRSS3_PHY_970_DATA
-				DDRSS3_PHY_971_DATA
-				DDRSS3_PHY_972_DATA
-				DDRSS3_PHY_973_DATA
-				DDRSS3_PHY_974_DATA
-				DDRSS3_PHY_975_DATA
-				DDRSS3_PHY_976_DATA
-				DDRSS3_PHY_977_DATA
-				DDRSS3_PHY_978_DATA
-				DDRSS3_PHY_979_DATA
-				DDRSS3_PHY_980_DATA
-				DDRSS3_PHY_981_DATA
-				DDRSS3_PHY_982_DATA
-				DDRSS3_PHY_983_DATA
-				DDRSS3_PHY_984_DATA
-				DDRSS3_PHY_985_DATA
-				DDRSS3_PHY_986_DATA
-				DDRSS3_PHY_987_DATA
-				DDRSS3_PHY_988_DATA
-				DDRSS3_PHY_989_DATA
-				DDRSS3_PHY_990_DATA
-				DDRSS3_PHY_991_DATA
-				DDRSS3_PHY_992_DATA
-				DDRSS3_PHY_993_DATA
-				DDRSS3_PHY_994_DATA
-				DDRSS3_PHY_995_DATA
-				DDRSS3_PHY_996_DATA
-				DDRSS3_PHY_997_DATA
-				DDRSS3_PHY_998_DATA
-				DDRSS3_PHY_999_DATA
-				DDRSS3_PHY_1000_DATA
-				DDRSS3_PHY_1001_DATA
-				DDRSS3_PHY_1002_DATA
-				DDRSS3_PHY_1003_DATA
-				DDRSS3_PHY_1004_DATA
-				DDRSS3_PHY_1005_DATA
-				DDRSS3_PHY_1006_DATA
-				DDRSS3_PHY_1007_DATA
-				DDRSS3_PHY_1008_DATA
-				DDRSS3_PHY_1009_DATA
-				DDRSS3_PHY_1010_DATA
-				DDRSS3_PHY_1011_DATA
-				DDRSS3_PHY_1012_DATA
-				DDRSS3_PHY_1013_DATA
-				DDRSS3_PHY_1014_DATA
-				DDRSS3_PHY_1015_DATA
-				DDRSS3_PHY_1016_DATA
-				DDRSS3_PHY_1017_DATA
-				DDRSS3_PHY_1018_DATA
-				DDRSS3_PHY_1019_DATA
-				DDRSS3_PHY_1020_DATA
-				DDRSS3_PHY_1021_DATA
-				DDRSS3_PHY_1022_DATA
-				DDRSS3_PHY_1023_DATA
-				DDRSS3_PHY_1024_DATA
-				DDRSS3_PHY_1025_DATA
-				DDRSS3_PHY_1026_DATA
-				DDRSS3_PHY_1027_DATA
-				DDRSS3_PHY_1028_DATA
-				DDRSS3_PHY_1029_DATA
-				DDRSS3_PHY_1030_DATA
-				DDRSS3_PHY_1031_DATA
-				DDRSS3_PHY_1032_DATA
-				DDRSS3_PHY_1033_DATA
-				DDRSS3_PHY_1034_DATA
-				DDRSS3_PHY_1035_DATA
-				DDRSS3_PHY_1036_DATA
-				DDRSS3_PHY_1037_DATA
-				DDRSS3_PHY_1038_DATA
-				DDRSS3_PHY_1039_DATA
-				DDRSS3_PHY_1040_DATA
-				DDRSS3_PHY_1041_DATA
-				DDRSS3_PHY_1042_DATA
-				DDRSS3_PHY_1043_DATA
-				DDRSS3_PHY_1044_DATA
-				DDRSS3_PHY_1045_DATA
-				DDRSS3_PHY_1046_DATA
-				DDRSS3_PHY_1047_DATA
-				DDRSS3_PHY_1048_DATA
-				DDRSS3_PHY_1049_DATA
-				DDRSS3_PHY_1050_DATA
-				DDRSS3_PHY_1051_DATA
-				DDRSS3_PHY_1052_DATA
-				DDRSS3_PHY_1053_DATA
-				DDRSS3_PHY_1054_DATA
-				DDRSS3_PHY_1055_DATA
-				DDRSS3_PHY_1056_DATA
-				DDRSS3_PHY_1057_DATA
-				DDRSS3_PHY_1058_DATA
-				DDRSS3_PHY_1059_DATA
-				DDRSS3_PHY_1060_DATA
-				DDRSS3_PHY_1061_DATA
-				DDRSS3_PHY_1062_DATA
-				DDRSS3_PHY_1063_DATA
-				DDRSS3_PHY_1064_DATA
-				DDRSS3_PHY_1065_DATA
-				DDRSS3_PHY_1066_DATA
-				DDRSS3_PHY_1067_DATA
-				DDRSS3_PHY_1068_DATA
-				DDRSS3_PHY_1069_DATA
-				DDRSS3_PHY_1070_DATA
-				DDRSS3_PHY_1071_DATA
-				DDRSS3_PHY_1072_DATA
-				DDRSS3_PHY_1073_DATA
-				DDRSS3_PHY_1074_DATA
-				DDRSS3_PHY_1075_DATA
-				DDRSS3_PHY_1076_DATA
-				DDRSS3_PHY_1077_DATA
-				DDRSS3_PHY_1078_DATA
-				DDRSS3_PHY_1079_DATA
-				DDRSS3_PHY_1080_DATA
-				DDRSS3_PHY_1081_DATA
-				DDRSS3_PHY_1082_DATA
-				DDRSS3_PHY_1083_DATA
-				DDRSS3_PHY_1084_DATA
-				DDRSS3_PHY_1085_DATA
-				DDRSS3_PHY_1086_DATA
-				DDRSS3_PHY_1087_DATA
-				DDRSS3_PHY_1088_DATA
-				DDRSS3_PHY_1089_DATA
-				DDRSS3_PHY_1090_DATA
-				DDRSS3_PHY_1091_DATA
-				DDRSS3_PHY_1092_DATA
-				DDRSS3_PHY_1093_DATA
-				DDRSS3_PHY_1094_DATA
-				DDRSS3_PHY_1095_DATA
-				DDRSS3_PHY_1096_DATA
-				DDRSS3_PHY_1097_DATA
-				DDRSS3_PHY_1098_DATA
-				DDRSS3_PHY_1099_DATA
-				DDRSS3_PHY_1100_DATA
-				DDRSS3_PHY_1101_DATA
-				DDRSS3_PHY_1102_DATA
-				DDRSS3_PHY_1103_DATA
-				DDRSS3_PHY_1104_DATA
-				DDRSS3_PHY_1105_DATA
-				DDRSS3_PHY_1106_DATA
-				DDRSS3_PHY_1107_DATA
-				DDRSS3_PHY_1108_DATA
-				DDRSS3_PHY_1109_DATA
-				DDRSS3_PHY_1110_DATA
-				DDRSS3_PHY_1111_DATA
-				DDRSS3_PHY_1112_DATA
-				DDRSS3_PHY_1113_DATA
-				DDRSS3_PHY_1114_DATA
-				DDRSS3_PHY_1115_DATA
-				DDRSS3_PHY_1116_DATA
-				DDRSS3_PHY_1117_DATA
-				DDRSS3_PHY_1118_DATA
-				DDRSS3_PHY_1119_DATA
-				DDRSS3_PHY_1120_DATA
-				DDRSS3_PHY_1121_DATA
-				DDRSS3_PHY_1122_DATA
-				DDRSS3_PHY_1123_DATA
-				DDRSS3_PHY_1124_DATA
-				DDRSS3_PHY_1125_DATA
-				DDRSS3_PHY_1126_DATA
-				DDRSS3_PHY_1127_DATA
-				DDRSS3_PHY_1128_DATA
-				DDRSS3_PHY_1129_DATA
-				DDRSS3_PHY_1130_DATA
-				DDRSS3_PHY_1131_DATA
-				DDRSS3_PHY_1132_DATA
-				DDRSS3_PHY_1133_DATA
-				DDRSS3_PHY_1134_DATA
-				DDRSS3_PHY_1135_DATA
-				DDRSS3_PHY_1136_DATA
-				DDRSS3_PHY_1137_DATA
-				DDRSS3_PHY_1138_DATA
-				DDRSS3_PHY_1139_DATA
-				DDRSS3_PHY_1140_DATA
-				DDRSS3_PHY_1141_DATA
-				DDRSS3_PHY_1142_DATA
-				DDRSS3_PHY_1143_DATA
-				DDRSS3_PHY_1144_DATA
-				DDRSS3_PHY_1145_DATA
-				DDRSS3_PHY_1146_DATA
-				DDRSS3_PHY_1147_DATA
-				DDRSS3_PHY_1148_DATA
-				DDRSS3_PHY_1149_DATA
-				DDRSS3_PHY_1150_DATA
-				DDRSS3_PHY_1151_DATA
-				DDRSS3_PHY_1152_DATA
-				DDRSS3_PHY_1153_DATA
-				DDRSS3_PHY_1154_DATA
-				DDRSS3_PHY_1155_DATA
-				DDRSS3_PHY_1156_DATA
-				DDRSS3_PHY_1157_DATA
-				DDRSS3_PHY_1158_DATA
-				DDRSS3_PHY_1159_DATA
-				DDRSS3_PHY_1160_DATA
-				DDRSS3_PHY_1161_DATA
-				DDRSS3_PHY_1162_DATA
-				DDRSS3_PHY_1163_DATA
-				DDRSS3_PHY_1164_DATA
-				DDRSS3_PHY_1165_DATA
-				DDRSS3_PHY_1166_DATA
-				DDRSS3_PHY_1167_DATA
-				DDRSS3_PHY_1168_DATA
-				DDRSS3_PHY_1169_DATA
-				DDRSS3_PHY_1170_DATA
-				DDRSS3_PHY_1171_DATA
-				DDRSS3_PHY_1172_DATA
-				DDRSS3_PHY_1173_DATA
-				DDRSS3_PHY_1174_DATA
-				DDRSS3_PHY_1175_DATA
-				DDRSS3_PHY_1176_DATA
-				DDRSS3_PHY_1177_DATA
-				DDRSS3_PHY_1178_DATA
-				DDRSS3_PHY_1179_DATA
-				DDRSS3_PHY_1180_DATA
-				DDRSS3_PHY_1181_DATA
-				DDRSS3_PHY_1182_DATA
-				DDRSS3_PHY_1183_DATA
-				DDRSS3_PHY_1184_DATA
-				DDRSS3_PHY_1185_DATA
-				DDRSS3_PHY_1186_DATA
-				DDRSS3_PHY_1187_DATA
-				DDRSS3_PHY_1188_DATA
-				DDRSS3_PHY_1189_DATA
-				DDRSS3_PHY_1190_DATA
-				DDRSS3_PHY_1191_DATA
-				DDRSS3_PHY_1192_DATA
-				DDRSS3_PHY_1193_DATA
-				DDRSS3_PHY_1194_DATA
-				DDRSS3_PHY_1195_DATA
-				DDRSS3_PHY_1196_DATA
-				DDRSS3_PHY_1197_DATA
-				DDRSS3_PHY_1198_DATA
-				DDRSS3_PHY_1199_DATA
-				DDRSS3_PHY_1200_DATA
-				DDRSS3_PHY_1201_DATA
-				DDRSS3_PHY_1202_DATA
-				DDRSS3_PHY_1203_DATA
-				DDRSS3_PHY_1204_DATA
-				DDRSS3_PHY_1205_DATA
-				DDRSS3_PHY_1206_DATA
-				DDRSS3_PHY_1207_DATA
-				DDRSS3_PHY_1208_DATA
-				DDRSS3_PHY_1209_DATA
-				DDRSS3_PHY_1210_DATA
-				DDRSS3_PHY_1211_DATA
-				DDRSS3_PHY_1212_DATA
-				DDRSS3_PHY_1213_DATA
-				DDRSS3_PHY_1214_DATA
-				DDRSS3_PHY_1215_DATA
-				DDRSS3_PHY_1216_DATA
-				DDRSS3_PHY_1217_DATA
-				DDRSS3_PHY_1218_DATA
-				DDRSS3_PHY_1219_DATA
-				DDRSS3_PHY_1220_DATA
-				DDRSS3_PHY_1221_DATA
-				DDRSS3_PHY_1222_DATA
-				DDRSS3_PHY_1223_DATA
-				DDRSS3_PHY_1224_DATA
-				DDRSS3_PHY_1225_DATA
-				DDRSS3_PHY_1226_DATA
-				DDRSS3_PHY_1227_DATA
-				DDRSS3_PHY_1228_DATA
-				DDRSS3_PHY_1229_DATA
-				DDRSS3_PHY_1230_DATA
-				DDRSS3_PHY_1231_DATA
-				DDRSS3_PHY_1232_DATA
-				DDRSS3_PHY_1233_DATA
-				DDRSS3_PHY_1234_DATA
-				DDRSS3_PHY_1235_DATA
-				DDRSS3_PHY_1236_DATA
-				DDRSS3_PHY_1237_DATA
-				DDRSS3_PHY_1238_DATA
-				DDRSS3_PHY_1239_DATA
-				DDRSS3_PHY_1240_DATA
-				DDRSS3_PHY_1241_DATA
-				DDRSS3_PHY_1242_DATA
-				DDRSS3_PHY_1243_DATA
-				DDRSS3_PHY_1244_DATA
-				DDRSS3_PHY_1245_DATA
-				DDRSS3_PHY_1246_DATA
-				DDRSS3_PHY_1247_DATA
-				DDRSS3_PHY_1248_DATA
-				DDRSS3_PHY_1249_DATA
-				DDRSS3_PHY_1250_DATA
-				DDRSS3_PHY_1251_DATA
-				DDRSS3_PHY_1252_DATA
-				DDRSS3_PHY_1253_DATA
-				DDRSS3_PHY_1254_DATA
-				DDRSS3_PHY_1255_DATA
-				DDRSS3_PHY_1256_DATA
-				DDRSS3_PHY_1257_DATA
-				DDRSS3_PHY_1258_DATA
-				DDRSS3_PHY_1259_DATA
-				DDRSS3_PHY_1260_DATA
-				DDRSS3_PHY_1261_DATA
-				DDRSS3_PHY_1262_DATA
-				DDRSS3_PHY_1263_DATA
-				DDRSS3_PHY_1264_DATA
-				DDRSS3_PHY_1265_DATA
-				DDRSS3_PHY_1266_DATA
-				DDRSS3_PHY_1267_DATA
-				DDRSS3_PHY_1268_DATA
-				DDRSS3_PHY_1269_DATA
-				DDRSS3_PHY_1270_DATA
-				DDRSS3_PHY_1271_DATA
-				DDRSS3_PHY_1272_DATA
-				DDRSS3_PHY_1273_DATA
-				DDRSS3_PHY_1274_DATA
-				DDRSS3_PHY_1275_DATA
-				DDRSS3_PHY_1276_DATA
-				DDRSS3_PHY_1277_DATA
-				DDRSS3_PHY_1278_DATA
-				DDRSS3_PHY_1279_DATA
-				DDRSS3_PHY_1280_DATA
-				DDRSS3_PHY_1281_DATA
-				DDRSS3_PHY_1282_DATA
-				DDRSS3_PHY_1283_DATA
-				DDRSS3_PHY_1284_DATA
-				DDRSS3_PHY_1285_DATA
-				DDRSS3_PHY_1286_DATA
-				DDRSS3_PHY_1287_DATA
-				DDRSS3_PHY_1288_DATA
-				DDRSS3_PHY_1289_DATA
-				DDRSS3_PHY_1290_DATA
-				DDRSS3_PHY_1291_DATA
-				DDRSS3_PHY_1292_DATA
-				DDRSS3_PHY_1293_DATA
-				DDRSS3_PHY_1294_DATA
-				DDRSS3_PHY_1295_DATA
-				DDRSS3_PHY_1296_DATA
-				DDRSS3_PHY_1297_DATA
-				DDRSS3_PHY_1298_DATA
-				DDRSS3_PHY_1299_DATA
-				DDRSS3_PHY_1300_DATA
-				DDRSS3_PHY_1301_DATA
-				DDRSS3_PHY_1302_DATA
-				DDRSS3_PHY_1303_DATA
-				DDRSS3_PHY_1304_DATA
-				DDRSS3_PHY_1305_DATA
-				DDRSS3_PHY_1306_DATA
-				DDRSS3_PHY_1307_DATA
-				DDRSS3_PHY_1308_DATA
-				DDRSS3_PHY_1309_DATA
-				DDRSS3_PHY_1310_DATA
-				DDRSS3_PHY_1311_DATA
-				DDRSS3_PHY_1312_DATA
-				DDRSS3_PHY_1313_DATA
-				DDRSS3_PHY_1314_DATA
-				DDRSS3_PHY_1315_DATA
-				DDRSS3_PHY_1316_DATA
-				DDRSS3_PHY_1317_DATA
-				DDRSS3_PHY_1318_DATA
-				DDRSS3_PHY_1319_DATA
-				DDRSS3_PHY_1320_DATA
-				DDRSS3_PHY_1321_DATA
-				DDRSS3_PHY_1322_DATA
-				DDRSS3_PHY_1323_DATA
-				DDRSS3_PHY_1324_DATA
-				DDRSS3_PHY_1325_DATA
-				DDRSS3_PHY_1326_DATA
-				DDRSS3_PHY_1327_DATA
-				DDRSS3_PHY_1328_DATA
-				DDRSS3_PHY_1329_DATA
-				DDRSS3_PHY_1330_DATA
-				DDRSS3_PHY_1331_DATA
-				DDRSS3_PHY_1332_DATA
-				DDRSS3_PHY_1333_DATA
-				DDRSS3_PHY_1334_DATA
-				DDRSS3_PHY_1335_DATA
-				DDRSS3_PHY_1336_DATA
-				DDRSS3_PHY_1337_DATA
-				DDRSS3_PHY_1338_DATA
-				DDRSS3_PHY_1339_DATA
-				DDRSS3_PHY_1340_DATA
-				DDRSS3_PHY_1341_DATA
-				DDRSS3_PHY_1342_DATA
-				DDRSS3_PHY_1343_DATA
-				DDRSS3_PHY_1344_DATA
-				DDRSS3_PHY_1345_DATA
-				DDRSS3_PHY_1346_DATA
-				DDRSS3_PHY_1347_DATA
-				DDRSS3_PHY_1348_DATA
-				DDRSS3_PHY_1349_DATA
-				DDRSS3_PHY_1350_DATA
-				DDRSS3_PHY_1351_DATA
-				DDRSS3_PHY_1352_DATA
-				DDRSS3_PHY_1353_DATA
-				DDRSS3_PHY_1354_DATA
-				DDRSS3_PHY_1355_DATA
-				DDRSS3_PHY_1356_DATA
-				DDRSS3_PHY_1357_DATA
-				DDRSS3_PHY_1358_DATA
-				DDRSS3_PHY_1359_DATA
-				DDRSS3_PHY_1360_DATA
-				DDRSS3_PHY_1361_DATA
-				DDRSS3_PHY_1362_DATA
-				DDRSS3_PHY_1363_DATA
-				DDRSS3_PHY_1364_DATA
-				DDRSS3_PHY_1365_DATA
-				DDRSS3_PHY_1366_DATA
-				DDRSS3_PHY_1367_DATA
-				DDRSS3_PHY_1368_DATA
-				DDRSS3_PHY_1369_DATA
-				DDRSS3_PHY_1370_DATA
-				DDRSS3_PHY_1371_DATA
-				DDRSS3_PHY_1372_DATA
-				DDRSS3_PHY_1373_DATA
-				DDRSS3_PHY_1374_DATA
-				DDRSS3_PHY_1375_DATA
-				DDRSS3_PHY_1376_DATA
-				DDRSS3_PHY_1377_DATA
-				DDRSS3_PHY_1378_DATA
-				DDRSS3_PHY_1379_DATA
-				DDRSS3_PHY_1380_DATA
-				DDRSS3_PHY_1381_DATA
-				DDRSS3_PHY_1382_DATA
-				DDRSS3_PHY_1383_DATA
-				DDRSS3_PHY_1384_DATA
-				DDRSS3_PHY_1385_DATA
-				DDRSS3_PHY_1386_DATA
-				DDRSS3_PHY_1387_DATA
-				DDRSS3_PHY_1388_DATA
-				DDRSS3_PHY_1389_DATA
-				DDRSS3_PHY_1390_DATA
-				DDRSS3_PHY_1391_DATA
-				DDRSS3_PHY_1392_DATA
-				DDRSS3_PHY_1393_DATA
-				DDRSS3_PHY_1394_DATA
-				DDRSS3_PHY_1395_DATA
-				DDRSS3_PHY_1396_DATA
-				DDRSS3_PHY_1397_DATA
-				DDRSS3_PHY_1398_DATA
-				DDRSS3_PHY_1399_DATA
-				DDRSS3_PHY_1400_DATA
-				DDRSS3_PHY_1401_DATA
-				DDRSS3_PHY_1402_DATA
-				DDRSS3_PHY_1403_DATA
-				DDRSS3_PHY_1404_DATA
-				DDRSS3_PHY_1405_DATA
-				DDRSS3_PHY_1406_DATA
-				DDRSS3_PHY_1407_DATA
-				DDRSS3_PHY_1408_DATA
-				DDRSS3_PHY_1409_DATA
-				DDRSS3_PHY_1410_DATA
-				DDRSS3_PHY_1411_DATA
-				DDRSS3_PHY_1412_DATA
-				DDRSS3_PHY_1413_DATA
-				DDRSS3_PHY_1414_DATA
-				DDRSS3_PHY_1415_DATA
-				DDRSS3_PHY_1416_DATA
-				DDRSS3_PHY_1417_DATA
-				DDRSS3_PHY_1418_DATA
-				DDRSS3_PHY_1419_DATA
-				DDRSS3_PHY_1420_DATA
-				DDRSS3_PHY_1421_DATA
-				DDRSS3_PHY_1422_DATA
-			>;
-		};
+		ti,phy-data = <
+			DDRSS3_PHY_00_DATA
+			DDRSS3_PHY_01_DATA
+			DDRSS3_PHY_02_DATA
+			DDRSS3_PHY_03_DATA
+			DDRSS3_PHY_04_DATA
+			DDRSS3_PHY_05_DATA
+			DDRSS3_PHY_06_DATA
+			DDRSS3_PHY_07_DATA
+			DDRSS3_PHY_08_DATA
+			DDRSS3_PHY_09_DATA
+			DDRSS3_PHY_10_DATA
+			DDRSS3_PHY_11_DATA
+			DDRSS3_PHY_12_DATA
+			DDRSS3_PHY_13_DATA
+			DDRSS3_PHY_14_DATA
+			DDRSS3_PHY_15_DATA
+			DDRSS3_PHY_16_DATA
+			DDRSS3_PHY_17_DATA
+			DDRSS3_PHY_18_DATA
+			DDRSS3_PHY_19_DATA
+			DDRSS3_PHY_20_DATA
+			DDRSS3_PHY_21_DATA
+			DDRSS3_PHY_22_DATA
+			DDRSS3_PHY_23_DATA
+			DDRSS3_PHY_24_DATA
+			DDRSS3_PHY_25_DATA
+			DDRSS3_PHY_26_DATA
+			DDRSS3_PHY_27_DATA
+			DDRSS3_PHY_28_DATA
+			DDRSS3_PHY_29_DATA
+			DDRSS3_PHY_30_DATA
+			DDRSS3_PHY_31_DATA
+			DDRSS3_PHY_32_DATA
+			DDRSS3_PHY_33_DATA
+			DDRSS3_PHY_34_DATA
+			DDRSS3_PHY_35_DATA
+			DDRSS3_PHY_36_DATA
+			DDRSS3_PHY_37_DATA
+			DDRSS3_PHY_38_DATA
+			DDRSS3_PHY_39_DATA
+			DDRSS3_PHY_40_DATA
+			DDRSS3_PHY_41_DATA
+			DDRSS3_PHY_42_DATA
+			DDRSS3_PHY_43_DATA
+			DDRSS3_PHY_44_DATA
+			DDRSS3_PHY_45_DATA
+			DDRSS3_PHY_46_DATA
+			DDRSS3_PHY_47_DATA
+			DDRSS3_PHY_48_DATA
+			DDRSS3_PHY_49_DATA
+			DDRSS3_PHY_50_DATA
+			DDRSS3_PHY_51_DATA
+			DDRSS3_PHY_52_DATA
+			DDRSS3_PHY_53_DATA
+			DDRSS3_PHY_54_DATA
+			DDRSS3_PHY_55_DATA
+			DDRSS3_PHY_56_DATA
+			DDRSS3_PHY_57_DATA
+			DDRSS3_PHY_58_DATA
+			DDRSS3_PHY_59_DATA
+			DDRSS3_PHY_60_DATA
+			DDRSS3_PHY_61_DATA
+			DDRSS3_PHY_62_DATA
+			DDRSS3_PHY_63_DATA
+			DDRSS3_PHY_64_DATA
+			DDRSS3_PHY_65_DATA
+			DDRSS3_PHY_66_DATA
+			DDRSS3_PHY_67_DATA
+			DDRSS3_PHY_68_DATA
+			DDRSS3_PHY_69_DATA
+			DDRSS3_PHY_70_DATA
+			DDRSS3_PHY_71_DATA
+			DDRSS3_PHY_72_DATA
+			DDRSS3_PHY_73_DATA
+			DDRSS3_PHY_74_DATA
+			DDRSS3_PHY_75_DATA
+			DDRSS3_PHY_76_DATA
+			DDRSS3_PHY_77_DATA
+			DDRSS3_PHY_78_DATA
+			DDRSS3_PHY_79_DATA
+			DDRSS3_PHY_80_DATA
+			DDRSS3_PHY_81_DATA
+			DDRSS3_PHY_82_DATA
+			DDRSS3_PHY_83_DATA
+			DDRSS3_PHY_84_DATA
+			DDRSS3_PHY_85_DATA
+			DDRSS3_PHY_86_DATA
+			DDRSS3_PHY_87_DATA
+			DDRSS3_PHY_88_DATA
+			DDRSS3_PHY_89_DATA
+			DDRSS3_PHY_90_DATA
+			DDRSS3_PHY_91_DATA
+			DDRSS3_PHY_92_DATA
+			DDRSS3_PHY_93_DATA
+			DDRSS3_PHY_94_DATA
+			DDRSS3_PHY_95_DATA
+			DDRSS3_PHY_96_DATA
+			DDRSS3_PHY_97_DATA
+			DDRSS3_PHY_98_DATA
+			DDRSS3_PHY_99_DATA
+			DDRSS3_PHY_100_DATA
+			DDRSS3_PHY_101_DATA
+			DDRSS3_PHY_102_DATA
+			DDRSS3_PHY_103_DATA
+			DDRSS3_PHY_104_DATA
+			DDRSS3_PHY_105_DATA
+			DDRSS3_PHY_106_DATA
+			DDRSS3_PHY_107_DATA
+			DDRSS3_PHY_108_DATA
+			DDRSS3_PHY_109_DATA
+			DDRSS3_PHY_110_DATA
+			DDRSS3_PHY_111_DATA
+			DDRSS3_PHY_112_DATA
+			DDRSS3_PHY_113_DATA
+			DDRSS3_PHY_114_DATA
+			DDRSS3_PHY_115_DATA
+			DDRSS3_PHY_116_DATA
+			DDRSS3_PHY_117_DATA
+			DDRSS3_PHY_118_DATA
+			DDRSS3_PHY_119_DATA
+			DDRSS3_PHY_120_DATA
+			DDRSS3_PHY_121_DATA
+			DDRSS3_PHY_122_DATA
+			DDRSS3_PHY_123_DATA
+			DDRSS3_PHY_124_DATA
+			DDRSS3_PHY_125_DATA
+			DDRSS3_PHY_126_DATA
+			DDRSS3_PHY_127_DATA
+			DDRSS3_PHY_128_DATA
+			DDRSS3_PHY_129_DATA
+			DDRSS3_PHY_130_DATA
+			DDRSS3_PHY_131_DATA
+			DDRSS3_PHY_132_DATA
+			DDRSS3_PHY_133_DATA
+			DDRSS3_PHY_134_DATA
+			DDRSS3_PHY_135_DATA
+			DDRSS3_PHY_136_DATA
+			DDRSS3_PHY_137_DATA
+			DDRSS3_PHY_138_DATA
+			DDRSS3_PHY_139_DATA
+			DDRSS3_PHY_140_DATA
+			DDRSS3_PHY_141_DATA
+			DDRSS3_PHY_142_DATA
+			DDRSS3_PHY_143_DATA
+			DDRSS3_PHY_144_DATA
+			DDRSS3_PHY_145_DATA
+			DDRSS3_PHY_146_DATA
+			DDRSS3_PHY_147_DATA
+			DDRSS3_PHY_148_DATA
+			DDRSS3_PHY_149_DATA
+			DDRSS3_PHY_150_DATA
+			DDRSS3_PHY_151_DATA
+			DDRSS3_PHY_152_DATA
+			DDRSS3_PHY_153_DATA
+			DDRSS3_PHY_154_DATA
+			DDRSS3_PHY_155_DATA
+			DDRSS3_PHY_156_DATA
+			DDRSS3_PHY_157_DATA
+			DDRSS3_PHY_158_DATA
+			DDRSS3_PHY_159_DATA
+			DDRSS3_PHY_160_DATA
+			DDRSS3_PHY_161_DATA
+			DDRSS3_PHY_162_DATA
+			DDRSS3_PHY_163_DATA
+			DDRSS3_PHY_164_DATA
+			DDRSS3_PHY_165_DATA
+			DDRSS3_PHY_166_DATA
+			DDRSS3_PHY_167_DATA
+			DDRSS3_PHY_168_DATA
+			DDRSS3_PHY_169_DATA
+			DDRSS3_PHY_170_DATA
+			DDRSS3_PHY_171_DATA
+			DDRSS3_PHY_172_DATA
+			DDRSS3_PHY_173_DATA
+			DDRSS3_PHY_174_DATA
+			DDRSS3_PHY_175_DATA
+			DDRSS3_PHY_176_DATA
+			DDRSS3_PHY_177_DATA
+			DDRSS3_PHY_178_DATA
+			DDRSS3_PHY_179_DATA
+			DDRSS3_PHY_180_DATA
+			DDRSS3_PHY_181_DATA
+			DDRSS3_PHY_182_DATA
+			DDRSS3_PHY_183_DATA
+			DDRSS3_PHY_184_DATA
+			DDRSS3_PHY_185_DATA
+			DDRSS3_PHY_186_DATA
+			DDRSS3_PHY_187_DATA
+			DDRSS3_PHY_188_DATA
+			DDRSS3_PHY_189_DATA
+			DDRSS3_PHY_190_DATA
+			DDRSS3_PHY_191_DATA
+			DDRSS3_PHY_192_DATA
+			DDRSS3_PHY_193_DATA
+			DDRSS3_PHY_194_DATA
+			DDRSS3_PHY_195_DATA
+			DDRSS3_PHY_196_DATA
+			DDRSS3_PHY_197_DATA
+			DDRSS3_PHY_198_DATA
+			DDRSS3_PHY_199_DATA
+			DDRSS3_PHY_200_DATA
+			DDRSS3_PHY_201_DATA
+			DDRSS3_PHY_202_DATA
+			DDRSS3_PHY_203_DATA
+			DDRSS3_PHY_204_DATA
+			DDRSS3_PHY_205_DATA
+			DDRSS3_PHY_206_DATA
+			DDRSS3_PHY_207_DATA
+			DDRSS3_PHY_208_DATA
+			DDRSS3_PHY_209_DATA
+			DDRSS3_PHY_210_DATA
+			DDRSS3_PHY_211_DATA
+			DDRSS3_PHY_212_DATA
+			DDRSS3_PHY_213_DATA
+			DDRSS3_PHY_214_DATA
+			DDRSS3_PHY_215_DATA
+			DDRSS3_PHY_216_DATA
+			DDRSS3_PHY_217_DATA
+			DDRSS3_PHY_218_DATA
+			DDRSS3_PHY_219_DATA
+			DDRSS3_PHY_220_DATA
+			DDRSS3_PHY_221_DATA
+			DDRSS3_PHY_222_DATA
+			DDRSS3_PHY_223_DATA
+			DDRSS3_PHY_224_DATA
+			DDRSS3_PHY_225_DATA
+			DDRSS3_PHY_226_DATA
+			DDRSS3_PHY_227_DATA
+			DDRSS3_PHY_228_DATA
+			DDRSS3_PHY_229_DATA
+			DDRSS3_PHY_230_DATA
+			DDRSS3_PHY_231_DATA
+			DDRSS3_PHY_232_DATA
+			DDRSS3_PHY_233_DATA
+			DDRSS3_PHY_234_DATA
+			DDRSS3_PHY_235_DATA
+			DDRSS3_PHY_236_DATA
+			DDRSS3_PHY_237_DATA
+			DDRSS3_PHY_238_DATA
+			DDRSS3_PHY_239_DATA
+			DDRSS3_PHY_240_DATA
+			DDRSS3_PHY_241_DATA
+			DDRSS3_PHY_242_DATA
+			DDRSS3_PHY_243_DATA
+			DDRSS3_PHY_244_DATA
+			DDRSS3_PHY_245_DATA
+			DDRSS3_PHY_246_DATA
+			DDRSS3_PHY_247_DATA
+			DDRSS3_PHY_248_DATA
+			DDRSS3_PHY_249_DATA
+			DDRSS3_PHY_250_DATA
+			DDRSS3_PHY_251_DATA
+			DDRSS3_PHY_252_DATA
+			DDRSS3_PHY_253_DATA
+			DDRSS3_PHY_254_DATA
+			DDRSS3_PHY_255_DATA
+			DDRSS3_PHY_256_DATA
+			DDRSS3_PHY_257_DATA
+			DDRSS3_PHY_258_DATA
+			DDRSS3_PHY_259_DATA
+			DDRSS3_PHY_260_DATA
+			DDRSS3_PHY_261_DATA
+			DDRSS3_PHY_262_DATA
+			DDRSS3_PHY_263_DATA
+			DDRSS3_PHY_264_DATA
+			DDRSS3_PHY_265_DATA
+			DDRSS3_PHY_266_DATA
+			DDRSS3_PHY_267_DATA
+			DDRSS3_PHY_268_DATA
+			DDRSS3_PHY_269_DATA
+			DDRSS3_PHY_270_DATA
+			DDRSS3_PHY_271_DATA
+			DDRSS3_PHY_272_DATA
+			DDRSS3_PHY_273_DATA
+			DDRSS3_PHY_274_DATA
+			DDRSS3_PHY_275_DATA
+			DDRSS3_PHY_276_DATA
+			DDRSS3_PHY_277_DATA
+			DDRSS3_PHY_278_DATA
+			DDRSS3_PHY_279_DATA
+			DDRSS3_PHY_280_DATA
+			DDRSS3_PHY_281_DATA
+			DDRSS3_PHY_282_DATA
+			DDRSS3_PHY_283_DATA
+			DDRSS3_PHY_284_DATA
+			DDRSS3_PHY_285_DATA
+			DDRSS3_PHY_286_DATA
+			DDRSS3_PHY_287_DATA
+			DDRSS3_PHY_288_DATA
+			DDRSS3_PHY_289_DATA
+			DDRSS3_PHY_290_DATA
+			DDRSS3_PHY_291_DATA
+			DDRSS3_PHY_292_DATA
+			DDRSS3_PHY_293_DATA
+			DDRSS3_PHY_294_DATA
+			DDRSS3_PHY_295_DATA
+			DDRSS3_PHY_296_DATA
+			DDRSS3_PHY_297_DATA
+			DDRSS3_PHY_298_DATA
+			DDRSS3_PHY_299_DATA
+			DDRSS3_PHY_300_DATA
+			DDRSS3_PHY_301_DATA
+			DDRSS3_PHY_302_DATA
+			DDRSS3_PHY_303_DATA
+			DDRSS3_PHY_304_DATA
+			DDRSS3_PHY_305_DATA
+			DDRSS3_PHY_306_DATA
+			DDRSS3_PHY_307_DATA
+			DDRSS3_PHY_308_DATA
+			DDRSS3_PHY_309_DATA
+			DDRSS3_PHY_310_DATA
+			DDRSS3_PHY_311_DATA
+			DDRSS3_PHY_312_DATA
+			DDRSS3_PHY_313_DATA
+			DDRSS3_PHY_314_DATA
+			DDRSS3_PHY_315_DATA
+			DDRSS3_PHY_316_DATA
+			DDRSS3_PHY_317_DATA
+			DDRSS3_PHY_318_DATA
+			DDRSS3_PHY_319_DATA
+			DDRSS3_PHY_320_DATA
+			DDRSS3_PHY_321_DATA
+			DDRSS3_PHY_322_DATA
+			DDRSS3_PHY_323_DATA
+			DDRSS3_PHY_324_DATA
+			DDRSS3_PHY_325_DATA
+			DDRSS3_PHY_326_DATA
+			DDRSS3_PHY_327_DATA
+			DDRSS3_PHY_328_DATA
+			DDRSS3_PHY_329_DATA
+			DDRSS3_PHY_330_DATA
+			DDRSS3_PHY_331_DATA
+			DDRSS3_PHY_332_DATA
+			DDRSS3_PHY_333_DATA
+			DDRSS3_PHY_334_DATA
+			DDRSS3_PHY_335_DATA
+			DDRSS3_PHY_336_DATA
+			DDRSS3_PHY_337_DATA
+			DDRSS3_PHY_338_DATA
+			DDRSS3_PHY_339_DATA
+			DDRSS3_PHY_340_DATA
+			DDRSS3_PHY_341_DATA
+			DDRSS3_PHY_342_DATA
+			DDRSS3_PHY_343_DATA
+			DDRSS3_PHY_344_DATA
+			DDRSS3_PHY_345_DATA
+			DDRSS3_PHY_346_DATA
+			DDRSS3_PHY_347_DATA
+			DDRSS3_PHY_348_DATA
+			DDRSS3_PHY_349_DATA
+			DDRSS3_PHY_350_DATA
+			DDRSS3_PHY_351_DATA
+			DDRSS3_PHY_352_DATA
+			DDRSS3_PHY_353_DATA
+			DDRSS3_PHY_354_DATA
+			DDRSS3_PHY_355_DATA
+			DDRSS3_PHY_356_DATA
+			DDRSS3_PHY_357_DATA
+			DDRSS3_PHY_358_DATA
+			DDRSS3_PHY_359_DATA
+			DDRSS3_PHY_360_DATA
+			DDRSS3_PHY_361_DATA
+			DDRSS3_PHY_362_DATA
+			DDRSS3_PHY_363_DATA
+			DDRSS3_PHY_364_DATA
+			DDRSS3_PHY_365_DATA
+			DDRSS3_PHY_366_DATA
+			DDRSS3_PHY_367_DATA
+			DDRSS3_PHY_368_DATA
+			DDRSS3_PHY_369_DATA
+			DDRSS3_PHY_370_DATA
+			DDRSS3_PHY_371_DATA
+			DDRSS3_PHY_372_DATA
+			DDRSS3_PHY_373_DATA
+			DDRSS3_PHY_374_DATA
+			DDRSS3_PHY_375_DATA
+			DDRSS3_PHY_376_DATA
+			DDRSS3_PHY_377_DATA
+			DDRSS3_PHY_378_DATA
+			DDRSS3_PHY_379_DATA
+			DDRSS3_PHY_380_DATA
+			DDRSS3_PHY_381_DATA
+			DDRSS3_PHY_382_DATA
+			DDRSS3_PHY_383_DATA
+			DDRSS3_PHY_384_DATA
+			DDRSS3_PHY_385_DATA
+			DDRSS3_PHY_386_DATA
+			DDRSS3_PHY_387_DATA
+			DDRSS3_PHY_388_DATA
+			DDRSS3_PHY_389_DATA
+			DDRSS3_PHY_390_DATA
+			DDRSS3_PHY_391_DATA
+			DDRSS3_PHY_392_DATA
+			DDRSS3_PHY_393_DATA
+			DDRSS3_PHY_394_DATA
+			DDRSS3_PHY_395_DATA
+			DDRSS3_PHY_396_DATA
+			DDRSS3_PHY_397_DATA
+			DDRSS3_PHY_398_DATA
+			DDRSS3_PHY_399_DATA
+			DDRSS3_PHY_400_DATA
+			DDRSS3_PHY_401_DATA
+			DDRSS3_PHY_402_DATA
+			DDRSS3_PHY_403_DATA
+			DDRSS3_PHY_404_DATA
+			DDRSS3_PHY_405_DATA
+			DDRSS3_PHY_406_DATA
+			DDRSS3_PHY_407_DATA
+			DDRSS3_PHY_408_DATA
+			DDRSS3_PHY_409_DATA
+			DDRSS3_PHY_410_DATA
+			DDRSS3_PHY_411_DATA
+			DDRSS3_PHY_412_DATA
+			DDRSS3_PHY_413_DATA
+			DDRSS3_PHY_414_DATA
+			DDRSS3_PHY_415_DATA
+			DDRSS3_PHY_416_DATA
+			DDRSS3_PHY_417_DATA
+			DDRSS3_PHY_418_DATA
+			DDRSS3_PHY_419_DATA
+			DDRSS3_PHY_420_DATA
+			DDRSS3_PHY_421_DATA
+			DDRSS3_PHY_422_DATA
+			DDRSS3_PHY_423_DATA
+			DDRSS3_PHY_424_DATA
+			DDRSS3_PHY_425_DATA
+			DDRSS3_PHY_426_DATA
+			DDRSS3_PHY_427_DATA
+			DDRSS3_PHY_428_DATA
+			DDRSS3_PHY_429_DATA
+			DDRSS3_PHY_430_DATA
+			DDRSS3_PHY_431_DATA
+			DDRSS3_PHY_432_DATA
+			DDRSS3_PHY_433_DATA
+			DDRSS3_PHY_434_DATA
+			DDRSS3_PHY_435_DATA
+			DDRSS3_PHY_436_DATA
+			DDRSS3_PHY_437_DATA
+			DDRSS3_PHY_438_DATA
+			DDRSS3_PHY_439_DATA
+			DDRSS3_PHY_440_DATA
+			DDRSS3_PHY_441_DATA
+			DDRSS3_PHY_442_DATA
+			DDRSS3_PHY_443_DATA
+			DDRSS3_PHY_444_DATA
+			DDRSS3_PHY_445_DATA
+			DDRSS3_PHY_446_DATA
+			DDRSS3_PHY_447_DATA
+			DDRSS3_PHY_448_DATA
+			DDRSS3_PHY_449_DATA
+			DDRSS3_PHY_450_DATA
+			DDRSS3_PHY_451_DATA
+			DDRSS3_PHY_452_DATA
+			DDRSS3_PHY_453_DATA
+			DDRSS3_PHY_454_DATA
+			DDRSS3_PHY_455_DATA
+			DDRSS3_PHY_456_DATA
+			DDRSS3_PHY_457_DATA
+			DDRSS3_PHY_458_DATA
+			DDRSS3_PHY_459_DATA
+			DDRSS3_PHY_460_DATA
+			DDRSS3_PHY_461_DATA
+			DDRSS3_PHY_462_DATA
+			DDRSS3_PHY_463_DATA
+			DDRSS3_PHY_464_DATA
+			DDRSS3_PHY_465_DATA
+			DDRSS3_PHY_466_DATA
+			DDRSS3_PHY_467_DATA
+			DDRSS3_PHY_468_DATA
+			DDRSS3_PHY_469_DATA
+			DDRSS3_PHY_470_DATA
+			DDRSS3_PHY_471_DATA
+			DDRSS3_PHY_472_DATA
+			DDRSS3_PHY_473_DATA
+			DDRSS3_PHY_474_DATA
+			DDRSS3_PHY_475_DATA
+			DDRSS3_PHY_476_DATA
+			DDRSS3_PHY_477_DATA
+			DDRSS3_PHY_478_DATA
+			DDRSS3_PHY_479_DATA
+			DDRSS3_PHY_480_DATA
+			DDRSS3_PHY_481_DATA
+			DDRSS3_PHY_482_DATA
+			DDRSS3_PHY_483_DATA
+			DDRSS3_PHY_484_DATA
+			DDRSS3_PHY_485_DATA
+			DDRSS3_PHY_486_DATA
+			DDRSS3_PHY_487_DATA
+			DDRSS3_PHY_488_DATA
+			DDRSS3_PHY_489_DATA
+			DDRSS3_PHY_490_DATA
+			DDRSS3_PHY_491_DATA
+			DDRSS3_PHY_492_DATA
+			DDRSS3_PHY_493_DATA
+			DDRSS3_PHY_494_DATA
+			DDRSS3_PHY_495_DATA
+			DDRSS3_PHY_496_DATA
+			DDRSS3_PHY_497_DATA
+			DDRSS3_PHY_498_DATA
+			DDRSS3_PHY_499_DATA
+			DDRSS3_PHY_500_DATA
+			DDRSS3_PHY_501_DATA
+			DDRSS3_PHY_502_DATA
+			DDRSS3_PHY_503_DATA
+			DDRSS3_PHY_504_DATA
+			DDRSS3_PHY_505_DATA
+			DDRSS3_PHY_506_DATA
+			DDRSS3_PHY_507_DATA
+			DDRSS3_PHY_508_DATA
+			DDRSS3_PHY_509_DATA
+			DDRSS3_PHY_510_DATA
+			DDRSS3_PHY_511_DATA
+			DDRSS3_PHY_512_DATA
+			DDRSS3_PHY_513_DATA
+			DDRSS3_PHY_514_DATA
+			DDRSS3_PHY_515_DATA
+			DDRSS3_PHY_516_DATA
+			DDRSS3_PHY_517_DATA
+			DDRSS3_PHY_518_DATA
+			DDRSS3_PHY_519_DATA
+			DDRSS3_PHY_520_DATA
+			DDRSS3_PHY_521_DATA
+			DDRSS3_PHY_522_DATA
+			DDRSS3_PHY_523_DATA
+			DDRSS3_PHY_524_DATA
+			DDRSS3_PHY_525_DATA
+			DDRSS3_PHY_526_DATA
+			DDRSS3_PHY_527_DATA
+			DDRSS3_PHY_528_DATA
+			DDRSS3_PHY_529_DATA
+			DDRSS3_PHY_530_DATA
+			DDRSS3_PHY_531_DATA
+			DDRSS3_PHY_532_DATA
+			DDRSS3_PHY_533_DATA
+			DDRSS3_PHY_534_DATA
+			DDRSS3_PHY_535_DATA
+			DDRSS3_PHY_536_DATA
+			DDRSS3_PHY_537_DATA
+			DDRSS3_PHY_538_DATA
+			DDRSS3_PHY_539_DATA
+			DDRSS3_PHY_540_DATA
+			DDRSS3_PHY_541_DATA
+			DDRSS3_PHY_542_DATA
+			DDRSS3_PHY_543_DATA
+			DDRSS3_PHY_544_DATA
+			DDRSS3_PHY_545_DATA
+			DDRSS3_PHY_546_DATA
+			DDRSS3_PHY_547_DATA
+			DDRSS3_PHY_548_DATA
+			DDRSS3_PHY_549_DATA
+			DDRSS3_PHY_550_DATA
+			DDRSS3_PHY_551_DATA
+			DDRSS3_PHY_552_DATA
+			DDRSS3_PHY_553_DATA
+			DDRSS3_PHY_554_DATA
+			DDRSS3_PHY_555_DATA
+			DDRSS3_PHY_556_DATA
+			DDRSS3_PHY_557_DATA
+			DDRSS3_PHY_558_DATA
+			DDRSS3_PHY_559_DATA
+			DDRSS3_PHY_560_DATA
+			DDRSS3_PHY_561_DATA
+			DDRSS3_PHY_562_DATA
+			DDRSS3_PHY_563_DATA
+			DDRSS3_PHY_564_DATA
+			DDRSS3_PHY_565_DATA
+			DDRSS3_PHY_566_DATA
+			DDRSS3_PHY_567_DATA
+			DDRSS3_PHY_568_DATA
+			DDRSS3_PHY_569_DATA
+			DDRSS3_PHY_570_DATA
+			DDRSS3_PHY_571_DATA
+			DDRSS3_PHY_572_DATA
+			DDRSS3_PHY_573_DATA
+			DDRSS3_PHY_574_DATA
+			DDRSS3_PHY_575_DATA
+			DDRSS3_PHY_576_DATA
+			DDRSS3_PHY_577_DATA
+			DDRSS3_PHY_578_DATA
+			DDRSS3_PHY_579_DATA
+			DDRSS3_PHY_580_DATA
+			DDRSS3_PHY_581_DATA
+			DDRSS3_PHY_582_DATA
+			DDRSS3_PHY_583_DATA
+			DDRSS3_PHY_584_DATA
+			DDRSS3_PHY_585_DATA
+			DDRSS3_PHY_586_DATA
+			DDRSS3_PHY_587_DATA
+			DDRSS3_PHY_588_DATA
+			DDRSS3_PHY_589_DATA
+			DDRSS3_PHY_590_DATA
+			DDRSS3_PHY_591_DATA
+			DDRSS3_PHY_592_DATA
+			DDRSS3_PHY_593_DATA
+			DDRSS3_PHY_594_DATA
+			DDRSS3_PHY_595_DATA
+			DDRSS3_PHY_596_DATA
+			DDRSS3_PHY_597_DATA
+			DDRSS3_PHY_598_DATA
+			DDRSS3_PHY_599_DATA
+			DDRSS3_PHY_600_DATA
+			DDRSS3_PHY_601_DATA
+			DDRSS3_PHY_602_DATA
+			DDRSS3_PHY_603_DATA
+			DDRSS3_PHY_604_DATA
+			DDRSS3_PHY_605_DATA
+			DDRSS3_PHY_606_DATA
+			DDRSS3_PHY_607_DATA
+			DDRSS3_PHY_608_DATA
+			DDRSS3_PHY_609_DATA
+			DDRSS3_PHY_610_DATA
+			DDRSS3_PHY_611_DATA
+			DDRSS3_PHY_612_DATA
+			DDRSS3_PHY_613_DATA
+			DDRSS3_PHY_614_DATA
+			DDRSS3_PHY_615_DATA
+			DDRSS3_PHY_616_DATA
+			DDRSS3_PHY_617_DATA
+			DDRSS3_PHY_618_DATA
+			DDRSS3_PHY_619_DATA
+			DDRSS3_PHY_620_DATA
+			DDRSS3_PHY_621_DATA
+			DDRSS3_PHY_622_DATA
+			DDRSS3_PHY_623_DATA
+			DDRSS3_PHY_624_DATA
+			DDRSS3_PHY_625_DATA
+			DDRSS3_PHY_626_DATA
+			DDRSS3_PHY_627_DATA
+			DDRSS3_PHY_628_DATA
+			DDRSS3_PHY_629_DATA
+			DDRSS3_PHY_630_DATA
+			DDRSS3_PHY_631_DATA
+			DDRSS3_PHY_632_DATA
+			DDRSS3_PHY_633_DATA
+			DDRSS3_PHY_634_DATA
+			DDRSS3_PHY_635_DATA
+			DDRSS3_PHY_636_DATA
+			DDRSS3_PHY_637_DATA
+			DDRSS3_PHY_638_DATA
+			DDRSS3_PHY_639_DATA
+			DDRSS3_PHY_640_DATA
+			DDRSS3_PHY_641_DATA
+			DDRSS3_PHY_642_DATA
+			DDRSS3_PHY_643_DATA
+			DDRSS3_PHY_644_DATA
+			DDRSS3_PHY_645_DATA
+			DDRSS3_PHY_646_DATA
+			DDRSS3_PHY_647_DATA
+			DDRSS3_PHY_648_DATA
+			DDRSS3_PHY_649_DATA
+			DDRSS3_PHY_650_DATA
+			DDRSS3_PHY_651_DATA
+			DDRSS3_PHY_652_DATA
+			DDRSS3_PHY_653_DATA
+			DDRSS3_PHY_654_DATA
+			DDRSS3_PHY_655_DATA
+			DDRSS3_PHY_656_DATA
+			DDRSS3_PHY_657_DATA
+			DDRSS3_PHY_658_DATA
+			DDRSS3_PHY_659_DATA
+			DDRSS3_PHY_660_DATA
+			DDRSS3_PHY_661_DATA
+			DDRSS3_PHY_662_DATA
+			DDRSS3_PHY_663_DATA
+			DDRSS3_PHY_664_DATA
+			DDRSS3_PHY_665_DATA
+			DDRSS3_PHY_666_DATA
+			DDRSS3_PHY_667_DATA
+			DDRSS3_PHY_668_DATA
+			DDRSS3_PHY_669_DATA
+			DDRSS3_PHY_670_DATA
+			DDRSS3_PHY_671_DATA
+			DDRSS3_PHY_672_DATA
+			DDRSS3_PHY_673_DATA
+			DDRSS3_PHY_674_DATA
+			DDRSS3_PHY_675_DATA
+			DDRSS3_PHY_676_DATA
+			DDRSS3_PHY_677_DATA
+			DDRSS3_PHY_678_DATA
+			DDRSS3_PHY_679_DATA
+			DDRSS3_PHY_680_DATA
+			DDRSS3_PHY_681_DATA
+			DDRSS3_PHY_682_DATA
+			DDRSS3_PHY_683_DATA
+			DDRSS3_PHY_684_DATA
+			DDRSS3_PHY_685_DATA
+			DDRSS3_PHY_686_DATA
+			DDRSS3_PHY_687_DATA
+			DDRSS3_PHY_688_DATA
+			DDRSS3_PHY_689_DATA
+			DDRSS3_PHY_690_DATA
+			DDRSS3_PHY_691_DATA
+			DDRSS3_PHY_692_DATA
+			DDRSS3_PHY_693_DATA
+			DDRSS3_PHY_694_DATA
+			DDRSS3_PHY_695_DATA
+			DDRSS3_PHY_696_DATA
+			DDRSS3_PHY_697_DATA
+			DDRSS3_PHY_698_DATA
+			DDRSS3_PHY_699_DATA
+			DDRSS3_PHY_700_DATA
+			DDRSS3_PHY_701_DATA
+			DDRSS3_PHY_702_DATA
+			DDRSS3_PHY_703_DATA
+			DDRSS3_PHY_704_DATA
+			DDRSS3_PHY_705_DATA
+			DDRSS3_PHY_706_DATA
+			DDRSS3_PHY_707_DATA
+			DDRSS3_PHY_708_DATA
+			DDRSS3_PHY_709_DATA
+			DDRSS3_PHY_710_DATA
+			DDRSS3_PHY_711_DATA
+			DDRSS3_PHY_712_DATA
+			DDRSS3_PHY_713_DATA
+			DDRSS3_PHY_714_DATA
+			DDRSS3_PHY_715_DATA
+			DDRSS3_PHY_716_DATA
+			DDRSS3_PHY_717_DATA
+			DDRSS3_PHY_718_DATA
+			DDRSS3_PHY_719_DATA
+			DDRSS3_PHY_720_DATA
+			DDRSS3_PHY_721_DATA
+			DDRSS3_PHY_722_DATA
+			DDRSS3_PHY_723_DATA
+			DDRSS3_PHY_724_DATA
+			DDRSS3_PHY_725_DATA
+			DDRSS3_PHY_726_DATA
+			DDRSS3_PHY_727_DATA
+			DDRSS3_PHY_728_DATA
+			DDRSS3_PHY_729_DATA
+			DDRSS3_PHY_730_DATA
+			DDRSS3_PHY_731_DATA
+			DDRSS3_PHY_732_DATA
+			DDRSS3_PHY_733_DATA
+			DDRSS3_PHY_734_DATA
+			DDRSS3_PHY_735_DATA
+			DDRSS3_PHY_736_DATA
+			DDRSS3_PHY_737_DATA
+			DDRSS3_PHY_738_DATA
+			DDRSS3_PHY_739_DATA
+			DDRSS3_PHY_740_DATA
+			DDRSS3_PHY_741_DATA
+			DDRSS3_PHY_742_DATA
+			DDRSS3_PHY_743_DATA
+			DDRSS3_PHY_744_DATA
+			DDRSS3_PHY_745_DATA
+			DDRSS3_PHY_746_DATA
+			DDRSS3_PHY_747_DATA
+			DDRSS3_PHY_748_DATA
+			DDRSS3_PHY_749_DATA
+			DDRSS3_PHY_750_DATA
+			DDRSS3_PHY_751_DATA
+			DDRSS3_PHY_752_DATA
+			DDRSS3_PHY_753_DATA
+			DDRSS3_PHY_754_DATA
+			DDRSS3_PHY_755_DATA
+			DDRSS3_PHY_756_DATA
+			DDRSS3_PHY_757_DATA
+			DDRSS3_PHY_758_DATA
+			DDRSS3_PHY_759_DATA
+			DDRSS3_PHY_760_DATA
+			DDRSS3_PHY_761_DATA
+			DDRSS3_PHY_762_DATA
+			DDRSS3_PHY_763_DATA
+			DDRSS3_PHY_764_DATA
+			DDRSS3_PHY_765_DATA
+			DDRSS3_PHY_766_DATA
+			DDRSS3_PHY_767_DATA
+			DDRSS3_PHY_768_DATA
+			DDRSS3_PHY_769_DATA
+			DDRSS3_PHY_770_DATA
+			DDRSS3_PHY_771_DATA
+			DDRSS3_PHY_772_DATA
+			DDRSS3_PHY_773_DATA
+			DDRSS3_PHY_774_DATA
+			DDRSS3_PHY_775_DATA
+			DDRSS3_PHY_776_DATA
+			DDRSS3_PHY_777_DATA
+			DDRSS3_PHY_778_DATA
+			DDRSS3_PHY_779_DATA
+			DDRSS3_PHY_780_DATA
+			DDRSS3_PHY_781_DATA
+			DDRSS3_PHY_782_DATA
+			DDRSS3_PHY_783_DATA
+			DDRSS3_PHY_784_DATA
+			DDRSS3_PHY_785_DATA
+			DDRSS3_PHY_786_DATA
+			DDRSS3_PHY_787_DATA
+			DDRSS3_PHY_788_DATA
+			DDRSS3_PHY_789_DATA
+			DDRSS3_PHY_790_DATA
+			DDRSS3_PHY_791_DATA
+			DDRSS3_PHY_792_DATA
+			DDRSS3_PHY_793_DATA
+			DDRSS3_PHY_794_DATA
+			DDRSS3_PHY_795_DATA
+			DDRSS3_PHY_796_DATA
+			DDRSS3_PHY_797_DATA
+			DDRSS3_PHY_798_DATA
+			DDRSS3_PHY_799_DATA
+			DDRSS3_PHY_800_DATA
+			DDRSS3_PHY_801_DATA
+			DDRSS3_PHY_802_DATA
+			DDRSS3_PHY_803_DATA
+			DDRSS3_PHY_804_DATA
+			DDRSS3_PHY_805_DATA
+			DDRSS3_PHY_806_DATA
+			DDRSS3_PHY_807_DATA
+			DDRSS3_PHY_808_DATA
+			DDRSS3_PHY_809_DATA
+			DDRSS3_PHY_810_DATA
+			DDRSS3_PHY_811_DATA
+			DDRSS3_PHY_812_DATA
+			DDRSS3_PHY_813_DATA
+			DDRSS3_PHY_814_DATA
+			DDRSS3_PHY_815_DATA
+			DDRSS3_PHY_816_DATA
+			DDRSS3_PHY_817_DATA
+			DDRSS3_PHY_818_DATA
+			DDRSS3_PHY_819_DATA
+			DDRSS3_PHY_820_DATA
+			DDRSS3_PHY_821_DATA
+			DDRSS3_PHY_822_DATA
+			DDRSS3_PHY_823_DATA
+			DDRSS3_PHY_824_DATA
+			DDRSS3_PHY_825_DATA
+			DDRSS3_PHY_826_DATA
+			DDRSS3_PHY_827_DATA
+			DDRSS3_PHY_828_DATA
+			DDRSS3_PHY_829_DATA
+			DDRSS3_PHY_830_DATA
+			DDRSS3_PHY_831_DATA
+			DDRSS3_PHY_832_DATA
+			DDRSS3_PHY_833_DATA
+			DDRSS3_PHY_834_DATA
+			DDRSS3_PHY_835_DATA
+			DDRSS3_PHY_836_DATA
+			DDRSS3_PHY_837_DATA
+			DDRSS3_PHY_838_DATA
+			DDRSS3_PHY_839_DATA
+			DDRSS3_PHY_840_DATA
+			DDRSS3_PHY_841_DATA
+			DDRSS3_PHY_842_DATA
+			DDRSS3_PHY_843_DATA
+			DDRSS3_PHY_844_DATA
+			DDRSS3_PHY_845_DATA
+			DDRSS3_PHY_846_DATA
+			DDRSS3_PHY_847_DATA
+			DDRSS3_PHY_848_DATA
+			DDRSS3_PHY_849_DATA
+			DDRSS3_PHY_850_DATA
+			DDRSS3_PHY_851_DATA
+			DDRSS3_PHY_852_DATA
+			DDRSS3_PHY_853_DATA
+			DDRSS3_PHY_854_DATA
+			DDRSS3_PHY_855_DATA
+			DDRSS3_PHY_856_DATA
+			DDRSS3_PHY_857_DATA
+			DDRSS3_PHY_858_DATA
+			DDRSS3_PHY_859_DATA
+			DDRSS3_PHY_860_DATA
+			DDRSS3_PHY_861_DATA
+			DDRSS3_PHY_862_DATA
+			DDRSS3_PHY_863_DATA
+			DDRSS3_PHY_864_DATA
+			DDRSS3_PHY_865_DATA
+			DDRSS3_PHY_866_DATA
+			DDRSS3_PHY_867_DATA
+			DDRSS3_PHY_868_DATA
+			DDRSS3_PHY_869_DATA
+			DDRSS3_PHY_870_DATA
+			DDRSS3_PHY_871_DATA
+			DDRSS3_PHY_872_DATA
+			DDRSS3_PHY_873_DATA
+			DDRSS3_PHY_874_DATA
+			DDRSS3_PHY_875_DATA
+			DDRSS3_PHY_876_DATA
+			DDRSS3_PHY_877_DATA
+			DDRSS3_PHY_878_DATA
+			DDRSS3_PHY_879_DATA
+			DDRSS3_PHY_880_DATA
+			DDRSS3_PHY_881_DATA
+			DDRSS3_PHY_882_DATA
+			DDRSS3_PHY_883_DATA
+			DDRSS3_PHY_884_DATA
+			DDRSS3_PHY_885_DATA
+			DDRSS3_PHY_886_DATA
+			DDRSS3_PHY_887_DATA
+			DDRSS3_PHY_888_DATA
+			DDRSS3_PHY_889_DATA
+			DDRSS3_PHY_890_DATA
+			DDRSS3_PHY_891_DATA
+			DDRSS3_PHY_892_DATA
+			DDRSS3_PHY_893_DATA
+			DDRSS3_PHY_894_DATA
+			DDRSS3_PHY_895_DATA
+			DDRSS3_PHY_896_DATA
+			DDRSS3_PHY_897_DATA
+			DDRSS3_PHY_898_DATA
+			DDRSS3_PHY_899_DATA
+			DDRSS3_PHY_900_DATA
+			DDRSS3_PHY_901_DATA
+			DDRSS3_PHY_902_DATA
+			DDRSS3_PHY_903_DATA
+			DDRSS3_PHY_904_DATA
+			DDRSS3_PHY_905_DATA
+			DDRSS3_PHY_906_DATA
+			DDRSS3_PHY_907_DATA
+			DDRSS3_PHY_908_DATA
+			DDRSS3_PHY_909_DATA
+			DDRSS3_PHY_910_DATA
+			DDRSS3_PHY_911_DATA
+			DDRSS3_PHY_912_DATA
+			DDRSS3_PHY_913_DATA
+			DDRSS3_PHY_914_DATA
+			DDRSS3_PHY_915_DATA
+			DDRSS3_PHY_916_DATA
+			DDRSS3_PHY_917_DATA
+			DDRSS3_PHY_918_DATA
+			DDRSS3_PHY_919_DATA
+			DDRSS3_PHY_920_DATA
+			DDRSS3_PHY_921_DATA
+			DDRSS3_PHY_922_DATA
+			DDRSS3_PHY_923_DATA
+			DDRSS3_PHY_924_DATA
+			DDRSS3_PHY_925_DATA
+			DDRSS3_PHY_926_DATA
+			DDRSS3_PHY_927_DATA
+			DDRSS3_PHY_928_DATA
+			DDRSS3_PHY_929_DATA
+			DDRSS3_PHY_930_DATA
+			DDRSS3_PHY_931_DATA
+			DDRSS3_PHY_932_DATA
+			DDRSS3_PHY_933_DATA
+			DDRSS3_PHY_934_DATA
+			DDRSS3_PHY_935_DATA
+			DDRSS3_PHY_936_DATA
+			DDRSS3_PHY_937_DATA
+			DDRSS3_PHY_938_DATA
+			DDRSS3_PHY_939_DATA
+			DDRSS3_PHY_940_DATA
+			DDRSS3_PHY_941_DATA
+			DDRSS3_PHY_942_DATA
+			DDRSS3_PHY_943_DATA
+			DDRSS3_PHY_944_DATA
+			DDRSS3_PHY_945_DATA
+			DDRSS3_PHY_946_DATA
+			DDRSS3_PHY_947_DATA
+			DDRSS3_PHY_948_DATA
+			DDRSS3_PHY_949_DATA
+			DDRSS3_PHY_950_DATA
+			DDRSS3_PHY_951_DATA
+			DDRSS3_PHY_952_DATA
+			DDRSS3_PHY_953_DATA
+			DDRSS3_PHY_954_DATA
+			DDRSS3_PHY_955_DATA
+			DDRSS3_PHY_956_DATA
+			DDRSS3_PHY_957_DATA
+			DDRSS3_PHY_958_DATA
+			DDRSS3_PHY_959_DATA
+			DDRSS3_PHY_960_DATA
+			DDRSS3_PHY_961_DATA
+			DDRSS3_PHY_962_DATA
+			DDRSS3_PHY_963_DATA
+			DDRSS3_PHY_964_DATA
+			DDRSS3_PHY_965_DATA
+			DDRSS3_PHY_966_DATA
+			DDRSS3_PHY_967_DATA
+			DDRSS3_PHY_968_DATA
+			DDRSS3_PHY_969_DATA
+			DDRSS3_PHY_970_DATA
+			DDRSS3_PHY_971_DATA
+			DDRSS3_PHY_972_DATA
+			DDRSS3_PHY_973_DATA
+			DDRSS3_PHY_974_DATA
+			DDRSS3_PHY_975_DATA
+			DDRSS3_PHY_976_DATA
+			DDRSS3_PHY_977_DATA
+			DDRSS3_PHY_978_DATA
+			DDRSS3_PHY_979_DATA
+			DDRSS3_PHY_980_DATA
+			DDRSS3_PHY_981_DATA
+			DDRSS3_PHY_982_DATA
+			DDRSS3_PHY_983_DATA
+			DDRSS3_PHY_984_DATA
+			DDRSS3_PHY_985_DATA
+			DDRSS3_PHY_986_DATA
+			DDRSS3_PHY_987_DATA
+			DDRSS3_PHY_988_DATA
+			DDRSS3_PHY_989_DATA
+			DDRSS3_PHY_990_DATA
+			DDRSS3_PHY_991_DATA
+			DDRSS3_PHY_992_DATA
+			DDRSS3_PHY_993_DATA
+			DDRSS3_PHY_994_DATA
+			DDRSS3_PHY_995_DATA
+			DDRSS3_PHY_996_DATA
+			DDRSS3_PHY_997_DATA
+			DDRSS3_PHY_998_DATA
+			DDRSS3_PHY_999_DATA
+			DDRSS3_PHY_1000_DATA
+			DDRSS3_PHY_1001_DATA
+			DDRSS3_PHY_1002_DATA
+			DDRSS3_PHY_1003_DATA
+			DDRSS3_PHY_1004_DATA
+			DDRSS3_PHY_1005_DATA
+			DDRSS3_PHY_1006_DATA
+			DDRSS3_PHY_1007_DATA
+			DDRSS3_PHY_1008_DATA
+			DDRSS3_PHY_1009_DATA
+			DDRSS3_PHY_1010_DATA
+			DDRSS3_PHY_1011_DATA
+			DDRSS3_PHY_1012_DATA
+			DDRSS3_PHY_1013_DATA
+			DDRSS3_PHY_1014_DATA
+			DDRSS3_PHY_1015_DATA
+			DDRSS3_PHY_1016_DATA
+			DDRSS3_PHY_1017_DATA
+			DDRSS3_PHY_1018_DATA
+			DDRSS3_PHY_1019_DATA
+			DDRSS3_PHY_1020_DATA
+			DDRSS3_PHY_1021_DATA
+			DDRSS3_PHY_1022_DATA
+			DDRSS3_PHY_1023_DATA
+			DDRSS3_PHY_1024_DATA
+			DDRSS3_PHY_1025_DATA
+			DDRSS3_PHY_1026_DATA
+			DDRSS3_PHY_1027_DATA
+			DDRSS3_PHY_1028_DATA
+			DDRSS3_PHY_1029_DATA
+			DDRSS3_PHY_1030_DATA
+			DDRSS3_PHY_1031_DATA
+			DDRSS3_PHY_1032_DATA
+			DDRSS3_PHY_1033_DATA
+			DDRSS3_PHY_1034_DATA
+			DDRSS3_PHY_1035_DATA
+			DDRSS3_PHY_1036_DATA
+			DDRSS3_PHY_1037_DATA
+			DDRSS3_PHY_1038_DATA
+			DDRSS3_PHY_1039_DATA
+			DDRSS3_PHY_1040_DATA
+			DDRSS3_PHY_1041_DATA
+			DDRSS3_PHY_1042_DATA
+			DDRSS3_PHY_1043_DATA
+			DDRSS3_PHY_1044_DATA
+			DDRSS3_PHY_1045_DATA
+			DDRSS3_PHY_1046_DATA
+			DDRSS3_PHY_1047_DATA
+			DDRSS3_PHY_1048_DATA
+			DDRSS3_PHY_1049_DATA
+			DDRSS3_PHY_1050_DATA
+			DDRSS3_PHY_1051_DATA
+			DDRSS3_PHY_1052_DATA
+			DDRSS3_PHY_1053_DATA
+			DDRSS3_PHY_1054_DATA
+			DDRSS3_PHY_1055_DATA
+			DDRSS3_PHY_1056_DATA
+			DDRSS3_PHY_1057_DATA
+			DDRSS3_PHY_1058_DATA
+			DDRSS3_PHY_1059_DATA
+			DDRSS3_PHY_1060_DATA
+			DDRSS3_PHY_1061_DATA
+			DDRSS3_PHY_1062_DATA
+			DDRSS3_PHY_1063_DATA
+			DDRSS3_PHY_1064_DATA
+			DDRSS3_PHY_1065_DATA
+			DDRSS3_PHY_1066_DATA
+			DDRSS3_PHY_1067_DATA
+			DDRSS3_PHY_1068_DATA
+			DDRSS3_PHY_1069_DATA
+			DDRSS3_PHY_1070_DATA
+			DDRSS3_PHY_1071_DATA
+			DDRSS3_PHY_1072_DATA
+			DDRSS3_PHY_1073_DATA
+			DDRSS3_PHY_1074_DATA
+			DDRSS3_PHY_1075_DATA
+			DDRSS3_PHY_1076_DATA
+			DDRSS3_PHY_1077_DATA
+			DDRSS3_PHY_1078_DATA
+			DDRSS3_PHY_1079_DATA
+			DDRSS3_PHY_1080_DATA
+			DDRSS3_PHY_1081_DATA
+			DDRSS3_PHY_1082_DATA
+			DDRSS3_PHY_1083_DATA
+			DDRSS3_PHY_1084_DATA
+			DDRSS3_PHY_1085_DATA
+			DDRSS3_PHY_1086_DATA
+			DDRSS3_PHY_1087_DATA
+			DDRSS3_PHY_1088_DATA
+			DDRSS3_PHY_1089_DATA
+			DDRSS3_PHY_1090_DATA
+			DDRSS3_PHY_1091_DATA
+			DDRSS3_PHY_1092_DATA
+			DDRSS3_PHY_1093_DATA
+			DDRSS3_PHY_1094_DATA
+			DDRSS3_PHY_1095_DATA
+			DDRSS3_PHY_1096_DATA
+			DDRSS3_PHY_1097_DATA
+			DDRSS3_PHY_1098_DATA
+			DDRSS3_PHY_1099_DATA
+			DDRSS3_PHY_1100_DATA
+			DDRSS3_PHY_1101_DATA
+			DDRSS3_PHY_1102_DATA
+			DDRSS3_PHY_1103_DATA
+			DDRSS3_PHY_1104_DATA
+			DDRSS3_PHY_1105_DATA
+			DDRSS3_PHY_1106_DATA
+			DDRSS3_PHY_1107_DATA
+			DDRSS3_PHY_1108_DATA
+			DDRSS3_PHY_1109_DATA
+			DDRSS3_PHY_1110_DATA
+			DDRSS3_PHY_1111_DATA
+			DDRSS3_PHY_1112_DATA
+			DDRSS3_PHY_1113_DATA
+			DDRSS3_PHY_1114_DATA
+			DDRSS3_PHY_1115_DATA
+			DDRSS3_PHY_1116_DATA
+			DDRSS3_PHY_1117_DATA
+			DDRSS3_PHY_1118_DATA
+			DDRSS3_PHY_1119_DATA
+			DDRSS3_PHY_1120_DATA
+			DDRSS3_PHY_1121_DATA
+			DDRSS3_PHY_1122_DATA
+			DDRSS3_PHY_1123_DATA
+			DDRSS3_PHY_1124_DATA
+			DDRSS3_PHY_1125_DATA
+			DDRSS3_PHY_1126_DATA
+			DDRSS3_PHY_1127_DATA
+			DDRSS3_PHY_1128_DATA
+			DDRSS3_PHY_1129_DATA
+			DDRSS3_PHY_1130_DATA
+			DDRSS3_PHY_1131_DATA
+			DDRSS3_PHY_1132_DATA
+			DDRSS3_PHY_1133_DATA
+			DDRSS3_PHY_1134_DATA
+			DDRSS3_PHY_1135_DATA
+			DDRSS3_PHY_1136_DATA
+			DDRSS3_PHY_1137_DATA
+			DDRSS3_PHY_1138_DATA
+			DDRSS3_PHY_1139_DATA
+			DDRSS3_PHY_1140_DATA
+			DDRSS3_PHY_1141_DATA
+			DDRSS3_PHY_1142_DATA
+			DDRSS3_PHY_1143_DATA
+			DDRSS3_PHY_1144_DATA
+			DDRSS3_PHY_1145_DATA
+			DDRSS3_PHY_1146_DATA
+			DDRSS3_PHY_1147_DATA
+			DDRSS3_PHY_1148_DATA
+			DDRSS3_PHY_1149_DATA
+			DDRSS3_PHY_1150_DATA
+			DDRSS3_PHY_1151_DATA
+			DDRSS3_PHY_1152_DATA
+			DDRSS3_PHY_1153_DATA
+			DDRSS3_PHY_1154_DATA
+			DDRSS3_PHY_1155_DATA
+			DDRSS3_PHY_1156_DATA
+			DDRSS3_PHY_1157_DATA
+			DDRSS3_PHY_1158_DATA
+			DDRSS3_PHY_1159_DATA
+			DDRSS3_PHY_1160_DATA
+			DDRSS3_PHY_1161_DATA
+			DDRSS3_PHY_1162_DATA
+			DDRSS3_PHY_1163_DATA
+			DDRSS3_PHY_1164_DATA
+			DDRSS3_PHY_1165_DATA
+			DDRSS3_PHY_1166_DATA
+			DDRSS3_PHY_1167_DATA
+			DDRSS3_PHY_1168_DATA
+			DDRSS3_PHY_1169_DATA
+			DDRSS3_PHY_1170_DATA
+			DDRSS3_PHY_1171_DATA
+			DDRSS3_PHY_1172_DATA
+			DDRSS3_PHY_1173_DATA
+			DDRSS3_PHY_1174_DATA
+			DDRSS3_PHY_1175_DATA
+			DDRSS3_PHY_1176_DATA
+			DDRSS3_PHY_1177_DATA
+			DDRSS3_PHY_1178_DATA
+			DDRSS3_PHY_1179_DATA
+			DDRSS3_PHY_1180_DATA
+			DDRSS3_PHY_1181_DATA
+			DDRSS3_PHY_1182_DATA
+			DDRSS3_PHY_1183_DATA
+			DDRSS3_PHY_1184_DATA
+			DDRSS3_PHY_1185_DATA
+			DDRSS3_PHY_1186_DATA
+			DDRSS3_PHY_1187_DATA
+			DDRSS3_PHY_1188_DATA
+			DDRSS3_PHY_1189_DATA
+			DDRSS3_PHY_1190_DATA
+			DDRSS3_PHY_1191_DATA
+			DDRSS3_PHY_1192_DATA
+			DDRSS3_PHY_1193_DATA
+			DDRSS3_PHY_1194_DATA
+			DDRSS3_PHY_1195_DATA
+			DDRSS3_PHY_1196_DATA
+			DDRSS3_PHY_1197_DATA
+			DDRSS3_PHY_1198_DATA
+			DDRSS3_PHY_1199_DATA
+			DDRSS3_PHY_1200_DATA
+			DDRSS3_PHY_1201_DATA
+			DDRSS3_PHY_1202_DATA
+			DDRSS3_PHY_1203_DATA
+			DDRSS3_PHY_1204_DATA
+			DDRSS3_PHY_1205_DATA
+			DDRSS3_PHY_1206_DATA
+			DDRSS3_PHY_1207_DATA
+			DDRSS3_PHY_1208_DATA
+			DDRSS3_PHY_1209_DATA
+			DDRSS3_PHY_1210_DATA
+			DDRSS3_PHY_1211_DATA
+			DDRSS3_PHY_1212_DATA
+			DDRSS3_PHY_1213_DATA
+			DDRSS3_PHY_1214_DATA
+			DDRSS3_PHY_1215_DATA
+			DDRSS3_PHY_1216_DATA
+			DDRSS3_PHY_1217_DATA
+			DDRSS3_PHY_1218_DATA
+			DDRSS3_PHY_1219_DATA
+			DDRSS3_PHY_1220_DATA
+			DDRSS3_PHY_1221_DATA
+			DDRSS3_PHY_1222_DATA
+			DDRSS3_PHY_1223_DATA
+			DDRSS3_PHY_1224_DATA
+			DDRSS3_PHY_1225_DATA
+			DDRSS3_PHY_1226_DATA
+			DDRSS3_PHY_1227_DATA
+			DDRSS3_PHY_1228_DATA
+			DDRSS3_PHY_1229_DATA
+			DDRSS3_PHY_1230_DATA
+			DDRSS3_PHY_1231_DATA
+			DDRSS3_PHY_1232_DATA
+			DDRSS3_PHY_1233_DATA
+			DDRSS3_PHY_1234_DATA
+			DDRSS3_PHY_1235_DATA
+			DDRSS3_PHY_1236_DATA
+			DDRSS3_PHY_1237_DATA
+			DDRSS3_PHY_1238_DATA
+			DDRSS3_PHY_1239_DATA
+			DDRSS3_PHY_1240_DATA
+			DDRSS3_PHY_1241_DATA
+			DDRSS3_PHY_1242_DATA
+			DDRSS3_PHY_1243_DATA
+			DDRSS3_PHY_1244_DATA
+			DDRSS3_PHY_1245_DATA
+			DDRSS3_PHY_1246_DATA
+			DDRSS3_PHY_1247_DATA
+			DDRSS3_PHY_1248_DATA
+			DDRSS3_PHY_1249_DATA
+			DDRSS3_PHY_1250_DATA
+			DDRSS3_PHY_1251_DATA
+			DDRSS3_PHY_1252_DATA
+			DDRSS3_PHY_1253_DATA
+			DDRSS3_PHY_1254_DATA
+			DDRSS3_PHY_1255_DATA
+			DDRSS3_PHY_1256_DATA
+			DDRSS3_PHY_1257_DATA
+			DDRSS3_PHY_1258_DATA
+			DDRSS3_PHY_1259_DATA
+			DDRSS3_PHY_1260_DATA
+			DDRSS3_PHY_1261_DATA
+			DDRSS3_PHY_1262_DATA
+			DDRSS3_PHY_1263_DATA
+			DDRSS3_PHY_1264_DATA
+			DDRSS3_PHY_1265_DATA
+			DDRSS3_PHY_1266_DATA
+			DDRSS3_PHY_1267_DATA
+			DDRSS3_PHY_1268_DATA
+			DDRSS3_PHY_1269_DATA
+			DDRSS3_PHY_1270_DATA
+			DDRSS3_PHY_1271_DATA
+			DDRSS3_PHY_1272_DATA
+			DDRSS3_PHY_1273_DATA
+			DDRSS3_PHY_1274_DATA
+			DDRSS3_PHY_1275_DATA
+			DDRSS3_PHY_1276_DATA
+			DDRSS3_PHY_1277_DATA
+			DDRSS3_PHY_1278_DATA
+			DDRSS3_PHY_1279_DATA
+			DDRSS3_PHY_1280_DATA
+			DDRSS3_PHY_1281_DATA
+			DDRSS3_PHY_1282_DATA
+			DDRSS3_PHY_1283_DATA
+			DDRSS3_PHY_1284_DATA
+			DDRSS3_PHY_1285_DATA
+			DDRSS3_PHY_1286_DATA
+			DDRSS3_PHY_1287_DATA
+			DDRSS3_PHY_1288_DATA
+			DDRSS3_PHY_1289_DATA
+			DDRSS3_PHY_1290_DATA
+			DDRSS3_PHY_1291_DATA
+			DDRSS3_PHY_1292_DATA
+			DDRSS3_PHY_1293_DATA
+			DDRSS3_PHY_1294_DATA
+			DDRSS3_PHY_1295_DATA
+			DDRSS3_PHY_1296_DATA
+			DDRSS3_PHY_1297_DATA
+			DDRSS3_PHY_1298_DATA
+			DDRSS3_PHY_1299_DATA
+			DDRSS3_PHY_1300_DATA
+			DDRSS3_PHY_1301_DATA
+			DDRSS3_PHY_1302_DATA
+			DDRSS3_PHY_1303_DATA
+			DDRSS3_PHY_1304_DATA
+			DDRSS3_PHY_1305_DATA
+			DDRSS3_PHY_1306_DATA
+			DDRSS3_PHY_1307_DATA
+			DDRSS3_PHY_1308_DATA
+			DDRSS3_PHY_1309_DATA
+			DDRSS3_PHY_1310_DATA
+			DDRSS3_PHY_1311_DATA
+			DDRSS3_PHY_1312_DATA
+			DDRSS3_PHY_1313_DATA
+			DDRSS3_PHY_1314_DATA
+			DDRSS3_PHY_1315_DATA
+			DDRSS3_PHY_1316_DATA
+			DDRSS3_PHY_1317_DATA
+			DDRSS3_PHY_1318_DATA
+			DDRSS3_PHY_1319_DATA
+			DDRSS3_PHY_1320_DATA
+			DDRSS3_PHY_1321_DATA
+			DDRSS3_PHY_1322_DATA
+			DDRSS3_PHY_1323_DATA
+			DDRSS3_PHY_1324_DATA
+			DDRSS3_PHY_1325_DATA
+			DDRSS3_PHY_1326_DATA
+			DDRSS3_PHY_1327_DATA
+			DDRSS3_PHY_1328_DATA
+			DDRSS3_PHY_1329_DATA
+			DDRSS3_PHY_1330_DATA
+			DDRSS3_PHY_1331_DATA
+			DDRSS3_PHY_1332_DATA
+			DDRSS3_PHY_1333_DATA
+			DDRSS3_PHY_1334_DATA
+			DDRSS3_PHY_1335_DATA
+			DDRSS3_PHY_1336_DATA
+			DDRSS3_PHY_1337_DATA
+			DDRSS3_PHY_1338_DATA
+			DDRSS3_PHY_1339_DATA
+			DDRSS3_PHY_1340_DATA
+			DDRSS3_PHY_1341_DATA
+			DDRSS3_PHY_1342_DATA
+			DDRSS3_PHY_1343_DATA
+			DDRSS3_PHY_1344_DATA
+			DDRSS3_PHY_1345_DATA
+			DDRSS3_PHY_1346_DATA
+			DDRSS3_PHY_1347_DATA
+			DDRSS3_PHY_1348_DATA
+			DDRSS3_PHY_1349_DATA
+			DDRSS3_PHY_1350_DATA
+			DDRSS3_PHY_1351_DATA
+			DDRSS3_PHY_1352_DATA
+			DDRSS3_PHY_1353_DATA
+			DDRSS3_PHY_1354_DATA
+			DDRSS3_PHY_1355_DATA
+			DDRSS3_PHY_1356_DATA
+			DDRSS3_PHY_1357_DATA
+			DDRSS3_PHY_1358_DATA
+			DDRSS3_PHY_1359_DATA
+			DDRSS3_PHY_1360_DATA
+			DDRSS3_PHY_1361_DATA
+			DDRSS3_PHY_1362_DATA
+			DDRSS3_PHY_1363_DATA
+			DDRSS3_PHY_1364_DATA
+			DDRSS3_PHY_1365_DATA
+			DDRSS3_PHY_1366_DATA
+			DDRSS3_PHY_1367_DATA
+			DDRSS3_PHY_1368_DATA
+			DDRSS3_PHY_1369_DATA
+			DDRSS3_PHY_1370_DATA
+			DDRSS3_PHY_1371_DATA
+			DDRSS3_PHY_1372_DATA
+			DDRSS3_PHY_1373_DATA
+			DDRSS3_PHY_1374_DATA
+			DDRSS3_PHY_1375_DATA
+			DDRSS3_PHY_1376_DATA
+			DDRSS3_PHY_1377_DATA
+			DDRSS3_PHY_1378_DATA
+			DDRSS3_PHY_1379_DATA
+			DDRSS3_PHY_1380_DATA
+			DDRSS3_PHY_1381_DATA
+			DDRSS3_PHY_1382_DATA
+			DDRSS3_PHY_1383_DATA
+			DDRSS3_PHY_1384_DATA
+			DDRSS3_PHY_1385_DATA
+			DDRSS3_PHY_1386_DATA
+			DDRSS3_PHY_1387_DATA
+			DDRSS3_PHY_1388_DATA
+			DDRSS3_PHY_1389_DATA
+			DDRSS3_PHY_1390_DATA
+			DDRSS3_PHY_1391_DATA
+			DDRSS3_PHY_1392_DATA
+			DDRSS3_PHY_1393_DATA
+			DDRSS3_PHY_1394_DATA
+			DDRSS3_PHY_1395_DATA
+			DDRSS3_PHY_1396_DATA
+			DDRSS3_PHY_1397_DATA
+			DDRSS3_PHY_1398_DATA
+			DDRSS3_PHY_1399_DATA
+			DDRSS3_PHY_1400_DATA
+			DDRSS3_PHY_1401_DATA
+			DDRSS3_PHY_1402_DATA
+			DDRSS3_PHY_1403_DATA
+			DDRSS3_PHY_1404_DATA
+			DDRSS3_PHY_1405_DATA
+			DDRSS3_PHY_1406_DATA
+			DDRSS3_PHY_1407_DATA
+			DDRSS3_PHY_1408_DATA
+			DDRSS3_PHY_1409_DATA
+			DDRSS3_PHY_1410_DATA
+			DDRSS3_PHY_1411_DATA
+			DDRSS3_PHY_1412_DATA
+			DDRSS3_PHY_1413_DATA
+			DDRSS3_PHY_1414_DATA
+			DDRSS3_PHY_1415_DATA
+			DDRSS3_PHY_1416_DATA
+			DDRSS3_PHY_1417_DATA
+			DDRSS3_PHY_1418_DATA
+			DDRSS3_PHY_1419_DATA
+			DDRSS3_PHY_1420_DATA
+			DDRSS3_PHY_1421_DATA
+			DDRSS3_PHY_1422_DATA
+		>;
 	};
 };
diff --git a/arch/arm/dts/k3-j784s4-evm-u-boot.dtsi b/arch/arm/dts/k3-j784s4-evm-u-boot.dtsi
index 8f0307321e8..8a60d7c6107 100644
--- a/arch/arm/dts/k3-j784s4-evm-u-boot.dtsi
+++ b/arch/arm/dts/k3-j784s4-evm-u-boot.dtsi
@@ -3,8 +3,83 @@
  * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/
  */
 
+#define SPL_BOARD_DTB "spl/dts/ti/k3-j784s4-evm.dtb"
+#define BOARD_DESCRIPTION "k3-j784s4-evm"
+#define UBOOT_BOARD_DESCRIPTION "U-Boot for J784S4 board"
+
 #include "k3-j784s4-binman.dtsi"
 
+#if defined(CONFIG_CPU_V7R)
+
+&binman {
+	tiboot3-j784s4-hs {
+		insert-template = <&tiboot3_j784s4_hs>;
+		filename = "tiboot3-j784s4-hs-evm.bin";
+	};
+
+	tiboot3-j784s4-hs-fs {
+		insert-template = <&tiboot3_j784s4_hs_fs>;
+		filename = "tiboot3-j784s4-hs-fs-evm.bin";
+	};
+
+	tiboot3-j784s4-gp {
+		insert-template = <&tiboot3_j784s4_gp>;
+		filename = "tiboot3-j784s4-gp-evm.bin";
+		symlink = "tiboot3.bin";
+	};
+};
+
+&ti_fs_gp {
+	filename = "ti-sysfw/ti-fs-firmware-j784s4-gp.bin";
+};
+
+&ti_fs_enc {
+	filename = "ti-sysfw/ti-fs-firmware-j784s4-hs-enc.bin";
+};
+
+&sysfw_inner_cert {
+	filename = "ti-sysfw/ti-fs-firmware-j784s4-hs-cert.bin";
+};
+
+&ti_fs_enc_fs {
+	filename = "ti-sysfw/ti-fs-firmware-j784s4-hs-fs-enc.bin";
+};
+
+&sysfw_inner_cert_fs {
+	filename = "ti-sysfw/ti-fs-firmware-j784s4-hs-fs-cert.bin";
+};
+
+#else // CONFIG_ARM64
+
+&binman {
+	ti-dm {
+		filename = "ti-dm.bin";
+
+		blob-ext {
+			filename = "ti-dm/j784s4/ipc_echo_testb_mcu1_0_release_strip.xer5f";
+			optional;
+		};
+	};
+
+	tispl {
+		insert-template = <&ti_spl>;
+	};
+
+	u-boot {
+		insert-template = <&u_boot>;
+	};
+
+	tispl-unsigned {
+		insert-template = <&ti_spl_unsigned>;
+	};
+
+	u-boot-unsigned {
+		insert-template = <&u_boot_unsigned>;
+	};
+};
+
+#endif
+
 / {
 	memory@80000000 {
 		bootph-all;
diff --git a/arch/arm/dts/k3-j784s4-j742s2-ddr.dtsi b/arch/arm/dts/k3-j784s4-j742s2-ddr.dtsi
new file mode 100644
index 00000000000..c03eddcb560
--- /dev/null
+++ b/arch/arm/dts/k3-j784s4-j742s2-ddr.dtsi
@@ -0,0 +1,4448 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+&main_navss {
+	ranges = <0x00 0x00114000 0x00 0x00114000 0x00 0x00000100>, // ctrl_mmr_lpr
+		 <0x00 0x02990000 0x00 0x02990000 0x00 0x00004000>, // ddr0 cfg
+		 <0x00 0x029b0000 0x00 0x029b0000 0x00 0x00004000>, // ddr1 cfg
+		 <0x00 0x029d0000 0x00 0x029d0000 0x00 0x00004000>, // ddr2 cfg
+		 <0x00 0x029f0000 0x00 0x029f0000 0x00 0x00004000>, // ddr3 cfg
+		 <0x00 0x02980000 0x00 0x02980000 0x00 0x00000200>, // ss cfg 0
+		 <0x00 0x029a0000 0x00 0x029a0000 0x00 0x00000200>, // ss cfg 1
+		 <0x00 0x029c0000 0x00 0x029c0000 0x00 0x00000200>, // ss cfg 2
+		 <0x00 0x029e0000 0x00 0x029e0000 0x00 0x00000200>, // ss cfg 3
+		 <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>;
+
+	msmc0: msmc {
+		compatible = "ti,j721s2-msmc";
+		intrlv-gran = <MULTI_DDR_CFG_INTRLV_GRAN>;
+		intrlv-size = <MULTI_DDR_CFG_INTRLV_SIZE>;
+		ecc-enable = <MULTI_DDR_CFG_ECC_ENABLE>;
+		emif-config = <MULTI_DDR_CFG_HYBRID_SELECT>;
+		emif-active = <MULTI_DDR_CFG_EMIFS_ACTIVE>;
+		#address-cells = <2>;
+		#size-cells = <2>;
+
+		bootph-pre-ram;
+
+		memorycontroller0: memorycontroller@2990000 {
+			compatible = "ti,j721s2-ddrss";
+			reg = <0x0 0x02990000 0x0 0x4000>,
+			      <0x0 0x0114000 0x0 0x100>,
+				  <0x0 0x02980000 0x0 0x200>;
+			reg-names = "cfg", "ctrl_mmr_lp4", "ss_cfg";
+			power-domains = <&k3_pds 191 TI_SCI_PD_SHARED>,
+				<&k3_pds 131 TI_SCI_PD_SHARED>;
+			clocks = <&k3_clks 191 1>, <&k3_clks 78 2>;
+			ti,ddr-freq0 = <DDRSS_PLL_FREQUENCY_0>;
+			ti,ddr-freq1 = <DDRSS_PLL_FREQUENCY_1>;
+			ti,ddr-freq2 = <DDRSS_PLL_FREQUENCY_2>;
+			ti,ddr-fhs-cnt = <DDRSS_PLL_FHS_CNT>;
+			instance = <0>;
+
+			bootph-pre-ram;
+
+			ti,ctl-data = <
+				DDRSS0_CTL_00_DATA
+				DDRSS0_CTL_01_DATA
+				DDRSS0_CTL_02_DATA
+				DDRSS0_CTL_03_DATA
+				DDRSS0_CTL_04_DATA
+				DDRSS0_CTL_05_DATA
+				DDRSS0_CTL_06_DATA
+				DDRSS0_CTL_07_DATA
+				DDRSS0_CTL_08_DATA
+				DDRSS0_CTL_09_DATA
+				DDRSS0_CTL_10_DATA
+				DDRSS0_CTL_11_DATA
+				DDRSS0_CTL_12_DATA
+				DDRSS0_CTL_13_DATA
+				DDRSS0_CTL_14_DATA
+				DDRSS0_CTL_15_DATA
+				DDRSS0_CTL_16_DATA
+				DDRSS0_CTL_17_DATA
+				DDRSS0_CTL_18_DATA
+				DDRSS0_CTL_19_DATA
+				DDRSS0_CTL_20_DATA
+				DDRSS0_CTL_21_DATA
+				DDRSS0_CTL_22_DATA
+				DDRSS0_CTL_23_DATA
+				DDRSS0_CTL_24_DATA
+				DDRSS0_CTL_25_DATA
+				DDRSS0_CTL_26_DATA
+				DDRSS0_CTL_27_DATA
+				DDRSS0_CTL_28_DATA
+				DDRSS0_CTL_29_DATA
+				DDRSS0_CTL_30_DATA
+				DDRSS0_CTL_31_DATA
+				DDRSS0_CTL_32_DATA
+				DDRSS0_CTL_33_DATA
+				DDRSS0_CTL_34_DATA
+				DDRSS0_CTL_35_DATA
+				DDRSS0_CTL_36_DATA
+				DDRSS0_CTL_37_DATA
+				DDRSS0_CTL_38_DATA
+				DDRSS0_CTL_39_DATA
+				DDRSS0_CTL_40_DATA
+				DDRSS0_CTL_41_DATA
+				DDRSS0_CTL_42_DATA
+				DDRSS0_CTL_43_DATA
+				DDRSS0_CTL_44_DATA
+				DDRSS0_CTL_45_DATA
+				DDRSS0_CTL_46_DATA
+				DDRSS0_CTL_47_DATA
+				DDRSS0_CTL_48_DATA
+				DDRSS0_CTL_49_DATA
+				DDRSS0_CTL_50_DATA
+				DDRSS0_CTL_51_DATA
+				DDRSS0_CTL_52_DATA
+				DDRSS0_CTL_53_DATA
+				DDRSS0_CTL_54_DATA
+				DDRSS0_CTL_55_DATA
+				DDRSS0_CTL_56_DATA
+				DDRSS0_CTL_57_DATA
+				DDRSS0_CTL_58_DATA
+				DDRSS0_CTL_59_DATA
+				DDRSS0_CTL_60_DATA
+				DDRSS0_CTL_61_DATA
+				DDRSS0_CTL_62_DATA
+				DDRSS0_CTL_63_DATA
+				DDRSS0_CTL_64_DATA
+				DDRSS0_CTL_65_DATA
+				DDRSS0_CTL_66_DATA
+				DDRSS0_CTL_67_DATA
+				DDRSS0_CTL_68_DATA
+				DDRSS0_CTL_69_DATA
+				DDRSS0_CTL_70_DATA
+				DDRSS0_CTL_71_DATA
+				DDRSS0_CTL_72_DATA
+				DDRSS0_CTL_73_DATA
+				DDRSS0_CTL_74_DATA
+				DDRSS0_CTL_75_DATA
+				DDRSS0_CTL_76_DATA
+				DDRSS0_CTL_77_DATA
+				DDRSS0_CTL_78_DATA
+				DDRSS0_CTL_79_DATA
+				DDRSS0_CTL_80_DATA
+				DDRSS0_CTL_81_DATA
+				DDRSS0_CTL_82_DATA
+				DDRSS0_CTL_83_DATA
+				DDRSS0_CTL_84_DATA
+				DDRSS0_CTL_85_DATA
+				DDRSS0_CTL_86_DATA
+				DDRSS0_CTL_87_DATA
+				DDRSS0_CTL_88_DATA
+				DDRSS0_CTL_89_DATA
+				DDRSS0_CTL_90_DATA
+				DDRSS0_CTL_91_DATA
+				DDRSS0_CTL_92_DATA
+				DDRSS0_CTL_93_DATA
+				DDRSS0_CTL_94_DATA
+				DDRSS0_CTL_95_DATA
+				DDRSS0_CTL_96_DATA
+				DDRSS0_CTL_97_DATA
+				DDRSS0_CTL_98_DATA
+				DDRSS0_CTL_99_DATA
+				DDRSS0_CTL_100_DATA
+				DDRSS0_CTL_101_DATA
+				DDRSS0_CTL_102_DATA
+				DDRSS0_CTL_103_DATA
+				DDRSS0_CTL_104_DATA
+				DDRSS0_CTL_105_DATA
+				DDRSS0_CTL_106_DATA
+				DDRSS0_CTL_107_DATA
+				DDRSS0_CTL_108_DATA
+				DDRSS0_CTL_109_DATA
+				DDRSS0_CTL_110_DATA
+				DDRSS0_CTL_111_DATA
+				DDRSS0_CTL_112_DATA
+				DDRSS0_CTL_113_DATA
+				DDRSS0_CTL_114_DATA
+				DDRSS0_CTL_115_DATA
+				DDRSS0_CTL_116_DATA
+				DDRSS0_CTL_117_DATA
+				DDRSS0_CTL_118_DATA
+				DDRSS0_CTL_119_DATA
+				DDRSS0_CTL_120_DATA
+				DDRSS0_CTL_121_DATA
+				DDRSS0_CTL_122_DATA
+				DDRSS0_CTL_123_DATA
+				DDRSS0_CTL_124_DATA
+				DDRSS0_CTL_125_DATA
+				DDRSS0_CTL_126_DATA
+				DDRSS0_CTL_127_DATA
+				DDRSS0_CTL_128_DATA
+				DDRSS0_CTL_129_DATA
+				DDRSS0_CTL_130_DATA
+				DDRSS0_CTL_131_DATA
+				DDRSS0_CTL_132_DATA
+				DDRSS0_CTL_133_DATA
+				DDRSS0_CTL_134_DATA
+				DDRSS0_CTL_135_DATA
+				DDRSS0_CTL_136_DATA
+				DDRSS0_CTL_137_DATA
+				DDRSS0_CTL_138_DATA
+				DDRSS0_CTL_139_DATA
+				DDRSS0_CTL_140_DATA
+				DDRSS0_CTL_141_DATA
+				DDRSS0_CTL_142_DATA
+				DDRSS0_CTL_143_DATA
+				DDRSS0_CTL_144_DATA
+				DDRSS0_CTL_145_DATA
+				DDRSS0_CTL_146_DATA
+				DDRSS0_CTL_147_DATA
+				DDRSS0_CTL_148_DATA
+				DDRSS0_CTL_149_DATA
+				DDRSS0_CTL_150_DATA
+				DDRSS0_CTL_151_DATA
+				DDRSS0_CTL_152_DATA
+				DDRSS0_CTL_153_DATA
+				DDRSS0_CTL_154_DATA
+				DDRSS0_CTL_155_DATA
+				DDRSS0_CTL_156_DATA
+				DDRSS0_CTL_157_DATA
+				DDRSS0_CTL_158_DATA
+				DDRSS0_CTL_159_DATA
+				DDRSS0_CTL_160_DATA
+				DDRSS0_CTL_161_DATA
+				DDRSS0_CTL_162_DATA
+				DDRSS0_CTL_163_DATA
+				DDRSS0_CTL_164_DATA
+				DDRSS0_CTL_165_DATA
+				DDRSS0_CTL_166_DATA
+				DDRSS0_CTL_167_DATA
+				DDRSS0_CTL_168_DATA
+				DDRSS0_CTL_169_DATA
+				DDRSS0_CTL_170_DATA
+				DDRSS0_CTL_171_DATA
+				DDRSS0_CTL_172_DATA
+				DDRSS0_CTL_173_DATA
+				DDRSS0_CTL_174_DATA
+				DDRSS0_CTL_175_DATA
+				DDRSS0_CTL_176_DATA
+				DDRSS0_CTL_177_DATA
+				DDRSS0_CTL_178_DATA
+				DDRSS0_CTL_179_DATA
+				DDRSS0_CTL_180_DATA
+				DDRSS0_CTL_181_DATA
+				DDRSS0_CTL_182_DATA
+				DDRSS0_CTL_183_DATA
+				DDRSS0_CTL_184_DATA
+				DDRSS0_CTL_185_DATA
+				DDRSS0_CTL_186_DATA
+				DDRSS0_CTL_187_DATA
+				DDRSS0_CTL_188_DATA
+				DDRSS0_CTL_189_DATA
+				DDRSS0_CTL_190_DATA
+				DDRSS0_CTL_191_DATA
+				DDRSS0_CTL_192_DATA
+				DDRSS0_CTL_193_DATA
+				DDRSS0_CTL_194_DATA
+				DDRSS0_CTL_195_DATA
+				DDRSS0_CTL_196_DATA
+				DDRSS0_CTL_197_DATA
+				DDRSS0_CTL_198_DATA
+				DDRSS0_CTL_199_DATA
+				DDRSS0_CTL_200_DATA
+				DDRSS0_CTL_201_DATA
+				DDRSS0_CTL_202_DATA
+				DDRSS0_CTL_203_DATA
+				DDRSS0_CTL_204_DATA
+				DDRSS0_CTL_205_DATA
+				DDRSS0_CTL_206_DATA
+				DDRSS0_CTL_207_DATA
+				DDRSS0_CTL_208_DATA
+				DDRSS0_CTL_209_DATA
+				DDRSS0_CTL_210_DATA
+				DDRSS0_CTL_211_DATA
+				DDRSS0_CTL_212_DATA
+				DDRSS0_CTL_213_DATA
+				DDRSS0_CTL_214_DATA
+				DDRSS0_CTL_215_DATA
+				DDRSS0_CTL_216_DATA
+				DDRSS0_CTL_217_DATA
+				DDRSS0_CTL_218_DATA
+				DDRSS0_CTL_219_DATA
+				DDRSS0_CTL_220_DATA
+				DDRSS0_CTL_221_DATA
+				DDRSS0_CTL_222_DATA
+				DDRSS0_CTL_223_DATA
+				DDRSS0_CTL_224_DATA
+				DDRSS0_CTL_225_DATA
+				DDRSS0_CTL_226_DATA
+				DDRSS0_CTL_227_DATA
+				DDRSS0_CTL_228_DATA
+				DDRSS0_CTL_229_DATA
+				DDRSS0_CTL_230_DATA
+				DDRSS0_CTL_231_DATA
+				DDRSS0_CTL_232_DATA
+				DDRSS0_CTL_233_DATA
+				DDRSS0_CTL_234_DATA
+				DDRSS0_CTL_235_DATA
+				DDRSS0_CTL_236_DATA
+				DDRSS0_CTL_237_DATA
+				DDRSS0_CTL_238_DATA
+				DDRSS0_CTL_239_DATA
+				DDRSS0_CTL_240_DATA
+				DDRSS0_CTL_241_DATA
+				DDRSS0_CTL_242_DATA
+				DDRSS0_CTL_243_DATA
+				DDRSS0_CTL_244_DATA
+				DDRSS0_CTL_245_DATA
+				DDRSS0_CTL_246_DATA
+				DDRSS0_CTL_247_DATA
+				DDRSS0_CTL_248_DATA
+				DDRSS0_CTL_249_DATA
+				DDRSS0_CTL_250_DATA
+				DDRSS0_CTL_251_DATA
+				DDRSS0_CTL_252_DATA
+				DDRSS0_CTL_253_DATA
+				DDRSS0_CTL_254_DATA
+				DDRSS0_CTL_255_DATA
+				DDRSS0_CTL_256_DATA
+				DDRSS0_CTL_257_DATA
+				DDRSS0_CTL_258_DATA
+				DDRSS0_CTL_259_DATA
+				DDRSS0_CTL_260_DATA
+				DDRSS0_CTL_261_DATA
+				DDRSS0_CTL_262_DATA
+				DDRSS0_CTL_263_DATA
+				DDRSS0_CTL_264_DATA
+				DDRSS0_CTL_265_DATA
+				DDRSS0_CTL_266_DATA
+				DDRSS0_CTL_267_DATA
+				DDRSS0_CTL_268_DATA
+				DDRSS0_CTL_269_DATA
+				DDRSS0_CTL_270_DATA
+				DDRSS0_CTL_271_DATA
+				DDRSS0_CTL_272_DATA
+				DDRSS0_CTL_273_DATA
+				DDRSS0_CTL_274_DATA
+				DDRSS0_CTL_275_DATA
+				DDRSS0_CTL_276_DATA
+				DDRSS0_CTL_277_DATA
+				DDRSS0_CTL_278_DATA
+				DDRSS0_CTL_279_DATA
+				DDRSS0_CTL_280_DATA
+				DDRSS0_CTL_281_DATA
+				DDRSS0_CTL_282_DATA
+				DDRSS0_CTL_283_DATA
+				DDRSS0_CTL_284_DATA
+				DDRSS0_CTL_285_DATA
+				DDRSS0_CTL_286_DATA
+				DDRSS0_CTL_287_DATA
+				DDRSS0_CTL_288_DATA
+				DDRSS0_CTL_289_DATA
+				DDRSS0_CTL_290_DATA
+				DDRSS0_CTL_291_DATA
+				DDRSS0_CTL_292_DATA
+				DDRSS0_CTL_293_DATA
+				DDRSS0_CTL_294_DATA
+				DDRSS0_CTL_295_DATA
+				DDRSS0_CTL_296_DATA
+				DDRSS0_CTL_297_DATA
+				DDRSS0_CTL_298_DATA
+				DDRSS0_CTL_299_DATA
+				DDRSS0_CTL_300_DATA
+				DDRSS0_CTL_301_DATA
+				DDRSS0_CTL_302_DATA
+				DDRSS0_CTL_303_DATA
+				DDRSS0_CTL_304_DATA
+				DDRSS0_CTL_305_DATA
+				DDRSS0_CTL_306_DATA
+				DDRSS0_CTL_307_DATA
+				DDRSS0_CTL_308_DATA
+				DDRSS0_CTL_309_DATA
+				DDRSS0_CTL_310_DATA
+				DDRSS0_CTL_311_DATA
+				DDRSS0_CTL_312_DATA
+				DDRSS0_CTL_313_DATA
+				DDRSS0_CTL_314_DATA
+				DDRSS0_CTL_315_DATA
+				DDRSS0_CTL_316_DATA
+				DDRSS0_CTL_317_DATA
+				DDRSS0_CTL_318_DATA
+				DDRSS0_CTL_319_DATA
+				DDRSS0_CTL_320_DATA
+				DDRSS0_CTL_321_DATA
+				DDRSS0_CTL_322_DATA
+				DDRSS0_CTL_323_DATA
+				DDRSS0_CTL_324_DATA
+				DDRSS0_CTL_325_DATA
+				DDRSS0_CTL_326_DATA
+				DDRSS0_CTL_327_DATA
+				DDRSS0_CTL_328_DATA
+				DDRSS0_CTL_329_DATA
+				DDRSS0_CTL_330_DATA
+				DDRSS0_CTL_331_DATA
+				DDRSS0_CTL_332_DATA
+				DDRSS0_CTL_333_DATA
+				DDRSS0_CTL_334_DATA
+				DDRSS0_CTL_335_DATA
+				DDRSS0_CTL_336_DATA
+				DDRSS0_CTL_337_DATA
+				DDRSS0_CTL_338_DATA
+				DDRSS0_CTL_339_DATA
+				DDRSS0_CTL_340_DATA
+				DDRSS0_CTL_341_DATA
+				DDRSS0_CTL_342_DATA
+				DDRSS0_CTL_343_DATA
+				DDRSS0_CTL_344_DATA
+				DDRSS0_CTL_345_DATA
+				DDRSS0_CTL_346_DATA
+				DDRSS0_CTL_347_DATA
+				DDRSS0_CTL_348_DATA
+				DDRSS0_CTL_349_DATA
+				DDRSS0_CTL_350_DATA
+				DDRSS0_CTL_351_DATA
+				DDRSS0_CTL_352_DATA
+				DDRSS0_CTL_353_DATA
+				DDRSS0_CTL_354_DATA
+				DDRSS0_CTL_355_DATA
+				DDRSS0_CTL_356_DATA
+				DDRSS0_CTL_357_DATA
+				DDRSS0_CTL_358_DATA
+				DDRSS0_CTL_359_DATA
+				DDRSS0_CTL_360_DATA
+				DDRSS0_CTL_361_DATA
+				DDRSS0_CTL_362_DATA
+				DDRSS0_CTL_363_DATA
+				DDRSS0_CTL_364_DATA
+				DDRSS0_CTL_365_DATA
+				DDRSS0_CTL_366_DATA
+				DDRSS0_CTL_367_DATA
+				DDRSS0_CTL_368_DATA
+				DDRSS0_CTL_369_DATA
+				DDRSS0_CTL_370_DATA
+				DDRSS0_CTL_371_DATA
+				DDRSS0_CTL_372_DATA
+				DDRSS0_CTL_373_DATA
+				DDRSS0_CTL_374_DATA
+				DDRSS0_CTL_375_DATA
+				DDRSS0_CTL_376_DATA
+				DDRSS0_CTL_377_DATA
+				DDRSS0_CTL_378_DATA
+				DDRSS0_CTL_379_DATA
+				DDRSS0_CTL_380_DATA
+				DDRSS0_CTL_381_DATA
+				DDRSS0_CTL_382_DATA
+				DDRSS0_CTL_383_DATA
+				DDRSS0_CTL_384_DATA
+				DDRSS0_CTL_385_DATA
+				DDRSS0_CTL_386_DATA
+				DDRSS0_CTL_387_DATA
+				DDRSS0_CTL_388_DATA
+				DDRSS0_CTL_389_DATA
+				DDRSS0_CTL_390_DATA
+				DDRSS0_CTL_391_DATA
+				DDRSS0_CTL_392_DATA
+				DDRSS0_CTL_393_DATA
+				DDRSS0_CTL_394_DATA
+				DDRSS0_CTL_395_DATA
+				DDRSS0_CTL_396_DATA
+				DDRSS0_CTL_397_DATA
+				DDRSS0_CTL_398_DATA
+				DDRSS0_CTL_399_DATA
+				DDRSS0_CTL_400_DATA
+				DDRSS0_CTL_401_DATA
+				DDRSS0_CTL_402_DATA
+				DDRSS0_CTL_403_DATA
+				DDRSS0_CTL_404_DATA
+				DDRSS0_CTL_405_DATA
+				DDRSS0_CTL_406_DATA
+				DDRSS0_CTL_407_DATA
+				DDRSS0_CTL_408_DATA
+				DDRSS0_CTL_409_DATA
+				DDRSS0_CTL_410_DATA
+				DDRSS0_CTL_411_DATA
+				DDRSS0_CTL_412_DATA
+				DDRSS0_CTL_413_DATA
+				DDRSS0_CTL_414_DATA
+				DDRSS0_CTL_415_DATA
+				DDRSS0_CTL_416_DATA
+				DDRSS0_CTL_417_DATA
+				DDRSS0_CTL_418_DATA
+				DDRSS0_CTL_419_DATA
+				DDRSS0_CTL_420_DATA
+				DDRSS0_CTL_421_DATA
+				DDRSS0_CTL_422_DATA
+				DDRSS0_CTL_423_DATA
+				DDRSS0_CTL_424_DATA
+				DDRSS0_CTL_425_DATA
+				DDRSS0_CTL_426_DATA
+				DDRSS0_CTL_427_DATA
+				DDRSS0_CTL_428_DATA
+				DDRSS0_CTL_429_DATA
+				DDRSS0_CTL_430_DATA
+				DDRSS0_CTL_431_DATA
+				DDRSS0_CTL_432_DATA
+				DDRSS0_CTL_433_DATA
+				DDRSS0_CTL_434_DATA
+				DDRSS0_CTL_435_DATA
+				DDRSS0_CTL_436_DATA
+				DDRSS0_CTL_437_DATA
+				DDRSS0_CTL_438_DATA
+				DDRSS0_CTL_439_DATA
+				DDRSS0_CTL_440_DATA
+				DDRSS0_CTL_441_DATA
+				DDRSS0_CTL_442_DATA
+				DDRSS0_CTL_443_DATA
+				DDRSS0_CTL_444_DATA
+				DDRSS0_CTL_445_DATA
+				DDRSS0_CTL_446_DATA
+				DDRSS0_CTL_447_DATA
+				DDRSS0_CTL_448_DATA
+				DDRSS0_CTL_449_DATA
+				DDRSS0_CTL_450_DATA
+				DDRSS0_CTL_451_DATA
+				DDRSS0_CTL_452_DATA
+				DDRSS0_CTL_453_DATA
+				DDRSS0_CTL_454_DATA
+				DDRSS0_CTL_455_DATA
+				DDRSS0_CTL_456_DATA
+				DDRSS0_CTL_457_DATA
+				DDRSS0_CTL_458_DATA
+			>;
+
+			ti,pi-data = <
+				DDRSS0_PI_00_DATA
+				DDRSS0_PI_01_DATA
+				DDRSS0_PI_02_DATA
+				DDRSS0_PI_03_DATA
+				DDRSS0_PI_04_DATA
+				DDRSS0_PI_05_DATA
+				DDRSS0_PI_06_DATA
+				DDRSS0_PI_07_DATA
+				DDRSS0_PI_08_DATA
+				DDRSS0_PI_09_DATA
+				DDRSS0_PI_10_DATA
+				DDRSS0_PI_11_DATA
+				DDRSS0_PI_12_DATA
+				DDRSS0_PI_13_DATA
+				DDRSS0_PI_14_DATA
+				DDRSS0_PI_15_DATA
+				DDRSS0_PI_16_DATA
+				DDRSS0_PI_17_DATA
+				DDRSS0_PI_18_DATA
+				DDRSS0_PI_19_DATA
+				DDRSS0_PI_20_DATA
+				DDRSS0_PI_21_DATA
+				DDRSS0_PI_22_DATA
+				DDRSS0_PI_23_DATA
+				DDRSS0_PI_24_DATA
+				DDRSS0_PI_25_DATA
+				DDRSS0_PI_26_DATA
+				DDRSS0_PI_27_DATA
+				DDRSS0_PI_28_DATA
+				DDRSS0_PI_29_DATA
+				DDRSS0_PI_30_DATA
+				DDRSS0_PI_31_DATA
+				DDRSS0_PI_32_DATA
+				DDRSS0_PI_33_DATA
+				DDRSS0_PI_34_DATA
+				DDRSS0_PI_35_DATA
+				DDRSS0_PI_36_DATA
+				DDRSS0_PI_37_DATA
+				DDRSS0_PI_38_DATA
+				DDRSS0_PI_39_DATA
+				DDRSS0_PI_40_DATA
+				DDRSS0_PI_41_DATA
+				DDRSS0_PI_42_DATA
+				DDRSS0_PI_43_DATA
+				DDRSS0_PI_44_DATA
+				DDRSS0_PI_45_DATA
+				DDRSS0_PI_46_DATA
+				DDRSS0_PI_47_DATA
+				DDRSS0_PI_48_DATA
+				DDRSS0_PI_49_DATA
+				DDRSS0_PI_50_DATA
+				DDRSS0_PI_51_DATA
+				DDRSS0_PI_52_DATA
+				DDRSS0_PI_53_DATA
+				DDRSS0_PI_54_DATA
+				DDRSS0_PI_55_DATA
+				DDRSS0_PI_56_DATA
+				DDRSS0_PI_57_DATA
+				DDRSS0_PI_58_DATA
+				DDRSS0_PI_59_DATA
+				DDRSS0_PI_60_DATA
+				DDRSS0_PI_61_DATA
+				DDRSS0_PI_62_DATA
+				DDRSS0_PI_63_DATA
+				DDRSS0_PI_64_DATA
+				DDRSS0_PI_65_DATA
+				DDRSS0_PI_66_DATA
+				DDRSS0_PI_67_DATA
+				DDRSS0_PI_68_DATA
+				DDRSS0_PI_69_DATA
+				DDRSS0_PI_70_DATA
+				DDRSS0_PI_71_DATA
+				DDRSS0_PI_72_DATA
+				DDRSS0_PI_73_DATA
+				DDRSS0_PI_74_DATA
+				DDRSS0_PI_75_DATA
+				DDRSS0_PI_76_DATA
+				DDRSS0_PI_77_DATA
+				DDRSS0_PI_78_DATA
+				DDRSS0_PI_79_DATA
+				DDRSS0_PI_80_DATA
+				DDRSS0_PI_81_DATA
+				DDRSS0_PI_82_DATA
+				DDRSS0_PI_83_DATA
+				DDRSS0_PI_84_DATA
+				DDRSS0_PI_85_DATA
+				DDRSS0_PI_86_DATA
+				DDRSS0_PI_87_DATA
+				DDRSS0_PI_88_DATA
+				DDRSS0_PI_89_DATA
+				DDRSS0_PI_90_DATA
+				DDRSS0_PI_91_DATA
+				DDRSS0_PI_92_DATA
+				DDRSS0_PI_93_DATA
+				DDRSS0_PI_94_DATA
+				DDRSS0_PI_95_DATA
+				DDRSS0_PI_96_DATA
+				DDRSS0_PI_97_DATA
+				DDRSS0_PI_98_DATA
+				DDRSS0_PI_99_DATA
+				DDRSS0_PI_100_DATA
+				DDRSS0_PI_101_DATA
+				DDRSS0_PI_102_DATA
+				DDRSS0_PI_103_DATA
+				DDRSS0_PI_104_DATA
+				DDRSS0_PI_105_DATA
+				DDRSS0_PI_106_DATA
+				DDRSS0_PI_107_DATA
+				DDRSS0_PI_108_DATA
+				DDRSS0_PI_109_DATA
+				DDRSS0_PI_110_DATA
+				DDRSS0_PI_111_DATA
+				DDRSS0_PI_112_DATA
+				DDRSS0_PI_113_DATA
+				DDRSS0_PI_114_DATA
+				DDRSS0_PI_115_DATA
+				DDRSS0_PI_116_DATA
+				DDRSS0_PI_117_DATA
+				DDRSS0_PI_118_DATA
+				DDRSS0_PI_119_DATA
+				DDRSS0_PI_120_DATA
+				DDRSS0_PI_121_DATA
+				DDRSS0_PI_122_DATA
+				DDRSS0_PI_123_DATA
+				DDRSS0_PI_124_DATA
+				DDRSS0_PI_125_DATA
+				DDRSS0_PI_126_DATA
+				DDRSS0_PI_127_DATA
+				DDRSS0_PI_128_DATA
+				DDRSS0_PI_129_DATA
+				DDRSS0_PI_130_DATA
+				DDRSS0_PI_131_DATA
+				DDRSS0_PI_132_DATA
+				DDRSS0_PI_133_DATA
+				DDRSS0_PI_134_DATA
+				DDRSS0_PI_135_DATA
+				DDRSS0_PI_136_DATA
+				DDRSS0_PI_137_DATA
+				DDRSS0_PI_138_DATA
+				DDRSS0_PI_139_DATA
+				DDRSS0_PI_140_DATA
+				DDRSS0_PI_141_DATA
+				DDRSS0_PI_142_DATA
+				DDRSS0_PI_143_DATA
+				DDRSS0_PI_144_DATA
+				DDRSS0_PI_145_DATA
+				DDRSS0_PI_146_DATA
+				DDRSS0_PI_147_DATA
+				DDRSS0_PI_148_DATA
+				DDRSS0_PI_149_DATA
+				DDRSS0_PI_150_DATA
+				DDRSS0_PI_151_DATA
+				DDRSS0_PI_152_DATA
+				DDRSS0_PI_153_DATA
+				DDRSS0_PI_154_DATA
+				DDRSS0_PI_155_DATA
+				DDRSS0_PI_156_DATA
+				DDRSS0_PI_157_DATA
+				DDRSS0_PI_158_DATA
+				DDRSS0_PI_159_DATA
+				DDRSS0_PI_160_DATA
+				DDRSS0_PI_161_DATA
+				DDRSS0_PI_162_DATA
+				DDRSS0_PI_163_DATA
+				DDRSS0_PI_164_DATA
+				DDRSS0_PI_165_DATA
+				DDRSS0_PI_166_DATA
+				DDRSS0_PI_167_DATA
+				DDRSS0_PI_168_DATA
+				DDRSS0_PI_169_DATA
+				DDRSS0_PI_170_DATA
+				DDRSS0_PI_171_DATA
+				DDRSS0_PI_172_DATA
+				DDRSS0_PI_173_DATA
+				DDRSS0_PI_174_DATA
+				DDRSS0_PI_175_DATA
+				DDRSS0_PI_176_DATA
+				DDRSS0_PI_177_DATA
+				DDRSS0_PI_178_DATA
+				DDRSS0_PI_179_DATA
+				DDRSS0_PI_180_DATA
+				DDRSS0_PI_181_DATA
+				DDRSS0_PI_182_DATA
+				DDRSS0_PI_183_DATA
+				DDRSS0_PI_184_DATA
+				DDRSS0_PI_185_DATA
+				DDRSS0_PI_186_DATA
+				DDRSS0_PI_187_DATA
+				DDRSS0_PI_188_DATA
+				DDRSS0_PI_189_DATA
+				DDRSS0_PI_190_DATA
+				DDRSS0_PI_191_DATA
+				DDRSS0_PI_192_DATA
+				DDRSS0_PI_193_DATA
+				DDRSS0_PI_194_DATA
+				DDRSS0_PI_195_DATA
+				DDRSS0_PI_196_DATA
+				DDRSS0_PI_197_DATA
+				DDRSS0_PI_198_DATA
+				DDRSS0_PI_199_DATA
+				DDRSS0_PI_200_DATA
+				DDRSS0_PI_201_DATA
+				DDRSS0_PI_202_DATA
+				DDRSS0_PI_203_DATA
+				DDRSS0_PI_204_DATA
+				DDRSS0_PI_205_DATA
+				DDRSS0_PI_206_DATA
+				DDRSS0_PI_207_DATA
+				DDRSS0_PI_208_DATA
+				DDRSS0_PI_209_DATA
+				DDRSS0_PI_210_DATA
+				DDRSS0_PI_211_DATA
+				DDRSS0_PI_212_DATA
+				DDRSS0_PI_213_DATA
+				DDRSS0_PI_214_DATA
+				DDRSS0_PI_215_DATA
+				DDRSS0_PI_216_DATA
+				DDRSS0_PI_217_DATA
+				DDRSS0_PI_218_DATA
+				DDRSS0_PI_219_DATA
+				DDRSS0_PI_220_DATA
+				DDRSS0_PI_221_DATA
+				DDRSS0_PI_222_DATA
+				DDRSS0_PI_223_DATA
+				DDRSS0_PI_224_DATA
+				DDRSS0_PI_225_DATA
+				DDRSS0_PI_226_DATA
+				DDRSS0_PI_227_DATA
+				DDRSS0_PI_228_DATA
+				DDRSS0_PI_229_DATA
+				DDRSS0_PI_230_DATA
+				DDRSS0_PI_231_DATA
+				DDRSS0_PI_232_DATA
+				DDRSS0_PI_233_DATA
+				DDRSS0_PI_234_DATA
+				DDRSS0_PI_235_DATA
+				DDRSS0_PI_236_DATA
+				DDRSS0_PI_237_DATA
+				DDRSS0_PI_238_DATA
+				DDRSS0_PI_239_DATA
+				DDRSS0_PI_240_DATA
+				DDRSS0_PI_241_DATA
+				DDRSS0_PI_242_DATA
+				DDRSS0_PI_243_DATA
+				DDRSS0_PI_244_DATA
+				DDRSS0_PI_245_DATA
+				DDRSS0_PI_246_DATA
+				DDRSS0_PI_247_DATA
+				DDRSS0_PI_248_DATA
+				DDRSS0_PI_249_DATA
+				DDRSS0_PI_250_DATA
+				DDRSS0_PI_251_DATA
+				DDRSS0_PI_252_DATA
+				DDRSS0_PI_253_DATA
+				DDRSS0_PI_254_DATA
+				DDRSS0_PI_255_DATA
+				DDRSS0_PI_256_DATA
+				DDRSS0_PI_257_DATA
+				DDRSS0_PI_258_DATA
+				DDRSS0_PI_259_DATA
+				DDRSS0_PI_260_DATA
+				DDRSS0_PI_261_DATA
+				DDRSS0_PI_262_DATA
+				DDRSS0_PI_263_DATA
+				DDRSS0_PI_264_DATA
+				DDRSS0_PI_265_DATA
+				DDRSS0_PI_266_DATA
+				DDRSS0_PI_267_DATA
+				DDRSS0_PI_268_DATA
+				DDRSS0_PI_269_DATA
+				DDRSS0_PI_270_DATA
+				DDRSS0_PI_271_DATA
+				DDRSS0_PI_272_DATA
+				DDRSS0_PI_273_DATA
+				DDRSS0_PI_274_DATA
+				DDRSS0_PI_275_DATA
+				DDRSS0_PI_276_DATA
+				DDRSS0_PI_277_DATA
+				DDRSS0_PI_278_DATA
+				DDRSS0_PI_279_DATA
+				DDRSS0_PI_280_DATA
+				DDRSS0_PI_281_DATA
+				DDRSS0_PI_282_DATA
+				DDRSS0_PI_283_DATA
+				DDRSS0_PI_284_DATA
+				DDRSS0_PI_285_DATA
+				DDRSS0_PI_286_DATA
+				DDRSS0_PI_287_DATA
+				DDRSS0_PI_288_DATA
+				DDRSS0_PI_289_DATA
+				DDRSS0_PI_290_DATA
+				DDRSS0_PI_291_DATA
+				DDRSS0_PI_292_DATA
+				DDRSS0_PI_293_DATA
+				DDRSS0_PI_294_DATA
+				DDRSS0_PI_295_DATA
+				DDRSS0_PI_296_DATA
+				DDRSS0_PI_297_DATA
+				DDRSS0_PI_298_DATA
+				DDRSS0_PI_299_DATA
+			>;
+
+			ti,phy-data = <
+				DDRSS0_PHY_00_DATA
+				DDRSS0_PHY_01_DATA
+				DDRSS0_PHY_02_DATA
+				DDRSS0_PHY_03_DATA
+				DDRSS0_PHY_04_DATA
+				DDRSS0_PHY_05_DATA
+				DDRSS0_PHY_06_DATA
+				DDRSS0_PHY_07_DATA
+				DDRSS0_PHY_08_DATA
+				DDRSS0_PHY_09_DATA
+				DDRSS0_PHY_10_DATA
+				DDRSS0_PHY_11_DATA
+				DDRSS0_PHY_12_DATA
+				DDRSS0_PHY_13_DATA
+				DDRSS0_PHY_14_DATA
+				DDRSS0_PHY_15_DATA
+				DDRSS0_PHY_16_DATA
+				DDRSS0_PHY_17_DATA
+				DDRSS0_PHY_18_DATA
+				DDRSS0_PHY_19_DATA
+				DDRSS0_PHY_20_DATA
+				DDRSS0_PHY_21_DATA
+				DDRSS0_PHY_22_DATA
+				DDRSS0_PHY_23_DATA
+				DDRSS0_PHY_24_DATA
+				DDRSS0_PHY_25_DATA
+				DDRSS0_PHY_26_DATA
+				DDRSS0_PHY_27_DATA
+				DDRSS0_PHY_28_DATA
+				DDRSS0_PHY_29_DATA
+				DDRSS0_PHY_30_DATA
+				DDRSS0_PHY_31_DATA
+				DDRSS0_PHY_32_DATA
+				DDRSS0_PHY_33_DATA
+				DDRSS0_PHY_34_DATA
+				DDRSS0_PHY_35_DATA
+				DDRSS0_PHY_36_DATA
+				DDRSS0_PHY_37_DATA
+				DDRSS0_PHY_38_DATA
+				DDRSS0_PHY_39_DATA
+				DDRSS0_PHY_40_DATA
+				DDRSS0_PHY_41_DATA
+				DDRSS0_PHY_42_DATA
+				DDRSS0_PHY_43_DATA
+				DDRSS0_PHY_44_DATA
+				DDRSS0_PHY_45_DATA
+				DDRSS0_PHY_46_DATA
+				DDRSS0_PHY_47_DATA
+				DDRSS0_PHY_48_DATA
+				DDRSS0_PHY_49_DATA
+				DDRSS0_PHY_50_DATA
+				DDRSS0_PHY_51_DATA
+				DDRSS0_PHY_52_DATA
+				DDRSS0_PHY_53_DATA
+				DDRSS0_PHY_54_DATA
+				DDRSS0_PHY_55_DATA
+				DDRSS0_PHY_56_DATA
+				DDRSS0_PHY_57_DATA
+				DDRSS0_PHY_58_DATA
+				DDRSS0_PHY_59_DATA
+				DDRSS0_PHY_60_DATA
+				DDRSS0_PHY_61_DATA
+				DDRSS0_PHY_62_DATA
+				DDRSS0_PHY_63_DATA
+				DDRSS0_PHY_64_DATA
+				DDRSS0_PHY_65_DATA
+				DDRSS0_PHY_66_DATA
+				DDRSS0_PHY_67_DATA
+				DDRSS0_PHY_68_DATA
+				DDRSS0_PHY_69_DATA
+				DDRSS0_PHY_70_DATA
+				DDRSS0_PHY_71_DATA
+				DDRSS0_PHY_72_DATA
+				DDRSS0_PHY_73_DATA
+				DDRSS0_PHY_74_DATA
+				DDRSS0_PHY_75_DATA
+				DDRSS0_PHY_76_DATA
+				DDRSS0_PHY_77_DATA
+				DDRSS0_PHY_78_DATA
+				DDRSS0_PHY_79_DATA
+				DDRSS0_PHY_80_DATA
+				DDRSS0_PHY_81_DATA
+				DDRSS0_PHY_82_DATA
+				DDRSS0_PHY_83_DATA
+				DDRSS0_PHY_84_DATA
+				DDRSS0_PHY_85_DATA
+				DDRSS0_PHY_86_DATA
+				DDRSS0_PHY_87_DATA
+				DDRSS0_PHY_88_DATA
+				DDRSS0_PHY_89_DATA
+				DDRSS0_PHY_90_DATA
+				DDRSS0_PHY_91_DATA
+				DDRSS0_PHY_92_DATA
+				DDRSS0_PHY_93_DATA
+				DDRSS0_PHY_94_DATA
+				DDRSS0_PHY_95_DATA
+				DDRSS0_PHY_96_DATA
+				DDRSS0_PHY_97_DATA
+				DDRSS0_PHY_98_DATA
+				DDRSS0_PHY_99_DATA
+				DDRSS0_PHY_100_DATA
+				DDRSS0_PHY_101_DATA
+				DDRSS0_PHY_102_DATA
+				DDRSS0_PHY_103_DATA
+				DDRSS0_PHY_104_DATA
+				DDRSS0_PHY_105_DATA
+				DDRSS0_PHY_106_DATA
+				DDRSS0_PHY_107_DATA
+				DDRSS0_PHY_108_DATA
+				DDRSS0_PHY_109_DATA
+				DDRSS0_PHY_110_DATA
+				DDRSS0_PHY_111_DATA
+				DDRSS0_PHY_112_DATA
+				DDRSS0_PHY_113_DATA
+				DDRSS0_PHY_114_DATA
+				DDRSS0_PHY_115_DATA
+				DDRSS0_PHY_116_DATA
+				DDRSS0_PHY_117_DATA
+				DDRSS0_PHY_118_DATA
+				DDRSS0_PHY_119_DATA
+				DDRSS0_PHY_120_DATA
+				DDRSS0_PHY_121_DATA
+				DDRSS0_PHY_122_DATA
+				DDRSS0_PHY_123_DATA
+				DDRSS0_PHY_124_DATA
+				DDRSS0_PHY_125_DATA
+				DDRSS0_PHY_126_DATA
+				DDRSS0_PHY_127_DATA
+				DDRSS0_PHY_128_DATA
+				DDRSS0_PHY_129_DATA
+				DDRSS0_PHY_130_DATA
+				DDRSS0_PHY_131_DATA
+				DDRSS0_PHY_132_DATA
+				DDRSS0_PHY_133_DATA
+				DDRSS0_PHY_134_DATA
+				DDRSS0_PHY_135_DATA
+				DDRSS0_PHY_136_DATA
+				DDRSS0_PHY_137_DATA
+				DDRSS0_PHY_138_DATA
+				DDRSS0_PHY_139_DATA
+				DDRSS0_PHY_140_DATA
+				DDRSS0_PHY_141_DATA
+				DDRSS0_PHY_142_DATA
+				DDRSS0_PHY_143_DATA
+				DDRSS0_PHY_144_DATA
+				DDRSS0_PHY_145_DATA
+				DDRSS0_PHY_146_DATA
+				DDRSS0_PHY_147_DATA
+				DDRSS0_PHY_148_DATA
+				DDRSS0_PHY_149_DATA
+				DDRSS0_PHY_150_DATA
+				DDRSS0_PHY_151_DATA
+				DDRSS0_PHY_152_DATA
+				DDRSS0_PHY_153_DATA
+				DDRSS0_PHY_154_DATA
+				DDRSS0_PHY_155_DATA
+				DDRSS0_PHY_156_DATA
+				DDRSS0_PHY_157_DATA
+				DDRSS0_PHY_158_DATA
+				DDRSS0_PHY_159_DATA
+				DDRSS0_PHY_160_DATA
+				DDRSS0_PHY_161_DATA
+				DDRSS0_PHY_162_DATA
+				DDRSS0_PHY_163_DATA
+				DDRSS0_PHY_164_DATA
+				DDRSS0_PHY_165_DATA
+				DDRSS0_PHY_166_DATA
+				DDRSS0_PHY_167_DATA
+				DDRSS0_PHY_168_DATA
+				DDRSS0_PHY_169_DATA
+				DDRSS0_PHY_170_DATA
+				DDRSS0_PHY_171_DATA
+				DDRSS0_PHY_172_DATA
+				DDRSS0_PHY_173_DATA
+				DDRSS0_PHY_174_DATA
+				DDRSS0_PHY_175_DATA
+				DDRSS0_PHY_176_DATA
+				DDRSS0_PHY_177_DATA
+				DDRSS0_PHY_178_DATA
+				DDRSS0_PHY_179_DATA
+				DDRSS0_PHY_180_DATA
+				DDRSS0_PHY_181_DATA
+				DDRSS0_PHY_182_DATA
+				DDRSS0_PHY_183_DATA
+				DDRSS0_PHY_184_DATA
+				DDRSS0_PHY_185_DATA
+				DDRSS0_PHY_186_DATA
+				DDRSS0_PHY_187_DATA
+				DDRSS0_PHY_188_DATA
+				DDRSS0_PHY_189_DATA
+				DDRSS0_PHY_190_DATA
+				DDRSS0_PHY_191_DATA
+				DDRSS0_PHY_192_DATA
+				DDRSS0_PHY_193_DATA
+				DDRSS0_PHY_194_DATA
+				DDRSS0_PHY_195_DATA
+				DDRSS0_PHY_196_DATA
+				DDRSS0_PHY_197_DATA
+				DDRSS0_PHY_198_DATA
+				DDRSS0_PHY_199_DATA
+				DDRSS0_PHY_200_DATA
+				DDRSS0_PHY_201_DATA
+				DDRSS0_PHY_202_DATA
+				DDRSS0_PHY_203_DATA
+				DDRSS0_PHY_204_DATA
+				DDRSS0_PHY_205_DATA
+				DDRSS0_PHY_206_DATA
+				DDRSS0_PHY_207_DATA
+				DDRSS0_PHY_208_DATA
+				DDRSS0_PHY_209_DATA
+				DDRSS0_PHY_210_DATA
+				DDRSS0_PHY_211_DATA
+				DDRSS0_PHY_212_DATA
+				DDRSS0_PHY_213_DATA
+				DDRSS0_PHY_214_DATA
+				DDRSS0_PHY_215_DATA
+				DDRSS0_PHY_216_DATA
+				DDRSS0_PHY_217_DATA
+				DDRSS0_PHY_218_DATA
+				DDRSS0_PHY_219_DATA
+				DDRSS0_PHY_220_DATA
+				DDRSS0_PHY_221_DATA
+				DDRSS0_PHY_222_DATA
+				DDRSS0_PHY_223_DATA
+				DDRSS0_PHY_224_DATA
+				DDRSS0_PHY_225_DATA
+				DDRSS0_PHY_226_DATA
+				DDRSS0_PHY_227_DATA
+				DDRSS0_PHY_228_DATA
+				DDRSS0_PHY_229_DATA
+				DDRSS0_PHY_230_DATA
+				DDRSS0_PHY_231_DATA
+				DDRSS0_PHY_232_DATA
+				DDRSS0_PHY_233_DATA
+				DDRSS0_PHY_234_DATA
+				DDRSS0_PHY_235_DATA
+				DDRSS0_PHY_236_DATA
+				DDRSS0_PHY_237_DATA
+				DDRSS0_PHY_238_DATA
+				DDRSS0_PHY_239_DATA
+				DDRSS0_PHY_240_DATA
+				DDRSS0_PHY_241_DATA
+				DDRSS0_PHY_242_DATA
+				DDRSS0_PHY_243_DATA
+				DDRSS0_PHY_244_DATA
+				DDRSS0_PHY_245_DATA
+				DDRSS0_PHY_246_DATA
+				DDRSS0_PHY_247_DATA
+				DDRSS0_PHY_248_DATA
+				DDRSS0_PHY_249_DATA
+				DDRSS0_PHY_250_DATA
+				DDRSS0_PHY_251_DATA
+				DDRSS0_PHY_252_DATA
+				DDRSS0_PHY_253_DATA
+				DDRSS0_PHY_254_DATA
+				DDRSS0_PHY_255_DATA
+				DDRSS0_PHY_256_DATA
+				DDRSS0_PHY_257_DATA
+				DDRSS0_PHY_258_DATA
+				DDRSS0_PHY_259_DATA
+				DDRSS0_PHY_260_DATA
+				DDRSS0_PHY_261_DATA
+				DDRSS0_PHY_262_DATA
+				DDRSS0_PHY_263_DATA
+				DDRSS0_PHY_264_DATA
+				DDRSS0_PHY_265_DATA
+				DDRSS0_PHY_266_DATA
+				DDRSS0_PHY_267_DATA
+				DDRSS0_PHY_268_DATA
+				DDRSS0_PHY_269_DATA
+				DDRSS0_PHY_270_DATA
+				DDRSS0_PHY_271_DATA
+				DDRSS0_PHY_272_DATA
+				DDRSS0_PHY_273_DATA
+				DDRSS0_PHY_274_DATA
+				DDRSS0_PHY_275_DATA
+				DDRSS0_PHY_276_DATA
+				DDRSS0_PHY_277_DATA
+				DDRSS0_PHY_278_DATA
+				DDRSS0_PHY_279_DATA
+				DDRSS0_PHY_280_DATA
+				DDRSS0_PHY_281_DATA
+				DDRSS0_PHY_282_DATA
+				DDRSS0_PHY_283_DATA
+				DDRSS0_PHY_284_DATA
+				DDRSS0_PHY_285_DATA
+				DDRSS0_PHY_286_DATA
+				DDRSS0_PHY_287_DATA
+				DDRSS0_PHY_288_DATA
+				DDRSS0_PHY_289_DATA
+				DDRSS0_PHY_290_DATA
+				DDRSS0_PHY_291_DATA
+				DDRSS0_PHY_292_DATA
+				DDRSS0_PHY_293_DATA
+				DDRSS0_PHY_294_DATA
+				DDRSS0_PHY_295_DATA
+				DDRSS0_PHY_296_DATA
+				DDRSS0_PHY_297_DATA
+				DDRSS0_PHY_298_DATA
+				DDRSS0_PHY_299_DATA
+				DDRSS0_PHY_300_DATA
+				DDRSS0_PHY_301_DATA
+				DDRSS0_PHY_302_DATA
+				DDRSS0_PHY_303_DATA
+				DDRSS0_PHY_304_DATA
+				DDRSS0_PHY_305_DATA
+				DDRSS0_PHY_306_DATA
+				DDRSS0_PHY_307_DATA
+				DDRSS0_PHY_308_DATA
+				DDRSS0_PHY_309_DATA
+				DDRSS0_PHY_310_DATA
+				DDRSS0_PHY_311_DATA
+				DDRSS0_PHY_312_DATA
+				DDRSS0_PHY_313_DATA
+				DDRSS0_PHY_314_DATA
+				DDRSS0_PHY_315_DATA
+				DDRSS0_PHY_316_DATA
+				DDRSS0_PHY_317_DATA
+				DDRSS0_PHY_318_DATA
+				DDRSS0_PHY_319_DATA
+				DDRSS0_PHY_320_DATA
+				DDRSS0_PHY_321_DATA
+				DDRSS0_PHY_322_DATA
+				DDRSS0_PHY_323_DATA
+				DDRSS0_PHY_324_DATA
+				DDRSS0_PHY_325_DATA
+				DDRSS0_PHY_326_DATA
+				DDRSS0_PHY_327_DATA
+				DDRSS0_PHY_328_DATA
+				DDRSS0_PHY_329_DATA
+				DDRSS0_PHY_330_DATA
+				DDRSS0_PHY_331_DATA
+				DDRSS0_PHY_332_DATA
+				DDRSS0_PHY_333_DATA
+				DDRSS0_PHY_334_DATA
+				DDRSS0_PHY_335_DATA
+				DDRSS0_PHY_336_DATA
+				DDRSS0_PHY_337_DATA
+				DDRSS0_PHY_338_DATA
+				DDRSS0_PHY_339_DATA
+				DDRSS0_PHY_340_DATA
+				DDRSS0_PHY_341_DATA
+				DDRSS0_PHY_342_DATA
+				DDRSS0_PHY_343_DATA
+				DDRSS0_PHY_344_DATA
+				DDRSS0_PHY_345_DATA
+				DDRSS0_PHY_346_DATA
+				DDRSS0_PHY_347_DATA
+				DDRSS0_PHY_348_DATA
+				DDRSS0_PHY_349_DATA
+				DDRSS0_PHY_350_DATA
+				DDRSS0_PHY_351_DATA
+				DDRSS0_PHY_352_DATA
+				DDRSS0_PHY_353_DATA
+				DDRSS0_PHY_354_DATA
+				DDRSS0_PHY_355_DATA
+				DDRSS0_PHY_356_DATA
+				DDRSS0_PHY_357_DATA
+				DDRSS0_PHY_358_DATA
+				DDRSS0_PHY_359_DATA
+				DDRSS0_PHY_360_DATA
+				DDRSS0_PHY_361_DATA
+				DDRSS0_PHY_362_DATA
+				DDRSS0_PHY_363_DATA
+				DDRSS0_PHY_364_DATA
+				DDRSS0_PHY_365_DATA
+				DDRSS0_PHY_366_DATA
+				DDRSS0_PHY_367_DATA
+				DDRSS0_PHY_368_DATA
+				DDRSS0_PHY_369_DATA
+				DDRSS0_PHY_370_DATA
+				DDRSS0_PHY_371_DATA
+				DDRSS0_PHY_372_DATA
+				DDRSS0_PHY_373_DATA
+				DDRSS0_PHY_374_DATA
+				DDRSS0_PHY_375_DATA
+				DDRSS0_PHY_376_DATA
+				DDRSS0_PHY_377_DATA
+				DDRSS0_PHY_378_DATA
+				DDRSS0_PHY_379_DATA
+				DDRSS0_PHY_380_DATA
+				DDRSS0_PHY_381_DATA
+				DDRSS0_PHY_382_DATA
+				DDRSS0_PHY_383_DATA
+				DDRSS0_PHY_384_DATA
+				DDRSS0_PHY_385_DATA
+				DDRSS0_PHY_386_DATA
+				DDRSS0_PHY_387_DATA
+				DDRSS0_PHY_388_DATA
+				DDRSS0_PHY_389_DATA
+				DDRSS0_PHY_390_DATA
+				DDRSS0_PHY_391_DATA
+				DDRSS0_PHY_392_DATA
+				DDRSS0_PHY_393_DATA
+				DDRSS0_PHY_394_DATA
+				DDRSS0_PHY_395_DATA
+				DDRSS0_PHY_396_DATA
+				DDRSS0_PHY_397_DATA
+				DDRSS0_PHY_398_DATA
+				DDRSS0_PHY_399_DATA
+				DDRSS0_PHY_400_DATA
+				DDRSS0_PHY_401_DATA
+				DDRSS0_PHY_402_DATA
+				DDRSS0_PHY_403_DATA
+				DDRSS0_PHY_404_DATA
+				DDRSS0_PHY_405_DATA
+				DDRSS0_PHY_406_DATA
+				DDRSS0_PHY_407_DATA
+				DDRSS0_PHY_408_DATA
+				DDRSS0_PHY_409_DATA
+				DDRSS0_PHY_410_DATA
+				DDRSS0_PHY_411_DATA
+				DDRSS0_PHY_412_DATA
+				DDRSS0_PHY_413_DATA
+				DDRSS0_PHY_414_DATA
+				DDRSS0_PHY_415_DATA
+				DDRSS0_PHY_416_DATA
+				DDRSS0_PHY_417_DATA
+				DDRSS0_PHY_418_DATA
+				DDRSS0_PHY_419_DATA
+				DDRSS0_PHY_420_DATA
+				DDRSS0_PHY_421_DATA
+				DDRSS0_PHY_422_DATA
+				DDRSS0_PHY_423_DATA
+				DDRSS0_PHY_424_DATA
+				DDRSS0_PHY_425_DATA
+				DDRSS0_PHY_426_DATA
+				DDRSS0_PHY_427_DATA
+				DDRSS0_PHY_428_DATA
+				DDRSS0_PHY_429_DATA
+				DDRSS0_PHY_430_DATA
+				DDRSS0_PHY_431_DATA
+				DDRSS0_PHY_432_DATA
+				DDRSS0_PHY_433_DATA
+				DDRSS0_PHY_434_DATA
+				DDRSS0_PHY_435_DATA
+				DDRSS0_PHY_436_DATA
+				DDRSS0_PHY_437_DATA
+				DDRSS0_PHY_438_DATA
+				DDRSS0_PHY_439_DATA
+				DDRSS0_PHY_440_DATA
+				DDRSS0_PHY_441_DATA
+				DDRSS0_PHY_442_DATA
+				DDRSS0_PHY_443_DATA
+				DDRSS0_PHY_444_DATA
+				DDRSS0_PHY_445_DATA
+				DDRSS0_PHY_446_DATA
+				DDRSS0_PHY_447_DATA
+				DDRSS0_PHY_448_DATA
+				DDRSS0_PHY_449_DATA
+				DDRSS0_PHY_450_DATA
+				DDRSS0_PHY_451_DATA
+				DDRSS0_PHY_452_DATA
+				DDRSS0_PHY_453_DATA
+				DDRSS0_PHY_454_DATA
+				DDRSS0_PHY_455_DATA
+				DDRSS0_PHY_456_DATA
+				DDRSS0_PHY_457_DATA
+				DDRSS0_PHY_458_DATA
+				DDRSS0_PHY_459_DATA
+				DDRSS0_PHY_460_DATA
+				DDRSS0_PHY_461_DATA
+				DDRSS0_PHY_462_DATA
+				DDRSS0_PHY_463_DATA
+				DDRSS0_PHY_464_DATA
+				DDRSS0_PHY_465_DATA
+				DDRSS0_PHY_466_DATA
+				DDRSS0_PHY_467_DATA
+				DDRSS0_PHY_468_DATA
+				DDRSS0_PHY_469_DATA
+				DDRSS0_PHY_470_DATA
+				DDRSS0_PHY_471_DATA
+				DDRSS0_PHY_472_DATA
+				DDRSS0_PHY_473_DATA
+				DDRSS0_PHY_474_DATA
+				DDRSS0_PHY_475_DATA
+				DDRSS0_PHY_476_DATA
+				DDRSS0_PHY_477_DATA
+				DDRSS0_PHY_478_DATA
+				DDRSS0_PHY_479_DATA
+				DDRSS0_PHY_480_DATA
+				DDRSS0_PHY_481_DATA
+				DDRSS0_PHY_482_DATA
+				DDRSS0_PHY_483_DATA
+				DDRSS0_PHY_484_DATA
+				DDRSS0_PHY_485_DATA
+				DDRSS0_PHY_486_DATA
+				DDRSS0_PHY_487_DATA
+				DDRSS0_PHY_488_DATA
+				DDRSS0_PHY_489_DATA
+				DDRSS0_PHY_490_DATA
+				DDRSS0_PHY_491_DATA
+				DDRSS0_PHY_492_DATA
+				DDRSS0_PHY_493_DATA
+				DDRSS0_PHY_494_DATA
+				DDRSS0_PHY_495_DATA
+				DDRSS0_PHY_496_DATA
+				DDRSS0_PHY_497_DATA
+				DDRSS0_PHY_498_DATA
+				DDRSS0_PHY_499_DATA
+				DDRSS0_PHY_500_DATA
+				DDRSS0_PHY_501_DATA
+				DDRSS0_PHY_502_DATA
+				DDRSS0_PHY_503_DATA
+				DDRSS0_PHY_504_DATA
+				DDRSS0_PHY_505_DATA
+				DDRSS0_PHY_506_DATA
+				DDRSS0_PHY_507_DATA
+				DDRSS0_PHY_508_DATA
+				DDRSS0_PHY_509_DATA
+				DDRSS0_PHY_510_DATA
+				DDRSS0_PHY_511_DATA
+				DDRSS0_PHY_512_DATA
+				DDRSS0_PHY_513_DATA
+				DDRSS0_PHY_514_DATA
+				DDRSS0_PHY_515_DATA
+				DDRSS0_PHY_516_DATA
+				DDRSS0_PHY_517_DATA
+				DDRSS0_PHY_518_DATA
+				DDRSS0_PHY_519_DATA
+				DDRSS0_PHY_520_DATA
+				DDRSS0_PHY_521_DATA
+				DDRSS0_PHY_522_DATA
+				DDRSS0_PHY_523_DATA
+				DDRSS0_PHY_524_DATA
+				DDRSS0_PHY_525_DATA
+				DDRSS0_PHY_526_DATA
+				DDRSS0_PHY_527_DATA
+				DDRSS0_PHY_528_DATA
+				DDRSS0_PHY_529_DATA
+				DDRSS0_PHY_530_DATA
+				DDRSS0_PHY_531_DATA
+				DDRSS0_PHY_532_DATA
+				DDRSS0_PHY_533_DATA
+				DDRSS0_PHY_534_DATA
+				DDRSS0_PHY_535_DATA
+				DDRSS0_PHY_536_DATA
+				DDRSS0_PHY_537_DATA
+				DDRSS0_PHY_538_DATA
+				DDRSS0_PHY_539_DATA
+				DDRSS0_PHY_540_DATA
+				DDRSS0_PHY_541_DATA
+				DDRSS0_PHY_542_DATA
+				DDRSS0_PHY_543_DATA
+				DDRSS0_PHY_544_DATA
+				DDRSS0_PHY_545_DATA
+				DDRSS0_PHY_546_DATA
+				DDRSS0_PHY_547_DATA
+				DDRSS0_PHY_548_DATA
+				DDRSS0_PHY_549_DATA
+				DDRSS0_PHY_550_DATA
+				DDRSS0_PHY_551_DATA
+				DDRSS0_PHY_552_DATA
+				DDRSS0_PHY_553_DATA
+				DDRSS0_PHY_554_DATA
+				DDRSS0_PHY_555_DATA
+				DDRSS0_PHY_556_DATA
+				DDRSS0_PHY_557_DATA
+				DDRSS0_PHY_558_DATA
+				DDRSS0_PHY_559_DATA
+				DDRSS0_PHY_560_DATA
+				DDRSS0_PHY_561_DATA
+				DDRSS0_PHY_562_DATA
+				DDRSS0_PHY_563_DATA
+				DDRSS0_PHY_564_DATA
+				DDRSS0_PHY_565_DATA
+				DDRSS0_PHY_566_DATA
+				DDRSS0_PHY_567_DATA
+				DDRSS0_PHY_568_DATA
+				DDRSS0_PHY_569_DATA
+				DDRSS0_PHY_570_DATA
+				DDRSS0_PHY_571_DATA
+				DDRSS0_PHY_572_DATA
+				DDRSS0_PHY_573_DATA
+				DDRSS0_PHY_574_DATA
+				DDRSS0_PHY_575_DATA
+				DDRSS0_PHY_576_DATA
+				DDRSS0_PHY_577_DATA
+				DDRSS0_PHY_578_DATA
+				DDRSS0_PHY_579_DATA
+				DDRSS0_PHY_580_DATA
+				DDRSS0_PHY_581_DATA
+				DDRSS0_PHY_582_DATA
+				DDRSS0_PHY_583_DATA
+				DDRSS0_PHY_584_DATA
+				DDRSS0_PHY_585_DATA
+				DDRSS0_PHY_586_DATA
+				DDRSS0_PHY_587_DATA
+				DDRSS0_PHY_588_DATA
+				DDRSS0_PHY_589_DATA
+				DDRSS0_PHY_590_DATA
+				DDRSS0_PHY_591_DATA
+				DDRSS0_PHY_592_DATA
+				DDRSS0_PHY_593_DATA
+				DDRSS0_PHY_594_DATA
+				DDRSS0_PHY_595_DATA
+				DDRSS0_PHY_596_DATA
+				DDRSS0_PHY_597_DATA
+				DDRSS0_PHY_598_DATA
+				DDRSS0_PHY_599_DATA
+				DDRSS0_PHY_600_DATA
+				DDRSS0_PHY_601_DATA
+				DDRSS0_PHY_602_DATA
+				DDRSS0_PHY_603_DATA
+				DDRSS0_PHY_604_DATA
+				DDRSS0_PHY_605_DATA
+				DDRSS0_PHY_606_DATA
+				DDRSS0_PHY_607_DATA
+				DDRSS0_PHY_608_DATA
+				DDRSS0_PHY_609_DATA
+				DDRSS0_PHY_610_DATA
+				DDRSS0_PHY_611_DATA
+				DDRSS0_PHY_612_DATA
+				DDRSS0_PHY_613_DATA
+				DDRSS0_PHY_614_DATA
+				DDRSS0_PHY_615_DATA
+				DDRSS0_PHY_616_DATA
+				DDRSS0_PHY_617_DATA
+				DDRSS0_PHY_618_DATA
+				DDRSS0_PHY_619_DATA
+				DDRSS0_PHY_620_DATA
+				DDRSS0_PHY_621_DATA
+				DDRSS0_PHY_622_DATA
+				DDRSS0_PHY_623_DATA
+				DDRSS0_PHY_624_DATA
+				DDRSS0_PHY_625_DATA
+				DDRSS0_PHY_626_DATA
+				DDRSS0_PHY_627_DATA
+				DDRSS0_PHY_628_DATA
+				DDRSS0_PHY_629_DATA
+				DDRSS0_PHY_630_DATA
+				DDRSS0_PHY_631_DATA
+				DDRSS0_PHY_632_DATA
+				DDRSS0_PHY_633_DATA
+				DDRSS0_PHY_634_DATA
+				DDRSS0_PHY_635_DATA
+				DDRSS0_PHY_636_DATA
+				DDRSS0_PHY_637_DATA
+				DDRSS0_PHY_638_DATA
+				DDRSS0_PHY_639_DATA
+				DDRSS0_PHY_640_DATA
+				DDRSS0_PHY_641_DATA
+				DDRSS0_PHY_642_DATA
+				DDRSS0_PHY_643_DATA
+				DDRSS0_PHY_644_DATA
+				DDRSS0_PHY_645_DATA
+				DDRSS0_PHY_646_DATA
+				DDRSS0_PHY_647_DATA
+				DDRSS0_PHY_648_DATA
+				DDRSS0_PHY_649_DATA
+				DDRSS0_PHY_650_DATA
+				DDRSS0_PHY_651_DATA
+				DDRSS0_PHY_652_DATA
+				DDRSS0_PHY_653_DATA
+				DDRSS0_PHY_654_DATA
+				DDRSS0_PHY_655_DATA
+				DDRSS0_PHY_656_DATA
+				DDRSS0_PHY_657_DATA
+				DDRSS0_PHY_658_DATA
+				DDRSS0_PHY_659_DATA
+				DDRSS0_PHY_660_DATA
+				DDRSS0_PHY_661_DATA
+				DDRSS0_PHY_662_DATA
+				DDRSS0_PHY_663_DATA
+				DDRSS0_PHY_664_DATA
+				DDRSS0_PHY_665_DATA
+				DDRSS0_PHY_666_DATA
+				DDRSS0_PHY_667_DATA
+				DDRSS0_PHY_668_DATA
+				DDRSS0_PHY_669_DATA
+				DDRSS0_PHY_670_DATA
+				DDRSS0_PHY_671_DATA
+				DDRSS0_PHY_672_DATA
+				DDRSS0_PHY_673_DATA
+				DDRSS0_PHY_674_DATA
+				DDRSS0_PHY_675_DATA
+				DDRSS0_PHY_676_DATA
+				DDRSS0_PHY_677_DATA
+				DDRSS0_PHY_678_DATA
+				DDRSS0_PHY_679_DATA
+				DDRSS0_PHY_680_DATA
+				DDRSS0_PHY_681_DATA
+				DDRSS0_PHY_682_DATA
+				DDRSS0_PHY_683_DATA
+				DDRSS0_PHY_684_DATA
+				DDRSS0_PHY_685_DATA
+				DDRSS0_PHY_686_DATA
+				DDRSS0_PHY_687_DATA
+				DDRSS0_PHY_688_DATA
+				DDRSS0_PHY_689_DATA
+				DDRSS0_PHY_690_DATA
+				DDRSS0_PHY_691_DATA
+				DDRSS0_PHY_692_DATA
+				DDRSS0_PHY_693_DATA
+				DDRSS0_PHY_694_DATA
+				DDRSS0_PHY_695_DATA
+				DDRSS0_PHY_696_DATA
+				DDRSS0_PHY_697_DATA
+				DDRSS0_PHY_698_DATA
+				DDRSS0_PHY_699_DATA
+				DDRSS0_PHY_700_DATA
+				DDRSS0_PHY_701_DATA
+				DDRSS0_PHY_702_DATA
+				DDRSS0_PHY_703_DATA
+				DDRSS0_PHY_704_DATA
+				DDRSS0_PHY_705_DATA
+				DDRSS0_PHY_706_DATA
+				DDRSS0_PHY_707_DATA
+				DDRSS0_PHY_708_DATA
+				DDRSS0_PHY_709_DATA
+				DDRSS0_PHY_710_DATA
+				DDRSS0_PHY_711_DATA
+				DDRSS0_PHY_712_DATA
+				DDRSS0_PHY_713_DATA
+				DDRSS0_PHY_714_DATA
+				DDRSS0_PHY_715_DATA
+				DDRSS0_PHY_716_DATA
+				DDRSS0_PHY_717_DATA
+				DDRSS0_PHY_718_DATA
+				DDRSS0_PHY_719_DATA
+				DDRSS0_PHY_720_DATA
+				DDRSS0_PHY_721_DATA
+				DDRSS0_PHY_722_DATA
+				DDRSS0_PHY_723_DATA
+				DDRSS0_PHY_724_DATA
+				DDRSS0_PHY_725_DATA
+				DDRSS0_PHY_726_DATA
+				DDRSS0_PHY_727_DATA
+				DDRSS0_PHY_728_DATA
+				DDRSS0_PHY_729_DATA
+				DDRSS0_PHY_730_DATA
+				DDRSS0_PHY_731_DATA
+				DDRSS0_PHY_732_DATA
+				DDRSS0_PHY_733_DATA
+				DDRSS0_PHY_734_DATA
+				DDRSS0_PHY_735_DATA
+				DDRSS0_PHY_736_DATA
+				DDRSS0_PHY_737_DATA
+				DDRSS0_PHY_738_DATA
+				DDRSS0_PHY_739_DATA
+				DDRSS0_PHY_740_DATA
+				DDRSS0_PHY_741_DATA
+				DDRSS0_PHY_742_DATA
+				DDRSS0_PHY_743_DATA
+				DDRSS0_PHY_744_DATA
+				DDRSS0_PHY_745_DATA
+				DDRSS0_PHY_746_DATA
+				DDRSS0_PHY_747_DATA
+				DDRSS0_PHY_748_DATA
+				DDRSS0_PHY_749_DATA
+				DDRSS0_PHY_750_DATA
+				DDRSS0_PHY_751_DATA
+				DDRSS0_PHY_752_DATA
+				DDRSS0_PHY_753_DATA
+				DDRSS0_PHY_754_DATA
+				DDRSS0_PHY_755_DATA
+				DDRSS0_PHY_756_DATA
+				DDRSS0_PHY_757_DATA
+				DDRSS0_PHY_758_DATA
+				DDRSS0_PHY_759_DATA
+				DDRSS0_PHY_760_DATA
+				DDRSS0_PHY_761_DATA
+				DDRSS0_PHY_762_DATA
+				DDRSS0_PHY_763_DATA
+				DDRSS0_PHY_764_DATA
+				DDRSS0_PHY_765_DATA
+				DDRSS0_PHY_766_DATA
+				DDRSS0_PHY_767_DATA
+				DDRSS0_PHY_768_DATA
+				DDRSS0_PHY_769_DATA
+				DDRSS0_PHY_770_DATA
+				DDRSS0_PHY_771_DATA
+				DDRSS0_PHY_772_DATA
+				DDRSS0_PHY_773_DATA
+				DDRSS0_PHY_774_DATA
+				DDRSS0_PHY_775_DATA
+				DDRSS0_PHY_776_DATA
+				DDRSS0_PHY_777_DATA
+				DDRSS0_PHY_778_DATA
+				DDRSS0_PHY_779_DATA
+				DDRSS0_PHY_780_DATA
+				DDRSS0_PHY_781_DATA
+				DDRSS0_PHY_782_DATA
+				DDRSS0_PHY_783_DATA
+				DDRSS0_PHY_784_DATA
+				DDRSS0_PHY_785_DATA
+				DDRSS0_PHY_786_DATA
+				DDRSS0_PHY_787_DATA
+				DDRSS0_PHY_788_DATA
+				DDRSS0_PHY_789_DATA
+				DDRSS0_PHY_790_DATA
+				DDRSS0_PHY_791_DATA
+				DDRSS0_PHY_792_DATA
+				DDRSS0_PHY_793_DATA
+				DDRSS0_PHY_794_DATA
+				DDRSS0_PHY_795_DATA
+				DDRSS0_PHY_796_DATA
+				DDRSS0_PHY_797_DATA
+				DDRSS0_PHY_798_DATA
+				DDRSS0_PHY_799_DATA
+				DDRSS0_PHY_800_DATA
+				DDRSS0_PHY_801_DATA
+				DDRSS0_PHY_802_DATA
+				DDRSS0_PHY_803_DATA
+				DDRSS0_PHY_804_DATA
+				DDRSS0_PHY_805_DATA
+				DDRSS0_PHY_806_DATA
+				DDRSS0_PHY_807_DATA
+				DDRSS0_PHY_808_DATA
+				DDRSS0_PHY_809_DATA
+				DDRSS0_PHY_810_DATA
+				DDRSS0_PHY_811_DATA
+				DDRSS0_PHY_812_DATA
+				DDRSS0_PHY_813_DATA
+				DDRSS0_PHY_814_DATA
+				DDRSS0_PHY_815_DATA
+				DDRSS0_PHY_816_DATA
+				DDRSS0_PHY_817_DATA
+				DDRSS0_PHY_818_DATA
+				DDRSS0_PHY_819_DATA
+				DDRSS0_PHY_820_DATA
+				DDRSS0_PHY_821_DATA
+				DDRSS0_PHY_822_DATA
+				DDRSS0_PHY_823_DATA
+				DDRSS0_PHY_824_DATA
+				DDRSS0_PHY_825_DATA
+				DDRSS0_PHY_826_DATA
+				DDRSS0_PHY_827_DATA
+				DDRSS0_PHY_828_DATA
+				DDRSS0_PHY_829_DATA
+				DDRSS0_PHY_830_DATA
+				DDRSS0_PHY_831_DATA
+				DDRSS0_PHY_832_DATA
+				DDRSS0_PHY_833_DATA
+				DDRSS0_PHY_834_DATA
+				DDRSS0_PHY_835_DATA
+				DDRSS0_PHY_836_DATA
+				DDRSS0_PHY_837_DATA
+				DDRSS0_PHY_838_DATA
+				DDRSS0_PHY_839_DATA
+				DDRSS0_PHY_840_DATA
+				DDRSS0_PHY_841_DATA
+				DDRSS0_PHY_842_DATA
+				DDRSS0_PHY_843_DATA
+				DDRSS0_PHY_844_DATA
+				DDRSS0_PHY_845_DATA
+				DDRSS0_PHY_846_DATA
+				DDRSS0_PHY_847_DATA
+				DDRSS0_PHY_848_DATA
+				DDRSS0_PHY_849_DATA
+				DDRSS0_PHY_850_DATA
+				DDRSS0_PHY_851_DATA
+				DDRSS0_PHY_852_DATA
+				DDRSS0_PHY_853_DATA
+				DDRSS0_PHY_854_DATA
+				DDRSS0_PHY_855_DATA
+				DDRSS0_PHY_856_DATA
+				DDRSS0_PHY_857_DATA
+				DDRSS0_PHY_858_DATA
+				DDRSS0_PHY_859_DATA
+				DDRSS0_PHY_860_DATA
+				DDRSS0_PHY_861_DATA
+				DDRSS0_PHY_862_DATA
+				DDRSS0_PHY_863_DATA
+				DDRSS0_PHY_864_DATA
+				DDRSS0_PHY_865_DATA
+				DDRSS0_PHY_866_DATA
+				DDRSS0_PHY_867_DATA
+				DDRSS0_PHY_868_DATA
+				DDRSS0_PHY_869_DATA
+				DDRSS0_PHY_870_DATA
+				DDRSS0_PHY_871_DATA
+				DDRSS0_PHY_872_DATA
+				DDRSS0_PHY_873_DATA
+				DDRSS0_PHY_874_DATA
+				DDRSS0_PHY_875_DATA
+				DDRSS0_PHY_876_DATA
+				DDRSS0_PHY_877_DATA
+				DDRSS0_PHY_878_DATA
+				DDRSS0_PHY_879_DATA
+				DDRSS0_PHY_880_DATA
+				DDRSS0_PHY_881_DATA
+				DDRSS0_PHY_882_DATA
+				DDRSS0_PHY_883_DATA
+				DDRSS0_PHY_884_DATA
+				DDRSS0_PHY_885_DATA
+				DDRSS0_PHY_886_DATA
+				DDRSS0_PHY_887_DATA
+				DDRSS0_PHY_888_DATA
+				DDRSS0_PHY_889_DATA
+				DDRSS0_PHY_890_DATA
+				DDRSS0_PHY_891_DATA
+				DDRSS0_PHY_892_DATA
+				DDRSS0_PHY_893_DATA
+				DDRSS0_PHY_894_DATA
+				DDRSS0_PHY_895_DATA
+				DDRSS0_PHY_896_DATA
+				DDRSS0_PHY_897_DATA
+				DDRSS0_PHY_898_DATA
+				DDRSS0_PHY_899_DATA
+				DDRSS0_PHY_900_DATA
+				DDRSS0_PHY_901_DATA
+				DDRSS0_PHY_902_DATA
+				DDRSS0_PHY_903_DATA
+				DDRSS0_PHY_904_DATA
+				DDRSS0_PHY_905_DATA
+				DDRSS0_PHY_906_DATA
+				DDRSS0_PHY_907_DATA
+				DDRSS0_PHY_908_DATA
+				DDRSS0_PHY_909_DATA
+				DDRSS0_PHY_910_DATA
+				DDRSS0_PHY_911_DATA
+				DDRSS0_PHY_912_DATA
+				DDRSS0_PHY_913_DATA
+				DDRSS0_PHY_914_DATA
+				DDRSS0_PHY_915_DATA
+				DDRSS0_PHY_916_DATA
+				DDRSS0_PHY_917_DATA
+				DDRSS0_PHY_918_DATA
+				DDRSS0_PHY_919_DATA
+				DDRSS0_PHY_920_DATA
+				DDRSS0_PHY_921_DATA
+				DDRSS0_PHY_922_DATA
+				DDRSS0_PHY_923_DATA
+				DDRSS0_PHY_924_DATA
+				DDRSS0_PHY_925_DATA
+				DDRSS0_PHY_926_DATA
+				DDRSS0_PHY_927_DATA
+				DDRSS0_PHY_928_DATA
+				DDRSS0_PHY_929_DATA
+				DDRSS0_PHY_930_DATA
+				DDRSS0_PHY_931_DATA
+				DDRSS0_PHY_932_DATA
+				DDRSS0_PHY_933_DATA
+				DDRSS0_PHY_934_DATA
+				DDRSS0_PHY_935_DATA
+				DDRSS0_PHY_936_DATA
+				DDRSS0_PHY_937_DATA
+				DDRSS0_PHY_938_DATA
+				DDRSS0_PHY_939_DATA
+				DDRSS0_PHY_940_DATA
+				DDRSS0_PHY_941_DATA
+				DDRSS0_PHY_942_DATA
+				DDRSS0_PHY_943_DATA
+				DDRSS0_PHY_944_DATA
+				DDRSS0_PHY_945_DATA
+				DDRSS0_PHY_946_DATA
+				DDRSS0_PHY_947_DATA
+				DDRSS0_PHY_948_DATA
+				DDRSS0_PHY_949_DATA
+				DDRSS0_PHY_950_DATA
+				DDRSS0_PHY_951_DATA
+				DDRSS0_PHY_952_DATA
+				DDRSS0_PHY_953_DATA
+				DDRSS0_PHY_954_DATA
+				DDRSS0_PHY_955_DATA
+				DDRSS0_PHY_956_DATA
+				DDRSS0_PHY_957_DATA
+				DDRSS0_PHY_958_DATA
+				DDRSS0_PHY_959_DATA
+				DDRSS0_PHY_960_DATA
+				DDRSS0_PHY_961_DATA
+				DDRSS0_PHY_962_DATA
+				DDRSS0_PHY_963_DATA
+				DDRSS0_PHY_964_DATA
+				DDRSS0_PHY_965_DATA
+				DDRSS0_PHY_966_DATA
+				DDRSS0_PHY_967_DATA
+				DDRSS0_PHY_968_DATA
+				DDRSS0_PHY_969_DATA
+				DDRSS0_PHY_970_DATA
+				DDRSS0_PHY_971_DATA
+				DDRSS0_PHY_972_DATA
+				DDRSS0_PHY_973_DATA
+				DDRSS0_PHY_974_DATA
+				DDRSS0_PHY_975_DATA
+				DDRSS0_PHY_976_DATA
+				DDRSS0_PHY_977_DATA
+				DDRSS0_PHY_978_DATA
+				DDRSS0_PHY_979_DATA
+				DDRSS0_PHY_980_DATA
+				DDRSS0_PHY_981_DATA
+				DDRSS0_PHY_982_DATA
+				DDRSS0_PHY_983_DATA
+				DDRSS0_PHY_984_DATA
+				DDRSS0_PHY_985_DATA
+				DDRSS0_PHY_986_DATA
+				DDRSS0_PHY_987_DATA
+				DDRSS0_PHY_988_DATA
+				DDRSS0_PHY_989_DATA
+				DDRSS0_PHY_990_DATA
+				DDRSS0_PHY_991_DATA
+				DDRSS0_PHY_992_DATA
+				DDRSS0_PHY_993_DATA
+				DDRSS0_PHY_994_DATA
+				DDRSS0_PHY_995_DATA
+				DDRSS0_PHY_996_DATA
+				DDRSS0_PHY_997_DATA
+				DDRSS0_PHY_998_DATA
+				DDRSS0_PHY_999_DATA
+				DDRSS0_PHY_1000_DATA
+				DDRSS0_PHY_1001_DATA
+				DDRSS0_PHY_1002_DATA
+				DDRSS0_PHY_1003_DATA
+				DDRSS0_PHY_1004_DATA
+				DDRSS0_PHY_1005_DATA
+				DDRSS0_PHY_1006_DATA
+				DDRSS0_PHY_1007_DATA
+				DDRSS0_PHY_1008_DATA
+				DDRSS0_PHY_1009_DATA
+				DDRSS0_PHY_1010_DATA
+				DDRSS0_PHY_1011_DATA
+				DDRSS0_PHY_1012_DATA
+				DDRSS0_PHY_1013_DATA
+				DDRSS0_PHY_1014_DATA
+				DDRSS0_PHY_1015_DATA
+				DDRSS0_PHY_1016_DATA
+				DDRSS0_PHY_1017_DATA
+				DDRSS0_PHY_1018_DATA
+				DDRSS0_PHY_1019_DATA
+				DDRSS0_PHY_1020_DATA
+				DDRSS0_PHY_1021_DATA
+				DDRSS0_PHY_1022_DATA
+				DDRSS0_PHY_1023_DATA
+				DDRSS0_PHY_1024_DATA
+				DDRSS0_PHY_1025_DATA
+				DDRSS0_PHY_1026_DATA
+				DDRSS0_PHY_1027_DATA
+				DDRSS0_PHY_1028_DATA
+				DDRSS0_PHY_1029_DATA
+				DDRSS0_PHY_1030_DATA
+				DDRSS0_PHY_1031_DATA
+				DDRSS0_PHY_1032_DATA
+				DDRSS0_PHY_1033_DATA
+				DDRSS0_PHY_1034_DATA
+				DDRSS0_PHY_1035_DATA
+				DDRSS0_PHY_1036_DATA
+				DDRSS0_PHY_1037_DATA
+				DDRSS0_PHY_1038_DATA
+				DDRSS0_PHY_1039_DATA
+				DDRSS0_PHY_1040_DATA
+				DDRSS0_PHY_1041_DATA
+				DDRSS0_PHY_1042_DATA
+				DDRSS0_PHY_1043_DATA
+				DDRSS0_PHY_1044_DATA
+				DDRSS0_PHY_1045_DATA
+				DDRSS0_PHY_1046_DATA
+				DDRSS0_PHY_1047_DATA
+				DDRSS0_PHY_1048_DATA
+				DDRSS0_PHY_1049_DATA
+				DDRSS0_PHY_1050_DATA
+				DDRSS0_PHY_1051_DATA
+				DDRSS0_PHY_1052_DATA
+				DDRSS0_PHY_1053_DATA
+				DDRSS0_PHY_1054_DATA
+				DDRSS0_PHY_1055_DATA
+				DDRSS0_PHY_1056_DATA
+				DDRSS0_PHY_1057_DATA
+				DDRSS0_PHY_1058_DATA
+				DDRSS0_PHY_1059_DATA
+				DDRSS0_PHY_1060_DATA
+				DDRSS0_PHY_1061_DATA
+				DDRSS0_PHY_1062_DATA
+				DDRSS0_PHY_1063_DATA
+				DDRSS0_PHY_1064_DATA
+				DDRSS0_PHY_1065_DATA
+				DDRSS0_PHY_1066_DATA
+				DDRSS0_PHY_1067_DATA
+				DDRSS0_PHY_1068_DATA
+				DDRSS0_PHY_1069_DATA
+				DDRSS0_PHY_1070_DATA
+				DDRSS0_PHY_1071_DATA
+				DDRSS0_PHY_1072_DATA
+				DDRSS0_PHY_1073_DATA
+				DDRSS0_PHY_1074_DATA
+				DDRSS0_PHY_1075_DATA
+				DDRSS0_PHY_1076_DATA
+				DDRSS0_PHY_1077_DATA
+				DDRSS0_PHY_1078_DATA
+				DDRSS0_PHY_1079_DATA
+				DDRSS0_PHY_1080_DATA
+				DDRSS0_PHY_1081_DATA
+				DDRSS0_PHY_1082_DATA
+				DDRSS0_PHY_1083_DATA
+				DDRSS0_PHY_1084_DATA
+				DDRSS0_PHY_1085_DATA
+				DDRSS0_PHY_1086_DATA
+				DDRSS0_PHY_1087_DATA
+				DDRSS0_PHY_1088_DATA
+				DDRSS0_PHY_1089_DATA
+				DDRSS0_PHY_1090_DATA
+				DDRSS0_PHY_1091_DATA
+				DDRSS0_PHY_1092_DATA
+				DDRSS0_PHY_1093_DATA
+				DDRSS0_PHY_1094_DATA
+				DDRSS0_PHY_1095_DATA
+				DDRSS0_PHY_1096_DATA
+				DDRSS0_PHY_1097_DATA
+				DDRSS0_PHY_1098_DATA
+				DDRSS0_PHY_1099_DATA
+				DDRSS0_PHY_1100_DATA
+				DDRSS0_PHY_1101_DATA
+				DDRSS0_PHY_1102_DATA
+				DDRSS0_PHY_1103_DATA
+				DDRSS0_PHY_1104_DATA
+				DDRSS0_PHY_1105_DATA
+				DDRSS0_PHY_1106_DATA
+				DDRSS0_PHY_1107_DATA
+				DDRSS0_PHY_1108_DATA
+				DDRSS0_PHY_1109_DATA
+				DDRSS0_PHY_1110_DATA
+				DDRSS0_PHY_1111_DATA
+				DDRSS0_PHY_1112_DATA
+				DDRSS0_PHY_1113_DATA
+				DDRSS0_PHY_1114_DATA
+				DDRSS0_PHY_1115_DATA
+				DDRSS0_PHY_1116_DATA
+				DDRSS0_PHY_1117_DATA
+				DDRSS0_PHY_1118_DATA
+				DDRSS0_PHY_1119_DATA
+				DDRSS0_PHY_1120_DATA
+				DDRSS0_PHY_1121_DATA
+				DDRSS0_PHY_1122_DATA
+				DDRSS0_PHY_1123_DATA
+				DDRSS0_PHY_1124_DATA
+				DDRSS0_PHY_1125_DATA
+				DDRSS0_PHY_1126_DATA
+				DDRSS0_PHY_1127_DATA
+				DDRSS0_PHY_1128_DATA
+				DDRSS0_PHY_1129_DATA
+				DDRSS0_PHY_1130_DATA
+				DDRSS0_PHY_1131_DATA
+				DDRSS0_PHY_1132_DATA
+				DDRSS0_PHY_1133_DATA
+				DDRSS0_PHY_1134_DATA
+				DDRSS0_PHY_1135_DATA
+				DDRSS0_PHY_1136_DATA
+				DDRSS0_PHY_1137_DATA
+				DDRSS0_PHY_1138_DATA
+				DDRSS0_PHY_1139_DATA
+				DDRSS0_PHY_1140_DATA
+				DDRSS0_PHY_1141_DATA
+				DDRSS0_PHY_1142_DATA
+				DDRSS0_PHY_1143_DATA
+				DDRSS0_PHY_1144_DATA
+				DDRSS0_PHY_1145_DATA
+				DDRSS0_PHY_1146_DATA
+				DDRSS0_PHY_1147_DATA
+				DDRSS0_PHY_1148_DATA
+				DDRSS0_PHY_1149_DATA
+				DDRSS0_PHY_1150_DATA
+				DDRSS0_PHY_1151_DATA
+				DDRSS0_PHY_1152_DATA
+				DDRSS0_PHY_1153_DATA
+				DDRSS0_PHY_1154_DATA
+				DDRSS0_PHY_1155_DATA
+				DDRSS0_PHY_1156_DATA
+				DDRSS0_PHY_1157_DATA
+				DDRSS0_PHY_1158_DATA
+				DDRSS0_PHY_1159_DATA
+				DDRSS0_PHY_1160_DATA
+				DDRSS0_PHY_1161_DATA
+				DDRSS0_PHY_1162_DATA
+				DDRSS0_PHY_1163_DATA
+				DDRSS0_PHY_1164_DATA
+				DDRSS0_PHY_1165_DATA
+				DDRSS0_PHY_1166_DATA
+				DDRSS0_PHY_1167_DATA
+				DDRSS0_PHY_1168_DATA
+				DDRSS0_PHY_1169_DATA
+				DDRSS0_PHY_1170_DATA
+				DDRSS0_PHY_1171_DATA
+				DDRSS0_PHY_1172_DATA
+				DDRSS0_PHY_1173_DATA
+				DDRSS0_PHY_1174_DATA
+				DDRSS0_PHY_1175_DATA
+				DDRSS0_PHY_1176_DATA
+				DDRSS0_PHY_1177_DATA
+				DDRSS0_PHY_1178_DATA
+				DDRSS0_PHY_1179_DATA
+				DDRSS0_PHY_1180_DATA
+				DDRSS0_PHY_1181_DATA
+				DDRSS0_PHY_1182_DATA
+				DDRSS0_PHY_1183_DATA
+				DDRSS0_PHY_1184_DATA
+				DDRSS0_PHY_1185_DATA
+				DDRSS0_PHY_1186_DATA
+				DDRSS0_PHY_1187_DATA
+				DDRSS0_PHY_1188_DATA
+				DDRSS0_PHY_1189_DATA
+				DDRSS0_PHY_1190_DATA
+				DDRSS0_PHY_1191_DATA
+				DDRSS0_PHY_1192_DATA
+				DDRSS0_PHY_1193_DATA
+				DDRSS0_PHY_1194_DATA
+				DDRSS0_PHY_1195_DATA
+				DDRSS0_PHY_1196_DATA
+				DDRSS0_PHY_1197_DATA
+				DDRSS0_PHY_1198_DATA
+				DDRSS0_PHY_1199_DATA
+				DDRSS0_PHY_1200_DATA
+				DDRSS0_PHY_1201_DATA
+				DDRSS0_PHY_1202_DATA
+				DDRSS0_PHY_1203_DATA
+				DDRSS0_PHY_1204_DATA
+				DDRSS0_PHY_1205_DATA
+				DDRSS0_PHY_1206_DATA
+				DDRSS0_PHY_1207_DATA
+				DDRSS0_PHY_1208_DATA
+				DDRSS0_PHY_1209_DATA
+				DDRSS0_PHY_1210_DATA
+				DDRSS0_PHY_1211_DATA
+				DDRSS0_PHY_1212_DATA
+				DDRSS0_PHY_1213_DATA
+				DDRSS0_PHY_1214_DATA
+				DDRSS0_PHY_1215_DATA
+				DDRSS0_PHY_1216_DATA
+				DDRSS0_PHY_1217_DATA
+				DDRSS0_PHY_1218_DATA
+				DDRSS0_PHY_1219_DATA
+				DDRSS0_PHY_1220_DATA
+				DDRSS0_PHY_1221_DATA
+				DDRSS0_PHY_1222_DATA
+				DDRSS0_PHY_1223_DATA
+				DDRSS0_PHY_1224_DATA
+				DDRSS0_PHY_1225_DATA
+				DDRSS0_PHY_1226_DATA
+				DDRSS0_PHY_1227_DATA
+				DDRSS0_PHY_1228_DATA
+				DDRSS0_PHY_1229_DATA
+				DDRSS0_PHY_1230_DATA
+				DDRSS0_PHY_1231_DATA
+				DDRSS0_PHY_1232_DATA
+				DDRSS0_PHY_1233_DATA
+				DDRSS0_PHY_1234_DATA
+				DDRSS0_PHY_1235_DATA
+				DDRSS0_PHY_1236_DATA
+				DDRSS0_PHY_1237_DATA
+				DDRSS0_PHY_1238_DATA
+				DDRSS0_PHY_1239_DATA
+				DDRSS0_PHY_1240_DATA
+				DDRSS0_PHY_1241_DATA
+				DDRSS0_PHY_1242_DATA
+				DDRSS0_PHY_1243_DATA
+				DDRSS0_PHY_1244_DATA
+				DDRSS0_PHY_1245_DATA
+				DDRSS0_PHY_1246_DATA
+				DDRSS0_PHY_1247_DATA
+				DDRSS0_PHY_1248_DATA
+				DDRSS0_PHY_1249_DATA
+				DDRSS0_PHY_1250_DATA
+				DDRSS0_PHY_1251_DATA
+				DDRSS0_PHY_1252_DATA
+				DDRSS0_PHY_1253_DATA
+				DDRSS0_PHY_1254_DATA
+				DDRSS0_PHY_1255_DATA
+				DDRSS0_PHY_1256_DATA
+				DDRSS0_PHY_1257_DATA
+				DDRSS0_PHY_1258_DATA
+				DDRSS0_PHY_1259_DATA
+				DDRSS0_PHY_1260_DATA
+				DDRSS0_PHY_1261_DATA
+				DDRSS0_PHY_1262_DATA
+				DDRSS0_PHY_1263_DATA
+				DDRSS0_PHY_1264_DATA
+				DDRSS0_PHY_1265_DATA
+				DDRSS0_PHY_1266_DATA
+				DDRSS0_PHY_1267_DATA
+				DDRSS0_PHY_1268_DATA
+				DDRSS0_PHY_1269_DATA
+				DDRSS0_PHY_1270_DATA
+				DDRSS0_PHY_1271_DATA
+				DDRSS0_PHY_1272_DATA
+				DDRSS0_PHY_1273_DATA
+				DDRSS0_PHY_1274_DATA
+				DDRSS0_PHY_1275_DATA
+				DDRSS0_PHY_1276_DATA
+				DDRSS0_PHY_1277_DATA
+				DDRSS0_PHY_1278_DATA
+				DDRSS0_PHY_1279_DATA
+				DDRSS0_PHY_1280_DATA
+				DDRSS0_PHY_1281_DATA
+				DDRSS0_PHY_1282_DATA
+				DDRSS0_PHY_1283_DATA
+				DDRSS0_PHY_1284_DATA
+				DDRSS0_PHY_1285_DATA
+				DDRSS0_PHY_1286_DATA
+				DDRSS0_PHY_1287_DATA
+				DDRSS0_PHY_1288_DATA
+				DDRSS0_PHY_1289_DATA
+				DDRSS0_PHY_1290_DATA
+				DDRSS0_PHY_1291_DATA
+				DDRSS0_PHY_1292_DATA
+				DDRSS0_PHY_1293_DATA
+				DDRSS0_PHY_1294_DATA
+				DDRSS0_PHY_1295_DATA
+				DDRSS0_PHY_1296_DATA
+				DDRSS0_PHY_1297_DATA
+				DDRSS0_PHY_1298_DATA
+				DDRSS0_PHY_1299_DATA
+				DDRSS0_PHY_1300_DATA
+				DDRSS0_PHY_1301_DATA
+				DDRSS0_PHY_1302_DATA
+				DDRSS0_PHY_1303_DATA
+				DDRSS0_PHY_1304_DATA
+				DDRSS0_PHY_1305_DATA
+				DDRSS0_PHY_1306_DATA
+				DDRSS0_PHY_1307_DATA
+				DDRSS0_PHY_1308_DATA
+				DDRSS0_PHY_1309_DATA
+				DDRSS0_PHY_1310_DATA
+				DDRSS0_PHY_1311_DATA
+				DDRSS0_PHY_1312_DATA
+				DDRSS0_PHY_1313_DATA
+				DDRSS0_PHY_1314_DATA
+				DDRSS0_PHY_1315_DATA
+				DDRSS0_PHY_1316_DATA
+				DDRSS0_PHY_1317_DATA
+				DDRSS0_PHY_1318_DATA
+				DDRSS0_PHY_1319_DATA
+				DDRSS0_PHY_1320_DATA
+				DDRSS0_PHY_1321_DATA
+				DDRSS0_PHY_1322_DATA
+				DDRSS0_PHY_1323_DATA
+				DDRSS0_PHY_1324_DATA
+				DDRSS0_PHY_1325_DATA
+				DDRSS0_PHY_1326_DATA
+				DDRSS0_PHY_1327_DATA
+				DDRSS0_PHY_1328_DATA
+				DDRSS0_PHY_1329_DATA
+				DDRSS0_PHY_1330_DATA
+				DDRSS0_PHY_1331_DATA
+				DDRSS0_PHY_1332_DATA
+				DDRSS0_PHY_1333_DATA
+				DDRSS0_PHY_1334_DATA
+				DDRSS0_PHY_1335_DATA
+				DDRSS0_PHY_1336_DATA
+				DDRSS0_PHY_1337_DATA
+				DDRSS0_PHY_1338_DATA
+				DDRSS0_PHY_1339_DATA
+				DDRSS0_PHY_1340_DATA
+				DDRSS0_PHY_1341_DATA
+				DDRSS0_PHY_1342_DATA
+				DDRSS0_PHY_1343_DATA
+				DDRSS0_PHY_1344_DATA
+				DDRSS0_PHY_1345_DATA
+				DDRSS0_PHY_1346_DATA
+				DDRSS0_PHY_1347_DATA
+				DDRSS0_PHY_1348_DATA
+				DDRSS0_PHY_1349_DATA
+				DDRSS0_PHY_1350_DATA
+				DDRSS0_PHY_1351_DATA
+				DDRSS0_PHY_1352_DATA
+				DDRSS0_PHY_1353_DATA
+				DDRSS0_PHY_1354_DATA
+				DDRSS0_PHY_1355_DATA
+				DDRSS0_PHY_1356_DATA
+				DDRSS0_PHY_1357_DATA
+				DDRSS0_PHY_1358_DATA
+				DDRSS0_PHY_1359_DATA
+				DDRSS0_PHY_1360_DATA
+				DDRSS0_PHY_1361_DATA
+				DDRSS0_PHY_1362_DATA
+				DDRSS0_PHY_1363_DATA
+				DDRSS0_PHY_1364_DATA
+				DDRSS0_PHY_1365_DATA
+				DDRSS0_PHY_1366_DATA
+				DDRSS0_PHY_1367_DATA
+				DDRSS0_PHY_1368_DATA
+				DDRSS0_PHY_1369_DATA
+				DDRSS0_PHY_1370_DATA
+				DDRSS0_PHY_1371_DATA
+				DDRSS0_PHY_1372_DATA
+				DDRSS0_PHY_1373_DATA
+				DDRSS0_PHY_1374_DATA
+				DDRSS0_PHY_1375_DATA
+				DDRSS0_PHY_1376_DATA
+				DDRSS0_PHY_1377_DATA
+				DDRSS0_PHY_1378_DATA
+				DDRSS0_PHY_1379_DATA
+				DDRSS0_PHY_1380_DATA
+				DDRSS0_PHY_1381_DATA
+				DDRSS0_PHY_1382_DATA
+				DDRSS0_PHY_1383_DATA
+				DDRSS0_PHY_1384_DATA
+				DDRSS0_PHY_1385_DATA
+				DDRSS0_PHY_1386_DATA
+				DDRSS0_PHY_1387_DATA
+				DDRSS0_PHY_1388_DATA
+				DDRSS0_PHY_1389_DATA
+				DDRSS0_PHY_1390_DATA
+				DDRSS0_PHY_1391_DATA
+				DDRSS0_PHY_1392_DATA
+				DDRSS0_PHY_1393_DATA
+				DDRSS0_PHY_1394_DATA
+				DDRSS0_PHY_1395_DATA
+				DDRSS0_PHY_1396_DATA
+				DDRSS0_PHY_1397_DATA
+				DDRSS0_PHY_1398_DATA
+				DDRSS0_PHY_1399_DATA
+				DDRSS0_PHY_1400_DATA
+				DDRSS0_PHY_1401_DATA
+				DDRSS0_PHY_1402_DATA
+				DDRSS0_PHY_1403_DATA
+				DDRSS0_PHY_1404_DATA
+				DDRSS0_PHY_1405_DATA
+				DDRSS0_PHY_1406_DATA
+				DDRSS0_PHY_1407_DATA
+				DDRSS0_PHY_1408_DATA
+				DDRSS0_PHY_1409_DATA
+				DDRSS0_PHY_1410_DATA
+				DDRSS0_PHY_1411_DATA
+				DDRSS0_PHY_1412_DATA
+				DDRSS0_PHY_1413_DATA
+				DDRSS0_PHY_1414_DATA
+				DDRSS0_PHY_1415_DATA
+				DDRSS0_PHY_1416_DATA
+				DDRSS0_PHY_1417_DATA
+				DDRSS0_PHY_1418_DATA
+				DDRSS0_PHY_1419_DATA
+				DDRSS0_PHY_1420_DATA
+				DDRSS0_PHY_1421_DATA
+				DDRSS0_PHY_1422_DATA
+			>;
+		};
+
+		memorycontroller1: memorycontroller@29b0000 {
+			compatible = "ti,j721s2-ddrss";
+			reg = <0x0 0x029b0000 0x0 0x4000>,
+			      <0x0 0x0114000 0x0 0x100>,
+				  <0x0 0x029a0000 0x0 0x200>;
+			reg-names = "cfg", "ctrl_mmr_lp4", "ss_cfg";
+			power-domains = <&k3_pds 192 TI_SCI_PD_SHARED>,
+				<&k3_pds 132 TI_SCI_PD_SHARED>;
+			clocks = <&k3_clks 192 1>, <&k3_clks 78 2>;
+			ti,ddr-freq0 = <DDRSS_PLL_FREQUENCY_0>;
+			ti,ddr-freq1 = <DDRSS_PLL_FREQUENCY_1>;
+			ti,ddr-freq2 = <DDRSS_PLL_FREQUENCY_2>;
+			ti,ddr-fhs-cnt = <DDRSS_PLL_FHS_CNT>;
+			instance = <1>;
+
+			bootph-pre-ram;
+
+			ti,ctl-data = <
+				DDRSS1_CTL_00_DATA
+				DDRSS1_CTL_01_DATA
+				DDRSS1_CTL_02_DATA
+				DDRSS1_CTL_03_DATA
+				DDRSS1_CTL_04_DATA
+				DDRSS1_CTL_05_DATA
+				DDRSS1_CTL_06_DATA
+				DDRSS1_CTL_07_DATA
+				DDRSS1_CTL_08_DATA
+				DDRSS1_CTL_09_DATA
+				DDRSS1_CTL_10_DATA
+				DDRSS1_CTL_11_DATA
+				DDRSS1_CTL_12_DATA
+				DDRSS1_CTL_13_DATA
+				DDRSS1_CTL_14_DATA
+				DDRSS1_CTL_15_DATA
+				DDRSS1_CTL_16_DATA
+				DDRSS1_CTL_17_DATA
+				DDRSS1_CTL_18_DATA
+				DDRSS1_CTL_19_DATA
+				DDRSS1_CTL_20_DATA
+				DDRSS1_CTL_21_DATA
+				DDRSS1_CTL_22_DATA
+				DDRSS1_CTL_23_DATA
+				DDRSS1_CTL_24_DATA
+				DDRSS1_CTL_25_DATA
+				DDRSS1_CTL_26_DATA
+				DDRSS1_CTL_27_DATA
+				DDRSS1_CTL_28_DATA
+				DDRSS1_CTL_29_DATA
+				DDRSS1_CTL_30_DATA
+				DDRSS1_CTL_31_DATA
+				DDRSS1_CTL_32_DATA
+				DDRSS1_CTL_33_DATA
+				DDRSS1_CTL_34_DATA
+				DDRSS1_CTL_35_DATA
+				DDRSS1_CTL_36_DATA
+				DDRSS1_CTL_37_DATA
+				DDRSS1_CTL_38_DATA
+				DDRSS1_CTL_39_DATA
+				DDRSS1_CTL_40_DATA
+				DDRSS1_CTL_41_DATA
+				DDRSS1_CTL_42_DATA
+				DDRSS1_CTL_43_DATA
+				DDRSS1_CTL_44_DATA
+				DDRSS1_CTL_45_DATA
+				DDRSS1_CTL_46_DATA
+				DDRSS1_CTL_47_DATA
+				DDRSS1_CTL_48_DATA
+				DDRSS1_CTL_49_DATA
+				DDRSS1_CTL_50_DATA
+				DDRSS1_CTL_51_DATA
+				DDRSS1_CTL_52_DATA
+				DDRSS1_CTL_53_DATA
+				DDRSS1_CTL_54_DATA
+				DDRSS1_CTL_55_DATA
+				DDRSS1_CTL_56_DATA
+				DDRSS1_CTL_57_DATA
+				DDRSS1_CTL_58_DATA
+				DDRSS1_CTL_59_DATA
+				DDRSS1_CTL_60_DATA
+				DDRSS1_CTL_61_DATA
+				DDRSS1_CTL_62_DATA
+				DDRSS1_CTL_63_DATA
+				DDRSS1_CTL_64_DATA
+				DDRSS1_CTL_65_DATA
+				DDRSS1_CTL_66_DATA
+				DDRSS1_CTL_67_DATA
+				DDRSS1_CTL_68_DATA
+				DDRSS1_CTL_69_DATA
+				DDRSS1_CTL_70_DATA
+				DDRSS1_CTL_71_DATA
+				DDRSS1_CTL_72_DATA
+				DDRSS1_CTL_73_DATA
+				DDRSS1_CTL_74_DATA
+				DDRSS1_CTL_75_DATA
+				DDRSS1_CTL_76_DATA
+				DDRSS1_CTL_77_DATA
+				DDRSS1_CTL_78_DATA
+				DDRSS1_CTL_79_DATA
+				DDRSS1_CTL_80_DATA
+				DDRSS1_CTL_81_DATA
+				DDRSS1_CTL_82_DATA
+				DDRSS1_CTL_83_DATA
+				DDRSS1_CTL_84_DATA
+				DDRSS1_CTL_85_DATA
+				DDRSS1_CTL_86_DATA
+				DDRSS1_CTL_87_DATA
+				DDRSS1_CTL_88_DATA
+				DDRSS1_CTL_89_DATA
+				DDRSS1_CTL_90_DATA
+				DDRSS1_CTL_91_DATA
+				DDRSS1_CTL_92_DATA
+				DDRSS1_CTL_93_DATA
+				DDRSS1_CTL_94_DATA
+				DDRSS1_CTL_95_DATA
+				DDRSS1_CTL_96_DATA
+				DDRSS1_CTL_97_DATA
+				DDRSS1_CTL_98_DATA
+				DDRSS1_CTL_99_DATA
+				DDRSS1_CTL_100_DATA
+				DDRSS1_CTL_101_DATA
+				DDRSS1_CTL_102_DATA
+				DDRSS1_CTL_103_DATA
+				DDRSS1_CTL_104_DATA
+				DDRSS1_CTL_105_DATA
+				DDRSS1_CTL_106_DATA
+				DDRSS1_CTL_107_DATA
+				DDRSS1_CTL_108_DATA
+				DDRSS1_CTL_109_DATA
+				DDRSS1_CTL_110_DATA
+				DDRSS1_CTL_111_DATA
+				DDRSS1_CTL_112_DATA
+				DDRSS1_CTL_113_DATA
+				DDRSS1_CTL_114_DATA
+				DDRSS1_CTL_115_DATA
+				DDRSS1_CTL_116_DATA
+				DDRSS1_CTL_117_DATA
+				DDRSS1_CTL_118_DATA
+				DDRSS1_CTL_119_DATA
+				DDRSS1_CTL_120_DATA
+				DDRSS1_CTL_121_DATA
+				DDRSS1_CTL_122_DATA
+				DDRSS1_CTL_123_DATA
+				DDRSS1_CTL_124_DATA
+				DDRSS1_CTL_125_DATA
+				DDRSS1_CTL_126_DATA
+				DDRSS1_CTL_127_DATA
+				DDRSS1_CTL_128_DATA
+				DDRSS1_CTL_129_DATA
+				DDRSS1_CTL_130_DATA
+				DDRSS1_CTL_131_DATA
+				DDRSS1_CTL_132_DATA
+				DDRSS1_CTL_133_DATA
+				DDRSS1_CTL_134_DATA
+				DDRSS1_CTL_135_DATA
+				DDRSS1_CTL_136_DATA
+				DDRSS1_CTL_137_DATA
+				DDRSS1_CTL_138_DATA
+				DDRSS1_CTL_139_DATA
+				DDRSS1_CTL_140_DATA
+				DDRSS1_CTL_141_DATA
+				DDRSS1_CTL_142_DATA
+				DDRSS1_CTL_143_DATA
+				DDRSS1_CTL_144_DATA
+				DDRSS1_CTL_145_DATA
+				DDRSS1_CTL_146_DATA
+				DDRSS1_CTL_147_DATA
+				DDRSS1_CTL_148_DATA
+				DDRSS1_CTL_149_DATA
+				DDRSS1_CTL_150_DATA
+				DDRSS1_CTL_151_DATA
+				DDRSS1_CTL_152_DATA
+				DDRSS1_CTL_153_DATA
+				DDRSS1_CTL_154_DATA
+				DDRSS1_CTL_155_DATA
+				DDRSS1_CTL_156_DATA
+				DDRSS1_CTL_157_DATA
+				DDRSS1_CTL_158_DATA
+				DDRSS1_CTL_159_DATA
+				DDRSS1_CTL_160_DATA
+				DDRSS1_CTL_161_DATA
+				DDRSS1_CTL_162_DATA
+				DDRSS1_CTL_163_DATA
+				DDRSS1_CTL_164_DATA
+				DDRSS1_CTL_165_DATA
+				DDRSS1_CTL_166_DATA
+				DDRSS1_CTL_167_DATA
+				DDRSS1_CTL_168_DATA
+				DDRSS1_CTL_169_DATA
+				DDRSS1_CTL_170_DATA
+				DDRSS1_CTL_171_DATA
+				DDRSS1_CTL_172_DATA
+				DDRSS1_CTL_173_DATA
+				DDRSS1_CTL_174_DATA
+				DDRSS1_CTL_175_DATA
+				DDRSS1_CTL_176_DATA
+				DDRSS1_CTL_177_DATA
+				DDRSS1_CTL_178_DATA
+				DDRSS1_CTL_179_DATA
+				DDRSS1_CTL_180_DATA
+				DDRSS1_CTL_181_DATA
+				DDRSS1_CTL_182_DATA
+				DDRSS1_CTL_183_DATA
+				DDRSS1_CTL_184_DATA
+				DDRSS1_CTL_185_DATA
+				DDRSS1_CTL_186_DATA
+				DDRSS1_CTL_187_DATA
+				DDRSS1_CTL_188_DATA
+				DDRSS1_CTL_189_DATA
+				DDRSS1_CTL_190_DATA
+				DDRSS1_CTL_191_DATA
+				DDRSS1_CTL_192_DATA
+				DDRSS1_CTL_193_DATA
+				DDRSS1_CTL_194_DATA
+				DDRSS1_CTL_195_DATA
+				DDRSS1_CTL_196_DATA
+				DDRSS1_CTL_197_DATA
+				DDRSS1_CTL_198_DATA
+				DDRSS1_CTL_199_DATA
+				DDRSS1_CTL_200_DATA
+				DDRSS1_CTL_201_DATA
+				DDRSS1_CTL_202_DATA
+				DDRSS1_CTL_203_DATA
+				DDRSS1_CTL_204_DATA
+				DDRSS1_CTL_205_DATA
+				DDRSS1_CTL_206_DATA
+				DDRSS1_CTL_207_DATA
+				DDRSS1_CTL_208_DATA
+				DDRSS1_CTL_209_DATA
+				DDRSS1_CTL_210_DATA
+				DDRSS1_CTL_211_DATA
+				DDRSS1_CTL_212_DATA
+				DDRSS1_CTL_213_DATA
+				DDRSS1_CTL_214_DATA
+				DDRSS1_CTL_215_DATA
+				DDRSS1_CTL_216_DATA
+				DDRSS1_CTL_217_DATA
+				DDRSS1_CTL_218_DATA
+				DDRSS1_CTL_219_DATA
+				DDRSS1_CTL_220_DATA
+				DDRSS1_CTL_221_DATA
+				DDRSS1_CTL_222_DATA
+				DDRSS1_CTL_223_DATA
+				DDRSS1_CTL_224_DATA
+				DDRSS1_CTL_225_DATA
+				DDRSS1_CTL_226_DATA
+				DDRSS1_CTL_227_DATA
+				DDRSS1_CTL_228_DATA
+				DDRSS1_CTL_229_DATA
+				DDRSS1_CTL_230_DATA
+				DDRSS1_CTL_231_DATA
+				DDRSS1_CTL_232_DATA
+				DDRSS1_CTL_233_DATA
+				DDRSS1_CTL_234_DATA
+				DDRSS1_CTL_235_DATA
+				DDRSS1_CTL_236_DATA
+				DDRSS1_CTL_237_DATA
+				DDRSS1_CTL_238_DATA
+				DDRSS1_CTL_239_DATA
+				DDRSS1_CTL_240_DATA
+				DDRSS1_CTL_241_DATA
+				DDRSS1_CTL_242_DATA
+				DDRSS1_CTL_243_DATA
+				DDRSS1_CTL_244_DATA
+				DDRSS1_CTL_245_DATA
+				DDRSS1_CTL_246_DATA
+				DDRSS1_CTL_247_DATA
+				DDRSS1_CTL_248_DATA
+				DDRSS1_CTL_249_DATA
+				DDRSS1_CTL_250_DATA
+				DDRSS1_CTL_251_DATA
+				DDRSS1_CTL_252_DATA
+				DDRSS1_CTL_253_DATA
+				DDRSS1_CTL_254_DATA
+				DDRSS1_CTL_255_DATA
+				DDRSS1_CTL_256_DATA
+				DDRSS1_CTL_257_DATA
+				DDRSS1_CTL_258_DATA
+				DDRSS1_CTL_259_DATA
+				DDRSS1_CTL_260_DATA
+				DDRSS1_CTL_261_DATA
+				DDRSS1_CTL_262_DATA
+				DDRSS1_CTL_263_DATA
+				DDRSS1_CTL_264_DATA
+				DDRSS1_CTL_265_DATA
+				DDRSS1_CTL_266_DATA
+				DDRSS1_CTL_267_DATA
+				DDRSS1_CTL_268_DATA
+				DDRSS1_CTL_269_DATA
+				DDRSS1_CTL_270_DATA
+				DDRSS1_CTL_271_DATA
+				DDRSS1_CTL_272_DATA
+				DDRSS1_CTL_273_DATA
+				DDRSS1_CTL_274_DATA
+				DDRSS1_CTL_275_DATA
+				DDRSS1_CTL_276_DATA
+				DDRSS1_CTL_277_DATA
+				DDRSS1_CTL_278_DATA
+				DDRSS1_CTL_279_DATA
+				DDRSS1_CTL_280_DATA
+				DDRSS1_CTL_281_DATA
+				DDRSS1_CTL_282_DATA
+				DDRSS1_CTL_283_DATA
+				DDRSS1_CTL_284_DATA
+				DDRSS1_CTL_285_DATA
+				DDRSS1_CTL_286_DATA
+				DDRSS1_CTL_287_DATA
+				DDRSS1_CTL_288_DATA
+				DDRSS1_CTL_289_DATA
+				DDRSS1_CTL_290_DATA
+				DDRSS1_CTL_291_DATA
+				DDRSS1_CTL_292_DATA
+				DDRSS1_CTL_293_DATA
+				DDRSS1_CTL_294_DATA
+				DDRSS1_CTL_295_DATA
+				DDRSS1_CTL_296_DATA
+				DDRSS1_CTL_297_DATA
+				DDRSS1_CTL_298_DATA
+				DDRSS1_CTL_299_DATA
+				DDRSS1_CTL_300_DATA
+				DDRSS1_CTL_301_DATA
+				DDRSS1_CTL_302_DATA
+				DDRSS1_CTL_303_DATA
+				DDRSS1_CTL_304_DATA
+				DDRSS1_CTL_305_DATA
+				DDRSS1_CTL_306_DATA
+				DDRSS1_CTL_307_DATA
+				DDRSS1_CTL_308_DATA
+				DDRSS1_CTL_309_DATA
+				DDRSS1_CTL_310_DATA
+				DDRSS1_CTL_311_DATA
+				DDRSS1_CTL_312_DATA
+				DDRSS1_CTL_313_DATA
+				DDRSS1_CTL_314_DATA
+				DDRSS1_CTL_315_DATA
+				DDRSS1_CTL_316_DATA
+				DDRSS1_CTL_317_DATA
+				DDRSS1_CTL_318_DATA
+				DDRSS1_CTL_319_DATA
+				DDRSS1_CTL_320_DATA
+				DDRSS1_CTL_321_DATA
+				DDRSS1_CTL_322_DATA
+				DDRSS1_CTL_323_DATA
+				DDRSS1_CTL_324_DATA
+				DDRSS1_CTL_325_DATA
+				DDRSS1_CTL_326_DATA
+				DDRSS1_CTL_327_DATA
+				DDRSS1_CTL_328_DATA
+				DDRSS1_CTL_329_DATA
+				DDRSS1_CTL_330_DATA
+				DDRSS1_CTL_331_DATA
+				DDRSS1_CTL_332_DATA
+				DDRSS1_CTL_333_DATA
+				DDRSS1_CTL_334_DATA
+				DDRSS1_CTL_335_DATA
+				DDRSS1_CTL_336_DATA
+				DDRSS1_CTL_337_DATA
+				DDRSS1_CTL_338_DATA
+				DDRSS1_CTL_339_DATA
+				DDRSS1_CTL_340_DATA
+				DDRSS1_CTL_341_DATA
+				DDRSS1_CTL_342_DATA
+				DDRSS1_CTL_343_DATA
+				DDRSS1_CTL_344_DATA
+				DDRSS1_CTL_345_DATA
+				DDRSS1_CTL_346_DATA
+				DDRSS1_CTL_347_DATA
+				DDRSS1_CTL_348_DATA
+				DDRSS1_CTL_349_DATA
+				DDRSS1_CTL_350_DATA
+				DDRSS1_CTL_351_DATA
+				DDRSS1_CTL_352_DATA
+				DDRSS1_CTL_353_DATA
+				DDRSS1_CTL_354_DATA
+				DDRSS1_CTL_355_DATA
+				DDRSS1_CTL_356_DATA
+				DDRSS1_CTL_357_DATA
+				DDRSS1_CTL_358_DATA
+				DDRSS1_CTL_359_DATA
+				DDRSS1_CTL_360_DATA
+				DDRSS1_CTL_361_DATA
+				DDRSS1_CTL_362_DATA
+				DDRSS1_CTL_363_DATA
+				DDRSS1_CTL_364_DATA
+				DDRSS1_CTL_365_DATA
+				DDRSS1_CTL_366_DATA
+				DDRSS1_CTL_367_DATA
+				DDRSS1_CTL_368_DATA
+				DDRSS1_CTL_369_DATA
+				DDRSS1_CTL_370_DATA
+				DDRSS1_CTL_371_DATA
+				DDRSS1_CTL_372_DATA
+				DDRSS1_CTL_373_DATA
+				DDRSS1_CTL_374_DATA
+				DDRSS1_CTL_375_DATA
+				DDRSS1_CTL_376_DATA
+				DDRSS1_CTL_377_DATA
+				DDRSS1_CTL_378_DATA
+				DDRSS1_CTL_379_DATA
+				DDRSS1_CTL_380_DATA
+				DDRSS1_CTL_381_DATA
+				DDRSS1_CTL_382_DATA
+				DDRSS1_CTL_383_DATA
+				DDRSS1_CTL_384_DATA
+				DDRSS1_CTL_385_DATA
+				DDRSS1_CTL_386_DATA
+				DDRSS1_CTL_387_DATA
+				DDRSS1_CTL_388_DATA
+				DDRSS1_CTL_389_DATA
+				DDRSS1_CTL_390_DATA
+				DDRSS1_CTL_391_DATA
+				DDRSS1_CTL_392_DATA
+				DDRSS1_CTL_393_DATA
+				DDRSS1_CTL_394_DATA
+				DDRSS1_CTL_395_DATA
+				DDRSS1_CTL_396_DATA
+				DDRSS1_CTL_397_DATA
+				DDRSS1_CTL_398_DATA
+				DDRSS1_CTL_399_DATA
+				DDRSS1_CTL_400_DATA
+				DDRSS1_CTL_401_DATA
+				DDRSS1_CTL_402_DATA
+				DDRSS1_CTL_403_DATA
+				DDRSS1_CTL_404_DATA
+				DDRSS1_CTL_405_DATA
+				DDRSS1_CTL_406_DATA
+				DDRSS1_CTL_407_DATA
+				DDRSS1_CTL_408_DATA
+				DDRSS1_CTL_409_DATA
+				DDRSS1_CTL_410_DATA
+				DDRSS1_CTL_411_DATA
+				DDRSS1_CTL_412_DATA
+				DDRSS1_CTL_413_DATA
+				DDRSS1_CTL_414_DATA
+				DDRSS1_CTL_415_DATA
+				DDRSS1_CTL_416_DATA
+				DDRSS1_CTL_417_DATA
+				DDRSS1_CTL_418_DATA
+				DDRSS1_CTL_419_DATA
+				DDRSS1_CTL_420_DATA
+				DDRSS1_CTL_421_DATA
+				DDRSS1_CTL_422_DATA
+				DDRSS1_CTL_423_DATA
+				DDRSS1_CTL_424_DATA
+				DDRSS1_CTL_425_DATA
+				DDRSS1_CTL_426_DATA
+				DDRSS1_CTL_427_DATA
+				DDRSS1_CTL_428_DATA
+				DDRSS1_CTL_429_DATA
+				DDRSS1_CTL_430_DATA
+				DDRSS1_CTL_431_DATA
+				DDRSS1_CTL_432_DATA
+				DDRSS1_CTL_433_DATA
+				DDRSS1_CTL_434_DATA
+				DDRSS1_CTL_435_DATA
+				DDRSS1_CTL_436_DATA
+				DDRSS1_CTL_437_DATA
+				DDRSS1_CTL_438_DATA
+				DDRSS1_CTL_439_DATA
+				DDRSS1_CTL_440_DATA
+				DDRSS1_CTL_441_DATA
+				DDRSS1_CTL_442_DATA
+				DDRSS1_CTL_443_DATA
+				DDRSS1_CTL_444_DATA
+				DDRSS1_CTL_445_DATA
+				DDRSS1_CTL_446_DATA
+				DDRSS1_CTL_447_DATA
+				DDRSS1_CTL_448_DATA
+				DDRSS1_CTL_449_DATA
+				DDRSS1_CTL_450_DATA
+				DDRSS1_CTL_451_DATA
+				DDRSS1_CTL_452_DATA
+				DDRSS1_CTL_453_DATA
+				DDRSS1_CTL_454_DATA
+				DDRSS1_CTL_455_DATA
+				DDRSS1_CTL_456_DATA
+				DDRSS1_CTL_457_DATA
+				DDRSS1_CTL_458_DATA
+			>;
+
+			ti,pi-data = <
+				DDRSS1_PI_00_DATA
+				DDRSS1_PI_01_DATA
+				DDRSS1_PI_02_DATA
+				DDRSS1_PI_03_DATA
+				DDRSS1_PI_04_DATA
+				DDRSS1_PI_05_DATA
+				DDRSS1_PI_06_DATA
+				DDRSS1_PI_07_DATA
+				DDRSS1_PI_08_DATA
+				DDRSS1_PI_09_DATA
+				DDRSS1_PI_10_DATA
+				DDRSS1_PI_11_DATA
+				DDRSS1_PI_12_DATA
+				DDRSS1_PI_13_DATA
+				DDRSS1_PI_14_DATA
+				DDRSS1_PI_15_DATA
+				DDRSS1_PI_16_DATA
+				DDRSS1_PI_17_DATA
+				DDRSS1_PI_18_DATA
+				DDRSS1_PI_19_DATA
+				DDRSS1_PI_20_DATA
+				DDRSS1_PI_21_DATA
+				DDRSS1_PI_22_DATA
+				DDRSS1_PI_23_DATA
+				DDRSS1_PI_24_DATA
+				DDRSS1_PI_25_DATA
+				DDRSS1_PI_26_DATA
+				DDRSS1_PI_27_DATA
+				DDRSS1_PI_28_DATA
+				DDRSS1_PI_29_DATA
+				DDRSS1_PI_30_DATA
+				DDRSS1_PI_31_DATA
+				DDRSS1_PI_32_DATA
+				DDRSS1_PI_33_DATA
+				DDRSS1_PI_34_DATA
+				DDRSS1_PI_35_DATA
+				DDRSS1_PI_36_DATA
+				DDRSS1_PI_37_DATA
+				DDRSS1_PI_38_DATA
+				DDRSS1_PI_39_DATA
+				DDRSS1_PI_40_DATA
+				DDRSS1_PI_41_DATA
+				DDRSS1_PI_42_DATA
+				DDRSS1_PI_43_DATA
+				DDRSS1_PI_44_DATA
+				DDRSS1_PI_45_DATA
+				DDRSS1_PI_46_DATA
+				DDRSS1_PI_47_DATA
+				DDRSS1_PI_48_DATA
+				DDRSS1_PI_49_DATA
+				DDRSS1_PI_50_DATA
+				DDRSS1_PI_51_DATA
+				DDRSS1_PI_52_DATA
+				DDRSS1_PI_53_DATA
+				DDRSS1_PI_54_DATA
+				DDRSS1_PI_55_DATA
+				DDRSS1_PI_56_DATA
+				DDRSS1_PI_57_DATA
+				DDRSS1_PI_58_DATA
+				DDRSS1_PI_59_DATA
+				DDRSS1_PI_60_DATA
+				DDRSS1_PI_61_DATA
+				DDRSS1_PI_62_DATA
+				DDRSS1_PI_63_DATA
+				DDRSS1_PI_64_DATA
+				DDRSS1_PI_65_DATA
+				DDRSS1_PI_66_DATA
+				DDRSS1_PI_67_DATA
+				DDRSS1_PI_68_DATA
+				DDRSS1_PI_69_DATA
+				DDRSS1_PI_70_DATA
+				DDRSS1_PI_71_DATA
+				DDRSS1_PI_72_DATA
+				DDRSS1_PI_73_DATA
+				DDRSS1_PI_74_DATA
+				DDRSS1_PI_75_DATA
+				DDRSS1_PI_76_DATA
+				DDRSS1_PI_77_DATA
+				DDRSS1_PI_78_DATA
+				DDRSS1_PI_79_DATA
+				DDRSS1_PI_80_DATA
+				DDRSS1_PI_81_DATA
+				DDRSS1_PI_82_DATA
+				DDRSS1_PI_83_DATA
+				DDRSS1_PI_84_DATA
+				DDRSS1_PI_85_DATA
+				DDRSS1_PI_86_DATA
+				DDRSS1_PI_87_DATA
+				DDRSS1_PI_88_DATA
+				DDRSS1_PI_89_DATA
+				DDRSS1_PI_90_DATA
+				DDRSS1_PI_91_DATA
+				DDRSS1_PI_92_DATA
+				DDRSS1_PI_93_DATA
+				DDRSS1_PI_94_DATA
+				DDRSS1_PI_95_DATA
+				DDRSS1_PI_96_DATA
+				DDRSS1_PI_97_DATA
+				DDRSS1_PI_98_DATA
+				DDRSS1_PI_99_DATA
+				DDRSS1_PI_100_DATA
+				DDRSS1_PI_101_DATA
+				DDRSS1_PI_102_DATA
+				DDRSS1_PI_103_DATA
+				DDRSS1_PI_104_DATA
+				DDRSS1_PI_105_DATA
+				DDRSS1_PI_106_DATA
+				DDRSS1_PI_107_DATA
+				DDRSS1_PI_108_DATA
+				DDRSS1_PI_109_DATA
+				DDRSS1_PI_110_DATA
+				DDRSS1_PI_111_DATA
+				DDRSS1_PI_112_DATA
+				DDRSS1_PI_113_DATA
+				DDRSS1_PI_114_DATA
+				DDRSS1_PI_115_DATA
+				DDRSS1_PI_116_DATA
+				DDRSS1_PI_117_DATA
+				DDRSS1_PI_118_DATA
+				DDRSS1_PI_119_DATA
+				DDRSS1_PI_120_DATA
+				DDRSS1_PI_121_DATA
+				DDRSS1_PI_122_DATA
+				DDRSS1_PI_123_DATA
+				DDRSS1_PI_124_DATA
+				DDRSS1_PI_125_DATA
+				DDRSS1_PI_126_DATA
+				DDRSS1_PI_127_DATA
+				DDRSS1_PI_128_DATA
+				DDRSS1_PI_129_DATA
+				DDRSS1_PI_130_DATA
+				DDRSS1_PI_131_DATA
+				DDRSS1_PI_132_DATA
+				DDRSS1_PI_133_DATA
+				DDRSS1_PI_134_DATA
+				DDRSS1_PI_135_DATA
+				DDRSS1_PI_136_DATA
+				DDRSS1_PI_137_DATA
+				DDRSS1_PI_138_DATA
+				DDRSS1_PI_139_DATA
+				DDRSS1_PI_140_DATA
+				DDRSS1_PI_141_DATA
+				DDRSS1_PI_142_DATA
+				DDRSS1_PI_143_DATA
+				DDRSS1_PI_144_DATA
+				DDRSS1_PI_145_DATA
+				DDRSS1_PI_146_DATA
+				DDRSS1_PI_147_DATA
+				DDRSS1_PI_148_DATA
+				DDRSS1_PI_149_DATA
+				DDRSS1_PI_150_DATA
+				DDRSS1_PI_151_DATA
+				DDRSS1_PI_152_DATA
+				DDRSS1_PI_153_DATA
+				DDRSS1_PI_154_DATA
+				DDRSS1_PI_155_DATA
+				DDRSS1_PI_156_DATA
+				DDRSS1_PI_157_DATA
+				DDRSS1_PI_158_DATA
+				DDRSS1_PI_159_DATA
+				DDRSS1_PI_160_DATA
+				DDRSS1_PI_161_DATA
+				DDRSS1_PI_162_DATA
+				DDRSS1_PI_163_DATA
+				DDRSS1_PI_164_DATA
+				DDRSS1_PI_165_DATA
+				DDRSS1_PI_166_DATA
+				DDRSS1_PI_167_DATA
+				DDRSS1_PI_168_DATA
+				DDRSS1_PI_169_DATA
+				DDRSS1_PI_170_DATA
+				DDRSS1_PI_171_DATA
+				DDRSS1_PI_172_DATA
+				DDRSS1_PI_173_DATA
+				DDRSS1_PI_174_DATA
+				DDRSS1_PI_175_DATA
+				DDRSS1_PI_176_DATA
+				DDRSS1_PI_177_DATA
+				DDRSS1_PI_178_DATA
+				DDRSS1_PI_179_DATA
+				DDRSS1_PI_180_DATA
+				DDRSS1_PI_181_DATA
+				DDRSS1_PI_182_DATA
+				DDRSS1_PI_183_DATA
+				DDRSS1_PI_184_DATA
+				DDRSS1_PI_185_DATA
+				DDRSS1_PI_186_DATA
+				DDRSS1_PI_187_DATA
+				DDRSS1_PI_188_DATA
+				DDRSS1_PI_189_DATA
+				DDRSS1_PI_190_DATA
+				DDRSS1_PI_191_DATA
+				DDRSS1_PI_192_DATA
+				DDRSS1_PI_193_DATA
+				DDRSS1_PI_194_DATA
+				DDRSS1_PI_195_DATA
+				DDRSS1_PI_196_DATA
+				DDRSS1_PI_197_DATA
+				DDRSS1_PI_198_DATA
+				DDRSS1_PI_199_DATA
+				DDRSS1_PI_200_DATA
+				DDRSS1_PI_201_DATA
+				DDRSS1_PI_202_DATA
+				DDRSS1_PI_203_DATA
+				DDRSS1_PI_204_DATA
+				DDRSS1_PI_205_DATA
+				DDRSS1_PI_206_DATA
+				DDRSS1_PI_207_DATA
+				DDRSS1_PI_208_DATA
+				DDRSS1_PI_209_DATA
+				DDRSS1_PI_210_DATA
+				DDRSS1_PI_211_DATA
+				DDRSS1_PI_212_DATA
+				DDRSS1_PI_213_DATA
+				DDRSS1_PI_214_DATA
+				DDRSS1_PI_215_DATA
+				DDRSS1_PI_216_DATA
+				DDRSS1_PI_217_DATA
+				DDRSS1_PI_218_DATA
+				DDRSS1_PI_219_DATA
+				DDRSS1_PI_220_DATA
+				DDRSS1_PI_221_DATA
+				DDRSS1_PI_222_DATA
+				DDRSS1_PI_223_DATA
+				DDRSS1_PI_224_DATA
+				DDRSS1_PI_225_DATA
+				DDRSS1_PI_226_DATA
+				DDRSS1_PI_227_DATA
+				DDRSS1_PI_228_DATA
+				DDRSS1_PI_229_DATA
+				DDRSS1_PI_230_DATA
+				DDRSS1_PI_231_DATA
+				DDRSS1_PI_232_DATA
+				DDRSS1_PI_233_DATA
+				DDRSS1_PI_234_DATA
+				DDRSS1_PI_235_DATA
+				DDRSS1_PI_236_DATA
+				DDRSS1_PI_237_DATA
+				DDRSS1_PI_238_DATA
+				DDRSS1_PI_239_DATA
+				DDRSS1_PI_240_DATA
+				DDRSS1_PI_241_DATA
+				DDRSS1_PI_242_DATA
+				DDRSS1_PI_243_DATA
+				DDRSS1_PI_244_DATA
+				DDRSS1_PI_245_DATA
+				DDRSS1_PI_246_DATA
+				DDRSS1_PI_247_DATA
+				DDRSS1_PI_248_DATA
+				DDRSS1_PI_249_DATA
+				DDRSS1_PI_250_DATA
+				DDRSS1_PI_251_DATA
+				DDRSS1_PI_252_DATA
+				DDRSS1_PI_253_DATA
+				DDRSS1_PI_254_DATA
+				DDRSS1_PI_255_DATA
+				DDRSS1_PI_256_DATA
+				DDRSS1_PI_257_DATA
+				DDRSS1_PI_258_DATA
+				DDRSS1_PI_259_DATA
+				DDRSS1_PI_260_DATA
+				DDRSS1_PI_261_DATA
+				DDRSS1_PI_262_DATA
+				DDRSS1_PI_263_DATA
+				DDRSS1_PI_264_DATA
+				DDRSS1_PI_265_DATA
+				DDRSS1_PI_266_DATA
+				DDRSS1_PI_267_DATA
+				DDRSS1_PI_268_DATA
+				DDRSS1_PI_269_DATA
+				DDRSS1_PI_270_DATA
+				DDRSS1_PI_271_DATA
+				DDRSS1_PI_272_DATA
+				DDRSS1_PI_273_DATA
+				DDRSS1_PI_274_DATA
+				DDRSS1_PI_275_DATA
+				DDRSS1_PI_276_DATA
+				DDRSS1_PI_277_DATA
+				DDRSS1_PI_278_DATA
+				DDRSS1_PI_279_DATA
+				DDRSS1_PI_280_DATA
+				DDRSS1_PI_281_DATA
+				DDRSS1_PI_282_DATA
+				DDRSS1_PI_283_DATA
+				DDRSS1_PI_284_DATA
+				DDRSS1_PI_285_DATA
+				DDRSS1_PI_286_DATA
+				DDRSS1_PI_287_DATA
+				DDRSS1_PI_288_DATA
+				DDRSS1_PI_289_DATA
+				DDRSS1_PI_290_DATA
+				DDRSS1_PI_291_DATA
+				DDRSS1_PI_292_DATA
+				DDRSS1_PI_293_DATA
+				DDRSS1_PI_294_DATA
+				DDRSS1_PI_295_DATA
+				DDRSS1_PI_296_DATA
+				DDRSS1_PI_297_DATA
+				DDRSS1_PI_298_DATA
+				DDRSS1_PI_299_DATA
+			>;
+
+			ti,phy-data = <
+				DDRSS1_PHY_00_DATA
+				DDRSS1_PHY_01_DATA
+				DDRSS1_PHY_02_DATA
+				DDRSS1_PHY_03_DATA
+				DDRSS1_PHY_04_DATA
+				DDRSS1_PHY_05_DATA
+				DDRSS1_PHY_06_DATA
+				DDRSS1_PHY_07_DATA
+				DDRSS1_PHY_08_DATA
+				DDRSS1_PHY_09_DATA
+				DDRSS1_PHY_10_DATA
+				DDRSS1_PHY_11_DATA
+				DDRSS1_PHY_12_DATA
+				DDRSS1_PHY_13_DATA
+				DDRSS1_PHY_14_DATA
+				DDRSS1_PHY_15_DATA
+				DDRSS1_PHY_16_DATA
+				DDRSS1_PHY_17_DATA
+				DDRSS1_PHY_18_DATA
+				DDRSS1_PHY_19_DATA
+				DDRSS1_PHY_20_DATA
+				DDRSS1_PHY_21_DATA
+				DDRSS1_PHY_22_DATA
+				DDRSS1_PHY_23_DATA
+				DDRSS1_PHY_24_DATA
+				DDRSS1_PHY_25_DATA
+				DDRSS1_PHY_26_DATA
+				DDRSS1_PHY_27_DATA
+				DDRSS1_PHY_28_DATA
+				DDRSS1_PHY_29_DATA
+				DDRSS1_PHY_30_DATA
+				DDRSS1_PHY_31_DATA
+				DDRSS1_PHY_32_DATA
+				DDRSS1_PHY_33_DATA
+				DDRSS1_PHY_34_DATA
+				DDRSS1_PHY_35_DATA
+				DDRSS1_PHY_36_DATA
+				DDRSS1_PHY_37_DATA
+				DDRSS1_PHY_38_DATA
+				DDRSS1_PHY_39_DATA
+				DDRSS1_PHY_40_DATA
+				DDRSS1_PHY_41_DATA
+				DDRSS1_PHY_42_DATA
+				DDRSS1_PHY_43_DATA
+				DDRSS1_PHY_44_DATA
+				DDRSS1_PHY_45_DATA
+				DDRSS1_PHY_46_DATA
+				DDRSS1_PHY_47_DATA
+				DDRSS1_PHY_48_DATA
+				DDRSS1_PHY_49_DATA
+				DDRSS1_PHY_50_DATA
+				DDRSS1_PHY_51_DATA
+				DDRSS1_PHY_52_DATA
+				DDRSS1_PHY_53_DATA
+				DDRSS1_PHY_54_DATA
+				DDRSS1_PHY_55_DATA
+				DDRSS1_PHY_56_DATA
+				DDRSS1_PHY_57_DATA
+				DDRSS1_PHY_58_DATA
+				DDRSS1_PHY_59_DATA
+				DDRSS1_PHY_60_DATA
+				DDRSS1_PHY_61_DATA
+				DDRSS1_PHY_62_DATA
+				DDRSS1_PHY_63_DATA
+				DDRSS1_PHY_64_DATA
+				DDRSS1_PHY_65_DATA
+				DDRSS1_PHY_66_DATA
+				DDRSS1_PHY_67_DATA
+				DDRSS1_PHY_68_DATA
+				DDRSS1_PHY_69_DATA
+				DDRSS1_PHY_70_DATA
+				DDRSS1_PHY_71_DATA
+				DDRSS1_PHY_72_DATA
+				DDRSS1_PHY_73_DATA
+				DDRSS1_PHY_74_DATA
+				DDRSS1_PHY_75_DATA
+				DDRSS1_PHY_76_DATA
+				DDRSS1_PHY_77_DATA
+				DDRSS1_PHY_78_DATA
+				DDRSS1_PHY_79_DATA
+				DDRSS1_PHY_80_DATA
+				DDRSS1_PHY_81_DATA
+				DDRSS1_PHY_82_DATA
+				DDRSS1_PHY_83_DATA
+				DDRSS1_PHY_84_DATA
+				DDRSS1_PHY_85_DATA
+				DDRSS1_PHY_86_DATA
+				DDRSS1_PHY_87_DATA
+				DDRSS1_PHY_88_DATA
+				DDRSS1_PHY_89_DATA
+				DDRSS1_PHY_90_DATA
+				DDRSS1_PHY_91_DATA
+				DDRSS1_PHY_92_DATA
+				DDRSS1_PHY_93_DATA
+				DDRSS1_PHY_94_DATA
+				DDRSS1_PHY_95_DATA
+				DDRSS1_PHY_96_DATA
+				DDRSS1_PHY_97_DATA
+				DDRSS1_PHY_98_DATA
+				DDRSS1_PHY_99_DATA
+				DDRSS1_PHY_100_DATA
+				DDRSS1_PHY_101_DATA
+				DDRSS1_PHY_102_DATA
+				DDRSS1_PHY_103_DATA
+				DDRSS1_PHY_104_DATA
+				DDRSS1_PHY_105_DATA
+				DDRSS1_PHY_106_DATA
+				DDRSS1_PHY_107_DATA
+				DDRSS1_PHY_108_DATA
+				DDRSS1_PHY_109_DATA
+				DDRSS1_PHY_110_DATA
+				DDRSS1_PHY_111_DATA
+				DDRSS1_PHY_112_DATA
+				DDRSS1_PHY_113_DATA
+				DDRSS1_PHY_114_DATA
+				DDRSS1_PHY_115_DATA
+				DDRSS1_PHY_116_DATA
+				DDRSS1_PHY_117_DATA
+				DDRSS1_PHY_118_DATA
+				DDRSS1_PHY_119_DATA
+				DDRSS1_PHY_120_DATA
+				DDRSS1_PHY_121_DATA
+				DDRSS1_PHY_122_DATA
+				DDRSS1_PHY_123_DATA
+				DDRSS1_PHY_124_DATA
+				DDRSS1_PHY_125_DATA
+				DDRSS1_PHY_126_DATA
+				DDRSS1_PHY_127_DATA
+				DDRSS1_PHY_128_DATA
+				DDRSS1_PHY_129_DATA
+				DDRSS1_PHY_130_DATA
+				DDRSS1_PHY_131_DATA
+				DDRSS1_PHY_132_DATA
+				DDRSS1_PHY_133_DATA
+				DDRSS1_PHY_134_DATA
+				DDRSS1_PHY_135_DATA
+				DDRSS1_PHY_136_DATA
+				DDRSS1_PHY_137_DATA
+				DDRSS1_PHY_138_DATA
+				DDRSS1_PHY_139_DATA
+				DDRSS1_PHY_140_DATA
+				DDRSS1_PHY_141_DATA
+				DDRSS1_PHY_142_DATA
+				DDRSS1_PHY_143_DATA
+				DDRSS1_PHY_144_DATA
+				DDRSS1_PHY_145_DATA
+				DDRSS1_PHY_146_DATA
+				DDRSS1_PHY_147_DATA
+				DDRSS1_PHY_148_DATA
+				DDRSS1_PHY_149_DATA
+				DDRSS1_PHY_150_DATA
+				DDRSS1_PHY_151_DATA
+				DDRSS1_PHY_152_DATA
+				DDRSS1_PHY_153_DATA
+				DDRSS1_PHY_154_DATA
+				DDRSS1_PHY_155_DATA
+				DDRSS1_PHY_156_DATA
+				DDRSS1_PHY_157_DATA
+				DDRSS1_PHY_158_DATA
+				DDRSS1_PHY_159_DATA
+				DDRSS1_PHY_160_DATA
+				DDRSS1_PHY_161_DATA
+				DDRSS1_PHY_162_DATA
+				DDRSS1_PHY_163_DATA
+				DDRSS1_PHY_164_DATA
+				DDRSS1_PHY_165_DATA
+				DDRSS1_PHY_166_DATA
+				DDRSS1_PHY_167_DATA
+				DDRSS1_PHY_168_DATA
+				DDRSS1_PHY_169_DATA
+				DDRSS1_PHY_170_DATA
+				DDRSS1_PHY_171_DATA
+				DDRSS1_PHY_172_DATA
+				DDRSS1_PHY_173_DATA
+				DDRSS1_PHY_174_DATA
+				DDRSS1_PHY_175_DATA
+				DDRSS1_PHY_176_DATA
+				DDRSS1_PHY_177_DATA
+				DDRSS1_PHY_178_DATA
+				DDRSS1_PHY_179_DATA
+				DDRSS1_PHY_180_DATA
+				DDRSS1_PHY_181_DATA
+				DDRSS1_PHY_182_DATA
+				DDRSS1_PHY_183_DATA
+				DDRSS1_PHY_184_DATA
+				DDRSS1_PHY_185_DATA
+				DDRSS1_PHY_186_DATA
+				DDRSS1_PHY_187_DATA
+				DDRSS1_PHY_188_DATA
+				DDRSS1_PHY_189_DATA
+				DDRSS1_PHY_190_DATA
+				DDRSS1_PHY_191_DATA
+				DDRSS1_PHY_192_DATA
+				DDRSS1_PHY_193_DATA
+				DDRSS1_PHY_194_DATA
+				DDRSS1_PHY_195_DATA
+				DDRSS1_PHY_196_DATA
+				DDRSS1_PHY_197_DATA
+				DDRSS1_PHY_198_DATA
+				DDRSS1_PHY_199_DATA
+				DDRSS1_PHY_200_DATA
+				DDRSS1_PHY_201_DATA
+				DDRSS1_PHY_202_DATA
+				DDRSS1_PHY_203_DATA
+				DDRSS1_PHY_204_DATA
+				DDRSS1_PHY_205_DATA
+				DDRSS1_PHY_206_DATA
+				DDRSS1_PHY_207_DATA
+				DDRSS1_PHY_208_DATA
+				DDRSS1_PHY_209_DATA
+				DDRSS1_PHY_210_DATA
+				DDRSS1_PHY_211_DATA
+				DDRSS1_PHY_212_DATA
+				DDRSS1_PHY_213_DATA
+				DDRSS1_PHY_214_DATA
+				DDRSS1_PHY_215_DATA
+				DDRSS1_PHY_216_DATA
+				DDRSS1_PHY_217_DATA
+				DDRSS1_PHY_218_DATA
+				DDRSS1_PHY_219_DATA
+				DDRSS1_PHY_220_DATA
+				DDRSS1_PHY_221_DATA
+				DDRSS1_PHY_222_DATA
+				DDRSS1_PHY_223_DATA
+				DDRSS1_PHY_224_DATA
+				DDRSS1_PHY_225_DATA
+				DDRSS1_PHY_226_DATA
+				DDRSS1_PHY_227_DATA
+				DDRSS1_PHY_228_DATA
+				DDRSS1_PHY_229_DATA
+				DDRSS1_PHY_230_DATA
+				DDRSS1_PHY_231_DATA
+				DDRSS1_PHY_232_DATA
+				DDRSS1_PHY_233_DATA
+				DDRSS1_PHY_234_DATA
+				DDRSS1_PHY_235_DATA
+				DDRSS1_PHY_236_DATA
+				DDRSS1_PHY_237_DATA
+				DDRSS1_PHY_238_DATA
+				DDRSS1_PHY_239_DATA
+				DDRSS1_PHY_240_DATA
+				DDRSS1_PHY_241_DATA
+				DDRSS1_PHY_242_DATA
+				DDRSS1_PHY_243_DATA
+				DDRSS1_PHY_244_DATA
+				DDRSS1_PHY_245_DATA
+				DDRSS1_PHY_246_DATA
+				DDRSS1_PHY_247_DATA
+				DDRSS1_PHY_248_DATA
+				DDRSS1_PHY_249_DATA
+				DDRSS1_PHY_250_DATA
+				DDRSS1_PHY_251_DATA
+				DDRSS1_PHY_252_DATA
+				DDRSS1_PHY_253_DATA
+				DDRSS1_PHY_254_DATA
+				DDRSS1_PHY_255_DATA
+				DDRSS1_PHY_256_DATA
+				DDRSS1_PHY_257_DATA
+				DDRSS1_PHY_258_DATA
+				DDRSS1_PHY_259_DATA
+				DDRSS1_PHY_260_DATA
+				DDRSS1_PHY_261_DATA
+				DDRSS1_PHY_262_DATA
+				DDRSS1_PHY_263_DATA
+				DDRSS1_PHY_264_DATA
+				DDRSS1_PHY_265_DATA
+				DDRSS1_PHY_266_DATA
+				DDRSS1_PHY_267_DATA
+				DDRSS1_PHY_268_DATA
+				DDRSS1_PHY_269_DATA
+				DDRSS1_PHY_270_DATA
+				DDRSS1_PHY_271_DATA
+				DDRSS1_PHY_272_DATA
+				DDRSS1_PHY_273_DATA
+				DDRSS1_PHY_274_DATA
+				DDRSS1_PHY_275_DATA
+				DDRSS1_PHY_276_DATA
+				DDRSS1_PHY_277_DATA
+				DDRSS1_PHY_278_DATA
+				DDRSS1_PHY_279_DATA
+				DDRSS1_PHY_280_DATA
+				DDRSS1_PHY_281_DATA
+				DDRSS1_PHY_282_DATA
+				DDRSS1_PHY_283_DATA
+				DDRSS1_PHY_284_DATA
+				DDRSS1_PHY_285_DATA
+				DDRSS1_PHY_286_DATA
+				DDRSS1_PHY_287_DATA
+				DDRSS1_PHY_288_DATA
+				DDRSS1_PHY_289_DATA
+				DDRSS1_PHY_290_DATA
+				DDRSS1_PHY_291_DATA
+				DDRSS1_PHY_292_DATA
+				DDRSS1_PHY_293_DATA
+				DDRSS1_PHY_294_DATA
+				DDRSS1_PHY_295_DATA
+				DDRSS1_PHY_296_DATA
+				DDRSS1_PHY_297_DATA
+				DDRSS1_PHY_298_DATA
+				DDRSS1_PHY_299_DATA
+				DDRSS1_PHY_300_DATA
+				DDRSS1_PHY_301_DATA
+				DDRSS1_PHY_302_DATA
+				DDRSS1_PHY_303_DATA
+				DDRSS1_PHY_304_DATA
+				DDRSS1_PHY_305_DATA
+				DDRSS1_PHY_306_DATA
+				DDRSS1_PHY_307_DATA
+				DDRSS1_PHY_308_DATA
+				DDRSS1_PHY_309_DATA
+				DDRSS1_PHY_310_DATA
+				DDRSS1_PHY_311_DATA
+				DDRSS1_PHY_312_DATA
+				DDRSS1_PHY_313_DATA
+				DDRSS1_PHY_314_DATA
+				DDRSS1_PHY_315_DATA
+				DDRSS1_PHY_316_DATA
+				DDRSS1_PHY_317_DATA
+				DDRSS1_PHY_318_DATA
+				DDRSS1_PHY_319_DATA
+				DDRSS1_PHY_320_DATA
+				DDRSS1_PHY_321_DATA
+				DDRSS1_PHY_322_DATA
+				DDRSS1_PHY_323_DATA
+				DDRSS1_PHY_324_DATA
+				DDRSS1_PHY_325_DATA
+				DDRSS1_PHY_326_DATA
+				DDRSS1_PHY_327_DATA
+				DDRSS1_PHY_328_DATA
+				DDRSS1_PHY_329_DATA
+				DDRSS1_PHY_330_DATA
+				DDRSS1_PHY_331_DATA
+				DDRSS1_PHY_332_DATA
+				DDRSS1_PHY_333_DATA
+				DDRSS1_PHY_334_DATA
+				DDRSS1_PHY_335_DATA
+				DDRSS1_PHY_336_DATA
+				DDRSS1_PHY_337_DATA
+				DDRSS1_PHY_338_DATA
+				DDRSS1_PHY_339_DATA
+				DDRSS1_PHY_340_DATA
+				DDRSS1_PHY_341_DATA
+				DDRSS1_PHY_342_DATA
+				DDRSS1_PHY_343_DATA
+				DDRSS1_PHY_344_DATA
+				DDRSS1_PHY_345_DATA
+				DDRSS1_PHY_346_DATA
+				DDRSS1_PHY_347_DATA
+				DDRSS1_PHY_348_DATA
+				DDRSS1_PHY_349_DATA
+				DDRSS1_PHY_350_DATA
+				DDRSS1_PHY_351_DATA
+				DDRSS1_PHY_352_DATA
+				DDRSS1_PHY_353_DATA
+				DDRSS1_PHY_354_DATA
+				DDRSS1_PHY_355_DATA
+				DDRSS1_PHY_356_DATA
+				DDRSS1_PHY_357_DATA
+				DDRSS1_PHY_358_DATA
+				DDRSS1_PHY_359_DATA
+				DDRSS1_PHY_360_DATA
+				DDRSS1_PHY_361_DATA
+				DDRSS1_PHY_362_DATA
+				DDRSS1_PHY_363_DATA
+				DDRSS1_PHY_364_DATA
+				DDRSS1_PHY_365_DATA
+				DDRSS1_PHY_366_DATA
+				DDRSS1_PHY_367_DATA
+				DDRSS1_PHY_368_DATA
+				DDRSS1_PHY_369_DATA
+				DDRSS1_PHY_370_DATA
+				DDRSS1_PHY_371_DATA
+				DDRSS1_PHY_372_DATA
+				DDRSS1_PHY_373_DATA
+				DDRSS1_PHY_374_DATA
+				DDRSS1_PHY_375_DATA
+				DDRSS1_PHY_376_DATA
+				DDRSS1_PHY_377_DATA
+				DDRSS1_PHY_378_DATA
+				DDRSS1_PHY_379_DATA
+				DDRSS1_PHY_380_DATA
+				DDRSS1_PHY_381_DATA
+				DDRSS1_PHY_382_DATA
+				DDRSS1_PHY_383_DATA
+				DDRSS1_PHY_384_DATA
+				DDRSS1_PHY_385_DATA
+				DDRSS1_PHY_386_DATA
+				DDRSS1_PHY_387_DATA
+				DDRSS1_PHY_388_DATA
+				DDRSS1_PHY_389_DATA
+				DDRSS1_PHY_390_DATA
+				DDRSS1_PHY_391_DATA
+				DDRSS1_PHY_392_DATA
+				DDRSS1_PHY_393_DATA
+				DDRSS1_PHY_394_DATA
+				DDRSS1_PHY_395_DATA
+				DDRSS1_PHY_396_DATA
+				DDRSS1_PHY_397_DATA
+				DDRSS1_PHY_398_DATA
+				DDRSS1_PHY_399_DATA
+				DDRSS1_PHY_400_DATA
+				DDRSS1_PHY_401_DATA
+				DDRSS1_PHY_402_DATA
+				DDRSS1_PHY_403_DATA
+				DDRSS1_PHY_404_DATA
+				DDRSS1_PHY_405_DATA
+				DDRSS1_PHY_406_DATA
+				DDRSS1_PHY_407_DATA
+				DDRSS1_PHY_408_DATA
+				DDRSS1_PHY_409_DATA
+				DDRSS1_PHY_410_DATA
+				DDRSS1_PHY_411_DATA
+				DDRSS1_PHY_412_DATA
+				DDRSS1_PHY_413_DATA
+				DDRSS1_PHY_414_DATA
+				DDRSS1_PHY_415_DATA
+				DDRSS1_PHY_416_DATA
+				DDRSS1_PHY_417_DATA
+				DDRSS1_PHY_418_DATA
+				DDRSS1_PHY_419_DATA
+				DDRSS1_PHY_420_DATA
+				DDRSS1_PHY_421_DATA
+				DDRSS1_PHY_422_DATA
+				DDRSS1_PHY_423_DATA
+				DDRSS1_PHY_424_DATA
+				DDRSS1_PHY_425_DATA
+				DDRSS1_PHY_426_DATA
+				DDRSS1_PHY_427_DATA
+				DDRSS1_PHY_428_DATA
+				DDRSS1_PHY_429_DATA
+				DDRSS1_PHY_430_DATA
+				DDRSS1_PHY_431_DATA
+				DDRSS1_PHY_432_DATA
+				DDRSS1_PHY_433_DATA
+				DDRSS1_PHY_434_DATA
+				DDRSS1_PHY_435_DATA
+				DDRSS1_PHY_436_DATA
+				DDRSS1_PHY_437_DATA
+				DDRSS1_PHY_438_DATA
+				DDRSS1_PHY_439_DATA
+				DDRSS1_PHY_440_DATA
+				DDRSS1_PHY_441_DATA
+				DDRSS1_PHY_442_DATA
+				DDRSS1_PHY_443_DATA
+				DDRSS1_PHY_444_DATA
+				DDRSS1_PHY_445_DATA
+				DDRSS1_PHY_446_DATA
+				DDRSS1_PHY_447_DATA
+				DDRSS1_PHY_448_DATA
+				DDRSS1_PHY_449_DATA
+				DDRSS1_PHY_450_DATA
+				DDRSS1_PHY_451_DATA
+				DDRSS1_PHY_452_DATA
+				DDRSS1_PHY_453_DATA
+				DDRSS1_PHY_454_DATA
+				DDRSS1_PHY_455_DATA
+				DDRSS1_PHY_456_DATA
+				DDRSS1_PHY_457_DATA
+				DDRSS1_PHY_458_DATA
+				DDRSS1_PHY_459_DATA
+				DDRSS1_PHY_460_DATA
+				DDRSS1_PHY_461_DATA
+				DDRSS1_PHY_462_DATA
+				DDRSS1_PHY_463_DATA
+				DDRSS1_PHY_464_DATA
+				DDRSS1_PHY_465_DATA
+				DDRSS1_PHY_466_DATA
+				DDRSS1_PHY_467_DATA
+				DDRSS1_PHY_468_DATA
+				DDRSS1_PHY_469_DATA
+				DDRSS1_PHY_470_DATA
+				DDRSS1_PHY_471_DATA
+				DDRSS1_PHY_472_DATA
+				DDRSS1_PHY_473_DATA
+				DDRSS1_PHY_474_DATA
+				DDRSS1_PHY_475_DATA
+				DDRSS1_PHY_476_DATA
+				DDRSS1_PHY_477_DATA
+				DDRSS1_PHY_478_DATA
+				DDRSS1_PHY_479_DATA
+				DDRSS1_PHY_480_DATA
+				DDRSS1_PHY_481_DATA
+				DDRSS1_PHY_482_DATA
+				DDRSS1_PHY_483_DATA
+				DDRSS1_PHY_484_DATA
+				DDRSS1_PHY_485_DATA
+				DDRSS1_PHY_486_DATA
+				DDRSS1_PHY_487_DATA
+				DDRSS1_PHY_488_DATA
+				DDRSS1_PHY_489_DATA
+				DDRSS1_PHY_490_DATA
+				DDRSS1_PHY_491_DATA
+				DDRSS1_PHY_492_DATA
+				DDRSS1_PHY_493_DATA
+				DDRSS1_PHY_494_DATA
+				DDRSS1_PHY_495_DATA
+				DDRSS1_PHY_496_DATA
+				DDRSS1_PHY_497_DATA
+				DDRSS1_PHY_498_DATA
+				DDRSS1_PHY_499_DATA
+				DDRSS1_PHY_500_DATA
+				DDRSS1_PHY_501_DATA
+				DDRSS1_PHY_502_DATA
+				DDRSS1_PHY_503_DATA
+				DDRSS1_PHY_504_DATA
+				DDRSS1_PHY_505_DATA
+				DDRSS1_PHY_506_DATA
+				DDRSS1_PHY_507_DATA
+				DDRSS1_PHY_508_DATA
+				DDRSS1_PHY_509_DATA
+				DDRSS1_PHY_510_DATA
+				DDRSS1_PHY_511_DATA
+				DDRSS1_PHY_512_DATA
+				DDRSS1_PHY_513_DATA
+				DDRSS1_PHY_514_DATA
+				DDRSS1_PHY_515_DATA
+				DDRSS1_PHY_516_DATA
+				DDRSS1_PHY_517_DATA
+				DDRSS1_PHY_518_DATA
+				DDRSS1_PHY_519_DATA
+				DDRSS1_PHY_520_DATA
+				DDRSS1_PHY_521_DATA
+				DDRSS1_PHY_522_DATA
+				DDRSS1_PHY_523_DATA
+				DDRSS1_PHY_524_DATA
+				DDRSS1_PHY_525_DATA
+				DDRSS1_PHY_526_DATA
+				DDRSS1_PHY_527_DATA
+				DDRSS1_PHY_528_DATA
+				DDRSS1_PHY_529_DATA
+				DDRSS1_PHY_530_DATA
+				DDRSS1_PHY_531_DATA
+				DDRSS1_PHY_532_DATA
+				DDRSS1_PHY_533_DATA
+				DDRSS1_PHY_534_DATA
+				DDRSS1_PHY_535_DATA
+				DDRSS1_PHY_536_DATA
+				DDRSS1_PHY_537_DATA
+				DDRSS1_PHY_538_DATA
+				DDRSS1_PHY_539_DATA
+				DDRSS1_PHY_540_DATA
+				DDRSS1_PHY_541_DATA
+				DDRSS1_PHY_542_DATA
+				DDRSS1_PHY_543_DATA
+				DDRSS1_PHY_544_DATA
+				DDRSS1_PHY_545_DATA
+				DDRSS1_PHY_546_DATA
+				DDRSS1_PHY_547_DATA
+				DDRSS1_PHY_548_DATA
+				DDRSS1_PHY_549_DATA
+				DDRSS1_PHY_550_DATA
+				DDRSS1_PHY_551_DATA
+				DDRSS1_PHY_552_DATA
+				DDRSS1_PHY_553_DATA
+				DDRSS1_PHY_554_DATA
+				DDRSS1_PHY_555_DATA
+				DDRSS1_PHY_556_DATA
+				DDRSS1_PHY_557_DATA
+				DDRSS1_PHY_558_DATA
+				DDRSS1_PHY_559_DATA
+				DDRSS1_PHY_560_DATA
+				DDRSS1_PHY_561_DATA
+				DDRSS1_PHY_562_DATA
+				DDRSS1_PHY_563_DATA
+				DDRSS1_PHY_564_DATA
+				DDRSS1_PHY_565_DATA
+				DDRSS1_PHY_566_DATA
+				DDRSS1_PHY_567_DATA
+				DDRSS1_PHY_568_DATA
+				DDRSS1_PHY_569_DATA
+				DDRSS1_PHY_570_DATA
+				DDRSS1_PHY_571_DATA
+				DDRSS1_PHY_572_DATA
+				DDRSS1_PHY_573_DATA
+				DDRSS1_PHY_574_DATA
+				DDRSS1_PHY_575_DATA
+				DDRSS1_PHY_576_DATA
+				DDRSS1_PHY_577_DATA
+				DDRSS1_PHY_578_DATA
+				DDRSS1_PHY_579_DATA
+				DDRSS1_PHY_580_DATA
+				DDRSS1_PHY_581_DATA
+				DDRSS1_PHY_582_DATA
+				DDRSS1_PHY_583_DATA
+				DDRSS1_PHY_584_DATA
+				DDRSS1_PHY_585_DATA
+				DDRSS1_PHY_586_DATA
+				DDRSS1_PHY_587_DATA
+				DDRSS1_PHY_588_DATA
+				DDRSS1_PHY_589_DATA
+				DDRSS1_PHY_590_DATA
+				DDRSS1_PHY_591_DATA
+				DDRSS1_PHY_592_DATA
+				DDRSS1_PHY_593_DATA
+				DDRSS1_PHY_594_DATA
+				DDRSS1_PHY_595_DATA
+				DDRSS1_PHY_596_DATA
+				DDRSS1_PHY_597_DATA
+				DDRSS1_PHY_598_DATA
+				DDRSS1_PHY_599_DATA
+				DDRSS1_PHY_600_DATA
+				DDRSS1_PHY_601_DATA
+				DDRSS1_PHY_602_DATA
+				DDRSS1_PHY_603_DATA
+				DDRSS1_PHY_604_DATA
+				DDRSS1_PHY_605_DATA
+				DDRSS1_PHY_606_DATA
+				DDRSS1_PHY_607_DATA
+				DDRSS1_PHY_608_DATA
+				DDRSS1_PHY_609_DATA
+				DDRSS1_PHY_610_DATA
+				DDRSS1_PHY_611_DATA
+				DDRSS1_PHY_612_DATA
+				DDRSS1_PHY_613_DATA
+				DDRSS1_PHY_614_DATA
+				DDRSS1_PHY_615_DATA
+				DDRSS1_PHY_616_DATA
+				DDRSS1_PHY_617_DATA
+				DDRSS1_PHY_618_DATA
+				DDRSS1_PHY_619_DATA
+				DDRSS1_PHY_620_DATA
+				DDRSS1_PHY_621_DATA
+				DDRSS1_PHY_622_DATA
+				DDRSS1_PHY_623_DATA
+				DDRSS1_PHY_624_DATA
+				DDRSS1_PHY_625_DATA
+				DDRSS1_PHY_626_DATA
+				DDRSS1_PHY_627_DATA
+				DDRSS1_PHY_628_DATA
+				DDRSS1_PHY_629_DATA
+				DDRSS1_PHY_630_DATA
+				DDRSS1_PHY_631_DATA
+				DDRSS1_PHY_632_DATA
+				DDRSS1_PHY_633_DATA
+				DDRSS1_PHY_634_DATA
+				DDRSS1_PHY_635_DATA
+				DDRSS1_PHY_636_DATA
+				DDRSS1_PHY_637_DATA
+				DDRSS1_PHY_638_DATA
+				DDRSS1_PHY_639_DATA
+				DDRSS1_PHY_640_DATA
+				DDRSS1_PHY_641_DATA
+				DDRSS1_PHY_642_DATA
+				DDRSS1_PHY_643_DATA
+				DDRSS1_PHY_644_DATA
+				DDRSS1_PHY_645_DATA
+				DDRSS1_PHY_646_DATA
+				DDRSS1_PHY_647_DATA
+				DDRSS1_PHY_648_DATA
+				DDRSS1_PHY_649_DATA
+				DDRSS1_PHY_650_DATA
+				DDRSS1_PHY_651_DATA
+				DDRSS1_PHY_652_DATA
+				DDRSS1_PHY_653_DATA
+				DDRSS1_PHY_654_DATA
+				DDRSS1_PHY_655_DATA
+				DDRSS1_PHY_656_DATA
+				DDRSS1_PHY_657_DATA
+				DDRSS1_PHY_658_DATA
+				DDRSS1_PHY_659_DATA
+				DDRSS1_PHY_660_DATA
+				DDRSS1_PHY_661_DATA
+				DDRSS1_PHY_662_DATA
+				DDRSS1_PHY_663_DATA
+				DDRSS1_PHY_664_DATA
+				DDRSS1_PHY_665_DATA
+				DDRSS1_PHY_666_DATA
+				DDRSS1_PHY_667_DATA
+				DDRSS1_PHY_668_DATA
+				DDRSS1_PHY_669_DATA
+				DDRSS1_PHY_670_DATA
+				DDRSS1_PHY_671_DATA
+				DDRSS1_PHY_672_DATA
+				DDRSS1_PHY_673_DATA
+				DDRSS1_PHY_674_DATA
+				DDRSS1_PHY_675_DATA
+				DDRSS1_PHY_676_DATA
+				DDRSS1_PHY_677_DATA
+				DDRSS1_PHY_678_DATA
+				DDRSS1_PHY_679_DATA
+				DDRSS1_PHY_680_DATA
+				DDRSS1_PHY_681_DATA
+				DDRSS1_PHY_682_DATA
+				DDRSS1_PHY_683_DATA
+				DDRSS1_PHY_684_DATA
+				DDRSS1_PHY_685_DATA
+				DDRSS1_PHY_686_DATA
+				DDRSS1_PHY_687_DATA
+				DDRSS1_PHY_688_DATA
+				DDRSS1_PHY_689_DATA
+				DDRSS1_PHY_690_DATA
+				DDRSS1_PHY_691_DATA
+				DDRSS1_PHY_692_DATA
+				DDRSS1_PHY_693_DATA
+				DDRSS1_PHY_694_DATA
+				DDRSS1_PHY_695_DATA
+				DDRSS1_PHY_696_DATA
+				DDRSS1_PHY_697_DATA
+				DDRSS1_PHY_698_DATA
+				DDRSS1_PHY_699_DATA
+				DDRSS1_PHY_700_DATA
+				DDRSS1_PHY_701_DATA
+				DDRSS1_PHY_702_DATA
+				DDRSS1_PHY_703_DATA
+				DDRSS1_PHY_704_DATA
+				DDRSS1_PHY_705_DATA
+				DDRSS1_PHY_706_DATA
+				DDRSS1_PHY_707_DATA
+				DDRSS1_PHY_708_DATA
+				DDRSS1_PHY_709_DATA
+				DDRSS1_PHY_710_DATA
+				DDRSS1_PHY_711_DATA
+				DDRSS1_PHY_712_DATA
+				DDRSS1_PHY_713_DATA
+				DDRSS1_PHY_714_DATA
+				DDRSS1_PHY_715_DATA
+				DDRSS1_PHY_716_DATA
+				DDRSS1_PHY_717_DATA
+				DDRSS1_PHY_718_DATA
+				DDRSS1_PHY_719_DATA
+				DDRSS1_PHY_720_DATA
+				DDRSS1_PHY_721_DATA
+				DDRSS1_PHY_722_DATA
+				DDRSS1_PHY_723_DATA
+				DDRSS1_PHY_724_DATA
+				DDRSS1_PHY_725_DATA
+				DDRSS1_PHY_726_DATA
+				DDRSS1_PHY_727_DATA
+				DDRSS1_PHY_728_DATA
+				DDRSS1_PHY_729_DATA
+				DDRSS1_PHY_730_DATA
+				DDRSS1_PHY_731_DATA
+				DDRSS1_PHY_732_DATA
+				DDRSS1_PHY_733_DATA
+				DDRSS1_PHY_734_DATA
+				DDRSS1_PHY_735_DATA
+				DDRSS1_PHY_736_DATA
+				DDRSS1_PHY_737_DATA
+				DDRSS1_PHY_738_DATA
+				DDRSS1_PHY_739_DATA
+				DDRSS1_PHY_740_DATA
+				DDRSS1_PHY_741_DATA
+				DDRSS1_PHY_742_DATA
+				DDRSS1_PHY_743_DATA
+				DDRSS1_PHY_744_DATA
+				DDRSS1_PHY_745_DATA
+				DDRSS1_PHY_746_DATA
+				DDRSS1_PHY_747_DATA
+				DDRSS1_PHY_748_DATA
+				DDRSS1_PHY_749_DATA
+				DDRSS1_PHY_750_DATA
+				DDRSS1_PHY_751_DATA
+				DDRSS1_PHY_752_DATA
+				DDRSS1_PHY_753_DATA
+				DDRSS1_PHY_754_DATA
+				DDRSS1_PHY_755_DATA
+				DDRSS1_PHY_756_DATA
+				DDRSS1_PHY_757_DATA
+				DDRSS1_PHY_758_DATA
+				DDRSS1_PHY_759_DATA
+				DDRSS1_PHY_760_DATA
+				DDRSS1_PHY_761_DATA
+				DDRSS1_PHY_762_DATA
+				DDRSS1_PHY_763_DATA
+				DDRSS1_PHY_764_DATA
+				DDRSS1_PHY_765_DATA
+				DDRSS1_PHY_766_DATA
+				DDRSS1_PHY_767_DATA
+				DDRSS1_PHY_768_DATA
+				DDRSS1_PHY_769_DATA
+				DDRSS1_PHY_770_DATA
+				DDRSS1_PHY_771_DATA
+				DDRSS1_PHY_772_DATA
+				DDRSS1_PHY_773_DATA
+				DDRSS1_PHY_774_DATA
+				DDRSS1_PHY_775_DATA
+				DDRSS1_PHY_776_DATA
+				DDRSS1_PHY_777_DATA
+				DDRSS1_PHY_778_DATA
+				DDRSS1_PHY_779_DATA
+				DDRSS1_PHY_780_DATA
+				DDRSS1_PHY_781_DATA
+				DDRSS1_PHY_782_DATA
+				DDRSS1_PHY_783_DATA
+				DDRSS1_PHY_784_DATA
+				DDRSS1_PHY_785_DATA
+				DDRSS1_PHY_786_DATA
+				DDRSS1_PHY_787_DATA
+				DDRSS1_PHY_788_DATA
+				DDRSS1_PHY_789_DATA
+				DDRSS1_PHY_790_DATA
+				DDRSS1_PHY_791_DATA
+				DDRSS1_PHY_792_DATA
+				DDRSS1_PHY_793_DATA
+				DDRSS1_PHY_794_DATA
+				DDRSS1_PHY_795_DATA
+				DDRSS1_PHY_796_DATA
+				DDRSS1_PHY_797_DATA
+				DDRSS1_PHY_798_DATA
+				DDRSS1_PHY_799_DATA
+				DDRSS1_PHY_800_DATA
+				DDRSS1_PHY_801_DATA
+				DDRSS1_PHY_802_DATA
+				DDRSS1_PHY_803_DATA
+				DDRSS1_PHY_804_DATA
+				DDRSS1_PHY_805_DATA
+				DDRSS1_PHY_806_DATA
+				DDRSS1_PHY_807_DATA
+				DDRSS1_PHY_808_DATA
+				DDRSS1_PHY_809_DATA
+				DDRSS1_PHY_810_DATA
+				DDRSS1_PHY_811_DATA
+				DDRSS1_PHY_812_DATA
+				DDRSS1_PHY_813_DATA
+				DDRSS1_PHY_814_DATA
+				DDRSS1_PHY_815_DATA
+				DDRSS1_PHY_816_DATA
+				DDRSS1_PHY_817_DATA
+				DDRSS1_PHY_818_DATA
+				DDRSS1_PHY_819_DATA
+				DDRSS1_PHY_820_DATA
+				DDRSS1_PHY_821_DATA
+				DDRSS1_PHY_822_DATA
+				DDRSS1_PHY_823_DATA
+				DDRSS1_PHY_824_DATA
+				DDRSS1_PHY_825_DATA
+				DDRSS1_PHY_826_DATA
+				DDRSS1_PHY_827_DATA
+				DDRSS1_PHY_828_DATA
+				DDRSS1_PHY_829_DATA
+				DDRSS1_PHY_830_DATA
+				DDRSS1_PHY_831_DATA
+				DDRSS1_PHY_832_DATA
+				DDRSS1_PHY_833_DATA
+				DDRSS1_PHY_834_DATA
+				DDRSS1_PHY_835_DATA
+				DDRSS1_PHY_836_DATA
+				DDRSS1_PHY_837_DATA
+				DDRSS1_PHY_838_DATA
+				DDRSS1_PHY_839_DATA
+				DDRSS1_PHY_840_DATA
+				DDRSS1_PHY_841_DATA
+				DDRSS1_PHY_842_DATA
+				DDRSS1_PHY_843_DATA
+				DDRSS1_PHY_844_DATA
+				DDRSS1_PHY_845_DATA
+				DDRSS1_PHY_846_DATA
+				DDRSS1_PHY_847_DATA
+				DDRSS1_PHY_848_DATA
+				DDRSS1_PHY_849_DATA
+				DDRSS1_PHY_850_DATA
+				DDRSS1_PHY_851_DATA
+				DDRSS1_PHY_852_DATA
+				DDRSS1_PHY_853_DATA
+				DDRSS1_PHY_854_DATA
+				DDRSS1_PHY_855_DATA
+				DDRSS1_PHY_856_DATA
+				DDRSS1_PHY_857_DATA
+				DDRSS1_PHY_858_DATA
+				DDRSS1_PHY_859_DATA
+				DDRSS1_PHY_860_DATA
+				DDRSS1_PHY_861_DATA
+				DDRSS1_PHY_862_DATA
+				DDRSS1_PHY_863_DATA
+				DDRSS1_PHY_864_DATA
+				DDRSS1_PHY_865_DATA
+				DDRSS1_PHY_866_DATA
+				DDRSS1_PHY_867_DATA
+				DDRSS1_PHY_868_DATA
+				DDRSS1_PHY_869_DATA
+				DDRSS1_PHY_870_DATA
+				DDRSS1_PHY_871_DATA
+				DDRSS1_PHY_872_DATA
+				DDRSS1_PHY_873_DATA
+				DDRSS1_PHY_874_DATA
+				DDRSS1_PHY_875_DATA
+				DDRSS1_PHY_876_DATA
+				DDRSS1_PHY_877_DATA
+				DDRSS1_PHY_878_DATA
+				DDRSS1_PHY_879_DATA
+				DDRSS1_PHY_880_DATA
+				DDRSS1_PHY_881_DATA
+				DDRSS1_PHY_882_DATA
+				DDRSS1_PHY_883_DATA
+				DDRSS1_PHY_884_DATA
+				DDRSS1_PHY_885_DATA
+				DDRSS1_PHY_886_DATA
+				DDRSS1_PHY_887_DATA
+				DDRSS1_PHY_888_DATA
+				DDRSS1_PHY_889_DATA
+				DDRSS1_PHY_890_DATA
+				DDRSS1_PHY_891_DATA
+				DDRSS1_PHY_892_DATA
+				DDRSS1_PHY_893_DATA
+				DDRSS1_PHY_894_DATA
+				DDRSS1_PHY_895_DATA
+				DDRSS1_PHY_896_DATA
+				DDRSS1_PHY_897_DATA
+				DDRSS1_PHY_898_DATA
+				DDRSS1_PHY_899_DATA
+				DDRSS1_PHY_900_DATA
+				DDRSS1_PHY_901_DATA
+				DDRSS1_PHY_902_DATA
+				DDRSS1_PHY_903_DATA
+				DDRSS1_PHY_904_DATA
+				DDRSS1_PHY_905_DATA
+				DDRSS1_PHY_906_DATA
+				DDRSS1_PHY_907_DATA
+				DDRSS1_PHY_908_DATA
+				DDRSS1_PHY_909_DATA
+				DDRSS1_PHY_910_DATA
+				DDRSS1_PHY_911_DATA
+				DDRSS1_PHY_912_DATA
+				DDRSS1_PHY_913_DATA
+				DDRSS1_PHY_914_DATA
+				DDRSS1_PHY_915_DATA
+				DDRSS1_PHY_916_DATA
+				DDRSS1_PHY_917_DATA
+				DDRSS1_PHY_918_DATA
+				DDRSS1_PHY_919_DATA
+				DDRSS1_PHY_920_DATA
+				DDRSS1_PHY_921_DATA
+				DDRSS1_PHY_922_DATA
+				DDRSS1_PHY_923_DATA
+				DDRSS1_PHY_924_DATA
+				DDRSS1_PHY_925_DATA
+				DDRSS1_PHY_926_DATA
+				DDRSS1_PHY_927_DATA
+				DDRSS1_PHY_928_DATA
+				DDRSS1_PHY_929_DATA
+				DDRSS1_PHY_930_DATA
+				DDRSS1_PHY_931_DATA
+				DDRSS1_PHY_932_DATA
+				DDRSS1_PHY_933_DATA
+				DDRSS1_PHY_934_DATA
+				DDRSS1_PHY_935_DATA
+				DDRSS1_PHY_936_DATA
+				DDRSS1_PHY_937_DATA
+				DDRSS1_PHY_938_DATA
+				DDRSS1_PHY_939_DATA
+				DDRSS1_PHY_940_DATA
+				DDRSS1_PHY_941_DATA
+				DDRSS1_PHY_942_DATA
+				DDRSS1_PHY_943_DATA
+				DDRSS1_PHY_944_DATA
+				DDRSS1_PHY_945_DATA
+				DDRSS1_PHY_946_DATA
+				DDRSS1_PHY_947_DATA
+				DDRSS1_PHY_948_DATA
+				DDRSS1_PHY_949_DATA
+				DDRSS1_PHY_950_DATA
+				DDRSS1_PHY_951_DATA
+				DDRSS1_PHY_952_DATA
+				DDRSS1_PHY_953_DATA
+				DDRSS1_PHY_954_DATA
+				DDRSS1_PHY_955_DATA
+				DDRSS1_PHY_956_DATA
+				DDRSS1_PHY_957_DATA
+				DDRSS1_PHY_958_DATA
+				DDRSS1_PHY_959_DATA
+				DDRSS1_PHY_960_DATA
+				DDRSS1_PHY_961_DATA
+				DDRSS1_PHY_962_DATA
+				DDRSS1_PHY_963_DATA
+				DDRSS1_PHY_964_DATA
+				DDRSS1_PHY_965_DATA
+				DDRSS1_PHY_966_DATA
+				DDRSS1_PHY_967_DATA
+				DDRSS1_PHY_968_DATA
+				DDRSS1_PHY_969_DATA
+				DDRSS1_PHY_970_DATA
+				DDRSS1_PHY_971_DATA
+				DDRSS1_PHY_972_DATA
+				DDRSS1_PHY_973_DATA
+				DDRSS1_PHY_974_DATA
+				DDRSS1_PHY_975_DATA
+				DDRSS1_PHY_976_DATA
+				DDRSS1_PHY_977_DATA
+				DDRSS1_PHY_978_DATA
+				DDRSS1_PHY_979_DATA
+				DDRSS1_PHY_980_DATA
+				DDRSS1_PHY_981_DATA
+				DDRSS1_PHY_982_DATA
+				DDRSS1_PHY_983_DATA
+				DDRSS1_PHY_984_DATA
+				DDRSS1_PHY_985_DATA
+				DDRSS1_PHY_986_DATA
+				DDRSS1_PHY_987_DATA
+				DDRSS1_PHY_988_DATA
+				DDRSS1_PHY_989_DATA
+				DDRSS1_PHY_990_DATA
+				DDRSS1_PHY_991_DATA
+				DDRSS1_PHY_992_DATA
+				DDRSS1_PHY_993_DATA
+				DDRSS1_PHY_994_DATA
+				DDRSS1_PHY_995_DATA
+				DDRSS1_PHY_996_DATA
+				DDRSS1_PHY_997_DATA
+				DDRSS1_PHY_998_DATA
+				DDRSS1_PHY_999_DATA
+				DDRSS1_PHY_1000_DATA
+				DDRSS1_PHY_1001_DATA
+				DDRSS1_PHY_1002_DATA
+				DDRSS1_PHY_1003_DATA
+				DDRSS1_PHY_1004_DATA
+				DDRSS1_PHY_1005_DATA
+				DDRSS1_PHY_1006_DATA
+				DDRSS1_PHY_1007_DATA
+				DDRSS1_PHY_1008_DATA
+				DDRSS1_PHY_1009_DATA
+				DDRSS1_PHY_1010_DATA
+				DDRSS1_PHY_1011_DATA
+				DDRSS1_PHY_1012_DATA
+				DDRSS1_PHY_1013_DATA
+				DDRSS1_PHY_1014_DATA
+				DDRSS1_PHY_1015_DATA
+				DDRSS1_PHY_1016_DATA
+				DDRSS1_PHY_1017_DATA
+				DDRSS1_PHY_1018_DATA
+				DDRSS1_PHY_1019_DATA
+				DDRSS1_PHY_1020_DATA
+				DDRSS1_PHY_1021_DATA
+				DDRSS1_PHY_1022_DATA
+				DDRSS1_PHY_1023_DATA
+				DDRSS1_PHY_1024_DATA
+				DDRSS1_PHY_1025_DATA
+				DDRSS1_PHY_1026_DATA
+				DDRSS1_PHY_1027_DATA
+				DDRSS1_PHY_1028_DATA
+				DDRSS1_PHY_1029_DATA
+				DDRSS1_PHY_1030_DATA
+				DDRSS1_PHY_1031_DATA
+				DDRSS1_PHY_1032_DATA
+				DDRSS1_PHY_1033_DATA
+				DDRSS1_PHY_1034_DATA
+				DDRSS1_PHY_1035_DATA
+				DDRSS1_PHY_1036_DATA
+				DDRSS1_PHY_1037_DATA
+				DDRSS1_PHY_1038_DATA
+				DDRSS1_PHY_1039_DATA
+				DDRSS1_PHY_1040_DATA
+				DDRSS1_PHY_1041_DATA
+				DDRSS1_PHY_1042_DATA
+				DDRSS1_PHY_1043_DATA
+				DDRSS1_PHY_1044_DATA
+				DDRSS1_PHY_1045_DATA
+				DDRSS1_PHY_1046_DATA
+				DDRSS1_PHY_1047_DATA
+				DDRSS1_PHY_1048_DATA
+				DDRSS1_PHY_1049_DATA
+				DDRSS1_PHY_1050_DATA
+				DDRSS1_PHY_1051_DATA
+				DDRSS1_PHY_1052_DATA
+				DDRSS1_PHY_1053_DATA
+				DDRSS1_PHY_1054_DATA
+				DDRSS1_PHY_1055_DATA
+				DDRSS1_PHY_1056_DATA
+				DDRSS1_PHY_1057_DATA
+				DDRSS1_PHY_1058_DATA
+				DDRSS1_PHY_1059_DATA
+				DDRSS1_PHY_1060_DATA
+				DDRSS1_PHY_1061_DATA
+				DDRSS1_PHY_1062_DATA
+				DDRSS1_PHY_1063_DATA
+				DDRSS1_PHY_1064_DATA
+				DDRSS1_PHY_1065_DATA
+				DDRSS1_PHY_1066_DATA
+				DDRSS1_PHY_1067_DATA
+				DDRSS1_PHY_1068_DATA
+				DDRSS1_PHY_1069_DATA
+				DDRSS1_PHY_1070_DATA
+				DDRSS1_PHY_1071_DATA
+				DDRSS1_PHY_1072_DATA
+				DDRSS1_PHY_1073_DATA
+				DDRSS1_PHY_1074_DATA
+				DDRSS1_PHY_1075_DATA
+				DDRSS1_PHY_1076_DATA
+				DDRSS1_PHY_1077_DATA
+				DDRSS1_PHY_1078_DATA
+				DDRSS1_PHY_1079_DATA
+				DDRSS1_PHY_1080_DATA
+				DDRSS1_PHY_1081_DATA
+				DDRSS1_PHY_1082_DATA
+				DDRSS1_PHY_1083_DATA
+				DDRSS1_PHY_1084_DATA
+				DDRSS1_PHY_1085_DATA
+				DDRSS1_PHY_1086_DATA
+				DDRSS1_PHY_1087_DATA
+				DDRSS1_PHY_1088_DATA
+				DDRSS1_PHY_1089_DATA
+				DDRSS1_PHY_1090_DATA
+				DDRSS1_PHY_1091_DATA
+				DDRSS1_PHY_1092_DATA
+				DDRSS1_PHY_1093_DATA
+				DDRSS1_PHY_1094_DATA
+				DDRSS1_PHY_1095_DATA
+				DDRSS1_PHY_1096_DATA
+				DDRSS1_PHY_1097_DATA
+				DDRSS1_PHY_1098_DATA
+				DDRSS1_PHY_1099_DATA
+				DDRSS1_PHY_1100_DATA
+				DDRSS1_PHY_1101_DATA
+				DDRSS1_PHY_1102_DATA
+				DDRSS1_PHY_1103_DATA
+				DDRSS1_PHY_1104_DATA
+				DDRSS1_PHY_1105_DATA
+				DDRSS1_PHY_1106_DATA
+				DDRSS1_PHY_1107_DATA
+				DDRSS1_PHY_1108_DATA
+				DDRSS1_PHY_1109_DATA
+				DDRSS1_PHY_1110_DATA
+				DDRSS1_PHY_1111_DATA
+				DDRSS1_PHY_1112_DATA
+				DDRSS1_PHY_1113_DATA
+				DDRSS1_PHY_1114_DATA
+				DDRSS1_PHY_1115_DATA
+				DDRSS1_PHY_1116_DATA
+				DDRSS1_PHY_1117_DATA
+				DDRSS1_PHY_1118_DATA
+				DDRSS1_PHY_1119_DATA
+				DDRSS1_PHY_1120_DATA
+				DDRSS1_PHY_1121_DATA
+				DDRSS1_PHY_1122_DATA
+				DDRSS1_PHY_1123_DATA
+				DDRSS1_PHY_1124_DATA
+				DDRSS1_PHY_1125_DATA
+				DDRSS1_PHY_1126_DATA
+				DDRSS1_PHY_1127_DATA
+				DDRSS1_PHY_1128_DATA
+				DDRSS1_PHY_1129_DATA
+				DDRSS1_PHY_1130_DATA
+				DDRSS1_PHY_1131_DATA
+				DDRSS1_PHY_1132_DATA
+				DDRSS1_PHY_1133_DATA
+				DDRSS1_PHY_1134_DATA
+				DDRSS1_PHY_1135_DATA
+				DDRSS1_PHY_1136_DATA
+				DDRSS1_PHY_1137_DATA
+				DDRSS1_PHY_1138_DATA
+				DDRSS1_PHY_1139_DATA
+				DDRSS1_PHY_1140_DATA
+				DDRSS1_PHY_1141_DATA
+				DDRSS1_PHY_1142_DATA
+				DDRSS1_PHY_1143_DATA
+				DDRSS1_PHY_1144_DATA
+				DDRSS1_PHY_1145_DATA
+				DDRSS1_PHY_1146_DATA
+				DDRSS1_PHY_1147_DATA
+				DDRSS1_PHY_1148_DATA
+				DDRSS1_PHY_1149_DATA
+				DDRSS1_PHY_1150_DATA
+				DDRSS1_PHY_1151_DATA
+				DDRSS1_PHY_1152_DATA
+				DDRSS1_PHY_1153_DATA
+				DDRSS1_PHY_1154_DATA
+				DDRSS1_PHY_1155_DATA
+				DDRSS1_PHY_1156_DATA
+				DDRSS1_PHY_1157_DATA
+				DDRSS1_PHY_1158_DATA
+				DDRSS1_PHY_1159_DATA
+				DDRSS1_PHY_1160_DATA
+				DDRSS1_PHY_1161_DATA
+				DDRSS1_PHY_1162_DATA
+				DDRSS1_PHY_1163_DATA
+				DDRSS1_PHY_1164_DATA
+				DDRSS1_PHY_1165_DATA
+				DDRSS1_PHY_1166_DATA
+				DDRSS1_PHY_1167_DATA
+				DDRSS1_PHY_1168_DATA
+				DDRSS1_PHY_1169_DATA
+				DDRSS1_PHY_1170_DATA
+				DDRSS1_PHY_1171_DATA
+				DDRSS1_PHY_1172_DATA
+				DDRSS1_PHY_1173_DATA
+				DDRSS1_PHY_1174_DATA
+				DDRSS1_PHY_1175_DATA
+				DDRSS1_PHY_1176_DATA
+				DDRSS1_PHY_1177_DATA
+				DDRSS1_PHY_1178_DATA
+				DDRSS1_PHY_1179_DATA
+				DDRSS1_PHY_1180_DATA
+				DDRSS1_PHY_1181_DATA
+				DDRSS1_PHY_1182_DATA
+				DDRSS1_PHY_1183_DATA
+				DDRSS1_PHY_1184_DATA
+				DDRSS1_PHY_1185_DATA
+				DDRSS1_PHY_1186_DATA
+				DDRSS1_PHY_1187_DATA
+				DDRSS1_PHY_1188_DATA
+				DDRSS1_PHY_1189_DATA
+				DDRSS1_PHY_1190_DATA
+				DDRSS1_PHY_1191_DATA
+				DDRSS1_PHY_1192_DATA
+				DDRSS1_PHY_1193_DATA
+				DDRSS1_PHY_1194_DATA
+				DDRSS1_PHY_1195_DATA
+				DDRSS1_PHY_1196_DATA
+				DDRSS1_PHY_1197_DATA
+				DDRSS1_PHY_1198_DATA
+				DDRSS1_PHY_1199_DATA
+				DDRSS1_PHY_1200_DATA
+				DDRSS1_PHY_1201_DATA
+				DDRSS1_PHY_1202_DATA
+				DDRSS1_PHY_1203_DATA
+				DDRSS1_PHY_1204_DATA
+				DDRSS1_PHY_1205_DATA
+				DDRSS1_PHY_1206_DATA
+				DDRSS1_PHY_1207_DATA
+				DDRSS1_PHY_1208_DATA
+				DDRSS1_PHY_1209_DATA
+				DDRSS1_PHY_1210_DATA
+				DDRSS1_PHY_1211_DATA
+				DDRSS1_PHY_1212_DATA
+				DDRSS1_PHY_1213_DATA
+				DDRSS1_PHY_1214_DATA
+				DDRSS1_PHY_1215_DATA
+				DDRSS1_PHY_1216_DATA
+				DDRSS1_PHY_1217_DATA
+				DDRSS1_PHY_1218_DATA
+				DDRSS1_PHY_1219_DATA
+				DDRSS1_PHY_1220_DATA
+				DDRSS1_PHY_1221_DATA
+				DDRSS1_PHY_1222_DATA
+				DDRSS1_PHY_1223_DATA
+				DDRSS1_PHY_1224_DATA
+				DDRSS1_PHY_1225_DATA
+				DDRSS1_PHY_1226_DATA
+				DDRSS1_PHY_1227_DATA
+				DDRSS1_PHY_1228_DATA
+				DDRSS1_PHY_1229_DATA
+				DDRSS1_PHY_1230_DATA
+				DDRSS1_PHY_1231_DATA
+				DDRSS1_PHY_1232_DATA
+				DDRSS1_PHY_1233_DATA
+				DDRSS1_PHY_1234_DATA
+				DDRSS1_PHY_1235_DATA
+				DDRSS1_PHY_1236_DATA
+				DDRSS1_PHY_1237_DATA
+				DDRSS1_PHY_1238_DATA
+				DDRSS1_PHY_1239_DATA
+				DDRSS1_PHY_1240_DATA
+				DDRSS1_PHY_1241_DATA
+				DDRSS1_PHY_1242_DATA
+				DDRSS1_PHY_1243_DATA
+				DDRSS1_PHY_1244_DATA
+				DDRSS1_PHY_1245_DATA
+				DDRSS1_PHY_1246_DATA
+				DDRSS1_PHY_1247_DATA
+				DDRSS1_PHY_1248_DATA
+				DDRSS1_PHY_1249_DATA
+				DDRSS1_PHY_1250_DATA
+				DDRSS1_PHY_1251_DATA
+				DDRSS1_PHY_1252_DATA
+				DDRSS1_PHY_1253_DATA
+				DDRSS1_PHY_1254_DATA
+				DDRSS1_PHY_1255_DATA
+				DDRSS1_PHY_1256_DATA
+				DDRSS1_PHY_1257_DATA
+				DDRSS1_PHY_1258_DATA
+				DDRSS1_PHY_1259_DATA
+				DDRSS1_PHY_1260_DATA
+				DDRSS1_PHY_1261_DATA
+				DDRSS1_PHY_1262_DATA
+				DDRSS1_PHY_1263_DATA
+				DDRSS1_PHY_1264_DATA
+				DDRSS1_PHY_1265_DATA
+				DDRSS1_PHY_1266_DATA
+				DDRSS1_PHY_1267_DATA
+				DDRSS1_PHY_1268_DATA
+				DDRSS1_PHY_1269_DATA
+				DDRSS1_PHY_1270_DATA
+				DDRSS1_PHY_1271_DATA
+				DDRSS1_PHY_1272_DATA
+				DDRSS1_PHY_1273_DATA
+				DDRSS1_PHY_1274_DATA
+				DDRSS1_PHY_1275_DATA
+				DDRSS1_PHY_1276_DATA
+				DDRSS1_PHY_1277_DATA
+				DDRSS1_PHY_1278_DATA
+				DDRSS1_PHY_1279_DATA
+				DDRSS1_PHY_1280_DATA
+				DDRSS1_PHY_1281_DATA
+				DDRSS1_PHY_1282_DATA
+				DDRSS1_PHY_1283_DATA
+				DDRSS1_PHY_1284_DATA
+				DDRSS1_PHY_1285_DATA
+				DDRSS1_PHY_1286_DATA
+				DDRSS1_PHY_1287_DATA
+				DDRSS1_PHY_1288_DATA
+				DDRSS1_PHY_1289_DATA
+				DDRSS1_PHY_1290_DATA
+				DDRSS1_PHY_1291_DATA
+				DDRSS1_PHY_1292_DATA
+				DDRSS1_PHY_1293_DATA
+				DDRSS1_PHY_1294_DATA
+				DDRSS1_PHY_1295_DATA
+				DDRSS1_PHY_1296_DATA
+				DDRSS1_PHY_1297_DATA
+				DDRSS1_PHY_1298_DATA
+				DDRSS1_PHY_1299_DATA
+				DDRSS1_PHY_1300_DATA
+				DDRSS1_PHY_1301_DATA
+				DDRSS1_PHY_1302_DATA
+				DDRSS1_PHY_1303_DATA
+				DDRSS1_PHY_1304_DATA
+				DDRSS1_PHY_1305_DATA
+				DDRSS1_PHY_1306_DATA
+				DDRSS1_PHY_1307_DATA
+				DDRSS1_PHY_1308_DATA
+				DDRSS1_PHY_1309_DATA
+				DDRSS1_PHY_1310_DATA
+				DDRSS1_PHY_1311_DATA
+				DDRSS1_PHY_1312_DATA
+				DDRSS1_PHY_1313_DATA
+				DDRSS1_PHY_1314_DATA
+				DDRSS1_PHY_1315_DATA
+				DDRSS1_PHY_1316_DATA
+				DDRSS1_PHY_1317_DATA
+				DDRSS1_PHY_1318_DATA
+				DDRSS1_PHY_1319_DATA
+				DDRSS1_PHY_1320_DATA
+				DDRSS1_PHY_1321_DATA
+				DDRSS1_PHY_1322_DATA
+				DDRSS1_PHY_1323_DATA
+				DDRSS1_PHY_1324_DATA
+				DDRSS1_PHY_1325_DATA
+				DDRSS1_PHY_1326_DATA
+				DDRSS1_PHY_1327_DATA
+				DDRSS1_PHY_1328_DATA
+				DDRSS1_PHY_1329_DATA
+				DDRSS1_PHY_1330_DATA
+				DDRSS1_PHY_1331_DATA
+				DDRSS1_PHY_1332_DATA
+				DDRSS1_PHY_1333_DATA
+				DDRSS1_PHY_1334_DATA
+				DDRSS1_PHY_1335_DATA
+				DDRSS1_PHY_1336_DATA
+				DDRSS1_PHY_1337_DATA
+				DDRSS1_PHY_1338_DATA
+				DDRSS1_PHY_1339_DATA
+				DDRSS1_PHY_1340_DATA
+				DDRSS1_PHY_1341_DATA
+				DDRSS1_PHY_1342_DATA
+				DDRSS1_PHY_1343_DATA
+				DDRSS1_PHY_1344_DATA
+				DDRSS1_PHY_1345_DATA
+				DDRSS1_PHY_1346_DATA
+				DDRSS1_PHY_1347_DATA
+				DDRSS1_PHY_1348_DATA
+				DDRSS1_PHY_1349_DATA
+				DDRSS1_PHY_1350_DATA
+				DDRSS1_PHY_1351_DATA
+				DDRSS1_PHY_1352_DATA
+				DDRSS1_PHY_1353_DATA
+				DDRSS1_PHY_1354_DATA
+				DDRSS1_PHY_1355_DATA
+				DDRSS1_PHY_1356_DATA
+				DDRSS1_PHY_1357_DATA
+				DDRSS1_PHY_1358_DATA
+				DDRSS1_PHY_1359_DATA
+				DDRSS1_PHY_1360_DATA
+				DDRSS1_PHY_1361_DATA
+				DDRSS1_PHY_1362_DATA
+				DDRSS1_PHY_1363_DATA
+				DDRSS1_PHY_1364_DATA
+				DDRSS1_PHY_1365_DATA
+				DDRSS1_PHY_1366_DATA
+				DDRSS1_PHY_1367_DATA
+				DDRSS1_PHY_1368_DATA
+				DDRSS1_PHY_1369_DATA
+				DDRSS1_PHY_1370_DATA
+				DDRSS1_PHY_1371_DATA
+				DDRSS1_PHY_1372_DATA
+				DDRSS1_PHY_1373_DATA
+				DDRSS1_PHY_1374_DATA
+				DDRSS1_PHY_1375_DATA
+				DDRSS1_PHY_1376_DATA
+				DDRSS1_PHY_1377_DATA
+				DDRSS1_PHY_1378_DATA
+				DDRSS1_PHY_1379_DATA
+				DDRSS1_PHY_1380_DATA
+				DDRSS1_PHY_1381_DATA
+				DDRSS1_PHY_1382_DATA
+				DDRSS1_PHY_1383_DATA
+				DDRSS1_PHY_1384_DATA
+				DDRSS1_PHY_1385_DATA
+				DDRSS1_PHY_1386_DATA
+				DDRSS1_PHY_1387_DATA
+				DDRSS1_PHY_1388_DATA
+				DDRSS1_PHY_1389_DATA
+				DDRSS1_PHY_1390_DATA
+				DDRSS1_PHY_1391_DATA
+				DDRSS1_PHY_1392_DATA
+				DDRSS1_PHY_1393_DATA
+				DDRSS1_PHY_1394_DATA
+				DDRSS1_PHY_1395_DATA
+				DDRSS1_PHY_1396_DATA
+				DDRSS1_PHY_1397_DATA
+				DDRSS1_PHY_1398_DATA
+				DDRSS1_PHY_1399_DATA
+				DDRSS1_PHY_1400_DATA
+				DDRSS1_PHY_1401_DATA
+				DDRSS1_PHY_1402_DATA
+				DDRSS1_PHY_1403_DATA
+				DDRSS1_PHY_1404_DATA
+				DDRSS1_PHY_1405_DATA
+				DDRSS1_PHY_1406_DATA
+				DDRSS1_PHY_1407_DATA
+				DDRSS1_PHY_1408_DATA
+				DDRSS1_PHY_1409_DATA
+				DDRSS1_PHY_1410_DATA
+				DDRSS1_PHY_1411_DATA
+				DDRSS1_PHY_1412_DATA
+				DDRSS1_PHY_1413_DATA
+				DDRSS1_PHY_1414_DATA
+				DDRSS1_PHY_1415_DATA
+				DDRSS1_PHY_1416_DATA
+				DDRSS1_PHY_1417_DATA
+				DDRSS1_PHY_1418_DATA
+				DDRSS1_PHY_1419_DATA
+				DDRSS1_PHY_1420_DATA
+				DDRSS1_PHY_1421_DATA
+				DDRSS1_PHY_1422_DATA
+			>;
+		};
+	};
+};
diff --git a/arch/arm/dts/mt7987-pinctrl.dtsi b/arch/arm/dts/mt7987-pinctrl.dtsi
index b5e643feffe..dfde21235b1 100644
--- a/arch/arm/dts/mt7987-pinctrl.dtsi
+++ b/arch/arm/dts/mt7987-pinctrl.dtsi
@@ -191,6 +191,20 @@
 		};
 	};
 
+	pwm_pins: pwm-pins {
+		mux {
+			/*
+			 * - pwm0   : PWM0@PIN13
+			 * - pwm1_0 : PWM1@PIN7  (share with JTAG)
+			 *   pwm1_1 : PWM1@PIN43 (share with i2c0)
+			 * - pwm2_0 : PWM2@PIN12 (share with PCM)
+			 *   pwm2_1 : PWM2@PIN44 (share with i2c0)
+			 */
+			function = "pwm";
+			groups = "pwm0";
+		};
+	};
+
 	uart1_pins: uart1-pins {
 		mux {
 			function = "uart";
diff --git a/arch/arm/dts/mt7987.dtsi b/arch/arm/dts/mt7987.dtsi
index fd1585f658d..4c1d597499c 100644
--- a/arch/arm/dts/mt7987.dtsi
+++ b/arch/arm/dts/mt7987.dtsi
@@ -389,21 +389,15 @@
 		};
 
 		pwm: pwm@10048000 {
-			compatible = "mediatek,mt7988-pwm";
+			compatible = "mediatek,mt7987-pwm";
 			reg = <0 0x10048000 0 0x1000>;
 			#pwm-cells = <2>;
 			clocks = <&infracfg CLK_INFRA_66M_PWM_BCK>,
 				 <&infracfg CLK_INFRA_66M_PWM_HCK>,
-				 <&clkxtal>,
-				 <&clkxtal>,
-				 <&clkxtal>,
-				 <&clkxtal>,
-				 <&clkxtal>,
-				 <&clkxtal>,
-				 <&clkxtal>,
-				 <&clkxtal>;
-			clock-names = "top", "main", "pwm1", "pwm2", "pwm3",
-				      "pwm4","pwm5","pwm6","pwm7","pwm8";
+				 <&infracfg CLK_INFRA_66M_PWM_HCK>,
+				 <&infracfg CLK_INFRA_66M_PWM_HCK>,
+				 <&infracfg CLK_INFRA_66M_PWM_HCK>;
+			clock-names = "top", "main", "pwm1", "pwm2", "pwm3";
 			status = "disabled";
 		};
 
diff --git a/arch/arm/dts/mt7987a-u-boot.dtsi b/arch/arm/dts/mt7987a-u-boot.dtsi
index ec0a6389d8b..a1cb42a9675 100644
--- a/arch/arm/dts/mt7987a-u-boot.dtsi
+++ b/arch/arm/dts/mt7987a-u-boot.dtsi
@@ -24,6 +24,10 @@
 			mediatek,hwver = <&hwver>;
 		};
 	};
+
+	reserved-memory {
+		/delete-node/ wmcpu-reserved@50000000;
+	};
 };
 
 &i2c0 {
diff --git a/arch/arm/dts/mt7987a.dtsi b/arch/arm/dts/mt7987a.dtsi
index 028f563fb39..365fefdbe17 100644
--- a/arch/arm/dts/mt7987a.dtsi
+++ b/arch/arm/dts/mt7987a.dtsi
@@ -29,7 +29,7 @@
 
 &fan {
 	pwms = <&pwm 0 50000 0>;
-	status = "okay";
+	status = "disabled";
 };
 
 &i2c0 {
@@ -59,6 +59,8 @@
 };
 
 &pwm {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pwm_pins>;
 	status = "okay";
 };
 
diff --git a/arch/arm/dts/nuvoton-common-npcm7xx.dtsi b/arch/arm/dts/nuvoton-common-npcm7xx.dtsi
index feb88872fc7..093d5427e30 100644
--- a/arch/arm/dts/nuvoton-common-npcm7xx.dtsi
+++ b/arch/arm/dts/nuvoton-common-npcm7xx.dtsi
@@ -95,6 +95,11 @@
 			compatible = "nuvoton,npcm750-rst", "syscon", "simple-mfd";
 			reg = <0x801000 0x6C>;
 		};
+
+		timer0: timer@f0801068 {
+			compatible = "nuvoton,npcm750-timer";
+			reg = <0x801068 0x8>;
+		};
 	};
 
 	ahb {
@@ -245,13 +250,6 @@
 				status = "disabled";
 			};
 
-			timer0: timer@8000 {
-				compatible = "nuvoton,npcm750-timer";
-				interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
-				reg = <0x8000 0x1C>;
-				clocks = <&clk NPCM7XX_CLK_TIMER>;
-			};
-
 			watchdog0: watchdog@801C {
 				compatible = "nuvoton,npcm750-wdt";
 				interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
diff --git a/arch/arm/dts/sam9x60.dtsi b/arch/arm/dts/sam9x60.dtsi
index 3b684fc63d5..60de9140226 100644
--- a/arch/arm/dts/sam9x60.dtsi
+++ b/arch/arm/dts/sam9x60.dtsi
@@ -17,6 +17,7 @@
 /{
 	model = "Microchip SAM9X60 SoC";
 	compatible = "microchip,sam9x60";
+	interrupt-parent = <&aic>;
 
 	aliases {
 		serial0 = &dbgu;
@@ -122,8 +123,6 @@
 			assigned-clock-rates = <100000000>;
 			assigned-clock-parents = <&pmc PMC_TYPE_CORE 10>; /* ID_PLL_A_DIV */
 			bus-width = <4>;
-			pinctrl-names = "default";
-			pinctrl-0 = <&pinctrl_sdhci0>;
 		};
 
 		sdhci1: sdhci-host@90000000 {
@@ -135,8 +134,6 @@
 			assigned-clock-rates = <100000000>;
 			assigned-clock-parents = <&pmc PMC_TYPE_CORE 10>; /* ID_PLL_A_DIV */
 			bus-width = <4>;
-			pinctrl-names = "default";
-			pinctrl-0 = <&pinctrl_sdhci1>;
 		};
 
 		apb {
@@ -176,8 +173,6 @@
 			macb0: ethernet@f802c000 {
 				compatible = "cdns,sam9x60-macb", "cdns,macb";
 				reg = <0xf802c000 0x100>;
-				pinctrl-names = "default";
-				pinctrl-0 = <&pinctrl_macb0_rmii>;
 				clock-names = "hclk", "pclk";
 				clocks = <&pmc PMC_TYPE_PERIPHERAL 24>, <&pmc PMC_TYPE_PERIPHERAL 24>;
 				status = "disabled";
@@ -199,11 +194,17 @@
 				reg = <0xffffea00 0x100>;
 			};
 
+			aic: interrupt-controller@fffff100 {
+				compatible = "microchip,sam9x60-aic";
+				#interrupt-cells = <3>;
+				interrupt-controller;
+				reg = <0xfffff100 0x100>;
+				atmel,external-irqs = <31>;
+			};
+
 			dbgu: serial@fffff200 {
 				compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart";
 				reg = <0xfffff200 0x200>;
-				pinctrl-names = "default";
-				pinctrl-0 = <&pinctrl_dbgu>;
 				clocks = <&pmc PMC_TYPE_PERIPHERAL 47>;
 				clock-names = "usart";
 			};
@@ -211,99 +212,63 @@
 			pinctrl: pinctrl@fffff400 {
 				#address-cells = <1>;
 				#size-cells = <1>;
-				compatible = "microchip,sam9x60-pinctrl", "simple-bus";
+				compatible = "microchip,sam9x60-pinctrl", "simple-mfd";
 				ranges = <0xfffff400 0xfffff400 0x800>;
-				reg = <0xfffff400 0x200		/* pioA */
-				       0xfffff600 0x200		/* pioB */
-				       0xfffff800 0x200		/* pioC */
-				       0xfffffa00 0x200>;	/* pioD */
-
-				/* shared pinctrl settings */
-				dbgu {
-					pinctrl_dbgu: dbgu-0 {
-						atmel,pins =
-							<AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_PULL_UP
-							 AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE>;
-					};
-				};
 
-				macb0 {
-					pinctrl_macb0_rmii: macb0_rmii-0 {
-						atmel,pins =
-							<AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB0 periph A */
-							 AT91_PIOB 1 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB1 periph A */
-							 AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB2 periph A */
-							 AT91_PIOB 3 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB3 periph A */
-							 AT91_PIOB 4 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB4 periph A */
-							 AT91_PIOB 5 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB5 periph A */
-							 AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB6 periph A */
-							 AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB7 periph A */
-							 AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB9 periph A */
-							 AT91_PIOB 10 AT91_PERIPH_A AT91_PINCTRL_NONE>;	/* PB10 periph A */
-					};
+				/* mux-mask corresponding to sam9x60 SoC in TFBGA228L package */
+				atmel,mux-mask = <
+						  /*     A       B       C       */
+						  0xffffffff 0xffe03fff 0xef00019d       /* pioA */
+						  0x03ffffff 0x02fc7e7f 0x00780000       /* pioB */
+						  0xffffffff 0xffffffff 0xf83fffff       /* pioC */
+						  0x003fffff 0x003f8000 0x00000000       /* pioD */
+						  >;
+
+				pioA: gpio@fffff400 {
+					compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
+					reg = <0xfffff400 0x200>;
+					interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
+					#gpio-cells = <2>;
+					gpio-controller;
+					interrupt-controller;
+					#interrupt-cells = <2>;
+					clocks = <&pmc PMC_TYPE_PERIPHERAL 2>;
 				};
 
-				sdhci0 {
-					pinctrl_sdhci0: sdhci0 {
-						atmel,pins =
-							<AT91_PIOA 17 AT91_PERIPH_A
-							 (AT91_PINCTRL_DRIVE_STRENGTH_HI | AT91_PINCTRL_SLEWRATE_ENA)	/* PA17 CK  periph A with pullup */
-							 AT91_PIOA 16 AT91_PERIPH_A
-							 (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI | AT91_PINCTRL_SLEWRATE_ENA)	/* PA16 CMD periph A with pullup */
-							 AT91_PIOA 15 AT91_PERIPH_A
-							 (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI | AT91_PINCTRL_SLEWRATE_ENA)	/* PA15 DAT0 periph A */
-							 AT91_PIOA 18 AT91_PERIPH_A
-							 (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI | AT91_PINCTRL_SLEWRATE_ENA)	/* PA18 DAT1 periph A with pullup */
-							 AT91_PIOA 19 AT91_PERIPH_A
-							 (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI | AT91_PINCTRL_SLEWRATE_ENA)	/* PA19 DAT2 periph A with pullup */
-							 AT91_PIOA 20 AT91_PERIPH_A
-							 (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI | AT91_PINCTRL_SLEWRATE_ENA)>;	/* PA20 DAT3 periph A with pullup */
-					};
+				pioB: gpio@fffff600 {
+					compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
+					reg = <0xfffff600 0x200>;
+					interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
+					#gpio-cells = <2>;
+					gpio-controller;
+					#gpio-lines = <26>;
+					interrupt-controller;
+					#interrupt-cells = <2>;
+					clocks = <&pmc PMC_TYPE_PERIPHERAL 3>;
 				};
 
-				sdhci1 {
-					pinctrl_sdhci1: sdhci1 {
-						atmel,pins =
-							<AT91_PIOA 13 AT91_PERIPH_B (AT91_PINCTRL_DRIVE_STRENGTH_HI)				/* PA13 CK periph B */
-							 AT91_PIOA 12 AT91_PERIPH_B (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI)	/* PA12 CMD periph B with pullup */
-							 AT91_PIOA 11 AT91_PERIPH_B (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI)	/* PA11 DAT0 periph B with pullup */
-							 AT91_PIOA  2 AT91_PERIPH_B (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI)	/* PA2 DAT1 periph B with pullup */
-							 AT91_PIOA  3 AT91_PERIPH_B (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI)	/* PA3 DAT2 periph B with pullup */
-							 AT91_PIOA  4 AT91_PERIPH_B (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI)>;	/* PA4 DAT3 periph B with pullup */
-					};
+				pioC: gpio@fffff800 {
+					compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
+					reg = <0xfffff800 0x200>;
+					interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>;
+					#gpio-cells = <2>;
+					gpio-controller;
+					interrupt-controller;
+					#interrupt-cells = <2>;
+					clocks = <&pmc PMC_TYPE_PERIPHERAL 4>;
 				};
-			};
-
-			pioA: gpio@fffff400 {
-				compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
-				reg = <0xfffff400 0x200>;
-				#gpio-cells = <2>;
-				gpio-controller;
-				clocks = <&pmc PMC_TYPE_PERIPHERAL 2>;
-			};
 
-			pioB: gpio@fffff600 {
-				compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
-				reg = <0xfffff600 0x200>;
-				#gpio-cells = <2>;
-				gpio-controller;
-				clocks = <&pmc PMC_TYPE_PERIPHERAL 3>;
-			};
-
-			pioC: gpio@fffff800 {
-				compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
-				reg = <0xfffff800 0x200>;
-				#gpio-cells = <2>;
-				gpio-controller;
-				clocks = <&pmc PMC_TYPE_PERIPHERAL 4>;
-			};
-
-			pioD: gpio@fffffa00 {
-				compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
-				reg = <0xfffffa00 0x200>;
-				#gpio-cells = <2>;
-				gpio-controller;
-				clocks = <&pmc PMC_TYPE_PERIPHERAL 44>;
+				pioD: gpio@fffffa00 {
+					compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
+					reg = <0xfffffa00 0x200>;
+					interrupts = <44 IRQ_TYPE_LEVEL_HIGH 1>;
+					#gpio-cells = <2>;
+					gpio-controller;
+					#gpio-lines = <22>;
+					interrupt-controller;
+					#interrupt-cells = <2>;
+					clocks = <&pmc PMC_TYPE_PERIPHERAL 44>;
+				};
 			};
 
 			pmc: pmc@fffffc00 {
diff --git a/arch/arm/dts/sam9x60ek.dts b/arch/arm/dts/sam9x60ek.dts
index 74016f5e288..6521585ee9c 100644
--- a/arch/arm/dts/sam9x60ek.dts
+++ b/arch/arm/dts/sam9x60ek.dts
@@ -78,79 +78,15 @@
 					};
 				};
 			};
-
-			pinctrl {
-				nand {
-					pinctrl_nand_oe_we: nand-oe-we-0 {
-						atmel,pins =
-							<AT91_PIOD 0 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)
-							 AT91_PIOD 1 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)>;
-					};
-
-					pinctrl_nand_rb: nand-rb-0 {
-						atmel,pins =
-							<AT91_PIOD 5 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>;
-					};
-
-					pinctrl_nand_cs: nand-cs-0 {
-						atmel,pins =
-							<AT91_PIOD 4 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>;
-					};
-				};
-
-				ebi {
-					pinctrl_ebi_data_0_7: ebi-data-lsb-0 {
-						atmel,pins =
-							<AT91_PIOD 6 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)
-							 AT91_PIOD 7 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)
-							 AT91_PIOD 8 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)
-							 AT91_PIOD 9 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)
-							 AT91_PIOD 10 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)
-							 AT91_PIOD 11 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)
-							 AT91_PIOD 12 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)
-							 AT91_PIOD 13 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)>;
-					};
-
-					pinctrl_ebi_addr_nand: ebi-addr-0 {
-						atmel,pins =
-							<AT91_PIOD 2 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)
-							 AT91_PIOD 3 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)>;
-					};
-				};
-
-				pinctrl_qspi: qspi {
-					atmel,pins =
-						<AT91_PIOB 19 AT91_PERIPH_A AT91_PINCTRL_NONE
-						 AT91_PIOB 20 AT91_PERIPH_A AT91_PINCTRL_NONE
-						 AT91_PIOB 21 AT91_PERIPH_A AT91_PINCTRL_PULL_UP
-						 AT91_PIOB 22 AT91_PERIPH_A AT91_PINCTRL_PULL_UP
-						 AT91_PIOB 23 AT91_PERIPH_A AT91_PINCTRL_PULL_UP
-						 AT91_PIOB 24 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;
-				};
-
-				pinctrl_flx0: flx0_default {
-					atmel,pins =
-						<AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE
-						 AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE>;
-				};
-
-				pinctrl_onewire_tm_default: onewire_tm_default {
-					atmel,pins =
-						<AT91_PIOD 14 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>;
-				};
-
-				usb1 {
-					pinctrl_usb_default: usb_default {
-						atmel,pins = <AT91_PIOD 15 AT91_PERIPH_GPIO AT91_PINCTRL_NONE
-								AT91_PIOD 16 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
-					};
-				};
-
-			};
 		};
 	};
 };
 
+&dbgu {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_dbgu>;
+};
+
 &ebi {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_ebi_addr_nand &pinctrl_ebi_data_0_7>;
@@ -218,9 +154,148 @@
 
 &macb0 {
 	phy-mode = "rmii";
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_macb0_rmii>;
 	status = "okay";
 };
 
+&pinctrl {
+	/* shared pinctrl settings */
+	dbgu {
+		pinctrl_dbgu: dbgu-0 {
+			atmel,pins =
+				<AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_PULL_UP
+				 AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+		};
+	};
+
+	qspi {
+		pinctrl_qspi: qspi {
+			atmel,pins =
+				<AT91_PIOB 19 AT91_PERIPH_A AT91_PINCTRL_NONE
+				 AT91_PIOB 20 AT91_PERIPH_A AT91_PINCTRL_NONE
+				 AT91_PIOB 21 AT91_PERIPH_A AT91_PINCTRL_PULL_UP
+				 AT91_PIOB 22 AT91_PERIPH_A AT91_PINCTRL_PULL_UP
+				 AT91_PIOB 23 AT91_PERIPH_A AT91_PINCTRL_PULL_UP
+				 AT91_PIOB 24 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;
+		};
+	};
+
+	nand {
+		pinctrl_nand_oe_we: nand-oe-we-0 {
+			atmel,pins =
+				<AT91_PIOD 0 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)
+				 AT91_PIOD 1 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)>;
+		};
+
+		pinctrl_nand_rb: nand-rb-0 {
+			atmel,pins =
+				<AT91_PIOD 5 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>;
+		};
+
+		pinctrl_nand_cs: nand-cs-0 {
+			atmel,pins =
+				<AT91_PIOD 4 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>;
+		};
+	};
+
+	ebi {
+		pinctrl_ebi_data_0_7: ebi-data-lsb-0 {
+			atmel,pins =
+				<AT91_PIOD 6 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)
+				 AT91_PIOD 7 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)
+				 AT91_PIOD 8 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)
+				 AT91_PIOD 9 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)
+				 AT91_PIOD 10 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)
+				 AT91_PIOD 11 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)
+				 AT91_PIOD 12 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)
+				 AT91_PIOD 13 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)>;
+		};
+
+		pinctrl_ebi_addr_nand: ebi-addr-0 {
+			atmel,pins =
+				<AT91_PIOD 2 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)
+				 AT91_PIOD 3 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)>;
+		};
+	};
+
+	flexcom {
+		pinctrl_flx0: flx0_default {
+			atmel,pins =
+				<AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE
+				 AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+		};
+	};
+
+	macb0 {
+		pinctrl_macb0_rmii: macb0_rmii-0 {
+			atmel,pins =
+				<AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB0 periph A */
+				 AT91_PIOB 1 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB1 periph A */
+				 AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB2 periph A */
+				 AT91_PIOB 3 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB3 periph A */
+				 AT91_PIOB 4 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB4 periph A */
+				 AT91_PIOB 5 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB5 periph A */
+				 AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB6 periph A */
+				 AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB7 periph A */
+				 AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB9 periph A */
+				 AT91_PIOB 10 AT91_PERIPH_A AT91_PINCTRL_NONE>;	/* PB10 periph A */
+		};
+	};
+
+	pinctrl_onewire_tm_default: onewire_tm_default {
+		atmel,pins =
+			<AT91_PIOD 14 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>;
+	};
+
+	sdhci0 {
+		pinctrl_sdhci0: sdhci0 {
+			atmel,pins =
+				<AT91_PIOA 17 AT91_PERIPH_A
+				 (AT91_PINCTRL_DRIVE_STRENGTH_HI | AT91_PINCTRL_SLEWRATE_ENA)	/* PA17 CK  periph A with pullup */
+				 AT91_PIOA 16 AT91_PERIPH_A
+				 (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI | AT91_PINCTRL_SLEWRATE_ENA)	/* PA16 CMD periph A with pullup */
+				 AT91_PIOA 15 AT91_PERIPH_A
+				 (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI | AT91_PINCTRL_SLEWRATE_ENA)	/* PA15 DAT0 periph A */
+				 AT91_PIOA 18 AT91_PERIPH_A
+				 (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI | AT91_PINCTRL_SLEWRATE_ENA)	/* PA18 DAT1 periph A with pullup */
+				 AT91_PIOA 19 AT91_PERIPH_A
+				 (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI | AT91_PINCTRL_SLEWRATE_ENA)	/* PA19 DAT2 periph A with pullup */
+				 AT91_PIOA 20 AT91_PERIPH_A
+				 (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI | AT91_PINCTRL_SLEWRATE_ENA)>;	/* PA20 DAT3 periph A with pullup */
+		};
+	};
+
+	sdhci1 {
+		pinctrl_sdhci1: sdhci1 {
+			atmel,pins =
+				<AT91_PIOA 13 AT91_PERIPH_B (AT91_PINCTRL_DRIVE_STRENGTH_HI)				/* PA13 CK periph B */
+				 AT91_PIOA 12 AT91_PERIPH_B (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI)	/* PA12 CMD periph B with pullup */
+				 AT91_PIOA 11 AT91_PERIPH_B (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI)	/* PA11 DAT0 periph B with pullup */
+				 AT91_PIOA 2 AT91_PERIPH_B (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI)	/* PA2 DAT1 periph B with pullup */
+				 AT91_PIOA 3 AT91_PERIPH_B (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI)	/* PA3 DAT2 periph B with pullup */
+				 AT91_PIOA 4 AT91_PERIPH_B (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI)>;	/* PA4 DAT3 periph B with pullup */
+		};
+	};
+
+	usb1 {
+		pinctrl_usb_default: usb_default {
+			atmel,pins = <AT91_PIOD 15 AT91_PERIPH_GPIO AT91_PINCTRL_NONE
+				      AT91_PIOD 16 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
+		};
+	};
+};
+
+&sdhci0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_sdhci0>;
+};
+
+&sdhci1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_sdhci1>;
+};
+
 &usb1 {
 	num-ports = <3>;
 	atmel,vbus-gpio = <0
diff --git a/arch/arm/dts/sama5d3.dtsi b/arch/arm/dts/sama5d3.dtsi
index 4c03a302ec7..10d6e74586d 100644
--- a/arch/arm/dts/sama5d3.dtsi
+++ b/arch/arm/dts/sama5d3.dtsi
@@ -492,12 +492,6 @@
 					0xffffffff 0xc001c0e0 0x0001c1e0	/* pioD */
 					0xffffffff 0xbf9f8000 0x18000000	/* pioE */
 					>;
-				reg = <0xfffff200 0x100		/* pioA */
-				       0xfffff400 0x100		/* pioB */
-				       0xfffff600 0x100		/* pioC */
-				       0xfffff800 0x100		/* pioD */
-				       0xfffffa00 0x100		/* pioE */
-				       >;
 
 				/* shared pinctrl settings */
 				adc0 {
@@ -873,66 +867,66 @@
 							 AT91_PIOE 17 AT91_PERIPH_B AT91_PINCTRL_NONE>;	/* PE17 periph B, conflicts with A17 */
 					};
 				};
-			};
 
-			pioA: gpio@fffff200 {
-				compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
-				reg = <0xfffff200 0x100>;
-				interrupts = <6 IRQ_TYPE_LEVEL_HIGH 1>;
-				#gpio-cells = <2>;
-				gpio-controller;
-				interrupt-controller;
-				#interrupt-cells = <2>;
-				clocks = <&pioA_clk>;
-				bootph-all;
-			};
+				pioA: gpio@fffff200 {
+					compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
+					reg = <0xfffff200 0x100>;
+					interrupts = <6 IRQ_TYPE_LEVEL_HIGH 1>;
+					#gpio-cells = <2>;
+					gpio-controller;
+					interrupt-controller;
+					#interrupt-cells = <2>;
+					clocks = <&pioA_clk>;
+					bootph-all;
+				};
 
-			pioB: gpio@fffff400 {
-				compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
-				reg = <0xfffff400 0x100>;
-				interrupts = <7 IRQ_TYPE_LEVEL_HIGH 1>;
-				#gpio-cells = <2>;
-				gpio-controller;
-				interrupt-controller;
-				#interrupt-cells = <2>;
-				clocks = <&pioB_clk>;
-				bootph-all;
-			};
+				pioB: gpio@fffff400 {
+					compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
+					reg = <0xfffff400 0x100>;
+					interrupts = <7 IRQ_TYPE_LEVEL_HIGH 1>;
+					#gpio-cells = <2>;
+					gpio-controller;
+					interrupt-controller;
+					#interrupt-cells = <2>;
+					clocks = <&pioB_clk>;
+					bootph-all;
+				};
 
-			pioC: gpio@fffff600 {
-				compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
-				reg = <0xfffff600 0x100>;
-				interrupts = <8 IRQ_TYPE_LEVEL_HIGH 1>;
-				#gpio-cells = <2>;
-				gpio-controller;
-				interrupt-controller;
-				#interrupt-cells = <2>;
-				clocks = <&pioC_clk>;
-				bootph-all;
-			};
+				pioC: gpio@fffff600 {
+					compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
+					reg = <0xfffff600 0x100>;
+					interrupts = <8 IRQ_TYPE_LEVEL_HIGH 1>;
+					#gpio-cells = <2>;
+					gpio-controller;
+					interrupt-controller;
+					#interrupt-cells = <2>;
+					clocks = <&pioC_clk>;
+					bootph-all;
+				};
 
-			pioD: gpio@fffff800 {
-				compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
-				reg = <0xfffff800 0x100>;
-				interrupts = <9 IRQ_TYPE_LEVEL_HIGH 1>;
-				#gpio-cells = <2>;
-				gpio-controller;
-				interrupt-controller;
-				#interrupt-cells = <2>;
-				clocks = <&pioD_clk>;
-				bootph-all;
-			};
+				pioD: gpio@fffff800 {
+					compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
+					reg = <0xfffff800 0x100>;
+					interrupts = <9 IRQ_TYPE_LEVEL_HIGH 1>;
+					#gpio-cells = <2>;
+					gpio-controller;
+					interrupt-controller;
+					#interrupt-cells = <2>;
+					clocks = <&pioD_clk>;
+					bootph-all;
+				};
 
-			pioE: gpio@fffffa00 {
-				compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
-				reg = <0xfffffa00 0x100>;
-				interrupts = <10 IRQ_TYPE_LEVEL_HIGH 1>;
-				#gpio-cells = <2>;
-				gpio-controller;
-				interrupt-controller;
-				#interrupt-cells = <2>;
-				clocks = <&pioE_clk>;
-				bootph-all;
+				pioE: gpio@fffffa00 {
+					compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
+					reg = <0xfffffa00 0x100>;
+					interrupts = <10 IRQ_TYPE_LEVEL_HIGH 1>;
+					#gpio-cells = <2>;
+					gpio-controller;
+					interrupt-controller;
+					#interrupt-cells = <2>;
+					clocks = <&pioE_clk>;
+					bootph-all;
+				};
 			};
 
 			pmc: pmc@fffffc00 {
diff --git a/arch/arm/dts/sama5d4.dtsi b/arch/arm/dts/sama5d4.dtsi
index 5e2c9a1db2f..482cf03e61b 100644
--- a/arch/arm/dts/sama5d4.dtsi
+++ b/arch/arm/dts/sama5d4.dtsi
@@ -1361,62 +1361,6 @@
 				status = "disabled";
 			};
 
-			pioA: gpio@fc06a000 {
-				compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
-				reg = <0xfc06a000 0x100>;
-				interrupts = <23 IRQ_TYPE_LEVEL_HIGH 1>;
-				#gpio-cells = <2>;
-				gpio-controller;
-				interrupt-controller;
-				#interrupt-cells = <2>;
-				clocks = <&pioA_clk>;
-			};
-
-			pioB: gpio@fc06b000 {
-				compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
-				reg = <0xfc06b000 0x100>;
-				interrupts = <24 IRQ_TYPE_LEVEL_HIGH 1>;
-				#gpio-cells = <2>;
-				gpio-controller;
-				interrupt-controller;
-				#interrupt-cells = <2>;
-				clocks = <&pioB_clk>;
-			};
-
-			pioC: gpio@fc06c000 {
-				compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
-				reg = <0xfc06c000 0x100>;
-				interrupts = <25 IRQ_TYPE_LEVEL_HIGH 1>;
-				#gpio-cells = <2>;
-				gpio-controller;
-				interrupt-controller;
-				#interrupt-cells = <2>;
-				clocks = <&pioC_clk>;
-				bootph-all;
-			};
-
-			pioD: gpio@fc068000 {
-				compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
-				reg = <0xfc068000 0x100>;
-				interrupts = <5 IRQ_TYPE_LEVEL_HIGH 1>;
-				#gpio-cells = <2>;
-				gpio-controller;
-				interrupt-controller;
-				#interrupt-cells = <2>;
-				clocks = <&pioD_clk>;
-			};
-
-			pioE: gpio@fc06d000 {
-				compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
-				reg = <0xfc06d000 0x100>;
-				interrupts = <26 IRQ_TYPE_LEVEL_HIGH 1>;
-				#gpio-cells = <2>;
-				gpio-controller;
-				interrupt-controller;
-				#interrupt-cells = <2>;
-				clocks = <&pioE_clk>;
-			};
-
 			pinctrl@fc06a000 {
 				bootph-all;
 				#address-cells = <1>;
@@ -1433,12 +1377,62 @@
 					0x0003ff00 0x8002a800 0x00000000	/* pioD */
 					0xffffffff 0x7fffffff 0x76fff1bf	/* pioE */
 					>;
-				reg = < 0xfc06a000 0x100
-					0xfc06b000 0x100
-					0xfc06c000 0x100
-					0xfc068000 0x100
-					0xfc06d000 0x100
-					>;
+
+				pioA: gpio@fc06a000 {
+					compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
+					reg = <0xfc06a000 0x100>;
+					interrupts = <23 IRQ_TYPE_LEVEL_HIGH 1>;
+					#gpio-cells = <2>;
+					gpio-controller;
+					interrupt-controller;
+					#interrupt-cells = <2>;
+					clocks = <&pioA_clk>;
+				};
+
+				pioB: gpio@fc06b000 {
+					compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
+					reg = <0xfc06b000 0x100>;
+					interrupts = <24 IRQ_TYPE_LEVEL_HIGH 1>;
+					#gpio-cells = <2>;
+					gpio-controller;
+					interrupt-controller;
+					#interrupt-cells = <2>;
+					clocks = <&pioB_clk>;
+				};
+
+				pioC: gpio@fc06c000 {
+					compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
+					reg = <0xfc06c000 0x100>;
+					interrupts = <25 IRQ_TYPE_LEVEL_HIGH 1>;
+					#gpio-cells = <2>;
+					gpio-controller;
+					interrupt-controller;
+					#interrupt-cells = <2>;
+					clocks = <&pioC_clk>;
+					bootph-all;
+				};
+
+				pioD: gpio@fc068000 {
+					compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
+					reg = <0xfc068000 0x100>;
+					interrupts = <5 IRQ_TYPE_LEVEL_HIGH 1>;
+					#gpio-cells = <2>;
+					gpio-controller;
+					interrupt-controller;
+					#interrupt-cells = <2>;
+					clocks = <&pioD_clk>;
+				};
+
+				pioE: gpio@fc06d000 {
+					compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
+					reg = <0xfc06d000 0x100>;
+					interrupts = <26 IRQ_TYPE_LEVEL_HIGH 1>;
+					#gpio-cells = <2>;
+					gpio-controller;
+					interrupt-controller;
+					#interrupt-cells = <2>;
+					clocks = <&pioE_clk>;
+				};
 
 				/* pinctrl pin settings */
 				adc0 {
diff --git a/arch/arm/dts/socfpga_agilex5-u-boot.dtsi b/arch/arm/dts/socfpga_agilex5-u-boot.dtsi
index a8167e5c14a..8d6503dd091 100644
--- a/arch/arm/dts/socfpga_agilex5-u-boot.dtsi
+++ b/arch/arm/dts/socfpga_agilex5-u-boot.dtsi
@@ -3,6 +3,7 @@
  * U-Boot additions
  *
  * Copyright (C) 2024 Intel Corporation <www.intel.com>
+ * Copyright (C) 2025 Altera Corporation <www.altera.com>
  */
 
 #include "socfpga_soc64_fit-u-boot.dtsi"
@@ -13,6 +14,659 @@
 		#size-cells = <2>;
 		bootph-all;
 	};
+
+	soc {
+		bootph-all;
+
+		socfpga_ccu_config: socfpga-ccu-config {
+			compatible = "intel,socfpga-dtreg";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			bootph-all;
+
+			/* DSU */
+			i_ccu_caiu0@1c000000 {
+				reg = <0x1c000000 0x00001000>;
+				intel,offset-settings =
+					/* CAIUMIFSR */
+					<0x000003c4 0x00000000 0x07070777>,
+					/* DII1_MPFEREGS */
+					<0x00000414 0x00018000 0xffffffff>,
+					<0x00000418 0x00000000 0x000000ff>,
+					<0x00000410 0xc0e00200 0xc1f03e1f>,
+					/* DII2_GICREGS */
+					<0x00000424 0x0001d000 0xffffffff>,
+					<0x00000428 0x00000000 0x000000ff>,
+					<0x00000420 0xc0800400 0xc1f03e1f>,
+					/* NCAIU0_LWSOC2FPGA */
+					<0x00000444 0x00020000 0xffffffff>,
+					<0x00000448 0x00000000 0x000000ff>,
+					<0x00000440 0xc1100006 0xc1f03e1f>,
+					/* NCAIU0_SOC2FPGA_1G */
+					<0x00000454 0x00040000 0xffffffff>,
+					<0x00000458 0x00000000 0x000000ff>,
+					<0x00000450 0xc1200006 0xc1f03e1f>,
+					/* DMI_SDRAM_2G */
+					<0x00000464 0x00080000 0xffffffff>,
+					<0x00000468 0x00000000 0x000000ff>,
+					/* NCAIU0_SOC2FPGA_16G */
+					<0x00000474 0x00400000 0xffffffff>,
+					<0x00000478 0x00000000 0x000000ff>,
+					<0x00000470 0xc1600006 0xc1f03e1f>,
+					/* DMI_SDRAM_30G */
+					<0x00000484 0x00800000 0xffffffff>,
+					<0x00000488 0x00000000 0x000000ff>,
+					/* NCAIU0_SOC2FPGA_256G */
+					<0x00000494 0x04000000 0xffffffff>,
+					<0x00000498 0x00000000 0x000000ff>,
+					<0x00000490 0xc1a00006 0xc1f03e1f>,
+					/* DMI_SDRAM_480G */
+					<0x000004a4 0x08000000 0xffffffff>,
+					<0x000004a8 0x00000000 0x000000ff>;
+				bootph-all;
+			};
+
+			/* FPGA2SOC */
+			i_ccu_ncaiu0@1c001000 {
+				reg = <0x1c001000 0x00001000>;
+				intel,offset-settings =
+					/* NCAIU0MIFSR */
+					<0x000003c4 0x00000000 0x07070777>,
+					/* PSS */
+					<0x00000404 0x00010000 0xffffffff>,
+					<0x00000408 0x00000000 0x000000ff>,
+					<0x00000400 0xC0F00000 0xc1f03e1f>,
+					/* DII1_MPFEREGS */
+					<0x00000414 0x00018000 0xffffffff>,
+					<0x00000418 0x00000000 0x000000ff>,
+					<0x00000410 0xc0e00200 0xc1f03e1f>,
+					/* NCAIU0_LWSOC2FPGA */
+					<0x00000444 0x00020000 0xffffffff>,
+					<0x00000448 0x00000000 0x000000ff>,
+					<0x00000440 0xc1100006 0xc1f03e1f>,
+					/* NCAIU0_SOC2FPGA_1G */
+					<0x00000454 0x00040000 0xffffffff>,
+					<0x00000458 0x00000000 0x000000ff>,
+					<0x00000450 0xc1200006 0xc1f03e1f>,
+					/* DMI_SDRAM_2G */
+					<0x00000464 0x00080000 0xffffffff>,
+					<0x00000468 0x00000000 0x000000ff>,
+					/* NCAIU0_SOC2FPGA_16G */
+					<0x00000474 0x00400000 0xffffffff>,
+					<0x00000478 0x00000000 0x000000ff>,
+					<0x00000470 0xc1600006 0xc1f03e1f>,
+					/* DMI_SDRAM_30G */
+					<0x00000484 0x00800000 0xffffffff>,
+					<0x00000488 0x00000000 0x000000ff>,
+					/* NCAIU0_SOC2FPGA_256G */
+					<0x00000494 0x04000000 0xffffffff>,
+					<0x00000498 0x00000000 0x000000ff>,
+					<0x00000490 0xc1a00006 0xc1f03e1f>,
+					/* DMI_SDRAM_480G */
+					<0x000004a4 0x08000000 0xffffffff>,
+					<0x000004a8 0x00000000 0x000000ff>;
+				bootph-all;
+			};
+
+			/* GIC_M */
+			i_ccu_ncaiu1@1c002000 {
+				reg = <0x1c002000 0x00001000>;
+				intel,offset-settings =
+					/* NCAIU1MIFSR */
+					<0x000003c4 0x00000000 0x07070777>,
+					/* DMI_SDRAM_2G */
+					<0x00000464 0x00080000 0xffffffff>,
+					<0x00000468 0x00000000 0x000000ff>,
+					/* DMI_SDRAM_30G */
+					<0x00000484 0x00800000 0xffffffff>,
+					<0x00000488 0x00000000 0x000000ff>,
+					/* DMI_SDRAM_480G */
+					<0x000004a4 0x08000000 0xffffffff>,
+					<0x000004a8 0x00000000 0x000000ff>;
+				bootph-all;
+			};
+
+			/* SMMU */
+			i_ccu_ncaiu2@1c003000 {
+				reg = <0x1c003000 0x00001000>;
+				intel,offset-settings =
+					/* NCAIU2MIFSR */
+					<0x000003c4 0x00000000 0x07070777>,
+					/* DMI_SDRAM_2G */
+					<0x00000464 0x00080000 0xffffffff>,
+					<0x00000468 0x00000000 0x000000ff>,
+					/* DMI_SDRAM_30G */
+					<0x00000484 0x00800000 0xffffffff>,
+					<0x00000488 0x00000000 0x000000ff>,
+					/* DMI_SDRAM_480G */
+					<0x000004a4 0x08000000 0xffffffff>,
+					<0x000004a8 0x00000000 0x000000ff>;
+				bootph-all;
+			};
+
+			/* PSS NOC */
+			i_ccu_ncaiu3@1c004000 {
+				reg = <0x1c004000 0x00001000>;
+				intel,offset-settings =
+					/* NCAIU3MIFSR */
+					<0x000003c4 0x00000000 0x07070777>,
+					/* DII1_MPFEREGS */
+					<0x00000414 0x00018000 0xffffffff>,
+					<0x00000418 0x00000000 0x000000ff>,
+					<0x00000410 0xc0e00200 0xc1f03e1f>,
+					/* DMI_SDRAM_2G */
+					<0x00000464 0x00080000 0xffffffff>,
+					<0x00000468 0x00000000 0x000000ff>,
+					/* DMI_SDRAM_30G */
+					<0x00000484 0x00800000 0xffffffff>,
+					<0x00000488 0x00000000 0x000000ff>,
+					/* DMI_SDRAM_480G */
+					<0x000004a4 0x08000000 0xffffffff>,
+					<0x000004a8 0x00000000 0x000000ff>;
+				bootph-all;
+			};
+
+			/* DCE0 */
+			i_ccu_dce0@1c005000 {
+				reg = <0x1c005000 0x00001000>;
+				intel,offset-settings =
+					/* DCEUMIFSR0 */
+					<0x000003c4 0x00000000 0x07070777>,
+					/* DMI_SDRAM_2G */
+					<0x00000464 0x00080000 0xffffffff>,
+					<0x00000468 0x00000000 0x000000ff>,
+					/* DMI_SDRAM_30G */
+					<0x00000484 0x00800000 0xffffffff>,
+					<0x00000488 0x00000000 0x000000ff>,
+					/* DMI_SDRAM_480G */
+					<0x000004a4 0x08000000 0xffffffff>,
+					<0x000004a8 0x00000000 0x000000ff>;
+				bootph-all;
+			};
+
+			/* DCE1 */
+			i_ccu_dce1@1c006000 {
+				reg = <0x1c006000 0x00001000>;
+				intel,offset-settings =
+					/* DCEUMIFSR1 */
+					<0x000003c4 0x00000000 0x07070777>,
+					/* DMI_SDRAM_2G */
+					<0x00000464 0x00080000 0xffffffff>,
+					<0x00000468 0x00000000 0x000000ff>,
+					/* DMI_SDRAM_30G */
+					<0x00000484 0x00800000 0xffffffff>,
+					<0x00000488 0x00000000 0x000000ff>,
+					/* DMI_SDRAM_480G */
+					<0x000004a4 0x08000000 0xffffffff>,
+					<0x000004a8 0x00000000 0x000000ff>;
+				bootph-all;
+			};
+
+			/* DMI0 */
+			i_ccu_dmi0@1c007000 {
+				reg = <0x1c007000 0x00001000>;
+				intel,offset-settings =
+					/* DMIUSMCTCR */
+					<0x00000300 0x00000001 0x00000003>,
+					<0x00000300 0x00000003 0x00000003>;
+				bootph-all;
+			};
+
+			/* DMI1 */
+			i_ccu_dmi0@1c008000 {
+				reg = <0x1c008000 0x00001000>;
+				intel,offset-settings =
+					/* DMIUSMCTCR */
+					<0x00000300 0x00000001 0x00000003>,
+					<0x00000300 0x00000003 0x00000003>;
+				bootph-all;
+			};
+		};
+
+		socfpga_firewall_config: socfpga-firewall-config {
+			compatible = "intel,socfpga-dtreg";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			bootph-all;
+
+			/* L4 peripherals firewall */
+			noc_fw_l4_per@10d21000 {
+				reg = <0x10d21000 0x0000008c>;
+				intel,offset-settings =
+					/* NAND */
+					<0x00000000 0x01010001 0x01010001>,
+					/* USB0 */
+					<0x0000000c 0x01010001 0x01010001>,
+					/* USB1 */
+					<0x00000010 0x01010001 0x01010001>,
+					/* SPI_MAIN0 */
+					<0x0000001c 0x01010301 0x01010301>,
+					/* SPI_MAIN1 */
+					<0x00000020 0x01010301 0x01010301>,
+					/* SPI_SECONDARY0 */
+					<0x00000024 0x01010301 0x01010301>,
+					/* SPI_SECONDARY1 */
+					<0x00000028 0x01010301 0x01010301>,
+					/* EMAC0 */
+					<0x0000002c 0x01010001 0x01010001>,
+					/* EMAC1 */
+					<0x00000030 0x01010001 0x01010001>,
+					/* EMAC2 */
+					<0x00000034 0x01010001 0x01010001>,
+					/* SDMMC */
+					<0x00000040 0x01010001 0x01010001>,
+					/* GPIO0 */
+					<0x00000044 0x01010301 0x01010301>,
+					/* GPIO1 */
+					<0x00000048 0x01010301 0x01010301>,
+					/* I2C0 */
+					<0x00000050 0x01010301 0x01010301>,
+					/* I2C1 */
+					<0x00000054 0x01010301 0x01010301>,
+					/* I2C2 */
+					<0x00000058 0x01010301 0x01010301>,
+					/* I2C3 */
+					<0x0000005c 0x01010301 0x01010301>,
+					/* I2C4 */
+					<0x00000060 0x01010301 0x01010301>,
+					/* SP_TIMER0 */
+					<0x00000064 0x01010301 0x01010301>,
+					/* SP_TIMER1 */
+					<0x00000068 0x01010301 0x01010301>,
+					/* UART0 */
+					<0x0000006c 0x01010301 0x01010301>,
+					/* UART1 */
+					<0x00000070 0x01010301 0x01010301>,
+					/* I3C0 */
+					<0x00000074 0x01010301 0x01010301>,
+					/* I3C1 */
+					<0x00000078 0x01010301 0x01010301>,
+					/* DMA0 */
+					<0x0000007c 0x01010001 0x01010001>,
+					/* DMA1 */
+					<0x00000080 0x01010001 0x01010001>,
+					/* COMBO_PHY */
+					<0x00000084 0x01010001 0x01010001>,
+					/* NAND_SDMA */
+					<0x00000088 0x01010301 0x01010301>;
+				bootph-all;
+			};
+
+			/* L4 system firewall */
+			noc_fw_l4_sys@10d21100 {
+				reg = <0x10d21100 0x00000098>;
+				intel,offset-settings =
+					/* DMA_ECC */
+					<0x00000008 0x01010001 0x01010001>,
+					/* EMAC0RX_ECC */
+					<0x0000000c 0x01010001 0x01010001>,
+					/* EMAC0TX_ECC */
+					<0x00000010 0x01010001 0x01010001>,
+					/* EMAC1RX_ECC */
+					<0x00000014 0x01010001 0x01010001>,
+					/* EMAC1TX_ECC */
+					<0x00000018 0x01010001 0x01010001>,
+					/* EMAC2RX_ECC */
+					<0x0000001c 0x01010001 0x01010001>,
+					/* EMAC2TX_ECC */
+					<0x00000020 0x01010001 0x01010001>,
+					/* NAND_ECC */
+					<0x0000002c 0x01010001 0x01010001>,
+					/* NAND_READ_ECC */
+					<0x00000030 0x01010001 0x01010001>,
+					/* NAND_WRITE_ECC */
+					<0x00000034 0x01010001 0x01010001>,
+					/* OCRAM_ECC */
+					<0x00000038 0x01010001 0x01010001>,
+					/* SDMMC_ECC */
+					<0x00000040 0x01010001 0x01010001>,
+					/* USB0_ECC */
+					<0x00000044 0x01010001 0x01010001>,
+					/* USB1_CACHEECC */
+					<0x00000048 0x01010001 0x01010001>,
+					/* CLOCK_MANAGER */
+					<0x0000004c 0x01010001 0x01010001>,
+					/* IO_MANAGER */
+					<0x00000054 0x01010001 0x01010001>,
+					/* RESET_MANAGER */
+					<0x00000058 0x01010001 0x01010001>,
+					/* SYSTEM_MANAGER */
+					<0x0000005c 0x01010001 0x01010001>,
+					/* OSC0_TIMER */
+					<0x00000060 0x01010301 0x01010301>,
+					/* OSC1_TIMER0*/
+					<0x00000064 0x01010301 0x01010301>,
+					/* WATCHDOG0 */
+					<0x00000068 0x01010301 0x01010301>,
+					/* WATCHDOG1 */
+					<0x0000006c 0x01010301 0x01010301>,
+					/* WATCHDOG2 */
+					<0x00000070 0x01010301 0x01010301>,
+					/* WATCHDOG3 */
+					<0x00000074 0x01010301 0x01010301>,
+					/* DAP */
+					<0x00000078 0x03010001 0x03010001>,
+					/* WATCHDOG4 */
+					<0x0000007c 0x01010301 0x01010301>,
+					/* POWER_MANAGER */
+					<0x00000080 0x01010001 0x01010001>,
+					/* USB1_RXECC */
+					<0x00000084 0x01010001 0x01010001>,
+					/* USB1_TXECC */
+					<0x00000088 0x01010001 0x01010001>,
+					/* L4_NOC_PROBES */
+					<0x00000090 0x01010001 0x01010001>,
+					/* L4_NOC_QOS */
+					<0x00000094 0x01010001 0x01010001>;
+				bootph-all;
+			};
+
+			/* Light weight SoC2FPGA */
+			noc_fw_lwsoc2fpga@10d21300 {
+				reg = <0x10d21300 0x0000004>;
+				intel,offset-settings =
+					/* LWSOC2FPGA_CSR */
+					<0x00000000 0x0ffe0301 0x0ffe0301>;
+				bootph-all;
+			};
+
+			/* SoC2FPGA */
+			noc_fw_soc2fpga@10d21200 {
+				reg = <0x10d21200 0x0000004>;
+				intel,offset-settings =
+					/* SOC2FPGA_CSR */
+					<0x00000000 0x0ffe0301 0x0ffe0301>;
+				bootph-all;
+			};
+
+			/* TCU */
+			noc_fw_tcu@10d21400 {
+				reg = <0x10d21400 0x0000004>;
+				intel,offset-settings =
+					/* TCU_CSR */
+					<0x00000000 0x01010001 0x01010001>;
+				bootph-all;
+			};
+		};
+
+		socfpga_ccu_ddr_interleaving_off: socfpga-ccu-ddr-interleaving-off {
+			compatible = "intel,socfpga-dtreg";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			bootph-all;
+
+			/* DSU */
+			i_ccu_caiu0@1c000000 {
+				reg = <0x1c000000 0x00001000>;
+				intel,offset-settings =
+					/* CAIUAMIGR */
+					<0x000003c0 0x00000003 0x0000001f>,
+					/* DMI_SDRAM_2G */
+					<0x00000460 0x81300006 0xc1f03e1f>,
+					/* DMI_SDRAM_30G */
+					<0x00000480 0x81700006 0xc1f03e1f>,
+					/* DMI_SDRAM_480G */
+					<0x000004a0 0x81b00006 0xc1f03e1f>;
+				bootph-all;
+			};
+
+			/* FPGA2SOC */
+			i_ccu_ncaiu0@1c001000 {
+				reg = <0x1c001000 0x00001000>;
+				intel,offset-settings =
+					/* NCAIU0AMIGR */
+					<0x000003c0 0x00000003 0x0000001f>,
+					/* DMI_SDRAM_2G */
+					<0x00000460 0x81300006 0xc1f03e1f>,
+					/* DMI_SDRAM_30G */
+					<0x00000480 0x81700006 0xc1f03e1f>,
+					/* DMI_SDRAM_480G */
+					<0x000004a0 0x81b00006 0xc1f03e1f>;
+				bootph-all;
+			};
+
+			/* GIC_M */
+			i_ccu_ncaiu1@1c002000 {
+				reg = <0x1c002000 0x00001000>;
+				intel,offset-settings =
+					/* NCAIU1AMIGR */
+					<0x000003c0 0x00000003 0x0000001f>,
+					/* DMI_SDRAM_2G */
+					<0x00000460 0x81300006 0xc1f03e1f>,
+					/* DMI_SDRAM_30G */
+					<0x00000480 0x81700006 0xc1f03e1f>,
+					/* DMI_SDRAM_480G */
+					<0x000004a0 0x81b00006 0xc1f03e1f>;
+				bootph-all;
+			};
+
+			/* SMMU */
+			i_ccu_ncaiu2@1c003000 {
+				reg = <0x1c003000 0x00001000>;
+				intel,offset-settings =
+					/* NCAIU2AMIGR */
+					<0x000003c0 0x00000003 0x0000001f>,
+					/* DMI_SDRAM_2G */
+					<0x00000460 0x81300006 0xc1f03e1f>,
+					/* DMI_SDRAM_30G */
+					<0x00000480 0x81700006 0xc1f03e1f>,
+					/* DMI_SDRAM_480G */
+					<0x000004a0 0x81b00006 0xc1f03e1f>;
+				bootph-all;
+			};
+
+			/* PSS NOC */
+			i_ccu_ncaiu3@1c004000 {
+				reg = <0x1c004000 0x00001000>;
+				intel,offset-settings =
+					/* NCAIU3AMIGR */
+					<0x000003c0 0x00000003 0x0000001f>,
+					/* DMI_SDRAM_2G */
+					<0x00000460 0x81300006 0xc1f03e1f>,
+					/* DMI_SDRAM_30G */
+					<0x00000480 0x81700006 0xc1f03e1f>,
+					/* DMI_SDRAM_480G */
+					<0x000004a0 0x81b00006 0xc1f03e1f>;
+				bootph-all;
+			};
+
+			/* DCE0 */
+			i_ccu_dce0@1c005000 {
+				reg = <0x1c005000 0x00001000>;
+				intel,offset-settings =
+					/* DCEUAMIGR0 */
+					<0x000003c0 0x00000003 0x0000001f>,
+					/* DMI_SDRAM_2G */
+					<0x00000460 0x81300006 0xc1f03e1f>,
+					/* DMI_SDRAM_30G */
+					<0x00000480 0x81700006 0xc1f03e1f>,
+					/* DMI_SDRAM_480G */
+					<0x000004a0 0x81b00006 0xc1f03e1f>;
+				bootph-all;
+			};
+
+			/* DCE1 */
+			i_ccu_dce1@1c006000 {
+				reg = <0x1c006000 0x00001000>;
+				intel,offset-settings =
+					/* DCEUAMIGR1 */
+					<0x000003c0 0x00000003 0x0000001f>,
+					/* DMI_SDRAM_2G */
+					<0x00000460 0x81300006 0xc1f03e1f>,
+					/* DMI_SDRAM_30G */
+					<0x00000480 0x81700006 0xc1f03e1f>,
+					/* DMI_SDRAM_480G */
+					<0x000004a0 0x81b00006 0xc1f03e1f>;
+				bootph-all;
+			};
+		};
+
+		socfpga_ccu_ddr_interleaving_on: socfpga-ccu-ddr-interleaving-on {
+			compatible = "intel,socfpga-dtreg";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			bootph-all;
+
+			/* DSU */
+			i_ccu_caiu0@1c000000 {
+				reg = <0x1c000000 0x00001000>;
+				intel,offset-settings =
+					/* CAIUAMIGR */
+					<0x000003c0 0x00000001 0x0000001f>,
+					/* DMI_SDRAM_2G */
+					<0x00000460 0x81200006 0xc1f03e1f>,
+					/* DMI_SDRAM_30G */
+					<0x00000480 0x81600006 0xc1f03e1f>,
+					/* DMI_SDRAM_480G */
+					<0x000004a0 0x81a00006 0xc1f03e1f>;
+				bootph-all;
+			};
+
+			/* FPGA2SOC */
+			i_ccu_ncaiu0@1c001000 {
+				reg = <0x1c001000 0x00001000>;
+				intel,offset-settings =
+					/* NCAIU0AMIGR */
+					<0x000003c0 0x00000001 0x0000001f>,
+					/* DMI_SDRAM_2G */
+					<0x00000460 0x81200006 0xc1f03e1f>,
+					/* DMI_SDRAM_30G */
+					<0x00000480 0x81600006 0xc1f03e1f>,
+					/* DMI_SDRAM_480G */
+					<0x000004a0 0x81a00006 0xc1f03e1f>;
+				bootph-all;
+			};
+
+			/* GIC_M */
+			i_ccu_ncaiu1@1c002000 {
+				reg = <0x1c002000 0x00001000>;
+				intel,offset-settings =
+					/* NCAIU1AMIGR */
+					<0x000003c0 0x00000001 0x0000001f>,
+					/* DMI_SDRAM_2G */
+					<0x00000460 0x81200006 0xc1f03e1f>,
+					/* DMI_SDRAM_30G */
+					<0x00000480 0x81600006 0xc1f03e1f>,
+					/* DMI_SDRAM_480G */
+					<0x000004a0 0x81a00006 0xc1f03e1f>;
+				bootph-all;
+			};
+
+			/* SMMU */
+			i_ccu_ncaiu2@1c003000 {
+				reg = <0x1c003000 0x00001000>;
+				intel,offset-settings =
+					/* NCAIU2AMIGR */
+					<0x000003c0 0x00000001 0x0000001f>,
+					/* DMI_SDRAM_2G */
+					<0x00000460 0x81200006 0xc1f03e1f>,
+					/* DMI_SDRAM_30G */
+					<0x00000480 0x81600006 0xc1f03e1f>,
+					/* DMI_SDRAM_480G */
+					<0x000004a0 0x81a00006 0xc1f03e1f>;
+				bootph-all;
+			};
+
+			/* PSS NOC */
+			i_ccu_ncaiu3@1c004000 {
+				reg = <0x1c004000 0x00001000>;
+				intel,offset-settings =
+					/* NCAIU3AMIGR */
+					<0x000003c0 0x00000001 0x0000001f>,
+					/* DMI_SDRAM_2G */
+					<0x00000460 0x81200006 0xc1f03e1f>,
+					/* DMI_SDRAM_30G */
+					<0x00000480 0x81600006 0xc1f03e1f>,
+					/* DMI_SDRAM_480G */
+					<0x000004a0 0x81a00006 0xc1f03e1f>;
+				bootph-all;
+			};
+
+			/* DCE0 */
+			i_ccu_dce0@1c005000 {
+				reg = <0x1c005000 0x00001000>;
+				intel,offset-settings =
+					/* DCEUAMIGR0 */
+					<0x000003c0 0x00000001 0x0000001f>,
+					/* DMI_SDRAM_2G */
+					<0x00000460 0x81200006 0xc1f03e1f>,
+					/* DMI_SDRAM_30G */
+					<0x00000480 0x81600006 0xc1f03e1f>,
+					/* DMI_SDRAM_480G */
+					<0x000004a0 0x81a00006 0xc1f03e1f>;
+				bootph-all;
+			};
+
+			/* DCE1 */
+			i_ccu_dce1@1c006000 {
+				reg = <0x1c006000 0x00001000>;
+				intel,offset-settings =
+					/* DCEUAMIGR1 */
+					<0x000003c0 0x00000001 0x0000001f>,
+					/* DMI_SDRAM_2G */
+					<0x00000460 0x81200006 0xc1f03e1f>,
+					/* DMI_SDRAM_30G */
+					<0x00000480 0x81600006 0xc1f03e1f>,
+					/* DMI_SDRAM_480G */
+					<0x000004a0 0x81a00006 0xc1f03e1f>;
+				bootph-all;
+			};
+		};
+
+		socfpga_smmu_secure_config: socfpga-smmu-secure-config {
+			compatible = "intel,socfpga-dtreg";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			bootph-all;
+
+			/* System manager */
+			i_sys_mgt_sysmgr_csr@10d12000 {
+				reg = <0x10d12000 0x00000500>;
+				intel,offset-settings =
+					/* dma_tbu_stream_ctrl_reg_0_dma0 */
+					<0x0000017c 0x00000000 0x0000003f>,
+					/* dma_tbu_stream_ctrl_reg_0_dma1 */
+					<0x00000180 0x00000000 0x0000003f>,
+					/* sdm_tbu_stream_ctrl_reg_1_sdm */
+					<0x00000184 0x00000000 0x0000003f>,
+					/* io_tbu_stream_ctrl_reg_2_usb2 */
+					<0x00000188 0x00000000 0x0000003f>,
+					/* io_tbu_stream_ctrl_reg_2_sdmmc */
+					<0x00000190 0x00000000 0x0000003f>,
+					/* io_tbu_stream_ctrl_reg_2_nand */
+					<0x00000194 0x00000000 0x0000003f>,
+					/* io_tbu_stream_ctrl_reg_2_etr */
+					<0x00000198 0x00000000 0x0000003f>,
+					/* tsn_tbu_stream_ctrl_reg_3_tsn0 */
+					<0x0000019c 0x00000000 0x0000003f>,
+					/* tsn_tbu_stream_ctrl_reg_3_tsn1 */
+					<0x000001a0 0x00000000 0x0000003f>,
+					/* tsn_tbu_stream_ctrl_reg_3_tsn2 */
+					<0x000001a4 0x00000000 0x0000003f>;
+				bootph-all;
+			};
+		};
+
+		socfpga_noc_fw_mpfe_csr: socfpga-noc-fw-mpfe-csr {
+			compatible = "intel,socfpga-dtreg";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			bootph-all;
+
+			/* noc fw mpfe csr */
+			i_noc_fw_mpfe_csr@18000d00 {
+				reg = <0x18000d00 0x00000100>;
+				intel,offset-settings =
+					/* mpfe scr io96b0 reg*/
+					<0x00000000 0x00000001 0x00010101>,
+					/* mpfe scr io96b1 reg*/
+					<0x00000004 0x00000001 0x00010101>,
+					/* mpfe scr noc csr*/
+					<0x00000008 0x00000001 0x00010101>;
+				bootph-all;
+			};
+		};
+	};
 };
 
 &clkmgr {
@@ -57,6 +711,13 @@
 	bootph-all;
 };
 
+&sdr {
+	compatible = "intel,sdr-ctl-agilex5";
+	reg = <0x18000000 0x400000>;
+	resets = <&rst DDRSCH_RESET>;
+	bootph-all;
+};
+
 &sysmgr {
 	compatible = "altr,sys-mgr", "syscon";
 	bootph-all;
diff --git a/arch/arm/dts/socfpga_agilex5.dtsi b/arch/arm/dts/socfpga_agilex5.dtsi
index 03b55040497..86322d7b0ce 100644
--- a/arch/arm/dts/socfpga_agilex5.dtsi
+++ b/arch/arm/dts/socfpga_agilex5.dtsi
@@ -1,6 +1,7 @@
 // SPDX-License-Identifier:     GPL-2.0
 /*
  * Copyright (C) 2024 Intel Corporation <www.intel.com>
+ * Copyright (C) 2025 Altera Corporation <www.altera.com>
  */
 
 /dts-v1/;
@@ -330,6 +331,20 @@
 			status = "disabled";
 		};
 
+		nand: nand@10b80000 {
+			compatible = "cdns,nand";
+			reg = <0x10b80000 0x10000>,
+				<0x10840000 0x1000>;
+			reg-names = "reg", "sdma";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			interrupts = <0 97 4>;
+			clocks = <&clkmgr AGILEX5_NAND_CLK>;
+			resets = <&rst NAND_RESET>, <&rst COMBOPHY_RESET>;
+			cdns,board-delay-ps = <4830>;
+			status = "disabled";
+		};
+
 		ocram: sram@00000000 {
 			compatible = "mmio-sram";
 			reg = <0x00000000 0x200000>;
@@ -544,6 +559,13 @@
 			status = "disabled";
 		};
 
+		sdr: sdr@18000000 {
+			compatible = "intel,sdr-ctl-agilex5";
+			reg = <0x18000000 0x400000>;
+			resets = <&rst DDRSCH_RESET>;
+			bootph-all;
+		};
+
 		/* QSPI address not available yet */
 		qspi: spi@108d2000 {
 			compatible = "cdns,qspi-nor";
diff --git a/arch/arm/dts/socfpga_agilex5_socdk-u-boot.dtsi b/arch/arm/dts/socfpga_agilex5_socdk-u-boot.dtsi
index 9eb21d65428..d7ab58267eb 100644
--- a/arch/arm/dts/socfpga_agilex5_socdk-u-boot.dtsi
+++ b/arch/arm/dts/socfpga_agilex5_socdk-u-boot.dtsi
@@ -3,6 +3,7 @@
  * U-Boot additions
  *
  * Copyright (C) 2024 Intel Corporation <www.intel.com>
+ * Copyright (C) 2025 Altera Corporation <www.altera.com>
  */
 
 #include "socfpga_agilex5-u-boot.dtsi"
@@ -21,11 +22,38 @@
 		};
 	};
 
-	memory {
-		/* 8GB */
-		reg = <0 0x80000000 0 0x80000000>,
-		      <8 0x80000000 1 0x80000000>;
-	};
+	/*
+	 * Both Memory base address and size default info is retrieved from HW setting.
+	 * Reconfiguration / Overwrite these info can be done with examples below.
+	 */
+	/*
+	 * Example for memory size with 2GB:
+	 * memory {
+	 *	reg = <0x0 0x80000000 0x0 0x80000000>;
+	 * };
+	 */
+	/*
+	 * Example for memory size with 8GB:
+	 * memory {
+	 *	reg = <0x0 0x80000000 0x0 0x80000000>,
+	 *	      <0x8 0x80000000 0x1 0x80000000>;
+	 * };
+	 */
+	/*
+	 * Example for memory size with 32GB:
+	 * memory {
+	 *	reg = <0x0 0x80000000 0x0 0x80000000>,
+	 *	      <0x8 0x80000000 0x7 0x80000000>;
+	 * };
+	 */
+	/*
+	 * Example for memory size with 512GB:
+	 * memory {
+	 *	reg = <0x0 0x80000000 0x0 0x80000000>,
+	 *	      <0x8 0x80000000 0x7 0x80000000>,
+	 *	      <0x88 0x00000000 0x78 0x00000000>;
+	 * };
+	 */
 
 	chosen {
 		stdout-path = "serial0:115200n8";
@@ -41,6 +69,10 @@
 	/delete-property/ cdns,read-delay;
 };
 
+&flash1 {
+	bootph-all;
+};
+
 &i3c0 {
 	bootph-all;
 };
@@ -102,6 +134,10 @@
 	status = "okay";
 };
 
+&nand {
+	bootph-all;
+};
+
 &timer0 {
 	bootph-all;
 };
@@ -122,3 +158,36 @@
 	bootph-all;
 };
 
+&gmac0 {
+	status = "okay";
+	phy-mode = "rgmii";
+	phy-handle = <&emac0_phy0>;
+
+	max-frame-size = <9000>;
+
+	mdio0 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "snps,dwxgmac-mdio";
+		emac0_phy0: ethernet-phy@0 {
+			reg = <0>;
+		};
+	};
+};
+
+&gmac2 {
+	status = "okay";
+	phy-mode = "rgmii";
+	phy-handle = <&emac2_phy0>;
+
+	max-frame-size = <9000>;
+
+	mdio0 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "snps,dwxgmac-mdio";
+		emac2_phy0: ethernet-phy@0 {
+			reg = <0>;
+		};
+	};
+};
diff --git a/arch/arm/dts/socfpga_agilex5_socdk.dts b/arch/arm/dts/socfpga_agilex5_socdk.dts
index 852e1e5ae3c..2ab143e38f8 100644
--- a/arch/arm/dts/socfpga_agilex5_socdk.dts
+++ b/arch/arm/dts/socfpga_agilex5_socdk.dts
@@ -62,6 +62,10 @@
 	status = "okay";
 };
 
+&i2c3 {
+	status = "okay";
+};
+
 &i3c0 {
 	status = "okay";
 };
@@ -161,3 +165,22 @@
 		};
 	};
 };
+
+&nand {
+	status = "okay";
+
+	flash1: flash@0 {
+		reg = <0>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		partition@0 {
+			label = "u-boot";
+			reg = <0 0x200000>;
+		};
+		partition@200000 {
+			label = "root";
+			reg = <0x200000 0x3fe00000>;
+		};
+	};
+};
diff --git a/arch/arm/dts/stm32746g-eval-u-boot.dtsi b/arch/arm/dts/stm32746g-eval-u-boot.dtsi
index 1c288acec99..32b5c7cea4b 100644
--- a/arch/arm/dts/stm32746g-eval-u-boot.dtsi
+++ b/arch/arm/dts/stm32746g-eval-u-boot.dtsi
@@ -22,16 +22,6 @@
 		mmc0 = &sdio1;
 		spi0 = &qspi;
 	};
-
-	button1 {
-		compatible = "st,button1";
-		button-gpio = <&gpioc 13 0>;
-	};
-
-	led1 {
-		compatible = "st,led1";
-		led-gpio = <&gpiof 10 0>;
-	};
 };
 
 &fmc {
diff --git a/arch/arm/dts/stm32f746-disco-u-boot.dtsi b/arch/arm/dts/stm32f746-disco-u-boot.dtsi
index 1b42d6cbbc1..38d797e49a0 100644
--- a/arch/arm/dts/stm32f746-disco-u-boot.dtsi
+++ b/arch/arm/dts/stm32f746-disco-u-boot.dtsi
@@ -22,16 +22,6 @@
 		mmc0 = &sdio1;
 		spi0 = &qspi;
 	};
-
-	button1 {
-		compatible = "st,button1";
-		button-gpio = <&gpioi 11 0>;
-	};
-
-	led1 {
-		compatible = "st,led1";
-		led-gpio = <&gpioi 1 0>;
-	};
 };
 
 &ltdc {
diff --git a/arch/arm/dts/stm32f769-disco-u-boot.dtsi b/arch/arm/dts/stm32f769-disco-u-boot.dtsi
index add55c96e21..7c99a6e61b6 100644
--- a/arch/arm/dts/stm32f769-disco-u-boot.dtsi
+++ b/arch/arm/dts/stm32f769-disco-u-boot.dtsi
@@ -23,16 +23,6 @@
 		spi0 = &qspi;
 	};
 
-	button1 {
-		compatible = "st,button1";
-		button-gpio = <&gpioa 0 0>;
-	};
-
-	led1 {
-		compatible = "st,led1";
-		led-gpio = <&gpioj 5 0>;
-	};
-
 	panel: panel {
 		compatible = "orisetech,otm8009a";
 		reset-gpios = <&gpioj 15 1>;
diff --git a/arch/arm/dts/stm32mp13-pinctrl.dtsi b/arch/arm/dts/stm32mp13-pinctrl.dtsi
index c01d39f03ea..52c2a9f24d7 100644
--- a/arch/arm/dts/stm32mp13-pinctrl.dtsi
+++ b/arch/arm/dts/stm32mp13-pinctrl.dtsi
@@ -215,6 +215,21 @@
 		};
 	};
 
+	pwm1_ch3n_pins_a: pwm1-ch3n-0 {
+		pins {
+			pinmux = <STM32_PINMUX('E', 12, AF1)>; /* TIM1_CH3N */
+			bias-pull-down;
+			drive-push-pull;
+			slew-rate = <0>;
+		};
+	};
+
+	pwm1_ch3n_sleep_pins_a: pwm1-ch3n-sleep-0 {
+		pins {
+			pinmux = <STM32_PINMUX('E', 12, ANALOG)>; /* TIM1_CH3N */
+		};
+	};
+
 	pwm3_pins_a: pwm3-0 {
 		pins {
 			pinmux = <STM32_PINMUX('B', 1, AF2)>; /* TIM3_CH4 */
diff --git a/arch/arm/dts/stm32mp135f-dhcor-dhsbc-u-boot.dtsi b/arch/arm/dts/stm32mp135f-dhcor-dhsbc-u-boot.dtsi
index d718aae16ca..eace94f5fa4 100644
--- a/arch/arm/dts/stm32mp135f-dhcor-dhsbc-u-boot.dtsi
+++ b/arch/arm/dts/stm32mp135f-dhcor-dhsbc-u-boot.dtsi
@@ -23,3 +23,25 @@
 &usbphyc {
 	bootph-all;
 };
+
+&st33htph {
+	reset-gpios = <&gpioe 12 GPIO_ACTIVE_LOW>;
+};
+
+/* LDO2 is expansion connector 3V3 supply on STM32MP13xx DHCOR DHSBC rev.200 */
+&vdd_ldo2 {
+	bootph-all;
+	regulator-always-on;
+	regulator-boot-on;
+	regulator-min-microvolt = <3300000>;
+	regulator-max-microvolt = <3300000>;
+};
+
+/* LDO5 is carrier board 3V3 supply on STM32MP13xx DHCOR DHSBC rev.200 */
+&vdd_sd {
+	bootph-all;
+	regulator-always-on;
+	regulator-boot-on;
+	regulator-min-microvolt = <3300000>;
+	regulator-max-microvolt = <3300000>;
+};
diff --git a/arch/arm/dts/stm32mp135f-dk.dts b/arch/arm/dts/stm32mp135f-dk.dts
index eea740d097c..275823da3c6 100644
--- a/arch/arm/dts/stm32mp135f-dk.dts
+++ b/arch/arm/dts/stm32mp135f-dk.dts
@@ -9,6 +9,7 @@
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
 #include <dt-bindings/leds/common.h>
+#include <dt-bindings/pwm/pwm.h>
 #include <dt-bindings/regulator/st,stm32mp13-regulator.h>
 #include "stm32mp135.dtsi"
 #include "stm32mp13xf.dtsi"
@@ -207,6 +208,19 @@
 	status = "disabled";
 };
 
+&timers1 {
+	/* spare dmas for other usage */
+	/delete-property/dmas;
+	/delete-property/dma-names;
+	status = "okay";
+	pwm1: pwm {
+		pinctrl-0 = <&pwm1_ch3n_pins_a>;
+		pinctrl-1 = <&pwm1_ch3n_sleep_pins_a>;
+		pinctrl-names = "default", "sleep";
+		status = "okay";
+	};
+};
+
 &timers3 {
 	/delete-property/dmas;
 	/delete-property/dma-names;
diff --git a/arch/arm/dts/stm32mp13xx-dhcor-u-boot.dtsi b/arch/arm/dts/stm32mp13xx-dhcor-u-boot.dtsi
index 30e3b91bccc..9ff42ab8248 100644
--- a/arch/arm/dts/stm32mp13xx-dhcor-u-boot.dtsi
+++ b/arch/arm/dts/stm32mp13xx-dhcor-u-boot.dtsi
@@ -13,6 +13,8 @@
 	config {
 		dh,ddr3-coding-gpios = <&gpiod 5 0>, <&gpiod 9 0>;
 		dh,som-coding-gpios = <&gpioa 13 0>, <&gpioi 1 0>;
+		u-boot,mmc-env-offset = <0x3fc000>;
+		u-boot,mmc-env-offset-redundant = <0x3fc000>;
 	};
 };
 
diff --git a/arch/arm/dts/tegra124-xiaomi-mocha.dts b/arch/arm/dts/tegra124-xiaomi-mocha.dts
new file mode 100644
index 00000000000..64386f2b7b7
--- /dev/null
+++ b/arch/arm/dts/tegra124-xiaomi-mocha.dts
@@ -0,0 +1,592 @@
+// SPDX-License-Identifier: GPL-2.0
+/dts-v1/;
+
+#include <dt-bindings/input/input.h>
+#include "tegra124.dtsi"
+
+/ {
+	model = "Xiaomi Mi Pad A0101";
+	compatible = "xiaomi,mocha", "nvidia,tegra124";
+
+	chosen {
+		stdout-path = &uartd;
+	};
+
+	aliases {
+		i2c0 = &pwr_i2c;
+		i2c1 = &gen1_i2c;
+
+		mmc0 = &sdmmc4; /* eMMC */
+		mmc1 = &sdmmc3; /* uSD slot */
+
+		usb0 = &usb1;
+	};
+
+	memory {
+		device_type = "memory";
+		reg = <0x80000000 0x80000000>;
+	};
+
+	host1x@50000000 {
+		dsia: dsi@54300000 {
+			status = "okay";
+
+			avdd-dsi-csi-supply = <&avdd_dsi_csi>;
+			nvidia,ganged-mode = <&dsib>;
+
+			panel@0 {
+				compatible = "sharp,lq079l1sx01";
+				reg = <0>;
+
+				link2 = <&panel_secondary>;
+
+				avdd-supply = <&avdd_lcd>;
+				vddio-supply = <&vdd_lcd_io>;
+
+				vsp-supply = <&vsp_5v5_lcd>;
+				vsn-supply = <&vsn_5v5_lcd>;
+
+				reset-gpios = <&gpio TEGRA_GPIO(H, 3) GPIO_ACTIVE_LOW>;
+
+				backlight = <&lp8556>;
+			};
+		};
+
+		dsib: dsi@54400000 {
+			status = "okay";
+
+			avdd-dsi-csi-supply = <&avdd_dsi_csi>;
+
+			panel_secondary: panel@0 {
+				compatible = "sharp,lq079l1sx01";
+				reg = <0>;
+			};
+		};
+	};
+
+	pinmux@70000868 {
+		pinctrl-names = "default";
+		pinctrl-0 = <&state_default>;
+
+		state_default: pinmux {
+			/* Keys pinmux */
+			keys {
+				nvidia,pins = "kb_col0_pq0",
+						"kb_col6_pq6",
+						"kb_col7_pq7";
+				nvidia,function = "rsvd2";
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+			hall-front {
+				nvidia,pins = "pi5";
+				nvidia,function = "gmi";
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+			hall-back {
+				nvidia,pins = "gpio_w3_aud_pw3";
+				nvidia,function = "spi1";
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+
+			/* Leds pinmux */
+			bl-en {
+				nvidia,pins = "pbb4";
+				nvidia,function = "vgp4";
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+			keys-led {
+				nvidia,pins = "ph1";
+				nvidia,function = "pwm1";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			/* Panel pinmux */
+			lcd-rst {
+				nvidia,pins = "ph3";
+				nvidia,function = "gmi";
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+			lcd-vsp {
+				nvidia,pins = "pi4";
+				nvidia,function = "gmi";
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+			lcd-vsn {
+				nvidia,pins = "kb_row10_ps2";
+				nvidia,function = "kbc";
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+			lcd-id {
+				nvidia,pins = "kb_row6_pr6";
+				nvidia,function = "displaya_alt";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+			lcd-pwm {
+				nvidia,pins = "ph2";
+				nvidia,function = "pwm2";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			/* SDMMC3 pinmux */
+			sdmmc3-clk {
+				nvidia,pins = "sdmmc3_clk_pa6";
+				nvidia,function = "sdmmc3";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+			sdmmc3-cmd {
+				nvidia,pins = "sdmmc3_cmd_pa7",
+						"sdmmc3_dat0_pb7",
+						"sdmmc3_dat1_pb6",
+						"sdmmc3_dat2_pb5",
+						"sdmmc3_dat3_pb4",
+						"sdmmc3_clk_lb_out_pee4",
+						"sdmmc3_clk_lb_in_pee5";
+				nvidia,function = "sdmmc3";
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+			sdmmc3-cd {
+				nvidia,pins = "sdmmc3_cd_n_pv2";
+				nvidia,function = "sdmmc3";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+			usd-pwr {
+				nvidia,pins = "kb_row0_pr0";
+				nvidia,function = "rsvd4";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			/* SDMMC4 pinmux */
+			sdmmc4-clk {
+				nvidia,pins = "sdmmc4_clk_pcc4";
+				nvidia,function = "sdmmc4";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+			sdmmc4-cmd {
+				nvidia,pins = "sdmmc4_cmd_pt7",
+						"sdmmc4_dat0_paa0",
+						"sdmmc4_dat1_paa1",
+						"sdmmc4_dat2_paa2",
+						"sdmmc4_dat3_paa3",
+						"sdmmc4_dat4_paa4",
+						"sdmmc4_dat5_paa5",
+						"sdmmc4_dat6_paa6",
+						"sdmmc4_dat7_paa7";
+				nvidia,function = "sdmmc4";
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+
+			/* I2C pinmux */
+			gen1-i2c {
+				nvidia,pins = "gen1_i2c_sda_pc5",
+						"gen1_i2c_scl_pc4";
+				nvidia,function = "i2c1";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+				nvidia,lock = <TEGRA_PIN_DISABLE>;
+				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
+			};
+			gen2-i2c {
+				nvidia,pins = "gen2_i2c_scl_pt5",
+						"gen2_i2c_sda_pt6";
+				nvidia,function = "i2c2";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+				nvidia,lock = <TEGRA_PIN_DISABLE>;
+				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
+			};
+			cam-i2c {
+				nvidia,pins = "cam_i2c_scl_pbb1",
+						"cam_i2c_sda_pbb2";
+				nvidia,function = "i2c3";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+				nvidia,lock = <TEGRA_PIN_DISABLE>;
+				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
+			};
+			ddc-i2c {
+				nvidia,pins = "ddc_scl_pv4",
+						"ddc_sda_pv5";
+				nvidia,function = "i2c4";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+			pwr-i2c {
+				nvidia,pins = "pwr_i2c_scl_pz6",
+						"pwr_i2c_sda_pz7";
+				nvidia,function = "i2cpwr";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
+			};
+
+			dsi-b {
+				nvidia,pins = "mipi_pad_ctrl_dsi_b";
+				nvidia,function = "dsi_b";
+			};
+
+			/* GPIO power/drive control */
+			drive-sdio1 {
+				nvidia,pins = "drive_sdio1";
+				nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>;
+				nvidia,schmitt = <TEGRA_PIN_DISABLE>;
+				nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>;
+				nvidia,pull-down-strength = <32>;
+				nvidia,pull-up-strength = <42>;
+				nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>;
+				nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>;
+			};
+
+			drive-sdio3 {
+				nvidia,pins = "drive_sdio3";
+				nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>;
+				nvidia,schmitt = <TEGRA_PIN_DISABLE>;
+				nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>;
+				nvidia,pull-down-strength = <20>;
+				nvidia,pull-up-strength = <36>;
+				nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>;
+				nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>;
+			};
+
+			drive-gma {
+				nvidia,pins = "drive_gma";
+				nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>;
+				nvidia,schmitt = <TEGRA_PIN_DISABLE>;
+				nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>;
+				nvidia,pull-down-strength = <1>;
+				nvidia,pull-up-strength = <2>;
+				nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>;
+				nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>;
+			};
+		};
+	};
+
+	uartd: serial@70006300 {
+		status = "okay";
+	};
+
+	gen1_i2c: i2c@7000c000 {
+		status = "okay";
+		clock-frequency = <400000>;
+
+		lp8556: backlight@2c {
+			compatible = "ti,lp8556";
+			reg = <0x2c>;
+
+			dev-ctrl = /bits/ 8 <0x83>;
+			init-brt = /bits/ 8 <0x1f>;
+
+			power-supply = <&vdd_3v3_sys>;
+			enable-supply = <&vddio_1v8_bl>;
+
+			rom-98h {
+				rom-addr = /bits/ 8 <0x98>;
+				rom-val = /bits/ 8 <0x80>;
+			};
+
+			rom-9eh {
+				rom-addr = /bits/ 8 <0x9e>;
+				rom-val = /bits/ 8 <0x21>;
+			};
+
+			rom-a0h {
+				rom-addr = /bits/ 8 <0xa0>;
+				rom-val = /bits/ 8 <0xff>;
+			};
+
+			rom-a1h {
+				rom-addr = /bits/ 8 <0xa1>;
+				rom-val = /bits/ 8 <0x3f>;
+			};
+
+			rom-a2h {
+				rom-addr = /bits/ 8 <0xa2>;
+				rom-val = /bits/ 8 <0x20>;
+			};
+
+			rom-a3h {
+				rom-addr = /bits/ 8 <0xa3>;
+				rom-val = /bits/ 8 <0x00>;
+			};
+
+			rom-a4h {
+				rom-addr = /bits/ 8 <0xa4>;
+				rom-val = /bits/ 8 <0x72>;
+			};
+
+			rom-a5h {
+				rom-addr = /bits/ 8 <0xa5>;
+				rom-val = /bits/ 8 <0x24>;
+			};
+
+			rom-a6h {
+				rom-addr = /bits/ 8 <0xa6>;
+				rom-val = /bits/ 8 <0x80>;
+			};
+
+			rom-a7h {
+				rom-addr = /bits/ 8 <0xa7>;
+				rom-val = /bits/ 8 <0xf5>;
+			};
+
+			rom-a8h {
+				rom-addr = /bits/ 8 <0xa8>;
+				rom-val = /bits/ 8 <0x24>;
+			};
+
+			rom-a9h {
+				rom-addr = /bits/ 8 <0xa9>;
+				rom-val = /bits/ 8 <0xb2>;
+			};
+
+			rom-aah {
+				rom-addr = /bits/ 8 <0xaa>;
+				rom-val = /bits/ 8 <0x8f>;
+			};
+
+			rom-aeh {
+				rom-addr = /bits/ 8 <0xae>;
+				rom-val = /bits/ 8 <0x0f>;
+			};
+		};
+	};
+
+	pwr_i2c: i2c@7000d000 {
+		status = "okay";
+		clock-frequency = <400000>;
+
+		/* Texas Instruments TPS65913 PMIC */
+		pmic: tps65913@58 {
+			compatible = "ti,tps65913";
+			reg = <0x58>;
+
+			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
+			#interrupt-cells = <2>;
+			interrupt-controller;
+
+			ti,system-power-controller;
+
+			palmas_gpio: gpio {
+				compatible = "ti,palmas-gpio";
+				gpio-controller;
+				#gpio-cells = <2>;
+			};
+
+			pinmux {
+				compatible = "ti,tps65913-pinctrl";
+
+				pinctrl-names = "default";
+				pinctrl-0 = <&palmas_default>;
+
+				palmas_default: pinmux {
+					pin_gpio4 {
+						pins = "gpio4";
+						function = "gpio";
+					};
+				};
+			};
+
+			pmic {
+				compatible = "ti,tps65913-pmic";
+
+				regulators {
+					vdd_1v8_vio: smps8 {
+						regulator-name = "vdd_1v8_gen";
+						regulator-min-microvolt = <1800000>;
+						regulator-max-microvolt = <1800000>;
+						regulator-always-on;
+						regulator-boot-on;
+					};
+
+					vdd_hv_sdmmc: smps9 {
+						regulator-name = "vdd_hv_sdmmc";
+						regulator-min-microvolt = <3300000>;
+						regulator-max-microvolt = <3300000>;
+						regulator-always-on;
+						regulator-boot-on;
+					};
+
+					avdd_lcd: ldo2 {
+						regulator-name = "avdd_lcd";
+						regulator-min-microvolt = <1800000>;
+						regulator-max-microvolt = <1800000>;
+						regulator-boot-on;
+					};
+
+					avdd_dsi_csi: ldo5 {
+						regulator-name = "avdd_dsi_csi";
+						regulator-min-microvolt = <1200000>;
+						regulator-max-microvolt = <1200000>;
+						regulator-boot-on;
+					};
+
+					vddio_usd: ldo9 {
+						regulator-name = "vddio_sdmmc";
+						regulator-min-microvolt = <3300000>;
+						regulator-max-microvolt = <3300000>;
+						regulator-always-on;
+						regulator-boot-on;
+					};
+
+					avdd_usb: ldousb {
+						regulator-name = "vdd_usb";
+						regulator-min-microvolt = <3300000>;
+						regulator-max-microvolt = <3300000>;
+						regulator-always-on;
+						regulator-boot-on;
+					};
+				};
+			};
+		};
+	};
+
+	sdmmc3: sdhci@700b0400 {
+		status = "okay";
+		bus-width = <4>;
+
+		cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>;
+		power-gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>;
+
+		vmmc-supply = <&vdd_hv_sdmmc>;
+		vqmmc-supply = <&vddio_usd>;
+	};
+
+	sdmmc4: sdhci@700b0600 {
+		status = "okay";
+		bus-width = <8>;
+		non-removable;
+
+		vmmc-supply = <&vdd_hv_sdmmc>;
+		vqmmc-supply = <&vdd_1v8_vio>;
+	};
+
+	usb1: usb@7d000000 {
+		status = "okay";
+		dr_mode = "otg";
+	};
+
+	clk32k_in: clock-32k {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <32768>;
+		clock-output-names = "ref-oscillator";
+	};
+
+	extcon-keys {
+		compatible = "gpio-keys";
+
+		switch-back-hall-sensor {
+			label = "Hall sensor (back)";
+			gpios = <&gpio TEGRA_GPIO(W, 3) GPIO_ACTIVE_LOW>;
+			linux,code = <SW_LID>;
+		};
+
+		switch-front-hall-sensor {
+			label = "Hall sensor (front)";
+			gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
+			linux,code = <SW_LID>;
+		};
+	};
+
+	gpio-keys {
+		compatible = "gpio-keys";
+
+		key-power {
+			label = "Power";
+			gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_ENTER>;
+		};
+
+		key-volume-down {
+			label = "Volume Down";
+			gpios = <&gpio TEGRA_GPIO(Q, 7) GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_DOWN>;
+		};
+
+		key-volume-up {
+			label = "Volume Up";
+			gpios = <&gpio TEGRA_GPIO(Q, 6) GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_UP>;
+		};
+	};
+
+	vdd_3v3_sys: regulator-bl-en {
+		compatible = "regulator-fixed";
+		regulator-name = "vdd_5v0_bl";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		enable-active-high;
+	};
+
+	vddio_1v8_bl: regulator-bl-io {
+		compatible = "regulator-fixed";
+		regulator-name = "vddio_1v8_bl";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+		enable-active-high;
+		gpio = <&gpio TEGRA_GPIO(BB, 4) GPIO_ACTIVE_HIGH>;
+	};
+
+	vdd_lcd_io: regulator-lcdvio {
+		compatible = "regulator-fixed";
+		regulator-name = "dvdd_lcd";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+		enable-active-high;
+		gpio = <&palmas_gpio 4 GPIO_ACTIVE_HIGH>;
+	};
+
+	vsp_5v5_lcd: regulator-vsp {
+		compatible = "regulator-fixed";
+		regulator-name = "avdd_lcd_vsp";
+		regulator-min-microvolt = <5500000>;
+		regulator-max-microvolt = <5500000>;
+		enable-active-high;
+		gpio = <&gpio TEGRA_GPIO(I, 4) GPIO_ACTIVE_HIGH>;
+	};
+
+	vsn_5v5_lcd: regulator-vsn {
+		compatible = "regulator-fixed";
+		regulator-name = "avdd_lcd_vsn";
+		regulator-min-microvolt = <5500000>;
+		regulator-max-microvolt = <5500000>;
+		enable-active-high;
+		gpio = <&gpio TEGRA_GPIO(S, 2) GPIO_ACTIVE_HIGH>;
+	};
+};
diff --git a/arch/arm/dts/tegra20-u-boot.dtsi b/arch/arm/dts/tegra20-u-boot.dtsi
index fa582bcb9fd..b74aa5bb0d4 100644
--- a/arch/arm/dts/tegra20-u-boot.dtsi
+++ b/arch/arm/dts/tegra20-u-boot.dtsi
@@ -9,5 +9,9 @@
 		dc@54200000 {
 			bootph-all;
 		};
+
+		dc@54240000 {
+			bootph-all;
+		};
 	};
 };
diff --git a/arch/arm/dts/tegra30-asus-p1801-t.dts b/arch/arm/dts/tegra30-asus-p1801-t.dts
index 243ff2bda26..58f1499cb92 100644
--- a/arch/arm/dts/tegra30-asus-p1801-t.dts
+++ b/arch/arm/dts/tegra30-asus-p1801-t.dts
@@ -34,20 +34,10 @@
 
 	host1x@50000000 {
 		dc@54200000 {
-			clocks = <&tegra_car TEGRA30_CLK_DISP1>,
-				 <&tegra_car TEGRA30_CLK_PLL_D_OUT0>;
-
-			rgb {
-				status = "okay";
-
-				nvidia,panel = <&hdmi>;
-			};
+			status = "disabled";
 		};
 
 		hdmi: hdmi@54280000 {
-			clocks = <&tegra_car TEGRA30_CLK_HDMI>,
-				 <&tegra_car TEGRA30_CLK_PLL_D_OUT0>;
-
 			status = "okay";
 
 			hdmi-supply = <&hdmi_5v0_sys>;
@@ -118,8 +108,8 @@
 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
-				nvidia,lock = <1>;
-				nvidia,io-reset = <1>;
+				nvidia,lock = <TEGRA_PIN_DISABLE>;
+				nvidia,io-reset = <TEGRA_PIN_DISABLE>;
 			};
 
 			/* SDMMC3 pinmux */
@@ -203,7 +193,7 @@
 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 				nvidia,open-drain = <TEGRA_PIN_ENABLE>;
-				nvidia,lock = <1>;
+				nvidia,lock = <TEGRA_PIN_DISABLE>;
 			};
 			gen2_i2c {
 				nvidia,pins = "gen2_i2c_scl_pt5",
@@ -213,7 +203,7 @@
 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 				nvidia,open-drain = <TEGRA_PIN_ENABLE>;
-				nvidia,lock = <1>;
+				nvidia,lock = <TEGRA_PIN_DISABLE>;
 			};
 			cam_i2c {
 				nvidia,pins = "cam_i2c_scl_pbb1",
@@ -223,7 +213,7 @@
 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 				nvidia,open-drain = <TEGRA_PIN_ENABLE>;
-				nvidia,lock = <1>;
+				nvidia,lock = <TEGRA_PIN_DISABLE>;
 			};
 			ddc_i2c {
 				nvidia,pins = "ddc_scl_pv4",
@@ -232,7 +222,7 @@
 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
-				nvidia,lock = <1>;
+				nvidia,lock = <TEGRA_PIN_DISABLE>;
 			};
 			pwr_i2c {
 				nvidia,pins = "pwr_i2c_scl_pz6",
@@ -242,7 +232,7 @@
 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 				nvidia,open-drain = <TEGRA_PIN_ENABLE>;
-				nvidia,lock = <1>;
+				nvidia,lock = <TEGRA_PIN_DISABLE>;
 			};
 			hotplug_i2c {
 				nvidia,pins = "pu4";
@@ -260,7 +250,7 @@
 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 				nvidia,open-drain = <TEGRA_PIN_ENABLE>;
-				nvidia,lock = <1>;
+				nvidia,lock = <TEGRA_PIN_DISABLE>;
 			};
 			hdmi_hpd {
 				nvidia,pins = "hdmi_int_pn7";
@@ -632,8 +622,8 @@
 				nvidia,pull = <TEGRA_PIN_PULL_UP>;
 				nvidia,tristate = <TEGRA_PIN_ENABLE>;
 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
-				nvidia,lock = <1>;
-				nvidia,io-reset = <1>;
+				nvidia,lock = <TEGRA_PIN_DISABLE>;
+				nvidia,io-reset = <TEGRA_PIN_DISABLE>;
 			};
 
 			/* GPIO keys pinmux */
@@ -718,8 +708,8 @@
 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
-				nvidia,lock = <1>;
-				nvidia,io-reset = <1>;
+				nvidia,lock = <TEGRA_PIN_DISABLE>;
+				nvidia,io-reset = <TEGRA_PIN_DISABLE>;
 			};
 			vi_d10_pt2 {
 				nvidia,pins = "vi_d10_pt2",
@@ -838,8 +828,8 @@
 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
-				nvidia,lock = <1>;
-				nvidia,io-reset = <1>;
+				nvidia,lock = <TEGRA_PIN_DISABLE>;
+				nvidia,io-reset = <TEGRA_PIN_DISABLE>;
 			};
 			vi_mclk_pt1 {
 				nvidia,pins = "vi_mclk_pt1";
diff --git a/arch/arm/dts/tegra30-asus-tf600t.dts b/arch/arm/dts/tegra30-asus-tf600t.dts
index 3ddd78b3df6..1b5729c65f4 100644
--- a/arch/arm/dts/tegra30-asus-tf600t.dts
+++ b/arch/arm/dts/tegra30-asus-tf600t.dts
@@ -90,8 +90,8 @@
 				nvidia,pull = <TEGRA_PIN_PULL_UP>;
 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
-				nvidia,lock = <1>;
-				nvidia,io-reset = <1>;
+				nvidia,lock = <TEGRA_PIN_DISABLE>;
+				nvidia,io-reset = <TEGRA_PIN_DISABLE>;
 			};
 
 			/* SDMMC2 pinmux */
@@ -107,8 +107,8 @@
 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
-				nvidia,lock = <1>;
-				nvidia,io-reset = <1>;
+				nvidia,lock = <TEGRA_PIN_DISABLE>;
+				nvidia,io-reset = <TEGRA_PIN_DISABLE>;
 			};
 
 			/* SDMMC3 pinmux */
@@ -142,8 +142,8 @@
 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
-				nvidia,lock = <1>;
-				nvidia,io-reset = <1>;
+				nvidia,lock = <TEGRA_PIN_DISABLE>;
+				nvidia,io-reset = <TEGRA_PIN_DISABLE>;
 			};
 			sdmmc4_cmd {
 				nvidia,pins = "sdmmc4_cmd_pt7",
@@ -159,8 +159,8 @@
 				nvidia,pull = <TEGRA_PIN_PULL_UP>;
 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
-				nvidia,lock = <1>;
-				nvidia,io-reset = <1>;
+				nvidia,lock = <TEGRA_PIN_DISABLE>;
+				nvidia,io-reset = <TEGRA_PIN_DISABLE>;
 			};
 			sdmmc4_rst_n {
 				nvidia,pins = "sdmmc4_rst_n_pcc3";
@@ -186,7 +186,7 @@
 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 				nvidia,open-drain = <TEGRA_PIN_ENABLE>;
-				nvidia,lock = <0>;
+				nvidia,lock = <TEGRA_PIN_DISABLE>;
 			};
 			gen2_i2c {
 				nvidia,pins = "gen2_i2c_scl_pt5",
@@ -196,7 +196,7 @@
 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 				nvidia,open-drain = <TEGRA_PIN_ENABLE>;
-				nvidia,lock = <0>;
+				nvidia,lock = <TEGRA_PIN_DISABLE>;
 			};
 			cam_i2c {
 				nvidia,pins = "cam_i2c_scl_pbb1",
@@ -206,7 +206,7 @@
 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 				nvidia,open-drain = <TEGRA_PIN_ENABLE>;
-				nvidia,lock = <0>;
+				nvidia,lock = <TEGRA_PIN_DISABLE>;
 			};
 			ddc_i2c {
 				nvidia,pins = "ddc_scl_pv4",
@@ -215,7 +215,7 @@
 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
-				nvidia,lock = <0>;
+				nvidia,lock = <TEGRA_PIN_DISABLE>;
 			};
 			pwr_i2c {
 				nvidia,pins = "pwr_i2c_scl_pz6",
@@ -225,7 +225,7 @@
 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 				nvidia,open-drain = <TEGRA_PIN_ENABLE>;
-				nvidia,lock = <0>;
+				nvidia,lock = <TEGRA_PIN_DISABLE>;
 			};
 			hotplug_i2c {
 				nvidia,pins = "pu4";
@@ -243,7 +243,7 @@
 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 				nvidia,open-drain = <TEGRA_PIN_ENABLE>;
-				nvidia,lock = <0>;
+				nvidia,lock = <TEGRA_PIN_DISABLE>;
 			};
 			hdmi_hpd {
 				nvidia,pins = "hdmi_int_pn7";
@@ -613,8 +613,8 @@
 				nvidia,pull = <TEGRA_PIN_PULL_UP>;
 				nvidia,tristate = <TEGRA_PIN_ENABLE>;
 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
-				nvidia,lock = <1>;
-				nvidia,io-reset = <1>;
+				nvidia,lock = <TEGRA_PIN_DISABLE>;
+				nvidia,io-reset = <TEGRA_PIN_DISABLE>;
 			};
 
 			/* GPIO keys pinmux */
@@ -701,8 +701,8 @@
 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
-				nvidia,lock = <1>;
-				nvidia,io-reset = <1>;
+				nvidia,lock = <TEGRA_PIN_DISABLE>;
+				nvidia,io-reset = <TEGRA_PIN_DISABLE>;
 			};
 			pbb0 {
 				nvidia,pins = "pbb0";
@@ -827,8 +827,8 @@
 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
-				nvidia,lock = <1>;
-				nvidia,io-reset = <1>;
+				nvidia,lock = <TEGRA_PIN_DISABLE>;
+				nvidia,io-reset = <TEGRA_PIN_DISABLE>;
 			};
 			vi_mclk_pt1 {
 				nvidia,pins = "vi_mclk_pt1";
@@ -836,8 +836,8 @@
 				nvidia,pull = <TEGRA_PIN_PULL_UP>;
 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
-				nvidia,lock = <1>;
-				nvidia,io-reset = <1>;
+				nvidia,lock = <TEGRA_PIN_DISABLE>;
+				nvidia,io-reset = <TEGRA_PIN_DISABLE>;
 			};
 
 			jtag {
diff --git a/arch/arm/dts/tegra30-asus-tf700t.dts b/arch/arm/dts/tegra30-asus-tf700t.dts
index 6dc760b90d6..47606ede9d6 100644
--- a/arch/arm/dts/tegra30-asus-tf700t.dts
+++ b/arch/arm/dts/tegra30-asus-tf700t.dts
@@ -15,7 +15,14 @@
 			rgb {
 				status = "okay";
 
-				nvidia,panel = <&tc358768>;
+				/delete-property/ nvidia,panel;
+
+				port {
+					dpi_output: endpoint {
+						remote-endpoint = <&bridge_input>;
+						bus-width = <24>;
+					};
+				};
 			};
 		};
 	};
@@ -118,38 +125,69 @@
 				vddio-supply = <&vdd_1v8_vio>;
 				vddmipi-supply = <&vdd_1v2_mipi>;
 
-				panel = <&panel>;
+				/*
+				 * Panasonic VVX10F004B00 or HYDIS HV101WU1-1E1
+				 * LCD SuperIPS+ Full HD panel.
+				 */
+				panel@1 {
+					compatible = "panasonic,vvx10f004b00";
+					reg = <1>;
+
+					power-supply = <&vdd_pnl_reg>;
+					backlight = <&backlight>;
+
+					display-timings {
+						timing@0 {
+							/* 1920x1200@60Hz */
+							clock-frequency = <154000000>;
+
+							hactive = <1920>;
+							hfront-porch = <48>;
+							hback-porch = <80>;
+							hsync-len = <32>;
+							hsync-active = <1>;
+
+							vactive = <1200>;
+							vfront-porch = <3>;
+							vback-porch = <26>;
+							vsync-len = <6>;
+							vsync-active = <1>;
+						};
+					};
+
+					port {
+						panel_input: endpoint {
+							remote-endpoint = <&bridge_output>;
+						};
+					};
+				};
+
+				ports {
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					port@0 {
+						reg = <0>;
+
+						bridge_input: endpoint {
+							remote-endpoint = <&dpi_output>;
+							bus-width = <24>;
+						};
+					};
+
+					port@1 {
+						reg = <1>;
+
+						bridge_output: endpoint {
+							remote-endpoint = <&panel_input>;
+						};
+					};
+				};
 			};
 		};
 	};
 
-	panel: panel {
-		compatible = "panasonic,vvx10f004b00";
-
-		power-supply = <&vdd_pnl_reg>;
-		backlight = <&backlight>;
-
-		/delete-property/ enable-gpios;
-
-		display-timings {
-			timing@0 {
-				/* 1920x1200@60Hz */
-				clock-frequency = <154000000>;
-
-				hactive = <1920>;
-				hfront-porch = <48>;
-				hback-porch = <80>;
-				hsync-len = <32>;
-				hsync-active = <1>;
-
-				vactive = <1200>;
-				vfront-porch = <3>;
-				vback-porch = <26>;
-				vsync-len = <6>;
-				vsync-active = <1>;
-			};
-		};
-	};
+	/delete-node/ panel;
 
 	vdd_1v2_mipi: regulator-mipi {
 		compatible = "regulator-fixed";
diff --git a/arch/arm/dts/tegra30-asus-transformer.dtsi b/arch/arm/dts/tegra30-asus-transformer.dtsi
index 03ba8fb9604..032fb3d00ac 100644
--- a/arch/arm/dts/tegra30-asus-transformer.dtsi
+++ b/arch/arm/dts/tegra30-asus-transformer.dtsi
@@ -99,8 +99,8 @@
 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
-				nvidia,lock = <1>;
-				nvidia,io-reset = <1>;
+				nvidia,lock = <TEGRA_PIN_DISABLE>;
+				nvidia,io-reset = <TEGRA_PIN_DISABLE>;
 			};
 
 			/* SDMMC3 pinmux */
@@ -189,7 +189,7 @@
 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 				nvidia,open-drain = <TEGRA_PIN_ENABLE>;
-				nvidia,lock = <1>;
+				nvidia,lock = <TEGRA_PIN_DISABLE>;
 			};
 
 			gen2_i2c {
@@ -200,7 +200,7 @@
 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 				nvidia,open-drain = <TEGRA_PIN_ENABLE>;
-				nvidia,lock = <1>;
+				nvidia,lock = <TEGRA_PIN_DISABLE>;
 			};
 
 			cam_i2c {
@@ -211,7 +211,7 @@
 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 				nvidia,open-drain = <TEGRA_PIN_ENABLE>;
-				nvidia,lock = <1>;
+				nvidia,lock = <TEGRA_PIN_DISABLE>;
 			};
 
 			ddc_i2c {
@@ -221,7 +221,7 @@
 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
-				nvidia,lock = <1>;
+				nvidia,lock = <TEGRA_PIN_DISABLE>;
 			};
 
 			pwr_i2c {
@@ -232,7 +232,7 @@
 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 				nvidia,open-drain = <TEGRA_PIN_ENABLE>;
-				nvidia,lock = <1>;
+				nvidia,lock = <TEGRA_PIN_DISABLE>;
 			};
 
 			hotplug_i2c {
@@ -647,8 +647,8 @@
 				nvidia,pull = <TEGRA_PIN_PULL_UP>;
 				nvidia,tristate = <TEGRA_PIN_ENABLE>;
 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
-				nvidia,lock = <1>;
-				nvidia,io-reset = <1>;
+				nvidia,lock = <TEGRA_PIN_DISABLE>;
+				nvidia,io-reset = <TEGRA_PIN_DISABLE>;
 			};
 
 			/* GPIO keys pinmux */
@@ -741,8 +741,8 @@
 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
-				nvidia,lock = <1>;
-				nvidia,io-reset = <1>;
+				nvidia,lock = <TEGRA_PIN_DISABLE>;
+				nvidia,io-reset = <TEGRA_PIN_DISABLE>;
 			};
 
 			vi_d10_pt2 {
@@ -879,8 +879,8 @@
 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
-				nvidia,lock = <1>;
-				nvidia,io-reset = <1>;
+				nvidia,lock = <TEGRA_PIN_DISABLE>;
+				nvidia,io-reset = <TEGRA_PIN_DISABLE>;
 			};
 
 			vi_mclk_pt1 {
diff --git a/arch/arm/dts/tegra30-htc-endeavoru.dts b/arch/arm/dts/tegra30-htc-endeavoru.dts
index dbff795bd89..db8ac457880 100644
--- a/arch/arm/dts/tegra30-htc-endeavoru.dts
+++ b/arch/arm/dts/tegra30-htc-endeavoru.dts
@@ -33,13 +33,11 @@
 
 	host1x@50000000 {
 		dc@54200000 {
-			clocks = <&tegra_car TEGRA30_CLK_DISP1>,
-				 <&tegra_car TEGRA30_CLK_PLL_D_OUT0>;
+			backlight: backlight {
+				compatible = "nvidia,tegra-pwm-backlight";
 
-			rgb {
-				status = "okay";
-
-				nvidia,panel = <&dsia>;
+				nvidia,pwm-source = <1>;
+				nvidia,default-brightness = <0x8E>;
 			};
 		};
 
@@ -48,7 +46,17 @@
 
 			avdd-dsi-csi-supply = <&avdd_dsi_csi>;
 
-			panel = <&panel>;
+			panel@0 {
+				compatible = "htc,edge-panel";
+				reg = <0>;
+
+				reset-gpios = <&gpio TEGRA_GPIO(N, 6) GPIO_ACTIVE_LOW>;
+
+				vdd-supply = <&vdd_3v3_panel>;
+				vddio-supply = <&vdd_1v8_panel>;
+
+				backlight = <&backlight>;
+			};
 		};
 	};
 
@@ -1255,13 +1263,6 @@
 		nvidia,xcvr-lsrslew = <2>;
 	};
 
-	backlight: backlight {
-		compatible = "nvidia,tegra-pwm-backlight";
-
-		nvidia,pwm-source = <1>;
-		nvidia,default-brightness = <0x8E>;
-	};
-
 	/* PMIC has a built-in 32KHz oscillator which is used by PMC */
 	clk32k_in: clock-32k {
 		compatible = "fixed-clock";
@@ -1292,17 +1293,6 @@
 		};
 	};
 
-	panel: panel {
-		compatible = "htc,edge-panel";
-
-		reset-gpios = <&gpio TEGRA_GPIO(N, 6) GPIO_ACTIVE_LOW>;
-
-		vdd-supply = <&vdd_3v3_panel>;
-		vddio-supply = <&vdd_1v8_panel>;
-
-		backlight = <&backlight>;
-	};
-
 	vcore_emmc: regulator-emmc {
 		compatible = "regulator-fixed";
 		regulator-name = "vdd_2v85_sdmmc";
diff --git a/arch/arm/dts/tegra30-lenovo-ideapad-yoga-11.dts b/arch/arm/dts/tegra30-lenovo-ideapad-yoga-11.dts
index 9a1e8c0601e..876fac7b661 100644
--- a/arch/arm/dts/tegra30-lenovo-ideapad-yoga-11.dts
+++ b/arch/arm/dts/tegra30-lenovo-ideapad-yoga-11.dts
@@ -109,8 +109,8 @@
 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
-				nvidia,lock = <1>;
-				nvidia,io-reset = <1>;
+				nvidia,lock = <TEGRA_PIN_DISABLE>;
+				nvidia,io-reset = <TEGRA_PIN_DISABLE>;
 			};
 			sdmmc4-cmd {
 				nvidia,pins = "sdmmc4_cmd_pt7",
@@ -127,8 +127,8 @@
 				nvidia,pull = <TEGRA_PIN_PULL_UP>;
 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
-				nvidia,lock = <1>;
-				nvidia,io-reset = <1>;
+				nvidia,lock = <TEGRA_PIN_DISABLE>;
+				nvidia,io-reset = <TEGRA_PIN_DISABLE>;
 			};
 			cam-mclk {
 				nvidia,pins = "cam_mclk_pcc0";
@@ -147,7 +147,7 @@
 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 				nvidia,open-drain = <TEGRA_PIN_ENABLE>;
-				nvidia,lock = <1>;
+				nvidia,lock = <TEGRA_PIN_DISABLE>;
 			};
 			gen2-i2c {
 				nvidia,pins = "gen2_i2c_scl_pt5",
@@ -157,7 +157,7 @@
 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 				nvidia,open-drain = <TEGRA_PIN_ENABLE>;
-				nvidia,lock = <1>;
+				nvidia,lock = <TEGRA_PIN_DISABLE>;
 			};
 			cam-i2c {
 				nvidia,pins = "cam_i2c_scl_pbb1",
@@ -167,7 +167,7 @@
 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 				nvidia,open-drain = <TEGRA_PIN_ENABLE>;
-				nvidia,lock = <1>;
+				nvidia,lock = <TEGRA_PIN_DISABLE>;
 			};
 			ddc-i2c {
 				nvidia,pins = "ddc_scl_pv4",
@@ -176,7 +176,7 @@
 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
-				nvidia,lock = <1>;
+				nvidia,lock = <TEGRA_PIN_DISABLE>;
 			};
 			pwr-i2c {
 				nvidia,pins = "pwr_i2c_scl_pz6",
@@ -186,7 +186,7 @@
 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 				nvidia,open-drain = <TEGRA_PIN_ENABLE>;
-				nvidia,lock = <1>;
+				nvidia,lock = <TEGRA_PIN_DISABLE>;
 			};
 
 			/* HDMI pinmux */
@@ -724,8 +724,8 @@
 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 				nvidia,tristate = <TEGRA_PIN_ENABLE>;
 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
-				nvidia,lock = <1>;
-				nvidia,io-reset = <1>;
+				nvidia,lock = <TEGRA_PIN_DISABLE>;
+				nvidia,io-reset = <TEGRA_PIN_DISABLE>;
 			};
 			vi-vsync-pd6 {
 				nvidia,pins = "vi_vsync_pd6",
@@ -736,8 +736,8 @@
 				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
 				nvidia,tristate = <TEGRA_PIN_ENABLE>;
 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
-				nvidia,lock = <1>;
-				nvidia,io-reset = <2>;
+				nvidia,lock = <TEGRA_PIN_DISABLE>;
+				nvidia,io-reset = <TEGRA_PIN_ENABLE>;
 			};
 			vi-hsync-pd7 {
 				nvidia,pins = "vi_hsync_pd7",
@@ -749,8 +749,8 @@
 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
-				nvidia,lock = <1>;
-				nvidia,io-reset = <1>;
+				nvidia,lock = <TEGRA_PIN_DISABLE>;
+				nvidia,io-reset = <TEGRA_PIN_DISABLE>;
 			};
 			vi-d2-pl0 {
 				nvidia,pins = "vi_d2_pl0",
@@ -760,8 +760,8 @@
 				nvidia,pull = <TEGRA_PIN_PULL_UP>;
 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
-				nvidia,lock = <1>;
-				nvidia,io-reset = <1>;
+				nvidia,lock = <TEGRA_PIN_DISABLE>;
+				nvidia,io-reset = <TEGRA_PIN_DISABLE>;
 			};
 			vi-mclk-pt1 {
 				nvidia,pins = "vi_mclk_pt1";
@@ -769,8 +769,8 @@
 				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
 				nvidia,tristate = <TEGRA_PIN_ENABLE>;
 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
-				nvidia,lock = <1>;
-				nvidia,io-reset = <2>;
+				nvidia,lock = <TEGRA_PIN_DISABLE>;
+				nvidia,io-reset = <TEGRA_PIN_ENABLE>;
 			};
 			vi-d11-pt3 {
 				nvidia,pins = "vi_d11_pt3";
@@ -778,8 +778,8 @@
 				nvidia,pull = <TEGRA_PIN_PULL_UP>;
 				nvidia,tristate = <TEGRA_PIN_ENABLE>;
 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
-				nvidia,lock = <1>;
-				nvidia,io-reset = <1>;
+				nvidia,lock = <TEGRA_PIN_DISABLE>;
+				nvidia,io-reset = <TEGRA_PIN_DISABLE>;
 			};
 			vi-d5-pl3 {
 				nvidia,pins = "vi_d5_pl3";
@@ -787,8 +787,8 @@
 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
-				nvidia,lock = <1>;
-				nvidia,io-reset = <1>;
+				nvidia,lock = <TEGRA_PIN_DISABLE>;
+				nvidia,io-reset = <TEGRA_PIN_DISABLE>;
 			};
 
 			/* PORT U */
diff --git a/arch/arm/dts/tegra30-lg-p880.dts b/arch/arm/dts/tegra30-lg-p880.dts
index 1d5ca1459bc..ab5993150b2 100644
--- a/arch/arm/dts/tegra30-lg-p880.dts
+++ b/arch/arm/dts/tegra30-lg-p880.dts
@@ -101,6 +101,31 @@
 		};
 	};
 
+	spi@7000dc00 {
+		bridge-spi@2 {
+			/*
+			 * JDI 4.57" 720x1280 DX12D100VM0EAA MIPI DSI panel
+			 */
+			panel@0 {
+				compatible = "jdi,dx12d100vm0eaa";
+				reg = <0>;
+
+				reset-gpios = <&gpio TEGRA_GPIO(W, 0) GPIO_ACTIVE_LOW>;
+
+				vdd-supply = <&vcc_3v0_lcd>;
+				vddio-supply = <&iovcc_1v8_lcd>;
+
+				backlight = <&backlight>;
+
+				port {
+					panel_input: endpoint {
+						remote-endpoint = <&bridge_output>;
+					};
+				};
+			};
+		};
+	};
+
 	sdmmc3: sdhci@78000400  {
 		status = "okay";
 		bus-width = <4>;
@@ -118,13 +143,4 @@
 			linux,code = <KEY_UP>;
 		};
 	};
-
-	panel: panel {
-		compatible = "jdi,dx12d100vm0eaa";
-
-		enable-gpios = <&gpio TEGRA_GPIO(Y, 0) GPIO_ACTIVE_HIGH>;
-		reset-gpios = <&gpio TEGRA_GPIO(W, 0) GPIO_ACTIVE_HIGH>;
-
-		backlight = <&backlight>;
-	};
 };
diff --git a/arch/arm/dts/tegra30-lg-p895.dts b/arch/arm/dts/tegra30-lg-p895.dts
index 43bb373a164..988e772172c 100644
--- a/arch/arm/dts/tegra30-lg-p895.dts
+++ b/arch/arm/dts/tegra30-lg-p895.dts
@@ -108,36 +108,37 @@
 		};
 	};
 
-	panel: panel {
-		compatible = "hitachi,tx13d100vm0eaa";
-
-		reset-gpios = <&gpio TEGRA_GPIO(W, 0) GPIO_ACTIVE_HIGH>;
-
-		renesas,gamma = <3>;
-		renesas,inversion;
-		renesas,contrast;
-
-		vcc-supply = <&vcc_3v0_lcd>;
-		iovcc-supply = <&iovcc_1v8_lcd>;
-
-		backlight = <&backlight>;
+	spi@7000dc00 {
+		bridge-spi@2 {
+			/*
+			 * HITACHI/KOE 5" 768x1024 TX13D100VM0EAA MIPI DSI panel
+			 */
+			panel@0 {
+				compatible = "koe,tx13d100vm0eaa";
+				reg = <0>;
+
+				reset-gpios = <&gpio TEGRA_GPIO(W, 0) GPIO_ACTIVE_LOW>;
+
+				renesas,gamma = <3>;
+				renesas,inversion;
+				renesas,contrast;
+
+				vcc-supply = <&vcc_3v0_lcd>;
+				iovcc-supply = <&iovcc_1v8_lcd>;
+
+				backlight = <&backlight>;
+
+				port {
+					panel_input: endpoint {
+						remote-endpoint = <&bridge_output>;
+					};
+				};
+			};
+		};
 	};
 
-	vcc_3v0_lcd: regulator-lcd {
-		compatible = "regulator-fixed";
-		regulator-name = "vcc_3v0_lcd";
-		regulator-min-microvolt = <3000000>;
-		regulator-max-microvolt = <3000000>;
+	regulator-lcd3v {
 		gpio = <&gpio TEGRA_GPIO(BB, 0) GPIO_ACTIVE_HIGH>;
 		enable-active-high;
 	};
-
-	iovcc_1v8_lcd: regulator-lcdvio {
-		compatible = "regulator-fixed";
-		regulator-name = "iovcc_1v8_lcd";
-		regulator-min-microvolt = <1800000>;
-		regulator-max-microvolt = <1800000>;
-		gpio = <&gpio TEGRA_GPIO(Y, 0) GPIO_ACTIVE_HIGH>;
-		enable-active-high;
-	};
 };
diff --git a/arch/arm/dts/tegra30-lg-x3.dtsi b/arch/arm/dts/tegra30-lg-x3.dtsi
index 30d6dcb6548..40b0ee07787 100644
--- a/arch/arm/dts/tegra30-lg-x3.dtsi
+++ b/arch/arm/dts/tegra30-lg-x3.dtsi
@@ -32,7 +32,12 @@
 			rgb {
 				status = "okay";
 
-				nvidia,panel = <&bridge>;
+				port {
+					dpi_output: endpoint {
+						remote-endpoint = <&bridge_input>;
+						bus-width = <24>;
+					};
+				};
 			};
 		};
 	};
@@ -890,12 +895,22 @@
 		status = "okay";
 		clock-frequency = <400000>;
 
-		backlight: lm3533@36 {
+		backlight: led-controller@36 {
 			compatible = "ti,lm3533";
 			reg = <0x36>;
 
 			enable-gpios = <&gpio TEGRA_GPIO(N, 6) GPIO_ACTIVE_HIGH>;
-			default-brightness-level = <128>;
+
+			ti,boost-ovp-microvolt = <24000000>;
+			ti,boost-freq-hz = <500000>;
+
+			backlight-0 {
+				compatible = "ti,lm3533-backlight";
+
+				ti,max-current-microamp = <23400>;
+				ti,linear-mapping-mode;
+				ti,hardware-controlled;
+			};
 		};
 
 		muic@44 {
@@ -969,18 +984,46 @@
 			compatible = "solomon,ssd2825";
 			reg = <2>;
 
+			#address-cells = <1>;
+			#size-cells = <0>;
+
 			spi-cpol;
 			spi-cpha;
 
 			spi-max-frequency = <1000000>;
 
-			power-gpios = <&gpio TEGRA_GPIO(B, 1) GPIO_ACTIVE_HIGH>;
-			reset-gpios = <&gpio TEGRA_GPIO(O, 2) GPIO_ACTIVE_HIGH>;
+			reset-gpios = <&gpio TEGRA_GPIO(O, 2) GPIO_ACTIVE_LOW>;
+
+			dvdd-supply = <&vdd_1v2_rgb>;
+			avdd-supply = <&vdd_1v2_rgb>;
+			vddio-supply = <&vdd_1v8_vio>;
+
+			solomon,hs-zero-delay-ns = <300>;
+			solomon,hs-prep-delay-ns = <65>;
 
 			clocks = <&ssd2825_refclk>;
-			clock-names = "tx_clk";
 
-			panel = <&panel>;
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					reg = <0>;
+
+					bridge_input: endpoint {
+						remote-endpoint = <&dpi_output>;
+						bus-width = <24>;
+					};
+				};
+
+				port@1 {
+					reg = <1>;
+
+					bridge_output: endpoint {
+						remote-endpoint = <&panel_input>;
+					};
+				};
+			};
 		};
 	};
 
@@ -1036,4 +1079,29 @@
 			linux,code = <KEY_DOWN>;
 		};
 	};
+
+	vdd_1v2_rgb: regulator-rgb1v2 {
+		compatible = "regulator-fixed";
+		regulator-name = "vdd_1v2_rgb";
+		regulator-min-microvolt = <1200000>;
+		regulator-max-microvolt = <1200000>;
+		gpio = <&gpio TEGRA_GPIO(B, 1) GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+	};
+
+	vcc_3v0_lcd: regulator-lcd3v {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc_3v0_lcd";
+		regulator-min-microvolt = <3000000>;
+		regulator-max-microvolt = <3000000>;
+	};
+
+	iovcc_1v8_lcd: regulator-lcd1v8 {
+		compatible = "regulator-fixed";
+		regulator-name = "iovcc_1v8_lcd";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+		gpio = <&gpio TEGRA_GPIO(Y, 0) GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+	};
 };
diff --git a/arch/arm/dts/tegra30-microsoft-surface-rt.dts b/arch/arm/dts/tegra30-microsoft-surface-rt.dts
index 6810350a90b..2d22d3e0bb1 100644
--- a/arch/arm/dts/tegra30-microsoft-surface-rt.dts
+++ b/arch/arm/dts/tegra30-microsoft-surface-rt.dts
@@ -103,8 +103,8 @@
 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
-				nvidia,lock = <1>;
-				nvidia,io-reset = <1>;
+				nvidia,lock = <TEGRA_PIN_DISABLE>;
+				nvidia,io-reset = <TEGRA_PIN_DISABLE>;
 			};
 			sdmmc4-cmd {
 				nvidia,pins = "sdmmc4_cmd_pt7",
@@ -121,8 +121,8 @@
 				nvidia,pull = <TEGRA_PIN_PULL_UP>;
 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
-				nvidia,lock = <1>;
-				nvidia,io-reset = <1>;
+				nvidia,lock = <TEGRA_PIN_DISABLE>;
+				nvidia,io-reset = <TEGRA_PIN_DISABLE>;
 			};
 			cam-mclk {
 				nvidia,pins = "cam_mclk_pcc0";
@@ -141,7 +141,7 @@
 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 				nvidia,open-drain = <TEGRA_PIN_ENABLE>;
-				nvidia,lock = <0>;
+				nvidia,lock = <TEGRA_PIN_DISABLE>;
 			};
 			gen2-i2c {
 				nvidia,pins = "gen2_i2c_scl_pt5",
@@ -151,7 +151,7 @@
 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 				nvidia,open-drain = <TEGRA_PIN_ENABLE>;
-				nvidia,lock = <0>;
+				nvidia,lock = <TEGRA_PIN_DISABLE>;
 			};
 			cam-i2c {
 				nvidia,pins = "cam_i2c_scl_pbb1",
@@ -161,7 +161,7 @@
 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 				nvidia,open-drain = <TEGRA_PIN_ENABLE>;
-				nvidia,lock = <0>;
+				nvidia,lock = <TEGRA_PIN_DISABLE>;
 			};
 			ddc-i2c {
 				nvidia,pins = "ddc_scl_pv4",
@@ -170,7 +170,7 @@
 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
-				nvidia,lock = <0>;
+				nvidia,lock = <TEGRA_PIN_DISABLE>;
 			};
 			pwr-i2c {
 				nvidia,pins = "pwr_i2c_scl_pz6",
@@ -180,7 +180,7 @@
 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 				nvidia,open-drain = <TEGRA_PIN_ENABLE>;
-				nvidia,lock = <0>;
+				nvidia,lock = <TEGRA_PIN_DISABLE>;
 			};
 
 			/* HDMI pinmux */
@@ -703,8 +703,8 @@
 				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
 				nvidia,tristate = <TEGRA_PIN_ENABLE>;
 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
-				nvidia,lock = <1>;
-				nvidia,io-reset = <1>;
+				nvidia,lock = <TEGRA_PIN_DISABLE>;
+				nvidia,io-reset = <TEGRA_PIN_DISABLE>;
 			};
 			vi-d3-pl1 {
 				nvidia,pins = "vi_d3_pl1";
@@ -712,8 +712,8 @@
 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 				nvidia,tristate = <TEGRA_PIN_ENABLE>;
 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
-				nvidia,lock = <1>;
-				nvidia,io-reset = <1>;
+				nvidia,lock = <TEGRA_PIN_DISABLE>;
+				nvidia,io-reset = <TEGRA_PIN_DISABLE>;
 			};
 			vi-hsync-pd7 {
 				nvidia,pins = "vi_hsync_pd7",
@@ -724,8 +724,8 @@
 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
-				nvidia,lock = <1>;
-				nvidia,io-reset = <1>;
+				nvidia,lock = <TEGRA_PIN_DISABLE>;
+				nvidia,io-reset = <TEGRA_PIN_DISABLE>;
 			};
 			vi-mclk-pt1 {
 				nvidia,pins = "vi_mclk_pt1";
@@ -733,8 +733,8 @@
 				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
 				nvidia,tristate = <TEGRA_PIN_ENABLE>;
 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
-				nvidia,lock = <1>;
-				nvidia,io-reset = <1>;
+				nvidia,lock = <TEGRA_PIN_DISABLE>;
+				nvidia,io-reset = <TEGRA_PIN_DISABLE>;
 			};
 			vi-d11-pt3 {
 				nvidia,pins = "vi_d11_pt3";
@@ -742,8 +742,8 @@
 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
-				nvidia,lock = <1>;
-				nvidia,io-reset = <1>;
+				nvidia,lock = <TEGRA_PIN_DISABLE>;
+				nvidia,io-reset = <TEGRA_PIN_DISABLE>;
 			};
 
 			/* PORT U */
diff --git a/arch/arm/dts/tegra30-ouya.dts b/arch/arm/dts/tegra30-ouya.dts
new file mode 100644
index 00000000000..04453eb2432
--- /dev/null
+++ b/arch/arm/dts/tegra30-ouya.dts
@@ -0,0 +1,2063 @@
+// SPDX-License-Identifier: GPL-2.0
+/dts-v1/;
+
+#include <dt-bindings/input/input.h>
+#include "tegra30.dtsi"
+
+/ {
+	model = "Ouya Game Console";
+	compatible = "ouya,ouya", "nvidia,tegra30";
+
+	chosen {
+		stdout-path = &uartd;
+	};
+
+	aliases {
+		i2c0 = &pwr_i2c;
+		i2c1 = &hdmi_ddc;
+
+		mmc0 = &sdmmc4;
+
+		rtc0 = &pmic;
+		rtc1 = "/rtc@7000e000";
+
+		usb0 = &micro_usb;
+		usb1 = &ethernet_usb;
+		usb2 = &fullsize_usb;
+	};
+
+	memory {
+		device_type = "memory";
+		reg = <0x80000000 0x40000000>;
+	};
+
+	host1x@50000000 {
+		dc@54200000 {
+			status = "disabled";
+		};
+
+		hdmi: hdmi@54280000 {
+			status = "okay";
+
+			hdmi-supply = <&sys_3v3_reg>;
+			pll-supply = <&ldo7_reg>;
+			vdd-supply = <&vdd_vid_reg>;
+
+			nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>;
+			nvidia,ddc-i2c-bus = <&hdmi_ddc>;
+		};
+	};
+
+	gpio@6000d000 {
+		fan-en-hog {
+			gpio-hog;
+			gpios = <TEGRA_GPIO(J, 2) GPIO_ACTIVE_HIGH>;
+			output-high;
+		};
+	};
+
+	pinmux@70000868 {
+		pinctrl-names = "default";
+		pinctrl-0 = <&state_default>;
+
+		state_default: pinmux {
+			clk_32k_out_pa0 {
+				nvidia,pins = "clk_32k_out_pa0";
+				nvidia,function = "blink";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			uart3_cts_n_pa1 {
+				nvidia,pins = "uart3_cts_n_pa1";
+				nvidia,function = "uartc";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+
+			dap2_fs_pa2 {
+				nvidia,pins = "dap2_fs_pa2";
+				nvidia,function = "i2s1";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+
+			dap2_sclk_pa3 {
+				nvidia,pins = "dap2_sclk_pa3";
+				nvidia,function = "i2s1";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+
+			dap2_din_pa4 {
+				nvidia,pins = "dap2_din_pa4";
+				nvidia,function = "i2s1";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+
+			dap2_dout_pa5 {
+				nvidia,pins = "dap2_dout_pa5";
+				nvidia,function = "i2s1";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+
+			sdmmc3_clk_pa6 {
+				nvidia,pins = "sdmmc3_clk_pa6";
+				nvidia,function = "sdmmc3";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+
+			sdmmc3_cmd_pa7 {
+				nvidia,pins = "sdmmc3_cmd_pa7";
+				nvidia,function = "sdmmc3";
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+
+			gmi_a17_pb0 {
+				nvidia,pins = "gmi_a17_pb0";
+				nvidia,function = "spi4";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			gmi_a18_pb1 {
+				nvidia,pins = "gmi_a18_pb1";
+				nvidia,function = "spi4";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			lcd_pwr0_pb2 {
+				nvidia,pins = "lcd_pwr0_pb2";
+				nvidia,function = "displaya";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			lcd_pclk_pb3 {
+				nvidia,pins = "lcd_pclk_pb3";
+				nvidia,function = "displaya";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			sdmmc3_dat3_pb4 {
+				nvidia,pins = "sdmmc3_dat3_pb4";
+				nvidia,function = "sdmmc3";
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+
+			sdmmc3_dat2_pb5 {
+				nvidia,pins = "sdmmc3_dat2_pb5";
+				nvidia,function = "sdmmc3";
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+
+			sdmmc3_dat1_pb6 {
+				nvidia,pins = "sdmmc3_dat1_pb6";
+				nvidia,function = "sdmmc3";
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+
+			sdmmc3_dat0_pb7 {
+				nvidia,pins = "sdmmc3_dat0_pb7";
+				nvidia,function = "sdmmc3";
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+
+			uart3_rts_n_pc0 {
+				nvidia,pins = "uart3_rts_n_pc0";
+				nvidia,function = "uartc";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			lcd_pwr1_pc1 {
+				nvidia,pins = "lcd_pwr1_pc1";
+				nvidia,function = "displaya";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			uart2_txd_pc2 {
+				nvidia,pins = "uart2_txd_pc2";
+				nvidia,function = "uartb";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			uart2_rxd_pc3 {
+				nvidia,pins = "uart2_rxd_pc3";
+				nvidia,function = "uartb";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			gen1_i2c_scl_pc4 {
+				nvidia,pins = "gen1_i2c_scl_pc4";
+				nvidia,function = "i2c1";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
+			};
+
+			gen1_i2c_sda_pc5 {
+				nvidia,pins = "gen1_i2c_sda_pc5";
+				nvidia,function = "i2c1";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
+			};
+
+			lcd_pwr2_pc6 {
+				nvidia,pins = "lcd_pwr2_pc6";
+				nvidia,function = "displaya";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			gmi_wp_n_pc7 {
+				nvidia,pins = "gmi_wp_n_pc7";
+				nvidia,function = "gmi";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+
+			sdmmc3_dat5_pd0 {
+				nvidia,pins = "sdmmc3_dat5_pd0";
+				nvidia,function = "sdmmc3";
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			sdmmc3_dat4_pd1 {
+				nvidia,pins = "sdmmc3_dat4_pd1";
+				nvidia,function = "sdmmc3";
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+
+			lcd_dc1_pd2 {
+				nvidia,pins = "lcd_dc1_pd2";
+				nvidia,function = "displaya";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			sdmmc3_dat6_pd3 {
+				nvidia,pins = "sdmmc3_dat6_pd3";
+				nvidia,function = "spi4";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			sdmmc3_dat7_pd4 {
+				nvidia,pins = "sdmmc3_dat7_pd4";
+				nvidia,function = "spi4";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			vi_d1_pd5 {
+				nvidia,pins = "vi_d1_pd5";
+				nvidia,function = "sdmmc2";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+
+			vi_vsync_pd6 {
+				nvidia,pins = "vi_vsync_pd6";
+				nvidia,function = "ddr";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+
+			vi_hsync_pd7 {
+				nvidia,pins = "vi_hsync_pd7";
+				nvidia,function = "ddr";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+
+			lcd_d0_pe0 {
+				nvidia,pins = "lcd_d0_pe0";
+				nvidia,function = "displaya";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			lcd_d1_pe1 {
+				nvidia,pins = "lcd_d1_pe1";
+				nvidia,function = "displaya";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			lcd_d2_pe2 {
+				nvidia,pins = "lcd_d2_pe2";
+				nvidia,function = "displaya";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			lcd_d3_pe3 {
+				nvidia,pins = "lcd_d3_pe3";
+				nvidia,function = "displaya";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			lcd_d4_pe4 {
+				nvidia,pins = "lcd_d4_pe4";
+				nvidia,function = "displaya";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			lcd_d5_pe5 {
+				nvidia,pins = "lcd_d5_pe5";
+				nvidia,function = "displaya";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			lcd_d6_pe6 {
+				nvidia,pins = "lcd_d6_pe6";
+				nvidia,function = "displaya";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			lcd_d7_pe7 {
+				nvidia,pins = "lcd_d7_pe7";
+				nvidia,function = "displaya";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			lcd_d8_pf0 {
+				nvidia,pins = "lcd_d8_pf0";
+				nvidia,function = "displaya";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			lcd_d9_pf1 {
+				nvidia,pins = "lcd_d9_pf1";
+				nvidia,function = "displaya";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			lcd_d10_pf2 {
+				nvidia,pins = "lcd_d10_pf2";
+				nvidia,function = "displaya";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			lcd_d11_pf3 {
+				nvidia,pins = "lcd_d11_pf3";
+				nvidia,function = "displaya";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			lcd_d12_pf4 {
+				nvidia,pins = "lcd_d12_pf4";
+				nvidia,function = "displaya";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			lcd_d13_pf5 {
+				nvidia,pins = "lcd_d13_pf5";
+				nvidia,function = "displaya";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			lcd_d14_pf6 {
+				nvidia,pins = "lcd_d14_pf6";
+				nvidia,function = "displaya";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			lcd_d15_pf7 {
+				nvidia,pins = "lcd_d15_pf7";
+				nvidia,function = "displaya";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			gmi_ad0_pg0 {
+				nvidia,pins = "gmi_ad0_pg0";
+				nvidia,function = "nand";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+
+			gmi_ad1_pg1 {
+				nvidia,pins = "gmi_ad1_pg1";
+				nvidia,function = "nand";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			gmi_ad2_pg2 {
+				nvidia,pins = "gmi_ad2_pg2";
+				nvidia,function = "nand";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+
+			gmi_ad3_pg3 {
+				nvidia,pins = "gmi_ad3_pg3";
+				nvidia,function = "nand";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+
+			gmi_ad4_pg4 {
+				nvidia,pins = "gmi_ad4_pg4";
+				nvidia,function = "nand";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+
+			gmi_ad5_pg5 {
+				nvidia,pins = "gmi_ad5_pg5";
+				nvidia,function = "nand";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+
+			gmi_ad6_pg6 {
+				nvidia,pins = "gmi_ad6_pg6";
+				nvidia,function = "nand";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+
+			gmi_ad7_pg7 {
+				nvidia,pins = "gmi_ad7_pg7";
+				nvidia,function = "nand";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+
+			gmi_ad8_ph0 {
+				nvidia,pins = "gmi_ad8_ph0";
+				nvidia,function = "pwm0";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			gmi_ad9_ph1 {
+				nvidia,pins = "gmi_ad9_ph1";
+				nvidia,function = "pwm1";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			gmi_ad10_ph2 {
+				nvidia,pins = "gmi_ad10_ph2";
+				nvidia,function = "pwm2";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			gmi_ad11_ph3 {
+				nvidia,pins = "gmi_ad11_ph3";
+				nvidia,function = "nand";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			gmi_ad12_ph4 {
+				nvidia,pins = "gmi_ad12_ph4";
+				nvidia,function = "nand";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			gmi_ad13_ph5 {
+				nvidia,pins = "gmi_ad13_ph5";
+				nvidia,function = "nand";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			gmi_ad14_ph6 {
+				nvidia,pins = "gmi_ad14_ph6";
+				nvidia,function = "nand";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			gmi_wr_n_pi0 {
+				nvidia,pins = "gmi_wr_n_pi0";
+				nvidia,function = "nand";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			gmi_oe_n_pi1 {
+				nvidia,pins = "gmi_oe_n_pi1";
+				nvidia,function = "nand";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			gmi_dqs_pi2 {
+				nvidia,pins = "gmi_dqs_pi2";
+				nvidia,function = "nand";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			gmi_iordy_pi5 {
+				nvidia,pins = "gmi_iordy_pi5";
+				nvidia,function = "rsvd1";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			gmi_cs7_n_pi6 {
+				nvidia,pins = "gmi_cs7_n_pi6";
+				nvidia,function = "nand";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			gmi_wait_pi7 {
+				nvidia,pins = "gmi_wait_pi7";
+				nvidia,function = "nand";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			lcd_de_pj1 {
+				nvidia,pins = "lcd_de_pj1";
+				nvidia,function = "displaya";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			gmi_cs1_n_pj2 {
+				nvidia,pins = "gmi_cs1_n_pj2";
+				nvidia,function = "rsvd1";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			lcd_hsync_pj3 {
+				nvidia,pins = "lcd_hsync_pj3";
+				nvidia,function = "displaya";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			lcd_vsync_pj4 {
+				nvidia,pins = "lcd_vsync_pj4";
+				nvidia,function = "displaya";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			uart2_cts_n_pj5 {
+				nvidia,pins = "uart2_cts_n_pj5";
+				nvidia,function = "uartb";
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			uart2_rts_n_pj6 {
+				nvidia,pins = "uart2_rts_n_pj6";
+				nvidia,function = "uartb";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			gmi_a16_pj7 {
+				nvidia,pins = "gmi_a16_pj7";
+				nvidia,function = "spi4";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			gmi_adv_n_pk0 {
+				nvidia,pins = "gmi_adv_n_pk0";
+				nvidia,function = "nand";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			gmi_clk_pk1 {
+				nvidia,pins = "gmi_clk_pk1";
+				nvidia,function = "nand";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			gmi_cs2_n_pk3 {
+				nvidia,pins = "gmi_cs2_n_pk3";
+				nvidia,function = "rsvd1";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			gmi_cs3_n_pk4 {
+				nvidia,pins = "gmi_cs3_n_pk4";
+				nvidia,function = "nand";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			spdif_out_pk5 {
+				nvidia,pins = "spdif_out_pk5";
+				nvidia,function = "spdif";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			spdif_in_pk6 {
+				nvidia,pins = "spdif_in_pk6";
+				nvidia,function = "spdif";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+
+			gmi_a19_pk7 {
+				nvidia,pins = "gmi_a19_pk7";
+				nvidia,function = "spi4";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			vi_d2_pl0 {
+				nvidia,pins = "vi_d2_pl0";
+				nvidia,function = "sdmmc2";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			vi_d3_pl1 {
+				nvidia,pins = "vi_d3_pl1";
+				nvidia,function = "sdmmc2";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			vi_d4_pl2 {
+				nvidia,pins = "vi_d4_pl2";
+				nvidia,function = "vi";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			vi_d5_pl3 {
+				nvidia,pins = "vi_d5_pl3";
+				nvidia,function = "sdmmc2";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			vi_d6_pl4 {
+				nvidia,pins = "vi_d6_pl4";
+				nvidia,function = "vi";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			vi_d7_pl5 {
+				nvidia,pins = "vi_d7_pl5";
+				nvidia,function = "sdmmc2";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			vi_d8_pl6 {
+				nvidia,pins = "vi_d8_pl6";
+				nvidia,function = "sdmmc2";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			vi_d9_pl7 {
+				nvidia,pins = "vi_d9_pl7";
+				nvidia,function = "sdmmc2";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			lcd_d16_pm0 {
+				nvidia,pins = "lcd_d16_pm0";
+				nvidia,function = "displaya";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			lcd_d17_pm1 {
+				nvidia,pins = "lcd_d17_pm1";
+				nvidia,function = "displaya";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			lcd_d18_pm2 {
+				nvidia,pins = "lcd_d18_pm2";
+				nvidia,function = "displaya";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			lcd_d19_pm3 {
+				nvidia,pins = "lcd_d19_pm3";
+				nvidia,function = "displaya";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			lcd_d20_pm4 {
+				nvidia,pins = "lcd_d20_pm4";
+				nvidia,function = "displaya";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			lcd_d21_pm5 {
+				nvidia,pins = "lcd_d21_pm5";
+				nvidia,function = "displaya";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			lcd_d22_pm6 {
+				nvidia,pins = "lcd_d22_pm6";
+				nvidia,function = "displaya";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			lcd_d23_pm7 {
+				nvidia,pins = "lcd_d23_pm7";
+				nvidia,function = "displaya";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			dap1_fs_pn0 {
+				nvidia,pins = "dap1_fs_pn0";
+				nvidia,function = "i2s0";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+
+			dap1_din_pn1 {
+				nvidia,pins = "dap1_din_pn1";
+				nvidia,function = "i2s0";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+
+			dap1_dout_pn2 {
+				nvidia,pins = "dap1_dout_pn2";
+				nvidia,function = "i2s0";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+
+			dap1_sclk_pn3 {
+				nvidia,pins = "dap1_sclk_pn3";
+				nvidia,function = "i2s0";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+
+			lcd_cs0_n_pn4 {
+				nvidia,pins = "lcd_cs0_n_pn4";
+				nvidia,function = "displaya";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			lcd_sdout_pn5 {
+				nvidia,pins = "lcd_sdout_pn5";
+				nvidia,function = "displaya";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			lcd_dc0_pn6 {
+				nvidia,pins = "lcd_dc0_pn6";
+				nvidia,function = "displaya";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			hdmi_int_pn7 {
+				nvidia,pins = "hdmi_int_pn7";
+				nvidia,function = "hdmi";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+
+			ulpi_data7_po0 {
+				nvidia,pins = "ulpi_data7_po0";
+				nvidia,function = "uarta";
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			ulpi_data0_po1 {
+				nvidia,pins = "ulpi_data0_po1";
+				nvidia,function = "uarta";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			ulpi_data1_po2 {
+				nvidia,pins = "ulpi_data1_po2";
+				nvidia,function = "uarta";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			ulpi_data2_po3 {
+				nvidia,pins = "ulpi_data2_po3";
+				nvidia,function = "uarta";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			ulpi_data3_po4 {
+				nvidia,pins = "ulpi_data3_po4";
+				nvidia,function = "uarta";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+
+			ulpi_data4_po5 {
+				nvidia,pins = "ulpi_data4_po5";
+				nvidia,function = "uarta";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			ulpi_data5_po6 {
+				nvidia,pins = "ulpi_data5_po6";
+				nvidia,function = "uarta";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			ulpi_data6_po7 {
+				nvidia,pins = "ulpi_data6_po7";
+				nvidia,function = "uarta";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			dap3_fs_pp0 {
+				nvidia,pins = "dap3_fs_pp0";
+				nvidia,function = "i2s2";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+
+			dap3_din_pp1 {
+				nvidia,pins = "dap3_din_pp1";
+				nvidia,function = "i2s2";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+
+			dap3_dout_pp2 {
+				nvidia,pins = "dap3_dout_pp2";
+				nvidia,function = "i2s2";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+
+			dap3_sclk_pp3 {
+				nvidia,pins = "dap3_sclk_pp3";
+				nvidia,function = "i2s2";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+
+			dap4_fs_pp4 {
+				nvidia,pins = "dap4_fs_pp4";
+				nvidia,function = "i2s3";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+
+			dap4_din_pp5 {
+				nvidia,pins = "dap4_din_pp5";
+				nvidia,function = "i2s3";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+
+			dap4_dout_pp6 {
+				nvidia,pins = "dap4_dout_pp6";
+				nvidia,function = "i2s3";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+
+			dap4_sclk_pp7 {
+				nvidia,pins = "dap4_sclk_pp7";
+				nvidia,function = "i2s3";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+
+			kb_col0_pq0 {
+				nvidia,pins = "kb_col0_pq0";
+				nvidia,function = "kbc";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			kb_col1_pq1 {
+				nvidia,pins = "kb_col1_pq1";
+				nvidia,function = "kbc";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			kb_col2_pq2 {
+				nvidia,pins = "kb_col2_pq2";
+				nvidia,function = "kbc";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			kb_col3_pq3 {
+				nvidia,pins = "kb_col3_pq3";
+				nvidia,function = "kbc";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			kb_col4_pq4 {
+				nvidia,pins = "kb_col4_pq4";
+				nvidia,function = "kbc";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			kb_col5_pq5 {
+				nvidia,pins = "kb_col5_pq5";
+				nvidia,function = "kbc";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			kb_col6_pq6 {
+				nvidia,pins = "kb_col6_pq6";
+				nvidia,function = "kbc";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			kb_col7_pq7 {
+				nvidia,pins = "kb_col7_pq7";
+				nvidia,function = "kbc";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			kb_row0_pr0 {
+				nvidia,pins = "kb_row0_pr0";
+				nvidia,function = "kbc";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			kb_row1_pr1 {
+				nvidia,pins = "kb_row1_pr1";
+				nvidia,function = "kbc";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			kb_row2_pr2 {
+				nvidia,pins = "kb_row2_pr2";
+				nvidia,function = "kbc";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			kb_row3_pr3 {
+				nvidia,pins = "kb_row3_pr3";
+				nvidia,function = "kbc";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			kb_row4_pr4 {
+				nvidia,pins = "kb_row4_pr4";
+				nvidia,function = "kbc";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			kb_row5_pr5 {
+				nvidia,pins = "kb_row5_pr5";
+				nvidia,function = "kbc";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			kb_row6_pr6 {
+				nvidia,pins = "kb_row6_pr6";
+				nvidia,function = "kbc";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			kb_row7_pr7 {
+				nvidia,pins = "kb_row7_pr7";
+				nvidia,function = "kbc";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+
+			kb_row8_ps0 {
+				nvidia,pins = "kb_row8_ps0";
+				nvidia,function = "kbc";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			kb_row9_ps1 {
+				nvidia,pins = "kb_row9_ps1";
+				nvidia,function = "kbc";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			kb_row10_ps2 {
+				nvidia,pins = "kb_row10_ps2";
+				nvidia,function = "kbc";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			kb_row11_ps3 {
+				nvidia,pins = "kb_row11_ps3";
+				nvidia,function = "kbc";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			kb_row12_ps4 {
+				nvidia,pins = "kb_row12_ps4";
+				nvidia,function = "kbc";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			kb_row13_ps5 {
+				nvidia,pins = "kb_row13_ps5";
+				nvidia,function = "kbc";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			kb_row14_ps6 {
+				nvidia,pins = "kb_row14_ps6";
+				nvidia,function = "kbc";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			kb_row15_ps7 {
+				nvidia,pins = "kb_row15_ps7";
+				nvidia,function = "kbc";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			vi_pclk_pt0 {
+				nvidia,pins = "vi_pclk_pt0";
+				nvidia,function = "rsvd1";
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			vi_mclk_pt1 {
+				nvidia,pins = "vi_mclk_pt1";
+				nvidia,function = "vi";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			vi_d10_pt2 {
+				nvidia,pins = "vi_d10_pt2";
+				nvidia,function = "ddr";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+
+			vi_d11_pt3 {
+				nvidia,pins = "vi_d11_pt3";
+				nvidia,function = "ddr";
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+
+			vi_d0_pt4 {
+				nvidia,pins = "vi_d0_pt4";
+				nvidia,function = "ddr";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+
+			gen2_i2c_scl_pt5 {
+				nvidia,pins = "gen2_i2c_scl_pt5";
+				nvidia,function = "i2c2";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
+			};
+
+			gen2_i2c_sda_pt6 {
+				nvidia,pins = "gen2_i2c_sda_pt6";
+				nvidia,function = "i2c2";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
+			};
+
+			pu0 {
+				nvidia,pins = "pu0";
+				nvidia,function = "owr";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			pu1 {
+				nvidia,pins = "pu1";
+				nvidia,function = "rsvd1";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			pu2 {
+				nvidia,pins = "pu2";
+				nvidia,function = "rsvd1";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			pu3 {
+				nvidia,pins = "pu3";
+				nvidia,function = "pwm0";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			pu4 {
+				nvidia,pins = "pu4";
+				nvidia,function = "pwm1";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			pu5 {
+				nvidia,pins = "pu5";
+				nvidia,function = "rsvd4";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			pu6 {
+				nvidia,pins = "pu6";
+				nvidia,function = "pwm3";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+
+			jtag_rtck_pu7 {
+				nvidia,pins = "jtag_rtck_pu7";
+				nvidia,function = "rtck";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			pv0 {
+				nvidia,pins = "pv0";
+				nvidia,function = "rsvd1";
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+
+			pv1 {
+				nvidia,pins = "pv1";
+				nvidia,function = "rsvd1";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			pv2 {
+				nvidia,pins = "pv2";
+				nvidia,function = "owr";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			pv3 {
+				nvidia,pins = "pv3";
+				nvidia,function = "clk_12m_out";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			ddc_scl_pv4 {
+				nvidia,pins = "ddc_scl_pv4";
+				nvidia,function = "i2c4";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+
+			ddc_sda_pv5 {
+				nvidia,pins = "ddc_sda_pv5";
+				nvidia,function = "i2c4";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+
+			crt_hsync_pv6 {
+				nvidia,pins = "crt_hsync_pv6";
+				nvidia,function = "crt";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			crt_vsync_pv7 {
+				nvidia,pins = "crt_vsync_pv7";
+				nvidia,function = "crt";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			lcd_cs1_n_pw0 {
+				nvidia,pins = "lcd_cs1_n_pw0";
+				nvidia,function = "displaya";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			lcd_m1_pw1 {
+				nvidia,pins = "lcd_m1_pw1";
+				nvidia,function = "displaya";
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			spi2_cs1_n_pw2 {
+				nvidia,pins = "spi2_cs1_n_pw2";
+				nvidia,function = "spi2";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			clk1_out_pw4 {
+				nvidia,pins = "clk1_out_pw4";
+				nvidia,function = "extperiph1";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+
+			clk2_out_pw5 {
+				nvidia,pins = "clk2_out_pw5";
+				nvidia,function = "extperiph2";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+
+			uart3_txd_pw6 {
+				nvidia,pins = "uart3_txd_pw6";
+				nvidia,function = "uartc";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			uart3_rxd_pw7 {
+				nvidia,pins = "uart3_rxd_pw7";
+				nvidia,function = "uartc";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+
+			spi2_sck_px2 {
+				nvidia,pins = "spi2_sck_px2";
+				nvidia,function = "gmi";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			spi1_mosi_px4 {
+				nvidia,pins = "spi1_mosi_px4";
+				nvidia,function = "spi1";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			spi1_sck_px5 {
+				nvidia,pins = "spi1_sck_px5";
+				nvidia,function = "spi1";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			spi1_cs0_n_px6 {
+				nvidia,pins = "spi1_cs0_n_px6";
+				nvidia,function = "spi1";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			spi1_miso_px7 {
+				nvidia,pins = "spi1_miso_px7";
+				nvidia,function = "spi1";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			ulpi_clk_py0 {
+				nvidia,pins = "ulpi_clk_py0";
+				nvidia,function = "uartd";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			ulpi_dir_py1 {
+				nvidia,pins = "ulpi_dir_py1";
+				nvidia,function = "uartd";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+
+			ulpi_nxt_py2 {
+				nvidia,pins = "ulpi_nxt_py2";
+				nvidia,function = "uartd";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+
+			ulpi_stp_py3 {
+				nvidia,pins = "ulpi_stp_py3";
+				nvidia,function = "uartd";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			sdmmc1_dat3_py4 {
+				nvidia,pins = "sdmmc1_dat3_py4";
+				nvidia,function = "sdmmc1";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			sdmmc1_dat2_py5 {
+				nvidia,pins = "sdmmc1_dat2_py5";
+				nvidia,function = "sdmmc1";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			sdmmc1_dat1_py6 {
+				nvidia,pins = "sdmmc1_dat1_py6";
+				nvidia,function = "sdmmc1";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			sdmmc1_dat0_py7 {
+				nvidia,pins = "sdmmc1_dat0_py7";
+				nvidia,function = "sdmmc1";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			sdmmc1_clk_pz0 {
+				nvidia,pins = "sdmmc1_clk_pz0";
+				nvidia,function = "sdmmc1";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			sdmmc1_cmd_pz1 {
+				nvidia,pins = "sdmmc1_cmd_pz1";
+				nvidia,function = "sdmmc1";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			lcd_sdin_pz2 {
+				nvidia,pins = "lcd_sdin_pz2";
+				nvidia,function = "displaya";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			lcd_wr_n_pz3 {
+				nvidia,pins = "lcd_wr_n_pz3";
+				nvidia,function = "displaya";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			lcd_sck_pz4 {
+				nvidia,pins = "lcd_sck_pz4";
+				nvidia,function = "displaya";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			sys_clk_req_pz5 {
+				nvidia,pins = "sys_clk_req_pz5";
+				nvidia,function = "sysclk";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			pwr_i2c_scl_pz6 {
+				nvidia,pins = "pwr_i2c_scl_pz6";
+				nvidia,function = "i2cpwr";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+				nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+			};
+
+			pwr_i2c_sda_pz7 {
+				nvidia,pins = "pwr_i2c_sda_pz7";
+				nvidia,function = "i2cpwr";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+				nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+			};
+
+			pbb0 {
+				nvidia,pins = "pbb0";
+				nvidia,function = "i2s4";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			cam_i2c_scl_pbb1 {
+				nvidia,pins = "cam_i2c_scl_pbb1";
+				nvidia,function = "i2c3";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
+			};
+
+			cam_i2c_sda_pbb2 {
+				nvidia,pins = "cam_i2c_sda_pbb2";
+				nvidia,function = "i2c3";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
+			};
+
+			pbb3 {
+				nvidia,pins = "pbb3";
+				nvidia,function = "vgp3";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			pbb4 {
+				nvidia,pins = "pbb4";
+				nvidia,function = "vgp4";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			pbb5 {
+				nvidia,pins = "pbb5";
+				nvidia,function = "vgp5";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			pbb6 {
+				nvidia,pins = "pbb6";
+				nvidia,function = "vgp6";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			pbb7 {
+				nvidia,pins = "pbb7";
+				nvidia,function = "i2s4";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			pcc1 {
+				nvidia,pins = "pcc1";
+				nvidia,function = "i2s4";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+
+			pcc2 {
+				nvidia,pins = "pcc2";
+				nvidia,function = "i2s4";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+
+			clk2_req_pcc5 {
+				nvidia,pins = "clk2_req_pcc5";
+				nvidia,function = "dap";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			pex_l2_rst_n_pcc6 {
+				nvidia,pins = "pex_l2_rst_n_pcc6";
+				nvidia,function = "pcie";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			pex_l2_clkreq_n_pcc7 {
+				nvidia,pins = "pex_l2_clkreq_n_pcc7";
+				nvidia,function = "pcie";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			pex_l0_prsnt_n_pdd0 {
+				nvidia,pins = "pex_l0_prsnt_n_pdd0";
+				nvidia,function = "pcie";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			pex_l0_rst_n_pdd1 {
+				nvidia,pins = "pex_l0_rst_n_pdd1";
+				nvidia,function = "pcie";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			pex_l0_clkreq_n_pdd2 {
+				nvidia,pins = "pex_l0_clkreq_n_pdd2";
+				nvidia,function = "pcie";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			pex_wake_n_pdd3 {
+				nvidia,pins = "pex_wake_n_pdd3";
+				nvidia,function = "pcie";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			pex_l1_prsnt_n_pdd4 {
+				nvidia,pins = "pex_l1_prsnt_n_pdd4";
+				nvidia,function = "pcie";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			pex_l1_rst_n_pdd5 {
+				nvidia,pins = "pex_l1_rst_n_pdd5";
+				nvidia,function = "pcie";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			pex_l1_clkreq_n_pdd6 {
+				nvidia,pins = "pex_l1_clkreq_n_pdd6";
+				nvidia,function = "pcie";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			pex_l2_prsnt_n_pdd7 {
+				nvidia,pins = "pex_l2_prsnt_n_pdd7";
+				nvidia,function = "pcie";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			clk3_out_pee0 {
+				nvidia,pins = "clk3_out_pee0";
+				nvidia,function = "extperiph3";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			clk3_req_pee1 {
+				nvidia,pins = "clk3_req_pee1";
+				nvidia,function = "dev3";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+
+			clk1_req_pee2 {
+				nvidia,pins = "clk1_req_pee2";
+				nvidia,function = "dap";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+
+			hdmi_cec_pee3 {
+				nvidia,pins = "hdmi_cec_pee3";
+				nvidia,function = "cec";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
+			};
+
+			owr {
+				nvidia,pins = "owr";
+				nvidia,function = "owr";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+			};
+
+			/* SDMMC4 pinmux */
+			sdmmc4_clk {
+				nvidia,pins = "sdmmc4_clk_pcc4";
+				nvidia,function = "sdmmc4";
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+				nvidia,lock = <TEGRA_PIN_DISABLE>;
+				nvidia,io-reset = <TEGRA_PIN_DISABLE>;
+			};
+			sdmmc4_cmd {
+				nvidia,pins = "sdmmc4_cmd_pt7",
+						"sdmmc4_dat0_paa0",
+						"sdmmc4_dat1_paa1",
+						"sdmmc4_dat2_paa2",
+						"sdmmc4_dat3_paa3",
+						"sdmmc4_dat4_paa4",
+						"sdmmc4_dat5_paa5",
+						"sdmmc4_dat6_paa6",
+						"sdmmc4_dat7_paa7";
+				nvidia,function = "sdmmc4";
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+				nvidia,lock = <TEGRA_PIN_DISABLE>;
+				nvidia,io-reset = <TEGRA_PIN_DISABLE>;
+			};
+			sdmmc4_rst_n {
+				nvidia,pins = "sdmmc4_rst_n_pcc3";
+				nvidia,function = "rsvd2";
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+			cam_mclk {
+				nvidia,pins = "cam_mclk_pcc0";
+				nvidia,function = "vi_alt3";
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+			};
+
+			drive_groups {
+				nvidia,pins = "drive_gma",
+					      "drive_gmb",
+					      "drive_gmc",
+					      "drive_gmd";
+				nvidia,pull-down-strength = <9>;
+				nvidia,pull-up-strength = <9>;
+				nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_SLOWEST>;
+				nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_SLOWEST>;
+			};
+		};
+	};
+
+	uartd: serial@70006300 {
+		status = "okay";
+	};
+
+	hdmi_ddc: i2c@7000c700 {
+		status = "okay";
+		clock-frequency = <100000>;
+	};
+
+	pwr_i2c: i2c@7000d000 {
+		status = "okay";
+		clock-frequency = <400000>;
+
+		pmic: pmic@2d {
+			compatible = "ti,tps65911";
+			reg = <0x2d>;
+
+			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
+			#interrupt-cells = <2>;
+			interrupt-controller;
+			wakeup-source;
+
+			ti,en-gpio-sleep = <0 1 1 1 1 1 0 0 1>;
+			ti,system-power-controller;
+			ti,sleep-keep-ck32k;
+			ti,sleep-enable;
+
+			#gpio-cells = <2>;
+			gpio-controller;
+
+			regulators {
+				vdd_1v8: vddio {
+					regulator-name = "vdd_1v8_gen";
+					regulator-min-microvolt = <1800000>;
+					regulator-max-microvolt = <1800000>;
+					regulator-always-on;
+					regulator-boot-on;
+				};
+
+				ldo7_reg: ldo7 {
+					regulator-name = "vdd_pllm,x,u,a_p_c_s";
+					regulator-min-microvolt = <1200000>;
+					regulator-max-microvolt = <1200000>;
+					regulator-boot-on;
+				};
+			};
+		};
+	};
+
+	sdmmc4: sdhci@78000600 {
+		status = "okay";
+		bus-width = <8>;
+		non-removable;
+
+		vmmc-supply = <&sys_3v3_reg>;
+		vqmmc-supply = <&vdd_1v8>;
+	};
+
+	micro_usb: usb@7d000000 {
+		status = "okay";
+		dr_mode = "otg";
+	};
+
+	usb-phy@7d000000 {
+		status = "okay";
+	};
+
+	ethernet_usb: usb@7d004000 {
+		status = "okay";
+		nvidia,vbus-gpio = <&gpio TEGRA_GPIO(DD, 5) GPIO_ACTIVE_HIGH>;
+
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		/* SMSC 10/100T Ethernet Controller */
+		ethernet@2 {
+			compatible = "usb424,9e00";
+			reg = <2>;
+			local-mac-address = [00 11 22 33 44 55];
+		};
+	};
+
+	usb-phy@7d004000 {
+		status = "okay";
+	};
+
+	fullsize_usb: usb@7d008000 {
+		status = "okay";
+		nvidia,vbus-gpio = <&gpio TEGRA_GPIO(DD, 4) GPIO_ACTIVE_HIGH>;
+	};
+
+	usb-phy@7d008000 {
+		status = "okay";
+	};
+
+	/* PMIC has a built-in 32KHz oscillator which is used by PMC */
+	clk32k_in: clock {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <32768>;
+		clock-output-names = "pmic-oscillator";
+	};
+
+	gpio-keys {
+		compatible = "gpio-keys";
+
+		key-power {
+			label = "Power";
+			gpios = <&gpio TEGRA_GPIO(V, 0) GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_POWER>;
+		};
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		led-power {
+			label = "power-led";
+			gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>;
+			default-state = "on";
+			linux,default-trigger = "heartbeat";
+			retain-state-suspended;
+		};
+	};
+
+	sys_3v3_reg: regulator-sys-3v3 {
+		compatible = "regulator-fixed";
+		regulator-name = "sys_3v3";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-always-on;
+		regulator-boot-on;
+	};
+
+	vdd_vid_reg: regulator-vdd-vid {
+		compatible = "regulator-fixed";
+		regulator-name = "vddio_vid";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		regulator-boot-on;
+		gpio = <&gpio TEGRA_GPIO(T, 0) GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+	};
+};
diff --git a/arch/arm/dts/tegra30-wexler-qc750.dts b/arch/arm/dts/tegra30-wexler-qc750.dts
index 87c2a4072e1..b376b91a7fa 100644
--- a/arch/arm/dts/tegra30-wexler-qc750.dts
+++ b/arch/arm/dts/tegra30-wexler-qc750.dts
@@ -157,7 +157,7 @@
 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 				nvidia,open-drain = <TEGRA_PIN_ENABLE>;
-				nvidia,lock = <0>;
+				nvidia,lock = <TEGRA_PIN_DISABLE>;
 			};
 			gen2-i2c {
 				nvidia,pins = "gen2_i2c_scl_pt5",
@@ -167,7 +167,7 @@
 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 				nvidia,open-drain = <TEGRA_PIN_ENABLE>;
-				nvidia,lock = <0>;
+				nvidia,lock = <TEGRA_PIN_DISABLE>;
 			};
 			cam-i2c {
 				nvidia,pins = "cam_i2c_scl_pbb1",
@@ -177,7 +177,7 @@
 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 				nvidia,open-drain = <TEGRA_PIN_ENABLE>;
-				nvidia,lock = <0>;
+				nvidia,lock = <TEGRA_PIN_DISABLE>;
 			};
 			ddc-i2c {
 				nvidia,pins = "ddc_scl_pv4",
@@ -186,7 +186,7 @@
 				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
-				nvidia,lock = <0>;
+				nvidia,lock = <TEGRA_PIN_DISABLE>;
 			};
 			pwr-i2c {
 				nvidia,pins = "pwr_i2c_scl_pz6",
@@ -196,7 +196,7 @@
 				nvidia,tristate = <TEGRA_PIN_DISABLE>;
 				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 				nvidia,open-drain = <TEGRA_PIN_ENABLE>;
-				nvidia,lock = <0>;
+				nvidia,lock = <TEGRA_PIN_DISABLE>;
 			};
 
 			/* HDMI pinmux */
diff --git a/arch/arm/include/asm/arch-meson/boot.h b/arch/arm/include/asm/arch-meson/boot.h
index c67d12d06c9..a11dfde719e 100644
--- a/arch/arm/include/asm/arch-meson/boot.h
+++ b/arch/arm/include/asm/arch-meson/boot.h
@@ -21,4 +21,18 @@ int meson_get_boot_device(void);
 
 int meson_get_soc_rev(char *buff, size_t buff_len);
 
+/**
+ * meson_get_socinfo - retrieve cpu_id of the Amlogic SoC
+ *
+ * The value in the following format is read from register:
+ *   +-----------+------------+------------+------------+
+ *   | family_id | package_id |  chip_rev  | layout_rev |
+ *   +-----------+------------+------------+------------+
+ *   | 31     24 | 23      16 | 15       8 | 7        0 |
+ *   +-----------+------------+------------+------------+
+ *
+ * Return: 4 bytes value of cpu_id on success or 0 on failure.
+ */
+u32 meson_get_socinfo(void);
+
 #endif /* __MESON_BOOT_H__ */
diff --git a/arch/arm/include/asm/arch-meson/sm.h b/arch/arm/include/asm/arch-meson/sm.h
index 4b1d564bc48..4d614955fc2 100644
--- a/arch/arm/include/asm/arch-meson/sm.h
+++ b/arch/arm/include/asm/arch-meson/sm.h
@@ -6,6 +6,8 @@
 #ifndef __MESON_SM_H__
 #define __MESON_SM_H__
 
+#include <asm/types.h>
+
 /**
  * meson_sm_read_efuse - read efuse memory into buffer
  *
@@ -27,16 +29,60 @@ ssize_t meson_sm_read_efuse(uintptr_t offset, void *buffer, size_t size);
 ssize_t meson_sm_write_efuse(uintptr_t offset, void *buffer, size_t size);
 
 #define SM_SERIAL_SIZE	12
+#define MESON_CPU_ID_SZ	4
+#define MESON_CHIP_ID_SZ 16
+
+/**
+ * union meson_cpu_id - Amlogic cpu_id.
+ * @raw: buffer to hold the cpu_id value as sequential bytes.
+ * @val: cpu_id represented as 32 bit value.
+ */
+union meson_cpu_id {
+	u8 raw[MESON_CPU_ID_SZ];
+	u32 val;
+};
+
+/**
+ * struct meson_sm_chip_id - Amlogic chip_id.
+ * @cpu_id: cpu_id value, which is distinct from socinfo in that the order of
+ *          PACK & MINOR bytes are swapped according to Amlogic chip_id format.
+ * @serial: 12 byte unique SoC number, identifying particular die, read
+ *          usually from efuse OTP storage. Serial comes in little-endian
+ *          order.
+ */
+struct meson_sm_chip_id {
+	union meson_cpu_id cpu_id;
+	u8 serial[SM_SERIAL_SIZE];
+};
 
 /**
- * meson_sm_get_serial - read chip unique id into buffer
+ * meson_sm_get_serial - read chip unique serial (OTP data) into buffer
  *
  * @buffer: pointer to buffer
  * @size: buffer size.
+ *
+ * Serial is returned in big-endian order.
+ *
  * @return: zero on success or -errno on failure
  */
 int meson_sm_get_serial(void *buffer, size_t size);
 
+/**
+ * meson_sm_get_chip_id - read Amlogic chip_id
+ *
+ * @chip_id: pointer to buffer capable to hold the struct meson_sm_chip_id
+ *
+ * Amlogic SoCs support 2 versions of chip_id. Function requests the newest
+ * one (v2), but if chip_id v2 is not supported, then secure monitor returns
+ * v1. All differences between v1 and v2 versions are handled by this function
+ * and chip_id is returned in unified format.
+ *
+ * chip_id contains serial, which is returned here in little-endian order.
+ *
+ * @return: 0 on success or -errno on failure
+ */
+int meson_sm_get_chip_id(struct meson_sm_chip_id *chip_id);
+
 enum {
 	REBOOT_REASON_COLD = 0,
 	REBOOT_REASON_NORMAL = 1,
diff --git a/arch/arm/include/asm/arch-npcm8xx/gmac.h b/arch/arm/include/asm/arch-npcm8xx/gmac.h
new file mode 100644
index 00000000000..f84eedddc22
--- /dev/null
+++ b/arch/arm/include/asm/arch-npcm8xx/gmac.h
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+
+#ifndef _NPCM_GMAC_H_
+#define _NPCM_GMAC_H_
+
+/* PCS registers */
+#define PCS_BA			0xF0780000
+#define PCS_IND_AC		0x1FE
+#define SR_MII_MMD		0x3E0000
+#define SR_MII_MMD_CTRL		0x0
+#define SR_MII_MMD_STS		0x2
+#define VR_MII_MMD		0x3F0000
+#define VR_MII_MMD_CTRL1	0x0
+#define VR_MII_MMD_AN_CTRL	0x2
+
+#define LINK_UP_TIMEOUT		(3 * CONFIG_SYS_HZ)
+
+#endif
diff --git a/arch/arm/include/asm/arch-sunxi/boot0.h b/arch/arm/include/asm/arch-sunxi/boot0.h
index 6b2bb5a4586..24c81391d58 100644
--- a/arch/arm/include/asm/arch-sunxi/boot0.h
+++ b/arch/arm/include/asm/arch-sunxi/boot0.h
@@ -16,10 +16,11 @@
  */
 	tst     x0, x0                  // this is "b #0x84" in ARM
 	b       reset
-	.space  0x7c
+	.space  0x78
+	.word	fel_stash - .
 
-	.word	0xe28f0070	// add     r0, pc, #112	 // @(fel_stash - .)
-	.word	0xe59f106c	// ldr     r1, [pc, #108] // fel_stash - .
+	.word	0xe24f000c	// sub     r0, pc, #12  // @(fel_stash - .)
+	.word	0xe51f1010	// ldr     r1, [pc, #-16] // fel_stash - .
 	.word	0xe0800001	// add     r0, r0, r1
 	.word	0xe580d000	// str     sp, [r0]
 	.word	0xe580e004	// str     lr, [r0, #4]
@@ -54,7 +55,6 @@
 #else
 	.word   CONFIG_TEXT_BASE
 #endif
-	.word	fel_stash - .
 #else
 /* normal execution */
 	b	reset
diff --git a/arch/arm/include/asm/arch-tegra/dc.h b/arch/arm/include/asm/arch-tegra/dc.h
index ca3718411ab..2fd07403bdf 100644
--- a/arch/arm/include/asm/arch-tegra/dc.h
+++ b/arch/arm/include/asm/arch-tegra/dc.h
@@ -448,6 +448,11 @@ enum win_color_depth_id {
 #define LVS_OUTPUT_POLARITY_LOW		BIT(28)
 #define LSC0_OUTPUT_POLARITY_LOW	BIT(24)
 
+/* DC_DISP_DISP_SIGNAL_OPTIONS0 0x400 */
+#define H_PULSE0_ENABLE		BIT(8)
+#define H_PULSE1_ENABLE		BIT(10)
+#define H_PULSE2_ENABLE		BIT(12)
+
 /* DC_DISP_DISP_WIN_OPTIONS 0x402 */
 #define	CURSOR_ENABLE		BIT(16)
 #define	SOR_ENABLE		BIT(25)
@@ -504,6 +509,22 @@ enum {
 	DATA_ORDER_BLUE_RED,
 };
 
+/* DC_DISP_DISP_COLOR_CONTROL 0x430 */
+#define DITHER_CONTROL_DISABLE	(0 << 8)
+#define DITHER_CONTROL_ORDERED	(2 << 8)
+#define DITHER_CONTROL_ERRDIFF	(3 << 8)
+enum {
+	BASE_COLOR_SIZE_666,
+	BASE_COLOR_SIZE_111,
+	BASE_COLOR_SIZE_222,
+	BASE_COLOR_SIZE_333,
+	BASE_COLOR_SIZE_444,
+	BASE_COLOR_SIZE_555,
+	BASE_COLOR_SIZE_565,
+	BASE_COLOR_SIZE_332,
+	BASE_COLOR_SIZE_888,
+};
+
 /* DC_DISP_DATA_ENABLE_OPTIONS 0x432 */
 #define DE_SELECT_SHIFT		0
 #define DE_SELECT_MASK		(0x3 << DE_SELECT_SHIFT)
@@ -570,8 +591,27 @@ enum {
 #define V_DDA_INC_SHIFT		16
 #define V_DDA_INC_MASK		(0xFFFF << V_DDA_INC_SHIFT)
 
-#define DC_POLL_TIMEOUT_MS		50
-#define DC_N_WINDOWS			5
-#define DC_REG_SAVE_SPACE		(DC_N_WINDOWS + 5)
+#define DC_POLL_TIMEOUT_MS	50
+#define DC_N_WINDOWS		5
+#define DC_REG_SAVE_SPACE	(DC_N_WINDOWS + 5)
+
+#define PULSE_MODE_NORMAL	(0 << 3)
+#define PULSE_MODE_ONE_CLOCK	(1 << 3)
+#define PULSE_POLARITY_HIGH	(0 << 4)
+#define PULSE_POLARITY_LOW	(1 << 4)
+#define PULSE_QUAL_ALWAYS	(0 << 6)
+#define PULSE_QUAL_VACTIVE	(2 << 6)
+#define PULSE_QUAL_VACTIVE1	(3 << 6)
+#define PULSE_LAST_START_A	(0 << 8)
+#define PULSE_LAST_END_A	(1 << 8)
+#define PULSE_LAST_START_B	(2 << 8)
+#define PULSE_LAST_END_B	(3 << 8)
+#define PULSE_LAST_START_C	(4 << 8)
+#define PULSE_LAST_END_C	(5 << 8)
+#define PULSE_LAST_START_D	(6 << 8)
+#define PULSE_LAST_END_D	(7 << 8)
+
+#define PULSE_START(x)		(((x) & 0xfff) <<  0)
+#define PULSE_END(x)		(((x) & 0xfff) << 16)
 
 #endif /* __ASM_ARCH_TEGRA_DC_H */
diff --git a/arch/arm/include/asm/arch-tegra/pinmux.h b/arch/arm/include/asm/arch-tegra/pinmux.h
index 4b6e8419504..9a5cc93884c 100644
--- a/arch/arm/include/asm/arch-tegra/pinmux.h
+++ b/arch/arm/include/asm/arch-tegra/pinmux.h
@@ -34,41 +34,41 @@ enum pmux_pin_io {
 
 #ifdef TEGRA_PMX_PINS_HAVE_LOCK
 enum pmux_pin_lock {
-	PMUX_PIN_LOCK_DEFAULT = 0,
-	PMUX_PIN_LOCK_DISABLE,
+	PMUX_PIN_LOCK_DISABLE = 0,
 	PMUX_PIN_LOCK_ENABLE,
+	PMUX_PIN_LOCK_DEFAULT,
 };
 #endif
 
 #ifdef TEGRA_PMX_PINS_HAVE_OD
 enum pmux_pin_od {
-	PMUX_PIN_OD_DEFAULT = 0,
-	PMUX_PIN_OD_DISABLE,
+	PMUX_PIN_OD_DISABLE = 0,
 	PMUX_PIN_OD_ENABLE,
+	PMUX_PIN_OD_DEFAULT,
 };
 #endif
 
 #ifdef TEGRA_PMX_PINS_HAVE_IO_RESET
 enum pmux_pin_ioreset {
-	PMUX_PIN_IO_RESET_DEFAULT = 0,
-	PMUX_PIN_IO_RESET_DISABLE,
+	PMUX_PIN_IO_RESET_DISABLE = 0,
 	PMUX_PIN_IO_RESET_ENABLE,
+	PMUX_PIN_IO_RESET_DEFAULT,
 };
 #endif
 
 #ifdef TEGRA_PMX_PINS_HAVE_RCV_SEL
 enum pmux_pin_rcv_sel {
-	PMUX_PIN_RCV_SEL_DEFAULT = 0,
-	PMUX_PIN_RCV_SEL_NORMAL,
+	PMUX_PIN_RCV_SEL_NORMAL = 0,
 	PMUX_PIN_RCV_SEL_HIGH,
+	PMUX_PIN_RCV_SEL_DEFAULT,
 };
 #endif
 
 #ifdef TEGRA_PMX_PINS_HAVE_E_IO_HV
 enum pmux_pin_e_io_hv {
-	PMUX_PIN_E_IO_HV_DEFAULT = 0,
-	PMUX_PIN_E_IO_HV_NORMAL,
+	PMUX_PIN_E_IO_HV_NORMAL = 0,
 	PMUX_PIN_E_IO_HV_HIGH,
+	PMUX_PIN_E_IO_HV_DEFAULT,
 };
 #endif
 
diff --git a/arch/arm/include/asm/arch-tegra124/pinmux.h b/arch/arm/include/asm/arch-tegra124/pinmux.h
index 3aba17d21e4..fbe15fc612d 100644
--- a/arch/arm/include/asm/arch-tegra124/pinmux.h
+++ b/arch/arm/include/asm/arch-tegra124/pinmux.h
@@ -578,6 +578,10 @@ static const char * const tegra_pinctrl_to_drvgrp[] = {
 	[PMUX_DRVGRP_AO4] = "ao4",
 };
 
+static const char * const tegra_pinctrl_to_mipipadgrp[] = {
+	[PMUX_MIPIPADCTRLGRP_DSI_B] = "mipi_pad_ctrl_dsi_b",
+};
+
 static const char * const tegra_pinctrl_to_func[] = {
 	[PMUX_FUNC_DEFAULT] = "default",
 	[PMUX_FUNC_BLINK] = "blink",
diff --git a/arch/arm/include/asm/arch-tegra20/clock-tables.h b/arch/arm/include/asm/arch-tegra20/clock-tables.h
index 861b3d5d07c..82685353bd1 100644
--- a/arch/arm/include/asm/arch-tegra20/clock-tables.h
+++ b/arch/arm/include/asm/arch-tegra20/clock-tables.h
@@ -32,6 +32,7 @@ enum clock_id {
 
 	CLOCK_ID_COUNT,	/* number of clocks */
 	CLOCK_ID_NONE = -1,
+	CLOCK_ID_DISPLAY2 = CLOCK_ID_NONE, /* for compatibility */
 };
 
 /* The clocks supported by the hardware */
@@ -159,6 +160,7 @@ enum periph_id {
 
 	PERIPH_ID_COUNT,
 	PERIPH_ID_NONE = -1,
+	PERIPH_ID_DSIB = CLOCK_ID_NONE, /* for compatibility */
 };
 
 enum pll_out_id {
diff --git a/arch/arm/include/asm/arch-tegra20/pinmux.h b/arch/arm/include/asm/arch-tegra20/pinmux.h
index 8c8579e87e3..9598851b100 100644
--- a/arch/arm/include/asm/arch-tegra20/pinmux.h
+++ b/arch/arm/include/asm/arch-tegra20/pinmux.h
@@ -467,14 +467,14 @@ static const char * const tegra_pinctrl_to_func[] = {
 	[PMUX_FUNC_DAP3] = "dap3",
 	[PMUX_FUNC_DAP4] = "dap4",
 	[PMUX_FUNC_DAP5] = "dap5",
-	[PMUX_FUNC_DISPA] = "dispa",
-	[PMUX_FUNC_DISPB] = "dispb",
+	[PMUX_FUNC_DISPA] = "displaya",
+	[PMUX_FUNC_DISPB] = "displayb",
 	[PMUX_FUNC_EMC_TEST0_DLL] = "emc_test0_dll",
 	[PMUX_FUNC_EMC_TEST1_DLL] = "emc_test1_dll",
 	[PMUX_FUNC_GMI] = "gmi",
 	[PMUX_FUNC_GMI_INT] = "gmi_int",
 	[PMUX_FUNC_HDMI] = "hdmi",
-	[PMUX_FUNC_I2C] = "i2c",
+	[PMUX_FUNC_I2C] = "i2c1",
 	[PMUX_FUNC_I2C2] = "i2c2",
 	[PMUX_FUNC_I2C3] = "i2c3",
 	[PMUX_FUNC_IDE] = "ide",
diff --git a/arch/arm/include/asm/armv8/cpu.h b/arch/arm/include/asm/armv8/cpu.h
index 4dbb589aab8..e906fdf1bf1 100644
--- a/arch/arm/include/asm/armv8/cpu.h
+++ b/arch/arm/include/asm/armv8/cpu.h
@@ -5,8 +5,11 @@
 
 #define MIDR_PARTNUM_CORTEX_A35		0xD04
 #define MIDR_PARTNUM_CORTEX_A53		0xD03
+#define MIDR_PARTNUM_CORTEX_A55		0xD05
 #define MIDR_PARTNUM_CORTEX_A57		0xD07
 #define MIDR_PARTNUM_CORTEX_A72		0xD08
+#define MIDR_PARTNUM_CORTEX_A73		0xD09
+#define MIDR_PARTNUM_CORTEX_A75		0xD0A
 #define MIDR_PARTNUM_CORTEX_A76		0xD0B
 #define MIDR_PARTNUM_SHIFT		0x4
 #define MIDR_PARTNUM_MASK		(0xFFF << MIDR_PARTNUM_SHIFT)
@@ -31,6 +34,9 @@ static inline unsigned int read_midr(void)
 
 is_cortex_a(35)
 is_cortex_a(53)
+is_cortex_a(55)
 is_cortex_a(57)
 is_cortex_a(72)
+is_cortex_a(73)
+is_cortex_a(75)
 is_cortex_a(76)
diff --git a/arch/arm/include/asm/armv8/mmu.h b/arch/arm/include/asm/armv8/mmu.h
index 0ab681c893d..6af8cd111a4 100644
--- a/arch/arm/include/asm/armv8/mmu.h
+++ b/arch/arm/include/asm/armv8/mmu.h
@@ -66,6 +66,7 @@
 #define PTE_BLOCK_NG		(1 << 11)
 #define PTE_BLOCK_PXN		(UL(1) << 53)
 #define PTE_BLOCK_UXN		(UL(1) << 54)
+#define PTE_BLOCK_RO            (UL(1) << 7)
 
 /*
  * AttrIndx[2:0]
@@ -75,6 +76,7 @@
 #define PMD_ATTRMASK		(PTE_BLOCK_PXN		| \
 				 PTE_BLOCK_UXN		| \
 				 PMD_ATTRINDX_MASK	| \
+				 PTE_BLOCK_RO		| \
 				 PTE_TYPE_VALID)
 
 /*
diff --git a/arch/arm/include/asm/setjmp.h b/arch/arm/include/asm/setjmp.h
index 662bec86321..a9eccf7f632 100644
--- a/arch/arm/include/asm/setjmp.h
+++ b/arch/arm/include/asm/setjmp.h
@@ -4,13 +4,11 @@
  * (C) Copyright 2016 Alexander Graf <agraf@suse.de>
  */
 
-#ifndef _SETJMP_H_
-#define _SETJMP_H_	1
+#ifndef _ASM_SETJMP_H_
+#define _ASM_SETJMP_H_	1
+
+#include <asm-generic/int-ll64.h>
 
-/*
- * This really should be opaque, but the EFI implementation wrongly
- * assumes that a 'struct jmp_buf_data' is defined.
- */
 struct jmp_buf_data {
 #if defined(__aarch64__)
 	u64  regs[13];
@@ -19,9 +17,4 @@ struct jmp_buf_data {
 #endif
 };
 
-typedef struct jmp_buf_data jmp_buf[1];
-
-int setjmp(jmp_buf jmp);
-void longjmp(jmp_buf jmp, int ret);
-
-#endif /* _SETJMP_H_ */
+#endif /* _ASM_SETJMP_H_ */
diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h
index 091082281c7..849b3d0efb7 100644
--- a/arch/arm/include/asm/system.h
+++ b/arch/arm/include/asm/system.h
@@ -303,8 +303,26 @@ void flush_l3_cache(void);
  * @emerg: Also map the region in the emergency table
  */
 void mmu_map_region(phys_addr_t start, u64 size, bool emerg);
+
+/**
+ * mmu_change_region_attr() - change a mapped region attributes
+ *
+ * @start: Start address of the region
+ * @size:  Size of the region
+ * @aatrs: New attributes
+ */
 void mmu_change_region_attr(phys_addr_t start, size_t size, u64 attrs);
 
+/**
+ * mmu_change_region_attr_nobreak() - change a mapped region attributes without doing
+ *                                    break-before-make
+ *
+ * @start: Start address of the region
+ * @size:  Size of the region
+ * @aatrs: New attributes
+ */
+void mmu_change_region_attr_nobreak(phys_addr_t addr, size_t size, u64 attrs);
+
 /*
  * smc_call() - issue a secure monitor call
  *
diff --git a/arch/arm/lib/Makefile b/arch/arm/lib/Makefile
index 1c95dd6fed2..74cd5051552 100644
--- a/arch/arm/lib/Makefile
+++ b/arch/arm/lib/Makefile
@@ -92,6 +92,7 @@ obj-$(CONFIG_GENERATE_ACPI_TABLE) += acpi_table.o
 # For EABI conformant tool chains, provide eabi_compat()
 ifneq (,$(findstring -mabi=aapcs-linux,$(PLATFORM_CPPFLAGS)))
 extra-y	+= eabi_compat.o
+CFLAGS_REMOVE_eabi_compat.o := $(LTO_CFLAGS)
 endif
 
 # some files can only build in ARM or THUMB2, not THUMB1
diff --git a/arch/arm/lib/bootm.c b/arch/arm/lib/bootm.c
index 974cbfe8400..7eb764e1f4e 100644
--- a/arch/arm/lib/bootm.c
+++ b/arch/arm/lib/bootm.c
@@ -61,10 +61,6 @@ static void announce_and_cleanup(int fake)
 	bootstage_report();
 #endif
 
-#ifdef CONFIG_USB_DEVICE
-	udc_disconnect();
-#endif
-
 	board_quiesce_devices();
 
 	printf("\nStarting kernel ...%s\n\n", fake ?
diff --git a/arch/arm/lib/cache.c b/arch/arm/lib/cache.c
index 516754caeaf..dd19bd3e4fb 100644
--- a/arch/arm/lib/cache.c
+++ b/arch/arm/lib/cache.c
@@ -10,6 +10,7 @@
 #include <malloc.h>
 #include <asm/cache.h>
 #include <asm/global_data.h>
+#include <linux/errno.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -170,3 +171,8 @@ __weak int arm_reserve_mmu(void)
 
 	return 0;
 }
+
+int __weak pgprot_set_attrs(phys_addr_t addr, size_t size, enum pgprot_attrs perm)
+{
+	return -ENOSYS;
+}
diff --git a/arch/arm/lib/crt0.S b/arch/arm/lib/crt0.S
index 3e4906e273d..a50dde60e8b 100644
--- a/arch/arm/lib/crt0.S
+++ b/arch/arm/lib/crt0.S
@@ -100,10 +100,8 @@ ENTRY(_main)
  * Set up initial C runtime environment and call board_init_f(0).
  */
 
-#if defined(CONFIG_TPL_BUILD) && defined(CONFIG_TPL_NEEDS_SEPARATE_STACK)
-	ldr	r0, =(CONFIG_TPL_STACK)
-#elif defined(CONFIG_XPL_BUILD) && defined(CONFIG_SPL_STACK)
-	ldr	r0, =(CONFIG_SPL_STACK)
+#if CONFIG_IS_ENABLED(HAVE_INIT_STACK)
+	ldr	r0, =CONFIG_VAL(STACK)
 #else
 	ldr	r0, =(SYS_INIT_SP_ADDR)
 #endif
diff --git a/arch/arm/lib/crt0_64.S b/arch/arm/lib/crt0_64.S
index 32401f544a7..30950ddaf9b 100644
--- a/arch/arm/lib/crt0_64.S
+++ b/arch/arm/lib/crt0_64.S
@@ -69,10 +69,8 @@ ENTRY(_main)
 /*
  * Set up initial C runtime environment and call board_init_f(0).
  */
-#if defined(CONFIG_TPL_BUILD) && defined(CONFIG_TPL_NEEDS_SEPARATE_STACK)
-	ldr	x0, =(CONFIG_TPL_STACK)
-#elif defined(CONFIG_XPL_BUILD) && defined(CONFIG_SPL_STACK)
-	ldr	x0, =(CONFIG_SPL_STACK)
+#if CONFIG_IS_ENABLED(HAVE_INIT_STACK)
+	ldr	x0, =CONFIG_VAL(STACK)
 #elif defined(CONFIG_INIT_SP_RELATIVE)
 #if CONFIG_POSITION_INDEPENDENT
 	adrp	x0, __bss_start     /* x0 <- Runtime &__bss_start */
diff --git a/arch/arm/lib/crt0_arm_efi.S b/arch/arm/lib/crt0_arm_efi.S
index 1e7de5c3343..593ee1e194a 100644
--- a/arch/arm/lib/crt0_arm_efi.S
+++ b/arch/arm/lib/crt0_arm_efi.S
@@ -150,7 +150,8 @@ _start:
 	adr		r1, .L_DYNAMIC
 	ldr		r0, [r1]
 	add		r1, r0, r1
-	adrl		r0, image_base
+	sub		r0, pc, #((.+8-image_base) & 0xff)
+	sub		r0, r0, #((.+4-image_base) & 0xff00)
 	bl		_relocate
 	teq		r0, #0
 	bne		0f
diff --git a/arch/arm/lib/eabi_compat.c b/arch/arm/lib/eabi_compat.c
index 602efe04c04..e6cafcc5f2b 100644
--- a/arch/arm/lib/eabi_compat.c
+++ b/arch/arm/lib/eabi_compat.c
@@ -33,7 +33,24 @@ void __aeabi_memcpy(void *dest, const void *src, size_t n)
 	(void) memcpy(dest, src, n);
 }
 
+void __aeabi_memcpy4(void *dest, const void *src, size_t n) __alias(__aeabi_memcpy);
+
+void __aeabi_memcpy8(void *dest, const void *src, size_t n) __alias(__aeabi_memcpy);
+
 void __aeabi_memset(void *dest, size_t n, int c)
 {
 	(void) memset(dest, c, n);
 }
+
+void __aeabi_memset4(void *dest, size_t n, int c) __alias(__aeabi_memset);
+
+void __aeabi_memset8(void *dest, size_t n, int c) __alias(__aeabi_memset);
+
+void __aeabi_memclr(void *dest, size_t n)
+{
+	(void) memset(dest, 0, n);
+}
+
+void __aeabi_memclr4(void *dest, size_t n) __alias(__aeabi_memclr);
+
+void __aeabi_memclr8(void *dest, size_t n) __alias(__aeabi_memclr);
diff --git a/arch/arm/lib/relocate.S b/arch/arm/lib/relocate.S
index 345e282e3e6..bffadfecba1 100644
--- a/arch/arm/lib/relocate.S
+++ b/arch/arm/lib/relocate.S
@@ -83,8 +83,6 @@ relocate_base:
 	add	r1, r3			/* r1 <- Run &__image_copy_start */
 	subs	r4, r0, r1		/* r4 <- Run to copy offset      */
 	beq	relocate_done		/* skip relocation               */
-	ldr	r1, _image_copy_start_ofs
-	add	r1, r3			/* r1 <- Run &__image_copy_start */
 	ldr	r2, _image_copy_end_ofs
 	add	r2, r3			/* r2 <- Run &__image_copy_end   */
 copy_loop:
diff --git a/arch/arm/lib/xferlist.c b/arch/arm/lib/xferlist.c
index f9c5d88bd47..6425936d354 100644
--- a/arch/arm/lib/xferlist.c
+++ b/arch/arm/lib/xferlist.c
@@ -8,18 +8,16 @@
 #include <bloblist.h>
 #include "xferlist.h"
 
-int xferlist_from_boot_arg(ulong addr, ulong size)
+int xferlist_from_boot_arg(ulong *addr)
 {
 	int ret;
 
-	ret = bloblist_check(saved_args[3], size);
-	if (ret)
-		return ret;
-
 	ret = bloblist_check_reg_conv(saved_args[0], saved_args[2],
-				      saved_args[1]);
+				      saved_args[1], saved_args[3]);
 	if (ret)
 		return ret;
 
-	return bloblist_reloc((void *)addr, size);
+	*addr = bloblist_get_base();
+
+	return 0;
 }
diff --git a/arch/arm/mach-airoha/Kconfig b/arch/arm/mach-airoha/Kconfig
new file mode 100644
index 00000000000..be3562ae3ff
--- /dev/null
+++ b/arch/arm/mach-airoha/Kconfig
@@ -0,0 +1,32 @@
+if ARCH_AIROHA
+
+config SYS_VENDOR
+	default "airoha"
+
+choice
+	prompt "Airoha board select"
+
+config TARGET_AN7581
+	bool "Airoha AN7581 SoC"
+	select ARM64
+	help
+	  The Airoha EN7581 is a ARM-based SoC with a quad-core Cortex-A7
+	  including NEON and GPU, Mali-450 graphics, several DDR3 options,
+	  crypto engine, built-in Wi-Fi / Bluetooth combo chip, JPEG decoder,
+	  video interfaces supporting HDMI and MIPI, and video codec support.
+	  Peripherals include Gigabit Ethernet, switch, USB3.0 and OTG, PCIe,
+	  I2S, PCM, S/PDIF, UART, SPI, I2C, IR TX/RX, and PWM.
+
+endchoice
+
+config SYS_SOC
+	default "an7581" if TARGET_AN7581
+
+config SYS_BOARD
+	default "an7581" if TARGET_AN7581
+
+config SYS_CONFIG_NAME
+	default "an7581" if TARGET_AN7581
+
+endif
+
diff --git a/arch/arm/mach-airoha/Makefile b/arch/arm/mach-airoha/Makefile
new file mode 100644
index 00000000000..215a300373b
--- /dev/null
+++ b/arch/arm/mach-airoha/Makefile
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier:	GPL-2.0
+
+obj-y	+= cpu.o
+
+obj-$(CONFIG_TARGET_AN7581) += an7581/
diff --git a/arch/arm/mach-airoha/an7581/Makefile b/arch/arm/mach-airoha/an7581/Makefile
new file mode 100644
index 00000000000..886ab7e4eb9
--- /dev/null
+++ b/arch/arm/mach-airoha/an7581/Makefile
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier:	GPL-2.0
+
+obj-y += init.o
diff --git a/arch/arm/mach-airoha/an7581/init.c b/arch/arm/mach-airoha/an7581/init.c
new file mode 100644
index 00000000000..cefe9c6db9e
--- /dev/null
+++ b/arch/arm/mach-airoha/an7581/init.c
@@ -0,0 +1,47 @@
+// SPDX-License-Identifier: GPL-2.0
+
+#include <fdtdec.h>
+#include <init.h>
+#include <asm/armv8/mmu.h>
+#include <asm/system.h>
+
+int print_cpuinfo(void)
+{
+	printf("CPU:   Airoha AN7581\n");
+	return 0;
+}
+
+int dram_init(void)
+{
+	return fdtdec_setup_mem_size_base();
+}
+
+int dram_init_banksize(void)
+{
+	return fdtdec_setup_memory_banksize();
+}
+
+void reset_cpu(ulong addr)
+{
+	psci_system_reset();
+}
+
+static struct mm_region an7581_mem_map[] = {
+	{
+		/* DDR */
+		.virt = 0x80000000UL,
+		.phys = 0x80000000UL,
+		.size = 0x80000000UL,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE,
+	}, {
+		.virt = 0x00000000UL,
+		.phys = 0x00000000UL,
+		.size = 0x20000000UL,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+			 PTE_BLOCK_NON_SHARE |
+			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
+	}, {
+		0,
+	}
+};
+struct mm_region *mem_map = an7581_mem_map;
diff --git a/arch/arm/mach-airoha/cpu.c b/arch/arm/mach-airoha/cpu.c
new file mode 100644
index 00000000000..a578e964664
--- /dev/null
+++ b/arch/arm/mach-airoha/cpu.c
@@ -0,0 +1,20 @@
+// SPDX-License-Identifier: GPL-2.0
+
+#include <cpu_func.h>
+#include <dm.h>
+#include <init.h>
+#include <wdt.h>
+#include <dm/uclass-internal.h>
+
+int arch_cpu_init(void)
+{
+	icache_enable();
+
+	return 0;
+}
+
+void enable_caches(void)
+{
+	/* Enable D-cache. I-cache is already enabled in start.S */
+	dcache_enable();
+}
diff --git a/arch/arm/mach-imx/imx8/Kconfig b/arch/arm/mach-imx/imx8/Kconfig
index 9a43beda6fa..257c14e61b6 100644
--- a/arch/arm/mach-imx/imx8/Kconfig
+++ b/arch/arm/mach-imx/imx8/Kconfig
@@ -9,6 +9,8 @@ config AHAB_BOOT
 config IMX8
 	bool
 	select HAS_CAAM
+	imply CPU
+	imply CPU_IMX
 
 config MU_BASE_SPL
 	hex "MU base address used in SPL"
diff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach-imx/imx8m/Kconfig
index 89f2b50c8a2..31f2f003d35 100644
--- a/arch/arm/mach-imx/imx8m/Kconfig
+++ b/arch/arm/mach-imx/imx8m/Kconfig
@@ -8,6 +8,9 @@ config IMX8M
 	select LTO
 	select ROM_UNIFIED_SECTIONS
 	select ARMV8_CRYPTO
+	imply CPU
+	imply CPU_IMX
+	imply IMX_TMU
 
 config IMX8MQ
 	bool
diff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/mach-imx/imx8m/soc.c
index 85dc8b51a14..567e8e9e81a 100644
--- a/arch/arm/mach-imx/imx8m/soc.c
+++ b/arch/arm/mach-imx/imx8m/soc.c
@@ -1270,8 +1270,9 @@ static int ft_add_optee_node(void *fdt, struct bd_info *bd)
 		}
 	}
 
+	/* Locate the optee node if it exists or create it. */
 	subpath = "optee";
-	offs = fdt_add_subnode(fdt, offs, subpath);
+	offs = fdt_find_or_add_subnode(fdt, offs, subpath);
 	if (offs < 0) {
 		printf("Could not create %s node.\n", subpath);
 		return offs;
diff --git a/arch/arm/mach-imx/imx9/Kconfig b/arch/arm/mach-imx/imx9/Kconfig
index 49220c0955e..1ccdb1cf64f 100644
--- a/arch/arm/mach-imx/imx9/Kconfig
+++ b/arch/arm/mach-imx/imx9/Kconfig
@@ -8,8 +8,11 @@ config AHAB_BOOT
 config IMX9
 	bool
 	select BINMAN
+	select CPU
+	select CPU_IMX
 	select HAS_CAAM
 	select ROM_UNIFIED_SECTIONS
+	imply IMX_TMU
 
 config IMX93
 	bool
diff --git a/arch/arm/mach-imx/imx9/container.cfg b/arch/arm/mach-imx/imx9/container.cfg
index 91a973161d1..a018c365c82 100644
--- a/arch/arm/mach-imx/imx9/container.cfg
+++ b/arch/arm/mach-imx/imx9/container.cfg
@@ -12,4 +12,6 @@ IMAGE A55 bl31.bin 0x204C0000
 IMAGE A55 bl31.bin 0x204E0000
 #endif
 IMAGE A55 u-boot.bin CONFIG_TEXT_BASE
+#ifdef CONFIG_OPTEE
 IMAGE A55 tee.bin 0x96000000
+#endif
diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig
index 4020e16d92d..2f873ed6ddf 100644
--- a/arch/arm/mach-imx/mx6/Kconfig
+++ b/arch/arm/mach-imx/mx6/Kconfig
@@ -550,6 +550,7 @@ config TARGET_LXR2
 	select DM_THERMAL
 	select SUPPORT_SPL
 	imply CMD_DM
+	imply OF_UPSTREAM
 
 config TARGET_PCM058
 	bool "Phytec PCM058 i.MX6 Quad"
diff --git a/arch/arm/mach-k3/Kconfig b/arch/arm/mach-k3/Kconfig
index a3ac490f677..1b8c0b1eb96 100644
--- a/arch/arm/mach-k3/Kconfig
+++ b/arch/arm/mach-k3/Kconfig
@@ -22,6 +22,9 @@ config SOC_K3_AM654
 config SOC_K3_J721E
 	bool "TI's K3 based J721E SoC Family Support"
 
+config SOC_K3_J7200
+	bool "TI's K3 based J7200 SoC Family Support"
+
 config SOC_K3_J721S2
 	bool "TI's K3 based J721S2 SoC Family Support"
 
@@ -33,18 +36,13 @@ config SOC_K3_J784S4
 
 endchoice
 
-if SOC_K3_J721E
-config SOC_K3_J721E_J7200
-	bool "TI's K3 based J7200 SoC variant Family Support"
-endif
-
 config SYS_SOC
 	default "k3"
 
 config SYS_K3_NON_SECURE_MSRAM_SIZE
 	hex
 	default 0x80000 if SOC_K3_AM654
-	default 0x100000 if SOC_K3_J721E || SOC_K3_J721S2 || SOC_K3_J784S4
+	default 0x100000 if SOC_K3_J721E || SOC_K3_J7200 || SOC_K3_J721S2 || SOC_K3_J784S4
 	default 0x1c0000 if SOC_K3_AM642
 	default 0x3c000 if SOC_K3_AM625 || SOC_K3_AM62A7
 	help
@@ -56,7 +54,7 @@ config SYS_K3_NON_SECURE_MSRAM_SIZE
 config SYS_K3_MAX_DOWNLODABLE_IMAGE_SIZE
 	hex
 	default 0x58000 if SOC_K3_AM654
-	default 0xc0000 if SOC_K3_J721E || SOC_K3_J721S2 || SOC_K3_J784S4
+	default 0xc0000 if SOC_K3_J721E || SOC_K3_J7200 || SOC_K3_J721S2 || SOC_K3_J784S4
 	default 0x180000 if SOC_K3_AM642
 	default 0x38000 if SOC_K3_AM625 || SOC_K3_AM62A7
 	help
@@ -66,21 +64,21 @@ config SYS_K3_MAX_DOWNLODABLE_IMAGE_SIZE
 config SYS_K3_MCU_SCRATCHPAD_BASE
 	hex
 	default 0x40280000 if SOC_K3_AM654
-	default 0x41cff9fc if SOC_K3_J721E || SOC_K3_J721S2 || SOC_K3_J784S4
+	default 0x41cff9fc if SOC_K3_J721E || SOC_K3_J7200 || SOC_K3_J721S2 || SOC_K3_J784S4
 	help
 	  Describes the base address of MCU Scratchpad RAM.
 
 config SYS_K3_MCU_SCRATCHPAD_SIZE
 	hex
 	default 0x200 if SOC_K3_AM654
-	default 0x200 if SOC_K3_J721E || SOC_K3_J721S2 || SOC_K3_J784S4
+	default 0x200 if SOC_K3_J721E || SOC_K3_J7200 || SOC_K3_J721S2 || SOC_K3_J784S4
 	help
 	  Describes the size of MCU Scratchpad RAM.
 
 config SYS_K3_BOOT_PARAM_TABLE_INDEX
 	hex
 	default 0x41c7fbfc if SOC_K3_AM654
-	default 0x41cffbfc if SOC_K3_J721E
+	default 0x41cffbfc if SOC_K3_J721E || SOC_K3_J7200
 	default 0x41cfdbfc if SOC_K3_J721S2 || SOC_K3_J784S4
 	default 0x701bebfc if SOC_K3_AM642
 	default 0x43c3f290 if SOC_K3_AM625
@@ -159,6 +157,30 @@ config K3_X509_SWRV
 config NR_DRAM_BANKS
 	default 2
 
+config K3_REMOTEPROC_R5F
+	bool "Enable K3 Remoteproc driver for R5F"
+	depends on ARM64
+	imply REMOTEPROC_TI_K3_R5F
+	default y if (SOC_K3_AM62A7 || SOC_K3_AM654 || SOC_K3_J721E || SOC_K3_J784S4 || SOC_K3_J721S2 || SOC_K3_J722S || SOC_K3_AM62P5 || SOC_K3_AM642)
+
+config K3_REMOTEPROC_DSP
+	bool "Enable K3 Remoteproc driver for DSP"
+	depends on ARM64
+	imply REMOTEPROC_TI_K3_DSP
+	default y if (SOC_K3_AM62A7 || SOC_K3_J721E || SOC_K3_J784S4 || SOC_K3_J721S2 || SOC_K3_J722S)
+
+config K3_REMOTEPROC_M4F
+	bool "Enable K3 Remoteproc driver for M4F"
+	depends on ARM64
+	imply REMOTEPROC_TI_K3_M4F
+	default y if (SOC_K3_AM625 || SOC_K3_AM642)
+
+config K3_REMOTEPROC_PRU
+	bool "Enable K3 Remoteproc driver for PRU"
+	depends on ARM64
+	imply REMOTEPROC_TI_PRU
+	default y if (SOC_K3_AM642 || SOC_K3_AM654)
+
 if CPU_V7R
 source "arch/arm/mach-k3/r5/Kconfig"
 endif
@@ -169,6 +191,7 @@ source "arch/arm/mach-k3/am62x/Kconfig"
 source "arch/arm/mach-k3/am62ax/Kconfig"
 source "arch/arm/mach-k3/am62px/Kconfig"
 source "arch/arm/mach-k3/j721e/Kconfig"
+source "arch/arm/mach-k3/j7200/Kconfig"
 source "arch/arm/mach-k3/j721s2/Kconfig"
 source "arch/arm/mach-k3/j722s/Kconfig"
 source "arch/arm/mach-k3/j784s4/Kconfig"
diff --git a/arch/arm/mach-k3/Makefile b/arch/arm/mach-k3/Makefile
index 5ce7fc62d80..b2fd5810b67 100644
--- a/arch/arm/mach-k3/Makefile
+++ b/arch/arm/mach-k3/Makefile
@@ -13,6 +13,7 @@ obj-$(CONFIG_SOC_K3_AM625) += am62x/
 obj-$(CONFIG_SOC_K3_AM642) += am64x/
 obj-$(CONFIG_SOC_K3_AM654) += am65x/
 obj-$(CONFIG_SOC_K3_J721E) += j721e/
+obj-$(CONFIG_SOC_K3_J7200) += j7200/
 obj-$(CONFIG_SOC_K3_J721S2) += j721s2/
 obj-$(CONFIG_SOC_K3_J722S) += j722s/
 obj-$(CONFIG_SOC_K3_J784S4) += j784s4/
diff --git a/arch/arm/mach-k3/am65x/Kconfig b/arch/arm/mach-k3/am65x/Kconfig
index 72a8298aebf..056ae118c9e 100644
--- a/arch/arm/mach-k3/am65x/Kconfig
+++ b/arch/arm/mach-k3/am65x/Kconfig
@@ -35,6 +35,8 @@ config TARGET_IOT2050_A53
 	select BOARD_LATE_INIT
 	select SYS_DISABLE_DCACHE_OPS
 	select BINMAN
+	select SYSINFO
+	select SPL_SYSINFO if SPL
 	help
 	  This builds U-Boot for the IOT2050 devices.
 
diff --git a/arch/arm/mach-k3/common_fdt.c b/arch/arm/mach-k3/common_fdt.c
index 4a016711566..361b0c0b31b 100644
--- a/arch/arm/mach-k3/common_fdt.c
+++ b/arch/arm/mach-k3/common_fdt.c
@@ -122,10 +122,8 @@ int fdt_fixup_reserved(void *blob, const char *name,
 
 	/* Find reserved-memory */
 	nodeoffset = fdt_subnode_offset(blob, 0, "reserved-memory");
-	if (nodeoffset < 0) {
-		debug("Could not find reserved-memory node\n");
-		return 0;
-	}
+	if (nodeoffset < 0)
+		goto add_carveout;
 
 	/* Find existing matching subnode and remove it */
 	fdt_for_each_subnode(subnode, blob, nodeoffset) {
@@ -154,6 +152,7 @@ int fdt_fixup_reserved(void *blob, const char *name,
 		}
 	}
 
+add_carveout:
 	struct fdt_memory carveout = {
 		.start = new_address,
 		.end = new_address + new_size - 1,
diff --git a/arch/arm/mach-k3/include/mach/hardware.h b/arch/arm/mach-k3/include/mach/hardware.h
index b191d53a0f5..fc7bee4d00b 100644
--- a/arch/arm/mach-k3/include/mach/hardware.h
+++ b/arch/arm/mach-k3/include/mach/hardware.h
@@ -32,6 +32,10 @@
 #include "j721e_hardware.h"
 #endif
 
+#ifdef CONFIG_SOC_K3_J7200
+#include "j721e_hardware.h"
+#endif
+
 #ifdef CONFIG_SOC_K3_J721S2
 #include "j721s2_hardware.h"
 #endif
@@ -62,6 +66,12 @@
 #define JTAG_ID_PARTNO_J722S	0xbba0
 #define JTAG_ID_PARTNO_J784S4	0xbb80
 
+#define CTRLMMR_WKUP_JTAG_DEVICE_ID		(WKUP_CTRL_MMR0_BASE + 0x18)
+#define JTAG_DEV_J742S2_PKG_MASK		GENMASK(2, 0)
+#define JTAG_DEV_J742S2_PKG_SHIFT		0
+
+#define JTAG_ID_PKG_J742S2	0x7
+
 #define K3_SOC_ID(id, ID) \
 static inline bool soc_is_##id(void) \
 { \
diff --git a/arch/arm/mach-k3/include/mach/k3-ddr.h b/arch/arm/mach-k3/include/mach/k3-ddr.h
index 95496e1c59d..39e6725bb9b 100644
--- a/arch/arm/mach-k3/include/mach/k3-ddr.h
+++ b/arch/arm/mach-k3/include/mach/k3-ddr.h
@@ -6,6 +6,8 @@
 #ifndef _K3_DDR_H_
 #define _K3_DDR_H_
 
+#include <spl.h>
+
 int dram_init(void);
 int dram_init_banksize(void);
 
diff --git a/arch/arm/mach-k3/include/mach/spl.h b/arch/arm/mach-k3/include/mach/spl.h
index ac1a34502ed..a47441ae6a5 100644
--- a/arch/arm/mach-k3/include/mach/spl.h
+++ b/arch/arm/mach-k3/include/mach/spl.h
@@ -14,6 +14,10 @@
 #include "j721e_spl.h"
 #endif
 
+#ifdef CONFIG_SOC_K3_J7200
+#include "j721e_spl.h"
+#endif
+
 #ifdef CONFIG_SOC_K3_J721S2
 #include "j721s2_spl.h"
 #endif
diff --git a/arch/arm/mach-k3/j7200/Kconfig b/arch/arm/mach-k3/j7200/Kconfig
new file mode 100644
index 00000000000..399daad8767
--- /dev/null
+++ b/arch/arm/mach-k3/j7200/Kconfig
@@ -0,0 +1,36 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2025 Texas Instruments Incorporated - https://www.ti.com/
+#	Andrew Davis <afd@ti.com>
+
+if SOC_K3_J7200
+
+choice
+	prompt "K3 J7200 based boards"
+	optional
+
+config TARGET_J7200_A72_EVM
+	bool "TI K3 based J7200 EVM running on A72"
+	select ARM64
+	select BOARD_LATE_INIT
+	imply TI_I2C_BOARD_DETECT
+	select SYS_DISABLE_DCACHE_OPS
+	select BINMAN
+
+config TARGET_J7200_R5_EVM
+	bool "TI K3 based J7200 EVM running on R5"
+	select CPU_V7R
+	select SYS_THUMB_BUILD
+	select K3_LOAD_SYSFW
+	select RAM
+	select SPL_RAM
+	select K3_DDRSS
+	select BINMAN
+	imply SYS_K3_SPL_ATF
+	imply TI_I2C_BOARD_DETECT
+
+endchoice
+
+source "board/ti/j7200/Kconfig"
+
+endif
diff --git a/arch/arm/mach-k3/j7200/Makefile b/arch/arm/mach-k3/j7200/Makefile
new file mode 100644
index 00000000000..6d3ff36e363
--- /dev/null
+++ b/arch/arm/mach-k3/j7200/Makefile
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2025 Texas Instruments Incorporated - https://www.ti.com/
+#	Andrew Davis <afd@ti.com>
+
+obj-$(CONFIG_OF_SYSTEM_SETUP) += ../j721e/j721e_fdt.o
+obj-$(CONFIG_XPL_BUILD) += ../j721e/j721e_init.o
diff --git a/arch/arm/mach-k3/j721e/Kconfig b/arch/arm/mach-k3/j721e/Kconfig
index 0761b82b15a..4d01f2c8af2 100644
--- a/arch/arm/mach-k3/j721e/Kconfig
+++ b/arch/arm/mach-k3/j721e/Kconfig
@@ -29,27 +29,6 @@ config TARGET_J721E_R5_EVM
 	imply SYS_K3_SPL_ATF
 	imply TI_I2C_BOARD_DETECT
 
-config TARGET_J7200_A72_EVM
-	bool "TI K3 based J7200 EVM running on A72"
-	select ARM64
-	select SOC_K3_J721E_J7200
-	select BOARD_LATE_INIT
-	imply TI_I2C_BOARD_DETECT
-	select SYS_DISABLE_DCACHE_OPS
-	select BINMAN
-
-config TARGET_J7200_R5_EVM
-	bool "TI K3 based J7200 EVM running on R5"
-	select CPU_V7R
-	select SYS_THUMB_BUILD
-	select K3_LOAD_SYSFW
-	select RAM
-	select SPL_RAM
-	select K3_DDRSS
-	select BINMAN
-	imply SYS_K3_SPL_ATF
-	imply TI_I2C_BOARD_DETECT
-
 endchoice
 
 source "board/beagle/beagleboneai64/Kconfig"
diff --git a/arch/arm/mach-k3/j721e/j721e_init.c b/arch/arm/mach-k3/j721e/j721e_init.c
index 7e2d2c16b45..f31c20f7ed6 100644
--- a/arch/arm/mach-k3/j721e/j721e_init.c
+++ b/arch/arm/mach-k3/j721e/j721e_init.c
@@ -48,7 +48,7 @@
 
 #ifdef CONFIG_K3_LOAD_SYSFW
 struct fwl_data cbass_hc_cfg0_fwls[] = {
-#if defined(CONFIG_TARGET_J721E_R5_EVM)
+#if defined(CONFIG_SOC_K3_J721E)
 	{ "PCIE0_CFG", 2560, 8 },
 	{ "PCIE1_CFG", 2561, 8 },
 	{ "USB3SS0_CORE", 2568, 4 },
@@ -57,11 +57,11 @@ struct fwl_data cbass_hc_cfg0_fwls[] = {
 	{ "UFS_HCI0_CFG", 2580, 4 },
 	{ "SERDES0", 2584, 1 },
 	{ "SERDES1", 2585, 1 },
-#elif defined(CONFIG_TARGET_J7200_R5_EVM)
+#elif defined(CONFIG_SOC_K3_J7200)
 	{ "PCIE1_CFG", 2561, 7 },
 #endif
 }, cbass_hc0_fwls[] = {
-#if defined(CONFIG_TARGET_J721E_R5_EVM)
+#if defined(CONFIG_SOC_K3_J721E)
 	{ "PCIE0_HP", 2528, 24 },
 	{ "PCIE0_LP", 2529, 24 },
 	{ "PCIE1_HP", 2530, 24 },
diff --git a/arch/arm/mach-k3/j722s/Kconfig b/arch/arm/mach-k3/j722s/Kconfig
index 39d38ea5cf5..fe76d77e58a 100644
--- a/arch/arm/mach-k3/j722s/Kconfig
+++ b/arch/arm/mach-k3/j722s/Kconfig
@@ -26,8 +26,26 @@ config TARGET_J722S_R5_EVM
 	select BINMAN
 	imply SYS_K3_SPL_ATF
 
+config TARGET_J722S_A53_BEAGLEY_AI
+	bool "BeagleBoard.org BeagleY-AI running on A53"
+	select ARM64
+	select BINMAN
+	select OF_SYSTEM_SETUP
+
+config TARGET_J722S_R5_BEAGLEY_AI
+	bool "BeagleBoard.org BeagleY-AI running on R5"
+	select CPU_V7R
+	select SYS_THUMB_BUILD
+	select K3_LOAD_SYSFW
+	select RAM
+	select SPL_RAM
+	select K3_DDRSS
+	select BINMAN
+	imply SYS_K3_SPL_ATF
+
 endchoice
 
 source "board/ti/j722s/Kconfig"
+source "board/beagle/beagley-ai/Kconfig"
 
 endif
diff --git a/arch/arm/mach-k3/j722s/j722s_init.c b/arch/arm/mach-k3/j722s/j722s_init.c
index f8c5c2a5edc..af211377e7c 100644
--- a/arch/arm/mach-k3/j722s/j722s_init.c
+++ b/arch/arm/mach-k3/j722s/j722s_init.c
@@ -27,6 +27,9 @@ struct fwl_data cbass_main_fwls[] = {
 u32 bootindex __section(".data");
 static struct rom_extended_boot_data bootdata __section(".data");
 
+#define CTRLMMR_MCU_RST_CTRL	(MCU_CTRL_MMR0_BASE + 0x18170)
+#define RST_CTRL_ESM_ERROR_RST_EN_Z_MASK  (~BIT(17))
+
 static void store_boot_info_from_rom(void)
 {
 	bootindex = *(u32 *)(CONFIG_SYS_K3_BOOT_PARAM_TABLE_INDEX);
@@ -161,11 +164,40 @@ static void k3_mem_init(void)
 	}
 }
 
+static __maybe_unused void enable_mcu_esm_reset(void)
+{
+	/* Set CTRLMMR_MCU_RST_CTRL:MCU_ESM_ERROR_RST_EN_Z  to '0' (low active) */
+	u32 stat = readl(CTRLMMR_MCU_RST_CTRL);
+
+	stat &= RST_CTRL_ESM_ERROR_RST_EN_Z_MASK;
+	writel(stat, CTRLMMR_MCU_RST_CTRL);
+}
+
 void board_init_f(ulong dummy)
 {
+	int ret;
+	struct udevice *dev;
+
 	k3_spl_init();
 	k3_mem_init();
 	setup_qos();
+
+	if (IS_ENABLED(CONFIG_ESM_K3)) {
+		/* Probe/configure ESM0 */
+		ret = uclass_get_device_by_name(UCLASS_MISC, "esm@420000", &dev);
+		if (ret) {
+			printf("esm main init failed: %d\n", ret);
+			return;
+		}
+
+		/* Probe/configure MCUESM */
+		ret = uclass_get_device_by_name(UCLASS_MISC, "esm@4100000", &dev);
+		if (ret) {
+			printf("esm mcu init failed: %d\n", ret);
+			return;
+		}
+		enable_mcu_esm_reset();
+	}
 }
 
 static u32 __get_backup_bootmedia(u32 devstat)
diff --git a/arch/arm/mach-k3/j784s4/Kconfig b/arch/arm/mach-k3/j784s4/Kconfig
index 1eadfb346a3..84194f6efa8 100644
--- a/arch/arm/mach-k3/j784s4/Kconfig
+++ b/arch/arm/mach-k3/j784s4/Kconfig
@@ -27,6 +27,24 @@ config TARGET_J784S4_R5_EVM
 	select BINMAN
 	imply SYS_K3_SPL_ATF
 
+config TARGET_J742S2_A72_EVM
+	bool "TI K3 based J742S2 EVM running on A72"
+	select ARM64
+	select BOARD_LATE_INIT
+	select SYS_DISABLE_DCACHE_OPS
+	select BINMAN
+
+config TARGET_J742S2_R5_EVM
+	bool "TI K3 based J742S2 EVM running on R5"
+	select CPU_V7R
+	select SYS_THUMB_BUILD
+	select K3_LOAD_SYSFW
+	select RAM
+	select SPL_RAM
+	select K3_DDRSS
+	select BINMAN
+	imply SYS_K3_SPL_ATF
+
 endchoice
 
 source "board/ti/j784s4/Kconfig"
diff --git a/arch/arm/mach-k3/r5/Makefile b/arch/arm/mach-k3/r5/Makefile
index f533c5e7743..074e3b61a26 100644
--- a/arch/arm/mach-k3/r5/Makefile
+++ b/arch/arm/mach-k3/r5/Makefile
@@ -7,7 +7,7 @@ obj-$(CONFIG_SOC_K3_AM625) += am62x/
 obj-$(CONFIG_SOC_K3_AM62A7) += am62ax/
 obj-$(CONFIG_SOC_K3_AM62P5) += am62px/
 obj-$(CONFIG_SOC_K3_J721E) += j721e/
-obj-$(CONFIG_SOC_K3_J721E) += j7200/
+obj-$(CONFIG_SOC_K3_J7200) += j7200/
 obj-$(CONFIG_SOC_K3_J721S2) += j721s2/
 obj-$(CONFIG_SOC_K3_J722S) += j722s/
 obj-$(CONFIG_SOC_K3_J784S4) += j784s4/
diff --git a/arch/arm/mach-mediatek/Kconfig b/arch/arm/mach-mediatek/Kconfig
index 39eea055f70..e54c456aec0 100644
--- a/arch/arm/mach-mediatek/Kconfig
+++ b/arch/arm/mach-mediatek/Kconfig
@@ -6,9 +6,6 @@ config SYS_SOC
 config SYS_VENDOR
 	default "mediatek"
 
-config MT8512
-	bool "MediaTek MT8512 SoC"
-
 choice
 	prompt "MediaTek board select"
 
@@ -96,9 +93,8 @@ config TARGET_MT8365
 	  I2C, I2S, S/PDIF, and several LPDDR3 and LPDDR4 options.
 
 config TARGET_MT8512
-        bool "MediaTek MT8512 M1 Board"
+        bool "MediaTek MT8512 SoC"
         select ARM64
-	select MT8512
         help
           The MediaTek MT8512 is a ARM64-based SoC with a dual-core Cortex-A53.
           including UART, SPI, USB2.0 and OTG, SD and MMC cards, NAND, PWM,
@@ -160,9 +156,8 @@ config SYS_CONFIG_NAME
 
 config MTK_BROM_HEADER_INFO
 	string
-	default "media=nor" if TARGET_MT8518 || TARGET_MT8512 || TARGET_MT7629 || TARGET_MT7622
+	default "media=nor" if TARGET_MT8518 || TARGET_MT8512 || TARGET_MT7629
 	default "media=emmc" if TARGET_MT8516 || TARGET_MT8365 || TARGET_MT8183
-	default "media=snand;nandinfo=2k+64" if TARGET_MT7981 || TARGET_MT7986 || TARGET_MT7987 || TARGET_MT7988
 	default "lk=1" if TARGET_MT7623
 
 config MTK_TZ_MOVABLE
diff --git a/arch/arm/mach-mediatek/Makefile b/arch/arm/mach-mediatek/Makefile
index 344434c6029..c11d6ad8aed 100644
--- a/arch/arm/mach-mediatek/Makefile
+++ b/arch/arm/mach-mediatek/Makefile
@@ -4,7 +4,6 @@ obj-y	+= cpu.o
 obj-$(CONFIG_MTK_TZ_MOVABLE)	+= tzcfg.o
 obj-$(CONFIG_XPL_BUILD)	+= spl.o
 
-obj-$(CONFIG_MT8512) += mt8512/
 obj-$(CONFIG_TARGET_MT7622) += mt7622/
 obj-$(CONFIG_TARGET_MT7623) += mt7623/
 obj-$(CONFIG_TARGET_MT7629) += mt7629/
@@ -14,5 +13,6 @@ obj-$(CONFIG_TARGET_MT7987) += mt7987/
 obj-$(CONFIG_TARGET_MT7988) += mt7988/
 obj-$(CONFIG_TARGET_MT8183) += mt8183/
 obj-$(CONFIG_TARGET_MT8365) += mt8365/
+obj-$(CONFIG_TARGET_MT8512) += mt8512/
 obj-$(CONFIG_TARGET_MT8516) += mt8516/
 obj-$(CONFIG_TARGET_MT8518) += mt8518/
diff --git a/arch/arm/mach-meson/board-info.c b/arch/arm/mach-meson/board-info.c
index b4058f59323..d3807dc787d 100644
--- a/arch/arm/mach-meson/board-info.c
+++ b/arch/arm/mach-meson/board-info.c
@@ -7,6 +7,7 @@
 #include <init.h>
 #include <asm/global_data.h>
 #include <asm/io.h>
+#include <asm/types.h>
 #include <dm.h>
 #include <linux/bitfield.h>
 #include <regmap.h>
@@ -125,12 +126,12 @@ static const char *socinfo_to_soc_id(u32 socinfo)
 	return "Unknown";
 }
 
-static unsigned int get_socinfo(void)
+u32 meson_get_socinfo(void)
 {
 	struct regmap *regmap;
 	int nodeoffset, ret;
 	ofnode node;
-	unsigned int socinfo;
+	u32 socinfo;
 
 	/* find the offset of compatible node */
 	nodeoffset = fdt_node_offset_by_compatible(gd->fdt_blob, -1,
@@ -162,9 +163,9 @@ static unsigned int get_socinfo(void)
 
 int checkboard(void)
 {
-	unsigned int socinfo;
+	u32 socinfo;
 
-	socinfo = get_socinfo();
+	socinfo = meson_get_socinfo();
 	if (!socinfo)
 		return 0;
 
@@ -181,9 +182,9 @@ int checkboard(void)
 
 int meson_get_soc_rev(char *buff, size_t buff_len)
 {
-	unsigned int socinfo;
+	u32 socinfo;
 
-	socinfo = get_socinfo();
+	socinfo = meson_get_socinfo();
 	if (!socinfo)
 		return -1;
 
diff --git a/arch/arm/mach-meson/sm.c b/arch/arm/mach-meson/sm.c
index 4d9f83d3b38..b1f91ca29ce 100644
--- a/arch/arm/mach-meson/sm.c
+++ b/arch/arm/mach-meson/sm.c
@@ -10,11 +10,13 @@
 #include <regmap.h>
 #include <sm.h>
 #include <syscon.h>
+#include <asm/arch/boot.h>
 #include <asm/arch/sm.h>
 #include <asm/cache.h>
 #include <asm/global_data.h>
 #include <asm/ptrace.h>
 #include <linux/bitops.h>
+#include <linux/compiler_attributes.h>
 #include <linux/err.h>
 #include <linux/kernel.h>
 #include <linux/bitfield.h>
@@ -76,31 +78,131 @@ ssize_t meson_sm_write_efuse(uintptr_t offset, void *buffer, size_t size)
 	return err;
 }
 
-#define SM_CHIP_ID_LENGTH	119
-#define SM_CHIP_ID_OFFSET	4
-#define SM_CHIP_ID_SIZE		12
+/*
+ * Helps to handle two flavors of cpu_id layouts:
+ *
+ * - in-register view (value read from cpu_id reg, a.k.a. socinfo):
+ *   +-----------+------------+------------+------------+
+ *   | family_id | package_id |  chip_rev  | layout_rev |
+ *   +-----------+------------+------------+------------+
+ *   | 31     24 | 23      16 | 15       8 | 7        0 |
+ *   +-----------+------------+------------+------------+
+ *
+ * - in-efuse view (value, residing inside efuse/shmem data usually for
+ *   chip_id v2. Chip_id v1 does not contain cpu_id value inside efuse
+ *   data (i.e. in chip_id_efuse)):
+ *   +-----------+------------+------------+------------+
+ *   | family_id |  chip_rev  | package_id | layout_rev |
+ *   +-----------+------------+------------+------------+
+ *   | 31     24 | 23      16 | 15       8 | 7        0 |
+ *   +-----------+------------+------------+------------+
+ */
+enum {
+	/* In-register view of cpu_id */
+	CPU_ID_REG_MAJOR,	/* 31-24 bits */
+	CPU_ID_REG_PACK,	/* 23-16 bits */
+	CPU_ID_REG_MINOR,	/* 15-8 bits */
+	CPU_ID_REG_MISC,	/* 7-0 bits */
 
-int meson_sm_get_serial(void *buffer, size_t size)
+	/* In-efuse view of cpu_id */
+	CPU_ID_MAJOR = CPU_ID_REG_MAJOR,
+	CPU_ID_PACK  = CPU_ID_REG_MINOR,
+	CPU_ID_MINOR = CPU_ID_REG_PACK,
+	CPU_ID_MISC  = CPU_ID_REG_MISC,
+};
+
+/*
+ * This is a beginning chunk of the whole efuse storage area, containing
+ * data related to chip_id only
+ */
+struct chip_id_efuse {
+	u32 version;
+	u8 raw[MESON_CHIP_ID_SZ]; /* payload */
+} __packed;
+
+static void meson_sm_serial_reverse(u8 serial[SM_SERIAL_SIZE])
+{
+	for (int i = 0; i < SM_SERIAL_SIZE / 2; i++) {
+		int k = SM_SERIAL_SIZE - 1 - i;
+
+		swap(serial[i], serial[k]);
+	}
+}
+
+int meson_sm_get_chip_id(struct meson_sm_chip_id *chip_id)
 {
 	struct udevice *dev;
+	union meson_cpu_id socinfo;
 	struct pt_regs regs = { 0 };
-	u8 id_buffer[SM_CHIP_ID_LENGTH];
+	struct chip_id_efuse chip_id_efuse;
 	int err;
 
 	dev = meson_get_sm_device();
 	if (IS_ERR(dev))
 		return PTR_ERR(dev);
 
-	err = sm_call_read(dev, id_buffer, SM_CHIP_ID_LENGTH,
+	/*
+	 * Request v2. If not supported by secure monitor, then v1 should be
+	 * returned.
+	 */
+	regs.regs[1] = 2;
+
+	err = sm_call_read(dev, &chip_id_efuse, sizeof(chip_id_efuse),
 			   MESON_SMC_CMD_CHIP_ID_GET, &regs);
-	if (err < 0)
-		pr_err("Failed to read serial number (%d)\n", err);
+	if (err < 0) {
+		pr_err("Failed to read chip_id (%d)\n", err);
+		return err;
+	}
+
+	if (chip_id_efuse.version == 2) {
+		memcpy((u8 *)chip_id, chip_id_efuse.raw,
+		       sizeof(struct meson_sm_chip_id));
+		return 0;
+	}
 
-	memcpy(buffer, id_buffer + SM_CHIP_ID_OFFSET, size);
+	/*
+	 * Legacy chip_id (v1) read out, transform data
+	 * to expected order format (little-endian)
+	 */
+	memcpy(chip_id->serial, chip_id_efuse.raw, sizeof(chip_id->serial));
+	meson_sm_serial_reverse(chip_id->serial);
+
+	socinfo.val = meson_get_socinfo();
+	if (!socinfo.val)
+		return -ENODEV;
+
+	chip_id->cpu_id = (union meson_cpu_id){
+		.raw[CPU_ID_MAJOR] = socinfo.raw[CPU_ID_REG_MAJOR],
+		.raw[CPU_ID_PACK]  = socinfo.raw[CPU_ID_REG_PACK],
+		.raw[CPU_ID_MINOR] = socinfo.raw[CPU_ID_REG_MINOR],
+		.raw[CPU_ID_MISC]  = socinfo.raw[CPU_ID_REG_MISC],
+	};
 
 	return 0;
 }
 
+int meson_sm_get_serial(void *buffer, size_t size)
+{
+	struct meson_sm_chip_id chip_id;
+	int ret;
+
+	if (size < SM_SERIAL_SIZE)
+		return -EINVAL;
+
+	ret = meson_sm_get_chip_id(&chip_id);
+	if (ret)
+		return ret;
+
+	/*
+	 * The order of serial inside chip_id and serial which function must
+	 * return does not match: stick here to big-endian for backward
+	 * compatibility.
+	 */
+	meson_sm_serial_reverse(chip_id.serial);
+	memcpy(buffer, chip_id.serial, sizeof(chip_id.serial));
+	return ret;
+}
+
 #define AO_SEC_SD_CFG15		0xfc
 #define REBOOT_REASON_MASK	GENMASK(15, 12)
 
diff --git a/arch/arm/mach-nexell/Kconfig b/arch/arm/mach-nexell/Kconfig
index 16324e15206..b43dd5a5c25 100644
--- a/arch/arm/mach-nexell/Kconfig
+++ b/arch/arm/mach-nexell/Kconfig
@@ -4,7 +4,6 @@ config ARCH_S5P4418
 	bool "Nexell S5P4418 SoC"
 	select CPU_V7A
 	select OF_CONTROL
-	select OF_SEPARATE
 	select NX_GPIO
 	select DM_SERIAL
 	select PL01X_SERIAL
diff --git a/arch/arm/mach-omap2/omap3/lowlevel_init.S b/arch/arm/mach-omap2/omap3/lowlevel_init.S
index 1ab9472e198..5541a4714ac 100644
--- a/arch/arm/mach-omap2/omap3/lowlevel_init.S
+++ b/arch/arm/mach-omap2/omap3/lowlevel_init.S
@@ -176,10 +176,10 @@ ENTRY(lowlevel_init)
 	ldr	sp, SRAM_STACK
 	str	ip, [sp]	/* stash ip register */
 	mov	ip, lr		/* save link reg across call */
-#if !defined(CONFIG_SYS_NAND_BOOT) && !defined(CONFIG_SYS_ONENAND_BOOT)
+#if !defined(CONFIG_SYS_NAND_BOOT)
 /*
  * No need to copy/exec the clock code - DPLL adjust already done
- * in NAND/oneNAND Boot.
+ * in NAND Boot.
  */
 	ldr	r1, =SRAM_CLK_CODE
 	bl	cpy_clk_code
diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig
index adac11a6b89..c6e347b8d9d 100644
--- a/arch/arm/mach-rockchip/Kconfig
+++ b/arch/arm/mach-rockchip/Kconfig
@@ -9,7 +9,7 @@ config ROCKCHIP_PX30
 	select SPL
 	select TPL
 	select TPL_TINY_FRAMEWORK if TPL
-	select TPL_NEEDS_SEPARATE_STACK if TPL
+	select TPL_HAVE_INIT_STACK if TPL
 	imply SPL_SEPARATE_BSS
 	select SPL_SERIAL
 	select TPL_SERIAL
@@ -107,7 +107,7 @@ config ROCKCHIP_RK322X
 	select TPL
 	select TPL_DM
 	select TPL_OF_LIBFDT
-	select TPL_NEEDS_SEPARATE_STACK if TPL
+	select TPL_HAVE_INIT_STACK if TPL
 	select SPL_DRIVERS_MISC
 	imply ROCKCHIP_COMMON_BOARD
 	imply SPL_SERIAL
@@ -140,7 +140,7 @@ config ROCKCHIP_RK3288
 	imply TPL_DRIVERS_MISC
 	imply TPL_LIBCOMMON_SUPPORT
 	imply TPL_LIBGENERIC_SUPPORT
-	imply TPL_NEEDS_SEPARATE_STACK
+	imply TPL_HAVE_INIT_STACK
 	imply TPL_OF_CONTROL
 	imply TPL_OF_PLATDATA
 	imply TPL_RAM
@@ -198,7 +198,7 @@ config ROCKCHIP_RK3328
 	select SPL
 	select SUPPORT_TPL
 	select TPL
-	select TPL_NEEDS_SEPARATE_STACK if TPL
+	select TPL_HAVE_INIT_STACK if TPL
 	imply ARMV8_CRYPTO
 	imply ARMV8_SET_SMPEN
 	imply MISC
@@ -226,7 +226,7 @@ config ROCKCHIP_RK3368
 	select ARM64
 	select SUPPORT_SPL
 	select SUPPORT_TPL
-	select TPL_NEEDS_SEPARATE_STACK if TPL
+	select TPL_HAVE_INIT_STACK if TPL
 	imply ROCKCHIP_COMMON_BOARD
 	imply SPL_ROCKCHIP_COMMON_BOARD
 	imply SPL_SEPARATE_BSS
@@ -258,7 +258,7 @@ config ROCKCHIP_RK3399
 	select SPL_RAM if SPL
 	select SPL_REGMAP if SPL
 	select SPL_SYSCON if SPL
-	select TPL_NEEDS_SEPARATE_STACK if TPL
+	select TPL_HAVE_INIT_STACK if TPL
 	select SPL_SEPARATE_BSS
 	select CLK
 	select FIT
@@ -393,7 +393,7 @@ config ROCKCHIP_RV1126
 	select SKIP_LOWLEVEL_INIT_ONLY
 	select TPL
 	select SUPPORT_TPL
-	select TPL_NEEDS_SEPARATE_STACK
+	select TPL_HAVE_INIT_STACK
 	select TPL_ROCKCHIP_BACK_TO_BROM
 	select SPL
 	select SUPPORT_SPL
diff --git a/arch/arm/mach-rockchip/bootrom.c b/arch/arm/mach-rockchip/bootrom.c
index 82a0b3efef9..1db38546d55 100644
--- a/arch/arm/mach-rockchip/bootrom.c
+++ b/arch/arm/mach-rockchip/bootrom.c
@@ -4,11 +4,11 @@
  */
 
 #include <hang.h>
+#include <setjmp.h>
 #include <asm/arch-rockchip/bootrom.h>
 #include <asm/arch-rockchip/boot_mode.h>
 #include <asm/cache.h>
 #include <asm/io.h>
-#include <asm/setjmp.h>
 #include <asm/system.h>
 
 /*
diff --git a/arch/arm/mach-sc5xx/soc.c b/arch/arm/mach-sc5xx/soc.c
index f3619206e91..8f13127a660 100644
--- a/arch/arm/mach-sc5xx/soc.c
+++ b/arch/arm/mach-sc5xx/soc.c
@@ -172,42 +172,6 @@ void fixup_dp83867_phy(struct phy_device *phydev)
 		phy_write(phydev, MDIO_DEVAD_NONE, 0, 0x3100);
 }
 
-extern char __bss_start, __bss_end;
-extern char __rel_dyn_end;
-
-void bss_clear(void)
-{
-	char *bss_start = &__bss_start;
-	char *bss_end = &__bss_end;
-	char *rel_dyn_end = &__rel_dyn_end;
-
-	char *start;
-
-	if (rel_dyn_end >= bss_start && rel_dyn_end <= bss_end)
-		start = rel_dyn_end;
-	else
-		start = bss_start;
-
-	u32 *pt;
-	size_t sz = bss_end - start;
-
-	for (int i = 0; i < sz; i += 4) {
-		pt = (u32 *)(start + i);
-		*pt = 0;
-	}
-}
-
-int board_early_init_f(void)
-{
-	bss_clear();
-	return 0;
-}
-
-int board_init(void)
-{
-	return 0;
-}
-
 int dram_init(void)
 {
 	gd->ram_size = CFG_SYS_SDRAM_SIZE;
diff --git a/arch/arm/mach-snapdragon/board.c b/arch/arm/mach-snapdragon/board.c
index 2ef936aab75..deae4d32378 100644
--- a/arch/arm/mach-snapdragon/board.c
+++ b/arch/arm/mach-snapdragon/board.c
@@ -88,7 +88,29 @@ int dram_init_banksize(void)
 	return 0;
 }
 
-static void qcom_parse_memory(const void *fdt)
+/**
+ * The generic memory parsing code in U-Boot lacks a few things that we
+ * need on Qualcomm:
+ *
+ * 1. It sets gd->ram_size and gd->ram_base to represent a single memory block
+ * 2. setup_dest_addr() later relocates U-Boot to ram_base + ram_size, the end
+ *    of that first memory block.
+ *
+ * This results in all memory beyond U-Boot being unusable in Linux when booting
+ * with EFI.
+ *
+ * Since the ranges in the memory node may be out of order, the only way for us
+ * to correctly determine the relocation address for U-Boot is to parse all
+ * memory regions and find the highest valid address.
+ *
+ * We can't use fdtdec_setup_memory_banksize() since it stores the result in
+ * gd->bd, which is not yet allocated.
+ *
+ * @fdt: FDT blob to parse /memory node from
+ *
+ * Return: 0 on success or -ENODATA if /memory node is missing or incomplete
+ */
+static int qcom_parse_memory(const void *fdt)
 {
 	int offset;
 	const fdt64_t *memory;
@@ -97,16 +119,12 @@ static void qcom_parse_memory(const void *fdt)
 	int i, j, banks;
 
 	offset = fdt_path_offset(fdt, "/memory");
-	if (offset < 0) {
-		log_err("No memory node found in device tree!\n");
-		return;
-	}
+	if (offset < 0)
+		return -ENODATA;
 
 	memory = fdt_getprop(fdt, offset, "reg", &memsize);
-	if (!memory) {
-		log_err("No memory configuration was provided by the previous bootloader!\n");
-		return;
-	}
+	if (!memory)
+		return -ENODATA;
 
 	banks = min(memsize / (2 * sizeof(u64)), (ulong)CONFIG_NR_DRAM_BANKS);
 
@@ -119,7 +137,6 @@ static void qcom_parse_memory(const void *fdt)
 	for (i = 0, j = 0; i < banks * 2; i += 2, j++) {
 		prevbl_ddr_banks[j].start = get_unaligned_be64(&memory[i]);
 		prevbl_ddr_banks[j].size = get_unaligned_be64(&memory[i + 1]);
-		/* SM8650 boards sometimes have empty regions! */
 		if (!prevbl_ddr_banks[j].size) {
 			j--;
 			continue;
@@ -127,13 +144,16 @@ static void qcom_parse_memory(const void *fdt)
 		ram_end = max(ram_end, prevbl_ddr_banks[j].start + prevbl_ddr_banks[j].size);
 	}
 
+	if (!banks || !prevbl_ddr_banks[0].size)
+		return -ENODATA;
+
 	/* Sort our RAM banks -_- */
 	qsort(prevbl_ddr_banks, banks, sizeof(prevbl_ddr_banks[0]), ddr_bank_cmp);
 
 	gd->ram_base = prevbl_ddr_banks[0].start;
 	gd->ram_size = ram_end - gd->ram_base;
-	debug("ram_base = %#011lx, ram_size = %#011llx, ram_end = %#011llx\n",
-	      gd->ram_base, gd->ram_size, ram_end);
+
+	return 0;
 }
 
 static void show_psci_version(void)
@@ -142,24 +162,56 @@ static void show_psci_version(void)
 
 	arm_smccc_smc(ARM_PSCI_0_2_FN_PSCI_VERSION, 0, 0, 0, 0, 0, 0, 0, &res);
 
+	/* Some older SoCs like MSM8916 don't always support PSCI */
+	if ((int)res.a0 == PSCI_RET_NOT_SUPPORTED)
+		return;
+
 	debug("PSCI:  v%ld.%ld\n",
 	      PSCI_VERSION_MAJOR(res.a0),
 	      PSCI_VERSION_MINOR(res.a0));
 }
 
+/**
+ * Most MSM8916 devices in the wild shipped without PSCI support, but the
+ * upstream DTs pretend that PSCI exists. If that situation is detected here,
+ * the /psci node is deleted. This is done very early to ensure the PSCI
+ * firmware driver doesn't bind (which then binds a sysreset driver that won't
+ * work).
+ */
+static void qcom_psci_fixup(void *fdt)
+{
+	int offset, ret;
+	struct arm_smccc_res res;
+
+	arm_smccc_smc(ARM_PSCI_0_2_FN_PSCI_VERSION, 0, 0, 0, 0, 0, 0, 0, &res);
+
+	if ((int)res.a0 != PSCI_RET_NOT_SUPPORTED)
+		return;
+
+	offset = fdt_path_offset(fdt, "/psci");
+	if (offset < 0)
+		return;
+
+	debug("Found /psci DT node on device with no PSCI. Deleting.\n");
+	ret = fdt_del_node(fdt, offset);
+	if (ret)
+		log_err("Failed to delete /psci node: %d\n", ret);
+}
+
 /* We support booting U-Boot with an internal DT when running as a first-stage bootloader
  * or for supporting quirky devices where it's easier to leave the downstream DT in place
  * to improve ABL compatibility. Otherwise, we use the DT provided by ABL.
  */
 int board_fdt_blob_setup(void **fdtp)
 {
-	struct fdt_header *fdt;
+	struct fdt_header *external_fdt, *internal_fdt;
 	bool internal_valid, external_valid;
-	int ret = 0;
+	int ret = -ENODATA;
 
-	fdt = (struct fdt_header *)get_prev_bl_fdt_addr();
-	external_valid = fdt && !fdt_check_header(fdt);
-	internal_valid = !fdt_check_header(*fdtp);
+	internal_fdt = (struct fdt_header *)*fdtp;
+	external_fdt = (struct fdt_header *)get_prev_bl_fdt_addr();
+	external_valid = external_fdt && !fdt_check_header(external_fdt);
+	internal_valid = !fdt_check_header(internal_fdt);
 
 	/*
 	 * There is no point returning an error here, U-Boot can't do anything useful in this situation.
@@ -167,31 +219,42 @@ int board_fdt_blob_setup(void **fdtp)
 	 */
 	if (!internal_valid && !external_valid)
 		panic("Internal FDT is invalid and no external FDT was provided! (fdt=%#llx)\n",
-		      (phys_addr_t)fdt);
+		      (phys_addr_t)external_fdt);
+
+	/* Prefer memory information from internal DT if it's present */
+	if (internal_valid)
+		ret = qcom_parse_memory(internal_fdt);
+
+	if (ret < 0 && external_valid) {
+		/* No internal FDT or it lacks a proper /memory node.
+		 * The previous bootloader handed us something, let's try that.
+		 */
+		if (internal_valid)
+			debug("No memory info in internal FDT, falling back to external\n");
+
+		ret = qcom_parse_memory(external_fdt);
+	}
+
+	if (ret < 0)
+		panic("No valid memory ranges found!\n");
+
+	debug("ram_base = %#011lx, ram_size = %#011llx\n",
+	      gd->ram_base, gd->ram_size);
 
 	if (internal_valid) {
 		debug("Using built in FDT\n");
 		ret = -EEXIST;
 	} else {
 		debug("Using external FDT\n");
-		/* So we can use it before returning */
-		*fdtp = fdt;
+		*fdtp = external_fdt;
+		ret = 0;
 	}
 
-	/*
-	 * Parse the /memory node while we're here,
-	 * this makes it easy to do other things early.
-	 */
-	qcom_parse_memory(*fdtp);
+	qcom_psci_fixup(*fdtp);
 
 	return ret;
 }
 
-void reset_cpu(void)
-{
-	psci_system_reset();
-}
-
 /*
  * Some Qualcomm boards require GPIO configuration when switching USB modes.
  * Support setting this configuration via pinctrl state.
diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig
index 6b6a162f568..a76a9fb2a39 100644
--- a/arch/arm/mach-socfpga/Kconfig
+++ b/arch/arm/mach-socfpga/Kconfig
@@ -55,6 +55,7 @@ config TARGET_SOCFPGA_AGILEX
 	select BINMAN if SPL_ATF
 	select CLK
 	select FPGA_INTEL_SDM_MAILBOX
+	select GICV2
 	select NCORE_CACHE
 	select SPL_CLK if SPL
 	select TARGET_SOCFPGA_SOC64
@@ -64,7 +65,6 @@ config TARGET_SOCFPGA_AGILEX5
 	select BINMAN if SPL_ATF
 	select CLK
 	select FPGA_INTEL_SDM_MAILBOX
-	select GICV3
 	select SPL_CLK if SPL
 	select TARGET_SOCFPGA_SOC64
 
@@ -74,6 +74,7 @@ config TARGET_SOCFPGA_ARRIA5
 
 config TARGET_SOCFPGA_ARRIA10
 	bool
+	select GICV2
 	select SPL_ALTERA_SDRAM
 	select SPL_BOARD_INIT if SPL
 	select SPL_CACHE if SPL
@@ -118,6 +119,7 @@ config TARGET_SOCFPGA_N5X
 	select ARMV8_SET_SMPEN
 	select BINMAN if SPL_ATF
 	select CLK
+	select GICV2
 	select FPGA_INTEL_SDM_MAILBOX
 	select NCORE_CACHE
 	select SPL_ALTERA_SDRAM
@@ -137,6 +139,7 @@ config TARGET_SOCFPGA_STRATIX10
 	select ARMV8_SET_SMPEN
 	select BINMAN if SPL_ATF
 	select FPGA_INTEL_SDM_MAILBOX
+	select GICV2
 	select TARGET_SOCFPGA_SOC64
 
 choice
diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index 5fc61b4a5c6..22d48dfae1c 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -3,7 +3,7 @@
 # (C) Copyright 2000-2003
 # Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 #
-# Copyright (C) 2012-2017 Altera Corporation <www.altera.com>
+# Copyright (C) 2012-2025 Altera Corporation <www.altera.com>
 # Copyright (C) 2017-2024 Intel Corporation <www.intel.com>
 
 obj-y	+= board.o
@@ -62,7 +62,12 @@ obj-y	+= mailbox_s10.o
 obj-y	+= misc_soc64.o
 obj-y	+= mmu-arm64_s10.o
 obj-y	+= reset_manager_s10.o
+obj-y	+= wrap_handoff_soc64.o
 obj-y	+= wrap_pll_config_soc64.o
+obj-y	+= altera-sysmgr.o
+obj-y	+= ccu_ncore3.o
+obj-y	+= system_manager_soc64.o
+obj-y	+= timer_s10.o
 endif
 
 ifdef CONFIG_TARGET_SOCFPGA_N5X
@@ -106,6 +111,7 @@ obj-y	+= spl_n5x.o
 endif
 ifdef CONFIG_TARGET_SOCFPGA_AGILEX5
 obj-y	+= spl_soc64.o
+obj-y	+= spl_agilex5.o
 endif
 else
 obj-$(CONFIG_SPL_ATF) += secure_reg_helper.o
diff --git a/arch/arm/mach-socfpga/altera-sysmgr.c b/arch/arm/mach-socfpga/altera-sysmgr.c
new file mode 100644
index 00000000000..ca3f5ca7dd5
--- /dev/null
+++ b/arch/arm/mach-socfpga/altera-sysmgr.c
@@ -0,0 +1,113 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2025 Altera Corporation <www.altera.com>
+ */
+
+/*
+ * This driver supports the SOCFPGA System Manager Register block which
+ * aggregates different peripheral function into one area.
+ * On 64 bit ARM parts, the system manager only can be accessed during
+ * EL3 mode. At lower exception level a SMC call is required to perform
+ * the read and write operation.
+ */
+
+#define LOG_CATEGORY UCLASS_NOP
+
+#include <dm.h>
+#include <log.h>
+#include <misc.h>
+#include <asm/io.h>
+#include <asm/system.h>
+#include <asm/arch/altera-sysmgr.h>
+#include <asm/arch/smc_api.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/intel-smc.h>
+
+static int altr_sysmgr_read_generic(struct udevice *dev, u32 *addr, u32 *value)
+{
+	u64 args[1];
+	u64 ret_arg;
+	int ret = 0;
+
+	debug("%s: %s(dev=%p, addr=0x%lx):\n", __func__,
+	      dev->name, dev, (uintptr_t)addr);
+
+	if (current_el() == 3) {
+		ret_arg = readl((uintptr_t)addr);
+	} else {
+		if (!(IS_ENABLED(CONFIG_SPL_BUILD)) && IS_ENABLED(CONFIG_SPL_ATF)) {
+			args[0] = (u64)(uintptr_t)addr;
+			ret = invoke_smc(INTEL_SIP_SMC_REG_READ, args, 1, &ret_arg, 1);
+		} else {
+			pr_err("%s Failed to read system manager at lower privilege and without BL31\n",
+			       dev->name);
+			return -EPROTONOSUPPORT;
+		}
+	}
+
+	*value = (u32)ret_arg;
+	return ret;
+}
+
+static int altr_sysmgr_write_generic(struct udevice *dev, u32 *addr, u32 value)
+{
+	u64 args[2];
+	int ret = 0;
+
+	debug("%s: %s(dev=%p, addr=0x%lx, val=0x%x):\n", __func__,
+	      dev->name, dev, (uintptr_t)addr, value);
+
+	if (current_el() == 3) {
+		writel(value, (uintptr_t)addr);
+	} else {
+		if (!(IS_ENABLED(CONFIG_SPL_BUILD)) && IS_ENABLED(CONFIG_SPL_ATF)) {
+			args[0] = (u64)(uintptr_t)(addr);
+			args[1] = value;
+			ret = invoke_smc(INTEL_SIP_SMC_REG_WRITE, args, 2, NULL, 0);
+		} else {
+			pr_err("%s Failed to write to system manager at lower privilege and without BL31\n",
+			       dev->name);
+			return -EPROTONOSUPPORT;
+		}
+	}
+
+	return ret;
+}
+
+static int altr_sysmgr_probe(struct udevice *dev)
+{
+	fdt_addr_t addr;
+	struct altr_sysmgr_priv *altr_priv = dev_get_priv(dev);
+
+	debug("%s: %s(dev=%p):\n", __func__, dev->name, dev);
+	addr = dev_read_addr(dev);
+	if (addr == FDT_ADDR_T_NONE) {
+		pr_err("%s dev_read_addr() failed\n", dev->name);
+		return -ENODEV;
+	}
+
+	altr_priv->regs = (void __iomem *)addr;
+	return 0;
+}
+
+static const struct altr_sysmgr_ops sysmgr_ops = {
+	.read = altr_sysmgr_read_generic,
+	.write = altr_sysmgr_write_generic,
+};
+
+static const struct udevice_id altr_sysmgr_ids[] = {
+	{ .compatible = "altr,sys-mgr-s10" },
+	{ .compatible = "altr,sys-mgr" },
+	{ },
+};
+
+U_BOOT_DRIVER(altr_sysmgr) = {
+	.name	= "altr_sysmgr",
+	.id	= UCLASS_NOP,
+	.of_match = altr_sysmgr_ids,
+	.probe	= altr_sysmgr_probe,
+	.ops	= &sysmgr_ops,
+	.priv_auto = sizeof(struct altr_sysmgr_priv),
+	.flags = DM_FLAG_PRE_RELOC,
+};
diff --git a/arch/arm/mach-socfpga/board.c b/arch/arm/mach-socfpga/board.c
index 24a15f7903f..27072e53135 100644
--- a/arch/arm/mach-socfpga/board.c
+++ b/arch/arm/mach-socfpga/board.c
@@ -6,22 +6,24 @@
  */
 
 #include <config.h>
-#include <asm/arch/clock_manager.h>
-#include <asm/arch/mailbox_s10.h>
-#include <asm/arch/misc.h>
-#include <asm/arch/reset_manager.h>
-#include <asm/arch/secure_vab.h>
-#include <asm/arch/smc_api.h>
-#include <asm/global_data.h>
-#include <asm/io.h>
 #include <errno.h>
 #include <fdtdec.h>
+#include <log.h>
+#include <init.h>
 #include <hang.h>
+#include <handoff.h>
 #include <image.h>
-#include <init.h>
-#include <log.h>
 #include <usb.h>
 #include <usb/dwc2_udc.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <asm/arch/clock_manager.h>
+#include <asm/arch/mailbox_s10.h>
+#include <asm/arch/misc.h>
+#include <asm/arch/reset_manager.h>
+#include <asm/arch/secure_vab.h>
+#include <asm/arch/smc_api.h>
+#include <bloblist.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -57,7 +59,18 @@ int board_init(void)
 
 int dram_init_banksize(void)
 {
+#if CONFIG_IS_ENABLED(HANDOFF) && IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5)
+#ifndef CONFIG_SPL_BUILD
+	struct spl_handoff *ho;
+
+	ho = bloblist_find(BLOBLISTT_U_BOOT_SPL_HANDOFF, sizeof(*ho));
+	if (!ho)
+		return log_msg_ret("Missing SPL hand-off info", -ENOENT);
+	handoff_load_dram_banks(ho);
+#endif
+#else
 	fdtdec_setup_memory_banksize();
+#endif /* HANDOFF && CONFIG_TARGET_SOCFPGA_AGILEX5 */
 
 	return 0;
 }
diff --git a/arch/arm/mach-socfpga/ccu_ncore3.c b/arch/arm/mach-socfpga/ccu_ncore3.c
new file mode 100644
index 00000000000..a399aedcd10
--- /dev/null
+++ b/arch/arm/mach-socfpga/ccu_ncore3.c
@@ -0,0 +1,64 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2025 Altera Corporation <www.altera.com>
+ *
+ */
+#include <wait_bit.h>
+#include <asm/arch/base_addr_soc64.h>
+#include <linux/bitfield.h>
+
+#define CCU_DMI0_DMIUSMCTCR				SOCFPGA_CCU_ADDRESS + 0x7300
+#define CCU_DMI0_DMIUSMCMCR				SOCFPGA_CCU_ADDRESS + 0x7340
+#define CCU_DMI0_DMIUSMCMAR				SOCFPGA_CCU_ADDRESS + 0x7344
+#define CCU_DMI0_DMIUSMCMCR_MNTOP		GENMASK(3, 0)
+#define MAX_DISTRIBUTED_MEM_INTERFACE	2
+#define FLUSH_ALL_ENTRIES				0x4
+#define CCU_DMI0_DMIUSMCMCR_ARRAY_ID	GENMASK(21, 16)
+#define ARRAY_ID_TAG					0x0
+#define ARRAY_ID_DATA					0x1
+#define CACHE_OPERATION_DONE			BIT(0)
+#define TIMEOUT_200MS					200
+
+int __asm_flush_l3_dcache(void)
+{
+	int i;
+	int ret = 0;
+
+	/* Flushing all entries in CCU system memory cache */
+	for (i = 0; i < MAX_DISTRIBUTED_MEM_INTERFACE; i++) {
+		/*
+		 * Skipping if the system memory cache is not enabled for
+		 * particular DMI
+		 */
+		if (!readl((uintptr_t)(CCU_DMI0_DMIUSMCTCR + (i * 0x1000))))
+			continue;
+
+		writel(FIELD_PREP(CCU_DMI0_DMIUSMCMCR_MNTOP, FLUSH_ALL_ENTRIES) |
+			   FIELD_PREP(CCU_DMI0_DMIUSMCMCR_ARRAY_ID, ARRAY_ID_TAG),
+			   (uintptr_t)(CCU_DMI0_DMIUSMCMCR + (i * 0x1000)));
+
+		/* Wait for cache maintenance operation done */
+		ret = wait_for_bit_le32((const void *)(uintptr_t)(CCU_DMI0_DMIUSMCMAR +
+				(i * 0x1000)), CACHE_OPERATION_DONE, false, TIMEOUT_200MS,
+				false);
+		if (ret) {
+			debug("%s: Timeout while waiting for flushing tag in DMI%d done\n",
+			      __func__, i);
+			return ret;
+		}
+
+		writel(FIELD_PREP(CCU_DMI0_DMIUSMCMCR_MNTOP, FLUSH_ALL_ENTRIES) |
+			   FIELD_PREP(CCU_DMI0_DMIUSMCMCR_ARRAY_ID, ARRAY_ID_DATA),
+			   (uintptr_t)(CCU_DMI0_DMIUSMCMCR + (i * 0x1000)));
+
+		/* Wait for cache maintenance operation done */
+		ret = wait_for_bit_le32((const void *)(uintptr_t)(CCU_DMI0_DMIUSMCMAR +
+				(i * 0x1000)), CACHE_OPERATION_DONE, false, TIMEOUT_200MS,
+				false);
+		if (ret)
+			debug("%s: Timeout waiting for flushing data in DMI%d done\n",
+			      __func__, i);
+	}
+
+	return ret;
+}
diff --git a/arch/arm/mach-socfpga/include/mach/altera-sysmgr.h b/arch/arm/mach-socfpga/include/mach/altera-sysmgr.h
new file mode 100644
index 00000000000..8516617efe5
--- /dev/null
+++ b/arch/arm/mach-socfpga/include/mach/altera-sysmgr.h
@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2025 Altera Corporation <www.altera.com>
+ */
+
+struct altr_sysmgr_ops {
+	int (*read)(struct udevice *dev, u32 *addr, u32 *value);
+	int (*write)(struct udevice *dev, u32 *addr, u32 value);
+};
+
+struct altr_sysmgr_priv {
+	void __iomem *regs;
+};
+
+#define altr_sysmgr_get_ops(dev)        ((struct altr_sysmgr_ops *)(dev)->driver->ops)
+#define altr_sysmgr_get_priv(dev)	((struct altr_sysmgr_priv *)(dev_get_priv(dev)))
diff --git a/arch/arm/mach-socfpga/include/mach/board.h b/arch/arm/mach-socfpga/include/mach/board.h
new file mode 100644
index 00000000000..2c3127e629f
--- /dev/null
+++ b/arch/arm/mach-socfpga/include/mach/board.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2025 Altera Corporation <www.altera.com>
+ */
+
+#ifndef BOARD_H_
+#define BOARD_H_
+
+u8 socfpga_get_board_id(void);
+
+#endif /* _BOARD_H_ */
diff --git a/arch/arm/mach-socfpga/include/mach/firewall.h b/arch/arm/mach-socfpga/include/mach/firewall.h
index 5cb7f23f8f0..2b436b64816 100644
--- a/arch/arm/mach-socfpga/include/mach/firewall.h
+++ b/arch/arm/mach-socfpga/include/mach/firewall.h
@@ -1,6 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0
  *
  * Copyright (C) 2017-2019 Intel Corporation <www.intel.com>
+ * Copyright (C) 2025 Altera Corporation <www.altera.com>
  *
  */
 
@@ -126,11 +127,27 @@ struct socfpga_firwall_l4_sys {
 #define FW_MPU_DDR_SCR_NONMPUREGION0ADDR_LIMITEXT	0x9c
 #define FW_MPU_DDR_SCR_NONMPUREGION0ADDR_LIMITEXT_FIELD	0xff
 
+/* Firewall F2SDRAM DDR SCR registers */
+#define FW_F2SDRAM_DDR_SCR_EN				0x00
+#define FW_F2SDRAM_DDR_SCR_EN_SET			0x04
+#define FW_F2SDRAM_DDR_SCR_REGION0ADDR_BASE		0x10
+#define FW_F2SDRAM_DDR_SCR_REGION0ADDR_BASEEXT		0x14
+#define FW_F2SDRAM_DDR_SCR_REGION0ADDR_LIMIT		0x18
+#define FW_F2SDRAM_DDR_SCR_REGION0ADDR_LIMITEXT		0x1c
+
 #define MPUREGION0_ENABLE				BIT(0)
 #define NONMPUREGION0_ENABLE				BIT(8)
 
+#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5)
+#define FW_MPU_DDR_SCR_WRITEL(data, reg)		\
+	writel(data, SOCFPGA_FW_DDR_CCU_DMI0_ADDRESS + (reg)); \
+	writel(data, SOCFPGA_FW_DDR_CCU_DMI1_ADDRESS + (reg))
+#define FW_F2SDRAM_DDR_SCR_WRITEL(data, reg)		\
+	writel(data, SOCFPGA_FW_TBU2NOC_ADDRESS + (reg))
+#else
 #define FW_MPU_DDR_SCR_WRITEL(data, reg)		\
 	writel(data, SOCFPGA_FW_MPU_DDR_SCR_ADDRESS + (reg))
+#endif
 
 void firewall_setup(void);
 
diff --git a/arch/arm/mach-socfpga/include/mach/handoff_soc64.h b/arch/arm/mach-socfpga/include/mach/handoff_soc64.h
index d839f288411..763b077d8c1 100644
--- a/arch/arm/mach-socfpga/include/mach/handoff_soc64.h
+++ b/arch/arm/mach-socfpga/include/mach/handoff_soc64.h
@@ -1,6 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0
  *
  * Copyright (C) 2016-2024 Intel Corporation <www.intel.com>
+ * Copyright (C) 2025 Altera Corporation <www.altera.com>
  *
  */
 
@@ -17,9 +18,9 @@
 #define SOC64_HANDOFF_MAGIC_FPGA	0x46504741
 #define SOC64_HANDOFF_MAGIC_DELAY	0x444C4159
 #define SOC64_HANDOFF_MAGIC_CLOCK	0x434C4B53
+#define SOC64_HANDOFF_MAGIC_SDRAM	0x5344524d
 #if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5)
 #define SOC64_HANDOFF_MAGIC_PERI	0x50455249
-#define SOC64_HANDOFF_MAGIC_SDRAM	0x5344524d
 #else
 #define SOC64_HANDOFF_MAGIC_MISC	0x4D495343
 #endif
@@ -68,7 +69,7 @@
 #if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5)
 #define SOC64_HANDOFF_PERI		(SOC64_HANDOFF_BASE + 0x620)
 #define SOC64_HANDOFF_SDRAM		(SOC64_HANDOFF_BASE + 0x634)
-#define SOC64_HANDOFF_SDRAM_LEN		1
+#define SOC64_HANDOFF_SDRAM_LEN		5
 #endif
 
 #if IS_ENABLED(CONFIG_TARGET_SOCFPGA_STRATIX10)
diff --git a/arch/arm/mach-socfpga/include/mach/misc.h b/arch/arm/mach-socfpga/include/mach/misc.h
index 8460acb00d9..ab46415168f 100644
--- a/arch/arm/mach-socfpga/include/mach/misc.h
+++ b/arch/arm/mach-socfpga/include/mach/misc.h
@@ -1,6 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0 */
 /*
  * Copyright (C) 2016-2021 Intel Corporation
+ * Copyright (C) 2025 Altera Corporation <www.altera.com>
  */
 
 #ifndef _SOCFPGA_MISC_H_
@@ -51,6 +52,7 @@ bool is_periph_program_force(void);
 void set_regular_boot(unsigned int status);
 void socfpga_pl310_clear(void);
 void socfpga_get_managers_addr(void);
+void socfpga_get_sys_mgr_addr(const char *compat);
 int qspi_flash_software_reset(void);
 
 #endif /* _SOCFPGA_MISC_H_ */
diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager_soc64.h b/arch/arm/mach-socfpga/include/mach/reset_manager_soc64.h
index c8bb727aa2b..058fdd6e548 100644
--- a/arch/arm/mach-socfpga/include/mach/reset_manager_soc64.h
+++ b/arch/arm/mach-socfpga/include/mach/reset_manager_soc64.h
@@ -1,6 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0 */
 /*
  *  Copyright (C) 2016-2019 Intel Corporation <www.intel.com>
+ *  Copyright (C) 2025 Altera Corporation <www.altera.com>
  */
 
 #ifndef _RESET_MANAGER_SOC64_H_
@@ -23,14 +24,20 @@ void socfpga_bridges_reset(int enable);
 #define RSTMGR_BRGMODRST_FPGA2SOC_MASK	0x00000004
 
 /* SDM, Watchdogs and MPU warm reset mask */
-#define RSTMGR_STAT_SDMWARMRST		BIT(1)
+#define RSTMGR_STAT_SDMWARMRST		0x2
 #define RSTMGR_STAT_MPU0RST_BITPOS	8
 #define RSTMGR_STAT_L4WD0RST_BITPOS	16
+#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5)
+#define RSTMGR_STAT_L4WD0RST_BIT	0x1F0000
+#define RSTMGR_L4WD_MPU_WARMRESET_MASK	(RSTMGR_STAT_SDMWARMRST | \
+		RSTMGR_STAT_L4WD0RST_BIT)
+#else
 #define RSTMGR_L4WD_MPU_WARMRESET_MASK	(RSTMGR_STAT_SDMWARMRST | \
 		GENMASK(RSTMGR_STAT_MPU0RST_BITPOS + 3, \
 			RSTMGR_STAT_MPU0RST_BITPOS) | \
 		GENMASK(RSTMGR_STAT_L4WD0RST_BITPOS + 3, \
 			RSTMGR_STAT_L4WD0RST_BITPOS))
+#endif
 
 /*
  * SocFPGA Stratix10 reset IDs, bank mapping is as follows:
diff --git a/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h b/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h
index 78eff247978..c2ca0a50e35 100644
--- a/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h
+++ b/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h
@@ -1,6 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0 */
 /*
  * Copyright (C) 2019-2021 Intel Corporation <www.intel.com>
+ * Copyright (C) 2025 Altera Corporation <www.altera.com>
  */
 
 #ifndef _SYSTEM_MANAGER_SOC64_H_
@@ -11,22 +12,43 @@ void sysmgr_pinmux_init(void);
 void populate_sysmgr_fpgaintf_module(void);
 void populate_sysmgr_pinmux(void);
 
-#define SYSMGR_SOC64_WDDBG			0x08
-#define SYSMGR_SOC64_DMA			0x20
-#define SYSMGR_SOC64_DMA_PERIPH			0x24
-#define SYSMGR_SOC64_SDMMC			0x28
-#define SYSMGR_SOC64_SDMMC_L3MASTER		0x2c
-#define SYSMGR_SOC64_EMAC_GLOBAL		0x40
-#define SYSMGR_SOC64_EMAC0			0x44
-#define SYSMGR_SOC64_EMAC1			0x48
-#define SYSMGR_SOC64_EMAC2			0x4c
-#define SYSMGR_SOC64_EMAC0_ACE			0x50
-#define SYSMGR_SOC64_EMAC1_ACE			0x54
-#define SYSMGR_SOC64_EMAC2_ACE			0x58
+#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5)
+#define SYSMGR_SOC64_SILICONID_1		0x00
+#define SYSMGR_SOC64_SILICONID_2		0x04
+#define SYSMGR_SOC64_MPU_STATUS			0x10
+#define SYSMGR_SOC64_COMBOPHY_DFISEL		0xfc
+#define SYSMGR_SOC64_COMBOPHY_DFISEL_SDMMC	0x1
+#define SYSMGR_SOC64_NANDGRP_L3MASTER		0x34
+#define SYSMGR_SOC64_USB0_L3MASTER		0x38
+#define SYSMGR_SOC64_USB1_L3MASTER		0x3c
+#define SYSMGR_SOC64_DMAC0_L3_MASTER		0x74
+#define SYSMGR_SOC64_ETR_L3_MASTER		0x78
+#define SYSMGR_SOC64_DMAC1_L3_MASTER		0x7C
+#define SYSMGR_SOC64_SEC_CTRL_SLT		0x80
+#define SYSMGR_SOC64_OSC_TRIM			0x84
+#define SYSMGR_SOC64_DMAC0_CTRL_STATUS_REG	0x88
+#define SYSMGR_SOC64_DMAC1_CTRL_STATUS_REG	0x8C
+#define SYSMGR_SOC64_ECC_INTMASK_VALUE		0x90
+#define SYSMGR_SOC64_ECC_INTMASK_SET		0x94
+#define SYSMGR_SOC64_ECC_INTMASK_CLR		0x98
+#define SYSMGR_SOC64_ECC_INTMASK_SERR		0x9C
+#define SYSMGR_SOC64_ECC_INTMASK_DERR		0xA0
+#define SYSMGR_SOC64_MPFE_CONFIG		0x228
+#define SYSMGR_SOC64_BOOT_SCRATCH_POR0		0x258
+#define SYSMGR_SOC64_BOOT_SCRATCH_POR1		0x25C
+#define SYSMGR_SCRATCH_REG_0_QSPI_REFCLK_MASK		GENMASK(31, 0)
+#define ALT_SYSMGR_SCRATCH_REG_3_DDR_RESET_TYPE_MASK	GENMASK(31, 29)
+#define ALT_SYSMGR_SCRATCH_REG_3_DDR_RESET_TYPE_SHIFT	29
+#define ALT_SYSMGR_SCRATCH_REG_3_DDR_PORT_INFO_MASK	BIT(27)
+#define ALT_SYSMGR_SCRATCH_REG_3_DDR_EMIF_INFO_MASK	BIT(28)
+#define ALT_SYSMGR_SCRATCH_REG_3_DDR_PORT_EMIF_INFO_MASK	GENMASK(28, 27)
+#define ALT_SYSMGR_SCRATCH_REG_3_DDR_DBE_MASK	BIT(1)
+#define ALT_SYSMGR_SCRATCH_REG_3_OCRAM_DBE_MASK	BIT(0)
+#define ALT_SYSMGR_SCRATCH_REG_POR_0_DDR_PROGRESS_MASK	BIT(0)
+#define ALT_SYSMGR_SCRATCH_REG_POR_1_REVA_WORKAROUND_USER_MODE_MASK	BIT(0)
+#define ALT_SYSMGR_SCRATCH_REG_POR_1_REVA_WORKAROUND_MASK	BIT(1)
+#else
 #define SYSMGR_SOC64_NAND_AXUSER		0x5c
-#define SYSMGR_SOC64_FPGAINTF_EN1		0x68
-#define SYSMGR_SOC64_FPGAINTF_EN2		0x6c
-#define SYSMGR_SOC64_FPGAINTF_EN3		0x70
 #define SYSMGR_SOC64_DMA_L3MASTER		0x74
 #if IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X)
 #define SYSMGR_SOC64_DDR_MODE			0xb8
@@ -34,39 +56,56 @@ void populate_sysmgr_pinmux(void);
 #define SYSMGR_SOC64_HMC_CLK			0xb4
 #define SYSMGR_SOC64_IO_PA_CTRL			0xb8
 #endif
-#define SYSMGR_SOC64_NOC_TIMEOUT		0xc0
-#define SYSMGR_SOC64_NOC_IDLEREQ_SET		0xc4
-#define SYSMGR_SOC64_NOC_IDLEREQ_CLR		0xc8
-#define SYSMGR_SOC64_NOC_IDLEREQ_VAL		0xcc
-#define SYSMGR_SOC64_NOC_IDLEACK		0xd0
-#define SYSMGR_SOC64_NOC_IDLESTATUS		0xd4
-#define SYSMGR_SOC64_FPGA2SOC_CTRL		0xd8
-#define SYSMGR_SOC64_FPGA_CONFIG		0xdc
 #define SYSMGR_SOC64_IOCSRCLK_GATE		0xe0
 #define SYSMGR_SOC64_GPO			0xe4
 #define SYSMGR_SOC64_GPI			0xe8
 #define SYSMGR_SOC64_MPU			0xf0
-/*
- * Bits[31:28] reserved for N5X DDR retention, bits[27:0] reserved for SOC 64-bit
- * storing qspi ref clock (kHz)
- */
-#define SYSMGR_SOC64_BOOT_SCRATCH_COLD0		0x200
-/* store osc1 clock freq */
-#define SYSMGR_SOC64_BOOT_SCRATCH_COLD1		0x204
-/* store fpga clock freq */
-#define SYSMGR_SOC64_BOOT_SCRATCH_COLD2		0x208
-/* reserved for customer use */
-#define SYSMGR_SOC64_BOOT_SCRATCH_COLD3		0x20c
-/* store PSCI_CPU_ON value */
-#define SYSMGR_SOC64_BOOT_SCRATCH_COLD4		0x210
-/* store PSCI_CPU_ON value */
-#define SYSMGR_SOC64_BOOT_SCRATCH_COLD5		0x214
-/* store VBAR_EL3 value */
-#define SYSMGR_SOC64_BOOT_SCRATCH_COLD6		0x218
-/* store VBAR_EL3 value */
-#define SYSMGR_SOC64_BOOT_SCRATCH_COLD7		0x21c
-#define SYSMGR_SOC64_BOOT_SCRATCH_COLD8		0x220
-#define SYSMGR_SOC64_BOOT_SCRATCH_COLD9		0x224
+#define SYSMGR_SCRATCH_REG_0_QSPI_REFCLK_MASK	GENMASK(27, 0)
+#endif /*CONFIG_TARGET_SOCFPGA_AGILEX5*/
+
+#define SYSMGR_SOC64_DMA			0x20
+#define SYSMGR_SOC64_DMA_PERIPH			0x24
+#define SYSMGR_SOC64_WDDBG			0x08
+#define SYSMGR_SOC64_SDMMC			0x28
+#define SYSMGR_SOC64_SDMMC_L3MASTER		0x2C
+#define SYSMGR_SOC64_FPGAINTF_EN1		0x68
+#define SYSMGR_SOC64_FPGAINTF_EN2		0x6C
+#define SYSMGR_SOC64_FPGAINTF_EN3		0x70
+#define SYSMGR_SOC64_NOC_TIMEOUT		0xC0
+#define SYSMGR_SOC64_NOC_IDLEREQ_SET		0xC4
+#define SYSMGR_SOC64_NOC_IDLEREQ_CLR		0xC8
+#define SYSMGR_SOC64_NOC_IDLEREQ_VAL		0xCC
+#define SYSMGR_SOC64_NOC_IDLEACK		0xd0
+#define SYSMGR_SOC64_NOC_IDLESTATUS		0xD4
+#define SYSMGR_SOC64_FPGA2SOC_CTRL		0xD8
+#define SYSMGR_SOC64_FPGA_CONFIG		0xDC
+
+#define SYSMGR_SOC64_TSN_GLOBAL			0x40
+#define SYSMGR_SOC64_TSN_0			0x44
+#define SYSMGR_SOC64_TSN_1			0x48
+#define SYSMGR_SOC64_TSN_2			0x4C
+#define SYSMGR_SOC64_TSN_0_ACE			0x50
+#define SYSMGR_SOC64_TSN_1_ACE			0x54
+#define SYSMGR_SOC64_TSN_2_ACE			0x58
+#define SYSMGR_SOC64_EMAC_GLOBAL	SYSMGR_SOC64_TSN_GLOBAL
+#define SYSMGR_SOC64_EMAC0		SYSMGR_SOC64_TSN_0
+#define SYSMGR_SOC64_EMAC1		SYSMGR_SOC64_TSN_1
+#define SYSMGR_SOC64_EMAC2		SYSMGR_SOC64_TSN_2
+#define SYSMGR_SOC64_EMAC0_ACE		SYSMGR_SOC64_TSN_0_ACE
+#define SYSMGR_SOC64_EMAC1_ACE		SYSMGR_SOC64_TSN_1_ACE
+#define SYSMGR_SOC64_EMAC2_ACE		SYSMGR_SOC64_TSN_2_ACE
+
+#define SYSMGR_SOC64_BOOT_SCRATCH_COLD0	0x200
+#define SYSMGR_SOC64_BOOT_SCRATCH_COLD1	0x204
+#define SYSMGR_SOC64_BOOT_SCRATCH_COLD2	0x208
+#define SYSMGR_SOC64_BOOT_SCRATCH_COLD3	0x20C
+#define SYSMGR_SOC64_BOOT_SCRATCH_COLD4	0x210
+#define SYSMGR_SOC64_BOOT_SCRATCH_COLD5	0x214
+#define SYSMGR_SOC64_BOOT_SCRATCH_COLD6	0x218
+#define SYSMGR_SOC64_BOOT_SCRATCH_COLD7	0x21C
+#define SYSMGR_SOC64_BOOT_SCRATCH_COLD8	0x220
+#define SYSMGR_SOC64_BOOT_SCRATCH_COLD9	0x224
+
 #define SYSMGR_SOC64_PINSEL0			0x1000
 #define SYSMGR_SOC64_IOCTRL0			0x1130
 #define SYSMGR_SOC64_EMAC0_USEFPGA		0x1300
@@ -97,7 +136,6 @@ void populate_sysmgr_pinmux(void);
  * Bits[31:28] reserved for DM DDR retention, bits[27:0] reserved for SOC 64-bit
  * storing qspi ref clock (kHz)
  */
-#define SYSMGR_SCRATCH_REG_0_QSPI_REFCLK_MASK		GENMASK(27, 0)
 #define ALT_SYSMGR_SCRATCH_REG_0_DDR_RETENTION_MASK	BIT(31)
 #define ALT_SYSMGR_SCRATCH_REG_0_DDR_SHA_MASK		BIT(30)
 #define ALT_SYSMGR_SCRATCH_REG_0_DDR_RESET_TYPE_MASK	(BIT(29) | BIT(28))
diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c
index 46f9c82bbb2..97e01140513 100644
--- a/arch/arm/mach-socfpga/misc.c
+++ b/arch/arm/mach-socfpga/misc.c
@@ -1,31 +1,33 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
- *  Copyright (C) 2012-2017 Altera Corporation <www.altera.com>
+ *  Copyright (C) 2012-2025 Altera Corporation <www.altera.com>
  */
 
 #include <config.h>
 #include <command.h>
-#include <cpu_func.h>
-#include <hang.h>
-#include <asm/cache.h>
-#include <init.h>
-#include <asm/global_data.h>
-#include <asm/io.h>
 #include <errno.h>
+#include <init.h>
+#include <handoff.h>
+#include <hang.h>
+#include <watchdog.h>
 #include <fdtdec.h>
 #include <linux/libfdt.h>
-#include <altera.h>
+#include <linux/printk.h>
 #include <miiphy.h>
 #include <netdev.h>
-#include <watchdog.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <asm/cache.h>
+#include <asm/pl310.h>
 #include <asm/arch/misc.h>
+#include <asm/arch/nic301.h>
 #include <asm/arch/reset_manager.h>
 #include <asm/arch/scan_manager.h>
-#include <asm/arch/system_manager.h>
-#include <asm/arch/nic301.h>
 #include <asm/arch/scu.h>
-#include <asm/pl310.h>
-#include <linux/printk.h>
+#include <asm/arch/system_manager.h>
+#include <altera.h>
+#include <bloblist.h>
+#include <cpu_func.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -51,8 +53,18 @@ struct bsel bsel_str[] = {
 
 int dram_init(void)
 {
+#if CONFIG_IS_ENABLED(HANDOFF) && IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5)
+	struct spl_handoff *ho;
+
+	ho = bloblist_find(BLOBLISTT_U_BOOT_SPL_HANDOFF, sizeof(*ho));
+	if (!ho)
+		return log_msg_ret("Missing SPL hand-off info", -ENOENT);
+	gd->ram_size = ho->ram_bank[0].size;
+	gd->ram_base = ho->ram_bank[0].start;
+#else
 	if (fdtdec_setup_mem_size_base() != 0)
 		return -EINVAL;
+#endif /* HANDOFF && CONFIG_TARGET_SOCFPGA_AGILEX5 */
 
 	return 0;
 }
@@ -248,21 +260,32 @@ void socfpga_get_managers_addr(void)
 	if (ret)
 		hang();
 
-	ret = socfpga_get_base_addr("altr,sys-mgr", &socfpga_sysmgr_base);
+	if (IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX))
+		ret = socfpga_get_base_addr("intel,agilex-clkmgr",
+					    &socfpga_clkmgr_base);
+	else if (IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X))
+		ret = socfpga_get_base_addr("intel,n5x-clkmgr",
+					    &socfpga_clkmgr_base);
+	else if (!IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5))
+		ret = socfpga_get_base_addr("altr,clk-mgr",
+					    &socfpga_clkmgr_base);
+
 	if (ret)
 		hang();
+}
 
-#ifdef CONFIG_TARGET_SOCFPGA_AGILEX
-	ret = socfpga_get_base_addr("intel,agilex-clkmgr",
-				    &socfpga_clkmgr_base);
-#elif IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X)
-	ret = socfpga_get_base_addr("intel,n5x-clkmgr",
-				    &socfpga_clkmgr_base);
-#else
-	ret = socfpga_get_base_addr("altr,clk-mgr", &socfpga_clkmgr_base);
-#endif
-	if (ret)
+void socfpga_get_sys_mgr_addr(const char *compat)
+{
+	int ret;
+	struct udevice *sysmgr_dev;
+
+	ret = uclass_get_device_by_name(UCLASS_NOP, compat, &sysmgr_dev);
+	if (ret) {
+		printf("Altera system manager init failed: %d\n", ret);
 		hang();
+	} else {
+		socfpga_sysmgr_base = (phys_addr_t)dev_read_addr(sysmgr_dev);
+	}
 }
 
 phys_addr_t socfpga_get_rstmgr_addr(void)
diff --git a/arch/arm/mach-socfpga/misc_soc64.c b/arch/arm/mach-socfpga/misc_soc64.c
index a6cc78454da..e0b2b4237e1 100644
--- a/arch/arm/mach-socfpga/misc_soc64.c
+++ b/arch/arm/mach-socfpga/misc_soc64.c
@@ -1,20 +1,23 @@
 // SPDX-License-Identifier: GPL-2.0
 /*
  * Copyright (C) 2016-2018 Intel Corporation <www.intel.com>
+ * Copyright (C) 2025 Altera Corporation <www.altera.com>
  *
  */
 
 #include <altera.h>
+#include <env.h>
+#include <errno.h>
+#include <init.h>
+#include <log.h>
+#include <asm/arch/board.h>
 #include <asm/arch/mailbox_s10.h>
 #include <asm/arch/misc.h>
 #include <asm/arch/reset_manager.h>
 #include <asm/arch/system_manager.h>
 #include <asm/io.h>
+#include <asm/system.h>
 #include <asm/global_data.h>
-#include <env.h>
-#include <errno.h>
-#include <init.h>
-#include <log.h>
 #include <mach/clock_manager.h>
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -40,12 +43,26 @@ static Altera_desc altera_fpga[] = {
 };
 
 /*
+ * The Agilex5 platform has enabled the bloblist feature, and the bloblist
+ * address and size are initialized based on the defconfig settings.
+ * During the SPL phase, this function is used to prevent the bloblist
+ * from initializing its address and size with the saved boot parameters,
+ * which may have been incorrectly set.
+ */
+void save_boot_params(unsigned long r0, unsigned long r1, unsigned long r2,
+		      unsigned long r3)
+{
+	save_boot_params_ret();
+}
+
+/*
  * Print CPU information
  */
 #if defined(CONFIG_DISPLAY_CPUINFO)
 int print_cpuinfo(void)
 {
-	puts("CPU:   Intel FPGA SoCFPGA Platform (ARMv8 64bit Cortex-A53)\n");
+	printf("CPU: Intel FPGA SoCFPGA Platform (ARMv8 64bit Cortex-%s)\n",
+	       IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) ? "A55/A76" : "A53");
 
 	return 0;
 }
@@ -55,10 +72,15 @@ int print_cpuinfo(void)
 int arch_misc_init(void)
 {
 	char qspi_string[13];
+	unsigned long id;
 
 	sprintf(qspi_string, "<0x%08x>", cm_get_qspi_controller_clk_hz());
 	env_set("qspi_clock", qspi_string);
 
+	/* Export board_id as environment variable */
+	id = socfpga_get_board_id();
+	env_set_ulong("board_id", id);
+
 	return 0;
 }
 #endif
diff --git a/arch/arm/mach-socfpga/smc_api.c b/arch/arm/mach-socfpga/smc_api.c
index ebaa0b8fa17..b212a94b321 100644
--- a/arch/arm/mach-socfpga/smc_api.c
+++ b/arch/arm/mach-socfpga/smc_api.c
@@ -1,9 +1,11 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright (C) 2020 Intel Corporation <www.intel.com>
+ * Copyright (C) 2025 Altera Corporation <www.altera.com>
  *
  */
 
+#include <cpu_func.h>
 #include <asm/ptrace.h>
 #include <asm/system.h>
 #include <linux/errno.h>
@@ -40,10 +42,16 @@ int smc_send_mailbox(u32 cmd, u32 len, u32 *arg, u8 urgent, u32 *resp_buf_len,
 	args[2] = len;
 	args[3] = urgent;
 	args[4] = (u64)resp_buf;
-	if (resp_buf_len)
+
+	if (arg && len > 0)
+		flush_dcache_range((uintptr_t)arg, (uintptr_t)arg + len);
+
+	if (resp_buf && resp_buf_len && *resp_buf_len > 0) {
 		args[5] = *resp_buf_len;
-	else
+		flush_dcache_range((uintptr_t)resp_buf, (uintptr_t)resp_buf + *resp_buf_len);
+	} else {
 		args[5] = 0;
+	}
 
 	ret = invoke_smc(INTEL_SIP_SMC_MBOX_SEND_CMD, args, ARRAY_SIZE(args),
 			 resp, ARRAY_SIZE(resp));
diff --git a/arch/arm/mach-socfpga/spl_agilex5.c b/arch/arm/mach-socfpga/spl_agilex5.c
new file mode 100644
index 00000000000..3451611082d
--- /dev/null
+++ b/arch/arm/mach-socfpga/spl_agilex5.c
@@ -0,0 +1,110 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2024 Intel Corporation <www.intel.com>
+ * Copyright (C) 2025 Altera Corporation <www.altera.com>
+ *
+ */
+
+#include <init.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <hang.h>
+#include <spl.h>
+#include <asm/arch/base_addr_soc64.h>
+#include <asm/arch/clock_manager.h>
+#include <asm/arch/mailbox_s10.h>
+#include <asm/arch/misc.h>
+#include <asm/arch/reset_manager.h>
+#include <asm/arch/system_manager.h>
+#include <wdt.h>
+#include <dm/uclass.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+u32 reset_flag(void)
+{
+	/* Check rstmgr.stat for warm reset status */
+	u32 status = readl(SOCFPGA_RSTMGR_ADDRESS);
+
+	/* Check whether any L4 watchdogs or SDM had triggered warm reset */
+	u32 warm_reset_mask = RSTMGR_L4WD_MPU_WARMRESET_MASK;
+
+	if (status & warm_reset_mask)
+		return 0;
+
+	return 1;
+}
+
+void board_init_f(ulong dummy)
+{
+	int ret;
+	struct udevice *dev;
+
+	/* Enable Async */
+	asm volatile("msr daifclr, #4");
+
+#ifdef CONFIG_SPL_BUILD
+	spl_save_restore_data();
+#endif
+
+	ret = spl_early_init();
+	if (ret)
+		hang();
+
+	socfpga_get_sys_mgr_addr("sysmgr@10d12000");
+	socfpga_get_managers_addr();
+
+	sysmgr_pinmux_init();
+
+	/* Ensure watchdog is paused when debugging is happening */
+	writel(SYSMGR_WDDBG_PAUSE_ALL_CPU,
+	       socfpga_get_sysmgr_addr() + SYSMGR_SOC64_WDDBG);
+
+	timer_init();
+
+	ret = uclass_get_device(UCLASS_CLK, 0, &dev);
+	if (ret) {
+		debug("Clock init failed: %d\n", ret);
+		hang();
+	}
+
+	/*
+	 * Enable watchdog as early as possible before initializing other
+	 * component. Watchdog need to be enabled after clock driver because
+	 * it will retrieve the clock frequency from clock driver.
+	 */
+	if (CONFIG_IS_ENABLED(WDT))
+		initr_watchdog();
+
+	preloader_console_init();
+	print_reset_info();
+	cm_print_clock_quick_summary();
+
+	ret = uclass_get_device_by_name(UCLASS_NOP, "socfpga-ccu-config", &dev);
+	if (ret) {
+		printf("HPS CCU settings init failed: %d\n", ret);
+		hang();
+	}
+
+	ret = uclass_get_device_by_name(UCLASS_NOP, "socfpga-firewall-config", &dev);
+	if (ret) {
+		printf("HPS firewall settings init failed: %d\n", ret);
+		hang();
+	}
+
+	if (IS_ENABLED(CONFIG_SPL_ALTERA_SDRAM)) {
+		ret = uclass_get_device(UCLASS_RAM, 0, &dev);
+		if (ret) {
+			debug("DRAM init failed: %d\n", ret);
+			hang();
+		}
+	}
+
+	mbox_init();
+
+	if (IS_ENABLED(CONFIG_CADENCE_QSPI))
+		mbox_qspi_open();
+
+	/* Enable non secure access to ocram */
+	clrbits_le32(SOCFPGA_OCRAM_FIREWALL_ADDRESS + 0x18, BIT(0));
+}
diff --git a/arch/arm/mach-socfpga/spl_soc64.c b/arch/arm/mach-socfpga/spl_soc64.c
index 4fe67ea0811..651d9fc9cb8 100644
--- a/arch/arm/mach-socfpga/spl_soc64.c
+++ b/arch/arm/mach-socfpga/spl_soc64.c
@@ -1,10 +1,13 @@
 // SPDX-License-Identifier: GPL-2.0
 /*
  *  Copyright (C) 2020 Intel Corporation. All rights reserved
+ *  Copyright (C) 2025 Altera Corporation <www.altera.com>
  *
  */
 
+#include <hang.h>
 #include <spl.h>
+#include <dm/uclass.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -13,6 +16,109 @@ u32 spl_boot_device(void)
 	return BOOT_DEVICE_MMC1;
 }
 
+/* This function is to map specified node onto SPL boot devices */
+static int spl_node_to_boot_device(int node)
+{
+	const void *blob = gd->fdt_blob;
+	struct udevice *parent;
+	const char *prop;
+
+	if (!uclass_get_device_by_of_offset(UCLASS_MMC, node, &parent))
+		return BOOT_DEVICE_MMC1;
+	else if (!uclass_get_device_by_of_offset(UCLASS_SPI_FLASH, node, &parent))
+		return BOOT_DEVICE_SPI;
+	else if (!uclass_get_device_by_of_offset(UCLASS_MTD, node, &parent))
+		return BOOT_DEVICE_NAND;
+
+	prop = fdt_getprop(blob, node, "device_type", NULL);
+	if (prop) {
+		if (!strcmp(prop, "memory"))
+			return BOOT_DEVICE_RAM;
+
+		printf("%s: unknown device_type %s\n", __func__, prop);
+	}
+
+	return -ENODEV;
+}
+
+static void default_spl_boot_list(u32 *spl_boot_list, int length)
+{
+	spl_boot_list[0] = spl_boot_device();
+
+	if (length > 1)
+		spl_boot_list[1] = BOOT_DEVICE_SPI;
+
+	if (length > 2)
+		spl_boot_list[2] = BOOT_DEVICE_NAND;
+}
+
+void board_boot_order(u32 *spl_boot_list)
+{
+	int idx = 0;
+	const void *blob = gd->fdt_blob;
+	int chosen_node = fdt_path_offset(blob, "/chosen");
+	const char *conf;
+	int elem;
+	int boot_device;
+	int node;
+	int length;
+
+	/* expect valid initialized spl_boot_list */
+	if (!spl_boot_list)
+		return;
+
+	length = 1;
+	while (spl_boot_list[length] == spl_boot_list[length - 1])
+		length++;
+
+	debug("%s: chosen_node is %d\n", __func__, chosen_node);
+	if (chosen_node < 0) {
+		printf("%s: /chosen not found, using default\n", __func__);
+		default_spl_boot_list(spl_boot_list, length);
+		return;
+	}
+
+	for (elem = 0;
+	    (conf = fdt_stringlist_get(blob, chosen_node,
+			"u-boot,spl-boot-order", elem, NULL));
+	    elem++) {
+		if (idx >= length) {
+			printf("%s: limit %d to spl_boot_list exceeded\n", __func__,
+			       length);
+			break;
+		}
+
+		/* Resolve conf item as a path in device tree */
+		node = fdt_path_offset(blob, conf);
+		if (node < 0) {
+			debug("%s: could not find %s in FDT\n", __func__, conf);
+			continue;
+		}
+
+		/* Try to map spl node back onto SPL boot devices */
+		boot_device = spl_node_to_boot_device(node);
+		if (boot_device < 0) {
+			debug("%s: could not map node @%x to a boot-device\n",
+			      __func__, node);
+			continue;
+		}
+
+		spl_boot_list[idx] = boot_device;
+		debug("%s: spl_boot_list[%d] = %u\n", __func__, idx,
+		      spl_boot_list[idx]);
+		idx++;
+	}
+
+	if (idx == 0) {
+		if (!conf && !elem) {
+			printf("%s: spl-boot-order invalid, using default\n", __func__);
+			default_spl_boot_list(spl_boot_list, length);
+		} else {
+			printf("%s: no valid element spl-boot-order list\n", __func__);
+		}
+	}
+}
+
 #if IS_ENABLED(CONFIG_SPL_MMC)
 u32 spl_boot_mode(const u32 boot_device)
 {
@@ -22,3 +128,16 @@ u32 spl_boot_mode(const u32 boot_device)
 		return MMCSD_MODE_RAW;
 }
 #endif
+
+/* board specific function prior loading SSBL / U-Boot */
+void spl_perform_fixups(struct spl_image_info *spl_image)
+{
+	int ret;
+	struct udevice *dev;
+
+	ret = uclass_get_device_by_name(UCLASS_NOP, "socfpga-smmu-secure-config", &dev);
+	if (ret) {
+		printf("HPS SMMU secure settings init failed: %d\n", ret);
+		hang();
+	}
+}
diff --git a/arch/arm/mach-socfpga/wrap_handoff_soc64.c b/arch/arm/mach-socfpga/wrap_handoff_soc64.c
index 92051d19b73..7105cdc4905 100644
--- a/arch/arm/mach-socfpga/wrap_handoff_soc64.c
+++ b/arch/arm/mach-socfpga/wrap_handoff_soc64.c
@@ -1,15 +1,17 @@
 // SPDX-License-Identifier: GPL-2.0
 /*
  * Copyright (C) 2020-2021 Intel Corporation <www.intel.com>
+ * Copyright (C) 2025 Altera Corporation <www.altera.com>
  *
  */
 
+#include <errno.h>
 #include <asm/arch/handoff_soc64.h>
 #include <asm/io.h>
-#include <errno.h>
 #include "log.h"
 
 #ifndef __ASSEMBLY__
+#include <asm/types.h>
 enum endianness {
 	LITTLE_ENDIAN = 0,
 	BIG_ENDIAN,
@@ -26,7 +28,12 @@ static enum endianness check_endianness(u32 handoff)
 	case SOC64_HANDOFF_MAGIC_FPGA:
 	case SOC64_HANDOFF_MAGIC_DELAY:
 	case SOC64_HANDOFF_MAGIC_CLOCK:
+	case SOC64_HANDOFF_MAGIC_SDRAM:
+#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5)
+	case SOC64_HANDOFF_MAGIC_PERI:
+#else
 	case SOC64_HANDOFF_MAGIC_MISC:
+#endif
 		return BIG_ENDIAN;
 #if IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X)
 	case SOC64_HANDOFF_DDR_UMCTL2_MAGIC:
diff --git a/arch/arm/mach-stm32mp/Kconfig b/arch/arm/mach-stm32mp/Kconfig
index 25663a99464..002da2e3d3b 100644
--- a/arch/arm/mach-stm32mp/Kconfig
+++ b/arch/arm/mach-stm32mp/Kconfig
@@ -153,6 +153,12 @@ config CMD_STM32KEY
 		This command is used to evaluate the secure boot on stm32mp SOC,
 		it is deactivated by default in real products.
 
+config MFD_STM32_TIMERS
+	bool "STM32 multifonction timer support"
+	help
+	  Select this to enable support for the multifunction timer found on
+	  STM32 devices.
+
 source "arch/arm/mach-stm32mp/Kconfig.13x"
 source "arch/arm/mach-stm32mp/Kconfig.15x"
 source "arch/arm/mach-stm32mp/Kconfig.25x"
diff --git a/arch/arm/mach-stm32mp/Makefile b/arch/arm/mach-stm32mp/Makefile
index db7ed19bd91..103e3410ad9 100644
--- a/arch/arm/mach-stm32mp/Makefile
+++ b/arch/arm/mach-stm32mp/Makefile
@@ -12,6 +12,7 @@ obj-$(CONFIG_STM32MP15X) += stm32mp1/
 obj-$(CONFIG_STM32MP13X) += stm32mp1/
 obj-$(CONFIG_STM32MP25X) += stm32mp2/
 
+obj-$(CONFIG_MFD_STM32_TIMERS) += timers.o
 obj-$(CONFIG_STM32_ECDSA_VERIFY) += ecdsa_romapi.o
 ifndef CONFIG_XPL_BUILD
 obj-y += cmd_stm32prog/
diff --git a/arch/arm/mach-stm32mp/include/mach/timers.h b/arch/arm/mach-stm32mp/include/mach/timers.h
new file mode 100644
index 00000000000..a84465bb28e
--- /dev/null
+++ b/arch/arm/mach-stm32mp/include/mach/timers.h
@@ -0,0 +1,55 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (C) 2025, STMicroelectronics - All Rights Reserved
+ * Author: Cheick Traore <cheick.traore@foss.st.com>
+ *
+ * Originally based on the Linux kernel v6.1 include/linux/mfd/stm32-timers.h.
+ */
+
+#ifndef __STM32_TIMERS_H
+#define __STM32_TIMERS_H
+
+#include <clk.h>
+
+#define TIM_CR1		0x00	/* Control Register 1      */
+#define TIM_CR2		0x04	/* Control Register 2      */
+#define TIM_SMCR	0x08	/* Slave mode control reg  */
+#define TIM_DIER	0x0C	/* DMA/interrupt register  */
+#define TIM_SR		0x10	/* Status register	   */
+#define TIM_EGR		0x14	/* Event Generation Reg    */
+#define TIM_CCMR1	0x18	/* Capt/Comp 1 Mode Reg    */
+#define TIM_CCMR2	0x1C	/* Capt/Comp 2 Mode Reg    */
+#define TIM_CCER	0x20	/* Capt/Comp Enable Reg    */
+#define TIM_CNT		0x24	/* Counter		   */
+#define TIM_PSC		0x28	/* Prescaler               */
+#define TIM_ARR		0x2c	/* Auto-Reload Register    */
+#define TIM_CCRx(x)	(0x34 + 4 * ((x) - 1))	/* Capt/Comp Register x (x ∈ {1, .. 4})	*/
+#define TIM_BDTR	0x44	/* Break and Dead-Time Reg */
+#define TIM_DCR		0x48	/* DMA control register    */
+#define TIM_DMAR	0x4C	/* DMA register for transfer */
+#define TIM_TISEL	0x68	/* Input Selection         */
+
+#define TIM_CR1_CEN	BIT(0)	/* Counter Enable	   */
+#define TIM_CR1_ARPE	BIT(7)
+#define TIM_CCER_CCXE	(BIT(0) | BIT(4) | BIT(8) | BIT(12))
+#define TIM_CCER_CC1E	BIT(0)
+#define TIM_CCER_CC1P	BIT(1)	/* Capt/Comp 1  Polarity   */
+#define TIM_CCER_CC1NE	BIT(2)	/* Capt/Comp 1N out Ena    */
+#define TIM_CCER_CC1NP	BIT(3)	/* Capt/Comp 1N Polarity   */
+#define TIM_CCMR_PE	BIT(3)	/* Channel Preload Enable  */
+#define TIM_CCMR_M1	(BIT(6) | BIT(5))  /* Channel PWM Mode 1 */
+#define TIM_BDTR_MOE	BIT(15)	/* Main Output Enable      */
+#define TIM_EGR_UG	BIT(0)	/* Update Generation       */
+
+#define MAX_TIM_PSC		0xFFFF
+
+struct stm32_timers_plat {
+	void __iomem *base;
+};
+
+struct stm32_timers_priv {
+	u32 max_arr;
+	ulong rate;
+};
+
+#endif
diff --git a/arch/arm/mach-stm32mp/stm32mp1/cpu.c b/arch/arm/mach-stm32mp/stm32mp1/cpu.c
index d5eaf6711b6..18175fd12cc 100644
--- a/arch/arm/mach-stm32mp/stm32mp1/cpu.c
+++ b/arch/arm/mach-stm32mp/stm32mp1/cpu.c
@@ -138,8 +138,6 @@ int mach_cpu_init(void)
 	if (IS_ENABLED(CONFIG_CMD_STM32PROG_SERIAL) &&
 	    (boot_mode & TAMP_BOOT_DEVICE_MASK) == BOOT_SERIAL_UART)
 		gd->flags |= GD_FLG_SILENT | GD_FLG_DISABLE_CONSOLE;
-	else if (IS_ENABLED(CONFIG_DEBUG_UART) && IS_ENABLED(CONFIG_XPL_BUILD))
-		debug_uart_init();
 
 	return 0;
 }
diff --git a/arch/arm/mach-stm32mp/timers.c b/arch/arm/mach-stm32mp/timers.c
new file mode 100644
index 00000000000..a3207895f40
--- /dev/null
+++ b/arch/arm/mach-stm32mp/timers.c
@@ -0,0 +1,82 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2025, STMicroelectronics - All Rights Reserved
+ * Author: Cheick Traore <cheick.traore@foss.st.com>
+ *
+ * Originally based on the Linux kernel v6.1 drivers/mfd/stm32-timers.c.
+ */
+
+#include <dm.h>
+#include <asm/io.h>
+#include <asm/arch/timers.h>
+#include <dm/device_compat.h>
+
+static void stm32_timers_get_arr_size(struct udevice *dev)
+{
+	struct stm32_timers_plat *plat = dev_get_plat(dev);
+	struct stm32_timers_priv *priv = dev_get_priv(dev);
+	u32 arr;
+
+	/* Backup ARR to restore it after getting the maximum value */
+	arr = readl(plat->base + TIM_ARR);
+
+	/*
+	 * Only the available bits will be written so when readback
+	 * we get the maximum value of auto reload register
+	 */
+	writel(~0L, plat->base + TIM_ARR);
+	priv->max_arr = readl(plat->base + TIM_ARR);
+	writel(arr, plat->base + TIM_ARR);
+}
+
+static int stm32_timers_of_to_plat(struct udevice *dev)
+{
+	struct stm32_timers_plat *plat = dev_get_plat(dev);
+
+	plat->base = dev_read_addr_ptr(dev);
+	if (!plat->base) {
+		dev_err(dev, "can't get address\n");
+		return -ENOENT;
+	}
+
+	return 0;
+}
+
+static int stm32_timers_probe(struct udevice *dev)
+{
+	struct stm32_timers_priv *priv = dev_get_priv(dev);
+	struct clk clk;
+	int ret = 0;
+
+	ret = clk_get_by_index(dev, 0, &clk);
+	if (ret < 0)
+		return ret;
+
+	ret = clk_enable(&clk);
+	if (ret) {
+		dev_err(dev, "failed to enable clock: ret=%d\n", ret);
+		return ret;
+	}
+
+	priv->rate = clk_get_rate(&clk);
+
+	stm32_timers_get_arr_size(dev);
+
+	return ret;
+}
+
+static const struct udevice_id stm32_timers_ids[] = {
+	{ .compatible = "st,stm32-timers" },
+	{}
+};
+
+U_BOOT_DRIVER(stm32_timers) = {
+	.name  = "stm32_timers",
+	.id = UCLASS_NOP,
+	.of_match = stm32_timers_ids,
+	.of_to_plat = stm32_timers_of_to_plat,
+	.plat_auto = sizeof(struct stm32_timers_plat),
+	.probe = stm32_timers_probe,
+	.priv_auto = sizeof(struct stm32_timers_priv),
+	.bind = dm_scan_fdt_dev,
+};
diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig
index ba1b1541437..ab432390d3c 100644
--- a/arch/arm/mach-sunxi/Kconfig
+++ b/arch/arm/mach-sunxi/Kconfig
@@ -457,6 +457,9 @@ config MACH_SUN50I_H616
 	select SUN50I_GEN_H6
 	imply OF_UPSTREAM
 
+config MACH_SUN50I_A133
+	bool "sun50i (Allwinner A133)"
+
 endchoice
 
 # The sun8i SoCs share a lot, this helps to avoid a lot of "if A23 || A33"
@@ -713,16 +716,10 @@ endif
 
 config SYS_CLK_FREQ
 	default 408000000 if MACH_SUNIV
-	default 1008000000 if MACH_SUN4I
-	default 1008000000 if MACH_SUN5I
-	default 1008000000 if MACH_SUN6I
-	default 912000000 if MACH_SUN7I
 	default 816000000 if MACH_SUN50I || MACH_SUN50I_H5
-	default 1008000000 if MACH_SUN8I
-	default 1008000000 if MACH_SUN9I
 	default 888000000 if MACH_SUN50I_H6
-	default 1008000000 if MACH_SUN50I_H616
-	default 1008000000 if MACH_SUN8I_R528
+	default 912000000 if MACH_SUN7I
+	default 1008000000
 
 config SYS_CONFIG_NAME
 	default "suniv" if MACH_SUNIV
@@ -1131,10 +1128,6 @@ config BLUETOOTH_DT_DEVICE_FIXUP
 	  The used address is "bdaddr" if set, and "ethaddr" with the LSB
 	  flipped elsewise.
 
-source "board/sunxi/Kconfig"
-
-endif
-
 config CHIP_DIP_SCAN
 	bool "Enable DIPs detection for CHIP board"
 	select SUPPORT_EXTENSION_SCAN
@@ -1143,3 +1136,7 @@ config CHIP_DIP_SCAN
 	select W1_EEPROM
 	select W1_EEPROM_DS24XXX
 	select CMD_EXTENSION
+
+source "board/sunxi/Kconfig"
+
+endif
diff --git a/arch/arm/mach-sunxi/clock_sun50i_h6.c b/arch/arm/mach-sunxi/clock_sun50i_h6.c
index b424a7893ea..359513d1669 100644
--- a/arch/arm/mach-sunxi/clock_sun50i_h6.c
+++ b/arch/arm/mach-sunxi/clock_sun50i_h6.c
@@ -147,15 +147,20 @@ unsigned int clock_get_pll6(void)
 	if (IS_ENABLED(CONFIG_SUNXI_GEN_NCAT2)) {
 		div1 = ((rval & CCM_PLL6_CTRL_P0_MASK) >>
 			CCM_PLL6_CTRL_P0_SHIFT) + 1;
-		m = 1;
 	} else {
 		div1 = ((rval & CCM_PLL6_CTRL_DIV1_MASK) >>
 			CCM_PLL6_CTRL_DIV1_SHIFT) + 1;
-		if (IS_ENABLED(CONFIG_MACH_SUN50I_H6))
-			m = 4;
-		else
-			m = 2;
 	}
 
+	/*
+	 * The factors encoded in the register describe the doubled clock
+	 * frequency, expect for the H6, where it's the quadrupled frequency.
+	 * Compensate for that here.
+	 */
+	if (IS_ENABLED(CONFIG_MACH_SUN50I_H6))
+		m = 4;
+	else
+		m = 2;
+
 	return 24000000U * n / m / div1 / div2;
 }
diff --git a/arch/arm/mach-sunxi/dram_sun50i_h616.c b/arch/arm/mach-sunxi/dram_sun50i_h616.c
index b3554cc64bf..cd9d321a018 100644
--- a/arch/arm/mach-sunxi/dram_sun50i_h616.c
+++ b/arch/arm/mach-sunxi/dram_sun50i_h616.c
@@ -1360,36 +1360,94 @@ static void mctl_auto_detect_rank_width(const struct dram_para *para,
 	panic("This DRAM setup is currently not supported.\n");
 }
 
+static void mctl_write_pattern(void)
+{
+	unsigned int i;
+	u32 *ptr, val;
+
+	ptr = (u32 *)CFG_SYS_SDRAM_BASE;
+	for (i = 0; i < 16; ptr++, i++) {
+		if (i & 1)
+			val = ~(ulong)ptr;
+		else
+			val = (ulong)ptr;
+		writel(val, ptr);
+	}
+}
+
+static bool mctl_check_pattern(ulong offset)
+{
+	unsigned int i;
+	u32 *ptr, val;
+
+	ptr = (u32 *)CFG_SYS_SDRAM_BASE;
+	for (i = 0; i < 16; ptr++, i++) {
+		if (i & 1)
+			val = ~(ulong)ptr;
+		else
+			val = (ulong)ptr;
+		if (val != *(ptr + offset / 4))
+			return false;
+	}
+
+	return true;
+}
+
 static void mctl_auto_detect_dram_size(const struct dram_para *para,
 				       struct dram_config *config)
 {
-	unsigned int shift;
+	unsigned int shift, cols, rows;
+	u32 buffer[16];
 
 	/* max. config for columns, but not rows */
 	config->cols = 11;
 	config->rows = 13;
 	mctl_core_init(para, config);
 
+	/*
+	 * Store content so it can be restored later. This is important
+	 * if controller was already initialized and holds any data
+	 * which is important for restoring system.
+	 */
+	memcpy(buffer, (u32 *)CFG_SYS_SDRAM_BASE, sizeof(buffer));
+
+	mctl_write_pattern();
+
 	shift = config->bus_full_width + 1;
 
 	/* detect column address bits */
-	for (config->cols = 8; config->cols < 11; config->cols++) {
-		if (mctl_mem_matches(1ULL << (config->cols + shift)))
+	for (cols = 8; cols < 11; cols++) {
+		if (mctl_check_pattern(1ULL << (cols + shift)))
 			break;
 	}
-	debug("detected %u columns\n", config->cols);
+	debug("detected %u columns\n", cols);
+
+	/* restore data */
+	memcpy((u32 *)CFG_SYS_SDRAM_BASE, buffer, sizeof(buffer));
 
 	/* reconfigure to make sure that all active rows are accessible */
-	config->rows = 18;
+	config->cols = 8;
+	config->rows = 17;
 	mctl_core_init(para, config);
 
+	/* store data again as it might be moved */
+	memcpy(buffer, (u32 *)CFG_SYS_SDRAM_BASE, sizeof(buffer));
+
+	mctl_write_pattern();
+
 	/* detect row address bits */
 	shift = config->bus_full_width + 4 + config->cols;
-	for (config->rows = 13; config->rows < 18; config->rows++) {
-		if (mctl_mem_matches(1ULL << (config->rows + shift)))
+	for (rows = 13; rows < 17; rows++) {
+		if (mctl_check_pattern(1ULL << (rows + shift)))
 			break;
 	}
-	debug("detected %u rows\n", config->rows);
+	debug("detected %u rows\n", rows);
+
+	/* restore data again */
+	memcpy((u32 *)CFG_SYS_SDRAM_BASE, buffer, sizeof(buffer));
+
+	config->cols = cols;
+	config->rows = rows;
 }
 
 static unsigned long mctl_calc_size(const struct dram_config *config)
diff --git a/arch/arm/mach-sunxi/pmic_bus.c b/arch/arm/mach-sunxi/pmic_bus.c
index 8e19324c8ac..c77dc538456 100644
--- a/arch/arm/mach-sunxi/pmic_bus.c
+++ b/arch/arm/mach-sunxi/pmic_bus.c
@@ -16,33 +16,10 @@
 #include <power/pmic.h>
 #include <asm/arch/pmic_bus.h>
 
-#define AXP152_I2C_ADDR			0x30
-
-#define AXP209_I2C_ADDR			0x34
-#define AXP717_I2C_ADDR			0x34
-
-#define AXP305_I2C_ADDR			0x36
-#define AXP313_I2C_ADDR			0x36
-
 #define AXP221_CHIP_ADDR		0x68
 
 #if CONFIG_IS_ENABLED(PMIC_AXP)
 static struct udevice *pmic;
-#else
-static int pmic_i2c_address(void)
-{
-	if (IS_ENABLED(CONFIG_AXP152_POWER))
-		return AXP152_I2C_ADDR;
-	if (IS_ENABLED(CONFIG_AXP305_POWER))
-		return AXP305_I2C_ADDR;
-	if (IS_ENABLED(CONFIG_AXP313_POWER))
-		return AXP313_I2C_ADDR;
-	if (IS_ENABLED(CONFIG_AXP717_POWER))
-		return AXP717_I2C_ADDR;
-
-	/* Other AXP2xx and AXP8xx variants */
-	return AXP209_I2C_ADDR;
-}
 #endif
 
 int pmic_bus_init(void)
@@ -88,7 +65,7 @@ int pmic_bus_read(u8 reg, u8 *data)
 	if (IS_ENABLED(CONFIG_SYS_I2C_SUN8I_RSB))
 		return rsb_read(AXP_PMIC_PRI_RUNTIME_ADDR, reg, data);
 
-	return i2c_read(pmic_i2c_address(), reg, 1, data, 1);
+	return i2c_read(CONFIG_AXP_I2C_ADDRESS, reg, 1, data, 1);
 #endif
 }
 
@@ -102,7 +79,7 @@ int pmic_bus_write(u8 reg, u8 data)
 	if (IS_ENABLED(CONFIG_SYS_I2C_SUN8I_RSB))
 		return rsb_write(AXP_PMIC_PRI_RUNTIME_ADDR, reg, data);
 
-	return i2c_write(pmic_i2c_address(), reg, 1, &data, 1);
+	return i2c_write(CONFIG_AXP_I2C_ADDRESS, reg, 1, &data, 1);
 #endif
 }
 
diff --git a/arch/arm/mach-sunxi/rmr_switch.S b/arch/arm/mach-sunxi/rmr_switch.S
index 33e55d49686..422007c985b 100644
--- a/arch/arm/mach-sunxi/rmr_switch.S
+++ b/arch/arm/mach-sunxi/rmr_switch.S
@@ -16,7 +16,9 @@
 @ the machine code must be inserted as verbatim .word statements into the
 @ beginning of the AArch64 U-Boot code.
 @ To get the encoded bytes, use:
-@ ${CROSS_COMPILE}gcc -c -o rmr_switch.o rmr_switch.S
+@ ${CROSS_COMPILE}gcc -c -Iinclude -Iarch/arm/include	\
+@   -D__ASSEMBLY__ -DCONFIG_ARM64			\
+@   -o rmr_switch.o arch/arm/mach-sunxi/rmr_switch.S
 @ ${CROSS_COMPILE}objdump -d rmr_switch.o
 @
 @ The resulting words should be inserted into the U-Boot file at
@@ -29,14 +31,40 @@
 #include <config.h>
 
 .text
+	b	start32			// this is "tst x0, x0" in AArch64
+	.word	0x14000047		// this is "b   reset"  in AArch64
 
-#ifndef CONFIG_SUN50I_GEN_H6
-	ldr	r1, =0x017000a0		@ MMIO mapped RVBAR[0] register
+	.space  0x78			// gap distance set by the common
+					// encoding of the first instruction
+fel_stash_addr:
+	.word	fel_stash - .		// distance to fel_stash buffer
+
+start32:
+	adr	r0, fel_stash_addr	// absolute location of fel_stash_addr
+	ldr	r1, fel_stash_addr	// distance to actual fel_stash
+	add	r0, r0, r1		// real address of fel_stash
+
+	/* save the current state as needed by the BROM for a later return */
+	str	sp, [r0]
+	str	lr, [r0, #4]
+	mrs	lr, CPSR
+	str	lr, [r0, #8]
+	mrc	p15, 0, lr, cr1, cr0, 0		// SCTLR
+	str	lr, [r0, #12]
+	mrc	p15, 0, lr, cr12, cr0, 0	// VBAR
+	str	lr, [r0, #16]
+
+	ldr	r1, =CONFIG_SUNXI_RVBAR_ADDRESS
+	ldr	r0, =SUNXI_SRAMC_BASE
+	ldr	r0, [r0, #36]			// SRAM_VER_REG
+	ands	r0, r0, #0xff
+	ldrne	r1, =CONFIG_SUNXI_RVBAR_ALTERNATIVE
+#ifdef CONFIG_XPL_BUILD
+	ldr	r0, =CONFIG_SPL_TEXT_BASE
 #else
-	ldr	r1, =0x09010040		@ MMIO mapped RVBAR[0] register
+	ldr	r0, =CONFIG_TEXT_BASE
 #endif
-	ldr	r0, =0x57aA7add		@ start address, to be replaced
-	str	r0, [r1]
+	str	r0, [r1]			// store start address in RVBAR
 	dsb	sy
 	isb	sy
 	mrc	15, 0, r0, cr12, cr0, 2	@ read RMR register
diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig
index 78b89729f19..4690dcb3ea6 100644
--- a/arch/arm/mach-tegra/Kconfig
+++ b/arch/arm/mach-tegra/Kconfig
@@ -247,7 +247,7 @@ config CMD_ENTERRCM
 
 config CMD_EBTUPDATE
 	bool "Enable 'ebtupdate' command"
-	depends on TEGRA20 || TEGRA30
+	depends on TEGRA20 || TEGRA30 || TEGRA124
 	select TEGRA_CRYPTO
 	help
 	  Updating u-boot from within u-boot in rather complex or even
diff --git a/arch/arm/mach-tegra/clock.c b/arch/arm/mach-tegra/clock.c
index 157e6c4911a..a375693481e 100644
--- a/arch/arm/mach-tegra/clock.c
+++ b/arch/arm/mach-tegra/clock.c
@@ -358,6 +358,13 @@ unsigned long clock_get_periph_rate(enum periph_id periph_id,
 		break;
 	}
 
+	/*
+	 * PLLD/PLLD2 raw clock rate is never used, instead plld_out0 is used
+	 * that is PLLD/PLLD2 halved.
+	 */
+	if (parent == CLOCK_ID_DISPLAY || parent == CLOCK_ID_DISPLAY2)
+		parent_rate /= 2;
+
 	return get_rate_from_divider(parent_rate, div);
 }
 
@@ -449,6 +456,7 @@ unsigned clock_adjust_periph_pll_div(enum periph_id periph_id,
 		enum clock_id parent, unsigned rate, int *extra_div)
 {
 	unsigned effective_rate;
+	unsigned int parent_rate;
 	int mux_bits, divider_bits, source;
 	int divider;
 	int xdiv = 0;
@@ -457,7 +465,17 @@ unsigned clock_adjust_periph_pll_div(enum periph_id periph_id,
 	source = get_periph_clock_source(periph_id, parent, &mux_bits,
 					 &divider_bits);
 
-	divider = find_best_divider(divider_bits, pll_rate[parent],
+	/*
+	 * Clocks derived from PLLD/D2 are actually sourced from its halved
+	 * output, plld_out0/plld2_out0. No peripheral clocks use the raw
+	 * PLLD/D2 frequency. This halving must be accounted for in derived
+	 * clock calculations.
+	 */
+	parent_rate = pll_rate[parent];
+	if (parent == CLOCK_ID_DISPLAY || parent == CLOCK_ID_DISPLAY2)
+		parent_rate /= 2;
+
+	divider = find_best_divider(divider_bits, parent_rate,
 				    rate, &xdiv);
 	if (extra_div)
 		*extra_div = xdiv;
@@ -685,6 +703,16 @@ int clock_set_rate(enum clock_id clkid, u32 n, u32 m, u32 p, u32 cpcon)
 	else
 		writel(base_reg, &simple_pll->pll_base);
 
+	/*
+	 * Changing clocks was never intended in the U-Boot for Tegra.
+	 * If a clock is changed after clock_init() the parent rate is wrong.
+	 * Usually there is no reason to change peripheral clocks, but Display
+	 * PLLs which needs to generate a precise pixelclock might be adjusted.
+	 * Especially in the case of HDMI display with changing and prior
+	 * unknown resolution.
+	 */
+	pll_rate[clkid] = clock_get_rate(clkid);
+
 	return 0;
 }
 
diff --git a/arch/arm/mach-tegra/tegra124/Kconfig b/arch/arm/mach-tegra/tegra124/Kconfig
index 84c8f86bad0..a62b055f7e6 100644
--- a/arch/arm/mach-tegra/tegra124/Kconfig
+++ b/arch/arm/mach-tegra/tegra124/Kconfig
@@ -30,6 +30,10 @@ config TARGET_CEI_TK1_SOM
 	  the SoC are assigned to which functions, and the PCIEe
 	  configuration.
 
+config TARGET_MOCHA
+	bool "Xiaomi Tegra124 Mi Pad board"
+	select BOARD_LATE_INIT
+
 config TARGET_NYAN_BIG
 	bool "Google/NVIDIA Nyan-big Chromebook"
 	select BOARD_LATE_INIT
@@ -54,5 +58,6 @@ source "board/nvidia/jetson-tk1/Kconfig"
 source "board/nvidia/nyan-big/Kconfig"
 source "board/nvidia/venice2/Kconfig"
 source "board/toradex/apalis-tk1/Kconfig"
+source "board/xiaomi/mocha/Kconfig"
 
 endif
diff --git a/arch/arm/mach-tegra/tegra124/Makefile b/arch/arm/mach-tegra/tegra124/Makefile
index dee790015a3..7b93db89c0f 100644
--- a/arch/arm/mach-tegra/tegra124/Makefile
+++ b/arch/arm/mach-tegra/tegra124/Makefile
@@ -6,6 +6,7 @@
 #
 
 obj-$(CONFIG_XPL_BUILD) += cpu.o
+obj-$(CONFIG_$(XPL_)CMD_EBTUPDATE) += bct.o
 
 obj-y	+= clock.o
 obj-y	+= pmc.o
diff --git a/arch/arm/mach-tegra/tegra124/bct.c b/arch/arm/mach-tegra/tegra124/bct.c
new file mode 100644
index 00000000000..a71aa87fce1
--- /dev/null
+++ b/arch/arm/mach-tegra/tegra124/bct.c
@@ -0,0 +1,91 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright (c) 2022, Ramin <raminterex@yahoo.com>
+ * Copyright (c) 2022, Svyatoslav Ryhel <clamor95@gmail.com>
+ */
+
+#include <command.h>
+#include <log.h>
+#include <vsprintf.h>
+#include <asm/arch-tegra/crypto.h>
+#include "bct.h"
+#include "uboot_aes.h"
+
+/* Device with "sbk burned: false" will expose zero key */
+const u8 nosbk[AES128_KEY_LENGTH] = { 0 };
+
+/*
+ * @param  bct		boot config table start in RAM
+ * @param  ect		bootloader start in RAM
+ * @param  ebt_size	bootloader file size in bytes
+ * Return: 0, or 1 if failed
+ */
+static int bct_patch(u8 *bct, u8 *ebt, u32 ebt_size)
+{
+	struct nvboot_config_table *bct_tbl = NULL;
+	u8 ebt_hash[AES128_KEY_LENGTH] = { 0 };
+	u8 bct_hash[AES128_KEY_LENGTH] = { 0 };
+	u8 sbk[AES128_KEY_LENGTH] = { 0 };
+	u8 *sbct = bct + UBCT_LENGTH;
+	bool encrypted;
+	int ret;
+
+	ebt_size = roundup(ebt_size, EBT_ALIGNMENT);
+
+	memcpy(sbk, (u8 *)(bct + UBCT_LENGTH + SBCT_LENGTH),
+	       NVBOOT_CMAC_AES_HASH_LENGTH * 4);
+
+	encrypted = memcmp(&sbk, &nosbk, AES128_KEY_LENGTH);
+
+	if (encrypted) {
+		ret = decrypt_data_block(sbct, SBCT_LENGTH, sbk);
+		if (ret)
+			return 1;
+
+		ret = encrypt_data_block(ebt, ebt_size, sbk);
+		if (ret)
+			return 1;
+	}
+
+	ret = sign_enc_data_block(ebt, ebt_size, ebt_hash, sbk);
+	if (ret)
+		return 1;
+
+	bct_tbl = (struct nvboot_config_table *)bct;
+
+	memcpy((u8 *)&bct_tbl->bootloader[0].crypto_hash,
+	       ebt_hash, NVBOOT_CMAC_AES_HASH_LENGTH * 4);
+	bct_tbl->bootloader[0].entry_point = CONFIG_SPL_TEXT_BASE;
+	bct_tbl->bootloader[0].load_addr = CONFIG_SPL_TEXT_BASE;
+	bct_tbl->bootloader[0].length = ebt_size;
+
+	if (encrypted) {
+		ret = encrypt_data_block(sbct, SBCT_LENGTH, sbk);
+		if (ret)
+			return 1;
+	}
+
+	ret = sign_enc_data_block(sbct, SBCT_LENGTH, bct_hash, sbk);
+	if (ret)
+		return 1;
+
+	memcpy((u8 *)&bct_tbl->crypto_hash, bct_hash,
+	       NVBOOT_CMAC_AES_HASH_LENGTH * 4);
+
+	return 0;
+}
+
+static int do_ebtupdate(struct cmd_tbl *cmdtp, int flag, int argc,
+			char *const argv[])
+{
+	u32 bct_addr = hextoul(argv[1], NULL);
+	u32 ebt_addr = hextoul(argv[2], NULL);
+	u32 ebt_size = hextoul(argv[3], NULL);
+
+	return bct_patch((u8 *)bct_addr, (u8 *)ebt_addr, ebt_size);
+}
+
+U_BOOT_CMD(ebtupdate,	4,	0,	do_ebtupdate,
+	   "update bootloader on re-crypted Tegra124 devices",
+	   ""
+);
diff --git a/arch/arm/mach-tegra/tegra124/bct.h b/arch/arm/mach-tegra/tegra124/bct.h
new file mode 100644
index 00000000000..eb0f712d595
--- /dev/null
+++ b/arch/arm/mach-tegra/tegra124/bct.h
@@ -0,0 +1,55 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+
+#ifndef _BCT_H_
+#define _BCT_H_
+
+/*
+ * Defines the BCT parametres for T124
+ */
+#define UBCT_LENGTH		0x6b0  /* bytes */
+#define SBCT_LENGTH		0x1950 /* bytes */
+
+#define BCT_HASH		0x10
+#define EBT_ALIGNMENT		0x10
+
+/*
+ * Defines the CMAC-AES-128 hash length in 32 bit words. (128 bits = 4 words)
+ */
+#define NVBOOT_CMAC_AES_HASH_LENGTH		4
+
+/*
+ * Defines the RSA modulus length in 32 bit words used for PKC secure boot.
+ */
+#define NVBOOT_SE_RSA_MODULUS_LENGTH		64
+
+/*
+ * Defines the maximum number of bootloader descriptions in the BCT.
+ */
+#define NVBOOT_MAX_BOOTLOADERS			4
+
+struct nv_bootloader_info {
+	u32 version;
+	u32 start_blk;
+	u32 start_page;
+	u32 length;
+	u32 load_addr;
+	u32 entry_point;
+	u32 attribute;
+
+	/* Specifies the AES-CMAC MAC or RSASSA-PSS signature of the BL. */
+	u32 crypto_hash[NVBOOT_CMAC_AES_HASH_LENGTH];
+	u32 bl_rsa_sig[NVBOOT_SE_RSA_MODULUS_LENGTH];
+};
+
+struct nvboot_config_table {
+	u32 ubct_unused1[196];
+	u32 crypto_hash[NVBOOT_CMAC_AES_HASH_LENGTH];
+	u32 ubct_unused2[228];
+
+	u32 sbct_unused1[1318];
+	u32 bootloader_used;
+	struct nv_bootloader_info bootloader[NVBOOT_MAX_BOOTLOADERS];
+	u32 sbct_unused2;
+};
+
+#endif /* _BCT_H_ */
diff --git a/arch/arm/mach-tegra/tegra30/Kconfig b/arch/arm/mach-tegra/tegra30/Kconfig
index e0f054af8e0..b5099ce67fc 100644
--- a/arch/arm/mach-tegra/tegra30/Kconfig
+++ b/arch/arm/mach-tegra/tegra30/Kconfig
@@ -32,6 +32,10 @@ config TARGET_IDEAPAD_YOGA_11
 	bool "Lenovo Ideapad Yoga 11 board"
 	select BOARD_LATE_INIT
 
+config TARGET_OUYA
+	bool "Ouya Game Console board"
+	select BOARD_LATE_INIT
+
 config TARGET_QC750
 	bool "Wexler QC750 board"
 	select BOARD_LATE_INIT
@@ -64,6 +68,7 @@ source "board/toradex/colibri_t30/Kconfig"
 source "board/htc/endeavoru/Kconfig"
 source "board/asus/grouper/Kconfig"
 source "board/lenovo/ideapad-yoga-11/Kconfig"
+source "board/ouya/ouya/Kconfig"
 source "board/wexler/qc750/Kconfig"
 source "board/microsoft/surface-rt/Kconfig"
 source "board/avionic-design/tec-ng/Kconfig"
diff --git a/arch/m68k/lib/cache.c b/arch/m68k/lib/cache.c
index 370ad40f142..a21fe327944 100644
--- a/arch/m68k/lib/cache.c
+++ b/arch/m68k/lib/cache.c
@@ -8,6 +8,7 @@
 #include <cpu_func.h>
 #include <asm/immap.h>
 #include <asm/cache.h>
+#include <linux/errno.h>
 
 volatile int *cf_icache_status = (int *)ICACHE_STATUS;
 volatile int *cf_dcache_status = (int *)DCACHE_STATUS;
@@ -151,3 +152,8 @@ __weak void flush_dcache_range(unsigned long start, unsigned long stop)
 {
 	/* An empty stub, real implementation should be in platform code */
 }
+
+int __weak pgprot_set_attrs(phys_addr_t addr, size_t size, enum pgprot_attrs perm)
+{
+	return -ENOSYS;
+}
diff --git a/arch/nios2/lib/cache.c b/arch/nios2/lib/cache.c
index 8f543f2a2f2..d7fd9ca8bd4 100644
--- a/arch/nios2/lib/cache.c
+++ b/arch/nios2/lib/cache.c
@@ -8,6 +8,7 @@
 #include <cpu_func.h>
 #include <asm/cache.h>
 #include <asm/global_data.h>
+#include <linux/errno.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -127,3 +128,8 @@ void dcache_disable(void)
 {
 	flush_dcache_all();
 }
+
+int __weak pgprot_set_attrs(phys_addr_t addr, size_t size, enum pgprot_attrs perm)
+{
+	return -ENOSYS;
+}
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h
index 819250f0090..abdaffbe00b 100644
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -133,7 +133,6 @@
 #define CFG_FM_PLAT_CLK_DIV	1
 #define CFG_SYS_FM1_CLK		CFG_FM_PLAT_CLK_DIV
 #define CFG_SYS_FM_MURAM_SIZE	0x30000
-#define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
 #define QE_MURAM_SIZE			0x6000UL
 #define MAX_QE_RISC			1
 #define QE_NUM_OF_SNUM			28
@@ -146,7 +145,6 @@
 #define CFG_SYS_FM1_CLK		0
 #define CFG_QBMAN_CLK_DIV		1
 #define CFG_SYS_FM_MURAM_SIZE	0x30000
-#define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
 #define QE_MURAM_SIZE			0x6000UL
 #define MAX_QE_RISC			1
 #define QE_NUM_OF_SNUM			28
@@ -165,7 +163,6 @@
 #define CFG_SYS_PME_CLK		CFG_PME_PLAT_CLK_DIV
 #define CFG_SYS_FM1_CLK		0
 #define CFG_SYS_FM_MURAM_SIZE	0x28000
-#define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
 
 #elif defined(CONFIG_ARCH_C29X)
 #define CFG_SYS_FSL_SEC_IDX_OFFSET	0x20000
diff --git a/arch/powerpc/lib/cache.c b/arch/powerpc/lib/cache.c
index a9cd7b8d30a..e4d9546039d 100644
--- a/arch/powerpc/lib/cache.c
+++ b/arch/powerpc/lib/cache.c
@@ -8,6 +8,7 @@
 #include <stdio.h>
 #include <asm/cache.h>
 #include <watchdog.h>
+#include <linux/errno.h>
 
 static ulong maybe_watchdog_reset(ulong flushed)
 {
@@ -58,3 +59,8 @@ void invalidate_icache_all(void)
 {
 	puts("No arch specific invalidate_icache_all available!\n");
 }
+
+int __weak pgprot_set_attrs(phys_addr_t addr, size_t size, enum pgprot_attrs perm)
+{
+	return -ENOSYS;
+}
diff --git a/arch/riscv/cpu/k1/Kconfig b/arch/riscv/cpu/k1/Kconfig
index d9cd8dce964..14201df80f2 100644
--- a/arch/riscv/cpu/k1/Kconfig
+++ b/arch/riscv/cpu/k1/Kconfig
@@ -13,6 +13,7 @@ config SPACEMIT_K1
 	imply RISCV_ACLINT if RISCV_MMODE
 	imply SPL_RISCV_ACLINT if SPL_RISCV_MMODE
 	imply CMD_CPU
+	imply DM_RESET
 	imply SPL_CPU
 	imply SPL_OPENSBI
 	imply SPL_LOAD_FIT
diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S
index 3f78932aa9d..7bafdfd390a 100644
--- a/arch/riscv/cpu/start.S
+++ b/arch/riscv/cpu/start.S
@@ -90,8 +90,8 @@ _start:
  * Set stackpointer in internal/ex RAM to call board_init_f
  */
 call_board_init_f:
-#if defined(CONFIG_XPL_BUILD) && defined(CONFIG_SPL_STACK)
-	li	t0, CONFIG_SPL_STACK
+#if CONFIG_IS_ENABLED(HAVE_INIT_STACK)
+	li	t0, CONFIG_VAL(STACK)
 #else
 	li	t0, SYS_INIT_SP_ADDR
 #endif
diff --git a/arch/riscv/dts/binman.dtsi b/arch/riscv/dts/binman.dtsi
index 0405faca574..ceb916b74a7 100644
--- a/arch/riscv/dts/binman.dtsi
+++ b/arch/riscv/dts/binman.dtsi
@@ -82,8 +82,9 @@
 					};
 				};
 
-#ifndef CONFIG_OF_BOARD
+#if !defined(CONFIG_OF_BOARD) || defined(CONFIG_MULTI_DTB_FIT)
 				@fdt-SEQ {
+					fit,operation = "gen-fdt-nodes";
 					description = "NAME";
 					type = "flat_dt";
 					compression = "none";
@@ -92,9 +93,12 @@
 			};
 
 			configurations {
+
+#ifndef CONFIG_MULTI_DTB_FIT
 				default = "conf-1";
+#endif
 
-#ifndef CONFIG_OF_BOARD
+#if !defined(CONFIG_OF_BOARD) || defined(CONFIG_MULTI_DTB_FIT)
 				@conf-SEQ {
 #else
 				conf-1 {
@@ -115,7 +119,7 @@
 #endif
 #endif /* CONFIG_OPTEE */
 
-#ifndef CONFIG_OF_BOARD
+#if !defined(CONFIG_OF_BOARD) || defined(CONFIG_MULTI_DTB_FIT)
 					fdt = "fdt-SEQ";
 #endif
 				};
diff --git a/arch/riscv/dts/cv18xx.dtsi b/arch/riscv/dts/cv18xx.dtsi
index 8a7386b76e6..6fac247e7ac 100644
--- a/arch/riscv/dts/cv18xx.dtsi
+++ b/arch/riscv/dts/cv18xx.dtsi
@@ -46,20 +46,6 @@
 		#clock-cells = <0>;
 	};
 
-	eth_csrclk: eth-csrclk {
-		compatible = "fixed-clock";
-		clock-frequency = <250000000>;
-		clock-output-names = "eth_csrclk";
-		#clock-cells = <0x0>;
-	};
-
-	eth_ptpclk: eth-ptpclk {
-		compatible = "fixed-clock";
-		clock-frequency = <50000000>;
-		clock-output-names = "eth_ptpclk";
-		#clock-cells = <0x0>;
-	};
-
 	soc {
 		compatible = "simple-bus";
 		interrupt-parent = <&plic>;
diff --git a/arch/riscv/dts/k1.dtsi b/arch/riscv/dts/k1.dtsi
index 514be453dba..7c0f1b928e2 100644
--- a/arch/riscv/dts/k1.dtsi
+++ b/arch/riscv/dts/k1.dtsi
@@ -327,7 +327,7 @@
 		ranges;
 
 		uart0: serial@d4017000 {
-			compatible = "spacemit,k1-uart", "snps,dw-apb-uart";
+			compatible = "spacemit,k1-uart", "intel,xscale-uart";
 			reg = <0x0 0xd4017000 0x0 0x100>;
 			interrupts = <42>;
 			clock-frequency = <14857000>;
@@ -337,7 +337,7 @@
 		};
 
 		uart2: serial@d4017100 {
-			compatible = "spacemit,k1-uart", "snps,dw-apb-uart";
+			compatible = "spacemit,k1-uart", "intel,xscale-uart";
 			reg = <0x0 0xd4017100 0x0 0x100>;
 			interrupts = <44>;
 			clock-frequency = <14857000>;
@@ -347,7 +347,7 @@
 		};
 
 		uart3: serial@d4017200 {
-			compatible = "spacemit,k1-uart", "snps,dw-apb-uart";
+			compatible = "spacemit,k1-uart", "intel,xscale-uart";
 			reg = <0x0 0xd4017200 0x0 0x100>;
 			interrupts = <45>;
 			clock-frequency = <14857000>;
@@ -357,7 +357,7 @@
 		};
 
 		uart4: serial@d4017300 {
-			compatible = "spacemit,k1-uart", "snps,dw-apb-uart";
+			compatible = "spacemit,k1-uart", "intel,xscale-uart";
 			reg = <0x0 0xd4017300 0x0 0x100>;
 			interrupts = <46>;
 			clock-frequency = <14857000>;
@@ -367,7 +367,7 @@
 		};
 
 		uart5: serial@d4017400 {
-			compatible = "spacemit,k1-uart", "snps,dw-apb-uart";
+			compatible = "spacemit,k1-uart", "intel,xscale-uart";
 			reg = <0x0 0xd4017400 0x0 0x100>;
 			interrupts = <47>;
 			clock-frequency = <14857000>;
@@ -377,7 +377,7 @@
 		};
 
 		uart6: serial@d4017500 {
-			compatible = "spacemit,k1-uart", "snps,dw-apb-uart";
+			compatible = "spacemit,k1-uart", "intel,xscale-uart";
 			reg = <0x0 0xd4017500 0x0 0x100>;
 			interrupts = <48>;
 			clock-frequency = <14857000>;
@@ -387,7 +387,7 @@
 		};
 
 		uart7: serial@d4017600 {
-			compatible = "spacemit,k1-uart", "snps,dw-apb-uart";
+			compatible = "spacemit,k1-uart", "intel,xscale-uart";
 			reg = <0x0 0xd4017600 0x0 0x100>;
 			interrupts = <49>;
 			clock-frequency = <14857000>;
@@ -397,7 +397,7 @@
 		};
 
 		uart8: serial@d4017700 {
-			compatible = "spacemit,k1-uart", "snps,dw-apb-uart";
+			compatible = "spacemit,k1-uart", "intel,xscale-uart";
 			reg = <0x0 0xd4017700 0x0 0x100>;
 			interrupts = <50>;
 			clock-frequency = <14857000>;
@@ -407,7 +407,7 @@
 		};
 
 		uart9: serial@d4017800 {
-			compatible = "spacemit,k1-uart", "snps,dw-apb-uart";
+			compatible = "spacemit,k1-uart", "intel,xscale-uart";
 			reg = <0x0 0xd4017800 0x0 0x100>;
 			interrupts = <51>;
 			clock-frequency = <14857000>;
@@ -447,7 +447,7 @@
 		};
 
 		sec_uart1: serial@f0612000 {
-			compatible = "spacemit,k1-uart", "snps,dw-apb-uart";
+			compatible = "spacemit,k1-uart", "intel,xscale-uart";
 			reg = <0x0 0xf0612000 0x0 0x100>;
 			interrupts = <43>;
 			clock-frequency = <14857000>;
@@ -455,5 +455,20 @@
 			reg-io-width = <4>;
 			status = "reserved"; /* for TEE usage */
 		};
+
+		reset: reset-controller@d4050000 {
+			compatible = "spacemit,k1-reset";
+			reg = <0x0 0xd4050000 0x0 0x209c>,
+				<0x0 0xd4282800 0x0 0x400>,
+				<0x0 0xd4015000 0x0 0x1000>,
+				<0x0 0xd4090000 0x0 0x1000>,
+				<0x0 0xd4282c00 0x0 0x400>,
+				<0x0 0xd8440000 0x0 0x98>,
+				<0x0 0xc0000000 0x0 0x4280>,
+				<0x0 0xf0610000 0x0 0x20>;
+			reg-names = "mpmu", "apmu", "apbc", "apbs", "ciu", "dciu", "ddrc", "apbc2";
+			#reset-cells = <1>;
+			status = "disabled";
+		};
 	};
 };
\ No newline at end of file
diff --git a/arch/riscv/dts/starfive-visionfive2-binman.dtsi b/arch/riscv/dts/starfive-visionfive2-binman.dtsi
index 4cce001e80d..05787bdb92d 100644
--- a/arch/riscv/dts/starfive-visionfive2-binman.dtsi
+++ b/arch/riscv/dts/starfive-visionfive2-binman.dtsi
@@ -13,82 +13,6 @@
 };
 
 &binman {
-	itb {
-		fit {
-			images {
-				fdt-jh7110-milkv-mars {
-					description = "jh7110-milkv-mars";
-					load = <0x40400000>;
-					compression = "none";
-
-					blob-ext {
-						filename = "dts/upstream/src/riscv/starfive/jh7110-milkv-mars.dtb";
-					};
-				};
-
-				fdt-jh7110-pine64-star64 {
-					description = "jh7110-pine64-star64";
-					load = <0x40400000>;
-					compression = "none";
-
-					blob-ext {
-						filename = "dts/upstream/src/riscv/starfive/jh7110-pine64-star64.dtb";
-					};
-				};
-
-				fdt-jh7110-starfive-visionfive-2-v1.2a {
-					description = "jh7110-starfive-visionfive-2-v1.2a";
-					load = <0x40400000>;
-					compression = "none";
-
-					blob-ext {
-						filename = "dts/upstream/src/riscv/starfive/jh7110-starfive-visionfive-2-v1.2a.dtb";
-					};
-				};
-
-				fdt-jh7110-starfive-visionfive-2-v1.3b {
-					description = "jh7110-starfive-visionfive-2-v1.3b";
-					load = <0x40400000>;
-					compression = "none";
-
-					blob-ext {
-						filename = "dts/upstream/src/riscv/starfive/jh7110-starfive-visionfive-2-v1.3b.dtb";
-					};
-				};
-			};
-
-			configurations {
-				conf-jh7110-milkv-mars {
-					description = "jh7110-milkv-mars";
-					firmware = "opensbi";
-					loadables = "uboot";
-					fdt = "fdt-jh7110-milkv-mars";
-				};
-
-				conf-jh7110-pine64-star64 {
-					description = "jh7110-pine64-star64";
-					firmware = "opensbi";
-					loadables = "uboot";
-					fdt = "fdt-jh7110-pine64-star64";
-				};
-
-				conf-jh7110-starfive-visionfive-2-v1.2a {
-					description = "jh7110-starfive-visionfive-2-v1.2a";
-					firmware = "opensbi";
-					loadables = "uboot";
-					fdt = "fdt-jh7110-starfive-visionfive-2-v1.2a";
-				};
-
-				conf-jh7110-starfive-visionfive-2-v1.3b {
-					description = "jh7110-starfive-visionfive-2-v1.3b";
-					firmware = "opensbi";
-					loadables = "uboot";
-					fdt = "fdt-jh7110-starfive-visionfive-2-v1.3b";
-				};
-			};
-		};
-	};
-
 	spl-img {
 		filename = "spl/u-boot-spl.bin.normal.out";
 
diff --git a/arch/riscv/include/asm/arch-jh7110/gpio.h b/arch/riscv/include/asm/arch-jh7110/gpio.h
index 90aa2f8a9ed..be2a1e0d1c8 100644
--- a/arch/riscv/include/asm/arch-jh7110/gpio.h
+++ b/arch/riscv/include/asm/arch-jh7110/gpio.h
@@ -63,6 +63,11 @@ enum gpio_state {
 			GPIO_DIN_MASK << GPIO_SHIFT(gpi), \
 			((gpio + 2) & GPIO_DIN_MASK) << GPIO_SHIFT(gpi))
 
+#define SYS_IOMUX_DIN_DISABLED(gpi)\
+	clrsetbits_le32(JH7110_SYS_IOMUX + GPIO_DIN + GPIO_OFFSET(gpi), \
+			GPIO_DIN_MASK << GPIO_SHIFT(gpi), \
+			((0x1) & GPIO_DIN_MASK) << GPIO_SHIFT(gpi))
+
 #define SYS_IOMUX_SET_DS(gpio, ds) \
 	clrsetbits_le32(JH7110_SYS_IOMUX + GPIO_CONFIG + gpio * 4, \
 			GPIO_DS_MASK, (ds) << GPIO_DS_SHIFT)
diff --git a/arch/riscv/include/asm/setjmp.h b/arch/riscv/include/asm/setjmp.h
index 72383d43303..08687e0f92b 100644
--- a/arch/riscv/include/asm/setjmp.h
+++ b/arch/riscv/include/asm/setjmp.h
@@ -3,13 +3,9 @@
  * (C) Copyright 2018 Alexander Graf <agraf@suse.de>
  */
 
-#ifndef _SETJMP_H_
-#define _SETJMP_H_	1
+#ifndef _ASM_SETJMP_H_
+#define _ASM_SETJMP_H_	1
 
-/*
- * This really should be opaque, but the EFI implementation wrongly
- * assumes that a 'struct jmp_buf_data' is defined.
- */
 struct jmp_buf_data {
 	/* x2, x8, x9, x18, x19, x20, x21, x22, x23, x24, x25, x26, x27, sp */
 	unsigned long s_regs[12];	/* s0 - s11 */
@@ -17,9 +13,4 @@ struct jmp_buf_data {
 	unsigned long sp;
 };
 
-typedef struct jmp_buf_data jmp_buf[1];
-
-int setjmp(jmp_buf jmp);
-void longjmp(jmp_buf jmp, int ret);
-
-#endif /* _SETJMP_H_ */
+#endif /* _ASM_SETJMP_H_ */
diff --git a/arch/riscv/lib/bootm.c b/arch/riscv/lib/bootm.c
index 76c610bcee0..9544907ab1e 100644
--- a/arch/riscv/lib/bootm.c
+++ b/arch/riscv/lib/bootm.c
@@ -46,10 +46,6 @@ static void announce_and_cleanup(int fake)
 	bootstage_report();
 #endif
 
-#ifdef CONFIG_USB_DEVICE
-	udc_disconnect();
-#endif
-
 	board_quiesce_devices();
 
 	/*
diff --git a/arch/riscv/lib/cache.c b/arch/riscv/lib/cache.c
index 71e4937ab54..31aa30bc7d7 100644
--- a/arch/riscv/lib/cache.c
+++ b/arch/riscv/lib/cache.c
@@ -8,6 +8,7 @@
 #include <dm.h>
 #include <asm/insn-def.h>
 #include <linux/const.h>
+#include <linux/errno.h>
 
 #define CBO_INVAL(base)						\
 	INSN_I(OPCODE_MISC_MEM, FUNC3(2), __RD(0),		\
@@ -151,3 +152,8 @@ __weak void enable_caches(void)
 	if (!zicbom_block_size)
 		log_debug("Zicbom not initialized.\n");
 }
+
+int __weak pgprot_set_attrs(phys_addr_t addr, size_t size, enum pgprot_attrs perm)
+{
+	return -ENOSYS;
+}
diff --git a/arch/sandbox/Kconfig b/arch/sandbox/Kconfig
index 4c169034d9a..d61a327f151 100644
--- a/arch/sandbox/Kconfig
+++ b/arch/sandbox/Kconfig
@@ -77,7 +77,7 @@ config SANDBOX_BITS_PER_LONG
 
 config SYS_FDT_LOAD_ADDR
 	hex "Address at which to load devicetree"
-	default 0x100
+	default 0x1000
 	help
 	  With sandbox the devicetree is loaded into the emulated RAM. This sets
 	  the address that is used. There must be enough space at this address
diff --git a/arch/sandbox/cpu/cpu.c b/arch/sandbox/cpu/cpu.c
index 6407193c5f1..6db8739e66b 100644
--- a/arch/sandbox/cpu/cpu.c
+++ b/arch/sandbox/cpu/cpu.c
@@ -10,10 +10,10 @@
 #include <errno.h>
 #include <log.h>
 #include <os.h>
+#include <setjmp.h>
 #include <asm/global_data.h>
 #include <asm/io.h>
 #include <asm/malloc.h>
-#include <asm/setjmp.h>
 #include <asm/state.h>
 #include <dm/ofnode.h>
 #include <linux/delay.h>
diff --git a/arch/sandbox/dts/test.dts b/arch/sandbox/dts/test.dts
index b8f3012873e..52e9ddbf50f 100644
--- a/arch/sandbox/dts/test.dts
+++ b/arch/sandbox/dts/test.dts
@@ -1047,6 +1047,31 @@
 		};
 	};
 
+	lvds-encoder {
+		compatible = "lvds-encoder";
+
+		ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@0 {
+				reg = <0>;
+
+				bridge_input: endpoint {
+					/* link to output */
+				};
+			};
+
+			port@1 {
+				reg = <1>;
+
+				bridge_output: endpoint {
+					remote-endpoint = <&panel_input>;
+				};
+			};
+		};
+	};
+
 	wdt-gpio-toggle {
 		gpios = <&gpio_a 8 0>;
 		compatible = "linux,wdt-gpio";
@@ -1402,6 +1427,27 @@
 	panel {
 		compatible = "simple-panel";
 		backlight = <&backlight 0 100>;
+
+		display-timings {
+			timing@0 {
+				/* 1280x800@60Hz */
+				clock-frequency = <68000000>;
+				hactive = <1280>;
+				hfront-porch = <48>;
+				hback-porch = <18>;
+				hsync-len = <30>;
+				vactive = <800>;
+				vfront-porch = <3>;
+				vback-porch = <12>;
+				vsync-len = <5>;
+			};
+		};
+
+		port {
+			panel_input: endpoint {
+				remote-endpoint = <&bridge_output>;
+			};
+		};
 	};
 
 	scsi {
@@ -2048,6 +2094,61 @@
 			sandbox,err-step-size = <512>;
 		};
 	};
+
+	graph1 {
+		ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@0 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				reg = <0>;
+
+				endpoint@0 {
+					reg = <0>;
+				};
+
+				endpoint@1 {
+					reg = <1>;
+				};
+			};
+
+			port@1 {
+				reg = <1>;
+
+				endpoint {
+					test-property-0;
+				};
+			};
+
+			port@2 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				reg = <2>;
+
+				graph2_link: endpoint@0 {
+					reg = <0>;
+					test-property-1;
+					remote-endpoint = <&graph1_link>;
+				};
+
+				endpoint@1 {
+					reg = <1>;
+				};
+			};
+		};
+	};
+
+	graph2 {
+		port {
+			graph1_link: endpoint {
+				remote-endpoint = <&graph2_link>;
+			};
+		};
+	};
 };
 
 #include "sandbox_pmic.dtsi"
diff --git a/arch/sandbox/include/asm/serial.h b/arch/sandbox/include/asm/serial.h
index 16589a1b219..41506341816 100644
--- a/arch/sandbox/include/asm/serial.h
+++ b/arch/sandbox/include/asm/serial.h
@@ -44,7 +44,7 @@ void sandbox_serial_endisable(bool enabled);
  * @buf: holds input characters available to be read by this driver
  */
 struct sandbox_serial_priv {
-	struct membuff buf;
+	struct membuf buf;
 	char serial_buf[16];
 	bool start_of_line;
 };
diff --git a/arch/sandbox/include/asm/setjmp.h b/arch/sandbox/include/asm/setjmp.h
index 001c7ea322d..3413c747783 100644
--- a/arch/sandbox/include/asm/setjmp.h
+++ b/arch/sandbox/include/asm/setjmp.h
@@ -4,8 +4,8 @@
  * Written by Simon Glass <sjg@chromium.org>
  */
 
-#ifndef _SETJMP_H_
-#define _SETJMP_H_
+#ifndef _ASM_SETJMP_H_
+#define _ASM_SETJMP_H_
 
 struct jmp_buf_data {
 	/*
@@ -19,17 +19,7 @@ struct jmp_buf_data {
 	 * We don't need to worry about 16-byte alignment, since this does not
 	 * run on Windows.
 	 */
-	ulong data[128];
+	unsigned long data[128];
 };
 
-typedef struct jmp_buf_data jmp_buf[1];
-
-/*
- * We have to directly link with the system versions of
- * setjmp/longjmp, because setjmp must not return as otherwise
- * the stack may become invalid.
- */
-int setjmp(jmp_buf jmp);
-__noreturn void longjmp(jmp_buf jmp, int ret);
-
-#endif /* _SETJMP_H_ */
+#endif /* _ASM_SETJMP_H_ */
diff --git a/arch/sh/cpu/sh4/cache.c b/arch/sh/cpu/sh4/cache.c
index 99acc599965..56161ee72e4 100644
--- a/arch/sh/cpu/sh4/cache.c
+++ b/arch/sh/cpu/sh4/cache.c
@@ -11,6 +11,7 @@
 #include <asm/io.h>
 #include <asm/processor.h>
 #include <asm/system.h>
+#include <linux/errno.h>
 
 #define CACHE_VALID       1
 #define CACHE_UPDATED     2
@@ -126,3 +127,8 @@ int dcache_status(void)
 {
 	return 0;
 }
+
+int __weak pgprot_set_attrs(phys_addr_t addr, size_t size, enum pgprot_attrs perm)
+{
+	return -ENOSYS;
+}
diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index 006a59d6fa6..dc9483ad723 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -30,7 +30,7 @@ config X86_RUN_32BIT
 	  arch_phys_memset() can be used for basic access to other memory.
 
 config X86_RUN_64BIT
-	bool "64-bit"
+	bool "32-bit SPL followed by 64-bit U-Boot"
 	select X86_64
 	select SPL if !EFI_APP
 	select SPL_SEPARATE_BSS if !EFI_APP
@@ -40,6 +40,14 @@ config X86_RUN_64BIT
 	  runs through the 16-bit and 32-bit init, then switches to 64-bit
 	  mode and jumps to U-Boot proper.
 
+config X86_RUN_64BIT_NO_SPL
+	bool "64-bit"
+	select X86_64
+	help
+          Build U-Boot as a 64-bit binary without SPL. As U-Boot enters
+          in 64-bit mode, the assumption is that the silicon is fully
+          initialized (MP, page tables, etc.).
+
 endchoice
 
 config X86_64
diff --git a/arch/x86/cpu/coreboot/Kconfig b/arch/x86/cpu/coreboot/Kconfig
index 085302c0482..66f25533b97 100644
--- a/arch/x86/cpu/coreboot/Kconfig
+++ b/arch/x86/cpu/coreboot/Kconfig
@@ -26,7 +26,7 @@ config SYS_COREBOOT
 	imply CBMEM_CONSOLE
 	imply X86_TSC_READ_BASE
 	imply USE_PREBOOT
-	select BINMAN if X86_64
+	select BINMAN if X86_RUN_64BIT
 	select SYSINFO
 	imply SYSINFO_EXTRA
 
diff --git a/arch/x86/cpu/coreboot/coreboot.c b/arch/x86/cpu/coreboot/coreboot.c
index fa7430b436f..d0719d1a405 100644
--- a/arch/x86/cpu/coreboot/coreboot.c
+++ b/arch/x86/cpu/coreboot/coreboot.c
@@ -22,7 +22,7 @@ int arch_cpu_init(void)
 {
 	int ret;
 
-	ret = IS_ENABLED(CONFIG_X86_RUN_64BIT) ? x86_cpu_reinit_f() :
+	ret = IS_ENABLED(CONFIG_X86_64) ? x86_cpu_reinit_f() :
 		x86_cpu_init_f();
 	if (ret)
 		return ret;
diff --git a/arch/x86/cpu/cpu.c b/arch/x86/cpu/cpu.c
index a8b21406ac0..c373b14df30 100644
--- a/arch/x86/cpu/cpu.c
+++ b/arch/x86/cpu/cpu.c
@@ -364,3 +364,27 @@ long locate_coreboot_table(void)
 
 	return addr;
 }
+
+static bool has_cpuid(void)
+{
+	return flag_is_changeable_p(X86_EFLAGS_ID);
+}
+
+static uint cpu_cpuid_extended_level(void)
+{
+	return cpuid_eax(0x80000000);
+}
+
+int cpu_phys_address_size(void)
+{
+	if (!has_cpuid())
+		return 32;
+
+	if (cpu_cpuid_extended_level() >= 0x80000008)
+		return cpuid_eax(0x80000008) & 0xff;
+
+	if (cpuid_edx(1) & (CPUID_FEATURE_PAE | CPUID_FEATURE_PSE36))
+		return 36;
+
+	return 32;
+}
diff --git a/arch/x86/cpu/i386/call64.S b/arch/x86/cpu/i386/call64.S
index d81bcc6f8f4..a9d3f16a6ad 100644
--- a/arch/x86/cpu/i386/call64.S
+++ b/arch/x86/cpu/i386/call64.S
@@ -7,10 +7,11 @@
  */
 
 #include <asm/msr-index.h>
+#include <asm/processor.h>
 #include <asm/processor-flags.h>
 
 .code32
-.section .text_call64
+.section .text_call64, "ax"
 .globl cpu_call64
 cpu_call64:
 	/*
@@ -21,17 +22,19 @@ cpu_call64:
 	 * ecx - target
 	 */
 	cli
+	pushl	$0		/* top 64-bits of target */
 	push	%ecx		/* arg2 = target */
 	push	%edx		/* arg1 = setup_base */
 	mov	%eax, %ebx
 
-	/* Load new GDT with the 64bit segments using 32bit descriptor */
-	leal	gdt, %eax
-	movl	%eax, gdt+2
-	lgdt	gdt
+	# disable paging
+	movl	%cr0, %eax
+	andl	$~X86_CR0_PG, %eax
+	movl	%eax, %cr0
 
 	/* Enable PAE mode */
-	movl	$(X86_CR4_PAE), %eax
+	movl	%cr4, %eax
+	orl	$X86_CR4_PAE, %eax
 	movl	%eax, %cr4
 
 	/* Enable the boot page tables */
@@ -44,12 +47,6 @@ cpu_call64:
 	btsl	$_EFER_LME, %eax
 	wrmsr
 
-	/* After gdt is loaded */
-	xorl	%eax, %eax
-	lldt	%ax
-	movl    $0x20, %eax
-	ltr	%ax
-
 	/*
 	 * Setup for the jump to 64bit mode
 	 *
@@ -62,22 +59,18 @@ cpu_call64:
 	 */
 	pop	%esi			/* setup_base */
 
-	pushl	$0x10
-	leal	lret_target, %eax
-	pushl	%eax
-
 	/* Enter paged protected Mode, activating Long Mode */
-	movl	$(X86_CR0_PG | X86_CR0_PE), %eax
+	movl	%cr0, %eax
+	orl	$X86_CR0_PG, %eax
 	movl	%eax, %cr0
 
 	/* Jump from 32bit compatibility mode into 64bit mode. */
-	lret
+	ljmp	$(X86_GDT_ENTRY_64BIT_CS * X86_GDT_ENTRY_SIZE), $lret_target
 
-code64:
+.code64
 lret_target:
-	pop	%eax			/* target */
-	mov	%eax, %eax		/* Clear bits 63:32 */
-	jmp	*%eax			/* Jump to the 64-bit target */
+	pop	%rax			/* target */
+	jmp	*%rax			/* Jump to the 64-bit target */
 
 .globl call64_stub_size
 call64_stub_size:
diff --git a/arch/x86/cpu/i386/cpu.c b/arch/x86/cpu/i386/cpu.c
index a51a24498a7..ee6dbeb5c48 100644
--- a/arch/x86/cpu/i386/cpu.c
+++ b/arch/x86/cpu/i386/cpu.c
@@ -35,10 +35,6 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#define CPUID_FEATURE_PAE	BIT(6)
-#define CPUID_FEATURE_PSE36	BIT(17)
-#define CPUID_FEAURE_HTT	BIT(28)
-
 /*
  * Constructor for a conventional segment GDT (or LDT) entry
  * This is a macro so it can be used in initialisers
@@ -160,6 +156,9 @@ void arch_setup_gd(gd_t *new_gd)
 
 	gdt_addr[X86_GDT_ENTRY_16BIT_FLAT_CS] = GDT_ENTRY(0x809b, 0, 0xfffff);
 	gdt_addr[X86_GDT_ENTRY_16BIT_FLAT_DS] = GDT_ENTRY(0x8093, 0, 0xfffff);
+	gdt_addr[X86_GDT_ENTRY_64BIT_CS] = GDT_ENTRY(0xaf9b, 0, 0xfffff);
+	gdt_addr[X86_GDT_ENTRY_64BIT_TS1] = GDT_ENTRY(0x8980, 0, 0xfffff);
+	gdt_addr[X86_GDT_ENTRY_64BIT_TS2] = 0;
 
 	load_gdt(gdt_addr, X86_GDT_NUM_ENTRIES);
 	load_ds(X86_GDT_ENTRY_32BIT_DS);
@@ -409,25 +408,6 @@ static void setup_identity(void)
 	}
 }
 
-static uint cpu_cpuid_extended_level(void)
-{
-	return cpuid_eax(0x80000000);
-}
-
-int cpu_phys_address_size(void)
-{
-	if (!has_cpuid())
-		return 32;
-
-	if (cpu_cpuid_extended_level() >= 0x80000008)
-		return cpuid_eax(0x80000008) & 0xff;
-
-	if (cpuid_edx(1) & (CPUID_FEATURE_PAE | CPUID_FEATURE_PSE36))
-		return 36;
-
-	return 32;
-}
-
 static void setup_mtrr(void)
 {
 	u64 mtrr_cap;
@@ -589,6 +569,13 @@ int cpu_has_64bit(void)
 #define PAGETABLE_BASE		0x80000
 #define PAGETABLE_SIZE		(6 * 4096)
 
+#define _PRES BIT(0)	/* present */
+#define _RW   BIT(1)	/* write allowed */
+#define _US   BIT(2)	/* user-access allowed */
+#define _A    BIT(5)	/* has been accessed */
+#define _DT   BIT(6)	/* has been written to */
+#define _PS   BIT(7)	/* indicates 2MB page size here */
+
 /**
  * build_pagetable() - build a flat 4GiB page table structure for 64-bti mode
  *
@@ -601,15 +588,17 @@ static void build_pagetable(uint32_t *pgtable)
 	memset(pgtable, '\0', PAGETABLE_SIZE);
 
 	/* Level 4 needs a single entry */
-	pgtable[0] = (ulong)&pgtable[1024] + 7;
+	pgtable[0] = (ulong)&pgtable[1024] + _PRES + _RW + _US + _A;
 
 	/* Level 3 has one 64-bit entry for each GiB of memory */
 	for (i = 0; i < 4; i++)
-		pgtable[1024 + i * 2] = (ulong)&pgtable[2048] + 0x1000 * i + 7;
+		pgtable[1024 + i * 2] = (ulong)&pgtable[2048] + 0x1000 * i +
+			_PRES + _RW + _US + _A;
 
 	/* Level 2 has 2048 64-bit entries, each repesenting 2MiB */
 	for (i = 0; i < 2048; i++)
-		pgtable[2048 + i * 2] = 0x183 + (i << 21UL);
+		pgtable[2048 + i * 2] = _PRES + _RW + _US + _PS + _A +  _DT +
+					 (i << 21UL);
 }
 
 int cpu_jump_to_64bit(ulong setup_base, ulong target)
diff --git a/arch/x86/cpu/mtrr.c b/arch/x86/cpu/mtrr.c
index 07ea89162de..7a0f00b9b8f 100644
--- a/arch/x86/cpu/mtrr.c
+++ b/arch/x86/cpu/mtrr.c
@@ -1,6 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
  * (C) Copyright 2014 Google, Inc
+ * Portions added from coreboot
  *
  * Memory Type Range Regsters - these are used to tell the CPU whether
  * memory is cacheable and if so the cache write mode to use.
@@ -16,6 +17,7 @@
  * since the MTRR registers are sometimes in flux.
  */
 
+#include <cpu.h>
 #include <cpu_func.h>
 #include <log.h>
 #include <sort.h>
@@ -39,6 +41,27 @@ static const char *const mtrr_type_name[MTRR_TYPE_COUNT] = {
 	"Back",
 };
 
+u64 mtrr_to_size(u64 mask)
+{
+	u64 size;
+
+	size = ~mask & ((1ULL << cpu_phys_address_size()) - 1);
+	size |= (1 << 12) - 1;
+	size += 1;
+
+	return size;
+}
+
+u64 mtrr_to_mask(u64 size)
+{
+	u64 mask;
+
+	mask = ~(size - 1);
+	mask &= (1ull << cpu_phys_address_size()) - 1;
+
+	return mask;
+}
+
 /* Prepare to adjust MTRRs */
 void mtrr_open(struct mtrr_state *state, bool do_caches)
 {
@@ -68,11 +91,9 @@ void mtrr_close(struct mtrr_state *state, bool do_caches)
 
 static void set_var_mtrr(uint reg, uint type, uint64_t start, uint64_t size)
 {
-	u64 mask;
+	u64 mask = mtrr_to_mask(size);
 
 	wrmsrl(MTRR_PHYS_BASE_MSR(reg), start | type);
-	mask = ~(size - 1);
-	mask &= (1ULL << CONFIG_CPU_ADDR_BITS) - 1;
 	wrmsrl(MTRR_PHYS_MASK_MSR(reg), mask | MTRR_PHYS_MASK_VALID);
 }
 
@@ -184,30 +205,80 @@ int mtrr_commit(bool do_caches)
 	return 0;
 }
 
-int mtrr_add_request(int type, uint64_t start, uint64_t size)
+/* fms: find most significant bit set (from Linux)  */
+static inline uint fms(uint val)
+{
+	uint ret;
+
+	__asm__("bsrl %1,%0\n\t"
+		"jnz 1f\n\t"
+		"movl $0,%0\n"
+		"1:" : "=r" (ret) : "mr" (val));
+
+	return ret;
+}
+
+/*
+ * fms64: find most significant bit set in a 64-bit word
+ * As samples, fms64(0x0) = 0; fms64(0x4400) = 14;
+ * fms64(0x40400000000) = 42.
+ */
+static uint fms64(uint64_t val)
+{
+	u32 hi = (u32)(val >> 32);
+
+	if (!hi)
+		return fms((u32)val);
+
+	return fms(hi) + 32;
+}
+
+int mtrr_add_request(int type, u64 base, uint64_t size)
 {
 	struct mtrr_request *req;
-	uint64_t mask;
+	u64 mask;
 
 	debug("%s: count=%d\n", __func__, gd->arch.mtrr_req_count);
 	if (!gd->arch.has_mtrr)
 		return -ENOSYS;
 
-	if (!is_power_of_2(size))
-		return -EINVAL;
-
-	if (gd->arch.mtrr_req_count == MAX_MTRR_REQUESTS)
-		return -ENOSPC;
-	req = &gd->arch.mtrr_req[gd->arch.mtrr_req_count++];
-	req->type = type;
-	req->start = start;
-	req->size = size;
-	debug("%d: type=%d, %08llx  %08llx\n", gd->arch.mtrr_req_count - 1,
-	      req->type, req->start, req->size);
-	mask = ~(req->size - 1);
-	mask &= (1ULL << CONFIG_CPU_ADDR_BITS) - 1;
-	mask |= MTRR_PHYS_MASK_VALID;
-	debug("   %016llx %016llx\n", req->start | req->type, mask);
+	while (size) {
+		uint addr_lsb;
+		uint size_msb;
+		u64 mtrr_size;
+
+		addr_lsb = fls64(base);
+		size_msb = fms64(size);
+
+		/*
+		 * All MTRR entries need to have their base aligned to the
+		 * mask size. The maximum size is calculated by a function of
+		 * the min base bit set and maximum size bit set.
+		 * Algorithm is from coreboot
+		 */
+		if (!addr_lsb || addr_lsb > size_msb)
+			mtrr_size = 1ull << size_msb;
+		else
+			mtrr_size = 1ull << addr_lsb;
+		log_debug("addr_lsb %x size_msb %x mtrr_size %llx\n",
+			  addr_lsb, size_msb, mtrr_size);
+
+		if (gd->arch.mtrr_req_count == MAX_MTRR_REQUESTS)
+			return -ENOSPC;
+		req = &gd->arch.mtrr_req[gd->arch.mtrr_req_count++];
+		req->type = type;
+		req->start = base;
+		req->size = mtrr_size;
+		log_debug("%d: type=%d, %08llx  %08llx ",
+			  gd->arch.mtrr_req_count - 1, req->type, req->start,
+			  req->size);
+		mask = mtrr_to_mask(req->size);
+		mask |= MTRR_PHYS_MASK_VALID;
+		log_debug("   %016llx %016llx\n", req->start | req->type, mask);
+
+		size -= mtrr_size;
+		base += mtrr_size;
+	}
 
 	return 0;
 }
@@ -360,9 +431,7 @@ int mtrr_list(int reg_count, int cpu_select)
 
 		base = info.mtrr[i].base;
 		mask = info.mtrr[i].mask;
-		size = ~mask & ((1ULL << CONFIG_CPU_ADDR_BITS) - 1);
-		size |= (1 << 12) - 1;
-		size += 1;
+		size = mtrr_to_size(mask);
 		valid = mask & MTRR_PHYS_MASK_VALID;
 		type = mtrr_type_name[base & MTRR_BASE_TYPE_MASK];
 		printf("%d   %-5s %-12s %016llx %016llx %016llx\n", i,
diff --git a/arch/x86/cpu/qemu/dram.c b/arch/x86/cpu/qemu/dram.c
index 62a301c0fd3..ba3638e6acc 100644
--- a/arch/x86/cpu/qemu/dram.c
+++ b/arch/x86/cpu/qemu/dram.c
@@ -4,7 +4,9 @@
  */
 
 #include <init.h>
+#include <spl.h>
 #include <asm/global_data.h>
+#include <asm/mtrr.h>
 #include <asm/post.h>
 #include <asm/arch/qemu.h>
 #include <linux/sizes.h>
@@ -44,6 +46,22 @@ int dram_init(void)
 	gd->ram_size += qemu_get_high_memory_size();
 	post_code(POST_DRAM);
 
+	if (xpl_phase() == PHASE_BOARD_F) {
+		u64 total = gd->ram_size;
+		int ret;
+
+		if (total > SZ_2G + SZ_1G)
+			total += SZ_1G;
+		ret = mtrr_add_request(MTRR_TYPE_WRBACK, 0, total);
+		if (ret != -ENOSYS) {
+			if (ret)
+				return log_msg_ret("mta", ret);
+			ret = mtrr_commit(false);
+			if (ret)
+				return log_msg_ret("mtc", ret);
+		}
+	}
+
 	return 0;
 }
 
diff --git a/arch/x86/cpu/qemu/e820.c b/arch/x86/cpu/qemu/e820.c
index 17a04f86479..078d1d86b02 100644
--- a/arch/x86/cpu/qemu/e820.c
+++ b/arch/x86/cpu/qemu/e820.c
@@ -6,6 +6,7 @@
  * (C) Copyright 2019 Bin Meng <bmeng.cn@gmail.com>
  */
 
+#include <bloblist.h>
 #include <env_internal.h>
 #include <malloc.h>
 #include <asm/e820.h>
@@ -19,51 +20,34 @@ unsigned int install_e820_map(unsigned int max_entries,
 			      struct e820_entry *entries)
 {
 	u64 high_mem_size;
-	int n = 0;
+	struct e820_ctx ctx;
 
-	entries[n].addr = 0;
-	entries[n].size = ISA_START_ADDRESS;
-	entries[n].type = E820_RAM;
-	n++;
+	e820_init(&ctx, entries, max_entries);
 
-	entries[n].addr = ISA_START_ADDRESS;
-	entries[n].size = ISA_END_ADDRESS - ISA_START_ADDRESS;
-	entries[n].type = E820_RESERVED;
-	n++;
+	e820_next(&ctx, E820_RAM, ISA_START_ADDRESS);
+	e820_next(&ctx, E820_RESERVED, ISA_END_ADDRESS);
 
 	/*
-	 * since we use memalign(malloc) to allocate high memory for
-	 * storing ACPI tables, we need to reserve them in e820 tables,
-	 * otherwise kernel will reclaim them and data will be corrupted
+	 * if we use bloblist to allocate high memory for storing ACPI tables,
+	 * we need to reserve that region in e820 tables, otherwise the kernel
+	 * will reclaim them and data will be corrupted. The ACPI tables may not
+	 * have been written yet, so use the whole bloblist size
 	 */
-	entries[n].addr = ISA_END_ADDRESS;
-	entries[n].size = gd->relocaddr - TOTAL_MALLOC_LEN - ISA_END_ADDRESS;
-	entries[n].type = E820_RAM;
-	n++;
-
-	/* for simplicity, reserve entire malloc space */
-	entries[n].addr = gd->relocaddr - TOTAL_MALLOC_LEN;
-	entries[n].size = TOTAL_MALLOC_LEN;
-	entries[n].type = E820_RESERVED;
-	n++;
-
-	entries[n].addr = gd->relocaddr;
-	entries[n].size = qemu_get_low_memory_size() - gd->relocaddr;
-	entries[n].type = E820_RESERVED;
-	n++;
-
-	entries[n].addr = CONFIG_PCIE_ECAM_BASE;
-	entries[n].size = CONFIG_PCIE_ECAM_SIZE;
-	entries[n].type = E820_RESERVED;
-	n++;
+	if (IS_ENABLED(CONFIG_BLOBLIST_TABLES)) {
+		e820_to_addr(&ctx, E820_RAM, (ulong)gd->bloblist);
+		e820_next(&ctx, E820_ACPI, bloblist_get_total_size());
+	} else {
+		/* If using memalign() reserve that whole region instead */
+		e820_to_addr(&ctx, E820_RAM, gd->relocaddr - TOTAL_MALLOC_LEN);
+		e820_next(&ctx, E820_ACPI, TOTAL_MALLOC_LEN);
+	}
+	e820_to_addr(&ctx, E820_RAM, qemu_get_low_memory_size());
+	e820_add(&ctx, E820_RESERVED, CONFIG_PCIE_ECAM_BASE,
+		 CONFIG_PCIE_ECAM_SIZE);
 
 	high_mem_size = qemu_get_high_memory_size();
-	if (high_mem_size) {
-		entries[n].addr = SZ_4G;
-		entries[n].size = high_mem_size;
-		entries[n].type = E820_RAM;
-		n++;
-	}
+	if (high_mem_size)
+		e820_add(&ctx, E820_RAM, SZ_4G, high_mem_size);
 
-	return n;
+	return e820_finish(&ctx);
 }
diff --git a/arch/x86/cpu/qemu/qemu.c b/arch/x86/cpu/qemu/qemu.c
index 563f63e2bc8..e846ccd44aa 100644
--- a/arch/x86/cpu/qemu/qemu.c
+++ b/arch/x86/cpu/qemu/qemu.c
@@ -15,14 +15,21 @@
 #include <asm/arch/qemu.h>
 #include <asm/u-boot-x86.h>
 
-static bool i440fx;
-
 #if CONFIG_IS_ENABLED(QFW_PIO)
 U_BOOT_DRVINFO(x86_qfw_pio) = {
 	.name = "qfw_pio",
 };
 #endif
 
+static bool is_i440fx(void)
+{
+	u16 device;
+
+	pci_read_config16(PCI_BDF(0, 0, 0), PCI_DEVICE_ID, &device);
+
+	return device == PCI_DEVICE_ID_INTEL_82441;
+}
+
 static void enable_pm_piix(void)
 {
 	u8 en;
@@ -50,16 +57,17 @@ static void enable_pm_ich9(void)
 
 void qemu_chipset_init(void)
 {
-	u16 device, xbcs;
+	bool i440fx;
+	u16 xbcs;
 	int pam, i;
 
+	i440fx = is_i440fx();
+
 	/*
 	 * i440FX and Q35 chipset have different PAM register offset, but with
 	 * the same bitfield layout. Here we determine the offset based on its
 	 * PCI device ID.
 	 */
-	pci_read_config16(PCI_BDF(0, 0, 0), PCI_DEVICE_ID, &device);
-	i440fx = (device == PCI_DEVICE_ID_INTEL_82441);
 	pam = i440fx ? I440FX_PAM : Q35_PAM;
 
 	/*
@@ -123,7 +131,7 @@ int mp_determine_pci_dstirq(int bus, int dev, int func, int pirq)
 {
 	u8 irq;
 
-	if (i440fx) {
+	if (is_i440fx()) {
 		/*
 		 * Not like most x86 platforms, the PIRQ[A-D] on PIIX3 are not
 		 * connected to I/O APIC INTPIN#16-19. Instead they are routed
diff --git a/arch/x86/cpu/start.S b/arch/x86/cpu/start.S
index 0ef27cc5a00..385a691265e 100644
--- a/arch/x86/cpu/start.S
+++ b/arch/x86/cpu/start.S
@@ -254,7 +254,7 @@ multiboot_header:
 	 * GDT is setup in a safe location in RAM
 	 */
 gdt_ptr2:
-	.word	0x1f		/* limit (31 bytes = 4 GDT entries - 1) */
+	.word	gdt2_end - gdt_ptr2 - 1
 	.long	gdt_rom2	/* base */
 
 	/* Some CPUs are picky about GDT alignment... */
@@ -313,4 +313,6 @@ gdt_rom2:
 	.byte	0x93		/* access */
 	.byte	0xcf		/* flags + limit_high */
 	.byte	0x00		/* base_high */
+gdt2_end:
+
 #endif
diff --git a/arch/x86/cpu/start16.S b/arch/x86/cpu/start16.S
index 865a49731e5..8d9acb193e0 100644
--- a/arch/x86/cpu/start16.S
+++ b/arch/x86/cpu/start16.S
@@ -61,7 +61,7 @@ idt_ptr:
 	 * GDT is setup in a safe location in RAM
 	 */
 gdt_ptr:
-	.word	0x1f		/* limit (31 bytes = 4 GDT entries - 1) */
+	.word	gdt_end - gdt_rom - 1
 	.long	BOOT_SEG + gdt_rom	/* base */
 
 	/* Some CPUs are picky about GDT alignment... */
@@ -120,3 +120,4 @@ gdt_rom:
 	.byte	0x93		/* access */
 	.byte	0xcf		/* flags + limit_high */
 	.byte	0x00		/* base_high */
+gdt_end:
diff --git a/arch/x86/cpu/x86_64/cpu.c b/arch/x86/cpu/x86_64/cpu.c
index 71bc07f872a..25ae92c702f 100644
--- a/arch/x86/cpu/x86_64/cpu.c
+++ b/arch/x86/cpu/x86_64/cpu.c
@@ -59,11 +59,6 @@ int x86_cpu_reinit_f(void)
 	return 0;
 }
 
-int cpu_phys_address_size(void)
-{
-	return CONFIG_CPU_ADDR_BITS;
-}
-
 int x86_cpu_init_f(void)
 {
 	return 0;
diff --git a/arch/x86/include/asm/bootparam.h b/arch/x86/include/asm/bootparam.h
index ac4865300f1..657d920b14f 100644
--- a/arch/x86/include/asm/bootparam.h
+++ b/arch/x86/include/asm/bootparam.h
@@ -122,6 +122,14 @@ struct efi_info {
 	__u32 efi_memmap_hi;
 };
 
+/* Gleaned from OFW's set-parameters in cpu/x86/pc/linux.fth */
+struct olpc_ofw_header {
+	__u32 ofw_magic;	/* OFW signature */
+	__u32 ofw_version;
+	__u32 cif_handler;	/* callback into OFW */
+	__u32 irq_desc_table;
+} __attribute__((packed));
+
 /* The so-called "zeropage" */
 struct boot_params {
 	struct screen_info screen_info;			/* 0x000 */
@@ -134,7 +142,12 @@ struct boot_params {
 	__u8  hd0_info[16];	/* obsolete! */		/* 0x080 */
 	__u8  hd1_info[16];	/* obsolete! */		/* 0x090 */
 	struct sys_desc_table sys_desc_table;		/* 0x0a0 */
-	__u8  _pad4[144];				/* 0x0b0 */
+	struct olpc_ofw_header olpc_ofw_header;		/* 0x0b0 */
+	__u32 ext_ramdisk_image;			/* 0x0c0 */
+	__u32 ext_ramdisk_size;				/* 0x0c4 */
+	__u32 ext_cmd_line_ptr;				/* 0x0c8 */
+	__u8  _pad4[112];				/* 0x0cc */
+	__u32 cc_blob_address;				/* 0x13c */
 	struct edid_info edid_info;			/* 0x140 */
 	struct efi_info efi_info;			/* 0x1c0 */
 	__u32 alt_mem_k;				/* 0x1e0 */
diff --git a/arch/x86/include/asm/cpu.h b/arch/x86/include/asm/cpu.h
index fd389d4024c..5d24c17f8a3 100644
--- a/arch/x86/include/asm/cpu.h
+++ b/arch/x86/include/asm/cpu.h
@@ -58,6 +58,10 @@ enum {
 	X86_SYSCON_PUNIT,	/* Power unit */
 };
 
+#define CPUID_FEATURE_PAE	BIT(6)
+#define CPUID_FEATURE_PSE36	BIT(17)
+#define CPUID_FEAURE_HTT	BIT(28)
+
 struct cpuid_result {
 	uint32_t eax;
 	uint32_t ebx;
@@ -105,68 +109,47 @@ static inline struct cpuid_result cpuid_ext(int op, unsigned ecx)
 	return result;
 }
 
-/*
- * CPUID functions returning a single datum
- */
-static inline unsigned int cpuid_eax(unsigned int op)
+static inline void native_cpuid(unsigned int *eax, unsigned int *ebx,
+				unsigned int *ecx, unsigned int *edx)
 {
-	unsigned int eax;
-
-	__asm__("mov %%ebx, %%edi;"
-		"cpuid;"
-		"mov %%edi, %%ebx;"
-		: "=a" (eax)
-		: "0" (op)
-		: "ecx", "edx", "edi");
-	return eax;
+	/* ecx is often an input as well as an output. */
+	asm volatile("cpuid"
+	    : "=a" (*eax),
+	      "=b" (*ebx),
+	      "=c" (*ecx),
+	      "=d" (*edx)
+	    : "0" (*eax), "2" (*ecx)
+	    : "memory");
 }
 
-static inline unsigned int cpuid_ebx(unsigned int op)
-{
-	unsigned int eax, ebx;
-
-	__asm__("mov %%ebx, %%edi;"
-		"cpuid;"
-		"mov %%ebx, %%esi;"
-		"mov %%edi, %%ebx;"
-		: "=a" (eax), "=S" (ebx)
-		: "0" (op)
-		: "ecx", "edx", "edi");
-	return ebx;
+#define native_cpuid_reg(reg)					\
+static inline unsigned int cpuid_##reg(unsigned int op)	\
+{								\
+	unsigned int eax = op, ebx, ecx = 0, edx;		\
+								\
+	native_cpuid(&eax, &ebx, &ecx, &edx);			\
+								\
+	return reg;						\
 }
 
-static inline unsigned int cpuid_ecx(unsigned int op)
-{
-	unsigned int eax, ecx;
-
-	__asm__("mov %%ebx, %%edi;"
-		"cpuid;"
-		"mov %%edi, %%ebx;"
-		: "=a" (eax), "=c" (ecx)
-		: "0" (op)
-		: "edx", "edi");
-	return ecx;
-}
+/*
+ * Native CPUID functions returning a single datum.
+ */
+native_cpuid_reg(eax)
+native_cpuid_reg(ebx)
+native_cpuid_reg(ecx)
+native_cpuid_reg(edx)
 
-static inline unsigned int cpuid_edx(unsigned int op)
+#if CONFIG_IS_ENABLED(X86_64)
+static inline int flag_is_changeable_p(u32 flag)
 {
-	unsigned int eax, edx;
-
-	__asm__("mov %%ebx, %%edi;"
-		"cpuid;"
-		"mov %%edi, %%ebx;"
-		: "=a" (eax), "=d" (edx)
-		: "0" (op)
-		: "ecx", "edi");
-	return edx;
+	return 1;
 }
-
-#if !CONFIG_IS_ENABLED(X86_64)
-
+#else
 /* Standard macro to see if a specific flag is changeable */
-static inline int flag_is_changeable_p(uint32_t flag)
+static inline int flag_is_changeable_p(u32 flag)
 {
-	uint32_t f1, f2;
+	u32 f1, f2;
 
 	asm(
 		"pushfl\n\t"
@@ -181,9 +164,9 @@ static inline int flag_is_changeable_p(uint32_t flag)
 		"popfl\n\t"
 		: "=&r" (f1), "=&r" (f2)
 		: "ir" (flag));
-	return ((f1^f2) & flag) != 0;
+	return ((f1 ^ f2) & flag) != 0;
 }
-#endif
+#endif /* X86_64 */
 
 /**
  * cpu_enable_paging_pae() - Enable PAE-paging
diff --git a/arch/x86/include/asm/e820.h b/arch/x86/include/asm/e820.h
index 1ab709abfc8..a535818b2d5 100644
--- a/arch/x86/include/asm/e820.h
+++ b/arch/x86/include/asm/e820.h
@@ -3,6 +3,8 @@
 
 #define E820MAX		128	/* number of entries in E820MAP */
 
+#ifdef __ASSEMBLY__
+
 #define E820_RAM	1
 #define E820_RESERVED	2
 #define E820_ACPI	3
@@ -10,9 +12,21 @@
 #define E820_UNUSABLE	5
 #define E820_COUNT	6	/* Number of types */
 
-#ifndef __ASSEMBLY__
+#else
+
 #include <linux/types.h>
 
+/* Available e820 memory-region types */
+enum e820_type {
+	E820_RAM	= 1,
+	E820_RESERVED,
+	E820_ACPI,
+	E820_NVS,
+	E820_UNUSABLE,
+
+	E820_COUNT,
+};
+
 struct e820_entry {
 	__u64 addr;	/* start of memory segment */
 	__u64 size;	/* size of memory segment */
@@ -22,11 +36,82 @@ struct e820_entry {
 #define ISA_START_ADDRESS	0xa0000
 #define ISA_END_ADDRESS		0x100000
 
+/**
+ * Context to use for e820_add()
+ *
+ * @entries: Table being filled in
+ * @addr: Current address we are up to
+ * @count: Number of entries added to @entries so far
+ * @max_entries: Maximum number of entries allowed
+ */
+struct e820_ctx {
+	struct e820_entry *entries;
+	u64 addr;
+	int count;
+	int max_entries;
+};
+
+/**
+ * e820_init() - Start setting up an e820 table
+ *
+ * @ctx: Context to set up
+ * @entries: Place to put entries
+ * @max_entries: Maximum size of @entries
+ */
+void e820_init(struct e820_ctx *ctx, struct e820_entry *entries,
+	       int max_entries);
+
+/**
+ * e820_add() - Add an entry to the table
+ *
+ * @ctx: Context
+ * @type: Type of entry
+ * @addr: Start address of entry
+ * @size Size of entry
+ */
+void e820_add(struct e820_ctx *ctx, enum e820_type type, u64 addr, u64 size);
+
+/**
+ * e820_to_addr() - Add an entry that covers the space up to a given address
+ *
+ * @ctx: Context
+ * @type: Type of entry
+ * @end_addr: Address where the entry should finish
+ */
+void e820_to_addr(struct e820_ctx *ctx, enum e820_type type, u64 end_addr);
+
+/**
+ * e820_next() - Add an entry that carries on from the last one
+ *
+ * @ctx: Context
+ * @type: Type of entry
+ * @size Size of entry
+ */
+void e820_next(struct e820_ctx *ctx, enum e820_type type, u64 size);
+
+/**
+ * e820_finish() - Finish the table
+ *
+ * Checks the table is not too large, panics if so
+ *
+ * @ctx: Context
+ * Returns: Number of entries
+ */
+int e820_finish(struct e820_ctx *ctx);
+
 /* Implementation-defined function to install an e820 map */
 unsigned int install_e820_map(unsigned int max_entries,
 			      struct e820_entry *);
 
 /**
+ * e820_dump() - Dump the e820 table
+ *
+ * @entries: Pointer to start of table
+ * @count: Number of entries in the table
+ */
+void e820_dump(struct e820_entry *entries, uint count);
+
+/**
  * cb_install_e820_map() - Install e820 map provided by coreboot sysinfo
  *
  * This should be used when booting from coreboot, since in that case the
@@ -39,6 +124,14 @@ unsigned int install_e820_map(unsigned int max_entries,
 unsigned int cb_install_e820_map(unsigned int max_entries,
 				 struct e820_entry *entries);
 
+/**
+ * e820_dump() - Dump an e820 table
+ *
+ * @entries: Pointer to first entry
+ * @count: Number of entries in the table
+ */
+void e820_dump(struct e820_entry *entries, uint count);
+
 #endif /* __ASSEMBLY__ */
 
 #endif /* _ASM_X86_E820_H */
diff --git a/arch/x86/include/asm/interrupt.h b/arch/x86/include/asm/interrupt.h
index e23fb2c8e72..c689fc23d08 100644
--- a/arch/x86/include/asm/interrupt.h
+++ b/arch/x86/include/asm/interrupt.h
@@ -10,6 +10,7 @@
 #ifndef __ASM_INTERRUPT_H_
 #define __ASM_INTERRUPT_H_ 1
 
+#include <stdbool.h>
 #include <asm/types.h>
 
 #define SYS_NUM_IRQS	16
diff --git a/arch/x86/include/asm/msr.h b/arch/x86/include/asm/msr.h
index af5f9a11980..39dc7b33aa0 100644
--- a/arch/x86/include/asm/msr.h
+++ b/arch/x86/include/asm/msr.h
@@ -59,15 +59,14 @@ static inline unsigned long long native_read_tscp(unsigned int *aux)
  * edx:eax, while for x86_64 it doesn't mean rdx:rax or edx:eax. Instead,
  * it means rax *or* rdx.
  */
-#ifdef CONFIG_X86_64
-#define DECLARE_ARGS(val, low, high)	unsigned low, high
-#define EAX_EDX_VAL(val, low, high)	((low) | ((u64)(high) << 32))
-#define EAX_EDX_ARGS(val, low, high)	"a" (low), "d" (high)
+#if CONFIG_IS_ENABLED(X86_64)
+/* Using 64-bit values saves one instruction clearing the high half of low */
+#define DECLARE_ARGS(val, low, high)	unsigned long low, high
+#define EAX_EDX_VAL(val, low, high)	((low) | (high) << 32)
 #define EAX_EDX_RET(val, low, high)	"=a" (low), "=d" (high)
 #else
 #define DECLARE_ARGS(val, low, high)	unsigned long long val
 #define EAX_EDX_VAL(val, low, high)	(val)
-#define EAX_EDX_ARGS(val, low, high)	"A" (val)
 #define EAX_EDX_RET(val, low, high)	"=A" (val)
 #endif
 
diff --git a/arch/x86/include/asm/mtrr.h b/arch/x86/include/asm/mtrr.h
index 2e995f54061..67e897daa25 100644
--- a/arch/x86/include/asm/mtrr.h
+++ b/arch/x86/include/asm/mtrr.h
@@ -91,6 +91,22 @@ struct mtrr_info {
 };
 
 /**
+ * mtrr_to_size() - Convert a mask to a size value
+ *
+ * @mask: Value of the mask register
+ * Return: associated size
+ */
+u64 mtrr_to_size(u64 mask);
+
+/**
+ * mtrr_to_mask() - Convert a size to a mask value
+ *
+ * @size: Value of the size register
+ * Return: associated mask, without MTRR_PHYS_MASK_VALID
+ */
+u64 mtrr_to_mask(u64 size);
+
+/**
  * mtrr_open() - Prepare to adjust MTRRs
  *
  * Use mtrr_open() passing in a structure - this function will init it. Then
diff --git a/arch/x86/include/asm/processor.h b/arch/x86/include/asm/processor.h
index d7b68367861..ad8240be387 100644
--- a/arch/x86/include/asm/processor.h
+++ b/arch/x86/include/asm/processor.h
@@ -18,7 +18,10 @@
 #define X86_GDT_ENTRY_16BIT_DS		6
 #define X86_GDT_ENTRY_16BIT_FLAT_CS	7
 #define X86_GDT_ENTRY_16BIT_FLAT_DS	8
-#define X86_GDT_NUM_ENTRIES		9
+#define X86_GDT_ENTRY_64BIT_CS		9
+#define X86_GDT_ENTRY_64BIT_TS1		10
+#define X86_GDT_ENTRY_64BIT_TS2		11
+#define X86_GDT_NUM_ENTRIES		12
 
 #define X86_GDT_SIZE		(X86_GDT_NUM_ENTRIES * X86_GDT_ENTRY_SIZE)
 
diff --git a/arch/x86/include/asm/setjmp.h b/arch/x86/include/asm/setjmp.h
index 15915d0dc6b..13772574e15 100644
--- a/arch/x86/include/asm/setjmp.h
+++ b/arch/x86/include/asm/setjmp.h
@@ -5,8 +5,8 @@
  * From Linux arch/um/sys-i386/setjmp.S
  */
 
-#ifndef __setjmp_h
-#define __setjmp_h
+#ifndef _ASM_SETJMP_H_
+#define _ASM_SETJMP_H_	1
 
 #ifdef CONFIG_X86_64
 
@@ -34,9 +34,4 @@ struct jmp_buf_data {
 
 #endif
 
-typedef struct jmp_buf_data jmp_buf[1];
-
-int setjmp(jmp_buf env);
-void longjmp(jmp_buf env, int val);
-
-#endif
+#endif /* _ASM_SETJMP_H_ */
diff --git a/arch/x86/lib/Makefile b/arch/x86/lib/Makefile
index 43e6a1de77d..a908356e8a6 100644
--- a/arch/x86/lib/Makefile
+++ b/arch/x86/lib/Makefile
@@ -26,7 +26,9 @@ obj-y	+= e820.o
 obj-y	+= init_helpers.o
 obj-y	+= interrupts.o
 obj-y	+= lpc-uclass.o
+ifndef CONFIG_XPL_BUILD
 obj-y	+= mpspec.o
+endif
 obj-$(CONFIG_$(PHASE_)ACPIGEN) += acpi_nhlt.o
 obj-y	+= northbridge-uclass.o
 obj-$(CONFIG_I8259_PIC) += i8259.o
diff --git a/arch/x86/lib/bios.c b/arch/x86/lib/bios.c
index 03f7360032c..de4578666fb 100644
--- a/arch/x86/lib/bios.c
+++ b/arch/x86/lib/bios.c
@@ -5,6 +5,9 @@
  * Copyright (C) 2007 Advanced Micro Devices, Inc.
  * Copyright (C) 2009-2010 coresystems GmbH
  */
+
+#define LOG_CATEGRORY	LOGC_ARCH
+
 #include <compiler.h>
 #include <bios_emul.h>
 #include <irq_func.h>
@@ -228,7 +231,11 @@ static void vbe_set_graphics(int vesa_mode, struct vesa_state *mode_info)
 {
 	unsigned char *framebuffer;
 
-	mode_info->video_mode = (1 << 14) | vesa_mode;
+	/*
+	 * bit 14 is linear-framebuffer mode
+	 * bit 15 means don't clear the display
+	 */
+	mode_info->video_mode = (1 << 14) | (1 << 15) | vesa_mode;
 	vbe_get_mode_info(mode_info);
 
 	framebuffer = (unsigned char *)(ulong)mode_info->vesa.phys_base_ptr;
@@ -298,16 +305,14 @@ asmlinkage int interrupt_handler(u32 intnumber, u32 gsfs, u32 dses,
 	cs = cs_ip >> 16;
 	flags = stackflags;
 
-#ifdef CONFIG_REALMODE_DEBUG
-	debug("oprom: INT# 0x%x\n", intnumber);
-	debug("oprom: eax: %08x ebx: %08x ecx: %08x edx: %08x\n",
-	      eax, ebx, ecx, edx);
-	debug("oprom: ebp: %08x esp: %08x edi: %08x esi: %08x\n",
-	      ebp, esp, edi, esi);
-	debug("oprom:  ip: %04x      cs: %04x   flags: %08x\n",
-	      ip, cs, flags);
-	debug("oprom: stackflags = %04x\n", stackflags);
-#endif
+	log_debug("oprom: INT# 0x%x\n", intnumber);
+	log_debug("oprom: eax: %08x ebx: %08x ecx: %08x edx: %08x\n",
+		  eax, ebx, ecx, edx);
+	log_debug("oprom: ebp: %08x esp: %08x edi: %08x esi: %08x\n",
+		  ebp, esp, edi, esi);
+	log_debug("oprom:  ip: %04x      cs: %04x   flags: %08x\n",
+		  ip, cs, flags);
+	log_debug("oprom: stackflags = %04x\n", stackflags);
 
 	/*
 	 * Fetch arguments from the stack and put them to a place
diff --git a/arch/x86/lib/bios_interrupts.c b/arch/x86/lib/bios_interrupts.c
index b2cf1527b1c..e0c2284a901 100644
--- a/arch/x86/lib/bios_interrupts.c
+++ b/arch/x86/lib/bios_interrupts.c
@@ -7,6 +7,8 @@
  * Copyright (C) 2007-2009 coresystems GmbH
  */
 
+#define LOG_CATEGRORY	LOGC_ARCH
+
 #include <log.h>
 #include <asm/pci.h>
 #include "bios_emul.h"
@@ -198,10 +200,8 @@ int int1a_handler(void)
 			dm_pci_write_config32(dev, reg, dword);
 			break;
 		}
-#ifdef CONFIG_REALMODE_DEBUG
-		debug("0x%x: bus %d devfn 0x%x reg 0x%x val 0x%x\n", func,
-		      bus, devfn, reg, M.x86.R_ECX);
-#endif
+		log_debug("0x%x: bus %d devfn 0x%x reg 0x%x val 0x%x\n", func,
+			  bus, devfn, reg, M.x86.R_ECX);
 		M.x86.R_EAX &= 0xffff00ff; /* Clear AH */
 		M.x86.R_EAX |= PCIBIOS_SUCCESSFUL;
 		retval = 1;
diff --git a/arch/x86/lib/e820.c b/arch/x86/lib/e820.c
index d478b7486e3..bcc5f6f3044 100644
--- a/arch/x86/lib/e820.c
+++ b/arch/x86/lib/e820.c
@@ -3,13 +3,39 @@
  * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
  */
 
+#define LOG_CATEGORY	LOGC_ARCH
+
 #include <efi_loader.h>
 #include <lmb.h>
+#include <log.h>
 #include <asm/e820.h>
 #include <asm/global_data.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
+static const char *const e820_type_name[E820_COUNT] = {
+	[E820_RAM] = "RAM",
+	[E820_RESERVED] = "Reserved",
+	[E820_ACPI] = "ACPI",
+	[E820_NVS] = "ACPI NVS",
+	[E820_UNUSABLE] = "Unusable",
+};
+
+void e820_dump(struct e820_entry *entries, uint count)
+{
+	int i;
+
+	printf("%12s  %10s  %s\n", "Addr", "Size", "Type");
+	for (i = 0; i < count; i++) {
+		struct e820_entry *entry = &entries[i];
+
+		printf("%12llx  %10llx  %s\n", entry->addr, entry->size,
+		       entry->type < E820_COUNT ?
+		       e820_type_name[entry->type] :
+		       simple_itoa(entry->type));
+	}
+}
+
 /*
  * Install a default e820 table with 4 entries as follows:
  *
@@ -37,6 +63,50 @@ __weak unsigned int install_e820_map(unsigned int max_entries,
 	return 4;
 }
 
+void e820_init(struct e820_ctx *ctx, struct e820_entry *entries,
+	       int max_entries)
+{
+	memset(ctx, '\0', sizeof(*ctx));
+	ctx->entries = entries;
+	ctx->max_entries = max_entries;
+}
+
+void e820_add(struct e820_ctx *ctx, enum e820_type type, u64 addr, u64 size)
+{
+	struct e820_entry *entry = &ctx->entries[ctx->count++];
+
+	if (ctx->count <= ctx->max_entries) {
+		entry->addr = addr;
+		entry->size = size;
+		entry->type = type;
+	}
+	ctx->addr = addr + size;
+}
+
+void e820_next(struct e820_ctx *ctx, enum e820_type type, u64 size)
+{
+	e820_add(ctx, type, ctx->addr, size);
+}
+
+void e820_to_addr(struct e820_ctx *ctx, enum e820_type type, u64 addr)
+{
+	e820_next(ctx, type, addr - ctx->addr);
+}
+
+int e820_finish(struct e820_ctx *ctx)
+{
+	if (ctx->count > ctx->max_entries) {
+		printf("e820 has %d entries but room for only %d\n", ctx->count,
+		       ctx->max_entries);
+		panic("e820 table too large");
+	}
+	log_debug("e820 map installed, n=%d\n", ctx->count);
+	if (_DEBUG)
+		e820_dump(ctx->entries, ctx->count);
+
+	return ctx->count;
+}
+
 #if CONFIG_IS_ENABLED(EFI_LOADER)
 void efi_add_known_memory(void)
 {
diff --git a/arch/x86/lib/i8259.c b/arch/x86/lib/i8259.c
index 465ff70146f..088f78f4661 100644
--- a/arch/x86/lib/i8259.c
+++ b/arch/x86/lib/i8259.c
@@ -13,6 +13,8 @@
  * Programmable Interrupt Controllers.
  */
 
+#define LOG_CATEGORY	UCLASS_IRQ
+
 #include <log.h>
 #include <asm/io.h>
 #include <asm/i8259.h>
diff --git a/arch/x86/lib/spl.c b/arch/x86/lib/spl.c
index 7a033505101..0a6a761987e 100644
--- a/arch/x86/lib/spl.c
+++ b/arch/x86/lib/spl.c
@@ -84,8 +84,6 @@ static int x86_spl_init(void)
 	log_debug("x86 spl starting\n");
 	if (IS_ENABLED(TPL))
 		ret = x86_cpu_reinit_f();
-	else
-		ret = x86_cpu_init_f();
 	ret = spl_init();
 	if (ret) {
 		log_debug("spl_init() failed (err=%d)\n", ret);
@@ -283,7 +281,7 @@ void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image)
 {
 	int ret;
 
-	printf("Jumping to 64-bit U-Boot: Note many features are missing\n");
+	log_debug("Jumping to 64-bit U-Boot\n");
 	ret = cpu_jump_to_64bit_uboot(spl_image->entry_point);
 	debug("ret=%d\n", ret);
 	hang();
diff --git a/arch/x86/lib/tables.c b/arch/x86/lib/tables.c
index 44fe80c5224..ec52992209f 100644
--- a/arch/x86/lib/tables.c
+++ b/arch/x86/lib/tables.c
@@ -45,6 +45,13 @@ struct table_info {
 	int align;
 };
 
+/* QEMU's tables include quite a bit of empty space */
+#ifdef CONFIG_QEMU
+#define ACPI_SIZE	(192 << 10)
+#else
+#define ACPI_SIZE	SZ_64K
+#endif
+
 static struct table_info table_list[] = {
 #ifdef CONFIG_GENERATE_PIRQ_TABLE
 	{ "pirq", write_pirq_routing_table },
@@ -60,7 +67,7 @@ static struct table_info table_list[] = {
 	 * that the calculation of gd->table_end works properly
 	 */
 #ifdef CONFIG_GENERATE_ACPI_TABLE
-	{ "acpi", write_acpi_tables, BLOBLISTT_ACPI_TABLES, SZ_64K, SZ_4K},
+	{ "acpi", write_acpi_tables, BLOBLISTT_ACPI_TABLES, ACPI_SIZE, SZ_4K},
 #endif
 #ifdef CONFIG_GENERATE_SMBIOS_TABLE
 	/*
diff --git a/arch/x86/lib/zimage.c b/arch/x86/lib/zimage.c
index 2eece34a073..2ea9bcf59c2 100644
--- a/arch/x86/lib/zimage.c
+++ b/arch/x86/lib/zimage.c
@@ -225,7 +225,7 @@ struct boot_params *load_zimage(char *image, unsigned long kernel_size,
 	else
 		*load_addressp = ZIMAGE_LOAD_ADDR;
 
-	printf("Building boot_params at 0x%8.8lx\n", (ulong)setup_base);
+	printf("Building boot_params at %lx\n", (ulong)setup_base);
 	memset(setup_base, 0, sizeof(*setup_base));
 	setup_base->hdr = params->hdr;
 
@@ -301,10 +301,13 @@ int setup_zimage(struct boot_params *setup_base, char *cmd_line, int auto_boot,
 		hdr->type_of_loader = 0x80;	/* U-Boot version 0 */
 		if (initrd_addr) {
 			printf("Initial RAM disk at linear address "
-			       "0x%08lx, size %ld bytes\n",
-			       initrd_addr, initrd_size);
+			       "%lx, size %lx (%ld bytes)\n",
+			       initrd_addr, initrd_size, initrd_size);
 
 			hdr->ramdisk_image = initrd_addr;
+			setup_base->ext_ramdisk_image = 0;
+			setup_base->ext_ramdisk_size = 0;
+			setup_base->ext_cmd_line_ptr = 0;
 			hdr->ramdisk_size = initrd_size;
 		}
 	}
@@ -375,8 +378,7 @@ int zboot_load(void)
 		struct boot_params *from = (struct boot_params *)state.base_ptr;
 
 		base_ptr = (struct boot_params *)DEFAULT_SETUP_BASE;
-		log_debug("Building boot_params at 0x%8.8lx\n",
-			  (ulong)base_ptr);
+		log_debug("Building boot_params at %lx\n", (ulong)base_ptr);
 		memset(base_ptr, '\0', sizeof(*base_ptr));
 		base_ptr->hdr = from->hdr;
 	} else {
@@ -424,7 +426,7 @@ int zboot_go(void)
 
 	entry = state.load_address;
 	image_64bit = false;
-	if (IS_ENABLED(CONFIG_X86_RUN_64BIT) &&
+	if (IS_ENABLED(CONFIG_X86_64) &&
 	    (hdr->xloadflags & XLF_KERNEL_64)) {
 		image_64bit = true;
 	}
@@ -464,14 +466,6 @@ static void print_num64(const char *name, u64 value)
 	printf("%-20s: %llx\n", name, value);
 }
 
-static const char *const e820_type_name[E820_COUNT] = {
-	[E820_RAM] = "RAM",
-	[E820_RESERVED] = "Reserved",
-	[E820_ACPI] = "ACPI",
-	[E820_NVS] = "ACPI NVS",
-	[E820_UNUSABLE] = "Unusable",
-};
-
 static const char *const bootloader_id[] = {
 	"LILO",
 	"Loadlin",
@@ -559,23 +553,13 @@ void zimage_dump(struct boot_params *base_ptr, bool show_cmdline)
 {
 	struct setup_header *hdr;
 	const char *version;
-	int i;
 
 	printf("Setup located at %p:\n\n", base_ptr);
 	print_num64("ACPI RSDP addr", base_ptr->acpi_rsdp_addr);
 
 	printf("E820: %d entries\n", base_ptr->e820_entries);
-	if (base_ptr->e820_entries) {
-		printf("%12s  %10s  %s\n", "Addr", "Size", "Type");
-		for (i = 0; i < base_ptr->e820_entries; i++) {
-			struct e820_entry *entry = &base_ptr->e820_map[i];
-
-			printf("%12llx  %10llx  %s\n", entry->addr, entry->size,
-			       entry->type < E820_COUNT ?
-			       e820_type_name[entry->type] :
-			       simple_itoa(entry->type));
-		}
-	}
+	if (base_ptr->e820_entries)
+		e820_dump(base_ptr->e820_map, base_ptr->e820_entries);
 
 	hdr = &base_ptr->hdr;
 	print_num("Setup sectors", hdr->setup_sects);
diff --git a/arch/xtensa/lib/cache.c b/arch/xtensa/lib/cache.c
index e6a7f6827fc..1229b407783 100644
--- a/arch/xtensa/lib/cache.c
+++ b/arch/xtensa/lib/cache.c
@@ -6,6 +6,7 @@
 
 #include <cpu_func.h>
 #include <asm/cache.h>
+#include <linux/errno.h>
 
 /*
  * We currently run always with caches enabled when running from memory.
@@ -57,3 +58,8 @@ void invalidate_icache_all(void)
 {
 	__invalidate_icache_all();
 }
+
+int __weak pgprot_set_attrs(phys_addr_t addr, size_t size, enum pgprot_attrs perm)
+{
+	return -ENOSYS;
+}
diff --git a/board/airoha/an7581/MAINTAINERS b/board/airoha/an7581/MAINTAINERS
new file mode 100644
index 00000000000..28ec2fbf2ea
--- /dev/null
+++ b/board/airoha/an7581/MAINTAINERS
@@ -0,0 +1,5 @@
+AN7581
+M:	Christian Marangi <ansuelsmth@gmail.com>
+S:	Maintained
+N:      airoha
+N:      an7581
diff --git a/board/airoha/an7581/Makefile b/board/airoha/an7581/Makefile
new file mode 100644
index 00000000000..70f8db7bce9
--- /dev/null
+++ b/board/airoha/an7581/Makefile
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier:	GPL-2.0
+
+obj-y	+= an7581_rfb.o
diff --git a/board/airoha/an7581/an7581_rfb.c b/board/airoha/an7581/an7581_rfb.c
new file mode 100644
index 00000000000..aa73679d929
--- /dev/null
+++ b/board/airoha/an7581/an7581_rfb.c
@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Author: Christian Marangi <ansuelsmth@gmail.com>
+ */
+
+#include <asm/global_data.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_init(void)
+{
+	/* address of boot parameters */
+	gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
+
+	return 0;
+}
diff --git a/board/armltd/vexpress64/Kconfig b/board/armltd/vexpress64/Kconfig
index 584b5455e97..7e8709444fe 100644
--- a/board/armltd/vexpress64/Kconfig
+++ b/board/armltd/vexpress64/Kconfig
@@ -28,7 +28,7 @@ choice
 config TARGET_VEXPRESS64_BASE_FVP
 	bool "Support Versatile Express ARMv8a FVP BASE model"
 	select VEXPRESS64_BASE_MODEL
-	imply OF_HAS_PRIOR_STAGE
+	imply OF_HAS_PRIOR_STAGE if !BLOBLIST
 
 config TARGET_VEXPRESS64_BASER_FVP
 	bool "Support Versatile Express ARMv8r64 FVP BASE model"
diff --git a/board/armltd/vexpress64/Makefile b/board/armltd/vexpress64/Makefile
index 1878fbed4ec..b0dd1d0af87 100644
--- a/board/armltd/vexpress64/Makefile
+++ b/board/armltd/vexpress64/Makefile
@@ -3,5 +3,8 @@
 # (C) Copyright 2000-2004
 # Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 
-obj-y	:= vexpress64.o lowlevel_init.o
+obj-y	:= vexpress64.o
+
+obj-$(CONFIG_OF_HAS_PRIOR_STAGE)	+= lowlevel_init.o
+
 obj-$(CONFIG_TARGET_VEXPRESS64_JUNO)	+= pcie.o
diff --git a/board/armltd/vexpress64/vexpress64.c b/board/armltd/vexpress64/vexpress64.c
index b5ede58757d..0b75c1358f0 100644
--- a/board/armltd/vexpress64/vexpress64.c
+++ b/board/armltd/vexpress64/vexpress64.c
@@ -100,7 +100,9 @@ int dram_init_banksize(void)
  * Push the variable into the .data section so that it
  * does not get cleared later.
  */
+#ifdef CONFIG_OF_HAS_PRIOR_STAGE
 unsigned long __section(".data") prior_stage_fdt_address[2];
+#endif
 
 #ifdef CONFIG_OF_BOARD
 
@@ -151,6 +153,7 @@ static phys_addr_t find_dtb_in_nor_flash(const char *partname)
 }
 #endif
 
+#ifdef CONFIG_OF_HAS_PRIOR_STAGE
 /*
  * Filter for a valid DTB, as TF-A happens to provide a pointer to some
  * data structure using the DTB format, which we cannot use.
@@ -201,6 +204,7 @@ int board_fdt_blob_setup(void **fdtp)
 	return -ENXIO;
 }
 #endif
+#endif
 
 /* Actual reset is done via PSCI. */
 void reset_cpu(void)
diff --git a/board/beacon/imx8mm/spl.c b/board/beacon/imx8mm/spl.c
index 12013aa5a4d..93ee5b7ee0c 100644
--- a/board/beacon/imx8mm/spl.c
+++ b/board/beacon/imx8mm/spl.c
@@ -100,9 +100,6 @@ void board_init_f(ulong dummy)
 	int ret;
 
 	arch_cpu_init();
-
-	init_uart_clk(1);
-
 	timer_init();
 
 	/* Clear the BSS. */
@@ -114,8 +111,6 @@ void board_init_f(ulong dummy)
 		hang();
 	}
 
-	preloader_console_init();
-
 	ret = uclass_get_device_by_name(UCLASS_CLK,
 					"clock-controller@30380000",
 					&dev);
@@ -124,6 +119,7 @@ void board_init_f(ulong dummy)
 		hang();
 	}
 
+	preloader_console_init();
 	enable_tzc380();
 
 	power_init_board();
diff --git a/board/beacon/imx8mn/spl.c b/board/beacon/imx8mn/spl.c
index f03841e5a01..e91d3fdcf5e 100644
--- a/board/beacon/imx8mn/spl.c
+++ b/board/beacon/imx8mn/spl.c
@@ -111,8 +111,6 @@ int board_early_init_f(void)
 	/* Claiming pwm pins prevents LCD flicker during startup*/
 	imx_iomux_v3_setup_multiple_pads(pwm_pads, ARRAY_SIZE(pwm_pads));
 
-	init_uart_clk(1);
-
 	return 0;
 }
 
diff --git a/board/beacon/imx8mp/spl.c b/board/beacon/imx8mp/spl.c
index 30d577f7e0e..027fae38278 100644
--- a/board/beacon/imx8mp/spl.c
+++ b/board/beacon/imx8mp/spl.c
@@ -50,7 +50,7 @@ void spl_board_init(void)
 	 * setting done. Default is 400Mhz (system_pll1_800m with div = 2)
 	 * set by ROM for ND VDD_SOC
 	 */
-	if (IS_ENABLED(CONFIG_IMX8M_VDD_SOC_850MV)) {
+	if (!IS_ENABLED(CONFIG_IMX8M_VDD_SOC_850MV)) {
 		clock_enable(CCGR_GIC, 0);
 		clock_set_target_val(GIC_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(5));
 		clock_enable(CCGR_GIC, 1);
@@ -112,8 +112,6 @@ void board_init_f(ulong dummy)
 
 	arch_cpu_init();
 
-	init_uart_clk(1);
-
 	ret = spl_early_init();
 	if (ret) {
 		debug("spl_init() failed: %d\n", ret);
diff --git a/board/beagle/beagley-ai/Kconfig b/board/beagle/beagley-ai/Kconfig
new file mode 100644
index 00000000000..bf953982151
--- /dev/null
+++ b/board/beagle/beagley-ai/Kconfig
@@ -0,0 +1,26 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2025 Texas Instruments Incorporated - https://www.ti.com/
+#
+
+if TARGET_J722S_R5_BEAGLEY_AI || TARGET_J722S_A53_BEAGLEY_AI
+
+config SYS_BOARD
+       default "beagley-ai"
+
+config SYS_VENDOR
+       default "beagle"
+
+config SYS_CONFIG_NAME
+       default "beagley_ai"
+
+source "board/ti/common/Kconfig"
+
+endif
+
+if TARGET_J722S_R5_BEAGLEY_AI
+
+config SPL_LDSCRIPT
+	default "arch/arm/mach-omap2/u-boot-spl.lds"
+
+endif
diff --git a/board/beagle/beagley-ai/MAINTAINERS b/board/beagle/beagley-ai/MAINTAINERS
new file mode 100644
index 00000000000..1623329b714
--- /dev/null
+++ b/board/beagle/beagley-ai/MAINTAINERS
@@ -0,0 +1,8 @@
+BEAGLEY-AI BOARD
+M:      Robert Nelson <robertcnelson@gmail.com>
+M:      Tom Rini <trini@konsulko.com>
+S:	Maintained
+F:	board/beagle/beagley-ai/
+F:	include/configs/beagley_ai.h
+F:	configs/am67a_beagley_ai_r5_defconfig
+F:	configs/am67a_beagley_ai_a53_defconfig
diff --git a/board/beagle/beagley-ai/Makefile b/board/beagle/beagley-ai/Makefile
new file mode 100644
index 00000000000..08593548e58
--- /dev/null
+++ b/board/beagle/beagley-ai/Makefile
@@ -0,0 +1,7 @@
+#
+# Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
+#
+# SPDX-License-Identifier:     GPL-2.0+
+#
+
+obj-y	+= beagley-ai.o
diff --git a/board/beagle/beagley-ai/beagley-ai.c b/board/beagle/beagley-ai/beagley-ai.c
new file mode 100644
index 00000000000..9786f628f6d
--- /dev/null
+++ b/board/beagle/beagley-ai/beagley-ai.c
@@ -0,0 +1,62 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * https://www.beagleboard.org/boards/beagley-ai
+ *
+ * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#include <asm/arch/hardware.h>
+#include <asm/io.h>
+#include <dm/uclass.h>
+#include <env.h>
+#include <fdt_support.h>
+#include <spl.h>
+#include <asm/arch/k3-ddr.h>
+
+#if IS_ENABLED(CONFIG_SET_DFU_ALT_INFO)
+void set_dfu_alt_info(char *interface, char *devstr)
+{
+	if (IS_ENABLED(CONFIG_EFI_HAVE_CAPSULE_SUPPORT))
+		env_set("dfu_alt_info", update_info.dfu_string);
+}
+#endif
+
+int board_init(void)
+{
+	return 0;
+}
+
+int dram_init(void)
+{
+	return fdtdec_setup_mem_size_base();
+}
+
+int dram_init_banksize(void)
+{
+	return fdtdec_setup_memory_banksize();
+}
+
+#if defined(CONFIG_XPL_BUILD)
+void spl_perform_fixups(struct spl_image_info *spl_image)
+{
+	if (IS_ENABLED(CONFIG_K3_DDRSS)) {
+		if (IS_ENABLED(CONFIG_K3_INLINE_ECC))
+			fixup_ddr_driver_for_ecc(spl_image);
+	} else {
+		fixup_memory_node(spl_image);
+	}
+}
+#endif
+
+#if IS_ENABLED(CONFIG_BOARD_LATE_INIT)
+int board_late_init(void)
+{
+	char fdtfile[50];
+
+	snprintf(fdtfile, sizeof(fdtfile), "%s.dtb", CONFIG_DEFAULT_DEVICE_TREE);
+
+	env_set("fdtfile", fdtfile);
+
+	return 0;
+}
+#endif
diff --git a/board/beagle/beagley-ai/beagley-ai.env b/board/beagle/beagley-ai/beagley-ai.env
new file mode 100644
index 00000000000..10d62034e1a
--- /dev/null
+++ b/board/beagle/beagley-ai/beagley-ai.env
@@ -0,0 +1,21 @@
+#include <env/ti/ti_common.env>
+#include <env/ti/mmc.env>
+
+#if CONFIG_CMD_REMOTEPROC
+#include <env/ti/k3_rproc.env>
+#endif
+
+name_kern=Image
+console=ttyS2,115200n8
+args_all=setenv optargs ${optargs} earlycon=ns16550a,mmio32,0x02800000
+	${mtdparts}
+run_kern=booti ${loadaddr} ${rd_spec} ${fdtaddr}
+
+boot_targets=mmc1 mmc0 pxe dhcp
+boot=mmc
+mmcdev=1
+bootpart=1:2
+bootdir=/boot
+rd_spec=-
+
+rproc_fw_binaries= 0 /lib/firmware/j722s-mcu-r5f0_0-fw 2 /lib/firmware/j722s-main-r5f0_0-fw 3 /lib/firmware/j722s-c71_0-fw 4 /lib/firmware/j722s-c71_1-fw
diff --git a/board/beagle/beagley-ai/board-cfg.yaml b/board/beagle/beagley-ai/board-cfg.yaml
new file mode 100644
index 00000000000..f9a4c438ca9
--- /dev/null
+++ b/board/beagle/beagley-ai/board-cfg.yaml
@@ -0,0 +1,36 @@
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
+#
+# Board configuration for J722S
+#
+
+---
+
+board-cfg:
+    rev:
+        boardcfg_abi_maj: 0x0
+        boardcfg_abi_min: 0x1
+    control:
+        subhdr:
+            magic: 0xC1D3
+            size: 7
+        main_isolation_enable: 0x5A
+        main_isolation_hostid: 0x2
+    secproxy:
+        subhdr:
+            magic: 0x1207
+            size: 7
+        scaling_factor: 0x1
+        scaling_profile: 0x1
+        disable_main_nav_secure_proxy: 0
+    msmc:
+        subhdr:
+            magic: 0xA5C3
+            size: 5
+        msmc_cache_size: 0x0
+    debug_cfg:
+        subhdr:
+            magic: 0x020C
+            size: 8
+        trace_dst_enables: 0x00
+        trace_src_enables: 0x00
diff --git a/board/beagle/beagley-ai/pm-cfg.yaml b/board/beagle/beagley-ai/pm-cfg.yaml
new file mode 100644
index 00000000000..46b3ad20109
--- /dev/null
+++ b/board/beagle/beagley-ai/pm-cfg.yaml
@@ -0,0 +1,12 @@
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
+#
+# Power management configuration for J722S
+#
+
+---
+
+pm-cfg:
+    rev:
+        boardcfg_abi_maj: 0x0
+        boardcfg_abi_min: 0x1
diff --git a/board/beagle/beagley-ai/rm-cfg.yaml b/board/beagle/beagley-ai/rm-cfg.yaml
new file mode 100644
index 00000000000..e32beb84795
--- /dev/null
+++ b/board/beagle/beagley-ai/rm-cfg.yaml
@@ -0,0 +1,1137 @@
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
+#
+# Resource management configuration for J722S
+#
+
+---
+
+rm-cfg:
+    rm_boardcfg:
+        rev:
+            boardcfg_abi_maj: 0x0
+            boardcfg_abi_min: 0x1
+        host_cfg:
+            subhdr:
+                magic: 0x4C41
+                size: 356
+            host_cfg_entries:
+                -
+                    host_id: 12
+                    allowed_atype: 0x2A
+                    allowed_qos: 0xAAAA
+                    allowed_orderid: 0xAAAAAAAA
+                    allowed_priority: 0xAAAA
+                    allowed_sched_priority: 0xAA
+                -
+                    host_id: 20
+                    allowed_atype: 0x2A
+                    allowed_qos: 0xAAAA
+                    allowed_orderid: 0xAAAAAAAA
+                    allowed_priority: 0xAAAA
+                    allowed_sched_priority: 0xAA
+                -
+                    host_id: 22
+                    allowed_atype: 0x2A
+                    allowed_qos: 0xAAAA
+                    allowed_orderid: 0xAAAAAAAA
+                    allowed_priority: 0xAAAA
+                    allowed_sched_priority: 0xAA
+                -
+                    host_id: 30
+                    allowed_atype: 0x2A
+                    allowed_qos: 0xAAAA
+                    allowed_orderid: 0xAAAAAAAA
+                    allowed_priority: 0xAAAA
+                    allowed_sched_priority: 0xAA
+                -
+                    host_id: 36
+                    allowed_atype: 0x2A
+                    allowed_qos: 0xAAAA
+                    allowed_orderid: 0xAAAAAAAA
+                    allowed_priority: 0xAAAA
+                    allowed_sched_priority: 0xAA
+                -
+                    host_id: 38
+                    allowed_atype: 0x2A
+                    allowed_qos: 0xAAAA
+                    allowed_orderid: 0xAAAAAAAA
+                    allowed_priority: 0xAAAA
+                    allowed_sched_priority: 0xAA
+                -
+                    host_id: 0
+                    allowed_atype: 0
+                    allowed_qos: 0
+                    allowed_orderid: 0
+                    allowed_priority: 0
+                    allowed_sched_priority: 0
+                -
+                    host_id: 0
+                    allowed_atype: 0
+                    allowed_qos: 0
+                    allowed_orderid: 0
+                    allowed_priority: 0
+                    allowed_sched_priority: 0
+                -
+                    host_id: 0
+                    allowed_atype: 0
+                    allowed_qos: 0
+                    allowed_orderid: 0
+                    allowed_priority: 0
+                    allowed_sched_priority: 0
+                -
+                    host_id: 0
+                    allowed_atype: 0
+                    allowed_qos: 0
+                    allowed_orderid: 0
+                    allowed_priority: 0
+                    allowed_sched_priority: 0
+                -
+                    host_id: 0
+                    allowed_atype: 0
+                    allowed_qos: 0
+                    allowed_orderid: 0
+                    allowed_priority: 0
+                    allowed_sched_priority: 0
+                -
+                    host_id: 0
+                    allowed_atype: 0
+                    allowed_qos: 0
+                    allowed_orderid: 0
+                    allowed_priority: 0
+                    allowed_sched_priority: 0
+                -
+                    host_id: 0
+                    allowed_atype: 0
+                    allowed_qos: 0
+                    allowed_orderid: 0
+                    allowed_priority: 0
+                    allowed_sched_priority: 0
+                -
+                    host_id: 0
+                    allowed_atype: 0
+                    allowed_qos: 0
+                    allowed_orderid: 0
+                    allowed_priority: 0
+                    allowed_sched_priority: 0
+                -
+                    host_id: 0
+                    allowed_atype: 0
+                    allowed_qos: 0
+                    allowed_orderid: 0
+                    allowed_priority: 0
+                    allowed_sched_priority: 0
+                -
+                    host_id: 0
+                    allowed_atype: 0
+                    allowed_qos: 0
+                    allowed_orderid: 0
+                    allowed_priority: 0
+                    allowed_sched_priority: 0
+                -
+                    host_id: 0
+                    allowed_atype: 0
+                    allowed_qos: 0
+                    allowed_orderid: 0
+                    allowed_priority: 0
+                    allowed_sched_priority: 0
+                -
+                    host_id: 0
+                    allowed_atype: 0
+                    allowed_qos: 0
+                    allowed_orderid: 0
+                    allowed_priority: 0
+                    allowed_sched_priority: 0
+                -
+                    host_id: 0
+                    allowed_atype: 0
+                    allowed_qos: 0
+                    allowed_orderid: 0
+                    allowed_priority: 0
+                    allowed_sched_priority: 0
+                -
+                    host_id: 0
+                    allowed_atype: 0
+                    allowed_qos: 0
+                    allowed_orderid: 0
+                    allowed_priority: 0
+                    allowed_sched_priority: 0
+                -
+                    host_id: 0
+                    allowed_atype: 0
+                    allowed_qos: 0
+                    allowed_orderid: 0
+                    allowed_priority: 0
+                    allowed_sched_priority: 0
+                -
+                    host_id: 0
+                    allowed_atype: 0
+                    allowed_qos: 0
+                    allowed_orderid: 0
+                    allowed_priority: 0
+                    allowed_sched_priority: 0
+                -
+                    host_id: 0
+                    allowed_atype: 0
+                    allowed_qos: 0
+                    allowed_orderid: 0
+                    allowed_priority: 0
+                    allowed_sched_priority: 0
+                -
+                    host_id: 0
+                    allowed_atype: 0
+                    allowed_qos: 0
+                    allowed_orderid: 0
+                    allowed_priority: 0
+                    allowed_sched_priority: 0
+                -
+                    host_id: 0
+                    allowed_atype: 0
+                    allowed_qos: 0
+                    allowed_orderid: 0
+                    allowed_priority: 0
+                    allowed_sched_priority: 0
+                -
+                    host_id: 0
+                    allowed_atype: 0
+                    allowed_qos: 0
+                    allowed_orderid: 0
+                    allowed_priority: 0
+                    allowed_sched_priority: 0
+                -
+                    host_id: 0
+                    allowed_atype: 0
+                    allowed_qos: 0
+                    allowed_orderid: 0
+                    allowed_priority: 0
+                    allowed_sched_priority: 0
+                -
+                    host_id: 0
+                    allowed_atype: 0
+                    allowed_qos: 0
+                    allowed_orderid: 0
+                    allowed_priority: 0
+                    allowed_sched_priority: 0
+                -
+                    host_id: 0
+                    allowed_atype: 0
+                    allowed_qos: 0
+                    allowed_orderid: 0
+                    allowed_priority: 0
+                    allowed_sched_priority: 0
+                -
+                    host_id: 0
+                    allowed_atype: 0
+                    allowed_qos: 0
+                    allowed_orderid: 0
+                    allowed_priority: 0
+                    allowed_sched_priority: 0
+                -
+                    host_id: 0
+                    allowed_atype: 0
+                    allowed_qos: 0
+                    allowed_orderid: 0
+                    allowed_priority: 0
+                    allowed_sched_priority: 0
+                -
+                    host_id: 0
+                    allowed_atype: 0
+                    allowed_qos: 0
+                    allowed_orderid: 0
+                    allowed_priority: 0
+                    allowed_sched_priority: 0
+        resasg:
+            subhdr:
+                magic: 0x7B25
+                size: 8
+            resasg_entries_size: 1184
+            reserved: 0
+    resasg_entries:
+        -
+            start_resource: 0
+            num_resource: 16
+            type: 192
+            host_id: 12
+            reserved: 0
+        -
+            start_resource: 16
+            num_resource: 6
+            type: 192
+            host_id: 38
+            reserved: 0
+        -
+            start_resource: 34
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+            host_id: 30
+            reserved: 0
+        -
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+            host_id: 12
+            reserved: 0
+        -
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+            host_id: 30
+            reserved: 0
+        -
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+            host_id: 38
+            reserved: 0
+        -
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+            type: 384
+            host_id: 128
+            reserved: 0
+        -
+            start_resource: 50176
+            num_resource: 164
+            type: 1666
+            host_id: 128
+            reserved: 0
+        -
+            start_resource: 0
+            num_resource: 1
+            type: 1667
+            host_id: 128
+            reserved: 0
+        -
+            start_resource: 0
+            num_resource: 16
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+            reserved: 0
+        -
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+            reserved: 0
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+            reserved: 0
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+            reserved: 0
+        -
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+        -
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+            reserved: 0
+        -
+            start_resource: 73
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+            host_id: 36
+            reserved: 0
+        -
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+            num_resource: 2
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+            host_id: 30
+            reserved: 0
+        -
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+            num_resource: 2
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+            reserved: 0
+        -
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+            host_id: 12
+            reserved: 0
+        -
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+            reserved: 0
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+        -
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+            reserved: 0
+        -
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+            reserved: 0
+        -
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+            reserved: 0
+        -
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+            reserved: 0
+        -
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+        -
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+            host_id: 12
+            reserved: 0
+        -
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+            host_id: 35
+            reserved: 0
+        -
+            start_resource: 529
+            num_resource: 256
+            type: 1805
+            host_id: 36
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diff --git a/board/beagle/beagley-ai/sec-cfg.yaml b/board/beagle/beagley-ai/sec-cfg.yaml
new file mode 100644
index 00000000000..a41374b30c9
--- /dev/null
+++ b/board/beagle/beagley-ai/sec-cfg.yaml
@@ -0,0 +1,379 @@
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
+#
+# Security management configuration for J722S
+#
+
+---
+
+sec-cfg:
+    rev:
+        boardcfg_abi_maj: 0x0
+        boardcfg_abi_min: 0x1
+    processor_acl_list:
+        subhdr:
+            magic: 0xF1EA
+            size: 164
+        proc_acl_entries:
+            -
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            -
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            -
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            -
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            -
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            -
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            -
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            -
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            -
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            -
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            -
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            -
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            -
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            -
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            -
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            -
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            -
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            -
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            -
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            -
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            -
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            -
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            -
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            -
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            -
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            -
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            -
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            -
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            -
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            -
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            -
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            -
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+    host_hierarchy:
+        subhdr:
+            magic: 0x8D27
+            size: 68
+        host_hierarchy_entries:
+            -
+                host_id: 0
+                supervisor_host_id: 0
+            -
+                host_id: 0
+                supervisor_host_id: 0
+            -
+                host_id: 0
+                supervisor_host_id: 0
+            -
+                host_id: 0
+                supervisor_host_id: 0
+            -
+                host_id: 0
+                supervisor_host_id: 0
+            -
+                host_id: 0
+                supervisor_host_id: 0
+            -
+                host_id: 0
+                supervisor_host_id: 0
+            -
+                host_id: 0
+                supervisor_host_id: 0
+            -
+                host_id: 0
+                supervisor_host_id: 0
+            -
+                host_id: 0
+                supervisor_host_id: 0
+            -
+                host_id: 0
+                supervisor_host_id: 0
+            -
+                host_id: 0
+                supervisor_host_id: 0
+            -
+                host_id: 0
+                supervisor_host_id: 0
+            -
+                host_id: 0
+                supervisor_host_id: 0
+            -
+                host_id: 0
+                supervisor_host_id: 0
+            -
+                host_id: 0
+                supervisor_host_id: 0
+            -
+                host_id: 0
+                supervisor_host_id: 0
+            -
+                host_id: 0
+                supervisor_host_id: 0
+            -
+                host_id: 0
+                supervisor_host_id: 0
+            -
+                host_id: 0
+                supervisor_host_id: 0
+            -
+                host_id: 0
+                supervisor_host_id: 0
+            -
+                host_id: 0
+                supervisor_host_id: 0
+            -
+                host_id: 0
+                supervisor_host_id: 0
+            -
+                host_id: 0
+                supervisor_host_id: 0
+            -
+                host_id: 0
+                supervisor_host_id: 0
+            -
+                host_id: 0
+                supervisor_host_id: 0
+            -
+                host_id: 0
+                supervisor_host_id: 0
+            -
+                host_id: 0
+                supervisor_host_id: 0
+            -
+                host_id: 0
+                supervisor_host_id: 0
+            -
+                host_id: 0
+                supervisor_host_id: 0
+            -
+                host_id: 0
+                supervisor_host_id: 0
+            -
+                host_id: 0
+                supervisor_host_id: 0
+    otp_config:
+        subhdr:
+            magic: 0x4081
+            size: 69
+        write_host_id: 0
+        otp_entry:
+            -
+                host_id: 0
+                host_perms: 0
+            -
+                host_id: 0
+                host_perms: 0
+            -
+                host_id: 0
+                host_perms: 0
+            -
+                host_id: 0
+                host_perms: 0
+            -
+                host_id: 0
+                host_perms: 0
+            -
+                host_id: 0
+                host_perms: 0
+            -
+                host_id: 0
+                host_perms: 0
+            -
+                host_id: 0
+                host_perms: 0
+            -
+                host_id: 0
+                host_perms: 0
+            -
+                host_id: 0
+                host_perms: 0
+            -
+                host_id: 0
+                host_perms: 0
+            -
+                host_id: 0
+                host_perms: 0
+            -
+                host_id: 0
+                host_perms: 0
+            -
+                host_id: 0
+                host_perms: 0
+            -
+                host_id: 0
+                host_perms: 0
+            -
+                host_id: 0
+                host_perms: 0
+            -
+                host_id: 0
+                host_perms: 0
+            -
+                host_id: 0
+                host_perms: 0
+            -
+                host_id: 0
+                host_perms: 0
+            -
+                host_id: 0
+                host_perms: 0
+            -
+                host_id: 0
+                host_perms: 0
+            -
+                host_id: 0
+                host_perms: 0
+            -
+                host_id: 0
+                host_perms: 0
+            -
+                host_id: 0
+                host_perms: 0
+            -
+                host_id: 0
+                host_perms: 0
+            -
+                host_id: 0
+                host_perms: 0
+            -
+                host_id: 0
+                host_perms: 0
+            -
+                host_id: 0
+                host_perms: 0
+            -
+                host_id: 0
+                host_perms: 0
+            -
+                host_id: 0
+                host_perms: 0
+            -
+                host_id: 0
+                host_perms: 0
+            -
+                host_id: 0
+                host_perms: 0
+    dkek_config:
+        subhdr:
+            magic: 0x5170
+            size: 12
+        allowed_hosts: [128, 0, 0, 0]
+        allow_dkek_export_tisci: 0x5A
+        rsvd: [0, 0, 0]
+    sa2ul_cfg:
+        subhdr:
+            magic: 0x23BE
+            size: 0
+        auth_resource_owner: 0
+        enable_saul_psil_global_config_writes: 0x5A
+        rsvd: [0, 0]
+    sec_dbg_config:
+        subhdr:
+            magic: 0x42AF
+            size: 16
+        allow_jtag_unlock: 0x5A
+        allow_wildcard_unlock: 0x5A
+        allowed_debug_level_rsvd: 0
+        rsvd: 0
+        min_cert_rev: 0x0
+        jtag_unlock_hosts: [0, 0, 0, 0]
+    sec_handover_cfg:
+        subhdr:
+            magic: 0x608F
+            size: 10
+        handover_msg_sender: 0
+        handover_to_host_id: 0
+        rsvd: [0, 0, 0, 0]
diff --git a/board/beagle/beagley-ai/tifs-rm-cfg.yaml b/board/beagle/beagley-ai/tifs-rm-cfg.yaml
new file mode 100644
index 00000000000..4a2af0ebcaf
--- /dev/null
+++ b/board/beagle/beagley-ai/tifs-rm-cfg.yaml
@@ -0,0 +1,993 @@
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
+#
+# Resource management configuration for J722S
+#
+
+---
+
+tifs-rm-cfg:
+    rm_boardcfg:
+        rev:
+            boardcfg_abi_maj: 0x0
+            boardcfg_abi_min: 0x1
+        host_cfg:
+            subhdr:
+                magic: 0x4C41
+                size: 356
+            host_cfg_entries:
+                - #1
+                    host_id: 12
+                    allowed_atype: 0x2A
+                    allowed_qos: 0xAAAA
+                    allowed_orderid: 0xAAAAAAAA
+                    allowed_priority: 0xAAAA
+                    allowed_sched_priority: 0xAA
+                - #2
+                    host_id: 20
+                    allowed_atype: 0x2A
+                    allowed_qos: 0xAAAA
+                    allowed_orderid: 0xAAAAAAAA
+                    allowed_priority: 0xAAAA
+                    allowed_sched_priority: 0xAA
+                - #3
+                    host_id: 22
+                    allowed_atype: 0x2A
+                    allowed_qos: 0xAAAA
+                    allowed_orderid: 0xAAAAAAAA
+                    allowed_priority: 0xAAAA
+                    allowed_sched_priority: 0xAA
+                - #4
+                    host_id: 30
+                    allowed_atype: 0x2A
+                    allowed_qos: 0xAAAA
+                    allowed_orderid: 0xAAAAAAAA
+                    allowed_priority: 0xAAAA
+                    allowed_sched_priority: 0xAA
+                - #5
+                    host_id: 36
+                    allowed_atype: 0x2A
+                    allowed_qos: 0xAAAA
+                    allowed_orderid: 0xAAAAAAAA
+                    allowed_priority: 0xAAAA
+                    allowed_sched_priority: 0xAA
+                - #6
+                    host_id: 38
+                    allowed_atype: 0x2A
+                    allowed_qos: 0xAAAA
+                    allowed_orderid: 0xAAAAAAAA
+                    allowed_priority: 0xAAAA
+                    allowed_sched_priority: 0xAA
+                - #7
+                    host_id: 0
+                    allowed_atype: 0
+                    allowed_qos: 0
+                    allowed_orderid: 0
+                    allowed_priority: 0
+                    allowed_sched_priority: 0
+                - #8
+                    host_id: 0
+                    allowed_atype: 0
+                    allowed_qos: 0
+                    allowed_orderid: 0
+                    allowed_priority: 0
+                    allowed_sched_priority: 0
+                - #9
+                    host_id: 0
+                    allowed_atype: 0
+                    allowed_qos: 0
+                    allowed_orderid: 0
+                    allowed_priority: 0
+                    allowed_sched_priority: 0
+                - #10
+                    host_id: 0
+                    allowed_atype: 0
+                    allowed_qos: 0
+                    allowed_orderid: 0
+                    allowed_priority: 0
+                    allowed_sched_priority: 0
+                - #11
+                    host_id: 0
+                    allowed_atype: 0
+                    allowed_qos: 0
+                    allowed_orderid: 0
+                    allowed_priority: 0
+                    allowed_sched_priority: 0
+                - #12
+                    host_id: 0
+                    allowed_atype: 0
+                    allowed_qos: 0
+                    allowed_orderid: 0
+                    allowed_priority: 0
+                    allowed_sched_priority: 0
+                - #13
+                    host_id: 0
+                    allowed_atype: 0
+                    allowed_qos: 0
+                    allowed_orderid: 0
+                    allowed_priority: 0
+                    allowed_sched_priority: 0
+                - #14
+                    host_id: 0
+                    allowed_atype: 0
+                    allowed_qos: 0
+                    allowed_orderid: 0
+                    allowed_priority: 0
+                    allowed_sched_priority: 0
+                - #15
+                    host_id: 0
+                    allowed_atype: 0
+                    allowed_qos: 0
+                    allowed_orderid: 0
+                    allowed_priority: 0
+                    allowed_sched_priority: 0
+                - #16
+                    host_id: 0
+                    allowed_atype: 0
+                    allowed_qos: 0
+                    allowed_orderid: 0
+                    allowed_priority: 0
+                    allowed_sched_priority: 0
+                - #17
+                    host_id: 0
+                    allowed_atype: 0
+                    allowed_qos: 0
+                    allowed_orderid: 0
+                    allowed_priority: 0
+                    allowed_sched_priority: 0
+                - #18
+                    host_id: 0
+                    allowed_atype: 0
+                    allowed_qos: 0
+                    allowed_orderid: 0
+                    allowed_priority: 0
+                    allowed_sched_priority: 0
+                - #19
+                    host_id: 0
+                    allowed_atype: 0
+                    allowed_qos: 0
+                    allowed_orderid: 0
+                    allowed_priority: 0
+                    allowed_sched_priority: 0
+                - #20
+                    host_id: 0
+                    allowed_atype: 0
+                    allowed_qos: 0
+                    allowed_orderid: 0
+                    allowed_priority: 0
+                    allowed_sched_priority: 0
+                - #21
+                    host_id: 0
+                    allowed_atype: 0
+                    allowed_qos: 0
+                    allowed_orderid: 0
+                    allowed_priority: 0
+                    allowed_sched_priority: 0
+                - #22
+                    host_id: 0
+                    allowed_atype: 0
+                    allowed_qos: 0
+                    allowed_orderid: 0
+                    allowed_priority: 0
+                    allowed_sched_priority: 0
+                - #23
+                    host_id: 0
+                    allowed_atype: 0
+                    allowed_qos: 0
+                    allowed_orderid: 0
+                    allowed_priority: 0
+                    allowed_sched_priority: 0
+                - #24
+                    host_id: 0
+                    allowed_atype: 0
+                    allowed_qos: 0
+                    allowed_orderid: 0
+                    allowed_priority: 0
+                    allowed_sched_priority: 0
+                - #25
+                    host_id: 0
+                    allowed_atype: 0
+                    allowed_qos: 0
+                    allowed_orderid: 0
+                    allowed_priority: 0
+                    allowed_sched_priority: 0
+                - #26
+                    host_id: 0
+                    allowed_atype: 0
+                    allowed_qos: 0
+                    allowed_orderid: 0
+                    allowed_priority: 0
+                    allowed_sched_priority: 0
+                - #27
+                    host_id: 0
+                    allowed_atype: 0
+                    allowed_qos: 0
+                    allowed_orderid: 0
+                    allowed_priority: 0
+                    allowed_sched_priority: 0
+                - #28
+                    host_id: 0
+                    allowed_atype: 0
+                    allowed_qos: 0
+                    allowed_orderid: 0
+                    allowed_priority: 0
+                    allowed_sched_priority: 0
+                - #29
+                    host_id: 0
+                    allowed_atype: 0
+                    allowed_qos: 0
+                    allowed_orderid: 0
+                    allowed_priority: 0
+                    allowed_sched_priority: 0
+                - #30
+                    host_id: 0
+                    allowed_atype: 0
+                    allowed_qos: 0
+                    allowed_orderid: 0
+                    allowed_priority: 0
+                    allowed_sched_priority: 0
+                - #31
+                    host_id: 0
+                    allowed_atype: 0
+                    allowed_qos: 0
+                    allowed_orderid: 0
+                    allowed_priority: 0
+                    allowed_sched_priority: 0
+                - #32
+                    host_id: 0
+                    allowed_atype: 0
+                    allowed_qos: 0
+                    allowed_orderid: 0
+                    allowed_priority: 0
+                    allowed_sched_priority: 0
+        resasg:
+            subhdr:
+                magic: 0x7B25
+                size: 8
+            resasg_entries_size: 992
+            reserved: 0
+    resasg_entries:
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+                reserved: 0
+        -
+                start_resource: 4096
+                num_resource: 32
+                type: 12828
+                host_id: 128
+                reserved: 0
diff --git a/board/comvetia/lxr2/lxr2.env b/board/comvetia/lxr2/lxr2.env
index ec213800222..26ad4f18c68 100644
--- a/board/comvetia/lxr2/lxr2.env
+++ b/board/comvetia/lxr2/lxr2.env
@@ -2,7 +2,6 @@ addcons=setenv bootargs ${bootargs} console=${console},${baudrate}
 addip=setenv bootargs ${bootargs} ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}:${netdev}:off
 addmisc=setenv bootargs ${bootargs} ${miscargs}
 addmtd=run mtdnand;run mtdspi;setenv bootargs ${bootargs} ${mtdparts}
-altbootcmd=run swupdate
 bootcmd=run nandboot;run swupdate
 bootcount=2
 bootlimit=3
diff --git a/board/coreboot/coreboot/MAINTAINERS b/board/coreboot/coreboot/MAINTAINERS
index d97383c030c..5166e7a762d 100644
--- a/board/coreboot/coreboot/MAINTAINERS
+++ b/board/coreboot/coreboot/MAINTAINERS
@@ -8,3 +8,8 @@ COREBOOT64 BOARD
 M:	Simon Glass <sjg@chromium.org>
 S:	Maintained
 F:	configs/coreboot64_defconfig
+
+COREBOOT64 NO SPL
+M:	Jeremy Compostella <jeremy.compostella@intel.com>
+S:	Maintained
+F:	configs/coreboot64-no-spl_defconfig
diff --git a/board/dhelectronics/dh_imx8mp/imx8mp_dhcom_pdk2.c b/board/dhelectronics/dh_imx8mp/imx8mp_dhcom_pdk2.c
index 4af3cbe9fe2..4275436b128 100644
--- a/board/dhelectronics/dh_imx8mp/imx8mp_dhcom_pdk2.c
+++ b/board/dhelectronics/dh_imx8mp/imx8mp_dhcom_pdk2.c
@@ -186,5 +186,7 @@ int board_late_init(void)
 
 enum env_location env_get_location(enum env_operation op, int prio)
 {
-	return prio ? ENVL_UNKNOWN : ENVL_SPI_FLASH;
+	return prio ? ENVL_UNKNOWN : CONFIG_IS_ENABLED(ENV_IS_IN_SPI_FLASH,
+						       (ENVL_SPI_FLASH),
+						       (ENVL_NOWHERE));
 }
diff --git a/board/emulation/qemu-riscv/Kconfig b/board/emulation/qemu-riscv/Kconfig
index 012ac14a123..134dbfd7151 100644
--- a/board/emulation/qemu-riscv/Kconfig
+++ b/board/emulation/qemu-riscv/Kconfig
@@ -62,6 +62,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	imply VIDEO_SIMPLE
 	imply PCIE_ECAM_GENERIC
 	imply DM_RNG
+	imply RNG_RISCV_ZKR
 	imply DM_RTC
 	imply RTC_GOLDFISH
 	imply SCSI
diff --git a/board/emulation/qemu-sbsa/Kconfig b/board/emulation/qemu-sbsa/Kconfig
index 72c76b351fa..9ea6303ec9c 100644
--- a/board/emulation/qemu-sbsa/Kconfig
+++ b/board/emulation/qemu-sbsa/Kconfig
@@ -30,9 +30,9 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select HAS_ROM
 	select MTD
 	select OF_LIBFDT_OVERLAY
-	select OF_SEPARATE
 	select PCI
 	select PCIE_ECAM_GENERIC
+	select SYS_PCI_64BIT
 	select USB
 	select GIC_V3
 	select GIC_V3_ITS
@@ -48,6 +48,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	imply CFI_FLASH
 	imply SYS_MTDPARTS_RUNTIME
 	imply SET_DFU_ALT_INFO
+	imply PCI_INIT_R
 
 if DEBUG_UART
 
diff --git a/board/gdsys/a38x/ihs_phys.c b/board/gdsys/a38x/ihs_phys.c
index 690a29690b9..d51301869cd 100644
--- a/board/gdsys/a38x/ihs_phys.c
+++ b/board/gdsys/a38x/ihs_phys.c
@@ -102,102 +102,6 @@ uint calculate_octo_phy_mask(void)
 	return octo_phy_mask;
 }
 
-int register_miiphy_bus(uint k, struct mii_dev **bus)
-{
-	int retval;
-	struct mii_dev *mdiodev = mdio_alloc();
-	char *name = bb_miiphy_buses[k].name;
-
-	if (!mdiodev)
-		return -ENOMEM;
-	strlcpy(mdiodev->name, name, MDIO_NAME_LEN);
-	mdiodev->read = bb_miiphy_read;
-	mdiodev->write = bb_miiphy_write;
-
-	retval = mdio_register(mdiodev);
-	if (retval < 0)
-		return retval;
-	*bus = miiphy_get_dev_by_name(name);
-
-	return 0;
-}
-
-struct porttype *get_porttype(uint octo_phy_mask, uint k)
-{
-	uint octo_index = k * 4;
-
-	if (!k) {
-		if (octo_phy_mask & 0x01)
-			return &porttypes[PORTTYPE_MAIN_CAT];
-		else if (!(octo_phy_mask & 0x03))
-			return &porttypes[PORTTYPE_16C_16F];
-	} else {
-		if (octo_phy_mask & (1 << octo_index))
-			return &porttypes[PORTTYPE_TOP_CAT];
-	}
-
-	return NULL;
-}
-
-int init_single_phy(struct porttype *porttype, struct mii_dev *bus,
-		    uint bus_idx, uint m, uint phy_idx)
-{
-	struct phy_device *phydev;
-
-	phydev = phy_find_by_mask(bus, BIT(m * 8 + phy_idx));
-	printf(" %u", bus_idx * 32 + m * 8 + phy_idx);
-
-	if (!phydev)
-		puts("!");
-	else
-		ihs_phy_config(phydev, porttype->phy_invert_in_pol,
-			       porttype->phy_invert_out_pol);
-
-	return 0;
-}
-
-int init_octo_phys(uint octo_phy_mask)
-{
-	uint bus_idx;
-
-	/* there are up to four octo-phys on each mdio bus */
-	for (bus_idx = 0; bus_idx < bb_miiphy_buses_num; ++bus_idx) {
-		uint m;
-		uint octo_index = bus_idx * 4;
-		struct mii_dev *bus = NULL;
-		struct porttype *porttype = NULL;
-		int ret;
-
-		porttype = get_porttype(octo_phy_mask, bus_idx);
-
-		if (!porttype)
-			continue;
-
-		for (m = 0; m < 4; ++m) {
-			uint phy_idx;
-
-			/**
-			 * Register a bus device if there is at least one phy
-			 * on the current bus
-			 */
-			if (!m && octo_phy_mask & (0xf << octo_index)) {
-				ret = register_miiphy_bus(bus_idx, &bus);
-				if (ret)
-					return ret;
-			}
-
-			if (!(octo_phy_mask & BIT(octo_index + m)))
-				continue;
-
-			for (phy_idx = 0; phy_idx < 8; ++phy_idx)
-				init_single_phy(porttype, bus, bus_idx, m,
-						phy_idx);
-		}
-	}
-
-	return 0;
-}
-
 /*
  * MII GPIO bitbang implementation
  * MDC MDIO bus
@@ -219,9 +123,9 @@ struct gpio_mii {
 	{ 2, {}, {}, 46, 24, 1 },
 };
 
-static int mii_mdio_init(struct bb_miiphy_bus *bus)
+static int mii_mdio_init(const int k)
 {
-	struct gpio_mii *gpio_mii = bus->priv;
+	struct gpio_mii *gpio_mii = &gpio_mii_set[k];
 	char name[32] = {};
 	struct udevice *gpio_dev1 = NULL;
 	struct udevice *gpio_dev2 = NULL;
@@ -260,27 +164,27 @@ static int mii_mdio_init(struct bb_miiphy_bus *bus)
 	return 0;
 }
 
-static int mii_mdio_active(struct bb_miiphy_bus *bus)
+static int mii_mdio_active(struct mii_dev *miidev)
 {
-	struct gpio_mii *gpio_mii = bus->priv;
+	struct gpio_mii *gpio_mii = miidev->priv;
 
 	dm_gpio_set_value(&gpio_mii->mdc_gpio, gpio_mii->mdio_value);
 
 	return 0;
 }
 
-static int mii_mdio_tristate(struct bb_miiphy_bus *bus)
+static int mii_mdio_tristate(struct mii_dev *miidev)
 {
-	struct gpio_mii *gpio_mii = bus->priv;
+	struct gpio_mii *gpio_mii = miidev->priv;
 
 	dm_gpio_set_dir_flags(&gpio_mii->mdio_gpio, GPIOD_IS_IN);
 
 	return 0;
 }
 
-static int mii_set_mdio(struct bb_miiphy_bus *bus, int v)
+static int mii_set_mdio(struct mii_dev *miidev, int v)
 {
-	struct gpio_mii *gpio_mii = bus->priv;
+	struct gpio_mii *gpio_mii = miidev->priv;
 
 	dm_gpio_set_dir_flags(&gpio_mii->mdio_gpio, GPIOD_IS_OUT);
 	dm_gpio_set_value(&gpio_mii->mdio_gpio, v);
@@ -289,9 +193,9 @@ static int mii_set_mdio(struct bb_miiphy_bus *bus, int v)
 	return 0;
 }
 
-static int mii_get_mdio(struct bb_miiphy_bus *bus, int *v)
+static int mii_get_mdio(struct mii_dev *miidev, int *v)
 {
-	struct gpio_mii *gpio_mii = bus->priv;
+	struct gpio_mii *gpio_mii = miidev->priv;
 
 	dm_gpio_set_dir_flags(&gpio_mii->mdio_gpio, GPIOD_IS_IN);
 	*v = (dm_gpio_get_value(&gpio_mii->mdio_gpio));
@@ -299,56 +203,135 @@ static int mii_get_mdio(struct bb_miiphy_bus *bus, int *v)
 	return 0;
 }
 
-static int mii_set_mdc(struct bb_miiphy_bus *bus, int v)
+static int mii_set_mdc(struct mii_dev *miidev, int v)
 {
-	struct gpio_mii *gpio_mii = bus->priv;
+	struct gpio_mii *gpio_mii = miidev->priv;
 
 	dm_gpio_set_value(&gpio_mii->mdc_gpio, v);
 
 	return 0;
 }
 
-static int mii_delay(struct bb_miiphy_bus *bus)
+static int mii_delay(struct mii_dev *miidev)
 {
 	udelay(1);
 
 	return 0;
 }
 
-struct bb_miiphy_bus bb_miiphy_buses[] = {
-	{
-		.name = "ihs0",
-		.init = mii_mdio_init,
-		.mdio_active = mii_mdio_active,
-		.mdio_tristate = mii_mdio_tristate,
-		.set_mdio = mii_set_mdio,
-		.get_mdio = mii_get_mdio,
-		.set_mdc = mii_set_mdc,
-		.delay = mii_delay,
-		.priv = &gpio_mii_set[0],
-	},
-	{
-		.name = "ihs1",
-		.init = mii_mdio_init,
-		.mdio_active = mii_mdio_active,
-		.mdio_tristate = mii_mdio_tristate,
-		.set_mdio = mii_set_mdio,
-		.get_mdio = mii_get_mdio,
-		.set_mdc = mii_set_mdc,
-		.delay = mii_delay,
-		.priv = &gpio_mii_set[1],
-	},
-	{
-		.name = "ihs2",
-		.init = mii_mdio_init,
-		.mdio_active = mii_mdio_active,
-		.mdio_tristate = mii_mdio_tristate,
-		.set_mdio = mii_set_mdio,
-		.get_mdio = mii_get_mdio,
-		.set_mdc = mii_set_mdc,
-		.delay = mii_delay,
-		.priv = &gpio_mii_set[2],
-	},
+static const struct bb_miiphy_bus_ops mii_bb_miiphy_bus_ops = {
+	.mdio_active	= mii_mdio_active,
+	.mdio_tristate	= mii_mdio_tristate,
+	.set_mdio	= mii_set_mdio,
+	.get_mdio	= mii_get_mdio,
+	.set_mdc	= mii_set_mdc,
+	.delay		= mii_delay,
 };
 
-int bb_miiphy_buses_num = ARRAY_SIZE(bb_miiphy_buses);
+static int mii_bb_miiphy_read(struct mii_dev *miidev, int addr,
+			      int devad, int reg)
+{
+	return bb_miiphy_read(miidev, &mii_bb_miiphy_bus_ops,
+			      addr, devad, reg);
+}
+
+static int mii_bb_miiphy_write(struct mii_dev *miidev, int addr,
+			       int devad, int reg, u16 value)
+{
+	return bb_miiphy_write(miidev, &mii_bb_miiphy_bus_ops,
+			       addr, devad, reg, value);
+}
+
+int register_miiphy_bus(uint k, struct mii_dev **bus)
+{
+	struct mii_dev *mdiodev = mdio_alloc();
+	int retval;
+
+	snprintf(mdiodev->name, MDIO_NAME_LEN, "ihs%d", k);
+	mdiodev->read = mii_bb_miiphy_read;
+	mdiodev->write = mii_bb_miiphy_write;
+	mdiodev->priv = &gpio_mii_set[k];
+
+	retval = mdio_register(mdiodev);
+	if (retval < 0)
+		return retval;
+	*bus = mdiodev;
+
+	return mii_mdio_init(k);
+}
+
+struct porttype *get_porttype(uint octo_phy_mask, uint k)
+{
+	uint octo_index = k * 4;
+
+	if (!k) {
+		if (octo_phy_mask & 0x01)
+			return &porttypes[PORTTYPE_MAIN_CAT];
+		else if (!(octo_phy_mask & 0x03))
+			return &porttypes[PORTTYPE_16C_16F];
+	} else {
+		if (octo_phy_mask & (1 << octo_index))
+			return &porttypes[PORTTYPE_TOP_CAT];
+	}
+
+	return NULL;
+}
+
+int init_single_phy(struct porttype *porttype, struct mii_dev *bus,
+		    uint bus_idx, uint m, uint phy_idx)
+{
+	struct phy_device *phydev;
+
+	phydev = phy_find_by_mask(bus, BIT(m * 8 + phy_idx));
+	printf(" %u", bus_idx * 32 + m * 8 + phy_idx);
+
+	if (!phydev)
+		puts("!");
+	else
+		ihs_phy_config(phydev, porttype->phy_invert_in_pol,
+			       porttype->phy_invert_out_pol);
+
+	return 0;
+}
+
+int init_octo_phys(uint octo_phy_mask)
+{
+	uint bus_idx;
+
+	/* there are up to four octo-phys on each mdio bus */
+	for (bus_idx = 0; bus_idx < ARRAY_SIZE(gpio_mii_set); ++bus_idx) {
+		uint m;
+		uint octo_index = bus_idx * 4;
+		struct mii_dev *bus = NULL;
+		struct porttype *porttype = NULL;
+		int ret;
+
+		porttype = get_porttype(octo_phy_mask, bus_idx);
+
+		if (!porttype)
+			continue;
+
+		for (m = 0; m < 4; ++m) {
+			uint phy_idx;
+
+			/**
+			 * Register a bus device if there is at least one phy
+			 * on the current bus
+			 */
+			if (!m && octo_phy_mask & (0xf << octo_index)) {
+				ret = register_miiphy_bus(bus_idx, &bus);
+				if (ret)
+					return ret;
+			}
+
+			if (!(octo_phy_mask & BIT(octo_index + m)))
+				continue;
+
+			for (phy_idx = 0; phy_idx < 8; ++phy_idx)
+				init_single_phy(porttype, bus, bus_idx, m,
+						phy_idx);
+		}
+	}
+
+	return 0;
+}
diff --git a/board/intel/agilex5-socdk/MAINTAINERS b/board/intel/agilex5-socdk/MAINTAINERS
index b696f788c81..30d8815d202 100644
--- a/board/intel/agilex5-socdk/MAINTAINERS
+++ b/board/intel/agilex5-socdk/MAINTAINERS
@@ -2,7 +2,9 @@ SOCFPGA BOARD
 M:	Tien Fong Chee <tien.fong.chee@intel.com>
 M:	Teik Heng Chong <teik.heng.chong@intel.com>
 M:	Jit Loon Lim <jit.loon.lim@intel.com>
+M:	Dinesh Maniyam <dinesh.maniyam@intel.com>
 S:	Maintained
 F:	board/intel/agilex5-socdk/
 F:	include/configs/socfpga_agilex5_socdk.h
 F:	configs/socfpga_agilex5_defconfig
+F:	configs/socfpga_agilex5_nand2_defconfig
diff --git a/board/intel/agilex5-socdk/Makefile b/board/intel/agilex5-socdk/Makefile
new file mode 100644
index 00000000000..306a8cf5f0b
--- /dev/null
+++ b/board/intel/agilex5-socdk/Makefile
@@ -0,0 +1,7 @@
+#
+# Copyright (C) 2025 Altera Corporation <www.altera.com>
+#
+# SPDX-License-Identifier:	GPL-2.0
+#
+
+obj-y	:= socfpga.o
diff --git a/board/intel/agilex5-socdk/socfpga.c b/board/intel/agilex5-socdk/socfpga.c
new file mode 100644
index 00000000000..d6628cfc696
--- /dev/null
+++ b/board/intel/agilex5-socdk/socfpga.c
@@ -0,0 +1,12 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2025 Altera Corporation <www.altera.com>
+ */
+
+#include <asm/arch/misc.h>
+
+int board_early_init_f(void)
+{
+	socfpga_get_sys_mgr_addr("sysmgr@10d12000");
+	return 0;
+}
diff --git a/board/keymile/scripts/develop-common.txt b/board/keymile/scripts/develop-common.txt
index 1bdff2f908f..cfc69357e43 100644
--- a/board/keymile/scripts/develop-common.txt
+++ b/board/keymile/scripts/develop-common.txt
@@ -1,4 +1,3 @@
-altbootcmd=run ${subbootcmds}
 bootcmd=run ${subbootcmds}
 configure=run set_uimage; run set_tftppath; km_setboardid && run try_import_nfs_path && saveenv && reset
 subbootcmds=tftpfdt tftpkernel nfsargs add_default boot
diff --git a/board/keymile/scripts/ramfs-common.txt b/board/keymile/scripts/ramfs-common.txt
index 0a4a9c80b7e..c86e6267bdc 100644
--- a/board/keymile/scripts/ramfs-common.txt
+++ b/board/keymile/scripts/ramfs-common.txt
@@ -1,6 +1,5 @@
 addramfs=setenv bootargs "${bootargs} phram.phram=rootfs${boot_bank},${rootfsaddr},${rootfssize}"
 boot_bank=-1
-altbootcmd=run ${subbootcmds}
 bootcmd=run ${subbootcmds}
 subbootcmds=save_and_reset_once tftpfdt tftpkernel setrootfsaddr tftpramfs flashargs add_default addpanic addramfs boot
 save_and_reset_once=setenv save_and_reset_once true && saveenv && reset
diff --git a/board/keymile/secu1/socfpga_secu.env b/board/keymile/secu1/socfpga_secu.env
index 147c4170ef5..60999882958 100644
--- a/board/keymile/secu1/socfpga_secu.env
+++ b/board/keymile/secu1/socfpga_secu.env
@@ -1,4 +1,3 @@
-altbootcmd=run bootcmd;
 bootlimit=6
 bootnum=1
 bootretry=CONFIG_BOOT_RETRY_TIME
diff --git a/board/nuvoton/arbel_evb/arbel_evb.c b/board/nuvoton/arbel_evb/arbel_evb.c
index 55e93a77f0f..699e5ca54a7 100644
--- a/board/nuvoton/arbel_evb/arbel_evb.c
+++ b/board/nuvoton/arbel_evb/arbel_evb.c
@@ -4,6 +4,7 @@
  */
 
 #include <dm.h>
+#include <event.h>
 #include <asm/io.h>
 #include <asm/arch/gcr.h>
 #include "../common/uart.h"
@@ -98,9 +99,5 @@ int dram_init_banksize(void)
 	return 0;
 }
 
-int last_stage_init(void)
-{
-	board_set_console();
+EVENT_SPY_SIMPLE(EVT_LAST_STAGE_INIT, board_set_console);
 
-	return 0;
-}
diff --git a/board/nuvoton/common/uart.c b/board/nuvoton/common/uart.c
index b35c795704a..06f637855f5 100644
--- a/board/nuvoton/common/uart.c
+++ b/board/nuvoton/common/uart.c
@@ -14,7 +14,7 @@
 #define UART_LCR	0xc
 #define LCR_DLAB	BIT(7)
 
-void board_set_console(void)
+int board_set_console(void)
 {
 	const unsigned long baudrate_table[] = CFG_SYS_BAUDRATE_TABLE;
 	struct udevice *dev = gd->cur_serial_dev;
@@ -28,12 +28,12 @@ void board_set_console(void)
 	int ret, i;
 
 	if (!dev)
-		return;
+		return -ENODEV;
 
 	uart_reg = dev_read_addr_ptr(dev);
 	ret = clk_get_by_index(dev, 0, &clk);
 	if (ret)
-		return;
+		return ret;
 
 	uart_clk = clk_get_rate(&clk);
 	setbits_8(uart_reg + UART_LCR, LCR_DLAB);
@@ -67,4 +67,5 @@ void board_set_console(void)
 	snprintf(string, sizeof(string), "ttyS0,%un8", gd->baudrate);
 	env_set("console", string);
 
+	return 0;
 }
diff --git a/board/nuvoton/common/uart.h b/board/nuvoton/common/uart.h
index 9cc895251b3..fc8ec477c8b 100644
--- a/board/nuvoton/common/uart.h
+++ b/board/nuvoton/common/uart.h
@@ -6,6 +6,6 @@
 #ifndef _NUVOTON_UART_H
 #define _NUVOTON_UART_H
 
-void board_set_console(void);
+int board_set_console(void);
 
 #endif /* _NUVOTON_COMMON_H */
diff --git a/board/nuvoton/poleg_evb/poleg_evb.c b/board/nuvoton/poleg_evb/poleg_evb.c
index 3c4e5aaf294..2faa34954eb 100644
--- a/board/nuvoton/poleg_evb/poleg_evb.c
+++ b/board/nuvoton/poleg_evb/poleg_evb.c
@@ -6,6 +6,7 @@
 
 #include <dm.h>
 #include <env.h>
+#include <event.h>
 #include <asm/io.h>
 #include <asm/arch/gcr.h>
 #include <asm/mach-types.h>
@@ -48,7 +49,7 @@ int dram_init(void)
 	return 0;
 }
 
-int last_stage_init(void)
+static int last_stage_init(void)
 {
 
 	char value[32];
@@ -68,8 +69,10 @@ int last_stage_init(void)
 		}
 		sprintf(value, "ttyS%d,115200n8", dev->seq_);
 		env_set("console", value);
-		board_set_console();
+		return board_set_console();
 	}
 
 	return 0;
 }
+EVENT_SPY_SIMPLE(EVT_LAST_STAGE_INIT, last_stage_init);
+
diff --git a/board/ouya/ouya/Kconfig b/board/ouya/ouya/Kconfig
new file mode 100644
index 00000000000..6bab40ce933
--- /dev/null
+++ b/board/ouya/ouya/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_OUYA
+
+config SYS_BOARD
+	default "ouya"
+
+config SYS_VENDOR
+	default "ouya"
+
+config SYS_CONFIG_NAME
+	default "ouya"
+
+endif
diff --git a/board/ouya/ouya/MAINTAINERS b/board/ouya/ouya/MAINTAINERS
new file mode 100644
index 00000000000..7f664b2e65f
--- /dev/null
+++ b/board/ouya/ouya/MAINTAINERS
@@ -0,0 +1,8 @@
+OUYA BOARD
+M:	Svyatoslav Ryhel <clamor95@gmail.com>
+M:	Peter Geis <pgwipeout@gmail.com>
+S:	Maintained
+F:	board/ouya/ouya/
+F:	configs/ouya_defconfig
+F:	doc/board/ouya/ouya.rst
+F:	include/configs/ouya.h
diff --git a/board/ouya/ouya/Makefile b/board/ouya/ouya/Makefile
new file mode 100644
index 00000000000..d479ec83e5e
--- /dev/null
+++ b/board/ouya/ouya/Makefile
@@ -0,0 +1,11 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+#  (C) Copyright 2010-2012
+#  NVIDIA Corporation <www.nvidia.com>
+#
+#  (C) Copyright 2021
+#  Svyatoslav Ryhel <clamor95@gmail.com>
+
+obj-$(CONFIG_XPL_BUILD) += ouya-spl.o
+
+obj-y += ouya.o
diff --git a/board/ouya/ouya/ouya-spl.c b/board/ouya/ouya/ouya-spl.c
new file mode 100644
index 00000000000..1f45853c8be
--- /dev/null
+++ b/board/ouya/ouya/ouya-spl.c
@@ -0,0 +1,41 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ *  T30 Ouya SPL stage configuration
+ *
+ *  (C) Copyright 2010-2013
+ *  NVIDIA Corporation <www.nvidia.com>
+ *
+ *  (C) Copyright 2025
+ *  Svyatoslav Ryhel <clamor95@gmail.com>
+ */
+
+#include <asm/arch/tegra.h>
+#include <asm/arch-tegra/tegra_i2c.h>
+#include <linux/delay.h>
+
+#define TPS65911_I2C_ADDR		(0x2D << 1)
+#define TPS65911_VDDCTRL_OP_REG		0x28
+#define TPS65911_VDDCTRL_SR_REG		0x27
+#define TPS65911_VDDCTRL_OP_DATA	(0x2400 | TPS65911_VDDCTRL_OP_REG)
+#define TPS65911_VDDCTRL_SR_DATA	(0x0100 | TPS65911_VDDCTRL_SR_REG)
+
+#define TPS62361B_I2C_ADDR		(0x60 << 1)
+#define TPS62361B_SET3_REG		0x03
+#define TPS62361B_SET3_DATA		(0x4600 | TPS62361B_SET3_REG)
+
+void pmic_enable_cpu_vdd(void)
+{
+	/* Set VDD_CORE to 1.200V. */
+	tegra_i2c_ll_write(TPS62361B_I2C_ADDR, TPS62361B_SET3_DATA);
+
+	udelay(1000);
+
+	/*
+	 * Bring up CPU VDD via the TPS65911x PMIC on the DVC I2C bus.
+	 * First set VDD to 1.0125V, then enable the VDD regulator.
+	 */
+	tegra_i2c_ll_write(TPS65911_I2C_ADDR, TPS65911_VDDCTRL_OP_DATA);
+	udelay(1000);
+	tegra_i2c_ll_write(TPS65911_I2C_ADDR, TPS65911_VDDCTRL_SR_DATA);
+	udelay(10 * 1000);
+}
diff --git a/board/ouya/ouya/ouya.c b/board/ouya/ouya/ouya.c
new file mode 100644
index 00000000000..6d6eb54afe2
--- /dev/null
+++ b/board/ouya/ouya/ouya.c
@@ -0,0 +1,21 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ *  (C) Copyright 2010-2013
+ *  NVIDIA Corporation <www.nvidia.com>
+ *
+ *  (C) Copyright 2025
+ *  Svyatoslav Ryhel <clamor95@gmail.com>
+ */
+
+#include <fdt_support.h>
+
+#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+	/* Remove TrustZone nodes */
+	fdt_del_node_and_alias(blob, "/firmware");
+	fdt_del_node_and_alias(blob, "/reserved-memory/trustzone@bfe00000");
+
+	return 0;
+}
+#endif
diff --git a/board/ouya/ouya/ouya.env b/board/ouya/ouya/ouya.env
new file mode 100644
index 00000000000..6ec881b910a
--- /dev/null
+++ b/board/ouya/ouya/ouya.env
@@ -0,0 +1,12 @@
+#include <env/nvidia/prod_upd.env>
+
+partitions=name=emmc,start=0,size=-,uuid=${uuid_gpt_rootfs}
+boot_interface=usb
+
+bootmenu_0=mount internal storage=usb start && ums 0 mmc 0; bootmenu
+bootmenu_1=fastboot=echo Starting Fastboot protocol ...; fastboot usb 0; bootmenu
+bootmenu_2=update bootloader=run flash_uboot
+bootmenu_3=reboot RCM=enterrcm
+bootmenu_4=reboot=reset
+bootmenu_5=power off=poweroff
+bootmenu_delay=-1
diff --git a/board/phytec/common/Kconfig b/board/phytec/common/Kconfig
index bc5511707ac..65451a3b20d 100644
--- a/board/phytec/common/Kconfig
+++ b/board/phytec/common/Kconfig
@@ -38,6 +38,17 @@ config PHYTEC_AM62_SOM_DETECTION
 	   Support of I2C EEPROM based SoM detection. Supported
 	   for PHYTEC AM62x boards.
 
+config PHYTEC_AM62A_SOM_DETECTION
+	bool "Support SoM detection for AM62Ax PHYTEC platforms"
+	depends on (TARGET_PHYCORE_AM62AX_A53 || TARGET_PHYCORE_AM62AX_R5) && \
+		   PHYTEC_SOM_DETECTION
+	select SUPPORT_EXTENSION_SCAN
+	depends on SPL_I2C && DM_I2C
+	default y
+	help
+	   Support of I2C EEPROM based SoM detection. Supported
+	   for PHYTEC AM62Ax boards.
+
 config PHYTEC_AM64_SOM_DETECTION
 	bool "Support SoM detection for AM64x PHYTEC platforms"
 	depends on (TARGET_PHYCORE_AM64X_A53 || TARGET_PHYCORE_AM64X_R5) && \
diff --git a/board/phytec/common/am6_som_detection.c b/board/phytec/common/am6_som_detection.c
index 7930ab42d1c..f5de5de4821 100644
--- a/board/phytec/common/am6_som_detection.c
+++ b/board/phytec/common/am6_som_detection.c
@@ -11,10 +11,12 @@
 extern struct phytec_eeprom_data eeprom_data;
 
 #if IS_ENABLED(CONFIG_PHYTEC_AM62_SOM_DETECTION) || \
+	IS_ENABLED(CONFIG_PHYTEC_AM62A_SOM_DETECTION) || \
 	IS_ENABLED(CONFIG_PHYTEC_AM64_SOM_DETECTION)
 
 /* Check if the SoM is actually one of the following products:
  * - phyCORE-AM62x
+ * - phyCORE-AM62Ax
  * - phyCORE-AM64x
  *
  * Returns 0 in case it's a known SoM. Otherwise, returns -1.
@@ -41,6 +43,9 @@ int phytec_am6_detect(struct phytec_eeprom_data *data)
 	if (som == PHYTEC_AM62X_SOM && soc_is_am62x())
 		return 0;
 
+	if (som == PHYTEC_AM62AX_SOM && soc_is_am62ax())
+		return 0;
+
 	if (som == PHYTEC_AM64X_SOM && soc_is_am64x())
 		return 0;
 
diff --git a/board/phytec/common/am6_som_detection.h b/board/phytec/common/am6_som_detection.h
index c5c6e179da6..0b3c9c8e1ee 100644
--- a/board/phytec/common/am6_som_detection.h
+++ b/board/phytec/common/am6_som_detection.h
@@ -11,6 +11,7 @@
 
 #define EEPROM_ADDR				0x50
 #define PHYTEC_AM62X_SOM			71
+#define PHYTEC_AM62AX_SOM			75
 #define PHYTEC_AM64X_SOM			72
 #define PHYTEC_EEPROM_VALUE_X			0x21
 #define PHYTEC_EEPROM_NOR_FLASH_64MB_QSPI	0xC
diff --git a/board/phytec/common/k3/board.c b/board/phytec/common/k3/board.c
index 9d833456810..7d2146d5727 100644
--- a/board/phytec/common/k3/board.c
+++ b/board/phytec/common/k3/board.c
@@ -48,7 +48,7 @@ struct efi_capsule_update_info update_info = {
  * Note: Currently, eMMC hardware partitions are not differentiated; Updates
  * are always applied to the first boot partition.
  */
-void configure_capsule_updates(void)
+static void configure_capsule_updates(void)
 {
 	static char dfu_string[128] = { 0 };
 	const char *dfu_raw = "tiboot3.bin raw 0x0 0x400 mmcpart 1;"
diff --git a/board/phytec/phycore_am62ax/MAINTAINERS b/board/phytec/phycore_am62ax/MAINTAINERS
index 3e4e2feff4e..7c8a29b20d9 100644
--- a/board/phytec/phycore_am62ax/MAINTAINERS
+++ b/board/phytec/phycore_am62ax/MAINTAINERS
@@ -10,5 +10,6 @@ F:	arch/arm/dts/k3-am62a7-r5-phycore-som-2gb.dts
 F:	board/phytec/phycore_am62ax/
 F:	configs/phycore_am62ax_a53_defconfig
 F:	configs/phycore_am62ax_r5_defconfig
+F:	configs/phycore_am62ax_r5_usbdfu_defconfig
 F:	include/configs/phycore_am62ax.h
 F:	doc/board/phytec/phycore-am62ax.rst
diff --git a/board/phytec/phycore_am62ax/phycore_am62ax.env b/board/phytec/phycore_am62ax/phycore_am62ax.env
index 77c5ea8d99a..a0eacd1dfc3 100644
--- a/board/phytec/phycore_am62ax/phycore_am62ax.env
+++ b/board/phytec/phycore_am62ax/phycore_am62ax.env
@@ -1,3 +1,8 @@
+#include <env/phytec/k3_dfu.env>
+#include <env/phytec/k3_mmc.env>
+#include <env/phytec/k3_net.env>
+#include <env/phytec/k3_spi.env>
+
 fdtaddr=0x88000000
 loadaddr=0x82000000
 scriptaddr=0x80000000
@@ -12,3 +17,9 @@ mmcroot=2
 mmcpart=1
 console=ttyS2,115200n8
 earlycon=ns16550a,mmio32,0x02800000
+
+get_cmd=tftp
+
+spi_fdt_addr=0x700000
+spi_image_addr=0x800000
+spi_ramdisk_addr=0x1e00000
diff --git a/board/phytec/phycore_am62x/MAINTAINERS b/board/phytec/phycore_am62x/MAINTAINERS
index 670c7473481..8f2b8069ad4 100644
--- a/board/phytec/phycore_am62x/MAINTAINERS
+++ b/board/phytec/phycore_am62x/MAINTAINERS
@@ -12,4 +12,5 @@ F:	configs/phycore_am62x_r5_defconfig
 F:	configs/phycore_am62x_r5_usbdfu_defconfig
 F:	include/configs/phycore_am62x.h
 F:	doc/board/phytec/phycore-am62x.rst
+F:	doc/board/phytec/k3-common.rst
 F:	board/phytec/common/k3
diff --git a/board/phytec/phycore_am62x/phycore_am62x.env b/board/phytec/phycore_am62x/phycore_am62x.env
index 711ca3040c4..5c48e856685 100644
--- a/board/phytec/phycore_am62x/phycore_am62x.env
+++ b/board/phytec/phycore_am62x/phycore_am62x.env
@@ -1,4 +1,4 @@
-#include <env/ti/k3_dfu.env>
+#include <env/phytec/k3_dfu.env>
 #include <env/phytec/k3_mmc.env>
 #include <env/phytec/k3_net.env>
 #include <env/phytec/k3_spi.env>
@@ -22,4 +22,4 @@ get_cmd=tftp
 
 spi_fdt_addr=0x700000
 spi_image_addr=0x800000
-spi_ramdisk_addr=0x1e00000
+spi_ramdisk_addr=0x2200000
diff --git a/board/phytec/phycore_am64x/phycore_am64x.env b/board/phytec/phycore_am64x/phycore_am64x.env
index 3032b518e0b..d69dfe75674 100644
--- a/board/phytec/phycore_am64x/phycore_am64x.env
+++ b/board/phytec/phycore_am64x/phycore_am64x.env
@@ -21,4 +21,4 @@ get_cmd=tftp
 
 spi_fdt_addr=0x700000
 spi_image_addr=0x800000
-spi_ramdisk_addr=0x1e00000
+spi_ramdisk_addr=0x2200000
diff --git a/board/phytec/phycore_imx8mp/Kconfig b/board/phytec/phycore_imx8mp/Kconfig
index bdf9e97beaa..caf9cb0c3c3 100644
--- a/board/phytec/phycore_imx8mp/Kconfig
+++ b/board/phytec/phycore_imx8mp/Kconfig
@@ -45,7 +45,6 @@ config PHYCORE_IMX8MP_RAM_SIZE_4GB
 
 config PHYCORE_IMX8MP_RAM_SIZE_8GB
 	bool "8GB RAM"
-	select PHYCORE_IMX8MP_USE_2GHZ_RAM_TIMINGS
 	help
 	  Set RAM size fix to 8GB for phyCORE-i.MX8MP.
 	  Only 2GHz RAMs are supported.
@@ -54,7 +53,6 @@ endchoice
 
 config PHYCORE_IMX8MP_RAM_FREQ_FIX
 	bool "Set phyCORE-i.MX8MP RAM frequency fix instead of detecting"
-	default false
 	help
 	  RAM frequency is automatic being detected with the help of
 	  the EEPROM introspection data. Set RAM frequency to a fix value
diff --git a/board/siemens/common/Kconfig b/board/siemens/common/Kconfig
index 4ae12b1c973..3808257cd07 100644
--- a/board/siemens/common/Kconfig
+++ b/board/siemens/common/Kconfig
@@ -3,4 +3,5 @@ config FACTORYSET
 
 config DDR_SI_TEST
 	bool "DDR signal integrity test implementations"
+	depends on TARGET_CAPRICORN
 	default y
diff --git a/board/siemens/iot2050/board.c b/board/siemens/iot2050/board.c
index e6bedc38917..d827f728a08 100644
--- a/board/siemens/iot2050/board.c
+++ b/board/siemens/iot2050/board.c
@@ -25,28 +25,7 @@
 #include <asm/gpio.h>
 #include <asm/io.h>
 
-#define IOT2050_INFO_MAGIC		0x20502050
-
-struct iot2050_info {
-	u32 magic;
-	u16 size;
-	char name[20 + 1];
-	char serial[16 + 1];
-	char mlfb[18 + 1];
-	char uuid[32 + 1];
-	char a5e[18 + 1];
-	u8 mac_addr_cnt;
-	u8 mac_addr[8][ARP_HLEN];
-	char seboot_version[40 + 1];
-	u8 padding[3];
-	u32 ddr_size_mb;
-} __packed;
-
-/*
- * Scratch SRAM (available before DDR RAM) contains extracted EEPROM data.
- */
-#define IOT2050_INFO_DATA ((struct iot2050_info *) \
-			     TI_SRAM_SCRATCH_BOARD_EEPROM_START)
+#include "../../../../drivers/sysinfo/iot2050.h"
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -117,6 +96,8 @@ static const char *m2_connector_mode_name[] = {
 
 static enum m2_connector_mode connector_mode;
 
+static char iot2050_board_name[21];
+
 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
 static void *connector_overlay;
 static u32 connector_overlay_size;
@@ -149,37 +130,57 @@ static void set_pinvalue(const char *gpio_name, const char *label, int value)
 	dm_gpio_set_value(&gpio, value);
 }
 
+static bool setup_sysinfo(struct udevice **sysinfo_ptr)
+{
+	if (sysinfo_get(sysinfo_ptr)) {
+		pr_err("Could not find sysinfo device.\n");
+		return false;
+	}
+	if (sysinfo_detect(*sysinfo_ptr)) {
+		pr_err("Board info parsing error\n");
+		return false;
+	}
+	return true;
+}
+
+static void get_board_name(void)
+{
+	struct udevice *sysinfo;
+
+	if (iot2050_board_name[0] != 0)
+		return;
+
+	if (!setup_sysinfo(&sysinfo))
+		return;
+
+	sysinfo_get_str(sysinfo, BOARD_NAME, sizeof(iot2050_board_name),
+			iot2050_board_name);
+}
+
 static bool board_is_advanced(void)
 {
-	struct iot2050_info *info = IOT2050_INFO_DATA;
 
-	return info->magic == IOT2050_INFO_MAGIC &&
-		strstr((char *)info->name, "IOT2050-ADVANCED") != NULL;
+	get_board_name();
+	return strstr(iot2050_board_name, "IOT2050-ADVANCED") != NULL;
 }
 
 static bool board_is_pg1(void)
 {
-	struct iot2050_info *info = IOT2050_INFO_DATA;
-
-	return info->magic == IOT2050_INFO_MAGIC &&
-		(strcmp((char *)info->name, "IOT2050-BASIC") == 0 ||
-		 strcmp((char *)info->name, "IOT2050-ADVANCED") == 0);
+	get_board_name();
+	return strcmp(iot2050_board_name, "IOT2050-BASIC") == 0 ||
+	       strcmp(iot2050_board_name, "IOT2050-ADVANCED") == 0;
 }
 
 static bool board_is_m2(void)
 {
-	struct iot2050_info *info = IOT2050_INFO_DATA;
-
-	return info->magic == IOT2050_INFO_MAGIC &&
-		strcmp((char *)info->name, "IOT2050-ADVANCED-M2") == 0;
+	get_board_name();
+	return strcmp(iot2050_board_name, "IOT2050-ADVANCED-M2") == 0;
 }
 
 static bool board_is_sm(void)
 {
-	struct iot2050_info *info = IOT2050_INFO_DATA;
-
-	return info->magic == IOT2050_INFO_MAGIC &&
-		strcmp((char *)info->name, "IOT2050-ADVANCED-SM") == 0;
+	get_board_name();
+	return strcmp(iot2050_board_name, "IOT2050-ADVANCED-SM") == 0;
 }
 
 static void remove_mmc1_target(void)
@@ -206,33 +207,43 @@ static void enable_pcie_connector_power(void)
 
 void set_board_info_env(void)
 {
-	struct iot2050_info *info = IOT2050_INFO_DATA;
-	u8 __maybe_unused mac_cnt;
+	struct udevice *sysinfo;
 	const char *fdtfile;
+	char buf[41];
 
-	if (info->magic != IOT2050_INFO_MAGIC) {
-		pr_err("IOT2050: Board info parsing error!\n");
+	if (env_get("board_uuid"))
 		return;
-	}
 
-	if (env_get("board_uuid"))
+	if (!setup_sysinfo(&sysinfo))
 		return;
 
-	env_set("board_name", info->name);
-	env_set("board_serial", info->serial);
-	env_set("mlfb", info->mlfb);
-	env_set("board_uuid", info->uuid);
-	env_set("board_a5e", info->a5e);
+	if (sysinfo_get_str(sysinfo, BOARD_NAME, sizeof(buf), buf) == 0)
+		env_set("board_name", buf);
+	if (sysinfo_get_str(sysinfo, SYSID_SM_SYSTEM_SERIAL, sizeof(buf), buf) == 0)
+		env_set("board_serial", buf);
+	if (sysinfo_get_str(sysinfo, BOARD_MLFB, sizeof(buf), buf) == 0)
+		env_set("mlfb", buf);
+	if (sysinfo_get_str(sysinfo, BOARD_UUID, sizeof(buf), buf) == 0)
+		env_set("board_uuid", buf);
+	if (sysinfo_get_str(sysinfo, BOARD_A5E, sizeof(buf), buf) == 0)
+		env_set("board_a5e", buf);
+	if (sysinfo_get_str(sysinfo, BOARD_SEBOOT_VER, sizeof(buf), buf) == 0)
+		env_set("seboot_version", buf);
 	env_set("fw_version", PLAIN_VERSION);
-	env_set("seboot_version", info->seboot_version);
 
 	if (IS_ENABLED(CONFIG_NET)) {
+		int mac_cnt;
+
+		mac_cnt = sysinfo_get_item_count(sysinfo, SYSID_BOARD_MAC_ADDR);
 		/* set MAC addresses to ensure forwarding to the OS */
-		for (mac_cnt = 0; mac_cnt < info->mac_addr_cnt; mac_cnt++) {
-			if (is_valid_ethaddr(info->mac_addr[mac_cnt]))
-				eth_env_set_enetaddr_by_index("eth",
-							      mac_cnt + 1,
-							      info->mac_addr[mac_cnt]);
+		for (int i = 0; i < mac_cnt; i++) {
+			u8 *mac = NULL;
+			size_t bytes = 0;
+
+			sysinfo_get_data_by_index(sysinfo, SYSID_BOARD_MAC_ADDR,
+						  i, (void **)&mac, &bytes);
+			if (bytes == ARP_HLEN && is_valid_ethaddr(mac))
+				eth_env_set_enetaddr_by_index("eth", i + 1, mac);
 		}
 	}
 
@@ -288,7 +299,7 @@ static void do_overlay_prepare(const char *overlay_path)
 	return;
 
 fit_error:
-	pr_err("M.2 device tree overlay %s not available,\n", overlay_path);
+	pr_err("M.2 device tree overlay %s not available.\n", overlay_path);
 #endif
 }
 
@@ -362,8 +373,15 @@ int board_init(void)
 
 int dram_init(void)
 {
-	struct iot2050_info *info = IOT2050_INFO_DATA;
-	gd->ram_size = ((phys_size_t)(info->ddr_size_mb)) << 20;
+	struct udevice *sysinfo;
+	u32 ddr_size_mb;
+
+	if (!setup_sysinfo(&sysinfo))
+		return -ENODEV;
+
+	sysinfo_get_int(sysinfo, SYSID_BOARD_RAM_SIZE_MB, &ddr_size_mb);
+
+	gd->ram_size = ((phys_size_t)(ddr_size_mb)) << 20;
 
 	return 0;
 }
@@ -405,18 +423,18 @@ int dram_init_banksize(void)
 #ifdef CONFIG_SPL_LOAD_FIT
 int board_fit_config_name_match(const char *name)
 {
-	struct iot2050_info *info = IOT2050_INFO_DATA;
 	char upper_name[32];
 
+	get_board_name();
+
 	/* skip the prefix "ti/k3-am65x8-" */
 	name += 13;
 
-	if (info->magic != IOT2050_INFO_MAGIC ||
-	    strlen(name) >= sizeof(upper_name))
+	if (strlen(name) >= sizeof(upper_name))
 		return -1;
 
 	str_to_upper(name, upper_name, sizeof(upper_name));
-	if (!strcmp(upper_name, (char *)info->name))
+	if (!strcmp(upper_name, iot2050_board_name))
 		return 0;
 
 	return -1;
diff --git a/board/st/stm32f746-disco/MAINTAINERS b/board/st/stm32f746-disco/MAINTAINERS
index 18e4c99c4fb..f9c3af6fb8b 100644
--- a/board/st/stm32f746-disco/MAINTAINERS
+++ b/board/st/stm32f746-disco/MAINTAINERS
@@ -1,5 +1,5 @@
 STM32F746 DISCOVERY BOARD
-M:	Vikas Manocha <vikas.manocha@st.com>
+M:	Patrice Chotard <patrice.chotard@foss.st.com>
 S:	Maintained
 F:	doc/board/st/
 F:	board/st/stm32f746-disco
diff --git a/board/st/stm32f746-disco/stm32f746-disco.c b/board/st/stm32f746-disco/stm32f746-disco.c
index 8966a09501e..07bc8a5f0a2 100644
--- a/board/st/stm32f746-disco/stm32f746-disco.c
+++ b/board/st/stm32f746-disco/stm32f746-disco.c
@@ -76,42 +76,6 @@ u32 spl_boot_device(void)
 }
 #endif
 
-int board_late_init(void)
-{
-	struct gpio_desc gpio = {};
-	int node;
-
-	node = fdt_node_offset_by_compatible(gd->fdt_blob, 0, "st,led1");
-	if (node < 0)
-		return -1;
-
-	gpio_request_by_name_nodev(offset_to_ofnode(node), "led-gpio", 0, &gpio,
-				   GPIOD_IS_OUT);
-
-	if (dm_gpio_is_valid(&gpio)) {
-		dm_gpio_set_value(&gpio, 0);
-		mdelay(10);
-		dm_gpio_set_value(&gpio, 1);
-	}
-
-	/* read button 1*/
-	node = fdt_node_offset_by_compatible(gd->fdt_blob, 0, "st,button1");
-	if (node < 0)
-		return -1;
-
-	gpio_request_by_name_nodev(offset_to_ofnode(node), "button-gpio", 0,
-				   &gpio, GPIOD_IS_IN);
-
-	if (dm_gpio_is_valid(&gpio)) {
-		if (dm_gpio_get_value(&gpio))
-			puts("usr button is at HIGH LEVEL\n");
-		else
-			puts("usr button is at LOW LEVEL\n");
-	}
-
-	return 0;
-}
-
 int board_init(void)
 {
 #ifdef CONFIG_ETH_DESIGNWARE
diff --git a/board/starfive/visionfive2/spl.c b/board/starfive/visionfive2/spl.c
index f41bd6d603f..3e4d3e21988 100644
--- a/board/starfive/visionfive2/spl.c
+++ b/board/starfive/visionfive2/spl.c
@@ -103,6 +103,9 @@ void board_init_f(ulong dummy)
 			JH7110_CLK_CPU_ROOT_MASK,
 			BIT(JH7110_CLK_CPU_ROOT_SHIFT));
 
+	/* Set USB overcurrent overflow pin disable */
+	SYS_IOMUX_DIN_DISABLED(2);
+
 	ret = spl_board_init_f();
 	if (ret) {
 		debug("spl_board_init_f init failed: %d\n", ret);
@@ -118,6 +121,10 @@ int board_fit_config_name_match(const char *name)
 
 	product_id = get_product_id_from_eeprom();
 
+	/* Strip off prefix */
+	if (strncmp(name, "starfive/", 9))
+		return -EINVAL;
+	name += 9;
 	if (!strncmp(product_id, "VF7110", 6)) {
 		version = get_pcb_revision_from_eeprom();
 		if ((version == 'b' || version == 'B') &&
diff --git a/board/storopack/smegw01/smegw01.env b/board/storopack/smegw01/smegw01.env
index 93de8669109..c0d408e4a20 100644
--- a/board/storopack/smegw01/smegw01.env
+++ b/board/storopack/smegw01/smegw01.env
@@ -12,21 +12,6 @@
 			setenv bootmenu_${emmc_priority} eMMC=run boot_emmc; \
 			setenv bootmenu_${sd_priority} SD=run boot_sd;
 #endif
-
-altbootcmd=
-	echo Performing rollback...;
-	if test "${mmcpart_committed}" = 1; then
-		setenv mmcpart 2;
-		setenv mmcpart_committed 2;
-	else
-		setenv mmcpart 1;
-		setenv mmcpart_committed 1;
-	fi;
-	setenv bootcount 0;
-	setenv upgrade_available;
-	setenv ustate 3;
-	saveenv;
-	run bootcmd;
 boot_emmc=setenv mmcdev_wanted 1; run persist_mmcdev; run bootcmd;
 boot_sd=setenv mmcdev_wanted 0; run persist_mmcdev; run bootcmd;
 bootcmd=
diff --git a/board/sunxi/board.c b/board/sunxi/board.c
index c7a2205ed61..ac9cefc6eac 100644
--- a/board/sunxi/board.c
+++ b/board/sunxi/board.c
@@ -563,7 +563,8 @@ void sunxi_board_init(void)
 #if defined CONFIG_AXP152_POWER || defined CONFIG_AXP209_POWER || \
 	defined CONFIG_AXP221_POWER || defined CONFIG_AXP305_POWER || \
 	defined CONFIG_AXP809_POWER || defined CONFIG_AXP818_POWER || \
-	defined CONFIG_AXP313_POWER || defined CONFIG_AXP717_POWER
+	defined CONFIG_AXP313_POWER || defined CONFIG_AXP717_POWER || \
+	defined CONFIG_AXP803_POWER
 	power_failed = axp_init();
 
 	if (IS_ENABLED(CONFIG_AXP_DISABLE_BOOT_ON_POWERON) && !power_failed) {
@@ -581,6 +582,8 @@ void sunxi_board_init(void)
 #endif
 #ifdef CONFIG_AXP_DCDC2_VOLT
 	power_failed |= axp_set_dcdc2(CONFIG_AXP_DCDC2_VOLT);
+#endif
+#ifdef CONFIG_AXP_DCDC3_VOLT
 	power_failed |= axp_set_dcdc3(CONFIG_AXP_DCDC3_VOLT);
 #endif
 #ifdef CONFIG_AXP_DCDC4_VOLT
diff --git a/board/ti/am62px/am62px.env b/board/ti/am62px/am62px.env
index 7ef54079aa8..f19e158d8d6 100644
--- a/board/ti/am62px/am62px.env
+++ b/board/ti/am62px/am62px.env
@@ -1,5 +1,12 @@
 #include <env/ti/ti_common.env>
 #include <env/ti/mmc.env>
+#include <env/ti/k3_dfu.env>
+
+#if CONFIG_CMD_REMOTEPROC
+#include <env/ti/k3_rproc.env>
+#endif
+
+rproc_fw_binaries= 0 /lib/firmware/am62p-mcu-r5f0_0-fw
 
 name_kern=Image
 console=ttyS2,115200n8
@@ -7,7 +14,7 @@ args_all=setenv optargs ${optargs} earlycon=ns16550a,mmio32,0x02800000
 	${mtdparts}
 run_kern=booti ${loadaddr} ${rd_spec} ${fdtaddr}
 
-boot_targets=mmc1 mmc0 pxe dhcp
+boot_targets=mmc1 mmc0 usb pxe dhcp
 boot=mmc
 mmcdev=1
 bootpart=1:2
@@ -17,4 +24,4 @@ rd_spec=-
 #if CONFIG_BOOTMETH_ANDROID
 #include <env/ti/android.env>
 adtb_idx=3
-#endif
\ No newline at end of file
+#endif
diff --git a/board/ti/am62px/rm-cfg.yaml b/board/ti/am62px/rm-cfg.yaml
index caa2f7a5a83..73da85eeade 100644
--- a/board/ti/am62px/rm-cfg.yaml
+++ b/board/ti/am62px/rm-cfg.yaml
@@ -1,5 +1,5 @@
 # SPDX-License-Identifier: GPL-2.0+
-# Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/
+# Copyright (C) 2022-2025 Texas Instruments Incorporated - https://www.ti.com/
 #
 # Resource management configuration for AM62P
 #
@@ -244,7 +244,7 @@ rm-cfg:
             subhdr:
                 magic: 0x7B25
                 size: 8
-            resasg_entries_size: 984
+            resasg_entries_size: 1112
             reserved: 0
     resasg_entries:
         -
@@ -303,31 +303,55 @@ rm-cfg:
             reserved: 0
         -
             start_resource: 0
+            num_resource: 2
+            type: 1676
+            host_id: 12
+            reserved: 0
+        -
+            start_resource: 2
+            num_resource: 1
+            type: 1676
+            host_id: 35
+            reserved: 0
+        -
+            start_resource: 2
+            num_resource: 1
+            type: 1676
+            host_id: 36
+            reserved: 0
+        -
+            start_resource: 3
+            num_resource: 1
+            type: 1676
+            host_id: 30
+            reserved: 0
+        -
+            start_resource: 4
             num_resource: 18
             type: 1677
             host_id: 12
             reserved: 0
         -
-            start_resource: 18
+            start_resource: 22
             num_resource: 6
             type: 1677
             host_id: 35
             reserved: 0
         -
-            start_resource: 18
+            start_resource: 22
             num_resource: 6
             type: 1677
             host_id: 36
             reserved: 0
         -
-            start_resource: 24
+            start_resource: 28
             num_resource: 2
             type: 1677
             host_id: 30
             reserved: 0
         -
-            start_resource: 26
-            num_resource: 6
+            start_resource: 30
+            num_resource: 2
             type: 1677
             host_id: 128
             reserved: 0
@@ -387,31 +411,55 @@ rm-cfg:
             reserved: 0
         -
             start_resource: 0
+            num_resource: 2
+            type: 1695
+            host_id: 12
+            reserved: 0
+        -
+            start_resource: 2
+            num_resource: 1
+            type: 1695
+            host_id: 35
+            reserved: 0
+        -
+            start_resource: 2
+            num_resource: 1
+            type: 1695
+            host_id: 36
+            reserved: 0
+        -
+            start_resource: 3
+            num_resource: 1
+            type: 1695
+            host_id: 30
+            reserved: 0
+        -
+            start_resource: 4
             num_resource: 18
             type: 1696
             host_id: 12
             reserved: 0
         -
-            start_resource: 18
+            start_resource: 22
             num_resource: 6
             type: 1696
             host_id: 35
             reserved: 0
         -
-            start_resource: 18
+            start_resource: 22
             num_resource: 6
             type: 1696
             host_id: 36
             reserved: 0
         -
-            start_resource: 24
+            start_resource: 28
             num_resource: 2
             type: 1696
             host_id: 30
             reserved: 0
         -
-            start_resource: 26
-            num_resource: 6
+            start_resource: 30
+            num_resource: 2
             type: 1696
             host_id: 128
             reserved: 0
@@ -476,13 +524,13 @@ rm-cfg:
             host_id: 12
             reserved: 0
         -
-            start_resource: 45
+            start_resource: 44
             num_resource: 35
             type: 1802
             host_id: 35
             reserved: 0
         -
-            start_resource: 45
+            start_resource: 44
             num_resource: 35
             type: 1802
             host_id: 36
@@ -494,31 +542,31 @@ rm-cfg:
             host_id: 30
             reserved: 0
         -
-            start_resource: 14
+            start_resource: 13
             num_resource: 512
             type: 1805
             host_id: 12
             reserved: 0
         -
-            start_resource: 526
+            start_resource: 525
             num_resource: 256
             type: 1805
             host_id: 35
             reserved: 0
         -
-            start_resource: 526
+            start_resource: 525
             num_resource: 256
             type: 1805
             host_id: 36
             reserved: 0
         -
-            start_resource: 782
+            start_resource: 781
             num_resource: 128
             type: 1805
             host_id: 30
             reserved: 0
         -
-            start_resource: 910
+            start_resource: 909
             num_resource: 626
             type: 1805
             host_id: 128
@@ -645,17 +693,29 @@ rm-cfg:
             reserved: 0
         -
             start_resource: 19
-            num_resource: 64
+            num_resource: 32
             type: 1937
             host_id: 12
             reserved: 0
         -
             start_resource: 19
-            num_resource: 64
+            num_resource: 32
             type: 1937
             host_id: 36
             reserved: 0
         -
+            start_resource: 51
+            num_resource: 32
+            type: 1937
+            host_id: 12
+            reserved: 0
+        -
+            start_resource: 51
+            num_resource: 32
+            type: 1937
+            host_id: 30
+            reserved: 0
+        -
             start_resource: 83
             num_resource: 8
             type: 1938
@@ -699,17 +759,29 @@ rm-cfg:
             reserved: 0
         -
             start_resource: 118
-            num_resource: 16
+            num_resource: 6
             type: 1943
             host_id: 12
             reserved: 0
         -
             start_resource: 118
-            num_resource: 16
+            num_resource: 6
             type: 1943
             host_id: 36
             reserved: 0
         -
+            start_resource: 124
+            num_resource: 10
+            type: 1943
+            host_id: 12
+            reserved: 0
+        -
+            start_resource: 124
+            num_resource: 10
+            type: 1943
+            host_id: 30
+            reserved: 0
+        -
             start_resource: 134
             num_resource: 8
             type: 1944
@@ -765,17 +837,29 @@ rm-cfg:
             reserved: 0
         -
             start_resource: 19
-            num_resource: 8
+            num_resource: 4
             type: 1956
             host_id: 12
             reserved: 0
         -
             start_resource: 19
-            num_resource: 8
+            num_resource: 4
             type: 1956
             host_id: 36
             reserved: 0
         -
+            start_resource: 23
+            num_resource: 4
+            type: 1956
+            host_id: 12
+            reserved: 0
+        -
+            start_resource: 23
+            num_resource: 4
+            type: 1956
+            host_id: 30
+            reserved: 0
+        -
             start_resource: 27
             num_resource: 1
             type: 1957
@@ -861,17 +945,29 @@ rm-cfg:
             reserved: 0
         -
             start_resource: 19
-            num_resource: 16
+            num_resource: 6
             type: 1964
             host_id: 12
             reserved: 0
         -
             start_resource: 19
-            num_resource: 16
+            num_resource: 6
             type: 1964
             host_id: 36
             reserved: 0
         -
+            start_resource: 25
+            num_resource: 10
+            type: 1964
+            host_id: 12
+            reserved: 0
+        -
+            start_resource: 25
+            num_resource: 10
+            type: 1964
+            host_id: 30
+            reserved: 0
+        -
             start_resource: 20
             num_resource: 1
             type: 1965
diff --git a/board/ti/am62px/tifs-rm-cfg.yaml b/board/ti/am62px/tifs-rm-cfg.yaml
index a80a2750467..80269748057 100644
--- a/board/ti/am62px/tifs-rm-cfg.yaml
+++ b/board/ti/am62px/tifs-rm-cfg.yaml
@@ -1,5 +1,5 @@
 # SPDX-License-Identifier: GPL-2.0+
-# Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/
+# Copyright (C) 2022-2025 Texas Instruments Incorporated - https://www.ti.com/
 #
 # Resource management configuration for AM62P
 #
@@ -244,7 +244,7 @@ tifs-rm-cfg:
             subhdr:
                 magic: 0x7B25
                 size: 8
-            resasg_entries_size: 840
+            resasg_entries_size: 904
             reserved: 0
     resasg_entries:
         -
@@ -423,13 +423,13 @@ tifs-rm-cfg:
                 reserved: 0
         -
                 start_resource: 44
-                num_resource: 36
+                num_resource: 35
                 type: 1802
                 host_id: 35
                 reserved: 0
         -
                 start_resource: 44
-                num_resource: 36
+                num_resource: 35
                 type: 1802
                 host_id: 36
                 reserved: 0
@@ -555,17 +555,29 @@ tifs-rm-cfg:
                 reserved: 0
         -
                 start_resource: 19
-                num_resource: 64
+                num_resource: 32
                 type: 1937
                 host_id: 12
                 reserved: 0
         -
                 start_resource: 19
-                num_resource: 64
+                num_resource: 32
                 type: 1937
                 host_id: 36
                 reserved: 0
         -
+                start_resource: 51
+                num_resource: 32
+                type: 1937
+                host_id: 12
+                reserved: 0
+        -
+                start_resource: 51
+                num_resource: 32
+                type: 1937
+                host_id: 30
+                reserved: 0
+        -
                 start_resource: 83
                 num_resource: 8
                 type: 1938
@@ -609,17 +621,29 @@ tifs-rm-cfg:
                 reserved: 0
         -
                 start_resource: 118
-                num_resource: 16
+                num_resource: 6
                 type: 1943
                 host_id: 12
                 reserved: 0
         -
                 start_resource: 118
-                num_resource: 16
+                num_resource: 6
                 type: 1943
                 host_id: 36
                 reserved: 0
         -
+                start_resource: 124
+                num_resource: 10
+                type: 1943
+                host_id: 12
+                reserved: 0
+        -
+                start_resource: 124
+                num_resource: 10
+                type: 1943
+                host_id: 30
+                reserved: 0
+        -
                 start_resource: 134
                 num_resource: 8
                 type: 1944
@@ -675,17 +699,29 @@ tifs-rm-cfg:
                 reserved: 0
         -
                 start_resource: 19
-                num_resource: 8
+                num_resource: 4
                 type: 1956
                 host_id: 12
                 reserved: 0
         -
                 start_resource: 19
-                num_resource: 8
+                num_resource: 4
                 type: 1956
                 host_id: 36
                 reserved: 0
         -
+                start_resource: 23
+                num_resource: 4
+                type: 1956
+                host_id: 12
+                reserved: 0
+        -
+                start_resource: 23
+                num_resource: 4
+                type: 1956
+                host_id: 30
+                reserved: 0
+        -
                 start_resource: 27
                 num_resource: 1
                 type: 1957
@@ -771,17 +807,29 @@ tifs-rm-cfg:
                 reserved: 0
         -
                 start_resource: 19
-                num_resource: 16
+                num_resource: 6
                 type: 1964
                 host_id: 12
                 reserved: 0
         -
                 start_resource: 19
-                num_resource: 16
+                num_resource: 6
                 type: 1964
                 host_id: 36
                 reserved: 0
         -
+                start_resource: 25
+                num_resource: 10
+                type: 1964
+                host_id: 12
+                reserved: 0
+        -
+                start_resource: 25
+                num_resource: 10
+                type: 1964
+                host_id: 30
+                reserved: 0
+        -
                 start_resource: 20
                 num_resource: 1
                 type: 1965
diff --git a/board/ti/am62x/am62x.env b/board/ti/am62x/am62x.env
index 078cc4b5ac9..60b5fd5e6ca 100644
--- a/board/ti/am62x/am62x.env
+++ b/board/ti/am62x/am62x.env
@@ -2,6 +2,12 @@
 #include <env/ti/mmc.env>
 #include <env/ti/k3_dfu.env>
 
+#if CONFIG_CMD_REMOTEPROC
+#include <env/ti/k3_rproc.env>
+#endif
+
+rproc_fw_binaries= 0 /lib/firmware/am62-mcu-m4f0_0-fw
+
 name_kern=Image
 console=ttyS2,115200n8
 args_all=setenv optargs ${optargs} earlycon=ns16550a,mmio32,0x02800000
diff --git a/board/ti/am64x/am64x.env b/board/ti/am64x/am64x.env
index 8ad805a613c..c8ab57b807c 100644
--- a/board/ti/am64x/am64x.env
+++ b/board/ti/am64x/am64x.env
@@ -2,6 +2,12 @@
 #include <env/ti/mmc.env>
 #include <env/ti/k3_dfu.env>
 
+#if CONFIG_CMD_REMOTEPROC
+#include <env/ti/k3_rproc.env>
+#endif
+
+rproc_fw_binaries= 0 /lib/firmware/am64-mcu-m4f0_0-fw 1 /lib/firmware/am64-main-r5f0_0-fw 2 /lib/firmware/am64-main-r5f0_1-fw 3 /lib/firmware/am64-main-r5f1_0-fw 4 /lib/firmware/am64-main-r5f1_1-fw
+
 name_kern=Image
 console=ttyS2,115200n8
 args_all=setenv optargs earlycon=ns16550a,mmio32,0x02800000 ${mtdparts}
diff --git a/board/ti/j7200/Kconfig b/board/ti/j7200/Kconfig
new file mode 100644
index 00000000000..093d23e7bf8
--- /dev/null
+++ b/board/ti/j7200/Kconfig
@@ -0,0 +1,40 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2018-2019 Texas Instruments Incorporated - https://www.ti.com/
+#	Lokesh Vutla <lokeshvutla@ti.com>
+
+if TARGET_J7200_A72_EVM
+
+config SYS_BOARD
+       default "j7200"
+
+config SYS_VENDOR
+       default "ti"
+
+config SYS_CONFIG_NAME
+       default "j721e_evm"
+
+config ENV_SOURCE_FILE
+       default "j7200"
+
+source "board/ti/common/Kconfig"
+
+endif
+
+if TARGET_J7200_R5_EVM
+
+config SYS_BOARD
+       default "j7200"
+
+config SYS_VENDOR
+       default "ti"
+
+config SYS_CONFIG_NAME
+       default "j721e_evm"
+
+config ENV_SOURCE_FILE
+       default "j7200"
+
+source "board/ti/common/Kconfig"
+
+endif
diff --git a/board/ti/j7200/MAINTAINERS b/board/ti/j7200/MAINTAINERS
new file mode 100644
index 00000000000..626141367a5
--- /dev/null
+++ b/board/ti/j7200/MAINTAINERS
@@ -0,0 +1,7 @@
+J7200 BOARD
+M:	Tom Rini <trini@konsulko.com>
+S:	Maintained
+F:	board/ti/j7200
+F:	include/configs/j7200_evm.h
+F:	configs/j7200_evm_r5_defconfig
+F:	configs/j7200_evm_a72_defconfig
diff --git a/board/ti/j7200/Makefile b/board/ti/j7200/Makefile
new file mode 100644
index 00000000000..4ae69aaea7b
--- /dev/null
+++ b/board/ti/j7200/Makefile
@@ -0,0 +1,7 @@
+#
+# Copyright (C) 2025 Texas Instruments Incorporated - https://www.ti.com/
+#
+# SPDX-License-Identifier:     GPL-2.0+
+#
+
+obj-y += ../j721e/evm.o
diff --git a/board/ti/j721e/board-cfg_j7200.yaml b/board/ti/j7200/board-cfg.yaml
index a1e55a26be5..a1e55a26be5 100644
--- a/board/ti/j721e/board-cfg_j7200.yaml
+++ b/board/ti/j7200/board-cfg.yaml
diff --git a/board/ti/j7200/j7200.env b/board/ti/j7200/j7200.env
new file mode 100644
index 00000000000..6cc92bf0d8d
--- /dev/null
+++ b/board/ti/j7200/j7200.env
@@ -0,0 +1,40 @@
+#include <env/ti/ti_common.env>
+#include <env/ti/mmc.env>
+#include <env/ti/ufs.env>
+#include <env/ti/k3_dfu.env>
+
+#if CONFIG_CMD_REMOTEPROC
+#include <env/ti/k3_rproc.env>
+#endif
+
+name_kern=Image
+console=ttyS2,115200n8
+args_all=setenv optargs earlycon=ns16550a,mmio32,0x02800000
+	${mtdparts}
+run_kern=booti ${loadaddr} ${rd_spec} ${fdtaddr}
+
+#if CONFIG_TARGET_J7200_R5_EVM
+addr_mcur5f0_0load=0x89000000
+name_mcur5f0_0fw=/lib/firmware/j7200-mcu-r5f0_0-fw
+#endif
+
+boot_targets=mmc1 mmc0 usb pxe dhcp
+boot=mmc
+mmcdev=1
+bootpart=1:2
+bootdir=/boot
+rd_spec=-
+
+#if CONFIG_TARGET_J7200_A72_EVM
+do_main_cpsw0_qsgmii_phyinit=1
+init_main_cpsw0_qsgmii_phy=gpio set gpio@22_17;
+	gpio clear gpio@22_16
+main_cpsw0_qsgmii_phyinit=
+	if test ${do_main_cpsw0_qsgmii_phyinit} -eq 1 && test ${dorprocboot} -eq 1 && test ${boot} = mmc; then
+		run init_main_cpsw0_qsgmii_phy;
+	fi;
+#endif
+
+#if CONFIG_TARGET_J7200_A72_EVM
+rproc_fw_binaries=2 /lib/firmware/j7200-main-r5f0_0-fw 3 /lib/firmware/j7200-main-r5f0_1-fw
+#endif
diff --git a/board/ti/j721e/pm-cfg_j7200.yaml b/board/ti/j7200/pm-cfg.yaml
index 85cd2c9dbca..85cd2c9dbca 100644
--- a/board/ti/j721e/pm-cfg_j7200.yaml
+++ b/board/ti/j7200/pm-cfg.yaml
diff --git a/board/ti/j721e/rm-cfg_j7200.yaml b/board/ti/j7200/rm-cfg.yaml
index f83184bbfc0..f83184bbfc0 100644
--- a/board/ti/j721e/rm-cfg_j7200.yaml
+++ b/board/ti/j7200/rm-cfg.yaml
diff --git a/board/ti/j721e/sec-cfg_j7200.yaml b/board/ti/j7200/sec-cfg.yaml
index 4726ac24a38..4726ac24a38 100644
--- a/board/ti/j721e/sec-cfg_j7200.yaml
+++ b/board/ti/j7200/sec-cfg.yaml
diff --git a/board/ti/j721e/Kconfig b/board/ti/j721e/Kconfig
index 6990f6ef4a4..7c7e23988d8 100644
--- a/board/ti/j721e/Kconfig
+++ b/board/ti/j721e/Kconfig
@@ -38,39 +38,3 @@ config ENV_SOURCE_FILE
 source "board/ti/common/Kconfig"
 
 endif
-
-if TARGET_J7200_A72_EVM
-
-config SYS_BOARD
-       default "j721e"
-
-config SYS_VENDOR
-       default "ti"
-
-config SYS_CONFIG_NAME
-       default "j721e_evm"
-
-config ENV_SOURCE_FILE
-       default "j721e"
-
-source "board/ti/common/Kconfig"
-
-endif
-
-if TARGET_J7200_R5_EVM
-
-config SYS_BOARD
-       default "j721e"
-
-config SYS_VENDOR
-       default "ti"
-
-config SYS_CONFIG_NAME
-       default "j721e_evm"
-
-config ENV_SOURCE_FILE
-       default "j721e"
-
-source "board/ti/common/Kconfig"
-
-endif
diff --git a/board/ti/j721e/MAINTAINERS b/board/ti/j721e/MAINTAINERS
index 06aba53d9b0..19199dbeadd 100644
--- a/board/ti/j721e/MAINTAINERS
+++ b/board/ti/j721e/MAINTAINERS
@@ -7,5 +7,3 @@ F:	configs/j721e_evm_r5_defconfig
 F:	configs/j721e_evm_a72_defconfig
 F:	configs/j721e_sk_r5_defconfig
 F:	configs/j721e_sk_a72_defconfig
-F:	configs/j7200_evm_r5_defconfig
-F:	configs/j7200_evm_a72_defconfig
diff --git a/board/ti/j721e/j721e.env b/board/ti/j721e/j721e.env
index 38bfd7d4963..e5b4225b3ce 100644
--- a/board/ti/j721e/j721e.env
+++ b/board/ti/j721e/j721e.env
@@ -16,9 +16,6 @@ run_kern=booti ${loadaddr} ${rd_spec} ${fdtaddr}
 #if CONFIG_TARGET_J721E_R5_EVM
 addr_mcur5f0_0load=0x89000000
 name_mcur5f0_0fw=/lib/firmware/j7-mcu-r5f0_0-fw
-#elif CONFIG_TARGET_J7200_R5_EVM
-addr_mcur5f0_0load=0x89000000
-name_mcur5f0_0fw=/lib/firmware/j7200-mcu-r5f0_0-fw
 #endif
 
 boot_targets=mmc1 mmc0 usb pxe dhcp
@@ -28,15 +25,7 @@ bootpart=1:2
 bootdir=/boot
 rd_spec=-
 
-#if CONFIG_TARGET_J7200_A72_EVM
-do_main_cpsw0_qsgmii_phyinit=1
-init_main_cpsw0_qsgmii_phy=gpio set gpio@22_17;
-	gpio clear gpio@22_16
-main_cpsw0_qsgmii_phyinit=
-	if test ${do_main_cpsw0_qsgmii_phyinit} -eq 1 && test ${dorprocboot} -eq 1 && test ${boot} = mmc; then
-		run init_main_cpsw0_qsgmii_phy;
-	fi;
-#elif CONFIG_TARGET_J721E_A72_EVM
+#if CONFIG_TARGET_J721E_A72_EVM
 init_main_cpsw0_qsgmii_phy=gpio set gpio@22_17;
 	gpio clear gpio@22_16
 main_cpsw0_qsgmii_phyinit=
@@ -51,7 +40,3 @@ main_cpsw0_qsgmii_phyinit=
 #if CONFIG_TARGET_J721E_A72_EVM
 rproc_fw_binaries=2 /lib/firmware/j7-main-r5f0_0-fw 3 /lib/firmware/j7-main-r5f0_1-fw 4 /lib/firmware/j7-main-r5f1_0-fw 5 /lib/firmware/j7-main-r5f1_1-fw 6 /lib/firmware/j7-c66_0-fw 7 /lib/firmware/j7-c66_1-fw 8 /lib/firmware/j7-c71_0-fw
 #endif
-
-#if CONFIG_TARGET_J7200_A72_EVM
-rproc_fw_binaries=2 /lib/firmware/j7200-main-r5f0_0-fw 3 /lib/firmware/j7200-main-r5f0_1-fw
-#endif
diff --git a/board/ti/j722s/j722s.env b/board/ti/j722s/j722s.env
index 10d62034e1a..4cc66e8d6da 100644
--- a/board/ti/j722s/j722s.env
+++ b/board/ti/j722s/j722s.env
@@ -1,5 +1,6 @@
 #include <env/ti/ti_common.env>
 #include <env/ti/mmc.env>
+#include <env/ti/k3_dfu.env>
 
 #if CONFIG_CMD_REMOTEPROC
 #include <env/ti/k3_rproc.env>
diff --git a/board/ti/j784s4/Kconfig b/board/ti/j784s4/Kconfig
index 490c7be66b3..de95ac575d7 100644
--- a/board/ti/j784s4/Kconfig
+++ b/board/ti/j784s4/Kconfig
@@ -35,3 +35,36 @@ config SPL_LDSCRIPT
 source "board/ti/common/Kconfig"
 
 endif
+
+if TARGET_J742S2_A72_EVM
+
+config SYS_BOARD
+       default "j784s4"
+
+config SYS_VENDOR
+       default "ti"
+
+config SYS_CONFIG_NAME
+       default "j784s4_evm"
+
+source "board/ti/common/Kconfig"
+
+endif
+
+if TARGET_J742S2_R5_EVM
+
+config SYS_BOARD
+       default "j784s4"
+
+config SYS_VENDOR
+       default "ti"
+
+config SYS_CONFIG_NAME
+       default "j784s4_evm"
+
+config SPL_LDSCRIPT
+	default "arch/arm/mach-omap2/u-boot-spl.lds"
+
+source "board/ti/common/Kconfig"
+
+endif
diff --git a/board/ti/j784s4/MAINTAINERS b/board/ti/j784s4/MAINTAINERS
index e92e8d03cb3..b289c639f3f 100644
--- a/board/ti/j784s4/MAINTAINERS
+++ b/board/ti/j784s4/MAINTAINERS
@@ -20,3 +20,13 @@ F:	arch/arm/dts/k3-am69-sk-u-boot.dtsi
 F:	arch/arm/dts/k3-am69-r5-sk.dts
 F:	configs/am69_sk_r5_defconfig
 F:	configs/am69_sk_a72_defconfig
+
+J742S2 EVM BOARD
+M:	Manorit Chawdhry <m-chawdhry@ti.com>
+S:	Maintained
+F:	arch/arm/dts/k3-j784s4-j742s2-ddr.dtsi
+F:	arch/arm/dts/k3-j742s2-r5-evm.dts
+F:	arch/arm/dts/k3-j742s2-evm-u-boot.dtsi
+F:	arch/arm/dts/k3-j742s2-ddr-evm-lp4-4266.dtsi
+F:	configs/j742s2_evm_r5_defconfig
+F:	configs/j742s2_evm_a72_defconfig
diff --git a/board/ti/j784s4/j784s4.env b/board/ti/j784s4/j784s4.env
index f5b72c7505e..9e1741be424 100644
--- a/board/ti/j784s4/j784s4.env
+++ b/board/ti/j784s4/j784s4.env
@@ -20,4 +20,8 @@ bootpart=1:2
 bootdir=/boot
 rd_spec=-
 
+#if CONFIG_TARGET_J784S4_A72_EVM
 rproc_fw_binaries= 2 /lib/firmware/j784s4-main-r5f0_0-fw 3 /lib/firmware/j784s4-main-r5f0_1-fw 4 /lib/firmware/j784s4-main-r5f1_0-fw 5 /lib/firmware/j784s4-main-r5f1_1-fw 6 /lib/firmware/j784s4-main-r5f2_0-fw 7 /lib/firmware/j784s4-main-r5f2_1-fw 8 /lib/firmware/j784s4-c71_0-fw 9 /lib/firmware/j784s4-c71_1-fw 10 /lib/firmware/j784s4-c71_2-fw 11 /lib/firmware/j784s4-c71_3-fw
+#elif CONFIG_TARGET_J742S2_A72_EVM
+rproc_fw_binaries= 2 /lib/firmware/j742s2-main-r5f0_0-fw 3 /lib/firmware/j742s2-main-r5f0_1-fw 4 /lib/firmware/j742s2-main-r5f1_0-fw 5 /lib/firmware/j742s2-main-r5f1_1-fw 6 /lib/firmware/j742s2-main-r5f2_0-fw 7 /lib/firmware/j742s2-main-r5f2_1-fw 8 /lib/firmware/j742s2-c71_0-fw 9 /lib/firmware/j742s2-c71_1-fw 10 /lib/firmware/j742s2-c71_2-fw
+#endif
diff --git a/board/ti/j784s4/rm-cfg.yaml b/board/ti/j784s4/rm-cfg.yaml
index a448bd2e1e0..6968d317522 100644
--- a/board/ti/j784s4/rm-cfg.yaml
+++ b/board/ti/j784s4/rm-cfg.yaml
@@ -406,49 +406,49 @@ rm-cfg:
             reserved: 0
         -
             start_resource: 16
-            num_resource: 16
+            num_resource: 32
             type: 17998
             host_id: 12
             reserved: 0
         -
-            start_resource: 32
-            num_resource: 16
+            start_resource: 16
+            num_resource: 32
             type: 17998
             host_id: 35
             reserved: 0
         -
             start_resource: 0
-            num_resource: 8
+            num_resource: 16
             type: 17999
             host_id: 12
             reserved: 0
         -
-            start_resource: 8
-            num_resource: 8
+            start_resource: 0
+            num_resource: 16
             type: 17999
             host_id: 35
             reserved: 0
         -
             start_resource: 0
-            num_resource: 16
+            num_resource: 32
             type: 18017
             host_id: 12
             reserved: 0
         -
-            start_resource: 16
-            num_resource: 16
+            start_resource: 0
+            num_resource: 32
             type: 18017
             host_id: 35
             reserved: 0
         -
             start_resource: 0
-            num_resource: 8
+            num_resource: 16
             type: 18018
             host_id: 12
             reserved: 0
         -
-            start_resource: 8
-            num_resource: 8
+            start_resource: 0
+            num_resource: 16
             type: 18018
             host_id: 35
             reserved: 0
diff --git a/board/ti/j784s4/tifs-rm-cfg.yaml b/board/ti/j784s4/tifs-rm-cfg.yaml
index 1c5faffb8e9..992ea23155a 100644
--- a/board/ti/j784s4/tifs-rm-cfg.yaml
+++ b/board/ti/j784s4/tifs-rm-cfg.yaml
@@ -250,49 +250,49 @@ tifs-rm-cfg:
     resasg_entries:
         -
             start_resource: 16
-            num_resource: 16
+            num_resource: 32
             type: 17998
             host_id: 12
             reserved: 0
         -
-            start_resource: 32
-            num_resource: 16
+            start_resource: 16
+            num_resource: 32
             type: 17998
             host_id: 35
             reserved: 0
         -
             start_resource: 0
-            num_resource: 8
+            num_resource: 16
             type: 17999
             host_id: 12
             reserved: 0
         -
-            start_resource: 8
-            num_resource: 8
+            start_resource: 0
+            num_resource: 16
             type: 17999
             host_id: 35
             reserved: 0
         -
             start_resource: 0
-            num_resource: 16
+            num_resource: 32
             type: 18017
             host_id: 12
             reserved: 0
         -
-            start_resource: 16
-            num_resource: 16
+            start_resource: 0
+            num_resource: 32
             type: 18017
             host_id: 35
             reserved: 0
         -
             start_resource: 0
-            num_resource: 8
+            num_resource: 16
             type: 18018
             host_id: 12
             reserved: 0
         -
-            start_resource: 8
-            num_resource: 8
+            start_resource: 0
+            num_resource: 16
             type: 18018
             host_id: 35
             reserved: 0
diff --git a/board/toradex/apalis_imx6/apalis_imx6.c b/board/toradex/apalis_imx6/apalis_imx6.c
index ec0f223c4aa..e0a7c661270 100644
--- a/board/toradex/apalis_imx6/apalis_imx6.c
+++ b/board/toradex/apalis_imx6/apalis_imx6.c
@@ -36,6 +36,7 @@
 #include <dwc_ahsata.h>
 #include <env.h>
 #include <fsl_esdhc_imx.h>
+#include <i2c.h>
 #include <imx_thermal.h>
 #include <micrel.h>
 #include <miiphy.h>
@@ -77,6 +78,8 @@ DECLARE_GLOBAL_DATA_PTR;
 
 #define APALIS_IMX6_SATA_INIT_RETRIES	10
 
+#define I2C_PWR	1
+
 int dram_init(void)
 {
 	/* use the DDR controllers configured size */
@@ -689,6 +692,32 @@ int board_init(void)
 	return 0;
 }
 
+static bool is_som_variant_1_2(void)
+{
+	struct udevice *bus;
+	struct udevice *i2c_dev;
+	int ret;
+
+	ret = uclass_get_device_by_seq(UCLASS_I2C, I2C_PWR, &bus);
+	if (ret) {
+		printf("Failed to get I2C_PWR\n");
+		return false;
+	}
+
+	/* V1.2 uses the TLA2024 at 0x49 instead of the STMPE811 at 0x41 */
+	ret = dm_i2c_probe(bus, 0x49, 0, &i2c_dev);
+
+	return (bool)!ret;
+}
+
+static void select_dt_from_module_version(void)
+{
+	if (is_som_variant_1_2())
+		env_set("variant", "-v1.2");
+	else
+		env_set("variant", "");
+}
+
 #ifdef CONFIG_BOARD_LATE_INIT
 int board_late_init(void)
 {
@@ -696,6 +725,8 @@ int board_late_init(void)
 	char env_str[256];
 	u32 rev;
 
+	select_dt_from_module_version();
+
 	rev = get_board_revision();
 	snprintf(env_str, ARRAY_SIZE(env_str), "%.4x", rev);
 	env_set("board_rev", env_str);
diff --git a/board/toradex/colibri_imx6/colibri_imx6.c b/board/toradex/colibri_imx6/colibri_imx6.c
index 64cf99e9cfc..69a3c5f3dfd 100644
--- a/board/toradex/colibri_imx6/colibri_imx6.c
+++ b/board/toradex/colibri_imx6/colibri_imx6.c
@@ -33,6 +33,7 @@
 #include <cpu.h>
 #include <dm/platform_data/serial_mxc.h>
 #include <fsl_esdhc_imx.h>
+#include <i2c.h>
 #include <imx_thermal.h>
 #include <miiphy.h>
 #include <netdev.h>
@@ -71,6 +72,8 @@ DECLARE_GLOBAL_DATA_PTR;
 
 #define OUTPUT_RGB (PAD_CTL_SPEED_MED|PAD_CTL_DSE_60ohm|PAD_CTL_SRE_FAST)
 
+#define I2C_PWR	1
+
 int dram_init(void)
 {
 	/* use the DDR controllers configured size */
@@ -609,6 +612,32 @@ int board_init(void)
 	return 0;
 }
 
+static bool is_som_variant_1_2(void)
+{
+	struct udevice *bus;
+	struct udevice *i2c_dev;
+	int ret;
+
+	ret = uclass_get_device_by_seq(UCLASS_I2C, I2C_PWR, &bus);
+	if (ret) {
+		printf("Failed to get I2C_PWR\n");
+		return false;
+	}
+
+	/* V1.2 uses the TLA2024 at 0x49 instead of the STMPE811 at 0x41 */
+	ret = dm_i2c_probe(bus, 0x49, 0, &i2c_dev);
+
+	return (bool)!ret;
+}
+
+static void select_dt_from_module_version(void)
+{
+	if (is_som_variant_1_2())
+		env_set("variant", "-v1.2");
+	else
+		env_set("variant", "");
+}
+
 #ifdef CONFIG_BOARD_LATE_INIT
 int board_late_init(void)
 {
@@ -616,6 +645,8 @@ int board_late_init(void)
 	char env_str[256];
 	u32 rev;
 
+	select_dt_from_module_version();
+
 	rev = get_board_revision();
 	snprintf(env_str, ARRAY_SIZE(env_str), "%.4x", rev);
 	env_set("board_rev", env_str);
diff --git a/board/xiaomi/mocha/Kconfig b/board/xiaomi/mocha/Kconfig
new file mode 100644
index 00000000000..25c61d4169e
--- /dev/null
+++ b/board/xiaomi/mocha/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_MOCHA
+
+config SYS_BOARD
+	default "mocha"
+
+config SYS_VENDOR
+	default "xiaomi"
+
+config SYS_CONFIG_NAME
+	default "mocha"
+
+endif
diff --git a/board/xiaomi/mocha/MAINTAINERS b/board/xiaomi/mocha/MAINTAINERS
new file mode 100644
index 00000000000..c3871a15a35
--- /dev/null
+++ b/board/xiaomi/mocha/MAINTAINERS
@@ -0,0 +1,8 @@
+MOCHA BOARD
+M:	Svyatoslav Ryhel <clamor95@gmail.com>
+S:	Maintained
+F:	arch/arm/dts/tegra124-xiaomi-mocha.dts
+F:	board/xiaomi/mocha/
+F:	configs/mocha_defconfig
+F:	doc/board/xiaomi/mocha.rst
+F:	include/configs/mocha.h
diff --git a/board/xiaomi/mocha/Makefile b/board/xiaomi/mocha/Makefile
new file mode 100644
index 00000000000..c42e42639b3
--- /dev/null
+++ b/board/xiaomi/mocha/Makefile
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: GPL-2.0
+#
+# Copyright (c) 2024, Svyatoslav Ryhel <clamor95@gmail.com>
+#
+
+obj-$(CONFIG_XPL_BUILD) += mocha-spl.o
+
+obj-y += mocha.o
+
diff --git a/board/xiaomi/mocha/mocha-spl.c b/board/xiaomi/mocha/mocha-spl.c
new file mode 100644
index 00000000000..5fb11df0a93
--- /dev/null
+++ b/board/xiaomi/mocha/mocha-spl.c
@@ -0,0 +1,49 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ *  Mocha SPL stage configuration
+ *
+ *  (C) Copyright 2024
+ *  Svyatoslav Ryhel <clamor95@gmail.com>
+ */
+
+#include <asm/arch/tegra.h>
+#include <asm/arch-tegra/tegra_i2c.h>
+#include <linux/delay.h>
+
+#define TPS65913_I2C_ADDR		(0x58 << 1)
+
+#define TPS65913_SMPS12_CTRL		0x20
+#define TPS65913_SMPS12_VOLTAGE		0x23
+#define TPS65913_SMPS45_CTRL		0x28
+#define TPS65913_SMPS45_VOLTAGE		0x2B
+#define TPS65913_SMPS7_CTRL		0x30
+#define TPS65913_SMPS7_VOLTAGE		0x33
+
+#define TPS65913_SMPS12_CTRL_DATA	(0x5100 | TPS65913_SMPS12_CTRL)
+#define TPS65913_SMPS12_VOLTAGE_DATA	(0x3800 | TPS65913_SMPS12_VOLTAGE)
+#define TPS65913_SMPS45_CTRL_DATA	(0x5100 | TPS65913_SMPS45_CTRL)
+#define TPS65913_SMPS45_VOLTAGE_DATA	(0x3800 | TPS65913_SMPS45_VOLTAGE)
+#define TPS65913_SMPS7_CTRL_DATA	(0x5100 | TPS65913_SMPS7_CTRL)
+#define TPS65913_SMPS7_VOLTAGE_DATA	(0x4700 | TPS65913_SMPS7_VOLTAGE)
+
+void pmic_enable_cpu_vdd(void)
+{
+	/* Set CORE VDD to 1.150V. */
+	tegra_i2c_ll_write(TPS65913_I2C_ADDR, TPS65913_SMPS7_VOLTAGE_DATA);
+	udelay(1000);
+	tegra_i2c_ll_write(TPS65913_I2C_ADDR, TPS65913_SMPS7_CTRL_DATA);
+
+	udelay(1000);
+
+	/* Set CPU VDD to 1.0V. */
+	tegra_i2c_ll_write(TPS65913_I2C_ADDR, TPS65913_SMPS12_VOLTAGE_DATA);
+	udelay(1000);
+	tegra_i2c_ll_write(TPS65913_I2C_ADDR, TPS65913_SMPS12_CTRL_DATA);
+	udelay(10 * 1000);
+
+	/* Set GPU VDD to 1.0V. */
+	tegra_i2c_ll_write(TPS65913_I2C_ADDR, TPS65913_SMPS45_VOLTAGE_DATA);
+	udelay(1000);
+	tegra_i2c_ll_write(TPS65913_I2C_ADDR, TPS65913_SMPS45_CTRL_DATA);
+	udelay(10 * 1000);
+}
diff --git a/board/xiaomi/mocha/mocha.c b/board/xiaomi/mocha/mocha.c
new file mode 100644
index 00000000000..5026d541a5f
--- /dev/null
+++ b/board/xiaomi/mocha/mocha.c
@@ -0,0 +1,41 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ *  (C) Copyright 2024
+ *  Svyatoslav Ryhel <clamor95@gmail.com>
+ */
+
+#include <dm.h>
+#include <fdt_support.h>
+#include <i2c.h>
+#include <log.h>
+
+#ifdef CONFIG_MMC_SDHCI_TEGRA
+
+#define TPS65913_I2C_ADDRESS			0x58
+#define TPS65913_PRIMARY_SECONDARY_PAD2		0xfb
+#define   GPIO_4				BIT(0)
+#define TPS65913_PRIMARY_SECONDARY_PAD3		0xfe
+#define   DVFS2					BIT(1)
+#define   DVFS1					BIT(0)
+
+/* We are using this function only till palmas pinctrl driver is available */
+void pin_mux_mmc(void)
+{
+	struct udevice *dev;
+	int ret;
+
+	ret = i2c_get_chip_for_busnum(0, TPS65913_I2C_ADDRESS, 1, &dev);
+	if (ret) {
+		log_debug("%s: cannot find PMIC I2C chip\n", __func__);
+		return;
+	}
+
+	/* GPIO4 function has to be GPIO */
+	dm_i2c_reg_clrset(dev, TPS65913_PRIMARY_SECONDARY_PAD2,
+			  GPIO_4, 0);
+
+	/* DVFS1 and DVFS2 are disabled */
+	dm_i2c_reg_clrset(dev, TPS65913_PRIMARY_SECONDARY_PAD3,
+			  DVFS2 | DVFS1, 0);
+}
+#endif
diff --git a/board/xiaomi/mocha/mocha.env b/board/xiaomi/mocha/mocha.env
new file mode 100644
index 00000000000..d93e24316f6
--- /dev/null
+++ b/board/xiaomi/mocha/mocha.env
@@ -0,0 +1,23 @@
+#include <env/nvidia/prod_upd.env>
+
+button_cmd_0_name=Volume Down
+button_cmd_0=bootmenu
+button_cmd_1_name=Hall sensor (back)
+button_cmd_1=poweroff
+button_cmd_1_name=Hall sensor (front)
+button_cmd_1=poweroff
+
+partitions=name=emmc,start=0,size=-,uuid=${uuid_gpt_rootfs}
+
+boot_block_size_r=0x400000
+boot_block_size=0x2000
+boot_dev=1
+
+bootmenu_0=mount internal storage=usb start && ums 0 mmc 0; bootmenu
+bootmenu_1=mount external storage=usb start && ums 0 mmc 1; bootmenu
+bootmenu_2=fastboot=echo Starting Fastboot protocol ...; fastboot usb 0; bootmenu
+bootmenu_3=update bootloader=run flash_uboot
+bootmenu_4=reboot RCM=enterrcm
+bootmenu_5=reboot=reset
+bootmenu_6=power off=poweroff
+bootmenu_delay=-1
diff --git a/boot/Kconfig b/boot/Kconfig
index c09a98c3233..f101200ba7a 100644
--- a/boot/Kconfig
+++ b/boot/Kconfig
@@ -1436,14 +1436,6 @@ config NAND_BOOT
 	  booted via NAND flash. This is not a must, some SoCs need this,
 	  some not.
 
-config ONENAND_BOOT
-	bool "Support for booting from ONENAND"
-	imply MTD_RAW_NAND
-	help
-	  Enabling this will make a U-Boot binary that is capable of being
-	  booted via ONENAND. This is not a must, some SoCs need this,
-	  some not.
-
 config QSPI_BOOT
 	bool "Support for booting from QSPI flash"
 	help
diff --git a/boot/bootdev-uclass.c b/boot/bootdev-uclass.c
index c39147940b6..3791ebfcb42 100644
--- a/boot/bootdev-uclass.c
+++ b/boot/bootdev-uclass.c
@@ -168,8 +168,10 @@ int bootdev_find_in_blk(struct udevice *dev, struct udevice *blk,
 		 */
 
 	/* if there are bootable partitions, scan only those */
-	} else if (iter->first_bootable >= 0 &&
+	} else if ((iter->flags & BOOTFLOWIF_ONLY_BOOTABLE) &&
+		   iter->first_bootable >= 0 &&
 		   (iter->first_bootable ? !info.bootable : iter->part != 1)) {
+		log_debug("Skipping non-bootable partition %d\n", iter->part);
 		return log_msg_ret("boot", -EINVAL);
 	} else {
 		ret = fs_set_blk_dev_with_part(desc, bflow->part);
@@ -577,6 +579,9 @@ int bootdev_next_label(struct bootflow_iter *iter, struct udevice **devp,
 	struct udevice *dev;
 
 	log_debug("next\n");
+	if (iter->cur_label >= 0 && !iter->labels[iter->cur_label])
+		return log_msg_ret("fil", -ENODEV);
+
 	for (dev = NULL; !dev && iter->labels[++iter->cur_label];) {
 		const char *label = iter->labels[iter->cur_label];
 		int ret;
diff --git a/boot/bootflow.c b/boot/bootflow.c
index 58a1afa7a75..4054a966af8 100644
--- a/boot/bootflow.c
+++ b/boot/bootflow.c
@@ -942,8 +942,9 @@ int bootflow_cmdline_auto(struct bootflow *bflow, const char *arg)
 	*buf = '\0';
 	if (!strcmp("earlycon", arg) && info.type == SERIAL_CHIP_16550_COMPATIBLE) {
 		snprintf(buf, sizeof(buf),
-			 "uart8250,mmio32,%#lx,%dn8", info.addr,
-			 info.baudrate);
+			 "uart8250,%s,%#lx,%dn8",
+			 info.addr_space == SERIAL_ADDRESS_SPACE_IO ? "io" :
+			 "mmio", info.addr, info.baudrate);
 	} else if (!strcmp("earlycon", arg) && info.type == SERIAL_CHIP_PL01X) {
 		snprintf(buf, sizeof(buf),
 			 "pl011,mmio32,%#lx,%dn8", info.addr,
@@ -954,7 +955,7 @@ int bootflow_cmdline_auto(struct bootflow *bflow, const char *arg)
 	}
 
 	if (!*buf) {
-		printf("Unknown param '%s\n", arg);
+		printf("Unknown param '%s'\n", arg);
 		return -ENOENT;
 	}
 
diff --git a/boot/bootmeth_extlinux.c b/boot/bootmeth_extlinux.c
index 17c6cebd2f4..921d721a27b 100644
--- a/boot/bootmeth_extlinux.c
+++ b/boot/bootmeth_extlinux.c
@@ -108,15 +108,15 @@ static int extlinux_check(struct udevice *dev, struct bootflow_iter *iter)
  */
 static int extlinux_fill_info(struct bootflow *bflow)
 {
-	struct membuff mb;
+	struct membuf mb;
 	char line[200];
 	char *data;
 	int len;
 
 	log_debug("parsing bflow file size %x\n", bflow->size);
-	membuff_init(&mb, bflow->buf, bflow->size);
-	membuff_putraw(&mb, bflow->size, true, &data);
-	while (len = membuff_readline(&mb, line, sizeof(line) - 1, ' ', true), len) {
+	membuf_init(&mb, bflow->buf, bflow->size);
+	membuf_putraw(&mb, bflow->size, true, &data);
+	while (len = membuf_readline(&mb, line, sizeof(line) - 1, ' ', true), len) {
 		char *tok, *p = line;
 
 		tok = strsep(&p, " ");
diff --git a/boot/fdt_support.c b/boot/fdt_support.c
index 49efeec3681..92f2f534ee0 100644
--- a/boot/fdt_support.c
+++ b/boot/fdt_support.c
@@ -18,6 +18,7 @@
 #include <dm/ofnode.h>
 #include <linux/ctype.h>
 #include <linux/types.h>
+#include <linux/sizes.h>
 #include <asm/global_data.h>
 #include <asm/unaligned.h>
 #include <linux/libfdt.h>
@@ -464,7 +465,6 @@ void do_fixup_by_compat_u32(void *fdt, const char *compat,
 	do_fixup_by_compat(fdt, compat, prop, &tmp, 4, create);
 }
 
-#ifdef CONFIG_ARCH_FIXUP_FDT_MEMORY
 /*
  * fdt_pack_reg - pack address and size array into the "reg"-suitable stream
  */
@@ -493,6 +493,7 @@ static int fdt_pack_reg(const void *fdt, void *buf, u64 *address, u64 *size,
 	return p - (char *)buf;
 }
 
+#ifdef CONFIG_ARCH_FIXUP_FDT_MEMORY
 #if CONFIG_NR_DRAM_BANKS > 4
 #define MEMORY_BANKS_MAX CONFIG_NR_DRAM_BANKS
 #else
@@ -2222,3 +2223,39 @@ int fdt_valid(struct fdt_header **blobp)
 	}
 	return 1;
 }
+
+int fdt_fixup_pmem_region(void *fdt, u64 pmem_start, u64 pmem_size)
+{
+	char node_name[32];
+	int nodeoffset, len;
+	int err;
+	u8 tmp[4 * 16]; /* Up to 64-bit address + 64-bit size */
+
+	if (!IS_ALIGNED(pmem_start, SZ_2M) ||
+	    !IS_ALIGNED(pmem_start + pmem_size, SZ_2M)) {
+		printf("Start and end address must be 2MiB aligned\n");
+		return -1;
+	}
+
+	snprintf(node_name, sizeof(node_name), "pmem@%llx", pmem_start);
+	nodeoffset = fdt_find_or_add_subnode(fdt, 0, node_name);
+	if (nodeoffset < 0)
+		return nodeoffset;
+
+	err = fdt_setprop_string(fdt, nodeoffset, "compatible", "pmem-region");
+	if (err)
+		return err;
+	err = fdt_setprop_empty(fdt, nodeoffset, "volatile");
+	if (err)
+		return err;
+
+	len = fdt_pack_reg(fdt, tmp, &pmem_start, &pmem_size, 1);
+	err = fdt_setprop(fdt, nodeoffset, "reg", tmp, len);
+	if (err < 0) {
+		printf("WARNING: could not set pmem %s %s.\n", "reg",
+		       fdt_strerror(err));
+		return err;
+	}
+
+	return 0;
+}
diff --git a/boot/image-fdt.c b/boot/image-fdt.c
index 9d1598b1a93..8f718ad29f6 100644
--- a/boot/image-fdt.c
+++ b/boot/image-fdt.c
@@ -11,6 +11,7 @@
 #include <command.h>
 #include <fdt_support.h>
 #include <fdtdec.h>
+#include <efi.h>
 #include <env.h>
 #include <errno.h>
 #include <image.h>
@@ -649,6 +650,12 @@ int image_setup_libfdt(struct bootm_headers *images, void *blob, bool lmb)
 	if (!ft_verify_fdt(blob))
 		goto err;
 
+	if (CONFIG_IS_ENABLED(BLKMAP) && CONFIG_IS_ENABLED(EFI_LOADER)) {
+		fdt_ret = fdt_efi_pmem_setup(blob);
+		if (fdt_ret)
+			goto err;
+	}
+
 	/* after here we are using a livetree */
 	if (!of_live_active() && CONFIG_IS_ENABLED(EVENT)) {
 		struct event_ft_fixup fixup;
diff --git a/boot/image-pre-load.c b/boot/image-pre-load.c
index cc19017404c..adf3b341a20 100644
--- a/boot/image-pre-load.c
+++ b/boot/image-pre-load.c
@@ -3,13 +3,24 @@
  * Copyright (C) 2021 Philippe Reynes <philippe.reynes@softathome.com>
  */
 
+#ifdef USE_HOSTCC
+#include "mkimage.h"
+#else
 #include <asm/global_data.h>
-DECLARE_GLOBAL_DATA_PTR;
-#include <image.h>
 #include <mapmem.h>
+DECLARE_GLOBAL_DATA_PTR;
+#endif /* !USE_HOSTCC*/
 
+#include <image.h>
 #include <u-boot/sha256.h>
 
+#ifdef USE_HOSTCC
+/* Define compat stuff for use in tools. */
+typedef uint8_t u8;
+typedef uint16_t u16;
+typedef uint32_t u32;
+#endif
+
 /*
  * Offset of the image
  *
@@ -17,6 +28,47 @@ DECLARE_GLOBAL_DATA_PTR;
  */
 ulong image_load_offset;
 
+#ifdef USE_HOSTCC
+/* Host tools use these implementations to setup information related to the
+ * pre-load signatures
+ */
+static struct image_sig_info *host_info;
+
+#define log_info(fmt, args...)	printf(fmt, ##args)
+#define log_err(fmt, args...)	printf(fmt, ##args)
+
+void image_pre_load_sig_set_info(struct image_sig_info *info)
+{
+	host_info = info;
+}
+
+/*
+ * This function sets a pointer to information for the signature check.
+ * It expects that host_info has been initially provision by the host
+ * application.
+ *
+ * return:
+ * < 0 => an error has occurred
+ *   0 => OK
+ */
+static int image_pre_load_sig_setup(struct image_sig_info *info)
+{
+	if (!info) {
+		log_err("ERROR: info is NULL\n");
+		return -EINVAL;
+	}
+
+	if (!host_info) {
+		log_err("ERROR: host_info is NULL\n");
+		log_err("ERROR: Set it with image_pre_load_sig_set_info()\n");
+		return -EINVAL;
+	}
+
+	memcpy(info, host_info, sizeof(struct image_sig_info));
+
+	return 0;
+}
+#else
 /*
  * This function gathers information about the signature check
  * that could be done before launching the image.
@@ -106,6 +158,7 @@ static int image_pre_load_sig_setup(struct image_sig_info *info)
  out:
 	return ret;
 }
+#endif /* !USE_HOSTCC */
 
 static int image_pre_load_sig_get_magic(ulong addr, u32 *magic)
 {
diff --git a/cmd/Kconfig b/cmd/Kconfig
index ce8393c72da..ecef664fcea 100644
--- a/cmd/Kconfig
+++ b/cmd/Kconfig
@@ -1236,6 +1236,14 @@ config CMD_FUSE
 	  which control the behaviour of the device. The command uses the
 	  fuse_...() API.
 
+config CMD_FUSE_WRITEBUFF
+	bool "Support for the fuse writebuff"
+	depends on CMD_FUSE
+	help
+	  This allows programming fuses, which control the behaviour of
+	  the device, using a structured buffer in memory. The command
+	  uses the fuse_writebuff() API.
+
 config CMD_GPIO
 	bool "gpio"
 	help
@@ -1602,6 +1610,7 @@ config CMD_READ
 config CMD_REMOTEPROC
 	bool "remoteproc"
 	depends on REMOTEPROC
+	default y if ARCH_K3
 	help
 	  Support for Remote Processor control
 
@@ -2059,7 +2068,7 @@ config CMD_SNTP
 
 config CMD_LINK_LOCAL
 	bool "linklocal"
-	select LIB_RAND
+	depends on (LIB_RAND || LIB_HW_RAND)
 	help
 	  Acquire a network IP address using the link-local protocol
 
@@ -2168,6 +2177,28 @@ config WGET_HTTPS
 	help
 	  Enable TLS over http for wget.
 
+config WGET_CACERT
+	bool "wget cacert"
+	depends on CMD_WGET
+	depends on WGET_HTTPS
+	help
+	  Adds the "cacert" sub-command to wget to provide root certificates
+	  to the HTTPS engine. Must be in DER format.
+
+config WGET_BUILTIN_CACERT
+	bool "Built-in CA certificates"
+	depends on WGET_HTTPS
+	select BUILD_BIN2C
+
+config WGET_BUILTIN_CACERT_PATH
+	string "Path to root certificates"
+	depends on WGET_BUILTIN_CACERT
+	default "cacert.crt"
+	help
+	  Set this to the path to a DER-encoded X509 file containing
+	  Certification Authority certificates, a.k.a. root certificates, for
+	  the purpose of authenticating HTTPS connections.
+
 config CMD_PXE
 	bool "pxe"
 	select PXE_UTILS
diff --git a/cmd/Makefile b/cmd/Makefile
index 8410be576bb..c1275d466c8 100644
--- a/cmd/Makefile
+++ b/cmd/Makefile
@@ -155,7 +155,6 @@ obj-$(CONFIG_CMD_QFW) += qfw.o
 obj-$(CONFIG_CMD_READ) += read.o
 obj-$(CONFIG_CMD_WRITE) += read.o
 obj-$(CONFIG_CMD_REGINFO) += reginfo.o
-obj-$(CONFIG_CMD_REISER) += reiser.o
 obj-$(CONFIG_CMD_REMOTEPROC) += remoteproc.o
 obj-$(CONFIG_CMD_RNG) += rng.o
 obj-$(CONFIG_CMD_KASLRSEED) += kaslrseed.o
diff --git a/cmd/acpi.c b/cmd/acpi.c
index 094d9d4e858..bb243202009 100644
--- a/cmd/acpi.c
+++ b/cmd/acpi.c
@@ -7,6 +7,7 @@
 #include <display_options.h>
 #include <log.h>
 #include <mapmem.h>
+#include <tables_csum.h>
 #include <acpi/acpi_table.h>
 #include <asm/acpi_table.h>
 #include <asm/global_data.h>
@@ -15,6 +16,17 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+static const char *show_checksum(void *ptr, uint size, bool chksums)
+{
+	uint checksum;
+
+	if (!chksums)
+		return "";
+	checksum = table_compute_checksum(ptr, size);
+
+	return checksum ? "  bad" : "  OK";
+}
+
 /**
  * dump_hdr() - Dump an ACPI header
  *
@@ -23,16 +35,17 @@ DECLARE_GLOBAL_DATA_PTR;
  *
  * @hdr: ACPI header to dump
  */
-static void dump_hdr(struct acpi_table_header *hdr)
+static void dump_hdr(struct acpi_table_header *hdr, bool chksums)
 {
 	bool has_hdr = memcmp(hdr->signature, "FACS", ACPI_NAME_LEN);
 
 	printf("%.*s  %16lx  %5x", ACPI_NAME_LEN, hdr->signature,
 	       (ulong)map_to_sysmem(hdr), hdr->length);
 	if (has_hdr) {
-		printf("  v%02d %.6s %.8s %x %.4s %x\n", hdr->revision,
+		printf("  v%02d %.6s %.8s %x %.4s %x%s\n", hdr->revision,
 		       hdr->oem_id, hdr->oem_table_id, hdr->oem_revision,
-		       hdr->creator_id, hdr->creator_revision);
+		       hdr->creator_id, hdr->creator_revision,
+		       show_checksum(hdr, hdr->length, chksums));
 	} else {
 		printf("\n");
 	}
@@ -52,22 +65,22 @@ static int dump_table_name(const char *sig)
 	return 0;
 }
 
-static void list_fadt(struct acpi_fadt *fadt)
+static void list_fadt(struct acpi_fadt *fadt, bool chksums)
 {
 	if (fadt->header.revision >= 3 && fadt->x_dsdt)
-		dump_hdr(nomap_sysmem(fadt->x_dsdt, 0));
+		dump_hdr(nomap_sysmem(fadt->x_dsdt, 0), chksums);
 	else if (fadt->dsdt)
-		dump_hdr(nomap_sysmem(fadt->dsdt, 0));
-	if (!IS_ENABLED(CONFIG_X86) &&
+		dump_hdr(nomap_sysmem(fadt->dsdt, 0), chksums);
+	if (!IS_ENABLED(CONFIG_X86) && !IS_ENABLED(CONFIG_SANDBOX) &&
 	    !(fadt->flags & ACPI_FADT_HW_REDUCED_ACPI))
 		log_err("FADT not ACPI-hardware-reduced-compliant\n");
 	if (fadt->header.revision >= 3 && fadt->x_firmware_ctrl)
-		dump_hdr(nomap_sysmem(fadt->x_firmware_ctrl, 0));
+		dump_hdr(nomap_sysmem(fadt->x_firmware_ctrl, 0), chksums);
 	else if (fadt->firmware_ctrl)
-		dump_hdr(nomap_sysmem(fadt->firmware_ctrl, 0));
+		dump_hdr(nomap_sysmem(fadt->firmware_ctrl, 0), chksums);
 }
 
-static void list_rsdt(struct acpi_rsdp *rsdp)
+static void list_rsdt(struct acpi_rsdp *rsdp, bool chksums)
 {
 	int len, i, count;
 	struct acpi_rsdt *rsdt;
@@ -75,11 +88,11 @@ static void list_rsdt(struct acpi_rsdp *rsdp)
 
 	if (rsdp->rsdt_address) {
 		rsdt = nomap_sysmem(rsdp->rsdt_address, 0);
-		dump_hdr(&rsdt->header);
+		dump_hdr(&rsdt->header, chksums);
 	}
 	if (rsdp->xsdt_address) {
 		xsdt = nomap_sysmem(rsdp->xsdt_address, 0);
-		dump_hdr(&xsdt->header);
+		dump_hdr(&xsdt->header, chksums);
 		len = xsdt->header.length - sizeof(xsdt->header);
 		count = len / sizeof(u64);
 	} else if (rsdp->rsdt_address) {
@@ -100,24 +113,28 @@ static void list_rsdt(struct acpi_rsdp *rsdp)
 		if (!entry)
 			break;
 		hdr = nomap_sysmem(entry, 0);
-		dump_hdr(hdr);
+		dump_hdr(hdr, chksums);
 		if (!memcmp(hdr->signature, "FACP", ACPI_NAME_LEN))
-			list_fadt((struct acpi_fadt *)hdr);
+			list_fadt((struct acpi_fadt *)hdr, chksums);
 	}
 }
 
-static void list_rsdp(struct acpi_rsdp *rsdp)
+static void list_rsdp(struct acpi_rsdp *rsdp, bool chksums)
 {
-	printf("RSDP  %16lx  %5x  v%02d %.6s\n", (ulong)map_to_sysmem(rsdp),
-	       rsdp->length, rsdp->revision, rsdp->oem_id);
-	list_rsdt(rsdp);
+	printf("RSDP  %16lx  %5x  v%02d %.6s%s%s\n",
+	       (ulong)map_to_sysmem(rsdp), rsdp->length, rsdp->revision,
+	       rsdp->oem_id, show_checksum(rsdp, 0x14, chksums),
+	       show_checksum(rsdp, rsdp->length, chksums));
+	list_rsdt(rsdp, chksums);
 }
 
 static int do_acpi_list(struct cmd_tbl *cmdtp, int flag, int argc,
 			char *const argv[])
 {
 	struct acpi_rsdp *rsdp;
+	bool chksums;
 
+	chksums = argc >= 2 && !strcmp("-c", argv[1]);
 	rsdp = map_sysmem(gd_acpi_start(), 0);
 	if (!rsdp) {
 		printf("No ACPI tables present\n");
@@ -125,7 +142,7 @@ static int do_acpi_list(struct cmd_tbl *cmdtp, int flag, int argc,
 	}
 	printf("Name              Base   Size  Detail\n"
 	       "----  ----------------  -----  ----------------------------\n");
-	list_rsdp(rsdp);
+	list_rsdp(rsdp, chksums);
 
 	return 0;
 }
@@ -187,13 +204,13 @@ static int do_acpi_dump(struct cmd_tbl *cmdtp, int flag, int argc,
 }
 
 U_BOOT_LONGHELP(acpi,
-	"list  - list ACPI tables\n"
+	"list [-c] - list ACPI tables [check checksums]\n"
 	"acpi items [-d]   - List/dump each piece of ACPI data from devices\n"
 	"acpi set [<addr>] - Set or show address of ACPI tables\n"
 	"acpi dump <name>  - Dump ACPI table");
 
 U_BOOT_CMD_WITH_SUBCMDS(acpi, "ACPI tables", acpi_help_text,
-	U_BOOT_SUBCMD_MKENT(list, 1, 1, do_acpi_list),
+	U_BOOT_SUBCMD_MKENT(list, 2, 1, do_acpi_list),
 	U_BOOT_SUBCMD_MKENT(items, 2, 1, do_acpi_items),
 	U_BOOT_SUBCMD_MKENT(set, 2, 1, do_acpi_set),
 	U_BOOT_SUBCMD_MKENT(dump, 2, 1, do_acpi_dump));
diff --git a/cmd/blkmap.c b/cmd/blkmap.c
index 164f80f1387..86a123b1cd3 100644
--- a/cmd/blkmap.c
+++ b/cmd/blkmap.c
@@ -62,13 +62,18 @@ static int do_blkmap_map_mem(struct map_ctx *ctx, int argc, char *const argv[])
 {
 	phys_addr_t addr;
 	int err;
+	bool preserve = false;
 
 	if (argc < 2)
 		return CMD_RET_USAGE;
 
 	addr = hextoul(argv[1], NULL);
 
-	err = blkmap_map_pmem(ctx->dev, ctx->blknr, ctx->blkcnt, addr);
+	if (argc == 3 && !strcmp(argv[2], "preserve"))
+		preserve = true;
+
+	err = blkmap_map_pmem(ctx->dev, ctx->blknr, ctx->blkcnt, addr,
+			      preserve);
 	if (err) {
 		printf("Unable to map %#llx at block 0x" LBAF ": %d\n",
 		       (unsigned long long)addr, ctx->blknr, err);
@@ -221,7 +226,7 @@ U_BOOT_CMD_WITH_SUBCMDS(
 	"blkmap create <label> - create device\n"
 	"blkmap destroy <label> - destroy device\n"
 	"blkmap map <label> <blk#> <cnt> linear <interface> <dev> <blk#> - device mapping\n"
-	"blkmap map <label> <blk#> <cnt> mem <addr> - memory mapping\n",
+	"blkmap map <label> <blk#> <cnt> mem <addr> [preserve] - memory mapping\n",
 	U_BOOT_SUBCMD_MKENT(info, 2, 1, do_blkmap_common),
 	U_BOOT_SUBCMD_MKENT(part, 2, 1, do_blkmap_common),
 	U_BOOT_SUBCMD_MKENT(dev, 4, 1, do_blkmap_common),
diff --git a/cmd/bootflow.c b/cmd/bootflow.c
index f88995a478f..a1fd59a69f4 100644
--- a/cmd/bootflow.c
+++ b/cmd/bootflow.c
@@ -173,7 +173,7 @@ static int do_bootflow_scan(struct cmd_tbl *cmdtp, int flag, int argc,
 
 	std->cur_bootflow = NULL;
 
-	flags = 0;
+	flags = BOOTFLOWIF_ONLY_BOOTABLE;
 	if (list)
 		flags |= BOOTFLOWIF_SHOW;
 	if (all)
diff --git a/cmd/fs.c b/cmd/fs.c
index 3d7e06d6f1e..7f1ab8f0fd2 100644
--- a/cmd/fs.c
+++ b/cmd/fs.c
@@ -85,6 +85,34 @@ U_BOOT_CMD(
 	"      device type 'interface' instance 'dev'."
 );
 
+static int do_mkdir_wrapper(struct cmd_tbl *cmdtp, int flag, int argc,
+			    char *const argv[])
+{
+	return do_mkdir(cmdtp, flag, argc, argv, FS_TYPE_ANY);
+}
+
+U_BOOT_CMD(
+	mkdir,	4,	1,	do_mkdir_wrapper,
+	"create a directory",
+	"<interface> [<dev[:part]>] <directory>\n"
+	"    - Create a directory 'directory' of partition 'part' on\n"
+	"      device type 'interface' instance 'dev'."
+);
+
+static int do_rm_wrapper(struct cmd_tbl *cmdtp, int flag, int argc,
+			 char *const argv[])
+{
+	return do_rm(cmdtp, flag, argc, argv, FS_TYPE_ANY);
+}
+
+U_BOOT_CMD(
+	rm,	4,	1,	do_rm_wrapper,
+	"delete a file",
+	"<interface> [<dev[:part]>] <filename>\n"
+	"    - delete a file with the name 'filename' on\n"
+	"      device type 'interface' instance 'dev'."
+);
+
 static int do_fstype_wrapper(struct cmd_tbl *cmdtp, int flag, int argc,
 			     char *const argv[])
 {
@@ -110,3 +138,17 @@ U_BOOT_CMD(
 	fstypes, 1, 1, do_fstypes_wrapper,
 	"List supported filesystem types", ""
 );
+
+static int do_mv_wrapper(struct cmd_tbl *cmdtp, int flag, int argc,
+			 char *const argv[])
+{
+	return do_mv(cmdtp, flag, argc, argv, FS_TYPE_ANY);
+}
+
+U_BOOT_CMD(
+	mv,	5,	1,	do_mv_wrapper,
+	"rename/move a file/directory",
+	"<interface> [<dev[:part]>] <old_path> <new_path>\n"
+	"    - renames/moves a file/directory in 'dev' on 'interface' from\n"
+	"      'old_path' to 'new_path'"
+);
diff --git a/cmd/fuse.c b/cmd/fuse.c
index 598ef496a43..6c42c096809 100644
--- a/cmd/fuse.c
+++ b/cmd/fuse.c
@@ -15,17 +15,6 @@
 #include <vsprintf.h>
 #include <linux/errno.h>
 
-static int strtou32(const char *str, unsigned int base, u32 *result)
-{
-	char *ep;
-
-	*result = simple_strtoul(str, &ep, base);
-	if (ep == str || *ep != '\0')
-		return -EINVAL;
-
-	return 0;
-}
-
 static int confirm_prog(void)
 {
 	puts("Warning: Programming fuses is an irreversible operation!\n"
@@ -54,14 +43,25 @@ static int do_fuse(struct cmd_tbl *cmdtp, int flag, int argc,
 	argc -= 2 + confirmed;
 	argv += 2 + confirmed;
 
-	if (argc < 2 || strtou32(argv[0], 0, &bank) ||
-			strtou32(argv[1], 0, &word))
-		return CMD_RET_USAGE;
+	if (IS_ENABLED(CONFIG_CMD_FUSE_WRITEBUFF) && !strcmp(op, "writebuff")) {
+		if (argc == 1)
+			addr = simple_strtoul(argv[0], NULL, 16);
+		else
+			return CMD_RET_USAGE;
+	} else {
+		if (argc < 2)
+			return CMD_RET_USAGE;
+
+		bank = simple_strtoul(argv[0], NULL, 0);
+		word = simple_strtoul(argv[1], NULL, 0);
+	}
 
 	if (!strcmp(op, "read")) {
 		if (argc == 2)
 			cnt = 1;
-		else if (argc != 3 || strtou32(argv[2], 0, &cnt))
+		else if (argc == 3)
+			cnt = simple_strtoul(argv[2], NULL, 0);
+		else
 			return CMD_RET_USAGE;
 
 		printf("Reading bank %u:\n", bank);
@@ -79,7 +79,9 @@ static int do_fuse(struct cmd_tbl *cmdtp, int flag, int argc,
 	} else if (!strcmp(op, "readm")) {
 		if (argc == 3)
 			cnt = 1;
-		else if (argc != 4 || strtou32(argv[3], 0, &cnt))
+		else if (argc == 4)
+			cnt = simple_strtoul(argv[3], NULL, 0);
+		else
 			return CMD_RET_USAGE;
 
 		addr = simple_strtoul(argv[2], NULL, 16);
@@ -99,7 +101,9 @@ static int do_fuse(struct cmd_tbl *cmdtp, int flag, int argc,
 
 		unmap_sysmem(start);
 	} else if (!strcmp(op, "cmp")) {
-		if (argc != 3 || strtou32(argv[2], 0, &cmp))
+		if (argc == 3)
+			cmp = simple_strtoul(argv[2], NULL, 0);
+		else
 			return CMD_RET_USAGE;
 
 		printf("Comparing bank %u:\n", bank);
@@ -119,7 +123,9 @@ static int do_fuse(struct cmd_tbl *cmdtp, int flag, int argc,
 	} else if (!strcmp(op, "sense")) {
 		if (argc == 2)
 			cnt = 1;
-		else if (argc != 3 || strtou32(argv[2], 0, &cnt))
+		else if (argc == 3)
+			cnt = simple_strtoul(argv[2], NULL, 0);
+		else
 			return CMD_RET_USAGE;
 
 		printf("Sensing bank %u:\n", bank);
@@ -139,8 +145,7 @@ static int do_fuse(struct cmd_tbl *cmdtp, int flag, int argc,
 			return CMD_RET_USAGE;
 
 		for (i = 2; i < argc; i++, word++) {
-			if (strtou32(argv[i], 16, &val))
-				return CMD_RET_USAGE;
+			val = simple_strtoul(argv[i], NULL, 16);
 
 			printf("Programming bank %u word 0x%.8x to 0x%.8x...\n",
 					bank, word, val);
@@ -155,8 +160,7 @@ static int do_fuse(struct cmd_tbl *cmdtp, int flag, int argc,
 			return CMD_RET_USAGE;
 
 		for (i = 2; i < argc; i++, word++) {
-			if (strtou32(argv[i], 16, &val))
-				return CMD_RET_USAGE;
+			val = simple_strtoul(argv[i], NULL, 16);
 
 			printf("Overriding bank %u word 0x%.8x with "
 					"0x%.8x...\n", bank, word, val);
@@ -164,6 +168,15 @@ static int do_fuse(struct cmd_tbl *cmdtp, int flag, int argc,
 			if (ret)
 				goto err;
 		}
+	} else if (IS_ENABLED(CONFIG_CMD_FUSE_WRITEBUFF) && !strcmp(op, "writebuff")) {
+		printf("Programming fuses using a structured buffer in memory "
+				"starting at addr 0x%lx\n", addr);
+		if (!confirmed && !confirm_prog())
+			return CMD_RET_FAILURE;
+
+		ret = fuse_writebuff(addr);
+		if (ret)
+			goto err;
 	} else {
 		return CMD_RET_USAGE;
 	}
@@ -189,5 +202,9 @@ U_BOOT_CMD(
 	"fuse prog [-y] <bank> <word> <hexval> [<hexval>...] - program 1 or\n"
 	"    several fuse words, starting at 'word' (PERMANENT)\n"
 	"fuse override <bank> <word> <hexval> [<hexval>...] - override 1 or\n"
-	"    several fuse words, starting at 'word'"
+	"    several fuse words, starting at 'word'\n"
+#ifdef CONFIG_CMD_FUSE_WRITEBUFF
+	"fuse writebuff [-y] <addr> - program fuse data\n"
+	"    using a structured buffer in memory starting at 'addr'\n"
+#endif /* CONFIG_CMD_FUSE_WRITEBUFF */
 );
diff --git a/cmd/meminfo.c b/cmd/meminfo.c
index 5e83d61c2dd..acdb38dcba0 100644
--- a/cmd/meminfo.c
+++ b/cmd/meminfo.c
@@ -15,6 +15,10 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+void __weak arch_dump_mem_attrs(void)
+{
+}
+
 static void print_region(const char *name, ulong base, ulong size, ulong *uptop)
 {
 	ulong end = base + size;
@@ -58,6 +62,8 @@ static int do_meminfo(struct cmd_tbl *cmdtp, int flag, int argc,
 	if (!IS_ENABLED(CONFIG_CMD_MEMINFO_MAP))
 		return 0;
 
+	arch_dump_mem_attrs();
+
 	printf("\n%-12s %8s %8s %8s %8s\n", "Region", "Base", "Size", "End",
 	       "Gap");
 	printf("------------------------------------------------\n");
diff --git a/cmd/net-lwip.c b/cmd/net-lwip.c
index 249556243d6..cecf8d02555 100644
--- a/cmd/net-lwip.c
+++ b/cmd/net-lwip.c
@@ -27,9 +27,24 @@ U_BOOT_CMD(dns, 3, 1, do_dns, "lookup the IP of a hostname",
 #endif
 
 #if defined(CONFIG_CMD_WGET)
-U_BOOT_CMD(wget, 3, 1, do_wget,
-	   "boot image via network using HTTP/HTTPS protocol",
+U_BOOT_CMD(wget, 4, 1, do_wget,
+	   "boot image via network using HTTP/HTTPS protocol"
+#if defined(CONFIG_WGET_CACERT)
+	   "\nwget cacert - configure wget root certificates"
+#endif
+	   ,
 	   "[loadAddress] url\n"
-	   "wget [loadAddress] [host:]path"
+	   "wget [loadAddress] [host:]path\n"
+	   "    - load file"
+#if defined(CONFIG_WGET_CACERT)
+	   "\nwget cacert <address> <length>\n"
+	   "    - provide CA certificates (0 0 to remove current)"
+	   "\nwget cacert none|optional|required\n"
+	   "    - set server certificate verification mode (default: optional)"
+#if defined(CONFIG_WGET_BUILTIN_CACERT)
+	   "\nwget cacert builtin\n"
+	   "    - use the builtin CA certificates"
+#endif
+#endif
 );
 #endif
diff --git a/cmd/x86/mtrr.c b/cmd/x86/mtrr.c
index b2afb598c73..289865515ef 100644
--- a/cmd/x86/mtrr.c
+++ b/cmd/x86/mtrr.c
@@ -13,8 +13,8 @@
 static int do_mtrr_set(int cpu_select, uint reg, int argc, char *const argv[])
 {
 	const char *typename = argv[0];
-	uint32_t start, size;
-	uint64_t base, mask;
+	u64 start, size;
+	u64 base, mask;
 	int type = -1;
 	bool valid;
 	int ret;
@@ -26,13 +26,12 @@ static int do_mtrr_set(int cpu_select, uint reg, int argc, char *const argv[])
 		printf("Invalid type name %s\n", typename);
 		return CMD_RET_USAGE;
 	}
-	start = hextoul(argv[1], NULL);
-	size = hextoul(argv[2], NULL);
+	start = hextoull(argv[1], NULL);
+	size = hextoull(argv[2], NULL);
 
 	base = start | type;
 	valid = native_read_msr(MTRR_PHYS_MASK_MSR(reg)) & MTRR_PHYS_MASK_VALID;
-	mask = ~((uint64_t)size - 1);
-	mask &= (1ULL << CONFIG_CPU_ADDR_BITS) - 1;
+	mask = mtrr_to_mask(size);
 	if (valid)
 		mask |= MTRR_PHYS_MASK_VALID;
 
diff --git a/common/Kconfig b/common/Kconfig
index 7685914fa6f..be517b80eb5 100644
--- a/common/Kconfig
+++ b/common/Kconfig
@@ -914,6 +914,19 @@ config STACKPROTECTOR
 	  Enable stack smash detection through compiler's stack-protector
 	  canary logic
 
+config MMU_PGPROT
+	bool "Enable RO, RW and RX mappings"
+	help
+	  U-Boot maps all pages as RWX. If selected pages will
+	  be marked as RO(.rodata), RX(.text), RW(.data) right after
+	  we relocate. Since code sections needs to be page aligned
+	  the final binary size will increase. The mappings can be dumped
+	  using the 'meminfo' command.
+
+	  Enabling this feature can expose bugs in U-Boot where we have
+	  code that violates read-only permissions for example. Use this
+	  feature with caution.
+
 config SPL_STACKPROTECTOR
 	bool "Stack Protector buffer overflow detection for SPL"
 	depends on STACKPROTECTOR && SPL
@@ -1055,8 +1068,8 @@ choice
 config BLOBLIST_FIXED
 	bool "Place bloblist at a fixed address in memory"
 	help
-	  Select this to used a fixed memory address for the bloblist. If the
-	  bloblist exists at this address from a previous phase, it used as is.
+	  Select this to use a fixed memory address for the bloblist. If the
+	  bloblist exists at this address from a previous phase, it is used as is.
 	  If not it is created at this address in U-Boot.
 
 config BLOBLIST_ALLOC
@@ -1066,11 +1079,21 @@ config BLOBLIST_ALLOC
 	  specify a fixed address on systems where this is unknown or can
 	  change at runtime.
 
+config BLOBLIST_PASSAGE_MANDATORY
+	bool "Use bloblist in-place mandatorily"
+	help
+	  By default U-Boot will use a bloblist in the incoming standard passage.
+	  This option controls whether U-Boot tries to load a static bloblist or
+	  allocate one if a valid incoming bloblist does not exist.
+	  Select this option to mark incoming standard passage as mandatory and
+	  U-Boot will report an error when a valid incoming bloblist does not
+	  exist.
+
 endchoice
 
 config BLOBLIST_ADDR
 	hex "Address of bloblist"
-	default 0xb000 if SANDBOX
+	default 0x100 if SANDBOX
 	depends on BLOBLIST_FIXED
 	help
 	  Sets the address of the bloblist, set up by the first part of U-Boot
@@ -1080,17 +1103,17 @@ config BLOBLIST_ADDR
 
 config BLOBLIST_SIZE
 	hex "Size of bloblist"
+	default 0x0 if BLOBLIST_PASSAGE_MANDATORY
 	default 0x400
 	help
 	  Sets the size of the bloblist in bytes. This must include all
 	  overhead (alignment, bloblist header, record header). The bloblist
 	  is set up in the first part of U-Boot to run (TPL, SPL or U-Boot
-	  proper), and this sane bloblist is used for subsequent phases.
+	  proper), and this same bloblist is used for subsequent phases.
 
 config BLOBLIST_SIZE_RELOC
 	hex "Size of bloblist after relocation"
 	default BLOBLIST_SIZE if BLOBLIST_FIXED || BLOBLIST_ALLOC
-	default 0x0 if BLOBLIST_PASSAGE
 	default 0x20000 if (ARM && EFI_LOADER && GENERATE_ACPI_TABLE)
 	help
 	  Sets the size of the bloblist in bytes after relocation. Since U-Boot
diff --git a/common/autoboot.c b/common/autoboot.c
index 898a57bc92b..0a254498d40 100644
--- a/common/autoboot.c
+++ b/common/autoboot.c
@@ -186,10 +186,15 @@ static int passwd_abort_sha256(uint64_t etime)
 	ret = hash_parse_string(algo_name, sha_env_str, sha_env);
 	if (ret) {
 		printf("Hash %s not supported!\n", algo_name);
+		free(presskey);
 		return 0;
 	}
 
 	sha = malloc_cache_aligned(SHA256_SUM_LEN);
+	if (!sha) {
+		free(presskey);
+		return -ENOMEM;
+	}
 	size = SHA256_SUM_LEN;
 	/*
 	 * We don't know how long the stop-string is, so we need to
diff --git a/common/bloblist.c b/common/bloblist.c
index ab48a3cdb98..6e4f020d7c4 100644
--- a/common/bloblist.c
+++ b/common/bloblist.c
@@ -488,6 +488,9 @@ int bloblist_reloc(void *to, uint to_size)
 {
 	struct bloblist_hdr *hdr;
 
+	if (!to_size)
+		return 0;
+
 	if (to_size < gd->bloblist->total_size)
 		return -ENOSPC;
 
@@ -502,8 +505,7 @@ int bloblist_reloc(void *to, uint to_size)
 /*
  * Weak default function for getting bloblist from boot args.
  */
-int __weak xferlist_from_boot_arg(ulong __always_unused addr,
-				  ulong __always_unused size)
+int __weak xferlist_from_boot_arg(ulong __always_unused *addr)
 {
 	return -ENOENT;
 }
@@ -511,38 +513,46 @@ int __weak xferlist_from_boot_arg(ulong __always_unused addr,
 int bloblist_init(void)
 {
 	bool fixed = IS_ENABLED(CONFIG_BLOBLIST_FIXED);
-	int ret = -ENOENT;
+	int ret = 0;
 	ulong addr = 0, size;
-	/*
-	 * If U-Boot is not in the first phase, an existing bloblist must be
-	 * at a fixed address.
-	 */
-	bool from_addr = fixed && !xpl_is_first_phase();
-	/*
-	 * If U-Boot is in the first phase that an arch custom routine should
-	 * install the bloblist passed from previous loader to this fixed
-	 * address.
-	 */
-	bool from_boot_arg = fixed && xpl_is_first_phase();
 
-	if (xpl_prev_phase() == PHASE_TPL && !IS_ENABLED(CONFIG_TPL_BLOBLIST))
-		from_addr = false;
-	if (fixed)
-		addr = IF_ENABLED_INT(CONFIG_BLOBLIST_FIXED,
-				      CONFIG_BLOBLIST_ADDR);
-	size = CONFIG_BLOBLIST_SIZE;
+	/* Check if a valid transfer list passed in */
+	if (!xferlist_from_boot_arg(&addr)) {
+		size = bloblist_get_total_size();
+	} else {
+		/*
+		 * If U-Boot is not in the first phase, an existing bloblist must
+		 * be at a fixed address.
+		 */
+		bool from_addr = fixed && !xpl_is_first_phase();
+
+		/*
+		 * If Firmware Handoff is mandatory but no transfer list is
+		 * observed, report it as an error.
+		 */
+		if (IS_ENABLED(CONFIG_BLOBLIST_PASSAGE_MANDATORY))
+			return -ENOENT;
 
-	if (from_boot_arg)
-		ret = xferlist_from_boot_arg(addr, size);
-	else if (from_addr)
-		ret = bloblist_check(addr, size);
+		ret = -ENOENT;
 
-	if (ret)
-		log_warning("Bloblist at %lx not found (err=%d)\n",
-			    addr, ret);
-	else
-		/* Get the real size */
-		size = gd->bloblist->total_size;
+		if (xpl_prev_phase() == PHASE_TPL &&
+		    !IS_ENABLED(CONFIG_TPL_BLOBLIST))
+			from_addr = false;
+		if (fixed)
+			addr = IF_ENABLED_INT(CONFIG_BLOBLIST_FIXED,
+					      CONFIG_BLOBLIST_ADDR);
+		size = CONFIG_BLOBLIST_SIZE;
+
+		if (from_addr)
+			ret = bloblist_check(addr, size);
+
+		if (ret)
+			log_warning("Bloblist at %lx not found (err=%d)\n",
+				    addr, ret);
+		else
+			/* Get the real size */
+			size = gd->bloblist->total_size;
+	}
 
 	if (ret) {
 		/*
@@ -567,6 +577,7 @@ int bloblist_init(void)
 		log_debug("Found existing bloblist size %lx at %lx\n", size,
 			  addr);
 	}
+
 	if (ret)
 		return log_msg_ret("ini", ret);
 	gd->flags |= GD_FLG_BLOBLIST_READY;
@@ -587,10 +598,11 @@ int bloblist_maybe_init(void)
 	return 0;
 }
 
-int bloblist_check_reg_conv(ulong rfdt, ulong rzero, ulong rsig)
+int bloblist_check_reg_conv(ulong rfdt, ulong rzero, ulong rsig, ulong xlist)
 {
 	u64 version = BLOBLIST_REGCONV_VER;
 	ulong sigval;
+	int ret;
 
 	if ((IS_ENABLED(CONFIG_64BIT) && !IS_ENABLED(CONFIG_SPL_BUILD)) ||
 			(IS_ENABLED(CONFIG_SPL_64BIT) && IS_ENABLED(CONFIG_SPL_BUILD))) {
@@ -601,8 +613,14 @@ int bloblist_check_reg_conv(ulong rfdt, ulong rzero, ulong rsig)
 			 ((version  & BLOBLIST_REGCONV_MASK) << BLOBLIST_REGCONV_SHIFT_32));
 	}
 
-	if (rzero || rsig != sigval ||
-	    rfdt != (ulong)bloblist_find(BLOBLISTT_CONTROL_FDT, 0)) {
+	if (rzero || rsig != sigval)
+		return -EIO;
+
+	ret = bloblist_check(xlist, 0);
+	if (ret)
+		return ret;
+
+	if (rfdt != (ulong)bloblist_find(BLOBLISTT_CONTROL_FDT, 0)) {
 		gd->bloblist = NULL;  /* Reset the gd bloblist pointer */
 		return -EIO;
 	}
diff --git a/common/board_f.c b/common/board_f.c
index 99616fdac80..baf98fb8ec8 100644
--- a/common/board_f.c
+++ b/common/board_f.c
@@ -624,11 +624,14 @@ static int reserve_stacks(void)
 static int reserve_bloblist(void)
 {
 #ifdef CONFIG_BLOBLIST
+	ulong size = bloblist_get_total_size();
+
+	if (size < CONFIG_BLOBLIST_SIZE_RELOC)
+		size = CONFIG_BLOBLIST_SIZE_RELOC;
+
 	/* Align to a 4KB boundary for easier reading of addresses */
-	gd->start_addr_sp = ALIGN_DOWN(gd->start_addr_sp -
-				       CONFIG_BLOBLIST_SIZE_RELOC, 0x1000);
-	gd->boardf->new_bloblist = map_sysmem(gd->start_addr_sp,
-					      CONFIG_BLOBLIST_SIZE_RELOC);
+	gd->start_addr_sp = ALIGN_DOWN(gd->start_addr_sp - size, 0x1000);
+	gd->boardf->new_bloblist = map_sysmem(gd->start_addr_sp, size);
 #endif
 
 	return 0;
@@ -698,11 +701,14 @@ static int reloc_bloblist(void)
 		return 0;
 	}
 	if (gd->boardf->new_bloblist) {
-		debug("Copying bloblist from %p to %p, size %x\n",
-		      gd->bloblist, gd->boardf->new_bloblist,
-	gd->bloblist->total_size);
-		return bloblist_reloc(gd->boardf->new_bloblist,
-				      CONFIG_BLOBLIST_SIZE_RELOC);
+		ulong size = bloblist_get_total_size();
+
+		if (size < CONFIG_BLOBLIST_SIZE_RELOC)
+			size = CONFIG_BLOBLIST_SIZE_RELOC;
+
+		debug("Copying bloblist from %p to %p, size %lx\n",
+		      gd->bloblist, gd->boardf->new_bloblist, size);
+		return bloblist_reloc(gd->boardf->new_bloblist, size);
 	}
 #endif
 
diff --git a/common/board_r.c b/common/board_r.c
index 179259b00de..8d69db1875d 100644
--- a/common/board_r.c
+++ b/common/board_r.c
@@ -170,7 +170,27 @@ static int initr_reloc_global_data(void)
 	efi_save_gd();
 
 	efi_runtime_relocate(gd->relocaddr, NULL);
+
 #endif
+	/*
+	 * We are done with all relocations change the permissions of the binary
+	 * NOTE: __start_rodata etc are defined in arm64 linker scripts and
+	 * sections.h. If you want to add support for your platform you need to
+	 * add the symbols on your linker script, otherwise they will point to
+	 * random addresses.
+	 *
+	 */
+	if (IS_ENABLED(CONFIG_MMU_PGPROT)) {
+		pgprot_set_attrs((phys_addr_t)(uintptr_t)(__start_rodata),
+				 (size_t)(uintptr_t)(__end_rodata - __start_rodata),
+				 MMU_ATTR_RO);
+		pgprot_set_attrs((phys_addr_t)(uintptr_t)(__start_data),
+				 (size_t)(uintptr_t)(__end_data - __start_data),
+				 MMU_ATTR_RW);
+		pgprot_set_attrs((phys_addr_t)(uintptr_t)(__text_start),
+				 (size_t)(uintptr_t)(__text_end - __text_start),
+				 MMU_ATTR_RX);
+	}
 
 	return 0;
 }
@@ -749,9 +769,6 @@ static init_fnc_t init_sequence_r[] = {
 #ifdef CONFIG_BOARD_LATE_INIT
 	board_late_init,
 #endif
-#ifdef CONFIG_BITBANGMII
-	bb_miiphy_init,
-#endif
 #ifdef CONFIG_PCI_ENDPOINT
 	pci_ep_init,
 #endif
diff --git a/common/cli_hush.c b/common/cli_hush.c
index a6a8edce1f4..9f437ae5f47 100644
--- a/common/cli_hush.c
+++ b/common/cli_hush.c
@@ -3626,7 +3626,13 @@ static char *make_string(char **inp, int *nonnull)
 		noeval = 1;
 	for (n = 0; inp[n]; n++) {
 		p = insert_var_value_sub(inp[n], noeval);
-		str = xrealloc(str, (len + strlen(p) + (2 * nonnull[n])));
+		char *new_str = xrealloc(str, (len + strlen(p) + (2 * nonnull[n])));
+		if (!new_str) {
+			free(str);
+			if (p != inp[n]) free(p);
+			return NULL;
+		}
+		str = new_str;
 		if (n) {
 			strcat(str, " ");
 		} else {
diff --git a/common/console.c b/common/console.c
index 863ac6aa9dc..b69bb189639 100644
--- a/common/console.c
+++ b/common/console.c
@@ -101,7 +101,7 @@ static void console_record_putc(const char c)
 	if (!(gd->flags & GD_FLG_RECORD))
 		return;
 	if  (gd->console_out.start &&
-	     !membuff_putbyte((struct membuff *)&gd->console_out, c))
+	     !membuf_putbyte((struct membuf *)&gd->console_out, c))
 		gd->flags |= GD_FLG_RECORD_OVF;
 }
 
@@ -112,7 +112,7 @@ static void console_record_puts(const char *s)
 	if  (gd->console_out.start) {
 		int len = strlen(s);
 
-		if (membuff_put((struct membuff *)&gd->console_out, s, len) !=
+		if (membuf_put((struct membuf *)&gd->console_out, s, len) !=
 		    len)
 			gd->flags |= GD_FLG_RECORD_OVF;
 	}
@@ -125,7 +125,7 @@ static int console_record_getc(void)
 	if (!gd->console_in.start)
 		return -1;
 
-	return membuff_getbyte((struct membuff *)&gd->console_in);
+	return membuf_getbyte((struct membuf *)&gd->console_in);
 }
 
 static int console_record_tstc(void)
@@ -133,7 +133,7 @@ static int console_record_tstc(void)
 	if (!(gd->flags & GD_FLG_RECORD))
 		return 0;
 	if (gd->console_in.start) {
-		if (membuff_peekbyte((struct membuff *)&gd->console_in) != -1)
+		if (membuf_peekbyte((struct membuf *)&gd->console_in) != -1)
 			return 1;
 	}
 	return 0;
@@ -810,14 +810,14 @@ int console_record_init(void)
 {
 	int ret;
 
-	ret = membuff_new((struct membuff *)&gd->console_out,
-			  gd->flags & GD_FLG_RELOC ?
-				  CONFIG_CONSOLE_RECORD_OUT_SIZE :
-				  CONFIG_CONSOLE_RECORD_OUT_SIZE_F);
+	ret = membuf_new((struct membuf *)&gd->console_out,
+			 gd->flags & GD_FLG_RELOC ?
+				CONFIG_CONSOLE_RECORD_OUT_SIZE :
+				CONFIG_CONSOLE_RECORD_OUT_SIZE_F);
 	if (ret)
 		return ret;
-	ret = membuff_new((struct membuff *)&gd->console_in,
-			  CONFIG_CONSOLE_RECORD_IN_SIZE);
+	ret = membuf_new((struct membuf *)&gd->console_in,
+			 CONFIG_CONSOLE_RECORD_IN_SIZE);
 
 	/* Start recording from the beginning */
 	gd->flags |= GD_FLG_RECORD;
@@ -827,8 +827,8 @@ int console_record_init(void)
 
 void console_record_reset(void)
 {
-	membuff_purge((struct membuff *)&gd->console_out);
-	membuff_purge((struct membuff *)&gd->console_in);
+	membuf_purge((struct membuf *)&gd->console_out);
+	membuf_purge((struct membuf *)&gd->console_in);
 	gd->flags &= ~GD_FLG_RECORD_OVF;
 }
 
@@ -847,23 +847,23 @@ int console_record_readline(char *str, int maxlen)
 	if (console_record_isempty())
 		return -ENOENT;
 
-	return membuff_readline((struct membuff *)&gd->console_out, str,
+	return membuf_readline((struct membuf *)&gd->console_out, str,
 				maxlen, '\0', false);
 }
 
 int console_record_avail(void)
 {
-	return membuff_avail((struct membuff *)&gd->console_out);
+	return membuf_avail((struct membuf *)&gd->console_out);
 }
 
 bool console_record_isempty(void)
 {
-	return membuff_isempty((struct membuff *)&gd->console_out);
+	return membuf_isempty((struct membuf *)&gd->console_out);
 }
 
 int console_in_puts(const char *str)
 {
-	return membuff_put((struct membuff *)&gd->console_in, str, strlen(str));
+	return membuf_put((struct membuf *)&gd->console_in, str, strlen(str));
 }
 
 #endif
@@ -942,11 +942,6 @@ struct stdio_dev *console_search_dev(int flags, const char *name)
 	struct stdio_dev *dev;
 
 	dev = stdio_get_by_name(name);
-#ifdef CONFIG_VIDCONSOLE_AS_LCD
-	if (!dev && !strcmp(name, CONFIG_VIDCONSOLE_AS_NAME))
-		dev = stdio_get_by_name("vidconsole");
-#endif
-
 	if (dev && (dev->flags & flags))
 		return dev;
 
@@ -1154,12 +1149,6 @@ done:
 	if (!IS_ENABLED(CONFIG_SYS_CONSOLE_INFO_QUIET))
 		stdio_print_current_devices();
 
-#ifdef CONFIG_VIDCONSOLE_AS_LCD
-	if (strstr(stdoutname, CONFIG_VIDCONSOLE_AS_NAME))
-		printf("Warning: Please change '%s' to 'vidconsole' in stdout/stderr environment vars\n",
-		       CONFIG_VIDCONSOLE_AS_NAME);
-#endif
-
 	if (IS_ENABLED(CONFIG_SYS_CONSOLE_ENV_OVERWRITE)) {
 		/* set the environment variables (will overwrite previous env settings) */
 		for (i = 0; i < MAX_FILES; i++)
diff --git a/common/edid.c b/common/edid.c
index 48a737690db..e5aa4ca494f 100644
--- a/common/edid.c
+++ b/common/edid.c
@@ -16,6 +16,199 @@
 #include <linux/ctype.h>
 #include <linux/string.h>
 
+#if CONFIG_IS_ENABLED(I2C_EDID_STANDARD)
+#define TIMING(c, ha, hfp, hbp, hsl, va, vfp, vbp, vsl, f)	\
+	.pixelclock = { (c), (c), (c) },			\
+	.hactive = { (ha), (ha), (ha) },			\
+	.hfront_porch = { (hfp), (hfp), (hfp) },		\
+	.hback_porch = { (hbp), (hbp), (hbp) },			\
+	.hsync_len = { (hsl), (hsl), (hsl) },			\
+	.vactive = { (va), (va), (va) },			\
+	.vfront_porch = { (vfp), (vfp), (vfp) },		\
+	.vback_porch = { (vbp), (vbp), (vbp) },			\
+	.vsync_len = { (vsl), (vsl), (vsl) },			\
+	.flags = (f)
+
+static const struct display_timing dmt_timings[] = {
+	{ TIMING(31500000, 640, 32, 64, 96, 350, 32, 3, 60,
+		 DISPLAY_FLAGS_HSYNC_HIGH | DISPLAY_FLAGS_VSYNC_LOW) },
+	{ TIMING(31500000, 640, 32, 64, 96, 400, 1, 3, 41,
+		 DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_HIGH) },
+	{ TIMING(35500000, 720, 36, 72, 108, 400, 1, 3, 42,
+		 DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_HIGH) },
+	{ TIMING(25175000, 640, 16, 96, 48, 480, 10, 2, 33,
+		 DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW) },
+	{ TIMING(31500000, 640, 24, 40, 128, 480, 9, 3, 28,
+		 DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW) },
+	{ TIMING(31500000, 640, 16, 64, 120, 480, 1, 3, 16,
+		 DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW) },
+	{ TIMING(36000000, 640, 56, 56, 80, 480, 1, 3, 25,
+		 DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW) },
+	{ TIMING(36000000, 800, 24, 72, 128, 600, 1, 2, 22,
+		 DISPLAY_FLAGS_HSYNC_HIGH | DISPLAY_FLAGS_VSYNC_HIGH) },
+	{ TIMING(40000000, 800, 40, 128, 88, 600, 1, 4, 23,
+		 DISPLAY_FLAGS_HSYNC_HIGH | DISPLAY_FLAGS_VSYNC_HIGH) },
+	{ TIMING(50000000, 800, 56, 120, 64, 600, 37, 6, 23,
+		 DISPLAY_FLAGS_HSYNC_HIGH | DISPLAY_FLAGS_VSYNC_HIGH) },
+	{ TIMING(49500000, 800, 16, 80, 160, 600, 1, 3, 21,
+		 DISPLAY_FLAGS_HSYNC_HIGH | DISPLAY_FLAGS_VSYNC_HIGH) },
+	{ TIMING(56250000, 800, 32, 64, 152, 600, 1, 3, 27,
+		 DISPLAY_FLAGS_HSYNC_HIGH | DISPLAY_FLAGS_VSYNC_HIGH) },
+	{ TIMING(73250000, 800, 48, 32, 80, 600, 3, 4, 29,
+		 DISPLAY_FLAGS_HSYNC_HIGH | DISPLAY_FLAGS_VSYNC_LOW) },
+	{ TIMING(33750000, 848, 16, 112, 112, 480, 6, 8, 23,
+		 DISPLAY_FLAGS_HSYNC_HIGH | DISPLAY_FLAGS_VSYNC_HIGH) },
+	{ TIMING(44900000, 1024, 8, 176, 56, 768, 0, 8, 41,
+		 DISPLAY_FLAGS_HSYNC_HIGH | DISPLAY_FLAGS_VSYNC_HIGH) },
+	{ TIMING(65000000, 1024, 24, 136, 160, 768, 3, 6, 29,
+		 DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW) },
+	{ TIMING(75000000, 1024, 24, 136, 144, 768, 3, 6, 29,
+		 DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW) },
+	{ TIMING(78750000, 1024, 16, 96, 176, 768, 1, 3, 28,
+		 DISPLAY_FLAGS_HSYNC_HIGH | DISPLAY_FLAGS_VSYNC_HIGH) },
+	{ TIMING(94500000, 1024, 48, 96, 208, 768, 1, 3, 36,
+		 DISPLAY_FLAGS_HSYNC_HIGH | DISPLAY_FLAGS_VSYNC_HIGH) },
+	{ TIMING(115500000, 1024, 48, 32, 80, 768, 3, 4, 38,
+		 DISPLAY_FLAGS_HSYNC_HIGH | DISPLAY_FLAGS_VSYNC_LOW) },
+	{ TIMING(108000000, 1152, 64, 128, 256, 864, 1, 3, 32,
+		 DISPLAY_FLAGS_HSYNC_HIGH | DISPLAY_FLAGS_VSYNC_HIGH) },
+	{ TIMING(74250000, 1280, 110, 40, 220, 720, 5, 5, 20,
+		 DISPLAY_FLAGS_HSYNC_HIGH | DISPLAY_FLAGS_VSYNC_HIGH) },
+	{ TIMING(68250000, 1280, 48, 32, 80, 768, 3, 7, 12,
+		 DISPLAY_FLAGS_HSYNC_HIGH | DISPLAY_FLAGS_VSYNC_LOW) },
+	{ TIMING(79500000, 1280, 64, 128, 192, 768, 3, 7, 20,
+		 DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_HIGH) },
+	{ TIMING(102250000, 1280, 80, 128, 208, 768, 3, 7, 27,
+		 DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_HIGH) },
+	{ TIMING(117500000, 1280, 80, 136, 216, 768, 3, 7, 31,
+		 DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_HIGH) },
+	{ TIMING(140250000, 1280, 48, 32, 80, 768, 3, 7, 35,
+		 DISPLAY_FLAGS_HSYNC_HIGH | DISPLAY_FLAGS_VSYNC_LOW) },
+	{ TIMING(71000000, 1280, 48, 32, 80, 800, 3, 6, 14,
+		 DISPLAY_FLAGS_HSYNC_HIGH | DISPLAY_FLAGS_VSYNC_LOW) },
+	{ TIMING(83500000, 1280, 72, 128, 200, 800, 3, 6, 22,
+		 DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_HIGH) },
+	{ TIMING(106500000, 1280, 80, 128, 208, 800, 3, 6, 29,
+		 DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_HIGH) },
+	{ TIMING(122500000, 1280, 80, 136, 216, 800, 3, 6, 34,
+		 DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_HIGH) },
+	{ TIMING(146250000, 1280, 48, 32, 80, 800, 3, 6, 38,
+		 DISPLAY_FLAGS_HSYNC_HIGH | DISPLAY_FLAGS_VSYNC_LOW) },
+	{ TIMING(108000000, 1280, 96, 112, 312, 960, 1, 3, 36,
+		 DISPLAY_FLAGS_HSYNC_HIGH | DISPLAY_FLAGS_VSYNC_HIGH) },
+	{ TIMING(148500000, 1280, 64, 160, 224, 960, 1, 3, 47,
+		 DISPLAY_FLAGS_HSYNC_HIGH | DISPLAY_FLAGS_VSYNC_HIGH) },
+	{ TIMING(175500000, 1280, 48, 32, 80, 960, 3, 4, 50,
+		 DISPLAY_FLAGS_HSYNC_HIGH | DISPLAY_FLAGS_VSYNC_LOW) },
+	{ TIMING(108000000, 1280, 48, 112, 248, 1024, 1, 3, 38,
+		 DISPLAY_FLAGS_HSYNC_HIGH | DISPLAY_FLAGS_VSYNC_HIGH) },
+	{ TIMING(135000000, 1280, 16, 144, 248, 1024, 1, 3, 38,
+		 DISPLAY_FLAGS_HSYNC_HIGH | DISPLAY_FLAGS_VSYNC_HIGH) },
+	{ TIMING(157500000, 1280, 64, 160, 224, 1024, 1, 3, 44,
+		 DISPLAY_FLAGS_HSYNC_HIGH | DISPLAY_FLAGS_VSYNC_HIGH) },
+	{ TIMING(187250000, 1280, 48, 32, 80, 1024, 3, 7, 50,
+		 DISPLAY_FLAGS_HSYNC_HIGH | DISPLAY_FLAGS_VSYNC_LOW) },
+	{ TIMING(85500000, 1360, 64, 112, 256, 768, 3, 6, 18,
+		 DISPLAY_FLAGS_HSYNC_HIGH | DISPLAY_FLAGS_VSYNC_HIGH) },
+	{ TIMING(148250000, 1360, 48, 32, 80, 768, 3, 5, 37,
+		 DISPLAY_FLAGS_HSYNC_HIGH | DISPLAY_FLAGS_VSYNC_LOW) },
+	{ TIMING(85500000, 1366, 70, 143, 213, 768, 3, 3, 24,
+		 DISPLAY_FLAGS_HSYNC_HIGH | DISPLAY_FLAGS_VSYNC_HIGH) },
+	{ TIMING(72000000, 1366, 14, 56, 64, 768, 1, 3, 28,
+		 DISPLAY_FLAGS_HSYNC_HIGH | DISPLAY_FLAGS_VSYNC_HIGH) },
+	{ TIMING(101000000, 1400, 48, 32, 80, 1050, 3, 4, 23,
+		 DISPLAY_FLAGS_HSYNC_HIGH | DISPLAY_FLAGS_VSYNC_LOW) },
+	{ TIMING(121750000, 1400, 88, 144, 232, 1050, 3, 4, 32,
+		 DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_HIGH) },
+	{ TIMING(156000000, 1400, 104, 144, 248, 1050, 3, 4, 42,
+		 DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_HIGH) },
+	{ TIMING(179500000, 1400, 104, 152, 256, 1050, 3, 4, 48,
+		 DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_HIGH) },
+	{ TIMING(208000000, 1400, 48, 32, 80, 1050, 3, 4, 55,
+		 DISPLAY_FLAGS_HSYNC_HIGH | DISPLAY_FLAGS_VSYNC_LOW) },
+	{ TIMING(88750000, 1440, 48, 32, 80, 900, 3, 6, 17,
+		 DISPLAY_FLAGS_HSYNC_HIGH | DISPLAY_FLAGS_VSYNC_LOW) },
+	{ TIMING(106500000, 1440, 80, 152, 232, 900, 3, 6, 25,
+		 DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_HIGH) },
+	{ TIMING(136750000, 1440, 96, 152, 248, 900, 3, 6, 33,
+		 DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_HIGH) },
+	{ TIMING(157000000, 1440, 104, 152, 256, 900, 3, 6, 39,
+		 DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_HIGH) },
+	{ TIMING(182750000, 1440, 48, 32, 80, 900, 3, 6, 44,
+		 DISPLAY_FLAGS_HSYNC_HIGH | DISPLAY_FLAGS_VSYNC_LOW) },
+	{ TIMING(108000000, 1600, 24, 80, 96, 900, 1, 3, 96,
+		 DISPLAY_FLAGS_HSYNC_HIGH | DISPLAY_FLAGS_VSYNC_HIGH) },
+	{ TIMING(162000000, 1600, 64, 192, 304, 1200, 1, 3, 46,
+		 DISPLAY_FLAGS_HSYNC_HIGH | DISPLAY_FLAGS_VSYNC_HIGH) },
+	{ TIMING(175500000, 1600, 64, 192, 304, 1200, 1, 3, 46,
+		 DISPLAY_FLAGS_HSYNC_HIGH | DISPLAY_FLAGS_VSYNC_HIGH) },
+	{ TIMING(189000000, 1600, 64, 192, 304, 1200, 1, 3, 46,
+		 DISPLAY_FLAGS_HSYNC_HIGH | DISPLAY_FLAGS_VSYNC_HIGH) },
+	{ TIMING(202500000, 1600, 64, 192, 304, 1200, 1, 3, 46,
+		 DISPLAY_FLAGS_HSYNC_HIGH | DISPLAY_FLAGS_VSYNC_HIGH) },
+	{ TIMING(229500000, 1600, 64, 192, 304, 1200, 1, 3, 46,
+		 DISPLAY_FLAGS_HSYNC_HIGH | DISPLAY_FLAGS_VSYNC_HIGH) },
+	{ TIMING(268250000, 1600, 48, 32, 80, 1200, 3, 4, 64,
+		 DISPLAY_FLAGS_HSYNC_HIGH | DISPLAY_FLAGS_VSYNC_LOW) },
+	{ TIMING(119000000, 1680, 48, 32, 80, 1050, 3, 6, 21,
+		 DISPLAY_FLAGS_HSYNC_HIGH | DISPLAY_FLAGS_VSYNC_LOW) },
+	{ TIMING(146250000, 1680, 104, 176, 280, 1050, 3, 6, 30,
+		 DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_HIGH) },
+	{ TIMING(187000000, 1680, 120, 176, 296, 1050, 3, 6, 40,
+		 DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_HIGH) },
+	{ TIMING(214750000, 1680, 128, 176, 304, 1050, 3, 6, 46,
+		 DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_HIGH) },
+	{ TIMING(245500000, 1680, 48, 32, 80, 1050, 3, 6, 53,
+		 DISPLAY_FLAGS_HSYNC_HIGH | DISPLAY_FLAGS_VSYNC_LOW) },
+	{ TIMING(204750000, 1792, 128, 200, 328, 1344, 1, 3, 46,
+		 DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_HIGH) },
+	{ TIMING(261000000, 1792, 96, 216, 352, 1344, 1, 3, 69,
+		 DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_HIGH) },
+	{ TIMING(333250000, 1792, 48, 32, 80, 1344, 3, 4, 72,
+		 DISPLAY_FLAGS_HSYNC_HIGH | DISPLAY_FLAGS_VSYNC_LOW) },
+	{ TIMING(218250000, 1856, 96, 224, 352, 1392, 1, 3, 43,
+		 DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_HIGH) },
+	{ TIMING(288000000, 1856, 128, 224, 352, 1392, 1, 3, 104,
+		 DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_HIGH) },
+	{ TIMING(356500000, 1856, 48, 32, 80, 1392, 3, 4, 75,
+		 DISPLAY_FLAGS_HSYNC_HIGH | DISPLAY_FLAGS_VSYNC_LOW) },
+	{ TIMING(148500000, 1920, 88, 44, 148, 1080, 4, 5, 36,
+		 DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW) },
+	{ TIMING(154000000, 1920, 48, 32, 80, 1200, 3, 6, 26,
+		 DISPLAY_FLAGS_HSYNC_HIGH | DISPLAY_FLAGS_VSYNC_LOW) },
+	{ TIMING(193250000, 1920, 136, 200, 336, 1200, 3, 6, 36,
+		 DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_HIGH) },
+	{ TIMING(245250000, 1920, 136, 208, 344, 1200, 3, 6, 46,
+		 DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_HIGH) },
+	{ TIMING(281250000, 1920, 144, 208, 352, 1200, 3, 6, 53,
+		 DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_HIGH) },
+	{ TIMING(317000000, 1920, 48, 32, 80, 1200, 3, 6, 62,
+		 DISPLAY_FLAGS_HSYNC_HIGH | DISPLAY_FLAGS_VSYNC_LOW) },
+	{ TIMING(234000000, 1920, 128, 208, 344, 1440, 1, 3, 56,
+		 DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_HIGH) },
+	{ TIMING(297000000, 1920, 144, 224, 352, 1440, 1, 3, 56,
+		 DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_HIGH) },
+	{ TIMING(380500000, 1920, 48, 32, 80, 1440, 3, 4, 78,
+		 DISPLAY_FLAGS_HSYNC_HIGH | DISPLAY_FLAGS_VSYNC_LOW) },
+	{ TIMING(162000000, 2048, 26, 80, 96, 1152, 1, 3, 44,
+		 DISPLAY_FLAGS_HSYNC_HIGH | DISPLAY_FLAGS_VSYNC_HIGH) },
+	{ TIMING(268500000, 2560, 48, 32, 80, 1600, 3, 6, 37,
+		 DISPLAY_FLAGS_HSYNC_HIGH | DISPLAY_FLAGS_VSYNC_LOW) },
+	{ TIMING(348500000, 2560, 192, 280, 472, 1600, 3, 6, 49,
+		 DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_HIGH) },
+	{ TIMING(443250000, 2560, 208, 280, 488, 1600, 3, 6, 63,
+		 DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_HIGH) },
+	{ TIMING(505250000, 2560, 208, 280, 488, 1600, 3, 6, 73,
+		 DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_HIGH) },
+	{ TIMING(552750000, 2560, 48, 32, 80, 1600, 3, 6, 85,
+		 DISPLAY_FLAGS_HSYNC_HIGH | DISPLAY_FLAGS_VSYNC_LOW) },
+	{ TIMING(556744000, 4096, 8, 32, 40, 2160, 48, 8, 6,
+		 DISPLAY_FLAGS_HSYNC_HIGH | DISPLAY_FLAGS_VSYNC_LOW) },
+	{ TIMING(556188000, 4096, 8, 32, 40, 2160, 48, 8, 6,
+		 DISPLAY_FLAGS_HSYNC_HIGH | DISPLAY_FLAGS_VSYNC_LOW) },
+};
+#endif
+
 int edid_check_info(struct edid1_info *edid_info)
 {
 	if ((edid_info == NULL) || (edid_info->version == 0))
@@ -168,11 +361,11 @@ static bool cea_is_hdmi_vsdb_present(struct edid_cea861_info *info)
 	return false;
 }
 
-static bool edid_find_valid_timing(void *buf, int count,
-				   struct display_timing *timing,
-				   bool (*mode_valid)(void *priv,
-					const struct display_timing *timing),
-				   void *mode_valid_priv)
+static bool edid_find_valid_detailed_timing(void *buf, int count,
+					    struct display_timing *timing,
+					    bool (*mode_valid)(void *priv,
+						const struct display_timing *timing),
+					    void *mode_valid_priv)
 {
 	struct edid_detailed_timing *t = buf;
 	bool found = false;
@@ -191,6 +384,73 @@ static bool edid_find_valid_timing(void *buf, int count,
 	return found;
 }
 
+static bool edid_get_standard_timing(struct edid1_info *edid, int i, unsigned int *x,
+				     unsigned int *y, unsigned int *freq)
+{
+	unsigned int aspect = 10000;
+	unsigned char xres, vfreq;
+
+	xres = EDID1_INFO_STANDARD_TIMING_XRESOLUTION(*edid, i);
+	vfreq = EDID1_INFO_STANDARD_TIMING_VFREQ(*edid, i);
+	if (xres != vfreq || (xres != 0 && xres != 1) ||
+	    (vfreq != 0 && vfreq != 1)) {
+		switch (EDID1_INFO_STANDARD_TIMING_ASPECT(*edid, i)) {
+		case ASPECT_625: // 16:10
+			aspect = 6250;
+			break;
+		case ASPECT_75: // 4:3
+			aspect = 7500;
+			break;
+		case ASPECT_8: // 5:4
+			aspect = 8000;
+			break;
+		case ASPECT_5625: // 16:9
+			aspect = 5625;
+			break;
+		}
+
+		*x = (xres + 31) * 8;
+		*y = *x * aspect / 10000;
+		*freq = (vfreq & 0x3f) + 60;
+
+		return true;
+	}
+
+	return false;
+}
+
+#if CONFIG_IS_ENABLED(I2C_EDID_STANDARD)
+static bool edid_find_valid_standard_timing(struct edid1_info *buf,
+					    struct display_timing *timing,
+					    bool (*mode_valid)(void *priv,
+						const struct display_timing *timing),
+					    void *mode_valid_priv)
+{
+	unsigned int x, y, freq;
+	bool found = false;
+	int i, k;
+
+	for (i = 0; i < ARRAY_SIZE(buf->standard_timings); i++) {
+		if (!edid_get_standard_timing(buf, i, &x, &y, &freq))
+			continue;
+
+		for (k = 0; k < ARRAY_SIZE(dmt_timings); k++) {
+			const struct display_timing *dt = &dmt_timings[k];
+
+			if (dt->hactive.typ == x && dt->vactive.typ == y) {
+				found = mode_valid(mode_valid_priv, dt);
+				if (found) {
+					memcpy(timing, dt, sizeof(*timing));
+					return true;
+				}
+			}
+		}
+	}
+
+	return found;
+}
+#endif
+
 int edid_get_timing_validate(u8 *buf, int buf_size,
 			     struct display_timing *timing,
 			     int *panel_bits_per_colourp,
@@ -217,8 +477,8 @@ int edid_get_timing_validate(u8 *buf, int buf_size,
 	}
 
 	/* Look for detailed timing in base EDID */
-	found = edid_find_valid_timing(edid->monitor_details.descriptor, 4,
-				       timing, mode_valid, mode_valid_priv);
+	found = edid_find_valid_detailed_timing(edid->monitor_details.descriptor, 4,
+						timing, mode_valid, mode_valid_priv);
 
 	/* Look for detailed timing in CTA-861 Extension Block */
 	if (!found && edid->extension_flag && buf_size >= EDID_EXT_SIZE) {
@@ -231,12 +491,19 @@ int edid_get_timing_validate(u8 *buf, int buf_size,
 			int size = count * sizeof(struct edid_detailed_timing);
 
 			if (offset >= 4 && offset + size < EDID_SIZE)
-				found = edid_find_valid_timing(
+				found = edid_find_valid_detailed_timing(
 					(u8 *)info + offset, count, timing,
 					mode_valid, mode_valid_priv);
 		}
 	}
 
+#if CONFIG_IS_ENABLED(I2C_EDID_STANDARD)
+	/* Look for timing in Standard Timings */
+	if (!found)
+		found = edid_find_valid_standard_timing(edid, timing, mode_valid,
+							mode_valid_priv);
+#endif
+
 	if (!found)
 		return -EINVAL;
 
@@ -461,34 +728,11 @@ void edid_print_info(struct edid1_info *edid_info)
 	/* Standard timings. */
 	printf("Standard timings:\n");
 	for (i = 0; i < ARRAY_SIZE(edid_info->standard_timings); i++) {
-		unsigned int aspect = 10000;
-		unsigned int x, y;
-		unsigned char xres, vfreq;
-
-		xres = EDID1_INFO_STANDARD_TIMING_XRESOLUTION(*edid_info, i);
-		vfreq = EDID1_INFO_STANDARD_TIMING_VFREQ(*edid_info, i);
-		if ((xres != vfreq) ||
-		    ((xres != 0) && (xres != 1)) ||
-		    ((vfreq != 0) && (vfreq != 1))) {
-			switch (EDID1_INFO_STANDARD_TIMING_ASPECT(*edid_info,
-					i)) {
-			case ASPECT_625:
-				aspect = 6250;
-				break;
-			case ASPECT_75:
-				aspect = 7500;
-				break;
-			case ASPECT_8:
-				aspect = 8000;
-				break;
-			case ASPECT_5625:
-				aspect = 5625;
-				break;
-			}
-			x = (xres + 31) * 8;
-			y = x * aspect / 10000;
+		unsigned int x, y, freq;
+
+		if (edid_get_standard_timing(edid_info, i, &x, &y, &freq)) {
 			printf("\t%dx%d%c\t%d Hz\n", x, y,
-			       x > 1000 ? ' ' : '\t', (vfreq & 0x3f) + 60);
+			       x > 1000 ? ' ' : '\t', freq);
 			have_timing = 1;
 		}
 	}
diff --git a/common/miiphyutil.c b/common/miiphyutil.c
index 6169ea884ae..274e88a4921 100644
--- a/common/miiphyutil.c
+++ b/common/miiphyutil.c
@@ -65,7 +65,7 @@ struct mii_dev *mdio_alloc(void)
 
 	memset(bus, 0, sizeof(*bus));
 
-	/* initalize mii_dev struct fields */
+	/* initialize mii_dev struct fields */
 	INIT_LIST_HEAD(&bus->link);
 
 	return bus;
diff --git a/common/spl/Kconfig b/common/spl/Kconfig
index 94e118f8465..c08045f9c8d 100644
--- a/common/spl/Kconfig
+++ b/common/spl/Kconfig
@@ -80,11 +80,10 @@ config SPL_MAX_SIZE
 	default 0x1b000 if AM33XX && !TI_SECURE_DEVICE
 	default 0xec00 if OMAP34XX
 	default 0x10000 if ARCH_MX6 && !MX6_OCRAM_256KB
-	default 0x7fa0 if SUNXI_SRAM_ADDRESS = 0x10000
-	default 0x7fa0 if SUNXI_SRAM_ADDRESS = 0x20000 && !MACH_SUN50I_H616
 	default 0xbfa0 if MACH_SUN50I_H616
 	default 0x7000 if RCAR_GEN3
 	default 0x5fa0 if SUNXI_SRAM_ADDRESS = 0x0
+	default 0x7fa0 if ARCH_SUNXI
 	default 0x10000 if ASPEED_AST2600
 	default 0x27000 if IMX8MM && SPL_TEXT_BASE = 0x7E1000
 	default 0x30000 if ARCH_SC5XX && (SC59X_64 || SC59X)
@@ -387,11 +386,29 @@ config SPL_SHARES_INIT_SP_ADDR
 	  both SPL and U-Boot itself.  If you need to specify a different address
 	  however, say N here and then set a different value in CONFIG_SPL_STACK.
 
-config SPL_STACK
-	hex "Initial stack pointer location"
+config SPL_HAVE_INIT_STACK
+	bool "SPL requires a initial, fixed, stack-pointer location"
 	depends on (ARM || ARCH_JZ47XX || MICROBLAZE || RISCV) && \
 		SPL_FRAMEWORK || ROCKCHIP_RK3036
 	depends on !SPL_SHARES_INIT_SP_ADDR
+	default y if ARCH_MX7
+	default y if ARCH_MX6 && MX6_OCRAM_256KB
+	default y if ARCH_MX6 && !MX6_OCRAM_256KB
+	default y if MACH_SUN50I_H6 || MACH_SUN50I_H616 || MACH_SUN8I_R528
+	default y if MACH_SUN50I || MACH_SUN50I_H5
+	default y if MACH_SUN9I
+	default y if ARCH_SUNXI
+	default y if ARCH_SC5XX && (SC59X_64 || SC59X)
+	default y if ARCH_SC5XX && SC58X
+	default y if ARCH_SC5XX && SC57X
+	help
+	  Enable if the SPL phase should not use inherit its initial
+	  stack-pointer from the settings for U-Boot proper, but should set
+	  its own value.
+
+config SPL_STACK
+	hex "Address of the initial stack-pointer for the SPL phase"
+	depends on SPL_HAVE_INIT_STACK
 	default 0x946bb8 if ARCH_MX7
 	default 0x93ffb8 if ARCH_MX6 && MX6_OCRAM_256KB
 	default 0x91ffb8 if ARCH_MX6 && !MX6_OCRAM_256KB
@@ -401,9 +418,9 @@ config SPL_STACK
 	default 0x54000 if MACH_SUN50I || MACH_SUN50I_H5
 	default 0x18000 if MACH_SUN9I
 	default 0x8000 if ARCH_SUNXI
-	default 0x200E4000 if ARCH_SC5XX && (SC59X_64 || SC59X)
-	default 0x200B0000 if ARCH_SC5XX && SC58X
-	default 0x200D0000 if ARCH_SC5XX && SC57X
+	default 0x200e4000 if ARCH_SC5XX && (SC59X_64 || SC59X)
+	default 0x200b0000 if ARCH_SC5XX && SC58X
+	default 0x200d0000 if ARCH_SC5XX && SC57X
 	help
 	  Address of the start of the stack SPL will use before SDRAM is
 	  initialized.
@@ -1287,6 +1304,7 @@ config SPL_RAM_DEVICE
 
 config SPL_REMOTEPROC
 	bool "Support REMOTEPROCS"
+	default y if (CPU_V7R && ARCH_K3)
 	help
 	  Enable support for REMOTEPROCs in SPL. This permits to load
 	  a remote processor firmware in SPL.
@@ -1431,6 +1449,24 @@ config SYS_SPI_U_BOOT_OFFS
 	 Address within SPI-Flash from where the u-boot payload is fetched
 	 from.
 
+config SYS_SPI_KERNEL_OFFS
+	hex "Falcon mode: address of kernel payload in SPI flash"
+	depends on SPL_SPI_FLASH_SUPPORT && SPL_OS_BOOT
+	help
+	 Address within SPI-Flash from where the kernel payload is fetched
+	 in falcon boot.
+
+config SYS_SPI_ARGS_OFFS
+	hex "Falcon mode: address of args payload in SPI flash"
+	depends on SPL_SPI_FLASH_SUPPORT && SPL_OS_BOOT
+	help
+	 Address within SPI-Flash from where the args payload (usually the
+	 dtb) is fetched in falcon boot.
+
+config SYS_SPI_ARGS_SIZE
+	hex "Falcon mode: size of args payload in SPI flash"
+	depends on SPL_SPI_FLASH_SUPPORT && SPL_OS_BOOT
+
 config SPL_THERMAL
 	bool "Driver support for thermal devices"
 	help
diff --git a/common/spl/Kconfig.tpl b/common/spl/Kconfig.tpl
index 22ca7016453..a535b61ecd3 100644
--- a/common/spl/Kconfig.tpl
+++ b/common/spl/Kconfig.tpl
@@ -106,12 +106,6 @@ config TPL_LDSCRIPT
 	  May be left empty to trigger the Makefile infrastructure to
 	  fall back to the linker-script used for the SPL stage.
 
-config TPL_NEEDS_SEPARATE_STACK
-	bool "TPL needs a separate initial stack-pointer"
-	help
-	  Enable, if the TPL stage should not inherit its initial
-	  stack-pointer from the settings for the SPL stage.
-
 config TPL_POWER
 	bool "Support power drivers"
 	help
@@ -140,11 +134,18 @@ config TPL_MAX_SIZE
 	help
 	  The maximum size (in bytes) of the TPL stage.
 
+config TPL_HAVE_INIT_STACK
+	bool "TPL requires a initial, fixed, stack-pointer location"
+	help
+	  Enable if the TPL phase should not inherit its initial
+	  stack-pointer from the settings for U-Boot proper, but should set its
+	  own value.
+
 config TPL_STACK
-	hex "Address of the initial stack-pointer for the TPL stage"
-	depends on TPL_NEEDS_SEPARATE_STACK
+	hex "Address of the initial stack-pointer for the TPL phase"
+	depends on TPL_HAVE_INIT_STACK
 	help
-	  The address of the initial stack-pointer for the TPL stage.
+	  The address of the initial stack-pointer for the TPL phase
 	  Usually this will be the (aligned) top-of-stack.
 
 config TPL_READ_ONLY
diff --git a/common/spl/Kconfig.vpl b/common/spl/Kconfig.vpl
index cf6b36c8e38..434562443ac 100644
--- a/common/spl/Kconfig.vpl
+++ b/common/spl/Kconfig.vpl
@@ -266,6 +266,20 @@ config VPL_MAX_SIZE
 	  The maximum size (in bytes) of the TPL stage. This size is determined
 	  by the amount of internal SRAM memory.
 
+config VPL_HAVE_INIT_STACK
+	bool "VPL requires a initial, fixed, stack-pointer location"
+	help
+	  Enable if the VPL phase should not use inherit its initial
+	  stack-pointer from the settings for U-Boot proper, but should set
+	  its own value.
+
+config VPL_STACK
+	hex "Address of the initial stack-pointer for the VPL phase"
+	depends on VPL_HAVE_INIT_STACK
+	help
+	  The address of the initial stack-pointer for the VPL phase
+	  Usually this will be the (aligned) top-of-stack.
+
 config VPL_BINMAN_SYMBOLS
 	bool "Declare binman symbols in VPL"
 	depends on VPL_FRAMEWORK && BINMAN
diff --git a/common/spl/spl_ext.c b/common/spl/spl_ext.c
index c5478820a9b..7e0274a3058 100644
--- a/common/spl/spl_ext.c
+++ b/common/spl/spl_ext.c
@@ -11,12 +11,20 @@
 static ulong spl_fit_read(struct spl_load_info *load, ulong file_offset,
 			  ulong size, void *buf)
 {
+	struct legacy_img_hdr *header;
 	int ret;
 	loff_t actlen;
 
 	ret = ext4fs_read(buf, file_offset, size, &actlen);
 	if (ret)
 		return ret;
+
+	if (CONFIG_IS_ENABLED(OS_BOOT)) {
+		header = (struct legacy_img_hdr *)buf;
+		if (image_get_magic(header) != FDT_MAGIC)
+			return size;
+	}
+
 	return actlen;
 }
 
diff --git a/common/spl/spl_fat.c b/common/spl/spl_fat.c
index fce451b7664..f426a068ff9 100644
--- a/common/spl/spl_fat.c
+++ b/common/spl/spl_fat.c
@@ -47,6 +47,7 @@ static int spl_register_fat_device(struct blk_desc *block_dev, int partition)
 static ulong spl_fit_read(struct spl_load_info *load, ulong file_offset,
 			  ulong size, void *buf)
 {
+	struct legacy_img_hdr *header;
 	loff_t actread;
 	int ret;
 	char *filename = load->priv;
@@ -55,6 +56,12 @@ static ulong spl_fit_read(struct spl_load_info *load, ulong file_offset,
 	if (ret)
 		return ret;
 
+	if (CONFIG_IS_ENABLED(OS_BOOT)) {
+		header = (struct legacy_img_hdr *)buf;
+		if (image_get_magic(header) != FDT_MAGIC)
+			return size;
+	}
+
 	return actread;
 }
 
diff --git a/common/spl/spl_fit.c b/common/spl/spl_fit.c
index 49b4df60560..86506d6905c 100644
--- a/common/spl/spl_fit.c
+++ b/common/spl/spl_fit.c
@@ -397,7 +397,7 @@ static int spl_fit_append_fdt(struct spl_image_info *spl_image,
 	 * Use the address following the image as target address for the
 	 * device tree.
 	 */
-	image_info.load_addr = spl_image->load_addr + spl_image->size;
+	image_info.load_addr = ALIGN(spl_image->load_addr + spl_image->size, 8);
 
 	/* Figure out which device tree the board wants to use */
 	node = spl_fit_get_image_node(ctx, FIT_FDT_PROP, index++);
diff --git a/common/spl/spl_opensbi.c b/common/spl/spl_opensbi.c
index 5a26d7c31a4..0ed6afeacc6 100644
--- a/common/spl/spl_opensbi.c
+++ b/common/spl/spl_opensbi.c
@@ -57,6 +57,11 @@ void __noreturn spl_invoke_opensbi(struct spl_image_info *spl_image)
 		hang();
 	}
 
+	if (!IS_ALIGNED((uintptr_t)spl_image->fdt_addr, 8)) {
+		pr_err("SPL image loaded an improperly-aligned device tree\n");
+		hang();
+	}
+
 	/*
 	 * Originally, u-boot-spl will place DTB directly after the kernel,
 	 * but the size of the kernel did not include the BSS section, which
diff --git a/common/spl/spl_spi.c b/common/spl/spl_spi.c
index 691a431a926..00dbd3011f0 100644
--- a/common/spl/spl_spi.c
+++ b/common/spl/spl_spi.c
@@ -82,13 +82,14 @@ static int spl_spi_load_image(struct spl_image_info *spl_image,
 #if CONFIG_IS_ENABLED(OS_BOOT)
 	if (spl_start_uboot()) {
 		int err = spl_load(spl_image, bootdev, &load, 0,
-				   CFG_SYS_SPI_KERNEL_OFFS);
+				   CONFIG_SYS_SPI_KERNEL_OFFS);
 
 		if (!err)
 			/* Read device tree. */
-			return spi_flash_read(flash, CFG_SYS_SPI_ARGS_OFFS,
-					      CFG_SYS_SPI_ARGS_SIZE,
-					      (void *)CONFIG_SPL_PAYLOAD_ARGS_ADDR);
+			return spi_flash_read(
+				flash, CONFIG_SYS_SPI_ARGS_OFFS,
+				CONFIG_SYS_SPI_ARGS_SIZE,
+				(void *)CONFIG_SPL_PAYLOAD_ARGS_ADDR);
 	}
 #endif
 
diff --git a/common/stdio.c b/common/stdio.c
index a61220ce4b9..3eeb289dd8b 100644
--- a/common/stdio.c
+++ b/common/stdio.c
@@ -357,9 +357,6 @@ int stdio_add_devices(void)
 
 	drv_system_init();
 	serial_stdio_init();
-#ifdef CONFIG_USB_TTY
-	drv_usbtty_init();
-#endif
 #ifdef CONFIG_USB_FUNCTION_ACM
 	drv_usbacm_init ();
 #endif
diff --git a/configs/alt_defconfig b/configs/alt_defconfig
index 7b16923e34d..29b98f1b7bc 100644
--- a/configs/alt_defconfig
+++ b/configs/alt_defconfig
@@ -14,6 +14,7 @@ CONFIG_ARCH_RENESAS_BOARD_STRING="Alt"
 CONFIG_R8A7794=y
 CONFIG_TARGET_ALT=y
 CONFIG_SPL_SERIAL=y
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_STACK=0xe6340000
 CONFIG_SPL_SYS_MALLOC_F_LEN=0x2000
 CONFIG_SPL=y
diff --git a/configs/am335x_guardian_defconfig b/configs/am335x_guardian_defconfig
index 4059d07b5c8..c550e5e121e 100644
--- a/configs/am335x_guardian_defconfig
+++ b/configs/am335x_guardian_defconfig
@@ -77,6 +77,7 @@ CONFIG_SPL_DM=y
 CONFIG_REGMAP=y
 CONFIG_BOOTCOUNT_LIMIT=y
 CONFIG_BOOTCOUNT_AM33XX_NVMEM=y
+CONFIG_BOOTCOUNT_ALTBOOTCMD="setenv boot_syslinux_conf \"extlinux/extlinux-rollback.conf\"; run distro_bootcmd; setenv boot_syslinux_conf \"extlinux/extlinux.conf\"; run bootcmd_ubifs0;"
 CONFIG_CLK=y
 CONFIG_CLK_CCF=y
 CONFIG_CLK_TI_AM3_DPLL=y
diff --git a/configs/am57xx_evm_defconfig b/configs/am57xx_evm_defconfig
index d10d2a5940f..24212082c3b 100644
--- a/configs/am57xx_evm_defconfig
+++ b/configs/am57xx_evm_defconfig
@@ -10,7 +10,6 @@ CONFIG_TARGET_AM57XX_EVM=y
 CONFIG_SPL_TEXT_BASE=0x40300000
 CONFIG_SYS_BOOTM_LEN=0x4000000
 CONFIG_SPL=y
-CONFIG_ENV_OFFSET_REDUND=0x280000
 CONFIG_SPL_SPI_FLASH_SUPPORT=y
 CONFIG_SPL_SPI=y
 CONFIG_ARMV7_LPAE=y
@@ -41,6 +40,9 @@ CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR=0x1500
 CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS=0x200
 CONFIG_SPL_SPI_LOAD=y
 CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000
+CONFIG_SYS_SPI_KERNEL_OFFS=0x1E0000
+CONFIG_SYS_SPI_ARGS_OFFS=0x140000
+CONFIG_SYS_SPI_ARGS_SIZE=0x80000
 CONFIG_SPL_YMODEM_SUPPORT=y
 CONFIG_CMD_ADTIMG=y
 CONFIG_CMD_ABOOTIMG=y
@@ -54,8 +56,7 @@ CONFIG_CMD_AVB=y
 CONFIG_OF_CONTROL=y
 CONFIG_SPL_OF_CONTROL=y
 CONFIG_OF_LIST="am57xx-beagle-x15 am57xx-beagle-x15-revb1 am57xx-beagle-x15-revc am5729-beagleboneai am572x-idk am571x-idk am574x-idk"
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_MMC=y
+# CONFIG_ENV_IS_IN_FAT is not set
 CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_SYS_MMC_ENV_DEV=1
diff --git a/configs/am57xx_hs_evm_defconfig b/configs/am57xx_hs_evm_defconfig
index 5cacd7f9cc5..2fc5e35873f 100644
--- a/configs/am57xx_hs_evm_defconfig
+++ b/configs/am57xx_hs_evm_defconfig
@@ -13,7 +13,6 @@ CONFIG_TI_SECURE_EMIF_PROTECTED_REGION_SIZE=0x01c00000
 CONFIG_TARGET_AM57XX_EVM=y
 CONFIG_SYS_BOOTM_LEN=0x4000000
 CONFIG_SPL=y
-CONFIG_ENV_OFFSET_REDUND=0x280000
 CONFIG_SPL_SPI_FLASH_SUPPORT=y
 CONFIG_SPL_SPI=y
 CONFIG_ARMV7_LPAE=y
@@ -39,6 +38,9 @@ CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot.img"
 CONFIG_SPL_DM_SPI_FLASH=y
 CONFIG_SPL_SPI_LOAD=y
 CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000
+CONFIG_SYS_SPI_KERNEL_OFFS=0x1E0000
+CONFIG_SYS_SPI_ARGS_OFFS=0x140000
+CONFIG_SYS_SPI_ARGS_SIZE=0x80000
 CONFIG_SPL_YMODEM_SUPPORT=y
 CONFIG_CMD_ADTIMG=y
 CONFIG_CMD_ABOOTIMG=y
@@ -50,8 +52,7 @@ CONFIG_CMD_AVB=y
 CONFIG_OF_CONTROL=y
 CONFIG_SPL_OF_CONTROL=y
 CONFIG_OF_LIST="am57xx-beagle-x15 am57xx-beagle-x15-revb1 am57xx-beagle-x15-revc am5729-beagleboneai am572x-idk am571x-idk am574x-idk"
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_MMC=y
+# CONFIG_ENV_IS_IN_FAT is not set
 CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_SYS_MMC_ENV_DEV=1
diff --git a/configs/am57xx_hs_evm_usb_defconfig b/configs/am57xx_hs_evm_usb_defconfig
index d865b123b90..634294e4766 100644
--- a/configs/am57xx_hs_evm_usb_defconfig
+++ b/configs/am57xx_hs_evm_usb_defconfig
@@ -41,6 +41,9 @@ CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot.img"
 CONFIG_SPL_DM_SPI_FLASH=y
 CONFIG_SPL_SPI_LOAD=y
 CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000
+CONFIG_SYS_SPI_KERNEL_OFFS=0x1E0000
+CONFIG_SYS_SPI_ARGS_OFFS=0x140000
+CONFIG_SYS_SPI_ARGS_SIZE=0x80000
 CONFIG_SPL_YMODEM_SUPPORT=y
 CONFIG_CMD_ADTIMG=y
 CONFIG_CMD_ABOOTIMG=y
diff --git a/configs/am62ax_evm_a53_defconfig b/configs/am62ax_evm_a53_defconfig
index bf6e9639901..d77ff2d7221 100644
--- a/configs/am62ax_evm_a53_defconfig
+++ b/configs/am62ax_evm_a53_defconfig
@@ -41,7 +41,6 @@ CONFIG_SPL_POWER_DOMAIN=y
 CONFIG_SPL_YMODEM_SUPPORT=y
 CONFIG_CMD_MMC=y
 CONFIG_MMC_SPEED_MODE_SET=y
-CONFIG_CMD_REMOTEPROC=y
 CONFIG_OF_CONTROL=y
 CONFIG_SPL_OF_CONTROL=y
 CONFIG_OF_UPSTREAM=y
@@ -95,9 +94,6 @@ CONFIG_SPL_DM_REGULATOR_FIXED=y
 CONFIG_DM_REGULATOR_GPIO=y
 CONFIG_SPL_DM_REGULATOR_GPIO=y
 CONFIG_K3_SYSTEM_CONTROLLER=y
-CONFIG_REMOTEPROC_TI_K3_ARM64=y
-CONFIG_REMOTEPROC_TI_K3_DSP=y
-CONFIG_REMOTEPROC_TI_K3_R5F=y
 CONFIG_RESET_TI_SCI=y
 CONFIG_DM_SERIAL=y
 CONFIG_SOC_DEVICE=y
@@ -107,3 +103,5 @@ CONFIG_SYSRESET=y
 CONFIG_SPL_SYSRESET=y
 CONFIG_SYSRESET_TI_SCI=y
 CONFIG_FS_FAT_MAX_CLUSTSIZE=16384
+
+#include <configs/am62x_a53_usbdfu.config>
diff --git a/configs/am62ax_evm_r5_defconfig b/configs/am62ax_evm_r5_defconfig
index 3953430c014..cbdc219e25e 100644
--- a/configs/am62ax_evm_r5_defconfig
+++ b/configs/am62ax_evm_r5_defconfig
@@ -48,7 +48,6 @@ CONFIG_SPL_DM_SPI_FLASH=y
 CONFIG_SPL_DM_RESET=y
 CONFIG_SPL_POWER_DOMAIN=y
 CONFIG_SPL_RAM_DEVICE=y
-CONFIG_SPL_REMOTEPROC=y
 CONFIG_SPL_THERMAL=y
 CONFIG_SPL_YMODEM_SUPPORT=y
 CONFIG_HUSH_PARSER=y
@@ -56,7 +55,6 @@ CONFIG_CMD_ASKENV=y
 CONFIG_CMD_DFU=y
 CONFIG_CMD_GPT=y
 CONFIG_CMD_MMC=y
-CONFIG_CMD_REMOTEPROC=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_TIME=y
 CONFIG_CMD_FAT=y
@@ -97,7 +95,6 @@ CONFIG_PINCTRL_SINGLE=y
 CONFIG_POWER_DOMAIN=y
 CONFIG_TI_POWER_DOMAIN=y
 CONFIG_K3_SYSTEM_CONTROLLER=y
-CONFIG_REMOTEPROC_TI_K3_ARM64=y
 CONFIG_RESET_TI_SCI=y
 CONFIG_SPECIFY_CONSOLE_INDEX=y
 CONFIG_DM_SERIAL=y
diff --git a/configs/am62px_evm_a53_defconfig b/configs/am62px_evm_a53_defconfig
index 30b4a24ee9a..4b5d1ec1613 100644
--- a/configs/am62px_evm_a53_defconfig
+++ b/configs/am62px_evm_a53_defconfig
@@ -40,14 +40,11 @@ CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1400
 CONFIG_SPL_DMA=y
-CONFIG_SPL_ENV_SUPPORT=y
 CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot.img"
 CONFIG_SPL_I2C=y
 CONFIG_SPL_DM_MAILBOX=y
 CONFIG_SPL_DM_SPI_FLASH=y
 CONFIG_SPL_POWER_DOMAIN=y
-CONFIG_SPL_RAM_SUPPORT=y
-CONFIG_SPL_RAM_DEVICE=y
 # CONFIG_SPL_SPI_FLASH_TINY is not set
 CONFIG_SPL_SPI_FLASH_SFDP_SUPPORT=y
 CONFIG_SPL_SPI_LOAD=y
@@ -57,7 +54,6 @@ CONFIG_SPL_YMODEM_SUPPORT=y
 CONFIG_CMD_BOOTEFI_SELFTEST=y
 CONFIG_CMD_NVEDIT_EFI=y
 CONFIG_CMD_CLK=y
-CONFIG_CMD_DFU=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_GPT=y
 CONFIG_CMD_I2C=y
@@ -84,17 +80,12 @@ CONFIG_SPL_DM_DEVICE_REMOVE=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_REGMAP=y
 CONFIG_SPL_REGMAP=y
-CONFIG_SPL_SYSCON=y
 CONFIG_SPL_OF_TRANSLATE=y
 CONFIG_CLK=y
 CONFIG_SPL_CLK=y
 CONFIG_CLK_TI_SCI=y
-CONFIG_DFU_MMC=y
 CONFIG_DFU_MTD=y
-CONFIG_DFU_RAM=y
 CONFIG_DFU_SF=y
-CONFIG_SYS_DFU_DATA_BUF_SIZE=0x40000
-CONFIG_SYS_DFU_MAX_FILE_SIZE=0x800000
 CONFIG_DMA_CHANNELS=y
 CONFIG_TI_K3_NAVSS_UDMA=y
 CONFIG_USB_FUNCTION_FASTBOOT=y
@@ -146,9 +137,6 @@ CONFIG_SPL_DM_REGULATOR_FIXED=y
 CONFIG_DM_REGULATOR_GPIO=y
 CONFIG_SPL_DM_REGULATOR_GPIO=y
 CONFIG_K3_SYSTEM_CONTROLLER=y
-CONFIG_REMOTEPROC_TI_K3_ARM64=y
-CONFIG_REMOTEPROC_TI_K3_DSP=y
-CONFIG_REMOTEPROC_TI_K3_R5F=y
 CONFIG_RESET_TI_SCI=y
 CONFIG_DM_RTC=y
 CONFIG_RTC_EMULATION=y
@@ -163,22 +151,10 @@ CONFIG_SYSRESET=y
 CONFIG_SPL_SYSRESET=y
 CONFIG_SYSRESET_TI_SCI=y
 CONFIG_DM_THERMAL=y
-CONFIG_USB=y
-CONFIG_DM_USB_GADGET=y
-CONFIG_SPL_DM_USB_GADGET=y
 CONFIG_SPL_USB_HOST=y
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_DWC3=y
-CONFIG_USB_DWC3_GENERIC=y
-CONFIG_SPL_USB_DWC3_GENERIC=y
 CONFIG_SPL_USB_STORAGE=y
-CONFIG_USB_GADGET=y
-CONFIG_SPL_USB_GADGET=y
-CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
-CONFIG_USB_GADGET_VENDOR_NUM=0x0451
-CONFIG_USB_GADGET_PRODUCT_NUM=0x6165
-CONFIG_SPL_DFU=y
 CONFIG_FS_FAT_MAX_CLUSTSIZE=16384
 CONFIG_EFI_SET_TIME=y
 
 #include <configs/k3_efi_capsule.config>
+#include <configs/am62x_a53_usbdfu.config>
diff --git a/configs/am62px_evm_r5_defconfig b/configs/am62px_evm_r5_defconfig
index f39356351f4..39b6a83ab42 100644
--- a/configs/am62px_evm_r5_defconfig
+++ b/configs/am62px_evm_r5_defconfig
@@ -49,7 +49,6 @@ CONFIG_SPL_DM_SPI_FLASH=y
 CONFIG_SPL_DM_RESET=y
 CONFIG_SPL_POWER_DOMAIN=y
 CONFIG_SPL_RAM_DEVICE=y
-CONFIG_SPL_REMOTEPROC=y
 # CONFIG_SPL_SPI_FLASH_TINY is not set
 CONFIG_SPL_SPI_FLASH_SFDP_SUPPORT=y
 CONFIG_SPL_SPI_LOAD=y
@@ -61,7 +60,6 @@ CONFIG_CMD_ASKENV=y
 CONFIG_CMD_DFU=y
 CONFIG_CMD_GPT=y
 CONFIG_CMD_MMC=y
-CONFIG_CMD_REMOTEPROC=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_TIME=y
 CONFIG_CMD_FAT=y
@@ -111,7 +109,6 @@ CONFIG_PINCTRL_SINGLE=y
 CONFIG_POWER_DOMAIN=y
 CONFIG_TI_POWER_DOMAIN=y
 CONFIG_K3_SYSTEM_CONTROLLER=y
-CONFIG_REMOTEPROC_TI_K3_ARM64=y
 CONFIG_RESET_TI_SCI=y
 CONFIG_SPECIFY_CONSOLE_INDEX=y
 CONFIG_DM_SERIAL=y
diff --git a/configs/am62x_a53_usbdfu.config b/configs/am62x_a53_usbdfu.config
index 812f99ee70b..16cd4c89f41 100644
--- a/configs/am62x_a53_usbdfu.config
+++ b/configs/am62x_a53_usbdfu.config
@@ -6,6 +6,7 @@ CONFIG_SPL_USB_GADGET=y
 CONFIG_SPL_DFU=y
 CONFIG_CMD_DFU=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
 CONFIG_SYSCON=y
 CONFIG_SPL_SYSCON=y
 CONFIG_DFU_MMC=y
diff --git a/configs/am62x_a53_usbmsc.config b/configs/am62x_a53_usbmsc.config
new file mode 100644
index 00000000000..873a559986b
--- /dev/null
+++ b/configs/am62x_a53_usbmsc.config
@@ -0,0 +1,20 @@
+CONFIG_USB=y
+CONFIG_USB_HOST=y
+CONFIG_SPL_USB_HOST=y
+CONFIG_SYSCON=y
+CONFIG_SPL_SYSCON=y
+CONFIG_MISC=y
+CONFIG_SPL_MISC=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_GADGET=y
+CONFIG_SPL_USB_GADGET=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GENERIC=y
+CONFIG_SPL_USB_DWC3_GENERIC=y
+CONFIG_USB_DWC3_AM62=y
+CONFIG_SPL_USB_DWC3_AM62=y
+CONFIG_USB_STORAGE=y
+CONFIG_SPL_USB_STORAGE=y
+# CONFIG_DM_USB_GADGET is not set
+# CONFIG_SPL_DM_USB_GADGET is not set
+# CONFIG_USB_GADGET_DOWNLOAD is not set
diff --git a/configs/am62x_beagleplay_a53_defconfig b/configs/am62x_beagleplay_a53_defconfig
index a8a73166597..cedd0f75378 100644
--- a/configs/am62x_beagleplay_a53_defconfig
+++ b/configs/am62x_beagleplay_a53_defconfig
@@ -110,7 +110,6 @@ CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_DM_REGULATOR_GPIO=y
 CONFIG_DM_REGULATOR_TPS65219=y
 CONFIG_K3_SYSTEM_CONTROLLER=y
-CONFIG_REMOTEPROC_TI_K3_ARM64=y
 CONFIG_RESET_TI_SCI=y
 CONFIG_DM_RTC=y
 CONFIG_RTC_EMULATION=y
diff --git a/configs/am62x_beagleplay_r5_defconfig b/configs/am62x_beagleplay_r5_defconfig
index bbc55417a7e..5a465bff158 100644
--- a/configs/am62x_beagleplay_r5_defconfig
+++ b/configs/am62x_beagleplay_r5_defconfig
@@ -50,14 +50,12 @@ CONFIG_SPL_DM_MAILBOX=y
 CONFIG_SPL_DM_RESET=y
 CONFIG_SPL_POWER_DOMAIN=y
 CONFIG_SPL_RAM_DEVICE=y
-CONFIG_SPL_REMOTEPROC=y
 CONFIG_SPL_YMODEM_SUPPORT=y
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_ASKENV=y
 CONFIG_CMD_DFU=y
 CONFIG_CMD_GPT=y
 CONFIG_CMD_MMC=y
-CONFIG_CMD_REMOTEPROC=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_TIME=y
 CONFIG_CMD_FAT=y
@@ -95,7 +93,6 @@ CONFIG_PINCTRL_SINGLE=y
 CONFIG_POWER_DOMAIN=y
 CONFIG_TI_POWER_DOMAIN=y
 CONFIG_K3_SYSTEM_CONTROLLER=y
-CONFIG_REMOTEPROC_TI_K3_ARM64=y
 CONFIG_RESET_TI_SCI=y
 CONFIG_SPECIFY_CONSOLE_INDEX=y
 CONFIG_DM_SERIAL=y
diff --git a/configs/am62x_evm_a53_defconfig b/configs/am62x_evm_a53_defconfig
index 6527200259e..d9596cb7224 100644
--- a/configs/am62x_evm_a53_defconfig
+++ b/configs/am62x_evm_a53_defconfig
@@ -119,7 +119,6 @@ CONFIG_SPL_DM_REGULATOR_FIXED=y
 CONFIG_DM_REGULATOR_GPIO=y
 CONFIG_SPL_DM_REGULATOR_GPIO=y
 CONFIG_K3_SYSTEM_CONTROLLER=y
-CONFIG_REMOTEPROC_TI_K3_ARM64=y
 CONFIG_RESET_TI_SCI=y
 CONFIG_DM_RTC=y
 CONFIG_RTC_EMULATION=y
diff --git a/configs/am62x_evm_r5_defconfig b/configs/am62x_evm_r5_defconfig
index b47f2f2d1f3..8eb59400eb2 100644
--- a/configs/am62x_evm_r5_defconfig
+++ b/configs/am62x_evm_r5_defconfig
@@ -53,7 +53,6 @@ CONFIG_SPL_DM_SPI_FLASH=y
 CONFIG_SPL_DM_RESET=y
 CONFIG_SPL_POWER_DOMAIN=y
 CONFIG_SPL_RAM_DEVICE=y
-CONFIG_SPL_REMOTEPROC=y
 # CONFIG_SPL_SPI_FLASH_TINY is not set
 CONFIG_SPL_SPI_FLASH_SFDP_SUPPORT=y
 CONFIG_SPL_SPI_LOAD=y
@@ -64,7 +63,6 @@ CONFIG_CMD_ASKENV=y
 CONFIG_CMD_DFU=y
 CONFIG_CMD_GPT=y
 CONFIG_CMD_MMC=y
-CONFIG_CMD_REMOTEPROC=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_TIME=y
 CONFIG_CMD_FAT=y
@@ -110,7 +108,6 @@ CONFIG_PINCTRL_SINGLE=y
 CONFIG_POWER_DOMAIN=y
 CONFIG_TI_POWER_DOMAIN=y
 CONFIG_K3_SYSTEM_CONTROLLER=y
-CONFIG_REMOTEPROC_TI_K3_ARM64=y
 CONFIG_RESET_TI_SCI=y
 CONFIG_SPECIFY_CONSOLE_INDEX=y
 CONFIG_DM_SERIAL=y
diff --git a/configs/am62x_r5_usbdfu.config b/configs/am62x_r5_usbdfu.config
index 62c9247c582..5bbb99ec30d 100644
--- a/configs/am62x_r5_usbdfu.config
+++ b/configs/am62x_r5_usbdfu.config
@@ -25,3 +25,6 @@ CONFIG_SPL_DFU=y
 # CONFIG_CMD_GPT is not set
 # CONFIG_CMD_FAT is not set
 # CONFIG_MMC is not set
+# CONFIG_SPL_MTD is not set
+# CONFIG_DMA_CHANNELS is not set
+# CONFIG_TI_K3_NAVSS_UDMA is not set
diff --git a/configs/am62x_r5_usbmsc.config b/configs/am62x_r5_usbmsc.config
new file mode 100644
index 00000000000..09f94511d28
--- /dev/null
+++ b/configs/am62x_r5_usbmsc.config
@@ -0,0 +1,24 @@
+CONFIG_USB=y
+CONFIG_SPL_USB_HOST=y
+CONFIG_SPL_SYSCON=y
+CONFIG_SPL_MISC=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_GADGET=y
+CONFIG_SPL_USB_GADGET=y
+CONFIG_USB_DWC3=y
+CONFIG_SPL_USB_DWC3_GENERIC=y
+CONFIG_SPL_USB_DWC3_AM62=y
+CONFIG_USB_STORAGE=y
+CONFIG_SPL_USB_STORAGE=y
+# CONFIG_CMD_DFU is not set
+# CONFIG_CMD_FAT is not set
+# CONFIG_CMD_GPT is not set
+# CONFIG_CMD_MMC is not set
+# CONFIG_DFU is not set
+# CONFIG_SPL_LIBDISK_SUPPORT is not set
+# CONFIG_SPL_MMC is not set
+# CONFIG_SPL_MTD is not set
+# CONFIG_SPL_RAM_DEVICE is not set
+# CONFIG_SPL_SPI is not set
+# CONFIG_SPL_SYS_MALLOC is not set
+# CONFIG_MMC_SDHCI is not set
diff --git a/configs/am64x_evm_a53_defconfig b/configs/am64x_evm_a53_defconfig
index a501f3f567e..c2ad1242d20 100644
--- a/configs/am64x_evm_a53_defconfig
+++ b/configs/am64x_evm_a53_defconfig
@@ -71,6 +71,7 @@ CONFIG_CMD_GPT=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
 CONFIG_CMD_EFIDEBUG=y
 CONFIG_CMD_TIME=y
 CONFIG_CMD_PMIC=y
@@ -148,9 +149,6 @@ CONFIG_PMIC_TPS65219=y
 CONFIG_DM_REGULATOR=y
 CONFIG_DM_REGULATOR_TPS65219=y
 CONFIG_K3_SYSTEM_CONTROLLER=y
-CONFIG_REMOTEPROC_TI_K3_ARM64=y
-CONFIG_REMOTEPROC_TI_PRU=y
-CONFIG_CMD_REMOTEPROC=y
 CONFIG_RESET_TI_SCI=y
 CONFIG_DM_RTC=y
 CONFIG_RTC_EMULATION=y
diff --git a/configs/am64x_evm_r5_defconfig b/configs/am64x_evm_r5_defconfig
index 0ceac16dd20..b222bcd6e43 100644
--- a/configs/am64x_evm_r5_defconfig
+++ b/configs/am64x_evm_r5_defconfig
@@ -59,7 +59,6 @@ CONFIG_SPL_NET_VCI_STRING="AM64X U-Boot R5 SPL"
 CONFIG_SPL_DM_RESET=y
 CONFIG_SPL_POWER_DOMAIN=y
 CONFIG_SPL_RAM_DEVICE=y
-CONFIG_SPL_REMOTEPROC=y
 # CONFIG_SPL_SPI_FLASH_TINY is not set
 CONFIG_SPL_SPI_FLASH_SFDP_SUPPORT=y
 CONFIG_SPL_SPI_LOAD=y
@@ -71,7 +70,6 @@ CONFIG_CMD_ASKENV=y
 CONFIG_CMD_DFU=y
 CONFIG_CMD_GPT=y
 CONFIG_CMD_MMC=y
-CONFIG_CMD_REMOTEPROC=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_USB_MASS_STORAGE=y
 # CONFIG_CMD_SETEXPR is not set
@@ -138,7 +136,6 @@ CONFIG_SPL_DM_REGULATOR=y
 CONFIG_DM_REGULATOR_GPIO=y
 CONFIG_SPL_DM_REGULATOR_GPIO=y
 CONFIG_K3_SYSTEM_CONTROLLER=y
-CONFIG_REMOTEPROC_TI_K3_ARM64=y
 CONFIG_RESET_TI_SCI=y
 CONFIG_SPECIFY_CONSOLE_INDEX=y
 CONFIG_DM_SERIAL=y
diff --git a/configs/am65x_evm_a53_defconfig b/configs/am65x_evm_a53_defconfig
index e9b736714a5..12c4cb96815 100644
--- a/configs/am65x_evm_a53_defconfig
+++ b/configs/am65x_evm_a53_defconfig
@@ -66,7 +66,6 @@ CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
 CONFIG_MMC_SPEED_MODE_SET=y
 CONFIG_CMD_PCI=y
-CONFIG_CMD_REMOTEPROC=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_TIME=y
 CONFIG_MTDIDS_DEFAULT="nor0=47040000.spi.0"
@@ -144,8 +143,6 @@ CONFIG_TI_SCI_POWER_DOMAIN=y
 CONFIG_DM_REGULATOR=y
 CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_DM_REGULATOR_GPIO=y
-CONFIG_REMOTEPROC_TI_K3_R5F=y
-CONFIG_REMOTEPROC_TI_PRU=y
 CONFIG_RESET_TI_SCI=y
 CONFIG_DM_SERIAL=y
 CONFIG_SOC_DEVICE=y
diff --git a/configs/am65x_evm_r5_defconfig b/configs/am65x_evm_r5_defconfig
index 289c41c3eb5..386749ebabd 100644
--- a/configs/am65x_evm_r5_defconfig
+++ b/configs/am65x_evm_r5_defconfig
@@ -53,7 +53,6 @@ CONFIG_SPL_DM_SPI_FLASH=y
 CONFIG_SPL_DM_RESET=y
 CONFIG_SPL_POWER_DOMAIN=y
 CONFIG_SPL_RAM_DEVICE=y
-CONFIG_SPL_REMOTEPROC=y
 # CONFIG_SPL_SPI_FLASH_TINY is not set
 CONFIG_SPL_SPI_FLASH_SFDP_SUPPORT=y
 CONFIG_SPL_SPI_LOAD=y
@@ -65,7 +64,6 @@ CONFIG_CMD_ASKENV=y
 CONFIG_CMD_GPT=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
-CONFIG_CMD_REMOTEPROC=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_TIME=y
 CONFIG_CMD_FAT=y
@@ -123,7 +121,6 @@ CONFIG_DM_REGULATOR_TPS62360=y
 CONFIG_RAM=y
 CONFIG_SPL_RAM=y
 CONFIG_K3_SYSTEM_CONTROLLER=y
-CONFIG_REMOTEPROC_TI_K3_ARM64=y
 CONFIG_RESET_TI_SCI=y
 CONFIG_DM_SERIAL=y
 CONFIG_SOC_DEVICE=y
diff --git a/configs/am65x_evm_r5_usbdfu_defconfig b/configs/am65x_evm_r5_usbdfu_defconfig
index 0b5eaeb363d..b0d333d95c2 100644
--- a/configs/am65x_evm_r5_usbdfu_defconfig
+++ b/configs/am65x_evm_r5_usbdfu_defconfig
@@ -1,7 +1,9 @@
+#include<configs/am65x_evm_r5_defconfig>
+
 CONFIG_ARM=y
 CONFIG_ARCH_K3=y
 CONFIG_SYS_MALLOC_LEN=0x2000000
-CONFIG_SYS_MALLOC_F_LEN=0x55000
+CONFIG_SYS_MALLOC_F_LEN=0x57000
 CONFIG_SPL_GPIO=y
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
@@ -13,106 +15,17 @@ CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x41c7effc
 CONFIG_ENV_SIZE=0x20000
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="k3-am654-r5-base-board"
-CONFIG_DM_RESET=y
-CONFIG_SPL_SERIAL=y
-CONFIG_SPL_DRIVERS_MISC=y
-CONFIG_SPL_STACK_R_ADDR=0x82000000
-CONFIG_SPL_TEXT_BASE=0x41c00000
-CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
-CONFIG_SPL_BSS_START_ADDR=0x41c7effc
-CONFIG_SPL_BSS_MAX_SIZE=0xc00
-CONFIG_SPL_STACK_R=y
-CONFIG_SPL_SIZE_LIMIT=0x7ec00
-CONFIG_SPL_SIZE_LIMIT_PROVIDE_STACK=0x2000
-CONFIG_SPL_LIBDISK_SUPPORT=y
-# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_SPL_LOAD_FIT=y
 CONFIG_SPL_LOAD_FIT_ADDRESS=0x80080000
-CONFIG_USE_BOOTCOMMAND=y
-# CONFIG_DISPLAY_CPUINFO is not set
-CONFIG_SPL_SIZE_LIMIT_SUBTRACT_GD=y
-CONFIG_SPL_SIZE_LIMIT_SUBTRACT_MALLOC=y
-CONFIG_SPL_MAX_SIZE=0x58000
-CONFIG_SPL_SYS_REPORT_STACK_F_USAGE=y
-CONFIG_SPL_SEPARATE_BSS=y
-CONFIG_SPL_SYS_MALLOC=y
-CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
-CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x84000000
-CONFIG_SPL_SYS_MALLOC_SIZE=0x1000000
-CONFIG_SPL_EARLY_BSS=y
-CONFIG_SPL_DMA=y
 CONFIG_SPL_ENV_SUPPORT=y
-CONFIG_SPL_I2C=y
-CONFIG_SPL_DM_MAILBOX=y
-CONFIG_SPL_DM_RESET=y
-CONFIG_SPL_POWER_DOMAIN=y
-CONFIG_SPL_RAM_DEVICE=y
-CONFIG_SPL_REMOTEPROC=y
-CONFIG_SPL_YMODEM_SUPPORT=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
-CONFIG_CMD_ASKENV=y
 CONFIG_CMD_DFU=y
-CONFIG_CMD_GPT=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_REMOTEPROC=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_TIME=y
-CONFIG_CMD_FAT=y
-CONFIG_OF_CONTROL=y
-CONFIG_SPL_OF_CONTROL=y
-CONFIG_SPL_MULTI_DTB_FIT=y
-CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_SPL_DM=y
-CONFIG_SPL_DM_SEQ_ALIAS=y
-CONFIG_REGMAP=y
-CONFIG_SPL_REGMAP=y
 CONFIG_SYSCON=y
 CONFIG_SPL_SYSCON=y
-CONFIG_SPL_OF_TRANSLATE=y
-CONFIG_CLK=y
-CONFIG_SPL_CLK=y
-CONFIG_CLK_TI_SCI=y
 CONFIG_SYS_DFU_DATA_BUF_SIZE=0x5000
 CONFIG_SYS_DFU_MAX_FILE_SIZE=0x800000
-CONFIG_TI_SCI_PROTOCOL=y
-CONFIG_DA8XX_GPIO=y
-CONFIG_DM_I2C=y
-CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
-CONFIG_SYS_I2C_OMAP24XX=y
-CONFIG_DM_MAILBOX=y
-CONFIG_K3_SEC_PROXY=y
 CONFIG_MISC=y
-CONFIG_K3_AVS0=y
-# CONFIG_MMC is not set
 CONFIG_PHY=y
 CONFIG_SPL_PHY=y
 CONFIG_OMAP_USB2_PHY=y
-CONFIG_PINCTRL=y
-# CONFIG_PINCTRL_GENERIC is not set
-CONFIG_SPL_PINCTRL=y
-# CONFIG_SPL_PINCTRL_GENERIC is not set
-CONFIG_PINCTRL_SINGLE=y
-CONFIG_POWER_DOMAIN=y
-CONFIG_TI_SCI_POWER_DOMAIN=y
-CONFIG_DM_REGULATOR=y
-CONFIG_SPL_DM_REGULATOR=y
-CONFIG_DM_REGULATOR_GPIO=y
-CONFIG_SPL_DM_REGULATOR_GPIO=y
-CONFIG_DM_REGULATOR_TPS62360=y
-CONFIG_RAM=y
-CONFIG_SPL_RAM=y
-CONFIG_K3_SYSTEM_CONTROLLER=y
-CONFIG_REMOTEPROC_TI_K3_ARM64=y
-CONFIG_RESET_TI_SCI=y
-CONFIG_DM_SERIAL=y
-CONFIG_SYSRESET=y
-CONFIG_SPL_SYSRESET=y
-CONFIG_SYSRESET_TI_SCI=y
-CONFIG_TIMER=y
-CONFIG_SPL_TIMER=y
-CONFIG_OMAP_TIMER=y
 CONFIG_USB=y
 CONFIG_DM_USB_GADGET=y
 CONFIG_SPL_DM_USB_GADGET=y
@@ -129,4 +42,34 @@ CONFIG_USB_GADGET_VENDOR_NUM=0x0451
 CONFIG_USB_GADGET_PRODUCT_NUM=0x6162
 CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_SPL_DFU=y
-CONFIG_FS_FAT_MAX_CLUSTSIZE=16384
+CONFIG_MMC=n
+CONFIG_SPL_DM_SPI=n
+CONFIG_SPL_MMC=n
+CONFIG_SPL_FS_FAT=n
+CONFIG_SPL_SPI_FLASH_SUPPORT=n
+CONFIG_SPL_SPI=n
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=n
+CONFIG_SPL_DM_SPI_FLASH=n
+CONFIG_SPL_SPI_FLASH_SFDP_SUPPORT=n
+CONFIG_SPL_SPI_LOAD=n
+CONFIG_CMD_MMC=n
+CONFIG_ENV_OVERWRITE=n
+CONFIG_ENV_IS_IN_FAT=n
+CONFIG_DMA_CHANNELS=n
+CONFIG_TI_K3_NAVSS_UDMA=n
+CONFIG_SUPPORT_EMMC_BOOT=n
+CONFIG_MMC_HS200_SUPPORT=n
+CONFIG_SPL_MMC_HS200_SUPPORT=n
+CONFIG_MMC_SDHCI=n
+CONFIG_SPL_MMC_SDHCI_ADMA=n
+CONFIG_MMC_SDHCI_AM654=n
+CONFIG_MTD=n
+CONFIG_DM_SPI_FLASH=n
+CONFIG_SPI_FLASH_SFDP_SUPPORT=n
+CONFIG_SPI_FLASH_STMICRO=n
+CONFIG_SOC_DEVICE=n
+CONFIG_SOC_DEVICE_TI_K3=n
+CONFIG_SOC_TI=n
+CONFIG_SPI=n
+CONFIG_DM_SPI=n
+CONFIG_CADENCE_QSPI=n
diff --git a/configs/am65x_evm_r5_usbmsc_defconfig b/configs/am65x_evm_r5_usbmsc_defconfig
index ef2ff411172..90a857b8b95 100644
--- a/configs/am65x_evm_r5_usbmsc_defconfig
+++ b/configs/am65x_evm_r5_usbmsc_defconfig
@@ -47,14 +47,12 @@ CONFIG_SPL_DM_MAILBOX=y
 CONFIG_SPL_DM_RESET=y
 CONFIG_SPL_POWER_DOMAIN=y
 CONFIG_SPL_RAM_DEVICE=y
-CONFIG_SPL_REMOTEPROC=y
 CONFIG_SPL_YMODEM_SUPPORT=y
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 CONFIG_CMD_ASKENV=y
 CONFIG_CMD_GPT=y
 CONFIG_CMD_I2C=y
-CONFIG_CMD_REMOTEPROC=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_TIME=y
 CONFIG_CMD_FAT=y
@@ -101,7 +99,6 @@ CONFIG_DM_REGULATOR_TPS62360=y
 CONFIG_RAM=y
 CONFIG_SPL_RAM=y
 CONFIG_K3_SYSTEM_CONTROLLER=y
-CONFIG_REMOTEPROC_TI_K3_ARM64=y
 CONFIG_RESET_TI_SCI=y
 CONFIG_DM_SERIAL=y
 CONFIG_SYSRESET=y
diff --git a/configs/am67a_beagley_ai_a53_defconfig b/configs/am67a_beagley_ai_a53_defconfig
new file mode 100644
index 00000000000..b0903b6ae8f
--- /dev/null
+++ b/configs/am67a_beagley_ai_a53_defconfig
@@ -0,0 +1,37 @@
+#include <configs/j722s_evm_a53_defconfig>
+
+CONFIG_ARM=y
+CONFIG_ARCH_K3=y
+CONFIG_SOC_K3_J722S=y
+CONFIG_TARGET_J722S_A53_BEAGLEY_AI=y
+
+CONFIG_DEFAULT_DEVICE_TREE="ti/k3-am67a-beagley-ai"
+CONFIG_SPL_OF_LIST="ti/k3-am67a-beagley-ai"
+CONFIG_OF_LIST="ti/k3-am67a-beagley-ai"
+
+CONFIG_BOOTCOMMAND="run findfdt; run envboot; run distro_bootcmd"
+CONFIG_EXT4_WRITE=y
+CONFIG_LZO=y
+CONFIG_AUTOBOOT_KEYED=y
+CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n"
+CONFIG_AUTOBOOT_DELAY_STR="d"
+CONFIG_AUTOBOOT_STOP_STR=" "
+CONFIG_TI_I2C_BOARD_DETECT=n
+CONFIG_SPL_SPI=n
+CONFIG_SPL_SPI_FLASH_SUPPORT=n
+CONFIG_SPL_DM_SPI_FLASH=n
+CONFIG_SPL_MTD_SUPPORT=n
+CONFIG_SPL_MTD_SUPPORT=n
+CONFIG_DM_SPI_FLASH=n
+CONFIG_SPI_FLASH=n
+CONFIG_MTD=n
+CONFIG_MTD_PARTITIONS=n
+CONFIG_DM_MTD=n
+CONFIG_MTD_UBI=n
+CONFIG_CMD_UBIFS=n
+CONFIG_CMD_UBI=n
+CONFIG_DFU_SF=n
+CONFIG_DM_SPI=n
+CONFIG_SPL_SPI_LOAD=n
+CONFIG_SPL_MTD=n
+CONFIG_CMD_SPI=n
diff --git a/configs/am67a_beagley_ai_r5_defconfig b/configs/am67a_beagley_ai_r5_defconfig
new file mode 100644
index 00000000000..5380747fe3c
--- /dev/null
+++ b/configs/am67a_beagley_ai_r5_defconfig
@@ -0,0 +1,14 @@
+#include <configs/j722s_evm_r5_defconfig>
+
+CONFIG_ARM=y
+CONFIG_ARCH_K3=y
+CONFIG_SOC_K3_J722S=y
+CONFIG_TARGET_J722S_R5_BEAGLEY_AI=y
+
+CONFIG_DEFAULT_DEVICE_TREE="k3-am67a-r5-beagley-ai"
+CONFIG_SPL_OF_LIST="k3-am67a-r5-beagley-ai"
+CONFIG_OF_LIST="k3-am67a-r5-beagley-ai"
+
+CONFIG_TI_I2C_BOARD_DETECT=n
+CONFIG_SPL_DM_SPI_FLASH=n
+CONFIG_SPL_MTD_SUPPORT=n
diff --git a/configs/am68_sk_r5_defconfig b/configs/am68_sk_r5_defconfig
index 097bed62061..d6ef89c7b84 100644
--- a/configs/am68_sk_r5_defconfig
+++ b/configs/am68_sk_r5_defconfig
@@ -6,7 +6,6 @@ CONFIG_SOC_K3_J721S2=y
 CONFIG_TARGET_J721S2_R5_EVM=y
 
 CONFIG_ESM_K3=n
-CONFIG_K3_AVS0=n
 CONFIG_ESM_PMIC=n
 CONFIG_DM_REGULATOR_TPS65941=n
 CONFIG_PMIC_TPS65941=n
diff --git a/configs/am69_sk_a72_defconfig b/configs/am69_sk_a72_defconfig
index 452de887258..bd8aaf7f201 100644
--- a/configs/am69_sk_a72_defconfig
+++ b/configs/am69_sk_a72_defconfig
@@ -5,5 +5,10 @@ CONFIG_ARCH_K3=y
 CONFIG_SOC_K3_J784S4=y
 CONFIG_TARGET_J784S4_A72_EVM=y
 
+CONFIG_CMD_UFS=n
+CONFIG_UFS=n
+CONFIG_CADENCE_UFS=n
+CONFIG_TI_J721E_UFS=n
+
 CONFIG_DEFAULT_DEVICE_TREE="ti/k3-am69-sk"
 CONFIG_OF_LIST="ti/k3-am69-sk"
diff --git a/configs/an7581_evb_defconfig b/configs/an7581_evb_defconfig
new file mode 100644
index 00000000000..f09b5b603a2
--- /dev/null
+++ b/configs/an7581_evb_defconfig
@@ -0,0 +1,78 @@
+CONFIG_ARM=y
+CONFIG_ARCH_AIROHA=y
+CONFIG_TEXT_BASE=0x81E00000
+CONFIG_SYS_MALLOC_F_LEN=0x4000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_ENV_SIZE=0x4000
+CONFIG_ENV_OFFSET=0x7c000
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="airoha/en7581-evb"
+CONFIG_DM_RESET=y
+CONFIG_SYS_LOAD_ADDR=0x81800000
+CONFIG_BUILD_TARGET="u-boot.bin"
+# CONFIG_EFI_LOADER is not set
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_BOOTDELAY=3
+CONFIG_DEFAULT_FDT_FILE="en7581-evb"
+CONFIG_SYS_PBSIZE=1049
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_HUSH_PARSER=y
+CONFIG_SYS_PROMPT="U-Boot> "
+CONFIG_SYS_MAXARGS=8
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_BOOTMENU=y
+# CONFIG_CMD_ELF is not set
+# CONFIG_CMD_XIMG is not set
+CONFIG_CMD_BIND=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_MTD=y
+CONFIG_CMD_SF_TEST=y
+CONFIG_CMD_SPI=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_PING=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_CMD_MTDPARTS=y
+CONFIG_CMD_LOG=y
+CONFIG_OF_UPSTREAM=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_CLK=y
+CONFIG_DMA=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
+CONFIG_MMC_HS200_SUPPORT=y
+CONFIG_MTD=y
+CONFIG_DM_MTD=y
+CONFIG_MTD_SPI_NAND=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH_EON=y
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_ISSI=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_SPI_FLASH_MTD=y
+CONFIG_PHYLIB=y
+CONFIG_PHY=y
+CONFIG_PINCTRL=y
+CONFIG_PINCONF=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_RAM=y
+CONFIG_DM_SERIAL=y
+CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_SHA512=y
diff --git a/configs/apalis-tk1_defconfig b/configs/apalis-tk1_defconfig
index ef982f70193..73463473dfb 100644
--- a/configs/apalis-tk1_defconfig
+++ b/configs/apalis-tk1_defconfig
@@ -31,6 +31,7 @@ CONFIG_ARCH_MISC_INIT=y
 CONFIG_SPL_FOOTPRINT_LIMIT=y
 CONFIG_SPL_MAX_FOOTPRINT=0x8000
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_SYS_MALLOC=y
 CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
 CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x80090000
diff --git a/configs/apalis_imx6_defconfig b/configs/apalis_imx6_defconfig
index a3f65c5c026..f51386d10a8 100644
--- a/configs/apalis_imx6_defconfig
+++ b/configs/apalis_imx6_defconfig
@@ -31,7 +31,7 @@ CONFIG_DISTRO_DEFAULTS=y
 CONFIG_BOOTDELAY=1
 CONFIG_BOOTCOMMAND="run distro_bootcmd; usb start; setenv stdout serial,vidconsole; setenv stdin serial,usbkbd"
 CONFIG_USE_PREBOOT=y
-CONFIG_PREBOOT="test -n ${fdtfile} || setenv fdtfile imx6q-apalis-${fdt_board}.dtb"
+CONFIG_PREBOOT="test -n ${fdtfile} || setenv fdtfile imx6q-apalis${variant}-${fdt_board}.dtb"
 CONFIG_SYS_CBSIZE=1024
 CONFIG_SYS_PBSIZE=1055
 CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
diff --git a/configs/apalis_t30_defconfig b/configs/apalis_t30_defconfig
index 3143566c2c7..411d6354f8b 100644
--- a/configs/apalis_t30_defconfig
+++ b/configs/apalis_t30_defconfig
@@ -26,6 +26,7 @@ CONFIG_ARCH_MISC_INIT=y
 CONFIG_SPL_FOOTPRINT_LIMIT=y
 CONFIG_SPL_MAX_FOOTPRINT=0x8000
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_SYS_MALLOC=y
 CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
 CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x80090000
diff --git a/configs/arbel_evb_defconfig b/configs/arbel_evb_defconfig
index 67627f5d26d..f5c05fd4616 100644
--- a/configs/arbel_evb_defconfig
+++ b/configs/arbel_evb_defconfig
@@ -25,7 +25,6 @@ CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_USE_BOOTCOMMAND=y
 CONFIG_BOOTCOMMAND="run common_bootargs; run romboot"
-CONFIG_LAST_STAGE_INIT=y
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="U-Boot>"
 CONFIG_SYS_MAXARGS=32
diff --git a/configs/axm_defconfig b/configs/axm_defconfig
index 7fd9e4046f2..6098e5caf5b 100644
--- a/configs/axm_defconfig
+++ b/configs/axm_defconfig
@@ -45,6 +45,7 @@ CONFIG_SPL_PAD_TO=0x20000
 # CONFIG_SPL_LEGACY_IMAGE_FORMAT is not set
 CONFIG_SPL_SYS_MALLOC_SIMPLE=y
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_SYS_MALLOC=y
 CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
 CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x20ba0000
diff --git a/configs/bananapi-f3_defconfig b/configs/bananapi-f3_defconfig
index 0f12db3db84..7483f128bae 100644
--- a/configs/bananapi-f3_defconfig
+++ b/configs/bananapi-f3_defconfig
@@ -18,3 +18,4 @@ CONFIG_HUSH_PARSER=y
 CONFIG_ENV_OVERWRITE=y
 CONFIG_SYS_NS16550=y
 CONFIG_SYS_NS16550_MEM32=y
+CONFIG_RESET_SPACEMIT_K1=y
diff --git a/configs/beaver_defconfig b/configs/beaver_defconfig
index 71037ee7474..8e0c5367352 100644
--- a/configs/beaver_defconfig
+++ b/configs/beaver_defconfig
@@ -22,6 +22,7 @@ CONFIG_SYS_STDIO_DEREGISTER=y
 CONFIG_SPL_FOOTPRINT_LIMIT=y
 CONFIG_SPL_MAX_FOOTPRINT=0x8000
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_SYS_MALLOC=y
 CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
 CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x80090000
diff --git a/configs/bitmain_antminer_s9_defconfig b/configs/bitmain_antminer_s9_defconfig
index edb49de207c..77744d55c3b 100644
--- a/configs/bitmain_antminer_s9_defconfig
+++ b/configs/bitmain_antminer_s9_defconfig
@@ -37,6 +37,7 @@ CONFIG_SYS_PBSIZE=2075
 CONFIG_CLOCKS=y
 CONFIG_SPL_MAX_SIZE=0x30000
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_SYS_MALLOC=y
 CONFIG_SPL_SYS_MALLOC_SIZE=0x2000000
 CONFIG_HUSH_PARSER=y
diff --git a/configs/bk4r1_defconfig b/configs/bk4r1_defconfig
index 3ed587a1060..2b72ec91632 100644
--- a/configs/bk4r1_defconfig
+++ b/configs/bk4r1_defconfig
@@ -59,6 +59,7 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_ARP_TIMEOUT=500
 CONFIG_NETCONSOLE=y
 CONFIG_BOOTCOUNT_LIMIT=y
+CONFIG_BOOTCOUNT_ALTBOOTCMD="led 5 on; boot"
 CONFIG_VYBRID_GPIO=y
 CONFIG_DM_I2C=y
 CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
diff --git a/configs/brppt2_defconfig b/configs/brppt2_defconfig
index f02aef24048..d468465a9cc 100644
--- a/configs/brppt2_defconfig
+++ b/configs/brppt2_defconfig
@@ -76,6 +76,7 @@ CONFIG_SPL_DM_SEQ_ALIAS=y
 # CONFIG_OF_TRANSLATE is not set
 # CONFIG_SPL_BLK is not set
 CONFIG_BOOTCOUNT_LIMIT=y
+CONFIG_BOOTCOUNT_ALTBOOTCMD="setenv b_mode 0; run b_default;"
 CONFIG_SYS_I2C_MXC=y
 CONFIG_MMC_BROKEN_CD=y
 # CONFIG_SPL_DM_MMC is not set
diff --git a/configs/capricorn_cxg3_defconfig b/configs/capricorn_cxg3_defconfig
index 4832a795e50..3cc46067f7d 100644
--- a/configs/capricorn_cxg3_defconfig
+++ b/configs/capricorn_cxg3_defconfig
@@ -52,6 +52,7 @@ CONFIG_SPL_LOAD_IMX_CONTAINER=y
 CONFIG_IMX_CONTAINER_CFG="board/siemens/capricorn/uboot-container.cfg"
 CONFIG_SPL_SYS_MALLOC_SIMPLE=y
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_SYS_MALLOC=y
 CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
 CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x120000
@@ -95,6 +96,7 @@ CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SPL_DM=y
 CONFIG_BOOTCOUNT_LIMIT=y
 CONFIG_BOOTCOUNT_ENV=y
+CONFIG_BOOTCOUNT_ALTBOOTCMD="run bootcmd"
 CONFIG_SPL_CLK=y
 CONFIG_CLK_IMX8=y
 CONFIG_CPU=y
diff --git a/configs/cardhu_defconfig b/configs/cardhu_defconfig
index 57978de66e1..4d1bb6e1cc1 100644
--- a/configs/cardhu_defconfig
+++ b/configs/cardhu_defconfig
@@ -22,6 +22,7 @@ CONFIG_SYS_STDIO_DEREGISTER=y
 CONFIG_SPL_FOOTPRINT_LIMIT=y
 CONFIG_SPL_MAX_FOOTPRINT=0x8000
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_SYS_MALLOC=y
 CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
 CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x80090000
diff --git a/configs/cei-tk1-som_defconfig b/configs/cei-tk1-som_defconfig
index d2778fbcd03..311dd70bc44 100644
--- a/configs/cei-tk1-som_defconfig
+++ b/configs/cei-tk1-som_defconfig
@@ -25,6 +25,7 @@ CONFIG_SYS_STDIO_DEREGISTER=y
 CONFIG_SPL_FOOTPRINT_LIMIT=y
 CONFIG_SPL_MAX_FOOTPRINT=0x8000
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_SYS_MALLOC=y
 CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
 CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x80090000
diff --git a/configs/cgtqmx8_defconfig b/configs/cgtqmx8_defconfig
index 37ae957db03..3f45e9efdde 100644
--- a/configs/cgtqmx8_defconfig
+++ b/configs/cgtqmx8_defconfig
@@ -40,6 +40,7 @@ CONFIG_SPL_MAX_SIZE=0x1f000
 # CONFIG_SPL_BINMAN_UBOOT_SYMBOLS is not set
 CONFIG_SPL_BOARD_INIT=y
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_SYS_MALLOC=y
 CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
 CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x120000
diff --git a/configs/chromebit_mickey_defconfig b/configs/chromebit_mickey_defconfig
index 874f266dad1..1b8d1d4c9e6 100644
--- a/configs/chromebit_mickey_defconfig
+++ b/configs/chromebit_mickey_defconfig
@@ -39,6 +39,7 @@ CONFIG_SPL_PAD_TO=0x7f8000
 CONFIG_SPL_NO_BSS_LIMIT=y
 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_SPI_LOAD=y
 CONFIG_SYS_SPI_U_BOOT_OFFS=0x20000
 CONFIG_CMD_GPIO=y
diff --git a/configs/chromebook_jerry_defconfig b/configs/chromebook_jerry_defconfig
index f40b8e84e39..36b123d2cc7 100644
--- a/configs/chromebook_jerry_defconfig
+++ b/configs/chromebook_jerry_defconfig
@@ -38,6 +38,7 @@ CONFIG_SPL_PAD_TO=0x7f8000
 CONFIG_SPL_NO_BSS_LIMIT=y
 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_SPI_LOAD=y
 CONFIG_SYS_SPI_U_BOOT_OFFS=0x20000
 CONFIG_CMD_GPIO=y
diff --git a/configs/chromebook_minnie_defconfig b/configs/chromebook_minnie_defconfig
index 2f125ba12ad..6b3387a7fb4 100644
--- a/configs/chromebook_minnie_defconfig
+++ b/configs/chromebook_minnie_defconfig
@@ -39,6 +39,7 @@ CONFIG_SPL_PAD_TO=0x7f8000
 CONFIG_SPL_NO_BSS_LIMIT=y
 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_SPI_LOAD=y
 CONFIG_SYS_SPI_U_BOOT_OFFS=0x20000
 CONFIG_CMD_GPIO=y
diff --git a/configs/chromebook_speedy_defconfig b/configs/chromebook_speedy_defconfig
index c19b0905d5c..99a0e454f1d 100644
--- a/configs/chromebook_speedy_defconfig
+++ b/configs/chromebook_speedy_defconfig
@@ -39,6 +39,7 @@ CONFIG_SPL_PAD_TO=0x7f8000
 CONFIG_SPL_NO_BSS_LIMIT=y
 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_SPI_LOAD=y
 CONFIG_SYS_SPI_U_BOOT_OFFS=0x20000
 CONFIG_CMD_GPIO=y
diff --git a/configs/ci20_mmc_defconfig b/configs/ci20_mmc_defconfig
index 2d094bd6e90..2b3086b8673 100644
--- a/configs/ci20_mmc_defconfig
+++ b/configs/ci20_mmc_defconfig
@@ -31,6 +31,7 @@ CONFIG_MISC_INIT_R=y
 CONFIG_SYS_MALLOC_BOOTPARAMS=y
 CONFIG_SPL_MAX_SIZE=0x2e00
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
 # CONFIG_SPL_BANNER_PRINT is not set
 CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1c
diff --git a/configs/clearfog_defconfig b/configs/clearfog_defconfig
index 6f6597c5331..d9314ed1e15 100644
--- a/configs/clearfog_defconfig
+++ b/configs/clearfog_defconfig
@@ -34,6 +34,7 @@ CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_SPL_MAX_SIZE=0x22fd0
 CONFIG_SPL_SYS_MALLOC_SIMPLE=y
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_I2C=y
 CONFIG_SYS_MAXARGS=32
 CONFIG_CMD_TLV_EEPROM=y
diff --git a/configs/clearfog_sata_defconfig b/configs/clearfog_sata_defconfig
index 491a27321f9..d5f90d06ca6 100644
--- a/configs/clearfog_sata_defconfig
+++ b/configs/clearfog_sata_defconfig
@@ -34,6 +34,7 @@ CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_SPL_MAX_SIZE=0x22fd0
 CONFIG_SPL_SYS_MALLOC_SIMPLE=y
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_I2C=y
 CONFIG_SYS_MAXARGS=32
 CONFIG_CMD_TLV_EEPROM=y
diff --git a/configs/clearfog_spi_defconfig b/configs/clearfog_spi_defconfig
index d3de1657c09..8868c7fde5e 100644
--- a/configs/clearfog_spi_defconfig
+++ b/configs/clearfog_spi_defconfig
@@ -34,6 +34,7 @@ CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_SPL_MAX_SIZE=0x22fd0
 CONFIG_SPL_SYS_MALLOC_SIMPLE=y
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_I2C=y
 CONFIG_SYS_MAXARGS=32
 CONFIG_CMD_TLV_EEPROM=y
diff --git a/configs/colibri_imx6_defconfig b/configs/colibri_imx6_defconfig
index 4c6ba80789b..9fc844b3269 100644
--- a/configs/colibri_imx6_defconfig
+++ b/configs/colibri_imx6_defconfig
@@ -30,7 +30,7 @@ CONFIG_DISTRO_DEFAULTS=y
 CONFIG_BOOTDELAY=1
 CONFIG_BOOTCOMMAND="run distro_bootcmd; usb start; setenv stdout serial,vidconsole; setenv stdin serial,usbkbd"
 CONFIG_USE_PREBOOT=y
-CONFIG_PREBOOT="test -n ${fdtfile} || setenv fdtfile imx6dl-colibri-${fdt_board}.dtb"
+CONFIG_PREBOOT="test -n ${fdtfile} || setenv fdtfile imx6dl-colibri${variant}-${fdt_board}.dtb"
 CONFIG_SYS_CBSIZE=1024
 CONFIG_SYS_PBSIZE=1056
 CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
diff --git a/configs/colibri_t20_defconfig b/configs/colibri_t20_defconfig
index 6c5c1a92712..feb24d843b3 100644
--- a/configs/colibri_t20_defconfig
+++ b/configs/colibri_t20_defconfig
@@ -24,6 +24,7 @@ CONFIG_ARCH_MISC_INIT=y
 CONFIG_SPL_FOOTPRINT_LIMIT=y
 CONFIG_SPL_MAX_FOOTPRINT=0x8000
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_SYS_MALLOC=y
 CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
 CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x90000
diff --git a/configs/colibri_t30_defconfig b/configs/colibri_t30_defconfig
index 4f2dde6d84a..3a8ea1c1a76 100644
--- a/configs/colibri_t30_defconfig
+++ b/configs/colibri_t30_defconfig
@@ -25,6 +25,7 @@ CONFIG_ARCH_MISC_INIT=y
 CONFIG_SPL_FOOTPRINT_LIMIT=y
 CONFIG_SPL_MAX_FOOTPRINT=0x8000
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_SYS_MALLOC=y
 CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
 CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x80090000
diff --git a/configs/controlcenterdc_defconfig b/configs/controlcenterdc_defconfig
index e6242e22509..0e1b22c49d9 100644
--- a/configs/controlcenterdc_defconfig
+++ b/configs/controlcenterdc_defconfig
@@ -44,6 +44,7 @@ CONFIG_SPL_MAX_SIZE=0x27fd0
 CONFIG_SPL_BOARD_INIT=y
 CONFIG_SPL_SYS_MALLOC_SIMPLE=y
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_I2C=y
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_MAXARGS=32
diff --git a/configs/coreboot64-no-spl_defconfig b/configs/coreboot64-no-spl_defconfig
new file mode 100644
index 00000000000..dd07524560b
--- /dev/null
+++ b/configs/coreboot64-no-spl_defconfig
@@ -0,0 +1,62 @@
+CONFIG_X86=y
+CONFIG_TEXT_BASE=0x1110000
+CONFIG_SYS_MALLOC_LEN=0x2000000
+CONFIG_NR_DRAM_BANKS=8
+CONFIG_ENV_SIZE=0x1000
+CONFIG_DEFAULT_DEVICE_TREE="coreboot"
+CONFIG_PRE_CON_BUF_ADDR=0x100000
+CONFIG_X86_RUN_64BIT_NO_SPL=y
+CONFIG_VENDOR_COREBOOT=y
+CONFIG_TARGET_COREBOOT=y
+CONFIG_FIT=y
+CONFIG_FIT_SIGNATURE=y
+CONFIG_BOOTSTD_FULL=y
+CONFIG_BOOTSTD_DEFAULTS=y
+CONFIG_SYS_MONITOR_BASE=0x01110000
+CONFIG_SHOW_BOOT_PROGRESS=y
+CONFIG_USE_BOOTARGS=y
+CONFIG_BOOTARGS="root=/dev/sdb3 init=/sbin/init rootwait ro"
+CONFIG_BOOTCOMMAND="bootflow scan -l; if bootflow menu; then bootflow boot; fi"
+CONFIG_PRE_CONSOLE_BUFFER=y
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
+CONFIG_LOG=y
+CONFIG_LOGF_LINE=y
+CONFIG_LOGF_FUNC=y
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_CMD_IDE=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SATA=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_BOOTP_BOOTFILESIZE=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_SOUND=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_MAC_PARTITION=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_USE_BOOTFILE=y
+CONFIG_BOOTFILE="bzImage"
+CONFIG_TFTP_TSIZE=y
+CONFIG_USE_ROOTPATH=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+# CONFIG_ACPIGEN is not set
+CONFIG_SYS_IDE_MAXDEVICE=4
+CONFIG_SYS_ATA_DATA_OFFSET=0
+CONFIG_SYS_ATA_REG_OFFSET=0
+CONFIG_SYS_ATA_ALT_OFFSET=0
+CONFIG_ATAPI=y
+CONFIG_LBA48=y
+CONFIG_SYS_64BIT_LBA=y
+CONFIG_NVME_PCI=y
+# CONFIG_PCI_PNP is not set
+CONFIG_SYS_NS16550_MEM32=y
+CONFIG_SOUND=y
+CONFIG_SOUND_I8254=y
+CONFIG_VIDEO_COPY=y
+CONFIG_CONSOLE_TRUETYPE=y
+CONFIG_CONSOLE_SCROLL_LINES=5
+CONFIG_CMD_DHRYSTONE=y
+# CONFIG_GZIP is not set
+CONFIG_SMBIOS_PARSER=y
diff --git a/configs/corvus_defconfig b/configs/corvus_defconfig
index ce2f4f7d91e..85cd4623c48 100644
--- a/configs/corvus_defconfig
+++ b/configs/corvus_defconfig
@@ -41,6 +41,7 @@ CONFIG_SPL_MAX_SIZE=0x3000
 CONFIG_SPL_PAD_TO=0x20000
 CONFIG_SPL_SYS_MALLOC_SIMPLE=y
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_NAND_SUPPORT=y
 CONFIG_SPL_NAND_RAW_ONLY=y
 CONFIG_SPL_NAND_DRIVERS=y
diff --git a/configs/da850evm_defconfig b/configs/da850evm_defconfig
index 4cddc7f5836..861bfea28e9 100644
--- a/configs/da850evm_defconfig
+++ b/configs/da850evm_defconfig
@@ -46,6 +46,7 @@ CONFIG_SPL_FOOTPRINT_LIMIT=y
 CONFIG_SPL_MAX_FOOTPRINT=0x8000
 CONFIG_SPL_SYS_MALLOC_SIMPLE=y
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_SYS_MALLOC=y
 CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
 CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0xc0f70000
diff --git a/configs/da850evm_nand_defconfig b/configs/da850evm_nand_defconfig
index b8b1a96c16a..27910a5b9b1 100644
--- a/configs/da850evm_nand_defconfig
+++ b/configs/da850evm_nand_defconfig
@@ -42,6 +42,7 @@ CONFIG_SPL_FOOTPRINT_LIMIT=y
 CONFIG_SPL_MAX_FOOTPRINT=0x8000
 CONFIG_SPL_SYS_MALLOC_SIMPLE=y
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_SYS_MALLOC=y
 CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
 CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0xc0f70000
diff --git a/configs/dalmore_defconfig b/configs/dalmore_defconfig
index 4dba3717abb..e35a4f43384 100644
--- a/configs/dalmore_defconfig
+++ b/configs/dalmore_defconfig
@@ -21,6 +21,7 @@ CONFIG_SYS_STDIO_DEREGISTER=y
 CONFIG_SPL_FOOTPRINT_LIMIT=y
 CONFIG_SPL_MAX_FOOTPRINT=0x8000
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_SYS_MALLOC=y
 CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
 CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x80090000
diff --git a/configs/db-88f6720_defconfig b/configs/db-88f6720_defconfig
index d2f400dae8d..79e3f568bf8 100644
--- a/configs/db-88f6720_defconfig
+++ b/configs/db-88f6720_defconfig
@@ -32,6 +32,7 @@ CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_SPL_MAX_SIZE=0x1ffd0
 CONFIG_SPL_SYS_MALLOC_SIMPLE=y
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_I2C=y
 CONFIG_SYS_MAXARGS=32
 CONFIG_CMD_I2C=y
diff --git a/configs/db-88f6820-amc_defconfig b/configs/db-88f6820-amc_defconfig
index 23fe44faf51..7742bf77482 100644
--- a/configs/db-88f6820-amc_defconfig
+++ b/configs/db-88f6820-amc_defconfig
@@ -35,6 +35,7 @@ CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_SPL_MAX_SIZE=0x22fd0
 CONFIG_SPL_SYS_MALLOC_SIMPLE=y
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_I2C=y
 CONFIG_SYS_MAXARGS=96
 CONFIG_CMD_I2C=y
diff --git a/configs/db-88f6820-amc_nand_defconfig b/configs/db-88f6820-amc_nand_defconfig
index f0dd977748b..d970cf72be7 100644
--- a/configs/db-88f6820-amc_nand_defconfig
+++ b/configs/db-88f6820-amc_nand_defconfig
@@ -37,6 +37,7 @@ CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_SPL_MAX_SIZE=0x22fd0
 CONFIG_SPL_SYS_MALLOC_SIMPLE=y
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_I2C=y
 CONFIG_SYS_MAXARGS=96
 CONFIG_CMD_I2C=y
diff --git a/configs/db-88f6820-gp_defconfig b/configs/db-88f6820-gp_defconfig
index cb017a72551..b93c717e5b3 100644
--- a/configs/db-88f6820-gp_defconfig
+++ b/configs/db-88f6820-gp_defconfig
@@ -33,6 +33,7 @@ CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_SPL_MAX_SIZE=0x22fd0
 CONFIG_SPL_SYS_MALLOC_SIMPLE=y
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_I2C=y
 CONFIG_SYS_MAXARGS=32
 CONFIG_CMD_I2C=y
diff --git a/configs/db-mv784mp-gp_defconfig b/configs/db-mv784mp-gp_defconfig
index a417c944b0f..5aa19109ed9 100644
--- a/configs/db-mv784mp-gp_defconfig
+++ b/configs/db-mv784mp-gp_defconfig
@@ -33,6 +33,7 @@ CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_SPL_MAX_SIZE=0x1bfd0
 CONFIG_SPL_SYS_MALLOC_SIMPLE=y
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_I2C=y
 CONFIG_SYS_MAXARGS=32
 CONFIG_CMD_I2C=y
diff --git a/configs/dh_imx6.config b/configs/dh_imx6.config
new file mode 100644
index 00000000000..01db41be2a0
--- /dev/null
+++ b/configs/dh_imx6.config
@@ -0,0 +1,76 @@
+#include <configs/imx_dhsom.config>
+
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_MX6QDL=y
+CONFIG_TARGET_DHCOMIMX6=y
+CONFIG_SPL_SYS_L2_PL310=y
+CONFIG_MX6_DDRCAL=y
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_OF_UPSTREAM=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_MULTI_DTB_FIT=y
+CONFIG_LTO=y
+
+CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_SYS_MALLOC_F_LEN=0x1000
+CONFIG_SYS_MAXARGS=32
+CONFIG_SYS_MEMTEST_END=0x20000000
+CONFIG_SYS_MEMTEST_START=0x10000000
+CONFIG_SYS_MONITOR_LEN=409600
+CONFIG_SYS_PBSIZE=532
+
+CONFIG_SYS_BOOTCOUNT_ADDR=0x020CC068
+CONFIG_SYS_BOOTCOUNT_BE=y
+CONFIG_BOOTCOUNT_LIMIT=y
+CONFIG_BOOTDELAY=3
+
+CONFIG_BZIP2=y
+CONFIG_CMD_SATA=y
+CONFIG_CMD_UNZIP=y
+CONFIG_CMD_WDT=y
+CONFIG_DISTRO_DEFAULTS=y
+
+CONFIG_ENV_OFFSET=0x100000
+CONFIG_ENV_OFFSET_REDUND=0x110000
+CONFIG_ENV_SECT_SIZE=0x10000
+CONFIG_ENV_SIZE=0x4000
+
+# CONFIG_CMD_SCSI is not set
+CONFIG_AHCI=y
+CONFIG_BOUNCE_BUFFER=y
+CONFIG_DWC_AHSATA=y
+CONFIG_LBA48=y
+CONFIG_SCSI=y
+
+CONFIG_ARP_TIMEOUT=200
+CONFIG_ETHPRIME="FEC"
+CONFIG_USE_ETHPRIME=y
+CONFIG_PHYLIB=y
+
+CONFIG_SF_DEFAULT_SPEED=25000000
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_UNLOCK_ALL=y
+
+CONFIG_MISC=y
+
+CONFIG_PINCTRL_IMX6=y
+
+CONFIG_SDP_LOADADDR=0x17ffffc0
+CONFIG_SPL_FIT=y
+CONFIG_SPL_SPI=y
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI_LOAD=y
+CONFIG_SPL_USB_GADGET=y
+CONFIG_SPL_USB_HOST=y
+CONFIG_SPL_USB_SDP_SUPPORT=y
+CONFIG_SYS_DFU_DATA_BUF_SIZE=0x1000000
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x11400
+CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+
+CONFIG_WATCHDOG_TIMEOUT_MSECS=60000
diff --git a/configs/dh_imx6_defconfig b/configs/dh_imx6_defconfig
index 43ac5a567ba..552d743b7df 100644
--- a/configs/dh_imx6_defconfig
+++ b/configs/dh_imx6_defconfig
@@ -1,78 +1,4 @@
-#include <configs/imx_dhsom.config>
+#include <configs/dh_imx6.config>
 
-CONFIG_ARM=y
-CONFIG_ARCH_MX6=y
-CONFIG_MX6QDL=y
-CONFIG_TARGET_DHCOMIMX6=y
-CONFIG_SPL_SYS_L2_PL310=y
 CONFIG_DEFAULT_DEVICE_TREE="nxp/imx/imx6q-dhcom-pdk2"
-CONFIG_MX6_DDRCAL=y
-CONFIG_NR_DRAM_BANKS=1
-CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_OF_LIST="nxp/imx/imx6q-dhcom-pdk2 nxp/imx/imx6dl-dhcom-pdk2 nxp/imx/imx6s-dhcom-drc02 nxp/imx/imx6dl-dhcom-picoitx"
-CONFIG_OF_UPSTREAM=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_MULTI_DTB_FIT=y
-CONFIG_LTO=y
-
-CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
-CONFIG_SYS_I2C_MXC=y
-CONFIG_SYS_MALLOC_F_LEN=0x1000
-CONFIG_SYS_MAXARGS=32
-CONFIG_SYS_MEMTEST_END=0x20000000
-CONFIG_SYS_MEMTEST_START=0x10000000
-CONFIG_SYS_MONITOR_LEN=409600
-CONFIG_SYS_PBSIZE=532
-
-CONFIG_SYS_BOOTCOUNT_ADDR=0x020CC068
-CONFIG_SYS_BOOTCOUNT_BE=y
-CONFIG_BOOTCOUNT_LIMIT=y
-CONFIG_BOOTDELAY=3
-
-CONFIG_BZIP2=y
-CONFIG_CMD_SATA=y
-CONFIG_CMD_UNZIP=y
-CONFIG_CMD_WDT=y
-CONFIG_DISTRO_DEFAULTS=y
-
-CONFIG_ENV_OFFSET=0x100000
-CONFIG_ENV_OFFSET_REDUND=0x110000
-CONFIG_ENV_SECT_SIZE=0x10000
-CONFIG_ENV_SIZE=0x4000
-
-# CONFIG_CMD_SCSI is not set
-CONFIG_AHCI=y
-CONFIG_BOUNCE_BUFFER=y
-CONFIG_DWC_AHSATA=y
-CONFIG_LBA48=y
-CONFIG_SCSI=y
-
-CONFIG_ARP_TIMEOUT=200
-CONFIG_ETHPRIME="FEC"
-CONFIG_USE_ETHPRIME=y
-CONFIG_PHYLIB=y
-
-CONFIG_SF_DEFAULT_SPEED=25000000
-CONFIG_SPI_FLASH_GIGADEVICE=y
-CONFIG_SPI_FLASH_MACRONIX=y
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_SPI_FLASH_UNLOCK_ALL=y
-
-CONFIG_MISC=y
-
-CONFIG_PINCTRL_IMX6=y
-
-CONFIG_SDP_LOADADDR=0x17ffffc0
-CONFIG_SPL_FIT=y
-CONFIG_SPL_SPI=y
-CONFIG_SPL_SPI_FLASH_SUPPORT=y
-CONFIG_SPL_SPI_LOAD=y
-CONFIG_SPL_USB_GADGET=y
-CONFIG_SPL_USB_HOST=y
-CONFIG_SPL_USB_SDP_SUPPORT=y
-CONFIG_SYS_DFU_DATA_BUF_SIZE=0x1000000
-CONFIG_SYS_SPI_U_BOOT_OFFS=0x11400
-CONFIG_CI_UDC=y
-CONFIG_USB_GADGET_DOWNLOAD=y
-
-CONFIG_WATCHDOG_TIMEOUT_MSECS=60000
diff --git a/configs/display5_defconfig b/configs/display5_defconfig
index 765920bd5d1..a00a042ada6 100644
--- a/configs/display5_defconfig
+++ b/configs/display5_defconfig
@@ -53,6 +53,9 @@ CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR=0x3F00
 CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS=0x10
 CONFIG_SPL_SPI_LOAD=y
 CONFIG_SYS_SPI_U_BOOT_OFFS=0x20000
+CONFIG_SYS_SPI_KERNEL_OFFS=0x150000
+CONFIG_SYS_SPI_ARGS_OFFS=0x140000
+CONFIG_SYS_SPI_ARGS_SIZE=0x10000
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="display5 > "
 CONFIG_SYS_MAXARGS=32
@@ -96,6 +99,7 @@ CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_BOUNCE_BUFFER=y
 CONFIG_BOOTCOUNT_LIMIT=y
+CONFIG_BOOTCOUNT_ALTBOOTCMD="run recovery"
 CONFIG_SPL_SYS_I2C_LEGACY=y
 CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
 CONFIG_I2C_DEFAULT_BUS_NUMBER=0x2
diff --git a/configs/display5_factory_defconfig b/configs/display5_factory_defconfig
index 4007c8900ce..9965e00a1d0 100644
--- a/configs/display5_factory_defconfig
+++ b/configs/display5_factory_defconfig
@@ -48,6 +48,9 @@ CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR=0x3F00
 CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS=0x10
 CONFIG_SPL_SPI_LOAD=y
 CONFIG_SYS_SPI_U_BOOT_OFFS=0x20000
+CONFIG_SYS_SPI_KERNEL_OFFS=0x150000
+CONFIG_SYS_SPI_ARGS_OFFS=0x140000
+CONFIG_SYS_SPI_ARGS_SIZE=0x10000
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="display5 factory > "
 CONFIG_SYS_MAXARGS=32
diff --git a/configs/dra7xx_evm_defconfig b/configs/dra7xx_evm_defconfig
index 2448befb295..f9cb732357c 100644
--- a/configs/dra7xx_evm_defconfig
+++ b/configs/dra7xx_evm_defconfig
@@ -43,6 +43,9 @@ CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR=0x1500
 CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS=0x200
 CONFIG_SPL_SPI_LOAD=y
 CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000
+CONFIG_SYS_SPI_KERNEL_OFFS=0x1E0000
+CONFIG_SYS_SPI_ARGS_OFFS=0x140000
+CONFIG_SYS_SPI_ARGS_SIZE=0x80000
 CONFIG_CMD_SPL=y
 CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
 CONFIG_CMD_NAND=y
diff --git a/configs/dra7xx_hs_evm_defconfig b/configs/dra7xx_hs_evm_defconfig
index f6f00454aaa..81da64be811 100644
--- a/configs/dra7xx_hs_evm_defconfig
+++ b/configs/dra7xx_hs_evm_defconfig
@@ -40,6 +40,9 @@ CONFIG_SPL_NAND_ECC=y
 CONFIG_SPL_DM_SPI_FLASH=y
 CONFIG_SPL_SPI_LOAD=y
 CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000
+CONFIG_SYS_SPI_KERNEL_OFFS=0x1E0000
+CONFIG_SYS_SPI_ARGS_OFFS=0x140000
+CONFIG_SYS_SPI_ARGS_SIZE=0x80000
 CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
 CONFIG_CMD_NAND=y
 CONFIG_BOOTP_DNS2=y
diff --git a/configs/dra7xx_hs_evm_usb_defconfig b/configs/dra7xx_hs_evm_usb_defconfig
index 850ccd934b7..1d099a56ee8 100644
--- a/configs/dra7xx_hs_evm_usb_defconfig
+++ b/configs/dra7xx_hs_evm_usb_defconfig
@@ -39,6 +39,9 @@ CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot.img"
 CONFIG_SPL_DM_SPI_FLASH=y
 CONFIG_SPL_SPI_LOAD=y
 CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000
+CONFIG_SYS_SPI_KERNEL_OFFS=0x1E0000
+CONFIG_SYS_SPI_ARGS_OFFS=0x140000
+CONFIG_SYS_SPI_ARGS_SIZE=0x80000
 CONFIG_SPL_YMODEM_SUPPORT=y
 CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
 # CONFIG_CMD_SETEXPR is not set
diff --git a/configs/draco-etamin_defconfig b/configs/draco-etamin_defconfig
index f650dbca660..6c175dd73b9 100644
--- a/configs/draco-etamin_defconfig
+++ b/configs/draco-etamin_defconfig
@@ -79,6 +79,7 @@ CONFIG_SPL_DM=y
 # CONFIG_SPL_BLK is not set
 CONFIG_BOOTCOUNT_LIMIT=y
 CONFIG_BOOTCOUNT_ENV=y
+CONFIG_BOOTCOUNT_ALTBOOTCMD="run bootcmd"
 CONFIG_CLK=y
 CONFIG_CLK_TI_CTRL=y
 CONFIG_DFU_NAND=y
diff --git a/configs/draco-rastaban_defconfig b/configs/draco-rastaban_defconfig
index 511956ec844..521a090e376 100644
--- a/configs/draco-rastaban_defconfig
+++ b/configs/draco-rastaban_defconfig
@@ -76,6 +76,7 @@ CONFIG_SPL_DM=y
 # CONFIG_SPL_BLK is not set
 CONFIG_BOOTCOUNT_LIMIT=y
 CONFIG_BOOTCOUNT_ENV=y
+CONFIG_BOOTCOUNT_ALTBOOTCMD="run bootcmd"
 CONFIG_CLK=y
 CONFIG_CLK_TI_CTRL=y
 CONFIG_DFU_NAND=y
diff --git a/configs/draco-thuban_defconfig b/configs/draco-thuban_defconfig
index 1b2ce3b0104..2c16db237f8 100644
--- a/configs/draco-thuban_defconfig
+++ b/configs/draco-thuban_defconfig
@@ -76,6 +76,7 @@ CONFIG_SPL_DM=y
 # CONFIG_SPL_BLK is not set
 CONFIG_BOOTCOUNT_LIMIT=y
 CONFIG_BOOTCOUNT_ENV=y
+CONFIG_BOOTCOUNT_ALTBOOTCMD="run bootcmd"
 CONFIG_CLK=y
 CONFIG_CLK_TI_CTRL=y
 CONFIG_DFU_NAND=y
diff --git a/configs/ds116_defconfig b/configs/ds116_defconfig
index 8562874ecde..f4481b88b30 100644
--- a/configs/ds116_defconfig
+++ b/configs/ds116_defconfig
@@ -40,6 +40,7 @@ CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_SPL_MAX_SIZE=0x22fd0
 CONFIG_SPL_SYS_MALLOC_SIMPLE=y
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_I2C=y
 CONFIG_SYS_PROMPT="DS116> "
 CONFIG_SYS_MAXARGS=32
diff --git a/configs/ds414_defconfig b/configs/ds414_defconfig
index 44e9b176827..ee2ee60c92c 100644
--- a/configs/ds414_defconfig
+++ b/configs/ds414_defconfig
@@ -40,6 +40,7 @@ CONFIG_MISC_INIT_R=y
 CONFIG_SPL_MAX_SIZE=0x1bfd0
 CONFIG_SPL_SYS_MALLOC_SIMPLE=y
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_I2C=y
 CONFIG_SYS_PROMPT="DS414> "
 CONFIG_SYS_MAXARGS=32
diff --git a/configs/endeavoru_defconfig b/configs/endeavoru_defconfig
index 1d1f1042291..fb3d7fc6238 100644
--- a/configs/endeavoru_defconfig
+++ b/configs/endeavoru_defconfig
@@ -21,11 +21,12 @@ CONFIG_AUTOBOOT_KEYED=y
 CONFIG_AUTOBOOT_KEYED_CTRLC=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_SYSTEM_SETUP=y
-CONFIG_BOOTCOMMAND="bootflow scan; poweroff"
+CONFIG_BOOTCOMMAND="bootflow scan; echo 'Boot configuration not found... Power off in 3 sec'; sleep 3; poweroff"
 CONFIG_SYS_PBSIZE=2084
 CONFIG_SPL_FOOTPRINT_LIMIT=y
 CONFIG_SPL_MAX_FOOTPRINT=0x8000
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_SYS_MALLOC=y
 CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
 CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x80090000
@@ -79,6 +80,7 @@ CONFIG_USB_GADGET_VENDOR_NUM=0x0bb4
 CONFIG_USB_GADGET_PRODUCT_NUM=0x0c02
 CONFIG_CI_UDC=y
 CONFIG_VIDEO=y
+CONFIG_VIDEO_BRIDGE=y
 # CONFIG_VIDEO_LOGO is not set
 CONFIG_VIDEO_LCD_ENDEAVORU=y
 CONFIG_VIDEO_DSI_TEGRA30=y
diff --git a/configs/evb-px5_defconfig b/configs/evb-px5_defconfig
index b08714437fd..9dbd26ed6bf 100644
--- a/configs/evb-px5_defconfig
+++ b/configs/evb-px5_defconfig
@@ -44,6 +44,7 @@ CONFIG_SPL_PAD_TO=0x7f8000
 CONFIG_SPL_BOOTROM_SUPPORT=y
 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_ATF=y
 CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
 CONFIG_TPL=y
diff --git a/configs/evb-rk3036_defconfig b/configs/evb-rk3036_defconfig
index d215af0c046..209d6b6ca90 100644
--- a/configs/evb-rk3036_defconfig
+++ b/configs/evb-rk3036_defconfig
@@ -29,6 +29,7 @@ CONFIG_DISPLAY_BOARDINFO_LATE=y
 # CONFIG_SPL_FRAMEWORK is not set
 CONFIG_SPL_PAD_TO=0x7f8000
 CONFIG_SPL_NO_BSS_LIMIT=y
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_CMD_GPT=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
diff --git a/configs/evb-rk3288_defconfig b/configs/evb-rk3288_defconfig
index ae79efebf57..95615ce1707 100644
--- a/configs/evb-rk3288_defconfig
+++ b/configs/evb-rk3288_defconfig
@@ -36,6 +36,7 @@ CONFIG_SPL_PAD_TO=0x7f8000
 CONFIG_SPL_NO_BSS_LIMIT=y
 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_OPTEE_IMAGE=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_GPT=y
diff --git a/configs/gardena-smart-gateway-at91sam_defconfig b/configs/gardena-smart-gateway-at91sam_defconfig
index c9eb661aab0..fbcc84da9ae 100644
--- a/configs/gardena-smart-gateway-at91sam_defconfig
+++ b/configs/gardena-smart-gateway-at91sam_defconfig
@@ -44,6 +44,7 @@ CONFIG_SPL_MAX_SIZE=0x7000
 CONFIG_SPL_PAD_TO=0x40000
 CONFIG_SPL_SYS_MALLOC_SIMPLE=y
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_SYS_MALLOC=y
 CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
 CONFIG_SPL_NAND_SUPPORT=y
diff --git a/configs/ge_b1x5v2_defconfig b/configs/ge_b1x5v2_defconfig
index 215858c789b..fec4b67aee2 100644
--- a/configs/ge_b1x5v2_defconfig
+++ b/configs/ge_b1x5v2_defconfig
@@ -78,6 +78,7 @@ CONFIG_BOUNCE_BUFFER=y
 CONFIG_BOOTCOUNT_LIMIT=y
 CONFIG_DM_BOOTCOUNT=y
 CONFIG_DM_BOOTCOUNT_SPI_FLASH=y
+CONFIG_BOOTCOUNT_ALTBOOTCMD="setenv mmcpart 1; run hasfirstboot || setenv mmcpart 2; run hasfirstboot || setenv mmcpart 0; if test ${mmcpart} != 0; then setenv bootcause REVERT; run swappartitions loadimage doboot; fi; run failbootcmd"
 CONFIG_DM_PCA953X=y
 CONFIG_DM_I2C=y
 CONFIG_SYS_I2C_MXC=y
diff --git a/configs/ge_bx50v3_defconfig b/configs/ge_bx50v3_defconfig
index c24513f6ab1..676b5bc8a28 100644
--- a/configs/ge_bx50v3_defconfig
+++ b/configs/ge_bx50v3_defconfig
@@ -52,6 +52,7 @@ CONFIG_BOUNCE_BUFFER=y
 CONFIG_BOOTCOUNT_LIMIT=y
 CONFIG_DM_BOOTCOUNT=y
 CONFIG_DM_BOOTCOUNT_I2C_EEPROM=y
+CONFIG_BOOTCOUNT_ALTBOOTCMD="run doquiet; setenv partnum 1; run hasfirstboot || setenv partnum 2; run hasfirstboot || setenv partnum 0; if test ${partnum} != 0; then run swappartitions loadimage doboot; fi; run failbootcmd"
 CONFIG_DM_I2C=y
 CONFIG_SYS_I2C_MXC=y
 CONFIG_I2C_MUX=y
diff --git a/configs/gose_defconfig b/configs/gose_defconfig
index b53f2f37409..b604647c8e4 100644
--- a/configs/gose_defconfig
+++ b/configs/gose_defconfig
@@ -14,6 +14,7 @@ CONFIG_ARCH_RENESAS_BOARD_STRING="Gose"
 CONFIG_R8A7793=y
 CONFIG_TARGET_GOSE=y
 CONFIG_SPL_SERIAL=y
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_STACK=0xe6340000
 CONFIG_SPL_SYS_MALLOC_F_LEN=0x2000
 CONFIG_SPL=y
diff --git a/configs/grouper_defconfig b/configs/grouper_defconfig
index 9221ffb46a3..b98f23a4baf 100644
--- a/configs/grouper_defconfig
+++ b/configs/grouper_defconfig
@@ -21,11 +21,12 @@ CONFIG_AUTOBOOT_KEYED=y
 CONFIG_AUTOBOOT_KEYED_CTRLC=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_SYSTEM_SETUP=y
-CONFIG_BOOTCOMMAND="bootflow scan; poweroff"
+CONFIG_BOOTCOMMAND="bootflow scan; echo 'Boot configuration not found... Power off in 3 sec'; sleep 3; poweroff"
 CONFIG_SYS_PBSIZE=2084
 CONFIG_SPL_FOOTPRINT_LIMIT=y
 CONFIG_SPL_MAX_FOOTPRINT=0x8000
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_SYS_MALLOC=y
 CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
 CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x80090000
diff --git a/configs/harmony_defconfig b/configs/harmony_defconfig
index d8cc8451bac..fa8fe24ca38 100644
--- a/configs/harmony_defconfig
+++ b/configs/harmony_defconfig
@@ -19,6 +19,7 @@ CONFIG_SYS_STDIO_DEREGISTER=y
 CONFIG_SPL_FOOTPRINT_LIMIT=y
 CONFIG_SPL_MAX_FOOTPRINT=0x8000
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_SYS_MALLOC=y
 CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
 CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x90000
diff --git a/configs/helios4_defconfig b/configs/helios4_defconfig
index 2778cb7dc86..6927e20abd1 100644
--- a/configs/helios4_defconfig
+++ b/configs/helios4_defconfig
@@ -34,6 +34,7 @@ CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_SPL_MAX_SIZE=0x22fd0
 CONFIG_SPL_SYS_MALLOC_SIMPLE=y
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_I2C=y
 CONFIG_SYS_MAXARGS=32
 CONFIG_CMD_TLV_EEPROM=y
diff --git a/configs/ideapad-yoga-11_defconfig b/configs/ideapad-yoga-11_defconfig
index 3c152cbfb98..bc7f615cdf0 100644
--- a/configs/ideapad-yoga-11_defconfig
+++ b/configs/ideapad-yoga-11_defconfig
@@ -24,6 +24,7 @@ CONFIG_SYS_PBSIZE=2084
 CONFIG_SPL_FOOTPRINT_LIMIT=y
 CONFIG_SPL_MAX_FOOTPRINT=0x8000
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_SYS_MALLOC=y
 CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
 CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x80090000
diff --git a/configs/imx28_xea_defconfig b/configs/imx28_xea_defconfig
index 38282e6ea92..bf80a19bd96 100644
--- a/configs/imx28_xea_defconfig
+++ b/configs/imx28_xea_defconfig
@@ -49,6 +49,7 @@ CONFIG_SPL_BOARD_INIT=y
 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
 CONFIG_SPL_SYS_MALLOC_SIMPLE=y
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x0
 CONFIG_SUPPORT_EMMC_BOOT_OVERRIDE_PART_CONFIG=y
 CONFIG_SPL_DMA=y
@@ -62,6 +63,9 @@ CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR=0x400
 CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS=0x40
 CONFIG_SPL_SPI_LOAD=y
 CONFIG_SYS_SPI_U_BOOT_OFFS=0x10000
+CONFIG_SYS_SPI_KERNEL_OFFS=0x100000
+CONFIG_SYS_SPI_ARGS_OFFS=0x80000
+CONFIG_SYS_SPI_ARGS_SIZE=0x8000
 CONFIG_SPL_YMODEM_SUPPORT=y
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_MAXARGS=32
diff --git a/configs/imx6_dhcom_drc02_defconfig b/configs/imx6_dhcom_drc02_defconfig
new file mode 100644
index 00000000000..72a0498d9b2
--- /dev/null
+++ b/configs/imx6_dhcom_drc02_defconfig
@@ -0,0 +1,4 @@
+#include <configs/dh_imx6.config>
+
+CONFIG_DEFAULT_DEVICE_TREE="nxp/imx/imx6s-dhcom-drc02"
+CONFIG_OF_LIST="nxp/imx/imx6s-dhcom-drc02"
diff --git a/configs/imx6_dhcom_pdk2_defconfig b/configs/imx6_dhcom_pdk2_defconfig
new file mode 100644
index 00000000000..6cc81f624f7
--- /dev/null
+++ b/configs/imx6_dhcom_pdk2_defconfig
@@ -0,0 +1,4 @@
+#include <configs/dh_imx6.config>
+
+CONFIG_DEFAULT_DEVICE_TREE="nxp/imx/imx6q-dhcom-pdk2"
+CONFIG_OF_LIST="nxp/imx/imx6q-dhcom-pdk2 nxp/imx/imx6dl-dhcom-pdk2"
diff --git a/configs/imx6_dhcom_picoitx_defconfig b/configs/imx6_dhcom_picoitx_defconfig
new file mode 100644
index 00000000000..837aab6810f
--- /dev/null
+++ b/configs/imx6_dhcom_picoitx_defconfig
@@ -0,0 +1,4 @@
+#include <configs/dh_imx6.config>
+
+CONFIG_DEFAULT_DEVICE_TREE="nxp/imx/imx6dl-dhcom-picoitx"
+CONFIG_OF_LIST="nxp/imx/imx6dl-dhcom-picoitx"
diff --git a/configs/imx6q_bosch_acc_defconfig b/configs/imx6q_bosch_acc_defconfig
index 54758df8c01..017c27479d2 100644
--- a/configs/imx6q_bosch_acc_defconfig
+++ b/configs/imx6q_bosch_acc_defconfig
@@ -86,6 +86,7 @@ CONFIG_SPL_DM=y
 CONFIG_BOOTCOUNT_LIMIT=y
 CONFIG_DM_BOOTCOUNT=y
 CONFIG_DM_BOOTCOUNT_PMIC_PFUZE100=y
+CONFIG_BOOTCOUNT_ALTBOOTCMD="run handle_ustate; run switch_bootset; run save_env; run bootcmd"
 CONFIG_SYS_I2C_MXC=y
 CONFIG_SUPPORT_EMMC_BOOT=y
 CONFIG_FSL_USDHC=y
diff --git a/configs/imx6qdl_icore_mmc_defconfig b/configs/imx6qdl_icore_mmc_defconfig
index fb0787d1beb..269fe271a76 100644
--- a/configs/imx6qdl_icore_mmc_defconfig
+++ b/configs/imx6qdl_icore_mmc_defconfig
@@ -72,6 +72,7 @@ CONFIG_ENV_IS_IN_MMC=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_BOUNCE_BUFFER=y
 CONFIG_BOOTCOUNT_LIMIT=y
+CONFIG_BOOTCOUNT_ALTBOOTCMD="run recoveryboot"
 CONFIG_SYS_BOOTCOUNT_MAGIC=0x0B01C041
 CONFIG_SYS_I2C_MXC=y
 CONFIG_FSL_USDHC=y
diff --git a/configs/imx8m_data_modul.config b/configs/imx8m_data_modul.config
index 2164c754915..37e11e518a8 100644
--- a/configs/imx8m_data_modul.config
+++ b/configs/imx8m_data_modul.config
@@ -13,6 +13,7 @@ CONFIG_ARCH_MISC_INIT=y
 CONFIG_ARM=y
 CONFIG_BOARD_LATE_INIT=y
 CONFIG_BOOTCOMMAND="run dmo_update_env ; load ${devtype} ${devnum}:${devpart} ${loadaddr} boot/fitImage && source ${loadaddr}:bootscr-boot.cmd ; reset"
+CONFIG_BOOTCOUNT_ALTBOOTCMD="run bootcmd"
 CONFIG_BOOTCOUNT_BOOTLIMIT=3
 CONFIG_BOOTCOUNT_LIMIT=y
 CONFIG_CLK_COMPOSITE_CCF=y
diff --git a/configs/imx8mm-cl-iot-gate-optee_defconfig b/configs/imx8mm-cl-iot-gate-optee_defconfig
index 722a5969732..dbc439c23f5 100644
--- a/configs/imx8mm-cl-iot-gate-optee_defconfig
+++ b/configs/imx8mm-cl-iot-gate-optee_defconfig
@@ -38,6 +38,7 @@ CONFIG_SYS_PBSIZE=2074
 CONFIG_BOARD_LATE_INIT=y
 CONFIG_SPL_BOARD_INIT=y
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_SYS_MALLOC=y
 CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
 CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000
diff --git a/configs/imx8mm-cl-iot-gate_defconfig b/configs/imx8mm-cl-iot-gate_defconfig
index 1aa42efe5ef..ea6a8789eea 100644
--- a/configs/imx8mm-cl-iot-gate_defconfig
+++ b/configs/imx8mm-cl-iot-gate_defconfig
@@ -40,6 +40,7 @@ CONFIG_SYS_PBSIZE=2074
 CONFIG_BOARD_LATE_INIT=y
 CONFIG_SPL_BOARD_INIT=y
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_SYS_MALLOC=y
 CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
 CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000
diff --git a/configs/imx8mm-icore-mx8mm-ctouch2_defconfig b/configs/imx8mm-icore-mx8mm-ctouch2_defconfig
index db44145f650..445145d6fe4 100644
--- a/configs/imx8mm-icore-mx8mm-ctouch2_defconfig
+++ b/configs/imx8mm-icore-mx8mm-ctouch2_defconfig
@@ -32,6 +32,7 @@ CONFIG_SYS_CBSIZE=2048
 CONFIG_SYS_PBSIZE=2074
 CONFIG_SPL_BOARD_INIT=y
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_SYS_MALLOC=y
 CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
 CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000
diff --git a/configs/imx8mm-icore-mx8mm-edimm2.2_defconfig b/configs/imx8mm-icore-mx8mm-edimm2.2_defconfig
index 94b4a9552cf..50f72dc516b 100644
--- a/configs/imx8mm-icore-mx8mm-edimm2.2_defconfig
+++ b/configs/imx8mm-icore-mx8mm-edimm2.2_defconfig
@@ -32,6 +32,7 @@ CONFIG_SYS_CBSIZE=2048
 CONFIG_SYS_PBSIZE=2074
 CONFIG_SPL_BOARD_INIT=y
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_SYS_MALLOC=y
 CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
 CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000
diff --git a/configs/imx8mm-mx8menlo_defconfig b/configs/imx8mm-mx8menlo_defconfig
index ae9595e82b4..8435bcc316a 100644
--- a/configs/imx8mm-mx8menlo_defconfig
+++ b/configs/imx8mm-mx8menlo_defconfig
@@ -48,6 +48,7 @@ CONFIG_ARCH_MISC_INIT=y
 CONFIG_BOARD_LATE_INIT=y
 CONFIG_SPL_BOARD_INIT=y
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_SYS_MALLOC=y
 CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
 CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000
@@ -102,6 +103,7 @@ CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_TFTP_BLOCKSIZE=4096
 CONFIG_SPL_DM=y
 CONFIG_BOOTCOUNT_LIMIT=y
+CONFIG_BOOTCOUNT_ALTBOOTCMD="mmc partconf 0 mmcpart ; if test ${mmcpart} -eq 1 ; then mmc partconf 0 1 2 0 ; else mmc partconf 0 1 1 0 ; fi ; boot"
 CONFIG_SYS_BOOTCOUNT_MAGIC=0xB0C40000
 CONFIG_SPL_CLK_COMPOSITE_CCF=y
 CONFIG_CLK_COMPOSITE_CCF=y
diff --git a/configs/imx8mm-phygate-tauri-l_defconfig b/configs/imx8mm-phygate-tauri-l_defconfig
index c7582843421..43c50e97726 100644
--- a/configs/imx8mm-phygate-tauri-l_defconfig
+++ b/configs/imx8mm-phygate-tauri-l_defconfig
@@ -34,6 +34,7 @@ CONFIG_SYS_CBSIZE=2048
 CONFIG_SYS_PBSIZE=2074
 CONFIG_BOARD_LATE_INIT=y
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_SYS_MALLOC=y
 CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
 CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000
diff --git a/configs/imx8mm_beacon_defconfig b/configs/imx8mm_beacon_defconfig
index 56e18893b77..e4eca19a10b 100644
--- a/configs/imx8mm_beacon_defconfig
+++ b/configs/imx8mm_beacon_defconfig
@@ -34,6 +34,7 @@ CONFIG_DEFAULT_FDT_FILE="imx8mm-beacon-kit.dtb"
 CONFIG_SYS_CBSIZE=2048
 CONFIG_SYS_PBSIZE=2074
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_SYS_MALLOC=y
 CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
 CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000
diff --git a/configs/imx8mm_beacon_fspi_defconfig b/configs/imx8mm_beacon_fspi_defconfig
index 2a8bd2df940..81510a10a1f 100644
--- a/configs/imx8mm_beacon_fspi_defconfig
+++ b/configs/imx8mm_beacon_fspi_defconfig
@@ -37,6 +37,7 @@ CONFIG_SPL_MAX_SIZE=0x25000
 CONFIG_SPL_PAD_TO=0x0
 CONFIG_SPL_BOARD_INIT=y
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_SYS_MALLOC=y
 CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
 CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000
diff --git a/configs/imx8mm_data_modul_edm_sbc_defconfig b/configs/imx8mm_data_modul_edm_sbc_defconfig
index 66cb1331ded..47f0d3cc050 100644
--- a/configs/imx8mm_data_modul_edm_sbc_defconfig
+++ b/configs/imx8mm_data_modul_edm_sbc_defconfig
@@ -30,6 +30,7 @@ CONFIG_SPL_DM_USB=y
 CONFIG_SPL_LEGACY_IMAGE_CRC_CHECK=y
 CONFIG_SPL_LEGACY_IMAGE_FORMAT=y
 CONFIG_SPL_RAM_DEVICE=y
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_STACK=0x920000
 CONFIG_SPL_SYS_MALLOC_SIZE=0x1000000
 CONFIG_SPL_TEXT_BASE=0x7E1000
diff --git a/configs/imx8mm_evk_defconfig b/configs/imx8mm_evk_defconfig
index 2048391439f..e8cd6a524fa 100644
--- a/configs/imx8mm_evk_defconfig
+++ b/configs/imx8mm_evk_defconfig
@@ -32,6 +32,7 @@ CONFIG_SYS_PBSIZE=2074
 CONFIG_BOARD_LATE_INIT=y
 CONFIG_SPL_BOARD_INIT=y
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_SYS_MALLOC=y
 CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
 CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000
diff --git a/configs/imx8mm_evk_fspi_defconfig b/configs/imx8mm_evk_fspi_defconfig
index 59ebdc5782f..902585b3b6d 100644
--- a/configs/imx8mm_evk_fspi_defconfig
+++ b/configs/imx8mm_evk_fspi_defconfig
@@ -36,6 +36,7 @@ CONFIG_BOARD_LATE_INIT=y
 CONFIG_SPL_MAX_SIZE=0x25000
 CONFIG_SPL_BOARD_INIT=y
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_SYS_MALLOC=y
 CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
 CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000
diff --git a/configs/imx8mm_phg_defconfig b/configs/imx8mm_phg_defconfig
index 384f2cc7b76..58dd8eb83f6 100644
--- a/configs/imx8mm_phg_defconfig
+++ b/configs/imx8mm_phg_defconfig
@@ -32,6 +32,7 @@ CONFIG_SYS_PBSIZE=2074
 CONFIG_BOARD_LATE_INIT=y
 CONFIG_SPL_BOARD_INIT=y
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_SYS_MALLOC=y
 CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
 CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000
diff --git a/configs/imx8mm_venice_defconfig b/configs/imx8mm_venice_defconfig
index 2e1c7a9f08a..0d3875d6a19 100644
--- a/configs/imx8mm_venice_defconfig
+++ b/configs/imx8mm_venice_defconfig
@@ -41,6 +41,7 @@ CONFIG_SYS_PBSIZE=2074
 CONFIG_BOARD_LATE_INIT=y
 CONFIG_SPL_BOARD_INIT=y
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_SYS_MALLOC=y
 CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
 CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000
diff --git a/configs/imx8mn_beacon_2g_defconfig b/configs/imx8mn_beacon_2g_defconfig
index b72fa93f90e..a5bc8aea027 100644
--- a/configs/imx8mn_beacon_2g_defconfig
+++ b/configs/imx8mn_beacon_2g_defconfig
@@ -44,6 +44,7 @@ CONFIG_SPL_MAX_SIZE=0x25000
 CONFIG_SPL_BOARD_INIT=y
 CONFIG_SPL_BOOTROM_SUPPORT=y
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_SYS_MALLOC=y
 CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
 CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000
diff --git a/configs/imx8mn_beacon_defconfig b/configs/imx8mn_beacon_defconfig
index 69af7cee092..c605567d9a6 100644
--- a/configs/imx8mn_beacon_defconfig
+++ b/configs/imx8mn_beacon_defconfig
@@ -43,6 +43,7 @@ CONFIG_SPL_MAX_SIZE=0x25000
 CONFIG_SPL_BOARD_INIT=y
 CONFIG_SPL_BOOTROM_SUPPORT=y
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_SYS_MALLOC=y
 CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
 CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000
diff --git a/configs/imx8mn_beacon_fspi_defconfig b/configs/imx8mn_beacon_fspi_defconfig
index b90cb9002bd..835654d2b63 100644
--- a/configs/imx8mn_beacon_fspi_defconfig
+++ b/configs/imx8mn_beacon_fspi_defconfig
@@ -43,6 +43,7 @@ CONFIG_SPL_MAX_SIZE=0x25000
 CONFIG_SPL_BOARD_INIT=y
 CONFIG_SPL_BOOTROM_SUPPORT=y
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_SYS_MALLOC=y
 CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
 CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000
diff --git a/configs/imx8mn_bsh_smm_s2_defconfig b/configs/imx8mn_bsh_smm_s2_defconfig
index f4a04744667..9ffcd3b221c 100644
--- a/configs/imx8mn_bsh_smm_s2_defconfig
+++ b/configs/imx8mn_bsh_smm_s2_defconfig
@@ -38,6 +38,7 @@ CONFIG_SPL_MAX_SIZE=0x25000
 CONFIG_SPL_BOARD_INIT=y
 CONFIG_SPL_BOOTROM_SUPPORT=y
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_SYS_MALLOC=y
 CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
 CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000
diff --git a/configs/imx8mn_bsh_smm_s2pro_defconfig b/configs/imx8mn_bsh_smm_s2pro_defconfig
index 9ca96a7f66f..d2010d13b8c 100644
--- a/configs/imx8mn_bsh_smm_s2pro_defconfig
+++ b/configs/imx8mn_bsh_smm_s2pro_defconfig
@@ -39,6 +39,7 @@ CONFIG_SPL_MAX_SIZE=0x25000
 CONFIG_SPL_BOARD_INIT=y
 CONFIG_SPL_BOOTROM_SUPPORT=y
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_SYS_MALLOC=y
 CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
 CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000
diff --git a/configs/imx8mn_ddr4_evk_defconfig b/configs/imx8mn_ddr4_evk_defconfig
index 3eb58d61c83..3cc7d2b6b13 100644
--- a/configs/imx8mn_ddr4_evk_defconfig
+++ b/configs/imx8mn_ddr4_evk_defconfig
@@ -37,6 +37,7 @@ CONFIG_SPL_MAX_SIZE=0x25000
 CONFIG_SPL_BOARD_INIT=y
 CONFIG_SPL_BOOTROM_SUPPORT=y
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_SYS_MALLOC=y
 CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
 CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000
diff --git a/configs/imx8mn_evk_defconfig b/configs/imx8mn_evk_defconfig
index 967eeea4051..a409cc0e49c 100644
--- a/configs/imx8mn_evk_defconfig
+++ b/configs/imx8mn_evk_defconfig
@@ -40,6 +40,7 @@ CONFIG_SPL_BOOTROM_SUPPORT=y
 CONFIG_SPL_LEGACY_IMAGE_FORMAT=y
 CONFIG_SPL_LEGACY_IMAGE_CRC_CHECK=y
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_SYS_MALLOC=y
 CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
 CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000
diff --git a/configs/imx8mn_var_som_defconfig b/configs/imx8mn_var_som_defconfig
index 9016c404017..5a9f31b1c2a 100644
--- a/configs/imx8mn_var_som_defconfig
+++ b/configs/imx8mn_var_som_defconfig
@@ -42,6 +42,7 @@ CONFIG_SPL_MAX_SIZE=0x25000
 CONFIG_SPL_BOARD_INIT=y
 CONFIG_SPL_BOOTROM_SUPPORT=y
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_SYS_MALLOC=y
 CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
 CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000
diff --git a/configs/imx8mn_venice_defconfig b/configs/imx8mn_venice_defconfig
index 44af3e61d5d..76353712936 100644
--- a/configs/imx8mn_venice_defconfig
+++ b/configs/imx8mn_venice_defconfig
@@ -42,6 +42,7 @@ CONFIG_SPL_MAX_SIZE=0x25000
 CONFIG_SPL_BOARD_INIT=y
 CONFIG_SPL_BOOTROM_SUPPORT=y
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_SYS_MALLOC=y
 CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
 CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000
diff --git a/configs/imx8mp-icore-mx8mp-edimm2.2_defconfig b/configs/imx8mp-icore-mx8mp-edimm2.2_defconfig
index d7d5df77c5a..b3c1b276ba2 100644
--- a/configs/imx8mp-icore-mx8mp-edimm2.2_defconfig
+++ b/configs/imx8mp-icore-mx8mp-edimm2.2_defconfig
@@ -40,6 +40,7 @@ CONFIG_SPL_BOARD_INIT=y
 CONFIG_SPL_BOOTROM_SUPPORT=y
 CONFIG_SPL_SYS_MALLOC_SIMPLE=y
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_SYS_MALLOC=y
 CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
 CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000
diff --git a/configs/imx8mp_beacon_defconfig b/configs/imx8mp_beacon_defconfig
index f39e4f5dd28..288626c1511 100644
--- a/configs/imx8mp_beacon_defconfig
+++ b/configs/imx8mp_beacon_defconfig
@@ -49,6 +49,7 @@ CONFIG_SPL_BOARD_INIT=y
 CONFIG_SPL_BOOTROM_SUPPORT=y
 CONFIG_SPL_SYS_MALLOC_SIMPLE=y
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_SYS_MALLOC=y
 CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
 CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000
@@ -86,6 +87,7 @@ CONFIG_USE_ETHPRIME=y
 CONFIG_ETHPRIME="eth1"
 CONFIG_SPL_DM=y
 CONFIG_CLK_COMPOSITE_CCF=y
+CONFIG_SPL_CLK_IMX8MP=y
 CONFIG_CLK_IMX8MP=y
 CONFIG_USB_FUNCTION_FASTBOOT=y
 CONFIG_FASTBOOT_BUF_ADDR=0x42800000
diff --git a/configs/imx8mp_data_modul_edm_sbc_defconfig b/configs/imx8mp_data_modul_edm_sbc_defconfig
index ea8109bf049..a30aaa57109 100644
--- a/configs/imx8mp_data_modul_edm_sbc_defconfig
+++ b/configs/imx8mp_data_modul_edm_sbc_defconfig
@@ -37,6 +37,7 @@ CONFIG_SPL_MMC_UHS_SUPPORT=y
 CONFIG_SPL_SPI=y
 CONFIG_SPL_SPI_FLASH_SUPPORT=y
 CONFIG_SPL_SPI_LOAD=y
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_STACK=0x96fc00
 CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
 CONFIG_SPL_TEXT_BASE=0x920000
diff --git a/configs/imx8mp_debix_model_a_defconfig b/configs/imx8mp_debix_model_a_defconfig
index 560ac12b10d..cf19ceae911 100644
--- a/configs/imx8mp_debix_model_a_defconfig
+++ b/configs/imx8mp_debix_model_a_defconfig
@@ -37,6 +37,7 @@ CONFIG_SPL_BOARD_INIT=y
 CONFIG_SPL_BOOTROM_SUPPORT=y
 CONFIG_SPL_SYS_MALLOC_SIMPLE=y
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
 CONFIG_SPL_I2C=y
diff --git a/configs/imx8mp_dhsom.config b/configs/imx8mp_dhsom.config
index 416143178c8..226c58c0277 100644
--- a/configs/imx8mp_dhsom.config
+++ b/configs/imx8mp_dhsom.config
@@ -41,6 +41,7 @@ CONFIG_SPL_LOAD_FIT_ADDRESS=0x44000000
 CONFIG_SPL_LOAD_FIT_APPLY_OVERLAY=y
 CONFIG_SPL_MAX_SIZE=0x26000
 CONFIG_SPL_OF_CONTROL=y
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_STACK=0x96fc00
 CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
 CONFIG_SPL_TEXT_BASE=0x920000
@@ -70,6 +71,7 @@ CONFIG_NXP_FSPI=y
 CONFIG_SF_DEFAULT_SPEED=50000000
 # CONFIG_SPI_FLASH_UNLOCK_ALL is not set
 
+CONFIG_BOOTCOUNT_ALTBOOTCMD="run bootcmd ; reset"
 CONFIG_BOOTCOUNT_LIMIT=y
 CONFIG_SYS_BOOTCOUNT_MAGIC=0xB0C40000
 
diff --git a/configs/imx8mp_evk_defconfig b/configs/imx8mp_evk_defconfig
index 2438ab5d26a..314ff8998b8 100644
--- a/configs/imx8mp_evk_defconfig
+++ b/configs/imx8mp_evk_defconfig
@@ -37,6 +37,7 @@ CONFIG_SPL_BOARD_INIT=y
 CONFIG_SPL_BOOTROM_SUPPORT=y
 CONFIG_SPL_SYS_MALLOC_SIMPLE=y
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_SYS_MALLOC=y
 CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
 CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000
diff --git a/configs/imx8mp_navqp_defconfig b/configs/imx8mp_navqp_defconfig
index 6c7eb330b70..d6e7edcfa28 100644
--- a/configs/imx8mp_navqp_defconfig
+++ b/configs/imx8mp_navqp_defconfig
@@ -36,6 +36,7 @@ CONFIG_SPL_BOARD_INIT=y
 CONFIG_SPL_BOOTROM_SUPPORT=y
 CONFIG_SPL_SYS_MALLOC_SIMPLE=y
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
 CONFIG_SPL_I2C=y
diff --git a/configs/imx8mp_rsb3720a1_4G_defconfig b/configs/imx8mp_rsb3720a1_4G_defconfig
index bfcda77b37e..ea091d32eee 100644
--- a/configs/imx8mp_rsb3720a1_4G_defconfig
+++ b/configs/imx8mp_rsb3720a1_4G_defconfig
@@ -54,6 +54,7 @@ CONFIG_SPL_BOARD_INIT=y
 CONFIG_SPL_BOOTROM_SUPPORT=y
 CONFIG_SPL_SYS_MALLOC_SIMPLE=y
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_SYS_MALLOC=y
 CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
 CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000
diff --git a/configs/imx8mp_rsb3720a1_6G_defconfig b/configs/imx8mp_rsb3720a1_6G_defconfig
index 69e67bcd498..03e558b9589 100644
--- a/configs/imx8mp_rsb3720a1_6G_defconfig
+++ b/configs/imx8mp_rsb3720a1_6G_defconfig
@@ -54,6 +54,7 @@ CONFIG_SPL_BOARD_INIT=y
 CONFIG_SPL_BOOTROM_SUPPORT=y
 CONFIG_SPL_SYS_MALLOC_SIMPLE=y
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_SYS_MALLOC=y
 CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
 CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000
diff --git a/configs/imx8mp_venice_defconfig b/configs/imx8mp_venice_defconfig
index 708412e3875..1b3849c3096 100644
--- a/configs/imx8mp_venice_defconfig
+++ b/configs/imx8mp_venice_defconfig
@@ -44,6 +44,7 @@ CONFIG_SPL_MAX_SIZE=0x26000
 CONFIG_SPL_BOARD_INIT=y
 CONFIG_SPL_BOOTROM_SUPPORT=y
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_SYS_MALLOC=y
 CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
 CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000
diff --git a/configs/imx8mq_cm_defconfig b/configs/imx8mq_cm_defconfig
index 7444b642aa5..1eff6bbc800 100644
--- a/configs/imx8mq_cm_defconfig
+++ b/configs/imx8mq_cm_defconfig
@@ -36,6 +36,7 @@ CONFIG_BOARD_LATE_INIT=y
 CONFIG_SPL_MAX_SIZE=0x1f000
 CONFIG_SPL_BOARD_INIT=y
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_SYS_MALLOC=y
 CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
 CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000
diff --git a/configs/imx8mq_evk_defconfig b/configs/imx8mq_evk_defconfig
index 0de98152b2b..a2a6991bee2 100644
--- a/configs/imx8mq_evk_defconfig
+++ b/configs/imx8mq_evk_defconfig
@@ -39,6 +39,7 @@ CONFIG_BOARD_LATE_INIT=y
 CONFIG_SPL_MAX_SIZE=0x1f000
 CONFIG_SPL_BOARD_INIT=y
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_SYS_MALLOC=y
 CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
 CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000
diff --git a/configs/imx8mq_phanbell_defconfig b/configs/imx8mq_phanbell_defconfig
index a3727390dc7..807c5602d66 100644
--- a/configs/imx8mq_phanbell_defconfig
+++ b/configs/imx8mq_phanbell_defconfig
@@ -39,6 +39,7 @@ CONFIG_BOARD_EARLY_INIT_F=y
 CONFIG_SPL_MAX_SIZE=0x2b000
 CONFIG_SPL_BOARD_INIT=y
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_SYS_MALLOC=y
 CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
 CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000
diff --git a/configs/imx8mq_reform2_defconfig b/configs/imx8mq_reform2_defconfig
index 1a6d6dcb8be..7d3c81c93d4 100644
--- a/configs/imx8mq_reform2_defconfig
+++ b/configs/imx8mq_reform2_defconfig
@@ -41,6 +41,7 @@ CONFIG_BOARD_LATE_INIT=y
 CONFIG_SPL_MAX_SIZE=0x1f000
 CONFIG_SPL_BOARD_INIT=y
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_SYS_MALLOC=y
 CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
 CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000
diff --git a/configs/imx8qm_dmsse20a1_defconfig b/configs/imx8qm_dmsse20a1_defconfig
index 9f2a6d78cee..dfee90bc6fb 100644
--- a/configs/imx8qm_dmsse20a1_defconfig
+++ b/configs/imx8qm_dmsse20a1_defconfig
@@ -43,6 +43,7 @@ CONFIG_SPL_MAX_SIZE=0x1f000
 CONFIG_SPL_BOARD_INIT=y
 CONFIG_SPL_SYS_MALLOC_SIMPLE=y
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_SYS_MALLOC=y
 CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
 CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x120000
diff --git a/configs/imx8qm_mek_defconfig b/configs/imx8qm_mek_defconfig
index 9bbbc6a4912..bfed8c2b01d 100644
--- a/configs/imx8qm_mek_defconfig
+++ b/configs/imx8qm_mek_defconfig
@@ -45,6 +45,7 @@ CONFIG_SPL_LOAD_IMX_CONTAINER=y
 CONFIG_IMX_CONTAINER_CFG="board/freescale/imx8qm_mek/uboot-container.cfg"
 CONFIG_SPL_SYS_MALLOC_SIMPLE=y
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_SYS_MALLOC=y
 CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
 CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x120000
diff --git a/configs/imx8qxp_mek_defconfig b/configs/imx8qxp_mek_defconfig
index dfb288b9861..2ca63942c04 100644
--- a/configs/imx8qxp_mek_defconfig
+++ b/configs/imx8qxp_mek_defconfig
@@ -46,6 +46,7 @@ CONFIG_SPL_LOAD_IMX_CONTAINER=y
 CONFIG_IMX_CONTAINER_CFG="board/freescale/imx8qxp_mek/uboot-container.cfg"
 CONFIG_SPL_SYS_MALLOC_SIMPLE=y
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_SYS_MALLOC=y
 CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
 CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x120000
diff --git a/configs/imx8ulp_evk_defconfig b/configs/imx8ulp_evk_defconfig
index cccc3153f50..e750b3d9ae0 100644
--- a/configs/imx8ulp_evk_defconfig
+++ b/configs/imx8ulp_evk_defconfig
@@ -40,6 +40,7 @@ CONFIG_SPL_BOOTROM_SUPPORT=y
 CONFIG_SPL_LOAD_IMX_CONTAINER=y
 CONFIG_IMX_CONTAINER_CFG="arch/arm/mach-imx/imx8ulp/container.cfg"
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_SYS_MALLOC=y
 CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
 CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x22040000
diff --git a/configs/imx91_11x11_evk_defconfig b/configs/imx91_11x11_evk_defconfig
index 1f711f2d051..0d8cdf19612 100644
--- a/configs/imx91_11x11_evk_defconfig
+++ b/configs/imx91_11x11_evk_defconfig
@@ -43,6 +43,7 @@ CONFIG_SPL_BOOTROM_SUPPORT=y
 CONFIG_SPL_LOAD_IMX_CONTAINER=y
 CONFIG_IMX_CONTAINER_CFG="arch/arm/mach-imx/imx9/container.cfg"
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_SYS_MALLOC=y
 CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
 CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x83200000
diff --git a/configs/imx91_11x11_evk_inline_ecc_defconfig b/configs/imx91_11x11_evk_inline_ecc_defconfig
index 14aee2c5b27..ddc59447b5f 100644
--- a/configs/imx91_11x11_evk_inline_ecc_defconfig
+++ b/configs/imx91_11x11_evk_inline_ecc_defconfig
@@ -43,6 +43,7 @@ CONFIG_SPL_BOOTROM_SUPPORT=y
 CONFIG_SPL_LOAD_IMX_CONTAINER=y
 CONFIG_IMX_CONTAINER_CFG="arch/arm/mach-imx/imx9/container.cfg"
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_SYS_MALLOC=y
 CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
 CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x83200000
diff --git a/configs/imx93-phycore_defconfig b/configs/imx93-phycore_defconfig
index cf9800118ac..af1fbc74698 100644
--- a/configs/imx93-phycore_defconfig
+++ b/configs/imx93-phycore_defconfig
@@ -46,6 +46,7 @@ CONFIG_SPL_BOOTROM_SUPPORT=y
 CONFIG_SPL_LOAD_IMX_CONTAINER=y
 CONFIG_IMX_CONTAINER_CFG="arch/arm/mach-imx/imx9/container.cfg"
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1040
 CONFIG_SPL_I2C=y
diff --git a/configs/imx93_11x11_evk_defconfig b/configs/imx93_11x11_evk_defconfig
index 43a67232d04..59c4da7fa2b 100644
--- a/configs/imx93_11x11_evk_defconfig
+++ b/configs/imx93_11x11_evk_defconfig
@@ -38,6 +38,7 @@ CONFIG_SPL_BOOTROM_SUPPORT=y
 CONFIG_SPL_LOAD_IMX_CONTAINER=y
 CONFIG_IMX_CONTAINER_CFG="arch/arm/mach-imx/imx9/container.cfg"
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_SYS_MALLOC=y
 CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
 CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x83200000
diff --git a/configs/imx93_9x9_qsb_defconfig b/configs/imx93_9x9_qsb_defconfig
index 8bd2ddda7da..6587f8d5daf 100644
--- a/configs/imx93_9x9_qsb_defconfig
+++ b/configs/imx93_9x9_qsb_defconfig
@@ -39,6 +39,7 @@ CONFIG_SPL_BOOTROM_SUPPORT=y
 CONFIG_SPL_LOAD_IMX_CONTAINER=y
 CONFIG_IMX_CONTAINER_CFG="arch/arm/mach-imx/imx9/container.cfg"
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_SYS_MALLOC=y
 CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
 CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x83200000
diff --git a/configs/imx93_9x9_qsb_inline_ecc_defconfig b/configs/imx93_9x9_qsb_inline_ecc_defconfig
index 3d07dfb0029..dafe4f65088 100644
--- a/configs/imx93_9x9_qsb_inline_ecc_defconfig
+++ b/configs/imx93_9x9_qsb_inline_ecc_defconfig
@@ -39,6 +39,7 @@ CONFIG_SPL_BOOTROM_SUPPORT=y
 CONFIG_SPL_LOAD_IMX_CONTAINER=y
 CONFIG_IMX_CONTAINER_CFG="arch/arm/mach-imx/imx9/container.cfg"
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_SYS_MALLOC=y
 CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
 CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x83200000
diff --git a/configs/imx93_var_som_defconfig b/configs/imx93_var_som_defconfig
index 96cd8622e90..23e1c316485 100644
--- a/configs/imx93_var_som_defconfig
+++ b/configs/imx93_var_som_defconfig
@@ -45,6 +45,7 @@ CONFIG_SPL_BOOTROM_SUPPORT=y
 CONFIG_SPL_LOAD_IMX_CONTAINER=y
 CONFIG_IMX_CONTAINER_CFG="arch/arm/mach-imx/imx9/container.cfg"
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1040
 CONFIG_SPL_I2C=y
diff --git a/configs/imxrt1050-evk_defconfig b/configs/imxrt1050-evk_defconfig
index b488ff1b7da..918713a1c7d 100644
--- a/configs/imxrt1050-evk_defconfig
+++ b/configs/imxrt1050-evk_defconfig
@@ -13,7 +13,7 @@ CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20020000
 CONFIG_ENV_OFFSET=0x80000
 CONFIG_DM_GPIO=y
-CONFIG_DEFAULT_DEVICE_TREE="imxrt1050-evk"
+CONFIG_DEFAULT_DEVICE_TREE="nxp/imx/imxrt1050-evk"
 CONFIG_TARGET_IMXRT1050_EVK=y
 CONFIG_SPL_MMC=y
 CONFIG_SPL_SERIAL=y
@@ -48,6 +48,7 @@ CONFIG_CMD_USB=y
 # CONFIG_EFI_PARTITION is not set
 CONFIG_OF_CONTROL=y
 CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_UPSTREAM=y
 CONFIG_ENV_IS_NOWHERE=y
 CONFIG_ENV_IS_IN_MMC=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
diff --git a/configs/imxrt1050-evk_fspi_defconfig b/configs/imxrt1050-evk_fspi_defconfig
index 5d58e723a70..86acd158391 100644
--- a/configs/imxrt1050-evk_fspi_defconfig
+++ b/configs/imxrt1050-evk_fspi_defconfig
@@ -15,7 +15,7 @@ CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20020000
 CONFIG_ENV_OFFSET=0x80000
 CONFIG_IMX_CONFIG="board/freescale/imxrt1050-evk/imximage-nor.cfg"
 CONFIG_DM_GPIO=y
-CONFIG_DEFAULT_DEVICE_TREE="imxrt1050-evk"
+CONFIG_DEFAULT_DEVICE_TREE="nxp/imx/imxrt1050-evk"
 CONFIG_TARGET_IMXRT1050_EVK=y
 CONFIG_SPL_MMC=y
 CONFIG_SPL_SERIAL=y
@@ -50,6 +50,7 @@ CONFIG_CMD_USB=y
 # CONFIG_EFI_PARTITION is not set
 CONFIG_OF_CONTROL=y
 CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_UPSTREAM=y
 CONFIG_ENV_IS_NOWHERE=y
 CONFIG_ENV_IS_IN_MMC=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
diff --git a/configs/iot2050_defconfig b/configs/iot2050_defconfig
index 2d5f18e5bd4..72d4b8e3695 100644
--- a/configs/iot2050_defconfig
+++ b/configs/iot2050_defconfig
@@ -70,7 +70,6 @@ CONFIG_CMD_GPT=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_PCI=y
-CONFIG_CMD_REMOTEPROC=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_WDT=y
 # CONFIG_CMD_SETEXPR is not set
@@ -131,7 +130,6 @@ CONFIG_SPL_PINCTRL=y
 CONFIG_PINCTRL_SINGLE=y
 CONFIG_POWER_DOMAIN=y
 CONFIG_TI_SCI_POWER_DOMAIN=y
-CONFIG_REMOTEPROC_TI_K3_R5F=y
 CONFIG_RESET_TI_SCI=y
 CONFIG_DM_SERIAL=y
 CONFIG_SOC_DEVICE=y
diff --git a/configs/j7200_evm_a72_defconfig b/configs/j7200_evm_a72_defconfig
index ac5b10ba149..3126ba3d771 100644
--- a/configs/j7200_evm_a72_defconfig
+++ b/configs/j7200_evm_a72_defconfig
@@ -6,7 +6,7 @@ CONFIG_TI_COMMON_CMD_OPTIONS=y
 CONFIG_SPL_GPIO=y
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SOC_K3_J721E=y
+CONFIG_SOC_K3_J7200=y
 CONFIG_TARGET_J7200_A72_EVM=y
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80480000
@@ -67,7 +67,6 @@ CONFIG_SPL_YMODEM_SUPPORT=y
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_MTD=y
 CONFIG_CMD_PCI=y
-CONFIG_CMD_REMOTEPROC=y
 CONFIG_CMD_UFS=y
 CONFIG_CMD_USB_MASS_STORAGE=y
 CONFIG_MTDIDS_DEFAULT="nor0=47040000.spi.0,nor0=47034000.hyperbus"
@@ -145,6 +144,7 @@ CONFIG_SPI_FLASH_S28HX_T=y
 CONFIG_SPI_FLASH_MTD=y
 CONFIG_MULTIPLEXER=y
 CONFIG_MUX_MMIO=y
+CONFIG_SPL_MUX_MMIO=y
 CONFIG_PHY_TI_DP83869=y
 CONFIG_PHY_FIXED=y
 CONFIG_TI_AM65_CPSW_NUSS=y
@@ -167,7 +167,6 @@ CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_DM_REGULATOR_GPIO=y
 CONFIG_RAM=y
 CONFIG_SPL_RAM=y
-CONFIG_REMOTEPROC_TI_K3_R5F=y
 CONFIG_RESET_TI_SCI=y
 CONFIG_SCSI=y
 CONFIG_DM_SERIAL=y
diff --git a/configs/j7200_evm_r5_defconfig b/configs/j7200_evm_r5_defconfig
index 265ae2e8e07..0ae07ddf7c8 100644
--- a/configs/j7200_evm_r5_defconfig
+++ b/configs/j7200_evm_r5_defconfig
@@ -5,7 +5,7 @@ CONFIG_SYS_MALLOC_F_LEN=0x70000
 CONFIG_SPL_GPIO=y
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SOC_K3_J721E=y
+CONFIG_SOC_K3_J7200=y
 CONFIG_K3_EARLY_CONS=y
 CONFIG_TARGET_J7200_R5_EVM=y
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
@@ -57,7 +57,6 @@ CONFIG_SPL_NOR_SUPPORT=y
 CONFIG_SPL_DM_RESET=y
 CONFIG_SPL_POWER_DOMAIN=y
 CONFIG_SPL_RAM_DEVICE=y
-CONFIG_SPL_REMOTEPROC=y
 # CONFIG_SPL_SPI_FLASH_TINY is not set
 CONFIG_SPL_SPI_FLASH_SFDP_SUPPORT=y
 CONFIG_SPL_SPI_LOAD=y
@@ -68,7 +67,6 @@ CONFIG_CMD_DFU=y
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_GPT=y
 CONFIG_CMD_MMC=y
-CONFIG_CMD_REMOTEPROC=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_TIME=y
 CONFIG_CMD_FAT=y
@@ -101,7 +99,9 @@ CONFIG_DM_MAILBOX=y
 CONFIG_K3_SEC_PROXY=y
 CONFIG_FS_LOADER=y
 CONFIG_SPL_FS_LOADER=y
+CONFIG_ESM_K3=y
 CONFIG_K3_AVS0=y
+CONFIG_ESM_PMIC=y
 CONFIG_SUPPORT_EMMC_BOOT=y
 CONFIG_SPL_MMC_HS400_SUPPORT=y
 CONFIG_MMC_SDHCI=y
@@ -138,7 +138,6 @@ CONFIG_DM_REGULATOR=y
 CONFIG_SPL_DM_REGULATOR=y
 CONFIG_DM_REGULATOR_TPS65941=y
 CONFIG_K3_SYSTEM_CONTROLLER=y
-CONFIG_REMOTEPROC_TI_K3_ARM64=y
 CONFIG_RESET_TI_SCI=y
 CONFIG_DM_SERIAL=y
 CONFIG_SOC_DEVICE=y
diff --git a/configs/j721e_beagleboneai64_a72_defconfig b/configs/j721e_beagleboneai64_a72_defconfig
index a5d95975fb4..fad01c27104 100644
--- a/configs/j721e_beagleboneai64_a72_defconfig
+++ b/configs/j721e_beagleboneai64_a72_defconfig
@@ -67,7 +67,6 @@ CONFIG_CMD_GPIO_READ=y
 CONFIG_CMD_GPT=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
-CONFIG_CMD_REMOTEPROC=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_USB_MASS_STORAGE=y
 CONFIG_CMD_EFIDEBUG=y
@@ -144,8 +143,6 @@ CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_DM_REGULATOR_GPIO=y
 CONFIG_RAM=y
 CONFIG_SPL_RAM=y
-CONFIG_REMOTEPROC_TI_K3_DSP=y
-CONFIG_REMOTEPROC_TI_K3_R5F=y
 CONFIG_RESET_TI_SCI=y
 CONFIG_DM_RTC=y
 CONFIG_RTC_EMULATION=y
diff --git a/configs/j721e_beagleboneai64_r5_defconfig b/configs/j721e_beagleboneai64_r5_defconfig
index 77e44963fd4..086ad99ff6d 100644
--- a/configs/j721e_beagleboneai64_r5_defconfig
+++ b/configs/j721e_beagleboneai64_r5_defconfig
@@ -52,13 +52,11 @@ CONFIG_SPL_DM_MAILBOX=y
 CONFIG_SPL_DM_RESET=y
 CONFIG_SPL_POWER_DOMAIN=y
 CONFIG_SPL_RAM_DEVICE=y
-CONFIG_SPL_REMOTEPROC=y
 CONFIG_SPL_YMODEM_SUPPORT=y
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_DFU=y
 CONFIG_CMD_GPT=y
 CONFIG_CMD_MMC=y
-CONFIG_CMD_REMOTEPROC=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_TIME=y
 CONFIG_CMD_FAT=y
@@ -111,7 +109,6 @@ CONFIG_DM_REGULATOR=y
 CONFIG_SPL_DM_REGULATOR=y
 CONFIG_DM_REGULATOR_TPS65941=y
 CONFIG_K3_SYSTEM_CONTROLLER=y
-CONFIG_REMOTEPROC_TI_K3_ARM64=y
 CONFIG_RESET_TI_SCI=y
 CONFIG_DM_SERIAL=y
 CONFIG_SOC_DEVICE=y
diff --git a/configs/j721e_evm_a72_defconfig b/configs/j721e_evm_a72_defconfig
index 1ddb1965d8b..6bc716650cf 100644
--- a/configs/j721e_evm_a72_defconfig
+++ b/configs/j721e_evm_a72_defconfig
@@ -68,7 +68,6 @@ CONFIG_CMD_NVEDIT_EFI=y
 CONFIG_CMD_DFU=y
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_MTD=y
-CONFIG_CMD_REMOTEPROC=y
 CONFIG_CMD_UFS=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_USB_MASS_STORAGE=y
@@ -152,6 +151,7 @@ CONFIG_SPI_FLASH_MT35XU=y
 CONFIG_SPI_FLASH_MTD=y
 CONFIG_MULTIPLEXER=y
 CONFIG_MUX_MMIO=y
+CONFIG_SPL_MUX_MMIO=y
 CONFIG_PHY_TI_DP83867=y
 CONFIG_PHY_FIXED=y
 CONFIG_TI_AM65_CPSW_NUSS=y
@@ -171,8 +171,6 @@ CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_DM_REGULATOR_GPIO=y
 CONFIG_RAM=y
 CONFIG_SPL_RAM=y
-CONFIG_REMOTEPROC_TI_K3_DSP=y
-CONFIG_REMOTEPROC_TI_K3_R5F=y
 CONFIG_RESET_TI_SCI=y
 CONFIG_DM_RTC=y
 CONFIG_RTC_EMULATION=y
diff --git a/configs/j721e_evm_r5_defconfig b/configs/j721e_evm_r5_defconfig
index c4e9f2d43b1..c8324d4c068 100644
--- a/configs/j721e_evm_r5_defconfig
+++ b/configs/j721e_evm_r5_defconfig
@@ -61,7 +61,6 @@ CONFIG_SPL_NOR_SUPPORT=y
 CONFIG_SPL_DM_RESET=y
 CONFIG_SPL_POWER_DOMAIN=y
 CONFIG_SPL_RAM_DEVICE=y
-CONFIG_SPL_REMOTEPROC=y
 # CONFIG_SPL_SPI_FLASH_TINY is not set
 CONFIG_SPL_SPI_FLASH_SFDP_SUPPORT=y
 CONFIG_SPL_SPI_LOAD=y
@@ -72,7 +71,6 @@ CONFIG_CMD_DFU=y
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_GPT=y
 CONFIG_CMD_MMC=y
-CONFIG_CMD_REMOTEPROC=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_TIME=y
 CONFIG_CMD_FAT=y
@@ -148,7 +146,6 @@ CONFIG_DM_REGULATOR=y
 CONFIG_SPL_DM_REGULATOR=y
 CONFIG_DM_REGULATOR_TPS65941=y
 CONFIG_K3_SYSTEM_CONTROLLER=y
-CONFIG_REMOTEPROC_TI_K3_ARM64=y
 CONFIG_RESET_TI_SCI=y
 CONFIG_DM_SERIAL=y
 CONFIG_SOC_DEVICE=y
diff --git a/configs/j721s2_evm_a72_defconfig b/configs/j721s2_evm_a72_defconfig
index ab943ebfab2..5e84abf8f21 100644
--- a/configs/j721s2_evm_a72_defconfig
+++ b/configs/j721s2_evm_a72_defconfig
@@ -64,7 +64,6 @@ CONFIG_SPL_THERMAL=y
 CONFIG_SPL_YMODEM_SUPPORT=y
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_MTD=y
-CONFIG_CMD_REMOTEPROC=y
 CONFIG_CMD_UFS=y
 CONFIG_CMD_USB_MASS_STORAGE=y
 CONFIG_MTDIDS_DEFAULT="nor0=47040000.spi.0,nor0=47034000.hyperbus"
@@ -161,8 +160,6 @@ CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_DM_REGULATOR_GPIO=y
 CONFIG_RAM=y
 CONFIG_SPL_RAM=y
-CONFIG_REMOTEPROC_TI_K3_DSP=y
-CONFIG_REMOTEPROC_TI_K3_R5F=y
 CONFIG_RESET_TI_SCI=y
 CONFIG_SCSI=y
 CONFIG_DM_SERIAL=y
diff --git a/configs/j721s2_evm_r5_defconfig b/configs/j721s2_evm_r5_defconfig
index 7ec9af8bc48..6ea1d712be1 100644
--- a/configs/j721s2_evm_r5_defconfig
+++ b/configs/j721s2_evm_r5_defconfig
@@ -62,7 +62,6 @@ CONFIG_SPL_NOR_SUPPORT=y
 CONFIG_SPL_DM_RESET=y
 CONFIG_SPL_POWER_DOMAIN=y
 CONFIG_SPL_RAM_DEVICE=y
-CONFIG_SPL_REMOTEPROC=y
 # CONFIG_SPL_SPI_FLASH_TINY is not set
 CONFIG_SPL_SPI_FLASH_SFDP_SUPPORT=y
 CONFIG_SPL_SPI_LOAD=y
@@ -74,7 +73,6 @@ CONFIG_CMD_DFU=y
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_GPT=y
 CONFIG_CMD_MMC=y
-CONFIG_CMD_REMOTEPROC=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_TIME=y
 CONFIG_CMD_FAT=y
@@ -148,7 +146,6 @@ CONFIG_DM_REGULATOR=y
 CONFIG_SPL_DM_REGULATOR=y
 CONFIG_DM_REGULATOR_TPS65941=y
 CONFIG_K3_SYSTEM_CONTROLLER=y
-CONFIG_REMOTEPROC_TI_K3_ARM64=y
 CONFIG_RESET_TI_SCI=y
 CONFIG_DM_SERIAL=y
 CONFIG_SOC_DEVICE=y
diff --git a/configs/j722s_evm_a53_defconfig b/configs/j722s_evm_a53_defconfig
index 667d633c899..5d2bb52b440 100644
--- a/configs/j722s_evm_a53_defconfig
+++ b/configs/j722s_evm_a53_defconfig
@@ -55,7 +55,6 @@ CONFIG_SPL_THERMAL=y
 CONFIG_SPL_YMODEM_SUPPORT=y
 CONFIG_CMD_CLK=y
 CONFIG_CMD_MTD=y
-CONFIG_CMD_REMOTEPROC=y
 CONFIG_CMD_USB_MASS_STORAGE=y
 CONFIG_CMD_MTDPARTS=y
 CONFIG_CMD_UBI=y
@@ -131,9 +130,6 @@ CONFIG_SPL_DM_REGULATOR_FIXED=y
 CONFIG_DM_REGULATOR_GPIO=y
 CONFIG_SPL_DM_REGULATOR_GPIO=y
 CONFIG_K3_SYSTEM_CONTROLLER=y
-CONFIG_REMOTEPROC_TI_K3_ARM64=y
-CONFIG_REMOTEPROC_TI_K3_DSP=y
-CONFIG_REMOTEPROC_TI_K3_R5F=y
 CONFIG_RESET_TI_SCI=y
 CONFIG_DM_SERIAL=y
 CONFIG_SOC_DEVICE=y
@@ -154,6 +150,8 @@ CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_DWC3=y
 CONFIG_USB_DWC3_GENERIC=y
 CONFIG_SPL_USB_DWC3_GENERIC=y
+CONFIG_SPL_USB_DWC3_AM62=y
+CONFIG_USB_DWC3_AM62=y
 CONFIG_SPL_USB_STORAGE=y
 CONFIG_USB_GADGET=y
 CONFIG_SPL_USB_GADGET=y
diff --git a/configs/j722s_evm_r5_defconfig b/configs/j722s_evm_r5_defconfig
index a78a66d33a7..d96392db479 100644
--- a/configs/j722s_evm_r5_defconfig
+++ b/configs/j722s_evm_r5_defconfig
@@ -49,7 +49,6 @@ CONFIG_SPL_DM_SPI_FLASH=y
 CONFIG_SPL_DM_RESET=y
 CONFIG_SPL_POWER_DOMAIN=y
 CONFIG_SPL_RAM_DEVICE=y
-CONFIG_SPL_REMOTEPROC=y
 # CONFIG_SPL_SPI_FLASH_TINY is not set
 CONFIG_SPL_SPI_FLASH_SFDP_SUPPORT=y
 CONFIG_SPL_SPI_LOAD=y
@@ -61,7 +60,6 @@ CONFIG_CMD_ASKENV=y
 CONFIG_CMD_DFU=y
 CONFIG_CMD_GPT=y
 CONFIG_CMD_MMC=y
-CONFIG_CMD_REMOTEPROC=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_TIME=y
 CONFIG_CMD_FAT=y
@@ -113,7 +111,6 @@ CONFIG_PINCTRL_SINGLE=y
 CONFIG_POWER_DOMAIN=y
 CONFIG_TI_POWER_DOMAIN=y
 CONFIG_K3_SYSTEM_CONTROLLER=y
-CONFIG_REMOTEPROC_TI_K3_ARM64=y
 CONFIG_RESET_TI_SCI=y
 CONFIG_SPECIFY_CONSOLE_INDEX=y
 CONFIG_DM_SERIAL=y
@@ -127,4 +124,7 @@ CONFIG_TIMER=y
 CONFIG_SPL_TIMER=y
 CONFIG_OMAP_TIMER=y
 CONFIG_LIB_RATIONAL=y
+CONFIG_ESM_K3=y
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL_MISC=y
 CONFIG_SPL_LIB_RATIONAL=y
diff --git a/configs/j742s2_evm_a72_defconfig b/configs/j742s2_evm_a72_defconfig
new file mode 100644
index 00000000000..e534ce4c2e3
--- /dev/null
+++ b/configs/j742s2_evm_a72_defconfig
@@ -0,0 +1,9 @@
+#include <configs/j784s4_evm_a72_defconfig>
+
+CONFIG_ARM=y
+CONFIG_ARCH_K3=y
+CONFIG_SOC_K3_J784S4=y
+CONFIG_TARGET_J742S2_A72_EVM=y
+
+CONFIG_DEFAULT_DEVICE_TREE="ti/k3-j742s2-evm"
+CONFIG_SPL_OF_LIST="ti/k3-j742s2-evm"
diff --git a/configs/j742s2_evm_r5_defconfig b/configs/j742s2_evm_r5_defconfig
new file mode 100644
index 00000000000..2be6318df76
--- /dev/null
+++ b/configs/j742s2_evm_r5_defconfig
@@ -0,0 +1,9 @@
+#include <configs/j784s4_evm_r5_defconfig>
+
+CONFIG_ARM=y
+CONFIG_ARCH_K3=y
+CONFIG_SOC_K3_J784S4=y
+CONFIG_TARGET_J742S2_R5_EVM=y
+
+CONFIG_DEFAULT_DEVICE_TREE="k3-j742s2-r5-evm"
+CONFIG_SPL_OF_LIST="k3-j742s2-r5-evm"
diff --git a/configs/j784s4_evm_a72_defconfig b/configs/j784s4_evm_a72_defconfig
index f058e3b1c00..1280194c7a7 100644
--- a/configs/j784s4_evm_a72_defconfig
+++ b/configs/j784s4_evm_a72_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_ARCH_K3=y
 CONFIG_SYS_MALLOC_LEN=0x2000000
 CONFIG_SYS_MALLOC_F_LEN=0x8000
+CONFIG_TI_COMMON_CMD_OPTIONS=y
 CONFIG_SPL_GPIO=y
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
@@ -14,13 +15,13 @@ CONFIG_ENV_SIZE=0x20000
 CONFIG_DM_GPIO=y
 CONFIG_SPL_DM_SPI=y
 CONFIG_DEFAULT_DEVICE_TREE="ti/k3-j784s4-evm"
-CONFIG_SPL_TEXT_BASE=0x80080000
 CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_DM_RESET=y
 CONFIG_SPL_MMC=y
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
 CONFIG_SPL_STACK_R_ADDR=0x82000000
+CONFIG_SPL_TEXT_BASE=0x80080000
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
 CONFIG_SPL_BSS_START_ADDR=0x80a00000
 CONFIG_SPL_BSS_MAX_SIZE=0x80000
@@ -29,6 +30,7 @@ CONFIG_SPL_FS_FAT=y
 CONFIG_SPL_LIBDISK_SUPPORT=y
 CONFIG_SPL_SPI_FLASH_SUPPORT=y
 CONFIG_SPL_SPI=y
+CONFIG_EFI_SET_TIME=y
 CONFIG_SPL_LOAD_FIT=y
 CONFIG_SPL_LOAD_FIT_ADDRESS=0x81000000
 CONFIG_BOOTSTD_FULL=y
@@ -38,10 +40,8 @@ CONFIG_SPL_MAX_SIZE=0xc0000
 CONFIG_SPL_BOARD_INIT=y
 CONFIG_SPL_SYS_MALLOC_SIMPLE=y
 CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
-CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1400
 CONFIG_SPL_DMA=y
-CONFIG_SPL_DM_DEVICE_REMOVE=y
 CONFIG_SPL_ENV_SUPPORT=y
 CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot.img"
 CONFIG_SPL_I2C=y
@@ -49,7 +49,6 @@ CONFIG_SPL_DM_MAILBOX=y
 CONFIG_SPL_DM_SPI_FLASH=y
 CONFIG_SPL_DM_RESET=y
 CONFIG_SPL_POWER_DOMAIN=y
-CONFIG_SPL_RAM_SUPPORT=y
 CONFIG_SPL_RAM_DEVICE=y
 # CONFIG_SPL_SPI_FLASH_TINY is not set
 CONFIG_SPL_SPI_FLASH_SFDP_SUPPORT=y
@@ -58,11 +57,9 @@ CONFIG_SYS_SPI_U_BOOT_OFFS=0x280000
 CONFIG_SPL_THERMAL=y
 CONFIG_SPL_YMODEM_SUPPORT=y
 CONFIG_CMD_BOOTEFI_SELFTEST=y
-CONFIG_CMD_ASKENV=y
 CONFIG_CMD_NVEDIT_EFI=y
 CONFIG_CMD_MTD=y
-CONFIG_CMD_REMOTEPROC=y
-CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
 CONFIG_CMD_EFIDEBUG=y
 CONFIG_OF_CONTROL=y
 CONFIG_SPL_OF_CONTROL=y
@@ -73,6 +70,7 @@ CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SPL_DM=y
+CONFIG_SPL_DM_DEVICE_REMOVE=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_REGMAP=y
 CONFIG_SPL_REGMAP=y
@@ -82,6 +80,8 @@ CONFIG_CLK=y
 CONFIG_SPL_CLK=y
 CONFIG_CLK_CCF=y
 CONFIG_CLK_TI_SCI=y
+CONFIG_DFU_MMC=y
+CONFIG_DFU_RAM=y
 CONFIG_DFU_SF=y
 CONFIG_SYS_DFU_DATA_BUF_SIZE=0x40000
 CONFIG_SYS_DFU_MAX_FILE_SIZE=0x800000
@@ -140,8 +140,6 @@ CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_DM_REGULATOR_GPIO=y
 CONFIG_RAM=y
 CONFIG_SPL_RAM=y
-CONFIG_REMOTEPROC_TI_K3_DSP=y
-CONFIG_REMOTEPROC_TI_K3_R5F=y
 CONFIG_RESET_TI_SCI=y
 CONFIG_DM_RTC=y
 CONFIG_RTC_EMULATION=y
@@ -157,7 +155,24 @@ CONFIG_SYSRESET=y
 CONFIG_SPL_SYSRESET=y
 CONFIG_SYSRESET_TI_SCI=y
 CONFIG_DM_THERMAL=y
-CONFIG_EFI_SET_TIME=y
-CONFIG_TI_COMMON_CMD_OPTIONS=y
+CONFIG_USB=y
+CONFIG_DM_USB_GADGET=y
+CONFIG_SPL_DM_USB_GADGET=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_CDNS3=y
+CONFIG_USB_CDNS3_GADGET=y
+CONFIG_USB_CDNS3_HOST=y
+CONFIG_SPL_USB_CDNS3_GADGET=y
+CONFIG_USB_GADGET=y
+CONFIG_SPL_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
+CONFIG_USB_GADGET_VENDOR_NUM=0x0451
+CONFIG_USB_GADGET_PRODUCT_NUM=0x6168
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_SPL_DFU=y
+CONFIG_CMD_UFS=y
+CONFIG_UFS=y
+CONFIG_CADENCE_UFS=y
+CONFIG_TI_J721E_UFS=y
 
 #include <configs/k3_efi_capsule.config>
diff --git a/configs/j784s4_evm_r5_defconfig b/configs/j784s4_evm_r5_defconfig
index b991ffb73be..5a5b0458b9b 100644
--- a/configs/j784s4_evm_r5_defconfig
+++ b/configs/j784s4_evm_r5_defconfig
@@ -55,7 +55,6 @@ CONFIG_SPL_DM_SPI_FLASH=y
 CONFIG_SPL_DM_RESET=y
 CONFIG_SPL_POWER_DOMAIN=y
 CONFIG_SPL_RAM_DEVICE=y
-CONFIG_SPL_REMOTEPROC=y
 # CONFIG_SPL_SPI_FLASH_TINY is not set
 CONFIG_SPL_SPI_FLASH_SFDP_SUPPORT=y
 CONFIG_SPL_SPI_LOAD=y
@@ -63,6 +62,7 @@ CONFIG_SYS_SPI_U_BOOT_OFFS=0x80000
 CONFIG_SPL_THERMAL=y
 CONFIG_SPL_YMODEM_SUPPORT=y
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_DFU=y
 CONFIG_CMD_GPT=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_TIME=y
@@ -85,6 +85,7 @@ CONFIG_SPL_CLK=y
 CONFIG_SPL_CLK_CCF=y
 CONFIG_SPL_CLK_K3_PLL=y
 CONFIG_SPL_CLK_K3=y
+CONFIG_SYS_DFU_DATA_BUF_SIZE=0x40000
 CONFIG_DMA_CHANNELS=y
 CONFIG_TI_K3_NAVSS_UDMA=y
 CONFIG_TI_SCI_PROTOCOL=y
@@ -128,7 +129,6 @@ CONFIG_DM_REGULATOR=y
 CONFIG_SPL_DM_REGULATOR=y
 CONFIG_SPL_DM_REGULATOR_TPS6287X=y
 CONFIG_K3_SYSTEM_CONTROLLER=y
-CONFIG_REMOTEPROC_TI_K3_ARM64=y
 CONFIG_RESET_TI_SCI=y
 CONFIG_DM_SERIAL=y
 CONFIG_SOC_DEVICE=y
@@ -144,6 +144,19 @@ CONFIG_DM_THERMAL=y
 CONFIG_TIMER=y
 CONFIG_SPL_TIMER=y
 CONFIG_OMAP_TIMER=y
+CONFIG_USB=y
+CONFIG_DM_USB_GADGET=y
+CONFIG_SPL_DM_USB_GADGET=y
+CONFIG_USB_CDNS3=y
+CONFIG_USB_CDNS3_GADGET=y
+CONFIG_SPL_USB_CDNS3_GADGET=y
+CONFIG_USB_GADGET=y
+CONFIG_SPL_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
+CONFIG_USB_GADGET_VENDOR_NUM=0x0451
+CONFIG_USB_GADGET_PRODUCT_NUM=0x6168
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_SPL_DFU=y
 CONFIG_FS_EXT4=y
 CONFIG_FS_FAT_MAX_CLUSTSIZE=16384
 CONFIG_PANIC_HANG=y
diff --git a/configs/jetson-tk1_defconfig b/configs/jetson-tk1_defconfig
index b92590eb5fd..3b74845046c 100644
--- a/configs/jetson-tk1_defconfig
+++ b/configs/jetson-tk1_defconfig
@@ -24,6 +24,7 @@ CONFIG_SYS_STDIO_DEREGISTER=y
 CONFIG_SPL_FOOTPRINT_LIMIT=y
 CONFIG_SPL_MAX_FOOTPRINT=0x8000
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_SYS_MALLOC=y
 CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
 CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x80090000
diff --git a/configs/k2e_evm_defconfig b/configs/k2e_evm_defconfig
index c2073096b6e..ab28e15a3ff 100644
--- a/configs/k2e_evm_defconfig
+++ b/configs/k2e_evm_defconfig
@@ -36,6 +36,7 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y
 CONFIG_BOARD_EARLY_INIT_F=y
 CONFIG_SPL_MAX_SIZE=0xfff8
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_SYS_MALLOC=y
 CONFIG_SPL_SYS_MALLOC_SIZE=0x8000
 CONFIG_SPL_I2C=y
diff --git a/configs/k2g_evm_defconfig b/configs/k2g_evm_defconfig
index c93e82a7c59..9b8fcc591ae 100644
--- a/configs/k2g_evm_defconfig
+++ b/configs/k2g_evm_defconfig
@@ -36,6 +36,7 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y
 CONFIG_BOARD_EARLY_INIT_F=y
 CONFIG_SPL_MAX_SIZE=0xfff8
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_SYS_MALLOC=y
 CONFIG_SPL_SYS_MALLOC_SIZE=0x8000
 CONFIG_SPL_I2C=y
diff --git a/configs/k2hk_evm_defconfig b/configs/k2hk_evm_defconfig
index 7ae7a3ba83c..31ffb762c26 100644
--- a/configs/k2hk_evm_defconfig
+++ b/configs/k2hk_evm_defconfig
@@ -36,6 +36,7 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y
 CONFIG_BOARD_EARLY_INIT_F=y
 CONFIG_SPL_MAX_SIZE=0xfff8
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_SYS_MALLOC=y
 CONFIG_SPL_SYS_MALLOC_SIZE=0x8000
 CONFIG_SPL_I2C=y
diff --git a/configs/k2l_evm_defconfig b/configs/k2l_evm_defconfig
index 9f08e9d7995..8f5c4855dd3 100644
--- a/configs/k2l_evm_defconfig
+++ b/configs/k2l_evm_defconfig
@@ -36,6 +36,7 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y
 CONFIG_BOARD_EARLY_INIT_F=y
 CONFIG_SPL_MAX_SIZE=0xfff8
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_SYS_MALLOC=y
 CONFIG_SPL_SYS_MALLOC_SIZE=0x8000
 CONFIG_SPL_I2C=y
diff --git a/configs/kmcent2_defconfig b/configs/kmcent2_defconfig
index 4e37df2e614..76e98c9b2a4 100644
--- a/configs/kmcent2_defconfig
+++ b/configs/kmcent2_defconfig
@@ -60,6 +60,7 @@ CONFIG_ENV_ADDR_REDUND=0xebf00000
 CONFIG_USE_ETHPRIME=y
 CONFIG_ETHPRIME="fm1-mac5"
 CONFIG_BOOTCOUNT_LIMIT=y
+CONFIG_BOOTCOUNT_ALTBOOTCMD="run bootcmd"
 CONFIG_SYS_BOOTCOUNT_BE=y
 CONFIG_FSL_CAAM=y
 CONFIG_DDR_CLK_FREQ=66666666
diff --git a/configs/kmcoge5ne_defconfig b/configs/kmcoge5ne_defconfig
index 6b2fc2ec6e7..cf50e2d27d8 100644
--- a/configs/kmcoge5ne_defconfig
+++ b/configs/kmcoge5ne_defconfig
@@ -166,6 +166,7 @@ CONFIG_VERSION_VARIABLE=y
 CONFIG_BOOTCOUNT_LIMIT=y
 CONFIG_DM_BOOTCOUNT=y
 CONFIG_BOOTCOUNT_MEM=y
+CONFIG_BOOTCOUNT_ALTBOOTCMD="run bootcmd"
 CONFIG_SYS_BOOTCOUNT_BE=y
 CONFIG_SYS_BR0_PRELIM_BOOL=y
 CONFIG_SYS_BR0_PRELIM=0xF0001001
diff --git a/configs/kmeter1_defconfig b/configs/kmeter1_defconfig
index 55e87b0215a..7638fc2f5cf 100644
--- a/configs/kmeter1_defconfig
+++ b/configs/kmeter1_defconfig
@@ -145,6 +145,7 @@ CONFIG_VERSION_VARIABLE=y
 CONFIG_BOOTCOUNT_LIMIT=y
 CONFIG_DM_BOOTCOUNT=y
 CONFIG_BOOTCOUNT_MEM=y
+CONFIG_BOOTCOUNT_ALTBOOTCMD="run bootcmd"
 CONFIG_SYS_BOOTCOUNT_BE=y
 CONFIG_SYS_BR0_PRELIM_BOOL=y
 CONFIG_SYS_BR0_PRELIM=0xF0001001
diff --git a/configs/kmopti2_defconfig b/configs/kmopti2_defconfig
index df419b01c68..1c750455fc6 100644
--- a/configs/kmopti2_defconfig
+++ b/configs/kmopti2_defconfig
@@ -152,6 +152,7 @@ CONFIG_VERSION_VARIABLE=y
 CONFIG_BOOTCOUNT_LIMIT=y
 CONFIG_DM_BOOTCOUNT=y
 CONFIG_BOOTCOUNT_MEM=y
+CONFIG_BOOTCOUNT_ALTBOOTCMD="run bootcmd"
 CONFIG_SYS_BR0_PRELIM_BOOL=y
 CONFIG_SYS_BR0_PRELIM=0xF0001001
 CONFIG_SYS_OR0_PRELIM=0xF0000E55
diff --git a/configs/kmsupx5_defconfig b/configs/kmsupx5_defconfig
index 1436860f1cc..5dd98175cd3 100644
--- a/configs/kmsupx5_defconfig
+++ b/configs/kmsupx5_defconfig
@@ -137,6 +137,7 @@ CONFIG_VERSION_VARIABLE=y
 CONFIG_BOOTCOUNT_LIMIT=y
 CONFIG_DM_BOOTCOUNT=y
 CONFIG_BOOTCOUNT_MEM=y
+CONFIG_BOOTCOUNT_ALTBOOTCMD="run bootcmd"
 CONFIG_SYS_BOOTCOUNT_BE=y
 CONFIG_SYS_BR0_PRELIM_BOOL=y
 CONFIG_SYS_BR0_PRELIM=0xF0001001
diff --git a/configs/kmtepr2_defconfig b/configs/kmtepr2_defconfig
index cce7a044aee..2b240b3380d 100644
--- a/configs/kmtepr2_defconfig
+++ b/configs/kmtepr2_defconfig
@@ -151,6 +151,7 @@ CONFIG_VERSION_VARIABLE=y
 CONFIG_BOOTCOUNT_LIMIT=y
 CONFIG_DM_BOOTCOUNT=y
 CONFIG_BOOTCOUNT_MEM=y
+CONFIG_BOOTCOUNT_ALTBOOTCMD="run bootcmd"
 CONFIG_SYS_BR0_PRELIM_BOOL=y
 CONFIG_SYS_BR0_PRELIM=0xF0001001
 CONFIG_SYS_OR0_PRELIM=0xF0000E55
diff --git a/configs/koelsch_defconfig b/configs/koelsch_defconfig
index eeb97474b2a..209a71c9c4c 100644
--- a/configs/koelsch_defconfig
+++ b/configs/koelsch_defconfig
@@ -14,6 +14,7 @@ CONFIG_ARCH_RENESAS_BOARD_STRING="Koelsch"
 CONFIG_R8A7791=y
 CONFIG_TARGET_KOELSCH=y
 CONFIG_SPL_SERIAL=y
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_STACK=0xe6340000
 CONFIG_SPL_SYS_MALLOC_F_LEN=0x2000
 CONFIG_SPL=y
diff --git a/configs/kontron-sl-mx8mm_defconfig b/configs/kontron-sl-mx8mm_defconfig
index f2d5bc1e7ab..54b5510085e 100644
--- a/configs/kontron-sl-mx8mm_defconfig
+++ b/configs/kontron-sl-mx8mm_defconfig
@@ -44,6 +44,7 @@ CONFIG_BOARD_TYPES=y
 CONFIG_BOARD_LATE_INIT=y
 CONFIG_SPL_BOARD_INIT=y
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_SYS_MALLOC=y
 CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
 CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000
diff --git a/configs/kontron_pitx_imx8m_defconfig b/configs/kontron_pitx_imx8m_defconfig
index 6e21870f006..8352176df61 100644
--- a/configs/kontron_pitx_imx8m_defconfig
+++ b/configs/kontron_pitx_imx8m_defconfig
@@ -43,6 +43,7 @@ CONFIG_BOARD_LATE_INIT=y
 CONFIG_MISC_INIT_R=y
 CONFIG_SPL_MAX_SIZE=0x1f000
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_SYS_MALLOC=y
 CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
 CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000
diff --git a/configs/kontron_sl28_defconfig b/configs/kontron_sl28_defconfig
index 1f684093252..c5f145aadc1 100644
--- a/configs/kontron_sl28_defconfig
+++ b/configs/kontron_sl28_defconfig
@@ -53,6 +53,7 @@ CONFIG_PCI_INIT_R=y
 CONFIG_SPL_MAX_SIZE=0x20000
 CONFIG_SPL_BOARD_INIT=y
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_SYS_MALLOC=y
 CONFIG_SPL_SYS_MALLOC_SIZE=0x200000
 CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
diff --git a/configs/kylin-rk3036_defconfig b/configs/kylin-rk3036_defconfig
index bc60bc57075..df5b9b949b0 100644
--- a/configs/kylin-rk3036_defconfig
+++ b/configs/kylin-rk3036_defconfig
@@ -31,6 +31,7 @@ CONFIG_DISPLAY_BOARDINFO_LATE=y
 # CONFIG_SPL_FRAMEWORK is not set
 CONFIG_SPL_PAD_TO=0x7f8000
 CONFIG_SPL_NO_BSS_LIMIT=y
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_CMD_GPT=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
diff --git a/configs/lager_defconfig b/configs/lager_defconfig
index b5682526c8c..b57f1ee1978 100644
--- a/configs/lager_defconfig
+++ b/configs/lager_defconfig
@@ -14,6 +14,7 @@ CONFIG_ARCH_RENESAS_BOARD_STRING="Lager"
 CONFIG_R8A7790=y
 CONFIG_TARGET_LAGER=y
 CONFIG_SPL_SERIAL=y
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_STACK=0xe6340000
 CONFIG_SPL_SYS_MALLOC_F_LEN=0x2000
 CONFIG_SPL=y
diff --git a/configs/librem5_defconfig b/configs/librem5_defconfig
index f81e828e4de..05bd08047ee 100644
--- a/configs/librem5_defconfig
+++ b/configs/librem5_defconfig
@@ -42,6 +42,7 @@ CONFIG_BOARD_LATE_INIT=y
 CONFIG_SPL_MAX_SIZE=0x25000
 CONFIG_SPL_BOARD_INIT=y
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_SYS_MALLOC=y
 CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
 CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000
diff --git a/configs/ls1021aiot_sdcard_defconfig b/configs/ls1021aiot_sdcard_defconfig
index f195d077687..c2763b4048a 100644
--- a/configs/ls1021aiot_sdcard_defconfig
+++ b/configs/ls1021aiot_sdcard_defconfig
@@ -46,6 +46,7 @@ CONFIG_SPL_MAX_SIZE=0x1a000
 CONFIG_SPL_PAD_TO=0x1c000
 CONFIG_SPL_FSL_PBL=y
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_SYS_MALLOC=y
 CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
 CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x82080000
diff --git a/configs/ls1021aqds_nand_defconfig b/configs/ls1021aqds_nand_defconfig
index 97d01225389..f56395a5451 100644
--- a/configs/ls1021aqds_nand_defconfig
+++ b/configs/ls1021aqds_nand_defconfig
@@ -57,6 +57,7 @@ CONFIG_SPL_MAX_SIZE=0x1a000
 CONFIG_SPL_PAD_TO=0x1c000
 CONFIG_SPL_FSL_PBL=y
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_SYS_MALLOC=y
 CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
 CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x80200000
diff --git a/configs/ls1021aqds_sdcard_ifc_defconfig b/configs/ls1021aqds_sdcard_ifc_defconfig
index 96314d542df..2f9d10dd6b5 100644
--- a/configs/ls1021aqds_sdcard_ifc_defconfig
+++ b/configs/ls1021aqds_sdcard_ifc_defconfig
@@ -56,6 +56,7 @@ CONFIG_SPL_MAX_SIZE=0x1a000
 CONFIG_SPL_PAD_TO=0x1c000
 CONFIG_SPL_FSL_PBL=y
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_SYS_MALLOC=y
 CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
 CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x820c0000
diff --git a/configs/ls1021aqds_sdcard_qspi_defconfig b/configs/ls1021aqds_sdcard_qspi_defconfig
index e466c3df145..58d1a68f595 100644
--- a/configs/ls1021aqds_sdcard_qspi_defconfig
+++ b/configs/ls1021aqds_sdcard_qspi_defconfig
@@ -55,6 +55,7 @@ CONFIG_SPL_MAX_SIZE=0x1a000
 CONFIG_SPL_PAD_TO=0x1c000
 CONFIG_SPL_FSL_PBL=y
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_SYS_MALLOC=y
 CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
 CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x820c0000
diff --git a/configs/ls1021atsn_sdcard_defconfig b/configs/ls1021atsn_sdcard_defconfig
index 86ee5315b42..ee3d9569699 100644
--- a/configs/ls1021atsn_sdcard_defconfig
+++ b/configs/ls1021atsn_sdcard_defconfig
@@ -49,6 +49,7 @@ CONFIG_SPL_MAX_SIZE=0x1a000
 CONFIG_SPL_PAD_TO=0x1c000
 CONFIG_SPL_FSL_PBL=y
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_SYS_MALLOC=y
 CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
 CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x82100000
diff --git a/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig b/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig
index 7dc3241124f..eb648f1e783 100644
--- a/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig
+++ b/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig
@@ -57,6 +57,7 @@ CONFIG_SPL_MAX_SIZE=0x1a000
 CONFIG_SPL_PAD_TO=0x1c000
 CONFIG_SPL_FSL_PBL=y
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_SYS_MALLOC=y
 CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
 CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x82104000
diff --git a/configs/ls1021atwr_sdcard_ifc_defconfig b/configs/ls1021atwr_sdcard_ifc_defconfig
index d62126274e5..f6edabaa76e 100644
--- a/configs/ls1021atwr_sdcard_ifc_defconfig
+++ b/configs/ls1021atwr_sdcard_ifc_defconfig
@@ -58,6 +58,7 @@ CONFIG_SPL_MAX_SIZE=0x1a000
 CONFIG_SPL_PAD_TO=0x1c000
 CONFIG_SPL_FSL_PBL=y
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_SYS_MALLOC=y
 CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
 CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x82100000
diff --git a/configs/ls1021atwr_sdcard_qspi_defconfig b/configs/ls1021atwr_sdcard_qspi_defconfig
index 53f487da198..24d20a262bb 100644
--- a/configs/ls1021atwr_sdcard_qspi_defconfig
+++ b/configs/ls1021atwr_sdcard_qspi_defconfig
@@ -59,6 +59,7 @@ CONFIG_SPL_MAX_SIZE=0x1a000
 CONFIG_SPL_PAD_TO=0x1c000
 CONFIG_SPL_FSL_PBL=y
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_SYS_MALLOC=y
 CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
 CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x82100000
diff --git a/configs/ls2080aqds_nand_defconfig b/configs/ls2080aqds_nand_defconfig
index 755411ed853..0685960f218 100644
--- a/configs/ls2080aqds_nand_defconfig
+++ b/configs/ls2080aqds_nand_defconfig
@@ -43,6 +43,7 @@ CONFIG_RESET_PHY_R=y
 CONFIG_SPL_MAX_SIZE=0x16000
 CONFIG_SPL_PAD_TO=0x20000
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_SYS_MALLOC=y
 CONFIG_SPL_ENV_SUPPORT=y
 CONFIG_SPL_I2C=y
diff --git a/configs/ls2080ardb_nand_defconfig b/configs/ls2080ardb_nand_defconfig
index 1be0b4e88cb..66276ec678e 100644
--- a/configs/ls2080ardb_nand_defconfig
+++ b/configs/ls2080ardb_nand_defconfig
@@ -49,6 +49,7 @@ CONFIG_RESET_PHY_R=y
 CONFIG_SPL_MAX_SIZE=0x16000
 CONFIG_SPL_PAD_TO=0x80000
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_SYS_MALLOC=y
 CONFIG_SPL_ENV_SUPPORT=y
 CONFIG_SPL_I2C=y
diff --git a/configs/lxr2_defconfig b/configs/lxr2_defconfig
index 7ab817960a2..0bc4ae0c7a5 100644
--- a/configs/lxr2_defconfig
+++ b/configs/lxr2_defconfig
@@ -13,7 +13,7 @@ CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_MX6Q=y
 CONFIG_TARGET_LXR2=y
 CONFIG_DM_GPIO=y
-CONFIG_DEFAULT_DEVICE_TREE="imx6q-lxr"
+CONFIG_DEFAULT_DEVICE_TREE="nxp/imx/imx6q-lxr"
 CONFIG_SYS_MONITOR_LEN=409600
 CONFIG_SPL_MMC=y
 CONFIG_SPL_SERIAL=y
@@ -77,6 +77,7 @@ CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
 CONFIG_ARP_TIMEOUT=200
 CONFIG_BOUNCE_BUFFER=y
 CONFIG_BOOTCOUNT_LIMIT=y
+CONFIG_BOOTCOUNT_ALTBOOTCMD="run swupdate"
 CONFIG_SYS_BOOTCOUNT_MAGIC=0xB0C4000
 CONFIG_SYS_BOOTCOUNT_BE=y
 CONFIG_DM_I2C=y
diff --git a/configs/m53menlo_defconfig b/configs/m53menlo_defconfig
index 6130cd8e466..cc6ef49b1d0 100644
--- a/configs/m53menlo_defconfig
+++ b/configs/m53menlo_defconfig
@@ -38,6 +38,7 @@ CONFIG_SPL_PAD_TO=0x8000
 CONFIG_SPL_NO_BSS_LIMIT=y
 CONFIG_SPL_BOARD_INIT=y
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_NAND_SUPPORT=y
 CONFIG_SPL_TARGET="u-boot-with-nand-spl.imx"
 CONFIG_HUSH_PARSER=y
@@ -79,6 +80,7 @@ CONFIG_USE_HOSTNAME=y
 CONFIG_HOSTNAME="m53menlo"
 CONFIG_VERSION_VARIABLE=y
 CONFIG_BOOTCOUNT_LIMIT=y
+CONFIG_BOOTCOUNT_ALTBOOTCMD="if test ${mmcpart} -eq 1 ; then setenv mmcpart 2 ; else setenv mmcpart 1 ; fi ; boot"
 CONFIG_SYS_BOOTCOUNT_MAGIC=0x0B01C041
 CONFIG_DM_I2C=y
 CONFIG_SYS_I2C_MXC=y
diff --git a/configs/maxbcm_defconfig b/configs/maxbcm_defconfig
index a3558c395b5..903f8a16d15 100644
--- a/configs/maxbcm_defconfig
+++ b/configs/maxbcm_defconfig
@@ -31,6 +31,7 @@ CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_SPL_MAX_SIZE=0x1bfd0
 CONFIG_SPL_SYS_MALLOC_SIMPLE=y
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_I2C=y
 CONFIG_SYS_MAXARGS=32
 CONFIG_CMD_I2C=y
diff --git a/configs/medcom-wide_defconfig b/configs/medcom-wide_defconfig
index def3f98bd72..737a0613ce1 100644
--- a/configs/medcom-wide_defconfig
+++ b/configs/medcom-wide_defconfig
@@ -19,6 +19,7 @@ CONFIG_SYS_STDIO_DEREGISTER=y
 CONFIG_SPL_FOOTPRINT_LIMIT=y
 CONFIG_SPL_MAX_FOOTPRINT=0x8000
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_SYS_MALLOC=y
 CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
 CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x90000
diff --git a/configs/microblaze-generic_defconfig b/configs/microblaze-generic_defconfig
index 87756cb26df..08f8bdb4240 100644
--- a/configs/microblaze-generic_defconfig
+++ b/configs/microblaze-generic_defconfig
@@ -35,6 +35,7 @@ CONFIG_SPL_MAX_FOOTPRINT=0xffb00
 CONFIG_SPL_BOARD_INIT=y
 CONFIG_SPL_SYS_MALLOC_SIMPLE=y
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_NOR_SUPPORT=y
 CONFIG_SYS_PROMPT="U-Boot-mONStR> "
 CONFIG_SYS_MAXARGS=15
diff --git a/configs/mk808_defconfig b/configs/mk808_defconfig
index e47d0b594f3..ecb9afa2f95 100644
--- a/configs/mk808_defconfig
+++ b/configs/mk808_defconfig
@@ -45,10 +45,11 @@ CONFIG_SPL_MAX_SIZE=0x32000
 CONFIG_SPL_PAD_TO=0x7f8000
 CONFIG_SPL_NO_BSS_LIMIT=y
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_SEPARATE_BSS=y
 CONFIG_SPL_FS_EXT4=y
 CONFIG_SYS_MMCSD_FS_BOOT_PARTITION=2
-CONFIG_TPL_NEEDS_SEPARATE_STACK=y
+CONFIG_TPL_HAVE_INIT_STACK=y
 # CONFIG_BOOTM_PLAN9 is not set
 # CONFIG_BOOTM_RTEMS is not set
 # CONFIG_BOOTM_VXWORKS is not set
diff --git a/configs/mocha_defconfig b/configs/mocha_defconfig
new file mode 100644
index 00000000000..dfeb16ac08e
--- /dev/null
+++ b/configs/mocha_defconfig
@@ -0,0 +1,92 @@
+CONFIG_ARM=y
+CONFIG_ARCH_TEGRA=y
+CONFIG_SUPPORT_PASSING_ATAGS=y
+CONFIG_CMDLINE_TAG=y
+CONFIG_INITRD_TAG=y
+CONFIG_TEXT_BASE=0x80110000
+CONFIG_SYS_MALLOC_LEN=0x2500000
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_ENV_SOURCE_FILE="mocha"
+CONFIG_ENV_SIZE=0x3000
+CONFIG_ENV_OFFSET=0xFFFFD000
+CONFIG_DEFAULT_DEVICE_TREE="tegra124-xiaomi-mocha"
+CONFIG_SPL_STACK=0x800ffffc
+CONFIG_SPL_TEXT_BASE=0x80108000
+CONFIG_SYS_LOAD_ADDR=0x82000000
+CONFIG_TEGRA124=y
+CONFIG_TARGET_MOCHA=y
+CONFIG_TEGRA_ENABLE_UARTD=y
+CONFIG_CMD_EBTUPDATE=y
+CONFIG_TEGRA_GPU=y
+CONFIG_BUTTON_CMD=y
+CONFIG_BOOTDELAY=0
+CONFIG_AUTOBOOT_KEYED=y
+CONFIG_AUTOBOOT_KEYED_CTRLC=y
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_BOOTCOMMAND="bootflow scan; echo 'Boot configuration not found... Power off in 3 sec'; sleep 3; poweroff"
+CONFIG_SYS_PBSIZE=2086
+CONFIG_SPL_FOOTPRINT_LIMIT=y
+CONFIG_SPL_MAX_FOOTPRINT=0x8000
+# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
+CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x80090000
+CONFIG_SPL_SYS_MALLOC_SIZE=0x10000
+CONFIG_SYS_PROMPT="Tegra124 (Mocha) # "
+# CONFIG_CMD_BOOTEFI_BOOTMGR is not set
+CONFIG_CMD_BOOTMENU=y
+# CONFIG_CMD_IMI is not set
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_GPT_RENAME=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_POWEROFF=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_UMS_ABORT_KEYED=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_PAUSE=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_EXT4_WRITE=y
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
+CONFIG_ENV_OVERWRITE=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_PART=2
+CONFIG_BUTTON=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x91000000
+CONFIG_FASTBOOT_BUF_SIZE=0x10000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=0
+CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
+CONFIG_PALMAS_GPIO=y
+CONFIG_SYS_I2C_TEGRA=y
+CONFIG_BUTTON_KEYBOARD=y
+CONFIG_DM_PMIC=y
+CONFIG_PMIC_PALMAS=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_PALMAS=y
+CONFIG_PWM_TEGRA=y
+CONFIG_SYS_NS16550=y
+CONFIG_SYSRESET_PALMAS=y
+CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_TEGRA=y
+CONFIG_USB_KEYBOARD=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="Xiaomi"
+CONFIG_USB_GADGET_VENDOR_NUM=0x18d1
+CONFIG_USB_GADGET_PRODUCT_NUM=0xd00d
+CONFIG_CI_UDC=y
+CONFIG_VIDEO=y
+CONFIG_VIDEO_BRIDGE=y
+# CONFIG_VIDEO_FONT_8X16 is not set
+CONFIG_VIDEO_FONT_16X32=y
+# CONFIG_VIDEO_LOGO is not set
+CONFIG_VIDEO_LCD_SHARP_LQ079L1SX01=y
+CONFIG_BACKLIGHT_LP855x=y
+CONFIG_VIDEO_DSI_TEGRA30=y
diff --git a/configs/msc_sm2s_imx8mp_defconfig b/configs/msc_sm2s_imx8mp_defconfig
index def90d470b1..5829898a3c6 100644
--- a/configs/msc_sm2s_imx8mp_defconfig
+++ b/configs/msc_sm2s_imx8mp_defconfig
@@ -39,6 +39,7 @@ CONFIG_SPL_BOARD_INIT=y
 CONFIG_SPL_BOOTROM_SUPPORT=y
 CONFIG_SPL_SYS_MALLOC_SIMPLE=y
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_SYS_MALLOC=y
 CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
 CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000
diff --git a/configs/mt7629_rfb_defconfig b/configs/mt7629_rfb_defconfig
index f69be08cc3f..f9d558819b7 100644
--- a/configs/mt7629_rfb_defconfig
+++ b/configs/mt7629_rfb_defconfig
@@ -35,6 +35,7 @@ CONFIG_SPL_FOOTPRINT_LIMIT=y
 CONFIG_SPL_MAX_FOOTPRINT=0x10000
 CONFIG_SPL_SYS_MALLOC_SIMPLE=y
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_NOR_SUPPORT=y
 CONFIG_SPL_WATCHDOG=y
 CONFIG_HUSH_PARSER=y
diff --git a/configs/mx53ppd_defconfig b/configs/mx53ppd_defconfig
index d91c59ffe46..4ec8516015f 100644
--- a/configs/mx53ppd_defconfig
+++ b/configs/mx53ppd_defconfig
@@ -47,6 +47,7 @@ CONFIG_ARP_TIMEOUT=200
 CONFIG_BOOTCOUNT_LIMIT=y
 CONFIG_DM_BOOTCOUNT=y
 CONFIG_DM_BOOTCOUNT_I2C_EEPROM=y
+CONFIG_BOOTCOUNT_ALTBOOTCMD="run doquiet; setenv partnum 1; run hasfirstboot || setenv partnum 2; run hasfirstboot || setenv partnum 0; if test ${partnum} != 0; then run swappartitions loadimage doboot; fi; run failbootcmd"
 CONFIG_DM_I2C=y
 CONFIG_SYS_I2C_MXC=y
 CONFIG_I2C_MUX=y
diff --git a/configs/mx6sxsabreauto_defconfig b/configs/mx6sxsabreauto_defconfig
index 870b7a1be10..25b0b11342d 100644
--- a/configs/mx6sxsabreauto_defconfig
+++ b/configs/mx6sxsabreauto_defconfig
@@ -13,7 +13,7 @@ CONFIG_DEFAULT_DEVICE_TREE="imx6sx-sabreauto"
 # CONFIG_CMD_BMODE is not set
 CONFIG_SUPPORT_RAW_INITRD=y
 CONFIG_USE_BOOTCOMMAND=y
-CONFIG_BOOTCOMMAND="mmc dev ${mmcdev};mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
+CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
 CONFIG_SYS_PBSIZE=532
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_MAXARGS=32
diff --git a/configs/mx6ul_14x14_evk_defconfig b/configs/mx6ul_14x14_evk_defconfig
index f841b21c016..737a079eaa7 100644
--- a/configs/mx6ul_14x14_evk_defconfig
+++ b/configs/mx6ul_14x14_evk_defconfig
@@ -24,7 +24,7 @@ CONFIG_SYS_MEMTEST_START=0x80000000
 CONFIG_SYS_MEMTEST_END=0x88000000
 CONFIG_SUPPORT_RAW_INITRD=y
 CONFIG_USE_BOOTCOMMAND=y
-CONFIG_BOOTCOMMAND="run findfdt;mmc dev ${mmcdev};mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
+CONFIG_BOOTCOMMAND="run findfdt;mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
 CONFIG_SYS_PBSIZE=532
 # CONFIG_CONSOLE_MUX is not set
 CONFIG_SYS_CONSOLE_IS_IN_ENV=y
diff --git a/configs/mx6ul_9x9_evk_defconfig b/configs/mx6ul_9x9_evk_defconfig
index 11a18d16f52..964d00a4085 100644
--- a/configs/mx6ul_9x9_evk_defconfig
+++ b/configs/mx6ul_9x9_evk_defconfig
@@ -24,7 +24,7 @@ CONFIG_SYS_MEMTEST_START=0x80000000
 CONFIG_SYS_MEMTEST_END=0x88000000
 CONFIG_SUPPORT_RAW_INITRD=y
 CONFIG_USE_BOOTCOMMAND=y
-CONFIG_BOOTCOMMAND="run findfdt;mmc dev ${mmcdev};mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
+CONFIG_BOOTCOMMAND="run findfdt;mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
 CONFIG_SYS_PBSIZE=532
 # CONFIG_CONSOLE_MUX is not set
 CONFIG_SYS_CONSOLE_IS_IN_ENV=y
diff --git a/configs/mx6ull_14x14_evk_defconfig b/configs/mx6ull_14x14_evk_defconfig
index 316f74c278b..369bc0f2e0a 100644
--- a/configs/mx6ull_14x14_evk_defconfig
+++ b/configs/mx6ull_14x14_evk_defconfig
@@ -14,7 +14,7 @@ CONFIG_SYS_MEMTEST_START=0x80000000
 CONFIG_SYS_MEMTEST_END=0x88000000
 CONFIG_SUPPORT_RAW_INITRD=y
 CONFIG_USE_BOOTCOMMAND=y
-CONFIG_BOOTCOMMAND="run findfdt;mmc dev ${mmcdev};mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
+CONFIG_BOOTCOMMAND="run findfdt;mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
 CONFIG_SYS_PBSIZE=532
 CONFIG_ARCH_MISC_INIT=y
 CONFIG_BOARD_EARLY_INIT_F=y
diff --git a/configs/mx6ull_14x14_evk_plugin_defconfig b/configs/mx6ull_14x14_evk_plugin_defconfig
index 8be5963a433..97d4f9fc65f 100644
--- a/configs/mx6ull_14x14_evk_plugin_defconfig
+++ b/configs/mx6ull_14x14_evk_plugin_defconfig
@@ -15,7 +15,7 @@ CONFIG_SYS_MEMTEST_START=0x80000000
 CONFIG_SYS_MEMTEST_END=0x88000000
 CONFIG_SUPPORT_RAW_INITRD=y
 CONFIG_USE_BOOTCOMMAND=y
-CONFIG_BOOTCOMMAND="run findfdt;mmc dev ${mmcdev};mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
+CONFIG_BOOTCOMMAND="run findfdt;mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
 CONFIG_SYS_PBSIZE=532
 CONFIG_ARCH_MISC_INIT=y
 CONFIG_BOARD_EARLY_INIT_F=y
diff --git a/configs/mx6ulz_14x14_evk_defconfig b/configs/mx6ulz_14x14_evk_defconfig
index 2c13dd4dbc3..1a49bc2cf01 100644
--- a/configs/mx6ulz_14x14_evk_defconfig
+++ b/configs/mx6ulz_14x14_evk_defconfig
@@ -14,7 +14,7 @@ CONFIG_SYS_MEMTEST_START=0x80000000
 CONFIG_SYS_MEMTEST_END=0x88000000
 CONFIG_SUPPORT_RAW_INITRD=y
 CONFIG_USE_BOOTCOMMAND=y
-CONFIG_BOOTCOMMAND="run findfdt;mmc dev ${mmcdev};mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
+CONFIG_BOOTCOMMAND="run findfdt;mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
 CONFIG_SYS_PBSIZE=532
 CONFIG_BOARD_EARLY_INIT_F=y
 CONFIG_HUSH_PARSER=y
diff --git a/configs/n2350_defconfig b/configs/n2350_defconfig
index 9fb84c3b946..b9ff95c5512 100644
--- a/configs/n2350_defconfig
+++ b/configs/n2350_defconfig
@@ -41,6 +41,7 @@ CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_SPL_MAX_SIZE=0x22fd0
 CONFIG_SPL_SYS_MALLOC_SIMPLE=y
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_I2C=y
 CONFIG_SYS_PROMPT="N2350 > "
 CONFIG_SYS_MAXARGS=32
diff --git a/configs/nyan-big_defconfig b/configs/nyan-big_defconfig
index 9054ec54ff9..d218fa34000 100644
--- a/configs/nyan-big_defconfig
+++ b/configs/nyan-big_defconfig
@@ -27,6 +27,7 @@ CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_SPL_FOOTPRINT_LIMIT=y
 CONFIG_SPL_MAX_FOOTPRINT=0xef8100
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_SYS_MALLOC=y
 CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
 CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x80090000
diff --git a/configs/omapl138_lcdk_defconfig b/configs/omapl138_lcdk_defconfig
index b9ea355151e..c0949fc8750 100644
--- a/configs/omapl138_lcdk_defconfig
+++ b/configs/omapl138_lcdk_defconfig
@@ -41,6 +41,7 @@ CONFIG_SPL_FOOTPRINT_LIMIT=y
 CONFIG_SPL_MAX_FOOTPRINT=0x8000
 CONFIG_SPL_SYS_MALLOC_SIMPLE=y
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_SYS_MALLOC=y
 CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
 CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0xc0f70000
diff --git a/configs/openpiton_riscv64_spl_defconfig b/configs/openpiton_riscv64_spl_defconfig
index 09054d93047..13d956aea32 100644
--- a/configs/openpiton_riscv64_spl_defconfig
+++ b/configs/openpiton_riscv64_spl_defconfig
@@ -33,6 +33,7 @@ CONFIG_SPL_MAX_SIZE=0x100000
 # CONFIG_SPL_LEGACY_IMAGE_FORMAT is not set
 CONFIG_SPL_SYS_MALLOC_SIMPLE=y
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_SYS_MALLOC=y
 # CONFIG_SPL_BANNER_PRINT is not set
 CONFIG_SPL_CPU=y
diff --git a/configs/ouya_defconfig b/configs/ouya_defconfig
new file mode 100644
index 00000000000..d4ae9dbb57c
--- /dev/null
+++ b/configs/ouya_defconfig
@@ -0,0 +1,87 @@
+CONFIG_ARM=y
+CONFIG_ARCH_TEGRA=y
+CONFIG_SUPPORT_PASSING_ATAGS=y
+CONFIG_CMDLINE_TAG=y
+CONFIG_INITRD_TAG=y
+CONFIG_TEXT_BASE=0x80110000
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_ENV_SOURCE_FILE="ouya"
+CONFIG_ENV_SIZE=0x3000
+CONFIG_ENV_OFFSET=0xFFFFD000
+CONFIG_DEFAULT_DEVICE_TREE="tegra30-ouya"
+CONFIG_SPL_STACK=0x800ffffc
+CONFIG_SPL_TEXT_BASE=0x80108000
+CONFIG_SYS_LOAD_ADDR=0x82000000
+CONFIG_TEGRA30=y
+CONFIG_TARGET_OUYA=y
+CONFIG_TEGRA_ENABLE_UARTD=y
+CONFIG_CMD_EBTUPDATE=y
+CONFIG_BUTTON_CMD=y
+CONFIG_BOOTDELAY=3
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_BOOTCOMMAND="bootflow scan; echo 'Boot configuration not found... Power off in 3 sec'; sleep 3; poweroff"
+CONFIG_USE_PREBOOT=y
+CONFIG_SYS_PBSIZE=2084
+CONFIG_SPL_FOOTPRINT_LIMIT=y
+CONFIG_SPL_MAX_FOOTPRINT=0x8000
+# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
+CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x80090000
+CONFIG_SPL_SYS_MALLOC_SIZE=0x10000
+CONFIG_SYS_PROMPT="Tegra30 (Ouya) # "
+# CONFIG_CMD_BOOTEFI_BOOTMGR is not set
+CONFIG_CMD_BOOTMENU=y
+# CONFIG_CMD_IMI is not set
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_GPT_RENAME=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_POWEROFF=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_UMS_ABORT_KEYED=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_PAUSE=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_EXT4_WRITE=y
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
+CONFIG_ENV_OVERWRITE=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_PART=2
+CONFIG_BUTTON=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x91000000
+CONFIG_FASTBOOT_BUF_SIZE=0x10000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=0
+CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
+CONFIG_GPIO_HOG=y
+CONFIG_SYS_I2C_TEGRA=y
+CONFIG_BUTTON_KEYBOARD=y
+CONFIG_LED=y
+CONFIG_LED_BLINK=y
+CONFIG_LED_GPIO=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_TPS65910=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_TPS65911=y
+CONFIG_PWM_TEGRA=y
+CONFIG_SYS_NS16550=y
+CONFIG_SYSRESET_TPS65910=y
+CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_TEGRA=y
+CONFIG_USB_KEYBOARD=y
+CONFIG_USB_GADGET=y
+CONFIG_CI_UDC=y
+CONFIG_VIDEO=y
+# CONFIG_VIDEO_LOGO is not set
+CONFIG_I2C_EDID_STANDARD=y
+CONFIG_VIDEO_BRIDGE=y
+CONFIG_VIDEO_HDMI_TEGRA=y
diff --git a/configs/paz00_defconfig b/configs/paz00_defconfig
index e93fa1c003a..b8645d66619 100644
--- a/configs/paz00_defconfig
+++ b/configs/paz00_defconfig
@@ -16,6 +16,7 @@ CONFIG_SYS_PBSIZE=2087
 CONFIG_SPL_FOOTPRINT_LIMIT=y
 CONFIG_SPL_MAX_FOOTPRINT=0x8000
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_SYS_MALLOC=y
 CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
 CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x90000
diff --git a/configs/peach-pi_defconfig b/configs/peach-pi_defconfig
index 594af5136e3..247df4c9036 100644
--- a/configs/peach-pi_defconfig
+++ b/configs/peach-pi_defconfig
@@ -81,7 +81,6 @@ CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_HOST_ETHER=y
 CONFIG_VIDEO=y
 # CONFIG_VIDEO_BPP8 is not set
-CONFIG_VIDCONSOLE_AS_LCD=y
 CONFIG_DISPLAY=y
 CONFIG_VIDEO_EXYNOS=y
 CONFIG_EXYNOS_DP=y
diff --git a/configs/peach-pit_defconfig b/configs/peach-pit_defconfig
index 2b34c25556a..df72be8047b 100644
--- a/configs/peach-pit_defconfig
+++ b/configs/peach-pit_defconfig
@@ -80,7 +80,6 @@ CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_HOST_ETHER=y
 CONFIG_VIDEO=y
 # CONFIG_VIDEO_BPP8 is not set
-CONFIG_VIDCONSOLE_AS_LCD=y
 CONFIG_DISPLAY=y
 CONFIG_VIDEO_EXYNOS=y
 CONFIG_EXYNOS_DP=y
diff --git a/configs/pg_wcom_expu1_defconfig b/configs/pg_wcom_expu1_defconfig
index 1120191585c..4b82b077ea7 100644
--- a/configs/pg_wcom_expu1_defconfig
+++ b/configs/pg_wcom_expu1_defconfig
@@ -73,6 +73,7 @@ CONFIG_HOSTNAME="EXPU1"
 CONFIG_VERSION_VARIABLE=y
 # CONFIG_SCSI_AHCI is not set
 CONFIG_BOOTCOUNT_LIMIT=y
+CONFIG_BOOTCOUNT_ALTBOOTCMD="run bootcmd"
 CONFIG_SYS_BOOTCOUNT_BE=y
 CONFIG_DDR_CLK_FREQ=50000000
 CONFIG_SYS_FSL_DDR3=y
diff --git a/configs/pg_wcom_expu1_update_defconfig b/configs/pg_wcom_expu1_update_defconfig
index 772aa210fc2..53d54789687 100644
--- a/configs/pg_wcom_expu1_update_defconfig
+++ b/configs/pg_wcom_expu1_update_defconfig
@@ -71,6 +71,7 @@ CONFIG_HOSTNAME="EXPU1"
 CONFIG_VERSION_VARIABLE=y
 # CONFIG_SCSI_AHCI is not set
 CONFIG_BOOTCOUNT_LIMIT=y
+CONFIG_BOOTCOUNT_ALTBOOTCMD="run bootcmd"
 CONFIG_SYS_BOOTCOUNT_BE=y
 CONFIG_DDR_CLK_FREQ=50000000
 CONFIG_SYS_FSL_DDR3=y
diff --git a/configs/pg_wcom_seli8_defconfig b/configs/pg_wcom_seli8_defconfig
index 6cde217a34c..731ca435089 100644
--- a/configs/pg_wcom_seli8_defconfig
+++ b/configs/pg_wcom_seli8_defconfig
@@ -73,6 +73,7 @@ CONFIG_HOSTNAME="SELI8"
 CONFIG_VERSION_VARIABLE=y
 # CONFIG_SCSI_AHCI is not set
 CONFIG_BOOTCOUNT_LIMIT=y
+CONFIG_BOOTCOUNT_ALTBOOTCMD="run bootcmd"
 CONFIG_SYS_BOOTCOUNT_BE=y
 CONFIG_DDR_CLK_FREQ=50000000
 CONFIG_SYS_FSL_DDR3=y
diff --git a/configs/pg_wcom_seli8_update_defconfig b/configs/pg_wcom_seli8_update_defconfig
index e8afc95d607..2598e477ed5 100644
--- a/configs/pg_wcom_seli8_update_defconfig
+++ b/configs/pg_wcom_seli8_update_defconfig
@@ -71,6 +71,7 @@ CONFIG_HOSTNAME="SELI8"
 CONFIG_VERSION_VARIABLE=y
 # CONFIG_SCSI_AHCI is not set
 CONFIG_BOOTCOUNT_LIMIT=y
+CONFIG_BOOTCOUNT_ALTBOOTCMD="run bootcmd"
 CONFIG_SYS_BOOTCOUNT_BE=y
 CONFIG_DDR_CLK_FREQ=50000000
 CONFIG_SYS_FSL_DDR3=y
diff --git a/configs/phycore-imx8mm_defconfig b/configs/phycore-imx8mm_defconfig
index a7555fdabc7..7de40106883 100644
--- a/configs/phycore-imx8mm_defconfig
+++ b/configs/phycore-imx8mm_defconfig
@@ -37,6 +37,7 @@ CONFIG_SYS_CBSIZE=2048
 CONFIG_SYS_PBSIZE=2074
 CONFIG_BOARD_LATE_INIT=y
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_SYS_MALLOC=y
 CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
 CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000
diff --git a/configs/phycore-imx8mp_defconfig b/configs/phycore-imx8mp_defconfig
index 58981e79a11..cc583e8665c 100644
--- a/configs/phycore-imx8mp_defconfig
+++ b/configs/phycore-imx8mp_defconfig
@@ -45,6 +45,7 @@ CONFIG_SPL_BOARD_INIT=y
 CONFIG_SPL_BOOTROM_SUPPORT=y
 CONFIG_SPL_SYS_MALLOC_SIMPLE=y
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_SYS_MALLOC=y
 CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
 CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000
diff --git a/configs/phycore-rk3288_defconfig b/configs/phycore-rk3288_defconfig
index 0f8e999ee3f..cbdc0a2bd27 100644
--- a/configs/phycore-rk3288_defconfig
+++ b/configs/phycore-rk3288_defconfig
@@ -33,6 +33,7 @@ CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_SPL_PAD_TO=0x7f8000
 CONFIG_SPL_NO_BSS_LIMIT=y
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_GPT=y
 CONFIG_CMD_I2C=y
diff --git a/configs/phycore_am62ax_a53_defconfig b/configs/phycore_am62ax_a53_defconfig
index 421dd851506..d86e19d914f 100644
--- a/configs/phycore_am62ax_a53_defconfig
+++ b/configs/phycore_am62ax_a53_defconfig
@@ -35,6 +35,9 @@ CONFIG_SPL_LIBDISK_SUPPORT=y
 CONFIG_SPL_SPI_FLASH_SUPPORT=y
 CONFIG_SPL_SPI=y
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_EFI_SET_TIME=y
+CONFIG_EFI_CAPSULE_ON_DISK=y
+CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y
 CONFIG_SPL_LOAD_FIT=y
 CONFIG_SPL_LOAD_FIT_ADDRESS=0x81000000
 CONFIG_BOOTSTD_FULL=y
@@ -62,19 +65,25 @@ CONFIG_SPL_SPI_FLASH_SFDP_SUPPORT=y
 CONFIG_SPL_SPI_LOAD=y
 CONFIG_SYS_SPI_U_BOOT_OFFS=0x280000
 CONFIG_SPL_YMODEM_SUPPORT=y
+# CONFIG_CMD_BOOTEFI_HELLO is not set
+CONFIG_CMD_BOOTEFI_SELFTEST=y
+CONFIG_CMD_NVEDIT_EFI=y
 CONFIG_CMD_DFU=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_MTD=y
+# CONFIG_CMD_POWEROFF is not set
 CONFIG_CMD_REMOTEPROC=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_USB_MASS_STORAGE=y
 CONFIG_CMD_CACHE=y
+CONFIG_CMD_EFIDEBUG=y
 CONFIG_CMD_RTC=y
 CONFIG_CMD_SMC=y
 CONFIG_OF_CONTROL=y
 CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_OVERLAY_LIST="ti/k3-am6xx-phycore-disable-spi-nor ti/k3-am6xx-phycore-disable-rtc ti/k3-am6xx-phycore-disable-eth-phy ti/k3-am6xx-phycore-qspi-nor"
 CONFIG_MULTI_DTB_FIT=y
 CONFIG_SPL_MULTI_DTB_FIT=y
 CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y
@@ -96,6 +105,7 @@ CONFIG_CLK=y
 CONFIG_SPL_CLK=y
 CONFIG_CLK_TI_SCI=y
 CONFIG_DFU_MMC=y
+CONFIG_DFU_MTD=y
 CONFIG_DFU_RAM=y
 CONFIG_DFU_SF=y
 CONFIG_SYS_DFU_DATA_BUF_SIZE=0x40000
@@ -119,6 +129,7 @@ CONFIG_MMC_SDHCI_ADMA=y
 CONFIG_SPL_MMC_SDHCI_ADMA=y
 CONFIG_MMC_SDHCI_AM654=y
 CONFIG_MTD=y
+CONFIG_DM_MTD=y
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH_SFDP_SUPPORT=y
 # CONFIG_SPI_FLASH_SMART_HWCAPS is not set
@@ -143,8 +154,6 @@ CONFIG_SPL_DM_REGULATOR_FIXED=y
 CONFIG_DM_REGULATOR_GPIO=y
 CONFIG_K3_SYSTEM_CONTROLLER=y
 CONFIG_REMOTEPROC_TI_K3_ARM64=y
-CONFIG_REMOTEPROC_TI_K3_DSP=y
-CONFIG_REMOTEPROC_TI_K3_R5F=y
 CONFIG_RESET_TI_SCI=y
 CONFIG_DM_RTC=y
 CONFIG_RTC_RV3028=y
@@ -178,3 +187,4 @@ CONFIG_USB_GADGET_VENDOR_NUM=0x0451
 CONFIG_USB_GADGET_PRODUCT_NUM=0x6165
 CONFIG_SPL_DFU=y
 CONFIG_FS_FAT_MAX_CLUSTSIZE=16384
+# CONFIG_HEXDUMP is not set
diff --git a/configs/phycore_am62ax_r5_defconfig b/configs/phycore_am62ax_r5_defconfig
index a71ebf0dc2c..25d2d9babba 100644
--- a/configs/phycore_am62ax_r5_defconfig
+++ b/configs/phycore_am62ax_r5_defconfig
@@ -49,7 +49,6 @@ CONFIG_SPL_DM_SPI_FLASH=y
 CONFIG_SPL_DM_RESET=y
 CONFIG_SPL_POWER_DOMAIN=y
 CONFIG_SPL_RAM_DEVICE=y
-CONFIG_SPL_REMOTEPROC=y
 CONFIG_SPL_SPI_LOAD=y
 CONFIG_SYS_SPI_U_BOOT_OFFS=0x80000
 CONFIG_SPL_THERMAL=y
@@ -59,7 +58,6 @@ CONFIG_CMD_ASKENV=y
 CONFIG_CMD_DFU=y
 CONFIG_CMD_GPT=y
 CONFIG_CMD_MMC=y
-CONFIG_CMD_REMOTEPROC=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_TIME=y
 CONFIG_CMD_FAT=y
@@ -112,7 +110,6 @@ CONFIG_PINCTRL_SINGLE=y
 CONFIG_POWER_DOMAIN=y
 CONFIG_TI_POWER_DOMAIN=y
 CONFIG_K3_SYSTEM_CONTROLLER=y
-CONFIG_REMOTEPROC_TI_K3_ARM64=y
 CONFIG_RESET_TI_SCI=y
 CONFIG_SPECIFY_CONSOLE_INDEX=y
 CONFIG_DM_SERIAL=y
diff --git a/configs/phycore_am62ax_r5_usbdfu_defconfig b/configs/phycore_am62ax_r5_usbdfu_defconfig
new file mode 100644
index 00000000000..34674ce4371
--- /dev/null
+++ b/configs/phycore_am62ax_r5_usbdfu_defconfig
@@ -0,0 +1,4 @@
+#include <configs/phycore_am62ax_r5_defconfig>
+#include <configs/am62x_r5_usbdfu.config>
+
+CONFIG_USB_GADGET_MANUFACTURER="PHYTEC"
diff --git a/configs/phycore_am62x_a53_defconfig b/configs/phycore_am62x_a53_defconfig
index 0494fc408b7..d7aa59bf1dd 100644
--- a/configs/phycore_am62x_a53_defconfig
+++ b/configs/phycore_am62x_a53_defconfig
@@ -13,6 +13,7 @@ CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80b80000
 CONFIG_SF_DEFAULT_SPEED=25000000
 CONFIG_ENV_SIZE=0x20000
 CONFIG_ENV_OFFSET=0x680000
+CONFIG_ENV_SECT_SIZE=0x20000
 CONFIG_SPL_DM_SPI=y
 CONFIG_DEFAULT_DEVICE_TREE="ti/k3-am625-phyboard-lyra-rdk"
 CONFIG_OF_LIBFDT_OVERLAY=y
@@ -84,6 +85,7 @@ CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y
 CONFIG_ENV_OVERWRITE=y
 CONFIG_ENV_IS_NOWHERE=y
 CONFIG_ENV_IS_IN_MMC=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
 CONFIG_SYS_MMC_ENV_DEV=1
 CONFIG_NET_RANDOM_ETHADDR=y
diff --git a/configs/phycore_am62x_r5_defconfig b/configs/phycore_am62x_r5_defconfig
index 25adca467b5..f157103be4a 100644
--- a/configs/phycore_am62x_r5_defconfig
+++ b/configs/phycore_am62x_r5_defconfig
@@ -55,7 +55,6 @@ CONFIG_SPL_DM_SPI_FLASH=y
 CONFIG_SPL_DM_RESET=y
 CONFIG_SPL_POWER_DOMAIN=y
 CONFIG_SPL_RAM_DEVICE=y
-CONFIG_SPL_REMOTEPROC=y
 # CONFIG_SPL_SPI_FLASH_TINY is not set
 CONFIG_SPL_SPI_FLASH_SFDP_SUPPORT=y
 CONFIG_SPL_SPI_LOAD=y
@@ -66,7 +65,6 @@ CONFIG_CMD_ASKENV=y
 CONFIG_CMD_DFU=y
 CONFIG_CMD_GPT=y
 CONFIG_CMD_MMC=y
-CONFIG_CMD_REMOTEPROC=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_TIME=y
 CONFIG_CMD_FAT=y
@@ -114,7 +112,6 @@ CONFIG_PINCTRL_SINGLE=y
 CONFIG_POWER_DOMAIN=y
 CONFIG_TI_POWER_DOMAIN=y
 CONFIG_K3_SYSTEM_CONTROLLER=y
-CONFIG_REMOTEPROC_TI_K3_ARM64=y
 CONFIG_RESET_TI_SCI=y
 CONFIG_SPECIFY_CONSOLE_INDEX=y
 CONFIG_DM_SERIAL=y
diff --git a/configs/phycore_am64x_a53_defconfig b/configs/phycore_am64x_a53_defconfig
index f0c7ee26384..4ee1bd829a3 100644
--- a/configs/phycore_am64x_a53_defconfig
+++ b/configs/phycore_am64x_a53_defconfig
@@ -14,6 +14,7 @@ CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80480000
 CONFIG_ENV_SIZE=0x20000
 CONFIG_ENV_OFFSET=0x680000
+CONFIG_ENV_SECT_SIZE=0x20000
 CONFIG_DM_GPIO=y
 CONFIG_SPL_DM_SPI=y
 CONFIG_DEFAULT_DEVICE_TREE="ti/k3-am642-phyboard-electra-rdk"
@@ -91,6 +92,7 @@ CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y
 CONFIG_ENV_OVERWRITE=y
 CONFIG_ENV_IS_NOWHERE=y
 CONFIG_ENV_IS_IN_MMC=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
 CONFIG_SYS_MMC_ENV_DEV=1
 CONFIG_NET_RANDOM_ETHADDR=y
diff --git a/configs/phycore_am64x_r5_defconfig b/configs/phycore_am64x_r5_defconfig
index d060a0f1d10..2552479713f 100644
--- a/configs/phycore_am64x_r5_defconfig
+++ b/configs/phycore_am64x_r5_defconfig
@@ -61,7 +61,6 @@ CONFIG_SPL_NET_VCI_STRING="AM64X U-Boot R5 SPL"
 CONFIG_SPL_DM_RESET=y
 CONFIG_SPL_POWER_DOMAIN=y
 CONFIG_SPL_RAM_DEVICE=y
-CONFIG_SPL_REMOTEPROC=y
 # CONFIG_SPL_SPI_FLASH_TINY is not set
 CONFIG_SPL_SPI_FLASH_SFDP_SUPPORT=y
 CONFIG_SPL_SPI_LOAD=y
@@ -73,7 +72,6 @@ CONFIG_CMD_ASKENV=y
 CONFIG_CMD_DFU=y
 CONFIG_CMD_GPT=y
 CONFIG_CMD_MMC=y
-CONFIG_CMD_REMOTEPROC=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_USB_MASS_STORAGE=y
 # CONFIG_CMD_SETEXPR is not set
@@ -140,7 +138,6 @@ CONFIG_SPL_DM_REGULATOR=y
 CONFIG_DM_REGULATOR_GPIO=y
 CONFIG_SPL_DM_REGULATOR_GPIO=y
 CONFIG_K3_SYSTEM_CONTROLLER=y
-CONFIG_REMOTEPROC_TI_K3_ARM64=y
 CONFIG_RESET_TI_SCI=y
 CONFIG_SPECIFY_CONSOLE_INDEX=y
 CONFIG_DM_SERIAL=y
diff --git a/configs/picasso_defconfig b/configs/picasso_defconfig
index 994951bb81e..fe1eeb6ed10 100644
--- a/configs/picasso_defconfig
+++ b/configs/picasso_defconfig
@@ -21,11 +21,12 @@ CONFIG_BOOTDELAY=0
 CONFIG_AUTOBOOT_KEYED=y
 CONFIG_AUTOBOOT_KEYED_CTRLC=y
 CONFIG_OF_SYSTEM_SETUP=y
-CONFIG_BOOTCOMMAND="bootflow scan; poweroff"
+CONFIG_BOOTCOMMAND="bootflow scan; echo 'Boot configuration not found... Power off in 3 sec'; sleep 3; poweroff"
 CONFIG_SYS_PBSIZE=2085
 CONFIG_SPL_FOOTPRINT_LIMIT=y
 CONFIG_SPL_MAX_FOOTPRINT=0x8000
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_SYS_MALLOC=y
 CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
 CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x90000
diff --git a/configs/pico-imx8mq_defconfig b/configs/pico-imx8mq_defconfig
index e9ba2a6bf42..02cfee2694f 100644
--- a/configs/pico-imx8mq_defconfig
+++ b/configs/pico-imx8mq_defconfig
@@ -39,6 +39,7 @@ CONFIG_BOARD_LATE_INIT=y
 CONFIG_SPL_MAX_SIZE=0x1f000
 CONFIG_SPL_BOARD_INIT=y
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_SYS_MALLOC=y
 CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
 CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000
diff --git a/configs/plutux_defconfig b/configs/plutux_defconfig
index 1f2889ea8b1..a5bc1f6b284 100644
--- a/configs/plutux_defconfig
+++ b/configs/plutux_defconfig
@@ -20,6 +20,7 @@ CONFIG_SYS_STDIO_DEREGISTER=y
 CONFIG_SPL_FOOTPRINT_LIMIT=y
 CONFIG_SPL_MAX_FOOTPRINT=0x8000
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_SYS_MALLOC=y
 CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
 CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x90000
diff --git a/configs/poleg_evb_defconfig b/configs/poleg_evb_defconfig
index 74f4092d288..365f6434f83 100644
--- a/configs/poleg_evb_defconfig
+++ b/configs/poleg_evb_defconfig
@@ -16,6 +16,7 @@ CONFIG_DEFAULT_DEVICE_TREE="nuvoton-npcm750-evb"
 CONFIG_DM_RESET=y
 CONFIG_SYS_LOAD_ADDR=0x10000000
 CONFIG_TARGET_POLEG=y
+CONFIG_SYS_SKIP_UART_INIT=y
 CONFIG_ENV_ADDR=0x80100000
 CONFIG_FIT=y
 CONFIG_USE_BOOTCOMMAND=y
diff --git a/configs/popmetal-rk3288_defconfig b/configs/popmetal-rk3288_defconfig
index 1b2fb4a38cd..13315df0607 100644
--- a/configs/popmetal-rk3288_defconfig
+++ b/configs/popmetal-rk3288_defconfig
@@ -32,6 +32,7 @@ CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_SPL_PAD_TO=0x7f8000
 CONFIG_SPL_NO_BSS_LIMIT=y
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_GPT=y
 CONFIG_CMD_I2C=y
diff --git a/configs/porter_defconfig b/configs/porter_defconfig
index cb18024da12..ea894b09e39 100644
--- a/configs/porter_defconfig
+++ b/configs/porter_defconfig
@@ -14,6 +14,7 @@ CONFIG_ARCH_RENESAS_BOARD_STRING="Porter"
 CONFIG_R8A7791=y
 CONFIG_TARGET_PORTER=y
 CONFIG_SPL_SERIAL=y
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_STACK=0xe6340000
 CONFIG_SPL_SYS_MALLOC_F_LEN=0x2000
 CONFIG_SPL=y
diff --git a/configs/pxm2_defconfig b/configs/pxm2_defconfig
index 162b1f1c748..fd2727e48d7 100644
--- a/configs/pxm2_defconfig
+++ b/configs/pxm2_defconfig
@@ -85,6 +85,7 @@ CONFIG_SPL_DM=y
 # CONFIG_SPL_BLK is not set
 CONFIG_BOOTCOUNT_LIMIT=y
 CONFIG_BOOTCOUNT_ENV=y
+CONFIG_BOOTCOUNT_ALTBOOTCMD="run bootcmd"
 CONFIG_DFU_NAND=y
 CONFIG_SYS_DFU_DATA_BUF_SIZE=0x100000
 CONFIG_DM_I2C=y
diff --git a/configs/qc750_defconfig b/configs/qc750_defconfig
index 2485e64a2f0..a42860dc9ba 100644
--- a/configs/qc750_defconfig
+++ b/configs/qc750_defconfig
@@ -22,11 +22,12 @@ CONFIG_AUTOBOOT_KEYED=y
 CONFIG_AUTOBOOT_KEYED_CTRLC=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_SYSTEM_SETUP=y
-CONFIG_BOOTCOMMAND="bootflow scan; poweroff"
+CONFIG_BOOTCOMMAND="bootflow scan; echo 'Boot configuration not found... Power off in 3 sec'; sleep 3; poweroff"
 CONFIG_SYS_PBSIZE=2084
 CONFIG_SPL_FOOTPRINT_LIMIT=y
 CONFIG_SPL_MAX_FOOTPRINT=0x8000
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_SYS_MALLOC=y
 CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
 CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x80090000
diff --git a/configs/qcom_defconfig b/configs/qcom_defconfig
index 661a484f7bf..ba4d38d100e 100644
--- a/configs/qcom_defconfig
+++ b/configs/qcom_defconfig
@@ -97,6 +97,7 @@ CONFIG_PINCTRL_QCOM_APQ8016=y
 CONFIG_PINCTRL_QCOM_APQ8096=y
 CONFIG_PINCTRL_QCOM_QCM2290=y
 CONFIG_PINCTRL_QCOM_QCS404=y
+CONFIG_PINCTRL_QCOM_SC7280=y
 CONFIG_PINCTRL_QCOM_SDM845=y
 CONFIG_PINCTRL_QCOM_SM6115=y
 CONFIG_PINCTRL_QCOM_SM8150=y
@@ -120,6 +121,7 @@ CONFIG_QCOM_RPMH=y
 CONFIG_SPMI_MSM=y
 CONFIG_SYSINFO=y
 CONFIG_SYSINFO_SMBIOS=y
+CONFIG_SYSRESET_QCOM_PSHOLD=y
 CONFIG_USB=y
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
diff --git a/configs/qcom_ipq9574_mmc_defconfig b/configs/qcom_ipq9574_mmc_defconfig
new file mode 100644
index 00000000000..9bc1e1c70b7
--- /dev/null
+++ b/configs/qcom_ipq9574_mmc_defconfig
@@ -0,0 +1,83 @@
+CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_POSITION_INDEPENDENT=y
+CONFIG_SYS_INIT_SP_BSS_OFFSET=1572864
+CONFIG_ARCH_SNAPDRAGON=y
+CONFIG_NR_DRAM_BANKS=24
+CONFIG_DEFAULT_DEVICE_TREE="qcom/ipq9574-rdp433"
+CONFIG_SYS_LOAD_ADDR=0x50000000
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+# CONFIG_EFI_LOADER is not set
+# CONFIG_EFI_BINARY_EXEC is not set
+# CONFIG_EFI_VARIABLE_FILE_STORE is not set
+# CONFIG_PXE_UTILS is not set
+# CONFIG_BOOTSTD is not set
+# CONFIG_BOOTMETH_VBE is not set
+CONFIG_BOOTDELAY=2
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_USE_PREBOOT=y
+CONFIG_SYS_CBSIZE=512
+CONFIG_LOG_MAX_LEVEL=9
+CONFIG_LOG_DEFAULT_LEVEL=4
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_PART=y
+CONFIG_OF_LIVE=y
+CONFIG_USE_DEFAULT_ENV_FILE=y
+CONFIG_DEFAULT_ENV_FILE="board/qualcomm/default.env"
+CONFIG_CLK=y
+CONFIG_CLK_QCOM_IPQ9574=y
+CONFIG_DFU_MMC=y
+CONFIG_DFU_SCSI=y
+CONFIG_SYS_DFU_DATA_BUF_SIZE=0x200000
+CONFIG_MSM_GPIO=y
+CONFIG_PINCTRL=y
+CONFIG_PINCONF=y
+CONFIG_PINCTRL_QCOM_IPQ9574=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_ADMA=y
+CONFIG_MMC_SDHCI_MSM=y
+CONFIG_DM_MDIO=y
+CONFIG_DM_ETH_PHY=y
+CONFIG_DWC_ETH_QOS=y
+CONFIG_DWC_ETH_QOS_QCOM=y
+CONFIG_RGMII=y
+CONFIG_PHY=y
+CONFIG_PHY_QCOM_QMP_UFS=y
+CONFIG_PHY_QCOM_QUSB2=y
+CONFIG_SCSI=y
+CONFIG_MSM_SERIAL=y
+CONFIG_MSM_GENI_SERIAL=y
+CONFIG_SOC_QCOM=y
+CONFIG_DEBUG_UART=y
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_DEBUG_UART_BASE=0x78b1000
+CONFIG_DEBUG_UART_MSM=y
+CONFIG_DEBUG_UART_CLOCK=1843200
+CONFIG_TEXT_BASE=0x4A240000
+CONFIG_REMAKE_ELF=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_BOOTSTD_FULL=y
+CONFIG_SYS_CBSIZE=1024
+CONFIG_SYS_PBSIZE=1024
+CONFIG_OF_LIVE=y
+CONFIG_MSM_SERIAL=y
+CONFIG_DM_EVENT=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_ENV_SIZE=0x40000
+CONFIG_ENV_OFFSET=0
+CONFIG_PARTITIONS=y
+CONFIG_PARTITION_UUIDS=y
+CONFIG_MTD=y
+CONFIG_MTD_PARTS=y
+CONFIG_HUSH_PARSER=y
+CONFIG_PARTITIONS=y
+CONFIG_EFI_PARTITION=y
+# CONFIG_I2C is not set
+# CONFIG_INPUT is not set
+# CONFIG_SCSI is not set
+# CONFIG_SPMI is not set
diff --git a/configs/qemu-x86_64_defconfig b/configs/qemu-x86_64_defconfig
index 662f9718419..58b1fbf132d 100644
--- a/configs/qemu-x86_64_defconfig
+++ b/configs/qemu-x86_64_defconfig
@@ -1,12 +1,13 @@
 CONFIG_X86=y
 CONFIG_TEXT_BASE=0x1110000
-CONFIG_SYS_MALLOC_F_LEN=0x1000
+CONFIG_SYS_MALLOC_F_LEN=0x1800
+CONFIG_BLOBLIST_SIZE_RELOC=0x40000
 CONFIG_NR_DRAM_BANKS=8
 CONFIG_ENV_SIZE=0x40000
 CONFIG_MAX_CPUS=2
 CONFIG_SPL_DM_SPI=y
 CONFIG_DEFAULT_DEVICE_TREE="qemu-x86_i440fx"
-CONFIG_SPL_SYS_MALLOC_F_LEN=0x3000
+CONFIG_SPL_SYS_MALLOC_F_LEN=0x4800
 CONFIG_SPL_TEXT_BASE=0xfffd0000
 CONFIG_DEBUG_UART_BASE=0x3f8
 CONFIG_DEBUG_UART_CLOCK=1843200
@@ -33,14 +34,14 @@ CONFIG_LOGF_FUNC=y
 CONFIG_SPL_LOG=y
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_PCI_INIT_R=y
-# CONFIG_BLOBLIST is not set
+CONFIG_BLOBLIST=y
+CONFIG_BLOBLIST_FIXED=y
+CONFIG_BLOBLIST_ADDR=0x10000
 CONFIG_SPL_NO_BSS_LIMIT=y
 CONFIG_SPL_BOARD_INIT=y
 CONFIG_SPL_SYS_MALLOC_SIMPLE=y
 CONFIG_SPL_CPU=y
-CONFIG_SPL_ENV_SUPPORT=y
 CONFIG_SPL_DM_SPI_FLASH=y
-CONFIG_SPL_NET=y
 CONFIG_SPL_PCI=y
 CONFIG_SPL_PCH=y
 CONFIG_SPL_RTC=y
@@ -51,6 +52,7 @@ CONFIG_CMD_MEM_SEARCH=y
 CONFIG_CMD_IDE=y
 CONFIG_CMD_SPI=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_CAT=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_BOOTP_BOOTFILESIZE=y
 CONFIG_CMD_EFIDEBUG=y
@@ -58,6 +60,9 @@ CONFIG_CMD_TIME=y
 CONFIG_CMD_BOOTSTAGE=y
 CONFIG_CMD_EXT4_WRITE=y
 CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_FAT=y
+CONFIG_ENV_FAT_INTERFACE="virtio"
+CONFIG_ENV_FAT_DEVICE_AND_PART="0:1"
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_USE_BOOTFILE=y
 CONFIG_BOOTFILE="bzImage"
@@ -80,11 +85,11 @@ CONFIG_SYS_NS16550_PORT_MAPPED=y
 CONFIG_SPI=y
 CONFIG_USB_KEYBOARD=y
 CONFIG_CONSOLE_TRUETYPE=y
-CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
-CONFIG_FRAMEBUFFER_VESA_MODE_USER=y
-CONFIG_FRAMEBUFFER_VESA_MODE=0x144
+CONFIG_VIDEO_BOCHS=y
+# CONFIG_VIDEO_VESA is not set
 CONFIG_CONSOLE_SCROLL_LINES=5
 CONFIG_SPL_VIDEO=y
 # CONFIG_SPL_USE_TINY_PRINTF is not set
 CONFIG_GENERATE_ACPI_TABLE=y
+CONFIG_CMD_DHRYSTONE=y
 # CONFIG_GZIP is not set
diff --git a/configs/qemu-x86_defconfig b/configs/qemu-x86_defconfig
index 9948fa6d716..099d3f32d1b 100644
--- a/configs/qemu-x86_defconfig
+++ b/configs/qemu-x86_defconfig
@@ -1,6 +1,7 @@
 CONFIG_X86=y
 CONFIG_TEXT_BASE=0xFFF00000
 CONFIG_SYS_MALLOC_F_LEN=0x1000
+CONFIG_BLOBLIST_SIZE_RELOC=0x40000
 CONFIG_NR_DRAM_BANKS=8
 CONFIG_ENV_SIZE=0x40000
 CONFIG_MAX_CPUS=2
@@ -23,7 +24,9 @@ CONFIG_LOG=y
 CONFIG_LOGF_FUNC=y
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_PCI_INIT_R=y
-# CONFIG_BLOBLIST is not set
+CONFIG_BLOBLIST=y
+CONFIG_BLOBLIST_FIXED=y
+CONFIG_BLOBLIST_ADDR=0x10000
 CONFIG_CMD_CPU=y
 CONFIG_CMD_BOOTEFI_SELFTEST=y
 CONFIG_CMD_NVEDIT_EFI=y
@@ -31,6 +34,7 @@ CONFIG_CMD_MEM_SEARCH=y
 CONFIG_CMD_IDE=y
 CONFIG_CMD_SPI=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_CAT=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_BOOTP_BOOTFILESIZE=y
 CONFIG_CMD_EFIDEBUG=y
@@ -39,6 +43,9 @@ CONFIG_CMD_BOOTSTAGE=y
 CONFIG_CMD_EXT4_WRITE=y
 CONFIG_MAC_PARTITION=y
 CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_FAT=y
+CONFIG_ENV_FAT_INTERFACE="virtio"
+CONFIG_ENV_FAT_DEVICE_AND_PART="0:1"
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_USE_BOOTFILE=y
 CONFIG_BOOTFILE="bzImage"
@@ -59,9 +66,9 @@ CONFIG_SYS_NS16550_PORT_MAPPED=y
 CONFIG_SPI=y
 CONFIG_USB_KEYBOARD=y
 CONFIG_CONSOLE_TRUETYPE=y
-CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
-CONFIG_FRAMEBUFFER_VESA_MODE_USER=y
-CONFIG_FRAMEBUFFER_VESA_MODE=0x144
+CONFIG_VIDEO_BOCHS=y
+# CONFIG_VIDEO_VESA is not set
 CONFIG_CONSOLE_SCROLL_LINES=5
 CONFIG_GENERATE_ACPI_TABLE=y
+CONFIG_CMD_DHRYSTONE=y
 # CONFIG_GZIP is not set
diff --git a/configs/qemu_arm64_lwip_defconfig b/configs/qemu_arm64_lwip_defconfig
index 754c770c33f..814e98729a3 100644
--- a/configs/qemu_arm64_lwip_defconfig
+++ b/configs/qemu_arm64_lwip_defconfig
@@ -8,3 +8,4 @@ CONFIG_CMD_DNS=y
 CONFIG_CMD_WGET=y
 CONFIG_EFI_HTTP_BOOT=y
 CONFIG_WGET_HTTPS=y
+CONFIG_WGET_CACERT=y
diff --git a/configs/r8a77970_eagle_defconfig b/configs/r8a77970_eagle_defconfig
index 4534b17adc1..0a03e6d0d9d 100644
--- a/configs/r8a77970_eagle_defconfig
+++ b/configs/r8a77970_eagle_defconfig
@@ -13,6 +13,7 @@ CONFIG_ENV_SECT_SIZE=0x40000
 CONFIG_DEFAULT_DEVICE_TREE="renesas/r8a77970-eagle"
 CONFIG_SPL_TEXT_BASE=0xe6318000
 CONFIG_TARGET_EAGLE=y
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_STACK=0xe6304000
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
 CONFIG_SPL_BSS_START_ADDR=0xe631f000
diff --git a/configs/r8a77970_v3msk_defconfig b/configs/r8a77970_v3msk_defconfig
index 4a146e1c859..96a5b81ed20 100644
--- a/configs/r8a77970_v3msk_defconfig
+++ b/configs/r8a77970_v3msk_defconfig
@@ -14,6 +14,7 @@ CONFIG_DEFAULT_DEVICE_TREE="renesas/r8a77970-v3msk"
 CONFIG_SPL_TEXT_BASE=0xe6318000
 CONFIG_R8A77970=y
 CONFIG_TARGET_V3MSK=y
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_STACK=0xe6304000
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
 CONFIG_SPL_BSS_START_ADDR=0xe631f000
diff --git a/configs/r8a77980_condor_defconfig b/configs/r8a77980_condor_defconfig
index 9cf93d7dab2..d46548256d7 100644
--- a/configs/r8a77980_condor_defconfig
+++ b/configs/r8a77980_condor_defconfig
@@ -12,6 +12,7 @@ CONFIG_ENV_SECT_SIZE=0x40000
 CONFIG_DEFAULT_DEVICE_TREE="renesas/r8a77980-condor"
 CONFIG_SPL_TEXT_BASE=0xe6318000
 CONFIG_TARGET_CONDOR=y
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_STACK=0xe6304000
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
 CONFIG_SPL_BSS_START_ADDR=0xe631f000
diff --git a/configs/r8a77980_v3hsk_defconfig b/configs/r8a77980_v3hsk_defconfig
index d17720789e7..51e8d2bd368 100644
--- a/configs/r8a77980_v3hsk_defconfig
+++ b/configs/r8a77980_v3hsk_defconfig
@@ -13,6 +13,7 @@ CONFIG_DEFAULT_DEVICE_TREE="renesas/r8a77980-v3hsk"
 CONFIG_SPL_TEXT_BASE=0xe6318000
 CONFIG_R8A77980=y
 CONFIG_TARGET_V3HSK=y
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_STACK=0xe6304000
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
 CONFIG_SPL_BSS_START_ADDR=0xe631f000
diff --git a/configs/r8a77990_ebisu_defconfig b/configs/r8a77990_ebisu_defconfig
index da93d442532..e7f63110420 100644
--- a/configs/r8a77990_ebisu_defconfig
+++ b/configs/r8a77990_ebisu_defconfig
@@ -12,6 +12,7 @@ CONFIG_ENV_OFFSET=0xFFFE0000
 CONFIG_DEFAULT_DEVICE_TREE="renesas/r8a77990-ebisu"
 CONFIG_SPL_TEXT_BASE=0xe6318000
 CONFIG_TARGET_EBISU=y
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_STACK=0xe6304000
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
 CONFIG_SPL_BSS_START_ADDR=0xe631f000
diff --git a/configs/r8a77995_draak_defconfig b/configs/r8a77995_draak_defconfig
index 0fe5be6b723..afabe788c45 100644
--- a/configs/r8a77995_draak_defconfig
+++ b/configs/r8a77995_draak_defconfig
@@ -12,6 +12,7 @@ CONFIG_ENV_OFFSET=0xFFFE0000
 CONFIG_DEFAULT_DEVICE_TREE="renesas/r8a77995-draak"
 CONFIG_SPL_TEXT_BASE=0xe6318000
 CONFIG_TARGET_DRAAK=y
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_STACK=0xe6304000
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
 CONFIG_SPL_BSS_START_ADDR=0xe631f000
diff --git a/configs/rcar3_salvator-x_defconfig b/configs/rcar3_salvator-x_defconfig
index 6b095f63549..35904f19152 100644
--- a/configs/rcar3_salvator-x_defconfig
+++ b/configs/rcar3_salvator-x_defconfig
@@ -10,6 +10,7 @@ CONFIG_ENV_OFFSET=0xFFFE0000
 CONFIG_DEFAULT_DEVICE_TREE="renesas/r8a77951-salvator-x"
 CONFIG_SPL_TEXT_BASE=0xe6338000
 CONFIG_TARGET_SALVATOR_X=y
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_STACK=0xe6304000
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
 CONFIG_SPL_BSS_START_ADDR=0xe633f000
@@ -28,6 +29,8 @@ CONFIG_CMD_DFU=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_PCI=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_DM_USB_GADGET=y
 CONFIG_OF_LIST="renesas/r8a77951-salvator-x renesas/r8a77960-salvator-x renesas/r8a77965-salvator-x"
 CONFIG_MULTI_DTB_FIT_LZO=y
 CONFIG_MULTI_DTB_FIT_USER_DEFINED_AREA=y
@@ -74,4 +77,10 @@ CONFIG_USB=y
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="Renesas"
+CONFIG_USB_GADGET_VENDOR_NUM=0x045b
+CONFIG_USB_GADGET_PRODUCT_NUM=0x023c
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_RENESAS_USBHS=y
 CONFIG_USB_STORAGE=y
diff --git a/configs/rcar3_ulcb_defconfig b/configs/rcar3_ulcb_defconfig
index 7ffa115cc76..52f7d8701dd 100644
--- a/configs/rcar3_ulcb_defconfig
+++ b/configs/rcar3_ulcb_defconfig
@@ -11,6 +11,7 @@ CONFIG_ENV_OFFSET=0xFFFE0000
 CONFIG_DEFAULT_DEVICE_TREE="renesas/r8a77951-ulcb"
 CONFIG_SPL_TEXT_BASE=0xe6338000
 CONFIG_TARGET_ULCB=y
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_STACK=0xe6304000
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
 CONFIG_SPL_BSS_START_ADDR=0xe633f000
diff --git a/configs/renesas_rzg2l_smarc_defconfig b/configs/renesas_rzg2l_smarc_defconfig
index 7a1224b3f07..b1d970b6b7e 100644
--- a/configs/renesas_rzg2l_smarc_defconfig
+++ b/configs/renesas_rzg2l_smarc_defconfig
@@ -26,6 +26,7 @@ CONFIG_CMD_GPIO=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_PART=y
+CONFIG_CMD_USB=y
 CONFIG_CMD_PMIC=y
 CONFIG_CMD_EXT2=y
 CONFIG_CMD_EXT4=y
@@ -54,5 +55,12 @@ CONFIG_PMIC_RAA215300=y
 CONFIG_DM_REGULATOR=y
 CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_RESET_RZG2L_USBPHY_CTRL=y
 CONFIG_SYSRESET=y
 CONFIG_SYSRESET_RAA215300=y
+CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_GENERIC=y
+CONFIG_USB_STORAGE=y
diff --git a/configs/rock-pi-n8-rk3288_defconfig b/configs/rock-pi-n8-rk3288_defconfig
index dde0b81eee4..eb642b012fc 100644
--- a/configs/rock-pi-n8-rk3288_defconfig
+++ b/configs/rock-pi-n8-rk3288_defconfig
@@ -31,6 +31,7 @@ CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_SPL_PAD_TO=0x7f8000
 CONFIG_SPL_NO_BSS_LIMIT=y
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_CMD_SPL=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_GPT=y
diff --git a/configs/rock2_defconfig b/configs/rock2_defconfig
index bff65d1fc41..ccef4e39955 100644
--- a/configs/rock2_defconfig
+++ b/configs/rock2_defconfig
@@ -32,6 +32,7 @@ CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_SPL_PAD_TO=0x7f8000
 CONFIG_SPL_NO_BSS_LIMIT=y
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_GPT=y
 CONFIG_CMD_I2C=y
diff --git a/configs/rock_defconfig b/configs/rock_defconfig
index 9c05bf45146..8243948d540 100644
--- a/configs/rock_defconfig
+++ b/configs/rock_defconfig
@@ -32,6 +32,7 @@ CONFIG_SPL_MAX_SIZE=0x7800
 CONFIG_SPL_PAD_TO=0x7f8000
 CONFIG_SPL_NO_BSS_LIMIT=y
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SPI=y
diff --git a/configs/rut_defconfig b/configs/rut_defconfig
index dd8df542aa3..b2930e8044d 100644
--- a/configs/rut_defconfig
+++ b/configs/rut_defconfig
@@ -86,6 +86,7 @@ CONFIG_SPL_DM=y
 # CONFIG_SPL_BLK is not set
 CONFIG_BOOTCOUNT_LIMIT=y
 CONFIG_BOOTCOUNT_ENV=y
+CONFIG_BOOTCOUNT_ALTBOOTCMD="run bootcmd"
 CONFIG_DFU_NAND=y
 CONFIG_SYS_DFU_DATA_BUF_SIZE=0x100000
 CONFIG_DM_I2C=y
diff --git a/configs/sama5d27_giantboard_defconfig b/configs/sama5d27_giantboard_defconfig
index bedd4f0baee..0b7940f4fb4 100644
--- a/configs/sama5d27_giantboard_defconfig
+++ b/configs/sama5d27_giantboard_defconfig
@@ -49,6 +49,7 @@ CONFIG_SYS_PBSIZE=276
 CONFIG_MISC_INIT_R=y
 CONFIG_SPL_MAX_SIZE=0x10000
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_SYS_MALLOC=y
 CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
 CONFIG_HUSH_PARSER=y
diff --git a/configs/sama5d27_som1_ek_mmc1_defconfig b/configs/sama5d27_som1_ek_mmc1_defconfig
index aceecf0b74a..2e5a4acf27d 100644
--- a/configs/sama5d27_som1_ek_mmc1_defconfig
+++ b/configs/sama5d27_som1_ek_mmc1_defconfig
@@ -46,6 +46,7 @@ CONFIG_SYS_PBSIZE=276
 CONFIG_MISC_INIT_R=y
 CONFIG_SPL_MAX_SIZE=0x10000
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_SYS_MALLOC=y
 CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
 CONFIG_HUSH_PARSER=y
diff --git a/configs/sama5d27_som1_ek_mmc_defconfig b/configs/sama5d27_som1_ek_mmc_defconfig
index 9e63401a769..11a536d714c 100644
--- a/configs/sama5d27_som1_ek_mmc_defconfig
+++ b/configs/sama5d27_som1_ek_mmc_defconfig
@@ -47,6 +47,7 @@ CONFIG_SYS_PBSIZE=276
 CONFIG_MISC_INIT_R=y
 CONFIG_SPL_MAX_SIZE=0x10000
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_SYS_MALLOC=y
 CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
 CONFIG_HUSH_PARSER=y
diff --git a/configs/sama5d27_som1_ek_qspiflash_defconfig b/configs/sama5d27_som1_ek_qspiflash_defconfig
index 92a0891f687..86cb5c287be 100644
--- a/configs/sama5d27_som1_ek_qspiflash_defconfig
+++ b/configs/sama5d27_som1_ek_qspiflash_defconfig
@@ -45,6 +45,7 @@ CONFIG_SYS_PBSIZE=276
 CONFIG_MISC_INIT_R=y
 CONFIG_SPL_MAX_SIZE=0x10000
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_SYS_MALLOC=y
 CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
 CONFIG_HUSH_PARSER=y
diff --git a/configs/sama5d27_wlsom1_ek_mmc_defconfig b/configs/sama5d27_wlsom1_ek_mmc_defconfig
index 378a8af2081..014f0093eee 100644
--- a/configs/sama5d27_wlsom1_ek_mmc_defconfig
+++ b/configs/sama5d27_wlsom1_ek_mmc_defconfig
@@ -48,6 +48,7 @@ CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_MISC_INIT_R=y
 CONFIG_SPL_MAX_SIZE=0x10000
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_SYS_MALLOC=y
 CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
 CONFIG_SPL_DISPLAY_PRINT=y
diff --git a/configs/sama5d27_wlsom1_ek_qspiflash_defconfig b/configs/sama5d27_wlsom1_ek_qspiflash_defconfig
index 6b75825a13e..efe23115f62 100644
--- a/configs/sama5d27_wlsom1_ek_qspiflash_defconfig
+++ b/configs/sama5d27_wlsom1_ek_qspiflash_defconfig
@@ -48,6 +48,7 @@ CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_MISC_INIT_R=y
 CONFIG_SPL_MAX_SIZE=0x10000
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_SYS_MALLOC=y
 CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
 CONFIG_SPL_DISPLAY_PRINT=y
diff --git a/configs/sama5d2_icp_mmc_defconfig b/configs/sama5d2_icp_mmc_defconfig
index 5e8b9b975e4..c27b181f19e 100644
--- a/configs/sama5d2_icp_mmc_defconfig
+++ b/configs/sama5d2_icp_mmc_defconfig
@@ -48,6 +48,7 @@ CONFIG_MISC_INIT_R=y
 CONFIG_SPL_MAX_SIZE=0x10000
 CONFIG_SPL_SYS_MALLOC_SIMPLE=y
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_SYS_MALLOC=y
 CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
 CONFIG_SPL_DISPLAY_PRINT=y
diff --git a/configs/sama5d2_xplained_emmc_defconfig b/configs/sama5d2_xplained_emmc_defconfig
index 736a6eeaf87..76187ea52ab 100644
--- a/configs/sama5d2_xplained_emmc_defconfig
+++ b/configs/sama5d2_xplained_emmc_defconfig
@@ -45,6 +45,7 @@ CONFIG_SYS_PBSIZE=276
 # CONFIG_DISPLAY_BOARDINFO is not set
 CONFIG_SPL_MAX_SIZE=0x10000
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_SYS_MALLOC=y
 CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
 CONFIG_HUSH_PARSER=y
diff --git a/configs/sama5d2_xplained_mmc_defconfig b/configs/sama5d2_xplained_mmc_defconfig
index 6fd1075ebdc..e752863f5e1 100644
--- a/configs/sama5d2_xplained_mmc_defconfig
+++ b/configs/sama5d2_xplained_mmc_defconfig
@@ -47,6 +47,7 @@ CONFIG_SYS_PBSIZE=276
 CONFIG_MISC_INIT_R=y
 CONFIG_SPL_MAX_SIZE=0x10000
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_SYS_MALLOC=y
 CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
 CONFIG_HUSH_PARSER=y
diff --git a/configs/sama5d2_xplained_qspiflash_defconfig b/configs/sama5d2_xplained_qspiflash_defconfig
index 4c30e9daa40..4b5a3c11a8e 100644
--- a/configs/sama5d2_xplained_qspiflash_defconfig
+++ b/configs/sama5d2_xplained_qspiflash_defconfig
@@ -48,6 +48,7 @@ CONFIG_SYS_PBSIZE=276
 CONFIG_MISC_INIT_R=y
 CONFIG_SPL_MAX_SIZE=0x10000
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_SYS_MALLOC=y
 CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
 CONFIG_HUSH_PARSER=y
diff --git a/configs/sama5d2_xplained_spiflash_defconfig b/configs/sama5d2_xplained_spiflash_defconfig
index 9431ff1caac..8941d8fb582 100644
--- a/configs/sama5d2_xplained_spiflash_defconfig
+++ b/configs/sama5d2_xplained_spiflash_defconfig
@@ -49,6 +49,7 @@ CONFIG_SYS_PBSIZE=276
 CONFIG_MISC_INIT_R=y
 CONFIG_SPL_MAX_SIZE=0x10000
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_SYS_MALLOC=y
 CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
 CONFIG_SPL_DM_SPI_FLASH=y
diff --git a/configs/sama5d3_xplained_mmc_defconfig b/configs/sama5d3_xplained_mmc_defconfig
index 0050d95188e..984d8146992 100644
--- a/configs/sama5d3_xplained_mmc_defconfig
+++ b/configs/sama5d3_xplained_mmc_defconfig
@@ -44,6 +44,7 @@ CONFIG_SYS_PBSIZE=276
 # CONFIG_DISPLAY_BOARDINFO is not set
 CONFIG_SPL_MAX_SIZE=0x18000
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_SYS_MALLOC=y
 CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
 CONFIG_HUSH_PARSER=y
diff --git a/configs/sama5d3_xplained_nandflash_defconfig b/configs/sama5d3_xplained_nandflash_defconfig
index 6a66637a9dc..0e3eb7d7b01 100644
--- a/configs/sama5d3_xplained_nandflash_defconfig
+++ b/configs/sama5d3_xplained_nandflash_defconfig
@@ -41,6 +41,7 @@ CONFIG_SYS_PBSIZE=276
 # CONFIG_DISPLAY_BOARDINFO is not set
 CONFIG_SPL_MAX_SIZE=0x18000
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_SYS_MALLOC=y
 CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
 CONFIG_SPL_NAND_SUPPORT=y
diff --git a/configs/sama5d3xek_mmc_defconfig b/configs/sama5d3xek_mmc_defconfig
index 4c7914673bf..9d0472dea2a 100644
--- a/configs/sama5d3xek_mmc_defconfig
+++ b/configs/sama5d3xek_mmc_defconfig
@@ -46,6 +46,7 @@ CONFIG_SYS_CONSOLE_IS_IN_ENV=y
 # CONFIG_DISPLAY_BOARDINFO is not set
 CONFIG_SPL_MAX_SIZE=0x18000
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_SYS_MALLOC=y
 CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
 CONFIG_HUSH_PARSER=y
diff --git a/configs/sama5d3xek_nandflash_defconfig b/configs/sama5d3xek_nandflash_defconfig
index 985a152ea42..995c9de1c80 100644
--- a/configs/sama5d3xek_nandflash_defconfig
+++ b/configs/sama5d3xek_nandflash_defconfig
@@ -43,6 +43,7 @@ CONFIG_SYS_CONSOLE_IS_IN_ENV=y
 # CONFIG_DISPLAY_BOARDINFO is not set
 CONFIG_SPL_MAX_SIZE=0x18000
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_SYS_MALLOC=y
 CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
 CONFIG_SPL_NAND_SUPPORT=y
diff --git a/configs/sama5d3xek_spiflash_defconfig b/configs/sama5d3xek_spiflash_defconfig
index 3f2bd734638..cccdd8e970e 100644
--- a/configs/sama5d3xek_spiflash_defconfig
+++ b/configs/sama5d3xek_spiflash_defconfig
@@ -46,6 +46,7 @@ CONFIG_SYS_PBSIZE=276
 # CONFIG_DISPLAY_BOARDINFO is not set
 CONFIG_SPL_MAX_SIZE=0x18000
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_SYS_MALLOC=y
 CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
 CONFIG_SPL_DM_SPI_FLASH=y
diff --git a/configs/sama5d4_xplained_mmc_defconfig b/configs/sama5d4_xplained_mmc_defconfig
index f0c4356cc9e..c476a9c4230 100644
--- a/configs/sama5d4_xplained_mmc_defconfig
+++ b/configs/sama5d4_xplained_mmc_defconfig
@@ -46,6 +46,7 @@ CONFIG_SYS_PBSIZE=276
 CONFIG_MISC_INIT_R=y
 CONFIG_SPL_MAX_SIZE=0x18000
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_SYS_MALLOC=y
 CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
 CONFIG_HUSH_PARSER=y
diff --git a/configs/sama5d4_xplained_nandflash_defconfig b/configs/sama5d4_xplained_nandflash_defconfig
index 4d6ca43a6cb..5401f34adc6 100644
--- a/configs/sama5d4_xplained_nandflash_defconfig
+++ b/configs/sama5d4_xplained_nandflash_defconfig
@@ -43,6 +43,7 @@ CONFIG_SYS_PBSIZE=276
 CONFIG_MISC_INIT_R=y
 CONFIG_SPL_MAX_SIZE=0x18000
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_SYS_MALLOC=y
 CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
 CONFIG_SPL_NAND_SUPPORT=y
diff --git a/configs/sama5d4_xplained_spiflash_defconfig b/configs/sama5d4_xplained_spiflash_defconfig
index c0680fbcb0d..98ec4d75f83 100644
--- a/configs/sama5d4_xplained_spiflash_defconfig
+++ b/configs/sama5d4_xplained_spiflash_defconfig
@@ -48,6 +48,7 @@ CONFIG_SYS_PBSIZE=276
 CONFIG_MISC_INIT_R=y
 CONFIG_SPL_MAX_SIZE=0x18000
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_SYS_MALLOC=y
 CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
 CONFIG_SPL_DM_SPI_FLASH=y
diff --git a/configs/sama5d4ek_mmc_defconfig b/configs/sama5d4ek_mmc_defconfig
index 347ccb47c89..6e6e601aab4 100644
--- a/configs/sama5d4ek_mmc_defconfig
+++ b/configs/sama5d4ek_mmc_defconfig
@@ -46,6 +46,7 @@ CONFIG_SYS_CONSOLE_IS_IN_ENV=y
 # CONFIG_DISPLAY_BOARDINFO is not set
 CONFIG_SPL_MAX_SIZE=0x18000
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_SYS_MALLOC=y
 CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
 CONFIG_HUSH_PARSER=y
diff --git a/configs/sama5d4ek_nandflash_defconfig b/configs/sama5d4ek_nandflash_defconfig
index b309b87dc6b..b22e0dd18a3 100644
--- a/configs/sama5d4ek_nandflash_defconfig
+++ b/configs/sama5d4ek_nandflash_defconfig
@@ -43,6 +43,7 @@ CONFIG_SYS_CONSOLE_IS_IN_ENV=y
 # CONFIG_DISPLAY_BOARDINFO is not set
 CONFIG_SPL_MAX_SIZE=0x18000
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_SYS_MALLOC=y
 CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
 CONFIG_SPL_NAND_SUPPORT=y
diff --git a/configs/sama5d4ek_spiflash_defconfig b/configs/sama5d4ek_spiflash_defconfig
index 38edafc1879..60c11f38460 100644
--- a/configs/sama5d4ek_spiflash_defconfig
+++ b/configs/sama5d4ek_spiflash_defconfig
@@ -46,6 +46,7 @@ CONFIG_SYS_PBSIZE=276
 # CONFIG_DISPLAY_BOARDINFO is not set
 CONFIG_SPL_MAX_SIZE=0x18000
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_SYS_MALLOC=y
 CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
 CONFIG_SPL_DM_SPI_FLASH=y
diff --git a/configs/sandbox64_defconfig b/configs/sandbox64_defconfig
index 7960b2ef42e..1236ce474a6 100644
--- a/configs/sandbox64_defconfig
+++ b/configs/sandbox64_defconfig
@@ -267,6 +267,7 @@ CONFIG_WDT_SANDBOX=y
 CONFIG_WDT_ALARM_SANDBOX=y
 CONFIG_FS_CBFS=y
 CONFIG_FS_CRAMFS=y
+CONFIG_FS_EXFAT=y
 CONFIG_CMD_DHRYSTONE=y
 CONFIG_TPM=y
 CONFIG_ERRNO_STR=y
diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig
index 861a1f4cd90..87f21fdbd12 100644
--- a/configs/sandbox_defconfig
+++ b/configs/sandbox_defconfig
@@ -328,6 +328,8 @@ CONFIG_USB_ETH_CDC=y
 CONFIG_VIDEO=y
 CONFIG_VIDEO_FONT_SUN12X22=y
 CONFIG_VIDEO_COPY=y
+CONFIG_VIDEO_BRIDGE=y
+CONFIG_VIDEO_BRIDGE_LVDS_CODEC=y
 CONFIG_CONSOLE_ROTATION=y
 CONFIG_CONSOLE_TRUETYPE=y
 CONFIG_CONSOLE_TRUETYPE_CANTORAONE=y
@@ -350,6 +352,7 @@ CONFIG_WDT_ALARM_SANDBOX=y
 CONFIG_WDT_FTWDT010=y
 CONFIG_FS_CBFS=y
 CONFIG_FS_CRAMFS=y
+CONFIG_FS_EXFAT=y
 CONFIG_ADDR_MAP=y
 CONFIG_PANIC_HANG=y
 CONFIG_CMD_DHRYSTONE=y
diff --git a/configs/sandbox_vpl_defconfig b/configs/sandbox_vpl_defconfig
index 46329395ba5..e1a0555744c 100644
--- a/configs/sandbox_vpl_defconfig
+++ b/configs/sandbox_vpl_defconfig
@@ -149,6 +149,7 @@ CONFIG_SPL_FIRMWARE=y
 CONFIG_GPIO_HOG=y
 CONFIG_QCOM_PMIC_GPIO=y
 CONFIG_SANDBOX_GPIO=y
+CONFIG_TPL_DM_I2C=y
 CONFIG_I2C_CROS_EC_TUNNEL=y
 CONFIG_I2C_CROS_EC_LDO=y
 CONFIG_DM_I2C_GPIO=y
diff --git a/configs/seaboard_defconfig b/configs/seaboard_defconfig
index 090dc04112a..eeb911a7805 100644
--- a/configs/seaboard_defconfig
+++ b/configs/seaboard_defconfig
@@ -18,6 +18,7 @@ CONFIG_SYS_PBSIZE=2086
 CONFIG_SPL_FOOTPRINT_LIMIT=y
 CONFIG_SPL_MAX_FOOTPRINT=0x8000
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_SYS_MALLOC=y
 CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
 CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x90000
diff --git a/configs/sifive_unleashed_defconfig b/configs/sifive_unleashed_defconfig
index 96b6f482c4f..b1c4d00c05e 100644
--- a/configs/sifive_unleashed_defconfig
+++ b/configs/sifive_unleashed_defconfig
@@ -32,6 +32,7 @@ CONFIG_DISPLAY_BOARDINFO=y
 CONFIG_MISC_INIT_R=y
 CONFIG_SPL_MAX_SIZE=0x100000
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_SYS_MALLOC=y
 CONFIG_SPL_DM_SPI_FLASH=y
 CONFIG_SPL_DM_RESET=y
diff --git a/configs/sifive_unmatched_defconfig b/configs/sifive_unmatched_defconfig
index 4fed7eda948..f70e3db4441 100644
--- a/configs/sifive_unmatched_defconfig
+++ b/configs/sifive_unmatched_defconfig
@@ -27,7 +27,7 @@ CONFIG_FIT=y
 CONFIG_SPL_LOAD_FIT_ADDRESS=0x84000000
 CONFIG_BOOTSTD_DEFAULTS=y
 CONFIG_USE_PREBOOT=y
-CONFIG_PREBOOT="setenv fdt_addr ${fdtcontroladdr};fdt addr ${fdtcontroladdr};"
+CONFIG_PREBOOT="setenv fdt_addr ${fdtcontroladdr};fdt addr ${fdtcontroladdr};nvme scan"
 CONFIG_DEFAULT_FDT_FILE="sifive/hifive-unmatched-a00.dtb"
 CONFIG_SYS_CBSIZE=256
 CONFIG_SYS_PBSIZE=276
@@ -38,6 +38,7 @@ CONFIG_ID_EEPROM=y
 CONFIG_PCI_INIT_R=y
 CONFIG_SPL_MAX_SIZE=0x100000
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_SYS_MALLOC=y
 CONFIG_SPL_DM_SPI_FLASH=y
 CONFIG_SPL_DM_RESET=y
diff --git a/configs/silinux_ek874_defconfig b/configs/silinux_ek874_defconfig
index 031fdc02691..c9a44247a86 100644
--- a/configs/silinux_ek874_defconfig
+++ b/configs/silinux_ek874_defconfig
@@ -13,6 +13,7 @@ CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_DEFAULT_DEVICE_TREE="renesas/r8a774c0-ek874"
 CONFIG_SPL_TEXT_BASE=0xe6318000
 CONFIG_TARGET_SILINUX_EK874=y
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_STACK=0xe6304000
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
 CONFIG_SPL_BSS_START_ADDR=0xe631f000
diff --git a/configs/silk_defconfig b/configs/silk_defconfig
index 1c70a16bf5b..7a4b147b030 100644
--- a/configs/silk_defconfig
+++ b/configs/silk_defconfig
@@ -14,6 +14,7 @@ CONFIG_ARCH_RENESAS_BOARD_STRING="Silk"
 CONFIG_R8A7794=y
 CONFIG_TARGET_SILK=y
 CONFIG_SPL_SERIAL=y
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_STACK=0xe6340000
 CONFIG_SPL_SYS_MALLOC_F_LEN=0x2000
 CONFIG_SPL=y
diff --git a/configs/smartweb_defconfig b/configs/smartweb_defconfig
index aa8adf51181..7253c997b24 100644
--- a/configs/smartweb_defconfig
+++ b/configs/smartweb_defconfig
@@ -41,6 +41,7 @@ CONFIG_BOARD_EARLY_INIT_F=y
 CONFIG_SPL_MAX_SIZE=0x1000
 CONFIG_SPL_PAD_TO=0x20000
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_SYS_MALLOC=y
 CONFIG_SPL_SYS_MALLOC_SIZE=0x460000
 CONFIG_SPL_NAND_SUPPORT=y
diff --git a/configs/smegw01_defconfig b/configs/smegw01_defconfig
index 6dc95e551e3..ae6c9b60cd5 100644
--- a/configs/smegw01_defconfig
+++ b/configs/smegw01_defconfig
@@ -60,6 +60,7 @@ CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_BOUNCE_BUFFER=y
 CONFIG_BOOTCOUNT_LIMIT=y
 CONFIG_BOOTCOUNT_ENV=y
+CONFIG_BOOTCOUNT_ALTBOOTCMD="echo Performing rollback...; if test \"${mmcpart_committed}\" = 1; then setenv mmcpart 2; setenv mmcpart_committed 2; else setenv mmcpart 1; setenv mmcpart_committed 1; fi; setenv bootcount 0; setenv upgrade_available; setenv ustate 3; saveenv; run bootcmd;"
 CONFIG_DFU_MMC=y
 CONFIG_DM_I2C=y
 CONFIG_SUPPORT_EMMC_BOOT=y
diff --git a/configs/snow_defconfig b/configs/snow_defconfig
index 27698f5ef36..adf6213f70b 100644
--- a/configs/snow_defconfig
+++ b/configs/snow_defconfig
@@ -98,7 +98,6 @@ CONFIG_USB_HOST_ETHER=y
 CONFIG_USB_ETHER_ASIX88179=y
 CONFIG_VIDEO=y
 # CONFIG_VIDEO_BPP8 is not set
-CONFIG_VIDCONSOLE_AS_LCD=y
 CONFIG_DISPLAY=y
 CONFIG_VIDEO_EXYNOS=y
 CONFIG_EXYNOS_DP=y
diff --git a/configs/socfpga_agilex5_defconfig b/configs/socfpga_agilex5_defconfig
index 8577ac610c2..8f327e5f2ab 100644
--- a/configs/socfpga_agilex5_defconfig
+++ b/configs/socfpga_agilex5_defconfig
@@ -1,8 +1,7 @@
 CONFIG_ARM=y
 CONFIG_ARCH_SOCFPGA=y
 CONFIG_TEXT_BASE=0x80200000
-CONFIG_NR_DRAM_BANKS=2
-CONFIG_SPL_LDSCRIPT="arch/arm/mach-socfpga/u-boot-spl-soc64.lds"
+CONFIG_NR_DRAM_BANKS=3
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80300000
 CONFIG_SF_DEFAULT_MODE=0x2003
@@ -10,7 +9,7 @@ CONFIG_ENV_SIZE=0x2000
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="socfpga_agilex5_socdk"
 CONFIG_DM_RESET=y
-CONFIG_SPL_STACK=0x7f000
+CONFIG_SPL_STACK=0x7d000
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
 CONFIG_SPL_BSS_START_ADDR=0xbff00000
 CONFIG_SPL_BSS_MAX_SIZE=0x100000
@@ -18,6 +17,7 @@ CONFIG_SYS_LOAD_ADDR=0x82000000
 CONFIG_TARGET_SOCFPGA_AGILEX5_SOCDK=y
 CONFIG_IDENT_STRING="socfpga_agilex5"
 CONFIG_SPL_FS_FAT=y
+CONFIG_SPL_RECOVER_DATA_SECTION=y
 # CONFIG_EFI_LOADER is not set
 CONFIG_FIT=y
 CONFIG_SPL_FIT_SIGNATURE=y
@@ -29,10 +29,20 @@ CONFIG_QSPI_BOOT=y
 CONFIG_BOOTDELAY=5
 CONFIG_USE_BOOTARGS=y
 CONFIG_BOOTARGS="console=ttyS0,115200 initrd=0x90000000 root=/dev/ram0 rw init=/sbin/init ramdisk_size=10000000 earlycon panic=-1 nosmp kvm-arm.mode=nvhe"
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_BLOBLIST=y
+CONFIG_BLOBLIST_SIZE=0x1000
 CONFIG_SPL_MAX_SIZE=0x40000
+CONFIG_HANDOFF=y
 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
+CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0xbfa00000
+CONFIG_SPL_SYS_MALLOC_SIZE=0x500000
 CONFIG_SPL_CACHE=y
+CONFIG_SPL_MTD=y
 CONFIG_SPL_SPI_FLASH_MTD=y
 CONFIG_SPL_SPI_LOAD=y
 CONFIG_SYS_SPI_U_BOOT_OFFS=0x04000000
@@ -72,6 +82,7 @@ CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_SPI_FLASH_STMICRO=y
 # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
 CONFIG_SPI_FLASH_MTD=y
+CONFIG_DWC_ETH_XGMAC=y
 CONFIG_RGMII=y
 CONFIG_SYS_NS16550_MEM32=y
 CONFIG_SPI=y
@@ -82,9 +93,7 @@ CONFIG_DESIGNWARE_APB_TIMER=y
 CONFIG_USB=y
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_DWC2=y
-# CONFIG_WATCHDOG_AUTOSTART is not set
 CONFIG_DESIGNWARE_WATCHDOG=y
 CONFIG_WDT=y
 # CONFIG_SPL_USE_TINY_PRINTF is not set
 CONFIG_PANIC_HANG=y
-CONFIG_SPL_CRC32=y
diff --git a/configs/socfpga_agilex5_nand2_defconfig b/configs/socfpga_agilex5_nand2_defconfig
new file mode 100644
index 00000000000..c9c7077be91
--- /dev/null
+++ b/configs/socfpga_agilex5_nand2_defconfig
@@ -0,0 +1,31 @@
+#include <configs/socfpga_agilex5_defconfig>
+
+CONFIG_ARM=y
+CONFIG_ARCH_SOCFPGA=y
+CONFIG_DEFAULT_DEVICE_TREE="socfpga_agilex5_socdk"
+CONFIG_BOOTARGS="earlycon panic=-1 root=${nandroot} rw rootwait rootfstype=ubifs ubi.mtd=1"
+CONFIG_TARGET_SOCFPGA_AGILEX5_NAND2=y
+CONFIG_PHY_CADENCE_COMBOPHY=n
+CONFIG_SPL_PHY_CADENCE_COMBOPHY=n
+# CONFIG_MMC_DW is not set
+CONFIG_SPL_MTD=y
+CONFIG_CMD_NAND_TRIMFFS=y
+CONFIG_CMD_NAND_LOCK_UNLOCK=y
+CONFIG_SPL_MTD_SUPPORT=y
+CONFIG_MTDIDS_DEFAULT="nand0=10b80000.nand.0"
+CONFIG_MTDPARTS_DEFAULT="mtdparts=10b80000.nand.0:2m(u-boot),-(root)"
+CONFIG_CMD_UBIFS=y
+CONFIG_MTD_UBI=y
+CONFIG_MTD_UBI_WL_THRESHOLD=4096
+CONFIG_MTD_UBI_BEB_LIMIT=20
+CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
+CONFIG_SYS_NAND_U_BOOT_OFFS=0x0
+CONFIG_SYS_NAND_U_BOOT_OFFS_REDUND=0x100000
+CONFIG_UBI_SILENCE_MSG=y
+CONFIG_MTD_RAW_NAND=y
+CONFIG_NAND_CADENCE=y
+CONFIG_SPL_NAND_SUPPORT=y
+CONFIG_SPL_NAND_CADENCE=y
+CONFIG_SYS_NAND_ONFI_DETECTION=y
+CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
+CONFIG_SYS_NAND_PAGE_SIZE=0x800
diff --git a/configs/socfpga_agilex_atf_defconfig b/configs/socfpga_agilex_atf_defconfig
index 8c4f7072aa8..a2bd40d5dbd 100644
--- a/configs/socfpga_agilex_atf_defconfig
+++ b/configs/socfpga_agilex_atf_defconfig
@@ -36,6 +36,7 @@ CONFIG_BOOTCOMMAND="run fatscript; run mmcfitload; run mmcfitboot"
 CONFIG_SYS_PBSIZE=2082
 CONFIG_SPL_MAX_SIZE=0x40000
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_SYS_MALLOC=y
 CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
 CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x3fa00000
diff --git a/configs/socfpga_agilex_defconfig b/configs/socfpga_agilex_defconfig
index eaa2161a2f7..0b6194c1f27 100644
--- a/configs/socfpga_agilex_defconfig
+++ b/configs/socfpga_agilex_defconfig
@@ -34,6 +34,7 @@ CONFIG_BOOTCOMMAND="run fatscript; run mmcload; run linux_qspi_enable; run mmcbo
 CONFIG_SYS_PBSIZE=2082
 CONFIG_SPL_MAX_SIZE=0x40000
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_SYS_MALLOC=y
 CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
 CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x3fa00000
diff --git a/configs/socfpga_agilex_vab_defconfig b/configs/socfpga_agilex_vab_defconfig
index 2883480b30b..8eec3d8d67a 100644
--- a/configs/socfpga_agilex_vab_defconfig
+++ b/configs/socfpga_agilex_vab_defconfig
@@ -37,6 +37,7 @@ CONFIG_BOOTCOMMAND="run fatscript; run mmcfitload; run mmcfitboot"
 CONFIG_SYS_PBSIZE=2082
 CONFIG_SPL_MAX_SIZE=0x40000
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_SYS_MALLOC=y
 CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
 CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x3fa00000
diff --git a/configs/socfpga_arria10_defconfig b/configs/socfpga_arria10_defconfig
index 7b3b022d202..7c6a3c8d081 100644
--- a/configs/socfpga_arria10_defconfig
+++ b/configs/socfpga_arria10_defconfig
@@ -30,6 +30,7 @@ CONFIG_CLOCKS=y
 CONFIG_SPL_PAD_TO=0x40000
 CONFIG_SPL_NO_BSS_LIMIT=y
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_SYS_MALLOC=y
 CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
 CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0xffe2b000
diff --git a/configs/socfpga_arria5_defconfig b/configs/socfpga_arria5_defconfig
index 9185af22c61..f3c142300f2 100644
--- a/configs/socfpga_arria5_defconfig
+++ b/configs/socfpga_arria5_defconfig
@@ -26,6 +26,7 @@ CONFIG_CLOCKS=y
 CONFIG_SPL_PAD_TO=0x10000
 CONFIG_SPL_NO_BSS_LIMIT=y
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_SPI_LOAD=y
 CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000
 CONFIG_SYS_MAXARGS=32
diff --git a/configs/socfpga_cyclone5_defconfig b/configs/socfpga_cyclone5_defconfig
index 69a9909aa63..97e5fae0f53 100644
--- a/configs/socfpga_cyclone5_defconfig
+++ b/configs/socfpga_cyclone5_defconfig
@@ -26,6 +26,7 @@ CONFIG_CLOCKS=y
 CONFIG_SPL_PAD_TO=0x10000
 CONFIG_SPL_NO_BSS_LIMIT=y
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_SPI_LOAD=y
 CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000
 CONFIG_SYS_MAXARGS=32
diff --git a/configs/socfpga_dbm_soc1_defconfig b/configs/socfpga_dbm_soc1_defconfig
index 5b320e06b4b..69b04979423 100644
--- a/configs/socfpga_dbm_soc1_defconfig
+++ b/configs/socfpga_dbm_soc1_defconfig
@@ -29,6 +29,7 @@ CONFIG_CLOCKS=y
 CONFIG_SPL_PAD_TO=0x10000
 CONFIG_SPL_NO_BSS_LIMIT=y
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_SPI_LOAD=y
 CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000
 CONFIG_HUSH_PARSER=y
diff --git a/configs/socfpga_de0_nano_soc_defconfig b/configs/socfpga_de0_nano_soc_defconfig
index 04b051cea9a..7188c46d98e 100644
--- a/configs/socfpga_de0_nano_soc_defconfig
+++ b/configs/socfpga_de0_nano_soc_defconfig
@@ -27,6 +27,7 @@ CONFIG_SPL_PAD_TO=0x10000
 CONFIG_SPL_NO_BSS_LIMIT=y
 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_SPI_LOAD=y
 CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000
 CONFIG_SYS_MAXARGS=32
diff --git a/configs/socfpga_de10_nano_defconfig b/configs/socfpga_de10_nano_defconfig
index 703af3f9c21..102e781f5c1 100644
--- a/configs/socfpga_de10_nano_defconfig
+++ b/configs/socfpga_de10_nano_defconfig
@@ -26,6 +26,7 @@ CONFIG_CLOCKS=y
 CONFIG_SPL_PAD_TO=0x10000
 CONFIG_SPL_NO_BSS_LIMIT=y
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_SPI_LOAD=y
 CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000
 CONFIG_SYS_MAXARGS=32
diff --git a/configs/socfpga_de10_standard_defconfig b/configs/socfpga_de10_standard_defconfig
index 76c41b21cec..fe3eaad12a3 100644
--- a/configs/socfpga_de10_standard_defconfig
+++ b/configs/socfpga_de10_standard_defconfig
@@ -26,6 +26,7 @@ CONFIG_CLOCKS=y
 CONFIG_SPL_PAD_TO=0x10000
 CONFIG_SPL_NO_BSS_LIMIT=y
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_SPI_LOAD=y
 CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000
 CONFIG_SYS_MAXARGS=32
diff --git a/configs/socfpga_de1_soc_defconfig b/configs/socfpga_de1_soc_defconfig
index 8cb158a0150..19e4ab98d59 100644
--- a/configs/socfpga_de1_soc_defconfig
+++ b/configs/socfpga_de1_soc_defconfig
@@ -28,6 +28,7 @@ CONFIG_SPL_PAD_TO=0x10000
 CONFIG_SPL_NO_BSS_LIMIT=y
 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_YMODEM_SUPPORT=y
 CONFIG_SYS_MAXARGS=32
 CONFIG_CMD_ASKENV=y
diff --git a/configs/socfpga_is1_defconfig b/configs/socfpga_is1_defconfig
index bc40e4f3d21..38286f71f84 100644
--- a/configs/socfpga_is1_defconfig
+++ b/configs/socfpga_is1_defconfig
@@ -29,6 +29,7 @@ CONFIG_CLOCKS=y
 CONFIG_SPL_PAD_TO=0x10000
 CONFIG_SPL_NO_BSS_LIMIT=y
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_SPI_LOAD=y
 CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000
 CONFIG_SYS_MAXARGS=32
diff --git a/configs/socfpga_mcvevk_defconfig b/configs/socfpga_mcvevk_defconfig
index 7aa2db6def0..f61a63d835a 100644
--- a/configs/socfpga_mcvevk_defconfig
+++ b/configs/socfpga_mcvevk_defconfig
@@ -27,6 +27,7 @@ CONFIG_CLOCKS=y
 CONFIG_SPL_PAD_TO=0x10000
 CONFIG_SPL_NO_BSS_LIMIT=y
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_SPI_LOAD=y
 CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000
 CONFIG_SYS_MAXARGS=32
diff --git a/configs/socfpga_n5x_atf_defconfig b/configs/socfpga_n5x_atf_defconfig
index 5e927170f21..5bf431b4a18 100644
--- a/configs/socfpga_n5x_atf_defconfig
+++ b/configs/socfpga_n5x_atf_defconfig
@@ -35,6 +35,7 @@ CONFIG_BOOTCOMMAND="run fatscript; run mmcfitload; run mmcfitboot"
 CONFIG_SYS_PBSIZE=2079
 CONFIG_SPL_MAX_SIZE=0x40000
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_SYS_MALLOC=y
 CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
 CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x3fa00000
diff --git a/configs/socfpga_n5x_defconfig b/configs/socfpga_n5x_defconfig
index 593325c25c3..879556614f6 100644
--- a/configs/socfpga_n5x_defconfig
+++ b/configs/socfpga_n5x_defconfig
@@ -31,6 +31,7 @@ CONFIG_BOOTCOMMAND="run fatscript; run mmcload; run linux_qspi_enable; run mmcbo
 CONFIG_SYS_PBSIZE=2079
 CONFIG_SPL_MAX_SIZE=0x40000
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_SYS_MALLOC=y
 CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
 CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x3fa00000
diff --git a/configs/socfpga_n5x_vab_defconfig b/configs/socfpga_n5x_vab_defconfig
index e3d52fe02e6..c0dc8558153 100644
--- a/configs/socfpga_n5x_vab_defconfig
+++ b/configs/socfpga_n5x_vab_defconfig
@@ -36,6 +36,7 @@ CONFIG_BOOTCOMMAND="run fatscript; run mmcfitload; run mmcfitboot"
 CONFIG_SYS_PBSIZE=2079
 CONFIG_SPL_MAX_SIZE=0x40000
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_SYS_MALLOC=y
 CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
 CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x3fa00000
diff --git a/configs/socfpga_secu1_defconfig b/configs/socfpga_secu1_defconfig
index dc6d66ade23..f7ae13c891b 100644
--- a/configs/socfpga_secu1_defconfig
+++ b/configs/socfpga_secu1_defconfig
@@ -42,6 +42,7 @@ CONFIG_SPL_PAD_TO=0x10000
 CONFIG_SPL_NO_BSS_LIMIT=y
 CONFIG_SPL_LEGACY_IMAGE_CRC_CHECK=y
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
 # CONFIG_SPL_SYS_MMCSD_RAW_MODE is not set
 CONFIG_SPL_MTD=y
 CONFIG_SPL_NAND_SUPPORT=y
@@ -74,6 +75,7 @@ CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_BOOTCOUNT_LIMIT=y
 CONFIG_DM_BOOTCOUNT=y
 CONFIG_DM_BOOTCOUNT_RTC=y
+CONFIG_BOOTCOUNT_ALTBOOTCMD="run bootcmd;"
 CONFIG_DWAPB_GPIO=y
 CONFIG_DM_I2C=y
 CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
diff --git a/configs/socfpga_sockit_defconfig b/configs/socfpga_sockit_defconfig
index 869ba3d8b79..96ce2485a02 100644
--- a/configs/socfpga_sockit_defconfig
+++ b/configs/socfpga_sockit_defconfig
@@ -26,6 +26,7 @@ CONFIG_CLOCKS=y
 CONFIG_SPL_PAD_TO=0x10000
 CONFIG_SPL_NO_BSS_LIMIT=y
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_SPI_LOAD=y
 CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000
 CONFIG_SYS_MAXARGS=32
diff --git a/configs/socfpga_socrates_defconfig b/configs/socfpga_socrates_defconfig
index 31b406461e8..d14dc86a742 100644
--- a/configs/socfpga_socrates_defconfig
+++ b/configs/socfpga_socrates_defconfig
@@ -25,6 +25,7 @@ CONFIG_CLOCKS=y
 CONFIG_SPL_PAD_TO=0x10000
 CONFIG_SPL_NO_BSS_LIMIT=y
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_SPI_LOAD=y
 CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000
 CONFIG_SYS_MAXARGS=32
diff --git a/configs/socfpga_sr1500_defconfig b/configs/socfpga_sr1500_defconfig
index cade0d427cd..820b935b70a 100644
--- a/configs/socfpga_sr1500_defconfig
+++ b/configs/socfpga_sr1500_defconfig
@@ -34,6 +34,7 @@ CONFIG_CLOCKS=y
 CONFIG_SPL_PAD_TO=0x10000
 CONFIG_SPL_NO_BSS_LIMIT=y
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_SPI_LOAD=y
 CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000
 CONFIG_SYS_MAXARGS=32
diff --git a/configs/socfpga_stratix10_atf_defconfig b/configs/socfpga_stratix10_atf_defconfig
index d3a358c029a..8381dca2649 100644
--- a/configs/socfpga_stratix10_atf_defconfig
+++ b/configs/socfpga_stratix10_atf_defconfig
@@ -36,6 +36,7 @@ CONFIG_BOOTCOMMAND="run fatscript; run mmcfitload; run mmcfitboot"
 CONFIG_SYS_PBSIZE=2085
 CONFIG_SPL_MAX_SIZE=0x40000
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_SYS_MALLOC=y
 CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
 CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x3fa00000
diff --git a/configs/socfpga_stratix10_defconfig b/configs/socfpga_stratix10_defconfig
index 3ea82598472..43e3efde2cd 100644
--- a/configs/socfpga_stratix10_defconfig
+++ b/configs/socfpga_stratix10_defconfig
@@ -36,6 +36,7 @@ CONFIG_BOOTCOMMAND="run fatscript; run mmcload; run linux_qspi_enable; run mmcbo
 CONFIG_SYS_PBSIZE=2085
 CONFIG_SPL_MAX_SIZE=0x40000
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_SYS_MALLOC=y
 CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
 CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x3fa00000
diff --git a/configs/socfpga_vining_fpga_defconfig b/configs/socfpga_vining_fpga_defconfig
index df8391dc214..b4e303ed6dd 100644
--- a/configs/socfpga_vining_fpga_defconfig
+++ b/configs/socfpga_vining_fpga_defconfig
@@ -35,6 +35,7 @@ CONFIG_MISC_INIT_R=y
 CONFIG_SPL_PAD_TO=0x10000
 CONFIG_SPL_NO_BSS_LIMIT=y
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_SPI_LOAD=y
 CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000
 CONFIG_CMDLINE_PS_SUPPORT=y
diff --git a/configs/spring_defconfig b/configs/spring_defconfig
index 43846e3cad9..d3b6656d631 100644
--- a/configs/spring_defconfig
+++ b/configs/spring_defconfig
@@ -92,7 +92,6 @@ CONFIG_USB_HOST_ETHER=y
 CONFIG_USB_ETHER_ASIX88179=y
 CONFIG_VIDEO=y
 # CONFIG_VIDEO_BPP8 is not set
-CONFIG_VIDCONSOLE_AS_LCD=y
 CONFIG_DISPLAY=y
 CONFIG_VIDEO_EXYNOS=y
 CONFIG_EXYNOS_DP=y
diff --git a/configs/starfive_visionfive2_defconfig b/configs/starfive_visionfive2_defconfig
index 1e0a99ed17b..6a5b247c4b5 100644
--- a/configs/starfive_visionfive2_defconfig
+++ b/configs/starfive_visionfive2_defconfig
@@ -52,6 +52,7 @@ CONFIG_PCI_INIT_R=y
 CONFIG_SPL_MAX_SIZE=0x40000
 CONFIG_SPL_PAD_TO=0x0
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_SYS_MALLOC=y
 CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
 CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x80000000
@@ -71,6 +72,7 @@ CONFIG_SYS_EEPROM_SIZE=512
 CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=4
 CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
 CONFIG_CMD_MEMINFO=y
+# CONFIG_CMD_BIND is not set
 CONFIG_CMD_I2C=y
 CONFIG_CMD_PCI=y
 CONFIG_CMD_USB=y
@@ -117,6 +119,9 @@ CONFIG_NVME_PCI=y
 CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCI_REGION_MULTI_ENTRY=y
 CONFIG_PCIE_STARFIVE_JH7110=y
+CONFIG_PHY=y
+CONFIG_PHY_STARFIVE_JH7110_PCIE=y
+CONFIG_PHY_STARFIVE_JH7110_USB2=y
 CONFIG_PINCTRL=y
 CONFIG_PINCONF=y
 CONFIG_SPL_PINCTRL=y
@@ -132,13 +137,19 @@ CONFIG_CADENCE_QSPI=y
 CONFIG_SYSRESET=y
 CONFIG_TIMER_EARLY=y
 CONFIG_USB=y
+CONFIG_DM_USB_GADGET=y
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_PCI=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_EHCI_PCI=y
 CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_OHCI_PCI=y
+CONFIG_USB_CDNS3=y
+CONFIG_USB_CDNS3_GADGET=y
+CONFIG_USB_CDNS3_HOST=y
+# CONFIG_USB_CDNS3_TI is not set
 CONFIG_USB_KEYBOARD=y
+CONFIG_USB_GADGET=y
 # CONFIG_WATCHDOG is not set
 # CONFIG_WATCHDOG_AUTOSTART is not set
 CONFIG_WDT=y
diff --git a/configs/stm32746g-eval_defconfig b/configs/stm32746g-eval_defconfig
index 4346ecd6e42..bd3a48b20a2 100644
--- a/configs/stm32746g-eval_defconfig
+++ b/configs/stm32746g-eval_defconfig
@@ -21,7 +21,6 @@ CONFIG_USE_BOOTARGS=y
 CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk consoleblank=0 ignore_loglevel"
 CONFIG_SYS_PBSIZE=1050
 # CONFIG_DISPLAY_CPUINFO is not set
-CONFIG_BOARD_LATE_INIT=y
 CONFIG_SYS_PROMPT="U-Boot > "
 CONFIG_CMD_GPT=y
 CONFIG_CMD_MMC=y
diff --git a/configs/stm32746g-eval_spl_defconfig b/configs/stm32746g-eval_spl_defconfig
index 2756ad5508f..d47d059d23b 100644
--- a/configs/stm32746g-eval_spl_defconfig
+++ b/configs/stm32746g-eval_spl_defconfig
@@ -30,7 +30,6 @@ CONFIG_USE_BOOTARGS=y
 CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk consoleblank=0 ignore_loglevel"
 CONFIG_SYS_PBSIZE=1050
 # CONFIG_DISPLAY_CPUINFO is not set
-CONFIG_BOARD_LATE_INIT=y
 CONFIG_SPL_PAD_TO=0x9000
 CONFIG_SPL_NO_BSS_LIMIT=y
 CONFIG_SPL_BOARD_INIT=y
diff --git a/configs/stm32f746-disco_defconfig b/configs/stm32f746-disco_defconfig
index 35a489c34e0..f6fbf83f68f 100644
--- a/configs/stm32f746-disco_defconfig
+++ b/configs/stm32f746-disco_defconfig
@@ -21,7 +21,6 @@ CONFIG_USE_BOOTARGS=y
 CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk consoleblank=0 ignore_loglevel"
 CONFIG_SYS_PBSIZE=1050
 # CONFIG_DISPLAY_CPUINFO is not set
-CONFIG_BOARD_LATE_INIT=y
 CONFIG_SYS_PROMPT="U-Boot > "
 CONFIG_CMD_GPT=y
 CONFIG_CMD_MMC=y
diff --git a/configs/stm32f746-disco_spl_defconfig b/configs/stm32f746-disco_spl_defconfig
index 6826b1cb755..dcf077dbfee 100644
--- a/configs/stm32f746-disco_spl_defconfig
+++ b/configs/stm32f746-disco_spl_defconfig
@@ -30,7 +30,6 @@ CONFIG_USE_BOOTARGS=y
 CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk consoleblank=0 ignore_loglevel"
 CONFIG_SYS_PBSIZE=1050
 # CONFIG_DISPLAY_CPUINFO is not set
-CONFIG_BOARD_LATE_INIT=y
 CONFIG_SPL_PAD_TO=0x9000
 CONFIG_SPL_NO_BSS_LIMIT=y
 CONFIG_SPL_BOARD_INIT=y
diff --git a/configs/stm32f769-disco_defconfig b/configs/stm32f769-disco_defconfig
index 5be221afd2f..9edda0e36b2 100644
--- a/configs/stm32f769-disco_defconfig
+++ b/configs/stm32f769-disco_defconfig
@@ -18,7 +18,7 @@ CONFIG_AUTOBOOT_KEYED=y
 CONFIG_AUTOBOOT_PROMPT="Hit SPACE in %d seconds to stop autoboot.\n"
 CONFIG_AUTOBOOT_STOP_STR=" "
 CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk consoleblank=0 ignore_loglevel"
+CONFIG_BOOTARGS="console=ttySTM0,115200n8 earlyprintk consoleblank=0 ignore_loglevel"
 CONFIG_SYS_PBSIZE=1050
 # CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_CYCLIC_MAX_CPU_TIME_US=8000
diff --git a/configs/stm32mp13_defconfig b/configs/stm32mp13_defconfig
index 0acd1487c9a..4c6a7f82fe5 100644
--- a/configs/stm32mp13_defconfig
+++ b/configs/stm32mp13_defconfig
@@ -10,6 +10,7 @@ CONFIG_SYS_LOAD_ADDR=0xc2000000
 CONFIG_STM32MP13X=y
 CONFIG_DDR_CACHEABLE_SIZE=0x8000000
 CONFIG_CMD_STM32KEY=y
+CONFIG_MFD_STM32_TIMERS=y
 CONFIG_TARGET_ST_STM32MP13X=y
 CONFIG_ENV_OFFSET_REDUND=0x940000
 CONFIG_CMD_STM32PROG=y
@@ -31,6 +32,7 @@ CONFIG_CMD_UNZIP=y
 CONFIG_CMD_CLK=y
 CONFIG_CMD_FUSE=y
 CONFIG_CMD_GPIO=y
+CONFIG_CMD_PWM=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_LSBLK=y
 CONFIG_CMD_MMC=y
@@ -80,6 +82,8 @@ CONFIG_DM_REGULATOR=y
 CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_DM_REGULATOR_GPIO=y
 CONFIG_DM_REGULATOR_SCMI=y
+CONFIG_DM_PWM=y
+CONFIG_PWM_STM32=y
 CONFIG_RESET_SCMI=y
 CONFIG_DM_RNG=y
 CONFIG_RNG_STM32=y
diff --git a/configs/stm32mp13_dhcor_defconfig b/configs/stm32mp13_dhcor_defconfig
index ff948b904be..2da9287ea7b 100644
--- a/configs/stm32mp13_dhcor_defconfig
+++ b/configs/stm32mp13_dhcor_defconfig
@@ -28,10 +28,14 @@ CONFIG_CMD_RNG=y
 CONFIG_CMD_LOG=y
 CONFIG_CMD_UBI=y
 CONFIG_ENV_IS_NOWHERE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_ENV_MMC_USE_DT=y
 CONFIG_ENV_SPI_MAX_HZ=50000000
 CONFIG_CLK_SCMI=y
 CONFIG_SET_DFU_ALT_INFO=y
 CONFIG_SYS_I2C_EEPROM_ADDR=0x50
+CONFIG_SYS_MMC_ENV_DEV=0
+CONFIG_SYS_MMC_ENV_PART=1
 CONFIG_PHY_REALTEK=y
 CONFIG_DM_REGULATOR_SCMI=y
 CONFIG_RESET_SCMI=y
diff --git a/configs/stm32mp15-icore-stm32mp1-ctouch2_defconfig b/configs/stm32mp15-icore-stm32mp1-ctouch2_defconfig
index 00c475307c9..28a5d93912a 100644
--- a/configs/stm32mp15-icore-stm32mp1-ctouch2_defconfig
+++ b/configs/stm32mp15-icore-stm32mp1-ctouch2_defconfig
@@ -23,6 +23,7 @@ CONFIG_SYS_PBSIZE=1050
 CONFIG_SPL_FOOTPRINT_LIMIT=y
 CONFIG_SPL_MAX_FOOTPRINT=0x3db00
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_SYS_MALLOC=y
 CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
 CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0xc0300000
diff --git a/configs/stm32mp15-icore-stm32mp1-edimm2.2_defconfig b/configs/stm32mp15-icore-stm32mp1-edimm2.2_defconfig
index b733913be01..efac47645a9 100644
--- a/configs/stm32mp15-icore-stm32mp1-edimm2.2_defconfig
+++ b/configs/stm32mp15-icore-stm32mp1-edimm2.2_defconfig
@@ -23,6 +23,7 @@ CONFIG_SYS_PBSIZE=1050
 CONFIG_SPL_FOOTPRINT_LIMIT=y
 CONFIG_SPL_MAX_FOOTPRINT=0x3db00
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_SYS_MALLOC=y
 CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
 CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0xc0300000
diff --git a/configs/stm32mp15-microgea-stm32mp1-microdev2-of7_defconfig b/configs/stm32mp15-microgea-stm32mp1-microdev2-of7_defconfig
index 35df3ea809d..f9f55d12a87 100644
--- a/configs/stm32mp15-microgea-stm32mp1-microdev2-of7_defconfig
+++ b/configs/stm32mp15-microgea-stm32mp1-microdev2-of7_defconfig
@@ -23,6 +23,7 @@ CONFIG_SYS_PBSIZE=1050
 CONFIG_SPL_FOOTPRINT_LIMIT=y
 CONFIG_SPL_MAX_FOOTPRINT=0x3db00
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_SYS_MALLOC=y
 CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
 CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0xc0300000
diff --git a/configs/stm32mp15-microgea-stm32mp1-microdev2_defconfig b/configs/stm32mp15-microgea-stm32mp1-microdev2_defconfig
index d1a92cbfbaa..d5732358376 100644
--- a/configs/stm32mp15-microgea-stm32mp1-microdev2_defconfig
+++ b/configs/stm32mp15-microgea-stm32mp1-microdev2_defconfig
@@ -23,6 +23,7 @@ CONFIG_SYS_PBSIZE=1050
 CONFIG_SPL_FOOTPRINT_LIMIT=y
 CONFIG_SPL_MAX_FOOTPRINT=0x3db00
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_SYS_MALLOC=y
 CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
 CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0xc0300000
diff --git a/configs/stm32mp15_basic_defconfig b/configs/stm32mp15_basic_defconfig
index b0dc944a247..cda17e5a40b 100644
--- a/configs/stm32mp15_basic_defconfig
+++ b/configs/stm32mp15_basic_defconfig
@@ -34,6 +34,7 @@ CONFIG_BOARD_EARLY_INIT_F=y
 CONFIG_SPL_FOOTPRINT_LIMIT=y
 CONFIG_SPL_MAX_FOOTPRINT=0x3db00
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_SYS_MALLOC=y
 CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
 CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0xc0300000
diff --git a/configs/stm32mp15_dhcom_basic.config b/configs/stm32mp15_dhcom_basic.config
new file mode 100644
index 00000000000..d78916bb5b2
--- /dev/null
+++ b/configs/stm32mp15_dhcom_basic.config
@@ -0,0 +1,8 @@
+#include <configs/stm32mp15_dhsom.config>
+
+CONFIG_ARM=y
+CONFIG_ARCH_STM32MP=y
+CONFIG_SYS_MEMTEST_START=0xc0000000
+CONFIG_SYS_MEMTEST_END=0xc4000000
+CONFIG_SYS_I2C_EEPROM_BUS=3
+CONFIG_SYS_I2C_EEPROM_ADDR=0x50
diff --git a/configs/stm32mp15_dhcom_basic_defconfig b/configs/stm32mp15_dhcom_basic_defconfig
index a28f2862048..297092bd746 100644
--- a/configs/stm32mp15_dhcom_basic_defconfig
+++ b/configs/stm32mp15_dhcom_basic_defconfig
@@ -1,10 +1,4 @@
-#include <configs/stm32mp15_dhsom.config>
+#include <configs/stm32mp15_dhcom_basic.config>
 
-CONFIG_ARM=y
-CONFIG_ARCH_STM32MP=y
 CONFIG_DEFAULT_DEVICE_TREE="st/stm32mp157c-dhcom-pdk2"
-CONFIG_SYS_MEMTEST_START=0xc0000000
-CONFIG_SYS_MEMTEST_END=0xc4000000
-CONFIG_SYS_I2C_EEPROM_BUS=3
 CONFIG_OF_LIST="st/stm32mp157c-dhcom-pdk2 st/stm32mp153c-dhcom-drc02 st/stm32mp157c-dhcom-picoitx"
-CONFIG_SYS_I2C_EEPROM_ADDR=0x50
diff --git a/configs/stm32mp15_dhcom_drc02_basic_defconfig b/configs/stm32mp15_dhcom_drc02_basic_defconfig
new file mode 100644
index 00000000000..838c3db253d
--- /dev/null
+++ b/configs/stm32mp15_dhcom_drc02_basic_defconfig
@@ -0,0 +1,4 @@
+#include <configs/stm32mp15_dhcom_basic.config>
+
+CONFIG_DEFAULT_DEVICE_TREE="st/stm32mp153c-dhcom-drc02"
+CONFIG_OF_LIST="st/stm32mp153c-dhcom-drc02"
diff --git a/configs/stm32mp15_dhcom_pdk2_basic_defconfig b/configs/stm32mp15_dhcom_pdk2_basic_defconfig
new file mode 100644
index 00000000000..c6996233c9f
--- /dev/null
+++ b/configs/stm32mp15_dhcom_pdk2_basic_defconfig
@@ -0,0 +1,4 @@
+#include <configs/stm32mp15_dhcom_basic.config>
+
+CONFIG_DEFAULT_DEVICE_TREE="st/stm32mp157c-dhcom-pdk2"
+CONFIG_OF_LIST="st/stm32mp157c-dhcom-pdk2"
diff --git a/configs/stm32mp15_dhcom_picoitx_basic_defconfig b/configs/stm32mp15_dhcom_picoitx_basic_defconfig
new file mode 100644
index 00000000000..5682edbfcbf
--- /dev/null
+++ b/configs/stm32mp15_dhcom_picoitx_basic_defconfig
@@ -0,0 +1,4 @@
+#include <configs/stm32mp15_dhcom_basic.config>
+
+CONFIG_DEFAULT_DEVICE_TREE="st/stm32mp157c-dhcom-picoitx"
+CONFIG_OF_LIST="st/stm32mp157c-dhcom-picoitx"
diff --git a/configs/stm32mp15_dhcor_avenger96_basic_defconfig b/configs/stm32mp15_dhcor_avenger96_basic_defconfig
new file mode 100644
index 00000000000..5d27cd5ed7e
--- /dev/null
+++ b/configs/stm32mp15_dhcor_avenger96_basic_defconfig
@@ -0,0 +1,4 @@
+#include <configs/stm32mp15_dhcor_basic.config>
+
+CONFIG_DEFAULT_DEVICE_TREE="st/stm32mp157a-dhcor-avenger96"
+CONFIG_OF_LIST="st/stm32mp157a-dhcor-avenger96"
diff --git a/configs/stm32mp15_dhcor_basic.config b/configs/stm32mp15_dhcor_basic.config
new file mode 100644
index 00000000000..e9c0cb9f95a
--- /dev/null
+++ b/configs/stm32mp15_dhcor_basic.config
@@ -0,0 +1,8 @@
+#include <configs/stm32mp15_dhsom.config>
+
+CONFIG_ARM=y
+CONFIG_ARCH_STM32MP=y
+CONFIG_SYS_I2C_EEPROM_BUS=2
+CONFIG_SYS_I2C_EEPROM_ADDR=0x53
+CONFIG_PHY_MICREL=y
+CONFIG_PHY_MICREL_KSZ90X1=y
diff --git a/configs/stm32mp15_dhcor_basic_defconfig b/configs/stm32mp15_dhcor_basic_defconfig
index f6f2af6e7a2..beb6d1d5a9a 100644
--- a/configs/stm32mp15_dhcor_basic_defconfig
+++ b/configs/stm32mp15_dhcor_basic_defconfig
@@ -1,10 +1,4 @@
-#include <configs/stm32mp15_dhsom.config>
+#include <configs/stm32mp15_dhcor_basic.config>
 
-CONFIG_ARM=y
-CONFIG_ARCH_STM32MP=y
 CONFIG_DEFAULT_DEVICE_TREE="st/stm32mp157a-dhcor-avenger96"
-CONFIG_SYS_I2C_EEPROM_BUS=2
 CONFIG_OF_LIST="st/stm32mp157a-dhcor-avenger96 st/stm32mp151a-dhcor-testbench st/stm32mp153c-dhcor-drc-compact"
-CONFIG_SYS_I2C_EEPROM_ADDR=0x53
-CONFIG_PHY_MICREL=y
-CONFIG_PHY_MICREL_KSZ90X1=y
diff --git a/configs/stm32mp15_dhcor_drc_compact_basic_defconfig b/configs/stm32mp15_dhcor_drc_compact_basic_defconfig
new file mode 100644
index 00000000000..7b1d73a33b5
--- /dev/null
+++ b/configs/stm32mp15_dhcor_drc_compact_basic_defconfig
@@ -0,0 +1,4 @@
+#include <configs/stm32mp15_dhcor_basic.config>
+
+CONFIG_DEFAULT_DEVICE_TREE="st/stm32mp153c-dhcor-drc-compact"
+CONFIG_OF_LIST="st/stm32mp153c-dhcor-drc-compact"
diff --git a/configs/stm32mp15_dhcor_testbench_basic_defconfig b/configs/stm32mp15_dhcor_testbench_basic_defconfig
new file mode 100644
index 00000000000..7ba327cbd82
--- /dev/null
+++ b/configs/stm32mp15_dhcor_testbench_basic_defconfig
@@ -0,0 +1,4 @@
+#include <configs/stm32mp15_dhcor_basic.config>
+
+CONFIG_DEFAULT_DEVICE_TREE="st/stm32mp151a-dhcor-testbench"
+CONFIG_OF_LIST="st/stm32mp151a-dhcor-testbench"
diff --git a/configs/stm32mp15_dhsom.config b/configs/stm32mp15_dhsom.config
index ac3ae82cda9..7e5b5aa67ef 100644
--- a/configs/stm32mp15_dhsom.config
+++ b/configs/stm32mp15_dhsom.config
@@ -55,6 +55,7 @@ CONFIG_SPL_RAM_DEVICE=y
 CONFIG_SPL_SPI=y
 CONFIG_SPL_SPI_FLASH_MTD=y
 CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_STACK=0x30000000
 CONFIG_SPL_SYS_MALLOC=y
 CONFIG_SPL_SYS_MALLOC_SIZE=0x1d00000
diff --git a/configs/stout_defconfig b/configs/stout_defconfig
index 59bb7075013..2100fbd0805 100644
--- a/configs/stout_defconfig
+++ b/configs/stout_defconfig
@@ -14,6 +14,7 @@ CONFIG_ARCH_RENESAS_BOARD_STRING="Stout"
 CONFIG_R8A7790=y
 CONFIG_TARGET_STOUT=y
 CONFIG_SPL_SERIAL=y
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_STACK=0xe6340000
 CONFIG_SPL_SYS_MALLOC_F_LEN=0x2000
 CONFIG_SPL=y
diff --git a/configs/surface-rt_defconfig b/configs/surface-rt_defconfig
index b5c84b4f003..24fca755dc5 100644
--- a/configs/surface-rt_defconfig
+++ b/configs/surface-rt_defconfig
@@ -23,6 +23,7 @@ CONFIG_SYS_PBSIZE=2084
 CONFIG_SPL_FOOTPRINT_LIMIT=y
 CONFIG_SPL_MAX_FOOTPRINT=0x8000
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_SYS_MALLOC=y
 CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
 CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x80090000
diff --git a/configs/syzygy_hub_defconfig b/configs/syzygy_hub_defconfig
index 27ff3915050..bf11e898145 100644
--- a/configs/syzygy_hub_defconfig
+++ b/configs/syzygy_hub_defconfig
@@ -30,6 +30,7 @@ CONFIG_SYS_PBSIZE=2071
 CONFIG_CLOCKS=y
 CONFIG_SPL_MAX_SIZE=0x30000
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_SYS_MALLOC=y
 CONFIG_SPL_SYS_MALLOC_SIZE=0x2000000
 CONFIG_SPL_FS_LOAD_ARGS_NAME="system.dtb"
diff --git a/configs/taurus_defconfig b/configs/taurus_defconfig
index b60dfc6cd6f..29fa4ea42af 100644
--- a/configs/taurus_defconfig
+++ b/configs/taurus_defconfig
@@ -49,6 +49,7 @@ CONFIG_SPL_PAD_TO=0x20000
 # CONFIG_SPL_LEGACY_IMAGE_FORMAT is not set
 CONFIG_SPL_SYS_MALLOC_SIMPLE=y
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_SYS_MALLOC=y
 CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
 CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x20ba0000
diff --git a/configs/tbs2910_defconfig b/configs/tbs2910_defconfig
index 99fe65d3109..c307d8c23d0 100644
--- a/configs/tbs2910_defconfig
+++ b/configs/tbs2910_defconfig
@@ -110,7 +110,6 @@ CONFIG_VIDEO=y
 # CONFIG_VIDEO_BPP32 is not set
 CONFIG_SYS_WHITE_ON_BLACK=y
 # CONFIG_PANEL is not set
-CONFIG_VIDCONSOLE_AS_LCD=y
 CONFIG_I2C_EDID=y
 CONFIG_VIDEO_IPUV3=y
 CONFIG_IMX_VIDEO_SKIP=y
diff --git a/configs/tec-ng_defconfig b/configs/tec-ng_defconfig
index 5e840ffcf2c..1af1aa4e0bf 100644
--- a/configs/tec-ng_defconfig
+++ b/configs/tec-ng_defconfig
@@ -21,6 +21,7 @@ CONFIG_SYS_STDIO_DEREGISTER=y
 CONFIG_SPL_FOOTPRINT_LIMIT=y
 CONFIG_SPL_MAX_FOOTPRINT=0x8000
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_SYS_MALLOC=y
 CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
 CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x80090000
diff --git a/configs/tec_defconfig b/configs/tec_defconfig
index 3d46c9e57e3..2f686105700 100644
--- a/configs/tec_defconfig
+++ b/configs/tec_defconfig
@@ -19,6 +19,7 @@ CONFIG_SYS_STDIO_DEREGISTER=y
 CONFIG_SPL_FOOTPRINT_LIMIT=y
 CONFIG_SPL_MAX_FOOTPRINT=0x8000
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_SYS_MALLOC=y
 CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
 CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x90000
diff --git a/configs/theadorable_debug_defconfig b/configs/theadorable_debug_defconfig
index f957167f0ad..dfcc08bbce5 100644
--- a/configs/theadorable_debug_defconfig
+++ b/configs/theadorable_debug_defconfig
@@ -39,6 +39,7 @@ CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_SPL_MAX_SIZE=0x1bfd0
 CONFIG_SPL_SYS_MALLOC_SIMPLE=y
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_I2C=y
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_MAXARGS=32
diff --git a/configs/tools-only_defconfig b/configs/tools-only_defconfig
index cecd26175d1..e64bb768440 100644
--- a/configs/tools-only_defconfig
+++ b/configs/tools-only_defconfig
@@ -9,10 +9,11 @@ CONFIG_EFI_LOADER=n
 CONFIG_ANDROID_BOOT_IMAGE=y
 CONFIG_TIMESTAMP=y
 CONFIG_FIT=y
-CONFIG_FIT_SIGNATURE=y
 CONFIG_BOOTSTD_FULL=n
 CONFIG_BOOTMETH_CROS=n
 CONFIG_BOOTMETH_VBE=n
+CONFIG_IMAGE_PRE_LOAD=y
+CONFIG_IMAGE_PRE_LOAD_SIG=y
 CONFIG_USE_BOOTCOMMAND=y
 CONFIG_BOOTCOMMAND="run distro_bootcmd"
 CONFIG_CMD_BOOTD=n
diff --git a/configs/topic_miami_defconfig b/configs/topic_miami_defconfig
index 039ac710b38..6bfcaab37dc 100644
--- a/configs/topic_miami_defconfig
+++ b/configs/topic_miami_defconfig
@@ -34,6 +34,7 @@ CONFIG_SYS_PBSIZE=2077
 CONFIG_CLOCKS=y
 CONFIG_SPL_MAX_SIZE=0x30000
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_SYS_MALLOC=y
 CONFIG_SPL_SYS_MALLOC_SIZE=0x2000000
 CONFIG_SPL_SPI_LOAD=y
diff --git a/configs/topic_miamilite_defconfig b/configs/topic_miamilite_defconfig
index b53f3a7150e..c48d64bf535 100644
--- a/configs/topic_miamilite_defconfig
+++ b/configs/topic_miamilite_defconfig
@@ -34,6 +34,7 @@ CONFIG_SYS_PBSIZE=2077
 CONFIG_CLOCKS=y
 CONFIG_SPL_MAX_SIZE=0x30000
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_SYS_MALLOC=y
 CONFIG_SPL_SYS_MALLOC_SIZE=0x2000000
 CONFIG_SPL_SPI_LOAD=y
diff --git a/configs/topic_miamiplus_defconfig b/configs/topic_miamiplus_defconfig
index ba7f248db3b..e16801032e3 100644
--- a/configs/topic_miamiplus_defconfig
+++ b/configs/topic_miamiplus_defconfig
@@ -34,6 +34,7 @@ CONFIG_SYS_PBSIZE=2077
 CONFIG_CLOCKS=y
 CONFIG_SPL_MAX_SIZE=0x30000
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_SYS_MALLOC=y
 CONFIG_SPL_SYS_MALLOC_SIZE=0x2000000
 CONFIG_SPL_SPI_LOAD=y
diff --git a/configs/transformer_t20_defconfig b/configs/transformer_t20_defconfig
index b69366581a4..50b5885bb09 100644
--- a/configs/transformer_t20_defconfig
+++ b/configs/transformer_t20_defconfig
@@ -21,11 +21,12 @@ CONFIG_BOOTDELAY=0
 CONFIG_AUTOBOOT_KEYED=y
 CONFIG_AUTOBOOT_KEYED_CTRLC=y
 CONFIG_OF_SYSTEM_SETUP=y
-CONFIG_BOOTCOMMAND="bootflow scan; poweroff"
+CONFIG_BOOTCOMMAND="bootflow scan; echo 'Boot configuration not found... Power off in 3 sec'; sleep 3; poweroff"
 CONFIG_SYS_PBSIZE=2085
 CONFIG_SPL_FOOTPRINT_LIMIT=y
 CONFIG_SPL_MAX_FOOTPRINT=0x8000
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_SYS_MALLOC=y
 CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
 CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x90000
diff --git a/configs/transformer_t30_defconfig b/configs/transformer_t30_defconfig
index c5f0bc2a613..3e2db0cb7d0 100644
--- a/configs/transformer_t30_defconfig
+++ b/configs/transformer_t30_defconfig
@@ -21,11 +21,12 @@ CONFIG_AUTOBOOT_KEYED=y
 CONFIG_AUTOBOOT_KEYED_CTRLC=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_SYSTEM_SETUP=y
-CONFIG_BOOTCOMMAND="bootflow scan; poweroff"
+CONFIG_BOOTCOMMAND="bootflow scan; echo 'Boot configuration not found... Power off in 3 sec'; sleep 3; poweroff"
 CONFIG_SYS_PBSIZE=2084
 CONFIG_SPL_FOOTPRINT_LIMIT=y
 CONFIG_SPL_MAX_FOOTPRINT=0x8000
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_SYS_MALLOC=y
 CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
 CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x80090000
@@ -89,6 +90,8 @@ CONFIG_USB_GADGET_VENDOR_NUM=0x0b05
 CONFIG_USB_GADGET_PRODUCT_NUM=0x4daf
 CONFIG_CI_UDC=y
 CONFIG_VIDEO=y
+CONFIG_VIDEO_BRIDGE=y
 # CONFIG_VIDEO_LOGO is not set
 CONFIG_VIDEO_BRIDGE_TOSHIBA_TC358768=y
 CONFIG_VIDEO_TEGRA20=y
+CONFIG_VIDEO_HDMI_TEGRA=y
diff --git a/configs/trimslice_defconfig b/configs/trimslice_defconfig
index c04fc1a7752..47e467e71b7 100644
--- a/configs/trimslice_defconfig
+++ b/configs/trimslice_defconfig
@@ -21,6 +21,7 @@ CONFIG_SYS_STDIO_DEREGISTER=y
 CONFIG_SPL_FOOTPRINT_LIMIT=y
 CONFIG_SPL_MAX_FOOTPRINT=0x8000
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_SYS_MALLOC=y
 CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
 CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x90000
diff --git a/configs/tuge1_defconfig b/configs/tuge1_defconfig
index d1b771993cf..ab0fd12bc48 100644
--- a/configs/tuge1_defconfig
+++ b/configs/tuge1_defconfig
@@ -137,6 +137,7 @@ CONFIG_VERSION_VARIABLE=y
 CONFIG_BOOTCOUNT_LIMIT=y
 CONFIG_DM_BOOTCOUNT=y
 CONFIG_BOOTCOUNT_MEM=y
+CONFIG_BOOTCOUNT_ALTBOOTCMD="run bootcmd"
 CONFIG_SYS_BOOTCOUNT_BE=y
 CONFIG_SYS_BR0_PRELIM_BOOL=y
 CONFIG_SYS_BR0_PRELIM=0xF0001001
diff --git a/configs/turris_omnia_defconfig b/configs/turris_omnia_defconfig
index bdcc7407143..29c34f9d549 100644
--- a/configs/turris_omnia_defconfig
+++ b/configs/turris_omnia_defconfig
@@ -52,6 +52,7 @@ CONFIG_MISC_INIT_R=y
 CONFIG_SPL_MAX_SIZE=0x22fd0
 CONFIG_SPL_BOARD_INIT=y
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_ENV_SUPPORT=y
 CONFIG_SPL_I2C=y
 CONFIG_SYS_MAXARGS=32
diff --git a/configs/tuxx1_defconfig b/configs/tuxx1_defconfig
index 1dc737e4954..e5a99b24dab 100644
--- a/configs/tuxx1_defconfig
+++ b/configs/tuxx1_defconfig
@@ -151,6 +151,7 @@ CONFIG_VERSION_VARIABLE=y
 CONFIG_BOOTCOUNT_LIMIT=y
 CONFIG_DM_BOOTCOUNT=y
 CONFIG_BOOTCOUNT_MEM=y
+CONFIG_BOOTCOUNT_ALTBOOTCMD="run bootcmd"
 CONFIG_SYS_BR0_PRELIM_BOOL=y
 CONFIG_SYS_BR0_PRELIM=0xF0001001
 CONFIG_SYS_OR0_PRELIM=0xF0000E55
diff --git a/configs/uniphier_ld4_sld8_defconfig b/configs/uniphier_ld4_sld8_defconfig
index a0fea87dafd..ece3d293d06 100644
--- a/configs/uniphier_ld4_sld8_defconfig
+++ b/configs/uniphier_ld4_sld8_defconfig
@@ -26,6 +26,7 @@ CONFIG_LOGLEVEL=6
 CONFIG_SPL_MAX_SIZE=0x10000
 CONFIG_SPL_PAD_TO=0x20000
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_NAND_SUPPORT=y
 CONFIG_SPL_NOR_SUPPORT=y
 CONFIG_SPL_TARGET="u-boot-with-spl.bin"
diff --git a/configs/uniphier_v7_defconfig b/configs/uniphier_v7_defconfig
index 12647bb8ce1..4472609d85e 100644
--- a/configs/uniphier_v7_defconfig
+++ b/configs/uniphier_v7_defconfig
@@ -26,6 +26,7 @@ CONFIG_LOGLEVEL=6
 CONFIG_SPL_MAX_SIZE=0x10000
 CONFIG_SPL_PAD_TO=0x20000
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_NAND_SUPPORT=y
 CONFIG_SPL_NOR_SUPPORT=y
 CONFIG_SPL_TARGET="u-boot-with-spl.bin"
diff --git a/configs/venice2_defconfig b/configs/venice2_defconfig
index dfe821b3674..3d80197ef38 100644
--- a/configs/venice2_defconfig
+++ b/configs/venice2_defconfig
@@ -21,6 +21,7 @@ CONFIG_SYS_STDIO_DEREGISTER=y
 CONFIG_SPL_FOOTPRINT_LIMIT=y
 CONFIG_SPL_MAX_FOOTPRINT=0x8000
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_SYS_MALLOC=y
 CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
 CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x80090000
diff --git a/configs/ventana_defconfig b/configs/ventana_defconfig
index 1357f5faf26..c24fdcad533 100644
--- a/configs/ventana_defconfig
+++ b/configs/ventana_defconfig
@@ -18,6 +18,7 @@ CONFIG_SYS_PBSIZE=2085
 CONFIG_SPL_FOOTPRINT_LIMIT=y
 CONFIG_SPL_MAX_FOOTPRINT=0x8000
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_SYS_MALLOC=y
 CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
 CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x90000
diff --git a/configs/verdin-am62_a53_defconfig b/configs/verdin-am62_a53_defconfig
index e7a88c9788d..ecd3284faaf 100644
--- a/configs/verdin-am62_a53_defconfig
+++ b/configs/verdin-am62_a53_defconfig
@@ -76,7 +76,6 @@ CONFIG_CMD_GPIO=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_READ=y
-CONFIG_CMD_REMOTEPROC=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_USB_MASS_STORAGE=y
 CONFIG_CMD_BOOTCOUNT=y
diff --git a/configs/verdin-am62_r5_defconfig b/configs/verdin-am62_r5_defconfig
index d4f904ac07d..9ac4b534f6c 100644
--- a/configs/verdin-am62_r5_defconfig
+++ b/configs/verdin-am62_r5_defconfig
@@ -48,14 +48,12 @@ CONFIG_SPL_DM_MAILBOX=y
 CONFIG_SPL_DM_RESET=y
 CONFIG_SPL_POWER_DOMAIN=y
 CONFIG_SPL_RAM_DEVICE=y
-CONFIG_SPL_REMOTEPROC=y
 CONFIG_SPL_YMODEM_SUPPORT=y
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_ASKENV=y
 CONFIG_CMD_DFU=y
 CONFIG_CMD_GPT=y
 CONFIG_CMD_MMC=y
-CONFIG_CMD_REMOTEPROC=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_TIME=y
 CONFIG_OF_CONTROL=y
@@ -97,7 +95,6 @@ CONFIG_PINCTRL_SINGLE=y
 CONFIG_POWER_DOMAIN=y
 CONFIG_TI_POWER_DOMAIN=y
 CONFIG_K3_SYSTEM_CONTROLLER=y
-CONFIG_REMOTEPROC_TI_K3_ARM64=y
 CONFIG_RESET_TI_SCI=y
 CONFIG_SPECIFY_CONSOLE_INDEX=y
 CONFIG_DM_SERIAL=y
diff --git a/configs/verdin-imx8mm_defconfig b/configs/verdin-imx8mm_defconfig
index b54028f3b60..e38a73e0c01 100644
--- a/configs/verdin-imx8mm_defconfig
+++ b/configs/verdin-imx8mm_defconfig
@@ -43,6 +43,7 @@ CONFIG_ARCH_MISC_INIT=y
 CONFIG_BOARD_LATE_INIT=y
 CONFIG_SPL_BOARD_INIT=y
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_SYS_MALLOC=y
 CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
 CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000
diff --git a/configs/verdin-imx8mp_defconfig b/configs/verdin-imx8mp_defconfig
index ec76cff4dbe..62c3bcb0a9d 100644
--- a/configs/verdin-imx8mp_defconfig
+++ b/configs/verdin-imx8mp_defconfig
@@ -56,6 +56,7 @@ CONFIG_SPL_BOARD_INIT=y
 CONFIG_SPL_BOOTROM_SUPPORT=y
 CONFIG_SPL_SYS_MALLOC_SIMPLE=y
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_SYS_MALLOC=y
 CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
 CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000
diff --git a/configs/vexpress_fvp_bloblist_defconfig b/configs/vexpress_fvp_bloblist_defconfig
new file mode 100644
index 00000000000..4d52b96202b
--- /dev/null
+++ b/configs/vexpress_fvp_bloblist_defconfig
@@ -0,0 +1,5 @@
+#include <configs/vexpress_fvp_defconfig>
+
+CONFIG_BLOBLIST=y
+CONFIG_BLOBLIST_PASSAGE_MANDATORY=y
+CONFIG_BLOBLIST_SIZE_RELOC=0x10000
diff --git a/configs/vexpress_fvp_defconfig b/configs/vexpress_fvp_defconfig
index 7362c1fc35c..fda0f5283c9 100644
--- a/configs/vexpress_fvp_defconfig
+++ b/configs/vexpress_fvp_defconfig
@@ -2,4 +2,5 @@ CONFIG_ARM=y
 CONFIG_ARCH_VEXPRESS64=y
 CONFIG_DEFAULT_DEVICE_TREE="arm_fvp"
 CONFIG_IDENT_STRING=" arm_fvp"
+# CONFIG_ARM64_CRC32 is not set
 # CONFIG_DISPLAY_CPUINFO is not set
diff --git a/configs/vyasa-rk3288_defconfig b/configs/vyasa-rk3288_defconfig
index e75466c1cad..b5f20f18ab8 100644
--- a/configs/vyasa-rk3288_defconfig
+++ b/configs/vyasa-rk3288_defconfig
@@ -32,6 +32,7 @@ CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_SPL_PAD_TO=0x7f8000
 CONFIG_SPL_NO_BSS_LIMIT=y
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_OS_BOOT=y
 CONFIG_SPL_PAYLOAD_ARGS_ADDR=0xffe5000
 CONFIG_SPL_FALCON_BOOT_MMCSD=y
diff --git a/configs/work_92105_defconfig b/configs/work_92105_defconfig
index 0b5ad853241..0b4989ca002 100644
--- a/configs/work_92105_defconfig
+++ b/configs/work_92105_defconfig
@@ -34,6 +34,7 @@ CONFIG_SPL_NO_BSS_LIMIT=y
 CONFIG_SPL_BOARD_INIT=y
 CONFIG_SPL_SYS_MALLOC_SIMPLE=y
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_NAND_SUPPORT=y
 CONFIG_SPL_NAND_DRIVERS=y
 CONFIG_SPL_NAND_BASE=y
diff --git a/configs/x3_t30_defconfig b/configs/x3_t30_defconfig
index c8da5b4ce35..e738bd232d0 100644
--- a/configs/x3_t30_defconfig
+++ b/configs/x3_t30_defconfig
@@ -21,11 +21,12 @@ CONFIG_AUTOBOOT_KEYED=y
 CONFIG_AUTOBOOT_KEYED_CTRLC=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_SYSTEM_SETUP=y
-CONFIG_BOOTCOMMAND="bootflow scan; poweroff"
+CONFIG_BOOTCOMMAND="bootflow scan; echo 'Boot configuration not found... Power off in 3 sec'; sleep 3; poweroff"
 CONFIG_SYS_PBSIZE=2084
 CONFIG_SPL_FOOTPRINT_LIMIT=y
 CONFIG_SPL_MAX_FOOTPRINT=0x8000
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_SYS_MALLOC=y
 CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
 CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x80090000
@@ -82,6 +83,7 @@ CONFIG_USB_GADGET_VENDOR_NUM=0x1004
 CONFIG_USB_GADGET_PRODUCT_NUM=0x7100
 CONFIG_CI_UDC=y
 CONFIG_VIDEO=y
+CONFIG_VIDEO_BRIDGE=y
 # CONFIG_VIDEO_LOGO is not set
 CONFIG_BACKLIGHT_LM3533=y
 CONFIG_VIDEO_BRIDGE_SOLOMON_SSD2825=y
diff --git a/configs/x530_defconfig b/configs/x530_defconfig
index 815370c90ec..c060fa0eb4c 100644
--- a/configs/x530_defconfig
+++ b/configs/x530_defconfig
@@ -40,6 +40,7 @@ CONFIG_SPL_MAX_SIZE=0x22fd0
 CONFIG_SPL_BOARD_INIT=y
 CONFIG_SPL_SYS_MALLOC_SIMPLE=y
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_WATCHDOG=y
 CONFIG_CMD_MEMINFO=y
 CONFIG_CMD_GPIO=y
diff --git a/configs/xilinx_mbv32_defconfig b/configs/xilinx_mbv32_defconfig
index 7333413267e..861d1475453 100644
--- a/configs/xilinx_mbv32_defconfig
+++ b/configs/xilinx_mbv32_defconfig
@@ -27,6 +27,7 @@ CONFIG_DISPLAY_BOARDINFO=y
 # CONFIG_BOARD_LATE_INIT is not set
 CONFIG_SPL_MAX_SIZE=0x40000
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_SYS_MALLOC=y
 CONFIG_SPL_SYS_MALLOC_SIZE=0x800000
 # CONFIG_CMD_MII is not set
diff --git a/configs/xilinx_mbv32_smode_defconfig b/configs/xilinx_mbv32_smode_defconfig
index 820681d505b..9398b4c240d 100644
--- a/configs/xilinx_mbv32_smode_defconfig
+++ b/configs/xilinx_mbv32_smode_defconfig
@@ -28,6 +28,7 @@ CONFIG_DISPLAY_BOARDINFO=y
 # CONFIG_BOARD_LATE_INIT is not set
 CONFIG_SPL_MAX_SIZE=0x40000
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_SYS_MALLOC=y
 CONFIG_SPL_SYS_MALLOC_SIZE=0x800000
 CONFIG_SPL_OPENSBI_SCRATCH_OPTIONS=0x2
diff --git a/configs/xilinx_mbv64_defconfig b/configs/xilinx_mbv64_defconfig
index aad9c3f140b..c39925bd86a 100644
--- a/configs/xilinx_mbv64_defconfig
+++ b/configs/xilinx_mbv64_defconfig
@@ -28,6 +28,7 @@ CONFIG_DISPLAY_BOARDINFO=y
 # CONFIG_BOARD_LATE_INIT is not set
 CONFIG_SPL_MAX_SIZE=0x40000
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_SYS_MALLOC=y
 CONFIG_SPL_SYS_MALLOC_SIZE=0x800000
 # CONFIG_CMD_MII is not set
diff --git a/configs/xilinx_mbv64_smode_defconfig b/configs/xilinx_mbv64_smode_defconfig
index 628e0ed5be2..811f93a2671 100644
--- a/configs/xilinx_mbv64_smode_defconfig
+++ b/configs/xilinx_mbv64_smode_defconfig
@@ -29,6 +29,7 @@ CONFIG_DISPLAY_BOARDINFO=y
 # CONFIG_BOARD_LATE_INIT is not set
 CONFIG_SPL_MAX_SIZE=0x40000
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_SYS_MALLOC=y
 CONFIG_SPL_SYS_MALLOC_SIZE=0x800000
 CONFIG_SPL_OPENSBI_SCRATCH_OPTIONS=0x2
diff --git a/configs/xilinx_zynq_virt_defconfig b/configs/xilinx_zynq_virt_defconfig
index 9196a95e88a..6859e24b731 100644
--- a/configs/xilinx_zynq_virt_defconfig
+++ b/configs/xilinx_zynq_virt_defconfig
@@ -41,6 +41,7 @@ CONFIG_SYS_PBSIZE=2071
 CONFIG_CLOCKS=y
 CONFIG_SPL_MAX_SIZE=0x30000
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_SYS_MALLOC=y
 CONFIG_SPL_SYS_MALLOC_SIZE=0x2000000
 CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot.img"
@@ -50,6 +51,9 @@ CONFIG_SPL_OS_BOOT=y
 CONFIG_SPL_PAYLOAD_ARGS_ADDR=0x10000000
 CONFIG_SPL_SPI_LOAD=y
 CONFIG_SYS_SPI_U_BOOT_OFFS=0x100000
+CONFIG_SYS_SPI_KERNEL_OFFS=0x280000
+CONFIG_SYS_SPI_ARGS_OFFS=0x200000
+CONFIG_SYS_SPI_ARGS_SIZE=0x80000
 CONFIG_SYS_MAXARGS=32
 # CONFIG_BOOTM_NETBSD is not set
 CONFIG_CMD_IMLS=y
diff --git a/configs/xilinx_zynqmp_kria_defconfig b/configs/xilinx_zynqmp_kria_defconfig
index 1a6bd67afb8..1f8e8c348eb 100644
--- a/configs/xilinx_zynqmp_kria_defconfig
+++ b/configs/xilinx_zynqmp_kria_defconfig
@@ -49,6 +49,7 @@ CONFIG_CLOCKS=y
 CONFIG_SPL_MAX_SIZE=0x40000
 # CONFIG_SPL_BINMAN_SYMBOLS is not set
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_FS_LOAD_KERNEL_NAME=""
 CONFIG_SPL_FS_LOAD_ARGS_NAME=""
 CONFIG_SPL_FPGA=y
@@ -57,6 +58,9 @@ CONFIG_SPL_PAYLOAD_ARGS_ADDR=0x8000000
 CONFIG_SPL_RAM_DEVICE=y
 CONFIG_SPL_SPI_LOAD=y
 CONFIG_SYS_SPI_U_BOOT_OFFS=0x80000
+CONFIG_SYS_SPI_KERNEL_OFFS=0x80000
+CONFIG_SYS_SPI_ARGS_OFFS=0xa0000
+CONFIG_SYS_SPI_ARGS_SIZE=0xa0000
 CONFIG_SPL_ATF=y
 CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
 CONFIG_CMD_SMBIOS=y
diff --git a/configs/xilinx_zynqmp_mini_emmc0_defconfig b/configs/xilinx_zynqmp_mini_emmc0_defconfig
index c19f79f4d1d..2ddaecd5875 100644
--- a/configs/xilinx_zynqmp_mini_emmc0_defconfig
+++ b/configs/xilinx_zynqmp_mini_emmc0_defconfig
@@ -31,6 +31,7 @@ CONFIG_CLOCKS=y
 CONFIG_SPL_MAX_SIZE=0x40000
 # CONFIG_SPL_BINMAN_SYMBOLS is not set
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_SYS_MALLOC=y
 CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
 CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x20000000
diff --git a/configs/xilinx_zynqmp_mini_emmc1_defconfig b/configs/xilinx_zynqmp_mini_emmc1_defconfig
index 459e0294715..31bba1712fb 100644
--- a/configs/xilinx_zynqmp_mini_emmc1_defconfig
+++ b/configs/xilinx_zynqmp_mini_emmc1_defconfig
@@ -31,6 +31,7 @@ CONFIG_CLOCKS=y
 CONFIG_SPL_MAX_SIZE=0x40000
 # CONFIG_SPL_BINMAN_SYMBOLS is not set
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_SYS_MALLOC=y
 CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
 CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x20000000
diff --git a/configs/xilinx_zynqmp_mini_qspi_defconfig b/configs/xilinx_zynqmp_mini_qspi_defconfig
index bb855f3b372..f2d0d6f16ed 100644
--- a/configs/xilinx_zynqmp_mini_qspi_defconfig
+++ b/configs/xilinx_zynqmp_mini_qspi_defconfig
@@ -33,6 +33,7 @@ CONFIG_CLOCKS=y
 CONFIG_SPL_MAX_SIZE=0x40000
 # CONFIG_SPL_BINMAN_SYMBOLS is not set
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_SYS_MALLOC=y
 CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
 CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x20000000
diff --git a/configs/xilinx_zynqmp_virt_defconfig b/configs/xilinx_zynqmp_virt_defconfig
index e5e56babf4c..abd1e1bb574 100644
--- a/configs/xilinx_zynqmp_virt_defconfig
+++ b/configs/xilinx_zynqmp_virt_defconfig
@@ -43,6 +43,7 @@ CONFIG_CLOCKS=y
 CONFIG_SPL_MAX_SIZE=0x40000
 # CONFIG_SPL_BINMAN_SYMBOLS is not set
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_SYS_MALLOC=y
 CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
 CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x20000000
@@ -55,6 +56,9 @@ CONFIG_SPL_PAYLOAD_ARGS_ADDR=0x8000000
 CONFIG_SPL_RAM_DEVICE=y
 CONFIG_SPL_SPI_LOAD=y
 CONFIG_SYS_SPI_U_BOOT_OFFS=0x100000
+CONFIG_SYS_SPI_KERNEL_OFFS=0x80000
+CONFIG_SYS_SPI_ARGS_OFFS=0xa0000
+CONFIG_SYS_SPI_ARGS_SIZE=0xa0000
 CONFIG_SPL_ATF=y
 CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
 CONFIG_CMD_SMBIOS=y
diff --git a/configs/zynq_cse_nand_defconfig b/configs/zynq_cse_nand_defconfig
index 972e78fbe52..7d15903bb3a 100644
--- a/configs/zynq_cse_nand_defconfig
+++ b/configs/zynq_cse_nand_defconfig
@@ -32,6 +32,7 @@ CONFIG_SYS_PBSIZE=1047
 CONFIG_CLOCKS=y
 CONFIG_SPL_MAX_SIZE=0x30000
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_SYS_MALLOC=y
 CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
 CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x200000
diff --git a/configs/zynq_cse_nor_defconfig b/configs/zynq_cse_nor_defconfig
index f3e23685157..fe4362d3b03 100644
--- a/configs/zynq_cse_nor_defconfig
+++ b/configs/zynq_cse_nor_defconfig
@@ -32,6 +32,7 @@ CONFIG_SYS_PBSIZE=1047
 CONFIG_CLOCKS=y
 CONFIG_SPL_MAX_SIZE=0x30000
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_SYS_MALLOC=y
 CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
 CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x200000
diff --git a/configs/zynq_cse_qspi_defconfig b/configs/zynq_cse_qspi_defconfig
index 09dbf7ba5a6..824758f8289 100644
--- a/configs/zynq_cse_qspi_defconfig
+++ b/configs/zynq_cse_qspi_defconfig
@@ -39,6 +39,7 @@ CONFIG_SYS_PBSIZE=1047
 CONFIG_CLOCKS=y
 CONFIG_SPL_MAX_SIZE=0x30000
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_SPL_SYS_MALLOC=y
 CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
 CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x200000
diff --git a/doc/README.fuse b/doc/README.fuse
deleted file mode 100644
index 1bc91c44a6a..00000000000
--- a/doc/README.fuse
+++ /dev/null
@@ -1,67 +0,0 @@
-Fuse API functions and commands
-
-The fuse API allows to control a fusebox and how it is used by the upper
-hardware layers.
-
-A fuse corresponds to a single non-volatile memory bit that can be programmed
-(i.e. blown, set to 1) only once. The programming operation is irreversible. A
-fuse that has not been programmed reads 0.
-
-Fuses can be used by SoCs to store various permanent configuration and data,
-e.g. boot configuration, security configuration, MAC addresses, etc.
-
-A fuse word is the smallest group of fuses that can be read at once from the
-fusebox control IP registers. This is limited to 32 bits with the current API.
-
-A fuse bank is the smallest group of fuse words having a common ID, as defined
-by each SoC.
-
-Upon startup, the fusebox control IP reads the fuse values and stores them to a
-volatile shadow cache.
-
-See the README files of the drivers implementing this API in order to know the
-SoC- and implementation-specific details.
-
-Functions / commands:
-
-   int fuse_read(u32 bank, u32 word, u32 *val);
-   fuse read <bank> <word> [<cnt>]
-      Read fuse words from the shadow cache.
-
-   int fuse_sense(u32 bank, u32 word, u32 *val);
-   fuse sense <bank> <word> [<cnt>]
-      Sense - i.e. read directly from the fusebox, skipping the shadow cache -
-      fuse words. This operation does not update the shadow cache.
-
-      This is useful to know the true value of fuses if an override has been
-      performed (see below).
-
-   int fuse_prog(u32 bank, u32 word, u32 val);
-   fuse prog [-y] <bank> <word> <hexval> [<hexval>...]
-      Program fuse words. This operation directly affects the fusebox and is
-      irreversible. The shadow cache is updated accordingly or not, depending on
-      each IP.
-
-      Only the bits to be programmed should be set in the input value (i.e. for
-      fuse bits that have already been programmed and hence should be left
-      unchanged by a further programming, it is preferable to clear the
-      corresponding bits in the input value in order not to perform a new
-      hardware programming operation on these fuse bits).
-
-   int fuse_override(u32 bank, u32 word, u32 val);
-   fuse override <bank> <word> <hexval> [<hexval>...]
-      Override fuse words in the shadow cache.
-
-      The fusebox is unaffected, so following this operation, the shadow cache
-      may differ from the fusebox values. Read or sense operations can then be
-      used to get the values from the shadow cache or from the fusebox.
-
-      This is useful to change the behaviors linked to some cached fuse values,
-      either because this is needed only temporarily, or because some of the
-      fuses have already been programmed or are locked (if the SoC allows to
-      override a locked fuse).
-
-Configuration:
-
-   CONFIG_CMD_FUSE
-      Define this to enable the fuse commands.
diff --git a/doc/arch/sandbox/sandbox.rst b/doc/arch/sandbox/sandbox.rst
index a8b0d7f0395..7e641306da2 100644
--- a/doc/arch/sandbox/sandbox.rst
+++ b/doc/arch/sandbox/sandbox.rst
@@ -658,10 +658,10 @@ that are mapped into that memory:
 ========   ========================   ===============================
 Addr       Config                     Usage
 ========   ========================   ===============================
-     100   CONFIG_SYS_FDT_LOAD_ADDR   Device tree
-    b000   CONFIG_BLOBLIST_ADDR       Blob list
-   10000   CFG_MALLOC_F_ADDR          Early memory allocation
+     100   CONFIG_BLOBLIST_ADDR       Blob list
+    1000   CONFIG_SYS_FDT_LOAD_ADDR   Device tree
    f0000   CONFIG_PRE_CON_BUF_ADDR    Pre-console buffer
+   f4000   CFG_MALLOC_F_ADDR          Early memory allocation
   100000   TCG Event log              TCG Event Log
   200000   CONFIG_TRACE_EARLY_ADDR    Early trace buffer (if enabled). Also used
   400000   CONFIG_TEXT_BASE           Load buffer for U-Boot (sandbox_spl only)
diff --git a/doc/board/amlogic/odroid-n2.rst b/doc/board/amlogic/odroid-n2.rst
index 883720f8fbf..5222a21c808 100644
--- a/doc/board/amlogic/odroid-n2.rst
+++ b/doc/board/amlogic/odroid-n2.rst
@@ -54,10 +54,9 @@ image so it is necessary to obtain binaries from sources published by the board
     $ tar xvfJ gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz
     $ export PATH=$PWD/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux/bin:$PWD/gcc-linaro-arm-none-eabi-4.8-2013.11_linux/bin:$PATH
 
-    $ DIR=odroid-n2
-    $ git clone --depth 1 https://github.com/hardkernel/u-boot.git -b odroidn2-v2015.01 $DIR
+    $ git clone --depth 1 https://github.com/hardkernel/u-boot.git -b odroidg12-v2015.01 odroidg12
 
-    $ cd odroid-n2
+    $ cd odroidg12
     $ make odroidn2_defconfig
     $ make
     $ export UBOOTDIR=$PWD
@@ -74,12 +73,8 @@ Go back to the mainline U-Boot source tree then:
     $ cp $UBOOTDIR/fip/g12b/bl2.bin fip/
     $ cp $UBOOTDIR/fip/g12b/bl30.bin fip/
     $ cp $UBOOTDIR/fip/g12b/bl31.img fip/
-    $ cp $UBOOTDIR/fip/g12b/ddr3_1d.fw fip/
     $ cp $UBOOTDIR/fip/g12b/ddr4_1d.fw fip/
     $ cp $UBOOTDIR/fip/g12b/ddr4_2d.fw fip/
-    $ cp $UBOOTDIR/fip/g12b/diag_lpddr4.fw fip/
-    $ cp $UBOOTDIR/fip/g12b/lpddr4_1d.fw fip/
-    $ cp $UBOOTDIR/fip/g12b/lpddr4_2d.fw fip/
     $ cp $UBOOTDIR/fip/g12b/piei.fw fip/
     $ cp $UBOOTDIR/fip/g12b/aml_ddr.fw fip/
     $ cp u-boot.bin fip/bl33.bin
@@ -113,7 +108,7 @@ Go back to the mainline U-Boot source tree then:
                                           --level v3 --type bl31
     $ $UBOOTDIR/fip/g12b/aml_encrypt_g12b --bl3sig --input fip/bl33.bin --compress lz4 \
                                           --output fip/bl33.bin.enc \
-                                          --level v3 --type bl33 --compress lz4
+                                          --level v3 --type bl33
     $ $UBOOTDIR/fip/g12b/aml_encrypt_g12b --bl2sig --input fip/bl2_new.bin \
                                           --output fip/bl2.n.bin.sig
     $ $UBOOTDIR/fip/g12b/aml_encrypt_g12b --bootmk \
@@ -124,11 +119,7 @@ Go back to the mainline U-Boot source tree then:
                                           --bl33 fip/bl33.bin.enc \
                                           --ddrfw1 fip/ddr4_1d.fw \
                                           --ddrfw2 fip/ddr4_2d.fw \
-                                          --ddrfw3 fip/ddr3_1d.fw \
                                           --ddrfw4 fip/piei.fw \
-                                          --ddrfw5 fip/lpddr4_1d.fw \
-                                          --ddrfw6 fip/lpddr4_2d.fw \
-                                          --ddrfw7 fip/diag_lpddr4.fw \
                                           --ddrfw8 fip/aml_ddr.fw \
                                           --level v3
 
diff --git a/doc/board/armltd/vexpress64.rst b/doc/board/armltd/vexpress64.rst
index a7f771d2667..109337d7fe3 100644
--- a/doc/board/armltd/vexpress64.rst
+++ b/doc/board/armltd/vexpress64.rst
@@ -19,6 +19,11 @@ view", which gives a comprehensive model on which to build and test software.
 The supported FVPs are available free of charge and can be downloaded from the
 Arm developer site [1]_ (user registration might be required).
 
+The Architecture Envelope Models (AEM) FVPs offer virtual platforms for Armv8-A,
+Armv9-A, and Armv8-R architectures, including a comprehensive set of System IP.
+For general use though, the Armv8-A Base Rev C FVP, which emulates a generic 64-bit
+Armv8-A hardware platform, is a suitable option.
+
 Supported features:
 
  * GICv3
@@ -31,6 +36,50 @@ into the TF-A build: ``make PLAT=<platform> all fip BL33=u-boot.bin``
 
 The FVPs can be debugged using Arm Development Studio [2]_.
 
+Building U-Boot
+^^^^^^^^^^^^^^^
+
+Set the ``CROSS_COMPILE`` environment variable as usual, and run:
+
+.. code-block:: bash
+
+    make vexpress_fvp_defconfig
+    make
+
+Running U-Boot
+^^^^^^^^^^^^^^
+
+Set ``CROSS_COMPILE`` as usual and build TF-A:
+
+.. code-block:: bash
+
+    git clone https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git
+    cd trusted-firmware-a
+    make PLAT=fvp BL33=/path/to/u-boot.bin fiptool all fip
+
+This command generates the ROM image `bl1.bin`, and a boot image `fip.bin` in
+TF-A's FIP format [5]_. It contains all images executed by TF-A, including U-Boot.
+Note that TF-A outputs the built binaries into `build/fvp/release/`.
+
+If you already have a FIP image, and are primarily interested in updating the BL33
+image (i.e., U-Boot), use `fiptool` from TF-A:
+
+.. code-block:: bash
+
+    make fiptool
+    tools/fiptool/fiptool update --nt-fw=/path/to/u-boot.bin /path/to/fip.bin
+
+To run the FVP:
+
+.. code-block:: bash
+
+    FVP_Base_RevC-2xAEMvA -C bp.flashloader0.fname=fip.bin \
+        -C bp.secureflashloader.fname=bl1.bin \
+        -C bp.vis.disable_visualisation=1
+
+This setup relies on semi-hosting, as well as, having a kernel image (``Image``)
+and ramdisk (``ramdisk.img``) in the current working directory.
+
 Juno
 ----
 
@@ -43,10 +92,27 @@ Juno is an Arm development board with the following features:
 
 More details can be found in the board documentation [3]_.
 
+Bloblist Support
+----------------
+
+The ``vexpress_fvp_bloblist_defconfig`` configures U-Boot to be compiled for
+Vexpress64 with Bloblist as the primary method for information handoff between
+boot stages. U-Boot offers three methods to set up a bloblist: using a
+predefined bloblist at a specified address, dynamically allocating memory for a
+bloblist, or utilizing a standard passage-provided bloblist with automatic size
+detection.
+
+By default, ``vexpress_fvp_bloblist_defconfig`` uses the standard passage method mandatorily
+(CONFIG_BLOBLIST_PASSAGE_MANDATORY) because TF-A provides a Transfer List in non-secure
+memory that U-Boot can utilise. This Bloblist, which is referred to as a Transfer List in
+TF-A, contains all necessary data for the handoff process, including DT and ACPI
+tables.
+
 References
 ----------
 
-.. [1] https://developer.arm.com/tools-and-software/simulation-models/fixed-virtual-platforms
+.. [1] https://developer.arm.com/Tools%20and%20Software/Fixed%20Virtual%20Platforms/Arm%20Architecture%20FVPs
 .. [2] https://developer.arm.com/tools-and-software/embedded/arm-development-studio
 .. [3] https://developer.arm.com/tools-and-software/development-boards/juno-development-board
-.. [4] https://trustedfirmware-a.readthedocs.io/
\ No newline at end of file
+.. [4] https://trustedfirmware-a.readthedocs.io/
+.. [5] https://trustedfirmware-a.readthedocs.io/en/latest/getting_started/image-terminology.html#firmware-image-package-fip
diff --git a/doc/board/index.rst b/doc/board/index.rst
index b055046e649..7ad1137c94a 100644
--- a/doc/board/index.rst
+++ b/doc/board/index.rst
@@ -43,6 +43,7 @@ Board-specific doc
    microsoft/index
    nxp/index
    openpiton/index
+   ouya/index
    phytec/index
    purism/index
    qualcomm/index
@@ -69,4 +70,5 @@ Board-specific doc
    variscite/index
    wexler/index
    xen/index
+   xiaomi/index
    xilinx/index
diff --git a/doc/board/ouya/index.rst b/doc/board/ouya/index.rst
new file mode 100644
index 00000000000..7413240a1b8
--- /dev/null
+++ b/doc/board/ouya/index.rst
@@ -0,0 +1,9 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+OUYA
+====
+
+.. toctree::
+   :maxdepth: 2
+
+   ouya
diff --git a/doc/board/ouya/ouya.rst b/doc/board/ouya/ouya.rst
new file mode 100644
index 00000000000..641affc6294
--- /dev/null
+++ b/doc/board/ouya/ouya.rst
@@ -0,0 +1,124 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+U-Boot for the Ouya Game Console (ouya)
+=======================================
+
+``DISCLAMER!`` Moving your Ouya to use U-Boot assumes replacement of the
+vendor bootloader. Vendor android firmwares will no longer be able to run on the
+device. This replacement IS reversible.
+
+Quick Start
+-----------
+
+- Build U-Boot
+- Process U-Boot
+- Flashing U-Boot into the eMMC
+- Boot
+- Self Upgrading
+
+Build U-Boot
+------------
+
+.. code-block:: bash
+
+    $ export CROSS_COMPILE=arm-none-eabi-
+    $ make ouya_defconfig
+    $ make
+
+After the build succeeds, you will obtain the final ``u-boot-dtb-tegra.bin``
+image, ready for further processing.
+
+Process U-Boot
+--------------
+
+``DISCLAMER!`` All questions related to the re-crypt work should be asked
+in re-crypt repo issues. NOT HERE!
+
+re-crypt is a tool that processes the ``u-boot-dtb-tegra.bin`` binary into form
+usable by device. This process is required only on the first installation or
+to recover the device in case of a failed update.
+
+Permanent installation can be performed either by using the nv3p protocol or by
+pre-loading just built U-Boot into RAM.
+
+Processing for the NV3P protocol
+********************************
+
+.. code-block:: bash
+
+    $ git clone https://gitlab.com/grate-driver/re-crypt.git
+    $ cd re-crypt # place your u-boot-dtb-tegra.bin here
+    $ ./re-crypt.py --dev ouya
+
+The script will produce a ``repart-block.bin`` ready to flash.
+
+Processing for pre-loaded U-Boot
+********************************
+
+The procedure is the same, but the ``--split`` argument is used with the
+``re-crypt.py``. The script will produce ``bct.img`` and ``ebt.img`` ready
+to flash.
+
+Flashing U-Boot into the eMMC
+-----------------------------
+
+Permanent installation can be performed either by using the nv3p protocol or by
+pre-loading just built U-Boot into RAM. Regardless of the method bct and bootloader
+will end up in boot0 and boot1 partitions of eMMC.
+
+Flashing with the NV3P protocol
+*******************************
+
+``DISCLAMER!`` All questions related to NvFlash should be asked in the proper
+place. NOT HERE! Flashing U-Boot will erase all eMMC, so make a backup before!
+
+Nv3p is a custom Nvidia protocol used to recover bricked devices. Devices can
+enter it by pre-loading vendor bootloader with the Fusée Gelée.
+
+With nv3p, ``repart-block.bin`` is used. It contains BCT and a bootloader in
+encrypted state in form, which can just be written RAW at the start of eMMC.
+
+.. code-block:: bash
+
+    $ ./run_bootloader.sh -s T30 -t ./bct/ouya.bct -b android_bootloader.bin
+    $ ./utiils/nvflash_v1.13.87205 --resume --rawdevicewrite 0 1024 repart-block.bin
+
+When flashing is done, reboot the device.
+
+Flashing with a pre-loaded U-Boot
+*********************************
+
+U-Boot pre-loaded into RAM acts the same as when it was booted "cold". Currently
+U-Boot supports bootmenu entry fastboot, which allows to write a processed copy
+of U-Boot permanently into eMMC.
+
+While pre-loading U-Boot, interrupt bootflow by pressing ``CTRL + C`` (USB keyboard
+must be plugged in before U-Boot is preloaded, else it will not work), input
+``bootmenu`` from the keyboard and hit enter. The bootmenu will appear. There, select
+``fastboot`` using the up and down arrows and enter key. After, on host PC, do:
+
+.. code-block:: bash
+
+    $ fastboot flash 0.1 bct.img
+    $ fastboot flash 0.2 ebt.img
+    $ fastboot reboot
+
+Device will reboot.
+
+Boot
+----
+
+To boot Linux, U-Boot will look for an ``extlinux.conf`` on eMMC. Additionally,
+bootmenu provides entries to mount eMMC as mass storage, fastboot, reboot,
+reboot RCM, poweroff, enter U-Boot console and update bootloader (check
+the next chapter).
+
+Flashing ``repart-block.bin`` eliminates vendor restrictions on eMMC and allows
+the user to use/partition it in any way the user desires.
+
+Self Upgrading
+--------------
+
+Place your ``u-boot-dtb-tegra.bin`` on the first partition of the USB. Enter
+bootmenu, choose update bootloader option with Enter and U-Boot should update
+itself. Once the process is completed, U-Boot will ask to press any button to reboot.
diff --git a/doc/board/phytec/k3-common.rst b/doc/board/phytec/k3-common.rst
new file mode 100644
index 00000000000..ffb50b51ad6
--- /dev/null
+++ b/doc/board/phytec/k3-common.rst
@@ -0,0 +1,67 @@
+.. SPDX-License-Identifier: GPL-2.0+
+.. sectionauthor:: Wadim Egorov <w.egorov@phytec.de>
+
+Environment
+-----------
+
+
+Variables Set at Runtime
+~~~~~~~~~~~~~~~~~~~~~~~~
+
+At runtime the `boot` environment variable is set to reflect the source from which the board was booted. This ensures that the correct boot path is followed for further system initialization.
+
+
+Environment Storage Selection
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+The environment is loaded from a storage location based on the boot device:
+
+* If booted from eMMC or uSD card, the environment is retrieved from FAT or a fixed offset if configured.
+
+* If booted from SPI, the environment is retrieved from SPI flash if enabled.
+
+For all other boot devices, the environment is not stored persistently (ENVL_NOWHERE).
+
+
+Saving the Environment
+~~~~~~~~~~~~~~~~~~~~~~
+
+The `saveenv` command will store the environment on the same device the board was booted from, ensuring consistency between boot sources and stored configurations.
+
+
+Capsule Updates
+---------------
+
+Capsules for each of these binaries are automatically generated as part of the build process and are named `<binary>-capsule.bin`. For example, the capsule for `u-boot.img` is named `uboot-capsule.bin`.
+
+
+
+Performing an Update
+~~~~~~~~~~~~~~~~~~~~
+
+Each board has a dynamically generated GUID. To retrieve it, run:
+
+.. code-block::
+
+ efidebug capsule esrt
+
+To update the firmware, follow these steps on the board. Ensure the capsule binaries are available on a uSD card.
+
+.. code-block:: bash
+
+ load mmc 1:1 $loadaddr tiboot3-capsule.bin
+ efidebug capsule update $loadaddr
+
+ load mmc 1:1 $loadaddr tispl-capsule.bin
+ efidebug capsule update $loadaddr
+
+ load mmc 1:1 $loadaddr uboot-capsule.bin
+ efidebug capsule update $loadaddr
+
+These commands load the capsule binaries into memory and trigger the EFI capsule update process.
+
+
+Important Notes
+~~~~~~~~~~~~~~~
+
+The updates are applied to the boot device from which the board is currently running. For eMMC, updates are always applied to the first boot partition. Capsule updates can be performed on eMMC, OSPI NOR, or a uSD card, depending on the boot device. For any additional configuration or troubleshooting, refer to :ref:`uefi_capsule_update_ref`.
diff --git a/doc/board/phytec/phycore-am62ax.rst b/doc/board/phytec/phycore-am62ax.rst
index 0c5b4814fc2..e1f741011e7 100644
--- a/doc/board/phytec/phycore-am62ax.rst
+++ b/doc/board/phytec/phycore-am62ax.rst
@@ -176,6 +176,8 @@ Boot switches should be changed with power off.
      - 11011100
      - 00000000
 
+.. include:: k3-common.rst
+
 Further Information
 -------------------
 
diff --git a/doc/board/phytec/phycore-am62x.rst b/doc/board/phytec/phycore-am62x.rst
index 56c1fd8354b..36315b49931 100644
--- a/doc/board/phytec/phycore-am62x.rst
+++ b/doc/board/phytec/phycore-am62x.rst
@@ -176,6 +176,8 @@ Boot switches should be changed with power off.
      - 11001010
      - 00100000
 
+.. include:: k3-common.rst
+
 Further Information
 -------------------
 
diff --git a/doc/board/phytec/phycore-am64x.rst b/doc/board/phytec/phycore-am64x.rst
index 01c42b90660..71f1fd7b404 100644
--- a/doc/board/phytec/phycore-am64x.rst
+++ b/doc/board/phytec/phycore-am64x.rst
@@ -175,6 +175,8 @@ Boot switches should be changed with power off.
      - 11011100
      - 00000000
 
+.. include:: k3-common.rst
+
 Further Information
 -------------------
 
diff --git a/doc/board/qualcomm/index.rst b/doc/board/qualcomm/index.rst
index 8c7969987a9..66bc922033a 100644
--- a/doc/board/qualcomm/index.rst
+++ b/doc/board/qualcomm/index.rst
@@ -10,3 +10,4 @@ Qualcomm
    rb3gen2
    board
    debugging
+   rdp
diff --git a/doc/board/qualcomm/rdp.rst b/doc/board/qualcomm/rdp.rst
new file mode 100644
index 00000000000..fd14f1d9829
--- /dev/null
+++ b/doc/board/qualcomm/rdp.rst
@@ -0,0 +1,55 @@
+.. SPDX-License-Identifier: GPL-2.0
+.. sectionauthor:: Varadarajan Narayanan <quic_varada@quicinc.com>
+
+Qualcomm Reference Design Platform (RDP)
+========================================
+
+Qualcomm RDPs are development boards based on the Qualcomm IPQ series of
+SoCs. These SoCs are used as the application processors in WiFi router
+platforms. RDPs come in multiple variants with differences in storage
+medium (NOR, NAND, MMC), no. of USB and PCIe ports, n/w ports etc.
+
+.. _Qualcomm's product page: https://www.qualcomm.com/products/internet-of-things/networking/wi-fi-networks/networking-pro-series/qualcomm-networking-pro-820-platform
+
+Installation
+------------
+First, setup ``CROSS_COMPILE`` for aarch64. Then, build U-Boot for ``IPQ9574``::
+
+  $ export CROSS_COMPILE=<aarch64 toolchain prefix>
+  $ make qcom_ipq9574_mmc_defconfig
+  $ make -j8
+
+This will build ``u-boot.elf`` in the configured output directory.
+
+Although the RDPs do not have secure boot set up by default, the firmware still
+expects firmware ELF images to be "signed". The signature does not provide any
+security in this case, but it provides the firmware with some required metadata.
+
+To "sign" ``u-boot.elf`` you can use e.g. `qtestsign`_::
+
+  $ qtestsign -v6 aboot -o u-boot.mbn u-boot.elf
+
+Then install the resulting ``u-boot.mbn`` to the ``0:APPSBL`` partition
+on your device with::
+
+  IPQ9574# tftpboot path/to/u-boot.mbn
+  IPQ9574# mmc part (note down the start & end block no.s of '0:APPSBL' partition)
+  IPQ9574# mmc erase <start blk no> <count>
+  IPQ9574# mmc write $fileaddr <blk no> <count>
+
+U-Boot should be running after a reboot (``reset``).
+
+.. WARNING
+	Boards with newer software versions would automatically go the emergency
+	download (EDL) mode if U-Boot is not functioning as expected. If its a
+	runtime failure at Uboot, the system will get reset (due to watchdog)
+	and XBL will try to boot from next bank and if Bank B also doesn't have
+	a functional image and is not booting fine, then the system will enter
+	EDL.  A tool like bkerler's `edl`_ can be used for flashing with the
+	firehose loader binary appropriate for the board.
+
+	Note that the support added is very basic. Restoring the original U-Boot
+	on boards with older version of the software requires a debugger.
+
+.. _qtestsign: https://github.com/msm8916-mainline/qtestsign
+.. _edl: https://github.com/bkerler/edl
diff --git a/doc/board/xiaomi/index.rst b/doc/board/xiaomi/index.rst
new file mode 100644
index 00000000000..109ab4a251f
--- /dev/null
+++ b/doc/board/xiaomi/index.rst
@@ -0,0 +1,9 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+Xiaomi
+======
+
+.. toctree::
+   :maxdepth: 2
+
+   mocha
diff --git a/doc/board/xiaomi/mocha.rst b/doc/board/xiaomi/mocha.rst
new file mode 100644
index 00000000000..be3e333127b
--- /dev/null
+++ b/doc/board/xiaomi/mocha.rst
@@ -0,0 +1,112 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+U-Boot for the Xiaomi Mi Pad tablet
+===================================
+
+``DISCLAMER!`` Moving your Xiaomi Mi Pad to use U-Boot assumes replacement
+of the vendor bootloader. Vendor Android firmwares will no longer be able
+to run on the device. This replacement IS reversible.
+
+Quick Start
+-----------
+
+- Build U-Boot
+- Boot U-Boot
+- Process and flash U-Boot
+- Boot Linux
+- Self Upgrading
+- Chainload configuration
+
+Build U-Boot
+------------
+
+.. code-block:: bash
+
+    $ export CROSS_COMPILE=arm-none-eabi-
+    $ make mocha_defconfig
+    $ make
+
+After the build succeeds, you will obtain the final ``u-boot-dtb-tegra.bin``
+image, ready for booting or further processing.
+
+Boot U-Boot
+-----------
+Existing tegrarcm loader can be used to pre-load U-Boot you have build
+into RAM and basically perform a tethered cold-boot.
+
+.. code-block:: bash
+
+    $ tegrarcm --bct mocha.bct --bootloader u-boot-dtb-tegra.bin --loadaddr 0x80108000
+
+U-Boot will try to load Linux kernel and if fails, it will turn the
+tablet off. While pre-loading U-Boot, hold the ``volume down`` button
+which will trigger the bootmenu.
+
+Process and flash U-Boot
+------------------------
+
+``DISCLAMER!`` All questions related to the re-crypt work should be asked
+in re-crypt repo issues. NOT HERE!
+
+re-crypt is a tool that processes the ``u-boot-dtb-tegra.bin`` binary into
+form usable by device. This process is required only on the first
+installation or to recover the device in case of a failed update.
+
+.. code-block:: bash
+
+    $ git clone https://gitlab.com/grate-driver/re-crypt.git
+    $ cd re-crypt # place your u-boot-dtb-tegra.bin here
+    $ ./re-crypt.py --dev mocha
+
+The script will produce ``bct.img`` and ``ebt.img`` ready to flash.
+
+Permanent installation can be performed by pre-loading just built U-Boot
+into RAM via tegrarcm. While pre-loading U-Boot, hold the ``volume down``
+button which will trigger the bootmenu. There, select ``fastboot`` using
+the volume and power buttons.
+
+After, on host PC, do:
+
+.. code-block:: bash
+
+    $ fastboot flash 0.1 bct.img
+    $ fastboot flash 0.2 ebt.img
+    $ fastboot reboot
+
+Device will reboot.
+
+Boot Linux
+----------
+
+To boot Linux, U-Boot will look for an ``extlinux.conf`` on MicroSD and then on
+eMMC. Additionally, if the ``volume down`` button is pressed while booting, the
+device will enter bootmenu. Bootmenu contains entries to mount MicroSD and eMMC
+as mass storage, fastboot, reboot, reboot RCM, poweroff, enter U-Boot console
+and update bootloader (check the next chapter).
+
+Flashing ``bct.img`` and ``ebt.img`` eliminates vendor restrictions on eMMC and
+allows the user to use/partition it in any way the user desires.
+
+Self Upgrading
+--------------
+
+Place your ``u-boot-dtb-tegra.bin`` on the first partition of the MicroSD card
+and insert it into the tablet. Enter bootmenu, choose update the bootloader
+option with the Power button and U-Boot should update itself. Once the process
+is completed, U-Boot will ask to press any button to reboot.
+
+Chainload configuration
+-----------------------
+
+To build U-Boot without SPL suitable for chainloading adjust mocha_defconfig:
+
+.. code-block::
+
+  CONFIG_TEXT_BASE=0x80A00000
+  CONFIG_SKIP_LOWLEVEL_INIT=y
+  # CONFIG_OF_BOARD_SETUP is not set
+  CONFIG_TEGRA_SUPPORT_NON_SECURE=y
+
+After the build succeeds, you will obtain the final ``u-boot-dtb.bin``
+file, ready for booting using vendor bootloader's fastboot or which can be
+further processed into a flashable image.
diff --git a/doc/develop/bootstd/overview.rst b/doc/develop/bootstd/overview.rst
index e3ce97cc4f5..9fe5630ab16 100644
--- a/doc/develop/bootstd/overview.rst
+++ b/doc/develop/bootstd/overview.rst
@@ -235,8 +235,9 @@ means that `default_get_bootflow()` is used. This simply obtains the
 block device and calls a bootdev helper function to do the rest. The
 implementation of `bootdev_find_in_blk()` checks the partition table, and
 attempts to read a file from a filesystem on the partition number given by the
-`@iter->part` parameter. If there are any bootable partitions in the table,
-then only bootable partitions are considered.
+`@iter->part` parameter. If there are any bootable partitions in the table and
+the BOOTFLOWIF_ONLY_BOOTABLE flag is set in `@iter->flags`, then only bootable
+partitions are considered.
 
 Each bootdev has a priority, which indicates the order in which it is used,
 if `boot_targets` is not used. Faster bootdevs are used first, since they are
diff --git a/doc/develop/driver-model/design.rst b/doc/develop/driver-model/design.rst
index 92f638a0204..30093737200 100644
--- a/doc/develop/driver-model/design.rst
+++ b/doc/develop/driver-model/design.rst
@@ -843,8 +843,10 @@ steps (see device_probe()):
       activated and 'known' by the uclass.
 
 For some platforms, certain devices must be probed to get the platform into
-a working state. To help with this, drivers marked with DM_FLAG_PROBE_AFTER_BIND
-will be probed immediately after all devices are bound. For now, this happens in
+a working state. To help with this, devices marked with DM_FLAG_PROBE_AFTER_BIND
+will be probed immediately after all devices are bound. This flag must be set
+on the device in its ``bind()`` function with
+``dev_or_flags(dev, DM_FLAG_PROBE_AFTER_BIND)``. For now, this happens in
 SPL, before relocation and after relocation. See the call to ``dm_autoprobe()``
 for where this is done.
 
diff --git a/doc/develop/py_testing.rst b/doc/develop/py_testing.rst
index b50473039be..40a85380343 100644
--- a/doc/develop/py_testing.rst
+++ b/doc/develop/py_testing.rst
@@ -125,7 +125,7 @@ browser, but may be read directly as plain text, perhaps with the aid of the
 If sandbox crashes (e.g. with a segfault) you will see message like this::
 
 
-    test/py/u_boot_spawn.py:171: in expect
+    test/py/spawn.py:171: in expect
         c = os.read(self.fd, 1024).decode(errors='replace')
     E   ValueError: U-Boot exited with signal 11 (Signals.SIGSEGV)
 
@@ -506,24 +506,24 @@ Writing tests
 Please refer to the pytest documentation for details of writing pytest tests.
 Details specific to the U-Boot test suite are described below.
 
-A test fixture named `u_boot_console` should be used by each test function. This
+A test fixture named `ubman` should be used by each test function. This
 provides the means to interact with the U-Boot console, and retrieve board and
 environment configuration information.
 
-The function `u_boot_console.run_command()` executes a shell command on the
+The function `ubman.run_command()` executes a shell command on the
 U-Boot console, and returns all output from that command. This allows
 validation or interpretation of the command output. This function validates
 that certain strings are not seen on the U-Boot console. These include shell
 error messages and the U-Boot sign-on message (in order to detect unexpected
-board resets). See the source of `u_boot_console_base.py` for a complete list of
+board resets). See the source of `console_base.py` for a complete list of
 "bad" strings. Some test scenarios are expected to trigger these strings. Use
-`u_boot_console.disable_check()` to temporarily disable checking for specific
+`ubman.disable_check()` to temporarily disable checking for specific
 strings. See `test_unknown_cmd.py` for an example.
 
 Board- and board-environment configuration values may be accessed as sub-fields
-of the `u_boot_console.config` object, for example
-`u_boot_console.config.ram_base`.
+of the `ubman.config` object, for example
+`ubman.config.ram_base`.
 
 Build configuration values (from `.config`) may be accessed via the dictionary
-`u_boot_console.config.buildconfig`, with keys equal to the Kconfig variable
+`ubman.config.buildconfig`, with keys equal to the Kconfig variable
 names.
diff --git a/doc/develop/tests_writing.rst b/doc/develop/tests_writing.rst
index 54efb7e1b04..7ea17081def 100644
--- a/doc/develop/tests_writing.rst
+++ b/doc/develop/tests_writing.rst
@@ -116,19 +116,19 @@ below are approximate, as measured on an AMD 2950X system. Here is is the test
 in Python::
 
    @pytest.mark.buildconfigspec('cmd_memory')
-   def test_md(u_boot_console):
+   def test_md(ubman):
        """Test that md reads memory as expected, and that memory can be modified
        using the mw command."""
 
-       ram_base = u_boot_utils.find_ram_base(u_boot_console)
+       ram_base = utils.find_ram_base(ubman)
        addr = '%08x' % ram_base
        val = 'a5f09876'
        expected_response = addr + ': ' + val
-       u_boot_console.run_command('mw ' + addr + ' 0 10')
-       response = u_boot_console.run_command('md ' + addr + ' 10')
+       ubman.run_command('mw ' + addr + ' 0 10')
+       response = ubman.run_command('md ' + addr + ' 10')
        assert(not (expected_response in response))
-       u_boot_console.run_command('mw ' + addr + ' ' + val)
-       response = u_boot_console.run_command('md ' + addr + ' 10')
+       ubman.run_command('mw ' + addr + ' ' + val)
+       response = ubman.run_command('md ' + addr + ' 10')
        assert(expected_response in response)
 
 This runs a few commands and checks the output. Note that it runs a command,
@@ -261,7 +261,7 @@ with the suite. For example, to add a new mem_search test::
    /* Test 'ms' command with 32-bit values */
    static int mem_test_ms_new_thing(struct unit_test_state *uts)
    {
-         /* test code here*/
+         /* test code here */
 
          return 0;
    }
@@ -291,32 +291,20 @@ suite. For example::
    /* Declare a new wibble test */
    #define WIBBLE_TEST(_name, _flags)   UNIT_TEST(_name, _flags, wibble_test)
 
-   /* Tetss go here */
-
-   /* At the bottom of the file: */
-
-   int do_ut_wibble(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
-   {
-     struct unit_test *tests = UNIT_TEST_SUITE_START(wibble_test);
-     const int n_ents = UNIT_TEST_SUITE_COUNT(wibble_test);
-
-     return cmd_ut_category("cmd_wibble", "wibble_test_", tests, n_ents, argc, argv);
-   }
+   /* Tests go here */
 
 Then add new tests to it as above.
 
 Register this new suite in test/cmd_ut.c by adding to cmd_ut_sub[]::
 
-  /* Within cmd_ut_sub[]... */
-
-  U_BOOT_CMD_MKENT(wibble, CONFIG_SYS_MAXARGS, 1, do_ut_wibble, "", ""),
+  /* with the other SUITE_DECL() declarations */
+  SUITE_DECL(wibble);
 
-and adding new help to ut_help_text[]::
+  /* Within suites[]... */
+  SUITE(wibble, "my test of wibbles");
 
-  "ut wibble - Test the wibble feature\n"
-
-If your feature is conditional on a particular Kconfig, then you can use #ifdef
-to control that.
+If your feature is conditional on a particular Kconfig, you do not need to add
+an #ifdef since the suite will automatically be compiled out in that case.
 
 Finally, add the test to the build by adding to the Makefile in the same
 directory::
@@ -326,17 +314,35 @@ directory::
 Note that CMDLINE is never enabled in SPL, so this test will only be present in
 U-Boot proper. See below for how to do SPL tests.
 
-As before, you can add an extra Kconfig check if needed::
+You can add an extra Kconfig check if needed::
 
   ifneq ($(CONFIG_$(XPL_)WIBBLE),)
   obj-$(CONFIG_$(XPL_)CMDLINE) += wibble.o
   endif
 
+Each suite can have an optional init and uninit function. These are run before
+and after any suite tests, respectively::
+
+   #define WIBBLE_TEST_INIT(_name, _flags)  UNIT_TEST_INIT(_name, _flags, wibble_test)
+   #define WIBBLE_TEST_UNINIT(_name, _flags)  UNIT_TEST_UNINIT(_name, _flags, wibble_test)
 
-Example commit: 919e7a8fb64 ("test: Add a simple test for bloblist") [1]
+   static int wibble_test_init(struct unit_test_state *uts)
+   {
+         /* init code here */
+
+         return 0;
+   }
+   WIBBLE_TEST_INIT(wibble_test_init, 0);
 
-[1] https://gitlab.denx.de/u-boot/u-boot/-/commit/919e7a8fb64
+   static int wibble_test_uninit(struct unit_test_state *uts)
+   {
+         /* uninit code here */
+
+         return 0;
+   }
+   WIBBLE_TEST_INIT(wibble_test_uninit, 0);
 
+Both functions are included in the totals for each suite.
 
 Making the test run from pytest
 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
diff --git a/doc/device-tree-bindings/mtd/cadence,nand.yaml b/doc/device-tree-bindings/mtd/cadence,nand.yaml
new file mode 100644
index 00000000000..11ce023ec64
--- /dev/null
+++ b/doc/device-tree-bindings/mtd/cadence,nand.yaml
@@ -0,0 +1,98 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mtd/cadence,nand.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Cadence NAND controller
+
+maintainers:
+  - Dinesh Maniyam <dinesh.maniyam@intel.com>
+
+properties:
+  compatible:
+    enum:
+      - cdns,nand
+
+  reg-names:
+    description: |
+      There are two register regions:
+        reg:  register interface
+        sdma: host data/command interface
+    items:
+      - const: reg
+      - const: sdma
+
+  reg:
+    minItems: 2
+    maxItems: 2
+
+  interrupts:
+    maxItems: 1
+
+  clocks:
+    description: |
+      There is one controller core clock
+    maxItems: 1
+
+  resets:
+    description: |
+      There are two resets:
+        controller core reset
+        combo-phy register reset
+    minItems: 1
+    maxItems: 2
+
+  cdns,board-delay-ps:
+     description: |
+        Estimated Board delay. The value includes the total
+        round trip delay for the signals and is used for deciding on values
+        associated with data read capture. The example formula for SDR mode is
+        the following:
+        board delay = RE#PAD delay + PCB trace to device + PCB trace from device
+        + DQ PAD delay
+     enum:
+       - 4830
+
+patternProperties:
+  "^nand@[a-f0-9]$":
+    type: object
+    properties:
+      compatible:
+        const: cdns,nand
+
+      reg:
+        maxItems: 1
+
+      label:
+        maxItems: 1
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - clocks
+  - cdns,board-delay-ps
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    nand-controller@60000000 {
+        compatible = "cdns,nand";
+        reg = <0x60000000 0x10000>, <0x80000000 0x1000>;
+        reg-names = "reg", "sdma";
+        #address-cells = <1>;
+        #size-cells = <0>;
+        clocks = <&clk>;
+        cdns,board-delay-ps = <4830>;
+        interrupts = <2 0>;
+        nand@0 {
+            label = "nand-0";
+            reg = <0>;
+        };
+        nand@1 {
+            label = "nand-1";
+            reg = <1>;
+        };
+    };
diff --git a/doc/device-tree-bindings/pinctrl/adi,adsp-pinctrl.yaml b/doc/device-tree-bindings/pinctrl/adi,adsp-pinctrl.yaml
new file mode 100644
index 00000000000..418ebd5ce41
--- /dev/null
+++ b/doc/device-tree-bindings/pinctrl/adi,adsp-pinctrl.yaml
@@ -0,0 +1,73 @@
+# SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pinctrl/adi,adsp-pinctrl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Pinctrl Driver for Analog Devices SC5xx Processors
+
+maintainers:
+  - Vasileios Bimpikas <vasileios.bimpikas@analog.com>
+  - Utsav Agarwal <utsav.agarwal@analog.com>
+  - Arturs Artamonovs <arturs.artamonovs@analog.com>
+
+description: |
+  This driver provides an interface for performing pin configuration
+  Analog Devices SoCs using the ADSP PORT hardware for pin
+  configuration according to the HRM. Currently this is only the
+  SC5xx series.
+
+properties:
+  compatible:
+    const: adi,adsp-pinctrl
+
+  reg:
+    maxItems: 1
+
+  adi,npins:
+    $ref: /schemas/types.yaml#/definitions/uint32
+    description:
+      Total number of pins available to this SoC's pin controller,
+      found in the HRM.
+
+patternProperties:
+  '_pins$':
+    type: object
+
+    properties:
+      adi,pins:
+        $ref: /schemas/types.yaml#/definitions/uint32-array
+        description:
+          For n pins, 2n values must be provided as a sequence of pin
+          name as identified with the ADI_ADSP_PIN() macro and a pin
+          function constant, both defined in
+          include/dt-bindings/pinctrl/adi-adsp.h.
+
+    required:
+     - adi,pins
+
+    additionalProperties: false
+
+required:
+  - compatible
+  - reg
+  - adi,npins
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/pinctrl/adi-adsp.h>
+
+    soc {
+      pinctrl0: pinctrl@0x31004000 {
+        compatible = "adi,adsp-pinctrl";
+        reg = <0x31004000 0x500>;
+        adi,npins = <135>;
+        uart0_default: uart0_pins {
+          adi,pins = <ADI_ADSP_PIN('A', 6) ADI_ADSP_PINFUNC_ALT1>,
+                     <ADI_ADSP_PIN('A', 7) ADI_ADSP_PINFUNC_ALT1>;
+        };
+      };
+
+    };
diff --git a/doc/usage/cmd/acpi.rst b/doc/usage/cmd/acpi.rst
index 9f30972fe53..e652968d584 100644
--- a/doc/usage/cmd/acpi.rst
+++ b/doc/usage/cmd/acpi.rst
@@ -11,7 +11,7 @@ Synopsis
 
 ::
 
-    acpi list
+    acpi list [-c]
     acpi items [-d]
     acpi dump <name>
     acpi set <address>
@@ -38,6 +38,9 @@ List the ACPI tables that have been generated. Each table has a 4-character
 table name (e.g. SSDT, FACS) and has a format defined by the
 `ACPI specification`_.
 
+The `-c` flag tells U-Boot to verify the checksums and print 'OK' or 'BAD' next
+to each table.
+
 U-Boot does not currently support decoding the tables. Unlike devicetree, ACPI
 tables have no regular schema and also some include bytecode, so decoding the
 tables requires a lot of code.
@@ -259,5 +262,20 @@ pointer::
     WAET  bff76a3b     28  v01 BOCHS  BXPC     1 BXPC 1
     SSDT  bff95040     c5  v02 COREv4 COREBOOT 2a CORE 20221020
 
+This shows checking that the checksums are correct for each table::
+
+    => acpi list -c
+    Name              Base   Size  Detail
+    ----  ----------------  -----  ----------------------------
+    RSDP          bec9a000     24  v00 BOCHS   OK OK
+    RSDT          bec9bd4a     38  v01 BOCHS  BXPC     1 BXPC 1  OK
+    FACP          bec9bb46     74  v01 BOCHS  BXPC     1 BXPC 1  OK
+    DSDT          bec9a080   1ac6  v01 BOCHS  BXPC     1 BXPC 1  OK
+    FACS          bec9a040     40
+    APIC          bec9bbba     78  v03 BOCHS  BXPC     1 BXPC 1  OK
+    HPET          bec9bc32     38  v01 BOCHS  BXPC     1 BXPC 1  OK
+    SRAT          bec9bc6a     b8  v01 BOCHS  BXPC     1 BXPC 1  OK
+    WAET          bec9bd22     28  v01 BOCHS  BXPC     1 BXPC 1  OK
+
 
 .. _`ACPI specification`: https://uefi.org/sites/default/files/resources/ACPI_6_3_final_Jan30.pdf
diff --git a/doc/usage/cmd/fuse.rst b/doc/usage/cmd/fuse.rst
new file mode 100644
index 00000000000..42c6e209f99
--- /dev/null
+++ b/doc/usage/cmd/fuse.rst
@@ -0,0 +1,176 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+.. index::
+   single: fuse (command)
+
+fuse command
+============
+
+Synopsis
+--------
+
+::
+
+    fuse read <bank> <word> [<cnt>]
+    fuse cmp <bank> <word> <hexval>
+    fuse readm <bank> <word> <addr> [<cnt>]
+    fuse sense <bank> <word> [<cnt>]
+    fuse prog [-y] <bank> <word> <hexval> [<hexval>...]
+    fuse override <bank> <word> <hexval> [<hexval>...]
+    fuse writebuff [-y] <addr>
+
+Description
+-----------
+
+The fuse API allows to control a fusebox and how it is used by the upper
+hardware layers.
+
+A fuse corresponds to a single non-volatile memory bit that can be programmed
+(i.e., blown, set to 1) only once. The programming operation is irreversible.
+A fuse that has not been programmed reads as 0.
+
+Fuses can be used by SoCs to store various permanent configurations and data,
+such as boot configurations, security settings, MAC addresses, etc.
+
+A fuse 'word' is the smallest group of fuses that can be read at once from
+the fusebox control IP registers. In the current API, this is limited to 32 bits.
+
+A fuse 'bank' is the smallest group of fuse words having a common ID, as
+defined by each SoC.
+
+Upon startup, the fusebox control IP reads the fuse values and stores them in a
+volatile shadow cache.
+
+Commands
+--------
+
+- **fuse read <bank> <word> [<cnt>]**
+  Reads 1 or 'cnt' fuse words, starting at 'word' from the shadow cache.
+
+- **fuse cmp <bank> <word> <hexval>**
+  Compares 'hexval' to fuse at 'word'.
+
+- **fuse readm <bank> <word> <addr> [<cnt>]**
+  Reads 1 or 'cnt' fuse words, starting at 'word' into memory at 'addr'.
+
+- **fuse sense <bank> <word> [<cnt>]**
+  Sense 1 or 'cnt' fuse words, starting at 'word'.
+  Sense - i.e. read directly from the fusebox, skipping the shadow cache -
+  fuse words. This operation does not update the shadow cache. This is
+  useful to know the true value of fuses if an override has been
+  performed (see below).
+
+- **fuse prog [-y] <bank> <word> <hexval> [<hexval>...]**
+  Permanently programs 1 or several fuse words, starting at 'word'.
+  This operation directly affects the fusebox and is irreversible. The
+  shadow cache is updated accordingly or not, depending on each IP.
+  Only the bits to be programmed should be set in the input value (i.e.
+  for fuse bits that have already been programmed and hence should be
+  left unchanged by a further programming, it is preferable to clear
+  the corresponding bits in the input value in order not to perform a
+  new hardware programming operation on these fuse bits).
+
+- **fuse override <bank> <word> <hexval> [<hexval>...]**
+  Override 1 or several fuse words, starting at 'word' in the shadow cache.
+  The fusebox is unaffected, so following this operation, the shadow cache
+  may differ from the fusebox values. Read or sense operations can then be
+  used to get the values from the shadow cache or from the fusebox.
+  This is useful to change the behaviours linked to some cached fuse values,
+  either because this is needed only temporarily, or because some of the
+  fuses have already been programmed or are locked (if the SoC allows to
+  override a locked fuse).
+
+- **fuse writebuff [-y] <addr>**
+  Programs fuse data using a structured buffer in memory starting at 'addr'.
+  This operation directly affects the fusebox and is irreversible.
+
+  The structure of the buffer should contain all necessary details for
+  programming fuses, such as the values to be written to the fuse, optional
+  metadata for validation or programming constraints and any configuration
+  data required for the operation. Define CONFIG_CMD_FUSE_WRITEBUFF to
+  enable the fuse writebuff command.
+
+Examples
+--------
+
+fuse read
+~~~~~~~~~
+
+::
+
+    u-boot=> fuse read 0 1
+      Reading bank 0:
+
+      Word 0x00000001: 00000001
+
+fuse cmp
+~~~~~~~~
+
+::
+
+    u-boot=> fuse cmp 0 1 0x1
+      Comparing bank 0:
+
+      Word 0x00000001:
+      Value 0x00000001:0x00000001
+      passed
+
+fuse readm
+~~~~~~~~~~
+
+::
+
+    u-boot=> fuse readm 0 1 0x83000000
+      Reading bank 0 len 1 to 0x83000000
+
+fuse sense
+~~~~~~~~~~
+
+::
+
+    u-boot=> fuse sense 0 1
+      Sensing bank 0:
+
+      Word 0x00000001: 00000001
+
+fuse prog
+~~~~~~~~~
+
+::
+
+    u-boot=> fuse prog 0 1 0x00000002
+      Programming bank 0 word 0x00000001 to 0x00000002...
+      Warning: Programming fuses is an irreversible operation!
+               This may brick your system.
+               Use this command only if you are sure of what you are doing!
+
+      Really perform this fuse programming? <y/N>
+      y
+
+fuse override
+~~~~~~~~~~~~~
+
+::
+
+    u-boot=> fuse override 0 1 0x00000003
+      Overriding bank 0 word 0x00000001 with 0x00000003...
+
+fuse writebuff
+~~~~~~~~~~~~~~
+
+::
+
+    u-boot=> fuse writebuff -y 0x84000000
+      Programming fuses with buffer at addr 0x84000000
+
+Configuration
+-------------
+
+The fuse commands are available if CONFIG_CMD_FUSE=y.
+The fuse writebuff command is available if CONFIG_CMD_FUSE_WRITEBUFF=y.
+
+Return code
+-----------
+
+The return value $? is set to 0 (true) if the command is successful,
+1 (false) otherwise.
diff --git a/doc/usage/cmd/meminfo.rst b/doc/usage/cmd/meminfo.rst
index 6c94493cccc..e10bdc6832c 100644
--- a/doc/usage/cmd/meminfo.rst
+++ b/doc/usage/cmd/meminfo.rst
@@ -18,7 +18,8 @@ Description
 
 The meminfo command shows the amount of memory. If ``CONFIG_CMD_MEMINFO_MAP`` is
 enabled, then it also shows the layout of memory used by U-Boot and the region
-which is free for use by images.
+which is free for use by images. In architectures that support it, it also prints
+the mapped pages and their permissions. The latter is architecture specific.
 
 The layout of memory is set up before relocation, within the init sequence in
 ``board_init_f()``, specifically the various ``reserve_...()`` functions. This
@@ -26,8 +27,9 @@ The layout of memory is set up before relocation, within the init sequence in
 ending with the stack. This results in the maximum possible amount of memory
 being left free for image-loading.
 
-The meminfo command writes the DRAM size, then the rest of its outputs in 5
-columns:
+The meminfo command writes the DRAM size. If the architecture also supports it,
+page table entries will be shown next. Finally the rest of the outputs are
+printed in 5 columns:
 
 Region
    Name of the region
@@ -99,28 +101,61 @@ free
     Free memory, which is available for loading images. The base address of
     this is ``gd->ram_base`` which is generally set by ``CFG_SYS_SDRAM_BASE``.
 
+Aarch64 specific flags
+----------------------
+
+More information on the output can be found
+Chapter D8 - The AArch64 Virtual Memory System Architecture at
+https://developer.arm.com/documentation/ddi0487/latest/
+
+In short, for a stage 1 translation regime the following apply:
+
+* RWX: Pages mapped with Read, Write and Execute permissions
+* RO:  Pages mapped with Read-Only permissions
+* PXN: PXN (Privileged Execute Never) applies to execution at EL1 and above
+* UXN: UXN (Unprivileged Execute Never) applies to EL0
+
 Example
 -------
 
 This example shows output with both ``CONFIG_CMD_MEMINFO`` and
-``CONFIG_CMD_MEMINFO_MAP`` enabled::
-
-    => meminfo
-    DRAM:  256 MiB
+``CONFIG_CMD_MEMINFO_MAP`` enabled for aarch64 qemu::
+
+    DRAM:  8 GiB
+    Walking pagetable at 000000023ffe0000, va_bits: 40. Using 4 levels
+    [0x0000023ffe1000]                          |  Table |            |               |
+      [0x0000023ffe2000]                        |  Table |            |               |
+        [0x00000000000000 - 0x00000008000000]   |  Block | RWX        | Normal        | Inner-shareable
+        [0x00000008000000 - 0x00000040000000]   |  Block | PXN UXN    | Device-nGnRnE | Non-shareable
+      [0x00000040000000 - 0x00000200000000]     |  Block | RWX        | Normal        | Inner-shareable
+      [0x0000023ffea000]                        |  Table |            |               |
+        [0x00000200000000 - 0x0000023f600000]   |  Block | RWX        | Normal        | Inner-shareable
+        [0x0000023ffeb000]                      |  Table |            |               |
+          [0x0000023f600000 - 0x0000023f68c000] |  Pages | RWX        | Normal        | Inner-shareable
+          [0x0000023f68c000 - 0x0000023f74f000] |  Pages | RO         | Normal        | Inner-shareable
+          [0x0000023f74f000 - 0x0000023f794000] |  Pages | PXN UXN RO | Normal        | Inner-shareable
+          [0x0000023f794000 - 0x0000023f79d000] |  Pages | PXN UXN    | Normal        | Inner-shareable
+          [0x0000023f79d000 - 0x0000023f800000] |  Pages | RWX        | Normal        | Inner-shareable
+        [0x0000023f800000 - 0x00000240000000]   |  Block | RWX        | Normal        | Inner-shareable
+      [0x00000240000000 - 0x00004000000000]     |  Block | RWX        | Normal        | Inner-shareable
+      [0x0000023ffe3000]                        |  Table |            |               |
+        [0x00004010000000 - 0x00004020000000]   |  Block | PXN UXN    | Device-nGnRnE | Non-shareable
+    [0x0000023ffe4000]                          |  Table |            |               |
+      [0x00008000000000 - 0x00010000000000]     |  Block | PXN UXN    | Device-nGnRnE | Non-shareable
 
     Region           Base     Size      End      Gap
     ------------------------------------------------
-    video         f000000  1000000 10000000
-    code          ec3a000   3c5d28  efffd28      2d8
-    malloc        8c38000  6002000  ec3a000        0
-    board_info    8c37f90       68  8c37ff8        8
-    global_data   8c37d80      208  8c37f88        8
-    devicetree    8c33000     4d7d  8c37d7d        3
-    bootstage     8c32c20      3c8  8c32fe8       18
-    bloblist      8c32000      400  8c32400      820
-    stack         7c31ff0  1000000  8c31ff0       10
-    free                0  7c31ff0  7c31ff0        0
-
+    video        23f7e0000   800000 23ffe0000
+    code         23f68a000   156000 23f7e0000        0
+    malloc       23e64a000  1040000 23f68a000        0
+    board_info   23e649f80       78 23e649ff8        8
+    global_data  23e649df0      188 23e649f78        8
+    devicetree   23e549df0   100000 23e649df0        0
+    bloblist     23e547000     2000 23e549000      df0
+    stack        23d546ff0  1000000 23e546ff0       10
+    lmb          23d546ff0        0 23d546ff0        0
+    lmb          23d543000     3ff0 23d546ff0        0
+    free         40000000 23d543000 27d543000 ffffffffc0000000
 
 Return value
 ------------
diff --git a/doc/usage/cmd/mv.rst b/doc/usage/cmd/mv.rst
new file mode 100644
index 00000000000..99864371038
--- /dev/null
+++ b/doc/usage/cmd/mv.rst
@@ -0,0 +1,61 @@
+.. SPDX-License-Identifier: GPL-2.0+:
+
+.. index::
+   single: mv (command)
+
+mv command
+==========
+
+Synopsis
+--------
+
+::
+
+    mv <interface> [<dev[:part]>] <old_path> <new_path>
+
+Description
+-----------
+
+The mv command renames/moves a file or directory within a filesystem.
+
+interface
+    interface for accessing the block device (mmc, sata, scsi, usb, ....)
+
+dev
+    device number
+
+part
+    partition number, defaults to 0 (whole device)
+
+old_path
+   existing path to file/directory
+
+new_path
+   new path/name for the rename/move
+
+
+Example
+-------
+
+    # Rename file 'foo' in directory 'dir' to 'bar'
+    mv mmc 0:0 dir/foo dir/bar
+
+    # Move file 'f' from directory 'foo' to existing directory 'bar' renaming
+    # 'f' to 'g'
+    mv mmc 0:0 foo/f bar/g
+
+    # Move directory 'abc' in directory 'dir1' into existing directory 'dir2'
+    mv mmc 0:0 dir1/abc dir2
+
+Configuration
+-------------
+
+The mv command is only available if CONFIG_CMD_FS_GENERIC=y.
+
+Return value
+------------
+
+The return value $? is set to 0 (true) if the file was successfully
+renamed/moved.
+
+If an error occurs, the return value $? is set to 1 (false).
diff --git a/doc/usage/cmd/ut.rst b/doc/usage/cmd/ut.rst
index e794922c806..1acf3126680 100644
--- a/doc/usage/cmd/ut.rst
+++ b/doc/usage/cmd/ut.rst
@@ -11,34 +11,44 @@ Synopsis
 
 ::
 
-    ut [-r<runs>] [-fs] [-I<n>:<one_test>] [<suite> [<test>]]
-
-       <runs>      Number of times to run each test
-       -f          Force 'manual' tests to run as well
-       <n>         Run <one test> after <n> other tests have run
-       <one_test>  Name of the 'one' test to run
-       <suite>     Test suite to run, or `all`
-       <test>      Name of single test to run
+    ut [-r<runs>] [-f] [-I<n>:<one_test>] [-r<n>] [<suite> | 'all' [<test>]]
+    ut [-s] info
 
 Description
 -----------
 
 The ut command runs unit tests written in C.
 
+suite
+    Specifies the suite to run, This can be a single suite, or a comma-separated
+    list
+
+test
+    Speciifes a particular test to run, within a suite, or all suites
+
+-f
+    Forces running of a manual test.
+
+-r <n>
+    Specifies the number of types to run each test
+
+-I <n>:<one_test>
+    Test to run after <n> other tests have run.  This is used to find which test
+    causes another test to fail. If the one test fails, testing stops
+    immediately.
+
 Typically the command is run on :ref:`arch/sandbox/sandbox:sandbox` since it
 includes a near-complete set of emulators, no code-size limits, many CONFIG
 options enabled and runs easily in CI without needing QEMU. It is also possible
 to run some tests on real boards.
 
-For a list of available test suites, type `ut info -s`.
-
 Each test is normally run once, although those marked with `UTF_DM` are
 run with livetree and flattree where possible. To run a test more than once,
 use the `-r` flag.
 
 Manual tests are normally skipped by this command. Use `-f` to run them. See
-See :ref:`develop/tests_writing:mixing python and c` for more information on
-manual test.
+:ref:`develop/tests_writing:mixing python and c` for more information on manual
+tests.
 
 When running unit tests, some may have side effects which cause a subsequent
 test to break. This can sometimes be seen when using 'ut dm' or similar. To
@@ -50,9 +60,22 @@ the problem.
 Generally all tests in the suite are run. To run just a single test from the
 suite, provide the <test> argument.
 
+To specify a list of suites to run, <suites> can also be a comma-separated list.
+
 See :ref:`develop/tests_writing:writing c tests` for more information on how to
 write unit tests.
 
+ut all
+~~~~~~
+
+Instead of a suite name 'all' may be used to run all tests.
+
+ut info
+~~~~~~~
+
+This provides information about the total number of suites and tests. Use the
+`-s` flag to show a detailed list of suites.
+
 Example
 -------
 
@@ -97,26 +120,84 @@ List available unit-test suites::
 
 Run one of the suites::
 
-    => ut bloblist
-    Running 14 bloblist tests
-    Test: bloblist_test_align: bloblist.c
-    Test: bloblist_test_bad_blob: bloblist.c
-    Test: bloblist_test_blob: bloblist.c
-    Test: bloblist_test_blob_ensure: bloblist.c
-    Test: bloblist_test_blob_maxsize: bloblist.c
-    Test: bloblist_test_checksum: bloblist.c
-    Test: bloblist_test_cmd_info: bloblist.c
-    Test: bloblist_test_cmd_list: bloblist.c
-    Test: bloblist_test_grow: bloblist.c
-    Test: bloblist_test_init: bloblist.c
-    Test: bloblist_test_reloc: bloblist.c
-    Test: bloblist_test_resize_fail: bloblist.c
-    Test: bloblist_test_resize_last: bloblist.c
-    Test: bloblist_test_shrink: bloblist.c
-    Failures: 0
+    => ut common
+    Running 14 common tests
+    Test: cli_ch_test: cread.c
+    Test: cread_test: cread.c
+    Test: dm_test_cyclic_running: cyclic.c
+    Test: print_display_buffer: print.c
+    Test: print_do_hex_dump: print.c
+    Test: print_efi_ut: print.c
+    Test: print_guid: print.c
+    Test: print_hexdump_line: print.c
+    Test: print_printf: print.c
+    Test: snprint: print.c
+    Test: test_autoboot: test_autoboot.c
+    Enter password "a" in 1 seconds to stop autoboot
+    Enter password "a" in 1 seconds to stop autoboot
+    Enter password "a" in 1 seconds to stop autoboot
+    Enter password "a" in 1 seconds to stop autoboot
+    Enter password "a" in 1 seconds to stop autoboot
+    Enter password "a" in 1 seconds to stop autoboot
+    Autoboot password unlock not successful
+    Test: test_event_base: event.c
+    Test: test_event_probe: event.c
+    Test: test_event_probe: event.c (flat tree)
+    Test: test_event_simple: event.c
+    Tests run: 14, 2611 ms, average 186 ms, skipped: 2, failures: 0
 
 Run just a single test in a suite::
 
-    => ut bloblist bloblist_test_grow
-    Test: bloblist_test_grow: bloblist.c
-    Failures: 0
+    => ut fdt_overlay change_int_property
+    Test: fdt_overlay_init: cmd_ut_fdt_overlay.c
+    Test: change_int_property: cmd_ut_fdt_overlay.c
+    Tests run: 2, 0 ms, average 0 ms, failures: 0
+
+Run a selection of three suites::
+
+    => ut bloblist,mem,fdt_overlay
+    Running 14 bloblist tests
+    Test: align: bloblist.c
+    Test: bad_blob: bloblist.c
+    Test: blob: bloblist.c
+    Test: blob_ensure: bloblist.c
+    Test: blob_maxsize: bloblist.c
+    Test: checksum: bloblist.c
+    Test: cmd_info: bloblist.c
+    Test: cmd_list: bloblist.c
+    Test: grow: bloblist.c
+    Test: init: bloblist.c
+    Test: reloc: bloblist.c
+    Test: resize_fail: bloblist.c
+    Test: resize_last: bloblist.c
+    Test: shrink: bloblist.c
+    Tests run: 14, 1 ms, average: 0 ms, failures: 0
+    Running 13 mem tests
+    Test: cp_b: mem_copy.c
+    Test: cp_l: mem_copy.c
+    Test: cp_q: mem_copy.c
+    Test: cp_w: mem_copy.c
+    Test: ms_b: mem_search.c
+    Test: ms_cont: mem_search.c
+    Test: ms_cont_end: mem_search.c
+    Test: ms_l: mem_search.c
+    Test: ms_limit: mem_search.c
+    Test: ms_mult: mem_search.c
+    Test: ms_quiet: mem_search.c
+    Test: ms_s: mem_search.c
+    Test: ms_w: mem_search.c
+    Tests run: 13, 13 ms, average: 1 ms, failures: 0
+    Running 10 fdt_overlay tests
+    Test: fdt_overlay_init: cmd_ut_fdt_overlay.c
+    Test: add_node_by_path: cmd_ut_fdt_overlay.c
+    Test: add_node_by_phandle: cmd_ut_fdt_overlay.c
+    Test: add_str_property: cmd_ut_fdt_overlay.c
+    Test: add_subnode_property: cmd_ut_fdt_overlay.c
+    Test: change_int_property: cmd_ut_fdt_overlay.c
+    Test: change_str_property: cmd_ut_fdt_overlay.c
+    Test: local_phandle: cmd_ut_fdt_overlay.c
+    Test: local_phandles: cmd_ut_fdt_overlay.c
+    Test: stacked: cmd_ut_fdt_overlay.c
+    Tests run: 10, 12 ms, average: 1 ms, failures: 0
+    Suites run: 3, total tests run: 37, 26 ms, average: 0 ms, failures: 0
+    Average test time: 0 ms, worst case 'mem' took 1 ms
diff --git a/doc/usage/cmd/wget.rst b/doc/usage/cmd/wget.rst
index 48bedf1e845..cc82e495a29 100644
--- a/doc/usage/cmd/wget.rst
+++ b/doc/usage/cmd/wget.rst
@@ -12,7 +12,9 @@ Synopsis
 ::
 
     wget [address] [host:]path
-    wget [address] url          # lwIP only
+    wget [address] url                  # lwIP only
+    wget cacert none|optional|required  # lwIP only
+    wget cacert <address> <size>        # lwIP only
 
 
 Description
@@ -54,6 +56,32 @@ address
 url
     HTTP or HTTPS URL, that is: http[s]://<host>[:<port>]/<path>.
 
+The cacert (stands for 'Certification Authority certificates') subcommand is
+used to provide root certificates for the purpose of HTTPS authentication. It
+also allows to enable or disable authentication.
+
+wget cacert <address> <size>
+
+address
+    memory address of the root certificates in X509 DER format
+
+size
+    the size of the root certificates
+
+wget cacert none|optional|required
+
+none
+    certificate verification is disabled. HTTPS is used without any server
+    authentication (unsafe)
+optional
+    certificate verification is enabled provided root certificates have been
+    provided via wget cacert <addr> <size> or wget cacert builtin. Otherwise
+    HTTPS is used without any server authentication (unsafe).
+required
+    certificate verification is mandatory. If no root certificates have been
+    configured, HTTPS transfers will fail.
+
+
 Examples
 --------
 
@@ -97,11 +125,61 @@ In the example the following steps are executed:
    1694892032 bytes transferred in 492181 ms (3.3 MiB/s)
    Bytes transferred = 1694892032 (65060000 hex)
 
+Here is an example showing how to configure built-in root certificates as
+well as providing some at run time. In this example it is assumed that
+CONFIG_WGET_BUILTIN_CACERT_PATH=DigiCertTLSRSA4096RootG5.crt downloaded from
+https://cacerts.digicert.com/DigiCertTLSRSA4096RootG5.crt.
+
+::
+
+   # Make sure IP is configured
+   => dhcp
+   # When built-in certificates are configured, authentication is mandatory
+   # (i.e., "wget cacert required"). Use a test server...
+   => wget https://digicert-tls-rsa4096-root-g5.chain-demos.digicert.com/
+   1864 bytes transferred in 1 ms (1.8 MiB/s)
+   Bytes transferred = 1864 (748 hex)
+   # Another server not signed against Digicert will fail
+   => wget https://www.google.com/
+   Certificate verification failed
+
+   HTTP client error 4
+   # Disable authentication to allow the command to proceed anyways
+   => wget cacert none
+   => wget https://www.google.com/
+   WARNING: no CA certificates, HTTPS connections not authenticated
+   16683 bytes transferred in 15 ms (1.1 MiB/s)
+   Bytes transferred = 16683 (412b hex)
+   # Force verification but unregister the CA certificates
+   => wget cacert required
+   => wget cacert 0 0
+   # Unsurprisingly, download fails
+   => wget https://digicert-tls-rsa4096-root-g5.chain-demos.digicert.com/
+   Error: cacert authentication mode is 'required' but no CA certificates given
+   # Get the same certificates as above from the network
+   => wget cacert none
+   => wget https://cacerts.digicert.com/DigiCertTLSRSA4096RootG5.crt
+   WARNING: no CA certificates, HTTPS connections not authenticated
+   1386 bytes transferred in 1 ms (1.3 MiB/s)
+   Bytes transferred = 1386 (56a hex)
+   # Register them and force authentication
+   => wget cacert $fileaddr $filesize
+   => wget cacert required
+   # Authentication is operational again
+   => wget https://digicert-tls-rsa4096-root-g5.chain-demos.digicert.com/
+   1864 bytes transferred in 1 ms (1.8 MiB/s)
+   Bytes transferred = 1864 (748 hex)
+   # The builtin certificates can be restored at any time
+   => wget cacert builtin
+
 Configuration
 -------------
 
 The command is only available if CONFIG_CMD_WGET=y.
-To enable lwIP support set CONFIG_NET_LWIP=y.
+To enable lwIP support set CONFIG_NET_LWIP=y. In this case, root certificates
+support can be enabled via CONFIG_WGET_BUILTIN_CACERT=y
+CONFIG_WGET_BUILTIN_CACERT_PATH=<some path> (for built-in certificates) and/or
+CONFIG_WGET_CACERT=y (for the wget cacert command).
 
 TCP Selective Acknowledgments in the legacy network stack can be enabled via
 CONFIG_PROT_TCP_SACK=y. This will improve the download speed. Selective
diff --git a/doc/usage/environment.rst b/doc/usage/environment.rst
index 30fc16794fc..7e2f2863d06 100644
--- a/doc/usage/environment.rst
+++ b/doc/usage/environment.rst
@@ -87,6 +87,18 @@ settings. For example::
 
    #include <env/ti/mmc.env>
 
+Quotes are not suppressed, for example::
+
+    fdtfile=CONFIG_DEFAULT_DEVICE_TREE.dtb
+    # produces: fdtfile="sun7i-a20-pcduino3.dtb"
+
+For this particular issue you can use ``DEFAULT_DEVICE_TREE`` instead::
+
+    fdtfile=DEFAULT_DEVICE_TREE.dtb
+    # produces: fdtfile=sun7i-a20-pcduino3.dtb
+
+There is no general way to remove quotes.
+
 If CONFIG_ENV_SOURCE_FILE is empty and the default filename is not present, then
 the old-style C environment is used instead. See below.
 
diff --git a/doc/usage/index.rst b/doc/usage/index.rst
index bf2335dc8f0..372ef56c967 100644
--- a/doc/usage/index.rst
+++ b/doc/usage/index.rst
@@ -72,6 +72,7 @@ Shell commands
    cmd/fdt
    cmd/font
    cmd/for
+   cmd/fuse
    cmd/fwu_mdata
    cmd/gpio
    cmd/gpt
@@ -93,6 +94,7 @@ Shell commands
    cmd/msr
    cmd/mtest
    cmd/mtrr
+   cmd/mv
    cmd/optee
    cmd/panic
    cmd/part
diff --git a/drivers/block/blkmap.c b/drivers/block/blkmap.c
index 34eed1380dc..473c65b5911 100644
--- a/drivers/block/blkmap.c
+++ b/drivers/block/blkmap.c
@@ -17,6 +17,30 @@
 struct blkmap;
 
 /**
+ * define BLKMAP_SLICE_LINEAR - Linear mapping to another block device
+ *
+ * This blkmap slice type is used for mapping to other existing block
+ * devices.
+ */
+#define BLKMAP_SLICE_LINEAR	BIT(0)
+
+/**
+ * define BLKMAP_SLICE_MEM - Linear mapping to memory based block device
+ *
+ * This blkmap slice type is used for mapping to memory based block
+ * devices, like ramdisks.
+ */
+#define BLKMAP_SLICE_MEM	BIT(1)
+
+/**
+ * define BLKMAP_SLICE_PRESERVE - Preserved blkmap slice
+ *
+ * This blkmap slice is intended to be preserved, and it's
+ * information passed on to a later stage, like OS.
+ */
+#define BLKMAP_SLICE_PRESERVE	BIT(2)
+
+/**
  * struct blkmap_slice - Region mapped to a blkmap
  *
  * Common data for a region mapped to a blkmap, specialized by each
@@ -25,12 +49,14 @@ struct blkmap;
  * @node: List node used to associate this slice with a blkmap
  * @blknr: Start block number of the mapping
  * @blkcnt: Number of blocks covered by this mapping
+ * @attr: Attributes of blkmap slice
  */
 struct blkmap_slice {
 	struct list_head node;
 
 	lbaint_t blknr;
 	lbaint_t blkcnt;
+	uint     attr;
 
 	/**
 	 * @read: - Read from slice
@@ -169,6 +195,7 @@ int blkmap_map_linear(struct udevice *dev, lbaint_t blknr, lbaint_t blkcnt,
 		.slice = {
 			.blknr = blknr,
 			.blkcnt = blkcnt,
+			.attr = BLKMAP_SLICE_LINEAR,
 
 			.read = blkmap_linear_read,
 			.write = blkmap_linear_write,
@@ -234,7 +261,7 @@ static void blkmap_mem_destroy(struct blkmap *bm, struct blkmap_slice *bms)
 }
 
 int __blkmap_map_mem(struct udevice *dev, lbaint_t blknr, lbaint_t blkcnt,
-		     void *addr, bool remapped)
+		     void *addr, bool remapped, bool preserve)
 {
 	struct blkmap *bm = dev_get_plat(dev);
 	struct blkmap_mem *bmm;
@@ -248,6 +275,7 @@ int __blkmap_map_mem(struct udevice *dev, lbaint_t blknr, lbaint_t blkcnt,
 		.slice = {
 			.blknr = blknr,
 			.blkcnt = blkcnt,
+			.attr = BLKMAP_SLICE_MEM,
 
 			.read = blkmap_mem_read,
 			.write = blkmap_mem_write,
@@ -258,6 +286,9 @@ int __blkmap_map_mem(struct udevice *dev, lbaint_t blknr, lbaint_t blkcnt,
 		.remapped = remapped,
 	};
 
+	if (preserve)
+		bmm->slice.attr |= BLKMAP_SLICE_PRESERVE;
+
 	err = blkmap_slice_add(bm, &bmm->slice);
 	if (err)
 		free(bmm);
@@ -268,11 +299,11 @@ int __blkmap_map_mem(struct udevice *dev, lbaint_t blknr, lbaint_t blkcnt,
 int blkmap_map_mem(struct udevice *dev, lbaint_t blknr, lbaint_t blkcnt,
 		   void *addr)
 {
-	return __blkmap_map_mem(dev, blknr, blkcnt, addr, false);
+	return __blkmap_map_mem(dev, blknr, blkcnt, addr, false, false);
 }
 
 int blkmap_map_pmem(struct udevice *dev, lbaint_t blknr, lbaint_t blkcnt,
-		    phys_addr_t paddr)
+		    phys_addr_t paddr, bool preserve)
 {
 	struct blkmap *bm = dev_get_plat(dev);
 	struct blk_desc *bd = dev_get_uclass_plat(bm->blk);
@@ -283,7 +314,7 @@ int blkmap_map_pmem(struct udevice *dev, lbaint_t blknr, lbaint_t blkcnt,
 	if (!addr)
 		return -ENOMEM;
 
-	err = __blkmap_map_mem(dev, blknr, blkcnt, addr, true);
+	err = __blkmap_map_mem(dev, blknr, blkcnt, addr, true, preserve);
 	if (err)
 		unmap_sysmem(addr);
 
@@ -486,6 +517,49 @@ err:
 	return err;
 }
 
+static bool blkmap_mem_preserve_slice(struct blkmap_slice *bms)
+{
+	return (bms->attr & (BLKMAP_SLICE_MEM | BLKMAP_SLICE_PRESERVE)) ==
+		(BLKMAP_SLICE_MEM | BLKMAP_SLICE_PRESERVE);
+}
+
+int blkmap_get_preserved_pmem_slices(int (*cb)(void *ctx, u64 addr,
+					       u64 size), void *ctx)
+{
+	int ret;
+	u64 addr, size;
+	struct udevice *dev;
+	struct uclass *uc;
+	struct blkmap *bm;
+	struct blkmap_mem *bmm;
+	struct blkmap_slice *bms;
+	struct blk_desc *bd;
+
+	if (!cb) {
+		log_debug("%s: No callback passed to the function\n", __func__);
+		return 0;
+	}
+
+	uclass_id_foreach_dev(UCLASS_BLKMAP, dev, uc) {
+		bm = dev_get_plat(dev);
+		bd = dev_get_uclass_plat(bm->blk);
+
+		list_for_each_entry(bms, &bm->slices, node) {
+			if (!blkmap_mem_preserve_slice(bms))
+				continue;
+
+			bmm = container_of(bms, struct blkmap_mem, slice);
+			addr = (u64)(uintptr_t)bmm->addr;
+			size = (u64)bms->blkcnt << bd->log2blksz;
+			ret = cb(ctx, addr, size);
+			if (ret)
+				return ret;
+		}
+	}
+
+	return 0;
+}
+
 int blkmap_destroy(struct udevice *dev)
 {
 	int err;
diff --git a/drivers/block/blkmap_helper.c b/drivers/block/blkmap_helper.c
index bfba14110d2..2f1bc28ee5d 100644
--- a/drivers/block/blkmap_helper.c
+++ b/drivers/block/blkmap_helper.c
@@ -28,7 +28,7 @@ int blkmap_create_ramdisk(const char *label, ulong image_addr, ulong image_size,
 	bm = dev_get_plat(bm_dev);
 	desc = dev_get_uclass_plat(bm->blk);
 	blknum = image_size >> desc->log2blksz;
-	ret = blkmap_map_pmem(bm_dev, 0, blknum, image_addr);
+	ret = blkmap_map_pmem(bm_dev, 0, blknum, image_addr, true);
 	if (ret) {
 		log_err("Unable to map %#llx at block %d : %d\n",
 			(unsigned long long)image_addr, 0, ret);
diff --git a/drivers/bootcount/Kconfig b/drivers/bootcount/Kconfig
index 0080d2a165c..99b6c7534fd 100644
--- a/drivers/bootcount/Kconfig
+++ b/drivers/bootcount/Kconfig
@@ -183,6 +183,9 @@ config BOOTCOUNT_BOOTLIMIT
 	  counter being cleared.
 	  If set to 0, do not set a boot limit in the environment.
 
+config BOOTCOUNT_ALTBOOTCMD
+	string "Alternative boot command when BOOTLIMIT is reached"
+
 config SYS_BOOTCOUNT_SINGLEWORD
 	bool "Use single word to pack boot count and magic value"
 	depends on BOOTCOUNT_GENERIC
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index fe0e49f6112..8411205ee04 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -14,6 +14,7 @@ obj-$(CONFIG_$(PHASE_)CLK_GPIO) += clk-gpio.o
 obj-$(CONFIG_$(PHASE_)CLK_STUB) += clk-stub.o
 
 obj-y += adi/
+obj-y += airoha/
 obj-y += analogbits/
 obj-y += imx/
 obj-$(CONFIG_CLK_JH7110) += starfive/
diff --git a/drivers/clk/airoha/Makefile b/drivers/clk/airoha/Makefile
new file mode 100644
index 00000000000..1744c5f7236
--- /dev/null
+++ b/drivers/clk/airoha/Makefile
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0
+# Core
+obj-$(CONFIG_ARCH_AIROHA) += clk-airoha.o
diff --git a/drivers/clk/airoha/clk-airoha.c b/drivers/clk/airoha/clk-airoha.c
new file mode 100644
index 00000000000..1b2c4c98de5
--- /dev/null
+++ b/drivers/clk/airoha/clk-airoha.c
@@ -0,0 +1,454 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Based on the Linux clk-en7523.c but majorly reworked
+ * for U-Boot that doesn't require CCF subsystem.
+ *
+ * Major modification, support for set_rate, realtime
+ * get_rate and split for reset part to a different driver.
+ *
+ * Author: Lorenzo Bianconi <lorenzo@kernel.org> (original driver)
+ *	   Christian Marangi <ansuelsmth@gmail.com>
+ */
+
+#include <clk-uclass.h>
+#include <dm.h>
+#include <dm/devres.h>
+#include <dm/device_compat.h>
+#include <dm/lists.h>
+#include <regmap.h>
+#include <syscon.h>
+
+#include <dt-bindings/clock/en7523-clk.h>
+
+#define REG_GSW_CLK_DIV_SEL		0x1b4
+#define REG_EMI_CLK_DIV_SEL		0x1b8
+#define REG_BUS_CLK_DIV_SEL		0x1bc
+#define REG_SPI_CLK_DIV_SEL		0x1c4
+#define REG_SPI_CLK_FREQ_SEL		0x1c8
+#define REG_NPU_CLK_DIV_SEL		0x1fc
+
+#define REG_NP_SCU_PCIC			0x88
+#define REG_NP_SCU_SSTR			0x9c
+#define REG_PCIE_XSI0_SEL_MASK		GENMASK(14, 13)
+#define REG_PCIE_XSI1_SEL_MASK		GENMASK(12, 11)
+#define REG_CRYPTO_CLKSRC2		0x20c
+
+#define EN7581_MAX_CLKS			9
+
+struct airoha_clk_desc {
+	int id;
+	const char *name;
+	u32 base_reg;
+	u8 base_bits;
+	u8 base_shift;
+	union {
+		const unsigned int *base_values;
+		unsigned int base_value;
+	};
+	size_t n_base_values;
+
+	u16 div_reg;
+	u8 div_bits;
+	u8 div_shift;
+	u16 div_val0;
+	u8 div_step;
+	u8 div_offset;
+};
+
+struct airoha_clk_priv {
+	struct regmap *chip_scu_map;
+	struct airoha_clk_soc_data *data;
+};
+
+struct airoha_clk_soc_data {
+	u32 num_clocks;
+	const struct airoha_clk_desc *descs;
+};
+
+static const u32 gsw_base[] = { 400000000, 500000000 };
+static const u32 slic_base[] = { 100000000, 3125000 };
+
+static const u32 emi7581_base[] = { 540000000, 480000000, 400000000, 300000000 };
+static const u32 bus7581_base[] = { 600000000, 540000000 };
+static const u32 npu7581_base[] = { 800000000, 750000000, 720000000, 600000000 };
+static const u32 crypto_base[] = { 540000000, 480000000 };
+static const u32 emmc7581_base[] = { 200000000, 150000000 };
+
+static const struct airoha_clk_desc en7581_base_clks[EN7581_MAX_CLKS] = {
+	[EN7523_CLK_GSW] = {
+		.id = EN7523_CLK_GSW,
+		.name = "gsw",
+
+		.base_reg = REG_GSW_CLK_DIV_SEL,
+		.base_bits = 1,
+		.base_shift = 8,
+		.base_values = gsw_base,
+		.n_base_values = ARRAY_SIZE(gsw_base),
+
+		.div_bits = 3,
+		.div_shift = 0,
+		.div_step = 1,
+		.div_offset = 1,
+	},
+	[EN7523_CLK_EMI] = {
+		.id = EN7523_CLK_EMI,
+		.name = "emi",
+
+		.base_reg = REG_EMI_CLK_DIV_SEL,
+		.base_bits = 2,
+		.base_shift = 8,
+		.base_values = emi7581_base,
+		.n_base_values = ARRAY_SIZE(emi7581_base),
+
+		.div_bits = 3,
+		.div_shift = 0,
+		.div_step = 1,
+		.div_offset = 1,
+	},
+	[EN7523_CLK_BUS] = {
+		.id = EN7523_CLK_BUS,
+		.name = "bus",
+
+		.base_reg = REG_BUS_CLK_DIV_SEL,
+		.base_bits = 1,
+		.base_shift = 8,
+		.base_values = bus7581_base,
+		.n_base_values = ARRAY_SIZE(bus7581_base),
+
+		.div_bits = 3,
+		.div_shift = 0,
+		.div_step = 1,
+		.div_offset = 1,
+	},
+	[EN7523_CLK_SLIC] = {
+		.id = EN7523_CLK_SLIC,
+		.name = "slic",
+
+		.base_reg = REG_SPI_CLK_FREQ_SEL,
+		.base_bits = 1,
+		.base_shift = 0,
+		.base_values = slic_base,
+		.n_base_values = ARRAY_SIZE(slic_base),
+
+		.div_reg = REG_SPI_CLK_DIV_SEL,
+		.div_bits = 5,
+		.div_shift = 24,
+		.div_val0 = 20,
+		.div_step = 2,
+	},
+	[EN7523_CLK_SPI] = {
+		.id = EN7523_CLK_SPI,
+		.name = "spi",
+
+		.base_reg = REG_SPI_CLK_DIV_SEL,
+
+		.base_value = 400000000,
+
+		.div_bits = 5,
+		.div_shift = 8,
+		.div_val0 = 40,
+		.div_step = 2,
+	},
+	[EN7523_CLK_NPU] = {
+		.id = EN7523_CLK_NPU,
+		.name = "npu",
+
+		.base_reg = REG_NPU_CLK_DIV_SEL,
+		.base_bits = 2,
+		.base_shift = 8,
+		.base_values = npu7581_base,
+		.n_base_values = ARRAY_SIZE(npu7581_base),
+
+		.div_bits = 3,
+		.div_shift = 0,
+		.div_step = 1,
+		.div_offset = 1,
+	},
+	[EN7523_CLK_CRYPTO] = {
+		.id = EN7523_CLK_CRYPTO,
+		.name = "crypto",
+
+		.base_reg = REG_CRYPTO_CLKSRC2,
+		.base_bits = 1,
+		.base_shift = 0,
+		.base_values = crypto_base,
+		.n_base_values = ARRAY_SIZE(crypto_base),
+	},
+	[EN7581_CLK_EMMC] = {
+		.id = EN7581_CLK_EMMC,
+		.name = "emmc",
+
+		.base_reg = REG_CRYPTO_CLKSRC2,
+		.base_bits = 1,
+		.base_shift = 12,
+		.base_values = emmc7581_base,
+		.n_base_values = ARRAY_SIZE(emmc7581_base),
+	}
+};
+
+static u32 airoha_clk_get_base_rate(const struct airoha_clk_desc *desc, u32 val)
+{
+	if (!desc->base_bits)
+		return desc->base_value;
+
+	val >>= desc->base_shift;
+	val &= (1 << desc->base_bits) - 1;
+
+	if (val >= desc->n_base_values)
+		return 0;
+
+	return desc->base_values[val];
+}
+
+static u32 airoha_clk_get_div(const struct airoha_clk_desc *desc, u32 val)
+{
+	if (!desc->div_bits)
+		return 1;
+
+	val >>= desc->div_shift;
+	val &= (1 << desc->div_bits) - 1;
+
+	if (!val && desc->div_val0)
+		return desc->div_val0;
+
+	return (val + desc->div_offset) * desc->div_step;
+}
+
+static int airoha_clk_enable(struct clk *clk)
+{
+	struct airoha_clk_priv *priv = dev_get_priv(clk->dev);
+	struct airoha_clk_soc_data *data = priv->data;
+	int id = clk->id;
+
+	if (id > data->num_clocks)
+		return -EINVAL;
+
+	return 0;
+}
+
+static int airoha_clk_disable(struct clk *clk)
+{
+	return 0;
+}
+
+static ulong airoha_clk_get_rate(struct clk *clk)
+{
+	struct airoha_clk_priv *priv = dev_get_priv(clk->dev);
+	struct airoha_clk_soc_data *data = priv->data;
+	const struct airoha_clk_desc *desc;
+	struct regmap *map = priv->chip_scu_map;
+	int id = clk->id;
+	u32 reg, val;
+	ulong rate;
+	int ret;
+
+	if (id > data->num_clocks) {
+		dev_err(clk->dev, "Invalid clk ID %d\n", id);
+		return 0;
+	}
+
+	desc = &data->descs[id];
+
+	ret = regmap_read(map, desc->base_reg, &val);
+	if (ret) {
+		dev_err(clk->dev, "Failed to read reg for clock %s\n",
+			desc->name);
+		return 0;
+	}
+
+	rate = airoha_clk_get_base_rate(desc, val);
+
+	reg = desc->div_reg ? desc->div_reg : desc->base_reg;
+	ret = regmap_read(map, reg, &val);
+	if (ret) {
+		dev_err(clk->dev, "Failed to read reg for clock %s\n",
+			desc->name);
+		return 0;
+	}
+
+	rate /= airoha_clk_get_div(desc, val);
+
+	return rate;
+}
+
+static int airoha_clk_search_rate(const struct airoha_clk_desc *desc, int div,
+				  ulong rate)
+{
+	int i;
+
+	/* Single base rate */
+	if (!desc->base_bits) {
+		if (rate != desc->base_value / div)
+			goto err;
+
+		return 0;
+	}
+
+	/* Check every base rate with provided divisor */
+	for (i = 0; i < desc->n_base_values; i++)
+		if (rate == desc->base_values[i] / div)
+			return i;
+
+err:
+	return -EINVAL;
+}
+
+static ulong airoha_clk_set_rate(struct clk *clk, ulong rate)
+{
+	struct airoha_clk_priv *priv = dev_get_priv(clk->dev);
+	struct airoha_clk_soc_data *data = priv->data;
+	const struct airoha_clk_desc *desc;
+	struct regmap *map = priv->chip_scu_map;
+	int div_val, base_val;
+	u32 reg, val, mask;
+	int id = clk->id;
+	int div;
+	int ret;
+
+	if (id > data->num_clocks) {
+		dev_err(clk->dev, "Invalid clk ID %d\n", id);
+		return 0;
+	}
+
+	desc = &data->descs[id];
+
+	if (!desc->base_bits && !desc->div_bits) {
+		dev_err(clk->dev, "Can't set rate for fixed clock %s\n",
+			desc->name);
+		return 0;
+	}
+
+	if (!desc->div_bits) {
+		/* Divisor not supported, just search in base rate */
+		div_val = 0;
+		base_val = airoha_clk_search_rate(desc, 1, rate);
+		if (base_val < 0) {
+			dev_err(clk->dev, "Invalid rate for clock %s\n",
+				desc->name);
+			return 0;
+		}
+	} else {
+		div_val = 0;
+
+		/* Check if div0 satisfy the request */
+		if (desc->div_val0) {
+			base_val = airoha_clk_search_rate(desc, desc->div_val0,
+							  rate);
+			if (base_val >= 0) {
+				div_val = 0;
+				goto apply;
+			}
+
+			/* Skip checking first divisor val */
+			div_val = 1;
+		}
+
+		/* Simulate rate with every divisor supported */
+		for (div_val = div_val + desc->div_offset;
+		     div_val < BIT(desc->div_bits) - 1; div_val++) {
+			div = div_val * desc->div_step;
+
+			base_val = airoha_clk_search_rate(desc, div, rate);
+			if (base_val >= 0)
+				break;
+		}
+
+		if (div_val == BIT(desc->div_bits) - 1) {
+			dev_err(clk->dev, "Invalid rate for clock %s\n",
+				desc->name);
+			return 0;
+		}
+	}
+
+apply:
+	if (desc->div_bits) {
+		reg = desc->div_reg ? desc->div_reg : desc->base_reg;
+
+		mask = (BIT(desc->div_bits) - 1) << desc->div_shift;
+		val = div_val << desc->div_shift;
+
+		ret = regmap_update_bits(map, reg, mask, val);
+		if (ret) {
+			dev_err(clk->dev, "Failed to update div reg for clock %s\n",
+				desc->name);
+			return 0;
+		}
+	}
+
+	if (desc->base_bits) {
+		mask = (BIT(desc->base_bits) - 1) << desc->base_shift;
+		val = base_val << desc->base_shift;
+
+		ret = regmap_update_bits(map, desc->base_reg, mask, val);
+		if (ret) {
+			dev_err(clk->dev, "Failed to update reg for clock %s\n",
+				desc->name);
+			return 0;
+		}
+	}
+
+	return rate;
+}
+
+const struct clk_ops airoha_clk_ops = {
+	.enable = airoha_clk_enable,
+	.disable = airoha_clk_disable,
+	.get_rate = airoha_clk_get_rate,
+	.set_rate = airoha_clk_set_rate,
+};
+
+static int airoha_clk_probe(struct udevice *dev)
+{
+	struct airoha_clk_priv *priv = dev_get_priv(dev);
+	ofnode chip_scu_node;
+
+	chip_scu_node = ofnode_by_compatible(ofnode_null(),
+					     "airoha,en7581-chip-scu");
+	if (!ofnode_valid(chip_scu_node))
+		return -EINVAL;
+
+	priv->chip_scu_map = syscon_node_to_regmap(chip_scu_node);
+	if (IS_ERR(priv->chip_scu_map))
+		return PTR_ERR(priv->chip_scu_map);
+
+	priv->data = (void *)dev_get_driver_data(dev);
+
+	return 0;
+}
+
+static int airoha_clk_bind(struct udevice *dev)
+{
+	struct udevice *rst_dev;
+	int ret = 0;
+
+	if (CONFIG_IS_ENABLED(RESET_AIROHA)) {
+		ret = device_bind_driver_to_node(dev, "airoha-reset", "reset",
+						 dev_ofnode(dev), &rst_dev);
+		if (ret)
+			debug("Warning: failed to bind reset controller\n");
+	}
+
+	return ret;
+}
+
+static const struct airoha_clk_soc_data en7581_data = {
+	.num_clocks = ARRAY_SIZE(en7581_base_clks),
+	.descs = en7581_base_clks,
+};
+
+static const struct udevice_id airoha_clk_ids[] = {
+	{ .compatible = "airoha,en7581-scu",
+	  .data = (ulong)&en7581_data,
+	},
+	{ }
+};
+
+U_BOOT_DRIVER(airoha_clk) = {
+	.name = "clk-airoha",
+	.id = UCLASS_CLK,
+	.of_match = airoha_clk_ids,
+	.probe = airoha_clk_probe,
+	.bind = airoha_clk_bind,
+	.priv_auto = sizeof(struct airoha_clk_priv),
+	.ops = &airoha_clk_ops,
+};
diff --git a/drivers/clk/altera/clk-agilex5.c b/drivers/clk/altera/clk-agilex5.c
index 716c71598bc..fb1e72ffc5c 100644
--- a/drivers/clk/altera/clk-agilex5.c
+++ b/drivers/clk/altera/clk-agilex5.c
@@ -1,13 +1,13 @@
 // SPDX-License-Identifier: GPL-2.0
 /*
  * Copyright (C) 2024 Intel Corporation <www.intel.com>
+ * Copyright (C) 2025 Altera Corporation <www.altera.com>
  */
 
-#include <clk-uclass.h>
 #include <config.h>
-#include <errno.h>
-#include <dm.h>
 #include <log.h>
+#include <dm.h>
+#include <errno.h>
 #include <stdarg.h>
 #include <stdio.h>
 #include <time.h>
@@ -23,9 +23,14 @@
 #include <linux/types.h>
 #include <asm/arch/clock_manager.h>
 #include <dt-bindings/clock/agilex5-clock.h>
+#include <wait_bit.h>
+#include <clk-uclass.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
+#define CLKMGR_CTRL_SWCTRLBTCLKEN_MASK		BIT(8)
+#define CLKMGR_CTRL_SWCTRLBTCLKSEL_MASK		BIT(9)
+
 struct socfpga_clk_plat {
 	void __iomem *regs;
 };
@@ -36,21 +41,30 @@ struct socfpga_clk_plat {
  */
 static void clk_write_bypass_mainpll(struct socfpga_clk_plat *plat, u32 val)
 {
+	uintptr_t base_addr = (uintptr_t)plat->regs;
+
 	CM_REG_WRITEL(plat, val, CLKMGR_MAINPLL_BYPASS);
-	cm_wait_for_fsm();
+	wait_for_bit_le32((const void *)(base_addr + CLKMGR_STAT), CLKMGR_STAT_BUSY,
+			  false, 20000, false);
 }
 
 static void clk_write_bypass_perpll(struct socfpga_clk_plat *plat, u32 val)
 {
+	uintptr_t base_addr = (uintptr_t)plat->regs;
+
 	CM_REG_WRITEL(plat, val, CLKMGR_PERPLL_BYPASS);
-	cm_wait_for_fsm();
+	wait_for_bit_le32((const void *)(base_addr + CLKMGR_STAT), CLKMGR_STAT_BUSY,
+			  false, 20000, false);
 }
 
 /* function to write the ctrl register which requires a poll of the busy bit */
 static void clk_write_ctrl(struct socfpga_clk_plat *plat, u32 val)
 {
+	uintptr_t base_addr = (uintptr_t)plat->regs;
+
 	CM_REG_WRITEL(plat, val, CLKMGR_CTRL);
-	cm_wait_for_fsm();
+	wait_for_bit_le32((const void *)(base_addr + CLKMGR_STAT), CLKMGR_STAT_BUSY,
+			  false, 20000, false);
 }
 
 static const struct {
@@ -59,15 +73,6 @@ static const struct {
 	u32 mask;
 } membus_pll[] = {
 	{
-		MEMBUS_CLKSLICE_REG,
-		/*
-		 * BIT[7:7]
-		 * Enable source synchronous mode
-		 */
-		BIT(7),
-		BIT(7)
-	},
-	{
 		MEMBUS_SYNTHCALFOSC_INIT_CENTERFREQ_REG,
 		/*
 		 * BIT[0:0]
@@ -238,6 +243,7 @@ static void clk_basic_init(struct udevice *dev,
 {
 	struct socfpga_clk_plat *plat = dev_get_plat(dev);
 	u32 vcocalib;
+	uintptr_t base_addr = (uintptr_t)plat->regs;
 
 	if (!cfg)
 		return;
@@ -249,7 +255,8 @@ static void clk_basic_init(struct udevice *dev,
 		CM_REG_SETBITS(plat, CLKMGR_PERPLL_PLLGLOB,
 			       CLKMGR_PLLGLOB_PD_MASK | CLKMGR_PLLGLOB_RST_MASK);
 
-		cm_wait_for_lock(CLKMGR_STAT_ALLPLL_LOCKED_MASK);
+		wait_for_bit_le32((const void *)(base_addr + CLKMGR_STAT),
+				  CLKMGR_STAT_ALLPLL_LOCKED_MASK, true, 20000, false);
 
 		/* Put both PLLs in bypass */
 		clk_write_bypass_mainpll(plat, CLKMGR_BYPASS_MAINPLL_ALL);
@@ -264,9 +271,14 @@ static void clk_basic_init(struct udevice *dev,
 			       CM_REG_READL(plat, CLKMGR_CTRL) & ~CLKMGR_CTRL_BOOTMODE);
 	} else {
 #ifdef CONFIG_XPL_BUILD
-		/* Always force clock manager into boot mode before any configuration */
-		clk_write_ctrl(plat,
-			       CM_REG_READL(plat, CLKMGR_CTRL) | CLKMGR_CTRL_BOOTMODE);
+		/*
+		 * Configure HPS Internal Oscillator as default boot_clk source,
+		 * always force clock manager into boot mode before any configuration
+		 */
+		clk_write_ctrl(plat, CM_REG_READL(plat, CLKMGR_CTRL) |
+			       CLKMGR_CTRL_BOOTMODE |
+			       CLKMGR_CTRL_SWCTRLBTCLKEN_MASK |
+			       CLKMGR_CTRL_SWCTRLBTCLKSEL_MASK);
 #else
 		/* Skip clock configuration in SSBL if it's not in boot mode */
 		if (!(CM_REG_READL(plat, CLKMGR_CTRL) & CLKMGR_CTRL_BOOTMODE))
@@ -365,7 +377,8 @@ static void clk_basic_init(struct udevice *dev,
 				CLKMGR_PLLCX_EN_SET_MSK,
 				CLKMGR_PERPLL_PLLC3);
 
-		cm_wait_for_lock(CLKMGR_STAT_ALLPLL_LOCKED_MASK);
+		wait_for_bit_le32((const void *)(base_addr + CLKMGR_STAT),
+				  CLKMGR_STAT_ALLPLL_LOCKED_MASK, true, 20000, false);
 
 		CM_REG_WRITEL(plat, CLKMGR_LOSTLOCK_SET_MASK, CLKMGR_MAINPLL_LOSTLOCK);
 		CM_REG_WRITEL(plat, CLKMGR_LOSTLOCK_SET_MASK, CLKMGR_PERPLL_LOSTLOCK);
diff --git a/drivers/clk/clk-composite.c b/drivers/clk/clk-composite.c
index 199ca6eaa37..9e3b5191767 100644
--- a/drivers/clk/clk-composite.c
+++ b/drivers/clk/clk-composite.c
@@ -97,7 +97,7 @@ static int clk_composite_disable(struct clk *clk)
 		return 0;
 }
 
-struct clk *clk_register_composite(struct device *dev, const char *name,
+struct clk *clk_register_composite(struct udevice *dev, const char *name,
 				   const char * const *parent_names,
 				   int num_parents, struct clk *mux,
 				   const struct clk_ops *mux_ops,
@@ -149,7 +149,7 @@ struct clk *clk_register_composite(struct device *dev, const char *name,
 	clk = &composite->clk;
 	clk->flags = flags;
 	ret = clk_register(clk, UBOOT_DM_CLK_COMPOSITE, name,
-			   parent_names[clk_composite_get_parent(clk)]);
+		clk_resolve_parent_clk(dev, parent_names[clk_composite_get_parent(clk)]));
 	if (ret) {
 		clk = ERR_PTR(ret);
 		goto err;
diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c
index aa210e3d15f..e692b9c2167 100644
--- a/drivers/clk/clk-divider.c
+++ b/drivers/clk/clk-divider.c
@@ -183,7 +183,7 @@ const struct clk_ops clk_divider_ops = {
 	.set_rate = clk_divider_set_rate,
 };
 
-static struct clk *_register_divider(struct device *dev, const char *name,
+static struct clk *_register_divider(struct udevice *dev, const char *name,
 		const char *parent_name, unsigned long flags,
 		void __iomem *reg, u8 shift, u8 width,
 		u8 clk_divider_flags, const struct clk_div_table *table)
@@ -218,7 +218,8 @@ static struct clk *_register_divider(struct device *dev, const char *name,
 	clk = &div->clk;
 	clk->flags = flags;
 
-	ret = clk_register(clk, UBOOT_DM_CLK_CCF_DIVIDER, name, parent_name);
+	ret = clk_register(clk, UBOOT_DM_CLK_CCF_DIVIDER, name,
+			   clk_resolve_parent_clk(dev, parent_name));
 	if (ret) {
 		kfree(div);
 		return ERR_PTR(ret);
@@ -227,7 +228,7 @@ static struct clk *_register_divider(struct device *dev, const char *name,
 	return clk;
 }
 
-struct clk *clk_register_divider(struct device *dev, const char *name,
+struct clk *clk_register_divider(struct udevice *dev, const char *name,
 		const char *parent_name, unsigned long flags,
 		void __iomem *reg, u8 shift, u8 width,
 		u8 clk_divider_flags)
diff --git a/drivers/clk/clk-fixed-factor.c b/drivers/clk/clk-fixed-factor.c
index 068798cf9b0..4eb8be728e6 100644
--- a/drivers/clk/clk-fixed-factor.c
+++ b/drivers/clk/clk-fixed-factor.c
@@ -37,7 +37,7 @@ const struct clk_ops ccf_clk_fixed_factor_ops = {
 	.get_rate = clk_factor_recalc_rate,
 };
 
-struct clk *clk_hw_register_fixed_factor(struct device *dev,
+struct clk *clk_hw_register_fixed_factor(struct udevice *dev,
 		const char *name, const char *parent_name, unsigned long flags,
 		unsigned int mult, unsigned int div)
 {
@@ -56,7 +56,7 @@ struct clk *clk_hw_register_fixed_factor(struct device *dev,
 	clk->flags = flags;
 
 	ret = clk_register(clk, UBOOT_DM_CLK_IMX_FIXED_FACTOR, name,
-			   parent_name);
+			   clk_resolve_parent_clk(dev, parent_name));
 	if (ret) {
 		kfree(fix);
 		return ERR_PTR(ret);
@@ -65,7 +65,7 @@ struct clk *clk_hw_register_fixed_factor(struct device *dev,
 	return clk;
 }
 
-struct clk *clk_register_fixed_factor(struct device *dev, const char *name,
+struct clk *clk_register_fixed_factor(struct udevice *dev, const char *name,
 		const char *parent_name, unsigned long flags,
 		unsigned int mult, unsigned int div)
 {
diff --git a/drivers/clk/clk-gate.c b/drivers/clk/clk-gate.c
index bf1c6a93b46..256ff108991 100644
--- a/drivers/clk/clk-gate.c
+++ b/drivers/clk/clk-gate.c
@@ -117,7 +117,7 @@ const struct clk_ops clk_gate_ops = {
 	.get_rate = clk_generic_get_rate,
 };
 
-struct clk *clk_register_gate(struct device *dev, const char *name,
+struct clk *clk_register_gate(struct udevice *dev, const char *name,
 			      const char *parent_name, unsigned long flags,
 			      void __iomem *reg, u8 bit_idx,
 			      u8 clk_gate_flags, spinlock_t *lock)
@@ -149,7 +149,8 @@ struct clk *clk_register_gate(struct device *dev, const char *name,
 	clk = &gate->clk;
 	clk->flags = flags;
 
-	ret = clk_register(clk, UBOOT_DM_CLK_GATE, name, parent_name);
+	ret = clk_register(clk, UBOOT_DM_CLK_GATE, name,
+		clk_resolve_parent_clk(dev, parent_name));
 	if (ret) {
 		kfree(gate);
 		return ERR_PTR(ret);
diff --git a/drivers/clk/clk-mux.c b/drivers/clk/clk-mux.c
index 62477e15d27..d7411f8f282 100644
--- a/drivers/clk/clk-mux.c
+++ b/drivers/clk/clk-mux.c
@@ -113,6 +113,11 @@ int clk_mux_fetch_parent_index(struct clk *clk, struct clk *parent)
 	for (i = 0; i < mux->num_parents; i++) {
 		if (!strcmp(parent->dev->name, mux->parent_names[i]))
 			return i;
+		if (!strcmp(parent->dev->name,
+			    clk_resolve_parent_clk(clk->dev,
+						   mux->parent_names[i])))
+			return i;
+
 	}
 
 	return -EINVAL;
@@ -159,15 +164,15 @@ const struct clk_ops clk_mux_ops = {
 	.set_parent = clk_mux_set_parent,
 };
 
-struct clk *clk_hw_register_mux_table(struct device *dev, const char *name,
+struct clk *clk_register_mux(struct udevice *dev, const char *name,
 		const char * const *parent_names, u8 num_parents,
 		unsigned long flags,
-		void __iomem *reg, u8 shift, u32 mask,
-		u8 clk_mux_flags, u32 *table)
+		void __iomem *reg, u8 shift, u8 width,
+		u8 clk_mux_flags)
 {
+	u32 mask = BIT(width) - 1;
 	struct clk_mux *mux;
 	struct clk *clk;
-	u8 width = 0;
 	int ret;
 
 	if (clk_mux_flags & CLK_MUX_HIWORD_MASK) {
@@ -192,7 +197,7 @@ struct clk *clk_hw_register_mux_table(struct device *dev, const char *name,
 	mux->shift = shift;
 	mux->mask = mask;
 	mux->flags = clk_mux_flags;
-	mux->table = table;
+	mux->table = NULL;
 #if IS_ENABLED(CONFIG_SANDBOX_CLK_CCF)
 	mux->io_mux_val = *(u32 *)reg;
 #endif
@@ -207,7 +212,8 @@ struct clk *clk_hw_register_mux_table(struct device *dev, const char *name,
 	 * for the corresponding clock (to do that define .set_parent() method).
 	 */
 	ret = clk_register(clk, UBOOT_DM_CLK_CCF_MUX, name,
-			   parent_names[clk_mux_get_parent(clk)]);
+			   clk_resolve_parent_clk(dev,
+				parent_names[clk_mux_get_parent(clk)]));
 	if (ret) {
 		kfree(mux);
 		return ERR_PTR(ret);
@@ -216,35 +222,6 @@ struct clk *clk_hw_register_mux_table(struct device *dev, const char *name,
 	return clk;
 }
 
-struct clk *clk_register_mux_table(struct device *dev, const char *name,
-		const char * const *parent_names, u8 num_parents,
-		unsigned long flags,
-		void __iomem *reg, u8 shift, u32 mask,
-		u8 clk_mux_flags, u32 *table)
-{
-	struct clk *clk;
-
-	clk = clk_hw_register_mux_table(dev, name, parent_names, num_parents,
-				       flags, reg, shift, mask, clk_mux_flags,
-				       table);
-	if (IS_ERR(clk))
-		return ERR_CAST(clk);
-	return clk;
-}
-
-struct clk *clk_register_mux(struct device *dev, const char *name,
-		const char * const *parent_names, u8 num_parents,
-		unsigned long flags,
-		void __iomem *reg, u8 shift, u8 width,
-		u8 clk_mux_flags)
-{
-	u32 mask = BIT(width) - 1;
-
-	return clk_register_mux_table(dev, name, parent_names, num_parents,
-				      flags, reg, shift, mask, clk_mux_flags,
-				      NULL);
-}
-
 U_BOOT_DRIVER(ccf_clk_mux) = {
 	.name	= UBOOT_DM_CLK_CCF_MUX,
 	.id	= UCLASS_CLK,
diff --git a/drivers/clk/clk-stub.c b/drivers/clk/clk-stub.c
index 5fbbb07b7f7..343fa5cd3fe 100644
--- a/drivers/clk/clk-stub.c
+++ b/drivers/clk/clk-stub.c
@@ -50,6 +50,7 @@ static struct clk_ops stub_clk_ops = {
 
 static const struct udevice_id stub_clk_ids[] = {
 	{ .compatible = "qcom,rpmcc" },
+	{ .compatible = "qcom,sc7280-rpmh-clk" },
 	{ .compatible = "qcom,sm8150-rpmh-clk" },
 	{ .compatible = "qcom,sm8250-rpmh-clk" },
 	{ .compatible = "qcom,sm8550-rpmh-clk" },
diff --git a/drivers/clk/clk-uclass.c b/drivers/clk/clk-uclass.c
index 353ae476068..90b70529a47 100644
--- a/drivers/clk/clk-uclass.c
+++ b/drivers/clk/clk-uclass.c
@@ -420,6 +420,24 @@ int clk_get_by_name_nodev(ofnode node, const char *name, struct clk *clk)
 	return clk_get_by_index_nodev(node, index, clk);
 }
 
+const char *
+clk_resolve_parent_clk(struct udevice *dev, const char *name)
+{
+	struct udevice *parent;
+	struct clk clk;
+	int ret;
+
+	ret = uclass_get_device_by_name(UCLASS_CLK, name, &parent);
+	if (!ret)
+		return name;
+
+	ret = clk_get_by_name(dev, name, &clk);
+	if (!clk.dev)
+		return name;
+
+	return clk.dev->name;
+}
+
 int clk_release_all(struct clk *clk, unsigned int count)
 {
 	unsigned int i;
diff --git a/drivers/clk/imx/Kconfig b/drivers/clk/imx/Kconfig
index 56d893e0579..d17a54fb9b3 100644
--- a/drivers/clk/imx/Kconfig
+++ b/drivers/clk/imx/Kconfig
@@ -60,6 +60,7 @@ config SPL_CLK_IMX8MP
 	depends on ARCH_IMX8M && SPL
 	select SPL_CLK
 	select SPL_CLK_CCF
+	select SPL_CLK_COMPOSITE_CCF
 	help
 	  This enables SPL DM/DTS support for clock driver in i.MX8MP
 
diff --git a/drivers/clk/imx/clk-composite-8m.c b/drivers/clk/imx/clk-composite-8m.c
index 64bffa3b181..14c5b92939c 100644
--- a/drivers/clk/imx/clk-composite-8m.c
+++ b/drivers/clk/imx/clk-composite-8m.c
@@ -151,7 +151,7 @@ const struct clk_ops imx8m_clk_mux_ops = {
 	.set_parent = imx8m_clk_mux_set_parent,
 };
 
-struct clk *imx8m_clk_composite_flags(const char *name,
+struct clk *imx8m_clk_composite_flags(struct udevice *dev, const char *name,
 				      const char * const *parent_names,
 				      int num_parents, void __iomem *reg,
 				      unsigned long flags)
@@ -187,7 +187,7 @@ struct clk *imx8m_clk_composite_flags(const char *name,
 	gate->reg = reg;
 	gate->bit_idx = PCG_CGC_SHIFT;
 
-	clk = clk_register_composite(NULL, name,
+	clk = clk_register_composite(dev, name,
 				     parent_names, num_parents,
 				     &mux->clk, &imx8m_clk_mux_ops, &div->clk,
 				     &imx8m_clk_composite_divider_ops,
diff --git a/drivers/clk/imx/clk-gate2.c b/drivers/clk/imx/clk-gate2.c
index 65fa6b5b139..fa07b13249b 100644
--- a/drivers/clk/imx/clk-gate2.c
+++ b/drivers/clk/imx/clk-gate2.c
@@ -90,7 +90,7 @@ static const struct clk_ops clk_gate2_ops = {
 	.get_rate = clk_generic_get_rate,
 };
 
-struct clk *clk_register_gate2(struct device *dev, const char *name,
+struct clk *clk_register_gate2(struct udevice *dev, const char *name,
 		const char *parent_name, unsigned long flags,
 		void __iomem *reg, u8 bit_idx, u8 cgr_val,
 		u8 clk_gate2_flags, unsigned int *share_count)
@@ -111,7 +111,8 @@ struct clk *clk_register_gate2(struct device *dev, const char *name,
 
 	clk = &gate->clk;
 
-	ret = clk_register(clk, UBOOT_DM_CLK_IMX_GATE2, name, parent_name);
+	ret = clk_register(clk, UBOOT_DM_CLK_IMX_GATE2, name,
+		clk_resolve_parent_clk(dev, parent_name));
 	if (ret) {
 		kfree(gate);
 		return ERR_PTR(ret);
diff --git a/drivers/clk/imx/clk-imx6q.c b/drivers/clk/imx/clk-imx6q.c
index df9f0285e1e..13239f2f64d 100644
--- a/drivers/clk/imx/clk-imx6q.c
+++ b/drivers/clk/imx/clk-imx6q.c
@@ -35,6 +35,8 @@ static const char *const usdhc_sels[] = { "pll2_pfd2_396m", "pll2_pfd0_352m", };
 static const char *const periph_sels[]	= { "periph_pre", "periph_clk2", };
 static const char *const periph_pre_sels[] = { "pll2_bus", "pll2_pfd2_396m",
 					       "pll2_pfd0_352m", "pll2_198m", };
+static const char *const uart_sels[] = { "pll3_80m", "osc", };
+static const char *const ecspi_sels[] = { "pll3_60m", "osc", };
 
 static int imx6q_clk_probe(struct udevice *dev)
 {
@@ -44,21 +46,21 @@ static int imx6q_clk_probe(struct udevice *dev)
 	base = (void *)ANATOP_BASE_ADDR;
 
 	clk_dm(IMX6QDL_CLK_PLL2,
-	       imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll2_bus", "osc",
+	       imx_clk_pllv3(dev, IMX_PLLV3_GENERIC, "pll2_bus", "osc",
 			     base + 0x30, 0x1));
 	clk_dm(IMX6QDL_CLK_PLL3_USB_OTG,
-	       imx_clk_pllv3(IMX_PLLV3_USB, "pll3_usb_otg", "osc",
+	       imx_clk_pllv3(dev, IMX_PLLV3_USB, "pll3_usb_otg", "osc",
 			     base + 0x10, 0x3));
 	clk_dm(IMX6QDL_CLK_PLL3_60M,
-	       imx_clk_fixed_factor("pll3_60m",  "pll3_usb_otg",   1, 8));
+	       imx_clk_fixed_factor(dev, "pll3_60m",  "pll3_usb_otg",   1, 8));
 	clk_dm(IMX6QDL_CLK_PLL2_PFD0_352M,
 	       imx_clk_pfd("pll2_pfd0_352m", "pll2_bus", base + 0x100, 0));
 	clk_dm(IMX6QDL_CLK_PLL2_PFD2_396M,
 	       imx_clk_pfd("pll2_pfd2_396m", "pll2_bus", base + 0x100, 2));
 	clk_dm(IMX6QDL_CLK_PLL6,
-	       imx_clk_pllv3(IMX_PLLV3_ENET, "pll6", "osc", base + 0xe0, 0x3));
+	       imx_clk_pllv3(dev, IMX_PLLV3_ENET, "pll6", "osc", base + 0xe0, 0x3));
 	clk_dm(IMX6QDL_CLK_PLL6_ENET,
-	       imx_clk_gate("pll6_enet", "pll6", base + 0xe0, 13));
+	       imx_clk_gate(dev, "pll6_enet", "pll6", base + 0xe0, 13));
 
 	/* CCM clocks */
 	base = dev_read_addr_ptr(dev);
@@ -66,76 +68,98 @@ static int imx6q_clk_probe(struct udevice *dev)
 		return -EINVAL;
 
 	clk_dm(IMX6QDL_CLK_USDHC1_SEL,
-	       imx_clk_mux("usdhc1_sel", base + 0x1c, 16, 1,
+	       imx_clk_mux(dev, "usdhc1_sel", base + 0x1c, 16, 1,
 			   usdhc_sels, ARRAY_SIZE(usdhc_sels)));
 	clk_dm(IMX6QDL_CLK_USDHC2_SEL,
-	       imx_clk_mux("usdhc2_sel", base + 0x1c, 17, 1,
+	       imx_clk_mux(dev, "usdhc2_sel", base + 0x1c, 17, 1,
 			   usdhc_sels, ARRAY_SIZE(usdhc_sels)));
 	clk_dm(IMX6QDL_CLK_USDHC3_SEL,
-	       imx_clk_mux("usdhc3_sel", base + 0x1c, 18, 1,
+	       imx_clk_mux(dev, "usdhc3_sel", base + 0x1c, 18, 1,
 			   usdhc_sels, ARRAY_SIZE(usdhc_sels)));
 	clk_dm(IMX6QDL_CLK_USDHC4_SEL,
-	       imx_clk_mux("usdhc4_sel", base + 0x1c, 19, 1,
+	       imx_clk_mux(dev, "usdhc4_sel", base + 0x1c, 19, 1,
 			   usdhc_sels, ARRAY_SIZE(usdhc_sels)));
 
+	if (of_machine_is_compatible("fsl,imx6qp")) {
+		clk_dm(IMX6QDL_CLK_UART_SEL,
+		       imx_clk_mux(dev, "uart_sel", base + 0x24, 6, 1, uart_sels,
+				   ARRAY_SIZE(uart_sels)));
+		clk_dm(IMX6QDL_CLK_ECSPI_SEL,
+		       imx_clk_mux(dev, "ecspi_sel", base + 0x38, 18, 1, ecspi_sels,
+				   ARRAY_SIZE(ecspi_sels)));
+	}
+
 	clk_dm(IMX6QDL_CLK_USDHC1_PODF,
-	       imx_clk_divider("usdhc1_podf", "usdhc1_sel",
+	       imx_clk_divider(dev, "usdhc1_podf", "usdhc1_sel",
 			       base + 0x24, 11, 3));
 	clk_dm(IMX6QDL_CLK_USDHC2_PODF,
-	       imx_clk_divider("usdhc2_podf", "usdhc2_sel",
+	       imx_clk_divider(dev, "usdhc2_podf", "usdhc2_sel",
 			       base + 0x24, 16, 3));
 	clk_dm(IMX6QDL_CLK_USDHC3_PODF,
-	       imx_clk_divider("usdhc3_podf", "usdhc3_sel",
+	       imx_clk_divider(dev, "usdhc3_podf", "usdhc3_sel",
 			       base + 0x24, 19, 3));
 	clk_dm(IMX6QDL_CLK_USDHC4_PODF,
-	       imx_clk_divider("usdhc4_podf", "usdhc4_sel",
+	       imx_clk_divider(dev, "usdhc4_podf", "usdhc4_sel",
 			       base + 0x24, 22, 3));
 
-	clk_dm(IMX6QDL_CLK_ECSPI_ROOT,
-	       imx_clk_divider("ecspi_root", "pll3_60m", base + 0x38, 19, 6));
+	if (of_machine_is_compatible("fsl,imx6qp")) {
+		clk_dm(IMX6QDL_CLK_UART_SERIAL_PODF,
+		       imx_clk_divider(dev, "uart_serial_podf", "uart_sel", base + 0x24, 0, 6));
+		clk_dm(IMX6QDL_CLK_ECSPI_ROOT,
+		       imx_clk_divider(dev, "ecspi_root", "ecspi_sel", base + 0x38, 19, 6));
+	} else {
+		clk_dm(IMX6QDL_CLK_UART_SERIAL_PODF,
+		       imx_clk_divider(dev, "uart_serial_podf", "pll3_80m", base + 0x24, 0, 6));
+		clk_dm(IMX6QDL_CLK_ECSPI_ROOT,
+		       imx_clk_divider(dev, "ecspi_root", "pll3_60m", base + 0x38, 19, 6));
+	}
 
 	clk_dm(IMX6QDL_CLK_ECSPI1,
-	       imx_clk_gate2("ecspi1", "ecspi_root", base + 0x6c, 0));
+	       imx_clk_gate2(dev, "ecspi1", "ecspi_root", base + 0x6c, 0));
 	clk_dm(IMX6QDL_CLK_ECSPI2,
-	       imx_clk_gate2("ecspi2", "ecspi_root", base + 0x6c, 2));
+	       imx_clk_gate2(dev, "ecspi2", "ecspi_root", base + 0x6c, 2));
 	clk_dm(IMX6QDL_CLK_ECSPI3,
-	       imx_clk_gate2("ecspi3", "ecspi_root", base + 0x6c, 4));
+	       imx_clk_gate2(dev, "ecspi3", "ecspi_root", base + 0x6c, 4));
 	clk_dm(IMX6QDL_CLK_ECSPI4,
-	       imx_clk_gate2("ecspi4", "ecspi_root", base + 0x6c, 6));
+	       imx_clk_gate2(dev, "ecspi4", "ecspi_root", base + 0x6c, 6));
+	clk_dm(IMX6QDL_CLK_UART_IPG,
+	       imx_clk_gate2(dev, "uart_ipg", "ipg", base + 0x7c, 24));
+	clk_dm(IMX6QDL_CLK_UART_SERIAL,
+	       imx_clk_gate2(dev, "uart_serial", "uart_serial_podf",  base + 0x7c, 26));
 	clk_dm(IMX6QDL_CLK_USDHC1,
-	       imx_clk_gate2("usdhc1", "usdhc1_podf", base + 0x80, 2));
+	       imx_clk_gate2(dev, "usdhc1", "usdhc1_podf", base + 0x80, 2));
 	clk_dm(IMX6QDL_CLK_USDHC2,
-	       imx_clk_gate2("usdhc2", "usdhc2_podf", base + 0x80, 4));
+	       imx_clk_gate2(dev, "usdhc2", "usdhc2_podf", base + 0x80, 4));
 	clk_dm(IMX6QDL_CLK_USDHC3,
-	       imx_clk_gate2("usdhc3", "usdhc3_podf", base + 0x80, 6));
+	       imx_clk_gate2(dev, "usdhc3", "usdhc3_podf", base + 0x80, 6));
 	clk_dm(IMX6QDL_CLK_USDHC4,
-	       imx_clk_gate2("usdhc4", "usdhc4_podf", base + 0x80, 8));
+	       imx_clk_gate2(dev, "usdhc4", "usdhc4_podf", base + 0x80, 8));
 
 	clk_dm(IMX6QDL_CLK_PERIPH_PRE,
-	       imx_clk_mux("periph_pre", base + 0x18, 18, 2, periph_pre_sels,
+	       imx_clk_mux(dev, "periph_pre", base + 0x18, 18, 2, periph_pre_sels,
 			   ARRAY_SIZE(periph_pre_sels)));
 	clk_dm(IMX6QDL_CLK_PERIPH,
-	       imx_clk_busy_mux("periph",  base + 0x14, 25, 1, base + 0x48,
+	       imx_clk_busy_mux(dev, "periph",  base + 0x14, 25, 1, base + 0x48,
 				5, periph_sels,  ARRAY_SIZE(periph_sels)));
 	clk_dm(IMX6QDL_CLK_AHB,
-	       imx_clk_busy_divider("ahb", "periph", base + 0x14, 10, 3,
+	       imx_clk_busy_divider(dev, "ahb", "periph", base + 0x14, 10, 3,
 				    base + 0x48, 1));
 	clk_dm(IMX6QDL_CLK_IPG,
-	       imx_clk_divider("ipg", "ahb", base + 0x14, 8, 2));
+	       imx_clk_divider(dev, "ipg", "ahb", base + 0x14, 8, 2));
 	clk_dm(IMX6QDL_CLK_IPG_PER,
-	       imx_clk_divider("ipg_per", "ipg", base + 0x1c, 0, 6));
+	       imx_clk_divider(dev, "ipg_per", "ipg", base + 0x1c, 0, 6));
 	clk_dm(IMX6QDL_CLK_I2C1,
-	       imx_clk_gate2("i2c1", "ipg_per", base + 0x70, 6));
+	       imx_clk_gate2(dev, "i2c1", "ipg_per", base + 0x70, 6));
 	clk_dm(IMX6QDL_CLK_I2C2,
-	       imx_clk_gate2("i2c2", "ipg_per", base + 0x70, 8));
+	       imx_clk_gate2(dev, "i2c2", "ipg_per", base + 0x70, 8));
 	clk_dm(IMX6QDL_CLK_I2C3,
-	       imx_clk_gate2("i2c3", "ipg_per", base + 0x70, 10));
+	       imx_clk_gate2(dev, "i2c3", "ipg_per", base + 0x70, 10));
 	clk_dm(IMX6QDL_CLK_PWM1,
-	       imx_clk_gate2("pwm1", "ipg_per", base + 0x78, 16));
+	       imx_clk_gate2(dev, "pwm1", "ipg_per", base + 0x78, 16));
 
-	clk_dm(IMX6QDL_CLK_ENET, imx_clk_gate2("enet", "ipg", base + 0x6c, 10));
+	clk_dm(IMX6QDL_CLK_ENET, imx_clk_gate2(dev, "enet", "ipg", base + 0x6c, 10));
 	clk_dm(IMX6QDL_CLK_ENET_REF,
-	       imx_clk_fixed_factor("enet_ref", "pll6_enet", 1, 1));
+	       imx_clk_fixed_factor(dev, "enet_ref", "pll6_enet", 1, 1));
 
 	return 0;
 }
diff --git a/drivers/clk/imx/clk-imx8mm.c b/drivers/clk/imx/clk-imx8mm.c
index bb6958f0ec2..b81db516a69 100644
--- a/drivers/clk/imx/clk-imx8mm.c
+++ b/drivers/clk/imx/clk-imx8mm.c
@@ -14,7 +14,7 @@
 
 #include "clk.h"
 
-static const char * const pll_ref_sels[] = { "clock-osc-24m", "dummy", "dummy", "dummy", };
+static const char * const pll_ref_sels[] = { "osc_24m", "dummy", "dummy", "dummy", };
 static const char * const dram_pll_bypass_sels[] = {"dram_pll", "dram_pll_ref_sel", };
 static const char * const arm_pll_bypass_sels[] = {"arm_pll", "arm_pll_ref_sel", };
 static const char * const sys_pll1_bypass_sels[] = {"sys_pll1", "sys_pll1_ref_sel", };
@@ -23,128 +23,144 @@ static const char * const sys_pll3_bypass_sels[] = {"sys_pll3", "sys_pll3_ref_se
 
 static const char * const imx8mm_arm_core_sels[] = {"arm_a53_src", "arm_pll_out", };
 
-static const char * const imx8mm_a53_sels[] = {"clock-osc-24m", "arm_pll_out", "sys_pll2_500m",
+static const char * const imx8mm_a53_sels[] = {"osc_24m", "arm_pll_out", "sys_pll2_500m",
 					       "sys_pll2_1000m", "sys_pll1_800m", "sys_pll1_400m",
 					       "audio_pll1_out", "sys_pll3_out", };
 
-static const char * const imx8mm_ahb_sels[] = {"clock-osc-24m", "sys_pll1_133m", "sys_pll1_800m",
+static const char * const imx8mm_ahb_sels[] = {"osc_24m", "sys_pll1_133m", "sys_pll1_800m",
 					       "sys_pll1_400m", "sys_pll2_125m", "sys_pll3_out",
 					       "audio_pll1_out", "video_pll1_out", };
 
 #ifndef CONFIG_XPL_BUILD
-static const char * const imx8mm_enet_axi_sels[] = {"clock-osc-24m", "sys_pll1_266m", "sys_pll1_800m",
+static const char * const imx8mm_enet_axi_sels[] = {"osc_24m", "sys_pll1_266m", "sys_pll1_800m",
 						    "sys_pll2_250m", "sys_pll2_200m", "audio_pll1_out",
 						    "video_pll1_out", "sys_pll3_out", };
 
-static const char * const imx8mm_enet_ref_sels[] = {"clock-osc-24m", "sys_pll2_125m", "sys_pll2_50m",
+static const char * const imx8mm_enet_ref_sels[] = {"osc_24m", "sys_pll2_125m", "sys_pll2_50m",
 						    "sys_pll2_100m", "sys_pll1_160m", "audio_pll1_out",
 						    "video_pll1_out", "clk_ext4", };
 
-static const char * const imx8mm_enet_timer_sels[] = {"clock-osc-24m", "sys_pll2_100m", "audio_pll1_out",
+static const char * const imx8mm_enet_timer_sels[] = {"osc_24m", "sys_pll2_100m", "audio_pll1_out",
 						      "clk_ext1", "clk_ext2", "clk_ext3",
 						      "clk_ext4", "video_pll1_out", };
 
-static const char * const imx8mm_enet_phy_sels[] = {"clock-osc-24m", "sys_pll2_50m", "sys_pll2_125m",
+static const char * const imx8mm_enet_phy_sels[] = {"osc_24m", "sys_pll2_50m", "sys_pll2_125m",
 						    "sys_pll2_200m", "sys_pll2_500m", "video_pll1_out",
 						    "audio_pll2_out", };
 #endif
 
-static const char * const imx8mm_nand_usdhc_sels[] = {"clock-osc-24m", "sys_pll1_266m", "sys_pll1_800m",
+static const char * const imx8mm_nand_usdhc_sels[] = {"osc_24m", "sys_pll1_266m", "sys_pll1_800m",
 						      "sys_pll2_200m", "sys_pll1_133m", "sys_pll3_out",
 						      "sys_pll2_250m", "audio_pll1_out", };
 
-static const char * const imx8mm_usb_bus_sels[] = {"clock-osc-24m", "sys_pll2_500m", "sys_pll1_800m",
+static const char * const imx8mm_usb_bus_sels[] = {"osc_24m", "sys_pll2_500m", "sys_pll1_800m",
 						   "sys_pll2_100m", "sys_pll2_200m", "clk_ext2",
 						   "clk_ext4", "audio_pll2_out", };
 
-static const char * const imx8mm_usdhc1_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sys_pll1_800m",
+static const char * const imx8mm_usdhc1_sels[] = {"osc_24m", "sys_pll1_400m", "sys_pll1_800m",
 						  "sys_pll2_500m", "sys_pll3_out", "sys_pll1_266m",
 						  "audio_pll2_out", "sys_pll1_100m", };
 
-static const char * const imx8mm_usdhc2_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sys_pll1_800m",
+static const char * const imx8mm_usdhc2_sels[] = {"osc_24m", "sys_pll1_400m", "sys_pll1_800m",
 						  "sys_pll2_500m", "sys_pll3_out", "sys_pll1_266m",
 						  "audio_pll2_out", "sys_pll1_100m", };
 
-static const char * const imx8mm_i2c1_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m",
+static const char * const imx8mm_i2c1_sels[] = {"osc_24m", "sys_pll1_160m", "sys_pll2_50m",
 						"sys_pll3_out", "audio_pll1_out", "video_pll1_out",
 						"audio_pll2_out", "sys_pll1_133m", };
 
-static const char * const imx8mm_i2c2_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m",
+static const char * const imx8mm_i2c2_sels[] = {"osc_24m", "sys_pll1_160m", "sys_pll2_50m",
 						"sys_pll3_out", "audio_pll1_out", "video_pll1_out",
 						"audio_pll2_out", "sys_pll1_133m", };
 
-static const char * const imx8mm_i2c3_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m",
+static const char * const imx8mm_i2c3_sels[] = {"osc_24m", "sys_pll1_160m", "sys_pll2_50m",
 						"sys_pll3_out", "audio_pll1_out", "video_pll1_out",
 						"audio_pll2_out", "sys_pll1_133m", };
 
-static const char * const imx8mm_i2c4_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m",
+static const char * const imx8mm_i2c4_sels[] = {"osc_24m", "sys_pll1_160m", "sys_pll2_50m",
 						"sys_pll3_out", "audio_pll1_out", "video_pll1_out",
 						"audio_pll2_out", "sys_pll1_133m", };
 
+static const char * const imx8mm_uart1_sels[] = {"clock-osc-24m", "sys_pll1_80m", "sys_pll2_200m",
+					  "sys_pll2_100m", "sys_pll3_out", "clk_ext2", "clk_ext4",
+					  "audio_pll2_out", };
+
+static const char * const imx8mm_uart2_sels[] = {"clock-osc-24m", "sys_pll1_80m", "sys_pll2_200m",
+					  "sys_pll2_100m", "sys_pll3_out", "clk_ext2", "clk_ext3",
+					  "audio_pll2_out", };
+
+static const char * const imx8mm_uart3_sels[] = {"clock-osc-24m", "sys_pll1_80m", "sys_pll2_200m",
+					  "sys_pll2_100m", "sys_pll3_out", "clk_ext2", "clk_ext4",
+					  "audio_pll2_out", };
+
+static const char * const imx8mm_uart4_sels[] = {"clock-osc-24m", "sys_pll1_80m", "sys_pll2_200m",
+					  "sys_pll2_100m", "sys_pll3_out", "clk_ext2", "clk_ext3",
+					  "audio_pll2_out", };
+
 #if CONFIG_IS_ENABLED(PCIE_DW_IMX)
-static const char * const imx8mm_pcie1_ctrl_sels[] = {"clock-osc-24m", "sys_pll2_250m", "sys_pll2_200m",
+static const char * const imx8mm_pcie1_ctrl_sels[] = {"osc_24m", "sys_pll2_250m", "sys_pll2_200m",
 						      "sys_pll1_266m", "sys_pll1_800m", "sys_pll2_500m",
 						      "sys_pll2_333m", "sys_pll3_out", };
 
-static const char * const imx8mm_pcie1_phy_sels[] = {"clock-osc-24m", "sys_pll2_100m", "sys_pll2_500m",
+static const char * const imx8mm_pcie1_phy_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll2_500m",
 						     "clk_ext1", "clk_ext2", "clk_ext3",
 						     "clk_ext4", "sys_pll1_400m", };
 
-static const char * const imx8mm_pcie1_aux_sels[] = {"clock-osc-24m", "sys_pll2_200m", "sys_pll2_50m",
+static const char * const imx8mm_pcie1_aux_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll2_50m",
 						     "sys_pll3_out", "sys_pll2_100m", "sys_pll1_80m",
 						     "sys_pll1_160m", "sys_pll1_200m", };
 #endif
 
 #ifndef CONFIG_XPL_BUILD
-static const char * const imx8mm_pwm1_sels[] = {"clock-osc-24m", "sys_pll2_100m", "sys_pll1_160m",
+static const char * const imx8mm_pwm1_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_160m",
 						"sys_pll1_40m", "sys_pll3_out", "clk_ext1",
 						"sys_pll1_80m", "video_pll1_out", };
 
-static const char * const imx8mm_pwm2_sels[] = {"clock-osc-24m", "sys_pll2_100m", "sys_pll1_160m",
+static const char * const imx8mm_pwm2_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_160m",
 						"sys_pll1_40m", "sys_pll3_out", "clk_ext1",
 						"sys_pll1_80m", "video_pll1_out", };
 
-static const char * const imx8mm_pwm3_sels[] = {"clock-osc-24m", "sys_pll2_100m", "sys_pll1_160m",
+static const char * const imx8mm_pwm3_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_160m",
 						"sys_pll1_40m", "sys_pll3_out", "clk_ext2",
 						"sys_pll1_80m", "video_pll1_out", };
 
-static const char * const imx8mm_pwm4_sels[] = {"clock-osc-24m", "sys_pll2_100m", "sys_pll1_160m",
+static const char * const imx8mm_pwm4_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_160m",
 						"sys_pll1_40m", "sys_pll3_out", "clk_ext2",
 						"sys_pll1_80m", "video_pll1_out", };
 #endif
 
-static const char * const imx8mm_wdog_sels[] = {"clock-osc-24m", "sys_pll1_133m", "sys_pll1_160m",
+static const char * const imx8mm_wdog_sels[] = {"osc_24m", "sys_pll1_133m", "sys_pll1_160m",
 						"vpu_pll_out", "sys_pll2_125m", "sys_pll3_out",
 						"sys_pll1_80m", "sys_pll2_166m", };
 
-static const char * const imx8mm_usdhc3_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sys_pll1_800m",
+static const char * const imx8mm_usdhc3_sels[] = {"osc_24m", "sys_pll1_400m", "sys_pll1_800m",
 						  "sys_pll2_500m", "sys_pll3_out", "sys_pll1_266m",
 						  "audio_pll2_clk", "sys_pll1_100m", };
 
 #if CONFIG_IS_ENABLED(NXP_FSPI)
-static const char * const imx8mm_qspi_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sys_pll2_333m",
+static const char * const imx8mm_qspi_sels[] = {"osc_24m", "sys_pll1_400m", "sys_pll2_333m",
 						"sys_pll2_500m", "audio_pll2_out", "sys_pll1_266m",
 						"sys_pll3_out", "sys_pll1_100m", };
 #endif
 
-static const char * const imx8mm_usb_core_sels[] = {"clock-osc-24m", "sys_pll1_100m", "sys_pll1_40m",
+static const char * const imx8mm_usb_core_sels[] = {"osc_24m", "sys_pll1_100m", "sys_pll1_40m",
 						    "sys_pll2_100m", "sys_pll2_200m", "clk_ext2",
 						    "clk_ext3", "audio_pll2_out", };
 
-static const char * const imx8mm_usb_phy_sels[] = {"clock-osc-24m", "sys_pll1_100m", "sys_pll1_40m",
+static const char * const imx8mm_usb_phy_sels[] = {"osc_24m", "sys_pll1_100m", "sys_pll1_40m",
 						   "sys_pll2_100m", "sys_pll2_200m", "clk_ext2",
 						   "clk_ext3", "audio_pll2_out", };
 
 #if CONFIG_IS_ENABLED(DM_SPI)
-static const char * const imx8mm_ecspi1_sels[] = {"clock-osc-24m", "sys_pll2_200m", "sys_pll1_40m",
+static const char * const imx8mm_ecspi1_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1_40m",
 						  "sys_pll1_160m", "sys_pll1_800m", "sys_pll3_out",
 						  "sys_pll2_250m", "audio_pll2_out", };
 
-static const char * const imx8mm_ecspi2_sels[] = {"clock-osc-24m", "sys_pll2_200m", "sys_pll1_40m",
+static const char * const imx8mm_ecspi2_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1_40m",
 						  "sys_pll1_160m", "sys_pll1_800m", "sys_pll3_out",
 						  "sys_pll2_250m", "audio_pll2_out", };
 
-static const char * const imx8mm_ecspi3_sels[] = {"clock-osc-24m", "sys_pll2_200m", "sys_pll1_40m",
+static const char * const imx8mm_ecspi3_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1_40m",
 						  "sys_pll1_160m", "sys_pll1_800m", "sys_pll3_out",
 						  "sys_pll2_250m", "audio_pll2_out", };
 #endif
@@ -156,19 +172,19 @@ static int imx8mm_clk_probe(struct udevice *dev)
 	base = (void *)ANATOP_BASE_ADDR;
 
 	clk_dm(IMX8MM_DRAM_PLL_REF_SEL,
-	       imx_clk_mux("dram_pll_ref_sel", base + 0x50, 0, 2,
+	       imx_clk_mux(dev, "dram_pll_ref_sel", base + 0x50, 0, 2,
 			   pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
 	clk_dm(IMX8MM_ARM_PLL_REF_SEL,
-	       imx_clk_mux("arm_pll_ref_sel", base + 0x84, 0, 2,
+	       imx_clk_mux(dev, "arm_pll_ref_sel", base + 0x84, 0, 2,
 			   pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
 	clk_dm(IMX8MM_SYS_PLL1_REF_SEL,
-	       imx_clk_mux("sys_pll1_ref_sel", base + 0x94, 0, 2,
+	       imx_clk_mux(dev, "sys_pll1_ref_sel", base + 0x94, 0, 2,
 			   pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
 	clk_dm(IMX8MM_SYS_PLL2_REF_SEL,
-	       imx_clk_mux("sys_pll2_ref_sel", base + 0x104, 0, 2,
+	       imx_clk_mux(dev, "sys_pll2_ref_sel", base + 0x104, 0, 2,
 			   pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
 	clk_dm(IMX8MM_SYS_PLL3_REF_SEL,
-	       imx_clk_mux("sys_pll3_ref_sel", base + 0x114, 0, 2,
+	       imx_clk_mux(dev, "sys_pll3_ref_sel", base + 0x114, 0, 2,
 			   pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
 
 	clk_dm(IMX8MM_DRAM_PLL,
@@ -189,238 +205,254 @@ static int imx8mm_clk_probe(struct udevice *dev)
 
 	/* PLL bypass out */
 	clk_dm(IMX8MM_DRAM_PLL_BYPASS,
-	       imx_clk_mux_flags("dram_pll_bypass", base + 0x50, 4, 1,
+	       imx_clk_mux_flags(dev, "dram_pll_bypass", base + 0x50, 4, 1,
 				 dram_pll_bypass_sels,
 				 ARRAY_SIZE(dram_pll_bypass_sels),
 				 CLK_SET_RATE_PARENT));
 	clk_dm(IMX8MM_ARM_PLL_BYPASS,
-	       imx_clk_mux_flags("arm_pll_bypass", base + 0x84, 4, 1,
+	       imx_clk_mux_flags(dev, "arm_pll_bypass", base + 0x84, 4, 1,
 				 arm_pll_bypass_sels,
 				 ARRAY_SIZE(arm_pll_bypass_sels),
 				 CLK_SET_RATE_PARENT));
 	clk_dm(IMX8MM_SYS_PLL1_BYPASS,
-	       imx_clk_mux_flags("sys_pll1_bypass", base + 0x94, 4, 1,
+	       imx_clk_mux_flags(dev, "sys_pll1_bypass", base + 0x94, 4, 1,
 				 sys_pll1_bypass_sels,
 				 ARRAY_SIZE(sys_pll1_bypass_sels),
 				 CLK_SET_RATE_PARENT));
 	clk_dm(IMX8MM_SYS_PLL2_BYPASS,
-	       imx_clk_mux_flags("sys_pll2_bypass", base + 0x104, 4, 1,
+	       imx_clk_mux_flags(dev, "sys_pll2_bypass", base + 0x104, 4, 1,
 				 sys_pll2_bypass_sels,
 				 ARRAY_SIZE(sys_pll2_bypass_sels),
 				 CLK_SET_RATE_PARENT));
 	clk_dm(IMX8MM_SYS_PLL3_BYPASS,
-	       imx_clk_mux_flags("sys_pll3_bypass", base + 0x114, 4, 1,
+	       imx_clk_mux_flags(dev, "sys_pll3_bypass", base + 0x114, 4, 1,
 				 sys_pll3_bypass_sels,
 				 ARRAY_SIZE(sys_pll3_bypass_sels),
 				 CLK_SET_RATE_PARENT));
 
 	/* PLL out gate */
 	clk_dm(IMX8MM_DRAM_PLL_OUT,
-	       imx_clk_gate("dram_pll_out", "dram_pll_bypass",
+	       imx_clk_gate(dev, "dram_pll_out", "dram_pll_bypass",
 			    base + 0x50, 13));
 	clk_dm(IMX8MM_ARM_PLL_OUT,
-	       imx_clk_gate("arm_pll_out", "arm_pll_bypass",
+	       imx_clk_gate(dev, "arm_pll_out", "arm_pll_bypass",
 			    base + 0x84, 11));
 	clk_dm(IMX8MM_SYS_PLL1_OUT,
-	       imx_clk_gate("sys_pll1_out", "sys_pll1_bypass",
+	       imx_clk_gate(dev, "sys_pll1_out", "sys_pll1_bypass",
 			    base + 0x94, 11));
 	clk_dm(IMX8MM_SYS_PLL2_OUT,
-	       imx_clk_gate("sys_pll2_out", "sys_pll2_bypass",
+	       imx_clk_gate(dev, "sys_pll2_out", "sys_pll2_bypass",
 			    base + 0x104, 11));
 	clk_dm(IMX8MM_SYS_PLL3_OUT,
-	       imx_clk_gate("sys_pll3_out", "sys_pll3_bypass",
+	       imx_clk_gate(dev, "sys_pll3_out", "sys_pll3_bypass",
 			    base + 0x114, 11));
 
 	/* SYS PLL fixed output */
 	clk_dm(IMX8MM_SYS_PLL1_40M,
-	       imx_clk_fixed_factor("sys_pll1_40m", "sys_pll1_out", 1, 20));
+	       imx_clk_fixed_factor(dev, "sys_pll1_40m", "sys_pll1_out", 1, 20));
 	clk_dm(IMX8MM_SYS_PLL1_80M,
-	       imx_clk_fixed_factor("sys_pll1_80m", "sys_pll1_out", 1, 10));
+	       imx_clk_fixed_factor(dev, "sys_pll1_80m", "sys_pll1_out", 1, 10));
 	clk_dm(IMX8MM_SYS_PLL1_100M,
-	       imx_clk_fixed_factor("sys_pll1_100m", "sys_pll1_out", 1, 8));
+	       imx_clk_fixed_factor(dev, "sys_pll1_100m", "sys_pll1_out", 1, 8));
 	clk_dm(IMX8MM_SYS_PLL1_133M,
-	       imx_clk_fixed_factor("sys_pll1_133m", "sys_pll1_out", 1, 6));
+	       imx_clk_fixed_factor(dev, "sys_pll1_133m", "sys_pll1_out", 1, 6));
 	clk_dm(IMX8MM_SYS_PLL1_160M,
-	       imx_clk_fixed_factor("sys_pll1_160m", "sys_pll1_out", 1, 5));
+	       imx_clk_fixed_factor(dev, "sys_pll1_160m", "sys_pll1_out", 1, 5));
 	clk_dm(IMX8MM_SYS_PLL1_200M,
-	       imx_clk_fixed_factor("sys_pll1_200m", "sys_pll1_out", 1, 4));
+	       imx_clk_fixed_factor(dev, "sys_pll1_200m", "sys_pll1_out", 1, 4));
 	clk_dm(IMX8MM_SYS_PLL1_266M,
-	       imx_clk_fixed_factor("sys_pll1_266m", "sys_pll1_out", 1, 3));
+	       imx_clk_fixed_factor(dev, "sys_pll1_266m", "sys_pll1_out", 1, 3));
 	clk_dm(IMX8MM_SYS_PLL1_400M,
-	       imx_clk_fixed_factor("sys_pll1_400m", "sys_pll1_out", 1, 2));
+	       imx_clk_fixed_factor(dev, "sys_pll1_400m", "sys_pll1_out", 1, 2));
 	clk_dm(IMX8MM_SYS_PLL1_800M,
-	       imx_clk_fixed_factor("sys_pll1_800m", "sys_pll1_out", 1, 1));
+	       imx_clk_fixed_factor(dev, "sys_pll1_800m", "sys_pll1_out", 1, 1));
 
 	clk_dm(IMX8MM_SYS_PLL2_50M,
-	       imx_clk_fixed_factor("sys_pll2_50m", "sys_pll2_out", 1, 20));
+	       imx_clk_fixed_factor(dev, "sys_pll2_50m", "sys_pll2_out", 1, 20));
 	clk_dm(IMX8MM_SYS_PLL2_100M,
-	       imx_clk_fixed_factor("sys_pll2_100m", "sys_pll2_out", 1, 10));
+	       imx_clk_fixed_factor(dev, "sys_pll2_100m", "sys_pll2_out", 1, 10));
 	clk_dm(IMX8MM_SYS_PLL2_125M,
-	       imx_clk_fixed_factor("sys_pll2_125m", "sys_pll2_out", 1, 8));
+	       imx_clk_fixed_factor(dev, "sys_pll2_125m", "sys_pll2_out", 1, 8));
 	clk_dm(IMX8MM_SYS_PLL2_166M,
-	       imx_clk_fixed_factor("sys_pll2_166m", "sys_pll2_out", 1, 6));
+	       imx_clk_fixed_factor(dev, "sys_pll2_166m", "sys_pll2_out", 1, 6));
 	clk_dm(IMX8MM_SYS_PLL2_200M,
-	       imx_clk_fixed_factor("sys_pll2_200m", "sys_pll2_out", 1, 5));
+	       imx_clk_fixed_factor(dev, "sys_pll2_200m", "sys_pll2_out", 1, 5));
 	clk_dm(IMX8MM_SYS_PLL2_250M,
-	       imx_clk_fixed_factor("sys_pll2_250m", "sys_pll2_out", 1, 4));
+	       imx_clk_fixed_factor(dev, "sys_pll2_250m", "sys_pll2_out", 1, 4));
 	clk_dm(IMX8MM_SYS_PLL2_333M,
-	       imx_clk_fixed_factor("sys_pll2_333m", "sys_pll2_out", 1, 3));
+	       imx_clk_fixed_factor(dev, "sys_pll2_333m", "sys_pll2_out", 1, 3));
 	clk_dm(IMX8MM_SYS_PLL2_500M,
-	       imx_clk_fixed_factor("sys_pll2_500m", "sys_pll2_out", 1, 2));
+	       imx_clk_fixed_factor(dev, "sys_pll2_500m", "sys_pll2_out", 1, 2));
 	clk_dm(IMX8MM_SYS_PLL2_1000M,
-	       imx_clk_fixed_factor("sys_pll2_1000m", "sys_pll2_out", 1, 1));
+	       imx_clk_fixed_factor(dev, "sys_pll2_1000m", "sys_pll2_out", 1, 1));
 
 	base = dev_read_addr_ptr(dev);
 	if (!base)
 		return -EINVAL;
 
 	clk_dm(IMX8MM_CLK_A53_SRC,
-	       imx_clk_mux2("arm_a53_src", base + 0x8000, 24, 3,
+	       imx_clk_mux2(dev, "arm_a53_src", base + 0x8000, 24, 3,
 			    imx8mm_a53_sels, ARRAY_SIZE(imx8mm_a53_sels)));
 	clk_dm(IMX8MM_CLK_A53_CG,
-	       imx_clk_gate3("arm_a53_cg", "arm_a53_src", base + 0x8000, 28));
+	       imx_clk_gate3(dev, "arm_a53_cg", "arm_a53_src", base + 0x8000, 28));
 	clk_dm(IMX8MM_CLK_A53_DIV,
-	       imx_clk_divider2("arm_a53_div", "arm_a53_cg",
+	       imx_clk_divider2(dev, "arm_a53_div", "arm_a53_cg",
 				base + 0x8000, 0, 3));
 
 	clk_dm(IMX8MM_CLK_AHB,
-	       imx8m_clk_composite_critical("ahb", imx8mm_ahb_sels,
+	       imx8m_clk_composite_critical(dev, "ahb", imx8mm_ahb_sels,
 					    base + 0x9000));
 	clk_dm(IMX8MM_CLK_IPG_ROOT,
-	       imx_clk_divider2("ipg_root", "ahb", base + 0x9080, 0, 1));
+	       imx_clk_divider2(dev, "ipg_root", "ahb", base + 0x9080, 0, 1));
 
 	clk_dm(IMX8MM_CLK_NAND_USDHC_BUS,
-	       imx8m_clk_composite_critical("nand_usdhc_bus",
+	       imx8m_clk_composite_critical(dev, "nand_usdhc_bus",
 					    imx8mm_nand_usdhc_sels,
 					    base + 0x8900));
 	clk_dm(IMX8MM_CLK_USB_BUS,
-		imx8m_clk_composite("usb_bus", imx8mm_usb_bus_sels, base + 0x8b80));
+		imx8m_clk_composite(dev, "usb_bus", imx8mm_usb_bus_sels, base + 0x8b80));
 
 	/* IP */
 #if CONFIG_IS_ENABLED(PCIE_DW_IMX)
 	clk_dm(IMX8MM_CLK_PCIE1_CTRL,
-	       imx8m_clk_composite("pcie1_ctrl", imx8mm_pcie1_ctrl_sels,
+	       imx8m_clk_composite(dev, "pcie1_ctrl", imx8mm_pcie1_ctrl_sels,
 				   base + 0xa300));
 	clk_dm(IMX8MM_CLK_PCIE1_PHY,
-	       imx8m_clk_composite("pcie1_phy", imx8mm_pcie1_phy_sels,
+	       imx8m_clk_composite(dev, "pcie1_phy", imx8mm_pcie1_phy_sels,
 				   base + 0xa380));
 	clk_dm(IMX8MM_CLK_PCIE1_AUX,
-	       imx8m_clk_composite("pcie1_aux", imx8mm_pcie1_aux_sels,
+	       imx8m_clk_composite(dev, "pcie1_aux", imx8mm_pcie1_aux_sels,
 				   base + 0xa400));
 #endif
 	clk_dm(IMX8MM_CLK_USDHC1,
-	       imx8m_clk_composite("usdhc1", imx8mm_usdhc1_sels,
+	       imx8m_clk_composite(dev, "usdhc1", imx8mm_usdhc1_sels,
 				   base + 0xac00));
 	clk_dm(IMX8MM_CLK_USDHC2,
-	       imx8m_clk_composite("usdhc2", imx8mm_usdhc2_sels,
+	       imx8m_clk_composite(dev, "usdhc2", imx8mm_usdhc2_sels,
 				   base + 0xac80));
 	clk_dm(IMX8MM_CLK_I2C1,
-	       imx8m_clk_composite("i2c1", imx8mm_i2c1_sels, base + 0xad00));
+	       imx8m_clk_composite(dev, "i2c1", imx8mm_i2c1_sels, base + 0xad00));
 	clk_dm(IMX8MM_CLK_I2C2,
-	       imx8m_clk_composite("i2c2", imx8mm_i2c2_sels, base + 0xad80));
+	       imx8m_clk_composite(dev, "i2c2", imx8mm_i2c2_sels, base + 0xad80));
 	clk_dm(IMX8MM_CLK_I2C3,
-	       imx8m_clk_composite("i2c3", imx8mm_i2c3_sels, base + 0xae00));
+	       imx8m_clk_composite(dev, "i2c3", imx8mm_i2c3_sels, base + 0xae00));
 	clk_dm(IMX8MM_CLK_I2C4,
-	       imx8m_clk_composite("i2c4", imx8mm_i2c4_sels, base + 0xae80));
+	       imx8m_clk_composite(dev, "i2c4", imx8mm_i2c4_sels, base + 0xae80));
+	clk_dm(IMX8MM_CLK_UART1,
+	       imx8m_clk_composite(dev, "uart1", imx8mm_uart1_sels, base + 0xaf00));
+	clk_dm(IMX8MM_CLK_UART2,
+	       imx8m_clk_composite(dev, "uart2", imx8mm_uart2_sels, base + 0xaf80));
+	clk_dm(IMX8MM_CLK_UART3,
+	       imx8m_clk_composite(dev, "uart3", imx8mm_uart3_sels, base + 0xb000));
+	clk_dm(IMX8MM_CLK_UART4,
+	       imx8m_clk_composite(dev, "uart4", imx8mm_uart4_sels, base + 0xb080));
+	clk_dm(IMX8MM_CLK_UART1_ROOT,
+	       imx_clk_gate4(dev, "uart1_root_clk", "uart1", base + 0x4490, 0));
+	clk_dm(IMX8MM_CLK_UART2_ROOT,
+	       imx_clk_gate4(dev, "uart2_root_clk", "uart2", base + 0x44a0, 0));
+	clk_dm(IMX8MM_CLK_UART3_ROOT,
+	       imx_clk_gate4(dev, "uart3_root_clk", "uart3", base + 0x44b0, 0));
+	clk_dm(IMX8MM_CLK_UART4_ROOT,
+	       imx_clk_gate4(dev, "uart4_root_clk", "uart4", base + 0x44c0, 0));
 	clk_dm(IMX8MM_CLK_WDOG,
-	       imx8m_clk_composite("wdog", imx8mm_wdog_sels, base + 0xb900));
+	       imx8m_clk_composite(dev, "wdog", imx8mm_wdog_sels, base + 0xb900));
 	clk_dm(IMX8MM_CLK_USDHC3,
-	       imx8m_clk_composite("usdhc3", imx8mm_usdhc3_sels,
+	       imx8m_clk_composite(dev, "usdhc3", imx8mm_usdhc3_sels,
 				   base + 0xbc80));
 	clk_dm(IMX8MM_CLK_USB_CORE_REF,
-		imx8m_clk_composite("usb_core_ref", imx8mm_usb_core_sels, base + 0xb100));
+		imx8m_clk_composite(dev, "usb_core_ref", imx8mm_usb_core_sels, base + 0xb100));
 	clk_dm(IMX8MM_CLK_USB_PHY_REF,
-		imx8m_clk_composite("usb_phy_ref", imx8mm_usb_phy_sels, base + 0xb180));
+		imx8m_clk_composite(dev, "usb_phy_ref", imx8mm_usb_phy_sels, base + 0xb180));
 	clk_dm(IMX8MM_CLK_I2C1_ROOT,
-	       imx_clk_gate4("i2c1_root_clk", "i2c1", base + 0x4170, 0));
+	       imx_clk_gate4(dev, "i2c1_root_clk", "i2c1", base + 0x4170, 0));
 	clk_dm(IMX8MM_CLK_I2C2_ROOT,
-	       imx_clk_gate4("i2c2_root_clk", "i2c2", base + 0x4180, 0));
+	       imx_clk_gate4(dev, "i2c2_root_clk", "i2c2", base + 0x4180, 0));
 	clk_dm(IMX8MM_CLK_I2C3_ROOT,
-	       imx_clk_gate4("i2c3_root_clk", "i2c3", base + 0x4190, 0));
+	       imx_clk_gate4(dev, "i2c3_root_clk", "i2c3", base + 0x4190, 0));
 	clk_dm(IMX8MM_CLK_I2C4_ROOT,
-	       imx_clk_gate4("i2c4_root_clk", "i2c4", base + 0x41a0, 0));
+	       imx_clk_gate4(dev, "i2c4_root_clk", "i2c4", base + 0x41a0, 0));
 	clk_dm(IMX8MM_CLK_OCOTP_ROOT,
-	       imx_clk_gate4("ocotp_root_clk", "ipg_root", base + 0x4220, 0));
+	       imx_clk_gate4(dev, "ocotp_root_clk", "ipg_root", base + 0x4220, 0));
 	clk_dm(IMX8MM_CLK_USDHC1_ROOT,
-	       imx_clk_gate4("usdhc1_root_clk", "usdhc1", base + 0x4510, 0));
+	       imx_clk_gate4(dev, "usdhc1_root_clk", "usdhc1", base + 0x4510, 0));
 	clk_dm(IMX8MM_CLK_USDHC2_ROOT,
-	       imx_clk_gate4("usdhc2_root_clk", "usdhc2", base + 0x4520, 0));
+	       imx_clk_gate4(dev, "usdhc2_root_clk", "usdhc2", base + 0x4520, 0));
 	clk_dm(IMX8MM_CLK_WDOG1_ROOT,
-	       imx_clk_gate4("wdog1_root_clk", "wdog", base + 0x4530, 0));
+	       imx_clk_gate4(dev, "wdog1_root_clk", "wdog", base + 0x4530, 0));
 	clk_dm(IMX8MM_CLK_WDOG2_ROOT,
-	       imx_clk_gate4("wdog2_root_clk", "wdog", base + 0x4540, 0));
+	       imx_clk_gate4(dev, "wdog2_root_clk", "wdog", base + 0x4540, 0));
 	clk_dm(IMX8MM_CLK_WDOG3_ROOT,
-	       imx_clk_gate4("wdog3_root_clk", "wdog", base + 0x4550, 0));
+	       imx_clk_gate4(dev, "wdog3_root_clk", "wdog", base + 0x4550, 0));
 	clk_dm(IMX8MM_CLK_USDHC3_ROOT,
-	       imx_clk_gate4("usdhc3_root_clk", "usdhc3", base + 0x45e0, 0));
+	       imx_clk_gate4(dev, "usdhc3_root_clk", "usdhc3", base + 0x45e0, 0));
 	clk_dm(IMX8MM_CLK_USB1_CTRL_ROOT,
-		imx_clk_gate4("usb1_ctrl_root_clk", "usb_bus", base + 0x44d0, 0));
+		imx_clk_gate4(dev, "usb1_ctrl_root_clk", "usb_bus", base + 0x44d0, 0));
 
 	/* clks not needed in SPL stage */
 #ifndef CONFIG_XPL_BUILD
 	clk_dm(IMX8MM_CLK_ENET_AXI,
-	       imx8m_clk_composite("enet_axi", imx8mm_enet_axi_sels,
+	       imx8m_clk_composite(dev, "enet_axi", imx8mm_enet_axi_sels,
 				   base + 0x8880));
 	clk_dm(IMX8MM_CLK_ENET_REF,
-	       imx8m_clk_composite("enet_ref", imx8mm_enet_ref_sels,
+	       imx8m_clk_composite(dev, "enet_ref", imx8mm_enet_ref_sels,
 	       base + 0xa980));
 	clk_dm(IMX8MM_CLK_ENET_TIMER,
-	       imx8m_clk_composite("enet_timer", imx8mm_enet_timer_sels,
+	       imx8m_clk_composite(dev, "enet_timer", imx8mm_enet_timer_sels,
 	       base + 0xaa00));
 	clk_dm(IMX8MM_CLK_ENET_PHY_REF,
-	       imx8m_clk_composite("enet_phy", imx8mm_enet_phy_sels,
+	       imx8m_clk_composite(dev, "enet_phy", imx8mm_enet_phy_sels,
 	       base + 0xaa80));
 	clk_dm(IMX8MM_CLK_ENET1_ROOT,
-	       imx_clk_gate4("enet1_root_clk", "enet_axi",
+	       imx_clk_gate4(dev, "enet1_root_clk", "enet_axi",
 	       base + 0x40a0, 0));
 	clk_dm(IMX8MM_CLK_PWM1,
-	       imx8m_clk_composite("pwm1", imx8mm_pwm1_sels, base + 0xb380));
+	       imx8m_clk_composite(dev, "pwm1", imx8mm_pwm1_sels, base + 0xb380));
 	clk_dm(IMX8MM_CLK_PWM2,
-	       imx8m_clk_composite("pwm2", imx8mm_pwm2_sels, base + 0xb400));
+	       imx8m_clk_composite(dev, "pwm2", imx8mm_pwm2_sels, base + 0xb400));
 	clk_dm(IMX8MM_CLK_PWM3,
-	       imx8m_clk_composite("pwm3", imx8mm_pwm3_sels, base + 0xb480));
+	       imx8m_clk_composite(dev, "pwm3", imx8mm_pwm3_sels, base + 0xb480));
 	clk_dm(IMX8MM_CLK_PWM4,
-	       imx8m_clk_composite("pwm4", imx8mm_pwm4_sels, base + 0xb500));
+	       imx8m_clk_composite(dev, "pwm4", imx8mm_pwm4_sels, base + 0xb500));
 	clk_dm(IMX8MM_CLK_PWM1_ROOT,
-	       imx_clk_gate4("pwm1_root_clk", "pwm1", base + 0x4280, 0));
+	       imx_clk_gate4(dev, "pwm1_root_clk", "pwm1", base + 0x4280, 0));
 	clk_dm(IMX8MM_CLK_PWM2_ROOT,
-	       imx_clk_gate4("pwm2_root_clk", "pwm2", base + 0x4290, 0));
+	       imx_clk_gate4(dev, "pwm2_root_clk", "pwm2", base + 0x4290, 0));
 	clk_dm(IMX8MM_CLK_PWM3_ROOT,
-	       imx_clk_gate4("pwm3_root_clk", "pwm3", base + 0x42a0, 0));
+	       imx_clk_gate4(dev, "pwm3_root_clk", "pwm3", base + 0x42a0, 0));
 	clk_dm(IMX8MM_CLK_PWM4_ROOT,
-	       imx_clk_gate4("pwm4_root_clk", "pwm4", base + 0x42b0, 0));
+	       imx_clk_gate4(dev, "pwm4_root_clk", "pwm4", base + 0x42b0, 0));
 #endif
 
 #if CONFIG_IS_ENABLED(PCIE_DW_IMX)
 	clk_dm(IMX8MM_CLK_PCIE1_ROOT,
-	       imx_clk_gate4("pcie1_root_clk", "pcie1_ctrl", base + 0x4250, 0));
+	       imx_clk_gate4(dev, "pcie1_root_clk", "pcie1_ctrl", base + 0x4250, 0));
 #endif
 
 #if CONFIG_IS_ENABLED(DM_SPI)
 	clk_dm(IMX8MM_CLK_ECSPI1,
-	       imx8m_clk_composite("ecspi1", imx8mm_ecspi1_sels, base + 0xb280));
+	       imx8m_clk_composite(dev, "ecspi1", imx8mm_ecspi1_sels, base + 0xb280));
 	clk_dm(IMX8MM_CLK_ECSPI2,
-	       imx8m_clk_composite("ecspi2", imx8mm_ecspi2_sels, base + 0xb300));
+	       imx8m_clk_composite(dev, "ecspi2", imx8mm_ecspi2_sels, base + 0xb300));
 	clk_dm(IMX8MM_CLK_ECSPI3,
-	       imx8m_clk_composite("ecspi3", imx8mm_ecspi3_sels, base + 0xc180));
+	       imx8m_clk_composite(dev, "ecspi3", imx8mm_ecspi3_sels, base + 0xc180));
 
 	clk_dm(IMX8MM_CLK_ECSPI1_ROOT,
-	       imx_clk_gate4("ecspi1_root_clk", "ecspi1", base + 0x4070, 0));
+	       imx_clk_gate4(dev, "ecspi1_root_clk", "ecspi1", base + 0x4070, 0));
 	clk_dm(IMX8MM_CLK_ECSPI2_ROOT,
-	       imx_clk_gate4("ecspi2_root_clk", "ecspi2", base + 0x4080, 0));
+	       imx_clk_gate4(dev, "ecspi2_root_clk", "ecspi2", base + 0x4080, 0));
 	clk_dm(IMX8MM_CLK_ECSPI3_ROOT,
-	       imx_clk_gate4("ecspi3_root_clk", "ecspi3", base + 0x4090, 0));
+	       imx_clk_gate4(dev, "ecspi3_root_clk", "ecspi3", base + 0x4090, 0));
 #endif
 
 #if CONFIG_IS_ENABLED(NXP_FSPI)
 	clk_dm(IMX8MM_CLK_QSPI,
-	       imx8m_clk_composite("qspi", imx8mm_qspi_sels, base + 0xab80));
+	       imx8m_clk_composite(dev, "qspi", imx8mm_qspi_sels, base + 0xab80));
 	clk_dm(IMX8MM_CLK_QSPI_ROOT,
-	       imx_clk_gate4("qspi_root_clk", "qspi", base + 0x42f0, 0));
+	       imx_clk_gate4(dev, "qspi_root_clk", "qspi", base + 0x42f0, 0));
 #endif
 
 	clk_dm(IMX8MM_CLK_ARM,
-	       imx_clk_mux2_flags("arm_core", base + 0x9880, 24, 1,
+	       imx_clk_mux2_flags(dev, "arm_core", base + 0x9880, 24, 1,
 				  imx8mm_arm_core_sels,
 				  ARRAY_SIZE(imx8mm_arm_core_sels),
 				  CLK_IS_CRITICAL));
diff --git a/drivers/clk/imx/clk-imx8mn.c b/drivers/clk/imx/clk-imx8mn.c
index be15ebd0e25..be5b7933a8d 100644
--- a/drivers/clk/imx/clk-imx8mn.c
+++ b/drivers/clk/imx/clk-imx8mn.c
@@ -16,7 +16,7 @@
 
 static u32 share_count_nand;
 
-static const char * const pll_ref_sels[] = { "clock-osc-24m", "dummy", "dummy", "dummy", };
+static const char * const pll_ref_sels[] = { "osc_24m", "dummy", "dummy", "dummy", };
 static const char * const dram_pll_bypass_sels[] = {"dram_pll", "dram_pll_ref_sel", };
 static const char * const arm_pll_bypass_sels[] = {"arm_pll", "arm_pll_ref_sel", };
 static const char * const sys_pll1_bypass_sels[] = {"sys_pll1", "sys_pll1_ref_sel", };
@@ -25,117 +25,133 @@ static const char * const sys_pll3_bypass_sels[] = {"sys_pll3", "sys_pll3_ref_se
 
 static const char * const imx8mn_arm_core_sels[] = {"arm_a53_src", "arm_pll_out", };
 
-static const char * const imx8mn_a53_sels[] = {"clock-osc-24m", "arm_pll_out", "sys_pll2_500m",
+static const char * const imx8mn_a53_sels[] = {"osc_24m", "arm_pll_out", "sys_pll2_500m",
 					       "sys_pll2_1000m", "sys_pll1_800m", "sys_pll1_400m",
 					       "audio_pll1_out", "sys_pll3_out", };
 
-static const char * const imx8mn_ahb_sels[] = {"clock-osc-24m", "sys_pll1_133m", "sys_pll1_800m",
+static const char * const imx8mn_ahb_sels[] = {"osc_24m", "sys_pll1_133m", "sys_pll1_800m",
 					       "sys_pll1_400m", "sys_pll2_125m", "sys_pll3_out",
 					       "audio_pll1_out", "video_pll_out", };
 
-static const char * const imx8mn_enet_axi_sels[] = {"clock-osc-24m", "sys_pll1_266m", "sys_pll1_800m",
+static const char * const imx8mn_enet_axi_sels[] = {"osc_24m", "sys_pll1_266m", "sys_pll1_800m",
 						    "sys_pll2_250m", "sys_pll2_200m", "audio_pll1_out",
 						    "video_pll_out", "sys_pll3_out", };
 
 #ifndef CONFIG_XPL_BUILD
-static const char * const imx8mn_enet_ref_sels[] = {"clock-osc-24m", "sys_pll2_125m", "sys_pll2_50m",
+static const char * const imx8mn_enet_ref_sels[] = {"osc_24m", "sys_pll2_125m", "sys_pll2_50m",
 						    "sys_pll2_100m", "sys_pll1_160m", "audio_pll1_out",
 						    "video_pll_out", "clk_ext4", };
 
-static const char * const imx8mn_enet_timer_sels[] = {"clock-osc-24m", "sys_pll2_100m", "audio_pll1_out",
+static const char * const imx8mn_enet_timer_sels[] = {"osc_24m", "sys_pll2_100m", "audio_pll1_out",
 						      "clk_ext1", "clk_ext2", "clk_ext3",
 						      "clk_ext4", "video_pll_out", };
 
-static const char * const imx8mn_enet_phy_sels[] = {"clock-osc-24m", "sys_pll2_50m", "sys_pll2_125m",
+static const char * const imx8mn_enet_phy_sels[] = {"osc_24m", "sys_pll2_50m", "sys_pll2_125m",
 						    "sys_pll2_200m", "sys_pll2_500m", "audio_pll1_out",
 						    "video_pll_out", "audio_pll2_out", };
 #endif
 
-static const char * const imx8mn_nand_usdhc_sels[] = {"clock-osc-24m", "sys_pll1_266m", "sys_pll1_800m",
+static const char * const imx8mn_nand_usdhc_sels[] = {"osc_24m", "sys_pll1_266m", "sys_pll1_800m",
 						      "sys_pll2_200m", "sys_pll1_133m", "sys_pll3_out",
 						      "sys_pll2_250m", "audio_pll1_out", };
 
-static const char * const imx8mn_usb_bus_sels[] = {"clock-osc-24m", "sys_pll2_500m", "sys_pll1_800m",
+static const char * const imx8mn_usb_bus_sels[] = {"osc_24m", "sys_pll2_500m", "sys_pll1_800m",
 						   "sys_pll2_100m", "sys_pll2_200m", "clk_ext2",
 						   "clk_ext4", "audio_pll2_out", };
 
-static const char * const imx8mn_usdhc1_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sys_pll1_800m",
+static const char * const imx8mn_usdhc1_sels[] = {"osc_24m", "sys_pll1_400m", "sys_pll1_800m",
 						  "sys_pll2_500m", "sys_pll3_out", "sys_pll1_266m",
 						  "audio_pll2_out", "sys_pll1_100m", };
 
-static const char * const imx8mn_usdhc2_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sys_pll1_800m",
+static const char * const imx8mn_usdhc2_sels[] = {"osc_24m", "sys_pll1_400m", "sys_pll1_800m",
 						  "sys_pll2_500m", "sys_pll3_out", "sys_pll1_266m",
 						  "audio_pll2_out", "sys_pll1_100m", };
 
 #if CONFIG_IS_ENABLED(DM_SPI)
-static const char * const imx8mn_ecspi1_sels[] = {"clock-osc-24m", "sys_pll2_200m", "sys_pll1_40m",
+static const char * const imx8mn_ecspi1_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1_40m",
 						  "sys_pll1_160m", "sys_pll1_800m", "sys_pll3_out",
 						  "sys_pll2_250m", "audio_pll2_out", };
 
-static const char * const imx8mn_ecspi2_sels[] = {"clock-osc-24m", "sys_pll2_200m", "sys_pll1_40m",
+static const char * const imx8mn_ecspi2_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1_40m",
 						  "sys_pll1_160m", "sys_pll1_800m", "sys_pll3_out",
 						  "sys_pll2_250m", "audio_pll2_out", };
 
-static const char * const imx8mn_ecspi3_sels[] = {"clock-osc-24m", "sys_pll2_200m", "sys_pll1_40m",
+static const char * const imx8mn_ecspi3_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1_40m",
 						  "sys_pll1_160m", "sys_pll1_800m", "sys_pll3_out",
 						  "sys_pll2_250m", "audio_pll2_out", };
 #endif
 
-static const char * const imx8mn_i2c1_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m",
+static const char * const imx8mn_i2c1_sels[] = {"osc_24m", "sys_pll1_160m", "sys_pll2_50m",
 						"sys_pll3_out", "audio_pll1_out", "video_pll_out",
 						"audio_pll2_out", "sys_pll1_133m", };
 
-static const char * const imx8mn_i2c2_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m",
+static const char * const imx8mn_i2c2_sels[] = {"osc_24m", "sys_pll1_160m", "sys_pll2_50m",
 						"sys_pll3_out", "audio_pll1_out", "video_pll_out",
 						"audio_pll2_out", "sys_pll1_133m", };
 
-static const char * const imx8mn_i2c3_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m",
+static const char * const imx8mn_i2c3_sels[] = {"osc_24m", "sys_pll1_160m", "sys_pll2_50m",
 						"sys_pll3_out", "audio_pll1_out", "video_pll_out",
 						"audio_pll2_out", "sys_pll1_133m", };
 
-static const char * const imx8mn_i2c4_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m",
+static const char * const imx8mn_i2c4_sels[] = {"osc_24m", "sys_pll1_160m", "sys_pll2_50m",
 						"sys_pll3_out", "audio_pll1_out", "video_pll_out",
 						"audio_pll2_out", "sys_pll1_133m", };
 
+static const char * const imx8mn_uart1_sels[] = {"clock-osc-24m", "sys_pll1_80m", "sys_pll2_200m",
+						 "sys_pll2_100m", "sys_pll3_out", "clk_ext2",
+						 "clk_ext4", "audio_pll2_out", };
+
+static const char * const imx8mn_uart2_sels[] = {"clock-osc-24m", "sys_pll1_80m", "sys_pll2_200m",
+						 "sys_pll2_100m", "sys_pll3_out", "clk_ext2",
+						 "clk_ext3", "audio_pll2_out", };
+
+static const char * const imx8mn_uart3_sels[] = {"clock-osc-24m", "sys_pll1_80m", "sys_pll2_200m",
+						 "sys_pll2_100m", "sys_pll3_out", "clk_ext2",
+						 "clk_ext4", "audio_pll2_out", };
+
+static const char * const imx8mn_uart4_sels[] = {"clock-osc-24m", "sys_pll1_80m", "sys_pll2_200m",
+						 "sys_pll2_100m", "sys_pll3_out", "clk_ext2",
+						 "clk_ext3", "audio_pll2_out", };
+
 #ifndef CONFIG_XPL_BUILD
-static const char * const imx8mn_pwm1_sels[] = {"clock-osc-24m", "sys_pll2_100m", "sys_pll1_160m",
+static const char * const imx8mn_pwm1_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_160m",
 						"sys_pll1_40m", "sys_pll3_out", "clk_ext1",
 						"sys_pll1_80m", "video_pll_out", };
 
-static const char * const imx8mn_pwm2_sels[] = {"clock-osc-24m", "sys_pll2_100m", "sys_pll1_160m",
+static const char * const imx8mn_pwm2_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_160m",
 						"sys_pll1_40m", "sys_pll3_out", "clk_ext1",
 						"sys_pll1_80m", "video_pll_out", };
 
-static const char * const imx8mn_pwm3_sels[] = {"clock-osc-24m", "sys_pll2_100m", "sys_pll1_160m",
+static const char * const imx8mn_pwm3_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_160m",
 						"sys_pll1_40m", "sys_pll3_out", "clk_ext2",
 						"sys_pll1_80m", "video_pll_out", };
 
-static const char * const imx8mn_pwm4_sels[] = {"clock-osc-24m", "sys_pll2_100m", "sys_pll1_160m",
+static const char * const imx8mn_pwm4_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_160m",
 						"sys_pll1_40m", "sys_pll3_out", "clk_ext2",
 						"sys_pll1_80m", "video_pll_out", };
 #endif
 
-static const char * const imx8mn_wdog_sels[] = {"clock-osc-24m", "sys_pll1_133m", "sys_pll1_160m",
+static const char * const imx8mn_wdog_sels[] = {"osc_24m", "sys_pll1_133m", "sys_pll1_160m",
 						"m7_alt_pll", "sys_pll2_125m", "sys_pll3_out",
 						"sys_pll1_80m", "sys_pll2_166m", };
 
-static const char * const imx8mn_usdhc3_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sys_pll1_800m",
+static const char * const imx8mn_usdhc3_sels[] = {"osc_24m", "sys_pll1_400m", "sys_pll1_800m",
 						  "sys_pll2_500m", "sys_pll3_out", "sys_pll1_266m",
 						  "audio_pll2_clk", "sys_pll1_100m", };
 
-static const char * const imx8mn_qspi_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sys_pll2_333m",
+static const char * const imx8mn_qspi_sels[] = {"osc_24m", "sys_pll1_400m", "sys_pll2_333m",
 						"sys_pll2_500m", "audio_pll2_out", "sys_pll1_266m",
 						"sys_pll3_out", "sys_pll1_100m", };
 
-static const char * const imx8mn_nand_sels[] = {"clock-osc-24m", "sys_pll2_500m", "audio_pll1_out",
+static const char * const imx8mn_nand_sels[] = {"osc_24m", "sys_pll2_500m", "audio_pll1_out",
 						"sys_pll1_400m", "audio_pll2_out", "sys_pll3_out",
 						"sys_pll2_250m", "video_pll_out", };
 
-static const char * const imx8mn_usb_core_sels[] = {"clock-osc-24m", "sys_pll1_100m", "sys_pll1_40m",
+static const char * const imx8mn_usb_core_sels[] = {"osc_24m", "sys_pll1_100m", "sys_pll1_40m",
 						    "sys_pll2_100m", "sys_pll2_200m", "clk_ext2",
 						    "clk_ext3", "audio_pll2_out", };
 
-static const char * const imx8mn_usb_phy_sels[] = {"clock-osc-24m", "sys_pll1_100m", "sys_pll1_40m",
+static const char * const imx8mn_usb_phy_sels[] = {"osc_24m", "sys_pll1_100m", "sys_pll1_40m",
 						   "sys_pll2_100m", "sys_pll2_200m", "clk_ext2",
 						   "clk_ext3", "audio_pll2_out", };
 
@@ -148,19 +164,19 @@ static int imx8mn_clk_probe(struct udevice *dev)
 	base = (void *)ANATOP_BASE_ADDR;
 
 	clk_dm(IMX8MN_DRAM_PLL_REF_SEL,
-	       imx_clk_mux("dram_pll_ref_sel", base + 0x50, 0, 2,
+	       imx_clk_mux(dev, "dram_pll_ref_sel", base + 0x50, 0, 2,
 			   pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
 	clk_dm(IMX8MN_ARM_PLL_REF_SEL,
-	       imx_clk_mux("arm_pll_ref_sel", base + 0x84, 0, 2,
+	       imx_clk_mux(dev, "arm_pll_ref_sel", base + 0x84, 0, 2,
 			   pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
 	clk_dm(IMX8MN_SYS_PLL1_REF_SEL,
-	       imx_clk_mux("sys_pll1_ref_sel", base + 0x94, 0, 2,
+	       imx_clk_mux(dev, "sys_pll1_ref_sel", base + 0x94, 0, 2,
 			   pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
 	clk_dm(IMX8MN_SYS_PLL2_REF_SEL,
-	       imx_clk_mux("sys_pll2_ref_sel", base + 0x104, 0, 2,
+	       imx_clk_mux(dev, "sys_pll2_ref_sel", base + 0x104, 0, 2,
 			   pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
 	clk_dm(IMX8MN_SYS_PLL3_REF_SEL,
-	       imx_clk_mux("sys_pll3_ref_sel", base + 0x114, 0, 2,
+	       imx_clk_mux(dev, "sys_pll3_ref_sel", base + 0x114, 0, 2,
 			   pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
 
 	clk_dm(IMX8MN_DRAM_PLL,
@@ -181,86 +197,86 @@ static int imx8mn_clk_probe(struct udevice *dev)
 
 	/* PLL bypass out */
 	clk_dm(IMX8MN_DRAM_PLL_BYPASS,
-	       imx_clk_mux_flags("dram_pll_bypass", base + 0x50, 4, 1,
+	       imx_clk_mux_flags(dev, "dram_pll_bypass", base + 0x50, 4, 1,
 				 dram_pll_bypass_sels,
 				 ARRAY_SIZE(dram_pll_bypass_sels),
 				 CLK_SET_RATE_PARENT));
 	clk_dm(IMX8MN_ARM_PLL_BYPASS,
-	       imx_clk_mux_flags("arm_pll_bypass", base + 0x84, 4, 1,
+	       imx_clk_mux_flags(dev, "arm_pll_bypass", base + 0x84, 4, 1,
 				 arm_pll_bypass_sels,
 				 ARRAY_SIZE(arm_pll_bypass_sels),
 				 CLK_SET_RATE_PARENT));
 	clk_dm(IMX8MN_SYS_PLL1_BYPASS,
-	       imx_clk_mux_flags("sys_pll1_bypass", base + 0x94, 4, 1,
+	       imx_clk_mux_flags(dev, "sys_pll1_bypass", base + 0x94, 4, 1,
 				 sys_pll1_bypass_sels,
 				 ARRAY_SIZE(sys_pll1_bypass_sels),
 				 CLK_SET_RATE_PARENT));
 	clk_dm(IMX8MN_SYS_PLL2_BYPASS,
-	       imx_clk_mux_flags("sys_pll2_bypass", base + 0x104, 4, 1,
+	       imx_clk_mux_flags(dev, "sys_pll2_bypass", base + 0x104, 4, 1,
 				 sys_pll2_bypass_sels,
 				 ARRAY_SIZE(sys_pll2_bypass_sels),
 				 CLK_SET_RATE_PARENT));
 	clk_dm(IMX8MN_SYS_PLL3_BYPASS,
-	       imx_clk_mux_flags("sys_pll3_bypass", base + 0x114, 4, 1,
+	       imx_clk_mux_flags(dev, "sys_pll3_bypass", base + 0x114, 4, 1,
 				 sys_pll3_bypass_sels,
 				 ARRAY_SIZE(sys_pll3_bypass_sels),
 				 CLK_SET_RATE_PARENT));
 
 	/* PLL out gate */
 	clk_dm(IMX8MN_DRAM_PLL_OUT,
-	       imx_clk_gate("dram_pll_out", "dram_pll_bypass",
+	       imx_clk_gate(dev, "dram_pll_out", "dram_pll_bypass",
 			    base + 0x50, 13));
 	clk_dm(IMX8MN_ARM_PLL_OUT,
-	       imx_clk_gate("arm_pll_out", "arm_pll_bypass",
+	       imx_clk_gate(dev, "arm_pll_out", "arm_pll_bypass",
 			    base + 0x84, 11));
 	clk_dm(IMX8MN_SYS_PLL1_OUT,
-	       imx_clk_gate("sys_pll1_out", "sys_pll1_bypass",
+	       imx_clk_gate(dev, "sys_pll1_out", "sys_pll1_bypass",
 			    base + 0x94, 11));
 	clk_dm(IMX8MN_SYS_PLL2_OUT,
-	       imx_clk_gate("sys_pll2_out", "sys_pll2_bypass",
+	       imx_clk_gate(dev, "sys_pll2_out", "sys_pll2_bypass",
 			    base + 0x104, 11));
 	clk_dm(IMX8MN_SYS_PLL3_OUT,
-	       imx_clk_gate("sys_pll3_out", "sys_pll3_bypass",
+	       imx_clk_gate(dev, "sys_pll3_out", "sys_pll3_bypass",
 			    base + 0x114, 11));
 
 	/* SYS PLL fixed output */
 	clk_dm(IMX8MN_SYS_PLL1_40M,
-	       imx_clk_fixed_factor("sys_pll1_40m", "sys_pll1_out", 1, 20));
+	       imx_clk_fixed_factor(dev, "sys_pll1_40m", "sys_pll1_out", 1, 20));
 	clk_dm(IMX8MN_SYS_PLL1_80M,
-	       imx_clk_fixed_factor("sys_pll1_80m", "sys_pll1_out", 1, 10));
+	       imx_clk_fixed_factor(dev, "sys_pll1_80m", "sys_pll1_out", 1, 10));
 	clk_dm(IMX8MN_SYS_PLL1_100M,
-	       imx_clk_fixed_factor("sys_pll1_100m", "sys_pll1_out", 1, 8));
+	       imx_clk_fixed_factor(dev, "sys_pll1_100m", "sys_pll1_out", 1, 8));
 	clk_dm(IMX8MN_SYS_PLL1_133M,
-	       imx_clk_fixed_factor("sys_pll1_133m", "sys_pll1_out", 1, 6));
+	       imx_clk_fixed_factor(dev, "sys_pll1_133m", "sys_pll1_out", 1, 6));
 	clk_dm(IMX8MN_SYS_PLL1_160M,
-	       imx_clk_fixed_factor("sys_pll1_160m", "sys_pll1_out", 1, 5));
+	       imx_clk_fixed_factor(dev, "sys_pll1_160m", "sys_pll1_out", 1, 5));
 	clk_dm(IMX8MN_SYS_PLL1_200M,
-	       imx_clk_fixed_factor("sys_pll1_200m", "sys_pll1_out", 1, 4));
+	       imx_clk_fixed_factor(dev, "sys_pll1_200m", "sys_pll1_out", 1, 4));
 	clk_dm(IMX8MN_SYS_PLL1_266M,
-	       imx_clk_fixed_factor("sys_pll1_266m", "sys_pll1_out", 1, 3));
+	       imx_clk_fixed_factor(dev, "sys_pll1_266m", "sys_pll1_out", 1, 3));
 	clk_dm(IMX8MN_SYS_PLL1_400M,
-	       imx_clk_fixed_factor("sys_pll1_400m", "sys_pll1_out", 1, 2));
+	       imx_clk_fixed_factor(dev, "sys_pll1_400m", "sys_pll1_out", 1, 2));
 	clk_dm(IMX8MN_SYS_PLL1_800M,
-	       imx_clk_fixed_factor("sys_pll1_800m", "sys_pll1_out", 1, 1));
+	       imx_clk_fixed_factor(dev, "sys_pll1_800m", "sys_pll1_out", 1, 1));
 
 	clk_dm(IMX8MN_SYS_PLL2_50M,
-	       imx_clk_fixed_factor("sys_pll2_50m", "sys_pll2_out", 1, 20));
+	       imx_clk_fixed_factor(dev, "sys_pll2_50m", "sys_pll2_out", 1, 20));
 	clk_dm(IMX8MN_SYS_PLL2_100M,
-	       imx_clk_fixed_factor("sys_pll2_100m", "sys_pll2_out", 1, 10));
+	       imx_clk_fixed_factor(dev, "sys_pll2_100m", "sys_pll2_out", 1, 10));
 	clk_dm(IMX8MN_SYS_PLL2_125M,
-	       imx_clk_fixed_factor("sys_pll2_125m", "sys_pll2_out", 1, 8));
+	       imx_clk_fixed_factor(dev, "sys_pll2_125m", "sys_pll2_out", 1, 8));
 	clk_dm(IMX8MN_SYS_PLL2_166M,
-	       imx_clk_fixed_factor("sys_pll2_166m", "sys_pll2_out", 1, 6));
+	       imx_clk_fixed_factor(dev, "sys_pll2_166m", "sys_pll2_out", 1, 6));
 	clk_dm(IMX8MN_SYS_PLL2_200M,
-	       imx_clk_fixed_factor("sys_pll2_200m", "sys_pll2_out", 1, 5));
+	       imx_clk_fixed_factor(dev, "sys_pll2_200m", "sys_pll2_out", 1, 5));
 	clk_dm(IMX8MN_SYS_PLL2_250M,
-	       imx_clk_fixed_factor("sys_pll2_250m", "sys_pll2_out", 1, 4));
+	       imx_clk_fixed_factor(dev, "sys_pll2_250m", "sys_pll2_out", 1, 4));
 	clk_dm(IMX8MN_SYS_PLL2_333M,
-	       imx_clk_fixed_factor("sys_pll2_333m", "sys_pll2_out", 1, 3));
+	       imx_clk_fixed_factor(dev, "sys_pll2_333m", "sys_pll2_out", 1, 3));
 	clk_dm(IMX8MN_SYS_PLL2_500M,
-	       imx_clk_fixed_factor("sys_pll2_500m", "sys_pll2_out", 1, 2));
+	       imx_clk_fixed_factor(dev, "sys_pll2_500m", "sys_pll2_out", 1, 2));
 	clk_dm(IMX8MN_SYS_PLL2_1000M,
-	       imx_clk_fixed_factor("sys_pll2_1000m", "sys_pll2_out", 1, 1));
+	       imx_clk_fixed_factor(dev, "sys_pll2_1000m", "sys_pll2_out", 1, 1));
 
 	ret = clk_get_by_name(dev, "osc_24m", &osc_24m_clk);
 	if (ret)
@@ -272,141 +288,157 @@ static int imx8mn_clk_probe(struct udevice *dev)
 		return -EINVAL;
 
 	clk_dm(IMX8MN_CLK_A53_SRC,
-	       imx_clk_mux2("arm_a53_src", base + 0x8000, 24, 3,
+	       imx_clk_mux2(dev, "arm_a53_src", base + 0x8000, 24, 3,
 			    imx8mn_a53_sels, ARRAY_SIZE(imx8mn_a53_sels)));
 	clk_dm(IMX8MN_CLK_A53_CG,
-	       imx_clk_gate3("arm_a53_cg", "arm_a53_src", base + 0x8000, 28));
+	       imx_clk_gate3(dev, "arm_a53_cg", "arm_a53_src", base + 0x8000, 28));
 	clk_dm(IMX8MN_CLK_A53_DIV,
-	       imx_clk_divider2("arm_a53_div", "arm_a53_cg",
+	       imx_clk_divider2(dev, "arm_a53_div", "arm_a53_cg",
 				base + 0x8000, 0, 3));
 
 	clk_dm(IMX8MN_CLK_AHB,
-	       imx8m_clk_composite_critical("ahb", imx8mn_ahb_sels,
+	       imx8m_clk_composite_critical(dev, "ahb", imx8mn_ahb_sels,
 					    base + 0x9000));
 	clk_dm(IMX8MN_CLK_IPG_ROOT,
-	       imx_clk_divider2("ipg_root", "ahb", base + 0x9080, 0, 1));
+	       imx_clk_divider2(dev, "ipg_root", "ahb", base + 0x9080, 0, 1));
 
 	clk_dm(IMX8MN_CLK_ENET_AXI,
-	       imx8m_clk_composite("enet_axi", imx8mn_enet_axi_sels,
+	       imx8m_clk_composite(dev, "enet_axi", imx8mn_enet_axi_sels,
 				   base + 0x8880));
 	clk_dm(IMX8MN_CLK_NAND_USDHC_BUS,
-	       imx8m_clk_composite_critical("nand_usdhc_bus",
+	       imx8m_clk_composite_critical(dev, "nand_usdhc_bus",
 					    imx8mn_nand_usdhc_sels,
 					    base + 0x8900));
 	clk_dm(IMX8MN_CLK_USB_BUS,
-		imx8m_clk_composite("usb_bus", imx8mn_usb_bus_sels, base + 0x8b80));
+		imx8m_clk_composite(dev, "usb_bus", imx8mn_usb_bus_sels, base + 0x8b80));
 
 	/* IP */
 	clk_dm(IMX8MN_CLK_USDHC1,
-	       imx8m_clk_composite("usdhc1", imx8mn_usdhc1_sels,
+	       imx8m_clk_composite(dev, "usdhc1", imx8mn_usdhc1_sels,
 				   base + 0xac00));
 	clk_dm(IMX8MN_CLK_USDHC2,
-	       imx8m_clk_composite("usdhc2", imx8mn_usdhc2_sels,
+	       imx8m_clk_composite(dev, "usdhc2", imx8mn_usdhc2_sels,
 				   base + 0xac80));
 	clk_dm(IMX8MN_CLK_I2C1,
-	       imx8m_clk_composite("i2c1", imx8mn_i2c1_sels, base + 0xad00));
+	       imx8m_clk_composite(dev, "i2c1", imx8mn_i2c1_sels, base + 0xad00));
 	clk_dm(IMX8MN_CLK_I2C2,
-	       imx8m_clk_composite("i2c2", imx8mn_i2c2_sels, base + 0xad80));
+	       imx8m_clk_composite(dev, "i2c2", imx8mn_i2c2_sels, base + 0xad80));
 	clk_dm(IMX8MN_CLK_I2C3,
-	       imx8m_clk_composite("i2c3", imx8mn_i2c3_sels, base + 0xae00));
+	       imx8m_clk_composite(dev, "i2c3", imx8mn_i2c3_sels, base + 0xae00));
 	clk_dm(IMX8MN_CLK_I2C4,
-	       imx8m_clk_composite("i2c4", imx8mn_i2c4_sels, base + 0xae80));
+	       imx8m_clk_composite(dev, "i2c4", imx8mn_i2c4_sels, base + 0xae80));
+	clk_dm(IMX8MN_CLK_UART1,
+	       imx8m_clk_composite(dev, "uart1", imx8mn_uart1_sels, base + 0xaf00));
+	clk_dm(IMX8MN_CLK_UART2,
+	       imx8m_clk_composite(dev, "uart2", imx8mn_uart2_sels, base + 0xaf80));
+	clk_dm(IMX8MN_CLK_UART3,
+	       imx8m_clk_composite(dev, "uart3", imx8mn_uart3_sels, base + 0xb000));
+	clk_dm(IMX8MN_CLK_UART4,
+	       imx8m_clk_composite(dev, "uart4", imx8mn_uart4_sels, base + 0xb080));
 	clk_dm(IMX8MN_CLK_WDOG,
-	       imx8m_clk_composite("wdog", imx8mn_wdog_sels, base + 0xb900));
+	       imx8m_clk_composite(dev, "wdog", imx8mn_wdog_sels, base + 0xb900));
 	clk_dm(IMX8MN_CLK_USDHC3,
-	       imx8m_clk_composite("usdhc3", imx8mn_usdhc3_sels,
+	       imx8m_clk_composite(dev, "usdhc3", imx8mn_usdhc3_sels,
 				   base + 0xbc80));
 	clk_dm(IMX8MN_CLK_NAND,
-	       imx8m_clk_composite("nand", imx8mn_nand_sels, base + 0xab00));
+	       imx8m_clk_composite(dev, "nand", imx8mn_nand_sels, base + 0xab00));
 	clk_dm(IMX8MN_CLK_QSPI,
-	       imx8m_clk_composite("qspi", imx8mn_qspi_sels, base + 0xab80));
+	       imx8m_clk_composite(dev, "qspi", imx8mn_qspi_sels, base + 0xab80));
 	clk_dm(IMX8MN_CLK_USB_CORE_REF,
-		imx8m_clk_composite("usb_core_ref", imx8mn_usb_core_sels, base + 0xb100));
+		imx8m_clk_composite(dev, "usb_core_ref", imx8mn_usb_core_sels, base + 0xb100));
 	clk_dm(IMX8MN_CLK_USB_PHY_REF,
-		imx8m_clk_composite("usb_phy_ref", imx8mn_usb_phy_sels, base + 0xb180));
+		imx8m_clk_composite(dev, "usb_phy_ref", imx8mn_usb_phy_sels, base + 0xb180));
 
 	clk_dm(IMX8MN_CLK_I2C1_ROOT,
-	       imx_clk_gate4("i2c1_root_clk", "i2c1", base + 0x4170, 0));
+	       imx_clk_gate4(dev, "i2c1_root_clk", "i2c1", base + 0x4170, 0));
 	clk_dm(IMX8MN_CLK_I2C2_ROOT,
-	       imx_clk_gate4("i2c2_root_clk", "i2c2", base + 0x4180, 0));
+	       imx_clk_gate4(dev, "i2c2_root_clk", "i2c2", base + 0x4180, 0));
 	clk_dm(IMX8MN_CLK_I2C3_ROOT,
-	       imx_clk_gate4("i2c3_root_clk", "i2c3", base + 0x4190, 0));
+	       imx_clk_gate4(dev, "i2c3_root_clk", "i2c3", base + 0x4190, 0));
 	clk_dm(IMX8MN_CLK_I2C4_ROOT,
-	       imx_clk_gate4("i2c4_root_clk", "i2c4", base + 0x41a0, 0));
+	       imx_clk_gate4(dev, "i2c4_root_clk", "i2c4", base + 0x41a0, 0));
 	clk_dm(IMX8MN_CLK_OCOTP_ROOT,
-	       imx_clk_gate4("ocotp_root_clk", "ipg_root", base + 0x4220, 0));
+	       imx_clk_gate4(dev, "ocotp_root_clk", "ipg_root", base + 0x4220, 0));
 	clk_dm(IMX8MN_CLK_USDHC1_ROOT,
-	       imx_clk_gate4("usdhc1_root_clk", "usdhc1", base + 0x4510, 0));
+	       imx_clk_gate4(dev, "usdhc1_root_clk", "usdhc1", base + 0x4510, 0));
 	clk_dm(IMX8MN_CLK_USDHC2_ROOT,
-	       imx_clk_gate4("usdhc2_root_clk", "usdhc2", base + 0x4520, 0));
+	       imx_clk_gate4(dev, "usdhc2_root_clk", "usdhc2", base + 0x4520, 0));
 	clk_dm(IMX8MN_CLK_WDOG1_ROOT,
-	       imx_clk_gate4("wdog1_root_clk", "wdog", base + 0x4530, 0));
+	       imx_clk_gate4(dev, "wdog1_root_clk", "wdog", base + 0x4530, 0));
 	clk_dm(IMX8MN_CLK_WDOG2_ROOT,
-	       imx_clk_gate4("wdog2_root_clk", "wdog", base + 0x4540, 0));
+	       imx_clk_gate4(dev, "wdog2_root_clk", "wdog", base + 0x4540, 0));
 	clk_dm(IMX8MN_CLK_WDOG3_ROOT,
-	       imx_clk_gate4("wdog3_root_clk", "wdog", base + 0x4550, 0));
+	       imx_clk_gate4(dev, "wdog3_root_clk", "wdog", base + 0x4550, 0));
 	clk_dm(IMX8MN_CLK_USDHC3_ROOT,
-	       imx_clk_gate4("usdhc3_root_clk", "usdhc3", base + 0x45e0, 0));
+	       imx_clk_gate4(dev, "usdhc3_root_clk", "usdhc3", base + 0x45e0, 0));
 	clk_dm(IMX8MN_CLK_QSPI_ROOT,
-	       imx_clk_gate4("qspi_root_clk", "qspi", base + 0x42f0, 0));
+	       imx_clk_gate4(dev, "qspi_root_clk", "qspi", base + 0x42f0, 0));
 	clk_dm(IMX8MN_CLK_NAND_ROOT,
-	       imx_clk_gate2_shared2("nand_root_clk", "nand", base + 0x4300, 0, &share_count_nand));
+	       imx_clk_gate2_shared2(dev, "nand_root_clk", "nand", base + 0x4300, 0, &share_count_nand));
 	clk_dm(IMX8MN_CLK_NAND_USDHC_BUS_RAWNAND_CLK,
-	       imx_clk_gate2_shared2("nand_usdhc_rawnand_clk",
+	       imx_clk_gate2_shared2(dev, "nand_usdhc_rawnand_clk",
 				     "nand_usdhc_bus", base + 0x4300, 0,
 				     &share_count_nand));
+	clk_dm(IMX8MN_CLK_UART1_ROOT,
+	       imx_clk_gate4(dev, "uart1_root_clk", "uart1", base + 0x4490, 0));
+	clk_dm(IMX8MN_CLK_UART2_ROOT,
+	       imx_clk_gate4(dev, "uart2_root_clk", "uart2", base + 0x44a0, 0));
+	clk_dm(IMX8MN_CLK_UART3_ROOT,
+	       imx_clk_gate4(dev, "uart3_root_clk", "uart3", base + 0x44b0, 0));
+	clk_dm(IMX8MN_CLK_UART4_ROOT,
+	       imx_clk_gate4(dev, "uart4_root_clk", "uart4", base + 0x44c0, 0));
 	clk_dm(IMX8MN_CLK_USB1_CTRL_ROOT,
-		imx_clk_gate4("usb1_ctrl_root_clk", "usb_bus", base + 0x44d0, 0));
+		imx_clk_gate4(dev, "usb1_ctrl_root_clk", "usb_bus", base + 0x44d0, 0));
 
 	/* clks not needed in SPL stage */
 #ifndef CONFIG_XPL_BUILD
 	clk_dm(IMX8MN_CLK_ENET_REF,
-	       imx8m_clk_composite("enet_ref", imx8mn_enet_ref_sels,
+	       imx8m_clk_composite(dev, "enet_ref", imx8mn_enet_ref_sels,
 	       base + 0xa980));
 	clk_dm(IMX8MN_CLK_ENET_TIMER,
-	       imx8m_clk_composite("enet_timer", imx8mn_enet_timer_sels,
+	       imx8m_clk_composite(dev, "enet_timer", imx8mn_enet_timer_sels,
 	       base + 0xaa00));
 	clk_dm(IMX8MN_CLK_ENET_PHY_REF,
-	       imx8m_clk_composite("enet_phy", imx8mn_enet_phy_sels,
+	       imx8m_clk_composite(dev, "enet_phy", imx8mn_enet_phy_sels,
 	       base + 0xaa80));
 	clk_dm(IMX8MN_CLK_ENET1_ROOT,
-	       imx_clk_gate4("enet1_root_clk", "enet_axi",
+	       imx_clk_gate4(dev, "enet1_root_clk", "enet_axi",
 	       base + 0x40a0, 0));
 	clk_dm(IMX8MN_CLK_PWM1,
-	       imx8m_clk_composite("pwm1", imx8mn_pwm1_sels, base + 0xb380));
+	       imx8m_clk_composite(dev, "pwm1", imx8mn_pwm1_sels, base + 0xb380));
 	clk_dm(IMX8MN_CLK_PWM2,
-	       imx8m_clk_composite("pwm2", imx8mn_pwm2_sels, base + 0xb400));
+	       imx8m_clk_composite(dev, "pwm2", imx8mn_pwm2_sels, base + 0xb400));
 	clk_dm(IMX8MN_CLK_PWM3,
-	       imx8m_clk_composite("pwm3", imx8mn_pwm3_sels, base + 0xb480));
+	       imx8m_clk_composite(dev, "pwm3", imx8mn_pwm3_sels, base + 0xb480));
 	clk_dm(IMX8MN_CLK_PWM4,
-	       imx8m_clk_composite("pwm4", imx8mn_pwm4_sels, base + 0xb500));
+	       imx8m_clk_composite(dev, "pwm4", imx8mn_pwm4_sels, base + 0xb500));
 	clk_dm(IMX8MN_CLK_PWM1_ROOT,
-	       imx_clk_gate4("pwm1_root_clk", "pwm1", base + 0x4280, 0));
+	       imx_clk_gate4(dev, "pwm1_root_clk", "pwm1", base + 0x4280, 0));
 	clk_dm(IMX8MN_CLK_PWM2_ROOT,
-	       imx_clk_gate4("pwm2_root_clk", "pwm2", base + 0x4290, 0));
+	       imx_clk_gate4(dev, "pwm2_root_clk", "pwm2", base + 0x4290, 0));
 	clk_dm(IMX8MN_CLK_PWM3_ROOT,
-	       imx_clk_gate4("pwm3_root_clk", "pwm3", base + 0x42a0, 0));
+	       imx_clk_gate4(dev, "pwm3_root_clk", "pwm3", base + 0x42a0, 0));
 	clk_dm(IMX8MN_CLK_PWM4_ROOT,
-	       imx_clk_gate4("pwm4_root_clk", "pwm4", base + 0x42b0, 0));
+	       imx_clk_gate4(dev, "pwm4_root_clk", "pwm4", base + 0x42b0, 0));
 #endif
 
 #if CONFIG_IS_ENABLED(DM_SPI)
 	clk_dm(IMX8MN_CLK_ECSPI1,
-	       imx8m_clk_composite("ecspi1", imx8mn_ecspi1_sels, base + 0xb280));
+	       imx8m_clk_composite(dev, "ecspi1", imx8mn_ecspi1_sels, base + 0xb280));
 	clk_dm(IMX8MN_CLK_ECSPI2,
-	       imx8m_clk_composite("ecspi2", imx8mn_ecspi2_sels, base + 0xb300));
+	       imx8m_clk_composite(dev, "ecspi2", imx8mn_ecspi2_sels, base + 0xb300));
 	clk_dm(IMX8MN_CLK_ECSPI3,
-	       imx8m_clk_composite("ecspi3", imx8mn_ecspi3_sels, base + 0xc180));
+	       imx8m_clk_composite(dev, "ecspi3", imx8mn_ecspi3_sels, base + 0xc180));
 	clk_dm(IMX8MN_CLK_ECSPI1_ROOT,
-	       imx_clk_gate4("ecspi1_root_clk", "ecspi1", base + 0x4070, 0));
+	       imx_clk_gate4(dev, "ecspi1_root_clk", "ecspi1", base + 0x4070, 0));
 	clk_dm(IMX8MN_CLK_ECSPI2_ROOT,
-	       imx_clk_gate4("ecspi2_root_clk", "ecspi2", base + 0x4080, 0));
+	       imx_clk_gate4(dev, "ecspi2_root_clk", "ecspi2", base + 0x4080, 0));
 	clk_dm(IMX8MN_CLK_ECSPI3_ROOT,
-	       imx_clk_gate4("ecspi3_root_clk", "ecspi3", base + 0x4090, 0));
+	       imx_clk_gate4(dev, "ecspi3_root_clk", "ecspi3", base + 0x4090, 0));
 #endif
 
 	clk_dm(IMX8MN_CLK_ARM,
-	       imx_clk_mux2_flags("arm_core", base + 0x9880, 24, 1,
+	       imx_clk_mux2_flags(dev, "arm_core", base + 0x9880, 24, 1,
 				  imx8mn_arm_core_sels,
 				  ARRAY_SIZE(imx8mn_arm_core_sels),
 				  CLK_IS_CRITICAL));
diff --git a/drivers/clk/imx/clk-imx8mp.c b/drivers/clk/imx/clk-imx8mp.c
index 1d04090ca00..bad579f8d5e 100644
--- a/drivers/clk/imx/clk-imx8mp.c
+++ b/drivers/clk/imx/clk-imx8mp.c
@@ -14,7 +14,7 @@
 
 #include "clk.h"
 
-static const char * const pll_ref_sels[] = { "clock-osc-24m", "dummy", "dummy", "dummy", };
+static const char * const pll_ref_sels[] = { "osc_24m", "dummy", "dummy", "dummy", };
 static const char * const dram_pll_bypass_sels[] = {"dram_pll", "dram_pll_ref_sel", };
 static const char * const arm_pll_bypass_sels[] = {"arm_pll", "arm_pll_ref_sel", };
 static const char * const sys_pll1_bypass_sels[] = {"sys_pll1", "sys_pll1_ref_sel", };
@@ -23,167 +23,167 @@ static const char * const sys_pll3_bypass_sels[] = {"sys_pll3", "sys_pll3_ref_se
 
 static const char * const imx8mp_arm_core_sels[] = {"arm_a53_src", "arm_pll_out", };
 
-static const char * const imx8mp_a53_sels[] = {"clock-osc-24m", "arm_pll_out", "sys_pll2_500m",
+static const char * const imx8mp_a53_sels[] = {"osc_24m", "arm_pll_out", "sys_pll2_500m",
 					       "sys_pll2_1000m", "sys_pll1_800m", "sys_pll1_400m",
 					       "audio_pll1_out", "sys_pll3_out", };
 
-static const char * const imx8mp_hsio_axi_sels[] = {"clock-osc-24m", "sys_pll2_500m", "sys_pll1_800m",
+static const char * const imx8mp_hsio_axi_sels[] = {"osc_24m", "sys_pll2_500m", "sys_pll1_800m",
 						    "sys_pll2_100m", "sys_pll2_200m", "clk_ext2",
 						    "clk_ext4", "audio_pll2_out", };
 
-static const char * const imx8mp_main_axi_sels[] = {"clock-osc-24m", "sys_pll2_333m", "sys_pll1_800m",
+static const char * const imx8mp_main_axi_sels[] = {"osc_24m", "sys_pll2_333m", "sys_pll1_800m",
 						    "sys_pll2_250m", "sys_pll2_1000m", "audio_pll1_out",
 						    "video_pll1_out", "sys_pll1_100m",};
 
-static const char * const imx8mp_enet_axi_sels[] = {"clock-osc-24m", "sys_pll1_266m", "sys_pll1_800m",
+static const char * const imx8mp_enet_axi_sels[] = {"osc_24m", "sys_pll1_266m", "sys_pll1_800m",
 						    "sys_pll2_250m", "sys_pll2_200m", "audio_pll1_out",
 						    "video_pll1_out", "sys_pll3_out", };
 
-static const char * const imx8mp_nand_usdhc_sels[] = {"clock-osc-24m", "sys_pll1_266m", "sys_pll1_800m",
+static const char * const imx8mp_nand_usdhc_sels[] = {"osc_24m", "sys_pll1_266m", "sys_pll1_800m",
 						      "sys_pll2_200m", "sys_pll1_133m", "sys_pll3_out",
 						      "sys_pll2_250m", "audio_pll1_out", };
 
-static const char * const imx8mp_noc_sels[] = {"clock-osc-24m", "sys_pll1_800m", "sys_pll3_out",
+static const char * const imx8mp_noc_sels[] = {"osc_24m", "sys_pll1_800m", "sys_pll3_out",
 					       "sys_pll2_1000m", "sys_pll2_500m", "audio_pll1_out",
 					       "video_pll1_out", "audio_pll2_out", };
 
-static const char * const imx8mp_noc_io_sels[] = {"clock-osc-24m", "sys_pll1_800m", "sys_pll3_out",
+static const char * const imx8mp_noc_io_sels[] = {"osc_24m", "sys_pll1_800m", "sys_pll3_out",
 						  "sys_pll2_1000m", "sys_pll2_500m", "audio_pll1_out",
 						  "video_pll1_out", "audio_pll2_out", };
 
-static const char * const imx8mp_ahb_sels[] = {"clock-osc-24m", "sys_pll1_133m", "sys_pll1_800m",
+static const char * const imx8mp_ahb_sels[] = {"osc_24m", "sys_pll1_133m", "sys_pll1_800m",
 					       "sys_pll1_400m", "sys_pll2_125m", "sys_pll3_out",
 					       "audio_pll1_out", "video_pll1_out", };
 
-static const char * const imx8mp_dram_alt_sels[] = {"clock-osc-24m", "sys_pll1_800m", "sys_pll1_100m",
+static const char * const imx8mp_dram_alt_sels[] = {"osc_24m", "sys_pll1_800m", "sys_pll1_100m",
 						    "sys_pll2_500m", "sys_pll2_1000m", "sys_pll3_out",
 						    "audio_pll1_out", "sys_pll1_266m", };
 
-static const char * const imx8mp_dram_apb_sels[] = {"clock-osc-24m", "sys_pll2_200m", "sys_pll1_40m",
+static const char * const imx8mp_dram_apb_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1_40m",
 						    "sys_pll1_160m", "sys_pll1_800m", "sys_pll3_out",
 						    "sys_pll2_250m", "audio_pll2_out", };
 
-static const char * const imx8mp_pcie_aux_sels[] = {"clock-osc-24m", "sys_pll2_200m", "sys_pll2_50m",
+static const char * const imx8mp_pcie_aux_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll2_50m",
 						    "sys_pll3_out", "sys_pll2_100m", "sys_pll1_80m",
 						    "sys_pll1_160m", "sys_pll1_200m", };
 
-static const char * const imx8mp_i2c5_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m",
+static const char * const imx8mp_i2c5_sels[] = {"osc_24m", "sys_pll1_160m", "sys_pll2_50m",
 						"sys_pll3_out", "audio_pll1_out", "video_pll1_out",
 						"audio_pll2_out", "sys_pll1_133m", };
 
-static const char * const imx8mp_i2c6_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m",
+static const char * const imx8mp_i2c6_sels[] = {"osc_24m", "sys_pll1_160m", "sys_pll2_50m",
 						"sys_pll3_out", "audio_pll1_out", "video_pll1_out",
 						"audio_pll2_out", "sys_pll1_133m", };
 
-static const char * const imx8mp_enet_qos_sels[] = {"clock-osc-24m", "sys_pll2_125m", "sys_pll2_50m",
+static const char * const imx8mp_enet_qos_sels[] = {"osc_24m", "sys_pll2_125m", "sys_pll2_50m",
 						    "sys_pll2_100m", "sys_pll1_160m", "audio_pll1_out",
 						    "video_pll1_out", "clk_ext4", };
 
-static const char * const imx8mp_enet_qos_timer_sels[] = {"clock-osc-24m", "sys_pll2_100m", "audio_pll1_out",
+static const char * const imx8mp_enet_qos_timer_sels[] = {"osc_24m", "sys_pll2_100m", "audio_pll1_out",
 							  "clk_ext1", "clk_ext2", "clk_ext3",
 							  "clk_ext4", "video_pll1_out", };
 
-static const char * const imx8mp_usdhc1_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sys_pll1_800m",
+static const char * const imx8mp_usdhc1_sels[] = {"osc_24m", "sys_pll1_400m", "sys_pll1_800m",
 						  "sys_pll2_500m", "sys_pll3_out", "sys_pll1_266m",
 						  "audio_pll2_out", "sys_pll1_100m", };
 
-static const char * const imx8mp_usdhc2_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sys_pll1_800m",
+static const char * const imx8mp_usdhc2_sels[] = {"osc_24m", "sys_pll1_400m", "sys_pll1_800m",
 						  "sys_pll2_500m", "sys_pll3_out", "sys_pll1_266m",
 						  "audio_pll2_out", "sys_pll1_100m", };
 
-static const char * const imx8mp_i2c1_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m",
+static const char * const imx8mp_i2c1_sels[] = {"osc_24m", "sys_pll1_160m", "sys_pll2_50m",
 						"sys_pll3_out", "audio_pll1_out", "video_pll1_out",
 						"audio_pll2_out", "sys_pll1_133m", };
 
-static const char * const imx8mp_i2c2_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m",
+static const char * const imx8mp_i2c2_sels[] = {"osc_24m", "sys_pll1_160m", "sys_pll2_50m",
 						"sys_pll3_out", "audio_pll1_out", "video_pll1_out",
 						"audio_pll2_out", "sys_pll1_133m", };
 
-static const char * const imx8mp_i2c3_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m",
+static const char * const imx8mp_i2c3_sels[] = {"osc_24m", "sys_pll1_160m", "sys_pll2_50m",
 						"sys_pll3_out", "audio_pll1_out", "video_pll1_out",
 						"audio_pll2_out", "sys_pll1_133m", };
 
-static const char * const imx8mp_i2c4_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m",
+static const char * const imx8mp_i2c4_sels[] = {"osc_24m", "sys_pll1_160m", "sys_pll2_50m",
 						"sys_pll3_out", "audio_pll1_out", "video_pll1_out",
 						"audio_pll2_out", "sys_pll1_133m", };
 
-static const char * const imx8mp_uart1_sels[] = {"clock-osc-24m", "sys_pll1_80m", "sys_pll2_200m",
+static const char * const imx8mp_uart1_sels[] = {"osc_24m", "sys_pll1_80m", "sys_pll2_200m",
 						 "sys_pll2_100m", "sys_pll3_out", "clk_ext2",
 						 "clk_ext4", "audio_pll2_out", };
 
-static const char * const imx8mp_uart2_sels[] = {"clock-osc-24m", "sys_pll1_80m", "sys_pll2_200m",
+static const char * const imx8mp_uart2_sels[] = {"osc_24m", "sys_pll1_80m", "sys_pll2_200m",
 						 "sys_pll2_100m", "sys_pll3_out", "clk_ext2",
 						 "clk_ext3", "audio_pll2_out", };
 
-static const char * const imx8mp_uart3_sels[] = {"clock-osc-24m", "sys_pll1_80m", "sys_pll2_200m",
+static const char * const imx8mp_uart3_sels[] = {"osc_24m", "sys_pll1_80m", "sys_pll2_200m",
 						 "sys_pll2_100m", "sys_pll3_out", "clk_ext2",
 						 "clk_ext4", "audio_pll2_out", };
 
-static const char * const imx8mp_uart4_sels[] = {"clock-osc-24m", "sys_pll1_80m", "sys_pll2_200m",
+static const char * const imx8mp_uart4_sels[] = {"osc_24m", "sys_pll1_80m", "sys_pll2_200m",
 						 "sys_pll2_100m", "sys_pll3_out", "clk_ext2",
 						 "clk_ext3", "audio_pll2_out", };
 
-static const char * const imx8mp_usb_core_ref_sels[] = {"clock-osc-24m", "sys_pll1_100m", "sys_pll1_40m",
+static const char * const imx8mp_usb_core_ref_sels[] = {"osc_24m", "sys_pll1_100m", "sys_pll1_40m",
 							"sys_pll2_100m", "sys_pll2_200m", "clk_ext2",
 							"clk_ext3", "audio_pll2_out", };
 
-static const char * const imx8mp_usb_phy_ref_sels[] = {"clock-osc-24m", "sys_pll1_100m", "sys_pll1_40m",
+static const char * const imx8mp_usb_phy_ref_sels[] = {"osc_24m", "sys_pll1_100m", "sys_pll1_40m",
 						       "sys_pll2_100m", "sys_pll2_200m", "clk_ext2",
 						       "clk_ext3", "audio_pll2_out", };
 
-static const char * const imx8mp_gic_sels[] = {"clock-osc-24m", "sys_pll2_200m", "sys_pll1_40m",
+static const char * const imx8mp_gic_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1_40m",
 					       "sys_pll2_100m", "sys_pll1_800m",
 					       "sys_pll2_500m", "clk_ext4", "audio_pll2_out" };
 
-static const char * const imx8mp_pwm1_sels[] = {"clock-osc-24m", "sys_pll2_100m", "sys_pll1_160m",
+static const char * const imx8mp_pwm1_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_160m",
 						"sys_pll1_40m", "sys_pll3_out", "clk_ext1",
 						"sys_pll1_80m", "video_pll1_out", };
 
-static const char * const imx8mp_pwm2_sels[] = {"clock-osc-24m", "sys_pll2_100m", "sys_pll1_160m",
+static const char * const imx8mp_pwm2_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_160m",
 						"sys_pll1_40m", "sys_pll3_out", "clk_ext1",
 						"sys_pll1_80m", "video_pll1_out", };
 
-static const char * const imx8mp_pwm3_sels[] = {"clock-osc-24m", "sys_pll2_100m", "sys_pll1_160m",
+static const char * const imx8mp_pwm3_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_160m",
 						"sys_pll1_40m", "sys_pll3_out", "clk_ext2",
 						"sys_pll1_80m", "video_pll1_out", };
 
-static const char * const imx8mp_pwm4_sels[] = {"clock-osc-24m", "sys_pll2_100m", "sys_pll1_160m",
+static const char * const imx8mp_pwm4_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_160m",
 						"sys_pll1_40m", "sys_pll3_out", "clk_ext2",
 						"sys_pll1_80m", "video_pll1_out", };
 
-static const char * const imx8mp_ecspi1_sels[] = {"clock-osc-24m", "sys_pll2_200m", "sys_pll1_40m",
+static const char * const imx8mp_ecspi1_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1_40m",
 						  "sys_pll1_160m", "sys_pll1_800m", "sys_pll3_out",
 						  "sys_pll2_250m", "audio_pll2_out", };
 
-static const char * const imx8mp_ecspi2_sels[] = {"clock-osc-24m", "sys_pll2_200m", "sys_pll1_40m",
+static const char * const imx8mp_ecspi2_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1_40m",
 						  "sys_pll1_160m", "sys_pll1_800m", "sys_pll3_out",
 						  "sys_pll2_250m", "audio_pll2_out", };
 
-static const char * const imx8mp_ecspi3_sels[] = {"clock-osc-24m", "sys_pll2_200m", "sys_pll1_40m",
+static const char * const imx8mp_ecspi3_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1_40m",
 						  "sys_pll1_160m", "sys_pll1_800m", "sys_pll3_out",
 						  "sys_pll2_250m", "audio_pll2_out", };
 
-static const char * const imx8mp_wdog_sels[] = {"clock-osc-24m", "sys_pll1_133m", "sys_pll1_160m",
+static const char * const imx8mp_wdog_sels[] = {"osc_24m", "sys_pll1_133m", "sys_pll1_160m",
 						"vpu_pll_out", "sys_pll2_125m", "sys_pll3_out",
 						"sys_pll1_80m", "sys_pll2_166m" };
 
-static const char * const imx8mp_qspi_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sys_pll2_333m",
+static const char * const imx8mp_qspi_sels[] = {"osc_24m", "sys_pll1_400m", "sys_pll2_333m",
 						"sys_pll2_500m", "audio_pll2_out", "sys_pll1_266m",
 						"sys_pll3_out", "sys_pll1_100m", };
 
-static const char * const imx8mp_usdhc3_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sys_pll1_800m",
+static const char * const imx8mp_usdhc3_sels[] = {"osc_24m", "sys_pll1_400m", "sys_pll1_800m",
 						  "sys_pll2_500m", "sys_pll3_out", "sys_pll1_266m",
 						  "audio_pll2_out", "sys_pll1_100m", };
 
-static const char * const imx8mp_enet_ref_sels[] = {"clock-osc-24m", "sys_pll2_125m", "sys_pll2_50m",
+static const char * const imx8mp_enet_ref_sels[] = {"osc_24m", "sys_pll2_125m", "sys_pll2_50m",
 						    "sys_pll2_100m", "sys_pll1_160m", "audio_pll1_out",
 						    "video_pll1_out", "clk_ext4", };
 
-static const char * const imx8mp_enet_timer_sels[] = {"clock-osc-24m", "sys_pll2_100m", "audio_pll1_out",
+static const char * const imx8mp_enet_timer_sels[] = {"osc_24m", "sys_pll2_100m", "audio_pll1_out",
 						      "clk_ext1", "clk_ext2", "clk_ext3",
 						      "clk_ext4", "video_pll1_out", };
 
-static const char * const imx8mp_enet_phy_ref_sels[] = {"clock-osc-24m", "sys_pll2_50m", "sys_pll2_125m",
+static const char * const imx8mp_enet_phy_ref_sels[] = {"osc_24m", "sys_pll2_50m", "sys_pll2_125m",
 							"sys_pll2_200m", "sys_pll2_500m", "audio_pll1_out",
 							"video_pll1_out", "audio_pll2_out", };
 
@@ -199,11 +199,11 @@ static int imx8mp_clk_probe(struct udevice *dev)
 
 	clk_dm(IMX8MP_CLK_DUMMY, clk_register_fixed_rate(NULL, "dummy", 0));
 
-	clk_dm(IMX8MP_DRAM_PLL_REF_SEL, imx_clk_mux("dram_pll_ref_sel", base + 0x50, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
-	clk_dm(IMX8MP_ARM_PLL_REF_SEL, imx_clk_mux("arm_pll_ref_sel", base + 0x84, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
-	clk_dm(IMX8MP_SYS_PLL1_REF_SEL, imx_clk_mux("sys_pll1_ref_sel", base + 0x94, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
-	clk_dm(IMX8MP_SYS_PLL2_REF_SEL, imx_clk_mux("sys_pll2_ref_sel", base + 0x104, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
-	clk_dm(IMX8MP_SYS_PLL3_REF_SEL, imx_clk_mux("sys_pll3_ref_sel", base + 0x114, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
+	clk_dm(IMX8MP_DRAM_PLL_REF_SEL, imx_clk_mux(dev, "dram_pll_ref_sel", base + 0x50, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
+	clk_dm(IMX8MP_ARM_PLL_REF_SEL, imx_clk_mux(dev, "arm_pll_ref_sel", base + 0x84, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
+	clk_dm(IMX8MP_SYS_PLL1_REF_SEL, imx_clk_mux(dev, "sys_pll1_ref_sel", base + 0x94, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
+	clk_dm(IMX8MP_SYS_PLL2_REF_SEL, imx_clk_mux(dev, "sys_pll2_ref_sel", base + 0x104, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
+	clk_dm(IMX8MP_SYS_PLL3_REF_SEL, imx_clk_mux(dev, "sys_pll3_ref_sel", base + 0x114, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
 
 	clk_dm(IMX8MP_DRAM_PLL, imx_clk_pll14xx("dram_pll", "dram_pll_ref_sel", base + 0x50,
 						&imx_1443x_dram_pll));
@@ -216,37 +216,37 @@ static int imx8mp_clk_probe(struct udevice *dev)
 	clk_dm(IMX8MP_SYS_PLL3, imx_clk_pll14xx("sys_pll3", "sys_pll3_ref_sel", base + 0x114,
 						&imx_1416x_pll));
 
-	clk_dm(IMX8MP_DRAM_PLL_BYPASS, imx_clk_mux_flags("dram_pll_bypass", base + 0x50, 4, 1, dram_pll_bypass_sels, ARRAY_SIZE(dram_pll_bypass_sels), CLK_SET_RATE_PARENT));
-	clk_dm(IMX8MP_ARM_PLL_BYPASS, imx_clk_mux_flags("arm_pll_bypass", base + 0x84, 4, 1, arm_pll_bypass_sels, ARRAY_SIZE(arm_pll_bypass_sels), CLK_SET_RATE_PARENT));
-	clk_dm(IMX8MP_SYS_PLL1_BYPASS, imx_clk_mux_flags("sys_pll1_bypass", base + 0x94, 4, 1, sys_pll1_bypass_sels, ARRAY_SIZE(sys_pll1_bypass_sels), CLK_SET_RATE_PARENT));
-	clk_dm(IMX8MP_SYS_PLL2_BYPASS, imx_clk_mux_flags("sys_pll2_bypass", base + 0x104, 4, 1, sys_pll2_bypass_sels, ARRAY_SIZE(sys_pll2_bypass_sels), CLK_SET_RATE_PARENT));
-	clk_dm(IMX8MP_SYS_PLL3_BYPASS, imx_clk_mux_flags("sys_pll3_bypass", base + 0x114, 4, 1, sys_pll3_bypass_sels, ARRAY_SIZE(sys_pll3_bypass_sels), CLK_SET_RATE_PARENT));
-
-	clk_dm(IMX8MP_DRAM_PLL_OUT, imx_clk_gate("dram_pll_out", "dram_pll_bypass", base + 0x50, 13));
-	clk_dm(IMX8MP_ARM_PLL_OUT, imx_clk_gate("arm_pll_out", "arm_pll_bypass", base + 0x84, 11));
-	clk_dm(IMX8MP_SYS_PLL1_OUT, imx_clk_gate("sys_pll1_out", "sys_pll1_bypass", base + 0x94, 11));
-	clk_dm(IMX8MP_SYS_PLL2_OUT, imx_clk_gate("sys_pll2_out", "sys_pll2_bypass", base + 0x104, 11));
-	clk_dm(IMX8MP_SYS_PLL3_OUT, imx_clk_gate("sys_pll3_out", "sys_pll3_bypass", base + 0x114, 11));
-
-	clk_dm(IMX8MP_SYS_PLL1_40M, imx_clk_fixed_factor("sys_pll1_40m", "sys_pll1_out", 1, 20));
-	clk_dm(IMX8MP_SYS_PLL1_80M, imx_clk_fixed_factor("sys_pll1_80m", "sys_pll1_out", 1, 10));
-	clk_dm(IMX8MP_SYS_PLL1_100M, imx_clk_fixed_factor("sys_pll1_100m", "sys_pll1_out", 1, 8));
-	clk_dm(IMX8MP_SYS_PLL1_133M, imx_clk_fixed_factor("sys_pll1_133m", "sys_pll1_out", 1, 6));
-	clk_dm(IMX8MP_SYS_PLL1_160M, imx_clk_fixed_factor("sys_pll1_160m", "sys_pll1_out", 1, 5));
-	clk_dm(IMX8MP_SYS_PLL1_200M, imx_clk_fixed_factor("sys_pll1_200m", "sys_pll1_out", 1, 4));
-	clk_dm(IMX8MP_SYS_PLL1_266M, imx_clk_fixed_factor("sys_pll1_266m", "sys_pll1_out", 1, 3));
-	clk_dm(IMX8MP_SYS_PLL1_400M, imx_clk_fixed_factor("sys_pll1_400m", "sys_pll1_out", 1, 2));
-	clk_dm(IMX8MP_SYS_PLL1_800M, imx_clk_fixed_factor("sys_pll1_800m", "sys_pll1_out", 1, 1));
-
-	clk_dm(IMX8MP_SYS_PLL2_50M, imx_clk_fixed_factor("sys_pll2_50m", "sys_pll2_out", 1, 20));
-	clk_dm(IMX8MP_SYS_PLL2_100M, imx_clk_fixed_factor("sys_pll2_100m", "sys_pll2_out", 1, 10));
-	clk_dm(IMX8MP_SYS_PLL2_125M, imx_clk_fixed_factor("sys_pll2_125m", "sys_pll2_out", 1, 8));
-	clk_dm(IMX8MP_SYS_PLL2_166M, imx_clk_fixed_factor("sys_pll2_166m", "sys_pll2_out", 1, 6));
-	clk_dm(IMX8MP_SYS_PLL2_200M, imx_clk_fixed_factor("sys_pll2_200m", "sys_pll2_out", 1, 5));
-	clk_dm(IMX8MP_SYS_PLL2_250M, imx_clk_fixed_factor("sys_pll2_250m", "sys_pll2_out", 1, 4));
-	clk_dm(IMX8MP_SYS_PLL2_333M, imx_clk_fixed_factor("sys_pll2_333m", "sys_pll2_out", 1, 3));
-	clk_dm(IMX8MP_SYS_PLL2_500M, imx_clk_fixed_factor("sys_pll2_500m", "sys_pll2_out", 1, 2));
-	clk_dm(IMX8MP_SYS_PLL2_1000M, imx_clk_fixed_factor("sys_pll2_1000m", "sys_pll2_out", 1, 1));
+	clk_dm(IMX8MP_DRAM_PLL_BYPASS, imx_clk_mux_flags(dev, "dram_pll_bypass", base + 0x50, 4, 1, dram_pll_bypass_sels, ARRAY_SIZE(dram_pll_bypass_sels), CLK_SET_RATE_PARENT));
+	clk_dm(IMX8MP_ARM_PLL_BYPASS, imx_clk_mux_flags(dev, "arm_pll_bypass", base + 0x84, 4, 1, arm_pll_bypass_sels, ARRAY_SIZE(arm_pll_bypass_sels), CLK_SET_RATE_PARENT));
+	clk_dm(IMX8MP_SYS_PLL1_BYPASS, imx_clk_mux_flags(dev, "sys_pll1_bypass", base + 0x94, 4, 1, sys_pll1_bypass_sels, ARRAY_SIZE(sys_pll1_bypass_sels), CLK_SET_RATE_PARENT));
+	clk_dm(IMX8MP_SYS_PLL2_BYPASS, imx_clk_mux_flags(dev, "sys_pll2_bypass", base + 0x104, 4, 1, sys_pll2_bypass_sels, ARRAY_SIZE(sys_pll2_bypass_sels), CLK_SET_RATE_PARENT));
+	clk_dm(IMX8MP_SYS_PLL3_BYPASS, imx_clk_mux_flags(dev, "sys_pll3_bypass", base + 0x114, 4, 1, sys_pll3_bypass_sels, ARRAY_SIZE(sys_pll3_bypass_sels), CLK_SET_RATE_PARENT));
+
+	clk_dm(IMX8MP_DRAM_PLL_OUT, imx_clk_gate(dev, "dram_pll_out", "dram_pll_bypass", base + 0x50, 13));
+	clk_dm(IMX8MP_ARM_PLL_OUT, imx_clk_gate(dev, "arm_pll_out", "arm_pll_bypass", base + 0x84, 11));
+	clk_dm(IMX8MP_SYS_PLL1_OUT, imx_clk_gate(dev, "sys_pll1_out", "sys_pll1_bypass", base + 0x94, 11));
+	clk_dm(IMX8MP_SYS_PLL2_OUT, imx_clk_gate(dev, "sys_pll2_out", "sys_pll2_bypass", base + 0x104, 11));
+	clk_dm(IMX8MP_SYS_PLL3_OUT, imx_clk_gate(dev, "sys_pll3_out", "sys_pll3_bypass", base + 0x114, 11));
+
+	clk_dm(IMX8MP_SYS_PLL1_40M, imx_clk_fixed_factor(dev, "sys_pll1_40m", "sys_pll1_out", 1, 20));
+	clk_dm(IMX8MP_SYS_PLL1_80M, imx_clk_fixed_factor(dev, "sys_pll1_80m", "sys_pll1_out", 1, 10));
+	clk_dm(IMX8MP_SYS_PLL1_100M, imx_clk_fixed_factor(dev, "sys_pll1_100m", "sys_pll1_out", 1, 8));
+	clk_dm(IMX8MP_SYS_PLL1_133M, imx_clk_fixed_factor(dev, "sys_pll1_133m", "sys_pll1_out", 1, 6));
+	clk_dm(IMX8MP_SYS_PLL1_160M, imx_clk_fixed_factor(dev, "sys_pll1_160m", "sys_pll1_out", 1, 5));
+	clk_dm(IMX8MP_SYS_PLL1_200M, imx_clk_fixed_factor(dev, "sys_pll1_200m", "sys_pll1_out", 1, 4));
+	clk_dm(IMX8MP_SYS_PLL1_266M, imx_clk_fixed_factor(dev, "sys_pll1_266m", "sys_pll1_out", 1, 3));
+	clk_dm(IMX8MP_SYS_PLL1_400M, imx_clk_fixed_factor(dev, "sys_pll1_400m", "sys_pll1_out", 1, 2));
+	clk_dm(IMX8MP_SYS_PLL1_800M, imx_clk_fixed_factor(dev, "sys_pll1_800m", "sys_pll1_out", 1, 1));
+
+	clk_dm(IMX8MP_SYS_PLL2_50M, imx_clk_fixed_factor(dev, "sys_pll2_50m", "sys_pll2_out", 1, 20));
+	clk_dm(IMX8MP_SYS_PLL2_100M, imx_clk_fixed_factor(dev, "sys_pll2_100m", "sys_pll2_out", 1, 10));
+	clk_dm(IMX8MP_SYS_PLL2_125M, imx_clk_fixed_factor(dev, "sys_pll2_125m", "sys_pll2_out", 1, 8));
+	clk_dm(IMX8MP_SYS_PLL2_166M, imx_clk_fixed_factor(dev, "sys_pll2_166m", "sys_pll2_out", 1, 6));
+	clk_dm(IMX8MP_SYS_PLL2_200M, imx_clk_fixed_factor(dev, "sys_pll2_200m", "sys_pll2_out", 1, 5));
+	clk_dm(IMX8MP_SYS_PLL2_250M, imx_clk_fixed_factor(dev, "sys_pll2_250m", "sys_pll2_out", 1, 4));
+	clk_dm(IMX8MP_SYS_PLL2_333M, imx_clk_fixed_factor(dev, "sys_pll2_333m", "sys_pll2_out", 1, 3));
+	clk_dm(IMX8MP_SYS_PLL2_500M, imx_clk_fixed_factor(dev, "sys_pll2_500m", "sys_pll2_out", 1, 2));
+	clk_dm(IMX8MP_SYS_PLL2_1000M, imx_clk_fixed_factor(dev, "sys_pll2_1000m", "sys_pll2_out", 1, 1));
 
 	ret = clk_get_by_name(dev, "osc_24m", &osc_24m_clk);
 	if (ret)
@@ -262,104 +262,104 @@ static int imx8mp_clk_probe(struct udevice *dev)
 	if (!base)
 		return -EINVAL;
 
-	clk_dm(IMX8MP_CLK_A53_SRC, imx_clk_mux2("arm_a53_src", base + 0x8000, 24, 3, imx8mp_a53_sels, ARRAY_SIZE(imx8mp_a53_sels)));
-	clk_dm(IMX8MP_CLK_A53_CG, imx_clk_gate3("arm_a53_cg", "arm_a53_src", base + 0x8000, 28));
-	clk_dm(IMX8MP_CLK_A53_DIV, imx_clk_divider2("arm_a53_div", "arm_a53_cg", base + 0x8000, 0, 3));
-
-	clk_dm(IMX8MP_CLK_HSIO_AXI, imx8m_clk_composite("hsio_axi", imx8mp_hsio_axi_sels, base + 0x8380));
-	clk_dm(IMX8MP_CLK_MAIN_AXI, imx8m_clk_composite_critical("main_axi", imx8mp_main_axi_sels, base + 0x8800));
-	clk_dm(IMX8MP_CLK_ENET_AXI, imx8m_clk_composite_critical("enet_axi", imx8mp_enet_axi_sels, base + 0x8880));
-	clk_dm(IMX8MP_CLK_NAND_USDHC_BUS, imx8m_clk_composite_critical("nand_usdhc_bus", imx8mp_nand_usdhc_sels, base + 0x8900));
-	clk_dm(IMX8MP_CLK_NOC, imx8m_clk_composite_critical("noc", imx8mp_noc_sels, base + 0x8d00));
-	clk_dm(IMX8MP_CLK_NOC_IO, imx8m_clk_composite_critical("noc_io", imx8mp_noc_io_sels, base + 0x8d80));
-
-	clk_dm(IMX8MP_CLK_AHB, imx8m_clk_composite_critical("ahb_root", imx8mp_ahb_sels, base + 0x9000));
-
-	clk_dm(IMX8MP_CLK_IPG_ROOT, imx_clk_divider2("ipg_root", "ahb_root", base + 0x9080, 0, 1));
-
-	clk_dm(IMX8MP_CLK_DRAM_ALT, imx8m_clk_composite("dram_alt", imx8mp_dram_alt_sels, base + 0xa000));
-	clk_dm(IMX8MP_CLK_DRAM_APB, imx8m_clk_composite_critical("dram_apb", imx8mp_dram_apb_sels, base + 0xa080));
-	clk_dm(IMX8MP_CLK_PCIE_AUX, imx8m_clk_composite("pcie_aux", imx8mp_pcie_aux_sels, base + 0xa400));
-	clk_dm(IMX8MP_CLK_I2C5, imx8m_clk_composite("i2c5", imx8mp_i2c5_sels, base + 0xa480));
-	clk_dm(IMX8MP_CLK_I2C6, imx8m_clk_composite("i2c6", imx8mp_i2c6_sels, base + 0xa500));
-	clk_dm(IMX8MP_CLK_ENET_QOS, imx8m_clk_composite("enet_qos", imx8mp_enet_qos_sels, base + 0xa880));
-	clk_dm(IMX8MP_CLK_ENET_QOS_TIMER, imx8m_clk_composite("enet_qos_timer", imx8mp_enet_qos_timer_sels, base + 0xa900));
-	clk_dm(IMX8MP_CLK_ENET_REF, imx8m_clk_composite("enet_ref", imx8mp_enet_ref_sels, base + 0xa980));
-	clk_dm(IMX8MP_CLK_ENET_TIMER, imx8m_clk_composite("enet_timer", imx8mp_enet_timer_sels, base + 0xaa00));
-	clk_dm(IMX8MP_CLK_ENET_PHY_REF, imx8m_clk_composite("enet_phy_ref", imx8mp_enet_phy_ref_sels, base + 0xaa80));
-	clk_dm(IMX8MP_CLK_QSPI, imx8m_clk_composite("qspi", imx8mp_qspi_sels, base + 0xab80));
-	clk_dm(IMX8MP_CLK_USDHC1, imx8m_clk_composite("usdhc1", imx8mp_usdhc1_sels, base + 0xac00));
-	clk_dm(IMX8MP_CLK_USDHC2, imx8m_clk_composite("usdhc2", imx8mp_usdhc2_sels, base + 0xac80));
-	clk_dm(IMX8MP_CLK_I2C1, imx8m_clk_composite("i2c1", imx8mp_i2c1_sels, base + 0xad00));
-	clk_dm(IMX8MP_CLK_I2C2, imx8m_clk_composite("i2c2", imx8mp_i2c2_sels, base + 0xad80));
-	clk_dm(IMX8MP_CLK_I2C3, imx8m_clk_composite("i2c3", imx8mp_i2c3_sels, base + 0xae00));
-	clk_dm(IMX8MP_CLK_I2C4, imx8m_clk_composite("i2c4", imx8mp_i2c4_sels, base + 0xae80));
-
-	clk_dm(IMX8MP_CLK_UART1, imx8m_clk_composite("uart1", imx8mp_uart1_sels, base + 0xaf00));
-	clk_dm(IMX8MP_CLK_UART2, imx8m_clk_composite("uart2", imx8mp_uart2_sels, base + 0xaf80));
-	clk_dm(IMX8MP_CLK_UART3, imx8m_clk_composite("uart3", imx8mp_uart3_sels, base + 0xb000));
-	clk_dm(IMX8MP_CLK_UART4, imx8m_clk_composite("uart4", imx8mp_uart4_sels, base + 0xb080));
-	clk_dm(IMX8MP_CLK_USB_CORE_REF, imx8m_clk_composite("usb_core_ref", imx8mp_usb_core_ref_sels, base + 0xb100));
-	clk_dm(IMX8MP_CLK_USB_PHY_REF, imx8m_clk_composite("usb_phy_ref", imx8mp_usb_phy_ref_sels, base + 0xb180));
-	clk_dm(IMX8MP_CLK_GIC, imx8m_clk_composite_critical("gic", imx8mp_gic_sels, base + 0xb200));
-	clk_dm(IMX8MP_CLK_ECSPI1, imx8m_clk_composite("ecspi1", imx8mp_ecspi1_sels, base + 0xb280));
-	clk_dm(IMX8MP_CLK_ECSPI2, imx8m_clk_composite("ecspi2", imx8mp_ecspi2_sels, base + 0xb300));
-	clk_dm(IMX8MP_CLK_PWM1, imx8m_clk_composite_critical("pwm1", imx8mp_pwm1_sels, base + 0xb380));
-	clk_dm(IMX8MP_CLK_PWM2, imx8m_clk_composite_critical("pwm2", imx8mp_pwm2_sels, base + 0xb400));
-	clk_dm(IMX8MP_CLK_PWM3, imx8m_clk_composite_critical("pwm3", imx8mp_pwm3_sels, base + 0xb480));
-	clk_dm(IMX8MP_CLK_PWM4, imx8m_clk_composite_critical("pwm4", imx8mp_pwm4_sels, base + 0xb500));
-	clk_dm(IMX8MP_CLK_ECSPI3, imx8m_clk_composite("ecspi3", imx8mp_ecspi3_sels, base + 0xc180));
-
-	clk_dm(IMX8MP_CLK_WDOG, imx8m_clk_composite("wdog", imx8mp_wdog_sels, base + 0xb900));
-	clk_dm(IMX8MP_CLK_USDHC3, imx8m_clk_composite("usdhc3", imx8mp_usdhc3_sels, base + 0xbc80));
-
-	clk_dm(IMX8MP_CLK_DRAM_ALT_ROOT, imx_clk_fixed_factor("dram_alt_root", "dram_alt", 1, 4));
-	clk_dm(IMX8MP_CLK_DRAM_CORE, imx_clk_mux2_flags("dram_core_clk", base + 0x9800, 24, 1, imx8mp_dram_core_sels, ARRAY_SIZE(imx8mp_dram_core_sels), CLK_IS_CRITICAL));
-
-	clk_dm(IMX8MP_CLK_DRAM1_ROOT, imx_clk_gate4_flags("dram1_root_clk", "dram_core_clk", base + 0x4050, 0, CLK_IS_CRITICAL));
-	clk_dm(IMX8MP_CLK_ECSPI1_ROOT, imx_clk_gate4("ecspi1_root_clk", "ecspi1", base + 0x4070, 0));
-	clk_dm(IMX8MP_CLK_ECSPI2_ROOT, imx_clk_gate4("ecspi2_root_clk", "ecspi2", base + 0x4080, 0));
-	clk_dm(IMX8MP_CLK_ECSPI3_ROOT, imx_clk_gate4("ecspi3_root_clk", "ecspi3", base + 0x4090, 0));
-	clk_dm(IMX8MP_CLK_ENET1_ROOT, imx_clk_gate4("enet1_root_clk", "enet_axi", base + 0x40a0, 0));
-	clk_dm(IMX8MP_CLK_GPIO1_ROOT, imx_clk_gate4("gpio1_root_clk", "ipg_root", base + 0x40b0, 0));
-	clk_dm(IMX8MP_CLK_GPIO2_ROOT, imx_clk_gate4("gpio2_root_clk", "ipg_root", base + 0x40c0, 0));
-	clk_dm(IMX8MP_CLK_GPIO3_ROOT, imx_clk_gate4("gpio3_root_clk", "ipg_root", base + 0x40d0, 0));
-	clk_dm(IMX8MP_CLK_GPIO4_ROOT, imx_clk_gate4("gpio4_root_clk", "ipg_root", base + 0x40e0, 0));
-	clk_dm(IMX8MP_CLK_GPIO5_ROOT, imx_clk_gate4("gpio5_root_clk", "ipg_root", base + 0x40f0, 0));
-	clk_dm(IMX8MP_CLK_I2C1_ROOT, imx_clk_gate4("i2c1_root_clk", "i2c1", base + 0x4170, 0));
-	clk_dm(IMX8MP_CLK_I2C2_ROOT, imx_clk_gate4("i2c2_root_clk", "i2c2", base + 0x4180, 0));
-	clk_dm(IMX8MP_CLK_I2C3_ROOT, imx_clk_gate4("i2c3_root_clk", "i2c3", base + 0x4190, 0));
-	clk_dm(IMX8MP_CLK_I2C4_ROOT, imx_clk_gate4("i2c4_root_clk", "i2c4", base + 0x41a0, 0));
-	clk_dm(IMX8MP_CLK_PCIE_ROOT, imx_clk_gate4("pcie_root_clk", "pcie_aux", base + 0x4250, 0));
-	clk_dm(IMX8MP_CLK_PWM1_ROOT, imx_clk_gate4("pwm1_root_clk", "pwm1", base + 0x4280, 0));
-	clk_dm(IMX8MP_CLK_PWM2_ROOT, imx_clk_gate4("pwm2_root_clk", "pwm2", base + 0x4290, 0));
-	clk_dm(IMX8MP_CLK_PWM3_ROOT, imx_clk_gate4("pwm3_root_clk", "pwm3", base + 0x42a0, 0));
-	clk_dm(IMX8MP_CLK_PWM4_ROOT, imx_clk_gate4("pwm4_root_clk", "pwm4", base + 0x42b0, 0));
-	clk_dm(IMX8MP_CLK_QOS_ROOT, imx_clk_gate4("qos_root_clk", "ipg_root", base + 0x42c0, 0));
-	clk_dm(IMX8MP_CLK_QOS_ENET_ROOT, imx_clk_gate4("qos_enet_root_clk", "ipg_root", base + 0x42e0, 0));
-	clk_dm(IMX8MP_CLK_QSPI_ROOT, imx_clk_gate4("qspi_root_clk", "qspi", base + 0x42f0, 0));
-	clk_dm(IMX8MP_CLK_I2C5_ROOT, imx_clk_gate2("i2c5_root_clk", "i2c5", base + 0x4330, 0));
-	clk_dm(IMX8MP_CLK_I2C6_ROOT, imx_clk_gate2("i2c6_root_clk", "i2c6", base + 0x4340, 0));
-	clk_dm(IMX8MP_CLK_SIM_ENET_ROOT, imx_clk_gate4("sim_enet_root_clk", "enet_axi", base + 0x4400, 0));
-	clk_dm(IMX8MP_CLK_ENET_QOS_ROOT, imx_clk_gate4("enet_qos_root_clk", "sim_enet_root_clk", base + 0x43b0, 0));
-	clk_dm(IMX8MP_CLK_UART1_ROOT, imx_clk_gate4("uart1_root_clk", "uart1", base + 0x4490, 0));
-	clk_dm(IMX8MP_CLK_UART2_ROOT, imx_clk_gate4("uart2_root_clk", "uart2", base + 0x44a0, 0));
-	clk_dm(IMX8MP_CLK_UART3_ROOT, imx_clk_gate4("uart3_root_clk", "uart3", base + 0x44b0, 0));
-	clk_dm(IMX8MP_CLK_UART4_ROOT, imx_clk_gate4("uart4_root_clk", "uart4", base + 0x44c0, 0));
-	clk_dm(IMX8MP_CLK_USB_ROOT, imx_clk_gate2("usb_root_clk", "hsio_axi", base + 0x44d0, 0));
-	clk_dm(IMX8MP_CLK_USB_SUSP, imx_clk_gate2("usb_suspend_clk", "clock-osc-24m", base + 0x44d0, 0));
-	clk_dm(IMX8MP_CLK_USB_PHY_ROOT, imx_clk_gate4("usb_phy_root_clk", "usb_phy_ref", base + 0x44f0, 0));
-	clk_dm(IMX8MP_CLK_USDHC1_ROOT, imx_clk_gate4("usdhc1_root_clk", "usdhc1", base + 0x4510, 0));
-	clk_dm(IMX8MP_CLK_USDHC2_ROOT, imx_clk_gate4("usdhc2_root_clk", "usdhc2", base + 0x4520, 0));
-	clk_dm(IMX8MP_CLK_WDOG1_ROOT, imx_clk_gate4("wdog1_root_clk", "wdog", base + 0x4530, 0));
-	clk_dm(IMX8MP_CLK_WDOG2_ROOT, imx_clk_gate4("wdog2_root_clk", "wdog", base + 0x4540, 0));
-	clk_dm(IMX8MP_CLK_WDOG3_ROOT, imx_clk_gate4("wdog3_root_clk", "wdog", base + 0x4550, 0));
-	clk_dm(IMX8MP_CLK_HSIO_ROOT, imx_clk_gate4("hsio_root_clk", "ipg_root", base + 0x45c0, 0));
-
-	clk_dm(IMX8MP_CLK_USDHC3_ROOT, imx_clk_gate4("usdhc3_root_clk", "usdhc3", base + 0x45e0, 0));
+	clk_dm(IMX8MP_CLK_A53_SRC, imx_clk_mux2(dev, "arm_a53_src", base + 0x8000, 24, 3, imx8mp_a53_sels, ARRAY_SIZE(imx8mp_a53_sels)));
+	clk_dm(IMX8MP_CLK_A53_CG, imx_clk_gate3(dev, "arm_a53_cg", "arm_a53_src", base + 0x8000, 28));
+	clk_dm(IMX8MP_CLK_A53_DIV, imx_clk_divider2(dev, "arm_a53_div", "arm_a53_cg", base + 0x8000, 0, 3));
+
+	clk_dm(IMX8MP_CLK_HSIO_AXI, imx8m_clk_composite(dev, "hsio_axi", imx8mp_hsio_axi_sels, base + 0x8380));
+	clk_dm(IMX8MP_CLK_MAIN_AXI, imx8m_clk_composite_critical(dev, "main_axi", imx8mp_main_axi_sels, base + 0x8800));
+	clk_dm(IMX8MP_CLK_ENET_AXI, imx8m_clk_composite_critical(dev, "enet_axi", imx8mp_enet_axi_sels, base + 0x8880));
+	clk_dm(IMX8MP_CLK_NAND_USDHC_BUS, imx8m_clk_composite_critical(dev, "nand_usdhc_bus", imx8mp_nand_usdhc_sels, base + 0x8900));
+	clk_dm(IMX8MP_CLK_NOC, imx8m_clk_composite_critical(dev, "noc", imx8mp_noc_sels, base + 0x8d00));
+	clk_dm(IMX8MP_CLK_NOC_IO, imx8m_clk_composite_critical(dev, "noc_io", imx8mp_noc_io_sels, base + 0x8d80));
+
+	clk_dm(IMX8MP_CLK_AHB, imx8m_clk_composite_critical(dev, "ahb_root", imx8mp_ahb_sels, base + 0x9000));
+
+	clk_dm(IMX8MP_CLK_IPG_ROOT, imx_clk_divider2(dev, "ipg_root", "ahb_root", base + 0x9080, 0, 1));
+
+	clk_dm(IMX8MP_CLK_DRAM_ALT, imx8m_clk_composite(dev, "dram_alt", imx8mp_dram_alt_sels, base + 0xa000));
+	clk_dm(IMX8MP_CLK_DRAM_APB, imx8m_clk_composite_critical(dev, "dram_apb", imx8mp_dram_apb_sels, base + 0xa080));
+	clk_dm(IMX8MP_CLK_PCIE_AUX, imx8m_clk_composite(dev, "pcie_aux", imx8mp_pcie_aux_sels, base + 0xa400));
+	clk_dm(IMX8MP_CLK_I2C5, imx8m_clk_composite(dev, "i2c5", imx8mp_i2c5_sels, base + 0xa480));
+	clk_dm(IMX8MP_CLK_I2C6, imx8m_clk_composite(dev, "i2c6", imx8mp_i2c6_sels, base + 0xa500));
+	clk_dm(IMX8MP_CLK_ENET_QOS, imx8m_clk_composite(dev, "enet_qos", imx8mp_enet_qos_sels, base + 0xa880));
+	clk_dm(IMX8MP_CLK_ENET_QOS_TIMER, imx8m_clk_composite(dev, "enet_qos_timer", imx8mp_enet_qos_timer_sels, base + 0xa900));
+	clk_dm(IMX8MP_CLK_ENET_REF, imx8m_clk_composite(dev, "enet_ref", imx8mp_enet_ref_sels, base + 0xa980));
+	clk_dm(IMX8MP_CLK_ENET_TIMER, imx8m_clk_composite(dev, "enet_timer", imx8mp_enet_timer_sels, base + 0xaa00));
+	clk_dm(IMX8MP_CLK_ENET_PHY_REF, imx8m_clk_composite(dev, "enet_phy_ref", imx8mp_enet_phy_ref_sels, base + 0xaa80));
+	clk_dm(IMX8MP_CLK_QSPI, imx8m_clk_composite(dev, "qspi", imx8mp_qspi_sels, base + 0xab80));
+	clk_dm(IMX8MP_CLK_USDHC1, imx8m_clk_composite(dev, "usdhc1", imx8mp_usdhc1_sels, base + 0xac00));
+	clk_dm(IMX8MP_CLK_USDHC2, imx8m_clk_composite(dev, "usdhc2", imx8mp_usdhc2_sels, base + 0xac80));
+	clk_dm(IMX8MP_CLK_I2C1, imx8m_clk_composite(dev, "i2c1", imx8mp_i2c1_sels, base + 0xad00));
+	clk_dm(IMX8MP_CLK_I2C2, imx8m_clk_composite(dev, "i2c2", imx8mp_i2c2_sels, base + 0xad80));
+	clk_dm(IMX8MP_CLK_I2C3, imx8m_clk_composite(dev, "i2c3", imx8mp_i2c3_sels, base + 0xae00));
+	clk_dm(IMX8MP_CLK_I2C4, imx8m_clk_composite(dev, "i2c4", imx8mp_i2c4_sels, base + 0xae80));
+
+	clk_dm(IMX8MP_CLK_UART1, imx8m_clk_composite(dev, "uart1", imx8mp_uart1_sels, base + 0xaf00));
+	clk_dm(IMX8MP_CLK_UART2, imx8m_clk_composite(dev, "uart2", imx8mp_uart2_sels, base + 0xaf80));
+	clk_dm(IMX8MP_CLK_UART3, imx8m_clk_composite(dev, "uart3", imx8mp_uart3_sels, base + 0xb000));
+	clk_dm(IMX8MP_CLK_UART4, imx8m_clk_composite(dev, "uart4", imx8mp_uart4_sels, base + 0xb080));
+	clk_dm(IMX8MP_CLK_USB_CORE_REF, imx8m_clk_composite(dev, "usb_core_ref", imx8mp_usb_core_ref_sels, base + 0xb100));
+	clk_dm(IMX8MP_CLK_USB_PHY_REF, imx8m_clk_composite(dev, "usb_phy_ref", imx8mp_usb_phy_ref_sels, base + 0xb180));
+	clk_dm(IMX8MP_CLK_GIC, imx8m_clk_composite_critical(dev, "gic", imx8mp_gic_sels, base + 0xb200));
+	clk_dm(IMX8MP_CLK_ECSPI1, imx8m_clk_composite(dev, "ecspi1", imx8mp_ecspi1_sels, base + 0xb280));
+	clk_dm(IMX8MP_CLK_ECSPI2, imx8m_clk_composite(dev, "ecspi2", imx8mp_ecspi2_sels, base + 0xb300));
+	clk_dm(IMX8MP_CLK_PWM1, imx8m_clk_composite_critical(dev, "pwm1", imx8mp_pwm1_sels, base + 0xb380));
+	clk_dm(IMX8MP_CLK_PWM2, imx8m_clk_composite_critical(dev, "pwm2", imx8mp_pwm2_sels, base + 0xb400));
+	clk_dm(IMX8MP_CLK_PWM3, imx8m_clk_composite_critical(dev, "pwm3", imx8mp_pwm3_sels, base + 0xb480));
+	clk_dm(IMX8MP_CLK_PWM4, imx8m_clk_composite_critical(dev, "pwm4", imx8mp_pwm4_sels, base + 0xb500));
+	clk_dm(IMX8MP_CLK_ECSPI3, imx8m_clk_composite(dev, "ecspi3", imx8mp_ecspi3_sels, base + 0xc180));
+
+	clk_dm(IMX8MP_CLK_WDOG, imx8m_clk_composite(dev, "wdog", imx8mp_wdog_sels, base + 0xb900));
+	clk_dm(IMX8MP_CLK_USDHC3, imx8m_clk_composite(dev, "usdhc3", imx8mp_usdhc3_sels, base + 0xbc80));
+
+	clk_dm(IMX8MP_CLK_DRAM_ALT_ROOT, imx_clk_fixed_factor(dev, "dram_alt_root", "dram_alt", 1, 4));
+	clk_dm(IMX8MP_CLK_DRAM_CORE, imx_clk_mux2_flags(dev, "dram_core_clk", base + 0x9800, 24, 1, imx8mp_dram_core_sels, ARRAY_SIZE(imx8mp_dram_core_sels), CLK_IS_CRITICAL));
+
+	clk_dm(IMX8MP_CLK_DRAM1_ROOT, imx_clk_gate4_flags(dev, "dram1_root_clk", "dram_core_clk", base + 0x4050, 0, CLK_IS_CRITICAL));
+	clk_dm(IMX8MP_CLK_ECSPI1_ROOT, imx_clk_gate4(dev, "ecspi1_root_clk", "ecspi1", base + 0x4070, 0));
+	clk_dm(IMX8MP_CLK_ECSPI2_ROOT, imx_clk_gate4(dev, "ecspi2_root_clk", "ecspi2", base + 0x4080, 0));
+	clk_dm(IMX8MP_CLK_ECSPI3_ROOT, imx_clk_gate4(dev, "ecspi3_root_clk", "ecspi3", base + 0x4090, 0));
+	clk_dm(IMX8MP_CLK_ENET1_ROOT, imx_clk_gate4(dev, "enet1_root_clk", "enet_axi", base + 0x40a0, 0));
+	clk_dm(IMX8MP_CLK_GPIO1_ROOT, imx_clk_gate4(dev, "gpio1_root_clk", "ipg_root", base + 0x40b0, 0));
+	clk_dm(IMX8MP_CLK_GPIO2_ROOT, imx_clk_gate4(dev, "gpio2_root_clk", "ipg_root", base + 0x40c0, 0));
+	clk_dm(IMX8MP_CLK_GPIO3_ROOT, imx_clk_gate4(dev, "gpio3_root_clk", "ipg_root", base + 0x40d0, 0));
+	clk_dm(IMX8MP_CLK_GPIO4_ROOT, imx_clk_gate4(dev, "gpio4_root_clk", "ipg_root", base + 0x40e0, 0));
+	clk_dm(IMX8MP_CLK_GPIO5_ROOT, imx_clk_gate4(dev, "gpio5_root_clk", "ipg_root", base + 0x40f0, 0));
+	clk_dm(IMX8MP_CLK_I2C1_ROOT, imx_clk_gate4(dev, "i2c1_root_clk", "i2c1", base + 0x4170, 0));
+	clk_dm(IMX8MP_CLK_I2C2_ROOT, imx_clk_gate4(dev, "i2c2_root_clk", "i2c2", base + 0x4180, 0));
+	clk_dm(IMX8MP_CLK_I2C3_ROOT, imx_clk_gate4(dev, "i2c3_root_clk", "i2c3", base + 0x4190, 0));
+	clk_dm(IMX8MP_CLK_I2C4_ROOT, imx_clk_gate4(dev, "i2c4_root_clk", "i2c4", base + 0x41a0, 0));
+	clk_dm(IMX8MP_CLK_PCIE_ROOT, imx_clk_gate4(dev, "pcie_root_clk", "pcie_aux", base + 0x4250, 0));
+	clk_dm(IMX8MP_CLK_PWM1_ROOT, imx_clk_gate4(dev, "pwm1_root_clk", "pwm1", base + 0x4280, 0));
+	clk_dm(IMX8MP_CLK_PWM2_ROOT, imx_clk_gate4(dev, "pwm2_root_clk", "pwm2", base + 0x4290, 0));
+	clk_dm(IMX8MP_CLK_PWM3_ROOT, imx_clk_gate4(dev, "pwm3_root_clk", "pwm3", base + 0x42a0, 0));
+	clk_dm(IMX8MP_CLK_PWM4_ROOT, imx_clk_gate4(dev, "pwm4_root_clk", "pwm4", base + 0x42b0, 0));
+	clk_dm(IMX8MP_CLK_QOS_ROOT, imx_clk_gate4(dev, "qos_root_clk", "ipg_root", base + 0x42c0, 0));
+	clk_dm(IMX8MP_CLK_QOS_ENET_ROOT, imx_clk_gate4(dev, "qos_enet_root_clk", "ipg_root", base + 0x42e0, 0));
+	clk_dm(IMX8MP_CLK_QSPI_ROOT, imx_clk_gate4(dev, "qspi_root_clk", "qspi", base + 0x42f0, 0));
+	clk_dm(IMX8MP_CLK_I2C5_ROOT, imx_clk_gate2(dev, "i2c5_root_clk", "i2c5", base + 0x4330, 0));
+	clk_dm(IMX8MP_CLK_I2C6_ROOT, imx_clk_gate2(dev, "i2c6_root_clk", "i2c6", base + 0x4340, 0));
+	clk_dm(IMX8MP_CLK_SIM_ENET_ROOT, imx_clk_gate4(dev, "sim_enet_root_clk", "enet_axi", base + 0x4400, 0));
+	clk_dm(IMX8MP_CLK_ENET_QOS_ROOT, imx_clk_gate4(dev, "enet_qos_root_clk", "sim_enet_root_clk", base + 0x43b0, 0));
+	clk_dm(IMX8MP_CLK_UART1_ROOT, imx_clk_gate4(dev, "uart1_root_clk", "uart1", base + 0x4490, 0));
+	clk_dm(IMX8MP_CLK_UART2_ROOT, imx_clk_gate4(dev, "uart2_root_clk", "uart2", base + 0x44a0, 0));
+	clk_dm(IMX8MP_CLK_UART3_ROOT, imx_clk_gate4(dev, "uart3_root_clk", "uart3", base + 0x44b0, 0));
+	clk_dm(IMX8MP_CLK_UART4_ROOT, imx_clk_gate4(dev, "uart4_root_clk", "uart4", base + 0x44c0, 0));
+	clk_dm(IMX8MP_CLK_USB_ROOT, imx_clk_gate2(dev, "usb_root_clk", "hsio_axi", base + 0x44d0, 0));
+	clk_dm(IMX8MP_CLK_USB_SUSP, imx_clk_gate2(dev, "usb_suspend_clk", "osc_24m", base + 0x44d0, 0));
+	clk_dm(IMX8MP_CLK_USB_PHY_ROOT, imx_clk_gate4(dev, "usb_phy_root_clk", "usb_phy_ref", base + 0x44f0, 0));
+	clk_dm(IMX8MP_CLK_USDHC1_ROOT, imx_clk_gate4(dev, "usdhc1_root_clk", "usdhc1", base + 0x4510, 0));
+	clk_dm(IMX8MP_CLK_USDHC2_ROOT, imx_clk_gate4(dev, "usdhc2_root_clk", "usdhc2", base + 0x4520, 0));
+	clk_dm(IMX8MP_CLK_WDOG1_ROOT, imx_clk_gate4(dev, "wdog1_root_clk", "wdog", base + 0x4530, 0));
+	clk_dm(IMX8MP_CLK_WDOG2_ROOT, imx_clk_gate4(dev, "wdog2_root_clk", "wdog", base + 0x4540, 0));
+	clk_dm(IMX8MP_CLK_WDOG3_ROOT, imx_clk_gate4(dev, "wdog3_root_clk", "wdog", base + 0x4550, 0));
+	clk_dm(IMX8MP_CLK_HSIO_ROOT, imx_clk_gate4(dev, "hsio_root_clk", "ipg_root", base + 0x45c0, 0));
+
+	clk_dm(IMX8MP_CLK_USDHC3_ROOT, imx_clk_gate4(dev, "usdhc3_root_clk", "usdhc3", base + 0x45e0, 0));
 
 	clk_dm(IMX8MP_CLK_ARM,
-	       imx_clk_mux2_flags("arm_core", base + 0x9880, 24, 1,
+	       imx_clk_mux2_flags(dev, "arm_core", base + 0x9880, 24, 1,
 				  imx8mp_arm_core_sels,
 				  ARRAY_SIZE(imx8mp_arm_core_sels),
 				  CLK_IS_CRITICAL));
diff --git a/drivers/clk/imx/clk-imx8mq.c b/drivers/clk/imx/clk-imx8mq.c
index ed4acd79ef7..fe6cba19758 100644
--- a/drivers/clk/imx/clk-imx8mq.c
+++ b/drivers/clk/imx/clk-imx8mq.c
@@ -152,31 +152,31 @@ static int imx8mq_clk_probe(struct udevice *dev)
 	clk_dm(IMX8MQ_CLK_27M, clk_register_fixed_rate(NULL, "clock-osc-27m", 27000000));
 
 	clk_dm(IMX8MQ_DRAM_PLL1_REF_SEL,
-	       imx_clk_mux("dram_pll_ref_sel", base + 0x60, 0, 2,
+	       imx_clk_mux(dev, "dram_pll_ref_sel", base + 0x60, 0, 2,
 			   pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
 	clk_dm(IMX8MQ_ARM_PLL_REF_SEL,
-	       imx_clk_mux("arm_pll_ref_sel", base + 0x28, 0, 2,
+	       imx_clk_mux(dev, "arm_pll_ref_sel", base + 0x28, 0, 2,
 			   pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
 	clk_dm(IMX8MQ_GPU_PLL_REF_SEL,
-	       imx_clk_mux("gpu_pll_ref_sel", base + 0x18, 0, 2,
+	       imx_clk_mux(dev, "gpu_pll_ref_sel", base + 0x18, 0, 2,
 			   pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
 	clk_dm(IMX8MQ_VPU_PLL_REF_SEL,
-	       imx_clk_mux("vpu_pll_ref_sel", base + 0x20, 0, 2,
+	       imx_clk_mux(dev, "vpu_pll_ref_sel", base + 0x20, 0, 2,
 			   pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
 	clk_dm(IMX8MQ_SYS3_PLL1_REF_SEL,
-	       imx_clk_mux("sys3_pll_ref_sel", base + 0x48, 0, 2,
+	       imx_clk_mux(dev, "sys3_pll_ref_sel", base + 0x48, 0, 2,
 			   pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
 	clk_dm(IMX8MQ_AUDIO_PLL1_REF_SEL,
-	       imx_clk_mux("audio_pll1_ref_sel", base + 0x0, 0, 2,
+	       imx_clk_mux(dev, "audio_pll1_ref_sel", base + 0x0, 0, 2,
 			   pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
 	clk_dm(IMX8MQ_AUDIO_PLL2_REF_SEL,
-	       imx_clk_mux("audio_pll2_ref_sel", base + 0x8, 0, 2,
+	       imx_clk_mux(dev, "audio_pll2_ref_sel", base + 0x8, 0, 2,
 			   pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
 	clk_dm(IMX8MQ_VIDEO_PLL1_REF_SEL,
-	       imx_clk_mux("video_pll1_ref_sel", base + 0x10, 0, 2,
+	       imx_clk_mux(dev, "video_pll1_ref_sel", base + 0x10, 0, 2,
 			   pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
 	clk_dm(IMX8MQ_VIDEO2_PLL1_REF_SEL,
-	       imx_clk_mux("video_pll2_ref_sel", base + 0x54, 0, 2,
+	       imx_clk_mux(dev, "video_pll2_ref_sel", base + 0x54, 0, 2,
 			   pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
 
 	clk_dm(IMX8MQ_ARM_PLL,
@@ -207,140 +207,140 @@ static int imx8mq_clk_probe(struct udevice *dev)
 
 	/* PLL bypass out */
 	clk_dm(IMX8MQ_ARM_PLL_BYPASS,
-	       imx_clk_mux_flags("arm_pll_bypass", base + 0x28, 4, 1,
+	       imx_clk_mux_flags(dev, "arm_pll_bypass", base + 0x28, 4, 1,
 				 arm_pll_bypass_sels,
 				 ARRAY_SIZE(arm_pll_bypass_sels),
 				 CLK_SET_RATE_PARENT));
 	clk_dm(IMX8MQ_GPU_PLL_BYPASS,
-	       imx_clk_mux_flags("gpu_pll_bypass", base + 0x18, 4, 1,
+	       imx_clk_mux_flags(dev, "gpu_pll_bypass", base + 0x18, 4, 1,
 				 gpu_pll_bypass_sels,
 				 ARRAY_SIZE(gpu_pll_bypass_sels),
 				 CLK_SET_RATE_PARENT));
 	clk_dm(IMX8MQ_VPU_PLL_BYPASS,
-	       imx_clk_mux_flags("vpu_pll_bypass", base + 0x20, 4, 1,
+	       imx_clk_mux_flags(dev, "vpu_pll_bypass", base + 0x20, 4, 1,
 				 vpu_pll_bypass_sels,
 				 ARRAY_SIZE(vpu_pll_bypass_sels),
 				 CLK_SET_RATE_PARENT));
 	clk_dm(IMX8MQ_AUDIO_PLL1_BYPASS,
-	       imx_clk_mux_flags("audio_pll1_bypass", base + 0x0, 4, 1,
+	       imx_clk_mux_flags(dev, "audio_pll1_bypass", base + 0x0, 4, 1,
 				 audio_pll1_bypass_sels,
 				 ARRAY_SIZE(audio_pll1_bypass_sels),
 				 CLK_SET_RATE_PARENT));
 	clk_dm(IMX8MQ_AUDIO_PLL2_BYPASS,
-	       imx_clk_mux_flags("audio_pll2_bypass", base + 0x8, 4, 1,
+	       imx_clk_mux_flags(dev, "audio_pll2_bypass", base + 0x8, 4, 1,
 				 audio_pll2_bypass_sels,
 				 ARRAY_SIZE(audio_pll2_bypass_sels),
 				 CLK_SET_RATE_PARENT));
 	clk_dm(IMX8MQ_VIDEO_PLL1_BYPASS,
-	       imx_clk_mux_flags("video_pll1_bypass", base + 0x10, 4, 1,
+	       imx_clk_mux_flags(dev, "video_pll1_bypass", base + 0x10, 4, 1,
 				 video_pll1_bypass_sels,
 				 ARRAY_SIZE(video_pll1_bypass_sels),
 				 CLK_SET_RATE_PARENT));
 
 	/* PLL out gate */
 	clk_dm(IMX8MQ_DRAM_PLL_OUT,
-	       imx_clk_gate("dram_pll_out", "dram_pll_ref_sel",
+	       imx_clk_gate(dev, "dram_pll_out", "dram_pll_ref_sel",
 			    base + 0x60, 13));
 	clk_dm(IMX8MQ_ARM_PLL_OUT,
-	       imx_clk_gate("arm_pll_out", "arm_pll_bypass",
+	       imx_clk_gate(dev, "arm_pll_out", "arm_pll_bypass",
 			    base + 0x28, 11));
 	clk_dm(IMX8MQ_GPU_PLL_OUT,
-	       imx_clk_gate("gpu_pll_out", "gpu_pll_bypass",
+	       imx_clk_gate(dev, "gpu_pll_out", "gpu_pll_bypass",
 			    base + 0x18, 11));
 	clk_dm(IMX8MQ_VPU_PLL_OUT,
-	       imx_clk_gate("vpu_pll_out", "vpu_pll_bypass",
+	       imx_clk_gate(dev, "vpu_pll_out", "vpu_pll_bypass",
 			    base + 0x20, 11));
 	clk_dm(IMX8MQ_AUDIO_PLL1_OUT,
-	       imx_clk_gate("audio_pll1_out", "audio_pll1_bypass",
+	       imx_clk_gate(dev, "audio_pll1_out", "audio_pll1_bypass",
 			    base + 0x0, 11));
 	clk_dm(IMX8MQ_AUDIO_PLL2_OUT,
-	       imx_clk_gate("audio_pll2_out", "audio_pll2_bypass",
+	       imx_clk_gate(dev, "audio_pll2_out", "audio_pll2_bypass",
 			    base + 0x8, 11));
 	clk_dm(IMX8MQ_VIDEO_PLL1_OUT,
-	       imx_clk_gate("video_pll1_out", "video_pll1_bypass",
+	       imx_clk_gate(dev, "video_pll1_out", "video_pll1_bypass",
 			    base + 0x10, 11));
 
 	clk_dm(IMX8MQ_SYS1_PLL_OUT,
-	       imx_clk_gate("sys_pll1_out", "sys1_pll",
+	       imx_clk_gate(dev, "sys_pll1_out", "sys1_pll",
 			    base + 0x30, 11));
 	clk_dm(IMX8MQ_SYS2_PLL_OUT,
-	       imx_clk_gate("sys_pll2_out", "sys2_pll",
+	       imx_clk_gate(dev, "sys_pll2_out", "sys2_pll",
 			    base + 0x3c, 11));
 	clk_dm(IMX8MQ_SYS3_PLL_OUT,
-	       imx_clk_gate("sys_pll3_out", "sys3_pll",
+	       imx_clk_gate(dev, "sys_pll3_out", "sys3_pll",
 			    base + 0x48, 11));
 	clk_dm(IMX8MQ_VIDEO2_PLL_OUT,
-	       imx_clk_gate("video_pll2_out", "video_pll2_ref_sel",
+	       imx_clk_gate(dev, "video_pll2_out", "video_pll2_ref_sel",
 			    base + 0x54, 11));
 
 	/* SYS PLL fixed output */
 	clk_dm(IMX8MQ_SYS1_PLL_40M,
-	       imx_clk_fixed_factor("sys_pll1_40m", "sys_pll1_out", 1, 20));
+	       imx_clk_fixed_factor(dev, "sys_pll1_40m", "sys_pll1_out", 1, 20));
 	clk_dm(IMX8MQ_SYS1_PLL_80M,
-	       imx_clk_fixed_factor("sys_pll1_80m", "sys_pll1_out", 1, 10));
+	       imx_clk_fixed_factor(dev, "sys_pll1_80m", "sys_pll1_out", 1, 10));
 	clk_dm(IMX8MQ_SYS1_PLL_100M,
-	       imx_clk_fixed_factor("sys_pll1_100m", "sys_pll1_out", 1, 8));
+	       imx_clk_fixed_factor(dev, "sys_pll1_100m", "sys_pll1_out", 1, 8));
 	clk_dm(IMX8MQ_SYS1_PLL_133M,
-	       imx_clk_fixed_factor("sys_pll1_133m", "sys_pll1_out", 1, 6));
+	       imx_clk_fixed_factor(dev, "sys_pll1_133m", "sys_pll1_out", 1, 6));
 	clk_dm(IMX8MQ_SYS1_PLL_160M,
-	       imx_clk_fixed_factor("sys_pll1_160m", "sys_pll1_out", 1, 5));
+	       imx_clk_fixed_factor(dev, "sys_pll1_160m", "sys_pll1_out", 1, 5));
 	clk_dm(IMX8MQ_SYS1_PLL_200M,
-	       imx_clk_fixed_factor("sys_pll1_200m", "sys_pll1_out", 1, 4));
+	       imx_clk_fixed_factor(dev, "sys_pll1_200m", "sys_pll1_out", 1, 4));
 	clk_dm(IMX8MQ_SYS1_PLL_266M,
-	       imx_clk_fixed_factor("sys_pll1_266m", "sys_pll1_out", 1, 3));
+	       imx_clk_fixed_factor(dev, "sys_pll1_266m", "sys_pll1_out", 1, 3));
 	clk_dm(IMX8MQ_SYS1_PLL_400M,
-	       imx_clk_fixed_factor("sys_pll1_400m", "sys_pll1_out", 1, 2));
+	       imx_clk_fixed_factor(dev, "sys_pll1_400m", "sys_pll1_out", 1, 2));
 	clk_dm(IMX8MQ_SYS1_PLL_800M,
-	       imx_clk_fixed_factor("sys_pll1_800m", "sys_pll1_out", 1, 1));
+	       imx_clk_fixed_factor(dev, "sys_pll1_800m", "sys_pll1_out", 1, 1));
 
 	clk_dm(IMX8MQ_SYS2_PLL_50M,
-	       imx_clk_fixed_factor("sys_pll2_50m", "sys_pll2_out", 1, 20));
+	       imx_clk_fixed_factor(dev, "sys_pll2_50m", "sys_pll2_out", 1, 20));
 	clk_dm(IMX8MQ_SYS2_PLL_100M,
-	       imx_clk_fixed_factor("sys_pll2_100m", "sys_pll2_out", 1, 10));
+	       imx_clk_fixed_factor(dev, "sys_pll2_100m", "sys_pll2_out", 1, 10));
 	clk_dm(IMX8MQ_SYS2_PLL_125M,
-	       imx_clk_fixed_factor("sys_pll2_125m", "sys_pll2_out", 1, 8));
+	       imx_clk_fixed_factor(dev, "sys_pll2_125m", "sys_pll2_out", 1, 8));
 	clk_dm(IMX8MQ_SYS2_PLL_166M,
-	       imx_clk_fixed_factor("sys_pll2_166m", "sys_pll2_out", 1, 6));
+	       imx_clk_fixed_factor(dev, "sys_pll2_166m", "sys_pll2_out", 1, 6));
 	clk_dm(IMX8MQ_SYS2_PLL_200M,
-	       imx_clk_fixed_factor("sys_pll2_200m", "sys_pll2_out", 1, 5));
+	       imx_clk_fixed_factor(dev, "sys_pll2_200m", "sys_pll2_out", 1, 5));
 	clk_dm(IMX8MQ_SYS2_PLL_250M,
-	       imx_clk_fixed_factor("sys_pll2_250m", "sys_pll2_out", 1, 4));
+	       imx_clk_fixed_factor(dev, "sys_pll2_250m", "sys_pll2_out", 1, 4));
 	clk_dm(IMX8MQ_SYS2_PLL_333M,
-	       imx_clk_fixed_factor("sys_pll2_333m", "sys_pll2_out", 1, 3));
+	       imx_clk_fixed_factor(dev, "sys_pll2_333m", "sys_pll2_out", 1, 3));
 	clk_dm(IMX8MQ_SYS2_PLL_500M,
-	       imx_clk_fixed_factor("sys_pll2_500m", "sys_pll2_out", 1, 2));
+	       imx_clk_fixed_factor(dev, "sys_pll2_500m", "sys_pll2_out", 1, 2));
 	clk_dm(IMX8MQ_SYS2_PLL_1000M,
-	       imx_clk_fixed_factor("sys_pll2_1000m", "sys_pll2_out", 1, 1));
+	       imx_clk_fixed_factor(dev, "sys_pll2_1000m", "sys_pll2_out", 1, 1));
 
 	clk_dm(IMX8MQ_CLK_MON_AUDIO_PLL1_DIV,
-	       imx_clk_divider("audio_pll1_out_monitor", "audio_pll1_bypass", base + 0x78, 0, 3));
+	       imx_clk_divider(dev, "audio_pll1_out_monitor", "audio_pll1_bypass", base + 0x78, 0, 3));
 	clk_dm(IMX8MQ_CLK_MON_AUDIO_PLL2_DIV,
-	       imx_clk_divider("audio_pll2_out_monitor", "audio_pll2_bypass", base + 0x78, 4, 3));
+	       imx_clk_divider(dev, "audio_pll2_out_monitor", "audio_pll2_bypass", base + 0x78, 4, 3));
 	clk_dm(IMX8MQ_CLK_MON_VIDEO_PLL1_DIV,
-	       imx_clk_divider("video_pll1_out_monitor", "video_pll1_bypass", base + 0x78, 8, 3));
+	       imx_clk_divider(dev, "video_pll1_out_monitor", "video_pll1_bypass", base + 0x78, 8, 3));
 	clk_dm(IMX8MQ_CLK_MON_GPU_PLL_DIV,
-	       imx_clk_divider("gpu_pll_out_monitor", "gpu_pll_bypass", base + 0x78, 12, 3));
+	       imx_clk_divider(dev, "gpu_pll_out_monitor", "gpu_pll_bypass", base + 0x78, 12, 3));
 	clk_dm(IMX8MQ_CLK_MON_VPU_PLL_DIV,
-	       imx_clk_divider("vpu_pll_out_monitor", "vpu_pll_bypass", base + 0x78, 16, 3));
+	       imx_clk_divider(dev, "vpu_pll_out_monitor", "vpu_pll_bypass", base + 0x78, 16, 3));
 	clk_dm(IMX8MQ_CLK_MON_ARM_PLL_DIV,
-	       imx_clk_divider("arm_pll_out_monitor", "arm_pll_bypass", base + 0x78, 20, 3));
+	       imx_clk_divider(dev, "arm_pll_out_monitor", "arm_pll_bypass", base + 0x78, 20, 3));
 	clk_dm(IMX8MQ_CLK_MON_SYS_PLL1_DIV,
-	       imx_clk_divider("sys_pll1_out_monitor", "sys_pll1_out", base + 0x7c, 0, 3));
+	       imx_clk_divider(dev, "sys_pll1_out_monitor", "sys_pll1_out", base + 0x7c, 0, 3));
 	clk_dm(IMX8MQ_CLK_MON_SYS_PLL2_DIV,
-	       imx_clk_divider("sys_pll2_out_monitor", "sys_pll2_out", base + 0x7c, 4, 3));
+	       imx_clk_divider(dev, "sys_pll2_out_monitor", "sys_pll2_out", base + 0x7c, 4, 3));
 	clk_dm(IMX8MQ_CLK_MON_SYS_PLL3_DIV,
-	       imx_clk_divider("sys_pll3_out_monitor", "sys_pll3_out", base + 0x7c, 8, 3));
+	       imx_clk_divider(dev, "sys_pll3_out_monitor", "sys_pll3_out", base + 0x7c, 8, 3));
 	clk_dm(IMX8MQ_CLK_MON_DRAM_PLL_DIV,
-	       imx_clk_divider("dram_pll_out_monitor", "dram_pll_out", base + 0x7c, 12, 3));
+	       imx_clk_divider(dev, "dram_pll_out_monitor", "dram_pll_out", base + 0x7c, 12, 3));
 	clk_dm(IMX8MQ_CLK_MON_VIDEO_PLL2_DIV,
-	       imx_clk_divider("video_pll2_out_monitor", "video_pll2_out", base + 0x7c, 16, 3));
+	       imx_clk_divider(dev, "video_pll2_out_monitor", "video_pll2_out", base + 0x7c, 16, 3));
 	clk_dm(IMX8MQ_CLK_MON_SEL,
-	       imx_clk_mux_flags("pllout_monitor_sel", base + 0x74, 0, 4,
+	       imx_clk_mux_flags(dev, "pllout_monitor_sel", base + 0x74, 0, 4,
 				 pllout_monitor_sels,
 				 ARRAY_SIZE(pllout_monitor_sels),
 				 CLK_SET_RATE_PARENT));
 	clk_dm(IMX8MQ_CLK_MON_CLK2_OUT,
-	       imx_clk_gate4("pllout_monitor_clk2", "pllout_monitor_sel", base + 0x74, 4));
+	       imx_clk_gate4(dev, "pllout_monitor_clk2", "pllout_monitor_sel", base + 0x74, 4));
 
 	base = dev_read_addr_ptr(dev);
 	if (!base) {
@@ -349,140 +349,140 @@ static int imx8mq_clk_probe(struct udevice *dev)
 	}
 
 	clk_dm(IMX8MQ_CLK_A53_SRC,
-	       imx_clk_mux2("arm_a53_src", base + 0x8000, 24, 3,
+	       imx_clk_mux2(dev, "arm_a53_src", base + 0x8000, 24, 3,
 			    imx8mq_a53_sels, ARRAY_SIZE(imx8mq_a53_sels)));
 	clk_dm(IMX8MQ_CLK_A53_CG,
-	       imx_clk_gate3("arm_a53_cg", "arm_a53_src", base + 0x8000, 28));
+	       imx_clk_gate3(dev, "arm_a53_cg", "arm_a53_src", base + 0x8000, 28));
 	clk_dm(IMX8MQ_CLK_A53_DIV,
-	       imx_clk_divider2("arm_a53_div", "arm_a53_cg",
+	       imx_clk_divider2(dev, "arm_a53_div", "arm_a53_cg",
 				base + 0x8000, 0, 3));
 	clk_dm(IMX8MQ_CLK_A53_CORE,
-	       imx_clk_mux2("arm_a53_src", base + 0x9880, 24, 1,
+	       imx_clk_mux2(dev, "arm_a53_src", base + 0x9880, 24, 1,
 			    imx8mq_a53_core_sels, ARRAY_SIZE(imx8mq_a53_core_sels)));
 
 	clk_dm(IMX8MQ_CLK_AHB,
-	       imx8m_clk_composite_critical("ahb", imx8mq_ahb_sels,
+	       imx8m_clk_composite_critical(dev, "ahb", imx8mq_ahb_sels,
 					    base + 0x9000));
 	clk_dm(IMX8MQ_CLK_IPG_ROOT,
-	       imx_clk_divider2("ipg_root", "ahb", base + 0x9080, 0, 1));
+	       imx_clk_divider2(dev, "ipg_root", "ahb", base + 0x9080, 0, 1));
 
 	clk_dm(IMX8MQ_CLK_ENET_AXI,
-	       imx8m_clk_composite("enet_axi", imx8mq_enet_axi_sels,
+	       imx8m_clk_composite(dev, "enet_axi", imx8mq_enet_axi_sels,
 				   base + 0x8880));
 	clk_dm(IMX8MQ_CLK_NAND_USDHC_BUS,
-	       imx8m_clk_composite_critical("nand_usdhc_bus",
+	       imx8m_clk_composite_critical(dev, "nand_usdhc_bus",
 					    imx8mq_nand_usdhc_sels,
 					    base + 0x8900));
 	clk_dm(IMX8MQ_CLK_USB_BUS,
-	       imx8m_clk_composite("usb_bus", imx8mq_usb_bus_sels, base + 0x8b80));
+	       imx8m_clk_composite(dev, "usb_bus", imx8mq_usb_bus_sels, base + 0x8b80));
 
 	/* DRAM */
 	clk_dm(IMX8MQ_CLK_DRAM_CORE,
-	       imx_clk_mux2("dram_core_clk", base + 0x9800, 24, 1,
+	       imx_clk_mux2(dev, "dram_core_clk", base + 0x9800, 24, 1,
 			    imx8mq_dram_core_sels, ARRAY_SIZE(imx8mq_dram_core_sels)));
 	clk_dm(IMX8MQ_CLK_DRAM_ALT,
-	       imx8m_clk_composite("dram_alt", imx8mq_dram_alt_sels, base + 0xa000));
+	       imx8m_clk_composite(dev, "dram_alt", imx8mq_dram_alt_sels, base + 0xa000));
 	clk_dm(IMX8MQ_CLK_DRAM_APB,
-	       imx8m_clk_composite_critical("dram_apb", imx8mq_dram_apb_sels, base + 0xa080));
+	       imx8m_clk_composite_critical(dev, "dram_apb", imx8mq_dram_apb_sels, base + 0xa080));
 
 	/* IP */
 	clk_dm(IMX8MQ_CLK_USDHC1,
-	       imx8m_clk_composite("usdhc1", imx8mq_usdhc1_sels,
+	       imx8m_clk_composite(dev, "usdhc1", imx8mq_usdhc1_sels,
 				   base + 0xac00));
 	clk_dm(IMX8MQ_CLK_USDHC2,
-	       imx8m_clk_composite("usdhc2", imx8mq_usdhc2_sels,
+	       imx8m_clk_composite(dev, "usdhc2", imx8mq_usdhc2_sels,
 				   base + 0xac80));
 	clk_dm(IMX8MQ_CLK_I2C1,
-	       imx8m_clk_composite("i2c1", imx8mq_i2c1_sels, base + 0xad00));
+	       imx8m_clk_composite(dev, "i2c1", imx8mq_i2c1_sels, base + 0xad00));
 	clk_dm(IMX8MQ_CLK_I2C2,
-	       imx8m_clk_composite("i2c2", imx8mq_i2c2_sels, base + 0xad80));
+	       imx8m_clk_composite(dev, "i2c2", imx8mq_i2c2_sels, base + 0xad80));
 	clk_dm(IMX8MQ_CLK_I2C3,
-	       imx8m_clk_composite("i2c3", imx8mq_i2c3_sels, base + 0xae00));
+	       imx8m_clk_composite(dev, "i2c3", imx8mq_i2c3_sels, base + 0xae00));
 	clk_dm(IMX8MQ_CLK_I2C4,
-	       imx8m_clk_composite("i2c4", imx8mq_i2c4_sels, base + 0xae80));
+	       imx8m_clk_composite(dev, "i2c4", imx8mq_i2c4_sels, base + 0xae80));
 	clk_dm(IMX8MQ_CLK_WDOG,
-	       imx8m_clk_composite("wdog", imx8mq_wdog_sels, base + 0xb900));
+	       imx8m_clk_composite(dev, "wdog", imx8mq_wdog_sels, base + 0xb900));
 	clk_dm(IMX8MQ_CLK_UART1,
-	       imx8m_clk_composite("uart1", imx8mq_uart1_sels, base + 0xaf00));
+	       imx8m_clk_composite(dev, "uart1", imx8mq_uart1_sels, base + 0xaf00));
 	clk_dm(IMX8MQ_CLK_UART2,
-	       imx8m_clk_composite("uart2", imx8mq_uart2_sels, base + 0xaf80));
+	       imx8m_clk_composite(dev, "uart2", imx8mq_uart2_sels, base + 0xaf80));
 	clk_dm(IMX8MQ_CLK_UART3,
-	       imx8m_clk_composite("uart3", imx8mq_uart3_sels, base + 0xb000));
+	       imx8m_clk_composite(dev, "uart3", imx8mq_uart3_sels, base + 0xb000));
 	clk_dm(IMX8MQ_CLK_UART4,
-	       imx8m_clk_composite("uart4", imx8mq_uart4_sels, base + 0xb080));
+	       imx8m_clk_composite(dev, "uart4", imx8mq_uart4_sels, base + 0xb080));
 	clk_dm(IMX8MQ_CLK_QSPI,
-	       imx8m_clk_composite("qspi", imx8mq_qspi_sels, base + 0xab80));
+	       imx8m_clk_composite(dev, "qspi", imx8mq_qspi_sels, base + 0xab80));
 	clk_dm(IMX8MQ_CLK_USB_CORE_REF,
-	       imx8m_clk_composite("usb_core_ref", imx8mq_usb_core_sels, base + 0xb100));
+	       imx8m_clk_composite(dev, "usb_core_ref", imx8mq_usb_core_sels, base + 0xb100));
 	clk_dm(IMX8MQ_CLK_USB_PHY_REF,
-	       imx8m_clk_composite("usb_phy_ref", imx8mq_usb_phy_sels, base + 0xb180));
+	       imx8m_clk_composite(dev, "usb_phy_ref", imx8mq_usb_phy_sels, base + 0xb180));
 	clk_dm(IMX8MQ_CLK_ECSPI1,
-	       imx8m_clk_composite("ecspi1", imx8mq_ecspi1_sels, base + 0xb280));
+	       imx8m_clk_composite(dev, "ecspi1", imx8mq_ecspi1_sels, base + 0xb280));
 	clk_dm(IMX8MQ_CLK_ECSPI2,
-	       imx8m_clk_composite("ecspi2", imx8mq_ecspi2_sels, base + 0xb300));
+	       imx8m_clk_composite(dev, "ecspi2", imx8mq_ecspi2_sels, base + 0xb300));
 	clk_dm(IMX8MQ_CLK_ECSPI3,
-	       imx8m_clk_composite("ecspi3", imx8mq_ecspi3_sels, base + 0xc180));
+	       imx8m_clk_composite(dev, "ecspi3", imx8mq_ecspi3_sels, base + 0xc180));
 
 	clk_dm(IMX8MQ_CLK_ECSPI1_ROOT,
-	       imx_clk_gate4("ecspi1_root_clk", "ecspi1", base + 0x4070, 0));
+	       imx_clk_gate4(dev, "ecspi1_root_clk", "ecspi1", base + 0x4070, 0));
 	clk_dm(IMX8MQ_CLK_ECSPI2_ROOT,
-	       imx_clk_gate4("ecspi2_root_clk", "ecspi2", base + 0x4080, 0));
+	       imx_clk_gate4(dev, "ecspi2_root_clk", "ecspi2", base + 0x4080, 0));
 	clk_dm(IMX8MQ_CLK_ECSPI3_ROOT,
-	       imx_clk_gate4("ecspi3_root_clk", "ecspi3", base + 0x4090, 0));
+	       imx_clk_gate4(dev, "ecspi3_root_clk", "ecspi3", base + 0x4090, 0));
 	clk_dm(IMX8MQ_CLK_I2C1_ROOT,
-	       imx_clk_gate4("i2c1_root_clk", "i2c1", base + 0x4170, 0));
+	       imx_clk_gate4(dev, "i2c1_root_clk", "i2c1", base + 0x4170, 0));
 	clk_dm(IMX8MQ_CLK_I2C2_ROOT,
-	       imx_clk_gate4("i2c2_root_clk", "i2c2", base + 0x4180, 0));
+	       imx_clk_gate4(dev, "i2c2_root_clk", "i2c2", base + 0x4180, 0));
 	clk_dm(IMX8MQ_CLK_I2C3_ROOT,
-	       imx_clk_gate4("i2c3_root_clk", "i2c3", base + 0x4190, 0));
+	       imx_clk_gate4(dev, "i2c3_root_clk", "i2c3", base + 0x4190, 0));
 	clk_dm(IMX8MQ_CLK_I2C4_ROOT,
-	       imx_clk_gate4("i2c4_root_clk", "i2c4", base + 0x41a0, 0));
+	       imx_clk_gate4(dev, "i2c4_root_clk", "i2c4", base + 0x41a0, 0));
 	clk_dm(IMX8MQ_CLK_UART1_ROOT,
-	       imx_clk_gate4("uart1_root_clk", "uart1", base + 0x4490, 0));
+	       imx_clk_gate4(dev, "uart1_root_clk", "uart1", base + 0x4490, 0));
 	clk_dm(IMX8MQ_CLK_UART2_ROOT,
-	       imx_clk_gate4("uart2_root_clk", "uart2", base + 0x44a0, 0));
+	       imx_clk_gate4(dev, "uart2_root_clk", "uart2", base + 0x44a0, 0));
 	clk_dm(IMX8MQ_CLK_UART3_ROOT,
-	       imx_clk_gate4("uart3_root_clk", "uart3", base + 0x44b0, 0));
+	       imx_clk_gate4(dev, "uart3_root_clk", "uart3", base + 0x44b0, 0));
 	clk_dm(IMX8MQ_CLK_UART4_ROOT,
-	       imx_clk_gate4("uart4_root_clk", "uart4", base + 0x44c0, 0));
+	       imx_clk_gate4(dev, "uart4_root_clk", "uart4", base + 0x44c0, 0));
 	clk_dm(IMX8MQ_CLK_OCOTP_ROOT,
-	       imx_clk_gate4("ocotp_root_clk", "ipg_root", base + 0x4220, 0));
+	       imx_clk_gate4(dev, "ocotp_root_clk", "ipg_root", base + 0x4220, 0));
 	clk_dm(IMX8MQ_CLK_USDHC1_ROOT,
-	       imx_clk_gate4("usdhc1_root_clk", "usdhc1", base + 0x4510, 0));
+	       imx_clk_gate4(dev, "usdhc1_root_clk", "usdhc1", base + 0x4510, 0));
 	clk_dm(IMX8MQ_CLK_USDHC2_ROOT,
-	       imx_clk_gate4("usdhc2_root_clk", "usdhc2", base + 0x4520, 0));
+	       imx_clk_gate4(dev, "usdhc2_root_clk", "usdhc2", base + 0x4520, 0));
 	clk_dm(IMX8MQ_CLK_WDOG1_ROOT,
-	       imx_clk_gate4("wdog1_root_clk", "wdog", base + 0x4530, 0));
+	       imx_clk_gate4(dev, "wdog1_root_clk", "wdog", base + 0x4530, 0));
 	clk_dm(IMX8MQ_CLK_WDOG2_ROOT,
-	       imx_clk_gate4("wdog2_root_clk", "wdog", base + 0x4540, 0));
+	       imx_clk_gate4(dev, "wdog2_root_clk", "wdog", base + 0x4540, 0));
 	clk_dm(IMX8MQ_CLK_WDOG3_ROOT,
-	       imx_clk_gate4("wdog3_root_clk", "wdog", base + 0x4550, 0));
+	       imx_clk_gate4(dev, "wdog3_root_clk", "wdog", base + 0x4550, 0));
 	clk_dm(IMX8MQ_CLK_QSPI_ROOT,
-	       imx_clk_gate4("qspi_root_clk", "qspi", base + 0x42f0, 0));
+	       imx_clk_gate4(dev, "qspi_root_clk", "qspi", base + 0x42f0, 0));
 	clk_dm(IMX8MQ_CLK_USB1_CTRL_ROOT,
-	       imx_clk_gate4("usb1_ctrl_root_clk", "usb_bus", base + 0x44d0, 0));
+	       imx_clk_gate4(dev, "usb1_ctrl_root_clk", "usb_bus", base + 0x44d0, 0));
 	clk_dm(IMX8MQ_CLK_USB2_CTRL_ROOT,
-	       imx_clk_gate4("usb2_ctrl_root_clk", "usb_bus", base + 0x44e0, 0));
+	       imx_clk_gate4(dev, "usb2_ctrl_root_clk", "usb_bus", base + 0x44e0, 0));
 	clk_dm(IMX8MQ_CLK_USB1_PHY_ROOT,
-	       imx_clk_gate4("usb1_phy_root_clk", "usb_phy_ref", base + 0x44f0, 0));
+	       imx_clk_gate4(dev, "usb1_phy_root_clk", "usb_phy_ref", base + 0x44f0, 0));
 	clk_dm(IMX8MQ_CLK_USB2_PHY_ROOT,
-	       imx_clk_gate4("usb2_phy_root_clk", "usb_phy_ref", base + 0x4500, 0));
+	       imx_clk_gate4(dev, "usb2_phy_root_clk", "usb_phy_ref", base + 0x4500, 0));
 
 	clk_dm(IMX8MQ_CLK_ENET_REF,
-	       imx8m_clk_composite("enet_ref", imx8mq_enet_ref_sels,
+	       imx8m_clk_composite(dev, "enet_ref", imx8mq_enet_ref_sels,
 				   base + 0xa980));
 	clk_dm(IMX8MQ_CLK_ENET_TIMER,
-	       imx8m_clk_composite("enet_timer", imx8mq_enet_timer_sels,
+	       imx8m_clk_composite(dev, "enet_timer", imx8mq_enet_timer_sels,
 				   base + 0xaa00));
 	clk_dm(IMX8MQ_CLK_ENET_PHY_REF,
-	       imx8m_clk_composite("enet_phy", imx8mq_enet_phy_sels,
+	       imx8m_clk_composite(dev, "enet_phy", imx8mq_enet_phy_sels,
 				   base + 0xaa80));
 	clk_dm(IMX8MQ_CLK_ENET1_ROOT,
-	       imx_clk_gate4("enet1_root_clk", "enet_axi",
+	       imx_clk_gate4(dev, "enet1_root_clk", "enet_axi",
 			     base + 0x40a0, 0));
 
 	clk_dm(IMX8MQ_CLK_DRAM_ALT_ROOT,
-	       imx_clk_fixed_factor("dram_alt_root", "dram_alt", 1, 4));
+	       imx_clk_fixed_factor(dev, "dram_alt_root", "dram_alt", 1, 4));
 
 	return 0;
 }
diff --git a/drivers/clk/imx/clk-imx93.c b/drivers/clk/imx/clk-imx93.c
index b31e57a4a01..c3112968c17 100644
--- a/drivers/clk/imx/clk-imx93.c
+++ b/drivers/clk/imx/clk-imx93.c
@@ -291,15 +291,15 @@ static int imx93_clk_probe(struct udevice *dev)
 	clk_dm(IMX93_CLK_SYS_PLL_PFD0,
 	       clk_register_fixed_rate(NULL, "sys_pll_pfd0", 1000000000));
 	clk_dm(IMX93_CLK_SYS_PLL_PFD0_DIV2,
-	       imx_clk_fixed_factor("sys_pll_pfd0_div2", "sys_pll_pfd0", 1, 2));
+	       imx_clk_fixed_factor(dev, "sys_pll_pfd0_div2", "sys_pll_pfd0", 1, 2));
 	clk_dm(IMX93_CLK_SYS_PLL_PFD1,
 	       clk_register_fixed_rate(NULL, "sys_pll_pfd1", 800000000));
 	clk_dm(IMX93_CLK_SYS_PLL_PFD1_DIV2,
-	       imx_clk_fixed_factor("sys_pll_pfd1_div2", "sys_pll_pfd1", 1, 2));
+	       imx_clk_fixed_factor(dev, "sys_pll_pfd1_div2", "sys_pll_pfd1", 1, 2));
 	clk_dm(IMX93_CLK_SYS_PLL_PFD2,
 	       clk_register_fixed_rate(NULL, "sys_pll_pfd2", 625000000));
 	clk_dm(IMX93_CLK_SYS_PLL_PFD2_DIV2,
-	       imx_clk_fixed_factor("sys_pll_pfd2_div2", "sys_pll_pfd2", 1, 2));
+	       imx_clk_fixed_factor(dev, "sys_pll_pfd2_div2", "sys_pll_pfd2", 1, 2));
 
 	anatop_base = (void *)ANATOP_BASE_ADDR;
 
@@ -338,7 +338,7 @@ static int imx93_clk_probe(struct udevice *dev)
 	}
 
 	clk_dm(IMX93_CLK_A55_SEL,
-	       imx_clk_mux2("a55_sel", base + 0x4820, 0, 1,
+	       imx_clk_mux2(dev, "a55_sel", base + 0x4820, 0, 1,
 			    a55_core_sels, ARRAY_SIZE(a55_core_sels)));
 
 	return 0;
diff --git a/drivers/clk/imx/clk-imxrt1020.c b/drivers/clk/imx/clk-imxrt1020.c
index 752434cb0ad..c14afdaf236 100644
--- a/drivers/clk/imx/clk-imxrt1020.c
+++ b/drivers/clk/imx/clk-imxrt1020.c
@@ -38,26 +38,26 @@ static int imxrt1020_clk_probe(struct udevice *dev)
 	base = (void *)ofnode_get_addr(ofnode_by_compatible(ofnode_null(), "fsl,imxrt-anatop"));
 
 	clk_dm(IMXRT1020_CLK_PLL2_SYS,
-	       imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll2_sys", "osc",
+	       imx_clk_pllv3(dev, IMX_PLLV3_GENERIC, "pll2_sys", "osc",
 			     base + 0x30, 0x1));
 	clk_dm(IMXRT1020_CLK_PLL3_USB_OTG,
-	       imx_clk_pllv3(IMX_PLLV3_USB, "pll3_usb_otg", "osc",
+	       imx_clk_pllv3(dev, IMX_PLLV3_USB, "pll3_usb_otg", "osc",
 			     base + 0x10, 0x1));
 
 	/* PLL bypass out */
 	clk_dm(IMXRT1020_CLK_PLL2_BYPASS,
-	       imx_clk_mux_flags("pll2_bypass", base + 0x30, 16, 1,
+	       imx_clk_mux_flags(dev, "pll2_bypass", base + 0x30, 16, 1,
 				 pll2_bypass_sels,
 				 ARRAY_SIZE(pll2_bypass_sels),
 				 CLK_SET_RATE_PARENT));
 	clk_dm(IMXRT1020_CLK_PLL3_BYPASS,
-	       imx_clk_mux_flags("pll3_bypass", base + 0x10, 16, 1,
+	       imx_clk_mux_flags(dev, "pll3_bypass", base + 0x10, 16, 1,
 				 pll3_bypass_sels,
 				 ARRAY_SIZE(pll3_bypass_sels),
 				 CLK_SET_RATE_PARENT));
 
 	clk_dm(IMXRT1020_CLK_PLL3_80M,
-	       imx_clk_fixed_factor("pll3_80m",  "pll3_usb_otg",   1, 6));
+	       imx_clk_fixed_factor(dev, "pll3_80m",  "pll3_usb_otg",   1, 6));
 
 	clk_dm(IMXRT1020_CLK_PLL2_PFD0_352M,
 	       imx_clk_pfd("pll2_pfd0_352m", "pll2_sys", base + 0x100, 0));
@@ -78,51 +78,51 @@ static int imxrt1020_clk_probe(struct udevice *dev)
 		return -EINVAL;
 
 	clk_dm(IMXRT1020_CLK_PRE_PERIPH_SEL,
-	       imx_clk_mux("pre_periph_sel", base + 0x18, 18, 2,
+	       imx_clk_mux(dev, "pre_periph_sel", base + 0x18, 18, 2,
 			   pre_periph_sels, ARRAY_SIZE(pre_periph_sels)));
 	clk_dm(IMXRT1020_CLK_PERIPH_SEL,
-	       imx_clk_mux("periph_sel", base + 0x14, 25, 1,
+	       imx_clk_mux(dev, "periph_sel", base + 0x14, 25, 1,
 			   periph_sels, ARRAY_SIZE(periph_sels)));
 	clk_dm(IMXRT1020_CLK_USDHC1_SEL,
-	       imx_clk_mux("usdhc1_sel", base + 0x1c, 16, 1,
+	       imx_clk_mux(dev, "usdhc1_sel", base + 0x1c, 16, 1,
 			   usdhc_sels, ARRAY_SIZE(usdhc_sels)));
 	clk_dm(IMXRT1020_CLK_USDHC2_SEL,
-	       imx_clk_mux("usdhc2_sel", base + 0x1c, 17, 1,
+	       imx_clk_mux(dev, "usdhc2_sel", base + 0x1c, 17, 1,
 			   usdhc_sels, ARRAY_SIZE(usdhc_sels)));
 	clk_dm(IMXRT1020_CLK_LPUART_SEL,
-	       imx_clk_mux("lpuart_sel", base + 0x24, 6, 1,
+	       imx_clk_mux(dev, "lpuart_sel", base + 0x24, 6, 1,
 			   lpuart_sels, ARRAY_SIZE(lpuart_sels)));
 	clk_dm(IMXRT1020_CLK_SEMC_ALT_SEL,
-	       imx_clk_mux("semc_alt_sel", base + 0x14, 7, 1,
+	       imx_clk_mux(dev, "semc_alt_sel", base + 0x14, 7, 1,
 			   semc_alt_sels, ARRAY_SIZE(semc_alt_sels)));
 	clk_dm(IMXRT1020_CLK_SEMC_SEL,
-	       imx_clk_mux("semc_sel", base + 0x14, 6, 1,
+	       imx_clk_mux(dev, "semc_sel", base + 0x14, 6, 1,
 			   semc_sels, ARRAY_SIZE(semc_sels)));
 
 	clk_dm(IMXRT1020_CLK_AHB_PODF,
-	       imx_clk_divider("ahb_podf", "periph_sel",
+	       imx_clk_divider(dev, "ahb_podf", "periph_sel",
 			       base + 0x14, 10, 3));
 	clk_dm(IMXRT1020_CLK_USDHC1_PODF,
-	       imx_clk_divider("usdhc1_podf", "usdhc1_sel",
+	       imx_clk_divider(dev, "usdhc1_podf", "usdhc1_sel",
 			       base + 0x24, 11, 3));
 	clk_dm(IMXRT1020_CLK_USDHC2_PODF,
-	       imx_clk_divider("usdhc2_podf", "usdhc2_sel",
+	       imx_clk_divider(dev, "usdhc2_podf", "usdhc2_sel",
 			       base + 0x24, 16, 3));
 	clk_dm(IMXRT1020_CLK_LPUART_PODF,
-	       imx_clk_divider("lpuart_podf", "lpuart_sel",
+	       imx_clk_divider(dev, "lpuart_podf", "lpuart_sel",
 			       base + 0x24, 0, 6));
 	clk_dm(IMXRT1020_CLK_SEMC_PODF,
-	       imx_clk_divider("semc_podf", "semc_sel",
+	       imx_clk_divider(dev, "semc_podf", "semc_sel",
 			       base + 0x14, 16, 3));
 
 	clk_dm(IMXRT1020_CLK_USDHC1,
-	       imx_clk_gate2("usdhc1", "usdhc1_podf", base + 0x80, 2));
+	       imx_clk_gate2(dev, "usdhc1", "usdhc1_podf", base + 0x80, 2));
 	clk_dm(IMXRT1020_CLK_USDHC2,
-	       imx_clk_gate2("usdhc2", "usdhc2_podf", base + 0x80, 4));
+	       imx_clk_gate2(dev, "usdhc2", "usdhc2_podf", base + 0x80, 4));
 	clk_dm(IMXRT1020_CLK_LPUART1,
-	       imx_clk_gate2("lpuart1", "lpuart_podf", base + 0x7c, 24));
+	       imx_clk_gate2(dev, "lpuart1", "lpuart_podf", base + 0x7c, 24));
 	clk_dm(IMXRT1020_CLK_SEMC,
-	       imx_clk_gate2("semc", "semc_podf", base + 0x74, 4));
+	       imx_clk_gate2(dev, "semc", "semc_podf", base + 0x74, 4));
 
 #ifdef CONFIG_XPL_BUILD
 	struct clk *clk, *clk1;
diff --git a/drivers/clk/imx/clk-imxrt1050.c b/drivers/clk/imx/clk-imxrt1050.c
index 2c029ec5a6e..ba5b48748ef 100644
--- a/drivers/clk/imx/clk-imxrt1050.c
+++ b/drivers/clk/imx/clk-imxrt1050.c
@@ -36,63 +36,63 @@ static int imxrt1050_clk_probe(struct udevice *dev)
 	base = (void *)ofnode_get_addr(ofnode_by_compatible(ofnode_null(), "fsl,imxrt-anatop"));
 
 	clk_dm(IMXRT1050_CLK_PLL1_REF_SEL,
-	       imx_clk_mux("pll1_arm_ref_sel", base + 0x0, 14, 2,
+	       imx_clk_mux(dev, "pll1_arm_ref_sel", base + 0x0, 14, 2,
 			   pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
 	clk_dm(IMXRT1050_CLK_PLL2_REF_SEL,
-	       imx_clk_mux("pll2_sys_ref_sel", base + 0x30, 14, 2,
+	       imx_clk_mux(dev, "pll2_sys_ref_sel", base + 0x30, 14, 2,
 			   pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
 	clk_dm(IMXRT1050_CLK_PLL3_REF_SEL,
-	       imx_clk_mux("pll3_usb_otg_ref_sel", base + 0x10, 14, 2,
+	       imx_clk_mux(dev, "pll3_usb_otg_ref_sel", base + 0x10, 14, 2,
 			   pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
 	clk_dm(IMXRT1050_CLK_PLL5_REF_SEL,
-	       imx_clk_mux("pll5_video_ref_sel", base + 0xa0, 14, 2,
+	       imx_clk_mux(dev, "pll5_video_ref_sel", base + 0xa0, 14, 2,
 			   pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
 
 	clk_dm(IMXRT1050_CLK_PLL1_ARM,
-	       imx_clk_pllv3(IMX_PLLV3_SYS, "pll1_arm", "pll1_arm_ref_sel",
+	       imx_clk_pllv3(dev, IMX_PLLV3_SYS, "pll1_arm", "pll1_arm_ref_sel",
 			     base + 0x0, 0x7f));
 	clk_dm(IMXRT1050_CLK_PLL2_SYS,
-	       imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll2_sys", "pll2_sys_ref_sel",
+	       imx_clk_pllv3(dev, IMX_PLLV3_GENERIC, "pll2_sys", "pll2_sys_ref_sel",
 			     base + 0x30, 0x1));
 	clk_dm(IMXRT1050_CLK_PLL3_USB_OTG,
-	       imx_clk_pllv3(IMX_PLLV3_USB, "pll3_usb_otg",
+	       imx_clk_pllv3(dev, IMX_PLLV3_USB, "pll3_usb_otg",
 			     "pll3_usb_otg_ref_sel",
 			     base + 0x10, 0x1));
 	clk_dm(IMXRT1050_CLK_PLL5_VIDEO,
-	       imx_clk_pllv3(IMX_PLLV3_AV, "pll5_video", "pll5_video_ref_sel",
+	       imx_clk_pllv3(dev, IMX_PLLV3_AV, "pll5_video", "pll5_video_ref_sel",
 			     base + 0xa0, 0x7f));
 
 	/* PLL bypass out */
 	clk_dm(IMXRT1050_CLK_PLL1_BYPASS,
-	       imx_clk_mux_flags("pll1_bypass", base + 0x0, 16, 1,
+	       imx_clk_mux_flags(dev, "pll1_bypass", base + 0x0, 16, 1,
 				 pll1_bypass_sels,
 				 ARRAY_SIZE(pll1_bypass_sels),
 				 CLK_SET_RATE_PARENT));
 	clk_dm(IMXRT1050_CLK_PLL2_BYPASS,
-	       imx_clk_mux_flags("pll2_bypass", base + 0x30, 16, 1,
+	       imx_clk_mux_flags(dev, "pll2_bypass", base + 0x30, 16, 1,
 				 pll2_bypass_sels,
 				 ARRAY_SIZE(pll2_bypass_sels),
 				 CLK_SET_RATE_PARENT));
 	clk_dm(IMXRT1050_CLK_PLL3_BYPASS,
-	       imx_clk_mux_flags("pll3_bypass", base + 0x10, 16, 1,
+	       imx_clk_mux_flags(dev, "pll3_bypass", base + 0x10, 16, 1,
 				 pll3_bypass_sels,
 				 ARRAY_SIZE(pll3_bypass_sels),
 				 CLK_SET_RATE_PARENT));
 	clk_dm(IMXRT1050_CLK_PLL5_BYPASS,
-	       imx_clk_mux_flags("pll5_bypass", base + 0xa0, 16, 1,
+	       imx_clk_mux_flags(dev, "pll5_bypass", base + 0xa0, 16, 1,
 				 pll5_bypass_sels,
 				 ARRAY_SIZE(pll5_bypass_sels),
 				 CLK_SET_RATE_PARENT));
 
 	clk_dm(IMXRT1050_CLK_VIDEO_POST_DIV_SEL,
-	       imx_clk_divider("video_post_div_sel", "pll5_video",
+	       imx_clk_divider(dev, "video_post_div_sel", "pll5_video",
 			       base + 0xa0, 19, 2));
 	clk_dm(IMXRT1050_CLK_VIDEO_DIV,
-	       imx_clk_divider("video_div", "video_post_div_sel",
+	       imx_clk_divider(dev, "video_div", "video_post_div_sel",
 			       base + 0x170, 30, 2));
 
 	clk_dm(IMXRT1050_CLK_PLL3_80M,
-	       imx_clk_fixed_factor("pll3_80m",  "pll3_usb_otg",   1, 6));
+	       imx_clk_fixed_factor(dev, "pll3_80m",  "pll3_usb_otg",   1, 6));
 
 	clk_dm(IMXRT1050_CLK_PLL2_PFD0_352M,
 	       imx_clk_pfd("pll2_pfd0_352m", "pll2_sys", base + 0x100, 0));
@@ -113,73 +113,73 @@ static int imxrt1050_clk_probe(struct udevice *dev)
 		return -EINVAL;
 
 	clk_dm(IMXRT1050_CLK_ARM_PODF,
-	       imx_clk_divider("arm_podf", "pll1_arm",
+	       imx_clk_divider(dev, "arm_podf", "pll1_arm",
 			       base + 0x10, 0, 3));
 
 	clk_dm(IMXRT1050_CLK_PRE_PERIPH_SEL,
-	       imx_clk_mux("pre_periph_sel", base + 0x18, 18, 2,
+	       imx_clk_mux(dev, "pre_periph_sel", base + 0x18, 18, 2,
 			   pre_periph_sels, ARRAY_SIZE(pre_periph_sels)));
 	clk_dm(IMXRT1050_CLK_PERIPH_SEL,
-	       imx_clk_mux("periph_sel", base + 0x14, 25, 1,
+	       imx_clk_mux(dev, "periph_sel", base + 0x14, 25, 1,
 			   periph_sels, ARRAY_SIZE(periph_sels)));
 	clk_dm(IMXRT1050_CLK_USDHC1_SEL,
-	       imx_clk_mux("usdhc1_sel", base + 0x1c, 16, 1,
+	       imx_clk_mux(dev, "usdhc1_sel", base + 0x1c, 16, 1,
 			   usdhc_sels, ARRAY_SIZE(usdhc_sels)));
 	clk_dm(IMXRT1050_CLK_USDHC2_SEL,
-	       imx_clk_mux("usdhc2_sel", base + 0x1c, 17, 1,
+	       imx_clk_mux(dev, "usdhc2_sel", base + 0x1c, 17, 1,
 			   usdhc_sels, ARRAY_SIZE(usdhc_sels)));
 	clk_dm(IMXRT1050_CLK_LPUART_SEL,
-	       imx_clk_mux("lpuart_sel", base + 0x24, 6, 1,
+	       imx_clk_mux(dev, "lpuart_sel", base + 0x24, 6, 1,
 			   lpuart_sels, ARRAY_SIZE(lpuart_sels)));
 	clk_dm(IMXRT1050_CLK_SEMC_ALT_SEL,
-	       imx_clk_mux("semc_alt_sel", base + 0x14, 7, 1,
+	       imx_clk_mux(dev, "semc_alt_sel", base + 0x14, 7, 1,
 			   semc_alt_sels, ARRAY_SIZE(semc_alt_sels)));
 	clk_dm(IMXRT1050_CLK_SEMC_SEL,
-	       imx_clk_mux("semc_sel", base + 0x14, 6, 1,
+	       imx_clk_mux(dev, "semc_sel", base + 0x14, 6, 1,
 			   semc_sels, ARRAY_SIZE(semc_sels)));
 	clk_dm(IMXRT1050_CLK_LCDIF_SEL,
-	       imx_clk_mux("lcdif_sel", base + 0x38, 15, 3,
+	       imx_clk_mux(dev, "lcdif_sel", base + 0x38, 15, 3,
 			   lcdif_sels, ARRAY_SIZE(lcdif_sels)));
 
 	clk_dm(IMXRT1050_CLK_AHB_PODF,
-	       imx_clk_divider("ahb_podf", "periph_sel",
+	       imx_clk_divider(dev, "ahb_podf", "periph_sel",
 			       base + 0x14, 10, 3));
 	clk_dm(IMXRT1050_CLK_IPG_PDOF,
-	       imx_clk_divider("ipg_podf", "ahb_podf",
+	       imx_clk_divider(dev, "ipg_podf", "ahb_podf",
 			       base + 0x14, 8, 2));
 	clk_dm(IMXRT1050_CLK_USDHC1_PODF,
-	       imx_clk_divider("usdhc1_podf", "usdhc1_sel",
+	       imx_clk_divider(dev, "usdhc1_podf", "usdhc1_sel",
 			       base + 0x24, 11, 3));
 	clk_dm(IMXRT1050_CLK_USDHC2_PODF,
-	       imx_clk_divider("usdhc2_podf", "usdhc2_sel",
+	       imx_clk_divider(dev, "usdhc2_podf", "usdhc2_sel",
 			       base + 0x24, 16, 3));
 	clk_dm(IMXRT1050_CLK_LPUART_PODF,
-	       imx_clk_divider("lpuart_podf", "lpuart_sel",
+	       imx_clk_divider(dev, "lpuart_podf", "lpuart_sel",
 			       base + 0x24, 0, 6));
 	clk_dm(IMXRT1050_CLK_SEMC_PODF,
-	       imx_clk_divider("semc_podf", "semc_sel",
+	       imx_clk_divider(dev, "semc_podf", "semc_sel",
 			       base + 0x14, 16, 3));
 	clk_dm(IMXRT1050_CLK_LCDIF_PRED,
-	       imx_clk_divider("lcdif_pred", "lcdif_sel",
+	       imx_clk_divider(dev, "lcdif_pred", "lcdif_sel",
 			       base + 0x38, 12, 3));
 	clk_dm(IMXRT1050_CLK_LCDIF_PODF,
-	       imx_clk_divider("lcdif_podf", "lcdif_pred",
+	       imx_clk_divider(dev, "lcdif_podf", "lcdif_pred",
 			       base + 0x18, 23, 3));
 
 	clk_dm(IMXRT1050_CLK_USDHC1,
-	       imx_clk_gate2("usdhc1", "usdhc1_podf", base + 0x80, 2));
+	       imx_clk_gate2(dev, "usdhc1", "usdhc1_podf", base + 0x80, 2));
 	clk_dm(IMXRT1050_CLK_USDHC2,
-	       imx_clk_gate2("usdhc2", "usdhc2_podf", base + 0x80, 4));
+	       imx_clk_gate2(dev, "usdhc2", "usdhc2_podf", base + 0x80, 4));
 	clk_dm(IMXRT1050_CLK_LPUART1,
-	       imx_clk_gate2("lpuart1", "lpuart_podf", base + 0x7c, 24));
+	       imx_clk_gate2(dev, "lpuart1", "lpuart_podf", base + 0x7c, 24));
 	clk_dm(IMXRT1050_CLK_SEMC,
-	       imx_clk_gate2("semc", "semc_podf", base + 0x74, 4));
+	       imx_clk_gate2(dev, "semc", "semc_podf", base + 0x74, 4));
 	clk_dm(IMXRT1050_CLK_LCDIF_APB,
-	       imx_clk_gate2("lcdif", "lcdif_podf", base + 0x70, 28));
+	       imx_clk_gate2(dev, "lcdif", "lcdif_podf", base + 0x70, 28));
 	clk_dm(IMXRT1050_CLK_LCDIF_PIX,
-	       imx_clk_gate2("lcdif_pix", "lcdif", base + 0x74, 10));
+	       imx_clk_gate2(dev, "lcdif_pix", "lcdif", base + 0x74, 10));
 	clk_dm(IMXRT1050_CLK_USBOH3,
-	       imx_clk_gate2("usboh3", "pll3_usb_otg", base + 0x80, 0));
+	       imx_clk_gate2(dev, "usboh3", "pll3_usb_otg", base + 0x80, 0));
 
 	struct clk *clk, *clk1;
 
diff --git a/drivers/clk/imx/clk-imxrt1170.c b/drivers/clk/imx/clk-imxrt1170.c
index 88a294f4165..3f55d0d0127 100644
--- a/drivers/clk/imx/clk-imxrt1170.c
+++ b/drivers/clk/imx/clk-imxrt1170.c
@@ -114,20 +114,20 @@ static int imxrt1170_clk_probe(struct udevice *dev)
 	base = (void *)ofnode_get_addr(ofnode_by_compatible(ofnode_null(), "fsl,imxrt-anatop"));
 
 	clk_dm(IMXRT1170_CLK_RCOSC_48M,
-	       imx_clk_fixed_factor("rcosc48M", "rcosc16M", 3, 1));
+	       imx_clk_fixed_factor(dev, "rcosc48M", "rcosc16M", 3, 1));
 	clk_dm(IMXRT1170_CLK_RCOSC_400M,
-	       imx_clk_fixed_factor("rcosc400M",  "rcosc16M", 25, 1));
+	       imx_clk_fixed_factor(dev, "rcosc400M",  "rcosc16M", 25, 1));
 	clk_dm(IMXRT1170_CLK_RCOSC_48M_DIV2,
-	       imx_clk_fixed_factor("rcosc48M_div2",  "rcosc48M", 1, 2));
+	       imx_clk_fixed_factor(dev, "rcosc48M_div2",  "rcosc48M", 1, 2));
 
 	clk_dm(IMXRT1170_CLK_PLL_ARM,
-	       imx_clk_pllv3(IMX_PLLV3_SYS, "pll_arm", "osc",
+	       imx_clk_pllv3(dev, IMX_PLLV3_SYS, "pll_arm", "osc",
 			     base + 0x200, 0xff));
 	clk_dm(IMXRT1170_CLK_PLL3,
-	       imx_clk_pllv3(IMX_PLLV3_GENERICV2, "pll3_sys", "osc",
+	       imx_clk_pllv3(dev, IMX_PLLV3_GENERICV2, "pll3_sys", "osc",
 			     base + 0x210, 1));
 	clk_dm(IMXRT1170_CLK_PLL2,
-	       imx_clk_pllv3(IMX_PLLV3_GENERICV2, "pll2_sys", "osc",
+	       imx_clk_pllv3(dev, IMX_PLLV3_GENERICV2, "pll2_sys", "osc",
 			     base + 0x240, 1));
 
 	clk_dm(IMXRT1170_CLK_PLL3_PFD0,
@@ -149,7 +149,7 @@ static int imxrt1170_clk_probe(struct udevice *dev)
 	       imx_clk_pfd("pll2_pfd3", "pll2_sys", base + 0x270, 3));
 
 	clk_dm(IMXRT1170_CLK_PLL3_DIV2,
-	       imx_clk_fixed_factor("pll3_div2", "pll3_sys", 1, 2));
+	       imx_clk_fixed_factor(dev, "pll3_div2", "pll3_sys", 1, 2));
 
 	/* CCM clocks */
 	base = dev_read_addr_ptr(dev);
@@ -157,31 +157,31 @@ static int imxrt1170_clk_probe(struct udevice *dev)
 		return -EINVAL;
 
 	clk_dm(IMXRT1170_CLK_LPUART1_SEL,
-	       imx_clk_mux("lpuart1_sel", base + (25 * 0x80), 8, 3,
+	       imx_clk_mux(dev, "lpuart1_sel", base + (25 * 0x80), 8, 3,
 			   lpuart1_sels, ARRAY_SIZE(lpuart1_sels)));
 	clk_dm(IMXRT1170_CLK_LPUART1,
-	       imx_clk_divider("lpuart1", "lpuart1_sel",
+	       imx_clk_divider(dev, "lpuart1", "lpuart1_sel",
 			       base + (25 * 0x80), 0, 8));
 
 	clk_dm(IMXRT1170_CLK_USDHC1_SEL,
-	       imx_clk_mux("usdhc1_sel", base + (58 * 0x80), 8, 3,
+	       imx_clk_mux(dev, "usdhc1_sel", base + (58 * 0x80), 8, 3,
 			   usdhc1_sels, ARRAY_SIZE(usdhc1_sels)));
 	clk_dm(IMXRT1170_CLK_USDHC1,
-	       imx_clk_divider("usdhc1", "usdhc1_sel",
+	       imx_clk_divider(dev, "usdhc1", "usdhc1_sel",
 			       base + (58 * 0x80), 0, 8));
 
 	clk_dm(IMXRT1170_CLK_GPT1_SEL,
-	       imx_clk_mux("gpt1_sel", base + (14 * 0x80), 8, 3,
+	       imx_clk_mux(dev, "gpt1_sel", base + (14 * 0x80), 8, 3,
 			   gpt1_sels, ARRAY_SIZE(gpt1_sels)));
 	clk_dm(IMXRT1170_CLK_GPT1,
-	       imx_clk_divider("gpt1", "gpt1_sel",
+	       imx_clk_divider(dev, "gpt1", "gpt1_sel",
 			       base + (14 * 0x80), 0, 8));
 
 	clk_dm(IMXRT1170_CLK_SEMC_SEL,
-	       imx_clk_mux("semc_sel", base + (4 * 0x80), 8, 3,
+	       imx_clk_mux(dev, "semc_sel", base + (4 * 0x80), 8, 3,
 			   semc_sels, ARRAY_SIZE(semc_sels)));
 	clk_dm(IMXRT1170_CLK_SEMC,
-	       imx_clk_divider("semc", "semc_sel",
+	       imx_clk_divider(dev, "semc", "semc_sel",
 			       base + (4 * 0x80), 0, 8));
 	struct clk *clk, *clk1;
 
diff --git a/drivers/clk/imx/clk-pllv3.c b/drivers/clk/imx/clk-pllv3.c
index c6692f2f9f5..85b6a9809e8 100644
--- a/drivers/clk/imx/clk-pllv3.c
+++ b/drivers/clk/imx/clk-pllv3.c
@@ -281,9 +281,9 @@ static const struct clk_ops clk_pllv3_enet_ops = {
 	.get_rate	= clk_pllv3_enet_get_rate,
 };
 
-struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name,
-			  const char *parent_name, void __iomem *base,
-			  u32 div_mask)
+struct clk *imx_clk_pllv3(struct udevice *dev, enum imx_pllv3_type type,
+			  const char *name, const char *parent_name,
+			  void __iomem *base, u32 div_mask)
 {
 	struct clk_pllv3 *pll;
 	struct clk *clk;
@@ -339,7 +339,8 @@ struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name,
 	pll->div_mask = div_mask;
 	clk = &pll->clk;
 
-	ret = clk_register(clk, drv_name, name, parent_name);
+	ret = clk_register(clk, drv_name, name,
+			   clk_resolve_parent_clk(dev, parent_name));
 	if (ret) {
 		kfree(pll);
 		return ERR_PTR(ret);
diff --git a/drivers/clk/imx/clk.h b/drivers/clk/imx/clk.h
index 27a53ae5583..7d14dbc395f 100644
--- a/drivers/clk/imx/clk.h
+++ b/drivers/clk/imx/clk.h
@@ -78,84 +78,89 @@ struct clk *imx_clk_pll14xx(const char *name, const char *parent_name,
 			    void __iomem *base,
 			    const struct imx_pll14xx_clk *pll_clk);
 
-struct clk *clk_register_gate2(struct device *dev, const char *name,
+struct clk *clk_register_gate2(struct udevice *dev, const char *name,
 		const char *parent_name, unsigned long flags,
 		void __iomem *reg, u8 bit_idx, u8 cgr_val,
 		u8 clk_gate_flags, unsigned int *share_count);
 
-struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name,
-			  const char *parent_name, void __iomem *base,
-			  u32 div_mask);
+struct clk *imx_clk_pllv3(struct udevice *dev, enum imx_pllv3_type type,
+			  const char *name, const char *parent_name,
+			  void __iomem *base, u32 div_mask);
 
-static inline struct clk *imx_clk_gate2(const char *name, const char *parent,
-					void __iomem *reg, u8 shift)
+static inline struct clk *imx_clk_gate2(struct udevice *dev, const char *name,
+					const char *parent, void __iomem *reg,
+					u8 shift)
 {
-	return clk_register_gate2(NULL, name, parent, CLK_SET_RATE_PARENT, reg,
+	return clk_register_gate2(dev, name, parent, CLK_SET_RATE_PARENT, reg,
 			shift, 0x3, 0, NULL);
 }
 
-static inline struct clk *imx_clk_gate2_shared(const char *name,
+static inline struct clk *imx_clk_gate2_shared(struct udevice *dev, const char *name,
 					       const char *parent,
 					       void __iomem *reg, u8 shift,
 					       unsigned int *share_count)
 {
-	return clk_register_gate2(NULL, name, parent, CLK_SET_RATE_PARENT, reg,
+	return clk_register_gate2(dev, name, parent, CLK_SET_RATE_PARENT, reg,
 				  shift, 0x3, 0, share_count);
 }
 
-static inline struct clk *imx_clk_gate2_shared2(const char *name,
+static inline struct clk *imx_clk_gate2_shared2(struct udevice *dev, const char *name,
 						const char *parent,
 						void __iomem *reg, u8 shift,
 						unsigned int *share_count)
 {
-	return clk_register_gate2(NULL, name, parent, CLK_SET_RATE_PARENT |
+	return clk_register_gate2(dev, name, parent, CLK_SET_RATE_PARENT |
 				  CLK_OPS_PARENT_ENABLE, reg, shift, 0x3, 0,
 				  share_count);
 }
 
-static inline struct clk *imx_clk_gate4(const char *name, const char *parent,
+static inline struct clk *imx_clk_gate4(struct udevice *dev, const char *name, const char *parent,
 		void __iomem *reg, u8 shift)
 {
-	return clk_register_gate2(NULL, name, parent,
+	return clk_register_gate2(dev, name, parent,
 			CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
 			reg, shift, 0x3, 0, NULL);
 }
 
-static inline struct clk *imx_clk_gate4_flags(const char *name,
+static inline struct clk *imx_clk_gate4_flags(struct udevice *dev, const char *name,
 		const char *parent, void __iomem *reg, u8 shift,
 		unsigned long flags)
 {
-	return clk_register_gate2(NULL, name, parent,
+	return clk_register_gate2(dev, name, parent,
 			flags | CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
 			reg, shift, 0x3, 0, NULL);
 }
 
-static inline struct clk *imx_clk_fixed_factor(const char *name,
-		const char *parent, unsigned int mult, unsigned int div)
+static inline struct clk *
+imx_clk_fixed_factor(struct udevice *dev, const char *name, const char *parent,
+		     unsigned int mult, unsigned int div)
 {
-	return clk_register_fixed_factor(NULL, name, parent,
+	return clk_register_fixed_factor(dev, name, parent,
 			CLK_SET_RATE_PARENT, mult, div);
 }
 
-static inline struct clk *imx_clk_divider(const char *name, const char *parent,
-		void __iomem *reg, u8 shift, u8 width)
+static inline struct clk *imx_clk_divider(struct udevice *dev, const char *name,
+					  const char *parent, void __iomem *reg,
+					  u8 shift, u8 width)
 {
-	return clk_register_divider(NULL, name, parent, CLK_SET_RATE_PARENT,
+	return clk_register_divider(dev, name, parent, CLK_SET_RATE_PARENT,
 			reg, shift, width, 0);
 }
 
 static inline struct clk *
-imx_clk_busy_divider(const char *name, const char *parent, void __iomem *reg,
-		     u8 shift, u8 width, void __iomem *busy_reg, u8 busy_shift)
+imx_clk_busy_divider(struct udevice *dev, const char *name,
+		     const char *parent, void __iomem *reg, u8 shift, u8 width,
+		     void __iomem *busy_reg, u8 busy_shift)
 {
-	return clk_register_divider(NULL, name, parent, CLK_SET_RATE_PARENT,
+	return clk_register_divider(dev, name, parent, CLK_SET_RATE_PARENT,
 			reg, shift, width, 0);
 }
 
-static inline struct clk *imx_clk_divider2(const char *name, const char *parent,
-		void __iomem *reg, u8 shift, u8 width)
+static inline struct clk *imx_clk_divider2(struct udevice *dev, const char *name,
+					   const char *parent, void __iomem *reg,
+					   u8 shift, u8 width)
 {
-	return clk_register_divider(NULL, name, parent,
+	return clk_register_divider(dev, name, parent,
 			CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
 			reg, shift, width, 0);
 }
@@ -167,90 +172,93 @@ struct clk *imx_clk_fixup_mux(const char *name, void __iomem *reg,
 			      u8 shift, u8 width, const char * const *parents,
 			      int num_parents, void (*fixup)(u32 *val));
 
-static inline struct clk *imx_clk_mux_flags(const char *name,
+static inline struct clk *imx_clk_mux_flags(struct udevice *dev, const char *name,
 			void __iomem *reg, u8 shift, u8 width,
 			const char * const *parents, int num_parents,
 			unsigned long flags)
 {
-	return clk_register_mux(NULL, name, parents, num_parents,
+	return clk_register_mux(dev, name, parents, num_parents,
 				flags | CLK_SET_RATE_NO_REPARENT, reg, shift,
 				width, 0);
 }
 
-static inline struct clk *imx_clk_mux2_flags(const char *name,
+static inline struct clk *imx_clk_mux2_flags(struct udevice *dev, const char *name,
 		void __iomem *reg, u8 shift, u8 width,
 		const char * const *parents,
 		int num_parents, unsigned long flags)
 {
-	return clk_register_mux(NULL, name, parents, num_parents,
+	return clk_register_mux(dev, name, parents, num_parents,
 			flags | CLK_SET_RATE_NO_REPARENT | CLK_OPS_PARENT_ENABLE,
 			reg, shift, width, 0);
 }
 
-static inline struct clk *imx_clk_mux(const char *name, void __iomem *reg,
-			u8 shift, u8 width, const char * const *parents,
+static inline struct clk *imx_clk_mux(struct udevice *dev, const char *name,
+			void __iomem *reg, u8 shift, u8 width, const char * const *parents,
 			int num_parents)
 {
-	return clk_register_mux(NULL, name, parents, num_parents,
+	return clk_register_mux(dev, name, parents, num_parents,
 			CLK_SET_RATE_NO_REPARENT, reg, shift,
 			width, 0);
 }
 
 static inline struct clk *
-imx_clk_busy_mux(const char *name, void __iomem *reg, u8 shift, u8 width,
+imx_clk_busy_mux(struct udevice *dev, const char *name, void __iomem *reg, u8 shift, u8 width,
 		 void __iomem *busy_reg, u8 busy_shift,
 		 const char * const *parents, int num_parents)
 {
-	return clk_register_mux(NULL, name, parents, num_parents,
+	return clk_register_mux(dev, name, parents, num_parents,
 			CLK_SET_RATE_NO_REPARENT, reg, shift,
 			width, 0);
 }
 
-static inline struct clk *imx_clk_mux2(const char *name, void __iomem *reg,
+static inline struct clk *imx_clk_mux2(struct udevice *dev, const char *name, void __iomem *reg,
 			u8 shift, u8 width, const char * const *parents,
 			int num_parents)
 {
-	return clk_register_mux(NULL, name, parents, num_parents,
+	return clk_register_mux(dev, name, parents, num_parents,
 			CLK_SET_RATE_NO_REPARENT | CLK_OPS_PARENT_ENABLE,
 			reg, shift, width, 0);
 }
 
-static inline struct clk *imx_clk_gate(const char *name, const char *parent,
-		void __iomem *reg, u8 shift)
+static inline struct clk *imx_clk_gate(struct udevice *dev, const char *name,
+				       const char *parent, void __iomem *reg,
+				       u8 shift)
 {
-	return clk_register_gate(NULL, name, parent, CLK_SET_RATE_PARENT, reg,
+	return clk_register_gate(dev, name, parent, CLK_SET_RATE_PARENT, reg,
 			shift, 0, NULL);
 }
 
-static inline struct clk *imx_clk_gate_flags(const char *name, const char *parent,
-		void __iomem *reg, u8 shift, unsigned long flags)
+static inline struct clk *imx_clk_gate_flags(struct udevice *dev, const char *name,
+					     const char *parent, void __iomem *reg,
+					     u8 shift, unsigned long flags)
 {
-	return clk_register_gate(NULL, name, parent, flags | CLK_SET_RATE_PARENT, reg,
+	return clk_register_gate(dev, name, parent, flags | CLK_SET_RATE_PARENT, reg,
 			shift, 0, NULL);
 }
 
-static inline struct clk *imx_clk_gate3(const char *name, const char *parent,
-		void __iomem *reg, u8 shift)
+static inline struct clk *imx_clk_gate3(struct udevice *dev, const char *name,
+					const char *parent, void __iomem *reg,
+					u8 shift)
 {
-	return clk_register_gate(NULL, name, parent,
+	return clk_register_gate(dev, name, parent,
 			CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
 			reg, shift, 0, NULL);
 }
 
-struct clk *imx8m_clk_composite_flags(const char *name,
+struct clk *imx8m_clk_composite_flags(struct udevice *dev, const char *name,
 		const char * const *parent_names,
 		int num_parents, void __iomem *reg, unsigned long flags);
 
-#define __imx8m_clk_composite(name, parent_names, reg, flags) \
-	imx8m_clk_composite_flags(name, parent_names, \
+#define __imx8m_clk_composite(dev, name, parent_names, reg, flags) \
+	imx8m_clk_composite_flags(dev, name, parent_names, \
 		ARRAY_SIZE(parent_names), reg, \
 		flags | CLK_SET_RATE_NO_REPARENT | CLK_OPS_PARENT_ENABLE)
 
-#define imx8m_clk_composite(name, parent_names, reg) \
-	__imx8m_clk_composite(name, parent_names, reg, 0)
+#define imx8m_clk_composite(dev, name, parent_names, reg) \
+	__imx8m_clk_composite(dev, name, parent_names, reg, 0)
 
-#define imx8m_clk_composite_critical(name, parent_names, reg) \
-	__imx8m_clk_composite(name, parent_names, reg, CLK_IS_CRITICAL)
+#define imx8m_clk_composite_critical(dev, name, parent_names, reg) \
+	__imx8m_clk_composite(dev, name, parent_names, reg, CLK_IS_CRITICAL)
 
 struct clk *imx93_clk_composite_flags(const char *name,
 				      const char * const *parent_names,
diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
index e412c92cafc..12893687b68 100644
--- a/drivers/clk/mediatek/Makefile
+++ b/drivers/clk/mediatek/Makefile
@@ -3,7 +3,6 @@
 obj-$(CONFIG_ARCH_MEDIATEK) += clk-mtk.o
 
 # SoC Drivers
-obj-$(CONFIG_MT8512) += clk-mt8512.o
 obj-$(CONFIG_TARGET_MT7623) += clk-mt7623.o
 obj-$(CONFIG_TARGET_MT7622) += clk-mt7622.o
 obj-$(CONFIG_TARGET_MT7629) += clk-mt7629.o
@@ -13,5 +12,6 @@ obj-$(CONFIG_TARGET_MT7988) += clk-mt7988.o
 obj-$(CONFIG_TARGET_MT7987) += clk-mt7987.o
 obj-$(CONFIG_TARGET_MT8183) += clk-mt8183.o
 obj-$(CONFIG_TARGET_MT8365) += clk-mt8365.o
+obj-$(CONFIG_TARGET_MT8512) += clk-mt8512.o
 obj-$(CONFIG_TARGET_MT8516) += clk-mt8516.o
 obj-$(CONFIG_TARGET_MT8518) += clk-mt8518.o
diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
index cb867acc48c..3ea01f3c969 100644
--- a/drivers/clk/qcom/Kconfig
+++ b/drivers/clk/qcom/Kconfig
@@ -31,6 +31,14 @@ config CLK_QCOM_IPQ4019
 	  on the Snapdragon IPQ4019 SoC. This driver supports the clocks
 	  and resets exposed by the GCC hardware block.
 
+config CLK_QCOM_IPQ9574
+	bool "Qualcomm IPQ9574 GCC"
+	select CLK_QCOM
+	help
+	  Say Y here to enable support for the Global Clock Controller
+	  on the Snapdragon IPQ9574 SoC. This driver supports the clocks
+	  and resets exposed by the GCC hardware block.
+
 config CLK_QCOM_QCM2290
 	bool "Qualcomm QCM2290 GCC"
 	select CLK_QCOM
diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
index 1bc0f15005b..e13fc8c1071 100644
--- a/drivers/clk/qcom/Makefile
+++ b/drivers/clk/qcom/Makefile
@@ -7,6 +7,7 @@ obj-$(CONFIG_CLK_QCOM_SDM845) += clock-sdm845.o
 obj-$(CONFIG_CLK_QCOM_APQ8016) += clock-apq8016.o
 obj-$(CONFIG_CLK_QCOM_APQ8096) += clock-apq8096.o
 obj-$(CONFIG_CLK_QCOM_IPQ4019) += clock-ipq4019.o
+obj-$(CONFIG_CLK_QCOM_IPQ9574) += clock-ipq9574.o
 obj-$(CONFIG_CLK_QCOM_QCM2290) += clock-qcm2290.o
 obj-$(CONFIG_CLK_QCOM_QCS404) += clock-qcs404.o
 obj-$(CONFIG_CLK_QCOM_SA8775P) += clock-sa8775p.o
diff --git a/drivers/clk/qcom/clock-apq8016.c b/drivers/clk/qcom/clock-apq8016.c
index b5def55dbc2..6a53f900a9e 100644
--- a/drivers/clk/qcom/clock-apq8016.c
+++ b/drivers/clk/qcom/clock-apq8016.c
@@ -54,8 +54,9 @@ static struct vote_clk gcc_blsp1_ahb_clk = {
 };
 
 static const struct gate_clk apq8016_clks[] = {
-	GATE_CLK(GCC_USB_HS_AHB_CLK,    0x41008, 0x00000001),
-	GATE_CLK(GCC_USB_HS_SYSTEM_CLK,	0x41004, 0x00000001),
+	GATE_CLK(GCC_PRNG_AHB_CLK,	0x45004, BIT(8)),
+	GATE_CLK(GCC_USB_HS_AHB_CLK,    0x41008, BIT(0)),
+	GATE_CLK(GCC_USB_HS_SYSTEM_CLK,	0x41004, BIT(0)),
 };
 
 /* SDHCI */
@@ -139,15 +140,14 @@ static int apq8016_clk_enable(struct clk *clk)
 {
 	struct msm_clk_priv *priv = dev_get_priv(clk->dev);
 
-	if (priv->data->num_clks < clk->id) {
+	if (priv->data->num_clks < clk->id || !apq8016_clks[clk->id].reg) {
 		log_warning("%s: unknown clk id %lu\n", __func__, clk->id);
 		return 0;
 	}
 
-	debug("%s: clk %s\n", __func__, apq8016_clks[clk->id].name);
-	qcom_gate_clk_en(priv, clk->id);
+	debug("%s: enabling clock %s\n", __func__, apq8016_clks[clk->id].name);
 
-	return 0;
+	return qcom_gate_clk_en(priv, clk->id);
 }
 
 static struct msm_clk_data apq8016_clk_data = {
diff --git a/drivers/clk/qcom/clock-ipq9574.c b/drivers/clk/qcom/clock-ipq9574.c
new file mode 100644
index 00000000000..b0af4036059
--- /dev/null
+++ b/drivers/clk/qcom/clock-ipq9574.c
@@ -0,0 +1,94 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Clock drivers for Qualcomm ipq9574
+ *
+ * (C) Copyright 2025 Linaro Ltd.
+ */
+
+#include <linux/types.h>
+#include <clk-uclass.h>
+#include <dm.h>
+#include <linux/delay.h>
+#include <asm/io.h>
+#include <linux/bug.h>
+#include <linux/bitops.h>
+#include <dt-bindings/clock/qcom,ipq9574-gcc.h>
+#include <dt-bindings/reset/qcom,ipq9574-gcc.h>
+
+#include "clock-qcom.h"
+
+#define GCC_BLSP1_AHB_CBCR			0x1004
+#define GCC_BLSP1_UART3_APPS_CMD_RCGR		0x402C
+#define GCC_BLSP1_UART3_APPS_CBCR		0x4054
+
+#define GCC_SDCC1_APPS_CBCR			0x3302C
+#define GCC_SDCC1_AHB_CBCR			0x33034
+#define GCC_SDCC1_APPS_CMD_RCGR			0x33004
+#define GCC_SDCC1_ICE_CORE_CBCR			0x33030
+
+static ulong ipq9574_set_rate(struct clk *clk, ulong rate)
+{
+	struct msm_clk_priv *priv = dev_get_priv(clk->dev);
+
+	switch (clk->id) {
+	case GCC_BLSP1_UART3_APPS_CLK:
+		clk_rcg_set_rate_mnd(priv->base, GCC_BLSP1_UART3_APPS_CMD_RCGR,
+				     0, 144, 15625, CFG_CLK_SRC_GPLL0, 16);
+		return rate;
+	case GCC_SDCC1_APPS_CLK:
+		clk_rcg_set_rate_mnd(priv->base, GCC_SDCC1_APPS_CMD_RCGR,
+				     11, 0, 0, CFG_CLK_SRC_GPLL2, 16);
+		return rate;
+	default:
+		return -EINVAL;
+	}
+}
+
+static const struct gate_clk ipq9574_clks[] = {
+	GATE_CLK(GCC_BLSP1_UART3_APPS_CLK,	 0x4054, 0x00000001),
+	GATE_CLK(GCC_BLSP1_AHB_CLK,		 0x1004, 0x00000001),
+	GATE_CLK(GCC_SDCC1_AHB_CLK,		0x33034, 0x00000001),
+	GATE_CLK(GCC_SDCC1_APPS_CLK,		0x3302C, 0x00000001),
+	GATE_CLK(GCC_SDCC1_ICE_CORE_CLK,	0x33030, 0x00000001),
+};
+
+static int ipq9574_enable(struct clk *clk)
+{
+	struct msm_clk_priv *priv = dev_get_priv(clk->dev);
+
+	debug("%s: clk %s\n", __func__, ipq9574_clks[clk->id].name);
+
+	if (!ipq9574_clks[clk->id].reg)
+		return -EINVAL;
+
+	qcom_gate_clk_en(priv, clk->id);
+
+	return 0;
+}
+
+static const struct qcom_reset_map ipq9574_gcc_resets[] = {
+	[GCC_SDCC_BCR] = { 0x33000 },
+};
+
+static struct msm_clk_data ipq9574_gcc_data = {
+	.resets = ipq9574_gcc_resets,
+	.num_resets = ARRAY_SIZE(ipq9574_gcc_resets),
+	.enable = ipq9574_enable,
+	.set_rate = ipq9574_set_rate,
+};
+
+static const struct udevice_id gcc_ipq9574_of_match[] = {
+	{
+		.compatible = "qcom,ipq9574-gcc",
+		.data = (ulong)&ipq9574_gcc_data,
+	},
+	{ }
+};
+
+U_BOOT_DRIVER(gcc_ipq9574) = {
+	.name		= "gcc_ipq9574",
+	.id		= UCLASS_NOP,
+	.of_match	= gcc_ipq9574_of_match,
+	.bind		= qcom_cc_bind,
+	.flags		= DM_FLAG_PRE_RELOC | DM_FLAG_DEFAULT_PD_CTRL_OFF,
+};
diff --git a/drivers/clk/qcom/clock-qcm2290.c b/drivers/clk/qcom/clock-qcm2290.c
index c78705cb8cf..1326b770c3e 100644
--- a/drivers/clk/qcom/clock-qcm2290.c
+++ b/drivers/clk/qcom/clock-qcm2290.c
@@ -134,9 +134,7 @@ static int qcm2290_enable(struct clk *clk)
 		break;
 	}
 
-	qcom_gate_clk_en(priv, clk->id);
-
-	return 0;
+	return qcom_gate_clk_en(priv, clk->id);
 }
 
 static const struct qcom_reset_map qcm2290_gcc_resets[] = {
diff --git a/drivers/clk/qcom/clock-qcom.h b/drivers/clk/qcom/clock-qcom.h
index ff336dea39c..f43edea2525 100644
--- a/drivers/clk/qcom/clock-qcom.h
+++ b/drivers/clk/qcom/clock-qcom.h
@@ -7,10 +7,12 @@
 
 #include <asm/io.h>
 #include <linux/bitfield.h>
+#include <errno.h>
 
 #define CFG_CLK_SRC_CXO   (0 << 8)
 #define CFG_CLK_SRC_GPLL0 (1 << 8)
 #define CFG_CLK_SRC_GPLL0_AUX2 (2 << 8)
+#define CFG_CLK_SRC_GPLL2 (2 << 8)
 #define CFG_CLK_SRC_GPLL9 (2 << 8)
 #define CFG_CLK_SRC_GPLL0_ODD (3 << 8)
 #define CFG_CLK_SRC_GPLL6 (4 << 8)
@@ -105,14 +107,19 @@ void clk_rcg_set_rate(phys_addr_t base, uint32_t cmd_rcgr, int div,
 		      int source);
 void clk_phy_mux_enable(phys_addr_t base, uint32_t cmd_rcgr, bool enabled);
 
-static inline void qcom_gate_clk_en(const struct msm_clk_priv *priv, unsigned long id)
+static inline int qcom_gate_clk_en(const struct msm_clk_priv *priv, unsigned long id)
 {
 	u32 val;
-	if (id >= priv->data->num_clks || priv->data->clks[id].reg == 0)
-		return;
+	if (id >= priv->data->num_clks || priv->data->clks[id].reg == 0) {
+		log_err("gcc@%#08llx: unknown clock ID %lu!\n",
+			priv->base, id);
+		return -ENOENT;
+	}
 
 	val = readl(priv->base + priv->data->clks[id].reg);
 	writel(val | priv->data->clks[id].en_val, priv->base + priv->data->clks[id].reg);
+
+	return 0;
 }
 
 #endif
diff --git a/drivers/clk/qcom/clock-sa8775p.c b/drivers/clk/qcom/clock-sa8775p.c
index e31f24ed4f0..527cecf5c82 100644
--- a/drivers/clk/qcom/clock-sa8775p.c
+++ b/drivers/clk/qcom/clock-sa8775p.c
@@ -73,9 +73,7 @@ static int sa8775p_enable(struct clk *clk)
 		break;
 	}
 
-	qcom_gate_clk_en(priv, clk->id);
-
-	return 0;
+	return qcom_gate_clk_en(priv, clk->id);
 }
 
 static const struct qcom_reset_map sa8775p_gcc_resets[] = {
diff --git a/drivers/clk/qcom/clock-sc7280.c b/drivers/clk/qcom/clock-sc7280.c
index 5d343f12051..8691f08109b 100644
--- a/drivers/clk/qcom/clock-sc7280.c
+++ b/drivers/clk/qcom/clock-sc7280.c
@@ -16,29 +16,64 @@
 
 #include "clock-qcom.h"
 
-#define USB30_PRIM_MOCK_UTMI_CLK_CMD_RCGR 0xf038
 #define USB30_PRIM_MASTER_CLK_CMD_RCGR 0xf020
+#define USB30_PRIM_MOCK_UTMI_CLK_CMD_RCGR 0xf038
+#define USB30_SEC_MASTER_CLK_CMD_RCGR 0x9e020
+#define USB30_SEC_MOCK_UTMI_CLK_CMD_RCGR 0x9e038
+#define PCIE_1_AUX_CLK_CMD_RCGR 0x8d058
+#define PCIE1_PHY_RCHNG_CMD_RCGR 0x8d03c
+#define PCIE_1_PIPE_CLK_PHY_MUX 0x8d054
+
+static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] = {
+	F(66666667, CFG_CLK_SRC_GPLL0_EVEN, 4.5, 0, 0),
+	F(133333333, CFG_CLK_SRC_GPLL0, 4.5, 0, 0),
+	F(200000000, CFG_CLK_SRC_GPLL0_ODD, 1, 0, 0),
+	F(240000000, CFG_CLK_SRC_GPLL0, 2.5, 0, 0),
+	{ }
+};
+
+static const struct freq_tbl ftbl_gcc_usb30_sec_master_clk_src[] = {
+	F(60000000, CFG_CLK_SRC_GPLL0_EVEN, 5, 0, 0),
+	F(120000000, CFG_CLK_SRC_GPLL0_EVEN, 2.5, 0, 0),
+	{ }
+};
 
 static ulong sc7280_set_rate(struct clk *clk, ulong rate)
 {
 	struct msm_clk_priv *priv = dev_get_priv(clk->dev);
+	const struct freq_tbl *freq;
 
 	if (clk->id < priv->data->num_clks)
 		debug("%s: %s, requested rate=%ld\n", __func__, priv->data->clks[clk->id].name, rate);
 
 	switch (clk->id) {
-	case GCC_USB30_PRIM_MOCK_UTMI_CLK:
-		WARN(rate != 19200000, "Unexpected rate for USB30_PRIM_MOCK_UTMI_CLK: %lu\n", rate);
-		clk_rcg_set_rate(priv->base, USB30_PRIM_MASTER_CLK_CMD_RCGR, 0, CFG_CLK_SRC_CXO);
-		return rate;
 	case GCC_USB30_PRIM_MASTER_CLK:
-		WARN(rate != 200000000, "Unexpected rate for USB30_PRIM_MASTER_CLK: %lu\n", rate);
+		freq = qcom_find_freq(ftbl_gcc_usb30_prim_master_clk_src, rate);
 		clk_rcg_set_rate_mnd(priv->base, USB30_PRIM_MASTER_CLK_CMD_RCGR,
-				     1, 0, 0, CFG_CLK_SRC_GPLL0_ODD, 8);
-		clk_rcg_set_rate(priv->base, 0xf064, 0, 0);
-		return rate;
+				     freq->pre_div, freq->m, freq->n, freq->src, 8);
+		return freq->freq;
+	case GCC_USB30_PRIM_MOCK_UTMI_CLK:
+		clk_rcg_set_rate(priv->base, USB30_PRIM_MOCK_UTMI_CLK_CMD_RCGR, 1, 0);
+		return 19200000;
+	case GCC_USB3_PRIM_PHY_AUX_CLK_SRC:
+		clk_rcg_set_rate(priv->base, USB30_PRIM_MOCK_UTMI_CLK_CMD_RCGR, 1, 0);
+		return 19200000;
+	case GCC_USB30_SEC_MASTER_CLK:
+		freq = qcom_find_freq(ftbl_gcc_usb30_sec_master_clk_src, rate);
+		clk_rcg_set_rate_mnd(priv->base, USB30_SEC_MASTER_CLK_CMD_RCGR,
+				     freq->pre_div, freq->m, freq->n, freq->src, 8);
+		return freq->freq;
+	case GCC_USB30_SEC_MOCK_UTMI_CLK:
+		clk_rcg_set_rate(priv->base, USB30_SEC_MOCK_UTMI_CLK_CMD_RCGR, 1, 0);
+		return 19200000;
+	case GCC_USB3_SEC_PHY_AUX_CLK_SRC:
+		clk_rcg_set_rate(priv->base, USB30_PRIM_MOCK_UTMI_CLK_CMD_RCGR, 1, 0);
+		return 19200000;
+	case GCC_PCIE1_PHY_RCHNG_CLK:
+		clk_rcg_set_rate(priv->base, PCIE1_PHY_RCHNG_CMD_RCGR, 5, CFG_CLK_SRC_GPLL0_EVEN);
+		return 100000000;
 	default:
-		return 0;
+		return rate;
 	}
 }
 
@@ -50,13 +85,35 @@ static const struct gate_clk sc7280_clks[] = {
 	GATE_CLK(GCC_USB30_PRIM_MOCK_UTMI_CLK, 0xf01c, 1),
 	GATE_CLK(GCC_USB3_PRIM_PHY_AUX_CLK, 0xf054, 1),
 	GATE_CLK(GCC_USB3_PRIM_PHY_COM_AUX_CLK, 0xf058, 1),
+	GATE_CLK(GCC_CFG_NOC_USB3_SEC_AXI_CLK, 0x9e07c, 1),
+	GATE_CLK(GCC_USB30_SEC_MASTER_CLK, 0x9e010, 1),
+	GATE_CLK(GCC_AGGRE_USB3_SEC_AXI_CLK, 0x9e080, 1),
+	GATE_CLK(GCC_USB30_SEC_SLEEP_CLK, 0x9e018, 1),
+	GATE_CLK(GCC_USB30_SEC_MOCK_UTMI_CLK, 0x9e01c, 1),
+	GATE_CLK(GCC_USB3_SEC_PHY_AUX_CLK, 0x9e054, 1),
+	GATE_CLK(GCC_USB3_SEC_PHY_COM_AUX_CLK, 0x9e058, 1),
+	GATE_CLK(GCC_PCIE_CLKREF_EN, 0x8c004, 1),
+	GATE_CLK(GCC_PCIE_1_PIPE_CLK, 0x52000, BIT(30)),
+	GATE_CLK(GCC_PCIE_1_AUX_CLK, 0x52000, BIT(29)),
+	GATE_CLK(GCC_PCIE_1_CFG_AHB_CLK, 0x52000, BIT(28)),
+	GATE_CLK(GCC_PCIE_1_MSTR_AXI_CLK, 0x52000, BIT(27)),
+	GATE_CLK(GCC_PCIE_1_SLV_AXI_CLK, 0x52000, BIT(26)),
+	GATE_CLK(GCC_PCIE_1_SLV_Q2A_AXI_CLK, 0x52000, BIT(25)),
+	GATE_CLK(GCC_PCIE1_PHY_RCHNG_CLK, 0x52000, BIT(23)),
+	GATE_CLK(GCC_DDRSS_PCIE_SF_CLK, 0x52000, BIT(19)),
+	GATE_CLK(GCC_AGGRE_NOC_PCIE_TBU_CLK, 0x52000, BIT(18)),
+	GATE_CLK(GCC_AGGRE_NOC_PCIE_1_AXI_CLK, 0x52000, BIT(11)),
+	GATE_CLK(GCC_AGGRE_NOC_PCIE_CENTER_SF_AXI_CLK, 0x52008, BIT(28)),
+	GATE_CLK(GCC_QUPV3_WRAP0_S0_CLK, 0x52008, BIT(10)),
+	GATE_CLK(GCC_QUPV3_WRAP0_S1_CLK, 0x52008, BIT(11)),
+	GATE_CLK(GCC_QUPV3_WRAP0_S3_CLK, 0x52008, BIT(13)),
 };
 
 static int sc7280_enable(struct clk *clk)
 {
 	struct msm_clk_priv *priv = dev_get_priv(clk->dev);
 
-	if (priv->data->num_clks < clk->id) {
+	if (priv->data->num_clks <= clk->id) {
 		debug("%s: unknown clk id %lu\n", __func__, clk->id);
 		return 0;
 	}
@@ -71,11 +128,32 @@ static int sc7280_enable(struct clk *clk)
 		qcom_gate_clk_en(priv, GCC_USB3_PRIM_PHY_AUX_CLK);
 		qcom_gate_clk_en(priv, GCC_USB3_PRIM_PHY_COM_AUX_CLK);
 		break;
+	case GCC_AGGRE_USB3_SEC_AXI_CLK:
+		qcom_gate_clk_en(priv, GCC_USB30_SEC_MASTER_CLK);
+		fallthrough;
+	case GCC_USB30_SEC_MASTER_CLK:
+		qcom_gate_clk_en(priv, GCC_USB3_SEC_PHY_AUX_CLK);
+		qcom_gate_clk_en(priv, GCC_USB3_SEC_PHY_COM_AUX_CLK);
+		break;
+	case GCC_PCIE_1_PIPE_CLK:
+		clk_phy_mux_enable(priv->base, PCIE_1_PIPE_CLK_PHY_MUX, true);
+		break;
+	case GCC_PCIE_1_AUX_CLK:
+		clk_rcg_set_rate_mnd(priv->base, PCIE_1_AUX_CLK_CMD_RCGR, 1, 0, 0,
+				     CFG_CLK_SRC_CXO, 16);
+		break;
+	case GCC_QUPV3_WRAP0_S0_CLK:
+		clk_rcg_set_rate_mnd(priv->base, 0x17010, 1, 0, 0, CFG_CLK_SRC_CXO, 16);
+		break;
+	case GCC_QUPV3_WRAP0_S1_CLK:
+		clk_rcg_set_rate_mnd(priv->base, 0x17140, 1, 0, 0, CFG_CLK_SRC_CXO, 16);
+		break;
+	case GCC_QUPV3_WRAP0_S3_CLK:
+		clk_rcg_set_rate_mnd(priv->base, 0x173a0, 1, 0, 0, CFG_CLK_SRC_CXO, 16);
+		break;
 	}
 
-	qcom_gate_clk_en(priv, clk->id);
-
-	return 0;
+	return qcom_gate_clk_en(priv, clk->id);
 }
 
 static const struct qcom_reset_map sc7280_gcc_resets[] = {
@@ -100,6 +178,20 @@ static const struct qcom_reset_map sc7280_gcc_resets[] = {
 static const struct qcom_power_map sc7280_gdscs[] = {
 	[GCC_UFS_PHY_GDSC] = { 0x77004 },
 	[GCC_USB30_PRIM_GDSC] = { 0xf004 },
+	[GCC_USB30_SEC_GDSC] = { 0x9e004 },
+	[GCC_PCIE_1_GDSC] = { 0x8d004 },
+};
+
+static const phys_addr_t sc7280_rcg_addrs[] = {
+	0x10f020, // USB30_PRIM_MASTER_CLK_CMD_RCGR
+	0x10f038, // USB30_PRIM_MOCK_UTMI_CLK_CMD_RCGR
+	0x18d058, // PCIE_1_AUX_CLK_CMD_RCGR
+};
+
+static const char *const sc7280_rcg_names[] = {
+	"USB30_PRIM_MASTER_CLK_SRC",
+	"USB30_PRIM_MOCK_UTMI_CLK_SRC",
+	"GCC_PCIE_1_AUX_CLK_SRC",
 };
 
 static struct msm_clk_data qcs404_gcc_data = {
@@ -113,6 +205,10 @@ static struct msm_clk_data qcs404_gcc_data = {
 
 	.enable = sc7280_enable,
 	.set_rate = sc7280_set_rate,
+
+	.dbg_rcg_addrs = sc7280_rcg_addrs,
+	.num_rcgs = ARRAY_SIZE(sc7280_rcg_addrs),
+	.dbg_rcg_names = sc7280_rcg_names,
 };
 
 static const struct udevice_id gcc_sc7280_of_match[] = {
diff --git a/drivers/clk/qcom/clock-sdm845.c b/drivers/clk/qcom/clock-sdm845.c
index adffb0cb240..6a0bf16ba2d 100644
--- a/drivers/clk/qcom/clock-sdm845.c
+++ b/drivers/clk/qcom/clock-sdm845.c
@@ -162,9 +162,7 @@ static int sdm845_clk_enable(struct clk *clk)
 		break;
 	}
 
-	qcom_gate_clk_en(priv, clk->id);
-
-	return 0;
+	return qcom_gate_clk_en(priv, clk->id);
 }
 
 static const struct qcom_reset_map sdm845_gcc_resets[] = {
diff --git a/drivers/clk/qcom/clock-sm6115.c b/drivers/clk/qcom/clock-sm6115.c
index 9057dfe0bb1..17c2e561758 100644
--- a/drivers/clk/qcom/clock-sm6115.c
+++ b/drivers/clk/qcom/clock-sm6115.c
@@ -146,9 +146,7 @@ static int sm6115_enable(struct clk *clk)
 		break;
 	}
 
-	qcom_gate_clk_en(priv, clk->id);
-
-	return 0;
+	return qcom_gate_clk_en(priv, clk->id);
 }
 
 static const struct qcom_reset_map sm6115_gcc_resets[] = {
diff --git a/drivers/clk/qcom/clock-sm8150.c b/drivers/clk/qcom/clock-sm8150.c
index 88f2e678f43..7dd0d56eb43 100644
--- a/drivers/clk/qcom/clock-sm8150.c
+++ b/drivers/clk/qcom/clock-sm8150.c
@@ -243,9 +243,7 @@ static int sm8150_clk_enable(struct clk *clk)
 		break;
 	};
 
-	qcom_gate_clk_en(priv, clk->id);
-
-	return 0;
+	return qcom_gate_clk_en(priv, clk->id);
 }
 
 static const struct qcom_reset_map sm8150_gcc_resets[] = {
diff --git a/drivers/clk/qcom/clock-sm8250.c b/drivers/clk/qcom/clock-sm8250.c
index e322a923a5c..26396847d85 100644
--- a/drivers/clk/qcom/clock-sm8250.c
+++ b/drivers/clk/qcom/clock-sm8250.c
@@ -195,9 +195,7 @@ static int sm8250_enable(struct clk *clk)
 		break;
 	}
 
-	qcom_gate_clk_en(priv, clk->id);
-
-	return 0;
+	return qcom_gate_clk_en(priv, clk->id);
 }
 
 static const struct qcom_reset_map sm8250_gcc_resets[] = {
diff --git a/drivers/clk/qcom/clock-sm8550.c b/drivers/clk/qcom/clock-sm8550.c
index 62b5a409e8e..7c06489b9c4 100644
--- a/drivers/clk/qcom/clock-sm8550.c
+++ b/drivers/clk/qcom/clock-sm8550.c
@@ -220,9 +220,7 @@ static int sm8550_enable(struct clk *clk)
 		break;
 	}
 
-	qcom_gate_clk_en(priv, clk->id);
-
-	return 0;
+	return qcom_gate_clk_en(priv, clk->id);
 }
 
 static const struct qcom_reset_map sm8550_gcc_resets[] = {
diff --git a/drivers/clk/qcom/clock-sm8650.c b/drivers/clk/qcom/clock-sm8650.c
index 9baaecb571f..364454644a6 100644
--- a/drivers/clk/qcom/clock-sm8650.c
+++ b/drivers/clk/qcom/clock-sm8650.c
@@ -217,9 +217,7 @@ static int sm8650_enable(struct clk *clk)
 		break;
 	}
 
-	qcom_gate_clk_en(priv, clk->id);
-
-	return 0;
+	return qcom_gate_clk_en(priv, clk->id);
 }
 
 static const struct qcom_reset_map sm8650_gcc_resets[] = {
diff --git a/drivers/clk/qcom/clock-x1e80100.c b/drivers/clk/qcom/clock-x1e80100.c
index bd9c6ed1c8a..542d6248d65 100644
--- a/drivers/clk/qcom/clock-x1e80100.c
+++ b/drivers/clk/qcom/clock-x1e80100.c
@@ -174,9 +174,7 @@ static int x1e80100_enable(struct clk *clk)
 		break;
 	}
 
-	qcom_gate_clk_en(priv, clk->id);
-
-	return 0;
+	return qcom_gate_clk_en(priv, clk->id);
 }
 
 static const struct qcom_reset_map x1e80100_gcc_resets[] = {
diff --git a/drivers/clk/renesas/rzg2l-cpg.c b/drivers/clk/renesas/rzg2l-cpg.c
index 3c5340df8ee..7fce1f70d13 100644
--- a/drivers/clk/renesas/rzg2l-cpg.c
+++ b/drivers/clk/renesas/rzg2l-cpg.c
@@ -70,17 +70,12 @@ static int rzg2l_cpg_clk_set(struct clk *clk, bool enable)
 	dev_dbg(clk->dev, "%s %s clock %u\n", enable ? "enable" : "disable",
 		is_mod_clk(clk->id) ? "module" : "core", cpg_clk_id);
 
-	if (!is_mod_clk(clk->id)) {
-		/*
-		 * Non-module clocks are always on. Ignore attempts to enable
-		 * them and reject attempts to disable them.
-		 */
-		if (enable)
-			return 0;
-
-		dev_err(clk->dev, "ID %lu is not a module clock\n", clk->id);
-		return -EINVAL;
-	}
+	/*
+	 * Non-module clocks are always on. Ignore attempts to enable or disable
+	 * them.
+	 */
+	if (!is_mod_clk(clk->id))
+		return 0;
 
 	for (i = 0; i < data->info->num_mod_clks; i++) {
 		if (data->info->mod_clks[i].id == cpg_clk_id) {
diff --git a/drivers/clk/sunxi/Kconfig b/drivers/clk/sunxi/Kconfig
index 8bdc0944896..f44db76c182 100644
--- a/drivers/clk/sunxi/Kconfig
+++ b/drivers/clk/sunxi/Kconfig
@@ -122,4 +122,11 @@ config CLK_SUN50I_A64
 	  This enables common clock driver support for platforms based
 	  on Allwinner A64 SoC.
 
+config CLK_SUN50I_A100
+	bool "Clock driver for Allwinner A100/A133"
+	default MACH_SUN50I_A133
+	help
+	  This enables common clock driver support for platforms based
+	  on Allwinner A100/A133 SoCs.
+
 endif # CLK_SUNXI
diff --git a/drivers/clk/sunxi/Makefile b/drivers/clk/sunxi/Makefile
index 90a277489dc..7ff71c756e0 100644
--- a/drivers/clk/sunxi/Makefile
+++ b/drivers/clk/sunxi/Makefile
@@ -24,3 +24,4 @@ obj-$(CONFIG_CLK_SUN50I_H6) += clk_h6.o
 obj-$(CONFIG_CLK_SUN50I_H6_R) += clk_h6_r.o
 obj-$(CONFIG_CLK_SUN50I_H616) += clk_h616.o
 obj-$(CONFIG_CLK_SUN50I_A64) += clk_a64.o
+obj-$(CONFIG_CLK_SUN50I_A100) += clk_a100.o
diff --git a/drivers/clk/sunxi/clk_a100.c b/drivers/clk/sunxi/clk_a100.c
new file mode 100644
index 00000000000..b641feb8612
--- /dev/null
+++ b/drivers/clk/sunxi/clk_a100.c
@@ -0,0 +1,102 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2023-2024 Arm Ltd.
+ */
+
+#include <clk/sunxi.h>
+#include <dt-bindings/clock/sun50i-a100-ccu.h>
+#include <dt-bindings/reset/sun50i-a100-ccu.h>
+#include <linux/bitops.h>
+
+static struct ccu_clk_gate a100_gates[] = {
+	[CLK_PLL_PERIPH0]	= GATE(0x020, BIT(31) | BIT(27)),
+
+	[CLK_APB1]		= GATE_DUMMY,
+
+	[CLK_DE]		= GATE(0x600, BIT(31)),
+	[CLK_BUS_DE]		= GATE(0x60c, BIT(0)),
+
+	[CLK_BUS_MMC0]		= GATE(0x84c, BIT(0)),
+	[CLK_BUS_MMC1]		= GATE(0x84c, BIT(1)),
+	[CLK_BUS_MMC2]		= GATE(0x84c, BIT(2)),
+
+	[CLK_BUS_UART0]		= GATE(0x90c, BIT(0)),
+	[CLK_BUS_UART1]		= GATE(0x90c, BIT(1)),
+	[CLK_BUS_UART2]		= GATE(0x90c, BIT(2)),
+	[CLK_BUS_UART3]		= GATE(0x90c, BIT(3)),
+	[CLK_BUS_UART4]		= GATE(0x90c, BIT(4)),
+
+	[CLK_BUS_I2C0]		= GATE(0x91c, BIT(0)),
+	[CLK_BUS_I2C1]		= GATE(0x91c, BIT(1)),
+	[CLK_BUS_I2C2]		= GATE(0x91c, BIT(2)),
+	[CLK_BUS_I2C3]		= GATE(0x91c, BIT(3)),
+
+	[CLK_SPI0]		= GATE(0x940, BIT(31)),
+	[CLK_SPI1]		= GATE(0x944, BIT(31)),
+	[CLK_SPI2]		= GATE(0x948, BIT(31)),
+
+	[CLK_BUS_SPI0]		= GATE(0x96c, BIT(0)),
+	[CLK_BUS_SPI1]		= GATE(0x96c, BIT(1)),
+	[CLK_BUS_SPI2]		= GATE(0x96c, BIT(2)),
+
+	[CLK_BUS_EMAC]		= GATE(0x97c, BIT(0)),
+
+	[CLK_USB_PHY0]		= GATE(0xa70, BIT(29)),
+	[CLK_USB_OHCI0]		= GATE(0xa70, BIT(31)),
+
+	[CLK_USB_PHY1]		= GATE(0xa74, BIT(29)),
+	[CLK_USB_OHCI1]		= GATE(0xa74, BIT(31)),
+
+	[CLK_BUS_OHCI0]		= GATE(0xa8c, BIT(0)),
+	[CLK_BUS_OHCI1]		= GATE(0xa8c, BIT(1)),
+	[CLK_BUS_EHCI0]		= GATE(0xa8c, BIT(4)),
+	[CLK_BUS_EHCI1]		= GATE(0xa8c, BIT(5)),
+	[CLK_BUS_OTG]		= GATE(0xa8c, BIT(8)),
+
+	[CLK_TCON_LCD]		= GATE(0xb60, BIT(31)),
+	[CLK_BUS_TCON_LCD]	= GATE(0xb7c, BIT(0)),
+};
+
+static struct ccu_reset a100_resets[] = {
+	[RST_BUS_DE]		= RESET(0x60c, BIT(16)),
+
+	[RST_BUS_MMC0]		= RESET(0x84c, BIT(16)),
+	[RST_BUS_MMC1]		= RESET(0x84c, BIT(17)),
+	[RST_BUS_MMC2]		= RESET(0x84c, BIT(18)),
+
+	[RST_BUS_UART0]		= RESET(0x90c, BIT(16)),
+	[RST_BUS_UART1]		= RESET(0x90c, BIT(17)),
+	[RST_BUS_UART2]		= RESET(0x90c, BIT(18)),
+	[RST_BUS_UART3]		= RESET(0x90c, BIT(19)),
+	[RST_BUS_UART4]		= RESET(0x90c, BIT(20)),
+
+	[RST_BUS_I2C0]		= RESET(0x91c, BIT(16)),
+	[RST_BUS_I2C1]		= RESET(0x91c, BIT(17)),
+	[RST_BUS_I2C2]		= RESET(0x91c, BIT(18)),
+	[RST_BUS_I2C3]		= RESET(0x91c, BIT(19)),
+
+	[RST_BUS_SPI0]		= RESET(0x96c, BIT(16)),
+	[RST_BUS_SPI1]		= RESET(0x96c, BIT(17)),
+	[RST_BUS_SPI2]		= RESET(0x96c, BIT(18)),
+
+	[RST_BUS_EMAC]		= RESET(0x97c, BIT(16)),
+
+	[RST_USB_PHY0]		= RESET(0xa70, BIT(30)),
+
+	[RST_USB_PHY1]		= RESET(0xa74, BIT(30)),
+
+	[RST_BUS_OHCI0]		= RESET(0xa8c, BIT(16)),
+	[RST_BUS_OHCI1]		= RESET(0xa8c, BIT(17)),
+	[RST_BUS_EHCI0]		= RESET(0xa8c, BIT(20)),
+	[RST_BUS_EHCI1]		= RESET(0xa8c, BIT(21)),
+	[RST_BUS_OTG]		= RESET(0xa8c, BIT(24)),
+
+	[RST_BUS_TCON_LCD]	= RESET(0xb7c, BIT(16)),
+};
+
+const struct ccu_desc a100_ccu_desc = {
+	.gates = a100_gates,
+	.resets = a100_resets,
+	.num_gates = ARRAY_SIZE(a100_gates),
+	.num_resets = ARRAY_SIZE(a100_resets),
+};
diff --git a/drivers/clk/sunxi/clk_sunxi.c b/drivers/clk/sunxi/clk_sunxi.c
index 2ef4f45dacf..e0765cbc6dc 100644
--- a/drivers/clk/sunxi/clk_sunxi.c
+++ b/drivers/clk/sunxi/clk_sunxi.c
@@ -122,6 +122,7 @@ extern const struct ccu_desc f1c100s_ccu_desc;
 extern const struct ccu_desc h3_ccu_desc;
 extern const struct ccu_desc h6_ccu_desc;
 extern const struct ccu_desc h616_ccu_desc;
+extern const struct ccu_desc a100_ccu_desc;
 extern const struct ccu_desc h6_r_ccu_desc;
 extern const struct ccu_desc r40_ccu_desc;
 extern const struct ccu_desc v3s_ccu_desc;
@@ -215,6 +216,10 @@ static const struct udevice_id sunxi_clk_ids[] = {
 	{ .compatible = "allwinner,sun50i-h616-r-ccu",
 	  .data = (ulong)&h6_r_ccu_desc },
 #endif
+#ifdef CONFIG_CLK_SUN50I_A100
+	{ .compatible = "allwinner,sun50i-a100-ccu",
+	  .data = (ulong)&a100_ccu_desc },
+#endif
 #ifdef CONFIG_CLK_SUNIV_F1C100S
 	{ .compatible = "allwinner,suniv-f1c100s-ccu",
 	  .data = (ulong)&f1c100s_ccu_desc },
diff --git a/drivers/clk/ti/clk-k3.c b/drivers/clk/ti/clk-k3.c
index bf65f573cb8..b38e559e45a 100644
--- a/drivers/clk/ti/clk-k3.c
+++ b/drivers/clk/ti/clk-k3.c
@@ -82,6 +82,8 @@ static const struct soc_attr ti_k3_soc_clk_data[] = {
 		.family = "J721E",
 		.data = &j721e_clk_platdata,
 	},
+#endif
+#if IS_ENABLED(CONFIG_SOC_K3_J7200)
 	{
 		.family = "J7200",
 		.data = &j7200_clk_platdata,
@@ -104,6 +106,10 @@ static const struct soc_attr ti_k3_soc_clk_data[] = {
 		.family = "J784S4",
 		.data = &j784s4_clk_platdata,
 	},
+	{
+		.family = "J742S2",
+		.data = &j784s4_clk_platdata,
+	},
 #endif
 	{ /* sentinel */ }
 };
diff --git a/drivers/core/Makefile b/drivers/core/Makefile
index 9ea57911f89..657e589c286 100644
--- a/drivers/core/Makefile
+++ b/drivers/core/Makefile
@@ -16,6 +16,6 @@ ifndef CONFIG_DM_DEV_READ_INLINE
 obj-$(CONFIG_OF_CONTROL) += read.o
 endif
 obj-$(CONFIG_$(XPL_)OF_PLATDATA) += read.o
-obj-$(CONFIG_OF_CONTROL) += of_extra.o ofnode.o read_extra.o
+obj-$(CONFIG_OF_CONTROL) += of_extra.o ofnode.o read_extra.o ofnode_graph.o
 
 ccflags-$(CONFIG_DM_DEBUG) += -DDEBUG
diff --git a/drivers/core/ofnode_graph.c b/drivers/core/ofnode_graph.c
new file mode 100644
index 00000000000..90c92af3258
--- /dev/null
+++ b/drivers/core/ofnode_graph.c
@@ -0,0 +1,217 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2025 Svyatoslav Ryhel <clamor95@gmail.com>
+ */
+
+#define LOG_CATEGORY	LOGC_DT
+
+#include <dm.h>
+#include <log.h>
+#include <dm/ofnode.h>
+#include <linux/err.h>
+
+/**
+ * ofnode_graph_get_endpoint_count() - get the number of endpoints in a device ofnode
+ * @parent: ofnode to the device containing ports and endpoints
+ *
+ * Return: count of endpoint of this device ofnode
+ */
+unsigned int ofnode_graph_get_endpoint_count(ofnode parent)
+{
+	ofnode ports, port, endpoint;
+	unsigned int num = 0;
+
+	/* Check if ports node exists */
+	ports = ofnode_find_subnode(parent, "ports");
+	if (ofnode_valid(ports))
+		parent = ports;
+
+	ofnode_for_each_subnode(port, parent) {
+		if (!strncmp(ofnode_get_name(port), "port", 4)) {
+			/* Port node can only contain endpoints */
+			ofnode_for_each_subnode(endpoint, port)
+				num++;
+		}
+	};
+
+	log_debug("%s: detected %d endpoints\n", __func__, num);
+
+	return num++;
+}
+
+/**
+ * ofnode_graph_get_port_count() - get the number of port in a device or ports ofnode
+ * @parent: ofnode to the device or ports node
+ *
+ * Return: count of port of this device or ports node
+ */
+unsigned int ofnode_graph_get_port_count(ofnode parent)
+{
+	ofnode ports, port;
+	unsigned int num = 0;
+
+	/* Check if ports node exists */
+	ports = ofnode_find_subnode(parent, "ports");
+	if (ofnode_valid(ports))
+		parent = ports;
+
+	ofnode_for_each_subnode(port, parent)
+		if (!strncmp(ofnode_get_name(port), "port", 4))
+			num++;
+
+	log_debug("%s: detected %d ports\n", __func__, num);
+
+	return num++;
+}
+
+/**
+ * ofnode_graph_get_port_by_id() - get the port matching a given id
+ * @parent: parent ofnode
+ * @id: id of the port
+ *
+ * Return: ofnode in given port.
+ */
+ofnode ofnode_graph_get_port_by_id(ofnode parent, u32 id)
+{
+	ofnode ports, port;
+	u32 port_id;
+
+	ports = ofnode_find_subnode(parent, "ports");
+	if (!ofnode_valid(ports))
+		return ofnode_null();
+
+	/* Check ports for node with desired id */
+	ofnode_for_each_subnode(port, ports) {
+		ofnode_read_u32(port, "reg", &port_id);
+		log_debug("%s: detected port %d\n", __func__, port_id);
+		if (port_id == id)
+			return port;
+	}
+
+	return ofnode_null();
+}
+
+/**
+ * ofnode_graph_get_endpoint_by_regs() - get the endpoint matching a given id
+ * @parent: parent ofnode
+ * @reg_id: id of the port
+ * @id: id for the endpoint
+ *
+ * Return: ofnode in given endpoint or ofnode_null() if not found.
+ * reg and port_reg are ignored when they are -1.
+ */
+ofnode ofnode_graph_get_endpoint_by_regs(ofnode parent, int reg_id, int id)
+{
+	ofnode port, endpoint;
+	u32 ep_id;
+
+	/* get the port to work with */
+	if (reg_id < 0)
+		port = ofnode_find_subnode(parent, "port");
+	else
+		port = ofnode_graph_get_port_by_id(parent, reg_id);
+
+	if (!ofnode_valid(port)) {
+		log_debug("%s: port node is not found\n", __func__);
+		return ofnode_null();
+	}
+
+	if (id < 0)
+		return ofnode_find_subnode(port, "endpoint");
+
+	/* Check endpoints for node with desired id */
+	ofnode_for_each_subnode(endpoint, port) {
+		ofnode_read_u32(endpoint, "reg", &ep_id);
+		log_debug("%s: detected endpoint %d\n", __func__, ep_id);
+		if (ep_id == id)
+			return endpoint;
+	}
+
+	return ofnode_null();
+}
+
+/**
+ * ofnode_graph_get_remote_endpoint() - get remote endpoint node
+ * @endpoint: ofnode of a local endpoint
+ *
+ * Return: Remote endpoint ofnode linked with local endpoint.
+ */
+ofnode ofnode_graph_get_remote_endpoint(ofnode endpoint)
+{
+	/* Get remote endpoint node. */
+	return ofnode_parse_phandle(endpoint, "remote-endpoint", 0);
+}
+
+/**
+ * ofnode_graph_get_port_parent() - get port's parent node
+ * @endpoint: ofnode of a local endpoint
+ *
+ * Return: device ofnode associated with endpoint
+ */
+ofnode ofnode_graph_get_port_parent(ofnode endpoint)
+{
+	ofnode port = ofnode_get_parent(endpoint);
+	ofnode parent = ofnode_get_parent(port);
+
+	/* check if we are on top level or in ports node */
+	if (!strcmp(ofnode_get_name(parent), "ports"))
+		parent = ofnode_get_parent(parent);
+
+	return parent;
+}
+
+/**
+ * ofnode_graph_get_remote_port_parent() - get remote port's parent ofnode
+ * @endpoint: ofnode of a local endpoint
+ *
+ * Return: device ofnode associated with endpoint linked to local endpoint.
+ */
+ofnode ofnode_graph_get_remote_port_parent(ofnode endpoint)
+{
+	ofnode remote_endpoint = ofnode_graph_get_remote_endpoint(endpoint);
+	if (!ofnode_valid(remote_endpoint)) {
+		log_debug("%s: remote endpoint is not found\n", __func__);
+		return ofnode_null();
+	}
+
+	return ofnode_graph_get_port_parent(remote_endpoint);
+}
+
+/**
+ * ofnode_graph_get_remote_port() - get remote port ofnode
+ * @endpoint: ofnode of a local endpoint
+ *
+ * Return: port ofnode associated with remote endpoint node linked
+ * to local endpoint.
+ */
+ofnode ofnode_graph_get_remote_port(ofnode endpoint)
+{
+	ofnode remote_endpoint = ofnode_graph_get_remote_endpoint(endpoint);
+	if (!ofnode_valid(remote_endpoint)) {
+		log_debug("%s: remote endpoint is not found\n", __func__);
+		return ofnode_null();
+	}
+
+	return ofnode_get_parent(remote_endpoint);
+}
+
+/**
+ * ofnode_graph_get_remote_node() - get remote parent ofnode for given port/endpoint
+ * @parent: parent ofnode containing graph port/endpoint
+ * @port: identifier (value of reg property) of the parent port ofnode
+ * @endpoint: identifier (value of reg property) of the endpoint ofnode
+ *
+ * Return: device ofnode associated with endpoint linked to local endpoint.
+ */
+ofnode ofnode_graph_get_remote_node(ofnode parent, int port, int endpoint)
+{
+	ofnode endpoint_ofnode;
+
+	endpoint_ofnode = ofnode_graph_get_endpoint_by_regs(parent, port, endpoint);
+	if (!ofnode_valid(endpoint_ofnode)) {
+		log_debug("%s: endpoint is not found\n", __func__);
+		return ofnode_null();
+	}
+
+	return ofnode_graph_get_remote_port_parent(endpoint_ofnode);
+}
diff --git a/drivers/cpu/imx8_cpu.c b/drivers/cpu/imx8_cpu.c
index 53d31b3c0bf..4e1eccaa5b0 100644
--- a/drivers/cpu/imx8_cpu.c
+++ b/drivers/cpu/imx8_cpu.c
@@ -35,11 +35,49 @@ static const char *get_imx_type_str(u32 imxtype)
 {
 	switch (imxtype) {
 	case MXC_CPU_IMX8MM:
-		return "8MM";
+		return "8MMQ";	/* Quad-core version of the imx8mm */
+	case MXC_CPU_IMX8MML:
+		return "8MMQL";	/* Quad-core Lite version of the imx8mm */
+	case MXC_CPU_IMX8MMD:
+		return "8MMD";	/* Dual-core version of the imx8mm */
+	case MXC_CPU_IMX8MMDL:
+		return "8MMDL";	/* Dual-core Lite version of the imx8mm */
+	case MXC_CPU_IMX8MMS:
+		return "8MMS";	/* Single-core version of the imx8mm */
+	case MXC_CPU_IMX8MMSL:
+		return "8MMSL";	/* Single-core Lite version of the imx8mm */
 	case MXC_CPU_IMX8MN:
-		return "8MN";
+		return "8MNano Quad"; /* Quad-core version */
+	case MXC_CPU_IMX8MND:
+		return "8MNano Dual"; /* Dual-core version */
+	case MXC_CPU_IMX8MNS:
+		return "8MNano Solo"; /* Single-core version */
+	case MXC_CPU_IMX8MNL:
+		return "8MNano QuadLite"; /* Quad-core Lite version */
+	case MXC_CPU_IMX8MNDL:
+		return "8MNano DualLite"; /* Dual-core Lite version */
+	case MXC_CPU_IMX8MNSL:
+		return "8MNano SoloLite";/* Single-core Lite version of the imx8mn */
+	case MXC_CPU_IMX8MNUQ:
+		return "8MNano UltraLite Quad";/* Quad-core UltraLite version of the imx8mn */
+	case MXC_CPU_IMX8MNUD:
+		return "8MNano UltraLite Dual";/* Dual-core UltraLite version of the imx8mn */
+	case MXC_CPU_IMX8MNUS:
+		return "8MNano UltraLite Solo";/* Single-core UltraLite version of the imx8mn */
 	case MXC_CPU_IMX8MP:
-		return "8MP";
+		return "8MP[8]";	/* Quad-core version of the imx8mp */
+	case MXC_CPU_IMX8MPD:
+		return "8MP Dual[3]";	/* Dual-core version of the imx8mp */
+	case MXC_CPU_IMX8MPL:
+		return "8MP Lite[4]";	/* Quad-core Lite version of the imx8mp */
+	case MXC_CPU_IMX8MP6:
+		return "8MP[6]";	/* Quad-core version of the imx8mp, NPU fused */
+	case MXC_CPU_IMX8MQ:
+		return "8MQ";	/* Quad-core version of the imx8mq */
+	case MXC_CPU_IMX8MQL:
+		return "8MQLite";	/* Quad-core Lite version of the imx8mq */
+	case MXC_CPU_IMX8MD:
+		return "8MD";	/* Dual-core version of the imx8mq */
 	case MXC_CPU_IMX8QXP:
 	case MXC_CPU_IMX8QXP_A0:
 		return "8QXP";
@@ -177,19 +215,19 @@ static int cpu_imx_get_desc(const struct udevice *dev, char *buf, int size)
 	ret = snprintf(buf, size, "NXP i.MX%s Rev%s %s at %u MHz",
 		       plat->type, plat->rev, plat->name, plat->freq_mhz);
 
-	if (IS_ENABLED(CONFIG_IMX9)) {
+	if (IS_ENABLED(CONFIG_IMX_TMU)) {
 		switch (get_cpu_temp_grade(&minc, &maxc)) {
 		case TEMP_AUTOMOTIVE:
-			grade = "Automotive temperature grade ";
+			grade = "Automotive temperature grade";
 			break;
 		case TEMP_INDUSTRIAL:
-			grade = "Industrial temperature grade ";
+			grade = "Industrial temperature grade";
 			break;
 		case TEMP_EXTCOMMERCIAL:
-			grade = "Extended Consumer temperature grade ";
+			grade = "Extended Consumer temperature grade";
 			break;
 		default:
-			grade = "Consumer temperature grade ";
+			grade = "Consumer temperature grade";
 			break;
 		}
 
diff --git a/drivers/ddr/altera/Makefile b/drivers/ddr/altera/Makefile
index c1d6a6b6c59..b19f3601813 100644
--- a/drivers/ddr/altera/Makefile
+++ b/drivers/ddr/altera/Makefile
@@ -4,7 +4,7 @@
 # Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 #
 # (C) Copyright 2010, Thomas Chou <thomas@wytron.com.tw>
-# Copyright (C) 2014-2021 Altera Corporation <www.altera.com>
+# Copyright (C) 2014-2025 Altera Corporation <www.altera.com>
 
 ifdef CONFIG_$(XPL_)ALTERA_SDRAM
 obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += sdram_gen5.o sequencer.o
@@ -12,4 +12,5 @@ obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += sdram_arria10.o
 obj-$(CONFIG_TARGET_SOCFPGA_STRATIX10) += sdram_soc64.o sdram_s10.o
 obj-$(CONFIG_TARGET_SOCFPGA_AGILEX) += sdram_soc64.o sdram_agilex.o
 obj-$(CONFIG_TARGET_SOCFPGA_N5X) += sdram_soc64.o sdram_n5x.o
+obj-$(CONFIG_TARGET_SOCFPGA_AGILEX5) += sdram_soc64.o sdram_agilex5.o iossm_mailbox.o
 endif
diff --git a/drivers/ddr/altera/iossm_mailbox.c b/drivers/ddr/altera/iossm_mailbox.c
new file mode 100644
index 00000000000..db9435db657
--- /dev/null
+++ b/drivers/ddr/altera/iossm_mailbox.c
@@ -0,0 +1,748 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2025 Altera Corporation <www.altera.com>
+ *
+ */
+
+#include <hang.h>
+#include <string.h>
+#include <wait_bit.h>
+#include <asm/arch/base_addr_soc64.h>
+#include <asm/io.h>
+#include <linux/bitfield.h>
+#include "iossm_mailbox.h"
+
+#define TIMEOUT_120000MS			120000
+#define TIMEOUT_60000MS				60000
+#define TIMEOUT					TIMEOUT_120000MS
+#define IOSSM_STATUS_CAL_SUCCESS		BIT(0)
+#define IOSSM_STATUS_CAL_FAIL			BIT(1)
+#define IOSSM_STATUS_CAL_BUSY			BIT(2)
+#define IOSSM_STATUS_COMMAND_RESPONSE_READY	BIT(0)
+#define IOSSM_CMD_RESPONSE_STATUS_OFFSET	0x45C
+#define IOSSM_CMD_RESPONSE_DATA_0_OFFSET	0x458
+#define IOSSM_CMD_RESPONSE_DATA_1_OFFSET	0x454
+#define IOSSM_CMD_RESPONSE_DATA_2_OFFSET	0x450
+#define IOSSM_CMD_REQ_OFFSET			0x43C
+#define IOSSM_CMD_PARAM_0_OFFSET		0x438
+#define IOSSM_CMD_PARAM_1_OFFSET		0x434
+#define IOSSM_CMD_PARAM_2_OFFSET		0x430
+#define IOSSM_CMD_PARAM_3_OFFSET		0x42C
+#define IOSSM_CMD_PARAM_4_OFFSET		0x428
+#define IOSSM_CMD_PARAM_5_OFFSET		0x424
+#define IOSSM_CMD_PARAM_6_OFFSET		0x420
+#define IOSSM_CMD_RESPONSE_DATA_SHORT_MASK	GENMASK(31, 16)
+#define IOSSM_CMD_RESPONSE_DATA_SHORT(n)	FIELD_GET(IOSSM_CMD_RESPONSE_DATA_SHORT_MASK, n)
+#define IOSSM_STATUS_CMD_RESPONSE_ERROR_MASK	GENMASK(7, 5)
+#define IOSSM_STATUS_CMD_RESPONSE_ERROR(n)	FIELD_GET(IOSSM_STATUS_CMD_RESPONSE_ERROR_MASK, n)
+#define IOSSM_STATUS_GENERAL_ERROR_MASK		GENMASK(4, 1)
+#define IOSSM_STATUS_GENERAL_ERROR(n)		FIELD_GET(IOSSM_STATUS_GENERAL_ERROR_MASK, n)
+
+/* Offset of Mailbox Read-only Registers  */
+#define IOSSM_MAILBOX_HEADER_OFFSET			0x0
+#define IOSSM_MEM_INTF_INFO_0_OFFSET			0X200
+#define IOSSM_MEM_INTF_INFO_1_OFFSET			0x280
+#define IOSSM_MEM_TECHNOLOGY_INTF0_OFFSET		0x210
+#define IOSSM_MEM_TECHNOLOGY_INTF1_OFFSET		0x290
+#define IOSSM_MEM_WIDTH_INFO_INTF0_OFFSET		0x230
+#define IOSSM_MEM_WIDTH_INFO_INTF1_OFFSET		0x2B0
+#define IOSSM_MEM_TOTAL_CAPACITY_INTF0_OFFSET		0x234
+#define IOSSM_MEM_TOTAL_CAPACITY_INTF1_OFFSET		0x2B4
+#define IOSSM_ECC_ENABLE_INTF0_OFFSET			0x240
+#define IOSSM_ECC_ENABLE_INTF1_OFFSET			0x2C0
+#define IOSSM_ECC_SCRUB_STATUS_INTF0_OFFSET		0x244
+#define IOSSM_ECC_SCRUB_STATUS_INTF1_OFFSET		0x2C4
+#define IOSSM_LP_MODE_INTF0_OFFSET			0x250
+#define IOSSM_LP_MODE_INTF1_OFFSET			0x2D0
+#define IOSSM_MEM_INIT_STATUS_INTF0_OFFSET		0x260
+#define IOSSM_MEM_INIT_STATUS_INTF1_OFFSET		0x2E0
+#define IOSSM_BIST_STATUS_INTF0_OFFSET			0x264
+#define IOSSM_BIST_STATUS_INTF1_OFFSET			0x2E4
+#define IOSSM_ECC_ERR_STATUS_OFFSET			0x300
+#define IOSSM_ECC_ERR_DATA_START_OFFSET			0x310
+#define IOSSM_STATUS_OFFSET				0x400
+#define IOSSM_STATUS_CAL_INTF0_OFFSET			0x404
+#define IOSSM_STATUS_CAL_INTF1_OFFSET			0x408
+
+#define ECC_INTSTATUS_SERR SOCFPGA_SYSMGR_ADDRESS + 0x9C
+#define ECC_INISTATUS_DERR SOCFPGA_SYSMGR_ADDRESS + 0xA0
+#define DDR_CSR_CLKGEN_LOCKED_IO96B0_MASK BIT(16)
+#define DDR_CSR_CLKGEN_LOCKED_IO96B1_MASK BIT(17)
+
+/* offset info of GET_MEM_INTF_INFO */
+#define INTF_IP_TYPE_MASK		GENMASK(31, 29)
+#define INTF_INSTANCE_ID_MASK		GENMASK(28, 24)
+
+/* offset info of GET_MEM_CAL_STATUS */
+#define INTF_UNUSED			0x0
+#define INTF_MEM_CAL_STATUS_SUCCESS	0x1
+#define INTF_MEM_CAL_STATUS_FAIL	0x2
+#define INTF_MEM_CAL_STATUS_ONGOING	0x4
+
+/* offset info of  MEM_TECHNOLOGY_INTF */
+#define INTF_DDR_TYPE_MASK		GENMASK(2, 0)
+
+/* offset info of MEM_TOTAL_CAPACITY_INTF */
+#define INTF_CAPACITY_GBITS_MASK	GENMASK(7, 0)
+
+/* offset info of ECC_ENABLE_INTF */
+#define INTF_ECC_ENABLE_TYPE_MASK	GENMASK(1, 0)
+
+/* cmd opcode BIST_MEM_INIT_START, BIST performed on full memory address range */
+#define BIST_FULL_MEM			BIT(6)
+
+/* offset info of ECC_ENABLE_INTF */
+#define INTF_BIST_STATUS_MASK		BIT(0)
+
+/* offset info of ECC_ERR_STATUS */
+#define ECC_ERR_COUNTER_MASK		GENMASK(15, 0)
+
+/* offset info of ECC_ERR_DATA */
+#define ECC_ERR_IP_TYPE_MASK		GENMASK(24, 22)
+#define ECC_ERR_INSTANCE_ID_MASK	GENMASK(21, 17)
+#define ECC_ERR_SOURCE_ID_MASK		GENMASK(16, 10)
+#define ECC_ERR_TYPE_MASK		GENMASK(9, 6)
+#define ECC_ERR_ADDR_UPPER_MASK		GENMASK(5, 0)
+#define ECC_ERR_ADDR_LOWER_MASK		GENMASK(31, 0)
+
+#define MAX_ECC_ERR_INFO_COUNT 16
+
+#define IO96B_MB_REQ_SETUP(v, w, x, y, z) \
+	usr_req.ip_type = v; \
+	usr_req.ip_id = w; \
+	usr_req.usr_cmd_type = x; \
+	usr_req.usr_cmd_opcode = y; \
+	usr_req.cmd_param[0] = z; \
+	for (n = 1; n < NUM_CMD_PARAM; n++) \
+		usr_req.cmd_param[n] = 0
+#define MAX_RETRY_COUNT 3
+#define NUM_CMD_RESPONSE_DATA 3
+
+#define IO96B0_PLL_A_MASK	BIT(0)
+#define IO96B0_PLL_B_MASK	BIT(1)
+#define IO96B1_PLL_A_MASK	BIT(2)
+#define IO96B1_PLL_B_MASK	BIT(3)
+
+/* supported DDR type list */
+static const char *ddr_type_list[7] = {
+		"DDR4", "DDR5", "DDR5_RDIMM", "LPDDR4", "LPDDR5", "QDRIV", "UNKNOWN"
+};
+
+/* Define an enumeration for ECC error types */
+enum ecc_error_type {
+	SINGLE_BIT_ERROR = 0,			/* 0b0000 */
+	MULTIPLE_SINGLE_BIT_ERRORS = 1,		/* 0b0001 */
+	DOUBLE_BIT_ERROR = 2,			/* 0b0010 */
+	MULTIPLE_DOUBLE_BIT_ERRORS = 3,		/* 0b0011 */
+	SINGLE_BIT_ERROR_SCRUBBING = 8,		/* 0b1000 */
+	WRITE_LINK_SINGLE_BIT_ERROR = 9,	/* 0b1001 */
+	WRITE_LINK_DOUBLE_BIT_ERROR = 10,	/* 0b1010 */
+	READ_LINK_SINGLE_BIT_ERROR = 11,	/* 0b1011 */
+	READ_LINK_DOUBLE_BIT_ERROR = 12,	/* 0b1100 */
+	READ_MODIFY_WRITE_DOUBLE_BIT_ERROR = 13	/* 0b1101 */
+};
+
+/*
+ * ecc error info
+ *
+ * @ip_type:		The IP type of the interface that produced the ECC interrupt.
+ * @instance_id:	The instance ID of the interface that produced the ECC interrupt.
+ * @ecc_err_source_id:	The source ID associated with the ECC event.
+ * @ecc_err_type:	The ECC error type of the ECC event.
+ * @ecc_err_addr_upper:	Upper 6 bits of the address of the read data that caused the ECC event.
+ * @ecc_err_addr_lower:	Lower 32 bits of the address of the read data that caused the ECC event.
+ */
+struct ecc_err_info {
+	u32 ip_type;
+	u32 instance_id;
+	u32 source_id;
+	enum ecc_error_type err_type;
+	u32 addr_upper;
+	u32 addr_lower;
+};
+
+static int is_ddr_csr_clkgen_locked(u8 io96b_pll)
+{
+	int ret = 0;
+	const char *pll_names[MAX_IO96B_SUPPORTED][2] = {
+		{"io96b_0 clkgenA", "io96b_0 clkgenB"},
+		{"io96b_1 clkgenA", "io96b_1 clkgenB"}
+	};
+	u32 masks[MAX_IO96B_SUPPORTED][2] = {
+		{IO96B0_PLL_A_MASK, IO96B0_PLL_B_MASK},
+		{IO96B1_PLL_A_MASK, IO96B1_PLL_B_MASK}
+	};
+	u32 lock_masks[MAX_IO96B_SUPPORTED] = {
+		DDR_CSR_CLKGEN_LOCKED_IO96B0_MASK,
+		DDR_CSR_CLKGEN_LOCKED_IO96B1_MASK
+	};
+
+	for (int i = 0; i < MAX_IO96B_SUPPORTED ; i++) {
+		/* Check for PLL_A */
+		if (io96b_pll & masks[i][0]) {
+			ret = wait_for_bit_le32((const void *)(ECC_INTSTATUS_SERR), lock_masks[i],
+						true, TIMEOUT, false);
+
+			if (ret) {
+				debug("%s: ddr csr %s locked is timeout\n",
+				      __func__, pll_names[i][0]);
+				goto err;
+			} else {
+				debug("%s: ddr csr %s is successfully locked\n",
+				      __func__, pll_names[i][0]);
+			}
+		}
+
+		/* Check for PLL_B */
+		if (io96b_pll & masks[i][1]) {
+			ret = wait_for_bit_le32((const void *)(ECC_INISTATUS_DERR), lock_masks[i],
+						true, TIMEOUT, false);
+
+			if (ret) {
+				debug("%s: ddr csr %s locked is timeout\n",
+				      __func__, pll_names[i][1]);
+				goto err;
+			} else {
+				debug("%s: ddr csr %s is successfully locked\n",
+				      __func__, pll_names[i][1]);
+			}
+		}
+	}
+
+err:
+	return ret;
+}
+
+/*
+ * Mailbox request function
+ * This function will send the request to IOSSM mailbox and wait for response return
+ *
+ * @io96b_csr_addr: CSR address for the target IO96B
+ * @req:            Structure contain command request for IOSSM mailbox command
+ * @resp_data_len:  User desire extra response data fields other than
+ *		    CMD_RESPONSE_DATA_SHORT field on CMD_RESPONSE_STATUS
+ * @resp:           Structure contain responses returned from the requested IOSSM
+ *		    mailbox command
+ */
+int io96b_mb_req(phys_addr_t io96b_csr_addr, struct io96b_mb_req req,
+		 u32 resp_data_len, struct io96b_mb_resp *resp)
+{
+	int i, ret;
+	u32 cmd_req;
+
+	if (!resp) {
+		ret = -EINVAL;
+		goto err;
+	}
+
+	/* Zero initialization for responses */
+	resp->cmd_resp_status = 0;
+
+	/* Ensure CMD_REQ is cleared before write any command request */
+	ret = wait_for_bit_le32((const void *)(io96b_csr_addr + IOSSM_CMD_REQ_OFFSET),
+				GENMASK(31, 0), false, TIMEOUT, false);
+	if (ret) {
+		printf("%s: Timeout of waiting DDR mailbox ready to be functioned!\n",
+		       __func__);
+		goto err;
+	}
+
+	/* Write CMD_PARAM_* */
+	for (i = 0; i < NUM_CMD_PARAM ; i++) {
+		switch (i) {
+		case 0:
+			if (req.cmd_param[0])
+				writel(req.cmd_param[0], io96b_csr_addr + IOSSM_CMD_PARAM_0_OFFSET);
+			break;
+		case 1:
+			if (req.cmd_param[1])
+				writel(req.cmd_param[1], io96b_csr_addr + IOSSM_CMD_PARAM_1_OFFSET);
+			break;
+		case 2:
+			if (req.cmd_param[2])
+				writel(req.cmd_param[2], io96b_csr_addr + IOSSM_CMD_PARAM_2_OFFSET);
+			break;
+		case 3:
+			if (req.cmd_param[3])
+				writel(req.cmd_param[3], io96b_csr_addr + IOSSM_CMD_PARAM_3_OFFSET);
+			break;
+		case 4:
+			if (req.cmd_param[4])
+				writel(req.cmd_param[4], io96b_csr_addr + IOSSM_CMD_PARAM_4_OFFSET);
+			break;
+		case 5:
+			if (req.cmd_param[5])
+				writel(req.cmd_param[5], io96b_csr_addr + IOSSM_CMD_PARAM_5_OFFSET);
+			break;
+		case 6:
+			if (req.cmd_param[6])
+				writel(req.cmd_param[6], io96b_csr_addr + IOSSM_CMD_PARAM_6_OFFSET);
+			break;
+		}
+	}
+
+	/* Write CMD_REQ (IP_TYPE, IP_INSTANCE_ID, CMD_TYPE and CMD_OPCODE) */
+	cmd_req = FIELD_PREP(CMD_TARGET_IP_TYPE_MASK, req.ip_type) |
+		FIELD_PREP(CMD_TARGET_IP_INSTANCE_ID_MASK, req.ip_id) |
+		FIELD_PREP(CMD_TYPE_MASK, req.usr_cmd_type) |
+		FIELD_PREP(CMD_OPCODE_MASK, req.usr_cmd_opcode);
+	writel(cmd_req, io96b_csr_addr + IOSSM_CMD_REQ_OFFSET);
+
+	debug("%s: Write 0x%x to IOSSM_CMD_REQ_OFFSET 0x%llx\n", __func__, cmd_req,
+	      io96b_csr_addr + IOSSM_CMD_REQ_OFFSET);
+
+	/* Read CMD_RESPONSE_READY in CMD_RESPONSE_STATUS */
+	ret = wait_for_bit_le32((const void *)(io96b_csr_addr + IOSSM_CMD_RESPONSE_STATUS_OFFSET),
+				IOSSM_STATUS_COMMAND_RESPONSE_READY, true, TIMEOUT, false);
+
+	/* read CMD_RESPONSE_STATUS */
+	resp->cmd_resp_status = readl(io96b_csr_addr + IOSSM_CMD_RESPONSE_STATUS_OFFSET);
+
+	debug("%s: CMD_RESPONSE_STATUS 0x%llx: 0x%x\n", __func__, io96b_csr_addr +
+	      IOSSM_CMD_RESPONSE_STATUS_OFFSET, resp->cmd_resp_status);
+
+	if (ret) {
+		printf("%s: CMD_RESPONSE ERROR:\n", __func__);
+
+		printf("%s: STATUS_GENERAL_ERROR: 0x%lx\n", __func__,
+		       IOSSM_STATUS_GENERAL_ERROR(resp->cmd_resp_status));
+		printf("%s: STATUS_CMD_RESPONSE_ERROR: 0x%lx\n", __func__,
+		       IOSSM_STATUS_CMD_RESPONSE_ERROR(resp->cmd_resp_status));
+		goto err;
+	}
+
+	/* read CMD_RESPONSE_DATA_* */
+	for (i = 0; i < resp_data_len; i++) {
+		switch (i) {
+		case 0:
+			resp->cmd_resp_data[i] =
+					readl(io96b_csr_addr + IOSSM_CMD_RESPONSE_DATA_0_OFFSET);
+
+			debug("%s: IOSSM_CMD_RESPONSE_DATA_0_OFFSET 0x%llx: 0x%x\n", __func__,
+			      io96b_csr_addr + IOSSM_CMD_RESPONSE_DATA_0_OFFSET,
+			      resp->cmd_resp_data[i]);
+			break;
+		case 1:
+			resp->cmd_resp_data[i] =
+					readl(io96b_csr_addr + IOSSM_CMD_RESPONSE_DATA_1_OFFSET);
+
+			debug("%s: IOSSM_CMD_RESPONSE_DATA_1_OFFSET 0x%llx: 0x%x\n", __func__,
+			      io96b_csr_addr + IOSSM_CMD_RESPONSE_DATA_1_OFFSET,
+			      resp->cmd_resp_data[i]);
+			break;
+		case 2:
+			resp->cmd_resp_data[i] =
+					readl(io96b_csr_addr + IOSSM_CMD_RESPONSE_DATA_2_OFFSET);
+
+			debug("%s: IOSSM_CMD_RESPONSE_DATA_2_OFFSET 0x%llx: 0x%x\n", __func__,
+			      io96b_csr_addr + IOSSM_CMD_RESPONSE_DATA_2_OFFSET,
+			      resp->cmd_resp_data[i]);
+			break;
+		default:
+			resp->cmd_resp_data[i] = 0;
+			printf("%s: Invalid response data\n", __func__);
+		}
+	}
+
+	/* write CMD_RESPONSE_READY = 0 */
+	clrbits_le32((u32 *)(uintptr_t)(io96b_csr_addr + IOSSM_CMD_RESPONSE_STATUS_OFFSET),
+		     IOSSM_STATUS_COMMAND_RESPONSE_READY);
+
+	debug("%s: After clear CMD_RESPONSE_READY bit: 0x%llx: 0x%x\n", __func__,
+	      io96b_csr_addr + IOSSM_CMD_RESPONSE_STATUS_OFFSET,
+	      readl(io96b_csr_addr + IOSSM_CMD_RESPONSE_STATUS_OFFSET));
+
+err:
+	return ret;
+}
+
+/*
+ * Initial function to be called to set memory interface IP type and instance ID
+ * IP type and instance ID need to be determined before sending mailbox command
+ */
+void io96b_mb_init(struct io96b_info *io96b_ctrl)
+{
+	int i, j;
+	u32 mem_intf_info_0, mem_intf_info_1;
+
+	debug("%s: num_instance %d\n", __func__, io96b_ctrl->num_instance);
+
+	for (i = 0; i < io96b_ctrl->num_instance; i++) {
+		debug("%s: get memory interface IO96B %d\n", __func__, i);
+		io96b_ctrl->io96b[i].mb_ctrl.num_mem_interface = 0;
+
+		mem_intf_info_0 = readl(io96b_ctrl->io96b[i].io96b_csr_addr +
+					IOSSM_MEM_INTF_INFO_0_OFFSET);
+		mem_intf_info_1 = readl(io96b_ctrl->io96b[i].io96b_csr_addr +
+					IOSSM_MEM_INTF_INFO_1_OFFSET);
+
+		io96b_ctrl->io96b[i].mb_ctrl.ip_type[0] = FIELD_GET(INTF_IP_TYPE_MASK,
+								    mem_intf_info_0);
+		io96b_ctrl->io96b[i].mb_ctrl.ip_id[0] = FIELD_GET(INTF_INSTANCE_ID_MASK,
+								  mem_intf_info_0);
+		io96b_ctrl->io96b[i].mb_ctrl.ip_type[1] = FIELD_GET(INTF_IP_TYPE_MASK,
+								    mem_intf_info_1);
+		io96b_ctrl->io96b[i].mb_ctrl.ip_id[1] = FIELD_GET(INTF_INSTANCE_ID_MASK,
+								  mem_intf_info_1);
+
+		for (j = 0; j < MAX_MEM_INTERFACE_SUPPORTED; j++) {
+			if (io96b_ctrl->io96b[i].mb_ctrl.ip_type[j]) {
+				io96b_ctrl->io96b[i].mb_ctrl.num_mem_interface++;
+
+				debug("%s: IO96B %d mem_interface %d: ip_type_ret: 0x%x\n",
+				      __func__, i, j, io96b_ctrl->io96b[i].mb_ctrl.ip_type[j]);
+				debug("%s: IO96B %d mem_interface %d: instance_id_ret: 0x%x\n",
+				      __func__, i, j, io96b_ctrl->io96b[i].mb_ctrl.ip_id[j]);
+			}
+		}
+
+		debug("%s: IO96B %d: num_mem_interface: 0x%x\n", __func__, i,
+		      io96b_ctrl->io96b[i].mb_ctrl.num_mem_interface);
+	}
+}
+
+int io96b_cal_status(phys_addr_t addr)
+{
+	u32 cal_success, cal_fail;
+	phys_addr_t status_addr = addr + IOSSM_STATUS_OFFSET;
+	u32 start = get_timer(0);
+
+	do {
+		if (get_timer(start) > TIMEOUT_60000MS) {
+			printf("%s: SDRAM calibration for IO96B instance 0x%llx timeout!\n",
+			       __func__, status_addr);
+			hang();
+		}
+
+		udelay(1);
+		schedule();
+
+		/* Polling until getting any calibration result */
+		cal_success = readl(status_addr) & IOSSM_STATUS_CAL_SUCCESS;
+		cal_fail = readl(status_addr) & IOSSM_STATUS_CAL_FAIL;
+	} while (!cal_success && !cal_fail);
+
+	debug("%s: Calibration for IO96B instance 0x%llx done at %ld msec!\n",
+	      __func__,  status_addr, get_timer(start));
+
+	if (cal_success && !cal_fail)
+		return 0;
+	else
+		return -EPERM;
+}
+
+void init_mem_cal(struct io96b_info *io96b_ctrl)
+{
+	int count, i, ret;
+
+	/* Initialize overall calibration status */
+	io96b_ctrl->overall_cal_status = false;
+
+	if (io96b_ctrl->ckgen_lock) {
+		ret = is_ddr_csr_clkgen_locked(io96b_ctrl->io96b_pll);
+		if (ret) {
+			printf("%s: iossm IO96B ckgena_lock is not locked\n", __func__);
+			hang();
+		}
+	}
+
+	/* Check initial calibration status for the assigned IO96B */
+	count = 0;
+	for (i = 0; i < io96b_ctrl->num_instance; i++) {
+		ret = io96b_cal_status(io96b_ctrl->io96b[i].io96b_csr_addr);
+		if (ret) {
+			io96b_ctrl->io96b[i].cal_status = false;
+
+			printf("%s: Initial DDR calibration IO96B_%d failed %d\n", __func__,
+			       i, ret);
+
+			hang();
+		}
+
+		io96b_ctrl->io96b[i].cal_status = true;
+
+		printf("%s: Initial DDR calibration IO96B_%d succeed\n", __func__, i);
+
+		count++;
+	}
+
+	if (count == io96b_ctrl->num_instance)
+		io96b_ctrl->overall_cal_status = true;
+}
+
+int get_mem_technology(struct io96b_info *io96b_ctrl)
+{
+	int i, j, ret = 0;
+	u32 mem_technology_intf;
+	u8 ddr_type_ret;
+
+	u32 mem_technology_intf_offset[MAX_MEM_INTERFACE_SUPPORTED] = {
+		IOSSM_MEM_TECHNOLOGY_INTF0_OFFSET,
+		IOSSM_MEM_TECHNOLOGY_INTF1_OFFSET
+	};
+
+	/* Initialize ddr type */
+	io96b_ctrl->ddr_type = ddr_type_list[6];
+
+	/* Get and ensure all memory interface(s) same DDR type */
+	for (i = 0; i < io96b_ctrl->num_instance; i++) {
+		for (j = 0; j < io96b_ctrl->io96b[i].mb_ctrl.num_mem_interface; j++) {
+			mem_technology_intf = readl(io96b_ctrl->io96b[i].io96b_csr_addr +
+						    mem_technology_intf_offset[j]);
+
+			ddr_type_ret = FIELD_GET(INTF_DDR_TYPE_MASK, mem_technology_intf);
+
+			if (!strcmp(io96b_ctrl->ddr_type, "UNKNOWN"))
+				io96b_ctrl->ddr_type = ddr_type_list[ddr_type_ret];
+
+			if (ddr_type_list[ddr_type_ret] != io96b_ctrl->ddr_type) {
+				printf("%s: Mismatch DDR type on IO96B_%d\n", __func__, i);
+
+				ret = -EINVAL;
+				goto err;
+			}
+		}
+	}
+
+err:
+	return ret;
+}
+
+int get_mem_width_info(struct io96b_info *io96b_ctrl)
+{
+	int i, j, ret = 0;
+	u32 mem_width_info;
+	u16 memory_size, total_memory_size = 0;
+
+	u32 mem_total_capacity_intf_offset[MAX_MEM_INTERFACE_SUPPORTED] = {
+		IOSSM_MEM_TOTAL_CAPACITY_INTF0_OFFSET,
+		IOSSM_MEM_TOTAL_CAPACITY_INTF1_OFFSET
+	};
+
+	/* Get all memory interface(s) total memory size on all instance(s) */
+	for (i = 0; i < io96b_ctrl->num_instance; i++) {
+		memory_size = 0;
+		for (j = 0; j < io96b_ctrl->io96b[i].mb_ctrl.num_mem_interface; j++) {
+			mem_width_info = readl(io96b_ctrl->io96b[i].io96b_csr_addr +
+					       mem_total_capacity_intf_offset[j]);
+
+			memory_size = memory_size +
+					FIELD_GET(INTF_CAPACITY_GBITS_MASK, mem_width_info);
+		}
+
+		if (!memory_size) {
+			printf("%s: Failed to get valid memory size\n", __func__);
+			ret = -EINVAL;
+			goto err;
+		}
+
+		io96b_ctrl->io96b[i].size = memory_size;
+
+		total_memory_size = total_memory_size + memory_size;
+	}
+
+	if (!total_memory_size) {
+		printf("%s: Failed to get valid memory size\n", __func__);
+		ret = -EINVAL;
+	}
+
+	io96b_ctrl->overall_size = total_memory_size;
+
+err:
+	return ret;
+}
+
+int ecc_enable_status(struct io96b_info *io96b_ctrl)
+{
+	int i, j, ret = 0;
+	u32 ecc_enable_intf;
+	bool ecc_stat, ecc_stat_set = false;
+
+	u32 ecc_enable_intf_offset[MAX_MEM_INTERFACE_SUPPORTED] = {
+		IOSSM_ECC_ENABLE_INTF0_OFFSET,
+		IOSSM_ECC_ENABLE_INTF1_OFFSET
+	};
+
+	/* Initialize ECC status */
+	io96b_ctrl->ecc_status = false;
+
+	/* Get and ensure all memory interface(s) same ECC status */
+	for (i = 0; i < io96b_ctrl->num_instance; i++) {
+		for (j = 0; j < io96b_ctrl->io96b[i].mb_ctrl.num_mem_interface; j++) {
+			ecc_enable_intf = readl(io96b_ctrl->io96b[i].io96b_csr_addr +
+						ecc_enable_intf_offset[j]);
+
+			ecc_stat = (FIELD_GET(INTF_ECC_ENABLE_TYPE_MASK, ecc_enable_intf)
+				    == 0) ? false : true;
+
+			if (!ecc_stat_set) {
+				io96b_ctrl->ecc_status = ecc_stat;
+				ecc_stat_set = true;
+			}
+
+			if (ecc_stat != io96b_ctrl->ecc_status) {
+				printf("%s: Mismatch DDR ECC status on IO96B_%d\n", __func__, i);
+
+				ret = -EINVAL;
+				goto err;
+			}
+		}
+	}
+
+	debug("%s: ECC enable status: %d\n", __func__, io96b_ctrl->ecc_status);
+
+err:
+	return ret;
+}
+
+bool is_double_bit_error(enum ecc_error_type err_type)
+{
+	switch (err_type) {
+	case DOUBLE_BIT_ERROR:
+	case MULTIPLE_DOUBLE_BIT_ERRORS:
+	case WRITE_LINK_DOUBLE_BIT_ERROR:
+	case READ_LINK_DOUBLE_BIT_ERROR:
+	case READ_MODIFY_WRITE_DOUBLE_BIT_ERROR:
+		return true;
+
+	default:
+		return false;
+	}
+}
+
+bool ecc_interrupt_status(struct io96b_info *io96b_ctrl)
+{
+	int i, j;
+	u32 ecc_err_status;
+	u16 ecc_err_counter;
+	bool ecc_error_flag = false;
+
+	/* Get ECC double-bit error status */
+	for (i = 0; i < io96b_ctrl->num_instance; i++) {
+		ecc_err_status = readl(io96b_ctrl->io96b[i].io96b_csr_addr +
+					IOSSM_ECC_ERR_STATUS_OFFSET);
+		ecc_err_counter = FIELD_GET(ECC_ERR_COUNTER_MASK, ecc_err_status);
+		debug("%s: ECC error number detected on IO96B_%d: %d\n",
+		      __func__, i, ecc_err_counter);
+
+		if (ecc_err_counter != 0) {
+			phys_addr_t address;
+			u32 ecc_err_data;
+			struct ecc_err_info err_info;
+
+			address = io96b_ctrl->io96b[i].io96b_csr_addr +
+				    IOSSM_ECC_ERR_DATA_START_OFFSET;
+
+			for (j = 0; j < ecc_err_counter && j < MAX_ECC_ERR_INFO_COUNT; j++) {
+				ecc_err_data = readl(address);
+				err_info.err_type = FIELD_GET(ECC_ERR_TYPE_MASK,
+							      ecc_err_data);
+				err_info.ip_type = FIELD_GET(ECC_ERR_IP_TYPE_MASK,
+							     ecc_err_data);
+				err_info.instance_id = FIELD_GET(ECC_ERR_INSTANCE_ID_MASK,
+								 ecc_err_data);
+				err_info.source_id = FIELD_GET(ECC_ERR_SOURCE_ID_MASK,
+							       ecc_err_data);
+				err_info.addr_upper = FIELD_GET(ECC_ERR_ADDR_UPPER_MASK,
+								ecc_err_data);
+				err_info.addr_lower = readl(address + sizeof(u32));
+
+				debug("%s: ECC double-bit error detected on IO96B_%d:\n",
+				      __func__, i);
+				debug("- error info address :0x%llx\n", address);
+				debug("- error ip type: %d\n", err_info.ip_type);
+				debug("- error instance id: %d\n", err_info.instance_id);
+				debug("- error source id: %d\n", err_info.source_id);
+				debug("- error type: %d\n", err_info.err_type);
+				debug("- error address upper: 0x%x\n", err_info.addr_upper);
+				debug("- error address lower: 0x%x\n", err_info.addr_lower);
+
+				if (is_double_bit_error(err_info.err_type)) {
+					if (!ecc_error_flag)
+						ecc_error_flag = true;
+				}
+
+				address += sizeof(u32) * 2;
+			}
+		}
+	}
+
+	if (ecc_error_flag)
+		printf("\n%s: ECC double-bit error detected!\n", __func__);
+
+	return ecc_error_flag;
+}
+
+int bist_mem_init_start(struct io96b_info *io96b_ctrl)
+{
+	struct io96b_mb_req usr_req;
+	struct io96b_mb_resp usr_resp;
+	int i, j, n, ret = 0;
+	bool bist_start, bist_success;
+	u32 mem_init_status_intf, start;
+
+	u32 mem_init_status_offset[MAX_MEM_INTERFACE_SUPPORTED] = {
+		IOSSM_MEM_INIT_STATUS_INTF0_OFFSET,
+		IOSSM_MEM_INIT_STATUS_INTF1_OFFSET
+	};
+
+	/* Full memory initialization BIST performed on all memory interface(s) */
+	for (i = 0; i < io96b_ctrl->num_instance; i++) {
+		for (j = 0; j < io96b_ctrl->io96b[i].mb_ctrl.num_mem_interface; j++) {
+			bist_start = false;
+			bist_success = false;
+
+			/* Start memory initialization BIST on full memory address */
+			IO96B_MB_REQ_SETUP(io96b_ctrl->io96b[i].mb_ctrl.ip_type[j],
+					   io96b_ctrl->io96b[i].mb_ctrl.ip_id[j],
+					   CMD_TRIG_CONTROLLER_OP, BIST_MEM_INIT_START,
+					   BIST_FULL_MEM);
+
+			ret = io96b_mb_req(io96b_ctrl->io96b[i].io96b_csr_addr,
+					   usr_req, 0, &usr_resp);
+			if (ret)
+				goto err;
+
+			bist_start = IOSSM_CMD_RESPONSE_DATA_SHORT(usr_resp.cmd_resp_status)
+				& BIT(0);
+
+			if (!bist_start) {
+				printf("%s: Failed to initialize memory on IO96B_%d\n", __func__,
+				       i);
+				printf("%s: BIST_MEM_INIT_START Error code 0x%lx\n", __func__,
+				       IOSSM_STATUS_CMD_RESPONSE_ERROR(usr_resp.cmd_resp_status));
+
+				ret = -EINVAL;
+				goto err;
+			}
+
+			/* Polling for the initiated memory initialization BIST status */
+			start = get_timer(0);
+			while (!bist_success) {
+				udelay(1);
+
+				mem_init_status_intf = readl(io96b_ctrl->io96b[i].io96b_csr_addr +
+							     mem_init_status_offset[j]);
+
+				bist_success = FIELD_GET(INTF_BIST_STATUS_MASK,
+							 mem_init_status_intf);
+
+				if (!bist_success && (get_timer(start) > TIMEOUT)) {
+					printf("%s: Timeout initialize memory on IO96B_%d\n",
+					       __func__, i);
+					printf("%s: BIST_MEM_INIT_STATUS Error code 0x%lx\n",
+					       __func__,
+					IOSSM_STATUS_CMD_RESPONSE_ERROR(usr_resp.cmd_resp_status));
+
+					ret = -ETIMEDOUT;
+					goto err;
+				}
+			}
+		}
+
+		debug("%s: Memory initialized successfully on IO96B_%d\n", __func__, i);
+	}
+
+err:
+	return ret;
+}
diff --git a/drivers/ddr/altera/iossm_mailbox.h b/drivers/ddr/altera/iossm_mailbox.h
new file mode 100644
index 00000000000..6f794781d30
--- /dev/null
+++ b/drivers/ddr/altera/iossm_mailbox.h
@@ -0,0 +1,136 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2025 Altera Corporation <www.altera.com>
+ *
+ */
+
+#define MAX_IO96B_SUPPORTED			2
+#define MAX_MEM_INTERFACE_SUPPORTED			2
+#define NUM_CMD_RESPONSE_DATA			3
+#define NUM_CMD_PARAM				7
+
+/* supported mailbox command type */
+enum iossm_mailbox_cmd_type  {
+	CMD_NOP,
+	CMD_GET_SYS_INFO,
+	CMD_GET_MEM_INFO,
+	CMD_GET_MEM_CAL_INFO,
+	CMD_TRIG_CONTROLLER_OP,
+	CMD_TRIG_MEM_CAL_OP
+};
+
+/* supported mailbox command opcode */
+enum iossm_mailbox_cmd_opcode  {
+	ECC_ENABLE_SET = 0x0101,
+	ECC_INTERRUPT_MASK = 0x0105,
+	ECC_WRITEBACK_ENABLE = 0x0106,
+	ECC_INJECT_ERROR = 0x0109,
+	ECC_SCRUB_MODE_0_START = 0x0202,
+	ECC_SCRUB_MODE_1_START = 0x0203,
+	BIST_STANDARD_MODE_START = 0x0301,
+	BIST_MEM_INIT_START = 0x0303,
+	BIST_SET_DATA_PATTERN_UPPER = 0x0305,
+	BIST_SET_DATA_PATTERN_LOWER = 0x0306,
+	TRIG_MEM_CAL = 0x000a
+};
+
+/*
+ * IOSSM mailbox required information
+ *
+ * @num_mem_interface:	Number of memory interfaces instantiated
+ * @ip_type:		IP type implemented on the IO96B
+ * @ip_instance_id:	IP identifier for every IP instance implemented on the IO96B
+ */
+struct io96b_mb_ctrl {
+	u32 num_mem_interface;
+	u32 ip_type[2];
+	u32 ip_id[2];
+};
+
+/* CMD_REQ Register Definition */
+#define CMD_TARGET_IP_TYPE_MASK		GENMASK(31, 29)
+#define CMD_TARGET_IP_INSTANCE_ID_MASK	GENMASK(28, 24)
+#define CMD_TYPE_MASK			GENMASK(23, 16)
+#define CMD_OPCODE_MASK			GENMASK(15, 0)
+
+/*
+ * IOSSM mailbox request
+ * @ip_type:	    IP type for the specified memory interface
+ * @ip_id:	    IP instance ID for the specified memory interface
+ * @usr_cmd_type:   User desire IOSSM mailbox command type
+ * @usr_cmd_opcode: User desire IOSSM mailbox command opcode
+ * @cmd_param_*:    Parameters (if applicable) for the requested IOSSM mailbox command
+ */
+struct io96b_mb_req {
+	u32 ip_type;
+	u32 ip_id;
+	u32 usr_cmd_type;
+	u32 usr_cmd_opcode;
+	u32 cmd_param[NUM_CMD_PARAM];
+};
+
+/*
+ * IOSSM mailbox response outputs
+ *
+ * @cmd_resp_status: Command Interface status
+ * @cmd_resp_data_*: More spaces for command response
+ */
+struct io96b_mb_resp {
+	u32 cmd_resp_status;
+	u32 cmd_resp_data[NUM_CMD_RESPONSE_DATA];
+};
+
+/*
+ * IO96B instance specific information
+ *
+ * @size:		Memory size
+ * @io96b_csr_addr:	IO96B instance CSR address
+ * @cal_status:		IO96B instance calibration status
+ * @mb_ctrl:		IOSSM mailbox required information
+ */
+struct io96b_instance {
+	u16 size;
+	phys_addr_t io96b_csr_addr;
+	bool cal_status;
+	struct io96b_mb_ctrl mb_ctrl;
+};
+
+/*
+ * Overall IO96B instance(s) information
+ *
+ * @num_instance:	Number of instance(s) assigned to HPS
+ * @overall_cal_status: Overall calibration status for all IO96B instance(s)
+ * @ddr_type:		DDR memory type
+ * @ecc_status:		ECC enable status (false = disabled, true = enabled)
+ * @overall_size:	Total DDR memory size
+ * @io96b[]:		IO96B instance specific information
+ * @ckgen_lock:		IO96B GEN PLL lock (false = not locked, true = locked)
+ * @num_port:		Number of IO96B port.
+ * @io96b_pll:		Selected IO96B PLL. Example bit 0: EMIF0 PLL A selected,
+ *			bit 1: EMIF0 PLL B selected, bit 2 - EMIF1 PLL A selected,
+ *			bit 3: EMIF1 PLL B selected
+ */
+struct io96b_info {
+	u8 num_instance;
+	bool overall_cal_status;
+	const char *ddr_type;
+	bool ecc_status;
+	u16 overall_size;
+	struct io96b_instance io96b[MAX_IO96B_SUPPORTED];
+	bool ckgen_lock;
+	u8 num_port;
+	u8 io96b_pll;
+};
+
+int io96b_mb_req(phys_addr_t io96b_csr_addr, struct io96b_mb_req req,
+		 u32 resp_data_len, struct io96b_mb_resp *resp);
+
+/* Supported IOSSM mailbox function */
+void io96b_mb_init(struct io96b_info *io96b_ctrl);
+int io96b_cal_status(phys_addr_t addr);
+void init_mem_cal(struct io96b_info *io96b_ctrl);
+int get_mem_technology(struct io96b_info *io96b_ctrl);
+int get_mem_width_info(struct io96b_info *io96b_ctrl);
+int ecc_enable_status(struct io96b_info *io96b_ctrl);
+int bist_mem_init_start(struct io96b_info *io96b_ctrl);
+bool ecc_interrupt_status(struct io96b_info *io96b_ctrl);
diff --git a/drivers/ddr/altera/sdram_agilex5.c b/drivers/ddr/altera/sdram_agilex5.c
new file mode 100644
index 00000000000..801a6bbab46
--- /dev/null
+++ b/drivers/ddr/altera/sdram_agilex5.c
@@ -0,0 +1,420 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2025 Altera Corporation <www.altera.com>
+ *
+ */
+
+#include <stdlib.h>
+#include <div64.h>
+#include <dm.h>
+#include <errno.h>
+#include <fdtdec.h>
+#include <hang.h>
+#include <log.h>
+#include <ram.h>
+#include <reset.h>
+#include <wait_bit.h>
+#include <wdt.h>
+#include <linux/bitfield.h>
+#include <linux/sizes.h>
+#include <asm/arch/firewall.h>
+#include <asm/arch/reset_manager.h>
+#include <asm/arch/system_manager.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include "iossm_mailbox.h"
+#include "sdram_soc64.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* MPFE NOC registers */
+#define F2SDRAM_SIDEBAND_FLAGOUTSET0	0x50
+#define F2SDRAM_SIDEBAND_FLAGOUTSTATUS0	0x58
+#define SIDEBANDMGR_FLAGOUTSET0_REG	SOCFPGA_F2SDRAM_MGR_ADDRESS +\
+					F2SDRAM_SIDEBAND_FLAGOUTSET0
+#define SIDEBANDMGR_FLAGOUTSTATUS0_REG	SOCFPGA_F2SDRAM_MGR_ADDRESS +\
+					F2SDRAM_SIDEBAND_FLAGOUTSTATUS0
+#define BOOT_SCRATCH_COLD3_REG	(socfpga_get_sysmgr_addr() +\
+				 SYSMGR_SOC64_BOOT_SCRATCH_COLD3)
+#define PORT_EMIF_CONFIG_OFFSET 4
+#define EMIF_PLL_MASK	GENMASK(19, 16)
+
+#define IO96B0_DUAL_PORT_MASK		BIT(0)
+#define IO96B0_DUAL_EMIF_MASK		BIT(1)
+
+#define FIREWALL_MPFE_SCR_IO96B0_REG		0x18000d00
+#define FIREWALL_MPFE_SCR_IO96B1_REG		0x18000d04
+#define FIREWALL_MPFE_NOC_CSR_REG		0x18000d08
+
+#define MEMORY_BANK_MAX_COUNT 3
+
+/* Reset type */
+enum reset_type {
+	POR_RESET,
+	WARM_RESET,
+	COLD_RESET,
+	NCONFIG,
+	JTAG_CONFIG,
+	RSU_RECONFIG
+};
+
+phys_addr_t io96b_csr_reg_addr[] = {
+	0x18400000, /* IO96B_0 CSR registers address */
+	0x18800000  /* IO96B_1 CSR registers address */
+};
+
+struct dram_bank_info_s {
+	phys_addr_t start;
+	phys_size_t max_size;
+};
+
+struct dram_bank_info_s dram_bank_info[MEMORY_BANK_MAX_COUNT] = {
+	{0x80000000, 0x80000000},	/* Memory Bank 0 */
+	{0x880000000, 0x780000000},	/* Memory Bank 1 */
+	{0x8800000000, 0x7800000000}	/* Memory Bank 2 */
+};
+
+static enum reset_type get_reset_type(u32 reg)
+{
+	return FIELD_GET(ALT_SYSMGR_SCRATCH_REG_3_DDR_RESET_TYPE_MASK, reg);
+}
+
+static void update_io96b_assigned_to_hps(bool dual_port_flag, bool dual_emif_flag)
+{
+	clrsetbits_le32(BOOT_SCRATCH_COLD3_REG,
+			ALT_SYSMGR_SCRATCH_REG_3_DDR_PORT_EMIF_INFO_MASK,
+			FIELD_PREP(ALT_SYSMGR_SCRATCH_REG_3_DDR_PORT_INFO_MASK, dual_port_flag) |
+			FIELD_PREP(ALT_SYSMGR_SCRATCH_REG_3_DDR_EMIF_INFO_MASK, dual_emif_flag));
+
+	debug("%s: update dual port dual emif info: 0x%x\n", __func__,
+	      readl(BOOT_SCRATCH_COLD3_REG));
+}
+
+static void set_mpfe_config(void)
+{
+	/* Set mpfe_lite_intfcsel */
+	setbits_le32(socfpga_get_sysmgr_addr() + SYSMGR_SOC64_MPFE_CONFIG, BIT(2));
+
+	/* Set mpfe_lite_active */
+	setbits_le32(socfpga_get_sysmgr_addr() + SYSMGR_SOC64_MPFE_CONFIG, BIT(8));
+
+	debug("%s: mpfe_config: 0x%x\n", __func__,
+	      readl(socfpga_get_sysmgr_addr() + SYSMGR_SOC64_MPFE_CONFIG));
+}
+
+static bool is_ddr_init_hang(void)
+{
+	u32 reg = readl(socfpga_get_sysmgr_addr() +
+			SYSMGR_SOC64_BOOT_SCRATCH_POR0);
+
+	debug("%s: 0x%x\n", __func__, reg);
+
+	if (reg & ALT_SYSMGR_SCRATCH_REG_POR_0_DDR_PROGRESS_MASK)
+		return true;
+
+	return false;
+}
+
+static void ddr_init_inprogress(bool start)
+{
+	if (start)
+		setbits_le32(socfpga_get_sysmgr_addr() +
+				SYSMGR_SOC64_BOOT_SCRATCH_POR0,
+				ALT_SYSMGR_SCRATCH_REG_POR_0_DDR_PROGRESS_MASK);
+	else
+		clrbits_le32(socfpga_get_sysmgr_addr() +
+				SYSMGR_SOC64_BOOT_SCRATCH_POR0,
+				ALT_SYSMGR_SCRATCH_REG_POR_0_DDR_PROGRESS_MASK);
+}
+
+static void populate_ddr_handoff(struct udevice *dev, struct io96b_info *io96b_ctrl)
+{
+	struct altera_sdram_plat *plat = dev_get_plat(dev);
+	int i;
+	u32 len = SOC64_HANDOFF_SDRAM_LEN;
+	u32 handoff_table[len];
+
+	/* Read handoff for DDR configuration */
+	socfpga_handoff_read((void *)SOC64_HANDOFF_SDRAM, handoff_table, len);
+
+	/* Read handoff - dual port */
+	plat->dualport = FIELD_GET(IO96B0_DUAL_PORT_MASK, handoff_table[PORT_EMIF_CONFIG_OFFSET]);
+	debug("%s: dualport from handoff: 0x%x\n", __func__, plat->dualport);
+
+	if (plat->dualport)
+		io96b_ctrl->num_port = 2;
+	else
+		io96b_ctrl->num_port = 1;
+
+	/* Read handoff - dual EMIF */
+	plat->dualemif = FIELD_GET(IO96B0_DUAL_EMIF_MASK, handoff_table[PORT_EMIF_CONFIG_OFFSET]);
+	debug("%s: dualemif from handoff: 0x%x\n", __func__, plat->dualemif);
+
+	if (plat->dualemif)
+		io96b_ctrl->num_instance = 2;
+	else
+		io96b_ctrl->num_instance = 1;
+
+	io96b_ctrl->io96b_pll = FIELD_GET(EMIF_PLL_MASK,
+					  handoff_table[PORT_EMIF_CONFIG_OFFSET]);
+	debug("%s: io96b enabled pll from handoff: 0x%x\n", __func__, io96b_ctrl->io96b_pll);
+
+	update_io96b_assigned_to_hps(plat->dualport, plat->dualemif);
+
+	/* Assign IO96B CSR base address if it is valid */
+	for (i = 0; i < io96b_ctrl->num_instance; i++) {
+		io96b_ctrl->io96b[i].io96b_csr_addr = io96b_csr_reg_addr[i];
+		debug("%s: IO96B 0x%llx CSR enabled\n", __func__,
+		      io96b_ctrl->io96b[i].io96b_csr_addr);
+	}
+}
+
+static void config_mpfe_sideband_mgr(struct udevice *dev)
+{
+	struct altera_sdram_plat *plat = dev_get_plat(dev);
+
+	/* Dual port setting */
+	if (plat->dualport)
+		setbits_le32(SIDEBANDMGR_FLAGOUTSET0_REG, BIT(4));
+
+	/* Dual EMIF setting */
+	if (plat->dualemif) {
+		set_mpfe_config();
+		setbits_le32(SIDEBANDMGR_FLAGOUTSET0_REG, BIT(5));
+	}
+
+	debug("%s: SIDEBANDMGR_FLAGOUTSTATUS0: 0x%x\n", __func__,
+	      readl(SIDEBANDMGR_FLAGOUTSTATUS0_REG));
+}
+
+static void config_ccu_mgr(struct udevice *dev)
+{
+	int ret = 0;
+	struct altera_sdram_plat *plat = dev_get_plat(dev);
+
+	if (plat->dualport || plat->dualemif) {
+		debug("%s: config interleaving on ccu reg\n", __func__);
+		ret = uclass_get_device_by_name(UCLASS_NOP,
+						"socfpga-ccu-ddr-interleaving-on", &dev);
+	} else {
+		debug("%s: config interleaving off ccu reg\n", __func__);
+		ret = uclass_get_device_by_name(UCLASS_NOP,
+						"socfpga-ccu-ddr-interleaving-off", &dev);
+	}
+
+	if (ret) {
+		printf("interleaving on/off ccu settings init failed: %d\n", ret);
+		hang();
+	}
+}
+
+static void config_firewall_mpfe_csr(struct udevice *dev)
+{
+	int ret = 0;
+
+	debug("%s: config Firewall setting for MPFE CSR\n", __func__);
+	ret = uclass_get_device_by_name(UCLASS_NOP,
+					"socfpga-noc-fw-mpfe-csr", &dev);
+
+	if (ret) {
+		printf("Firewall setting for MPFE CSR init failed: %d\n", ret);
+		hang();
+	}
+}
+
+static bool hps_ocram_dbe_status(void)
+{
+	u32 reg = readl(BOOT_SCRATCH_COLD3_REG);
+
+	if (reg & ALT_SYSMGR_SCRATCH_REG_3_OCRAM_DBE_MASK)
+		return true;
+
+	return false;
+}
+
+int sdram_mmr_init_full(struct udevice *dev)
+{
+	int i, ret = 0;
+	phys_size_t hw_size;
+	struct altera_sdram_plat *plat = dev_get_plat(dev);
+	struct altera_sdram_priv *priv = dev_get_priv(dev);
+	struct io96b_info *io96b_ctrl = malloc(sizeof(*io96b_ctrl));
+
+	u32 reg = readl(BOOT_SCRATCH_COLD3_REG);
+	enum reset_type reset_t = get_reset_type(reg);
+	bool full_mem_init = false;
+
+	/* DDR initialization progress status tracking */
+	bool is_ddr_hang_be4_rst = is_ddr_init_hang();
+
+	debug("DDR: SDRAM init in progress ...\n");
+	ddr_init_inprogress(true);
+
+	gd->bd = (struct bd_info *)malloc(sizeof(struct bd_info));
+	memset(gd->bd, '\0', sizeof(struct bd_info));
+
+	debug("DDR: Address MPFE 0x%llx\n", plat->mpfe_base_addr);
+
+	/* Populating DDR handoff data */
+	debug("DDR: Checking SDRAM configuration in progress ...\n");
+	populate_ddr_handoff(dev, io96b_ctrl);
+
+	/* Configuring MPFE sideband manager registers - dual port & dual emif */
+	config_mpfe_sideband_mgr(dev);
+
+	/* Configuring Interleave/Non-interleave ccu registers */
+	config_ccu_mgr(dev);
+
+	/* Configure if polling is needed for IO96B GEN PLL locked */
+	io96b_ctrl->ckgen_lock = true;
+
+	/* Ensure calibration status passing */
+	init_mem_cal(io96b_ctrl);
+
+	printf("DDR: Calibration success\n");
+
+	/* Initiate IOSSM mailbox */
+	io96b_mb_init(io96b_ctrl);
+
+	/* DDR type, DDR size and ECC status) */
+	ret = get_mem_technology(io96b_ctrl);
+	if (ret) {
+		printf("DDR: Failed to get DDR type\n");
+
+		goto err;
+	}
+
+	ret = get_mem_width_info(io96b_ctrl);
+	if (ret) {
+		printf("DDR: Failed to get DDR size\n");
+
+		goto err;
+	}
+
+	hw_size = (phys_size_t)io96b_ctrl->overall_size * SZ_1G / SZ_8;
+
+	/* Get bank configuration from devicetree */
+	ret = fdtdec_decode_ram_size(gd->fdt_blob, NULL, 0, NULL,
+				     (phys_size_t *)&gd->ram_size, gd->bd);
+	if (ret) {
+		puts("DDR: Failed to decode memory node\n");
+		ret = -ENXIO;
+
+		goto err;
+	}
+
+	if (gd->ram_size > hw_size) {
+		printf("DDR: Warning: DRAM size from device tree (%lld MiB) exceeds\n",
+		       gd->ram_size >> 20);
+		printf(" the actual hardware capacity(%lld MiB). Memory configuration will be\n",
+		       hw_size >> 20);
+		printf(" adjusted to match the detected hardware size.\n");
+		gd->ram_size = 0;
+	}
+
+	if (gd->ram_size > 0 && gd->ram_size != hw_size) {
+		printf("DDR: Warning: DRAM size from device tree (%lld MiB)\n",
+		       gd->ram_size >> 20);
+		printf(" mismatch with hardware capacity(%lld MiB).\n",
+		       hw_size >> 20);
+	}
+
+	if (gd->ram_size == 0 && hw_size > 0) {
+		phys_size_t remaining_size, size_counter = 0;
+		u8 config_dram_banks;
+
+		if (CONFIG_NR_DRAM_BANKS > MEMORY_BANK_MAX_COUNT) {
+			printf("DDR: Warning: CONFIG_NR_DRAM_BANKS(%d) is bigger than Max Memory Bank count(%d).\n",
+			       CONFIG_NR_DRAM_BANKS, MEMORY_BANK_MAX_COUNT);
+			printf(" Max Memory Bank count is in use instead of CONFIG_NR_DRAM_BANKS.\n");
+			config_dram_banks = MEMORY_BANK_MAX_COUNT;
+		} else {
+			config_dram_banks = CONFIG_NR_DRAM_BANKS;
+		}
+
+		for (i = 0; i < config_dram_banks; i++) {
+			remaining_size = hw_size - size_counter;
+			if (remaining_size <= dram_bank_info[i].max_size) {
+				gd->bd->bi_dram[i].start = dram_bank_info[i].start;
+				gd->bd->bi_dram[i].size = remaining_size;
+				debug("Memory bank[%d]  Starting address: 0x%llx  size: 0x%llx\n",
+				      i, gd->bd->bi_dram[i].start, gd->bd->bi_dram[i].size);
+				break;
+			}
+
+			gd->bd->bi_dram[i].start = dram_bank_info[i].start;
+			gd->bd->bi_dram[i].size = dram_bank_info[i].max_size;
+
+			debug("Memory bank[%d]  Starting address: 0x%llx  size: 0x%llx\n",
+			      i, gd->bd->bi_dram[i].start, gd->bd->bi_dram[i].size);
+			size_counter += gd->bd->bi_dram[i].size;
+		}
+
+		gd->ram_size = hw_size;
+	}
+
+	printf("%s: %lld MiB\n", io96b_ctrl->ddr_type, gd->ram_size >> 20);
+
+	ret = ecc_enable_status(io96b_ctrl);
+	if (ret) {
+		printf("DDR: Failed to get ECC enabled status\n");
+
+		goto err;
+	}
+
+	/* Is HPS cold or warm reset? If yes, Skip full memory initialization if ECC
+	 *  enabled to preserve memory content
+	 */
+	if (io96b_ctrl->ecc_status) {
+		if (ecc_interrupt_status(io96b_ctrl)) {
+			if (CONFIG_IS_ENABLED(WDT)) {
+				struct udevice *wdt;
+
+				printf("DDR: ECC error recover start now\n");
+				ret = uclass_first_device_err(UCLASS_WDT, &wdt);
+				if (ret) {
+					printf("DDR: Failed to trigger watchdog reset\n");
+					hang();
+				}
+
+				wdt_expire_now(wdt, 0);
+			}
+			hang();
+		}
+
+		full_mem_init = hps_ocram_dbe_status() | is_ddr_hang_be4_rst;
+		if (full_mem_init || !(reset_t == WARM_RESET || reset_t == COLD_RESET)) {
+			ret = bist_mem_init_start(io96b_ctrl);
+			if (ret) {
+				printf("DDR: Failed to fully initialize DDR memory\n");
+
+				goto err;
+			}
+		}
+
+		printf("SDRAM-ECC: Initialized success\n");
+	}
+
+	sdram_size_check(gd->bd);
+	printf("DDR: size check success\n");
+
+	sdram_set_firewall(gd->bd);
+
+	/* Firewall setting for MPFE CSR */
+	config_firewall_mpfe_csr(dev);
+
+	printf("DDR: firewall init success\n");
+
+	priv->info.base = gd->bd->bi_dram[0].start;
+	priv->info.size = gd->ram_size;
+
+	/* Ending DDR driver initialization success tracking */
+	ddr_init_inprogress(false);
+
+	printf("DDR: init success\n");
+
+err:
+	free(io96b_ctrl);
+
+	return ret;
+}
diff --git a/drivers/ddr/altera/sdram_soc64.c b/drivers/ddr/altera/sdram_soc64.c
index 10a8e64af3d..c8c9211adce 100644
--- a/drivers/ddr/altera/sdram_soc64.c
+++ b/drivers/ddr/altera/sdram_soc64.c
@@ -1,6 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0
 /*
  * Copyright (C) 2016-2022 Intel Corporation <www.intel.com>
+ * Copyright (C) 2025 Altera Corporation <www.altera.com>
  *
  */
 
@@ -28,6 +29,7 @@
 
 #define PGTABLE_OFF	0x4000
 
+#if !IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5)
 u32 hmc_readl(struct altera_sdram_plat *plat, u32 reg)
 {
 	return readl(plat->iomhc + reg);
@@ -99,8 +101,9 @@ int emif_reset(struct altera_sdram_plat *plat)
 	debug("DDR: %s triggered successly\n", __func__);
 	return 0;
 }
+#endif
 
-#if !IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X)
+#if !(IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X) || IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5))
 int poll_hmc_clock_status(void)
 {
 	return wait_for_bit_le32((const void *)(socfpga_get_sysmgr_addr() +
@@ -252,7 +255,7 @@ phys_size_t sdram_calculate_size(struct altera_sdram_plat *plat)
 	return size;
 }
 
-void sdram_set_firewall(struct bd_info *bd)
+static void sdram_set_firewall_non_f2sdram(struct bd_info *bd)
 {
 	u32 i;
 	phys_size_t value;
@@ -288,7 +291,7 @@ void sdram_set_firewall(struct bd_info *bd)
 				      FW_MPU_DDR_SCR_NONMPUREGION0ADDR_BASEEXT +
 				      (i * 4 * sizeof(u32)));
 
-		/* Setting non-secure MPU limit and limit extexded */
+		/* Setting non-secure MPU limit and limit extended */
 		value = bd->bi_dram[i].start + bd->bi_dram[i].size - 1;
 
 		lower = lower_32_bits(value);
@@ -301,7 +304,7 @@ void sdram_set_firewall(struct bd_info *bd)
 				      FW_MPU_DDR_SCR_MPUREGION0ADDR_LIMITEXT +
 				      (i * 4 * sizeof(u32)));
 
-		/* Setting non-secure Non-MPU limit and limit extexded */
+		/* Setting non-secure Non-MPU limit and limit extended */
 		FW_MPU_DDR_SCR_WRITEL(lower,
 				      FW_MPU_DDR_SCR_NONMPUREGION0ADDR_LIMIT +
 				      (i * 4 * sizeof(u32)));
@@ -314,15 +317,77 @@ void sdram_set_firewall(struct bd_info *bd)
 	}
 }
 
+#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5)
+static void sdram_set_firewall_f2sdram(struct bd_info *bd)
+{
+	u32 i, lower, upper;
+	phys_size_t value;
+
+	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
+		if (!bd->bi_dram[i].size)
+			continue;
+
+		value = bd->bi_dram[i].start;
+
+		/* Keep first 1MB of SDRAM memory region as secure region when
+		 * using ATF flow, where the ATF code is located.
+		 */
+		if (IS_ENABLED(CONFIG_SPL_ATF) && i == 0)
+			value += SZ_1M;
+
+		/* Setting base and base extended */
+		lower = lower_32_bits(value);
+		upper = upper_32_bits(value);
+		FW_F2SDRAM_DDR_SCR_WRITEL(lower,
+					  FW_F2SDRAM_DDR_SCR_REGION0ADDR_BASE +
+					  (i * 4 * sizeof(u32)));
+		FW_F2SDRAM_DDR_SCR_WRITEL(upper & 0xff,
+					  FW_F2SDRAM_DDR_SCR_REGION0ADDR_BASEEXT +
+					  (i * 4 * sizeof(u32)));
+
+		/* Setting limit and limit extended */
+		value = bd->bi_dram[i].start + bd->bi_dram[i].size - 1;
+
+		lower = lower_32_bits(value);
+		upper = upper_32_bits(value);
+
+		FW_F2SDRAM_DDR_SCR_WRITEL(lower,
+					  FW_F2SDRAM_DDR_SCR_REGION0ADDR_LIMIT +
+					  (i * 4 * sizeof(u32)));
+		FW_F2SDRAM_DDR_SCR_WRITEL(upper & 0xff,
+					  FW_F2SDRAM_DDR_SCR_REGION0ADDR_LIMITEXT +
+					  (i * 4 * sizeof(u32)));
+
+		FW_F2SDRAM_DDR_SCR_WRITEL(BIT(i), FW_F2SDRAM_DDR_SCR_EN_SET);
+	}
+}
+#endif
+
+void sdram_set_firewall(struct bd_info *bd)
+{
+	sdram_set_firewall_non_f2sdram(bd);
+
+#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5)
+	sdram_set_firewall_f2sdram(bd);
+#endif
+}
+
 static int altera_sdram_of_to_plat(struct udevice *dev)
 {
+#if !IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X)
 	struct altera_sdram_plat *plat = dev_get_plat(dev);
 	fdt_addr_t addr;
+#endif
 
 	/* These regs info are part of DDR handoff in bitstream */
 #if IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X)
 	return 0;
-#endif
+#elif IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5)
+	addr = dev_read_addr_index(dev, 0);
+	if (addr == FDT_ADDR_T_NONE)
+		return -EINVAL;
+	plat->mpfe_base_addr = addr;
+#else
 
 	addr = dev_read_addr_index(dev, 0);
 	if (addr == FDT_ADDR_T_NONE)
@@ -338,7 +403,7 @@ static int altera_sdram_of_to_plat(struct udevice *dev)
 	if (addr == FDT_ADDR_T_NONE)
 		return -EINVAL;
 	plat->hmc = (void __iomem *)addr;
-
+#endif
 	return 0;
 }
 
@@ -385,6 +450,7 @@ static const struct udevice_id altera_sdram_ids[] = {
 	{ .compatible = "altr,sdr-ctl-s10" },
 	{ .compatible = "intel,sdr-ctl-agilex" },
 	{ .compatible = "intel,sdr-ctl-n5x" },
+	{ .compatible = "intel,sdr-ctl-agilex5" },
 	{ /* sentinel */ }
 };
 
diff --git a/drivers/ddr/altera/sdram_soc64.h b/drivers/ddr/altera/sdram_soc64.h
index 87a70a861ba..183b1a33080 100644
--- a/drivers/ddr/altera/sdram_soc64.h
+++ b/drivers/ddr/altera/sdram_soc64.h
@@ -1,6 +1,8 @@
 /* SPDX-License-Identifier: GPL-2.0 */
 /*
  * Copyright (C) 2017-2019 Intel Corporation <www.intel.com>
+ * Copyright (C) 2025 Altera Corporation <www.altera.com>
+ *
  */
 
 #ifndef	_SDRAM_SOC64_H_
@@ -13,11 +15,19 @@ struct altera_sdram_priv {
 	struct reset_ctl_bulk resets;
 };
 
+#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5)
+struct altera_sdram_plat {
+	fdt_addr_t mpfe_base_addr;
+	bool dualport;
+	bool dualemif;
+};
+#else
 struct altera_sdram_plat {
 	void __iomem *hmc;
 	void __iomem *ddr_sch;
 	void __iomem *iomhc;
 };
+#endif
 
 /* ECC HMC registers */
 #define DDRIOCTRL			0x8
diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig
index 3c64e894646..4b47be6b016 100644
--- a/drivers/dma/Kconfig
+++ b/drivers/dma/Kconfig
@@ -76,6 +76,13 @@ config XILINX_DPDMA
 	  this file is used as placeholder for driver. The main reason is
 	  to record compatible string and calling power domain driver.
 
+config ADI_DMA
+	bool "ADI DMA driver"
+	depends on DMA && DMA_CHANNELS
+	help
+	  Enable DMA support for Analog Devices SOCs, such as the SC5xx.
+	  Currently this is a minimalistic driver tested against OSPI use only.
+
 if APBH_DMA
 config APBH_DMA_BURST
 	bool "Enable DMA BURST"
diff --git a/drivers/dma/Makefile b/drivers/dma/Makefile
index 48811eaaeb3..00d765864cd 100644
--- a/drivers/dma/Makefile
+++ b/drivers/dma/Makefile
@@ -13,5 +13,6 @@ obj-$(CONFIG_TI_KSNAV) += keystone_nav.o keystone_nav_cfg.o
 obj-$(CONFIG_TI_EDMA3) += ti-edma3.o
 obj-$(CONFIG_DMA_LPC32XX) += lpc32xx_dma.o
 obj-$(CONFIG_XILINX_DPDMA) += xilinx_dpdma.o
+obj-$(CONFIG_ADI_DMA) += adi_dma.o
 
 obj-y += ti/
diff --git a/drivers/dma/adi_dma.c b/drivers/dma/adi_dma.c
new file mode 100644
index 00000000000..28afe488db0
--- /dev/null
+++ b/drivers/dma/adi_dma.c
@@ -0,0 +1,253 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Analog Devices DMA controller driver
+ *
+ * (C) Copyright 2024 - Analog Devices, Inc.
+ *
+ * Written and/or maintained by Timesys Corporation
+ *
+ * Contact: Nathan Barrett-Morrison <nathan.morrison@timesys.com>
+ * Contact: Greg Malysa <greg.malysa@timesys.com>
+ * Contact: Ian Roberts <ian.roberts@timesys.com>
+ *
+ */
+#include <dm.h>
+#include <dma.h>
+#include <dma-uclass.h>
+#include <dm/device_compat.h>
+#include <linux/errno.h>
+#include <linux/io.h>
+
+#define HAS_MDMA	BIT(0)
+
+#define REG_ADDRSTART	0x04
+#define REG_CFG		0x08
+#define REG_XCNT	0x0C
+#define REG_XMOD	0x10
+#define REG_STAT	0x30
+
+#define BITP_DMA_CFG_MSIZE                        8
+#define BITP_DMA_CFG_PSIZE                        4
+#define BITM_DMA_CFG_WNR                 0x00000002
+#define BITM_DMA_CFG_EN                  0x00000001
+#define ENUM_DMA_CFG_XCNT_INT            0x00100000
+
+#define BITP_DMA_STAT_PBWID                      12
+#define BITP_DMA_STAT_ERRC                        4
+#define BITM_DMA_STAT_PBWID              0x00003000
+#define BITM_DMA_STAT_ERRC               0x00000070
+#define BITM_DMA_STAT_PIRQ               0x00000004
+#define BITM_DMA_STAT_IRQERR             0x00000002
+#define BITM_DMA_STAT_IRQDONE            0x00000001
+
+#define DMA_MDMA_SRC_DEFAULT_CONFIG(psize, msize) \
+	(BITM_DMA_CFG_EN | ((psize) << BITP_DMA_CFG_PSIZE) | ((msize) << BITP_DMA_CFG_MSIZE))
+#define DMA_MDMA_DST_DEFAULT_CONFIG(psize, msize) \
+	(BITM_DMA_CFG_EN | BITM_DMA_CFG_WNR | ENUM_DMA_CFG_XCNT_INT | \
+	((psize) << BITP_DMA_CFG_PSIZE) | ((msize) << BITP_DMA_CFG_MSIZE))
+
+struct adi_dma_channel {
+	int id;
+	struct adi_dma *dma;
+	void __iomem *iosrc;
+	void __iomem *iodest;
+};
+
+struct adi_dma {
+	struct udevice *dev;
+	struct adi_dma_channel channels[1];
+	void __iomem *ioaddr;
+	unsigned long hw_cfg;
+};
+
+static const struct udevice_id dma_dt_ids[] = {
+	{ .compatible = "adi,mdma-controller", .data = HAS_MDMA },
+	{ }
+};
+
+static u8 adi_dma_get_msize(u32 n_bytecount, u32 n_address)
+{
+	/* Calculate MSIZE, PSIZE, XCNT and XMOD */
+	u8 n_msize = 0;
+	u32 n_value = n_bytecount | n_address;
+	u32 n_mask = 0x1;
+
+	for (n_msize = 0; n_msize < 5; n_msize++, n_mask <<= 1) {
+		if ((n_value & n_mask) == n_mask)
+			break;
+	}
+
+	return n_msize;
+}
+
+static int adi_dma_get_ch_error(void __iomem *ch)
+{
+	u32 cause = (ioread32(ch + REG_STAT) &  BITM_DMA_STAT_ERRC) >>
+		    BITP_DMA_STAT_ERRC;
+	switch (cause) {
+	case 0:
+		return -EINVAL;
+	case 1:
+		return -EBUSY;
+	case 2:
+		return -EFAULT;
+	case 3:
+		fallthrough;
+	case 5:
+		fallthrough;
+	case 6:
+		fallthrough;
+	default:
+		return -EIO;
+	}
+}
+
+static int adi_mdma_transfer(struct udevice *dev, int direction,
+			     dma_addr_t dst, dma_addr_t src, size_t len)
+{
+	struct adi_dma *priv = dev_get_priv(dev);
+	void __iomem *chsrc = priv->channels[0].iosrc;
+	void __iomem *chdst = priv->channels[0].iodest;
+
+	int result = 0;
+	u32 reg;
+	u32 bytecount = len;
+
+	u8 n_srcmsize;
+	u8 n_dstmsize;
+	u8 n_srcpsize;
+	u8 n_dstpsize;
+	u8 n_psize;
+	u32 srcconfig;
+	u32 dstconfig;
+	u8 srcpsizemax = (ioread32(chsrc + REG_STAT) & BITM_DMA_STAT_PBWID) >>
+			 BITP_DMA_STAT_PBWID;
+	u8 dstpsizemax = (ioread32(chdst + REG_STAT) & BITM_DMA_STAT_PBWID) >>
+			 BITP_DMA_STAT_PBWID;
+
+	const u32 CLRSTAT = (BITM_DMA_STAT_IRQDONE | BITM_DMA_STAT_IRQERR |
+			     BITM_DMA_STAT_PIRQ);
+
+	if (len == 0)
+		return -EINVAL;
+
+	/* Clear DMA status */
+	iowrite32(CLRSTAT, chsrc + REG_STAT);
+	iowrite32(CLRSTAT, chdst + REG_STAT);
+
+	/* Calculate MSIZE, PSIZE, XCNT and XMOD */
+	n_srcmsize = adi_dma_get_msize(bytecount, src);
+	n_dstmsize = adi_dma_get_msize(bytecount, dst);
+	n_srcpsize = min(n_srcmsize, srcpsizemax);
+	n_dstpsize = min(n_dstmsize, dstpsizemax);
+	n_psize = min(n_srcpsize, n_dstpsize);
+
+	srcconfig = DMA_MDMA_SRC_DEFAULT_CONFIG(n_psize, n_srcmsize);
+	dstconfig = DMA_MDMA_DST_DEFAULT_CONFIG(n_psize, n_dstmsize);
+
+	/* Load the DMA descriptors */
+	iowrite32(src,			chsrc + REG_ADDRSTART);
+	iowrite32(bytecount >> n_srcmsize,	chsrc + REG_XCNT);
+	iowrite32(1 << n_srcmsize,		chsrc + REG_XMOD);
+	iowrite32(dst,			chdst + REG_ADDRSTART);
+	iowrite32(bytecount >> n_dstmsize,	chdst + REG_XCNT);
+	iowrite32(1 << n_dstmsize,		chdst + REG_XMOD);
+
+	iowrite32(dstconfig, chdst + REG_CFG);
+	iowrite32(srcconfig, chsrc + REG_CFG);
+
+	/* Wait for DMA to complete while checking for a DMA error */
+	do {
+		reg = ioread32(chsrc + REG_STAT);
+		if ((reg & BITM_DMA_STAT_IRQERR) == BITM_DMA_STAT_IRQERR) {
+			result = adi_dma_get_ch_error(chsrc);
+			break;
+		}
+		reg = ioread32(chdst + REG_STAT);
+		if ((reg & BITM_DMA_STAT_IRQERR) == BITM_DMA_STAT_IRQERR) {
+			result = adi_dma_get_ch_error(chdst);
+			break;
+		}
+	} while ((reg & BITM_DMA_STAT_IRQDONE) == 0);
+
+	clrbits_32(chsrc + REG_CFG, 1);
+	clrbits_32(chdst + REG_CFG, 1);
+
+	return result;
+}
+
+static int adi_dma_init_channel(struct adi_dma *dma,
+				struct adi_dma_channel *channel, ofnode node)
+{
+	u32 offset;
+
+	if (ofnode_read_u32(node, "adi,id", &channel->id)) {
+		dev_err(dma->dev, "Missing adi,id for channel %s\n",
+			ofnode_get_name(node));
+		return -ENOENT;
+	}
+
+	if (ofnode_read_u32(node, "adi,src-offset", &offset)) {
+		dev_err(dma->dev, "Missing adi,src-offset for channel %s\n",
+			ofnode_get_name(node));
+		return -ENOENT;
+	}
+
+	channel->iosrc = dma->ioaddr + offset;
+	channel->dma = dma;
+
+	if (dma->hw_cfg & HAS_MDMA) {
+		if (ofnode_read_u32(node, "adi,dest-offset", &offset)) {
+			dev_err(dma->dev,
+				"Missing adi,dest-offset for channel %s\n",
+				ofnode_get_name(node));
+			return -ENOENT;
+		}
+		channel->iodest = dma->ioaddr + offset;
+	}
+
+	return 0;
+}
+
+static int adi_dma_probe(struct udevice *dev)
+{
+	struct dma_dev_priv *uc_priv = dev_get_uclass_priv(dev);
+	struct adi_dma *priv = dev_get_priv(dev);
+	ofnode node, child;
+
+	priv->hw_cfg = dev_get_driver_data(dev);
+	if (priv->hw_cfg & HAS_MDMA)
+		uc_priv->supported = DMA_SUPPORTS_MEM_TO_MEM;
+
+	priv->ioaddr = dev_remap_addr(dev);
+	if (!priv->ioaddr)
+		return -EINVAL;
+
+	node = dev_read_first_subnode(dev);
+	if (!ofnode_valid(node)) {
+		dev_err(dev,
+			"Error: device tree DMA channel config missing!\n");
+		return -ENODEV;
+	}
+
+	node = dev_ofnode(dev);
+	ofnode_for_each_subnode(child, node) {
+		adi_dma_init_channel(priv, priv->channels, child);
+		break; //Only 1 channel supported for now
+	}
+
+	return 0;
+}
+
+static const struct dma_ops adi_dma_ops = {
+	.transfer = adi_mdma_transfer,
+};
+
+U_BOOT_DRIVER(adi_dma) = {
+	.name = "adi_dma",
+	.id = UCLASS_DMA,
+	.of_match = dma_dt_ids,
+	.ops = &adi_dma_ops,
+	.probe = adi_dma_probe,
+	.priv_auto = sizeof(struct adi_dma),
+};
diff --git a/drivers/dma/ti/Makefile b/drivers/dma/ti/Makefile
index 94ec13ba7ca..90c20a6a3fa 100644
--- a/drivers/dma/ti/Makefile
+++ b/drivers/dma/ti/Makefile
@@ -5,6 +5,7 @@ obj-$(CONFIG_TI_K3_PSIL) += k3-psil-data.o
 k3-psil-data-y += k3-psil.o
 k3-psil-data-$(CONFIG_SOC_K3_AM654) += k3-psil-am654.o
 k3-psil-data-$(CONFIG_SOC_K3_J721E) += k3-psil-j721e.o
+k3-psil-data-$(CONFIG_SOC_K3_J7200) += k3-psil-j721e.o
 k3-psil-data-$(CONFIG_SOC_K3_J721S2) += k3-psil-j721s2.o
 k3-psil-data-$(CONFIG_SOC_K3_AM642) += k3-psil-am64.o
 k3-psil-data-$(CONFIG_SOC_K3_AM625) += k3-psil-am62.o
diff --git a/drivers/dma/ti/k3-psil.c b/drivers/dma/ti/k3-psil.c
index 369e679886f..39798844a8a 100644
--- a/drivers/dma/ti/k3-psil.c
+++ b/drivers/dma/ti/k3-psil.c
@@ -20,6 +20,8 @@ struct psil_endpoint_config *psil_get_ep_config(u32 thread_id)
 			soc_ep_map = &am654_ep_map;
 		else if (IS_ENABLED(CONFIG_SOC_K3_J721E))
 			soc_ep_map = &j721e_ep_map;
+		else if (IS_ENABLED(CONFIG_SOC_K3_J7200))
+			soc_ep_map = &j721e_ep_map;
 		else if (IS_ENABLED(CONFIG_SOC_K3_J721S2))
 			soc_ep_map = &j721s2_ep_map;
 		else if (IS_ENABLED(CONFIG_SOC_K3_AM642))
diff --git a/drivers/dma/ti/k3-udma.c b/drivers/dma/ti/k3-udma.c
index 3013c4741d0..723265ab2e5 100644
--- a/drivers/dma/ti/k3-udma.c
+++ b/drivers/dma/ti/k3-udma.c
@@ -36,6 +36,7 @@
 #include "k3-psil-priv.h"
 
 #define K3_UDMA_MAX_RFLOWS 1024
+#define K3_UDMA_MAX_TR 2
 
 struct udma_chan;
 
@@ -74,7 +75,6 @@ struct udma_tchan {
 	struct k3_nav_ring *t_ring; /* Transmit ring */
 	struct k3_nav_ring *tc_ring; /* Transmit Completion ring */
 	int tflow_id; /* applicable only for PKTDMA */
-
 };
 
 #define udma_bchan udma_tchan
@@ -175,6 +175,7 @@ struct udma_dev {
 	struct udma_rflow *rflows;
 
 	struct udma_match_data *match_data;
+	void *bc_desc;
 
 	struct udma_chan *channels;
 	u32 psil_base;
@@ -1349,6 +1350,7 @@ static int udma_setup_resources(struct udma_dev *ud)
 	struct ti_sci_resource_desc *rm_desc;
 	struct ti_sci_resource *rm_res;
 	struct udma_tisci_rm *tisci_rm = &ud->tisci_rm;
+	size_t desc_size;
 
 	ud->tchan_map = devm_kmalloc_array(dev, BITS_TO_LONGS(ud->tchan_cnt),
 					   sizeof(unsigned long), GFP_KERNEL);
@@ -1366,9 +1368,11 @@ static int udma_setup_resources(struct udma_dev *ud)
 	ud->rflows = devm_kcalloc(dev, ud->rflow_cnt, sizeof(*ud->rflows),
 				  GFP_KERNEL);
 
+	desc_size = cppi5_trdesc_calc_size(K3_UDMA_MAX_TR, sizeof(struct cppi5_tr_type15_t));
+	ud->bc_desc = devm_kzalloc(dev, ALIGN(desc_size, ARCH_DMA_MINALIGN), GFP_KERNEL);
 	if (!ud->tchan_map || !ud->rchan_map || !ud->rflow_map ||
 	    !ud->rflow_map_reserved || !ud->tchans || !ud->rchans ||
-	    !ud->rflows)
+	    !ud->rflows || !ud->bc_desc)
 		return -ENOMEM;
 
 	/*
@@ -1444,6 +1448,7 @@ static int bcdma_setup_resources(struct udma_dev *ud)
 	struct ti_sci_resource_desc *rm_desc;
 	struct ti_sci_resource *rm_res;
 	struct udma_tisci_rm *tisci_rm = &ud->tisci_rm;
+	size_t desc_size;
 
 	ud->bchan_map = devm_kmalloc_array(dev, BITS_TO_LONGS(ud->bchan_cnt),
 					   sizeof(unsigned long), GFP_KERNEL);
@@ -1460,9 +1465,12 @@ static int bcdma_setup_resources(struct udma_dev *ud)
 	ud->rflows = devm_kcalloc(dev, ud->rchan_cnt, sizeof(*ud->rflows),
 				  GFP_KERNEL);
 
+	desc_size = cppi5_trdesc_calc_size(K3_UDMA_MAX_TR, sizeof(struct cppi5_tr_type15_t));
+	ud->bc_desc = devm_kzalloc(dev, ALIGN(desc_size, ARCH_DMA_MINALIGN), GFP_KERNEL);
+
 	if (!ud->bchan_map || !ud->tchan_map || !ud->rchan_map ||
 	    !ud->bchans || !ud->tchans || !ud->rchans ||
-	    !ud->rflows)
+	    !ud->rflows || !ud->bc_desc)
 		return -ENOMEM;
 
 	/* Get resource ranges from tisci */
@@ -1718,8 +1726,7 @@ static int *udma_prep_dma_memcpy(struct udma_chan *uc, dma_addr_t dest,
 	int num_tr;
 	size_t tr_size = sizeof(struct cppi5_tr_type15_t);
 	u16 tr0_cnt0, tr0_cnt1, tr1_cnt0;
-	unsigned long dummy;
-	void *tr_desc;
+	void *tr_desc = uc->ud->bc_desc;
 	size_t desc_size;
 
 	if (len < SZ_64K) {
@@ -1748,9 +1755,6 @@ static int *udma_prep_dma_memcpy(struct udma_chan *uc, dma_addr_t dest,
 	}
 
 	desc_size = cppi5_trdesc_calc_size(num_tr, tr_size);
-	tr_desc = dma_alloc_coherent(desc_size, &dummy);
-	if (!tr_desc)
-		return NULL;
 	memset(tr_desc, 0, desc_size);
 
 	cppi5_trdesc_init(tr_desc, num_tr, tr_size, 0, 0);
diff --git a/drivers/firmware/ti_sci_static_data.h b/drivers/firmware/ti_sci_static_data.h
index 3370f80231d..2e61e0c7de1 100644
--- a/drivers/firmware/ti_sci_static_data.h
+++ b/drivers/firmware/ti_sci_static_data.h
@@ -16,7 +16,7 @@ struct ti_sci_resource_static_data {
 
 #if IS_ENABLED(CONFIG_K3_DM_FW)
 
-#if IS_ENABLED(CONFIG_SOC_K3_J721E)
+#if IS_ENABLED(CONFIG_SOC_K3_J721E) || IS_ENABLED(CONFIG_SOC_K3_J7200)
 static struct ti_sci_resource_static_data rm_static_data[] = {
 	/* Free rings */
 	{
diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index 21361f56e69..e11109fb56d 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -97,6 +97,15 @@ config SPL_DM_GPIO_LOOKUP_LABEL
 	  different gpios on different hardware versions
 	  for the same functionality in board code.
 
+config ADI_GPIO
+	bool "ADI GPIO driver"
+	depends on DM_GPIO && ARCH_SC5XX
+	help
+	  This driver supports GPIO banks on SC5xx processors. It
+	  supports inputs and outputs but does not support pin
+	  interrupt functionality (PINT) or other features in the
+	  Linux version of the driver.
+
 config ALTERA_PIO
 	bool "Altera PIO driver"
 	depends on DM_GPIO
@@ -545,6 +554,14 @@ config DM_PCA953X
 	  Now, max 24 bits chips and PCA953X compatible chips are
 	  supported
 
+config ADP5588_GPIO
+	bool "ADP5588 GPIO expander driver"
+	depends on DM_GPIO && DM_I2C
+	help
+	  Say yes here to support GPIO functionality of ADI ADP5588 chips.
+
+	  The ADP5588 is an 18-port I2C GPIO expander and keypad controller.
+
 config SPL_DM_PCA953X
 	bool "PCA95[357]x, PCA9698, TCA64xx, and MAX7310 I/O ports in SPL"
 	depends on SPL_DM_GPIO
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index 3f882c065d8..d426d3a2d7b 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -12,6 +12,7 @@ obj-$(CONFIG_$(PHASE_)DM_GPIO) += gpio-uclass.o
 
 obj-$(CONFIG_$(XPL_)DM_PCA953X)	+= pca953x_gpio.o
 
+obj-$(CONFIG_ADI_GPIO)		+= gpio-adi-adsp.o
 obj-$(CONFIG_ASPEED_GPIO)	+= gpio-aspeed.o
 obj-$(CONFIG_ASPEED_G7_GPIO)	+= gpio-aspeed-g7.o
 obj-$(CONFIG_ASPEED_SGPIO)	+= gpio-aspeed-sgpio.o
@@ -74,6 +75,7 @@ obj-$(CONFIG_NOMADIK_GPIO)	+= nmk_gpio.o
 obj-$(CONFIG_MAX7320_GPIO)	+= max7320_gpio.o
 obj-$(CONFIG_$(XPL_)MAX77663_GPIO)	+= max77663_gpio.o
 obj-$(CONFIG_SL28CPLD_GPIO)	+= sl28cpld-gpio.o
+obj-$(CONFIG_ADP5588_GPIO)	+= adp5588_gpio.o
 obj-$(CONFIG_ZYNQMP_GPIO_MODEPIN)	+= zynqmp_gpio_modepin.o
 obj-$(CONFIG_SLG7XL45106_I2C_GPO)	+= gpio_slg7xl45106.o
 obj-$(CONFIG_FTGPIO010)		+= ftgpio010.o
diff --git a/drivers/gpio/adp5588_gpio.c b/drivers/gpio/adp5588_gpio.c
new file mode 100644
index 00000000000..d081e169897
--- /dev/null
+++ b/drivers/gpio/adp5588_gpio.c
@@ -0,0 +1,208 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * GPIO Chip driver for Analog Devices
+ * ADP5588/ADP5587 I/O Expander and QWERTY Keypad Controller
+ *
+ * (C) Copyright 2022 - Analog Devices, Inc.
+ *
+ * Written and/or maintained by Timesys Corporation
+ *
+ * Contact: Nathan Barrett-Morrison <nathan.morrison@timesys.com>
+ * Contact: Greg Malysa <greg.malysa@timesys.com>
+ *
+ * Based on Michael Hennerich's Linux driver:
+ * Michael Hennerich <michael.hennerich@analog.com>
+ *
+ */
+
+#include <dm.h>
+#include <i2c.h>
+#include <asm-generic/gpio.h>
+
+#define ADP5588_MAXGPIO     18
+#define ADP5588_BANK(offs)  ((offs) >> 3)
+#define ADP5588_BIT(offs)   (1u << ((offs) & 0x7))
+
+#define DEV_ID          0x00    /* Device ID */
+#define GPIO_DAT_STAT1  0x14    /* GPIO Data Status, Read twice to clear */
+#define GPIO_DAT_STAT2  0x15    /* GPIO Data Status, Read twice to clear */
+#define GPIO_DAT_STAT3  0x16    /* GPIO Data Status, Read twice to clear */
+#define GPIO_DAT_OUT1   0x17    /* GPIO DATA OUT */
+#define GPIO_DAT_OUT2   0x18    /* GPIO DATA OUT */
+#define GPIO_DAT_OUT3   0x19    /* GPIO DATA OUT */
+#define GPIO_INT_EN1    0x1A    /* GPIO Interrupt Enable */
+#define GPIO_INT_EN2    0x1B    /* GPIO Interrupt Enable */
+#define GPIO_INT_EN3    0x1C    /* GPIO Interrupt Enable */
+#define KP_GPIO1        0x1D    /* Keypad or GPIO Selection */
+#define KP_GPIO2        0x1E    /* Keypad or GPIO Selection */
+#define KP_GPIO3        0x1F    /* Keypad or GPIO Selection */
+#define GPIO_DIR1       0x23    /* GPIO Data Direction */
+#define GPIO_DIR2       0x24    /* GPIO Data Direction */
+#define GPIO_DIR3       0x25	/* GPIO Data Direction */
+#define GPIO_PULL1      0x2C    /* GPIO Pull Disable */
+#define GPIO_PULL2      0x2D    /* GPIO Pull Disable */
+#define GPIO_PULL3      0x2E    /* GPIO Pull Disable */
+#define ID_MASK	        0x0F
+
+struct adp5588_gpio {
+	u8 dat_out[3];
+	u8 dir[3];
+};
+
+static int adp5588_gpio_read(struct udevice *dev, u8 reg)
+{
+	int ret;
+	u8 val;
+
+	ret = dm_i2c_read(dev, reg, &val, 1);
+
+	if (ret < 0) {
+		pr_err("%s: read error\n", __func__);
+		return ret;
+	}
+
+	return val;
+}
+
+static int adp5588_gpio_write(struct udevice *dev, u8 reg, u8 val)
+{
+	int ret;
+
+	ret = dm_i2c_write(dev, reg, &val, 1);
+	if (ret < 0) {
+		pr_err("%s: write error\n", __func__);
+		return ret;
+	}
+
+	return 0;
+}
+
+static int adp5588_get_value(struct udevice *dev, u32 offset)
+{
+	struct adp5588_gpio *plat = dev_get_plat(dev);
+	unsigned int bank = ADP5588_BANK(offset);
+	unsigned int bit = ADP5588_BIT(offset);
+	int val;
+
+	if (plat->dir[bank] & bit)
+		val = plat->dat_out[bank];
+	else
+		val = adp5588_gpio_read(dev, GPIO_DAT_STAT1 + bank);
+
+	return !!(val & bit);
+}
+
+static int adp5588_set_value(struct udevice *dev, u32 offset,
+			     int32_t value)
+{
+	unsigned int bank, bit;
+	int ret;
+	struct adp5588_gpio *plat = dev_get_plat(dev);
+
+	bank = ADP5588_BANK(offset);
+	bit = ADP5588_BIT(offset);
+
+	if (value)
+		plat->dat_out[bank] |= bit;
+	else
+		plat->dat_out[bank] &= ~bit;
+
+	ret = adp5588_gpio_write(dev, GPIO_DAT_OUT1 + bank,
+				 plat->dat_out[bank]);
+
+	return ret;
+}
+
+static int adp5588_direction_input(struct udevice *dev, u32 offset)
+{
+	int ret;
+	unsigned int bank;
+	struct adp5588_gpio *plat = dev_get_plat(dev);
+
+	bank = ADP5588_BANK(offset);
+
+	plat->dir[bank] &= ~ADP5588_BIT(offset);
+	ret = adp5588_gpio_write(dev, GPIO_DIR1 + bank, plat->dir[bank]);
+
+	return ret;
+}
+
+static int adp5588_direction_output(struct udevice *dev,
+				    u32 offset, int value)
+{
+	int ret;
+	unsigned int bank, bit;
+	struct adp5588_gpio *plat = dev_get_plat(dev);
+
+	bank = ADP5588_BANK(offset);
+	bit = ADP5588_BIT(offset);
+
+	plat->dir[bank] |= bit;
+
+	if (value)
+		plat->dat_out[bank] |= bit;
+	else
+		plat->dat_out[bank] &= ~bit;
+
+	ret = adp5588_gpio_write(dev, GPIO_DAT_OUT1 + bank,
+				 plat->dat_out[bank]);
+	ret |= adp5588_gpio_write(dev, GPIO_DIR1 + bank,
+				 plat->dir[bank]);
+
+	return ret;
+}
+
+static int adp5588_ofdata_platdata(struct udevice *dev)
+{
+	struct adp5588_gpio *plat = dev_get_plat(dev);
+	struct gpio_dev_priv *priv = dev_get_uclass_priv(dev);
+	int node = dev_of_offset(dev);
+	int ret, i, revid;
+
+	priv->gpio_count = ADP5588_MAXGPIO;
+	priv->bank_name = fdt_get_name(gd->fdt_blob, node, NULL);
+
+	ret = adp5588_gpio_read(dev, DEV_ID);
+	if (ret < 0)
+		return ret;
+
+	revid = ret & ID_MASK;
+
+	printf("ADP5588 Detected: Rev %x, Rev ID %x\n", ret, revid);
+
+	for (i = 0, ret = 0; i <= ADP5588_BANK(ADP5588_MAXGPIO); i++) {
+		plat->dat_out[i] = adp5588_gpio_read(dev, GPIO_DAT_OUT1 + i);
+		plat->dir[i] = adp5588_gpio_read(dev, GPIO_DIR1 + i);
+		ret |= adp5588_gpio_write(dev, KP_GPIO1 + i, 0);
+		ret |= adp5588_gpio_write(dev, GPIO_PULL1 + i, 0);
+		ret |= adp5588_gpio_write(dev, GPIO_INT_EN1 + i, 0);
+		if (ret) {
+			pr_err("%s: Initialization error\n", __func__);
+			return ret;
+		}
+	}
+
+	return 0;
+}
+
+static const struct dm_gpio_ops adp5588_ops = {
+	.direction_input  = adp5588_direction_input,
+	.direction_output = adp5588_direction_output,
+	.get_value		  = adp5588_get_value,
+	.set_value		  = adp5588_set_value,
+};
+
+static const struct udevice_id adp5588_of_match_list[] = {
+	{ .compatible = "adi,adp5588"},
+	{ /* sentinel */ }
+};
+
+U_BOOT_DRIVER(gpio_adp5588) = {
+	.name					  = "gpio_adp5588",
+	.id						  = UCLASS_GPIO,
+	.ops					  = &adp5588_ops,
+	.of_match				  = adp5588_of_match_list,
+	.of_to_plat		  = adp5588_ofdata_platdata,
+	.plat_auto = sizeof(struct adp5588_gpio),
+	.flags					  = DM_FLAG_PRE_RELOC,
+};
diff --git a/drivers/gpio/gpio-adi-adsp.c b/drivers/gpio/gpio-adi-adsp.c
new file mode 100644
index 00000000000..0ce00572e08
--- /dev/null
+++ b/drivers/gpio/gpio-adi-adsp.c
@@ -0,0 +1,179 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * (C) Copyright 2022 - Analog Devices, Inc.
+ *
+ * Written and/or maintained by Timesys Corporation
+ *
+ * Author: Greg Malysa <greg.malysa@timesys.com>
+ * Additional Contact: Nathan Barrett-Morrison <nathan.morrison@timesys.com>
+ */
+
+#include <dm.h>
+#include <asm-generic/gpio.h>
+#include <dm/device_compat.h>
+#include <linux/bitops.h>
+#include <linux/io.h>
+
+#define ADSP_PORT_MMIO_SIZE		0x80
+#define ADSP_PORT_PIN_SIZE		16
+
+#define ADSP_PORT_REG_FER			0x00
+#define ADSP_PORT_REG_FER_SET		0x04
+#define ADSP_PORT_REG_FER_CLEAR		0x08
+#define ADSP_PORT_REG_DATA			0x0c
+#define ADSP_PORT_REG_DATA_SET		0x10
+#define ADSP_PORT_REG_DATA_CLEAR	0x14
+#define ADSP_PORT_REG_DIR			0x18
+#define ADSP_PORT_REG_DIR_SET		0x1c
+#define ADSP_PORT_REG_DIR_CLEAR		0x20
+#define ADSP_PORT_REG_INEN			0x24
+#define ADSP_PORT_REG_INEN_SET		0x28
+#define ADSP_PORT_REG_INEN_CLEAR	0x2c
+#define ADSP_PORT_REG_PORT_MUX		0x30
+#define ADSP_PORT_REG_DATA_TGL		0x34
+#define ADSP_PORT_REG_POLAR			0x38
+#define ADSP_PORT_REG_POLAR_SET		0x3c
+#define ADSP_PORT_REG_POLAR_CLEAR	0x40
+#define ADSP_PORT_REG_LOCK			0x44
+#define ADSP_PORT_REG_TRIG_TGL		0x48
+
+struct adsp_gpio_priv {
+	void __iomem *base;
+	int ngpio;
+};
+
+static u32 get_port(unsigned int pin)
+{
+	return pin / ADSP_PORT_PIN_SIZE;
+}
+
+static u32 get_offset(unsigned int pin)
+{
+	return pin % ADSP_PORT_PIN_SIZE;
+}
+
+static int adsp_gpio_input(struct udevice *udev, unsigned int pin)
+{
+	struct adsp_gpio_priv *priv = dev_get_priv(udev);
+	u32 port, offset;
+	void __iomem *portbase;
+
+	if (pin < priv->ngpio) {
+		port = get_port(pin);
+		offset = get_offset(pin);
+		portbase = priv->base + port * ADSP_PORT_MMIO_SIZE;
+
+		iowrite16(BIT(offset), portbase + ADSP_PORT_REG_FER_CLEAR);
+		iowrite16(BIT(offset), portbase + ADSP_PORT_REG_DIR_CLEAR);
+		iowrite16(BIT(offset), portbase + ADSP_PORT_REG_INEN_SET);
+		return 0;
+	}
+
+	return -EINVAL;
+}
+
+static int adsp_gpio_output(struct udevice *udev, unsigned int pin, int value)
+{
+	struct adsp_gpio_priv *priv = dev_get_priv(udev);
+	u32 port, offset;
+	void __iomem *portbase;
+
+	if (pin < priv->ngpio) {
+		port = get_port(pin);
+		offset = get_offset(pin);
+		portbase = priv->base + port * ADSP_PORT_MMIO_SIZE;
+
+		iowrite16(BIT(offset), portbase + ADSP_PORT_REG_FER_CLEAR);
+
+		if (value)
+			iowrite16(BIT(offset), portbase + ADSP_PORT_REG_DATA_SET);
+		else
+			iowrite16(BIT(offset), portbase + ADSP_PORT_REG_DATA_CLEAR);
+
+		iowrite16(BIT(offset), portbase + ADSP_PORT_REG_DIR_SET);
+		iowrite16(BIT(offset), portbase + ADSP_PORT_REG_INEN_CLEAR);
+		return 0;
+	}
+
+	return -EINVAL;
+}
+
+static int adsp_gpio_get_value(struct udevice *udev, unsigned int pin)
+{
+	struct adsp_gpio_priv *priv = dev_get_priv(udev);
+	u32 port, offset;
+	u16 val;
+	void __iomem *portbase;
+
+	if (pin < priv->ngpio) {
+		port = get_port(pin);
+		offset = get_offset(pin);
+		portbase = priv->base + port * ADSP_PORT_MMIO_SIZE;
+
+		val = ioread16(portbase + ADSP_PORT_REG_DATA);
+		return !!(val & BIT(offset));
+	}
+
+	return 0;
+}
+
+static int adsp_gpio_set_value(struct udevice *udev, unsigned int pin, int value)
+{
+	struct adsp_gpio_priv *priv = dev_get_priv(udev);
+	u32 port, offset;
+	void __iomem *portbase;
+
+	if (pin < priv->ngpio) {
+		port = get_port(pin);
+		offset = get_offset(pin);
+		portbase = priv->base + port * ADSP_PORT_MMIO_SIZE;
+
+		if (value)
+			iowrite16(BIT(offset), portbase + ADSP_PORT_REG_DATA_SET);
+		else
+			iowrite16(BIT(offset), portbase + ADSP_PORT_REG_DATA_CLEAR);
+	}
+
+	return 0;
+}
+
+static const struct dm_gpio_ops adsp_gpio_ops = {
+	.direction_input = adsp_gpio_input,
+	.direction_output = adsp_gpio_output,
+	.get_value = adsp_gpio_get_value,
+	.set_value = adsp_gpio_set_value,
+};
+
+static int adsp_gpio_probe(struct udevice *udev)
+{
+	struct adsp_gpio_priv *priv = dev_get_priv(udev);
+	struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(udev);
+
+	uc_priv->bank_name = "adsp gpio";
+	uc_priv->gpio_count = dev_read_u32_default(udev, "adi,ngpios", 0);
+
+	if (!uc_priv->gpio_count) {
+		dev_err(udev, "Missing adi,ngpios property!\n");
+		return -ENOENT;
+	}
+
+	priv->base = dev_read_addr_ptr(udev);
+	priv->ngpio = uc_priv->gpio_count;
+
+	return 0;
+}
+
+static const struct udevice_id adsp_gpio_match[] = {
+	{ .compatible = "adi,adsp-gpio" },
+	{ },
+};
+
+U_BOOT_DRIVER(adi_adsp_gpio) = {
+	.name	= "adi_adsp_gpio",
+	.id	= UCLASS_GPIO,
+	.ops	= &adsp_gpio_ops,
+	.probe	= adsp_gpio_probe,
+	.priv_auto = sizeof(struct adsp_gpio_priv),
+	.of_match = adsp_gpio_match,
+	.flags = DM_FLAG_PRE_RELOC,
+};
diff --git a/drivers/gpio/pca953x_gpio.c b/drivers/gpio/pca953x_gpio.c
index e84038f312e..523ca8473a8 100644
--- a/drivers/gpio/pca953x_gpio.c
+++ b/drivers/gpio/pca953x_gpio.c
@@ -393,6 +393,8 @@ static const struct udevice_id pca953x_ids[] = {
 	{ .compatible = "nxp,pca9575", .data = OF_957X(16, PCA_INT), },
 	{ .compatible = "nxp,pca9698", .data = OF_953X(40, 0), },
 
+	{ .compatible = "nxp,pcal6408", .data = OF_953X(8, PCA_LATCH_INT), },
+	{ .compatible = "nxp,pcal6416", .data = OF_953X(16, PCA_LATCH_INT), },
 	{ .compatible = "nxp,pcal6524", .data = OF_953X(24, PCA_LATCH_INT), },
 
 	{ .compatible = "maxim,max7310", .data = OF_953X(8, 0), },
diff --git a/drivers/i2c/Kconfig b/drivers/i2c/Kconfig
index cdae6825736..46e76385961 100644
--- a/drivers/i2c/Kconfig
+++ b/drivers/i2c/Kconfig
@@ -154,6 +154,13 @@ config SPL_DM_I2C_GPIO
 	  bindings are supported.
 	  Binding info: doc/device-tree-bindings/i2c/i2c-gpio.txt
 
+config SYS_I2C_ADI
+	bool "ADI I2C driver"
+	depends on DM_I2C && ARCH_SC5XX
+	help
+	  Add support for the ADI (Analog Devices) I2C driver as used
+	  in SC57X, SC58X, SC59X, SC59X_64.
+
 config SYS_I2C_AT91
 	bool "Atmel I2C driver"
 	depends on DM_I2C && ARCH_AT91
diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile
index bebd728e7da..2713289f7db 100644
--- a/drivers/i2c/Makefile
+++ b/drivers/i2c/Makefile
@@ -11,6 +11,7 @@ obj-$(CONFIG_$(XPL_)I2C_CROS_EC_TUNNEL) += cros_ec_tunnel.o
 obj-$(CONFIG_$(XPL_)I2C_CROS_EC_LDO) += cros_ec_ldo.o
 
 obj-$(CONFIG_$(XPL_)SYS_I2C_LEGACY) += i2c_core.o
+obj-$(CONFIG_SYS_I2C_ADI) += adi_i2c.o
 obj-$(CONFIG_SYS_I2C_ASPEED) += ast_i2c.o
 obj-$(CONFIG_SYS_I2C_AST2600) += ast2600_i2c.o
 obj-$(CONFIG_SYS_I2C_AT91) += at91_i2c.o
diff --git a/drivers/i2c/adi_i2c.c b/drivers/i2c/adi_i2c.c
new file mode 100644
index 00000000000..4cddcfa6b7f
--- /dev/null
+++ b/drivers/i2c/adi_i2c.c
@@ -0,0 +1,386 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * (C) Copyright 2022 - Analog Devices, Inc.
+ *
+ * Written and/or maintained by Timesys Corporation
+ *
+ * Converted to driver model by Nathan Barrett-Morrison
+ *
+ * Contact: Nathan Barrett-Morrison <nathan.morrison@timesys.com>
+ * Contact: Greg Malysa <greg.malysa@timesys.com>
+ */
+
+#include <clk.h>
+#include <dm.h>
+#include <i2c.h>
+#include <mapmem.h>
+#include <linux/io.h>
+
+#define CLKLOW(x) ((x) & 0xFF)     // Periods Clock Is Held Low
+#define CLKHI(y) (((y) & 0xFF) << 0x8) // Periods Clock Is High
+
+#define PRESCALE        0x007F     // SCLKs Per Internal Time Reference (10MHz)
+#define TWI_ENA         0x0080     // TWI Enable
+#define SCCB            0x0200     // SCCB Compatibility Enable
+
+#define SEN             0x0001     // Slave Enable
+#define SADD_LEN        0x0002     // Slave Address Length
+#define STDVAL          0x0004     // Slave Transmit Data Valid
+#define TSC_NAK         0x0008     // NAK Generated At Conclusion Of Transfer
+#define GEN             0x0010     // General Call Adrress Matching Enabled
+
+#define SDIR            0x0001     // Slave Transfer Direction
+#define GCALL           0x0002     // General Call Indicator
+
+#define MEN             0x0001     // Master Mode Enable
+#define MADD_LEN        0x0002     // Master Address Length
+#define MDIR            0x0004     // Master Transmit Direction (RX/TX*)
+#define FAST            0x0008     // Use Fast Mode Timing Specs
+#define STOP            0x0010     // Issue Stop Condition
+#define RSTART          0x0020     // Repeat Start or Stop* At End Of Transfer
+#define DCNT            0x3FC0     // Data Bytes To Transfer
+#define SDAOVR          0x4000     // Serial Data Override
+#define SCLOVR          0x8000     // Serial Clock Override
+
+#define MPROG           0x0001     // Master Transfer In Progress
+#define LOSTARB         0x0002     // Lost Arbitration Indicator (Xfer Aborted)
+#define ANAK            0x0004     // Address Not Acknowledged
+#define DNAK            0x0008     // Data Not Acknowledged
+#define BUFRDERR        0x0010     // Buffer Read Error
+#define BUFWRERR        0x0020     // Buffer Write Error
+#define SDASEN          0x0040     // Serial Data Sense
+#define SCLSEN          0x0080     // Serial Clock Sense
+#define BUSBUSY         0x0100     // Bus Busy Indicator
+
+#define SINIT           0x0001     // Slave Transfer Initiated
+#define SCOMP           0x0002     // Slave Transfer Complete
+#define SERR            0x0004     // Slave Transfer Error
+#define SOVF            0x0008     // Slave Overflow
+#define MCOMP           0x0010     // Master Transfer Complete
+#define MERR            0x0020     // Master Transfer Error
+#define XMTSERV         0x0040     // Transmit FIFO Service
+#define RCVSERV         0x0080     // Receive FIFO Service
+
+#define XMTFLUSH        0x0001     // Transmit Buffer Flush
+#define RCVFLUSH        0x0002     // Receive Buffer Flush
+#define XMTINTLEN       0x0004     // Transmit Buffer Interrupt Length
+#define RCVINTLEN       0x0008     // Receive Buffer Interrupt Length
+
+#define XMTSTAT         0x0003     // Transmit FIFO Status
+#define XMT_EMPTY       0x0000     // Transmit FIFO Empty
+#define XMT_HALF        0x0001     // Transmit FIFO Has 1 Byte To Write
+#define XMT_FULL        0x0003     // Transmit FIFO Full (2 Bytes To Write)
+
+#define RCVSTAT         0x000C     // Receive FIFO Status
+#define RCV_EMPTY       0x0000     // Receive FIFO Empty
+#define RCV_HALF        0x0004     // Receive FIFO Has 1 Byte To Read
+#define RCV_FULL        0x000C     // Receive FIFO Full (2 Bytes To Read)
+
+/* Every register is 32bit aligned, but only 16bits in size */
+#define ureg(name) u16 name; u16 __pad_##name
+
+struct twi_regs {
+	ureg(clkdiv);
+	ureg(control);
+	ureg(slave_ctl);
+	ureg(slave_stat);
+	ureg(slave_addr);
+	ureg(master_ctl);
+	ureg(master_stat);
+	ureg(master_addr);
+	ureg(int_stat);
+	ureg(int_mask);
+	ureg(fifo_ctl);
+	ureg(fifo_stat);
+	u8 __pad[0x50];
+
+	ureg(xmt_data8);
+	ureg(xmt_data16);
+	ureg(rcv_data8);
+	ureg(rcv_data16);
+};
+
+#undef ureg
+
+/*
+ * The way speed is changed into duty often results in integer truncation
+ * with 50% duty, so we'll force rounding up to the next duty by adding 1
+ * to the max. In practice this will get us a speed of something like
+ * 385 KHz. The other limit is easy to handle as it is only 8 bits.
+ */
+#define I2C_SPEED_MAX             400000
+#define I2C_SPEED_TO_DUTY(speed)  (5000000 / (speed))
+#define I2C_DUTY_MAX              (I2C_SPEED_TO_DUTY(I2C_SPEED_MAX) + 1)
+#define I2C_DUTY_MIN              0xff	/* 8 bit limited */
+
+#define I2C_M_COMBO		0x4
+#define I2C_M_STOP		0x2
+#define I2C_M_READ		0x1
+
+/*
+ * All transfers are described by this data structure
+ */
+struct adi_i2c_msg {
+	u8 flags;
+	u32 len;		/* msg length */
+	u8 *buf;		/* pointer to msg data */
+	u32 olen;		/* addr length */
+	u8 *obuf;		/* addr buffer */
+};
+
+struct adi_i2c_dev {
+	struct twi_regs  __iomem *base;
+	u32 i2c_clk;
+	uint speed;
+};
+
+/* Allow msec timeout per ~byte transfer */
+#define I2C_TIMEOUT 10
+
+/**
+ * wait_for_completion - manage the actual i2c transfer
+ *	@msg: the i2c msg
+ */
+static int wait_for_completion(struct twi_regs *twi, struct adi_i2c_msg *msg)
+{
+	u16 int_stat;
+	ulong timebase = get_timer(0);
+
+	do {
+		int_stat = ioread16(&twi->int_stat);
+
+		if (int_stat & XMTSERV) {
+			iowrite16(XMTSERV, &twi->int_stat);
+			if (msg->olen) {
+				iowrite16(*(msg->obuf++), &twi->xmt_data8);
+				--msg->olen;
+			} else if (!(msg->flags & I2C_M_COMBO) && msg->len) {
+				iowrite16(*(msg->buf++), &twi->xmt_data8);
+				--msg->len;
+			} else {
+				if (msg->flags & I2C_M_COMBO)
+					setbits_16(&twi->master_ctl, RSTART | MDIR);
+				else
+					setbits_16(&twi->master_ctl, STOP);
+			}
+		}
+		if (int_stat & RCVSERV) {
+			iowrite16(RCVSERV, &twi->int_stat);
+			if (msg->len) {
+				*(msg->buf++) = ioread16(&twi->rcv_data8);
+				--msg->len;
+			} else if (msg->flags & I2C_M_STOP) {
+				setbits_16(&twi->master_ctl, STOP);
+			}
+		}
+		if (int_stat & MERR) {
+			pr_err("%s: master transmit terror: %d\n", __func__,
+			       ioread16(&twi->master_stat));
+			iowrite16(MERR, &twi->int_stat);
+			return -EIO;
+		}
+		if (int_stat & MCOMP) {
+			iowrite16(MCOMP, &twi->int_stat);
+			if (msg->flags & I2C_M_COMBO && msg->len) {
+				u16 mlen = min(msg->len, 0xffu) << 6;
+				clrsetbits_16(&twi->master_ctl, RSTART, mlen | MEN | MDIR);
+			} else {
+				break;
+			}
+		}
+
+		/* If we were able to do something, reset timeout */
+		if (int_stat)
+			timebase = get_timer(0);
+
+	} while (get_timer(timebase) < I2C_TIMEOUT);
+
+	return 0;
+}
+
+static int i2c_transfer(struct twi_regs *twi, u8 chip, u8 *offset,
+			int olen, u8 *buffer, int len, u8 flags)
+{
+	int ret;
+	u16 ctl;
+
+	struct adi_i2c_msg msg = {
+		.flags = flags | (len >= 0xff ? I2C_M_STOP : 0),
+		.buf   = buffer,
+		.len   = len,
+		.obuf  = offset,
+		.olen  = olen,
+	};
+
+	/* wait for things to settle */
+	while (ioread16(&twi->master_stat) & BUSBUSY)
+		if (!IS_ENABLED(CONFIG_SPL_BUILD) && ctrlc())
+			return -EINTR;
+
+	/* Set Transmit device address */
+	iowrite16(chip, &twi->master_addr);
+
+	/* Clear the FIFO before starting things */
+	iowrite16(XMTFLUSH | RCVFLUSH, &twi->fifo_ctl);
+	iowrite16(0, &twi->fifo_ctl);
+
+	/* Prime the pump */
+	if (msg.olen) {
+		len = (msg.flags & I2C_M_COMBO) ? msg.olen : msg.olen + len;
+		iowrite16(*(msg.obuf++), &twi->xmt_data8);
+		--msg.olen;
+	} else if (!(msg.flags & I2C_M_READ) && msg.len) {
+		iowrite16(*(msg.buf++), &twi->xmt_data8);
+		--msg.len;
+	}
+
+	/* clear int stat */
+	iowrite16(-1, &twi->master_stat);
+	iowrite16(-1, &twi->int_stat);
+	iowrite16(0, &twi->int_mask);
+
+	/* Master enable */
+	ctl = ioread16(&twi->master_ctl);
+	ctl = (ctl & FAST) | (min(len, 0xff) << 6) | MEN |
+		((msg.flags & I2C_M_READ) ? MDIR : 0);
+	iowrite16(ctl, &twi->master_ctl);
+
+	/* Process the rest */
+	ret = wait_for_completion(twi, &msg);
+
+	clrbits_16(&twi->master_ctl, MEN);
+	clrbits_16(&twi->control, TWI_ENA);
+	setbits_16(&twi->control, TWI_ENA);
+	return ret;
+}
+
+static int adi_i2c_read(struct twi_regs *twi, u8 chip,
+			u8 *offset, int olen, u8 *buffer, int len)
+{
+	return i2c_transfer(twi, chip, offset, olen, buffer,
+			len, olen ? I2C_M_COMBO : I2C_M_READ);
+}
+
+static int adi_i2c_write(struct twi_regs *twi, u8 chip,
+			 u8 *offset, int olen, u8 *buffer, int len)
+{
+	return i2c_transfer(twi, chip, offset, olen, buffer, len, 0);
+}
+
+static int adi_i2c_set_bus_speed(struct udevice *bus, uint speed)
+{
+	struct adi_i2c_dev *dev = dev_get_priv(bus);
+	struct twi_regs *twi = dev->base;
+	u16 clkdiv = I2C_SPEED_TO_DUTY(speed);
+
+	/* Set TWI interface clock */
+	if (clkdiv < I2C_DUTY_MAX || clkdiv > I2C_DUTY_MIN)
+		return -1;
+	clkdiv = (clkdiv << 8) | (clkdiv & 0xff);
+	iowrite16(clkdiv, &twi->clkdiv);
+
+	/* Don't turn it on */
+	iowrite16(speed > 100000 ? FAST : 0, &twi->master_ctl);
+
+	return 0;
+}
+
+static int adi_i2c_of_to_plat(struct udevice *bus)
+{
+	struct adi_i2c_dev *dev = dev_get_priv(bus);
+	struct clk clock;
+	u32 ret;
+
+	dev->base = map_sysmem(dev_read_addr(bus), sizeof(struct twi_regs));
+
+	if (!dev->base)
+		return -ENOMEM;
+
+	dev->speed = dev_read_u32_default(bus, "clock-frequency",
+					  I2C_SPEED_FAST_RATE);
+
+	ret = clk_get_by_name(bus, "i2c", &clock);
+	if (ret < 0)
+		printf("%s: Can't get I2C clk: %d\n", __func__, ret);
+	else
+		dev->i2c_clk = clk_get_rate(&clock);
+
+	return 0;
+}
+
+static int adi_i2c_probe_chip(struct udevice *bus, u32 chip_addr,
+			      u32 chip_flags)
+{
+	struct adi_i2c_dev *dev = dev_get_priv(bus);
+	u8 byte;
+
+	return adi_i2c_read(dev->base, chip_addr, NULL, 0, &byte, 1);
+}
+
+static int adi_i2c_xfer(struct udevice *bus, struct i2c_msg *msg, int nmsgs)
+{
+	struct adi_i2c_dev *dev = dev_get_priv(bus);
+	struct i2c_msg *dmsg, *omsg, dummy;
+
+	memset(&dummy, 0, sizeof(struct i2c_msg));
+
+	/*
+	 * We expect either two messages (one with an offset and one with the
+	 * actual data) or one message (just data)
+	 */
+	if (nmsgs > 2 || nmsgs == 0) {
+		debug("%s: Only one or two messages are supported.", __func__);
+		return -EINVAL;
+	}
+
+	omsg = nmsgs == 1 ? &dummy : msg;
+	dmsg = nmsgs == 1 ? msg : msg + 1;
+
+	if (dmsg->flags & I2C_M_RD)
+		return adi_i2c_read(dev->base, dmsg->addr, omsg->buf, omsg->len,
+				  dmsg->buf, dmsg->len);
+	else
+		return adi_i2c_write(dev->base, dmsg->addr, omsg->buf, omsg->len,
+				   dmsg->buf, dmsg->len);
+}
+
+int adi_i2c_probe(struct udevice *bus)
+{
+	struct adi_i2c_dev *dev = dev_get_priv(bus);
+	struct twi_regs *twi = dev->base;
+
+	u16 prescale = ((dev->i2c_clk / 1000 / 1000 + 5) / 10) & 0x7F;
+
+	/* Set TWI internal clock as 10MHz */
+	iowrite16(prescale, &twi->control);
+
+	/* Set TWI interface clock as specified */
+	adi_i2c_set_bus_speed(bus, dev->speed);
+
+	/* Enable it */
+	iowrite16(TWI_ENA | prescale, &twi->control);
+
+	return 0;
+}
+
+static const struct dm_i2c_ops adi_i2c_ops = {
+	.xfer           = adi_i2c_xfer,
+	.probe_chip     = adi_i2c_probe_chip,
+	.set_bus_speed  = adi_i2c_set_bus_speed,
+};
+
+static const struct udevice_id adi_i2c_ids[] = {
+	{ .compatible = "adi-i2c", },
+	{ /* sentinel */ }
+};
+
+U_BOOT_DRIVER(i2c_adi) = {
+	.name = "i2c_adi",
+	.id = UCLASS_I2C,
+	.of_match = adi_i2c_ids,
+	.probe = adi_i2c_probe,
+	.of_to_plat = adi_i2c_of_to_plat,
+	.priv_auto = sizeof(struct adi_i2c_dev),
+	.ops = &adi_i2c_ops,
+	.flags = DM_FLAG_PRE_RELOC,
+};
diff --git a/drivers/mailbox/Kconfig b/drivers/mailbox/Kconfig
index 67d5ac1a742..4d9f004ebad 100644
--- a/drivers/mailbox/Kconfig
+++ b/drivers/mailbox/Kconfig
@@ -21,6 +21,13 @@ config APPLE_MBOX
 	  such as the System Management Controller (SMC) and NVMe and this
 	  driver is required to get that functionality up and running.
 
+config IMX_MU_MBOX
+	bool "Enable i.MX MU MBOX support"
+	depends on DM_MAILBOX
+	help
+	  Enable support for i.MX Messaging Unit for communication with other
+	  processors on the SoC using mailbox interface
+
 config SANDBOX_MBOX
 	bool "Enable the sandbox mailbox test driver"
 	depends on DM_MAILBOX && SANDBOX
diff --git a/drivers/mailbox/Makefile b/drivers/mailbox/Makefile
index 6072fa1956b..574add60005 100644
--- a/drivers/mailbox/Makefile
+++ b/drivers/mailbox/Makefile
@@ -5,6 +5,7 @@
 
 obj-$(CONFIG_$(XPL_)DM_MAILBOX) += mailbox-uclass.o
 obj-$(CONFIG_APPLE_MBOX) += apple-mbox.o
+obj-$(CONFIG_IMX_MU_MBOX) += imx-mailbox.o
 obj-$(CONFIG_SANDBOX_MBOX) += sandbox-mbox.o
 obj-$(CONFIG_SANDBOX_MBOX) += sandbox-mbox-test.o
 obj-$(CONFIG_STM32_IPCC) += stm32-ipcc.o
diff --git a/drivers/mailbox/imx-mailbox.c b/drivers/mailbox/imx-mailbox.c
new file mode 100644
index 00000000000..b1e0465e7a8
--- /dev/null
+++ b/drivers/mailbox/imx-mailbox.c
@@ -0,0 +1,443 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2025 NXP
+ */
+
+#include <asm/io.h>
+#include <dm.h>
+#include <dm/device_compat.h>
+#include <mailbox-uclass.h>
+#include <linux/bitfield.h>
+#include <linux/bug.h>
+#include <linux/iopoll.h>
+#include <linux/compat.h>
+
+/* This driver only exposes the status bits to keep with the
+ * polling methodology of u-boot.
+ */
+DECLARE_GLOBAL_DATA_PTR;
+
+#define IMX_MU_CHANS		24
+
+#define IMX_MU_V2_PAR_OFF	0x4
+#define IMX_MU_V2_TR_MASK	GENMASK(7, 0)
+#define IMX_MU_V2_RR_MASK	GENMASK(15, 8)
+
+enum imx_mu_chan_type {
+	IMX_MU_TYPE_TX          = 0, /* Tx */
+	IMX_MU_TYPE_RX          = 1, /* Rx */
+	IMX_MU_TYPE_TXDB        = 2, /* Tx doorbell */
+	IMX_MU_TYPE_RXDB        = 3, /* Rx doorbell */
+	IMX_MU_TYPE_RST         = 4, /* Reset */
+	IMX_MU_TYPE_TXDB_V2     = 5, /* Tx doorbell with S/W ACK */
+};
+
+enum imx_mu_xcr {
+	IMX_MU_CR,
+	IMX_MU_GIER,
+	IMX_MU_GCR,
+	IMX_MU_TCR,
+	IMX_MU_RCR,
+	IMX_MU_xCR_MAX,
+};
+
+enum imx_mu_xsr {
+	IMX_MU_SR,
+	IMX_MU_GSR,
+	IMX_MU_TSR,
+	IMX_MU_RSR,
+	IMX_MU_xSR_MAX,
+};
+
+struct imx_mu_con_priv {
+	unsigned int		idx;
+	enum imx_mu_chan_type	type;
+	struct mbox_chan	*chan;
+};
+
+enum imx_mu_type {
+	IMX_MU_V1,
+	IMX_MU_V2 = BIT(1),
+	IMX_MU_V2_S4 = BIT(15),
+	IMX_MU_V2_IRQ = BIT(16),
+};
+
+struct imx_mu {
+	void __iomem *base;
+	const struct imx_mu_dcfg *dcfg;
+	u32 num_tr;
+	u32 num_rr;
+	/* use pointers to channel as a way to reserve channels */
+	struct mbox_chan *channels[IMX_MU_CHANS];
+	struct imx_mu_con_priv  con_priv[IMX_MU_CHANS];
+};
+
+struct imx_mu_dcfg {
+	int (*tx)(struct imx_mu *plat, struct imx_mu_con_priv *cp, const void *data);
+	int (*rx)(struct imx_mu *plat, struct imx_mu_con_priv *cp);
+	int (*rxdb)(struct imx_mu *plat, struct imx_mu_con_priv *cp);
+	int (*init)(struct imx_mu *plat);
+	int (*of_xlate)(struct mbox_chan *chan, struct ofnode_phandle_args *args);
+	enum imx_mu_type type;
+	u32	xTR;			/* Transmit Register0 */
+	u32	xRR;			/* Receive Register0 */
+	u32	xSR[IMX_MU_xSR_MAX];	/* Status Registers */
+	u32	xCR[IMX_MU_xCR_MAX];	/* Control Registers */
+};
+
+#define IMX_MU_xSR_GIPn(type, x) (type & IMX_MU_V2 ? BIT(x) : BIT(28 + (3 - (x))))
+#define IMX_MU_xSR_RFn(type, x) (type & IMX_MU_V2 ? BIT(x) : BIT(24 + (3 - (x))))
+#define IMX_MU_xSR_TEn(type, x) (type & IMX_MU_V2 ? BIT(x) : BIT(20 + (3 - (x))))
+
+/* General Purpose Interrupt Enable */
+#define IMX_MU_xCR_GIEn(type, x) (type & IMX_MU_V2 ? BIT(x) : BIT(28 + (3 - (x))))
+/* Receive Interrupt Enable */
+#define IMX_MU_xCR_RIEn(type, x) (type & IMX_MU_V2 ? BIT(x) : BIT(24 + (3 - (x))))
+/* Transmit Interrupt Enable */
+#define IMX_MU_xCR_TIEn(type, x) (type & IMX_MU_V2 ? BIT(x) : BIT(20 + (3 - (x))))
+/* General Purpose Interrupt Request */
+#define IMX_MU_xCR_GIRn(type, x) (type & IMX_MU_V2 ? BIT(x) : BIT(16 + (3 - (x))))
+/* MU reset */
+#define IMX_MU_xCR_RST(type)	(type & IMX_MU_V2 ? BIT(0) : BIT(5))
+#define IMX_MU_xSR_RST(type)	(type & IMX_MU_V2 ? BIT(0) : BIT(7))
+
+static void imx_mu_write(struct imx_mu *plat, u32 val, u32 offs)
+{
+	iowrite32(val, plat->base + offs);
+}
+
+static u32 imx_mu_read(struct imx_mu *plat, u32 offs)
+{
+	return ioread32(plat->base + offs);
+}
+
+static u32 imx_mu_xcr_rmw(struct imx_mu *plat, enum imx_mu_xcr type, u32 set, u32 clr)
+{
+	u32 val;
+
+	val = imx_mu_read(plat, plat->dcfg->xCR[type]);
+	val &= ~clr;
+	val |= set;
+	imx_mu_write(plat, val, plat->dcfg->xCR[type]);
+
+	return val;
+}
+
+/* check that the channel is open or owned by caller */
+static int imx_mu_check_channel(struct mbox_chan *chan)
+{
+	struct imx_mu *plat = dev_get_plat(chan->dev);
+
+	if (plat->channels[chan->id]) {
+		/* if reserved check that caller owns */
+		if (plat->channels[chan->id] == chan)
+			return 1; /* caller owns the channel */
+
+		return -EACCES;
+	}
+
+	return 0; /* channel empty */
+}
+
+static int imx_mu_chan_request(struct mbox_chan *chan)
+{
+	struct imx_mu *plat = dev_get_plat(chan->dev);
+	struct imx_mu_con_priv *cp;
+	enum imx_mu_chan_type type;
+	int idx;
+
+	type = chan->id / 4;
+	idx = chan->id % 4;
+
+	if (imx_mu_check_channel(chan) < 0) /* check if channel already in use */
+		return -EPERM;
+
+	plat->channels[chan->id] = chan;
+	chan->con_priv = kcalloc(1, sizeof(struct imx_mu_con_priv), 0);
+	if (!chan->con_priv)
+		return -ENOMEM;
+	cp = chan->con_priv;
+	cp->idx = idx;
+	cp->type = type;
+	cp->chan = chan;
+
+	switch (type) {
+	case IMX_MU_TYPE_RX:
+		imx_mu_xcr_rmw(plat, IMX_MU_RCR, IMX_MU_xCR_RIEn(plat->dcfg->type, idx), 0);
+		break;
+	case IMX_MU_TYPE_TXDB_V2:
+	case IMX_MU_TYPE_TXDB:
+	case IMX_MU_TYPE_RXDB:
+		imx_mu_xcr_rmw(plat, IMX_MU_GIER, IMX_MU_xCR_GIEn(plat->dcfg->type, idx), 0);
+		break;
+	default:
+		break;
+	}
+
+	return 0;
+}
+
+static int imx_mu_chan_free(struct mbox_chan *chan)
+{
+	struct imx_mu *plat = dev_get_plat(chan->dev);
+	struct imx_mu_con_priv *cp = chan->con_priv;
+
+	if (imx_mu_check_channel(chan) <= 0) /* check that the channel is also not empty */
+		return -EINVAL;
+
+	/* if you own channel and  channel is NOT empty */
+	plat->channels[chan->id] = NULL;
+	switch (cp->type) {
+	case IMX_MU_TYPE_TX:
+		imx_mu_xcr_rmw(plat, IMX_MU_TCR, 0, IMX_MU_xCR_TIEn(plat->dcfg->type, cp->idx));
+		break;
+	case IMX_MU_TYPE_RX:
+		imx_mu_xcr_rmw(plat, IMX_MU_RCR, 0, IMX_MU_xCR_RIEn(plat->dcfg->type, cp->idx));
+		break;
+	case IMX_MU_TYPE_TXDB_V2:
+	case IMX_MU_TYPE_TXDB:
+	case IMX_MU_TYPE_RXDB:
+		imx_mu_xcr_rmw(plat, IMX_MU_GIER, 0, IMX_MU_xCR_GIEn(plat->dcfg->type, cp->idx));
+		break;
+	default:
+		break;
+	}
+
+	kfree(cp);
+
+	return 0;
+}
+
+static int imx_mu_send(struct mbox_chan *chan, const void *data)
+{
+	struct imx_mu *plat = dev_get_plat(chan->dev);
+	struct imx_mu_con_priv *cp = chan->con_priv;
+
+	if (imx_mu_check_channel(chan) < 1) /* return if channel isn't owned */
+		return -EPERM;
+
+	return plat->dcfg->tx(plat, cp, data);
+}
+
+static int imx_mu_recv(struct mbox_chan *chan, void *data)
+{
+	struct imx_mu *plat = dev_get_plat(chan->dev);
+	struct imx_mu_con_priv *cp = chan->con_priv;
+	u32 ctrl, val;
+
+	if (imx_mu_check_channel(chan) < 1) /* return if channel isn't owned */
+		return -EPERM;
+
+	switch (cp->type) {
+	case IMX_MU_TYPE_TXDB_V2:
+	case IMX_MU_TYPE_RXDB:
+		/* check if GSR[GIRn] bit is set */
+		if (readx_poll_timeout(ioread32, plat->base + plat->dcfg->xSR[IMX_MU_GSR],
+			val, val & BIT(cp->idx), 1000000) < 0)
+			return -EBUSY;
+
+		ctrl = imx_mu_read(plat, plat->dcfg->xCR[IMX_MU_GIER]);
+		val = imx_mu_read(plat, plat->dcfg->xSR[IMX_MU_GSR]);
+		val &= IMX_MU_xSR_GIPn(plat->dcfg->type, cp->idx) &
+			(ctrl & IMX_MU_xCR_GIEn(plat->dcfg->type, cp->idx));
+		break;
+	default:
+		dev_warn(chan->dev, "Unhandled channel type %d\n", cp->type);
+		return -EOPNOTSUPP;
+	};
+
+	if (val == IMX_MU_xSR_GIPn(plat->dcfg->type, cp->idx))
+		plat->dcfg->rxdb(plat, cp);
+
+	return 0;
+}
+
+static int imx_mu_of_to_plat(struct udevice *dev)
+{
+	struct imx_mu *plat = dev_get_plat(dev);
+	fdt_addr_t addr;
+
+	addr = dev_read_addr(dev);
+	if (addr == FDT_ADDR_T_NONE)
+		return -ENODEV;
+
+	plat->base = (struct mu_type *)addr;
+
+	return 0;
+}
+
+static int imx_mu_init_generic(struct imx_mu *plat)
+{
+	unsigned int i;
+	unsigned int val;
+
+	if (plat->num_rr > 4 || plat->num_tr > 4) {
+		WARN_ONCE(true, "%s not support TR/RR larger than 4\n", __func__);
+		return -EOPNOTSUPP;
+	}
+
+	/* Set default MU configuration */
+	for (i = 0; i < IMX_MU_xCR_MAX; i++)
+		imx_mu_write(plat, 0, plat->dcfg->xCR[i]);
+
+	/* Clear any pending GIP */
+	val = imx_mu_read(plat, plat->dcfg->xSR[IMX_MU_GSR]);
+	imx_mu_write(plat, val, plat->dcfg->xSR[IMX_MU_GSR]);
+
+	/* Clear any pending RSR */
+	for (i = 0; i < plat->num_rr; i++)
+		imx_mu_read(plat, plat->dcfg->xRR + i * 4);
+
+	return 0;
+}
+
+static int imx_mu_generic_of_xlate(struct mbox_chan *chan, struct ofnode_phandle_args *args)
+{
+	enum imx_mu_chan_type type;
+	int idx, cid;
+
+	if (args->args_count != 2) {
+		dev_err(chan->dev, "Invalid argument count %d\n", args->args_count);
+		return -EINVAL;
+	}
+
+	type = args->args[0]; /* channel type */
+	idx = args->args[1]; /* index */
+
+	cid = type * 4 + idx;
+	if (cid >= IMX_MU_CHANS) {
+		dev_err(chan->dev, "Not supported channel number: %d. (type: %d, idx: %d)\n",
+			cid, type, idx);
+		return -EINVAL;
+	}
+
+	chan->id = cid;
+
+	return 0;
+}
+
+static int imx_mu_generic_tx(struct imx_mu *plat, struct imx_mu_con_priv *cp,
+			     const void *data)
+{
+	switch (cp->type) {
+	case IMX_MU_TYPE_TXDB_V2:
+		imx_mu_xcr_rmw(plat, IMX_MU_GCR, IMX_MU_xCR_GIRn(plat->dcfg->type, cp->idx), 0);
+		break;
+	default:
+		dev_warn(cp->chan->dev, "Send data on wrong channel type: %d\n", cp->type);
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+static int imx_mu_generic_rxdb(struct imx_mu *plat, struct imx_mu_con_priv *cp)
+{
+	imx_mu_write(plat, IMX_MU_xSR_GIPn(plat->dcfg->type, cp->idx),
+		     plat->dcfg->xSR[IMX_MU_GSR]);
+
+	return 0;
+}
+
+static const struct imx_mu_dcfg imx_mu_cfg_imx6sx = {
+	.tx	= imx_mu_generic_tx,
+	.rxdb	= imx_mu_generic_rxdb,
+	.init	= imx_mu_init_generic,
+	.of_xlate = imx_mu_generic_of_xlate,
+	.type	= IMX_MU_V1,
+	.xTR	= 0x0,
+	.xRR	= 0x10,
+	.xSR	= {0x20, 0x20, 0x20, 0x20},
+	.xCR	= {0x24, 0x24, 0x24, 0x24, 0x24},
+};
+
+static const struct imx_mu_dcfg imx_mu_cfg_imx7ulp = {
+	.tx	= imx_mu_generic_tx,
+	.rxdb	= imx_mu_generic_rxdb,
+	.init	= imx_mu_init_generic,
+	.of_xlate = imx_mu_generic_of_xlate,
+	.type	= IMX_MU_V1,
+	.xTR	= 0x20,
+	.xRR	= 0x40,
+	.xSR	= {0x60, 0x60, 0x60, 0x60},
+	.xCR	= {0x64, 0x64, 0x64, 0x64, 0x64},
+};
+
+static const struct imx_mu_dcfg imx_mu_cfg_imx95 = {
+	.tx	= imx_mu_generic_tx,
+	.rxdb	= imx_mu_generic_rxdb,
+	.init	= imx_mu_init_generic,
+	.of_xlate = imx_mu_generic_of_xlate,
+	.type	= IMX_MU_V2,
+	.xTR	= 0x200,
+	.xRR	= 0x280,
+	.xSR	= {0xC, 0x118, 0x124, 0x12C},
+	.xCR	= {0x8, 0x110, 0x114, 0x120, 0x128},
+};
+
+static const struct udevice_id ids[] = {
+	{ .compatible = "fsl,imx6sx-mu", .data = (ulong)&imx_mu_cfg_imx6sx },
+	{ .compatible = "fsl,imx7ulp-mu", .data = (ulong)&imx_mu_cfg_imx7ulp },
+	{ .compatible = "fsl,imx95-mu", .data = (ulong)&imx_mu_cfg_imx95 },
+	{ }
+};
+
+int imx_mu_of_xlate(struct mbox_chan *chan, struct ofnode_phandle_args *args)
+{
+	struct imx_mu *plat = dev_get_plat(chan->dev);
+
+	return plat->dcfg->of_xlate(chan, args);
+}
+
+struct mbox_ops imx_mu_ops = {
+	.of_xlate = imx_mu_of_xlate,
+	.request  = imx_mu_chan_request,
+	.rfree    = imx_mu_chan_free,
+	.send     = imx_mu_send,
+	.recv     = imx_mu_recv,
+};
+
+static void imx_mu_get_tr_rr(struct imx_mu *plat)
+{
+	u32 val;
+
+	if (plat->dcfg->type & IMX_MU_V2) {
+		val = imx_mu_read(plat, IMX_MU_V2_PAR_OFF);
+		plat->num_tr = FIELD_GET(IMX_MU_V2_TR_MASK, val);
+		plat->num_rr = FIELD_GET(IMX_MU_V2_RR_MASK, val);
+	} else {
+		plat->num_tr = 4;
+		plat->num_rr = 4;
+	}
+}
+
+static int imx_mu_probe(struct udevice *dev)
+{
+	struct imx_mu *plat = dev_get_plat(dev);
+	int ret;
+
+	debug("%s(dev=%p)\n", __func__, dev);
+
+	plat->dcfg = (void *)dev_get_driver_data(dev);
+
+	imx_mu_get_tr_rr(plat);
+
+	ret = plat->dcfg->init(plat);
+	if (ret) {
+		dev_err(dev, "Failed to init MU\n");
+		return ret;
+	}
+
+	return 0;
+}
+
+U_BOOT_DRIVER(imx_mu) = {
+	.name = "imx-mu",
+	.id = UCLASS_MAILBOX,
+	.of_match = ids,
+	.of_to_plat = imx_mu_of_to_plat,
+	.plat_auto = sizeof(struct imx_mu),
+	.probe = imx_mu_probe,
+	.ops = &imx_mu_ops,
+	.flags = DM_FLAG_PRE_RELOC,
+};
diff --git a/drivers/mailbox/zynqmp-ipi.c b/drivers/mailbox/zynqmp-ipi.c
index 713d93a200c..851aa737c03 100644
--- a/drivers/mailbox/zynqmp-ipi.c
+++ b/drivers/mailbox/zynqmp-ipi.c
@@ -270,5 +270,4 @@ U_BOOT_DRIVER(zynqmp_ipi) = {
 	.id = UCLASS_NOP,
 	.of_match = zynqmp_ipi_ids,
 	.probe = zynqmp_ipi_probe,
-	.flags = DM_FLAG_PROBE_AFTER_BIND,
 };
diff --git a/drivers/memory/ti-gpmc.c b/drivers/memory/ti-gpmc.c
index e979c431e33..29e02f12ae0 100644
--- a/drivers/memory/ti-gpmc.c
+++ b/drivers/memory/ti-gpmc.c
@@ -1242,4 +1242,5 @@ U_BOOT_DRIVER(ti_gpmc) = {
 	.of_match = gpmc_dt_ids,
 	.probe  = gpmc_probe,
 	.flags  = DM_FLAG_ALLOC_PRIV_DMA,
+	.priv_auto = sizeof(struct ti_gpmc),
 };
diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
index da84b35e804..834e0285097 100644
--- a/drivers/misc/Kconfig
+++ b/drivers/misc/Kconfig
@@ -468,6 +468,13 @@ config STM32MP_FUSE
 	  for STM32MP architecture.
 	  This API is needed for CMD_FUSE.
 
+config K3_FUSE
+	bool "Enable TI K3 fuse wrapper providing the fuse API"
+	depends on MISC && CMD_FUSE && CMD_FUSE_WRITEBUFF
+	help
+	  If you say Y here, you will get support for the fuse API (OTP)
+	  for TI K3 architecture.
+
 config STM32_RCC
 	bool "Enable RCC driver for the STM32 SoC's family"
 	depends on (ARCH_STM32 || ARCH_STM32MP) && MISC
diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
index dac805e4cdd..0b81ba2604f 100644
--- a/drivers/misc/Makefile
+++ b/drivers/misc/Makefile
@@ -48,6 +48,7 @@ obj-$(CONFIG_$(XPL_)I2C_EEPROM) += i2c_eeprom.o
 obj-$(CONFIG_IHS_FPGA) += ihs_fpga.o
 obj-$(CONFIG_IMX8) += imx8/
 obj-$(CONFIG_IMX_ELE) += imx_ele/
+obj-$(CONFIG_K3_FUSE) += k3_fuse.o
 obj-$(CONFIG_LED_STATUS) += status_led.o
 obj-$(CONFIG_LED_STATUS_GPIO) += gpio_led.o
 obj-$(CONFIG_MPC83XX_SERDES) += mpc83xx_serdes.o
diff --git a/drivers/misc/k3_fuse.c b/drivers/misc/k3_fuse.c
new file mode 100644
index 00000000000..4a8ff1f2523
--- /dev/null
+++ b/drivers/misc/k3_fuse.c
@@ -0,0 +1,78 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2025 Texas Instruments Incorporated, <www.ti.com>
+ */
+
+#include <errno.h>
+#include <stdio.h>
+#include <fuse.h>
+#include <linux/arm-smccc.h>
+#include <string.h>
+
+#define K3_SIP_OTP_WRITEBUFF 0xC2000000
+#define K3_SIP_OTP_WRITE 0xC2000001
+#define K3_SIP_OTP_READ 0xC2000002
+
+int fuse_read(u32 bank, u32 word, u32 *val)
+{
+	struct arm_smccc_res res;
+
+	if (bank != 0U) {
+		printf("Invalid bank argument, ONLY bank 0 is supported\n");
+		return -EINVAL;
+	}
+
+	/* Make SiP SMC call and send the word in the parameter register */
+	arm_smccc_smc(K3_SIP_OTP_READ, word,
+		      0, 0, 0, 0, 0, 0, &res);
+
+	*val = res.a1;
+	if (res.a0 != 0)
+		printf("SMC call failed: Error code %lu\n", res.a0);
+
+	return res.a0;
+}
+
+int fuse_sense(u32 bank, u32 word, u32 *val)
+{
+	return -EPERM;
+}
+
+int fuse_prog(u32 bank, u32 word, u32 val)
+{
+	struct arm_smccc_res res;
+	u32 mask = val;
+
+	if (bank != 0U) {
+		printf("Invalid bank argument, ONLY bank 0 is supported\n");
+		return -EINVAL;
+	}
+
+	/* Make SiP SMC call and send the word, val and mask in the parameter register */
+	arm_smccc_smc(K3_SIP_OTP_WRITE, word,
+		      val, mask, 0, 0, 0, 0, &res);
+
+	if (res.a0 != 0)
+		printf("SMC call failed: Error code %lu\n", res.a0);
+
+	return res.a0;
+}
+
+int fuse_override(u32 bank, u32 word, u32 val)
+{
+	return -EPERM;
+}
+
+int fuse_writebuff(ulong addr)
+{
+	struct arm_smccc_res res;
+
+	/* Make SiP SMC call and send the addr in the parameter register */
+	arm_smccc_smc(K3_SIP_OTP_WRITEBUFF, (unsigned long)addr,
+		      0, 0, 0, 0, 0, 0, &res);
+
+	if (res.a0 != 0)
+		printf("SMC call failed: Error code %lu\n", res.a0);
+
+	return res.a0;
+}
diff --git a/drivers/misc/qfw_acpi.c b/drivers/misc/qfw_acpi.c
index 77cebae5e3f..c6c052ac6c3 100644
--- a/drivers/misc/qfw_acpi.c
+++ b/drivers/misc/qfw_acpi.c
@@ -25,17 +25,18 @@ DECLARE_GLOBAL_DATA_PTR;
  *
  * @entry : BIOS linker command entry which tells where to allocate memory
  *          (either high memory or low memory)
- * @addr  : The address that should be used for low memory allcation. If the
+ * @addr  : The address that should be used for low memory allocation. If the
  *          memory allocation request is 'ZONE_HIGH' then this parameter will
  *          be ignored.
  * @return: 0 on success, or negative value on failure
  */
-static int bios_linker_allocate(struct udevice *dev,
+static int bios_linker_allocate(struct acpi_ctx *ctx, struct udevice *dev,
 				struct bios_linker_entry *entry, ulong *addr)
 {
 	uint32_t size, align;
 	struct fw_file *file;
 	unsigned long aligned_addr;
+	struct acpi_rsdp *rsdp;
 
 	align = le32_to_cpu(entry->alloc.align);
 	/* align must be power of 2 */
@@ -58,7 +59,9 @@ static int bios_linker_allocate(struct udevice *dev,
 	 * If allocation zone is ZONE_FSEG, then we use the 'addr' passed
 	 * in which is low memory
 	 */
-	if (entry->alloc.zone == BIOS_LINKER_LOADER_ALLOC_ZONE_HIGH) {
+	if (IS_ENABLED(CONFIG_BLOBLIST_TABLES)) {
+		aligned_addr = ALIGN(*addr, align);
+	} else if (entry->alloc.zone == BIOS_LINKER_LOADER_ALLOC_ZONE_HIGH) {
 		aligned_addr = (unsigned long)memalign(align, size);
 		if (!aligned_addr) {
 			printf("error: allocating resource\n");
@@ -83,8 +86,13 @@ static int bios_linker_allocate(struct udevice *dev,
 		       (void *)aligned_addr);
 	file->addr = aligned_addr;
 
+	rsdp = (void *)aligned_addr;
+	if (!strncmp(rsdp->signature, RSDP_SIG, sizeof(rsdp->signature)))
+		ctx->rsdp = rsdp;
+
 	/* adjust address for low memory allocation */
-	if (entry->alloc.zone == BIOS_LINKER_LOADER_ALLOC_ZONE_FSEG)
+	if (IS_ENABLED(CONFIG_BLOBLIST_TABLES) ||
+	    entry->alloc.zone == BIOS_LINKER_LOADER_ALLOC_ZONE_FSEG)
 		*addr = (aligned_addr + size);
 
 	return 0;
@@ -209,19 +217,23 @@ ulong write_acpi_tables(ulong addr)
 	qfw_read_entry(dev, be16_to_cpu(file->cfg.select), size, table_loader);
 
 	for (i = 0; i < (size / sizeof(*entry)); i++) {
+		log_content("entry %d: addr %lx\n", i, addr);
 		entry = table_loader + i;
 		switch (le32_to_cpu(entry->command)) {
 		case BIOS_LINKER_LOADER_COMMAND_ALLOCATE:
-			ret = bios_linker_allocate(dev, entry, &addr);
+			log_content("   - %s\n", entry->alloc.file);
+			ret = bios_linker_allocate(ctx, dev, entry, &addr);
 			if (ret)
 				goto out;
 			break;
 		case BIOS_LINKER_LOADER_COMMAND_ADD_POINTER:
+			log_content("   - %s\n", entry->pointer.src_file);
 			ret = bios_linker_add_pointer(dev, entry);
 			if (ret)
 				goto out;
 			break;
 		case BIOS_LINKER_LOADER_COMMAND_ADD_CHECKSUM:
+			log_content("   - %s\n", entry->cksum.file);
 			ret = bios_linker_add_checksum(dev, entry);
 			if (ret)
 				goto out;
@@ -246,6 +258,16 @@ out:
 
 	free(table_loader);
 
+	if (!ctx->rsdp) {
+		printf("error: no RSDP found\n");
+		return addr;
+	}
+	struct acpi_rsdp *rsdp = ctx->rsdp;
+
+	rsdp->length = sizeof(*rsdp);
+	rsdp->xsdt_address = 0;
+	rsdp->ext_checksum = table_compute_checksum((u8 *)rsdp, sizeof(*rsdp));
+
 	gd_set_acpi_start(acpi_get_rsdp_addr());
 
 	return addr;
diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig
index 4827834b4aa..6740591a653 100644
--- a/drivers/mmc/Kconfig
+++ b/drivers/mmc/Kconfig
@@ -292,6 +292,15 @@ config MMC_DW_ROCKCHIP
 	  SD 3.0, SDIO 3.0 and MMC 4.5 and supports common eMMC chips as well
 	  as removeable SD and micro-SD cards.
 
+config MMC_SDHCI_ADI
+	bool "ADI SD/MMC controller support"
+	depends on ARCH_SC5XX
+	depends on DM_MMC && OF_CONTROL
+	depends on MMC_SDHCI && MMC_SDHCI_ADMA
+	help
+	  This enables support for the SD/MMC controller included in some Analog
+	  Devices SC5XX Socs.
+
 config MMC_DW_SOCFPGA
 	bool "SOCFPGA specific extensions for Synopsys DW Memory Card Interface"
 	depends on ARCH_SOCFPGA
@@ -919,6 +928,12 @@ config ESDHC_DETECT_QUIRK
 	bool "QIXIS-based eSDHC quirk detection"
 	depends on FSL_ESDHC && FSL_QIXIS
 
+config ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
+	bool
+	depends on FSL_ESDHC || FSL_ESDHC_IMX
+	def_bool y if ARCH_T1024 || ARCH_T1040 || ARCH_T1042 || ARCH_T2080 \
+		|| FSL_ESDHC_IMX
+
 config FSL_ESDHC_IMX
 	bool "Freescale/NXP i.MX eSDHC controller support"
 	help
diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile
index 90e76f90769..94ed28ead71 100644
--- a/drivers/mmc/Makefile
+++ b/drivers/mmc/Makefile
@@ -70,6 +70,7 @@ obj-$(CONFIG_MMC_SDHCI_MV)		+= mv_sdhci.o
 obj-$(CONFIG_MMC_SDHCI_NPCM)            += npcm_sdhci.o
 obj-$(CONFIG_MMC_SDHCI_PIC32)		+= pic32_sdhci.o
 obj-$(CONFIG_MMC_SDHCI_ROCKCHIP)	+= rockchip_sdhci.o
+obj-$(CONFIG_MMC_SDHCI_ADI)		+= adi_sdhci.o
 obj-$(CONFIG_MMC_SDHCI_S5P)		+= s5p_sdhci.o
 obj-$(CONFIG_MMC_SDHCI_SNPS)		+= snps_sdhci.o
 obj-$(CONFIG_MMC_SDHCI_STI)		+= sti_sdhci.o
diff --git a/drivers/mmc/adi_sdhci.c b/drivers/mmc/adi_sdhci.c
new file mode 100644
index 00000000000..65a22cefb71
--- /dev/null
+++ b/drivers/mmc/adi_sdhci.c
@@ -0,0 +1,148 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * (C) Copyright 2022 - Analog Devices, Inc.
+ *
+ * Written and/or maintained by Timesys Corporation
+ *
+ * Contact: Nathan Barrett-Morrison <nathan.morrison@timesys.com>
+ * Contact: Greg Malysa <greg.malysa@timesys.com>
+ *
+ * Based on Rockchip's sdhci.c file
+ */
+
+#include <clk.h>
+#include <dm.h>
+#include <malloc.h>
+#include <sdhci.h>
+#include <asm/cache.h>
+
+/* 400KHz is max freq for card ID etc. Use that as min */
+#define EMMC_MIN_FREQ	400000
+
+/* Check if an operation crossed a boundary of size ADMA_BOUNDARY_ALIGN */
+#define ADMA_BOUNDARY_ALGN SZ_128M
+#define BOUNDARY_OK(addr, len) \
+	(((addr) | (ADMA_BOUNDARY_ALGN - 1)) == (((addr) + (len) - 1) | \
+	(ADMA_BOUNDARY_ALGN - 1)))
+
+/* We split a descriptor for every crossing of the ADMA alignment boundary,
+ * so we need an additional descriptor for every expected crossing.
+ * As I understand it, the max expected transaction size is:
+ *  CONFIG_SYS_MMC_MAX_BLK_COUNT * MMC_MAX_BLOCK_LEN
+ *
+ * With the way the SDHCI-ADMA driver is implemented, if ADMA_MAX_LEN was a
+ * clean power of two, we'd only ever need +1 descriptor as the first
+ * descriptor that got split would then bring the remaining DMA
+ * destination addresses into alignment. Unfortunately, it's currently
+ * hardcoded to a non-power-of-two value.
+ *
+ * If that ever becomes parameterized, ADMA max length can be set to
+ * 0x10000, and set this to 1.
+ */
+#define ADMA_POTENTIAL_CROSSINGS \
+	DIV_ROUND_UP((CONFIG_SYS_MMC_MAX_BLK_COUNT * MMC_MAX_BLOCK_LEN), \
+		 ADMA_BOUNDARY_ALGN)
+/* +1 descriptor for each crossing.
+ */
+#define ADMA_TABLE_EXTRA_SZ (ADMA_POTENTIAL_CROSSINGS * ADMA_DESC_LEN)
+
+struct adi_sdhc_plat {
+	struct mmc_config cfg;
+	struct mmc mmc;
+};
+
+void adi_dwcmshc_adma_write_desc(struct sdhci_host *host, void **desc,
+				 dma_addr_t addr, int len, bool end)
+{
+	int tmplen, offset;
+
+	if (likely(!len || BOUNDARY_OK(addr, len))) {
+		sdhci_adma_write_desc(host, desc, addr, len, end);
+		return;
+	}
+
+	offset = addr & (ADMA_BOUNDARY_ALGN - 1);
+	tmplen = ADMA_BOUNDARY_ALGN - offset;
+	sdhci_adma_write_desc(host, desc, addr, tmplen, false);
+
+	addr += tmplen;
+	len -= tmplen;
+	sdhci_adma_write_desc(host, desc, addr, len, end);
+}
+
+struct sdhci_ops adi_dwcmshc_sdhci_ops = {
+	.adma_write_desc = adi_dwcmshc_adma_write_desc,
+};
+
+static int adi_dwcmshc_sdhci_probe(struct udevice *dev)
+{
+	struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
+	struct adi_sdhc_plat *plat = dev_get_plat(dev);
+	struct sdhci_host *host = dev_get_priv(dev);
+	int max_frequency, ret;
+	struct clk clk;
+
+	max_frequency = dev_read_u32_default(dev, "max-frequency", 0);
+	ret = clk_get_by_index(dev, 0, &clk);
+
+	host->quirks = 0;
+	host->max_clk = max_frequency;
+	/*
+	 * The sdhci-driver only supports 4bit and 8bit, as sdhci_setup_cfg
+	 * doesn't allow us to clear MMC_MODE_4BIT.  Consequently, we don't
+	 * check for other bus-width values.
+	 */
+	if (host->bus_width == 8)
+		host->host_caps |= MMC_MODE_8BIT;
+
+	host->mmc = &plat->mmc;
+	host->mmc->priv = host;
+	host->mmc->dev = dev;
+	upriv->mmc = host->mmc;
+
+	host->ops = &adi_dwcmshc_sdhci_ops;
+	host->adma_desc_table = memalign(ARCH_DMA_MINALIGN,
+					 ADMA_TABLE_SZ + ADMA_TABLE_EXTRA_SZ);
+	host->adma_addr = virt_to_phys(host->adma_desc_table);
+
+	ret = sdhci_setup_cfg(&plat->cfg, host, 0, EMMC_MIN_FREQ);
+	if (ret)
+		return ret;
+
+	return sdhci_probe(dev);
+}
+
+static int adi_dwcmshc_sdhci_of_to_plat(struct udevice *dev)
+{
+	struct sdhci_host *host = dev_get_priv(dev);
+
+	host->name = dev->name;
+	host->ioaddr = dev_read_addr_ptr(dev);
+	host->bus_width = dev_read_u32_default(dev, "bus-width", 4);
+
+	return 0;
+}
+
+static int adi_sdhci_bind(struct udevice *dev)
+{
+	struct adi_sdhc_plat *plat = dev_get_plat(dev);
+
+	return sdhci_bind(dev, &plat->mmc, &plat->cfg);
+}
+
+static const struct udevice_id adi_dwcmshc_sdhci_ids[] = {
+	{ .compatible = "adi,dwc-sdhci" },
+	{ }
+};
+
+U_BOOT_DRIVER(adi_dwcmshc_sdhci_drv) = {
+	.name		= "adi_sdhci",
+	.id		= UCLASS_MMC,
+	.of_match	= adi_dwcmshc_sdhci_ids,
+	.of_to_plat	= adi_dwcmshc_sdhci_of_to_plat,
+	.ops		= &sdhci_ops,
+	.bind		= adi_sdhci_bind,
+	.probe		= adi_dwcmshc_sdhci_probe,
+	.priv_auto	= sizeof(struct sdhci_host),
+	.plat_auto	= sizeof(struct adi_sdhc_plat),
+};
diff --git a/drivers/mmc/fsl_esdhc_imx.c b/drivers/mmc/fsl_esdhc_imx.c
index d7a45ef0ad0..926113f79d3 100644
--- a/drivers/mmc/fsl_esdhc_imx.c
+++ b/drivers/mmc/fsl_esdhc_imx.c
@@ -40,12 +40,6 @@
 #include <linux/iopoll.h>
 #include <linux/dma-mapping.h>
 
-#ifndef ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
-#ifdef CONFIG_FSL_USDHC
-#define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE	1
-#endif
-#endif
-
 DECLARE_GLOBAL_DATA_PTR;
 
 #define SDHCI_IRQ_EN_BITS		(IRQSTATEN_CC | IRQSTATEN_TC | \
@@ -376,7 +370,7 @@ static int esdhc_setup_data(struct fsl_esdhc_priv *priv, struct mmc *mmc,
 	    (timeout == 4 || timeout == 8 || timeout == 12))
 		timeout++;
 
-	if (IS_ENABLED(ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE))
+	if (IS_ENABLED(CONFIG_ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE))
 		timeout = 0xE;
 
 	esdhc_clrsetbits32(&regs->sysctl, SYSCTL_TIMEOUT_MASK, timeout << 16);
diff --git a/drivers/mmc/msm_sdhci.c b/drivers/mmc/msm_sdhci.c
index 27bb7052fca..ac77fb06bf7 100644
--- a/drivers/mmc/msm_sdhci.c
+++ b/drivers/mmc/msm_sdhci.c
@@ -10,6 +10,7 @@
 #include <clk.h>
 #include <dm.h>
 #include <malloc.h>
+#include <reset.h>
 #include <sdhci.h>
 #include <wait_bit.h>
 #include <asm/global_data.h>
@@ -153,9 +154,18 @@ static int msm_sdc_probe(struct udevice *dev)
 	const struct msm_sdhc_variant_info *var_info;
 	struct sdhci_host *host = &prv->host;
 	u32 core_version, core_minor, core_major;
+	struct reset_ctl bcr_rst;
 	u32 caps;
 	int ret;
 
+	ret = reset_get_by_index(dev, 0, &bcr_rst);
+	if (!ret) {
+		reset_assert(&bcr_rst);
+		udelay(200);
+		reset_deassert(&bcr_rst);
+		udelay(200);
+	}
+
 	host->quirks = SDHCI_QUIRK_WAIT_SEND_CMD | SDHCI_QUIRK_BROKEN_R1B;
 
 	host->max_clk = 0;
diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c
index 0b56d1405be..951e6acd34d 100644
--- a/drivers/mmc/sunxi_mmc.c
+++ b/drivers/mmc/sunxi_mmc.c
@@ -92,6 +92,13 @@ static int mmc_set_mod_clk(struct sunxi_mmc_priv *priv, unsigned int hz)
 		pll = CCM_MMC_CTRL_PLL6;
 		pll_hz = clock_get_pll6();
 #endif
+		/*
+		 * On the D1/R528/T113 mux source 1 refers to PLL_PERIPH0(1x),
+		 * like for the older SoCs. However we still have the hidden
+		 * divider of 2x, so compensate for that here.
+		 */
+		if (IS_ENABLED(CONFIG_MACH_SUN8I_R528))
+			pll_hz /= 2;
 	}
 
 	div = pll_hz / hz;
@@ -442,6 +449,26 @@ out:
 	return error;
 }
 
+static void sunxi_mmc_reset(void *regs)
+{
+	/* Reset controller */
+	writel(SUNXI_MMC_GCTRL_RESET, regs + SUNXI_MMC_GCTRL);
+	udelay(1000);
+
+	if (IS_ENABLED(CONFIG_SUN50I_GEN_H6) || IS_ENABLED(CONFIG_SUNXI_GEN_NCAT2)) {
+		/* Reset card */
+		writel(SUNXI_MMC_HWRST_ASSERT, regs + SUNXI_MMC_HWRST);
+		udelay(10);
+		writel(SUNXI_MMC_HWRST_DEASSERT, regs + SUNXI_MMC_HWRST);
+		udelay(300);
+
+		/* Setup FIFO R/W threshold. Needed on H616. */
+		writel(SUNXI_MMC_THLDC_READ_THLD(512) |
+		       SUNXI_MMC_THLDC_WRITE_EN |
+		       SUNXI_MMC_THLDC_READ_EN, regs + SUNXI_MMC_THLDC);
+	}
+}
+
 /* non-DM code here is used by the (ARM) SPL only */
 
 #if !CONFIG_IS_ENABLED(DM_MMC)
@@ -489,9 +516,7 @@ static int sunxi_mmc_core_init(struct mmc *mmc)
 {
 	struct sunxi_mmc_priv *priv = mmc->priv;
 
-	/* Reset controller */
-	writel(SUNXI_MMC_GCTRL_RESET, &priv->reg->gctrl);
-	udelay(1000);
+	sunxi_mmc_reset(priv->reg);
 
 	return 0;
 }
@@ -684,9 +709,7 @@ static int sunxi_mmc_probe(struct udevice *dev)
 
 	upriv->mmc = &plat->mmc;
 
-	/* Reset controller */
-	writel(SUNXI_MMC_GCTRL_RESET, &priv->reg->gctrl);
-	udelay(1000);
+	sunxi_mmc_reset(priv->reg);
 
 	return 0;
 }
diff --git a/drivers/mmc/sunxi_mmc.h b/drivers/mmc/sunxi_mmc.h
index f4ae5a790c8..71865160319 100644
--- a/drivers/mmc/sunxi_mmc.h
+++ b/drivers/mmc/sunxi_mmc.h
@@ -37,7 +37,9 @@ struct sunxi_mmc {
 	u32 res0;		/* 0x54 reserved */
 	u32 a12a;		/* 0x58 Auto command 12 argument */
 	u32 ntsr;		/* 0x5c	New timing set register */
-	u32 res1[8];
+	u32 res1[6];
+	u32 hwrst;		/* 0x78 Hardware Reset */
+	u32 res5;
 	u32 dmac;		/* 0x80 internal DMA control */
 	u32 dlba;		/* 0x84 internal DMA descr list base address */
 	u32 idst;		/* 0x88 internal DMA status */
@@ -46,7 +48,8 @@ struct sunxi_mmc {
 	u32 cbda;		/* 0x94 */
 	u32 res2[26];
 #if defined(CONFIG_SUNXI_GEN_SUN6I) || defined(CONFIG_SUN50I_GEN_H6) || defined(CONFIG_SUNXI_GEN_NCAT2)
-	u32 res3[17];
+	u32 thldc;		/* 0x100 Threshold control */
+	u32 res3[16];
 	u32 samp_dl;
 	u32 res4[46];
 #endif
@@ -57,6 +60,7 @@ struct sunxi_mmc {
 #define SUNXI_MMC_CLK_ENABLE		(0x1 << 16)
 #define SUNXI_MMC_CLK_DIVIDER_MASK	(0xff)
 
+#define SUNXI_MMC_GCTRL		0x000
 #define SUNXI_MMC_GCTRL_SOFT_RESET	(0x1 << 0)
 #define SUNXI_MMC_GCTRL_FIFO_RESET	(0x1 << 1)
 #define SUNXI_MMC_GCTRL_DMA_RESET	(0x1 << 2)
@@ -123,6 +127,10 @@ struct sunxi_mmc {
 
 #define SUNXI_MMC_NTSR_MODE_SEL_NEW		(0x1 << 31)
 
+#define SUNXI_MMC_HWRST		0x078
+#define SUNXI_MMC_HWRST_ASSERT		(0x0 << 0)
+#define SUNXI_MMC_HWRST_DEASSERT	(0x1 << 0)
+
 #define SUNXI_MMC_IDMAC_RESET		(0x1 << 0)
 #define SUNXI_MMC_IDMAC_FIXBURST	(0x1 << 1)
 #define SUNXI_MMC_IDMAC_ENABLE		(0x1 << 7)
@@ -133,6 +141,12 @@ struct sunxi_mmc {
 #define SUNXI_MMC_COMMON_CLK_GATE		(1 << 16)
 #define SUNXI_MMC_COMMON_RESET			(1 << 18)
 
+#define SUNXI_MMC_THLDC		0x100
+#define SUNXI_MMC_THLDC_READ_EN		(0x1 << 0)
+#define SUNXI_MMC_THLDC_BSY_CLR_INT_EN	(0x1 << 1)
+#define SUNXI_MMC_THLDC_WRITE_EN	(0x1 << 2)
+#define SUNXI_MMC_THLDC_READ_THLD(x)	(((x) & 0xfff) << 16)
+
 #define SUNXI_MMC_CAL_DL_SW_EN		(0x1 << 7)
 
 #endif /* _SUNXI_MMC_H */
diff --git a/drivers/mtd/mtdpart.c b/drivers/mtd/mtdpart.c
index 88094b81e7a..3f8edeb5093 100644
--- a/drivers/mtd/mtdpart.c
+++ b/drivers/mtd/mtdpart.c
@@ -208,7 +208,7 @@ int mtd_parse_partitions(struct mtd_info *parent, const char **_mtdparts,
 {
 	struct mtd_partition partition = {}, *parts;
 	const char *mtdparts = *_mtdparts;
-	uint64_t cur_off = 0, cur_sz = 0;
+	uint64_t cur_off = 0;
 	int nparts = 0;
 	int ret, idx;
 	u64 sz;
@@ -237,8 +237,7 @@ int mtd_parse_partitions(struct mtd_info *parent, const char **_mtdparts,
 			return ret;
 
 		if (parts[idx].size == MTD_SIZE_REMAINING)
-			parts[idx].size = parent->size - cur_sz;
-		cur_sz += parts[idx].size;
+			parts[idx].size = parent->size - parts[idx].offset;
 
 		sz = parts[idx].size;
 		if (sz < parent->writesize || do_div(sz, parent->writesize)) {
diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig
index 609bdffbf77..adb271dfb8f 100644
--- a/drivers/mtd/nand/raw/Kconfig
+++ b/drivers/mtd/nand/raw/Kconfig
@@ -190,6 +190,21 @@ config SPL_NAND_LOAD
 	def_bool y
 	depends on NAND_DAVINCI && ARCH_DAVINCI && SPL_NAND_SUPPORT
 
+config NAND_CADENCE
+	bool "Support Cadence NAND controller as a DT device"
+	depends on OF_CONTROL && DM_MTD
+	select SYS_NAND_SELF_INIT
+	select SPL_SYS_NAND_SELF_INIT
+	select SPL_NAND_BASE
+	select SPL_NAND_DRIVERS
+	select SPL_NAND_IDENT
+	select SPL_NAND_INIT
+	select SPL_NAND_ECC
+	imply CMD_NAND
+	help
+	  Enable the driver for NAND flash on platforms using a Cadence NAND
+	  controller as a DT device.
+
 config NAND_DENALI
 	bool
 	select SYS_NAND_SELF_INIT
@@ -673,7 +688,7 @@ config SYS_NAND_PAGE_SIZE
 		SPL_NAND_SIMPLE || (NAND_MXC && SPL_NAND_SUPPORT) || \
 		MVEBU_SPL_BOOT_DEVICE_NAND || \
 		(NAND_ATMEL && SPL_NAND_SUPPORT) || \
-		SPL_GENERATE_ATMEL_PMECC_HEADER || NAND_SANDBOX
+		SPL_GENERATE_ATMEL_PMECC_HEADER || NAND_SANDBOX || NAND_CADENCE
 	depends on !NAND_MXS && !NAND_DENALI_DT && !NAND_LPC32XX_MLC && !NAND_MT7621
 	help
 	  Number of data bytes in one page for the NAND chip on the
@@ -775,6 +790,13 @@ config SPL_NAND_AM33XX_BCH
 	  so those platforms should use CONFIG_SPL_NAND_SIMPLE for enabling
 	  SPL-NAND driver with software ECC correction support.
 
+config SPL_NAND_CADENCE
+	bool "Support Cadence NAND controller for SPL"
+	depends on SPL_NAND_SUPPORT
+	help
+	  This is a small implementation of the Cadence NAND controller
+	  for use on SPL.
+
 config SPL_NAND_DENALI
 	bool "Support Denali NAND controller for SPL"
 	depends on SPL_NAND_SUPPORT
diff --git a/drivers/mtd/nand/raw/Makefile b/drivers/mtd/nand/raw/Makefile
index b47a3d787ce..34cba77046a 100644
--- a/drivers/mtd/nand/raw/Makefile
+++ b/drivers/mtd/nand/raw/Makefile
@@ -10,6 +10,7 @@ NORMAL_DRIVERS=y
 endif
 
 obj-$(CONFIG_SPL_NAND_AM33XX_BCH) += am335x_spl_bch.o
+obj-$(CONFIG_SPL_NAND_CADENCE) += cadence_spl.o
 obj-$(CONFIG_SPL_NAND_DENALI) += denali_spl.o
 obj-$(CONFIG_SPL_NAND_SIMPLE) += nand_spl_simple.o
 obj-$(CONFIG_SPL_NAND_LOAD) += nand_spl_load.o
@@ -51,6 +52,7 @@ obj-$(CONFIG_NAND_ATMEL) += atmel_nand.o
 obj-$(CONFIG_DM_NAND_ATMEL) += atmel/
 obj-$(CONFIG_NAND_ARASAN) += arasan_nfc.o
 obj-$(CONFIG_NAND_BRCMNAND) += brcmnand/
+obj-$(CONFIG_NAND_CADENCE) += cadence_nand.o
 obj-$(CONFIG_NAND_DAVINCI) += davinci_nand.o
 obj-$(CONFIG_NAND_DENALI) += denali.o
 obj-$(CONFIG_NAND_DENALI_DT) += denali_dt.o
diff --git a/drivers/mtd/nand/raw/atmel/nand-controller.c b/drivers/mtd/nand/raw/atmel/nand-controller.c
index 56fbd64ef68..c90a4eab8df 100644
--- a/drivers/mtd/nand/raw/atmel/nand-controller.c
+++ b/drivers/mtd/nand/raw/atmel/nand-controller.c
@@ -1127,7 +1127,7 @@ static int atmel_smc_nand_prepare_smcconf(struct atmel_nand *nand,
 					  const struct nand_data_interface *conf,
 					  struct atmel_smc_cs_conf *smcconf)
 {
-	u32 ncycles, totalcycles, timeps, mckperiodps;
+	u32 ncycles, totalcycles, timeps, mckperiodps, pulse;
 	struct atmel_nand_controller *nc;
 	int ret;
 
@@ -1253,11 +1253,16 @@ static int atmel_smc_nand_prepare_smcconf(struct atmel_nand *nand,
 			 ATMEL_SMC_MODE_TDFMODE_OPTIMIZED;
 
 	/*
-	 * Read pulse timing directly matches tRP:
+	 * Read pulse timing would directly match tRP,
+	 * but some NAND flash chips (S34ML01G2 and W29N02KVxxAF)
+	 * do not work properly in timing mode 3.
+	 * The workaround is to extend the SMC NRD pulse to meet tREA
+	 * timing.
 	 *
-	 * NRD_PULSE = tRP
+	 * NRD_PULSE = max(tRP, tREA)
 	 */
-	ncycles = DIV_ROUND_UP(conf->timings.sdr.tRP_min, mckperiodps);
+	pulse = max(conf->timings.sdr.tRP_min, conf->timings.sdr.tREA_max);
+	ncycles = DIV_ROUND_UP(pulse, mckperiodps);
 	totalcycles += ncycles;
 	ret = atmel_smc_cs_conf_set_pulse(smcconf, ATMEL_SMC_NRD_SHIFT,
 					  ncycles);
diff --git a/drivers/mtd/nand/raw/cadence_nand.c b/drivers/mtd/nand/raw/cadence_nand.c
new file mode 100644
index 00000000000..27aa7f97a45
--- /dev/null
+++ b/drivers/mtd/nand/raw/cadence_nand.c
@@ -0,0 +1,2423 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Cadence NAND flash controller driver
+ *
+ * Copyright (C) 2019 Cadence
+ *
+ * Author: Piotr Sroka <piotrs@cadence.com>
+ *
+ */
+
+#include <cadence-nand.h>
+#include <clk.h>
+#include <dm.h>
+#include <hang.h>
+#include <malloc.h>
+#include <memalign.h>
+#include <nand.h>
+#include <reset.h>
+#include <wait_bit.h>
+#include <dm/device_compat.h>
+#include <dm/devres.h>
+#include <linux/bitfield.h>
+#include <linux/bug.h>
+#include <linux/delay.h>
+#include <linux/dma-direction.h>
+#include <linux/dma-mapping.h>
+#include <linux/io.h>
+#include <linux/iopoll.h>
+#include <linux/ioport.h>
+#include <linux/printk.h>
+#include <linux/sizes.h>
+
+static inline struct
+cdns_nand_chip *to_cdns_nand_chip(struct nand_chip *chip)
+{
+	return container_of(chip, struct cdns_nand_chip, chip);
+}
+
+static inline struct
+cadence_nand_info *to_cadence_nand_info(struct nand_hw_control *controller)
+{
+	return container_of(controller, struct cadence_nand_info, controller);
+}
+
+static bool
+cadence_nand_dma_buf_ok(struct cadence_nand_info *cadence, const void *buf,
+			u32 buf_len)
+{
+	u8 data_dma_width = cadence->caps2.data_dma_width;
+
+	return buf &&
+		likely(IS_ALIGNED((uintptr_t)buf, data_dma_width)) &&
+		likely(IS_ALIGNED(buf_len, DMA_DATA_SIZE_ALIGN));
+}
+
+static int cadence_nand_wait_for_value(struct cadence_nand_info *cadence,
+				       u32 reg_offset, u32 timeout_us,
+				       u32 mask, bool is_clear)
+{
+	u32 val;
+	int ret;
+
+	ret = readl_poll_sleep_timeout(cadence->reg + reg_offset,
+				       val, !(val & mask) == is_clear,
+				       10, timeout_us);
+
+	if (ret < 0) {
+		dev_err(cadence->dev,
+			"Timeout while waiting for reg %x with mask %x is clear %d\n",
+			reg_offset, mask, is_clear);
+	}
+
+	return ret;
+}
+
+static int cadence_nand_set_ecc_enable(struct cadence_nand_info *cadence,
+				       bool enable)
+{
+	u32 reg;
+
+	if (cadence_nand_wait_for_value(cadence, CTRL_STATUS,
+					TIMEOUT_US,
+					CTRL_STATUS_CTRL_BUSY, true))
+		return -ETIMEDOUT;
+
+	reg = readl_relaxed(cadence->reg + ECC_CONFIG_0);
+
+	if (enable)
+		reg |= ECC_CONFIG_0_ECC_EN;
+	else
+		reg &= ~ECC_CONFIG_0_ECC_EN;
+
+	writel_relaxed(reg, cadence->reg + ECC_CONFIG_0);
+
+	return 0;
+}
+
+static void cadence_nand_set_ecc_strength(struct cadence_nand_info *cadence,
+					  u8 corr_str_idx)
+{
+	u32 reg;
+
+	if (cadence->curr_corr_str_idx == corr_str_idx)
+		return;
+
+	reg = readl_relaxed(cadence->reg + ECC_CONFIG_0);
+	reg &= ~ECC_CONFIG_0_CORR_STR;
+	reg |= FIELD_PREP(ECC_CONFIG_0_CORR_STR, corr_str_idx);
+	writel_relaxed(reg, cadence->reg + ECC_CONFIG_0);
+
+	cadence->curr_corr_str_idx = corr_str_idx;
+}
+
+static int cadence_nand_get_ecc_strength_idx(struct cadence_nand_info *cadence,
+					     u8 strength)
+{
+	int i, corr_str_idx = -1;
+
+	for (i = 0; i < BCH_MAX_NUM_CORR_CAPS; i++) {
+		if (cadence->ecc_strengths[i] == strength) {
+			corr_str_idx = i;
+			break;
+		}
+	}
+
+	return corr_str_idx;
+}
+
+static int cadence_nand_set_skip_marker_val(struct cadence_nand_info *cadence,
+					    u16 marker_value)
+{
+	u32 reg;
+
+	if (cadence_nand_wait_for_value(cadence, CTRL_STATUS,
+					TIMEOUT_US,
+					CTRL_STATUS_CTRL_BUSY, true))
+		return -ETIMEDOUT;
+
+	reg = readl_relaxed(cadence->reg + SKIP_BYTES_CONF);
+	reg &= ~SKIP_BYTES_MARKER_VALUE;
+	reg |= FIELD_PREP(SKIP_BYTES_MARKER_VALUE,
+			  marker_value);
+
+	writel_relaxed(reg, cadence->reg + SKIP_BYTES_CONF);
+
+	return 0;
+}
+
+static int cadence_nand_set_skip_bytes_conf(struct cadence_nand_info *cadence,
+					    u8 num_of_bytes,
+					    u32 offset_value,
+					    int enable)
+{
+	u32 reg, skip_bytes_offset;
+
+	if (cadence_nand_wait_for_value(cadence, CTRL_STATUS,
+					TIMEOUT_US,
+					CTRL_STATUS_CTRL_BUSY, true))
+		return -ETIMEDOUT;
+
+	if (!enable) {
+		num_of_bytes = 0;
+		offset_value = 0;
+	}
+
+	reg = readl_relaxed(cadence->reg + SKIP_BYTES_CONF);
+	reg &= ~SKIP_BYTES_NUM_OF_BYTES;
+	reg |= FIELD_PREP(SKIP_BYTES_NUM_OF_BYTES,
+			  num_of_bytes);
+	skip_bytes_offset = FIELD_PREP(SKIP_BYTES_OFFSET_VALUE,
+				       offset_value);
+
+	writel_relaxed(reg, cadence->reg + SKIP_BYTES_CONF);
+	writel_relaxed(skip_bytes_offset, cadence->reg + SKIP_BYTES_OFFSET);
+
+	return 0;
+}
+
+/* Functions enables/disables hardware detection of erased data */
+static void cadence_nand_set_erase_detection(struct cadence_nand_info *cadence,
+					     bool enable,
+					     u8 bitflips_threshold)
+{
+	u32 reg;
+
+	reg = readl_relaxed(cadence->reg + ECC_CONFIG_0);
+
+	if (enable)
+		reg |= ECC_CONFIG_0_ERASE_DET_EN;
+	else
+		reg &= ~ECC_CONFIG_0_ERASE_DET_EN;
+
+	writel_relaxed(reg, cadence->reg + ECC_CONFIG_0);
+	writel_relaxed(bitflips_threshold, cadence->reg + ECC_CONFIG_1);
+}
+
+static int cadence_nand_set_access_width16(struct cadence_nand_info *cadence,
+					   bool bit_bus16)
+{
+	u32 reg;
+
+	if (cadence_nand_wait_for_value(cadence, CTRL_STATUS,
+					TIMEOUT_US,
+					CTRL_STATUS_CTRL_BUSY, true))
+		return -ETIMEDOUT;
+
+	reg = readl_relaxed(cadence->reg + COMMON_SET);
+	if (!bit_bus16)
+		reg &= ~COMMON_SET_DEVICE_16BIT;
+	else
+		reg |= COMMON_SET_DEVICE_16BIT;
+	writel_relaxed(reg, cadence->reg + COMMON_SET);
+
+	return 0;
+}
+
+static void
+cadence_nand_clear_interrupt(struct cadence_nand_info *cadence,
+			     struct cadence_nand_irq_status *irq_status)
+{
+	writel_relaxed(irq_status->status, cadence->reg + INTR_STATUS);
+	writel_relaxed(irq_status->trd_status,
+		       cadence->reg + TRD_COMP_INT_STATUS);
+	writel_relaxed(irq_status->trd_error,
+		       cadence->reg + TRD_ERR_INT_STATUS);
+}
+
+static void
+cadence_nand_read_int_status(struct cadence_nand_info *cadence,
+			     struct cadence_nand_irq_status *irq_status)
+{
+	irq_status->status = readl_relaxed(cadence->reg + INTR_STATUS);
+	irq_status->trd_status = readl_relaxed(cadence->reg
+					       + TRD_COMP_INT_STATUS);
+	irq_status->trd_error = readl_relaxed(cadence->reg
+					      + TRD_ERR_INT_STATUS);
+}
+
+static u32 irq_detected(struct cadence_nand_info *cadence,
+			struct cadence_nand_irq_status *irq_status)
+{
+	cadence_nand_read_int_status(cadence, irq_status);
+
+	return irq_status->status || irq_status->trd_status ||
+		irq_status->trd_error;
+}
+
+static void cadence_nand_reset_irq(struct cadence_nand_info *cadence)
+{
+	memset(&cadence->irq_status, 0, sizeof(cadence->irq_status));
+	memset(&cadence->irq_mask, 0, sizeof(cadence->irq_mask));
+}
+
+/*
+ * This is the interrupt service routine. It handles all interrupts
+ * sent to this device.
+ */
+static irqreturn_t cadence_nand_isr(struct cadence_nand_info *cadence)
+{
+	struct cadence_nand_irq_status irq_status;
+	irqreturn_t result = IRQ_NONE;
+
+	if (irq_detected(cadence, &irq_status)) {
+		/* Handle interrupt. */
+		/* First acknowledge it. */
+		cadence_nand_clear_interrupt(cadence, &irq_status);
+		/* Status in the device context for someone to read. */
+		cadence->irq_status.status |= irq_status.status;
+		cadence->irq_status.trd_status |= irq_status.trd_status;
+		cadence->irq_status.trd_error |= irq_status.trd_error;
+		/* Tell the OS that we've handled this. */
+		result = IRQ_HANDLED;
+	}
+	return result;
+}
+
+static void cadence_nand_set_irq_mask(struct cadence_nand_info *cadence,
+				      struct cadence_nand_irq_status *irq_mask)
+{
+	writel_relaxed(INTR_ENABLE_INTR_EN | irq_mask->status,
+		       cadence->reg + INTR_ENABLE);
+
+	writel_relaxed(irq_mask->trd_error,
+		       cadence->reg + TRD_ERR_INT_STATUS_EN);
+}
+
+static void
+cadence_nand_wait_for_irq(struct cadence_nand_info *cadence,
+			  struct cadence_nand_irq_status *irq_mask,
+			  struct cadence_nand_irq_status *irq_status)
+{
+	irqreturn_t result = IRQ_NONE;
+	u32 start = get_timer(0);
+
+	while (get_timer(start) < TIMEOUT_US) {
+		result = cadence_nand_isr(cadence);
+
+		if (result == IRQ_HANDLED) {
+			*irq_status = cadence->irq_status;
+			break;
+		}
+		udelay(1);
+	}
+
+	if (!result) {
+		/* Timeout error. */
+		dev_err(cadence->dev, "timeout occurred:\n");
+		dev_err(cadence->dev, "\tstatus = 0x%x, mask = 0x%x\n",
+			irq_status->status, irq_mask->status);
+		dev_err(cadence->dev,
+			"\ttrd_status = 0x%x, trd_status mask = 0x%x\n",
+			irq_status->trd_status, irq_mask->trd_status);
+		dev_err(cadence->dev,
+			"\t trd_error = 0x%x, trd_error mask = 0x%x\n",
+			irq_status->trd_error, irq_mask->trd_error);
+	}
+}
+
+/* Execute generic command on NAND controller. */
+static int cadence_nand_generic_cmd_send(struct cadence_nand_info *cadence,
+					 u8 chip_nr,
+					 u64 mini_ctrl_cmd)
+{
+	u32 mini_ctrl_cmd_l, mini_ctrl_cmd_h, reg;
+
+	mini_ctrl_cmd |= FIELD_PREP(GCMD_LAY_CS, chip_nr);
+	mini_ctrl_cmd_l = mini_ctrl_cmd & 0xFFFFFFFF;
+	mini_ctrl_cmd_h = mini_ctrl_cmd >> 32;
+
+	if (cadence_nand_wait_for_value(cadence, CTRL_STATUS,
+					TIMEOUT_US,
+					CTRL_STATUS_CTRL_BUSY, true))
+		return -ETIMEDOUT;
+
+	cadence_nand_reset_irq(cadence);
+
+	writel_relaxed(mini_ctrl_cmd_l, cadence->reg + CMD_REG2);
+	writel_relaxed(mini_ctrl_cmd_h, cadence->reg + CMD_REG3);
+
+	/* Select generic command. */
+	reg = FIELD_PREP(CMD_REG0_CT, CMD_REG0_CT_GEN);
+	/* Thread number. */
+	reg |= FIELD_PREP(CMD_REG0_TN, 0);
+
+	/* Issue command. */
+	writel_relaxed(reg, cadence->reg + CMD_REG0);
+	cadence->buf_index = 0;
+
+	return 0;
+}
+
+/* Wait for data on slave DMA interface. */
+static int cadence_nand_wait_on_sdma(struct cadence_nand_info *cadence, u8 *out_sdma_trd,
+				     u32 *out_sdma_size)
+{
+	struct cadence_nand_irq_status irq_mask, irq_status;
+
+	irq_mask.trd_status = 0;
+	irq_mask.trd_error = 0;
+	irq_mask.status = INTR_STATUS_SDMA_TRIGG
+		| INTR_STATUS_SDMA_ERR
+		| INTR_STATUS_UNSUPP_CMD;
+
+	cadence_nand_set_irq_mask(cadence, &irq_mask);
+	cadence_nand_wait_for_irq(cadence, &irq_mask, &irq_status);
+	if (irq_status.status == 0) {
+		dev_err(cadence->dev, "Timeout while waiting for SDMA\n");
+		return -ETIMEDOUT;
+	}
+
+	if (irq_status.status & INTR_STATUS_SDMA_TRIGG) {
+		*out_sdma_size = readl_relaxed(cadence->reg + SDMA_SIZE);
+		*out_sdma_trd  = readl_relaxed(cadence->reg + SDMA_TRD_NUM);
+		*out_sdma_trd =
+			FIELD_GET(SDMA_TRD_NUM_SDMA_TRD, *out_sdma_trd);
+	} else {
+		dev_err(cadence->dev, "SDMA error - irq_status %x\n",
+			irq_status.status);
+		return -EIO;
+	}
+
+	return 0;
+}
+
+static void cadence_nand_get_caps(struct cadence_nand_info *cadence)
+{
+	u32  reg;
+
+	reg = readl_relaxed(cadence->reg + CTRL_FEATURES);
+
+	cadence->caps2.max_banks = 1 << FIELD_GET(CTRL_FEATURES_N_BANKS, reg);
+
+	if (FIELD_GET(CTRL_FEATURES_DMA_DWITH64, reg))
+		cadence->caps2.data_dma_width = 8;
+	else
+		cadence->caps2.data_dma_width = 4;
+
+	if (reg & CTRL_FEATURES_CONTROL_DATA)
+		cadence->caps2.data_control_supp = true;
+
+	if (reg & (CTRL_FEATURES_NVDDR_2_3
+		   | CTRL_FEATURES_NVDDR))
+		cadence->caps2.is_phy_type_dll = true;
+}
+
+/* Prepare CDMA descriptor. */
+static void
+cadence_nand_cdma_desc_prepare(struct cadence_nand_info *cadence,
+			       char nf_mem, u32 flash_ptr, dma_addr_t mem_ptr,
+			       dma_addr_t ctrl_data_ptr, u16 ctype)
+{
+	struct cadence_nand_cdma_desc *cdma_desc = cadence->cdma_desc;
+
+	memset(cdma_desc, 0, sizeof(struct cadence_nand_cdma_desc));
+
+	/* Set fields for one descriptor. */
+	cdma_desc->flash_pointer = flash_ptr;
+	if (cadence->ctrl_rev >= 13)
+		cdma_desc->bank = nf_mem;
+	else
+		cdma_desc->flash_pointer |= (nf_mem << CDMA_CFPTR_MEM_SHIFT);
+
+	cdma_desc->command_flags |= CDMA_CF_DMA_MASTER;
+	cdma_desc->command_flags  |= CDMA_CF_INT;
+
+	cdma_desc->memory_pointer = mem_ptr;
+	cdma_desc->status = 0;
+	cdma_desc->sync_flag_pointer = 0;
+	cdma_desc->sync_arguments = 0;
+
+	cdma_desc->command_type = ctype;
+	cdma_desc->ctrl_data_ptr = ctrl_data_ptr;
+
+	flush_cache((dma_addr_t)cadence->cdma_desc,
+		    ROUND(sizeof(struct cadence_nand_cdma_desc),
+			  ARCH_DMA_MINALIGN));
+}
+
+static u8 cadence_nand_check_desc_error(struct cadence_nand_info *cadence,
+					u32 desc_status)
+{
+	if (desc_status & CDMA_CS_ERP)
+		return STAT_ERASED;
+
+	if (desc_status & CDMA_CS_UNCE)
+		return STAT_ECC_UNCORR;
+
+	if (desc_status & CDMA_CS_ERR) {
+		dev_err(cadence->dev, ":CDMA desc error flag detected.\n");
+		return STAT_FAIL;
+	}
+
+	if (FIELD_GET(CDMA_CS_MAXERR, desc_status))
+		return STAT_ECC_CORR;
+
+	return STAT_FAIL;
+}
+
+static int cadence_nand_cdma_finish(struct cadence_nand_info *cadence)
+{
+	struct cadence_nand_cdma_desc *desc_ptr = cadence->cdma_desc;
+	u8 status = STAT_BUSY;
+
+	invalidate_dcache_range((dma_addr_t)cadence->cdma_desc,
+				(dma_addr_t)cadence->cdma_desc +
+				ROUND(sizeof(struct cadence_nand_cdma_desc),
+				      ARCH_DMA_MINALIGN));
+
+	if (desc_ptr->status & CDMA_CS_FAIL) {
+		status = cadence_nand_check_desc_error(cadence,
+						       desc_ptr->status);
+		dev_err(cadence->dev, ":CDMA error %x\n", desc_ptr->status);
+	} else if (desc_ptr->status & CDMA_CS_COMP) {
+		/* Descriptor finished with no errors. */
+		if (desc_ptr->command_flags & CDMA_CF_CONT) {
+			dev_info(cadence->dev, "DMA unsupported flag is set");
+			status = STAT_UNKNOWN;
+		} else {
+			/* Last descriptor.  */
+			status = STAT_OK;
+		}
+	}
+
+	return status;
+}
+
+static int cadence_nand_cdma_send(struct cadence_nand_info *cadence,
+				  u8 thread)
+{
+	u32 reg;
+	int status;
+
+	/* Wait for thread ready. */
+	status = cadence_nand_wait_for_value(cadence, TRD_STATUS,
+					     TIMEOUT_US,
+					     BIT(thread), true);
+	if (status)
+		return status;
+
+	cadence_nand_reset_irq(cadence);
+
+	writel_relaxed((u32)cadence->dma_cdma_desc,
+		       cadence->reg + CMD_REG2);
+	writel_relaxed(0, cadence->reg + CMD_REG3);
+
+	/* Select CDMA mode. */
+	reg = FIELD_PREP(CMD_REG0_CT, CMD_REG0_CT_CDMA);
+	/* Thread number. */
+	reg |= FIELD_PREP(CMD_REG0_TN, thread);
+	/* Issue command. */
+	writel_relaxed(reg, cadence->reg + CMD_REG0);
+
+	return 0;
+}
+
+/* Send SDMA command and wait for finish. */
+static u32
+cadence_nand_cdma_send_and_wait(struct cadence_nand_info *cadence,
+				u8 thread)
+{
+	struct cadence_nand_irq_status irq_mask, irq_status = {0};
+	int status;
+	u32 val;
+
+	irq_mask.trd_status = BIT(thread);
+	irq_mask.trd_error = BIT(thread);
+	irq_mask.status = INTR_STATUS_CDMA_TERR;
+
+	cadence_nand_set_irq_mask(cadence, &irq_mask);
+
+	status = cadence_nand_cdma_send(cadence, thread);
+	if (status)
+		return status;
+
+	/* Make sure the descriptor processing is complete */
+	status = readl_poll_timeout(cadence->reg + TRD_COMP_INT_STATUS, val,
+				    (val & BIT(thread)), TIMEOUT_US);
+	if (status) {
+		pr_err("cmd thread completion timeout!\n");
+		return status;
+	}
+
+	cadence_nand_wait_for_irq(cadence, &irq_mask, &irq_status);
+
+	if (irq_status.status == 0 && irq_status.trd_status == 0 &&
+	    irq_status.trd_error == 0) {
+		dev_err(cadence->dev, "CDMA command timeout\n");
+		return -ETIMEDOUT;
+	}
+	if (irq_status.status & irq_mask.status) {
+		dev_err(cadence->dev, "CDMA command failed\n");
+		return -EIO;
+	}
+
+	return 0;
+}
+
+/*
+ * ECC size depends on configured ECC strength and on maximum supported
+ * ECC step size.
+ */
+static int cadence_nand_calc_ecc_bytes(int max_step_size, int strength)
+{
+	int nbytes = DIV_ROUND_UP(fls(8 * max_step_size) * strength, 8);
+
+	return ALIGN(nbytes, 2);
+}
+
+#define CADENCE_NAND_CALC_ECC_BYTES(max_step_size) \
+	static int \
+	cadence_nand_calc_ecc_bytes_##max_step_size(int step_size, \
+						    int strength)\
+	{\
+		return cadence_nand_calc_ecc_bytes(max_step_size, strength);\
+	}
+
+CADENCE_NAND_CALC_ECC_BYTES(256)
+CADENCE_NAND_CALC_ECC_BYTES(512)
+CADENCE_NAND_CALC_ECC_BYTES(1024)
+CADENCE_NAND_CALC_ECC_BYTES(2048)
+CADENCE_NAND_CALC_ECC_BYTES(4096)
+
+/* Function reads BCH capabilities. */
+static int cadence_nand_read_bch_caps(struct cadence_nand_info *cadence)
+{
+	struct nand_ecc_caps *ecc_caps = &cadence->ecc_caps;
+	int max_step_size = 0, nstrengths, i;
+	u32 reg;
+
+	reg = readl_relaxed(cadence->reg + BCH_CFG_3);
+	cadence->bch_metadata_size = FIELD_GET(BCH_CFG_3_METADATA_SIZE, reg);
+	if (cadence->bch_metadata_size < 4) {
+		dev_err(cadence->dev,
+			"Driver needs at least 4 bytes of BCH meta data\n");
+		return -EIO;
+	}
+
+	reg = readl_relaxed(cadence->reg + BCH_CFG_0);
+	cadence->ecc_strengths[0] = FIELD_GET(BCH_CFG_0_CORR_CAP_0, reg);
+	cadence->ecc_strengths[1] = FIELD_GET(BCH_CFG_0_CORR_CAP_1, reg);
+	cadence->ecc_strengths[2] = FIELD_GET(BCH_CFG_0_CORR_CAP_2, reg);
+	cadence->ecc_strengths[3] = FIELD_GET(BCH_CFG_0_CORR_CAP_3, reg);
+
+	reg = readl_relaxed(cadence->reg + BCH_CFG_1);
+	cadence->ecc_strengths[4] = FIELD_GET(BCH_CFG_1_CORR_CAP_4, reg);
+	cadence->ecc_strengths[5] = FIELD_GET(BCH_CFG_1_CORR_CAP_5, reg);
+	cadence->ecc_strengths[6] = FIELD_GET(BCH_CFG_1_CORR_CAP_6, reg);
+	cadence->ecc_strengths[7] = FIELD_GET(BCH_CFG_1_CORR_CAP_7, reg);
+
+	reg = readl_relaxed(cadence->reg + BCH_CFG_2);
+	cadence->ecc_stepinfos[0].stepsize =
+		FIELD_GET(BCH_CFG_2_SECT_0, reg);
+
+	cadence->ecc_stepinfos[1].stepsize =
+		FIELD_GET(BCH_CFG_2_SECT_1, reg);
+
+	nstrengths = 0;
+	for (i = 0; i < BCH_MAX_NUM_CORR_CAPS; i++) {
+		if (cadence->ecc_strengths[i] != 0)
+			nstrengths++;
+	}
+
+	ecc_caps->nstepinfos = 0;
+	for (i = 0; i < BCH_MAX_NUM_SECTOR_SIZES; i++) {
+		/* ECC strengths are common for all step infos. */
+		cadence->ecc_stepinfos[i].nstrengths = nstrengths;
+		cadence->ecc_stepinfos[i].strengths =
+			cadence->ecc_strengths;
+
+		if (cadence->ecc_stepinfos[i].stepsize != 0)
+			ecc_caps->nstepinfos++;
+
+		if (cadence->ecc_stepinfos[i].stepsize > max_step_size)
+			max_step_size = cadence->ecc_stepinfos[i].stepsize;
+	}
+	ecc_caps->stepinfos = &cadence->ecc_stepinfos[0];
+
+	switch (max_step_size) {
+	case 256:
+		ecc_caps->calc_ecc_bytes = &cadence_nand_calc_ecc_bytes_256;
+		break;
+	case 512:
+		ecc_caps->calc_ecc_bytes = &cadence_nand_calc_ecc_bytes_512;
+		break;
+	case 1024:
+		ecc_caps->calc_ecc_bytes = &cadence_nand_calc_ecc_bytes_1024;
+		break;
+	case 2048:
+		ecc_caps->calc_ecc_bytes = &cadence_nand_calc_ecc_bytes_2048;
+		break;
+	case 4096:
+		ecc_caps->calc_ecc_bytes = &cadence_nand_calc_ecc_bytes_4096;
+		break;
+	default:
+		dev_err(cadence->dev,
+			"Unsupported sector size(ecc step size) %d\n",
+			max_step_size);
+		return -EIO;
+	}
+
+	return 0;
+}
+
+/* Hardware initialization. */
+static int cadence_nand_hw_init(struct cadence_nand_info *cadence)
+{
+	int status;
+	u32 reg;
+
+	status = cadence_nand_wait_for_value(cadence, CTRL_STATUS,
+					     TIMEOUT_US,
+					     CTRL_STATUS_INIT_COMP, false);
+	if (status)
+		return status;
+
+	reg = readl_relaxed(cadence->reg + CTRL_VERSION);
+	cadence->ctrl_rev = FIELD_GET(CTRL_VERSION_REV, reg);
+
+	dev_info(cadence->dev,
+		 "%s: cadence nand controller version reg %x\n",
+		 __func__, reg);
+
+	/* Disable cache and multiplane. */
+	writel_relaxed(0, cadence->reg + MULTIPLANE_CFG);
+	writel_relaxed(0, cadence->reg + CACHE_CFG);
+
+	/* Clear all interrupts. */
+	writel_relaxed(0xFFFFFFFF, cadence->reg + INTR_STATUS);
+
+	cadence_nand_get_caps(cadence);
+	if (cadence_nand_read_bch_caps(cadence))
+		return -EIO;
+
+	/*
+	 * Set IO width access to 8.
+	 * It is because during SW device discovering width access
+	 * is expected to be 8.
+	 */
+	status = cadence_nand_set_access_width16(cadence, false);
+
+	return status;
+}
+
+#define TT_MAIN_OOB_AREAS		2
+#define TT_RAW_PAGE			3
+#define TT_BBM				4
+#define TT_MAIN_OOB_AREA_EXT		5
+
+/* Prepare size of data to transfer. */
+static void
+cadence_nand_prepare_data_size(struct mtd_info *mtd,
+			       int transfer_type)
+{
+	struct nand_chip *chip = mtd_to_nand(mtd);
+	struct cadence_nand_info *cadence = to_cadence_nand_info(chip->controller);
+	struct cdns_nand_chip *cdns_chip = to_cdns_nand_chip(chip);
+	u32 sec_size = 0, offset = 0, sec_cnt = 1;
+	u32 last_sec_size = cdns_chip->sector_size;
+	u32 data_ctrl_size = 0;
+	u32 reg = 0;
+
+	if (cadence->curr_trans_type == transfer_type)
+		return;
+
+	switch (transfer_type) {
+	case TT_MAIN_OOB_AREA_EXT:
+		sec_cnt = cdns_chip->sector_count;
+		sec_size = cdns_chip->sector_size;
+		data_ctrl_size = cdns_chip->avail_oob_size;
+		break;
+	case TT_MAIN_OOB_AREAS:
+		sec_cnt = cdns_chip->sector_count;
+		last_sec_size = cdns_chip->sector_size
+			+ cdns_chip->avail_oob_size;
+		sec_size = cdns_chip->sector_size;
+		break;
+	case TT_RAW_PAGE:
+		last_sec_size = mtd->writesize + mtd->oobsize;
+		break;
+	case TT_BBM:
+		offset = mtd->writesize + cdns_chip->bbm_offs;
+		last_sec_size = 8;
+		break;
+	}
+
+	reg = 0;
+	reg |= FIELD_PREP(TRAN_CFG_0_OFFSET, offset);
+	reg |= FIELD_PREP(TRAN_CFG_0_SEC_CNT, sec_cnt);
+	writel_relaxed(reg, cadence->reg + TRAN_CFG_0);
+
+	reg = 0;
+	reg |= FIELD_PREP(TRAN_CFG_1_LAST_SEC_SIZE, last_sec_size);
+	reg |= FIELD_PREP(TRAN_CFG_1_SECTOR_SIZE, sec_size);
+	writel_relaxed(reg, cadence->reg + TRAN_CFG_1);
+
+	if (cadence->caps2.data_control_supp) {
+		reg = readl_relaxed(cadence->reg + CONTROL_DATA_CTRL);
+		reg &= ~CONTROL_DATA_CTRL_SIZE;
+		reg |= FIELD_PREP(CONTROL_DATA_CTRL_SIZE, data_ctrl_size);
+		writel_relaxed(reg, cadence->reg + CONTROL_DATA_CTRL);
+	}
+
+	cadence->curr_trans_type = transfer_type;
+}
+
+static int
+cadence_nand_cdma_transfer(struct cadence_nand_info *cadence, u8 chip_nr,
+			   int page, void *buf, void *ctrl_dat, u32 buf_size,
+			   u32 ctrl_dat_size, enum dma_data_direction dir,
+			   bool with_ecc)
+{
+	dma_addr_t dma_buf, dma_ctrl_dat = 0;
+	u8 thread_nr = chip_nr;
+	int status;
+	u16 ctype;
+
+	if (dir == DMA_FROM_DEVICE)
+		ctype = CDMA_CT_RD;
+	else
+		ctype = CDMA_CT_WR;
+
+	cadence_nand_set_ecc_enable(cadence, with_ecc);
+
+	dma_buf = dma_map_single(buf, buf_size, dir);
+	if (dma_mapping_error(cadence->dev, dma_buf)) {
+		dev_err(cadence->dev, "Failed to map DMA buffer\n");
+		return -EIO;
+	}
+
+	if (ctrl_dat && ctrl_dat_size) {
+		dma_ctrl_dat = dma_map_single(ctrl_dat,
+					      ctrl_dat_size, dir);
+		if (dma_mapping_error(cadence->dev, dma_ctrl_dat)) {
+			dma_unmap_single(dma_buf,
+					 buf_size, dir);
+			dev_err(cadence->dev, "Failed to map DMA buffer\n");
+			return -EIO;
+		}
+	}
+
+	cadence_nand_cdma_desc_prepare(cadence, chip_nr, page,
+				       dma_buf, dma_ctrl_dat, ctype);
+
+	status = cadence_nand_cdma_send_and_wait(cadence, thread_nr);
+
+	dma_unmap_single(dma_buf,
+			 buf_size, dir);
+
+	if (ctrl_dat && ctrl_dat_size)
+		dma_unmap_single(dma_ctrl_dat,
+				 ctrl_dat_size, dir);
+	if (status)
+		return status;
+
+	return cadence_nand_cdma_finish(cadence);
+}
+
+static void cadence_nand_set_timings(struct cadence_nand_info *cadence,
+				     struct cadence_nand_timings *t)
+{
+	writel_relaxed(t->async_toggle_timings,
+		       cadence->reg + ASYNC_TOGGLE_TIMINGS);
+	writel_relaxed(t->timings0, cadence->reg + TIMINGS0);
+	writel_relaxed(t->timings1, cadence->reg + TIMINGS1);
+	writel_relaxed(t->timings2, cadence->reg + TIMINGS2);
+
+	if (cadence->caps2.is_phy_type_dll)
+		writel_relaxed(t->dll_phy_ctrl, cadence->reg + DLL_PHY_CTRL);
+
+	writel_relaxed(t->phy_ctrl, cadence->reg + PHY_CTRL);
+
+	if (cadence->caps2.is_phy_type_dll) {
+		writel_relaxed(0, cadence->reg + PHY_TSEL);
+		writel_relaxed(2, cadence->reg + PHY_DQ_TIMING);
+		writel_relaxed(t->phy_dqs_timing,
+			       cadence->reg + PHY_DQS_TIMING);
+		writel_relaxed(t->phy_gate_lpbk_ctrl,
+			       cadence->reg + PHY_GATE_LPBK_CTRL);
+		writel_relaxed(PHY_DLL_MASTER_CTRL_BYPASS_MODE,
+			       cadence->reg + PHY_DLL_MASTER_CTRL);
+		writel_relaxed(0, cadence->reg + PHY_DLL_SLAVE_CTRL);
+	}
+}
+
+static int cadence_nand_select_target(struct nand_chip *chip)
+{
+	struct cadence_nand_info *cadence = to_cadence_nand_info(chip->controller);
+	struct cdns_nand_chip *cdns_chip = to_cdns_nand_chip(chip);
+
+	if (chip == cadence->selected_chip)
+		return 0;
+
+	if (cadence_nand_wait_for_value(cadence, CTRL_STATUS,
+					TIMEOUT_US,
+					CTRL_STATUS_CTRL_BUSY, true))
+		return -ETIMEDOUT;
+
+	cadence_nand_set_timings(cadence, &cdns_chip->timings);
+
+	cadence_nand_set_ecc_strength(cadence,
+				      cdns_chip->corr_str_idx);
+
+	cadence_nand_set_erase_detection(cadence, true,
+					 chip->ecc.strength);
+
+	cadence->curr_trans_type = -1;
+	cadence->selected_chip = chip;
+
+	return 0;
+}
+
+static int cadence_nand_erase(struct mtd_info *mtd, int page)
+{
+	struct nand_chip *chip = mtd_to_nand(mtd);
+	struct cadence_nand_info *cadence = to_cadence_nand_info(chip->controller);
+	struct cdns_nand_chip *cdns_chip = to_cdns_nand_chip(chip);
+	int status;
+	u8 thread_nr = cdns_chip->cs[chip->cur_cs];
+
+	cadence_nand_cdma_desc_prepare(cadence,
+				       cdns_chip->cs[chip->cur_cs],
+				       page, 0, 0,
+				       CDMA_CT_ERASE);
+	status = cadence_nand_cdma_send_and_wait(cadence, thread_nr);
+	if (status) {
+		dev_err(cadence->dev, "erase operation failed\n");
+		return -EIO;
+	}
+
+	status = cadence_nand_cdma_finish(cadence);
+	if (status)
+		return status;
+
+	return 0;
+}
+
+static int cadence_ecc_setup(struct mtd_info *mtd, struct nand_chip *chip, int oobavail)
+{
+	struct cadence_nand_info *cadence = to_cadence_nand_info(chip->controller);
+	int ret;
+
+	/*
+	 * If .size and .strength are already set (usually by DT),
+	 * check if they are supported by this controller.
+	 */
+	if (chip->ecc.size && chip->ecc.strength)
+		return nand_check_ecc_caps(chip, &cadence->ecc_caps, oobavail);
+
+	/*
+	 * We want .size and .strength closest to the chip's requirement
+	 * unless NAND_ECC_MAXIMIZE is requested.
+	 */
+	if (!(chip->ecc.options & NAND_ECC_MAXIMIZE)) {
+		ret = nand_match_ecc_req(chip, &cadence->ecc_caps, oobavail);
+		if (!ret)
+			return 0;
+	}
+
+	/* Max ECC strength is the last thing we can do */
+	return nand_maximize_ecc(chip, &cadence->ecc_caps, oobavail);
+}
+
+static int cadence_nand_read_bbm(struct mtd_info *mtd, struct nand_chip *chip, int page, u8 *buf)
+{
+	int status;
+	struct cadence_nand_info *cadence = to_cadence_nand_info(chip->controller);
+	struct cdns_nand_chip *cdns_chip = to_cdns_nand_chip(chip);
+
+	cadence_nand_prepare_data_size(mtd, TT_BBM);
+
+	cadence_nand_set_skip_bytes_conf(cadence, 0, 0, 0);
+
+	/*
+	 * Read only bad block marker from offset
+	 * defined by a memory manufacturer.
+	 */
+	status = cadence_nand_cdma_transfer(cadence,
+					    cdns_chip->cs[chip->cur_cs],
+					    page, cadence->buf, NULL,
+					    mtd->oobsize,
+					    0, DMA_FROM_DEVICE, false);
+	if (status) {
+		dev_err(cadence->dev, "read BBM failed\n");
+		return -EIO;
+	}
+
+	memcpy(buf + cdns_chip->bbm_offs, cadence->buf, cdns_chip->bbm_len);
+
+	return 0;
+}
+
+static int cadence_nand_write_page(struct mtd_info *mtd, struct nand_chip *chip,
+				   const u8 *buf, int oob_required, int page)
+{
+	struct cadence_nand_info *cadence = to_cadence_nand_info(chip->controller);
+	struct cdns_nand_chip *cdns_chip = to_cdns_nand_chip(chip);
+	int status;
+	u16 marker_val = 0xFFFF;
+
+	status = cadence_nand_select_target(chip);
+	if (status)
+		return status;
+
+	cadence_nand_set_skip_bytes_conf(cadence, cdns_chip->bbm_len,
+					 mtd->writesize
+					 + cdns_chip->bbm_offs,
+					 1);
+
+	if (oob_required) {
+		marker_val = *(u16 *)(chip->oob_poi
+				      + cdns_chip->bbm_offs);
+	} else {
+		/* Set oob data to 0xFF. */
+		memset(cadence->buf + mtd->writesize, 0xFF,
+		       cdns_chip->avail_oob_size);
+	}
+
+	cadence_nand_set_skip_marker_val(cadence, marker_val);
+
+	cadence_nand_prepare_data_size(mtd, TT_MAIN_OOB_AREA_EXT);
+
+	if (cadence_nand_dma_buf_ok(cadence, buf, mtd->writesize) &&
+	    cadence->caps2.data_control_supp && !(chip->options & NAND_USE_BOUNCE_BUFFER)) {
+		u8 *oob;
+
+		if (oob_required)
+			oob = chip->oob_poi;
+		else
+			oob = cadence->buf + mtd->writesize;
+
+		status = cadence_nand_cdma_transfer(cadence,
+						    cdns_chip->cs[chip->cur_cs],
+						    page, (void *)buf, oob,
+						    mtd->writesize,
+						    cdns_chip->avail_oob_size,
+						    DMA_TO_DEVICE, true);
+		if (status) {
+			dev_err(cadence->dev, "write page failed\n");
+			return -EIO;
+		}
+
+		return 0;
+	}
+
+	if (oob_required) {
+		/* Transfer the data to the oob area. */
+		memcpy(cadence->buf + mtd->writesize, chip->oob_poi,
+		       cdns_chip->avail_oob_size);
+	}
+
+	memcpy(cadence->buf, buf, mtd->writesize);
+
+	cadence_nand_prepare_data_size(mtd, TT_MAIN_OOB_AREAS);
+
+	return cadence_nand_cdma_transfer(cadence,
+					  cdns_chip->cs[chip->cur_cs],
+					  page, cadence->buf, NULL,
+					  mtd->writesize
+					  + cdns_chip->avail_oob_size,
+					  0, DMA_TO_DEVICE, true);
+}
+
+static int cadence_nand_write_oob(struct mtd_info *mtd, struct nand_chip *chip,
+				  int page)
+{
+	struct cadence_nand_info *cadence = to_cadence_nand_info(chip->controller);
+
+	memset(cadence->buf, 0xFF, mtd->writesize);
+
+	return cadence_nand_write_page(mtd, chip, cadence->buf, 1, page);
+}
+
+static int cadence_nand_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
+				       const u8 *buf, int oob_required, int page)
+{
+	struct cadence_nand_info *cadence = to_cadence_nand_info(chip->controller);
+	struct cdns_nand_chip *cdns_chip = to_cdns_nand_chip(chip);
+	int writesize = mtd->writesize;
+	int oobsize = mtd->oobsize;
+	int ecc_steps = chip->ecc.steps;
+	int ecc_size = chip->ecc.size;
+	int ecc_bytes = chip->ecc.bytes;
+	void *tmp_buf = cadence->buf;
+	int oob_skip = cdns_chip->bbm_len;
+	size_t size = writesize + oobsize;
+	int i, pos, len;
+	int status;
+
+	status = cadence_nand_select_target(chip);
+	if (status)
+		return status;
+
+	/*
+	 * Fill the buffer with 0xff first except the full page transfer.
+	 * This simplifies the logic.
+	 */
+	if (!buf || !oob_required)
+		memset(tmp_buf, 0xff, size);
+
+	cadence_nand_set_skip_bytes_conf(cadence, 0, 0, 0);
+
+	/* Arrange the buffer for syndrome payload/ecc layout. */
+	if (buf) {
+		for (i = 0; i < ecc_steps; i++) {
+			pos = i * (ecc_size + ecc_bytes);
+			len = ecc_size;
+
+			if (pos >= writesize)
+				pos += oob_skip;
+			else if (pos + len > writesize)
+				len = writesize - pos;
+
+			memcpy(tmp_buf + pos, buf, len);
+			buf += len;
+			if (len < ecc_size) {
+				len = ecc_size - len;
+				memcpy(tmp_buf + writesize + oob_skip, buf,
+				       len);
+				buf += len;
+			}
+		}
+	}
+
+	if (oob_required) {
+		const u8 *oob = chip->oob_poi;
+		u32 oob_data_offset = (cdns_chip->sector_count - 1) *
+			(cdns_chip->sector_size + chip->ecc.bytes)
+			+ cdns_chip->sector_size + oob_skip;
+
+		/* BBM at the beginning of the OOB area. */
+		memcpy(tmp_buf + writesize, oob, oob_skip);
+
+		/* OOB free. */
+		memcpy(tmp_buf + oob_data_offset, oob,
+		       cdns_chip->avail_oob_size);
+		oob += cdns_chip->avail_oob_size;
+
+		/* OOB ECC. */
+		for (i = 0; i < ecc_steps; i++) {
+			pos = ecc_size + i * (ecc_size + ecc_bytes);
+			if (i == (ecc_steps - 1))
+				pos += cdns_chip->avail_oob_size;
+
+			len = ecc_bytes;
+
+			if (pos >= writesize)
+				pos += oob_skip;
+			else if (pos + len > writesize)
+				len = writesize - pos;
+
+			memcpy(tmp_buf + pos, oob, len);
+			oob += len;
+			if (len < ecc_bytes) {
+				len = ecc_bytes - len;
+				memcpy(tmp_buf + writesize + oob_skip, oob,
+				       len);
+				oob += len;
+			}
+		}
+	}
+
+	cadence_nand_prepare_data_size(mtd, TT_RAW_PAGE);
+
+	return cadence_nand_cdma_transfer(cadence,
+					  cdns_chip->cs[chip->cur_cs],
+					  page, cadence->buf, NULL,
+					  mtd->writesize +
+					  mtd->oobsize,
+					  0, DMA_TO_DEVICE, false);
+}
+
+static int cadence_nand_write_oob_raw(struct mtd_info *mtd, struct nand_chip *chip,
+				      int page)
+{
+	return cadence_nand_write_page_raw(mtd, chip, NULL, true, page);
+}
+
+static int cadence_nand_read_page(struct mtd_info *mtd, struct nand_chip *chip,
+				  u8 *buf, int oob_required, int page)
+{
+	struct cadence_nand_info *cadence = to_cadence_nand_info(chip->controller);
+	struct cdns_nand_chip *cdns_chip = to_cdns_nand_chip(chip);
+	int status;
+	int ecc_err_count = 0;
+
+	status = cadence_nand_select_target(chip);
+	if (status)
+		return status;
+
+	cadence_nand_set_skip_bytes_conf(cadence, cdns_chip->bbm_len,
+					 mtd->writesize
+					 + cdns_chip->bbm_offs, 1);
+
+	/*
+	 * If data buffer can be accessed by DMA and data_control feature
+	 * is supported then transfer data and oob directly.
+	 */
+	if (cadence_nand_dma_buf_ok(cadence, buf, mtd->writesize) &&
+	    cadence->caps2.data_control_supp && !(chip->options & NAND_USE_BOUNCE_BUFFER)) {
+		u8 *oob;
+
+		if (oob_required)
+			oob = chip->oob_poi;
+		else
+			oob = cadence->buf + mtd->writesize;
+
+		cadence_nand_prepare_data_size(mtd, TT_MAIN_OOB_AREA_EXT);
+		status = cadence_nand_cdma_transfer(cadence,
+						    cdns_chip->cs[chip->cur_cs],
+						    page, buf, oob,
+						    mtd->writesize,
+						    cdns_chip->avail_oob_size,
+						    DMA_FROM_DEVICE, true);
+	/* Otherwise use bounce buffer. */
+	} else {
+		cadence_nand_prepare_data_size(mtd, TT_MAIN_OOB_AREAS);
+		status = cadence_nand_cdma_transfer(cadence,
+						    cdns_chip->cs[chip->cur_cs],
+						    page, cadence->buf,
+						    NULL, mtd->writesize
+						    + cdns_chip->avail_oob_size,
+						    0, DMA_FROM_DEVICE, true);
+
+		memcpy(buf, cadence->buf, mtd->writesize);
+		if (oob_required)
+			memcpy(chip->oob_poi,
+			       cadence->buf + mtd->writesize,
+			       mtd->oobsize);
+	}
+
+	switch (status) {
+	case STAT_ECC_UNCORR:
+		mtd->ecc_stats.failed++;
+		ecc_err_count++;
+		break;
+	case STAT_ECC_CORR:
+		ecc_err_count = FIELD_GET(CDMA_CS_MAXERR,
+					  cadence->cdma_desc->status);
+		mtd->ecc_stats.corrected += ecc_err_count;
+		break;
+	case STAT_ERASED:
+	case STAT_OK:
+		break;
+	default:
+		dev_err(cadence->dev, "read page failed\n");
+		return -EIO;
+	}
+
+	if (oob_required)
+		if (cadence_nand_read_bbm(mtd, chip, page, chip->oob_poi))
+			return -EIO;
+
+	return ecc_err_count;
+}
+
+static int cadence_nand_read_oob(struct mtd_info *mtd, struct nand_chip *chip,
+				 int page)
+{
+	struct cadence_nand_info *cadence = to_cadence_nand_info(chip->controller);
+
+	return cadence_nand_read_page(mtd, chip, cadence->buf, 1, page);
+}
+
+static int cadence_nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
+				      u8 *buf, int oob_required, int page)
+{
+	struct cadence_nand_info *cadence = to_cadence_nand_info(chip->controller);
+	struct cdns_nand_chip *cdns_chip = to_cdns_nand_chip(chip);
+	int oob_skip = cdns_chip->bbm_len;
+	int writesize = mtd->writesize;
+	int ecc_steps = chip->ecc.steps;
+	int ecc_size = chip->ecc.size;
+	int ecc_bytes = chip->ecc.bytes;
+	void *tmp_buf = cadence->buf;
+	int i, pos, len;
+	int status;
+
+	status = cadence_nand_select_target(chip);
+	if (status)
+		return status;
+
+	cadence_nand_set_skip_bytes_conf(cadence, 0, 0, 0);
+
+	cadence_nand_prepare_data_size(mtd, TT_RAW_PAGE);
+	status = cadence_nand_cdma_transfer(cadence,
+					    cdns_chip->cs[chip->cur_cs],
+					    page, cadence->buf, NULL,
+					    mtd->writesize
+					    + mtd->oobsize,
+					    0, DMA_FROM_DEVICE, false);
+
+	switch (status) {
+	case STAT_ERASED:
+	case STAT_OK:
+		break;
+	default:
+		dev_err(cadence->dev, "read raw page failed\n");
+		return -EIO;
+	}
+
+	/* Arrange the buffer for syndrome payload/ecc layout. */
+	if (buf) {
+		for (i = 0; i < ecc_steps; i++) {
+			pos = i * (ecc_size + ecc_bytes);
+			len = ecc_size;
+
+			if (pos >= writesize)
+				pos += oob_skip;
+			else if (pos + len > writesize)
+				len = writesize - pos;
+
+			memcpy(buf, tmp_buf + pos, len);
+			buf += len;
+			if (len < ecc_size) {
+				len = ecc_size - len;
+				memcpy(buf, tmp_buf + writesize + oob_skip,
+				       len);
+				buf += len;
+			}
+		}
+	}
+
+	if (oob_required) {
+		u8 *oob = chip->oob_poi;
+		u32 oob_data_offset = (cdns_chip->sector_count - 1) *
+			(cdns_chip->sector_size + chip->ecc.bytes)
+			+ cdns_chip->sector_size + oob_skip;
+
+		/* OOB free. */
+		memcpy(oob, tmp_buf + oob_data_offset,
+		       cdns_chip->avail_oob_size);
+
+		/* BBM at the beginning of the OOB area. */
+		memcpy(oob, tmp_buf + writesize, oob_skip);
+
+		oob += cdns_chip->avail_oob_size;
+
+		/* OOB ECC */
+		for (i = 0; i < ecc_steps; i++) {
+			pos = ecc_size + i * (ecc_size + ecc_bytes);
+			len = ecc_bytes;
+
+			if (i == (ecc_steps - 1))
+				pos += cdns_chip->avail_oob_size;
+
+			if (pos >= writesize)
+				pos += oob_skip;
+			else if (pos + len > writesize)
+				len = writesize - pos;
+
+			memcpy(oob, tmp_buf + pos, len);
+			oob += len;
+			if (len < ecc_bytes) {
+				len = ecc_bytes - len;
+				memcpy(oob, tmp_buf + writesize + oob_skip,
+				       len);
+				oob += len;
+			}
+		}
+	}
+	return 0;
+}
+
+static int cadence_nand_read_oob_raw(struct mtd_info *mtd, struct nand_chip *chip,
+				     int page)
+{
+	return cadence_nand_read_page_raw(mtd, chip, NULL, true, page);
+}
+
+static void cadence_nand_read_buf(struct mtd_info *mtd, u8 *buf, int len)
+{
+	struct nand_chip *chip = mtd_to_nand(mtd);
+	struct cadence_nand_info *cadence = to_cadence_nand_info(chip->controller);
+	u8 thread_nr = 0;
+	u32 sdma_size;
+	int status;
+	int len_in_words = len >> 2;
+
+	/* Wait until slave DMA interface is ready to data transfer. */
+	status = cadence_nand_wait_on_sdma(cadence, &thread_nr, &sdma_size);
+	if (status) {
+		pr_err("Wait on sdma failed:%x\n", status);
+		hang();
+	}
+
+	if (!cadence->caps1->has_dma) {
+		readsq(cadence->io.virt, buf, len_in_words);
+
+		if (sdma_size > len) {
+			memcpy(cadence->buf, buf + (len_in_words << 2),
+			       len - (len_in_words << 2));
+			readsl(cadence->io.virt, cadence->buf,
+			       sdma_size / 4 - len_in_words);
+		}
+	}
+}
+
+static void cadence_nand_write_buf(struct mtd_info *mtd, const u8 *buf, int len)
+{
+	struct nand_chip *chip = mtd_to_nand(mtd);
+	struct cadence_nand_info *cadence = to_cadence_nand_info(chip->controller);
+	u8 thread_nr = 0;
+	u32 sdma_size;
+	int status;
+	int len_in_words = len >> 2;
+
+	/* Wait until slave DMA interface is ready to data transfer. */
+	status = cadence_nand_wait_on_sdma(cadence, &thread_nr, &sdma_size);
+	if (status) {
+		pr_err("Wait on sdma failed:%x\n", status);
+		hang();
+	}
+
+	if (!cadence->caps1->has_dma) {
+		writesq(cadence->io.virt, buf, len_in_words);
+
+		if (sdma_size > len) {
+			memcpy(cadence->buf, buf + (len_in_words << 2),
+			       len - (len_in_words << 2));
+			writesl(cadence->io.virt, cadence->buf,
+				sdma_size / 4 - len_in_words);
+		}
+	}
+}
+
+static int cadence_nand_cmd_opcode(struct nand_chip *chip, unsigned int op_id)
+{
+	struct cadence_nand_info *cadence = to_cadence_nand_info(chip->controller);
+	struct cdns_nand_chip *cdns_chip = to_cdns_nand_chip(chip);
+	u64 mini_ctrl_cmd = 0;
+	int ret;
+
+	mini_ctrl_cmd |= GCMD_LAY_TWB;
+	mini_ctrl_cmd |= FIELD_PREP(GCMD_LAY_INSTR, GCMD_LAY_INSTR_CMD);
+	mini_ctrl_cmd |= FIELD_PREP(GCMD_LAY_INPUT_CMD, op_id);
+
+	ret = cadence_nand_generic_cmd_send(cadence,
+					    cdns_chip->cs[chip->cur_cs],
+					    mini_ctrl_cmd);
+
+	if (ret)
+		dev_err(cadence->dev, "send cmd %x failed\n",
+			op_id);
+
+	return ret;
+}
+
+static int cadence_nand_cmd_address(struct nand_chip *chip,
+				    unsigned int naddrs, const u8 *addrs)
+{
+	struct cadence_nand_info *cadence = to_cadence_nand_info(chip->controller);
+	struct cdns_nand_chip *cdns_chip = to_cdns_nand_chip(chip);
+	u64 address = 0;
+	u64 mini_ctrl_cmd = 0;
+	int ret;
+	int i;
+
+	mini_ctrl_cmd |= GCMD_LAY_TWB;
+
+	mini_ctrl_cmd |= FIELD_PREP(GCMD_LAY_INSTR,
+				    GCMD_LAY_INSTR_ADDR);
+
+	for (i = 0; i < naddrs; i++)
+		address |= (u64)addrs[i] << (8 * i);
+
+	mini_ctrl_cmd |= FIELD_PREP(GCMD_LAY_INPUT_ADDR,
+				    address);
+	mini_ctrl_cmd |= FIELD_PREP(GCMD_LAY_INPUT_ADDR_SIZE,
+				    naddrs - 1);
+
+	ret = cadence_nand_generic_cmd_send(cadence,
+					    cdns_chip->cs[chip->cur_cs],
+					    mini_ctrl_cmd);
+
+	if (ret)
+		pr_err("send address %llx failed\n", address);
+
+	return ret;
+}
+
+static int cadence_nand_cmd_data(struct nand_chip *chip,
+				 unsigned int len, u8 mode)
+{
+	struct cadence_nand_info *cadence = to_cadence_nand_info(chip->controller);
+	struct cdns_nand_chip *cdns_chip = to_cdns_nand_chip(chip);
+	u64 mini_ctrl_cmd = 0;
+	int ret;
+
+	mini_ctrl_cmd |= GCMD_LAY_TWB;
+	mini_ctrl_cmd |= FIELD_PREP(GCMD_LAY_INSTR,
+				    GCMD_LAY_INSTR_DATA);
+
+	if (mode)
+		mini_ctrl_cmd |= FIELD_PREP(GCMD_DIR, GCMD_DIR_WRITE);
+
+	mini_ctrl_cmd |= FIELD_PREP(GCMD_SECT_CNT, 1);
+	mini_ctrl_cmd |= FIELD_PREP(GCMD_LAST_SIZE, len);
+
+	ret = cadence_nand_generic_cmd_send(cadence,
+					    cdns_chip->cs[chip->cur_cs],
+					    mini_ctrl_cmd);
+
+	if (ret) {
+		pr_err("send generic data cmd failed\n");
+		return ret;
+	}
+
+	return ret;
+}
+
+static int cadence_nand_waitfunc(struct mtd_info *mtd, struct nand_chip *chip)
+{
+	struct cadence_nand_info *cadence = to_cadence_nand_info(chip->controller);
+	struct cdns_nand_chip *cdns_chip = to_cdns_nand_chip(chip);
+	int status;
+
+	status = cadence_nand_wait_for_value(cadence, RBN_SETINGS,
+					     TIMEOUT_US,
+					     BIT(cdns_chip->cs[chip->cur_cs]),
+					     false);
+	return status;
+}
+
+static int cadence_nand_ooblayout_free(struct mtd_info *mtd, int section,
+				       struct mtd_oob_region *oobregion)
+{
+	struct nand_chip *chip = mtd_to_nand(mtd);
+	struct cdns_nand_chip *cdns_chip = to_cdns_nand_chip(chip);
+
+	if (section)
+		return -ERANGE;
+
+	oobregion->offset = cdns_chip->bbm_len;
+	oobregion->length = cdns_chip->avail_oob_size
+		- cdns_chip->bbm_len;
+
+	return 0;
+}
+
+static int cadence_nand_ooblayout_ecc(struct mtd_info *mtd, int section,
+				      struct mtd_oob_region *oobregion)
+{
+	struct nand_chip *chip = mtd_to_nand(mtd);
+	struct cdns_nand_chip *cdns_chip = to_cdns_nand_chip(chip);
+
+	if (section)
+		return -ERANGE;
+
+	oobregion->offset = cdns_chip->avail_oob_size;
+	oobregion->length = chip->ecc.total;
+
+	return 0;
+}
+
+static const struct mtd_ooblayout_ops cadence_nand_ooblayout_ops = {
+	.rfree = cadence_nand_ooblayout_free,
+	.ecc = cadence_nand_ooblayout_ecc,
+};
+
+static int calc_cycl(u32 timing, u32 clock)
+{
+	if (timing == 0 || clock == 0)
+		return 0;
+
+	if ((timing % clock) > 0)
+		return timing / clock;
+	else
+		return timing / clock - 1;
+}
+
+/* Calculate max data valid window. */
+static inline u32 calc_tdvw_max(u32 trp_cnt, u32 clk_period, u32 trhoh_min,
+				u32 board_delay_skew_min, u32 ext_mode)
+{
+	if (ext_mode == 0)
+		clk_period /= 2;
+
+	return (trp_cnt + 1) * clk_period + trhoh_min +
+		board_delay_skew_min;
+}
+
+/* Calculate data valid window. */
+static inline u32 calc_tdvw(u32 trp_cnt, u32 clk_period, u32 trhoh_min,
+			    u32 trea_max, u32 ext_mode)
+{
+	if (ext_mode == 0)
+		clk_period /= 2;
+
+	return (trp_cnt + 1) * clk_period + trhoh_min - trea_max;
+}
+
+static inline int of_get_child_count(const ofnode node)
+{
+	return fdtdec_get_child_count(gd->fdt_blob, ofnode_to_offset(node));
+}
+
+static int cadence_setup_data_interface(struct mtd_info *mtd, int chipnr,
+					const struct nand_data_interface *conf)
+{
+	struct nand_chip *chip = mtd_to_nand(mtd);
+	struct cadence_nand_info *cadence = to_cadence_nand_info(chip->controller);
+	struct cdns_nand_chip *cdns_chip = to_cdns_nand_chip(mtd_to_nand(mtd));
+	const struct nand_sdr_timings *sdr;
+	struct cadence_nand_timings *t = &cdns_chip->timings;
+	u32 reg;
+	u32 board_delay = cadence->board_delay;
+	u32 clk_period = DIV_ROUND_DOWN_ULL(1000000000000ULL,
+					    cadence->nf_clk_rate);
+	u32 tceh_cnt, tcs_cnt, tadl_cnt, tccs_cnt;
+	u32 tfeat_cnt, trhz_cnt, tvdly_cnt;
+	u32 trhw_cnt, twb_cnt, twh_cnt = 0, twhr_cnt;
+	u32 twp_cnt = 0, trp_cnt = 0, trh_cnt = 0;
+	u32 if_skew = cadence->caps1->if_skew;
+	u32 board_delay_skew_min = board_delay - if_skew;
+	u32 board_delay_skew_max = board_delay + if_skew;
+	u32 dqs_sampl_res, phony_dqs_mod;
+	u32 tdvw, tdvw_min, tdvw_max;
+	u32 ext_rd_mode, ext_wr_mode;
+	u32 dll_phy_dqs_timing = 0, phony_dqs_timing = 0, rd_del_sel = 0;
+	u32 sampling_point;
+
+	sdr = nand_get_sdr_timings(conf);
+	if (IS_ERR(sdr))
+		return PTR_ERR(sdr);
+
+	memset(t, 0, sizeof(*t));
+	/* Sampling point calculation. */
+	if (cadence->caps2.is_phy_type_dll)
+		phony_dqs_mod = 2;
+	else
+		phony_dqs_mod = 1;
+
+	dqs_sampl_res = clk_period / phony_dqs_mod;
+
+	tdvw_min = sdr->tREA_max + board_delay_skew_max;
+	/*
+	 * The idea of those calculation is to get the optimum value
+	 * for tRP and tRH timings. If it is NOT possible to sample data
+	 * with optimal tRP/tRH settings, the parameters will be extended.
+	 * If clk_period is 50ns (the lowest value) this condition is met
+	 * for SDR timing modes 1, 2, 3, 4 and 5.
+	 * If clk_period is 20ns the condition is met only for SDR timing
+	 * mode 5.
+	 */
+	if (sdr->tRC_min <= clk_period &&
+	    sdr->tRP_min <= (clk_period / 2) &&
+	    sdr->tREH_min <= (clk_period / 2)) {
+		/* Performance mode. */
+		ext_rd_mode = 0;
+		tdvw = calc_tdvw(trp_cnt, clk_period, sdr->tRHOH_min,
+				 sdr->tREA_max, ext_rd_mode);
+		tdvw_max = calc_tdvw_max(trp_cnt, clk_period, sdr->tRHOH_min,
+					 board_delay_skew_min,
+					 ext_rd_mode);
+		/*
+		 * Check if data valid window and sampling point can be found
+		 * and is not on the edge (ie. we have hold margin).
+		 * If not extend the tRP timings.
+		 */
+		if (tdvw > 0) {
+			if (tdvw_max <= tdvw_min ||
+			    (tdvw_max % dqs_sampl_res) == 0) {
+				/*
+				 * No valid sampling point so the RE pulse need
+				 * to be widen widening by half clock cycle.
+				 */
+				ext_rd_mode = 1;
+			}
+		} else {
+			/*
+			 * There is no valid window
+			 * to be able to sample data the tRP need to be widen.
+			 * Very safe calculations are performed here.
+			 */
+			trp_cnt = (sdr->tREA_max + board_delay_skew_max
+				   + dqs_sampl_res) / clk_period;
+			ext_rd_mode = 1;
+		}
+
+	} else {
+		/* Extended read mode. */
+		u32 trh;
+
+		ext_rd_mode = 1;
+		trp_cnt = calc_cycl(sdr->tRP_min, clk_period);
+		trh = sdr->tRC_min - ((trp_cnt + 1) * clk_period);
+		if (sdr->tREH_min >= trh)
+			trh_cnt = calc_cycl(sdr->tREH_min, clk_period);
+		else
+			trh_cnt = calc_cycl(trh, clk_period);
+
+		tdvw = calc_tdvw(trp_cnt, clk_period, sdr->tRHOH_min,
+				 sdr->tREA_max, ext_rd_mode);
+		/*
+		 * Check if data valid window and sampling point can be found
+		 * or if it is at the edge check if previous is valid
+		 * - if not extend the tRP timings.
+		 */
+		if (tdvw > 0) {
+			tdvw_max = calc_tdvw_max(trp_cnt, clk_period,
+						 sdr->tRHOH_min,
+						 board_delay_skew_min,
+						 ext_rd_mode);
+
+			if ((((tdvw_max / dqs_sampl_res)
+			      * dqs_sampl_res) <= tdvw_min) ||
+			    (((tdvw_max % dqs_sampl_res) == 0) &&
+			     (((tdvw_max / dqs_sampl_res - 1)
+			       * dqs_sampl_res) <= tdvw_min))) {
+				/*
+				 * Data valid window width is lower than
+				 * sampling resolution and do not hit any
+				 * sampling point to be sure the sampling point
+				 * will be found the RE low pulse width will be
+				 *  extended by one clock cycle.
+				 */
+				trp_cnt = trp_cnt + 1;
+			}
+		} else {
+			/*
+			 * There is no valid window to be able to sample data.
+			 * The tRP need to be widen.
+			 * Very safe calculations are performed here.
+			 */
+			trp_cnt = (sdr->tREA_max + board_delay_skew_max
+				   + dqs_sampl_res) / clk_period;
+		}
+	}
+
+	tdvw_max = calc_tdvw_max(trp_cnt, clk_period,
+				 sdr->tRHOH_min,
+				 board_delay_skew_min, ext_rd_mode);
+
+	if (sdr->tWC_min <= clk_period &&
+	    (sdr->tWP_min + if_skew) <= (clk_period / 2) &&
+	    (sdr->tWH_min + if_skew) <= (clk_period / 2)) {
+		ext_wr_mode = 0;
+	} else {
+		u32 twh;
+
+		ext_wr_mode = 1;
+		twp_cnt = calc_cycl(sdr->tWP_min + if_skew, clk_period);
+		if ((twp_cnt + 1) * clk_period < (sdr->tALS_min + if_skew))
+			twp_cnt = calc_cycl(sdr->tALS_min + if_skew,
+					    clk_period);
+
+		twh = (sdr->tWC_min - (twp_cnt + 1) * clk_period);
+		if (sdr->tWH_min >= twh)
+			twh = sdr->tWH_min;
+
+		twh_cnt = calc_cycl(twh + if_skew, clk_period);
+	}
+
+	reg = FIELD_PREP(ASYNC_TOGGLE_TIMINGS_TRH, trh_cnt);
+	reg |= FIELD_PREP(ASYNC_TOGGLE_TIMINGS_TRP, trp_cnt);
+	reg |= FIELD_PREP(ASYNC_TOGGLE_TIMINGS_TWH, twh_cnt);
+	reg |= FIELD_PREP(ASYNC_TOGGLE_TIMINGS_TWP, twp_cnt);
+	t->async_toggle_timings = reg;
+	dev_dbg(cadence->dev, "ASYNC_TOGGLE_TIMINGS_SDR\t%x\n", reg);
+
+	tadl_cnt = calc_cycl((sdr->tADL_min + if_skew), clk_period);
+	tccs_cnt = calc_cycl((sdr->tCCS_min + if_skew), clk_period);
+	twhr_cnt = calc_cycl((sdr->tWHR_min + if_skew), clk_period);
+	trhw_cnt = calc_cycl((sdr->tRHW_min + if_skew), clk_period);
+	reg = FIELD_PREP(TIMINGS0_TADL, tadl_cnt);
+
+	/*
+	 * If timing exceeds delay field in timing register
+	 * then use maximum value.
+	 */
+	if (FIELD_FIT(TIMINGS0_TCCS, tccs_cnt))
+		reg |= FIELD_PREP(TIMINGS0_TCCS, tccs_cnt);
+	else
+		reg |= TIMINGS0_TCCS;
+
+	reg |= FIELD_PREP(TIMINGS0_TWHR, twhr_cnt);
+	reg |= FIELD_PREP(TIMINGS0_TRHW, trhw_cnt);
+	t->timings0 = reg;
+	dev_dbg(cadence->dev, "TIMINGS0_SDR\t%x\n", reg);
+
+	/* The following is related to single signal so skew is not needed. */
+	trhz_cnt = calc_cycl(sdr->tRHZ_max, clk_period);
+	trhz_cnt = trhz_cnt + 1;
+	twb_cnt = calc_cycl((sdr->tWB_max + board_delay), clk_period);
+	/*
+	 * Because of the two stage syncflop the value must be increased by 3
+	 * first value is related with sync, second value is related
+	 * with output if delay.
+	 */
+	twb_cnt = twb_cnt + 3 + 5;
+	/*
+	 * The following is related to the we edge of the random data input
+	 * sequence so skew is not needed.
+	 */
+	tvdly_cnt = calc_cycl(500000 + if_skew, clk_period);
+	reg = FIELD_PREP(TIMINGS1_TRHZ, trhz_cnt);
+	reg |= FIELD_PREP(TIMINGS1_TWB, twb_cnt);
+	reg |= FIELD_PREP(TIMINGS1_TVDLY, tvdly_cnt);
+	t->timings1 = reg;
+	dev_dbg(cadence->dev, "TIMINGS1_SDR\t%x\n", reg);
+
+	tfeat_cnt = calc_cycl(sdr->tFEAT_max, clk_period);
+	if (tfeat_cnt < twb_cnt)
+		tfeat_cnt = twb_cnt;
+
+	tceh_cnt = calc_cycl(sdr->tCEH_min, clk_period);
+	tcs_cnt = calc_cycl((sdr->tCS_min + if_skew), clk_period);
+
+	reg = FIELD_PREP(TIMINGS2_TFEAT, tfeat_cnt);
+	reg |= FIELD_PREP(TIMINGS2_CS_HOLD_TIME, tceh_cnt);
+	reg |= FIELD_PREP(TIMINGS2_CS_SETUP_TIME, tcs_cnt);
+	t->timings2 = reg;
+	dev_dbg(cadence->dev, "TIMINGS2_SDR\t%x\n", reg);
+
+	if (cadence->caps2.is_phy_type_dll) {
+		reg = DLL_PHY_CTRL_DLL_RST_N;
+		if (ext_wr_mode)
+			reg |= DLL_PHY_CTRL_EXTENDED_WR_MODE;
+		if (ext_rd_mode)
+			reg |= DLL_PHY_CTRL_EXTENDED_RD_MODE;
+
+		reg |= FIELD_PREP(DLL_PHY_CTRL_RS_HIGH_WAIT_CNT, 7);
+		reg |= FIELD_PREP(DLL_PHY_CTRL_RS_IDLE_CNT, 7);
+		t->dll_phy_ctrl = reg;
+		dev_dbg(cadence->dev, "DLL_PHY_CTRL_SDR\t%x\n", reg);
+	}
+
+	/* Sampling point calculation. */
+	if ((tdvw_max % dqs_sampl_res) > 0)
+		sampling_point = tdvw_max / dqs_sampl_res;
+	else
+		sampling_point = (tdvw_max / dqs_sampl_res - 1);
+
+	if (sampling_point * dqs_sampl_res > tdvw_min) {
+		dll_phy_dqs_timing =
+			FIELD_PREP(PHY_DQS_TIMING_DQS_SEL_OE_END, 4);
+		dll_phy_dqs_timing |= PHY_DQS_TIMING_USE_PHONY_DQS;
+		phony_dqs_timing = sampling_point / phony_dqs_mod;
+
+		if ((sampling_point % 2) > 0) {
+			dll_phy_dqs_timing |= PHY_DQS_TIMING_PHONY_DQS_SEL;
+			if ((tdvw_max % dqs_sampl_res) == 0)
+				/*
+				 * Calculation for sampling point at the edge
+				 * of data and being odd number.
+				 */
+				phony_dqs_timing = (tdvw_max / dqs_sampl_res)
+					/ phony_dqs_mod - 1;
+
+			if (!cadence->caps2.is_phy_type_dll)
+				phony_dqs_timing--;
+
+		} else {
+			phony_dqs_timing--;
+		}
+		rd_del_sel = phony_dqs_timing + 3;
+	} else {
+		dev_warn(cadence->dev,
+			 "ERROR : cannot find valid sampling point\n");
+	}
+
+	reg = FIELD_PREP(PHY_CTRL_PHONY_DQS, phony_dqs_timing);
+	if (cadence->caps2.is_phy_type_dll)
+		reg  |= PHY_CTRL_SDR_DQS;
+	t->phy_ctrl = reg;
+	dev_dbg(cadence->dev, "PHY_CTRL_REG_SDR\t%x\n", reg);
+
+	if (cadence->caps2.is_phy_type_dll) {
+		dev_dbg(cadence->dev, "PHY_TSEL_REG_SDR\t%x\n", 0);
+		dev_dbg(cadence->dev, "PHY_DQ_TIMING_REG_SDR\t%x\n", 2);
+		dev_dbg(cadence->dev, "PHY_DQS_TIMING_REG_SDR\t%x\n",
+			dll_phy_dqs_timing);
+		t->phy_dqs_timing = dll_phy_dqs_timing;
+
+		reg = FIELD_PREP(PHY_GATE_LPBK_CTRL_RDS, rd_del_sel);
+		dev_dbg(cadence->dev, "PHY_GATE_LPBK_CTRL_REG_SDR\t%x\n",
+			reg);
+		t->phy_gate_lpbk_ctrl = reg;
+
+		dev_dbg(cadence->dev, "PHY_DLL_MASTER_CTRL_REG_SDR\t%lx\n",
+			PHY_DLL_MASTER_CTRL_BYPASS_MODE);
+		dev_dbg(cadence->dev, "PHY_DLL_SLAVE_CTRL_REG_SDR\t%x\n", 0);
+	}
+	return 0;
+}
+
+static int cadence_nand_attach_chip(struct nand_chip *chip)
+{
+	struct cadence_nand_info *cadence = to_cadence_nand_info(chip->controller);
+	struct cdns_nand_chip *cdns_chip = to_cdns_nand_chip(chip);
+	static struct nand_ecclayout nand_oob;
+	u32 ecc_size;
+	struct mtd_info *mtd = nand_to_mtd(chip);
+	int ret;
+
+	if (chip->options & NAND_BUSWIDTH_16) {
+		ret = cadence_nand_set_access_width16(cadence, true);
+		if (ret)
+			return ret;
+	}
+
+	chip->options |= NAND_USE_BOUNCE_BUFFER;
+	chip->bbt_options |= NAND_BBT_USE_FLASH;
+	chip->bbt_options |= NAND_BBT_NO_OOB;
+	chip->ecc.mode = NAND_ECC_HW_SYNDROME;
+
+	chip->options |= NAND_NO_SUBPAGE_WRITE;
+
+	cdns_chip->bbm_offs = chip->badblockpos;
+	cdns_chip->bbm_offs &= ~0x01;
+	/* this value should be even number */
+	cdns_chip->bbm_len = 2;
+
+	ret = cadence_ecc_setup(mtd, chip, mtd->oobsize - cdns_chip->bbm_len);
+	if (ret) {
+		dev_err(cadence->dev, "ECC configuration failed\n");
+		return ret;
+	}
+
+	dev_dbg(cadence->dev,
+		"chosen ECC settings: step=%d, strength=%d, bytes=%d\n",
+		chip->ecc.size, chip->ecc.strength, chip->ecc.bytes);
+
+	/* Error correction configuration. */
+	cdns_chip->sector_size = chip->ecc.size;
+	cdns_chip->sector_count = mtd->writesize / cdns_chip->sector_size;
+	ecc_size = cdns_chip->sector_count * chip->ecc.bytes;
+
+	cdns_chip->avail_oob_size = mtd->oobsize - ecc_size;
+
+	if (cdns_chip->avail_oob_size > cadence->bch_metadata_size)
+		cdns_chip->avail_oob_size = cadence->bch_metadata_size;
+
+	if ((cdns_chip->avail_oob_size + cdns_chip->bbm_len + ecc_size)
+	    > mtd->oobsize)
+		cdns_chip->avail_oob_size -= 4;
+
+	ret = cadence_nand_get_ecc_strength_idx(cadence, chip->ecc.strength);
+	if (ret < 0)
+		return -EINVAL;
+
+	cdns_chip->corr_str_idx = (u8)ret;
+
+	if (cadence_nand_wait_for_value(cadence, CTRL_STATUS,
+					TIMEOUT_US,
+					CTRL_STATUS_CTRL_BUSY, true))
+		return -ETIMEDOUT;
+
+	cadence_nand_set_ecc_strength(cadence,
+				      cdns_chip->corr_str_idx);
+
+	cadence_nand_set_erase_detection(cadence, true,
+					 chip->ecc.strength);
+
+	dev_dbg(cadence->dev,
+		"chosen ECC settings: step=%d, strength=%d, bytes=%d\n",
+		chip->ecc.size, chip->ecc.strength, chip->ecc.bytes);
+
+	/* Override the default read operations. */
+	chip->ecc.options |= NAND_ECC_CUSTOM_PAGE_ACCESS;
+	chip->ecc.read_page = cadence_nand_read_page;
+	chip->ecc.read_page_raw = cadence_nand_read_page_raw;
+	chip->ecc.write_page = cadence_nand_write_page;
+	chip->ecc.write_page_raw = cadence_nand_write_page_raw;
+	chip->ecc.read_oob = cadence_nand_read_oob;
+	chip->ecc.write_oob = cadence_nand_write_oob;
+	chip->ecc.read_oob_raw = cadence_nand_read_oob_raw;
+	chip->ecc.write_oob_raw = cadence_nand_write_oob_raw;
+	chip->erase = cadence_nand_erase;
+
+	if ((mtd->writesize + mtd->oobsize) > cadence->buf_size)
+		cadence->buf_size = mtd->writesize + mtd->oobsize;
+
+	mtd_set_ooblayout(mtd, &cadence_nand_ooblayout_ops);
+
+	nand_oob.eccbytes = cdns_chip->chip.ecc.bytes;
+	cdns_chip->chip.ecc.layout = &nand_oob;
+
+	return 0;
+}
+
+/* Dummy implementation: we don't support multiple chips */
+static void cadence_nand_select_chip(struct mtd_info *mtd, int chipnr)
+{
+	switch (chipnr) {
+	case -1:
+	case 0:
+		break;
+
+	default:
+		WARN_ON(chipnr);
+	}
+}
+
+static int cadence_nand_status(struct mtd_info *mtd, unsigned int command)
+{
+	struct nand_chip *chip = mtd_to_nand(mtd);
+	int ret = 0;
+
+	ret = cadence_nand_cmd_opcode(chip, command);
+	if (ret)
+		return ret;
+
+	ret = cadence_nand_cmd_data(chip, 1, GCMD_DIR_READ);
+	if (ret)
+		return ret;
+
+	return 0;
+}
+
+static int cadence_nand_readid(struct mtd_info *mtd, int offset_in_page, unsigned int command)
+{
+	struct nand_chip *chip = mtd_to_nand(mtd);
+	u8 addrs = (u8)offset_in_page;
+	int ret = 0;
+
+	ret = cadence_nand_cmd_opcode(chip, command);
+	if (ret)
+		return ret;
+
+	ret = cadence_nand_cmd_address(chip, ONE_CYCLE, &addrs);
+	if (ret)
+		return ret;
+
+	ret = cadence_nand_cmd_data(chip, 8, GCMD_DIR_READ);
+	if (ret)
+		return ret;
+
+	return 0;
+}
+
+static int cadence_nand_param(struct mtd_info *mtd, u8 offset_in_page, unsigned int command)
+{
+	struct nand_chip *chip = mtd_to_nand(mtd);
+	int ret = 0;
+
+	ret = cadence_nand_cmd_opcode(chip, command);
+	if (ret)
+		return ret;
+
+	ret = cadence_nand_cmd_address(chip, ONE_CYCLE, &offset_in_page);
+	if (ret)
+		return ret;
+
+	ret = cadence_nand_waitfunc(mtd, chip);
+	if (ret)
+		return ret;
+
+	ret = cadence_nand_cmd_data(chip, sizeof(struct nand_jedec_params), GCMD_DIR_READ);
+	if (ret)
+		return ret;
+
+	return 0;
+}
+
+static int cadence_nand_reset(struct mtd_info *mtd, unsigned int command)
+{
+	struct nand_chip *chip = mtd_to_nand(mtd);
+	int ret = 0;
+
+	ret = cadence_nand_cmd_opcode(chip, command);
+	if (ret)
+		return ret;
+
+	ret = cadence_nand_waitfunc(mtd, chip);
+	if (ret)
+		return ret;
+
+	return 0;
+}
+
+static int cadence_nand_features(struct mtd_info *mtd, u8 offset_in_page, u32 command)
+{
+	struct nand_chip *chip = mtd_to_nand(mtd);
+	int ret = 0;
+
+	ret = cadence_nand_cmd_opcode(chip, command);
+	if (ret)
+		return ret;
+
+	ret = cadence_nand_cmd_address(chip, ONE_CYCLE, &offset_in_page);
+	if (ret)
+		return ret;
+
+	if (command == NAND_CMD_GET_FEATURES)
+		ret = cadence_nand_cmd_data(chip, ONFI_SUBFEATURE_PARAM_LEN,
+					    GCMD_DIR_READ);
+	else
+		ret = cadence_nand_cmd_data(chip, ONFI_SUBFEATURE_PARAM_LEN,
+					    GCMD_DIR_WRITE);
+
+	return ret;
+}
+
+static void cadence_nand_cmdfunc(struct mtd_info *mtd, unsigned int command,
+				 int offset_in_page, int page)
+{
+	struct nand_chip *chip = mtd_to_nand(mtd);
+	struct cadence_nand_info *cadence = to_cadence_nand_info(chip->controller);
+	int ret = 0;
+
+	cadence->cmd = command;
+	switch (command) {
+	case NAND_CMD_STATUS:
+		ret = cadence_nand_status(mtd, command);
+		break;
+
+	case NAND_CMD_READID:
+		ret = cadence_nand_readid(mtd, offset_in_page, command);
+		break;
+
+	case NAND_CMD_PARAM:
+		ret = cadence_nand_param(mtd, offset_in_page, command);
+		break;
+
+	case NAND_CMD_RESET:
+		ret = cadence_nand_reset(mtd, command);
+		break;
+
+	case NAND_CMD_SET_FEATURES:
+	case NAND_CMD_GET_FEATURES:
+		ret = cadence_nand_features(mtd, offset_in_page, command);
+		break;
+	/*
+	 * ecc will override other command for read, write and erase
+	 */
+	default:
+		break;
+	}
+
+	if (cadence->cmd == NAND_CMD_RESET) {
+		ret = cadence_nand_select_target(chip);
+		if (ret)
+			dev_err(cadence->dev, "Chip select failure after reset\n");
+	}
+
+	if (ret != 0)
+		printf("ERROR:%s:command:0x%x\n", __func__, cadence->cmd);
+}
+
+static int cadence_nand_dev_ready(struct mtd_info *mtd)
+{
+	struct nand_chip *chip = mtd_to_nand(mtd);
+	struct cadence_nand_info *cadence = to_cadence_nand_info(chip->controller);
+
+	if (cadence_nand_wait_for_value(cadence, CTRL_STATUS,
+					TIMEOUT_US,
+					CTRL_STATUS_CTRL_BUSY, true))
+		return -ETIMEDOUT;
+
+	return 0;
+}
+
+static u8 cadence_nand_read_byte(struct mtd_info *mtd)
+{
+	struct nand_chip *chip = mtd_to_nand(mtd);
+	struct cadence_nand_info *cadence = to_cadence_nand_info(chip->controller);
+	u32 size = 1;
+	u8 val;
+
+	if (cadence->buf_index == 0) {
+		if (cadence->cmd == NAND_CMD_READID)
+			size = 8;
+		else if (cadence->cmd == NAND_CMD_PARAM)
+			size = sizeof(struct nand_jedec_params);
+		else if (cadence->cmd == NAND_CMD_GET_FEATURES)
+			size = ONFI_SUBFEATURE_PARAM_LEN;
+
+		cadence_nand_read_buf(mtd, &cadence->buf[0], size);
+	}
+
+	val = *(&cadence->buf[0] + cadence->buf_index);
+	cadence->buf_index++;
+
+	return val;
+}
+
+static void cadence_nand_write_byte(struct mtd_info *mtd, u8 byte)
+{
+	cadence_nand_write_buf(mtd, &byte, 1);
+}
+
+static int cadence_nand_chip_init(struct cadence_nand_info *cadence, ofnode node)
+{
+	struct cdns_nand_chip *cdns_chip;
+	struct nand_chip *chip;
+	struct mtd_info *mtd;
+	int ret, i;
+	int nsels;
+	u32 cs;
+
+	if (!ofnode_get_property(node, "reg", &nsels))
+		return -ENODEV;
+
+	nsels /= sizeof(u32);
+	if (nsels <= 0) {
+		dev_err(cadence->dev, "invalid reg property size %d\n", nsels);
+		return -EINVAL;
+	}
+
+	cdns_chip = devm_kzalloc(cadence->dev, sizeof(*cdns_chip) +
+				 (nsels * sizeof(u8)), GFP_KERNEL);
+	if (!cdns_chip)
+		return -ENODEV;
+
+	cdns_chip->nsels = nsels;
+	for (i = 0; i < nsels; i++) {
+		/* Retrieve CS id. */
+		ret = ofnode_read_u32_index(node, "reg", i, &cs);
+		if (ret) {
+			dev_err(cadence->dev,
+				"could not retrieve reg property: %d\n",
+				ret);
+			goto free_buf;
+		}
+
+		if (cs >= cadence->caps2.max_banks) {
+			dev_err(cadence->dev,
+				"invalid reg value: %u (max CS = %d)\n",
+				cs, cadence->caps2.max_banks);
+			ret = -EINVAL;
+			goto free_buf;
+		}
+
+		if (test_and_set_bit(cs, &cadence->assigned_cs)) {
+			dev_err(cadence->dev,
+				"CS %d already assigned\n", cs);
+			ret = -EINVAL;
+			goto free_buf;
+		}
+
+		cdns_chip->cs[i] = cs;
+	}
+
+	chip = &cdns_chip->chip;
+	chip->controller = &cadence->controller;
+	nand_set_flash_node(chip, node);
+	mtd = nand_to_mtd(chip);
+	mtd->dev->parent = cadence->dev;
+
+	chip->options |= NAND_BUSWIDTH_AUTO;
+	chip->select_chip = cadence_nand_select_chip;
+	chip->cmdfunc = cadence_nand_cmdfunc;
+	chip->dev_ready = cadence_nand_dev_ready;
+	chip->read_byte = cadence_nand_read_byte;
+	chip->write_byte = cadence_nand_write_byte;
+	chip->waitfunc = cadence_nand_waitfunc;
+	chip->read_buf = cadence_nand_read_buf;
+	chip->write_buf = cadence_nand_write_buf;
+	chip->setup_data_interface = cadence_setup_data_interface;
+
+	ret = nand_scan_ident(mtd, 1, NULL);
+	if (ret) {
+		dev_err(cadence->dev, "Chip identification failure\n");
+		goto free_buf;
+	}
+
+	ret = cadence_nand_attach_chip(chip);
+	if (ret) {
+		dev_err(cadence->dev, "Chip not able to attached\n");
+		goto free_buf;
+	}
+
+	ret = nand_scan_tail(mtd);
+	if (ret) {
+		dev_err(cadence->dev, "could not scan the nand chip\n");
+		goto free_buf;
+	}
+
+	ret = nand_register(0, mtd);
+	if (ret) {
+		dev_err(cadence->dev, "Failed to register MTD: %d\n", ret);
+		goto free_buf;
+	}
+
+	return 0;
+
+free_buf:
+	devm_kfree(cadence->dev, cdns_chip);
+	return ret;
+}
+
+static int cadence_nand_chips_init(struct cadence_nand_info *cadence)
+{
+	struct udevice *dev = cadence->dev;
+	ofnode node = dev_ofnode(dev);
+	ofnode nand_node;
+	int max_cs = cadence->caps2.max_banks;
+	int nchips, ret;
+
+	nchips = of_get_child_count(node);
+
+	if (nchips > max_cs) {
+		dev_err(cadence->dev,
+			"too many NAND chips: %d (max = %d CS)\n",
+			nchips, max_cs);
+		return -EINVAL;
+	}
+
+	ofnode_for_each_subnode(nand_node, node) {
+		ret = cadence_nand_chip_init(cadence, nand_node);
+		if (ret)
+			return ret;
+	}
+
+	return 0;
+}
+
+static int cadence_nand_init(struct cadence_nand_info *cadence)
+{
+	int ret;
+
+	cadence->cdma_desc = dma_alloc_coherent(sizeof(*cadence->cdma_desc),
+						(unsigned long *)&cadence->dma_cdma_desc);
+	if (!cadence->cdma_desc)
+		return -ENOMEM;
+
+	cadence->buf_size = SZ_16K;
+	cadence->buf = kmalloc(cadence->buf_size, GFP_KERNEL);
+	if (!cadence->buf) {
+		ret = -ENOMEM;
+		goto free_buf_desc;
+	}
+
+	//Hardware initialization
+	ret = cadence_nand_hw_init(cadence);
+	if (ret)
+		goto free_buf;
+
+	cadence->curr_corr_str_idx = 0xFF;
+
+	ret = cadence_nand_chips_init(cadence);
+	if (ret) {
+		dev_err(cadence->dev, "Failed to register MTD: %d\n",
+			ret);
+		goto free_buf;
+	}
+
+	kfree(cadence->buf);
+	cadence->buf = kzalloc(cadence->buf_size, GFP_KERNEL);
+	if (!cadence->buf) {
+		ret = -ENOMEM;
+		goto free_buf_desc;
+	}
+
+	return 0;
+
+free_buf:
+	kfree(cadence->buf);
+
+free_buf_desc:
+	dma_free_coherent(cadence->cdma_desc);
+
+	return ret;
+}
+
+static const struct cadence_nand_dt_devdata cadence_nand_default = {
+	.if_skew = 0,
+	.has_dma = 0,
+};
+
+static const struct udevice_id cadence_nand_dt_ids[] = {
+	{
+		.compatible = "cdns,nand",
+		.data = (unsigned long)&cadence_nand_default
+	}, {}
+};
+
+static int cadence_nand_dt_probe(struct udevice *dev)
+{
+	struct cadence_nand_info *cadence = dev_get_priv(dev);
+	const struct udevice_id *of_id;
+	const struct cadence_nand_dt_devdata *devdata;
+	struct resource res;
+	int ret;
+	u32 val;
+
+	if (!dev) {
+		dev_warn(dev, "Device ptr null\n");
+		return -EINVAL;
+	}
+
+	of_id = &cadence_nand_dt_ids[0];
+	devdata = (struct cadence_nand_dt_devdata *)of_id->data;
+
+	cadence->caps1 = devdata;
+	cadence->dev = dev;
+
+	ret = clk_get_by_index(dev, 0, &cadence->clk);
+	if (ret)
+		return ret;
+
+	ret = clk_enable(&cadence->clk);
+	if (ret && ret != -ENOSYS && ret != -ENOMEM) {
+		dev_err(dev, "failed to enable clock\n");
+		return ret;
+	}
+	cadence->nf_clk_rate = clk_get_rate(&cadence->clk);
+
+	ret = reset_get_by_index(dev, 1, &cadence->softphy_reset);
+	if (ret) {
+		if (ret != -ENOMEM)
+			dev_warn(dev, "Can't get softphy_reset: %d\n", ret);
+	} else {
+		reset_deassert(&cadence->softphy_reset);
+	}
+
+	ret = reset_get_by_index(dev, 0, &cadence->nand_reset);
+	if (ret) {
+		if (ret != -ENOMEM)
+			dev_warn(dev, "Can't get nand_reset: %d\n", ret);
+	} else {
+		reset_deassert(&cadence->nand_reset);
+	}
+
+	ret = dev_read_resource_byname(dev, "reg", &res);
+	if (ret)
+		return ret;
+	cadence->reg = devm_ioremap(dev, res.start, resource_size(&res));
+
+	ret = dev_read_resource_byname(dev, "sdma", &res);
+	if (ret)
+		return ret;
+	cadence->io.dma = res.start;
+	cadence->io.virt = devm_ioremap(dev, res.start, resource_size(&res));
+
+	ret = ofnode_read_u32(dev_ofnode(dev->parent),
+			      "cdns,board-delay-ps", &val);
+	if (ret) {
+		val = 4830;
+		dev_info(cadence->dev,
+			 "missing cdns,board-delay-ps property, %d was set\n",
+			 val);
+	}
+	cadence->board_delay = val;
+
+	ret = cadence_nand_init(cadence);
+	if (ret)
+		return ret;
+
+	return 0;
+}
+
+U_BOOT_DRIVER(cadence_nand_dt) = {
+	.name = "cadence-nand-dt",
+	.id = UCLASS_MTD,
+	.of_match = cadence_nand_dt_ids,
+	.probe = cadence_nand_dt_probe,
+	.priv_auto = sizeof(struct cadence_nand_info),
+};
+
+void board_nand_init(void)
+{
+	struct udevice *dev;
+	int ret;
+
+	ret = uclass_get_device_by_driver(UCLASS_MTD,
+					  DM_DRIVER_GET(cadence_nand_dt),
+					  &dev);
+	if (ret && ret != -ENODEV)
+		pr_err("Failed to initialize Cadence NAND controller. (error %d)\n",
+		       ret);
+}
diff --git a/drivers/mtd/nand/raw/cadence_spl.c b/drivers/mtd/nand/raw/cadence_spl.c
new file mode 100644
index 00000000000..17058e49faa
--- /dev/null
+++ b/drivers/mtd/nand/raw/cadence_spl.c
@@ -0,0 +1,59 @@
+// SPDX-License-Identifier:     GPL-2.0
+/*
+ * Copyright (C) 2024 Intel Corporation <www.intel.com>
+ */
+
+#include <cadence-nand.h>
+#include <dm.h>
+#include <hang.h>
+#include <nand.h>
+#include <system-constants.h>
+
+/* Unselect after operation */
+void nand_deselect(void)
+{
+	struct mtd_info *mtd;
+	struct nand_chip *chip;
+
+	mtd = get_nand_dev_by_index(nand_curr_device);
+	if (!mtd)
+		hang();
+	chip = mtd_to_nand(mtd);
+
+	if (chip->select_chip)
+		chip->select_chip(mtd, -1);
+}
+
+static int nand_is_bad_block(int block)
+{
+	struct mtd_info *mtd;
+	struct nand_chip *chip;
+	loff_t ofs = block * CONFIG_SYS_NAND_BLOCK_SIZE;
+
+	mtd = get_nand_dev_by_index(nand_curr_device);
+	if (!mtd)
+		hang();
+	chip = mtd_to_nand(mtd);
+
+	return chip->block_bad(mtd, ofs);
+}
+
+static int nand_read_page(int block, int page, uchar *dst)
+{
+	struct mtd_info *mtd;
+	int page_addr = block * SYS_NAND_BLOCK_PAGES + page;
+	loff_t ofs = page_addr * CONFIG_SYS_NAND_PAGE_SIZE;
+	int ret;
+	size_t len = CONFIG_SYS_NAND_PAGE_SIZE;
+
+	mtd = get_nand_dev_by_index(nand_curr_device);
+	if (!mtd)
+		hang();
+
+	ret = nand_read(mtd, ofs, &len, dst);
+	if (ret)
+		printf("nand_read failed %d\n", ret);
+
+	return ret;
+}
+#include "nand_spl_loaders.c"
diff --git a/drivers/mtd/nand/raw/meson_nand.c b/drivers/mtd/nand/raw/meson_nand.c
index 28c851f103b..7e683f49c5e 100644
--- a/drivers/mtd/nand/raw/meson_nand.c
+++ b/drivers/mtd/nand/raw/meson_nand.c
@@ -618,9 +618,7 @@ static int meson_nfc_write_page_hwecc(struct mtd_info *mtd, struct nand_chip *ch
 		memcpy(meson_chip->data_buf, buf, mtd->writesize);
 
 	memset(meson_chip->info_buf, 0, chip->ecc.steps * PER_INFO_BYTE);
-
-	if (oob_required)
-		meson_nfc_set_user_byte(chip, chip->oob_poi);
+	meson_nfc_set_user_byte(chip, chip->oob_poi);
 
 	return meson_nfc_write_page_sub(chip, page, false);
 }
diff --git a/drivers/mtd/nand/raw/nand_base.c b/drivers/mtd/nand/raw/nand_base.c
index 1b65c6f6443..bb5460e0068 100644
--- a/drivers/mtd/nand/raw/nand_base.c
+++ b/drivers/mtd/nand/raw/nand_base.c
@@ -306,6 +306,35 @@ void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len)
 	ioread16_rep(chip->IO_ADDR_R, p, len >> 1);
 }
 
+/*
+ * nand_bbm_get_next_page - Get the next page for bad block markers
+ * @chip: The NAND chip
+ * @page: First page to start checking for bad block marker usage
+ *
+ * Returns an integer that corresponds to the page offset within a block, for
+ * a page that is used to store bad block markers. If no more pages are
+ * available, -EINVAL is returned.
+ */
+int nand_bbm_get_next_page(struct nand_chip *chip, int page)
+{
+	struct mtd_info *mtd = nand_to_mtd(chip);
+	int last_page = ((mtd->erasesize - mtd->writesize) >>
+			 chip->page_shift) & chip->pagemask;
+	unsigned int bbm_flags = NAND_BBM_FIRSTPAGE | NAND_BBM_SECONDPAGE
+		| NAND_BBM_LASTPAGE;
+
+	if (page == 0 && !(chip->options & bbm_flags))
+		return 0;
+	if (page == 0 && chip->options & NAND_BBM_FIRSTPAGE)
+		return 0;
+	if (page <= 1 && chip->options & NAND_BBM_SECONDPAGE)
+		return 1;
+	if (page <= last_page && chip->options & NAND_BBM_LASTPAGE)
+		return last_page;
+
+	return -EINVAL;
+}
+
 /**
  * nand_block_bad - [DEFAULT] Read bad block marker from the chip
  * @mtd: MTD device structure
@@ -315,40 +344,32 @@ void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len)
  */
 static int nand_block_bad(struct mtd_info *mtd, loff_t ofs)
 {
-	int page, res = 0, i = 0;
 	struct nand_chip *chip = mtd_to_nand(mtd);
-	u16 bad;
+	int first_page, page_offset;
+	int res;
+	u8 bad;
 
-	if (chip->bbt_options & NAND_BBT_SCANLASTPAGE)
-		ofs += mtd->erasesize - mtd->writesize;
+	first_page = (int)(ofs >> chip->page_shift) & chip->pagemask;
+	page_offset = nand_bbm_get_next_page(chip, 0);
 
-	page = (int)(ofs >> chip->page_shift) & chip->pagemask;
+	while (page_offset >= 0) {
+		res = chip->ecc.read_oob(mtd, chip, first_page + page_offset);
+		if (res < 0)
+			return res;
 
-	do {
-		if (chip->options & NAND_BUSWIDTH_16) {
-			chip->cmdfunc(mtd, NAND_CMD_READOOB,
-					chip->badblockpos & 0xFE, page);
-			bad = cpu_to_le16(chip->read_word(mtd));
-			if (chip->badblockpos & 0x1)
-				bad >>= 8;
-			else
-				bad &= 0xFF;
-		} else {
-			chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos,
-					page);
-			bad = chip->read_byte(mtd);
-		}
+		bad = chip->oob_poi[chip->badblockpos];
 
 		if (likely(chip->badblockbits == 8))
 			res = bad != 0xFF;
 		else
 			res = hweight8(bad) < chip->badblockbits;
-		ofs += mtd->writesize;
-		page = (int)(ofs >> chip->page_shift) & chip->pagemask;
-		i++;
-	} while (!res && i < 2 && (chip->bbt_options & NAND_BBT_SCAN2NDPAGE));
+		if (res)
+			return res;
 
-	return res;
+		page_offset = nand_bbm_get_next_page(chip, page_offset + 1);
+	}
+
+	return 0;
 }
 
 /**
diff --git a/drivers/mux/Kconfig b/drivers/mux/Kconfig
index f15ee4f833f..2b95eb02177 100644
--- a/drivers/mux/Kconfig
+++ b/drivers/mux/Kconfig
@@ -10,6 +10,16 @@ config MULTIPLEXER
 
 if MULTIPLEXER
 
+config SPL_MUX_MMIO
+	bool "MMIO register bitfield-controlled Multiplexer"
+        depends on MULTIPLEXER && SYSCON
+        help
+          MMIO register bitfield-controlled Multiplexer controller.
+
+          The driver builds multiplexer controllers for bitfields in a syscon
+          register. For N bit wide bitfields, there will be 2^N possible
+          multiplexer states.
+
 config MUX_MMIO
 	bool "MMIO register bitfield-controlled Multiplexer"
 	depends on MULTIPLEXER && SYSCON
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index 1563404ca17..3db784faedd 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -237,6 +237,13 @@ config DWC_ETH_QOS
 	  Of Service) IP block. The IP supports many options for bus type,
 	  clocking/reset structure, and feature list.
 
+config DWC_ETH_QOS_ADI
+	bool "Synopsys DWC Ethernet QOS device support for ADI SC59x-64 parts"
+	depends on DWC_ETH_QOS
+	help
+		The Synopsis Designware Ethernet QoS IP block with the specific
+		configuration used in the ADI ADSP-SC59X 64 bit SoCs
+
 config DWC_ETH_QOS_IMX
 	bool "Synopsys DWC Ethernet QOS device support for IMX"
 	depends on DWC_ETH_QOS
@@ -852,6 +859,7 @@ config RENESAS_ETHER_SWITCH
 config RENESAS_RAVB
 	bool "Renesas Ethernet AVB MAC"
 	depends on RCAR_64
+	select BITBANGMII
 	select PHYLIB
 	select PHY_ETHERNET_ID
 	help
diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index 80d70212971..d919d437c08 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -19,6 +19,7 @@ obj-$(CONFIG_DM_ETH_PHY) += eth-phy-uclass.o
 obj-$(CONFIG_DRIVER_DM9000) += dm9000x.o
 obj-$(CONFIG_DSA_SANDBOX) += dsa_sandbox.o
 obj-$(CONFIG_DWC_ETH_QOS) += dwc_eth_qos.o
+obj-$(CONFIG_DWC_ETH_QOS_ADI) += dwc_eth_qos_adi.o
 obj-$(CONFIG_DWC_ETH_QOS_IMX) += dwc_eth_qos_imx.o
 obj-$(CONFIG_DWC_ETH_QOS_INTEL) += dwc_eth_qos_intel.o
 obj-$(CONFIG_DWC_ETH_QOS_ROCKCHIP) += dwc_eth_qos_rockchip.o
diff --git a/drivers/net/designware.c b/drivers/net/designware.c
index 0a1fff38727..0f93c25e3fe 100644
--- a/drivers/net/designware.c
+++ b/drivers/net/designware.c
@@ -33,6 +33,9 @@
 #include <linux/printk.h>
 #include <power/regulator.h>
 #include "designware.h"
+#if IS_ENABLED(CONFIG_ARCH_NPCM8XX)
+#include <asm/arch/gmac.h>
+#endif
 
 static int dw_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
 {
@@ -223,6 +226,136 @@ static int dw_dm_mdio_init(const char *name, void *priv)
 }
 #endif
 
+#if IS_ENABLED(CONFIG_BITBANGMII) && IS_ENABLED(CONFIG_DM_GPIO)
+static int dw_eth_bb_mdio_active(struct mii_dev *miidev)
+{
+	struct dw_eth_dev *priv = miidev->priv;
+	struct gpio_desc *desc = &priv->mdio_gpio;
+
+	desc->flags = 0;
+	dm_gpio_set_dir_flags(&priv->mdio_gpio, GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
+
+	return 0;
+}
+
+static int dw_eth_bb_mdio_tristate(struct mii_dev *miidev)
+{
+	struct dw_eth_dev *priv = miidev->priv;
+	struct gpio_desc *desc = &priv->mdio_gpio;
+
+	desc->flags = 0;
+	dm_gpio_set_dir_flags(&priv->mdio_gpio, GPIOD_IS_IN);
+
+	return 0;
+}
+
+static int dw_eth_bb_set_mdio(struct mii_dev *miidev, int v)
+{
+	struct dw_eth_dev *priv = miidev->priv;
+
+	if (v)
+		dm_gpio_set_value(&priv->mdio_gpio, 1);
+	else
+		dm_gpio_set_value(&priv->mdio_gpio, 0);
+
+	return 0;
+}
+
+static int dw_eth_bb_get_mdio(struct mii_dev *miidev, int *v)
+{
+	struct dw_eth_dev *priv = miidev->priv;
+
+	*v = dm_gpio_get_value(&priv->mdio_gpio);
+
+	return 0;
+}
+
+static int dw_eth_bb_set_mdc(struct mii_dev *miidev, int v)
+{
+	struct dw_eth_dev *priv = miidev->priv;
+
+	if (v)
+		dm_gpio_set_value(&priv->mdc_gpio, 1);
+	else
+		dm_gpio_set_value(&priv->mdc_gpio, 0);
+
+	return 0;
+}
+
+static int dw_eth_bb_delay(struct mii_dev *miidev)
+{
+	struct dw_eth_dev *priv = miidev->priv;
+
+	udelay(priv->bb_delay);
+	return 0;
+}
+
+static const struct bb_miiphy_bus_ops dw_eth_bb_miiphy_bus_ops = {
+	.mdio_active	= dw_eth_bb_mdio_active,
+	.mdio_tristate	= dw_eth_bb_mdio_tristate,
+	.set_mdio	= dw_eth_bb_set_mdio,
+	.get_mdio	= dw_eth_bb_get_mdio,
+	.set_mdc	= dw_eth_bb_set_mdc,
+	.delay		= dw_eth_bb_delay,
+};
+
+static int dw_bb_miiphy_read(struct mii_dev *miidev, int addr,
+			     int devad, int reg)
+{
+	return bb_miiphy_read(miidev, &dw_eth_bb_miiphy_bus_ops,
+			      addr, devad, reg);
+}
+
+static int dw_bb_miiphy_write(struct mii_dev *miidev, int addr,
+			      int devad, int reg, u16 value)
+{
+	return bb_miiphy_write(miidev, &dw_eth_bb_miiphy_bus_ops,
+			       addr, devad, reg, value);
+}
+
+static int dw_bb_mdio_init(const char *name, struct udevice *dev)
+{
+	struct dw_eth_dev *dwpriv = dev_get_priv(dev);
+	struct mii_dev *bus = mdio_alloc();
+	int ret;
+
+	if (!bus) {
+		printf("Failed to allocate MDIO bus\n");
+		return -ENOMEM;
+	}
+
+	debug("\n%s: use bitbang mii..\n", dev->name);
+	ret = gpio_request_by_name(dev, "snps,mdc-gpio", 0,
+				   &dwpriv->mdc_gpio,
+				   GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
+	if (ret) {
+		debug("no mdc-gpio\n");
+		return ret;
+	}
+	ret = gpio_request_by_name(dev, "snps,mdio-gpio", 0,
+				   &dwpriv->mdio_gpio,
+				   GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
+	if (ret) {
+		debug("no mdio-gpio\n");
+		return ret;
+	}
+	dwpriv->bb_delay = dev_read_u32_default(dev, "snps,bitbang-delay", 1);
+
+	dwpriv->bus = bus;
+	dwpriv->dev = dev;
+
+	snprintf(bus->name, sizeof(bus->name), "%s", name);
+	bus->read = dw_bb_miiphy_read;
+	bus->write = dw_bb_miiphy_write;
+#if CONFIG_IS_ENABLED(DM_GPIO)
+	bus->reset = dw_mdio_reset;
+#endif
+	bus->priv = dwpriv;
+
+	return mdio_register(bus);
+}
+#endif
+
 static void tx_descs_init(struct dw_eth_dev *priv)
 {
 	struct eth_dma_regs *dma_p = priv->dma_regs_p;
@@ -352,10 +485,35 @@ static int dw_adjust_link(struct dw_eth_dev *priv, struct eth_mac_regs *mac_p,
 	       (phydev->port == PORT_FIBRE) ? ", fiber mode" : "");
 
 #ifdef CONFIG_ARCH_NPCM8XX
+	if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
+		unsigned int start;
+
+		/* Indirect access to VR_MII_MMD registers */
+		writew((VR_MII_MMD >> 9), PCS_BA + PCS_IND_AC);
+		/* Set PCS_Mode to SGMII */
+		clrsetbits_le16(PCS_BA + VR_MII_MMD_AN_CTRL, BIT(1), BIT(2));
+		/* Set Auto Speed Mode Change */
+		setbits_le16(PCS_BA + VR_MII_MMD_CTRL1, BIT(9));
+		/* Indirect access to SR_MII_MMD registers */
+		writew((SR_MII_MMD >> 9), PCS_BA + PCS_IND_AC);
+		/* Restart Auto-Negotiation */
+		setbits_le16(PCS_BA + SR_MII_MMD_CTRL, BIT(9) | BIT(12));
+
+		printf("SGMII PHY Wait for link up \n");
+		/* SGMII PHY Wait for link up */
+		start = get_timer(0);
+		while (!(readw(PCS_BA + SR_MII_MMD_STS) & BIT(2))) {
+			if (get_timer(start) >= LINK_UP_TIMEOUT) {
+				printf("PHY link up timeout\n");
+				return -ETIMEDOUT;
+			}
+			mdelay(1);
+		};
+	}
 	/* Pass all Multicast Frames */
 	setbits_le32(&mac_p->framefilt, BIT(4));
-
 #endif
+
 	return 0;
 }
 
@@ -784,51 +942,29 @@ int designware_eth_probe(struct udevice *dev)
 	priv->interface = pdata->phy_interface;
 	priv->max_speed = pdata->max_speed;
 
-#if IS_ENABLED(CONFIG_DM_MDIO)
-	ret = dw_dm_mdio_init(dev->name, dev);
-#else
-	ret = dw_mdio_init(dev->name, dev);
-#endif
-	if (ret) {
-		err = ret;
-		goto mdio_err;
-	}
-	priv->bus = miiphy_get_dev_by_name(dev->name);
-	priv->dev = dev;
-
 #if IS_ENABLED(CONFIG_BITBANGMII) && IS_ENABLED(CONFIG_DM_GPIO)
 	if (dev_read_bool(dev, "snps,bitbang-mii")) {
-		int bus_idx;
-
-		debug("\n%s: use bitbang mii..\n", dev->name);
-		ret = gpio_request_by_name(dev, "snps,mdc-gpio", 0,
-					   &priv->mdc_gpio, GPIOD_IS_OUT
-					   | GPIOD_IS_OUT_ACTIVE);
+		ret = dw_bb_mdio_init(dev->name, dev);
 		if (ret) {
-			debug("no mdc-gpio\n");
-			return ret;
+			err = ret;
+			goto mdio_err;
 		}
-		ret = gpio_request_by_name(dev, "snps,mdio-gpio", 0,
-					   &priv->mdio_gpio, GPIOD_IS_OUT
-					   | GPIOD_IS_OUT_ACTIVE);
+	} else
+#endif
+	{
+#if IS_ENABLED(CONFIG_DM_MDIO)
+		ret = dw_dm_mdio_init(dev->name, dev);
+#else
+		ret = dw_mdio_init(dev->name, dev);
+#endif
 		if (ret) {
-			debug("no mdio-gpio\n");
-			return ret;
-		}
-		priv->bb_delay = dev_read_u32_default(dev, "snps,bitbang-delay", 1);
-
-		for (bus_idx = 0; bus_idx < bb_miiphy_buses_num; bus_idx++) {
-			if (!bb_miiphy_buses[bus_idx].priv) {
-				bb_miiphy_buses[bus_idx].priv = priv;
-				strlcpy(bb_miiphy_buses[bus_idx].name, priv->bus->name,
-					MDIO_NAME_LEN);
-				priv->bus->read = bb_miiphy_read;
-				priv->bus->write = bb_miiphy_write;
-				break;
-			}
+			err = ret;
+			goto mdio_err;
 		}
+		priv->bus = miiphy_get_dev_by_name(dev->name);
+		priv->dev = dev;
 	}
-#endif
+
 	ret = dw_phy_init(priv, dev);
 	debug("%s, ret=%d\n", __func__, ret);
 	if (!ret)
@@ -939,83 +1075,3 @@ static struct pci_device_id supported[] = {
 };
 
 U_BOOT_PCI_DEVICE(eth_designware, supported);
-
-#if IS_ENABLED(CONFIG_BITBANGMII) && IS_ENABLED(CONFIG_DM_GPIO)
-static int dw_eth_bb_mdio_active(struct bb_miiphy_bus *bus)
-{
-	struct dw_eth_dev *priv = bus->priv;
-	struct gpio_desc *desc = &priv->mdio_gpio;
-
-	desc->flags = 0;
-	dm_gpio_set_dir_flags(&priv->mdio_gpio, GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
-
-	return 0;
-}
-
-static int dw_eth_bb_mdio_tristate(struct bb_miiphy_bus *bus)
-{
-	struct dw_eth_dev *priv = bus->priv;
-	struct gpio_desc *desc = &priv->mdio_gpio;
-
-	desc->flags = 0;
-	dm_gpio_set_dir_flags(&priv->mdio_gpio, GPIOD_IS_IN);
-
-	return 0;
-}
-
-static int dw_eth_bb_set_mdio(struct bb_miiphy_bus *bus, int v)
-{
-	struct dw_eth_dev *priv = bus->priv;
-
-	if (v)
-		dm_gpio_set_value(&priv->mdio_gpio, 1);
-	else
-		dm_gpio_set_value(&priv->mdio_gpio, 0);
-
-	return 0;
-}
-
-static int dw_eth_bb_get_mdio(struct bb_miiphy_bus *bus, int *v)
-{
-	struct dw_eth_dev *priv = bus->priv;
-
-	*v = dm_gpio_get_value(&priv->mdio_gpio);
-
-	return 0;
-}
-
-static int dw_eth_bb_set_mdc(struct bb_miiphy_bus *bus, int v)
-{
-	struct dw_eth_dev *priv = bus->priv;
-
-	if (v)
-		dm_gpio_set_value(&priv->mdc_gpio, 1);
-	else
-		dm_gpio_set_value(&priv->mdc_gpio, 0);
-
-	return 0;
-}
-
-static int dw_eth_bb_delay(struct bb_miiphy_bus *bus)
-{
-	struct dw_eth_dev *priv = bus->priv;
-
-	udelay(priv->bb_delay);
-	return 0;
-}
-
-struct bb_miiphy_bus bb_miiphy_buses[] = {
-	{
-		.name		= BB_MII_DEVNAME,
-		.mdio_active	= dw_eth_bb_mdio_active,
-		.mdio_tristate	= dw_eth_bb_mdio_tristate,
-		.set_mdio	= dw_eth_bb_set_mdio,
-		.get_mdio	= dw_eth_bb_get_mdio,
-		.set_mdc	= dw_eth_bb_set_mdc,
-		.delay		= dw_eth_bb_delay,
-		.priv		= NULL,
-	}
-};
-
-int bb_miiphy_buses_num = ARRAY_SIZE(bb_miiphy_buses);
-#endif
diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c
index 2279481d935..b4ec3614696 100644
--- a/drivers/net/dwc_eth_qos.c
+++ b/drivers/net/dwc_eth_qos.c
@@ -1632,6 +1632,12 @@ static const struct udevice_id eqos_ids[] = {
 		.data = (ulong)&eqos_jh7110_config
 	},
 #endif
+#if IS_ENABLED(CONFIG_DWC_ETH_QOS_ADI)
+	{
+		.compatible = "adi,sc59x-dwmac-eqos",
+		.data = (ulong)&eqos_adi_config
+	},
+#endif
 	{ }
 };
 
diff --git a/drivers/net/dwc_eth_qos.h b/drivers/net/dwc_eth_qos.h
index 123f98d5d53..403e8203974 100644
--- a/drivers/net/dwc_eth_qos.h
+++ b/drivers/net/dwc_eth_qos.h
@@ -87,6 +87,7 @@ struct eqos_mac_regs {
 #define EQOS_MAC_MDIO_ADDRESS_CR_MASK			GENMASK(11, 8)
 #define EQOS_MAC_MDIO_ADDRESS_CR_100_150		1
 #define EQOS_MAC_MDIO_ADDRESS_CR_20_35			2
+#define EQOS_MAC_MDIO_ADDRESS_CR_150_250		4
 #define EQOS_MAC_MDIO_ADDRESS_CR_250_300		5
 #define EQOS_MAC_MDIO_ADDRESS_SKAP			BIT(4)
 #define EQOS_MAC_MDIO_ADDRESS_GOC_MASK			GENMASK(3, 2)
@@ -301,3 +302,4 @@ extern struct eqos_config eqos_qcom_config;
 extern struct eqos_config eqos_stm32mp13_config;
 extern struct eqos_config eqos_stm32mp15_config;
 extern struct eqos_config eqos_jh7110_config;
+extern struct eqos_config eqos_adi_config;
diff --git a/drivers/net/dwc_eth_qos_adi.c b/drivers/net/dwc_eth_qos_adi.c
new file mode 100644
index 00000000000..0e6a901e303
--- /dev/null
+++ b/drivers/net/dwc_eth_qos_adi.c
@@ -0,0 +1,103 @@
+// SPDX-License-Identifier: GPL-2.0
+/**
+ * (C) Copyright 2024 - Analog Devices, Inc.
+ *
+ * Written and/or maintained by Timesys Corporation
+ *
+ * Author: Greg Malysa <greg.malysa@timesys.com>
+ * Additional Contact: Nathan Barrett-Morrison <nathan.morrison@timesys.com>
+ */
+
+#include <clk.h>
+#include <dm.h>
+#include <net.h>
+#include <phy.h>
+#include <reset.h>
+#include <linux/io.h>
+
+#include <asm/arch-adi/sc5xx/sc5xx.h>
+
+#include "dwc_eth_qos.h"
+
+static int eqos_start_resets_adi(struct udevice *dev)
+{
+	struct eqos_priv *eqos = dev_get_priv(dev);
+
+	/*
+	 * Settings need to latch with the DMA reset below. Currently only
+	 * rgmii is supported but other phy interfaces may be supported in
+	 * the future
+	 */
+	sc5xx_enable_rgmii();
+	setbits_32(&eqos->dma_regs->mode, EQOS_DMA_MODE_SWR);
+
+	return 0;
+}
+
+static int eqos_probe_resources_adi(struct udevice *dev)
+{
+	struct eqos_priv *eqos = dev_get_priv(dev);
+	phy_interface_t interface;
+	int ret;
+
+	ret = eqos_get_base_addr_dt(dev);
+	if (ret) {
+		pr_err("eqos_get_base_addr_dt failed: %d\n", ret);
+		return ret;
+	}
+
+	interface = eqos->config->interface(dev);
+	if (interface == PHY_INTERFACE_MODE_NA) {
+		pr_err("Invalid PHY interface\n");
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+/**
+ * rgmii tx clock rate is set to 125 MHz regardless of phy mode, and
+ * by default the internal clock is always connected to 125 MHz. According
+ * to the HRM it is invalid for this clock to have any other speed, so
+ * the hardware won't work anyway if this is wrong.
+ */
+static ulong eqos_get_tick_clk_rate_adi(struct udevice *dev)
+{
+	return 125 * 1000000;
+}
+
+static int eqos_get_enetaddr_adi(struct udevice *dev)
+{
+	struct eth_pdata *pdata = dev_get_plat(dev);
+
+	return eth_env_get_enetaddr("ethaddr", pdata->enetaddr);
+}
+
+static struct eqos_ops eqos_adi_ops = {
+	.eqos_inval_desc = eqos_inval_desc_generic,
+	.eqos_flush_desc = eqos_flush_desc_generic,
+	.eqos_inval_buffer = eqos_inval_buffer_generic,
+	.eqos_flush_buffer = eqos_flush_buffer_generic,
+	.eqos_probe_resources = eqos_probe_resources_adi,
+	.eqos_remove_resources = eqos_null_ops,
+	.eqos_start_resets = eqos_start_resets_adi,
+	.eqos_stop_resets = eqos_null_ops,
+	.eqos_start_clks = eqos_null_ops,
+	.eqos_stop_clks = eqos_null_ops,
+	.eqos_calibrate_pads = eqos_null_ops,
+	.eqos_disable_calibration = eqos_null_ops,
+	.eqos_set_tx_clk_speed = eqos_null_ops,
+	.eqos_get_enetaddr = eqos_get_enetaddr_adi,
+	.eqos_get_tick_clk_rate = eqos_get_tick_clk_rate_adi,
+};
+
+struct eqos_config __maybe_unused eqos_adi_config = {
+	.reg_access_always_ok = true,
+	.mdio_wait =  20,
+	.swr_wait = 50,
+	.config_mac = EQOS_MAC_RXQ_CTRL0_RXQ0EN_ENABLED_DCB,
+	.config_mac_mdio = EQOS_MAC_MDIO_ADDRESS_CR_150_250,
+	.axi_bus_width = EQOS_AXI_WIDTH_32,
+	.interface = dev_read_phy_mode,
+	.ops = &eqos_adi_ops,
+};
diff --git a/drivers/net/phy/micrel_ksz90x1.c b/drivers/net/phy/micrel_ksz90x1.c
index c48ae6e88f3..ee8eae1efd9 100644
--- a/drivers/net/phy/micrel_ksz90x1.c
+++ b/drivers/net/phy/micrel_ksz90x1.c
@@ -389,10 +389,126 @@ U_BOOT_PHY_DRIVER(ksz9031) = {
 #define KSZ9131RN_DLL_ENABLE_DELAY	0
 #define KSZ9131RN_DLL_DISABLE_DELAY	BIT(12)
 
+#define KSZ9131RN_COMMON_CTRL				0
+#define KSZ9131RN_COMMON_CTRL_INDIVIDUAL_LED_MODE	BIT(4)
+
+#define KSZ9131RN_LED_ERRATA_REG	0x1e
+#define KSZ9131RN_LED_ERRATA_BIT	BIT(9)
+
+#define KSZ9131RN_CONTROL_PAD_SKEW	4
+#define KSZ9131RN_RX_DATA_PAD_SKEW	5
+#define KSZ9131RN_TX_DATA_PAD_SKEW	6
+#define KSZ9131RN_CLK_PAD_SKEW		8
+
+#define KSZ9131RN_SKEW_5BIT_MAX		2400
+#define KSZ9131RN_SKEW_4BIT_MAX		800
+#define KSZ9131RN_OFFSET		700
+#define KSZ9131RN_STEP			100
+
+static int ksz9131_of_load_skew_values(struct phy_device *phydev,
+				       ofnode of_node,
+				       u16 reg, size_t field_sz,
+				       const char *field[], u8 numfields)
+{
+	int val[4] = {-(1 + KSZ9131RN_OFFSET), -(2 + KSZ9131RN_OFFSET),
+		      -(3 + KSZ9131RN_OFFSET), -(4 + KSZ9131RN_OFFSET)};
+	int skewval, skewmax = 0;
+	int matches = 0;
+	u16 maxval;
+	u16 newval;
+	u16 mask;
+	int i;
+
+	/* psec properties in dts should mean x pico seconds */
+	if (field_sz == 5)
+		skewmax = KSZ9131RN_SKEW_5BIT_MAX;
+	else
+		skewmax = KSZ9131RN_SKEW_4BIT_MAX;
+
+	for (i = 0; i < numfields; i++)
+		if (!ofnode_read_s32(of_node, field[i], &skewval)) {
+			if (skewval < -KSZ9131RN_OFFSET)
+				skewval = -KSZ9131RN_OFFSET;
+			else if (skewval > skewmax)
+				skewval = skewmax;
+
+			val[i] = skewval + KSZ9131RN_OFFSET;
+			matches++;
+		}
+
+	if (!matches)
+		return 0;
+
+	if (matches < numfields)
+		newval = phy_read_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG, reg);
+	else
+		newval = 0;
+
+	maxval = (field_sz == 4) ? 0xf : 0x1f;
+	for (i = 0; i < numfields; i++)
+		if (val[i] != -(i + 1 + KSZ9131RN_OFFSET)) {
+			mask = 0xffff;
+			mask ^= maxval << (field_sz * i);
+			newval = (newval & mask) |
+				(((val[i] / KSZ9131RN_STEP) & maxval)
+					<< (field_sz * i));
+		}
+
+	return phy_write_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG, reg, newval);
+}
+
+static int ksz9131_of_load_all_skew_values(struct phy_device *phydev)
+{
+	const char *control_skews[2] = { "txen-skew-psec", "rxdv-skew-psec" };
+	const char *clk_skews[2] = { "rxc-skew-psec", "txc-skew-psec" };
+	const char *rx_data_skews[4] = {
+		"rxd0-skew-psec", "rxd1-skew-psec",
+		"rxd2-skew-psec", "rxd3-skew-psec"
+	};
+	const char *tx_data_skews[4] = {
+		"txd0-skew-psec", "txd1-skew-psec",
+		"txd2-skew-psec", "txd3-skew-psec"
+	};
+	struct ofnode_phandle_args phandle_args;
+	int ret;
+
+	/*
+	 * Silently ignore failure here as the device tree is not required to
+	 * contain a phy node.
+	 */
+	if (dev_read_phandle_with_args(phydev->dev, "phy-handle", NULL, 0, 0,
+				       &phandle_args))
+		return 0;
+
+	if (!ofnode_valid(phandle_args.node))
+		return 0;
+
+	ret = ksz9131_of_load_skew_values(phydev, phandle_args.node,
+					  KSZ9131RN_CLK_PAD_SKEW, 5,
+					  clk_skews, 2);
+	if (ret < 0)
+		return ret;
+
+	ret = ksz9131_of_load_skew_values(phydev, phandle_args.node,
+					  KSZ9131RN_CONTROL_PAD_SKEW, 4,
+					  control_skews, 2);
+	if (ret < 0)
+		return ret;
+
+	ret = ksz9131_of_load_skew_values(phydev, phandle_args.node,
+					  KSZ9131RN_RX_DATA_PAD_SKEW, 4,
+					  rx_data_skews, 4);
+	if (ret < 0)
+		return ret;
+
+	return ksz9131_of_load_skew_values(phydev, phandle_args.node,
+					   KSZ9131RN_TX_DATA_PAD_SKEW, 4,
+					   tx_data_skews, 4);
+}
+
 static int ksz9131_config_rgmii_delay(struct phy_device *phydev)
 {
-	struct phy_driver *drv = phydev->drv;
-	u16 rxcdll_val, txcdll_val, val;
+	u16 rxcdll_val, txcdll_val;
 	int ret;
 
 	switch (phydev->interface) {
@@ -416,24 +532,37 @@ static int ksz9131_config_rgmii_delay(struct phy_device *phydev)
 		return 0;
 	}
 
-	val = drv->readext(phydev, 0, KSZ9131RN_MMD_COMMON_CTRL_REG,
-			   KSZ9131RN_RXC_DLL_CTRL);
-	val &= ~KSZ9131RN_DLL_CTRL_BYPASS;
-	val |= rxcdll_val;
-	ret = drv->writeext(phydev, 0, KSZ9131RN_MMD_COMMON_CTRL_REG,
-			    KSZ9131RN_RXC_DLL_CTRL, val);
-	if (ret)
+	ret = phy_modify_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
+			     KSZ9131RN_RXC_DLL_CTRL, KSZ9131RN_DLL_CTRL_BYPASS,
+			     rxcdll_val);
+	if (ret < 0)
 		return ret;
 
-	val = drv->readext(phydev, 0, KSZ9131RN_MMD_COMMON_CTRL_REG,
-			   KSZ9131RN_TXC_DLL_CTRL);
+	return phy_modify_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
+			      KSZ9131RN_TXC_DLL_CTRL, KSZ9131RN_DLL_CTRL_BYPASS,
+			      txcdll_val);
+}
+
+/* Silicon Errata DS80000693B
+ *
+ * When LEDs are configured in Individual Mode, LED1 is ON in a no-link
+ * condition. Workaround is to set register 0x1e, bit 9, this way LED1 behaves
+ * according to the datasheet (off if there is no link).
+ */
+static int ksz9131_led_errata(struct phy_device *phydev)
+{
+	int reg;
 
-	val &= ~KSZ9131RN_DLL_CTRL_BYPASS;
-	val |= txcdll_val;
-	ret = drv->writeext(phydev, 0, KSZ9131RN_MMD_COMMON_CTRL_REG,
-			    KSZ9131RN_TXC_DLL_CTRL, val);
+	reg = phy_read_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
+			   KSZ9131RN_COMMON_CTRL);
+	if (reg < 0)
+		return reg;
 
-	return ret;
+	if (!(reg & KSZ9131RN_COMMON_CTRL_INDIVIDUAL_LED_MODE))
+		return 0;
+
+	return phy_set_bits(phydev, MDIO_DEVAD_NONE, KSZ9131RN_LED_ERRATA_REG,
+			    KSZ9131RN_LED_ERRATA_BIT);
 }
 
 static int ksz9131_config(struct phy_device *phydev)
@@ -446,6 +575,14 @@ static int ksz9131_config(struct phy_device *phydev)
 			return ret;
 	}
 
+	ret = ksz9131_of_load_all_skew_values(phydev);
+	if (ret < 0)
+		return ret;
+
+	ret = ksz9131_led_errata(phydev);
+	if (ret < 0)
+		return ret;
+
 	/* add an option to disable the gigabit feature of this PHY */
 	if (env_get("disable_giga")) {
 		unsigned features;
diff --git a/drivers/net/phy/miiphybb.c b/drivers/net/phy/miiphybb.c
index 9f5f9b12c9f..76463da7299 100644
--- a/drivers/net/phy/miiphybb.c
+++ b/drivers/net/phy/miiphybb.c
@@ -17,37 +17,13 @@
 #include <miiphy.h>
 #include <asm/global_data.h>
 
-int bb_miiphy_init(void)
-{
-	int i;
-
-	for (i = 0; i < bb_miiphy_buses_num; i++)
-		if (bb_miiphy_buses[i].init != NULL)
-			bb_miiphy_buses[i].init(&bb_miiphy_buses[i]);
-
-	return 0;
-}
-
-static inline struct bb_miiphy_bus *bb_miiphy_getbus(const char *devname)
-{
-	int i;
-
-	/* Search the correct bus */
-	for (i = 0; i < bb_miiphy_buses_num; i++) {
-		if (!strcmp(bb_miiphy_buses[i].name, devname)) {
-			return &bb_miiphy_buses[i];
-		}
-	}
-	return NULL;
-}
-
 /*****************************************************************************
  *
  * Utility to send the preamble, address, and register (common to read
  * and write).
  */
-static void miiphy_pre(struct bb_miiphy_bus *bus, char read,
-		       unsigned char addr, unsigned char reg)
+static void miiphy_pre(struct mii_dev *miidev, const struct bb_miiphy_bus_ops *ops,
+		       char read, unsigned char addr, unsigned char reg)
 {
 	int j;
 
@@ -59,62 +35,62 @@ static void miiphy_pre(struct bb_miiphy_bus *bus, char read,
 	 * but it is safer and will be much more robust.
 	 */
 
-	bus->mdio_active(bus);
-	bus->set_mdio(bus, 1);
+	ops->mdio_active(miidev);
+	ops->set_mdio(miidev, 1);
 	for (j = 0; j < 32; j++) {
-		bus->set_mdc(bus, 0);
-		bus->delay(bus);
-		bus->set_mdc(bus, 1);
-		bus->delay(bus);
+		ops->set_mdc(miidev, 0);
+		ops->delay(miidev);
+		ops->set_mdc(miidev, 1);
+		ops->delay(miidev);
 	}
 
 	/* send the start bit (01) and the read opcode (10) or write (10) */
-	bus->set_mdc(bus, 0);
-	bus->set_mdio(bus, 0);
-	bus->delay(bus);
-	bus->set_mdc(bus, 1);
-	bus->delay(bus);
-	bus->set_mdc(bus, 0);
-	bus->set_mdio(bus, 1);
-	bus->delay(bus);
-	bus->set_mdc(bus, 1);
-	bus->delay(bus);
-	bus->set_mdc(bus, 0);
-	bus->set_mdio(bus, read);
-	bus->delay(bus);
-	bus->set_mdc(bus, 1);
-	bus->delay(bus);
-	bus->set_mdc(bus, 0);
-	bus->set_mdio(bus, !read);
-	bus->delay(bus);
-	bus->set_mdc(bus, 1);
-	bus->delay(bus);
+	ops->set_mdc(miidev, 0);
+	ops->set_mdio(miidev, 0);
+	ops->delay(miidev);
+	ops->set_mdc(miidev, 1);
+	ops->delay(miidev);
+	ops->set_mdc(miidev, 0);
+	ops->set_mdio(miidev, 1);
+	ops->delay(miidev);
+	ops->set_mdc(miidev, 1);
+	ops->delay(miidev);
+	ops->set_mdc(miidev, 0);
+	ops->set_mdio(miidev, read);
+	ops->delay(miidev);
+	ops->set_mdc(miidev, 1);
+	ops->delay(miidev);
+	ops->set_mdc(miidev, 0);
+	ops->set_mdio(miidev, !read);
+	ops->delay(miidev);
+	ops->set_mdc(miidev, 1);
+	ops->delay(miidev);
 
 	/* send the PHY address */
 	for (j = 0; j < 5; j++) {
-		bus->set_mdc(bus, 0);
+		ops->set_mdc(miidev, 0);
 		if ((addr & 0x10) == 0) {
-			bus->set_mdio(bus, 0);
+			ops->set_mdio(miidev, 0);
 		} else {
-			bus->set_mdio(bus, 1);
+			ops->set_mdio(miidev, 1);
 		}
-		bus->delay(bus);
-		bus->set_mdc(bus, 1);
-		bus->delay(bus);
+		ops->delay(miidev);
+		ops->set_mdc(miidev, 1);
+		ops->delay(miidev);
 		addr <<= 1;
 	}
 
 	/* send the register address */
 	for (j = 0; j < 5; j++) {
-		bus->set_mdc(bus, 0);
+		ops->set_mdc(miidev, 0);
 		if ((reg & 0x10) == 0) {
-			bus->set_mdio(bus, 0);
+			ops->set_mdio(miidev, 0);
 		} else {
-			bus->set_mdio(bus, 1);
+			ops->set_mdio(miidev, 1);
 		}
-		bus->delay(bus);
-		bus->set_mdc(bus, 1);
-		bus->delay(bus);
+		ops->delay(miidev);
+		ops->set_mdc(miidev, 1);
+		ops->delay(miidev);
 		reg <<= 1;
 	}
 }
@@ -126,62 +102,57 @@ static void miiphy_pre(struct bb_miiphy_bus *bus, char read,
  * Returns:
  *   0 on success
  */
-int bb_miiphy_read(struct mii_dev *miidev, int addr, int devad, int reg)
+int bb_miiphy_read(struct mii_dev *miidev, const struct bb_miiphy_bus_ops *ops,
+		   int addr, int devad, int reg)
 {
 	unsigned short rdreg; /* register working value */
 	int v;
 	int j; /* counter */
-	struct bb_miiphy_bus *bus;
 
-	bus = bb_miiphy_getbus(miidev->name);
-	if (bus == NULL) {
-		return -1;
-	}
-
-	miiphy_pre (bus, 1, addr, reg);
+	miiphy_pre(miidev, ops, 1, addr, reg);
 
 	/* tri-state our MDIO I/O pin so we can read */
-	bus->set_mdc(bus, 0);
-	bus->mdio_tristate(bus);
-	bus->delay(bus);
-	bus->set_mdc(bus, 1);
-	bus->delay(bus);
+	ops->set_mdc(miidev, 0);
+	ops->mdio_tristate(miidev);
+	ops->delay(miidev);
+	ops->set_mdc(miidev, 1);
+	ops->delay(miidev);
 
 	/* check the turnaround bit: the PHY should be driving it to zero */
-	bus->get_mdio(bus, &v);
+	ops->get_mdio(miidev, &v);
 	if (v != 0) {
 		/* puts ("PHY didn't drive TA low\n"); */
 		for (j = 0; j < 32; j++) {
-			bus->set_mdc(bus, 0);
-			bus->delay(bus);
-			bus->set_mdc(bus, 1);
-			bus->delay(bus);
+			ops->set_mdc(miidev, 0);
+			ops->delay(miidev);
+			ops->set_mdc(miidev, 1);
+			ops->delay(miidev);
 		}
 		/* There is no PHY, return */
 		return -1;
 	}
 
-	bus->set_mdc(bus, 0);
-	bus->delay(bus);
+	ops->set_mdc(miidev, 0);
+	ops->delay(miidev);
 
 	/* read 16 bits of register data, MSB first */
 	rdreg = 0;
 	for (j = 0; j < 16; j++) {
-		bus->set_mdc(bus, 1);
-		bus->delay(bus);
+		ops->set_mdc(miidev, 1);
+		ops->delay(miidev);
 		rdreg <<= 1;
-		bus->get_mdio(bus, &v);
+		ops->get_mdio(miidev, &v);
 		rdreg |= (v & 0x1);
-		bus->set_mdc(bus, 0);
-		bus->delay(bus);
+		ops->set_mdc(miidev, 0);
+		ops->delay(miidev);
 	}
 
-	bus->set_mdc(bus, 1);
-	bus->delay(bus);
-	bus->set_mdc(bus, 0);
-	bus->delay(bus);
-	bus->set_mdc(bus, 1);
-	bus->delay(bus);
+	ops->set_mdc(miidev, 1);
+	ops->delay(miidev);
+	ops->set_mdc(miidev, 0);
+	ops->delay(miidev);
+	ops->set_mdc(miidev, 1);
+	ops->delay(miidev);
 
 	debug("%s[%s](0x%x) @ 0x%x = 0x%04x\n", __func__, miidev->name, reg, addr, rdreg);
 
@@ -195,54 +166,47 @@ int bb_miiphy_read(struct mii_dev *miidev, int addr, int devad, int reg)
  * Returns:
  *   0 on success
  */
-int bb_miiphy_write(struct mii_dev *miidev, int addr, int devad, int reg,
-		    u16 value)
+int bb_miiphy_write(struct mii_dev *miidev, const struct bb_miiphy_bus_ops *ops,
+		    int addr, int devad, int reg, u16 value)
 {
-	struct bb_miiphy_bus *bus;
 	int j;			/* counter */
 
-	bus = bb_miiphy_getbus(miidev->name);
-	if (bus == NULL) {
-		/* Bus not found! */
-		return -1;
-	}
-
-	miiphy_pre (bus, 0, addr, reg);
+	miiphy_pre(miidev, ops, 0, addr, reg);
 
 	/* send the turnaround (10) */
-	bus->set_mdc(bus, 0);
-	bus->set_mdio(bus, 1);
-	bus->delay(bus);
-	bus->set_mdc(bus, 1);
-	bus->delay(bus);
-	bus->set_mdc(bus, 0);
-	bus->set_mdio(bus, 0);
-	bus->delay(bus);
-	bus->set_mdc(bus, 1);
-	bus->delay(bus);
+	ops->set_mdc(miidev, 0);
+	ops->set_mdio(miidev, 1);
+	ops->delay(miidev);
+	ops->set_mdc(miidev, 1);
+	ops->delay(miidev);
+	ops->set_mdc(miidev, 0);
+	ops->set_mdio(miidev, 0);
+	ops->delay(miidev);
+	ops->set_mdc(miidev, 1);
+	ops->delay(miidev);
 
 	/* write 16 bits of register data, MSB first */
 	for (j = 0; j < 16; j++) {
-		bus->set_mdc(bus, 0);
+		ops->set_mdc(miidev, 0);
 		if ((value & 0x00008000) == 0) {
-			bus->set_mdio(bus, 0);
+			ops->set_mdio(miidev, 0);
 		} else {
-			bus->set_mdio(bus, 1);
+			ops->set_mdio(miidev, 1);
 		}
-		bus->delay(bus);
-		bus->set_mdc(bus, 1);
-		bus->delay(bus);
+		ops->delay(miidev);
+		ops->set_mdc(miidev, 1);
+		ops->delay(miidev);
 		value <<= 1;
 	}
 
 	/*
 	 * Tri-state the MDIO line.
 	 */
-	bus->mdio_tristate(bus);
-	bus->set_mdc(bus, 0);
-	bus->delay(bus);
-	bus->set_mdc(bus, 1);
-	bus->delay(bus);
+	ops->mdio_tristate(miidev);
+	ops->set_mdc(miidev, 0);
+	ops->delay(miidev);
+	ops->set_mdc(miidev, 1);
+	ops->delay(miidev);
 
 	return 0;
 }
diff --git a/drivers/net/ravb.c b/drivers/net/ravb.c
index 7286ad19598..539fd37ee59 100644
--- a/drivers/net/ravb.c
+++ b/drivers/net/ravb.c
@@ -354,8 +354,15 @@ static int ravb_mac_init(struct ravb_priv *eth)
 	/* Disable MAC Interrupt */
 	writel(0, eth->iobase + RAVB_REG_ECSIPR);
 
-	/* Recv frame limit set register */
-	writel(RFLR_RFL_MIN, eth->iobase + RAVB_REG_RFLR);
+	/*
+	 * Set receive frame length
+	 *
+	 * The length set here describes the frame from the destination address
+	 * up to and including the CRC data. However only the frame data,
+	 * excluding the CRC, are transferred to memory. To allow for the
+	 * largest frames add the CRC length to the maximum Rx descriptor size.
+	 */
+	writel(RFLR_RFL_MIN + ETH_FCS_LEN, eth->iobase + RAVB_REG_RFLR);
 
 	return 0;
 }
@@ -490,6 +497,88 @@ static void ravb_stop(struct udevice *dev)
 	ravb_reset(dev);
 }
 
+/* Bitbang MDIO access */
+static int ravb_bb_mdio_active(struct mii_dev *miidev)
+{
+	struct ravb_priv *eth = miidev->priv;
+
+	setbits_le32(eth->iobase + RAVB_REG_PIR, PIR_MMD);
+
+	return 0;
+}
+
+static int ravb_bb_mdio_tristate(struct mii_dev *miidev)
+{
+	struct ravb_priv *eth = miidev->priv;
+
+	clrbits_le32(eth->iobase + RAVB_REG_PIR, PIR_MMD);
+
+	return 0;
+}
+
+static int ravb_bb_set_mdio(struct mii_dev *miidev, int v)
+{
+	struct ravb_priv *eth = miidev->priv;
+
+	if (v)
+		setbits_le32(eth->iobase + RAVB_REG_PIR, PIR_MDO);
+	else
+		clrbits_le32(eth->iobase + RAVB_REG_PIR, PIR_MDO);
+
+	return 0;
+}
+
+static int ravb_bb_get_mdio(struct mii_dev *miidev, int *v)
+{
+	struct ravb_priv *eth = miidev->priv;
+
+	*v = (readl(eth->iobase + RAVB_REG_PIR) & PIR_MDI) >> 3;
+
+	return 0;
+}
+
+static int ravb_bb_set_mdc(struct mii_dev *miidev, int v)
+{
+	struct ravb_priv *eth = miidev->priv;
+
+	if (v)
+		setbits_le32(eth->iobase + RAVB_REG_PIR, PIR_MDC);
+	else
+		clrbits_le32(eth->iobase + RAVB_REG_PIR, PIR_MDC);
+
+	return 0;
+}
+
+static int ravb_bb_delay(struct mii_dev *miidev)
+{
+	udelay(10);
+
+	return 0;
+}
+
+static const struct bb_miiphy_bus_ops ravb_bb_miiphy_bus_ops = {
+	.mdio_active	= ravb_bb_mdio_active,
+	.mdio_tristate	= ravb_bb_mdio_tristate,
+	.set_mdio	= ravb_bb_set_mdio,
+	.get_mdio	= ravb_bb_get_mdio,
+	.set_mdc	= ravb_bb_set_mdc,
+	.delay		= ravb_bb_delay,
+};
+
+static int ravb_bb_miiphy_read(struct mii_dev *miidev, int addr,
+			       int devad, int reg)
+{
+	return bb_miiphy_read(miidev, &ravb_bb_miiphy_bus_ops,
+			      addr, devad, reg);
+}
+
+static int ravb_bb_miiphy_write(struct mii_dev *miidev, int addr,
+				int devad, int reg, u16 value)
+{
+	return bb_miiphy_write(miidev, &ravb_bb_miiphy_bus_ops,
+			       addr, devad, reg, value);
+}
+
 static int ravb_probe(struct udevice *dev)
 {
 	struct eth_pdata *pdata = dev_get_plat(dev);
@@ -503,7 +592,7 @@ static int ravb_probe(struct udevice *dev)
 
 	ret = clk_get_bulk(dev, &eth->clks);
 	if (ret < 0)
-		goto err_mdio_alloc;
+		goto err_clk_get;
 
 	mdiodev = mdio_alloc();
 	if (!mdiodev) {
@@ -511,37 +600,39 @@ static int ravb_probe(struct udevice *dev)
 		goto err_mdio_alloc;
 	}
 
-	mdiodev->read = bb_miiphy_read;
-	mdiodev->write = bb_miiphy_write;
-	bb_miiphy_buses[0].priv = eth;
+	mdiodev->read = ravb_bb_miiphy_read;
+	mdiodev->write = ravb_bb_miiphy_write;
+	mdiodev->priv = eth;
 	snprintf(mdiodev->name, sizeof(mdiodev->name), dev->name);
 
 	ret = mdio_register(mdiodev);
 	if (ret < 0)
 		goto err_mdio_register;
 
-	eth->bus = miiphy_get_dev_by_name(dev->name);
+	eth->bus = mdiodev;
 
 	/* Bring up PHY */
 	ret = clk_enable_bulk(&eth->clks);
 	if (ret)
-		goto err_mdio_register;
+		goto err_clk_enable;
 
 	ret = ravb_reset(dev);
 	if (ret)
-		goto err_mdio_reset;
+		goto err_clk_enable;
 
 	ret = ravb_phy_config(dev);
 	if (ret)
-		goto err_mdio_reset;
+		goto err_clk_enable;
 
 	return 0;
 
-err_mdio_reset:
-	clk_release_bulk(&eth->clks);
+err_clk_enable:
+	mdio_unregister(mdiodev);
 err_mdio_register:
 	mdio_free(mdiodev);
 err_mdio_alloc:
+	clk_release_bulk(&eth->clks);
+err_clk_get:
 	unmap_physmem(eth->iobase, MAP_NOCACHE);
 	return ret;
 }
@@ -560,83 +651,6 @@ static int ravb_remove(struct udevice *dev)
 	return 0;
 }
 
-static int ravb_bb_init(struct bb_miiphy_bus *bus)
-{
-	return 0;
-}
-
-static int ravb_bb_mdio_active(struct bb_miiphy_bus *bus)
-{
-	struct ravb_priv *eth = bus->priv;
-
-	setbits_le32(eth->iobase + RAVB_REG_PIR, PIR_MMD);
-
-	return 0;
-}
-
-static int ravb_bb_mdio_tristate(struct bb_miiphy_bus *bus)
-{
-	struct ravb_priv *eth = bus->priv;
-
-	clrbits_le32(eth->iobase + RAVB_REG_PIR, PIR_MMD);
-
-	return 0;
-}
-
-static int ravb_bb_set_mdio(struct bb_miiphy_bus *bus, int v)
-{
-	struct ravb_priv *eth = bus->priv;
-
-	if (v)
-		setbits_le32(eth->iobase + RAVB_REG_PIR, PIR_MDO);
-	else
-		clrbits_le32(eth->iobase + RAVB_REG_PIR, PIR_MDO);
-
-	return 0;
-}
-
-static int ravb_bb_get_mdio(struct bb_miiphy_bus *bus, int *v)
-{
-	struct ravb_priv *eth = bus->priv;
-
-	*v = (readl(eth->iobase + RAVB_REG_PIR) & PIR_MDI) >> 3;
-
-	return 0;
-}
-
-static int ravb_bb_set_mdc(struct bb_miiphy_bus *bus, int v)
-{
-	struct ravb_priv *eth = bus->priv;
-
-	if (v)
-		setbits_le32(eth->iobase + RAVB_REG_PIR, PIR_MDC);
-	else
-		clrbits_le32(eth->iobase + RAVB_REG_PIR, PIR_MDC);
-
-	return 0;
-}
-
-static int ravb_bb_delay(struct bb_miiphy_bus *bus)
-{
-	udelay(10);
-
-	return 0;
-}
-
-struct bb_miiphy_bus bb_miiphy_buses[] = {
-	{
-		.name		= "ravb",
-		.init		= ravb_bb_init,
-		.mdio_active	= ravb_bb_mdio_active,
-		.mdio_tristate	= ravb_bb_mdio_tristate,
-		.set_mdio	= ravb_bb_set_mdio,
-		.get_mdio	= ravb_bb_get_mdio,
-		.set_mdc	= ravb_bb_set_mdc,
-		.delay		= ravb_bb_delay,
-	},
-};
-int bb_miiphy_buses_num = ARRAY_SIZE(bb_miiphy_buses);
-
 static const struct eth_ops ravb_ops = {
 	.start			= ravb_start,
 	.send			= ravb_send,
@@ -658,8 +672,6 @@ int ravb_of_to_plat(struct udevice *dev)
 
 	pdata->max_speed = dev_read_u32_default(dev, "max-speed", 1000);
 
-	sprintf(bb_miiphy_buses[0].name, dev->name);
-
 	return 0;
 }
 
diff --git a/drivers/net/sh_eth.c b/drivers/net/sh_eth.c
index f1ce994cfd5..f695a3a41d2 100644
--- a/drivers/net/sh_eth.c
+++ b/drivers/net/sh_eth.c
@@ -643,6 +643,97 @@ static void sh_ether_stop(struct udevice *dev)
 	sh_eth_stop(&priv->shdev);
 }
 
+/******* for bb_miiphy *******/
+static int sh_eth_bb_mdio_active(struct mii_dev *miidev)
+{
+	struct sh_eth_dev *eth = miidev->priv;
+	struct sh_eth_info *port_info = &eth->port_info[eth->port];
+
+	sh_eth_write(port_info, sh_eth_read(port_info, PIR) | PIR_MMD, PIR);
+
+	return 0;
+}
+
+static int sh_eth_bb_mdio_tristate(struct mii_dev *miidev)
+{
+	struct sh_eth_dev *eth = miidev->priv;
+	struct sh_eth_info *port_info = &eth->port_info[eth->port];
+
+	sh_eth_write(port_info, sh_eth_read(port_info, PIR) & ~PIR_MMD, PIR);
+
+	return 0;
+}
+
+static int sh_eth_bb_set_mdio(struct mii_dev *miidev, int v)
+{
+	struct sh_eth_dev *eth = miidev->priv;
+	struct sh_eth_info *port_info = &eth->port_info[eth->port];
+
+	if (v)
+		sh_eth_write(port_info,
+			     sh_eth_read(port_info, PIR) | PIR_MDO, PIR);
+	else
+		sh_eth_write(port_info,
+			     sh_eth_read(port_info, PIR) & ~PIR_MDO, PIR);
+
+	return 0;
+}
+
+static int sh_eth_bb_get_mdio(struct mii_dev *miidev, int *v)
+{
+	struct sh_eth_dev *eth = miidev->priv;
+	struct sh_eth_info *port_info = &eth->port_info[eth->port];
+
+	*v = (sh_eth_read(port_info, PIR) & PIR_MDI) >> 3;
+
+	return 0;
+}
+
+static int sh_eth_bb_set_mdc(struct mii_dev *miidev, int v)
+{
+	struct sh_eth_dev *eth = miidev->priv;
+	struct sh_eth_info *port_info = &eth->port_info[eth->port];
+
+	if (v)
+		sh_eth_write(port_info,
+			     sh_eth_read(port_info, PIR) | PIR_MDC, PIR);
+	else
+		sh_eth_write(port_info,
+			     sh_eth_read(port_info, PIR) & ~PIR_MDC, PIR);
+
+	return 0;
+}
+
+static int sh_eth_bb_delay(struct mii_dev *miidev)
+{
+	udelay(10);
+
+	return 0;
+}
+
+static const struct bb_miiphy_bus_ops sh_ether_bb_miiphy_bus_ops = {
+	.mdio_active	= sh_eth_bb_mdio_active,
+	.mdio_tristate	= sh_eth_bb_mdio_tristate,
+	.set_mdio	= sh_eth_bb_set_mdio,
+	.get_mdio	= sh_eth_bb_get_mdio,
+	.set_mdc	= sh_eth_bb_set_mdc,
+	.delay		= sh_eth_bb_delay,
+};
+
+static int sh_eth_bb_miiphy_read(struct mii_dev *miidev, int addr,
+				 int devad, int reg)
+{
+	return bb_miiphy_read(miidev, &sh_ether_bb_miiphy_bus_ops,
+			      addr, devad, reg);
+}
+
+static int sh_eth_bb_miiphy_write(struct mii_dev *miidev, int addr,
+				  int devad, int reg, u16 value)
+{
+	return bb_miiphy_write(miidev, &sh_ether_bb_miiphy_bus_ops,
+			       addr, devad, reg, value);
+}
+
 static int sh_ether_probe(struct udevice *udev)
 {
 	struct eth_pdata *pdata = dev_get_plat(udev);
@@ -664,16 +755,16 @@ static int sh_ether_probe(struct udevice *udev)
 		return ret;
 	}
 
-	mdiodev->read = bb_miiphy_read;
-	mdiodev->write = bb_miiphy_write;
-	bb_miiphy_buses[0].priv = eth;
+	mdiodev->read = sh_eth_bb_miiphy_read;
+	mdiodev->write = sh_eth_bb_miiphy_write;
+	mdiodev->priv = eth;
 	snprintf(mdiodev->name, sizeof(mdiodev->name), udev->name);
 
 	ret = mdio_register(mdiodev);
 	if (ret < 0)
 		goto err_mdio_register;
 
-	priv->bus = miiphy_get_dev_by_name(udev->name);
+	priv->bus = mdiodev;
 
 	eth->port = CFG_SH_ETHER_USE_PORT;
 	eth->port_info[eth->port].phy_addr = CFG_SH_ETHER_PHY_ADDR;
@@ -748,8 +839,6 @@ int sh_ether_of_to_plat(struct udevice *dev)
 	if (cell)
 		pdata->max_speed = fdt32_to_cpu(*cell);
 
-	sprintf(bb_miiphy_buses[0].name, dev->name);
-
 	return 0;
 }
 
@@ -775,91 +864,3 @@ U_BOOT_DRIVER(eth_sh_ether) = {
 	.plat_auto	= sizeof(struct eth_pdata),
 	.flags		= DM_FLAG_ALLOC_PRIV_DMA,
 };
-
-/******* for bb_miiphy *******/
-static int sh_eth_bb_init(struct bb_miiphy_bus *bus)
-{
-	return 0;
-}
-
-static int sh_eth_bb_mdio_active(struct bb_miiphy_bus *bus)
-{
-	struct sh_eth_dev *eth = bus->priv;
-	struct sh_eth_info *port_info = &eth->port_info[eth->port];
-
-	sh_eth_write(port_info, sh_eth_read(port_info, PIR) | PIR_MMD, PIR);
-
-	return 0;
-}
-
-static int sh_eth_bb_mdio_tristate(struct bb_miiphy_bus *bus)
-{
-	struct sh_eth_dev *eth = bus->priv;
-	struct sh_eth_info *port_info = &eth->port_info[eth->port];
-
-	sh_eth_write(port_info, sh_eth_read(port_info, PIR) & ~PIR_MMD, PIR);
-
-	return 0;
-}
-
-static int sh_eth_bb_set_mdio(struct bb_miiphy_bus *bus, int v)
-{
-	struct sh_eth_dev *eth = bus->priv;
-	struct sh_eth_info *port_info = &eth->port_info[eth->port];
-
-	if (v)
-		sh_eth_write(port_info,
-			     sh_eth_read(port_info, PIR) | PIR_MDO, PIR);
-	else
-		sh_eth_write(port_info,
-			     sh_eth_read(port_info, PIR) & ~PIR_MDO, PIR);
-
-	return 0;
-}
-
-static int sh_eth_bb_get_mdio(struct bb_miiphy_bus *bus, int *v)
-{
-	struct sh_eth_dev *eth = bus->priv;
-	struct sh_eth_info *port_info = &eth->port_info[eth->port];
-
-	*v = (sh_eth_read(port_info, PIR) & PIR_MDI) >> 3;
-
-	return 0;
-}
-
-static int sh_eth_bb_set_mdc(struct bb_miiphy_bus *bus, int v)
-{
-	struct sh_eth_dev *eth = bus->priv;
-	struct sh_eth_info *port_info = &eth->port_info[eth->port];
-
-	if (v)
-		sh_eth_write(port_info,
-			     sh_eth_read(port_info, PIR) | PIR_MDC, PIR);
-	else
-		sh_eth_write(port_info,
-			     sh_eth_read(port_info, PIR) & ~PIR_MDC, PIR);
-
-	return 0;
-}
-
-static int sh_eth_bb_delay(struct bb_miiphy_bus *bus)
-{
-	udelay(10);
-
-	return 0;
-}
-
-struct bb_miiphy_bus bb_miiphy_buses[] = {
-	{
-		.name		= "sh_eth",
-		.init		= sh_eth_bb_init,
-		.mdio_active	= sh_eth_bb_mdio_active,
-		.mdio_tristate	= sh_eth_bb_mdio_tristate,
-		.set_mdio	= sh_eth_bb_set_mdio,
-		.get_mdio	= sh_eth_bb_get_mdio,
-		.set_mdc	= sh_eth_bb_set_mdc,
-		.delay		= sh_eth_bb_delay,
-	}
-};
-
-int bb_miiphy_buses_num = ARRAY_SIZE(bb_miiphy_buses);
diff --git a/drivers/net/ti/am65-cpsw-nuss.c b/drivers/net/ti/am65-cpsw-nuss.c
index c70b42f6bcc..3c62fc0b428 100644
--- a/drivers/net/ti/am65-cpsw-nuss.c
+++ b/drivers/net/ti/am65-cpsw-nuss.c
@@ -661,7 +661,7 @@ static int am65_cpsw_ofdata_parse_phy(struct udevice *dev)
 
 	dev_read_u32(dev, "max-speed", (u32 *)&pdata->max_speed);
 	if (pdata->max_speed)
-		dev_err(dev, "Port %u speed froced to %uMbit\n",
+		dev_err(dev, "Port %u speed forced to %uMbit\n",
 			priv->port_id, pdata->max_speed);
 
 	return 0;
diff --git a/drivers/pci/pci_auto.c b/drivers/pci/pci_auto.c
index 90f81886445..e68e31a8227 100644
--- a/drivers/pci/pci_auto.c
+++ b/drivers/pci/pci_auto.c
@@ -107,7 +107,8 @@ static void dm_pciauto_setup_device(struct udevice *dev,
 			}
 
 			if (prefetch &&
-			    (bar_response & PCI_BASE_ADDRESS_MEM_PREFETCH))
+			    (bar_response & PCI_BASE_ADDRESS_MEM_PREFETCH) &&
+			    (found_mem64 || prefetch->bus_lower < 0x100000000ULL))
 				bar_res = prefetch;
 			else
 				bar_res = mem;
diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index e12347e8a03..d3fe90d939e 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -163,8 +163,8 @@ config PHY_RCAR_GEN2
 
 config PHY_RCAR_GEN3
 	tristate "Renesas R-Car Gen3 USB PHY"
-	depends on PHY && RCAR_GEN3 && CLK && DM_REGULATOR
-	default y if RCAR_GEN3
+	depends on PHY && CLK && DM_REGULATOR && (RCAR_GEN3 || RZG2L)
+	default y if (RCAR_GEN3 || RZG2L)
 	help
 	  Support for the Renesas R-Car Gen3 USB PHY. This driver operates the
 	  PHY connected to EHCI USB module and controls USB OTG operation.
@@ -309,5 +309,6 @@ source "drivers/phy/cadence/Kconfig"
 source "drivers/phy/ti/Kconfig"
 source "drivers/phy/qcom/Kconfig"
 source "drivers/phy/renesas/Kconfig"
+source "drivers/phy/starfive/Kconfig"
 
 endmenu
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index c35f9294dd9..ce4ea28b299 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -44,3 +44,4 @@ obj-y += cadence/
 obj-y += ti/
 obj-y += qcom/
 obj-y += renesas/
+obj-y += starfive/
diff --git a/drivers/phy/phy-rcar-gen3.c b/drivers/phy/phy-rcar-gen3.c
index 8c004eaf4c6..d06861c4f79 100644
--- a/drivers/phy/phy-rcar-gen3.c
+++ b/drivers/phy/phy-rcar-gen3.c
@@ -55,6 +55,7 @@
 
 /* VBCTRL */
 #define USB2_VBCTRL_DRVVBUSSEL		BIT(8)
+#define USB2_VBCTRL_VBOUT		BIT(0)
 
 /* LINECTRL1 */
 #define USB2_LINECTRL1_DPRPD_EN		BIT(19)
@@ -68,6 +69,13 @@
 #define USB2_ADPCTRL_IDPULLUP		BIT(5)	/* 1 = ID sampling is enabled */
 #define USB2_ADPCTRL_DRVVBUS		BIT(4)
 
+/*  RZ/G2L specific */
+#define USB2_OBINT_IDCHG_EN		BIT(0)
+#define USB2_LINECTRL1_USB2_IDMON	BIT(0)
+
+/* Device flags */
+#define RCAR_GEN3_PHY_NO_ADPCTRL	BIT(0)
+
 struct rcar_gen3_phy {
 	fdt_addr_t	regs;
 	struct clk	clk;
@@ -122,15 +130,50 @@ static int rcar_gen3_phy_phy_power_off(struct phy *phy)
 	return regulator_set_enable(priv->vbus_supply, false);
 }
 
+static bool rcar_gen3_phy_check_id(struct phy *phy)
+{
+	const u32 adpdevmask = USB2_ADPCTRL_IDDIG | USB2_ADPCTRL_OTGSESSVLD;
+	struct rcar_gen3_phy *priv = dev_get_priv(phy->dev);
+	ulong flags = dev_get_driver_data(phy->dev);
+	u32 val;
+
+	if (flags & RCAR_GEN3_PHY_NO_ADPCTRL) {
+		val = readl(priv->regs + USB2_LINECTRL1);
+		return !!(val & USB2_LINECTRL1_USB2_IDMON);
+	}
+
+	val = readl(priv->regs + USB2_ADPCTRL);
+	return (val & adpdevmask) == adpdevmask;
+}
+
+static void rcar_gen3_phy_set_vbus(struct phy *phy, bool enable)
+{
+	struct rcar_gen3_phy *priv = dev_get_priv(phy->dev);
+	ulong flags = dev_get_driver_data(phy->dev);
+	u32 bits = USB2_ADPCTRL_DRVVBUS;
+	u64 reg = USB2_ADPCTRL;
+
+	if (flags & RCAR_GEN3_PHY_NO_ADPCTRL) {
+		bits = USB2_VBCTRL_VBOUT;
+		reg = USB2_VBCTRL;
+	}
+
+	if (enable)
+		setbits_le32(priv->regs + reg, bits);
+	else
+		clrbits_le32(priv->regs + reg, bits);
+}
+
 static int rcar_gen3_phy_phy_set_mode(struct phy *phy, enum phy_mode mode,
 				      int submode)
 {
-	const u32 adpdevmask = USB2_ADPCTRL_IDDIG | USB2_ADPCTRL_OTGSESSVLD;
 	struct rcar_gen3_phy *priv = dev_get_priv(phy->dev);
-	u32 adpctrl;
+	ulong flags = dev_get_driver_data(phy->dev);
 
 	if (mode == PHY_MODE_USB_OTG) {
 		if (submode) {
+			u32 obint_enable_bits;
+
 			/* OTG submode is used as initialization indicator */
 			writel(USB2_INT_ENABLE_UCOM_INTEN |
 			       USB2_INT_ENABLE_USBH_INTB_EN |
@@ -138,13 +181,16 @@ static int rcar_gen3_phy_phy_set_mode(struct phy *phy, enum phy_mode mode,
 			       priv->regs + USB2_INT_ENABLE);
 			setbits_le32(priv->regs + USB2_VBCTRL,
 				     USB2_VBCTRL_DRVVBUSSEL);
-			writel(USB2_OBINT_SESSVLDCHG | USB2_OBINT_IDDIGCHG,
-			       priv->regs + USB2_OBINTSTA);
-			setbits_le32(priv->regs + USB2_OBINTEN,
-				     USB2_OBINT_SESSVLDCHG |
-				     USB2_OBINT_IDDIGCHG);
-			setbits_le32(priv->regs + USB2_ADPCTRL,
-				     USB2_ADPCTRL_IDPULLUP);
+			if (flags & RCAR_GEN3_PHY_NO_ADPCTRL) {
+				obint_enable_bits = USB2_OBINT_IDCHG_EN;
+			} else {
+				obint_enable_bits = USB2_OBINT_SESSVLDCHG |
+						    USB2_OBINT_IDDIGCHG;
+				setbits_le32(priv->regs + USB2_ADPCTRL,
+					     USB2_ADPCTRL_IDPULLUP);
+			}
+			writel(obint_enable_bits, priv->regs + USB2_OBINTSTA);
+			setbits_le32(priv->regs + USB2_OBINTEN, obint_enable_bits);
 			clrsetbits_le32(priv->regs + USB2_LINECTRL1,
 					USB2_LINECTRL1_DP_RPD |
 					USB2_LINECTRL1_DM_RPD |
@@ -154,8 +200,7 @@ static int rcar_gen3_phy_phy_set_mode(struct phy *phy, enum phy_mode mode,
 					USB2_LINECTRL1_DMRPD_EN);
 		}
 
-		adpctrl = readl(priv->regs + USB2_ADPCTRL);
-		if ((adpctrl & adpdevmask) == adpdevmask)
+		if (rcar_gen3_phy_check_id(phy))
 			mode = PHY_MODE_USB_DEVICE;
 		else
 			mode = PHY_MODE_USB_HOST;
@@ -165,13 +210,13 @@ static int rcar_gen3_phy_phy_set_mode(struct phy *phy, enum phy_mode mode,
 		clrbits_le32(priv->regs + USB2_COMMCTRL, USB2_COMMCTRL_OTG_PERI);
 		setbits_le32(priv->regs + USB2_LINECTRL1,
 			     USB2_LINECTRL1_DP_RPD | USB2_LINECTRL1_DM_RPD);
-		setbits_le32(priv->regs + USB2_ADPCTRL, USB2_ADPCTRL_DRVVBUS);
+		rcar_gen3_phy_set_vbus(phy, true);
 	} else if (mode == PHY_MODE_USB_DEVICE) {
 		setbits_le32(priv->regs + USB2_COMMCTRL, USB2_COMMCTRL_OTG_PERI);
 		clrsetbits_le32(priv->regs + USB2_LINECTRL1,
 				USB2_LINECTRL1_DP_RPD | USB2_LINECTRL1_DM_RPD,
 				USB2_LINECTRL1_DM_RPD);
-		clrbits_le32(priv->regs + USB2_ADPCTRL, USB2_ADPCTRL_DRVVBUS);
+		rcar_gen3_phy_set_vbus(phy, false);
 	} else {
 		dev_err(phy->dev, "Unknown mode %d\n", mode);
 		return -EINVAL;
@@ -226,7 +271,13 @@ static int rcar_gen3_phy_remove(struct udevice *dev)
 }
 
 static const struct udevice_id rcar_gen3_phy_of_match[] = {
-	{ .compatible = "renesas,rcar-gen3-usb2-phy", },
+	{
+		.compatible = "renesas,rcar-gen3-usb2-phy",
+	},
+	{
+		.compatible = "renesas,rzg2l-usb2-phy",
+		.data = RCAR_GEN3_PHY_NO_ADPCTRL,
+	},
 	{ },
 };
 
diff --git a/drivers/phy/starfive/Kconfig b/drivers/phy/starfive/Kconfig
new file mode 100644
index 00000000000..d11338ed484
--- /dev/null
+++ b/drivers/phy/starfive/Kconfig
@@ -0,0 +1,21 @@
+#
+# PHY drivers for Starfive platforms
+#
+
+menu "Starfive PHY driver"
+
+config PHY_STARFIVE_JH7110_PCIE
+	bool "Starfive JH7110 PCIe 2.0 PHY driver"
+	depends on PHY
+	help
+	  Enable this to support the Starfive JH7110 PCIE 2.0/USB 3.0 PHY.
+	  Generic PHY driver JH7110 USB 3.0/ PCIe 2.0.
+
+config PHY_STARFIVE_JH7110_USB2
+	bool "Starfive JH7110 USB 2.0 PHY driver"
+	depends on PHY
+	help
+	  Enable this to support the Starfive JH7110 USB 2.0 PHY.
+	  Generic PHY driver JH7110 USB 2.0.
+
+endmenu
diff --git a/drivers/phy/starfive/Makefile b/drivers/phy/starfive/Makefile
new file mode 100644
index 00000000000..82f25aa21b7
--- /dev/null
+++ b/drivers/phy/starfive/Makefile
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2023 Starfive
+#
+
+obj-$(CONFIG_PHY_STARFIVE_JH7110_PCIE)	+= phy-jh7110-pcie.o
+obj-$(CONFIG_PHY_STARFIVE_JH7110_USB2)	+= phy-jh7110-usb2.o
diff --git a/drivers/phy/starfive/phy-jh7110-pcie.c b/drivers/phy/starfive/phy-jh7110-pcie.c
new file mode 100644
index 00000000000..a30582821d9
--- /dev/null
+++ b/drivers/phy/starfive/phy-jh7110-pcie.c
@@ -0,0 +1,239 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * StarFive JH7110 PCIe 2.0 PHY driver
+ *
+ * Copyright (C) 2024 StarFive Technology Co., Ltd.
+ * Author: Minda Chen <minda.chen@starfivetech.com>
+ */
+#include <asm/io.h>
+#include <dm.h>
+#include <dm/device_compat.h>
+#include <errno.h>
+#include <generic-phy.h>
+#include <regmap.h>
+#include <soc.h>
+#include <syscon.h>
+#include <linux/bitops.h>
+#include <linux/err.h>
+
+#include "phy-jh7110-usb-syscon.h"
+
+#define PCIE_KVCO_LEVEL_OFF			0x28
+#define PCIE_USB3_PHY_PLL_CTL_OFF		0x7c
+#define PCIE_USB3_PHY_SS_MODE			BIT(4)
+#define PCIE_KVCO_TUNE_SIGNAL_OFF		0x80
+#define PHY_KVCO_FINE_TUNE_LEVEL		0x91
+#define PHY_KVCO_FINE_TUNE_SIGNALS		0xc
+
+#define PCIE_USB3_PHY_MODE			0x1
+#define PCIE_BUS_WIDTH				0x2
+#define PCIE_USB3_PHY_ENABLE			0x1
+#define PCIE_USB3_PHY_SPLIT			0x1
+
+struct jh7110_pcie_phy {
+	struct phy *phy;
+	struct regmap *stg_syscon;
+	struct regmap *sys_syscon;
+	void __iomem *regs;
+	struct regmap_field *phy_mode;
+	struct regmap_field *bus_width;
+	struct regmap_field *usb3_phy_en;
+	struct regmap_field *usb_split;
+	enum phy_mode mode;
+};
+
+static int phy_pcie_mode_set(struct jh7110_pcie_phy *data, bool usb_mode)
+{
+	unsigned int phy_mode, width, usb3_phy, ss_mode, split;
+
+	/* default is PCIe mode */
+	if (!data->stg_syscon || !data->sys_syscon) {
+		if (usb_mode) {
+			dev_err(data->phy->dev, "doesn't support USB3 mode\n");
+			return -EINVAL;
+		}
+		return 0;
+	}
+
+	if (usb_mode) {
+		phy_mode = PCIE_USB3_PHY_MODE;
+		width = 0;
+		usb3_phy = PCIE_USB3_PHY_ENABLE;
+		ss_mode = PCIE_USB3_PHY_SS_MODE;
+		split = 0;
+	} else {
+		phy_mode = 0;
+		width = PCIE_BUS_WIDTH;
+		usb3_phy = 0;
+		ss_mode = 0;
+		split = PCIE_USB3_PHY_SPLIT;
+	}
+
+	regmap_field_write(data->phy_mode, phy_mode);
+	regmap_field_write(data->bus_width, width);
+	regmap_field_write(data->usb3_phy_en, usb3_phy);
+	clrsetbits_le32(data->regs + PCIE_USB3_PHY_PLL_CTL_OFF,
+			PCIE_USB3_PHY_SS_MODE, ss_mode);
+	regmap_field_write(data->usb_split, split);
+
+	return 0;
+}
+
+static void phy_kvco_gain_set(struct jh7110_pcie_phy *phy)
+{
+	/* PCIe Multi-PHY PLL KVCO Gain fine tune settings: */
+	writel(PHY_KVCO_FINE_TUNE_LEVEL, phy->regs + PCIE_KVCO_LEVEL_OFF);
+	writel(PHY_KVCO_FINE_TUNE_SIGNALS, phy->regs + PCIE_KVCO_TUNE_SIGNAL_OFF);
+}
+
+static int jh7110_pcie_phy_set_mode(struct phy *phy,
+				    enum phy_mode mode, int submode)
+{
+	struct udevice *dev = phy->dev;
+	struct jh7110_pcie_phy *pcie_phy = dev_get_priv(dev);
+	int ret;
+
+	if (mode == pcie_phy->mode)
+		return 0;
+
+	switch (mode) {
+	case PHY_MODE_USB_HOST:
+	case PHY_MODE_USB_DEVICE:
+	case PHY_MODE_USB_OTG:
+		ret = phy_pcie_mode_set(pcie_phy, 1);
+		if (ret)
+			return ret;
+		break;
+	case PHY_MODE_PCIE:
+		phy_pcie_mode_set(pcie_phy, 0);
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	dev_dbg(phy->dev, "Changing PHY mode to %d\n", mode);
+	pcie_phy->mode = mode;
+
+	return 0;
+}
+
+static const struct phy_ops jh7110_pcie_phy_ops = {
+	.set_mode	= jh7110_pcie_phy_set_mode,
+};
+
+static int phy_stg_regfield_init(struct udevice *dev, int mode, int usb3)
+{
+	struct jh7110_pcie_phy *phy = dev_get_priv(dev);
+	struct reg_field phy_mode = REG_FIELD(mode, 20, 21);
+	struct reg_field bus_width = REG_FIELD(usb3, 2, 3);
+	struct reg_field usb3_phy_en = REG_FIELD(usb3, 4, 4);
+
+	phy->phy_mode = devm_regmap_field_alloc(dev, phy->stg_syscon, phy_mode);
+	if (IS_ERR(phy->phy_mode)) {
+		dev_err(dev, "PHY mode reg field init failed\n");
+		return PTR_ERR(phy->phy_mode);
+	}
+
+	phy->bus_width = devm_regmap_field_alloc(dev, phy->stg_syscon, bus_width);
+	if (IS_ERR(phy->bus_width)) {
+		dev_err(dev, "PHY bus width reg field init failed\n");
+		return PTR_ERR(phy->bus_width);
+	}
+
+	phy->usb3_phy_en = devm_regmap_field_alloc(dev, phy->stg_syscon, usb3_phy_en);
+	if (IS_ERR(phy->usb3_phy_en)) {
+		dev_err(dev, "USB3 PHY enable field init failed\n");
+		return PTR_ERR(phy->bus_width);
+	}
+
+	return 0;
+}
+
+static int phy_sys_regfield_init(struct udevice *dev, int split)
+{
+	struct jh7110_pcie_phy *phy = dev_get_priv(dev);
+	struct reg_field usb_split  = REG_FIELD(split, USB_PDRSTN_SPLIT_BIT, USB_PDRSTN_SPLIT_BIT);
+
+	phy->usb_split = devm_regmap_field_alloc(dev, phy->sys_syscon, usb_split);
+	if (IS_ERR(phy->usb_split)) {
+		dev_err(dev, "USB split field init failed\n");
+		return PTR_ERR(phy->usb_split);
+	}
+
+	return 0;
+}
+
+static int starfive_pcie_phy_get_syscon(struct udevice *dev)
+{
+	struct jh7110_pcie_phy *phy = dev_get_priv(dev);
+	struct ofnode_phandle_args sys_phandle, stg_phandle;
+	int ret;
+
+	/* get corresponding syscon phandle */
+	ret = dev_read_phandle_with_args(dev, "starfive,sys-syscon", NULL, 1, 0,
+					 &sys_phandle);
+
+	if (ret < 0) {
+		dev_err(dev, "Can't get sys cfg phandle: %d\n", ret);
+		return ret;
+	}
+
+	ret = dev_read_phandle_with_args(dev, "starfive,stg-syscon", NULL, 2, 0,
+					 &stg_phandle);
+
+	if (ret < 0) {
+		dev_err(dev, "Can't get stg cfg phandle: %d\n", ret);
+		return ret;
+	}
+
+	phy->sys_syscon = syscon_node_to_regmap(sys_phandle.node);
+	/* get syscon register offset */
+	if (!IS_ERR(phy->sys_syscon)) {
+		ret = phy_sys_regfield_init(dev, SYSCON_USB_PDRSTN_REG_OFFSET);
+		if (ret)
+			return ret;
+	} else {
+		phy->sys_syscon = NULL;
+	}
+
+	phy->stg_syscon = syscon_node_to_regmap(stg_phandle.node);
+	if (!IS_ERR(phy->stg_syscon))
+		return phy_stg_regfield_init(dev, stg_phandle.args[0],
+					     stg_phandle.args[1]);
+	else
+		phy->stg_syscon = NULL;
+
+	return 0;
+}
+
+int jh7110_pcie_phy_probe(struct udevice *dev)
+{
+	struct jh7110_pcie_phy *phy = dev_get_priv(dev);
+	int rc;
+
+	phy->regs = dev_read_addr_ptr(dev);
+	if (!phy->regs)
+		return -EINVAL;
+
+	rc = starfive_pcie_phy_get_syscon(dev);
+	if (rc)
+		return rc;
+
+	phy_kvco_gain_set(phy);
+
+	return 0;
+}
+
+static const struct udevice_id jh7110_pcie_phy[] = {
+	{ .compatible = "starfive,jh7110-pcie-phy"},
+	{},
+};
+
+U_BOOT_DRIVER(jh7110_pcie_phy) = {
+	.name = "jh7110_pcie_phy",
+	.id = UCLASS_PHY,
+	.of_match = jh7110_pcie_phy,
+	.probe = jh7110_pcie_phy_probe,
+	.ops = &jh7110_pcie_phy_ops,
+	.priv_auto	= sizeof(struct jh7110_pcie_phy),
+};
diff --git a/drivers/phy/starfive/phy-jh7110-usb-syscon.h b/drivers/phy/starfive/phy-jh7110-usb-syscon.h
new file mode 100644
index 00000000000..0eb66f0d859
--- /dev/null
+++ b/drivers/phy/starfive/phy-jh7110-usb-syscon.h
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+
+#ifndef PHY_JH7110_USB_SYSCON_H_
+#define PHY_JH7110_USB_SYSCON_H_
+
+#define SYSCON_USB_PDRSTN_REG_OFFSET	0x18
+#define USB_PDRSTN_SPLIT_BIT		 17
+
+#endif
diff --git a/drivers/phy/starfive/phy-jh7110-usb2.c b/drivers/phy/starfive/phy-jh7110-usb2.c
new file mode 100644
index 00000000000..1a28381e0df
--- /dev/null
+++ b/drivers/phy/starfive/phy-jh7110-usb2.c
@@ -0,0 +1,162 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * StarFive JH7110 USB 2.0 PHY driver
+ *
+ * Copyright (C) 2024 StarFive Technology Co., Ltd.
+ * Author: Minda Chen <minda.chen@starfivetech.com>
+ */
+
+#include <asm/io.h>
+#include <clk.h>
+#include <dm.h>
+#include <dm/device_compat.h>
+#include <errno.h>
+#include <generic-phy.h>
+#include <regmap.h>
+#include <soc.h>
+#include <syscon.h>
+#include <linux/bitops.h>
+#include <linux/err.h>
+
+#include "phy-jh7110-usb-syscon.h"
+
+#define USB_LS_KEEPALIVE_OFF		0x4
+#define USB_LS_KEEPALIVE_ENABLE		BIT(4)
+#define USB_PHY_CLK_RATE		125000000
+
+struct jh7110_usb2_phy {
+	struct phy *phy;
+	struct regmap *sys_syscon;
+	void __iomem *regs;
+	struct clk *usb_125m_clk;
+	struct clk *app_125m;
+	struct regmap_field *usb_split;
+	enum phy_mode mode;
+};
+
+static void usb2_set_ls_keepalive(struct jh7110_usb2_phy *phy, bool set)
+{
+	/* Host mode enable the LS speed keep-alive signal */
+	clrsetbits_le32(phy->regs + USB_LS_KEEPALIVE_OFF,
+			USB_LS_KEEPALIVE_ENABLE,
+			set ? USB_LS_KEEPALIVE_ENABLE : 0);
+}
+
+static int usb2_phy_set_mode(struct phy *phy,
+			     enum phy_mode mode, int submode)
+{
+	struct udevice *dev = phy->dev;
+	struct jh7110_usb2_phy *usb2_phy = dev_get_priv(dev);
+
+	if (mode == usb2_phy->mode)
+		return 0;
+
+	switch (mode) {
+	case PHY_MODE_USB_HOST:
+	case PHY_MODE_USB_DEVICE:
+	case PHY_MODE_USB_OTG:
+		dev_dbg(dev, "Changing PHY to %d\n", mode);
+		usb2_phy->mode = mode;
+		usb2_set_ls_keepalive(usb2_phy, (mode != PHY_MODE_USB_DEVICE));
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	/* set default split usb 2.0 only mode */
+	regmap_field_write(usb2_phy->usb_split, true);
+
+	return 0;
+}
+
+static int jh7110_usb2_phy_init(struct phy *phy)
+{
+	struct udevice *dev = phy->dev;
+	struct jh7110_usb2_phy *usb2_phy = dev_get_priv(dev);
+	int ret;
+
+	ret = clk_set_rate(usb2_phy->usb_125m_clk, USB_PHY_CLK_RATE);
+	if (ret < 0) {
+		dev_err(dev, "Failed to set 125m clock\n");
+		return ret;
+	}
+
+	return clk_prepare_enable(usb2_phy->app_125m);
+}
+
+static int jh7110_usb2_phy_exit(struct phy *phy)
+{
+	struct udevice *dev = phy->dev;
+	struct jh7110_usb2_phy *usb2_phy = dev_get_priv(dev);
+
+	clk_disable_unprepare(usb2_phy->app_125m);
+
+	return 0;
+}
+
+struct phy_ops jh7110_usb2_phy_ops = {
+	.init     = jh7110_usb2_phy_init,
+	.exit     = jh7110_usb2_phy_exit,
+	.set_mode = usb2_phy_set_mode,
+};
+
+int jh7110_usb2_phy_probe(struct udevice *dev)
+{
+	struct jh7110_usb2_phy *phy = dev_get_priv(dev);
+	ofnode node;
+	struct reg_field usb_split;
+	int ret;
+
+	phy->regs = dev_read_addr_ptr(dev);
+	if (!phy->regs)
+		return -EINVAL;
+
+	node = ofnode_by_compatible(ofnode_null(), "starfive,jh7110-sys-syscon");
+	if (!ofnode_valid(node)) {
+		dev_err(dev, "Can't get syscon dev node\n");
+		return -ENODEV;
+	}
+
+	phy->sys_syscon = syscon_node_to_regmap(node);
+	if (IS_ERR(phy->sys_syscon)) {
+		dev_err(dev, "Can't get syscon regmap: %d\n", ret);
+		return PTR_ERR(phy->sys_syscon);
+	}
+
+	usb_split.reg = SYSCON_USB_PDRSTN_REG_OFFSET;
+	usb_split.lsb = USB_PDRSTN_SPLIT_BIT;
+	usb_split.msb = USB_PDRSTN_SPLIT_BIT;
+	phy->usb_split = devm_regmap_field_alloc(dev, phy->sys_syscon, usb_split);
+	if (IS_ERR(phy->usb_split)) {
+		dev_err(dev, "USB split field init failed\n");
+		return PTR_ERR(phy->usb_split);
+	}
+
+	phy->usb_125m_clk = devm_clk_get(dev, "125m");
+	if (IS_ERR(phy->usb_125m_clk)) {
+		dev_err(dev, "Failed to get 125m clock\n");
+		return PTR_ERR(phy->usb_125m_clk);
+	}
+
+	phy->app_125m = devm_clk_get(dev, "app_125m");
+	if (IS_ERR(phy->app_125m)) {
+		dev_err(dev, "Failed to get app 125m clock\n");
+		return PTR_ERR(phy->app_125m);
+	}
+
+	return 0;
+}
+
+static const struct udevice_id jh7110_usb2_phy[] = {
+	{ .compatible = "starfive,jh7110-usb-phy"},
+	{},
+};
+
+U_BOOT_DRIVER(jh7110_usb2_phy) = {
+	.name = "jh7110_usb2_phy",
+	.id = UCLASS_PHY,
+	.of_match = jh7110_usb2_phy,
+	.probe = jh7110_usb2_phy_probe,
+	.ops = &jh7110_usb2_phy_ops,
+	.priv_auto	= sizeof(struct jh7110_usb2_phy),
+};
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index 6ee7dc1cce8..687fb339ea0 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -178,6 +178,14 @@ config PINCTRL_APPLE
 	  both the GPIO definitions and pin control functions for each
 	  available multiplex function.
 
+config PINCTRL_ADI
+	bool "ADI pinctrl driver"
+	depends on DM && ARCH_SC5XX
+	help
+	  This driver enables pinctrl support on SC5xx processors. This
+	  driver covers only the pin configuration functionality, and
+	  GPIO functionality is contained in the separate GPIO driver.
+
 config PINCTRL_AR933X
 	bool "QCA/Athores ar933x pin control driver"
 	depends on DM && SOC_AR933X
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index 634047a91f4..6deb6aaf6eb 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -3,6 +3,7 @@
 obj-y					+= pinctrl-uclass.o
 obj-$(CONFIG_$(XPL_)PINCTRL_GENERIC)	+= pinctrl-generic.o
 
+obj-$(CONFIG_PINCTRL_ADI)		+= pinctrl-adi-adsp.o
 obj-$(CONFIG_PINCTRL_APPLE)		+= pinctrl-apple.o
 obj-$(CONFIG_PINCTRL_AT91)		+= pinctrl-at91.o
 obj-$(CONFIG_PINCTRL_AT91PIO4)		+= pinctrl-at91-pio4.o
@@ -15,7 +16,6 @@ obj-$(CONFIG_ARCH_MTMIPS) += mtmips/
 obj-$(CONFIG_ARCH_NPCM)         += nuvoton/
 obj-$(CONFIG_PINCTRL_QCOM) += qcom/
 obj-$(CONFIG_ARCH_RENESAS) += renesas/
-obj-$(CONFIG_ARCH_RZN1) += renesas/
 obj-$(CONFIG_PINCTRL_SANDBOX)	+= pinctrl-sandbox.o
 obj-$(CONFIG_PINCTRL_SUNXI)	+= sunxi/
 obj-$(CONFIG_$(XPL_)PINCTRL_TEGRA)	+= tegra/
diff --git a/drivers/pinctrl/intel/Kconfig b/drivers/pinctrl/intel/Kconfig
index 316a8fe27fd..0d8bfc53c11 100644
--- a/drivers/pinctrl/intel/Kconfig
+++ b/drivers/pinctrl/intel/Kconfig
@@ -8,9 +8,6 @@ config INTEL_PINCTRL_DUAL_ROUTE_SUPPORT
 	bool
 	default y
 
-config INTEL_PINCTRL_PADCFG_PADTOL
-	bool n
-
 config INTEL_PINCTRL_IOSTANDBY
 	bool
 	default y
diff --git a/drivers/pinctrl/pinctrl-adi-adsp.c b/drivers/pinctrl/pinctrl-adi-adsp.c
new file mode 100644
index 00000000000..debf434212d
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-adi-adsp.c
@@ -0,0 +1,161 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * (C) Copyright 2022 - Analog Devices, Inc.
+ *
+ * Written and/or maintained by Timesys Corporation
+ *
+ * Author: Greg Malysa <greg.malysa@timesys.com>
+ * Additional Contact: Nathan Barrett-Morrison <nathan.morrison@timesys.com>
+ *
+ * dm pinctrl implementation for ADI ADSP SoCs
+ *
+ */
+
+#include <dm.h>
+#include <dm/pinctrl.h>
+#include <dm/device_compat.h>
+#include <linux/bitops.h>
+#include <linux/io.h>
+
+#define ADSP_PORT_MMIO_SIZE		0x80
+#define ADSP_PORT_PIN_SIZE		16
+
+#define ADSP_PORT_PORT_MUX_BITS		2
+#define ADSP_PORT_PORT_MUX_MASK		0x03
+#define ADSP_PINCTRL_FUNCTION_COUNT 4
+
+#define ADSP_PORT_REG_FER			0x00
+#define ADSP_PORT_REG_FER_SET		0x04
+#define ADSP_PORT_REG_FER_CLEAR		0x08
+#define ADSP_PORT_REG_DATA			0x0c
+#define ADSP_PORT_REG_DATA_SET		0x10
+#define ADSP_PORT_REG_DATA_CLEAR	0x14
+#define ADSP_PORT_REG_DIR			0x18
+#define ADSP_PORT_REG_DIR_SET		0x1c
+#define ADSP_PORT_REG_DIR_CLEAR		0x20
+#define ADSP_PORT_REG_INEN			0x24
+#define ADSP_PORT_REG_INEN_SET		0x28
+#define ADSP_PORT_REG_INEN_CLEAR	0x2c
+#define ADSP_PORT_REG_PORT_MUX		0x30
+#define ADSP_PORT_REG_DATA_TGL		0x34
+#define ADSP_PORT_REG_POLAR			0x38
+#define ADSP_PORT_REG_POLAR_SET		0x3c
+#define ADSP_PORT_REG_POLAR_CLEAR	0x40
+#define ADSP_PORT_REG_LOCK			0x44
+#define ADSP_PORT_REG_TRIG_TGL		0x48
+
+struct adsp_pinctrl_priv {
+	void __iomem *base;
+	int npins;
+	char pinbuf[16];
+};
+
+static u32 get_port(unsigned int pin)
+{
+	return pin / ADSP_PORT_PIN_SIZE;
+}
+
+static u32 get_offset(unsigned int pin)
+{
+	return pin % ADSP_PORT_PIN_SIZE;
+}
+
+static int adsp_pinctrl_pinmux_set(struct udevice *udev, unsigned int pin, unsigned int func)
+{
+	struct adsp_pinctrl_priv *priv = dev_get_priv(udev);
+	void __iomem *portbase;
+	u32 port, offset;
+	u32 val;
+
+	if (pin >= priv->npins)
+		return -ENODEV;
+
+	if (func >= ADSP_PINCTRL_FUNCTION_COUNT)
+		return -EINVAL;
+
+	port = get_port(pin);
+	offset = get_offset(pin);
+	portbase = priv->base + port * ADSP_PORT_MMIO_SIZE;
+
+	val = ioread32(portbase + ADSP_PORT_REG_PORT_MUX);
+	val &= ~(ADSP_PORT_PORT_MUX_MASK << (ADSP_PORT_PORT_MUX_BITS * offset));
+	val |= func << (ADSP_PORT_PORT_MUX_BITS * offset);
+	iowrite32(val, portbase + ADSP_PORT_REG_PORT_MUX);
+
+	iowrite32(BIT(offset), portbase + ADSP_PORT_REG_FER_SET);
+	return 0;
+}
+
+static int adsp_pinctrl_set_state(struct udevice *udev, struct udevice *config)
+{
+	const struct fdt_property *pinlist;
+	int length = 0;
+	int ret, i;
+	u32 pin, function;
+
+	pinlist = dev_read_prop(config, "adi,pins", &length);
+	if (!pinlist) {
+		dev_err(udev, "missing adi,pins property in pinctrl config node\n");
+		return -EINVAL;
+	}
+
+	if (length % (sizeof(uint32_t) * 2)) {
+		dev_err(udev, "adi,pins property must be a multiple of two uint32_ts\n");
+		return -EINVAL;
+	}
+
+	for (i = 0; i < length / sizeof(uint32_t); i += 2) {
+		ret = dev_read_u32_index(config, "adi,pins", i, &pin);
+		if (ret)
+			return ret;
+
+		ret = dev_read_u32_index(config, "adi,pins", i + 1, &function);
+		if (ret)
+			return ret;
+
+		ret = adsp_pinctrl_pinmux_set(udev, pin, function);
+		if (ret)
+			return ret;
+	}
+
+	return 0;
+}
+
+const struct pinctrl_ops adsp_pinctrl_ops = {
+	.set_state = adsp_pinctrl_set_state,
+};
+
+static int adsp_pinctrl_probe(struct udevice *udev)
+{
+	struct adsp_pinctrl_priv *priv = dev_get_priv(udev);
+
+	priv->base = dev_read_addr_ptr(udev);
+	priv->npins = dev_read_u32_default(udev, "adi,npins", 0);
+
+	if (!priv->base) {
+		dev_err(udev, "Missing or invalid pinctrl base address\n");
+		return -ENOENT;
+	}
+
+	if (!priv->npins) {
+		dev_err(udev, "Missing adi,npins property!\n");
+		return -ENOENT;
+	}
+
+	return 0;
+}
+
+static const struct udevice_id adsp_pinctrl_match[] = {
+	{ .compatible = "adi,adsp-pinctrl" },
+	{ },
+};
+
+U_BOOT_DRIVER(adi_adsp_pinctrl) = {
+	.name = "adi_adsp_pinctrl",
+	.id = UCLASS_PINCTRL,
+	.of_match = adsp_pinctrl_match,
+	.probe = adsp_pinctrl_probe,
+	.priv_auto = sizeof(struct adsp_pinctrl_priv),
+	.ops = &adsp_pinctrl_ops,
+	.flags = DM_FLAG_PRE_RELOC,
+};
diff --git a/drivers/pinctrl/pinctrl-at91.c b/drivers/pinctrl/pinctrl-at91.c
index 5038cb535e3..2938635ed95 100644
--- a/drivers/pinctrl/pinctrl-at91.c
+++ b/drivers/pinctrl/pinctrl-at91.c
@@ -9,6 +9,8 @@
 #include <dm.h>
 #include <log.h>
 #include <asm/global_data.h>
+#include <dm/device-internal.h>
+#include <dm/lists.h>
 #include <dm/pinctrl.h>
 #include <asm/hardware.h>
 #include <linux/bitops.h>
@@ -492,21 +494,58 @@ const struct pinctrl_ops at91_pinctrl_ops  = {
 	.set_state = at91_pinctrl_set_state,
 };
 
+/**
+ * at91_pinctrl_bind() - Iterates through all subnodes of the pinctrl device
+ * in the DT and binds them to U-Boot's device model. Each subnode
+ * typically represents a GPIO controller or pin configuration data.
+ *
+ * @dev: Pointer to the pinctrl device
+ *
+ * Returns 0 on success or negative error on failure
+ */
+static int at91_pinctrl_bind(struct udevice *dev)
+{
+	ofnode gpio_node;
+	struct udevice *gpio;
+	int ret;
+
+	ofnode_for_each_subnode(gpio_node, dev_ofnode(dev)) {
+		ret = lists_bind_fdt(dev, gpio_node, &gpio, NULL, false);
+		if (ret)
+			return ret;
+	}
+
+	return 0;
+}
+
 static int at91_pinctrl_probe(struct udevice *dev)
 {
 	struct at91_pinctrl_priv *priv = dev_get_priv(dev);
 	fdt_addr_t addr_base;
+	struct udevice *gpio_node;
 	int index;
 
-	for (index = 0; index < MAX_GPIO_BANKS; index++) {
-		addr_base = devfdt_get_addr_index(dev, index);
-		if (addr_base == FDT_ADDR_T_NONE)
-			break;
+	if (list_empty(&dev->child_head)) {
+		for (index = 0; index < MAX_GPIO_BANKS; index++) {
+			addr_base = devfdt_get_addr_index(dev, index);
+			if (addr_base == FDT_ADDR_T_NONE)
+				break;
 
-		priv->reg_base[index] = (struct at91_port *)addr_base;
+			priv->reg_base[index] = (struct at91_port *)addr_base;
+		}
+	} else {
+		index = 0;
+		list_for_each_entry(gpio_node, &dev->child_head, sibling_node) {
+			addr_base = dev_read_addr(gpio_node);
+			if (addr_base == FDT_ADDR_T_NONE)
+				break;
+
+			priv->reg_base[index] = (struct at91_port *)addr_base;
+			index++;
+		}
 	}
 
-	priv->nbanks = index;
+	priv->nbanks = index < MAX_GPIO_BANKS ? index : MAX_GPIO_BANKS;
 
 	return 0;
 }
@@ -524,6 +563,7 @@ U_BOOT_DRIVER(atmel_sama5d3_pinctrl) = {
 	.id = UCLASS_PINCTRL,
 	.of_match = at91_pinctrl_match,
 	.probe = at91_pinctrl_probe,
+	.bind = at91_pinctrl_bind,
 	.priv_auto	= sizeof(struct at91_pinctrl_priv),
 	.ops = &at91_pinctrl_ops,
 };
diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig
index d3eb6998551..f4a3942ee2f 100644
--- a/drivers/pinctrl/qcom/Kconfig
+++ b/drivers/pinctrl/qcom/Kconfig
@@ -7,84 +7,98 @@ config PINCTRL_QCOM
 menu "Qualcomm pinctrl drivers"
 
 config PINCTRL_QCOM_APQ8016
-	bool "Qualcomm APQ8016 GCC"
+	bool "Qualcomm APQ8016 Pinctrl"
 	select PINCTRL_QCOM
 	help
 	  Say Y here to enable support for pinctrl on the MSM8916 / APQ8016
 	  Snapdragon 410 SoC, as well as the associated GPIO driver.
 
 config PINCTRL_QCOM_APQ8096
-	bool "Qualcomm APQ8096 GCC"
+	bool "Qualcomm APQ8096 Pinctrl"
 	select PINCTRL_QCOM
 	help
 	  Say Y here to enable support for pinctrl on the MSM8996 / APQ8096
 	  Snapdragon 820 SoC, as well as the associated GPIO driver.
 
 config PINCTRL_QCOM_IPQ4019
-	bool "Qualcomm IPQ4019 GCC"
+	bool "Qualcomm IPQ4019 Pinctrl"
 	select PINCTRL_QCOM
 	help
 	  Say Y here to enable support for pinctrl on the IPQ4019 SoC,
 	  as well as the associated GPIO driver.
 
+config PINCTRL_QCOM_IPQ9574
+	bool "Qualcomm IPQ9574 Pinctrl"
+	select PINCTRL_QCOM
+	help
+	  Say Y here to enable support for pinctrl on the IPQ9574 SoC,
+	  as well as the associated GPIO driver.
+
 config PINCTRL_QCOM_QCM2290
-	bool "Qualcomm QCM2290 GCC"
+	bool "Qualcomm QCM2290 Pinctrl"
 	select PINCTRL_QCOM
 	help
 	  Say Y here to enable support for pinctrl on the Snapdragon QCM2290 SoC,
 	  as well as the associated GPIO driver.
 
 config PINCTRL_QCOM_QCS404
-	bool "Qualcomm QCS404 GCC"
+	bool "Qualcomm QCS404 Pinctrl"
 	select PINCTRL_QCOM
 	help
 	  Say Y here to enable support for pinctrl on the Snapdragon QCS404 SoC,
 	  as well as the associated GPIO driver.
 
+config PINCTRL_QCOM_SC7280
+	bool "Qualcomm SC7280/QCM6490 Pinctrl"
+	select PINCTRL_QCOM
+	help
+	  Say Y here to enable support for pinctrl on the Snapdragon SC7280 SoC,
+	  as well as the associated GPIO driver.
+
 config PINCTRL_QCOM_SDM845
-	bool "Qualcomm SDM845 GCC"
+	bool "Qualcomm SDM845 Pinctrl"
 	select PINCTRL_QCOM
 	help
 	  Say Y here to enable support for pinctrl on the Snapdragon 845 SoC,
 	  as well as the associated GPIO driver.
 
 config PINCTRL_QCOM_SM6115
-	bool "Qualcomm SM6115 GCC"
+	bool "Qualcomm SM6115 Pinctrl"
 	select PINCTRL_QCOM
 	help
 	  Say Y here to enable support for pinctrl on the Snapdragon SM6115 SoC,
 	  as well as the associated GPIO driver.
 
 config PINCTRL_QCOM_SM8150
-	bool "Qualcomm SM8150 GCC"
+	bool "Qualcomm SM8150 Pinctrl"
 	select PINCTRL_QCOM
 	help
 	  Say Y here to enable support for pinctrl on the Snapdragon SM8150 SoC,
 	  as well as the associated GPIO driver.
 
 config PINCTRL_QCOM_SM8250
-	bool "Qualcomm SM8250 GCC"
+	bool "Qualcomm SM8250 Pinctrl"
 	select PINCTRL_QCOM
 	help
 	  Say Y here to enable support for pinctrl on the Snapdragon SM8250 SoC,
 	  as well as the associated GPIO driver.
 
 config PINCTRL_QCOM_SM8550
-	bool "Qualcomm SM8550 GCC"
+	bool "Qualcomm SM8550 Pinctrl"
 	select PINCTRL_QCOM
 	help
 	  Say Y here to enable support for pinctrl on the Snapdragon SM8550 SoC,
 	  as well as the associated GPIO driver.
 
 config PINCTRL_QCOM_SM8650
-	bool "Qualcomm SM8650 GCC"
+	bool "Qualcomm SM8650 Pinctrl"
 	select PINCTRL_QCOM
 	help
 	  Say Y here to enable support for pinctrl on the Snapdragon SM8650 SoC,
 	  as well as the associated GPIO driver.
 
 config PINCTRL_QCOM_X1E80100
-	bool "Qualcomm X1E80100 GCC"
+	bool "Qualcomm X1E80100 Pinctrl"
 	select PINCTRL_QCOM
 	help
 	  Say Y here to enable support for pinctrl on the Snapdragon X1E80100 SoC,
diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile
index 06d3c95f93a..94cdc6e4a62 100644
--- a/drivers/pinctrl/qcom/Makefile
+++ b/drivers/pinctrl/qcom/Makefile
@@ -5,9 +5,11 @@
 obj-$(CONFIG_PINCTRL_QCOM) += pinctrl-qcom.o
 obj-$(CONFIG_PINCTRL_QCOM_APQ8016) += pinctrl-apq8016.o
 obj-$(CONFIG_PINCTRL_QCOM_IPQ4019) += pinctrl-ipq4019.o
+obj-$(CONFIG_PINCTRL_QCOM_IPQ9574) += pinctrl-ipq9574.o
 obj-$(CONFIG_PINCTRL_QCOM_APQ8096) += pinctrl-apq8096.o
 obj-$(CONFIG_PINCTRL_QCOM_QCM2290) += pinctrl-qcm2290.o
 obj-$(CONFIG_PINCTRL_QCOM_QCS404) += pinctrl-qcs404.o
+obj-$(CONFIG_PINCTRL_QCOM_SC7280) += pinctrl-sc7280.o
 obj-$(CONFIG_PINCTRL_QCOM_SDM845) += pinctrl-sdm845.o
 obj-$(CONFIG_PINCTRL_QCOM_SM6115) += pinctrl-sm6115.o
 obj-$(CONFIG_PINCTRL_QCOM_SM8150) += pinctrl-sm8150.o
diff --git a/drivers/pinctrl/qcom/pinctrl-apq8016.c b/drivers/pinctrl/qcom/pinctrl-apq8016.c
index 0c7437822ff..9ae07d43d93 100644
--- a/drivers/pinctrl/qcom/pinctrl-apq8016.c
+++ b/drivers/pinctrl/qcom/pinctrl-apq8016.c
@@ -50,8 +50,8 @@ static const char *apq8016_get_pin_name(struct udevice *dev,
 	}
 }
 
-static unsigned int apq8016_get_function_mux(__maybe_unused unsigned int pin,
-					     unsigned int selector)
+static int apq8016_get_function_mux(__maybe_unused unsigned int pin,
+				    unsigned int selector)
 {
 	return msm_pinctrl_functions[selector].val;
 }
diff --git a/drivers/pinctrl/qcom/pinctrl-apq8096.c b/drivers/pinctrl/qcom/pinctrl-apq8096.c
index 132ece868bf..eaa927c6e22 100644
--- a/drivers/pinctrl/qcom/pinctrl-apq8096.c
+++ b/drivers/pinctrl/qcom/pinctrl-apq8096.c
@@ -43,8 +43,8 @@ static const char *apq8096_get_pin_name(struct udevice *dev,
 	}
 }
 
-static unsigned int apq8096_get_function_mux(__maybe_unused unsigned int pin,
-					     unsigned int selector)
+static int apq8096_get_function_mux(__maybe_unused unsigned int pin,
+				    unsigned int selector)
 {
 	return msm_pinctrl_functions[selector].val;
 }
diff --git a/drivers/pinctrl/qcom/pinctrl-ipq4019.c b/drivers/pinctrl/qcom/pinctrl-ipq4019.c
index 3215c677b26..dafcd494df4 100644
--- a/drivers/pinctrl/qcom/pinctrl-ipq4019.c
+++ b/drivers/pinctrl/qcom/pinctrl-ipq4019.c
@@ -311,8 +311,7 @@ static const char *ipq4019_get_pin_name(struct udevice *dev,
 	return pin_name;
 }
 
-static unsigned int ipq4019_get_function_mux(unsigned int pin,
-					     unsigned int selector)
+static int ipq4019_get_function_mux(unsigned int pin, unsigned int selector)
 {
 	unsigned int i;
 	const msm_pin_function *func = ipq4019_pin_functions + pin;
diff --git a/drivers/pinctrl/qcom/pinctrl-ipq9574.c b/drivers/pinctrl/qcom/pinctrl-ipq9574.c
new file mode 100644
index 00000000000..ce09072ae3c
--- /dev/null
+++ b/drivers/pinctrl/qcom/pinctrl-ipq9574.c
@@ -0,0 +1,226 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * pinctrl driver for Qualcomm ipq9574
+ *
+ * (C) Copyright 2025 Linaro Ltd.
+ */
+
+#include <dm.h>
+
+#include "pinctrl-qcom.h"
+
+#define MAX_PIN_NAME_LEN 32
+static char pin_name[MAX_PIN_NAME_LEN] __section(".data");
+
+enum ipq9574_functions {
+	msm_mux_blsp0_spi,
+	msm_mux_blsp0_uart,
+	msm_mux_blsp1_i2c,
+	msm_mux_blsp1_spi,
+	msm_mux_blsp1_uart,
+	msm_mux_blsp2_i2c,
+	msm_mux_blsp2_spi,
+	msm_mux_blsp2_uart,
+	msm_mux_blsp3_i2c,
+	msm_mux_blsp3_spi,
+	msm_mux_blsp3_uart,
+	msm_mux_blsp4_i2c,
+	msm_mux_blsp4_spi,
+	msm_mux_blsp4_uart,
+	msm_mux_blsp5_i2c,
+	msm_mux_blsp5_uart,
+	msm_mux_gpio,
+	msm_mux_mdc,
+	msm_mux_mdio,
+	msm_mux_pcie0_clk,
+	msm_mux_pcie0_wake,
+	msm_mux_pcie1_clk,
+	msm_mux_pcie1_wake,
+	msm_mux_pcie2_clk,
+	msm_mux_pcie2_wake,
+	msm_mux_pcie3_clk,
+	msm_mux_pcie3_wake,
+	msm_mux_qspi_data,
+	msm_mux_qspi_clk,
+	msm_mux_qspi_cs,
+	msm_mux_sdc_data,
+	msm_mux_sdc_clk,
+	msm_mux_sdc_cmd,
+	msm_mux_sdc_rclk,
+	msm_mux_NA,
+};
+
+#define MSM_PIN_FUNCTION(fname)				\
+	[msm_mux_##fname] = {#fname, msm_mux_##fname}
+
+static const struct pinctrl_function msm_pinctrl_functions[] = {
+	MSM_PIN_FUNCTION(blsp0_spi),
+	MSM_PIN_FUNCTION(blsp0_uart),
+	MSM_PIN_FUNCTION(blsp1_i2c),
+	MSM_PIN_FUNCTION(blsp1_spi),
+	MSM_PIN_FUNCTION(blsp1_uart),
+	MSM_PIN_FUNCTION(blsp2_i2c),
+	MSM_PIN_FUNCTION(blsp2_spi),
+	MSM_PIN_FUNCTION(blsp2_uart),
+	MSM_PIN_FUNCTION(blsp3_i2c),
+	MSM_PIN_FUNCTION(blsp3_spi),
+	MSM_PIN_FUNCTION(blsp3_uart),
+	MSM_PIN_FUNCTION(blsp4_i2c),
+	MSM_PIN_FUNCTION(blsp4_spi),
+	MSM_PIN_FUNCTION(blsp4_uart),
+	MSM_PIN_FUNCTION(blsp5_i2c),
+	MSM_PIN_FUNCTION(blsp5_uart),
+	MSM_PIN_FUNCTION(gpio),
+	MSM_PIN_FUNCTION(mdc),
+	MSM_PIN_FUNCTION(mdio),
+	MSM_PIN_FUNCTION(pcie0_clk),
+	MSM_PIN_FUNCTION(pcie0_wake),
+	MSM_PIN_FUNCTION(pcie1_clk),
+	MSM_PIN_FUNCTION(pcie1_wake),
+	MSM_PIN_FUNCTION(pcie2_clk),
+	MSM_PIN_FUNCTION(pcie2_wake),
+	MSM_PIN_FUNCTION(pcie3_clk),
+	MSM_PIN_FUNCTION(pcie3_wake),
+	MSM_PIN_FUNCTION(qspi_data),
+	MSM_PIN_FUNCTION(qspi_clk),
+	MSM_PIN_FUNCTION(qspi_cs),
+	MSM_PIN_FUNCTION(sdc_data),
+	MSM_PIN_FUNCTION(sdc_clk),
+	MSM_PIN_FUNCTION(sdc_cmd),
+	MSM_PIN_FUNCTION(sdc_rclk),
+};
+
+typedef unsigned int msm_pin_function[10];
+
+#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9) \
+	[id] = {        msm_mux_gpio, /* gpio mode */	\
+			msm_mux_##f1,			\
+			msm_mux_##f2,			\
+			msm_mux_##f3,			\
+			msm_mux_##f4,			\
+			msm_mux_##f5,			\
+			msm_mux_##f6,			\
+			msm_mux_##f7,			\
+			msm_mux_##f8,			\
+			msm_mux_##f9,			\
+	}
+
+static const msm_pin_function ipq9574_pin_functions[] = {
+	PINGROUP(0, sdc_data, qspi_data, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(1, sdc_data, qspi_data, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(2, sdc_data, qspi_data, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(3, sdc_data, qspi_data, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(4, sdc_cmd, qspi_cs, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(5, sdc_clk, qspi_clk, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(6, sdc_data, NA, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(7, sdc_data, NA, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(8, sdc_data, NA, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(9, sdc_data, NA, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(10, sdc_rclk, NA, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(11, blsp0_spi, blsp0_uart, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(12, blsp0_spi, blsp0_uart, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(13, blsp0_spi, blsp0_uart, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(14, blsp0_spi, blsp0_uart, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(15, blsp3_spi, blsp3_i2c, blsp3_uart, NA, NA, NA, NA, NA, NA),
+	PINGROUP(16, blsp3_spi, blsp3_i2c, blsp3_uart, NA, NA, NA, NA, NA, NA),
+	PINGROUP(17, blsp3_spi, blsp3_uart, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(18, blsp3_spi, blsp3_uart, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(19, blsp3_spi, NA, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(20, blsp3_spi, NA, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(21, blsp3_spi, NA, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(22, pcie0_clk, NA, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(23, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(24, pcie0_wake, NA, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(25, pcie1_clk, NA, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(26, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(27, pcie1_wake, NA, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(28, pcie2_clk, NA, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(29, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(30, pcie2_wake, NA, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(31, pcie3_clk, NA, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(32, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(33, pcie3_wake, NA, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(34, blsp2_uart, blsp2_i2c, blsp2_spi, blsp1_uart, NA, NA, NA, NA, NA),
+	PINGROUP(35, blsp2_uart, blsp2_i2c, blsp2_spi, blsp1_uart, NA, NA, NA, NA, NA),
+	PINGROUP(36, blsp1_uart, blsp1_i2c, blsp2_spi, NA, NA, NA, NA, NA, NA),
+	PINGROUP(37, blsp1_uart, blsp1_i2c, blsp2_spi, NA, NA, NA, NA, NA, NA),
+	PINGROUP(38, mdc, NA, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(39, mdio, NA, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(40, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(41, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(42, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(43, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(44, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(45, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(46, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(47, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(48, blsp5_i2c, blsp5_uart, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(49, blsp5_i2c, blsp5_uart, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(50, blsp4_uart, blsp4_i2c, blsp4_spi, NA, NA, NA, NA, NA, NA),
+	PINGROUP(51, blsp4_uart, blsp4_i2c, blsp4_spi, NA, NA, NA, NA, NA, NA),
+	PINGROUP(52, blsp4_uart, blsp4_spi, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(53, blsp4_uart, blsp4_spi, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(54, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(55, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(56, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(57, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(58, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(59, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(60, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(61, blsp1_spi, NA, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(62, blsp1_spi, NA, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(63, blsp1_spi, NA, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(64, blsp1_spi, NA, NA, NA, NA, NA, NA, NA, NA),
+};
+
+static const char *ipq9574_get_function_name(struct udevice *dev,
+					     unsigned int selector)
+{
+	return msm_pinctrl_functions[selector].name;
+}
+
+static const char *ipq9574_get_pin_name(struct udevice *dev,
+					unsigned int selector)
+{
+	snprintf(pin_name, MAX_PIN_NAME_LEN, "gpio%u", selector);
+	return pin_name;
+}
+
+static int ipq9574_get_function_mux(unsigned int pin, unsigned int selector)
+{
+	unsigned int i;
+	const msm_pin_function *func = ipq9574_pin_functions + pin;
+
+	for (i = 0; i < 10; i++)
+		if ((*func)[i] == selector)
+			return i;
+
+	debug("Can't find requested function for pin:selector %u:%u\n",
+	      pin, selector);
+
+	return -EINVAL;
+}
+
+static const struct msm_pinctrl_data ipq9574_data = {
+	.pin_data = {
+		.pin_count = 65,
+	},
+	.functions_count = ARRAY_SIZE(msm_pinctrl_functions),
+	.get_function_name = ipq9574_get_function_name,
+	.get_function_mux = ipq9574_get_function_mux,
+	.get_pin_name = ipq9574_get_pin_name,
+};
+
+static const struct udevice_id msm_pinctrl_ids[] = {
+	{ .compatible = "qcom,ipq9574-tlmm", .data = (ulong)&ipq9574_data },
+	{ /* Sentinal */ }
+};
+
+U_BOOT_DRIVER(pinctrl_ipq9574) = {
+	.name		= "pinctrl_ipq9574",
+	.id		= UCLASS_NOP,
+	.of_match	= msm_pinctrl_ids,
+	.ops		= &msm_pinctrl_ops,
+	.bind		= msm_pinctrl_bind,
+	.flags = DM_FLAG_PRE_RELOC,
+};
diff --git a/drivers/pinctrl/qcom/pinctrl-qcm2290.c b/drivers/pinctrl/qcom/pinctrl-qcm2290.c
index af969e177d7..0c2222ce663 100644
--- a/drivers/pinctrl/qcom/pinctrl-qcm2290.c
+++ b/drivers/pinctrl/qcom/pinctrl-qcm2290.c
@@ -38,7 +38,7 @@ static const char *qcm2290_get_pin_name(struct udevice *dev, unsigned int select
 	return pin_name;
 }
 
-static unsigned int qcm2290_get_function_mux(__maybe_unused unsigned int pin, unsigned int selector)
+static int qcm2290_get_function_mux(__maybe_unused unsigned int pin, unsigned int selector)
 {
 	return msm_pinctrl_functions[selector].val;
 }
diff --git a/drivers/pinctrl/qcom/pinctrl-qcom.c b/drivers/pinctrl/qcom/pinctrl-qcom.c
index 26a3fba194a..24d031947a3 100644
--- a/drivers/pinctrl/qcom/pinctrl-qcom.c
+++ b/drivers/pinctrl/qcom/pinctrl-qcom.c
@@ -92,7 +92,10 @@ static int msm_pinmux_set(struct udevice *dev, unsigned int pin_selector,
 			  unsigned int func_selector)
 {
 	struct msm_pinctrl_priv *priv = dev_get_priv(dev);
-	u32 func = priv->data->get_function_mux(pin_selector, func_selector);
+	int func = priv->data->get_function_mux(pin_selector, func_selector);
+
+	if (func < 0)
+		return func;
 
 	/* Always NOP for special pins, assume they're in the correct state */
 	if (qcom_is_special_pin(&priv->data->pin_data, pin_selector))
diff --git a/drivers/pinctrl/qcom/pinctrl-qcom.h b/drivers/pinctrl/qcom/pinctrl-qcom.h
index 49b7bfbc001..cd167e63868 100644
--- a/drivers/pinctrl/qcom/pinctrl-qcom.h
+++ b/drivers/pinctrl/qcom/pinctrl-qcom.h
@@ -18,8 +18,7 @@ struct msm_pinctrl_data {
 	int functions_count;
 	const char *(*get_function_name)(struct udevice *dev,
 					 unsigned int selector);
-	unsigned int (*get_function_mux)(unsigned int pin,
-					 unsigned int selector);
+	int (*get_function_mux)(unsigned int pin, unsigned int selector);
 	const char *(*get_pin_name)(struct udevice *dev,
 				    unsigned int selector);
 };
diff --git a/drivers/pinctrl/qcom/pinctrl-qcs404.c b/drivers/pinctrl/qcom/pinctrl-qcs404.c
index fb6defaeddf..c272595aa2a 100644
--- a/drivers/pinctrl/qcom/pinctrl-qcs404.c
+++ b/drivers/pinctrl/qcom/pinctrl-qcs404.c
@@ -93,8 +93,8 @@ static const char *qcs404_get_pin_name(struct udevice *dev,
 	}
 }
 
-static unsigned int qcs404_get_function_mux(__maybe_unused unsigned int pin,
-					    unsigned int selector)
+static int qcs404_get_function_mux(__maybe_unused unsigned int pin,
+				   unsigned int selector)
 {
 	return msm_pinctrl_functions[selector].val;
 }
diff --git a/drivers/pinctrl/qcom/pinctrl-sc7280.c b/drivers/pinctrl/qcom/pinctrl-sc7280.c
new file mode 100644
index 00000000000..fe87947fbbf
--- /dev/null
+++ b/drivers/pinctrl/qcom/pinctrl-sc7280.c
@@ -0,0 +1,106 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Qualcomm sc7280 pinctrl
+ *
+ * (C) Copyright 2024 Linaro Ltd.
+ *
+ */
+
+#include <dm.h>
+
+#include "pinctrl-qcom.h"
+
+#define WEST 0x00000000
+#define SOUTH 0x00400000
+#define NORTH 0x00800000
+
+#define MAX_PIN_NAME_LEN 32
+static char pin_name[MAX_PIN_NAME_LEN] __section(".data");
+
+static const struct pinctrl_function msm_pinctrl_functions[] = {
+	{ "qup05", 1 },
+	{ "gpio", 0 },
+	{ "pcie1_clkreqn", 3},
+};
+#define SDC_PINGROUP(pg_name, ctl, pull, drv)		\
+	{						\
+		.name = pg_name,			\
+		.ctl_reg = ctl,				\
+		.io_reg = 0,				\
+		.pull_bit = pull,			\
+		.drv_bit = drv,				\
+		.oe_bit = -1,				\
+		.in_bit = -1,				\
+		.out_bit = -1,				\
+	}
+
+#define UFS_RESET(pg_name, offset)			\
+	{						\
+		.name = pg_name,			\
+		.ctl_reg = offset,			\
+		.io_reg = offset + 0x4,			\
+		.pull_bit = 3,				\
+		.drv_bit = 0,				\
+		.oe_bit = -1,				\
+		.in_bit = -1,				\
+		.out_bit = 0,				\
+	}
+
+static const struct msm_special_pin_data sc7280_special_pins_data[] = {
+	[0] = UFS_RESET("ufs_reset", SOUTH + 0xbe000),
+	[1] = SDC_PINGROUP("sdc1_rclk", 0xb3004, 0, 6),
+	[2] = SDC_PINGROUP("sdc1_clk", 0xb3000, 13, 6),
+	[3] = SDC_PINGROUP("sdc1_cmd", 0xb3000, 11, 3),
+	[4] = SDC_PINGROUP("sdc1_data", 0xb3000, 9, 0),
+	[5] = SDC_PINGROUP("sdc2_clk", 0xb4000, 14, 6),
+	[6] = SDC_PINGROUP("sdc2_cmd", 0xb4000, 11, 3),
+	[7] = SDC_PINGROUP("sdc2_data", 0xb4000, 9, 0),
+};
+
+static const char *sc7280_get_function_name(struct udevice *dev, unsigned int selector)
+{
+	return msm_pinctrl_functions[selector].name;
+}
+
+static const char *sc7280_get_pin_name(struct udevice *dev, unsigned int selector)
+{
+	if (selector >= 175 && selector <= 182)
+		snprintf(pin_name, MAX_PIN_NAME_LEN,
+			 sc7280_special_pins_data[selector - 175].name);
+	else
+		snprintf(pin_name, MAX_PIN_NAME_LEN, "gpio%u", selector);
+
+	return pin_name;
+}
+
+static int sc7280_get_function_mux(__maybe_unused unsigned int pin, unsigned int selector)
+{
+	return msm_pinctrl_functions[selector].val;
+}
+
+static struct msm_pinctrl_data sc7280_data = {
+	.pin_data = {
+		.pin_count = 183,
+		.special_pins_start = 175,
+		.special_pins_data = sc7280_special_pins_data,
+	},
+	.functions_count = ARRAY_SIZE(msm_pinctrl_functions),
+	.get_function_name = sc7280_get_function_name,
+	.get_function_mux = sc7280_get_function_mux,
+	.get_pin_name = sc7280_get_pin_name,
+};
+
+static const struct udevice_id msm_pinctrl_ids[] = {
+	{
+		.compatible = "qcom,sc7280-pinctrl",
+		.data = (ulong)&sc7280_data
+	},
+	{ /* Sentinel */ } };
+
+U_BOOT_DRIVER(pinctrl_sc7280) = {
+	.name = "pinctrl_sc7280",
+	.id = UCLASS_NOP,
+	.of_match = msm_pinctrl_ids,
+	.ops = &msm_pinctrl_ops,
+	.bind = msm_pinctrl_bind,
+};
diff --git a/drivers/pinctrl/qcom/pinctrl-sdm845.c b/drivers/pinctrl/qcom/pinctrl-sdm845.c
index f1a23f51099..3f55fc81c8e 100644
--- a/drivers/pinctrl/qcom/pinctrl-sdm845.c
+++ b/drivers/pinctrl/qcom/pinctrl-sdm845.c
@@ -80,8 +80,8 @@ static const char *sdm845_get_pin_name(struct udevice *dev,
 	return pin_name;
 }
 
-static unsigned int sdm845_get_function_mux(__maybe_unused unsigned int pin,
-					    unsigned int selector)
+static int sdm845_get_function_mux(__maybe_unused unsigned int pin,
+				   unsigned int selector)
 {
 	return msm_pinctrl_functions[selector].val;
 }
diff --git a/drivers/pinctrl/qcom/pinctrl-sm6115.c b/drivers/pinctrl/qcom/pinctrl-sm6115.c
index f07f39f4ac3..7e80ea39a12 100644
--- a/drivers/pinctrl/qcom/pinctrl-sm6115.c
+++ b/drivers/pinctrl/qcom/pinctrl-sm6115.c
@@ -167,7 +167,7 @@ static const char *sm6115_get_pin_name(struct udevice *dev, unsigned int selecto
 	return pin_name;
 }
 
-static unsigned int sm6115_get_function_mux(__maybe_unused unsigned int pin, unsigned int selector)
+static int sm6115_get_function_mux(__maybe_unused unsigned int pin, unsigned int selector)
 {
 	return msm_pinctrl_functions[selector].val;
 }
diff --git a/drivers/pinctrl/qcom/pinctrl-sm8150.c b/drivers/pinctrl/qcom/pinctrl-sm8150.c
index 1fb2ffb9597..fe789e8639b 100644
--- a/drivers/pinctrl/qcom/pinctrl-sm8150.c
+++ b/drivers/pinctrl/qcom/pinctrl-sm8150.c
@@ -123,8 +123,8 @@ static const char *sm8150_get_pin_name(struct udevice *dev,
 	return pin_name;
 }
 
-static unsigned int sm8150_get_function_mux(__maybe_unused unsigned int pin,
-					    unsigned int selector)
+static int sm8150_get_function_mux(__maybe_unused unsigned int pin,
+				   unsigned int selector)
 {
 	return msm_pinctrl_functions[selector].val;
 }
diff --git a/drivers/pinctrl/qcom/pinctrl-sm8250.c b/drivers/pinctrl/qcom/pinctrl-sm8250.c
index b21cdc4d24b..d5447651695 100644
--- a/drivers/pinctrl/qcom/pinctrl-sm8250.c
+++ b/drivers/pinctrl/qcom/pinctrl-sm8250.c
@@ -99,7 +99,7 @@ static const char *sm8250_get_pin_name(struct udevice *dev, unsigned int selecto
 	return pin_name;
 }
 
-static unsigned int sm8250_get_function_mux(__maybe_unused unsigned int pin, unsigned int selector)
+static int sm8250_get_function_mux(__maybe_unused unsigned int pin, unsigned int selector)
 {
 	return msm_pinctrl_functions[selector].val;
 }
diff --git a/drivers/pinctrl/qcom/pinctrl-sm8550.c b/drivers/pinctrl/qcom/pinctrl-sm8550.c
index 25b972a6d82..f7fcad0e4aa 100644
--- a/drivers/pinctrl/qcom/pinctrl-sm8550.c
+++ b/drivers/pinctrl/qcom/pinctrl-sm8550.c
@@ -68,8 +68,8 @@ static const char *sm8550_get_pin_name(struct udevice *dev,
 	return pin_name;
 }
 
-static unsigned int sm8550_get_function_mux(__maybe_unused unsigned int pin,
-					    unsigned int selector)
+static int sm8550_get_function_mux(__maybe_unused unsigned int pin,
+				   unsigned int selector)
 {
 	return msm_pinctrl_functions[selector].val;
 }
diff --git a/drivers/pinctrl/qcom/pinctrl-sm8650.c b/drivers/pinctrl/qcom/pinctrl-sm8650.c
index 9146d6abd9a..6b9d56b1058 100644
--- a/drivers/pinctrl/qcom/pinctrl-sm8650.c
+++ b/drivers/pinctrl/qcom/pinctrl-sm8650.c
@@ -69,8 +69,8 @@ static const char *sm8650_get_pin_name(struct udevice *dev,
 	return pin_name;
 }
 
-static unsigned int sm8650_get_function_mux(__maybe_unused unsigned int pin,
-					    unsigned int selector)
+static int sm8650_get_function_mux(__maybe_unused unsigned int pin,
+				   unsigned int selector)
 {
 	return msm_pinctrl_functions[selector].val;
 }
diff --git a/drivers/pinctrl/qcom/pinctrl-x1e80100.c b/drivers/pinctrl/qcom/pinctrl-x1e80100.c
index f39dc426d68..319667bfc16 100644
--- a/drivers/pinctrl/qcom/pinctrl-x1e80100.c
+++ b/drivers/pinctrl/qcom/pinctrl-x1e80100.c
@@ -72,8 +72,8 @@ static const char *x1e80100_get_pin_name(struct udevice *dev,
 	return pin_name;
 }
 
-static unsigned int x1e80100_get_function_mux(__maybe_unused unsigned int pin,
-					      unsigned int selector)
+static int x1e80100_get_function_mux(__maybe_unused unsigned int pin,
+				     unsigned int selector)
 {
 	return msm_pinctrl_functions[selector].val;
 }
diff --git a/drivers/pinctrl/sunxi/Kconfig b/drivers/pinctrl/sunxi/Kconfig
index cbd61795986..65e8192a99a 100644
--- a/drivers/pinctrl/sunxi/Kconfig
+++ b/drivers/pinctrl/sunxi/Kconfig
@@ -124,6 +124,16 @@ config PINCTRL_SUN50I_H616_R
 	default MACH_SUN50I_H616
 	select PINCTRL_SUNXI
 
+config PINCTRL_SUN50I_A100
+	bool "Support for the Allwinner A100/A133 PIO"
+	default MACH_SUN50I_A133
+	select PINCTRL_SUNXI
+
+config PINCTRL_SUN50I_A100_R
+	bool "Support for the Allwinner A100/A133 R-PIO"
+	default MACH_SUN50I_A133
+	select PINCTRL_SUNXI
+
 config PINCTRL_SUN20I_D1
 	bool "Support for the Allwinner D1/R528 PIO"
 	default MACH_SUN8I_R528
diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.c b/drivers/pinctrl/sunxi/pinctrl-sunxi.c
index 37ea93715d1..c38edf7d4f5 100644
--- a/drivers/pinctrl/sunxi/pinctrl-sunxi.c
+++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.c
@@ -774,6 +774,41 @@ static const struct sunxi_pinctrl_desc __maybe_unused sun50i_h616_r_pinctrl_desc
 	.num_banks	= 1,
 };
 
+static const struct sunxi_pinctrl_function sun50i_a100_pinctrl_functions[] = {
+	{ "emac0",	5 },	/* PH0-PH16 */
+	{ "gpio_in",	0 },
+	{ "gpio_out",	1 },
+	{ "mmc0",	2 },	/* PF0-PF5 */
+	{ "mmc1",	2 },	/* PG0-PG5 */
+	{ "mmc2",	3 },	/* PC0-PC16 */
+	{ "spi0",	4 },	/* PC2-PC4, PC7, PC12, PC15-PC16 */
+#if IS_ENABLED(CONFIG_UART0_PORT_F)
+	{ "uart0",	3 },	/* PF2-PF4 */
+#else
+	{ "uart0",	2 },	/* PB9-PB10 */
+#endif
+};
+
+static const struct sunxi_pinctrl_desc __maybe_unused sun50i_a100_pinctrl_desc = {
+	.functions	= sun50i_a100_pinctrl_functions,
+	.num_functions	= ARRAY_SIZE(sun50i_a100_pinctrl_functions),
+	.first_bank	= SUNXI_GPIO_A,
+	.num_banks	= 8,
+};
+
+static const struct sunxi_pinctrl_function sun50i_a100_r_pinctrl_functions[] = {
+	{ "gpio_in",	0 },
+	{ "gpio_out",	1 },
+	{ "s_i2c0",	2 },
+};
+
+static const struct sunxi_pinctrl_desc __maybe_unused sun50i_a100_r_pinctrl_desc = {
+	.functions	= sun50i_a100_r_pinctrl_functions,
+	.num_functions	= ARRAY_SIZE(sun50i_a100_r_pinctrl_functions),
+	.first_bank	= SUNXI_GPIO_L,
+	.num_banks	= 1,
+};
+
 static const struct udevice_id sunxi_pinctrl_ids[] = {
 #ifdef CONFIG_PINCTRL_SUNIV_F1C100S
 	{
@@ -937,6 +972,18 @@ static const struct udevice_id sunxi_pinctrl_ids[] = {
 		.data = (ulong)&sun50i_h616_r_pinctrl_desc,
 	},
 #endif
+#ifdef CONFIG_PINCTRL_SUN50I_A100
+	{
+		.compatible = "allwinner,sun50i-a100-pinctrl",
+		.data = (ulong)&sun50i_a100_pinctrl_desc,
+	},
+#endif
+#ifdef CONFIG_PINCTRL_SUN50I_A100_R
+	{
+		.compatible = "allwinner,sun50i-a100-r-pinctrl",
+		.data = (ulong)&sun50i_a100_r_pinctrl_desc,
+	},
+#endif
 	{}
 };
 
diff --git a/drivers/pinctrl/tegra/pinctrl-tegra.c b/drivers/pinctrl/tegra/pinctrl-tegra.c
index ad7112a05e6..b04be168bc8 100644
--- a/drivers/pinctrl/tegra/pinctrl-tegra.c
+++ b/drivers/pinctrl/tegra/pinctrl-tegra.c
@@ -23,18 +23,18 @@ static void tegra_pinctrl_set_drive(struct udevice *config, int drvcnt)
 		return;
 	}
 
-	drive_group[0].slwf = dev_read_u32_default(config, "nvidia,slew-rate-falling", 0);
-	drive_group[0].slwr = dev_read_u32_default(config, "nvidia,slew-rate-rising", 0);
-	drive_group[0].drvup = dev_read_u32_default(config, "nvidia,pull-up-strength", 0);
-	drive_group[0].drvdn = dev_read_u32_default(config, "nvidia,pull-down-strength", 0);
+	drive_group[0].slwf = dev_read_u32_default(config, "nvidia,slew-rate-falling", PMUX_SLWF_NONE);
+	drive_group[0].slwr = dev_read_u32_default(config, "nvidia,slew-rate-rising", PMUX_SLWR_NONE);
+	drive_group[0].drvup = dev_read_u32_default(config, "nvidia,pull-up-strength", PMUX_DRVUP_NONE);
+	drive_group[0].drvdn = dev_read_u32_default(config, "nvidia,pull-down-strength", PMUX_DRVDN_NONE);
 #ifdef TEGRA_PMX_GRPS_HAVE_LPMD
-	drive_group[0].lpmd = dev_read_u32_default(config, "nvidia,low-power-mode", 0);
+	drive_group[0].lpmd = dev_read_u32_default(config, "nvidia,low-power-mode", PMUX_LPMD_NONE);
 #endif
 #ifdef TEGRA_PMX_GRPS_HAVE_SCHMT
-	drive_group[0].schmt = dev_read_u32_default(config, "nvidia,schmitt", 0);
+	drive_group[0].schmt = dev_read_u32_default(config, "nvidia,schmitt", PMUX_SCHMT_NONE);
 #endif
 #ifdef TEGRA_PMX_GRPS_HAVE_HSM
-	drive_group[0].hsm = dev_read_u32_default(config, "nvidia,high-speed-mode", 0);
+	drive_group[0].hsm = dev_read_u32_default(config, "nvidia,high-speed-mode", PMUX_HSM_NONE);
 #endif
 
 	for (i = 1; i < drvcnt; i++)
@@ -67,6 +67,58 @@ exit:
 	kfree(drive_group);
 }
 
+#ifdef TEGRA_PMX_SOC_HAS_MIPI_PAD_CTRL_GRPS
+static void tegra_pinctrl_set_mipipad(struct udevice *config, int padcnt)
+{
+	struct pmux_mipipadctrlgrp_config *mipipad_group;
+	int i, ret, pad_id;
+	const char *function;
+	const char **pads;
+
+	mipipad_group = kmalloc_array(padcnt, sizeof(*mipipad_group), GFP_KERNEL);
+	if (!mipipad_group) {
+		log_debug("%s: cannot allocate mipi pad group array\n", __func__);
+		return;
+	}
+
+	/* decode function id and fill the first copy of pmux_mipipadctrlgrp_config */
+	function = dev_read_string(config, "nvidia,function");
+	if (function)
+		for (i = 0; i < PMUX_FUNC_COUNT; i++)
+			if (tegra_pinctrl_to_func[i])
+				if (!strcmp(function, tegra_pinctrl_to_func[i]))
+					break;
+
+	mipipad_group[0].func = i;
+
+	for (i = 1; i < padcnt; i++)
+		memcpy(&mipipad_group[i], &mipipad_group[0], sizeof(mipipad_group[0]));
+
+	ret = dev_read_string_list(config, "nvidia,pins", &pads);
+	if (ret < 0) {
+		log_debug("%s: could not parse property nvidia,pins\n", __func__);
+		goto exit;
+	}
+
+	for (i = 0; i < padcnt; i++) {
+		for (pad_id = 0; pad_id < PMUX_MIPIPADCTRLGRP_COUNT; pad_id++)
+			if (tegra_pinctrl_to_mipipadgrp[pad_id])
+				if (!strcmp(pads[i], tegra_pinctrl_to_mipipadgrp[pad_id])) {
+					mipipad_group[i].grp = pad_id;
+					break;
+				}
+	}
+
+	pinmux_config_mipipadctrlgrp_table(mipipad_group, padcnt);
+
+	free(pads);
+exit:
+	kfree(mipipad_group);
+}
+#else
+static void tegra_pinctrl_set_mipipad(struct udevice *config, int padcnt) { }
+#endif
+
 static void tegra_pinctrl_set_pin(struct udevice *config, int pincnt)
 {
 	struct pmux_pingrp_config *pinmux_group;
@@ -90,31 +142,31 @@ static void tegra_pinctrl_set_pin(struct udevice *config, int pincnt)
 
 	pinmux_group[0].func = i;
 
-	pinmux_group[0].pull = dev_read_u32_default(config, "nvidia,pull", 0);
-	pinmux_group[0].tristate = dev_read_u32_default(config, "nvidia,tristate", 0);
+	pinmux_group[0].pull = dev_read_u32_default(config, "nvidia,pull", PMUX_PULL_NORMAL);
+	pinmux_group[0].tristate = dev_read_u32_default(config, "nvidia,tristate", PMUX_TRI_TRISTATE);
 #ifdef TEGRA_PMX_PINS_HAVE_E_INPUT
-	pinmux_group[0].io = dev_read_u32_default(config, "nvidia,enable-input", 0);
+	pinmux_group[0].io = dev_read_u32_default(config, "nvidia,enable-input", PMUX_PIN_NONE);
 #endif
 #ifdef TEGRA_PMX_PINS_HAVE_LOCK
-	pinmux_group[0].lock = dev_read_u32_default(config, "nvidia,lock", 0);
+	pinmux_group[0].lock = dev_read_u32_default(config, "nvidia,lock", PMUX_PIN_LOCK_DEFAULT);
 #endif
 #ifdef TEGRA_PMX_PINS_HAVE_OD
-	pinmux_group[0].od = dev_read_u32_default(config, "nvidia,open-drain", 0);
+	pinmux_group[0].od = dev_read_u32_default(config, "nvidia,open-drain", PMUX_PIN_OD_DEFAULT);
 #endif
 #ifdef TEGRA_PMX_PINS_HAVE_IO_RESET
-	pinmux_group[0].ioreset = dev_read_u32_default(config, "nvidia,io-reset", 0);
+	pinmux_group[0].ioreset = dev_read_u32_default(config, "nvidia,io-reset", PMUX_PIN_IO_RESET_DEFAULT);
 #endif
 #ifdef TEGRA_PMX_PINS_HAVE_RCV_SEL
-	pinmux_group[0].rcv_sel = dev_read_u32_default(config, "nvidia,rcv-sel", 0);
+	pinmux_group[0].rcv_sel = dev_read_u32_default(config, "nvidia,rcv-sel", PMUX_PIN_RCV_SEL_DEFAULT);
 #endif
 #ifdef TEGRA_PMX_PINS_HAVE_E_IO_HV
-	pinmux_group[0].e_io_hv = dev_read_u32_default(config, "nvidia,io-hv", 0);
+	pinmux_group[0].e_io_hv = dev_read_u32_default(config, "nvidia,io-hv", PMUX_PIN_E_IO_HV_DEFAULT);
 #endif
 #ifdef TEGRA_PMX_PINS_HAVE_SCHMT
-	pinmux_group[0].schmt = dev_read_u32_default(config, "nvidia,schmitt", 0);
+	pinmux_group[0].schmt = dev_read_u32_default(config, "nvidia,schmitt", PMUX_SCHMT_NONE);
 #endif
 #ifdef TEGRA_PMX_PINS_HAVE_HSM
-	pinmux_group[0].hsm = dev_read_u32_default(config, "nvidia,high-speed-mode", 0);
+	pinmux_group[0].hsm = dev_read_u32_default(config, "nvidia,high-speed-mode", PMUX_HSM_NONE);
 #endif
 
 	for (i = 1; i < pincnt; i++)
@@ -170,6 +222,9 @@ static int tegra_pinctrl_set_state(struct udevice *dev, struct udevice *config)
 		if (!strncmp(name, "drive_", 6))
 			/* Drive node is detected */
 			tegra_pinctrl_set_drive(child, ret);
+		else if (!strncmp(name, "mipi_pad_ctrl_", 14))
+			/* Handle T124 specific pinconfig */
+			tegra_pinctrl_set_mipipad(child, ret);
 		else
 			/* Pin node is detected */
 			tegra_pinctrl_set_pin(child, ret);
@@ -236,6 +291,7 @@ static int tegra_pinctrl_bind(struct udevice *dev)
 static const struct udevice_id tegra_pinctrl_ids[] = {
 	{ .compatible = "nvidia,tegra30-pinmux" },
 	{ .compatible = "nvidia,tegra114-pinmux" },
+	{ .compatible = "nvidia,tegra124-pinmux" },
 	{ },
 };
 
diff --git a/drivers/power/Kconfig b/drivers/power/Kconfig
index 4b81aeb7497..eed65058e66 100644
--- a/drivers/power/Kconfig
+++ b/drivers/power/Kconfig
@@ -116,6 +116,12 @@ config AXP717_POWER
 	---help---
 	Select this to enable support for the AXP717 PMIC found on some boards.
 
+config AXP803_POWER
+	bool "AXP803 PMIC support"
+	select AXP_PMIC_BUS
+	---help---
+	Select this to enable support for the AXP803 PMIC found on some boards.
+
 config AXP809_POWER
 	bool "axp809 pmic support"
 	depends on MACH_SUN9I
@@ -142,10 +148,20 @@ config SY8106A_POWER
 
 endchoice
 
+config AXP_I2C_ADDRESS
+	hex "AXP PMIC I2C address"
+	depends on ARCH_SUNXI && !SUNXI_NO_PMIC
+	default 0x36 if AXP305_POWER
+	default 0x36 if AXP313_POWER
+	default 0x30 if AXP152_POWER
+	default 0x34
+	---help---
+	I2C address of the AXP PMIC, used for the SPL only.
+
 config AXP_DCDC1_VOLT
 	int "axp pmic dcdc1 voltage"
-	depends on AXP221_POWER || AXP809_POWER || AXP818_POWER
-	default 3300 if AXP818_POWER || MACH_SUN8I_R40
+	depends on AXP221_POWER || AXP809_POWER || AXP818_POWER || AXP803_POWER
+	default 3300 if AXP818_POWER || MACH_SUN8I_R40 || AXP803_POWER
 	default 3000 if MACH_SUN6I || MACH_SUN8I || MACH_SUN9I
 	---help---
 	Set the voltage (mV) to program the axp pmic dcdc1 at, set to 0 to
@@ -158,11 +174,12 @@ config AXP_DCDC1_VOLT
 
 config AXP_DCDC2_VOLT
 	int "axp pmic dcdc2 voltage"
-	depends on AXP152_POWER || AXP209_POWER || AXP221_POWER || AXP809_POWER || AXP818_POWER || AXP313_POWER || AXP717_POWER
+	depends on AXP152_POWER || AXP209_POWER || AXP221_POWER || AXP809_POWER || AXP818_POWER || AXP313_POWER || AXP717_POWER || AXP803_POWER
 	default 900 if AXP818_POWER
 	default 1400 if AXP152_POWER || AXP209_POWER
 	default 1000 if AXP313_POWER
 	default 1000 if AXP717_POWER
+	default 1000 if AXP803_POWER
 	default 1200 if MACH_SUN6I
 	default 1100 if MACH_SUN8I
 	default 0 if MACH_SUN9I
@@ -219,7 +236,7 @@ config AXP_DCDC4_VOLT
 
 config AXP_DCDC5_VOLT
 	int "axp pmic dcdc5 voltage"
-	depends on AXP221_POWER || AXP809_POWER || AXP818_POWER
+	depends on AXP221_POWER || AXP809_POWER || AXP818_POWER || AXP803_POWER
 	default 1500 if MACH_SUN6I || MACH_SUN8I || MACH_SUN9I
 	---help---
 	Set the voltage (mV) to program the axp pmic dcdc5 at, set to 0 to
diff --git a/drivers/power/Makefile b/drivers/power/Makefile
index 3f4d56f5139..3363191fdc8 100644
--- a/drivers/power/Makefile
+++ b/drivers/power/Makefile
@@ -17,6 +17,7 @@ obj-$(CONFIG_AXP313_POWER)	+= axp_spl.o
 obj-$(CONFIG_AXP717_POWER)	+= axp_spl.o
 obj-$(CONFIG_AXP809_POWER)	+= axp809.o
 obj-$(CONFIG_AXP818_POWER)	+= axp818.o
+obj-$(CONFIG_AXP803_POWER)	+= axp_spl.o
 endif
 obj-$(CONFIG_EXYNOS_TMU)	+= exynos-tmu.o
 obj-$(CONFIG_SY8106A_POWER)	+= sy8106a.o
diff --git a/drivers/power/axp_spl.c b/drivers/power/axp_spl.c
index 3c86eb20ab4..7c51a9b3dfb 100644
--- a/drivers/power/axp_spl.c
+++ b/drivers/power/axp_spl.c
@@ -36,6 +36,23 @@ static const struct axp_reg_desc_spl axp_spl_dcdc_regulators[] = {
 #define AXP_SHUTDOWN_REG	0x27
 #define AXP_SHUTDOWN_MASK	BIT(0)
 
+#elif defined(CONFIG_AXP803_POWER)				/* AXP803 */
+
+static const struct axp_reg_desc_spl axp_spl_dcdc_regulators[] = {
+	{ 0x10, BIT(0), 0x20, 0x1f, 1600, 3400, 100, NA },
+	{ 0x10, BIT(1), 0x21, 0x7f,  500, 1300,  10, 70 },
+	{ 0x10, BIT(2), 0x22, 0x7f,  500, 1300,  10, 70 },
+	{ 0x10, BIT(3), 0x23, 0x7f,  500, 1300,  10, 70 },
+	{ 0x10, BIT(4), 0x24, 0x7f,  800, 1840,  10, 32 },
+	{ 0x10, BIT(5), 0x25, 0x7f,  600, 1520,  10, 50 },
+};
+
+#define AXP_CHIP_VERSION	0x3
+#define AXP_CHIP_VERSION_MASK	0xcf
+#define AXP_CHIP_ID		0x41
+#define AXP_SHUTDOWN_REG	0x32
+#define AXP_SHUTDOWN_MASK	BIT(7)
+
 #elif defined(CONFIG_AXP313_POWER)				/* AXP313 */
 
 static const struct axp_reg_desc_spl axp_spl_dcdc_regulators[] = {
diff --git a/drivers/power/domain/ti-power-domain.c b/drivers/power/domain/ti-power-domain.c
index 5e7a4c5648d..c3519307340 100644
--- a/drivers/power/domain/ti-power-domain.c
+++ b/drivers/power/domain/ti-power-domain.c
@@ -94,6 +94,8 @@ static const struct soc_attr ti_k3_soc_pd_data[] = {
 		.family = "J721E",
 		.data = &j721e_pd_platdata,
 	},
+#endif
+#if IS_ENABLED(CONFIG_SOC_K3_J7200)
 	{
 		.family = "J7200",
 		.data = &j7200_pd_platdata,
@@ -116,6 +118,10 @@ static const struct soc_attr ti_k3_soc_pd_data[] = {
 		.family = "J784S4",
 		.data = &j784s4_pd_platdata,
 	},
+	{
+		.family = "J742S2",
+		.data = &j784s4_pd_platdata,
+	},
 #endif
 	{ /* sentinel */ }
 };
diff --git a/drivers/power/regulator/Kconfig b/drivers/power/regulator/Kconfig
index 958f337c7e7..8f102a92c23 100644
--- a/drivers/power/regulator/Kconfig
+++ b/drivers/power/regulator/Kconfig
@@ -478,3 +478,11 @@ config DM_REGULATOR_TPS65219
 	features for REGULATOR TPS65219 and the family of TPS65219 PMICs.
 	TPS65219 series of PMICs have 3 single phase BUCKs & 4 LDOs.
 	The driver implements get/set api for value and enable.
+
+config REGULATOR_RZG2L_USBPHY
+	bool "Enable driver for RZ/G2L USB PHY VBUS supply"
+	depends on DM_REGULATOR
+	help
+	  Enable this option to support controlling the VBUS supply in
+	  the USB PHY peripheral of the Renesas RZ/G2L SoC. This option
+	  is required in order to use the USB OTG port.
diff --git a/drivers/power/regulator/Makefile b/drivers/power/regulator/Makefile
index ca6c89d13b5..4382d4b3ab9 100644
--- a/drivers/power/regulator/Makefile
+++ b/drivers/power/regulator/Makefile
@@ -42,3 +42,4 @@ obj-$(CONFIG_DM_REGULATOR_TPS65941) += tps65941_regulator.o
 obj-$(CONFIG_DM_REGULATOR_SCMI) += scmi_regulator.o
 obj-$(CONFIG_$(XPL_)DM_REGULATOR_ANATOP) += anatop_regulator.o
 obj-$(CONFIG_DM_REGULATOR_TPS65219) += tps65219_regulator.o
+obj-$(CONFIG_REGULATOR_RZG2L_USBPHY) += rzg2l-usbphy-regulator.o
diff --git a/drivers/power/regulator/rzg2l-usbphy-regulator.c b/drivers/power/regulator/rzg2l-usbphy-regulator.c
new file mode 100644
index 00000000000..451f04c140e
--- /dev/null
+++ b/drivers/power/regulator/rzg2l-usbphy-regulator.c
@@ -0,0 +1,42 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2024 Renesas Electronics Corporation
+ */
+
+#include <asm/io.h>
+#include <dm.h>
+#include <power/regulator.h>
+#include <renesas/rzg2l-usbphy.h>
+
+#define VBENCTL			0x03c
+#define VBENCTL_VBUS_SEL	BIT(0)
+
+static int rzg2l_usbphy_regulator_set_enable(struct udevice *dev, bool enable)
+{
+	struct rzg2l_usbphy_ctrl_priv *priv = dev_get_priv(dev->parent);
+
+	if (enable)
+		clrbits_le32(priv->regs + VBENCTL, VBENCTL_VBUS_SEL);
+	else
+		setbits_le32(priv->regs + VBENCTL, VBENCTL_VBUS_SEL);
+
+	return 0;
+}
+
+static int rzg2l_usbphy_regulator_get_enable(struct udevice *dev)
+{
+	struct rzg2l_usbphy_ctrl_priv *priv = dev_get_priv(dev->parent);
+
+	return !!readl(priv->regs + VBENCTL) & VBENCTL_VBUS_SEL;
+}
+
+static const struct dm_regulator_ops rzg2l_usbphy_regulator_ops = {
+	.get_enable = rzg2l_usbphy_regulator_get_enable,
+	.set_enable = rzg2l_usbphy_regulator_set_enable,
+};
+
+U_BOOT_DRIVER(rzg2l_usbphy_regulator) = {
+	.name = "rzg2l_usbphy_regulator",
+	.id = UCLASS_REGULATOR,
+	.ops = &rzg2l_usbphy_regulator_ops,
+};
diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig
index 6e79868d0ef..de312656746 100644
--- a/drivers/pwm/Kconfig
+++ b/drivers/pwm/Kconfig
@@ -105,6 +105,14 @@ config PWM_TEGRA
 	  32KHz clock is supported by the driver but the duty cycle is
 	  configurable.
 
+config PWM_STM32
+	bool "Enable support for STM32 PWM"
+	depends on DM_PWM && MFD_STM32_TIMERS
+	help
+	  This enables PWM driver for STMicroelectronics STM32 pulse width
+	  modulation. It uses STM32 timer devices that can have up to 4 output
+	  channels, with complementary outputs and configurable polarity.
+
 config PWM_SUNXI
 	bool "Enable support for the Allwinner Sunxi PWM"
 	depends on DM_PWM
diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile
index e4d10c8dc3e..76305b93bc9 100644
--- a/drivers/pwm/Makefile
+++ b/drivers/pwm/Makefile
@@ -22,5 +22,6 @@ obj-$(CONFIG_PWM_ROCKCHIP)	+= rk_pwm.o
 obj-$(CONFIG_PWM_SANDBOX)	+= sandbox_pwm.o
 obj-$(CONFIG_PWM_SIFIVE)	+= pwm-sifive.o
 obj-$(CONFIG_PWM_TEGRA)		+= tegra_pwm.o
+obj-$(CONFIG_PWM_STM32)		+= pwm-stm32.o
 obj-$(CONFIG_PWM_SUNXI)		+= sunxi_pwm.o
 obj-$(CONFIG_PWM_TI_EHRPWM)	+= pwm-ti-ehrpwm.o
diff --git a/drivers/pwm/pwm-mtk.c b/drivers/pwm/pwm-mtk.c
index 5cf2eba2ba0..898e353b370 100644
--- a/drivers/pwm/pwm-mtk.c
+++ b/drivers/pwm/pwm-mtk.c
@@ -30,6 +30,7 @@
 enum mtk_pwm_reg_ver {
 	PWM_REG_V1,
 	PWM_REG_V2,
+	PWM_REG_V3,
 };
 
 static const unsigned int mtk_pwm_reg_offset_v1[] = {
@@ -40,6 +41,10 @@ static const unsigned int mtk_pwm_reg_offset_v2[] = {
 	0x0080, 0x00c0, 0x0100, 0x0140, 0x0180, 0x01c0, 0x0200, 0x0240
 };
 
+static const unsigned int mtk_pwm_reg_offset_v3[] = {
+	0x0100, 0x0200, 0x0300, 0x0400, 0x0500, 0x600, 0x700, 0x0800
+};
+
 struct mtk_pwm_soc {
 	unsigned int num_pwms;
 	bool pwm45_fixup;
@@ -60,6 +65,10 @@ static void mtk_pwm_w32(struct udevice *dev, uint channel, uint reg, uint val)
 	u32 offset;
 
 	switch (priv->soc->reg_ver) {
+	case PWM_REG_V3:
+		offset = mtk_pwm_reg_offset_v3[channel];
+		break;
+
 	case PWM_REG_V2:
 		offset = mtk_pwm_reg_offset_v2[channel];
 		break;
@@ -203,6 +212,12 @@ static const struct mtk_pwm_soc mt7986_data = {
 	.reg_ver = PWM_REG_V1,
 };
 
+static const struct mtk_pwm_soc mt7987_data = {
+	.num_pwms = 3,
+	.pwm45_fixup = false,
+	.reg_ver = PWM_REG_V3,
+};
+
 static const struct mtk_pwm_soc mt7988_data = {
 	.num_pwms = 8,
 	.pwm45_fixup = false,
@@ -215,6 +230,7 @@ static const struct udevice_id mtk_pwm_ids[] = {
 	{ .compatible = "mediatek,mt7629-pwm", .data = (ulong)&mt7629_data },
 	{ .compatible = "mediatek,mt7981-pwm", .data = (ulong)&mt7981_data },
 	{ .compatible = "mediatek,mt7986-pwm", .data = (ulong)&mt7986_data },
+	{ .compatible = "mediatek,mt7987-pwm", .data = (ulong)&mt7987_data },
 	{ .compatible = "mediatek,mt7988-pwm", .data = (ulong)&mt7988_data },
 	{ }
 };
diff --git a/drivers/pwm/pwm-stm32.c b/drivers/pwm/pwm-stm32.c
new file mode 100644
index 00000000000..5fa649b5903
--- /dev/null
+++ b/drivers/pwm/pwm-stm32.c
@@ -0,0 +1,205 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2025, STMicroelectronics - All Rights Reserved
+ * Author: Cheick Traore <cheick.traore@foss.st.com>
+ *
+ * Originally based on the Linux kernel v6.10 drivers/pwm/pwm-stm32.c.
+ */
+
+#include <div64.h>
+#include <dm.h>
+#include <pwm.h>
+#include <asm/io.h>
+#include <asm/arch/timers.h>
+#include <dm/device_compat.h>
+#include <linux/time.h>
+
+#define CCMR_CHANNEL_SHIFT	8
+#define CCMR_CHANNEL_MASK	0xFF
+
+struct stm32_pwm_priv {
+	bool have_complementary_output;
+	bool invert_polarity;
+};
+
+static u32 active_channels(struct stm32_timers_plat *plat)
+{
+	return readl(plat->base + TIM_CCER) & TIM_CCER_CCXE;
+}
+
+static int stm32_pwm_set_config(struct udevice *dev, uint channel,
+				uint period_ns, uint duty_ns)
+{
+	struct stm32_timers_plat *plat = dev_get_plat(dev_get_parent(dev));
+	struct stm32_timers_priv *priv = dev_get_priv(dev_get_parent(dev));
+	unsigned long long prd, div, dty;
+	unsigned int prescaler = 0;
+	u32 ccmr, mask, shift;
+
+	if (duty_ns > period_ns)
+		return -EINVAL;
+
+	/*
+	 * Period and prescaler values depends on clock rate
+	 * First we need to find the minimal value for prescaler such that
+	 *
+	 *        period_ns * clkrate
+	 *   ------------------------------ < max_arr + 1
+	 *   NSEC_PER_SEC * (prescaler + 1)
+	 *
+	 * This equation is equivalent to
+	 *
+	 *        period_ns * clkrate
+	 *   ---------------------------- < prescaler + 1
+	 *   NSEC_PER_SEC * (max_arr + 1)
+	 *
+	 * Using integer division and knowing that the right hand side is
+	 * integer, this is further equivalent to
+	 *
+	 *   (period_ns * clkrate) // (NSEC_PER_SEC * (max_arr + 1)) ≤ prescaler
+	 */
+
+	div = (unsigned long long)priv->rate * period_ns;
+	do_div(div, NSEC_PER_SEC);
+	prd = div;
+
+	do_div(div, priv->max_arr + 1);
+	prescaler = div;
+	if (prescaler > MAX_TIM_PSC)
+		return -EINVAL;
+
+	do_div(prd, prescaler + 1);
+	if (!prd)
+		return -EINVAL;
+
+	/*
+	 * All channels share the same prescaler and counter so when two
+	 * channels are active at the same time we can't change them
+	 */
+	if (active_channels(plat) & ~(1 << channel * 4)) {
+		u32 psc, arr;
+
+		psc = readl(plat->base + TIM_PSC);
+		arr = readl(plat->base + TIM_ARR);
+		if (psc != prescaler || arr != prd - 1)
+			return -EBUSY;
+	}
+
+	writel(prescaler, plat->base + TIM_PSC);
+	writel(prd - 1, plat->base + TIM_ARR);
+	setbits_le32(plat->base + TIM_CR1, TIM_CR1_ARPE);
+
+	/* Calculate the duty cycles */
+	dty = prd * duty_ns;
+	do_div(dty, period_ns);
+
+	writel(dty, plat->base + TIM_CCRx(channel + 1));
+
+	/* Configure output mode */
+	shift = (channel & 0x1) * CCMR_CHANNEL_SHIFT;
+	ccmr = (TIM_CCMR_PE | TIM_CCMR_M1) << shift;
+	mask = CCMR_CHANNEL_MASK << shift;
+	if (channel < 2)
+		clrsetbits_le32(plat->base + TIM_CCMR1, mask, ccmr);
+	else
+		clrsetbits_le32(plat->base + TIM_CCMR2, mask, ccmr);
+
+	setbits_le32(plat->base + TIM_BDTR, TIM_BDTR_MOE);
+
+	return 0;
+}
+
+static int stm32_pwm_set_enable(struct udevice *dev, uint channel,
+				bool enable)
+{
+	struct stm32_timers_plat *plat = dev_get_plat(dev_get_parent(dev));
+	struct stm32_pwm_priv *priv = dev_get_priv(dev);
+	u32 mask;
+
+	/* Enable channel */
+	mask = TIM_CCER_CC1E << (channel * 4);
+	if (priv->have_complementary_output)
+		mask |= TIM_CCER_CC1NE << (channel * 4);
+
+	if (enable) {
+		setbits_le32(plat->base + TIM_CCER, mask);
+		/* Make sure that registers are updated */
+		setbits_le32(plat->base + TIM_EGR, TIM_EGR_UG);
+		/* Enable controller */
+		setbits_le32(plat->base + TIM_CR1, TIM_CR1_CEN);
+	} else {
+		clrbits_le32(plat->base + TIM_CCER, mask);
+		/* When all channels are disabled, we can disable the controller */
+		if (!active_channels(plat))
+			clrbits_le32(plat->base + TIM_CR1, TIM_CR1_CEN);
+	}
+
+	return 0;
+}
+
+static int stm32_pwm_set_invert(struct udevice *dev, uint channel,
+				bool polarity)
+{
+	struct stm32_timers_plat *plat = dev_get_plat(dev_get_parent(dev));
+	struct stm32_pwm_priv *priv = dev_get_priv(dev);
+	u32 mask;
+
+	mask = TIM_CCER_CC1P << (channel * 4);
+	if (priv->have_complementary_output)
+		mask |= TIM_CCER_CC1NP << (channel * 4);
+
+	clrsetbits_le32(plat->base + TIM_CCER, mask, polarity ? mask : 0);
+
+	return 0;
+}
+
+static void stm32_pwm_detect_complementary(struct udevice *dev)
+{
+	struct stm32_timers_plat *plat = dev_get_plat(dev_get_parent(dev));
+	struct stm32_pwm_priv *priv = dev_get_priv(dev);
+	u32 ccer;
+
+	/*
+	 * If complementary bit doesn't exist writing 1 will have no
+	 * effect so we can detect it.
+	 */
+	setbits_le32(plat->base + TIM_CCER, TIM_CCER_CC1NE);
+	ccer = readl(plat->base + TIM_CCER);
+	clrbits_le32(plat->base + TIM_CCER, TIM_CCER_CC1NE);
+
+	priv->have_complementary_output = (ccer != 0);
+}
+
+static int stm32_pwm_probe(struct udevice *dev)
+{
+	struct stm32_timers_priv *timer = dev_get_priv(dev_get_parent(dev));
+
+	if (timer->rate > 1000000000) {
+		dev_err(dev, "Clock freq too high (%lu)\n", timer->rate);
+		return -EINVAL;
+	}
+
+	stm32_pwm_detect_complementary(dev);
+
+	return 0;
+}
+
+static const struct pwm_ops stm32_pwm_ops = {
+	.set_config	= stm32_pwm_set_config,
+	.set_enable	= stm32_pwm_set_enable,
+	.set_invert	= stm32_pwm_set_invert,
+};
+
+static const struct udevice_id stm32_pwm_ids[] = {
+	{ .compatible = "st,stm32-pwm" },
+	{ }
+};
+
+U_BOOT_DRIVER(stm32_pwm) = {
+	.name		= "stm32_pwm",
+	.id		= UCLASS_PWM,
+	.of_match	= stm32_pwm_ids,
+	.ops		= &stm32_pwm_ops,
+	.probe          = stm32_pwm_probe,
+	.priv_auto	= sizeof(struct stm32_pwm_priv),
+};
diff --git a/drivers/ram/Kconfig b/drivers/ram/Kconfig
index 899d7585489..2a40b0c9f81 100644
--- a/drivers/ram/Kconfig
+++ b/drivers/ram/Kconfig
@@ -71,7 +71,7 @@ choice
 	depends on K3_DDRSS
 	prompt "K3 DDRSS Arch Support"
 
-	default K3_J721E_DDRSS if SOC_K3_J721E || SOC_K3_J721S2 || SOC_K3_J784S4
+	default K3_J721E_DDRSS if SOC_K3_J721E || SOC_K3_J7200 || SOC_K3_J721S2 || SOC_K3_J784S4
 	default K3_AM64_DDRSS if SOC_K3_AM642
 	default K3_AM64_DDRSS if SOC_K3_AM625
 	default K3_AM62A_DDRSS if SOC_K3_AM62A7 || SOC_K3_AM62P5 || SOC_K3_J722S
diff --git a/drivers/ram/renesas/dbsc5/dram.c b/drivers/ram/renesas/dbsc5/dram.c
index 6f78afb0ab5..ca8a7fb4783 100644
--- a/drivers/ram/renesas/dbsc5/dram.c
+++ b/drivers/ram/renesas/dbsc5/dram.c
@@ -1325,6 +1325,11 @@ static const u32 PI_DARRAY3_1_CSx_Fx[CS_CNT][3] = {
 #define DBSC_DBACEN			0x200
 #define DBSC_DBRFEN			0x204
 #define DBSC_DBCMD			0x208
+#define DBSC_DBCMD_CMD_OPCODE_PD	0x8
+#define DBSC_DBCMD_CMD_OPCODE_MRW	0xe
+#define DBSC_DBCMD_CMD_OPCODE_MRR	0xf
+#define DBSC_DBCMD_CMD_CHANNEL_ALL	0x8
+#define DBSC_DBCMD_CMD_RANK_ALL		0x4
 #define DBSC_DBWAIT			0x210
 #define DBSC_DBBL			0x400
 #define DBSC_DBBLA			0x400
@@ -1736,24 +1741,20 @@ static void dbsc5_reg_write(void __iomem *addr, u32 data)
 }
 
 /**
- * dbsc5_reg_write() - DRAM Command Write Access
+ * dbsc5_wait_dbwait() - DRAM Command Wait Access Completion
  * @dev: DBSC5 device
- * @cmd DRAM command.
  *
- * First, execute the dummy read to DBSC_DBCMD.
- * Confirm that no DBSC command operation is in progress 0.
- * Write the contents of the command to be sent to DRAM.
+ * Wait for DRAM access completion. This is used before sending a command
+ * to the DRAM to assure no other command is in flight already, or while
+ * waiting for MRR command to complete.
  */
-static void dbsc5_send_dbcmd2(struct udevice *dev, u32 cmd)
+static void dbsc5_wait_dbwait(struct udevice *dev)
 {
 	struct renesas_dbsc5_dram_priv *priv = dev_get_priv(dev);
 	void __iomem *regs_dbsc_d = priv->regs + DBSC5_DBSC_D_OFFSET;
 	u32 val;
 	int ret;
 
-	/* dummy read */
-	readl(regs_dbsc_d + DBSC_DBCMD);
-
 	ret = readl_poll_timeout(regs_dbsc_d + DBSC_DBWAIT, val, ((val & BIT(0)) == 0), 1000000);
 	if (ret < 0) {
 		printf("%s DBWAIT bit 0 timeout\n", __func__);
@@ -1765,6 +1766,32 @@ static void dbsc5_send_dbcmd2(struct udevice *dev, u32 cmd)
 		printf("%s DBWAIT + 0x4000 bit 0 timeout\n", __func__);
 		hang();
 	}
+}
+
+/**
+ * dbsc5_send_dbcmd2() - DRAM Command Write Access
+ * @dev: DBSC5 device
+ * @opcode DRAM controller opcode
+ * @channel DRAM controller channel (0..3)
+ * @rank DRAM controller rank (0..1)
+ * @arg Command and argument bits (command specific encoding)
+ *
+ * First, execute the dummy read to DBSC_DBCMD.
+ * Confirm that no DBSC command operation is in progress 0.
+ * Write the contents of the command to be sent to DRAM.
+ */
+static void dbsc5_send_dbcmd2(struct udevice *dev, const u8 opcode,
+			      const u8 channel, const u8 rank,
+			      const u16 arg)
+{
+	const u32 cmd = (opcode << 24) | (channel << 20) | (rank << 16) | arg;
+	struct renesas_dbsc5_dram_priv *priv = dev_get_priv(dev);
+	void __iomem *regs_dbsc_d = priv->regs + DBSC5_DBSC_D_OFFSET;
+
+	/* dummy read */
+	readl(regs_dbsc_d + DBSC_DBCMD);
+
+	dbsc5_wait_dbwait(dev);
 
 	dbsc5_reg_write(regs_dbsc_d + DBSC_DBCMD, cmd);
 }
@@ -2950,10 +2977,14 @@ static u32 dbsc5_pi_training(struct udevice *dev)
 		writel(0x21, regs_dbsc_d + DBSC_DBDFICNT(ch));
 
 	/* Dummy PDE */
-	dbsc5_send_dbcmd2(dev, 0x8840000);
+	dbsc5_send_dbcmd2(dev, DBSC_DBCMD_CMD_OPCODE_PD,
+			  DBSC_DBCMD_CMD_CHANNEL_ALL,
+			  DBSC_DBCMD_CMD_RANK_ALL, 0);
 
 	/* PDX */
-	dbsc5_send_dbcmd2(dev, 0x8840001);
+	dbsc5_send_dbcmd2(dev, DBSC_DBCMD_CMD_OPCODE_PD,
+			  DBSC_DBCMD_CMD_CHANNEL_ALL,
+			  DBSC_DBCMD_CMD_RANK_ALL, 1);
 
 	/* Wait init_complete */
 	for (retry = 0; retry < retry_max; retry++) {
@@ -4085,25 +4116,27 @@ static u32 dbsc5_read_training(struct udevice *dev)
 }
 
 /**
- * dbsc5_ddr_register_set() - DDR mode register setting
+ * dbsc5_ddr_register_mr28_set() - DDR mode register MR28 set
  * @dev: DBSC5 device
  *
  * Set the mode register 28 of the SDRAM.
  * ZQ Mode: Command-Based ZQ Calibration
  * ZQ interval: Background Cal Interval < 64ms
  */
-static void dbsc5_ddr_register_set(struct udevice *dev)
+static void dbsc5_ddr_register_mr28_set(struct udevice *dev)
 {
-	dbsc5_send_dbcmd2(dev, 0xE841C24);
+	dbsc5_send_dbcmd2(dev, DBSC_DBCMD_CMD_OPCODE_MRW,
+			  DBSC_DBCMD_CMD_CHANNEL_ALL,
+			  DBSC_DBCMD_CMD_RANK_ALL, (28 << 8) | 0x24);
 }
 
 /**
- * dbsc5_ddr_register_read() - DDR mode register read
+ * dbsc5_ddr_register_mr27_mr57_read() - DDR mode register MR27/MR57 read
  * @dev: DBSC5 device
  *
  * Set the mode register 27 and 57 of the SDRAM.
  */
-static void dbsc5_ddr_register_read(struct udevice *dev)
+static void dbsc5_ddr_register_mr27_mr57_read(struct udevice *dev)
 {
 	struct renesas_dbsc5_dram_priv *priv = dev_get_priv(dev);
 
@@ -4111,17 +4144,21 @@ static void dbsc5_ddr_register_read(struct udevice *dev)
 		return;
 
 	/* MR27 rank0 */
-	dbsc5_send_dbcmd2(dev, 0xF801B00);
+	dbsc5_send_dbcmd2(dev, DBSC_DBCMD_CMD_OPCODE_MRR,
+			  DBSC_DBCMD_CMD_CHANNEL_ALL, 0, 27 << 8);
 	/* MR57 rank0 */
-	dbsc5_send_dbcmd2(dev, 0xF803900);
+	dbsc5_send_dbcmd2(dev, DBSC_DBCMD_CMD_OPCODE_MRR,
+			  DBSC_DBCMD_CMD_CHANNEL_ALL, 0, 57 << 8);
 
 	if (!priv->ch_have_this_cs[1])
 		return;
 
 	/* MR27 rank1 */
-	dbsc5_send_dbcmd2(dev, 0xF811B00);
+	dbsc5_send_dbcmd2(dev, DBSC_DBCMD_CMD_OPCODE_MRR,
+			  DBSC_DBCMD_CMD_CHANNEL_ALL, 1, 27 << 8);
 	/* MR57 rank1 */
-	dbsc5_send_dbcmd2(dev, 0xF813900);
+	dbsc5_send_dbcmd2(dev, DBSC_DBCMD_CMD_OPCODE_MRR,
+			  DBSC_DBCMD_CMD_CHANNEL_ALL, 1, 57 << 8);
 }
 
 /**
@@ -4200,8 +4237,8 @@ static u32 dbsc5_init_ddr(struct udevice *dev)
 	dbsc5_dbsc_regset(dev);
 
 	/* Frequency selection change (F1->F2) */
-	 dbsc5_ddr_setval_all_ch(dev, PHY_FREQ_SEL_INDEX, 0x1);
-	 dbsc5_ddr_setval_all_ch(dev, PHY_FREQ_SEL_MULTICAST_EN, 0x0);
+	dbsc5_ddr_setval_all_ch(dev, PHY_FREQ_SEL_INDEX, 0x1);
+	dbsc5_ddr_setval_all_ch(dev, PHY_FREQ_SEL_MULTICAST_EN, 0x0);
 
 	/* dfi_init_start (start ddrphy) & execute pi_training */
 	phytrainingok = dbsc5_pi_training(dev);
@@ -4278,10 +4315,10 @@ static u32 dbsc5_init_ddr(struct udevice *dev)
 
 	/* setup DDR mode registers */
 	/* MRS */
-	dbsc5_ddr_register_set(dev);
+	dbsc5_ddr_register_mr28_set(dev);
 
 	/* MRR */
-	dbsc5_ddr_register_read(dev);
+	dbsc5_ddr_register_mr27_mr57_read(dev);
 
 	/* training complete, setup DBSC */
 	dbsc5_dbsc_regset_post(dev);
@@ -4296,10 +4333,13 @@ static u32 dbsc5_init_ddr(struct udevice *dev)
 
 /**
  * dbsc5_get_board_data() - Obtain board specific DRAM configuration
+ * @dev: DBSC5 device
+ * @modemr0: MODEMR0 register content
  *
  * Return board specific DRAM configuration structure pointer.
  */
-__weak const struct renesas_dbsc5_board_config *dbsc5_get_board_data(void)
+__weak const struct renesas_dbsc5_board_config *
+dbsc5_get_board_data(struct udevice *dev, const u32 modemr0)
 {
 	return &renesas_v4h_dbsc5_board_config;
 }
@@ -4335,7 +4375,7 @@ static int renesas_dbsc5_dram_probe(struct udevice *dev)
 	u32 ch, cs;
 
 	/* Get board data */
-	priv->dbsc5_board_config = dbsc5_get_board_data();
+	priv->dbsc5_board_config = dbsc5_get_board_data(dev, modemr0);
 	priv->ddr_phyvalid = (u32)(priv->dbsc5_board_config->bdcfg_phyvalid);
 	priv->max_density = 0;
 	priv->cpg_regs = (void __iomem *)ofnode_get_addr(cnode);
diff --git a/drivers/remoteproc/Kconfig b/drivers/remoteproc/Kconfig
index 2790b168b19..a3ecea05e20 100644
--- a/drivers/remoteproc/Kconfig
+++ b/drivers/remoteproc/Kconfig
@@ -13,6 +13,7 @@ config REMOTEPROC
 	depends on DM
 
 # Please keep the configuration alphabetically sorted.
+
 config K3_SYSTEM_CONTROLLER
 	bool "Support for TI' K3 System Controller"
 	select REMOTEPROC
@@ -22,6 +23,16 @@ config K3_SYSTEM_CONTROLLER
 	help
 	  Say 'y' here to add support for TI' K3 System Controller.
 
+config REMOTEPROC_ADI_SC5XX
+	bool "Support for ADI SC5xx SHARC cores"
+	select REMOTEPROC
+	depends on DM
+	depends on ARCH_SC5XX
+	depends on SYSCON
+	help
+	  Say 'y' here to add support for loading code onto SHARC cores in
+	  an ADSP-SC5xx SoC from Analog Devices
+
 config REMOTEPROC_RENESAS_APMU
 	bool "Support for Renesas R-Car Gen4 APMU start of CR52 processor"
 	select REMOTEPROC
@@ -55,6 +66,7 @@ config REMOTEPROC_TI_K3_ARM64
 	depends on DM
 	depends on ARCH_K3
 	depends on OF_CONTROL
+	default y if SYS_K3_SPL_ATF
 	help
 	  Say y here to support TI's ARM64 processor subsystems
 	  on various TI K3 family of SoCs through the remote processor
@@ -70,6 +82,16 @@ config REMOTEPROC_TI_K3_DSP
 	  on various TI K3 family of SoCs through the remote processor
 	  framework.
 
+config REMOTEPROC_TI_K3_M4F
+	bool "TI K3 M4F remoteproc support"
+	select REMOTEPROC
+	depends on ARCH_K3
+	depends on TI_SCI_PROTOCOL
+	help
+	  Say y here to support TI's M4F remote processor subsystems
+	  on various TI K3 family of SoCs through the remote processor
+	  framework.
+
 config REMOTEPROC_TI_K3_R5F
 	bool "TI K3 R5F remoteproc support"
 	select REMOTEPROC
diff --git a/drivers/remoteproc/Makefile b/drivers/remoteproc/Makefile
index 3a092b7660e..bd94ea771be 100644
--- a/drivers/remoteproc/Makefile
+++ b/drivers/remoteproc/Makefile
@@ -8,11 +8,13 @@ obj-$(CONFIG_$(XPL_)REMOTEPROC) += rproc-uclass.o rproc-elf-loader.o
 
 # Remote proc drivers - Please keep this list alphabetically sorted.
 obj-$(CONFIG_K3_SYSTEM_CONTROLLER) += k3_system_controller.o
+obj-$(CONFIG_REMOTEPROC_ADI_SC5XX) += adi_sc5xx_rproc.o
 obj-$(CONFIG_REMOTEPROC_RENESAS_APMU) += renesas_apmu.o
 obj-$(CONFIG_REMOTEPROC_SANDBOX) += sandbox_testproc.o
 obj-$(CONFIG_REMOTEPROC_STM32_COPRO) += stm32_copro.o
 obj-$(CONFIG_REMOTEPROC_TI_K3_ARM64) += ti_k3_arm64_rproc.o
 obj-$(CONFIG_REMOTEPROC_TI_K3_DSP) += ti_k3_dsp_rproc.o
+obj-$(CONFIG_REMOTEPROC_TI_K3_M4F) += ti_k3_m4_rproc.o
 obj-$(CONFIG_REMOTEPROC_TI_K3_R5F) += ti_k3_r5f_rproc.o
 obj-$(CONFIG_REMOTEPROC_TI_POWER) += ti_power_proc.o
 obj-$(CONFIG_REMOTEPROC_TI_PRU) += pru_rproc.o
diff --git a/drivers/remoteproc/adi_sc5xx_rproc.c b/drivers/remoteproc/adi_sc5xx_rproc.c
new file mode 100644
index 00000000000..86acd1b98c7
--- /dev/null
+++ b/drivers/remoteproc/adi_sc5xx_rproc.c
@@ -0,0 +1,277 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * (C) Copyright 2022 - Analog Devices, Inc.
+ *
+ * Written and/or maintained by Timesys Corporation
+ *
+ * Contact: Nathan Barrett-Morrison <nathan.morrison@timesys.com>
+ * Contact: Greg Malysa <greg.malysa@timesys.com>
+ *
+ * Analog Devices SC5xx remoteproc driver for loading code onto SHARC cores
+ */
+
+#include <dm.h>
+#include <regmap.h>
+#include <remoteproc.h>
+#include <syscon.h>
+#include <dm/device_compat.h>
+#include <linux/delay.h>
+#include <linux/io.h>
+
+/* Register offsets */
+#ifdef CONFIG_SC58X
+#define ADI_RCU_REG_CTL		0x00
+#define ADI_RCU_REG_STAT	0x04
+#define ADI_RCU_REG_CRCTL	0x08
+#define ADI_RCU_REG_CRSTAT	0x0c
+#define ADI_RCU_REG_SIDIS	0x10
+#define ADI_RCU_REG_SISTAT	0x14
+#define ADI_RCU_REG_BCODE	0x1c
+#define ADI_RCU_REG_SVECT0	0x20
+#define ADI_RCU_REG_SVECT1	0x24
+#define ADI_RCU_REG_SVECT2	0x28
+#define ADI_RCU_REG_MSG		0x60
+#define ADI_RCU_REG_MSG_SET	0x64
+#define ADI_RCU_REG_MSG_CLR	0x68
+#else
+#define ADI_RCU_REG_CTL		0x00
+#define ADI_RCU_REG_STAT	0x04
+#define ADI_RCU_REG_CRCTL	0x08
+#define ADI_RCU_REG_CRSTAT	0x0c
+#define ADI_RCU_REG_SRRQSTAT	0x18
+#define ADI_RCU_REG_SIDIS	0x1c
+#define ADI_RCU_REG_SISTAT	0x20
+#define ADI_RCU_REG_SVECT_LCK	0x24
+#define ADI_RCU_REG_BCODE	0x28
+#define ADI_RCU_REG_SVECT0	0x2c
+#define ADI_RCU_REG_SVECT1	0x30
+#define ADI_RCU_REG_SVECT2	0x34
+#define ADI_RCU_REG_MSG		0x6c
+#define ADI_RCU_REG_MSG_SET	0x70
+#define ADI_RCU_REG_MSG_CLR	0x74
+#endif /* CONFIG_SC58X */
+
+/* Register bit definitions */
+#define ADI_RCU_CTL_SYSRST		BIT(0)
+
+/* Bit values for the RCU0_MSG register */
+#define RCU0_MSG_C0IDLE			0x00000100		/* Core 0 Idle */
+#define RCU0_MSG_C1IDLE			0x00000200		/* Core 1 Idle */
+#define RCU0_MSG_C2IDLE			0x00000400		/* Core 2 Idle */
+#define RCU0_MSG_CRR0			0x00001000		/* Core 0 reset request */
+#define RCU0_MSG_CRR1			0x00002000		/* Core 1 reset request */
+#define RCU0_MSG_CRR2			0x00004000		/* Core 2 reset request */
+#define RCU0_MSG_C1ACTIVATE		0x00080000		/* Core 1 Activated */
+#define RCU0_MSG_C2ACTIVATE		0x00100000		/* Core 2 Activated */
+
+struct sc5xx_rproc_data {
+	/* Address to load to svect when rebooting core */
+	u32 load_addr;
+
+	/* RCU parameters */
+	struct regmap *rcu;
+	u32 svect_offset;
+	u32 coreid;
+};
+
+struct block_code_flag {
+	u32 bcode:4,		/* 0-3 */
+	    bflag_save:1,	/* 4 */
+	    bflag_aux:1,	/* 5 */
+	    breserved:1,	/* 6 */
+	    bflag_forward:1,	/* 7 */
+	    bflag_fill:1,	/* 8 */
+	    bflag_quickboot:1,	/* 9 */
+	    bflag_callback:1,	/* 10 */
+	    bflag_init:1,	/* 11 */
+	    bflag_ignore:1,	/* 12 */
+	    bflag_indirect:1,	/* 13 */
+	    bflag_first:1,	/* 14 */
+	    bflag_final:1,	/* 15 */
+	    bhdrchk:8,		/* 16-23 */
+	    bhdrsign:8;		/* 0xAD, 0xAC or 0xAB */
+};
+
+struct ldr_hdr {
+	struct block_code_flag bcode_flag;
+	u32 target_addr;
+	u32 byte_count;
+	u32 argument;
+};
+
+static int is_final(struct ldr_hdr *hdr)
+{
+	return hdr->bcode_flag.bflag_final;
+}
+
+static int is_empty(struct ldr_hdr *hdr)
+{
+	return hdr->bcode_flag.bflag_ignore || (hdr->byte_count == 0);
+}
+
+static int adi_valid_firmware(struct ldr_hdr *adi_ldr_hdr)
+{
+	if (!adi_ldr_hdr->byte_count &&
+	    (adi_ldr_hdr->bcode_flag.bhdrsign == 0xAD ||
+	     adi_ldr_hdr->bcode_flag.bhdrsign == 0xAC ||
+	     adi_ldr_hdr->bcode_flag.bhdrsign == 0xAB))
+		return 1;
+
+	return 0;
+}
+
+static int sharc_load(struct udevice *dev, ulong addr, ulong size)
+{
+	struct sc5xx_rproc_data *priv = dev_get_priv(dev);
+	size_t offset;
+	u8 *buf = (u8 *)addr;
+	struct ldr_hdr *ldr = (struct ldr_hdr *)addr;
+	struct ldr_hdr *block_hdr;
+	struct ldr_hdr *next_hdr;
+
+	if (!adi_valid_firmware(ldr)) {
+		dev_err(dev, "Firmware at 0x%lx does not appear to be an LDR image\n", addr);
+		dev_err(dev, "Note: Signed firmware is not currently supported\n");
+		return -EINVAL;
+	}
+
+	do {
+		block_hdr = (struct ldr_hdr *)buf;
+		offset = sizeof(struct ldr_hdr) + (block_hdr->bcode_flag.bflag_fill ?
+							0 : block_hdr->byte_count);
+		next_hdr = (struct ldr_hdr *)(buf + offset);
+
+		if (block_hdr->bcode_flag.bflag_first)
+			priv->load_addr = (unsigned long)block_hdr->target_addr;
+
+		if (!is_empty(block_hdr)) {
+			if (block_hdr->bcode_flag.bflag_fill) {
+				memset_io((void *)(phys_addr_t)block_hdr->target_addr,
+					  block_hdr->argument,
+					  block_hdr->byte_count);
+			} else {
+				memcpy_toio((void *)(phys_addr_t)block_hdr->target_addr,
+					  buf + sizeof(struct ldr_hdr),
+					  block_hdr->byte_count);
+			}
+		}
+
+		if (is_final(block_hdr))
+			break;
+
+		buf += offset;
+	} while (1);
+
+	return 0;
+}
+
+static void sharc_reset(struct sc5xx_rproc_data *priv)
+{
+	u32 coreid = priv->coreid;
+	u32 val;
+
+	/* First put core in reset.
+	 * Clear CRSTAT bit for given coreid.
+	 */
+	regmap_write(priv->rcu, ADI_RCU_REG_CRSTAT, 1 << coreid);
+
+	/* Set SIDIS to disable the system interface */
+	regmap_read(priv->rcu, ADI_RCU_REG_SIDIS, &val);
+	regmap_write(priv->rcu, ADI_RCU_REG_SIDIS, val | (1 << (coreid - 1)));
+
+	/*
+	 * Wait for access to coreX have been disabled and all the pending
+	 * transactions have completed
+	 */
+	udelay(50);
+
+	/* Set CRCTL bit to put core in reset */
+	regmap_read(priv->rcu, ADI_RCU_REG_CRCTL, &val);
+	regmap_write(priv->rcu, ADI_RCU_REG_CRCTL, val | (1 << coreid));
+
+	/* Poll until Core is in reset */
+	while (!(regmap_read(priv->rcu, ADI_RCU_REG_CRSTAT, &val), val & (1 << coreid)))
+		;
+
+	/* Clear SIDIS to reenable the system interface */
+	regmap_read(priv->rcu, ADI_RCU_REG_SIDIS, &val);
+	regmap_write(priv->rcu, ADI_RCU_REG_SIDIS, val & ~(1 << (coreid - 1)));
+
+	udelay(50);
+
+	/* Take Core out of reset */
+	regmap_read(priv->rcu, ADI_RCU_REG_CRCTL, &val);
+	regmap_write(priv->rcu, ADI_RCU_REG_CRCTL, val & ~(1 << coreid));
+
+	/* Wait for done */
+	udelay(50);
+}
+
+static int sharc_start(struct udevice *dev)
+{
+	struct sc5xx_rproc_data *priv = dev_get_priv(dev);
+
+	/* Write load address to appropriate SVECT for core */
+	regmap_write(priv->rcu, priv->svect_offset, priv->load_addr);
+
+	sharc_reset(priv);
+
+	/* Clear the IDLE bit when start the SHARC core */
+	regmap_write(priv->rcu, ADI_RCU_REG_MSG_CLR, RCU0_MSG_C0IDLE << priv->coreid);
+
+	/* Notify CCES */
+	regmap_write(priv->rcu, ADI_RCU_REG_MSG_SET, RCU0_MSG_C1ACTIVATE << (priv->coreid - 1));
+	return 0;
+}
+
+static const struct dm_rproc_ops sc5xx_ops = {
+	.load = sharc_load,
+	.start = sharc_start,
+};
+
+static int sc5xx_probe(struct udevice *dev)
+{
+	struct sc5xx_rproc_data *priv = dev_get_priv(dev);
+	u32 coreid;
+
+	if (dev_read_u32(dev, "coreid", &coreid)) {
+		dev_err(dev, "Missing property coreid\n");
+		return -ENOENT;
+	}
+
+	priv->coreid = coreid;
+	switch (coreid) {
+	case 1:
+		priv->svect_offset = ADI_RCU_REG_SVECT1;
+		break;
+	case 2:
+		priv->svect_offset = ADI_RCU_REG_SVECT2;
+		break;
+	default:
+		dev_err(dev, "Invalid value %d for coreid, must be 1 or 2\n", coreid);
+		return -EINVAL;
+	}
+
+	priv->rcu = syscon_regmap_lookup_by_phandle(dev, "adi,rcu");
+	if (IS_ERR(priv->rcu))
+		return PTR_ERR(priv->rcu);
+
+	dev_err(dev, "sc5xx remoteproc core %d available\n", priv->coreid);
+
+	return 0;
+}
+
+static const struct udevice_id sc5xx_ids[] = {
+	{ .compatible = "adi,sc5xx-rproc" },
+	{ }
+};
+
+U_BOOT_DRIVER(adi_sc5xx_rproc) = {
+	.name = "adi_sc5xx_rproc",
+	.of_match = sc5xx_ids,
+	.id = UCLASS_REMOTEPROC,
+	.ops = &sc5xx_ops,
+	.probe = sc5xx_probe,
+	.priv_auto = sizeof(struct sc5xx_rproc_data),
+	.flags = 0,
+};
diff --git a/drivers/remoteproc/ti_k3_dsp_rproc.c b/drivers/remoteproc/ti_k3_dsp_rproc.c
index e90f75a188c..5a7d6377283 100644
--- a/drivers/remoteproc/ti_k3_dsp_rproc.c
+++ b/drivers/remoteproc/ti_k3_dsp_rproc.c
@@ -15,6 +15,7 @@
 #include <clk.h>
 #include <reset.h>
 #include <asm/io.h>
+#include <asm/system.h>
 #include <power-domain.h>
 #include <dm/device_compat.h>
 #include <linux/err.h>
@@ -56,7 +57,9 @@ struct k3_dsp_boot_data {
  * @data:		Pointer to DSP specific boot data structure
  * @mem:		Array of available memories
  * @num_mem:		Number of available memories
- * @in_use: flag to tell if the core is already in use.
+ * @cached_addr:	Cached memory address
+ * @cached_size:	Cached memory size
+ * @in_use:		flag to tell if the core is already in use.
  */
 struct k3_dsp_privdata {
 	struct reset_ctl dsp_rst;
@@ -64,6 +67,8 @@ struct k3_dsp_privdata {
 	struct k3_dsp_boot_data *data;
 	struct k3_dsp_mem *mem;
 	int num_mems;
+	void __iomem *cached_addr;
+	size_t cached_size;
 	bool in_use;
 };
 
@@ -158,6 +163,13 @@ static int k3_dsp_load(struct udevice *dev, ulong addr, ulong size)
 		goto unprepare;
 	}
 
+	if (dsp->cached_addr && IS_ENABLED(CONFIG_SYS_DISABLE_DCACHE_OPS)) {
+		dev_dbg(dev, "final flush 0x%lx to 0x%lx\n",
+			(ulong)dsp->cached_addr, dsp->cached_size);
+		__asm_invalidate_dcache_range((u64)dsp->cached_addr,
+					      (u64)dsp->cached_addr + (u64)dsp->cached_size);
+	}
+
 	boot_vector = rproc_elf_get_boot_addr(dev, addr);
 	if (boot_vector & (data->boot_align_addr - 1)) {
 		ret = -EINVAL;
@@ -253,7 +265,6 @@ static void *k3_dsp_da_to_va(struct udevice *dev, ulong da, ulong len)
 {
 	struct k3_dsp_privdata *dsp = dev_get_priv(dev);
 	phys_addr_t bus_addr, dev_addr;
-	void __iomem *va = NULL;
 	size_t size;
 	u32 offset;
 	int i;
@@ -263,6 +274,16 @@ static void *k3_dsp_da_to_va(struct udevice *dev, ulong da, ulong len)
 	if (len <= 0)
 		return NULL;
 
+	if (dsp->cached_addr && IS_ENABLED(CONFIG_SYS_DISABLE_DCACHE_OPS)) {
+		dev_dbg(dev, "flush 0x%lx to 0x%lx\n", (ulong)dsp->cached_addr,
+			dsp->cached_size);
+		__asm_invalidate_dcache_range((u64)dsp->cached_addr,
+					      (u64)dsp->cached_addr + (u64)dsp->cached_size);
+	}
+
+	dsp->cached_size = len;
+	dsp->cached_addr = NULL;
+
 	for (i = 0; i < dsp->num_mems; i++) {
 		bus_addr = dsp->mem[i].bus_addr;
 		dev_addr = dsp->mem[i].dev_addr;
@@ -270,19 +291,20 @@ static void *k3_dsp_da_to_va(struct udevice *dev, ulong da, ulong len)
 
 		if (da >= dev_addr && ((da + len) <= (dev_addr + size))) {
 			offset = da - dev_addr;
-			va = dsp->mem[i].cpu_addr + offset;
-			return (__force void *)va;
+			dsp->cached_addr = dsp->mem[i].cpu_addr + offset;
 		}
 
 		if (da >= bus_addr && (da + len) <= (bus_addr + size)) {
 			offset = da - bus_addr;
-			va = dsp->mem[i].cpu_addr + offset;
-			return (__force void *)va;
+			dsp->cached_addr = dsp->mem[i].cpu_addr + offset;
 		}
 	}
 
 	/* Assume it is DDR region and return da */
-	return map_physmem(da, len, MAP_NOCACHE);
+	if (!dsp->cached_addr)
+		dsp->cached_addr = map_physmem(da, len, MAP_NOCACHE);
+
+	return dsp->cached_addr;
 }
 
 static const struct dm_rproc_ops k3_dsp_ops = {
diff --git a/drivers/remoteproc/ti_k3_m4_rproc.c b/drivers/remoteproc/ti_k3_m4_rproc.c
new file mode 100644
index 00000000000..31b9de71579
--- /dev/null
+++ b/drivers/remoteproc/ti_k3_m4_rproc.c
@@ -0,0 +1,371 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Texas Instruments' K3 M4 Remoteproc driver
+ *
+ * Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com/
+ *	Hari Nagalla <hnagalla@ti.com>
+ */
+
+#include <dm.h>
+#include <log.h>
+#include <malloc.h>
+#include <remoteproc.h>
+#include <errno.h>
+#include <clk.h>
+#include <reset.h>
+#include <asm/io.h>
+#include <power-domain.h>
+#include <dm/device_compat.h>
+#include <linux/err.h>
+#include <linux/sizes.h>
+#include <linux/soc/ti/ti_sci_protocol.h>
+#include "ti_sci_proc.h"
+#include <mach/security.h>
+
+/**
+ * struct k3_m4_mem - internal memory structure
+ * @cpu_addr: MPU virtual address of the memory region
+ * @bus_addr: Bus address used to access the memory region
+ * @dev_addr: Device address from remoteproc view
+ * @size: Size of the memory region
+ */
+struct k3_m4_mem {
+	void __iomem *cpu_addr;
+	phys_addr_t bus_addr;
+	phys_addr_t dev_addr;
+	size_t size;
+};
+
+/**
+ * struct k3_m4_mem_data - memory definitions for m4 remote core
+ * @name: name for this memory entry
+ * @dev_addr: device address for the memory entry
+ */
+struct k3_m4_mem_data {
+	const char *name;
+	const u32 dev_addr;
+};
+
+/**
+ * struct k3_m4_boot_data - internal data structure used for boot
+ * @boot_align_addr: Boot vector address alignment granularity
+ */
+struct k3_m4_boot_data {
+	u32 boot_align_addr;
+};
+
+/**
+ * struct k3_m4_privdata - Structure representing Remote processor data.
+ * @m4_rst:		m4 rproc reset control data
+ * @tsp:		Pointer to TISCI proc contrl handle
+ * @data:		Pointer to DSP specific boot data structure
+ * @mem:		Array of available memories
+ * @num_mem:		Number of available memories
+ */
+struct k3_m4_privdata {
+	struct reset_ctl m4_rst;
+	struct ti_sci_proc tsp;
+	struct k3_m4_boot_data *data;
+	struct k3_m4_mem *mem;
+	int num_mems;
+};
+
+/*
+ * The M4 cores have a local reset that affects only the CPU, and a
+ * generic module reset that powers on the device and allows the M4 internal
+ * memories to be accessed while the local reset is asserted. This function is
+ * used to release the global reset on M4F to allow loading into the M4F
+ * internal RAMs. This helper function is invoked in k3_m4_load() before any
+ * actual firmware loading happens and is undone only in k3_m4_stop(). The local
+ * reset cannot be released on M4 cores until after the firmware images are loaded.
+ */
+static int k3_m4_prepare(struct udevice *dev)
+{
+	struct k3_m4_privdata *m4 = dev_get_priv(dev);
+	int ret;
+
+	ret = ti_sci_proc_power_domain_on(&m4->tsp);
+	if (ret)
+		dev_err(dev, "cannot enable internal RAM loading, ret = %d\n",
+			ret);
+
+	return ret;
+}
+
+/*
+ * This function is the counterpart to k3_m4_prepare() and is used to assert
+ * the global reset on M4 cores. This completes the second step of powering
+ * down the M4 cores. The cores themselves are halted through the local reset
+ * in first step. This function is invoked in k3_m4_stop() after the local
+ * reset is asserted.
+ */
+static int k3_m4_unprepare(struct udevice *dev)
+{
+	struct k3_m4_privdata *m4 = dev_get_priv(dev);
+
+	return ti_sci_proc_power_domain_off(&m4->tsp);
+}
+
+/**
+ * k3_m4_load() - Load up the Remote processor image
+ * @dev:	rproc device pointer
+ * @addr:	Address at which image is available
+ * @size:	size of the image
+ *
+ * Return: 0 if all goes good, else appropriate error message.
+ */
+static int k3_m4_load(struct udevice *dev, ulong addr, ulong size)
+{
+	struct k3_m4_privdata *m4 = dev_get_priv(dev);
+	void *image_addr = (void *)addr;
+	int ret;
+
+	ret = ti_sci_proc_request(&m4->tsp);
+	if (ret)
+		return ret;
+
+	ret = k3_m4_prepare(dev);
+	if (ret) {
+		dev_err(dev, "Prepare failed for core %d\n",
+			m4->tsp.proc_id);
+		goto proc_release;
+	}
+
+	ti_secure_image_post_process(&image_addr, &size);
+
+	ret = rproc_elf_load_image(dev, addr, size);
+	if (ret < 0) {
+		dev_err(dev, "Loading elf failed %d\n", ret);
+		goto unprepare;
+	}
+
+unprepare:
+	if (ret)
+		k3_m4_unprepare(dev);
+proc_release:
+	ti_sci_proc_release(&m4->tsp);
+	return ret;
+}
+
+/**
+ * k3_m4_start() - Start the remote processor
+ * @dev:	rproc device pointer
+ *
+ * Return: 0 if all went ok, else return appropriate error
+ */
+static int k3_m4_start(struct udevice *dev)
+{
+	struct k3_m4_privdata *m4 = dev_get_priv(dev);
+	int ret;
+
+	ret = ti_sci_proc_request(&m4->tsp);
+	if (ret)
+		return ret;
+
+	ret = reset_deassert(&m4->m4_rst);
+
+	ti_sci_proc_release(&m4->tsp);
+
+	return ret;
+}
+
+static int k3_m4_stop(struct udevice *dev)
+{
+	struct k3_m4_privdata *m4 = dev_get_priv(dev);
+
+	ti_sci_proc_request(&m4->tsp);
+	reset_assert(&m4->m4_rst);
+	k3_m4_unprepare(dev);
+	ti_sci_proc_release(&m4->tsp);
+
+	return 0;
+}
+
+static void *k3_m4_da_to_va(struct udevice *dev, ulong da, ulong len)
+{
+	struct k3_m4_privdata *m4 = dev_get_priv(dev);
+	phys_addr_t bus_addr, dev_addr;
+	void __iomem *va = NULL;
+	size_t size;
+	u32 offset;
+	int i;
+
+	if (len <= 0)
+		return NULL;
+
+	for (i = 0; i < m4->num_mems; i++) {
+		bus_addr = m4->mem[i].bus_addr;
+		dev_addr = m4->mem[i].dev_addr;
+		size = m4->mem[i].size;
+
+		if (da >= dev_addr && ((da + len) <= (dev_addr + size))) {
+			offset = da - dev_addr;
+			va = m4->mem[i].cpu_addr + offset;
+			return (__force void *)va;
+		}
+
+		if (da >= bus_addr && (da + len) <= (bus_addr + size)) {
+			offset = da - bus_addr;
+			va = m4->mem[i].cpu_addr + offset;
+			return (__force void *)va;
+		}
+	}
+
+	/* Assume it is DDR region and return da */
+	return map_physmem(da, len, MAP_NOCACHE);
+}
+
+static const struct dm_rproc_ops k3_m4_ops = {
+	.load = k3_m4_load,
+	.start = k3_m4_start,
+	.stop = k3_m4_stop,
+	.device_to_virt = k3_m4_da_to_va,
+};
+
+static int ti_sci_proc_of_to_priv(struct udevice *dev, struct ti_sci_proc *tsp)
+{
+	u32 ids[2];
+	int ret;
+
+	tsp->sci = ti_sci_get_by_phandle(dev, "ti,sci");
+	if (IS_ERR(tsp->sci)) {
+		dev_err(dev, "ti_sci get failed: %ld\n", PTR_ERR(tsp->sci));
+		return PTR_ERR(tsp->sci);
+	}
+
+	ret = dev_read_u32_array(dev, "ti,sci-proc-ids", ids, 2);
+	if (ret) {
+		dev_err(dev, "Proc IDs not populated %d\n", ret);
+		return ret;
+	}
+
+	tsp->ops = &tsp->sci->ops.proc_ops;
+	tsp->proc_id = ids[0];
+	tsp->host_id = ids[1];
+	tsp->dev_id = dev_read_u32_default(dev, "ti,sci-dev-id",
+					   TI_SCI_RESOURCE_NULL);
+	if (tsp->dev_id == TI_SCI_RESOURCE_NULL) {
+		dev_err(dev, "Device ID not populated %d\n", ret);
+		return -ENODEV;
+	}
+
+	return 0;
+}
+
+static const struct k3_m4_mem_data am6_m4_mems[] = {
+	{ .name = "iram", .dev_addr = 0x0 },
+	{ .name = "dram", .dev_addr = 0x30000 },
+};
+
+static int k3_m4_of_get_memories(struct udevice *dev)
+{
+	struct k3_m4_privdata *m4 = dev_get_priv(dev);
+	int i;
+
+	m4->num_mems = ARRAY_SIZE(am6_m4_mems);
+	m4->mem = calloc(m4->num_mems, sizeof(*m4->mem));
+	if (!m4->mem)
+		return -ENOMEM;
+
+	for (i = 0; i < m4->num_mems; i++) {
+		m4->mem[i].bus_addr = dev_read_addr_size_name(dev,
+							      am6_m4_mems[i].name,
+					  (fdt_addr_t *)&m4->mem[i].size);
+		if (m4->mem[i].bus_addr == FDT_ADDR_T_NONE) {
+			dev_err(dev, "%s bus address not found\n",
+				am6_m4_mems[i].name);
+			return -EINVAL;
+		}
+		m4->mem[i].cpu_addr = map_physmem(m4->mem[i].bus_addr,
+						  m4->mem[i].size,
+						  MAP_NOCACHE);
+		m4->mem[i].dev_addr = am6_m4_mems[i].dev_addr;
+	}
+
+	return 0;
+}
+
+/**
+ * k3_of_to_priv() - generate private data from device tree
+ * @dev:	corresponding k3 m4 processor device
+ * @m4:		pointer to driver specific private data
+ *
+ * Return: 0 if all goes good, else appropriate error message.
+ */
+static int k3_m4_of_to_priv(struct udevice *dev, struct k3_m4_privdata *m4)
+{
+	int ret;
+
+	ret = reset_get_by_index(dev, 0, &m4->m4_rst);
+	if (ret) {
+		dev_err(dev, "reset_get() failed: %d\n", ret);
+		return ret;
+	}
+
+	ret = ti_sci_proc_of_to_priv(dev, &m4->tsp);
+	if (ret)
+		return ret;
+
+	ret =  k3_m4_of_get_memories(dev);
+	if (ret)
+		return ret;
+
+	m4->data = (struct k3_m4_boot_data *)dev_get_driver_data(dev);
+
+	return 0;
+}
+
+/**
+ * k3_m4_probe() - Basic probe
+ * @dev:	corresponding k3 remote processor device
+ *
+ * Return: 0 if all goes good, else appropriate error message.
+ */
+static int k3_m4_probe(struct udevice *dev)
+{
+	struct k3_m4_privdata *m4;
+	int ret;
+
+	m4 = dev_get_priv(dev);
+	ret = k3_m4_of_to_priv(dev, m4);
+	if (ret)
+		return ret;
+
+	/*
+	 * The M4 local resets are deasserted by default on Power-On-Reset.
+	 * Assert the local resets to ensure the M4s don't execute bogus code
+	 * in .load() callback when the module reset is released to support
+	 * internal memory loading. This is needed for M4 cores.
+	 */
+	reset_assert(&m4->m4_rst);
+
+	return 0;
+}
+
+static int k3_m4_remove(struct udevice *dev)
+{
+	struct k3_m4_privdata *m4 = dev_get_priv(dev);
+
+	free(m4->mem);
+
+	return 0;
+}
+
+static const struct k3_m4_boot_data m4_data = {
+	.boot_align_addr = SZ_1K,
+};
+
+static const struct udevice_id k3_m4_ids[] = {
+	{ .compatible = "ti,am64-m4fss", .data = (ulong)&m4_data, },
+	{}
+};
+
+U_BOOT_DRIVER(k3_m4) = {
+	.name = "k3_m4",
+	.of_match = k3_m4_ids,
+	.id = UCLASS_REMOTEPROC,
+	.ops = &k3_m4_ops,
+	.probe = k3_m4_probe,
+	.remove = k3_m4_remove,
+	.priv_auto = sizeof(struct k3_m4_privdata),
+};
diff --git a/drivers/remoteproc/ti_k3_r5f_rproc.c b/drivers/remoteproc/ti_k3_r5f_rproc.c
index d78b3fa1bbd..57268e7f8ff 100644
--- a/drivers/remoteproc/ti_k3_r5f_rproc.c
+++ b/drivers/remoteproc/ti_k3_r5f_rproc.c
@@ -886,6 +886,7 @@ static const struct udevice_id k3_r5f_rproc_ids[] = {
 	{ .compatible = "ti,j7200-r5f", .data = (ulong)&j7200_j721s2_data, },
 	{ .compatible = "ti,j721s2-r5f", .data = (ulong)&j7200_j721s2_data, },
 	{ .compatible = "ti,am62-r5f", .data = (ulong)&am62_data, },
+	{ .compatible = "ti,am64-r5f", .data = (ulong)&j7200_j721s2_data, },
 	{}
 };
 
@@ -930,6 +931,7 @@ static const struct udevice_id k3_r5fss_ids[] = {
 	{ .compatible = "ti,j7200-r5fss"},
 	{ .compatible = "ti,j721s2-r5fss"},
 	{ .compatible = "ti,am62-r5fss"},
+	{ .compatible = "ti,am64-r5fss"},
 	{}
 };
 
diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
index fe5c1214f57..a0d079c4555 100644
--- a/drivers/reset/Kconfig
+++ b/drivers/reset/Kconfig
@@ -49,6 +49,13 @@ config TEGRA186_RESET
 	  Enable support for manipulating Tegra's on-SoC reset signals via IPC
 	  requests to the BPMP (Boot and Power Management Processor).
 
+config RESET_AIROHA
+	bool "Reset controller driver for Airoha SoCs"
+	depends on DM_RESET && ARCH_AIROHA
+	default y
+	help
+	  Support for reset controller on Airoha SoCs.
+
 config RESET_TI_SCI
 	bool "TI System Control Interface (TI SCI) reset driver"
 	depends on DM_RESET && TI_SCI_PROTOCOL
@@ -235,4 +242,20 @@ config RESET_AT91
 	  This enables the Reset Controller driver support for Microchip/Atmel
 	  SoCs. Mainly used to expose assert/deassert methods to other drivers
 	  that require it.
+
+config RESET_RZG2L_USBPHY_CTRL
+	bool "Enable support for Renesas RZ/G2L USB 2.0 PHY control"
+	depends on DM_RESET
+	select REGULATOR_RZG2L_USBPHY
+	help
+	  Enable support for controlling USB 2.0 PHY resets on the Renesas
+	  RZ/G2L SoC. This is required for USB 2.0 functionality to work on this
+	  SoC.
+
+config RESET_SPACEMIT_K1
+	bool "Support for SPACEMIT's K1 Reset driver"
+	depends on DM_RESET
+	help
+	  Support for SPACEMIT's K1 Reset system. Basic Assert/Deassert
+	  is supported.
 endmenu
diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
index d99a78c9828..b9494396013 100644
--- a/drivers/reset/Makefile
+++ b/drivers/reset/Makefile
@@ -10,6 +10,7 @@ obj-$(CONFIG_STI_RESET) += sti-reset.o
 obj-$(CONFIG_STM32_RESET) += stm32-reset.o
 obj-$(CONFIG_TEGRA_CAR_RESET) += tegra-car-reset.o
 obj-$(CONFIG_TEGRA186_RESET) += tegra186-reset.o
+obj-$(CONFIG_RESET_AIROHA) += reset-airoha.o
 obj-$(CONFIG_RESET_TI_SCI) += reset-ti-sci.o
 obj-$(CONFIG_RESET_HSDK) += reset-hsdk.o
 obj-$(CONFIG_RESET_BCM6345) += reset-bcm6345.o
@@ -33,3 +34,5 @@ obj-$(CONFIG_RESET_ZYNQMP) += reset-zynqmp.o
 obj-$(CONFIG_RESET_DRA7) += reset-dra7.o
 obj-$(CONFIG_RESET_AT91) += reset-at91.o
 obj-$(CONFIG_$(PHASE_)RESET_JH7110) += reset-jh7110.o
+obj-$(CONFIG_RESET_RZG2L_USBPHY_CTRL) += reset-rzg2l-usbphy-ctrl.o
+obj-$(CONFIG_RESET_SPACEMIT_K1) += reset-spacemit-k1.o
diff --git a/drivers/reset/reset-airoha.c b/drivers/reset/reset-airoha.c
new file mode 100644
index 00000000000..e878af6167c
--- /dev/null
+++ b/drivers/reset/reset-airoha.c
@@ -0,0 +1,173 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Based on Linux drivers/clk/clk-en7523.c reworked
+ * and detached to a dedicated driver
+ *
+ * Author: Lorenzo Bianconi <lorenzo@kernel.org> (original driver)
+ *	   Christian Marangi <ansuelsmth@gmail.com>
+ */
+
+#include <dm.h>
+#include <linux/io.h>
+#include <reset-uclass.h>
+
+#include <dt-bindings/reset/airoha,en7581-reset.h>
+
+#define RST_NR_PER_BANK			32
+
+#define REG_RESET_CONTROL2		0x830
+#define REG_RESET_CONTROL1		0x834
+
+struct airoha_reset_priv {
+	const u16 *bank_ofs;
+	const u16 *idx_map;
+	void __iomem *base;
+};
+
+static const u16 en7581_rst_ofs[] = {
+	REG_RESET_CONTROL2,
+	REG_RESET_CONTROL1,
+};
+
+static const u16 en7581_rst_map[] = {
+	/* RST_CTRL2 */
+	[EN7581_XPON_PHY_RST]		= 0,
+	[EN7581_CPU_TIMER2_RST]		= 2,
+	[EN7581_HSUART_RST]		= 3,
+	[EN7581_UART4_RST]		= 4,
+	[EN7581_UART5_RST]		= 5,
+	[EN7581_I2C2_RST]		= 6,
+	[EN7581_XSI_MAC_RST]		= 7,
+	[EN7581_XSI_PHY_RST]		= 8,
+	[EN7581_NPU_RST]		= 9,
+	[EN7581_I2S_RST]		= 10,
+	[EN7581_TRNG_RST]		= 11,
+	[EN7581_TRNG_MSTART_RST]	= 12,
+	[EN7581_DUAL_HSI0_RST]		= 13,
+	[EN7581_DUAL_HSI1_RST]		= 14,
+	[EN7581_HSI_RST]		= 15,
+	[EN7581_DUAL_HSI0_MAC_RST]	= 16,
+	[EN7581_DUAL_HSI1_MAC_RST]	= 17,
+	[EN7581_HSI_MAC_RST]		= 18,
+	[EN7581_WDMA_RST]		= 19,
+	[EN7581_WOE0_RST]		= 20,
+	[EN7581_WOE1_RST]		= 21,
+	[EN7581_HSDMA_RST]		= 22,
+	[EN7581_TDMA_RST]		= 24,
+	[EN7581_EMMC_RST]		= 25,
+	[EN7581_SOE_RST]		= 26,
+	[EN7581_PCIE2_RST]		= 27,
+	[EN7581_XFP_MAC_RST]		= 28,
+	[EN7581_USB_HOST_P1_RST]	= 29,
+	[EN7581_USB_HOST_P1_U3_PHY_RST]	= 30,
+	/* RST_CTRL1 */
+	[EN7581_PCM1_ZSI_ISI_RST]	= RST_NR_PER_BANK + 0,
+	[EN7581_FE_PDMA_RST]		= RST_NR_PER_BANK + 1,
+	[EN7581_FE_QDMA_RST]		= RST_NR_PER_BANK + 2,
+	[EN7581_PCM_SPIWP_RST]		= RST_NR_PER_BANK + 4,
+	[EN7581_CRYPTO_RST]		= RST_NR_PER_BANK + 6,
+	[EN7581_TIMER_RST]		= RST_NR_PER_BANK + 8,
+	[EN7581_PCM1_RST]		= RST_NR_PER_BANK + 11,
+	[EN7581_UART_RST]		= RST_NR_PER_BANK + 12,
+	[EN7581_GPIO_RST]		= RST_NR_PER_BANK + 13,
+	[EN7581_GDMA_RST]		= RST_NR_PER_BANK + 14,
+	[EN7581_I2C_MASTER_RST]		= RST_NR_PER_BANK + 16,
+	[EN7581_PCM2_ZSI_ISI_RST]	= RST_NR_PER_BANK + 17,
+	[EN7581_SFC_RST]		= RST_NR_PER_BANK + 18,
+	[EN7581_UART2_RST]		= RST_NR_PER_BANK + 19,
+	[EN7581_GDMP_RST]		= RST_NR_PER_BANK + 20,
+	[EN7581_FE_RST]			= RST_NR_PER_BANK + 21,
+	[EN7581_USB_HOST_P0_RST]	= RST_NR_PER_BANK + 22,
+	[EN7581_GSW_RST]		= RST_NR_PER_BANK + 23,
+	[EN7581_SFC2_PCM_RST]		= RST_NR_PER_BANK + 25,
+	[EN7581_PCIE0_RST]		= RST_NR_PER_BANK + 26,
+	[EN7581_PCIE1_RST]		= RST_NR_PER_BANK + 27,
+	[EN7581_CPU_TIMER_RST]		= RST_NR_PER_BANK + 28,
+	[EN7581_PCIE_HB_RST]		= RST_NR_PER_BANK + 29,
+	[EN7581_XPON_MAC_RST]		= RST_NR_PER_BANK + 31,
+};
+
+static int airoha_reset_update(struct airoha_reset_priv *priv,
+			       unsigned long id, bool assert)
+{
+	void __iomem *addr = priv->base + priv->bank_ofs[id / RST_NR_PER_BANK];
+	u32 val;
+
+	val = readl(addr);
+	if (assert)
+		val |= BIT(id % RST_NR_PER_BANK);
+	else
+		val &= ~BIT(id % RST_NR_PER_BANK);
+	writel(val, addr);
+
+	return 0;
+}
+
+static int airoha_reset_assert(struct reset_ctl *reset_ctl)
+{
+	struct airoha_reset_priv *priv = dev_get_priv(reset_ctl->dev);
+	int id = reset_ctl->id;
+
+	return airoha_reset_update(priv, id, true);
+}
+
+static int airoha_reset_deassert(struct reset_ctl *reset_ctl)
+{
+	struct airoha_reset_priv *priv = dev_get_priv(reset_ctl->dev);
+	int id = reset_ctl->id;
+
+	return airoha_reset_update(priv, id, false);
+}
+
+static int airoha_reset_status(struct reset_ctl *reset_ctl)
+{
+	struct airoha_reset_priv *priv = dev_get_priv(reset_ctl->dev);
+	int id = reset_ctl->id;
+	void __iomem *addr;
+
+	addr = priv->base + priv->bank_ofs[id / RST_NR_PER_BANK];
+
+	return !!(readl(addr) & BIT(id % RST_NR_PER_BANK));
+}
+
+static int airoha_reset_xlate(struct reset_ctl *reset_ctl,
+			      struct ofnode_phandle_args *args)
+{
+	struct airoha_reset_priv *priv = dev_get_priv(reset_ctl->dev);
+
+	if (args->args[0] >= ARRAY_SIZE(en7581_rst_map))
+		return -EINVAL;
+
+	reset_ctl->id = priv->idx_map[args->args[0]];
+
+	return 0;
+}
+
+static struct reset_ops airoha_reset_ops = {
+	.of_xlate = airoha_reset_xlate,
+	.rst_assert = airoha_reset_assert,
+	.rst_deassert = airoha_reset_deassert,
+	.rst_status = airoha_reset_status,
+};
+
+static int airoha_reset_probe(struct udevice *dev)
+{
+	struct airoha_reset_priv *priv = dev_get_priv(dev);
+
+	priv->base = dev_remap_addr(dev);
+	if (!priv->base)
+		return -ENOMEM;
+
+	priv->bank_ofs = en7581_rst_ofs;
+	priv->idx_map = en7581_rst_map;
+
+	return 0;
+}
+
+U_BOOT_DRIVER(airoha_reset) = {
+	.name = "airoha-reset",
+	.id = UCLASS_RESET,
+	.probe = airoha_reset_probe,
+	.ops = &airoha_reset_ops,
+	.priv_auto = sizeof(struct airoha_reset_priv),
+};
diff --git a/drivers/reset/reset-rzg2l-usbphy-ctrl.c b/drivers/reset/reset-rzg2l-usbphy-ctrl.c
new file mode 100644
index 00000000000..622d7b9cf4f
--- /dev/null
+++ b/drivers/reset/reset-rzg2l-usbphy-ctrl.c
@@ -0,0 +1,142 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2024 Renesas Electronics Corporation
+ */
+
+#include <asm/io.h>
+#include <dm.h>
+#include <dm/device-internal.h>
+#include <dm/device_compat.h>
+#include <dm/lists.h>
+#include <renesas/rzg2l-usbphy.h>
+#include <reset-uclass.h>
+#include <reset.h>
+
+#define RESET			0x000
+
+#define RESET_SEL_PLLRESET	BIT(12)
+#define RESET_PLLRESET		BIT(8)
+
+#define RESET_SEL_P2RESET	BIT(5)
+#define RESET_SEL_P1RESET	BIT(4)
+#define RESET_PHYRST_2		BIT(1)
+#define RESET_PHYRST_1		BIT(0)
+
+#define PHY_RESET_MASK          (RESET_PHYRST_1 | RESET_PHYRST_2)
+
+#define NUM_PORTS		2
+
+static int rzg2l_usbphy_ctrl_assert(struct reset_ctl *reset_ctl)
+{
+	struct rzg2l_usbphy_ctrl_priv *priv = dev_get_priv(reset_ctl->dev);
+	u32 val;
+
+	val = readl(priv->regs + RESET);
+	val |= reset_ctl->id ? RESET_PHYRST_2 : RESET_PHYRST_1;
+
+	/* If both ports are in reset, we can also place the PLL into reset. */
+	if ((val & PHY_RESET_MASK) == PHY_RESET_MASK)
+		val |= RESET_PLLRESET;
+
+	writel(val, priv->regs + RESET);
+	return 0;
+}
+
+static int rzg2l_usbphy_ctrl_deassert(struct reset_ctl *reset_ctl)
+{
+	struct rzg2l_usbphy_ctrl_priv *priv = dev_get_priv(reset_ctl->dev);
+	u32 val = reset_ctl->id ? RESET_PHYRST_2 : RESET_PHYRST_1;
+
+	/* If either port is out of reset, the PLL must also be out of reset. */
+	val |= RESET_PLLRESET;
+
+	clrbits_le32(priv->regs + RESET, val);
+	return 0;
+}
+
+static int rzg2l_usbphy_ctrl_of_xlate(struct reset_ctl *reset_ctl,
+				      struct ofnode_phandle_args *args)
+{
+	if (args->args[0] >= NUM_PORTS)
+		return -EINVAL;
+
+	reset_ctl->id = args->args[0];
+	return 0;
+}
+
+struct reset_ops rzg2l_usbphy_ctrl_ops = {
+	.rst_assert = rzg2l_usbphy_ctrl_assert,
+	.rst_deassert = rzg2l_usbphy_ctrl_deassert,
+	.of_xlate = rzg2l_usbphy_ctrl_of_xlate,
+};
+
+static int rzg2l_usbphy_ctrl_probe(struct udevice *dev)
+{
+	struct rzg2l_usbphy_ctrl_priv *priv = dev_get_priv(dev);
+	struct reset_ctl rst;
+	int ret;
+
+	priv->regs = dev_read_addr(dev);
+
+	ret = reset_get_by_index(dev, 0, &rst);
+	if (ret < 0) {
+		dev_err(dev, "failed to get reset line: %d\n", ret);
+		return ret;
+	}
+
+	ret = reset_deassert(&rst);
+	if (ret < 0) {
+		dev_err(dev, "failed to de-assert reset line: %d\n", ret);
+		return ret;
+	}
+
+	/* put pll and phy into reset state */
+	setbits_le32(priv->regs + RESET,
+		     RESET_SEL_PLLRESET | RESET_PLLRESET |
+		     RESET_SEL_P1RESET | RESET_PHYRST_1 |
+		     RESET_SEL_P2RESET | RESET_PHYRST_2);
+
+	return 0;
+}
+
+static const struct udevice_id rzg2l_usbphy_ctrl_ids[] = {
+	{ .compatible = "renesas,rzg2l-usbphy-ctrl", },
+	{ /* sentinel */ }
+};
+
+static int rzg2l_usbphy_ctrl_bind(struct udevice *dev)
+{
+	struct driver *drv;
+	ofnode node;
+	int ret;
+
+	node = ofnode_find_subnode(dev_ofnode(dev), "regulator-vbus");
+	if (!ofnode_valid(node)) {
+		dev_err(dev, "Failed to find vbus regulator devicetree node\n");
+		return -ENOENT;
+	}
+
+	drv = lists_driver_lookup_name("rzg2l_usbphy_regulator");
+	if (!drv) {
+		dev_err(dev, "Failed to find vbus regulator driver\n");
+		return -ENOENT;
+	}
+
+	ret = device_bind(dev, drv, dev->name, NULL, node, NULL);
+	if (ret) {
+		dev_err(dev, "Failed to bind vbus regulator: %d\n", ret);
+		return ret;
+	}
+
+	return 0;
+}
+
+U_BOOT_DRIVER(rzg2l_usbphy_ctrl) = {
+	.name           = "rzg2l_usbphy_ctrl",
+	.id             = UCLASS_RESET,
+	.of_match       = rzg2l_usbphy_ctrl_ids,
+	.bind           = rzg2l_usbphy_ctrl_bind,
+	.probe          = rzg2l_usbphy_ctrl_probe,
+	.ops            = &rzg2l_usbphy_ctrl_ops,
+	.priv_auto      = sizeof(struct rzg2l_usbphy_ctrl_priv),
+};
diff --git a/drivers/reset/reset-spacemit-k1.c b/drivers/reset/reset-spacemit-k1.c
new file mode 100644
index 00000000000..613e002fc4f
--- /dev/null
+++ b/drivers/reset/reset-spacemit-k1.c
@@ -0,0 +1,548 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2022 Spacemit Inc.
+ * Copyright (C) 2025 Huan Zhou <pericycle.cc@gmail.com>
+ */
+
+#include <asm/io.h>
+#include <config.h>
+#include <dm.h>
+#include <dm/device_compat.h>
+#include <dm/device-internal.h>
+#include <dm/lists.h>
+#include <dt-bindings/reset/spacemit-k1-reset.h>
+#include <linux/bitops.h>
+#include <reset-uclass.h>
+
+/* APBC register offset */
+#define APBC_UART1_CLK_RST      0x0
+#define APBC_UART2_CLK_RST      0x4
+#define APBC_GPIO_CLK_RST       0x8
+#define APBC_PWM0_CLK_RST       0xc
+#define APBC_PWM1_CLK_RST       0x10
+#define APBC_PWM2_CLK_RST       0x14
+#define APBC_PWM3_CLK_RST       0x18
+#define APBC_TWSI8_CLK_RST      0x20
+#define APBC_UART3_CLK_RST      0x24
+#define APBC_RTC_CLK_RST        0x28
+#define APBC_TWSI0_CLK_RST      0x2c
+#define APBC_TWSI1_CLK_RST      0x30
+#define APBC_TIMERS1_CLK_RST    0x34
+#define APBC_TWSI2_CLK_RST      0x38
+#define APBC_AIB_CLK_RST        0x3c
+#define APBC_TWSI4_CLK_RST      0x40
+#define APBC_TIMERS2_CLK_RST    0x44
+#define APBC_ONEWIRE_CLK_RST    0x48
+#define APBC_TWSI5_CLK_RST      0x4c
+#define APBC_DRO_CLK_RST        0x58
+#define APBC_IR_CLK_RST         0x5c
+#define APBC_TWSI6_CLK_RST      0x60
+#define APBC_TWSI7_CLK_RST      0x68
+#define APBC_TSEN_CLK_RST       0x6c
+
+#define APBC_UART4_CLK_RST      0x70
+#define APBC_UART5_CLK_RST      0x74
+#define APBC_UART6_CLK_RST      0x78
+#define APBC_SSP3_CLK_RST       0x7c
+
+#define APBC_SSPA0_CLK_RST      0x80
+#define APBC_SSPA1_CLK_RST      0x84
+
+#define APBC_IPC_AP2AUD_CLK_RST 0x90
+#define APBC_UART7_CLK_RST      0x94
+#define APBC_UART8_CLK_RST      0x98
+#define APBC_UART9_CLK_RST      0x9c
+
+#define APBC_CAN0_CLK_RST       0xa0
+#define APBC_PWM4_CLK_RST       0xa8
+#define APBC_PWM5_CLK_RST       0xac
+#define APBC_PWM6_CLK_RST       0xb0
+#define APBC_PWM7_CLK_RST       0xb4
+#define APBC_PWM8_CLK_RST       0xb8
+#define APBC_PWM9_CLK_RST       0xbc
+#define APBC_PWM10_CLK_RST      0xc0
+#define APBC_PWM11_CLK_RST      0xc4
+#define APBC_PWM12_CLK_RST      0xc8
+#define APBC_PWM13_CLK_RST      0xcc
+#define APBC_PWM14_CLK_RST      0xd0
+#define APBC_PWM15_CLK_RST      0xd4
+#define APBC_PWM16_CLK_RST      0xd8
+#define APBC_PWM17_CLK_RST      0xdc
+#define APBC_PWM18_CLK_RST      0xe0
+#define APBC_PWM19_CLK_RST      0xe4
+/* end of APBC register offset */
+
+/* MPMU register offset */
+#define MPMU_WDTPCR     0x200
+/* end of MPMU register offset */
+
+/* APMU register offset */
+#define APMU_JPG_CLK_RES_CTRL       0x20
+#define APMU_CSI_CCIC2_CLK_RES_CTRL 0x24
+#define APMU_ISP_CLK_RES_CTRL       0x38
+#define APMU_LCD_CLK_RES_CTRL1      0x44
+#define APMU_LCD_SPI_CLK_RES_CTRL   0x48
+#define APMU_LCD_CLK_RES_CTRL2      0x4c
+#define APMU_CCIC_CLK_RES_CTRL      0x50
+#define APMU_SDH0_CLK_RES_CTRL      0x54
+#define APMU_SDH1_CLK_RES_CTRL      0x58
+#define APMU_USB_CLK_RES_CTRL       0x5c
+#define APMU_QSPI_CLK_RES_CTRL      0x60
+#define APMU_USB_CLK_RES_CTRL       0x5c
+#define APMU_DMA_CLK_RES_CTRL       0x64
+#define APMU_AES_CLK_RES_CTRL       0x68
+#define APMU_VPU_CLK_RES_CTRL       0xa4
+#define APMU_GPU_CLK_RES_CTRL       0xcc
+#define APMU_SDH2_CLK_RES_CTRL      0xe0
+#define APMU_PMUA_MC_CTRL           0xe8
+#define APMU_PMU_CC2_AP             0x100
+#define APMU_PMUA_EM_CLK_RES_CTRL   0x104
+
+#define APMU_AUDIO_CLK_RES_CTRL     0x14c
+#define APMU_HDMI_CLK_RES_CTRL      0x1B8
+
+#define APMU_PCIE_CLK_RES_CTRL_0    0x3cc
+#define APMU_PCIE_CLK_RES_CTRL_1    0x3d4
+#define APMU_PCIE_CLK_RES_CTRL_2    0x3dc
+
+#define APMU_EMAC0_CLK_RES_CTRL     0x3e4
+#define APMU_EMAC1_CLK_RES_CTRL     0x3ec
+/* end of APMU register offset */
+
+/* APBC2 register offset */
+#define APBC2_UART1_CLK_RST		0x00
+#define APBC2_SSP2_CLK_RST		0x04
+#define APBC2_TWSI3_CLK_RST		0x08
+#define APBC2_RTC_CLK_RST		0x0c
+#define APBC2_TIMERS0_CLK_RST	0x10
+#define APBC2_KPC_CLK_RST		0x14
+#define APBC2_GPIO_CLK_RST		0x1c
+/* end of APBC2 register offset */
+
+enum spacemit_reset_base_type {
+	RST_BASE_TYPE_MPMU       = 0,
+	RST_BASE_TYPE_APMU       = 1,
+	RST_BASE_TYPE_APBC       = 2,
+	RST_BASE_TYPE_APBS       = 3,
+	RST_BASE_TYPE_CIU        = 4,
+	RST_BASE_TYPE_DCIU       = 5,
+	RST_BASE_TYPE_DDRC       = 6,
+	RST_BASE_TYPE_AUDC       = 7,
+	RST_BASE_TYPE_APBC2      = 8,
+};
+
+struct spacemit_reset_signal {
+	u32 offset;
+	u32 mask;
+	u32 deassert_val;
+	u32 assert_val;
+	enum spacemit_reset_base_type type;
+};
+
+struct spacemit_reset_base {
+	void __iomem *mpmu_base;
+	void __iomem *apmu_base;
+	void __iomem *apbc_base;
+	void __iomem *apbs_base;
+	void __iomem *ciu_base;
+	void __iomem *dciu_base;
+	void __iomem *ddrc_base;
+	void __iomem *audio_ctrl_base;
+	void __iomem *apbc2_base;
+};
+
+struct spacemit_reset {
+	struct spacemit_reset_base io_base;
+	const struct spacemit_reset_signal *signals;
+};
+
+enum {
+	RESET_TWSI6_SPL = 0,
+	RESET_TWSI8_SPL,
+	RESET_SDH_AXI_SPL,
+	RESET_SDH0_SPL,
+	RESET_USB_AXI_SPL,
+	RESET_USBP1_AXI_SPL,
+	RESET_USB3_0_SPL,
+	RESET_QSPI_SPL,
+	RESET_QSPI_BUS_SPL,
+	RESET_AES_SPL,
+	RESET_SDH2_SPL,
+	RESET_NUMBER_SPL
+};
+
+static const struct spacemit_reset_signal
+	k1_reset_signals[RESET_NUMBER] = {
+	[RESET_UART1]   = { APBC_UART1_CLK_RST, BIT(2), 0, BIT(2), RST_BASE_TYPE_APBC },
+	[RESET_UART2]   = { APBC_UART2_CLK_RST, BIT(2), 0, BIT(2), RST_BASE_TYPE_APBC },
+	[RESET_GPIO]    = { APBC_GPIO_CLK_RST, BIT(2), 0,
+			BIT(2),
+			RST_BASE_TYPE_APBC },
+	[RESET_PWM0]    = { APBC_PWM0_CLK_RST,
+			BIT(2) | BIT(0),
+			BIT(0),
+			BIT(2),
+			RST_BASE_TYPE_APBC },
+	[RESET_PWM1]    = { APBC_PWM1_CLK_RST,
+			BIT(2) | BIT(0),
+			BIT(0),
+			BIT(2),
+			RST_BASE_TYPE_APBC },
+	[RESET_PWM2]    = { APBC_PWM2_CLK_RST,
+			BIT(2) | BIT(0),
+			BIT(0),
+			BIT(2),
+			RST_BASE_TYPE_APBC },
+	[RESET_PWM3]    = { APBC_PWM3_CLK_RST,
+			BIT(2) | BIT(0),
+			BIT(0),
+			BIT(2),
+			RST_BASE_TYPE_APBC },
+	[RESET_PWM4]    = { APBC_PWM4_CLK_RST,
+			BIT(2) | BIT(0),
+			BIT(0),
+			BIT(2),
+			RST_BASE_TYPE_APBC },
+	[RESET_PWM5]    = { APBC_PWM5_CLK_RST,
+			BIT(2) | BIT(0),
+			BIT(0),
+			BIT(2),
+			RST_BASE_TYPE_APBC },
+	[RESET_PWM6]    = { APBC_PWM6_CLK_RST,
+			BIT(2) | BIT(0),
+			BIT(0),
+			BIT(2),
+			RST_BASE_TYPE_APBC },
+	[RESET_PWM7]    = { APBC_PWM7_CLK_RST,
+			BIT(2) | BIT(0),
+			BIT(0),
+			BIT(2),
+			RST_BASE_TYPE_APBC },
+	[RESET_PWM8]    = { APBC_PWM8_CLK_RST,
+			BIT(2) | BIT(0),
+			BIT(0),
+			BIT(2),
+			RST_BASE_TYPE_APBC },
+	[RESET_PWM9]    = { APBC_PWM9_CLK_RST,
+			BIT(2) | BIT(0),
+			BIT(0),
+			BIT(2),
+			RST_BASE_TYPE_APBC },
+	[RESET_PWM10]   = { APBC_PWM10_CLK_RST,
+			BIT(2) | BIT(0),
+			BIT(0),
+			BIT(2),
+			RST_BASE_TYPE_APBC },
+	[RESET_PWM11]   = { APBC_PWM11_CLK_RST,
+			BIT(2) | BIT(0),
+			BIT(0),
+			BIT(2),
+			RST_BASE_TYPE_APBC },
+	[RESET_PWM12]   = { APBC_PWM12_CLK_RST,
+			BIT(2) | BIT(0),
+			BIT(0),
+			BIT(2),
+			RST_BASE_TYPE_APBC },
+	[RESET_PWM13]   = { APBC_PWM13_CLK_RST,
+			BIT(2) | BIT(0),
+			BIT(0),
+			BIT(2),
+			RST_BASE_TYPE_APBC },
+	[RESET_PWM14]   = { APBC_PWM14_CLK_RST,
+			BIT(2) | BIT(0),
+			BIT(0),
+			BIT(2),
+			RST_BASE_TYPE_APBC },
+	[RESET_PWM15]   = { APBC_PWM15_CLK_RST,
+			BIT(2) | BIT(0),
+			BIT(0),
+			BIT(2),
+			RST_BASE_TYPE_APBC },
+	[RESET_PWM16]   = { APBC_PWM16_CLK_RST,
+			BIT(2) | BIT(0),
+			BIT(0),
+			BIT(2),
+			RST_BASE_TYPE_APBC },
+	[RESET_PWM17]   = { APBC_PWM17_CLK_RST,
+			BIT(2) | BIT(0),
+			BIT(0),
+			BIT(2),
+			RST_BASE_TYPE_APBC },
+	[RESET_PWM18]   = { APBC_PWM18_CLK_RST,
+			BIT(2) | BIT(0),
+			BIT(0),
+			BIT(2),
+			RST_BASE_TYPE_APBC },
+	[RESET_PWM19]   = { APBC_PWM19_CLK_RST,
+			BIT(2) | BIT(0),
+			BIT(0),
+			BIT(2),
+			RST_BASE_TYPE_APBC },
+	[RESET_SSP3]    = { APBC_SSP3_CLK_RST, BIT(2), 0, BIT(2), RST_BASE_TYPE_APBC },
+	[RESET_UART3]   = { APBC_UART3_CLK_RST, BIT(2), 0, BIT(2), RST_BASE_TYPE_APBC },
+	[RESET_RTC]     = { APBC_RTC_CLK_RST, BIT(2), 0, BIT(2), RST_BASE_TYPE_APBC },
+	[RESET_TWSI0]   = { APBC_TWSI0_CLK_RST, BIT(2), 0, BIT(2), RST_BASE_TYPE_APBC },
+	[RESET_TIMERS1] = { APBC_TIMERS1_CLK_RST, BIT(2), 0, BIT(2), RST_BASE_TYPE_APBC },
+	[RESET_AIB]     = { APBC_AIB_CLK_RST, BIT(2), 0, BIT(2), RST_BASE_TYPE_APBC },
+	[RESET_TIMERS2] = { APBC_TIMERS2_CLK_RST, BIT(2), 0, BIT(2), RST_BASE_TYPE_APBC },
+	[RESET_ONEWIRE] = { APBC_ONEWIRE_CLK_RST, BIT(2), 0, BIT(2), RST_BASE_TYPE_APBC },
+	[RESET_SSPA0]   = { APBC_SSPA0_CLK_RST, BIT(2), 0, BIT(2), RST_BASE_TYPE_APBC },
+	[RESET_SSPA1]   = { APBC_SSPA1_CLK_RST, BIT(2), 0, BIT(2), RST_BASE_TYPE_APBC },
+	[RESET_DRO]     = { APBC_DRO_CLK_RST, BIT(2), 0, BIT(2), RST_BASE_TYPE_APBC },
+	[RESET_IR]      = { APBC_IR_CLK_RST, BIT(2), 0, BIT(2), RST_BASE_TYPE_APBC },
+	[RESET_TWSI1]   = { APBC_TWSI1_CLK_RST, BIT(2), 0, BIT(2), RST_BASE_TYPE_APBC },
+	[RESET_TSEN]    = { APBC_TSEN_CLK_RST, BIT(2), 0, BIT(2), RST_BASE_TYPE_APBC },
+	[RESET_TWSI2]   = { APBC_TWSI2_CLK_RST, BIT(2), 0, BIT(2), RST_BASE_TYPE_APBC },
+	[RESET_TWSI4]   = { APBC_TWSI4_CLK_RST, BIT(2), 0, BIT(2), RST_BASE_TYPE_APBC },
+	[RESET_TWSI5]   = { APBC_TWSI5_CLK_RST, BIT(2), 0, BIT(2), RST_BASE_TYPE_APBC },
+	[RESET_TWSI6]   = { APBC_TWSI6_CLK_RST, BIT(2), 0, BIT(2), RST_BASE_TYPE_APBC },
+	[RESET_TWSI7]   = { APBC_TWSI7_CLK_RST, BIT(2), 0, BIT(2), RST_BASE_TYPE_APBC },
+	[RESET_TWSI8]   = { APBC_TWSI8_CLK_RST, BIT(2), 0, BIT(2), RST_BASE_TYPE_APBC },
+	[RESET_IPC_AP2AUD]   = { APBC_IPC_AP2AUD_CLK_RST, BIT(2), 0, BIT(2), RST_BASE_TYPE_APBC },
+	[RESET_UART4]   = { APBC_UART4_CLK_RST, BIT(2), 0, BIT(2), RST_BASE_TYPE_APBC },
+	[RESET_UART5]   = { APBC_UART5_CLK_RST, BIT(2), 0, BIT(2), RST_BASE_TYPE_APBC },
+	[RESET_UART6]   = { APBC_UART6_CLK_RST, BIT(2), 0, BIT(2), RST_BASE_TYPE_APBC },
+	[RESET_UART7]   = { APBC_UART7_CLK_RST, BIT(2), 0, BIT(2), RST_BASE_TYPE_APBC },
+	[RESET_UART8]   = { APBC_UART8_CLK_RST, BIT(2), 0, BIT(2), RST_BASE_TYPE_APBC },
+	[RESET_UART9]   = { APBC_UART9_CLK_RST, BIT(2), 0, BIT(2), RST_BASE_TYPE_APBC },
+	[RESET_CAN0]    = { APBC_CAN0_CLK_RST, BIT(2), 0, BIT(2), RST_BASE_TYPE_APBC },
+	/* MPMU */
+	[RESET_WDT]     = { MPMU_WDTPCR, BIT(2), 0, BIT(2), RST_BASE_TYPE_MPMU },
+	/* APMU */
+	[RESET_JPG]     = { APMU_JPG_CLK_RES_CTRL, BIT(0), BIT(0), 0, RST_BASE_TYPE_APMU },
+	[RESET_CSI]     = { APMU_CSI_CCIC2_CLK_RES_CTRL, BIT(1), BIT(1), 0, RST_BASE_TYPE_APMU },
+	[RESET_CCIC2_PHY]   = { APMU_CSI_CCIC2_CLK_RES_CTRL,
+				BIT(2),
+				BIT(2),
+				0,
+				RST_BASE_TYPE_APMU },
+	[RESET_CCIC3_PHY]   = { APMU_CSI_CCIC2_CLK_RES_CTRL,
+				BIT(29),
+				BIT(29),
+				0,
+				RST_BASE_TYPE_APMU },
+	[RESET_ISP]     = { APMU_ISP_CLK_RES_CTRL, BIT(0), BIT(0), 0, RST_BASE_TYPE_APMU },
+	[RESET_ISP_AHB] = { APMU_ISP_CLK_RES_CTRL, BIT(3), BIT(3), 0, RST_BASE_TYPE_APMU },
+	[RESET_ISP_CI]  = { APMU_ISP_CLK_RES_CTRL, BIT(16), BIT(16), 0, RST_BASE_TYPE_APMU },
+	[RESET_ISP_CPP] = { APMU_ISP_CLK_RES_CTRL, BIT(27), BIT(27), 0, RST_BASE_TYPE_APMU },
+	[RESET_LCD]     = { APMU_LCD_CLK_RES_CTRL1, BIT(4), BIT(4), 0, RST_BASE_TYPE_APMU },
+	[RESET_DSI_ESC] = { APMU_LCD_CLK_RES_CTRL1, BIT(3), BIT(3), 0, RST_BASE_TYPE_APMU },
+	[RESET_V2D]     = { APMU_LCD_CLK_RES_CTRL1, BIT(27), BIT(27), 0, RST_BASE_TYPE_APMU },
+	[RESET_MIPI]    = { APMU_LCD_CLK_RES_CTRL1, BIT(15), BIT(15), 0, RST_BASE_TYPE_APMU },
+	[RESET_LCD_SPI] = { APMU_LCD_SPI_CLK_RES_CTRL, BIT(0), BIT(0), 0, RST_BASE_TYPE_APMU },
+	[RESET_LCD_SPI_BUS]     = { APMU_LCD_SPI_CLK_RES_CTRL,
+				BIT(4),
+				BIT(4),
+				0,
+				RST_BASE_TYPE_APMU },
+	[RESET_LCD_SPI_HBUS]    = { APMU_LCD_SPI_CLK_RES_CTRL,
+				BIT(2),
+				BIT(2),
+				0,
+				RST_BASE_TYPE_APMU },
+	[RESET_LCD_MCLK]    = { APMU_LCD_CLK_RES_CTRL2, BIT(9), BIT(9), 0, RST_BASE_TYPE_APMU },
+	[RESET_CCIC_4X]     = { APMU_CCIC_CLK_RES_CTRL, BIT(1), BIT(1), 0, RST_BASE_TYPE_APMU },
+	[RESET_CCIC1_PHY]   = { APMU_CCIC_CLK_RES_CTRL, BIT(2), BIT(2), 0, RST_BASE_TYPE_APMU },
+	[RESET_SDH_AXI]     = { APMU_SDH0_CLK_RES_CTRL, BIT(0), BIT(0), 0, RST_BASE_TYPE_APMU },
+	[RESET_SDH0]      = { APMU_SDH0_CLK_RES_CTRL, BIT(1), BIT(1), 0, RST_BASE_TYPE_APMU },
+	[RESET_SDH1]	  = { APMU_SDH1_CLK_RES_CTRL, BIT(1), BIT(1), 0, RST_BASE_TYPE_APMU },
+	[RESET_USB_AXI]	  = { APMU_USB_CLK_RES_CTRL, BIT(0), BIT(0), 0, RST_BASE_TYPE_APMU },
+	[RESET_USBP1_AXI] = { APMU_USB_CLK_RES_CTRL, BIT(4), BIT(4), 0, RST_BASE_TYPE_APMU },
+	[RESET_USB3_0]	  = { APMU_USB_CLK_RES_CTRL,
+				BIT(9) | BIT(10) | BIT(11),
+				BIT(9) | BIT(10) | BIT(11),
+				0,
+				RST_BASE_TYPE_APMU },
+	[RESET_QSPI]  = { APMU_QSPI_CLK_RES_CTRL, BIT(1), BIT(1), 0, RST_BASE_TYPE_APMU },
+	[RESET_QSPI_BUS]  = { APMU_QSPI_CLK_RES_CTRL, BIT(0), BIT(0), 0, RST_BASE_TYPE_APMU },
+	[RESET_DMA]	 = { APMU_DMA_CLK_RES_CTRL, BIT(0), BIT(0), 0, RST_BASE_TYPE_APMU },
+	[RESET_AES]	 = { APMU_AES_CLK_RES_CTRL, BIT(4), BIT(4), 0, RST_BASE_TYPE_APMU },
+	[RESET_VPU]	 = { APMU_VPU_CLK_RES_CTRL, BIT(0), BIT(0), 0, RST_BASE_TYPE_APMU },
+	[RESET_GPU]	 = { APMU_GPU_CLK_RES_CTRL, BIT(1), BIT(1), 0, RST_BASE_TYPE_APMU },
+	[RESET_SDH2] = { APMU_SDH2_CLK_RES_CTRL, BIT(1), BIT(1), 0, RST_BASE_TYPE_APMU },
+	[RESET_MC]	 = { APMU_PMUA_MC_CTRL, BIT(0), BIT(0), 0, RST_BASE_TYPE_APMU },
+	[RESET_EM_AXI]	= { APMU_PMUA_EM_CLK_RES_CTRL, BIT(0), BIT(0), 0, RST_BASE_TYPE_APMU },
+	[RESET_EM]	= { APMU_PMUA_EM_CLK_RES_CTRL, BIT(1), BIT(1), 0, RST_BASE_TYPE_APMU },
+	[RESET_AUDIO_SYS] = { APMU_AUDIO_CLK_RES_CTRL,
+				BIT(0) | BIT(2) | BIT(3),
+				BIT(0) | BIT(2) | BIT(3),
+				0,
+				RST_BASE_TYPE_APMU },
+	[RESET_HDMI]	 = { APMU_HDMI_CLK_RES_CTRL, BIT(9), BIT(9), 0, RST_BASE_TYPE_APMU },
+	[RESET_PCIE0]	 = { APMU_PCIE_CLK_RES_CTRL_0,
+				BIT(3) | BIT(4) | BIT(5) | BIT(8),
+				BIT(3) | BIT(4) | BIT(5),
+				BIT(8),
+				RST_BASE_TYPE_APMU },
+	[RESET_PCIE1]	 = { APMU_PCIE_CLK_RES_CTRL_1,
+				BIT(3) | BIT(4) | BIT(5) | BIT(8),
+				BIT(3) | BIT(4) | BIT(5),
+				BIT(8),
+				RST_BASE_TYPE_APMU },
+	[RESET_PCIE2]	 = { APMU_PCIE_CLK_RES_CTRL_2, 0x138, 0x38, 0x100, RST_BASE_TYPE_APMU },
+	[RESET_EMAC0]	 = { APMU_EMAC0_CLK_RES_CTRL, BIT(1), BIT(1), 0, RST_BASE_TYPE_APMU },
+	[RESET_EMAC1]	 = { APMU_EMAC1_CLK_RES_CTRL, BIT(1), BIT(1), 0, RST_BASE_TYPE_APMU },
+	[RESET_SEC_UART1]	= { APBC2_UART1_CLK_RST, BIT(2), 0, BIT(2), RST_BASE_TYPE_APBC2 },
+	[RESET_SEC_SSP2]	= { APBC2_SSP2_CLK_RST, BIT(2), 0, BIT(2), RST_BASE_TYPE_APBC2 },
+	[RESET_SEC_TWSI3]	= { APBC2_TWSI3_CLK_RST, BIT(2), 0, BIT(2), RST_BASE_TYPE_APBC2 },
+	[RESET_SEC_RTC]		= { APBC2_RTC_CLK_RST, BIT(2), 0, BIT(2), RST_BASE_TYPE_APBC2 },
+	[RESET_SEC_TIMERS0]	= { APBC2_TIMERS0_CLK_RST, BIT(2), 0, BIT(2), RST_BASE_TYPE_APBC2 },
+	[RESET_SEC_KPC]		= { APBC2_KPC_CLK_RST, BIT(2), 0, BIT(2), RST_BASE_TYPE_APBC2 },
+	[RESET_SEC_GPIO]	= { APBC2_GPIO_CLK_RST, BIT(2), 0, BIT(2), RST_BASE_TYPE_APBC2 },
+	};
+
+static u32 spacemit_reset_read(struct spacemit_reset *reset, u32 id)
+{
+	void __iomem *base;
+
+	switch (reset->signals[id].type) {
+	case RST_BASE_TYPE_APMU:
+		base = reset->io_base.apmu_base;
+		break;
+	case RST_BASE_TYPE_APBC:
+		base = reset->io_base.apbc_base;
+		break;
+	default:
+		base = reset->io_base.apbc_base;
+		break;
+	}
+
+	return readl(base + reset->signals[id].offset);
+}
+
+static void spacemit_reset_write(struct spacemit_reset *reset, u32 value, u32 id)
+{
+	void __iomem *base;
+
+	switch (reset->signals[id].type) {
+	case RST_BASE_TYPE_APMU:
+		base = reset->io_base.apmu_base;
+		break;
+	case RST_BASE_TYPE_APBC:
+		base = reset->io_base.apbc_base;
+		break;
+	default:
+		base = reset->io_base.apbc_base;
+		break;
+	}
+
+	writel(value, base + reset->signals[id].offset);
+}
+
+static void spacemit_reset_set(struct reset_ctl *rst, u32 id, bool assert)
+{
+	u32 value;
+	struct spacemit_reset *reset = dev_get_priv(rst->dev);
+
+	value = spacemit_reset_read(reset, id);
+
+	if (assert) {
+		value &= ~reset->signals[id].mask;
+		value |= reset->signals[id].assert_val;
+	} else {
+		value &= ~reset->signals[id].mask;
+		value |= reset->signals[id].deassert_val;
+	}
+
+	spacemit_reset_write(reset, value, id);
+}
+
+static int spacemit_reset_update(struct reset_ctl *rst, bool assert)
+{
+	if (rst->id < RESET_UART1 || rst->id >= RESET_NUMBER)
+		return 0;
+
+	/* can not write to twsi8 */
+	if (rst->id == RESET_TWSI8)
+		return 0;
+
+	spacemit_reset_set(rst, rst->id, assert);
+	return 0;
+}
+
+static int spacemit_reset_assert(struct reset_ctl *rst)
+{
+	return spacemit_reset_update(rst, true);
+}
+
+static int spacemit_reset_deassert(struct reset_ctl *rst)
+{
+	return spacemit_reset_update(rst, false);
+}
+
+static int spacemit_k1_reset_probe(struct udevice *dev)
+{
+	struct spacemit_reset *reset = dev_get_priv(dev);
+
+	reset->io_base.mpmu_base = (void *)dev_remap_addr_index(dev, 0);
+	if (!reset->io_base.mpmu_base) {
+		pr_err("failed to map mpmu registers\n");
+		goto out;
+	}
+
+	reset->io_base.apmu_base = (void *)dev_remap_addr_index(dev, 1);
+	if (!reset->io_base.apmu_base) {
+		pr_err("failed to map apmu registers\n");
+		goto out;
+	}
+
+	reset->io_base.apbc_base = (void *)dev_remap_addr_index(dev, 2);
+	if (!reset->io_base.apbc_base) {
+		pr_err("failed to map apbc registers\n");
+		goto out;
+	}
+
+	reset->io_base.apbs_base = (void *)dev_remap_addr_index(dev, 3);
+	if (!reset->io_base.apbs_base) {
+		pr_err("failed to map apbs registers\n");
+		goto out;
+	}
+
+	reset->io_base.ciu_base = (void *)dev_remap_addr_index(dev, 4);
+	if (!reset->io_base.ciu_base) {
+		pr_err("failed to map ciu registers\n");
+		goto out;
+	}
+
+	reset->io_base.dciu_base = (void *)dev_remap_addr_index(dev, 5);
+	if (!reset->io_base.dciu_base) {
+		pr_err("failed to map dragon ciu registers\n");
+		goto out;
+	}
+
+	reset->io_base.ddrc_base = (void *)dev_remap_addr_index(dev, 6);
+	if (!reset->io_base.ddrc_base) {
+		pr_err("failed to map ddrc registers\n");
+		goto out;
+	}
+
+	reset->io_base.apbc2_base = (void *)dev_remap_addr_index(dev, 7);
+	if (!reset->io_base.apbc2_base) {
+		pr_err("failed to map apbc2 registers\n");
+		goto out;
+	}
+
+	reset->signals = k1_reset_signals;
+
+out:
+	return 0;
+}
+
+const struct reset_ops k1_reset_ops = {
+	.rst_assert = spacemit_reset_assert,
+	.rst_deassert = spacemit_reset_deassert,
+};
+
+static const struct udevice_id k1_reset_ids[] = {
+	{ .compatible = "spacemit,k1-reset", },
+	{},
+};
+
+U_BOOT_DRIVER(k1_reset) = {
+	.name		= "spacemit,k1-reset",
+	.id		= UCLASS_RESET,
+	.ops		= &k1_reset_ops,
+	.of_match	= k1_reset_ids,
+	.probe		= spacemit_k1_reset_probe,
+	.priv_auto	= sizeof(struct spacemit_reset),
+};
diff --git a/drivers/rng/msm_rng.c b/drivers/rng/msm_rng.c
index f790d3b60f9..aab602c5ed0 100644
--- a/drivers/rng/msm_rng.c
+++ b/drivers/rng/msm_rng.c
@@ -44,6 +44,11 @@ static int msm_rng_read(struct udevice *dev, void *data, size_t len)
 	u32 *retdata = data;
 	size_t maxsize;
 	u32 val;
+	int ret;
+
+	ret = clk_enable(&priv->clk);
+	if (ret < 0)
+		return ret;
 
 	/* calculate max size bytes to transfer back to caller */
 	maxsize = min_t(size_t, MAX_HW_FIFO_SIZE, len);
@@ -66,6 +71,8 @@ static int msm_rng_read(struct udevice *dev, void *data, size_t len)
 			break;
 	} while (currsize < maxsize);
 
+	clk_disable(&priv->clk);
+
 	return 0;
 }
 
@@ -76,7 +83,7 @@ static int msm_rng_enable(struct msm_rng_priv *priv, int enable)
 	if (enable) {
 		/* Enable PRNG only if it is not already enabled */
 		val = readl_relaxed(priv->base + PRNG_CONFIG);
-		if (val & PRNG_CONFIG_HW_ENABLE) {
+		if (!(val & PRNG_CONFIG_HW_ENABLE)) {
 			val = readl_relaxed(priv->base + PRNG_LFSR_CFG);
 			val &= ~PRNG_LFSR_CFG_MASK;
 			val |= PRNG_LFSR_CFG_CLOCKS;
@@ -118,7 +125,9 @@ static int msm_rng_probe(struct udevice *dev)
 	if (ret < 0)
 		return ret;
 
-	return msm_rng_enable(priv, 1);
+	ret = msm_rng_enable(priv, 1);
+	clk_disable(&priv->clk);
+	return ret;
 }
 
 static int msm_rng_remove(struct udevice *dev)
diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
index c4f4a8d78df..84130524c2d 100644
--- a/drivers/serial/Kconfig
+++ b/drivers/serial/Kconfig
@@ -789,6 +789,12 @@ config SPL_SYS_NS16550_SERIAL
 	default y if SYS_NS16550_SERIAL || ARCH_SUNXI || ARCH_OMAP2PLUS
 	select SYS_NS16550
 
+config TPL_SYS_NS16550_SERIAL
+	bool "NS16550 UART or compatible legacy driver in TPL"
+	depends on TPL && !TPL_DM_SERIAL
+	default y if SPL_SYS_NS16550_SERIAL
+	select SYS_NS16550
+
 config SYS_NS16550
 	bool "NS16550 UART or compatible"
 	help
diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile
index ebe692a9963..2ef8ba20cf5 100644
--- a/drivers/serial/Makefile
+++ b/drivers/serial/Makefile
@@ -63,7 +63,4 @@ obj-$(CONFIG_XEN_SERIAL) += serial_xen.o
 obj-$(CONFIG_XTENSA_SEMIHOSTING_SERIAL) += serial_xtensa_semihosting.o
 obj-$(CONFIG_S5P4418_PL011_SERIAL) += serial_s5p4418_pl011.o
 
-ifndef CONFIG_XPL_BUILD
-obj-$(CONFIG_USB_TTY) += usbtty.o
-endif
 obj-$(CONFIG_UART4_SERIAL) += serial_adi_uart4.o
diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c
index 0e267d097c5..4f7de3ea215 100644
--- a/drivers/serial/ns16550.c
+++ b/drivers/serial/ns16550.c
@@ -112,9 +112,9 @@ static void serial_out_dynamic(struct ns16550_plat *plat, u8 *addr,
 	} else if (plat->reg_width == 4) {
 		if (plat->flags & NS16550_FLAG_ENDIAN) {
 			if (plat->flags & NS16550_FLAG_BE)
-				out_be32(addr, value);
+				out_be32((u32 *)addr, value);
 			else
-				out_le32(addr, value);
+				out_le32((u32 *)addr, value);
 		} else {
 			writel(value, addr);
 		}
@@ -132,9 +132,9 @@ static int serial_in_dynamic(struct ns16550_plat *plat, u8 *addr)
 	} else if (plat->reg_width == 4) {
 		if (plat->flags & NS16550_FLAG_ENDIAN) {
 			if (plat->flags & NS16550_FLAG_BE)
-				return in_be32(addr);
+				return in_be32((u32 *)addr);
 			else
-				return in_le32(addr);
+				return in_le32((u32 *)addr);
 		} else {
 			return readl(addr);
 		}
@@ -294,13 +294,9 @@ void ns16550_putc(struct ns16550 *com_port, char c)
 #if !CONFIG_IS_ENABLED(NS16550_MIN_FUNCTIONS)
 char ns16550_getc(struct ns16550 *com_port)
 {
-	while ((serial_in(&com_port->lsr) & UART_LSR_DR) == 0) {
-#if !defined(CONFIG_XPL_BUILD) && defined(CONFIG_USB_TTY)
-		extern void usbtty_poll(void);
-		usbtty_poll();
-#endif
+	while ((serial_in(&com_port->lsr) & UART_LSR_DR) == 0)
 		schedule();
-	}
+
 	return serial_in(&com_port->rbr);
 }
 
diff --git a/drivers/serial/sandbox.c b/drivers/serial/sandbox.c
index 77a1558db68..cc0491bc3c8 100644
--- a/drivers/serial/sandbox.c
+++ b/drivers/serial/sandbox.c
@@ -63,7 +63,7 @@ static int sandbox_serial_probe(struct udevice *dev)
 
 	if (state->term_raw != STATE_TERM_RAW)
 		disable_ctrlc(1);
-	membuff_init(&priv->buf, priv->serial_buf, sizeof(priv->serial_buf));
+	membuf_init(&priv->buf, priv->serial_buf, sizeof(priv->serial_buf));
 
 	return 0;
 }
@@ -138,15 +138,15 @@ static int sandbox_serial_pending(struct udevice *dev, bool input)
 		return 0;
 
 	os_usleep(100);
-	avail = membuff_putraw(&priv->buf, 100, false, &data);
+	avail = membuf_putraw(&priv->buf, 100, false, &data);
 	if (!avail)
 		return 1;	/* buffer full */
 
 	count = os_read(0, data, avail);
 	if (count > 0)
-		membuff_putraw(&priv->buf, count, true, &data);
+		membuf_putraw(&priv->buf, count, true, &data);
 
-	return membuff_avail(&priv->buf);
+	return membuf_avail(&priv->buf);
 }
 
 static int sandbox_serial_getc(struct udevice *dev)
@@ -156,7 +156,7 @@ static int sandbox_serial_getc(struct udevice *dev)
 	if (!sandbox_serial_pending(dev, true))
 		return -EAGAIN;	/* buffer empty */
 
-	return membuff_getbyte(&priv->buf);
+	return membuf_getbyte(&priv->buf);
 }
 
 #ifdef CONFIG_DEBUG_UART_SANDBOX
diff --git a/drivers/serial/serial_mxc.c b/drivers/serial/serial_mxc.c
index c5fd740be4d..28f4435d01d 100644
--- a/drivers/serial/serial_mxc.c
+++ b/drivers/serial/serial_mxc.c
@@ -3,6 +3,7 @@
  * (c) 2007 Sascha Hauer <s.hauer@pengutronix.de>
  */
 
+#include <clk.h>
 #include <dm.h>
 #include <errno.h>
 #include <watchdog.h>
@@ -312,7 +313,17 @@ int mxc_serial_setbrg(struct udevice *dev, int baudrate)
 static int mxc_serial_probe(struct udevice *dev)
 {
 	struct mxc_serial_plat *plat = dev_get_plat(dev);
+#if CONFIG_IS_ENABLED(CLK_CCF)
+	int ret;
 
+	ret = clk_get_bulk(dev, &plat->clks);
+	if (ret)
+		return ret;
+
+	ret = clk_enable_bulk(&plat->clks);
+	if (ret)
+		return ret;
+#endif
 	_mxc_serial_init(plat->reg, plat->use_dte);
 
 	return 0;
diff --git a/drivers/serial/serial_stm32.c b/drivers/serial/serial_stm32.c
index 1ee58142b3f..1675a9cb9d1 100644
--- a/drivers/serial/serial_stm32.c
+++ b/drivers/serial/serial_stm32.c
@@ -299,13 +299,19 @@ static inline struct stm32_uart_info *_debug_uart_info(void)
 
 static inline void _debug_uart_init(void)
 {
-	void __iomem *base = (void __iomem *)CONFIG_VAL(DEBUG_UART_BASE);
-	struct stm32_uart_info *uart_info = _debug_uart_info();
+	void __maybe_unused __iomem *base = (void __iomem *)CONFIG_VAL(DEBUG_UART_BASE);
+	struct stm32_uart_info *uart_info __maybe_unused = _debug_uart_info();
 
-	_stm32_serial_init(base, uart_info);
-	_stm32_serial_setbrg(base, uart_info,
-			     CONFIG_DEBUG_UART_CLOCK,
-			     CONFIG_BAUDRATE);
+	/*
+	 * debug_uart_init() is only usable when SPL_BUILD is enabled
+	 * (STM32MP1 case only)
+	 */
+	if (IS_ENABLED(CONFIG_DEBUG_UART) && IS_ENABLED(CONFIG_SPL_BUILD)) {
+		_stm32_serial_init(base, uart_info);
+		_stm32_serial_setbrg(base, uart_info,
+				     CONFIG_DEBUG_UART_CLOCK,
+				     CONFIG_BAUDRATE);
+	}
 }
 
 static inline void _debug_uart_putc(int c)
diff --git a/drivers/serial/usbtty.c b/drivers/serial/usbtty.c
deleted file mode 100644
index b7d77fbb6a9..00000000000
--- a/drivers/serial/usbtty.c
+++ /dev/null
@@ -1,983 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2003
- * Gerry Hamel, geh@ti.com, Texas Instruments
- *
- * (C) Copyright 2006
- * Bryan O'Donoghue, bodonoghue@codehermit.ie
- */
-
-#include <config.h>
-#include <circbuf.h>
-#include <env.h>
-#include <serial.h>
-#include <stdio_dev.h>
-#include <asm/unaligned.h>
-#include "usbtty.h"
-#include "usb_cdc_acm.h"
-#include "usbdescriptors.h"
-
-#ifdef DEBUG
-#define TTYDBG(fmt,args...)\
-	serial_printf("[%s] %s %d: "fmt, __FILE__,__FUNCTION__,__LINE__,##args)
-#else
-#define TTYDBG(fmt,args...) do{}while(0)
-#endif
-
-#if 1
-#define TTYERR(fmt,args...)\
-	serial_printf("ERROR![%s] %s %d: "fmt, __FILE__,__FUNCTION__,\
-	__LINE__,##args)
-#else
-#define TTYERR(fmt,args...) do{}while(0)
-#endif
-
-/*
- * Defines
- */
-#define NUM_CONFIGS    1
-#define MAX_INTERFACES 2
-#define NUM_ENDPOINTS  3
-#define ACM_TX_ENDPOINT 3
-#define ACM_RX_ENDPOINT 2
-#define GSERIAL_TX_ENDPOINT 2
-#define GSERIAL_RX_ENDPOINT 1
-#define NUM_ACM_INTERFACES 2
-#define NUM_GSERIAL_INTERFACES 1
-#define CFG_USBD_DATA_INTERFACE_STR "Bulk Data Interface"
-#define CFG_USBD_CTRL_INTERFACE_STR "Control Interface"
-
-/*
- * Buffers to hold input and output data
- */
-#define USBTTY_BUFFER_SIZE 2048
-static circbuf_t usbtty_input;
-static circbuf_t usbtty_output;
-
-/*
- * Instance variables
- */
-static struct stdio_dev usbttydev;
-static struct usb_device_instance device_instance[1];
-static struct usb_bus_instance bus_instance[1];
-static struct usb_configuration_instance config_instance[NUM_CONFIGS];
-static struct usb_interface_instance interface_instance[MAX_INTERFACES];
-static struct usb_alternate_instance alternate_instance[MAX_INTERFACES];
-/* one extra for control endpoint */
-static struct usb_endpoint_instance endpoint_instance[NUM_ENDPOINTS+1];
-
-/*
- * Global flag
- */
-int usbtty_configured_flag = 0;
-
-/*
- * Serial number
- */
-static char serial_number[16];
-
-/*
- * Descriptors, Strings, Local variables.
- */
-
-/* defined and used by gadget/ep0.c */
-extern struct usb_string_descriptor **usb_strings;
-
-/* Indicies, References */
-static unsigned short rx_endpoint = 0;
-static unsigned short tx_endpoint = 0;
-static unsigned short interface_count = 0;
-static struct usb_string_descriptor *usbtty_string_table[STR_COUNT];
-
-/* USB Descriptor Strings */
-static u8 wstrLang[4] = {4,USB_DT_STRING,0x9,0x4};
-static u8 wstrManufacturer[2 + 2*(sizeof(CONFIG_USBD_MANUFACTURER)-1)];
-static u8 wstrProduct[2 + 2*(sizeof(CONFIG_USBD_PRODUCT_NAME)-1)];
-static u8 wstrSerial[2 + 2*(sizeof(serial_number) - 1)];
-static u8 wstrConfiguration[2 + 2*(sizeof(CFG_USBD_CONFIGURATION_STR)-1)];
-static u8 wstrDataInterface[2 + 2*(sizeof(CFG_USBD_DATA_INTERFACE_STR)-1)];
-static u8 wstrCtrlInterface[2 + 2*(sizeof(CFG_USBD_DATA_INTERFACE_STR)-1)];
-
-/* Standard USB Data Structures */
-static struct usb_interface_descriptor interface_descriptors[MAX_INTERFACES];
-static struct usb_endpoint_descriptor *ep_descriptor_ptrs[NUM_ENDPOINTS];
-static struct usb_configuration_descriptor	*configuration_descriptor = 0;
-static struct usb_device_descriptor device_descriptor = {
-	.bLength = sizeof(struct usb_device_descriptor),
-	.bDescriptorType =	USB_DT_DEVICE,
-	.bcdUSB =		cpu_to_le16(USB_BCD_VERSION),
-	.bDeviceSubClass =	0x00,
-	.bDeviceProtocol =	0x00,
-	.bMaxPacketSize0 =	EP0_MAX_PACKET_SIZE,
-	.idVendor =		cpu_to_le16(CONFIG_USBD_VENDORID),
-	.bcdDevice =		cpu_to_le16(USBTTY_BCD_DEVICE),
-	.iManufacturer =	STR_MANUFACTURER,
-	.iProduct =		STR_PRODUCT,
-	.iSerialNumber =	STR_SERIAL,
-	.bNumConfigurations =	NUM_CONFIGS
-};
-
-/*
- * Static CDC ACM specific descriptors
- */
-
-struct acm_config_desc {
-	struct usb_configuration_descriptor configuration_desc;
-
-	/* Master Interface */
-	struct usb_interface_descriptor interface_desc;
-
-	struct usb_class_header_function_descriptor usb_class_header;
-	struct usb_class_call_management_descriptor usb_class_call_mgt;
-	struct usb_class_abstract_control_descriptor usb_class_acm;
-	struct usb_class_union_function_descriptor usb_class_union;
-	struct usb_endpoint_descriptor notification_endpoint;
-
-	/* Slave Interface */
-	struct usb_interface_descriptor data_class_interface;
-	struct usb_endpoint_descriptor data_endpoints[NUM_ENDPOINTS-1];
-} __attribute__((packed));
-
-static struct acm_config_desc acm_configuration_descriptors[NUM_CONFIGS] = {
-	{
-		.configuration_desc ={
-			.bLength =
-				sizeof(struct usb_configuration_descriptor),
-			.bDescriptorType = USB_DT_CONFIG,
-			.wTotalLength =
-				cpu_to_le16(sizeof(struct acm_config_desc)),
-			.bNumInterfaces = NUM_ACM_INTERFACES,
-			.bConfigurationValue = 1,
-			.iConfiguration = STR_CONFIG,
-			.bmAttributes =
-				BMATTRIBUTE_SELF_POWERED|BMATTRIBUTE_RESERVED,
-			.bMaxPower = USBTTY_MAXPOWER
-		},
-		/* Interface 1 */
-		.interface_desc = {
-			.bLength  = sizeof(struct usb_interface_descriptor),
-			.bDescriptorType = USB_DT_INTERFACE,
-			.bInterfaceNumber = 0,
-			.bAlternateSetting = 0,
-			.bNumEndpoints = 0x01,
-			.bInterfaceClass =
-				COMMUNICATIONS_INTERFACE_CLASS_CONTROL,
-			.bInterfaceSubClass = COMMUNICATIONS_ACM_SUBCLASS,
-			.bInterfaceProtocol = COMMUNICATIONS_V25TER_PROTOCOL,
-			.iInterface = STR_CTRL_INTERFACE,
-		},
-		.usb_class_header = {
-			.bFunctionLength	=
-				sizeof(struct usb_class_header_function_descriptor),
-			.bDescriptorType	= CS_INTERFACE,
-			.bDescriptorSubtype	= USB_ST_HEADER,
-			.bcdCDC	= cpu_to_le16(110),
-		},
-		.usb_class_call_mgt = {
-			.bFunctionLength	=
-				sizeof(struct usb_class_call_management_descriptor),
-			.bDescriptorType	= CS_INTERFACE,
-			.bDescriptorSubtype	= USB_ST_CMF,
-			.bmCapabilities		= 0x00,
-			.bDataInterface		= 0x01,
-		},
-		.usb_class_acm = {
-			.bFunctionLength	=
-				sizeof(struct usb_class_abstract_control_descriptor),
-			.bDescriptorType	= CS_INTERFACE,
-			.bDescriptorSubtype	= USB_ST_ACMF,
-			.bmCapabilities		= 0x00,
-		},
-		.usb_class_union = {
-			.bFunctionLength	=
-				sizeof(struct usb_class_union_function_descriptor),
-			.bDescriptorType	= CS_INTERFACE,
-			.bDescriptorSubtype	= USB_ST_UF,
-			.bMasterInterface	= 0x00,
-			.bSlaveInterface0	= 0x01,
-		},
-		.notification_endpoint = {
-			.bLength =
-				sizeof(struct usb_endpoint_descriptor),
-			.bDescriptorType	= USB_DT_ENDPOINT,
-			.bEndpointAddress	= UDC_INT_ENDPOINT | USB_DIR_IN,
-			.bmAttributes		= USB_ENDPOINT_XFER_INT,
-			.wMaxPacketSize
-				= cpu_to_le16(CFG_USBD_SERIAL_INT_PKTSIZE),
-			.bInterval		= 0xFF,
-		},
-
-		/* Interface 2 */
-		.data_class_interface = {
-			.bLength		=
-				sizeof(struct usb_interface_descriptor),
-			.bDescriptorType	= USB_DT_INTERFACE,
-			.bInterfaceNumber	= 0x01,
-			.bAlternateSetting	= 0x00,
-			.bNumEndpoints		= 0x02,
-			.bInterfaceClass	=
-				COMMUNICATIONS_INTERFACE_CLASS_DATA,
-			.bInterfaceSubClass	= DATA_INTERFACE_SUBCLASS_NONE,
-			.bInterfaceProtocol	= DATA_INTERFACE_PROTOCOL_NONE,
-			.iInterface		= STR_DATA_INTERFACE,
-		},
-		.data_endpoints = {
-			{
-				.bLength		=
-					sizeof(struct usb_endpoint_descriptor),
-				.bDescriptorType	= USB_DT_ENDPOINT,
-				.bEndpointAddress	= UDC_OUT_ENDPOINT | USB_DIR_OUT,
-				.bmAttributes		=
-					USB_ENDPOINT_XFER_BULK,
-				.wMaxPacketSize		=
-					cpu_to_le16(CFG_USBD_SERIAL_BULK_PKTSIZE),
-				.bInterval		= 0xFF,
-			},
-			{
-				.bLength		=
-					sizeof(struct usb_endpoint_descriptor),
-				.bDescriptorType	= USB_DT_ENDPOINT,
-				.bEndpointAddress	= UDC_IN_ENDPOINT | USB_DIR_IN,
-				.bmAttributes		=
-					USB_ENDPOINT_XFER_BULK,
-				.wMaxPacketSize		=
-					cpu_to_le16(CFG_USBD_SERIAL_BULK_PKTSIZE),
-				.bInterval		= 0xFF,
-			},
-		},
-	},
-};
-
-static struct rs232_emu rs232_desc={
-		.dter		=	115200,
-		.stop_bits	=	0x00,
-		.parity		=	0x00,
-		.data_bits	=	0x08
-};
-
-/*
- * Static Generic Serial specific data
- */
-
-struct gserial_config_desc {
-
-	struct usb_configuration_descriptor configuration_desc;
-	struct usb_interface_descriptor	interface_desc[NUM_GSERIAL_INTERFACES];
-	struct usb_endpoint_descriptor data_endpoints[NUM_ENDPOINTS];
-
-} __attribute__((packed));
-
-static struct gserial_config_desc
-gserial_configuration_descriptors[NUM_CONFIGS] ={
-	{
-		.configuration_desc ={
-			.bLength = sizeof(struct usb_configuration_descriptor),
-			.bDescriptorType = USB_DT_CONFIG,
-			.wTotalLength =
-				cpu_to_le16(sizeof(struct gserial_config_desc)),
-			.bNumInterfaces = NUM_GSERIAL_INTERFACES,
-			.bConfigurationValue = 1,
-			.iConfiguration = STR_CONFIG,
-			.bmAttributes =
-				BMATTRIBUTE_SELF_POWERED|BMATTRIBUTE_RESERVED,
-			.bMaxPower = USBTTY_MAXPOWER
-		},
-		.interface_desc = {
-			{
-				.bLength  =
-					sizeof(struct usb_interface_descriptor),
-				.bDescriptorType = USB_DT_INTERFACE,
-				.bInterfaceNumber = 0,
-				.bAlternateSetting = 0,
-				.bNumEndpoints = NUM_ENDPOINTS,
-				.bInterfaceClass =
-					COMMUNICATIONS_INTERFACE_CLASS_VENDOR,
-				.bInterfaceSubClass =
-					COMMUNICATIONS_NO_SUBCLASS,
-				.bInterfaceProtocol =
-					COMMUNICATIONS_NO_PROTOCOL,
-				.iInterface = STR_DATA_INTERFACE
-			},
-		},
-		.data_endpoints  = {
-			{
-				.bLength =
-					sizeof(struct usb_endpoint_descriptor),
-				.bDescriptorType =	USB_DT_ENDPOINT,
-				.bEndpointAddress =	UDC_OUT_ENDPOINT | USB_DIR_OUT,
-				.bmAttributes =		USB_ENDPOINT_XFER_BULK,
-				.wMaxPacketSize =
-					cpu_to_le16(CFG_USBD_SERIAL_OUT_PKTSIZE),
-				.bInterval=		0xFF,
-			},
-			{
-				.bLength =
-					sizeof(struct usb_endpoint_descriptor),
-				.bDescriptorType =	USB_DT_ENDPOINT,
-				.bEndpointAddress =	UDC_IN_ENDPOINT | USB_DIR_IN,
-				.bmAttributes =		USB_ENDPOINT_XFER_BULK,
-				.wMaxPacketSize =
-					cpu_to_le16(CFG_USBD_SERIAL_IN_PKTSIZE),
-				.bInterval =		0xFF,
-			},
-			{
-				.bLength =
-					sizeof(struct usb_endpoint_descriptor),
-				.bDescriptorType =	USB_DT_ENDPOINT,
-				.bEndpointAddress =	UDC_INT_ENDPOINT | USB_DIR_IN,
-				.bmAttributes =		USB_ENDPOINT_XFER_INT,
-				.wMaxPacketSize =
-					cpu_to_le16(CFG_USBD_SERIAL_INT_PKTSIZE),
-				.bInterval =		0xFF,
-			},
-		},
-	},
-};
-
-/*
- * Static Function Prototypes
- */
-
-static void usbtty_init_strings (void);
-static void usbtty_init_instances (void);
-static void usbtty_init_endpoints (void);
-static void usbtty_init_terminal_type(short type);
-static void usbtty_event_handler (struct usb_device_instance *device,
-				usb_device_event_t event, int data);
-static int usbtty_cdc_setup(struct usb_device_request *request,
-				struct urb *urb);
-static int usbtty_configured (void);
-static int write_buffer (circbuf_t * buf);
-static int fill_buffer (circbuf_t * buf);
-
-void usbtty_poll (void);
-
-/* utility function for converting char* to wide string used by USB */
-static void str2wide (char *str, u16 * wide)
-{
-	int i;
-	for (i = 0; i < strlen (str) && str[i]; i++){
-		#if defined(__LITTLE_ENDIAN)
-			wide[i] = (u16) str[i];
-		#elif defined(__BIG_ENDIAN)
-			wide[i] = ((u16)(str[i])<<8);
-		#else
-			#error "__LITTLE_ENDIAN or __BIG_ENDIAN undefined"
-		#endif
-	}
-}
-
-/*
- * Test whether a character is in the RX buffer
- */
-
-int usbtty_tstc(struct stdio_dev *dev)
-{
-	struct usb_endpoint_instance *endpoint =
-		&endpoint_instance[rx_endpoint];
-
-	/* If no input data exists, allow more RX to be accepted */
-	if(usbtty_input.size <= 0){
-		udc_unset_nak(endpoint->endpoint_address&0x03);
-	}
-
-	usbtty_poll ();
-	return (usbtty_input.size > 0);
-}
-
-/*
- * Read a single byte from the usb client port. Returns 1 on success, 0
- * otherwise. When the function is succesfull, the character read is
- * written into its argument c.
- */
-
-int usbtty_getc(struct stdio_dev *dev)
-{
-	char c;
-	struct usb_endpoint_instance *endpoint =
-		&endpoint_instance[rx_endpoint];
-
-	while (usbtty_input.size <= 0) {
-		udc_unset_nak(endpoint->endpoint_address&0x03);
-		usbtty_poll ();
-	}
-
-	buf_pop (&usbtty_input, &c, 1);
-	udc_set_nak(endpoint->endpoint_address&0x03);
-
-	return c;
-}
-
-/*
- * Output a single byte to the usb client port.
- */
-void usbtty_putc(struct stdio_dev *dev, const char c)
-{
-	if (!usbtty_configured ())
-		return;
-
-	/* If \n, also do \r */
-	if (c == '\n')
-		buf_push (&usbtty_output, "\r", 1);
-
-	buf_push(&usbtty_output, &c, 1);
-
-	/* Poll at end to handle new data... */
-	if ((usbtty_output.size + 2) >= usbtty_output.totalsize) {
-		usbtty_poll ();
-	}
-}
-
-/* usbtty_puts() helper function for finding the next '\n' in a string */
-static int next_nl_pos (const char *s)
-{
-	int i;
-
-	for (i = 0; s[i] != '\0'; i++) {
-		if (s[i] == '\n')
-			return i;
-	}
-	return i;
-}
-
-/*
- * Output a string to the usb client port - implementing flow control
- */
-
-static void __usbtty_puts (const char *str, int len)
-{
-	int maxlen = usbtty_output.totalsize;
-	int space, n;
-
-	/* break str into chunks < buffer size, if needed */
-	while (len > 0) {
-		usbtty_poll ();
-
-		space = maxlen - usbtty_output.size;
-		/* Empty buffer here, if needed, to ensure space... */
-		if (space) {
-			write_buffer (&usbtty_output);
-
-			n = min(space, min(len, maxlen));
-			buf_push (&usbtty_output, str, n);
-
-			str += n;
-			len -= n;
-		}
-	}
-}
-
-void usbtty_puts(struct stdio_dev *dev, const char *str)
-{
-	int n;
-	int len;
-
-	if (!usbtty_configured ())
-		return;
-
-	len = strlen (str);
-	/* add '\r' for each '\n' */
-	while (len > 0) {
-		n = next_nl_pos (str);
-
-		if (str[n] == '\n') {
-			__usbtty_puts(str, n);
-			__usbtty_puts("\r\n", 2);
-			str += (n + 1);
-			len -= (n + 1);
-		} else {
-			/* No \n found.	 All done. */
-			__usbtty_puts (str, n);
-			break;
-		}
-	}
-
-	/* Poll at end to handle new data... */
-	usbtty_poll ();
-}
-
-/*
- * Initialize the usb client port.
- *
- */
-int drv_usbtty_init (void)
-{
-	int rc;
-	char * sn;
-	char * tt;
-	int snlen;
-
-	/* Get serial number */
-	sn = env_get("serial#");
-	if (!sn)
-		sn = "000000000000";
-	snlen = strlen(sn);
-	if (snlen > sizeof(serial_number) - 1) {
-		printf ("Warning: serial number %s is too long (%d > %lu)\n",
-			sn, snlen, (ulong)(sizeof(serial_number) - 1));
-		snlen = sizeof(serial_number) - 1;
-	}
-	memcpy (serial_number, sn, snlen);
-	serial_number[snlen] = '\0';
-
-	/* Decide on which type of UDC device to be.
-	 */
-	tt = env_get("usbtty");
-	if (!tt)
-		tt = "generic";
-	usbtty_init_terminal_type(strcmp(tt,"cdc_acm"));
-
-	/* prepare buffers... */
-	buf_init (&usbtty_input, USBTTY_BUFFER_SIZE);
-	buf_init (&usbtty_output, USBTTY_BUFFER_SIZE);
-
-	/* Now, set up USB controller and infrastructure */
-	udc_init ();		/* Basic USB initialization */
-
-	usbtty_init_strings ();
-	usbtty_init_instances ();
-
-	usbtty_init_endpoints ();
-
-	udc_startup_events (device_instance);/* Enable dev, init udc pointers */
-	udc_connect ();		/* Enable pullup for host detection */
-
-	/* Device initialization */
-	memset (&usbttydev, 0, sizeof (usbttydev));
-
-	strcpy (usbttydev.name, "usbtty");
-	usbttydev.ext = 0;	/* No extensions */
-	usbttydev.flags = DEV_FLAGS_INPUT | DEV_FLAGS_OUTPUT;
-	usbttydev.tstc = usbtty_tstc;	/* 'tstc' function */
-	usbttydev.getc = usbtty_getc;	/* 'getc' function */
-	usbttydev.putc = usbtty_putc;	/* 'putc' function */
-	usbttydev.puts = usbtty_puts;	/* 'puts' function */
-
-	rc = stdio_register (&usbttydev);
-
-	return (rc == 0) ? 1 : rc;
-}
-
-static void usbtty_init_strings (void)
-{
-	struct usb_string_descriptor *string;
-
-	usbtty_string_table[STR_LANG] =
-		(struct usb_string_descriptor*)wstrLang;
-
-	string = (struct usb_string_descriptor *) wstrManufacturer;
-	string->bLength = sizeof(wstrManufacturer);
-	string->bDescriptorType = USB_DT_STRING;
-	str2wide (CONFIG_USBD_MANUFACTURER, string->wData);
-	usbtty_string_table[STR_MANUFACTURER]=string;
-
-	string = (struct usb_string_descriptor *) wstrProduct;
-	string->bLength = sizeof(wstrProduct);
-	string->bDescriptorType = USB_DT_STRING;
-	str2wide (CONFIG_USBD_PRODUCT_NAME, string->wData);
-	usbtty_string_table[STR_PRODUCT]=string;
-
-	string = (struct usb_string_descriptor *) wstrSerial;
-	string->bLength = sizeof(serial_number);
-	string->bDescriptorType = USB_DT_STRING;
-	str2wide (serial_number, string->wData);
-	usbtty_string_table[STR_SERIAL]=string;
-
-	string = (struct usb_string_descriptor *) wstrConfiguration;
-	string->bLength = sizeof(wstrConfiguration);
-	string->bDescriptorType = USB_DT_STRING;
-	str2wide (CFG_USBD_CONFIGURATION_STR, string->wData);
-	usbtty_string_table[STR_CONFIG]=string;
-
-	string = (struct usb_string_descriptor *) wstrDataInterface;
-	string->bLength = sizeof(wstrDataInterface);
-	string->bDescriptorType = USB_DT_STRING;
-	str2wide (CFG_USBD_DATA_INTERFACE_STR, string->wData);
-	usbtty_string_table[STR_DATA_INTERFACE]=string;
-
-	string = (struct usb_string_descriptor *) wstrCtrlInterface;
-	string->bLength = sizeof(wstrCtrlInterface);
-	string->bDescriptorType = USB_DT_STRING;
-	str2wide (CFG_USBD_CTRL_INTERFACE_STR, string->wData);
-	usbtty_string_table[STR_CTRL_INTERFACE]=string;
-
-	/* Now, initialize the string table for ep0 handling */
-	usb_strings = usbtty_string_table;
-}
-
-#define init_wMaxPacketSize(x)	le16_to_cpu(get_unaligned(\
-			&ep_descriptor_ptrs[(x) - 1]->wMaxPacketSize));
-
-static void usbtty_init_instances (void)
-{
-	int i;
-
-	/* initialize device instance */
-	memset (device_instance, 0, sizeof (struct usb_device_instance));
-	device_instance->device_state = STATE_INIT;
-	device_instance->device_descriptor = &device_descriptor;
-	device_instance->event = usbtty_event_handler;
-	device_instance->cdc_recv_setup = usbtty_cdc_setup;
-	device_instance->bus = bus_instance;
-	device_instance->configurations = NUM_CONFIGS;
-	device_instance->configuration_instance_array = config_instance;
-
-	/* initialize bus instance */
-	memset (bus_instance, 0, sizeof (struct usb_bus_instance));
-	bus_instance->device = device_instance;
-	bus_instance->endpoint_array = endpoint_instance;
-	bus_instance->max_endpoints = 1;
-	bus_instance->maxpacketsize = 64;
-	bus_instance->serial_number_str = serial_number;
-
-	/* configuration instance */
-	memset (config_instance, 0,
-		sizeof (struct usb_configuration_instance));
-	config_instance->interfaces = interface_count;
-	config_instance->configuration_descriptor = configuration_descriptor;
-	config_instance->interface_instance_array = interface_instance;
-
-	/* interface instance */
-	memset (interface_instance, 0,
-		sizeof (struct usb_interface_instance));
-	interface_instance->alternates = 1;
-	interface_instance->alternates_instance_array = alternate_instance;
-
-	/* alternates instance */
-	memset (alternate_instance, 0,
-		sizeof (struct usb_alternate_instance));
-	alternate_instance->interface_descriptor = interface_descriptors;
-	alternate_instance->endpoints = NUM_ENDPOINTS;
-	alternate_instance->endpoints_descriptor_array = ep_descriptor_ptrs;
-
-	/* endpoint instances */
-	memset (&endpoint_instance[0], 0,
-		sizeof (struct usb_endpoint_instance));
-	endpoint_instance[0].endpoint_address = 0;
-	endpoint_instance[0].rcv_packetSize = EP0_MAX_PACKET_SIZE;
-	endpoint_instance[0].rcv_attributes = USB_ENDPOINT_XFER_CONTROL;
-	endpoint_instance[0].tx_packetSize = EP0_MAX_PACKET_SIZE;
-	endpoint_instance[0].tx_attributes = USB_ENDPOINT_XFER_CONTROL;
-	udc_setup_ep (device_instance, 0, &endpoint_instance[0]);
-
-	for (i = 1; i <= NUM_ENDPOINTS; i++) {
-		memset (&endpoint_instance[i], 0,
-			sizeof (struct usb_endpoint_instance));
-
-		endpoint_instance[i].endpoint_address =
-			ep_descriptor_ptrs[i - 1]->bEndpointAddress;
-
-		endpoint_instance[i].rcv_attributes =
-			ep_descriptor_ptrs[i - 1]->bmAttributes;
-
-		endpoint_instance[i].rcv_packetSize = init_wMaxPacketSize(i);
-
-		endpoint_instance[i].tx_attributes =
-			ep_descriptor_ptrs[i - 1]->bmAttributes;
-
-		endpoint_instance[i].tx_packetSize = init_wMaxPacketSize(i);
-
-		endpoint_instance[i].tx_attributes =
-			ep_descriptor_ptrs[i - 1]->bmAttributes;
-
-		urb_link_init (&endpoint_instance[i].rcv);
-		urb_link_init (&endpoint_instance[i].rdy);
-		urb_link_init (&endpoint_instance[i].tx);
-		urb_link_init (&endpoint_instance[i].done);
-
-		if (endpoint_instance[i].endpoint_address & USB_DIR_IN)
-			endpoint_instance[i].tx_urb =
-				usbd_alloc_urb (device_instance,
-						&endpoint_instance[i]);
-		else
-			endpoint_instance[i].rcv_urb =
-				usbd_alloc_urb (device_instance,
-						&endpoint_instance[i]);
-	}
-}
-
-static void usbtty_init_endpoints (void)
-{
-	int i;
-
-	bus_instance->max_endpoints = NUM_ENDPOINTS + 1;
-	for (i = 1; i <= NUM_ENDPOINTS; i++) {
-		udc_setup_ep (device_instance, i, &endpoint_instance[i]);
-	}
-}
-
-/* usbtty_init_terminal_type
- *
- * Do some late binding for our device type.
- */
-static void usbtty_init_terminal_type(short type)
-{
-	switch(type){
-		/* CDC ACM */
-		case 0:
-			/* Assign endpoint descriptors */
-			ep_descriptor_ptrs[0] =
-				&acm_configuration_descriptors[0].notification_endpoint;
-			ep_descriptor_ptrs[1] =
-				&acm_configuration_descriptors[0].data_endpoints[0];
-			ep_descriptor_ptrs[2] =
-				&acm_configuration_descriptors[0].data_endpoints[1];
-
-			/* Enumerate Device Descriptor */
-			device_descriptor.bDeviceClass =
-				COMMUNICATIONS_DEVICE_CLASS;
-			device_descriptor.idProduct =
-				cpu_to_le16(CONFIG_USBD_PRODUCTID_CDCACM);
-
-			/* Assign endpoint indices */
-			tx_endpoint = ACM_TX_ENDPOINT;
-			rx_endpoint = ACM_RX_ENDPOINT;
-
-			/* Configuration Descriptor */
-			configuration_descriptor =
-				(struct usb_configuration_descriptor*)
-				&acm_configuration_descriptors;
-
-			/* Interface count */
-			interface_count = NUM_ACM_INTERFACES;
-		break;
-
-		/* BULK IN/OUT & Default */
-		case 1:
-		default:
-			/* Assign endpoint descriptors */
-			ep_descriptor_ptrs[0] =
-				&gserial_configuration_descriptors[0].data_endpoints[0];
-			ep_descriptor_ptrs[1] =
-				&gserial_configuration_descriptors[0].data_endpoints[1];
-			ep_descriptor_ptrs[2] =
-				&gserial_configuration_descriptors[0].data_endpoints[2];
-
-			/* Enumerate Device Descriptor */
-			device_descriptor.bDeviceClass = 0xFF;
-			device_descriptor.idProduct =
-				cpu_to_le16(CONFIG_USBD_PRODUCTID_GSERIAL);
-			/* Assign endpoint indices */
-			tx_endpoint = GSERIAL_TX_ENDPOINT;
-			rx_endpoint = GSERIAL_RX_ENDPOINT;
-
-			/* Configuration Descriptor */
-			configuration_descriptor =
-				(struct usb_configuration_descriptor*)
-				&gserial_configuration_descriptors;
-
-			/* Interface count */
-			interface_count = NUM_GSERIAL_INTERFACES;
-		break;
-	}
-}
-
-/******************************************************************************/
-
-static struct urb *next_urb (struct usb_device_instance *device,
-			     struct usb_endpoint_instance *endpoint)
-{
-	struct urb *current_urb = NULL;
-	int space;
-
-	/* If there's a queue, then we should add to the last urb */
-	if (!endpoint->tx_queue) {
-		current_urb = endpoint->tx_urb;
-	} else {
-		/* Last urb from tx chain */
-		current_urb =
-			p2surround (struct urb, link, endpoint->tx.prev);
-	}
-
-	/* Make sure this one has enough room */
-	space = current_urb->buffer_length - current_urb->actual_length;
-	if (space > 0) {
-		return current_urb;
-	} else {		/* No space here */
-		/* First look at done list */
-		current_urb = first_urb_detached (&endpoint->done);
-		if (!current_urb) {
-			current_urb = usbd_alloc_urb (device, endpoint);
-		}
-
-		urb_append (&endpoint->tx, current_urb);
-		endpoint->tx_queue++;
-	}
-	return current_urb;
-}
-
-static int write_buffer (circbuf_t * buf)
-{
-	if (!usbtty_configured ()) {
-		return 0;
-	}
-
-	struct usb_endpoint_instance *endpoint =
-			&endpoint_instance[tx_endpoint];
-	struct urb *current_urb = NULL;
-
-	/* TX data still exists - send it now
-	 */
-	if(endpoint->sent < endpoint->tx_urb->actual_length){
-		if(udc_endpoint_write (endpoint)){
-			/* Write pre-empted by RX */
-			return -1;
-		}
-	}
-
-	if (buf->size) {
-		char *dest;
-
-		int space_avail;
-		int popnum, popped;
-		int total = 0;
-
-		/* Break buffer into urb sized pieces,
-		 * and link each to the endpoint
-		 */
-		while (buf->size > 0) {
-
-			current_urb = next_urb (device_instance, endpoint);
-
-			dest = (char*)current_urb->buffer +
-				current_urb->actual_length;
-
-			space_avail =
-				current_urb->buffer_length -
-				current_urb->actual_length;
-			popnum = min(space_avail, (int)buf->size);
-			if (popnum == 0)
-				break;
-
-			popped = buf_pop (buf, dest, popnum);
-			if (popped == 0)
-				break;
-			current_urb->actual_length += popped;
-			total += popped;
-
-			/* If endpoint->last == 0, then transfers have
-			 * not started on this endpoint
-			 */
-			if (endpoint->last == 0) {
-				if(udc_endpoint_write (endpoint)){
-					/* Write pre-empted by RX */
-					return -1;
-				}
-			}
-
-		}/* end while */
-		return total;
-	}
-
-	return 0;
-}
-
-static int fill_buffer (circbuf_t * buf)
-{
-	struct usb_endpoint_instance *endpoint =
-		&endpoint_instance[rx_endpoint];
-
-	if (endpoint->rcv_urb && endpoint->rcv_urb->actual_length) {
-		unsigned int nb = 0;
-		char *src = (char *) endpoint->rcv_urb->buffer;
-		unsigned int rx_avail = buf->totalsize - buf->size;
-
-		if(rx_avail >= endpoint->rcv_urb->actual_length){
-
-			nb = endpoint->rcv_urb->actual_length;
-			buf_push (buf, src, nb);
-			endpoint->rcv_urb->actual_length = 0;
-
-		}
-		return nb;
-	}
-	return 0;
-}
-
-static int usbtty_configured (void)
-{
-	return usbtty_configured_flag;
-}
-
-/******************************************************************************/
-
-static void usbtty_event_handler (struct usb_device_instance *device,
-				  usb_device_event_t event, int data)
-{
-	switch (event) {
-	case DEVICE_RESET:
-	case DEVICE_BUS_INACTIVE:
-		usbtty_configured_flag = 0;
-		break;
-	case DEVICE_CONFIGURED:
-		usbtty_configured_flag = 1;
-		break;
-
-	case DEVICE_ADDRESS_ASSIGNED:
-		usbtty_init_endpoints ();
-
-	default:
-		break;
-	}
-}
-
-/******************************************************************************/
-
-int usbtty_cdc_setup(struct usb_device_request *request, struct urb *urb)
-{
-	switch (request->bRequest){
-
-		case ACM_SET_CONTROL_LINE_STATE:	/* Implies DTE ready */
-			break;
-		case ACM_SEND_ENCAPSULATED_COMMAND :	/* Required */
-			break;
-		case ACM_SET_LINE_ENCODING :		/* DTE stop/parity bits
-							 * per character */
-			break;
-		case ACM_GET_ENCAPSULATED_RESPONSE :	/* request response */
-			break;
-		case ACM_GET_LINE_ENCODING :		/* request DTE rate,
-							 * stop/parity bits */
-			memcpy (urb->buffer , &rs232_desc, sizeof(rs232_desc));
-			urb->actual_length = sizeof(rs232_desc);
-
-			break;
-		default:
-			return 1;
-	}
-	return 0;
-}
-
-/******************************************************************************/
-
-/*
- * Since interrupt handling has not yet been implemented, we use this function
- * to handle polling.  This is called by the tstc,getc,putc,puts routines to
- * update the USB state.
- */
-void usbtty_poll (void)
-{
-	/* New interrupts? */
-	udc_irq();
-
-	/* Write any output data to host buffer
-	 * (do this before checking interrupts to avoid missing one)
-	 */
-	if (usbtty_configured ()) {
-		write_buffer (&usbtty_output);
-	}
-
-	/* New interrupts? */
-	udc_irq();
-
-	/* Check for new data from host..
-	 * (do this after checking interrupts to get latest data)
-	 */
-	if (usbtty_configured ()) {
-		fill_buffer (&usbtty_input);
-	}
-
-	/* New interrupts? */
-	udc_irq();
-
-}
diff --git a/drivers/serial/usbtty.h b/drivers/serial/usbtty.h
deleted file mode 100644
index b176a7961b8..00000000000
--- a/drivers/serial/usbtty.h
+++ /dev/null
@@ -1,49 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2003
- * Gerry Hamel, geh@ti.com, Texas Instruments
- *
- * (C) Copyright 2006
- * Bryan O'Donoghue, bodonoghue@codehermit.ie, CodeHermit
- */
-
-#ifndef __USB_TTY_H__
-#define __USB_TTY_H__
-
-#include <usbdevice.h>
-#if defined(CONFIG_PPC)
-#include <usb/mpc8xx_udc.h>
-#elif defined(CONFIG_CI_UDC)
-#include <usb/ci_udc.h>
-#endif
-
-#include <usb/udc.h>
-#include <version.h>
-
-#ifndef CFG_USBD_CONFIGURATION_STR
-#define CFG_USBD_CONFIGURATION_STR	"TTY via USB"
-#endif
-
-#define CFG_USBD_SERIAL_OUT_ENDPOINT UDC_OUT_ENDPOINT
-#define CFG_USBD_SERIAL_OUT_PKTSIZE	UDC_OUT_PACKET_SIZE
-#define CFG_USBD_SERIAL_IN_ENDPOINT	UDC_IN_ENDPOINT
-#define CFG_USBD_SERIAL_IN_PKTSIZE	UDC_IN_PACKET_SIZE
-#define CFG_USBD_SERIAL_INT_ENDPOINT UDC_INT_ENDPOINT
-#define CFG_USBD_SERIAL_INT_PKTSIZE	UDC_INT_PACKET_SIZE
-#define CFG_USBD_SERIAL_BULK_PKTSIZE	UDC_BULK_PACKET_SIZE
-
-#define USBTTY_DEVICE_CLASS	COMMUNICATIONS_DEVICE_CLASS
-
-#define USBTTY_BCD_DEVICE	0x00
-#define USBTTY_MAXPOWER		0x00
-
-#define STR_LANG		0x00
-#define STR_MANUFACTURER	0x01
-#define STR_PRODUCT		0x02
-#define STR_SERIAL		0x03
-#define STR_CONFIG		0x04
-#define STR_DATA_INTERFACE	0x05
-#define STR_CTRL_INTERFACE	0x06
-#define STR_COUNT		0x07
-
-#endif
diff --git a/drivers/soc/soc_ti_k3.c b/drivers/soc/soc_ti_k3.c
index a3acca4d394..b34cbd08e07 100644
--- a/drivers/soc/soc_ti_k3.c
+++ b/drivers/soc/soc_ti_k3.c
@@ -18,8 +18,12 @@ struct soc_ti_k3_plat {
 static const char *get_family_string(u32 idreg)
 {
 	const char *family;
+	u32 jtag_dev_id;
+	u32 pkg;
 	u32 soc;
 
+	jtag_dev_id = readl(CTRLMMR_WKUP_JTAG_DEVICE_ID);
+
 	soc = (idreg & JTAG_ID_PARTNO_MASK) >> JTAG_ID_PARTNO_SHIFT;
 
 	switch (soc) {
@@ -51,8 +55,16 @@ static const char *get_family_string(u32 idreg)
 		family = "J722S";
 		break;
 	case JTAG_ID_PARTNO_J784S4:
-		family = "J784S4";
-		break;
+		{
+			/* Keep default family as J784S4 */
+			family = "J784S4";
+
+			pkg = (jtag_dev_id & JTAG_DEV_J742S2_PKG_MASK) >> JTAG_DEV_J742S2_PKG_SHIFT;
+			if (pkg == JTAG_ID_PKG_J742S2)
+				family = "J742S2";
+
+			break;
+		}
 	default:
 		family = "Unknown Silicon";
 	};
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index 96ea033082b..f475f341c9c 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -52,6 +52,13 @@ config SPI_DIRMAP
 
 if DM_SPI
 
+config ADI_SPI3
+	bool "Enable ADI SPI Driver"
+	depends on ARCH_SC5XX
+	help
+	  Enable the ADI (Analog Devices) SPI controller driver. This
+	  driver enables the support for SC5XX spi controller.
+
 config ALTERA_SPI
 	bool "Altera SPI driver"
 	help
@@ -85,7 +92,7 @@ config ATH79_SPI
 
 config ATMEL_QSPI
 	bool "Atmel Quad SPI Controller"
-	depends on ARCH_AT91
+	depends on ARCH_AT91 && SPI_MEM
 	help
 	  Enable the Atmel Quad SPI controller in master mode. This driver
 	  does not support generic SPI. The implementation supports only the
@@ -135,7 +142,7 @@ config BCMSTB_SPI
 
 config CORTINA_SFLASH
 	bool "Cortina-Access Serial Flash controller driver"
-	depends on DM_SPI && SPI_MEM
+	depends on SPI_MEM
 	help
 	  Enable the Cortina-Access Serial Flash controller driver. This driver
 	  can be used to access the SPI NOR/NAND flash on platforms embedding this
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 7051e2a00c6..21895d46429 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -19,6 +19,7 @@ obj-y += spi.o
 obj-$(CONFIG_SPI_MEM) += spi-mem-nodm.o
 endif
 
+obj-$(CONFIG_ADI_SPI3) += adi_spi3.o
 obj-$(CONFIG_ALTERA_SPI) += altera_spi.o
 obj-$(CONFIG_APPLE_SPI) += apple_spi.o
 obj-$(CONFIG_ATH79_SPI) += ath79_spi.o
diff --git a/drivers/spi/adi_spi3.c b/drivers/spi/adi_spi3.c
new file mode 100644
index 00000000000..2125d25561a
--- /dev/null
+++ b/drivers/spi/adi_spi3.c
@@ -0,0 +1,679 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * (C) Copyright 2022 - Analog Devices, Inc.
+ *
+ * Written and/or maintained by Timesys Corporation
+ *
+ * Converted to driver model by Nathan Barrett-Morrison
+ *
+ * Contact: Nathan Barrett-Morrison <nathan.morrison@timesys.com>
+ * Contact: Greg Malysa <greg.malysa@timesys.com>
+ * Contact: Ian Roberts <ian.roberts@timesys.com>
+ * Contact: Piotr Wojtaszczyk <piotr.wojtaszczyk@timesys.com>
+ *
+ */
+
+#include <clk.h>
+#include <dm.h>
+#include <mapmem.h>
+#include <spi.h>
+#include <spi-mem.h>
+#include <dm/device_compat.h>
+#include <linux/io.h>
+
+#define SPI_IDLE_VAL	0xff
+
+#define MAX_CTRL_CS 7
+
+/* SPI_CONTROL */
+#define SPI_CTL_EN          0x00000001 /* Enable */
+#define SPI_CTL_MSTR        0x00000002 /* Master/Slave */
+#define SPI_CTL_PSSE        0x00000004 /* controls modf error in master mode */
+#define SPI_CTL_ODM         0x00000008 /* Open Drain Mode */
+#define SPI_CTL_CPHA        0x00000010 /* Clock Phase */
+#define SPI_CTL_CPOL        0x00000020 /* Clock Polarity */
+#define SPI_CTL_ASSEL       0x00000040 /* Slave Select Pin Control */
+#define SPI_CTL_SELST       0x00000080 /* Slave Select Polarity in transfers */
+#define SPI_CTL_EMISO       0x00000100 /*Enable MISO */
+#define SPI_CTL_SIZE        0x00000600 /*Word Transfer Size */
+#define SPI_CTL_SIZE08      0x00000000 /*SIZE: 8 bits */
+#define SPI_CTL_SIZE16      0x00000200 /*SIZE: 16 bits */
+#define SPI_CTL_SIZE32      0x00000400 /*SIZE: 32 bits */
+#define SPI_CTL_LSBF        0x00001000 /*LSB First */
+#define SPI_CTL_FCEN        0x00002000 /*Flow-Control Enable */
+#define SPI_CTL_FCCH        0x00004000 /*Flow-Control Channel Selection */
+#define SPI_CTL_FCPL        0x00008000 /*Flow-Control Polarity */
+#define SPI_CTL_FCWM        0x00030000 /*Flow-Control Water-Mark */
+#define SPI_CTL_FIFO0       0x00000000 /*FCWM: Tx empty or Rx Full */
+#define SPI_CTL_FIFO1       0x00010000 /*FCWM: Tx empty or Rx full (>=75%) */
+#define SPI_CTL_FIFO2       0x00020000 /*FCWM: Tx empty or Rx full (>=50%) */
+#define SPI_CTL_FMODE       0x00040000 /*Fast-mode Enable */
+#define SPI_CTL_MIOM        0x00300000 /*Multiple I/O Mode */
+#define SPI_CTL_MIO_DIS     0x00000000 /*MIOM: Disable */
+#define SPI_CTL_MIO_DUAL    0x00100000 /*MIOM: Enable DIOM (Dual I/O Mode) */
+#define SPI_CTL_MIO_QUAD    0x00200000 /*MIOM: Enable QUAD (Quad SPI Mode) */
+#define SPI_CTL_SOSI        0x00400000 /*Start on MOSI */
+#define SPI_CTL_MMWEM       0x40000000 /*Start on MMWEM */
+#define SPI_CTL_MMSE        0x80000000 /*Start on MMSE */
+/* SPI_RX_CONTROL */
+#define SPI_RXCTL_REN       0x00000001 /*Receive Channel Enable */
+#define SPI_RXCTL_RTI       0x00000004 /*Receive Transfer Initiate */
+#define SPI_RXCTL_RWCEN     0x00000008 /*Receive Word Counter Enable */
+#define SPI_RXCTL_RDR       0x00000070 /*Receive Data Request */
+#define SPI_RXCTL_RDR_DIS   0x00000000 /*RDR: Disabled */
+#define SPI_RXCTL_RDR_NE    0x00000010 /*RDR: RFIFO not empty */
+#define SPI_RXCTL_RDR_25    0x00000020 /*RDR: RFIFO 25% full */
+#define SPI_RXCTL_RDR_50    0x00000030 /*RDR: RFIFO 50% full */
+#define SPI_RXCTL_RDR_75    0x00000040 /*RDR: RFIFO 75% full */
+#define SPI_RXCTL_RDR_FULL  0x00000050 /*RDR: RFIFO full */
+#define SPI_RXCTL_RDO       0x00000100 /*Receive Data Over-Run */
+#define SPI_RXCTL_RRWM      0x00003000 /*FIFO Regular Water-Mark */
+#define SPI_RXCTL_RWM_0     0x00000000 /*RRWM: RFIFO Empty */
+#define SPI_RXCTL_RWM_25    0x00001000 /*RRWM: RFIFO 25% full */
+#define SPI_RXCTL_RWM_50    0x00002000 /*RRWM: RFIFO 50% full */
+#define SPI_RXCTL_RWM_75    0x00003000 /*RRWM: RFIFO 75% full */
+#define SPI_RXCTL_RUWM      0x00070000 /*FIFO Urgent Water-Mark */
+#define SPI_RXCTL_UWM_DIS   0x00000000 /*RUWM: Disabled */
+#define SPI_RXCTL_UWM_25    0x00010000 /*RUWM: RFIFO 25% full */
+#define SPI_RXCTL_UWM_50    0x00020000 /*RUWM: RFIFO 50% full */
+#define SPI_RXCTL_UWM_75    0x00030000 /*RUWM: RFIFO 75% full */
+#define SPI_RXCTL_UWM_FULL  0x00040000 /*RUWM: RFIFO full */
+/* SPI_TX_CONTROL */
+#define SPI_TXCTL_TEN       0x00000001 /*Transmit Channel Enable */
+#define SPI_TXCTL_TTI       0x00000004 /*Transmit Transfer Initiate */
+#define SPI_TXCTL_TWCEN     0x00000008 /*Transmit Word Counter Enable */
+#define SPI_TXCTL_TDR       0x00000070 /*Transmit Data Request */
+#define SPI_TXCTL_TDR_DIS   0x00000000 /*TDR: Disabled */
+#define SPI_TXCTL_TDR_NF    0x00000010 /*TDR: TFIFO not full */
+#define SPI_TXCTL_TDR_25    0x00000020 /*TDR: TFIFO 25% empty */
+#define SPI_TXCTL_TDR_50    0x00000030 /*TDR: TFIFO 50% empty */
+#define SPI_TXCTL_TDR_75    0x00000040 /*TDR: TFIFO 75% empty */
+#define SPI_TXCTL_TDR_EMPTY 0x00000050 /*TDR: TFIFO empty */
+#define SPI_TXCTL_TDU       0x00000100 /*Transmit Data Under-Run */
+#define SPI_TXCTL_TRWM      0x00003000 /*FIFO Regular Water-Mark */
+#define SPI_TXCTL_RWM_FULL  0x00000000 /*TRWM: TFIFO full */
+#define SPI_TXCTL_RWM_25    0x00001000 /*TRWM: TFIFO 25% empty */
+#define SPI_TXCTL_RWM_50    0x00002000 /*TRWM: TFIFO 50% empty */
+#define SPI_TXCTL_RWM_75    0x00003000 /*TRWM: TFIFO 75% empty */
+#define SPI_TXCTL_TUWM      0x00070000 /*FIFO Urgent Water-Mark */
+#define SPI_TXCTL_UWM_DIS   0x00000000 /*TUWM: Disabled */
+#define SPI_TXCTL_UWM_25    0x00010000 /*TUWM: TFIFO 25% empty */
+#define SPI_TXCTL_UWM_50    0x00020000 /*TUWM: TFIFO 50% empty */
+#define SPI_TXCTL_UWM_75    0x00030000 /*TUWM: TFIFO 75% empty */
+#define SPI_TXCTL_UWM_EMPTY 0x00040000 /*TUWM: TFIFO empty */
+/* SPI_CLOCK */
+#define SPI_CLK_BAUD        0x0000FFFF /*Baud Rate */
+/* SPI_DELAY */
+#define SPI_DLY_STOP        0x000000FF /*Transfer delay time */
+#define SPI_DLY_LEADX       0x00000100 /*Extended (1 SCK) LEAD Control */
+#define SPI_DLY_LAGX        0x00000200 /*Extended (1 SCK) LAG control */
+/* SPI_SSEL */
+#define SPI_SLVSEL_SSE1     0x00000002 /*SPISSEL1 Enable */
+#define SPI_SLVSEL_SSE2     0x00000004 /*SPISSEL2 Enable */
+#define SPI_SLVSEL_SSE3     0x00000008 /*SPISSEL3 Enable */
+#define SPI_SLVSEL_SSE4     0x00000010 /*SPISSEL4 Enable */
+#define SPI_SLVSEL_SSE5     0x00000020 /*SPISSEL5 Enable */
+#define SPI_SLVSEL_SSE6     0x00000040 /*SPISSEL6 Enable */
+#define SPI_SLVSEL_SSE7     0x00000080 /*SPISSEL7 Enable */
+#define SPI_SLVSEL_SSEL1    0x00000200 /*SPISSEL1 Value */
+#define SPI_SLVSEL_SSEL2    0x00000400 /*SPISSEL2 Value */
+#define SPI_SLVSEL_SSEL3    0x00000800 /*SPISSEL3 Value */
+#define SPI_SLVSEL_SSEL4    0x00001000 /*SPISSEL4 Value */
+#define SPI_SLVSEL_SSEL5    0x00002000 /*SPISSEL5 Value */
+#define SPI_SLVSEL_SSEL6    0x00004000 /*SPISSEL6 Value */
+#define SPI_SLVSEL_SSEL7    0x00008000 /*SPISSEL7 Value */
+/* SPI_RWC */
+#define SPI_RWC_VALUE       0x0000FFFF /*Received Word-Count */
+/* SPI_RWCR */
+#define SPI_RWCR_VALUE      0x0000FFFF /*Received Word-Count Reload */
+/* SPI_TWC */
+#define SPI_TWC_VALUE       0x0000FFFF /*Transmitted Word-Count */
+/* SPI_TWCR */
+#define SPI_TWCR_VALUE      0x0000FFFF /*Transmitted Word-Count Reload */
+/* SPI_IMASK */
+#define SPI_IMSK_RUWM       0x00000002 /*Receive Water-Mark Interrupt Mask */
+#define SPI_IMSK_TUWM       0x00000004 /*Transmit Water-Mark Interrupt Mask */
+#define SPI_IMSK_ROM        0x00000010 /*Receive Over-Run Interrupt Mask */
+#define SPI_IMSK_TUM        0x00000020 /*Transmit Under-Run Interrupt Mask */
+#define SPI_IMSK_TCM        0x00000040 /*Transmit Collision Interrupt Mask */
+#define SPI_IMSK_MFM        0x00000080 /*Mode Fault Interrupt Mask */
+#define SPI_IMSK_RSM        0x00000100 /*Receive Start Interrupt Mask */
+#define SPI_IMSK_TSM        0x00000200 /*Transmit Start Interrupt Mask */
+#define SPI_IMSK_RFM        0x00000400 /*Receive Finish Interrupt Mask */
+#define SPI_IMSK_TFM        0x00000800 /*Transmit Finish Interrupt Mask */
+/* SPI_IMASKCL */
+#define SPI_IMSK_CLR_RUW    0x00000002 /*Receive Water-Mark Interrupt Mask */
+#define SPI_IMSK_CLR_TUWM   0x00000004 /*Transmit Water-Mark Interrupt Mask */
+#define SPI_IMSK_CLR_ROM    0x00000010 /*Receive Over-Run Interrupt Mask */
+#define SPI_IMSK_CLR_TUM    0x00000020 /*Transmit Under-Run Interrupt Mask */
+#define SPI_IMSK_CLR_TCM    0x00000040 /*Transmit Collision Interrupt Mask */
+#define SPI_IMSK_CLR_MFM    0x00000080 /*Mode Fault Interrupt Mask */
+#define SPI_IMSK_CLR_RSM    0x00000100 /*Receive Start Interrupt Mask */
+#define SPI_IMSK_CLR_TSM    0x00000200 /*Transmit Start Interrupt Mask */
+#define SPI_IMSK_CLR_RFM    0x00000400 /*Receive Finish Interrupt Mask */
+#define SPI_IMSK_CLR_TFM    0x00000800 /*Transmit Finish Interrupt Mask */
+/* SPI_IMASKST */
+#define SPI_IMSK_SET_RUWM   0x00000002 /*Receive Water-Mark Interrupt Mask */
+#define SPI_IMSK_SET_TUWM   0x00000004 /*Transmit Water-Mark Interrupt Mask */
+#define SPI_IMSK_SET_ROM    0x00000010 /*Receive Over-Run Interrupt Mask */
+#define SPI_IMSK_SET_TUM    0x00000020 /*Transmit Under-Run Interrupt Mask */
+#define SPI_IMSK_SET_TCM    0x00000040 /*Transmit Collision Interrupt Mask */
+#define SPI_IMSK_SET_MFM    0x00000080 /*Mode Fault Interrupt Mask */
+#define SPI_IMSK_SET_RSM    0x00000100 /*Receive Start Interrupt Mask */
+#define SPI_IMSK_SET_TSM    0x00000200 /*Transmit Start Interrupt Mask */
+#define SPI_IMSK_SET_RFM    0x00000400 /*Receive Finish Interrupt Mask */
+#define SPI_IMSK_SET_TFM    0x00000800 /*Transmit Finish Interrupt Mask */
+/* SPI_STATUS */
+#define SPI_STAT_SPIF       0x00000001 /*SPI Finished */
+#define SPI_STAT_RUWM       0x00000002 /*Receive Water-Mark Breached */
+#define SPI_STAT_TUWM       0x00000004 /*Transmit Water-Mark Breached */
+#define SPI_STAT_ROE        0x00000010 /*Receive Over-Run Indication */
+#define SPI_STAT_TUE        0x00000020 /*Transmit Under-Run Indication */
+#define SPI_STAT_TCE        0x00000040 /*Transmit Collision Indication */
+#define SPI_STAT_MODF       0x00000080 /*Mode Fault Indication */
+#define SPI_STAT_RS         0x00000100 /*Receive Start Indication */
+#define SPI_STAT_TS         0x00000200 /*Transmit Start Indication */
+#define SPI_STAT_RF         0x00000400 /*Receive Finish Indication */
+#define SPI_STAT_TF         0x00000800 /*Transmit Finish Indication */
+#define SPI_STAT_RFS        0x00007000 /*SPI_RFIFO status */
+#define SPI_STAT_RFIFO_EMPTY 0x00000000 /*RFS: RFIFO Empty */
+#define SPI_STAT_RFIFO_25   0x00001000 /*RFS: RFIFO 25% Full */
+#define SPI_STAT_RFIFO_50   0x00002000 /*RFS: RFIFO 50% Full */
+#define SPI_STAT_RFIFO_75   0x00003000 /*RFS: RFIFO 75% Full */
+#define SPI_STAT_RFIFO_FULL 0x00004000 /*RFS: RFIFO Full */
+#define SPI_STAT_TFS        0x00070000 /*SPI_TFIFO status */
+#define SPI_STAT_TFIFO_FULL 0x00000000 /*TFS: TFIFO full */
+#define SPI_STAT_TFIFO_25   0x00010000 /*TFS: TFIFO 25% empty */
+#define SPI_STAT_TFIFO_50   0x00020000 /*TFS: TFIFO 50% empty */
+#define SPI_STAT_TFIFO_75   0x00030000 /*TFS: TFIFO 75% empty */
+#define SPI_STAT_TFIFO_EMPTY 0x00040000 /*TFS: TFIFO empty */
+#define SPI_STAT_FCS        0x00100000 /*Flow-Control Stall Indication */
+#define SPI_STAT_RFE        0x00400000 /*SPI_RFIFO Empty */
+#define SPI_STAT_TFF        0x00800000 /*SPI_TFIFO Full */
+/* SPI_ILAT */
+#define SPI_ILAT_RUWMI      0x00000002 /*Receive Water Mark Interrupt */
+#define SPI_ILAT_TUWMI      0x00000004 /*Transmit Water Mark Interrupt */
+#define SPI_ILAT_ROI        0x00000010 /*Receive Over-Run Indication */
+#define SPI_ILAT_TUI        0x00000020 /*Transmit Under-Run Indication */
+#define SPI_ILAT_TCI        0x00000040 /*Transmit Collision Indication */
+#define SPI_ILAT_MFI        0x00000080 /*Mode Fault Indication */
+#define SPI_ILAT_RSI        0x00000100 /*Receive Start Indication */
+#define SPI_ILAT_TSI        0x00000200 /*Transmit Start Indication */
+#define SPI_ILAT_RFI        0x00000400 /*Receive Finish Indication */
+#define SPI_ILAT_TFI        0x00000800 /*Transmit Finish Indication */
+/* SPI_ILATCL */
+#define SPI_ILAT_CLR_RUWMI  0x00000002 /*Receive Water Mark Interrupt */
+#define SPI_ILAT_CLR_TUWMI  0x00000004 /*Transmit Water Mark Interrupt */
+#define SPI_ILAT_CLR_ROI    0x00000010 /*Receive Over-Run Indication */
+#define SPI_ILAT_CLR_TUI    0x00000020 /*Transmit Under-Run Indication */
+#define SPI_ILAT_CLR_TCI    0x00000040 /*Transmit Collision Indication */
+#define SPI_ILAT_CLR_MFI    0x00000080 /*Mode Fault Indication */
+#define SPI_ILAT_CLR_RSI    0x00000100 /*Receive Start Indication */
+#define SPI_ILAT_CLR_TSI    0x00000200 /*Transmit Start Indication */
+#define SPI_ILAT_CLR_RFI    0x00000400 /*Receive Finish Indication */
+#define SPI_ILAT_CLR_TFI    0x00000800 /*Transmit Finish Indication */
+/* SPI_MMRDH */
+#define SPI_MMRDH_MERGE     0x04000000 /*Merge Enable */
+#define SPI_MMRDH_DMY_SZ    0x00007000 /*Bytes of Dummy */
+#define SPI_MMRDH_ADDR_PINS 0x00000800 /*Pins used for Address */
+#define SPI_MMRDH_ADDR_SZ   0x00000700 /*Bytes of Read Address */
+#define SPI_MMRDH_OPCODE    0x000000FF /*Read Opcode */
+
+#define SPI_MMRDH_TRIDMY_OFF	24 /*Bytes of Dummy offset */
+#define SPI_MMRDH_DMY_SZ_OFF	12 /*Bytes of Dummy offset */
+#define SPI_MMRDH_ADDR_SZ_OFF	8  /*Bytes of Read Address offset */
+
+#define BIT_SSEL_VAL(x) ((1 << 8) << (x)) /* Slave Select input value bit */
+#define BIT_SSEL_EN(x) (1 << (x))         /* Slave Select enable bit*/
+
+struct adi_spi_regs {
+	u32 revid;
+	u32 control;
+	u32 rx_control;
+	u32 tx_control;
+	u32 clock;
+	u32 delay;
+	u32 ssel;
+	u32 rwc;
+	u32 rwcr;
+	u32 twc;
+	u32 twcr;
+	u32 reserved0;
+	u32 emask;
+	u32 emaskcl;
+	u32 emaskst;
+	u32 reserved1;
+	u32 status;
+	u32 elat;
+	u32 elatcl;
+	u32 reserved2;
+	u32 rfifo;
+	u32 reserved3;
+	u32 tfifo;
+	u32 reserved4;
+	u32 mmrdh;
+	u32 mmtop;
+};
+
+struct adi_spi_platdata {
+	u32 max_hz;
+	u32 bus_num;
+	struct adi_spi_regs __iomem *regs;
+};
+
+struct adi_spi_priv {
+	u32 control;
+	u32 clock;
+	u32 bus_num;
+	u32 max_cs;
+	struct adi_spi_regs __iomem *regs;
+};
+
+/**
+ * By convention, this driver uses the same CS numbering that is used with the SSEL bit
+ * definitions (both here and in the TRM on which this is based), which are 1-indexed not
+ * 0-indexed. The valid CS range is therefore [1,max_cs], in contrast with other drivers
+ * where it is [0,max_cs-1].
+ */
+static int adi_spi_cs_info(struct udevice *bus, uint cs,
+			   struct spi_cs_info *info)
+{
+	struct adi_spi_priv *priv = dev_get_priv(bus);
+
+	if (cs == 0 || cs > priv->max_cs) {
+		dev_err(bus, "invalid chipselect %u\n", cs);
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+static int adi_spi_of_to_plat(struct udevice *bus)
+{
+	struct adi_spi_platdata *plat = dev_get_plat(bus);
+	fdt_addr_t addr;
+
+	plat->max_hz = dev_read_u32_default(bus, "spi-max-frequency", 500000);
+	plat->bus_num = dev_read_u32_default(bus, "bus-num", 0);
+	addr = dev_read_addr(bus);
+
+	if (addr == FDT_ADDR_T_NONE)
+		return -EINVAL;
+
+	plat->regs = map_sysmem(addr, sizeof(*plat->regs));
+
+	return 0;
+}
+
+static int adi_spi_probe(struct udevice *bus)
+{
+	struct adi_spi_platdata *plat = dev_get_plat(bus);
+	struct adi_spi_priv *priv = dev_get_priv(bus);
+
+	priv->bus_num = plat->bus_num;
+	priv->regs = plat->regs;
+	priv->max_cs = dev_read_u32_default(bus, "num-cs", MAX_CTRL_CS);
+
+	iowrite32(0x0, &plat->regs->control);
+	iowrite32(0x0, &plat->regs->rx_control);
+	iowrite32(0x0, &plat->regs->tx_control);
+
+	return 0;
+}
+
+static int adi_spi_remove(struct udevice *dev)
+{
+	return -ENODEV;
+}
+
+static int adi_spi_claim_bus(struct udevice *dev)
+{
+	struct adi_spi_priv *priv;
+	struct udevice *bus = dev->parent;
+
+	priv = dev_get_priv(bus);
+
+	debug("%s: control:%i clock:%i\n",
+	      __func__, priv->control, priv->clock);
+
+	iowrite32(priv->control, &priv->regs->control);
+	iowrite32(priv->clock, &priv->regs->clock);
+	iowrite32(0x0, &priv->regs->delay);
+
+	return 0;
+}
+
+static int adi_spi_release_bus(struct udevice *dev)
+{
+	struct adi_spi_priv *priv;
+	struct udevice *bus = dev->parent;
+
+	priv = dev_get_priv(bus);
+
+	debug("%s: control:%i clock:%i\n",
+	      __func__, priv->control, priv->clock);
+
+	iowrite32(0x0, &priv->regs->rx_control);
+	iowrite32(0x0, &priv->regs->tx_control);
+	iowrite32(0x0, &priv->regs->control);
+
+	return 0;
+}
+
+void adi_spi_enable_ssel(struct adi_spi_priv *priv, int cs)
+{
+	setbits_32(&priv->regs->ssel, BIT_SSEL_EN(cs));
+}
+
+void adi_spi_set_ssel(struct adi_spi_priv *priv, int cs, int high)
+{
+	if (high)
+		setbits_32(&priv->regs->ssel, BIT_SSEL_VAL(cs));
+	else
+		clrbits_32(&priv->regs->ssel, BIT_SSEL_VAL(cs));
+}
+
+void adi_spi_cs_activate(struct adi_spi_priv *priv, struct dm_spi_slave_plat *slave_plat)
+{
+	bool high = slave_plat->mode & SPI_CS_HIGH;
+
+	adi_spi_set_ssel(priv, slave_plat->cs[0], high);
+	adi_spi_enable_ssel(priv, slave_plat->cs[0]);
+}
+
+void adi_spi_cs_deactivate(struct adi_spi_priv *priv, struct dm_spi_slave_plat *slave_plat)
+{
+	bool high = slave_plat->mode & SPI_CS_HIGH;
+
+	/* invert CS for matching SSEL to deactivate */
+	adi_spi_set_ssel(priv, slave_plat->cs[0], !high);
+}
+
+static void discard_rx_fifo_contents(struct adi_spi_regs *regs)
+{
+	while (!(ioread32(&regs->status) & SPI_STAT_RFE))
+		ioread32(&regs->rfifo);
+}
+
+static int adi_spi_fifo_mio_xfer(struct adi_spi_priv *priv, const u8 *tx, u8 *rx,
+				 uint bytes, uint32_t mio_mode)
+{
+	u8 value;
+
+	/* switch current SPI transfer to mio SPI mode */
+	clrsetbits_32(&priv->regs->control, SPI_CTL_SOSI, mio_mode);
+	/*
+	 * Data can only be transferred in one direction in multi-io SPI
+	 * modes, trigger the transfer in respective direction.
+	 */
+	if (rx) {
+		iowrite32(0x0, &priv->regs->tx_control);
+		iowrite32(SPI_RXCTL_REN | SPI_RXCTL_RTI, &priv->regs->rx_control);
+
+		while (bytes--) {
+			while (ioread32(&priv->regs->status) &
+				SPI_STAT_RFE)
+				if (ctrlc())
+					return -1;
+			value = ioread32(&priv->regs->rfifo);
+			*rx++ = value;
+		}
+	} else if (tx) {
+		iowrite32(0x0, &priv->regs->rx_control);
+		iowrite32(SPI_TXCTL_TEN | SPI_TXCTL_TTI, &priv->regs->tx_control);
+
+		while (bytes--) {
+			value = *tx++;
+			iowrite32(value, &priv->regs->tfifo);
+			while (ioread32(&priv->regs->status) &
+				SPI_STAT_TFF)
+				if (ctrlc())
+					return -1;
+		}
+
+		/* Wait till the tfifo is empty */
+		while ((ioread32(&priv->regs->status) & SPI_STAT_TFS) != SPI_STAT_TFIFO_EMPTY)
+			if (ctrlc())
+				return -1;
+	} else {
+		return -1;
+	}
+	return 0;
+}
+
+static int adi_spi_fifo_1x_xfer(struct adi_spi_priv *priv, const u8 *tx, u8 *rx,
+				uint bytes)
+{
+	u8 value;
+
+	/*
+	 * Set current SPI transfer in normal mode and trigger
+	 * the bi-direction transfer by tx write operation.
+	 */
+	iowrite32(priv->control, &priv->regs->control);
+	iowrite32(SPI_RXCTL_REN, &priv->regs->rx_control);
+	iowrite32(SPI_TXCTL_TEN | SPI_TXCTL_TTI, &priv->regs->tx_control);
+
+	while (bytes--) {
+		value = (tx ? *tx++ : SPI_IDLE_VAL);
+		debug("%s: tx:%x ", __func__, value);
+		iowrite32(value, &priv->regs->tfifo);
+		while (ioread32(&priv->regs->status) & SPI_STAT_RFE)
+			if (ctrlc())
+				return -1;
+		value = ioread32(&priv->regs->rfifo);
+		if (rx)
+			*rx++ = value;
+		debug("rx:%x\n", value);
+	}
+	return 0;
+}
+
+static int adi_spi_fifo_xfer(struct adi_spi_priv *priv, int buswidth,
+			     const u8 *tx, u8 *rx, uint bytes)
+{
+	switch (buswidth) {
+	case 1:
+		return adi_spi_fifo_1x_xfer(priv, tx, rx, bytes);
+	case 2:
+		return adi_spi_fifo_mio_xfer(priv, tx, rx, bytes, SPI_CTL_MIO_DUAL);
+	case 4:
+		return adi_spi_fifo_mio_xfer(priv, tx, rx, bytes, SPI_CTL_MIO_QUAD);
+	default:
+		return -ENOTSUPP;
+	}
+}
+
+static int adi_spi_xfer(struct udevice *dev, unsigned int bitlen,
+			const void *dout, void *din, unsigned long flags)
+{
+	struct udevice *bus = dev->parent;
+	struct adi_spi_priv *priv = dev_get_priv(bus);
+	struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev);
+
+	const u8 *tx = dout;
+	u8 *rx = din;
+	uint bytes = bitlen / 8;
+	int ret = 0;
+
+	debug("%s: bus_num:%i cs:%i bitlen:%i bytes:%i flags:%lx\n", __func__,
+	      priv->bus_num, slave_plat->cs[0], bitlen, bytes, flags);
+
+	if (flags & SPI_XFER_BEGIN)
+		adi_spi_cs_activate(priv, slave_plat);
+
+	if (bitlen == 0)
+		goto done;
+
+	/* we can only do 8 bit transfers */
+	if (bitlen % 8) {
+		flags |= SPI_XFER_END;
+		goto done;
+	}
+
+	/* Discard invalid rx data and empty rfifo */
+	discard_rx_fifo_contents(priv->regs);
+
+	ret = adi_spi_fifo_1x_xfer(priv, tx, rx, bytes);
+
+ done:
+	if (flags & SPI_XFER_END)
+		adi_spi_cs_deactivate(priv, slave_plat);
+
+	return ret;
+}
+
+static int adi_spi_set_speed(struct udevice *bus, uint speed)
+{
+	struct adi_spi_platdata *plat = dev_get_plat(bus);
+	struct adi_spi_priv *priv = dev_get_priv(bus);
+	int ret;
+	u32 clock, spi_base_clk;
+	struct clk spi_clk;
+
+	ret = clk_get_by_name(bus, "spi", &spi_clk);
+	if (ret < 0) {
+		dev_err(bus, "Can't get SPI clk: %d\n", ret);
+		return ret;
+	}
+	spi_base_clk = clk_get_rate(&spi_clk);
+
+	if (speed > plat->max_hz)
+		speed = plat->max_hz;
+
+	if (speed > spi_base_clk)
+		return -ENODEV;
+
+	clock = spi_base_clk / speed;
+	if (clock)
+		clock--;
+
+	priv->clock = clock;
+
+	debug("%s: priv->clock: %x, speed: %x, get_spi_clk(): %x\n",
+	      __func__, clock, speed, spi_base_clk);
+
+	return 0;
+}
+
+static int adi_spi_set_mode(struct udevice *bus, uint mode)
+{
+	struct adi_spi_priv *priv = dev_get_priv(bus);
+	u32 reg;
+
+	reg = SPI_CTL_EN | SPI_CTL_MSTR;
+	if (mode & SPI_CPHA)
+		reg |= SPI_CTL_CPHA;
+	if (mode & SPI_CPOL)
+		reg |= SPI_CTL_CPOL;
+	if (mode & SPI_LSB_FIRST)
+		reg |= SPI_CTL_LSBF;
+	reg &= ~SPI_CTL_ASSEL;
+
+	priv->control = reg;
+
+	debug("%s: control=%d, cs_pol=%d\n", __func__, reg, mode & SPI_CS_HIGH ? 1 : 0);
+
+	return 0;
+}
+
+/**
+ * U-boot's version of spi-mem does not support mixed bus-width
+ * commands nor anything more than 1x mode.
+ * Using a custom exec_op implementation, we can support it.
+ */
+static int adi_spi_mem_exec_op(struct spi_slave *slave,
+			       const struct spi_mem_op *op)
+{
+	int rv = 0;
+	struct udevice *bus = slave->dev->parent;
+	struct adi_spi_priv *priv = dev_get_priv(bus);
+	struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(slave->dev);
+	u8 tmpbuf[64];
+	int i;
+
+	if ((op->cmd.nbytes + op->addr.nbytes + op->dummy.nbytes) >
+	    sizeof(tmpbuf))
+		return -ENOMEM;
+
+	for (i = 0; i < op->cmd.nbytes; i++)
+		tmpbuf[i] = op->cmd.opcode >>
+				(8 * (op->cmd.nbytes - i - 1));
+	for (i = 0; i < op->addr.nbytes; i++)
+		tmpbuf[i + op->cmd.nbytes] = op->addr.val >>
+				(8 * (op->addr.nbytes - i - 1));
+	memset(tmpbuf + op->addr.nbytes + op->cmd.nbytes, 0xff,
+	       op->dummy.nbytes);
+
+	adi_spi_cs_activate(priv, slave_plat);
+	discard_rx_fifo_contents(priv->regs);
+
+	if (op->cmd.nbytes) {
+		rv = adi_spi_fifo_xfer(priv, op->cmd.buswidth,
+				       tmpbuf, NULL, op->cmd.nbytes);
+		if (rv != 0)
+			goto cleanup;
+	}
+
+	if (op->addr.nbytes) {
+		rv = adi_spi_fifo_xfer(priv, op->addr.buswidth,
+				       tmpbuf + op->cmd.nbytes, NULL,
+				       op->addr.nbytes);
+		if (rv != 0)
+			goto cleanup;
+	}
+
+	if (op->dummy.nbytes) {
+		rv = adi_spi_fifo_xfer(priv, op->dummy.buswidth,
+				       tmpbuf + op->cmd.nbytes +
+				       op->addr.nbytes,
+				       NULL, op->dummy.nbytes);
+		if (rv != 0)
+			goto cleanup;
+	}
+
+	if (op->data.dir == SPI_MEM_DATA_IN)
+		rv = adi_spi_fifo_xfer(priv, op->data.buswidth,
+				       NULL, op->data.buf.in,
+				       op->data.nbytes);
+	else if (op->data.dir == SPI_MEM_DATA_OUT)
+		rv = adi_spi_fifo_xfer(priv, op->data.buswidth,
+				       op->data.buf.out, NULL,
+				       op->data.nbytes);
+
+cleanup:
+	adi_spi_cs_deactivate(priv, slave_plat);
+	return rv;
+}
+
+static const struct spi_controller_mem_ops adi_spi_mem_ops = {
+	.exec_op = adi_spi_mem_exec_op,
+};
+
+static const struct dm_spi_ops adi_spi_ops = {
+	.claim_bus = adi_spi_claim_bus,
+	.release_bus = adi_spi_release_bus,
+	.xfer = adi_spi_xfer,
+	.set_speed = adi_spi_set_speed,
+	.set_mode = adi_spi_set_mode,
+	.cs_info = adi_spi_cs_info,
+	.mem_ops = &adi_spi_mem_ops,
+};
+
+static const struct udevice_id adi_spi_ids[] = {
+	{ .compatible = "adi,spi3" },
+	{ }
+};
+
+U_BOOT_DRIVER(adi_spi3) = {
+	.name = "adi_spi3",
+	.id = UCLASS_SPI,
+	.of_match = adi_spi_ids,
+	.ops = &adi_spi_ops,
+	.of_to_plat = adi_spi_of_to_plat,
+	.probe = adi_spi_probe,
+	.remove = adi_spi_remove,
+	.plat_auto = sizeof(struct adi_spi_platdata),
+	.priv_auto = sizeof(struct adi_spi_priv),
+	.per_child_auto = sizeof(struct spi_slave),
+};
diff --git a/drivers/spi/atmel-quadspi.c b/drivers/spi/atmel-quadspi.c
index 3efb661803b..8aa7a83aef4 100644
--- a/drivers/spi/atmel-quadspi.c
+++ b/drivers/spi/atmel-quadspi.c
@@ -10,11 +10,13 @@
  */
 
 #include <malloc.h>
+#include <asm/gpio.h>
 #include <asm/io.h>
 #include <clk.h>
 #include <dm.h>
 #include <errno.h>
 #include <fdtdec.h>
+#include <log.h>
 #include <dm/device_compat.h>
 #include <linux/bitfield.h>
 #include <linux/bitops.h>
@@ -258,6 +260,7 @@ struct atmel_qspi_caps {
 
 struct atmel_qspi_priv_ops;
 
+#define MAX_CS_COUNT	2
 struct atmel_qspi {
 	void __iomem *regs;
 	void __iomem *mem;
@@ -267,6 +270,7 @@ struct atmel_qspi {
 	struct udevice *dev;
 	ulong bus_clk_rate;
 	u32 mr;
+	struct gpio_desc cs_gpios[MAX_CS_COUNT];
 };
 
 struct atmel_qspi_priv_ops {
@@ -395,6 +399,26 @@ static void atmel_qspi_write(u32 value, struct atmel_qspi *aq, u32 offset)
 	writel(value, aq->regs + offset);
 }
 
+static int atmel_qspi_reg_sync(struct atmel_qspi *aq)
+{
+	u32 val;
+
+	return readl_poll_timeout(aq->regs + QSPI_SR2, val,
+				  !(val & QSPI_SR2_SYNCBSY),
+				  ATMEL_QSPI_SYNC_TIMEOUT);
+}
+
+static int atmel_qspi_update_config(struct atmel_qspi *aq)
+{
+	int ret;
+
+	ret = atmel_qspi_reg_sync(aq);
+	if (ret)
+		return ret;
+	atmel_qspi_write(QSPI_CR_UPDCFG, aq, QSPI_CR);
+	return atmel_qspi_reg_sync(aq);
+}
+
 static inline bool atmel_qspi_is_compatible(const struct spi_mem_op *op,
 					    const struct atmel_qspi_mode *mode)
 {
@@ -458,6 +482,29 @@ static bool atmel_qspi_supports_op(struct spi_slave *slave,
 	return true;
 }
 
+/*
+ * Switch QSPI controller between regular SPI mode or Serial Memory Mode (SMM).
+ */
+static int atmel_qspi_set_serial_memory_mode(struct atmel_qspi *aq,
+					     bool enable)
+{
+	int ret = 0;
+
+	/* only write if designated state differs from current state */
+	if (!!(aq->mr & QSPI_MR_SMM) != enable) {
+		if (enable)
+			aq->mr |= QSPI_MR_SMM;
+		else
+			aq->mr &= ~QSPI_MR_SMM;
+		atmel_qspi_write(aq->mr, aq, QSPI_MR);
+
+		if (aq->caps->has_gclk)
+			ret = atmel_qspi_update_config(aq);
+	}
+
+	return ret;
+}
+
 static int atmel_qspi_set_cfg(struct atmel_qspi *aq,
 			      const struct spi_mem_op *op, u32 *offset)
 {
@@ -474,7 +521,7 @@ static int atmel_qspi_set_cfg(struct atmel_qspi *aq,
 		return mode;
 	ifr |= atmel_qspi_modes[mode].config;
 
-	if (op->dummy.buswidth && op->dummy.nbytes)
+	if (op->dummy.nbytes)
 		dummy_cycles = op->dummy.nbytes * 8 / op->dummy.buswidth;
 
 	/*
@@ -529,43 +576,39 @@ static int atmel_qspi_set_cfg(struct atmel_qspi *aq,
 	if (dummy_cycles)
 		ifr |= QSPI_IFR_NBDUM(dummy_cycles);
 
-	/* Set data enable */
-	if (op->data.nbytes)
+	/* Set data enable and data transfer type. */
+	if (op->data.nbytes) {
 		ifr |= QSPI_IFR_DATAEN;
 
-	/*
-	 * If the QSPI controller is set in regular SPI mode, set it in
-	 * Serial Memory Mode (SMM).
-	 */
-	if (aq->mr != QSPI_MR_SMM) {
-		atmel_qspi_write(QSPI_MR_SMM, aq, QSPI_MR);
-		aq->mr = QSPI_MR_SMM;
+		if (op->addr.nbytes)
+			ifr |= QSPI_IFR_TFRTYP_MEM;
 	}
 
+	mode = atmel_qspi_set_serial_memory_mode(aq, true);
+	if (mode < 0)
+		return mode;
+
 	/* Clear pending interrupts */
 	(void)atmel_qspi_read(aq, QSPI_SR);
 
-	if (aq->caps->has_ricr) {
-		if (!op->addr.nbytes && op->data.dir == SPI_MEM_DATA_IN)
-			ifr |= QSPI_IFR_APBTFRTYP_READ;
-
-		/* Set QSPI Instruction Frame registers */
+	/* Set QSPI Instruction Frame registers. */
+	if (op->addr.nbytes && !op->data.nbytes)
 		atmel_qspi_write(iar, aq, QSPI_IAR);
+
+	if (aq->caps->has_ricr) {
 		if (op->data.dir == SPI_MEM_DATA_IN)
 			atmel_qspi_write(icr, aq, QSPI_RICR);
 		else
 			atmel_qspi_write(icr, aq, QSPI_WICR);
-		atmel_qspi_write(ifr, aq, QSPI_IFR);
 	} else {
-		if (op->data.dir == SPI_MEM_DATA_OUT)
+		if (op->data.nbytes && op->data.dir == SPI_MEM_DATA_OUT)
 			ifr |= QSPI_IFR_SAMA5D2_WRITE_TRSFR;
 
-		/* Set QSPI Instruction Frame registers */
-		atmel_qspi_write(iar, aq, QSPI_IAR);
 		atmel_qspi_write(icr, aq, QSPI_ICR);
-		atmel_qspi_write(ifr, aq, QSPI_IFR);
 	}
 
+	atmel_qspi_write(ifr, aq, QSPI_IFR);
+
 	return 0;
 }
 
@@ -597,26 +640,6 @@ static int atmel_qspi_transfer(struct atmel_qspi *aq,
 				  ATMEL_QSPI_TIMEOUT);
 }
 
-static int atmel_qspi_reg_sync(struct atmel_qspi *aq)
-{
-	u32 val;
-
-	return readl_poll_timeout(aq->regs + QSPI_SR2, val,
-				  !(val & QSPI_SR2_SYNCBSY),
-				  ATMEL_QSPI_SYNC_TIMEOUT);
-}
-
-static int atmel_qspi_update_config(struct atmel_qspi *aq)
-{
-	int ret;
-
-	ret = atmel_qspi_reg_sync(aq);
-	if (ret)
-		return ret;
-	atmel_qspi_write(QSPI_CR_UPDCFG, aq, QSPI_CR);
-	return atmel_qspi_reg_sync(aq);
-}
-
 static int atmel_qspi_sama7g5_set_cfg(struct atmel_qspi *aq,
 				      const struct spi_mem_op *op, u32 *offset)
 {
@@ -668,17 +691,9 @@ static int atmel_qspi_sama7g5_set_cfg(struct atmel_qspi *aq,
 			ifr |= QSPI_IFR_TFRTYP_MEM;
 	}
 
-	/*
-	 * If the QSPI controller is set in regular SPI mode, set it in
-	 * Serial Memory Mode (SMM).
-	 */
-	if (aq->mr != QSPI_MR_SMM) {
-		atmel_qspi_write(QSPI_MR_SMM | QSPI_MR_DQSDLYEN, aq, QSPI_MR);
-		ret = atmel_qspi_update_config(aq);
-		if (ret)
-			return ret;
-		aq->mr = QSPI_MR_SMM;
-	}
+	ret = atmel_qspi_set_serial_memory_mode(aq, true);
+	if (ret < 0)
+		return ret;
 
 	/* Clear pending interrupts */
 	(void)atmel_qspi_read(aq, QSPI_SR);
@@ -902,11 +917,10 @@ static int atmel_qspi_sama7g5_set_speed(struct udevice *bus, uint hz)
 	}
 
 	/* Set the QSPI controller by default in Serial Memory Mode */
-	atmel_qspi_write(QSPI_MR_SMM | QSPI_MR_DQSDLYEN, aq, QSPI_MR);
-	ret = atmel_qspi_update_config(aq);
-	if (ret)
+	aq->mr |= QSPI_MR_DQSDLYEN;
+	ret = atmel_qspi_set_serial_memory_mode(aq, true);
+	if (ret < 0)
 		return ret;
-	aq->mr = QSPI_MR_SMM;
 
 	/* Enable the QSPI controller. */
 	ret = atmel_qspi_reg_sync(aq);
@@ -930,6 +944,135 @@ static int atmel_qspi_sama7g5_set_speed(struct udevice *bus, uint hz)
 	return ret;
 }
 
+static int atmel_qspi_claim_bus(struct udevice *dev)
+{
+	struct udevice *bus = dev_get_parent(dev);
+	struct atmel_qspi *aq = dev_get_priv(bus);
+	int ret;
+
+	aq->mr &= ~QSPI_MR_CSMODE_MASK;
+	aq->mr |= QSPI_MR_CSMODE_LASTXFER | QSPI_MR_WDRBT;
+	atmel_qspi_write(aq->mr, aq, QSPI_MR);
+
+	ret = atmel_qspi_set_serial_memory_mode(aq, false);
+	if (ret)
+		return log_ret(ret);
+
+	/* de-assert all chip selects */
+	if (IS_ENABLED(CONFIG_DM_GPIO)) {
+		for (int i = 0; i < ARRAY_SIZE(aq->cs_gpios); i++) {
+			if (dm_gpio_is_valid(&aq->cs_gpios[i]))
+				dm_gpio_set_value(&aq->cs_gpios[i], 0);
+		}
+	}
+
+	atmel_qspi_write(QSPI_CR_QSPIEN, aq, QSPI_CR);
+
+	return 0;
+}
+
+static int atmel_qspi_release_bus(struct udevice *dev)
+{
+	struct udevice *bus = dev_get_parent(dev);
+	struct atmel_qspi *aq = dev_get_priv(bus);
+
+	/* de-assert all chip selects */
+	if (IS_ENABLED(CONFIG_DM_GPIO)) {
+		for (int i = 0; i < ARRAY_SIZE(aq->cs_gpios); i++) {
+			if (dm_gpio_is_valid(&aq->cs_gpios[i]))
+				dm_gpio_set_value(&aq->cs_gpios[i], 0);
+		}
+	}
+
+	atmel_qspi_write(QSPI_CR_QSPIDIS, aq, QSPI_CR);
+
+	return 0;
+}
+
+static int atmel_qspi_set_cs(struct udevice *dev, int value)
+{
+	struct udevice *bus = dev_get_parent(dev);
+	struct atmel_qspi *aq = dev_get_priv(bus);
+	int cs = spi_chip_select(dev);
+
+	if (IS_ENABLED(CONFIG_DM_GPIO)) {
+		if (!dm_gpio_is_valid(&aq->cs_gpios[cs]))
+			return log_ret(-ENOENT);
+
+		return dm_gpio_set_value(&aq->cs_gpios[cs], value);
+	} else {
+		return -ENOENT;
+	}
+}
+
+static int atmel_qspi_xfer(struct udevice *dev, unsigned int bitlen,
+			   const void *dout, void *din, unsigned long flags)
+{
+	struct udevice *bus = dev_get_parent(dev);
+	struct atmel_qspi *aq = dev_get_priv(bus);
+	unsigned int len, len_rx, len_tx;
+	const u8 *txp = dout;
+	u8 *rxp = din;
+	u32 reg;
+	int ret;
+
+	if (bitlen == 0)
+		goto out;
+
+	if (bitlen % 8) {
+		flags |= SPI_XFER_END;
+		goto out;
+	}
+
+	len = bitlen / 8;
+
+	if (flags & SPI_XFER_BEGIN) {
+		ret = atmel_qspi_set_cs(dev, 1);
+		if (ret)
+			return log_ret(ret);
+		reg = atmel_qspi_read(aq, QSPI_RD);
+	}
+
+	for (len_tx = 0, len_rx = 0; len_rx < len; ) {
+		u32 status = atmel_qspi_read(aq, QSPI_SR);
+		u8 value;
+
+		if (status & QSPI_SR_OVRES)
+			return log_ret(-1);
+
+		if (len_tx < len && (status & QSPI_SR_TDRE)) {
+			if (txp)
+				value = *txp++;
+			else
+				value = 0;
+			atmel_qspi_write(value, aq, QSPI_TD);
+			len_tx++;
+		}
+
+		if (status & QSPI_SR_RDRF) {
+			value = atmel_qspi_read(aq, QSPI_RD);
+			if (rxp)
+				*rxp++ = value;
+			len_rx++;
+		}
+	}
+
+out:
+	if (flags & SPI_XFER_END) {
+		readl_poll_timeout(aq->regs + QSPI_SR, reg,
+				   reg & QSPI_SR_TXEMPTY,
+				   ATMEL_QSPI_TIMEOUT);
+
+		atmel_qspi_write(QSPI_CR_LASTXFER, aq, QSPI_CR);
+
+		ret = atmel_qspi_set_cs(dev, 0);
+		if (ret)
+			return log_ret(ret);
+	}
+
+	return 0;
+}
+
 static int atmel_qspi_set_speed(struct udevice *bus, uint hz)
 {
 	struct atmel_qspi *aq = dev_get_priv(bus);
@@ -939,6 +1082,7 @@ static int atmel_qspi_set_speed(struct udevice *bus, uint hz)
 		return atmel_qspi_sama7g5_set_speed(bus, hz);
 
 	/* Compute the QSPI baudrate */
+	dev_dbg(bus, "bus_clk_rate: %lu, hz: %u\n", aq->bus_clk_rate, hz);
 	scbr = DIV_ROUND_UP(aq->bus_clk_rate, hz);
 	if (scbr > 0)
 		scbr--;
@@ -1046,10 +1190,6 @@ static int atmel_qspi_init(struct atmel_qspi *aq)
 	/* Reset the QSPI controller */
 	atmel_qspi_write(QSPI_CR_SWRST, aq, QSPI_CR);
 
-	/* Set the QSPI controller by default in Serial Memory Mode */
-	atmel_qspi_write(QSPI_MR_SMM, aq, QSPI_MR);
-	aq->mr = QSPI_MR_SMM;
-
 	/* Enable the QSPI controller */
 	atmel_qspi_write(QSPI_CR_QSPIEN, aq, QSPI_CR);
 
@@ -1075,7 +1215,7 @@ static int atmel_qspi_probe(struct udevice *dev)
 	aq->caps = (struct atmel_qspi_caps *)dev_get_driver_data(dev);
 	if (!aq->caps) {
 		dev_err(dev, "Could not retrieve QSPI caps\n");
-		return -EINVAL;
+		return log_ret(-EINVAL);
 	};
 
 	if (aq->caps->has_gclk)
@@ -1083,36 +1223,53 @@ static int atmel_qspi_probe(struct udevice *dev)
 	else
 		aq->ops = &atmel_qspi_priv_ops;
 
+	if (IS_ENABLED(CONFIG_DM_GPIO)) {
+		ret = gpio_request_list_by_name(dev, "cs-gpios", aq->cs_gpios,
+						ARRAY_SIZE(aq->cs_gpios), 0);
+		if (ret < 0) {
+			pr_err("Can't get %s gpios! Error: %d", dev->name, ret);
+			return log_ret(ret);
+		}
+
+		for (int i = 0; i < ARRAY_SIZE(aq->cs_gpios); i++) {
+			if (!dm_gpio_is_valid(&aq->cs_gpios[i]))
+				continue;
+
+			dm_gpio_set_dir_flags(&aq->cs_gpios[i],
+					      GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
+		}
+	}
+
 	/* Map the registers */
 	ret = dev_read_resource_byname(dev, "qspi_base", &res);
 	if (ret) {
 		dev_err(dev, "missing registers\n");
-		return ret;
+		return log_ret(ret);
 	}
 
 	aq->regs = devm_ioremap(dev, res.start, resource_size(&res));
 	if (IS_ERR(aq->regs))
-		return PTR_ERR(aq->regs);
+		return log_ret(PTR_ERR(aq->regs));
 
 	/* Map the AHB memory */
 	ret = dev_read_resource_byname(dev, "qspi_mmap", &res);
 	if (ret) {
 		dev_err(dev, "missing AHB memory\n");
-		return ret;
+		return log_ret(ret);
 	}
 
 	aq->mem = devm_ioremap(dev, res.start, resource_size(&res));
 	if (IS_ERR(aq->mem))
-		return PTR_ERR(aq->mem);
+		return log_ret(PTR_ERR(aq->mem));
 
 	aq->mmap_size = resource_size(&res);
 
 	ret = atmel_qspi_enable_clk(dev);
 	if (ret)
-		return ret;
+		return log_ret(ret);
 
 	aq->dev = dev;
-	return atmel_qspi_init(aq);
+	return log_ret(atmel_qspi_init(aq));
 }
 
 static const struct spi_controller_mem_ops atmel_qspi_mem_ops = {
@@ -1121,9 +1278,12 @@ static const struct spi_controller_mem_ops atmel_qspi_mem_ops = {
 };
 
 static const struct dm_spi_ops atmel_qspi_ops = {
+	.claim_bus = atmel_qspi_claim_bus,
+	.release_bus = atmel_qspi_release_bus,
+	.xfer = atmel_qspi_xfer,
+	.mem_ops = &atmel_qspi_mem_ops,
 	.set_speed = atmel_qspi_set_speed,
 	.set_mode = atmel_qspi_set_mode,
-	.mem_ops = &atmel_qspi_mem_ops,
 };
 
 static const struct atmel_qspi_caps atmel_sama5d2_qspi_caps = {};
diff --git a/drivers/spi/soft_spi.c b/drivers/spi/soft_spi.c
index a8ec2f4f7b4..50bd7be5640 100644
--- a/drivers/spi/soft_spi.c
+++ b/drivers/spi/soft_spi.c
@@ -124,8 +124,19 @@ static int soft_spi_xfer(struct udevice *dev, unsigned int bitlen,
 	u8		*rxd = din;
 	int		cpha = !!(priv->mode & SPI_CPHA);
 	int		cidle = !!(priv->mode & SPI_CPOL);
+	int		txrx = plat->flags;
 	unsigned int	j;
 
+	if (priv->mode & SPI_3WIRE) {
+		if (txd && rxd)
+			return -EINVAL;
+
+		txrx = txd ? SPI_MASTER_NO_RX : SPI_MASTER_NO_TX;
+		dm_gpio_set_dir_flags(&plat->mosi,
+				      txd ? GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE :
+					    GPIOD_IS_IN | GPIOD_PULL_UP);
+	}
+
 	debug("spi_xfer: slave %s:%s dout %08X din %08X bitlen %u\n",
 	      dev->parent->name, dev->name, *(uint *)txd, *(uint *)rxd,
 	      bitlen);
@@ -160,7 +171,7 @@ static int soft_spi_xfer(struct udevice *dev, unsigned int bitlen,
 		 */
 		if (cpha)
 			soft_spi_scl(dev, !cidle);
-		if ((plat->flags & SPI_MASTER_NO_TX) == 0)
+		if ((txrx & SPI_MASTER_NO_TX) == 0)
 			soft_spi_sda(dev, !!(tmpdout & 0x80));
 		udelay(plat->spi_delay_us);
 
@@ -174,8 +185,10 @@ static int soft_spi_xfer(struct udevice *dev, unsigned int bitlen,
 		else
 			soft_spi_scl(dev, cidle);
 		tmpdin	<<= 1;
-		if ((plat->flags & SPI_MASTER_NO_RX) == 0)
-			tmpdin	|= dm_gpio_get_value(&plat->miso);
+		if ((txrx & SPI_MASTER_NO_RX) == 0)
+			tmpdin |= dm_gpio_get_value((priv->mode & SPI_3WIRE) ?
+							    &plat->mosi :
+							    &plat->miso);
 		tmpdout	<<= 1;
 		udelay(plat->spi_delay_us);
 
diff --git a/drivers/sysinfo/Kconfig b/drivers/sysinfo/Kconfig
index 2030e4babc9..df83df69ffb 100644
--- a/drivers/sysinfo/Kconfig
+++ b/drivers/sysinfo/Kconfig
@@ -31,6 +31,13 @@ config SYSINFO_RCAR3
 	help
 	  Support querying SoC version information for Renesas R-Car Gen3.
 
+config SYSINFO_IOT2050
+	bool "Enable sysinfo driver for the Siemens IOT2050"
+	depends on TARGET_IOT2050_A53
+	default y if TARGET_IOT2050_A53
+	help
+	  Support querying device information for Siemens IOT2050.
+
 config SYSINFO_SANDBOX
 	bool "Enable sysinfo driver for the Sandbox board"
 	help
diff --git a/drivers/sysinfo/Makefile b/drivers/sysinfo/Makefile
index 680dde77fe8..26ca3150999 100644
--- a/drivers/sysinfo/Makefile
+++ b/drivers/sysinfo/Makefile
@@ -5,6 +5,7 @@
 obj-y += sysinfo-uclass.o
 obj-$(CONFIG_SYSINFO_GAZERBEAM) += gazerbeam.o
 obj-$(CONFIG_SYSINFO_GPIO) += gpio.o
+obj-$(CONFIG_SYSINFO_IOT2050) += iot2050.o
 obj-$(CONFIG_SYSINFO_RCAR3) += rcar3.o
 obj-$(CONFIG_SYSINFO_SANDBOX) += sandbox.o
 obj-$(CONFIG_SYSINFO_SMBIOS) += smbios.o
diff --git a/drivers/sysinfo/iot2050.c b/drivers/sysinfo/iot2050.c
new file mode 100644
index 00000000000..579a9f4711d
--- /dev/null
+++ b/drivers/sysinfo/iot2050.c
@@ -0,0 +1,202 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) Siemens AG, 2025
+ */
+
+#include <dm.h>
+#include <sysinfo.h>
+#include <net.h>
+#include <u-boot/uuid.h>
+#include <asm/arch/hardware.h>
+
+#include "iot2050.h"
+
+#define IOT2050_INFO_MAGIC		0x20502050
+
+#define IOT2050_UUID_STR_LEN		(32)
+
+struct iot2050_info {
+	u32 magic;
+	u16 size;
+	char name[20 + 1];
+	char serial[16 + 1];
+	char mlfb[18 + 1];
+	char uuid[IOT2050_UUID_STR_LEN + 1];
+	char a5e[18 + 1];
+	u8 mac_addr_cnt;
+	u8 mac_addr[8][ARP_HLEN];
+	char seboot_version[40 + 1];
+	u8 padding[3];
+	u32 ddr_size_mb;
+} __packed;
+
+/**
+ * struct sysinfo_iot2050_priv - sysinfo private data
+ * @info: iot2050 board info
+ */
+struct sysinfo_iot2050_priv {
+	struct iot2050_info *info;
+	u8 uuid_smbios[16];
+};
+
+static int sysinfo_iot2050_detect(struct udevice *dev)
+{
+	struct sysinfo_iot2050_priv *priv = dev_get_priv(dev);
+
+	if (!priv->info || priv->info->magic != IOT2050_INFO_MAGIC)
+		return -EFAULT;
+
+	return 0;
+}
+
+static int sysinfo_iot2050_get_str(struct udevice *dev, int id, size_t size,
+				   char *val)
+{
+	struct sysinfo_iot2050_priv *priv = dev_get_priv(dev);
+
+	switch (id) {
+	case BOARD_NAME:
+	case SYSID_SM_BASEBOARD_VERSION:
+		strlcpy(val, priv->info->name, size);
+		break;
+	case SYSID_SM_SYSTEM_SERIAL:
+		strlcpy(val, priv->info->serial, size);
+		break;
+	case BOARD_MLFB:
+	case SYSID_SM_SYSTEM_VERSION:
+		strlcpy(val, priv->info->mlfb, size);
+		break;
+	case BOARD_UUID:
+		strlcpy(val, priv->info->uuid, size);
+		break;
+	case BOARD_A5E:
+	case SYSID_SM_BASEBOARD_PRODUCT:
+		strlcpy(val, priv->info->a5e, size);
+		break;
+	case BOARD_SEBOOT_VER:
+	case SYSID_PRIOR_STAGE_VERSION:
+		strlcpy(val, priv->info->seboot_version, size);
+		break;
+	default:
+		return -EINVAL;
+	};
+
+	val[size - 1] = '\0';
+	return 0;
+}
+
+static int sysinfo_iot2050_get_int(struct udevice *dev, int id, int *val)
+{
+	struct sysinfo_iot2050_priv *priv = dev_get_priv(dev);
+
+	switch (id) {
+	case SYSID_BOARD_RAM_SIZE_MB:
+		*val = priv->info->ddr_size_mb;
+		return 0;
+	default:
+		return -EINVAL;
+	};
+}
+
+static int sysinfo_iot2050_get_data(struct udevice *dev, int id, void **data,
+				    size_t *size)
+{
+	struct sysinfo_iot2050_priv *priv = dev_get_priv(dev);
+
+	switch (id) {
+	case SYSID_SM_SYSTEM_UUID:
+		*data = priv->uuid_smbios;
+		*size = 16;
+		return 0;
+	default:
+		return -EINVAL;
+	};
+}
+
+static int sysinfo_iot2050_get_item_count(struct udevice *dev, int id)
+{
+	struct sysinfo_iot2050_priv *priv = dev_get_priv(dev);
+
+	switch (id) {
+	case SYSID_BOARD_MAC_ADDR:
+		return priv->info->mac_addr_cnt;
+	default:
+		return -EINVAL;
+	};
+}
+
+static int sysinfo_iot2050_get_data_by_index(struct udevice *dev, int id,
+					     int index, void **data,
+					     size_t *size)
+{
+	struct sysinfo_iot2050_priv *priv = dev_get_priv(dev);
+
+	switch (id) {
+	case SYSID_BOARD_MAC_ADDR:
+		if (index >= priv->info->mac_addr_cnt)
+			return -EINVAL;
+		*data = priv->info->mac_addr[index];
+		*size = ARP_HLEN;
+		return 0;
+	default:
+		return -EINVAL;
+	};
+}
+
+static const struct sysinfo_ops sysinfo_iot2050_ops = {
+	.detect = sysinfo_iot2050_detect,
+	.get_str = sysinfo_iot2050_get_str,
+	.get_int = sysinfo_iot2050_get_int,
+	.get_data = sysinfo_iot2050_get_data,
+	.get_item_count = sysinfo_iot2050_get_item_count,
+	.get_data_by_index = sysinfo_iot2050_get_data_by_index,
+};
+
+/**
+ * @brief Convert the IOT2050 UUID string to the SMBIOS format
+ *
+ * @param uuid_raw The IOT2050 UUID string parsed from the eeprom
+ * @param uuid_smbios The buffer to hold the SMBIOS formatted UUID
+ */
+static void sysinfo_iot2050_convert_uuid(const char *uuid_iot2050,
+					 u8 *uuid_smbios)
+{
+	char uuid_rfc4122_str[IOT2050_UUID_STR_LEN + 4 + 1] = {0};
+	char *tmp = uuid_rfc4122_str;
+
+	for (int i = 0; i < 16; i++) {
+		memcpy(tmp, uuid_iot2050 + i * 2, 2);
+		tmp += 2;
+		if (i == 3 || i == 5 || i == 7 || i == 9)
+			*tmp++ = '-';
+	}
+	uuid_str_to_bin(uuid_rfc4122_str, uuid_smbios, UUID_STR_FORMAT_GUID);
+}
+
+static int sysinfo_iot2050_probe(struct udevice *dev)
+{
+	struct sysinfo_iot2050_priv *priv = dev_get_priv(dev);
+	unsigned long offset;
+
+	offset = dev_read_u32_default(dev, "offset",
+				      TI_SRAM_SCRATCH_BOARD_EEPROM_START);
+	priv->info = (struct iot2050_info *)offset;
+
+	sysinfo_iot2050_convert_uuid(priv->info->uuid, priv->uuid_smbios);
+
+	return 0;
+}
+
+static const struct udevice_id sysinfo_iot2050_ids[] = {
+	{ .compatible = "siemens,sysinfo-iot2050" },
+	{ /* sentinel */ }
+};
+
+U_BOOT_DRIVER(sysinfo_iot2050) = {
+	.name           = "sysinfo_iot2050",
+	.id             = UCLASS_SYSINFO,
+	.of_match       = sysinfo_iot2050_ids,
+	.ops		= &sysinfo_iot2050_ops,
+	.priv_auto	= sizeof(struct sysinfo_iot2050_priv),
+	.probe          = sysinfo_iot2050_probe,
+};
diff --git a/drivers/sysinfo/iot2050.h b/drivers/sysinfo/iot2050.h
new file mode 100644
index 00000000000..657221db096
--- /dev/null
+++ b/drivers/sysinfo/iot2050.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) Siemens AG, 2025
+ */
+
+#include <sysinfo.h>
+
+enum sysinfo_id_iot2050 {
+	BOARD_MLFB		= SYSID_USER,
+	BOARD_A5E,
+	BOARD_NAME,
+	BOARD_UUID,
+	BOARD_SEBOOT_VER,
+};
diff --git a/drivers/sysinfo/sysinfo-uclass.c b/drivers/sysinfo/sysinfo-uclass.c
index 3c0cd51273e..f04998ef8bb 100644
--- a/drivers/sysinfo/sysinfo-uclass.c
+++ b/drivers/sysinfo/sysinfo-uclass.c
@@ -119,6 +119,35 @@ int sysinfo_get_data(struct udevice *dev, int id, void **data, size_t *size)
 	return ops->get_data(dev, id, data, size);
 }
 
+int sysinfo_get_item_count(struct udevice *dev, int id)
+{
+	struct sysinfo_priv *priv = dev_get_uclass_priv(dev);
+	struct sysinfo_ops *ops = sysinfo_get_ops(dev);
+
+	if (!priv->detected)
+		return -EPERM;
+
+	if (!ops->get_item_count)
+		return -ENOSYS;
+
+	return ops->get_item_count(dev, id);
+}
+
+int sysinfo_get_data_by_index(struct udevice *dev, int id, int index,
+			      void **data, size_t *size)
+{
+	struct sysinfo_priv *priv = dev_get_uclass_priv(dev);
+	struct sysinfo_ops *ops = sysinfo_get_ops(dev);
+
+	if (!priv->detected)
+		return -EPERM;
+
+	if (!ops->get_data_by_index)
+		return -ENOSYS;
+
+	return ops->get_data_by_index(dev, id, index, data, size);
+}
+
 UCLASS_DRIVER(sysinfo) = {
 	.id		= UCLASS_SYSINFO,
 	.name		= "sysinfo",
diff --git a/drivers/sysreset/Kconfig b/drivers/sysreset/Kconfig
index 121194e4418..475540ffac7 100644
--- a/drivers/sysreset/Kconfig
+++ b/drivers/sysreset/Kconfig
@@ -242,7 +242,6 @@ config SYSRESET_RAA215300
 
 config SYSRESET_QCOM_PSHOLD
 	bool "Support sysreset for Qualcomm SoCs via PSHOLD"
-	depends on ARCH_IPQ40XX
 	help
 	  Add support for the system reboot on Qualcomm SoCs via PSHOLD.
 
diff --git a/drivers/timer/sandbox_timer.c b/drivers/timer/sandbox_timer.c
index e8b54a02965..c1baf3c69ec 100644
--- a/drivers/timer/sandbox_timer.c
+++ b/drivers/timer/sandbox_timer.c
@@ -18,6 +18,11 @@ void timer_test_add_offset(unsigned long offset)
 	sandbox_timer_offset += offset;
 }
 
+ulong timer_test_get_offset(void)
+{
+	return sandbox_timer_offset;
+};
+
 u64 notrace timer_early_get_count(void)
 {
 	return os_get_nsec() / 1000 + sandbox_timer_offset * 1000;
diff --git a/drivers/ufs/ufs.c b/drivers/ufs/ufs.c
index f7d8c40c448..91f6ad3bfef 100644
--- a/drivers/ufs/ufs.c
+++ b/drivers/ufs/ufs.c
@@ -19,6 +19,7 @@
 #include <malloc.h>
 #include <hexdump.h>
 #include <scsi.h>
+#include <ufs.h>
 #include <asm/io.h>
 #include <asm/dma-mapping.h>
 #include <linux/bitops.h>
@@ -313,16 +314,12 @@ static int ufshcd_disable_tx_lcc(struct ufs_hba *hba, bool peer)
 		ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES),
 				    &tx_lanes);
 	for (i = 0; i < tx_lanes; i++) {
+		unsigned int val = UIC_ARG_MIB_SEL(TX_LCC_ENABLE,
+						   UIC_ARG_MPHY_TX_GEN_SEL_INDEX(i));
 		if (!peer)
-			err = ufshcd_dme_set(hba,
-					     UIC_ARG_MIB_SEL(TX_LCC_ENABLE,
-					     UIC_ARG_MPHY_TX_GEN_SEL_INDEX(i)),
-					     0);
+			err = ufshcd_dme_set(hba, val, 0);
 		else
-			err = ufshcd_dme_peer_set(hba,
-					UIC_ARG_MIB_SEL(TX_LCC_ENABLE,
-					UIC_ARG_MPHY_TX_GEN_SEL_INDEX(i)),
-					0);
+			err = ufshcd_dme_peer_set(hba, val, 0);
 		if (err) {
 			dev_err(hba->dev, "%s: TX LCC Disable failed, peer = %d, lane = %d, err = %d\n",
 				__func__, peer, i, err);
@@ -1034,8 +1031,8 @@ static inline void ufshcd_init_query(struct ufs_hba *hba,
 /**
  * ufshcd_query_flag() - API function for sending flag query requests
  */
-int ufshcd_query_flag(struct ufs_hba *hba, enum query_opcode opcode,
-		      enum flag_idn idn, bool *flag_res)
+static int ufshcd_query_flag(struct ufs_hba *hba, enum query_opcode opcode,
+			     enum flag_idn idn, bool *flag_res)
 {
 	struct ufs_query_req *request = NULL;
 	struct ufs_query_res *response = NULL;
@@ -1170,9 +1167,9 @@ out:
 /**
  * ufshcd_query_descriptor_retry - API function for sending descriptor requests
  */
-int ufshcd_query_descriptor_retry(struct ufs_hba *hba, enum query_opcode opcode,
-				  enum desc_idn idn, u8 index, u8 selector,
-				  u8 *desc_buf, int *buf_len)
+static int ufshcd_query_descriptor_retry(struct ufs_hba *hba, enum query_opcode opcode,
+					 enum desc_idn idn, u8 index, u8 selector,
+					 u8 *desc_buf, int *buf_len)
 {
 	int err;
 	int retries;
@@ -1264,8 +1261,8 @@ static void ufshcd_init_desc_sizes(struct ufs_hba *hba)
  * ufshcd_map_desc_id_to_length - map descriptor IDN to its length
  *
  */
-int ufshcd_map_desc_id_to_length(struct ufs_hba *hba, enum desc_idn desc_id,
-				 int *desc_len)
+static int ufshcd_map_desc_id_to_length(struct ufs_hba *hba, enum desc_idn desc_id,
+					int *desc_len)
 {
 	switch (desc_id) {
 	case QUERY_DESC_IDN_DEVICE:
@@ -1302,15 +1299,14 @@ int ufshcd_map_desc_id_to_length(struct ufs_hba *hba, enum desc_idn desc_id,
 	}
 	return 0;
 }
-EXPORT_SYMBOL(ufshcd_map_desc_id_to_length);
 
 /**
  * ufshcd_read_desc_param - read the specified descriptor parameter
  *
  */
-int ufshcd_read_desc_param(struct ufs_hba *hba, enum desc_idn desc_id,
-			   int desc_index, u8 param_offset, u8 *param_read_buf,
-			   u8 param_size)
+static int ufshcd_read_desc_param(struct ufs_hba *hba, enum desc_idn desc_id,
+				  int desc_index, u8 param_offset,
+				  u8 *param_read_buf, u8 param_size)
 {
 	int ret;
 	u8 *desc_buf;
@@ -1569,8 +1565,8 @@ static int ufshcd_read_device_desc(struct ufs_hba *hba, u8 *buf, u32 size)
  * ufshcd_read_string_desc - read string descriptor
  *
  */
-int ufshcd_read_string_desc(struct ufs_hba *hba, int desc_index,
-			    u8 *buf, u32 size, bool ascii)
+static int ufshcd_read_string_desc(struct ufs_hba *hba, int desc_index,
+				   u8 *buf, u32 size, bool ascii)
 {
 	int err = 0;
 
@@ -1881,7 +1877,7 @@ static void ufshcd_def_desc_sizes(struct ufs_hba *hba)
 	hba->desc_size.hlth_desc = QUERY_DESC_HEALTH_DEF_SIZE;
 }
 
-int ufs_start(struct ufs_hba *hba)
+static int ufs_start(struct ufs_hba *hba)
 {
 	struct ufs_dev_desc card = {0};
 	int ret;
@@ -1962,7 +1958,7 @@ int ufshcd_probe(struct udevice *ufs_dev, struct ufs_hba_ops *hba_ops)
 
 	ufshcd_ops_init(hba);
 
-	/* Read capabilties registers */
+	/* Read capabilities registers */
 	hba->capabilities = ufshcd_readl(hba, REG_CONTROLLER_CAPABILITIES);
 	if (hba->quirks & UFSHCD_QUIRK_BROKEN_64BIT_ADDRESS)
 		hba->capabilities &= ~MASK_64_ADDRESSING_SUPPORT;
@@ -2001,7 +1997,7 @@ int ufshcd_probe(struct udevice *ufs_dev, struct ufs_hba_ops *hba_ops)
 		      REG_INTERRUPT_STATUS);
 	ufshcd_writel(hba, 0, REG_INTERRUPT_ENABLE);
 
-	mb();
+	mb(); /* flush previous writes */
 
 	/* Reset the attached device */
 	ufshcd_device_reset(hba);
diff --git a/drivers/ufs/ufs.h b/drivers/ufs/ufs.h
index 00ecca350c3..53137fae3a8 100644
--- a/drivers/ufs/ufs.h
+++ b/drivers/ufs/ufs.h
@@ -4,6 +4,7 @@
 
 #include <linux/types.h>
 #include <asm/io.h>
+#include "ufshci.h"
 #include "unipro.h"
 
 struct udevice;
@@ -14,11 +15,6 @@ struct udevice;
 #define RESPONSE_UPIU_SENSE_DATA_LENGTH	18
 #define UFS_MAX_LUNS		0x7F
 
-enum {
-	TASK_REQ_UPIU_SIZE_DWORDS	= 8,
-	TASK_RSP_UPIU_SIZE_DWORDS	= 8,
-	ALIGNED_UPIU_SIZE		= 512,
-};
 
 /* UFS device power modes */
 enum ufs_dev_pwr_mode {
@@ -84,44 +80,6 @@ enum {
 /* Offset of the response code in the UPIU header */
 #define UPIU_RSP_CODE_OFFSET		8
 
-/* To accommodate UFS2.0 required Command type */
-enum {
-	UTP_CMD_TYPE_UFS_STORAGE	= 0x1,
-};
-
-enum {
-	UTP_SCSI_COMMAND		= 0x00000000,
-	UTP_NATIVE_UFS_COMMAND		= 0x10000000,
-	UTP_DEVICE_MANAGEMENT_FUNCTION	= 0x20000000,
-	UTP_REQ_DESC_INT_CMD		= 0x01000000,
-};
-
-/* UTP Transfer Request Data Direction (DD) */
-enum {
-	UTP_NO_DATA_TRANSFER	= 0x00000000,
-	UTP_HOST_TO_DEVICE	= 0x02000000,
-	UTP_DEVICE_TO_HOST	= 0x04000000,
-};
-
-/* Overall command status values */
-enum {
-	OCS_SUCCESS			= 0x0,
-	OCS_INVALID_CMD_TABLE_ATTR	= 0x1,
-	OCS_INVALID_PRDT_ATTR		= 0x2,
-	OCS_MISMATCH_DATA_BUF_SIZE	= 0x3,
-	OCS_MISMATCH_RESP_UPIU_SIZE	= 0x4,
-	OCS_PEER_COMM_FAILURE		= 0x5,
-	OCS_ABORTED			= 0x6,
-	OCS_FATAL_ERROR			= 0x7,
-	OCS_INVALID_COMMAND_STATUS	= 0x0F,
-	MASK_OCS			= 0x0F,
-};
-
-/* The maximum length of the data byte count field in the PRDT is 256KB */
-#define PRDT_DATA_BYTE_COUNT_MAX	(256 * 1024)
-/* The granularity of the data byte count field in the PRDT is 32-bit */
-#define PRDT_DATA_BYTE_COUNT_PAD	4
-
 #define GENERAL_UPIU_REQUEST_SIZE (sizeof(struct utp_upiu_req))
 #define QUERY_DESC_MAX_SIZE       255
 #define QUERY_DESC_MIN_SIZE       2
@@ -130,8 +88,8 @@ enum {
 					(sizeof(struct utp_upiu_header)))
 #define RESPONSE_UPIU_SENSE_DATA_LENGTH	18
 #define UPIU_HEADER_DWORD(byte3, byte2, byte1, byte0)\
-			cpu_to_be32((byte3 << 24) | (byte2 << 16) |\
-			 (byte1 << 8) | (byte0))
+			cpu_to_be32(((byte3) << 24) | ((byte2) << 16) |\
+			 ((byte1) << 8) | (byte0))
 /*
  * UFS Protocol Information Unit related definitions
  */
@@ -297,79 +255,6 @@ enum desc_header_offset {
 	QUERY_DESC_DESC_TYPE_OFFSET	= 0x01,
 };
 
-struct ufshcd_sg_entry {
-	__le32    base_addr;
-	__le32    upper_addr;
-	__le32    reserved;
-	__le32    size;
-};
-
-#define MAX_BUFF	128
-/**
- * struct utp_transfer_cmd_desc - UFS Command Descriptor structure
- * @command_upiu: Command UPIU Frame address
- * @response_upiu: Response UPIU Frame address
- * @prd_table: Physical Region Descriptor
- */
-struct utp_transfer_cmd_desc {
-	u8 command_upiu[ALIGNED_UPIU_SIZE];
-	u8 response_upiu[ALIGNED_UPIU_SIZE];
-	struct ufshcd_sg_entry    prd_table[MAX_BUFF];
-};
-
-/**
- * struct request_desc_header - Descriptor Header common to both UTRD and UTMRD
- * @dword0: Descriptor Header DW0
- * @dword1: Descriptor Header DW1
- * @dword2: Descriptor Header DW2
- * @dword3: Descriptor Header DW3
- */
-struct request_desc_header {
-	__le32 dword_0;
-	__le32 dword_1;
-	__le32 dword_2;
-	__le32 dword_3;
-};
-
-/**
- * struct utp_transfer_req_desc - UTRD structure
- * @header: UTRD header DW-0 to DW-3
- * @command_desc_base_addr_lo: UCD base address low DW-4
- * @command_desc_base_addr_hi: UCD base address high DW-5
- * @response_upiu_length: response UPIU length DW-6
- * @response_upiu_offset: response UPIU offset DW-6
- * @prd_table_length: Physical region descriptor length DW-7
- * @prd_table_offset: Physical region descriptor offset DW-7
- */
-struct utp_transfer_req_desc {
-	/* DW 0-3 */
-	struct request_desc_header header;
-
-	/* DW 4-5*/
-	__le32  command_desc_base_addr_lo;
-	__le32  command_desc_base_addr_hi;
-
-	/* DW 6 */
-	__le16  response_upiu_length;
-	__le16  response_upiu_offset;
-
-	/* DW 7 */
-	__le16  prd_table_length;
-	__le16  prd_table_offset;
-};
-
-/**
- * struct utp_upiu_header - UPIU header structure
- * @dword_0: UPIU header DW-0
- * @dword_1: UPIU header DW-1
- * @dword_2: UPIU header DW-2
- */
-struct utp_upiu_header {
-	__be32 dword_0;
-	__be32 dword_1;
-	__be32 dword_2;
-};
-
 /**
  * struct utp_upiu_query - upiu request buffer structure for
  * query request.
@@ -403,27 +288,6 @@ struct utp_upiu_cmd {
 	u8 cdb[UFS_CDB_SIZE];
 };
 
-/*
- * UTMRD structure.
- */
-struct utp_task_req_desc {
-	/* DW 0-3 */
-	struct request_desc_header header;
-
-	/* DW 4-11 - Task request UPIU structure */
-	struct utp_upiu_header	req_header;
-	__be32			input_param1;
-	__be32			input_param2;
-	__be32			input_param3;
-	__be32			__reserved1[2];
-
-	/* DW 12-19 - Task Management Response UPIU structure */
-	struct utp_upiu_header	rsp_header;
-	__be32			output_param1;
-	__be32			output_param2;
-	__be32			__reserved2[3];
-};
-
 /**
  * struct utp_upiu_req - general upiu request structure
  * @header:UPIU header structure DW-0 to DW-2
@@ -551,63 +415,6 @@ struct uic_command {
 	int result;
 };
 
-/* GenSelectorIndex calculation macros for M-PHY attributes */
-#define UIC_ARG_MPHY_TX_GEN_SEL_INDEX(lane) (lane)
-#define UIC_ARG_MPHY_RX_GEN_SEL_INDEX(lane) (PA_MAXDATALANES + (lane))
-
-#define UIC_ARG_MIB_SEL(attr, sel)	((((attr) & 0xFFFF) << 16) |\
-					 ((sel) & 0xFFFF))
-#define UIC_ARG_MIB(attr)		UIC_ARG_MIB_SEL(attr, 0)
-#define UIC_ARG_ATTR_TYPE(t)		(((t) & 0xFF) << 16)
-#define UIC_GET_ATTR_ID(v)		(((v) >> 16) & 0xFFFF)
-
-/* Link Status*/
-enum link_status {
-	UFSHCD_LINK_IS_DOWN	= 1,
-	UFSHCD_LINK_IS_UP	= 2,
-};
-
-#define UIC_ARG_MIB_SEL(attr, sel)	((((attr) & 0xFFFF) << 16) |\
-					 ((sel) & 0xFFFF))
-#define UIC_ARG_MIB(attr)		UIC_ARG_MIB_SEL(attr, 0)
-#define UIC_ARG_ATTR_TYPE(t)		(((t) & 0xFF) << 16)
-#define UIC_GET_ATTR_ID(v)		(((v) >> 16) & 0xFFFF)
-
-/* UIC Commands */
-enum uic_cmd_dme {
-	UIC_CMD_DME_GET			= 0x01,
-	UIC_CMD_DME_SET			= 0x02,
-	UIC_CMD_DME_PEER_GET		= 0x03,
-	UIC_CMD_DME_PEER_SET		= 0x04,
-	UIC_CMD_DME_POWERON		= 0x10,
-	UIC_CMD_DME_POWEROFF		= 0x11,
-	UIC_CMD_DME_ENABLE		= 0x12,
-	UIC_CMD_DME_RESET		= 0x14,
-	UIC_CMD_DME_END_PT_RST		= 0x15,
-	UIC_CMD_DME_LINK_STARTUP	= 0x16,
-	UIC_CMD_DME_HIBER_ENTER		= 0x17,
-	UIC_CMD_DME_HIBER_EXIT		= 0x18,
-	UIC_CMD_DME_TEST_MODE		= 0x1A,
-};
-
-/* UIC Config result code / Generic error code */
-enum {
-	UIC_CMD_RESULT_SUCCESS			= 0x00,
-	UIC_CMD_RESULT_INVALID_ATTR		= 0x01,
-	UIC_CMD_RESULT_FAILURE			= 0x01,
-	UIC_CMD_RESULT_INVALID_ATTR_VALUE	= 0x02,
-	UIC_CMD_RESULT_READ_ONLY_ATTR		= 0x03,
-	UIC_CMD_RESULT_WRITE_ONLY_ATTR		= 0x04,
-	UIC_CMD_RESULT_BAD_INDEX		= 0x05,
-	UIC_CMD_RESULT_LOCKED_ATTR		= 0x06,
-	UIC_CMD_RESULT_BAD_TEST_FEATURE_INDEX	= 0x07,
-	UIC_CMD_RESULT_PEER_COMM_FAILURE	= 0x08,
-	UIC_CMD_RESULT_BUSY			= 0x09,
-	UIC_CMD_RESULT_DME_FAILURE		= 0x0A,
-};
-
-#define MASK_UIC_COMMAND_RESULT			0xFF
-
 /* Host <-> Device UniPro Link state */
 enum uic_link_state {
 	UIC_LINK_OFF_STATE	= 0, /* Link powered down or disabled */
@@ -915,7 +722,7 @@ static inline int ufshcd_ops_get_max_pwr_mode(struct ufs_hba *hba,
 }
 
 static inline int ufshcd_ops_hce_enable_notify(struct ufs_hba *hba,
-						bool status)
+					       bool status)
 {
 	if (hba->ops && hba->ops->hce_enable_notify)
 		return hba->ops->hce_enable_notify(hba, status);
@@ -940,17 +747,6 @@ static inline int ufshcd_vops_device_reset(struct ufs_hba *hba)
 	return 0;
 }
 
-/* Controller UFSHCI version */
-enum {
-	UFSHCI_VERSION_10 = 0x00010000, /* 1.0 */
-	UFSHCI_VERSION_11 = 0x00010100, /* 1.1 */
-	UFSHCI_VERSION_20 = 0x00000200, /* 2.0 */
-	UFSHCI_VERSION_21 = 0x00000210, /* 2.1 */
-	UFSHCI_VERSION_30 = 0x00000300, /* 3.0 */
-	UFSHCI_VERSION_31 = 0x00000310, /* 3.1 */
-	UFSHCI_VERSION_40 = 0x00000400, /* 4.0 */
-};
-
 /* Interrupt disable masks */
 enum {
 	/* Interrupt disable mask for UFSHCI v1.0 */
@@ -964,123 +760,6 @@ enum {
 	INTERRUPT_MASK_ALL_VER_21	= 0x71FFF,
 };
 
-/* UFSHCI Registers */
-enum {
-	REG_CONTROLLER_CAPABILITIES		= 0x00,
-	REG_UFS_VERSION				= 0x08,
-	REG_CONTROLLER_DEV_ID			= 0x10,
-	REG_CONTROLLER_PROD_ID			= 0x14,
-	REG_AUTO_HIBERNATE_IDLE_TIMER		= 0x18,
-	REG_INTERRUPT_STATUS			= 0x20,
-	REG_INTERRUPT_ENABLE			= 0x24,
-	REG_CONTROLLER_STATUS			= 0x30,
-	REG_CONTROLLER_ENABLE			= 0x34,
-	REG_UIC_ERROR_CODE_PHY_ADAPTER_LAYER	= 0x38,
-	REG_UIC_ERROR_CODE_DATA_LINK_LAYER	= 0x3C,
-	REG_UIC_ERROR_CODE_NETWORK_LAYER	= 0x40,
-	REG_UIC_ERROR_CODE_TRANSPORT_LAYER	= 0x44,
-	REG_UIC_ERROR_CODE_DME			= 0x48,
-	REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL	= 0x4C,
-	REG_UTP_TRANSFER_REQ_LIST_BASE_L	= 0x50,
-	REG_UTP_TRANSFER_REQ_LIST_BASE_H	= 0x54,
-	REG_UTP_TRANSFER_REQ_DOOR_BELL		= 0x58,
-	REG_UTP_TRANSFER_REQ_LIST_CLEAR		= 0x5C,
-	REG_UTP_TRANSFER_REQ_LIST_RUN_STOP	= 0x60,
-	REG_UTP_TASK_REQ_LIST_BASE_L		= 0x70,
-	REG_UTP_TASK_REQ_LIST_BASE_H		= 0x74,
-	REG_UTP_TASK_REQ_DOOR_BELL		= 0x78,
-	REG_UTP_TASK_REQ_LIST_CLEAR		= 0x7C,
-	REG_UTP_TASK_REQ_LIST_RUN_STOP		= 0x80,
-	REG_UIC_COMMAND				= 0x90,
-	REG_UIC_COMMAND_ARG_1			= 0x94,
-	REG_UIC_COMMAND_ARG_2			= 0x98,
-	REG_UIC_COMMAND_ARG_3			= 0x9C,
-
-	UFSHCI_REG_SPACE_SIZE			= 0xA0,
-
-	REG_UFS_CCAP				= 0x100,
-	REG_UFS_CRYPTOCAP			= 0x104,
-
-	UFSHCI_CRYPTO_REG_SPACE_SIZE		= 0x400,
-};
-
-/* Controller capability masks */
-enum {
-	MASK_TRANSFER_REQUESTS_SLOTS		= 0x0000001F,
-	MASK_TASK_MANAGEMENT_REQUEST_SLOTS	= 0x00070000,
-	MASK_AUTO_HIBERN8_SUPPORT		= 0x00800000,
-	MASK_64_ADDRESSING_SUPPORT		= 0x01000000,
-	MASK_OUT_OF_ORDER_DATA_DELIVERY_SUPPORT	= 0x02000000,
-	MASK_UIC_DME_TEST_MODE_SUPPORT		= 0x04000000,
-};
-
-/* Interrupt Status 20h */
-#define UTP_TRANSFER_REQ_COMPL			0x1
-#define UIC_DME_END_PT_RESET			0x2
-#define UIC_ERROR				0x4
-#define UIC_TEST_MODE				0x8
-#define UIC_POWER_MODE				0x10
-#define UIC_HIBERNATE_EXIT			0x20
-#define UIC_HIBERNATE_ENTER			0x40
-#define UIC_LINK_LOST				0x80
-#define UIC_LINK_STARTUP			0x100
-#define UTP_TASK_REQ_COMPL			0x200
-#define UIC_COMMAND_COMPL			0x400
-#define DEVICE_FATAL_ERROR			0x800
-#define CONTROLLER_FATAL_ERROR			0x10000
-#define SYSTEM_BUS_FATAL_ERROR			0x20000
-
-#define UFSHCD_UIC_PWR_MASK	(UIC_HIBERNATE_ENTER |\
-				UIC_HIBERNATE_EXIT |\
-				UIC_POWER_MODE)
-
-#define UFSHCD_UIC_MASK		(UIC_COMMAND_COMPL | UIC_POWER_MODE)
-
-#define UFSHCD_ERROR_MASK	(UIC_ERROR |\
-				DEVICE_FATAL_ERROR |\
-				CONTROLLER_FATAL_ERROR |\
-				SYSTEM_BUS_FATAL_ERROR)
-
-#define INT_FATAL_ERRORS	(DEVICE_FATAL_ERROR |\
-				CONTROLLER_FATAL_ERROR |\
-				SYSTEM_BUS_FATAL_ERROR)
-
-/* Host Controller Enable 0x34h */
-#define CONTROLLER_ENABLE	0x1
-#define CONTROLLER_DISABLE	0x0
-/* HCS - Host Controller Status 30h */
-#define DEVICE_PRESENT				0x1
-#define UTP_TRANSFER_REQ_LIST_READY		0x2
-#define UTP_TASK_REQ_LIST_READY			0x4
-#define UIC_COMMAND_READY			0x8
-#define HOST_ERROR_INDICATOR			0x10
-#define DEVICE_ERROR_INDICATOR			0x20
-#define UIC_POWER_MODE_CHANGE_REQ_STATUS_MASK	UFS_MASK(0x7, 8)
-
-#define UFSHCD_STATUS_READY	(UTP_TRANSFER_REQ_LIST_READY |\
-				UTP_TASK_REQ_LIST_READY |\
-				UIC_COMMAND_READY)
-
-enum {
-	PWR_OK		= 0x0,
-	PWR_LOCAL	= 0x01,
-	PWR_REMOTE	= 0x02,
-	PWR_BUSY	= 0x03,
-	PWR_ERROR_CAP	= 0x04,
-	PWR_FATAL_ERROR	= 0x05,
-};
-
-/* UICCMD - UIC Command */
-#define COMMAND_OPCODE_MASK		0xFF
-#define GEN_SELECTOR_INDEX_MASK		0xFFFF
-
-#define MIB_ATTRIBUTE_MASK		UFS_MASK(0xFFFF, 16)
-#define RESET_LEVEL			0xFF
-
-#define ATTR_SET_TYPE_MASK		UFS_MASK(0xFF, 16)
-#define CFG_RESULT_CODE_MASK		0xFF
-#define GENERIC_ERROR_CODE_MASK		0xFF
-
 #define ufshcd_writel(hba, val, reg)   \
 	writel((val), (hba)->mmio_base + (reg))
 #define ufshcd_readl(hba, reg) \
@@ -1103,12 +782,6 @@ static inline void ufshcd_rmwl(struct ufs_hba *hba, u32 mask, u32 val, u32 reg)
 	ufshcd_writel(hba, tmp, reg);
 }
 
-/* UTRLRSR - UTP Transfer Request Run-Stop Register 60h */
-#define UTP_TRANSFER_REQ_LIST_RUN_STOP_BIT	0x1
-
-/* UTMRLRSR - UTP Task Management Request Run-Stop Register 80h */
-#define UTP_TASK_REQ_LIST_RUN_STOP_BIT		0x1
-
 int ufshcd_probe(struct udevice *dev, struct ufs_hba_ops *hba_ops);
 
 #endif
diff --git a/drivers/ufs/ufshci.h b/drivers/ufs/ufshci.h
new file mode 100644
index 00000000000..90cbf87a3a4
--- /dev/null
+++ b/drivers/ufs/ufshci.h
@@ -0,0 +1,469 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+#ifndef __UFSHCI_H
+#define __UFSHCI_H
+
+enum {
+	TASK_REQ_UPIU_SIZE_DWORDS	= 8,
+	TASK_RSP_UPIU_SIZE_DWORDS	= 8,
+	ALIGNED_UPIU_SIZE		= 512,
+};
+
+/* UFSHCI Registers */
+enum {
+	REG_CONTROLLER_CAPABILITIES		= 0x00,
+	REG_MCQCAP				= 0x04,
+	REG_UFS_VERSION				= 0x08,
+	REG_EXT_CONTROLLER_CAPABILITIES		= 0x0C,
+	REG_CONTROLLER_PID			= 0x10,
+	REG_CONTROLLER_MID			= 0x14,
+	REG_AUTO_HIBERNATE_IDLE_TIMER		= 0x18,
+	REG_INTERRUPT_STATUS			= 0x20,
+	REG_INTERRUPT_ENABLE			= 0x24,
+	REG_CONTROLLER_STATUS			= 0x30,
+	REG_CONTROLLER_ENABLE			= 0x34,
+	REG_UIC_ERROR_CODE_PHY_ADAPTER_LAYER	= 0x38,
+	REG_UIC_ERROR_CODE_DATA_LINK_LAYER	= 0x3C,
+	REG_UIC_ERROR_CODE_NETWORK_LAYER	= 0x40,
+	REG_UIC_ERROR_CODE_TRANSPORT_LAYER	= 0x44,
+	REG_UIC_ERROR_CODE_DME			= 0x48,
+	REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL	= 0x4C,
+	REG_UTP_TRANSFER_REQ_LIST_BASE_L	= 0x50,
+	REG_UTP_TRANSFER_REQ_LIST_BASE_H	= 0x54,
+	REG_UTP_TRANSFER_REQ_DOOR_BELL		= 0x58,
+	REG_UTP_TRANSFER_REQ_LIST_CLEAR		= 0x5C,
+	REG_UTP_TRANSFER_REQ_LIST_RUN_STOP	= 0x60,
+	REG_UTP_TASK_REQ_LIST_BASE_L		= 0x70,
+	REG_UTP_TASK_REQ_LIST_BASE_H		= 0x74,
+	REG_UTP_TASK_REQ_DOOR_BELL		= 0x78,
+	REG_UTP_TASK_REQ_LIST_CLEAR		= 0x7C,
+	REG_UTP_TASK_REQ_LIST_RUN_STOP		= 0x80,
+	REG_UIC_COMMAND				= 0x90,
+	REG_UIC_COMMAND_ARG_1			= 0x94,
+	REG_UIC_COMMAND_ARG_2			= 0x98,
+	REG_UIC_COMMAND_ARG_3			= 0x9C,
+
+	UFSHCI_REG_SPACE_SIZE			= 0xA0,
+
+	REG_UFS_CCAP				= 0x100,
+	REG_UFS_CRYPTOCAP			= 0x104,
+
+	REG_UFS_MEM_CFG				= 0x300,
+	REG_UFS_MCQ_CFG				= 0x380,
+	REG_UFS_ESILBA				= 0x384,
+	REG_UFS_ESIUBA				= 0x388,
+	UFSHCI_CRYPTO_REG_SPACE_SIZE		= 0x400,
+};
+
+/* Controller capability masks */
+enum {
+	MASK_TRANSFER_REQUESTS_SLOTS_SDB	= 0x0000001F,
+	MASK_TRANSFER_REQUESTS_SLOTS_MCQ	= 0x000000FF,
+	MASK_NUMBER_OUTSTANDING_RTT		= 0x0000FF00,
+	MASK_TASK_MANAGEMENT_REQUEST_SLOTS	= 0x00070000,
+	MASK_EHSLUTRD_SUPPORTED			= 0x00400000,
+	MASK_AUTO_HIBERN8_SUPPORT		= 0x00800000,
+	MASK_64_ADDRESSING_SUPPORT		= 0x01000000,
+	MASK_OUT_OF_ORDER_DATA_DELIVERY_SUPPORT	= 0x02000000,
+	MASK_UIC_DME_TEST_MODE_SUPPORT		= 0x04000000,
+	MASK_CRYPTO_SUPPORT			= 0x10000000,
+	MASK_LSDB_SUPPORT			= 0x20000000,
+	MASK_MCQ_SUPPORT			= 0x40000000,
+};
+
+/* MCQ capability mask */
+enum {
+	MASK_EXT_IID_SUPPORT = 0x00000400,
+};
+
+enum {
+	REG_SQATTR		= 0x0,
+	REG_SQLBA		= 0x4,
+	REG_SQUBA		= 0x8,
+	REG_SQDAO		= 0xC,
+	REG_SQISAO		= 0x10,
+
+	REG_CQATTR		= 0x20,
+	REG_CQLBA		= 0x24,
+	REG_CQUBA		= 0x28,
+	REG_CQDAO		= 0x2C,
+	REG_CQISAO		= 0x30,
+};
+
+enum {
+	REG_SQHP		= 0x0,
+	REG_SQTP		= 0x4,
+	REG_SQRTC		= 0x8,
+	REG_SQCTI		= 0xC,
+	REG_SQRTS		= 0x10,
+};
+
+enum {
+	REG_CQHP		= 0x0,
+	REG_CQTP		= 0x4,
+};
+
+enum {
+	REG_CQIS		= 0x0,
+	REG_CQIE		= 0x4,
+};
+
+enum {
+	SQ_START		= 0x0,
+	SQ_STOP			= 0x1,
+	SQ_ICU			= 0x2,
+};
+
+enum {
+	SQ_STS			= 0x1,
+	SQ_CUS			= 0x2,
+};
+
+#define SQ_ICU_ERR_CODE_MASK		GENMASK(7, 4)
+#define UFS_MASK(mask, offset)		((mask) << (offset))
+
+/* UFS Version 08h */
+#define MINOR_VERSION_NUM_MASK		UFS_MASK(0xFFFF, 0)
+#define MAJOR_VERSION_NUM_MASK		UFS_MASK(0xFFFF, 16)
+
+/* Controller UFSHCI version */
+enum {
+	UFSHCI_VERSION_10 = 0x00010000, /* 1.0 */
+	UFSHCI_VERSION_11 = 0x00010100, /* 1.1 */
+	UFSHCI_VERSION_20 = 0x00000200, /* 2.0 */
+	UFSHCI_VERSION_21 = 0x00000210, /* 2.1 */
+	UFSHCI_VERSION_30 = 0x00000300, /* 3.0 */
+	UFSHCI_VERSION_31 = 0x00000310, /* 3.1 */
+	UFSHCI_VERSION_40 = 0x00000400, /* 4.0 */
+};
+
+/*
+ * IS - Interrupt Status - 20h
+ */
+#define UTP_TRANSFER_REQ_COMPL			0x1
+#define UIC_DME_END_PT_RESET			0x2
+#define UIC_ERROR				0x4
+#define UIC_TEST_MODE				0x8
+#define UIC_POWER_MODE				0x10
+#define UIC_HIBERNATE_EXIT			0x20
+#define UIC_HIBERNATE_ENTER			0x40
+#define UIC_LINK_LOST				0x80
+#define UIC_LINK_STARTUP			0x100
+#define UTP_TASK_REQ_COMPL			0x200
+#define UIC_COMMAND_COMPL			0x400
+#define DEVICE_FATAL_ERROR			0x800
+#define CONTROLLER_FATAL_ERROR			0x10000
+#define SYSTEM_BUS_FATAL_ERROR			0x20000
+#define CRYPTO_ENGINE_FATAL_ERROR		0x40000
+#define MCQ_CQ_EVENT_STATUS			0x100000
+
+#define UFSHCD_UIC_HIBERN8_MASK	(UIC_HIBERNATE_ENTER |\
+				UIC_HIBERNATE_EXIT)
+
+#define UFSHCD_UIC_PWR_MASK	(UFSHCD_UIC_HIBERN8_MASK |\
+				UIC_POWER_MODE)
+
+#define UFSHCD_UIC_MASK		(UIC_COMMAND_COMPL | UFSHCD_UIC_PWR_MASK)
+
+#define UFSHCD_ERROR_MASK	(UIC_ERROR | INT_FATAL_ERRORS)
+
+#define INT_FATAL_ERRORS	(DEVICE_FATAL_ERROR |\
+				CONTROLLER_FATAL_ERROR |\
+				SYSTEM_BUS_FATAL_ERROR |\
+				CRYPTO_ENGINE_FATAL_ERROR |\
+				UIC_LINK_LOST)
+
+/* HCS - Host Controller Status 30h */
+#define DEVICE_PRESENT				0x1
+#define UTP_TRANSFER_REQ_LIST_READY		0x2
+#define UTP_TASK_REQ_LIST_READY			0x4
+#define UIC_COMMAND_READY			0x8
+#define HOST_ERROR_INDICATOR			0x10
+#define DEVICE_ERROR_INDICATOR			0x20
+#define UIC_POWER_MODE_CHANGE_REQ_STATUS_MASK	UFS_MASK(0x7, 8)
+
+#define UFSHCD_STATUS_READY	(UTP_TRANSFER_REQ_LIST_READY |\
+				UTP_TASK_REQ_LIST_READY |\
+				UIC_COMMAND_READY)
+
+enum {
+	PWR_OK		= 0x0,
+	PWR_LOCAL	= 0x01,
+	PWR_REMOTE	= 0x02,
+	PWR_BUSY	= 0x03,
+	PWR_ERROR_CAP	= 0x04,
+	PWR_FATAL_ERROR	= 0x05,
+};
+
+/* HCE - Host Controller Enable 34h */
+#define CONTROLLER_ENABLE	0x1
+#define CONTROLLER_DISABLE	0x0
+#define CRYPTO_GENERAL_ENABLE	0x2
+
+/* UECPA - Host UIC Error Code PHY Adapter Layer 38h */
+#define UIC_PHY_ADAPTER_LAYER_ERROR			0x80000000
+#define UIC_PHY_ADAPTER_LAYER_ERROR_CODE_MASK		0x1F
+#define UIC_PHY_ADAPTER_LAYER_LANE_ERR_MASK		0xF
+#define UIC_PHY_ADAPTER_LAYER_GENERIC_ERROR		0x10
+
+/* UECDL - Host UIC Error Code Data Link Layer 3Ch */
+#define UIC_DATA_LINK_LAYER_ERROR		0x80000000
+#define UIC_DATA_LINK_LAYER_ERROR_CODE_MASK	0xFFFF
+#define UIC_DATA_LINK_LAYER_ERROR_TCX_REP_TIMER_EXP	0x2
+#define UIC_DATA_LINK_LAYER_ERROR_AFCX_REQ_TIMER_EXP	0x4
+#define UIC_DATA_LINK_LAYER_ERROR_FCX_PRO_TIMER_EXP	0x8
+#define UIC_DATA_LINK_LAYER_ERROR_RX_BUF_OF	0x20
+#define UIC_DATA_LINK_LAYER_ERROR_PA_INIT	0x2000
+#define UIC_DATA_LINK_LAYER_ERROR_NAC_RECEIVED	0x0001
+#define UIC_DATA_LINK_LAYER_ERROR_TCx_REPLAY_TIMEOUT 0x0002
+
+/* UECN - Host UIC Error Code Network Layer 40h */
+#define UIC_NETWORK_LAYER_ERROR			0x80000000
+#define UIC_NETWORK_LAYER_ERROR_CODE_MASK	0x7
+#define UIC_NETWORK_UNSUPPORTED_HEADER_TYPE	0x1
+#define UIC_NETWORK_BAD_DEVICEID_ENC		0x2
+#define UIC_NETWORK_LHDR_TRAP_PACKET_DROPPING	0x4
+
+/* UECT - Host UIC Error Code Transport Layer 44h */
+#define UIC_TRANSPORT_LAYER_ERROR		0x80000000
+#define UIC_TRANSPORT_LAYER_ERROR_CODE_MASK	0x7F
+#define UIC_TRANSPORT_UNSUPPORTED_HEADER_TYPE	0x1
+#define UIC_TRANSPORT_UNKNOWN_CPORTID		0x2
+#define UIC_TRANSPORT_NO_CONNECTION_RX		0x4
+#define UIC_TRANSPORT_CONTROLLED_SEGMENT_DROPPING	0x8
+#define UIC_TRANSPORT_BAD_TC			0x10
+#define UIC_TRANSPORT_E2E_CREDIT_OVERFOW	0x20
+#define UIC_TRANSPORT_SAFETY_VALUE_DROPPING	0x40
+
+/* UECDME - Host UIC Error Code DME 48h */
+#define UIC_DME_ERROR			0x80000000
+#define UIC_DME_ERROR_CODE_MASK		0x1
+
+/* UTRIACR - Interrupt Aggregation control register - 0x4Ch */
+#define INT_AGGR_TIMEOUT_VAL_MASK		0xFF
+#define INT_AGGR_COUNTER_THRESHOLD_MASK		UFS_MASK(0x1F, 8)
+#define INT_AGGR_COUNTER_AND_TIMER_RESET	0x10000
+#define INT_AGGR_STATUS_BIT			0x100000
+#define INT_AGGR_PARAM_WRITE			0x1000000
+#define INT_AGGR_ENABLE				0x80000000
+
+/* UTRLRSR - UTP Transfer Request Run-Stop Register 60h */
+#define UTP_TRANSFER_REQ_LIST_RUN_STOP_BIT	0x1
+
+/* UTMRLRSR - UTP Task Management Request Run-Stop Register 80h */
+#define UTP_TASK_REQ_LIST_RUN_STOP_BIT		0x1
+
+/* REG_UFS_MEM_CFG - Global Config Registers 300h */
+#define MCQ_MODE_SELECT	BIT(0)
+
+/* CQISy - CQ y Interrupt Status Register  */
+#define UFSHCD_MCQ_CQIS_TAIL_ENT_PUSH_STS	0x1
+
+/* UICCMD - UIC Command */
+#define COMMAND_OPCODE_MASK		0xFF
+#define GEN_SELECTOR_INDEX_MASK		0xFFFF
+
+#define MIB_ATTRIBUTE_MASK		UFS_MASK(0xFFFF, 16)
+#define RESET_LEVEL			0xFF
+
+#define ATTR_SET_TYPE_MASK		UFS_MASK(0xFF, 16)
+#define CFG_RESULT_CODE_MASK		0xFF
+#define GENERIC_ERROR_CODE_MASK		0xFF
+
+/* GenSelectorIndex calculation macros for M-PHY attributes */
+#define UIC_ARG_MPHY_TX_GEN_SEL_INDEX(lane) (lane)
+#define UIC_ARG_MPHY_RX_GEN_SEL_INDEX(lane) (PA_MAXDATALANES + (lane))
+
+#define UIC_ARG_MIB_SEL(attr, sel)	((((attr) & 0xFFFF) << 16) |\
+					 ((sel) & 0xFFFF))
+#define UIC_ARG_MIB(attr)		UIC_ARG_MIB_SEL(attr, 0)
+#define UIC_ARG_ATTR_TYPE(t)		(((t) & 0xFF) << 16)
+#define UIC_GET_ATTR_ID(v)		(((v) >> 16) & 0xFFFF)
+
+/* Link Status*/
+enum link_status {
+	UFSHCD_LINK_IS_DOWN	= 1,
+	UFSHCD_LINK_IS_UP	= 2,
+};
+
+/* UIC Commands */
+enum uic_cmd_dme {
+	UIC_CMD_DME_GET			= 0x01,
+	UIC_CMD_DME_SET			= 0x02,
+	UIC_CMD_DME_PEER_GET		= 0x03,
+	UIC_CMD_DME_PEER_SET		= 0x04,
+	UIC_CMD_DME_POWERON		= 0x10,
+	UIC_CMD_DME_POWEROFF		= 0x11,
+	UIC_CMD_DME_ENABLE		= 0x12,
+	UIC_CMD_DME_RESET		= 0x14,
+	UIC_CMD_DME_END_PT_RST		= 0x15,
+	UIC_CMD_DME_LINK_STARTUP	= 0x16,
+	UIC_CMD_DME_HIBER_ENTER		= 0x17,
+	UIC_CMD_DME_HIBER_EXIT		= 0x18,
+	UIC_CMD_DME_TEST_MODE		= 0x1A,
+};
+
+/* UIC Config result code / Generic error code */
+enum {
+	UIC_CMD_RESULT_SUCCESS			= 0x00,
+	UIC_CMD_RESULT_INVALID_ATTR		= 0x01,
+	UIC_CMD_RESULT_FAILURE			= 0x01,
+	UIC_CMD_RESULT_INVALID_ATTR_VALUE	= 0x02,
+	UIC_CMD_RESULT_READ_ONLY_ATTR		= 0x03,
+	UIC_CMD_RESULT_WRITE_ONLY_ATTR		= 0x04,
+	UIC_CMD_RESULT_BAD_INDEX		= 0x05,
+	UIC_CMD_RESULT_LOCKED_ATTR		= 0x06,
+	UIC_CMD_RESULT_BAD_TEST_FEATURE_INDEX	= 0x07,
+	UIC_CMD_RESULT_PEER_COMM_FAILURE	= 0x08,
+	UIC_CMD_RESULT_BUSY			= 0x09,
+	UIC_CMD_RESULT_DME_FAILURE		= 0x0A,
+};
+
+#define MASK_UIC_COMMAND_RESULT			0xFF
+
+#define INT_AGGR_COUNTER_THLD_VAL(c)	(((c) & 0x1F) << 8)
+#define INT_AGGR_TIMEOUT_VAL(t)		(((t) & 0xFF) << 0)
+
+/*
+ * Request Descriptor Definitions
+ */
+
+/* To accommodate UFS2.0 required Command type */
+enum {
+	UTP_CMD_TYPE_UFS_STORAGE	= 0x1,
+};
+
+enum {
+	UTP_SCSI_COMMAND		= 0x00000000,
+	UTP_REQ_DESC_INT_CMD            = 0x01000000,
+	UTP_NATIVE_UFS_COMMAND		= 0x10000000,
+	UTP_DEVICE_MANAGEMENT_FUNCTION	= 0x20000000,
+};
+
+/* UTP Transfer Request Data Direction (DD) */
+enum utp_data_direction {
+	UTP_NO_DATA_TRANSFER	= 0,
+	UTP_HOST_TO_DEVICE	= 1,
+	UTP_DEVICE_TO_HOST	= 2,
+};
+
+/* Overall command status values */
+enum utp_ocs {
+	OCS_SUCCESS			= 0x0,
+	OCS_INVALID_CMD_TABLE_ATTR	= 0x1,
+	OCS_INVALID_PRDT_ATTR		= 0x2,
+	OCS_MISMATCH_DATA_BUF_SIZE	= 0x3,
+	OCS_MISMATCH_RESP_UPIU_SIZE	= 0x4,
+	OCS_PEER_COMM_FAILURE		= 0x5,
+	OCS_ABORTED			= 0x6,
+	OCS_FATAL_ERROR			= 0x7,
+	OCS_DEVICE_FATAL_ERROR		= 0x8,
+	OCS_INVALID_CRYPTO_CONFIG	= 0x9,
+	OCS_GENERAL_CRYPTO_ERROR	= 0xA,
+	OCS_INVALID_COMMAND_STATUS	= 0x0F,
+};
+
+enum {
+	MASK_OCS			= 0x0F,
+};
+
+/* The maximum length of the data byte count field in the PRDT is 256KB */
+#define PRDT_DATA_BYTE_COUNT_MAX	SZ_256K
+/* The granularity of the data byte count field in the PRDT is 32-bit */
+#define PRDT_DATA_BYTE_COUNT_PAD	4
+
+
+struct ufshcd_sg_entry {
+	__le32    base_addr;
+	__le32    upper_addr;
+	__le32    reserved;
+	__le32    size;
+};
+
+#define MAX_BUFF	128
+/**
+ * struct utp_transfer_cmd_desc - UFS Command Descriptor structure
+ * @command_upiu: Command UPIU Frame address
+ * @response_upiu: Response UPIU Frame address
+ * @prd_table: Physical Region Descriptor
+ */
+struct utp_transfer_cmd_desc {
+	u8 command_upiu[ALIGNED_UPIU_SIZE];
+	u8 response_upiu[ALIGNED_UPIU_SIZE];
+	struct ufshcd_sg_entry    prd_table[MAX_BUFF];
+};
+
+/**
+ * struct request_desc_header - Descriptor Header common to both UTRD and UTMRD
+ * @dword0: Descriptor Header DW0
+ * @dword1: Descriptor Header DW1
+ * @dword2: Descriptor Header DW2
+ * @dword3: Descriptor Header DW3
+ */
+struct request_desc_header {
+	__le32 dword_0;
+	__le32 dword_1;
+	__le32 dword_2;
+	__le32 dword_3;
+};
+
+/**
+ * struct utp_transfer_req_desc - UTRD structure
+ * @header: UTRD header DW-0 to DW-3
+ * @command_desc_base_addr_lo: UCD base address low DW-4
+ * @command_desc_base_addr_hi: UCD base address high DW-5
+ * @response_upiu_length: response UPIU length DW-6
+ * @response_upiu_offset: response UPIU offset DW-6
+ * @prd_table_length: Physical region descriptor length DW-7
+ * @prd_table_offset: Physical region descriptor offset DW-7
+ */
+struct utp_transfer_req_desc {
+	/* DW 0-3 */
+	struct request_desc_header header;
+
+	/* DW 4-5*/
+	__le32  command_desc_base_addr_lo;
+	__le32  command_desc_base_addr_hi;
+
+	/* DW 6 */
+	__le16  response_upiu_length;
+	__le16  response_upiu_offset;
+
+	/* DW 7 */
+	__le16  prd_table_length;
+	__le16  prd_table_offset;
+};
+
+/**
+ * struct utp_upiu_header - UPIU header structure
+ * @dword_0: UPIU header DW-0
+ * @dword_1: UPIU header DW-1
+ * @dword_2: UPIU header DW-2
+ */
+struct utp_upiu_header {
+	__be32 dword_0;
+	__be32 dword_1;
+	__be32 dword_2;
+};
+
+/*
+ * UTMRD structure.
+ */
+struct utp_task_req_desc {
+	/* DW 0-3 */
+	struct request_desc_header header;
+
+	/* DW 4-11 - Task request UPIU structure */
+	struct utp_upiu_header	req_header;
+	__be32			input_param1;
+	__be32			input_param2;
+	__be32			input_param3;
+	__be32			__reserved1[2];
+
+	/* DW 12-19 - Task Management Response UPIU structure */
+	struct utp_upiu_header	rsp_header;
+	__be32			output_param1;
+	__be32			output_param2;
+	__be32			__reserved2[3];
+};
+
+#endif
diff --git a/drivers/ufs/unipro.h b/drivers/ufs/unipro.h
index 6df953e6e60..56833602b77 100644
--- a/drivers/ufs/unipro.h
+++ b/drivers/ufs/unipro.h
@@ -34,6 +34,18 @@
 /*
  * M-RX Configuration Attributes
  */
+#define RX_HS_G1_SYNC_LENGTH_CAP		0x008B
+#define RX_HS_G1_PREP_LENGTH_CAP		0x008C
+#define RX_MIN_ACTIVATETIME_CAPABILITY		0x008F
+#define RX_HIBERN8TIME_CAPABILITY		0x0092
+#define RX_HS_G2_SYNC_LENGTH_CAP		0x0094
+#define RX_HS_G3_SYNC_LENGTH_CAP		0x0095
+#define RX_HS_G2_PREP_LENGTH_CAP		0x0096
+#define RX_HS_G3_PREP_LENGTH_CAP		0x0097
+#define RX_ADV_GRANULARITY_CAP			0x0098
+#define RX_HIBERN8TIME_CAP			0x0092
+#define RX_ADV_HIBERN8TIME_CAP			0x0099
+#define RX_ADV_MIN_ACTIVATETIME_CAP		0x009A
 #define RX_MODE					0x00A1
 #define RX_HSRATE_SERIES			0x00A2
 #define RX_HSGEAR				0x00A3
@@ -42,24 +54,27 @@
 #define RX_HS_UNTERMINATED_ENABLE		0x00A6
 #define RX_ENTER_HIBERN8			0x00A7
 #define RX_BYPASS_8B10B_ENABLE			0x00A8
-#define RX_TERMINATION_FORCE_ENABLE		0x0089
-#define RX_MIN_ACTIVATETIME_CAPABILITY		0x008F
-#define RX_HIBERN8TIME_CAPABILITY		0x0092
+#define RX_TERMINATION_FORCE_ENABLE		0x00A9
+#define RXCALCTRL				0x00B4
+#define RXSQCTRL				0x00B5
+#define CFGRXCDR8				0x00BA
+#define CFGRXOVR8				0x00BD
+#define CFGRXOVR6				0x00BF
+#define RXDIRECTCTRL2				0x00C7
+#define CFGRXOVR4				0x00E9
 #define RX_REFCLKFREQ				0x00EB
 #define	RX_CFGCLKFREQVAL			0x00EC
 #define CFGWIDEINLN				0x00F0
-#define CFGRXCDR8				0x00BA
 #define ENARXDIRECTCFG4				0x00F2
-#define CFGRXOVR8				0x00BD
-#define RXDIRECTCTRL2				0x00C7
 #define ENARXDIRECTCFG3				0x00F3
-#define RXCALCTRL				0x00B4
 #define ENARXDIRECTCFG2				0x00F4
-#define CFGRXOVR4				0x00E9
-#define RXSQCTRL				0x00B5
-#define CFGRXOVR6				0x00BF
 
-#define is_mphy_tx_attr(attr)			(attr < RX_MODE)
+#define is_mphy_tx_attr(attr)			((attr) < RX_MODE)
+#define RX_ADV_FINE_GRAN_STEP(x)		((((x) & 0x3) << 1) | 0x1)
+#define SYNC_LEN_FINE(x)			((x) & 0x3F)
+#define SYNC_LEN_COARSE(x)			((1 << 6) | ((x) & 0x3F))
+#define PREP_LEN(x)				((x) & 0xF)
+
 #define RX_MIN_ACTIVATETIME_UNIT_US		100
 #define HIBERN8TIME_UNIT_US			100
 
@@ -77,51 +92,54 @@
 #define CBPRGPLL2				UNIPRO_CB_OFFSET(0x00F8)
 #define CBPRGTUNING				UNIPRO_CB_OFFSET(0x00FB)
 
-#define UNIPRO_CB_OFFSET(x)			(0x8000 | x)
+#define UNIPRO_CB_OFFSET(x)			(0x8000 | (x))
 
 /*
- * PHY Adpater attributes
+ * PHY Adapter attributes
  */
-#define PA_ACTIVETXDATALANES	0x1560
-#define PA_ACTIVERXDATALANES	0x1580
-#define PA_TXTRAILINGCLOCKS	0x1564
 #define PA_PHY_TYPE		0x1500
 #define PA_AVAILTXDATALANES	0x1520
-#define PA_AVAILRXDATALANES	0x1540
-#define PA_MINRXTRAILINGCLOCKS	0x1543
-#define PA_TXPWRSTATUS		0x1567
-#define PA_RXPWRSTATUS		0x1582
-#define PA_TXFORCECLOCK		0x1562
-#define PA_TXPWRMODE		0x1563
-#define PA_LEGACYDPHYESCDL	0x1570
 #define PA_MAXTXSPEEDFAST	0x1521
 #define PA_MAXTXSPEEDSLOW	0x1522
 #define PA_MAXRXSPEEDFAST	0x1541
 #define PA_MAXRXSPEEDSLOW	0x1542
 #define PA_TXLINKSTARTUPHS	0x1544
+#define PA_AVAILRXDATALANES	0x1540
+#define PA_MINRXTRAILINGCLOCKS	0x1543
 #define PA_LOCAL_TX_LCC_ENABLE	0x155E
+#define PA_ACTIVETXDATALANES	0x1560
+#define PA_CONNECTEDTXDATALANES	0x1561
+#define PA_TXFORCECLOCK		0x1562
+#define PA_TXPWRMODE		0x1563
+#define PA_TXTRAILINGCLOCKS	0x1564
 #define PA_TXSPEEDFAST		0x1565
 #define PA_TXSPEEDSLOW		0x1566
-#define PA_REMOTEVERINFO	0x15A0
+#define PA_TXPWRSTATUS		0x1567
 #define PA_TXGEAR		0x1568
 #define PA_TXTERMINATION	0x1569
 #define PA_HSSERIES		0x156A
+#define PA_LEGACYDPHYESCDL	0x1570
 #define PA_PWRMODE		0x1571
+#define PA_ACTIVERXDATALANES	0x1580
+#define PA_CONNECTEDRXDATALANES	0x1581
+#define PA_RXPWRSTATUS		0x1582
 #define PA_RXGEAR		0x1583
 #define PA_RXTERMINATION	0x1584
 #define PA_MAXRXPWMGEAR		0x1586
 #define PA_MAXRXHSGEAR		0x1587
-#define PA_RXHSUNTERMCAP	0x15A5
-#define PA_RXLSTERMCAP		0x15A6
-#define PA_GRANULARITY		0x15AA
 #define PA_PACPREQTIMEOUT	0x1590
 #define PA_PACPREQEOBTIMEOUT	0x1591
+#define PA_REMOTEVERINFO	0x15A0
+#define PA_LOGICALLANEMAP	0x15A1
+#define PA_SLEEPNOCONFIGTIME	0x15A2
+#define PA_STALLNOCONFIGTIME	0x15A3
+#define PA_SAVECONFIGTIME	0x15A4
+#define PA_RXHSUNTERMCAP	0x15A5
+#define PA_RXLSTERMCAP		0x15A6
 #define PA_HIBERN8TIME		0x15A7
 #define PA_LOCALVERINFO		0x15A9
+#define PA_GRANULARITY		0x15AA
 #define PA_TACTIVATE		0x15A8
-#define PA_PACPFRAMECOUNT	0x15C0
-#define PA_PACPERRORCOUNT	0x15C1
-#define PA_PHYTESTCONTROL	0x15C2
 #define PA_PWRMODEUSERDATA0	0x15B0
 #define PA_PWRMODEUSERDATA1	0x15B1
 #define PA_PWRMODEUSERDATA2	0x15B2
@@ -134,12 +152,9 @@
 #define PA_PWRMODEUSERDATA9	0x15B9
 #define PA_PWRMODEUSERDATA10	0x15BA
 #define PA_PWRMODEUSERDATA11	0x15BB
-#define PA_CONNECTEDTXDATALANES	0x1561
-#define PA_CONNECTEDRXDATALANES	0x1581
-#define PA_LOGICALLANEMAP	0x15A1
-#define PA_SLEEPNOCONFIGTIME	0x15A2
-#define PA_STALLNOCONFIGTIME	0x15A3
-#define PA_SAVECONFIGTIME	0x15A4
+#define PA_PACPFRAMECOUNT	0x15C0
+#define PA_PACPERRORCOUNT	0x15C1
+#define PA_PHYTESTCONTROL	0x15C2
 #define PA_TXHSADAPTTYPE	0x15D4
 
 /* Adapt type for PA_TXHSADAPTTYPE attribute */
@@ -151,9 +166,9 @@
 #define PA_HIBERN8_TIME_UNIT_US		100
 
 /*Other attributes*/
+#define VS_POWERSTATE		0xD083
 #define VS_MPHYCFGUPDT		0xD085
 #define VS_DEBUGOMC		0xD09E
-#define VS_POWERSTATE		0xD083
 #define VS_MPHYDISABLE		0xD0C1
 
 #define PA_GRANULARITY_MIN_VAL	1
@@ -163,7 +178,7 @@
 #define PA_MAXDATALANES	4
 
 /* PA power modes */
-enum {
+enum ufs_pa_pwr_mode {
 	FAST_MODE	= 1,
 	SLOW_MODE	= 2,
 	FASTAUTO_MODE	= 4,
@@ -171,8 +186,11 @@ enum {
 	UNCHANGED	= 7,
 };
 
+#define PWRMODE_MASK		0xF
+#define PWRMODE_RX_OFFSET	4
+
 /* PA TX/RX Frequency Series */
-enum {
+enum ufs_hs_gear_rate {
 	PA_HS_MODE_A	= 1,
 	PA_HS_MODE_B	= 2,
 };
@@ -193,14 +211,24 @@ enum ufs_hs_gear_tag {
 	UFS_HS_G1,		/* HS Gear 1 (default for reset) */
 	UFS_HS_G2,		/* HS Gear 2 */
 	UFS_HS_G3,		/* HS Gear 3 */
+	UFS_HS_G4,		/* HS Gear 4 */
+	UFS_HS_G5		/* HS Gear 5 */
+};
+
+enum ufs_lanes {
+	UFS_LANE_DONT_CHANGE,	/* Don't change Lane */
+	UFS_LANE_1,		/* Lane 1 (default for reset) */
+	UFS_LANE_2,		/* Lane 2 */
 };
 
 enum ufs_unipro_ver {
 	UFS_UNIPRO_VER_RESERVED = 0,
 	UFS_UNIPRO_VER_1_40 = 1, /* UniPro version 1.40 */
 	UFS_UNIPRO_VER_1_41 = 2, /* UniPro version 1.41 */
-	UFS_UNIPRO_VER_1_6 = 3,  /* UniPro version 1.6 */
-	UFS_UNIPRO_VER_MAX = 4,  /* UniPro unsupported version */
+	UFS_UNIPRO_VER_1_6  = 3, /* UniPro version 1.6 */
+	UFS_UNIPRO_VER_1_61 = 4, /* UniPro version 1.61 */
+	UFS_UNIPRO_VER_1_8  = 5, /* UniPro version 1.8 */
+	UFS_UNIPRO_VER_MAX  = 6, /* UniPro unsupported version */
 	/* UniPro version field mask in PA_LOCALVERINFO */
 	UFS_UNIPRO_VER_MASK = 0xF,
 };
@@ -208,27 +236,27 @@ enum ufs_unipro_ver {
 /*
  * Data Link Layer Attributes
  */
+#define DL_TXPREEMPTIONCAP	0x2000
+#define DL_TC0TXMAXSDUSIZE	0x2001
+#define DL_TC0RXINITCREDITVAL	0x2002
+#define DL_TC1TXMAXSDUSIZE	0x2003
+#define DL_TC1RXINITCREDITVAL	0x2004
+#define DL_TC0TXBUFFERSIZE	0x2005
+#define DL_TC1TXBUFFERSIZE	0x2006
 #define DL_TC0TXFCTHRESHOLD	0x2040
 #define DL_FC0PROTTIMEOUTVAL	0x2041
 #define DL_TC0REPLAYTIMEOUTVAL	0x2042
 #define DL_AFC0REQTIMEOUTVAL	0x2043
 #define DL_AFC0CREDITTHRESHOLD	0x2044
 #define DL_TC0OUTACKTHRESHOLD	0x2045
+#define DL_PEERTC0PRESENT	0x2046
+#define DL_PEERTC0RXINITCREVAL	0x2047
 #define DL_TC1TXFCTHRESHOLD	0x2060
 #define DL_FC1PROTTIMEOUTVAL	0x2061
 #define DL_TC1REPLAYTIMEOUTVAL	0x2062
 #define DL_AFC1REQTIMEOUTVAL	0x2063
 #define DL_AFC1CREDITTHRESHOLD	0x2064
 #define DL_TC1OUTACKTHRESHOLD	0x2065
-#define DL_TXPREEMPTIONCAP	0x2000
-#define DL_TC0TXMAXSDUSIZE	0x2001
-#define DL_TC0RXINITCREDITVAL	0x2002
-#define DL_TC0TXBUFFERSIZE	0x2005
-#define DL_PEERTC0PRESENT	0x2046
-#define DL_PEERTC0RXINITCREVAL	0x2047
-#define DL_TC1TXMAXSDUSIZE	0x2003
-#define DL_TC1RXINITCREDITVAL	0x2004
-#define DL_TC1TXBUFFERSIZE	0x2006
 #define DL_PEERTC1PRESENT	0x2066
 #define DL_PEERTC1RXINITCREVAL	0x2067
 
diff --git a/drivers/usb/cdns3/Kconfig b/drivers/usb/cdns3/Kconfig
index 35b61497d9c..1d5e4afac6c 100644
--- a/drivers/usb/cdns3/Kconfig
+++ b/drivers/usb/cdns3/Kconfig
@@ -49,6 +49,13 @@ config SPL_USB_CDNS3_HOST
 	  Host controller is compliant with XHCI so it will use
 	  standard XHCI driver.
 
+config USB_CDNS3_STARFIVE
+	tristate "Cadence USB3 support on Starfive platforms"
+	default y if STARFIVE_JH7110
+	help
+	  Say 'Y' here if you are building for Starfive platforms
+	  that contain Cadence USB3 controller core. E.g.: JH7110.
+
 config USB_CDNS3_TI
 	tristate "Cadence USB3 support on TI platforms"
 	default USB_CDNS3
diff --git a/drivers/usb/cdns3/Makefile b/drivers/usb/cdns3/Makefile
index d6047856091..1f00f23f704 100644
--- a/drivers/usb/cdns3/Makefile
+++ b/drivers/usb/cdns3/Makefile
@@ -8,4 +8,5 @@ cdns3-$(CONFIG_$(XPL_)USB_CDNS3_GADGET)	+= gadget.o ep0.o
 
 cdns3-$(CONFIG_$(XPL_)USB_CDNS3_HOST)	+= host.o
 
+obj-$(CONFIG_USB_CDNS3_STARFIVE)	+= cdns3-starfive.o
 obj-$(CONFIG_USB_CDNS3_TI)		+= cdns3-ti.o
diff --git a/drivers/usb/cdns3/cdns3-starfive.c b/drivers/usb/cdns3/cdns3-starfive.c
new file mode 100644
index 00000000000..78ceb831b19
--- /dev/null
+++ b/drivers/usb/cdns3/cdns3-starfive.c
@@ -0,0 +1,182 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * cdns3-starfive.c - StarFive specific Glue layer for Cadence USB Controller
+ *
+ * Copyright (C) 2024 StarFive Technology Co., Ltd.
+ *
+ * Author:	Minda Chen <minda.chen@starfivetech.com>
+ */
+
+#include <asm/io.h>
+#include <clk.h>
+#include <dm.h>
+#include <dm/device_compat.h>
+#include <linux/bitops.h>
+#include <linux/usb/otg.h>
+#include <malloc.h>
+#include <reset.h>
+#include <regmap.h>
+#include <syscon.h>
+
+#include "core.h"
+
+#define USB_STRAP_HOST			BIT(17)
+#define USB_STRAP_DEVICE		BIT(18)
+#define USB_STRAP_MASK			GENMASK(18, 16)
+
+#define USB_SUSPENDM_HOST		BIT(19)
+#define USB_SUSPENDM_MASK		BIT(19)
+
+#define USB_MISC_CFG_MASK		GENMASK(23, 20)
+#define USB_SUSPENDM_BYPS		BIT(20)
+#define USB_PLL_EN			BIT(22)
+#define USB_REFCLK_MODE			BIT(23)
+
+struct cdns_starfive {
+	struct udevice *dev;
+	struct regmap *stg_syscon;
+	struct reset_ctl_bulk resets;
+	struct clk_bulk clks;
+	u32 stg_usb_mode;
+	enum usb_dr_mode mode;
+};
+
+static void cdns_mode_init(struct cdns_starfive *data, enum usb_dr_mode mode)
+{
+	unsigned int strap, suspendm;
+
+	regmap_update_bits(data->stg_syscon, data->stg_usb_mode,
+			   USB_MISC_CFG_MASK,
+			   USB_SUSPENDM_BYPS | USB_PLL_EN | USB_REFCLK_MODE);
+
+	switch (mode) {
+	case USB_DR_MODE_HOST:
+		strap = USB_STRAP_HOST;
+		suspendm = USB_SUSPENDM_HOST;
+		break;
+	case USB_DR_MODE_PERIPHERAL:
+		strap = USB_STRAP_DEVICE;
+		suspendm = 0;
+		break;
+	default:
+		return;
+	}
+
+	regmap_update_bits(data->stg_syscon, data->stg_usb_mode,
+			   USB_SUSPENDM_MASK | USB_STRAP_MASK,
+			   strap | suspendm);
+}
+
+static void cdns_clk_rst_deinit(struct cdns_starfive *data)
+{
+	reset_assert_bulk(&data->resets);
+	clk_disable_bulk(&data->clks);
+}
+
+static int cdns_clk_rst_init(struct cdns_starfive *data)
+{
+	int ret;
+
+	ret = clk_get_bulk(data->dev, &data->clks);
+	if (ret)
+		return ret;
+
+	ret = reset_get_bulk(data->dev, &data->resets);
+	if (ret)
+		goto err_clk;
+
+	ret = clk_enable_bulk(&data->clks);
+	if (ret) {
+		dev_err(data->dev, "clk enable failed: %d\n", ret);
+		goto err_en_clk;
+	}
+
+	ret = reset_deassert_bulk(&data->resets);
+	if (ret) {
+		dev_err(data->dev, "reset deassert failed: %d\n", ret);
+		goto err_reset;
+	}
+
+	return 0;
+
+err_reset:
+	clk_disable_bulk(&data->clks);
+err_en_clk:
+	reset_release_bulk(&data->resets);
+err_clk:
+	clk_release_bulk(&data->clks);
+
+	return ret;
+}
+
+static int cdns_starfive_get_syscon(struct cdns_starfive *data)
+{
+	struct ofnode_phandle_args phandle;
+	int ret;
+
+	ret = dev_read_phandle_with_args(data->dev, "starfive,stg-syscon", NULL, 1, 0,
+					 &phandle);
+	if (ret < 0) {
+		dev_err(data->dev, "Can't get stg cfg phandle: %d\n", ret);
+		return ret;
+	}
+
+	data->stg_syscon = syscon_node_to_regmap(phandle.node);
+	if (IS_ERR(data->stg_syscon)) {
+		dev_err(data->dev, "fail to get regmap: %d\n", (int)PTR_ERR(data->stg_syscon));
+		return PTR_ERR(data->stg_syscon);
+	}
+
+	data->stg_usb_mode = phandle.args[0];
+
+	return 0;
+}
+
+static int cdns_starfive_probe(struct udevice *dev)
+{
+	struct cdns_starfive *data = dev_get_plat(dev);
+	enum usb_dr_mode dr_mode;
+	int ret;
+
+	data->dev = dev;
+
+	ret = cdns_starfive_get_syscon(data);
+	if (ret)
+		return ret;
+
+	dr_mode = usb_get_dr_mode(dev_ofnode(dev));
+
+	data->mode = dr_mode;
+	ret = cdns_clk_rst_init(data);
+	if (ret) {
+		dev_err(data->dev, "clk reset failed: %d\n", ret);
+		return ret;
+	}
+	cdns_mode_init(data, dr_mode);
+
+	return 0;
+}
+
+static int cdns_starfive_remove(struct udevice *dev)
+{
+	struct cdns_starfive *data = dev_get_plat(dev);
+
+	cdns_clk_rst_deinit(data);
+	return 0;
+}
+
+static const struct udevice_id cdns_starfive_of_match[] = {
+	{ .compatible = "starfive,jh7110-usb", },
+	{},
+};
+
+U_BOOT_DRIVER(cdns_starfive) = {
+	.name = "cdns-starfive",
+	.id = UCLASS_NOP,
+	.of_match = cdns_starfive_of_match,
+	.bind = cdns3_bind,
+	.probe = cdns_starfive_probe,
+	.remove = cdns_starfive_remove,
+	.plat_auto	= sizeof(struct cdns_starfive),
+	.flags = DM_FLAG_OS_PREPARE,
+};
diff --git a/drivers/usb/cdns3/core.c b/drivers/usb/cdns3/core.c
index 4cfd38ec245..4434dc15bec 100644
--- a/drivers/usb/cdns3/core.c
+++ b/drivers/usb/cdns3/core.c
@@ -410,6 +410,9 @@ int cdns3_bind(struct udevice *parent)
 	name = ofnode_get_name(node);
 	dr_mode = usb_get_dr_mode(node);
 
+	if (dr_mode == USB_DR_MODE_UNKNOWN)
+		dr_mode = usb_get_dr_mode(dev_ofnode(parent));
+
 	switch (dr_mode) {
 #if defined(CONFIG_SPL_USB_HOST) || \
 	(!defined(CONFIG_XPL_BUILD) && defined(CONFIG_USB_HOST))
diff --git a/drivers/usb/cdns3/drd.c b/drivers/usb/cdns3/drd.c
index 47874fec29e..cbb13342343 100644
--- a/drivers/usb/cdns3/drd.c
+++ b/drivers/usb/cdns3/drd.c
@@ -217,15 +217,19 @@ static int cdns3_init_otg_mode(struct cdns3 *cdns)
 int cdns3_drd_update_mode(struct cdns3 *cdns)
 {
 	int ret = 0;
+	int mode;
 
 	switch (cdns->dr_mode) {
 	case USB_DR_MODE_PERIPHERAL:
+		mode = PHY_MODE_USB_DEVICE;
 		ret = cdns3_set_mode(cdns, USB_DR_MODE_PERIPHERAL);
 		break;
 	case USB_DR_MODE_HOST:
+		mode = PHY_MODE_USB_HOST;
 		ret = cdns3_set_mode(cdns, USB_DR_MODE_HOST);
 		break;
 	case USB_DR_MODE_OTG:
+		mode = PHY_MODE_USB_OTG;
 		ret = cdns3_init_otg_mode(cdns);
 		break;
 	default:
@@ -234,6 +238,16 @@ int cdns3_drd_update_mode(struct cdns3 *cdns)
 		return -EINVAL;
 	}
 
+	ret = generic_phy_set_mode(&cdns->usb2_phy, mode, 0);
+	if (ret) {
+		dev_err(cdns->dev, "Set usb 2.0 PHY mode failed %d\n", ret);
+		return ret;
+	}
+
+	ret = generic_phy_set_mode(&cdns->usb3_phy, mode, 0);
+	if (ret)
+		dev_err(cdns->dev, "Set usb 3.0 PHY mode failed %d\n", ret);
+
 	return ret;
 }
 
diff --git a/drivers/usb/emul/sandbox_keyb.c b/drivers/usb/emul/sandbox_keyb.c
index db769883ba3..5ed8c2c799a 100644
--- a/drivers/usb/emul/sandbox_keyb.c
+++ b/drivers/usb/emul/sandbox_keyb.c
@@ -38,7 +38,7 @@ enum {
  *
  */
 struct sandbox_keyb_priv {
-	struct membuff in;
+	struct membuf in;
 };
 
 struct sandbox_keyb_plat {
@@ -167,7 +167,7 @@ int sandbox_usb_keyb_add_string(struct udevice *dev,
 	struct sandbox_keyb_priv *priv = dev_get_priv(dev);
 	int ret;
 
-	ret = membuff_put(&priv->in, scancode, USB_KBD_BOOT_REPORT_SIZE);
+	ret = membuf_put(&priv->in, scancode, USB_KBD_BOOT_REPORT_SIZE);
 	if (ret != USB_KBD_BOOT_REPORT_SIZE)
 		return -ENOSPC;
 
@@ -194,7 +194,7 @@ static int sandbox_keyb_interrupt(struct udevice *dev, struct usb_device *udev,
 	if (length < USB_KBD_BOOT_REPORT_SIZE)
 		return 0;
 
-	membuff_get(&priv->in, buffer, USB_KBD_BOOT_REPORT_SIZE);
+	membuf_get(&priv->in, buffer, USB_KBD_BOOT_REPORT_SIZE);
 
 	return 0;
 }
@@ -220,7 +220,7 @@ static int sandbox_keyb_probe(struct udevice *dev)
 	struct sandbox_keyb_priv *priv = dev_get_priv(dev);
 
 	/* Provide an 80 character keyboard buffer */
-	return membuff_new(&priv->in, 80 * USB_KBD_BOOT_REPORT_SIZE);
+	return membuf_new(&priv->in, 80 * USB_KBD_BOOT_REPORT_SIZE);
 }
 
 static const struct dm_usb_ops sandbox_usb_keyb_ops = {
diff --git a/drivers/usb/gadget/Makefile b/drivers/usb/gadget/Makefile
index 4bda224ff1a..db5f8895a33 100644
--- a/drivers/usb/gadget/Makefile
+++ b/drivers/usb/gadget/Makefile
@@ -35,7 +35,3 @@ endif
 endif
 
 obj-$(CONFIG_CI_UDC) += ci_udc.o
-
-# Devices not related to the new gadget layer depend on CONFIG_USB_DEVICE
-# This is really only N900 and USBTTY now.
-obj-$(CONFIG_USB_DEVICE) += core.o ep0.o
diff --git a/drivers/usb/gadget/core.c b/drivers/usb/gadget/core.c
deleted file mode 100644
index bcb1ad3082c..00000000000
--- a/drivers/usb/gadget/core.c
+++ /dev/null
@@ -1,621 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2003
- * Gerry Hamel, geh@ti.com, Texas Instruments
- *
- * Based on
- * linux/drivers/usbd/usbd.c.c - USB Device Core Layer
- *
- * Copyright (c) 2000, 2001, 2002 Lineo
- * Copyright (c) 2001 Hewlett Packard
- *
- * By:
- *	Stuart Lynne <sl@lineo.com>,
- *	Tom Rushworth <tbr@lineo.com>,
- *	Bruce Balden <balden@lineo.com>
- */
-
-#include <log.h>
-#include <malloc.h>
-#include <serial.h>
-#include <usbdevice.h>
-
-#define MAX_INTERFACES 2
-
-int maxstrings = 20;
-
-/* Global variables ************************************************************************** */
-
-struct usb_string_descriptor **usb_strings;
-
-int usb_devices;
-
-extern struct usb_function_driver ep0_driver;
-
-int registered_functions;
-int registered_devices;
-
-__maybe_unused static char *usbd_device_events[] = {
-	"DEVICE_UNKNOWN",
-	"DEVICE_INIT",
-	"DEVICE_CREATE",
-	"DEVICE_HUB_CONFIGURED",
-	"DEVICE_RESET",
-	"DEVICE_ADDRESS_ASSIGNED",
-	"DEVICE_CONFIGURED",
-	"DEVICE_SET_INTERFACE",
-	"DEVICE_SET_FEATURE",
-	"DEVICE_CLEAR_FEATURE",
-	"DEVICE_DE_CONFIGURED",
-	"DEVICE_BUS_INACTIVE",
-	"DEVICE_BUS_ACTIVITY",
-	"DEVICE_POWER_INTERRUPTION",
-	"DEVICE_HUB_RESET",
-	"DEVICE_DESTROY",
-	"DEVICE_FUNCTION_PRIVATE",
-};
-
-__maybe_unused static char *usbd_device_status[] = {
-	"USBD_OPENING",
-	"USBD_OK",
-	"USBD_SUSPENDED",
-	"USBD_CLOSING",
-};
-
-#define USBD_DEVICE_STATUS(x) (((unsigned int)x <= USBD_CLOSING) ? usbd_device_status[x] : "UNKNOWN")
-
-/* Descriptor support functions ************************************************************** */
-
-/**
- * usbd_get_string - find and return a string descriptor
- * @index: string index to return
- *
- * Find an indexed string and return a pointer to a it.
- */
-struct usb_string_descriptor *usbd_get_string (__u8 index)
-{
-	if (index >= maxstrings) {
-		return NULL;
-	}
-	return usb_strings[index];
-}
-
-/* Access to device descriptor functions ***************************************************** */
-
-/* *
- * usbd_device_configuration_instance - find a configuration instance for this device
- * @device:
- * @configuration: index to configuration, 0 - N-1
- *
- * Get specifed device configuration. Index should be bConfigurationValue-1.
- */
-static struct usb_configuration_instance *usbd_device_configuration_instance (struct usb_device_instance *device,
-		unsigned int port, unsigned int configuration)
-{
-	if (configuration >= device->configurations)
-		return NULL;
-
-	return device->configuration_instance_array + configuration;
-}
-
-/* *
- * usbd_device_interface_instance
- * @device:
- * @configuration: index to configuration, 0 - N-1
- * @interface: index to interface
- *
- * Return the specified interface descriptor for the specified device.
- */
-struct usb_interface_instance *usbd_device_interface_instance (struct usb_device_instance *device, int port, int configuration, int interface)
-{
-	struct usb_configuration_instance *configuration_instance;
-
-	if ((configuration_instance = usbd_device_configuration_instance (device, port, configuration)) == NULL) {
-		return NULL;
-	}
-	if (interface >= configuration_instance->interfaces) {
-		return NULL;
-	}
-	return configuration_instance->interface_instance_array + interface;
-}
-
-/* *
- * usbd_device_alternate_descriptor_list
- * @device:
- * @configuration: index to configuration, 0 - N-1
- * @interface: index to interface
- * @alternate: alternate setting
- *
- * Return the specified alternate descriptor for the specified device.
- */
-struct usb_alternate_instance *usbd_device_alternate_instance (struct usb_device_instance *device, int port, int configuration, int interface, int alternate)
-{
-	struct usb_interface_instance *interface_instance;
-
-	if ((interface_instance = usbd_device_interface_instance (device, port, configuration, interface)) == NULL) {
-		return NULL;
-	}
-
-	if (alternate >= interface_instance->alternates) {
-		return NULL;
-	}
-
-	return interface_instance->alternates_instance_array + alternate;
-}
-
-/* *
- * usbd_device_device_descriptor
- * @device: which device
- * @configuration: index to configuration, 0 - N-1
- * @port: which port
- *
- * Return the specified configuration descriptor for the specified device.
- */
-struct usb_device_descriptor *usbd_device_device_descriptor (struct usb_device_instance *device, int port)
-{
-	return (device->device_descriptor);
-}
-
-/**
- * usbd_device_configuration_descriptor
- * @device: which device
- * @port: which port
- * @configuration: index to configuration, 0 - N-1
- *
- * Return the specified configuration descriptor for the specified device.
- */
-struct usb_configuration_descriptor *usbd_device_configuration_descriptor (struct
-									   usb_device_instance
-									   *device, int port, int configuration)
-{
-	struct usb_configuration_instance *configuration_instance;
-	if (!(configuration_instance = usbd_device_configuration_instance (device, port, configuration))) {
-		return NULL;
-	}
-	return (configuration_instance->configuration_descriptor);
-}
-
-/**
- * usbd_device_interface_descriptor
- * @device: which device
- * @port: which port
- * @configuration: index to configuration, 0 - N-1
- * @interface: index to interface
- * @alternate: alternate setting
- *
- * Return the specified interface descriptor for the specified device.
- */
-struct usb_interface_descriptor *usbd_device_interface_descriptor (struct usb_device_instance
-								   *device, int port, int configuration, int interface, int alternate)
-{
-	struct usb_interface_instance *interface_instance;
-	if (!(interface_instance = usbd_device_interface_instance (device, port, configuration, interface))) {
-		return NULL;
-	}
-	if ((alternate < 0) || (alternate >= interface_instance->alternates)) {
-		return NULL;
-	}
-	return (interface_instance->alternates_instance_array[alternate].interface_descriptor);
-}
-
-/**
- * usbd_device_endpoint_descriptor_index
- * @device: which device
- * @port: which port
- * @configuration: index to configuration, 0 - N-1
- * @interface: index to interface
- * @alternate: index setting
- * @index: which index
- *
- * Return the specified endpoint descriptor for the specified device.
- */
-struct usb_endpoint_descriptor *usbd_device_endpoint_descriptor_index (struct usb_device_instance
-								       *device, int port, int configuration, int interface, int alternate, int index)
-{
-	struct usb_alternate_instance *alternate_instance;
-
-	if (!(alternate_instance = usbd_device_alternate_instance (device, port, configuration, interface, alternate))) {
-		return NULL;
-	}
-	if (index >= alternate_instance->endpoints) {
-		return NULL;
-	}
-	return *(alternate_instance->endpoints_descriptor_array + index);
-}
-
-/**
- * usbd_device_endpoint_transfersize
- * @device: which device
- * @port: which port
- * @configuration: index to configuration, 0 - N-1
- * @interface: index to interface
- * @index: which index
- *
- * Return the specified endpoint transfer size;
- */
-int usbd_device_endpoint_transfersize (struct usb_device_instance *device, int port, int configuration, int interface, int alternate, int index)
-{
-	struct usb_alternate_instance *alternate_instance;
-
-	if (!(alternate_instance = usbd_device_alternate_instance (device, port, configuration, interface, alternate))) {
-		return 0;
-	}
-	if (index >= alternate_instance->endpoints) {
-		return 0;
-	}
-	return *(alternate_instance->endpoint_transfersize_array + index);
-}
-
-/**
- * usbd_device_endpoint_descriptor
- * @device: which device
- * @port: which port
- * @configuration: index to configuration, 0 - N-1
- * @interface: index to interface
- * @alternate: alternate setting
- * @endpoint: which endpoint
- *
- * Return the specified endpoint descriptor for the specified device.
- */
-struct usb_endpoint_descriptor *usbd_device_endpoint_descriptor (struct usb_device_instance *device, int port, int configuration, int interface, int alternate, int endpoint)
-{
-	struct usb_endpoint_descriptor *endpoint_descriptor;
-	int i;
-
-	for (i = 0; !(endpoint_descriptor = usbd_device_endpoint_descriptor_index (device, port, configuration, interface, alternate, i)); i++) {
-		if (endpoint_descriptor->bEndpointAddress == endpoint) {
-			return endpoint_descriptor;
-		}
-	}
-	return NULL;
-}
-
-/**
- * usbd_endpoint_halted
- * @device: point to struct usb_device_instance
- * @endpoint: endpoint to check
- *
- * Return non-zero if endpoint is halted.
- */
-int usbd_endpoint_halted (struct usb_device_instance *device, int endpoint)
-{
-	return (device->status == USB_STATUS_HALT);
-}
-
-/**
- * usbd_rcv_complete - complete a receive
- * @endpoint:
- * @len:
- * @urb_bad:
- *
- * Called from rcv interrupt to complete.
- */
-void usbd_rcv_complete(struct usb_endpoint_instance *endpoint, int len, int urb_bad)
-{
-	if (endpoint) {
-		struct urb *rcv_urb;
-
-		/*usbdbg("len: %d urb: %p\n", len, endpoint->rcv_urb); */
-
-		/* if we had an urb then update actual_length, dispatch if neccessary */
-		if ((rcv_urb = endpoint->rcv_urb)) {
-
-			/*usbdbg("actual: %d buffer: %d\n", */
-			/*rcv_urb->actual_length, rcv_urb->buffer_length); */
-
-			/* check the urb is ok, are we adding data less than the packetsize */
-			if (!urb_bad && (len <= endpoint->rcv_packetSize)) {
-			  /*usbdbg("updating actual_length by %d\n",len); */
-
-				/* increment the received data size */
-				rcv_urb->actual_length += len;
-
-			} else {
-				usberr(" RECV_ERROR actual: %d buffer: %d urb_bad: %d\n",
-				       rcv_urb->actual_length, rcv_urb->buffer_length, urb_bad);
-
-				rcv_urb->actual_length = 0;
-				rcv_urb->status = RECV_ERROR;
-			}
-		} else {
-			usberr("no rcv_urb!");
-		}
-	} else {
-		usberr("no endpoint!");
-	}
-
-}
-
-/**
- * usbd_tx_complete - complete a transmit
- * @endpoint:
- * @resetart:
- *
- * Called from tx interrupt to complete.
- */
-void usbd_tx_complete (struct usb_endpoint_instance *endpoint)
-{
-	if (endpoint) {
-		struct urb *tx_urb;
-
-		/* if we have a tx_urb advance or reset, finish if complete */
-		if ((tx_urb = endpoint->tx_urb)) {
-			int sent = endpoint->last;
-			endpoint->sent += sent;
-			endpoint->last -= sent;
-
-			if( (endpoint->tx_urb->actual_length - endpoint->sent) <= 0 ) {
-				tx_urb->actual_length = 0;
-				endpoint->sent = 0;
-				endpoint->last = 0;
-
-				/* Remove from active, save for re-use */
-				urb_detach(tx_urb);
-				urb_append(&endpoint->done, tx_urb);
-				/*usbdbg("done->next %p, tx_urb %p, done %p", */
-				/*	 endpoint->done.next, tx_urb, &endpoint->done); */
-
-				endpoint->tx_urb = first_urb_detached(&endpoint->tx);
-				if( endpoint->tx_urb ) {
-					endpoint->tx_queue--;
-					usbdbg("got urb from tx list");
-				}
-				if( !endpoint->tx_urb ) {
-					/*usbdbg("taking urb from done list"); */
-					endpoint->tx_urb = first_urb_detached(&endpoint->done);
-				}
-				if( !endpoint->tx_urb ) {
-					usbdbg("allocating new urb for tx_urb");
-					endpoint->tx_urb = usbd_alloc_urb(tx_urb->device, endpoint);
-				}
-			}
-		}
-	}
-}
-
-/* URB linked list functions ***************************************************** */
-
-/*
- * Initialize an urb_link to be a single element list.
- * If the urb_link is being used as a distinguished list head
- * the list is empty when the head is the only link in the list.
- */
-void urb_link_init (urb_link * ul)
-{
-	if (ul) {
-		ul->prev = ul->next = ul;
-	}
-}
-
-/*
- * Detach an urb_link from a list, and set it
- * up as a single element list, so no dangling
- * pointers can be followed, and so it can be
- * joined to another list if so desired.
- */
-void urb_detach (struct urb *urb)
-{
-	if (urb) {
-		urb_link *ul = &urb->link;
-		ul->next->prev = ul->prev;
-		ul->prev->next = ul->next;
-		urb_link_init (ul);
-	}
-}
-
-/*
- * Return the first urb_link in a list with a distinguished
- * head "hd", or NULL if the list is empty.  This will also
- * work as a predicate, returning NULL if empty, and non-NULL
- * otherwise.
- */
-urb_link *first_urb_link (urb_link * hd)
-{
-	urb_link *nx;
-	if (NULL != hd && NULL != (nx = hd->next) && nx != hd) {
-		/* There is at least one element in the list */
-		/* (besides the distinguished head). */
-		return (nx);
-	}
-	/* The list is empty */
-	return (NULL);
-}
-
-/*
- * Return the first urb in a list with a distinguished
- * head "hd", or NULL if the list is empty.
- */
-struct urb *first_urb (urb_link * hd)
-{
-	urb_link *nx;
-	if (NULL == (nx = first_urb_link (hd))) {
-		/* The list is empty */
-		return (NULL);
-	}
-	return (p2surround (struct urb, link, nx));
-}
-
-/*
- * Detach and return the first urb in a list with a distinguished
- * head "hd", or NULL if the list is empty.
- *
- */
-struct urb *first_urb_detached (urb_link * hd)
-{
-	struct urb *urb;
-	if ((urb = first_urb (hd))) {
-		urb_detach (urb);
-	}
-	return urb;
-}
-
-/*
- * Append an urb_link (or a whole list of
- * urb_links) to the tail of another list
- * of urb_links.
- */
-void urb_append (urb_link * hd, struct urb *urb)
-{
-	if (hd && urb) {
-		urb_link *new = &urb->link;
-
-		/* This allows the new urb to be a list of urbs, */
-		/* with new pointing at the first, but the link */
-		/* must be initialized. */
-		/* Order is important here... */
-		urb_link *pul = hd->prev;
-		new->prev->next = hd;
-		hd->prev = new->prev;
-		new->prev = pul;
-		pul->next = new;
-	}
-}
-
-/* URB create/destroy functions ***************************************************** */
-
-/**
- * usbd_alloc_urb - allocate an URB appropriate for specified endpoint
- * @device: device instance
- * @endpoint: endpoint
- *
- * Allocate an urb structure. The usb device urb structure is used to
- * contain all data associated with a transfer, including a setup packet for
- * control transfers.
- *
- * NOTE: endpoint_address MUST contain a direction flag.
- */
-struct urb *usbd_alloc_urb (struct usb_device_instance *device,
-			    struct usb_endpoint_instance *endpoint)
-{
-	struct urb *urb;
-
-	if (!(urb = (struct urb *) malloc (sizeof (struct urb)))) {
-		usberr (" F A T A L:  malloc(%zu) FAILED!!!!",
-			sizeof (struct urb));
-		return NULL;
-	}
-
-	/* Fill in known fields */
-	memset (urb, 0, sizeof (struct urb));
-	urb->endpoint = endpoint;
-	urb->device = device;
-	urb->buffer = (u8 *) urb->buffer_data;
-	urb->buffer_length = sizeof (urb->buffer_data);
-
-	urb_link_init (&urb->link);
-
-	return urb;
-}
-
-/**
- * usbd_dealloc_urb - deallocate an URB and associated buffer
- * @urb: pointer to an urb structure
- *
- * Deallocate an urb structure and associated data.
- */
-void usbd_dealloc_urb (struct urb *urb)
-{
-	if (urb) {
-		free (urb);
-	}
-}
-
-/* Event signaling functions ***************************************************** */
-
-/**
- * usbd_device_event - called to respond to various usb events
- * @device: pointer to struct device
- * @event: event to respond to
- *
- * Used by a Bus driver to indicate an event.
- */
-void usbd_device_event_irq (struct usb_device_instance *device, usb_device_event_t event, int data)
-{
-	usb_device_state_t state;
-
-	if (!device || !device->bus) {
-		usberr("(%p,%d) NULL device or device->bus", device, event);
-		return;
-	}
-
-	state = device->device_state;
-
-	usbinfo("%s", usbd_device_events[event]);
-
-	switch (event) {
-	case DEVICE_UNKNOWN:
-		break;
-	case DEVICE_INIT:
-		device->device_state = STATE_INIT;
-		break;
-
-	case DEVICE_CREATE:
-		device->device_state = STATE_ATTACHED;
-		break;
-
-	case DEVICE_HUB_CONFIGURED:
-		device->device_state = STATE_POWERED;
-		break;
-
-	case DEVICE_RESET:
-		device->device_state = STATE_DEFAULT;
-		device->address = 0;
-		break;
-
-	case DEVICE_ADDRESS_ASSIGNED:
-		device->device_state = STATE_ADDRESSED;
-		break;
-
-	case DEVICE_CONFIGURED:
-		device->device_state = STATE_CONFIGURED;
-		break;
-
-	case DEVICE_DE_CONFIGURED:
-		device->device_state = STATE_ADDRESSED;
-		break;
-
-	case DEVICE_BUS_INACTIVE:
-		if (device->status != USBD_CLOSING) {
-			device->status = USBD_SUSPENDED;
-		}
-		break;
-	case DEVICE_BUS_ACTIVITY:
-		if (device->status != USBD_CLOSING) {
-			device->status = USBD_OK;
-		}
-		break;
-
-	case DEVICE_SET_INTERFACE:
-		break;
-	case DEVICE_SET_FEATURE:
-		break;
-	case DEVICE_CLEAR_FEATURE:
-		break;
-
-	case DEVICE_POWER_INTERRUPTION:
-		device->device_state = STATE_POWERED;
-		break;
-	case DEVICE_HUB_RESET:
-		device->device_state = STATE_ATTACHED;
-		break;
-	case DEVICE_DESTROY:
-		device->device_state = STATE_UNKNOWN;
-		break;
-
-	case DEVICE_FUNCTION_PRIVATE:
-		break;
-
-	default:
-		usbdbg("event %d - not handled",event);
-		break;
-	}
-	debug("%s event: %d oldstate: %d newstate: %d status: %d address: %d",
-		device->name, event, state,
-		device->device_state, device->status, device->address);
-
-	/* tell the bus interface driver */
-	if( device->event ) {
-		/* usbdbg("calling device->event"); */
-		device->event(device, event, data);
-	}
-}
diff --git a/drivers/usb/gadget/ep0.c b/drivers/usb/gadget/ep0.c
deleted file mode 100644
index 8c7fc17c2ea..00000000000
--- a/drivers/usb/gadget/ep0.c
+++ /dev/null
@@ -1,619 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2003
- * Gerry Hamel, geh@ti.com, Texas Instruments
- *
- * (C) Copyright 2006
- * Bryan O'Donoghue, deckard@CodeHermit.ie
- *
- * Based on
- * linux/drivers/usbd/ep0.c
- *
- * Copyright (c) 2000, 2001, 2002 Lineo
- * Copyright (c) 2001 Hewlett Packard
- *
- * By:
- *	Stuart Lynne <sl@lineo.com>,
- *	Tom Rushworth <tbr@lineo.com>,
- *	Bruce Balden <balden@lineo.com>
- */
-
-/*
- * This is the builtin ep0 control function. It implements all required functionality
- * for responding to control requests (SETUP packets).
- *
- * XXX
- *
- * Currently we do not pass any SETUP packets (or other) to the configured
- * function driver. This may need to change.
- *
- * XXX
- *
- * As alluded to above, a simple callback cdc_recv_setup has been implemented
- * in the usb_device data structure to facilicate passing
- * Common Device Class packets to a function driver.
- *
- * XXX
- */
-
-#include <serial.h>
-#include <usbdevice.h>
-
-#if 0
-#define dbg_ep0(lvl,fmt,args...) serial_printf("[%s] %s:%d: "fmt"\n",__FILE__,__FUNCTION__,__LINE__,##args)
-#else
-#define dbg_ep0(lvl,fmt,args...)
-#endif
-
-__maybe_unused static char *usbd_device_descriptors[] = {
-	"UNKNOWN",		/* 0 */
-	"DEVICE",		/* 1 */
-	"CONFIG",		/* 2 */
-	"STRING",		/* 3 */
-	"INTERFACE",		/* 4 */
-	"ENDPOINT",		/* 5 */
-	"DEVICE QUALIFIER",	/* 6 */
-	"OTHER SPEED",		/* 7 */
-	"INTERFACE POWER",	/* 8 */
-};
-
-#define USBD_DEVICE_DESCRIPTORS(x) (((unsigned int)x <= USB_DESCRIPTOR_TYPE_INTERFACE_POWER) ? \
-		usbd_device_descriptors[x] : "UNKNOWN")
-
-__maybe_unused static char *usbd_device_states[] = {
-	"STATE_INIT",
-	"STATE_CREATED",
-	"STATE_ATTACHED",
-	"STATE_POWERED",
-	"STATE_DEFAULT",
-	"STATE_ADDRESSED",
-	"STATE_CONFIGURED",
-	"STATE_UNKNOWN",
-};
-
-#define USBD_DEVICE_STATE(x) (((unsigned int)x <= STATE_UNKNOWN) ? usbd_device_states[x] : "UNKNOWN")
-
-__maybe_unused static char *usbd_device_requests[] = {
-	"GET STATUS",		/* 0 */
-	"CLEAR FEATURE",	/* 1 */
-	"RESERVED",		/* 2 */
-	"SET FEATURE",		/* 3 */
-	"RESERVED",		/* 4 */
-	"SET ADDRESS",		/* 5 */
-	"GET DESCRIPTOR",	/* 6 */
-	"SET DESCRIPTOR",	/* 7 */
-	"GET CONFIGURATION",	/* 8 */
-	"SET CONFIGURATION",	/* 9 */
-	"GET INTERFACE",	/* 10 */
-	"SET INTERFACE",	/* 11 */
-	"SYNC FRAME",		/* 12 */
-};
-
-#define USBD_DEVICE_REQUESTS(x) (((unsigned int)x <= USB_REQ_SYNCH_FRAME) ? usbd_device_requests[x] : "UNKNOWN")
-
-/* EP0 Configuration Set ********************************************************************* */
-
-/**
- * ep0_get_status - fill in URB data with appropriate status
- * @device:
- * @urb:
- * @index:
- * @requesttype:
- *
- */
-static int ep0_get_status (struct usb_device_instance *device,
-			   struct urb *urb, int index, int requesttype)
-{
-	char *cp;
-
-	urb->actual_length = 2;
-	cp = (char*)urb->buffer;
-	cp[0] = cp[1] = 0;
-
-	switch (requesttype) {
-	case USB_REQ_RECIPIENT_DEVICE:
-		cp[0] = USB_STATUS_SELFPOWERED;
-		break;
-	case USB_REQ_RECIPIENT_INTERFACE:
-		break;
-	case USB_REQ_RECIPIENT_ENDPOINT:
-		cp[0] = usbd_endpoint_halted (device, index);
-		break;
-	case USB_REQ_RECIPIENT_OTHER:
-		urb->actual_length = 0;
-	default:
-		break;
-	}
-	dbg_ep0 (2, "%02x %02x", cp[0], cp[1]);
-	return 0;
-}
-
-/**
- * ep0_get_one
- * @device:
- * @urb:
- * @result:
- *
- * Set a single byte value in the urb send buffer. Return non-zero to signal
- * a request error.
- */
-static int ep0_get_one (struct usb_device_instance *device, struct urb *urb,
-			__u8 result)
-{
-	urb->actual_length = 1;	/* XXX 2? */
-	((char *) urb->buffer)[0] = result;
-	return 0;
-}
-
-/**
- * copy_config
- * @urb: pointer to urb
- * @data: pointer to configuration data
- * @length: length of data
- *
- * Copy configuration data to urb transfer buffer if there is room for it.
- */
-void copy_config (struct urb *urb, void *data, int max_length,
-			 int max_buf)
-{
-	int available;
-	int length;
-
-	/*dbg_ep0(3, "-> actual: %d buf: %d max_buf: %d max_length: %d data: %p", */
-	/*        urb->actual_length, urb->buffer_length, max_buf, max_length, data); */
-
-	if (!data) {
-		dbg_ep0 (1, "data is NULL");
-		return;
-	}
-	length = max_length;
-
-	if (length > max_length) {
-		dbg_ep0 (1, "length: %d >= max_length: %d", length,
-			 max_length);
-		return;
-	}
-	/*dbg_ep0(1, "   actual: %d buf: %d max_buf: %d max_length: %d length: %d", */
-	/*        urb->actual_length, urb->buffer_length, max_buf, max_length, length); */
-
-	if ((available =
-	     /*urb->buffer_length */ max_buf - urb->actual_length) <= 0) {
-		return;
-	}
-	/*dbg_ep0(1, "actual: %d buf: %d max_buf: %d length: %d available: %d", */
-	/*        urb->actual_length, urb->buffer_length, max_buf, length, available); */
-
-	if (length > available) {
-		length = available;
-	}
-	/*dbg_ep0(1, "actual: %d buf: %d max_buf: %d length: %d available: %d", */
-	/*        urb->actual_length, urb->buffer_length, max_buf, length, available); */
-
-	memcpy (urb->buffer + urb->actual_length, data, length);
-	urb->actual_length += length;
-
-	dbg_ep0 (3,
-		 "copy_config: <- actual: %d buf: %d max_buf: %d max_length: %d available: %d",
-		 urb->actual_length, urb->buffer_length, max_buf, max_length,
-		 available);
-}
-
-/**
- * ep0_get_descriptor
- * @device:
- * @urb:
- * @max:
- * @descriptor_type:
- * @index:
- *
- * Called by ep0_rx_process for a get descriptor device command. Determine what
- * descriptor is being requested, copy to send buffer. Return zero if ok to send,
- * return non-zero to signal a request error.
- */
-static int ep0_get_descriptor (struct usb_device_instance *device,
-			       struct urb *urb, int max, int descriptor_type,
-			       int index)
-{
-	int port = 0;		/* XXX compound device */
-
-	/*dbg_ep0(3, "max: %x type: %x index: %x", max, descriptor_type, index); */
-
-	if (!urb || !urb->buffer || !urb->buffer_length
-	    || (urb->buffer_length < 255)) {
-		dbg_ep0 (2, "invalid urb %p", urb);
-		return -1L;
-	}
-
-	/* setup tx urb */
-	urb->actual_length = 0;
-
-	dbg_ep0 (2, "%s", USBD_DEVICE_DESCRIPTORS (descriptor_type));
-
-	switch (descriptor_type) {
-	case USB_DESCRIPTOR_TYPE_DEVICE:
-		{
-			struct usb_device_descriptor *device_descriptor;
-			if (!
-			    (device_descriptor =
-			     usbd_device_device_descriptor (device, port))) {
-				return -1;
-			}
-			/* copy descriptor for this device */
-			copy_config (urb, device_descriptor,
-				     sizeof (struct usb_device_descriptor),
-				     max);
-
-			/* correct the correct control endpoint 0 max packet size into the descriptor */
-			device_descriptor =
-				(struct usb_device_descriptor *) urb->buffer;
-
-		}
-		dbg_ep0(3, "copied device configuration, actual_length: 0x%x", urb->actual_length);
-		break;
-
-	case USB_DESCRIPTOR_TYPE_CONFIGURATION:
-		{
-			struct usb_configuration_descriptor
-				*configuration_descriptor;
-			struct usb_device_descriptor *device_descriptor;
-			if (!
-			    (device_descriptor =
-			     usbd_device_device_descriptor (device, port))) {
-				return -1;
-			}
-			/*dbg_ep0(2, "%d %d", index, device_descriptor->bNumConfigurations); */
-			if (index >= device_descriptor->bNumConfigurations) {
-				dbg_ep0 (0, "index too large: %d >= %d", index,
-					 device_descriptor->
-					 bNumConfigurations);
-				return -1;
-			}
-
-			if (!
-			    (configuration_descriptor =
-			     usbd_device_configuration_descriptor (device,
-								   port,
-								   index))) {
-				dbg_ep0 (0,
-					 "usbd_device_configuration_descriptor failed: %d",
-					 index);
-				return -1;
-			}
-			dbg_ep0(0, "attempt to copy %d bytes to urb\n",cpu_to_le16(configuration_descriptor->wTotalLength));
-			copy_config (urb, configuration_descriptor,
-
-					cpu_to_le16(configuration_descriptor->wTotalLength),
-				     max);
-		}
-
-		break;
-
-	case USB_DESCRIPTOR_TYPE_STRING:
-		{
-			struct usb_string_descriptor *string_descriptor;
-			if (!(string_descriptor = usbd_get_string (index))) {
-				dbg_ep0(0, "Invalid string index %d\n", index);
-				return -1;
-			}
-			dbg_ep0(3, "string_descriptor: %p length %d", string_descriptor, string_descriptor->bLength);
-			copy_config (urb, string_descriptor, string_descriptor->bLength, max);
-		}
-		break;
-	case USB_DESCRIPTOR_TYPE_INTERFACE:
-		dbg_ep0(2, "USB_DESCRIPTOR_TYPE_INTERFACE - error not implemented\n");
-		return -1;
-	case USB_DESCRIPTOR_TYPE_ENDPOINT:
-		dbg_ep0(2, "USB_DESCRIPTOR_TYPE_ENDPOINT - error not implemented\n");
-		return -1;
-	case USB_DESCRIPTOR_TYPE_HID:
-		{
-			dbg_ep0(2, "USB_DESCRIPTOR_TYPE_HID - error not implemented\n");
-			return -1;	/* unsupported at this time */
-#if 0
-			int bNumInterface =
-				le16_to_cpu (urb->device_request.wIndex);
-			int bAlternateSetting = 0;
-			int class = 0;
-			struct usb_class_descriptor *class_descriptor;
-
-			if (!(class_descriptor =
-			      usbd_device_class_descriptor_index (device,
-								  port, 0,
-								  bNumInterface,
-								  bAlternateSetting,
-								  class))
-			    || class_descriptor->descriptor.hid.bDescriptorType != USB_DT_HID) {
-				dbg_ep0 (3, "[%d] interface is not HID",
-					 bNumInterface);
-				return -1;
-			}
-			/* copy descriptor for this class */
-			copy_config (urb, class_descriptor,
-				     class_descriptor->descriptor.hid.bLength,
-				     max);
-#endif
-		}
-		break;
-	case USB_DESCRIPTOR_TYPE_REPORT:
-		{
-			dbg_ep0(2, "USB_DESCRIPTOR_TYPE_REPORT - error not implemented\n");
-			return -1;	/* unsupported at this time */
-#if 0
-			int bNumInterface =
-				le16_to_cpu (urb->device_request.wIndex);
-			int bAlternateSetting = 0;
-			int class = 0;
-			struct usb_class_report_descriptor *report_descriptor;
-
-			if (!(report_descriptor =
-			      usbd_device_class_report_descriptor_index
-			      (device, port, 0, bNumInterface,
-			       bAlternateSetting, class))
-			    || report_descriptor->bDescriptorType !=
-			    USB_DT_REPORT) {
-				dbg_ep0 (3, "[%d] descriptor is not REPORT",
-					 bNumInterface);
-				return -1;
-			}
-			/* copy report descriptor for this class */
-			/*copy_config(urb, &report_descriptor->bData[0], report_descriptor->wLength, max); */
-			if (max - urb->actual_length > 0) {
-				int length =
-					min(report_descriptor->wLength,
-					     max - urb->actual_length);
-				memcpy (urb->buffer + urb->actual_length,
-					&report_descriptor->bData[0], length);
-				urb->actual_length += length;
-			}
-#endif
-		}
-		break;
-	case USB_DESCRIPTOR_TYPE_DEVICE_QUALIFIER:
-		return -1;
-
-	default:
-		return -1;
-	}
-
-	dbg_ep0 (1, "urb: buffer: %p buffer_length: %2d actual_length: %2d tx_packetSize: %2d",
-		 urb->buffer, urb->buffer_length, urb->actual_length,
-		 device->bus->endpoint_array[0].tx_packetSize);
-/*
-    if ((urb->actual_length < max) && !(urb->actual_length % device->bus->endpoint_array[0].tx_packetSize)) {
-	dbg_ep0(0, "adding null byte");
-	urb->buffer[urb->actual_length++] = 0;
-	dbg_ep0(0, "urb: buffer_length: %2d actual_length: %2d packet size: %2d",
-		urb->buffer_length, urb->actual_length device->bus->endpoint_array[0].tx_packetSize);
-    }
-*/
-	return 0;
-
-}
-
-/**
- * ep0_recv_setup - called to indicate URB has been received
- * @urb: pointer to struct urb
- *
- * Check if this is a setup packet, process the device request, put results
- * back into the urb and return zero or non-zero to indicate success (DATA)
- * or failure (STALL).
- *
- */
-int ep0_recv_setup (struct urb *urb)
-{
-	/*struct usb_device_request *request = urb->buffer; */
-	/*struct usb_device_instance *device = urb->device; */
-
-	struct usb_device_request *request;
-	struct usb_device_instance *device;
-	int address;
-
-	dbg_ep0 (0, "entering ep0_recv_setup()");
-	if (!urb || !urb->device) {
-		dbg_ep0 (3, "invalid URB %p", urb);
-		return -1;
-	}
-
-	request = &urb->device_request;
-	device = urb->device;
-
-	dbg_ep0 (3, "urb: %p device: %p", urb, urb->device);
-
-	/*dbg_ep0(2, "-       -       -       -       -       -       -       -       -       -"); */
-
-	dbg_ep0 (2,
-		 "bmRequestType:%02x bRequest:%02x wValue:%04x wIndex:%04x wLength:%04x %s",
-		 request->bmRequestType, request->bRequest,
-		 le16_to_cpu (request->wValue), le16_to_cpu (request->wIndex),
-		 le16_to_cpu (request->wLength),
-		 USBD_DEVICE_REQUESTS (request->bRequest));
-
-	/* handle USB Standard Request (c.f. USB Spec table 9-2) */
-	if ((request->bmRequestType & USB_REQ_TYPE_MASK) != 0) {
-		if(device->device_state <= STATE_CONFIGURED){
-			/*	Attempt to handle a CDC specific request if we are
-			 *	in the configured state.
-			 */
-			return device->cdc_recv_setup(request,urb);
-		}
-		dbg_ep0 (1, "non standard request: %x",
-			 request->bmRequestType & USB_REQ_TYPE_MASK);
-		return -1;	/* Stall here */
-	}
-
-	switch (device->device_state) {
-	case STATE_CREATED:
-	case STATE_ATTACHED:
-	case STATE_POWERED:
-		/* It actually is important to allow requests in these states,
-		 * Windows will request descriptors before assigning an
-		 * address to the client.
-		 */
-
-		/*dbg_ep0 (1, "request %s not allowed in this state: %s", */
-		/*                USBD_DEVICE_REQUESTS(request->bRequest), */
-		/*                usbd_device_states[device->device_state]); */
-		/*return -1; */
-		break;
-
-	case STATE_INIT:
-	case STATE_DEFAULT:
-		switch (request->bRequest) {
-		case USB_REQ_GET_STATUS:
-		case USB_REQ_GET_INTERFACE:
-		case USB_REQ_SYNCH_FRAME:	/* XXX should never see this (?) */
-		case USB_REQ_CLEAR_FEATURE:
-		case USB_REQ_SET_FEATURE:
-		case USB_REQ_SET_DESCRIPTOR:
-			/* case USB_REQ_SET_CONFIGURATION: */
-		case USB_REQ_SET_INTERFACE:
-			dbg_ep0 (1,
-				 "request %s not allowed in DEFAULT state: %s",
-				 USBD_DEVICE_REQUESTS (request->bRequest),
-				 usbd_device_states[device->device_state]);
-			return -1;
-
-		case USB_REQ_SET_CONFIGURATION:
-		case USB_REQ_SET_ADDRESS:
-		case USB_REQ_GET_DESCRIPTOR:
-		case USB_REQ_GET_CONFIGURATION:
-			break;
-		}
-	case STATE_ADDRESSED:
-	case STATE_CONFIGURED:
-		break;
-	case STATE_UNKNOWN:
-		dbg_ep0 (1, "request %s not allowed in UNKNOWN state: %s",
-			 USBD_DEVICE_REQUESTS (request->bRequest),
-			 usbd_device_states[device->device_state]);
-		return -1;
-	}
-
-	/* handle all requests that return data (direction bit set on bm RequestType) */
-	if ((request->bmRequestType & USB_REQ_DIRECTION_MASK)) {
-
-		dbg_ep0 (3, "Device-to-Host");
-
-		switch (request->bRequest) {
-
-		case USB_REQ_GET_STATUS:
-			return ep0_get_status (device, urb, request->wIndex,
-					       request->bmRequestType &
-					       USB_REQ_RECIPIENT_MASK);
-
-		case USB_REQ_GET_DESCRIPTOR:
-			return ep0_get_descriptor (device, urb,
-						   le16_to_cpu (request->wLength),
-						   le16_to_cpu (request->wValue) >> 8,
-						   le16_to_cpu (request->wValue) & 0xff);
-
-		case USB_REQ_GET_CONFIGURATION:
-			dbg_ep0(2, "get config %d\n", device->configuration);
-			return ep0_get_one (device, urb,
-					    device->configuration);
-
-		case USB_REQ_GET_INTERFACE:
-			return ep0_get_one (device, urb, device->alternate);
-
-		case USB_REQ_SYNCH_FRAME:	/* XXX should never see this (?) */
-			return -1;
-
-		case USB_REQ_CLEAR_FEATURE:
-		case USB_REQ_SET_FEATURE:
-		case USB_REQ_SET_ADDRESS:
-		case USB_REQ_SET_DESCRIPTOR:
-		case USB_REQ_SET_CONFIGURATION:
-		case USB_REQ_SET_INTERFACE:
-			return -1;
-		}
-	}
-	/* handle the requests that do not return data */
-	else {
-
-		/*dbg_ep0(3, "Host-to-Device"); */
-		switch (request->bRequest) {
-
-		case USB_REQ_CLEAR_FEATURE:
-		case USB_REQ_SET_FEATURE:
-			dbg_ep0 (0, "Host-to-Device");
-			switch (request->
-				bmRequestType & USB_REQ_RECIPIENT_MASK) {
-			case USB_REQ_RECIPIENT_DEVICE:
-				/* XXX DEVICE_REMOTE_WAKEUP or TEST_MODE would be added here */
-				/* XXX fall through for now as we do not support either */
-			case USB_REQ_RECIPIENT_INTERFACE:
-			case USB_REQ_RECIPIENT_OTHER:
-				dbg_ep0 (0, "request %s not",
-					 USBD_DEVICE_REQUESTS (request->bRequest));
-			default:
-				return -1;
-
-			case USB_REQ_RECIPIENT_ENDPOINT:
-				dbg_ep0 (0, "ENDPOINT: %x", le16_to_cpu (request->wValue));
-				if (le16_to_cpu (request->wValue) == USB_ENDPOINT_HALT) {
-					/*return usbd_device_feature (device, le16_to_cpu (request->wIndex), */
-					/*                    request->bRequest == USB_REQ_SET_FEATURE); */
-					/* NEED TO IMPLEMENT THIS!!! */
-					return -1;
-				} else {
-					dbg_ep0 (1, "request %s bad wValue: %04x",
-						 USBD_DEVICE_REQUESTS
-						 (request->bRequest),
-						 le16_to_cpu (request->wValue));
-					return -1;
-				}
-			}
-
-		case USB_REQ_SET_ADDRESS:
-			/* check if this is a re-address, reset first if it is (this shouldn't be possible) */
-			if (device->device_state != STATE_DEFAULT) {
-				dbg_ep0 (1, "set_address: %02x state: %s",
-					 le16_to_cpu (request->wValue),
-					 usbd_device_states[device->device_state]);
-				return -1;
-			}
-			address = le16_to_cpu (request->wValue);
-			if ((address & 0x7f) != address) {
-				dbg_ep0 (1, "invalid address %04x %04x",
-					 address, address & 0x7f);
-				return -1;
-			}
-			device->address = address;
-
-			/*dbg_ep0(2, "address: %d %d %d", */
-			/*        request->wValue, le16_to_cpu(request->wValue), device->address); */
-
-			return 0;
-
-		case USB_REQ_SET_DESCRIPTOR:	/* XXX should we support this? */
-			dbg_ep0 (0, "set descriptor: NOT SUPPORTED");
-			return -1;
-
-		case USB_REQ_SET_CONFIGURATION:
-			/* c.f. 9.4.7 - the top half of wValue is reserved */
-			device->configuration = le16_to_cpu(request->wValue) & 0xff;
-
-			/* reset interface and alternate settings */
-			device->interface = device->alternate = 0;
-
-			/*dbg_ep0(2, "set configuration: %d", device->configuration); */
-			/*dbg_ep0(2, "DEVICE_CONFIGURED.. event?\n"); */
-			return 0;
-
-		case USB_REQ_SET_INTERFACE:
-			device->interface = le16_to_cpu (request->wIndex);
-			device->alternate = le16_to_cpu (request->wValue);
-			/*dbg_ep0(2, "set interface: %d alternate: %d", device->interface, device->alternate); */
-			dbg_ep0(2, "DEVICE_SET_INTERFACE.. event?\n");
-			return 0;
-
-		case USB_REQ_GET_STATUS:
-		case USB_REQ_GET_DESCRIPTOR:
-		case USB_REQ_GET_CONFIGURATION:
-		case USB_REQ_GET_INTERFACE:
-		case USB_REQ_SYNCH_FRAME:	/* XXX should never see this (?) */
-			return -1;
-		}
-	}
-	return -1;
-}
diff --git a/drivers/usb/musb-new/Kconfig b/drivers/usb/musb-new/Kconfig
index c52afd41a75..ad9072a5327 100644
--- a/drivers/usb/musb-new/Kconfig
+++ b/drivers/usb/musb-new/Kconfig
@@ -22,6 +22,13 @@ config USB_MUSB_GADGET
 	  Enables the MUSB USB dual-role controller in gadget mode.
 
 if USB_MUSB_HOST || USB_MUSB_GADGET
+config USB_MUSB_SC5XX
+        bool "Analog Devices MUSB support"
+        depends on (SC57X || SC58X)
+	help
+	 Say y here to enable support for the USB controller on
+	 ADI SC57X/SC58X processors.
+
 config USB_MUSB_DA8XX
 	bool "Enable DA8xx MUSB Controller"
 	depends on ARCH_DAVINCI
diff --git a/drivers/usb/musb-new/Makefile b/drivers/usb/musb-new/Makefile
index 396ff02654b..6638772daca 100644
--- a/drivers/usb/musb-new/Makefile
+++ b/drivers/usb/musb-new/Makefile
@@ -14,6 +14,7 @@ obj-$(CONFIG_USB_MUSB_PIC32) += pic32.o
 obj-$(CONFIG_USB_MUSB_SUNXI) += sunxi.o
 obj-$(CONFIG_USB_MUSB_TI) += ti-musb.o
 obj-$(CONFIG_USB_MUSB_UX500) += ux500.o
+obj-$(CONFIG_USB_MUSB_SC5XX) += sc5xx.o
 
 ccflags-y := $(call cc-option,-Wno-unused-variable) \
 		$(call cc-option,-Wno-unused-but-set-variable) \
diff --git a/drivers/usb/musb-new/sc5xx.c b/drivers/usb/musb-new/sc5xx.c
new file mode 100644
index 00000000000..16201480b43
--- /dev/null
+++ b/drivers/usb/musb-new/sc5xx.c
@@ -0,0 +1,202 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * (C) Copyright 2022 - Analog Devices, Inc.
+ *
+ * ADI SC5XX MUSB "glue layer"
+ *
+ * Written and/or maintained by Timesys Corporation
+ *
+ * Loosely ported from Linux driver:
+ * Author: Nathan Barrett-Morrison <nathan.morrison@timesys.com>
+ *
+ */
+
+#include <dm.h>
+#include <dm/device_compat.h>
+#include <linux/bitops.h>
+#include <linux/io.h>
+#include <linux/usb/musb.h>
+#include "linux-compat.h"
+#include "musb_core.h"
+#include "musb_uboot.h"
+
+#define MUSB_SOFTRST		0x7f
+#define  MUSB_SOFTRST_NRST	BIT(0)
+#define  MUSB_SOFTRST_NRSTX	BIT(1)
+
+#define REG_USB_VBUS_CTL	0x380
+#define REG_USB_ID_CTL		0x382
+#define REG_USB_PHY_CTL		0x394
+#define REG_USB_PLL_OSC		0x398
+#define REG_USB_UTMI_CTL	0x39c
+
+/* controller data */
+struct sc5xx_musb_data {
+	struct musb_host_data mdata;
+	struct device dev;
+};
+
+#define to_sc5xx_musb_data(d)	\
+	container_of(d, struct sc5xx_musb_data, dev)
+
+static void sc5xx_musb_disable(struct musb *musb)
+{
+	/* no way to shut the controller */
+}
+
+static int sc5xx_musb_enable(struct musb *musb)
+{
+	/* soft reset by NRSTx */
+	musb_writeb(musb->mregs, MUSB_SOFTRST, MUSB_SOFTRST_NRSTX);
+	/* set mode */
+	musb_platform_set_mode(musb, musb->board_mode);
+
+	return 0;
+}
+
+static irqreturn_t sc5xx_interrupt(int irq, void *hci)
+{
+	struct musb  *musb = hci;
+	irqreturn_t ret = IRQ_NONE;
+	u8 devctl;
+
+	musb->int_usb = musb_readb(musb->mregs, MUSB_INTRUSB);
+	musb->int_tx = musb_readw(musb->mregs, MUSB_INTRTX);
+	musb->int_rx = musb_readw(musb->mregs, MUSB_INTRRX);
+
+	if (musb->int_usb & MUSB_INTR_VBUSERROR) {
+		musb->int_usb &= ~MUSB_INTR_VBUSERROR;
+		devctl = musb_readw(musb->mregs, MUSB_DEVCTL);
+		devctl |= MUSB_DEVCTL_SESSION;
+		musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
+	}
+	if (musb->int_usb || musb->int_tx || musb->int_rx) {
+		musb_writeb(musb->mregs, MUSB_INTRUSB, musb->int_usb);
+		musb_writew(musb->mregs, MUSB_INTRTX, musb->int_tx);
+		musb_writew(musb->mregs, MUSB_INTRRX, musb->int_rx);
+		ret = musb_interrupt(musb);
+	}
+
+	if (musb->int_usb & MUSB_INTR_DISCONNECT && is_host_active(musb))
+		musb_writeb(musb->mregs, REG_USB_VBUS_CTL, 0x0);
+
+	return ret;
+}
+
+static int sc5xx_musb_set_mode(struct musb *musb, u8 mode)
+{
+	struct device *dev = musb->controller;
+	struct sc5xx_musb_data *pdata = to_sc5xx_musb_data(dev);
+
+	switch (mode) {
+	case MUSB_HOST:
+		musb_writeb(musb->mregs, REG_USB_ID_CTL, 0x1);
+		break;
+	case MUSB_PERIPHERAL:
+		musb_writeb(musb->mregs, REG_USB_ID_CTL, 0x3);
+		break;
+	case MUSB_OTG:
+		musb_writeb(musb->mregs, REG_USB_ID_CTL, 0x0);
+		break;
+	default:
+		dev_err(dev, "unsupported mode %d\n", mode);
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+static int sc5xx_musb_init(struct musb *musb)
+{
+	struct sc5xx_musb_data *pdata = to_sc5xx_musb_data(musb->controller);
+
+	musb->isr = sc5xx_interrupt;
+
+	musb_writel(musb->mregs, REG_USB_PLL_OSC, 20 << 1);
+	musb_writeb(musb->mregs, REG_USB_VBUS_CTL, 0x0);
+	musb_writeb(musb->mregs, REG_USB_PHY_CTL, 0x80);
+	musb_writel(musb->mregs, REG_USB_UTMI_CTL,
+		    0x40 | musb_readl(musb->mregs, REG_USB_UTMI_CTL));
+
+	return 0;
+}
+
+const struct musb_platform_ops sc5xx_musb_ops = {
+	.init		= sc5xx_musb_init,
+	.set_mode	= sc5xx_musb_set_mode,
+	.disable	= sc5xx_musb_disable,
+	.enable		= sc5xx_musb_enable,
+};
+
+static struct musb_hdrc_config sc5xx_musb_config = {
+	.multipoint     = 1,
+	.dyn_fifo       = 1,
+	.num_eps        = 16,
+	.ram_bits       = 12,
+};
+
+/* has one MUSB controller which can be host or gadget */
+static struct musb_hdrc_platform_data sc5xx_musb_plat = {
+	.mode           = MUSB_HOST,
+	.config         = &sc5xx_musb_config,
+	.power          = 100,
+	.platform_ops	= &sc5xx_musb_ops,
+};
+
+static int musb_usb_probe(struct udevice *dev)
+{
+	struct usb_bus_priv *priv = dev_get_uclass_priv(dev);
+	struct sc5xx_musb_data *pdata = dev_get_priv(dev);
+	struct musb_host_data *mdata = &pdata->mdata;
+	void __iomem *mregs;
+	int ret;
+
+	priv->desc_before_addr = true;
+
+	mregs = dev_remap_addr(dev);
+	if (!mregs)
+		return -EINVAL;
+
+	/* init controller */
+	if (IS_ENABLED(CONFIG_USB_MUSB_HOST)) {
+		mdata->host = musb_init_controller(&sc5xx_musb_plat,
+						   &pdata->dev, mregs);
+		if (!mdata->host)
+			return -EIO;
+
+		ret = musb_lowlevel_init(mdata);
+	} else {
+		sc5xx_musb_plat.mode = MUSB_PERIPHERAL;
+		mdata->host = musb_register(&sc5xx_musb_plat, &pdata->dev, mregs);
+		if (!mdata->host)
+			return -EIO;
+	}
+	return ret;
+}
+
+static int musb_usb_remove(struct udevice *dev)
+{
+	struct sc5xx_musb_data *pdata = dev_get_priv(dev);
+
+	musb_stop(pdata->mdata.host);
+
+	return 0;
+}
+
+static const struct udevice_id sc5xx_musb_ids[] = {
+	{ .compatible = "adi,sc5xx-musb" },
+	{ }
+};
+
+U_BOOT_DRIVER(usb_musb) = {
+	.name		= "sc5xx-musb",
+	.id		= UCLASS_USB,
+	.of_match	= sc5xx_musb_ids,
+	.probe		= musb_usb_probe,
+	.remove		= musb_usb_remove,
+#ifdef CONFIG_USB_MUSB_HOST
+	.ops		= &musb_usb_ops,
+#endif
+	.plat_auto	= sizeof(struct usb_plat),
+	.priv_auto	= sizeof(struct sc5xx_musb_data),
+};
diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
index 3c3cebaacd0..df607303616 100644
--- a/drivers/video/Kconfig
+++ b/drivers/video/Kconfig
@@ -293,27 +293,6 @@ config PANEL_HX8238D
 
 source "drivers/video/fonts/Kconfig"
 
-config VIDCONSOLE_AS_LCD
-	bool "Use 'vidconsole' when CONFIG_VIDCONSOLE_AS_NAME string is seen in stdout"
-	help
-	  This is a work-around for boards which have 'lcd' or 'vga' in their
-	  stdout environment variable, but have moved to use driver model for
-	  video. In this case the console will no-longer work. While it is
-	  possible to update the environment, the breakage may be confusing for
-	  users. This option will be removed around the end of 2020.
-
-config VIDCONSOLE_AS_NAME
-	string "Use 'vidconsole' when string defined here is seen in stdout"
-	depends on VIDCONSOLE_AS_LCD
-	default "lcd" if LCD || TEGRA_COMMON
-	default "vga" if !LCD
-	help
-	  This is a work-around for boards which have 'lcd' or 'vga' in their
-	  stdout environment variable, but have moved to use driver model for
-	  video. In this case the console will no-longer work. While it is
-	  possible to update the environment, the breakage may be confusing for
-	  users. This option will be removed around the end of 2020.
-
 config VIDEO_BOCHS
 	bool "Enable Bochs video emulation for QEMU"
 	help
@@ -599,6 +578,15 @@ config VIDEO_LCD_SAMSUNG_LTL106HL02
 	  LCD module found in Microsoft Surface 2. The panel has a FullHD
 	  resolution (1920x1080).
 
+config VIDEO_LCD_SHARP_LQ079L1SX01
+	tristate "Sharp LQ079L1SX01 1536x2048 DSI video mode panel"
+	depends on PANEL && BACKLIGHT
+	select VIDEO_MIPI_DSI
+	help
+	  Say Y here if you want to enable support for Sharp LQ079L1SX01
+	  LCD module found in Xiaomi Mi Pad tablet. The panel has a QXGA
+	  resolution (1536x2048).
+
 config VIDEO_LCD_SHARP_LQ101R1SX01
 	tristate "Sharp LQ101R1SX01 2560x1600 DSI video mode panel"
 	depends on PANEL && BACKLIGHT
@@ -712,6 +700,12 @@ config I2C_EDID
 	help
 	   This enables library for accessing EDID data from an LCD panel.
 
+config I2C_EDID_STANDARD
+	bool "Enable standard timings EDID library expansion"
+	depends on I2C_EDID
+	help
+	   This enables standard timings expansion for EDID data from an LCD panel.
+
 config DISPLAY
 	bool "Enable Display support"
 	depends on DM
@@ -743,6 +737,16 @@ config BACKLIGHT_LM3533
 	  LM3533 Lighting Power chip. Only Bank A is supported as for now.
 	  Supported backlight level range is from 2 to 255 with step of 1.
 
+config BACKLIGHT_LP855x
+	bool "Backlight Driver for LP855x"
+	depends on BACKLIGHT
+	select DM_I2C
+	help
+	  Say Y to enable the backlight driver for National Semiconductor / TI
+	  LP8550/1/2/3/5/6/7 LED Backlight Driver. Only register driven mode is
+	  supported for now, PWM mode can be added if there will be any need in
+	  it. Supported backlight level range is from 0 to 255 with step of 1.
+
 source "drivers/video/ti/Kconfig"
 
 source "drivers/video/exynos/Kconfig"
diff --git a/drivers/video/Makefile b/drivers/video/Makefile
index 5a00438ce06..6073bc5234a 100644
--- a/drivers/video/Makefile
+++ b/drivers/video/Makefile
@@ -30,6 +30,7 @@ obj-$(CONFIG_$(PHASE_)BMP) += bmp.o
 endif
 
 obj-$(CONFIG_BACKLIGHT_LM3533) += lm3533_backlight.o
+obj-$(CONFIG_BACKLIGHT_LP855x) += lp855x_backlight.o
 obj-${CONFIG_EXYNOS_FB} += exynos/
 obj-${CONFIG_VIDEO_ROCKCHIP} += rockchip/
 obj-${CONFIG_VIDEO_STM32} += stm32/
@@ -64,6 +65,7 @@ obj-$(CONFIG_VIDEO_LCD_RAYDIUM_RM68200) += raydium-rm68200.o
 obj-$(CONFIG_VIDEO_LCD_RENESAS_R61307) += renesas-r61307.o
 obj-$(CONFIG_VIDEO_LCD_RENESAS_R69328) += renesas-r69328.o
 obj-$(CONFIG_VIDEO_LCD_SAMSUNG_LTL106HL02) += samsung-ltl106hl02.o
+obj-$(CONFIG_VIDEO_LCD_SHARP_LQ079L1SX01) += sharp-lq079l1sx01.o
 obj-$(CONFIG_VIDEO_LCD_SHARP_LQ101R1SX01) += sharp-lq101r1sx01.o
 obj-$(CONFIG_VIDEO_LCD_SSD2828) += ssd2828.o
 obj-$(CONFIG_VIDEO_LCD_TDO_TL070WSH30) += tdo-tl070wsh30.o
diff --git a/drivers/video/bridge/Kconfig b/drivers/video/bridge/Kconfig
index ab917273720..be53034bd3d 100644
--- a/drivers/video/bridge/Kconfig
+++ b/drivers/video/bridge/Kconfig
@@ -9,7 +9,7 @@ config VIDEO_BRIDGE
 
 config VIDEO_BRIDGE_PARADE_DP501
 	bool "Support Parade DP501 DP & DVI/HDMI dual mode transmitter"
-	depends on PANEL && DM_GPIO
+	depends on VIDEO_BRIDGE && PANEL && DM_GPIO
 	select DM_I2C
 	help
 	  The Parade DP501 is a DP & DVI/HDMI dual-mode transmitter. It
@@ -46,16 +46,23 @@ config VIDEO_BRIDGE_ANALOGIX_ANX6345
 
 config VIDEO_BRIDGE_SOLOMON_SSD2825
 	bool "Solomon SSD2825 bridge driver"
-	depends on PANEL && DM_GPIO
+	depends on VIDEO_BRIDGE && PANEL && DM_GPIO
 	select VIDEO_MIPI_DSI
 	help
-	  Solomon SSD2824 SPI RGB-DSI bridge driver wrapped into panel uClass.
+	  Solomon SSD2824 SPI RGB-DSI bridge driver.
 
 config VIDEO_BRIDGE_TOSHIBA_TC358768
 	bool "Support Toshiba TC358768 MIPI DSI bridge"
-	depends on PANEL && DM_GPIO
+	depends on VIDEO_BRIDGE && PANEL && DM_GPIO
 	select VIDEO_MIPI_DSI
 	select DM_I2C
 	help
 	  Toshiba TC358768AXBG/TC358778XBG DSI bridge chip driver.
 	  Found in Asus Transformer Infinity TF700T.
+
+config VIDEO_BRIDGE_LVDS_CODEC
+	bool "Transparent LVDS encoders and decoders support"
+	depends on VIDEO_BRIDGE && PANEL && DM_GPIO
+	help
+	  Support for transparent LVDS encoders and decoders that don't
+	  require any configuration.
diff --git a/drivers/video/bridge/Makefile b/drivers/video/bridge/Makefile
index 58697e3cbe9..63dc6e62c49 100644
--- a/drivers/video/bridge/Makefile
+++ b/drivers/video/bridge/Makefile
@@ -10,3 +10,4 @@ obj-$(CONFIG_VIDEO_BRIDGE_NXP_PTN3460) += ptn3460.o
 obj-$(CONFIG_VIDEO_BRIDGE_ANALOGIX_ANX6345) += anx6345.o
 obj-$(CONFIG_VIDEO_BRIDGE_SOLOMON_SSD2825) += ssd2825.o
 obj-$(CONFIG_VIDEO_BRIDGE_TOSHIBA_TC358768) += tc358768.o
+obj-$(CONFIG_VIDEO_BRIDGE_LVDS_CODEC) += lvds-codec.o
diff --git a/drivers/video/bridge/dp501.c b/drivers/video/bridge/dp501.c
index 095e3e71fed..9937cfe095b 100644
--- a/drivers/video/bridge/dp501.c
+++ b/drivers/video/bridge/dp501.c
@@ -9,6 +9,7 @@
 #include <log.h>
 #include <backlight.h>
 #include <panel.h>
+#include <video_bridge.h>
 #include <linux/delay.h>
 #include <linux/err.h>
 #include <power/regulator.h>
@@ -206,7 +207,6 @@ struct dp501_priv {
 	struct udevice *chip2;
 
 	struct udevice *vdd;
-	struct gpio_desc reset_gpio;
 	struct gpio_desc enable_gpio;
 };
 
@@ -484,16 +484,19 @@ static int dp501_panel_timings(struct udevice *dev,
 	return 0;
 }
 
-static void dp501_hw_init(struct dp501_priv *priv)
+static void dp501_hw_init(struct udevice *dev)
 {
-	dm_gpio_set_value(&priv->reset_gpio, 1);
+	struct dp501_priv *priv = dev_get_priv(dev);
+	struct video_bridge_priv *uc_priv = dev_get_uclass_priv(dev);
+
+	dm_gpio_set_value(&uc_priv->reset, 1);
 
 	regulator_set_enable_if_allowed(priv->vdd, 1);
 	dm_gpio_set_value(&priv->enable_gpio, 1);
 
 	udelay(100);
 
-	dm_gpio_set_value(&priv->reset_gpio, 0);
+	dm_gpio_set_value(&uc_priv->reset, 0);
 	mdelay(80);
 }
 
@@ -521,14 +524,6 @@ static int dp501_setup(struct udevice *dev)
 	}
 
 	/* get gpios */
-	ret = gpio_request_by_name(dev, "reset-gpios", 0,
-				   &priv->reset_gpio, GPIOD_IS_OUT);
-	if (ret) {
-		log_debug("%s: Could not decode reset-gpios (%d)\n",
-			  __func__, ret);
-		return ret;
-	}
-
 	ret = gpio_request_by_name(dev, "enable-gpios", 0,
 				   &priv->enable_gpio, GPIOD_IS_OUT);
 	if (ret) {
@@ -544,7 +539,7 @@ static int dp501_setup(struct udevice *dev)
 		return ret;
 	}
 
-	dp501_hw_init(priv);
+	dp501_hw_init(dev);
 
 	/* get EDID */
 	return panel_get_display_timing(priv->panel, &priv->timing);
@@ -558,8 +553,8 @@ static int dp501_probe(struct udevice *dev)
 	return dp501_setup(dev);
 }
 
-struct panel_ops dp501_ops = {
-	.enable_backlight	= dp501_attach,
+static const struct video_bridge_ops dp501_ops = {
+	.attach			= dp501_attach,
 	.set_backlight		= dp501_set_backlight,
 	.get_display_timing	= dp501_panel_timings,
 };
@@ -571,7 +566,7 @@ static const struct udevice_id dp501_ids[] = {
 
 U_BOOT_DRIVER(dp501) = {
 	.name		= "dp501",
-	.id		= UCLASS_PANEL,
+	.id		= UCLASS_VIDEO_BRIDGE,
 	.of_match	= dp501_ids,
 	.ops		= &dp501_ops,
 	.probe		= dp501_probe,
diff --git a/drivers/video/bridge/lvds-codec.c b/drivers/video/bridge/lvds-codec.c
new file mode 100644
index 00000000000..6cd8368a39e
--- /dev/null
+++ b/drivers/video/bridge/lvds-codec.c
@@ -0,0 +1,128 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2025 Svyatoslav Ryhel <clamor95@gmail.com>
+ * Loosely based on Linux lvds-codec.c driver
+ */
+
+#include <dm.h>
+#include <dm/ofnode_graph.h>
+#include <log.h>
+#include <panel.h>
+#include <video_bridge.h>
+#include <asm/gpio.h>
+#include <power/regulator.h>
+
+struct lvds_codec_priv {
+	struct udevice *panel;
+	struct display_timing timing;
+
+	struct gpio_desc powerdown_gpio;
+	struct udevice *power;
+};
+
+static int lvds_codec_attach(struct udevice *dev)
+{
+	struct lvds_codec_priv *priv = dev_get_priv(dev);
+
+	regulator_set_enable_if_allowed(priv->power, 1);
+	dm_gpio_set_value(&priv->powerdown_gpio, 0);
+
+	return panel_enable_backlight(priv->panel);
+}
+
+static int lvds_codec_set_panel(struct udevice *dev, int percent)
+{
+	struct lvds_codec_priv *priv = dev_get_priv(dev);
+
+	return panel_set_backlight(priv->panel, percent);
+}
+
+static int lvds_codec_panel_timings(struct udevice *dev,
+				    struct display_timing *timing)
+{
+	struct lvds_codec_priv *priv = dev_get_priv(dev);
+
+	memcpy(timing, &priv->timing, sizeof(*timing));
+
+	return 0;
+}
+
+/* Function is purely for sandbox testing */
+static int lvds_codec_read_edid(struct udevice *dev, u8 *buf, int buf_size)
+{
+	return 0;
+}
+
+static int lvds_codec_get_panel(struct udevice *dev)
+{
+	struct lvds_codec_priv *priv = dev_get_priv(dev);
+	int i, ret;
+
+	u32 num = ofnode_graph_get_port_count(dev_ofnode(dev));
+
+	for (i = 0; i < num; i++) {
+		ofnode remote = ofnode_graph_get_remote_node(dev_ofnode(dev), i, -1);
+
+		ret = uclass_get_device_by_of_offset(UCLASS_PANEL,
+						     ofnode_to_offset(remote),
+						     &priv->panel);
+		if (!ret)
+			return 0;
+	}
+
+	/* If this point is reached, no panels were found */
+	return -ENODEV;
+}
+
+static int lvds_codec_probe(struct udevice *dev)
+{
+	struct lvds_codec_priv *priv = dev_get_priv(dev);
+	int ret;
+
+	ret = lvds_codec_get_panel(dev);
+	if (ret) {
+		log_debug("%s: cannot get panel: ret=%d\n", __func__, ret);
+		return log_ret(ret);
+	}
+
+	panel_get_display_timing(priv->panel, &priv->timing);
+
+	ret = gpio_request_by_name(dev, "powerdown-gpios", 0,
+				   &priv->powerdown_gpio, GPIOD_IS_OUT);
+	if (ret) {
+		log_debug("%s: could not get powerdown-gpios (%d)\n", __func__, ret);
+		if (ret != -ENOENT)
+			return log_ret(ret);
+	}
+
+	ret = device_get_supply_regulator(dev, "power-supply", &priv->power);
+	if (ret) {
+		log_debug("%s: power regulator error: %d\n", __func__, ret);
+		if (ret != -ENOENT)
+			return log_ret(ret);
+	}
+
+	return 0;
+}
+
+static const struct video_bridge_ops lvds_codec_ops = {
+	.attach			= lvds_codec_attach,
+	.set_backlight		= lvds_codec_set_panel,
+	.get_display_timing	= lvds_codec_panel_timings,
+	.read_edid		= lvds_codec_read_edid,
+};
+
+static const struct udevice_id lvds_codec_ids[] = {
+	{ .compatible = "lvds-decoder" },
+	{ .compatible = "lvds-encoder" },
+	{ }
+};
+
+U_BOOT_DRIVER(lvds_codec) = {
+	.name		= "lvds_codec",
+	.id		= UCLASS_VIDEO_BRIDGE,
+	.of_match	= lvds_codec_ids,
+	.ops		= &lvds_codec_ops,
+	.probe		= lvds_codec_probe,
+	.priv_auto	= sizeof(struct lvds_codec_priv),
+};
diff --git a/drivers/video/bridge/ssd2825.c b/drivers/video/bridge/ssd2825.c
index f978021c860..a307993377c 100644
--- a/drivers/video/bridge/ssd2825.c
+++ b/drivers/video/bridge/ssd2825.c
@@ -5,12 +5,15 @@
 
 #include <clk.h>
 #include <dm.h>
+#include <dm/ofnode_graph.h>
 #include <log.h>
 #include <misc.h>
 #include <mipi_display.h>
 #include <mipi_dsi.h>
 #include <backlight.h>
+#include <video_bridge.h>
 #include <panel.h>
+#include <power/regulator.h>
 #include <spi.h>
 #include <linux/delay.h>
 #include <linux/err.h>
@@ -106,6 +109,10 @@
 #define SSD2825_LP_MIN_CLK		5000 /* KHz */
 #define SSD2825_REF_MIN_CLK		2000 /* KHz */
 
+static const char * const ssd2825_supplies[] = {
+	"dvdd-supply", "avdd-supply", "vddio-supply"
+};
+
 struct ssd2825_bridge_priv {
 	struct mipi_dsi_host host;
 	struct mipi_dsi_device device;
@@ -113,12 +120,16 @@ struct ssd2825_bridge_priv {
 	struct udevice *panel;
 	struct display_timing timing;
 
+	struct udevice *supplies[ARRAY_SIZE(ssd2825_supplies)];
+
 	struct gpio_desc power_gpio;
-	struct gpio_desc reset_gpio;
 
 	struct clk *tx_clk;
 
 	u32 pll_freq_kbps;	/* PLL in kbps */
+
+	u32 hzd;		/* HS Zero Delay in ns */
+	u32 hpd;		/* HS Prepare Delay is ns */
 };
 
 static int ssd2825_spi_write(struct udevice *dev, int reg,
@@ -231,7 +242,6 @@ static ssize_t ssd2825_bridge_transfer(struct mipi_dsi_host *host,
 				       const struct mipi_dsi_msg *msg)
 {
 	struct udevice *dev = (struct udevice *)host->dev;
-	u8 buf = *(u8 *)msg->tx_buf;
 	u16 config;
 	int ret;
 
@@ -260,15 +270,6 @@ static ssize_t ssd2825_bridge_transfer(struct mipi_dsi_host *host,
 	ssd2825_write_register(dev, SSD2825_VC_CTRL_REG, 0x0000);
 	ssd2825_write_dsi(dev, msg->tx_buf, msg->tx_len);
 
-	if (buf == MIPI_DCS_SET_DISPLAY_ON) {
-		ssd2825_write_register(dev, SSD2825_CONFIGURATION_REG,
-				SSD2825_CONF_REG_HS | SSD2825_CONF_REG_VEN |
-				SSD2825_CONF_REG_DCS | SSD2825_CONF_REG_ECD |
-				SSD2825_CONF_REG_EOT);
-		ssd2825_write_register(dev, SSD2825_PLL_CTRL_REG, 0x0001);
-		ssd2825_write_register(dev, SSD2825_VC_CTRL_REG, 0x0000);
-	}
-
 	return 0;
 }
 
@@ -312,9 +313,14 @@ static void ssd2825_setup_pll(struct udevice *dev)
 	struct mipi_dsi_device *device = &priv->device;
 	struct display_timing *dt = &priv->timing;
 	u16 pll_config, lp_div;
+	u32 nibble_delay, nibble_freq_khz;
 	u32 pclk_mult, tx_freq_khz, pd_lines;
+	u8 hzd, hpd;
 
 	tx_freq_khz = clk_get_rate(priv->tx_clk) / 1000;
+	if (!tx_freq_khz || tx_freq_khz < 0)
+		tx_freq_khz = SSD2825_REF_MIN_CLK;
+
 	pd_lines = mipi_dsi_pixel_format_to_bpp(device->format);
 	pclk_mult = pd_lines / device->lanes + 1;
 
@@ -324,12 +330,19 @@ static void ssd2825_setup_pll(struct udevice *dev)
 
 	lp_div = priv->pll_freq_kbps / (SSD2825_LP_MIN_CLK * 8);
 
+	/* nibble_delay in nanoseconds */
+	nibble_freq_khz = priv->pll_freq_kbps / 4;
+	nibble_delay = 1000 * 1000 / nibble_freq_khz;
+
+	hzd = priv->hzd / nibble_delay;
+	hpd = (priv->hpd - 4 * nibble_delay) / nibble_delay;
+
 	/* Disable PLL */
 	ssd2825_write_register(dev, SSD2825_PLL_CTRL_REG, 0x0000);
 	ssd2825_write_register(dev, SSD2825_LINE_CTRL_REG, 0x0001);
 
 	/* Set delays */
-	ssd2825_write_register(dev, SSD2825_DELAY_ADJ_REG_1, 0x2103);
+	ssd2825_write_register(dev, SSD2825_DELAY_ADJ_REG_1, (hzd << 8) | hpd);
 
 	/* Set PLL coeficients */
 	ssd2825_write_register(dev, SSD2825_PLL_CONFIGURATION_REG, pll_config);
@@ -343,11 +356,30 @@ static void ssd2825_setup_pll(struct udevice *dev)
 	ssd2825_write_register(dev, SSD2825_VC_CTRL_REG, 0x0000);
 }
 
-static int ssd2825_bridge_enable_panel(struct udevice *dev)
+static int ssd2825_bridge_attach(struct udevice *dev)
 {
 	struct ssd2825_bridge_priv *priv = dev_get_priv(dev);
 	struct mipi_dsi_device *device = &priv->device;
 	struct display_timing *dt = &priv->timing;
+	u8 pixel_format;
+	int ret;
+
+	/* Set pixel format */
+	switch (device->format) {
+	case MIPI_DSI_FMT_RGB565:
+		pixel_format = 0x00;
+		break;
+	case MIPI_DSI_FMT_RGB666_PACKED:
+		pixel_format = 0x01;
+		break;
+	case MIPI_DSI_FMT_RGB666:
+		pixel_format = 0x02;
+		break;
+	case MIPI_DSI_FMT_RGB888:
+	default:
+		pixel_format = 0x03;
+		break;
+	}
 
 	/* Perform SW reset */
 	ssd2825_write_register(dev, SSD2825_OPERATION_CTRL_REG, 0x0100);
@@ -367,7 +399,7 @@ static int ssd2825_bridge_enable_panel(struct udevice *dev)
 	ssd2825_write_register(dev, SSD2825_RGB_INTERFACE_CTRL_REG_6,
 			       SSD2825_HSYNC_HIGH | SSD2825_VSYNC_HIGH |
 			       SSD2825_PCKL_HIGH | SSD2825_NON_BURST |
-			       (3 - device->format));
+			       pixel_format);
 	ssd2825_write_register(dev, SSD2825_LANE_CONFIGURATION_REG,
 			       device->lanes - 1);
 	ssd2825_write_register(dev, SSD2825_TEST_REG, 0x0004);
@@ -384,7 +416,18 @@ static int ssd2825_bridge_enable_panel(struct udevice *dev)
 	ssd2825_write_register(dev, SSD2825_VC_CTRL_REG, 0x0000);
 
 	/* Perform panel setup */
-	return panel_enable_backlight(priv->panel);
+	ret = panel_enable_backlight(priv->panel);
+	if (ret)
+		return ret;
+
+	ssd2825_write_register(dev, SSD2825_CONFIGURATION_REG,
+			       SSD2825_CONF_REG_HS | SSD2825_CONF_REG_VEN |
+			       SSD2825_CONF_REG_DCS | SSD2825_CONF_REG_ECD |
+			       SSD2825_CONF_REG_EOT);
+	ssd2825_write_register(dev, SSD2825_PLL_CTRL_REG, 0x0001);
+	ssd2825_write_register(dev, SSD2825_VC_CTRL_REG, 0x0000);
+
+	return 0;
 }
 
 static int ssd2825_bridge_set_panel(struct udevice *dev, int percent)
@@ -407,7 +450,8 @@ static int ssd2825_bridge_panel_timings(struct udevice *dev,
 static int ssd2825_bridge_hw_init(struct udevice *dev)
 {
 	struct ssd2825_bridge_priv *priv = dev_get_priv(dev);
-	int ret;
+	struct video_bridge_priv *uc_priv = dev_get_uclass_priv(dev);
+	int i, ret;
 
 	ret = clk_prepare_enable(priv->tx_clk);
 	if (ret) {
@@ -416,25 +460,28 @@ static int ssd2825_bridge_hw_init(struct udevice *dev)
 		return ret;
 	}
 
-	ret = dm_gpio_set_value(&priv->power_gpio, 1);
-	if (ret) {
-		log_debug("%s: error changing power-gpios (%d)\n",
-			  __func__, ret);
-		return ret;
+	/* enable supplies */
+	for (i = 0; i < ARRAY_SIZE(ssd2825_supplies); i++) {
+		ret = regulator_set_enable_if_allowed(priv->supplies[i], 1);
+		if (ret) {
+			log_debug("%s: cannot enable %s %d\n", __func__,
+				  ssd2825_supplies[i], ret);
+			return ret;
+		}
 	}
 	mdelay(10);
 
-	ret = dm_gpio_set_value(&priv->reset_gpio, 0);
+	ret = dm_gpio_set_value(&uc_priv->reset, 1);
 	if (ret) {
-		log_debug("%s: error changing reset-gpios (%d)\n",
+		log_debug("%s: error entering reset (%d)\n",
 			  __func__, ret);
 		return ret;
 	}
 	mdelay(10);
 
-	ret = dm_gpio_set_value(&priv->reset_gpio, 1);
+	ret = dm_gpio_set_value(&uc_priv->reset, 0);
 	if (ret) {
-		log_debug("%s: error changing reset-gpios (%d)\n",
+		log_debug("%s: error exiting reset (%d)\n",
 			  __func__, ret);
 		return ret;
 	}
@@ -443,13 +490,33 @@ static int ssd2825_bridge_hw_init(struct udevice *dev)
 	return 0;
 }
 
+static int ssd2825_bridge_get_panel(struct udevice *dev)
+{
+	struct ssd2825_bridge_priv *priv = dev_get_priv(dev);
+	int i, ret;
+
+	u32 num = ofnode_graph_get_port_count(dev_ofnode(dev));
+
+	for (i = 0; i < num; i++) {
+		ofnode remote = ofnode_graph_get_remote_node(dev_ofnode(dev), i, -1);
+
+		ret = uclass_get_device_by_ofnode(UCLASS_PANEL, remote,
+						  &priv->panel);
+		if (!ret)
+			return 0;
+	}
+
+	/* If this point is reached, no panels were found */
+	return -ENODEV;
+}
+
 static int ssd2825_bridge_probe(struct udevice *dev)
 {
 	struct ssd2825_bridge_priv *priv = dev_get_priv(dev);
 	struct spi_slave *slave = dev_get_parent_priv(dev);
 	struct mipi_dsi_device *device = &priv->device;
 	struct mipi_dsi_panel_plat *mipi_plat;
-	int ret;
+	int i, ret;
 
 	ret = spi_claim_bus(slave);
 	if (ret) {
@@ -457,10 +524,9 @@ static int ssd2825_bridge_probe(struct udevice *dev)
 		return ret;
 	}
 
-	ret = uclass_get_device_by_phandle(UCLASS_PANEL, dev,
-					   "panel", &priv->panel);
+	ret = ssd2825_bridge_get_panel(dev);
 	if (ret) {
-		log_err("cannot get panel: ret=%d\n", ret);
+		log_debug("%s: panel not found, ret %d\n", __func__, ret);
 		return ret;
 	}
 
@@ -477,33 +543,33 @@ static int ssd2825_bridge_probe(struct udevice *dev)
 	device->format = mipi_plat->format;
 	device->mode_flags = mipi_plat->mode_flags;
 
-	/* get panel gpios */
-	ret = gpio_request_by_name(dev, "power-gpios", 0,
-				   &priv->power_gpio, GPIOD_IS_OUT);
-	if (ret) {
-		log_err("could not decode power-gpios (%d)\n", ret);
-		return ret;
-	}
-
-	ret = gpio_request_by_name(dev, "reset-gpios", 0,
-				   &priv->reset_gpio, GPIOD_IS_OUT);
-	if (ret) {
-		log_err("could not decode reset-gpios (%d)\n", ret);
-		return ret;
+	/* get supplies */
+	for (i = 0; i < ARRAY_SIZE(ssd2825_supplies); i++) {
+		ret = device_get_supply_regulator(dev, ssd2825_supplies[i],
+						  &priv->supplies[i]);
+		if (ret) {
+			log_debug("%s: cannot get %s %d\n", __func__,
+				  ssd2825_supplies[i], ret);
+			if (ret != -ENOENT)
+				return log_ret(ret);
+		}
 	}
 
 	/* get clk */
-	priv->tx_clk = devm_clk_get(dev, "tx_clk");
+	priv->tx_clk = devm_clk_get_optional(dev, NULL);
 	if (IS_ERR(priv->tx_clk)) {
 		log_err("cannot get tx_clk: %ld\n", PTR_ERR(priv->tx_clk));
 		return PTR_ERR(priv->tx_clk);
 	}
 
+	priv->hzd = dev_read_u32_default(dev, "solomon,hs-zero-delay-ns", 133);
+	priv->hpd = dev_read_u32_default(dev, "solomon,hs-prep-delay-ns", 40);
+
 	return ssd2825_bridge_hw_init(dev);
 }
 
-static const struct panel_ops ssd2825_bridge_ops = {
-	.enable_backlight	= ssd2825_bridge_enable_panel,
+static const struct video_bridge_ops ssd2825_bridge_ops = {
+	.attach			= ssd2825_bridge_attach,
 	.set_backlight		= ssd2825_bridge_set_panel,
 	.get_display_timing	= ssd2825_bridge_panel_timings,
 };
@@ -515,9 +581,10 @@ static const struct udevice_id ssd2825_bridge_ids[] = {
 
 U_BOOT_DRIVER(ssd2825) = {
 	.name		= "ssd2825",
-	.id		= UCLASS_PANEL,
+	.id		= UCLASS_VIDEO_BRIDGE,
 	.of_match	= ssd2825_bridge_ids,
 	.ops		= &ssd2825_bridge_ops,
+	.bind		= dm_scan_fdt_dev,
 	.probe		= ssd2825_bridge_probe,
 	.priv_auto	= sizeof(struct ssd2825_bridge_priv),
 };
diff --git a/drivers/video/bridge/tc358768.c b/drivers/video/bridge/tc358768.c
index 19b6ca29d3e..358004f30f2 100644
--- a/drivers/video/bridge/tc358768.c
+++ b/drivers/video/bridge/tc358768.c
@@ -6,12 +6,14 @@
 
 #include <clk.h>
 #include <dm.h>
+#include <dm/ofnode_graph.h>
 #include <i2c.h>
 #include <log.h>
 #include <mipi_display.h>
 #include <mipi_dsi.h>
 #include <backlight.h>
 #include <panel.h>
+#include <video_bridge.h>
 #include <linux/delay.h>
 #include <linux/err.h>
 #include <linux/kernel.h>
@@ -122,6 +124,10 @@
 #define NANO	1000000000UL
 #define PICO	1000000000000ULL
 
+static const char * const tc358768_supplies[] = {
+	"vddc-supply", "vddmipi-supply", "vddio-supply"
+};
+
 struct tc358768_priv {
 	struct mipi_dsi_host host;
 	struct mipi_dsi_device device;
@@ -129,9 +135,7 @@ struct tc358768_priv {
 	struct udevice *panel;
 	struct display_timing timing;
 
-	struct udevice *vddc;
-	struct udevice *vddmipi;
-	struct udevice *vddio;
+	struct udevice *supplies[ARRAY_SIZE(tc358768_supplies)];
 
 	struct clk *refclk;
 
@@ -265,25 +269,27 @@ static void tc358768_sw_reset(struct udevice *dev)
 	tc358768_write(dev, TC358768_SYSCTL, 0);
 }
 
-static void tc358768_hw_enable(struct tc358768_priv *priv)
+static void tc358768_hw_enable(struct udevice *dev)
 {
+	struct tc358768_priv *priv = dev_get_priv(dev);
+	struct video_bridge_priv *uc_priv = dev_get_uclass_priv(dev);
 	int ret;
 
 	ret = clk_prepare_enable(priv->refclk);
 	if (ret)
 		log_debug("%s: error enabling refclk (%d)\n", __func__, ret);
 
-	ret = regulator_set_enable_if_allowed(priv->vddc, true);
+	ret = regulator_set_enable_if_allowed(priv->supplies[0], true);
 	if (ret)
 		log_debug("%s: error enabling vddc (%d)\n", __func__, ret);
 
-	ret = regulator_set_enable_if_allowed(priv->vddmipi, true);
+	ret = regulator_set_enable_if_allowed(priv->supplies[1], true);
 	if (ret)
 		log_debug("%s: error enabling vddmipi (%d)\n", __func__, ret);
 
 	mdelay(10);
 
-	ret = regulator_set_enable_if_allowed(priv->vddio, true);
+	ret = regulator_set_enable_if_allowed(priv->supplies[2], true);
 	if (ret)
 		log_debug("%s: error enabling vddio (%d)\n", __func__, ret);
 
@@ -293,7 +299,7 @@ static void tc358768_hw_enable(struct tc358768_priv *priv)
 	 * The RESX is active low (GPIO_ACTIVE_LOW).
 	 * DEASSERT (value = 0) the reset_gpio to enable the chip
 	 */
-	ret = dm_gpio_set_value(&priv->reset_gpio, 0);
+	ret = dm_gpio_set_value(&uc_priv->reset, 0);
 	if (ret)
 		log_debug("%s: error changing reset-gpio (%d)\n", __func__, ret);
 
@@ -477,7 +483,7 @@ static int tc358768_attach(struct udevice *dev)
 		device->mode_flags &= ~MIPI_DSI_CLOCK_NON_CONTINUOUS;
 	}
 
-	tc358768_hw_enable(priv);
+	tc358768_hw_enable(dev);
 	tc358768_sw_reset(dev);
 
 	tc358768_setup_pll(dev);
@@ -874,12 +880,33 @@ static int tc358768_panel_timings(struct udevice *dev,
 	return 0;
 }
 
+static int tc358768_get_panel(struct udevice *dev)
+{
+	struct tc358768_priv *priv = dev_get_priv(dev);
+	int i, ret;
+
+	u32 num = ofnode_graph_get_port_count(dev_ofnode(dev));
+
+	for (i = 0; i < num; i++) {
+		ofnode remote = ofnode_graph_get_remote_node(dev_ofnode(dev), i, -1);
+
+		ret = uclass_get_device_by_ofnode(UCLASS_PANEL, remote,
+						  &priv->panel);
+		if (!ret)
+			return 0;
+	}
+
+	/* If this point is reached, no panels were found */
+	return -ENODEV;
+}
+
 static int tc358768_setup(struct udevice *dev)
 {
 	struct tc358768_priv *priv = dev_get_priv(dev);
+	struct video_bridge_priv *uc_priv = dev_get_uclass_priv(dev);
 	struct mipi_dsi_device *device = &priv->device;
 	struct mipi_dsi_panel_plat *mipi_plat;
-	int ret;
+	int i, ret;
 
 	/* The bridge uses 16 bit registers */
 	ret = i2c_set_chip_offset_len(dev, 2);
@@ -889,11 +916,10 @@ static int tc358768_setup(struct udevice *dev)
 		return ret;
 	}
 
-	ret = uclass_get_device_by_phandle(UCLASS_PANEL, dev,
-					   "panel", &priv->panel);
+	ret = tc358768_get_panel(dev);
 	if (ret) {
-		log_debug("%s: Cannot get panel: ret=%d\n", __func__, ret);
-		return log_ret(ret);
+		log_debug("%s: panel not found, ret %d\n", __func__, ret);
+		return ret;
 	}
 
 	panel_get_display_timing(priv->panel, &priv->timing);
@@ -913,44 +939,26 @@ static int tc358768_setup(struct udevice *dev)
 	priv->dsi_lanes = device->lanes;
 
 	/* get regulators */
-	ret = device_get_supply_regulator(dev, "vddc-supply", &priv->vddc);
-	if (ret) {
-		log_debug("%s: vddc regulator error: %d\n", __func__, ret);
-		if (ret != -ENOENT)
-			return log_ret(ret);
-	}
-
-	ret = device_get_supply_regulator(dev, "vddmipi-supply", &priv->vddmipi);
-	if (ret) {
-		log_debug("%s: vddmipi regulator error: %d\n", __func__, ret);
-		if (ret != -ENOENT)
-			return log_ret(ret);
-	}
-
-	ret = device_get_supply_regulator(dev, "vddio-supply", &priv->vddio);
-	if (ret) {
-		log_debug("%s: vddio regulator error: %d\n", __func__, ret);
-		if (ret != -ENOENT)
-			return log_ret(ret);
+	for (i = 0; i < ARRAY_SIZE(tc358768_supplies); i++) {
+		ret = device_get_supply_regulator(dev, tc358768_supplies[i],
+						  &priv->supplies[i]);
+		if (ret) {
+			log_debug("%s: cannot get %s %d\n", __func__,
+				  tc358768_supplies[i], ret);
+			if (ret != -ENOENT)
+				return log_ret(ret);
+		}
 	}
 
 	/* get clk */
-	priv->refclk = devm_clk_get(dev, "refclk");
+	priv->refclk = devm_clk_get(dev, NULL);
 	if (IS_ERR(priv->refclk)) {
 		log_debug("%s: Could not get refclk: %ld\n",
 			  __func__, PTR_ERR(priv->refclk));
 		return PTR_ERR(priv->refclk);
 	}
 
-	/* get gpios */
-	ret = gpio_request_by_name(dev, "reset-gpios", 0,
-				   &priv->reset_gpio, GPIOD_IS_OUT);
-	if (ret) {
-		log_debug("%s: Could not decode reset-gpios (%d)\n", __func__, ret);
-		return ret;
-	}
-
-	dm_gpio_set_value(&priv->reset_gpio, 1);
+	dm_gpio_set_value(&uc_priv->reset, 1);
 
 	return 0;
 }
@@ -963,8 +971,8 @@ static int tc358768_probe(struct udevice *dev)
 	return tc358768_setup(dev);
 }
 
-struct panel_ops tc358768_ops = {
-	.enable_backlight	= tc358768_attach,
+static const struct video_bridge_ops tc358768_ops = {
+	.attach			= tc358768_attach,
 	.set_backlight		= tc358768_set_backlight,
 	.get_display_timing	= tc358768_panel_timings,
 };
@@ -977,9 +985,10 @@ static const struct udevice_id tc358768_ids[] = {
 
 U_BOOT_DRIVER(tc358768) = {
 	.name		= "tc358768",
-	.id		= UCLASS_PANEL,
+	.id		= UCLASS_VIDEO_BRIDGE,
 	.of_match	= tc358768_ids,
 	.ops		= &tc358768_ops,
+	.bind		= dm_scan_fdt_dev,
 	.probe		= tc358768_probe,
 	.priv_auto	= sizeof(struct tc358768_priv),
 };
diff --git a/drivers/video/bridge/video-bridge-uclass.c b/drivers/video/bridge/video-bridge-uclass.c
index 2084a2e03ee..1b8aa12b9e8 100644
--- a/drivers/video/bridge/video-bridge-uclass.c
+++ b/drivers/video/bridge/video-bridge-uclass.c
@@ -33,6 +33,17 @@ int video_bridge_attach(struct udevice *dev)
 	return ops->attach(dev);
 }
 
+int video_bridge_get_display_timing(struct udevice *dev,
+				    struct display_timing *timings)
+{
+	struct video_bridge_ops *ops = video_bridge_get_ops(dev);
+
+	if (!ops->get_display_timing)
+		return -ENOSYS;
+
+	return ops->get_display_timing(dev, timings);
+}
+
 int video_bridge_check_attached(struct udevice *dev)
 {
 	struct video_bridge_priv *uc_priv = dev_get_uclass_priv(dev);
diff --git a/drivers/video/endeavoru-panel.c b/drivers/video/endeavoru-panel.c
index d4ba4d8b6da..9950ff8bb05 100644
--- a/drivers/video/endeavoru-panel.c
+++ b/drivers/video/endeavoru-panel.c
@@ -117,6 +117,18 @@ static int endeavoru_panel_set_backlight(struct udevice *dev, int percent)
 	struct endeavoru_panel_priv *priv = dev_get_priv(dev);
 	int ret;
 
+	/*
+	 * Due to the use of the Tegra DC backlight feature, backlight
+	 * requests MUST NOT be made during probe or earlier. This is
+	 * because it creates a loop, as the backlight is a DC child.
+	 */
+	ret = uclass_get_device_by_phandle(UCLASS_PANEL_BACKLIGHT, dev,
+					   "backlight", &priv->backlight);
+	if (ret) {
+		log_err("cannot get backlight: ret = %d\n", ret);
+		return ret;
+	}
+
 	ret = backlight_enable(priv->backlight);
 	if (ret)
 		return ret;
@@ -136,13 +148,6 @@ static int endeavoru_panel_of_to_plat(struct udevice *dev)
 	struct endeavoru_panel_priv *priv = dev_get_priv(dev);
 	int ret;
 
-	ret = uclass_get_device_by_phandle(UCLASS_PANEL_BACKLIGHT, dev,
-					   "backlight", &priv->backlight);
-	if (ret) {
-		log_err("cannot get backlight: ret = %d\n", ret);
-		return ret;
-	}
-
 	ret = uclass_get_device_by_phandle(UCLASS_REGULATOR, dev,
 					   "vdd-supply", &priv->vdd);
 	if (ret) {
@@ -231,7 +236,7 @@ static int endeavoru_panel_probe(struct udevice *dev)
 	/* fill characteristics of DSI data link */
 	plat->lanes = 2;
 	plat->format = MIPI_DSI_FMT_RGB888;
-	plat->mode_flags = MIPI_DSI_MODE_VIDEO;
+	plat->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_LPM;
 
 	return endeavoru_panel_hw_init(dev);
 }
diff --git a/drivers/video/lg-ld070wx3.c b/drivers/video/lg-ld070wx3.c
index 610a06ffe7b..3676e45bc65 100644
--- a/drivers/video/lg-ld070wx3.c
+++ b/drivers/video/lg-ld070wx3.c
@@ -158,7 +158,7 @@ static int lg_ld070wx3_probe(struct udevice *dev)
 	/* fill characteristics of DSI data link */
 	plat->lanes = 4;
 	plat->format = MIPI_DSI_FMT_RGB888;
-	plat->mode_flags = MIPI_DSI_MODE_VIDEO;
+	plat->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_LPM;
 
 	return lg_ld070wx3_hw_init(dev);
 }
diff --git a/drivers/video/lm3533_backlight.c b/drivers/video/lm3533_backlight.c
index 6b51fa0628e..7b87b6bd40b 100644
--- a/drivers/video/lm3533_backlight.c
+++ b/drivers/video/lm3533_backlight.c
@@ -7,6 +7,7 @@
 
 #include <backlight.h>
 #include <dm.h>
+#include <dm/ofnode.h>
 #include <i2c.h>
 #include <log.h>
 #include <linux/delay.h>
@@ -17,56 +18,79 @@
 #define LM3533_BL_MAX_BRIGHTNESS			0xFF
 
 #define LM3533_SINK_OUTPUT_CONFIG_1			0x10
-#define LM3533_CONTROL_BANK_A_PWM			0x14
+#define LM3533_CONTROL_PWM_BASE				0x14
+#define   PWM_MAX					GENMASK(5, 0)
 #define LM3533_CONTROL_BANK_AB_BRIGHTNESS		0x1A
-#define LM3533_CONTROL_BANK_A_FULLSCALE_CURRENT		0x1F
+#define LM3533_CONTROL_FULLSCALE_CURRENT_BASE		0x1F
+#define   MAX_CURRENT_MIN				5000
+#define   MAX_CURRENT_MAX				29800
+#define   MAX_CURRENT_STEP				800
 #define LM3533_CONTROL_BANK_ENABLE			0x27
 #define LM3533_OVP_FREQUENCY_PWM_POLARITY		0x2C
+#define   BOOST_OVP_MASK				GENMASK(2, 1)
+#define   BOOST_OVP_SHIFT				1
+#define   BOOST_FREQ_MASK				BIT(0)
+#define   BOOST_FREQ_SHIFT				0
 #define LM3533_BRIGHTNESS_REGISTER_A			0x40
 
+#define LM3533_BOOST_OVP_16V				16000000UL
+#define LM3533_BOOST_FREQ_500KHZ			500000UL
+
 struct lm3533_backlight_priv {
 	struct gpio_desc enable_gpio;
 	u32 def_bl_lvl;
+
+	/* Core */
+	u32 boost_ovp;
+	u32 boost_freq;
+
+	/* Backlight */
+	u32 reg;
+	u16 max_current;		/* 5000 - 29800 uA (800 uA step) */
+	u8 pwm;				/* 0 - 0x3f */
+	bool linear;
+	bool hvled;
 };
 
 static int lm3533_backlight_enable(struct udevice *dev)
 {
 	struct lm3533_backlight_priv *priv = dev_get_priv(dev);
+	u8 val, id = priv->reg;
 	int ret;
 
-	dm_gpio_set_value(&priv->enable_gpio, 1);
-	mdelay(5);
+	if (priv->linear) {
+		ret = dm_i2c_reg_clrset(dev, LM3533_CONTROL_BANK_AB_BRIGHTNESS,
+					BIT(2 * id + 1), BIT(2 * id + 1));
+		if (ret)
+			return ret;
+	}
 
-	/* HVLED 1 & 2 are controlled by Bank A */
-	ret = dm_i2c_reg_write(dev, LM3533_SINK_OUTPUT_CONFIG_1, 0x00);
-	if (ret)
-		return ret;
+	if (priv->hvled) {
+		ret = dm_i2c_reg_clrset(dev, LM3533_SINK_OUTPUT_CONFIG_1,
+					BIT(0) | BIT(1), id | id << 1);
+		if (ret)
+			return ret;
+	}
 
-	/* PWM input is disabled for CABC */
-	ret = dm_i2c_reg_write(dev, LM3533_CONTROL_BANK_A_PWM, 0x00);
-	if (ret)
-		return ret;
+	/* Set current */
+	if (priv->max_current < MAX_CURRENT_MIN || priv->max_current > MAX_CURRENT_MAX)
+		return -EINVAL;
 
-	/* Linear & Control Bank A is configured for register Current control */
-	ret = dm_i2c_reg_write(dev, LM3533_CONTROL_BANK_AB_BRIGHTNESS, 0x02);
+	val = (priv->max_current - MAX_CURRENT_MIN) / MAX_CURRENT_STEP;
+	ret = dm_i2c_reg_write(dev, LM3533_CONTROL_FULLSCALE_CURRENT_BASE + id, val);
 	if (ret)
 		return ret;
 
-	/* Full-Scale Current (20.2mA) */
-	ret = dm_i2c_reg_write(dev, LM3533_CONTROL_BANK_A_FULLSCALE_CURRENT, 0x13);
-	if (ret)
-		return ret;
+	/* Set PWM mask */
+	if (priv->pwm > PWM_MAX)
+		return -EINVAL;
 
-	/* Control Bank A is enable */
-	ret = dm_i2c_reg_write(dev, LM3533_CONTROL_BANK_ENABLE, 0x01);
+	ret = dm_i2c_reg_write(dev, LM3533_CONTROL_PWM_BASE + id, priv->pwm);
 	if (ret)
 		return ret;
 
-	ret = dm_i2c_reg_write(dev, LM3533_OVP_FREQUENCY_PWM_POLARITY, 0x0A);
-	if (ret)
-		return ret;
-
-	return 0;
+	/* Enable Control Bank */
+	return dm_i2c_reg_clrset(dev, LM3533_CONTROL_BANK_ENABLE, BIT(id), BIT(id));
 }
 
 static int lm3533_backlight_set_brightness(struct udevice *dev, int percent)
@@ -92,6 +116,56 @@ static int lm3533_backlight_set_brightness(struct udevice *dev, int percent)
 	return 0;
 }
 
+static int lm3533_backlight_of_to_plat(struct udevice *dev)
+{
+	struct lm3533_backlight_priv *priv = dev_get_priv(dev);
+	ofnode child;
+	int ret;
+
+	ret = gpio_request_by_name(dev, "enable-gpios", 0,
+				   &priv->enable_gpio, GPIOD_IS_OUT);
+	if (ret) {
+		log_err("Could not decode enable-gpios (%d)\n", ret);
+		return ret;
+	}
+
+	priv->boost_ovp = dev_read_u32_default(dev, "ti,boost-ovp-microvolt",
+					       LM3533_BOOST_OVP_16V);
+
+	/* boost_ovp is defined in microvolts, convert to enum value */
+	priv->boost_ovp = priv->boost_ovp / (8 * 1000 * 1000) - 2;
+
+	priv->boost_freq = dev_read_u32_default(dev, "ti,boost-freq-hz",
+						LM3533_BOOST_FREQ_500KHZ);
+
+	/* boost_freq is defined in Hz, convert to enum value */
+	priv->boost_freq = priv->boost_freq / (500 * 1000) - 1;
+
+	/* Backlight is one of children but has no dedicated driver */
+	ofnode_for_each_subnode(child, dev_ofnode(dev)) {
+		if (ofnode_device_is_compatible(child, "ti,lm3533-backlight")) {
+			const char *node_name = ofnode_get_name(child);
+
+			if (!strcmp(&node_name[10], "1"))
+				priv->reg = 1;
+			else
+				priv->reg = 0;
+
+			priv->max_current = ofnode_read_u32_default(child, "ti,max-current-microamp",
+								    5000);
+			priv->pwm = ofnode_read_u32_default(child, "ti,pwm-config-mask", 0);
+
+			priv->def_bl_lvl = ofnode_read_u32_default(child, "default-brightness",
+								   LM3533_BL_MAX_BRIGHTNESS);
+
+			priv->linear = ofnode_read_bool(child, "ti,linear-mapping-mode");
+			priv->hvled = ofnode_read_bool(child, "ti,hardware-controlled");
+		}
+	}
+
+	return 0;
+}
+
 static int lm3533_backlight_probe(struct udevice *dev)
 {
 	struct lm3533_backlight_priv *priv = dev_get_priv(dev);
@@ -100,15 +174,22 @@ static int lm3533_backlight_probe(struct udevice *dev)
 	if (device_get_uclass_id(dev->parent) != UCLASS_I2C)
 		return -EPROTONOSUPPORT;
 
-	ret = gpio_request_by_name(dev, "enable-gpios", 0,
-				   &priv->enable_gpio, GPIOD_IS_OUT);
+	dm_gpio_set_value(&priv->enable_gpio, 1);
+	mdelay(5);
+
+	ret = dm_i2c_reg_clrset(dev, LM3533_OVP_FREQUENCY_PWM_POLARITY,
+				BOOST_FREQ_MASK, priv->boost_freq << BOOST_FREQ_SHIFT);
 	if (ret) {
-		log_err("Could not decode enable-gpios (%d)\n", ret);
+		log_debug("%s: freq config failed %d\n", __func__, ret);
 		return ret;
 	}
 
-	priv->def_bl_lvl = dev_read_u32_default(dev, "default-brightness-level",
-						LM3533_BL_MAX_BRIGHTNESS);
+	ret = dm_i2c_reg_clrset(dev, LM3533_OVP_FREQUENCY_PWM_POLARITY,
+				BOOST_OVP_MASK, priv->boost_ovp << BOOST_OVP_SHIFT);
+	if (ret) {
+		log_debug("%s: ovp config failed %d\n", __func__, ret);
+		return ret;
+	}
 
 	return 0;
 }
@@ -127,6 +208,7 @@ U_BOOT_DRIVER(lm3533_backlight) = {
 	.name		= "lm3533_backlight",
 	.id		= UCLASS_PANEL_BACKLIGHT,
 	.of_match	= lm3533_backlight_ids,
+	.of_to_plat	= lm3533_backlight_of_to_plat,
 	.probe		= lm3533_backlight_probe,
 	.ops		= &lm3533_backlight_ops,
 	.priv_auto	= sizeof(struct lm3533_backlight_priv),
diff --git a/drivers/video/lp855x_backlight.c b/drivers/video/lp855x_backlight.c
new file mode 100644
index 00000000000..5debc0aa453
--- /dev/null
+++ b/drivers/video/lp855x_backlight.c
@@ -0,0 +1,302 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2011 Texas Instruments
+ * Copyright (c) 2024 Svyatoslav Ryhel <clamor95@gmail.com>
+ */
+
+#define LOG_CATEGORY UCLASS_PANEL_BACKLIGHT
+
+#include <malloc.h>
+#include <backlight.h>
+#include <dm.h>
+#include <dm/devres.h>
+#include <i2c.h>
+#include <log.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <asm/gpio.h>
+#include <power/regulator.h>
+
+#define LP855x_MIN_BRIGHTNESS		0x00
+#define LP855x_MAX_BRIGHTNESS		0xff
+
+/* LP8550/1/2/3/6 Registers */
+#define LP855X_BRIGHTNESS_CTRL		0x00
+#define LP855X_DEVICE_CTRL		0x01
+#define LP855X_EEPROM_START		0xa0
+#define LP855X_EEPROM_END		0xa7
+#define LP8556_EPROM_START		0x98
+#define LP8556_EPROM_END		0xaf
+
+/* LP8555/7 Registers */
+#define LP8557_BL_CMD			0x00
+#define LP8557_BL_MASK			0x01
+#define LP8557_BL_ON			0x01
+#define LP8557_BL_OFF			0x00
+#define LP8557_BRIGHTNESS_CTRL		0x04
+#define LP8557_CONFIG			0x10
+#define LP8555_EPROM_START		0x10
+#define LP8555_EPROM_END		0x7a
+#define LP8557_EPROM_START		0x10
+#define LP8557_EPROM_END		0x1e
+
+struct lp855x_rom_data {
+	u8 addr;
+	u8 val;
+};
+
+struct lp855x_backlight_priv;
+
+/*
+ * struct lp855x_device_config
+ * @pre_init_device: init device function call before updating the brightness
+ * @reg_brightness: register address for brigthenss control
+ * @reg_devicectrl: register address for device control
+ * @post_init_device: late init device function call
+ */
+struct lp855x_device_config {
+	int (*pre_init_device)(struct udevice *dev);
+	u8 reg_brightness;
+	u8 reg_devicectrl;
+	u8 reg_eepromstart;
+	u8 reg_eepromend;
+	int (*post_init_device)(struct udevice *dev);
+};
+
+struct lp855x_backlight_priv {
+	struct udevice *supply;	/* regulator for VDD input */
+	struct udevice *enable;	/* regulator for EN/VDDIO input */
+
+	u8 device_control;
+	u8 initial_brightness;
+
+	int size_program;
+	struct lp855x_rom_data *rom_data;
+	struct lp855x_device_config *cfg;
+};
+
+static int lp855x_backlight_enable(struct udevice *dev)
+{
+	struct lp855x_backlight_priv *priv = dev_get_priv(dev);
+	int ret;
+
+	ret = regulator_set_enable_if_allowed(priv->supply, 1);
+	if (ret) {
+		log_debug("%s: enabling power-supply failed (%d)\n",
+			  __func__, ret);
+		return ret;
+	}
+
+	ret = regulator_set_enable_if_allowed(priv->enable, 1);
+	if (ret) {
+		log_debug("%s: enabling enable-supply failed (%d)\n",
+			  __func__, ret);
+		return ret;
+	}
+	mdelay(2);
+
+	if (priv->cfg->pre_init_device) {
+		ret = priv->cfg->pre_init_device(dev);
+		if (ret) {
+			log_debug("%s: pre init device err: %d\n",
+				  __func__, ret);
+			return ret;
+		}
+	}
+
+	ret = dm_i2c_reg_write(dev, priv->cfg->reg_brightness,
+			       priv->initial_brightness);
+	if (ret)
+		return ret;
+
+	ret = dm_i2c_reg_write(dev, priv->cfg->reg_devicectrl,
+			       priv->device_control);
+	if (ret)
+		return ret;
+
+	if (priv->size_program > 0) {
+		int i;
+		u8 val, addr;
+
+		for (i = 0; i < priv->size_program; i++) {
+			addr = priv->rom_data[i].addr;
+			val = priv->rom_data[i].val;
+
+			if (addr < priv->cfg->reg_eepromstart &&
+			    addr > priv->cfg->reg_eepromend)
+				continue;
+
+			ret = dm_i2c_reg_write(dev, addr, val);
+			if (ret)
+				return ret;
+		}
+	}
+
+	if (priv->cfg->post_init_device) {
+		ret = priv->cfg->post_init_device(dev);
+		if (ret) {
+			log_debug("%s: post init device err: %d\n",
+				  __func__, ret);
+			return ret;
+		}
+	}
+
+	return 0;
+}
+
+static int lp855x_backlight_set_brightness(struct udevice *dev, int percent)
+{
+	struct lp855x_backlight_priv *priv = dev_get_priv(dev);
+
+	if (percent == BACKLIGHT_DEFAULT)
+		percent = priv->initial_brightness;
+
+	if (percent < LP855x_MIN_BRIGHTNESS)
+		percent = LP855x_MIN_BRIGHTNESS;
+
+	if (percent > LP855x_MAX_BRIGHTNESS)
+		percent = LP855x_MAX_BRIGHTNESS;
+
+	/* Set brightness level */
+	return dm_i2c_reg_write(dev, priv->cfg->reg_brightness,
+				percent);
+}
+
+static int lp855x_backlight_probe(struct udevice *dev)
+{
+	struct lp855x_backlight_priv *priv = dev_get_priv(dev);
+	int rom_length, ret;
+
+	if (device_get_uclass_id(dev->parent) != UCLASS_I2C)
+		return -EPROTONOSUPPORT;
+
+	priv->cfg = (struct lp855x_device_config *)dev_get_driver_data(dev);
+
+	dev_read_u8(dev, "dev-ctrl", &priv->device_control);
+	dev_read_u8(dev, "init-brt", &priv->initial_brightness);
+
+	/* Fill ROM platform data if defined */
+	rom_length = dev_get_child_count(dev);
+	if (rom_length > 0) {
+		struct lp855x_rom_data *rom;
+		ofnode child;
+		int i = 0;
+
+		rom = devm_kcalloc(dev, rom_length, sizeof(*rom), GFP_KERNEL);
+		if (!rom)
+			return -ENOMEM;
+
+		dev_for_each_subnode(child, dev) {
+			ofnode_read_u8(child, "rom-addr", &rom[i].addr);
+			ofnode_read_u8(child, "rom-val", &rom[i].val);
+			i++;
+		}
+
+		priv->size_program = rom_length;
+		priv->rom_data = &rom[0];
+	}
+
+	ret = uclass_get_device_by_phandle(UCLASS_REGULATOR, dev,
+					   "power-supply", &priv->supply);
+	if (ret) {
+		log_err("%s: cannot get power-supply: ret = %d\n", __func__, ret);
+		return ret;
+	}
+
+	ret = uclass_get_device_by_phandle(UCLASS_REGULATOR, dev,
+					   "enable-supply", &priv->enable);
+	if (ret) {
+		log_err("%s: cannot get enable-supply: ret = %d\n", __func__, ret);
+		return ret;
+	}
+
+	return 0;
+}
+
+static const struct backlight_ops lp855x_backlight_ops = {
+	.enable = lp855x_backlight_enable,
+	.set_brightness = lp855x_backlight_set_brightness,
+};
+
+static int lp8556_bl_rst(struct udevice *dev)
+{
+	int ret;
+
+	/* Reset backlight after updating EPROM settings */
+	ret = dm_i2c_reg_clrset(dev, LP855X_DEVICE_CTRL, LP8557_BL_MASK,
+				LP8557_BL_OFF);
+	if (ret)
+		return ret;
+
+	mdelay(10);
+
+	return dm_i2c_reg_clrset(dev, LP855X_DEVICE_CTRL, LP8557_BL_MASK,
+				 LP8557_BL_ON);
+}
+
+static int lp8557_bl_off(struct udevice *dev)
+{
+	/* BL_ON = 0 before updating EPROM settings */
+	return dm_i2c_reg_clrset(dev, LP8557_BL_CMD, LP8557_BL_MASK,
+				 LP8557_BL_OFF);
+}
+
+static int lp8557_bl_on(struct udevice *dev)
+{
+	/* BL_ON = 1 after updating EPROM settings */
+	return dm_i2c_reg_clrset(dev, LP8557_BL_CMD, LP8557_BL_MASK,
+				 LP8557_BL_ON);
+}
+
+static struct lp855x_device_config lp855x_dev_cfg = {
+	.reg_brightness = LP855X_BRIGHTNESS_CTRL,
+	.reg_devicectrl = LP855X_DEVICE_CTRL,
+	.reg_eepromstart = LP855X_EEPROM_START,
+	.reg_eepromend = LP855X_EEPROM_END,
+};
+
+static struct lp855x_device_config lp8555_dev_cfg = {
+	.reg_brightness = LP8557_BRIGHTNESS_CTRL,
+	.reg_devicectrl = LP8557_CONFIG,
+	.reg_eepromstart = LP8555_EPROM_START,
+	.reg_eepromend = LP8555_EPROM_END,
+	.pre_init_device = lp8557_bl_off,
+	.post_init_device = lp8557_bl_on,
+};
+
+static struct lp855x_device_config lp8556_dev_cfg = {
+	.reg_brightness = LP855X_BRIGHTNESS_CTRL,
+	.reg_devicectrl = LP855X_DEVICE_CTRL,
+	.reg_eepromstart = LP8556_EPROM_START,
+	.reg_eepromend = LP8556_EPROM_END,
+	.post_init_device = lp8556_bl_rst,
+};
+
+static struct lp855x_device_config lp8557_dev_cfg = {
+	.reg_brightness = LP8557_BRIGHTNESS_CTRL,
+	.reg_devicectrl = LP8557_CONFIG,
+	.reg_eepromstart = LP8557_EPROM_START,
+	.reg_eepromend = LP8557_EPROM_END,
+	.pre_init_device = lp8557_bl_off,
+	.post_init_device = lp8557_bl_on,
+};
+
+static const struct udevice_id lp855x_backlight_ids[] = {
+	{ .compatible = "ti,lp8550", .data = (ulong)&lp855x_dev_cfg },
+	{ .compatible = "ti,lp8551", .data = (ulong)&lp855x_dev_cfg },
+	{ .compatible = "ti,lp8552", .data = (ulong)&lp855x_dev_cfg },
+	{ .compatible = "ti,lp8553", .data = (ulong)&lp855x_dev_cfg },
+	{ .compatible = "ti,lp8555", .data = (ulong)&lp8555_dev_cfg },
+	{ .compatible = "ti,lp8556", .data = (ulong)&lp8556_dev_cfg },
+	{ .compatible = "ti,lp8557", .data = (ulong)&lp8557_dev_cfg },
+	{ }
+};
+
+U_BOOT_DRIVER(lp855x_backlight) = {
+	.name		= "lp855x_backlight",
+	.id		= UCLASS_PANEL_BACKLIGHT,
+	.of_match	= lp855x_backlight_ids,
+	.probe		= lp855x_backlight_probe,
+	.ops		= &lp855x_backlight_ops,
+	.priv_auto	= sizeof(struct lp855x_backlight_priv),
+};
diff --git a/drivers/video/renesas-r61307.c b/drivers/video/renesas-r61307.c
index a3697bce5ee..ef6fab1e953 100644
--- a/drivers/video/renesas-r61307.c
+++ b/drivers/video/renesas-r61307.c
@@ -254,17 +254,17 @@ static int renesas_r61307_hw_init(struct udevice *dev)
 		return ret;
 	}
 
-	ret = dm_gpio_set_value(&priv->reset_gpio, 0);
+	ret = dm_gpio_set_value(&priv->reset_gpio, 1);
 	if (ret) {
-		log_debug("%s: changing reset-gpio failed (%d)\n",
+		log_debug("%s: entering reset failed (%d)\n",
 			  __func__, ret);
 		return ret;
 	}
 	mdelay(5);
 
-	ret = dm_gpio_set_value(&priv->reset_gpio, 1);
+	ret = dm_gpio_set_value(&priv->reset_gpio, 0);
 	if (ret) {
-		log_debug("%s: changing reset-gpio failed (%d)\n",
+		log_debug("%s: exiting reset failed (%d)\n",
 			  __func__, ret);
 		return ret;
 	}
@@ -281,7 +281,8 @@ static int renesas_r61307_probe(struct udevice *dev)
 	/* fill characteristics of DSI data link */
 	plat->lanes = 4;
 	plat->format = MIPI_DSI_FMT_RGB888;
-	plat->mode_flags = MIPI_DSI_MODE_VIDEO;
+	plat->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
+			   MIPI_DSI_CLOCK_NON_CONTINUOUS | MIPI_DSI_MODE_LPM;
 
 	return renesas_r61307_hw_init(dev);
 }
@@ -294,7 +295,7 @@ static const struct panel_ops renesas_r61307_ops = {
 
 static const struct udevice_id renesas_r61307_ids[] = {
 	{ .compatible = "koe,tx13d100vm0eaa" },
-	{ .compatible = "hitachi,tx13d100vm0eaa" },
+	{ .compatible = "hit,tx13d100vm0eaa" },
 	{ }
 };
 
diff --git a/drivers/video/renesas-r69328.c b/drivers/video/renesas-r69328.c
index 9861c3fef11..0954b04b62e 100644
--- a/drivers/video/renesas-r69328.c
+++ b/drivers/video/renesas-r69328.c
@@ -32,9 +32,11 @@
 #define R69328_POWER_SET	0xD1
 
 struct renesas_r69328_priv {
+	struct udevice *vdd;
+	struct udevice *vddio;
+
 	struct udevice *backlight;
 
-	struct gpio_desc enable_gpio;
 	struct gpio_desc reset_gpio;
 };
 
@@ -159,10 +161,15 @@ static int renesas_r69328_of_to_plat(struct udevice *dev)
 		return ret;
 	}
 
-	ret = gpio_request_by_name(dev, "enable-gpios", 0,
-				   &priv->enable_gpio, GPIOD_IS_OUT);
+	ret = device_get_supply_regulator(dev, "vdd-supply", &priv->vdd);
 	if (ret) {
-		log_err("could not decode enable-gpios (%d)\n", ret);
+		log_err("Cannot get vdd-supply: ret = %d\n", ret);
+		return ret;
+	}
+
+	ret = device_get_supply_regulator(dev, "vddio-supply", &priv->vddio);
+	if (ret) {
+		log_err("Cannot get vddio-supply: ret = %d\n", ret);
 		return ret;
 	}
 
@@ -181,25 +188,32 @@ static int renesas_r69328_hw_init(struct udevice *dev)
 	struct renesas_r69328_priv *priv = dev_get_priv(dev);
 	int ret;
 
-	ret = dm_gpio_set_value(&priv->enable_gpio, 1);
+	ret = regulator_set_enable_if_allowed(priv->vddio, 1);
 	if (ret) {
-		log_debug("%s: error changing enable-gpios (%d)\n",
+		log_debug("%s: enabling vddio-supply failed (%d)\n",
 			  __func__, ret);
 		return ret;
 	}
 	mdelay(5);
 
-	ret = dm_gpio_set_value(&priv->reset_gpio, 0);
+	ret = regulator_set_enable_if_allowed(priv->vdd, 1);
 	if (ret) {
-		log_debug("%s: error changing reset-gpios (%d)\n",
+		log_debug("%s: enabling vdd-supply failed (%d)\n",
 			  __func__, ret);
 		return ret;
 	}
-	mdelay(5);
 
 	ret = dm_gpio_set_value(&priv->reset_gpio, 1);
 	if (ret) {
-		log_debug("%s: error changing reset-gpios (%d)\n",
+		log_debug("%s: error entering reset (%d)\n",
+			  __func__, ret);
+		return ret;
+	}
+	mdelay(5);
+
+	ret = dm_gpio_set_value(&priv->reset_gpio, 0);
+	if (ret) {
+		log_debug("%s: error exiting reset (%d)\n",
 			  __func__, ret);
 		return ret;
 	}
@@ -216,7 +230,8 @@ static int renesas_r69328_probe(struct udevice *dev)
 	/* fill characteristics of DSI data link */
 	plat->lanes = 4;
 	plat->format = MIPI_DSI_FMT_RGB888;
-	plat->mode_flags = MIPI_DSI_MODE_VIDEO;
+	plat->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
+			   MIPI_DSI_CLOCK_NON_CONTINUOUS | MIPI_DSI_MODE_LPM;
 
 	return renesas_r69328_hw_init(dev);
 }
diff --git a/drivers/video/samsung-ltl106hl02.c b/drivers/video/samsung-ltl106hl02.c
index 5e6c11c4be3..1efc9fca610 100644
--- a/drivers/video/samsung-ltl106hl02.c
+++ b/drivers/video/samsung-ltl106hl02.c
@@ -129,7 +129,7 @@ static int samsung_ltl106hl02_probe(struct udevice *dev)
 	/* fill characteristics of DSI data link */
 	plat->lanes = 4;
 	plat->format = MIPI_DSI_FMT_RGB888;
-	plat->mode_flags = MIPI_DSI_MODE_VIDEO;
+	plat->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_LPM;
 
 	return samsung_ltl106hl02_hw_init(dev);
 }
diff --git a/drivers/video/sharp-lq079l1sx01.c b/drivers/video/sharp-lq079l1sx01.c
new file mode 100644
index 00000000000..a8197f40fc7
--- /dev/null
+++ b/drivers/video/sharp-lq079l1sx01.c
@@ -0,0 +1,288 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Sharp LQ079L1SX01 DSI panel driver
+ *
+ * Copyright (c) 2024 Svyatoslav Ryhel <clamor95@gmail.com>
+ */
+
+#include <backlight.h>
+#include <dm.h>
+#include <panel.h>
+#include <log.h>
+#include <mipi_dsi.h>
+#include <linux/delay.h>
+#include <asm/gpio.h>
+#include <power/regulator.h>
+
+struct sharp_lq079l1sx01_priv {
+	struct udevice *backlight;
+	struct udevice *panel_sec;
+
+	struct udevice *avdd;
+	struct udevice *vddio;
+	struct udevice *vsp;
+	struct udevice *vsn;
+
+	struct gpio_desc reset_gpio;
+};
+
+static struct display_timing default_timing = {
+	.pixelclock.typ		= 215000000,
+	.hactive.typ		= 1536,
+	.hfront_porch.typ	= 136,
+	.hback_porch.typ	= 28,
+	.hsync_len.typ		= 28,
+	.vactive.typ		= 2048,
+	.vfront_porch.typ	= 14,
+	.vback_porch.typ	= 8,
+	.vsync_len.typ		= 2,
+};
+
+static int dcs_write_one(struct mipi_dsi_device *dsi, u8 cmd, u8 data)
+{
+	return mipi_dsi_dcs_write(dsi, cmd, &data, 1);
+}
+
+static int sharp_lq079l1sx01_configure_link(struct udevice *dev)
+{
+	struct mipi_dsi_panel_plat *plat = dev_get_plat(dev);
+	struct mipi_dsi_device *dsi = plat->device;
+	int ret;
+
+	ret = mipi_dsi_dcs_exit_sleep_mode(dsi);
+	if (ret < 0) {
+		log_debug("%s: failed to exit sleep mode %s: %d\n",
+			  __func__, dev->parent->name, ret);
+	}
+	mdelay(120);
+
+	ret = dcs_write_one(dsi, MIPI_DCS_SET_DISPLAY_BRIGHTNESS, 0xff);
+	if (ret < 0) {
+		log_debug("%s: failed to SET_DISPLAY_BRIGHTNESS %s: %d\n",
+			  __func__, dev->parent->name, ret);
+	}
+	ret = dcs_write_one(dsi, MIPI_DCS_WRITE_POWER_SAVE, 0x01);
+	if (ret < 0) {
+		log_debug("%s: failed to WRITE_POWER_SAVE %s: %d\n",
+			  __func__, dev->parent->name, ret);
+	}
+	ret = dcs_write_one(dsi, MIPI_DCS_WRITE_CONTROL_DISPLAY, 0x2c);
+	if (ret < 0) {
+		log_debug("%s: failed to WRITE_CONTROL_DISPLAY %s: %d\n",
+			  __func__, dev->parent->name, ret);
+	}
+
+	ret = mipi_dsi_dcs_set_display_on(dsi);
+	if (ret < 0) {
+		log_debug("%s: failed to set panel on %s: %d\n",
+			  __func__, dev->parent->name, ret);
+	}
+
+	return 0;
+}
+
+static int sharp_lq079l1sx01_enable_backlight(struct udevice *dev)
+{
+	struct sharp_lq079l1sx01_priv *priv = dev_get_priv(dev);
+
+	if (!priv->panel_sec)
+		return 0;
+
+	sharp_lq079l1sx01_configure_link(dev);
+	sharp_lq079l1sx01_configure_link(priv->panel_sec);
+
+	return 0;
+}
+
+static int sharp_lq079l1sx01_set_backlight(struct udevice *dev, int percent)
+{
+	struct sharp_lq079l1sx01_priv *priv = dev_get_priv(dev);
+	int ret;
+
+	if (!priv->panel_sec)
+		return 0;
+
+	ret = backlight_enable(priv->backlight);
+	if (ret)
+		return ret;
+
+	return backlight_set_brightness(priv->backlight, percent);
+}
+
+static int sharp_lq079l1sx01_timings(struct udevice *dev,
+				     struct display_timing *timing)
+{
+	memcpy(timing, &default_timing, sizeof(*timing));
+	return 0;
+}
+
+static int sharp_lq079l1sx01_of_to_plat(struct udevice *dev)
+{
+	struct sharp_lq079l1sx01_priv *priv = dev_get_priv(dev);
+	int ret;
+
+	/* If node has no link2 it is secondary panel */
+	if (!dev_read_bool(dev, "link2"))
+		return 0;
+
+	ret = uclass_get_device_by_phandle(UCLASS_PANEL, dev,
+					   "link2", &priv->panel_sec);
+	if (ret) {
+		log_debug("%s: cannot get secondary panel: ret = %d\n",
+			  __func__, ret);
+		return ret;
+	}
+
+	ret = uclass_get_device_by_phandle(UCLASS_PANEL_BACKLIGHT, dev,
+					   "backlight", &priv->backlight);
+	if (ret) {
+		log_debug("%s: cannot get backlight: ret = %d\n",
+			  __func__, ret);
+		return ret;
+	}
+
+	ret = uclass_get_device_by_phandle(UCLASS_REGULATOR, dev,
+					   "avdd-supply", &priv->avdd);
+	if (ret) {
+		log_debug("%s: cannot get avdd-supply: ret = %d\n",
+			  __func__, ret);
+		return ret;
+	}
+
+	ret = uclass_get_device_by_phandle(UCLASS_REGULATOR, dev,
+					   "vddio-supply", &priv->vddio);
+	if (ret) {
+		log_debug("%s: cannot get vddio-supply: ret = %d\n",
+			  __func__, ret);
+		return ret;
+	}
+
+	ret = uclass_get_device_by_phandle(UCLASS_REGULATOR, dev,
+					   "vsp-supply", &priv->vsp);
+	if (ret) {
+		log_debug("%s: cannot get vsp-supply: ret = %d\n",
+			  __func__, ret);
+		return ret;
+	}
+
+	ret = uclass_get_device_by_phandle(UCLASS_REGULATOR, dev,
+					   "vsn-supply", &priv->vsn);
+	if (ret) {
+		log_debug("%s: cannot get vsn-supply: ret = %d\n",
+			  __func__, ret);
+		return ret;
+	}
+
+	ret = gpio_request_by_name(dev, "reset-gpios", 0,
+				   &priv->reset_gpio, GPIOD_IS_OUT);
+	if (ret) {
+		log_debug("%s: cannot get reser-gpios (%d)\n",
+			  __func__, ret);
+		return ret;
+	}
+
+	return 0;
+}
+
+static int sharp_lq079l1sx01_hw_init(struct udevice *dev)
+{
+	struct sharp_lq079l1sx01_priv *priv = dev_get_priv(dev);
+	int ret;
+
+	if (!priv->panel_sec)
+		return 0;
+
+	ret = regulator_set_enable_if_allowed(priv->vddio, 1);
+	if (ret) {
+		log_debug("%s: enabling vddio-supply failed (%d)\n",
+			  __func__, ret);
+		return ret;
+	}
+
+	ret = regulator_set_enable_if_allowed(priv->avdd, 1);
+	if (ret) {
+		log_debug("%s: enabling avdd-supply failed (%d)\n",
+			  __func__, ret);
+		return ret;
+	}
+
+	mdelay(12);
+
+	ret = regulator_set_enable_if_allowed(priv->vsp, 1);
+	if (ret) {
+		log_debug("%s: enabling vsp-supply failed (%d)\n",
+			  __func__, ret);
+		return ret;
+	}
+
+	mdelay(12);
+
+	ret = regulator_set_enable_if_allowed(priv->vsn, 1);
+	if (ret) {
+		log_debug("%s: enabling vsn-supply failed (%d)\n",
+			  __func__, ret);
+		return ret;
+	}
+
+	mdelay(24);
+
+	ret = dm_gpio_set_value(&priv->reset_gpio, 0);
+	if (ret) {
+		log_debug("%s: error disabling reset-gpios (%d)\n",
+			  __func__, ret);
+		return ret;
+	}
+	udelay(3);
+
+	ret = dm_gpio_set_value(&priv->reset_gpio, 1);
+	if (ret) {
+		log_debug("%s: error enabling reset-gpios (%d)\n",
+			  __func__, ret);
+		return ret;
+	}
+	udelay(3);
+
+	ret = dm_gpio_set_value(&priv->reset_gpio, 0);
+	if (ret) {
+		log_debug("%s: error disabling reset-gpios (%d)\n",
+			  __func__, ret);
+		return ret;
+	}
+	mdelay(32);
+
+	return 0;
+}
+
+static int sharp_lq079l1sx01_probe(struct udevice *dev)
+{
+	struct mipi_dsi_panel_plat *plat = dev_get_plat(dev);
+
+	/* fill characteristics of DSI data link */
+	plat->lanes = 4;
+	plat->format = MIPI_DSI_FMT_RGB888;
+	plat->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_LPM;
+
+	return sharp_lq079l1sx01_hw_init(dev);
+}
+
+static const struct panel_ops sharp_lq079l1sx01_ops = {
+	.enable_backlight	= sharp_lq079l1sx01_enable_backlight,
+	.set_backlight		= sharp_lq079l1sx01_set_backlight,
+	.get_display_timing	= sharp_lq079l1sx01_timings,
+};
+
+static const struct udevice_id sharp_lq079l1sx01_ids[] = {
+	{ .compatible = "sharp,lq079l1sx01" },
+	{ }
+};
+
+U_BOOT_DRIVER(sharp_lq079l1sx01) = {
+	.name		= "sharp_lq079l1sx01",
+	.id		= UCLASS_PANEL,
+	.of_match	= sharp_lq079l1sx01_ids,
+	.ops		= &sharp_lq079l1sx01_ops,
+	.of_to_plat	= sharp_lq079l1sx01_of_to_plat,
+	.probe		= sharp_lq079l1sx01_probe,
+	.plat_auto	= sizeof(struct mipi_dsi_panel_plat),
+	.priv_auto	= sizeof(struct sharp_lq079l1sx01_priv),
+};
diff --git a/drivers/video/sharp-lq101r1sx01.c b/drivers/video/sharp-lq101r1sx01.c
index 5d8453fd796..4fdf0da8a94 100644
--- a/drivers/video/sharp-lq101r1sx01.c
+++ b/drivers/video/sharp-lq101r1sx01.c
@@ -255,6 +255,7 @@ static int sharp_lq101r1sx01_probe(struct udevice *dev)
 	/* fill characteristics of DSI data link */
 	plat->lanes = 4;
 	plat->format = MIPI_DSI_FMT_RGB888;
+	plat->mode_flags = MIPI_DSI_MODE_LPM;
 
 	return sharp_lq101r1sx01_hw_init(dev);
 }
diff --git a/drivers/video/tegra20/Kconfig b/drivers/video/tegra20/Kconfig
index f5c4843e119..598f9ea1f21 100644
--- a/drivers/video/tegra20/Kconfig
+++ b/drivers/video/tegra20/Kconfig
@@ -1,6 +1,11 @@
+config HOST1X_TEGRA
+	bool "NVIDIA Tegra host1x BUS support"
+	depends on SIMPLE_BUS
+
 config VIDEO_TEGRA20
 	bool "Enable Display Controller support on Tegra20 and Tegra 30"
 	depends on OF_CONTROL
+	select HOST1X_TEGRA
 	help
 	   T20/T30 support video output to an attached LCD panel as well as
 	   other options such as HDMI. Only the LCD is supported in U-Boot.
@@ -9,13 +14,22 @@ config VIDEO_TEGRA20
 
 config VIDEO_DSI_TEGRA30
 	bool "Enable Tegra 30 DSI support"
-	depends on PANEL && DM_GPIO
+	depends on VIDEO_BRIDGE && PANEL && DM_GPIO
 	select VIDEO_TEGRA20
 	select VIDEO_MIPI_DSI
 	help
 	   T30 has native support for DSI panels. This option enables support
 	   for such panels which can be used on endeavoru and tf600t.
 
+config VIDEO_HDMI_TEGRA
+	bool "Enable Tegra HDMI support"
+	depends on VIDEO_BRIDGE && DM_I2C
+	select I2C_EDID
+	select VIDEO_TEGRA20
+	help
+	   Tegra has native support for HDMI. This option enables support
+	   for such connection and can be used for any supported device.
+
 config TEGRA_BACKLIGHT_PWM
 	bool "Enable Tegra DC PWM backlight support"
 	depends on BACKLIGHT
diff --git a/drivers/video/tegra20/Makefile b/drivers/video/tegra20/Makefile
index a75aea2a875..78521405749 100644
--- a/drivers/video/tegra20/Makefile
+++ b/drivers/video/tegra20/Makefile
@@ -1,5 +1,7 @@
 # SPDX-License-Identifier: GPL-2.0+
 
+obj-$(CONFIG_HOST1X_TEGRA) += tegra-host1x.o
 obj-$(CONFIG_VIDEO_TEGRA20) += tegra-dc.o
 obj-$(CONFIG_VIDEO_DSI_TEGRA30) += tegra-dsi.o tegra-mipi.o mipi-phy.o
+obj-$(CONFIG_VIDEO_HDMI_TEGRA) += tegra-hdmi.o
 obj-$(CONFIG_TEGRA_BACKLIGHT_PWM) += tegra-pwm-backlight.o
diff --git a/drivers/video/tegra20/tegra-dc.c b/drivers/video/tegra20/tegra-dc.c
index d24aa375b39..1f43153ff27 100644
--- a/drivers/video/tegra20/tegra-dc.c
+++ b/drivers/video/tegra20/tegra-dc.c
@@ -1,28 +1,23 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright (c) 2011 The Chromium OS Authors.
+ * Copyright (c) 2024 Svyatoslav Ryhel <clamor95@gmail.com>
  */
 
 #include <backlight.h>
 #include <cpu_func.h>
+#include <clk.h>
 #include <dm.h>
+#include <dm/ofnode_graph.h>
 #include <fdtdec.h>
 #include <log.h>
 #include <panel.h>
-#include <part.h>
-#include <pwm.h>
 #include <video.h>
-#include <asm/cache.h>
-#include <asm/global_data.h>
+#include <video_bridge.h>
 #include <asm/system.h>
-#include <asm/gpio.h>
 #include <asm/io.h>
-
 #include <asm/arch/clock.h>
-#include <asm/arch/funcmux.h>
-#include <asm/arch/pinmux.h>
 #include <asm/arch/powergate.h>
-#include <asm/arch/pwm.h>
 
 #include "tegra-dc.h"
 
@@ -39,12 +34,14 @@ struct tegra_lcd_priv {
 	int height;			/* height in pixels */
 	enum video_log2_bpp log2_bpp;	/* colour depth */
 	struct display_timing timing;
-	struct udevice *panel;
+	struct udevice *panel;		/* Panels attached to RGB */
+	struct udevice *bridge;		/* Bridge linked with DC */
 	struct dc_ctlr *dc;		/* Display controller regmap */
 	const struct tegra_dc_soc_info *soc;
 	fdt_addr_t frame_buffer;	/* Address of frame buffer */
 	unsigned pixel_clock;		/* Pixel clock in Hz */
-	int dc_clk[2];			/* Contains clk and its parent */
+	struct clk *clk;
+	struct clk *clk_parent;
 	ulong scdiv;			/* Clock divider used by disp_clk_ctrl */
 	bool rotation;			/* 180 degree panel turn */
 	int pipe;			/* DC controller: 0 for A, 1 for B */
@@ -144,10 +141,9 @@ static int update_display_mode(struct tegra_lcd_priv *priv)
 		val |= DATA_ALIGNMENT_MSB << DATA_ALIGNMENT_SHIFT;
 		val |= DATA_ORDER_RED_BLUE << DATA_ORDER_SHIFT;
 		writel(val, &disp->disp_interface_ctrl);
-	}
 
-	if (priv->soc->has_rgb)
 		writel(0x00010001, &disp->shift_clk_opt);
+	}
 
 	val = PIXEL_CLK_DIVIDER_PCD1 << PIXEL_CLK_DIVIDER_SHIFT;
 	val |= priv->scdiv << SHIFT_CLK_DIVIDER_SHIFT;
@@ -267,7 +263,9 @@ static int setup_window(struct tegra_lcd_priv *priv,
 	win->out_h = priv->height;
 	win->phys_addr = priv->frame_buffer;
 	win->stride = priv->width * (1 << priv->log2_bpp) / 8;
-	debug("%s: depth = %d\n", __func__, priv->log2_bpp);
+
+	log_debug("%s: depth = %d\n", __func__, priv->log2_bpp);
+
 	switch (priv->log2_bpp) {
 	case VIDEO_BPP32:
 		win->fmt = COLOR_DEPTH_R8G8B8A8;
@@ -279,7 +277,7 @@ static int setup_window(struct tegra_lcd_priv *priv,
 		break;
 
 	default:
-		debug("Unsupported LCD bit depth");
+		log_debug("Unsupported LCD bit depth\n");
 		return -1;
 	}
 
@@ -301,7 +299,8 @@ static int tegra_display_probe(struct tegra_lcd_priv *priv,
 			       void *default_lcd_base)
 {
 	struct disp_ctl_win window;
-	unsigned long rate = clock_get_rate(priv->dc_clk[1]);
+	unsigned long rate = clk_get_rate(priv->clk_parent);
+	int ret;
 
 	priv->frame_buffer = (u32)default_lcd_base;
 
@@ -309,15 +308,10 @@ static int tegra_display_probe(struct tegra_lcd_priv *priv,
 	 * We halve the rate if DISP1 parent is PLLD, since actual parent
 	 * is plld_out0 which is PLLD divided by 2.
 	 */
-	if (priv->dc_clk[1] == CLOCK_ID_DISPLAY)
+	if (priv->clk_parent->id == CLOCK_ID_DISPLAY ||
+	    priv->clk_parent->id == CLOCK_ID_DISPLAY2)
 		rate /= 2;
 
-#ifndef CONFIG_TEGRA20
-	/* PLLD2 obeys same rules as PLLD but it is present only on T30+ */
-	if (priv->dc_clk[1] == CLOCK_ID_DISPLAY2)
-		rate /= 2;
-#endif
-
 	/*
 	 * The pixel clock divider is in 7.1 format (where the bottom bit
 	 * represents 0.5). Here we calculate the divider needed to get from
@@ -327,14 +321,9 @@ static int tegra_display_probe(struct tegra_lcd_priv *priv,
 	if (!priv->scdiv)
 		priv->scdiv = ((rate * 2 + priv->pixel_clock / 2)
 						/ priv->pixel_clock) - 2;
-	debug("Display clock %lu, divider %lu\n", rate, priv->scdiv);
+	log_debug("Display clock %lu, divider %lu\n", rate, priv->scdiv);
 
-	/*
-	 * HOST1X is init by default at 150MHz with PLLC as parent
-	 */
-	clock_start_periph_pll(PERIPH_ID_HOST1X, CLOCK_ID_CGENERAL,
-			       150 * 1000000);
-	clock_start_periph_pll(priv->dc_clk[0], priv->dc_clk[1],
+	clock_start_periph_pll(priv->clk->id, priv->clk_parent->id,
 			       rate);
 
 	basic_init(&priv->dc->cmd);
@@ -348,8 +337,9 @@ static int tegra_display_probe(struct tegra_lcd_priv *priv,
 	if (priv->pixel_clock)
 		update_display_mode(priv);
 
-	if (setup_window(priv, &window))
-		return -1;
+	ret = setup_window(priv, &window);
+	if (ret)
+		return ret;
 
 	update_window(priv, &window);
 
@@ -364,10 +354,6 @@ static int tegra_lcd_probe(struct udevice *dev)
 	int ret;
 
 	/* Initialize the Tegra display controller */
-#ifdef CONFIG_TEGRA20
-	funcmux_select(PERIPH_ID_DISP1, FUNCMUX_DEFAULT);
-#endif
-
 	if (priv->soc->has_pgate) {
 		uint powergate;
 
@@ -378,44 +364,51 @@ static int tegra_lcd_probe(struct udevice *dev)
 
 		ret = tegra_powergate_power_off(powergate);
 		if (ret < 0) {
-			log_err("failed to power off DISP gate: %d", ret);
+			log_debug("failed to power off DISP gate: %d", ret);
 			return ret;
 		}
 
 		ret = tegra_powergate_sequence_power_up(powergate,
-							priv->dc_clk[0]);
+							priv->clk->id);
 		if (ret < 0) {
-			log_err("failed to power up DISP gate: %d", ret);
+			log_debug("failed to power up DISP gate: %d", ret);
 			return ret;
 		}
 	}
 
 	/* Get shift clock divider from Tegra DSI if used */
-	if (!strcmp(priv->panel->name, TEGRA_DSI_A) ||
-	    !strcmp(priv->panel->name, TEGRA_DSI_B)) {
-		struct tegra_dc_plat *dc_plat = dev_get_plat(priv->panel);
+	if (priv->bridge) {
+		if (!strcmp(priv->bridge->driver->name, "tegra_dsi")) {
+			struct tegra_dc_plat *dc_plat = dev_get_plat(priv->bridge);
 
-		priv->scdiv = dc_plat->scdiv;
+			priv->scdiv = dc_plat->scdiv;
+		}
 	}
 
 	/* Clean the framebuffer area */
 	memset((u8 *)plat->base, 0, plat->size);
 	flush_dcache_all();
 
-	if (tegra_display_probe(priv, (void *)plat->base)) {
-		debug("%s: Failed to probe display driver\n", __func__);
-		return -1;
+	ret = tegra_display_probe(priv, (void *)plat->base);
+	if (ret) {
+		log_debug("%s: Failed to probe display driver\n", __func__);
+		return ret;
 	}
 
-#ifdef CONFIG_TEGRA20
-	pinmux_set_func(PMUX_PINGRP_GPU, PMUX_FUNC_PWM);
-	pinmux_tristate_disable(PMUX_PINGRP_GPU);
-#endif
+	if (priv->panel) {
+		ret = panel_enable_backlight(priv->panel);
+		if (ret) {
+			log_debug("%s: Cannot enable backlight, ret=%d\n", __func__, ret);
+			return ret;
+		}
+	}
 
-	ret = panel_enable_backlight(priv->panel);
-	if (ret) {
-		debug("%s: Cannot enable backlight, ret=%d\n", __func__, ret);
-		return ret;
+	if (priv->bridge) {
+		ret = video_bridge_attach(priv->bridge);
+		if (ret) {
+			log_debug("%s: Cannot attach bridge, ret=%d\n", __func__, ret);
+			return ret;
+		}
 	}
 
 	mmu_set_region_dcache_behaviour(priv->frame_buffer, plat->size,
@@ -427,81 +420,198 @@ static int tegra_lcd_probe(struct udevice *dev)
 	uc_priv->xsize = priv->width;
 	uc_priv->ysize = priv->height;
 	uc_priv->bpix = priv->log2_bpp;
-	debug("LCD frame buffer at %08x, size %x\n", priv->frame_buffer,
-	      plat->size);
+	log_debug("LCD frame buffer at %08x, size %x\n", priv->frame_buffer,
+		  plat->size);
 
-	return panel_set_backlight(priv->panel, BACKLIGHT_DEFAULT);
+	if (priv->panel) {
+		ret = panel_set_backlight(priv->panel, BACKLIGHT_DEFAULT);
+		if (ret)
+			return ret;
+	}
+
+	if (priv->bridge) {
+		ret = video_bridge_set_backlight(priv->bridge, BACKLIGHT_DEFAULT);
+		if (ret)
+			return ret;
+	}
+
+	return 0;
+}
+
+static int tegra_lcd_configure_rgb(struct udevice *dev, ofnode rgb)
+{
+	struct tegra_lcd_priv *priv = dev_get_priv(dev);
+	ofnode remote;
+	int ret;
+
+	/* DC can have only 1 port */
+	remote = ofnode_graph_get_remote_node(rgb, -1, -1);
+
+	ret = uclass_get_device_by_ofnode(UCLASS_PANEL, remote, &priv->panel);
+	if (!ret)
+		return 0;
+
+	ret = uclass_get_device_by_ofnode(UCLASS_VIDEO_BRIDGE, remote, &priv->bridge);
+	if (!ret)
+		return 0;
+
+	/* Try legacy method if graph did not work */
+	remote = ofnode_parse_phandle(rgb, "nvidia,panel", 0);
+	if (!ofnode_valid(remote))
+		return -EINVAL;
+
+	ret = uclass_get_device_by_ofnode(UCLASS_PANEL, remote, &priv->panel);
+	if (ret) {
+		log_debug("%s: Cannot find panel for '%s' (ret=%d)\n",
+			  __func__, dev->name, ret);
+
+		ret = uclass_get_device_by_ofnode(UCLASS_VIDEO_BRIDGE, remote,
+						  &priv->bridge);
+		if (ret) {
+			log_err("%s: Cannot find panel or bridge for '%s' (ret=%d)\n",
+				__func__, dev->name, ret);
+			return ret;
+		}
+	}
+
+	return 0;
+}
+
+static int tegra_lcd_configure_internal(struct udevice *dev)
+{
+	struct tegra_lcd_priv *priv = dev_get_priv(dev);
+	struct tegra_dc_plat *dc_plat;
+	ofnode host1x = ofnode_get_parent(dev_ofnode(dev));
+	ofnode node;
+	int ret;
+
+	switch (priv->pipe) {
+	case 0: /* DC0 is usually used for DSI */
+		/* Check for ganged DSI configuration */
+		ofnode_for_each_subnode(node, host1x)
+			if (ofnode_name_eq(node, "dsi") && ofnode_is_enabled(node) &&
+			    ofnode_read_bool(node, "nvidia,ganged-mode"))
+				goto exit;
+
+		/* If no master DSI found loop for any active DSI */
+		ofnode_for_each_subnode(node, host1x)
+			if (ofnode_name_eq(node, "dsi") && ofnode_is_enabled(node))
+				goto exit;
+
+		log_err("%s: failed to find DSI device for '%s'\n",
+			__func__, dev->name);
+
+		return -ENODEV;
+	case 1: /* DC1 is usually used for HDMI */
+		ofnode_for_each_subnode(node, host1x)
+			if (ofnode_name_eq(node, "hdmi"))
+				goto exit;
+
+		log_err("%s: failed to find HDMI device for '%s'\n",
+			__func__, dev->name);
+
+		return -ENODEV;
+	default:
+		log_debug("Unsupported DC selection\n");
+		return -EINVAL;
+	}
+
+exit:
+	ret = uclass_get_device_by_ofnode(UCLASS_VIDEO_BRIDGE, node, &priv->bridge);
+	if (ret) {
+		log_err("%s: failed to get DSI/HDMI device for '%s' (ret %d)\n",
+			__func__, dev->name, ret);
+		return ret;
+	}
+
+	priv->clk_parent = devm_clk_get(priv->bridge, "parent");
+	if (IS_ERR(priv->clk_parent)) {
+		log_debug("%s: Could not get DC clock parent from DSI/HDMI: %ld\n",
+			  __func__, PTR_ERR(priv->clk_parent));
+		return PTR_ERR(priv->clk_parent);
+	}
+
+	dc_plat = dev_get_plat(priv->bridge);
+
+	/* Fill the platform data for internal devices */
+	dc_plat->dev = dev;
+	dc_plat->dc = priv->dc;
+	dc_plat->pipe = priv->pipe;
+
+	return 0;
 }
 
 static int tegra_lcd_of_to_plat(struct udevice *dev)
 {
 	struct tegra_lcd_priv *priv = dev_get_priv(dev);
-	const void *blob = gd->fdt_blob;
 	struct display_timing *timing;
-	int node = dev_of_offset(dev);
-	int panel_node;
-	int rgb;
+	ofnode rgb;
 	int ret;
 
 	priv->dc = (struct dc_ctlr *)dev_read_addr_ptr(dev);
 	if (!priv->dc) {
-		debug("%s: No display controller address\n", __func__);
+		log_debug("%s: No display controller address\n", __func__);
 		return -EINVAL;
 	}
 
 	priv->soc = (struct tegra_dc_soc_info *)dev_get_driver_data(dev);
 
-	ret = clock_decode_pair(dev, priv->dc_clk);
-	if (ret < 0) {
-		debug("%s: Cannot decode clocks for '%s' (ret = %d)\n",
-		      __func__, dev->name, ret);
-		return -EINVAL;
+	priv->clk = devm_clk_get(dev, NULL);
+	if (IS_ERR(priv->clk)) {
+		log_debug("%s: Could not get DC clock: %ld\n",
+			  __func__, PTR_ERR(priv->clk));
+		return PTR_ERR(priv->clk);
+	}
+
+	priv->clk_parent = devm_clk_get(dev, "parent");
+	if (IS_ERR(priv->clk_parent)) {
+		log_debug("%s: Could not get DC clock parent: %ld\n",
+			  __func__, PTR_ERR(priv->clk_parent));
+		return PTR_ERR(priv->clk_parent);
 	}
 
 	priv->rotation = dev_read_bool(dev, "nvidia,180-rotation");
 	priv->pipe = dev_read_u32_default(dev, "nvidia,head", 0);
 
-	rgb = fdt_subnode_offset(blob, node, "rgb");
-	if (rgb < 0) {
-		debug("%s: Cannot find rgb subnode for '%s' (ret=%d)\n",
-		      __func__, dev->name, rgb);
-		return -EINVAL;
-	}
-
 	/*
-	 * Sadly the panel phandle is in an rgb subnode so we cannot use
-	 * uclass_get_device_by_phandle().
+	 * Usual logic of Tegra video routing should be next:
+	 * 1. Check rgb subnode for RGB/LVDS panels or bridges
+	 * 2. If none found, then iterate through bridges bound,
+	 *    looking for DSIA or DSIB for DC0 and HDMI for DC1.
+	 * If none of above is valid, then configuration is not
+	 * valid.
 	 */
-	panel_node = fdtdec_lookup_phandle(blob, rgb, "nvidia,panel");
-	if (panel_node < 0) {
-		debug("%s: Cannot find panel information\n", __func__);
-		return -EINVAL;
-	}
 
-	ret = uclass_get_device_by_of_offset(UCLASS_PANEL, panel_node,
-					     &priv->panel);
-	if (ret) {
-		debug("%s: Cannot find panel for '%s' (ret=%d)\n", __func__,
-		      dev->name, ret);
-		return ret;
+	rgb = dev_read_subnode(dev, "rgb");
+	if (ofnode_valid(rgb) && ofnode_is_enabled(rgb)) {
+		/* RGB is available, use it */
+		ret = tegra_lcd_configure_rgb(dev, rgb);
+		if (ret)
+			return ret;
+	} else {
+		/* RGB is not available, check for internal devices */
+		ret = tegra_lcd_configure_internal(dev);
+		if (ret)
+			return ret;
 	}
 
-	/* Fill the platform data for internal devices */
-	if (!strcmp(priv->panel->name, TEGRA_DSI_A) ||
-	    !strcmp(priv->panel->name, TEGRA_DSI_B)) {
-		struct tegra_dc_plat *dc_plat = dev_get_plat(priv->panel);
-
-		dc_plat->dev = dev;
-		dc_plat->dc = priv->dc;
-		dc_plat->pipe = priv->pipe;
+	if (priv->panel) {
+		ret = panel_get_display_timing(priv->panel, &priv->timing);
+		if (ret) {
+			ret = ofnode_decode_display_timing(rgb, 0, &priv->timing);
+			if (ret) {
+				log_debug("%s: Cannot read display timing for '%s' (ret=%d)\n",
+					  __func__, dev->name, ret);
+				return -EINVAL;
+			}
+		}
 	}
 
-	ret = panel_get_display_timing(priv->panel, &priv->timing);
-	if (ret) {
-		ret = fdtdec_decode_display_timing(blob, rgb, 0, &priv->timing);
+	if (priv->bridge) {
+		ret = video_bridge_get_display_timing(priv->bridge, &priv->timing);
 		if (ret) {
-			debug("%s: Cannot read display timing for '%s' (ret=%d)\n",
-			      __func__, dev->name, ret);
+			log_debug("%s: Cannot read display timing for '%s' (ret=%d)\n",
+				  __func__, dev->name, ret);
 			return -EINVAL;
 		}
 	}
@@ -518,23 +628,13 @@ static int tegra_lcd_of_to_plat(struct udevice *dev)
 static int tegra_lcd_bind(struct udevice *dev)
 {
 	struct video_uc_plat *plat = dev_get_uclass_plat(dev);
-	const void *blob = gd->fdt_blob;
-	int node = dev_of_offset(dev);
-	int rgb;
-
-	rgb = fdt_subnode_offset(blob, node, "rgb");
-	if ((rgb < 0) || !fdtdec_get_is_enabled(blob, rgb))
-		return -ENODEV;
 
 	plat->size = LCD_MAX_WIDTH * LCD_MAX_HEIGHT *
 		(1 << LCD_MAX_LOG2_BPP) / 8;
 
-	return 0;
+	return dm_scan_fdt_dev(dev);
 }
 
-static const struct video_ops tegra_lcd_ops = {
-};
-
 static const struct tegra_dc_soc_info tegra20_dc_soc_info = {
 	.has_timer = true,
 	.has_rgb = true,
@@ -564,6 +664,9 @@ static const struct udevice_id tegra_lcd_ids[] = {
 		.compatible = "nvidia,tegra114-dc",
 		.data = (ulong)&tegra114_dc_soc_info
 	}, {
+		.compatible = "nvidia,tegra124-dc",
+		.data = (ulong)&tegra114_dc_soc_info
+	}, {
 		/* sentinel */
 	}
 };
@@ -572,7 +675,6 @@ U_BOOT_DRIVER(tegra_lcd) = {
 	.name		= "tegra_lcd",
 	.id		= UCLASS_VIDEO,
 	.of_match	= tegra_lcd_ids,
-	.ops		= &tegra_lcd_ops,
 	.bind		= tegra_lcd_bind,
 	.probe		= tegra_lcd_probe,
 	.of_to_plat	= tegra_lcd_of_to_plat,
diff --git a/drivers/video/tegra20/tegra-dc.h b/drivers/video/tegra20/tegra-dc.h
index 7d0c189ec80..2a4013b3355 100644
--- a/drivers/video/tegra20/tegra-dc.h
+++ b/drivers/video/tegra20/tegra-dc.h
@@ -14,9 +14,6 @@
 /* arch-tegra/dc exists only because T124 uses it */
 #include <asm/arch-tegra/dc.h>
 
-#define TEGRA_DSI_A		"dsi@54300000"
-#define TEGRA_DSI_B		"dsi@54400000"
-
 struct tegra_dc_plat {
 	struct udevice *dev;		/* Display controller device */
 	struct dc_ctlr *dc;		/* Display controller regmap */
diff --git a/drivers/video/tegra20/tegra-dsi.c b/drivers/video/tegra20/tegra-dsi.c
index 6327266dd22..a2a22fa0fe2 100644
--- a/drivers/video/tegra20/tegra-dsi.c
+++ b/drivers/video/tegra20/tegra-dsi.c
@@ -5,11 +5,13 @@
  */
 
 #include <dm.h>
+#include <clk.h>
 #include <log.h>
 #include <misc.h>
 #include <mipi_display.h>
 #include <mipi_dsi.h>
 #include <backlight.h>
+#include <video_bridge.h>
 #include <panel.h>
 #include <reset.h>
 #include <linux/delay.h>
@@ -46,10 +48,13 @@ struct tegra_dsi_priv {
 
 	enum tegra_dsi_format format;
 
-	int dsi_clk;
+	struct clk *clk;
+	struct clk *clk_parent;
+
 	int video_fifo_depth;
 	int host_fifo_depth;
 
+	u32 calibration_pads;
 	u32 version;
 
 	/* for ganged-mode support */
@@ -246,6 +251,9 @@ static ssize_t tegra_dsi_host_transfer(struct mipi_dsi_host *host,
 	value = DSI_HOST_CONTROL_CRC_RESET | DSI_HOST_CONTROL_TX_TRIG_HOST |
 		DSI_HOST_CONTROL_CS | DSI_HOST_CONTROL_ECC;
 
+	if ((msg->flags & MIPI_DSI_MSG_USE_LPM) == 0)
+		value |= DSI_HOST_CONTROL_HS;
+
 	/*
 	 * The host FIFO has a maximum of 64 words, so larger transmissions
 	 * need to use the video FIFO.
@@ -515,8 +523,9 @@ static void tegra_dsi_pad_calibrate(struct dsi_pad_ctrl_reg *pad)
 	writel(value, TEGRA_VI_BASE + (CSI_CIL_PAD_CONFIG << 2));
 }
 
-static void tegra_dsi_mipi_calibrate(struct tegra_dsi_priv *priv)
+static void tegra_dsi_mipi_calibrate(struct udevice *dev)
 {
+	struct tegra_dsi_priv *priv = dev_get_priv(dev);
 	struct dsi_pad_ctrl_reg *pad = &priv->dsi->pad;
 	u32 value;
 	int ret;
@@ -545,15 +554,20 @@ static void tegra_dsi_mipi_calibrate(struct tegra_dsi_priv *priv)
 		DSI_PAD_PREEMP_PD(0x03) | DSI_PAD_PREEMP_PU(0x3);
 	writel(value, &pad->pad_ctrl_3);
 
-	ret = misc_write(priv->mipi, 0, NULL, 0);
+	ret = misc_write(priv->mipi, priv->calibration_pads, NULL, 0);
 	if (ret)
 		log_debug("%s: MIPI calibration failed %d\n", __func__, ret);
+
+	if (priv->slave)
+		tegra_dsi_mipi_calibrate(priv->slave);
 }
 
-static void tegra_dsi_set_timeout(struct dsi_timeout_reg *rtimeout,
+static void tegra_dsi_set_timeout(struct udevice *dev,
 				  unsigned long bclk,
 				  unsigned int vrefresh)
 {
+	struct tegra_dsi_priv *priv = dev_get_priv(dev);
+	struct dsi_timeout_reg *rtimeout = &priv->dsi->timeout;
 	unsigned int timeout;
 	u32 value;
 
@@ -569,12 +583,17 @@ static void tegra_dsi_set_timeout(struct dsi_timeout_reg *rtimeout,
 
 	value = DSI_TALLY_TA(0) | DSI_TALLY_LRX(0) | DSI_TALLY_HTX(0);
 	writel(value, &rtimeout->dsi_to_tally);
+
+	if (priv->slave)
+		tegra_dsi_set_timeout(priv->slave, bclk, vrefresh);
 }
 
-static void tegra_dsi_set_phy_timing(struct dsi_timing_reg *ptiming,
+static void tegra_dsi_set_phy_timing(struct udevice *dev,
 				     unsigned long period,
 				     const struct mipi_dphy_timing *dphy_timing)
 {
+	struct tegra_dsi_priv *priv = dev_get_priv(dev);
+	struct dsi_timing_reg *ptiming = &priv->dsi->ptiming;
 	u32 value;
 
 	value = DSI_TIMING_FIELD(dphy_timing->hsexit, period, 1) << 24 |
@@ -598,6 +617,31 @@ static void tegra_dsi_set_phy_timing(struct dsi_timing_reg *ptiming,
 		DSI_TIMING_FIELD(dphy_timing->tasure, period, 1) << 8 |
 		DSI_TIMING_FIELD(dphy_timing->tago, period, 1);
 	writel(value, &ptiming->dsi_bta_timing);
+
+	if (priv->slave)
+		tegra_dsi_set_phy_timing(priv->slave, period, dphy_timing);
+}
+
+static u32 tegra_dsi_get_lanes(struct udevice *dev)
+{
+	struct tegra_dsi_priv *priv = dev_get_priv(dev);
+	struct mipi_dsi_device *device = &priv->device;
+
+	if (priv->master) {
+		struct tegra_dsi_priv *mpriv = dev_get_priv(priv->master);
+		struct mipi_dsi_device *mdevice = &mpriv->device;
+
+		return mdevice->lanes + device->lanes;
+	}
+
+	if (priv->slave) {
+		struct tegra_dsi_priv *spriv = dev_get_priv(priv->slave);
+		struct mipi_dsi_device *sdevice = &spriv->device;
+
+		return device->lanes + sdevice->lanes;
+	}
+
+	return device->lanes;
 }
 
 static void tegra_dsi_ganged_enable(struct udevice *dev, unsigned int start,
@@ -611,7 +655,7 @@ static void tegra_dsi_ganged_enable(struct udevice *dev, unsigned int start,
 	writel(DSI_GANGED_MODE_CONTROL_ENABLE, &ganged->ganged_mode_ctrl);
 }
 
-static void tegra_dsi_configure(struct udevice *dev,
+static void tegra_dsi_configure(struct udevice *dev, unsigned int pipe,
 				unsigned long mode_flags)
 {
 	struct tegra_dsi_priv *priv = dev_get_priv(dev);
@@ -642,7 +686,7 @@ static void tegra_dsi_configure(struct udevice *dev,
 	value = DSI_CONTROL_CHANNEL(0) |
 		DSI_CONTROL_FORMAT(priv->format) |
 		DSI_CONTROL_LANES(device->lanes - 1) |
-		DSI_CONTROL_SOURCE(0);
+		DSI_CONTROL_SOURCE(pipe);
 	writel(value, &misc->dsi_ctrl);
 
 	writel(priv->video_fifo_depth, &misc->dsi_max_threshold);
@@ -680,12 +724,19 @@ static void tegra_dsi_configure(struct udevice *dev,
 		/* horizontal back porch */
 		hbp = timing->hback_porch.typ * mul / div;
 
-		if ((mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) == 0)
-			hbp += hsw;
-
 		/* horizontal front porch */
 		hfp = timing->hfront_porch.typ * mul / div;
 
+		if (priv->master || priv->slave) {
+			hact /= 2;
+			hsw /= 2;
+			hbp = hbp / 2 - 1;
+			hfp /= 2;
+		}
+
+		if ((mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) == 0)
+			hbp += hsw;
+
 		/* subtract packet overhead */
 		hsw -= 10;
 		hbp -= 14;
@@ -695,9 +746,6 @@ static void tegra_dsi_configure(struct udevice *dev,
 		writel(hact << 16 | hbp, &len->dsi_pkt_len_2_3);
 		writel(hfp, &len->dsi_pkt_len_4_5);
 		writel(0x0f0f << 16, &len->dsi_pkt_len_6_7);
-
-		/* set SOL delay (for non-burst mode only) */
-		writel(8 * mul / div, &misc->dsi_sol_delay);
 	} else {
 		if (priv->master || priv->slave) {
 			/*
@@ -717,32 +765,33 @@ static void tegra_dsi_configure(struct udevice *dev,
 		value = MIPI_DCS_WRITE_MEMORY_START << 8 |
 			MIPI_DCS_WRITE_MEMORY_CONTINUE;
 		writel(value, &len->dsi_dcs_cmds);
+	}
 
-		/* set SOL delay */
-		if (priv->master || priv->slave) {
-			unsigned long delay, bclk, bclk_ganged;
-			unsigned int lanes = device->lanes;
-			unsigned long htotal = timing->hactive.typ + timing->hfront_porch.typ +
-					       timing->hback_porch.typ + timing->hsync_len.typ;
-
-			/* SOL to valid, valid to FIFO and FIFO write delay */
-			delay = 4 + 4 + 2;
-			delay = DIV_ROUND_UP(delay * mul, div * lanes);
-			/* FIFO read delay */
-			delay = delay + 6;
-
-			bclk = DIV_ROUND_UP(htotal * mul, div * lanes);
-			bclk_ganged = DIV_ROUND_UP(bclk * lanes / 2, lanes);
-			value = bclk - bclk_ganged + delay + 20;
-		} else {
-			/* TODO: revisit for non-ganged mode */
-			value = 8 * mul / div;
-		}
-
-		writel(value, &misc->dsi_sol_delay);
+	/* set SOL delay */
+	if (priv->master || priv->slave) {
+		unsigned long delay, bclk, bclk_ganged;
+		unsigned int lanes = tegra_dsi_get_lanes(dev);
+		unsigned long htotal = timing->hactive.typ + timing->hfront_porch.typ +
+				       timing->hback_porch.typ + timing->hsync_len.typ;
+
+		/* SOL to valid, valid to FIFO and FIFO write delay */
+		delay = 4 + 4 + 2;
+		delay = DIV_ROUND_UP(delay * mul, div * lanes);
+		/* FIFO read delay */
+		delay = delay + 6;
+
+		bclk = DIV_ROUND_UP(htotal * mul, div * lanes);
+		bclk_ganged = DIV_ROUND_UP(bclk * lanes / 2, lanes);
+		value = bclk - bclk_ganged + delay + 20;
+	} else {
+		/* set SOL delay (for non-burst mode only) */
+		value = 8 * mul / div;
 	}
 
+	writel(value, &misc->dsi_sol_delay);
+
 	if (priv->slave) {
+		tegra_dsi_configure(priv->slave, pipe, mode_flags);
 		/*
 		 * TODO: Support modes other than symmetrical left-right
 		 * split.
@@ -753,15 +802,31 @@ static void tegra_dsi_configure(struct udevice *dev,
 	}
 }
 
+static void tegra_dsi_enable(struct udevice *dev)
+{
+	struct tegra_dsi_priv *priv = dev_get_priv(dev);
+	struct dsi_misc_reg *misc = &priv->dsi->misc;
+	u32 value;
+
+	/* enable DSI controller */
+	value = readl(&misc->dsi_pwr_ctrl);
+	value |= DSI_POWER_CONTROL_ENABLE;
+	writel(value, &misc->dsi_pwr_ctrl);
+
+	if (priv->slave)
+		tegra_dsi_enable(priv->slave);
+}
+
 static int tegra_dsi_encoder_enable(struct udevice *dev)
 {
 	struct tegra_dsi_priv *priv = dev_get_priv(dev);
+	struct tegra_dc_plat *dc_plat = dev_get_plat(dev);
 	struct mipi_dsi_device *device = &priv->device;
 	struct display_timing *timing = &priv->timing;
 	struct dsi_misc_reg *misc = &priv->dsi->misc;
 	unsigned int mul, div;
 	unsigned long bclk, plld, period;
-	u32 value;
+	u32 value, lanes;
 	int ret;
 
 	/* If for some reasone DSI is enabled then it needs to
@@ -780,16 +845,17 @@ static int tegra_dsi_encoder_enable(struct udevice *dev)
 	writel(0, &misc->int_enable);
 
 	if (priv->version)
-		tegra_dsi_mipi_calibrate(priv);
+		tegra_dsi_mipi_calibrate(dev);
 	else
 		tegra_dsi_pad_calibrate(&priv->dsi->pad);
 
 	tegra_dsi_get_muldiv(device->format, &mul, &div);
 
 	/* compute byte clock */
-	bclk = (timing->pixelclock.typ * mul) / (div * device->lanes);
+	lanes = tegra_dsi_get_lanes(dev);
+	bclk = (timing->pixelclock.typ * mul) / (div * lanes);
 
-	tegra_dsi_set_timeout(&priv->dsi->timeout, bclk, 60);
+	tegra_dsi_set_timeout(dev, bclk, 60);
 
 	/*
 	 * Compute bit clock and round up to the next MHz.
@@ -813,25 +879,18 @@ static int tegra_dsi_encoder_enable(struct udevice *dev)
 	 * The D-PHY timing fields are expressed in byte-clock cycles, so
 	 * multiply the period by 8.
 	 */
-	tegra_dsi_set_phy_timing(&priv->dsi->ptiming,
-				 period * 8, &priv->dphy_timing);
+	tegra_dsi_set_phy_timing(dev, period * 8, &priv->dphy_timing);
 
 	/* Perform panel HW setup */
 	ret = panel_enable_backlight(priv->panel);
 	if (ret)
 		return ret;
 
-	tegra_dsi_configure(dev, device->mode_flags);
+	tegra_dsi_configure(dev, dc_plat->pipe, device->mode_flags);
 
 	tegra_dc_enable_controller(dev);
 
-	/* enable DSI controller */
-	value = readl(&misc->dsi_pwr_ctrl);
-	value |= DSI_POWER_CONTROL_ENABLE;
-	writel(value, &misc->dsi_pwr_ctrl);
-
-	if (priv->slave)
-		tegra_dsi_encoder_enable(priv->slave);
+	tegra_dsi_enable(dev);
 
 	return 0;
 }
@@ -859,21 +918,35 @@ static void tegra_dsi_init_clocks(struct udevice *dev)
 	struct tegra_dsi_priv *priv = dev_get_priv(dev);
 	struct tegra_dc_plat *dc_plat = dev_get_plat(dev);
 	struct mipi_dsi_device *device = &priv->device;
-	unsigned int mul, div;
+	unsigned int mul, div, lanes;
 	unsigned long bclk, plld;
 
-	if (!priv->slave) {
+	/* Switch parents of DSI clocks in case of not standard parent */
+	if (priv->clk->id == PERIPH_ID_DSI &&
+	    priv->clk_parent->id == CLOCK_ID_DISPLAY2) {
+		/* Change DSIA clock parent to PLLD2 */
+		struct clk_rst_ctlr *clkrst =
+			(struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
+
+		/* DSIA_CLK_SRC */
+		setbits_le32(&clkrst->crc_pll[CLOCK_ID_DISPLAY].pll_base,
+			     BIT(25));
+	}
+
+	if (priv->clk->id == PERIPH_ID_DSIB &&
+	    priv->clk_parent->id == CLOCK_ID_DISPLAY) {
 		/* Change DSIB clock parent to match DSIA */
 		struct clk_rst_ctlr *clkrst =
 			(struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
 
-		clrbits_le32(&clkrst->plld2.pll_base, BIT(25)); /* DSIB_CLK_SRC */
+		/* DSIB_CLK_SRC */
+		clrbits_le32(&clkrst->plld2.pll_base, BIT(25));
 	}
 
 	tegra_dsi_get_muldiv(device->format, &mul, &div);
 
-	bclk = (priv->timing.pixelclock.typ * mul) /
-					(div * device->lanes);
+	lanes = tegra_dsi_get_lanes(dev);
+	bclk = (priv->timing.pixelclock.typ * mul) / (div * lanes);
 
 	plld = DIV_ROUND_UP(bclk * 8, USEC_PER_SEC);
 
@@ -893,16 +966,16 @@ static void tegra_dsi_init_clocks(struct udevice *dev)
 	switch (clock_get_osc_freq()) {
 	case CLOCK_OSC_FREQ_12_0: /* OSC is 12Mhz */
 	case CLOCK_OSC_FREQ_48_0: /* OSC is 48Mhz */
-		clock_set_rate(CLOCK_ID_DISPLAY, plld, 12, 0, 8);
+		clock_set_rate(priv->clk_parent->id, plld, 12, 0, 8);
 		break;
 
 	case CLOCK_OSC_FREQ_26_0: /* OSC is 26Mhz */
-		clock_set_rate(CLOCK_ID_DISPLAY, plld, 26, 0, 8);
+		clock_set_rate(priv->clk_parent->id, plld, 26, 0, 8);
 		break;
 
 	case CLOCK_OSC_FREQ_13_0: /* OSC is 13Mhz */
 	case CLOCK_OSC_FREQ_16_8: /* OSC is 16.8Mhz */
-		clock_set_rate(CLOCK_ID_DISPLAY, plld, 13, 0, 8);
+		clock_set_rate(priv->clk_parent->id, plld, 13, 0, 8);
 		break;
 
 	case CLOCK_OSC_FREQ_19_2:
@@ -914,11 +987,7 @@ static void tegra_dsi_init_clocks(struct udevice *dev)
 		break;
 	}
 
-	priv->dsi_clk = clock_decode_periph_id(dev);
-
-	clock_enable(priv->dsi_clk);
-	udelay(2);
-	reset_set_enable(priv->dsi_clk, 0);
+	clk_enable(priv->clk);
 }
 
 static int tegra_dsi_ganged_probe(struct udevice *dev)
@@ -926,7 +995,7 @@ static int tegra_dsi_ganged_probe(struct udevice *dev)
 	struct tegra_dsi_priv *mpriv = dev_get_priv(dev);
 	struct udevice *gangster;
 
-	uclass_get_device_by_phandle(UCLASS_PANEL, dev,
+	uclass_get_device_by_phandle(UCLASS_VIDEO_BRIDGE, dev,
 				     "nvidia,ganged-mode", &gangster);
 	if (gangster) {
 		/* Ganged mode is set */
@@ -955,6 +1024,20 @@ static int tegra_dsi_bridge_probe(struct udevice *dev)
 		return -EINVAL;
 	}
 
+	priv->clk = devm_clk_get(dev, NULL);
+	if (IS_ERR(priv->clk)) {
+		log_debug("%s: Could not get DSI clock: %ld\n",
+			  __func__, PTR_ERR(priv->clk));
+		return PTR_ERR(priv->clk);
+	}
+
+	priv->clk_parent = devm_clk_get(dev, "parent");
+	if (IS_ERR(priv->clk_parent)) {
+		log_debug("%s: Could not get DSI clock parent: %ld\n",
+			  __func__, PTR_ERR(priv->clk_parent));
+		return PTR_ERR(priv->clk_parent);
+	}
+
 	priv->video_fifo_depth = 1920;
 	priv->host_fifo_depth = 64;
 
@@ -973,10 +1056,22 @@ static int tegra_dsi_bridge_probe(struct udevice *dev)
 		debug("%s: Cannot get avdd-dsi-csi-supply: error %d\n",
 		      __func__, ret);
 
-	ret = uclass_get_device_by_phandle(UCLASS_PANEL, dev,
-					   "panel", &priv->panel);
+	/* Check all DSI children */
+	device_foreach_child(priv->panel, dev) {
+		if (device_get_uclass_id(priv->panel) == UCLASS_PANEL)
+			break;
+	}
+
+	/* if loop exits without panel device return error */
+	if (device_get_uclass_id(priv->panel) != UCLASS_PANEL) {
+		log_debug("%s: panel not found, ret %d\n", __func__, ret);
+		return -EINVAL;
+	}
+
+	ret = uclass_get_device_by_ofnode(UCLASS_PANEL, dev_ofnode(priv->panel),
+					  &priv->panel);
 	if (ret) {
-		printf("%s: Cannot get panel: error %d\n", __func__, ret);
+		log_debug("%s: Cannot get panel: error %d\n", __func__, ret);
 		return log_ret(ret);
 	}
 
@@ -988,6 +1083,14 @@ static int tegra_dsi_bridge_probe(struct udevice *dev)
 			log_debug("%s: cannot get MIPI: error %d\n", __func__, ret);
 			return ret;
 		}
+
+		ret = dev_read_u32_index(dev, "nvidia,mipi-calibrate", 1,
+					 &priv->calibration_pads);
+		if (ret) {
+			log_debug("%s: cannot get calibration pads: error %d\n",
+				  __func__, ret);
+			return ret;
+		}
 	}
 
 	panel_get_display_timing(priv->panel, &priv->timing);
@@ -1019,8 +1122,8 @@ static int tegra_dsi_bridge_probe(struct udevice *dev)
 	return 0;
 }
 
-static const struct panel_ops tegra_dsi_bridge_ops = {
-	.enable_backlight	= tegra_dsi_encoder_enable,
+static const struct video_bridge_ops tegra_dsi_bridge_ops = {
+	.attach			= tegra_dsi_encoder_enable,
 	.set_backlight		= tegra_dsi_bridge_set_panel,
 	.get_display_timing	= tegra_dsi_panel_timings,
 };
@@ -1028,14 +1131,16 @@ static const struct panel_ops tegra_dsi_bridge_ops = {
 static const struct udevice_id tegra_dsi_bridge_ids[] = {
 	{ .compatible = "nvidia,tegra30-dsi", .data = DSI_V0 },
 	{ .compatible = "nvidia,tegra114-dsi", .data = DSI_V1 },
+	{ .compatible = "nvidia,tegra124-dsi", .data = DSI_V1 },
 	{ }
 };
 
 U_BOOT_DRIVER(tegra_dsi) = {
 	.name		= "tegra_dsi",
-	.id		= UCLASS_PANEL,
+	.id		= UCLASS_VIDEO_BRIDGE,
 	.of_match	= tegra_dsi_bridge_ids,
 	.ops		= &tegra_dsi_bridge_ops,
+	.bind		= dm_scan_fdt_dev,
 	.probe		= tegra_dsi_bridge_probe,
 	.plat_auto	= sizeof(struct tegra_dc_plat),
 	.priv_auto	= sizeof(struct tegra_dsi_priv),
diff --git a/drivers/video/tegra20/tegra-hdmi.c b/drivers/video/tegra20/tegra-hdmi.c
new file mode 100644
index 00000000000..bda69919d92
--- /dev/null
+++ b/drivers/video/tegra20/tegra-hdmi.c
@@ -0,0 +1,623 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2013 NVIDIA Corporation
+ * Copyright (c) 2023 Svyatoslav Ryhel <clamor95@gmail.com>
+ */
+
+#include <clk.h>
+#include <dm.h>
+#include <edid.h>
+#include <i2c.h>
+#include <log.h>
+#include <misc.h>
+#include <panel.h>
+#include <reset.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/time.h>
+#include <power/regulator.h>
+#include <video_bridge.h>
+
+#include <asm/gpio.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+
+#include "tegra-dc.h"
+#include "tegra-hdmi.h"
+
+#define DDCCI_ENTRY_ADDR	0x37
+#define DDCCI_SOURSE_ADDR	0x51
+#define DDCCI_COMMAND_WRITE	0x03
+#define DDCCI_CTRL_BRIGHTNESS	0x10
+
+#define HDMI_EDID_I2C_ADDR	0x50
+#define HDMI_REKEY_DEFAULT	56
+
+static const char * const hdmi_supplies[] = {
+	"hdmi-supply", "pll-supply", "vdd-supply"
+};
+
+struct tmds_config {
+	unsigned int pclk;
+	u32 pll0;
+	u32 pll1;
+	u32 pe_current;
+	u32 drive_current;
+	u32 peak_current;
+};
+
+struct tegra_hdmi_config {
+	const struct tmds_config *tmds;
+	unsigned int num_tmds;
+	unsigned int max_pclk;
+
+	/* to be filled */
+};
+
+struct tegra_hdmi_priv {
+	struct hdmi_ctlr *hdmi_regmap;
+
+	struct udevice *supplies[ARRAY_SIZE(hdmi_supplies)];
+	struct udevice *hdmi_ddc;
+
+	struct gpio_desc hpd; /* hotplug detection gpio */
+	struct display_timing timing;
+
+	struct clk *clk;
+	struct clk *clk_parent;
+
+	int panel_bits_per_colourp;
+	const struct tegra_hdmi_config *config;
+};
+
+/* 1280x720p 60hz: EIA/CEA-861-B Format 4 */
+static struct display_timing default_720p_timing = {
+	.pixelclock.typ		= 74250000,
+	.hactive.typ		= 1280,
+	.hfront_porch.typ	= 110,
+	.hback_porch.typ	= 220,
+	.hsync_len.typ		= 40,
+	.vactive.typ		= 720,
+	.vfront_porch.typ	= 5,
+	.vback_porch.typ	= 20,
+	.vsync_len.typ		= 5,
+	.flags			= DISPLAY_FLAGS_HSYNC_HIGH |
+				  DISPLAY_FLAGS_VSYNC_HIGH,
+};
+
+static const struct tmds_config tegra20_tmds_config[] = {
+	{ /* slow pixel clock modes */
+		.pclk = 27000000,
+		.pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
+			SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(0) |
+			SOR_PLL_TX_REG_LOAD(3),
+		.pll1 = SOR_PLL_TMDS_TERM_ENABLE,
+		.pe_current = PE_CURRENT0(PE_CURRENT_0_0_mA) |
+			PE_CURRENT1(PE_CURRENT_0_0_mA) |
+			PE_CURRENT2(PE_CURRENT_0_0_mA) |
+			PE_CURRENT3(PE_CURRENT_0_0_mA),
+		.drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_7_125_mA) |
+			DRIVE_CURRENT_LANE1(DRIVE_CURRENT_7_125_mA) |
+			DRIVE_CURRENT_LANE2(DRIVE_CURRENT_7_125_mA) |
+			DRIVE_CURRENT_LANE3(DRIVE_CURRENT_7_125_mA),
+	},
+	{ /* high pixel clock modes */
+		.pclk = UINT_MAX,
+		.pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
+			SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(1) |
+			SOR_PLL_TX_REG_LOAD(3),
+		.pll1 = SOR_PLL_TMDS_TERM_ENABLE | SOR_PLL_PE_EN,
+		.pe_current = PE_CURRENT0(PE_CURRENT_6_0_mA) |
+			PE_CURRENT1(PE_CURRENT_6_0_mA) |
+			PE_CURRENT2(PE_CURRENT_6_0_mA) |
+			PE_CURRENT3(PE_CURRENT_6_0_mA),
+		.drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_7_125_mA) |
+			DRIVE_CURRENT_LANE1(DRIVE_CURRENT_7_125_mA) |
+			DRIVE_CURRENT_LANE2(DRIVE_CURRENT_7_125_mA) |
+			DRIVE_CURRENT_LANE3(DRIVE_CURRENT_7_125_mA),
+	},
+};
+
+static const struct tmds_config tegra30_tmds_config[] = {
+	{ /* 480p modes */
+		.pclk = 27000000,
+		.pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
+			SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(0) |
+			SOR_PLL_TX_REG_LOAD(0),
+		.pll1 = SOR_PLL_TMDS_TERM_ENABLE,
+		.pe_current = PE_CURRENT0(PE_CURRENT_0_0_mA) |
+			PE_CURRENT1(PE_CURRENT_0_0_mA) |
+			PE_CURRENT2(PE_CURRENT_0_0_mA) |
+			PE_CURRENT3(PE_CURRENT_0_0_mA),
+		.drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_5_250_mA) |
+			DRIVE_CURRENT_LANE1(DRIVE_CURRENT_5_250_mA) |
+			DRIVE_CURRENT_LANE2(DRIVE_CURRENT_5_250_mA) |
+			DRIVE_CURRENT_LANE3(DRIVE_CURRENT_5_250_mA),
+	}, { /* 720p modes */
+		.pclk = 74250000,
+		.pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
+			SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(1) |
+			SOR_PLL_TX_REG_LOAD(0),
+		.pll1 = SOR_PLL_TMDS_TERM_ENABLE | SOR_PLL_PE_EN,
+		.pe_current = PE_CURRENT0(PE_CURRENT_5_0_mA) |
+			PE_CURRENT1(PE_CURRENT_5_0_mA) |
+			PE_CURRENT2(PE_CURRENT_5_0_mA) |
+			PE_CURRENT3(PE_CURRENT_5_0_mA),
+		.drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_5_250_mA) |
+			DRIVE_CURRENT_LANE1(DRIVE_CURRENT_5_250_mA) |
+			DRIVE_CURRENT_LANE2(DRIVE_CURRENT_5_250_mA) |
+			DRIVE_CURRENT_LANE3(DRIVE_CURRENT_5_250_mA),
+	}, { /* 1080p modes */
+		.pclk = UINT_MAX,
+		.pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
+			SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(3) |
+			SOR_PLL_TX_REG_LOAD(0),
+		.pll1 = SOR_PLL_TMDS_TERM_ENABLE | SOR_PLL_PE_EN,
+		.pe_current = PE_CURRENT0(PE_CURRENT_5_0_mA) |
+			PE_CURRENT1(PE_CURRENT_5_0_mA) |
+			PE_CURRENT2(PE_CURRENT_5_0_mA) |
+			PE_CURRENT3(PE_CURRENT_5_0_mA),
+		.drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_5_250_mA) |
+			DRIVE_CURRENT_LANE1(DRIVE_CURRENT_5_250_mA) |
+			DRIVE_CURRENT_LANE2(DRIVE_CURRENT_5_250_mA) |
+			DRIVE_CURRENT_LANE3(DRIVE_CURRENT_5_250_mA),
+	},
+};
+
+static void tegra_dc_enable_controller(struct udevice *dev)
+{
+	struct tegra_dc_plat *dc_plat = dev_get_plat(dev);
+	struct dc_ctlr *dc = dc_plat->dc;
+	u32 value;
+
+	value = readl(&dc->disp.disp_win_opt);
+	value |= HDMI_ENABLE;
+	writel(value, &dc->disp.disp_win_opt);
+
+	writel(GENERAL_UPDATE, &dc->cmd.state_ctrl);
+	writel(GENERAL_ACT_REQ, &dc->cmd.state_ctrl);
+}
+
+static void tegra_hdmi_setup_tmds(struct tegra_hdmi_priv *priv,
+				  const struct tmds_config *tmds)
+{
+	struct hdmi_ctlr *hdmi = priv->hdmi_regmap;
+	u32 value;
+
+	writel(tmds->pll0, &hdmi->nv_pdisp_sor_pll0);
+	writel(tmds->pll1, &hdmi->nv_pdisp_sor_pll1);
+	writel(tmds->pe_current, &hdmi->nv_pdisp_pe_current);
+
+	writel(tmds->drive_current, &hdmi->nv_pdisp_sor_lane_drive_current);
+
+	value = readl(&hdmi->nv_pdisp_sor_lane_drive_current);
+	value |= BIT(31);
+	writel(value, &hdmi->nv_pdisp_sor_lane_drive_current);
+}
+
+static int tegra_hdmi_encoder_enable(struct udevice *dev)
+{
+	struct tegra_dc_plat *dc_plat = dev_get_plat(dev);
+	struct tegra_hdmi_priv *priv = dev_get_priv(dev);
+	struct dc_ctlr *dc = dc_plat->dc;
+	struct display_timing *dt = &priv->timing;
+	struct hdmi_ctlr *hdmi = priv->hdmi_regmap;
+	unsigned long rate, div82;
+	unsigned int pulse_start, rekey;
+	int retries = 1000;
+	u32 value;
+	int i;
+
+	/* power up sequence */
+	value = readl(&hdmi->nv_pdisp_sor_pll0);
+	value &= ~SOR_PLL_PDBG;
+	writel(value, &hdmi->nv_pdisp_sor_pll0);
+
+	udelay(20);
+
+	value = readl(&hdmi->nv_pdisp_sor_pll0);
+	value &= ~SOR_PLL_PWR;
+	writel(value, &hdmi->nv_pdisp_sor_pll0);
+
+	writel(VSYNC_H_POSITION(1), &dc->disp.disp_timing_opt);
+	writel(DITHER_CONTROL_DISABLE | BASE_COLOR_SIZE_888,
+	       &dc->disp.disp_color_ctrl);
+
+	/* video_preamble uses h_pulse2 */
+	pulse_start = 1 + dt->hsync_len.typ + dt->hback_porch.typ - 10;
+
+	writel(H_PULSE2_ENABLE, &dc->disp.disp_signal_opt0);
+
+	value = PULSE_MODE_NORMAL | PULSE_POLARITY_HIGH |
+		PULSE_QUAL_VACTIVE | PULSE_LAST_END_A;
+	writel(value, &dc->disp.h_pulse[H_PULSE2].h_pulse_ctrl);
+
+	value = PULSE_START(pulse_start) | PULSE_END(pulse_start + 8);
+	writel(value, &dc->disp.h_pulse[H_PULSE2].h_pulse_pos[H_PULSE0_POSITION_A]);
+
+	value = VSYNC_WINDOW_END(0x210) | VSYNC_WINDOW_START(0x200) |
+		VSYNC_WINDOW_ENABLE;
+	writel(value, &hdmi->nv_pdisp_hdmi_vsync_window);
+
+	if (dc_plat->pipe)
+		value = HDMI_SRC_DISPLAYB;
+	else
+		value = HDMI_SRC_DISPLAYA;
+
+	if (dt->hactive.typ == 720 && (dt->vactive.typ == 480 ||
+				       dt->vactive.typ == 576))
+		writel(value | ARM_VIDEO_RANGE_FULL,
+		       &hdmi->nv_pdisp_input_control);
+	else
+		writel(value | ARM_VIDEO_RANGE_LIMITED,
+		       &hdmi->nv_pdisp_input_control);
+
+	rate = clock_get_periph_rate(priv->clk->id, priv->clk_parent->id);
+	div82 = rate / USEC_PER_SEC * 4;
+	value = SOR_REFCLK_DIV_INT(div82 >> 2) | SOR_REFCLK_DIV_FRAC(div82);
+	writel(value, &hdmi->nv_pdisp_sor_refclk);
+
+	rekey = HDMI_REKEY_DEFAULT;
+	value = HDMI_CTRL_REKEY(rekey);
+	value |= HDMI_CTRL_MAX_AC_PACKET((dt->hsync_len.typ + dt->hback_porch.typ +
+					  dt->hfront_porch.typ - rekey - 18) / 32);
+	writel(value, &hdmi->nv_pdisp_hdmi_ctrl);
+
+	/* TMDS CONFIG */
+	for (i = 0; i < priv->config->num_tmds; i++) {
+		if (dt->pixelclock.typ <= priv->config->tmds[i].pclk) {
+			tegra_hdmi_setup_tmds(priv, &priv->config->tmds[i]);
+			break;
+		}
+	}
+
+	writel(SOR_SEQ_PU_PC(0) | SOR_SEQ_PU_PC_ALT(0) | SOR_SEQ_PD_PC(8) |
+	       SOR_SEQ_PD_PC_ALT(8), &hdmi->nv_pdisp_sor_seq_ctl);
+
+	value = SOR_SEQ_INST_WAIT_TIME(1) | SOR_SEQ_INST_WAIT_UNITS_VSYNC |
+		SOR_SEQ_INST_HALT | SOR_SEQ_INST_PIN_A_LOW |
+		SOR_SEQ_INST_PIN_B_LOW | SOR_SEQ_INST_DRIVE_PWM_OUT_LO;
+
+	writel(value, &hdmi->nv_pdisp_sor_seq_inst0);
+	writel(value, &hdmi->nv_pdisp_sor_seq_inst8);
+
+	value = readl(&hdmi->nv_pdisp_sor_cstm);
+
+	value &= ~SOR_CSTM_ROTCLK(~0);
+	value |= SOR_CSTM_ROTCLK(2);
+	value |= SOR_CSTM_PLLDIV;
+	value &= ~SOR_CSTM_LVDS_ENABLE;
+	value &= ~SOR_CSTM_MODE_MASK;
+	value |= SOR_CSTM_MODE_TMDS;
+
+	writel(value, &hdmi->nv_pdisp_sor_cstm);
+
+	/* start SOR */
+	writel(SOR_PWR_NORMAL_STATE_PU | SOR_PWR_NORMAL_START_NORMAL |
+	       SOR_PWR_SAFE_STATE_PD | SOR_PWR_SETTING_NEW_TRIGGER,
+	       &hdmi->nv_pdisp_sor_pwr);
+	writel(SOR_PWR_NORMAL_STATE_PU | SOR_PWR_NORMAL_START_NORMAL |
+	       SOR_PWR_SAFE_STATE_PD | SOR_PWR_SETTING_NEW_DONE,
+	       &hdmi->nv_pdisp_sor_pwr);
+
+	do {
+		if (--retries < 0)
+			return -ETIME;
+		value = readl(&hdmi->nv_pdisp_sor_pwr);
+	} while (value & SOR_PWR_SETTING_NEW_PENDING);
+
+	value = SOR_STATE_ASY_CRCMODE_COMPLETE |
+		SOR_STATE_ASY_OWNER_HEAD0 |
+		SOR_STATE_ASY_SUBOWNER_BOTH |
+		SOR_STATE_ASY_PROTOCOL_SINGLE_TMDS_A |
+		SOR_STATE_ASY_DEPOL_POS;
+
+	/* setup sync polarities */
+	if (dt->flags & DISPLAY_FLAGS_HSYNC_HIGH)
+		value |= SOR_STATE_ASY_HSYNCPOL_POS;
+
+	if (dt->flags & DISPLAY_FLAGS_HSYNC_LOW)
+		value |= SOR_STATE_ASY_HSYNCPOL_NEG;
+
+	if (dt->flags & DISPLAY_FLAGS_VSYNC_HIGH)
+		value |= SOR_STATE_ASY_VSYNCPOL_POS;
+
+	if (dt->flags & DISPLAY_FLAGS_VSYNC_LOW)
+		value |= SOR_STATE_ASY_VSYNCPOL_NEG;
+
+	writel(value, &hdmi->nv_pdisp_sor_state2);
+
+	value = SOR_STATE_ASY_HEAD_OPMODE_AWAKE | SOR_STATE_ASY_ORMODE_NORMAL;
+	writel(value, &hdmi->nv_pdisp_sor_state1);
+
+	writel(0, &hdmi->nv_pdisp_sor_state0);
+	writel(SOR_STATE_UPDATE, &hdmi->nv_pdisp_sor_state0);
+	writel(value | SOR_STATE_ATTACHED,
+	       &hdmi->nv_pdisp_sor_state1);
+	writel(0, &hdmi->nv_pdisp_sor_state0);
+
+	tegra_dc_enable_controller(dev);
+
+	return 0;
+}
+
+/* DDC/CI backlight control */
+static int tegra_hdmi_set_connector(struct udevice *dev, int percent)
+{
+	struct tegra_hdmi_priv *priv = dev_get_priv(dev);
+	struct udevice *ddc_entry;
+	struct i2c_msg msg[1];
+	u8 checksum = DDCCI_ENTRY_ADDR << 1;
+	int i, ret;
+
+	ret = dm_i2c_probe(priv->hdmi_ddc, DDCCI_ENTRY_ADDR, 0, &ddc_entry);
+	if (ret) {
+		log_debug("%s: cannot probe DDC/CI entry: error %d\n",
+			  __func__, ret);
+		return 0;
+	}
+
+	/*
+	 * payload[1] is length: hithest bit OR last 4 bits indicate
+	 * the number of following bytes (excluding checksum)
+	 */
+	u8 payload[7] = { DDCCI_SOURSE_ADDR, BIT(7) | (sizeof(payload) - 3),
+			  DDCCI_COMMAND_WRITE, DDCCI_CTRL_BRIGHTNESS,
+			  (u8)(percent & 0xff), (u8)(percent & 0xff), 0 };
+
+	/* DDC/CI checksum is a simple XOR of all preceding bytes */
+	for (i = 0; i < (sizeof(payload) - 1); i++)
+		checksum ^= payload[i];
+
+	payload[6] = checksum;
+
+	msg->addr = DDCCI_ENTRY_ADDR;
+	msg->flags = 0;
+	msg->len = sizeof(payload);
+	msg->buf = payload;
+
+	dm_i2c_xfer(ddc_entry, msg, 1);
+
+	return 0;
+}
+
+static int tegra_hdmi_timings(struct udevice *dev,
+			      struct display_timing *timing)
+{
+	struct tegra_hdmi_priv *priv = dev_get_priv(dev);
+
+	memcpy(timing, &priv->timing, sizeof(*timing));
+
+	return 0;
+}
+
+static void tegra_hdmi_init_clocks(struct udevice *dev)
+{
+	struct tegra_hdmi_priv *priv = dev_get_priv(dev);
+	u32 n = priv->timing.pixelclock.typ * 2 / USEC_PER_SEC;
+
+	switch (clock_get_osc_freq()) {
+	case CLOCK_OSC_FREQ_12_0: /* OSC is 12Mhz */
+	case CLOCK_OSC_FREQ_48_0: /* OSC is 48Mhz */
+		clock_set_rate(priv->clk_parent->id, n, 12, 0, 8);
+		break;
+
+	case CLOCK_OSC_FREQ_26_0: /* OSC is 26Mhz */
+		clock_set_rate(priv->clk_parent->id, n, 26, 0, 8);
+		break;
+
+	case CLOCK_OSC_FREQ_13_0: /* OSC is 13Mhz */
+	case CLOCK_OSC_FREQ_16_8: /* OSC is 16.8Mhz */
+		clock_set_rate(priv->clk_parent->id, n, 13, 0, 8);
+		break;
+
+	case CLOCK_OSC_FREQ_19_2:
+	case CLOCK_OSC_FREQ_38_4:
+	default:
+		/*
+		 * These are not supported.
+		 */
+		break;
+	}
+
+	clock_start_periph_pll(priv->clk->id, priv->clk_parent->id,
+			       priv->timing.pixelclock.typ);
+}
+
+static bool tegra_hdmi_mode_valid(void *hdmi_priv, const struct display_timing *timing)
+{
+	struct tegra_hdmi_priv *priv = hdmi_priv;
+
+	if (timing->pixelclock.typ > priv->config->max_pclk)
+		return false;
+
+	return true;
+}
+
+static int tegra_hdmi_decode_edid(struct udevice *dev)
+{
+	struct tegra_hdmi_priv *priv = dev_get_priv(dev);
+	struct udevice *hdmi_edid;
+	uchar edid_buf[EDID_SIZE] = { 0 };
+	int i, ret;
+
+	/* Poll for 1 sec in case EDID is not ready right after hpd */
+	for (i = 0; i < 10; i++) {
+		ret = dm_i2c_probe(priv->hdmi_ddc, HDMI_EDID_I2C_ADDR, 0,
+				   &hdmi_edid);
+		if (!ret)
+			break;
+
+		mdelay(100);
+	}
+	if (ret) {
+		log_debug("%s: cannot probe EDID: error %d\n",
+			  __func__, ret);
+		return ret;
+	}
+
+	ret = dm_i2c_read(hdmi_edid, 0, edid_buf, sizeof(edid_buf));
+	if (ret) {
+		log_debug("%s: cannot dump EDID buffer: error %d\n",
+			  __func__, ret);
+		return ret;
+	}
+
+	ret = edid_get_timing_validate(edid_buf, sizeof(edid_buf), &priv->timing,
+				       &priv->panel_bits_per_colourp,
+				       tegra_hdmi_mode_valid, priv);
+	if (ret) {
+		log_debug("%s: cannot decode EDID info: error %d\n",
+			  __func__, ret);
+		return ret;
+	}
+
+	return 0;
+}
+
+static int tegra_hdmi_wait_hpd(struct tegra_hdmi_priv *priv)
+{
+	int i;
+
+	/* Poll 1 second for HPD signal */
+	for (i = 0; i < 10; i++) {
+		if (dm_gpio_get_value(&priv->hpd))
+			return 0;
+
+		mdelay(100);
+	}
+
+	return -ETIMEDOUT;
+}
+
+static int tegra_hdmi_probe(struct udevice *dev)
+{
+	struct tegra_hdmi_priv *priv = dev_get_priv(dev);
+	struct reset_ctl reset_ctl;
+	int i, ret;
+
+	priv->hdmi_regmap = (struct hdmi_ctlr *)dev_read_addr_ptr(dev);
+	if (!priv->hdmi_regmap) {
+		log_debug("%s: no display controller address\n", __func__);
+		return -EINVAL;
+	}
+
+	priv->config = (struct tegra_hdmi_config *)dev_get_driver_data(dev);
+
+	priv->clk = devm_clk_get(dev, NULL);
+	if (IS_ERR(priv->clk)) {
+		log_debug("%s: Could not get HDMI clock: %ld\n",
+			  __func__, PTR_ERR(priv->clk));
+		return PTR_ERR(priv->clk);
+	}
+
+	priv->clk_parent = devm_clk_get(dev, "parent");
+	if (IS_ERR(priv->clk_parent)) {
+		log_debug("%s: Could not get HDMI clock parent: %ld\n",
+			  __func__, PTR_ERR(priv->clk_parent));
+		return PTR_ERR(priv->clk_parent);
+	}
+
+	for (i = 0; i < ARRAY_SIZE(hdmi_supplies); i++) {
+		ret = device_get_supply_regulator(dev, hdmi_supplies[i],
+						  &priv->supplies[i]);
+		if (ret) {
+			log_debug("%s: cannot get %s %d\n", __func__,
+				  hdmi_supplies[i], ret);
+			if (ret != -ENOENT)
+				return log_ret(ret);
+		}
+
+		ret = regulator_set_enable_if_allowed(priv->supplies[i], true);
+		if (ret && ret != -ENOSYS) {
+			log_debug("%s: cannot enable %s: error %d\n",
+				  __func__, hdmi_supplies[i], ret);
+			return ret;
+		}
+	}
+
+	ret = reset_get_by_name(dev, "hdmi", &reset_ctl);
+	if (ret) {
+		log_debug("%s: reset_get_by_name() failed: %d\n",
+			  __func__, ret);
+		return ret;
+	}
+
+	ret = uclass_get_device_by_phandle(UCLASS_I2C, dev,
+					   "nvidia,ddc-i2c-bus",
+					   &priv->hdmi_ddc);
+	if (ret) {
+		log_debug("%s: cannot get hdmi ddc i2c bus: error %d\n",
+			  __func__, ret);
+		return ret;
+	}
+
+	ret = gpio_request_by_name(dev, "nvidia,hpd-gpio", 0,
+				   &priv->hpd, GPIOD_IS_IN);
+	if (ret) {
+		log_debug("%s: Could not decode hpd-gpios (%d)\n",
+			  __func__, ret);
+		return ret;
+	}
+
+	/* wait for connector */
+	ret = tegra_hdmi_wait_hpd(priv);
+	if (ret) {
+		/* HPD failed, use default timings */
+		memcpy(&priv->timing, &default_720p_timing,
+		       sizeof(default_720p_timing));
+	} else {
+		ret = tegra_hdmi_decode_edid(dev);
+		if (ret)
+			memcpy(&priv->timing, &default_720p_timing,
+			       sizeof(default_720p_timing));
+	}
+
+	reset_assert(&reset_ctl);
+	tegra_hdmi_init_clocks(dev);
+
+	mdelay(2);
+	reset_deassert(&reset_ctl);
+
+	return 0;
+}
+
+static const struct tegra_hdmi_config tegra20_hdmi_config = {
+	.tmds = tegra20_tmds_config,
+	.num_tmds = ARRAY_SIZE(tegra20_tmds_config),
+	.max_pclk = 148500000, /* 1080p */
+};
+
+static const struct tegra_hdmi_config tegra30_hdmi_config = {
+	.tmds = tegra30_tmds_config,
+	.num_tmds = ARRAY_SIZE(tegra30_tmds_config),
+	.max_pclk = 148500000, /* 1080p */
+};
+
+static const struct video_bridge_ops tegra_hdmi_ops = {
+	.attach			= tegra_hdmi_encoder_enable,
+	.set_backlight		= tegra_hdmi_set_connector,
+	.get_display_timing	= tegra_hdmi_timings,
+};
+
+static const struct udevice_id tegra_hdmi_ids[] = {
+	{
+		.compatible = "nvidia,tegra20-hdmi",
+		.data = (ulong)&tegra20_hdmi_config
+	}, {
+		.compatible = "nvidia,tegra30-hdmi",
+		.data = (ulong)&tegra30_hdmi_config
+	}, {
+		/* sentinel */
+	}
+};
+
+U_BOOT_DRIVER(tegra_hdmi) = {
+	.name		= "tegra_hdmi",
+	.id		= UCLASS_VIDEO_BRIDGE,
+	.of_match	= tegra_hdmi_ids,
+	.ops		= &tegra_hdmi_ops,
+	.probe		= tegra_hdmi_probe,
+	.plat_auto	= sizeof(struct tegra_dc_plat),
+	.priv_auto	= sizeof(struct tegra_hdmi_priv),
+};
diff --git a/drivers/video/tegra20/tegra-hdmi.h b/drivers/video/tegra20/tegra-hdmi.h
new file mode 100644
index 00000000000..d17655973e3
--- /dev/null
+++ b/drivers/video/tegra20/tegra-hdmi.h
@@ -0,0 +1,648 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ *  (C) Copyright 2010
+ *  NVIDIA Corporation <www.nvidia.com>
+ */
+
+#ifndef _TEGRA_HDMI_H
+#define _TEGRA_HDMI_H
+
+#ifndef __ASSEMBLY__
+#include <linux/bitops.h>
+#endif
+
+/* Register definitions for the Tegra high-definition multimedia interface */
+
+/* High-Definition Multimedia Interface (HDMI_) regs */
+struct hdmi_ctlr {
+	/* Address 0x000 ~ 0x0d2 */
+	uint ctxsw;						/* _CTXSW */  /* 0x00 */
+
+	uint nv_pdisp_sor_state0;				/* _NV_PDISP_SOR_STATE0 */
+	uint nv_pdisp_sor_state1;				/* _NV_PDISP_SOR_STATE1 */
+	uint nv_pdisp_sor_state2;				/* _NV_PDISP_SOR_STATE2 */
+
+	uint nv_pdisp_rg_hdcp_an_msb;				/* _NV_PDISP_RG_HDCP_AN_MSB */
+	uint nv_pdisp_rg_hdcp_an_lsb;				/* _NV_PDISP_RG_HDCP_AN_LSB */
+	uint nv_pdisp_rg_hdcp_cn_msb;				/* _NV_PDISP_RG_HDCP_CN_MSB */
+	uint nv_pdisp_rg_hdcp_cn_lsb;				/* _NV_PDISP_RG_HDCP_CN_LSB */
+	uint nv_pdisp_rg_hdcp_aksv_msb;				/* _NV_PDISP_RG_HDCP_AKSV_MSB */
+	uint nv_pdisp_rg_hdcp_aksv_lsb;				/* _NV_PDISP_RG_HDCP_AKSV_LSB */
+	uint nv_pdisp_rg_hdcp_bksv_msb;				/* _NV_PDISP_RG_HDCP_BKSV_MSB */
+	uint nv_pdisp_rg_hdcp_bksv_lsb;				/* _NV_PDISP_RG_HDCP_BKSV_LSB */
+	uint nv_pdisp_rg_hdcp_cksv_msb;				/* _NV_PDISP_RG_HDCP_CKSV_MSB */
+	uint nv_pdisp_rg_hdcp_cksv_lsb;				/* _NV_PDISP_RG_HDCP_CKSV_LSB */
+	uint nv_pdisp_rg_hdcp_dksv_msb;				/* _NV_PDISP_RG_HDCP_DKSV_MSB */
+	uint nv_pdisp_rg_hdcp_dksv_lsb;				/* _NV_PDISP_RG_HDCP_DKSV_LSB */
+	uint nv_pdisp_rg_hdcp_ctrl;				/* _NV_PDISP_RG_HDCP_CTRL */  /* 0x10 */
+	uint nv_pdisp_rg_hdcp_cmode;				/* _NV_PDISP_RG_HDCP_CMODE */
+	uint nv_pdisp_rg_hdcp_mprime_msb;			/* _NV_PDISP_RG_HDCP_MPRIME_MSB */
+	uint nv_pdisp_rg_hdcp_mprime_lsb;			/* _NV_PDISP_RG_HDCP_MPRIME_LSB */
+	uint nv_pdisp_rg_hdcp_sprime_msb;			/* _NV_PDISP_RG_HDCP_SPRIME_MSB */
+	uint nv_pdisp_rg_hdcp_sprime_lsb2;			/* _NV_PDISP_RG_HDCP_SPRIME_LSB2 */
+	uint nv_pdisp_rg_hdcp_sprime_lsb1;			/* _NV_PDISP_RG_HDCP_SPRIME_LSB1 */
+	uint nv_pdisp_rg_hdcp_ri;				/* _NV_PDISP_RG_HDCP_RI */
+	uint nv_pdisp_rg_hdcp_cs_msb;				/* _NV_PDISP_RG_HDCP_CS_MSB */
+	uint nv_pdisp_rg_hdcp_cs_lsb;				/* _NV_PDISP_RG_HDCP_CS_LSB */
+
+	uint nv_pdisp_hdmi_audio_emu0;				/* _NV_PDISP_HDMI_AUDIO_EMU0 */
+	uint nv_pdisp_hdmi_audio_emu_rdata0;			/* _NV_PDISP_HDMI_AUDIO_EMU_RDATA0 */
+	uint nv_pdisp_hdmi_audio_emu1;				/* _NV_PDISP_HDMI_AUDIO_EMU1 */
+	uint nv_pdisp_hdmi_audio_emu2;				/* _NV_PDISP_HDMI_AUDIO_EMU2 */
+	uint nv_pdisp_hdmi_audio_infoframe_ctrl;		/* _NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL */
+	uint nv_pdisp_hdmi_audio_infoframe_status;		/* _NV_PDISP_HDMI_AUDIO_INFOFRAME_STATUS */
+	uint nv_pdisp_hdmi_audio_infoframe_header;		/* _NV_PDISP_HDMI_AUDIO_INFOFRAME_HEADER */  /* 0x20 */
+	uint nv_pdisp_hdmi_audio_infoframe_subpack0_low;	/* _NV_PDISP_HDMI_AUDIO_INFOFRAME_SUBPACK0_LOW */
+	uint nv_pdisp_hdmi_audio_infoframe_subpack0_high;	/* _NV_PDISP_HDMI_AUDIO_INFOFRAME_SUBPACK0_HIGH */
+
+	uint nv_pdisp_hdmi_avi_infoframe_ctrl;			/* _NV_PDISP_HDMI_AVI_INFOFRAME_CTRL */
+	uint nv_pdisp_hdmi_avi_infoframe_status;		/* _NV_PDISP_HDMI_AVI_INFOFRAME_STATUS */
+	uint nv_pdisp_hdmi_avi_infoframe_header;		/* _NV_PDISP_HDMI_AVI_INFOFRAME_HEADER */
+	uint nv_pdisp_hdmi_avi_infoframe_subpack0_low;		/* _NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK0_LOW */
+	uint nv_pdisp_hdmi_avi_infoframe_subpack0_high;		/* _NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH */
+	uint nv_pdisp_hdmi_avi_infoframe_subpack1_low;		/* _NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK1_LOW */
+	uint nv_pdisp_hdmi_avi_infoframe_subpack1_high;		/* _NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH */
+
+	uint nv_pdisp_hdmi_generic_ctrl;			/* _NV_PDISP_HDMI_GENERIC_CTRL */
+	uint nv_pdisp_hdmi_generic_status;			/* _NV_PDISP_HDMI_GENERIC_STATUS */
+	uint nv_pdisp_hdmi_generic_header;			/* _NV_PDISP_HDMI_GENERIC_HEADER */
+	uint nv_pdisp_hdmi_generic_subpack0_low;		/* _NV_PDISP_HDMI_GENERIC_SUBPACK0_LOW */
+	uint nv_pdisp_hdmi_generic_subpack0_high;		/* _NV_PDISP_HDMI_GENERIC_SUBPACK0_HIGH */
+	uint nv_pdisp_hdmi_generic_subpack1_low;		/* _NV_PDISP_HDMI_GENERIC_SUBPACK1_LOW */
+	uint nv_pdisp_hdmi_generic_subpack1_high;		/* _NV_PDISP_HDMI_GENERIC_SUBPACK1_HIGH */
+	uint nv_pdisp_hdmi_generic_subpack2_low;		/* _NV_PDISP_HDMI_GENERIC_SUBPACK2_LOW */
+	uint nv_pdisp_hdmi_generic_subpack2_high;		/* _NV_PDISP_HDMI_GENERIC_SUBPACK2_HIGH */
+	uint nv_pdisp_hdmi_generic_subpack3_low;		/* _NV_PDISP_HDMI_GENERIC_SUBPACK3_LOW */
+	uint nv_pdisp_hdmi_generic_subpack3_high;		/* _NV_PDISP_HDMI_GENERIC_SUBPACK3_HIGH */
+
+	uint nv_pdisp_hdmi_acr_ctrl;				/* _NV_PDISP_HDMI_ACR_CTRL */
+	uint nv_pdisp_hdmi_acr_0320_subpack_low;		/* _NV_PDISP_HDMI_ACR_0320_SUBPACK_LOW */
+	uint nv_pdisp_hdmi_acr_0320_subpack_high;		/* _NV_PDISP_HDMI_ACR_0320_SUBPACK_HIGH */
+	uint nv_pdisp_hdmi_acr_0441_subpack_low;		/* _NV_PDISP_HDMI_ACR_0441_SUBPACK_LOW */
+	uint nv_pdisp_hdmi_acr_0441_subpack_high;		/* _NV_PDISP_HDMI_ACR_0441_SUBPACK_HIGH */
+	uint nv_pdisp_hdmi_acr_0882_subpack_low;		/* _NV_PDISP_HDMI_ACR_0882_SUBPACK_LOW */
+	uint nv_pdisp_hdmi_acr_0882_subpack_high;		/* _NV_PDISP_HDMI_ACR_0882_SUBPACK_HIGH */
+	uint nv_pdisp_hdmi_acr_1764_subpack_low;		/* _NV_PDISP_HDMI_ACR_1764_SUBPACK_LOW */
+	uint nv_pdisp_hdmi_acr_1764_subpack_high;		/* _NV_PDISP_HDMI_ACR_1764_SUBPACK_HIGH */
+	uint nv_pdisp_hdmi_acr_0480_subpack_low;		/* _NV_PDISP_HDMI_ACR_0480_SUBPACK_LOW */
+	uint nv_pdisp_hdmi_acr_0480_subpack_high;		/* _NV_PDISP_HDMI_ACR_0480_SUBPACK_HIGH */
+	uint nv_pdisp_hdmi_acr_0960_subpack_low;		/* _NV_PDISP_HDMI_ACR_0960_SUBPACK_LOW */
+	uint nv_pdisp_hdmi_acr_0960_subpack_high;		/* _NV_PDISP_HDMI_ACR_0960_SUBPACK_HIGH */
+	uint nv_pdisp_hdmi_acr_1920_subpack_low;		/* _NV_PDISP_HDMI_ACR_1920_SUBPACK_LOW */
+	uint nv_pdisp_hdmi_acr_1920_subpack_high;		/* _NV_PDISP_HDMI_ACR_1920_SUBPACK_HIGH */
+
+	uint nv_pdisp_hdmi_ctrl;				/* _NV_PDISP_HDMI_CTRL */
+	uint nv_pdisp_hdmi_vsync_keepout;			/* _NV_PDISP_HDMI_VSYNC_KEEPOUT */
+	uint nv_pdisp_hdmi_vsync_window;			/* _NV_PDISP_HDMI_VSYNC_WINDOW */
+	uint nv_pdisp_hdmi_gcp_ctrl;				/* _NV_PDISP_HDMI_GCP_CTRL */
+	uint nv_pdisp_hdmi_gcp_status;				/* _NV_PDISP_HDMI_GCP_STATUS */
+	uint nv_pdisp_hdmi_gcp_subpack;				/* _NV_PDISP_HDMI_GCP_SUBPACK */
+	uint nv_pdisp_hdmi_channel_status1;			/* _NV_PDISP_HDMI_CHANNEL_STATUS1 */
+	uint nv_pdisp_hdmi_channel_status2;			/* _NV_PDISP_HDMI_CHANNEL_STATUS2 */
+	uint nv_pdisp_hdmi_emu0;				/* _NV_PDISP_HDMI_EMU0 */
+	uint nv_pdisp_hdmi_emu1;				/* _NV_PDISP_HDMI_EMU1 */
+	uint nv_pdisp_hdmi_emu1_rdata;				/* _NV_PDISP_HDMI_EMU1_RDATA */
+	uint nv_pdisp_hdmi_spare;				/* _NV_PDISP_HDMI_SPARE */
+	uint nv_pdisp_hdmi_spdif_chn_status1;			/* _NV_PDISP_HDMI_SPDIF_CHN_STATUS1 */
+	uint nv_pdisp_hdmi_spdif_chn_status2;			/* _NV_PDISP_HDMI_SPDIF_CHN_STATUS2 */
+
+	uint nv_pdisp_hdcprif_rom_ctrl;				/* _NV_PDISP_HDCPRIF_ROM_CTRL */
+
+	uint unused;
+
+	uint nv_pdisp_sor_cap;					/* _NV_PDISP_SOR_CAP */
+	uint nv_pdisp_sor_pwr;					/* _NV_PDISP_SOR_PWR */
+	uint nv_pdisp_sor_test;					/* _NV_PDISP_SOR_TEST */
+	uint nv_pdisp_sor_pll0;					/* _NV_PDISP_SOR_PLL0 */
+	uint nv_pdisp_sor_pll1;					/* _NV_PDISP_SOR_PLL1 */
+	uint nv_pdisp_sor_pll2;					/* _NV_PDISP_SOR_PLL2 */
+	uint nv_pdisp_sor_cstm;					/* _NV_PDISP_SOR_CSTM */
+	uint nv_pdisp_sor_lvds;					/* _NV_PDISP_SOR_LVDS */
+	uint nv_pdisp_sor_crca;					/* _NV_PDISP_SOR_CRCA */
+	uint nv_pdisp_sor_crcb;					/* _NV_PDISP_SOR_CRCB */
+	uint nv_pdisp_sor_blank;				/* _NV_PDISP_SOR_BLANK */
+
+	uint nv_pdisp_sor_seq_ctl;				/* _NV_PDISP_SOR_SEQ_CTL */
+	uint nv_pdisp_sor_seq_inst0;				/* _NV_PDISP_SOR_SEQ_INST0 */
+	uint nv_pdisp_sor_seq_inst1;				/* _NV_PDISP_SOR_SEQ_INST1 */
+	uint nv_pdisp_sor_seq_inst2;				/* _NV_PDISP_SOR_SEQ_INST2 */
+	uint nv_pdisp_sor_seq_inst3;				/* _NV_PDISP_SOR_SEQ_INST3 */
+	uint nv_pdisp_sor_seq_inst4;				/* _NV_PDISP_SOR_SEQ_INST4 */
+	uint nv_pdisp_sor_seq_inst5;				/* _NV_PDISP_SOR_SEQ_INST5 */
+	uint nv_pdisp_sor_seq_inst6;				/* _NV_PDISP_SOR_SEQ_INST6 */
+	uint nv_pdisp_sor_seq_inst7;				/* _NV_PDISP_SOR_SEQ_INST7 */
+	uint nv_pdisp_sor_seq_inst8;				/* _NV_PDISP_SOR_SEQ_INST8 */
+	uint nv_pdisp_sor_seq_inst9;				/* _NV_PDISP_SOR_SEQ_INST9 */
+	uint nv_pdisp_sor_seq_insta;				/* _NV_PDISP_SOR_SEQ_INSTA */
+	uint nv_pdisp_sor_seq_instb;				/* _NV_PDISP_SOR_SEQ_INSTB */
+	uint nv_pdisp_sor_seq_instc;				/* _NV_PDISP_SOR_SEQ_INSTC */
+	uint nv_pdisp_sor_seq_instd;				/* _NV_PDISP_SOR_SEQ_INSTD */
+	uint nv_pdisp_sor_seq_inste;				/* _NV_PDISP_SOR_SEQ_INSTE */
+	uint nv_pdisp_sor_seq_instf;				/* _NV_PDISP_SOR_SEQ_INSTF */
+
+	uint unused1[2];
+
+	uint nv_pdisp_sor_vcrca0;				/* _NV_PDISP_SOR_VCRCA0 */
+	uint nv_pdisp_sor_vcrca1;				/* _NV_PDISP_SOR_VCRCA1 */
+	uint nv_pdisp_sor_ccrca0;				/* _NV_PDISP_SOR_CCRCA0 */
+	uint nv_pdisp_sor_ccrca1;				/* _NV_PDISP_SOR_CCRCA1 */
+
+	uint nv_pdisp_sor_edataa0;				/* _NV_PDISP_SOR_EDATAA0 */
+	uint nv_pdisp_sor_edataa1;				/* _NV_PDISP_SOR_EDATAA1 */
+
+	uint nv_pdisp_sor_counta0;				/* _NV_PDISP_SOR_COUNTA0 */
+	uint nv_pdisp_sor_counta1;				/* _NV_PDISP_SOR_COUNTA1 */
+
+	uint nv_pdisp_sor_debuga0;				/* _NV_PDISP_SOR_DEBUGA0 */
+	uint nv_pdisp_sor_debuga1;				/* _NV_PDISP_SOR_DEBUGA1 */
+
+	uint nv_pdisp_sor_trig;					/* _NV_PDISP_SOR_TRIG */
+	uint nv_pdisp_sor_mscheck;				/* _NV_PDISP_SOR_MSCHECK */
+	uint nv_pdisp_sor_lane_drive_current;			/* _NV_PDISP_SOR_LANE_DRIVE_CURRENT */
+
+	uint nv_pdisp_audio_debug0;				/* _NV_PDISP_AUDIO_DEBUG0 0x7f */
+	uint nv_pdisp_audio_debug1;				/* _NV_PDISP_AUDIO_DEBUG1 0x80 */
+	uint nv_pdisp_audio_debug2;				/* _NV_PDISP_AUDIO_DEBUG2 0x81 */
+
+	uint nv_pdisp_audio_fs1;				/* _NV_PDISP_AUDIO_FS1 0x82 */
+	uint nv_pdisp_audio_fs2;				/* _NV_PDISP_AUDIO_FS2 */
+	uint nv_pdisp_audio_fs3;				/* _NV_PDISP_AUDIO_FS3 */
+	uint nv_pdisp_audio_fs4;				/* _NV_PDISP_AUDIO_FS4 */
+	uint nv_pdisp_audio_fs5;				/* _NV_PDISP_AUDIO_FS5 */
+	uint nv_pdisp_audio_fs6;				/* _NV_PDISP_AUDIO_FS6 */
+	uint nv_pdisp_audio_fs7;				/* _NV_PDISP_AUDIO_FS7 0x88 */
+
+	uint nv_pdisp_audio_pulse_width;			/* _NV_PDISP_AUDIO_PULSE_WIDTH */
+	uint nv_pdisp_audio_threshold;				/* _NV_PDISP_AUDIO_THRESHOLD */
+	uint nv_pdisp_audio_cntrl0;				/* _NV_PDISP_AUDIO_CNTRL0 */
+	uint nv_pdisp_audio_n;					/* _NV_PDISP_AUDIO_N */
+	uint nv_pdisp_audio_nval[7];				/* _NV_PDISP_AUDIO_NVAL */
+
+	uint nv_pdisp_hdcprif_rom_timing;			/* _NV_PDISP_HDCPRIF_ROM_TIMING */
+	uint nv_pdisp_sor_refclk;				/* _NV_PDISP_SOR_REFCLK */
+	uint nv_pdisp_crc_control;				/* _NV_PDISP_CRC_CONTROL */
+	uint nv_pdisp_input_control;				/* _NV_PDISP_INPUT_CONTROL */
+	uint nv_pdisp_scratch;					/* _NV_PDISP_SCRATCH */
+	uint nv_pdisp_pe_current;				/* _NV_PDISP_PE_CURRENT */
+
+	uint nv_pdisp_key_ctrl;					/* _NV_PDISP_KEY_CTRL */
+	uint nv_pdisp_key_debug0;				/* _NV_PDISP_KEY_DEBUG0 */
+	uint nv_pdisp_key_debug1;				/* _NV_PDISP_KEY_DEBUG1 */
+	uint nv_pdisp_key_debug2;				/* _NV_PDISP_KEY_DEBUG2 */
+	uint nv_pdisp_key_hdcp_key_0;				/* _NV_PDISP_KEY_HDCP_KEY_0 */
+	uint nv_pdisp_key_hdcp_key_1;				/* _NV_PDISP_KEY_HDCP_KEY_1 */
+	uint nv_pdisp_key_hdcp_key_2;				/* _NV_PDISP_KEY_HDCP_KEY_2 */
+	uint nv_pdisp_key_hdcp_key_3;				/* _NV_PDISP_KEY_HDCP_KEY_3 */
+	uint nv_pdisp_key_hdcp_key_trig;			/* _NV_PDISP_KEY_HDCP_KEY_3 */
+	uint nv_pdisp_key_skey_index;				/* _NV_PDISP_KEY_HDCP_KEY_3 */ /* 0xa3 */
+
+	uint unused2[8];
+
+	uint nv_pdisp_sor_audio_cntrl0;				/* _NV_PDISP_SOR_AUDIO_CNTRL0 */ /* 0xac */
+	uint nv_pdisp_sor_audio_debug;				/* _NV_PDISP_SOR_AUDIO_DEBUG */
+	uint nv_pdisp_sor_audio_spare0;				/* _NV_PDISP_SOR_AUDIO_SPARE0 */
+	uint nv_pdisp_sor_audio_nval[7];			/* _NV_PDISP_SOR_AUDIO_NVAL 0xaf ~ 0xb5 */
+	uint nv_pdisp_sor_audio_hda_scratch[4];			/* _NV_PDISP_SOR_AUDIO_HDA_SCRATCH 0xb6 ~ 0xb9 */
+	uint nv_pdisp_sor_audio_hda_codec_scratch[2];		/* _NV_PDISP_SOR_AUDIO_HDA_CODEC_SCRATCH 0xba ~ 0xbb */
+
+	uint nv_pdisp_sor_audio_hda_eld_bufwr;			/* _NV_PDISP_SOR_AUDIO_HDA_ELD_BUFWR */
+	uint nv_pdisp_sor_audio_hda_presense;			/* _NV_PDISP_SOR_AUDIO_HDA_PRESENSE */
+	uint nv_pdisp_sor_audio_hda_cp;				/* _NV_PDISP_SOR_AUDIO_HDA_CP */
+	uint nv_pdisp_sor_audio_aval[8];			/* _NV_PDISP_SOR_AUDIO_AVAL */
+	uint nv_pdisp_sor_audio_gen_ctrl;			/* _NV_PDISP_SOR_AUDIO_GEN_CTRL */
+
+	uint unused3[4];
+
+	uint nv_pdisp_int_status;				/* _NV_PDISP_INT_STATUS */
+	uint nv_pdisp_int_mask;					/* _NV_PDISP_INT_MASK */
+	uint nv_pdisp_int_enable;				/* _NV_PDISP_INT_ENABLE */
+
+	uint unused4[2];
+
+	uint nv_pdisp_sor_io_peak_current;			/* _NV_PDISP_SOR_IO_PEAK_CURRENT */
+	uint nv_pdisp_sor_pad_ctls0;				/* _NV_PDISP_SOR_PAD_CTLS0 */
+};
+
+/* HDMI_NV_PDISP_SOR_STATE0	0x01 */
+#define SOR_STATE_UPDATE			BIT(0)
+
+/* HDMI_NV_PDISP_SOR_STATE1	0x02 */
+#define SOR_STATE_ASY_HEAD_OPMODE_AWAKE		BIT(1)
+#define SOR_STATE_ASY_ORMODE_NORMAL		BIT(2)
+#define SOR_STATE_ATTACHED			BIT(3)
+
+/* HDMI_NV_PDISP_SOR_STATE2	0x03 */
+#define SOR_STATE_ASY_OWNER_NONE		(0 << 0)
+#define SOR_STATE_ASY_OWNER_HEAD0		(1 << 0)
+#define SOR_STATE_ASY_SUBOWNER_NONE		(0 << 4)
+#define SOR_STATE_ASY_SUBOWNER_SUBHEAD0		(1 << 4)
+#define SOR_STATE_ASY_SUBOWNER_SUBHEAD1		(2 << 4)
+#define SOR_STATE_ASY_SUBOWNER_BOTH		(3 << 4)
+#define SOR_STATE_ASY_CRCMODE_ACTIVE		(0 << 6)
+#define SOR_STATE_ASY_CRCMODE_COMPLETE		(1 << 6)
+#define SOR_STATE_ASY_CRCMODE_NON_ACTIVE	(2 << 6)
+#define SOR_STATE_ASY_PROTOCOL_SINGLE_TMDS_A	(1 << 8)
+#define SOR_STATE_ASY_PROTOCOL_CUSTOM		(15 << 8)
+#define SOR_STATE_ASY_HSYNCPOL_POS		(0 << 12)
+#define SOR_STATE_ASY_HSYNCPOL_NEG		(1 << 12)
+#define SOR_STATE_ASY_VSYNCPOL_POS		(0 << 13)
+#define SOR_STATE_ASY_VSYNCPOL_NEG		(1 << 13)
+#define SOR_STATE_ASY_DEPOL_POS			(0 << 14)
+#define SOR_STATE_ASY_DEPOL_NEG			(1 << 14)
+
+#define INFOFRAME_CTRL_ENABLE			BIT(0)
+#define INFOFRAME_HEADER_TYPE(x)		(((x) & 0xff) <<  0)
+#define INFOFRAME_HEADER_VERSION(x)		(((x) & 0xff) <<  8)
+#define INFOFRAME_HEADER_LEN(x)			(((x) & 0x0f) << 16)
+
+/* HDMI_NV_PDISP_HDMI_GENERIC_CTRL	0x2a */
+#define GENERIC_CTRL_ENABLE			BIT(0)
+#define GENERIC_CTRL_OTHER			BIT(4)
+#define GENERIC_CTRL_SINGLE			BIT(8)
+#define GENERIC_CTRL_HBLANK			BIT(12)
+#define GENERIC_CTRL_AUDIO			BIT(16)
+
+/* HDMI_NV_PDISP_HDMI_ACR_* */
+#define ACR_SUBPACK_CTS(x)			(((x) & 0xffffff) << 8)
+#define ACR_SUBPACK_N(x)			(((x) & 0xffffff) << 0)
+#define ACR_ENABLE				BIT(31)
+
+/* HDMI_NV_PDISP_HDMI_CTRL	0x44 */
+#define HDMI_CTRL_REKEY(x)			(((x) & 0x7f) <<  0)
+#define HDMI_CTRL_MAX_AC_PACKET(x)		(((x) & 0x1f) << 16)
+#define HDMI_CTRL_ENABLE			BIT(30)
+
+/* HDMI_NV_PDISP_HDMI_VSYNC_* */
+#define VSYNC_WINDOW_END(x)			(((x) & 0x3ff) <<  0)
+#define VSYNC_WINDOW_START(x)			(((x) & 0x3ff) << 16)
+#define VSYNC_WINDOW_ENABLE			BIT(31)
+
+/* HDMI_NV_PDISP_HDMI_SPARE	0x4f */
+#define SPARE_HW_CTS				BIT(0)
+#define SPARE_FORCE_SW_CTS			BIT(1)
+#define SPARE_CTS_RESET_VAL(x)			(((x) & 0x7) << 16)
+
+/* HDMI_NV_PDISP_SOR_PWR	0x55 */
+#define SOR_PWR_NORMAL_STATE_PD			(0 <<  0)
+#define SOR_PWR_NORMAL_STATE_PU			(1 <<  0)
+#define SOR_PWR_NORMAL_START_NORMAL		(0 <<  1)
+#define SOR_PWR_NORMAL_START_ALT		(1 <<  1)
+#define SOR_PWR_SAFE_STATE_PD			(0 << 16)
+#define SOR_PWR_SAFE_STATE_PU			(1 << 16)
+#define SOR_PWR_SETTING_NEW_DONE		(0 << 31)
+#define SOR_PWR_SETTING_NEW_PENDING		(1 << 31)
+#define SOR_PWR_SETTING_NEW_TRIGGER		(1 << 31)
+
+/* HDMI_NV_PDISP_SOR_PLL0	0x57 */
+#define SOR_PLL_PWR				BIT(0)
+#define SOR_PLL_PDBG				BIT(1)
+#define SOR_PLL_VCAPD				BIT(2)
+#define SOR_PLL_PDPORT				BIT(3)
+#define SOR_PLL_RESISTORSEL			BIT(4)
+#define SOR_PLL_PULLDOWN			BIT(5)
+#define SOR_PLL_VCOCAP(x)			(((x) & 0xf) <<  8)
+#define SOR_PLL_BG_V17_S(x)			(((x) & 0xf) << 12)
+#define SOR_PLL_FILTER(x)			(((x) & 0xf) << 16)
+#define SOR_PLL_ICHPMP(x)			(((x) & 0xf) << 24)
+#define SOR_PLL_TX_REG_LOAD(x)			(((x) & 0xf) << 28)
+
+/* HDMI_NV_PDISP_SOR_PLL1	0x58 */
+#define SOR_PLL_TMDS_TERM_ENABLE		BIT(8)
+#define SOR_PLL_TMDS_TERMADJ(x)			(((x) & 0xf) <<  9)
+#define SOR_PLL_LOADADJ(x)			(((x) & 0xf) << 20)
+#define SOR_PLL_PE_EN				BIT(28)
+#define SOR_PLL_HALF_FULL_PE			BIT(29)
+#define SOR_PLL_S_D_PIN_PE			BIT(30)
+
+/* HDMI_NV_PDISP_SOR_CSTM	0x5a */
+#define SOR_CSTM_ROTCLK(x)			(((x) & 0xf) << 24)
+#define SOR_CSTM_PLLDIV				BIT(21)
+#define SOR_CSTM_LVDS_ENABLE			BIT(16)
+#define SOR_CSTM_MODE_LVDS			(0 << 12)
+#define SOR_CSTM_MODE_TMDS			(1 << 12)
+#define SOR_CSTM_MODE_MASK			(3 << 12)
+
+/* HDMI_NV_PDISP_SOR_SEQ_CTL	0x5f */
+#define SOR_SEQ_PU_PC(x)			(((x) & 0xf) <<  0)
+#define SOR_SEQ_PU_PC_ALT(x)			(((x) & 0xf) <<  4)
+#define SOR_SEQ_PD_PC(x)			(((x) & 0xf) <<  8)
+#define SOR_SEQ_PD_PC_ALT(x)			(((x) & 0xf) << 12)
+#define SOR_SEQ_PC(x)				(((x) & 0xf) << 16)
+#define SOR_SEQ_STATUS				BIT(28)
+#define SOR_SEQ_SWITCH				BIT(30)
+
+/* HDMI_NV_PDISP_SOR_SEQ_INST(x)	(0x60 + (x)) */
+#define SOR_SEQ_INST_WAIT_TIME(x)		(((x) & 0x3ff) << 0)
+#define SOR_SEQ_INST_WAIT_UNITS_VSYNC		(2 << 12)
+#define SOR_SEQ_INST_HALT			(1 << 15)
+#define SOR_SEQ_INST_PIN_A_LOW			(0 << 21)
+#define SOR_SEQ_INST_PIN_A_HIGH			(1 << 21)
+#define SOR_SEQ_INST_PIN_B_LOW			(0 << 22)
+#define SOR_SEQ_INST_PIN_B_HIGH			(1 << 22)
+#define SOR_SEQ_INST_DRIVE_PWM_OUT_LO		(1 << 23)
+
+/* HDMI_NV_PDISP_SOR_LANE_DRIVE_CURRENT	0x7e */
+#define DRIVE_CURRENT_LANE0(x)			(((x) & 0x3f) <<  0)
+#define DRIVE_CURRENT_LANE1(x)			(((x) & 0x3f) <<  8)
+#define DRIVE_CURRENT_LANE2(x)			(((x) & 0x3f) << 16)
+#define DRIVE_CURRENT_LANE3(x)			(((x) & 0x3f) << 24)
+#define DRIVE_CURRENT_LANE0_T114(x)		(((x) & 0x7f) <<  0)
+#define DRIVE_CURRENT_LANE1_T114(x)		(((x) & 0x7f) <<  8)
+#define DRIVE_CURRENT_LANE2_T114(x)		(((x) & 0x7f) << 16)
+#define DRIVE_CURRENT_LANE3_T114(x)		(((x) & 0x7f) << 24)
+
+/* Drive current list */
+enum {
+	DRIVE_CURRENT_1_500_mA,
+	DRIVE_CURRENT_1_875_mA,
+	DRIVE_CURRENT_2_250_mA,
+	DRIVE_CURRENT_2_625_mA,
+	DRIVE_CURRENT_3_000_mA,
+	DRIVE_CURRENT_3_375_mA,
+	DRIVE_CURRENT_3_750_mA,
+	DRIVE_CURRENT_4_125_mA,
+	DRIVE_CURRENT_4_500_mA,
+	DRIVE_CURRENT_4_875_mA,
+	DRIVE_CURRENT_5_250_mA,
+	DRIVE_CURRENT_5_625_mA,
+	DRIVE_CURRENT_6_000_mA,
+	DRIVE_CURRENT_6_375_mA,
+	DRIVE_CURRENT_6_750_mA,
+	DRIVE_CURRENT_7_125_mA,
+	DRIVE_CURRENT_7_500_mA,
+	DRIVE_CURRENT_7_875_mA,
+	DRIVE_CURRENT_8_250_mA,
+	DRIVE_CURRENT_8_625_mA,
+	DRIVE_CURRENT_9_000_mA,
+	DRIVE_CURRENT_9_375_mA,
+	DRIVE_CURRENT_9_750_mA,
+	DRIVE_CURRENT_10_125_mA,
+	DRIVE_CURRENT_10_500_mA,
+	DRIVE_CURRENT_10_875_mA,
+	DRIVE_CURRENT_11_250_mA,
+	DRIVE_CURRENT_11_625_mA,
+	DRIVE_CURRENT_12_000_mA,
+	DRIVE_CURRENT_12_375_mA,
+	DRIVE_CURRENT_12_750_mA,
+	DRIVE_CURRENT_13_125_mA,
+	DRIVE_CURRENT_13_500_mA,
+	DRIVE_CURRENT_13_875_mA,
+	DRIVE_CURRENT_14_250_mA,
+	DRIVE_CURRENT_14_625_mA,
+	DRIVE_CURRENT_15_000_mA,
+	DRIVE_CURRENT_15_375_mA,
+	DRIVE_CURRENT_15_750_mA,
+	DRIVE_CURRENT_16_125_mA,
+	DRIVE_CURRENT_16_500_mA,
+	DRIVE_CURRENT_16_875_mA,
+	DRIVE_CURRENT_17_250_mA,
+	DRIVE_CURRENT_17_625_mA,
+	DRIVE_CURRENT_18_000_mA,
+	DRIVE_CURRENT_18_375_mA,
+	DRIVE_CURRENT_18_750_mA,
+	DRIVE_CURRENT_19_125_mA,
+	DRIVE_CURRENT_19_500_mA,
+	DRIVE_CURRENT_19_875_mA,
+	DRIVE_CURRENT_20_250_mA,
+	DRIVE_CURRENT_20_625_mA,
+	DRIVE_CURRENT_21_000_mA,
+	DRIVE_CURRENT_21_375_mA,
+	DRIVE_CURRENT_21_750_mA,
+	DRIVE_CURRENT_22_125_mA,
+	DRIVE_CURRENT_22_500_mA,
+	DRIVE_CURRENT_22_875_mA,
+	DRIVE_CURRENT_23_250_mA,
+	DRIVE_CURRENT_23_625_mA,
+	DRIVE_CURRENT_24_000_mA,
+	DRIVE_CURRENT_24_375_mA,
+	DRIVE_CURRENT_24_750_mA,
+};
+
+/* Drive current list for T114 */
+enum {
+	DRIVE_CURRENT_0_000_mA_T114,
+	DRIVE_CURRENT_0_400_mA_T114,
+	DRIVE_CURRENT_0_800_mA_T114,
+	DRIVE_CURRENT_1_200_mA_T114,
+	DRIVE_CURRENT_1_600_mA_T114,
+	DRIVE_CURRENT_2_000_mA_T114,
+	DRIVE_CURRENT_2_400_mA_T114,
+	DRIVE_CURRENT_2_800_mA_T114,
+	DRIVE_CURRENT_3_200_mA_T114,
+	DRIVE_CURRENT_3_600_mA_T114,
+	DRIVE_CURRENT_4_000_mA_T114,
+	DRIVE_CURRENT_4_400_mA_T114,
+	DRIVE_CURRENT_4_800_mA_T114,
+	DRIVE_CURRENT_5_200_mA_T114,
+	DRIVE_CURRENT_5_600_mA_T114,
+	DRIVE_CURRENT_6_000_mA_T114,
+	DRIVE_CURRENT_6_400_mA_T114,
+	DRIVE_CURRENT_6_800_mA_T114,
+	DRIVE_CURRENT_7_200_mA_T114,
+	DRIVE_CURRENT_7_600_mA_T114,
+	DRIVE_CURRENT_8_000_mA_T114,
+	DRIVE_CURRENT_8_400_mA_T114,
+	DRIVE_CURRENT_8_800_mA_T114,
+	DRIVE_CURRENT_9_200_mA_T114,
+	DRIVE_CURRENT_9_600_mA_T114,
+	DRIVE_CURRENT_10_000_mA_T114,
+	DRIVE_CURRENT_10_400_mA_T114,
+	DRIVE_CURRENT_10_800_mA_T114,
+	DRIVE_CURRENT_11_200_mA_T114,
+	DRIVE_CURRENT_11_600_mA_T114,
+	DRIVE_CURRENT_12_000_mA_T114,
+	DRIVE_CURRENT_12_400_mA_T114,
+	DRIVE_CURRENT_12_800_mA_T114,
+	DRIVE_CURRENT_13_200_mA_T114,
+	DRIVE_CURRENT_13_600_mA_T114,
+	DRIVE_CURRENT_14_000_mA_T114,
+	DRIVE_CURRENT_14_400_mA_T114,
+	DRIVE_CURRENT_14_800_mA_T114,
+	DRIVE_CURRENT_15_200_mA_T114,
+	DRIVE_CURRENT_15_600_mA_T114,
+	DRIVE_CURRENT_16_000_mA_T114,
+	DRIVE_CURRENT_16_400_mA_T114,
+	DRIVE_CURRENT_16_800_mA_T114,
+	DRIVE_CURRENT_17_200_mA_T114,
+	DRIVE_CURRENT_17_600_mA_T114,
+	DRIVE_CURRENT_18_000_mA_T114,
+	DRIVE_CURRENT_18_400_mA_T114,
+	DRIVE_CURRENT_18_800_mA_T114,
+	DRIVE_CURRENT_19_200_mA_T114,
+	DRIVE_CURRENT_19_600_mA_T114,
+	DRIVE_CURRENT_20_000_mA_T114,
+	DRIVE_CURRENT_20_400_mA_T114,
+	DRIVE_CURRENT_20_800_mA_T114,
+	DRIVE_CURRENT_21_200_mA_T114,
+	DRIVE_CURRENT_21_600_mA_T114,
+	DRIVE_CURRENT_22_000_mA_T114,
+	DRIVE_CURRENT_22_400_mA_T114,
+	DRIVE_CURRENT_22_800_mA_T114,
+	DRIVE_CURRENT_23_200_mA_T114,
+	DRIVE_CURRENT_23_600_mA_T114,
+	DRIVE_CURRENT_24_000_mA_T114,
+	DRIVE_CURRENT_24_400_mA_T114,
+	DRIVE_CURRENT_24_800_mA_T114,
+	DRIVE_CURRENT_25_200_mA_T114,
+	DRIVE_CURRENT_25_400_mA_T114,
+	DRIVE_CURRENT_25_800_mA_T114,
+	DRIVE_CURRENT_26_200_mA_T114,
+	DRIVE_CURRENT_26_600_mA_T114,
+	DRIVE_CURRENT_27_000_mA_T114,
+	DRIVE_CURRENT_27_400_mA_T114,
+	DRIVE_CURRENT_27_800_mA_T114,
+	DRIVE_CURRENT_28_200_mA_T114,
+};
+
+/* HDMI_NV_PDISP_AUDIO_FS */
+#define AUDIO_FS_LOW(x)				(((x) & 0xfff) <<  0)
+#define AUDIO_FS_HIGH(x)			(((x) & 0xfff) << 16)
+
+/* HDMI_NV_PDISP_AUDIO_CNTRL0	0x8b */
+#define AUDIO_CNTRL0_ERROR_TOLERANCE(x)		(((x) & 0xff) << 0)
+#define AUDIO_CNTRL0_SOURCE_SELECT_AUTO		(0 << 20)
+#define AUDIO_CNTRL0_SOURCE_SELECT_SPDIF	(1 << 20)
+#define AUDIO_CNTRL0_SOURCE_SELECT_HDAL		(2 << 20)
+#define AUDIO_CNTRL0_FRAMES_PER_BLOCK(x)	(((x) & 0xff) << 24)
+
+/* HDMI_NV_PDISP_AUDIO_N	0x8c */
+#define AUDIO_N_VALUE(x)			(((x) & 0xfffff) << 0)
+#define AUDIO_N_RESETF				(1 << 20)
+#define AUDIO_N_GENERATE_NORMAL			(0 << 24)
+#define AUDIO_N_GENERATE_ALTERNATE		(1 << 24)
+
+/* HDMI_NV_PDISP_SOR_REFCLK	0x95 */
+#define SOR_REFCLK_DIV_INT(x)			(((x) & 0xff) << 8)
+#define SOR_REFCLK_DIV_FRAC(x)			(((x) & 0x03) << 6)
+
+/* HDMI_NV_PDISP_INPUT_CONTROL	0x97 */
+#define HDMI_SRC_DISPLAYA			(0 << 0)
+#define HDMI_SRC_DISPLAYB			(1 << 0)
+#define ARM_VIDEO_RANGE_FULL			(0 << 1)
+#define ARM_VIDEO_RANGE_LIMITED			(1 << 1)
+
+/* HDMI_NV_PDISP_PE_CURRENT	0x99 */
+#define PE_CURRENT0(x)				(((x) & 0xf) << 0)
+#define PE_CURRENT1(x)				(((x) & 0xf) << 8)
+#define PE_CURRENT2(x)				(((x) & 0xf) << 16)
+#define PE_CURRENT3(x)				(((x) & 0xf) << 24)
+
+enum {
+	PE_CURRENT_0_0_mA,
+	PE_CURRENT_0_5_mA,
+	PE_CURRENT_1_0_mA,
+	PE_CURRENT_1_5_mA,
+	PE_CURRENT_2_0_mA,
+	PE_CURRENT_2_5_mA,
+	PE_CURRENT_3_0_mA,
+	PE_CURRENT_3_5_mA,
+	PE_CURRENT_4_0_mA,
+	PE_CURRENT_4_5_mA,
+	PE_CURRENT_5_0_mA,
+	PE_CURRENT_5_5_mA,
+	PE_CURRENT_6_0_mA,
+	PE_CURRENT_6_5_mA,
+	PE_CURRENT_7_0_mA,
+	PE_CURRENT_7_5_mA,
+};
+
+enum {
+	PE_CURRENT_0_mA_T114,
+	PE_CURRENT_1_mA_T114,
+	PE_CURRENT_2_mA_T114,
+	PE_CURRENT_3_mA_T114,
+	PE_CURRENT_4_mA_T114,
+	PE_CURRENT_5_mA_T114,
+	PE_CURRENT_6_mA_T114,
+	PE_CURRENT_7_mA_T114,
+	PE_CURRENT_8_mA_T114,
+	PE_CURRENT_9_mA_T114,
+	PE_CURRENT_10_mA_T114,
+	PE_CURRENT_11_mA_T114,
+	PE_CURRENT_12_mA_T114,
+	PE_CURRENT_13_mA_T114,
+	PE_CURRENT_14_mA_T114,
+	PE_CURRENT_15_mA_T114,
+};
+
+/* HDMI_NV_PDISP_SOR_AUDIO_CNTRL0	0xac */
+#define SOR_AUDIO_CNTRL0_SOURCE_SELECT_AUTO	(0 << 20)
+#define SOR_AUDIO_CNTRL0_SOURCE_SELECT_SPDIF	(1 << 20)
+#define SOR_AUDIO_CNTRL0_SOURCE_SELECT_HDAL	(2 << 20)
+#define SOR_AUDIO_CNTRL0_INJECT_NULLSMPL	(1 << 29)
+
+/* HDMI_NV_PDISP_SOR_AUDIO_SPARE0	0xae */
+#define SOR_AUDIO_SPARE0_HBR_ENABLE		BIT(27)
+
+/* HDMI_NV_PDISP_SOR_AUDIO_HDA_CODEC_SCRATCH0	0xba */
+#define SOR_AUDIO_HDA_CODEC_SCRATCH0_VALID	BIT(30)
+#define SOR_AUDIO_HDA_CODEC_SCRATCH0_FMT_MASK	0xffff
+
+/* HDMI_NV_PDISP_SOR_AUDIO_HDA_PRESENSE	0xbd */
+#define SOR_AUDIO_HDA_PRESENSE_VALID		BIT(1)
+#define SOR_AUDIO_HDA_PRESENSE_PRESENT		BIT(0)
+
+/* HDMI_NV_PDISP_INT_STATUS		0xcc */
+#define INT_SCRATCH				BIT(3)
+#define INT_CP_REQUEST				BIT(2)
+#define INT_CODEC_SCRATCH1			BIT(1)
+#define INT_CODEC_SCRATCH0			BIT(0)
+
+/* HDMI_NV_PDISP_SOR_IO_PEAK_CURRENT	0xd1 */
+#define PEAK_CURRENT_LANE0(x)			(((x) & 0x7f) <<  0)
+#define PEAK_CURRENT_LANE1(x)			(((x) & 0x7f) <<  8)
+#define PEAK_CURRENT_LANE2(x)			(((x) & 0x7f) << 16)
+#define PEAK_CURRENT_LANE3(x)			(((x) & 0x7f) << 24)
+
+enum {
+	PEAK_CURRENT_0_000_mA,
+	PEAK_CURRENT_0_200_mA,
+	PEAK_CURRENT_0_400_mA,
+	PEAK_CURRENT_0_600_mA,
+	PEAK_CURRENT_0_800_mA,
+	PEAK_CURRENT_1_000_mA,
+	PEAK_CURRENT_1_200_mA,
+	PEAK_CURRENT_1_400_mA,
+	PEAK_CURRENT_1_600_mA,
+	PEAK_CURRENT_1_800_mA,
+	PEAK_CURRENT_2_000_mA,
+	PEAK_CURRENT_2_200_mA,
+	PEAK_CURRENT_2_400_mA,
+	PEAK_CURRENT_2_600_mA,
+	PEAK_CURRENT_2_800_mA,
+	PEAK_CURRENT_3_000_mA,
+	PEAK_CURRENT_3_200_mA,
+	PEAK_CURRENT_3_400_mA,
+	PEAK_CURRENT_3_600_mA,
+	PEAK_CURRENT_3_800_mA,
+	PEAK_CURRENT_4_000_mA,
+	PEAK_CURRENT_4_200_mA,
+	PEAK_CURRENT_4_400_mA,
+	PEAK_CURRENT_4_600_mA,
+	PEAK_CURRENT_4_800_mA,
+	PEAK_CURRENT_5_000_mA,
+	PEAK_CURRENT_5_200_mA,
+	PEAK_CURRENT_5_400_mA,
+	PEAK_CURRENT_5_600_mA,
+	PEAK_CURRENT_5_800_mA,
+	PEAK_CURRENT_6_000_mA,
+	PEAK_CURRENT_6_200_mA,
+	PEAK_CURRENT_6_400_mA,
+	PEAK_CURRENT_6_600_mA,
+	PEAK_CURRENT_6_800_mA,
+	PEAK_CURRENT_7_000_mA,
+	PEAK_CURRENT_7_200_mA,
+	PEAK_CURRENT_7_400_mA,
+	PEAK_CURRENT_7_600_mA,
+	PEAK_CURRENT_7_800_mA,
+	PEAK_CURRENT_8_000_mA,
+	PEAK_CURRENT_8_200_mA,
+	PEAK_CURRENT_8_400_mA,
+	PEAK_CURRENT_8_600_mA,
+	PEAK_CURRENT_8_800_mA,
+	PEAK_CURRENT_9_000_mA,
+	PEAK_CURRENT_9_200_mA,
+	PEAK_CURRENT_9_400_mA,
+};
+
+#endif /* _TEGRA_HDMI_H */
diff --git a/drivers/video/tegra20/tegra-host1x.c b/drivers/video/tegra20/tegra-host1x.c
new file mode 100644
index 00000000000..58ab871a3b4
--- /dev/null
+++ b/drivers/video/tegra20/tegra-host1x.c
@@ -0,0 +1,86 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2025 Svyatoslav Ryhel <clamor95@gmail.com>
+ */
+
+#include <dm.h>
+#include <clk.h>
+#include <log.h>
+#include <reset.h>
+#include <linux/delay.h>
+
+#include <asm/arch/clock.h>
+#include <asm/arch-tegra/clk_rst.h>
+
+struct tegra_host1x_info {
+	u32 clk_parent;
+	u32 rate;
+};
+
+static int tegra_host1x_probe(struct udevice *dev)
+{
+	struct clk *clk;
+	struct reset_ctl reset_ctl;
+	const struct tegra_host1x_info *info;
+	int ret;
+
+	clk = devm_clk_get(dev, NULL);
+	if (IS_ERR(clk)) {
+		log_debug("%s: cannot get HOST1X clock: %ld\n",
+			  __func__, PTR_ERR(clk));
+		return PTR_ERR(clk);
+	}
+
+	ret = reset_get_by_name(dev, "host1x", &reset_ctl);
+	if (ret) {
+		log_debug("%s: cannot get HOST1X reset: %d\n",
+			  __func__, ret);
+		return ret;
+	}
+
+	info = (struct tegra_host1x_info *)dev_get_driver_data(dev);
+
+	reset_assert(&reset_ctl);
+	clock_start_periph_pll(clk->id, info->clk_parent, info->rate);
+
+	mdelay(2);
+	reset_deassert(&reset_ctl);
+
+	return 0;
+}
+
+static const struct tegra_host1x_info tegra20_host1x_info = {
+	.clk_parent = CLOCK_ID_CGENERAL,
+	.rate = 150000000, /* 150 MHz */
+};
+
+static const struct tegra_host1x_info tegra114_host1x_info = {
+	.clk_parent = CLOCK_ID_PERIPH,
+	.rate = 136000000, /* 136 MHz */
+};
+
+static const struct udevice_id tegra_host1x_ids[] = {
+	{
+		.compatible = "nvidia,tegra20-host1x",
+		.data = (ulong)&tegra20_host1x_info
+	}, {
+		.compatible = "nvidia,tegra30-host1x",
+		.data = (ulong)&tegra20_host1x_info
+	}, {
+		.compatible = "nvidia,tegra114-host1x",
+		.data = (ulong)&tegra114_host1x_info
+	}, {
+		.compatible = "nvidia,tegra124-host1x",
+		.data = (ulong)&tegra114_host1x_info
+	}, {
+		/* sentinel */
+	}
+};
+
+U_BOOT_DRIVER(tegra_host1x) = {
+	.name		= "tegra_host1x",
+	.id		= UCLASS_SIMPLE_BUS,
+	.of_match	= tegra_host1x_ids,
+	.probe		= tegra_host1x_probe,
+	.flags		= DM_FLAG_PRE_RELOC,
+};
diff --git a/drivers/video/tegra20/tegra-mipi.c b/drivers/video/tegra20/tegra-mipi.c
index 2df3c1a9942..a4f4343d008 100644
--- a/drivers/video/tegra20/tegra-mipi.c
+++ b/drivers/video/tegra20/tegra-mipi.c
@@ -10,9 +10,10 @@
 #include <linux/delay.h>
 #include <linux/iopoll.h>
 
+#include <asm/arch/clock.h>
 #include <asm/io.h>
 
-/* MIPI control registers 0x00 ~ 0x60 */
+/* MIPI control registers 0x00 ~ 0x74 */
 struct mipi_ctlr {
 	uint mipi_cal_ctrl;
 	uint mipi_cal_autocal_ctrl;
@@ -38,8 +39,17 @@ struct mipi_ctlr {
 	uint mipi_cal_bias_pad_cfg0;
 	uint mipi_cal_bias_pad_cfg1;
 	uint mipi_cal_bias_pad_cfg2;
+
+	uint mipi_cal_dsia_config_2;
+	uint mipi_cal_dsib_config_2;
+	uint mipi_cal_cilc_config_2;
+	uint mipi_cal_cild_config_2;
+	uint mipi_cal_csie_config_2;
 };
 
+#define MIPI_DSIA_PADS			0x60
+#define MIPI_DSIB_PADS			0x180
+
 #define MIPI_CAL_CTRL_NOISE_FILTER(x)	(((x) & 0xf) << 26)
 #define MIPI_CAL_CTRL_PRESCALE(x)	(((x) & 0x3) << 24)
 #define MIPI_CAL_CTRL_CLKEN_OVR		BIT(4)
@@ -64,26 +74,25 @@ struct mipi_ctlr {
 #define MIPI_CAL_BIAS_PAD_VAUXP(x)	(((x) & 0x7) << 4)
 #define MIPI_CAL_BIAS_PAD_PDVREG	BIT(1)
 
+#define MIPI_CAL_HSCLKPDOSDSI(x)	(((x) & 0x1f) << 8)
+#define MIPI_CAL_HSCLKPUOSDSI(x)	(((x) & 0x1f) << 0)
+
 struct tegra_mipi_priv {
 	struct mipi_ctlr	*mipi;
 	struct clk		*mipi_cal;
+	u32 version;
 };
 
-static int tegra_mipi_calibrate(struct udevice *dev, int offset, const void *buf,
-				int size)
+enum {
+	T114,
+	T124,
+};
+
+static void tegra114_mipi_pads_cal(struct tegra_mipi_priv *priv,
+				   int calibration_pads)
 {
-	struct tegra_mipi_priv *priv = dev_get_priv(dev);
 	u32 value;
 
-	value = MIPI_CAL_BIAS_PAD_DRV_DN_REF(0x2) |
-		MIPI_CAL_BIAS_PAD_DRV_UP_REF(0x0);
-	writel(value, &priv->mipi->mipi_cal_bias_pad_cfg1);
-
-	value = readl(&priv->mipi->mipi_cal_bias_pad_cfg2);
-	value &= ~MIPI_CAL_BIAS_PAD_VCLAMP(0x7);
-	value &= ~MIPI_CAL_BIAS_PAD_VAUXP(0x7);
-	writel(value, &priv->mipi->mipi_cal_bias_pad_cfg2);
-
 	value = MIPI_CAL_OVERIDE(0x0) | MIPI_CAL_SEL(0x1) |
 		MIPI_CAL_HSPDOS(0x0) | MIPI_CAL_HSPUOS(0x4) |
 		MIPI_CAL_TERMOS(0x5);
@@ -99,6 +108,95 @@ static int tegra_mipi_calibrate(struct udevice *dev, int offset, const void *buf
 	value = readl(&priv->mipi->mipi_cal_config_dsid);
 	value &= ~(MIPI_CAL_SEL(0x1));
 	writel(value, &priv->mipi->mipi_cal_config_dsid);
+}
+
+static void tegra124_mipi_pads_cal(struct tegra_mipi_priv *priv,
+				   int calibration_pads)
+{
+	u32 value;
+
+	/* Calibrate DSI-A */
+	if (calibration_pads == MIPI_DSIA_PADS) {
+		printf("Calibrating DSI-A pads\n");
+
+		value = MIPI_CAL_OVERIDE(0x0) | MIPI_CAL_SEL(0x1) |
+			MIPI_CAL_HSPDOS(0x0) | MIPI_CAL_HSPUOS(0x0) |
+			MIPI_CAL_TERMOS(0x0);
+		writel(value, &priv->mipi->mipi_cal_config_dsia);
+		writel(value, &priv->mipi->mipi_cal_config_dsib);
+
+		value = MIPI_CAL_SEL(0x1) |
+			MIPI_CAL_HSCLKPDOSDSI(0x1) |
+			MIPI_CAL_HSCLKPUOSDSI(0x2);
+		writel(value, &priv->mipi->mipi_cal_dsia_config_2);
+		writel(value, &priv->mipi->mipi_cal_dsib_config_2);
+
+		/* Deselect PAD C */
+		value = readl(&priv->mipi->mipi_cal_cilc_config_2);
+		value &= ~(MIPI_CAL_SEL(0x1));
+		writel(value, &priv->mipi->mipi_cal_cilc_config_2);
+
+		/* Deselect PAD D */
+		value = readl(&priv->mipi->mipi_cal_cild_config_2);
+		value &= ~(MIPI_CAL_SEL(0x1));
+		writel(value, &priv->mipi->mipi_cal_cild_config_2);
+	}
+
+	/* Calibrate DSI-B */
+	if (calibration_pads == MIPI_DSIB_PADS) {
+		printf("Calibrating DSI-B pads\n");
+
+		value = MIPI_CAL_OVERIDE(0x0) | MIPI_CAL_SEL(0x1) |
+			MIPI_CAL_HSPDOS(0x0) | MIPI_CAL_HSPUOS(0x0) |
+			MIPI_CAL_TERMOS(0x0);
+		writel(value, &priv->mipi->mipi_cal_config_csic);
+		writel(value, &priv->mipi->mipi_cal_config_csid);
+
+		value = MIPI_CAL_SEL(0x1) |
+			MIPI_CAL_HSCLKPDOSDSI(0x1) |
+			MIPI_CAL_HSCLKPUOSDSI(0x2);
+		writel(value, &priv->mipi->mipi_cal_cilc_config_2);
+		writel(value, &priv->mipi->mipi_cal_cild_config_2);
+
+		/* Deselect PAD A */
+		value = readl(&priv->mipi->mipi_cal_dsia_config_2);
+		value &= ~(MIPI_CAL_SEL(0x1));
+		writel(value, &priv->mipi->mipi_cal_dsia_config_2);
+
+		/* Deselect PAD B */
+		value = readl(&priv->mipi->mipi_cal_dsib_config_2);
+		value &= ~(MIPI_CAL_SEL(0x1));
+		writel(value, &priv->mipi->mipi_cal_dsib_config_2);
+	}
+}
+
+static int tegra_mipi_calibrate(struct udevice *dev, int offset, const void *buf,
+				int size)
+{
+	struct tegra_mipi_priv *priv = dev_get_priv(dev);
+	u32 value;
+
+	value = MIPI_CAL_BIAS_PAD_DRV_DN_REF(0x2) |
+		MIPI_CAL_BIAS_PAD_DRV_UP_REF(0x0);
+	writel(value, &priv->mipi->mipi_cal_bias_pad_cfg1);
+
+	value = readl(&priv->mipi->mipi_cal_bias_pad_cfg2);
+	value &= ~MIPI_CAL_BIAS_PAD_VCLAMP(0x7);
+	value &= ~MIPI_CAL_BIAS_PAD_VAUXP(0x7);
+	writel(value, &priv->mipi->mipi_cal_bias_pad_cfg2);
+
+	switch (priv->version) {
+	case T114:
+		tegra114_mipi_pads_cal(priv, offset);
+		break;
+
+	case T124:
+		tegra124_mipi_pads_cal(priv, offset);
+		break;
+
+	default:
+		return -EINVAL;
+	}
 
 	value = readl(&priv->mipi->mipi_cal_ctrl);
 	value &= ~MIPI_CAL_CTRL_NOISE_FILTER(0xf);
@@ -134,6 +232,11 @@ static int tegra_mipi_enable(struct udevice *dev, bool val)
 	struct tegra_mipi_priv *priv = dev_get_priv(dev);
 	u32 value;
 
+	reset_set_enable(priv->mipi_cal->id, 1);
+	mdelay(100);
+	reset_set_enable(priv->mipi_cal->id, 0);
+	mdelay(1);
+
 	clk_enable(priv->mipi_cal);
 
 	value = readl(&priv->mipi->mipi_cal_bias_pad_cfg0);
@@ -157,6 +260,8 @@ static int tegra_mipi_probe(struct udevice *dev)
 {
 	struct tegra_mipi_priv *priv = dev_get_priv(dev);
 
+	priv->version = dev_get_driver_data(dev);
+
 	priv->mipi = (struct mipi_ctlr *)dev_read_addr_ptr(dev);
 	if (!priv->mipi) {
 		log_debug("%s: no MIPI controller address\n", __func__);
@@ -174,7 +279,8 @@ static int tegra_mipi_probe(struct udevice *dev)
 }
 
 static const struct udevice_id tegra_mipi_ids[] = {
-	{ .compatible = "nvidia,tegra114-mipi" },
+	{ .compatible = "nvidia,tegra114-mipi", .data = T114 },
+	{ .compatible = "nvidia,tegra124-mipi", .data = T124 },
 	{ }
 };
 
diff --git a/drivers/video/tegra20/tegra-pwm-backlight.c b/drivers/video/tegra20/tegra-pwm-backlight.c
index 79d8a021a3a..998f0df1991 100644
--- a/drivers/video/tegra20/tegra-pwm-backlight.c
+++ b/drivers/video/tegra20/tegra-pwm-backlight.c
@@ -17,9 +17,6 @@
 
 #include "tegra-dc.h"
 
-#define TEGRA_DISPLAY_A_BASE		0x54200000
-#define TEGRA_DISPLAY_B_BASE		0x54240000
-
 #define TEGRA_PWM_BL_MIN_BRIGHTNESS	0x10
 #define TEGRA_PWM_BL_MAX_BRIGHTNESS	0xFF
 
@@ -106,14 +103,11 @@ static int tegra_pwm_backlight_enable(struct udevice *dev)
 static int tegra_pwm_backlight_probe(struct udevice *dev)
 {
 	struct tegra_pwm_backlight_priv *priv = dev_get_priv(dev);
+	ofnode dc = ofnode_get_parent(dev_ofnode(dev));
 
-	if (dev_read_bool(dev, "nvidia,display-b-base"))
-		priv->dc = (struct dc_ctlr *)TEGRA_DISPLAY_B_BASE;
-	else
-		priv->dc = (struct dc_ctlr *)TEGRA_DISPLAY_A_BASE;
-
+	priv->dc = (struct dc_ctlr *)ofnode_get_addr(dc);
 	if (!priv->dc) {
-		log_err("no display controller address\n");
+		log_err("%s: failed to get DC controller\n", __func__);
 		return -EINVAL;
 	}
 
diff --git a/drivers/video/ti/tilcdc.c b/drivers/video/ti/tilcdc.c
index 493e2f18cd2..340c79299ba 100644
--- a/drivers/video/ti/tilcdc.c
+++ b/drivers/video/ti/tilcdc.c
@@ -234,7 +234,7 @@ static int tilcdc_probe(struct udevice *dev)
 		return -EINVAL;
 	}
 
-	err = uclass_get_device_by_name(UCLASS_CLK, "lcd_gclk@534", &clk_dev);
+	err = uclass_get_device_by_name(UCLASS_CLK, "clock-lcd-gclk@534", &clk_dev);
 	if (err) {
 		dev_err(dev, "failed to get lcd_gclk device\n");
 		return err;
@@ -252,7 +252,7 @@ static int tilcdc_probe(struct udevice *dev)
 		return rate;
 	}
 
-	err = uclass_get_device_by_name(UCLASS_CLK, "dpll_disp_m2_ck@4a4",
+	err = uclass_get_device_by_name(UCLASS_CLK, "clock-dpll-disp-m2@4a4",
 					&clk_dev);
 	if (err) {
 		dev_err(dev, "failed to get dpll_disp_m2 clock device\n");
diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig
index b39b2546e5c..1bb67f50352 100644
--- a/drivers/watchdog/Kconfig
+++ b/drivers/watchdog/Kconfig
@@ -95,6 +95,15 @@ config WDT_APPLE
 	  The watchdog will perform a full SoC reset resulting in a
 	  reboot of the entire system.
 
+config WDT_ADI
+	bool "Analog Devices watchdog timer support"
+	select WDT
+	select SPL_WDT if SPL
+	depends on ARCH_SC5XX
+	help
+	  Enable this to support Watchdog Timer on ADI SC57X, SC58X, SC59X,
+	  and SC59X_64 processors
+
 config WDT_ARMADA_37XX
 	bool "Marvell Armada 37xx watchdog timer support"
 	depends on WDT && ARMADA_3700
diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile
index 9b6b1a8e8ad..e6bd4c587af 100644
--- a/drivers/watchdog/Makefile
+++ b/drivers/watchdog/Makefile
@@ -53,3 +53,4 @@ obj-$(CONFIG_WDT_STM32MP) += stm32mp_wdt.o
 obj-$(CONFIG_WDT_SUNXI) += sunxi_wdt.o
 obj-$(CONFIG_WDT_TANGIER) += tangier_wdt.o
 obj-$(CONFIG_WDT_XILINX) += xilinx_wwdt.o
+obj-$(CONFIG_WDT_ADI) += adi_wdt.o
diff --git a/drivers/watchdog/adi_wdt.c b/drivers/watchdog/adi_wdt.c
new file mode 100644
index 00000000000..6f5b3d5d042
--- /dev/null
+++ b/drivers/watchdog/adi_wdt.c
@@ -0,0 +1,143 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * (C) Copyright 2022 - Analog Devices, Inc.
+ *
+ * Written and/or maintained by Timesys Corporation
+ *
+ * Converted to driver model by Nathan Barrett-Morrison
+ *
+ * Contact: Nathan Barrett-Morrison <nathan.morrison@timesys.com>
+ * Contact: Greg Malysa <greg.malysa@timesys.com>
+ *
+ * adi_wtd.c - driver for ADI on-chip watchdog
+ *
+ */
+
+#include <clk.h>
+#include <dm.h>
+#include <wdt.h>
+#include <linux/delay.h>
+#include <linux/ioport.h>
+#include <linux/io.h>
+
+#define WDOG_CTL  0x0
+#define WDOG_CNT  0x4
+#define WDOG_STAT 0x8
+
+#define RCU_CTL   0x0
+#define RCU_STAT  0x4
+
+#define SEC_GCTL  0x0
+#define SEC_FCTL  0x10
+#define SEC_SCTL0 0x800
+
+#define WDEN      0x0010
+#define WDDIS     0x0AD0
+
+struct adi_wdt_priv {
+	void __iomem *rcu_base;
+	void __iomem *sec_base;
+	void __iomem *wdt_base;
+	struct clk clock;
+};
+
+static int adi_wdt_reset(struct udevice *dev)
+{
+	struct adi_wdt_priv *priv = dev_get_priv(dev);
+
+	iowrite32(0, priv->wdt_base + WDOG_STAT);
+
+	return 0;
+}
+
+static int adi_wdt_start(struct udevice *dev, u64 timeout_ms, ulong flags)
+{
+	struct adi_wdt_priv *priv = dev_get_priv(dev);
+
+	/* Disable SYSCD_RESETb input and clear the RCU0 reset status */
+	iowrite32(0xf, priv->rcu_base + RCU_STAT);
+	iowrite32(0x0, priv->rcu_base + RCU_CTL);
+
+	/* reset the SEC controller */
+	iowrite32(0x2, priv->sec_base + SEC_GCTL);
+	iowrite32(0x2, priv->sec_base + SEC_FCTL);
+
+	udelay(50);
+
+	/* enable SEC fault event */
+	iowrite32(0x1, priv->sec_base + SEC_GCTL);
+
+	/* ANOMALY 36100004 Spurious External Fault event occurs when FCTL
+	 * is re-programmed when currently active fault is not cleared
+	 */
+	iowrite32(0xc0, priv->sec_base + SEC_FCTL);
+	iowrite32(0xc1, priv->sec_base + SEC_FCTL);
+
+	/* enable SEC fault source for watchdog0 */
+	setbits_32(priv->sec_base + SEC_SCTL0 + (3*8), 0x6);
+
+	/* Enable SYSCD_RESETb input */
+	iowrite32(0x100, priv->rcu_base + RCU_CTL);
+
+	/* enable watchdog0 */
+	iowrite32(WDDIS, priv->wdt_base + WDOG_CTL);
+
+	iowrite32(timeout_ms / 1000 *
+	       (clk_get_rate(&priv->clock) / (IS_ENABLED(CONFIG_SC58X) ? 2 : 1)),
+	       priv->wdt_base + WDOG_CNT);
+
+	iowrite32(0, priv->wdt_base + WDOG_STAT);
+	iowrite32(WDEN, priv->wdt_base + WDOG_CTL);
+
+	return 0;
+}
+
+static int adi_wdt_probe(struct udevice *dev)
+{
+	struct adi_wdt_priv *priv = dev_get_priv(dev);
+	int ret;
+	struct resource res;
+
+	ret = dev_read_resource_byname(dev, "rcu", &res);
+	if (ret)
+		return ret;
+	priv->rcu_base = devm_ioremap(dev, res.start, resource_size(&res));
+
+	ret = dev_read_resource_byname(dev, "sec", &res);
+	if (ret)
+		return ret;
+	priv->sec_base = devm_ioremap(dev, res.start, resource_size(&res));
+
+	ret = dev_read_resource_byname(dev, "wdt", &res);
+	if (ret)
+		return ret;
+	priv->wdt_base = devm_ioremap(dev, res.start, resource_size(&res));
+
+	ret = clk_get_by_name(dev, "sclk0", &priv->clock);
+	if (ret < 0) {
+		printf("Can't get WDT clk: %d\n", ret);
+		return ret;
+	}
+
+	return 0;
+}
+
+static const struct wdt_ops adi_wdt_ops = {
+	.start		= adi_wdt_start,
+	.reset		= adi_wdt_reset,
+};
+
+static const struct udevice_id adi_wdt_ids[] = {
+	{ .compatible = "adi,wdt" },
+	{}
+};
+
+U_BOOT_DRIVER(adi_wdt) = {
+	.name		= "adi_wdt",
+	.id		= UCLASS_WDT,
+	.of_match	= adi_wdt_ids,
+	.probe		= adi_wdt_probe,
+	.ops		= &adi_wdt_ops,
+	.priv_auto = sizeof(struct adi_wdt_priv),
+	.flags		= DM_FLAG_PRE_RELOC,
+};
diff --git a/drivers/watchdog/da9063-wdt.c b/drivers/watchdog/da9063-wdt.c
index b7216b57863..ec9bc033011 100644
--- a/drivers/watchdog/da9063-wdt.c
+++ b/drivers/watchdog/da9063-wdt.c
@@ -145,5 +145,4 @@ U_BOOT_DRIVER(da9063_wdt) = {
 	.id = UCLASS_WDT,
 	.of_match = da9063_wdt_ids,
 	.ops = &da9063_wdt_ops,
-	.flags = DM_FLAG_PROBE_AFTER_BIND,
 };
diff --git a/dts/upstream/Bindings/arm/altera/socfpga-system.txt b/dts/upstream/Bindings/arm/altera/socfpga-system.txt
deleted file mode 100644
index 82edbaaa3f8..00000000000
--- a/dts/upstream/Bindings/arm/altera/socfpga-system.txt
+++ /dev/null
@@ -1,25 +0,0 @@
-Altera SOCFPGA System Manager
-
-Required properties:
-- compatible : "altr,sys-mgr"
-- reg : Should contain 1 register ranges(address and length)
-- cpu1-start-addr : CPU1 start address in hex.
-
-Example:
-	 sysmgr@ffd08000 {
-		compatible = "altr,sys-mgr";
-		reg = <0xffd08000 0x1000>;
-		cpu1-start-addr = <0xffd080c4>;
-	};
-
-ARM64 - Stratix10
-Required properties:
-- compatible : "altr,sys-mgr-s10"
-- reg : Should contain 1 register range(address and length)
-        for system manager register.
-
-Example:
-	 sysmgr@ffd12000 {
-		compatible = "altr,sys-mgr-s10";
-		reg = <0xffd12000 0x228>;
-	};
diff --git a/dts/upstream/Bindings/arm/arm,coresight-dummy-source.yaml b/dts/upstream/Bindings/arm/arm,coresight-dummy-source.yaml
index 04a8c37b4af..742dc4e25d3 100644
--- a/dts/upstream/Bindings/arm/arm,coresight-dummy-source.yaml
+++ b/dts/upstream/Bindings/arm/arm,coresight-dummy-source.yaml
@@ -38,6 +38,12 @@ properties:
     enum:
       - arm,coresight-dummy-source
 
+  arm,static-trace-id:
+    description: If dummy source needs static id support, use this to set trace id.
+    $ref: /schemas/types.yaml#/definitions/uint32
+    minimum: 1
+    maximum: 111
+
   out-ports:
     $ref: /schemas/graph.yaml#/properties/ports
 
diff --git a/dts/upstream/Bindings/arm/arm,coresight-static-replicator.yaml b/dts/upstream/Bindings/arm/arm,coresight-static-replicator.yaml
index 1892a091ac3..a6f793ea03b 100644
--- a/dts/upstream/Bindings/arm/arm,coresight-static-replicator.yaml
+++ b/dts/upstream/Bindings/arm/arm,coresight-static-replicator.yaml
@@ -45,7 +45,22 @@ properties:
     patternProperties:
       '^port@[01]$':
         description: Output connections to CoreSight Trace bus
-        $ref: /schemas/graph.yaml#/properties/port
+        $ref: /schemas/graph.yaml#/$defs/port-base
+        unevaluatedProperties: false
+
+        properties:
+          endpoint:
+            $ref: /schemas/graph.yaml#/$defs/endpoint-base
+            unevaluatedProperties: false
+
+            properties:
+              filter-source:
+                $ref: /schemas/types.yaml#/definitions/phandle
+                description:
+                  phandle to the coresight trace source device matching the
+                  hard coded filtering for this port
+
+              remote-endpoint: true
 
 required:
   - compatible
@@ -72,6 +87,7 @@ examples:
                 reg = <0>;
                 replicator_out_port0: endpoint {
                     remote-endpoint = <&etb_in_port>;
+                    filter-source = <&tpdm_video>;
                 };
             };
 
@@ -79,6 +95,7 @@ examples:
                 reg = <1>;
                 replicator_out_port1: endpoint {
                     remote-endpoint = <&tpiu_in_port>;
+                    filter-source = <&tpdm_mdss>;
                 };
             };
         };
diff --git a/dts/upstream/Bindings/arm/arm,embedded-trace-extension.yaml b/dts/upstream/Bindings/arm/arm,embedded-trace-extension.yaml
index f725e694099..9c2c9ac9705 100644
--- a/dts/upstream/Bindings/arm/arm,embedded-trace-extension.yaml
+++ b/dts/upstream/Bindings/arm/arm,embedded-trace-extension.yaml
@@ -23,7 +23,7 @@ description: |
 
 properties:
   $nodename:
-    pattern: "^ete([0-9a-f]+)$"
+    pattern: "^ete(-[0-9]+)?$"
   compatible:
     items:
       - const: arm,embedded-trace-extension
@@ -55,13 +55,13 @@ examples:
 
 # An ETE node without legacy CoreSight connections
   - |
-    ete0 {
+    ete-0 {
       compatible = "arm,embedded-trace-extension";
       cpu = <&cpu_0>;
     };
 # An ETE node with legacy CoreSight connections
   - |
-   ete1 {
+   ete-1 {
       compatible = "arm,embedded-trace-extension";
       cpu = <&cpu_1>;
 
diff --git a/dts/upstream/Bindings/arm/aspeed/aspeed.yaml b/dts/upstream/Bindings/arm/aspeed/aspeed.yaml
index 2f92b8ab08f..01333ac111f 100644
--- a/dts/upstream/Bindings/arm/aspeed/aspeed.yaml
+++ b/dts/upstream/Bindings/arm/aspeed/aspeed.yaml
@@ -74,6 +74,7 @@ properties:
       - description: AST2600 based boards
         items:
           - enum:
+              - ampere,mtjefferson-bmc
               - ampere,mtmitchell-bmc
               - aspeed,ast2600-evb
               - aspeed,ast2600-evb-a1
@@ -91,6 +92,7 @@ properties:
               - ibm,everest-bmc
               - ibm,fuji-bmc
               - ibm,rainier-bmc
+              - ibm,sbp1-bmc
               - ibm,system1-bmc
               - ibm,tacoma-bmc
               - inventec,starscream-bmc
diff --git a/dts/upstream/Bindings/arm/atmel-at91.yaml b/dts/upstream/Bindings/arm/atmel-at91.yaml
index 7160ec80ac1..0ec29366e6c 100644
--- a/dts/upstream/Bindings/arm/atmel-at91.yaml
+++ b/dts/upstream/Bindings/arm/atmel-at91.yaml
@@ -180,6 +180,13 @@ properties:
           - const: atmel,sama5d4
           - const: atmel,sama5
 
+      - description: Microchip SAMA7D65 Curiosity Board
+        items:
+          - const: microchip,sama7d65-curiosity
+          - const: microchip,sama7d65
+          - const: microchip,sama7d6
+          - const: microchip,sama7
+
       - items:
           - const: microchip,sama7g5ek # SAMA7G5 Evaluation Kit
           - const: microchip,sama7g5
diff --git a/dts/upstream/Bindings/arm/atmel-sysregs.txt b/dts/upstream/Bindings/arm/atmel-sysregs.txt
index 76e2b797825..1a173e92bb1 100644
--- a/dts/upstream/Bindings/arm/atmel-sysregs.txt
+++ b/dts/upstream/Bindings/arm/atmel-sysregs.txt
@@ -13,6 +13,7 @@ PIT Timer required properties:
 PIT64B Timer required properties:
 - compatible: Should be "microchip,sam9x60-pit64b" or
 			"microchip,sam9x7-pit64b", "microchip,sam9x60-pit64b"
+			"microchip,sama7d65-pit64b", "microchip,sam9x60-pit64b"
 - reg: Should contain registers location and length
 - interrupts: Should contain interrupt for PIT64B timer
 - clocks: Should contain the available clock sources for PIT64B timer.
@@ -27,12 +28,13 @@ Its subnodes can be:
 - watchdog: compatible should be "atmel,at91rm9200-wdt"
 
 RAMC SDRAM/DDR Controller required properties:
-- compatible: Should be "atmel,at91rm9200-sdramc", "syscon"
-			"atmel,at91sam9260-sdramc",
-			"atmel,at91sam9g45-ddramc",
-			"atmel,sama5d3-ddramc",
-			"microchip,sam9x60-ddramc",
-			"microchip,sama7g5-uddrc",
+- compatible: Should be "atmel,at91rm9200-sdramc", "syscon" or
+			"atmel,at91sam9260-sdramc" or
+			"atmel,at91sam9g45-ddramc" or
+			"atmel,sama5d3-ddramc" or
+			"microchip,sam9x60-ddramc" or
+			"microchip,sama7g5-uddrc" or
+			"microchip,sama7d65-uddrc", "microchip,sama7g5-uddrc" or
 			"microchip,sam9x7-ddramc", "atmel,sama5d3-ddramc".
 - reg: Should contain registers location and length
 
diff --git a/dts/upstream/Bindings/arm/bcm/brcm,bcmbca.yaml b/dts/upstream/Bindings/arm/bcm/brcm,bcmbca.yaml
index 07892cbdd23..354bb1420cd 100644
--- a/dts/upstream/Bindings/arm/bcm/brcm,bcmbca.yaml
+++ b/dts/upstream/Bindings/arm/bcm/brcm,bcmbca.yaml
@@ -34,6 +34,7 @@ properties:
           - enum:
               - netgear,r8000p
               - tplink,archer-c2300-v1
+              - zyxel,ex3510b
           - const: brcm,bcm4906
           - const: brcm,bcm4908
           - const: brcm,bcmbca
@@ -115,6 +116,7 @@ properties:
         items:
           - enum:
               - brcm,bcm96846
+              - genexis,xg6846b
           - const: brcm,bcm6846
           - const: brcm,bcmbca
 
diff --git a/dts/upstream/Bindings/arm/blaize.yaml b/dts/upstream/Bindings/arm/blaize.yaml
new file mode 100644
index 00000000000..af39e275640
--- /dev/null
+++ b/dts/upstream/Bindings/arm/blaize.yaml
@@ -0,0 +1,40 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/blaize.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Blaize Platforms
+
+maintainers:
+  - James Cowgill <james.cowgill@blaize.com>
+  - Matt Redfearn <matt.redfearn@blaize.com>
+  - Neil Jones <neil.jones@blaize.com>
+  - Nikolaos Pasaloukos <nikolaos.pasaloukos@blaize.com>
+
+description: |
+  Blaize Platforms using SoCs designed by Blaize Inc.
+
+  The products based on the BLZP1600 SoC:
+
+  - BLZP1600-SoM: SoM (System on Module)
+  - BLZP1600-CB2: Development board CB2 based on BLZP1600-SoM
+
+  BLZP1600 SoC integrates a dual core ARM Cortex A53 cluster
+  and a Blaize Graph Streaming Processor for AI and ML workloads,
+  plus a suite of connectivity and other peripherals.
+
+properties:
+  $nodename:
+    const: '/'
+  compatible:
+    oneOf:
+      - description: Blaize BLZP1600 based boards
+        items:
+          - enum:
+              - blaize,blzp1600-cb2
+          - const: blaize,blzp1600
+
+additionalProperties: true
+
+...
diff --git a/dts/upstream/Bindings/arm/fsl.yaml b/dts/upstream/Bindings/arm/fsl.yaml
index 6e0dcf4307f..0db2cbd7891 100644
--- a/dts/upstream/Bindings/arm/fsl.yaml
+++ b/dts/upstream/Bindings/arm/fsl.yaml
@@ -1091,6 +1091,7 @@ properties:
               - dmo,imx8mp-data-modul-edm-sbc # i.MX8MP eDM SBC
               - emcraft,imx8mp-navqp      # i.MX8MP Emcraft Systems NavQ+ Kit
               - fsl,imx8mp-evk            # i.MX8MP EVK Board
+              - fsl,imx8mp-evk-revb4      # i.MX8MP EVK Rev B4 Board
               - gateworks,imx8mp-gw71xx-2x # i.MX8MP Gateworks Board
               - gateworks,imx8mp-gw72xx-2x # i.MX8MP Gateworks Board
               - gateworks,imx8mp-gw73xx-2x # i.MX8MP Gateworks Board
@@ -1106,6 +1107,15 @@ properties:
               - ysoft,imx8mp-iota2-lumpy  # Y Soft i.MX8MP IOTA2 Lumpy Board
           - const: fsl,imx8mp
 
+      - description: ABB Boards with i.MX8M Plus Modules from ADLink
+        items:
+          - enum:
+              - abb,imx8mp-aristanetos3-adpismarc # i.MX8MP ABB SoM on PI SMARC Board
+              - abb,imx8mp-aristanetos3-helios    # i.MX8MP ABB SoM on helios Board
+              - abb,imx8mp-aristanetos3-proton2s  # i.MX8MP ABB SoM on proton2s Board
+          - const: abb,imx8mp-aristanetos3-som    # i.MX8MP ABB SoM
+          - const: fsl,imx8mp
+
       - description: Avnet (MSC Branded) Boards with SM2S i.MX8M Plus Modules
         items:
           - const: avnet,sm2s-imx8mp-14N0600E-ep1 # SM2S-IMX8PLUS-14N0600E on SM2-MB-EP1 Carrier Board
@@ -1262,6 +1272,7 @@ properties:
         items:
           - enum:
               - fsl,imx8qm-mek           # i.MX8QM MEK Board
+              - fsl,imx8qm-mek-revd      # i.MX8QM MEK Rev D Board
               - toradex,apalis-imx8      # Apalis iMX8 Modules
               - toradex,apalis-imx8-v1.1 # Apalis iMX8 V1.1 Modules
           - const: fsl,imx8qm
@@ -1290,6 +1301,7 @@ properties:
           - enum:
               - einfochips,imx8qxp-ai_ml  # i.MX8QXP AI_ML Board
               - fsl,imx8qxp-mek           # i.MX8QXP MEK Board
+              - fsl,imx8qxp-mek-wcpu      # i.MX8QXP MEK WCPU Board
           - const: fsl,imx8qxp
 
       - description: i.MX8DXL based Boards
diff --git a/dts/upstream/Bindings/arm/mediatek.yaml b/dts/upstream/Bindings/arm/mediatek.yaml
index 1d4bb50fcd8..3ce34d68c21 100644
--- a/dts/upstream/Bindings/arm/mediatek.yaml
+++ b/dts/upstream/Bindings/arm/mediatek.yaml
@@ -239,6 +239,34 @@ properties:
           - enum:
               - mediatek,mt8183-pumpkin
           - const: mediatek,mt8183
+      - description: Google Chinchou (Asus Chromebook CZ1104CM2A/CZ1204CM2A)
+        items:
+          - const: google,chinchou-sku0
+          - const: google,chinchou-sku2
+          - const: google,chinchou-sku4
+          - const: google,chinchou-sku5
+          - const: google,chinchou
+          - const: mediatek,mt8186
+      - description: Google Chinchou (Asus Chromebook CZ1104FM2A/CZ1204FM2A/CZ1104CM2A/CZ1204CM2A)
+        items:
+          - const: google,chinchou-sku1
+          - const: google,chinchou-sku3
+          - const: google,chinchou-sku6
+          - const: google,chinchou-sku7
+          - const: google,chinchou-sku17
+          - const: google,chinchou-sku20
+          - const: google,chinchou-sku22
+          - const: google,chinchou-sku23
+          - const: google,chinchou
+          - const: mediatek,mt8186
+      - description: Google Chinchou360 (Asus Chromebook CZ1104FM2A/CZ1204FM2A Flip)
+        items:
+          - const: google,chinchou-sku16
+          - const: google,chinchou-sku18
+          - const: google,chinchou-sku19
+          - const: google,chinchou-sku21
+          - const: google,chinchou
+          - const: mediatek,mt8186
       - description: Google Magneton (Lenovo IdeaPad Slim 3 Chromebook (14M868))
         items:
           - const: google,steelix-sku393219
@@ -263,6 +291,19 @@ properties:
           - const: google,steelix-sku196608
           - const: google,steelix
           - const: mediatek,mt8186
+      - description: Google Starmie (ASUS Chromebook Enterprise CM30 (CM3001))
+        items:
+          - const: google,starmie-sku0
+          - const: google,starmie-sku2
+          - const: google,starmie-sku3
+          - const: google,starmie
+          - const: mediatek,mt8186
+      - description: Google Starmie (ASUS Chromebook Enterprise CM30 (CM3001))
+        items:
+          - const: google,starmie-sku1
+          - const: google,starmie-sku4
+          - const: google,starmie
+          - const: mediatek,mt8186
       - description: Google Steelix (Lenovo 300e Yoga Chromebook Gen 4)
         items:
           - enum:
@@ -307,6 +348,19 @@ properties:
           - enum:
               - mediatek,mt8186-evb
           - const: mediatek,mt8186
+      - description: Google Ciri (Lenovo Chromebook Duet (11", 9))
+        items:
+          - enum:
+              - google,ciri-sku0
+              - google,ciri-sku1
+              - google,ciri-sku2
+              - google,ciri-sku3
+              - google,ciri-sku4
+              - google,ciri-sku5
+              - google,ciri-sku6
+              - google,ciri-sku7
+          - const: google,ciri
+          - const: mediatek,mt8188
       - items:
           - enum:
               - mediatek,mt8188-evb
@@ -316,12 +370,6 @@ properties:
           - const: google,hayato-rev1
           - const: google,hayato
           - const: mediatek,mt8192
-      - description: Google Hayato rev5
-        items:
-          - const: google,hayato-rev5-sku2
-          - const: google,hayato-sku2
-          - const: google,hayato
-          - const: mediatek,mt8192
       - description: Google Spherion (Acer Chromebook 514)
         items:
           - const: google,spherion-rev3
@@ -330,11 +378,6 @@ properties:
           - const: google,spherion-rev0
           - const: google,spherion
           - const: mediatek,mt8192
-      - description: Google Spherion rev4 (Acer Chromebook 514)
-        items:
-          - const: google,spherion-rev4
-          - const: google,spherion
-          - const: mediatek,mt8192
       - items:
           - enum:
               - mediatek,mt8192-evb
diff --git a/dts/upstream/Bindings/arm/qcom-soc.yaml b/dts/upstream/Bindings/arm/qcom-soc.yaml
index d0751a572af..a77d68dcad4 100644
--- a/dts/upstream/Bindings/arm/qcom-soc.yaml
+++ b/dts/upstream/Bindings/arm/qcom-soc.yaml
@@ -23,7 +23,7 @@ description: |
 select:
   properties:
     compatible:
-      pattern: "^qcom,.*(apq|ipq|mdm|msm|qcm|qcs|q[dr]u|sa|sc|sd[amx]|sm|x1e)[0-9]+.*$"
+      pattern: "^qcom,.*(apq|ipq|mdm|msm|qcm|qcs|q[dr]u|sa|sar|sc|sd[amx]|sm|x1[ep])[0-9]+.*$"
   required:
     - compatible
 
@@ -31,7 +31,8 @@ properties:
   compatible:
     oneOf:
       # Preferred naming style for compatibles of SoC components:
-      - pattern: "^qcom,(apq|ipq|mdm|msm|qcm|qcs|q[dr]u|sa|sc|sd[amx]|sm|x1e)[0-9]+(pro)?-.*$"
+      - pattern: "^qcom,(apq|ipq|mdm|msm|qcm|qcs|q[dr]u|sa|sc|sd[amx]|sm|x1[ep])[0-9]+(pro)?-.*$"
+      - pattern: "^qcom,sar[0-9]+[a-z]?-.*$"
       - pattern: "^qcom,(sa|sc)8[0-9]+[a-z][a-z]?-.*$"
 
       # Legacy namings - variations of existing patterns/compatibles are OK,
@@ -39,9 +40,9 @@ properties:
       - pattern: "^qcom,[ak]pss-wdt-(apq|ipq|mdm|msm|qcm|qcs|q[dr]u|sa|sc|sd[amx]|sm)[0-9]+.*$"
       - pattern: "^qcom,gcc-(apq|ipq|mdm|msm|qcm|qcs|q[dr]u|sa|sc|sd[amx]|sm)[0-9]+.*$"
       - pattern: "^qcom,mmcc-(apq|ipq|mdm|msm|qcm|qcs|q[dr]u|sa|sc|sd[amx]|sm)[0-9]+.*$"
-      - pattern: "^qcom,pcie-(apq|ipq|mdm|msm|qcm|qcs|q[dr]u|sa|sc|sd[amx]|sm|x1e)[0-9]+.*$"
+      - pattern: "^qcom,pcie-(apq|ipq|mdm|msm|qcm|qcs|q[dr]u|sa|sc|sd[amx]|sm|x1[ep])[0-9]+.*$"
       - pattern: "^qcom,rpm-(apq|ipq|mdm|msm|qcm|qcs|q[dr]u|sa|sc|sd[amx]|sm)[0-9]+.*$"
-      - pattern: "^qcom,scm-(apq|ipq|mdm|msm|qcm|qcs|q[dr]u|sa|sc|sd[amx]|sm|x1e)[0-9]+.*$"
+      - pattern: "^qcom,scm-(apq|ipq|mdm|msm|qcm|qcs|q[dr]u|sa|sc|sd[amx]|sm|x1[ep])[0-9]+.*$"
       - enum:
           - qcom,dsi-ctrl-6g-qcm2290
           - qcom,gpucc-sdm630
diff --git a/dts/upstream/Bindings/arm/qcom.yaml b/dts/upstream/Bindings/arm/qcom.yaml
index 9679fed7259..618a87693ac 100644
--- a/dts/upstream/Bindings/arm/qcom.yaml
+++ b/dts/upstream/Bindings/arm/qcom.yaml
@@ -19,29 +19,42 @@ description: |
 
         apq8016
         apq8026
+        apq8064
         apq8074
         apq8084
+        apq8094
         apq8096
         ipq4018
+        ipq4019
         ipq5018
         ipq5332
+        ipq5424
         ipq6018
+        ipq8064
         ipq8074
         ipq9574
         mdm9615
         msm8226
+        msm8660
         msm8916
+        msm8917
+        msm8926
+        msm8929
         msm8939
         msm8953
         msm8956
         msm8960
         msm8974
+        msm8974pro
         msm8976
         msm8992
         msm8994
         msm8996
+        msm8996pro
         msm8998
         qcs404
+        qcs615
+        qcs8300
         qcs8550
         qcm2290
         qcm6490
@@ -53,6 +66,7 @@ description: |
         sa8155p
         sa8540p
         sa8775p
+        sar2130p
         sc7180
         sc7280
         sc8180x
@@ -84,7 +98,10 @@ description: |
         sm8450
         sm8550
         sm8650
+        sm8750
+        x1e78100
         x1e80100
+        x1p42100
 
   There are many devices in the list below that run the standard ChromeOS
   bootloader setup and use the open source depthcharge bootloader to boot the
@@ -252,6 +269,11 @@ properties:
 
       - items:
           - enum:
+              - xiaomi,riva
+          - const: qcom,msm8917
+
+      - items:
+          - enum:
               - motorola,potter
               - xiaomi,daisy
               - xiaomi,mido
@@ -354,6 +376,11 @@ properties:
 
       - items:
           - enum:
+              - qcom,ipq5424-rdp466
+          - const: qcom,ipq5424
+
+      - items:
+          - enum:
               - mikrotik,rb3011
               - qcom,ipq8064-ap148
           - const: qcom,ipq8064
@@ -408,6 +435,12 @@ properties:
               - qcom,qru1000-idp
           - const: qcom,qru1000
 
+      - description: Qualcomm AR2 Gen1 platform
+        items:
+          - enum:
+              - qcom,qar2130p
+          - const: qcom,sar2130p
+
       - items:
           - enum:
               - acer,aspire1
@@ -822,8 +855,10 @@ properties:
 
       - items:
           - enum:
+              - huawei,gaokun3
               - lenovo,thinkpad-x13s
               - microsoft,arcata
+              - microsoft,blackrock
               - qcom,sc8280xp-crd
               - qcom,sc8280xp-qrd
           - const: qcom,sc8280xp
@@ -900,6 +935,16 @@ properties:
 
       - items:
           - enum:
+              - qcom,qcs8300-ride
+          - const: qcom,qcs8300
+
+      - items:
+          - enum:
+              - qcom,qcs615-ride
+          - const: qcom,qcs615
+
+      - items:
+          - enum:
               - qcom,sa8155p-adp
           - const: qcom,sa8155p
 
@@ -1066,6 +1111,18 @@ properties:
 
       - items:
           - enum:
+              - qcom,sm8750-mtp
+              - qcom,sm8750-qrd
+          - const: qcom,sm8750
+
+      - items:
+          - enum:
+              - qcom,x1e001de-devkit
+          - const: qcom,x1e001de
+          - const: qcom,x1e80100
+
+      - items:
+          - enum:
               - lenovo,thinkpad-t14s
           - const: qcom,x1e78100
           - const: qcom,x1e80100
@@ -1074,6 +1131,7 @@ properties:
           - enum:
               - asus,vivobook-s15
               - dell,xps13-9345
+              - hp,omnibook-x14
               - lenovo,yoga-slim7x
               - microsoft,romulus13
               - microsoft,romulus15
@@ -1081,6 +1139,11 @@ properties:
               - qcom,x1e80100-qcp
           - const: qcom,x1e80100
 
+      - items:
+          - enum:
+              - qcom,x1p42100-crd
+          - const: qcom,x1p42100
+
   # Board compatibles go above
 
   qcom,msm-id:
@@ -1158,6 +1221,7 @@ allOf:
               - qcom,apq8026
               - qcom,apq8094
               - qcom,apq8096
+              - qcom,msm8917
               - qcom,msm8939
               - qcom,msm8953
               - qcom,msm8956
diff --git a/dts/upstream/Bindings/arm/rockchip.yaml b/dts/upstream/Bindings/arm/rockchip.yaml
index 753199a1292..522a6f0450e 100644
--- a/dts/upstream/Bindings/arm/rockchip.yaml
+++ b/dts/upstream/Bindings/arm/rockchip.yaml
@@ -81,6 +81,17 @@ properties:
           - const: azw,beelink-a1
           - const: rockchip,rk3328
 
+      - description: BigTreeTech CB2 Manta M4/8P
+        items:
+          - const: bigtreetech,cb2-manta
+          - const: bigtreetech,cb2
+          - const: rockchip,rk3566
+
+      - description: BigTreeTech Pi 2
+        items:
+          - const: bigtreetech,pi2
+          - const: rockchip,rk3566
+
       - description: bq Curie 2 tablet
         items:
           - const: mundoreader,bq-curie2
@@ -167,6 +178,13 @@ properties:
           - const: engicam,px30-core
           - const: rockchip,px30
 
+      - description: Firefly Core-3588J-based boards
+        items:
+          - enum:
+              - firefly,itx-3588j
+          - const: firefly,core-3588j
+          - const: rockchip,rk3588
+
       - description: Firefly Core-PX30-JD4 on MB-JD4-PX30 baseboard
         items:
           - const: firefly,px30-jd4-core-mb
@@ -597,6 +615,11 @@ properties:
           - const: google,veyron
           - const: rockchip,rk3288
 
+      - description: H96 Max V58 TV Box
+        items:
+          - const: haochuangyi,h96-max-v58
+          - const: rockchip,rk3588
+
       - description: Haoyu MarsBoard RK3066
         items:
           - const: haoyu,marsboard-rk3066
@@ -812,6 +835,12 @@ properties:
           - const: radxa,e20c
           - const: rockchip,rk3528
 
+      - description: Radxa E52C
+        items:
+          - const: radxa,e52c
+          - const: rockchip,rk3582
+          - const: rockchip,rk3588s
+
       - description: Radxa Rock
         items:
           - const: radxa,rock
@@ -1006,6 +1035,21 @@ properties:
           - const: rockchip,rk3399-sapphire-excavator
           - const: rockchip,rk3399
 
+      - description: Rockchip RK3566 BOX Evaluation Demo board
+        items:
+          - const: rockchip,rk3566-box-demo
+          - const: rockchip,rk3566
+
+      - description: Rockchip RK3568 Evaluation board
+        items:
+          - const: rockchip,rk3568-evb1-v10
+          - const: rockchip,rk3568
+
+      - description: Rockchip RK3576 Evaluation board
+        items:
+          - const: rockchip,rk3576-evb1-v10
+          - const: rockchip,rk3576
+
       - description: Rockchip RK3588 Evaluation board
         items:
           - const: rockchip,rk3588-evb1-v10
@@ -1026,6 +1070,23 @@ properties:
           - const: rockchip,rk3588-toybrick-x0
           - const: rockchip,rk3588
 
+      - description: Sinovoip RK3308 Banana Pi P2 Pro
+        items:
+          - const: sinovoip,rk3308-bpi-p2pro
+          - const: rockchip,rk3308
+
+      - description: Sinovoip RK3568 Banana Pi R2 Pro
+        items:
+          - const: sinovoip,rk3568-bpi-r2pro
+          - const: rockchip,rk3568
+
+      - description: Sonoff iHost Smart Home Hub
+        items:
+          - const: itead,sonoff-ihost
+          - enum:
+              - rockchip,rv1126
+              - rockchip,rv1109
+
       - description: Theobroma Systems PX30-uQ7 with Haikou baseboard
         items:
           - const: tsd,px30-ringneck-haikou
@@ -1075,9 +1136,11 @@ properties:
           - const: xunlong,orangepi-3b
           - const: rockchip,rk3566
 
-      - description: Xunlong Orange Pi 5 Plus
+      - description: Xunlong Orange Pi 5 Max/Plus
         items:
-          - const: xunlong,orangepi-5-plus
+          - enum:
+              - xunlong,orangepi-5-max
+              - xunlong,orangepi-5-plus
           - const: rockchip,rk3588
 
       - description: Xunlong Orange Pi R1 Plus / LTS
@@ -1099,33 +1162,6 @@ properties:
           - const: zkmagic,a95x-z2
           - const: rockchip,rk3318
 
-      - description: Rockchip RK3566 BOX Evaluation Demo board
-        items:
-          - const: rockchip,rk3566-box-demo
-          - const: rockchip,rk3566
-
-      - description: Rockchip RK3568 Evaluation board
-        items:
-          - const: rockchip,rk3568-evb1-v10
-          - const: rockchip,rk3568
-
-      - description: Sinovoip RK3308 Banana Pi P2 Pro
-        items:
-          - const: sinovoip,rk3308-bpi-p2pro
-          - const: rockchip,rk3308
-
-      - description: Sinovoip RK3568 Banana Pi R2 Pro
-        items:
-          - const: sinovoip,rk3568-bpi-r2pro
-          - const: rockchip,rk3568
-
-      - description: Sonoff iHost Smart Home Hub
-        items:
-          - const: itead,sonoff-ihost
-          - enum:
-              - rockchip,rv1126
-              - rockchip,rv1109
-
 additionalProperties: true
 
 ...
diff --git a/dts/upstream/Bindings/arm/rockchip/pmu.yaml b/dts/upstream/Bindings/arm/rockchip/pmu.yaml
index 932f981265c..52016a14122 100644
--- a/dts/upstream/Bindings/arm/rockchip/pmu.yaml
+++ b/dts/upstream/Bindings/arm/rockchip/pmu.yaml
@@ -53,11 +53,17 @@ properties:
   reg:
     maxItems: 1
 
+  power-controller:
+    type: object
+
+  reboot-mode:
+    type: object
+
 required:
   - compatible
   - reg
 
-additionalProperties: true
+additionalProperties: false
 
 examples:
   - |
diff --git a/dts/upstream/Bindings/arm/samsung/samsung-boards.yaml b/dts/upstream/Bindings/arm/samsung/samsung-boards.yaml
index b5ba5ffc36d..fab29f95d8e 100644
--- a/dts/upstream/Bindings/arm/samsung/samsung-boards.yaml
+++ b/dts/upstream/Bindings/arm/samsung/samsung-boards.yaml
@@ -240,6 +240,9 @@ properties:
         items:
           - enum:
               - samsung,c1s                     # Samsung Galaxy Note20 5G (SM-N981B)
+              - samsung,r8s                     # Samsung Galaxy S20 FE (SM-G780F)
+              - samsung,x1s                     # Samsung Galaxy S20 5G (SM-G981B)
+              - samsung,x1slte                  # Samsung Galaxy S20 (SM-G980F)
           - const: samsung,exynos990
 
       - description: Exynos Auto v9 based boards
diff --git a/dts/upstream/Bindings/arm/stm32/stm32.yaml b/dts/upstream/Bindings/arm/stm32/stm32.yaml
index 703d4b57439..b6c56d4ce6b 100644
--- a/dts/upstream/Bindings/arm/stm32/stm32.yaml
+++ b/dts/upstream/Bindings/arm/stm32/stm32.yaml
@@ -91,6 +91,13 @@ properties:
           - const: dh,stm32mp153c-dhcor-som
           - const: st,stm32mp153
 
+      - description: Octavo OSD32MP153 System-in-Package based boards
+        items:
+          - enum:
+              - lxa,stm32mp153c-tac-gen3 # Linux Automation TAC (Generation 3)
+          - const: oct,stm32mp153x-osd32
+          - const: st,stm32mp153
+
       - items:
           - enum:
               - shiratech,stm32mp157a-iot-box # IoT Box
diff --git a/dts/upstream/Bindings/cache/qcom,llcc.yaml b/dts/upstream/Bindings/cache/qcom,llcc.yaml
index 03b1941eaa3..e5effbb4a60 100644
--- a/dts/upstream/Bindings/cache/qcom,llcc.yaml
+++ b/dts/upstream/Bindings/cache/qcom,llcc.yaml
@@ -20,6 +20,7 @@ description: |
 properties:
   compatible:
     enum:
+      - qcom,ipq5424-llcc
       - qcom,qcs615-llcc
       - qcom,qcs8300-llcc
       - qcom,qdu1000-llcc
@@ -42,11 +43,11 @@ properties:
       - qcom,x1e80100-llcc
 
   reg:
-    minItems: 2
+    minItems: 1
     maxItems: 10
 
   reg-names:
-    minItems: 2
+    minItems: 1
     maxItems: 10
 
   interrupts:
@@ -71,6 +72,21 @@ allOf:
         compatible:
           contains:
             enum:
+              - qcom,ipq5424-llcc
+    then:
+      properties:
+        reg:
+          items:
+            - description: LLCC0 base register region
+        reg-names:
+          items:
+            - const: llcc0_base
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
               - qcom,sar1130p-llcc
               - qcom,sar2130p-llcc
     then:
diff --git a/dts/upstream/Bindings/chrome/google,cros-kbd-led-backlight.yaml b/dts/upstream/Bindings/chrome/google,cros-kbd-led-backlight.yaml
deleted file mode 100644
index c94ab8f9e0b..00000000000
--- a/dts/upstream/Bindings/chrome/google,cros-kbd-led-backlight.yaml
+++ /dev/null
@@ -1,36 +0,0 @@
-# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
-%YAML 1.2
----
-$id: http://devicetree.org/schemas/chrome/google,cros-kbd-led-backlight.yaml#
-$schema: http://devicetree.org/meta-schemas/core.yaml#
-
-title: ChromeOS keyboard backlight LED driver.
-
-maintainers:
-  - Tzung-Bi Shih <tzungbi@kernel.org>
-
-properties:
-  compatible:
-    const: google,cros-kbd-led-backlight
-
-required:
-  - compatible
-
-additionalProperties: false
-
-examples:
-  - |
-    spi {
-      #address-cells = <1>;
-      #size-cells = <0>;
-
-      cros_ec: ec@0 {
-        compatible = "google,cros-ec-spi";
-        reg = <0>;
-        interrupts = <15 0>;
-
-        kbd-led-backlight {
-          compatible = "google,cros-kbd-led-backlight";
-        };
-      };
-    };
diff --git a/dts/upstream/Bindings/clock/atmel,at91rm9200-pmc.yaml b/dts/upstream/Bindings/clock/atmel,at91rm9200-pmc.yaml
index c9eb60776b4..885d47dd572 100644
--- a/dts/upstream/Bindings/clock/atmel,at91rm9200-pmc.yaml
+++ b/dts/upstream/Bindings/clock/atmel,at91rm9200-pmc.yaml
@@ -43,6 +43,7 @@ properties:
               - atmel,sama5d4-pmc
               - microchip,sam9x60-pmc
               - microchip,sam9x7-pmc
+              - microchip,sama7d65-pmc
               - microchip,sama7g5-pmc
           - const: syscon
 
@@ -90,6 +91,7 @@ allOf:
             enum:
               - microchip,sam9x60-pmc
               - microchip,sam9x7-pmc
+              - microchip,sama7d65-pmc
               - microchip,sama7g5-pmc
     then:
       properties:
diff --git a/dts/upstream/Bindings/clock/atmel,at91sam9x5-sckc.yaml b/dts/upstream/Bindings/clock/atmel,at91sam9x5-sckc.yaml
index c2283cd07f0..d4cf8ae2961 100644
--- a/dts/upstream/Bindings/clock/atmel,at91sam9x5-sckc.yaml
+++ b/dts/upstream/Bindings/clock/atmel,at91sam9x5-sckc.yaml
@@ -20,6 +20,7 @@ properties:
       - items:
           - enum:
               - microchip,sam9x7-sckc
+              - microchip,sama7d65-sckc
               - microchip,sama7g5-sckc
           - const: microchip,sam9x60-sckc
 
diff --git a/dts/upstream/Bindings/clock/qcom,gpucc.yaml b/dts/upstream/Bindings/clock/qcom,gpucc.yaml
index 0858fd63528..4cdff6161bf 100644
--- a/dts/upstream/Bindings/clock/qcom,gpucc.yaml
+++ b/dts/upstream/Bindings/clock/qcom,gpucc.yaml
@@ -8,6 +8,7 @@ title: Qualcomm Graphics Clock & Reset Controller
 
 maintainers:
   - Taniya Das <quic_tdas@quicinc.com>
+  - Imran Shaik <quic_imrashai@quicinc.com>
 
 description: |
   Qualcomm graphics clock control module provides the clocks, resets and power
@@ -23,10 +24,12 @@ description: |
     include/dt-bindings/clock/qcom,gpucc-sm8150.h
     include/dt-bindings/clock/qcom,gpucc-sm8250.h
     include/dt-bindings/clock/qcom,gpucc-sm8350.h
+    include/dt-bindings/clock/qcom,qcs8300-gpucc.h
 
 properties:
   compatible:
     enum:
+      - qcom,qcs8300-gpucc
       - qcom,sdm845-gpucc
       - qcom,sa8775p-gpucc
       - qcom,sc7180-gpucc
diff --git a/dts/upstream/Bindings/clock/qcom,ipq9574-cmn-pll.yaml b/dts/upstream/Bindings/clock/qcom,ipq9574-cmn-pll.yaml
new file mode 100644
index 00000000000..f869b3739be
--- /dev/null
+++ b/dts/upstream/Bindings/clock/qcom,ipq9574-cmn-pll.yaml
@@ -0,0 +1,77 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/qcom,ipq9574-cmn-pll.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm CMN PLL Clock Controller on IPQ SoC
+
+maintainers:
+  - Bjorn Andersson <andersson@kernel.org>
+  - Luo Jie <quic_luoj@quicinc.com>
+
+description:
+  The CMN (or common) PLL clock controller expects a reference
+  input clock. This reference clock is from the on-board Wi-Fi.
+  The CMN PLL supplies a number of fixed rate output clocks to
+  the devices providing networking functions and to GCC. These
+  networking hardware include PPE (packet process engine), PCS
+  and the externally connected switch or PHY devices. The CMN
+  PLL block also outputs fixed rate clocks to GCC. The PLL's
+  primary function is to enable fixed rate output clocks for
+  networking hardware functions used with the IPQ SoC.
+
+properties:
+  compatible:
+    enum:
+      - qcom,ipq9574-cmn-pll
+
+  reg:
+    maxItems: 1
+
+  clocks:
+    items:
+      - description: The reference clock. The supported clock rates include
+          25000000, 31250000, 40000000, 48000000, 50000000 and 96000000 HZ.
+      - description: The AHB clock
+      - description: The SYS clock
+    description:
+      The reference clock is the source clock of CMN PLL, which is from the
+      Wi-Fi. The AHB and SYS clocks must be enabled to access CMN PLL
+      clock registers.
+
+  clock-names:
+    items:
+      - const: ref
+      - const: ahb
+      - const: sys
+
+  "#clock-cells":
+    const: 1
+
+required:
+  - compatible
+  - reg
+  - clocks
+  - clock-names
+  - "#clock-cells"
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/qcom,ipq-cmn-pll.h>
+    #include <dt-bindings/clock/qcom,ipq9574-gcc.h>
+
+    cmn_pll: clock-controller@9b000 {
+        compatible = "qcom,ipq9574-cmn-pll";
+        reg = <0x0009b000 0x800>;
+        clocks = <&cmn_pll_ref_clk>,
+                 <&gcc GCC_CMN_12GPLL_AHB_CLK>,
+                 <&gcc GCC_CMN_12GPLL_SYS_CLK>;
+        clock-names = "ref", "ahb", "sys";
+        #clock-cells = <1>;
+        assigned-clocks = <&cmn_pll CMN_PLL_CLK>;
+        assigned-clock-rates-u64 = /bits/ 64 <12000000000>;
+    };
+...
diff --git a/dts/upstream/Bindings/clock/qcom,mmcc.yaml b/dts/upstream/Bindings/clock/qcom,mmcc.yaml
index aa35a40648b..59ac288ca5f 100644
--- a/dts/upstream/Bindings/clock/qcom,mmcc.yaml
+++ b/dts/upstream/Bindings/clock/qcom,mmcc.yaml
@@ -78,6 +78,7 @@ allOf:
     then:
       properties:
         clocks:
+          minItems: 8
           items:
             - description: Board PXO source
             - description: PLL 3 clock
@@ -87,8 +88,10 @@ allOf:
             - description: DSI phy instance 2 dsi clock
             - description: DSI phy instance 2 byte clock
             - description: HDMI phy PLL clock
+            - description: LVDS PLL clock
 
         clock-names:
+          minItems: 8
           items:
             - const: pxo
             - const: pll3
@@ -98,6 +101,7 @@ allOf:
             - const: dsi2pll
             - const: dsi2pllbyte
             - const: hdmipll
+            - const: lvdspll
 
   - if:
       properties:
diff --git a/dts/upstream/Bindings/clock/qcom,qcs615-gcc.yaml b/dts/upstream/Bindings/clock/qcom,qcs615-gcc.yaml
new file mode 100644
index 00000000000..4a828e102d2
--- /dev/null
+++ b/dts/upstream/Bindings/clock/qcom,qcs615-gcc.yaml
@@ -0,0 +1,59 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/qcom,qcs615-gcc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Global Clock & Reset Controller on QCS615
+
+maintainers:
+  - Taniya Das <quic_tdas@quicinc.com>
+
+description: |
+  Qualcomm global clock control module provides the clocks, resets and power
+  domains on QCS615.
+
+  See also: include/dt-bindings/clock/qcom,qcs615-gcc.h
+
+properties:
+  compatible:
+    const: qcom,qcs615-gcc
+
+  clocks:
+    items:
+      - description: Board XO source
+      - description: Board active XO source
+      - description: Sleep clock source
+
+  clock-names:
+    items:
+      - const: bi_tcxo
+      - const: bi_tcxo_ao
+      - const: sleep_clk
+
+required:
+  - compatible
+  - clocks
+  - clock-names
+  - '#power-domain-cells'
+
+allOf:
+  - $ref: qcom,gcc.yaml#
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/qcom,rpmh.h>
+    clock-controller@100000 {
+      compatible = "qcom,qcs615-gcc";
+      reg = <0x00100000 0x1f0000>;
+      clocks = <&rpmhcc RPMH_CXO_CLK>,
+               <&rpmhcc RPMH_CXO_CLK_A>,
+               <&sleep_clk>;
+      clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk";
+      #clock-cells = <1>;
+      #reset-cells = <1>;
+      #power-domain-cells = <1>;
+    };
+...
diff --git a/dts/upstream/Bindings/clock/qcom,rpmcc.yaml b/dts/upstream/Bindings/clock/qcom,rpmcc.yaml
index 02fcffe93f1..be3835e2e04 100644
--- a/dts/upstream/Bindings/clock/qcom,rpmcc.yaml
+++ b/dts/upstream/Bindings/clock/qcom,rpmcc.yaml
@@ -33,6 +33,8 @@ properties:
           - qcom,rpmcc-msm8916
           - qcom,rpmcc-msm8917
           - qcom,rpmcc-msm8936
+          - qcom,rpmcc-msm8937
+          - qcom,rpmcc-msm8940
           - qcom,rpmcc-msm8953
           - qcom,rpmcc-msm8974
           - qcom,rpmcc-msm8976
@@ -110,6 +112,8 @@ allOf:
               - qcom,rpmcc-msm8916
               - qcom,rpmcc-msm8917
               - qcom,rpmcc-msm8936
+              - qcom,rpmcc-msm8937
+              - qcom,rpmcc-msm8940
               - qcom,rpmcc-msm8953
               - qcom,rpmcc-msm8974
               - qcom,rpmcc-msm8976
diff --git a/dts/upstream/Bindings/clock/qcom,rpmhcc.yaml b/dts/upstream/Bindings/clock/qcom,rpmhcc.yaml
index a561a306b94..dcb872b9cf3 100644
--- a/dts/upstream/Bindings/clock/qcom,rpmhcc.yaml
+++ b/dts/upstream/Bindings/clock/qcom,rpmhcc.yaml
@@ -17,6 +17,7 @@ description: |
 properties:
   compatible:
     enum:
+      - qcom,qcs615-rpmh-clk
       - qcom,qdu1000-rpmh-clk
       - qcom,sa8775p-rpmh-clk
       - qcom,sar2130p-rpmh-clk
@@ -37,6 +38,7 @@ properties:
       - qcom,sm8450-rpmh-clk
       - qcom,sm8550-rpmh-clk
       - qcom,sm8650-rpmh-clk
+      - qcom,sm8750-rpmh-clk
       - qcom,x1e80100-rpmh-clk
 
   clocks:
diff --git a/dts/upstream/Bindings/clock/qcom,sa8775p-camcc.yaml b/dts/upstream/Bindings/clock/qcom,sa8775p-camcc.yaml
index 36a60d8f5ae..81623f59d11 100644
--- a/dts/upstream/Bindings/clock/qcom,sa8775p-camcc.yaml
+++ b/dts/upstream/Bindings/clock/qcom,sa8775p-camcc.yaml
@@ -8,16 +8,20 @@ title: Qualcomm Camera Clock & Reset Controller on SA8775P
 
 maintainers:
   - Taniya Das <quic_tdas@quicinc.com>
+  - Imran Shaik <quic_imrashai@quicinc.com>
 
 description: |
   Qualcomm camera clock control module provides the clocks, resets and power
   domains on SA8775p.
 
-  See also: include/dt-bindings/clock/qcom,sa8775p-camcc.h
+  See also:
+    include/dt-bindings/clock/qcom,qcs8300-camcc.h
+    include/dt-bindings/clock/qcom,sa8775p-camcc.h
 
 properties:
   compatible:
     enum:
+      - qcom,qcs8300-camcc
       - qcom,sa8775p-camcc
 
   clocks:
diff --git a/dts/upstream/Bindings/clock/qcom,sa8775p-videocc.yaml b/dts/upstream/Bindings/clock/qcom,sa8775p-videocc.yaml
index 928131bff4c..07e5d811d81 100644
--- a/dts/upstream/Bindings/clock/qcom,sa8775p-videocc.yaml
+++ b/dts/upstream/Bindings/clock/qcom,sa8775p-videocc.yaml
@@ -18,6 +18,7 @@ description: |
 properties:
   compatible:
     enum:
+      - qcom,qcs8300-videocc
       - qcom,sa8775p-videocc
 
   clocks:
diff --git a/dts/upstream/Bindings/clock/qcom,sc7280-lpasscorecc.yaml b/dts/upstream/Bindings/clock/qcom,sc7280-lpasscorecc.yaml
index deee5423d66..488d6395942 100644
--- a/dts/upstream/Bindings/clock/qcom,sc7280-lpasscorecc.yaml
+++ b/dts/upstream/Bindings/clock/qcom,sc7280-lpasscorecc.yaml
@@ -18,12 +18,6 @@ description: |
     include/dt-bindings/clock/qcom,lpassaudiocc-sc7280.h
 
 properties:
-  clocks: true
-
-  clock-names: true
-
-  reg: true
-
   compatible:
     enum:
       - qcom,sc7280-lpassaoncc
@@ -31,12 +25,24 @@ properties:
       - qcom,sc7280-lpasscorecc
       - qcom,sc7280-lpasshm
 
-  power-domains:
-    maxItems: 1
+  reg:
+    minItems: 1
+    maxItems: 2
+
+  clocks:
+    minItems: 1
+    maxItems: 3
+
+  clock-names:
+    minItems: 1
+    maxItems: 3
 
   '#clock-cells':
     const: 1
 
+  power-domains:
+    maxItems: 1
+
   '#power-domain-cells':
     const: 1
 
@@ -57,8 +63,6 @@ required:
   - '#clock-cells'
   - '#power-domain-cells'
 
-additionalProperties: false
-
 allOf:
   - if:
       properties:
@@ -125,6 +129,9 @@ allOf:
 
         reg:
           maxItems: 1
+
+additionalProperties: false
+
 examples:
   - |
     #include <dt-bindings/clock/qcom,rpmh.h>
diff --git a/dts/upstream/Bindings/clock/qcom,sdm845-camcc.yaml b/dts/upstream/Bindings/clock/qcom,sdm845-camcc.yaml
index 810b852ae37..fa95c3a1ba3 100644
--- a/dts/upstream/Bindings/clock/qcom,sdm845-camcc.yaml
+++ b/dts/upstream/Bindings/clock/qcom,sdm845-camcc.yaml
@@ -20,7 +20,11 @@ allOf:
 
 properties:
   compatible:
-    const: qcom,sdm845-camcc
+    oneOf:
+      - items:
+          - const: qcom,sdm670-camcc
+          - const: qcom,sdm845-camcc
+      - const: qcom,sdm845-camcc
 
   clocks:
     items:
diff --git a/dts/upstream/Bindings/clock/qcom,sm6115-lpasscc.yaml b/dts/upstream/Bindings/clock/qcom,sm6115-lpasscc.yaml
new file mode 100644
index 00000000000..8cbab3fbb66
--- /dev/null
+++ b/dts/upstream/Bindings/clock/qcom,sm6115-lpasscc.yaml
@@ -0,0 +1,46 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/qcom,sm6115-lpasscc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm LPASS Core & Audio Clock Controller on SM6115
+
+maintainers:
+  - Konrad Dybcio <konradybcio@kernel.org>
+  - Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
+
+description: |
+  Qualcomm LPASS core and audio clock controllers provide audio-related resets
+  on SM6115 and its derivatives.
+
+  See also::
+    include/dt-bindings/clock/qcom,sm6115-lpasscc.h
+
+properties:
+  compatible:
+    enum:
+      - qcom,sm6115-lpassaudiocc
+      - qcom,sm6115-lpasscc
+
+  reg:
+    maxItems: 1
+
+  '#reset-cells':
+    const: 1
+
+required:
+  - compatible
+  - reg
+  - '#reset-cells'
+
+additionalProperties: false
+
+examples:
+  - |
+    lpass_audiocc: clock-controller@a6a9000 {
+        compatible = "qcom,sm6115-lpassaudiocc";
+        reg = <0x0a6a9000 0x1000>;
+        #reset-cells = <1>;
+    };
+...
diff --git a/dts/upstream/Bindings/clock/qcom,sm8450-camcc.yaml b/dts/upstream/Bindings/clock/qcom,sm8450-camcc.yaml
index 0766f66c7dc..b88b6c9b399 100644
--- a/dts/upstream/Bindings/clock/qcom,sm8450-camcc.yaml
+++ b/dts/upstream/Bindings/clock/qcom,sm8450-camcc.yaml
@@ -19,7 +19,6 @@ description: |
     include/dt-bindings/clock/qcom,sm8450-camcc.h
     include/dt-bindings/clock/qcom,sm8550-camcc.h
     include/dt-bindings/clock/qcom,sm8650-camcc.h
-    include/dt-bindings/clock/qcom,x1e80100-camcc.h
 
 properties:
   compatible:
@@ -29,7 +28,6 @@ properties:
       - qcom,sm8475-camcc
       - qcom,sm8550-camcc
       - qcom,sm8650-camcc
-      - qcom,x1e80100-camcc
 
   clocks:
     items:
diff --git a/dts/upstream/Bindings/clock/qcom,sm8450-gpucc.yaml b/dts/upstream/Bindings/clock/qcom,sm8450-gpucc.yaml
index 5c65f5ecf0f..02968632fb3 100644
--- a/dts/upstream/Bindings/clock/qcom,sm8450-gpucc.yaml
+++ b/dts/upstream/Bindings/clock/qcom,sm8450-gpucc.yaml
@@ -32,6 +32,7 @@ properties:
       - qcom,sm8550-gpucc
       - qcom,sm8650-gpucc
       - qcom,x1e80100-gpucc
+      - qcom,x1p42100-gpucc
 
   clocks:
     items:
diff --git a/dts/upstream/Bindings/clock/qcom,sm8550-dispcc.yaml b/dts/upstream/Bindings/clock/qcom,sm8550-dispcc.yaml
index c57d55a9293..30e4b463157 100644
--- a/dts/upstream/Bindings/clock/qcom,sm8550-dispcc.yaml
+++ b/dts/upstream/Bindings/clock/qcom,sm8550-dispcc.yaml
@@ -12,11 +12,12 @@ maintainers:
 
 description: |
   Qualcomm display clock control module provides the clocks, resets and power
-  domains on SM8550.
+  domains on SM8550, SM8650, SM8750 and few other platforms.
 
   See also:
   - include/dt-bindings/clock/qcom,sm8550-dispcc.h
   - include/dt-bindings/clock/qcom,sm8650-dispcc.h
+  - include/dt-bindings/clock/qcom,sm8750-dispcc.h
   - include/dt-bindings/clock/qcom,x1e80100-dispcc.h
 
 properties:
@@ -25,6 +26,7 @@ properties:
       - qcom,sar2130p-dispcc
       - qcom,sm8550-dispcc
       - qcom,sm8650-dispcc
+      - qcom,sm8750-dispcc
       - qcom,x1e80100-dispcc
 
   clocks:
diff --git a/dts/upstream/Bindings/clock/qcom,sm8550-tcsr.yaml b/dts/upstream/Bindings/clock/qcom,sm8550-tcsr.yaml
index 3b546deb514..f3afbb25e86 100644
--- a/dts/upstream/Bindings/clock/qcom,sm8550-tcsr.yaml
+++ b/dts/upstream/Bindings/clock/qcom,sm8550-tcsr.yaml
@@ -16,6 +16,7 @@ description: |
   See also:
   - include/dt-bindings/clock/qcom,sm8550-tcsr.h
   - include/dt-bindings/clock/qcom,sm8650-tcsr.h
+  - include/dt-bindings/clock/qcom,sm8750-tcsr.h
 
 properties:
   compatible:
@@ -24,6 +25,7 @@ properties:
           - qcom,sar2130p-tcsr
           - qcom,sm8550-tcsr
           - qcom,sm8650-tcsr
+          - qcom,sm8750-tcsr
           - qcom,x1e80100-tcsr
       - const: syscon
 
diff --git a/dts/upstream/Bindings/clock/qcom,sm8750-gcc.yaml b/dts/upstream/Bindings/clock/qcom,sm8750-gcc.yaml
new file mode 100644
index 00000000000..aab7039fd28
--- /dev/null
+++ b/dts/upstream/Bindings/clock/qcom,sm8750-gcc.yaml
@@ -0,0 +1,62 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/qcom,sm8750-gcc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Global Clock & Reset Controller on SM8750
+
+maintainers:
+  - Taniya Das <quic_tdas@quicinc.com>
+
+description: |
+  Qualcomm global clock control module provides the clocks, resets and power
+  domains on SM8750
+
+  See also: include/dt-bindings/clock/qcom,sm8750-gcc.h
+
+properties:
+  compatible:
+    const: qcom,sm8750-gcc
+
+  clocks:
+    items:
+      - description: Board XO source
+      - description: Board Always On XO source
+      - description: Sleep clock source
+      - description: PCIE 0 Pipe clock source
+      - description: UFS Phy Rx symbol 0 clock source
+      - description: UFS Phy Rx symbol 1 clock source
+      - description: UFS Phy Tx symbol 0 clock source
+      - description: USB3 Phy wrapper pipe clock source
+
+required:
+  - compatible
+  - clocks
+  - '#power-domain-cells'
+
+allOf:
+  - $ref: qcom,gcc.yaml#
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/qcom,rpmh.h>
+    clock-controller@100000 {
+      compatible = "qcom,sm8750-gcc";
+      reg = <0x00100000 0x001f4200>;
+      clocks = <&rpmhcc RPMH_CXO_CLK>,
+               <&rpmhcc RPMH_CXO_CLK_A>,
+               <&sleep_clk>,
+               <&pcie0_phy>,
+               <&ufs_mem_phy 0>,
+               <&ufs_mem_phy 1>,
+               <&ufs_mem_phy 2>,
+               <&usb_1_qmpphy>;
+      #clock-cells = <1>;
+      #reset-cells = <1>;
+      #power-domain-cells = <1>;
+    };
+
+...
diff --git a/dts/upstream/Bindings/clock/qcom,x1e80100-camcc.yaml b/dts/upstream/Bindings/clock/qcom,x1e80100-camcc.yaml
new file mode 100644
index 00000000000..5bbbaa15a26
--- /dev/null
+++ b/dts/upstream/Bindings/clock/qcom,x1e80100-camcc.yaml
@@ -0,0 +1,74 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/qcom,x1e80100-camcc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Camera Clock & Reset Controller on x1e80100
+
+maintainers:
+  - Bryan O'Donoghue <bryan.odonoghue@linaro.org>
+
+description: |
+  Qualcomm camera clock control module provides the clocks, resets and power
+  domains on x1e80100.
+
+  See also:
+    include/dt-bindings/clock/qcom,x1e80100-camcc.h
+
+allOf:
+  - $ref: qcom,gcc.yaml#
+
+properties:
+  compatible:
+    enum:
+      - qcom,x1e80100-camcc
+
+  reg:
+    maxItems: 1
+
+  clocks:
+    items:
+      - description: Camera AHB clock from GCC
+      - description: Board XO source
+      - description: Board active XO source
+      - description: Sleep clock source
+
+  power-domains:
+    items:
+      - description: A phandle to the MXC power-domain
+      - description: A phandle to the MMCX power-domain
+
+  required-opps:
+    maxItems: 1
+    description:
+      A phandle to an OPP node describing MMCX performance points.
+
+required:
+  - compatible
+  - clocks
+  - power-domains
+  - required-opps
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/qcom,x1e80100-gcc.h>
+    #include <dt-bindings/clock/qcom,rpmh.h>
+    #include <dt-bindings/power/qcom,rpmhpd.h>
+    clock-controller@ade0000 {
+      compatible = "qcom,x1e80100-camcc";
+      reg = <0xade0000 0x20000>;
+      clocks = <&gcc GCC_CAMERA_AHB_CLK>,
+               <&rpmhcc RPMH_CXO_CLK>,
+               <&rpmhcc RPMH_CXO_CLK_A>,
+               <&sleep_clk>;
+      power-domains = <&rpmhpd RPMHPD_MXC>,
+                      <&rpmhpd RPMHPD_MMCX>;
+      required-opps = <&rpmhpd_opp_low_svs>;
+      #clock-cells = <1>;
+      #reset-cells = <1>;
+      #power-domain-cells = <1>;
+    };
+...
diff --git a/dts/upstream/Bindings/clock/qcom,x1e80100-gcc.yaml b/dts/upstream/Bindings/clock/qcom,x1e80100-gcc.yaml
index 5951a60ab08..28797d0c5d8 100644
--- a/dts/upstream/Bindings/clock/qcom,x1e80100-gcc.yaml
+++ b/dts/upstream/Bindings/clock/qcom,x1e80100-gcc.yaml
@@ -17,7 +17,11 @@ description: |
 
 properties:
   compatible:
-    const: qcom,x1e80100-gcc
+    oneOf:
+      - items:
+          - const: qcom,x1p42100-gcc
+          - const: qcom,x1e80100-gcc
+      - const: qcom,x1e80100-gcc
 
   clocks:
     items:
diff --git a/dts/upstream/Bindings/clock/renesas,5p35023.yaml b/dts/upstream/Bindings/clock/renesas,5p35023.yaml
index 42b6f80613f..162d3803518 100644
--- a/dts/upstream/Bindings/clock/renesas,5p35023.yaml
+++ b/dts/upstream/Bindings/clock/renesas,5p35023.yaml
@@ -31,6 +31,7 @@ description: |
 properties:
   compatible:
     enum:
+      - renesas,5l35023
       - renesas,5p35023
 
   reg:
diff --git a/dts/upstream/Bindings/clock/renesas,rzv2h-cpg.yaml b/dts/upstream/Bindings/clock/renesas,rzv2h-cpg.yaml
index 926c503bed1..c3fe76abd54 100644
--- a/dts/upstream/Bindings/clock/renesas,rzv2h-cpg.yaml
+++ b/dts/upstream/Bindings/clock/renesas,rzv2h-cpg.yaml
@@ -4,19 +4,22 @@
 $id: http://devicetree.org/schemas/clock/renesas,rzv2h-cpg.yaml#
 $schema: http://devicetree.org/meta-schemas/core.yaml#
 
-title: Renesas RZ/V2H(P) Clock Pulse Generator (CPG)
+title: Renesas RZ/{G3E,V2H(P)} Clock Pulse Generator (CPG)
 
 maintainers:
   - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
 
 description:
-  On Renesas RZ/V2H(P) SoCs, the CPG (Clock Pulse Generator) handles generation
-  and control of clock signals for the IP modules, generation and control of resets,
-  and control over booting, low power consumption and power supply domains.
+  On Renesas RZ/{G3E,V2H(P)} SoCs, the CPG (Clock Pulse Generator) handles
+  generation and control of clock signals for the IP modules, generation and
+  control of resets, and control over booting, low power consumption and power
+  supply domains.
 
 properties:
   compatible:
-    const: renesas,r9a09g057-cpg
+    enum:
+      - renesas,r9a09g047-cpg # RZ/G3E
+      - renesas,r9a09g057-cpg # RZ/V2H
 
   reg:
     maxItems: 1
@@ -37,7 +40,7 @@ properties:
     description: |
       - For CPG core clocks, the two clock specifier cells must be "CPG_CORE"
         and a core clock reference, as defined in
-        <dt-bindings/clock/renesas,r9a09g057-cpg.h>,
+        <dt-bindings/clock/renesas,r9a09g0*-cpg.h>,
       - For module clocks, the two clock specifier cells must be "CPG_MOD" and
         a module number.  The module number is calculated as the CLKON register
         offset index multiplied by 16, plus the actual bit in the register
diff --git a/dts/upstream/Bindings/clock/samsung,exynos990-clock.yaml b/dts/upstream/Bindings/clock/samsung,exynos990-clock.yaml
new file mode 100644
index 00000000000..9e7944b5f13
--- /dev/null
+++ b/dts/upstream/Bindings/clock/samsung,exynos990-clock.yaml
@@ -0,0 +1,121 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/samsung,exynos990-clock.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Samsung Exynos990 SoC clock controller
+
+maintainers:
+  - Igor Belwon <igor.belwon@mentallysanemainliners.org>
+  - Chanwoo Choi <cw00.choi@samsung.com>
+  - Krzysztof Kozlowski <krzk@kernel.org>
+
+description: |
+  Exynos990 clock controller is comprised of several CMU units, generating
+  clocks for different domains. Those CMU units are modeled as separate device
+  tree nodes, and might depend on each other. The root clock in that root tree
+  is an external clock: OSCCLK (26 MHz). This external clock must be defined
+  as a fixed-rate clock in dts.
+
+  CMU_TOP is a top-level CMU, where all base clocks are prepared using PLLs and
+  dividers; all other clocks of function blocks (other CMUs) are usually
+  derived from CMU_TOP.
+
+  Each clock is assigned an identifier and client nodes can use this identifier
+  to specify the clock which they consume. All clocks available for usage
+  in clock consumer nodes are defined as preprocessor macros in
+  'include/dt-bindings/clock/samsung,exynos990.h' header.
+
+properties:
+  compatible:
+    enum:
+      - samsung,exynos990-cmu-hsi0
+      - samsung,exynos990-cmu-top
+
+  clocks:
+    minItems: 1
+    maxItems: 5
+
+  clock-names:
+    minItems: 1
+    maxItems: 5
+
+  "#clock-cells":
+    const: 1
+
+  reg:
+    maxItems: 1
+
+required:
+  - compatible
+  - clocks
+  - clock-names
+  - "#clock-cells"
+  - reg
+
+allOf:
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: samsung,exynos990-cmu-hsi0
+
+    then:
+      properties:
+        clocks:
+          items:
+            - description: External reference clock (26 MHz)
+            - description: CMU_HSI0 BUS clock (from CMU_TOP)
+            - description: CMU_HSI0 USB31DRD clock (from CMU_TOP)
+            - description: CMU_HSI0 USBDP_DEBUG clock (from CMU_TOP)
+            - description: CMU_HSI0 DPGTC clock (from CMU_TOP)
+
+        clock-names:
+          items:
+            - const: oscclk
+            - const: bus
+            - const: usb31drd
+            - const: usbdp_debug
+            - const: dpgtc
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: samsung,exynos990-cmu-top
+
+    then:
+      properties:
+        clocks:
+          items:
+            - description: External reference clock (26 MHz)
+
+        clock-names:
+          items:
+            - const: oscclk
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/samsung,exynos990.h>
+
+    cmu_hsi0: clock-controller@10a00000 {
+        compatible = "samsung,exynos990-cmu-hsi0";
+        reg = <0x10a00000 0x8000>;
+        #clock-cells = <1>;
+
+        clocks = <&oscclk>,
+                 <&cmu_top CLK_DOUT_CMU_HSI0_BUS>,
+                 <&cmu_top CLK_DOUT_CMU_HSI0_USB31DRD>,
+                 <&cmu_top CLK_DOUT_CMU_HSI0_USBDP_DEBUG>,
+                 <&cmu_top CLK_DOUT_CMU_HSI0_DPGTC>;
+        clock-names = "oscclk",
+                      "bus",
+                      "usb31drd",
+                      "usbdp_debug",
+                      "dpgtc";
+    };
+
+...
diff --git a/dts/upstream/Bindings/clock/st,stm32-rcc.txt b/dts/upstream/Bindings/clock/st,stm32-rcc.txt
deleted file mode 100644
index cfa04b614d8..00000000000
--- a/dts/upstream/Bindings/clock/st,stm32-rcc.txt
+++ /dev/null
@@ -1,138 +0,0 @@
-STMicroelectronics STM32 Reset and Clock Controller
-===================================================
-
-The RCC IP is both a reset and a clock controller.
-
-Please refer to clock-bindings.txt for common clock controller binding usage.
-Please also refer to reset.txt for common reset controller binding usage.
-
-Required properties:
-- compatible: Should be:
-  "st,stm32f42xx-rcc"
-  "st,stm32f469-rcc"
-  "st,stm32f746-rcc"
-  "st,stm32f769-rcc"
-
-- reg: should be register base and length as documented in the
-  datasheet
-- #reset-cells: 1, see below
-- #clock-cells: 2, device nodes should specify the clock in their "clocks"
-  property, containing a phandle to the clock device node, an index selecting
-  between gated clocks and other clocks and an index specifying the clock to
-  use.
-- clocks: External oscillator clock phandle
-  - high speed external clock signal (HSE)
-  - external I2S clock (I2S_CKIN)
-
-Example:
-
-	rcc: rcc@40023800 {
-		#reset-cells = <1>;
-		#clock-cells = <2>
-		compatible = "st,stm32f42xx-rcc", "st,stm32-rcc";
-		reg = <0x40023800 0x400>;
-		clocks = <&clk_hse>, <&clk_i2s_ckin>;
-	};
-
-Specifying gated clocks
-=======================
-
-The primary index must be set to 0.
-
-The secondary index is the bit number within the RCC register bank, starting
-from the first RCC clock enable register (RCC_AHB1ENR, address offset 0x30).
-
-It is calculated as: index = register_offset / 4 * 32 + bit_offset.
-Where bit_offset is the bit offset within the register (LSB is 0, MSB is 31).
-
-To simplify the usage and to share bit definition with the reset and clock
-drivers of the RCC IP, macros are available to generate the index in
-human-readble format.
-
-For STM32F4 series, the macro are available here:
- - include/dt-bindings/mfd/stm32f4-rcc.h
-
-Example:
-
-	/* Gated clock, AHB1 bit 0 (GPIOA) */
-	... {
-		clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOA)>
-	};
-
-	/* Gated clock, AHB2 bit 4 (CRYP) */
-	... {
-		clocks = <&rcc 0 STM32F4_AHB2_CLOCK(CRYP)>
-	};
-
-Specifying other clocks
-=======================
-
-The primary index must be set to 1.
-
-The secondary index is bound with the following magic numbers:
-
-	0	SYSTICK
-	1	FCLK
-	2	CLK_LSI		(low-power clock source)
-	3	CLK_LSE		(generated from a 32.768 kHz low-speed external
-				 crystal or ceramic resonator)
-	4	CLK_HSE_RTC	(HSE division factor for RTC clock)
-	5	CLK_RTC		(real-time clock)
-	6	PLL_VCO_I2S	(vco frequency of I2S pll)
-	7	PLL_VCO_SAI	(vco frequency of SAI pll)
-	8	CLK_LCD		(LCD-TFT)
-	9	CLK_I2S		(I2S clocks)
-	10	CLK_SAI1	(audio clocks)
-	11	CLK_SAI2
-	12	CLK_I2SQ_PDIV	(post divisor of pll i2s q divisor)
-	13	CLK_SAIQ_PDIV	(post divisor of pll sai q divisor)
-
-	14	CLK_HSI		(Internal ocscillator clock)
-	15	CLK_SYSCLK	(System Clock)
-	16	CLK_HDMI_CEC	(HDMI-CEC clock)
-	17	CLK_SPDIF	(SPDIF-Rx clock)
-	18	CLK_USART1	(U(s)arts clocks)
-	19	CLK_USART2
-	20	CLK_USART3
-	21	CLK_UART4
-	22	CLK_UART5
-	23	CLK_USART6
-	24	CLK_UART7
-	25	CLK_UART8
-	26	CLK_I2C1	(I2S clocks)
-	27	CLK_I2C2
-	28	CLK_I2C3
-	29	CLK_I2C4
-	30	CLK_LPTIMER	(LPTimer1 clock)
-	31	CLK_PLL_SRC
-	32	CLK_DFSDM1
-	33	CLK_ADFSDM1
-	34	CLK_F769_DSI
-)
-
-Example:
-
-	/* Misc clock, FCLK */
-	... {
-		clocks = <&rcc 1 STM32F4_APB1_CLOCK(TIM2)>
-	};
-
-
-Specifying softreset control of devices
-=======================================
-
-Device nodes should specify the reset channel required in their "resets"
-property, containing a phandle to the reset device node and an index specifying
-which channel to use.
-The index is the bit number within the RCC registers bank, starting from RCC
-base address.
-It is calculated as: index = register_offset / 4 * 32 + bit_offset.
-Where bit_offset is the bit offset within the register.
-For example, for CRC reset:
-  crc = AHB1RSTR_offset / 4 * 32 + CRCRST_bit_offset = 0x10 / 4 * 32 + 12 = 140
-
-example:
-
-	timer2 {
-		resets	= <&rcc STM32F4_APB1_RESET(TIM2)>;
-	};
diff --git a/dts/upstream/Bindings/clock/st,stm32-rcc.yaml b/dts/upstream/Bindings/clock/st,stm32-rcc.yaml
new file mode 100644
index 00000000000..f83a6120d65
--- /dev/null
+++ b/dts/upstream/Bindings/clock/st,stm32-rcc.yaml
@@ -0,0 +1,144 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/st,stm32-rcc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: STMicroelectronics STM32 Reset Clock Controller
+
+maintainers:
+  - Dario Binacchi <dario.binacchi@amarulasolutions.com>
+
+description: |
+  The RCC IP is both a reset and a clock controller.
+  The reset phandle argument is the bit number within the RCC registers bank,
+  starting from RCC base address.
+
+properties:
+  compatible:
+    oneOf:
+      - items:
+          - enum:
+              - st,stm32f42xx-rcc
+              - st,stm32f746-rcc
+              - st,stm32h743-rcc
+          - const: st,stm32-rcc
+      - items:
+          - enum:
+              - st,stm32f469-rcc
+          - const: st,stm32f42xx-rcc
+          - const: st,stm32-rcc
+      - items:
+          - enum:
+              - st,stm32f769-rcc
+          - const: st,stm32f746-rcc
+          - const: st,stm32-rcc
+
+  reg:
+    maxItems: 1
+
+  '#reset-cells':
+    const: 1
+
+  '#clock-cells':
+    enum: [1, 2]
+
+  clocks:
+    minItems: 2
+    maxItems: 3
+
+  st,syscfg:
+    $ref: /schemas/types.yaml#/definitions/phandle
+    description:
+      Phandle to system configuration controller. It can be used to control the
+      power domain circuitry.
+
+  st,ssc-modfreq-hz:
+    description:
+      The modulation frequency for main PLL (in Hz)
+
+  st,ssc-moddepth-permyriad:
+    $ref: /schemas/types.yaml#/definitions/uint32
+    description:
+      The modulation rate for main PLL (in permyriad, i.e. 0.01%)
+    minimum: 25
+    maximum: 200
+
+  st,ssc-modmethod:
+    $ref: /schemas/types.yaml#/definitions/string
+    description:
+      The modulation techniques for main PLL.
+    items:
+      enum:
+        - center-spread
+        - down-spread
+
+required:
+  - compatible
+  - reg
+  - '#reset-cells'
+  - '#clock-cells'
+  - clocks
+  - st,syscfg
+
+allOf:
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: st,stm32h743-rcc
+    then:
+      properties:
+        '#clock-cells':
+          const: 1
+          description: |
+            The clock index for the specified type.
+        clocks:
+          items:
+            - description: high speed external (HSE) clock input
+            - description: low speed external (LSE) clock input
+            - description: Inter-IC sound (I2S) clock input
+        st,ssc-modfreq-hz: false
+        st,ssc-moddepth-permyriad: false
+        st,ssc-modmethod: false
+
+    else:
+      properties:
+        '#clock-cells':
+          const: 2
+          description: |
+            - The first cell is the clock type, possible values are 0 for
+              gated clocks and 1 otherwise.
+            - The second cell is the clock index for the specified type.
+        clocks:
+          items:
+            - description: high speed external (HSE) clock input
+            - description: Inter-IC sound (I2S) clock input
+
+additionalProperties: false
+
+examples:
+  # Reset and Clock Control Module node:
+  - |
+    clock-controller@40023800 {
+        compatible = "st,stm32f42xx-rcc", "st,stm32-rcc";
+        reg = <0x40023800 0x400>;
+        #clock-cells = <2>;
+        #reset-cells = <1>;
+        clocks = <&clk_hse>, <&clk_i2s_ckin>;
+        st,syscfg = <&pwrcfg>;
+        st,ssc-modfreq-hz = <10000>;
+        st,ssc-moddepth-permyriad = <200>;
+        st,ssc-modmethod = "center-spread";
+    };
+  - |
+    clock-controller@58024400 {
+        compatible = "st,stm32h743-rcc", "st,stm32-rcc";
+        reg = <0x58024400 0x400>;
+        #clock-cells = <1>;
+        #reset-cells = <1>;
+        clocks = <&clk_hse>, <&clk_lse>, <&clk_i2s>;
+        st,syscfg = <&pwrcfg>;
+    };
+
+...
diff --git a/dts/upstream/Bindings/clock/st,stm32mp1-rcc.yaml b/dts/upstream/Bindings/clock/st,stm32mp1-rcc.yaml
index 9b3aaae546c..e72f46e79b9 100644
--- a/dts/upstream/Bindings/clock/st,stm32mp1-rcc.yaml
+++ b/dts/upstream/Bindings/clock/st,stm32mp1-rcc.yaml
@@ -21,7 +21,7 @@ description: |
   =================
 
   All available clocks are defined as preprocessor macros in
-  dt-bindings/clock/stm32mp1-clks.h header and can be used in device
+  include/dt-bindings/clock/stm32mp1-clks.h header and can be used in device
   tree sources.
 
   Specifying softreset control of devices
@@ -40,8 +40,8 @@ description: |
           = 0x180 / 4 * 32 + 0 = 3072
 
   The list of valid indices for STM32MP1 is available in:
-  include/dt-bindings/reset-controller/stm32mp1-resets.h
-  include/dt-bindings/reset-controller/stm32mp13-resets.h
+  include/dt-bindings/reset/stm32mp1-resets.h
+  include/dt-bindings/reset/stm32mp13-resets.h
 
   This file implements defines like:
   #define LTDC_R	3072
diff --git a/dts/upstream/Bindings/clock/ti/composite.txt b/dts/upstream/Bindings/clock/ti/composite.txt
deleted file mode 100644
index 238e6f7d74f..00000000000
--- a/dts/upstream/Bindings/clock/ti/composite.txt
+++ /dev/null
@@ -1,55 +0,0 @@
-Binding for TI composite clock.
-
-This binding uses the common clock binding[1]. It assumes a
-register-mapped composite clock with multiple different sub-types;
-
-a multiplexer clock with multiple input clock signals or parents, one
-of which can be selected as output, this behaves exactly as [2]
-
-an adjustable clock rate divider, this behaves exactly as [3]
-
-a gating function which can be used to enable and disable the output
-clock, this behaves exactly as [4]
-
-The binding must provide a list of the component clocks that shall be
-merged to this clock. The component clocks shall be of one of the
-"ti,*composite*-clock" types.
-
-[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
-[2] Documentation/devicetree/bindings/clock/ti/ti,mux-clock.yaml
-[3] Documentation/devicetree/bindings/clock/ti/ti,divider-clock.yaml
-[4] Documentation/devicetree/bindings/clock/ti/gate.txt
-
-Required properties:
-- compatible : shall be: "ti,composite-clock"
-- clocks : link phandles of component clocks
-- #clock-cells : from common clock binding; shall be set to 0.
-
-Optional properties:
-- clock-output-names : from common clock binding.
-
-Examples:
-
-usb_l4_gate_ick: usb_l4_gate_ick {
-	#clock-cells = <0>;
-	compatible = "ti,composite-interface-clock";
-	clocks = <&l4_ick>;
-	ti,bit-shift = <5>;
-	reg = <0x0a10>;
-};
-
-usb_l4_div_ick: usb_l4_div_ick {
-	#clock-cells = <0>;
-	compatible = "ti,composite-divider-clock";
-	clocks = <&l4_ick>;
-	ti,bit-shift = <4>;
-	ti,max-div = <1>;
-	reg = <0x0a40>;
-	ti,index-starts-at-one;
-};
-
-usb_l4_ick: usb_l4_ick {
-	#clock-cells = <0>;
-	compatible = "ti,composite-clock";
-	clocks = <&usb_l4_gate_ick>, <&usb_l4_div_ick>;
-};
diff --git a/dts/upstream/Bindings/clock/ti/gate.txt b/dts/upstream/Bindings/clock/ti/gate.txt
deleted file mode 100644
index a8e0335b006..00000000000
--- a/dts/upstream/Bindings/clock/ti/gate.txt
+++ /dev/null
@@ -1,105 +0,0 @@
-Binding for Texas Instruments gate clock.
-
-This binding uses the common clock binding[1]. This clock is
-quite much similar to the basic gate-clock [2], however,
-it supports a number of additional features. If no register
-is provided for this clock, the code assumes that a clockdomain
-will be controlled instead and the corresponding hw-ops for
-that is used.
-
-[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
-[2] Documentation/devicetree/bindings/clock/gpio-gate-clock.yaml
-[3] Documentation/devicetree/bindings/clock/ti/clockdomain.txt
-
-Required properties:
-- compatible : shall be one of:
-  "ti,gate-clock" - basic gate clock
-  "ti,wait-gate-clock" - gate clock which waits until clock is active before
-			 returning from clk_enable()
-  "ti,dss-gate-clock" - gate clock with DSS specific hardware handling
-  "ti,am35xx-gate-clock" - gate clock with AM35xx specific hardware handling
-  "ti,clkdm-gate-clock" - clockdomain gate clock, which derives its functional
-			  clock directly from a clockdomain, see [3] how
-			  to map clockdomains properly
-  "ti,hsdiv-gate-clock" - gate clock with OMAP36xx specific hardware handling,
-			  required for a hardware errata
-  "ti,composite-gate-clock" - composite gate clock, to be part of composite
-			      clock
-  "ti,composite-no-wait-gate-clock" - composite gate clock that does not wait
-				      for clock to be active before returning
-				      from clk_enable()
-- #clock-cells : from common clock binding; shall be set to 0
-- clocks : link to phandle of parent clock
-- reg : offset for register controlling adjustable gate, not needed for
-	ti,clkdm-gate-clock type
-
-Optional properties:
-- clock-output-names : from common clock binding.
-- ti,bit-shift : bit shift for programming the clock gate, invalid for
-		 ti,clkdm-gate-clock type
-- ti,set-bit-to-disable : inverts default gate programming. Setting the bit
-  gates the clock and clearing the bit ungates the clock.
-
-Examples:
-	mmchs2_fck: mmchs2_fck@48004a00 {
-		#clock-cells = <0>;
-		compatible = "ti,gate-clock";
-		clocks = <&core_96m_fck>;
-		reg = <0x0a00>;
-		ti,bit-shift = <25>;
-	};
-
-	uart4_fck_am35xx: uart4_fck_am35xx {
-		#clock-cells = <0>;
-		compatible = "ti,wait-gate-clock";
-		clocks = <&core_48m_fck>;
-		reg = <0x0a00>;
-		ti,bit-shift = <23>;
-	};
-
-	dss1_alwon_fck_3430es2: dss1_alwon_fck_3430es2@48004e00 {
-		#clock-cells = <0>;
-		compatible = "ti,dss-gate-clock";
-		clocks = <&dpll4_m4x2_ck>;
-		reg = <0x0e00>;
-		ti,bit-shift = <0>;
-	};
-
-	emac_ick: emac_ick@4800259c {
-		#clock-cells = <0>;
-		compatible = "ti,am35xx-gate-clock";
-		clocks = <&ipss_ick>;
-		reg = <0x059c>;
-		ti,bit-shift = <1>;
-	};
-
-	emu_src_ck: emu_src_ck {
-		#clock-cells = <0>;
-		compatible = "ti,clkdm-gate-clock";
-		clocks = <&emu_src_mux_ck>;
-	};
-
-	dpll4_m2x2_ck: dpll4_m2x2_ck@48004d00 {
-		#clock-cells = <0>;
-		compatible = "ti,hsdiv-gate-clock";
-		clocks = <&dpll4_m2x2_mul_ck>;
-		ti,bit-shift = <0x1b>;
-		reg = <0x0d00>;
-		ti,set-bit-to-disable;
-	};
-
-	vlynq_gate_fck: vlynq_gate_fck {
-		#clock-cells = <0>;
-		compatible = "ti,composite-gate-clock";
-		clocks = <&core_ck>;
-		ti,bit-shift = <3>;
-		reg = <0x0200>;
-	};
-
-	sys_clkout2_src_gate: sys_clkout2_src_gate {
-		#clock-cells = <0>;
-		compatible = "ti,composite-no-wait-gate-clock";
-		clocks = <&core_ck>;
-		ti,bit-shift = <15>;
-		reg = <0x0070>;
-	};
diff --git a/dts/upstream/Bindings/clock/ti/ti,composite-clock.yaml b/dts/upstream/Bindings/clock/ti/ti,composite-clock.yaml
new file mode 100644
index 00000000000..31a6794852c
--- /dev/null
+++ b/dts/upstream/Bindings/clock/ti/ti,composite-clock.yaml
@@ -0,0 +1,82 @@
+# SPDX-License-Identifier: GPL-2.0-only
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/ti/ti,composite-clock.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Texas Instruments composite clock
+
+maintainers:
+  - Tero Kristo <kristo@kernel.org>
+
+description: |
+  *Deprecated design pattern: one node per clock*
+
+  This binding assumes a register-mapped composite clock with multiple
+  different sub-types:
+
+    a multiplexer clock with multiple input clock signals or parents, one
+    of which can be selected as output, this behaves exactly as [1].
+
+    an adjustable clock rate divider, this behaves exactly as [2].
+
+    a gating function which can be used to enable and disable the output
+    clock, this behaves exactly as [3].
+
+  The binding must provide a list of the component clocks that shall be
+  merged to this clock. The component clocks shall be of one of the
+  "ti,*composite*-clock" types.
+
+  [1] Documentation/devicetree/bindings/clock/ti/ti,mux-clock.yaml
+  [2] Documentation/devicetree/bindings/clock/ti/ti,divider-clock.yaml
+  [3] Documentation/devicetree/bindings/clock/ti/ti,gate-clock.yaml
+
+properties:
+  compatible:
+    const: ti,composite-clock
+
+  "#clock-cells":
+    const: 0
+
+  clocks: true
+
+  clock-output-names:
+    maxItems: 1
+
+required:
+  - compatible
+  - "#clock-cells"
+  - clocks
+
+additionalProperties: false
+
+examples:
+  - |
+    bus {
+      #address-cells = <1>;
+      #size-cells = <0>;
+
+      usb_l4_gate_ick: clock-controller@a10 {
+        #clock-cells = <0>;
+        compatible = "ti,composite-gate-clock";
+        clocks = <&l4_ick>;
+        ti,bit-shift = <5>;
+        reg = <0x0a10>;
+      };
+
+      usb_l4_div_ick: clock-controller@a40 {
+        #clock-cells = <0>;
+        compatible = "ti,composite-divider-clock";
+        clocks = <&l4_ick>;
+        ti,bit-shift = <4>;
+        ti,max-div = <1>;
+        reg = <0x0a40>;
+        ti,index-starts-at-one;
+      };
+    };
+
+    clock-controller {
+      #clock-cells = <0>;
+      compatible = "ti,composite-clock";
+      clocks = <&usb_l4_gate_ick>, <&usb_l4_div_ick>;
+    };
diff --git a/dts/upstream/Bindings/clock/ti/ti,gate-clock.yaml b/dts/upstream/Bindings/clock/ti/ti,gate-clock.yaml
new file mode 100644
index 00000000000..eaa727ab0d7
--- /dev/null
+++ b/dts/upstream/Bindings/clock/ti/ti,gate-clock.yaml
@@ -0,0 +1,125 @@
+# SPDX-License-Identifier: GPL-2.0-only
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/ti/ti,gate-clock.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Texas Instruments gate clock
+
+maintainers:
+  - Tero Kristo <kristo@kernel.org>
+
+description: |
+  *Deprecated design pattern: one node per clock*
+
+  This clock is quite much similar to the basic gate-clock [1], however,
+  it supports a number of additional features. If no register
+  is provided for this clock, the code assumes that a clockdomain
+  will be controlled instead and the corresponding hw-ops for
+  that is used.
+
+  [1] Documentation/devicetree/bindings/clock/gpio-gate-clock.yaml
+  [2] Documentation/devicetree/bindings/clock/ti/clockdomain.txt
+
+properties:
+  compatible:
+    enum:
+      - ti,gate-clock           # basic gate clock
+      - ti,wait-gate-clock      # gate clock which waits until clock is
+                                # active before returning from clk_enable()
+      - ti,dss-gate-clock       # gate clock with DSS specific hardware
+                                # handling
+      - ti,am35xx-gate-clock    # gate clock with AM35xx specific hardware
+                                # handling
+      - ti,clkdm-gate-clock     # clockdomain gate clock, which derives its
+                                # functional clock directly from a
+                                # clockdomain, see [2] how to map
+                                # clockdomains properly
+      - ti,hsdiv-gate-clock     # gate clock with OMAP36xx specific hardware
+                                # handling, required for a hardware errata
+      - ti,composite-gate-clock # composite gate clock, to be part of
+                                # composite clock
+      - ti,composite-no-wait-gate-clock # composite gate clock that does not
+                                        # wait for clock to be active before
+                                        # returning from clk_enable()
+  "#clock-cells":
+    const: 0
+
+  clocks: true
+
+  clock-output-names:
+    maxItems: 1
+
+  reg:
+    maxItems: 1
+
+  ti,bit-shift:
+    $ref: /schemas/types.yaml#/definitions/uint32
+    description:
+      Number of bits to shift the bit-mask
+    maximum: 31
+    default: 0
+
+  ti,set-bit-to-disable:
+    type: boolean
+    description:
+      Inverts default gate programming. Setting the bit
+      gates the clock and clearing the bit ungates the clock.
+
+  ti,set-rate-parent:
+    type: boolean
+    description:
+      clk_set_rate is propagated to parent clock,
+
+if:
+  properties:
+    compatible:
+      contains:
+        const: ti,clkdm-gate-clock
+then:
+  properties:
+    reg: false
+  required:
+    - compatible
+    - "#clock-cells"
+    - clocks
+else:
+  required:
+    - compatible
+    - "#clock-cells"
+    - clocks
+    - reg
+
+additionalProperties: false
+
+examples:
+  - |
+    bus {
+      #address-cells = <1>;
+      #size-cells = <0>;
+
+      clock-controller@a00 {
+        #clock-cells = <0>;
+        compatible = "ti,gate-clock";
+        clocks = <&core_96m_fck>;
+        reg = <0x0a00>;
+        ti,bit-shift = <25>;
+      };
+
+      clock-controller@d00 {
+        compatible = "ti,hsdiv-gate-clock";
+        reg = <0x0d00>;
+        #clock-cells = <0>;
+        clocks = <&dpll4_m2x2_mul_ck>;
+        ti,bit-shift = <0x1b>;
+        ti,set-bit-to-disable;
+      };
+    };
+
+  - |
+    clock-controller {
+      #clock-cells = <0>;
+      compatible = "ti,clkdm-gate-clock";
+      clocks = <&emu_src_mux_ck>;
+    };
+
diff --git a/dts/upstream/Bindings/clock/xlnx,vcu.yaml b/dts/upstream/Bindings/clock/xlnx,vcu.yaml
new file mode 100644
index 00000000000..19dc923e2ee
--- /dev/null
+++ b/dts/upstream/Bindings/clock/xlnx,vcu.yaml
@@ -0,0 +1,59 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/xlnx,vcu.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+title: LogicoreIP designed compatible with Xilinx ZYNQ family.
+
+maintainers:
+  - Rohit Visavalia <rohit.visavalia@amd.com>
+
+description:
+  LogicoreIP design to provide the isolation between processing system
+  and programmable logic. Also provides the list of register set to configure
+  the frequency.
+
+properties:
+  compatible:
+    items:
+      - enum:
+          - xlnx,vcu
+          - xlnx,vcu-logicoreip-1.0
+
+  reg:
+    maxItems: 1
+
+  clocks:
+    items:
+      - description: pll ref clocksource
+      - description: aclk
+
+  clock-names:
+    items:
+      - const: pll_ref
+      - const: aclk
+
+  reset-gpios:
+    maxItems: 1
+
+required:
+  - reg
+  - clocks
+  - clock-names
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/gpio/gpio.h>
+    fpga {
+        #address-cells = <2>;
+        #size-cells = <2>;
+        xlnx_vcu: vcu@a0040000 {
+            compatible = "xlnx,vcu-logicoreip-1.0";
+            reg = <0x0 0xa0040000 0x0 0x1000>;
+            reset-gpios = <&gpio 78 GPIO_ACTIVE_HIGH>;
+            clocks = <&si570_1>, <&clkc 71>;
+            clock-names = "pll_ref", "aclk";
+        };
+    };
diff --git a/dts/upstream/Bindings/connector/usb-connector.yaml b/dts/upstream/Bindings/connector/usb-connector.yaml
index 67700440e23..11e40d225b9 100644
--- a/dts/upstream/Bindings/connector/usb-connector.yaml
+++ b/dts/upstream/Bindings/connector/usb-connector.yaml
@@ -293,6 +293,13 @@ properties:
       PD negotiation till BC1.2 detection completes.
     default: 0
 
+  pd-revision:
+    description: Specifies the maximum USB PD revision and version supported by
+      the connector. This property is specified in the following order;
+      <revision_major, revision_minor, version_major, version_minor>.
+    $ref: /schemas/types.yaml#/definitions/uint8-array
+    maxItems: 4
+
 dependencies:
   sink-vdos-v1: [ sink-vdos ]
   sink-vdos: [ sink-vdos-v1 ]
diff --git a/dts/upstream/Bindings/cpufreq/airoha,en7581-cpufreq.yaml b/dts/upstream/Bindings/cpufreq/airoha,en7581-cpufreq.yaml
new file mode 100644
index 00000000000..7d4510b3219
--- /dev/null
+++ b/dts/upstream/Bindings/cpufreq/airoha,en7581-cpufreq.yaml
@@ -0,0 +1,55 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/cpufreq/airoha,en7581-cpufreq.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Airoha EN7581 CPUFreq
+
+maintainers:
+  - Christian Marangi <ansuelsmth@gmail.com>
+
+description: |
+  On newer Airoha SoC, CPU Frequency is scaled indirectly with SMC commands
+  to ATF.
+
+  A virtual clock is exposed. This virtual clock is a get-only clock and
+  is used to expose the current global CPU clock. The frequency info comes
+  by the output of the SMC command that reports the clock in MHz.
+
+  The SMC sets the CPU clock by providing an index, this is modelled as
+  performance states in a power domain.
+
+  CPUs can't be individually scaled as the CPU frequency is shared across
+  all CPUs and is global.
+
+properties:
+  compatible:
+    const: airoha,en7581-cpufreq
+
+  '#clock-cells':
+    const: 0
+
+  '#power-domain-cells':
+    const: 0
+
+  operating-points-v2: true
+
+required:
+  - compatible
+  - '#clock-cells'
+  - '#power-domain-cells'
+  - operating-points-v2
+
+additionalProperties: false
+
+examples:
+  - |
+    performance-domain {
+        compatible = "airoha,en7581-cpufreq";
+
+        operating-points-v2 = <&cpu_smcc_opp_table>;
+
+        #power-domain-cells = <0>;
+        #clock-cells = <0>;
+    };
diff --git a/dts/upstream/Bindings/cpufreq/apple,cluster-cpufreq.yaml b/dts/upstream/Bindings/cpufreq/apple,cluster-cpufreq.yaml
index 76cb9726660..896276b8c6b 100644
--- a/dts/upstream/Bindings/cpufreq/apple,cluster-cpufreq.yaml
+++ b/dts/upstream/Bindings/cpufreq/apple,cluster-cpufreq.yaml
@@ -24,9 +24,17 @@ properties:
               - apple,t8112-cluster-cpufreq
           - const: apple,cluster-cpufreq
       - items:
-          - const: apple,t6000-cluster-cpufreq
+          - enum:
+              - apple,s8000-cluster-cpufreq
+              - apple,t8010-cluster-cpufreq
+              - apple,t8015-cluster-cpufreq
+              - apple,t6000-cluster-cpufreq
           - const: apple,t8103-cluster-cpufreq
           - const: apple,cluster-cpufreq
+      - items:
+          - const: apple,t7000-cluster-cpufreq
+          - const: apple,s5l8960x-cluster-cpufreq
+      - const: apple,s5l8960x-cluster-cpufreq
 
   reg:
     maxItems: 1
diff --git a/dts/upstream/Bindings/crypto/qcom,inline-crypto-engine.yaml b/dts/upstream/Bindings/crypto/qcom,inline-crypto-engine.yaml
index 0304f074cf0..08fe6a707a3 100644
--- a/dts/upstream/Bindings/crypto/qcom,inline-crypto-engine.yaml
+++ b/dts/upstream/Bindings/crypto/qcom,inline-crypto-engine.yaml
@@ -13,12 +13,14 @@ properties:
   compatible:
     items:
       - enum:
+          - qcom,qcs8300-inline-crypto-engine
           - qcom,sa8775p-inline-crypto-engine
           - qcom,sc7180-inline-crypto-engine
           - qcom,sc7280-inline-crypto-engine
           - qcom,sm8450-inline-crypto-engine
           - qcom,sm8550-inline-crypto-engine
           - qcom,sm8650-inline-crypto-engine
+          - qcom,sm8750-inline-crypto-engine
       - const: qcom,inline-crypto-engine
 
   reg:
diff --git a/dts/upstream/Bindings/crypto/qcom,prng.yaml b/dts/upstream/Bindings/crypto/qcom,prng.yaml
index 048b769a73c..5e6f8b64254 100644
--- a/dts/upstream/Bindings/crypto/qcom,prng.yaml
+++ b/dts/upstream/Bindings/crypto/qcom,prng.yaml
@@ -17,12 +17,17 @@ properties:
           - qcom,prng-ee  # 8996 and later using EE
       - items:
           - enum:
+              - qcom,ipq5332-trng
+              - qcom,ipq5424-trng
+              - qcom,ipq9574-trng
+              - qcom,qcs8300-trng
               - qcom,sa8255p-trng
               - qcom,sa8775p-trng
               - qcom,sc7280-trng
               - qcom,sm8450-trng
               - qcom,sm8550-trng
               - qcom,sm8650-trng
+              - qcom,sm8750-trng
           - const: qcom,trng
 
   reg:
diff --git a/dts/upstream/Bindings/crypto/qcom-qce.yaml b/dts/upstream/Bindings/crypto/qcom-qce.yaml
index c09be97434a..3ed56d9d378 100644
--- a/dts/upstream/Bindings/crypto/qcom-qce.yaml
+++ b/dts/upstream/Bindings/crypto/qcom-qce.yaml
@@ -7,7 +7,8 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
 title: Qualcomm crypto engine driver
 
 maintainers:
-  - Bhupesh Sharma <bhupesh.sharma@linaro.org>
+  - Bjorn Andersson <andersson@kernel.org>
+  - Konrad Dybcio <konradybcio@kernel.org>
 
 description:
   This document defines the binding for the QCE crypto
@@ -44,6 +45,7 @@ properties:
 
       - items:
           - enum:
+              - qcom,qcs8300-qce
               - qcom,sa8775p-qce
               - qcom,sc7280-qce
               - qcom,sm6350-qce
@@ -52,6 +54,7 @@ properties:
               - qcom,sm8450-qce
               - qcom,sm8550-qce
               - qcom,sm8650-qce
+              - qcom,sm8750-qce
           - const: qcom,sm8150-qce
           - const: qcom,qce
 
diff --git a/dts/upstream/Bindings/display/amlogic,meson-dw-hdmi.yaml b/dts/upstream/Bindings/display/amlogic,meson-dw-hdmi.yaml
index 84d68b8cfcc..416fe263ac9 100644
--- a/dts/upstream/Bindings/display/amlogic,meson-dw-hdmi.yaml
+++ b/dts/upstream/Bindings/display/amlogic,meson-dw-hdmi.yaml
@@ -148,10 +148,10 @@ examples:
 
         /* TMDS Output */
         hdmi_tx_tmds_port: port@1 {
-             reg = <1>;
+            reg = <1>;
 
-             hdmi_tx_tmds_out: endpoint {
-                 remote-endpoint = <&hdmi_connector_in>;
-             };
+            hdmi_tx_tmds_out: endpoint {
+                remote-endpoint = <&hdmi_connector_in>;
+            };
         };
     };
diff --git a/dts/upstream/Bindings/display/brcm,bcm2711-hdmi.yaml b/dts/upstream/Bindings/display/brcm,bcm2711-hdmi.yaml
index 5b35adf34c7..6d11f5955b5 100644
--- a/dts/upstream/Bindings/display/brcm,bcm2711-hdmi.yaml
+++ b/dts/upstream/Bindings/display/brcm,bcm2711-hdmi.yaml
@@ -14,6 +14,8 @@ properties:
     enum:
       - brcm,bcm2711-hdmi0
       - brcm,bcm2711-hdmi1
+      - brcm,bcm2712-hdmi0
+      - brcm,bcm2712-hdmi1
 
   reg:
     items:
diff --git a/dts/upstream/Bindings/display/brcm,bcm2835-hvs.yaml b/dts/upstream/Bindings/display/brcm,bcm2835-hvs.yaml
index 2e8566f47e6..f91c9dce2a4 100644
--- a/dts/upstream/Bindings/display/brcm,bcm2835-hvs.yaml
+++ b/dts/upstream/Bindings/display/brcm,bcm2835-hvs.yaml
@@ -13,6 +13,7 @@ properties:
   compatible:
     enum:
       - brcm,bcm2711-hvs
+      - brcm,bcm2712-hvs
       - brcm,bcm2835-hvs
 
   reg:
@@ -36,7 +37,9 @@ if:
   properties:
     compatible:
       contains:
-        const: brcm,bcm2711-hvs
+        enum:
+          - brcm,bcm2711-hvs
+          - brcm,bcm2712-hvs
 
 then:
   required:
diff --git a/dts/upstream/Bindings/display/brcm,bcm2835-pixelvalve0.yaml b/dts/upstream/Bindings/display/brcm,bcm2835-pixelvalve0.yaml
index 4e1ba03f647..6b5b1d3fbc0 100644
--- a/dts/upstream/Bindings/display/brcm,bcm2835-pixelvalve0.yaml
+++ b/dts/upstream/Bindings/display/brcm,bcm2835-pixelvalve0.yaml
@@ -20,6 +20,9 @@ properties:
       - brcm,bcm2711-pixelvalve2
       - brcm,bcm2711-pixelvalve3
       - brcm,bcm2711-pixelvalve4
+      - brcm,bcm2712-pixelvalve0
+      - brcm,bcm2712-pixelvalve1
+      - brcm,bcm2712-pixelvalve2
 
   reg:
     maxItems: 1
diff --git a/dts/upstream/Bindings/display/brcm,bcm2835-txp.yaml b/dts/upstream/Bindings/display/brcm,bcm2835-txp.yaml
index bb186197e47..16f45afd2ba 100644
--- a/dts/upstream/Bindings/display/brcm,bcm2835-txp.yaml
+++ b/dts/upstream/Bindings/display/brcm,bcm2835-txp.yaml
@@ -11,7 +11,10 @@ maintainers:
 
 properties:
   compatible:
-    const: brcm,bcm2835-txp
+    enum:
+      - brcm,bcm2712-mop
+      - brcm,bcm2712-moplet
+      - brcm,bcm2835-txp
 
   reg:
     maxItems: 1
diff --git a/dts/upstream/Bindings/display/brcm,bcm2835-vc4.yaml b/dts/upstream/Bindings/display/brcm,bcm2835-vc4.yaml
index 49a5e041aa4..2aa9d5d2aff 100644
--- a/dts/upstream/Bindings/display/brcm,bcm2835-vc4.yaml
+++ b/dts/upstream/Bindings/display/brcm,bcm2835-vc4.yaml
@@ -18,6 +18,7 @@ properties:
   compatible:
     enum:
       - brcm,bcm2711-vc5
+      - brcm,bcm2712-vc6
       - brcm,bcm2835-vc4
       - brcm,cygnus-vc4
 
diff --git a/dts/upstream/Bindings/display/bridge/fsl,imx8mp-hdmi-tx.yaml b/dts/upstream/Bindings/display/bridge/fsl,imx8mp-hdmi-tx.yaml
index 3791c9f4eba..05442d43775 100644
--- a/dts/upstream/Bindings/display/bridge/fsl,imx8mp-hdmi-tx.yaml
+++ b/dts/upstream/Bindings/display/bridge/fsl,imx8mp-hdmi-tx.yaml
@@ -82,21 +82,21 @@ examples:
         power-domains = <&hdmi_blk_ctrl IMX8MP_HDMIBLK_PD_HDMI_TX>;
         reg-io-width = <1>;
         ports {
-           #address-cells = <1>;
-           #size-cells = <0>;
-           port@0 {
-             reg = <0>;
-
-             hdmi_tx_from_pvi: endpoint {
-               remote-endpoint = <&pvi_to_hdmi_tx>;
-             };
-          };
-
-          port@1 {
-            reg = <1>;
-              hdmi_tx_out: endpoint {
-                remote-endpoint = <&hdmi0_con>;
-              };
-          };
+            #address-cells = <1>;
+            #size-cells = <0>;
+            port@0 {
+                reg = <0>;
+
+                endpoint {
+                    remote-endpoint = <&pvi_to_hdmi_tx>;
+                };
+            };
+
+            port@1 {
+                reg = <1>;
+                endpoint {
+                    remote-endpoint = <&hdmi0_con>;
+                };
+            };
         };
     };
diff --git a/dts/upstream/Bindings/display/bridge/renesas,dsi-csi2-tx.yaml b/dts/upstream/Bindings/display/bridge/renesas,dsi-csi2-tx.yaml
index d33026f85e1..c167795c63f 100644
--- a/dts/upstream/Bindings/display/bridge/renesas,dsi-csi2-tx.yaml
+++ b/dts/upstream/Bindings/display/bridge/renesas,dsi-csi2-tx.yaml
@@ -19,6 +19,7 @@ properties:
     enum:
       - renesas,r8a779a0-dsi-csi2-tx    # for V3U
       - renesas,r8a779g0-dsi-csi2-tx    # for V4H
+      - renesas,r8a779h0-dsi-csi2-tx    # for V4M
 
   reg:
     maxItems: 1
diff --git a/dts/upstream/Bindings/display/bridge/samsung,mipi-dsim.yaml b/dts/upstream/Bindings/display/bridge/samsung,mipi-dsim.yaml
index 4ed7a799ba2..1acad99f396 100644
--- a/dts/upstream/Bindings/display/bridge/samsung,mipi-dsim.yaml
+++ b/dts/upstream/Bindings/display/bridge/samsung,mipi-dsim.yaml
@@ -27,7 +27,9 @@ properties:
           - fsl,imx8mm-mipi-dsim
           - fsl,imx8mp-mipi-dsim
       - items:
-          - const: fsl,imx8mn-mipi-dsim
+          - enum:
+              - fsl,imx7d-mipi-dsim
+              - fsl,imx8mn-mipi-dsim
           - const: fsl,imx8mm-mipi-dsim
 
   reg:
@@ -241,40 +243,40 @@ examples:
     #include <dt-bindings/interrupt-controller/arm-gic.h>
 
     dsi@13900000 {
-       compatible = "samsung,exynos5433-mipi-dsi";
-       reg = <0x13900000 0xC0>;
-       interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
-       phys = <&mipi_phy 1>;
-       phy-names = "dsim";
-       clocks = <&cmu_disp CLK_PCLK_DSIM0>,
-                <&cmu_disp CLK_PHYCLK_MIPIDPHY0_BITCLKDIV8>,
-                <&cmu_disp CLK_PHYCLK_MIPIDPHY0_RXCLKESC0>,
-                <&cmu_disp CLK_SCLK_RGB_VCLK_TO_DSIM0>,
-                <&cmu_disp CLK_SCLK_DSIM0>;
-       clock-names = "bus_clk",
-                     "phyclk_mipidphy0_bitclkdiv8",
-                     "phyclk_mipidphy0_rxclkesc0",
-                     "sclk_rgb_vclk_to_dsim0",
-                     "sclk_mipi";
-       power-domains = <&pd_disp>;
-       vddcore-supply = <&ldo6_reg>;
-       vddio-supply = <&ldo7_reg>;
-       samsung,burst-clock-frequency = <512000000>;
-       samsung,esc-clock-frequency = <16000000>;
-       samsung,pll-clock-frequency = <24000000>;
-       pinctrl-names = "default";
-       pinctrl-0 = <&te_irq>;
-
-       ports {
-          #address-cells = <1>;
-          #size-cells = <0>;
-
-          port@0 {
-             reg = <0>;
-
-             dsi_to_mic: endpoint {
-                remote-endpoint = <&mic_to_dsi>;
-             };
-          };
-       };
+        compatible = "samsung,exynos5433-mipi-dsi";
+        reg = <0x13900000 0xC0>;
+        interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
+        phys = <&mipi_phy 1>;
+        phy-names = "dsim";
+        clocks = <&cmu_disp CLK_PCLK_DSIM0>,
+                 <&cmu_disp CLK_PHYCLK_MIPIDPHY0_BITCLKDIV8>,
+                 <&cmu_disp CLK_PHYCLK_MIPIDPHY0_RXCLKESC0>,
+                 <&cmu_disp CLK_SCLK_RGB_VCLK_TO_DSIM0>,
+                 <&cmu_disp CLK_SCLK_DSIM0>;
+        clock-names = "bus_clk",
+                      "phyclk_mipidphy0_bitclkdiv8",
+                      "phyclk_mipidphy0_rxclkesc0",
+                      "sclk_rgb_vclk_to_dsim0",
+                      "sclk_mipi";
+        power-domains = <&pd_disp>;
+        vddcore-supply = <&ldo6_reg>;
+        vddio-supply = <&ldo7_reg>;
+        samsung,burst-clock-frequency = <512000000>;
+        samsung,esc-clock-frequency = <16000000>;
+        samsung,pll-clock-frequency = <24000000>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&te_irq>;
+
+        ports {
+            #address-cells = <1>;
+            #size-cells = <0>;
+
+            port@0 {
+                reg = <0>;
+
+                dsi_to_mic: endpoint {
+                    remote-endpoint = <&mic_to_dsi>;
+                };
+            };
+        };
     };
diff --git a/dts/upstream/Bindings/display/bridge/ti,sn65dsi83.yaml b/dts/upstream/Bindings/display/bridge/ti,sn65dsi83.yaml
index 48a97bb3e2e..bad6f5c81b0 100644
--- a/dts/upstream/Bindings/display/bridge/ti,sn65dsi83.yaml
+++ b/dts/upstream/Bindings/display/bridge/ti,sn65dsi83.yaml
@@ -80,12 +80,12 @@ properties:
                   - const: 4
 
       port@2:
-        $ref: /schemas/graph.yaml#/properties/port
         description: Video port for LVDS Channel-A output (panel or bridge).
+        $ref: '#/$defs/lvds-port'
 
       port@3:
-        $ref: /schemas/graph.yaml#/properties/port
         description: Video port for LVDS Channel-B output (panel or bridge).
+        $ref: '#/$defs/lvds-port'
 
     required:
       - port@0
@@ -96,6 +96,36 @@ required:
   - reg
   - ports
 
+$defs:
+  lvds-port:
+    $ref: /schemas/graph.yaml#/$defs/port-base
+    unevaluatedProperties: false
+
+    properties:
+      endpoint:
+        $ref: /schemas/media/video-interfaces.yaml#
+        unevaluatedProperties: false
+
+        properties:
+          ti,lvds-termination-ohms:
+            description: The value of near end differential termination in ohms.
+            enum: [100, 200]
+            default: 200
+
+          ti,lvds-vod-swing-clock-microvolt:
+            description: LVDS diferential output voltage <min max> for clock
+              lanes in microvolts.
+            $ref: /schemas/types.yaml#/definitions/uint32-array
+            minItems: 2
+            maxItems: 2
+
+          ti,lvds-vod-swing-data-microvolt:
+            description: LVDS diferential output voltage <min max> for data
+              lanes in microvolts.
+            $ref: /schemas/types.yaml#/definitions/uint32-array
+            minItems: 2
+            maxItems: 2
+
 allOf:
   - if:
       properties:
diff --git a/dts/upstream/Bindings/display/mediatek/mediatek,aal.yaml b/dts/upstream/Bindings/display/mediatek/mediatek,aal.yaml
index 47ddba5c41a..5d2089dc596 100644
--- a/dts/upstream/Bindings/display/mediatek/mediatek,aal.yaml
+++ b/dts/upstream/Bindings/display/mediatek/mediatek,aal.yaml
@@ -104,30 +104,30 @@ examples:
         #size-cells = <2>;
 
         aal@14015000 {
-           compatible = "mediatek,mt8173-disp-aal";
-           reg = <0 0x14015000 0 0x1000>;
-           interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_LOW>;
-           power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
-           clocks = <&mmsys CLK_MM_DISP_AAL>;
-           mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x5000 0x1000>;
-
-           ports {
-               #address-cells = <1>;
-               #size-cells = <0>;
-
-               port@0 {
-                   reg = <0>;
-                   aal0_in: endpoint {
-                       remote-endpoint = <&ccorr0_out>;
-                   };
-               };
-
-               port@1 {
-                   reg = <1>;
-                   aal0_out: endpoint {
-                       remote-endpoint = <&gamma0_in>;
-                   };
-               };
-           };
-       };
+            compatible = "mediatek,mt8173-disp-aal";
+            reg = <0 0x14015000 0 0x1000>;
+            interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_LOW>;
+            power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
+            clocks = <&mmsys CLK_MM_DISP_AAL>;
+            mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x5000 0x1000>;
+
+            ports {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                port@0 {
+                    reg = <0>;
+                    endpoint {
+                        remote-endpoint = <&ccorr0_out>;
+                    };
+                };
+
+                port@1 {
+                    reg = <1>;
+                    endpoint {
+                        remote-endpoint = <&gamma0_in>;
+                    };
+                };
+            };
+        };
     };
diff --git a/dts/upstream/Bindings/display/mediatek/mediatek,ovl.yaml b/dts/upstream/Bindings/display/mediatek/mediatek,ovl.yaml
index 9ea796a033b..4f110635afb 100644
--- a/dts/upstream/Bindings/display/mediatek/mediatek,ovl.yaml
+++ b/dts/upstream/Bindings/display/mediatek/mediatek,ovl.yaml
@@ -26,6 +26,7 @@ properties:
           - mediatek,mt8173-disp-ovl
           - mediatek,mt8183-disp-ovl
           - mediatek,mt8192-disp-ovl
+          - mediatek,mt8195-disp-ovl
           - mediatek,mt8195-mdp3-ovl
       - items:
           - enum:
@@ -38,14 +39,15 @@ properties:
           - const: mediatek,mt8173-disp-ovl
       - items:
           - enum:
-              - mediatek,mt8188-disp-ovl
-              - mediatek,mt8195-disp-ovl
-          - const: mediatek,mt8183-disp-ovl
-      - items:
-          - enum:
               - mediatek,mt8186-disp-ovl
               - mediatek,mt8365-disp-ovl
           - const: mediatek,mt8192-disp-ovl
+      - items:
+          - const: mediatek,mt8188-disp-ovl
+          - const: mediatek,mt8195-disp-ovl
+      - items:
+          - const: mediatek,mt8188-mdp3-ovl
+          - const: mediatek,mt8195-mdp3-ovl
 
   reg:
     maxItems: 1
diff --git a/dts/upstream/Bindings/display/msm/dp-controller.yaml b/dts/upstream/Bindings/display/msm/dp-controller.yaml
index a212f335d5f..e00b88332f2 100644
--- a/dts/upstream/Bindings/display/msm/dp-controller.yaml
+++ b/dts/upstream/Bindings/display/msm/dp-controller.yaml
@@ -8,6 +8,7 @@ title: MSM Display Port Controller
 
 maintainers:
   - Kuogee Hsieh <quic_khsieh@quicinc.com>
+  - Abhinav Kumar <quic_abhinavk@quicinc.com>
 
 description: |
   Device tree bindings for DisplayPort host controller for MSM targets
diff --git a/dts/upstream/Bindings/display/msm/dsi-controller-main.yaml b/dts/upstream/Bindings/display/msm/dsi-controller-main.yaml
index b0fd96b76ed..ffbd1dc9470 100644
--- a/dts/upstream/Bindings/display/msm/dsi-controller-main.yaml
+++ b/dts/upstream/Bindings/display/msm/dsi-controller-main.yaml
@@ -30,6 +30,7 @@ properties:
               - qcom,sdm845-dsi-ctrl
               - qcom,sm6115-dsi-ctrl
               - qcom,sm6125-dsi-ctrl
+              - qcom,sm6150-dsi-ctrl
               - qcom,sm6350-dsi-ctrl
               - qcom,sm6375-dsi-ctrl
               - qcom,sm7150-dsi-ctrl
@@ -349,6 +350,7 @@ allOf:
             enum:
               - qcom,sc7180-dsi-ctrl
               - qcom,sc7280-dsi-ctrl
+              - qcom,sm6150-dsi-ctrl
               - qcom,sm7150-dsi-ctrl
               - qcom,sm8150-dsi-ctrl
               - qcom,sm8250-dsi-ctrl
@@ -416,63 +418,63 @@ unevaluatedProperties: false
 
 examples:
   - |
-     #include <dt-bindings/interrupt-controller/arm-gic.h>
-     #include <dt-bindings/clock/qcom,dispcc-sdm845.h>
-     #include <dt-bindings/clock/qcom,gcc-sdm845.h>
-     #include <dt-bindings/power/qcom-rpmpd.h>
-
-     dsi@ae94000 {
-           compatible = "qcom,sc7180-dsi-ctrl", "qcom,mdss-dsi-ctrl";
-           reg = <0x0ae94000 0x400>;
-           reg-names = "dsi_ctrl";
-
-           #address-cells = <1>;
-           #size-cells = <0>;
-
-           interrupt-parent = <&mdss>;
-           interrupts = <4>;
-
-           clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
-                    <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
-                    <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
-                    <&dispcc DISP_CC_MDSS_ESC0_CLK>,
-                    <&dispcc DISP_CC_MDSS_AHB_CLK>,
-                    <&dispcc DISP_CC_MDSS_AXI_CLK>;
-           clock-names = "byte",
-                         "byte_intf",
-                         "pixel",
-                         "core",
-                         "iface",
-                         "bus";
-
-           phys = <&dsi0_phy>;
-           phy-names = "dsi";
-
-           assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
-           assigned-clock-parents = <&dsi_phy 0>, <&dsi_phy 1>;
-
-           power-domains = <&rpmhpd SC7180_CX>;
-           operating-points-v2 = <&dsi_opp_table>;
-
-           ports {
-                  #address-cells = <1>;
-                  #size-cells = <0>;
-
-                  port@0 {
-                          reg = <0>;
-                          dsi0_in: endpoint {
-                                   remote-endpoint = <&dpu_intf1_out>;
-                          };
-                  };
-
-                  port@1 {
-                          reg = <1>;
-                          dsi0_out: endpoint {
-                                   remote-endpoint = <&sn65dsi86_in>;
-                                   data-lanes = <0 1 2 3>;
-                                   qcom,te-source = "mdp_vsync_e";
-                          };
-                  };
-           };
-     };
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+    #include <dt-bindings/clock/qcom,dispcc-sdm845.h>
+    #include <dt-bindings/clock/qcom,gcc-sdm845.h>
+    #include <dt-bindings/power/qcom-rpmpd.h>
+
+    dsi@ae94000 {
+        compatible = "qcom,sc7180-dsi-ctrl", "qcom,mdss-dsi-ctrl";
+        reg = <0x0ae94000 0x400>;
+        reg-names = "dsi_ctrl";
+
+        #address-cells = <1>;
+        #size-cells = <0>;
+
+        interrupt-parent = <&mdss>;
+        interrupts = <4>;
+
+        clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
+                 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
+                 <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
+                 <&dispcc DISP_CC_MDSS_ESC0_CLK>,
+                 <&dispcc DISP_CC_MDSS_AHB_CLK>,
+                 <&dispcc DISP_CC_MDSS_AXI_CLK>;
+        clock-names = "byte",
+                      "byte_intf",
+                      "pixel",
+                      "core",
+                      "iface",
+                      "bus";
+
+        phys = <&dsi0_phy>;
+        phy-names = "dsi";
+
+        assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
+        assigned-clock-parents = <&dsi_phy 0>, <&dsi_phy 1>;
+
+        power-domains = <&rpmhpd SC7180_CX>;
+        operating-points-v2 = <&dsi_opp_table>;
+
+        ports {
+            #address-cells = <1>;
+            #size-cells = <0>;
+
+            port@0 {
+                reg = <0>;
+                endpoint {
+                    remote-endpoint = <&dpu_intf1_out>;
+                };
+            };
+
+            port@1 {
+                reg = <1>;
+                endpoint {
+                    remote-endpoint = <&sn65dsi86_in>;
+                    data-lanes = <0 1 2 3>;
+                    qcom,te-source = "mdp_vsync_e";
+                };
+            };
+        };
+    };
 ...
diff --git a/dts/upstream/Bindings/display/msm/dsi-phy-10nm.yaml b/dts/upstream/Bindings/display/msm/dsi-phy-10nm.yaml
index 69d13867b7c..fc9abf090f0 100644
--- a/dts/upstream/Bindings/display/msm/dsi-phy-10nm.yaml
+++ b/dts/upstream/Bindings/display/msm/dsi-phy-10nm.yaml
@@ -74,28 +74,28 @@ unevaluatedProperties: false
 
 examples:
   - |
-     #include <dt-bindings/clock/qcom,dispcc-sdm845.h>
-     #include <dt-bindings/clock/qcom,rpmh.h>
-
-     dsi-phy@ae94400 {
-         compatible = "qcom,dsi-phy-10nm";
-         reg = <0x0ae94400 0x200>,
-               <0x0ae94600 0x280>,
-               <0x0ae94a00 0x1e0>;
-         reg-names = "dsi_phy",
-                     "dsi_phy_lane",
-                     "dsi_pll";
-
-         #clock-cells = <1>;
-         #phy-cells = <0>;
-
-         vdds-supply = <&vdda_mipi_dsi0_pll>;
-         clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
-                  <&rpmhcc RPMH_CXO_CLK>;
-         clock-names = "iface", "ref";
-
-         qcom,phy-rescode-offset-top = /bits/ 8 <0 0 0 0 0>;
-         qcom,phy-rescode-offset-bot = /bits/ 8 <0 0 0 0 0>;
-         qcom,phy-drive-ldo-level = <400>;
-     };
+    #include <dt-bindings/clock/qcom,dispcc-sdm845.h>
+    #include <dt-bindings/clock/qcom,rpmh.h>
+
+    dsi-phy@ae94400 {
+        compatible = "qcom,dsi-phy-10nm";
+        reg = <0x0ae94400 0x200>,
+              <0x0ae94600 0x280>,
+              <0x0ae94a00 0x1e0>;
+        reg-names = "dsi_phy",
+                    "dsi_phy_lane",
+                    "dsi_pll";
+
+        #clock-cells = <1>;
+        #phy-cells = <0>;
+
+        vdds-supply = <&vdda_mipi_dsi0_pll>;
+        clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
+                 <&rpmhcc RPMH_CXO_CLK>;
+        clock-names = "iface", "ref";
+
+        qcom,phy-rescode-offset-top = /bits/ 8 <0 0 0 0 0>;
+        qcom,phy-rescode-offset-bot = /bits/ 8 <0 0 0 0 0>;
+        qcom,phy-drive-ldo-level = <400>;
+    };
 ...
diff --git a/dts/upstream/Bindings/display/msm/dsi-phy-14nm.yaml b/dts/upstream/Bindings/display/msm/dsi-phy-14nm.yaml
index 52bbe132e6d..206a9a4b384 100644
--- a/dts/upstream/Bindings/display/msm/dsi-phy-14nm.yaml
+++ b/dts/upstream/Bindings/display/msm/dsi-phy-14nm.yaml
@@ -20,6 +20,7 @@ properties:
       - qcom,dsi-phy-14nm-660
       - qcom,dsi-phy-14nm-8953
       - qcom,sm6125-dsi-phy-14nm
+      - qcom,sm6150-dsi-phy-14nm
 
   reg:
     items:
@@ -55,24 +56,24 @@ unevaluatedProperties: false
 
 examples:
   - |
-     #include <dt-bindings/clock/qcom,dispcc-sdm845.h>
-     #include <dt-bindings/clock/qcom,rpmh.h>
+    #include <dt-bindings/clock/qcom,dispcc-sdm845.h>
+    #include <dt-bindings/clock/qcom,rpmh.h>
 
-     dsi-phy@ae94400 {
-         compatible = "qcom,dsi-phy-14nm";
-         reg = <0x0ae94400 0x200>,
-               <0x0ae94600 0x280>,
-               <0x0ae94a00 0x1e0>;
-         reg-names = "dsi_phy",
-                     "dsi_phy_lane",
-                     "dsi_pll";
+    dsi-phy@ae94400 {
+        compatible = "qcom,dsi-phy-14nm";
+        reg = <0x0ae94400 0x200>,
+              <0x0ae94600 0x280>,
+              <0x0ae94a00 0x1e0>;
+        reg-names = "dsi_phy",
+                    "dsi_phy_lane",
+                    "dsi_pll";
 
-         #clock-cells = <1>;
-         #phy-cells = <0>;
+        #clock-cells = <1>;
+        #phy-cells = <0>;
 
-         vcca-supply = <&vcca_reg>;
-         clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
-                  <&rpmhcc RPMH_CXO_CLK>;
-         clock-names = "iface", "ref";
-     };
+        vcca-supply = <&vcca_reg>;
+        clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
+                 <&rpmhcc RPMH_CXO_CLK>;
+        clock-names = "iface", "ref";
+    };
 ...
diff --git a/dts/upstream/Bindings/display/msm/dsi-phy-20nm.yaml b/dts/upstream/Bindings/display/msm/dsi-phy-20nm.yaml
index 7e6687cb002..93570052992 100644
--- a/dts/upstream/Bindings/display/msm/dsi-phy-20nm.yaml
+++ b/dts/upstream/Bindings/display/msm/dsi-phy-20nm.yaml
@@ -45,26 +45,26 @@ unevaluatedProperties: false
 
 examples:
   - |
-     #include <dt-bindings/clock/qcom,dispcc-sdm845.h>
-     #include <dt-bindings/clock/qcom,rpmh.h>
+    #include <dt-bindings/clock/qcom,dispcc-sdm845.h>
+    #include <dt-bindings/clock/qcom,rpmh.h>
 
-     dsi-phy@fd922a00 {
-         compatible = "qcom,dsi-phy-20nm";
-         reg = <0xfd922a00 0xd4>,
-               <0xfd922b00 0x2b0>,
-               <0xfd922d80 0x7b>;
-         reg-names = "dsi_pll",
-                     "dsi_phy",
-                     "dsi_phy_regulator";
+    dsi-phy@fd922a00 {
+        compatible = "qcom,dsi-phy-20nm";
+        reg = <0xfd922a00 0xd4>,
+              <0xfd922b00 0x2b0>,
+              <0xfd922d80 0x7b>;
+        reg-names = "dsi_pll",
+                    "dsi_phy",
+                    "dsi_phy_regulator";
 
-         #clock-cells = <1>;
-         #phy-cells = <0>;
+        #clock-cells = <1>;
+        #phy-cells = <0>;
 
-         vcca-supply = <&vcca_reg>;
-         vddio-supply = <&vddio_reg>;
+        vcca-supply = <&vcca_reg>;
+        vddio-supply = <&vddio_reg>;
 
-         clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
-                  <&rpmhcc RPMH_CXO_CLK>;
-         clock-names = "iface", "ref";
-     };
+        clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
+                 <&rpmhcc RPMH_CXO_CLK>;
+        clock-names = "iface", "ref";
+    };
 ...
diff --git a/dts/upstream/Bindings/display/msm/dsi-phy-28nm.yaml b/dts/upstream/Bindings/display/msm/dsi-phy-28nm.yaml
index a55c2445d18..371befa9f9d 100644
--- a/dts/upstream/Bindings/display/msm/dsi-phy-28nm.yaml
+++ b/dts/upstream/Bindings/display/msm/dsi-phy-28nm.yaml
@@ -51,25 +51,25 @@ unevaluatedProperties: false
 
 examples:
   - |
-     #include <dt-bindings/clock/qcom,dispcc-sdm845.h>
-     #include <dt-bindings/clock/qcom,rpmh.h>
+    #include <dt-bindings/clock/qcom,dispcc-sdm845.h>
+    #include <dt-bindings/clock/qcom,rpmh.h>
 
-     dsi-phy@fd922a00 {
-         compatible = "qcom,dsi-phy-28nm-lp";
-         reg = <0xfd922a00 0xd4>,
-               <0xfd922b00 0x2b0>,
-               <0xfd922d80 0x7b>;
-         reg-names = "dsi_pll",
-                     "dsi_phy",
-                     "dsi_phy_regulator";
+    dsi-phy@fd922a00 {
+        compatible = "qcom,dsi-phy-28nm-lp";
+        reg = <0xfd922a00 0xd4>,
+              <0xfd922b00 0x2b0>,
+              <0xfd922d80 0x7b>;
+        reg-names = "dsi_pll",
+                    "dsi_phy",
+                    "dsi_phy_regulator";
 
-         #clock-cells = <1>;
-         #phy-cells = <0>;
+        #clock-cells = <1>;
+        #phy-cells = <0>;
 
-         vddio-supply = <&vddio_reg>;
+        vddio-supply = <&vddio_reg>;
 
-         clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
-                  <&rpmhcc RPMH_CXO_CLK>;
-         clock-names = "iface", "ref";
-     };
+        clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
+                 <&rpmhcc RPMH_CXO_CLK>;
+        clock-names = "iface", "ref";
+    };
 ...
diff --git a/dts/upstream/Bindings/display/msm/dsi-phy-7nm.yaml b/dts/upstream/Bindings/display/msm/dsi-phy-7nm.yaml
index 7e764eac3ef..321470435e6 100644
--- a/dts/upstream/Bindings/display/msm/dsi-phy-7nm.yaml
+++ b/dts/upstream/Bindings/display/msm/dsi-phy-7nm.yaml
@@ -54,23 +54,23 @@ unevaluatedProperties: false
 
 examples:
   - |
-     #include <dt-bindings/clock/qcom,dispcc-sm8250.h>
-     #include <dt-bindings/clock/qcom,rpmh.h>
+    #include <dt-bindings/clock/qcom,dispcc-sm8250.h>
+    #include <dt-bindings/clock/qcom,rpmh.h>
 
-     dsi-phy@ae94400 {
-         compatible = "qcom,dsi-phy-7nm";
-         reg = <0x0ae94400 0x200>,
-               <0x0ae94600 0x280>,
-               <0x0ae94900 0x260>;
-         reg-names = "dsi_phy",
-                     "dsi_phy_lane",
-                     "dsi_pll";
+    dsi-phy@ae94400 {
+        compatible = "qcom,dsi-phy-7nm";
+        reg = <0x0ae94400 0x200>,
+              <0x0ae94600 0x280>,
+              <0x0ae94900 0x260>;
+        reg-names = "dsi_phy",
+                    "dsi_phy_lane",
+                    "dsi_pll";
 
-         #clock-cells = <1>;
-         #phy-cells = <0>;
+        #clock-cells = <1>;
+        #phy-cells = <0>;
 
-         vdds-supply = <&vreg_l5a_0p88>;
-         clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
-                  <&rpmhcc RPMH_CXO_CLK>;
-         clock-names = "iface", "ref";
-     };
+        vdds-supply = <&vreg_l5a_0p88>;
+        clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
+                 <&rpmhcc RPMH_CXO_CLK>;
+        clock-names = "iface", "ref";
+    };
diff --git a/dts/upstream/Bindings/display/msm/qcom,sa8775p-mdss.yaml b/dts/upstream/Bindings/display/msm/qcom,sa8775p-mdss.yaml
index 58f8a01f29c..a90a8b3f1a9 100644
--- a/dts/upstream/Bindings/display/msm/qcom,sa8775p-mdss.yaml
+++ b/dts/upstream/Bindings/display/msm/qcom,sa8775p-mdss.yaml
@@ -78,7 +78,6 @@ examples:
                              "mdp1-mem",
                              "cpu-cfg";
 
-
         resets = <&dispcc_core_bcr>;
         power-domains = <&dispcc_gdsc>;
 
@@ -129,7 +128,7 @@ examples:
                 port@0 {
                     reg = <0>;
                     dpu_intf0_out: endpoint {
-                         remote-endpoint = <&mdss0_dp0_in>;
+                        remote-endpoint = <&mdss0_dp0_in>;
                     };
                 };
             };
@@ -168,7 +167,8 @@ examples:
             reg = <0xaf54000 0x104>,
                   <0xaf54200 0x0c0>,
                   <0xaf55000 0x770>,
-                  <0xaf56000 0x09c>;
+                  <0xaf56000 0x09c>,
+                  <0xaf57000 0x09c>;
 
             interrupt-parent = <&mdss0>;
             interrupts = <12>;
@@ -208,8 +208,8 @@ examples:
                 };
 
                 port@1 {
-                   reg = <1>;
-                   mdss0_dp_out: endpoint { };
+                    reg = <1>;
+                    mdss0_dp_out: endpoint { };
                 };
             };
 
diff --git a/dts/upstream/Bindings/display/msm/qcom,sm6150-dpu.yaml b/dts/upstream/Bindings/display/msm/qcom,sm6150-dpu.yaml
new file mode 100644
index 00000000000..b4f43717221
--- /dev/null
+++ b/dts/upstream/Bindings/display/msm/qcom,sm6150-dpu.yaml
@@ -0,0 +1,108 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/msm/qcom,sm6150-dpu.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm SM6150 Display DPU
+
+maintainers:
+  - Abhinav Kumar <quic_abhinavk@quicinc.com>
+  - Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
+
+$ref: /schemas/display/msm/dpu-common.yaml#
+
+properties:
+  compatible:
+    const: qcom,sm6150-dpu
+
+  reg:
+    items:
+      - description: Address offset and size for mdp register set
+      - description: Address offset and size for vbif register set
+
+  reg-names:
+    items:
+      - const: mdp
+      - const: vbif
+
+  clocks:
+    items:
+      - description: Display ahb clock
+      - description: Display hf axi clock
+      - description: Display core clock
+      - description: Display vsync clock
+
+  clock-names:
+    items:
+      - const: iface
+      - const: bus
+      - const: core
+      - const: vsync
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+    #include <dt-bindings/power/qcom,rpmhpd.h>
+
+    display-controller@ae01000 {
+        compatible = "qcom,sm6150-dpu";
+        reg = <0x0ae01000 0x8f000>,
+              <0x0aeb0000 0x2008>;
+        reg-names = "mdp", "vbif";
+
+        clocks = <&dispcc_mdss_ahb_clk>,
+                 <&gcc_disp_hf_axi_clk>,
+                 <&dispcc_mdss_mdp_clk>,
+                 <&dispcc_mdss_vsync_clk>;
+        clock-names = "iface", "bus", "core", "vsync";
+
+        assigned-clocks = <&dispcc_mdss_vsync_clk>;
+        assigned-clock-rates = <19200000>;
+
+        operating-points-v2 = <&mdp_opp_table>;
+        power-domains = <&rpmhpd RPMHPD_CX>;
+
+        interrupt-parent = <&mdss>;
+        interrupts = <0>;
+
+        ports {
+            #address-cells = <1>;
+            #size-cells = <0>;
+
+            port@0 {
+                reg = <0>;
+                dpu_intf0_out: endpoint {
+                };
+            };
+
+            port@1 {
+                reg = <1>;
+                dpu_intf1_out: endpoint {
+                  remote-endpoint = <&mdss_dsi0_in>;
+                };
+            };
+        };
+
+        mdp_opp_table: opp-table {
+            compatible = "operating-points-v2";
+
+            opp-19200000 {
+              opp-hz = /bits/ 64 <19200000>;
+              required-opps = <&rpmhpd_opp_low_svs>;
+            };
+
+            opp-25600000 {
+              opp-hz = /bits/ 64 <25600000>;
+              required-opps = <&rpmhpd_opp_svs>;
+            };
+
+            opp-307200000 {
+              opp-hz = /bits/ 64 <307200000>;
+              required-opps = <&rpmhpd_opp_nom>;
+            };
+        };
+    };
+...
diff --git a/dts/upstream/Bindings/display/msm/qcom,sm6150-mdss.yaml b/dts/upstream/Bindings/display/msm/qcom,sm6150-mdss.yaml
new file mode 100644
index 00000000000..9ac24f99d3a
--- /dev/null
+++ b/dts/upstream/Bindings/display/msm/qcom,sm6150-mdss.yaml
@@ -0,0 +1,245 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/msm/qcom,sm6150-mdss.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm SM6150 Display MDSS
+
+maintainers:
+  - Abhinav Kumar <quic_abhinavk@quicinc.com>
+  - Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
+
+description:
+  Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates
+  sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree
+  bindings of MDSS are mentioned for SM6150 target.
+
+$ref: /schemas/display/msm/mdss-common.yaml#
+
+properties:
+  compatible:
+    items:
+      - const: qcom,sm6150-mdss
+
+  clocks:
+    items:
+      - description: Display AHB clock from gcc
+      - description: Display hf axi clock
+      - description: Display core clock
+
+  clock-names:
+    items:
+      - const: iface
+      - const: bus
+      - const: core
+
+  iommus:
+    maxItems: 1
+
+  interconnects:
+    maxItems: 2
+
+  interconnect-names:
+    maxItems: 2
+
+patternProperties:
+  "^display-controller@[0-9a-f]+$":
+    type: object
+    additionalProperties: true
+    properties:
+      compatible:
+        const: qcom,sm6150-dpu
+
+  "^dsi@[0-9a-f]+$":
+    type: object
+    additionalProperties: true
+    properties:
+      compatible:
+        items:
+          - const: qcom,sm6150-dsi-ctrl
+          - const: qcom,mdss-dsi-ctrl
+
+  "^phy@[0-9a-f]+$":
+    type: object
+    additionalProperties: true
+    properties:
+      compatible:
+        const: qcom,sm6150-dsi-phy-14nm
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/qcom,rpmh.h>
+    #include <dt-bindings/interconnect/qcom,icc.h>
+    #include <dt-bindings/interconnect/qcom,qcs615-rpmh.h>
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+    #include <dt-bindings/power/qcom,rpmhpd.h>
+
+    display-subsystem@ae00000 {
+        #address-cells = <1>;
+        #size-cells = <1>;
+        compatible = "qcom,sm6150-mdss";
+        reg = <0x0ae00000 0x1000>;
+        reg-names = "mdss";
+
+        interconnects = <&mmss_noc MASTER_MDP0 QCOM_ICC_TAG_ALWAYS
+                         &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
+                        <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+                         &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>;
+        interconnect-names = "mdp0-mem", "cpu-cfg";
+
+        power-domains = <&dispcc_mdss_gdsc>;
+
+        clocks = <&dispcc_mdss_ahb_clk>,
+                 <&gcc_disp_hf_axi_clk>,
+                 <&dispcc_mdss_mdp_clk>;
+
+        interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
+        interrupt-controller;
+        #interrupt-cells = <1>;
+
+        iommus = <&apps_smmu 0x800 0x0>;
+
+        ranges;
+
+        display-controller@ae01000 {
+            compatible = "qcom,sm6150-dpu";
+            reg = <0x0ae01000 0x8f000>,
+                  <0x0aeb0000 0x2008>;
+            reg-names = "mdp", "vbif";
+
+            clocks = <&dispcc_mdss_ahb_clk>,
+                     <&gcc_disp_hf_axi_clk>,
+                     <&dispcc_mdss_mdp_clk>,
+                     <&dispcc_mdss_vsync_clk>;
+            clock-names = "iface", "bus", "core", "vsync";
+
+            assigned-clocks = <&dispcc_mdss_vsync_clk>;
+            assigned-clock-rates = <19200000>;
+
+            operating-points-v2 = <&mdp_opp_table>;
+            power-domains = <&rpmhpd RPMHPD_CX>;
+
+            interrupt-parent = <&mdss>;
+            interrupts = <0>;
+
+            ports {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                port@0 {
+                  reg = <0>;
+                  dpu_intf0_out: endpoint {
+                  };
+                };
+
+                port@1 {
+                  reg = <1>;
+                  dpu_intf1_out: endpoint {
+                      remote-endpoint = <&mdss_dsi0_in>;
+                  };
+                };
+            };
+
+            mdp_opp_table: opp-table {
+                compatible = "operating-points-v2";
+
+                opp-19200000 {
+                  opp-hz = /bits/ 64 <19200000>;
+                  required-opps = <&rpmhpd_opp_low_svs>;
+                };
+
+                opp-25600000 {
+                  opp-hz = /bits/ 64 <25600000>;
+                  required-opps = <&rpmhpd_opp_svs>;
+                };
+
+                opp-307200000 {
+                  opp-hz = /bits/ 64 <307200000>;
+                  required-opps = <&rpmhpd_opp_nom>;
+                };
+            };
+        };
+
+        dsi@ae94000 {
+            compatible = "qcom,sm6150-dsi-ctrl",
+                         "qcom,mdss-dsi-ctrl";
+            reg = <0x0ae94000 0x400>;
+            reg-names = "dsi_ctrl";
+
+            interrupt-parent = <&mdss>;
+            interrupts = <4>;
+
+            clocks = <&dispcc_mdss_byte0_clk>,
+                     <&dispcc_mdss_byte0_intf_clk>,
+                     <&dispcc_mdss_pclk0_clk>,
+                     <&dispcc_mdss_esc0_clk>,
+                     <&dispcc_mdss_ahb_clk>,
+                     <&gcc_disp_hf_axi_clk>;
+            clock-names = "byte",
+                          "byte_intf",
+                          "pixel",
+                          "core",
+                          "iface",
+                          "bus";
+
+            assigned-clocks = <&dispcc_mdss_byte0_clk_src>,
+                              <&dispcc_mdss_pclk0_clk_src>;
+            assigned-clock-parents = <&mdss_dsi0_phy 0>,
+                                     <&mdss_dsi0_phy 1>;
+
+            operating-points-v2 = <&dsi0_opp_table>;
+
+            phys = <&mdss_dsi0_phy>;
+
+            #address-cells = <1>;
+            #size-cells = <0>;
+
+            ports {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                port@0 {
+                    reg = <0>;
+                    mdss_dsi0_in: endpoint {
+                        remote-endpoint = <&dpu_intf1_out>;
+                    };
+                };
+
+                port@1 {
+                    reg = <1>;
+                    mdss_dsi0_out: endpoint {
+                    };
+                };
+            };
+
+            dsi0_opp_table: opp-table {
+                compatible = "operating-points-v2";
+
+                opp-164000000 {
+                    opp-hz = /bits/ 64 <164000000>;
+                    required-opps = <&rpmhpd_opp_low_svs>;
+                };
+            };
+        };
+
+        mdss_dsi0_phy: phy@ae94400 {
+            compatible = "qcom,sm6150-dsi-phy-14nm";
+            reg = <0x0ae94400 0x100>,
+                  <0x0ae94500 0x300>,
+                  <0x0ae94800 0x188>;
+            reg-names = "dsi_phy",
+                        "dsi_phy_lane",
+                        "dsi_pll";
+
+            #clock-cells = <1>;
+            #phy-cells = <0>;
+
+            clocks = <&dispcc_mdss_ahb_clk>,
+                     <&rpmhcc RPMH_CXO_CLK>;
+            clock-names = "iface", "ref";
+        };
+    };
+...
diff --git a/dts/upstream/Bindings/display/panel/panel-lvds.yaml b/dts/upstream/Bindings/display/panel/panel-lvds.yaml
index 5af2d693007..fcb5834f799 100644
--- a/dts/upstream/Bindings/display/panel/panel-lvds.yaml
+++ b/dts/upstream/Bindings/display/panel/panel-lvds.yaml
@@ -42,6 +42,8 @@ properties:
           # Admatec 9904379 10.1" 1024x600 LVDS panel
           - admatec,9904379
           - auo,b101ew05
+          # AUO G084SN05 V9 8.4" 800x600 LVDS panel
+          - auo,g084sn05
           # Chunghwa Picture Tubes Ltd. 7" WXGA (800x1280) TFT LCD LVDS panel
           - chunghwa,claa070wp03xg
           # EDT ETML0700Z9NDHA 7.0" WSVGA (1024x600) color TFT LCD LVDS panel
diff --git a/dts/upstream/Bindings/display/panel/panel-simple.yaml b/dts/upstream/Bindings/display/panel/panel-simple.yaml
index 18b63f356bb..e3ee3a332bb 100644
--- a/dts/upstream/Bindings/display/panel/panel-simple.yaml
+++ b/dts/upstream/Bindings/display/panel/panel-simple.yaml
@@ -206,12 +206,16 @@ properties:
       - mitsubishi,aa070mc01-ca1
         # Mitsubishi AA084XE01 8.4" XGA TFT LCD panel
       - mitsubishi,aa084xe01
+        # Multi-Inno Technology Co.,Ltd MI0700A2T-30 7" 800x480 TFT Resistive Touch Module
+      - multi-inno,mi0700a2t-30
         # Multi-Inno Technology Co.,Ltd MI0700S4T-6 7" 800x480 TFT Resistive Touch Module
       - multi-inno,mi0700s4t-6
         # Multi-Inno Technology Co.,Ltd MI0800FT-9 8" 800x600 TFT Resistive Touch Module
       - multi-inno,mi0800ft-9
         # Multi-Inno Technology Co.,Ltd MI1010AIT-1CP 10.1" 1280x800 LVDS IPS Cap Touch Mod.
       - multi-inno,mi1010ait-1cp
+        # Multi-Inno Technology Co.,Ltd MI1010Z1T-1CP11 10.1" 1024x600 TFT Resistive Touch Module
+      - multi-inno,mi1010z1t-1cp11
         # NEC LCD Technologies, Ltd. 12.1" WXGA (1280x800) LVDS TFT LCD panel
       - nec,nl12880bc20-05
         # NEC LCD Technologies,Ltd. WQVGA TFT LCD panel
@@ -280,10 +284,14 @@ properties:
       - team-source-display,tst043015cmhx
         # Tianma Micro-electronics TM070JDHG30 7.0" WXGA TFT LCD panel
       - tianma,tm070jdhg30
+        # Tianma Micro-electronics TM070JDHG34-00 7.0" WXGA (1280x800) LVDS TFT LCD panel
+      - tianma,tm070jdhg34-00
         # Tianma Micro-electronics TM070JVHG33 7.0" WXGA TFT LCD panel
       - tianma,tm070jvhg33
         # Tianma Micro-electronics TM070RVHG71 7.0" WXGA TFT LCD panel
       - tianma,tm070rvhg71
+        # Topland TIAN-G07017-01 7.0" WSVGA TFT-LCD panel with capacitive touch
+      - topland,tian-g07017-01
         # Toshiba 8.9" WXGA (1280x768) TFT LCD panel
       - toshiba,lt089ac29000
         # TPK U.S.A. LLC Fusion 7" 800 x 480 (WVGA) LCD panel with capacitive touch
diff --git a/dts/upstream/Bindings/display/panel/powertip,hx8238a.yaml b/dts/upstream/Bindings/display/panel/powertip,hx8238a.yaml
new file mode 100644
index 00000000000..b7d74faeb5d
--- /dev/null
+++ b/dts/upstream/Bindings/display/panel/powertip,hx8238a.yaml
@@ -0,0 +1,29 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/panel/powertip,hx8238a.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Powertip Electronic Technology Co. 320 x 240 LCD panel
+
+maintainers:
+  - Lukasz Majewski <lukma@denx.de>
+
+allOf:
+  - $ref: panel-dpi.yaml#
+
+properties:
+  compatible:
+    items:
+      - const: powertip,hx8238a
+      - {} # panel-dpi, but not listed here to avoid false select
+
+  height-mm: true
+  panel-timing: true
+  port: true
+  power-supply: true
+  width-mm: true
+
+additionalProperties: false
+
+...
diff --git a/dts/upstream/Bindings/display/panel/powertip,st7272.yaml b/dts/upstream/Bindings/display/panel/powertip,st7272.yaml
new file mode 100644
index 00000000000..f3622800f13
--- /dev/null
+++ b/dts/upstream/Bindings/display/panel/powertip,st7272.yaml
@@ -0,0 +1,29 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/panel/powertip,st7272.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Powertip Electronic Technology Co. 320 x 240 LCD panel
+
+maintainers:
+  - Lukasz Majewski <lukma@denx.de>
+
+allOf:
+  - $ref: panel-dpi.yaml#
+
+properties:
+  compatible:
+    items:
+      - const: powertip,st7272
+      - {} # panel-dpi, but not listed here to avoid false select
+
+  height-mm: true
+  panel-timing: true
+  port: true
+  power-supply: true
+  width-mm: true
+
+additionalProperties: false
+
+...
diff --git a/dts/upstream/Bindings/display/panel/samsung,atna33xc20.yaml b/dts/upstream/Bindings/display/panel/samsung,atna33xc20.yaml
index 032f783eefc..684c2896d23 100644
--- a/dts/upstream/Bindings/display/panel/samsung,atna33xc20.yaml
+++ b/dts/upstream/Bindings/display/panel/samsung,atna33xc20.yaml
@@ -23,6 +23,8 @@ properties:
               - samsung,atna45af01
               # Samsung 14.5" 3K (2944x1840 pixels) eDP AMOLED panel
               - samsung,atna45dc02
+              # Samsung 15.6" 3K (2880x1620 pixels) eDP AMOLED panel
+              - samsung,atna56ac03
           - const: samsung,atna33xc20
 
   enable-gpios: true
diff --git a/dts/upstream/Bindings/display/renesas,cmm.yaml b/dts/upstream/Bindings/display/renesas,cmm.yaml
index 561efaaa5a9..fc4933c343c 100644
--- a/dts/upstream/Bindings/display/renesas,cmm.yaml
+++ b/dts/upstream/Bindings/display/renesas,cmm.yaml
@@ -58,10 +58,10 @@ examples:
     #include <dt-bindings/power/r8a7796-sysc.h>
 
     cmm0: cmm@fea40000 {
-         compatible = "renesas,r8a7796-cmm",
-                      "renesas,rcar-gen3-cmm";
-         reg = <0xfea40000 0x1000>;
-         power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
-         clocks = <&cpg CPG_MOD 711>;
-         resets = <&cpg 711>;
+        compatible = "renesas,r8a7796-cmm",
+                     "renesas,rcar-gen3-cmm";
+        reg = <0xfea40000 0x1000>;
+        power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
+        clocks = <&cpg CPG_MOD 711>;
+        resets = <&cpg 711>;
     };
diff --git a/dts/upstream/Bindings/display/renesas,du.yaml b/dts/upstream/Bindings/display/renesas,du.yaml
index c5b9e6812bc..3880b4c2ea9 100644
--- a/dts/upstream/Bindings/display/renesas,du.yaml
+++ b/dts/upstream/Bindings/display/renesas,du.yaml
@@ -41,6 +41,7 @@ properties:
       - renesas,du-r8a77995 # for R-Car D3 compatible DU
       - renesas,du-r8a779a0 # for R-Car V3U compatible DU
       - renesas,du-r8a779g0 # for R-Car V4H compatible DU
+      - renesas,du-r8a779h0 # for R-Car V4M compatible DU
 
   reg:
     maxItems: 1
@@ -69,14 +70,12 @@ properties:
         $ref: /schemas/graph.yaml#/properties/port
         unevaluatedProperties: false
 
-    required:
-      - port@0
-      - port@1
-
     unevaluatedProperties: false
 
   renesas,cmms:
     $ref: /schemas/types.yaml#/definitions/phandle-array
+    minItems: 1
+    maxItems: 4
     items:
       maxItems: 1
     description:
@@ -85,6 +84,8 @@ properties:
 
   renesas,vsps:
     $ref: /schemas/types.yaml#/definitions/phandle-array
+    minItems: 1
+    maxItems: 4
     items:
       items:
         - description: phandle to VSP instance that serves the DU channel
@@ -489,9 +490,11 @@ allOf:
 
         renesas,cmms:
           minItems: 4
+          maxItems: 4
 
         renesas,vsps:
           minItems: 4
+          maxItems: 4
 
       required:
         - clock-names
@@ -558,9 +561,11 @@ allOf:
 
         renesas,cmms:
           minItems: 3
+          maxItems: 3
 
         renesas,vsps:
           minItems: 3
+          maxItems: 3
 
       required:
         - clock-names
@@ -627,9 +632,11 @@ allOf:
 
         renesas,cmms:
           minItems: 3
+          maxItems: 3
 
         renesas,vsps:
           minItems: 3
+          maxItems: 3
 
       required:
         - clock-names
@@ -683,7 +690,7 @@ allOf:
             - port@1
 
         renesas,vsps:
-          minItems: 1
+          maxItems: 1
 
       required:
         - clock-names
@@ -746,9 +753,11 @@ allOf:
 
         renesas,cmms:
           minItems: 2
+          maxItems: 2
 
         renesas,vsps:
           minItems: 2
+          maxItems: 2
 
       required:
         - clock-names
@@ -799,6 +808,54 @@ allOf:
 
         renesas,vsps:
           minItems: 2
+          maxItems: 2
+
+      required:
+        - clock-names
+        - interrupts
+        - resets
+        - reset-names
+        - renesas,vsps
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - renesas,du-r8a779h0
+    then:
+      properties:
+        clocks:
+          items:
+            - description: Functional clock
+
+        clock-names:
+          items:
+            - const: du.0
+
+        interrupts:
+          maxItems: 1
+
+        resets:
+          maxItems: 1
+
+        reset-names:
+          items:
+            - const: du.0
+
+        ports:
+          properties:
+            port@0:
+              description: DSI 0
+            port@1: false
+            port@2: false
+            port@3: false
+
+          required:
+            - port@0
+
+        renesas,vsps:
+          maxItems: 1
 
       required:
         - clock-names
diff --git a/dts/upstream/Bindings/display/rockchip/rockchip,rk3588-mipi-dsi2.yaml b/dts/upstream/Bindings/display/rockchip/rockchip,rk3588-mipi-dsi2.yaml
new file mode 100644
index 00000000000..53384e47b50
--- /dev/null
+++ b/dts/upstream/Bindings/display/rockchip/rockchip,rk3588-mipi-dsi2.yaml
@@ -0,0 +1,120 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/rockchip/rockchip,rk3588-mipi-dsi2.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Rockchip specific extensions to the Synopsys Designware MIPI DSI2
+
+maintainers:
+  - Heiko Stuebner <heiko@sntech.de>
+
+properties:
+  compatible:
+    enum:
+      - rockchip,rk3588-mipi-dsi2
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+
+  clocks:
+    maxItems: 2
+
+  clock-names:
+    items:
+      - const: pclk
+      - const: sys
+
+  rockchip,grf:
+    $ref: /schemas/types.yaml#/definitions/phandle
+    description:
+      This SoC uses GRF regs to switch between vopl/vopb.
+
+  phys:
+    maxItems: 1
+
+  phy-names:
+    const: dcphy
+
+  power-domains:
+    maxItems: 1
+
+  resets:
+    maxItems: 1
+
+  reset-names:
+    const: apb
+
+  ports:
+    $ref: /schemas/graph.yaml#/properties/ports
+
+    properties:
+      port@0:
+        $ref: /schemas/graph.yaml#/properties/port
+        description: Input node to receive pixel data.
+
+      port@1:
+        $ref: /schemas/graph.yaml#/properties/port
+        description: DSI output node to panel.
+
+    required:
+      - port@0
+      - port@1
+
+required:
+  - compatible
+  - clocks
+  - clock-names
+  - rockchip,grf
+  - phys
+  - phy-names
+  - ports
+  - reg
+
+allOf:
+  - $ref: /schemas/display/dsi-controller.yaml#
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/rockchip,rk3588-cru.h>
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+    #include <dt-bindings/interrupt-controller/irq.h>
+    #include <dt-bindings/phy/phy.h>
+    #include <dt-bindings/power/rk3588-power.h>
+    #include <dt-bindings/reset/rockchip,rk3588-cru.h>
+
+    soc {
+      #address-cells = <2>;
+      #size-cells = <2>;
+
+      dsi@fde20000 {
+        compatible = "rockchip,rk3588-mipi-dsi2";
+        reg = <0x0 0xfde20000 0x0 0x10000>;
+        interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH 0>;
+        clocks = <&cru PCLK_DSIHOST0>, <&cru CLK_DSIHOST0>;
+        clock-names = "pclk", "sys";
+        resets = <&cru SRST_P_DSIHOST0>;
+        reset-names = "apb";
+        power-domains = <&power RK3588_PD_VOP>;
+        phys = <&mipidcphy0 PHY_TYPE_DPHY>;
+        phy-names = "dcphy";
+        rockchip,grf = <&vop_grf>;
+
+        ports {
+          #address-cells = <1>;
+          #size-cells = <0>;
+          dsi0_in: port@0 {
+            reg = <0>;
+          };
+
+          dsi0_out: port@1 {
+            reg = <1>;
+          };
+        };
+      };
+    };
diff --git a/dts/upstream/Bindings/display/ti/ti,am65x-dss.yaml b/dts/upstream/Bindings/display/ti/ti,am65x-dss.yaml
index 55e3e490d0e..31c4ffcb599 100644
--- a/dts/upstream/Bindings/display/ti/ti,am65x-dss.yaml
+++ b/dts/upstream/Bindings/display/ti/ti,am65x-dss.yaml
@@ -23,7 +23,7 @@ properties:
   compatible:
     enum:
       - ti,am625-dss
-      - ti,am62a7,dss
+      - ti,am62a7-dss
       - ti,am65x-dss
 
   reg:
diff --git a/dts/upstream/Bindings/display/xlnx/xlnx,zynqmp-dpsub.yaml b/dts/upstream/Bindings/display/xlnx/xlnx,zynqmp-dpsub.yaml
index 554f9d5809d..6b754d4f260 100644
--- a/dts/upstream/Bindings/display/xlnx/xlnx,zynqmp-dpsub.yaml
+++ b/dts/upstream/Bindings/display/xlnx/xlnx,zynqmp-dpsub.yaml
@@ -100,12 +100,16 @@ properties:
       - description: Video layer, plane 1 (U/V or U)
       - description: Video layer, plane 2 (V)
       - description: Graphics layer
+      - description: Audio channel 0
+      - description: Audio channel 1
   dma-names:
     items:
       - const: vid0
       - const: vid1
       - const: vid2
       - const: gfx0
+      - const: aud0
+      - const: aud1
 
   phys:
     description: PHYs for the DP data lanes
@@ -194,11 +198,13 @@ examples:
         power-domains = <&pd_dp>;
         resets = <&reset ZYNQMP_RESET_DP>;
 
-        dma-names = "vid0", "vid1", "vid2", "gfx0";
+        dma-names = "vid0", "vid1", "vid2", "gfx0", "aud0", "aud1";
         dmas = <&xlnx_dpdma 0>,
                <&xlnx_dpdma 1>,
                <&xlnx_dpdma 2>,
-               <&xlnx_dpdma 3>;
+               <&xlnx_dpdma 3>,
+               <&xlnx_dpdma 4>,
+               <&xlnx_dpdma 5>;
 
         phys = <&psgtr 1 PHY_TYPE_DP 0 3>,
                <&psgtr 0 PHY_TYPE_DP 1 3>;
diff --git a/dts/upstream/Bindings/dma/adi,axi-dmac.txt b/dts/upstream/Bindings/dma/adi,axi-dmac.txt
deleted file mode 100644
index cd17684aaab..00000000000
--- a/dts/upstream/Bindings/dma/adi,axi-dmac.txt
+++ /dev/null
@@ -1,61 +0,0 @@
-Analog Devices AXI-DMAC DMA controller
-
-Required properties:
- - compatible: Must be "adi,axi-dmac-1.00.a".
- - reg: Specification for the controllers memory mapped register map.
- - interrupts: Specification for the controllers interrupt.
- - clocks: Phandle and specifier to the controllers AXI interface clock
- - #dma-cells: Must be 1.
-
-Required sub-nodes:
- - adi,channels: This sub-node must contain a sub-node for each DMA channel. For
-   the channel sub-nodes the following bindings apply. They must match the
-   configuration options of the peripheral as it was instantiated.
-
-Required properties for adi,channels sub-node:
- - #size-cells: Must be 0
- - #address-cells: Must be 1
-
-Required channel sub-node properties:
- - reg: Which channel this node refers to.
- - adi,source-bus-width,
-   adi,destination-bus-width: Width of the source or destination bus in bits.
- - adi,source-bus-type,
-   adi,destination-bus-type: Type of the source or destination bus. Must be one
-   of the following:
-	0 (AXI_DMAC_TYPE_AXI_MM): Memory mapped AXI interface
-	1 (AXI_DMAC_TYPE_AXI_STREAM): Streaming AXI interface
-	2 (AXI_DMAC_TYPE_AXI_FIFO): FIFO interface
-
-Deprecated optional channel properties:
- - adi,length-width: Width of the DMA transfer length register.
- - adi,cyclic: Must be set if the channel supports hardware cyclic DMA
-   transfers.
- - adi,2d: Must be set if the channel supports hardware 2D DMA transfers.
-
-DMA clients connected to the AXI-DMAC DMA controller must use the format
-described in the dma.txt file using a one-cell specifier. The value of the
-specifier refers to the DMA channel index.
-
-Example:
-
-dma: dma@7c420000 {
-	compatible = "adi,axi-dmac-1.00.a";
-	reg = <0x7c420000 0x10000>;
-	interrupts = <0 57 0>;
-	clocks = <&clkc 16>;
-	#dma-cells = <1>;
-
-	adi,channels {
-		#size-cells = <0>;
-		#address-cells = <1>;
-
-		dma-channel@0 {
-			reg = <0>;
-			adi,source-bus-width = <32>;
-			adi,source-bus-type = <ADI_AXI_DMAC_TYPE_MM_AXI>;
-			adi,destination-bus-width = <64>;
-			adi,destination-bus-type = <ADI_AXI_DMAC_TYPE_FIFO>;
-		};
-	};
-};
diff --git a/dts/upstream/Bindings/dma/adi,axi-dmac.yaml b/dts/upstream/Bindings/dma/adi,axi-dmac.yaml
new file mode 100644
index 00000000000..63b6fb0423c
--- /dev/null
+++ b/dts/upstream/Bindings/dma/adi,axi-dmac.yaml
@@ -0,0 +1,129 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/dma/adi,axi-dmac.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Analog Devices AXI-DMAC DMA controller
+
+description: |
+  FPGA-based DMA controller designed for use with high-speed converter hardware.
+
+  http://analogdevicesinc.github.io/hdl/library/axi_dmac/index.html
+
+maintainers:
+  - Nuno Sa <nuno.sa@analog.com>
+
+additionalProperties: false
+
+properties:
+  compatible:
+    const: adi,axi-dmac-1.00.a
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+
+  clocks:
+    maxItems: 1
+
+  "#dma-cells":
+    const: 1
+
+  adi,channels:
+    deprecated: true
+    type: object
+    description:
+      This sub-node must contain a sub-node for each DMA channel. This node is
+      only required for IP versions older than 4.3.a and should otherwise be
+      omitted.
+    additionalProperties: false
+
+    properties:
+      "#size-cells":
+        const: 0
+      "#address-cells":
+        const: 1
+
+    patternProperties:
+      "^dma-channel@[0-9a-f]+$":
+        type: object
+        description:
+          DMA channel properties based on HDL compile-time configuration.
+        additionalProperties: false
+
+        properties:
+          reg:
+            maxItems: 1
+
+          adi,source-bus-width:
+            $ref: /schemas/types.yaml#/definitions/uint32
+            description: Width of the source bus in bits.
+            enum: [8, 16, 32, 64, 128]
+
+          adi,destination-bus-width:
+            $ref: /schemas/types.yaml#/definitions/uint32
+            description: Width of the destination bus in bits.
+            enum: [8, 16, 32, 64, 128]
+
+          adi,source-bus-type:
+            $ref: /schemas/types.yaml#/definitions/uint32
+            description: |
+              Type of the source bus.
+
+              0: Memory mapped AXI interface
+              1: Streaming AXI interface
+              2: FIFO interface
+            enum: [0, 1, 2]
+
+          adi,destination-bus-type:
+            $ref: /schemas/types.yaml#/definitions/uint32
+            description: Type of the destination bus (see adi,source-bus-type).
+            enum: [0, 1, 2]
+
+          adi,length-width:
+            deprecated: true
+            $ref: /schemas/types.yaml#/definitions/uint32
+            description: Width of the DMA transfer length register.
+
+          adi,cyclic:
+            deprecated: true
+            type: boolean
+            description:
+              Must be set if the channel supports hardware cyclic DMA transfers.
+
+          adi,2d:
+            deprecated: true
+            type: boolean
+            description:
+              Must be set if the channel supports hardware 2D DMA transfers.
+
+        required:
+          - reg
+          - adi,source-bus-width
+          - adi,destination-bus-width
+          - adi,source-bus-type
+          - adi,destination-bus-type
+
+    required:
+      - "#size-cells"
+      - "#address-cells"
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - clocks
+  - "#dma-cells"
+
+examples:
+  - |
+    dma-controller@7c420000 {
+        compatible = "adi,axi-dmac-1.00.a";
+        reg = <0x7c420000 0x10000>;
+        interrupts = <0 57 0>;
+        clocks = <&clkc 16>;
+        #dma-cells = <1>;
+    };
diff --git a/dts/upstream/Bindings/dma/allwinner,sun4i-a10-dma.yaml b/dts/upstream/Bindings/dma/allwinner,sun4i-a10-dma.yaml
index 02d5bd03540..9b5180c0a7c 100644
--- a/dts/upstream/Bindings/dma/allwinner,sun4i-a10-dma.yaml
+++ b/dts/upstream/Bindings/dma/allwinner,sun4i-a10-dma.yaml
@@ -22,7 +22,9 @@ properties:
       number.
 
   compatible:
-    const: allwinner,sun4i-a10-dma
+    enum:
+      - allwinner,sun4i-a10-dma
+      - allwinner,suniv-f1c100s-dma
 
   reg:
     maxItems: 1
diff --git a/dts/upstream/Bindings/dma/atmel,sama5d4-dma.yaml b/dts/upstream/Bindings/dma/atmel,sama5d4-dma.yaml
new file mode 100644
index 00000000000..9ca1c5d1f00
--- /dev/null
+++ b/dts/upstream/Bindings/dma/atmel,sama5d4-dma.yaml
@@ -0,0 +1,79 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/dma/atmel,sama5d4-dma.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Microchip AT91 Extensible Direct Memory Access Controller
+
+maintainers:
+  - Nicolas Ferre <nicolas.ferre@microchip.com>
+  - Charan Pedumuru <charan.pedumuru@microchip.com>
+
+description:
+  The DMA Controller (XDMAC) is a AHB-protocol central direct memory access
+  controller. It performs peripheral data transfer and memory move operations
+  over one or two bus ports through the unidirectional communication
+  channel. Each channel is fully programmable and provides both peripheral
+  or memory-to-memory transfers. The channel features are configurable at
+  implementation.
+
+allOf:
+  - $ref: dma-controller.yaml#
+
+properties:
+  compatible:
+    oneOf:
+      - enum:
+          - atmel,sama5d4-dma
+          - microchip,sama7g5-dma
+      - items:
+          - enum:
+              - microchip,sam9x60-dma
+              - microchip,sam9x7-dma
+          - const: atmel,sama5d4-dma
+
+  "#dma-cells":
+    description: |
+      Represents the number of integer cells in the `dmas` property of client
+      devices. The single cell specifies the channel configuration register:
+        - bit 13: SIF (Source Interface Identifier) for memory interface.
+        - bit 14: DIF (Destination Interface Identifier) for peripheral interface.
+        - bit 30-24: PERID (Peripheral Identifier).
+    const: 1
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+
+  clocks:
+    maxItems: 1
+
+  clock-names:
+    const: dma_clk
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - clocks
+  - clock-names
+  - "#dma-cells"
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/at91.h>
+    #include <dt-bindings/dma/at91.h>
+    #include <dt-bindings/interrupt-controller/irq.h>
+    dma-controller@f0008000 {
+        compatible = "atmel,sama5d4-dma";
+        reg = <0xf0008000 0x1000>;
+        interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>;
+        #dma-cells = <1>;
+        clocks = <&pmc PMC_TYPE_PERIPHERAL 20>;
+        clock-names = "dma_clk";
+    };
diff --git a/dts/upstream/Bindings/dma/atmel-xdma.txt b/dts/upstream/Bindings/dma/atmel-xdma.txt
deleted file mode 100644
index 76d649b3a25..00000000000
--- a/dts/upstream/Bindings/dma/atmel-xdma.txt
+++ /dev/null
@@ -1,54 +0,0 @@
-* Atmel Extensible Direct Memory Access Controller (XDMAC)
-
-* XDMA Controller
-Required properties:
-- compatible: Should be "atmel,sama5d4-dma", "microchip,sam9x60-dma" or
-  "microchip,sama7g5-dma" or
-  "microchip,sam9x7-dma", "atmel,sama5d4-dma".
-- reg: Should contain DMA registers location and length.
-- interrupts: Should contain DMA interrupt.
-- #dma-cells: Must be <1>, used to represent the number of integer cells in
-the dmas property of client devices.
-  - The 1st cell specifies the channel configuration register:
-    - bit 13: SIF, source interface identifier, used to get the memory
-    interface identifier,
-    - bit 14: DIF, destination interface identifier, used to get the peripheral
-    interface identifier,
-    - bit 30-24: PERID, peripheral identifier.
-
-Example:
-
-dma1: dma-controller@f0004000 {
-	compatible = "atmel,sama5d4-dma";
-	reg = <0xf0004000 0x200>;
-	interrupts = <50 4 0>;
-	#dma-cells = <1>;
-};
-
-
-* DMA clients
-DMA clients connected to the Atmel XDMA controller must use the format
-described in the dma.txt file, using a one-cell specifier for each channel.
-The two cells in order are:
-1. A phandle pointing to the DMA controller.
-2. Channel configuration register. Configurable fields are:
-    - bit 13: SIF, source interface identifier, used to get the memory
-    interface identifier,
-    - bit 14: DIF, destination interface identifier, used to get the peripheral
-    interface identifier,
-  - bit 30-24: PERID, peripheral identifier.
-
-Example:
-
-i2c2: i2c@f8024000 {
-	compatible = "atmel,at91sam9x5-i2c";
-	reg = <0xf8024000 0x4000>;
-	interrupts = <34 4 6>;
-	dmas = <&dma1
-		(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
-		 | AT91_XDMAC_DT_PERID(6))>,
-	       <&dma1
-		(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
-		| AT91_XDMAC_DT_PERID(7))>;
-	dma-names = "tx", "rx";
-};
diff --git a/dts/upstream/Bindings/dma/fsl,edma.yaml b/dts/upstream/Bindings/dma/fsl,edma.yaml
index d54140f18d3..4f925469533 100644
--- a/dts/upstream/Bindings/dma/fsl,edma.yaml
+++ b/dts/upstream/Bindings/dma/fsl,edma.yaml
@@ -26,9 +26,13 @@ properties:
           - fsl,imx93-edma3
           - fsl,imx93-edma4
           - fsl,imx95-edma5
+          - nxp,s32g2-edma
       - items:
           - const: fsl,ls1028a-edma
           - const: fsl,vf610-edma
+      - items:
+          - const: nxp,s32g3-edma
+          - const: nxp,s32g2-edma
 
   reg:
     minItems: 1
@@ -221,6 +225,36 @@ allOf:
       properties:
         power-domains: false
 
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: nxp,s32g2-edma
+    then:
+      properties:
+        clocks:
+          minItems: 2
+          maxItems: 2
+        clock-names:
+          items:
+            - const: dmamux0
+            - const: dmamux1
+        interrupts:
+          minItems: 3
+          maxItems: 3
+        interrupt-names:
+          items:
+            - const: tx-0-15
+            - const: tx-16-31
+            - const: err
+        reg:
+          minItems: 3
+          maxItems: 3
+        "#dma-cells":
+          const: 2
+        dma-channels:
+          const: 32
+
 unevaluatedProperties: false
 
 examples:
diff --git a/dts/upstream/Bindings/dma/nvidia,tegra210-adma.yaml b/dts/upstream/Bindings/dma/nvidia,tegra210-adma.yaml
index 877147e95ec..d3f8c269916 100644
--- a/dts/upstream/Bindings/dma/nvidia,tegra210-adma.yaml
+++ b/dts/upstream/Bindings/dma/nvidia,tegra210-adma.yaml
@@ -13,9 +13,6 @@ description: |
 maintainers:
   - Jon Hunter <jonathanh@nvidia.com>
 
-allOf:
-  - $ref: dma-controller.yaml#
-
 properties:
   compatible:
     oneOf:
@@ -29,7 +26,19 @@ properties:
           - const: nvidia,tegra186-adma
 
   reg:
-    maxItems: 1
+    description:
+      The 'page' region describes the address space of the page
+      used for accessing the DMA channel registers. The 'global'
+      region describes the address space of the global DMA registers.
+      In the absence of the 'reg-names' property, there must be a
+      single entry that covers the address space of the global DMA
+      registers and the DMA channel registers.
+    minItems: 1
+    maxItems: 2
+
+  reg-names:
+    minItems: 1
+    maxItems: 2
 
   interrupts:
     description: |
@@ -63,6 +72,49 @@ required:
   - clocks
   - clock-names
 
+allOf:
+  - $ref: dma-controller.yaml#
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - nvidia,tegra210-adma
+    then:
+      properties:
+        reg:
+          items:
+            - description: Full address space range of DMA registers.
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - nvidia,tegra186-adma
+    then:
+      anyOf:
+        - properties:
+            reg:
+              items:
+                - description: Full address space range of DMA registers.
+        - properties:
+            reg:
+              items:
+                - description: Channel Page address space range of DMA registers.
+            reg-names:
+              items:
+                - const: page
+        - properties:
+            reg:
+              items:
+                - description: Channel Page address space range of DMA registers.
+                - description: Global Page address space range of DMA registers.
+            reg-names:
+              items:
+                - const: page
+                - const: global
+
 additionalProperties: false
 
 examples:
diff --git a/dts/upstream/Bindings/dma/qcom,gpi.yaml b/dts/upstream/Bindings/dma/qcom,gpi.yaml
index 4ad56a409b9..7052468b15c 100644
--- a/dts/upstream/Bindings/dma/qcom,gpi.yaml
+++ b/dts/upstream/Bindings/dma/qcom,gpi.yaml
@@ -25,7 +25,9 @@ properties:
       - items:
           - enum:
               - qcom,qcm2290-gpi-dma
+              - qcom,qcs8300-gpi-dma
               - qcom,qdu1000-gpi-dma
+              - qcom,sa8775p-gpi-dma
               - qcom,sar2130p-gpi-dma
               - qcom,sc7280-gpi-dma
               - qcom,sdx75-gpi-dma
@@ -35,10 +37,12 @@ properties:
               - qcom,sm8450-gpi-dma
               - qcom,sm8550-gpi-dma
               - qcom,sm8650-gpi-dma
+              - qcom,sm8750-gpi-dma
               - qcom,x1e80100-gpi-dma
           - const: qcom,sm6350-gpi-dma
       - items:
           - enum:
+              - qcom,qcs615-gpi-dma
               - qcom,sdm670-gpi-dma
               - qcom,sm6125-gpi-dma
               - qcom,sm8150-gpi-dma
diff --git a/dts/upstream/Bindings/dma/stm32/st,stm32-dmamux.yaml b/dts/upstream/Bindings/dma/stm32/st,stm32-dmamux.yaml
index f26c914a3a9..b7bca1a8376 100644
--- a/dts/upstream/Bindings/dma/stm32/st,stm32-dmamux.yaml
+++ b/dts/upstream/Bindings/dma/stm32/st,stm32-dmamux.yaml
@@ -15,6 +15,16 @@ allOf:
 properties:
   "#dma-cells":
     const: 3
+    description: |
+      Each cell represents the following:
+      1. The mux input number/line for the request
+      2. Bitfield representing DMA channel configuration that is passed
+         to the real DMA controller
+      3. Bitfield representing device dependent DMA features passed to
+         the real DMA controller
+
+      For bitfield definitions of cells 2 and 3, see the associated
+      bindings doc for the actual DMA controller in st,stm32-dma.yaml.
 
   compatible:
     const: st,stm32h7-dmamux
diff --git a/dts/upstream/Bindings/dma/ti/k3-bcdma.yaml b/dts/upstream/Bindings/dma/ti/k3-bcdma.yaml
index 27b8e163656..b5bc842c5a0 100644
--- a/dts/upstream/Bindings/dma/ti/k3-bcdma.yaml
+++ b/dts/upstream/Bindings/dma/ti/k3-bcdma.yaml
@@ -34,6 +34,7 @@ properties:
       - ti,am62a-dmss-bcdma-csirx
       - ti,am64-dmss-bcdma
       - ti,j721s2-dmss-bcdma-csi
+      - ti,j722s-dmss-bcdma-csi
 
   reg:
     minItems: 3
@@ -196,7 +197,9 @@ allOf:
       properties:
         compatible:
           contains:
-            const: ti,j721s2-dmss-bcdma-csi
+            enum:
+              - ti,j721s2-dmss-bcdma-csi
+              - ti,j722s-dmss-bcdma-csi
     then:
       properties:
         ti,sci-rm-range-bchan: false
diff --git a/dts/upstream/Bindings/dts-coding-style.rst b/dts/upstream/Bindings/dts-coding-style.rst
index 8a68331075a..4772ded8a98 100644
--- a/dts/upstream/Bindings/dts-coding-style.rst
+++ b/dts/upstream/Bindings/dts-coding-style.rst
@@ -162,14 +162,17 @@ Example::
 		status = "okay";
 	}
 
-Indentation
------------
+Indentation and wrapping
+------------------------
 
-1. Use indentation according to Documentation/process/coding-style.rst.
+1. Use indentation and wrap lines according to
+   Documentation/process/coding-style.rst.
 2. Each entry in arrays with multiple cells, e.g. "reg" with two IO addresses,
    shall be enclosed in <>.
-3. For arrays spanning across lines, it is preferred to align the continued
-   entries with opening < from the first line.
+3. For arrays spanning across lines, it is preferred to split on item boundary
+   and align the continued entries with opening < from the first line.
+   Usually avoid splitting individual items unless they significantly exceed
+   line wrap limit.
 
 Example::
 
@@ -177,6 +180,9 @@ Example::
 		compatible = "qcom,sm8550-tsens", "qcom,tsens-v2";
 		reg = <0x0 0x0c271000 0x0 0x1000>,
 		      <0x0 0x0c222000 0x0 0x1000>;
+		/* Lines exceeding coding style line wrap limit: */
+		interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>,
+				<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>;
 	};
 
 Organizing DTSI and DTS
diff --git a/dts/upstream/Bindings/eeprom/at24.yaml b/dts/upstream/Bindings/eeprom/at24.yaml
index 590ba0ef5fa..c9e4afbdc44 100644
--- a/dts/upstream/Bindings/eeprom/at24.yaml
+++ b/dts/upstream/Bindings/eeprom/at24.yaml
@@ -134,10 +134,15 @@ properties:
           - const: atmel,24c64
       - items:
           - enum:
+              - giantec,gt24p128f
               - renesas,r1ex24128
               - samsung,s524ad0xd1
           - const: atmel,24c128
       - items:
+          - enum:
+              - puya,p24c256c
+          - const: atmel,24c256
+      - items:
           - const: microchip,24aa025e48
       - items:
           - const: microchip,24aa025e64
diff --git a/dts/upstream/Bindings/firmware/qcom,scm.yaml b/dts/upstream/Bindings/firmware/qcom,scm.yaml
index 2ee03000000..8cdaac8011b 100644
--- a/dts/upstream/Bindings/firmware/qcom,scm.yaml
+++ b/dts/upstream/Bindings/firmware/qcom,scm.yaml
@@ -26,6 +26,7 @@ properties:
           - qcom,scm-ipq4019
           - qcom,scm-ipq5018
           - qcom,scm-ipq5332
+          - qcom,scm-ipq5424
           - qcom,scm-ipq6018
           - qcom,scm-ipq806x
           - qcom,scm-ipq8074
@@ -42,6 +43,7 @@ properties:
           - qcom,scm-msm8996
           - qcom,scm-msm8998
           - qcom,scm-qcm2290
+          - qcom,scm-qcs615
           - qcom,scm-qcs8300
           - qcom,scm-qdu1000
           - qcom,scm-sa8255p
diff --git a/dts/upstream/Bindings/gpio/brcm,brcmstb-gpio.yaml b/dts/upstream/Bindings/gpio/brcm,brcmstb-gpio.yaml
index f096f286da1..fbd69b4cecc 100644
--- a/dts/upstream/Bindings/gpio/brcm,brcmstb-gpio.yaml
+++ b/dts/upstream/Bindings/gpio/brcm,brcmstb-gpio.yaml
@@ -64,6 +64,10 @@ properties:
 
   gpio-ranges: true
 
+  gpio-line-names:
+    minItems: 1
+    maxItems: 128
+
   wakeup-source:
     type: boolean
     description: >
diff --git a/dts/upstream/Bindings/gpio/fairchild,74hc595.yaml b/dts/upstream/Bindings/gpio/fairchild,74hc595.yaml
index e8bc9f018ed..0e5c22929bd 100644
--- a/dts/upstream/Bindings/gpio/fairchild,74hc595.yaml
+++ b/dts/upstream/Bindings/gpio/fairchild,74hc595.yaml
@@ -6,6 +6,23 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
 
 title: Generic 8-bit shift register
 
+description: |
+  NOTE: These chips nominally don't have a chip select pin. They do however
+  have a rising-edge triggered latch clock (or storage register clock) pin,
+  which behaves like an active-low chip select.
+
+  After the bits are shifted into the shift register, CS# is driven high, which
+  the 74HC595 sees as a rising edge on the latch clock that results in a
+  transfer of the bits from the shift register to the storage register and thus
+  to the output pins.
+                      _   _       _   _
+  shift clock    ____| |_| |_..._| |_| |_________
+
+  latch clock                           * trigger
+                 ___                     ________
+  chip select#      |___________________|
+
+
 maintainers:
   - Maxime Ripard <mripard@kernel.org>
 
diff --git a/dts/upstream/Bindings/gpio/fsl,qoriq-gpio.yaml b/dts/upstream/Bindings/gpio/fsl,qoriq-gpio.yaml
index 84fd82291ee..f1b60ab3f35 100644
--- a/dts/upstream/Bindings/gpio/fsl,qoriq-gpio.yaml
+++ b/dts/upstream/Bindings/gpio/fsl,qoriq-gpio.yaml
@@ -15,6 +15,7 @@ properties:
       - enum:
           - fsl,mpc5121-gpio
           - fsl,mpc5125-gpio
+          - fsl,mpc8314-gpio
           - fsl,mpc8349-gpio
           - fsl,mpc8572-gpio
           - fsl,mpc8610-gpio
diff --git a/dts/upstream/Bindings/gpu/arm,mali-utgard.yaml b/dts/upstream/Bindings/gpu/arm,mali-utgard.yaml
index abd4aa335fb..9318817ea13 100644
--- a/dts/upstream/Bindings/gpu/arm,mali-utgard.yaml
+++ b/dts/upstream/Bindings/gpu/arm,mali-utgard.yaml
@@ -33,6 +33,7 @@ properties:
               - rockchip,rk3188-mali
               - rockchip,rk3228-mali
               - samsung,exynos4210-mali
+              - st,stih410-mali
               - stericsson,db8500-mali
               - xlnx,zynqmp-mali
           - const: arm,mali-400
diff --git a/dts/upstream/Bindings/hwmon/adi,adm1275.yaml b/dts/upstream/Bindings/hwmon/adi,adm1275.yaml
index 5b076d67739..fd79bf2e0d1 100644
--- a/dts/upstream/Bindings/hwmon/adi,adm1275.yaml
+++ b/dts/upstream/Bindings/hwmon/adi,adm1275.yaml
@@ -24,6 +24,7 @@ properties:
     enum:
       - adi,adm1075
       - adi,adm1272
+      - adi,adm1273
       - adi,adm1275
       - adi,adm1276
       - adi,adm1278
@@ -79,6 +80,7 @@ allOf:
           contains:
             enum:
               - adi,adm1272
+              - adi,adm1273
     then:
       properties:
         adi,volt-curr-sample-average:
diff --git a/dts/upstream/Bindings/hwmon/lm75.yaml b/dts/upstream/Bindings/hwmon/lm75.yaml
index 29bd7460cc2..c38255243f5 100644
--- a/dts/upstream/Bindings/hwmon/lm75.yaml
+++ b/dts/upstream/Bindings/hwmon/lm75.yaml
@@ -28,6 +28,7 @@ properties:
       - maxim,max31725
       - maxim,max31726
       - maxim,mcp980x
+      - nxp,p3t1755
       - nxp,pct2075
       - st,stds75
       - st,stlm75
diff --git a/dts/upstream/Bindings/i2c/i2c-exynos5.yaml b/dts/upstream/Bindings/i2c/i2c-exynos5.yaml
index cc8bba5537b..70cc2ee9ee2 100644
--- a/dts/upstream/Bindings/i2c/i2c-exynos5.yaml
+++ b/dts/upstream/Bindings/i2c/i2c-exynos5.yaml
@@ -25,6 +25,7 @@ properties:
           - samsung,exynos5250-hsi2c    # Exynos5250 and Exynos5420
           - samsung,exynos5260-hsi2c    # Exynos5260
           - samsung,exynos7-hsi2c       # Exynos7
+          - samsung,exynos8895-hsi2c
           - samsung,exynosautov9-hsi2c
       - items:
           - enum:
diff --git a/dts/upstream/Bindings/i2c/qcom,i2c-cci.yaml b/dts/upstream/Bindings/i2c/qcom,i2c-cci.yaml
index ef26ba6eda2..73144473b9b 100644
--- a/dts/upstream/Bindings/i2c/qcom,i2c-cci.yaml
+++ b/dts/upstream/Bindings/i2c/qcom,i2c-cci.yaml
@@ -34,6 +34,7 @@ properties:
               - qcom,sm8450-cci
               - qcom,sm8550-cci
               - qcom,sm8650-cci
+              - qcom,x1e80100-cci
           - const: qcom,msm8996-cci # CCI v2
 
   "#address-cells":
@@ -224,6 +225,7 @@ allOf:
             enum:
               - qcom,sm8550-cci
               - qcom,sm8650-cci
+              - qcom,x1e80100-cci
     then:
       properties:
         clocks:
diff --git a/dts/upstream/Bindings/i2c/renesas,riic.yaml b/dts/upstream/Bindings/i2c/renesas,riic.yaml
index 505a8ec9226..1b7fed23264 100644
--- a/dts/upstream/Bindings/i2c/renesas,riic.yaml
+++ b/dts/upstream/Bindings/i2c/renesas,riic.yaml
@@ -26,7 +26,9 @@ properties:
           - const: renesas,riic-rz      # RZ/A or RZ/G2L
 
       - items:
-          - const: renesas,riic-r9a08g045   # RZ/G3S
+          - enum:
+              - renesas,riic-r9a08g045   # RZ/G3S
+              - renesas,riic-r9a09g047   # RZ/G3E
           - const: renesas,riic-r9a09g057   # RZ/V2H(P)
 
       - const: renesas,riic-r9a09g057   # RZ/V2H(P)
@@ -89,6 +91,7 @@ if:
           - renesas,riic-r9a07g043
           - renesas,riic-r9a07g044
           - renesas,riic-r9a07g054
+          - renesas,riic-r9a09g057
 then:
   required:
     - resets
diff --git a/dts/upstream/Bindings/iio/accel/adi,adxl345.yaml b/dts/upstream/Bindings/iio/accel/adi,adxl345.yaml
index 280ed479ef5..84d94939201 100644
--- a/dts/upstream/Bindings/iio/accel/adi,adxl345.yaml
+++ b/dts/upstream/Bindings/iio/accel/adi,adxl345.yaml
@@ -37,10 +37,17 @@ properties:
   interrupts:
     maxItems: 1
 
+  interrupt-names:
+    items:
+      - enum: [INT1, INT2]
+
+dependencies:
+  interrupts: [ interrupt-names ]
+  interrupt-names: [ interrupts ]
+
 required:
   - compatible
   - reg
-  - interrupts
 
 allOf:
   - $ref: /schemas/spi/spi-peripheral-props.yaml#
@@ -61,6 +68,7 @@ examples:
             reg = <0x2a>;
             interrupt-parent = <&gpio0>;
             interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
+            interrupt-names = "INT1";
         };
     };
   - |
@@ -79,5 +87,6 @@ examples:
             spi-cpha;
             interrupt-parent = <&gpio0>;
             interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
+            interrupt-names = "INT2";
         };
     };
diff --git a/dts/upstream/Bindings/iio/accel/kionix,kx022a.yaml b/dts/upstream/Bindings/iio/accel/kionix,kx022a.yaml
index 66ea894dbe5..f07c70e51c4 100644
--- a/dts/upstream/Bindings/iio/accel/kionix,kx022a.yaml
+++ b/dts/upstream/Bindings/iio/accel/kionix,kx022a.yaml
@@ -4,23 +4,26 @@
 $id: http://devicetree.org/schemas/iio/accel/kionix,kx022a.yaml#
 $schema: http://devicetree.org/meta-schemas/core.yaml#
 
-title: ROHM/Kionix KX022A, KX132-1211 and KX132ACR-LBZ Accelerometers
+title: ROHM/Kionix KX022A, KX132/134-1211 and KX132/134ACR-LBZ Accelerometers
 
 maintainers:
   - Matti Vaittinen <mazziesaccount@gmail.com>
 
 description: |
   KX022A, KX132ACR-LBZ and KX132-1211 are 3-axis accelerometers supporting
-  +/- 2G, 4G, 8G and 16G ranges, variable output data-rates and a
-  hardware-fifo buffering. These accelerometers can be accessed either
-  via I2C or SPI.
+  +/- 2G, 4G, 8G and 16G ranges. The KX134ACR-LBZ and KX134-1211 support
+  +/- 8G, 16G, 32G and 64G. All the sensors also have variable output
+  data-rates and a hardware-fifo buffering. These accelerometers can be
+  accessed either via I2C or SPI.
 
 properties:
   compatible:
     enum:
       - kionix,kx022a
       - kionix,kx132-1211
+      - kionix,kx134-1211
       - rohm,kx132acr-lbz
+      - rohm,kx134acr-lbz
 
   reg:
     maxItems: 1
diff --git a/dts/upstream/Bindings/iio/accel/nxp,fxls8962af.yaml b/dts/upstream/Bindings/iio/accel/nxp,fxls8962af.yaml
index 783c7ddfcd9..c175f4c4cbd 100644
--- a/dts/upstream/Bindings/iio/accel/nxp,fxls8962af.yaml
+++ b/dts/upstream/Bindings/iio/accel/nxp,fxls8962af.yaml
@@ -14,12 +14,20 @@ description: |
   SPI and I2C interface.
     https://www.nxp.com/docs/en/data-sheet/FXLS8962AF.pdf
     https://www.nxp.com/docs/en/data-sheet/FXLS8964AF.pdf
+    https://www.nxp.com/docs/en/data-sheet/FXLS8967AF.pdf
+    https://www.nxp.com/docs/en/data-sheet/FXLS8974CF.pdf
 
 properties:
   compatible:
-    enum:
-      - nxp,fxls8962af
-      - nxp,fxls8964af
+    oneOf:
+      - enum:
+          - nxp,fxls8962af
+          - nxp,fxls8964af
+      - items:
+          - enum:
+              - nxp,fxls8967af
+              - nxp,fxls8974cf
+          - const: nxp,fxls8962af
 
   reg:
     maxItems: 1
@@ -38,6 +46,11 @@ properties:
   drive-open-drain:
     type: boolean
 
+  wakeup-source:
+    $ref: /schemas/types.yaml#/definitions/flag
+    description:
+      Enable wake on accelerometer event
+
 required:
   - compatible
   - reg
@@ -61,6 +74,7 @@ examples:
             interrupt-parent = <&gpio0>;
             interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
             interrupt-names = "INT1";
+            wakeup-source;
         };
     };
   - |
diff --git a/dts/upstream/Bindings/iio/adc/adi,ad4000.yaml b/dts/upstream/Bindings/iio/adc/adi,ad4000.yaml
index e413a9d8d2a..96e01a97dd9 100644
--- a/dts/upstream/Bindings/iio/adc/adi,ad4000.yaml
+++ b/dts/upstream/Bindings/iio/adc/adi,ad4000.yaml
@@ -19,49 +19,82 @@ description: |
     https://www.analog.com/media/en/technical-documentation/data-sheets/ad4020-4021-4022.pdf
     https://www.analog.com/media/en/technical-documentation/data-sheets/adaq4001.pdf
     https://www.analog.com/media/en/technical-documentation/data-sheets/adaq4003.pdf
+    https://www.analog.com/media/en/technical-documentation/data-sheets/ad7685.pdf
+    https://www.analog.com/media/en/technical-documentation/data-sheets/ad7686.pdf
+    https://www.analog.com/media/en/technical-documentation/data-sheets/ad7687.pdf
+    https://www.analog.com/media/en/technical-documentation/data-sheets/ad7688.pdf
+    https://www.analog.com/media/en/technical-documentation/data-sheets/ad7690.pdf
+    https://www.analog.com/media/en/technical-documentation/data-sheets/ad7691.pdf
+    https://www.analog.com/media/en/technical-documentation/data-sheets/ad7693.pdf
+    https://www.analog.com/media/en/technical-documentation/data-sheets/ad7942.pdf
+    https://www.analog.com/media/en/technical-documentation/data-sheets/ad7946.pdf
+    https://www.analog.com/media/en/technical-documentation/data-sheets/ad7980.pdf
+    https://www.analog.com/media/en/technical-documentation/data-sheets/ad7982.pdf
+    https://www.analog.com/media/en/technical-documentation/data-sheets/ad7983.pdf
+    https://www.analog.com/media/en/technical-documentation/data-sheets/ad7984.pdf
+    https://www.analog.com/media/en/technical-documentation/data-sheets/ad7988-1_7988-5.pdf
 
 $ref: /schemas/spi/spi-peripheral-props.yaml#
 
 properties:
   compatible:
     oneOf:
-      - const: adi,ad4000
+      - enum:
+          - adi,ad4000
+          - adi,ad4001
+          - adi,ad4002
+          - adi,ad4003
+          - adi,ad4020
+          - adi,adaq4001
+          - adi,adaq4003
+          - adi,ad7687
+          - adi,ad7691
+          - adi,ad7942
+          - adi,ad7946
+          - adi,ad7983
       - items:
           - enum:
               - adi,ad4004
               - adi,ad4008
           - const: adi,ad4000
-
-      - const: adi,ad4001
       - items:
           - enum:
               - adi,ad4005
           - const: adi,ad4001
-
-      - const: adi,ad4002
       - items:
           - enum:
               - adi,ad4006
               - adi,ad4010
           - const: adi,ad4002
-
-      - const: adi,ad4003
       - items:
           - enum:
               - adi,ad4007
               - adi,ad4011
           - const: adi,ad4003
-
-      - const: adi,ad4020
       - items:
           - enum:
               - adi,ad4021
               - adi,ad4022
           - const: adi,ad4020
-
-      - const: adi,adaq4001
-
-      - const: adi,adaq4003
+      - items:
+          - enum:
+              - adi,ad7685
+              - adi,ad7686
+              - adi,ad7980
+              - adi,ad7988-1
+              - adi,ad7988-5
+          - const: adi,ad7983
+      - items:
+          - enum:
+              - adi,ad7688
+              - adi,ad7693
+          - const: adi,ad7687
+      - items:
+          - enum:
+              - adi,ad7690
+              - adi,ad7982
+              - adi,ad7984
+          - const: adi,ad7691
 
   reg:
     maxItems: 1
@@ -133,6 +166,22 @@ required:
   - ref-supply
 
 allOf:
+  # Single-channel PulSAR devices have SDI either tied to VIO, GND, or host CS.
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - adi,ad7687
+              - adi,ad7691
+              - adi,ad7942
+              - adi,ad7946
+              - adi,ad7983
+    then:
+      properties:
+        adi,sdi-pin:
+          enum: [ high, low, cs ]
+          default: cs
   # The configuration register can only be accessed if SDI is connected to MOSI
   - if:
       required:
diff --git a/dts/upstream/Bindings/iio/adc/adi,ad4695.yaml b/dts/upstream/Bindings/iio/adc/adi,ad4695.yaml
index 310f046e139..7d2229dee44 100644
--- a/dts/upstream/Bindings/iio/adc/adi,ad4695.yaml
+++ b/dts/upstream/Bindings/iio/adc/adi,ad4695.yaml
@@ -134,8 +134,9 @@ patternProperties:
         description:
           Describes the common mode channel for single channels. 0xFF is REFGND
           and OxFE is COM. Macros are available for these values in
-          dt-bindings/iio/adi,ad4695.h. Values 1 to 15 correspond to INx inputs.
-          Only odd numbered INx inputs can be used as common mode channels.
+          dt-bindings/iio/adc/adi,ad4695.h. Values 1 to 15 correspond to INx
+          inputs. Only odd numbered INx inputs can be used as common mode
+          channels.
         enum: [1, 3, 5, 7, 9, 11, 13, 15, 0xFE, 0xFF]
         default: 0xFF
 
@@ -209,7 +210,7 @@ unevaluatedProperties: false
 examples:
   - |
     #include <dt-bindings/gpio/gpio.h>
-    #include <dt-bindings/iio/adi,ad4695.h>
+    #include <dt-bindings/iio/adc/adi,ad4695.h>
 
     spi {
         #address-cells = <1>;
diff --git a/dts/upstream/Bindings/iio/adc/adi,ad7124.yaml b/dts/upstream/Bindings/iio/adc/adi,ad7124.yaml
index 35ed04350e2..7146a654ae3 100644
--- a/dts/upstream/Bindings/iio/adc/adi,ad7124.yaml
+++ b/dts/upstream/Bindings/iio/adc/adi,ad7124.yaml
@@ -37,6 +37,17 @@ properties:
     description: IRQ line for the ADC
     maxItems: 1
 
+  rdy-gpios:
+    description:
+      GPIO reading the R̅D̅Y̅ line. Having such a GPIO is technically optional but
+      highly recommended because DOUT/R̅D̅Y̅ toggles during SPI transfers (in its
+      DOUT aka MISO role) and so usually triggers a spurious interrupt. The
+      distinction between such a spurious event and a real one can only be done
+      by reading such a GPIO. (There is a register telling the same
+      information, but accessing that one needs a SPI transfer which then
+      triggers another interrupt event.)
+    maxItems: 1
+
   '#address-cells':
     const: 1
 
@@ -111,6 +122,7 @@ unevaluatedProperties: false
 
 examples:
   - |
+    #include <dt-bindings/gpio/gpio.h>
     spi {
       #address-cells = <1>;
       #size-cells = <0>;
@@ -121,6 +133,7 @@ examples:
         spi-max-frequency = <5000000>;
         interrupts = <25 2>;
         interrupt-parent = <&gpio>;
+        rdy-gpios = <&gpio 25 GPIO_ACTIVE_LOW>;
         refin1-supply = <&adc_vref>;
         clocks = <&ad7124_mclk>;
         clock-names = "mclk";
diff --git a/dts/upstream/Bindings/iio/adc/adi,ad7173.yaml b/dts/upstream/Bindings/iio/adc/adi,ad7173.yaml
index ad15cf9bc2f..21ee319d467 100644
--- a/dts/upstream/Bindings/iio/adc/adi,ad7173.yaml
+++ b/dts/upstream/Bindings/iio/adc/adi,ad7173.yaml
@@ -135,6 +135,17 @@ properties:
   '#clock-cells':
     const: 0
 
+  rdy-gpios:
+    description:
+      GPIO reading the R̅D̅Y̅ line. Having such a GPIO is technically optional but
+      highly recommended because DOUT/R̅D̅Y̅ toggles during SPI transfers (in its
+      DOUT aka MISO role) and so usually triggers a spurious interrupt. The
+      distinction between such a spurious event and a real one can only be done
+      by reading such a GPIO. (There is a register telling the same
+      information, but accessing that one needs a SPI transfer which then
+      triggers another interrupt event.)
+    maxItems: 1
+
 patternProperties:
   "^channel@[0-9a-f]$":
     type: object
@@ -443,6 +454,7 @@ examples:
         interrupts = <25 IRQ_TYPE_EDGE_FALLING>;
         interrupt-names = "rdy";
         interrupt-parent = <&gpio>;
+        rdy-gpios = <&gpio 25 GPIO_ACTIVE_LOW>;
         spi-max-frequency = <5000000>;
         gpio-controller;
         #gpio-cells = <2>;
diff --git a/dts/upstream/Bindings/iio/adc/adi,ad7192.yaml b/dts/upstream/Bindings/iio/adc/adi,ad7192.yaml
index 66dd1c549bd..0bd2c6906c8 100644
--- a/dts/upstream/Bindings/iio/adc/adi,ad7192.yaml
+++ b/dts/upstream/Bindings/iio/adc/adi,ad7192.yaml
@@ -106,6 +106,17 @@ properties:
     description: see Documentation/devicetree/bindings/iio/adc/adc.yaml
     type: boolean
 
+  rdy-gpios:
+    description:
+      GPIO reading the R̅D̅Y̅ line. Having such a GPIO is technically optional but
+      highly recommended because DOUT/R̅D̅Y̅ toggles during SPI transfers (in its
+      DOUT aka MISO role) and so usually triggers a spurious interrupt. The
+      distinction between such a spurious event and a real one can only be done
+      by reading such a GPIO. (There is a register telling the same
+      information, but accessing that one needs a SPI transfer which then
+      triggers another interrupt event.)
+    maxItems: 1
+
 patternProperties:
   "^channel@[0-9a-f]+$":
     type: object
@@ -181,6 +192,7 @@ unevaluatedProperties: false
 
 examples:
   - |
+    #include <dt-bindings/gpio/gpio.h>
     spi {
         #address-cells = <1>;
         #size-cells = <0>;
@@ -195,6 +207,7 @@ examples:
             clock-names = "mclk";
             interrupts = <25 0x2>;
             interrupt-parent = <&gpio>;
+            rdy-gpios = <&gpio 25 GPIO_ACTIVE_LOW>;
             aincom-supply = <&aincom>;
             dvdd-supply = <&dvdd>;
             avdd-supply = <&avdd>;
@@ -207,6 +220,7 @@ examples:
         };
     };
   - |
+    #include <dt-bindings/gpio/gpio.h>
     spi {
         #address-cells = <1>;
         #size-cells = <0>;
@@ -224,6 +238,7 @@ examples:
             #clock-cells = <0>;
             interrupts = <25 0x2>;
             interrupt-parent = <&gpio>;
+            rdy-gpios = <&gpio 25 GPIO_ACTIVE_LOW>;
             aincom-supply = <&aincom>;
             dvdd-supply = <&dvdd>;
             avdd-supply = <&avdd>;
diff --git a/dts/upstream/Bindings/iio/adc/adi,ad7606.yaml b/dts/upstream/Bindings/iio/adc/adi,ad7606.yaml
index ab5881d0d01..52d3f1ce336 100644
--- a/dts/upstream/Bindings/iio/adc/adi,ad7606.yaml
+++ b/dts/upstream/Bindings/iio/adc/adi,ad7606.yaml
@@ -146,6 +146,7 @@ properties:
     maxItems: 2
 
   pwm-names:
+    minItems: 1
     items:
       - const: convst1
       - const: convst2
diff --git a/dts/upstream/Bindings/iio/adc/adi,ad7780.yaml b/dts/upstream/Bindings/iio/adc/adi,ad7780.yaml
index be2616ff9af..5c8df45bfab 100644
--- a/dts/upstream/Bindings/iio/adc/adi,ad7780.yaml
+++ b/dts/upstream/Bindings/iio/adc/adi,ad7780.yaml
@@ -63,6 +63,17 @@ properties:
       marked GPIO_ACTIVE_LOW.
     maxItems: 1
 
+  rdy-gpios:
+    description:
+      GPIO reading the R̅D̅Y̅ line. Having such a GPIO is technically optional but
+      highly recommended because DOUT/R̅D̅Y̅ toggles during SPI transfers (in its
+      DOUT aka MISO role) and so usually triggers a spurious interrupt. The
+      distinction between such a spurious event and a real one can only be done
+      by reading such a GPIO. (There is a register telling the same
+      information, but accessing that one needs a SPI transfer which then
+      triggers another interrupt event.)
+    maxItems: 1
+
 required:
   - compatible
   - reg
diff --git a/dts/upstream/Bindings/iio/adc/renesas,rzg2l-adc.yaml b/dts/upstream/Bindings/iio/adc/renesas,rzg2l-adc.yaml
index ba86c7b7d62..40341d54172 100644
--- a/dts/upstream/Bindings/iio/adc/renesas,rzg2l-adc.yaml
+++ b/dts/upstream/Bindings/iio/adc/renesas,rzg2l-adc.yaml
@@ -17,12 +17,15 @@ description: |
 
 properties:
   compatible:
-    items:
-      - enum:
-          - renesas,r9a07g043-adc   # RZ/G2UL and RZ/Five
-          - renesas,r9a07g044-adc   # RZ/G2L
-          - renesas,r9a07g054-adc   # RZ/V2L
-      - const: renesas,rzg2l-adc
+    oneOf:
+      - items:
+          - enum:
+              - renesas,r9a07g043-adc   # RZ/G2UL and RZ/Five
+              - renesas,r9a07g044-adc   # RZ/G2L
+              - renesas,r9a07g054-adc   # RZ/V2L
+          - const: renesas,rzg2l-adc
+      - items:
+          - const: renesas,r9a08g045-adc  # RZ/G3S
 
   reg:
     maxItems: 1
@@ -57,6 +60,9 @@ properties:
   '#size-cells':
     const: 0
 
+  "#io-channel-cells":
+    const: 1
+
 required:
   - compatible
   - reg
@@ -68,7 +74,7 @@ required:
   - reset-names
 
 patternProperties:
-  "^channel@[0-7]$":
+  "^channel@[0-8]$":
     $ref: adc.yaml
     type: object
     description: |
@@ -78,6 +84,8 @@ patternProperties:
       reg:
         description: |
           The channel number.
+        minimum: 0
+        maximum: 8
 
     required:
       - reg
@@ -92,18 +100,25 @@ allOf:
             const: renesas,r9a07g043-adc
     then:
       patternProperties:
-        "^channel@[2-7]$": false
+        "^channel@[2-8]$": false
         "^channel@[0-1]$":
           properties:
             reg:
-              minimum: 0
               maximum: 1
-    else:
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - renesas,r9a07g044-adc
+              - renesas,r9a07g054-adc
+    then:
       patternProperties:
+        "^channel@[8]$": false
         "^channel@[0-7]$":
           properties:
             reg:
-              minimum: 0
               maximum: 7
 
 additionalProperties: false
diff --git a/dts/upstream/Bindings/iio/chemical/bosch,bme680.yaml b/dts/upstream/Bindings/iio/chemical/bosch,bme680.yaml
new file mode 100644
index 00000000000..fe98ec44f08
--- /dev/null
+++ b/dts/upstream/Bindings/iio/chemical/bosch,bme680.yaml
@@ -0,0 +1,62 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/chemical/bosch,bme680.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Bosch BME680 Gas sensor
+
+maintainers:
+  - Vasileios Amoiridis <vassilisamir@gmail.com>
+
+description: >
+  BME680 is a gas sensor which combines relative humidity, barometric pressure,
+  ambient temperature and gas (VOC - Volatile Organic Compounds) measurements.
+
+  https://www.bosch-sensortec.com/media/boschsensortec/downloads/datasheets/bst-bme680-ds001.pdf
+
+properties:
+  compatible:
+    const: bosch,bme680
+
+  reg:
+    maxItems: 1
+
+  vdd-supply: true
+  vddio-supply: true
+
+required:
+  - compatible
+  - reg
+
+allOf:
+  - $ref: /schemas/spi/spi-peripheral-props.yaml#
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    i2c {
+        #address-cells = <1>;
+        #size-cells = <0>;
+
+        co2-sensor@77 {
+            compatible = "bosch,bme680";
+            reg = <0x77>;
+            vddio-supply = <&vddio>;
+            vdd-supply = <&vdd>;
+        };
+    };
+  - |
+    spi {
+        #address-cells = <1>;
+        #size-cells = <0>;
+
+        co2-sensor@0 {
+            compatible = "bosch,bme680";
+            reg = <0>;
+            spi-max-frequency = <500000>;
+            vddio-supply = <&vddio>;
+            vdd-supply = <&vdd>;
+        };
+    };
diff --git a/dts/upstream/Bindings/iio/dac/adi,ad5791.yaml b/dts/upstream/Bindings/iio/dac/adi,ad5791.yaml
index 79cb4b78a88..2bd89e0aa46 100644
--- a/dts/upstream/Bindings/iio/dac/adi,ad5791.yaml
+++ b/dts/upstream/Bindings/iio/dac/adi,ad5791.yaml
@@ -91,7 +91,7 @@ examples:
             vrefn-supply = <&dac_vrefn>;
             reset-gpios = <&gpio_bd 16 GPIO_ACTIVE_LOW>;
             clear-gpios = <&gpio_bd 17 GPIO_ACTIVE_LOW>;
-            ldac-gpios = <&gpio_bd 18 GPIO_ACTIVE_HIGH>;
+            ldac-gpios = <&gpio_bd 18 GPIO_ACTIVE_LOW>;
         };
     };
 ...
diff --git a/dts/upstream/Bindings/iio/dac/rohm,bd79703.yaml b/dts/upstream/Bindings/iio/dac/rohm,bd79703.yaml
new file mode 100644
index 00000000000..941a49c9394
--- /dev/null
+++ b/dts/upstream/Bindings/iio/dac/rohm,bd79703.yaml
@@ -0,0 +1,62 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+# Copyright 2024 ROHM Semiconductor.
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/dac/rohm,bd79703.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: ROHM BD79703 DAC device driver
+
+maintainers:
+  - Matti Vaittinen <mazziesaccount@gmail.com>
+
+description: |
+  The ROHM BD79703 is a 6 channel, 8-bit DAC.
+  Datasheet can be found here:
+  https://fscdn.rohm.com/en/products/databook/datasheet/ic/data_converter/dac/bd79702fv-lb_bd79703fv-lb-e.pdf
+
+properties:
+  compatible:
+    const: rohm,bd79703
+
+  reg:
+    maxItems: 1
+
+  spi-max-frequency:
+    maximum: 30000000
+
+  vfs-supply:
+    description:
+      The regulator to use as a full scale voltage. The voltage should be between 2.7V .. VCC
+
+  vcc-supply:
+    description:
+      The regulator supplying the operating voltage. Should be between 2.7V ... 5.5V
+
+required:
+  - compatible
+  - reg
+  - spi-max-frequency
+  - vfs-supply
+  - vcc-supply
+
+allOf:
+  - $ref: /schemas/spi/spi-peripheral-props.yaml#
+
+additionalProperties: false
+
+examples:
+  - |
+    spi {
+        #address-cells = <1>;
+        #size-cells = <0>;
+
+        dac@0 {
+            compatible = "rohm,bd79703";
+            reg = <0>;
+            spi-max-frequency = <30000000>;
+            vcc-supply = <&vcc>;
+            vfs-supply = <&vref>;
+        };
+    };
+...
diff --git a/dts/upstream/Bindings/iio/imu/adi,adis16480.yaml b/dts/upstream/Bindings/iio/imu/adi,adis16480.yaml
index e3eec38897b..7a1a74fec28 100644
--- a/dts/upstream/Bindings/iio/imu/adi,adis16480.yaml
+++ b/dts/upstream/Bindings/iio/imu/adi,adis16480.yaml
@@ -11,24 +11,30 @@ maintainers:
 
 properties:
   compatible:
-    enum:
-      - adi,adis16375
-      - adi,adis16480
-      - adi,adis16485
-      - adi,adis16488
-      - adi,adis16490
-      - adi,adis16495-1
-      - adi,adis16495-2
-      - adi,adis16495-3
-      - adi,adis16497-1
-      - adi,adis16497-2
-      - adi,adis16497-3
-      - adi,adis16545-1
-      - adi,adis16545-2
-      - adi,adis16545-3
-      - adi,adis16547-1
-      - adi,adis16547-2
-      - adi,adis16547-3
+    oneOf:
+      - enum:
+          - adi,adis16375
+          - adi,adis16480
+          - adi,adis16485
+          - adi,adis16486
+          - adi,adis16488
+          - adi,adis16489
+          - adi,adis16490
+          - adi,adis16495-1
+          - adi,adis16495-2
+          - adi,adis16495-3
+          - adi,adis16497-1
+          - adi,adis16497-2
+          - adi,adis16497-3
+          - adi,adis16545-1
+          - adi,adis16545-2
+          - adi,adis16545-3
+          - adi,adis16547-1
+          - adi,adis16547-2
+          - adi,adis16547-3
+      - items:
+          - const: adi,adis16487
+          - const: adi,adis16485
 
   reg:
     maxItems: 1
diff --git a/dts/upstream/Bindings/iio/imu/bosch,bmi160.yaml b/dts/upstream/Bindings/iio/imu/bosch,bmi160.yaml
index 3b0a2d8b2e9..2cf8a0c7eb4 100644
--- a/dts/upstream/Bindings/iio/imu/bosch,bmi160.yaml
+++ b/dts/upstream/Bindings/iio/imu/bosch,bmi160.yaml
@@ -37,6 +37,7 @@ properties:
       to "INT2" if INT2 pin should be used instead
 
   drive-open-drain:
+    type: boolean
     description: |
       set if the specified interrupt pin should be configured as
       open drain. If not set, defaults to push-pull.
diff --git a/dts/upstream/Bindings/iio/imu/bosch,bmi270.yaml b/dts/upstream/Bindings/iio/imu/bosch,bmi270.yaml
index 7b0cde1c9b0..860a6c1fea3 100644
--- a/dts/upstream/Bindings/iio/imu/bosch,bmi270.yaml
+++ b/dts/upstream/Bindings/iio/imu/bosch,bmi270.yaml
@@ -41,6 +41,7 @@ properties:
         - INT2
 
   drive-open-drain:
+    type: boolean
     description:
       set if the specified interrupt pins should be configured as
       open drain. If not set, defaults to push-pull.
diff --git a/dts/upstream/Bindings/iio/imu/bosch,bmi323.yaml b/dts/upstream/Bindings/iio/imu/bosch,bmi323.yaml
index 64ef26e1966..7bf8294a8f2 100644
--- a/dts/upstream/Bindings/iio/imu/bosch,bmi323.yaml
+++ b/dts/upstream/Bindings/iio/imu/bosch,bmi323.yaml
@@ -38,6 +38,7 @@ properties:
         - INT2
 
   drive-open-drain:
+    type: boolean
     description:
       set if the specified interrupt pin should be configured as
       open drain. If not set, defaults to push-pull.
diff --git a/dts/upstream/Bindings/iio/imu/invensense,mpu6050.yaml b/dts/upstream/Bindings/iio/imu/invensense,mpu6050.yaml
index f91954870a4..0bce71529e3 100644
--- a/dts/upstream/Bindings/iio/imu/invensense,mpu6050.yaml
+++ b/dts/upstream/Bindings/iio/imu/invensense,mpu6050.yaml
@@ -16,6 +16,7 @@ properties:
   compatible:
     oneOf:
       - enum:
+          - invensense,iam20380
           - invensense,iam20680
           - invensense,icm20608
           - invensense,icm20609
diff --git a/dts/upstream/Bindings/iio/light/rohm,bu27008.yaml b/dts/upstream/Bindings/iio/light/rohm,bu27008.yaml
deleted file mode 100644
index 4f66fd47b01..00000000000
--- a/dts/upstream/Bindings/iio/light/rohm,bu27008.yaml
+++ /dev/null
@@ -1,49 +0,0 @@
-# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
-%YAML 1.2
----
-$id: http://devicetree.org/schemas/iio/light/rohm,bu27008.yaml#
-$schema: http://devicetree.org/meta-schemas/core.yaml#
-
-title: ROHM BU27008 color sensor
-
-maintainers:
-  - Matti Vaittinen <mazziesaccount@gmail.com>
-
-description:
-  The ROHM BU27008 is a sensor with 5 photodiodes (red, green, blue, clear
-  and IR) with four configurable channels. Red and green being always
-  available and two out of the rest three (blue, clear, IR) can be
-  selected to be simultaneously measured. Typical application is adjusting
-  LCD backlight of TVs, mobile phones and tablet PCs.
-
-properties:
-  compatible:
-    const: rohm,bu27008
-
-  reg:
-    maxItems: 1
-
-  interrupts:
-    maxItems: 1
-
-  vdd-supply: true
-
-required:
-  - compatible
-  - reg
-
-additionalProperties: false
-
-examples:
-  - |
-    i2c {
-      #address-cells = <1>;
-      #size-cells = <0>;
-
-      light-sensor@38 {
-        compatible = "rohm,bu27008";
-        reg = <0x38>;
-      };
-    };
-
-...
diff --git a/dts/upstream/Bindings/iio/light/rohm,bu27010.yaml b/dts/upstream/Bindings/iio/light/rohm,bu27010.yaml
deleted file mode 100644
index bed42d5d0d9..00000000000
--- a/dts/upstream/Bindings/iio/light/rohm,bu27010.yaml
+++ /dev/null
@@ -1,50 +0,0 @@
-# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
-%YAML 1.2
----
-$id: http://devicetree.org/schemas/iio/light/rohm,bu27010.yaml#
-$schema: http://devicetree.org/meta-schemas/core.yaml#
-
-title: ROHM BU27010 color sensor
-
-maintainers:
-  - Matti Vaittinen <mazziesaccount@gmail.com>
-
-description: |
-  The ROHM BU27010 is a sensor with 6 photodiodes (red, green, blue, clear,
-  IR and flickering detection) with five configurable channels. Red, green
-  and flickering detection being always available and two out of the rest
-  three (blue, clear, IR) can be selected to be simultaneously measured.
-  Typical application is adjusting LCD/OLED backlight of TVs, mobile phones
-  and tablet PCs.
-
-properties:
-  compatible:
-    const: rohm,bu27010
-
-  reg:
-    maxItems: 1
-
-  interrupts:
-    maxItems: 1
-
-  vdd-supply: true
-
-required:
-  - compatible
-  - reg
-  - vdd-supply
-
-additionalProperties: false
-
-examples:
-  - |
-    i2c {
-      #address-cells = <1>;
-      #size-cells = <0>;
-
-      light-sensor@38 {
-        compatible = "rohm,bu27010";
-        reg = <0x38>;
-        vdd-supply = <&vdd>;
-      };
-    };
diff --git a/dts/upstream/Bindings/iio/light/ti,opt4060.yaml b/dts/upstream/Bindings/iio/light/ti,opt4060.yaml
new file mode 100644
index 00000000000..568fb2a9b7a
--- /dev/null
+++ b/dts/upstream/Bindings/iio/light/ti,opt4060.yaml
@@ -0,0 +1,51 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/light/ti,opt4060.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Texas Instruments OPT4060 RGBW Color Sensor
+
+maintainers:
+  - Per-Daniel Olsson <perdaniel.olsson@axis.com>
+
+description:
+  Texas Instrument RGBW high resolution color sensor over I2C.
+  https://www.ti.com/lit/gpn/opt4060
+
+properties:
+  compatible:
+    enum:
+      - ti,opt4060
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+
+  vdd-supply: true
+
+required:
+  - compatible
+  - reg
+  - vdd-supply
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/interrupt-controller/irq.h>
+    i2c {
+        #address-cells = <1>;
+        #size-cells = <0>;
+
+        light-sensor@44 {
+            compatible = "ti,opt4060";
+            reg = <0x44>;
+            vdd-supply = <&vdd_reg>;
+            interrupt-parent = <&gpio5>;
+            interrupts = <13 IRQ_TYPE_EDGE_FALLING>;
+        };
+    };
+...
diff --git a/dts/upstream/Bindings/iio/pressure/bmp085.yaml b/dts/upstream/Bindings/iio/pressure/bmp085.yaml
index cb201cecfa1..706b7e24f18 100644
--- a/dts/upstream/Bindings/iio/pressure/bmp085.yaml
+++ b/dts/upstream/Bindings/iio/pressure/bmp085.yaml
@@ -55,12 +55,16 @@ properties:
       If not set, defaults to push-pull configuration.
     type: boolean
 
+  spi-max-frequency:
+    maximum: 10000000
+
 required:
   - compatible
   - vddd-supply
   - vdda-supply
 
 allOf:
+  - $ref: /schemas/spi/spi-peripheral-props.yaml#
   - if:
       properties:
         compatible:
@@ -73,6 +77,16 @@ allOf:
     then:
       properties:
         interrupts: false
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - bosch,bmp085
+              - bosch,bmp180
+    then:
+      properties:
+        spi-max-frequency: false
 
 additionalProperties: false
 
@@ -93,3 +107,18 @@ examples:
             vdda-supply = <&bar>;
         };
     };
+  - |
+    # include <dt-bindings/gpio/gpio.h>
+    # include <dt-bindings/interrupt-controller/irq.h>
+    spi {
+        #address-cells = <1>;
+        #size-cells = <0>;
+        pressure@0 {
+            compatible = "bosch,bmp280";
+            reg = <0>;
+            spi-max-frequency = <10000000>;
+            reset-gpios = <&gpio0 26 GPIO_ACTIVE_LOW>;
+            vddd-supply = <&foo>;
+            vdda-supply = <&bar>;
+        };
+    };
diff --git a/dts/upstream/Bindings/input/mediatek,mt6779-keypad.yaml b/dts/upstream/Bindings/input/mediatek,mt6779-keypad.yaml
index 47aac8794b6..517a4ac1bea 100644
--- a/dts/upstream/Bindings/input/mediatek,mt6779-keypad.yaml
+++ b/dts/upstream/Bindings/input/mediatek,mt6779-keypad.yaml
@@ -26,6 +26,9 @@ properties:
       - items:
           - enum:
               - mediatek,mt6873-keypad
+              - mediatek,mt8183-keypad
+              - mediatek,mt8365-keypad
+              - mediatek,mt8516-keypad
           - const: mediatek,mt6779-keypad
 
   reg:
diff --git a/dts/upstream/Bindings/input/mediatek,pmic-keys.yaml b/dts/upstream/Bindings/input/mediatek,pmic-keys.yaml
index 60f09caa0e4..b95435bd6a9 100644
--- a/dts/upstream/Bindings/input/mediatek,pmic-keys.yaml
+++ b/dts/upstream/Bindings/input/mediatek,pmic-keys.yaml
@@ -25,6 +25,7 @@ properties:
   compatible:
     enum:
       - mediatek,mt6323-keys
+      - mediatek,mt6328-keys
       - mediatek,mt6331-keys
       - mediatek,mt6357-keys
       - mediatek,mt6358-keys
diff --git a/dts/upstream/Bindings/input/touchscreen/imagis,ist3038c.yaml b/dts/upstream/Bindings/input/touchscreen/imagis,ist3038c.yaml
index e24cbd96099..bd8ede3a4ad 100644
--- a/dts/upstream/Bindings/input/touchscreen/imagis,ist3038c.yaml
+++ b/dts/upstream/Bindings/input/touchscreen/imagis,ist3038c.yaml
@@ -19,6 +19,7 @@ properties:
       - imagis,ist3038
       - imagis,ist3038b
       - imagis,ist3038c
+      - imagis,ist3038h
 
   reg:
     maxItems: 1
diff --git a/dts/upstream/Bindings/interconnect/qcom,msm8998-bwmon.yaml b/dts/upstream/Bindings/interconnect/qcom,msm8998-bwmon.yaml
index 251410aabf3..83bcf0575cd 100644
--- a/dts/upstream/Bindings/interconnect/qcom,msm8998-bwmon.yaml
+++ b/dts/upstream/Bindings/interconnect/qcom,msm8998-bwmon.yaml
@@ -26,6 +26,7 @@ properties:
       - items:
           - enum:
               - qcom,qcm2290-cpu-bwmon
+              - qcom,qcs615-cpu-bwmon
               - qcom,qcs8300-cpu-bwmon
               - qcom,sa8775p-cpu-bwmon
               - qcom,sc7180-cpu-bwmon
@@ -37,10 +38,12 @@ properties:
               - qcom,sm8250-cpu-bwmon
               - qcom,sm8550-cpu-bwmon
               - qcom,sm8650-cpu-bwmon
+              - qcom,sm8750-cpu-bwmon
               - qcom,x1e80100-cpu-bwmon
           - const: qcom,sdm845-bwmon    # BWMON v4, unified register space
       - items:
           - enum:
+              - qcom,qcs615-llcc-bwmon
               - qcom,qcs8300-llcc-bwmon
               - qcom,sa8775p-llcc-bwmon
               - qcom,sc7180-llcc-bwmon
diff --git a/dts/upstream/Bindings/interconnect/qcom,osm-l3.yaml b/dts/upstream/Bindings/interconnect/qcom,osm-l3.yaml
index 21dae0b9281..4ac0863205b 100644
--- a/dts/upstream/Bindings/interconnect/qcom,osm-l3.yaml
+++ b/dts/upstream/Bindings/interconnect/qcom,osm-l3.yaml
@@ -33,6 +33,7 @@ properties:
               - qcom,sm6375-cpucp-l3
               - qcom,sm8250-epss-l3
               - qcom,sm8350-epss-l3
+              - qcom,sm8650-epss-l3
           - const: qcom,epss-l3
 
   reg:
diff --git a/dts/upstream/Bindings/interconnect/qcom,sm8750-rpmh.yaml b/dts/upstream/Bindings/interconnect/qcom,sm8750-rpmh.yaml
new file mode 100644
index 00000000000..a816acc301e
--- /dev/null
+++ b/dts/upstream/Bindings/interconnect/qcom,sm8750-rpmh.yaml
@@ -0,0 +1,136 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/interconnect/qcom,sm8750-rpmh.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm RPMh Network-On-Chip Interconnect on SM8750
+
+maintainers:
+  - Abel Vesa <abel.vesa@linaro.org>
+  - Neil Armstrong <neil.armstrong@linaro.org>
+
+description: |
+  RPMh interconnect providers support system bandwidth requirements through
+  RPMh hardware accelerators known as Bus Clock Manager (BCM). The provider is
+  able to communicate with the BCM through the Resource State Coordinator (RSC)
+  associated with each execution environment. Provider nodes must point to at
+  least one RPMh device child node pertaining to their RSC and each provider
+  can map to multiple RPMh resources.
+
+  See also:: include/dt-bindings/interconnect/qcom,sm8750-rpmh.h
+
+properties:
+  compatible:
+    enum:
+      - qcom,sm8750-aggre1-noc
+      - qcom,sm8750-aggre2-noc
+      - qcom,sm8750-clk-virt
+      - qcom,sm8750-cnoc-main
+      - qcom,sm8750-config-noc
+      - qcom,sm8750-gem-noc
+      - qcom,sm8750-lpass-ag-noc
+      - qcom,sm8750-lpass-lpiaon-noc
+      - qcom,sm8750-lpass-lpicx-noc
+      - qcom,sm8750-mc-virt
+      - qcom,sm8750-mmss-noc
+      - qcom,sm8750-nsp-noc
+      - qcom,sm8750-pcie-anoc
+      - qcom,sm8750-system-noc
+
+  reg:
+    maxItems: 1
+
+  clocks:
+    minItems: 1
+    maxItems: 2
+
+required:
+  - compatible
+
+allOf:
+  - $ref: qcom,rpmh-common.yaml#
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - qcom,sm8750-clk-virt
+              - qcom,sm8750-mc-virt
+    then:
+      properties:
+        reg: false
+    else:
+      required:
+        - reg
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - qcom,sm8750-pcie-anoc
+    then:
+      properties:
+        clocks:
+          items:
+            - description: aggre-NOC PCIe AXI clock
+            - description: cfg-NOC PCIe a-NOC AHB clock
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - qcom,sm8750-aggre1-noc
+    then:
+      properties:
+        clocks:
+          items:
+            - description: aggre UFS PHY AXI clock
+            - description: aggre USB3 PRIM AXI clock
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - qcom,sm8750-aggre2-noc
+    then:
+      properties:
+        clocks:
+          items:
+            - description: RPMH CC IPA clock
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - qcom,sm8750-aggre1-noc
+              - qcom,sm8750-aggre2-noc
+              - qcom,sm8750-pcie-anoc
+    then:
+      required:
+        - clocks
+    else:
+      properties:
+        clocks: false
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    clk_virt: interconnect-0 {
+      compatible = "qcom,sm8750-clk-virt";
+      #interconnect-cells = <2>;
+      qcom,bcm-voters = <&apps_bcm_voter>;
+    };
+
+    aggre1_noc: interconnect@16e0000 {
+      compatible = "qcom,sm8750-aggre1-noc";
+      reg = <0x016e0000 0x16400>;
+      #interconnect-cells = <2>;
+      clocks = <&gcc_phy_axi_clk>, <&gcc_prim_axi_clk>;
+      qcom,bcm-voters = <&apps_bcm_voter>;
+    };
diff --git a/dts/upstream/Bindings/interrupt-controller/arm,gic.yaml b/dts/upstream/Bindings/interrupt-controller/arm,gic.yaml
index a2846e49349..7173c4b5a22 100644
--- a/dts/upstream/Bindings/interrupt-controller/arm,gic.yaml
+++ b/dts/upstream/Bindings/interrupt-controller/arm,gic.yaml
@@ -110,8 +110,8 @@ properties:
 
   interrupts:
     description: Interrupt source of the parent interrupt controller on
-      secondary GICs, or VGIC maintenance interrupt on primary GIC (see
-      below).
+      secondary GICs, or VGIC maintenance interrupt on primary GIC (see "GICv2
+      with virtualization extensions" paragraph in the "reg" property).
     maxItems: 1
 
   cpu-offset:
diff --git a/dts/upstream/Bindings/interrupt-controller/aspeed,ast2400-vic.yaml b/dts/upstream/Bindings/interrupt-controller/aspeed,ast2400-vic.yaml
index 73e8b9a39bd..86516cd44b9 100644
--- a/dts/upstream/Bindings/interrupt-controller/aspeed,ast2400-vic.yaml
+++ b/dts/upstream/Bindings/interrupt-controller/aspeed,ast2400-vic.yaml
@@ -52,11 +52,11 @@ additionalProperties: false
 examples:
   - |
     interrupt-controller@1e6c0080 {
-         compatible = "aspeed,ast2400-vic";
-         reg = <0x1e6c0080 0x80>;
-         interrupt-controller;
-         #interrupt-cells = <1>;
-         valid-sources = <0xffffffff 0x0007ffff>;
+        compatible = "aspeed,ast2400-vic";
+        reg = <0x1e6c0080 0x80>;
+        interrupt-controller;
+        #interrupt-cells = <1>;
+        valid-sources = <0xffffffff 0x0007ffff>;
     };
 
 ...
diff --git a/dts/upstream/Bindings/interrupt-controller/brcm,bcm7120-l2-intc.yaml b/dts/upstream/Bindings/interrupt-controller/brcm,bcm7120-l2-intc.yaml
index 786f2426399..0fcbe304cd0 100644
--- a/dts/upstream/Bindings/interrupt-controller/brcm,bcm7120-l2-intc.yaml
+++ b/dts/upstream/Bindings/interrupt-controller/brcm,bcm7120-l2-intc.yaml
@@ -130,23 +130,23 @@ required:
 examples:
   - |
     irq0_intc: interrupt-controller@f0406800 {
-      compatible = "brcm,bcm7120-l2-intc";
-      interrupt-parent = <&intc>;
-      #interrupt-cells = <1>;
-      reg = <0xf0406800 0x8>;
-      interrupt-controller;
-      interrupts = <0x0 0x42 0x0>, <0x0 0x40 0x0>;
-      brcm,int-map-mask = <0xeb8>, <0x140>;
-      brcm,int-fwd-mask = <0x7>;
+        compatible = "brcm,bcm7120-l2-intc";
+        interrupt-parent = <&intc>;
+        #interrupt-cells = <1>;
+        reg = <0xf0406800 0x8>;
+        interrupt-controller;
+        interrupts = <0x0 0x42 0x0>, <0x0 0x40 0x0>;
+        brcm,int-map-mask = <0xeb8>, <0x140>;
+        brcm,int-fwd-mask = <0x7>;
     };
 
   - |
     irq1_intc: interrupt-controller@10000020 {
-       compatible = "brcm,bcm3380-l2-intc";
-       reg = <0x10000024 0x4>, <0x1000002c 0x4>,
-             <0x10000020 0x4>, <0x10000028 0x4>;
-       interrupt-controller;
-       #interrupt-cells = <1>;
-       interrupt-parent = <&cpu_intc>;
-       interrupts = <2>;
+        compatible = "brcm,bcm3380-l2-intc";
+        reg = <0x10000024 0x4>, <0x1000002c 0x4>,
+              <0x10000020 0x4>, <0x10000028 0x4>;
+        interrupt-controller;
+        #interrupt-cells = <1>;
+        interrupt-parent = <&cpu_intc>;
+        interrupts = <2>;
     };
diff --git a/dts/upstream/Bindings/interrupt-controller/microchip,lan966x-oic.yaml b/dts/upstream/Bindings/interrupt-controller/microchip,lan966x-oic.yaml
index b2adc717417..dca16e202da 100644
--- a/dts/upstream/Bindings/interrupt-controller/microchip,lan966x-oic.yaml
+++ b/dts/upstream/Bindings/interrupt-controller/microchip,lan966x-oic.yaml
@@ -14,9 +14,8 @@ allOf:
 
 description: |
   The Microchip LAN966x outband interrupt controller (OIC) maps the internal
-  interrupt sources of the LAN966x device to an external interrupt.
-  When the LAN966x device is used as a PCI device, the external interrupt is
-  routed to the PCI interrupt.
+  interrupt sources of the LAN966x device to a PCI interrupt when the LAN966x
+  device is used as a PCI device.
 
 properties:
   compatible:
diff --git a/dts/upstream/Bindings/interrupt-controller/qcom,pdc.yaml b/dts/upstream/Bindings/interrupt-controller/qcom,pdc.yaml
index a54da66a89e..f06b40f8877 100644
--- a/dts/upstream/Bindings/interrupt-controller/qcom,pdc.yaml
+++ b/dts/upstream/Bindings/interrupt-controller/qcom,pdc.yaml
@@ -26,6 +26,8 @@ properties:
   compatible:
     items:
       - enum:
+          - qcom,qcs615-pdc
+          - qcom,qcs8300-pdc
           - qcom,qdu1000-pdc
           - qcom,sa8255p-pdc
           - qcom,sa8775p-pdc
@@ -47,6 +49,7 @@ properties:
           - qcom,sm8450-pdc
           - qcom,sm8550-pdc
           - qcom,sm8650-pdc
+          - qcom,sm8750-pdc
           - qcom,x1e80100-pdc
       - const: qcom,pdc
 
diff --git a/dts/upstream/Bindings/interrupt-controller/riscv,imsics.yaml b/dts/upstream/Bindings/interrupt-controller/riscv,imsics.yaml
index 84976f17a4a..c23b5c09fdb 100644
--- a/dts/upstream/Bindings/interrupt-controller/riscv,imsics.yaml
+++ b/dts/upstream/Bindings/interrupt-controller/riscv,imsics.yaml
@@ -142,7 +142,7 @@ examples:
                             <&cpu2_intc 11>,
                             <&cpu3_intc 11>,
                             <&cpu4_intc 11>;
-      reg = <0x28000000 0x4000>;
+      reg = <0x24000000 0x4000>;
       interrupt-controller;
       #interrupt-cells = <0>;
       msi-controller;
diff --git a/dts/upstream/Bindings/interrupt-controller/sifive,plic-1.0.0.yaml b/dts/upstream/Bindings/interrupt-controller/sifive,plic-1.0.0.yaml
index 7e1451f9786..3dfe425909d 100644
--- a/dts/upstream/Bindings/interrupt-controller/sifive,plic-1.0.0.yaml
+++ b/dts/upstream/Bindings/interrupt-controller/sifive,plic-1.0.0.yaml
@@ -59,6 +59,7 @@ properties:
           - enum:
               - canaan,k210-plic
               - sifive,fu540-c000-plic
+              - spacemit,k1-plic
               - starfive,jh7100-plic
               - starfive,jh7110-plic
           - const: sifive,plic-1.0.0
diff --git a/dts/upstream/Bindings/interrupt-controller/ti,omap4-wugen-mpu b/dts/upstream/Bindings/interrupt-controller/ti,omap4-wugen-mpu.txt
index 422d6908f8b..422d6908f8b 100644
--- a/dts/upstream/Bindings/interrupt-controller/ti,omap4-wugen-mpu
+++ b/dts/upstream/Bindings/interrupt-controller/ti,omap4-wugen-mpu.txt
diff --git a/dts/upstream/Bindings/iommu/arm,smmu.yaml b/dts/upstream/Bindings/iommu/arm,smmu.yaml
index c1e11bc6b7a..032fdc27127 100644
--- a/dts/upstream/Bindings/iommu/arm,smmu.yaml
+++ b/dts/upstream/Bindings/iommu/arm,smmu.yaml
@@ -61,6 +61,7 @@ properties:
               - qcom,sm8450-smmu-500
               - qcom,sm8550-smmu-500
               - qcom,sm8650-smmu-500
+              - qcom,sm8750-smmu-500
               - qcom,x1e80100-smmu-500
           - const: qcom,smmu-500
           - const: arm,mmu-500
@@ -88,6 +89,7 @@ properties:
         items:
           - enum:
               - qcom,qcm2290-smmu-500
+              - qcom,qcs615-smmu-500
               - qcom,sa8255p-smmu-500
               - qcom,sa8775p-smmu-500
               - qcom,sar2130p-smmu-500
@@ -102,6 +104,7 @@ properties:
               - qcom,sm8450-smmu-500
               - qcom,sm8550-smmu-500
               - qcom,sm8650-smmu-500
+              - qcom,sm8750-smmu-500
               - qcom,x1e80100-smmu-500
           - const: qcom,adreno-smmu
           - const: qcom,smmu-500
@@ -122,6 +125,7 @@ properties:
               - qcom,msm8996-smmu-v2
               - qcom,sc7180-smmu-v2
               - qcom,sdm630-smmu-v2
+              - qcom,sdm670-smmu-v2
               - qcom,sdm845-smmu-v2
               - qcom,sm6350-smmu-v2
               - qcom,sm7150-smmu-v2
@@ -474,6 +478,7 @@ allOf:
           items:
             - enum:
                 - qcom,qcm2290-smmu-500
+                - qcom,qcs615-smmu-500
                 - qcom,sm6115-smmu-500
                 - qcom,sm6125-smmu-500
             - const: qcom,adreno-smmu
@@ -550,6 +555,23 @@ allOf:
             - description: GPU SNoC bus clock
             - description: GPU AHB clock
 
+  - if:
+      properties:
+        compatible:
+          items:
+            - const: qcom,sm8750-smmu-500
+            - const: qcom,adreno-smmu
+            - const: qcom,smmu-500
+            - const: arm,mmu-500
+    then:
+      properties:
+        clock-names:
+          items:
+            - const: hlos
+        clocks:
+          items:
+            - description: HLOS vote clock
+
   # Disallow clocks for all other platforms with specific compatibles
   - if:
       properties:
@@ -559,7 +581,6 @@ allOf:
               - cavium,smmu-v2
               - marvell,ap806-smmu-500
               - nvidia,smmu-500
-              - qcom,qcs615-smmu-500
               - qcom,qcs8300-smmu-500
               - qcom,qdu1000-smmu-500
               - qcom,sa8255p-smmu-500
diff --git a/dts/upstream/Bindings/iommu/qcom,iommu.yaml b/dts/upstream/Bindings/iommu/qcom,iommu.yaml
index f8cebc9e8cd..5ae9a628261 100644
--- a/dts/upstream/Bindings/iommu/qcom,iommu.yaml
+++ b/dts/upstream/Bindings/iommu/qcom,iommu.yaml
@@ -21,6 +21,7 @@ properties:
       - items:
           - enum:
               - qcom,msm8916-iommu
+              - qcom,msm8917-iommu
               - qcom,msm8953-iommu
           - const: qcom,msm-iommu-v1
       - items:
diff --git a/dts/upstream/Bindings/iommu/rockchip,iommu.yaml b/dts/upstream/Bindings/iommu/rockchip,iommu.yaml
index 621dde0e45d..6ce41d11ff5 100644
--- a/dts/upstream/Bindings/iommu/rockchip,iommu.yaml
+++ b/dts/upstream/Bindings/iommu/rockchip,iommu.yaml
@@ -25,6 +25,7 @@ properties:
           - rockchip,rk3568-iommu
       - items:
           - enum:
+              - rockchip,rk3576-iommu
               - rockchip,rk3588-iommu
           - const: rockchip,rk3568-iommu
 
diff --git a/dts/upstream/Bindings/leds/cznic,turris-omnia-leds.yaml b/dts/upstream/Bindings/leds/cznic,turris-omnia-leds.yaml
index 34ef5215c15..f52f6304c79 100644
--- a/dts/upstream/Bindings/leds/cznic,turris-omnia-leds.yaml
+++ b/dts/upstream/Bindings/leds/cznic,turris-omnia-leds.yaml
@@ -23,6 +23,12 @@ properties:
     description: I2C slave address of the microcontroller.
     maxItems: 1
 
+  interrupts:
+    description:
+      Specifier for the global LED brightness changed by front button press
+      interrupt.
+    maxItems: 1
+
   "#address-cells":
     const: 1
 
@@ -56,6 +62,7 @@ additionalProperties: false
 examples:
   - |
 
+    #include <dt-bindings/interrupt-controller/irq.h>
     #include <dt-bindings/leds/common.h>
 
     i2c {
@@ -65,6 +72,7 @@ examples:
         led-controller@2b {
             compatible = "cznic,turris-omnia-leds";
             reg = <0x2b>;
+            interrupts-extended = <&mcu 11 IRQ_TYPE_NONE>;
             #address-cells = <1>;
             #size-cells = <0>;
 
diff --git a/dts/upstream/Bindings/leds/leds-class-multicolor.yaml b/dts/upstream/Bindings/leds/leds-class-multicolor.yaml
index e850a889475..bb40bb9e036 100644
--- a/dts/upstream/Bindings/leds/leds-class-multicolor.yaml
+++ b/dts/upstream/Bindings/leds/leds-class-multicolor.yaml
@@ -27,7 +27,7 @@ properties:
     description: |
       For multicolor LED support this property should be defined as either
       LED_COLOR_ID_RGB or LED_COLOR_ID_MULTI which can be found in
-      include/linux/leds/common.h.
+      include/dt-bindings/leds/common.h.
     enum: [ 8, 9 ]
 
 required:
diff --git a/dts/upstream/Bindings/leds/leds-lp8860.txt b/dts/upstream/Bindings/leds/leds-lp8860.txt
deleted file mode 100644
index 8bb25749a3d..00000000000
--- a/dts/upstream/Bindings/leds/leds-lp8860.txt
+++ /dev/null
@@ -1,50 +0,0 @@
-* Texas Instruments - lp8860 4-Channel LED Driver
-
-The LP8860-Q1 is an high-efficiency LED
-driver with boost controller. It has 4 high-precision
-current sinks that can be controlled by a PWM input
-signal, a SPI/I2C master, or both.
-
-Required properties:
-	- compatible :
-		"ti,lp8860"
-	- reg : I2C slave address
-	- #address-cells : 1
-	- #size-cells : 0
-
-Optional properties:
-	- enable-gpios : gpio pin to enable (active high)/disable the device.
-	- vled-supply : LED supply
-
-Required child properties:
-	- reg : 0
-
-Optional child properties:
-	- function : see Documentation/devicetree/bindings/leds/common.txt
-	- color : see Documentation/devicetree/bindings/leds/common.txt
-	- label : see Documentation/devicetree/bindings/leds/common.txt (deprecated)
-	- linux,default-trigger :
-	   see Documentation/devicetree/bindings/leds/common.txt
-
-Example:
-
-#include <dt-bindings/leds/common.h>
-
-led-controller@2d {
-	compatible = "ti,lp8860";
-	#address-cells = <1>;
-	#size-cells = <0>;
-	reg = <0x2d>;
-	enable-gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>;
-	vled-supply = <&vbatt>;
-
-	led@0 {
-		reg = <0>;
-		function = LED_FUNCTION_BACKLIGHT;
-		color = <LED_COLOR_ID_WHITE>;
-		linux,default-trigger = "backlight";
-	};
-}
-
-For more product information please see the link below:
-https://www.ti.com/product/lp8860-q1
diff --git a/dts/upstream/Bindings/leds/qcom,spmi-flash-led.yaml b/dts/upstream/Bindings/leds/qcom,spmi-flash-led.yaml
index 1ba607685f5..bcf0ad4ea57 100644
--- a/dts/upstream/Bindings/leds/qcom,spmi-flash-led.yaml
+++ b/dts/upstream/Bindings/leds/qcom,spmi-flash-led.yaml
@@ -23,6 +23,7 @@ properties:
     items:
       - enum:
           - qcom,pm6150l-flash-led
+          - qcom,pm660l-flash-led
           - qcom,pm8150c-flash-led
           - qcom,pm8150l-flash-led
           - qcom,pm8350c-flash-led
diff --git a/dts/upstream/Bindings/leds/st,led1202.yaml b/dts/upstream/Bindings/leds/st,led1202.yaml
new file mode 100644
index 00000000000..f1e5e4efaa3
--- /dev/null
+++ b/dts/upstream/Bindings/leds/st,led1202.yaml
@@ -0,0 +1,132 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/leds/st,led1202.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: ST LED1202 LED controllers
+
+maintainers:
+  - Vicentiu Galanopulo <vicentiu.galanopulo@remote-tech.co.uk>
+
+description: |
+  The LED1202 is a 12-channel low quiescent current LED controller
+  programmable via I2C; The output current can be adjusted separately
+  for each channel by 8-bit analog and 12-bit digital dimming control.
+  Datasheet available at
+  https://www.st.com/en/power-management/led1202.html
+
+properties:
+  compatible:
+    const: st,led1202
+
+  reg:
+    maxItems: 1
+
+  "#address-cells":
+    const: 1
+
+  "#size-cells":
+    const: 0
+
+patternProperties:
+  "^led@[0-9a-f]$":
+    type: object
+    $ref: common.yaml#
+    unevaluatedProperties: false
+
+    properties:
+      reg:
+        minimum: 0
+        maximum: 11
+
+    required:
+      - reg
+
+required:
+  - compatible
+  - reg
+  - "#address-cells"
+  - "#size-cells"
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/leds/common.h>
+
+    i2c {
+        #address-cells = <1>;
+        #size-cells = <0>;
+
+        led-controller@58 {
+            compatible = "st,led1202";
+            reg = <0x58>;
+            #address-cells = <1>;
+            #size-cells = <0>;
+
+            led@0 {
+                reg = <0x0>;
+                function = LED_FUNCTION_STATUS;
+                color = <LED_COLOR_ID_RED>;
+                function-enumerator = <1>;
+            };
+
+            led@1 {
+                reg = <0x1>;
+                function = LED_FUNCTION_STATUS;
+                color = <LED_COLOR_ID_GREEN>;
+                function-enumerator = <2>;
+            };
+
+            led@2 {
+                reg = <0x2>;
+                function = LED_FUNCTION_STATUS;
+                color = <LED_COLOR_ID_BLUE>;
+                function-enumerator = <3>;
+            };
+
+            led@3 {
+                reg = <0x3>;
+                function = LED_FUNCTION_STATUS;
+                color = <LED_COLOR_ID_RED>;
+                function-enumerator = <4>;
+            };
+
+            led@4 {
+                reg = <0x4>;
+                function = LED_FUNCTION_STATUS;
+                color = <LED_COLOR_ID_GREEN>;
+                function-enumerator = <5>;
+            };
+
+            led@5 {
+                reg = <0x5>;
+                function = LED_FUNCTION_STATUS;
+                color = <LED_COLOR_ID_BLUE>;
+                function-enumerator = <6>;
+            };
+
+            led@6 {
+                reg = <0x6>;
+                function = LED_FUNCTION_STATUS;
+                color = <LED_COLOR_ID_RED>;
+                function-enumerator = <7>;
+            };
+
+            led@7 {
+                reg = <0x7>;
+                function = LED_FUNCTION_STATUS;
+                color = <LED_COLOR_ID_GREEN>;
+                function-enumerator = <8>;
+            };
+
+            led@8 {
+                reg = <0x8>;
+                function = LED_FUNCTION_STATUS;
+                color = <LED_COLOR_ID_BLUE>;
+                function-enumerator = <9>;
+            };
+        };
+    };
+...
diff --git a/dts/upstream/Bindings/leds/ti,lp8860.yaml b/dts/upstream/Bindings/leds/ti,lp8860.yaml
new file mode 100644
index 00000000000..0ee357b0266
--- /dev/null
+++ b/dts/upstream/Bindings/leds/ti,lp8860.yaml
@@ -0,0 +1,90 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/leds/ti,lp8860.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Texas Instruments - lp8860 4-Channel LED Driver
+
+maintainers:
+  - Andrew Davis <afd@ti.com>
+
+description: |
+  The LP8860-Q1 is an high-efficiency LED driver with boost controller.
+  It has 4 high-precision current sinks that can be controlled by a PWM input
+  signal, a SPI/I2C master, or both.
+
+  For more product information please see the link below:
+    https://www.ti.com/product/lp8860-q1
+
+properties:
+  compatible:
+    const: ti,lp8860
+
+  reg:
+    maxItems: 1
+    description: I2C slave address
+
+  "#address-cells":
+    const: 1
+
+  "#size-cells":
+    const: 0
+
+  enable-gpios:
+    maxItems: 1
+    description: GPIO pin to enable (active high) / disable the device
+
+  vled-supply:
+    description: LED supply
+
+patternProperties:
+  "^led(@[0-3])?$":
+    type: object
+    $ref: common.yaml#
+    unevaluatedProperties: false
+
+    properties:
+      reg:
+        description:
+          Index of the LED.
+        maxItems: 1
+
+      function: true
+      color: true
+      label: true
+      linux,default-trigger: true
+
+required:
+  - compatible
+  - reg
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/gpio/gpio.h>
+    #include <dt-bindings/leds/common.h>
+
+    i2c {
+        #address-cells = <1>;
+        #size-cells = <0>;
+
+        led-controller@2d {
+            compatible = "ti,lp8860";
+            #address-cells = <1>;
+            #size-cells = <0>;
+            reg = <0x2d>;
+            enable-gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>;
+            vled-supply = <&vbatt>;
+
+            led@0 {
+                reg = <0>;
+                function = LED_FUNCTION_BACKLIGHT;
+                color = <LED_COLOR_ID_WHITE>;
+                linux,default-trigger = "backlight";
+            };
+        };
+    };
+
+...
diff --git a/dts/upstream/Bindings/mailbox/google,gs101-mbox.yaml b/dts/upstream/Bindings/mailbox/google,gs101-mbox.yaml
new file mode 100644
index 00000000000..e249db4c1fb
--- /dev/null
+++ b/dts/upstream/Bindings/mailbox/google,gs101-mbox.yaml
@@ -0,0 +1,69 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright 2024 Linaro Ltd.
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mailbox/google,gs101-mbox.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Samsung Exynos Mailbox Controller
+
+maintainers:
+  - Tudor Ambarus <tudor.ambarus@linaro.org>
+
+description:
+  The Samsung Exynos mailbox controller, used on Google GS101 SoC, has 16 flag
+  bits for hardware interrupt generation and a shared register for passing
+  mailbox messages. When the controller is used by the ACPM interface
+  the shared register is ignored and the mailbox controller acts as a doorbell.
+  The controller just raises the interrupt to the firmware after the
+  ACPM interface has written the message to SRAM.
+
+properties:
+  compatible:
+    const: google,gs101-mbox
+
+  reg:
+    maxItems: 1
+
+  clocks:
+    maxItems: 1
+
+  clock-names:
+    items:
+      - const: pclk
+
+  interrupts:
+    description: IRQ line for the RX mailbox.
+    maxItems: 1
+
+  '#mbox-cells':
+    const: 0
+
+required:
+  - compatible
+  - reg
+  - clocks
+  - clock-names
+  - interrupts
+  - '#mbox-cells'
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+    #include <dt-bindings/clock/google,gs101.h>
+
+    soc {
+        #address-cells = <1>;
+        #size-cells = <1>;
+
+        ap2apm_mailbox: mailbox@17610000 {
+            compatible = "google,gs101-mbox";
+            reg = <0x17610000 0x1000>;
+            clocks = <&cmu_apm CLK_GOUT_APM_MAILBOX_APM_AP_PCLK>;
+            clock-names = "pclk";
+            interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH 0>;
+            #mbox-cells = <0>;
+        };
+    };
diff --git a/dts/upstream/Bindings/mailbox/microchip,sbi-ipc.yaml b/dts/upstream/Bindings/mailbox/microchip,sbi-ipc.yaml
new file mode 100644
index 00000000000..8ed67ea7c88
--- /dev/null
+++ b/dts/upstream/Bindings/mailbox/microchip,sbi-ipc.yaml
@@ -0,0 +1,123 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mailbox/microchip,sbi-ipc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Microchip Inter-processor communication (IPC) mailbox controller
+
+maintainers:
+  - Valentina Fernandez <valentina.fernandezalanis@microchip.com>
+
+description:
+  The Microchip Inter-processor Communication (IPC) facilitates
+  message passing between processors using an interrupt signaling
+  mechanism.
+
+properties:
+  compatible:
+    oneOf:
+      - description:
+          Intended for use by software running in supervisor privileged
+          mode (s-mode). This SBI interface is compatible with the Mi-V
+          Inter-hart Communication (IHC) IP.
+        const: microchip,sbi-ipc
+
+      - description:
+          Intended for use by the SBI implementation in machine mode
+          (m-mode), this compatible string is for the MIV_IHC Soft-IP.
+        const: microchip,miv-ihc-rtl-v2
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    minItems: 1
+    maxItems: 5
+
+  interrupt-names:
+    minItems: 1
+    maxItems: 5
+    items:
+      enum:
+        - hart-0
+        - hart-1
+        - hart-2
+        - hart-3
+        - hart-4
+        - hart-5
+
+  "#mbox-cells":
+    description: >
+      For "microchip,sbi-ipc", the cell represents the global "logical"
+      channel IDs. The meaning of channel IDs are platform firmware dependent.
+
+      For "microchip,miv-ihc-rtl-v2", the cell represents the physical
+      channel and does not vary based on the platform firmware.
+    const: 1
+
+  microchip,ihc-chan-disabled-mask:
+    description: >
+      Represents the enable/disable state of the bi-directional IHC
+      channels within the MIV-IHC IP configuration.
+
+      A bit set to '1' indicates that the corresponding channel is disabled,
+      and any read or write operations to that channel will return zero.
+
+      A bit set to '0' indicates that the corresponding channel is enabled
+      and will be accessible through its dedicated address range registers.
+
+      The actual enable/disable state of each channel is determined by the
+      IP block’s configuration.
+    $ref: /schemas/types.yaml#/definitions/uint16
+    maximum: 0x7fff
+    default: 0
+
+required:
+  - compatible
+  - interrupts
+  - interrupt-names
+  - "#mbox-cells"
+
+allOf:
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: microchip,sbi-ipc
+    then:
+      properties:
+        reg:
+          not: {}
+          description:
+            The 'microchip,sbi-ipc' operates in a programming model
+            that does not require memory-mapped I/O (MMIO) registers
+            since it uses SBI ecalls provided by the m-mode/firmware
+            SBI implementation to access hardware registers.
+        microchip,ihc-chan-disabled-mask: false
+    else:
+      required:
+        - reg
+        - microchip,ihc-chan-disabled-mask
+
+additionalProperties: false
+
+examples:
+  - |
+    mailbox {
+      compatible = "microchip,sbi-ipc";
+      interrupt-parent = <&plic>;
+      interrupts = <180>, <179>, <178>;
+      interrupt-names = "hart-1", "hart-2", "hart-3";
+      #mbox-cells = <1>;
+    };
+  - |
+    mailbox@50000000 {
+      compatible = "microchip,miv-ihc-rtl-v2";
+      microchip,ihc-chan-disabled-mask = /bits/ 16 <0>;
+      reg = <0x50000000 0x1c000>;
+      interrupt-parent = <&plic>;
+      interrupts = <180>, <179>, <178>;
+      interrupt-names = "hart-1", "hart-2", "hart-3";
+      #mbox-cells = <1>;
+    };
diff --git a/dts/upstream/Bindings/mailbox/qcom,apcs-kpss-global.yaml b/dts/upstream/Bindings/mailbox/qcom,apcs-kpss-global.yaml
index 9d2dfd85b20..78f68dacd02 100644
--- a/dts/upstream/Bindings/mailbox/qcom,apcs-kpss-global.yaml
+++ b/dts/upstream/Bindings/mailbox/qcom,apcs-kpss-global.yaml
@@ -20,6 +20,7 @@ properties:
           - enum:
               - qcom,ipq5018-apcs-apps-global
               - qcom,ipq5332-apcs-apps-global
+              - qcom,ipq5424-apcs-apps-global
               - qcom,ipq8074-apcs-apps-global
               - qcom,ipq9574-apcs-apps-global
           - const: qcom,ipq6018-apcs-apps-global
@@ -44,6 +45,7 @@ properties:
           - const: qcom,msm8994-apcs-kpss-global
       - items:
           - enum:
+              - qcom,qcs615-apss-shared
               - qcom,sc7180-apss-shared
               - qcom,sc8180x-apss-shared
               - qcom,sm8150-apss-shared
diff --git a/dts/upstream/Bindings/media/allwinner,sun50i-h6-vpu-g2.yaml b/dts/upstream/Bindings/media/allwinner,sun50i-h6-vpu-g2.yaml
index a4f06bbdfe4..8ba5177ac63 100644
--- a/dts/upstream/Bindings/media/allwinner,sun50i-h6-vpu-g2.yaml
+++ b/dts/upstream/Bindings/media/allwinner,sun50i-h6-vpu-g2.yaml
@@ -1,5 +1,4 @@
 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
-
 %YAML 1.2
 ---
 $id: http://devicetree.org/schemas/media/allwinner,sun50i-h6-vpu-g2.yaml#
diff --git a/dts/upstream/Bindings/media/amlogic,meson-ir-tx.yaml b/dts/upstream/Bindings/media/amlogic,meson-ir-tx.yaml
index 377acce9342..6da8a6aded2 100644
--- a/dts/upstream/Bindings/media/amlogic,meson-ir-tx.yaml
+++ b/dts/upstream/Bindings/media/amlogic,meson-ir-tx.yaml
@@ -1,5 +1,4 @@
 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
-
 %YAML 1.2
 ---
 $id: http://devicetree.org/schemas/media/amlogic,meson-ir-tx.yaml#
diff --git a/dts/upstream/Bindings/media/amphion,vpu.yaml b/dts/upstream/Bindings/media/amphion,vpu.yaml
index 9801de3ed84..5a920d9e78c 100644
--- a/dts/upstream/Bindings/media/amphion,vpu.yaml
+++ b/dts/upstream/Bindings/media/amphion,vpu.yaml
@@ -1,5 +1,4 @@
 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
-
 %YAML 1.2
 ---
 $id: http://devicetree.org/schemas/media/amphion,vpu.yaml#
diff --git a/dts/upstream/Bindings/media/fsl,imx6ull-pxp.yaml b/dts/upstream/Bindings/media/fsl,imx6ull-pxp.yaml
index 84a5e894ace..3f47744459a 100644
--- a/dts/upstream/Bindings/media/fsl,imx6ull-pxp.yaml
+++ b/dts/upstream/Bindings/media/fsl,imx6ull-pxp.yaml
@@ -1,5 +1,4 @@
 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
-
 %YAML 1.2
 ---
 $id: http://devicetree.org/schemas/media/fsl,imx6ull-pxp.yaml#
diff --git a/dts/upstream/Bindings/media/i2c/sony,imx290.yaml b/dts/upstream/Bindings/media/i2c/sony,imx290.yaml
index bf05ca48601..fa69bd21c8d 100644
--- a/dts/upstream/Bindings/media/i2c/sony,imx290.yaml
+++ b/dts/upstream/Bindings/media/i2c/sony,imx290.yaml
@@ -33,6 +33,8 @@ properties:
           - sony,imx290lqr # Colour
           - sony,imx290llr # Monochrome
           - sony,imx327lqr # Colour
+          - sony,imx462lqr # Colour
+          - sony,imx462llr # Monochrome
       - const: sony,imx290
         deprecated: true
 
diff --git a/dts/upstream/Bindings/media/mediatek,vcodec-decoder.yaml b/dts/upstream/Bindings/media/mediatek,vcodec-decoder.yaml
index b401c67e3ba..d726d141a43 100644
--- a/dts/upstream/Bindings/media/mediatek,vcodec-decoder.yaml
+++ b/dts/upstream/Bindings/media/mediatek,vcodec-decoder.yaml
@@ -1,5 +1,4 @@
 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
-
 %YAML 1.2
 ---
 $id: http://devicetree.org/schemas/media/mediatek,vcodec-decoder.yaml#
diff --git a/dts/upstream/Bindings/media/mediatek,vcodec-encoder.yaml b/dts/upstream/Bindings/media/mediatek,vcodec-encoder.yaml
index b45743d0a9e..110e8f5f1f9 100644
--- a/dts/upstream/Bindings/media/mediatek,vcodec-encoder.yaml
+++ b/dts/upstream/Bindings/media/mediatek,vcodec-encoder.yaml
@@ -1,5 +1,4 @@
 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
-
 %YAML 1.2
 ---
 $id: http://devicetree.org/schemas/media/mediatek,vcodec-encoder.yaml#
diff --git a/dts/upstream/Bindings/media/mediatek,vcodec-subdev-decoder.yaml b/dts/upstream/Bindings/media/mediatek,vcodec-subdev-decoder.yaml
index a500a585c69..5865e6f0be8 100644
--- a/dts/upstream/Bindings/media/mediatek,vcodec-subdev-decoder.yaml
+++ b/dts/upstream/Bindings/media/mediatek,vcodec-subdev-decoder.yaml
@@ -1,5 +1,4 @@
 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
-
 %YAML 1.2
 ---
 $id: http://devicetree.org/schemas/media/mediatek,vcodec-subdev-decoder.yaml#
diff --git a/dts/upstream/Bindings/media/microchip,sama5d4-vdec.yaml b/dts/upstream/Bindings/media/microchip,sama5d4-vdec.yaml
index 59b805ca47c..ede086d55ad 100644
--- a/dts/upstream/Bindings/media/microchip,sama5d4-vdec.yaml
+++ b/dts/upstream/Bindings/media/microchip,sama5d4-vdec.yaml
@@ -1,5 +1,4 @@
 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
-
 %YAML 1.2
 ---
 $id: http://devicetree.org/schemas/media/microchip,sama5d4-vdec.yaml#
@@ -36,12 +35,12 @@ additionalProperties: false
 
 examples:
   - |
-        #include <dt-bindings/clock/at91.h>
-        #include <dt-bindings/interrupt-controller/irq.h>
-
-        vdec0: vdec@300000 {
-                compatible = "microchip,sama5d4-vdec";
-                reg = <0x00300000 0x100000>;
-                interrupts = <19 IRQ_TYPE_LEVEL_HIGH 4>;
-                clocks = <&pmc PMC_TYPE_PERIPHERAL 19>;
-        };
+    #include <dt-bindings/clock/at91.h>
+    #include <dt-bindings/interrupt-controller/irq.h>
+
+    vdec@300000 {
+        compatible = "microchip,sama5d4-vdec";
+        reg = <0x00300000 0x100000>;
+        interrupts = <19 IRQ_TYPE_LEVEL_HIGH 4>;
+        clocks = <&pmc PMC_TYPE_PERIPHERAL 19>;
+    };
diff --git a/dts/upstream/Bindings/media/nxp,imx8-isi.yaml b/dts/upstream/Bindings/media/nxp,imx8-isi.yaml
index 4d5348d456a..f43b91984f0 100644
--- a/dts/upstream/Bindings/media/nxp,imx8-isi.yaml
+++ b/dts/upstream/Bindings/media/nxp,imx8-isi.yaml
@@ -21,6 +21,7 @@ properties:
     enum:
       - fsl,imx8mn-isi
       - fsl,imx8mp-isi
+      - fsl,imx8ulp-isi
       - fsl,imx93-isi
 
   reg:
@@ -75,6 +76,7 @@ allOf:
           contains:
             enum:
               - fsl,imx8mn-isi
+              - fsl,imx8ulp-isi
               - fsl,imx93-isi
     then:
       properties:
diff --git a/dts/upstream/Bindings/media/nxp,imx8mq-vpu.yaml b/dts/upstream/Bindings/media/nxp,imx8mq-vpu.yaml
index 3d58f02b0c5..19528262810 100644
--- a/dts/upstream/Bindings/media/nxp,imx8mq-vpu.yaml
+++ b/dts/upstream/Bindings/media/nxp,imx8mq-vpu.yaml
@@ -1,5 +1,4 @@
 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
-
 %YAML 1.2
 ---
 $id: http://devicetree.org/schemas/media/nxp,imx8mq-vpu.yaml#
@@ -44,26 +43,26 @@ additionalProperties: false
 
 examples:
   - |
-        #include <dt-bindings/clock/imx8mq-clock.h>
-        #include <dt-bindings/power/imx8mq-power.h>
-        #include <dt-bindings/interrupt-controller/arm-gic.h>
+    #include <dt-bindings/clock/imx8mq-clock.h>
+    #include <dt-bindings/power/imx8mq-power.h>
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
 
-        vpu_g1: video-codec@38300000 {
-                compatible = "nxp,imx8mq-vpu-g1";
-                reg = <0x38300000 0x10000>;
-                interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&clk IMX8MQ_CLK_VPU_G1_ROOT>;
-                power-domains = <&vpu_blk_ctrl IMX8MQ_VPUBLK_PD_G1>;
-        };
+    video-codec@38300000 {
+        compatible = "nxp,imx8mq-vpu-g1";
+        reg = <0x38300000 0x10000>;
+        interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+        clocks = <&clk IMX8MQ_CLK_VPU_G1_ROOT>;
+        power-domains = <&vpu_blk_ctrl IMX8MQ_VPUBLK_PD_G1>;
+    };
   - |
-        #include <dt-bindings/clock/imx8mq-clock.h>
-        #include <dt-bindings/power/imx8mq-power.h>
-        #include <dt-bindings/interrupt-controller/arm-gic.h>
+    #include <dt-bindings/clock/imx8mq-clock.h>
+    #include <dt-bindings/power/imx8mq-power.h>
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
 
-        vpu_g2: video-codec@38300000 {
-                compatible = "nxp,imx8mq-vpu-g2";
-                reg = <0x38310000 0x10000>;
-                interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&clk IMX8MQ_CLK_VPU_G2_ROOT>;
-                power-domains = <&vpu_blk_ctrl IMX8MQ_VPUBLK_PD_G2>;
-        };
+    video-codec@38300000 {
+        compatible = "nxp,imx8mq-vpu-g2";
+        reg = <0x38310000 0x10000>;
+        interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
+        clocks = <&clk IMX8MQ_CLK_VPU_G2_ROOT>;
+        power-domains = <&vpu_blk_ctrl IMX8MQ_VPUBLK_PD_G2>;
+    };
diff --git a/dts/upstream/Bindings/media/qcom,msm8916-camss.yaml b/dts/upstream/Bindings/media/qcom,msm8916-camss.yaml
index 9cc0a968a40..3469a43f00d 100644
--- a/dts/upstream/Bindings/media/qcom,msm8916-camss.yaml
+++ b/dts/upstream/Bindings/media/qcom,msm8916-camss.yaml
@@ -1,5 +1,4 @@
 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
-
 %YAML 1.2
 ---
 $id: http://devicetree.org/schemas/media/qcom,msm8916-camss.yaml#
diff --git a/dts/upstream/Bindings/media/qcom,msm8916-venus.yaml b/dts/upstream/Bindings/media/qcom,msm8916-venus.yaml
index 9410f13ca97..da140c2e3d3 100644
--- a/dts/upstream/Bindings/media/qcom,msm8916-venus.yaml
+++ b/dts/upstream/Bindings/media/qcom,msm8916-venus.yaml
@@ -45,6 +45,7 @@ properties:
     required:
       - compatible
 
+    deprecated: true
     additionalProperties: false
 
   video-encoder:
@@ -57,13 +58,12 @@ properties:
     required:
       - compatible
 
+    deprecated: true
     additionalProperties: false
 
 required:
   - compatible
   - iommus
-  - video-decoder
-  - video-encoder
 
 unevaluatedProperties: false
 
@@ -83,12 +83,4 @@ examples:
         power-domains = <&gcc VENUS_GDSC>;
         iommus = <&apps_iommu 5>;
         memory-region = <&venus_mem>;
-
-        video-decoder {
-            compatible = "venus-decoder";
-        };
-
-        video-encoder {
-            compatible = "venus-encoder";
-        };
     };
diff --git a/dts/upstream/Bindings/media/qcom,msm8996-camss.yaml b/dts/upstream/Bindings/media/qcom,msm8996-camss.yaml
index 5cb0e337ea6..644646de338 100644
--- a/dts/upstream/Bindings/media/qcom,msm8996-camss.yaml
+++ b/dts/upstream/Bindings/media/qcom,msm8996-camss.yaml
@@ -1,5 +1,4 @@
 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
-
 %YAML 1.2
 ---
 $id: http://devicetree.org/schemas/media/qcom,msm8996-camss.yaml#
diff --git a/dts/upstream/Bindings/media/qcom,sc7180-venus.yaml b/dts/upstream/Bindings/media/qcom,sc7180-venus.yaml
index 5cec1d077cd..83c4a5d95f0 100644
--- a/dts/upstream/Bindings/media/qcom,sc7180-venus.yaml
+++ b/dts/upstream/Bindings/media/qcom,sc7180-venus.yaml
@@ -70,6 +70,7 @@ properties:
     required:
       - compatible
 
+    deprecated: true
     additionalProperties: false
 
   video-encoder:
@@ -82,14 +83,13 @@ properties:
     required:
       - compatible
 
+    deprecated: true
     additionalProperties: false
 
 required:
   - compatible
   - power-domain-names
   - iommus
-  - video-decoder
-  - video-encoder
 
 unevaluatedProperties: false
 
@@ -114,12 +114,4 @@ examples:
                       "vcodec0_core", "vcodec0_bus";
         iommus = <&apps_smmu 0x0c00 0x60>;
         memory-region = <&venus_mem>;
-
-        video-decoder {
-            compatible = "venus-decoder";
-        };
-
-        video-encoder {
-            compatible = "venus-encoder";
-        };
     };
diff --git a/dts/upstream/Bindings/media/qcom,sc7280-camss.yaml b/dts/upstream/Bindings/media/qcom,sc7280-camss.yaml
new file mode 100644
index 00000000000..e11141b812a
--- /dev/null
+++ b/dts/upstream/Bindings/media/qcom,sc7280-camss.yaml
@@ -0,0 +1,425 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/qcom,sc7280-camss.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm SC7280 CAMSS ISP
+
+maintainers:
+  - Azam Sadiq Pasha Kapatrala Syed <akapatra@quicinc.com>
+  - Hariram Purushothaman <hariramp@quicinc.com>
+
+description:
+  The CAMSS IP is a CSI decoder and ISP present on Qualcomm platforms.
+
+properties:
+  compatible:
+    const: qcom,sc7280-camss
+
+  reg:
+    maxItems: 15
+
+  reg-names:
+    items:
+      - const: csid0
+      - const: csid1
+      - const: csid2
+      - const: csid_lite0
+      - const: csid_lite1
+      - const: csiphy0
+      - const: csiphy1
+      - const: csiphy2
+      - const: csiphy3
+      - const: csiphy4
+      - const: vfe0
+      - const: vfe1
+      - const: vfe2
+      - const: vfe_lite0
+      - const: vfe_lite1
+
+  clocks:
+    maxItems: 33
+
+  clock-names:
+    items:
+      - const: camnoc_axi
+      - const: cpas_ahb
+      - const: csiphy0
+      - const: csiphy0_timer
+      - const: csiphy1
+      - const: csiphy1_timer
+      - const: csiphy2
+      - const: csiphy2_timer
+      - const: csiphy3
+      - const: csiphy3_timer
+      - const: csiphy4
+      - const: csiphy4_timer
+      - const: gcc_camera_ahb
+      - const: gcc_cam_hf_axi
+      - const: icp_ahb
+      - const: vfe0
+      - const: vfe0_axi
+      - const: vfe0_cphy_rx
+      - const: vfe0_csid
+      - const: vfe1
+      - const: vfe1_axi
+      - const: vfe1_cphy_rx
+      - const: vfe1_csid
+      - const: vfe2
+      - const: vfe2_axi
+      - const: vfe2_cphy_rx
+      - const: vfe2_csid
+      - const: vfe_lite0
+      - const: vfe_lite0_cphy_rx
+      - const: vfe_lite0_csid
+      - const: vfe_lite1
+      - const: vfe_lite1_cphy_rx
+      - const: vfe_lite1_csid
+
+  interrupts:
+    maxItems: 15
+
+  interrupt-names:
+    items:
+      - const: csid0
+      - const: csid1
+      - const: csid2
+      - const: csid_lite0
+      - const: csid_lite1
+      - const: csiphy0
+      - const: csiphy1
+      - const: csiphy2
+      - const: csiphy3
+      - const: csiphy4
+      - const: vfe0
+      - const: vfe1
+      - const: vfe2
+      - const: vfe_lite0
+      - const: vfe_lite1
+
+  interconnects:
+    maxItems: 2
+
+  interconnect-names:
+    items:
+      - const: ahb
+      - const: hf_0
+
+  iommus:
+    maxItems: 1
+
+  power-domains:
+    items:
+      - description: IFE0 GDSC - Image Front End, Global Distributed Switch Controller.
+      - description: IFE1 GDSC - Image Front End, Global Distributed Switch Controller.
+      - description: IFE2 GDSC - Image Front End, Global Distributed Switch Controller.
+      - description: Titan GDSC - Titan ISP Block, Global Distributed Switch Controller.
+
+  power-domain-names:
+    items:
+      - const: ife0
+      - const: ife1
+      - const: ife2
+      - const: top
+
+  vdda-phy-supply:
+    description:
+      Phandle to a regulator supply to PHY core block.
+
+  vdda-pll-supply:
+    description:
+      Phandle to 1.8V regulator supply to PHY refclk pll block.
+
+  ports:
+    $ref: /schemas/graph.yaml#/properties/ports
+
+    description:
+      CSI input ports.
+
+    properties:
+      port@0:
+        $ref: /schemas/graph.yaml#/$defs/port-base
+        unevaluatedProperties: false
+        description:
+          Input port for receiving CSI data on CSIPHY 0.
+
+        properties:
+          endpoint:
+            $ref: video-interfaces.yaml#
+            unevaluatedProperties: false
+
+            properties:
+              data-lanes:
+                minItems: 1
+                maxItems: 4
+
+            required:
+              - data-lanes
+
+      port@1:
+        $ref: /schemas/graph.yaml#/$defs/port-base
+        unevaluatedProperties: false
+        description:
+          Input port for receiving CSI data on CSIPHY 1.
+
+        properties:
+          endpoint:
+            $ref: video-interfaces.yaml#
+            unevaluatedProperties: false
+
+            properties:
+              data-lanes:
+                minItems: 1
+                maxItems: 4
+
+            required:
+              - data-lanes
+
+      port@2:
+        $ref: /schemas/graph.yaml#/$defs/port-base
+        unevaluatedProperties: false
+        description:
+          Input port for receiving CSI data on CSIPHY 2.
+
+        properties:
+          endpoint:
+            $ref: video-interfaces.yaml#
+            unevaluatedProperties: false
+
+            properties:
+              data-lanes:
+                minItems: 1
+                maxItems: 4
+
+            required:
+              - data-lanes
+
+      port@3:
+        $ref: /schemas/graph.yaml#/$defs/port-base
+        unevaluatedProperties: false
+        description:
+          Input port for receiving CSI data on CSIPHY 3.
+
+        properties:
+          endpoint:
+            $ref: video-interfaces.yaml#
+            unevaluatedProperties: false
+
+            properties:
+              data-lanes:
+                minItems: 1
+                maxItems: 4
+
+            required:
+              - data-lanes
+
+      port@4:
+        $ref: /schemas/graph.yaml#/$defs/port-base
+        unevaluatedProperties: false
+        description:
+          Input port for receiving CSI data on CSIPHY 4.
+
+        properties:
+          endpoint:
+            $ref: video-interfaces.yaml#
+            unevaluatedProperties: false
+
+            properties:
+              data-lanes:
+                minItems: 1
+                maxItems: 4
+
+            required:
+              - data-lanes
+
+required:
+  - compatible
+  - reg
+  - reg-names
+  - clocks
+  - clock-names
+  - interrupts
+  - interrupt-names
+  - interconnects
+  - interconnect-names
+  - iommus
+  - power-domains
+  - power-domain-names
+  - vdda-phy-supply
+  - vdda-pll-supply
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/qcom,camcc-sc7280.h>
+    #include <dt-bindings/clock/qcom,gcc-sc7280.h>
+    #include <dt-bindings/interconnect/qcom,sc7280.h>
+    #include <dt-bindings/interconnect/qcom,icc.h>
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+    #include <dt-bindings/power/qcom-rpmpd.h>
+
+    soc {
+        #address-cells = <2>;
+        #size-cells = <2>;
+
+        isp@acb3000 {
+            compatible = "qcom,sc7280-camss";
+
+            reg = <0x0 0x0acb3000 0x0 0x1000>,
+                  <0x0 0x0acba000 0x0 0x1000>,
+                  <0x0 0x0acc1000 0x0 0x1000>,
+                  <0x0 0x0acc8000 0x0 0x1000>,
+                  <0x0 0x0accf000 0x0 0x1000>,
+                  <0x0 0x0ace0000 0x0 0x2000>,
+                  <0x0 0x0ace2000 0x0 0x2000>,
+                  <0x0 0x0ace4000 0x0 0x2000>,
+                  <0x0 0x0ace6000 0x0 0x2000>,
+                  <0x0 0x0ace8000 0x0 0x2000>,
+                  <0x0 0x0acaf000 0x0 0x4000>,
+                  <0x0 0x0acb6000 0x0 0x4000>,
+                  <0x0 0x0acbd000 0x0 0x4000>,
+                  <0x0 0x0acc4000 0x0 0x4000>,
+                  <0x0 0x0accb000 0x0 0x4000>;
+            reg-names = "csid0",
+                        "csid1",
+                        "csid2",
+                        "csid_lite0",
+                        "csid_lite1",
+                        "csiphy0",
+                        "csiphy1",
+                        "csiphy2",
+                        "csiphy3",
+                        "csiphy4",
+                        "vfe0",
+                        "vfe1",
+                        "vfe2",
+                        "vfe_lite0",
+                        "vfe_lite1";
+
+            clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>,
+                     <&camcc CAM_CC_CPAS_AHB_CLK>,
+                     <&camcc CAM_CC_CSIPHY0_CLK>,
+                     <&camcc CAM_CC_CSI0PHYTIMER_CLK>,
+                     <&camcc CAM_CC_CSIPHY1_CLK>,
+                     <&camcc CAM_CC_CSI1PHYTIMER_CLK>,
+                     <&camcc CAM_CC_CSIPHY2_CLK>,
+                     <&camcc CAM_CC_CSI2PHYTIMER_CLK>,
+                     <&camcc CAM_CC_CSIPHY3_CLK>,
+                     <&camcc CAM_CC_CSI3PHYTIMER_CLK>,
+                     <&camcc CAM_CC_CSIPHY4_CLK>,
+                     <&camcc CAM_CC_CSI4PHYTIMER_CLK>,
+                     <&gcc GCC_CAMERA_AHB_CLK>,
+                     <&gcc GCC_CAMERA_HF_AXI_CLK>,
+                     <&camcc CAM_CC_ICP_AHB_CLK>,
+                     <&camcc CAM_CC_IFE_0_CLK>,
+                     <&camcc CAM_CC_IFE_0_AXI_CLK>,
+                     <&camcc CAM_CC_IFE_0_CPHY_RX_CLK>,
+                     <&camcc CAM_CC_IFE_0_CSID_CLK>,
+                     <&camcc CAM_CC_IFE_1_CLK>,
+                     <&camcc CAM_CC_IFE_1_AXI_CLK>,
+                     <&camcc CAM_CC_IFE_1_CPHY_RX_CLK>,
+                     <&camcc CAM_CC_IFE_1_CSID_CLK>,
+                     <&camcc CAM_CC_IFE_2_CLK>,
+                     <&camcc CAM_CC_IFE_2_AXI_CLK>,
+                     <&camcc CAM_CC_IFE_2_CPHY_RX_CLK>,
+                     <&camcc CAM_CC_IFE_2_CSID_CLK>,
+                     <&camcc CAM_CC_IFE_LITE_0_CLK>,
+                     <&camcc CAM_CC_IFE_LITE_0_CPHY_RX_CLK>,
+                     <&camcc CAM_CC_IFE_LITE_0_CSID_CLK>,
+                     <&camcc CAM_CC_IFE_LITE_1_CLK>,
+                     <&camcc CAM_CC_IFE_LITE_1_CPHY_RX_CLK>,
+                     <&camcc CAM_CC_IFE_LITE_1_CSID_CLK>;
+            clock-names = "camnoc_axi",
+                          "cpas_ahb",
+                          "csiphy0",
+                          "csiphy0_timer",
+                          "csiphy1",
+                          "csiphy1_timer",
+                          "csiphy2",
+                          "csiphy2_timer",
+                          "csiphy3",
+                          "csiphy3_timer",
+                          "csiphy4",
+                          "csiphy4_timer",
+                          "gcc_camera_ahb",
+                          "gcc_cam_hf_axi",
+                          "icp_ahb",
+                          "vfe0",
+                          "vfe0_axi",
+                          "vfe0_cphy_rx",
+                          "vfe0_csid",
+                          "vfe1",
+                          "vfe1_axi",
+                          "vfe1_cphy_rx",
+                          "vfe1_csid",
+                          "vfe2",
+                          "vfe2_axi",
+                          "vfe2_cphy_rx",
+                          "vfe2_csid",
+                          "vfe_lite0",
+                          "vfe_lite0_cphy_rx",
+                          "vfe_lite0_csid",
+                          "vfe_lite1",
+                          "vfe_lite1_cphy_rx",
+                          "vfe_lite1_csid";
+
+            interrupts = <GIC_SPI 464 IRQ_TYPE_EDGE_RISING>,
+                         <GIC_SPI 466 IRQ_TYPE_EDGE_RISING>,
+                         <GIC_SPI 640 IRQ_TYPE_EDGE_RISING>,
+                         <GIC_SPI 468 IRQ_TYPE_EDGE_RISING>,
+                         <GIC_SPI 359 IRQ_TYPE_EDGE_RISING>,
+                         <GIC_SPI 477 IRQ_TYPE_EDGE_RISING>,
+                         <GIC_SPI 478 IRQ_TYPE_EDGE_RISING>,
+                         <GIC_SPI 479 IRQ_TYPE_EDGE_RISING>,
+                         <GIC_SPI 448 IRQ_TYPE_EDGE_RISING>,
+                         <GIC_SPI 122 IRQ_TYPE_EDGE_RISING>,
+                         <GIC_SPI 465 IRQ_TYPE_EDGE_RISING>,
+                         <GIC_SPI 467 IRQ_TYPE_EDGE_RISING>,
+                         <GIC_SPI 641 IRQ_TYPE_EDGE_RISING>,
+                         <GIC_SPI 469 IRQ_TYPE_EDGE_RISING>,
+                         <GIC_SPI 360 IRQ_TYPE_EDGE_RISING>;
+            interrupt-names = "csid0",
+                              "csid1",
+                              "csid2",
+                              "csid_lite0",
+                              "csid_lite1",
+                              "csiphy0",
+                              "csiphy1",
+                              "csiphy2",
+                              "csiphy3",
+                              "csiphy4",
+                              "vfe0",
+                              "vfe1",
+                              "vfe2",
+                              "vfe_lite0",
+                              "vfe_lite1";
+
+            interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+                             &cnoc2 SLAVE_CAMERA_CFG QCOM_ICC_TAG_ACTIVE_ONLY>,
+                            <&mmss_noc MASTER_CAMNOC_HF QCOM_ICC_TAG_ALWAYS
+                             &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+            interconnect-names = "ahb",
+                                 "hf_0";
+
+            iommus = <&apps_smmu 0x800 0x4e0>;
+
+            power-domains = <&camcc CAM_CC_IFE_0_GDSC>,
+                            <&camcc CAM_CC_IFE_1_GDSC>,
+                            <&camcc CAM_CC_IFE_2_GDSC>,
+                            <&camcc CAM_CC_TITAN_TOP_GDSC>;
+            power-domain-names = "ife0",
+                                 "ife1",
+                                 "ife2",
+                                 "top";
+
+            vdda-phy-supply = <&vreg_l10c_0p88>;
+            vdda-pll-supply = <&vreg_l6b_1p2>;
+
+            ports {
+                #address-cells = <1>;
+                #size-cells = <0>;
+            };
+        };
+    };
diff --git a/dts/upstream/Bindings/media/qcom,sc7280-venus.yaml b/dts/upstream/Bindings/media/qcom,sc7280-venus.yaml
index 10c334e6b3d..413c5b4ee65 100644
--- a/dts/upstream/Bindings/media/qcom,sc7280-venus.yaml
+++ b/dts/upstream/Bindings/media/qcom,sc7280-venus.yaml
@@ -68,6 +68,7 @@ properties:
     required:
       - compatible
 
+    deprecated: true
     additionalProperties: false
 
   video-encoder:
@@ -80,14 +81,13 @@ properties:
     required:
       - compatible
 
+    deprecated: true
     additionalProperties: false
 
 required:
   - compatible
   - power-domain-names
   - iommus
-  - video-decoder
-  - video-encoder
 
 unevaluatedProperties: false
 
@@ -125,14 +125,6 @@ examples:
 
         memory-region = <&video_mem>;
 
-        video-decoder {
-            compatible = "venus-decoder";
-        };
-
-        video-encoder {
-            compatible = "venus-encoder";
-        };
-
         video-firmware {
             iommus = <&apps_smmu 0x21a2 0x0>;
         };
diff --git a/dts/upstream/Bindings/media/qcom,sc8280xp-camss.yaml b/dts/upstream/Bindings/media/qcom,sc8280xp-camss.yaml
index c0bc3170987..9936f013241 100644
--- a/dts/upstream/Bindings/media/qcom,sc8280xp-camss.yaml
+++ b/dts/upstream/Bindings/media/qcom,sc8280xp-camss.yaml
@@ -328,26 +328,26 @@ examples:
             vdda-phy-supply = <&vreg_l6d>;
             vdda-pll-supply = <&vreg_l4d>;
 
-            interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>,
-                         <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>,
-                         <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>,
-                         <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>,
-                         <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>,
-                         <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>,
-                         <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>,
-                         <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>,
-                         <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>,
-                         <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>,
-                         <GIC_SPI 478 IRQ_TYPE_LEVEL_HIGH>,
-                         <GIC_SPI 479 IRQ_TYPE_LEVEL_HIGH>,
-                         <GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH>,
-                         <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>,
-                         <GIC_SPI 758 IRQ_TYPE_LEVEL_HIGH>,
-                         <GIC_SPI 759 IRQ_TYPE_LEVEL_HIGH>,
-                         <GIC_SPI 760 IRQ_TYPE_LEVEL_HIGH>,
-                         <GIC_SPI 761 IRQ_TYPE_LEVEL_HIGH>,
-                         <GIC_SPI 762 IRQ_TYPE_LEVEL_HIGH>,
-                         <GIC_SPI 764 IRQ_TYPE_LEVEL_HIGH>;
+            interrupts = <GIC_SPI 359 IRQ_TYPE_EDGE_RISING>,
+                         <GIC_SPI 360 IRQ_TYPE_EDGE_RISING>,
+                         <GIC_SPI 448 IRQ_TYPE_EDGE_RISING>,
+                         <GIC_SPI 464 IRQ_TYPE_EDGE_RISING>,
+                         <GIC_SPI 465 IRQ_TYPE_EDGE_RISING>,
+                         <GIC_SPI 466 IRQ_TYPE_EDGE_RISING>,
+                         <GIC_SPI 467 IRQ_TYPE_EDGE_RISING>,
+                         <GIC_SPI 468 IRQ_TYPE_EDGE_RISING>,
+                         <GIC_SPI 469 IRQ_TYPE_EDGE_RISING>,
+                         <GIC_SPI 477 IRQ_TYPE_EDGE_RISING>,
+                         <GIC_SPI 478 IRQ_TYPE_EDGE_RISING>,
+                         <GIC_SPI 479 IRQ_TYPE_EDGE_RISING>,
+                         <GIC_SPI 640 IRQ_TYPE_EDGE_RISING>,
+                         <GIC_SPI 641 IRQ_TYPE_EDGE_RISING>,
+                         <GIC_SPI 758 IRQ_TYPE_EDGE_RISING>,
+                         <GIC_SPI 759 IRQ_TYPE_EDGE_RISING>,
+                         <GIC_SPI 760 IRQ_TYPE_EDGE_RISING>,
+                         <GIC_SPI 761 IRQ_TYPE_EDGE_RISING>,
+                         <GIC_SPI 762 IRQ_TYPE_EDGE_RISING>,
+                         <GIC_SPI 764 IRQ_TYPE_EDGE_RISING>;
 
             interrupt-names = "csid1_lite",
                               "vfe_lite1",
diff --git a/dts/upstream/Bindings/media/qcom,sdm660-camss.yaml b/dts/upstream/Bindings/media/qcom,sdm660-camss.yaml
index 584106e275f..68d8670557f 100644
--- a/dts/upstream/Bindings/media/qcom,sdm660-camss.yaml
+++ b/dts/upstream/Bindings/media/qcom,sdm660-camss.yaml
@@ -1,5 +1,4 @@
 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
-
 %YAML 1.2
 ---
 $id: http://devicetree.org/schemas/media/qcom,sdm660-camss.yaml#
diff --git a/dts/upstream/Bindings/media/qcom,sdm845-camss.yaml b/dts/upstream/Bindings/media/qcom,sdm845-camss.yaml
index ec4380a0a03..289494f561e 100644
--- a/dts/upstream/Bindings/media/qcom,sdm845-camss.yaml
+++ b/dts/upstream/Bindings/media/qcom,sdm845-camss.yaml
@@ -1,5 +1,4 @@
 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
-
 %YAML 1.2
 ---
 $id: http://devicetree.org/schemas/media/qcom,sdm845-camss.yaml#
@@ -296,16 +295,16 @@ examples:
           "vfe_lite_cphy_rx",
           "vfe_lite_src";
 
-        interrupts = <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>,
-          <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>,
-          <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>,
-          <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>,
-          <GIC_SPI 478 IRQ_TYPE_LEVEL_HIGH>,
-          <GIC_SPI 479 IRQ_TYPE_LEVEL_HIGH>,
-          <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>,
-          <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>,
-          <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>,
-          <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>;
+        interrupts = <GIC_SPI 464 IRQ_TYPE_EDGE_RISING>,
+          <GIC_SPI 466 IRQ_TYPE_EDGE_RISING>,
+          <GIC_SPI 468 IRQ_TYPE_EDGE_RISING>,
+          <GIC_SPI 477 IRQ_TYPE_EDGE_RISING>,
+          <GIC_SPI 478 IRQ_TYPE_EDGE_RISING>,
+          <GIC_SPI 479 IRQ_TYPE_EDGE_RISING>,
+          <GIC_SPI 448 IRQ_TYPE_EDGE_RISING>,
+          <GIC_SPI 465 IRQ_TYPE_EDGE_RISING>,
+          <GIC_SPI 467 IRQ_TYPE_EDGE_RISING>,
+          <GIC_SPI 469 IRQ_TYPE_EDGE_RISING>;
 
         interrupt-names = "csid0",
           "csid1",
diff --git a/dts/upstream/Bindings/media/qcom,sdm845-venus-v2.yaml b/dts/upstream/Bindings/media/qcom,sdm845-venus-v2.yaml
index 6228fd2b324..c839cb1ebc0 100644
--- a/dts/upstream/Bindings/media/qcom,sdm845-venus-v2.yaml
+++ b/dts/upstream/Bindings/media/qcom,sdm845-venus-v2.yaml
@@ -70,6 +70,7 @@ properties:
     required:
       - compatible
 
+    deprecated: true
     additionalProperties: false
 
   video-core1:
@@ -82,14 +83,13 @@ properties:
     required:
       - compatible
 
+    deprecated: true
     additionalProperties: false
 
 required:
   - compatible
   - power-domain-names
   - iommus
-  - video-core0
-  - video-core1
 
 unevaluatedProperties: false
 
@@ -119,12 +119,4 @@ examples:
         iommus = <&apps_smmu 0x10a0 0x8>,
                  <&apps_smmu 0x10b0 0x0>;
         memory-region = <&venus_mem>;
-
-        video-core0 {
-            compatible = "venus-decoder";
-        };
-
-        video-core1 {
-            compatible = "venus-encoder";
-        };
     };
diff --git a/dts/upstream/Bindings/media/qcom,sm8250-camss.yaml b/dts/upstream/Bindings/media/qcom,sm8250-camss.yaml
index fa5073c0fd1..a372d991e65 100644
--- a/dts/upstream/Bindings/media/qcom,sm8250-camss.yaml
+++ b/dts/upstream/Bindings/media/qcom,sm8250-camss.yaml
@@ -1,5 +1,4 @@
 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
-
 %YAML 1.2
 ---
 $id: http://devicetree.org/schemas/media/qcom,sm8250-camss.yaml#
@@ -329,20 +328,20 @@ examples:
             vdda-phy-supply = <&vreg_l5a_0p88>;
             vdda-pll-supply = <&vreg_l9a_1p2>;
 
-            interrupts = <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>,
-                         <GIC_SPI 478 IRQ_TYPE_LEVEL_HIGH>,
-                         <GIC_SPI 479 IRQ_TYPE_LEVEL_HIGH>,
-                         <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>,
-                         <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
-                         <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
-                         <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>,
-                         <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>,
-                         <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>,
-                         <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>,
-                         <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>,
-                         <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>,
-                         <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>,
-                         <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
+            interrupts = <GIC_SPI 477 IRQ_TYPE_EDGE_RISING>,
+                         <GIC_SPI 478 IRQ_TYPE_EDGE_RISING>,
+                         <GIC_SPI 479 IRQ_TYPE_EDGE_RISING>,
+                         <GIC_SPI 448 IRQ_TYPE_EDGE_RISING>,
+                         <GIC_SPI 86 IRQ_TYPE_EDGE_RISING>,
+                         <GIC_SPI 89 IRQ_TYPE_EDGE_RISING>,
+                         <GIC_SPI 464 IRQ_TYPE_EDGE_RISING>,
+                         <GIC_SPI 466 IRQ_TYPE_EDGE_RISING>,
+                         <GIC_SPI 468 IRQ_TYPE_EDGE_RISING>,
+                         <GIC_SPI 359 IRQ_TYPE_EDGE_RISING>,
+                         <GIC_SPI 465 IRQ_TYPE_EDGE_RISING>,
+                         <GIC_SPI 467 IRQ_TYPE_EDGE_RISING>,
+                         <GIC_SPI 469 IRQ_TYPE_EDGE_RISING>,
+                         <GIC_SPI 360 IRQ_TYPE_EDGE_RISING>;
             interrupt-names = "csiphy0",
                               "csiphy1",
                               "csiphy2",
diff --git a/dts/upstream/Bindings/media/qcom,sm8250-venus.yaml b/dts/upstream/Bindings/media/qcom,sm8250-venus.yaml
index f66033ae8b5..da54493220c 100644
--- a/dts/upstream/Bindings/media/qcom,sm8250-venus.yaml
+++ b/dts/upstream/Bindings/media/qcom,sm8250-venus.yaml
@@ -73,6 +73,7 @@ properties:
     required:
       - compatible
 
+    deprecated: true
     additionalProperties: false
 
   video-encoder:
@@ -85,6 +86,7 @@ properties:
     required:
       - compatible
 
+    deprecated: true
     additionalProperties: false
 
 required:
@@ -95,8 +97,6 @@ required:
   - iommus
   - resets
   - reset-names
-  - video-decoder
-  - video-encoder
 
 unevaluatedProperties: false
 
@@ -132,12 +132,4 @@ examples:
         resets = <&gcc GCC_VIDEO_AXI0_CLK_ARES>,
                  <&videocc VIDEO_CC_MVS0C_CLK_ARES>;
         reset-names = "bus", "core";
-
-        video-decoder {
-            compatible = "venus-decoder";
-        };
-
-        video-encoder {
-            compatible = "venus-encoder";
-        };
     };
diff --git a/dts/upstream/Bindings/media/rockchip,rk3568-vepu.yaml b/dts/upstream/Bindings/media/rockchip,rk3568-vepu.yaml
index 947ad699cc5..d246f5d3842 100644
--- a/dts/upstream/Bindings/media/rockchip,rk3568-vepu.yaml
+++ b/dts/upstream/Bindings/media/rockchip,rk3568-vepu.yaml
@@ -1,5 +1,4 @@
 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
-
 %YAML 1.2
 ---
 $id: http://devicetree.org/schemas/media/rockchip,rk3568-vepu.yaml#
diff --git a/dts/upstream/Bindings/media/rockchip-vpu.yaml b/dts/upstream/Bindings/media/rockchip-vpu.yaml
index 719aeb2dc59..8c250163408 100644
--- a/dts/upstream/Bindings/media/rockchip-vpu.yaml
+++ b/dts/upstream/Bindings/media/rockchip-vpu.yaml
@@ -1,5 +1,4 @@
 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
-
 %YAML 1.2
 ---
 $id: http://devicetree.org/schemas/media/rockchip-vpu.yaml#
@@ -92,18 +91,18 @@ additionalProperties: false
 
 examples:
   - |
-        #include <dt-bindings/clock/rk3288-cru.h>
-        #include <dt-bindings/interrupt-controller/arm-gic.h>
-        #include <dt-bindings/power/rk3288-power.h>
-
-        vpu: video-codec@ff9a0000 {
-                compatible = "rockchip,rk3288-vpu";
-                reg = <0xff9a0000 0x800>;
-                interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
-                             <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
-                interrupt-names = "vepu", "vdpu";
-                clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
-                clock-names = "aclk", "hclk";
-                power-domains = <&power RK3288_PD_VIDEO>;
-                iommus = <&vpu_mmu>;
-        };
+    #include <dt-bindings/clock/rk3288-cru.h>
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+    #include <dt-bindings/power/rk3288-power.h>
+
+    video-codec@ff9a0000 {
+        compatible = "rockchip,rk3288-vpu";
+        reg = <0xff9a0000 0x800>;
+        interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
+                     <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+        interrupt-names = "vepu", "vdpu";
+        clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
+        clock-names = "aclk", "hclk";
+        power-domains = <&power RK3288_PD_VIDEO>;
+        iommus = <&vpu_mmu>;
+    };
diff --git a/dts/upstream/Bindings/media/st,stm32-dcmipp.yaml b/dts/upstream/Bindings/media/st,stm32-dcmipp.yaml
index 87731f3ce7b..7b03a77adbc 100644
--- a/dts/upstream/Bindings/media/st,stm32-dcmipp.yaml
+++ b/dts/upstream/Bindings/media/st,stm32-dcmipp.yaml
@@ -12,7 +12,9 @@ maintainers:
 
 properties:
   compatible:
-    const: st,stm32mp13-dcmipp
+    enum:
+      - st,stm32mp13-dcmipp
+      - st,stm32mp25-dcmipp
 
   reg:
     maxItems: 1
@@ -21,11 +23,24 @@ properties:
     maxItems: 1
 
   clocks:
-    maxItems: 1
+    items:
+      - description: bus clock
+      - description: csi clock
+    minItems: 1
+
+  clock-names:
+    items:
+      - const: kclk
+      - const: mclk
+    minItems: 1
 
   resets:
     maxItems: 1
 
+  access-controllers:
+    minItems: 1
+    maxItems: 2
+
   port:
     $ref: /schemas/graph.yaml#/$defs/port-base
     unevaluatedProperties: false
@@ -39,7 +54,7 @@ properties:
 
         properties:
           bus-type:
-            enum: [5, 6]
+            enum: [4, 5, 6]
             default: 5
 
           bus-width:
@@ -50,9 +65,6 @@ properties:
           hsync-active: true
           vsync-active: true
 
-        required:
-          - pclk-sample
-
 required:
   - compatible
   - reg
@@ -61,6 +73,35 @@ required:
   - resets
   - port
 
+allOf:
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - st,stm32mp13-dcmipp
+    then:
+      properties:
+        clocks:
+          maxItems: 1
+
+        clock-names:
+          maxItems: 1
+
+        port:
+          properties:
+            endpoint:
+              properties:
+                bus-type:
+                  enum: [5, 6]
+    else:
+      properties:
+        clocks:
+          minItems: 2
+
+        clock-names:
+          minItems: 2
+
 additionalProperties: false
 
 examples:
diff --git a/dts/upstream/Bindings/media/st,stm32mp25-csi.yaml b/dts/upstream/Bindings/media/st,stm32mp25-csi.yaml
new file mode 100644
index 00000000000..33bedfe4192
--- /dev/null
+++ b/dts/upstream/Bindings/media/st,stm32mp25-csi.yaml
@@ -0,0 +1,125 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/st,stm32mp25-csi.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: STMicroelectronics STM32 CSI controller
+
+description:
+  The STM32 CSI controller allows connecting a CSI based
+  camera to the DCMIPP camera pipeline.
+
+maintainers:
+  - Alain Volmat <alain.volmat@foss.st.com>
+
+properties:
+  compatible:
+    enum:
+      - st,stm32mp25-csi
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+
+  clocks:
+    maxItems: 3
+
+  clock-names:
+    items:
+      - const: pclk
+      - const: txesc
+      - const: csi2phy
+
+  resets:
+    maxItems: 1
+
+  vdd-supply:
+    description: Digital core power supply (0.91V)
+
+  vdda18-supply:
+    description: System analog power supply (1.8V)
+
+  access-controllers:
+    minItems: 1
+    maxItems: 2
+
+  ports:
+    $ref: /schemas/graph.yaml#/properties/ports
+
+    properties:
+      port@0:
+        $ref: /schemas/graph.yaml#/$defs/port-base
+        unevaluatedProperties: false
+        description:
+          Input port node
+
+        properties:
+          endpoint:
+            $ref: video-interfaces.yaml#
+            unevaluatedProperties: false
+
+            properties:
+              data-lanes:
+                minItems: 1
+                items:
+                  - const: 1
+                  - const: 2
+
+            required:
+              - data-lanes
+
+      port@1:
+        $ref: /schemas/graph.yaml#/properties/port
+        description:
+          Output port node
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - clocks
+  - clock-names
+  - resets
+  - ports
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/st,stm32mp25-rcc.h>
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+    #include <dt-bindings/media/video-interfaces.h>
+    #include <dt-bindings/reset/st,stm32mp25-rcc.h>
+    csi@48020000 {
+        compatible = "st,stm32mp25-csi";
+        reg = <0x48020000 0x2000>;
+        interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
+        resets = <&rcc CSI_R>;
+        clocks = <&rcc CK_KER_CSI>, <&rcc CK_KER_CSITXESC>, <&rcc CK_KER_CSIPHY>;
+        clock-names = "pclk", "txesc", "csi2phy";
+
+        ports {
+            #address-cells = <1>;
+            #size-cells = <0>;
+            port@0 {
+                reg = <0>;
+                endpoint {
+                    remote-endpoint = <&imx335_ep>;
+                    data-lanes = <1 2>;
+                    bus-type = <MEDIA_BUS_TYPE_CSI2_DPHY>;
+                };
+            };
+
+            port@1 {
+                reg = <1>;
+                endpoint {
+                    remote-endpoint = <&dcmipp_0>;
+                };
+            };
+        };
+    };
+
+...
diff --git a/dts/upstream/Bindings/media/video-interfaces.yaml b/dts/upstream/Bindings/media/video-interfaces.yaml
index 26e3e7d7c67..038e85b45be 100644
--- a/dts/upstream/Bindings/media/video-interfaces.yaml
+++ b/dts/upstream/Bindings/media/video-interfaces.yaml
@@ -210,6 +210,27 @@ properties:
       lane-polarities property is omitted, the value must be interpreted as 0
       (normal). This property is valid for serial busses only.
 
+  line-orders:
+    $ref: /schemas/types.yaml#/definitions/uint32-array
+    minItems: 1
+    maxItems: 8
+    items:
+      enum:
+        - 0 # ABC
+        - 1 # ACB
+        - 2 # BAC
+        - 3 # BCA
+        - 4 # CAB
+        - 5 # CBA
+    description:
+      An array of line orders of the CSI-2 C-PHY data lanes. The order of the
+      lanes are the same as in data-lanes property. Valid values are 0-5 as
+      defined in the MIPI Discovery and Configuration (DisCo) Specification for
+      Imaging. The length of the array must be the same length as the
+      data-lanes property. If the line-orders property is omitted, the value
+      shall be interpreted as 0 (ABC). This property is valid for CSI-2 C-PHY
+      busses only.
+
   strobe:
     $ref: /schemas/types.yaml#/definitions/uint32
     enum: [ 0, 1 ]
diff --git a/dts/upstream/Bindings/memory-controllers/qca,ath79-ddr-controller.yaml b/dts/upstream/Bindings/memory-controllers/qca,ath79-ddr-controller.yaml
index 0c511ab906b..8b937f90a1f 100644
--- a/dts/upstream/Bindings/memory-controllers/qca,ath79-ddr-controller.yaml
+++ b/dts/upstream/Bindings/memory-controllers/qca,ath79-ddr-controller.yaml
@@ -52,10 +52,3 @@ examples:
 
         #qca,ddr-wb-channel-cells = <1>;
     };
-
-    interrupt-controller {
-        // ...
-        qca,ddr-wb-channel-interrupts = <2>, <3>, <4>, <5>;
-        qca,ddr-wb-channels = <&ddr_ctrl 3>, <&ddr_ctrl 2>,
-                              <&ddr_ctrl 0>, <&ddr_ctrl 1>;
-    };
diff --git a/dts/upstream/Bindings/mfd/atmel,at91sam9260-gpbr.yaml b/dts/upstream/Bindings/mfd/atmel,at91sam9260-gpbr.yaml
new file mode 100644
index 00000000000..f805545aa62
--- /dev/null
+++ b/dts/upstream/Bindings/mfd/atmel,at91sam9260-gpbr.yaml
@@ -0,0 +1,44 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mfd/atmel,at91sam9260-gpbr.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Microchip AT91 General Purpose Backup Registers
+
+maintainers:
+  - Nicolas Ferre <nicolas.ferre@microchip.com>
+
+description:
+  The system controller embeds 256 bits of General Purpose Backup
+  registers organized as 8 32-bit registers.
+
+properties:
+  compatible:
+    oneOf:
+      - items:
+          - enum:
+              - atmel,at91sam9260-gpbr
+          - const: syscon
+      - items:
+          - enum:
+              - microchip,sam9x60-gpbr
+              - microchip,sam9x7-gpbr
+          - const: atmel,at91sam9260-gpbr
+          - const: syscon
+
+  reg:
+    maxItems: 1
+
+required:
+  - compatible
+  - reg
+
+additionalProperties: false
+
+examples:
+  - |
+    syscon@fffffd50 {
+        compatible = "atmel,at91sam9260-gpbr", "syscon";
+        reg = <0xfffffd50 0x10>;
+    };
diff --git a/dts/upstream/Bindings/mfd/atmel,at91sam9260-matrix.yaml b/dts/upstream/Bindings/mfd/atmel,at91sam9260-matrix.yaml
new file mode 100644
index 00000000000..447b3a3edbf
--- /dev/null
+++ b/dts/upstream/Bindings/mfd/atmel,at91sam9260-matrix.yaml
@@ -0,0 +1,52 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mfd/atmel,at91sam9260-matrix.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Microchip AT91 Bus Matrix
+
+maintainers:
+  - Nicolas Ferre <nicolas.ferre@microchip.com>
+
+description:
+  The Bus Matrix (MATRIX) implements a multi-layer AHB, based on the
+  AHB-Lite protocol, that enables parallel access paths between multiple
+  masters and slaves in a system, thus increasing the overall bandwidth.
+
+properties:
+  compatible:
+    oneOf:
+      - items:
+          - enum:
+              - atmel,at91sam9260-matrix
+              - atmel,at91sam9261-matrix
+              - atmel,at91sam9263-matrix
+              - atmel,at91sam9rl-matrix
+              - atmel,at91sam9g45-matrix
+              - atmel,at91sam9n12-matrix
+              - atmel,at91sam9x5-matrix
+              - atmel,sama5d3-matrix
+          - const: syscon
+      - items:
+          - enum:
+              - microchip,sam9x60-matrix
+              - microchip,sam9x7-matrix
+          - const: atmel,at91sam9x5-matrix
+          - const: syscon
+
+  reg:
+    maxItems: 1
+
+required:
+  - compatible
+  - reg
+
+additionalProperties: false
+
+examples:
+  - |
+    syscon@ffffec00 {
+        compatible = "atmel,sama5d3-matrix", "syscon";
+        reg = <0xffffec00 0x200>;
+    };
diff --git a/dts/upstream/Bindings/mfd/atmel-gpbr.txt b/dts/upstream/Bindings/mfd/atmel-gpbr.txt
deleted file mode 100644
index 3c989d1760a..00000000000
--- a/dts/upstream/Bindings/mfd/atmel-gpbr.txt
+++ /dev/null
@@ -1,18 +0,0 @@
-* Device tree bindings for Atmel GPBR (General Purpose Backup Registers)
-
-The GPBR are a set of battery-backed registers.
-
-Required properties:
-- compatible:		Should be one of the following:
-			"atmel,at91sam9260-gpbr", "syscon"
-			"microchip,sam9x60-gpbr", "syscon"
-			"microchip,sam9x7-gpbr", "microchip,sam9x60-gpbr", "syscon"
-- reg:			contains offset/length value of the GPBR memory
-			region.
-
-Example:
-
-gpbr: gpbr@fffffd50 {
-	compatible = "atmel,at91sam9260-gpbr", "syscon";
-	reg = <0xfffffd50 0x10>;
-};
diff --git a/dts/upstream/Bindings/mfd/atmel-matrix.txt b/dts/upstream/Bindings/mfd/atmel-matrix.txt
deleted file mode 100644
index 6e5f83614e8..00000000000
--- a/dts/upstream/Bindings/mfd/atmel-matrix.txt
+++ /dev/null
@@ -1,26 +0,0 @@
-* Device tree bindings for Atmel Bus Matrix
-
-The Bus Matrix registers are used to configure Atmel SoCs internal bus
-behavior (master/slave priorities, undefined burst length type, ...)
-
-Required properties:
-- compatible:		Should be one of the following
-			"atmel,at91sam9260-matrix", "syscon"
-			"atmel,at91sam9261-matrix", "syscon"
-			"atmel,at91sam9263-matrix", "syscon"
-			"atmel,at91sam9rl-matrix", "syscon"
-			"atmel,at91sam9g45-matrix", "syscon"
-			"atmel,at91sam9n12-matrix", "syscon"
-			"atmel,at91sam9x5-matrix", "syscon"
-			"atmel,sama5d3-matrix", "syscon"
-			"microchip,sam9x60-matrix", "syscon"
-			"microchip,sam9x7-matrix", "atmel,at91sam9x5-matrix", "syscon"
-- reg:			Contains offset/length value of the Bus Matrix
-			memory region.
-
-Example:
-
-matrix: matrix@ffffec00 {
-	compatible = "atmel,sama5d3-matrix", "syscon";
-	reg = <0xffffec00 0x200>;
-};
diff --git a/dts/upstream/Bindings/mfd/google,cros-ec.yaml b/dts/upstream/Bindings/mfd/google,cros-ec.yaml
index aac8819bd00..50f45709006 100644
--- a/dts/upstream/Bindings/mfd/google,cros-ec.yaml
+++ b/dts/upstream/Bindings/mfd/google,cros-ec.yaml
@@ -108,9 +108,6 @@ properties:
   pwm:
     $ref: /schemas/pwm/google,cros-ec-pwm.yaml#
 
-  kbd-led-backlight:
-    $ref: /schemas/chrome/google,cros-kbd-led-backlight.yaml#
-
   keyboard-controller:
     $ref: /schemas/input/google,cros-ec-keyb.yaml#
 
diff --git a/dts/upstream/Bindings/mfd/mediatek,mt6397.yaml b/dts/upstream/Bindings/mfd/mediatek,mt6397.yaml
index 86451f151a6..6a89b479d10 100644
--- a/dts/upstream/Bindings/mfd/mediatek,mt6397.yaml
+++ b/dts/upstream/Bindings/mfd/mediatek,mt6397.yaml
@@ -36,6 +36,7 @@ properties:
       - enum:
           - mediatek,mt6323
           - mediatek,mt6331 # "mediatek,mt6331" for PMIC MT6331 and MT6332.
+          - mediatek,mt6328
           - mediatek,mt6358
           - mediatek,mt6359
           - mediatek,mt6397
@@ -88,6 +89,7 @@ properties:
         oneOf:
           - enum:
               - mediatek,mt6323-regulator
+              - mediatek,mt6328-regulator
               - mediatek,mt6358-regulator
               - mediatek,mt6359-regulator
               - mediatek,mt6397-regulator
diff --git a/dts/upstream/Bindings/mfd/qcom,tcsr.yaml b/dts/upstream/Bindings/mfd/qcom,tcsr.yaml
index 79add913e35..a503b67f2db 100644
--- a/dts/upstream/Bindings/mfd/qcom,tcsr.yaml
+++ b/dts/upstream/Bindings/mfd/qcom,tcsr.yaml
@@ -42,6 +42,7 @@ properties:
           - qcom,tcsr-apq8064
           - qcom,tcsr-apq8084
           - qcom,tcsr-ipq5332
+          - qcom,tcsr-ipq5424
           - qcom,tcsr-ipq6018
           - qcom,tcsr-ipq8064
           - qcom,tcsr-ipq8074
diff --git a/dts/upstream/Bindings/mfd/qnap,ts433-mcu.yaml b/dts/upstream/Bindings/mfd/qnap,ts433-mcu.yaml
new file mode 100644
index 00000000000..877078ac172
--- /dev/null
+++ b/dts/upstream/Bindings/mfd/qnap,ts433-mcu.yaml
@@ -0,0 +1,42 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mfd/qnap,ts433-mcu.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: QNAP NAS on-board Microcontroller
+
+maintainers:
+  - Heiko Stuebner <heiko@sntech.de>
+
+description:
+  QNAP embeds a microcontroller on their NAS devices adding system feature
+  as PWM Fan control, additional LEDs, power button status and more.
+
+properties:
+  compatible:
+    enum:
+      - qnap,ts433-mcu
+
+patternProperties:
+  "^fan-[0-9]+$":
+    $ref: /schemas/hwmon/fan-common.yaml#
+    unevaluatedProperties: false
+
+required:
+  - compatible
+
+additionalProperties: false
+
+examples:
+  - |
+    uart {
+      mcu {
+        compatible = "qnap,ts433-mcu";
+
+        fan-0 {
+          #cooling-cells = <2>;
+          cooling-levels = <0 64 89 128 166 204 221 238>;
+        };
+      };
+    };
diff --git a/dts/upstream/Bindings/mfd/rohm,bd71815-pmic.yaml b/dts/upstream/Bindings/mfd/rohm,bd71815-pmic.yaml
index bb81307dc11..4fc78efaa55 100644
--- a/dts/upstream/Bindings/mfd/rohm,bd71815-pmic.yaml
+++ b/dts/upstream/Bindings/mfd/rohm,bd71815-pmic.yaml
@@ -50,15 +50,15 @@ properties:
     minimum: 0
     maximum: 1
 
-  rohm,charger-sense-resistor-ohms:
-    minimum: 10000000
-    maximum: 50000000
+  rohm,charger-sense-resistor-micro-ohms:
+    minimum: 10000
+    maximum: 50000
     description: |
-      BD71827 and BD71828 have SAR ADC for measuring charging currents.
-      External sense resistor (RSENSE in data sheet) should be used. If
-      something other but 30MOhm resistor is used the resistance value
-      should be given here in Ohms.
-    default: 30000000
+      BD71815 has SAR ADC for measuring charging currents. External sense
+      resistor (RSENSE in data sheet) should be used. If something other
+      but a 30 mOhm resistor is used the resistance value should be given
+      here in micro Ohms.
+    default: 30000
 
   regulators:
     $ref: /schemas/regulator/rohm,bd71815-regulator.yaml
@@ -67,7 +67,7 @@ properties:
 
   gpio-reserved-ranges:
     description: |
-      Usage of BD71828 GPIO pins can be changed via OTP. This property can be
+      Usage of BD71815 GPIO pins can be changed via OTP. This property can be
       used to mark the pins which should not be configured for GPIO. Please see
       the ../gpio/gpio.txt for more information.
 
@@ -113,7 +113,7 @@ examples:
             gpio-controller;
             #gpio-cells = <2>;
 
-            rohm,charger-sense-resistor-ohms = <10000000>;
+            rohm,charger-sense-resistor-micro-ohms = <10000>;
 
             regulators {
                 buck1: buck1 {
diff --git a/dts/upstream/Bindings/mfd/sprd,sc2731.yaml b/dts/upstream/Bindings/mfd/sprd,sc2731.yaml
index 8beec7e8e4c..b023e1ef8d3 100644
--- a/dts/upstream/Bindings/mfd/sprd,sc2731.yaml
+++ b/dts/upstream/Bindings/mfd/sprd,sc2731.yaml
@@ -67,15 +67,7 @@ patternProperties:
 
   "^efuse@[0-9a-f]+$":
     type: object
-    additionalProperties: true
-    properties:
-      compatible:
-        enum:
-          - sprd,sc2720-efuse
-          - sprd,sc2721-efuse
-          - sprd,sc2723-efuse
-          - sprd,sc2730-efuse
-          - sprd,sc2731-efuse
+    $ref: /schemas/nvmem/sprd,sc2731-efuse.yaml#
 
   "^fuel-gauge@[0-9a-f]+$":
     type: object
@@ -199,7 +191,7 @@ examples:
           };
         };
 
-        adc@480 {
+        pmic_adc: adc@480 {
           compatible = "sprd,sc2731-adc";
           reg = <0x480>;
           interrupt-parent = <&sc2731_pmic>;
diff --git a/dts/upstream/Bindings/mfd/syscon.yaml b/dts/upstream/Bindings/mfd/syscon.yaml
index b414de4fa77..4d67ff26d44 100644
--- a/dts/upstream/Bindings/mfd/syscon.yaml
+++ b/dts/upstream/Bindings/mfd/syscon.yaml
@@ -27,7 +27,7 @@ select:
     compatible:
       contains:
         enum:
-          - al,alpine-sysfabric-servic
+          - al,alpine-sysfabric-service
           - allwinner,sun8i-a83t-system-controller
           - allwinner,sun8i-h3-system-controller
           - allwinner,sun8i-v3s-system-controller
@@ -103,6 +103,7 @@ select:
           - rockchip,rk3288-qos
           - rockchip,rk3368-qos
           - rockchip,rk3399-qos
+          - rockchip,rk3562-qos
           - rockchip,rk3568-qos
           - rockchip,rk3576-qos
           - rockchip,rk3588-qos
@@ -201,6 +202,7 @@ properties:
           - rockchip,rk3288-qos
           - rockchip,rk3368-qos
           - rockchip,rk3399-qos
+          - rockchip,rk3562-qos
           - rockchip,rk3568-qos
           - rockchip,rk3576-qos
           - rockchip,rk3588-qos
@@ -213,6 +215,7 @@ properties:
           - ti,am625-dss-oldi-io-ctrl
           - ti,am62p-cpsw-mac-efuse
           - ti,am654-dss-oldi-io-ctrl
+          - ti,j784s4-acspcie-proxy-ctrl
           - ti,j784s4-pcie-ctrl
           - ti,keystone-pllctrl
       - const: syscon
diff --git a/dts/upstream/Bindings/misc/lwn,bk4-spi.yaml b/dts/upstream/Bindings/misc/lwn,bk4-spi.yaml
new file mode 100644
index 00000000000..73fbf672e22
--- /dev/null
+++ b/dts/upstream/Bindings/misc/lwn,bk4-spi.yaml
@@ -0,0 +1,54 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/misc/lwn,bk4-spi.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Liebherr's BK4 external SPI controller
+
+maintainers:
+  - Lukasz Majewski <lukma@denx.de>
+
+description: |
+  Liebherr's BK4 external SPI controller is a device which handles data
+  acquisition from compatible industrial peripherals.
+  The SPI is used for data and management purposes in both master and
+  slave modes.
+
+allOf:
+  - $ref: /schemas/spi/spi-peripheral-props.yaml#
+
+properties:
+  compatible:
+    const: lwn,bk4-spi
+
+  reg:
+    maxItems: 1
+
+  spi-max-frequency:
+    maximum: 30000000
+
+  fsl,spi-cs-sck-delay: true
+
+  fsl,spi-sck-cs-delay: true
+
+required:
+  - compatible
+  - spi-max-frequency
+
+additionalProperties: false
+
+examples:
+  - |
+    spi {
+        #address-cells = <1>;
+        #size-cells = <0>;
+
+        spidev@0 {
+            compatible = "lwn,bk4-spi";
+            reg = <0>;
+            spi-max-frequency = <30000000>;
+            fsl,spi-cs-sck-delay = <200>;
+            fsl,spi-sck-cs-delay = <400>;
+        };
+    };
diff --git a/dts/upstream/Bindings/misc/lwn-bk4.txt b/dts/upstream/Bindings/misc/lwn-bk4.txt
deleted file mode 100644
index d6a8c188c08..00000000000
--- a/dts/upstream/Bindings/misc/lwn-bk4.txt
+++ /dev/null
@@ -1,26 +0,0 @@
-* Liebherr's BK4 controller external SPI
-
-A device which handles data acquisition from compatible industrial
-peripherals.
-The SPI is used for data and management purposes in both master and
-slave modes.
-
-Required properties:
-
-- compatible : Should be "lwn,bk4"
-
-Required SPI properties:
-
-- reg : Should be address of the device chip select within
-  the controller.
-
-- spi-max-frequency : Maximum SPI clocking speed of device in Hz, should be
-  30MHz at most for the Liebherr's BK4 external bus.
-
-Example:
-
-spidev0: spi@0 {
-	compatible = "lwn,bk4";
-	spi-max-frequency = <30000000>;
-	reg = <0>;
-};
diff --git a/dts/upstream/Bindings/mmc/amlogic,meson-mx-sdio.txt b/dts/upstream/Bindings/mmc/amlogic,meson-mx-sdio.txt
deleted file mode 100644
index 8765c605e6b..00000000000
--- a/dts/upstream/Bindings/mmc/amlogic,meson-mx-sdio.txt
+++ /dev/null
@@ -1,54 +0,0 @@
-* Amlogic Meson6, Meson8 and Meson8b SDIO/MMC controller
-
-The highspeed MMC host controller on Amlogic SoCs provides an interface
-for MMC, SD, SDIO and SDHC types of memory cards.
-
-Supported maximum speeds are the ones of the eMMC standard 4.41 as well
-as the speed of SD standard 2.0.
-
-The hardware provides an internal "mux" which allows up to three slots
-to be controlled. Only one slot can be accessed at a time.
-
-Required properties:
- - compatible : must be one of
-	- "amlogic,meson8-sdio"
-	- "amlogic,meson8b-sdio"
-	along with the generic "amlogic,meson-mx-sdio"
- - reg : mmc controller base registers
- - interrupts : mmc controller interrupt
- - #address-cells : must be 1
- - size-cells : must be 0
- - clocks : phandle to clock providers
- - clock-names : must contain "core" and "clkin"
-
-Required child nodes:
-A node for each slot provided by the MMC controller is required.
-NOTE: due to a driver limitation currently only one slot (= child node)
-      is supported!
-
-Required properties on each child node (= slot):
- - compatible : must be "mmc-slot" (see mmc.txt within this directory)
- - reg : the slot (or "port") ID
-
-Optional properties on each child node (= slot):
- - bus-width : must be 1 or 4 (8-bit bus is not supported)
- - for cd and all other additional generic mmc parameters
-   please refer to mmc.txt within this directory
-
-Examples:
-	mmc@c1108c20 {
-		compatible = "amlogic,meson8-sdio", "amlogic,meson-mx-sdio";
-		reg = <0xc1108c20 0x20>;
-		interrupts = <0 28 1>;
-		#address-cells = <1>;
-		#size-cells = <0>;
-		clocks = <&clkc CLKID_SDIO>, <&clkc CLKID_CLK81>;
-		clock-names = "core", "clkin";
-
-		slot@1 {
-			compatible = "mmc-slot";
-			reg = <1>;
-
-			bus-width = <4>;
-		};
-	};
diff --git a/dts/upstream/Bindings/mmc/amlogic,meson-mx-sdio.yaml b/dts/upstream/Bindings/mmc/amlogic,meson-mx-sdio.yaml
new file mode 100644
index 00000000000..022682a977c
--- /dev/null
+++ b/dts/upstream/Bindings/mmc/amlogic,meson-mx-sdio.yaml
@@ -0,0 +1,94 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mmc/amlogic,meson-mx-sdio.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Amlogic Meson6, Meson8 and Meson8b SDIO/MMC controller
+
+description: |
+  The highspeed MMC host controller on Amlogic SoCs provides an interface
+  for MMC, SD, SDIO and SDHC types of memory cards.
+
+  Supported maximum speeds are the ones of the eMMC standard 4.41 as well
+  as the speed of SD standard 2.0.
+
+  The hardware provides an internal "mux" which allows up to three slots
+  to be controlled. Only one slot can be accessed at a time.
+
+maintainers:
+  - Neil Armstrong <neil.armstrong@linaro.org>
+
+properties:
+  compatible:
+    items:
+      - enum:
+          - amlogic,meson8-sdio
+          - amlogic,meson8b-sdio
+      - const: amlogic,meson-mx-sdio
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+
+  clocks:
+    maxItems: 2
+
+  clock-names:
+    items:
+      - const: core
+      - const: clkin
+
+  "#address-cells":
+    const: 1
+
+  "#size-cells":
+    const: 0
+
+patternProperties:
+  "slot@[0-2]$":
+    $ref: mmc-slot.yaml#
+    description:
+      A node for each slot provided by the MMC controller
+
+    properties:
+      reg:
+        enum: [0, 1, 2]
+
+      bus-width:
+        enum: [1, 4]
+
+    unevaluatedProperties: false
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - clocks
+  - clock-names
+  - "#address-cells"
+  - "#size-cells"
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/interrupt-controller/irq.h>
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+    mmc@c1108c20 {
+        compatible = "amlogic,meson8-sdio", "amlogic,meson-mx-sdio";
+        reg = <0xc1108c20 0x20>;
+        interrupts = <GIC_SPI 28 IRQ_TYPE_EDGE_RISING>;
+        clocks = <&clk_core>, <&clk_in>;
+        clock-names = "core", "clkin";
+        #address-cells = <1>;
+        #size-cells = <0>;
+
+        slot@1 {
+            compatible = "mmc-slot";
+            reg = <1>;
+            bus-width = <4>;
+        };
+    };
diff --git a/dts/upstream/Bindings/mmc/atmel,sama5d2-sdhci.yaml b/dts/upstream/Bindings/mmc/atmel,sama5d2-sdhci.yaml
index 8c8ade88e8f..ba75623b777 100644
--- a/dts/upstream/Bindings/mmc/atmel,sama5d2-sdhci.yaml
+++ b/dts/upstream/Bindings/mmc/atmel,sama5d2-sdhci.yaml
@@ -22,6 +22,7 @@ properties:
       - items:
           - enum:
               - microchip,sam9x7-sdhci
+              - microchip,sama7d65-sdhci
               - microchip,sama7g5-sdhci
           - const: microchip,sam9x60-sdhci
 
diff --git a/dts/upstream/Bindings/mmc/marvell,xenon-sdhci.yaml b/dts/upstream/Bindings/mmc/marvell,xenon-sdhci.yaml
index cfe6237716f..3f48d8292d5 100644
--- a/dts/upstream/Bindings/mmc/marvell,xenon-sdhci.yaml
+++ b/dts/upstream/Bindings/mmc/marvell,xenon-sdhci.yaml
@@ -38,15 +38,9 @@ properties:
 
   reg:
     minItems: 1
-    maxItems: 2
-    description: |
-      For "marvell,armada-3700-sdhci", two register areas.  The first one
-      for Xenon IP register. The second one for the Armada 3700 SoC PHY PAD
-      Voltage Control register.  Please follow the examples with compatible
-      "marvell,armada-3700-sdhci" in below.
-      Please also check property marvell,pad-type in below.
-
-      For other compatible strings, one register area for Xenon IP.
+    items:
+      - description: Xenon IP registers
+      - description: Armada 3700 SoC PHY PAD Voltage Control register
 
   clocks:
     minItems: 1
@@ -61,6 +55,17 @@ properties:
   interrupts:
     maxItems: 1
 
+  marvell,pad-type:
+    $ref: /schemas/types.yaml#/definitions/string
+    enum:
+      - sd
+      - fixed-1-8v
+    description:
+      Type of Armada 3700 SoC PHY PAD Voltage Controller register. If "sd" is
+      selected, SoC PHY PAD is set as 3.3V at the beginning and is switched to
+      1.8V when later in higher speed mode. If "fixed-1-8v" is selected, SoC PHY
+      PAD is fixed 1.8V, such as for eMMC.
+
   marvell,xenon-sdhc-id:
     $ref: /schemas/types.yaml#/definitions/uint32
     minimum: 0
@@ -147,27 +152,18 @@ allOf:
     then:
       properties:
         reg:
-          items:
-            - description: Xenon IP registers
-            - description: Armada 3700 SoC PHY PAD Voltage Control register
-
-        marvell,pad-type:
-          $ref: /schemas/types.yaml#/definitions/string
-          enum:
-            - sd
-            - fixed-1-8v
-          description: |
-            Type of Armada 3700 SoC PHY PAD Voltage Controller register.
-            If "sd" is selected, SoC PHY PAD is set as 3.3V at the beginning
-            and is switched to 1.8V when later in higher speed mode.
-            If "fixed-1-8v" is selected, SoC PHY PAD is fixed 1.8V, such as for
-            eMMC.
-            Please follow the examples with compatible
-            "marvell,armada-3700-sdhci" in below.
+          minItems: 2
 
       required:
         - marvell,pad-type
 
+    else:
+      properties:
+        reg:
+          maxItems: 1
+
+        marvell,pad-type: false
+
   - if:
       properties:
         compatible:
diff --git a/dts/upstream/Bindings/mmc/mmc-controller-common.yaml b/dts/upstream/Bindings/mmc/mmc-controller-common.yaml
new file mode 100644
index 00000000000..9a723543975
--- /dev/null
+++ b/dts/upstream/Bindings/mmc/mmc-controller-common.yaml
@@ -0,0 +1,357 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mmc/mmc-controller-common.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MMC Controller & Slots Common Properties
+
+maintainers:
+  - Ulf Hansson <ulf.hansson@linaro.org>
+
+description:
+  These properties are common to multiple MMC host controllers and the
+  possible slots or ports for multi-slot controllers.
+
+properties:
+  "#address-cells":
+    const: 1
+    description:
+      The cell is the SDIO function number if a function subnode is used.
+
+  "#size-cells":
+    const: 0
+
+  # Card Detection.
+  # If none of these properties are supplied, the host native card
+  # detect will be used. Only one of them should be provided.
+
+  broken-cd:
+    $ref: /schemas/types.yaml#/definitions/flag
+    description:
+      There is no card detection available; polling must be used.
+
+  cd-gpios:
+    maxItems: 1
+    description:
+      The card detection will be done using the GPIO provided.
+
+  non-removable:
+    $ref: /schemas/types.yaml#/definitions/flag
+    description:
+      Non-removable slot (like eMMC); assume always present.
+
+  # *NOTE* on CD and WP polarity. To use common for all SD/MMC host
+  # controllers line polarity properties, we have to fix the meaning
+  # of the "normal" and "inverted" line levels. We choose to follow
+  # the SDHCI standard, which specifies both those lines as "active
+  # low." Therefore, using the "cd-inverted" property means, that the
+  # CD line is active high, i.e. it is high, when a card is
+  # inserted. Similar logic applies to the "wp-inverted" property.
+  #
+  # CD and WP lines can be implemented on the hardware in one of two
+  # ways: as GPIOs, specified in cd-gpios and wp-gpios properties, or
+  # as dedicated pins. Polarity of dedicated pins can be specified,
+  # using *-inverted properties. GPIO polarity can also be specified
+  # using the GPIO_ACTIVE_LOW flag. This creates an ambiguity in the
+  # latter case. We choose to use the XOR logic for GPIO CD and WP
+  # lines.  This means, the two properties are "superimposed," for
+  # example leaving the GPIO_ACTIVE_LOW flag clear and specifying the
+  # respective *-inverted property property results in a
+  # double-inversion and actually means the "normal" line polarity is
+  # in effect.
+  wp-inverted:
+    $ref: /schemas/types.yaml#/definitions/flag
+    description:
+      The Write Protect line polarity is inverted.
+
+  cd-inverted:
+    $ref: /schemas/types.yaml#/definitions/flag
+    description:
+      The CD line polarity is inverted.
+
+  # Other properties
+
+  bus-width:
+    description:
+      Number of data lines.
+    $ref: /schemas/types.yaml#/definitions/uint32
+    enum: [1, 4, 8]
+    default: 1
+
+  max-frequency:
+    description: |
+      Maximum operating frequency of the bus:
+        - for eMMC, the maximum supported frequency is 200MHz,
+        - for SD/SDIO cards the SDR104 mode has a max supported
+          frequency of 208MHz,
+        - some mmc host controllers do support a max frequency upto
+          384MHz.
+      So, lets keep the maximum supported value here.
+
+    $ref: /schemas/types.yaml#/definitions/uint32
+    minimum: 400000
+    maximum: 384000000
+
+  disable-wp:
+    $ref: /schemas/types.yaml#/definitions/flag
+    description:
+      When set, no physical write-protect line is present. This
+      property should only be specified when the controller has a
+      dedicated write-protect detection logic. If a GPIO is always used
+      for the write-protect detection logic, it is sufficient to not
+      specify the wp-gpios property in the absence of a write-protect
+      line. Not used in combination with eMMC or SDIO.
+
+  wp-gpios:
+    maxItems: 1
+    description:
+      GPIO to use for the write-protect detection.
+
+  cd-debounce-delay-ms:
+    description:
+      Set delay time before detecting card after card insert
+      interrupt.
+
+  no-1-8-v:
+    $ref: /schemas/types.yaml#/definitions/flag
+    description:
+      When specified, denotes that 1.8V card voltage is not supported
+      on this system, even if the controller claims it.
+
+  cap-sd-highspeed:
+    $ref: /schemas/types.yaml#/definitions/flag
+    description:
+      SD high-speed timing is supported.
+
+  cap-mmc-highspeed:
+    $ref: /schemas/types.yaml#/definitions/flag
+    description:
+      MMC high-speed timing is supported.
+
+  sd-uhs-sdr12:
+    $ref: /schemas/types.yaml#/definitions/flag
+    description:
+      SD UHS SDR12 speed is supported.
+
+  sd-uhs-sdr25:
+    $ref: /schemas/types.yaml#/definitions/flag
+    description:
+      SD UHS SDR25 speed is supported.
+
+  sd-uhs-sdr50:
+    $ref: /schemas/types.yaml#/definitions/flag
+    description:
+      SD UHS SDR50 speed is supported.
+
+  sd-uhs-sdr104:
+    $ref: /schemas/types.yaml#/definitions/flag
+    description:
+      SD UHS SDR104 speed is supported.
+
+  sd-uhs-ddr50:
+    $ref: /schemas/types.yaml#/definitions/flag
+    description:
+      SD UHS DDR50 speed is supported.
+
+  cap-power-off-card:
+    $ref: /schemas/types.yaml#/definitions/flag
+    description:
+      Powering off the card is safe.
+
+  cap-mmc-hw-reset:
+    $ref: /schemas/types.yaml#/definitions/flag
+    description:
+      eMMC hardware reset is supported
+
+  cap-sdio-irq:
+    $ref: /schemas/types.yaml#/definitions/flag
+    description:
+      enable SDIO IRQ signalling on this interface
+
+  full-pwr-cycle:
+    $ref: /schemas/types.yaml#/definitions/flag
+    description:
+      Full power cycle of the card is supported.
+
+  full-pwr-cycle-in-suspend:
+    $ref: /schemas/types.yaml#/definitions/flag
+    description:
+      Full power cycle of the card in suspend is supported.
+
+  mmc-ddr-1_2v:
+    $ref: /schemas/types.yaml#/definitions/flag
+    description:
+      eMMC high-speed DDR mode (1.2V I/O) is supported.
+
+  mmc-ddr-1_8v:
+    $ref: /schemas/types.yaml#/definitions/flag
+    description:
+      eMMC high-speed DDR mode (1.8V I/O) is supported.
+
+  mmc-ddr-3_3v:
+    $ref: /schemas/types.yaml#/definitions/flag
+    description:
+      eMMC high-speed DDR mode (3.3V I/O) is supported.
+
+  mmc-hs200-1_2v:
+    $ref: /schemas/types.yaml#/definitions/flag
+    description:
+      eMMC HS200 mode (1.2V I/O) is supported.
+
+  mmc-hs200-1_8v:
+    $ref: /schemas/types.yaml#/definitions/flag
+    description:
+      eMMC HS200 mode (1.8V I/O) is supported.
+
+  mmc-hs400-1_2v:
+    $ref: /schemas/types.yaml#/definitions/flag
+    description:
+      eMMC HS400 mode (1.2V I/O) is supported.
+
+  mmc-hs400-1_8v:
+    $ref: /schemas/types.yaml#/definitions/flag
+    description:
+      eMMC HS400 mode (1.8V I/O) is supported.
+
+  mmc-hs400-enhanced-strobe:
+    $ref: /schemas/types.yaml#/definitions/flag
+    description:
+      eMMC HS400 enhanced strobe mode is supported
+
+  no-mmc-hs400:
+    $ref: /schemas/types.yaml#/definitions/flag
+    description:
+      All eMMC HS400 modes are not supported.
+
+  dsr:
+    description:
+      Value the card Driver Stage Register (DSR) should be programmed
+      with.
+    $ref: /schemas/types.yaml#/definitions/uint32
+    minimum: 0
+    maximum: 0xffff
+
+  no-sdio:
+    $ref: /schemas/types.yaml#/definitions/flag
+    description:
+      Controller is limited to send SDIO commands during
+      initialization.
+
+  no-sd:
+    $ref: /schemas/types.yaml#/definitions/flag
+    description:
+      Controller is limited to send SD commands during initialization.
+
+  no-mmc:
+    $ref: /schemas/types.yaml#/definitions/flag
+    description:
+      Controller is limited to send MMC commands during
+      initialization.
+
+  fixed-emmc-driver-type:
+    description:
+      For non-removable eMMC, enforce this driver type. The value is
+      the driver type as specified in the eMMC specification (table
+      206 in spec version 5.1)
+    $ref: /schemas/types.yaml#/definitions/uint32
+    minimum: 0
+    maximum: 4
+
+  post-power-on-delay-ms:
+    description:
+      It was invented for MMC pwrseq-simple which could be referred to
+      mmc-pwrseq-simple.yaml. But now it\'s reused as a tunable delay
+      waiting for I/O signalling and card power supply to be stable,
+      regardless of whether pwrseq-simple is used. Default to 10ms if
+      no available.
+    default: 10
+
+  supports-cqe:
+    $ref: /schemas/types.yaml#/definitions/flag
+    description:
+      The presence of this property indicates that the corresponding
+      MMC host controller supports HW command queue feature.
+
+  disable-cqe-dcmd:
+    $ref: /schemas/types.yaml#/definitions/flag
+    description:
+      The presence of this property indicates that the MMC
+      controller\'s command queue engine (CQE) does not support direct
+      commands (DCMDs).
+
+  keep-power-in-suspend:
+    $ref: /schemas/types.yaml#/definitions/flag
+    description:
+      SDIO only. Preserves card power during a suspend/resume cycle.
+
+  wakeup-source:
+    $ref: /schemas/types.yaml#/definitions/flag
+    description:
+      SDIO only. Enables wake up of host system on SDIO IRQ assertion.
+
+  vmmc-supply:
+    description:
+      Supply for the card power
+
+  vqmmc-supply:
+    description:
+      Supply for the bus IO line power, such as a level shifter.
+      If the level shifter is controlled by a GPIO line, this shall
+      be modeled as a "regulator-fixed" with a GPIO line for
+      switching the level shifter on/off.
+
+  mmc-pwrseq:
+    $ref: /schemas/types.yaml#/definitions/phandle
+    description:
+      System-on-Chip designs may specify a specific MMC power
+      sequence. To successfully detect an (e)MMC/SD/SDIO card, that
+      power sequence must be maintained while initializing the card.
+
+patternProperties:
+  "^.*@[0-9]+$":
+    type: object
+    description: |
+      On embedded systems the cards connected to a host may need
+      additional properties. These can be specified in subnodes to the
+      host controller node. The subnodes are identified by the
+      standard \'reg\' property. Which information exactly can be
+      specified depends on the bindings for the SDIO function driver
+      for the subnode, as specified by the compatible string.
+
+    properties:
+      compatible:
+        description:
+          Name of SDIO function following generic names recommended
+          practice
+
+      reg:
+        items:
+          - minimum: 0
+            maximum: 7
+            description:
+              Must contain the SDIO function number of the function this
+              subnode describes. A value of 0 denotes the memory SD
+              function, values from 1 to 7 denote the SDIO functions.
+
+    required:
+      - reg
+
+  "^clk-phase-(legacy|sd-hs|mmc-(hs|hs[24]00|ddr52)|uhs-(sdr(12|25|50|104)|ddr50))$":
+    $ref: /schemas/types.yaml#/definitions/uint32-array
+
+    minItems: 2
+    maxItems: 2
+    items:
+      minimum: 0
+      maximum: 359
+      description:
+        Set the clock (phase) delays which are to be configured in the
+        controller while switching to particular speed mode. These values
+        are in pair of degrees.
+
+dependencies:
+  cd-debounce-delay-ms: [ cd-gpios ]
+  fixed-emmc-driver-type: [ non-removable ]
+
+additionalProperties: true
diff --git a/dts/upstream/Bindings/mmc/mmc-controller.yaml b/dts/upstream/Bindings/mmc/mmc-controller.yaml
index 58ae298cd2f..9d7a1298c45 100644
--- a/dts/upstream/Bindings/mmc/mmc-controller.yaml
+++ b/dts/upstream/Bindings/mmc/mmc-controller.yaml
@@ -9,7 +9,7 @@ title: MMC Controller Common Properties
 maintainers:
   - Ulf Hansson <ulf.hansson@linaro.org>
 
-description: |
+description:
   These properties are common to multiple MMC host controllers. Any host
   that requires the respective functionality should implement them using
   these definitions.
@@ -18,351 +18,13 @@ description: |
   (and the corresponding mmcblkN devices) by defining an alias in the
   /aliases device tree node.
 
+$ref: mmc-controller-common.yaml#
+
 properties:
   $nodename:
     pattern: "^mmc(@.*)?$"
 
-  "#address-cells":
-    const: 1
-    description: |
-      The cell is the slot ID if a function subnode is used.
-
-  "#size-cells":
-    const: 0
-
-  # Card Detection.
-  # If none of these properties are supplied, the host native card
-  # detect will be used. Only one of them should be provided.
-
-  broken-cd:
-    $ref: /schemas/types.yaml#/definitions/flag
-    description:
-      There is no card detection available; polling must be used.
-
-  cd-gpios:
-    maxItems: 1
-    description:
-      The card detection will be done using the GPIO provided.
-
-  non-removable:
-    $ref: /schemas/types.yaml#/definitions/flag
-    description:
-      Non-removable slot (like eMMC); assume always present.
-
-  # *NOTE* on CD and WP polarity. To use common for all SD/MMC host
-  # controllers line polarity properties, we have to fix the meaning
-  # of the "normal" and "inverted" line levels. We choose to follow
-  # the SDHCI standard, which specifies both those lines as "active
-  # low." Therefore, using the "cd-inverted" property means, that the
-  # CD line is active high, i.e. it is high, when a card is
-  # inserted. Similar logic applies to the "wp-inverted" property.
-  #
-  # CD and WP lines can be implemented on the hardware in one of two
-  # ways: as GPIOs, specified in cd-gpios and wp-gpios properties, or
-  # as dedicated pins. Polarity of dedicated pins can be specified,
-  # using *-inverted properties. GPIO polarity can also be specified
-  # using the GPIO_ACTIVE_LOW flag. This creates an ambiguity in the
-  # latter case. We choose to use the XOR logic for GPIO CD and WP
-  # lines.  This means, the two properties are "superimposed," for
-  # example leaving the GPIO_ACTIVE_LOW flag clear and specifying the
-  # respective *-inverted property property results in a
-  # double-inversion and actually means the "normal" line polarity is
-  # in effect.
-  wp-inverted:
-    $ref: /schemas/types.yaml#/definitions/flag
-    description:
-      The Write Protect line polarity is inverted.
-
-  cd-inverted:
-    $ref: /schemas/types.yaml#/definitions/flag
-    description:
-      The CD line polarity is inverted.
-
-  # Other properties
-
-  bus-width:
-    description:
-      Number of data lines.
-    $ref: /schemas/types.yaml#/definitions/uint32
-    enum: [1, 4, 8]
-    default: 1
-
-  max-frequency:
-    description: |
-      Maximum operating frequency of the bus:
-        - for eMMC, the maximum supported frequency is 200MHz,
-        - for SD/SDIO cards the SDR104 mode has a max supported
-          frequency of 208MHz,
-        - some mmc host controllers do support a max frequency upto
-          384MHz.
-      So, lets keep the maximum supported value here.
-
-    $ref: /schemas/types.yaml#/definitions/uint32
-    minimum: 400000
-    maximum: 384000000
-
-  disable-wp:
-    $ref: /schemas/types.yaml#/definitions/flag
-    description:
-      When set, no physical write-protect line is present. This
-      property should only be specified when the controller has a
-      dedicated write-protect detection logic. If a GPIO is always used
-      for the write-protect detection logic, it is sufficient to not
-      specify the wp-gpios property in the absence of a write-protect
-      line. Not used in combination with eMMC or SDIO.
-
-  wp-gpios:
-    maxItems: 1
-    description:
-      GPIO to use for the write-protect detection.
-
-  cd-debounce-delay-ms:
-    description:
-      Set delay time before detecting card after card insert
-      interrupt.
-
-  no-1-8-v:
-    $ref: /schemas/types.yaml#/definitions/flag
-    description:
-      When specified, denotes that 1.8V card voltage is not supported
-      on this system, even if the controller claims it.
-
-  cap-sd-highspeed:
-    $ref: /schemas/types.yaml#/definitions/flag
-    description:
-      SD high-speed timing is supported.
-
-  cap-mmc-highspeed:
-    $ref: /schemas/types.yaml#/definitions/flag
-    description:
-      MMC high-speed timing is supported.
-
-  sd-uhs-sdr12:
-    $ref: /schemas/types.yaml#/definitions/flag
-    description:
-      SD UHS SDR12 speed is supported.
-
-  sd-uhs-sdr25:
-    $ref: /schemas/types.yaml#/definitions/flag
-    description:
-      SD UHS SDR25 speed is supported.
-
-  sd-uhs-sdr50:
-    $ref: /schemas/types.yaml#/definitions/flag
-    description:
-      SD UHS SDR50 speed is supported.
-
-  sd-uhs-sdr104:
-    $ref: /schemas/types.yaml#/definitions/flag
-    description:
-      SD UHS SDR104 speed is supported.
-
-  sd-uhs-ddr50:
-    $ref: /schemas/types.yaml#/definitions/flag
-    description:
-      SD UHS DDR50 speed is supported.
-
-  cap-power-off-card:
-    $ref: /schemas/types.yaml#/definitions/flag
-    description:
-      Powering off the card is safe.
-
-  cap-mmc-hw-reset:
-    $ref: /schemas/types.yaml#/definitions/flag
-    description:
-      eMMC hardware reset is supported
-
-  cap-sdio-irq:
-    $ref: /schemas/types.yaml#/definitions/flag
-    description:
-      enable SDIO IRQ signalling on this interface
-
-  full-pwr-cycle:
-    $ref: /schemas/types.yaml#/definitions/flag
-    description:
-      Full power cycle of the card is supported.
-
-  full-pwr-cycle-in-suspend:
-    $ref: /schemas/types.yaml#/definitions/flag
-    description:
-      Full power cycle of the card in suspend is supported.
-
-  mmc-ddr-1_2v:
-    $ref: /schemas/types.yaml#/definitions/flag
-    description:
-      eMMC high-speed DDR mode (1.2V I/O) is supported.
-
-  mmc-ddr-1_8v:
-    $ref: /schemas/types.yaml#/definitions/flag
-    description:
-      eMMC high-speed DDR mode (1.8V I/O) is supported.
-
-  mmc-ddr-3_3v:
-    $ref: /schemas/types.yaml#/definitions/flag
-    description:
-      eMMC high-speed DDR mode (3.3V I/O) is supported.
-
-  mmc-hs200-1_2v:
-    $ref: /schemas/types.yaml#/definitions/flag
-    description:
-      eMMC HS200 mode (1.2V I/O) is supported.
-
-  mmc-hs200-1_8v:
-    $ref: /schemas/types.yaml#/definitions/flag
-    description:
-      eMMC HS200 mode (1.8V I/O) is supported.
-
-  mmc-hs400-1_2v:
-    $ref: /schemas/types.yaml#/definitions/flag
-    description:
-      eMMC HS400 mode (1.2V I/O) is supported.
-
-  mmc-hs400-1_8v:
-    $ref: /schemas/types.yaml#/definitions/flag
-    description:
-      eMMC HS400 mode (1.8V I/O) is supported.
-
-  mmc-hs400-enhanced-strobe:
-    $ref: /schemas/types.yaml#/definitions/flag
-    description:
-      eMMC HS400 enhanced strobe mode is supported
-
-  no-mmc-hs400:
-    $ref: /schemas/types.yaml#/definitions/flag
-    description:
-      All eMMC HS400 modes are not supported.
-
-  dsr:
-    description:
-      Value the card Driver Stage Register (DSR) should be programmed
-      with.
-    $ref: /schemas/types.yaml#/definitions/uint32
-    minimum: 0
-    maximum: 0xffff
-
-  no-sdio:
-    $ref: /schemas/types.yaml#/definitions/flag
-    description:
-      Controller is limited to send SDIO commands during
-      initialization.
-
-  no-sd:
-    $ref: /schemas/types.yaml#/definitions/flag
-    description:
-      Controller is limited to send SD commands during initialization.
-
-  no-mmc:
-    $ref: /schemas/types.yaml#/definitions/flag
-    description:
-      Controller is limited to send MMC commands during
-      initialization.
-
-  fixed-emmc-driver-type:
-    description:
-      For non-removable eMMC, enforce this driver type. The value is
-      the driver type as specified in the eMMC specification (table
-      206 in spec version 5.1)
-    $ref: /schemas/types.yaml#/definitions/uint32
-    minimum: 0
-    maximum: 4
-
-  post-power-on-delay-ms:
-    description:
-      It was invented for MMC pwrseq-simple which could be referred to
-      mmc-pwrseq-simple.yaml. But now it\'s reused as a tunable delay
-      waiting for I/O signalling and card power supply to be stable,
-      regardless of whether pwrseq-simple is used. Default to 10ms if
-      no available.
-    default: 10
-
-  supports-cqe:
-    $ref: /schemas/types.yaml#/definitions/flag
-    description:
-      The presence of this property indicates that the corresponding
-      MMC host controller supports HW command queue feature.
-
-  disable-cqe-dcmd:
-    $ref: /schemas/types.yaml#/definitions/flag
-    description:
-      The presence of this property indicates that the MMC
-      controller\'s command queue engine (CQE) does not support direct
-      commands (DCMDs).
-
-  keep-power-in-suspend:
-    $ref: /schemas/types.yaml#/definitions/flag
-    description:
-      SDIO only. Preserves card power during a suspend/resume cycle.
-
-  wakeup-source:
-    $ref: /schemas/types.yaml#/definitions/flag
-    description:
-      SDIO only. Enables wake up of host system on SDIO IRQ assertion.
-
-  vmmc-supply:
-    description:
-      Supply for the card power
-
-  vqmmc-supply:
-    description:
-      Supply for the bus IO line power, such as a level shifter.
-      If the level shifter is controlled by a GPIO line, this shall
-      be modeled as a "regulator-fixed" with a GPIO line for
-      switching the level shifter on/off.
-
-  mmc-pwrseq:
-    $ref: /schemas/types.yaml#/definitions/phandle
-    description:
-      System-on-Chip designs may specify a specific MMC power
-      sequence. To successfully detect an (e)MMC/SD/SDIO card, that
-      power sequence must be maintained while initializing the card.
-
-patternProperties:
-  "^.*@[0-9]+$":
-    type: object
-    description: |
-      On embedded systems the cards connected to a host may need
-      additional properties. These can be specified in subnodes to the
-      host controller node. The subnodes are identified by the
-      standard \'reg\' property. Which information exactly can be
-      specified depends on the bindings for the SDIO function driver
-      for the subnode, as specified by the compatible string.
-
-    properties:
-      compatible:
-        description: |
-          Name of SDIO function following generic names recommended
-          practice
-
-      reg:
-        items:
-          - minimum: 0
-            maximum: 7
-            description:
-              Must contain the SDIO function number of the function this
-              subnode describes. A value of 0 denotes the memory SD
-              function, values from 1 to 7 denote the SDIO functions.
-
-    required:
-      - reg
-
-  "^clk-phase-(legacy|sd-hs|mmc-(hs|hs[24]00|ddr52)|uhs-(sdr(12|25|50|104)|ddr50))$":
-    $ref: /schemas/types.yaml#/definitions/uint32-array
-
-    minItems: 2
-    maxItems: 2
-    items:
-      minimum: 0
-      maximum: 359
-      description:
-        Set the clock (phase) delays which are to be configured in the
-        controller while switching to particular speed mode. These values
-        are in pair of degrees.
-
-dependencies:
-  cd-debounce-delay-ms: [ cd-gpios ]
-  fixed-emmc-driver-type: [ non-removable ]
-
-additionalProperties: true
+unevaluatedProperties: true
 
 examples:
   - |
diff --git a/dts/upstream/Bindings/mmc/mmc-slot.yaml b/dts/upstream/Bindings/mmc/mmc-slot.yaml
new file mode 100644
index 00000000000..1f066782806
--- /dev/null
+++ b/dts/upstream/Bindings/mmc/mmc-slot.yaml
@@ -0,0 +1,49 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mmc/mmc-slot.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MMC slot properties
+
+maintainers:
+  - Ulf Hansson <ulf.hansson@linaro.org>
+
+description:
+  These properties defines slot properties for MMC controlers that
+  have multiple slots or ports provided by the same controller and
+  sharing the same resources.
+
+$ref: mmc-controller-common.yaml#
+
+properties:
+  $nodename:
+    pattern: "^slot(@.*)?$"
+
+  compatible:
+    const: mmc-slot
+
+  reg:
+    description:
+      the slot (or "port") ID
+    maxItems: 1
+
+required:
+  - compatible
+  - reg
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    mmc {
+      #address-cells = <1>;
+      #size-cells = <0>;
+      slot@0 {
+        compatible = "mmc-slot";
+        reg = <0>;
+        bus-width = <4>;
+      };
+    };
+
+...
diff --git a/dts/upstream/Bindings/mmc/mtk-sd.yaml b/dts/upstream/Bindings/mmc/mtk-sd.yaml
index f86ebd81f5a..0debccbd651 100644
--- a/dts/upstream/Bindings/mmc/mtk-sd.yaml
+++ b/dts/upstream/Bindings/mmc/mtk-sd.yaml
@@ -235,11 +235,19 @@ allOf:
       properties:
         compatible:
           contains:
-            const: mediatek,mt8183-mmc
+            enum:
+              - mediatek,mt7986-mmc
+              - mediatek,mt7988-mmc
+              - mediatek,mt8183-mmc
+              - mediatek,mt8196-mmc
     then:
       properties:
         reg:
           minItems: 2
+    else:
+      properties:
+        reg:
+          maxItems: 1
 
   - if:
       properties:
diff --git a/dts/upstream/Bindings/mmc/samsung,exynos-dw-mshc.yaml b/dts/upstream/Bindings/mmc/samsung,exynos-dw-mshc.yaml
index 5fe65795f79..ef2d1d7c92f 100644
--- a/dts/upstream/Bindings/mmc/samsung,exynos-dw-mshc.yaml
+++ b/dts/upstream/Bindings/mmc/samsung,exynos-dw-mshc.yaml
@@ -29,6 +29,7 @@ properties:
               - samsung,exynos5433-dw-mshc-smu
               - samsung,exynos7885-dw-mshc-smu
               - samsung,exynos850-dw-mshc-smu
+              - samsung,exynos8895-dw-mshc-smu
           - const: samsung,exynos7-dw-mshc-smu
 
   reg:
diff --git a/dts/upstream/Bindings/mmc/sdhci-msm.yaml b/dts/upstream/Bindings/mmc/sdhci-msm.yaml
index 8b393e26e02..eed9063e9bb 100644
--- a/dts/upstream/Bindings/mmc/sdhci-msm.yaml
+++ b/dts/upstream/Bindings/mmc/sdhci-msm.yaml
@@ -7,7 +7,8 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
 title: Qualcomm SDHCI controller (sdhci-msm)
 
 maintainers:
-  - Bhupesh Sharma <bhupesh.sharma@linaro.org>
+  - Bjorn Andersson <andersson@kernel.org>
+  - Konrad Dybcio <konradybcio@kernel.org>
 
 description:
   Secure Digital Host Controller Interface (SDHCI) present on
diff --git a/dts/upstream/Bindings/mtd/cadence-nand-controller.txt b/dts/upstream/Bindings/mtd/cadence-nand-controller.txt
deleted file mode 100644
index d2eada5044b..00000000000
--- a/dts/upstream/Bindings/mtd/cadence-nand-controller.txt
+++ /dev/null
@@ -1,53 +0,0 @@
-* Cadence NAND controller
-
-Required properties:
-  - compatible : "cdns,hp-nfc"
-  - reg : Contains two entries, each of which is a tuple consisting of a
-	  physical address and length. The first entry is the address and
-	  length of the controller register set. The second entry is the
-	  address and length of the Slave DMA data port.
-  - reg-names: should contain "reg" and "sdma"
-  - #address-cells: should be 1. The cell encodes the chip select connection.
-  - #size-cells : should be 0.
-  - interrupts : The interrupt number.
-  - clocks: phandle of the controller core clock (nf_clk).
-
-Optional properties:
-  - dmas: shall reference DMA channel associated to the NAND controller
-  - cdns,board-delay-ps : Estimated Board delay. The value includes the total
-    round trip delay for the signals and is used for deciding on values
-    associated with data read capture. The example formula for SDR mode is
-    the following:
-    board delay = RE#PAD delay + PCB trace to device + PCB trace from device
-    + DQ PAD delay
-
-Child nodes represent the available NAND chips.
-
-Required properties of NAND chips:
-  - reg: shall contain the native Chip Select ids from 0 to max supported by
-    the cadence nand flash controller
-
-See Documentation/devicetree/bindings/mtd/nand-controller.yaml for more details on
-generic bindings.
-
-Example:
-
-nand_controller: nand-controller@60000000 {
-	  compatible = "cdns,hp-nfc";
-	  #address-cells = <1>;
-	  #size-cells = <0>;
-	  reg = <0x60000000 0x10000>, <0x80000000 0x10000>;
-	  reg-names = "reg", "sdma";
-	  clocks = <&nf_clk>;
-	  cdns,board-delay-ps = <4830>;
-	  interrupts = <2 0>;
-	  nand@0 {
-	      reg = <0>;
-	      label = "nand-1";
-	  };
-	  nand@1 {
-	      reg = <1>;
-	      label = "nand-2";
-	  };
-
-};
diff --git a/dts/upstream/Bindings/mtd/cdns,hp-nfc.yaml b/dts/upstream/Bindings/mtd/cdns,hp-nfc.yaml
new file mode 100644
index 00000000000..e1f4d7c35a8
--- /dev/null
+++ b/dts/upstream/Bindings/mtd/cdns,hp-nfc.yaml
@@ -0,0 +1,81 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mtd/cdns,hp-nfc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Cadence NAND controller
+
+maintainers:
+  - Niravkumar L Rabara <niravkumar.l.rabara@intel.com>
+
+allOf:
+  - $ref: nand-controller.yaml
+
+properties:
+  compatible:
+    items:
+      - const: cdns,hp-nfc
+
+  reg:
+    items:
+      - description: Controller register set
+      - description: Slave DMA data port register set
+
+  reg-names:
+    items:
+      - const: reg
+      - const: sdma
+
+  interrupts:
+    maxItems: 1
+
+  clocks:
+    maxItems: 1
+
+  clock-names:
+    items:
+      - const: nf_clk
+
+  dmas:
+    maxItems: 1
+
+  cdns,board-delay-ps:
+    description: |
+      Estimated Board delay. The value includes the total round trip
+      delay for the signals and is used for deciding on values associated
+      with data read capture. The example formula for SDR mode is the
+      following.
+      board delay = RE#PAD delay + PCB trace to device + PCB trace from device
+      + DQ PAD delay
+
+required:
+  - compatible
+  - reg
+  - reg-names
+  - interrupts
+  - clocks
+  - clock-names
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+    nand-controller@10b80000 {
+        compatible = "cdns,hp-nfc";
+        reg = <0x10b80000 0x10000>,
+              <0x10840000 0x10000>;
+        reg-names = "reg", "sdma";
+        #address-cells = <1>;
+        #size-cells = <0>;
+        interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
+        clocks = <&clk>;
+        clock-names = "nf_clk";
+        cdns,board-delay-ps = <4830>;
+
+        nand@0 {
+            reg = <0>;
+        };
+    };
diff --git a/dts/upstream/Bindings/mtd/davinci-nand.txt b/dts/upstream/Bindings/mtd/davinci-nand.txt
deleted file mode 100644
index eb8e2ff4dbd..00000000000
--- a/dts/upstream/Bindings/mtd/davinci-nand.txt
+++ /dev/null
@@ -1,94 +0,0 @@
-Device tree bindings for Texas instruments Davinci/Keystone NAND controller
-
-This file provides information, what the device node for the davinci/keystone
-NAND interface contains.
-
-Documentation:
-Davinci DM646x - https://www.ti.com/lit/ug/sprueq7c/sprueq7c.pdf
-Kestone - https://www.ti.com/lit/ug/sprugz3a/sprugz3a.pdf
-
-Required properties:
-
-- compatible:			"ti,davinci-nand"
-				"ti,keystone-nand"
-
-- reg:				Contains 2 offset/length values:
-				- offset and length for the access window.
-				- offset and length for accessing the AEMIF
-				control registers.
-
-- ti,davinci-chipselect:	number of chipselect. Indicates on the
-				davinci_nand driver which chipselect is used
-				for accessing the nand.
-				Can be in the range [0-3].
-
-Recommended properties :
-
-- ti,davinci-mask-ale:		mask for ALE. Needed for executing address
-				phase. These offset will be added to the base
-				address for the chip select space the NAND Flash
-				device is connected to.
-				If not set equal to 0x08.
-
-- ti,davinci-mask-cle:		mask for CLE. Needed for executing command
-				phase. These offset will be added to the base
-				address for the chip select space the NAND Flash
-				device is connected to.
-				If not set equal to 0x10.
-
-- ti,davinci-mask-chipsel:	mask for chipselect address. Needed to mask
-				addresses for given chipselect.
-
-- nand-ecc-mode:		operation mode of the NAND ecc mode. ECC mode
-				valid values for davinci driver:
-				- "none"
-				- "soft"
-				- "hw"
-
-- ti,davinci-ecc-bits:		used ECC bits, currently supported 1 or 4.
-
-- nand-bus-width:		buswidth 8 or 16. If not present 8.
-
-- nand-on-flash-bbt:		use flash based bad block table support. OOB
-				identifier is saved in OOB area. If not present
-				false.
-
-Deprecated properties:
-
-- ti,davinci-ecc-mode:		operation mode of the NAND ecc mode. ECC mode
-				valid values for davinci driver:
-				- "none"
-				- "soft"
-				- "hw"
-
-- ti,davinci-nand-buswidth:	buswidth 8 or 16. If not present 8.
-
-- ti,davinci-nand-use-bbt:	use flash based bad block table support. OOB
-				identifier is saved in OOB area. If not present
-				false.
-
-Nand device bindings may contain additional sub-nodes describing partitions of
-the address space. See mtd.yaml for more detail. The NAND Flash timing
-values must be programmed in the chip select’s node of AEMIF
-memory-controller (see Documentation/devicetree/bindings/memory-controllers/
-davinci-aemif.txt).
-
-Example(da850 EVM ):
-
-nand_cs3@62000000 {
-	compatible = "ti,davinci-nand";
-	reg = <0x62000000 0x807ff
-	       0x68000000 0x8000>;
-	ti,davinci-chipselect = <1>;
-	ti,davinci-mask-ale = <0>;
-	ti,davinci-mask-cle = <0>;
-	ti,davinci-mask-chipsel = <0>;
-	nand-ecc-mode = "hw";
-	ti,davinci-ecc-bits = <4>;
-	nand-on-flash-bbt;
-
-	partition@180000 {
-		label = "ubifs";
-		reg = <0x180000 0x7e80000>;
-	};
-};
diff --git a/dts/upstream/Bindings/mtd/jedec,spi-nor.yaml b/dts/upstream/Bindings/mtd/jedec,spi-nor.yaml
index 6e3afb42926..335f8204aa1 100644
--- a/dts/upstream/Bindings/mtd/jedec,spi-nor.yaml
+++ b/dts/upstream/Bindings/mtd/jedec,spi-nor.yaml
@@ -96,6 +96,10 @@ properties:
       If "broken-flash-reset" is present then having this property does not
       make any difference.
 
+  vcc-supply:
+    description:
+      Supply for the SPI NOR power.
+
   spi-cpol: true
   spi-cpha: true
 
diff --git a/dts/upstream/Bindings/mtd/microchip,mchp48l640.yaml b/dts/upstream/Bindings/mtd/microchip,mchp48l640.yaml
index 0ff32bd00bf..5c6b628c608 100644
--- a/dts/upstream/Bindings/mtd/microchip,mchp48l640.yaml
+++ b/dts/upstream/Bindings/mtd/microchip,mchp48l640.yaml
@@ -16,8 +16,9 @@ description: |
 
 properties:
   compatible:
-    items:
-      - const: microchip,48l640
+    enum:
+      - fujitsu,mb85rs128ty
+      - microchip,48l640
 
   reg:
     maxItems: 1
diff --git a/dts/upstream/Bindings/mtd/nuvoton,ma35d1-nand.yaml b/dts/upstream/Bindings/mtd/nuvoton,ma35d1-nand.yaml
new file mode 100644
index 00000000000..0b651450a8f
--- /dev/null
+++ b/dts/upstream/Bindings/mtd/nuvoton,ma35d1-nand.yaml
@@ -0,0 +1,95 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mtd/nuvoton,ma35d1-nand.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Nuvoton MA35D1 NAND Flash Interface (NFI) Controller
+
+maintainers:
+  - Hui-Ping Chen <hpchen0nvt@gmail.com>
+
+allOf:
+  - $ref: nand-controller.yaml#
+
+properties:
+  compatible:
+    enum:
+      - nuvoton,ma35d1-nand-controller
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+
+  clocks:
+    maxItems: 1
+
+patternProperties:
+  "^nand@[a-f0-9]$":
+    type: object
+    $ref: raw-nand-chip.yaml
+    properties:
+      reg:
+        minimum: 0
+        maximum: 1
+
+      nand-ecc-step-size:
+        enum: [512, 1024]
+
+      nand-ecc-strength:
+        enum: [8, 12, 24]
+
+    required:
+      - reg
+
+    unevaluatedProperties: false
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - clocks
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+    #include <dt-bindings/clock/nuvoton,ma35d1-clk.h>
+
+    soc {
+        #address-cells = <2>;
+        #size-cells = <2>;
+
+        nand-controller@401A0000 {
+            compatible = "nuvoton,ma35d1-nand-controller";
+            reg = <0x0 0x401A0000 0x0 0x1000>;
+            interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
+            clocks = <&clk NAND_GATE>;
+            #address-cells = <1>;
+            #size-cells = <0>;
+
+            nand@0 {
+                reg = <0>;
+                nand-on-flash-bbt;
+                nand-ecc-step-size = <512>;
+                nand-ecc-strength = <8>;
+
+                partitions {
+                    compatible = "fixed-partitions";
+                    #address-cells = <1>;
+                    #size-cells = <1>;
+
+                    uboot@0 {
+                        label = "nand-uboot";
+                        read-only;
+                        reg = <0x0 0x300000>;
+                    };
+                };
+            };
+        };
+    };
+
+...
diff --git a/dts/upstream/Bindings/mtd/ti,davinci-nand.yaml b/dts/upstream/Bindings/mtd/ti,davinci-nand.yaml
new file mode 100644
index 00000000000..ed24b0ea86e
--- /dev/null
+++ b/dts/upstream/Bindings/mtd/ti,davinci-nand.yaml
@@ -0,0 +1,124 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mtd/ti,davinci-nand.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: TI DaVinci NAND controller
+
+maintainers:
+  - Marcus Folkesson <marcus.folkesson@gmail.com>
+
+allOf:
+  - $ref: nand-controller.yaml
+
+properties:
+  compatible:
+    enum:
+      - ti,davinci-nand
+      - ti,keystone-nand
+
+  reg:
+    items:
+      - description: Access window.
+      - description: AEMIF control registers.
+
+  partitions:
+    $ref: /schemas/mtd/partitions/partitions.yaml
+
+  ti,davinci-chipselect:
+    description:
+      Number of chipselect. Indicate on the davinci_nand driver which
+      chipselect is used for accessing the nand.
+    $ref: /schemas/types.yaml#/definitions/uint32
+    enum: [0, 1, 2, 3]
+
+  ti,davinci-mask-ale:
+    description:
+      Mask for ALE. Needed for executing address phase. These offset will be
+      added to the base address for the chip select space the NAND Flash
+      device is connected to.
+    $ref: /schemas/types.yaml#/definitions/uint32
+    default: 0x08
+
+  ti,davinci-mask-cle:
+    description:
+      Mask for CLE. Needed for executing command phase. These offset will be
+      added to the base address for the chip select space the NAND Flash device
+      is connected to.
+    $ref: /schemas/types.yaml#/definitions/uint32
+    default: 0x10
+
+  ti,davinci-mask-chipsel:
+    description:
+      Mask for chipselect address. Needed to mask addresses for given
+      chipselect.
+    $ref: /schemas/types.yaml#/definitions/uint32
+    default: 0
+
+  ti,davinci-ecc-bits:
+    description: Used ECC bits.
+    enum: [1, 4]
+
+  ti,davinci-ecc-mode:
+    description: Operation mode of the NAND ECC mode.
+    $ref: /schemas/types.yaml#/definitions/string
+    enum: [none, soft, hw, on-die]
+    deprecated: true
+
+  ti,davinci-nand-buswidth:
+    description: Bus width to the NAND chip.
+    $ref: /schemas/types.yaml#/definitions/uint32
+    enum: [8, 16]
+    default: 8
+    deprecated: true
+
+  ti,davinci-nand-use-bbt:
+    type: boolean
+    description:
+      Use flash based bad block table support. OOB identifier is saved in OOB
+      area.
+    deprecated: true
+
+required:
+  - compatible
+  - reg
+  - ti,davinci-chipselect
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    bus {
+      #address-cells = <2>;
+      #size-cells = <1>;
+
+      nand-controller@2000000,0 {
+        compatible = "ti,davinci-nand";
+        #address-cells = <1>;
+        #size-cells = <0>;
+        reg = <0 0x02000000 0x02000000>,
+              <1 0x00000000 0x00008000>;
+
+        ti,davinci-chipselect = <1>;
+        ti,davinci-mask-ale = <0>;
+        ti,davinci-mask-cle = <0>;
+        ti,davinci-mask-chipsel = <0>;
+
+        ti,davinci-nand-buswidth = <16>;
+        ti,davinci-ecc-mode = "hw";
+        ti,davinci-ecc-bits = <4>;
+        ti,davinci-nand-use-bbt;
+
+        partitions {
+          compatible = "fixed-partitions";
+          #address-cells = <1>;
+          #size-cells = <1>;
+
+          partition@0 {
+            label = "u-boot env";
+            reg = <0 0x020000>;
+          };
+        };
+      };
+    };
diff --git a/dts/upstream/Bindings/net/amlogic,meson-dwmac.yaml b/dts/upstream/Bindings/net/amlogic,meson-dwmac.yaml
index d1e2bca3c50..798a4c19f18 100644
--- a/dts/upstream/Bindings/net/amlogic,meson-dwmac.yaml
+++ b/dts/upstream/Bindings/net/amlogic,meson-dwmac.yaml
@@ -166,11 +166,11 @@ unevaluatedProperties: false
 examples:
   - |
     ethmac: ethernet@c9410000 {
-         compatible = "amlogic,meson-gxbb-dwmac", "snps,dwmac";
-         reg = <0xc9410000 0x10000>, <0xc8834540 0x8>;
-         interrupts = <8>;
-         interrupt-names = "macirq";
-         clocks = <&clk_eth>, <&clk_fclk_div2>, <&clk_mpll2>, <&clk_fclk_div2>;
-         clock-names = "stmmaceth", "clkin0", "clkin1", "timing-adjustment";
-         phy-mode = "rgmii";
+        compatible = "amlogic,meson-gxbb-dwmac", "snps,dwmac";
+        reg = <0xc9410000 0x10000>, <0xc8834540 0x8>;
+        interrupts = <8>;
+        interrupt-names = "macirq";
+        clocks = <&clk_eth>, <&clk_fclk_div2>, <&clk_mpll2>, <&clk_fclk_div2>;
+        clock-names = "stmmaceth", "clkin0", "clkin1", "timing-adjustment";
+        phy-mode = "rgmii";
     };
diff --git a/dts/upstream/Bindings/net/asix,ax88178.yaml b/dts/upstream/Bindings/net/asix,ax88178.yaml
index 768504ccbf7..03341b7438d 100644
--- a/dts/upstream/Bindings/net/asix,ax88178.yaml
+++ b/dts/upstream/Bindings/net/asix,ax88178.yaml
@@ -63,8 +63,8 @@ examples:
             #size-cells = <0>;
 
             ethernet@1 {
-               compatible = "usbb95,772b";
-               reg = <1>;
+                compatible = "usbb95,772b";
+                reg = <1>;
             };
         };
     };
diff --git a/dts/upstream/Bindings/net/bluetooth/qualcomm-bluetooth.yaml b/dts/upstream/Bindings/net/bluetooth/qualcomm-bluetooth.yaml
index 7bb68311c60..a72152f7e29 100644
--- a/dts/upstream/Bindings/net/bluetooth/qualcomm-bluetooth.yaml
+++ b/dts/upstream/Bindings/net/bluetooth/qualcomm-bluetooth.yaml
@@ -101,7 +101,10 @@ properties:
   max-speed: true
 
   firmware-name:
-    description: specify the name of nvm firmware to load
+    minItems: 1
+    items:
+      - description: specify the name of nvm firmware to load
+      - description: specify the name of rampatch firmware to load
 
   local-bd-address: true
 
@@ -154,16 +157,11 @@ allOf:
               - qcom,wcn6750-bt
     then:
       required:
-        - enable-gpios
-        - swctrl-gpios
-        - vddio-supply
         - vddaon-supply
-        - vddbtcxmx-supply
         - vddrfacmn-supply
         - vddrfa0p8-supply
         - vddrfa1p7-supply
         - vddrfa1p2-supply
-        - vddasd-supply
   - if:
       properties:
         compatible:
diff --git a/dts/upstream/Bindings/net/brcm,bcmgenet.yaml b/dts/upstream/Bindings/net/brcm,bcmgenet.yaml
index 7c90a439053..0e3fb4e42e3 100644
--- a/dts/upstream/Bindings/net/brcm,bcmgenet.yaml
+++ b/dts/upstream/Bindings/net/brcm,bcmgenet.yaml
@@ -85,16 +85,16 @@ examples:
         #size-cells = <1>;
 
         mdio0: mdio@e14 {
-           compatible = "brcm,genet-mdio-v4";
-           #address-cells = <1>;
-           #size-cells = <0>;
-           reg = <0xe14 0x8>;
+            compatible = "brcm,genet-mdio-v4";
+            #address-cells = <1>;
+            #size-cells = <0>;
+            reg = <0xe14 0x8>;
 
-           phy1: ethernet-phy@1 {
+            phy1: ethernet-phy@1 {
                 max-speed = <1000>;
                 reg = <1>;
                 compatible = "ethernet-phy-ieee802.3-c22";
-           };
+            };
         };
     };
 
@@ -110,10 +110,10 @@ examples:
         interrupts = <0x0 0x16 0x0>, <0x0 0x17 0x0>;
 
         mdio1: mdio@e14 {
-           compatible = "brcm,genet-mdio-v4";
-           #address-cells = <1>;
-           #size-cells = <0>;
-           reg = <0xe14 0x8>;
+            compatible = "brcm,genet-mdio-v4";
+            #address-cells = <1>;
+            #size-cells = <0>;
+            reg = <0xe14 0x8>;
         };
     };
 
@@ -129,15 +129,15 @@ examples:
         interrupts = <0x0 0x18 0x0>, <0x0 0x19 0x0>;
 
         mdio2: mdio@e14 {
-           compatible = "brcm,genet-mdio-v4";
-           #address-cells = <1>;
-           #size-cells = <0>;
-           reg = <0xe14 0x8>;
+            compatible = "brcm,genet-mdio-v4";
+            #address-cells = <1>;
+            #size-cells = <0>;
+            reg = <0xe14 0x8>;
 
-           phy0: ethernet-phy@0 {
+            phy0: ethernet-phy@0 {
                 max-speed = <1000>;
                 reg = <0>;
                 compatible = "ethernet-phy-ieee802.3-c22";
-           };
+            };
         };
     };
diff --git a/dts/upstream/Bindings/net/brcm,mdio-mux-iproc.yaml b/dts/upstream/Bindings/net/brcm,mdio-mux-iproc.yaml
index af96b4fd89d..3f27746d9a5 100644
--- a/dts/upstream/Bindings/net/brcm,mdio-mux-iproc.yaml
+++ b/dts/upstream/Bindings/net/brcm,mdio-mux-iproc.yaml
@@ -38,43 +38,43 @@ unevaluatedProperties: false
 
 examples:
   - |
-    mdio_mux_iproc: mdio-mux@66020000 {
+    mdio-mux@66020000 {
         compatible = "brcm,mdio-mux-iproc";
         reg = <0x66020000 0x250>;
         #address-cells = <1>;
         #size-cells = <0>;
 
         mdio@0 {
-           reg = <0x0>;
-           #address-cells = <1>;
-           #size-cells = <0>;
-
-           pci_phy0: pci-phy@0 {
-              compatible = "brcm,ns2-pcie-phy";
-              reg = <0x0>;
-              #phy-cells = <0>;
-           };
+            reg = <0x0>;
+            #address-cells = <1>;
+            #size-cells = <0>;
+
+            pci-phy@0 {
+                compatible = "brcm,ns2-pcie-phy";
+                reg = <0x0>;
+                #phy-cells = <0>;
+            };
         };
 
         mdio@7 {
-           reg = <0x7>;
-           #address-cells = <1>;
-           #size-cells = <0>;
-
-           pci_phy1: pci-phy@0 {
-              compatible = "brcm,ns2-pcie-phy";
-              reg = <0x0>;
-              #phy-cells = <0>;
-           };
+            reg = <0x7>;
+            #address-cells = <1>;
+            #size-cells = <0>;
+
+            pci-phy@0 {
+                compatible = "brcm,ns2-pcie-phy";
+                reg = <0x0>;
+                #phy-cells = <0>;
+            };
         };
 
         mdio@10 {
-           reg = <0x10>;
-           #address-cells = <1>;
-           #size-cells = <0>;
+            reg = <0x10>;
+            #address-cells = <1>;
+            #size-cells = <0>;
 
-           gphy0: eth-phy@10 {
-              reg = <0x10>;
-           };
+            eth-phy@10 {
+                reg = <0x10>;
+            };
         };
     };
diff --git a/dts/upstream/Bindings/net/can/atmel,at91sam9263-can.yaml b/dts/upstream/Bindings/net/can/atmel,at91sam9263-can.yaml
new file mode 100644
index 00000000000..c818c01a718
--- /dev/null
+++ b/dts/upstream/Bindings/net/can/atmel,at91sam9263-can.yaml
@@ -0,0 +1,58 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/net/can/atmel,at91sam9263-can.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Microchip AT91 CAN Controller
+
+maintainers:
+  - Nicolas Ferre <nicolas.ferre@microchip.com>
+
+allOf:
+  - $ref: can-controller.yaml#
+
+properties:
+  compatible:
+    oneOf:
+      - enum:
+          - atmel,at91sam9263-can
+          - atmel,at91sam9x5-can
+      - items:
+          - enum:
+              - microchip,sam9x60-can
+          - const: atmel,at91sam9x5-can
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+
+  clocks:
+    maxItems: 1
+
+  clock-names:
+    items:
+      - const: can_clk
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - clocks
+  - clock-names
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/interrupt-controller/irq.h>
+    #include <dt-bindings/clock/at91.h>
+    can@f000c000 {
+          compatible = "atmel,at91sam9263-can";
+          reg = <0xf000c000 0x300>;
+          interrupts = <30 IRQ_TYPE_LEVEL_HIGH 3>;
+          clocks = <&pmc PMC_TYPE_PERIPHERAL 12>;
+          clock-names = "can_clk";
+    };
diff --git a/dts/upstream/Bindings/net/can/atmel-can.txt b/dts/upstream/Bindings/net/can/atmel-can.txt
deleted file mode 100644
index 218a3b3eb27..00000000000
--- a/dts/upstream/Bindings/net/can/atmel-can.txt
+++ /dev/null
@@ -1,15 +0,0 @@
-* AT91 CAN *
-
-Required properties:
-  - compatible: Should be "atmel,at91sam9263-can", "atmel,at91sam9x5-can" or
-    "microchip,sam9x60-can"
-  - reg: Should contain CAN controller registers location and length
-  - interrupts: Should contain IRQ line for the CAN controller
-
-Example:
-
-	can0: can@f000c000 {
-		compatible = "atmel,at91sam9x5-can";
-		reg = <0xf000c000 0x300>;
-		interrupts = <40 4 5>
-	};
diff --git a/dts/upstream/Bindings/net/can/bosch,c_can.yaml b/dts/upstream/Bindings/net/can/bosch,c_can.yaml
index 4d7d67ee175..ff1b59a0294 100644
--- a/dts/upstream/Bindings/net/can/bosch,c_can.yaml
+++ b/dts/upstream/Bindings/net/can/bosch,c_can.yaml
@@ -99,11 +99,11 @@ examples:
     #include <dt-bindings/reset/altr,rst-mgr.h>
 
     can@ffc00000 {
-       compatible = "bosch,d_can";
-       reg = <0xffc00000 0x1000>;
-       interrupts = <0 131 4>, <0 132 4>, <0 133 4>, <0 134 4>;
-       clocks = <&can0_clk>;
-       resets = <&rst CAN0_RESET>;
+        compatible = "bosch,d_can";
+        reg = <0xffc00000 0x1000>;
+        interrupts = <0 131 4>, <0 132 4>, <0 133 4>, <0 134 4>;
+        clocks = <&can0_clk>;
+        resets = <&rst CAN0_RESET>;
     };
   - |
     can@0 {
diff --git a/dts/upstream/Bindings/net/can/microchip,mcp2510.yaml b/dts/upstream/Bindings/net/can/microchip,mcp2510.yaml
index db446dde684..e0ec53bc10c 100644
--- a/dts/upstream/Bindings/net/can/microchip,mcp2510.yaml
+++ b/dts/upstream/Bindings/net/can/microchip,mcp2510.yaml
@@ -56,15 +56,15 @@ examples:
         #size-cells = <0>;
 
         can@1 {
-             compatible = "microchip,mcp2515";
-             reg = <1>;
-             clocks = <&clk24m>;
-             interrupt-parent = <&gpio4>;
-             interrupts = <13 IRQ_TYPE_LEVEL_LOW>;
-             vdd-supply = <&reg5v0>;
-             xceiver-supply = <&reg5v0>;
-             gpio-controller;
-             #gpio-cells = <2>;
+            compatible = "microchip,mcp2515";
+            reg = <1>;
+            clocks = <&clk24m>;
+            interrupt-parent = <&gpio4>;
+            interrupts = <13 IRQ_TYPE_LEVEL_LOW>;
+            vdd-supply = <&reg5v0>;
+            xceiver-supply = <&reg5v0>;
+            gpio-controller;
+            #gpio-cells = <2>;
         };
     };
 
diff --git a/dts/upstream/Bindings/net/can/microchip,mpfs-can.yaml b/dts/upstream/Bindings/net/can/microchip,mpfs-can.yaml
index 01e4d4a54df..1219c5cb601 100644
--- a/dts/upstream/Bindings/net/can/microchip,mpfs-can.yaml
+++ b/dts/upstream/Bindings/net/can/microchip,mpfs-can.yaml
@@ -15,7 +15,11 @@ allOf:
 
 properties:
   compatible:
-    const: microchip,mpfs-can
+    oneOf:
+      - items:
+          - const: microchip,pic64gx-can
+          - const: microchip,mpfs-can
+      - const: microchip,mpfs-can
 
   reg:
     maxItems: 1
diff --git a/dts/upstream/Bindings/net/can/renesas,rcar-canfd.yaml b/dts/upstream/Bindings/net/can/renesas,rcar-canfd.yaml
index 7c5ac5d2e88..f6884f6e59e 100644
--- a/dts/upstream/Bindings/net/can/renesas,rcar-canfd.yaml
+++ b/dts/upstream/Bindings/net/can/renesas,rcar-canfd.yaml
@@ -170,7 +170,7 @@ allOf:
             const: renesas,r8a779h0-canfd
     then:
       patternProperties:
-        "^channel[5-7]$": false
+        "^channel[4-7]$": false
     else:
       if:
         not:
diff --git a/dts/upstream/Bindings/net/can/st,stm32-bxcan.yaml b/dts/upstream/Bindings/net/can/st,stm32-bxcan.yaml
index de1d4298893..c7510b00954 100644
--- a/dts/upstream/Bindings/net/can/st,stm32-bxcan.yaml
+++ b/dts/upstream/Bindings/net/can/st,stm32-bxcan.yaml
@@ -63,7 +63,7 @@ properties:
     maxItems: 1
 
   st,gcan:
-    $ref: /schemas/types.yaml#/definitions/phandle-array
+    $ref: /schemas/types.yaml#/definitions/phandle
     description:
       The phandle to the gcan node which allows to access the 512-bytes
       SRAM memory shared by the two bxCAN cells (CAN1 primary and CAN2
diff --git a/dts/upstream/Bindings/net/can/tcan4x5x.txt b/dts/upstream/Bindings/net/can/tcan4x5x.txt
deleted file mode 100644
index 20c0572c985..00000000000
--- a/dts/upstream/Bindings/net/can/tcan4x5x.txt
+++ /dev/null
@@ -1,48 +0,0 @@
-Texas Instruments TCAN4x5x CAN Controller
-================================================
-
-This file provides device node information for the TCAN4x5x interface contains.
-
-Required properties:
-	- compatible:
-		"ti,tcan4552", "ti,tcan4x5x"
-		"ti,tcan4553", "ti,tcan4x5x" or
-		"ti,tcan4x5x"
-	- reg: 0
-	- #address-cells: 1
-	- #size-cells: 0
-	- spi-max-frequency: Maximum frequency of the SPI bus the chip can
-			     operate at should be less than or equal to 18 MHz.
-	- interrupt-parent: the phandle to the interrupt controller which provides
-                    the interrupt.
-	- interrupts: interrupt specification for data-ready.
-
-See Documentation/devicetree/bindings/net/can/bosch,m_can.yaml for additional
-required property details.
-
-Optional properties:
-	- reset-gpios: Hardwired output GPIO. If not defined then software
-		       reset.
-	- device-state-gpios: Input GPIO that indicates if the device is in
-			      a sleep state or if the device is active. Not
-			      available with tcan4552/4553.
-	- device-wake-gpios: Wake up GPIO to wake up the TCAN device. Not
-			     available with tcan4552/4553.
-	- wakeup-source: Leave the chip running when suspended, and configure
-			 the RX interrupt to wake up the device.
-
-Example:
-tcan4x5x: tcan4x5x@0 {
-		compatible = "ti,tcan4x5x";
-		reg = <0>;
-		#address-cells = <1>;
-		#size-cells = <1>;
-		spi-max-frequency = <10000000>;
-		bosch,mram-cfg = <0x0 0 0 16 0 0 1 1>;
-		interrupt-parent = <&gpio1>;
-		interrupts = <14 IRQ_TYPE_LEVEL_LOW>;
-		device-state-gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>;
-		device-wake-gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>;
-		reset-gpios = <&gpio1 27 GPIO_ACTIVE_HIGH>;
-		wakeup-source;
-};
diff --git a/dts/upstream/Bindings/net/can/ti,tcan4x5x.yaml b/dts/upstream/Bindings/net/can/ti,tcan4x5x.yaml
new file mode 100644
index 00000000000..384e15da271
--- /dev/null
+++ b/dts/upstream/Bindings/net/can/ti,tcan4x5x.yaml
@@ -0,0 +1,199 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/net/can/ti,tcan4x5x.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Texas Instruments TCAN4x5x CAN Controller
+
+maintainers:
+  - Marc Kleine-Budde <mkl@pengutronix.de>
+
+properties:
+  compatible:
+    oneOf:
+      - items:
+          - enum:
+              - ti,tcan4552
+              - ti,tcan4553
+          - const: ti,tcan4x5x
+      - const: ti,tcan4x5x
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+    description: The GPIO parent interrupt.
+
+  clocks:
+    maxItems: 1
+
+  clock-names:
+    items:
+      - const: cclk
+
+  reset-gpios:
+    description: Hardwired output GPIO. If not defined then software reset.
+    maxItems: 1
+
+  device-state-gpios:
+    description:
+      Input GPIO that indicates if the device is in a sleep state or if the
+      device is active. Not available with tcan4552/4553.
+    maxItems: 1
+
+  device-wake-gpios:
+    description:
+      Wake up GPIO to wake up the TCAN device.
+      Not available with tcan4552/4553.
+    maxItems: 1
+
+  bosch,mram-cfg:
+    description: |
+      Message RAM configuration data.
+      Multiple M_CAN instances can share the same Message RAM
+      and each element(e.g Rx FIFO or Tx Buffer and etc) number
+      in Message RAM is also configurable, so this property is
+      telling driver how the shared or private Message RAM are
+      used by this M_CAN controller.
+
+      The format should be as follows:
+      <offset sidf_elems xidf_elems rxf0_elems rxf1_elems rxb_elems txe_elems txb_elems>
+      The 'offset' is an address offset of the Message RAM where
+      the following elements start from. This is usually set to
+      0x0 if you're using a private Message RAM. The remain cells
+      are used to specify how many elements are used for each FIFO/Buffer.
+
+      M_CAN includes the following elements according to user manual:
+      11-bit Filter	0-128 elements / 0-128 words
+      29-bit Filter	0-64 elements / 0-128 words
+      Rx FIFO 0		0-64 elements / 0-1152 words
+      Rx FIFO 1		0-64 elements / 0-1152 words
+      Rx Buffers	0-64 elements / 0-1152 words
+      Tx Event FIFO	0-32 elements / 0-64 words
+      Tx Buffers	0-32 elements / 0-576 words
+
+      Please refer to 2.4.1 Message RAM Configuration in Bosch
+      M_CAN user manual for details.
+    $ref: /schemas/types.yaml#/definitions/int32-array
+    items:
+      - description: The 'offset' is an address offset of the Message RAM where
+          the following elements start from. This is usually set to 0x0 if
+          you're using a private Message RAM.
+        default: 0
+      - description: 11-bit Filter 0-128 elements / 0-128 words
+        minimum: 0
+        maximum: 128
+      - description: 29-bit Filter 0-64 elements / 0-128 words
+        minimum: 0
+        maximum: 64
+      - description: Rx FIFO 0 0-64 elements / 0-1152 words
+        minimum: 0
+        maximum: 64
+      - description: Rx FIFO 1 0-64 elements / 0-1152 words
+        minimum: 0
+        maximum: 64
+      - description: Rx Buffers 0-64 elements / 0-1152 words
+        minimum: 0
+        maximum: 64
+      - description: Tx Event FIFO 0-32 elements / 0-64 words
+        minimum: 0
+        maximum: 32
+      - description: Tx Buffers 0-32 elements / 0-576 words
+        minimum: 0
+        maximum: 32
+    minItems: 1
+
+  spi-max-frequency:
+    description:
+      Must be half or less of "clocks" frequency.
+    maximum: 18000000
+
+  ti,nwkrq-voltage-vio:
+    type: boolean
+    description:
+      nWKRQ Pin GPO buffer voltage configuration.
+      Set nWKRQ to use VIO voltage rail.
+      When not set nWKRQ will use internal voltage rail.
+
+  wakeup-source:
+    $ref: /schemas/types.yaml#/definitions/flag
+    description:
+      Enable CAN remote wakeup.
+
+allOf:
+  - $ref: can-controller.yaml#
+  - $ref: /schemas/spi/spi-peripheral-props.yaml#
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - ti,tcan4552
+              - ti,tcan4553
+    then:
+      properties:
+        device-state-gpios: false
+        device-wake-gpios: false
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - clocks
+  - clock-names
+  - bosch,mram-cfg
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/gpio/gpio.h>
+    #include <dt-bindings/interrupt-controller/irq.h>
+
+    spi {
+        #address-cells = <1>;
+        #size-cells = <0>;
+
+        can@0 {
+            compatible = "ti,tcan4x5x";
+            reg = <0>;
+            clocks = <&can0_osc>;
+            clock-names = "cclk";
+            pinctrl-names = "default";
+            pinctrl-0 = <&can0_pins>;
+            spi-max-frequency = <10000000>;
+            bosch,mram-cfg = <0x0 0 0 16 0 0 1 1>;
+            interrupt-parent = <&gpio1>;
+            interrupts = <14 IRQ_TYPE_LEVEL_LOW>;
+            device-state-gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>;
+            device-wake-gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>;
+            reset-gpios = <&gpio1 27 GPIO_ACTIVE_HIGH>;
+            ti,nwkrq-voltage-vio;
+            wakeup-source;
+        };
+    };
+  - |
+    #include <dt-bindings/gpio/gpio.h>
+    #include <dt-bindings/interrupt-controller/irq.h>
+
+    spi {
+        #address-cells = <1>;
+        #size-cells = <0>;
+
+        can@0 {
+            compatible = "ti,tcan4552", "ti,tcan4x5x";
+            reg = <0>;
+            clocks = <&can0_osc>;
+            clock-names = "cclk";
+            pinctrl-names = "default";
+            pinctrl-0 = <&can0_pins>;
+            spi-max-frequency = <10000000>;
+            bosch,mram-cfg = <0x0 0 0 16 0 0 1 1>;
+            interrupt-parent = <&gpio1>;
+            interrupts = <14 IRQ_TYPE_LEVEL_LOW>;
+            reset-gpios = <&gpio1 27 GPIO_ACTIVE_HIGH>;
+            wakeup-source;
+        };
+    };
diff --git a/dts/upstream/Bindings/net/microchip,sparx5-switch.yaml b/dts/upstream/Bindings/net/microchip,sparx5-switch.yaml
index dedfad52666..a73fc503690 100644
--- a/dts/upstream/Bindings/net/microchip,sparx5-switch.yaml
+++ b/dts/upstream/Bindings/net/microchip,sparx5-switch.yaml
@@ -129,6 +129,24 @@ properties:
             minimum: 0
             maximum: 383
 
+          rx-internal-delay-ps:
+            description:
+              RGMII Receive Clock Delay defined in pico seconds, used to select
+              the DLL phase shift between 1000 ps (45 degree shift at 1Gbps) and
+              3300 ps (147 degree shift at 1Gbps). A value of 0 ps will disable
+              any delay. The Default is no delay.
+            enum: [0, 1000, 1700, 2000, 2500, 3000, 3300]
+            default: 0
+
+          tx-internal-delay-ps:
+            description:
+              RGMII Transmit Clock Delay defined in pico seconds, used to select
+              the DLL phase shift between 1000 ps (45 degree shift at 1Gbps) and
+              3300 ps (147 degree shift at 1Gbps). A value of 0 ps will disable
+              any delay. The Default is no delay.
+            enum: [0, 1000, 1700, 2000, 2500, 3000, 3300]
+            default: 0
+
         required:
           - reg
           - phys
diff --git a/dts/upstream/Bindings/net/nxp,s32-dwmac.yaml b/dts/upstream/Bindings/net/nxp,s32-dwmac.yaml
new file mode 100644
index 00000000000..2b8b74c5fee
--- /dev/null
+++ b/dts/upstream/Bindings/net/nxp,s32-dwmac.yaml
@@ -0,0 +1,105 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright 2021-2024 NXP
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/net/nxp,s32-dwmac.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NXP S32G2xx/S32G3xx/S32R45 GMAC ethernet controller
+
+maintainers:
+  - Jan Petrous (OSS) <jan.petrous@oss.nxp.com>
+
+description:
+  This device is a Synopsys DWC IP, integrated on NXP S32G/R SoCs.
+  The SoC series S32G2xx and S32G3xx feature one DWMAC instance,
+  the SoC S32R45 has two instances. The devices can use RGMII/RMII/MII
+  interface over Pinctrl device or the output can be routed
+  to the embedded SerDes for SGMII connectivity.
+
+properties:
+  compatible:
+    oneOf:
+      - const: nxp,s32g2-dwmac
+      - items:
+          - enum:
+              - nxp,s32g3-dwmac
+              - nxp,s32r45-dwmac
+          - const: nxp,s32g2-dwmac
+
+  reg:
+    items:
+      - description: Main GMAC registers
+      - description: GMAC PHY mode control register
+
+  interrupts:
+    maxItems: 1
+
+  interrupt-names:
+    const: macirq
+
+  clocks:
+    items:
+      - description: Main GMAC clock
+      - description: Transmit clock
+      - description: Receive clock
+      - description: PTP reference clock
+
+  clock-names:
+    items:
+      - const: stmmaceth
+      - const: tx
+      - const: rx
+      - const: ptp_ref
+
+required:
+  - clocks
+  - clock-names
+
+allOf:
+  - $ref: snps,dwmac.yaml#
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+    #include <dt-bindings/interrupt-controller/irq.h>
+    #include <dt-bindings/phy/phy.h>
+    bus {
+      #address-cells = <2>;
+      #size-cells = <2>;
+
+      ethernet@4033c000 {
+        compatible = "nxp,s32g2-dwmac";
+        reg = <0x0 0x4033c000 0x0 0x2000>, /* gmac IP */
+              <0x0 0x4007c004 0x0 0x4>;    /* GMAC_0_CTRL_STS */
+        interrupt-parent = <&gic>;
+        interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
+        interrupt-names = "macirq";
+        snps,mtl-rx-config = <&mtl_rx_setup>;
+        snps,mtl-tx-config = <&mtl_tx_setup>;
+        clocks = <&clks 24>, <&clks 17>, <&clks 16>, <&clks 15>;
+        clock-names = "stmmaceth", "tx", "rx", "ptp_ref";
+        phy-mode = "rgmii-id";
+        phy-handle = <&phy0>;
+
+        mtl_rx_setup: rx-queues-config {
+          snps,rx-queues-to-use = <5>;
+        };
+
+        mtl_tx_setup: tx-queues-config {
+          snps,tx-queues-to-use = <5>;
+        };
+
+        mdio {
+          #address-cells = <1>;
+          #size-cells = <0>;
+          compatible = "snps,dwmac-mdio";
+
+          phy0: ethernet-phy@0 {
+            reg = <0>;
+          };
+        };
+      };
+    };
diff --git a/dts/upstream/Bindings/net/qcom,ethqos.yaml b/dts/upstream/Bindings/net/qcom,ethqos.yaml
index 0bcd593a7bd..e7ee0d9efed 100644
--- a/dts/upstream/Bindings/net/qcom,ethqos.yaml
+++ b/dts/upstream/Bindings/net/qcom,ethqos.yaml
@@ -7,7 +7,8 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
 title: Qualcomm Ethernet ETHQOS device
 
 maintainers:
-  - Bhupesh Sharma <bhupesh.sharma@linaro.org>
+  - Bjorn Andersson <andersson@kernel.org>
+  - Konrad Dybcio <konradybcio@kernel.org>
 
 description:
   dwmmac based Qualcomm ethernet devices which support Gigabit
@@ -21,12 +22,12 @@ properties:
     oneOf:
       - items:
           - enum:
-              - qcom,qcs8300-ethqos
-          - const: qcom,sa8775p-ethqos
+              - qcom,qcs615-ethqos
+          - const: qcom,qcs404-ethqos
       - items:
           - enum:
-              - qcom,qcs615-ethqos
-          - const: qcom,sm8150-ethqos
+              - qcom,qcs8300-ethqos
+          - const: qcom,sa8775p-ethqos
       - enum:
           - qcom,qcs404-ethqos
           - qcom,sa8775p-ethqos
diff --git a/dts/upstream/Bindings/net/qcom,ipa.yaml b/dts/upstream/Bindings/net/qcom,ipa.yaml
index 53cae71d995..1a46d80a66e 100644
--- a/dts/upstream/Bindings/net/qcom,ipa.yaml
+++ b/dts/upstream/Bindings/net/qcom,ipa.yaml
@@ -239,7 +239,7 @@ examples:
 
                 qcom,gsi-loader = "self";
                 memory-region = <&ipa_fw_mem>;
-                firmware-name = "qcom/sc7180-trogdor/modem/modem.mdt";
+                firmware-name = "qcom/sc7180-trogdor/modem/modem.mbn";
 
                 iommus = <&apps_smmu 0x440 0x0>,
                          <&apps_smmu 0x442 0x0>;
diff --git a/dts/upstream/Bindings/net/snps,dwmac.yaml b/dts/upstream/Bindings/net/snps,dwmac.yaml
index eb1f3ae41ab..91e75eb3f32 100644
--- a/dts/upstream/Bindings/net/snps,dwmac.yaml
+++ b/dts/upstream/Bindings/net/snps,dwmac.yaml
@@ -67,6 +67,7 @@ properties:
         - ingenic,x2000-mac
         - loongson,ls2k-dwmac
         - loongson,ls7a-dwmac
+        - nxp,s32g2-dwmac
         - qcom,qcs404-ethqos
         - qcom,sa8775p-ethqos
         - qcom,sc8280xp-ethqos
diff --git a/dts/upstream/Bindings/net/stm32-dwmac.yaml b/dts/upstream/Bindings/net/stm32-dwmac.yaml
index bf23838fe6e..85cea9966a2 100644
--- a/dts/upstream/Bindings/net/stm32-dwmac.yaml
+++ b/dts/upstream/Bindings/net/stm32-dwmac.yaml
@@ -154,56 +154,56 @@ examples:
     #include <dt-bindings/interrupt-controller/arm-gic.h>
     #include <dt-bindings/clock/stm32mp1-clks.h>
     //Example 1
-     ethernet0: ethernet@5800a000 {
-           compatible = "st,stm32mp1-dwmac", "snps,dwmac-4.20a";
-           reg = <0x5800a000 0x2000>;
-           reg-names = "stmmaceth";
-           interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
-           interrupt-names = "macirq";
-           clock-names = "stmmaceth",
-                     "mac-clk-tx",
-                     "mac-clk-rx",
-                     "ethstp",
-                     "eth-ck";
-           clocks = <&rcc ETHMAC>,
-                <&rcc ETHTX>,
-                <&rcc ETHRX>,
-                <&rcc ETHSTP>,
-                <&rcc ETHCK_K>;
-           st,syscon = <&syscfg 0x4>;
-           snps,pbl = <2>;
-           snps,axi-config = <&stmmac_axi_config_0>;
-           snps,tso;
-           phy-mode = "rgmii";
-       };
+    ethernet0: ethernet@5800a000 {
+        compatible = "st,stm32mp1-dwmac", "snps,dwmac-4.20a";
+        reg = <0x5800a000 0x2000>;
+        reg-names = "stmmaceth";
+        interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
+        interrupt-names = "macirq";
+        clock-names = "stmmaceth",
+                      "mac-clk-tx",
+                      "mac-clk-rx",
+                      "ethstp",
+                      "eth-ck";
+        clocks = <&rcc ETHMAC>,
+                 <&rcc ETHTX>,
+                 <&rcc ETHRX>,
+                 <&rcc ETHSTP>,
+                 <&rcc ETHCK_K>;
+        st,syscon = <&syscfg 0x4>;
+        snps,pbl = <2>;
+        snps,axi-config = <&stmmac_axi_config_0>;
+        snps,tso;
+        phy-mode = "rgmii";
+    };
 
   - |
     //Example 2 (MCU example)
-     ethernet1: ethernet@40028000 {
-           compatible = "st,stm32-dwmac", "snps,dwmac-3.50a";
-           reg = <0x40028000 0x8000>;
-           reg-names = "stmmaceth";
-           interrupts = <0 61 0>, <0 62 0>;
-           interrupt-names = "macirq", "eth_wake_irq";
-           clock-names = "stmmaceth", "mac-clk-tx", "mac-clk-rx";
-           clocks = <&rcc 0 25>, <&rcc 0 26>, <&rcc 0 27>;
-           st,syscon = <&syscfg 0x4>;
-           snps,pbl = <8>;
-           snps,mixed-burst;
-           phy-mode = "mii";
-       };
+    ethernet1: ethernet@40028000 {
+        compatible = "st,stm32-dwmac", "snps,dwmac-3.50a";
+        reg = <0x40028000 0x8000>;
+        reg-names = "stmmaceth";
+        interrupts = <0 61 0>, <0 62 0>;
+        interrupt-names = "macirq", "eth_wake_irq";
+        clock-names = "stmmaceth", "mac-clk-tx", "mac-clk-rx";
+        clocks = <&rcc 0 25>, <&rcc 0 26>, <&rcc 0 27>;
+        st,syscon = <&syscfg 0x4>;
+        snps,pbl = <8>;
+        snps,mixed-burst;
+        phy-mode = "mii";
+    };
 
   - |
     //Example 3
-     ethernet2: ethernet@40027000 {
-           compatible = "st,stm32-dwmac", "snps,dwmac-4.10a";
-           reg = <0x40028000 0x8000>;
-           reg-names = "stmmaceth";
-           interrupts = <61>;
-           interrupt-names = "macirq";
-           clock-names = "stmmaceth", "mac-clk-tx", "mac-clk-rx";
-           clocks = <&rcc 62>, <&rcc 61>, <&rcc 60>;
-           st,syscon = <&syscfg 0x4>;
-           snps,pbl = <8>;
-           phy-mode = "mii";
-       };
+    ethernet2: ethernet@40027000 {
+        compatible = "st,stm32-dwmac", "snps,dwmac-4.10a";
+        reg = <0x40028000 0x8000>;
+        reg-names = "stmmaceth";
+        interrupts = <61>;
+        interrupt-names = "macirq";
+        clock-names = "stmmaceth", "mac-clk-tx", "mac-clk-rx";
+        clocks = <&rcc 62>, <&rcc 61>, <&rcc 60>;
+        st,syscon = <&syscfg 0x4>;
+        snps,pbl = <8>;
+        phy-mode = "mii";
+    };
diff --git a/dts/upstream/Bindings/net/ti,davinci-mdio.yaml b/dts/upstream/Bindings/net/ti,davinci-mdio.yaml
index 53604fab0b7..08119b6880e 100644
--- a/dts/upstream/Bindings/net/ti,davinci-mdio.yaml
+++ b/dts/upstream/Bindings/net/ti,davinci-mdio.yaml
@@ -72,9 +72,9 @@ unevaluatedProperties: false
 examples:
   - |
     davinci_mdio: mdio@4a101000 {
-         compatible = "ti,davinci_mdio";
-         #address-cells = <1>;
-         #size-cells = <0>;
-         reg = <0x4a101000 0x1000>;
-         bus_freq = <1000000>;
+        compatible = "ti,davinci_mdio";
+        #address-cells = <1>;
+        #size-cells = <0>;
+        reg = <0x4a101000 0x1000>;
+        bus_freq = <1000000>;
     };
diff --git a/dts/upstream/Bindings/net/ti,dp83822.yaml b/dts/upstream/Bindings/net/ti,dp83822.yaml
index 784866ea392..50c24248df2 100644
--- a/dts/upstream/Bindings/net/ti,dp83822.yaml
+++ b/dts/upstream/Bindings/net/ti,dp83822.yaml
@@ -96,6 +96,32 @@ properties:
       - master
       - slave
 
+  ti,gpio2-clk-out:
+    description: |
+       DP83822 PHY only.
+       The GPIO2 pin on the DP83822 can be configured as clock output. When
+       omitted, the PHY's default will be left as is.
+
+       - 'mac-if': In MII mode the clock frequency is 25-MHz, in RMII Mode the
+         clock frequency is 50-MHz and in RGMII Mode the clock frequency is
+         25-MHz.
+       - 'xi': XI clock(pass-through clock from XI pin).
+       - 'int-ref': Internal reference clock 25-MHz.
+       - 'rmii-master-mode-ref': RMII master mode reference clock 50-MHz. RMII
+         master mode reference clock is identical to MAC IF clock in RMII master
+         mode.
+       - 'free-running': Free running clock 125-MHz.
+       - 'recovered': Recovered clock is a 125-MHz recovered clock from a
+         connected link partner.
+    $ref: /schemas/types.yaml#/definitions/string
+    enum:
+      - mac-if
+      - xi
+      - int-ref
+      - rmii-master-mode-ref
+      - free-running
+      - recovered
+
 required:
   - reg
 
@@ -110,6 +136,7 @@ examples:
         reg = <0>;
         rx-internal-delay-ps = <1>;
         tx-internal-delay-ps = <1>;
+        ti,gpio2-clk-out = "xi";
       };
     };
 
diff --git a/dts/upstream/Bindings/net/ti,k3-am654-cpsw-nuss.yaml b/dts/upstream/Bindings/net/ti,k3-am654-cpsw-nuss.yaml
index 02b6d32003c..b11894fbaec 100644
--- a/dts/upstream/Bindings/net/ti,k3-am654-cpsw-nuss.yaml
+++ b/dts/upstream/Bindings/net/ti,k3-am654-cpsw-nuss.yaml
@@ -302,16 +302,16 @@ examples:
                     ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
                 };
             };
-        };
 
-        cpts@3d000 {
-             compatible = "ti,am65-cpts";
-             reg = <0x0 0x3d000 0x0 0x400>;
-             clocks = <&k3_clks 18 2>;
-             clock-names = "cpts";
-             interrupts-extended = <&gic500 GIC_SPI 858 IRQ_TYPE_LEVEL_HIGH>;
-             interrupt-names = "cpts";
-             ti,cpts-ext-ts-inputs = <4>;
-             ti,cpts-periodic-outputs = <2>;
+            cpts@3d000 {
+                compatible = "ti,am65-cpts";
+                reg = <0x0 0x3d000 0x0 0x400>;
+                clocks = <&k3_clks 18 2>;
+                clock-names = "cpts";
+                interrupts-extended = <&gic500 GIC_SPI 858 IRQ_TYPE_LEVEL_HIGH>;
+                interrupt-names = "cpts";
+                ti,cpts-ext-ts-inputs = <4>;
+                ti,cpts-periodic-outputs = <2>;
+            };
         };
     };
diff --git a/dts/upstream/Bindings/net/ti,k3-am654-cpts.yaml b/dts/upstream/Bindings/net/ti,k3-am654-cpts.yaml
index 3888692275a..3572749147f 100644
--- a/dts/upstream/Bindings/net/ti,k3-am654-cpts.yaml
+++ b/dts/upstream/Bindings/net/ti,k3-am654-cpts.yaml
@@ -131,23 +131,23 @@ examples:
     #include <dt-bindings/interrupt-controller/arm-gic.h>
 
     cpts@310d0000 {
-         compatible = "ti,am65-cpts";
-         reg = <0x310d0000 0x400>;
-         reg-names = "cpts";
-         clocks = <&main_cpts_mux>;
-         clock-names = "cpts";
-         interrupts-extended = <&k3_irq 163 0 IRQ_TYPE_LEVEL_HIGH>;
-         interrupt-names = "cpts";
-         ti,cpts-periodic-outputs = <6>;
-         ti,cpts-ext-ts-inputs = <8>;
-
-         main_cpts_mux: refclk-mux {
-               #clock-cells = <0>;
-               clocks = <&k3_clks 118 5>, <&k3_clks 118 11>,
-                        <&k3_clks 157 91>, <&k3_clks 157 77>,
-                        <&k3_clks 157 102>, <&k3_clks 157 80>,
-                        <&k3_clks 120 3>, <&k3_clks 121 3>;
-               assigned-clocks = <&main_cpts_mux>;
-               assigned-clock-parents = <&k3_clks 118 11>;
-         };
+        compatible = "ti,am65-cpts";
+        reg = <0x310d0000 0x400>;
+        reg-names = "cpts";
+        clocks = <&main_cpts_mux>;
+        clock-names = "cpts";
+        interrupts-extended = <&k3_irq 163 0 IRQ_TYPE_LEVEL_HIGH>;
+        interrupt-names = "cpts";
+        ti,cpts-periodic-outputs = <6>;
+        ti,cpts-ext-ts-inputs = <8>;
+
+        main_cpts_mux: refclk-mux {
+            #clock-cells = <0>;
+            clocks = <&k3_clks 118 5>, <&k3_clks 118 11>,
+                     <&k3_clks 157 91>, <&k3_clks 157 77>,
+                     <&k3_clks 157 102>, <&k3_clks 157 80>,
+                     <&k3_clks 120 3>, <&k3_clks 121 3>;
+            assigned-clocks = <&main_cpts_mux>;
+            assigned-clock-parents = <&k3_clks 118 11>;
+        };
     };
diff --git a/dts/upstream/Bindings/net/wireless/marvell,sd8787.yaml b/dts/upstream/Bindings/net/wireless/marvell,sd8787.yaml
index 1715b22e0dc..930b700b73d 100644
--- a/dts/upstream/Bindings/net/wireless/marvell,sd8787.yaml
+++ b/dts/upstream/Bindings/net/wireless/marvell,sd8787.yaml
@@ -79,15 +79,14 @@ examples:
     #include <dt-bindings/interrupt-controller/irq.h>
 
     mmc {
-         #address-cells = <1>;
-         #size-cells = <0>;
-
-         wifi@1 {
-             compatible = "marvell,sd8897";
-             reg = <1>;
-             interrupt-parent = <&pio>;
-             interrupts = <38 IRQ_TYPE_LEVEL_LOW>;
-             marvell,wakeup-pin = <3>;
+        #address-cells = <1>;
+        #size-cells = <0>;
+
+        wifi@1 {
+            compatible = "marvell,sd8897";
+            reg = <1>;
+            interrupt-parent = <&pio>;
+            interrupts = <38 IRQ_TYPE_LEVEL_LOW>;
+            marvell,wakeup-pin = <3>;
         };
     };
-
diff --git a/dts/upstream/Bindings/net/wireless/qcom,ath10k.yaml b/dts/upstream/Bindings/net/wireless/qcom,ath10k.yaml
index 070c4c9b864..aace072e2d5 100644
--- a/dts/upstream/Bindings/net/wireless/qcom,ath10k.yaml
+++ b/dts/upstream/Bindings/net/wireless/qcom,ath10k.yaml
@@ -7,7 +7,6 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
 title: Qualcomm Technologies ath10k wireless devices
 
 maintainers:
-  - Kalle Valo <kvalo@kernel.org>
   - Jeff Johnson <jjohnson@kernel.org>
 
 description:
diff --git a/dts/upstream/Bindings/net/wireless/qcom,ath11k-pci.yaml b/dts/upstream/Bindings/net/wireless/qcom,ath11k-pci.yaml
index a71fdf05bc1..a4425cf196a 100644
--- a/dts/upstream/Bindings/net/wireless/qcom,ath11k-pci.yaml
+++ b/dts/upstream/Bindings/net/wireless/qcom,ath11k-pci.yaml
@@ -8,7 +8,6 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
 title: Qualcomm Technologies ath11k wireless devices (PCIe)
 
 maintainers:
-  - Kalle Valo <kvalo@kernel.org>
   - Jeff Johnson <jjohnson@kernel.org>
 
 description: |
diff --git a/dts/upstream/Bindings/net/wireless/qcom,ath11k.yaml b/dts/upstream/Bindings/net/wireless/qcom,ath11k.yaml
index ff5763dc66a..a69ffb7b3cb 100644
--- a/dts/upstream/Bindings/net/wireless/qcom,ath11k.yaml
+++ b/dts/upstream/Bindings/net/wireless/qcom,ath11k.yaml
@@ -8,7 +8,6 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
 title: Qualcomm Technologies ath11k wireless devices
 
 maintainers:
-  - Kalle Valo <kvalo@kernel.org>
   - Jeff Johnson <jjohnson@kernel.org>
 
 description: |
diff --git a/dts/upstream/Bindings/net/wireless/qcom,ath12k-wsi.yaml b/dts/upstream/Bindings/net/wireless/qcom,ath12k-wsi.yaml
new file mode 100644
index 00000000000..318f305405e
--- /dev/null
+++ b/dts/upstream/Bindings/net/wireless/qcom,ath12k-wsi.yaml
@@ -0,0 +1,203 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/net/wireless/qcom,ath12k-wsi.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Technologies ath12k wireless devices (PCIe) with WSI interface
+
+maintainers:
+  - Jeff Johnson <jjohnson@kernel.org>
+
+description: |
+  Qualcomm Technologies IEEE 802.11be PCIe devices with WSI interface.
+
+  The ath12k devices (QCN9274) feature WSI support. WSI stands for
+  WLAN Serial Interface. It is used for the exchange of specific
+  control information across radios based on the doorbell mechanism.
+  This WSI connection is essential to exchange control information
+  among these devices.
+
+  The WSI interface includes TX and RX ports, which are used to connect
+  multiple WSI-supported devices together, forming a WSI group.
+
+  Diagram to represent one WSI connection (one WSI group) among
+  three devices.
+
+           +-------+        +-------+        +-------+
+           | pcie1 |        | pcie2 |        | pcie3 |
+           |       |        |       |        |       |
+    +----->|  wsi  |------->|  wsi  |------->|  wsi  |-----+
+    |      | grp 0 |        | grp 0 |        | grp 0 |     |
+    |      +-------+        +-------+        +-------+     |
+    +------------------------------------------------------+
+
+  Diagram to represent two WSI connections (two separate WSI groups)
+  among four devices.
+
+       +-------+    +-------+          +-------+    +-------+
+       | pcie0 |    | pcie1 |          | pcie2 |    | pcie3 |
+       |       |    |       |          |       |    |       |
+   +-->|  wsi  |--->|  wsi  |--+   +-->|  wsi  |--->|  wsi  |--+
+   |   | grp 0 |    | grp 0 |  |   |   | grp 1 |    | grp 1 |  |
+   |   +-------+    +-------+  |   |   +-------+    +-------+  |
+   +---------------------------+   +---------------------------+
+
+properties:
+  compatible:
+    enum:
+      - pci17cb,1109  # QCN9274
+
+  reg:
+    maxItems: 1
+
+  qcom,ath12k-calibration-variant:
+    $ref: /schemas/types.yaml#/definitions/string
+    description:
+      String to uniquely identify variant of the calibration data for designs
+      with colliding bus and device ids
+
+  qcom,wsi-controller:
+    $ref: /schemas/types.yaml#/definitions/flag
+    description:
+      The WSI controller device in the WSI group aids (is capable) to
+      synchronize the Timing Synchronization Function (TSF) clock across
+      all devices in the WSI group.
+
+  ports:
+    $ref: /schemas/graph.yaml#/properties/ports
+    properties:
+      port@0:
+        $ref: /schemas/graph.yaml#/properties/port
+        description:
+          This is the TX port of WSI interface. It is attached to the RX
+          port of the next device in the WSI connection.
+
+      port@1:
+        $ref: /schemas/graph.yaml#/properties/port
+        description:
+          This is the RX port of WSI interface. It is attached to the TX
+          port of the previous device in the WSI connection.
+
+required:
+  - compatible
+  - reg
+
+additionalProperties: false
+
+examples:
+  - |
+    pcie {
+        #address-cells = <3>;
+        #size-cells = <2>;
+
+        pcie@0 {
+            device_type = "pci";
+            reg = <0x0 0x0 0x0 0x0 0x0>;
+            #address-cells = <3>;
+            #size-cells = <2>;
+            ranges;
+
+            wifi@0 {
+                compatible = "pci17cb,1109";
+                reg = <0x0 0x0 0x0 0x0 0x0>;
+
+                qcom,ath12k-calibration-variant = "RDP433_1";
+
+                ports {
+                    #address-cells = <1>;
+                    #size-cells = <0>;
+
+                    port@0 {
+                        reg = <0>;
+
+                        wifi1_wsi_tx: endpoint {
+                            remote-endpoint = <&wifi2_wsi_rx>;
+                        };
+                    };
+
+                    port@1 {
+                        reg = <1>;
+
+                        wifi1_wsi_rx: endpoint {
+                            remote-endpoint = <&wifi3_wsi_tx>;
+                        };
+                    };
+                };
+            };
+        };
+
+        pcie@1 {
+            device_type = "pci";
+            reg = <0x0 0x0 0x1 0x0 0x0>;
+            #address-cells = <3>;
+            #size-cells = <2>;
+            ranges;
+
+            wifi@0 {
+                compatible = "pci17cb,1109";
+                reg = <0x0 0x0 0x0 0x0 0x0>;
+
+                qcom,ath12k-calibration-variant = "RDP433_2";
+                qcom,wsi-controller;
+
+                ports {
+                    #address-cells = <1>;
+                    #size-cells = <0>;
+
+                    port@0 {
+                        reg = <0>;
+
+                        wifi2_wsi_tx: endpoint {
+                            remote-endpoint = <&wifi3_wsi_rx>;
+                        };
+                    };
+
+                    port@1 {
+                        reg = <1>;
+
+                        wifi2_wsi_rx: endpoint {
+                            remote-endpoint = <&wifi1_wsi_tx>;
+                        };
+                    };
+                };
+            };
+        };
+
+        pcie@2 {
+            device_type = "pci";
+            reg = <0x0 0x0 0x2 0x0 0x0>;
+            #address-cells = <3>;
+            #size-cells = <2>;
+            ranges;
+
+            wifi@0 {
+                compatible = "pci17cb,1109";
+                reg = <0x0 0x0 0x0 0x0 0x0>;
+
+                qcom,ath12k-calibration-variant = "RDP433_3";
+
+                ports {
+                    #address-cells = <1>;
+                    #size-cells = <0>;
+
+                    port@0 {
+                        reg = <0>;
+
+                        wifi3_wsi_tx: endpoint {
+                            remote-endpoint = <&wifi1_wsi_rx>;
+                        };
+                    };
+
+                    port@1 {
+                        reg = <1>;
+
+                        wifi3_wsi_rx: endpoint {
+                            remote-endpoint = <&wifi2_wsi_tx>;
+                        };
+                    };
+                };
+            };
+        };
+    };
diff --git a/dts/upstream/Bindings/net/wireless/qcom,ath12k.yaml b/dts/upstream/Bindings/net/wireless/qcom,ath12k.yaml
index 1b5884015b1..9e557cb838c 100644
--- a/dts/upstream/Bindings/net/wireless/qcom,ath12k.yaml
+++ b/dts/upstream/Bindings/net/wireless/qcom,ath12k.yaml
@@ -9,7 +9,6 @@ title: Qualcomm Technologies ath12k wireless devices (PCIe)
 
 maintainers:
   - Jeff Johnson <quic_jjohnson@quicinc.com>
-  - Kalle Valo <kvalo@kernel.org>
 
 description:
   Qualcomm Technologies IEEE 802.11be PCIe devices.
diff --git a/dts/upstream/Bindings/nvmem/qcom,qfprom.yaml b/dts/upstream/Bindings/nvmem/qcom,qfprom.yaml
index 80845c722ae..39c209249c9 100644
--- a/dts/upstream/Bindings/nvmem/qcom,qfprom.yaml
+++ b/dts/upstream/Bindings/nvmem/qcom,qfprom.yaml
@@ -20,18 +20,23 @@ properties:
           - qcom,apq8064-qfprom
           - qcom,apq8084-qfprom
           - qcom,ipq5332-qfprom
+          - qcom,ipq5424-qfprom
           - qcom,ipq6018-qfprom
           - qcom,ipq8064-qfprom
           - qcom,ipq8074-qfprom
           - qcom,ipq9574-qfprom
           - qcom,msm8226-qfprom
           - qcom,msm8916-qfprom
+          - qcom,msm8917-qfprom
           - qcom,msm8974-qfprom
           - qcom,msm8976-qfprom
           - qcom,msm8996-qfprom
           - qcom,msm8998-qfprom
           - qcom,qcm2290-qfprom
           - qcom,qcs404-qfprom
+          - qcom,qcs615-qfprom
+          - qcom,qcs8300-qfprom
+          - qcom,sar2130p-qfprom
           - qcom,sc7180-qfprom
           - qcom,sc7280-qfprom
           - qcom,sc8280xp-qfprom
diff --git a/dts/upstream/Bindings/nvmem/rmem.yaml b/dts/upstream/Bindings/nvmem/rmem.yaml
index 1ec0d09bcaf..85f9f5de390 100644
--- a/dts/upstream/Bindings/nvmem/rmem.yaml
+++ b/dts/upstream/Bindings/nvmem/rmem.yaml
@@ -16,6 +16,7 @@ properties:
   compatible:
     items:
       - enum:
+          - mobileye,eyeq5-bootloader-config
           - raspberrypi,bootloader-config
           - raspberrypi,bootloader-public-key
       - const: nvmem-rmem
diff --git a/dts/upstream/Bindings/nvmem/sprd,sc2731-efuse.yaml b/dts/upstream/Bindings/nvmem/sprd,sc2731-efuse.yaml
index dc25fe3d184..8672bde24a9 100644
--- a/dts/upstream/Bindings/nvmem/sprd,sc2731-efuse.yaml
+++ b/dts/upstream/Bindings/nvmem/sprd,sc2731-efuse.yaml
@@ -36,33 +36,4 @@ allOf:
   - $ref: nvmem-deprecated-cells.yaml#
 
 unevaluatedProperties: false
-
-examples:
-  - |
-    pmic {
-      #address-cells = <1>;
-      #size-cells = <0>;
-
-      efuse@380 {
-        compatible = "sprd,sc2731-efuse";
-        reg = <0x380>;
-        hwlocks = <&hwlock 12>;
-        #address-cells = <1>;
-        #size-cells = <1>;
-
-        /* Data cells */
-        fgu_calib: calib@6 {
-          reg = <0x6 0x2>;
-          bits = <0 9>;
-        };
-
-        adc_big_scale: calib@24 {
-          reg = <0x24 0x2>;
-        };
-
-        adc_small_scale: calib@26 {
-          reg = <0x26 0x2>;
-        };
-      };
-    };
 ...
diff --git a/dts/upstream/Bindings/opp/allwinner,sun50i-h6-operating-points.yaml b/dts/upstream/Bindings/opp/allwinner,sun50i-h6-operating-points.yaml
index ec5e424bb3c..75ab552f6ec 100644
--- a/dts/upstream/Bindings/opp/allwinner,sun50i-h6-operating-points.yaml
+++ b/dts/upstream/Bindings/opp/allwinner,sun50i-h6-operating-points.yaml
@@ -22,6 +22,7 @@ allOf:
 properties:
   compatible:
     enum:
+      - allwinner,sun50i-a100-operating-points
       - allwinner,sun50i-h6-operating-points
       - allwinner,sun50i-h616-operating-points
 
diff --git a/dts/upstream/Bindings/pci/fsl,imx6q-pcie-common.yaml b/dts/upstream/Bindings/pci/fsl,imx6q-pcie-common.yaml
index a8b34f58f8f..cddbe21f99f 100644
--- a/dts/upstream/Bindings/pci/fsl,imx6q-pcie-common.yaml
+++ b/dts/upstream/Bindings/pci/fsl,imx6q-pcie-common.yaml
@@ -17,11 +17,11 @@ description:
 properties:
   clocks:
     minItems: 3
-    maxItems: 4
+    maxItems: 5
 
   clock-names:
     minItems: 3
-    maxItems: 4
+    maxItems: 5
 
   num-lanes:
     const: 1
diff --git a/dts/upstream/Bindings/pci/fsl,imx6q-pcie-ep.yaml b/dts/upstream/Bindings/pci/fsl,imx6q-pcie-ep.yaml
index 84ca12e8b25..0b3526de1d6 100644
--- a/dts/upstream/Bindings/pci/fsl,imx6q-pcie-ep.yaml
+++ b/dts/upstream/Bindings/pci/fsl,imx6q-pcie-ep.yaml
@@ -22,6 +22,7 @@ properties:
       - fsl,imx8mm-pcie-ep
       - fsl,imx8mq-pcie-ep
       - fsl,imx8mp-pcie-ep
+      - fsl,imx8q-pcie-ep
       - fsl,imx95-pcie-ep
 
   clocks:
@@ -78,6 +79,20 @@ allOf:
       properties:
         compatible:
           enum:
+            - fsl,imx8q-pcie-ep
+    then:
+      properties:
+        reg:
+          maxItems: 2
+        reg-names:
+          items:
+            - const: dbi
+            - const: addr_space
+
+  - if:
+      properties:
+        compatible:
+          enum:
             - fsl,imx95-pcie-ep
     then:
       properties:
@@ -103,13 +118,21 @@ allOf:
       properties:
         clocks:
           minItems: 4
+          maxItems: 4
         clock-names:
           items:
             - const: pcie
             - const: pcie_bus
             - const: pcie_phy
             - const: pcie_aux
-    else:
+
+  - if:
+      properties:
+        compatible:
+          enum:
+            - fsl,imx8mm-pcie-ep
+            - fsl,imx8mp-pcie-ep
+    then:
       properties:
         clocks:
           maxItems: 3
@@ -119,6 +142,20 @@ allOf:
             - const: pcie_bus
             - const: pcie_aux
 
+  - if:
+      properties:
+        compatible:
+          enum:
+            - fsl,imxq-pcie-ep
+    then:
+      properties:
+        clocks:
+          maxItems: 3
+        clock-names:
+          items:
+            - const: dbi
+            - const: mstr
+            - const: slv
 
 unevaluatedProperties: false
 
diff --git a/dts/upstream/Bindings/pci/fsl,imx6q-pcie.yaml b/dts/upstream/Bindings/pci/fsl,imx6q-pcie.yaml
index 1e05c560d79..4c76cd3f98a 100644
--- a/dts/upstream/Bindings/pci/fsl,imx6q-pcie.yaml
+++ b/dts/upstream/Bindings/pci/fsl,imx6q-pcie.yaml
@@ -40,10 +40,11 @@ properties:
       - description: PCIe PHY clock.
       - description: Additional required clock entry for imx6sx-pcie,
            imx6sx-pcie-ep, imx8mq-pcie, imx8mq-pcie-ep.
+      - description: PCIe reference clock.
 
   clock-names:
     minItems: 3
-    maxItems: 4
+    maxItems: 5
 
   interrupts:
     items:
@@ -127,7 +128,7 @@ allOf:
     then:
       properties:
         clocks:
-          minItems: 4
+          maxItems: 4
         clock-names:
           items:
             - const: pcie
@@ -140,11 +141,10 @@ allOf:
         compatible:
           enum:
             - fsl,imx8mq-pcie
-            - fsl,imx95-pcie
     then:
       properties:
         clocks:
-          minItems: 4
+          maxItems: 4
         clock-names:
           items:
             - const: pcie
@@ -200,6 +200,23 @@ allOf:
             - const: mstr
             - const: slv
 
+  - if:
+      properties:
+        compatible:
+          enum:
+            - fsl,imx95-pcie
+    then:
+      properties:
+        clocks:
+          maxItems: 5
+        clock-names:
+          items:
+            - const: pcie
+            - const: pcie_bus
+            - const: pcie_phy
+            - const: pcie_aux
+            - const: ref
+
 unevaluatedProperties: false
 
 examples:
diff --git a/dts/upstream/Bindings/pci/layerscape-pcie-gen4.txt b/dts/upstream/Bindings/pci/layerscape-pcie-gen4.txt
deleted file mode 100644
index b40fb5d15d3..00000000000
--- a/dts/upstream/Bindings/pci/layerscape-pcie-gen4.txt
+++ /dev/null
@@ -1,52 +0,0 @@
-NXP Layerscape PCIe Gen4 controller
-
-This PCIe controller is based on the Mobiveil PCIe IP and thus inherits all
-the common properties defined in mobiveil-pcie.txt.
-
-Required properties:
-- compatible: should contain the platform identifier such as:
-  "fsl,lx2160a-pcie"
-- reg: base addresses and lengths of the PCIe controller register blocks.
-  "csr_axi_slave": Bridge config registers
-  "config_axi_slave": PCIe controller registers
-- interrupts: A list of interrupt outputs of the controller. Must contain an
-  entry for each entry in the interrupt-names property.
-- interrupt-names: It could include the following entries:
-  "intr": The interrupt that is asserted for controller interrupts
-  "aer": Asserted for aer interrupt when chip support the aer interrupt with
-	 none MSI/MSI-X/INTx mode,but there is interrupt line for aer.
-  "pme": Asserted for pme interrupt when chip support the pme interrupt with
-	 none MSI/MSI-X/INTx mode,but there is interrupt line for pme.
-- dma-coherent: Indicates that the hardware IP block can ensure the coherency
-  of the data transferred from/to the IP block. This can avoid the software
-  cache flush/invalid actions, and improve the performance significantly.
-- msi-parent : See the generic MSI binding described in
-  Documentation/devicetree/bindings/interrupt-controller/msi.txt.
-
-Example:
-
-	pcie@3400000 {
-		compatible = "fsl,lx2160a-pcie";
-		reg = <0x00 0x03400000 0x0 0x00100000   /* controller registers */
-		       0x80 0x00000000 0x0 0x00001000>; /* configuration space */
-		reg-names = "csr_axi_slave", "config_axi_slave";
-		interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */
-			     <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
-			     <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
-		interrupt-names = "aer", "pme", "intr";
-		#address-cells = <3>;
-		#size-cells = <2>;
-		device_type = "pci";
-		apio-wins = <8>;
-		ppio-wins = <8>;
-		dma-coherent;
-		bus-range = <0x0 0xff>;
-		msi-parent = <&its>;
-		ranges = <0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>;
-		#interrupt-cells = <1>;
-		interrupt-map-mask = <0 0 0 7>;
-		interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
-				<0000 0 0 2 &gic 0 0 GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
-				<0000 0 0 3 &gic 0 0 GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
-				<0000 0 0 4 &gic 0 0 GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
-	};
diff --git a/dts/upstream/Bindings/pci/mbvl,gpex40-pcie.yaml b/dts/upstream/Bindings/pci/mbvl,gpex40-pcie.yaml
new file mode 100644
index 00000000000..d286b77921e
--- /dev/null
+++ b/dts/upstream/Bindings/pci/mbvl,gpex40-pcie.yaml
@@ -0,0 +1,173 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pci/mbvl,gpex40-pcie.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Mobiveil AXI PCIe Host Bridge
+
+maintainers:
+  - Frank Li <Frank Li@nxp.com>
+
+description:
+  Mobiveil's GPEX 4.0 is a PCIe Gen4 host bridge IP. This configurable IP
+  has up to 8 outbound and inbound windows for address translation.
+
+  NXP Layerscape PCIe Gen4 controller (Deprecated) base on Mobiveil's GPEX 4.0.
+
+properties:
+  compatible:
+    enum:
+      - fsl,lx2160a-pcie
+      - mbvl,gpex40-pcie
+
+  reg:
+    items:
+      - description: PCIe controller registers
+      - description: Bridge config registers
+      - description: GPIO registers to control slot power
+      - description: MSI registers
+    minItems: 2
+
+  reg-names:
+    items:
+      - const: csr_axi_slave
+      - const: config_axi_slave
+      - const: gpio_slave
+      - const: apb_csr
+    minItems: 2
+
+  apio-wins:
+    $ref: /schemas/types.yaml#/definitions/uint32
+    description: |
+      number of requested APIO outbound windows
+        1. Config window
+        2. Memory window
+    default: 2
+    maximum: 256
+
+  ppio-wins:
+    $ref: /schemas/types.yaml#/definitions/uint32
+    description: number of requested PPIO inbound windows
+    default: 1
+    maximum: 256
+
+  interrupt-controller: true
+
+  "#interrupt-cells":
+    const: 1
+
+  interrupts:
+    minItems: 1
+    maxItems: 3
+
+  interrupt-names:
+    minItems: 1
+    maxItems: 3
+
+  dma-coherent: true
+
+  msi-parent: true
+
+required:
+  - compatible
+  - reg
+  - reg-names
+
+allOf:
+  - $ref: /schemas/pci/pci-host-bridge.yaml#
+  - if:
+      properties:
+        compatible:
+          enum:
+            - fsl,lx2160a-pcie
+    then:
+      properties:
+        reg:
+          maxItems: 2
+
+        reg-names:
+          maxItems: 2
+
+        interrupts:
+          minItems: 3
+
+        interrupt-names:
+          items:
+            - const: aer
+            - const: pme
+            - const: intr
+    else:
+      properties:
+        dma-coherent: false
+        msi-parent: false
+        interrupts:
+          maxItems: 1
+        interrupt-names: false
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+    pcie@b0000000 {
+        compatible = "mbvl,gpex40-pcie";
+        reg = <0xb0000000 0x00010000>,
+              <0xa0000000 0x00001000>,
+              <0xff000000 0x00200000>,
+              <0xb0010000 0x00001000>;
+        reg-names = "csr_axi_slave",
+                    "config_axi_slave",
+                    "gpio_slave",
+                    "apb_csr";
+        ranges = <0x83000000 0 0x00000000 0xa8000000 0 0x8000000>;
+        #address-cells = <3>;
+        #size-cells = <2>;
+        device_type = "pci";
+        apio-wins = <2>;
+        ppio-wins = <1>;
+        bus-range = <0x00 0xff>;
+        interrupt-controller;
+        #interrupt-cells = <1>;
+        interrupt-parent = <&gic>;
+        interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
+        interrupt-map-mask = <0 0 0 7>;
+        interrupt-map = <0 0 0 0 &pci_express 0>,
+                        <0 0 0 1 &pci_express 1>,
+                        <0 0 0 2 &pci_express 2>,
+                        <0 0 0 3 &pci_express 3>;
+    };
+
+  - |
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+    soc {
+        #address-cells = <2>;
+        #size-cells = <2>;
+        pcie@3400000 {
+            compatible = "fsl,lx2160a-pcie";
+            reg = <0x00 0x03400000 0x0 0x00100000   /* controller registers */
+                   0x80 0x00000000 0x0 0x00001000>; /* configuration space */
+            reg-names = "csr_axi_slave", "config_axi_slave";
+            ranges = <0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>;
+            interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */
+                         <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
+                         <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
+            interrupt-names = "aer", "pme", "intr";
+            #address-cells = <3>;
+            #size-cells = <2>;
+            device_type = "pci";
+            apio-wins = <8>;
+            ppio-wins = <8>;
+            dma-coherent;
+            bus-range = <0x00 0xff>;
+            msi-parent = <&its>;
+            #interrupt-cells = <1>;
+            interrupt-map-mask = <0 0 0 7>;
+            interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
+                            <0000 0 0 2 &gic 0 0 GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
+                            <0000 0 0 3 &gic 0 0 GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
+                            <0000 0 0 4 &gic 0 0 GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
+        };
+    };
diff --git a/dts/upstream/Bindings/pci/microchip,pcie-host.yaml b/dts/upstream/Bindings/pci/microchip,pcie-host.yaml
index 2e154756970..103574d18db 100644
--- a/dts/upstream/Bindings/pci/microchip,pcie-host.yaml
+++ b/dts/upstream/Bindings/pci/microchip,pcie-host.yaml
@@ -50,6 +50,8 @@ properties:
     items:
       pattern: '^fic[0-3]$'
 
+  dma-coherent: true
+
   ranges:
     minItems: 1
     maxItems: 3
diff --git a/dts/upstream/Bindings/pci/mobiveil-pcie.txt b/dts/upstream/Bindings/pci/mobiveil-pcie.txt
deleted file mode 100644
index 64156993e05..00000000000
--- a/dts/upstream/Bindings/pci/mobiveil-pcie.txt
+++ /dev/null
@@ -1,72 +0,0 @@
-* Mobiveil AXI PCIe Root Port Bridge DT description
-
-Mobiveil's GPEX 4.0 is a PCIe Gen4 root port bridge IP. This configurable IP
-has up to 8 outbound and inbound windows for the address translation.
-
-Required properties:
-- #address-cells: Address representation for root ports, set to <3>
-- #size-cells: Size representation for root ports, set to <2>
-- #interrupt-cells: specifies the number of cells needed to encode an
-	interrupt source. The value must be 1.
-- compatible: Should contain "mbvl,gpex40-pcie"
-- reg: Should contain PCIe registers location and length
-	Mandatory:
-	"config_axi_slave": PCIe controller registers
-	"csr_axi_slave"	  : Bridge config registers
-	Optional:
-	"gpio_slave"	  : GPIO registers to control slot power
-	"apb_csr"	  : MSI registers
-
-- device_type: must be "pci"
-- apio-wins : number of requested apio outbound windows
-		default 2 outbound windows are configured -
-		1. Config window
-		2. Memory window
-- ppio-wins : number of requested ppio inbound windows
-		default 1 inbound memory window is configured.
-- bus-range: PCI bus numbers covered
-- interrupt-controller: identifies the node as an interrupt controller
-- #interrupt-cells: specifies the number of cells needed to encode an
-	interrupt source. The value must be 1.
-- interrupts: The interrupt line of the PCIe controller
-		last cell of this field is set to 4 to
-		denote it as IRQ_TYPE_LEVEL_HIGH type interrupt.
-- interrupt-map-mask,
-	interrupt-map: standard PCI properties to define the mapping of the
-	PCI interface to interrupt numbers.
-- ranges: ranges for the PCI memory regions (I/O space region is not
-	supported by hardware)
-	Please refer to the standard PCI bus binding document for a more
-	detailed explanation
-
-
-Example:
-++++++++
-	pcie0: pcie@a0000000 {
-		#address-cells = <3>;
-		#size-cells = <2>;
-		compatible = "mbvl,gpex40-pcie";
-		reg =	<0xa0000000 0x00001000>,
-			<0xb0000000 0x00010000>,
-			<0xff000000 0x00200000>,
-			<0xb0010000 0x00001000>;
-		reg-names =	"config_axi_slave",
-				"csr_axi_slave",
-				"gpio_slave",
-				"apb_csr";
-		device_type = "pci";
-		apio-wins = <2>;
-		ppio-wins = <1>;
-		bus-range = <0x00000000 0x000000ff>;
-		interrupt-controller;
-		interrupt-parent = <&gic>;
-		#interrupt-cells = <1>;
-		interrupts = < 0 89 4 >;
-		interrupt-map-mask = <0 0 0 7>;
-		interrupt-map = <0 0 0 0 &pci_express 0>,
-				<0 0 0 1 &pci_express 1>,
-				<0 0 0 2 &pci_express 2>,
-				<0 0 0 3 &pci_express 3>;
-		ranges = < 0x83000000 0 0x00000000 0xa8000000 0 0x8000000>;
-
-	};
diff --git a/dts/upstream/Bindings/pci/qcom,pcie-sm8550.yaml b/dts/upstream/Bindings/pci/qcom,pcie-sm8550.yaml
index 2b5498a35dc..dbce671ba01 100644
--- a/dts/upstream/Bindings/pci/qcom,pcie-sm8550.yaml
+++ b/dts/upstream/Bindings/pci/qcom,pcie-sm8550.yaml
@@ -57,9 +57,10 @@ properties:
 
   interrupts:
     minItems: 8
-    maxItems: 8
+    maxItems: 9
 
   interrupt-names:
+    minItems: 8
     items:
       - const: msi0
       - const: msi1
@@ -69,6 +70,7 @@ properties:
       - const: msi5
       - const: msi6
       - const: msi7
+      - const: global
 
   resets:
     minItems: 1
@@ -139,9 +141,10 @@ examples:
                          <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
                          <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
                          <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
-                         <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
+                         <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
+                         <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
             interrupt-names = "msi0", "msi1", "msi2", "msi3",
-                              "msi4", "msi5", "msi6", "msi7";
+                              "msi4", "msi5", "msi6", "msi7", "global";
             #interrupt-cells = <1>;
             interrupt-map-mask = <0 0 0 0x7>;
             interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
diff --git a/dts/upstream/Bindings/pci/qcom,pcie.yaml b/dts/upstream/Bindings/pci/qcom,pcie.yaml
index bd87f6b49d6..7235d6554cf 100644
--- a/dts/upstream/Bindings/pci/qcom,pcie.yaml
+++ b/dts/upstream/Bindings/pci/qcom,pcie.yaml
@@ -32,6 +32,10 @@ properties:
           - qcom,pcie-sdm845
           - qcom,pcie-sdx55
       - items:
+          - enum:
+              - qcom,pcie-ipq5424
+          - const: qcom,pcie-ipq9574
+      - items:
           - const: qcom,pcie-msm8998
           - const: qcom,pcie-msm8996
 
diff --git a/dts/upstream/Bindings/pci/xilinx-versal-cpm.yaml b/dts/upstream/Bindings/pci/xilinx-versal-cpm.yaml
index 989fb0fa257..b63a759ec2d 100644
--- a/dts/upstream/Bindings/pci/xilinx-versal-cpm.yaml
+++ b/dts/upstream/Bindings/pci/xilinx-versal-cpm.yaml
@@ -17,6 +17,7 @@ properties:
     enum:
       - xlnx,versal-cpm-host-1.00
       - xlnx,versal-cpm5-host
+      - xlnx,versal-cpm5-host1
 
   reg:
     items:
diff --git a/dts/upstream/Bindings/phy/phy-rockchip-naneng-combphy.yaml b/dts/upstream/Bindings/phy/phy-rockchip-naneng-combphy.yaml
index d3cd7997879..1b3de6678c0 100644
--- a/dts/upstream/Bindings/phy/phy-rockchip-naneng-combphy.yaml
+++ b/dts/upstream/Bindings/phy/phy-rockchip-naneng-combphy.yaml
@@ -13,6 +13,7 @@ properties:
   compatible:
     enum:
       - rockchip,rk3568-naneng-combphy
+      - rockchip,rk3576-naneng-combphy
       - rockchip,rk3588-naneng-combphy
 
   reg:
diff --git a/dts/upstream/Bindings/phy/qcom,ipq8074-qmp-pcie-phy.yaml b/dts/upstream/Bindings/phy/qcom,ipq8074-qmp-pcie-phy.yaml
index 58ce2d91d28..f6080468741 100644
--- a/dts/upstream/Bindings/phy/qcom,ipq8074-qmp-pcie-phy.yaml
+++ b/dts/upstream/Bindings/phy/qcom,ipq8074-qmp-pcie-phy.yaml
@@ -15,12 +15,21 @@ description:
 
 properties:
   compatible:
-    enum:
-      - qcom,ipq6018-qmp-pcie-phy
-      - qcom,ipq8074-qmp-gen3-pcie-phy
-      - qcom,ipq8074-qmp-pcie-phy
-      - qcom,ipq9574-qmp-gen3x1-pcie-phy
-      - qcom,ipq9574-qmp-gen3x2-pcie-phy
+    oneOf:
+      - enum:
+          - qcom,ipq6018-qmp-pcie-phy
+          - qcom,ipq8074-qmp-gen3-pcie-phy
+          - qcom,ipq8074-qmp-pcie-phy
+          - qcom,ipq9574-qmp-gen3x1-pcie-phy
+          - qcom,ipq9574-qmp-gen3x2-pcie-phy
+      - items:
+          - enum:
+              - qcom,ipq5424-qmp-gen3x1-pcie-phy
+          - const: qcom,ipq9574-qmp-gen3x1-pcie-phy
+      - items:
+          - enum:
+              - qcom,ipq5424-qmp-gen3x2-pcie-phy
+          - const: qcom,ipq9574-qmp-gen3x2-pcie-phy
 
   reg:
     items:
diff --git a/dts/upstream/Bindings/phy/qcom,qusb2-phy.yaml b/dts/upstream/Bindings/phy/qcom,qusb2-phy.yaml
index 4aed4b5d65e..39851ba9de4 100644
--- a/dts/upstream/Bindings/phy/qcom,qusb2-phy.yaml
+++ b/dts/upstream/Bindings/phy/qcom,qusb2-phy.yaml
@@ -18,6 +18,7 @@ properties:
     oneOf:
       - items:
           - enum:
+              - qcom,ipq5424-qusb2-phy
               - qcom,ipq6018-qusb2-phy
               - qcom,ipq8074-qusb2-phy
               - qcom,ipq9574-qusb2-phy
diff --git a/dts/upstream/Bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml b/dts/upstream/Bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml
index 13fdf5f1beb..89391649e0b 100644
--- a/dts/upstream/Bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml
+++ b/dts/upstream/Bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml
@@ -16,8 +16,10 @@ description:
 properties:
   compatible:
     enum:
+      - qcom,qcs615-qmp-gen3x1-pcie-phy
       - qcom,sa8775p-qmp-gen4x2-pcie-phy
       - qcom,sa8775p-qmp-gen4x4-pcie-phy
+      - qcom,sar2130p-qmp-gen3x2-pcie-phy
       - qcom,sc8180x-qmp-pcie-phy
       - qcom,sc8280xp-qmp-gen3x1-pcie-phy
       - qcom,sc8280xp-qmp-gen3x2-pcie-phy
@@ -32,6 +34,7 @@ properties:
       - qcom,sm8250-qmp-gen3x2-pcie-phy
       - qcom,sm8250-qmp-modem-pcie-phy
       - qcom,sm8350-qmp-gen3x1-pcie-phy
+      - qcom,sm8350-qmp-gen3x2-pcie-phy
       - qcom,sm8450-qmp-gen3x1-pcie-phy
       - qcom,sm8450-qmp-gen4x2-pcie-phy
       - qcom,sm8550-qmp-gen3x2-pcie-phy
@@ -139,6 +142,7 @@ allOf:
         compatible:
           contains:
             enum:
+              - qcom,sar2130p-qmp-gen3x2-pcie-phy
               - qcom,sc8180x-qmp-pcie-phy
               - qcom,sdm845-qhp-pcie-phy
               - qcom,sdm845-qmp-pcie-phy
@@ -149,6 +153,7 @@ allOf:
               - qcom,sm8250-qmp-gen3x2-pcie-phy
               - qcom,sm8250-qmp-modem-pcie-phy
               - qcom,sm8350-qmp-gen3x1-pcie-phy
+              - qcom,sm8350-qmp-gen3x2-pcie-phy
               - qcom,sm8450-qmp-gen3x1-pcie-phy
               - qcom,sm8450-qmp-gen3x2-pcie-phy
               - qcom,sm8550-qmp-gen3x2-pcie-phy
@@ -167,6 +172,7 @@ allOf:
         compatible:
           contains:
             enum:
+              - qcom,qcs615-qmp-gen3x1-pcie-phy
               - qcom,sc8280xp-qmp-gen3x1-pcie-phy
               - qcom,sc8280xp-qmp-gen3x2-pcie-phy
               - qcom,sc8280xp-qmp-gen3x4-pcie-phy
diff --git a/dts/upstream/Bindings/phy/qcom,sc8280xp-qmp-usb3-uni-phy.yaml b/dts/upstream/Bindings/phy/qcom,sc8280xp-qmp-usb3-uni-phy.yaml
index baf5134ea3d..a1b55168e05 100644
--- a/dts/upstream/Bindings/phy/qcom,sc8280xp-qmp-usb3-uni-phy.yaml
+++ b/dts/upstream/Bindings/phy/qcom,sc8280xp-qmp-usb3-uni-phy.yaml
@@ -16,6 +16,7 @@ description:
 properties:
   compatible:
     enum:
+      - qcom,ipq5424-qmp-usb3-phy
       - qcom,ipq6018-qmp-usb3-phy
       - qcom,ipq8074-qmp-usb3-phy
       - qcom,ipq9574-qmp-usb3-phy
@@ -89,6 +90,7 @@ allOf:
         compatible:
           contains:
             enum:
+              - qcom,ipq5424-qmp-usb3-phy
               - qcom,ipq6018-qmp-usb3-phy
               - qcom,ipq8074-qmp-usb3-phy
               - qcom,ipq9574-qmp-usb3-phy
diff --git a/dts/upstream/Bindings/phy/qcom,sc8280xp-qmp-usb43dp-phy.yaml b/dts/upstream/Bindings/phy/qcom,sc8280xp-qmp-usb43dp-phy.yaml
index 2d0d7e9e643..358a6736a95 100644
--- a/dts/upstream/Bindings/phy/qcom,sc8280xp-qmp-usb43dp-phy.yaml
+++ b/dts/upstream/Bindings/phy/qcom,sc8280xp-qmp-usb43dp-phy.yaml
@@ -16,6 +16,7 @@ description:
 properties:
   compatible:
     enum:
+      - qcom,sar2130p-qmp-usb3-dp-phy
       - qcom,sc7180-qmp-usb3-dp-phy
       - qcom,sc7280-qmp-usb3-dp-phy
       - qcom,sc8180x-qmp-usb3-dp-phy
@@ -127,6 +128,7 @@ allOf:
       properties:
         compatible:
           enum:
+            - qcom,sar2130p-qmp-usb3-dp-phy
             - qcom,sc8280xp-qmp-usb43dp-phy
             - qcom,sm6350-qmp-usb3-dp-phy
             - qcom,sm8550-qmp-usb3-dp-phy
diff --git a/dts/upstream/Bindings/pinctrl/allwinner,sun4i-a10-pinctrl.yaml b/dts/upstream/Bindings/pinctrl/allwinner,sun4i-a10-pinctrl.yaml
index 45024057031..990b7876542 100644
--- a/dts/upstream/Bindings/pinctrl/allwinner,sun4i-a10-pinctrl.yaml
+++ b/dts/upstream/Bindings/pinctrl/allwinner,sun4i-a10-pinctrl.yaml
@@ -44,6 +44,7 @@ properties:
       - allwinner,sun8i-r40-pinctrl
       - allwinner,sun8i-v3-pinctrl
       - allwinner,sun8i-v3s-pinctrl
+      - allwinner,sun8i-v853-pinctrl
       - allwinner,sun9i-a80-pinctrl
       - allwinner,sun9i-a80-r-pinctrl
       - allwinner,sun20i-d1-pinctrl
@@ -183,6 +184,18 @@ allOf:
       properties:
         compatible:
           enum:
+            - allwinner,sun8i-v853-pinctrl
+
+    then:
+      properties:
+        interrupts:
+          minItems: 8
+          maxItems: 8
+
+  - if:
+      properties:
+        compatible:
+          enum:
             - allwinner,sun20i-d1-pinctrl
 
     then:
diff --git a/dts/upstream/Bindings/pinctrl/atmel,at91rm9200-pinctrl.yaml b/dts/upstream/Bindings/pinctrl/atmel,at91rm9200-pinctrl.yaml
index 1bb386b4203..a7ede29c144 100644
--- a/dts/upstream/Bindings/pinctrl/atmel,at91rm9200-pinctrl.yaml
+++ b/dts/upstream/Bindings/pinctrl/atmel,at91rm9200-pinctrl.yaml
@@ -145,40 +145,40 @@ additionalProperties:
 
 examples:
   - |
-     #include <dt-bindings/clock/at91.h>
-     #include <dt-bindings/interrupt-controller/irq.h>
-     #include <dt-bindings/pinctrl/at91.h>
-
-     pinctrl@fffff400 {
-       #address-cells = <1>;
-       #size-cells = <1>;
-       compatible = "atmel,at91rm9200-pinctrl", "simple-mfd";
-       ranges = <0xfffff400 0xfffff400 0x600>;
-
-       atmel,mux-mask = <
-         /*    A         B     */
-         0xffffffff 0xffc00c3b  /* pioA */
-         0xffffffff 0x7fff3ccf  /* pioB */
-         0xffffffff 0x007fffff  /* pioC */
-         >;
-
-       dbgu {
-         pinctrl_dbgu: dbgu-0 {
-           atmel,pins =
-             <AT91_PIOB 14 AT91_PERIPH_A AT91_PINCTRL_PULL_UP
-              AT91_PIOB 15 AT91_PERIPH_A AT91_PINCTRL_NONE>;
-         };
-       };
-
-       pioA: gpio@fffff400 {
-         compatible = "atmel,at91rm9200-gpio";
-         reg = <0xfffff400 0x200>;
-         interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
-         #gpio-cells = <2>;
-         gpio-controller;
-         interrupt-controller;
-         #interrupt-cells = <2>;
-         clocks = <&pmc PMC_TYPE_PERIPHERAL 2>;
-       };
-     };
+    #include <dt-bindings/clock/at91.h>
+    #include <dt-bindings/interrupt-controller/irq.h>
+    #include <dt-bindings/pinctrl/at91.h>
+
+    pinctrl@fffff400 {
+        #address-cells = <1>;
+        #size-cells = <1>;
+        compatible = "atmel,at91rm9200-pinctrl", "simple-mfd";
+        ranges = <0xfffff400 0xfffff400 0x600>;
+
+        atmel,mux-mask = <
+          /*    A         B     */
+          0xffffffff 0xffc00c3b  /* pioA */
+          0xffffffff 0x7fff3ccf  /* pioB */
+          0xffffffff 0x007fffff  /* pioC */
+          >;
+
+        dbgu {
+            dbgu-0 {
+                atmel,pins =
+                  <AT91_PIOB 14 AT91_PERIPH_A AT91_PINCTRL_PULL_UP
+                   AT91_PIOB 15 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+            };
+        };
+
+        gpio@fffff400 {
+            compatible = "atmel,at91rm9200-gpio";
+            reg = <0xfffff400 0x200>;
+            interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
+            #gpio-cells = <2>;
+            gpio-controller;
+            interrupt-controller;
+            #interrupt-cells = <2>;
+            clocks = <&pmc PMC_TYPE_PERIPHERAL 2>;
+        };
+    };
 ...
diff --git a/dts/upstream/Bindings/pinctrl/mediatek,mt7988-pinctrl.yaml b/dts/upstream/Bindings/pinctrl/mediatek,mt7988-pinctrl.yaml
new file mode 100644
index 00000000000..26dfe7e7735
--- /dev/null
+++ b/dts/upstream/Bindings/pinctrl/mediatek,mt7988-pinctrl.yaml
@@ -0,0 +1,575 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pinctrl/mediatek,mt7988-pinctrl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MediaTek MT7988 Pin Controller
+
+maintainers:
+  - Sean Wang <sean.wang@kernel.org>
+
+description:
+  The MediaTek's MT7988 Pin controller is used to control SoC pins.
+
+properties:
+  compatible:
+    enum:
+      - mediatek,mt7988-pinctrl
+
+  reg:
+    minItems: 7
+    maxItems: 7
+
+  reg-names:
+    items:
+      - const: gpio
+      - const: iocfg_tr
+      - const: iocfg_br
+      - const: iocfg_rb
+      - const: iocfg_lb
+      - const: iocfg_tl
+      - const: eint
+
+  gpio-controller: true
+
+  "#gpio-cells":
+    const: 2
+
+  gpio-ranges:
+    minItems: 1
+    maxItems: 5
+    description:
+      GPIO valid number range.
+
+  interrupt-controller: true
+
+  interrupts:
+    maxItems: 1
+
+  "#interrupt-cells":
+    const: 2
+
+allOf:
+  - $ref: pinctrl.yaml#
+
+required:
+  - compatible
+  - reg
+  - reg-names
+  - gpio-controller
+  - "#gpio-cells"
+
+patternProperties:
+  '-pins$':
+    type: object
+    additionalProperties: false
+
+    properties:
+      mux:
+        type: object
+        additionalProperties: false
+        $ref: /schemas/pinctrl/pinmux-node.yaml
+        description: |
+          pinmux configuration nodes.
+
+          The following table shows the effective values of "group", "function"
+          properties and chip pinout pins
+
+          groups               function           pins (in pin#)
+          ---------------------------------------------------------------------
+          "tops_jtag0_0"       "jtag"             0, 1, 2, 3, 4
+          "wo0_jtag"           "jtag"             50, 51, 52, 53, 54
+          "wo1_jtag"           "jtag"             50, 51, 52, 53, 54
+          "wo2_jtag"           "jtag"             50, 51, 52, 53, 54
+          "jtag"               "jtag"             58, 59, 60, 61, 62
+          "tops_jtag0_1"       "jtag"             58, 59, 60, 61, 62
+          "int_usxgmii"        "int_usxgmii"      2, 3
+          "pwm0"               "pwm"              57
+          "pwm1"               "pwm"              21
+          "pwm2"               "pwm"              80
+          "pwm2_0"             "pwm"              58
+          "pwm3"               "pwm"              81
+          "pwm3_0"             "pwm"              59
+          "pwm4"               "pwm"              82
+          "pwm4_0"             "pwm"              60
+          "pwm5"               "pwm"              83
+          "pwm5_0"             "pwm"              61
+          "pwm6"               "pwm"              69
+          "pwm6_0"             "pwm"              62
+          "pwm7"               "pwm"              70
+          "pwm7_0"             "pwm"              4
+          "dfd"                "dfd"              0, 1, 2, 3, 4
+          "xfi_phy0_i2c0"      "i2c"              0, 1
+          "xfi_phy1_i2c0"      "i2c"              0, 1
+          "xfi_phy_pll_i2c0"   "i2c"              3, 4
+          "xfi_phy_pll_i2c1"   "i2c"              3, 4
+          "i2c0_0"             "i2c"              5, 6
+          "i2c1_sfp"           "i2c"              5, 6
+          "xfi_pextp_phy0_i2c" "i2c"              5, 6
+          "xfi_pextp_phy1_i2c" "i2c"              5, 6
+          "i2c0_1"             "i2c"              15, 16
+          "u30_phy_i2c0"       "i2c"              15, 16
+          "u32_phy_i2c0"       "i2c"              15, 16
+          "xfi_phy0_i2c1"      "i2c"              15, 16
+          "xfi_phy1_i2c1"      "i2c"              15, 16
+          "xfi_phy_pll_i2c2"   "i2c"              15, 16
+          "i2c1_0"             "i2c"              17, 18
+          "u30_phy_i2c1"       "i2c"              17, 18
+          "u32_phy_i2c1"       "i2c"              17, 18
+          "xfi_phy_pll_i2c3"   "i2c"              17, 18
+          "sgmii0_i2c"         "i2c"              17, 18
+          "sgmii1_i2c"         "i2c"              17, 18
+          "i2c1_2"             "i2c"              69, 70
+          "i2c2_0"             "i2c"              69, 70
+          "i2c2_1"             "i2c"              71, 72
+          "mdc_mdio0"          "eth"              5, 6
+          "2p5g_ext_mdio"      "eth"              28, 29
+          "gbe_ext_mdio"       "eth"              30, 31
+          "mdc_mdio1"          "eth"              69, 70
+          "pcie_wake_n0_0"     "pcie"             7
+          "pcie_clk_req_n0_0"  "pcie"             8
+          "pcie_wake_n3_0"     "pcie"             9
+          "pcie_clk_req_n3"    "pcie"             10
+          "pcie_clk_req_n0_1"  "pcie"             10
+          "pcie_p0_phy_i2c"    "pcie"             7, 8
+          "pcie_p1_phy_i2c"    "pcie"             7, 8
+          "pcie_p3_phy_i2c"    "pcie"             9, 10
+          "pcie_p2_phy_i2c"    "pcie"             7, 8
+          "ckm_phy_i2c"        "pcie"             9, 10
+          "pcie_wake_n0_1"     "pcie"             13
+          "pcie_wake_n3_1"     "pcie"             14
+          "pcie_2l_0_pereset"  "pcie"             19
+          "pcie_1l_1_pereset"  "pcie"             20
+          "pcie_clk_req_n2_1"  "pcie"             63
+          "pcie_2l_1_pereset"  "pcie"             73
+          "pcie_1l_0_pereset"  "pcie"             74
+          "pcie_wake_n1_0"     "pcie"             75
+          "pcie_clk_req_n1"    "pcie"             76
+          "pcie_wake_n2_0"     "pcie"             77
+          "pcie_clk_req_n2_0"  "pcie"             78
+          "pcie_wake_n2_1"     "pcie"             79
+          "pmic"               "pmic"             11
+          "watchdog"           "watchdog"         12
+          "spi0_wp_hold"       "spi"              22, 23
+          "spi0"               "spi"              24, 25, 26, 27
+          "spi1"               "spi"              28, 29, 30, 31
+          "spi2"               "spi"              32, 33, 34, 35
+          "spi2_wp_hold"       "spi"              36, 37
+          "snfi"               "flash"            22, 23, 24, 25, 26, 27
+          "emmc_45"            "flash"            21, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37
+          "sdcard"             "flash"            32, 33, 34, 35, 36, 37
+          "emmc_51"            "flash"            38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49
+          "uart2"              "uart"             0, 1, 2, 3
+          "tops_uart0_0"       "uart"             22, 23
+          "uart2_0"            "uart"             28, 29, 30, 31
+          "uart1_0"            "uart"             32, 33, 34, 35
+          "uart2_1"            "uart"             32, 33, 34, 35
+          "net_wo0_uart_txd_0" "uart"             28
+          "net_wo1_uart_txd_0" "uart"             29
+          "net_wo2_uart_txd_0" "uart"             30
+          "tops_uart1_0"       "uart"             28, 29
+          "tops_uart0_1"       "uart"             30, 31
+          "tops_uart1_1"       "uart"             36, 37
+          "uart0"              "uart"             55, 56
+          "tops_uart0_2"       "uart"             55, 56
+          "uart2_2"            "uart"             50, 51, 52, 53
+          "uart1_1"            "uart"             58, 59, 60, 61
+          "uart2_3"            "uart"             58, 59, 60, 61
+          "uart1_2"            "uart"             80, 81, 82, 83
+          "uart1_2_lite"       "uart"             80, 81
+          "tops_uart1_2"       "uart"             80, 81
+          "net_wo0_uart_txd_1" "uart"             80
+          "net_wo1_uart_txd_1" "uart"             81
+          "net_wo2_uart_txd_1" "uart"             82
+          "udi"                "udi"              32, 33, 34, 35, 36
+          "i2s"                "audio"            50, 51, 52, 53, 54
+          "pcm"                "audio"            50, 51, 52, 53
+          "gbe0_led1"          "led"              58
+          "gbe1_led1"          "led"              59
+          "gbe2_led1"          "led"              60
+          "gbe3_led1"          "led"              61
+          "2p5gbe_led1"        "led"              62
+          "gbe0_led0"          "led"              64
+          "gbe1_led0"          "led"              65
+          "gbe2_led0"          "led"              66
+          "gbe3_led0"          "led"              67
+          "2p5gbe_led0"        "led"              68
+          "drv_vbus_p1"        "usb"              63
+          "drv_vbus"           "usb"              79
+
+        properties:
+          function:
+            description:
+              A string containing the name of the function to mux to the group.
+            enum: [audio, dfd, eth, flash, i2c, int_usxgmii, jtag, led, pcie, pmic, pwm, spi,
+                   uart, udi, usb, watchdog]
+          groups:
+            description:
+              An array of strings. Each string contains the name of a group.
+
+        required:
+          - function
+          - groups
+
+        allOf:
+          - if:
+              properties:
+                function:
+                  const: audio
+            then:
+              properties:
+                groups:
+                  enum: [i2s, pcm]
+          - if:
+              properties:
+                function:
+                  const: jtag
+            then:
+              properties:
+                groups:
+                  enum: [jtag, tops_jtag0_0, tops_jtag0_1, wo0_jtag, wo1_jtag, wo2_jtag]
+          - if:
+              properties:
+                function:
+                  const: int_usxgmii
+            then:
+              properties:
+                groups:
+                  const: int_usxgmii
+          - if:
+              properties:
+                function:
+                  const: dfd
+            then:
+              properties:
+                groups:
+                  const: dfd
+          - if:
+              properties:
+                function:
+                  const: flash
+            then:
+              properties:
+                groups:
+                  enum: [emmc_45, emmc_51, sdcard, snfi]
+          - if:
+              properties:
+                function:
+                  const: eth
+            then:
+              properties:
+                groups:
+                  enum: [2p5g_ext_mdio, gbe_ext_mdio, mdc_mdio0, mdc_mdio1]
+          - if:
+              properties:
+                function:
+                  const: i2c
+            then:
+              properties:
+                groups:
+                  enum: [xfi_phy0_i2c0, xfi_phy1_i2c0, xfi_phy_pll_i2c0,
+                         xfi_phy_pll_i2c1, i2c0_0, i2c1_sfp, xfi_pextp_phy0_i2c,
+                         xfi_pextp_phy1_i2c, i2c0_1, u30_phy_i2c0, u32_phy_i2c0,
+                         xfi_phy0_i2c1, xfi_phy1_i2c1, xfi_phy_pll_i2c2, i2c1_0,
+                         u30_phy_i2c1, u32_phy_i2c1, xfi_phy_pll_i2c3, sgmii0_i2c,
+                         sgmii1_i2c, i2c1_2, i2c2_0, i2c2_1]
+          - if:
+              properties:
+                function:
+                  const: led
+            then:
+              properties:
+                groups:
+                  enum: [2p5gbe_led0, 2p5gbe_led1, gbe0_led0, gbe0_led1, gbe1_led0, gbe1_led1,
+                         gbe2_led0, gbe2_led1, gbe3_led0, gbe3_led1, wf5g_led0, wf5g_led1]
+          - if:
+              properties:
+                function:
+                  const: pcie
+            then:
+              properties:
+                groups:
+                  items:
+                    enum: [pcie_wake_n0_0, pcie_clk_req_n0_0, pcie_wake_n3_0,
+                           pcie_clk_req_n3, pcie_p0_phy_i2c, pcie_p1_phy_i2c,
+                           pcie_p3_phy_i2c, pcie_p2_phy_i2c, ckm_phy_i2c,
+                           pcie_wake_n0_1, pcie_wake_n3_1, pcie_2l_0_pereset,
+                           pcie_1l_1_pereset, pcie_clk_req_n2_1, pcie_2l_1_pereset,
+                           pcie_1l_0_pereset, pcie_wake_n1_0, pcie_clk_req_n1,
+                           pcie_wake_n2_0, pcie_clk_req_n2_0, pcie_wake_n2_1,
+                           pcie_clk_req_n0_1]
+                  maxItems: 3
+          - if:
+              properties:
+                function:
+                  const: pmic
+            then:
+              properties:
+                groups:
+                  const: pmic
+          - if:
+              properties:
+                function:
+                  const: pwm
+            then:
+              properties:
+                groups:
+                  items:
+                    enum: [pwm0, pwm1, pwm2, pwm2_0, pwm3, pwm3_0, pwm4, pwm4_0, pwm5, pwm5_0,
+                           pwm6, pwm6_0, pwm7, pwm7_0]
+                  maxItems: 2
+          - if:
+              properties:
+                function:
+                  const: spi
+            then:
+              properties:
+                groups:
+                  items:
+                    enum: [spi0, spi0_wp_hold, spi1, spi2, spi2_wp_hold]
+                  maxItems: 2
+          - if:
+              properties:
+                function:
+                  const: uart
+            then:
+              properties:
+                groups:
+                  items:
+                    enum: [net_wo0_uart_txd_0, net_wo0_uart_txd_1, net_wo1_uart_txd_0,
+                           net_wo1_uart_txd_1, net_wo2_uart_txd_0, net_wo2_uart_txd_1,
+                           tops_uart0_0, tops_uart0_1, tops_uart0_2, tops_uart1_0,
+                           tops_uart1_1, tops_uart1_2, uart0, uart1_0, uart1_1, uart1_2,
+                           uart1_2_lite, uart2, uart2_0, uart2_1, uart2_3]
+                  maxItems: 2
+          - if:
+              properties:
+                function:
+                  const: watchdog
+            then:
+              properties:
+                groups:
+                  const: watchdog
+          - if:
+              properties:
+                function:
+                  const: udi
+            then:
+              properties:
+                groups:
+                  const: udi
+          - if:
+              properties:
+                function:
+                  const: usb
+            then:
+              properties:
+                groups:
+                  items:
+                    enum: [drv_vbus, drv_vbus_p1]
+                  maxItems: 1
+
+    patternProperties:
+      '^conf(-[-a-z]*)?$':
+        type: object
+        additionalProperties: false
+        description:
+          pinconf configuration nodes.
+        $ref: /schemas/pinctrl/pincfg-node.yaml
+
+        properties:
+          pins:
+            description:
+              An array of strings. Each string contains the name of a pin.
+            items:
+              enum: [UART2_RXD, UART2_TXD, UART2_CTS, UART2_RTS, GPIO_A, SMI_0_MDC,
+                     SMI_0_MDIO, PCIE30_2L_0_WAKE_N, PCIE30_2L_0_CLKREQ_N,
+                     PCIE30_1L_1_WAKE_N, PCIE30_1L_1_CLKREQ_N, GPIO_P, WATCHDOG,
+                     GPIO_RESET, GPIO_WPS, PMIC_I2C_SCL, PMIC_I2C_SDA, I2C_1_SCL,
+                     I2C_1_SDA, PCIE30_2L_0_PRESET_N, PCIE30_1L_1_PRESET_N, PWMD1,
+                     SPI0_WP, SPI0_HOLD, SPI0_CSB, SPI0_MISO, SPI0_MOSI, SPI0_CLK,
+                     SPI1_CSB, SPI1_MISO, SPI1_MOSI, SPI1_CLK, SPI2_CLK, SPI2_MOSI,
+                     SPI2_MISO, SPI2_CSB, SPI2_HOLD, SPI2_WP, EMMC_RSTB, EMMC_DSL,
+                     EMMC_CK, EMMC_CMD, EMMC_DATA_7, EMMC_DATA_6, EMMC_DATA_5,
+                     EMMC_DATA_4, EMMC_DATA_3, EMMC_DATA_2, EMMC_DATA_1,
+                     EMMC_DATA_0, PCM_FS_I2S_LRCK, PCM_CLK_I2S_BCLK,
+                     PCM_DRX_I2S_DIN, PCM_DTX_I2S_DOUT, PCM_MCK_I2S_MCLK,
+                     UART0_RXD, UART0_TXD, PWMD0, JTAG_JTDI, JTAG_JTDO, JTAG_JTMS,
+                     JTAG_JTCLK, JTAG_JTRST_N, USB_DRV_VBUS_P1, LED_A, LED_B, LED_C,
+                     LED_D, LED_E, GPIO_B, GPIO_C, I2C_2_SCL, I2C_2_SDA,
+                     PCIE30_2L_1_PRESET_N, PCIE30_1L_0_PRESET_N,
+                     PCIE30_2L_1_WAKE_N, PCIE30_2L_1_CLKREQ_N,
+                     PCIE30_1L_0_WAKE_N, PCIE30_1L_0_CLKREQ_N, USB_DRV_VBUS_P0,
+                     UART1_RXD, UART1_TXD, UART1_CTS, UART1_RTS]
+            maxItems: 84
+
+          bias-disable: true
+
+          bias-pull-up:
+            oneOf:
+              - type: boolean
+                description: normal pull up.
+              - enum: [100, 101, 102, 103]
+                description:
+                  PUPD/R1/R0 pull down type. See MTK_PUPD_SET_R1R0 defines in
+                  dt-bindings/pinctrl/mt65xx.h.
+
+          bias-pull-down:
+            oneOf:
+              - type: boolean
+                description: normal pull down.
+              - enum: [100, 101, 102, 103]
+                description:
+                  PUPD/R1/R0 pull down type. See MTK_PUPD_SET_R1R0 defines in
+                  dt-bindings/pinctrl/mt65xx.h.
+
+          input-enable: true
+
+          input-disable: true
+
+          output-enable: true
+
+          output-low: true
+
+          output-high: true
+
+          input-schmitt-enable: true
+
+          input-schmitt-disable: true
+
+          drive-strength:
+            enum: [2, 4, 6, 8, 10, 12, 14, 16]
+
+          mediatek,pull-up-adv:
+            description: |
+              Valid arguments for 'mediatek,pull-up-adv' are '0', '1', '2', '3'
+              Pull up settings for 2 pull resistors, R0 and R1. Valid arguments
+              are described as below:
+              0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled.
+              1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled.
+              2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled.
+              3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled.
+            $ref: /schemas/types.yaml#/definitions/uint32
+            enum: [0, 1, 2, 3]
+
+          mediatek,pull-down-adv:
+            description: |
+              Valid arguments for 'mediatek,pull-up-adv' are '0', '1', '2', '3'
+              Pull down settings for 2 pull resistors, R0 and R1. Valid arguments
+              are described as below:
+              0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled.
+              1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled.
+              2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled.
+              3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled.
+            $ref: /schemas/types.yaml#/definitions/uint32
+            enum: [0, 1, 2, 3]
+
+        required:
+          - pins
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/interrupt-controller/irq.h>
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+    #include <dt-bindings/pinctrl/mt65xx.h>
+
+    soc {
+      #address-cells = <2>;
+      #size-cells = <2>;
+
+      pio: pinctrl@1001f000 {
+        compatible = "mediatek,mt7988-pinctrl";
+        reg = <0 0x1001f000 0 0x1000>,
+        <0 0x11c10000 0 0x1000>,
+        <0 0x11d00000 0 0x1000>,
+        <0 0x11d20000 0 0x1000>,
+        <0 0x11e00000 0 0x1000>,
+        <0 0x11f00000 0 0x1000>,
+        <0 0x1000b000 0 0x1000>;
+        reg-names = "gpio", "iocfg_tr",
+          "iocfg_br", "iocfg_rb",
+          "iocfg_lb", "iocfg_tl", "eint";
+        gpio-controller;
+        #gpio-cells = <2>;
+        gpio-ranges = <&pio 0 0 84>;
+        interrupt-controller;
+        interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
+        interrupt-parent = <&gic>;
+        #interrupt-cells = <2>;
+
+        i2c0_pins: i2c0-g0-pins {
+          mux {
+            function = "i2c";
+            groups = "i2c0_1";
+          };
+        };
+
+        mdio0_pins: mdio0-pins {
+          mux {
+            function = "eth";
+            groups = "mdc_mdio0";
+          };
+
+          conf {
+            pins = "SMI_0_MDC", "SMI_0_MDIO";
+            drive-strength = <8>;
+          };
+        };
+
+        mmc0_pins_emmc_51: mmc0-emmc-51-pins {
+          mux {
+            function = "flash";
+            groups = "emmc_51";
+          };
+        };
+
+        mmc0_pins_sdcard: mmc0-sdcard-pins {
+          mux {
+            function = "flash";
+            groups = "sdcard";
+          };
+        };
+
+        pcie0_pins: pcie0-pins {
+          mux {
+            function = "pcie";
+            groups = "pcie_2l_0_pereset", "pcie_clk_req_n0_0",
+                     "pcie_wake_n0_0";
+          };
+        };
+
+        pcie1_pins: pcie1-pins {
+          mux {
+            function = "pcie";
+            groups = "pcie_2l_1_pereset", "pcie_clk_req_n1",
+                     "pcie_wake_n1_0";
+          };
+        };
+
+        pcie2_pins: pcie2-pins {
+          mux {
+            function = "pcie";
+            groups = "pcie_1l_0_pereset", "pcie_clk_req_n2_0",
+                     "pcie_wake_n2_0";
+          };
+        };
+
+        pcie3_pins: pcie3-pins {
+          mux {
+            function = "pcie";
+            groups = "pcie_1l_1_pereset", "pcie_clk_req_n3",
+                     "pcie_wake_n3_0";
+          };
+        };
+
+        uart0_pins: uart0-pins {
+          mux {
+            function = "uart";
+            groups =  "uart0";
+          };
+        };
+      };
+    };
diff --git a/dts/upstream/Bindings/pinctrl/qcom,ipq5424-tlmm.yaml b/dts/upstream/Bindings/pinctrl/qcom,ipq5424-tlmm.yaml
index 5e64a232fc7..df284d3645c 100644
--- a/dts/upstream/Bindings/pinctrl/qcom,ipq5424-tlmm.yaml
+++ b/dts/upstream/Bindings/pinctrl/qcom,ipq5424-tlmm.yaml
@@ -79,8 +79,8 @@ $defs:
                 qdss_cti_trig_out_b0, qdss_cti_trig_in_b1, qdss_cti_trig_out_b1,
                 qdss_traceclk_a, qdss_tracectl_a, qdss_tracedata_a, qspi_clk,
                 qspi_cs, qspi_data, resout, rx0, rx1, rx2, sdc_clk, sdc_cmd,
-                sdc_data, spi0, spi1, spi10, spi11, tsens_max, uart0, uart1,
-                wci_txd, wci_rxd, wsi_clk, wsi_data ]
+                sdc_data, spi0_cs, spi0_clk, spi0_miso, spi0_mosi, spi1, spi10,
+                spi11, tsens_max, uart0, uart1, wci_txd, wci_rxd, wsi_clk, wsi_data ]
 
     required:
       - pins
diff --git a/dts/upstream/Bindings/pinctrl/qcom,msm8917-pinctrl.yaml b/dts/upstream/Bindings/pinctrl/qcom,msm8917-pinctrl.yaml
new file mode 100644
index 00000000000..16d0c010e58
--- /dev/null
+++ b/dts/upstream/Bindings/pinctrl/qcom,msm8917-pinctrl.yaml
@@ -0,0 +1,160 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pinctrl/qcom,msm8917-pinctrl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm MSM8917 TLMM pin controller
+
+maintainers:
+  - Barnabas Czeman <barnabas.czeman@mainlining.org>
+
+description:
+  Top Level Mode Multiplexer pin controller in Qualcomm MSM8917 SoC.
+
+properties:
+  compatible:
+    const: qcom,msm8917-pinctrl
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+
+  gpio-reserved-ranges:
+    minItems: 1
+    maxItems: 66
+
+  gpio-line-names:
+    maxItems: 134
+
+patternProperties:
+  "-state$":
+    oneOf:
+      - $ref: "#/$defs/qcom-msm8917-tlmm-state"
+      - patternProperties:
+          "-pins$":
+            $ref: "#/$defs/qcom-msm8917-tlmm-state"
+        additionalProperties: false
+
+$defs:
+  qcom-msm8917-tlmm-state:
+    type: object
+    description:
+      Pinctrl node's client devices use subnodes for desired pin configuration.
+      Client device subnodes use below standard properties.
+    $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
+    unevaluatedProperties: false
+
+    properties:
+      pins:
+        description:
+          List of gpio pins affected by the properties specified in this
+          subnode.
+        items:
+          oneOf:
+            - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-2][0-9]|13[0-3])$"
+            - enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc1_rclk, sdc2_clk,
+                      sdc2_cmd, sdc2_data, qdsd_clk, qdsd_cmd, qdsd_data0,
+                      qdsd_data1, qdsd_data2, qdsd_data3 ]
+        minItems: 1
+        maxItems: 16
+
+      function:
+        description:
+          Specify the alternative function to be configured for the specified
+          pins.
+
+        enum: [ accel_int, adsp_ext, alsp_int, atest_bbrx0, atest_bbrx1,
+                atest_char, atest_char0, atest_char1, atest_char2,
+                atest_char3, atest_combodac_to_gpio_native,
+                atest_gpsadc_dtest0_native, atest_gpsadc_dtest1_native,
+                atest_tsens, atest_wlan0, atest_wlan1, audio_ref,
+                audio_reset, bimc_dte0, bimc_dte1, blsp6_spi, blsp8_spi,
+                blsp_i2c1, blsp_i2c2, blsp_i2c3, blsp_i2c4, blsp_i2c5,
+                blsp_i2c6, blsp_i2c7, blsp_i2c8, blsp_spi1, blsp_spi2,
+                blsp_spi3, blsp_spi4, blsp_spi5, blsp_spi6, blsp_spi7,
+                blsp_spi8, blsp_uart1, blsp_uart2, blsp_uart3, blsp_uart4,
+                blsp_uart5, blsp_uart6, blsp_uart7, blsp_uart8, cam0_ldo,
+                cam1_rst, cam1_standby, cam2_rst, cam2_standby, cam_mclk,
+                cci_async, cci_i2c, cci_timer0, cci_timer1, cdc_pdm0,
+                codec_int1, codec_int2, codec_mad, coex_uart, cri_trng,
+                cri_trng0, cri_trng1, dbg_out, dmic0_clk, dmic0_data,
+                ebi_cdc, ebi_ch0, ext_lpass, forced_usb, fp_gpio, fp_int,
+                gcc_gp1_clk_a, gcc_gp1_clk_b, gcc_gp2_clk_a, gcc_gp2_clk_b,
+                gcc_gp3_clk_a, gcc_gp3_clk_b, gcc_plltest, gcc_tlmm, gpio,
+                gsm0_tx, key_focus, key_snapshot, key_volp, ldo_en,
+                ldo_update, lpass_slimbus, lpass_slimbus0, lpass_slimbus1,
+                m_voc, mag_int, mdp_vsync, mipi_dsi0, modem_tsync, nav_pps,
+                nav_pps_in_a, nav_pps_in_b, nav_tsync, nfc_pwr, ov_ldo,
+                pa_indicator, pbs0, pbs1, pbs2, pri_mi2s, pri_mi2s_mclk_a,
+                pri_mi2s_mclk_b, pri_mi2s_ws, prng_rosc,
+                pwr_crypto_enabled_a, pwr_crypto_enabled_b,
+                pwr_modem_enabled_a, pwr_modem_enabled_b, pwr_nav_enabled_a,
+                pwr_nav_enabled_b, qdss_cti_trig_in_a0, qdss_cti_trig_in_a1,
+                qdss_cti_trig_in_b0, qdss_cti_trig_in_b1,
+                qdss_cti_trig_out_a0, qdss_cti_trig_out_a1,
+                qdss_cti_trig_out_b0, qdss_cti_trig_out_b1, qdss_traceclk_a,
+                qdss_traceclk_b, qdss_tracectl_a, qdss_tracectl_b,
+                qdss_tracedata_a, qdss_tracedata_b, sd_write, sdcard_det,
+                sec_mi2s, sec_mi2s_mclk_a, sec_mi2s_mclk_b, sensor_rst,
+                smb_int, ssbi_wtr1, ts_resout, ts_sample, uim1_clk,
+                uim1_data, uim1_present, uim1_reset, uim2_clk, uim2_data,
+                uim2_present, uim2_reset, uim_batt, us_emitter, us_euro,
+                wcss_bt, wcss_fm, wcss_wlan, wcss_wlan0, wcss_wlan1,
+                wcss_wlan2, webcam_rst, webcam_standby, wsa_io, wsa_irq ]
+
+    required:
+      - pins
+
+allOf:
+  - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
+
+required:
+  - compatible
+  - reg
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+    tlmm: pinctrl@1000000 {
+        compatible = "qcom,msm8917-pinctrl";
+        reg = <0x01000000 0x300000>;
+        interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
+        gpio-controller;
+        gpio-ranges = <&tlmm 0 0 134>;
+        #gpio-cells = <2>;
+        interrupt-controller;
+        #interrupt-cells = <2>;
+
+        blsp1-uart2-sleep-state {
+            pins = "gpio4", "gpio5";
+            function = "gpio";
+
+            drive-strength = <2>;
+            bias-pull-down;
+        };
+
+        spi1-default-state {
+            spi-pins {
+                pins = "gpio0", "gpio1", "gpio3";
+                function = "blsp_spi1";
+
+                drive-strength = <12>;
+                bias-disable;
+            };
+
+            cs-pins {
+                pins = "gpio2";
+                function = "gpio";
+
+                drive-strength = <16>;
+                bias-disable;
+                output-high;
+            };
+        };
+    };
diff --git a/dts/upstream/Bindings/pinctrl/realtek,rtd1315e-pinctrl.yaml b/dts/upstream/Bindings/pinctrl/realtek,rtd1315e-pinctrl.yaml
index fc6c65fea73..90bd49d87d2 100644
--- a/dts/upstream/Bindings/pinctrl/realtek,rtd1315e-pinctrl.yaml
+++ b/dts/upstream/Bindings/pinctrl/realtek,rtd1315e-pinctrl.yaml
@@ -159,30 +159,30 @@ additionalProperties: false
 
 examples:
   - |
-     pinctrl@4e000 {
-         compatible = "realtek,rtd1315e-pinctrl";
-         reg = <0x4e000 0x130>;
-
-         emmc-hs200-pins {
-             pins = "emmc_clk",
-                    "emmc_cmd",
-                    "emmc_data_0",
-                    "emmc_data_1",
-                    "emmc_data_2",
-                    "emmc_data_3",
-                    "emmc_data_4",
-                    "emmc_data_5",
-                    "emmc_data_6",
-                    "emmc_data_7";
-             function = "emmc";
-             realtek,drive-strength-p = <0x2>;
-             realtek,drive-strength-n = <0x2>;
-         };
-
-         i2c-0-pins {
-             pins = "gpio_12",
-                    "gpio_13";
-             function = "i2c0";
-             drive-strength = <4>;
-         };
-     };
+    pinctrl@4e000 {
+        compatible = "realtek,rtd1315e-pinctrl";
+        reg = <0x4e000 0x130>;
+
+        emmc-hs200-pins {
+            pins = "emmc_clk",
+                   "emmc_cmd",
+                   "emmc_data_0",
+                   "emmc_data_1",
+                   "emmc_data_2",
+                   "emmc_data_3",
+                   "emmc_data_4",
+                   "emmc_data_5",
+                   "emmc_data_6",
+                   "emmc_data_7";
+            function = "emmc";
+            realtek,drive-strength-p = <0x2>;
+            realtek,drive-strength-n = <0x2>;
+        };
+
+        i2c-0-pins {
+            pins = "gpio_12",
+                   "gpio_13";
+            function = "i2c0";
+            drive-strength = <4>;
+        };
+    };
diff --git a/dts/upstream/Bindings/pinctrl/realtek,rtd1319d-pinctrl.yaml b/dts/upstream/Bindings/pinctrl/realtek,rtd1319d-pinctrl.yaml
index f07361d60ac..b6211c8544c 100644
--- a/dts/upstream/Bindings/pinctrl/realtek,rtd1319d-pinctrl.yaml
+++ b/dts/upstream/Bindings/pinctrl/realtek,rtd1319d-pinctrl.yaml
@@ -158,30 +158,30 @@ additionalProperties: false
 
 examples:
   - |
-     pinctrl@4e000 {
-         compatible = "realtek,rtd1319d-pinctrl";
-         reg = <0x4e000 0x130>;
-
-         emmc-hs200-pins {
-             pins = "emmc_clk",
-                    "emmc_cmd",
-                    "emmc_data_0",
-                    "emmc_data_1",
-                    "emmc_data_2",
-                    "emmc_data_3",
-                    "emmc_data_4",
-                    "emmc_data_5",
-                    "emmc_data_6",
-                    "emmc_data_7";
-             function = "emmc";
-             realtek,drive-strength-p = <0x2>;
-             realtek,drive-strength-n = <0x2>;
-         };
-
-         i2c-0-pins {
-             pins = "gpio_12",
-                    "gpio_13";
-             function = "i2c0";
-             drive-strength = <4>;
-         };
-     };
+    pinctrl@4e000 {
+        compatible = "realtek,rtd1319d-pinctrl";
+        reg = <0x4e000 0x130>;
+
+        emmc-hs200-pins {
+            pins = "emmc_clk",
+                   "emmc_cmd",
+                   "emmc_data_0",
+                   "emmc_data_1",
+                   "emmc_data_2",
+                   "emmc_data_3",
+                   "emmc_data_4",
+                   "emmc_data_5",
+                   "emmc_data_6",
+                   "emmc_data_7";
+            function = "emmc";
+            realtek,drive-strength-p = <0x2>;
+            realtek,drive-strength-n = <0x2>;
+        };
+
+        i2c-0-pins {
+            pins = "gpio_12",
+                   "gpio_13";
+            function = "i2c0";
+            drive-strength = <4>;
+        };
+    };
diff --git a/dts/upstream/Bindings/pinctrl/realtek,rtd1619b-pinctrl.yaml b/dts/upstream/Bindings/pinctrl/realtek,rtd1619b-pinctrl.yaml
index 671e4ec8462..e88bc649cc7 100644
--- a/dts/upstream/Bindings/pinctrl/realtek,rtd1619b-pinctrl.yaml
+++ b/dts/upstream/Bindings/pinctrl/realtek,rtd1619b-pinctrl.yaml
@@ -157,30 +157,30 @@ additionalProperties: false
 
 examples:
   - |
-     pinctrl@4e000 {
-         compatible = "realtek,rtd1619b-pinctrl";
-         reg = <0x4e000 0x130>;
-
-         emmc-hs200-pins {
-             pins = "emmc_clk",
-                    "emmc_cmd",
-                    "emmc_data_0",
-                    "emmc_data_1",
-                    "emmc_data_2",
-                    "emmc_data_3",
-                    "emmc_data_4",
-                    "emmc_data_5",
-                    "emmc_data_6",
-                    "emmc_data_7";
-             function = "emmc";
-             realtek,drive-strength-p = <0x2>;
-             realtek,drive-strength-n = <0x2>;
-         };
-
-         i2c-0-pins {
-             pins = "gpio_12",
-                    "gpio_13";
-             function = "i2c0";
-             drive-strength = <4>;
-         };
-     };
+    pinctrl@4e000 {
+        compatible = "realtek,rtd1619b-pinctrl";
+        reg = <0x4e000 0x130>;
+
+        emmc-hs200-pins {
+            pins = "emmc_clk",
+                   "emmc_cmd",
+                   "emmc_data_0",
+                   "emmc_data_1",
+                   "emmc_data_2",
+                   "emmc_data_3",
+                   "emmc_data_4",
+                   "emmc_data_5",
+                   "emmc_data_6",
+                   "emmc_data_7";
+            function = "emmc";
+            realtek,drive-strength-p = <0x2>;
+            realtek,drive-strength-n = <0x2>;
+        };
+
+        i2c-0-pins {
+            pins = "gpio_12",
+                   "gpio_13";
+            function = "i2c0";
+            drive-strength = <4>;
+        };
+    };
diff --git a/dts/upstream/Bindings/pinctrl/renesas,rzg2l-pinctrl.yaml b/dts/upstream/Bindings/pinctrl/renesas,rzg2l-pinctrl.yaml
index a1805b6e3f6..768bb3c2b45 100644
--- a/dts/upstream/Bindings/pinctrl/renesas,rzg2l-pinctrl.yaml
+++ b/dts/upstream/Bindings/pinctrl/renesas,rzg2l-pinctrl.yaml
@@ -26,6 +26,7 @@ properties:
               - renesas,r9a07g043-pinctrl # RZ/G2UL{Type-1,Type-2} and RZ/Five
               - renesas,r9a07g044-pinctrl # RZ/G2{L,LC}
               - renesas,r9a08g045-pinctrl # RZ/G3S
+              - renesas,r9a09g047-pinctrl # RZ/G3E
               - renesas,r9a09g057-pinctrl # RZ/V2H(P)
 
       - items:
@@ -125,7 +126,7 @@ additionalProperties:
         drive-push-pull: true
         renesas,output-impedance:
           description:
-            Output impedance for pins on the RZ/V2H(P) SoC. The value provided by this
+            Output impedance for pins on the RZ/{G3E,V2H(P)} SoC. The value provided by this
             property corresponds to register bit values that can be set in the PFC_IOLH_mn
             register, which adjusts the drive strength value and is pin-dependent.
           $ref: /schemas/types.yaml#/definitions/uint32
@@ -142,7 +143,9 @@ allOf:
       properties:
         compatible:
           contains:
-            const: renesas,r9a09g057-pinctrl
+            enum:
+              - renesas,r9a09g047-pinctrl
+              - renesas,r9a09g057-pinctrl
     then:
       properties:
         resets:
diff --git a/dts/upstream/Bindings/pinctrl/rockchip,pinctrl.yaml b/dts/upstream/Bindings/pinctrl/rockchip,pinctrl.yaml
index 6a23d845f1f..80a2b193484 100644
--- a/dts/upstream/Bindings/pinctrl/rockchip,pinctrl.yaml
+++ b/dts/upstream/Bindings/pinctrl/rockchip,pinctrl.yaml
@@ -44,6 +44,7 @@ properties:
       - rockchip,rk3328-pinctrl
       - rockchip,rk3368-pinctrl
       - rockchip,rk3399-pinctrl
+      - rockchip,rk3562-pinctrl
       - rockchip,rk3568-pinctrl
       - rockchip,rk3576-pinctrl
       - rockchip,rk3588-pinctrl
diff --git a/dts/upstream/Bindings/pinctrl/xlnx,pinctrl-zynq.yaml b/dts/upstream/Bindings/pinctrl/xlnx,pinctrl-zynq.yaml
index de6c10ba36c..70548cb37ad 100644
--- a/dts/upstream/Bindings/pinctrl/xlnx,pinctrl-zynq.yaml
+++ b/dts/upstream/Bindings/pinctrl/xlnx,pinctrl-zynq.yaml
@@ -180,38 +180,31 @@ additionalProperties: false
 examples:
   - |
     #include <dt-bindings/pinctrl/pinctrl-zynq.h>
-    pinctrl0: pinctrl@700 {
-       compatible = "xlnx,pinctrl-zynq";
-       reg = <0x700 0x200>;
-       syscon = <&slcr>;
-
-       pinctrl_uart1_default: uart1-default {
-           mux {
-               groups = "uart1_10_grp";
-               function = "uart1";
-           };
-
-           conf {
-               groups = "uart1_10_grp";
-               slew-rate = <0>;
-               power-source = <IO_STANDARD_LVCMOS18>;
-           };
-
-           conf-rx {
-               pins = "MIO49";
-               bias-high-impedance;
-           };
-
-           conf-tx {
-               pins = "MIO48";
-               bias-disable;
-           };
-       };
+    pinctrl@700 {
+        compatible = "xlnx,pinctrl-zynq";
+        reg = <0x700 0x200>;
+        syscon = <&slcr>;
+
+        uart1-default {
+            mux {
+                groups = "uart1_10_grp";
+                function = "uart1";
+            };
+
+            conf {
+                groups = "uart1_10_grp";
+                slew-rate = <0>;
+                power-source = <IO_STANDARD_LVCMOS18>;
+            };
+
+            conf-rx {
+                pins = "MIO49";
+                bias-high-impedance;
+            };
+
+            conf-tx {
+                pins = "MIO48";
+                bias-disable;
+            };
+        };
     };
-
-    uart1 {
-         pinctrl-names = "default";
-         pinctrl-0 = <&pinctrl_uart1_default>;
-    };
-
-...
diff --git a/dts/upstream/Bindings/power/domain-idle-state.yaml b/dts/upstream/Bindings/power/domain-idle-state.yaml
index ec1f6f669e5..4dd4f59bbbe 100644
--- a/dts/upstream/Bindings/power/domain-idle-state.yaml
+++ b/dts/upstream/Bindings/power/domain-idle-state.yaml
@@ -54,6 +54,11 @@ patternProperties:
           (i.e. idle states node with entry-method property is set to "psci")
           must specify this property.
 
+      idle-state-name:
+        $ref: /schemas/types.yaml#/definitions/string
+        description:
+          A string used as a descriptive name for the idle state.
+
     required:
       - compatible
       - entry-latency-us
diff --git a/dts/upstream/Bindings/power/raspberrypi,bcm2835-power.yaml b/dts/upstream/Bindings/power/raspberrypi,bcm2835-power.yaml
new file mode 100644
index 00000000000..57579f70264
--- /dev/null
+++ b/dts/upstream/Bindings/power/raspberrypi,bcm2835-power.yaml
@@ -0,0 +1,42 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/power/raspberrypi,bcm2835-power.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Broadcom BCM2835 power domain
+
+maintainers:
+  - Alexander Aring <alex.aring@gmail.com>
+  - Florian Fainelli <florian.fainelli@broadcom.com>
+
+description:
+  The Raspberry Pi power domain manages power for various subsystems
+  in the Raspberry Pi BCM2835 SoC.
+
+properties:
+  compatible:
+    enum:
+      - raspberrypi,bcm2835-power
+
+  firmware:
+    $ref: /schemas/types.yaml#/definitions/phandle
+    description: Reference to the RPi firmware device node
+
+  "#power-domain-cells":
+    const: 1
+
+required:
+  - compatible
+  - firmware
+  - "#power-domain-cells"
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    power-controller {
+      compatible = "raspberrypi,bcm2835-power";
+      firmware = <&firmware>;
+      #power-domain-cells = <1>;
+    };
diff --git a/dts/upstream/Bindings/power/reset/atmel,sama5d2-shdwc.yaml b/dts/upstream/Bindings/power/reset/atmel,sama5d2-shdwc.yaml
index 8c58e12cdb6..0735ceb7c10 100644
--- a/dts/upstream/Bindings/power/reset/atmel,sama5d2-shdwc.yaml
+++ b/dts/upstream/Bindings/power/reset/atmel,sama5d2-shdwc.yaml
@@ -22,6 +22,9 @@ properties:
       - enum:
           - atmel,sama5d2-shdwc
           - microchip,sam9x60-shdwc
+      - items:
+          - const: microchip,sam9x7-shdwc
+          - const: microchip,sam9x60-shdwc
 
   reg:
     maxItems: 1
diff --git a/dts/upstream/Bindings/power/supply/bq24190.yaml b/dts/upstream/Bindings/power/supply/bq24190.yaml
index 131b7e57d22..07adf88997b 100644
--- a/dts/upstream/Bindings/power/supply/bq24190.yaml
+++ b/dts/upstream/Bindings/power/supply/bq24190.yaml
@@ -21,6 +21,7 @@ properties:
       - ti,bq24192i
       - ti,bq24196
       - ti,bq24296
+      - ti,bq24297
 
   reg:
     maxItems: 1
diff --git a/dts/upstream/Bindings/power/supply/gpio-charger.yaml b/dts/upstream/Bindings/power/supply/gpio-charger.yaml
index 89f8e2bcb2d..25826bfc289 100644
--- a/dts/upstream/Bindings/power/supply/gpio-charger.yaml
+++ b/dts/upstream/Bindings/power/supply/gpio-charger.yaml
@@ -58,6 +58,10 @@ properties:
             charge-current-limit-gpios property. Bit 1 second to last
             GPIO and so on.
 
+  charge-current-limit-default-microamp:
+    description: Default charge current limit. Must be listed in
+      charge-current-limit-mapping.
+
 required:
   - compatible
 
@@ -72,6 +76,7 @@ anyOf:
 dependencies:
   charge-current-limit-gpios: [ charge-current-limit-mapping ]
   charge-current-limit-mapping: [ charge-current-limit-gpios ]
+  charge-current-limit-default-microamp: [charge-current-limit-mapping]
 
 additionalProperties: false
 
@@ -91,4 +96,5 @@ examples:
       charge-current-limit-mapping = <2500000 0x00>, // 2.5 A => both GPIOs low
                                      <700000 0x01>, // 700 mA => GPIO A.12 high
                                      <0 0x02>; // 0 mA => GPIO A.11 high
+      charge-current-limit-default-microamp = <700000>;
     };
diff --git a/dts/upstream/Bindings/power/supply/ltc4162-l.yaml b/dts/upstream/Bindings/power/supply/ltc4162-l.yaml
index 29d53654115..06595a95365 100644
--- a/dts/upstream/Bindings/power/supply/ltc4162-l.yaml
+++ b/dts/upstream/Bindings/power/supply/ltc4162-l.yaml
@@ -17,12 +17,18 @@ description: |
   panels, etc., and a rechargeable Lithium-Ion/Polymer battery.
 
   Specifications about the charger can be found at:
+    https://www.analog.com/en/products/ltc4162-l.html
+    https://www.analog.com/en/products/ltc4162-f.html
     https://www.analog.com/en/products/ltc4162-s.html
+    https://www.analog.com/en/products/ltc4015.html
 
 properties:
   compatible:
     enum:
+      - lltc,ltc4015
+      - lltc,ltc4162-f
       - lltc,ltc4162-l
+      - lltc,ltc4162-s
 
   reg:
     maxItems: 1
diff --git a/dts/upstream/Bindings/power/supply/maxim,max17042.yaml b/dts/upstream/Bindings/power/supply/maxim,max17042.yaml
index 085e2504d0d..14242de7fc0 100644
--- a/dts/upstream/Bindings/power/supply/maxim,max17042.yaml
+++ b/dts/upstream/Bindings/power/supply/maxim,max17042.yaml
@@ -19,6 +19,7 @@ properties:
       - maxim,max17047
       - maxim,max17050
       - maxim,max17055
+      - maxim,max77705-battery
       - maxim,max77849-battery
 
   reg:
diff --git a/dts/upstream/Bindings/power/supply/st,stc3117.yaml b/dts/upstream/Bindings/power/supply/st,stc3117.yaml
new file mode 100644
index 00000000000..e486131a27a
--- /dev/null
+++ b/dts/upstream/Bindings/power/supply/st,stc3117.yaml
@@ -0,0 +1,74 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/power/supply/st,stc3117.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: STMicroelectronics STC3117 Fuel Gauge Unit Power Supply
+
+maintainers:
+  - Hardevsinh Palaniya <hardevsinh.palaniya@siliconsignals.io>
+  - Bhavin Sharma <bhavin.sharma@siliconsignals.io>
+
+description: |
+  The STC3117 includes the STMicroelectronics OptimGauge algorithm.
+  It provides accurate battery state-of-charge (SOC) monitoring, tracks
+  battery parameter changes with operation conditions, temperature,
+  and aging, and allows the application to get a battery state-of-health
+  (SOH) indication.
+
+  An alarm output signals low SOC or low voltage conditions and also
+  indicates fault conditions like a missing or swapped battery.
+
+  Datasheet is available at
+  https://www.st.com/resource/en/datasheet/stc3117.pdf
+
+allOf:
+  - $ref: power-supply.yaml#
+
+properties:
+  compatible:
+    enum:
+      - st,stc3117
+
+  reg:
+    maxItems: 1
+
+  monitored-battery:
+    description: |
+      The fuel gauge uses the following battery properties:
+      - charge-full-design-microamp-hours
+      - voltage-min-design-microvolt
+      - voltage-max-design-microvolt
+
+  shunt-resistor-micro-ohms:
+    description: Current sense resistor
+
+  interrupts:
+    maxItems: 1
+
+required:
+  - compatible
+  - reg
+  - monitored-battery
+  - shunt-resistor-micro-ohms
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/interrupt-controller/irq.h>
+
+    i2c {
+      #address-cells = <1>;
+      #size-cells = <0>;
+
+      battery@70 {
+        compatible = "st,stc3117";
+        reg = <0x70>;
+        interrupt-parent = <&gpio0>;
+        interrupts = <31 IRQ_TYPE_LEVEL_LOW>;
+        monitored-battery = <&bat>;
+        shunt-resistor-micro-ohms = <10000>;
+      };
+    };
diff --git a/dts/upstream/Bindings/pwm/adi,axi-pwmgen.yaml b/dts/upstream/Bindings/pwm/adi,axi-pwmgen.yaml
index aa35209f74c..45e112d0efb 100644
--- a/dts/upstream/Bindings/pwm/adi,axi-pwmgen.yaml
+++ b/dts/upstream/Bindings/pwm/adi,axi-pwmgen.yaml
@@ -41,8 +41,8 @@ unevaluatedProperties: false
 examples:
   - |
     pwm@44b00000 {
-       compatible = "adi,axi-pwmgen-2.00.a";
-       reg = <0x44b00000 0x1000>;
-       clocks = <&spi_clk>;
-       #pwm-cells = <3>;
+        compatible = "adi,axi-pwmgen-2.00.a";
+        reg = <0x44b00000 0x1000>;
+        clocks = <&spi_clk>;
+        #pwm-cells = <3>;
     };
diff --git a/dts/upstream/Bindings/pwm/brcm,bcm7038-pwm.yaml b/dts/upstream/Bindings/pwm/brcm,bcm7038-pwm.yaml
index 119de3d7f9d..44548a9da15 100644
--- a/dts/upstream/Bindings/pwm/brcm,bcm7038-pwm.yaml
+++ b/dts/upstream/Bindings/pwm/brcm,bcm7038-pwm.yaml
@@ -35,8 +35,8 @@ additionalProperties: false
 examples:
   - |
     pwm: pwm@f0408000 {
-       compatible = "brcm,bcm7038-pwm";
-       reg = <0xf0408000 0x28>;
-       #pwm-cells = <2>;
-       clocks = <&upg_fixed>;
+        compatible = "brcm,bcm7038-pwm";
+        reg = <0xf0408000 0x28>;
+        #pwm-cells = <2>;
+        clocks = <&upg_fixed>;
     };
diff --git a/dts/upstream/Bindings/pwm/brcm,kona-pwm.yaml b/dts/upstream/Bindings/pwm/brcm,kona-pwm.yaml
index e86c8053b36..fd785da5d3d 100644
--- a/dts/upstream/Bindings/pwm/brcm,kona-pwm.yaml
+++ b/dts/upstream/Bindings/pwm/brcm,kona-pwm.yaml
@@ -43,9 +43,9 @@ examples:
     #include <dt-bindings/clock/bcm281xx.h>
 
     pwm@3e01a000 {
-       compatible = "brcm,bcm11351-pwm", "brcm,kona-pwm";
-       reg = <0x3e01a000 0xcc>;
-       clocks = <&slave_ccu BCM281XX_SLAVE_CCU_PWM>;
-       #pwm-cells = <3>;
+        compatible = "brcm,bcm11351-pwm", "brcm,kona-pwm";
+        reg = <0x3e01a000 0xcc>;
+        clocks = <&slave_ccu BCM281XX_SLAVE_CCU_PWM>;
+        #pwm-cells = <3>;
     };
 ...
diff --git a/dts/upstream/Bindings/pwm/marvell,berlin-pwm.yaml b/dts/upstream/Bindings/pwm/marvell,berlin-pwm.yaml
new file mode 100644
index 00000000000..091fec03df1
--- /dev/null
+++ b/dts/upstream/Bindings/pwm/marvell,berlin-pwm.yaml
@@ -0,0 +1,44 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pwm/marvell,berlin-pwm.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Berlin PWM controller
+
+maintainers:
+  - Jisheng Zhang <jszhang@kernel.org>
+  - Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+
+properties:
+  compatible:
+    const: marvell,berlin-pwm
+
+  reg:
+    maxItems: 1
+
+  "#pwm-cells":
+    const: 3
+
+  clocks:
+    maxItems: 1
+
+required:
+  - compatible
+  - reg
+  - clocks
+
+allOf:
+  - $ref: pwm.yaml#
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    pwm@f7f20000 {
+        compatible = "marvell,berlin-pwm";
+        reg = <0xf7f20000 0x40>;
+        clocks = <&chip_clk 12>;
+        #pwm-cells = <3>;
+    };
+
diff --git a/dts/upstream/Bindings/pwm/pwm-berlin.txt b/dts/upstream/Bindings/pwm/pwm-berlin.txt
deleted file mode 100644
index f01e993a498..00000000000
--- a/dts/upstream/Bindings/pwm/pwm-berlin.txt
+++ /dev/null
@@ -1,17 +0,0 @@
-Berlin PWM controller
-
-Required properties:
-- compatible: should be "marvell,berlin-pwm"
-- reg: physical base address and length of the controller's registers
-- clocks: phandle to the input clock
-- #pwm-cells: should be 3. See pwm.yaml in this directory for a description of
-  the cells format.
-
-Example:
-
-pwm: pwm@f7f20000 {
-	compatible = "marvell,berlin-pwm";
-	reg = <0xf7f20000 0x40>;
-	clocks = <&chip_clk CLKID_CFG>;
-	#pwm-cells = <3>;
-}
diff --git a/dts/upstream/Bindings/pwm/pwm-sprd.txt b/dts/upstream/Bindings/pwm/pwm-sprd.txt
deleted file mode 100644
index 87b206fd061..00000000000
--- a/dts/upstream/Bindings/pwm/pwm-sprd.txt
+++ /dev/null
@@ -1,40 +0,0 @@
-Spreadtrum PWM controller
-
-Spreadtrum SoCs PWM controller provides 4 PWM channels.
-
-Required properties:
-- compatible : Should be "sprd,ums512-pwm".
-- reg: Physical base address and length of the controller's registers.
-- clocks: The phandle and specifier referencing the controller's clocks.
-- clock-names: Should contain following entries:
-  "pwmn": used to derive the functional clock for PWM channel n (n range: 0 ~ 3).
-  "enablen": for PWM channel n enable clock (n range: 0 ~ 3).
-- #pwm-cells: Should be 2. See pwm.yaml in this directory for a description of
-  the cells format.
-
-Optional properties:
-- assigned-clocks: Reference to the PWM clock entries.
-- assigned-clock-parents: The phandle of the parent clock of PWM clock.
-
-Example:
-	pwms: pwm@32260000 {
-		compatible = "sprd,ums512-pwm";
-		reg = <0 0x32260000 0 0x10000>;
-		clock-names = "pwm0", "enable0",
-			"pwm1", "enable1",
-			"pwm2", "enable2",
-			"pwm3", "enable3";
-		clocks = <&aon_clk CLK_PWM0>, <&aonapb_gate CLK_PWM0_EB>,
-		       <&aon_clk CLK_PWM1>, <&aonapb_gate CLK_PWM1_EB>,
-		       <&aon_clk CLK_PWM2>, <&aonapb_gate CLK_PWM2_EB>,
-		       <&aon_clk CLK_PWM3>, <&aonapb_gate CLK_PWM3_EB>;
-		assigned-clocks = <&aon_clk CLK_PWM0>,
-			<&aon_clk CLK_PWM1>,
-			<&aon_clk CLK_PWM2>,
-			<&aon_clk CLK_PWM3>;
-		assigned-clock-parents = <&ext_26m>,
-			<&ext_26m>,
-			<&ext_26m>,
-			<&ext_26m>;
-		#pwm-cells = <2>;
-	};
diff --git a/dts/upstream/Bindings/pwm/sprd,ums512-pwm.yaml b/dts/upstream/Bindings/pwm/sprd,ums512-pwm.yaml
new file mode 100644
index 00000000000..c806b676808
--- /dev/null
+++ b/dts/upstream/Bindings/pwm/sprd,ums512-pwm.yaml
@@ -0,0 +1,66 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pwm/sprd,ums512-pwm.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Spreadtrum/Unisoc UMS512 PWM Controller
+
+maintainers:
+  - Orson Zhai <orsonzhai@gmail.com>
+  - Baolin Wang <baolin.wang@linux.alibaba.com>
+  - Chunyan Zhang <zhang.lyra@gmail.com>
+
+properties:
+  compatible:
+    const: sprd,ums512-pwm
+
+  reg:
+    maxItems: 1
+
+  clocks:
+    maxItems: 8
+
+  clock-names:
+    items:
+      - const: pwm0
+      - const: enable0
+      - const: pwm1
+      - const: enable1
+      - const: pwm2
+      - const: enable2
+      - const: pwm3
+      - const: enable3
+
+  '#pwm-cells':
+    const: 2
+
+required:
+  - compatible
+  - reg
+  - clocks
+  - clock-names
+
+allOf:
+  - $ref: pwm.yaml#
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/sprd,ums512-clk.h>
+
+    pwm@32260000 {
+      compatible = "sprd,ums512-pwm";
+      reg = <0x32260000 0x10000>;
+      clocks = <&aon_clk CLK_PWM0>, <&aonapb_gate CLK_PWM0_EB>,
+               <&aon_clk CLK_PWM1>, <&aonapb_gate CLK_PWM1_EB>,
+               <&aon_clk CLK_PWM2>, <&aonapb_gate CLK_PWM2_EB>,
+               <&aon_clk CLK_PWM3>, <&aonapb_gate CLK_PWM3_EB>;
+      clock-names = "pwm0", "enable0",
+                    "pwm1", "enable1",
+                    "pwm2", "enable2",
+                    "pwm3", "enable3";
+      #pwm-cells = <2>;
+    };
+...
diff --git a/dts/upstream/Bindings/regulator/mt6315-regulator.yaml b/dts/upstream/Bindings/regulator/mt6315-regulator.yaml
index cd4aa27218a..fa6743bb269 100644
--- a/dts/upstream/Bindings/regulator/mt6315-regulator.yaml
+++ b/dts/upstream/Bindings/regulator/mt6315-regulator.yaml
@@ -35,10 +35,6 @@ properties:
         $ref: regulator.yaml#
         unevaluatedProperties: false
 
-        properties:
-          regulator-compatible:
-            pattern: "^vbuck[1-4]$"
-
     additionalProperties: false
 
 required:
@@ -56,7 +52,6 @@ examples:
 
       regulators {
         vbuck1 {
-          regulator-compatible = "vbuck1";
           regulator-min-microvolt = <300000>;
           regulator-max-microvolt = <1193750>;
           regulator-enable-ramp-delay = <256>;
@@ -64,7 +59,6 @@ examples:
         };
 
         vbuck3 {
-          regulator-compatible = "vbuck3";
           regulator-min-microvolt = <300000>;
           regulator-max-microvolt = <1193750>;
           regulator-enable-ramp-delay = <256>;
diff --git a/dts/upstream/Bindings/regulator/nxp,pca9450-regulator.yaml b/dts/upstream/Bindings/regulator/nxp,pca9450-regulator.yaml
index f8057bba747..68709a7dc43 100644
--- a/dts/upstream/Bindings/regulator/nxp,pca9450-regulator.yaml
+++ b/dts/upstream/Bindings/regulator/nxp,pca9450-regulator.yaml
@@ -29,6 +29,7 @@ properties:
       - nxp,pca9450b
       - nxp,pca9450c
       - nxp,pca9451a
+      - nxp,pca9452
 
   reg:
     maxItems: 1
diff --git a/dts/upstream/Bindings/regulator/qcom,smd-rpm-regulator.yaml b/dts/upstream/Bindings/regulator/qcom,smd-rpm-regulator.yaml
index f2fd2df68a9..b7241ce975b 100644
--- a/dts/upstream/Bindings/regulator/qcom,smd-rpm-regulator.yaml
+++ b/dts/upstream/Bindings/regulator/qcom,smd-rpm-regulator.yaml
@@ -22,7 +22,7 @@ description:
   Each sub-node is identified using the node's name, with valid values listed
   for each of the pmics below.
 
-  For mp5496, s1, s2
+  For mp5496, s1, s2, l2, l5
 
   For pm2250, s1, s2, s3, s4, l1, l2, l3, l4, l5, l6, l7, l8, l9, l10, l11,
   l12, l13, l14, l15, l16, l17, l18, l19, l20, l21, l22
diff --git a/dts/upstream/Bindings/regulator/regulator.yaml b/dts/upstream/Bindings/regulator/regulator.yaml
index 1ef380d1515..77573bcb6b7 100644
--- a/dts/upstream/Bindings/regulator/regulator.yaml
+++ b/dts/upstream/Bindings/regulator/regulator.yaml
@@ -34,6 +34,9 @@ properties:
   regulator-input-current-limit-microamp:
     description: maximum input current regulator allows
 
+  regulator-power-budget-milliwatt:
+    description: power budget of the regulator
+
   regulator-always-on:
     description: boolean, regulator should never be disabled
     type: boolean
diff --git a/dts/upstream/Bindings/remoteproc/qcom,sa8775p-pas.yaml b/dts/upstream/Bindings/remoteproc/qcom,sa8775p-pas.yaml
index 7fe401a0680..a66007951d5 100644
--- a/dts/upstream/Bindings/remoteproc/qcom,sa8775p-pas.yaml
+++ b/dts/upstream/Bindings/remoteproc/qcom,sa8775p-pas.yaml
@@ -15,12 +15,25 @@ description:
 
 properties:
   compatible:
-    enum:
-      - qcom,sa8775p-adsp-pas
-      - qcom,sa8775p-cdsp0-pas
-      - qcom,sa8775p-cdsp1-pas
-      - qcom,sa8775p-gpdsp0-pas
-      - qcom,sa8775p-gpdsp1-pas
+    oneOf:
+      - items:
+          - enum:
+              - qcom,qcs8300-adsp-pas
+          - const: qcom,sa8775p-adsp-pas
+      - items:
+          - enum:
+              - qcom,qcs8300-cdsp-pas
+          - const: qcom,sa8775p-cdsp0-pas
+      - items:
+          - enum:
+              - qcom,qcs8300-gpdsp-pas
+          - const: qcom,sa8775p-gpdsp0-pas
+      - enum:
+          - qcom,sa8775p-adsp-pas
+          - qcom,sa8775p-cdsp0-pas
+          - qcom,sa8775p-cdsp1-pas
+          - qcom,sa8775p-gpdsp0-pas
+          - qcom,sa8775p-gpdsp1-pas
 
   reg:
     maxItems: 1
@@ -63,8 +76,9 @@ allOf:
   - if:
       properties:
         compatible:
-          enum:
-            - qcom,sa8775p-adsp-pas
+          contains:
+            enum:
+              - qcom,sa8775p-adsp-pas
     then:
       properties:
         power-domains:
@@ -79,9 +93,10 @@ allOf:
   - if:
       properties:
         compatible:
-          enum:
-            - qcom,sa8775p-cdsp0-pas
-            - qcom,sa8775p-cdsp1-pas
+          contains:
+            enum:
+              - qcom,sa8775p-cdsp0-pas
+              - qcom,sa8775p-cdsp1-pas
     then:
       properties:
         power-domains:
@@ -98,9 +113,10 @@ allOf:
   - if:
       properties:
         compatible:
-          enum:
-            - qcom,sa8775p-gpdsp0-pas
-            - qcom,sa8775p-gpdsp1-pas
+          contains:
+            enum:
+              - qcom,sa8775p-gpdsp0-pas
+              - qcom,sa8775p-gpdsp1-pas
     then:
       properties:
         power-domains:
diff --git a/dts/upstream/Bindings/remoteproc/qcom,sm6115-pas.yaml b/dts/upstream/Bindings/remoteproc/qcom,sm6115-pas.yaml
index 758adb06c8d..059cb87b4d6 100644
--- a/dts/upstream/Bindings/remoteproc/qcom,sm6115-pas.yaml
+++ b/dts/upstream/Bindings/remoteproc/qcom,sm6115-pas.yaml
@@ -7,7 +7,8 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
 title: Qualcomm SM6115 Peripheral Authentication Service
 
 maintainers:
-  - Bhupesh Sharma <bhupesh.sharma@linaro.org>
+  - Bjorn Andersson <andersson@kernel.org>
+  - Konrad Dybcio <konradybcio@kernel.org>
 
 description:
   Qualcomm SM6115 SoC Peripheral Authentication Service loads and boots
diff --git a/dts/upstream/Bindings/reset/st,stm32-rcc.txt b/dts/upstream/Bindings/reset/st,stm32-rcc.txt
index 01db3437519..384035e8e60 100644
--- a/dts/upstream/Bindings/reset/st,stm32-rcc.txt
+++ b/dts/upstream/Bindings/reset/st,stm32-rcc.txt
@@ -3,4 +3,4 @@ STMicroelectronics STM32 Peripheral Reset Controller
 
 The RCC IP is both a reset and a clock controller.
 
-Please see Documentation/devicetree/bindings/clock/st,stm32-rcc.txt
+Please see Documentation/devicetree/bindings/clock/st,stm32-rcc.yaml
diff --git a/dts/upstream/Bindings/riscv/cpus.yaml b/dts/upstream/Bindings/riscv/cpus.yaml
index 8edc8261241..2c72f148a74 100644
--- a/dts/upstream/Bindings/riscv/cpus.yaml
+++ b/dts/upstream/Bindings/riscv/cpus.yaml
@@ -26,6 +26,18 @@ description: |
 allOf:
   - $ref: /schemas/cpu.yaml#
   - $ref: extensions.yaml
+  - if:
+      not:
+        properties:
+          compatible:
+            contains:
+              enum:
+                - thead,c906
+                - thead,c910
+                - thead,c920
+    then:
+      properties:
+        thead,vlenb: false
 
 properties:
   compatible:
@@ -46,6 +58,7 @@ properties:
               - sifive,u7
               - sifive,u74
               - sifive,u74-mc
+              - spacemit,x60
               - thead,c906
               - thead,c908
               - thead,c910
@@ -95,6 +108,13 @@ properties:
     description:
       The blocksize in bytes for the Zicboz cache operations.
 
+  thead,vlenb:
+    $ref: /schemas/types.yaml#/definitions/uint32
+    description:
+      VLEN/8, the vector register length in bytes. This property is required on
+      thead systems where the vector register length is not identical on all harts, or
+      the vlenb CSR is not available.
+
   # RISC-V has multiple properties for cache op block sizes as the sizes
   # differ between individual CBO extensions
   cache-op-block-size: false
diff --git a/dts/upstream/Bindings/riscv/extensions.yaml b/dts/upstream/Bindings/riscv/extensions.yaml
index 9c7dd7e75e0..a63b994e076 100644
--- a/dts/upstream/Bindings/riscv/extensions.yaml
+++ b/dts/upstream/Bindings/riscv/extensions.yaml
@@ -621,6 +621,10 @@ properties:
             latency, as ratified in commit 56ed795 ("Update
             riscv-crypto-spec-vector.adoc") of riscv-crypto.
 
+        # vendor extensions, each extension sorted alphanumerically under the
+        # vendor they belong to. Vendors are sorted alphanumerically as well.
+
+        # Andes
         - const: xandespmu
           description:
             The Andes Technology performance monitor extension for counter overflow
@@ -628,6 +632,12 @@ properties:
             Registers in the AX45MP datasheet.
             https://www.andestech.com/wp-content/uploads/AX45MP-1C-Rev.-5.0.0-Datasheet.pdf
 
+        # T-HEAD
+        - const: xtheadvector
+          description:
+            The T-HEAD specific 0.7.1 vector implementation as written in
+            https://github.com/T-head-Semi/thead-extension-spec/blob/95358cb2cca9489361c61d335e03d3134b14133f/xtheadvector.adoc.
+
     allOf:
       # Zcb depends on Zca
       - if:
diff --git a/dts/upstream/Bindings/riscv/spacemit.yaml b/dts/upstream/Bindings/riscv/spacemit.yaml
new file mode 100644
index 00000000000..52e55077af1
--- /dev/null
+++ b/dts/upstream/Bindings/riscv/spacemit.yaml
@@ -0,0 +1,28 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/riscv/spacemit.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: SpacemiT SoC-based boards
+
+maintainers:
+  - Yangyu Chen <cyy@cyyself.name>
+  - Yixun Lan <dlan@gentoo.org>
+
+description:
+  SpacemiT SoC-based boards
+
+properties:
+  $nodename:
+    const: '/'
+  compatible:
+    oneOf:
+      - items:
+          - enum:
+              - bananapi,bpi-f3
+          - const: spacemit,k1
+
+additionalProperties: true
+
+...
diff --git a/dts/upstream/Bindings/rtc/rtc-mxc.yaml b/dts/upstream/Bindings/rtc/rtc-mxc.yaml
index a14b52178c4..2599b847f40 100644
--- a/dts/upstream/Bindings/rtc/rtc-mxc.yaml
+++ b/dts/upstream/Bindings/rtc/rtc-mxc.yaml
@@ -14,9 +14,13 @@ maintainers:
 
 properties:
   compatible:
-    enum:
-      - fsl,imx1-rtc
-      - fsl,imx21-rtc
+    oneOf:
+      - const: fsl,imx1-rtc
+      - const: fsl,imx21-rtc
+      - items:
+          - enum:
+              - fsl,imx31-rtc
+          - const: fsl,imx21-rtc
 
   reg:
     maxItems: 1
diff --git a/dts/upstream/Bindings/serial/8250.yaml b/dts/upstream/Bindings/serial/8250.yaml
index 692aa05500f..0bde2379e86 100644
--- a/dts/upstream/Bindings/serial/8250.yaml
+++ b/dts/upstream/Bindings/serial/8250.yaml
@@ -111,7 +111,9 @@ properties:
               - mediatek,mt7623-btif
           - const: mediatek,mtk-btif
       - items:
-          - const: mrvl,mmp-uart
+          - enum:
+              - mrvl,mmp-uart
+              - spacemit,k1-uart
           - const: intel,xscale-uart
       - items:
           - enum:
diff --git a/dts/upstream/Bindings/serial/nxp,sc16is7xx.yaml b/dts/upstream/Bindings/serial/nxp,sc16is7xx.yaml
index 88871480018..ab39b95dae4 100644
--- a/dts/upstream/Bindings/serial/nxp,sc16is7xx.yaml
+++ b/dts/upstream/Bindings/serial/nxp,sc16is7xx.yaml
@@ -23,6 +23,8 @@ properties:
     maxItems: 1
 
   interrupts:
+    description:
+      When missing, device driver uses polling instead.
     maxItems: 1
 
   clocks:
@@ -76,7 +78,6 @@ properties:
 required:
   - compatible
   - reg
-  - interrupts
 
 allOf:
   - $ref: /schemas/spi/spi-peripheral-props.yaml#
diff --git a/dts/upstream/Bindings/serial/renesas,scif.yaml b/dts/upstream/Bindings/serial/renesas,scif.yaml
index 51d9fb0f476..8e82999e6ac 100644
--- a/dts/upstream/Bindings/serial/renesas,scif.yaml
+++ b/dts/upstream/Bindings/serial/renesas,scif.yaml
@@ -83,6 +83,11 @@ properties:
 
       - const: renesas,scif-r9a09g057       # RZ/V2H(P)
 
+      - items:
+          - enum:
+              - renesas,scif-r9a09g047      # RZ/G3E
+          - const: renesas,scif-r9a09g057   # RZ/V2H fallback
+
   reg:
     maxItems: 1
 
diff --git a/dts/upstream/Bindings/soc/altera/altr,sys-mgr.yaml b/dts/upstream/Bindings/soc/altera/altr,sys-mgr.yaml
new file mode 100644
index 00000000000..d56ff4c05ae
--- /dev/null
+++ b/dts/upstream/Bindings/soc/altera/altr,sys-mgr.yaml
@@ -0,0 +1,51 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/soc/altera/altr,sys-mgr.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Altera SOCFPGA System Manager
+
+maintainers:
+  - Dinh Nguyen <dinguyen@kernel.org>
+
+properties:
+  compatible:
+    oneOf:
+      - description: Cyclone5/Arria5/Arria10
+        const: altr,sys-mgr
+      - description: Stratix10 SoC
+        items:
+          - const: altr,sys-mgr-s10
+          - const: altr,sys-mgr
+
+  reg:
+    maxItems: 1
+
+  cpu1-start-addr:
+    $ref: /schemas/types.yaml#/definitions/uint32
+    description: CPU1 start address in hex
+
+required:
+  - compatible
+  - reg
+
+allOf:
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: altr,sys-mgr-s10
+    then:
+      properties:
+        cpu1-start-addr: false
+
+additionalProperties: false
+
+examples:
+  - |
+    sysmgr@ffd08000 {
+      compatible = "altr,sys-mgr";
+      reg = <0xffd08000 0x1000>;
+      cpu1-start-addr = <0xffd080c4>;
+    };
diff --git a/dts/upstream/Bindings/soc/amlogic/amlogic,meson-gx-hhi-sysctrl.yaml b/dts/upstream/Bindings/soc/amlogic/amlogic,meson-gx-hhi-sysctrl.yaml
index c6bce40946d..3dc66f1de02 100644
--- a/dts/upstream/Bindings/soc/amlogic/amlogic,meson-gx-hhi-sysctrl.yaml
+++ b/dts/upstream/Bindings/soc/amlogic/amlogic,meson-gx-hhi-sysctrl.yaml
@@ -13,6 +13,7 @@ properties:
   compatible:
     items:
       - enum:
+          - amlogic,meson-hhi-sysctrl
           - amlogic,meson-gx-hhi-sysctrl
           - amlogic,meson-gx-ao-sysctrl
           - amlogic,meson-axg-hhi-sysctrl
@@ -40,6 +41,19 @@ allOf:
       properties:
         compatible:
           enum:
+            - amlogic,meson-hhi-sysctrl
+    then:
+      properties:
+        clock-controller:
+          $ref: /schemas/clock/amlogic,meson8-clkc.yaml#
+
+        pinctrl: false
+        phy: false
+
+  - if:
+      properties:
+        compatible:
+          enum:
             - amlogic,meson-gx-hhi-sysctrl
             - amlogic,meson-axg-hhi-sysctrl
     then:
diff --git a/dts/upstream/Bindings/soc/bcm/raspberrypi,bcm2835-power.txt b/dts/upstream/Bindings/soc/bcm/raspberrypi,bcm2835-power.txt
deleted file mode 100644
index 30942cf7992..00000000000
--- a/dts/upstream/Bindings/soc/bcm/raspberrypi,bcm2835-power.txt
+++ /dev/null
@@ -1,47 +0,0 @@
-Raspberry Pi power domain driver
-
-Required properties:
-
-- compatible:		Should be "raspberrypi,bcm2835-power".
-- firmware:		Reference to the RPi firmware device node.
-- #power-domain-cells:	Should be <1>, we providing multiple power domains.
-
-The valid defines for power domain are:
-
- RPI_POWER_DOMAIN_I2C0
- RPI_POWER_DOMAIN_I2C1
- RPI_POWER_DOMAIN_I2C2
- RPI_POWER_DOMAIN_VIDEO_SCALER
- RPI_POWER_DOMAIN_VPU1
- RPI_POWER_DOMAIN_HDMI
- RPI_POWER_DOMAIN_USB
- RPI_POWER_DOMAIN_VEC
- RPI_POWER_DOMAIN_JPEG
- RPI_POWER_DOMAIN_H264
- RPI_POWER_DOMAIN_V3D
- RPI_POWER_DOMAIN_ISP
- RPI_POWER_DOMAIN_UNICAM0
- RPI_POWER_DOMAIN_UNICAM1
- RPI_POWER_DOMAIN_CCP2RX
- RPI_POWER_DOMAIN_CSI2
- RPI_POWER_DOMAIN_CPI
- RPI_POWER_DOMAIN_DSI0
- RPI_POWER_DOMAIN_DSI1
- RPI_POWER_DOMAIN_TRANSPOSER
- RPI_POWER_DOMAIN_CCP2TX
- RPI_POWER_DOMAIN_CDP
- RPI_POWER_DOMAIN_ARM
-
-Example:
-
-power: power {
-	compatible = "raspberrypi,bcm2835-power";
-	firmware = <&firmware>;
-	#power-domain-cells = <1>;
-};
-
-Example for using power domain:
-
-&usb {
-       power-domains = <&power RPI_POWER_DOMAIN_USB>;
-};
diff --git a/dts/upstream/Bindings/soc/qcom/qcom,aoss-qmp.yaml b/dts/upstream/Bindings/soc/qcom/qcom,aoss-qmp.yaml
index e63f800c6ca..41fbbe059d8 100644
--- a/dts/upstream/Bindings/soc/qcom/qcom,aoss-qmp.yaml
+++ b/dts/upstream/Bindings/soc/qcom/qcom,aoss-qmp.yaml
@@ -25,6 +25,7 @@ properties:
   compatible:
     items:
       - enum:
+          - qcom,qcs615-aoss-qmp
           - qcom,qcs8300-aoss-qmp
           - qcom,qdu1000-aoss-qmp
           - qcom,sa8255p-aoss-qmp
diff --git a/dts/upstream/Bindings/soc/renesas/renesas.yaml b/dts/upstream/Bindings/soc/renesas/renesas.yaml
index b7acb65bdec..225c0f07ae9 100644
--- a/dts/upstream/Bindings/soc/renesas/renesas.yaml
+++ b/dts/upstream/Bindings/soc/renesas/renesas.yaml
@@ -360,19 +360,21 @@ properties:
               - renesas,white-hawk-cpu # White Hawk CPU board (RTP8A779G0ASKB0FC0SA000)
           - const: renesas,r8a779g0
 
-      - description: R-Car V4H (R8A779G2)
-        items:
-          - enum:
-              - renesas,white-hawk-single # White Hawk Single board (RTP8A779G2ASKB0F10SA001)
-          - const: renesas,r8a779g2
-          - const: renesas,r8a779g0
-
       - items:
           - enum:
               - renesas,white-hawk-breakout # White Hawk BreakOut board (RTP8A779G0ASKB0SB0SA000)
           - const: renesas,white-hawk-cpu
           - const: renesas,r8a779g0
 
+      - description: R-Car V4H (R8A779G[23])
+        items:
+          - enum:
+              - renesas,white-hawk-single # White Hawk Single board (RTP8A779G[23]ASKB0F10SA001)
+          - enum:
+              - renesas,r8a779g2 # ES2.x
+              - renesas,r8a779g3 # ES3.x
+          - const: renesas,r8a779g0
+
       - description: R-Car V4M (R8A779H0)
         items:
           - enum:
@@ -525,6 +527,23 @@ properties:
               - renesas,rzv2mevk2   # RZ/V2M Eval Board v2.0
           - const: renesas,r9a09g011
 
+      - description: RZ/G3E (R9A09G047)
+        items:
+          - enum:
+              - renesas,smarc2-evk # RZ SMARC Carrier-II EVK
+          - enum:
+              - renesas,rzg3e-smarcm # RZ/G3E SMARC Module (SoM)
+          - enum:
+              - renesas,r9a09g047e27 # Dual Cortex-A55 + Cortex-M33 (15mm BGA)
+              - renesas,r9a09g047e28 # Dual Cortex-A55 + Cortex-M33 (21mm BGA)
+              - renesas,r9a09g047e37 # Dual Cortex-A55 + Cortex-M33 + Ethos-U55 (15mm BGA)
+              - renesas,r9a09g047e38 # Dual Cortex-A55 + Cortex-M33 + Ethos-U55 (21mm BGA)
+              - renesas,r9a09g047e47 # Quad Cortex-A55 + Cortex-M33 (15mm BGA)
+              - renesas,r9a09g047e48 # Quad Cortex-A55 + Cortex-M33 (21mm BGA)
+              - renesas,r9a09g047e57 # Quad Cortex-A55 + Cortex-M33 + Ethos-U55 (15mm BGA)
+              - renesas,r9a09g047e58 # Quad Cortex-A55 + Cortex-M33 + Ethos-U55 (21mm BGA)
+          - const: renesas,r9a09g047
+
       - description: RZ/V2H(P) (R9A09G057)
         items:
           - enum:
diff --git a/dts/upstream/Bindings/soc/rockchip/grf.yaml b/dts/upstream/Bindings/soc/rockchip/grf.yaml
index 7eca9e1ad6a..61f38b68a4a 100644
--- a/dts/upstream/Bindings/soc/rockchip/grf.yaml
+++ b/dts/upstream/Bindings/soc/rockchip/grf.yaml
@@ -23,6 +23,7 @@ properties:
               - rockchip,rk3576-bigcore-grf
               - rockchip,rk3576-cci-grf
               - rockchip,rk3576-gpu-grf
+              - rockchip,rk3576-hdptxphy-grf
               - rockchip,rk3576-litcore-grf
               - rockchip,rk3576-npu-grf
               - rockchip,rk3576-php-grf
diff --git a/dts/upstream/Bindings/soc/samsung/exynos-pmu.yaml b/dts/upstream/Bindings/soc/samsung/exynos-pmu.yaml
index 6cdfe7e059a..8e6d051d8c9 100644
--- a/dts/upstream/Bindings/soc/samsung/exynos-pmu.yaml
+++ b/dts/upstream/Bindings/soc/samsung/exynos-pmu.yaml
@@ -55,6 +55,7 @@ properties:
               - samsung,exynos7885-pmu
               - samsung,exynos8895-pmu
               - samsung,exynos9810-pmu
+              - samsung,exynos990-pmu
               - samsung,exynosautov9-pmu
               - samsung,exynosautov920-pmu
               - tesla,fsd-pmu
diff --git a/dts/upstream/Bindings/soc/samsung/exynos-usi.yaml b/dts/upstream/Bindings/soc/samsung/exynos-usi.yaml
index f80fcbc3128..5b046932fbc 100644
--- a/dts/upstream/Bindings/soc/samsung/exynos-usi.yaml
+++ b/dts/upstream/Bindings/soc/samsung/exynos-usi.yaml
@@ -64,6 +64,7 @@ properties:
 
   samsung,mode:
     $ref: /schemas/types.yaml#/definitions/uint32
+    enum: [0, 1, 2, 3]
     description:
       Selects USI function (which serial protocol to use). Refer to
       <include/dt-bindings/soc/samsung,exynos-usi.h> for valid USI mode values.
diff --git a/dts/upstream/Bindings/soc/samsung/samsung,exynos-sysreg.yaml b/dts/upstream/Bindings/soc/samsung/samsung,exynos-sysreg.yaml
index 3ca22058289..a75aef24062 100644
--- a/dts/upstream/Bindings/soc/samsung/samsung,exynos-sysreg.yaml
+++ b/dts/upstream/Bindings/soc/samsung/samsung,exynos-sysreg.yaml
@@ -21,6 +21,10 @@ properties:
               - samsung,exynos3-sysreg
               - samsung,exynos4-sysreg
               - samsung,exynos5-sysreg
+              - samsung,exynos8895-fsys0-sysreg
+              - samsung,exynos8895-fsys1-sysreg
+              - samsung,exynos8895-peric0-sysreg
+              - samsung,exynos8895-peric1-sysreg
               - samsung,exynosautov920-peric0-sysreg
               - samsung,exynosautov920-peric1-sysreg
               - tesla,fsd-cam-sysreg
@@ -79,6 +83,10 @@ allOf:
               - samsung,exynos850-cmgp-sysreg
               - samsung,exynos850-peri-sysreg
               - samsung,exynos850-sysreg
+              - samsung,exynos8895-fsys0-sysreg
+              - samsung,exynos8895-fsys1-sysreg
+              - samsung,exynos8895-peric0-sysreg
+              - samsung,exynos8895-peric1-sysreg
     then:
       required:
         - clocks
diff --git a/dts/upstream/Bindings/soc/ti/ti,pruss.yaml b/dts/upstream/Bindings/soc/ti/ti,pruss.yaml
index 3cb1471cc6b..927b3200e29 100644
--- a/dts/upstream/Bindings/soc/ti/ti,pruss.yaml
+++ b/dts/upstream/Bindings/soc/ti/ti,pruss.yaml
@@ -92,6 +92,16 @@ properties:
     description: |
       This property is as per sci-pm-domain.txt.
 
+  clocks:
+    items:
+      - description: ICSSG_CORE Clock
+      - description: ICSSG_IEP Clock
+      - description: ICSSG_RGMII_MHZ_250 Clock
+      - description: ICSSG_RGMII_MHZ_50 Clock
+      - description: ICSSG_RGMII_MHZ_5 Clock
+      - description: ICSSG_UART Clock
+      - description: ICSSG_ICLK Clock
+
 patternProperties:
 
   memories@[a-f0-9]+$:
diff --git a/dts/upstream/Bindings/soc/xilinx/xlnx,vcu.txt b/dts/upstream/Bindings/soc/xilinx/xlnx,vcu.txt
deleted file mode 100644
index 2417b13ba46..00000000000
--- a/dts/upstream/Bindings/soc/xilinx/xlnx,vcu.txt
+++ /dev/null
@@ -1,26 +0,0 @@
-LogicoreIP designed compatible with Xilinx ZYNQ family.
--------------------------------------------------------
-
-General concept
----------------
-
-LogicoreIP design to provide the isolation between processing system
-and programmable logic. Also provides the list of register set to configure
-the frequency.
-
-Required properties:
-- compatible: shall be one of:
-	"xlnx,vcu"
-	"xlnx,vcu-logicoreip-1.0"
-- reg : The base offset and size of the VCU_PL_SLCR register space.
-- clocks: phandle for aclk and pll_ref clocksource
-- clock-names: The identification string, "aclk", is always required for
-   the axi clock. "pll_ref" is required for pll.
-Example:
-
-	xlnx_vcu: vcu@a0040000 {
-		compatible = "xlnx,vcu-logicoreip-1.0";
-		reg = <0x0 0xa0040000 0x0 0x1000>;
-		clocks = <&si570_1>, <&clkc 71>;
-		clock-names = "pll_ref", "aclk";
-	};
diff --git a/dts/upstream/Bindings/sound/adi,ssm2518.yaml b/dts/upstream/Bindings/sound/adi,ssm2518.yaml
index f3f32540779..f1beae84cad 100644
--- a/dts/upstream/Bindings/sound/adi,ssm2518.yaml
+++ b/dts/upstream/Bindings/sound/adi,ssm2518.yaml
@@ -36,12 +36,14 @@ unevaluatedProperties: false
 
 examples:
   - |
-   i2c {
-     #address-cells = <1>;
-     #size-cells = <0>;
-     codec@34 {
-       compatible = "adi,ssm2518";
-       reg = <0x34>;
-       gpios = <&gpio 5 0>;
-     };
-   };
+    #include <dt-bindings/gpio/gpio.h>
+
+    i2c {
+        #address-cells = <1>;
+        #size-cells = <0>;
+        codec@34 {
+            compatible = "adi,ssm2518";
+            reg = <0x34>;
+            gpios = <&gpio 5 GPIO_ACTIVE_HIGH>;
+        };
+    };
diff --git a/dts/upstream/Bindings/sound/allwinner,sun4i-a10-codec.yaml b/dts/upstream/Bindings/sound/allwinner,sun4i-a10-codec.yaml
index ebc9097f936..ccae64ce307 100644
--- a/dts/upstream/Bindings/sound/allwinner,sun4i-a10-codec.yaml
+++ b/dts/upstream/Bindings/sound/allwinner,sun4i-a10-codec.yaml
@@ -23,6 +23,7 @@ properties:
       - allwinner,sun8i-h3-codec
       - allwinner,sun8i-v3s-codec
       - allwinner,sun50i-h616-codec
+      - allwinner,suniv-f1c100s-codec
 
   reg:
     maxItems: 1
@@ -77,6 +78,7 @@ properties:
         - MIC1
         - MIC2
         - MIC3
+        - MIC
 
         # Microphone Biases from the SoC
         - HBIAS
@@ -87,6 +89,8 @@ properties:
         - Headset Mic
         - Line In
         - Line Out
+        - Right FM In
+        - Left FM In
         - Mic
         - Speaker
 
@@ -270,6 +274,33 @@ allOf:
             - const: rx
             - const: tx
 
+  - if:
+      properties:
+        compatible:
+          enum:
+            - allwinner,suniv-f1c100s-codec
+
+    then:
+      properties:
+        allwinner,audio-routing:
+          items:
+            enum:
+              - HP
+              - HPCOM
+              - LINEIN
+              - LINEOUT
+              - MIC
+              - HBIAS
+              - MBIAS
+              - Headphone
+              - Headset Mic
+              - Line In
+              - Line Out
+              - Right FM In
+              - Left FM In
+              - Mic
+              - Speaker
+
 unevaluatedProperties: false
 
 examples:
diff --git a/dts/upstream/Bindings/sound/awinic,aw88395.yaml b/dts/upstream/Bindings/sound/awinic,aw88395.yaml
index 3b0b743e49c..6676406bf2d 100644
--- a/dts/upstream/Bindings/sound/awinic,aw88395.yaml
+++ b/dts/upstream/Bindings/sound/awinic,aw88395.yaml
@@ -18,6 +18,7 @@ properties:
   compatible:
     enum:
       - awinic,aw88081
+      - awinic,aw88083
       - awinic,aw88261
       - awinic,aw88395
       - awinic,aw88399
@@ -58,6 +59,7 @@ allOf:
           contains:
             enum:
               - awinic,aw88081
+              - awinic,aw88083
               - awinic,aw88261
     then:
       properties:
diff --git a/dts/upstream/Bindings/sound/everest,es71x4.yaml b/dts/upstream/Bindings/sound/everest,es71x4.yaml
index fd1b3281222..efe9f3fd377 100644
--- a/dts/upstream/Bindings/sound/everest,es71x4.yaml
+++ b/dts/upstream/Bindings/sound/everest,es71x4.yaml
@@ -53,10 +53,10 @@ unevaluatedProperties: false
 
 examples:
   - |
-   codec {
-       compatible = "everest,es7134";
-       #sound-dai-cells = <0>;
-       VDD-supply = <&vdd_supply>;
-   };
+    codec {
+        compatible = "everest,es7134";
+        #sound-dai-cells = <0>;
+        VDD-supply = <&vdd_supply>;
+    };
 
 ...
diff --git a/dts/upstream/Bindings/sound/everest,es7241.yaml b/dts/upstream/Bindings/sound/everest,es7241.yaml
index f179af75873..e5cfb40f1ef 100644
--- a/dts/upstream/Bindings/sound/everest,es7241.yaml
+++ b/dts/upstream/Bindings/sound/everest,es7241.yaml
@@ -54,14 +54,15 @@ unevaluatedProperties: false
 
 examples:
   - |
-   #include <dt-bindings/gpio/gpio.h>
-   codec {
-       compatible = "everest,es7241";
-       #sound-dai-cells = <0>;
-       reset-gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>;
-       VDDP-supply = <&vddp_supply>;
-       VDDA-supply = <&vdda_supply>;
-       VDDD-supply = <&vddd_supply>;
-   };
+    #include <dt-bindings/gpio/gpio.h>
+
+    codec {
+        compatible = "everest,es7241";
+        #sound-dai-cells = <0>;
+        reset-gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>;
+        VDDP-supply = <&vddp_supply>;
+        VDDA-supply = <&vdda_supply>;
+        VDDD-supply = <&vddd_supply>;
+    };
 
 ...
diff --git a/dts/upstream/Bindings/sound/fsl,easrc.yaml b/dts/upstream/Bindings/sound/fsl,easrc.yaml
index 0782f3f9947..c454110f428 100644
--- a/dts/upstream/Bindings/sound/fsl,easrc.yaml
+++ b/dts/upstream/Bindings/sound/fsl,easrc.yaml
@@ -87,20 +87,20 @@ examples:
     #include <dt-bindings/clock/imx8mn-clock.h>
 
     easrc: easrc@300c0000 {
-           compatible = "fsl,imx8mn-easrc";
-           reg = <0x300c0000 0x10000>;
-           interrupts = <0x0 122 0x4>;
-           clocks = <&clk IMX8MN_CLK_ASRC_ROOT>;
-           clock-names = "mem";
-           dmas = <&sdma2 16 23 0> , <&sdma2 17 23 0>,
-                  <&sdma2 18 23 0> , <&sdma2 19 23 0>,
-                  <&sdma2 20 23 0> , <&sdma2 21 23 0>,
-                  <&sdma2 22 23 0> , <&sdma2 23 23 0>;
-           dma-names = "ctx0_rx", "ctx0_tx",
-                       "ctx1_rx", "ctx1_tx",
-                       "ctx2_rx", "ctx2_tx",
-                       "ctx3_rx", "ctx3_tx";
-           firmware-name = "imx/easrc/easrc-imx8mn.bin";
-           fsl,asrc-rate  = <8000>;
-           fsl,asrc-format = <2>;
+        compatible = "fsl,imx8mn-easrc";
+        reg = <0x300c0000 0x10000>;
+        interrupts = <0x0 122 0x4>;
+        clocks = <&clk IMX8MN_CLK_ASRC_ROOT>;
+        clock-names = "mem";
+        dmas = <&sdma2 16 23 0> , <&sdma2 17 23 0>,
+               <&sdma2 18 23 0> , <&sdma2 19 23 0>,
+               <&sdma2 20 23 0> , <&sdma2 21 23 0>,
+               <&sdma2 22 23 0> , <&sdma2 23 23 0>;
+        dma-names = "ctx0_rx", "ctx0_tx",
+                    "ctx1_rx", "ctx1_tx",
+                    "ctx2_rx", "ctx2_tx",
+                    "ctx3_rx", "ctx3_tx";
+        firmware-name = "imx/easrc/easrc-imx8mn.bin";
+        fsl,asrc-rate  = <8000>;
+        fsl,asrc-format = <2>;
     };
diff --git a/dts/upstream/Bindings/sound/fsl,micfil.yaml b/dts/upstream/Bindings/sound/fsl,micfil.yaml
index c1e9803fc11..c47b7a09749 100644
--- a/dts/upstream/Bindings/sound/fsl,micfil.yaml
+++ b/dts/upstream/Bindings/sound/fsl,micfil.yaml
@@ -25,6 +25,7 @@ properties:
           - fsl,imx8mm-micfil
           - fsl,imx8mp-micfil
           - fsl,imx93-micfil
+          - fsl,imx943-micfil
 
   reg:
     maxItems: 1
diff --git a/dts/upstream/Bindings/sound/fsl,mqs.yaml b/dts/upstream/Bindings/sound/fsl,mqs.yaml
index 030ccc17313..8c22e8348b1 100644
--- a/dts/upstream/Bindings/sound/fsl,mqs.yaml
+++ b/dts/upstream/Bindings/sound/fsl,mqs.yaml
@@ -23,6 +23,8 @@ properties:
       - fsl,imx8qm-mqs
       - fsl,imx8qxp-mqs
       - fsl,imx93-mqs
+      - fsl,imx943-aonmix-mqs
+      - fsl,imx943-wakeupmix-mqs
       - fsl,imx95-aonmix-mqs
       - fsl,imx95-netcmix-mqs
 
diff --git a/dts/upstream/Bindings/sound/fsl,xcvr.yaml b/dts/upstream/Bindings/sound/fsl,xcvr.yaml
index 5e280101422..f68d0e0ecfe 100644
--- a/dts/upstream/Bindings/sound/fsl,xcvr.yaml
+++ b/dts/upstream/Bindings/sound/fsl,xcvr.yaml
@@ -140,21 +140,21 @@ examples:
     #include <dt-bindings/reset/imx8mp-reset.h>
 
     xcvr: xcvr@30cc0000 {
-           compatible = "fsl,imx8mp-xcvr";
-           reg = <0x30cc0000 0x800>,
-                 <0x30cc0800 0x400>,
-                 <0x30cc0c00 0x080>,
-                 <0x30cc0e00 0x080>;
-           reg-names = "ram", "regs", "rxfifo", "txfifo";
-           interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
-                        <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
-                        <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
-           clocks = <&audiomix_clk IMX8MP_CLK_AUDIOMIX_EARC_IPG>,
-                    <&audiomix_clk IMX8MP_CLK_AUDIOMIX_EARC_PHY>,
-                    <&audiomix_clk IMX8MP_CLK_AUDIOMIX_SPBA2_ROOT>,
-                    <&audiomix_clk IMX8MP_CLK_AUDIOMIX_AUDPLL_ROOT>;
-           clock-names = "ipg", "phy", "spba", "pll_ipg";
-           dmas = <&sdma2 30 2 0>, <&sdma2 31 2 0>;
-           dma-names = "rx", "tx";
-           resets = <&audiomix_reset 0>;
+        compatible = "fsl,imx8mp-xcvr";
+        reg = <0x30cc0000 0x800>,
+              <0x30cc0800 0x400>,
+              <0x30cc0c00 0x080>,
+              <0x30cc0e00 0x080>;
+        reg-names = "ram", "regs", "rxfifo", "txfifo";
+        interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
+                     <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
+                     <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
+        clocks = <&audiomix_clk IMX8MP_CLK_AUDIOMIX_EARC_IPG>,
+                 <&audiomix_clk IMX8MP_CLK_AUDIOMIX_EARC_PHY>,
+                 <&audiomix_clk IMX8MP_CLK_AUDIOMIX_SPBA2_ROOT>,
+                 <&audiomix_clk IMX8MP_CLK_AUDIOMIX_AUDPLL_ROOT>;
+        clock-names = "ipg", "phy", "spba", "pll_ipg";
+        dmas = <&sdma2 30 2 0>, <&sdma2 31 2 0>;
+        dma-names = "rx", "tx";
+        resets = <&audiomix_reset 0>;
     };
diff --git a/dts/upstream/Bindings/sound/intel,keembay-i2s.yaml b/dts/upstream/Bindings/sound/intel,keembay-i2s.yaml
index 76b6f2cf25d..dca61786093 100644
--- a/dts/upstream/Bindings/sound/intel,keembay-i2s.yaml
+++ b/dts/upstream/Bindings/sound/intel,keembay-i2s.yaml
@@ -72,19 +72,19 @@ unevaluatedProperties: false
 
 examples:
   - |
-     #include <dt-bindings/interrupt-controller/arm-gic.h>
-     #include <dt-bindings/interrupt-controller/irq.h>
-     #define KEEM_BAY_PSS_AUX_I2S3
-     #define KEEM_BAY_PSS_I2S3
-     i2s3: i2s@20140000 {
-         compatible = "intel,keembay-i2s";
-         #sound-dai-cells = <0>;
-         reg = <0x20140000 0x200>, /* I2S registers */
-               <0x202a00a4 0x4>; /* I2S gen configuration */
-         reg-names = "i2s-regs", "i2s_gen_cfg";
-         interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
-         clock-names = "osc", "apb_clk";
-         clocks = <&scmi_clk KEEM_BAY_PSS_AUX_I2S3>, <&scmi_clk KEEM_BAY_PSS_I2S3>;
-         dmas = <&axi_dma0 29>, <&axi_dma0 33>;
-         dma-names = "tx", "rx";
-     };
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+    #include <dt-bindings/interrupt-controller/irq.h>
+    #define KEEM_BAY_PSS_AUX_I2S3
+    #define KEEM_BAY_PSS_I2S3
+    i2s@20140000 {
+        compatible = "intel,keembay-i2s";
+        #sound-dai-cells = <0>;
+        reg = <0x20140000 0x200>, /* I2S registers */
+              <0x202a00a4 0x4>; /* I2S gen configuration */
+        reg-names = "i2s-regs", "i2s_gen_cfg";
+        interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
+        clock-names = "osc", "apb_clk";
+        clocks = <&scmi_clk KEEM_BAY_PSS_AUX_I2S3>, <&scmi_clk KEEM_BAY_PSS_I2S3>;
+        dmas = <&axi_dma0 29>, <&axi_dma0 33>;
+        dma-names = "tx", "rx";
+    };
diff --git a/dts/upstream/Bindings/sound/mediatek,mt8188-mt6359.yaml b/dts/upstream/Bindings/sound/mediatek,mt8188-mt6359.yaml
index ba482747f0e..362e729b51b 100644
--- a/dts/upstream/Bindings/sound/mediatek,mt8188-mt6359.yaml
+++ b/dts/upstream/Bindings/sound/mediatek,mt8188-mt6359.yaml
@@ -14,11 +14,15 @@ allOf:
 
 properties:
   compatible:
-    enum:
-      - mediatek,mt8188-es8326
-      - mediatek,mt8188-mt6359-evb
-      - mediatek,mt8188-nau8825
-      - mediatek,mt8188-rt5682s
+    oneOf:
+      - enum:
+          - mediatek,mt8188-es8326
+          - mediatek,mt8188-mt6359-evb
+          - mediatek,mt8188-nau8825
+          - mediatek,mt8188-rt5682s
+      - items:
+          - const: mediatek,mt8390-mt6359-evk
+          - const: mediatek,mt8188-mt6359-evb
 
   audio-routing:
     description:
@@ -56,6 +60,8 @@ patternProperties:
             - ETDM2_OUT_BE
             - ETDM3_OUT_BE
             - PCM1_BE
+            - DL_SRC_BE
+            - UL_SRC_BE
 
       codec:
         description: Holds subnode which indicates codec dai.
diff --git a/dts/upstream/Bindings/sound/neofidelity,ntp8918.yaml b/dts/upstream/Bindings/sound/neofidelity,ntp8918.yaml
index 952768b3590..6946177e391 100644
--- a/dts/upstream/Bindings/sound/neofidelity,ntp8918.yaml
+++ b/dts/upstream/Bindings/sound/neofidelity,ntp8918.yaml
@@ -55,16 +55,18 @@ unevaluatedProperties: false
 
 examples:
   - |
-   #include <dt-bindings/gpio/gpio.h>
-   i2c {
-     #address-cells = <1>;
-     #size-cells = <0>;
-     audio-codec@2a {
-       compatible = "neofidelity,ntp8918";
-       #sound-dai-cells = <0>;
-       reg = <0x2a>;
-       clocks = <&clkc 150>, <&clkc 151>, <&clkc 152>;
-       clock-names =  "wck", "scl", "bck";
-       reset-gpios = <&gpio 5 GPIO_ACTIVE_LOW>;
+    #include <dt-bindings/gpio/gpio.h>
+
+    i2c {
+        #address-cells = <1>;
+        #size-cells = <0>;
+
+        audio-codec@2a {
+            compatible = "neofidelity,ntp8918";
+            #sound-dai-cells = <0>;
+            reg = <0x2a>;
+            clocks = <&clkc 150>, <&clkc 151>, <&clkc 152>;
+            clock-names =  "wck", "scl", "bck";
+            reset-gpios = <&gpio 5 GPIO_ACTIVE_LOW>;
+        };
     };
-   };
diff --git a/dts/upstream/Bindings/sound/realtek,rt5682.yaml b/dts/upstream/Bindings/sound/realtek,rt5682.yaml
new file mode 100644
index 00000000000..39333ea0564
--- /dev/null
+++ b/dts/upstream/Bindings/sound/realtek,rt5682.yaml
@@ -0,0 +1,156 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/sound/realtek,rt5682.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Realtek rt5682 and rt5682i codecs
+
+maintainers:
+  - Bard Liao <bardliao@realtek.com>
+
+allOf:
+  - $ref: dai-common.yaml#
+
+properties:
+  compatible:
+    enum:
+      - realtek,rt5682
+      - realtek,rt5682i
+
+  reg:
+    maxItems: 1
+    description: I2C address of the device.
+
+  interrupts:
+    maxItems: 1
+    description: The CODEC's interrupt output.
+
+  realtek,dmic1-data-pin:
+    $ref: /schemas/types.yaml#/definitions/uint32
+    enum:
+      - 0 # dmic1 data is not used
+      - 1 # using GPIO2 pin as dmic1 data pin
+      - 2 # using GPIO5 pin as dmic1 data pin
+    description:
+      Specify which GPIO pin be used as DMIC1 data pin.
+
+  realtek,dmic1-clk-pin:
+    $ref: /schemas/types.yaml#/definitions/uint32
+    enum:
+      - 0 # using GPIO1 pin as dmic1 clock pin
+      - 1 # using GPIO3 pin as dmic1 clock pin
+    description:
+      Specify which GPIO pin be used as DMIC1 clk pin.
+
+  realtek,jd-src:
+    $ref: /schemas/types.yaml#/definitions/uint32
+    enum:
+      - 0 # No JD is used
+      - 1 # using JD1 as JD source
+    description:
+      Specify which JD source be used.
+
+  realtek,ldo1-en-gpios:
+    description:
+      The GPIO that controls the CODEC's LDO1_EN pin.
+
+  realtek,btndet-delay:
+    $ref: /schemas/types.yaml#/definitions/uint32
+    description:
+      The debounce delay for push button.
+      The delay time is realtek,btndet-delay value multiple of 8.192 ms.
+      If absent, the default is 16.
+
+  realtek,dmic-clk-rate-hz:
+    description:
+      Set the clock rate (hz) for the requirement of the particular DMIC.
+
+  realtek,dmic-delay-ms:
+    description:
+      Set the delay time (ms) for the requirement of the particular DMIC.
+
+  realtek,dmic-clk-driving-high:
+    type: boolean
+    description:
+      Set the high driving of the DMIC clock out.
+
+  clocks:
+    items:
+      - description: phandle and clock specifier for codec MCLK.
+
+  clock-names:
+    items:
+      - const: mclk
+
+  "#clock-cells":
+    const: 1
+
+  clock-output-names:
+    minItems: 2
+    maxItems: 2
+    description: Name given for DAI word clock and bit clock outputs.
+
+  "#sound-dai-cells":
+    const: 1
+
+  AVDD-supply:
+    description: Regulator supplying analog power through the AVDD pin.
+
+  MICVDD-supply:
+    description: Regulator supplying power for the microphone bias through
+      the MICVDD pin.
+
+  VBAT-supply:
+    description: Regulator supplying battery power through the VBAT pin.
+
+  DBVDD-supply:
+    description: Regulator supplying I/O power through the DBVDD pin.
+
+  LDO1-IN-supply:
+    description: Regulator supplying power to the digital core and charge
+      pump through the LDO1_IN pin.
+
+required:
+  - compatible
+  - reg
+  - AVDD-supply
+  - VBAT-supply
+  - MICVDD-supply
+  - DBVDD-supply
+  - LDO1-IN-supply
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/gpio/gpio.h>
+    #include <dt-bindings/interrupt-controller/irq.h>
+
+    i2c {
+        #address-cells = <1>;
+        #size-cells = <0>;
+
+        codec@1a {
+            compatible = "realtek,rt5682";
+            reg = <0x1a>;
+            interrupts = <6 IRQ_TYPE_LEVEL_HIGH>;
+            realtek,ldo1-en-gpios =
+                <&gpio 2 GPIO_ACTIVE_HIGH>;
+            realtek,dmic1-data-pin = <1>;
+            realtek,dmic1-clk-pin = <1>;
+            realtek,jd-src = <1>;
+
+            #clock-cells = <1>;
+            clock-output-names = "rt5682-dai-wclk", "rt5682-dai-bclk";
+
+            clocks = <&osc>;
+            clock-names = "mclk";
+
+            AVDD-supply = <&avdd_reg>;
+            VBAT-supply = <&vbat_reg>;
+            MICVDD-supply = <&micvdd_reg>;
+            DBVDD-supply = <&dbvdd_reg>;
+            LDO1-IN-supply = <&ldo1_in_reg>;
+        };
+    };
diff --git a/dts/upstream/Bindings/sound/renesas,rsnd.yaml b/dts/upstream/Bindings/sound/renesas,rsnd.yaml
index 6d0d1514cd4..e8a2acb9264 100644
--- a/dts/upstream/Bindings/sound/renesas,rsnd.yaml
+++ b/dts/upstream/Bindings/sound/renesas,rsnd.yaml
@@ -112,12 +112,6 @@ properties:
     description: List of necessary clock names.
     # details are defined below
 
-  post-init-providers:
-    description: At least if rsnd is using DPCM connection on Audio-Graph-Card2,
-      fw_devlink might doesn't have enough information to break the cycle. rsnd
-      driver will not be probed in such case. Same problem might occur with
-      Multi-CPU/Codec or Codec2Codec.
-
   # ports is below
   port:
     $ref: audio-graph-port.yaml#/definitions/port-base
diff --git a/dts/upstream/Bindings/sound/renesas,rz-ssi.yaml b/dts/upstream/Bindings/sound/renesas,rz-ssi.yaml
index f4610eaed1e..e4cdbf2202b 100644
--- a/dts/upstream/Bindings/sound/renesas,rz-ssi.yaml
+++ b/dts/upstream/Bindings/sound/renesas,rz-ssi.yaml
@@ -19,6 +19,7 @@ properties:
           - renesas,r9a07g043-ssi  # RZ/G2UL and RZ/Five
           - renesas,r9a07g044-ssi  # RZ/G2{L,LC}
           - renesas,r9a07g054-ssi  # RZ/V2L
+          - renesas,r9a08g045-ssi  # RZ/G3S
       - const: renesas,rz-ssi
 
   reg:
@@ -57,24 +58,6 @@ properties:
   dmas:
     minItems: 1
     maxItems: 2
-    description:
-      The first cell represents a phandle to dmac.
-      The second cell specifies the encoded MID/RID values of the SSI port
-      connected to the DMA client and the slave channel configuration
-      parameters.
-      bits[0:9]   - Specifies MID/RID value of a SSI channel as below
-                    MID/RID value of SSI rx0 = 0x256
-                    MID/RID value of SSI tx0 = 0x255
-                    MID/RID value of SSI rx1 = 0x25a
-                    MID/RID value of SSI tx1 = 0x259
-                    MID/RID value of SSI rt2 = 0x25f
-                    MID/RID value of SSI rx3 = 0x262
-                    MID/RID value of SSI tx3 = 0x261
-      bit[10]     - HIEN = 1, Detects a request in response to the rising edge
-                    of the signal
-      bit[11]     - LVL = 0, Detects based on the edge
-      bits[12:14] - AM = 2, Bus cycle mode
-      bit[15]     - TM = 0, Single transfer mode
 
   dma-names:
     oneOf:
diff --git a/dts/upstream/Bindings/sound/rt5682.txt b/dts/upstream/Bindings/sound/rt5682.txt
deleted file mode 100644
index 5e1d08de18a..00000000000
--- a/dts/upstream/Bindings/sound/rt5682.txt
+++ /dev/null
@@ -1,98 +0,0 @@
-RT5682 audio CODEC
-
-This device supports I2C only.
-
-Required properties:
-
-- compatible : "realtek,rt5682" or "realtek,rt5682i"
-
-- reg : The I2C address of the device.
-
-- AVDD-supply: phandle to the regulator supplying analog power through the
-  AVDD pin
-
-- MICVDD-supply: phandle to the regulator supplying power for the microphone
-  bias through the MICVDD pin. Either MICVDD or VBAT should be present.
-
-- VBAT-supply: phandle to the regulator supplying battery power through the
-  VBAT pin. Either MICVDD or VBAT should be present.
-
-- DBVDD-supply: phandle to the regulator supplying I/O power through the DBVDD
-  pin.
-
-- LDO1-IN-supply: phandle to the regulator supplying power to the digital core
-  and charge pump through the LDO1_IN pin.
-
-Optional properties:
-
-- interrupts : The CODEC's interrupt output.
-
-- realtek,dmic1-data-pin
-  0: dmic1 is not used
-  1: using GPIO2 pin as dmic1 data pin
-  2: using GPIO5 pin as dmic1 data pin
-
-- realtek,dmic1-clk-pin
-  0: using GPIO1 pin as dmic1 clock pin
-  1: using GPIO3 pin as dmic1 clock pin
-
-- realtek,jd-src
-  0: No JD is used
-  1: using JD1 as JD source
-
-- realtek,ldo1-en-gpios : The GPIO that controls the CODEC's LDO1_EN pin.
-
-- realtek,btndet-delay
-  The debounce delay for push button.
-  The delay time is realtek,btndet-delay value multiple of 8.192 ms.
-  If absent, the default is 16.
-
-- #clock-cells : Should be set to '<1>',  wclk and bclk sources provided.
-- clock-output-names : Name given for DAI clocks output.
-
-- clocks : phandle and clock specifier for codec MCLK.
-- clock-names : Clock name string for 'clocks' attribute, should be "mclk".
-
-- realtek,dmic-clk-rate-hz : Set the clock rate (hz) for the requirement of
-  the particular DMIC.
-
-- realtek,dmic-delay-ms : Set the delay time (ms) for the requirement of
-  the particular DMIC.
-
-- realtek,dmic-clk-driving-high : Set the high driving of the DMIC clock out.
-
-- #sound-dai-cells: Should be set to '<1>'.
-
-Pins on the device (for linking into audio routes) for RT5682:
-
-  * DMIC L1
-  * DMIC R1
-  * IN1P
-  * HPOL
-  * HPOR
-
-Example:
-
-rt5682 {
-	compatible = "realtek,rt5682i";
-	reg = <0x1a>;
-	interrupt-parent = <&gpio>;
-	interrupts = <TEGRA_GPIO(U, 6) IRQ_TYPE_LEVEL_HIGH>;
-	realtek,ldo1-en-gpios =
-		<&gpio TEGRA_GPIO(R, 2) GPIO_ACTIVE_HIGH>;
-	realtek,dmic1-data-pin = <1>;
-	realtek,dmic1-clk-pin = <1>;
-	realtek,jd-src = <1>;
-	realtek,btndet-delay = <16>;
-
-	#clock-cells = <1>;
-	clock-output-names = "rt5682-dai-wclk", "rt5682-dai-bclk";
-
-	clocks = <&osc>;
-	clock-names = "mclk";
-
-	AVDD-supply = <&avdd_reg>;
-	MICVDD-supply = <&micvdd_reg>;
-	DBVDD-supply = <&dbvdd_reg>;
-	LDO1-IN-supply = <&ldo1_in_reg>;
-};
diff --git a/dts/upstream/Bindings/sound/ti,pcm1681.yaml b/dts/upstream/Bindings/sound/ti,pcm1681.yaml
index 5aa00617291..1f0e6787a74 100644
--- a/dts/upstream/Bindings/sound/ti,pcm1681.yaml
+++ b/dts/upstream/Bindings/sound/ti,pcm1681.yaml
@@ -4,7 +4,7 @@
 $id: http://devicetree.org/schemas/sound/ti,pcm1681.yaml#
 $schema: http://devicetree.org/meta-schemas/core.yaml#
 
-title: Texas Instruments PCM1681 8-channel PWM Processor
+title: Texas Instruments PCM1681 8-channel Digital-to-Analog Converter
 
 maintainers:
   - Shenghao Ding <shenghao-ding@ti.com>
diff --git a/dts/upstream/Bindings/sound/ti,pcm6240.yaml b/dts/upstream/Bindings/sound/ti,pcm6240.yaml
index dd5b08e3d7a..d89b4255b51 100644
--- a/dts/upstream/Bindings/sound/ti,pcm6240.yaml
+++ b/dts/upstream/Bindings/sound/ti,pcm6240.yaml
@@ -159,19 +159,21 @@ additionalProperties: false
 
 examples:
   - |
-   #include <dt-bindings/gpio/gpio.h>
-   i2c {
-     /* example for two devices with interrupt support */
-     #address-cells = <1>;
-     #size-cells = <0>;
-     pcm6240: audio-codec@48 {
-       compatible = "ti,pcm6240";
-       reg = <0x48>, /* primary-device */
-             <0x4b>; /* secondary-device */
-       #sound-dai-cells = <0>;
-       reset-gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>;
-       interrupt-parent = <&gpio1>;
-       interrupts = <15>;
-     };
-   };
+    #include <dt-bindings/gpio/gpio.h>
+
+    i2c {
+        /* example for two devices with interrupt support */
+        #address-cells = <1>;
+        #size-cells = <0>;
+
+        audio-codec@48 {
+            compatible = "ti,pcm6240";
+            reg = <0x48>, /* primary-device */
+                  <0x4b>; /* secondary-device */
+            #sound-dai-cells = <0>;
+            reset-gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>;
+            interrupt-parent = <&gpio1>;
+            interrupts = <15>;
+        };
+    };
 ...
diff --git a/dts/upstream/Bindings/sound/ti,tas2562.yaml b/dts/upstream/Bindings/sound/ti,tas2562.yaml
index 8bc3b0c7531..3763ca16b91 100644
--- a/dts/upstream/Bindings/sound/ti,tas2562.yaml
+++ b/dts/upstream/Bindings/sound/ti,tas2562.yaml
@@ -65,17 +65,19 @@ unevaluatedProperties: false
 
 examples:
   - |
-   #include <dt-bindings/gpio/gpio.h>
-   i2c {
-     #address-cells = <1>;
-     #size-cells = <0>;
-     codec: codec@4c {
-       compatible = "ti,tas2562";
-       reg = <0x4c>;
-       #sound-dai-cells = <0>;
-       interrupt-parent = <&gpio1>;
-       interrupts = <14>;
-       shutdown-gpios = <&gpio1 15 0>;
-       ti,imon-slot-no = <0>;
-     };
-   };
+    #include <dt-bindings/gpio/gpio.h>
+
+    i2c {
+        #address-cells = <1>;
+        #size-cells = <0>;
+
+        codec@4c {
+            compatible = "ti,tas2562";
+            reg = <0x4c>;
+            #sound-dai-cells = <0>;
+            interrupt-parent = <&gpio1>;
+            interrupts = <14>;
+            shutdown-gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>;
+            ti,imon-slot-no = <0>;
+        };
+    };
diff --git a/dts/upstream/Bindings/sound/ti,tas2770.yaml b/dts/upstream/Bindings/sound/ti,tas2770.yaml
index 362c2e6154f..5e7aea43ace 100644
--- a/dts/upstream/Bindings/sound/ti,tas2770.yaml
+++ b/dts/upstream/Bindings/sound/ti,tas2770.yaml
@@ -69,19 +69,21 @@ unevaluatedProperties: false
 
 examples:
   - |
-   #include <dt-bindings/gpio/gpio.h>
-   i2c {
-     #address-cells = <1>;
-     #size-cells = <0>;
-     codec: codec@41 {
-       compatible = "ti,tas2770";
-       reg = <0x41>;
-       #sound-dai-cells = <0>;
-       interrupt-parent = <&gpio1>;
-       interrupts = <14>;
-       reset-gpio = <&gpio1 15 0>;
-       shutdown-gpios = <&gpio1 14 0>;
-       ti,imon-slot-no = <0>;
-       ti,vmon-slot-no = <2>;
-     };
-   };
+    #include <dt-bindings/gpio/gpio.h>
+
+    i2c {
+        #address-cells = <1>;
+        #size-cells = <0>;
+
+        codec@41 {
+            compatible = "ti,tas2770";
+            reg = <0x41>;
+            #sound-dai-cells = <0>;
+            interrupt-parent = <&gpio1>;
+            interrupts = <14>;
+            reset-gpio = <&gpio1 15 GPIO_ACTIVE_HIGH>;
+            shutdown-gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>;
+            ti,imon-slot-no = <0>;
+            ti,vmon-slot-no = <2>;
+        };
+    };
diff --git a/dts/upstream/Bindings/sound/ti,tas2781.yaml b/dts/upstream/Bindings/sound/ti,tas2781.yaml
index 97623868924..5ea1cdc593b 100644
--- a/dts/upstream/Bindings/sound/ti,tas2781.yaml
+++ b/dts/upstream/Bindings/sound/ti,tas2781.yaml
@@ -101,22 +101,24 @@ additionalProperties: false
 
 examples:
   - |
-   #include <dt-bindings/gpio/gpio.h>
-   i2c {
-     /* example with quad tas2781s, such as tablet or pad device */
-     #address-cells = <1>;
-     #size-cells = <0>;
-     quad_tas2781: tas2781@38 {
-       compatible = "ti,tas2781";
-       reg = <0x38>, /* Audio slot 0 */
-             <0x3a>, /* Audio slot 1 */
-             <0x39>, /* Audio slot 2 */
-             <0x3b>; /* Audio slot 3 */
-
-       #sound-dai-cells = <0>;
-       reset-gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>;
-       interrupt-parent = <&gpio1>;
-       interrupts = <15>;
-     };
-   };
+    #include <dt-bindings/gpio/gpio.h>
+
+    i2c {
+        /* example with quad tas2781s, such as tablet or pad device */
+        #address-cells = <1>;
+        #size-cells = <0>;
+
+        audio-codec@38 {
+            compatible = "ti,tas2781";
+            reg = <0x38>, /* Audio slot 0 */
+                  <0x3a>, /* Audio slot 1 */
+                  <0x39>, /* Audio slot 2 */
+                  <0x3b>; /* Audio slot 3 */
+
+            #sound-dai-cells = <0>;
+            reset-gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>;
+            interrupt-parent = <&gpio1>;
+            interrupts = <15>;
+        };
+    };
 ...
diff --git a/dts/upstream/Bindings/sound/ti,tas27xx.yaml b/dts/upstream/Bindings/sound/ti,tas27xx.yaml
index 530bc393784..5447482179c 100644
--- a/dts/upstream/Bindings/sound/ti,tas27xx.yaml
+++ b/dts/upstream/Bindings/sound/ti,tas27xx.yaml
@@ -62,21 +62,23 @@ unevaluatedProperties: false
 
 examples:
   - |
-   #include <dt-bindings/gpio/gpio.h>
-   i2c {
-     #address-cells = <1>;
-     #size-cells = <0>;
-     codec: codec@38 {
-       compatible = "ti,tas2764";
-       reg = <0x38>;
-       #sound-dai-cells = <0>;
-       interrupt-parent = <&gpio1>;
-       interrupts = <14>;
-       reset-gpios = <&gpio1 15 0>;
-       shutdown-gpios = <&gpio1 15 0>;
-       ti,imon-slot-no = <0>;
-       ti,vmon-slot-no = <2>;
-     };
-   };
+    #include <dt-bindings/gpio/gpio.h>
+
+    i2c {
+        #address-cells = <1>;
+        #size-cells = <0>;
+
+        codec@38 {
+            compatible = "ti,tas2764";
+            reg = <0x38>;
+            #sound-dai-cells = <0>;
+            interrupt-parent = <&gpio1>;
+            interrupts = <14>;
+            reset-gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>;
+            shutdown-gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>;
+            ti,imon-slot-no = <0>;
+            ti,vmon-slot-no = <2>;
+        };
+    };
 
 ...
diff --git a/dts/upstream/Bindings/sound/ti,tas57xx.yaml b/dts/upstream/Bindings/sound/ti,tas57xx.yaml
index 2f917238db9..74f7d02b424 100644
--- a/dts/upstream/Bindings/sound/ti,tas57xx.yaml
+++ b/dts/upstream/Bindings/sound/ti,tas57xx.yaml
@@ -112,22 +112,24 @@ unevaluatedProperties: false
 
 examples:
   - |
-   i2c {
-     #address-cells = <1>;
-     #size-cells = <0>;
-
-     codec@2a {
-       compatible = "ti,tas5717";
-       reg = <0x2a>;
-       #sound-dai-cells = <0>;
-       reset-gpios = <&gpio1 15 0>;
-       pdn-gpios = <&gpio1 15 0>;
-       AVDD-supply = <&avdd_supply>;
-       DVDD-supply = <&dvdd_supply>;
-       HPVDD-supply = <&hpvdd_supply>;
-       PVDD_AB-supply = <&pvdd_ab_supply>;
-       PVDD_CD-supply = <&pvdd_cd_supply>;
-     };
-   };
+    #include <dt-bindings/gpio/gpio.h>
+
+    i2c {
+        #address-cells = <1>;
+        #size-cells = <0>;
+
+        codec@2a {
+            compatible = "ti,tas5717";
+            reg = <0x2a>;
+            #sound-dai-cells = <0>;
+            reset-gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>;
+            pdn-gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>;
+            AVDD-supply = <&avdd_supply>;
+            DVDD-supply = <&dvdd_supply>;
+            HPVDD-supply = <&hpvdd_supply>;
+            PVDD_AB-supply = <&pvdd_ab_supply>;
+            PVDD_CD-supply = <&pvdd_cd_supply>;
+        };
+    };
 
 ...
diff --git a/dts/upstream/Bindings/spi/cdns,qspi-nor.yaml b/dts/upstream/Bindings/spi/cdns,qspi-nor.yaml
index d48ecd6cd5a..b6bc71d1928 100644
--- a/dts/upstream/Bindings/spi/cdns,qspi-nor.yaml
+++ b/dts/upstream/Bindings/spi/cdns,qspi-nor.yaml
@@ -68,6 +68,7 @@ properties:
       - items:
           - enum:
               - amd,pensando-elba-qspi
+              - amd,versal2-ospi
               - intel,lgm-qspi
               - intel,socfpga-qspi
               - mobileye,eyeq5-ospi
diff --git a/dts/upstream/Bindings/spi/spi-controller.yaml b/dts/upstream/Bindings/spi/spi-controller.yaml
index 093150c0cb8..82d051f7bd6 100644
--- a/dts/upstream/Bindings/spi/spi-controller.yaml
+++ b/dts/upstream/Bindings/spi/spi-controller.yaml
@@ -69,6 +69,11 @@ properties:
          Should be generally avoided and be replaced by
          spi-cs-high + ACTIVE_HIGH.
 
+      The simplest way to obtain an active-high CS signal is to configure the
+      controller's cs-gpio property with the ACTIVE_HIGH flag and set the
+      peripheral's spi-cs-high property. See example below for a better
+      understanding.
+
   fifo-depth:
     $ref: /schemas/types.yaml#/definitions/uint32
     description:
@@ -189,3 +194,23 @@ examples:
             stacked-memories = /bits/ 64 <0x10000000 0x10000000>;
         };
     };
+
+  - |
+    #include <dt-bindings/gpio/gpio.h>
+
+    spi@20204000 {
+        #address-cells = <1>;
+        #size-cells = <0>;
+        compatible = "brcm,bcm2835-spi";
+        reg = <0x7e204000 0x1000>;
+        interrupts = <2 22>;
+        clocks = <&clk_spi>;
+        cs-gpios = <&gpio 8 GPIO_ACTIVE_HIGH>;
+
+        display@0 {
+            compatible = "lg,lg4573";
+            spi-max-frequency = <1000000>;
+            reg = <0>;
+            spi-cs-high;
+        };
+    };
diff --git a/dts/upstream/Bindings/sram/allwinner,sun4i-a10-system-control.yaml b/dts/upstream/Bindings/sram/allwinner,sun4i-a10-system-control.yaml
index d9322704f35..a7236f7db4e 100644
--- a/dts/upstream/Bindings/sram/allwinner,sun4i-a10-system-control.yaml
+++ b/dts/upstream/Bindings/sram/allwinner,sun4i-a10-system-control.yaml
@@ -47,7 +47,9 @@ properties:
           - const: allwinner,sun8i-v3s-system-control
           - const: allwinner,sun8i-h3-system-control
       - items:
-          - const: allwinner,sun50i-h6-system-control
+          - enum:
+              - allwinner,sun50i-a100-system-control
+              - allwinner,sun50i-h6-system-control
           - const: allwinner,sun50i-a64-system-control
 
   reg:
diff --git a/dts/upstream/Bindings/sram/qcom,imem.yaml b/dts/upstream/Bindings/sram/qcom,imem.yaml
index 9b06bcd0195..2711f90d966 100644
--- a/dts/upstream/Bindings/sram/qcom,imem.yaml
+++ b/dts/upstream/Bindings/sram/qcom,imem.yaml
@@ -20,6 +20,7 @@ properties:
           - qcom,apq8064-imem
           - qcom,msm8226-imem
           - qcom,msm8974-imem
+          - qcom,msm8976-imem
           - qcom,qcs404-imem
           - qcom,qcs8300-imem
           - qcom,qdu1000-imem
diff --git a/dts/upstream/Bindings/thermal/qcom-tsens.yaml b/dts/upstream/Bindings/thermal/qcom-tsens.yaml
index ed5de0f92a9..b9829bb22cc 100644
--- a/dts/upstream/Bindings/thermal/qcom-tsens.yaml
+++ b/dts/upstream/Bindings/thermal/qcom-tsens.yaml
@@ -80,6 +80,7 @@ properties:
       - description: v2 of TSENS with combined interrupt
         items:
           - enum:
+              - qcom,ipq6018-tsens
               - qcom,ipq9574-tsens
           - const: qcom,ipq8074-tsens
 
diff --git a/dts/upstream/Bindings/timer/fsl,imxgpt.yaml b/dts/upstream/Bindings/timer/fsl,imxgpt.yaml
index e2607377cba..9898dc7ea97 100644
--- a/dts/upstream/Bindings/timer/fsl,imxgpt.yaml
+++ b/dts/upstream/Bindings/timer/fsl,imxgpt.yaml
@@ -21,6 +21,7 @@ properties:
       - items:
           - enum:
               - fsl,imx25-gpt
+              - fsl,imx35-gpt
               - fsl,imx50-gpt
               - fsl,imx51-gpt
               - fsl,imx53-gpt
@@ -31,6 +32,7 @@ properties:
           - enum:
               - fsl,imx6sl-gpt
               - fsl,imx6sx-gpt
+              - fsl,imx7d-gpt
               - fsl,imx8mp-gpt
               - fsl,imxrt1050-gpt
               - fsl,imxrt1170-gpt
@@ -38,7 +40,6 @@ properties:
       - items:
           - enum:
               - fsl,imx6ul-gpt
-              - fsl,imx7d-gpt
           - const: fsl,imx6sx-gpt
 
   reg:
diff --git a/dts/upstream/Bindings/timer/sifive,clint.yaml b/dts/upstream/Bindings/timer/sifive,clint.yaml
index b42d43d2de4..76d83aea4e2 100644
--- a/dts/upstream/Bindings/timer/sifive,clint.yaml
+++ b/dts/upstream/Bindings/timer/sifive,clint.yaml
@@ -31,6 +31,7 @@ properties:
           - enum:
               - canaan,k210-clint       # Canaan Kendryte K210
               - sifive,fu540-c000-clint # SiFive FU540
+              - spacemit,k1-clint       # SpacemiT K1
               - starfive,jh7100-clint   # StarFive JH7100
               - starfive,jh7110-clint   # StarFive JH7110
               - starfive,jh8100-clint   # StarFive JH8100
diff --git a/dts/upstream/Bindings/trivial-devices.yaml b/dts/upstream/Bindings/trivial-devices.yaml
index 88abb5c174f..fadbd3c041c 100644
--- a/dts/upstream/Bindings/trivial-devices.yaml
+++ b/dts/upstream/Bindings/trivial-devices.yaml
@@ -55,8 +55,6 @@ properties:
           - atmel,atsha204a
             # BPA-RS600: Power Supply
           - blutek,bpa-rs600
-            # Bosch Sensortec pressure, temperature, humididty and VOC sensor
-          - bosch,bme680
             # CM32181: Ambient Light Sensor
           - capella,cm32181
             # CM3232: Ambient Light Sensor
@@ -147,8 +145,12 @@ properties:
           - injoinic,ip5207
             # Injoinic IP5209 2.4A Power Bank IC with I2C
           - injoinic,ip5209
+            # Injoinic IP5306 2.1A Power Bank IC with I2C option
+          - injoinic,ip5306
             # Inspur Power System power supply unit version 1
           - inspur,ipsps1
+            # Intel common redudant power supply crps185
+          - intel,crps185
             # Intersil ISL29028 Ambient Light and Proximity Sensor
           - isil,isl29028
             # Intersil ISL29030 Ambient Light and Proximity Sensor
diff --git a/dts/upstream/Bindings/ufs/qcom,ufs.yaml b/dts/upstream/Bindings/ufs/qcom,ufs.yaml
index cde334e3206..a03fff5df5e 100644
--- a/dts/upstream/Bindings/ufs/qcom,ufs.yaml
+++ b/dts/upstream/Bindings/ufs/qcom,ufs.yaml
@@ -26,6 +26,7 @@ properties:
           - qcom,msm8994-ufshc
           - qcom,msm8996-ufshc
           - qcom,msm8998-ufshc
+          - qcom,qcs615-ufshc
           - qcom,qcs8300-ufshc
           - qcom,sa8775p-ufshc
           - qcom,sc7180-ufshc
@@ -243,6 +244,7 @@ allOf:
         compatible:
           contains:
             enum:
+              - qcom,qcs615-ufshc
               - qcom,sm6115-ufshc
               - qcom,sm6125-ufshc
     then:
diff --git a/dts/upstream/Bindings/ufs/renesas,ufs.yaml b/dts/upstream/Bindings/ufs/renesas,ufs.yaml
index f04f9f61fa9..1949a15e73d 100644
--- a/dts/upstream/Bindings/ufs/renesas,ufs.yaml
+++ b/dts/upstream/Bindings/ufs/renesas,ufs.yaml
@@ -50,12 +50,12 @@ examples:
     #include <dt-bindings/power/r8a779f0-sysc.h>
 
     ufs: ufs@e686000 {
-            compatible = "renesas,r8a779f0-ufs";
-            reg = <0xe6860000 0x100>;
-            interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>;
-            clocks = <&cpg CPG_MOD 1514>, <&ufs30_clk>;
-            clock-names = "fck", "ref_clk";
-            freq-table-hz = <200000000 200000000>, <38400000 38400000>;
-            power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
-            resets = <&cpg 1514>;
+        compatible = "renesas,r8a779f0-ufs";
+        reg = <0xe6860000 0x100>;
+        interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>;
+        clocks = <&cpg CPG_MOD 1514>, <&ufs30_clk>;
+        clock-names = "fck", "ref_clk";
+        freq-table-hz = <200000000 200000000>, <38400000 38400000>;
+        power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
+        resets = <&cpg 1514>;
     };
diff --git a/dts/upstream/Bindings/ufs/samsung,exynos-ufs.yaml b/dts/upstream/Bindings/ufs/samsung,exynos-ufs.yaml
index 720879820f6..b4e744ebffd 100644
--- a/dts/upstream/Bindings/ufs/samsung,exynos-ufs.yaml
+++ b/dts/upstream/Bindings/ufs/samsung,exynos-ufs.yaml
@@ -112,19 +112,19 @@ examples:
     #include <dt-bindings/clock/exynos7-clk.h>
 
     ufs: ufs@15570000 {
-       compatible = "samsung,exynos7-ufs";
-       reg = <0x15570000 0x100>,
-             <0x15570100 0x100>,
-             <0x15571000 0x200>,
-             <0x15572000 0x300>;
-       reg-names = "hci", "vs_hci", "unipro", "ufsp";
-       interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>;
-       clocks = <&clock_fsys1 ACLK_UFS20_LINK>,
-                <&clock_fsys1 SCLK_UFSUNIPRO20_USER>;
-       clock-names = "core_clk", "sclk_unipro_main";
-       pinctrl-names = "default";
-       pinctrl-0 = <&ufs_rst_n &ufs_refclk_out>;
-       phys = <&ufs_phy>;
-       phy-names = "ufs-phy";
+        compatible = "samsung,exynos7-ufs";
+        reg = <0x15570000 0x100>,
+              <0x15570100 0x100>,
+              <0x15571000 0x200>,
+              <0x15572000 0x300>;
+        reg-names = "hci", "vs_hci", "unipro", "ufsp";
+        interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>;
+        clocks = <&clock_fsys1 ACLK_UFS20_LINK>,
+                 <&clock_fsys1 SCLK_UFSUNIPRO20_USER>;
+        clock-names = "core_clk", "sclk_unipro_main";
+        pinctrl-names = "default";
+        pinctrl-0 = <&ufs_rst_n &ufs_refclk_out>;
+        phys = <&ufs_phy>;
+        phy-names = "ufs-phy";
     };
 ...
diff --git a/dts/upstream/Bindings/usb/aspeed,usb-vhub.yaml b/dts/upstream/Bindings/usb/aspeed,usb-vhub.yaml
index a86bcd95100..7f22f9c031b 100644
--- a/dts/upstream/Bindings/usb/aspeed,usb-vhub.yaml
+++ b/dts/upstream/Bindings/usb/aspeed,usb-vhub.yaml
@@ -113,27 +113,27 @@ examples:
   - |
     #include <dt-bindings/clock/aspeed-clock.h>
     vhub: usb-vhub@1e6a0000 {
-            compatible = "aspeed,ast2500-usb-vhub";
-            reg = <0x1e6a0000 0x300>;
-            interrupts = <5>;
-            clocks = <&syscon ASPEED_CLK_GATE_USBPORT1CLK>;
-            aspeed,vhub-downstream-ports = <5>;
-            aspeed,vhub-generic-endpoints = <15>;
-            pinctrl-names = "default";
-            pinctrl-0 = <&pinctrl_usb2ad_default>;
-
-            vhub-vendor-id = <0x1d6b>;
-            vhub-product-id = <0x0107>;
-            vhub-device-revision = <0x0100>;
-            vhub-strings {
-                #address-cells = <1>;
-                #size-cells = <0>;
-
-                string@409 {
-                        reg = <0x409>;
-                        manufacturer = "ASPEED";
-                        product = "USB Virtual Hub";
-                        serial-number = "0000";
-                };
+        compatible = "aspeed,ast2500-usb-vhub";
+        reg = <0x1e6a0000 0x300>;
+        interrupts = <5>;
+        clocks = <&syscon ASPEED_CLK_GATE_USBPORT1CLK>;
+        aspeed,vhub-downstream-ports = <5>;
+        aspeed,vhub-generic-endpoints = <15>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_usb2ad_default>;
+
+        vhub-vendor-id = <0x1d6b>;
+        vhub-product-id = <0x0107>;
+        vhub-device-revision = <0x0100>;
+        vhub-strings {
+            #address-cells = <1>;
+            #size-cells = <0>;
+
+            string@409 {
+                reg = <0x409>;
+                manufacturer = "ASPEED";
+                product = "USB Virtual Hub";
+                serial-number = "0000";
             };
+        };
     };
diff --git a/dts/upstream/Bindings/usb/brcm,bdc.yaml b/dts/upstream/Bindings/usb/brcm,bdc.yaml
index 9e561fee98f..f9375c69e86 100644
--- a/dts/upstream/Bindings/usb/brcm,bdc.yaml
+++ b/dts/upstream/Bindings/usb/brcm,bdc.yaml
@@ -41,10 +41,10 @@ additionalProperties: false
 
 examples:
   - |
-        usb@f0b02000 {
-                compatible = "brcm,bdc-udc-v2";
-                reg = <0xf0b02000 0xfc4>;
-                interrupts = <0x0 0x60 0x0>;
-                phys = <&usbphy_0 0x0>;
-                clocks = <&sw_usbd>;
-        };
+    usb@f0b02000 {
+        compatible = "brcm,bdc-udc-v2";
+        reg = <0xf0b02000 0xfc4>;
+        interrupts = <0x0 0x60 0x0>;
+        phys = <&usbphy_0 0x0>;
+        clocks = <&sw_usbd>;
+    };
diff --git a/dts/upstream/Bindings/usb/cypress,hx3.yaml b/dts/upstream/Bindings/usb/cypress,hx3.yaml
index e44e88d993d..1033b7a4b8f 100644
--- a/dts/upstream/Bindings/usb/cypress,hx3.yaml
+++ b/dts/upstream/Bindings/usb/cypress,hx3.yaml
@@ -56,21 +56,21 @@ examples:
 
         /* 2.0 hub on port 1 */
         hub_2_0: hub@1 {
-          compatible = "usb4b4,6504";
-          reg = <1>;
-          peer-hub = <&hub_3_0>;
-          reset-gpios = <&gpio1 11 GPIO_ACTIVE_LOW>;
-          vdd-supply = <&reg_1v2_usb>;
-          vdd2-supply = <&reg_3v3_usb>;
+            compatible = "usb4b4,6504";
+            reg = <1>;
+            peer-hub = <&hub_3_0>;
+            reset-gpios = <&gpio1 11 GPIO_ACTIVE_LOW>;
+            vdd-supply = <&reg_1v2_usb>;
+            vdd2-supply = <&reg_3v3_usb>;
         };
 
         /* 3.0 hub on port 2 */
         hub_3_0: hub@2 {
-          compatible = "usb4b4,6506";
-          reg = <2>;
-          peer-hub = <&hub_2_0>;
-          reset-gpios = <&gpio1 11 GPIO_ACTIVE_LOW>;
-          vdd-supply = <&reg_1v2_usb>;
-          vdd2-supply = <&reg_3v3_usb>;
+            compatible = "usb4b4,6506";
+            reg = <2>;
+            peer-hub = <&hub_2_0>;
+            reset-gpios = <&gpio1 11 GPIO_ACTIVE_LOW>;
+            vdd-supply = <&reg_1v2_usb>;
+            vdd2-supply = <&reg_3v3_usb>;
         };
     };
diff --git a/dts/upstream/Bindings/usb/dwc2.yaml b/dts/upstream/Bindings/usb/dwc2.yaml
index a5f2e3442a0..e83d30a91b8 100644
--- a/dts/upstream/Bindings/usb/dwc2.yaml
+++ b/dts/upstream/Bindings/usb/dwc2.yaml
@@ -192,7 +192,7 @@ unevaluatedProperties: false
 
 examples:
   - |
-      usb@101c0000 {
+    usb@101c0000 {
         compatible = "rockchip,rk3066-usb", "snps,dwc2";
         reg = <0x10180000 0x40000>;
         interrupts = <18>;
@@ -200,6 +200,6 @@ examples:
         clock-names = "otg";
         phys = <&usbphy>;
         phy-names = "usb2-phy";
-      };
+    };
 
 ...
diff --git a/dts/upstream/Bindings/usb/fcs,fsa4480.yaml b/dts/upstream/Bindings/usb/fcs,fsa4480.yaml
index 8b25b9a01ce..e3a7df91f7f 100644
--- a/dts/upstream/Bindings/usb/fcs,fsa4480.yaml
+++ b/dts/upstream/Bindings/usb/fcs,fsa4480.yaml
@@ -87,21 +87,21 @@ examples:
         #size-cells = <0>;
 
         typec-mux@42 {
-          compatible = "fcs,fsa4480";
-          reg = <0x42>;
+            compatible = "fcs,fsa4480";
+            reg = <0x42>;
 
-          interrupts-extended = <&tlmm 2 IRQ_TYPE_LEVEL_LOW>;
+            interrupts-extended = <&tlmm 2 IRQ_TYPE_LEVEL_LOW>;
 
-          vcc-supply = <&vreg_bob>;
+            vcc-supply = <&vreg_bob>;
 
-          mode-switch;
-          orientation-switch;
+            mode-switch;
+            orientation-switch;
 
-          port {
-            fsa4480_ept: endpoint {
-              remote-endpoint = <&typec_controller>;
+            port {
+                fsa4480_ept: endpoint {
+                    remote-endpoint = <&typec_controller>;
+                };
             };
-          };
         };
     };
 ...
diff --git a/dts/upstream/Bindings/usb/gpio-sbu-mux.yaml b/dts/upstream/Bindings/usb/gpio-sbu-mux.yaml
index 8a5f837eff9..e588514fab2 100644
--- a/dts/upstream/Bindings/usb/gpio-sbu-mux.yaml
+++ b/dts/upstream/Bindings/usb/gpio-sbu-mux.yaml
@@ -20,6 +20,7 @@ properties:
     items:
       - enum:
           - nxp,cbdtu02043
+          - onnn,fsusb42
           - onnn,fsusb43l10x
           - pericom,pi3usb102
           - ti,tmuxhs4212
diff --git a/dts/upstream/Bindings/usb/intel,keembay-dwc3.yaml b/dts/upstream/Bindings/usb/intel,keembay-dwc3.yaml
index d3511f48cd5..1a75544a8c3 100644
--- a/dts/upstream/Bindings/usb/intel,keembay-dwc3.yaml
+++ b/dts/upstream/Bindings/usb/intel,keembay-dwc3.yaml
@@ -58,20 +58,20 @@ examples:
     #define KEEM_BAY_A53_AUX_USB_SUSPEND
 
     usb {
-          compatible = "intel,keembay-dwc3";
-          clocks = <&scmi_clk KEEM_BAY_A53_AUX_USB>,
-                   <&scmi_clk KEEM_BAY_A53_AUX_USB_REF>,
-                   <&scmi_clk KEEM_BAY_A53_AUX_USB_ALT_REF>,
-                   <&scmi_clk KEEM_BAY_A53_AUX_USB_SUSPEND>;
-          clock-names = "async_master", "ref", "alt_ref", "suspend";
-          ranges;
-          #address-cells = <1>;
-          #size-cells = <1>;
-
-          usb@34000000 {
-                compatible = "snps,dwc3";
-                reg = <0x34000000 0x10000>;
-                interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
-                dr_mode = "peripheral";
-          };
+        compatible = "intel,keembay-dwc3";
+        clocks = <&scmi_clk KEEM_BAY_A53_AUX_USB>,
+                 <&scmi_clk KEEM_BAY_A53_AUX_USB_REF>,
+                 <&scmi_clk KEEM_BAY_A53_AUX_USB_ALT_REF>,
+                 <&scmi_clk KEEM_BAY_A53_AUX_USB_SUSPEND>;
+        clock-names = "async_master", "ref", "alt_ref", "suspend";
+        ranges;
+        #address-cells = <1>;
+        #size-cells = <1>;
+
+        usb@34000000 {
+            compatible = "snps,dwc3";
+            reg = <0x34000000 0x10000>;
+            interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
+            dr_mode = "peripheral";
+        };
     };
diff --git a/dts/upstream/Bindings/usb/ite,it5205.yaml b/dts/upstream/Bindings/usb/ite,it5205.yaml
index 36ec4251b5f..889710733de 100644
--- a/dts/upstream/Bindings/usb/ite,it5205.yaml
+++ b/dts/upstream/Bindings/usb/ite,it5205.yaml
@@ -54,19 +54,19 @@ examples:
         #size-cells = <0>;
 
         typec-mux@48 {
-          compatible = "ite,it5205";
-          reg = <0x48>;
+            compatible = "ite,it5205";
+            reg = <0x48>;
 
-          mode-switch;
-          orientation-switch;
+            mode-switch;
+            orientation-switch;
 
-          vcc-supply = <&mt6359_vibr_ldo_reg>;
+            vcc-supply = <&mt6359_vibr_ldo_reg>;
 
-          port {
-            it5205_usbss_sbu: endpoint {
-              remote-endpoint = <&typec_controller>;
+            port {
+                it5205_usbss_sbu: endpoint {
+                    remote-endpoint = <&typec_controller>;
+                };
             };
-          };
         };
     };
 ...
diff --git a/dts/upstream/Bindings/usb/maxim,max33359.yaml b/dts/upstream/Bindings/usb/maxim,max33359.yaml
index 20b62228371..3de4dc40b79 100644
--- a/dts/upstream/Bindings/usb/maxim,max33359.yaml
+++ b/dts/upstream/Bindings/usb/maxim,max33359.yaml
@@ -13,8 +13,12 @@ description: Maxim TCPCI Type-C PD controller
 
 properties:
   compatible:
-    enum:
-      - maxim,max33359
+    oneOf:
+      - enum:
+          - maxim,max33359
+      - items:
+          - const: maxim,max77759-tcpci
+          - const: maxim,max33359
 
   reg:
     maxItems: 1
@@ -70,6 +74,7 @@ examples:
                                        PDO_FIXED_DUAL_ROLE)
                                        PDO_FIXED(9000, 2000, 0)>;
                 sink-bc12-completion-time-ms = <500>;
+                pd-revision = /bits/ 8 <0x03 0x01 0x01 0x08>;
             };
         };
     };
diff --git a/dts/upstream/Bindings/usb/maxim,max3420-udc.yaml b/dts/upstream/Bindings/usb/maxim,max3420-udc.yaml
index 8e0f4ecc010..6edb1fc5044 100644
--- a/dts/upstream/Bindings/usb/maxim,max3420-udc.yaml
+++ b/dts/upstream/Bindings/usb/maxim,max3420-udc.yaml
@@ -50,18 +50,18 @@ additionalProperties: false
 
 examples:
   - |
-      #include <dt-bindings/gpio/gpio.h>
-      #include <dt-bindings/interrupt-controller/irq.h>
-      spi {
-            #address-cells = <1>;
-            #size-cells = <0>;
+    #include <dt-bindings/gpio/gpio.h>
+    #include <dt-bindings/interrupt-controller/irq.h>
+    spi {
+        #address-cells = <1>;
+        #size-cells = <0>;
 
-            udc@0 {
-                  compatible = "maxim,max3420-udc";
-                  reg = <0>;
-                  interrupt-parent = <&gpio>;
-                  interrupts = <0 IRQ_TYPE_EDGE_FALLING>, <10 IRQ_TYPE_EDGE_BOTH>;
-                  interrupt-names = "udc", "vbus";
-                  spi-max-frequency = <12500000>;
-            };
-      };
+        udc@0 {
+            compatible = "maxim,max3420-udc";
+            reg = <0>;
+            interrupt-parent = <&gpio>;
+            interrupts = <0 IRQ_TYPE_EDGE_FALLING>, <10 IRQ_TYPE_EDGE_BOTH>;
+            interrupt-names = "udc", "vbus";
+            spi-max-frequency = <12500000>;
+        };
+    };
diff --git a/dts/upstream/Bindings/usb/nvidia,tegra210-xusb.yaml b/dts/upstream/Bindings/usb/nvidia,tegra210-xusb.yaml
index 90296613b3a..c0e313c70bb 100644
--- a/dts/upstream/Bindings/usb/nvidia,tegra210-xusb.yaml
+++ b/dts/upstream/Bindings/usb/nvidia,tegra210-xusb.yaml
@@ -189,7 +189,7 @@ examples:
         #size-cells = <0>;
 
         ethernet@1 {
-                compatible = "usb955,9ff";
-                reg = <1>;
+            compatible = "usb955,9ff";
+            reg = <1>;
         };
     };
diff --git a/dts/upstream/Bindings/usb/qcom,dwc3.yaml b/dts/upstream/Bindings/usb/qcom,dwc3.yaml
index 935e204b607..a2b3cf625e5 100644
--- a/dts/upstream/Bindings/usb/qcom,dwc3.yaml
+++ b/dts/upstream/Bindings/usb/qcom,dwc3.yaml
@@ -16,6 +16,7 @@ properties:
           - qcom,ipq4019-dwc3
           - qcom,ipq5018-dwc3
           - qcom,ipq5332-dwc3
+          - qcom,ipq5424-dwc3
           - qcom,ipq6018-dwc3
           - qcom,ipq8064-dwc3
           - qcom,ipq8074-dwc3
@@ -26,6 +27,7 @@ properties:
           - qcom,msm8998-dwc3
           - qcom,qcm2290-dwc3
           - qcom,qcs404-dwc3
+          - qcom,qcs615-dwc3
           - qcom,qcs8300-dwc3
           - qcom,qdu1000-dwc3
           - qcom,sa8775p-dwc3
@@ -341,6 +343,7 @@ allOf:
           contains:
             enum:
               - qcom,qcm2290-dwc3
+              - qcom,qcs615-dwc3
               - qcom,sar2130p-dwc3
               - qcom,sc8180x-dwc3
               - qcom,sc8180x-dwc3-mp
@@ -453,8 +456,10 @@ allOf:
     then:
       properties:
         interrupts:
+          minItems: 3
           maxItems: 4
         interrupt-names:
+          minItems: 3
           items:
             - const: pwr_event
             - const: dp_hs_phy_irq
@@ -469,6 +474,7 @@ allOf:
               - qcom,ipq4019-dwc3
               - qcom,ipq8064-dwc3
               - qcom,msm8994-dwc3
+              - qcom,qcs615-dwc3
               - qcom,qcs8300-dwc3
               - qcom,qdu1000-dwc3
               - qcom,sa8775p-dwc3
diff --git a/dts/upstream/Bindings/usb/renesas,rzv2m-usb3drd.yaml b/dts/upstream/Bindings/usb/renesas,rzv2m-usb3drd.yaml
index ff625600d9a..b87e139c29e 100644
--- a/dts/upstream/Bindings/usb/renesas,rzv2m-usb3drd.yaml
+++ b/dts/upstream/Bindings/usb/renesas,rzv2m-usb3drd.yaml
@@ -104,26 +104,26 @@ examples:
         #size-cells = <1>;
 
         usb3host: usb@85060000 {
-           compatible = "renesas,r9a09g011-xhci",
-                        "renesas,rzv2m-xhci";
-           reg = <0x85060000 0x2000>;
-           interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>;
-           clocks = <&cpg CPG_MOD R9A09G011_USB_ACLK_H>,
-                    <&cpg CPG_MOD R9A09G011_USB_PCLK>;
-           clock-names = "axi", "reg";
-           power-domains = <&cpg>;
-           resets = <&cpg R9A09G011_USB_ARESETN_H>;
+            compatible = "renesas,r9a09g011-xhci",
+                         "renesas,rzv2m-xhci";
+            reg = <0x85060000 0x2000>;
+            interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>;
+            clocks = <&cpg CPG_MOD R9A09G011_USB_ACLK_H>,
+                     <&cpg CPG_MOD R9A09G011_USB_PCLK>;
+            clock-names = "axi", "reg";
+            power-domains = <&cpg>;
+            resets = <&cpg R9A09G011_USB_ARESETN_H>;
         };
 
         usb3peri: usb3peri@85070000 {
-           compatible = "renesas,r9a09g011-usb3-peri",
-                        "renesas,rzv2m-usb3-peri";
-           reg = <0x85070000 0x400>;
-           interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
-           clocks = <&cpg CPG_MOD R9A09G011_USB_ACLK_P>,
-                    <&cpg CPG_MOD R9A09G011_USB_PCLK>;
-           clock-names = "axi", "reg";
-           power-domains = <&cpg>;
-           resets = <&cpg R9A09G011_USB_ARESETN_P>;
+            compatible = "renesas,r9a09g011-usb3-peri",
+                         "renesas,rzv2m-usb3-peri";
+            reg = <0x85070000 0x400>;
+            interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
+            clocks = <&cpg CPG_MOD R9A09G011_USB_ACLK_P>,
+                     <&cpg CPG_MOD R9A09G011_USB_PCLK>;
+            clock-names = "axi", "reg";
+            power-domains = <&cpg>;
+            resets = <&cpg R9A09G011_USB_ARESETN_P>;
         };
     };
diff --git a/dts/upstream/Bindings/usb/renesas,usb3-peri.yaml b/dts/upstream/Bindings/usb/renesas,usb3-peri.yaml
index b2b811a0ade..4e56e4ffeaf 100644
--- a/dts/upstream/Bindings/usb/renesas,usb3-peri.yaml
+++ b/dts/upstream/Bindings/usb/renesas,usb3-peri.yaml
@@ -132,19 +132,19 @@ examples:
         usb-role-switch;
 
         ports {
-                #address-cells = <1>;
-                #size-cells = <0>;
-                port@0 {
-                        reg = <0>;
-                        usb3_hs_ep: endpoint {
-                                remote-endpoint = <&hs_ep>;
-                        };
+            #address-cells = <1>;
+            #size-cells = <0>;
+            port@0 {
+                reg = <0>;
+                usb3_hs_ep: endpoint {
+                    remote-endpoint = <&hs_ep>;
                 };
-                port@1 {
-                        reg = <1>;
-                        usb3_role_switch: endpoint {
-                                remote-endpoint = <&hd3ss3220_out_ep>;
-                        };
+            };
+            port@1 {
+                reg = <1>;
+                usb3_role_switch: endpoint {
+                    remote-endpoint = <&hd3ss3220_out_ep>;
                 };
+            };
         };
     };
diff --git a/dts/upstream/Bindings/usb/renesas,usbhs.yaml b/dts/upstream/Bindings/usb/renesas,usbhs.yaml
index b23ef29bf79..980f325341d 100644
--- a/dts/upstream/Bindings/usb/renesas,usbhs.yaml
+++ b/dts/upstream/Bindings/usb/renesas,usbhs.yaml
@@ -26,6 +26,7 @@ properties:
               - renesas,usbhs-r9a07g043 # RZ/G2UL and RZ/Five
               - renesas,usbhs-r9a07g044 # RZ/G2{L,LC}
               - renesas,usbhs-r9a07g054 # RZ/V2L
+              - renesas,usbhs-r9a08g045 # RZ/G3S
           - const: renesas,rzg2l-usbhs
 
       - items:
@@ -130,6 +131,7 @@ allOf:
               - renesas,usbhs-r9a07g043
               - renesas,usbhs-r9a07g044
               - renesas,usbhs-r9a07g054
+              - renesas,usbhs-r9a08g045
     then:
       properties:
         interrupts:
diff --git a/dts/upstream/Bindings/usb/snps,dwc3-common.yaml b/dts/upstream/Bindings/usb/snps,dwc3-common.yaml
new file mode 100644
index 00000000000..c956053fd03
--- /dev/null
+++ b/dts/upstream/Bindings/usb/snps,dwc3-common.yaml
@@ -0,0 +1,415 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/usb/snps,dwc3-common.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Synopsys DesignWare USB3 Controller common properties
+
+maintainers:
+  - Felipe Balbi <balbi@kernel.org>
+
+description:
+  Defines the properties of the DWC3 core as being embedded in either an
+  vendor-specific implementation or as a standalone component.
+
+allOf:
+  - $ref: usb-drd.yaml#
+  - if:
+      properties:
+        dr_mode:
+          const: peripheral
+
+      required:
+        - dr_mode
+    then:
+      $ref: usb.yaml#
+    else:
+      $ref: usb-xhci.yaml#
+
+properties:
+  extcon:
+    maxItems: 1
+    deprecated: true
+
+  usb-phy:
+    minItems: 1
+    items:
+      - description: USB2/HS PHY
+      - description: USB3/SS PHY
+
+  phys:
+    minItems: 1
+    maxItems: 19
+
+  phy-names:
+    minItems: 1
+    maxItems: 19
+    oneOf:
+      - items:
+          enum: [ usb2-phy, usb3-phy ]
+      - items:
+          pattern: "^usb(2-([0-9]|1[0-4])|3-[0-3])$"
+
+  snps,usb2-lpm-disable:
+    description: Indicate if we don't want to enable USB2 HW LPM for host
+      mode.
+    type: boolean
+
+  snps,usb3_lpm_capable:
+    description: Determines if platform is USB3 LPM capable
+    type: boolean
+
+  snps,usb2-gadget-lpm-disable:
+    description: Indicate if we don't want to enable USB2 HW LPM for gadget
+      mode.
+    type: boolean
+
+  snps,dis-start-transfer-quirk:
+    description:
+      When set, disable isoc START TRANSFER command failure SW work-around
+      for DWC_usb31 version 1.70a-ea06 and prior.
+    type: boolean
+
+  snps,disable_scramble_quirk:
+    description:
+      True when SW should disable data scrambling. Only really useful for FPGA
+      builds.
+    type: boolean
+
+  snps,has-lpm-erratum:
+    description: True when DWC3 was configured with LPM Erratum enabled
+    type: boolean
+
+  snps,lpm-nyet-threshold:
+    description: LPM NYET threshold
+    $ref: /schemas/types.yaml#/definitions/uint8
+
+  snps,u2exit_lfps_quirk:
+    description: Set if we want to enable u2exit lfps quirk
+    type: boolean
+
+  snps,u2ss_inp3_quirk:
+    description: Set if we enable P3 OK for U2/SS Inactive quirk
+    type: boolean
+
+  snps,req_p1p2p3_quirk:
+    description:
+      When set, the core will always request for P1/P2/P3 transition sequence.
+    type: boolean
+
+  snps,del_p1p2p3_quirk:
+    description:
+      When set core will delay P1/P2/P3 until a certain amount of 8B10B errors
+      occur.
+    type: boolean
+
+  snps,del_phy_power_chg_quirk:
+    description: When set core will delay PHY power change from P0 to P1/P2/P3.
+    type: boolean
+
+  snps,lfps_filter_quirk:
+    description: When set core will filter LFPS reception.
+    type: boolean
+
+  snps,rx_detect_poll_quirk:
+    description:
+      when set core will disable a 400us delay to start Polling LFPS after
+      RX.Detect.
+    type: boolean
+
+  snps,tx_de_emphasis_quirk:
+    description: When set core will set Tx de-emphasis value
+    type: boolean
+
+  snps,tx_de_emphasis:
+    description:
+      The value driven to the PHY is controlled by the LTSSM during USB3
+      Compliance mode.
+    $ref: /schemas/types.yaml#/definitions/uint8
+    enum:
+      - 0 # -6dB de-emphasis
+      - 1 # -3.5dB de-emphasis
+      - 2 # No de-emphasis
+
+  snps,dis_u3_susphy_quirk:
+    description: When set core will disable USB3 suspend phy
+    type: boolean
+
+  snps,dis_u2_susphy_quirk:
+    description: When set core will disable USB2 suspend phy
+    type: boolean
+
+  snps,dis_enblslpm_quirk:
+    description:
+      When set clears the enblslpm in GUSB2PHYCFG, disabling the suspend signal
+      to the PHY.
+    type: boolean
+
+  snps,dis-u1-entry-quirk:
+    description: Set if link entering into U1 needs to be disabled
+    type: boolean
+
+  snps,dis-u2-entry-quirk:
+    description: Set if link entering into U2 needs to be disabled
+    type: boolean
+
+  snps,dis_rxdet_inp3_quirk:
+    description:
+      When set core will disable receiver detection in PHY P3 power state.
+    type: boolean
+
+  snps,dis-u2-freeclk-exists-quirk:
+    description:
+      When set, clear the u2_freeclk_exists in GUSB2PHYCFG, specify that USB2
+      PHY doesn't provide a free-running PHY clock.
+    type: boolean
+
+  snps,dis-del-phy-power-chg-quirk:
+    description:
+      When set core will change PHY power from P0 to P1/P2/P3 without delay.
+    type: boolean
+
+  snps,dis-tx-ipgap-linecheck-quirk:
+    description: When set, disable u2mac linestate check during HS transmit
+    type: boolean
+
+  snps,parkmode-disable-ss-quirk:
+    description:
+      When set, all SuperSpeed bus instances in park mode are disabled.
+    type: boolean
+
+  snps,parkmode-disable-hs-quirk:
+    description:
+      When set, all HighSpeed bus instances in park mode are disabled.
+    type: boolean
+
+  snps,dis_metastability_quirk:
+    description:
+      When set, disable metastability workaround. CAUTION! Use only if you are
+      absolutely sure of it.
+    type: boolean
+
+  snps,dis-split-quirk:
+    description:
+      When set, change the way URBs are handled by the driver. Needed to
+      avoid -EPROTO errors with usbhid on some devices (Hikey 970).
+    type: boolean
+
+  snps,gfladj-refclk-lpm-sel-quirk:
+    description:
+      When set, run the SOF/ITP counter based on ref_clk.
+    type: boolean
+
+  snps,resume-hs-terminations:
+    description:
+      Fix the issue of HS terminations CRC error on resume by enabling this
+      quirk. When set, all the termsel, xcvrsel, opmode becomes 0 during end
+      of resume. This option is to support certain legacy ULPI PHYs.
+    type: boolean
+
+  snps,ulpi-ext-vbus-drv:
+    description:
+      Some ULPI USB PHY does not support internal VBUS supply, and driving
+      the CPEN pin, requires the configuration of the ulpi DRVVBUSEXTERNAL
+      bit. When set, the xhci host will configure the USB2 PHY drives VBUS
+      with an external supply.
+    type: boolean
+
+  snps,is-utmi-l1-suspend:
+    description:
+      True when DWC3 asserts output signal utmi_l1_suspend_n, false when
+      asserts utmi_sleep_n.
+    type: boolean
+
+  snps,hird-threshold:
+    description: HIRD threshold
+    $ref: /schemas/types.yaml#/definitions/uint8
+
+  snps,hsphy_interface:
+    description:
+      High-Speed PHY interface selection between UTMI+ and ULPI when the
+      DWC_USB3_HSPHY_INTERFACE has value 3.
+    $ref: /schemas/types.yaml#/definitions/string
+    enum: [utmi, ulpi]
+
+  snps,quirk-frame-length-adjustment:
+    description:
+      Value for GFLADJ_30MHZ field of GFLADJ register for post-silicon frame
+      length adjustment when the fladj_30mhz_sdbnd signal is invalid or
+      incorrect.
+    $ref: /schemas/types.yaml#/definitions/uint32
+    minimum: 0
+    maximum: 0x3f
+
+  snps,ref-clock-period-ns:
+    description:
+      Value for REFCLKPER field of GUCTL register for reference clock period in
+      nanoseconds, when the hardware set default does not match the actual
+      clock.
+
+      This binding is deprecated. Instead, provide an appropriate reference clock.
+    minimum: 8
+    maximum: 62
+    deprecated: true
+
+  snps,rx-thr-num-pkt:
+    description:
+      USB RX packet threshold count. In host mode, this field specifies
+      the space that must be available in the RX FIFO before the core can
+      start the corresponding USB RX transaction (burst).
+      In device mode, this field specifies the space that must be
+      available in the RX FIFO before the core can send ERDY for a
+      flow-controlled endpoint. It is only used for SuperSpeed.
+      The valid values for this field are from 1 to 15. (DWC3 SuperSpeed
+      USB 3.0 Controller Databook)
+    $ref: /schemas/types.yaml#/definitions/uint8
+    minimum: 1
+    maximum: 15
+
+  snps,rx-max-burst:
+    description:
+      Max USB RX burst size. In host mode, this field specifies the
+      Maximum Bulk IN burst the DWC_usb3 core can perform. When the system
+      bus is slower than the USB, RX FIFO can overrun during a long burst.
+      You can program a smaller value to this field to limit the RX burst
+      size that the core can perform. It only applies to SS Bulk,
+      Isochronous, and Interrupt IN endpoints in the host mode.
+      In device mode, this field specifies the NUMP value that is sent in
+      ERDY for an OUT endpoint.
+      The valid values for this field are from 1 to 16. (DWC3 SuperSpeed
+      USB 3.0 Controller Databook)
+    $ref: /schemas/types.yaml#/definitions/uint8
+    minimum: 1
+    maximum: 16
+
+  snps,tx-thr-num-pkt:
+    description:
+      USB TX packet threshold count. This field specifies the number of
+      packets that must be in the TXFIFO before the core can start
+      transmission for the corresponding USB transaction (burst).
+      This count is valid in both host and device modes. It is only used
+      for SuperSpeed operation.
+      Valid values are from 1 to 15. (DWC3 SuperSpeed USB 3.0 Controller
+      Databook)
+    $ref: /schemas/types.yaml#/definitions/uint8
+    minimum: 1
+    maximum: 15
+
+  snps,tx-max-burst:
+    description:
+      Max USB TX burst size. When the system bus is slower than the USB,
+      TX FIFO can underrun during a long burst. Program a smaller value
+      to this field to limit the TX burst size that the core can execute.
+      In Host mode, it only applies to SS Bulk, Isochronous, and Interrupt
+      OUT endpoints. This value is not used in device mode.
+      Valid values are from 1 to 16. (DWC3 SuperSpeed USB 3.0 Controller
+      Databook)
+    $ref: /schemas/types.yaml#/definitions/uint8
+    minimum: 1
+    maximum: 16
+
+  snps,rx-thr-num-pkt-prd:
+    description:
+      Periodic ESS RX packet threshold count (host mode only). Set this and
+      snps,rx-max-burst-prd to a valid, non-zero value 1-16 (DWC_usb31
+      programming guide section 1.2.4) to enable periodic ESS RX threshold.
+    $ref: /schemas/types.yaml#/definitions/uint8
+    minimum: 1
+    maximum: 16
+
+  snps,rx-max-burst-prd:
+    description:
+      Max periodic ESS RX burst size (host mode only). Set this and
+      snps,rx-thr-num-pkt-prd to a valid, non-zero value 1-16 (DWC_usb31
+      programming guide section 1.2.4) to enable periodic ESS RX threshold.
+    $ref: /schemas/types.yaml#/definitions/uint8
+    minimum: 1
+    maximum: 16
+
+  snps,tx-thr-num-pkt-prd:
+    description:
+      Periodic ESS TX packet threshold count (host mode only). Set this and
+      snps,tx-max-burst-prd to a valid, non-zero value 1-16 (DWC_usb31
+      programming guide section 1.2.3) to enable periodic ESS TX threshold.
+    $ref: /schemas/types.yaml#/definitions/uint8
+    minimum: 1
+    maximum: 16
+
+  snps,tx-max-burst-prd:
+    description:
+      Max periodic ESS TX burst size (host mode only). Set this and
+      snps,tx-thr-num-pkt-prd to a valid, non-zero value 1-16 (DWC_usb31
+      programming guide section 1.2.3) to enable periodic ESS TX threshold.
+    $ref: /schemas/types.yaml#/definitions/uint8
+    minimum: 1
+    maximum: 16
+
+  tx-fifo-resize:
+    description: Determines if the TX fifos can be dynamically resized depending
+      on the number of IN endpoints used and if bursting is supported.  This
+      may help improve bandwidth on platforms with higher system latencies, as
+      increased fifo space allows for the controller to prefetch data into its
+      internal memory.
+    type: boolean
+
+  tx-fifo-max-num:
+    description: Specifies the max number of packets the txfifo resizing logic
+      can account for when higher endpoint bursting is used. (bMaxBurst > 6) The
+      higher the number, the more fifo space the txfifo resizing logic will
+      allocate for that endpoint.
+    $ref: /schemas/types.yaml#/definitions/uint8
+    minimum: 3
+
+  snps,incr-burst-type-adjustment:
+    description:
+      Value for INCR burst type of GSBUSCFG0 register, undefined length INCR
+      burst type enable and INCRx type. A single value means INCRX burst mode
+      enabled. If more than one value specified, undefined length INCR burst
+      type will be enabled with burst lengths utilized up to the maximum
+      of the values passed in this property.
+    $ref: /schemas/types.yaml#/definitions/uint32-array
+    minItems: 1
+    maxItems: 8
+    uniqueItems: true
+    items:
+      enum: [1, 4, 8, 16, 32, 64, 128, 256]
+
+  num-hc-interrupters:
+    maximum: 8
+    default: 1
+
+  port:
+    $ref: /schemas/graph.yaml#/properties/port
+    description:
+      This port is used with the 'usb-role-switch' property  to connect the
+      dwc3 to type C connector.
+
+  ports:
+    $ref: /schemas/graph.yaml#/properties/ports
+    description:
+      Those ports should be used with any connector to the data bus of this
+      controller using the OF graph bindings specified if the "usb-role-switch"
+      property is used.
+
+    properties:
+      port@0:
+        $ref: /schemas/graph.yaml#/properties/port
+        description: High Speed (HS) data bus.
+
+      port@1:
+        $ref: /schemas/graph.yaml#/properties/port
+        description: Super Speed (SS) data bus.
+
+  wakeup-source:
+    $ref: /schemas/types.yaml#/definitions/flag
+    description:
+      Enable USB remote wakeup.
+
+required:
+  - compatible
+  - reg
+
+additionalProperties: true
+...
+
diff --git a/dts/upstream/Bindings/usb/snps,dwc3.yaml b/dts/upstream/Bindings/usb/snps,dwc3.yaml
index 1cd0ca90127..4380bb6fa2f 100644
--- a/dts/upstream/Bindings/usb/snps,dwc3.yaml
+++ b/dts/upstream/Bindings/usb/snps,dwc3.yaml
@@ -15,18 +15,7 @@ description:
   compatible string.
 
 allOf:
-  - $ref: usb-drd.yaml#
-  - if:
-      properties:
-        dr_mode:
-          const: peripheral
-
-      required:
-        - dr_mode
-    then:
-      $ref: usb.yaml#
-    else:
-      $ref: usb-xhci.yaml#
+  - $ref: snps,dwc3-common.yaml#
 
 properties:
   compatible:
@@ -70,32 +59,9 @@ properties:
 
   dma-coherent: true
 
-  extcon:
-    maxItems: 1
-    deprecated: true
-
   iommus:
     maxItems: 1
 
-  usb-phy:
-    minItems: 1
-    items:
-      - description: USB2/HS PHY
-      - description: USB3/SS PHY
-
-  phys:
-    minItems: 1
-    maxItems: 19
-
-  phy-names:
-    minItems: 1
-    maxItems: 19
-    oneOf:
-      - items:
-          enum: [ usb2-phy, usb3-phy ]
-      - items:
-          pattern: "^usb(2-([0-9]|1[0-4])|3-[0-3])$"
-
   power-domains:
     description:
       The DWC3 has 2 power-domains. The power management unit (PMU) and
@@ -109,361 +75,6 @@ properties:
   resets:
     minItems: 1
 
-  snps,usb2-lpm-disable:
-    description: Indicate if we don't want to enable USB2 HW LPM for host
-      mode.
-    type: boolean
-
-  snps,usb3_lpm_capable:
-    description: Determines if platform is USB3 LPM capable
-    type: boolean
-
-  snps,usb2-gadget-lpm-disable:
-    description: Indicate if we don't want to enable USB2 HW LPM for gadget
-      mode.
-    type: boolean
-
-  snps,dis-start-transfer-quirk:
-    description:
-      When set, disable isoc START TRANSFER command failure SW work-around
-      for DWC_usb31 version 1.70a-ea06 and prior.
-    type: boolean
-
-  snps,disable_scramble_quirk:
-    description:
-      True when SW should disable data scrambling. Only really useful for FPGA
-      builds.
-    type: boolean
-
-  snps,has-lpm-erratum:
-    description: True when DWC3 was configured with LPM Erratum enabled
-    type: boolean
-
-  snps,lpm-nyet-threshold:
-    description: LPM NYET threshold
-    $ref: /schemas/types.yaml#/definitions/uint8
-
-  snps,u2exit_lfps_quirk:
-    description: Set if we want to enable u2exit lfps quirk
-    type: boolean
-
-  snps,u2ss_inp3_quirk:
-    description: Set if we enable P3 OK for U2/SS Inactive quirk
-    type: boolean
-
-  snps,req_p1p2p3_quirk:
-    description:
-      When set, the core will always request for P1/P2/P3 transition sequence.
-    type: boolean
-
-  snps,del_p1p2p3_quirk:
-    description:
-      When set core will delay P1/P2/P3 until a certain amount of 8B10B errors
-      occur.
-    type: boolean
-
-  snps,del_phy_power_chg_quirk:
-    description: When set core will delay PHY power change from P0 to P1/P2/P3.
-    type: boolean
-
-  snps,lfps_filter_quirk:
-    description: When set core will filter LFPS reception.
-    type: boolean
-
-  snps,rx_detect_poll_quirk:
-    description:
-      when set core will disable a 400us delay to start Polling LFPS after
-      RX.Detect.
-    type: boolean
-
-  snps,tx_de_emphasis_quirk:
-    description: When set core will set Tx de-emphasis value
-    type: boolean
-
-  snps,tx_de_emphasis:
-    description:
-      The value driven to the PHY is controlled by the LTSSM during USB3
-      Compliance mode.
-    $ref: /schemas/types.yaml#/definitions/uint8
-    enum:
-      - 0 # -6dB de-emphasis
-      - 1 # -3.5dB de-emphasis
-      - 2 # No de-emphasis
-
-  snps,dis_u3_susphy_quirk:
-    description: When set core will disable USB3 suspend phy
-    type: boolean
-
-  snps,dis_u2_susphy_quirk:
-    description: When set core will disable USB2 suspend phy
-    type: boolean
-
-  snps,dis_enblslpm_quirk:
-    description:
-      When set clears the enblslpm in GUSB2PHYCFG, disabling the suspend signal
-      to the PHY.
-    type: boolean
-
-  snps,dis-u1-entry-quirk:
-    description: Set if link entering into U1 needs to be disabled
-    type: boolean
-
-  snps,dis-u2-entry-quirk:
-    description: Set if link entering into U2 needs to be disabled
-    type: boolean
-
-  snps,dis_rxdet_inp3_quirk:
-    description:
-      When set core will disable receiver detection in PHY P3 power state.
-    type: boolean
-
-  snps,dis-u2-freeclk-exists-quirk:
-    description:
-      When set, clear the u2_freeclk_exists in GUSB2PHYCFG, specify that USB2
-      PHY doesn't provide a free-running PHY clock.
-    type: boolean
-
-  snps,dis-del-phy-power-chg-quirk:
-    description:
-      When set core will change PHY power from P0 to P1/P2/P3 without delay.
-    type: boolean
-
-  snps,dis-tx-ipgap-linecheck-quirk:
-    description: When set, disable u2mac linestate check during HS transmit
-    type: boolean
-
-  snps,parkmode-disable-ss-quirk:
-    description:
-      When set, all SuperSpeed bus instances in park mode are disabled.
-    type: boolean
-
-  snps,parkmode-disable-hs-quirk:
-    description:
-      When set, all HighSpeed bus instances in park mode are disabled.
-    type: boolean
-
-  snps,dis_metastability_quirk:
-    description:
-      When set, disable metastability workaround. CAUTION! Use only if you are
-      absolutely sure of it.
-    type: boolean
-
-  snps,dis-split-quirk:
-    description:
-      When set, change the way URBs are handled by the driver. Needed to
-      avoid -EPROTO errors with usbhid on some devices (Hikey 970).
-    type: boolean
-
-  snps,gfladj-refclk-lpm-sel-quirk:
-    description:
-      When set, run the SOF/ITP counter based on ref_clk.
-    type: boolean
-
-  snps,resume-hs-terminations:
-    description:
-      Fix the issue of HS terminations CRC error on resume by enabling this
-      quirk. When set, all the termsel, xcvrsel, opmode becomes 0 during end
-      of resume. This option is to support certain legacy ULPI PHYs.
-    type: boolean
-
-  snps,ulpi-ext-vbus-drv:
-    description:
-      Some ULPI USB PHY does not support internal VBUS supply, and driving
-      the CPEN pin, requires the configuration of the ulpi DRVVBUSEXTERNAL
-      bit. When set, the xhci host will configure the USB2 PHY drives VBUS
-      with an external supply.
-    type: boolean
-
-  snps,is-utmi-l1-suspend:
-    description:
-      True when DWC3 asserts output signal utmi_l1_suspend_n, false when
-      asserts utmi_sleep_n.
-    type: boolean
-
-  snps,hird-threshold:
-    description: HIRD threshold
-    $ref: /schemas/types.yaml#/definitions/uint8
-
-  snps,hsphy_interface:
-    description:
-      High-Speed PHY interface selection between UTMI+ and ULPI when the
-      DWC_USB3_HSPHY_INTERFACE has value 3.
-    $ref: /schemas/types.yaml#/definitions/string
-    enum: [utmi, ulpi]
-
-  snps,quirk-frame-length-adjustment:
-    description:
-      Value for GFLADJ_30MHZ field of GFLADJ register for post-silicon frame
-      length adjustment when the fladj_30mhz_sdbnd signal is invalid or
-      incorrect.
-    $ref: /schemas/types.yaml#/definitions/uint32
-    minimum: 0
-    maximum: 0x3f
-
-  snps,ref-clock-period-ns:
-    description:
-      Value for REFCLKPER field of GUCTL register for reference clock period in
-      nanoseconds, when the hardware set default does not match the actual
-      clock.
-
-      This binding is deprecated. Instead, provide an appropriate reference clock.
-    minimum: 8
-    maximum: 62
-    deprecated: true
-
-  snps,rx-thr-num-pkt:
-    description:
-      USB RX packet threshold count. In host mode, this field specifies
-      the space that must be available in the RX FIFO before the core can
-      start the corresponding USB RX transaction (burst).
-      In device mode, this field specifies the space that must be
-      available in the RX FIFO before the core can send ERDY for a
-      flow-controlled endpoint. It is only used for SuperSpeed.
-      The valid values for this field are from 1 to 15. (DWC3 SuperSpeed
-      USB 3.0 Controller Databook)
-    $ref: /schemas/types.yaml#/definitions/uint8
-    minimum: 1
-    maximum: 15
-
-  snps,rx-max-burst:
-    description:
-      Max USB RX burst size. In host mode, this field specifies the
-      Maximum Bulk IN burst the DWC_usb3 core can perform. When the system
-      bus is slower than the USB, RX FIFO can overrun during a long burst.
-      You can program a smaller value to this field to limit the RX burst
-      size that the core can perform. It only applies to SS Bulk,
-      Isochronous, and Interrupt IN endpoints in the host mode.
-      In device mode, this field specifies the NUMP value that is sent in
-      ERDY for an OUT endpoint.
-      The valid values for this field are from 1 to 16. (DWC3 SuperSpeed
-      USB 3.0 Controller Databook)
-    $ref: /schemas/types.yaml#/definitions/uint8
-    minimum: 1
-    maximum: 16
-
-  snps,tx-thr-num-pkt:
-    description:
-      USB TX packet threshold count. This field specifies the number of
-      packets that must be in the TXFIFO before the core can start
-      transmission for the corresponding USB transaction (burst).
-      This count is valid in both host and device modes. It is only used
-      for SuperSpeed operation.
-      Valid values are from 1 to 15. (DWC3 SuperSpeed USB 3.0 Controller
-      Databook)
-    $ref: /schemas/types.yaml#/definitions/uint8
-    minimum: 1
-    maximum: 15
-
-  snps,tx-max-burst:
-    description:
-      Max USB TX burst size. When the system bus is slower than the USB,
-      TX FIFO can underrun during a long burst. Program a smaller value
-      to this field to limit the TX burst size that the core can execute.
-      In Host mode, it only applies to SS Bulk, Isochronous, and Interrupt
-      OUT endpoints. This value is not used in device mode.
-      Valid values are from 1 to 16. (DWC3 SuperSpeed USB 3.0 Controller
-      Databook)
-    $ref: /schemas/types.yaml#/definitions/uint8
-    minimum: 1
-    maximum: 16
-
-  snps,rx-thr-num-pkt-prd:
-    description:
-      Periodic ESS RX packet threshold count (host mode only). Set this and
-      snps,rx-max-burst-prd to a valid, non-zero value 1-16 (DWC_usb31
-      programming guide section 1.2.4) to enable periodic ESS RX threshold.
-    $ref: /schemas/types.yaml#/definitions/uint8
-    minimum: 1
-    maximum: 16
-
-  snps,rx-max-burst-prd:
-    description:
-      Max periodic ESS RX burst size (host mode only). Set this and
-      snps,rx-thr-num-pkt-prd to a valid, non-zero value 1-16 (DWC_usb31
-      programming guide section 1.2.4) to enable periodic ESS RX threshold.
-    $ref: /schemas/types.yaml#/definitions/uint8
-    minimum: 1
-    maximum: 16
-
-  snps,tx-thr-num-pkt-prd:
-    description:
-      Periodic ESS TX packet threshold count (host mode only). Set this and
-      snps,tx-max-burst-prd to a valid, non-zero value 1-16 (DWC_usb31
-      programming guide section 1.2.3) to enable periodic ESS TX threshold.
-    $ref: /schemas/types.yaml#/definitions/uint8
-    minimum: 1
-    maximum: 16
-
-  snps,tx-max-burst-prd:
-    description:
-      Max periodic ESS TX burst size (host mode only). Set this and
-      snps,tx-thr-num-pkt-prd to a valid, non-zero value 1-16 (DWC_usb31
-      programming guide section 1.2.3) to enable periodic ESS TX threshold.
-    $ref: /schemas/types.yaml#/definitions/uint8
-    minimum: 1
-    maximum: 16
-
-  tx-fifo-resize:
-    description: Determines if the TX fifos can be dynamically resized depending
-      on the number of IN endpoints used and if bursting is supported.  This
-      may help improve bandwidth on platforms with higher system latencies, as
-      increased fifo space allows for the controller to prefetch data into its
-      internal memory.
-    type: boolean
-
-  tx-fifo-max-num:
-    description: Specifies the max number of packets the txfifo resizing logic
-      can account for when higher endpoint bursting is used. (bMaxBurst > 6) The
-      higher the number, the more fifo space the txfifo resizing logic will
-      allocate for that endpoint.
-    $ref: /schemas/types.yaml#/definitions/uint8
-    minimum: 3
-
-  snps,incr-burst-type-adjustment:
-    description:
-      Value for INCR burst type of GSBUSCFG0 register, undefined length INCR
-      burst type enable and INCRx type. A single value means INCRX burst mode
-      enabled. If more than one value specified, undefined length INCR burst
-      type will be enabled with burst lengths utilized up to the maximum
-      of the values passed in this property.
-    $ref: /schemas/types.yaml#/definitions/uint32-array
-    minItems: 1
-    maxItems: 8
-    uniqueItems: true
-    items:
-      enum: [1, 4, 8, 16, 32, 64, 128, 256]
-
-  num-hc-interrupters:
-    maximum: 8
-    default: 1
-
-  port:
-    $ref: /schemas/graph.yaml#/properties/port
-    description:
-      This port is used with the 'usb-role-switch' property  to connect the
-      dwc3 to type C connector.
-
-  ports:
-    $ref: /schemas/graph.yaml#/properties/ports
-    description:
-      Those ports should be used with any connector to the data bus of this
-      controller using the OF graph bindings specified if the "usb-role-switch"
-      property is used.
-
-    properties:
-      port@0:
-        $ref: /schemas/graph.yaml#/properties/port
-        description: High Speed (HS) data bus.
-
-      port@1:
-        $ref: /schemas/graph.yaml#/properties/port
-        description: Super Speed (SS) data bus.
-
-  wakeup-source:
-    $ref: /schemas/types.yaml#/definitions/flag
-    description:
-      Enable USB remote wakeup.
-
 unevaluatedProperties: false
 
 required:
diff --git a/dts/upstream/Bindings/usb/ti,hd3ss3220.yaml b/dts/upstream/Bindings/usb/ti,hd3ss3220.yaml
index 54c6586cb56..bec1c8047bc 100644
--- a/dts/upstream/Bindings/usb/ti,hd3ss3220.yaml
+++ b/dts/upstream/Bindings/usb/ti,hd3ss3220.yaml
@@ -56,26 +56,26 @@ examples:
         #size-cells = <0>;
 
         hd3ss3220@47 {
-                compatible = "ti,hd3ss3220";
-                reg = <0x47>;
-                interrupt-parent = <&gpio6>;
-                interrupts = <3>;
+            compatible = "ti,hd3ss3220";
+            reg = <0x47>;
+            interrupt-parent = <&gpio6>;
+            interrupts = <3>;
 
-                ports {
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                        port@0 {
-                                reg = <0>;
-                                hd3ss3220_in_ep: endpoint {
-                                        remote-endpoint = <&ss_ep>;
-                                };
-                        };
-                        port@1 {
-                                reg = <1>;
-                                hd3ss3220_out_ep: endpoint {
-                                        remote-endpoint = <&usb3_role_switch>;
-                                };
-                        };
+            ports {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                port@0 {
+                    reg = <0>;
+                    hd3ss3220_in_ep: endpoint {
+                        remote-endpoint = <&ss_ep>;
+                    };
                 };
+                port@1 {
+                    reg = <1>;
+                    hd3ss3220_out_ep: endpoint {
+                        remote-endpoint = <&usb3_role_switch>;
+                    };
+                };
+            };
         };
     };
diff --git a/dts/upstream/Bindings/usb/ti,tusb73x0-pci.yaml b/dts/upstream/Bindings/usb/ti,tusb73x0-pci.yaml
index ddda734f36f..c4a91b3d661 100644
--- a/dts/upstream/Bindings/usb/ti,tusb73x0-pci.yaml
+++ b/dts/upstream/Bindings/usb/ti,tusb73x0-pci.yaml
@@ -48,8 +48,8 @@ examples:
         device_type = "pci";
 
         usb@0 {
-              compatible = "pci104c,8241";
-              reg = <0x0 0x0 0x0 0x0 0x0>;
-              ti,pwron-active-high;
+            compatible = "pci104c,8241";
+            reg = <0x0 0x0 0x0 0x0 0x0>;
+            ti,pwron-active-high;
         };
     };
diff --git a/dts/upstream/Bindings/usb/ti,usb8020b.yaml b/dts/upstream/Bindings/usb/ti,usb8020b.yaml
index 8ef117793e1..61217da8b2f 100644
--- a/dts/upstream/Bindings/usb/ti,usb8020b.yaml
+++ b/dts/upstream/Bindings/usb/ti,usb8020b.yaml
@@ -51,19 +51,19 @@ examples:
 
         /* 2.0 hub on port 1 */
         hub_2_0: hub@1 {
-          compatible = "usb451,8027";
-          reg = <1>;
-          peer-hub = <&hub_3_0>;
-          reset-gpios = <&pio 7 GPIO_ACTIVE_HIGH>;
-          vdd-supply = <&usb_hub_fixed_3v3>;
+            compatible = "usb451,8027";
+            reg = <1>;
+            peer-hub = <&hub_3_0>;
+            reset-gpios = <&pio 7 GPIO_ACTIVE_HIGH>;
+            vdd-supply = <&usb_hub_fixed_3v3>;
         };
 
         /* 3.0 hub on port 2 */
         hub_3_0: hub@2 {
-          compatible = "usb451,8025";
-          reg = <2>;
-          peer-hub = <&hub_2_0>;
-          reset-gpios = <&pio 7 GPIO_ACTIVE_HIGH>;
-          vdd-supply = <&usb_hub_fixed_3v3>;
+            compatible = "usb451,8025";
+            reg = <2>;
+            peer-hub = <&hub_2_0>;
+            reset-gpios = <&pio 7 GPIO_ACTIVE_HIGH>;
+            vdd-supply = <&usb_hub_fixed_3v3>;
         };
     };
diff --git a/dts/upstream/Bindings/usb/ti,usb8041.yaml b/dts/upstream/Bindings/usb/ti,usb8041.yaml
index c2e29bd61e1..bce730a5e23 100644
--- a/dts/upstream/Bindings/usb/ti,usb8041.yaml
+++ b/dts/upstream/Bindings/usb/ti,usb8041.yaml
@@ -51,17 +51,17 @@ examples:
 
         /* 2.0 hub on port 1 */
         hub_2_0: hub@1 {
-          compatible = "usb451,8142";
-          reg = <1>;
-          peer-hub = <&hub_3_0>;
-          reset-gpios = <&gpio1 11 GPIO_ACTIVE_LOW>;
+            compatible = "usb451,8142";
+            reg = <1>;
+            peer-hub = <&hub_3_0>;
+            reset-gpios = <&gpio1 11 GPIO_ACTIVE_LOW>;
         };
 
         /* 3.0 hub on port 2 */
         hub_3_0: hub@2 {
-          compatible = "usb451,8140";
-          reg = <2>;
-          peer-hub = <&hub_2_0>;
-          reset-gpios = <&gpio1 11 GPIO_ACTIVE_LOW>;
+            compatible = "usb451,8140";
+            reg = <2>;
+            peer-hub = <&hub_2_0>;
+            reset-gpios = <&gpio1 11 GPIO_ACTIVE_LOW>;
         };
     };
diff --git a/dts/upstream/Bindings/vendor-prefixes.yaml b/dts/upstream/Bindings/vendor-prefixes.yaml
index da01616802c..5079ca6ce1d 100644
--- a/dts/upstream/Bindings/vendor-prefixes.yaml
+++ b/dts/upstream/Bindings/vendor-prefixes.yaml
@@ -218,6 +218,8 @@ patternProperties:
     description: Shenzhen BigTree Tech Co., LTD
   "^bitmain,.*":
     description: Bitmain Technologies
+  "^blaize,.*":
+    description: Blaize, Inc.
   "^blutek,.*":
     description: BluTek Power
   "^boe,.*":
@@ -575,6 +577,8 @@ patternProperties:
     description: Gemtek Technology Co., Ltd.
   "^genesys,.*":
     description: Genesys Logic, Inc.
+  "^genexis,.*":
+    description: Genexis BV/AB
   "^geniatech,.*":
     description: Geniatech, Inc.
   "^giantec,.*":
@@ -1204,6 +1208,8 @@ patternProperties:
     description: PulsedLight, Inc
   "^purism,.*":
     description: Purism, SPC
+  "^puya,.*":
+    description: Puya Semiconductor (Shanghai) Co., Ltd.
   "^qca,.*":
     description: Qualcomm Atheros, Inc.
   "^qcom,.*":
@@ -1336,6 +1342,8 @@ patternProperties:
     description: Siemens AG
   "^sifive,.*":
     description: SiFive, Inc.
+  "^siflower,.*":
+    description: Shanghai Siflower Communication Co.
   "^sigma,.*":
     description: Sigma Designs, Inc.
   "^sii,.*":
@@ -1524,6 +1532,8 @@ patternProperties:
     description: Topeet
   "^topic,.*":
     description: Topic Embedded Systems
+  "^topland,.*":
+    description: Topland Electronics (H.K) Co., Ltd.
   "^toppoly,.*":
     description: TPO (deprecated, use tpo)
     deprecated: true
diff --git a/dts/upstream/Bindings/w1/maxim,ds2482.yaml b/dts/upstream/Bindings/w1/maxim,ds2482.yaml
index 422becc6e1f..fe6b3f9a3f8 100644
--- a/dts/upstream/Bindings/w1/maxim,ds2482.yaml
+++ b/dts/upstream/Bindings/w1/maxim,ds2482.yaml
@@ -25,6 +25,8 @@ properties:
   reg:
     maxItems: 1
 
+  vcc-supply: true
+
 required:
   - compatible
   - reg
diff --git a/dts/upstream/Bindings/watchdog/qcom-wdt.yaml b/dts/upstream/Bindings/watchdog/qcom-wdt.yaml
index 34896a39fa9..49e2b807db0 100644
--- a/dts/upstream/Bindings/watchdog/qcom-wdt.yaml
+++ b/dts/upstream/Bindings/watchdog/qcom-wdt.yaml
@@ -20,6 +20,7 @@ properties:
               - qcom,kpss-wdt-ipq4019
               - qcom,apss-wdt-ipq5018
               - qcom,apss-wdt-ipq5332
+              - qcom,apss-wdt-ipq5424
               - qcom,apss-wdt-ipq9574
               - qcom,apss-wdt-msm8226
               - qcom,apss-wdt-msm8974
diff --git a/dts/upstream/include/dt-bindings/arm/qcom,ids.h b/dts/upstream/include/dt-bindings/arm/qcom,ids.h
index e850dc3a1ad..1b3e0176dcb 100644
--- a/dts/upstream/include/dt-bindings/arm/qcom,ids.h
+++ b/dts/upstream/include/dt-bindings/arm/qcom,ids.h
@@ -284,6 +284,7 @@
 #define QCOM_ID_QCS9100			667
 #define QCOM_ID_QCS8300			674
 #define QCOM_ID_QCS8275			675
+#define QCOM_ID_QCS9075			676
 #define QCOM_ID_QCS615			680
 
 /*
diff --git a/dts/upstream/include/dt-bindings/clock/at91.h b/dts/upstream/include/dt-bindings/clock/at91.h
index 6ede88c3992..f2a7b7d39c0 100644
--- a/dts/upstream/include/dt-bindings/clock/at91.h
+++ b/dts/upstream/include/dt-bindings/clock/at91.h
@@ -42,6 +42,10 @@
 #define PMC_PLLADIV2		(PMC_MAIN + 11)
 #define PMC_LVDSPLL		(PMC_MAIN + 12)
 
+/* SAMA7D65 */
+#define PMC_MCK3		(PMC_MAIN + 13)
+#define PMC_MCK5		(PMC_MAIN + 14)
+
 #ifndef AT91_PMC_MOSCS
 #define AT91_PMC_MOSCS		0		/* MOSCS Flag */
 #define AT91_PMC_LOCKA		1		/* PLLA Lock */
@@ -55,4 +59,8 @@
 #define AT91_PMC_GCKRDY		24		/* Generated Clocks */
 #endif
 
+/* Slow clock. */
+#define SCKC_MD_SLCK		0
+#define SCKC_TD_SLCK		1
+
 #endif
diff --git a/dts/upstream/include/dt-bindings/clock/en7523-clk.h b/dts/upstream/include/dt-bindings/clock/en7523-clk.h
index 717d23a5e5a..edfa64045f5 100644
--- a/dts/upstream/include/dt-bindings/clock/en7523-clk.h
+++ b/dts/upstream/include/dt-bindings/clock/en7523-clk.h
@@ -12,6 +12,6 @@
 #define EN7523_CLK_CRYPTO	6
 #define EN7523_CLK_PCIE		7
 
-#define EN7523_NUM_CLOCKS	8
+#define EN7581_CLK_EMMC		8
 
 #endif /* _DT_BINDINGS_CLOCK_AIROHA_EN7523_H_ */
diff --git a/dts/upstream/include/dt-bindings/clock/imx93-clock.h b/dts/upstream/include/dt-bindings/clock/imx93-clock.h
index 6c685067288..c393fad3a34 100644
--- a/dts/upstream/include/dt-bindings/clock/imx93-clock.h
+++ b/dts/upstream/include/dt-bindings/clock/imx93-clock.h
@@ -209,5 +209,6 @@
 #define IMX91_CLK_ENET2_REGULAR     204
 #define IMX91_CLK_ENET2_REGULAR_GATE		205
 #define IMX91_CLK_ENET1_QOS_TSN_GATE		206
+#define IMX93_CLK_SPDIF_IPG		207
 
 #endif
diff --git a/dts/upstream/include/dt-bindings/clock/qcom,ipq-cmn-pll.h b/dts/upstream/include/dt-bindings/clock/qcom,ipq-cmn-pll.h
new file mode 100644
index 00000000000..936e92b3b62
--- /dev/null
+++ b/dts/upstream/include/dt-bindings/clock/qcom,ipq-cmn-pll.h
@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_CLK_QCOM_IPQ_CMN_PLL_H
+#define _DT_BINDINGS_CLK_QCOM_IPQ_CMN_PLL_H
+
+/* CMN PLL core clock. */
+#define CMN_PLL_CLK			0
+
+/* The output clocks from CMN PLL of IPQ9574. */
+#define XO_24MHZ_CLK			1
+#define SLEEP_32KHZ_CLK			2
+#define PCS_31P25MHZ_CLK		3
+#define NSS_1200MHZ_CLK			4
+#define PPE_353MHZ_CLK			5
+#define ETH0_50MHZ_CLK			6
+#define ETH1_50MHZ_CLK			7
+#define ETH2_50MHZ_CLK			8
+#define ETH_25MHZ_CLK			9
+#endif
diff --git a/dts/upstream/include/dt-bindings/clock/qcom,ipq5424-gcc.h b/dts/upstream/include/dt-bindings/clock/qcom,ipq5424-gcc.h
index 755ce7a71c7..c15ad16923b 100644
--- a/dts/upstream/include/dt-bindings/clock/qcom,ipq5424-gcc.h
+++ b/dts/upstream/include/dt-bindings/clock/qcom,ipq5424-gcc.h
@@ -12,7 +12,6 @@
 #define GPLL2					2
 #define GPLL2_OUT_MAIN                          3
 #define GCC_SLEEP_CLK_SRC			4
-#define GCC_APSS_DBG_CLK                        5
 #define GCC_USB0_EUD_AT_CLK			6
 #define GCC_PCIE0_AXI_M_CLK_SRC			7
 #define GCC_PCIE0_AXI_M_CLK			8
@@ -152,5 +151,6 @@
 #define GCC_PCIE3_RCHNG_CLK_SRC			142
 #define GCC_PCIE3_RCHNG_CLK			143
 #define GCC_IM_SLEEP_CLK			144
+#define GCC_XO_CLK				145
 
 #endif
diff --git a/dts/upstream/include/dt-bindings/clock/qcom,mmcc-msm8960.h b/dts/upstream/include/dt-bindings/clock/qcom,mmcc-msm8960.h
index 81714fc859c..717431d735c 100644
--- a/dts/upstream/include/dt-bindings/clock/qcom,mmcc-msm8960.h
+++ b/dts/upstream/include/dt-bindings/clock/qcom,mmcc-msm8960.h
@@ -133,5 +133,7 @@
 #define VCAP_CLK					124
 #define VCAP_NPL_CLK					125
 #define PLL15						126
+#define DSI2_PIXEL_LVDS_SRC				127
+#define LVDS_CLK					128
 
 #endif
diff --git a/dts/upstream/include/dt-bindings/clock/qcom,qcs615-gcc.h b/dts/upstream/include/dt-bindings/clock/qcom,qcs615-gcc.h
new file mode 100644
index 00000000000..9704091636b
--- /dev/null
+++ b/dts/upstream/include/dt-bindings/clock/qcom,qcs615-gcc.h
@@ -0,0 +1,211 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_CLK_QCOM_GCC_QCS615_H
+#define _DT_BINDINGS_CLK_QCOM_GCC_QCS615_H
+
+/* GCC clocks */
+#define GPLL0_OUT_AUX2_DIV					0
+#define GPLL3_OUT_AUX2_DIV					1
+#define GPLL0							2
+#define GPLL3							3
+#define GPLL4							4
+#define GPLL6							5
+#define GPLL6_OUT_MAIN						6
+#define GPLL7							7
+#define GPLL8							8
+#define GPLL8_OUT_MAIN						9
+#define GCC_AGGRE_UFS_PHY_AXI_CLK				10
+#define GCC_AGGRE_USB2_SEC_AXI_CLK				11
+#define GCC_AGGRE_USB3_PRIM_AXI_CLK				12
+#define GCC_AHB2PHY_EAST_CLK					13
+#define GCC_AHB2PHY_WEST_CLK					14
+#define GCC_BOOT_ROM_AHB_CLK					15
+#define GCC_CAMERA_AHB_CLK					16
+#define GCC_CAMERA_HF_AXI_CLK					17
+#define GCC_CAMERA_XO_CLK					18
+#define GCC_CE1_AHB_CLK						19
+#define GCC_CE1_AXI_CLK						20
+#define GCC_CE1_CLK						21
+#define GCC_CFG_NOC_USB2_SEC_AXI_CLK				22
+#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK				23
+#define GCC_CPUSS_AHB_CLK					24
+#define GCC_CPUSS_AHB_CLK_SRC					25
+#define GCC_CPUSS_GNOC_CLK					26
+#define GCC_DDRSS_GPU_AXI_CLK					27
+#define GCC_DISP_AHB_CLK					28
+#define GCC_DISP_GPLL0_DIV_CLK_SRC				29
+#define GCC_DISP_HF_AXI_CLK					30
+#define GCC_DISP_XO_CLK						31
+#define GCC_EMAC_AXI_CLK					32
+#define GCC_EMAC_PTP_CLK					33
+#define GCC_EMAC_PTP_CLK_SRC					34
+#define GCC_EMAC_RGMII_CLK					35
+#define GCC_EMAC_RGMII_CLK_SRC					36
+#define GCC_EMAC_SLV_AHB_CLK					37
+#define GCC_GP1_CLK						38
+#define GCC_GP1_CLK_SRC						39
+#define GCC_GP2_CLK						40
+#define GCC_GP2_CLK_SRC						41
+#define GCC_GP3_CLK						42
+#define GCC_GP3_CLK_SRC						43
+#define GCC_GPU_CFG_AHB_CLK					44
+#define GCC_GPU_GPLL0_CLK_SRC					45
+#define GCC_GPU_GPLL0_DIV_CLK_SRC				46
+#define GCC_GPU_IREF_CLK					47
+#define GCC_GPU_MEMNOC_GFX_CLK					48
+#define GCC_GPU_SNOC_DVM_GFX_CLK				49
+#define GCC_PCIE0_PHY_REFGEN_CLK				50
+#define GCC_PCIE_0_AUX_CLK					51
+#define GCC_PCIE_0_AUX_CLK_SRC					52
+#define GCC_PCIE_0_CFG_AHB_CLK					53
+#define GCC_PCIE_0_CLKREF_CLK					54
+#define GCC_PCIE_0_MSTR_AXI_CLK					55
+#define GCC_PCIE_0_PIPE_CLK					56
+#define GCC_PCIE_0_SLV_AXI_CLK					57
+#define GCC_PCIE_0_SLV_Q2A_AXI_CLK				58
+#define GCC_PCIE_PHY_AUX_CLK					59
+#define GCC_PCIE_PHY_REFGEN_CLK_SRC				60
+#define GCC_PDM2_CLK						61
+#define GCC_PDM2_CLK_SRC					62
+#define GCC_PDM_AHB_CLK						63
+#define GCC_PDM_XO4_CLK						64
+#define GCC_PRNG_AHB_CLK					65
+#define GCC_QMIP_CAMERA_NRT_AHB_CLK				66
+#define GCC_QMIP_DISP_AHB_CLK					67
+#define GCC_QMIP_PCIE_AHB_CLK					68
+#define GCC_QMIP_VIDEO_VCODEC_AHB_CLK				69
+#define GCC_QSPI_CNOC_PERIPH_AHB_CLK				70
+#define GCC_QSPI_CORE_CLK					71
+#define GCC_QSPI_CORE_CLK_SRC					72
+#define GCC_QUPV3_WRAP0_CORE_2X_CLK				73
+#define GCC_QUPV3_WRAP0_CORE_CLK				74
+#define GCC_QUPV3_WRAP0_S0_CLK					75
+#define GCC_QUPV3_WRAP0_S0_CLK_SRC				76
+#define GCC_QUPV3_WRAP0_S1_CLK					77
+#define GCC_QUPV3_WRAP0_S1_CLK_SRC				78
+#define GCC_QUPV3_WRAP0_S2_CLK					79
+#define GCC_QUPV3_WRAP0_S2_CLK_SRC				80
+#define GCC_QUPV3_WRAP0_S3_CLK					81
+#define GCC_QUPV3_WRAP0_S3_CLK_SRC				82
+#define GCC_QUPV3_WRAP0_S4_CLK					83
+#define GCC_QUPV3_WRAP0_S4_CLK_SRC				84
+#define GCC_QUPV3_WRAP0_S5_CLK					85
+#define GCC_QUPV3_WRAP0_S5_CLK_SRC				86
+#define GCC_QUPV3_WRAP1_CORE_2X_CLK				87
+#define GCC_QUPV3_WRAP1_CORE_CLK				88
+#define GCC_QUPV3_WRAP1_S0_CLK					89
+#define GCC_QUPV3_WRAP1_S0_CLK_SRC				90
+#define GCC_QUPV3_WRAP1_S1_CLK					91
+#define GCC_QUPV3_WRAP1_S1_CLK_SRC				92
+#define GCC_QUPV3_WRAP1_S2_CLK					93
+#define GCC_QUPV3_WRAP1_S2_CLK_SRC				94
+#define GCC_QUPV3_WRAP1_S3_CLK					95
+#define GCC_QUPV3_WRAP1_S3_CLK_SRC				96
+#define GCC_QUPV3_WRAP1_S4_CLK					97
+#define GCC_QUPV3_WRAP1_S4_CLK_SRC				98
+#define GCC_QUPV3_WRAP1_S5_CLK					99
+#define GCC_QUPV3_WRAP1_S5_CLK_SRC				100
+#define GCC_QUPV3_WRAP_0_M_AHB_CLK				101
+#define GCC_QUPV3_WRAP_0_S_AHB_CLK				102
+#define GCC_QUPV3_WRAP_1_M_AHB_CLK				103
+#define GCC_QUPV3_WRAP_1_S_AHB_CLK				104
+#define GCC_RX1_USB2_CLKREF_CLK					105
+#define GCC_RX3_USB2_CLKREF_CLK					106
+#define GCC_SDCC1_AHB_CLK					107
+#define GCC_SDCC1_APPS_CLK					108
+#define GCC_SDCC1_APPS_CLK_SRC					109
+#define GCC_SDCC1_ICE_CORE_CLK					110
+#define GCC_SDCC1_ICE_CORE_CLK_SRC				111
+#define GCC_SDCC2_AHB_CLK					112
+#define GCC_SDCC2_APPS_CLK					113
+#define GCC_SDCC2_APPS_CLK_SRC					114
+#define GCC_SDR_CORE_CLK					115
+#define GCC_SDR_CSR_HCLK					116
+#define GCC_SDR_PRI_MI2S_CLK					117
+#define GCC_SDR_SEC_MI2S_CLK					118
+#define GCC_SDR_WR0_MEM_CLK					119
+#define GCC_SDR_WR1_MEM_CLK					120
+#define GCC_SDR_WR2_MEM_CLK					121
+#define GCC_SYS_NOC_CPUSS_AHB_CLK				122
+#define GCC_UFS_CARD_CLKREF_CLK					123
+#define GCC_UFS_MEM_CLKREF_CLK					124
+#define GCC_UFS_PHY_AHB_CLK					125
+#define GCC_UFS_PHY_AXI_CLK					126
+#define GCC_UFS_PHY_AXI_CLK_SRC					127
+#define GCC_UFS_PHY_ICE_CORE_CLK				128
+#define GCC_UFS_PHY_ICE_CORE_CLK_SRC				129
+#define GCC_UFS_PHY_PHY_AUX_CLK					130
+#define GCC_UFS_PHY_PHY_AUX_CLK_SRC				131
+#define GCC_UFS_PHY_RX_SYMBOL_0_CLK				132
+#define GCC_UFS_PHY_TX_SYMBOL_0_CLK				133
+#define GCC_UFS_PHY_UNIPRO_CORE_CLK				134
+#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC				135
+#define GCC_USB20_SEC_MASTER_CLK				136
+#define GCC_USB20_SEC_MASTER_CLK_SRC				137
+#define GCC_USB20_SEC_MOCK_UTMI_CLK				138
+#define GCC_USB20_SEC_MOCK_UTMI_CLK_SRC				139
+#define GCC_USB20_SEC_SLEEP_CLK					140
+#define GCC_USB2_PRIM_CLKREF_CLK				141
+#define GCC_USB2_SEC_CLKREF_CLK					142
+#define GCC_USB2_SEC_PHY_AUX_CLK				143
+#define GCC_USB2_SEC_PHY_AUX_CLK_SRC				144
+#define GCC_USB2_SEC_PHY_COM_AUX_CLK				145
+#define GCC_USB2_SEC_PHY_PIPE_CLK				146
+#define GCC_USB30_PRIM_MASTER_CLK				147
+#define GCC_USB30_PRIM_MASTER_CLK_SRC				148
+#define GCC_USB30_PRIM_MOCK_UTMI_CLK				149
+#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC			150
+#define GCC_USB30_PRIM_SLEEP_CLK				151
+#define GCC_USB3_PRIM_CLKREF_CLK				152
+#define GCC_USB3_PRIM_PHY_AUX_CLK				153
+#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC				154
+#define GCC_USB3_PRIM_PHY_COM_AUX_CLK				155
+#define GCC_USB3_PRIM_PHY_PIPE_CLK				156
+#define GCC_USB3_SEC_CLKREF_CLK					157
+#define GCC_VIDEO_AHB_CLK					158
+#define GCC_VIDEO_AXI0_CLK					159
+#define GCC_VIDEO_XO_CLK					160
+#define GCC_VSENSOR_CLK_SRC					161
+#define GCC_AGGRE_UFS_PHY_AXI_HW_CTL_CLK			162
+#define GCC_UFS_PHY_AXI_HW_CTL_CLK				163
+#define GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK				164
+#define GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK				165
+#define GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK			166
+
+/* GCC Resets */
+#define GCC_EMAC_BCR                                            0
+#define GCC_QUSB2PHY_PRIM_BCR                                   1
+#define GCC_QUSB2PHY_SEC_BCR                                    2
+#define GCC_USB30_PRIM_BCR                                      3
+#define GCC_USB2_PHY_SEC_BCR                                    4
+#define GCC_USB3_DP_PHY_SEC_BCR                                 5
+#define GCC_USB3PHY_PHY_SEC_BCR                                 6
+#define GCC_PCIE_0_BCR                                          7
+#define GCC_PCIE_0_PHY_BCR                                      8
+#define GCC_PCIE_PHY_BCR                                        9
+#define GCC_PCIE_PHY_COM_BCR                                    10
+#define GCC_UFS_PHY_BCR                                         11
+#define GCC_USB20_SEC_BCR                                       12
+#define GCC_USB3_PHY_PRIM_SP0_BCR                               13
+#define GCC_USB3PHY_PHY_PRIM_SP0_BCR                            14
+#define GCC_SDCC1_BCR                                           15
+#define GCC_SDCC2_BCR                                           16
+
+/* GCC power domains */
+#define EMAC_GDSC						0
+#define PCIE_0_GDSC						1
+#define UFS_PHY_GDSC						2
+#define USB20_SEC_GDSC						3
+#define USB30_PRIM_GDSC						4
+#define HLOS1_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDSC			5
+#define HLOS1_VOTE_AGGRE_NOC_MMU_TBU1_GDSC			6
+#define HLOS1_VOTE_AGGRE_NOC_MMU_TBU2_GDSC			7
+#define HLOS1_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDSC			8
+#define HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC			9
+#define HLOS1_VOTE_MMNOC_MMU_TBU_SF_GDSC			10
+#define HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDSC			11
+
+#endif
diff --git a/dts/upstream/include/dt-bindings/clock/qcom,qcs8300-camcc.h b/dts/upstream/include/dt-bindings/clock/qcom,qcs8300-camcc.h
new file mode 100644
index 00000000000..fc535c84785
--- /dev/null
+++ b/dts/upstream/include/dt-bindings/clock/qcom,qcs8300-camcc.h
@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_CLK_QCOM_QCS8300_CAM_CC_H
+#define _DT_BINDINGS_CLK_QCOM_QCS8300_CAM_CC_H
+
+#include "qcom,sa8775p-camcc.h"
+
+/* QCS8300 introduces below new clocks compared to SA8775P */
+
+/* CAM_CC clocks */
+#define CAM_CC_TITAN_TOP_ACCU_SHIFT_CLK				86
+
+#endif
diff --git a/dts/upstream/include/dt-bindings/clock/qcom,qcs8300-gpucc.h b/dts/upstream/include/dt-bindings/clock/qcom,qcs8300-gpucc.h
new file mode 100644
index 00000000000..afa187467b4
--- /dev/null
+++ b/dts/upstream/include/dt-bindings/clock/qcom,qcs8300-gpucc.h
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_CLK_QCOM_GPUCC_QCS8300_H
+#define _DT_BINDINGS_CLK_QCOM_GPUCC_QCS8300_H
+
+#include "qcom,sa8775p-gpucc.h"
+
+/* QCS8300 introduces below new clocks compared to SA8775P */
+
+/* GPU_CC clocks */
+#define GPU_CC_CX_ACCU_SHIFT_CLK		23
+#define GPU_CC_GX_ACCU_SHIFT_CLK		24
+
+#endif
diff --git a/dts/upstream/include/dt-bindings/clock/qcom,sm6115-lpasscc.h b/dts/upstream/include/dt-bindings/clock/qcom,sm6115-lpasscc.h
new file mode 100644
index 00000000000..799274517c9
--- /dev/null
+++ b/dts/upstream/include/dt-bindings/clock/qcom,sm6115-lpasscc.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2023, Linaro Ltd.
+ */
+
+#ifndef _DT_BINDINGS_CLK_QCOM_LPASSCC_SM6115_H
+#define _DT_BINDINGS_CLK_QCOM_LPASSCC_SM6115_H
+
+/* LPASS CC */
+#define LPASS_SWR_TX_CONFIG_CGCR		0
+
+/* LPASS_AUDIO CC */
+#define LPASS_AUDIO_SWR_RX_CGCR			0
+
+#endif
diff --git a/dts/upstream/include/dt-bindings/clock/qcom,sm8750-dispcc.h b/dts/upstream/include/dt-bindings/clock/qcom,sm8750-dispcc.h
new file mode 100644
index 00000000000..dafb5069c96
--- /dev/null
+++ b/dts/upstream/include/dt-bindings/clock/qcom,sm8750-dispcc.h
@@ -0,0 +1,112 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2022, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2024, Linaro Ltd.
+ */
+
+#ifndef _DT_BINDINGS_CLK_QCOM_SM8750_DISP_CC_H
+#define _DT_BINDINGS_CLK_QCOM_SM8750_DISP_CC_H
+
+/* DISP_CC clocks */
+#define DISP_CC_ESYNC0_CLK					0
+#define DISP_CC_ESYNC0_CLK_SRC					1
+#define DISP_CC_ESYNC1_CLK					2
+#define DISP_CC_ESYNC1_CLK_SRC					3
+#define DISP_CC_MDSS_ACCU_SHIFT_CLK				4
+#define DISP_CC_MDSS_AHB1_CLK					5
+#define DISP_CC_MDSS_AHB_CLK					6
+#define DISP_CC_MDSS_AHB_CLK_SRC				7
+#define DISP_CC_MDSS_BYTE0_CLK					8
+#define DISP_CC_MDSS_BYTE0_CLK_SRC				9
+#define DISP_CC_MDSS_BYTE0_DIV_CLK_SRC				10
+#define DISP_CC_MDSS_BYTE0_INTF_CLK				11
+#define DISP_CC_MDSS_BYTE1_CLK					12
+#define DISP_CC_MDSS_BYTE1_CLK_SRC				13
+#define DISP_CC_MDSS_BYTE1_DIV_CLK_SRC				14
+#define DISP_CC_MDSS_BYTE1_INTF_CLK				15
+#define DISP_CC_MDSS_DPTX0_AUX_CLK				16
+#define DISP_CC_MDSS_DPTX0_AUX_CLK_SRC				17
+#define DISP_CC_MDSS_DPTX0_CRYPTO_CLK				18
+#define DISP_CC_MDSS_DPTX0_LINK_CLK				19
+#define DISP_CC_MDSS_DPTX0_LINK_CLK_SRC				20
+#define DISP_CC_MDSS_DPTX0_LINK_DIV_CLK_SRC			21
+#define DISP_CC_MDSS_DPTX0_LINK_INTF_CLK			22
+#define DISP_CC_MDSS_DPTX0_PIXEL0_CLK				23
+#define DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC			24
+#define DISP_CC_MDSS_DPTX0_PIXEL1_CLK				25
+#define DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC			26
+#define DISP_CC_MDSS_DPTX0_USB_ROUTER_LINK_INTF_CLK		27
+#define DISP_CC_MDSS_DPTX1_AUX_CLK				28
+#define DISP_CC_MDSS_DPTX1_AUX_CLK_SRC				29
+#define DISP_CC_MDSS_DPTX1_CRYPTO_CLK				30
+#define DISP_CC_MDSS_DPTX1_LINK_CLK				31
+#define DISP_CC_MDSS_DPTX1_LINK_CLK_SRC				32
+#define DISP_CC_MDSS_DPTX1_LINK_DIV_CLK_SRC			33
+#define DISP_CC_MDSS_DPTX1_LINK_INTF_CLK			34
+#define DISP_CC_MDSS_DPTX1_PIXEL0_CLK				35
+#define DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC			36
+#define DISP_CC_MDSS_DPTX1_PIXEL1_CLK				37
+#define DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC			38
+#define DISP_CC_MDSS_DPTX1_USB_ROUTER_LINK_INTF_CLK		39
+#define DISP_CC_MDSS_DPTX2_AUX_CLK				40
+#define DISP_CC_MDSS_DPTX2_AUX_CLK_SRC				41
+#define DISP_CC_MDSS_DPTX2_CRYPTO_CLK				42
+#define DISP_CC_MDSS_DPTX2_LINK_CLK				43
+#define DISP_CC_MDSS_DPTX2_LINK_CLK_SRC				44
+#define DISP_CC_MDSS_DPTX2_LINK_DIV_CLK_SRC			45
+#define DISP_CC_MDSS_DPTX2_LINK_INTF_CLK			46
+#define DISP_CC_MDSS_DPTX2_PIXEL0_CLK				47
+#define DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC			48
+#define DISP_CC_MDSS_DPTX2_PIXEL1_CLK				49
+#define DISP_CC_MDSS_DPTX2_PIXEL1_CLK_SRC			50
+#define DISP_CC_MDSS_DPTX3_AUX_CLK				51
+#define DISP_CC_MDSS_DPTX3_AUX_CLK_SRC				52
+#define DISP_CC_MDSS_DPTX3_CRYPTO_CLK				53
+#define DISP_CC_MDSS_DPTX3_LINK_CLK				54
+#define DISP_CC_MDSS_DPTX3_LINK_CLK_SRC				55
+#define DISP_CC_MDSS_DPTX3_LINK_DIV_CLK_SRC			56
+#define DISP_CC_MDSS_DPTX3_LINK_INTF_CLK			57
+#define DISP_CC_MDSS_DPTX3_PIXEL0_CLK				58
+#define DISP_CC_MDSS_DPTX3_PIXEL0_CLK_SRC			59
+#define DISP_CC_MDSS_ESC0_CLK					60
+#define DISP_CC_MDSS_ESC0_CLK_SRC				61
+#define DISP_CC_MDSS_ESC1_CLK					62
+#define DISP_CC_MDSS_ESC1_CLK_SRC				63
+#define DISP_CC_MDSS_MDP1_CLK					64
+#define DISP_CC_MDSS_MDP_CLK					65
+#define DISP_CC_MDSS_MDP_CLK_SRC				66
+#define DISP_CC_MDSS_MDP_LUT1_CLK				67
+#define DISP_CC_MDSS_MDP_LUT_CLK				68
+#define DISP_CC_MDSS_NON_GDSC_AHB_CLK				69
+#define DISP_CC_MDSS_PCLK0_CLK					70
+#define DISP_CC_MDSS_PCLK0_CLK_SRC				71
+#define DISP_CC_MDSS_PCLK1_CLK					72
+#define DISP_CC_MDSS_PCLK1_CLK_SRC				73
+#define DISP_CC_MDSS_PCLK2_CLK					74
+#define DISP_CC_MDSS_PCLK2_CLK_SRC				75
+#define DISP_CC_MDSS_RSCC_AHB_CLK				76
+#define DISP_CC_MDSS_RSCC_VSYNC_CLK				77
+#define DISP_CC_MDSS_VSYNC1_CLK					78
+#define DISP_CC_MDSS_VSYNC_CLK					79
+#define DISP_CC_MDSS_VSYNC_CLK_SRC				80
+#define DISP_CC_OSC_CLK						81
+#define DISP_CC_OSC_CLK_SRC					82
+#define DISP_CC_PLL0						83
+#define DISP_CC_PLL1						84
+#define DISP_CC_PLL2						85
+#define DISP_CC_SLEEP_CLK					86
+#define DISP_CC_SLEEP_CLK_SRC					87
+#define DISP_CC_XO_CLK						88
+#define DISP_CC_XO_CLK_SRC					89
+
+/* DISP_CC resets */
+#define DISP_CC_MDSS_CORE_BCR					0
+#define DISP_CC_MDSS_CORE_INT2_BCR				1
+#define DISP_CC_MDSS_RSCC_BCR					2
+
+/* DISP_CC GDSCR */
+#define MDSS_GDSC						0
+#define MDSS_INT2_GDSC						1
+
+#endif
diff --git a/dts/upstream/include/dt-bindings/clock/qcom,sm8750-gcc.h b/dts/upstream/include/dt-bindings/clock/qcom,sm8750-gcc.h
new file mode 100644
index 00000000000..e234595d7f4
--- /dev/null
+++ b/dts/upstream/include/dt-bindings/clock/qcom,sm8750-gcc.h
@@ -0,0 +1,226 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_CLK_QCOM_GCC_SM8750_H
+#define _DT_BINDINGS_CLK_QCOM_GCC_SM8750_H
+
+/* GCC clocks */
+#define GCC_AGGRE_NOC_PCIE_AXI_CLK				0
+#define GCC_AGGRE_UFS_PHY_AXI_CLK				1
+#define GCC_AGGRE_UFS_PHY_AXI_HW_CTL_CLK			2
+#define GCC_AGGRE_USB3_PRIM_AXI_CLK				3
+#define GCC_BOOT_ROM_AHB_CLK					4
+#define GCC_CAM_BIST_MCLK_AHB_CLK				5
+#define GCC_CAMERA_AHB_CLK					6
+#define GCC_CAMERA_HF_AXI_CLK					7
+#define GCC_CAMERA_SF_AXI_CLK					8
+#define GCC_CAMERA_XO_CLK					9
+#define GCC_CFG_NOC_PCIE_ANOC_AHB_CLK				10
+#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK				11
+#define GCC_CNOC_PCIE_SF_AXI_CLK				12
+#define GCC_DDRSS_GPU_AXI_CLK					13
+#define GCC_DDRSS_PCIE_SF_QTB_CLK				14
+#define GCC_DISP_AHB_CLK					15
+#define GCC_DISP_HF_AXI_CLK					16
+#define GCC_EVA_AHB_CLK						17
+#define GCC_EVA_AXI0_CLK					18
+#define GCC_EVA_AXI0C_CLK					19
+#define GCC_EVA_XO_CLK						20
+#define GCC_GP1_CLK						21
+#define GCC_GP1_CLK_SRC						22
+#define GCC_GP2_CLK						23
+#define GCC_GP2_CLK_SRC						24
+#define GCC_GP3_CLK						25
+#define GCC_GP3_CLK_SRC						26
+#define GCC_GPLL0						27
+#define GCC_GPLL0_OUT_EVEN					28
+#define GCC_GPLL1						29
+#define GCC_GPLL4						30
+#define GCC_GPLL7						31
+#define GCC_GPLL9						32
+#define GCC_GPU_CFG_AHB_CLK					33
+#define GCC_GPU_GEMNOC_GFX_CLK					34
+#define GCC_GPU_GPLL0_CLK_SRC					35
+#define GCC_GPU_GPLL0_DIV_CLK_SRC				36
+#define GCC_PCIE_0_AUX_CLK					37
+#define GCC_PCIE_0_AUX_CLK_SRC					38
+#define GCC_PCIE_0_CFG_AHB_CLK					39
+#define GCC_PCIE_0_MSTR_AXI_CLK					40
+#define GCC_PCIE_0_PHY_RCHNG_CLK				41
+#define GCC_PCIE_0_PHY_RCHNG_CLK_SRC				42
+#define GCC_PCIE_0_PIPE_CLK					43
+#define GCC_PCIE_0_PIPE_CLK_SRC					44
+#define GCC_PCIE_0_SLV_AXI_CLK					45
+#define GCC_PCIE_0_SLV_Q2A_AXI_CLK				46
+#define GCC_PCIE_RSCC_CFG_AHB_CLK				47
+#define GCC_PCIE_RSCC_XO_CLK					48
+#define GCC_PDM2_CLK						49
+#define GCC_PDM2_CLK_SRC					50
+#define GCC_PDM_AHB_CLK						51
+#define GCC_PDM_XO4_CLK						52
+#define GCC_QMIP_CAMERA_CMD_AHB_CLK				53
+#define GCC_QMIP_CAMERA_NRT_AHB_CLK				54
+#define GCC_QMIP_CAMERA_RT_AHB_CLK				55
+#define GCC_QMIP_GPU_AHB_CLK					56
+#define GCC_QMIP_PCIE_AHB_CLK					57
+#define GCC_QMIP_VIDEO_CV_CPU_AHB_CLK				58
+#define GCC_QMIP_VIDEO_CVP_AHB_CLK				59
+#define GCC_QMIP_VIDEO_V_CPU_AHB_CLK				60
+#define GCC_QMIP_VIDEO_VCODEC_AHB_CLK				61
+#define GCC_QUPV3_I2C_CORE_CLK					62
+#define GCC_QUPV3_I2C_S0_CLK					63
+#define GCC_QUPV3_I2C_S0_CLK_SRC				64
+#define GCC_QUPV3_I2C_S1_CLK					65
+#define GCC_QUPV3_I2C_S1_CLK_SRC				66
+#define GCC_QUPV3_I2C_S2_CLK					67
+#define GCC_QUPV3_I2C_S2_CLK_SRC				68
+#define GCC_QUPV3_I2C_S3_CLK					69
+#define GCC_QUPV3_I2C_S3_CLK_SRC				70
+#define GCC_QUPV3_I2C_S4_CLK					71
+#define GCC_QUPV3_I2C_S4_CLK_SRC				72
+#define GCC_QUPV3_I2C_S5_CLK					73
+#define GCC_QUPV3_I2C_S5_CLK_SRC				74
+#define GCC_QUPV3_I2C_S6_CLK					75
+#define GCC_QUPV3_I2C_S6_CLK_SRC				76
+#define GCC_QUPV3_I2C_S7_CLK					77
+#define GCC_QUPV3_I2C_S7_CLK_SRC				78
+#define GCC_QUPV3_I2C_S8_CLK					79
+#define GCC_QUPV3_I2C_S8_CLK_SRC				80
+#define GCC_QUPV3_I2C_S9_CLK					81
+#define GCC_QUPV3_I2C_S9_CLK_SRC				82
+#define GCC_QUPV3_I2C_S_AHB_CLK					83
+#define GCC_QUPV3_WRAP1_CORE_2X_CLK				84
+#define GCC_QUPV3_WRAP1_CORE_CLK				85
+#define GCC_QUPV3_WRAP1_QSPI_REF_CLK				86
+#define GCC_QUPV3_WRAP1_QSPI_REF_CLK_SRC			87
+#define GCC_QUPV3_WRAP1_S0_CLK					88
+#define GCC_QUPV3_WRAP1_S0_CLK_SRC				89
+#define GCC_QUPV3_WRAP1_S1_CLK					90
+#define GCC_QUPV3_WRAP1_S1_CLK_SRC				91
+#define GCC_QUPV3_WRAP1_S2_CLK					92
+#define GCC_QUPV3_WRAP1_S2_CLK_SRC				93
+#define GCC_QUPV3_WRAP1_S3_CLK					94
+#define GCC_QUPV3_WRAP1_S3_CLK_SRC				95
+#define GCC_QUPV3_WRAP1_S4_CLK					96
+#define GCC_QUPV3_WRAP1_S4_CLK_SRC				97
+#define GCC_QUPV3_WRAP1_S5_CLK					98
+#define GCC_QUPV3_WRAP1_S5_CLK_SRC				99
+#define GCC_QUPV3_WRAP1_S6_CLK					100
+#define GCC_QUPV3_WRAP1_S6_CLK_SRC				101
+#define GCC_QUPV3_WRAP1_S7_CLK					102
+#define GCC_QUPV3_WRAP1_S7_CLK_SRC				103
+#define GCC_QUPV3_WRAP2_CORE_2X_CLK				104
+#define GCC_QUPV3_WRAP2_CORE_CLK				105
+#define GCC_QUPV3_WRAP2_IBI_CTRL_0_CLK_SRC			106
+#define GCC_QUPV3_WRAP2_IBI_CTRL_2_CLK				107
+#define GCC_QUPV3_WRAP2_IBI_CTRL_3_CLK				108
+#define GCC_QUPV3_WRAP2_S0_CLK					109
+#define GCC_QUPV3_WRAP2_S0_CLK_SRC				110
+#define GCC_QUPV3_WRAP2_S1_CLK					111
+#define GCC_QUPV3_WRAP2_S1_CLK_SRC				112
+#define GCC_QUPV3_WRAP2_S2_CLK					113
+#define GCC_QUPV3_WRAP2_S2_CLK_SRC				114
+#define GCC_QUPV3_WRAP2_S3_CLK					115
+#define GCC_QUPV3_WRAP2_S3_CLK_SRC				116
+#define GCC_QUPV3_WRAP2_S4_CLK					117
+#define GCC_QUPV3_WRAP2_S4_CLK_SRC				118
+#define GCC_QUPV3_WRAP2_S5_CLK					119
+#define GCC_QUPV3_WRAP2_S5_CLK_SRC				120
+#define GCC_QUPV3_WRAP2_S6_CLK					121
+#define GCC_QUPV3_WRAP2_S6_CLK_SRC				122
+#define GCC_QUPV3_WRAP2_S7_CLK					123
+#define GCC_QUPV3_WRAP2_S7_CLK_SRC				124
+#define GCC_QUPV3_WRAP_1_M_AHB_CLK				125
+#define GCC_QUPV3_WRAP_1_S_AHB_CLK				126
+#define GCC_QUPV3_WRAP_2_IBI_2_AHB_CLK				127
+#define GCC_QUPV3_WRAP_2_IBI_3_AHB_CLK				128
+#define GCC_QUPV3_WRAP_2_M_AHB_CLK				129
+#define GCC_QUPV3_WRAP_2_S_AHB_CLK				130
+#define GCC_SDCC2_AHB_CLK					131
+#define GCC_SDCC2_APPS_CLK					132
+#define GCC_SDCC2_APPS_CLK_SRC					133
+#define GCC_SDCC4_AHB_CLK					134
+#define GCC_SDCC4_APPS_CLK					135
+#define GCC_SDCC4_APPS_CLK_SRC					136
+#define GCC_UFS_PHY_AHB_CLK					137
+#define GCC_UFS_PHY_AXI_CLK					138
+#define GCC_UFS_PHY_AXI_CLK_SRC					139
+#define GCC_UFS_PHY_AXI_HW_CTL_CLK				140
+#define GCC_UFS_PHY_ICE_CORE_CLK				141
+#define GCC_UFS_PHY_ICE_CORE_CLK_SRC				142
+#define GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK				143
+#define GCC_UFS_PHY_PHY_AUX_CLK					144
+#define GCC_UFS_PHY_PHY_AUX_CLK_SRC				145
+#define GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK				146
+#define GCC_UFS_PHY_RX_SYMBOL_0_CLK				147
+#define GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC				148
+#define GCC_UFS_PHY_RX_SYMBOL_1_CLK				149
+#define GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC				150
+#define GCC_UFS_PHY_TX_SYMBOL_0_CLK				151
+#define GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC				152
+#define GCC_UFS_PHY_UNIPRO_CORE_CLK				153
+#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC				154
+#define GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK			155
+#define GCC_USB30_PRIM_MASTER_CLK				156
+#define GCC_USB30_PRIM_MASTER_CLK_SRC				157
+#define GCC_USB30_PRIM_MOCK_UTMI_CLK				158
+#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC			159
+#define GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC		160
+#define GCC_USB30_PRIM_SLEEP_CLK				161
+#define GCC_USB3_PRIM_PHY_AUX_CLK				162
+#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC				163
+#define GCC_USB3_PRIM_PHY_COM_AUX_CLK				164
+#define GCC_USB3_PRIM_PHY_PIPE_CLK				165
+#define GCC_USB3_PRIM_PHY_PIPE_CLK_SRC				166
+#define GCC_VIDEO_AHB_CLK					167
+#define GCC_VIDEO_AXI0_CLK					168
+#define GCC_VIDEO_AXI1_CLK					169
+#define GCC_VIDEO_XO_CLK					170
+
+/* GCC power domains */
+#define GCC_PCIE_0_GDSC						0
+#define GCC_PCIE_0_PHY_GDSC					1
+#define GCC_UFS_MEM_PHY_GDSC					2
+#define GCC_UFS_PHY_GDSC					3
+#define GCC_USB30_PRIM_GDSC					4
+#define GCC_USB3_PHY_GDSC					5
+
+/* GCC resets */
+#define GCC_CAMERA_BCR						0
+#define GCC_DISPLAY_BCR						1
+#define GCC_EVA_BCR						2
+#define GCC_GPU_BCR						3
+#define GCC_PCIE_0_BCR						4
+#define GCC_PCIE_0_LINK_DOWN_BCR				5
+#define GCC_PCIE_0_NOCSR_COM_PHY_BCR				6
+#define GCC_PCIE_0_PHY_BCR					7
+#define GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR			8
+#define GCC_PCIE_PHY_BCR					9
+#define GCC_PCIE_PHY_CFG_AHB_BCR				10
+#define GCC_PCIE_PHY_COM_BCR					11
+#define GCC_PCIE_RSCC_BCR					12
+#define GCC_PDM_BCR						13
+#define GCC_QUPV3_WRAPPER_1_BCR					14
+#define GCC_QUPV3_WRAPPER_2_BCR					15
+#define GCC_QUPV3_WRAPPER_I2C_BCR				16
+#define GCC_QUSB2PHY_PRIM_BCR					17
+#define GCC_QUSB2PHY_SEC_BCR					18
+#define GCC_SDCC2_BCR						19
+#define GCC_SDCC4_BCR						20
+#define GCC_UFS_PHY_BCR						21
+#define GCC_USB30_PRIM_BCR					22
+#define GCC_USB3_DP_PHY_PRIM_BCR				23
+#define GCC_USB3_DP_PHY_SEC_BCR					24
+#define GCC_USB3_PHY_PRIM_BCR					25
+#define GCC_USB3_PHY_SEC_BCR					26
+#define GCC_USB3PHY_PHY_PRIM_BCR				27
+#define GCC_USB3PHY_PHY_SEC_BCR					28
+#define GCC_VIDEO_AXI0_CLK_ARES					29
+#define GCC_VIDEO_AXI1_CLK_ARES					30
+#define GCC_VIDEO_BCR						31
+#define GCC_EVA_AXI0_CLK_ARES					32
+#define GCC_EVA_AXI0C_CLK_ARES					33
+
+#endif
diff --git a/dts/upstream/include/dt-bindings/clock/qcom,sm8750-tcsr.h b/dts/upstream/include/dt-bindings/clock/qcom,sm8750-tcsr.h
new file mode 100644
index 00000000000..1c502ac7c7f
--- /dev/null
+++ b/dts/upstream/include/dt-bindings/clock/qcom,sm8750-tcsr.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_CLK_QCOM_TCSR_CC_SM8750_H
+#define _DT_BINDINGS_CLK_QCOM_TCSR_CC_SM8750_H
+
+/* TCSR_CC clocks */
+#define TCSR_PCIE_0_CLKREF_EN				0
+#define TCSR_UFS_CLKREF_EN				1
+#define TCSR_USB2_CLKREF_EN				2
+#define TCSR_USB3_CLKREF_EN				3
+
+#endif
diff --git a/dts/upstream/include/dt-bindings/clock/qcom,x1e80100-gpucc.h b/dts/upstream/include/dt-bindings/clock/qcom,x1e80100-gpucc.h
index 61a3a8f3ac4..27b8f50541f 100644
--- a/dts/upstream/include/dt-bindings/clock/qcom,x1e80100-gpucc.h
+++ b/dts/upstream/include/dt-bindings/clock/qcom,x1e80100-gpucc.h
@@ -33,9 +33,22 @@
 #define GPU_CC_SLEEP_CLK					23
 #define GPU_CC_XO_CLK_SRC					24
 #define GPU_CC_XO_DIV_CLK_SRC					25
+#define GPU_CC_CX_ACCU_SHIFT_CLK				26
+#define GPU_CC_GX_ACCU_SHIFT_CLK				27
 
 /* GDSCs */
 #define GPU_CX_GDSC						0
 #define GPU_GX_GDSC						1
 
+/* GPU_CC resets */
+#define GPU_CC_ACD_BCR                                          0
+#define GPU_CC_CB_BCR                                           1
+#define GPU_CC_CX_BCR                                           2
+#define GPU_CC_FAST_HUB_BCR                                     3
+#define GPU_CC_FF_BCR                                           4
+#define GPU_CC_GFX3D_AON_BCR                                    5
+#define GPU_CC_GMU_BCR                                          6
+#define GPU_CC_GX_BCR                                           7
+#define GPU_CC_XO_BCR                                           8
+
 #endif
diff --git a/dts/upstream/include/dt-bindings/clock/renesas,r9a08g045-vbattb.h b/dts/upstream/include/dt-bindings/clock/renesas,r9a08g045-vbattb.h
index 67774eafad0..4cc8fc34b23 100644
--- a/dts/upstream/include/dt-bindings/clock/renesas,r9a08g045-vbattb.h
+++ b/dts/upstream/include/dt-bindings/clock/renesas,r9a08g045-vbattb.h
@@ -2,12 +2,12 @@
  *
  * Copyright (C) 2024 Renesas Electronics Corp.
  */
-#ifndef __DT_BINDINGS_CLOCK_R9A08G045_VBATTB_H__
-#define __DT_BINDINGS_CLOCK_R9A08G045_VBATTB_H__
+#ifndef __DT_BINDINGS_CLOCK_RENESAS_R9A08G045_VBATTB_H__
+#define __DT_BINDINGS_CLOCK_RENESAS_R9A08G045_VBATTB_H__
 
 #define VBATTB_XC		0
 #define VBATTB_XBYP		1
 #define VBATTB_MUX		2
 #define VBATTB_VBATTCLK		3
 
-#endif /* __DT_BINDINGS_CLOCK_R9A08G045_VBATTB_H__ */
+#endif /* __DT_BINDINGS_CLOCK_RENESAS_R9A08G045_VBATTB_H__ */
diff --git a/dts/upstream/include/dt-bindings/clock/renesas,r9a09g047-cpg.h b/dts/upstream/include/dt-bindings/clock/renesas,r9a09g047-cpg.h
new file mode 100644
index 00000000000..1d031bf6bf0
--- /dev/null
+++ b/dts/upstream/include/dt-bindings/clock/renesas,r9a09g047-cpg.h
@@ -0,0 +1,21 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+ *
+ * Copyright (C) 2024 Renesas Electronics Corp.
+ */
+#ifndef __DT_BINDINGS_CLOCK_RENESAS_R9A09G047_CPG_H__
+#define __DT_BINDINGS_CLOCK_RENESAS_R9A09G047_CPG_H__
+
+#include <dt-bindings/clock/renesas-cpg-mssr.h>
+
+/* Core Clock list */
+#define R9A09G047_SYS_0_PCLK			0
+#define R9A09G047_CA55_0_CORECLK0		1
+#define R9A09G047_CA55_0_CORECLK1		2
+#define R9A09G047_CA55_0_CORECLK2		3
+#define R9A09G047_CA55_0_CORECLK3		4
+#define R9A09G047_CA55_0_PERIPHCLK		5
+#define R9A09G047_CM33_CLK0			6
+#define R9A09G047_CST_0_SWCLKTCK		7
+#define R9A09G047_IOTOP_0_SHCLK			8
+
+#endif /* __DT_BINDINGS_CLOCK_RENESAS_R9A09G047_CPG_H__ */
diff --git a/dts/upstream/include/dt-bindings/clock/samsung,exynos990.h b/dts/upstream/include/dt-bindings/clock/samsung,exynos990.h
new file mode 100644
index 00000000000..307215a3f3e
--- /dev/null
+++ b/dts/upstream/include/dt-bindings/clock/samsung,exynos990.h
@@ -0,0 +1,236 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (C) 2024 Igor Belwon <igor.belwon@mentallysanemainliners.org>
+ *
+ * Device Tree binding constants for Exynos990 clock controller.
+ */
+
+#ifndef _DT_BINDINGS_CLOCK_EXYNOS_990_H
+#define _DT_BINDINGS_CLOCK_EXYNOS_990_H
+
+/* CMU_TOP */
+#define CLK_FOUT_SHARED0_PLL		1
+#define CLK_FOUT_SHARED1_PLL		2
+#define CLK_FOUT_SHARED2_PLL		3
+#define CLK_FOUT_SHARED3_PLL		4
+#define CLK_FOUT_SHARED4_PLL		5
+#define CLK_FOUT_G3D_PLL		6
+#define CLK_FOUT_MMC_PLL		7
+#define CLK_MOUT_PLL_SHARED0		8
+#define CLK_MOUT_PLL_SHARED1		9
+#define CLK_MOUT_PLL_SHARED2		10
+#define CLK_MOUT_PLL_SHARED3		11
+#define CLK_MOUT_PLL_SHARED4		12
+#define CLK_MOUT_PLL_MMC		13
+#define CLK_MOUT_PLL_G3D		14
+#define CLK_MOUT_CMU_APM_BUS		15
+#define CLK_MOUT_CMU_AUD_CPU		16
+#define CLK_MOUT_CMU_BUS0_BUS		17
+#define CLK_MOUT_CMU_BUS1_BUS		18
+#define CLK_MOUT_CMU_BUS1_SSS		19
+#define CLK_MOUT_CMU_CIS_CLK0		20
+#define CLK_MOUT_CMU_CIS_CLK1		21
+#define CLK_MOUT_CMU_CIS_CLK2		22
+#define CLK_MOUT_CMU_CIS_CLK3		23
+#define CLK_MOUT_CMU_CIS_CLK4		24
+#define CLK_MOUT_CMU_CIS_CLK5		25
+#define CLK_MOUT_CMU_CMU_BOOST		26
+#define CLK_MOUT_CMU_CORE_BUS		27
+#define CLK_MOUT_CMU_CPUCL0_DBG_BUS	28
+#define CLK_MOUT_CMU_CPUCL0_SWITCH	29
+#define CLK_MOUT_CMU_CPUCL1_SWITCH	30
+#define CLK_MOUT_CMU_CPUCL2_BUSP	31
+#define CLK_MOUT_CMU_CPUCL2_SWITCH	32
+#define CLK_MOUT_CMU_CSIS_BUS		33
+#define CLK_MOUT_CMU_CSIS_OIS_MCU	34
+#define CLK_MOUT_CMU_DNC_BUS		35
+#define CLK_MOUT_CMU_DNC_BUSM		36
+#define CLK_MOUT_CMU_DNS_BUS		37
+#define CLK_MOUT_CMU_DPU		38
+#define CLK_MOUT_CMU_DPU_ALT		39
+#define CLK_MOUT_CMU_DSP_BUS		40
+#define CLK_MOUT_CMU_G2D_G2D		41
+#define CLK_MOUT_CMU_G2D_MSCL		42
+#define CLK_MOUT_CMU_HPM		43
+#define CLK_MOUT_CMU_HSI0_BUS		44
+#define CLK_MOUT_CMU_HSI0_DPGTC		45
+#define CLK_MOUT_CMU_HSI0_USB31DRD	46
+#define CLK_MOUT_CMU_HSI0_USBDP_DEBUG	47
+#define CLK_MOUT_CMU_HSI1_BUS		48
+#define CLK_MOUT_CMU_HSI1_MMC_CARD	49
+#define CLK_MOUT_CMU_HSI1_PCIE		50
+#define CLK_MOUT_CMU_HSI1_UFS_CARD	51
+#define CLK_MOUT_CMU_HSI1_UFS_EMBD	52
+#define CLK_MOUT_CMU_HSI2_BUS		53
+#define CLK_MOUT_CMU_HSI2_PCIE		54
+#define CLK_MOUT_CMU_IPP_BUS		55
+#define CLK_MOUT_CMU_ITP_BUS		56
+#define CLK_MOUT_CMU_MCSC_BUS		57
+#define CLK_MOUT_CMU_MCSC_GDC		58
+#define CLK_MOUT_CMU_CMU_BOOST_CPU	59
+#define CLK_MOUT_CMU_MFC0_MFC0		60
+#define CLK_MOUT_CMU_MFC0_WFD		61
+#define CLK_MOUT_CMU_MIF_BUSP		62
+#define CLK_MOUT_CMU_MIF_SWITCH		63
+#define CLK_MOUT_CMU_NPU_BUS		64
+#define CLK_MOUT_CMU_PERIC0_BUS		65
+#define CLK_MOUT_CMU_PERIC0_IP		66
+#define CLK_MOUT_CMU_PERIC1_BUS		67
+#define CLK_MOUT_CMU_PERIC1_IP		68
+#define CLK_MOUT_CMU_PERIS_BUS		69
+#define CLK_MOUT_CMU_SSP_BUS		70
+#define CLK_MOUT_CMU_TNR_BUS		71
+#define CLK_MOUT_CMU_VRA_BUS		72
+#define CLK_DOUT_CMU_APM_BUS		73
+#define CLK_DOUT_CMU_AUD_CPU		74
+#define CLK_DOUT_CMU_BUS0_BUS		75
+#define CLK_DOUT_CMU_BUS1_BUS		76
+#define CLK_DOUT_CMU_BUS1_SSS		77
+#define CLK_DOUT_CMU_CIS_CLK0		78
+#define CLK_DOUT_CMU_CIS_CLK1		79
+#define CLK_DOUT_CMU_CIS_CLK2		80
+#define CLK_DOUT_CMU_CIS_CLK3		81
+#define CLK_DOUT_CMU_CIS_CLK4		82
+#define CLK_DOUT_CMU_CIS_CLK5		83
+#define CLK_DOUT_CMU_CMU_BOOST		84
+#define CLK_DOUT_CMU_CORE_BUS		85
+#define CLK_DOUT_CMU_CPUCL0_DBG_BUS	86
+#define CLK_DOUT_CMU_CPUCL0_SWITCH	87
+#define CLK_DOUT_CMU_CPUCL1_SWITCH	88
+#define CLK_DOUT_CMU_CPUCL2_BUSP	89
+#define CLK_DOUT_CMU_CPUCL2_SWITCH	90
+#define CLK_DOUT_CMU_CSIS_BUS		91
+#define CLK_DOUT_CMU_CSIS_OIS_MCU	92
+#define CLK_DOUT_CMU_DNC_BUS		93
+#define CLK_DOUT_CMU_DNC_BUSM		94
+#define CLK_DOUT_CMU_DNS_BUS		95
+#define CLK_DOUT_CMU_DSP_BUS		96
+#define CLK_DOUT_CMU_G2D_G2D		97
+#define CLK_DOUT_CMU_G2D_MSCL		98
+#define CLK_DOUT_CMU_G3D_SWITCH		99
+#define CLK_DOUT_CMU_HPM		100
+#define CLK_DOUT_CMU_HSI0_BUS		101
+#define CLK_DOUT_CMU_HSI0_DPGTC		102
+#define CLK_DOUT_CMU_HSI0_USB31DRD	103
+#define CLK_DOUT_CMU_HSI0_USBDP_DEBUG	104
+#define CLK_DOUT_CMU_HSI1_BUS		105
+#define CLK_DOUT_CMU_HSI1_MMC_CARD	106
+#define CLK_DOUT_CMU_HSI1_PCIE		107
+#define CLK_DOUT_CMU_HSI1_UFS_CARD	108
+#define CLK_DOUT_CMU_HSI1_UFS_EMBD	109
+#define CLK_DOUT_CMU_HSI2_BUS		110
+#define CLK_DOUT_CMU_HSI2_PCIE		111
+#define CLK_DOUT_CMU_IPP_BUS		112
+#define CLK_DOUT_CMU_ITP_BUS		113
+#define CLK_DOUT_CMU_MCSC_BUS		114
+#define CLK_DOUT_CMU_MCSC_GDC		115
+#define CLK_DOUT_CMU_CMU_BOOST_CPU	116
+#define CLK_DOUT_CMU_MFC0_MFC0		117
+#define CLK_DOUT_CMU_MFC0_WFD		118
+#define CLK_DOUT_CMU_MIF_BUSP		119
+#define CLK_DOUT_CMU_NPU_BUS		120
+#define CLK_DOUT_CMU_OTP		121
+#define CLK_DOUT_CMU_PERIC0_BUS		122
+#define CLK_DOUT_CMU_PERIC0_IP		123
+#define CLK_DOUT_CMU_PERIC1_BUS		124
+#define CLK_DOUT_CMU_PERIC1_IP		125
+#define CLK_DOUT_CMU_PERIS_BUS		126
+#define CLK_DOUT_CMU_SSP_BUS		127
+#define CLK_DOUT_CMU_TNR_BUS		128
+#define CLK_DOUT_CMU_VRA_BUS		129
+#define CLK_DOUT_CMU_DPU		130
+#define CLK_DOUT_CMU_DPU_ALT		131
+#define CLK_DOUT_CMU_SHARED0_DIV2	132
+#define CLK_DOUT_CMU_SHARED0_DIV3	133
+#define CLK_DOUT_CMU_SHARED0_DIV4	134
+#define CLK_DOUT_CMU_SHARED1_DIV2	135
+#define CLK_DOUT_CMU_SHARED1_DIV3	136
+#define CLK_DOUT_CMU_SHARED1_DIV4	137
+#define CLK_DOUT_CMU_SHARED2_DIV2	138
+#define CLK_DOUT_CMU_SHARED4_DIV2	139
+#define CLK_DOUT_CMU_SHARED4_DIV3	140
+#define CLK_DOUT_CMU_SHARED4_DIV4	141
+#define CLK_GOUT_CMU_G3D_BUS		142
+#define CLK_GOUT_CMU_MIF_SWITCH		143
+#define CLK_GOUT_CMU_APM_BUS		144
+#define CLK_GOUT_CMU_AUD_CPU		145
+#define CLK_GOUT_CMU_BUS0_BUS		146
+#define CLK_GOUT_CMU_BUS1_BUS		147
+#define CLK_GOUT_CMU_BUS1_SSS		148
+#define CLK_GOUT_CMU_CIS_CLK0		149
+#define CLK_GOUT_CMU_CIS_CLK1		150
+#define CLK_GOUT_CMU_CIS_CLK2		151
+#define CLK_GOUT_CMU_CIS_CLK3		152
+#define CLK_GOUT_CMU_CIS_CLK4		153
+#define CLK_GOUT_CMU_CIS_CLK5		154
+#define CLK_GOUT_CMU_CORE_BUS		155
+#define CLK_GOUT_CMU_CPUCL0_DBG_BUS	156
+#define CLK_GOUT_CMU_CPUCL0_SWITCH	157
+#define CLK_GOUT_CMU_CPUCL1_SWITCH	158
+#define CLK_GOUT_CMU_CPUCL2_BUSP	159
+#define CLK_GOUT_CMU_CPUCL2_SWITCH	160
+#define CLK_GOUT_CMU_CSIS_BUS		161
+#define CLK_GOUT_CMU_CSIS_OIS_MCU	162
+#define CLK_GOUT_CMU_DNC_BUS		163
+#define CLK_GOUT_CMU_DNC_BUSM		164
+#define CLK_GOUT_CMU_DNS_BUS		165
+#define CLK_GOUT_CMU_DPU		166
+#define CLK_GOUT_CMU_DPU_BUS		167
+#define CLK_GOUT_CMU_DSP_BUS		168
+#define CLK_GOUT_CMU_G2D_G2D		169
+#define CLK_GOUT_CMU_G2D_MSCL		170
+#define CLK_GOUT_CMU_G3D_SWITCH		171
+#define CLK_GOUT_CMU_HPM		172
+#define CLK_GOUT_CMU_HSI0_BUS		173
+#define CLK_GOUT_CMU_HSI0_DPGTC		174
+#define CLK_GOUT_CMU_HSI0_USB31DRD	175
+#define CLK_GOUT_CMU_HSI0_USBDP_DEBUG	176
+#define CLK_GOUT_CMU_HSI1_BUS		177
+#define CLK_GOUT_CMU_HSI1_MMC_CARD	178
+#define CLK_GOUT_CMU_HSI1_PCIE		179
+#define CLK_GOUT_CMU_HSI1_UFS_CARD	180
+#define CLK_GOUT_CMU_HSI1_UFS_EMBD	181
+#define CLK_GOUT_CMU_HSI2_BUS		182
+#define CLK_GOUT_CMU_HSI2_PCIE		183
+#define CLK_GOUT_CMU_IPP_BUS		184
+#define CLK_GOUT_CMU_ITP_BUS		185
+#define CLK_GOUT_CMU_MCSC_BUS		186
+#define CLK_GOUT_CMU_MCSC_GDC		187
+#define CLK_GOUT_CMU_MFC0_MFC0		188
+#define CLK_GOUT_CMU_MFC0_WFD		189
+#define CLK_GOUT_CMU_MIF_BUSP		190
+#define CLK_GOUT_CMU_NPU_BUS		191
+#define CLK_GOUT_CMU_PERIC0_BUS		192
+#define CLK_GOUT_CMU_PERIC0_IP		193
+#define CLK_GOUT_CMU_PERIC1_BUS		194
+#define CLK_GOUT_CMU_PERIC1_IP		195
+#define CLK_GOUT_CMU_PERIS_BUS		196
+#define CLK_GOUT_CMU_SSP_BUS		197
+#define CLK_GOUT_CMU_TNR_BUS		198
+#define CLK_GOUT_CMU_VRA_BUS		199
+
+/* CMU_HSI0 */
+#define CLK_MOUT_HSI0_BUS_USER				1
+#define CLK_MOUT_HSI0_USB31DRD_USER			2
+#define CLK_MOUT_HSI0_USBDP_DEBUG_USER			3
+#define CLK_MOUT_HSI0_DPGTC_USER			4
+#define CLK_GOUT_HSI0_DP_LINK_DP_GTC_CLK		5
+#define CLK_GOUT_HSI0_DP_LINK_PCLK			6
+#define CLK_GOUT_HSI0_D_TZPC_HSI0_PCLK			7
+#define CLK_GOUT_HSI0_LHM_AXI_P_HSI0_CLK		8
+#define CLK_GOUT_HSI0_PPMU_HSI0_BUS1_ACLK		9
+#define CLK_GOUT_HSI0_PPMU_HSI0_BUS1_PCLK		10
+#define CLK_GOUT_HSI0_CLK_HSI0_BUS_CLK			11
+#define CLK_GOUT_HSI0_SYSMMU_USB_CLK_S2			12
+#define CLK_GOUT_HSI0_SYSREG_HSI0_PCLK			13
+#define CLK_GOUT_HSI0_USB31DRD_ACLK_PHYCTRL		14
+#define CLK_GOUT_HSI0_USB31DRD_BUS_CLK_EARLY		15
+#define CLK_GOUT_HSI0_USB31DRD_USB31DRD_REF_CLK_40	16
+#define CLK_GOUT_HSI0_USB31DRD_USBDPPHY_REF_SOC_PLL	17
+#define CLK_GOUT_HSI0_USB31DRD_USBDPPHY_SCL_APB		18
+#define CLK_GOUT_HSI0_USB31DRD_USBPCS_APB_CLK		19
+#define CLK_GOUT_HSI0_VGEN_LITE_HSI0_CLK		20
+#define CLK_GOUT_HSI0_CMU_HSI0_PCLK			21
+#define CLK_GOUT_HSI0_XIU_D_HSI0_ACLK			22
+
+#endif
diff --git a/dts/upstream/include/dt-bindings/clock/stm32fx-clock.h b/dts/upstream/include/dt-bindings/clock/stm32fx-clock.h
index e5dad050d51..b6ff9c68cb3 100644
--- a/dts/upstream/include/dt-bindings/clock/stm32fx-clock.h
+++ b/dts/upstream/include/dt-bindings/clock/stm32fx-clock.h
@@ -10,7 +10,7 @@
  * List of clocks which are not derived from system clock (SYSCLOCK)
  *
  * The index of these clocks is the secondary index of DT bindings
- * (see Documentation/devicetree/bindings/clock/st,stm32-rcc.txt)
+ * (see Documentation/devicetree/bindings/clock/st,stm32-rcc.yaml)
  *
  * e.g:
 	<assigned-clocks = <&rcc 1 CLK_LSE>;
diff --git a/dts/upstream/include/dt-bindings/clock/sun50i-a64-ccu.h b/dts/upstream/include/dt-bindings/clock/sun50i-a64-ccu.h
index 175892189e9..4f220ea7a23 100644
--- a/dts/upstream/include/dt-bindings/clock/sun50i-a64-ccu.h
+++ b/dts/upstream/include/dt-bindings/clock/sun50i-a64-ccu.h
@@ -44,7 +44,9 @@
 #define _DT_BINDINGS_CLK_SUN50I_A64_H_
 
 #define CLK_PLL_VIDEO0		7
+#define CLK_PLL_VIDEO0_2X	8
 #define CLK_PLL_PERIPH0		11
+#define CLK_PLL_MIPI		17
 
 #define CLK_CPUX		21
 #define CLK_BUS_MIPI_DSI	28
diff --git a/dts/upstream/include/dt-bindings/iio/adi,ad4695.h b/dts/upstream/include/dt-bindings/iio/adc/adi,ad4695.h
index 9fbef542bf6..9fbef542bf6 100644
--- a/dts/upstream/include/dt-bindings/iio/adi,ad4695.h
+++ b/dts/upstream/include/dt-bindings/iio/adc/adi,ad4695.h
diff --git a/dts/upstream/include/dt-bindings/input/linux-event-codes.h b/dts/upstream/include/dt-bindings/input/linux-event-codes.h
index a4206723f50..5a199f3d4a2 100644
--- a/dts/upstream/include/dt-bindings/input/linux-event-codes.h
+++ b/dts/upstream/include/dt-bindings/input/linux-event-codes.h
@@ -519,6 +519,7 @@
 #define KEY_NOTIFICATION_CENTER	0x1bc	/* Show/hide the notification center */
 #define KEY_PICKUP_PHONE	0x1bd	/* Answer incoming call */
 #define KEY_HANGUP_PHONE	0x1be	/* Decline incoming call */
+#define KEY_LINK_PHONE		0x1bf   /* AL Phone Syncing */
 
 #define KEY_DEL_EOL		0x1c0
 #define KEY_DEL_EOS		0x1c1
diff --git a/dts/upstream/include/dt-bindings/interconnect/qcom,ipq5424.h b/dts/upstream/include/dt-bindings/interconnect/qcom,ipq5424.h
new file mode 100644
index 00000000000..a770356112e
--- /dev/null
+++ b/dts/upstream/include/dt-bindings/interconnect/qcom,ipq5424.h
@@ -0,0 +1,24 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+#ifndef INTERCONNECT_QCOM_IPQ5424_H
+#define INTERCONNECT_QCOM_IPQ5424_H
+
+#define MASTER_ANOC_PCIE0		0
+#define SLAVE_ANOC_PCIE0		1
+#define MASTER_CNOC_PCIE0		2
+#define SLAVE_CNOC_PCIE0		3
+#define MASTER_ANOC_PCIE1		4
+#define SLAVE_ANOC_PCIE1		5
+#define MASTER_CNOC_PCIE1		6
+#define SLAVE_CNOC_PCIE1		7
+#define MASTER_ANOC_PCIE2		8
+#define SLAVE_ANOC_PCIE2		9
+#define MASTER_CNOC_PCIE2		10
+#define SLAVE_CNOC_PCIE2		11
+#define MASTER_ANOC_PCIE3		12
+#define SLAVE_ANOC_PCIE3		13
+#define MASTER_CNOC_PCIE3		14
+#define SLAVE_CNOC_PCIE3		15
+#define MASTER_CNOC_USB			16
+#define SLAVE_CNOC_USB			17
+
+#endif /* INTERCONNECT_QCOM_IPQ5424_H */
diff --git a/dts/upstream/include/dt-bindings/interconnect/qcom,sm8750-rpmh.h b/dts/upstream/include/dt-bindings/interconnect/qcom,sm8750-rpmh.h
new file mode 100644
index 00000000000..30563952a64
--- /dev/null
+++ b/dts/upstream/include/dt-bindings/interconnect/qcom,sm8750-rpmh.h
@@ -0,0 +1,143 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_SM8750_H
+#define __DT_BINDINGS_INTERCONNECT_QCOM_SM8750_H
+
+#define MASTER_QSPI_0				0
+#define MASTER_QUP_1				1
+#define MASTER_QUP_3				2
+#define MASTER_SDCC_4				3
+#define MASTER_UFS_MEM				4
+#define MASTER_USB3_0				5
+#define SLAVE_A1NOC_SNOC			6
+
+#define MASTER_QDSS_BAM				0
+#define MASTER_QUP_2				1
+#define MASTER_CRYPTO				2
+#define MASTER_IPA				3
+#define MASTER_SOCCP_AGGR_NOC			4
+#define MASTER_SP				5
+#define MASTER_QDSS_ETR				6
+#define MASTER_QDSS_ETR_1			7
+#define MASTER_SDCC_2				8
+#define SLAVE_A2NOC_SNOC			9
+
+#define MASTER_QUP_CORE_0			0
+#define MASTER_QUP_CORE_1			1
+#define MASTER_QUP_CORE_2			2
+#define SLAVE_QUP_CORE_0			3
+#define SLAVE_QUP_CORE_1			4
+#define SLAVE_QUP_CORE_2			5
+
+#define MASTER_CNOC_CFG				0
+#define SLAVE_AHB2PHY_SOUTH			1
+#define SLAVE_AHB2PHY_NORTH			2
+#define SLAVE_CAMERA_CFG			3
+#define SLAVE_CLK_CTL				4
+#define SLAVE_CRYPTO_0_CFG			5
+#define SLAVE_DISPLAY_CFG			6
+#define SLAVE_EVA_CFG				7
+#define SLAVE_GFX3D_CFG				8
+#define SLAVE_I2C				9
+#define SLAVE_I3C_IBI0_CFG			10
+#define SLAVE_I3C_IBI1_CFG			11
+#define SLAVE_IMEM_CFG				12
+#define SLAVE_CNOC_MSS				13
+#define SLAVE_PCIE_CFG				14
+#define SLAVE_PRNG				15
+#define SLAVE_QDSS_CFG				16
+#define SLAVE_QSPI_0				17
+#define SLAVE_QUP_3				18
+#define SLAVE_QUP_1				19
+#define SLAVE_QUP_2				20
+#define SLAVE_SDCC_2				21
+#define SLAVE_SDCC_4				22
+#define SLAVE_SPSS_CFG				23
+#define SLAVE_TCSR				24
+#define SLAVE_TLMM				25
+#define SLAVE_UFS_MEM_CFG			26
+#define SLAVE_USB3_0				27
+#define SLAVE_VENUS_CFG				28
+#define SLAVE_VSENSE_CTRL_CFG			29
+#define SLAVE_CNOC_MNOC_CFG			30
+#define SLAVE_PCIE_ANOC_CFG			31
+#define SLAVE_QDSS_STM				32
+#define SLAVE_TCU				33
+
+#define MASTER_GEM_NOC_CNOC			0
+#define MASTER_GEM_NOC_PCIE_SNOC		1
+#define SLAVE_AOSS				2
+#define SLAVE_IPA_CFG				3
+#define SLAVE_IPC_ROUTER_CFG			4
+#define SLAVE_SOCCP				5
+#define SLAVE_TME_CFG				6
+#define SLAVE_APPSS				7
+#define SLAVE_CNOC_CFG				8
+#define SLAVE_DDRSS_CFG				9
+#define SLAVE_BOOT_IMEM				10
+#define SLAVE_IMEM				11
+#define SLAVE_BOOT_IMEM_2			12
+#define SLAVE_SERVICE_CNOC			13
+#define SLAVE_PCIE_0				14
+
+#define MASTER_GPU_TCU				0
+#define MASTER_SYS_TCU				1
+#define MASTER_APPSS_PROC			2
+#define MASTER_GFX3D				3
+#define MASTER_LPASS_GEM_NOC			4
+#define MASTER_MSS_PROC				5
+#define MASTER_MNOC_HF_MEM_NOC			6
+#define MASTER_MNOC_SF_MEM_NOC			7
+#define MASTER_COMPUTE_NOC			8
+#define MASTER_ANOC_PCIE_GEM_NOC		9
+#define MASTER_SNOC_SF_MEM_NOC			10
+#define MASTER_UBWC_P				11
+#define MASTER_GIC				12
+#define SLAVE_UBWC_P				13
+#define SLAVE_GEM_NOC_CNOC			14
+#define SLAVE_LLCC				15
+#define SLAVE_MEM_NOC_PCIE_SNOC			16
+
+#define MASTER_LPIAON_NOC			0
+#define SLAVE_LPASS_GEM_NOC			1
+
+#define MASTER_LPASS_LPINOC			0
+#define SLAVE_LPIAON_NOC_LPASS_AG_NOC		1
+
+#define MASTER_LPASS_PROC			0
+#define SLAVE_LPICX_NOC_LPIAON_NOC		1
+
+#define MASTER_LLCC				0
+#define SLAVE_EBI1				1
+
+#define MASTER_CAMNOC_HF			0
+#define MASTER_CAMNOC_NRT_ICP_SF		1
+#define MASTER_CAMNOC_RT_CDM_SF			2
+#define MASTER_CAMNOC_SF			3
+#define MASTER_MDP				4
+#define MASTER_CDSP_HCP				5
+#define MASTER_VIDEO_CV_PROC			6
+#define MASTER_VIDEO_EVA			7
+#define MASTER_VIDEO_MVP			8
+#define MASTER_VIDEO_V_PROC			9
+#define MASTER_CNOC_MNOC_CFG			10
+#define SLAVE_MNOC_HF_MEM_NOC			11
+#define SLAVE_MNOC_SF_MEM_NOC			12
+#define SLAVE_SERVICE_MNOC			13
+
+#define MASTER_CDSP_PROC			0
+#define SLAVE_CDSP_MEM_NOC			1
+
+#define MASTER_PCIE_ANOC_CFG			0
+#define MASTER_PCIE_0				1
+#define SLAVE_ANOC_PCIE_GEM_NOC			2
+#define SLAVE_SERVICE_PCIE_ANOC			3
+
+#define MASTER_A1NOC_SNOC			0
+#define MASTER_A2NOC_SNOC			1
+#define SLAVE_SNOC_GEM_NOC_SF			2
+
+#endif
diff --git a/dts/upstream/include/dt-bindings/media/video-interfaces.h b/dts/upstream/include/dt-bindings/media/video-interfaces.h
index 68ac4e05e37..88b9d05d807 100644
--- a/dts/upstream/include/dt-bindings/media/video-interfaces.h
+++ b/dts/upstream/include/dt-bindings/media/video-interfaces.h
@@ -13,4 +13,11 @@
 #define MEDIA_BUS_TYPE_PARALLEL			5
 #define MEDIA_BUS_TYPE_BT656			6
 
+#define MEDIA_BUS_CSI2_CPHY_LINE_ORDER_ABC	0
+#define MEDIA_BUS_CSI2_CPHY_LINE_ORDER_ACB	1
+#define MEDIA_BUS_CSI2_CPHY_LINE_ORDER_BAC	2
+#define MEDIA_BUS_CSI2_CPHY_LINE_ORDER_BCA	3
+#define MEDIA_BUS_CSI2_CPHY_LINE_ORDER_CAB	4
+#define MEDIA_BUS_CSI2_CPHY_LINE_ORDER_CBA	5
+
 #endif /* __DT_BINDINGS_MEDIA_VIDEO_INTERFACES_H__ */
diff --git a/dts/upstream/include/dt-bindings/pinctrl/renesas,r9a09g047-pinctrl.h b/dts/upstream/include/dt-bindings/pinctrl/renesas,r9a09g047-pinctrl.h
new file mode 100644
index 00000000000..5917096720b
--- /dev/null
+++ b/dts/upstream/include/dt-bindings/pinctrl/renesas,r9a09g047-pinctrl.h
@@ -0,0 +1,41 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * This header provides constants for Renesas RZ/G3E family pinctrl bindings.
+ *
+ * Copyright (C) 2024 Renesas Electronics Corp.
+ *
+ */
+
+#ifndef __DT_BINDINGS_PINCTRL_RENESAS_R9A09G047_PINCTRL_H__
+#define __DT_BINDINGS_PINCTRL_RENESAS_R9A09G047_PINCTRL_H__
+
+#include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
+
+/* RZG3E_Px = Offset address of PFC_P_mn  - 0x20 */
+#define RZG3E_P0	0
+#define RZG3E_P1	1
+#define RZG3E_P2	2
+#define RZG3E_P3	3
+#define RZG3E_P4	4
+#define RZG3E_P5	5
+#define RZG3E_P6	6
+#define RZG3E_P7	7
+#define RZG3E_P8	8
+#define RZG3E_PA	10
+#define RZG3E_PB	11
+#define RZG3E_PC	12
+#define RZG3E_PD	13
+#define RZG3E_PE	14
+#define RZG3E_PF	15
+#define RZG3E_PG	16
+#define RZG3E_PH	17
+#define RZG3E_PJ	19
+#define RZG3E_PK	20
+#define RZG3E_PL	21
+#define RZG3E_PM	22
+#define RZG3E_PS	28
+
+#define RZG3E_PORT_PINMUX(b, p, f)	RZG2L_PORT_PINMUX(RZG3E_P##b, p, f)
+#define RZG3E_GPIO(port, pin)		RZG2L_GPIO(RZG3E_P##port, pin)
+
+#endif /* __DT_BINDINGS_PINCTRL_RENESAS_R9A09G047_PINCTRL_H__ */
diff --git a/dts/upstream/include/dt-bindings/pinctrl/renesas,r9a09g057-pinctrl.h b/dts/upstream/include/dt-bindings/pinctrl/renesas,r9a09g057-pinctrl.h
new file mode 100644
index 00000000000..2e83bf43160
--- /dev/null
+++ b/dts/upstream/include/dt-bindings/pinctrl/renesas,r9a09g057-pinctrl.h
@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * This header provides constants for Renesas RZ/V2H family pinctrl bindings.
+ *
+ * Copyright (C) 2024 Renesas Electronics Corp.
+ *
+ */
+
+#ifndef __DT_BINDINGS_PINCTRL_RENESAS_R9A09G057_PINCTRL_H__
+#define __DT_BINDINGS_PINCTRL_RENESAS_R9A09G057_PINCTRL_H__
+
+#include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
+
+/* RZV2H_Px = Offset address of PFC_P_mn  - 0x20 */
+#define RZV2H_P0	0
+#define RZV2H_P1	1
+#define RZV2H_P2	2
+#define RZV2H_P3	3
+#define RZV2H_P4	4
+#define RZV2H_P5	5
+#define RZV2H_P6	6
+#define RZV2H_P7	7
+#define RZV2H_P8	8
+#define RZV2H_P9	9
+#define RZV2H_PA	10
+#define RZV2H_PB	11
+
+#define RZV2H_PORT_PINMUX(b, p, f)	RZG2L_PORT_PINMUX(RZV2H_P##b, p, f)
+#define RZV2H_GPIO(port, pin)		RZG2L_GPIO(RZV2H_P##port, pin)
+
+#endif /* __DT_BINDINGS_PINCTRL_RENESAS_R9A09G057_PINCTRL_H__ */
diff --git a/dts/upstream/include/dt-bindings/reset/amlogic,meson-a1-audio-reset.h b/dts/upstream/include/dt-bindings/reset/amlogic,meson-a1-audio-reset.h
new file mode 100644
index 00000000000..7693552f150
--- /dev/null
+++ b/dts/upstream/include/dt-bindings/reset/amlogic,meson-a1-audio-reset.h
@@ -0,0 +1,36 @@
+/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
+/*
+ * Copyright (c) 2024, SaluteDevices. All Rights Reserved.
+ *
+ * Author: Jan Dakinevich <jan.dakinevich@salutedevices.com>
+ */
+
+#ifndef _DT_BINDINGS_AMLOGIC_MESON_A1_AUDIO_RESET_H
+#define _DT_BINDINGS_AMLOGIC_MESON_A1_AUDIO_RESET_H
+
+#define AUD_RESET_DDRARB	0
+#define AUD_RESET_TDMIN_A	1
+#define AUD_RESET_TDMIN_B	2
+#define AUD_RESET_TDMIN_LB	3
+#define AUD_RESET_LOOPBACK	4
+#define AUD_RESET_TDMOUT_A	5
+#define AUD_RESET_TDMOUT_B	6
+#define AUD_RESET_FRDDR_A	7
+#define AUD_RESET_FRDDR_B	8
+#define AUD_RESET_TODDR_A	9
+#define AUD_RESET_TODDR_B	10
+#define AUD_RESET_SPDIFIN	11
+#define AUD_RESET_RESAMPLE	12
+#define AUD_RESET_EQDRC		13
+#define AUD_RESET_LOCKER	14
+#define AUD_RESET_TOACODEC	30
+#define AUD_RESET_CLKTREE	31
+
+#define AUD_VAD_RESET_DDRARB	0
+#define AUD_VAD_RESET_PDM	1
+#define AUD_VAD_RESET_TDMIN_VAD	2
+#define AUD_VAD_RESET_TODDR_VAD	3
+#define AUD_VAD_RESET_TOVAD	4
+#define AUD_VAD_RESET_CLKTREE	5
+
+#endif /* _DT_BINDINGS_AMLOGIC_MESON_A1_AUDIO_RESET_H */
diff --git a/dts/upstream/include/dt-bindings/sound/qcom,wcd9335.h b/dts/upstream/include/dt-bindings/sound/qcom,wcd9335.h
index f5e9f1db091..4fc68aeb9e0 100644
--- a/dts/upstream/include/dt-bindings/sound/qcom,wcd9335.h
+++ b/dts/upstream/include/dt-bindings/sound/qcom,wcd9335.h
@@ -10,6 +10,5 @@
 #define AIF3_PB                 4
 #define AIF3_CAP                5
 #define AIF4_PB                 6
-#define NUM_CODEC_DAIS          7
 
 #endif
diff --git a/dts/upstream/src/arm/allwinner/suniv-f1c100s-licheepi-nano.dts b/dts/upstream/src/arm/allwinner/suniv-f1c100s-licheepi-nano.dts
index 43896723a99..472ded0aafc 100644
--- a/dts/upstream/src/arm/allwinner/suniv-f1c100s-licheepi-nano.dts
+++ b/dts/upstream/src/arm/allwinner/suniv-f1c100s-licheepi-nano.dts
@@ -62,6 +62,14 @@
 	status = "okay";
 };
 
+&codec {
+	allwinner,audio-routing =
+		"Headphone", "HP",
+		"Headphone", "HPCOM",
+		"MIC", "Mic";
+	status = "okay";
+};
+
 &usb_otg {
 	dr_mode = "otg";
 	status = "okay";
diff --git a/dts/upstream/src/arm/allwinner/suniv-f1c100s.dtsi b/dts/upstream/src/arm/allwinner/suniv-f1c100s.dtsi
index 3c61d59ab5f..e4b41bc9385 100644
--- a/dts/upstream/src/arm/allwinner/suniv-f1c100s.dtsi
+++ b/dts/upstream/src/arm/allwinner/suniv-f1c100s.dtsi
@@ -6,6 +6,7 @@
 
 #include <dt-bindings/clock/suniv-ccu-f1c100s.h>
 #include <dt-bindings/reset/suniv-ccu-f1c100s.h>
+#include <dt-bindings/dma/sun4i-a10.h>
 
 / {
 	#address-cells = <1>;
@@ -159,6 +160,15 @@
 			status = "disabled";
 		};
 
+		dma: dma-controller@1c02000 {
+			compatible = "allwinner,suniv-f1c100s-dma";
+			reg = <0x01c02000 0x1000>;
+			interrupts = <18>;
+			clocks = <&ccu CLK_BUS_DMA>;
+			resets = <&ccu RST_BUS_DMA>;
+			#dma-cells = <2>;
+		};
+
 		ccu: clock@1c20000 {
 			compatible = "allwinner,suniv-f1c100s-ccu";
 			reg = <0x01c20000 0x400>;
@@ -326,5 +336,19 @@
 			resets = <&ccu RST_BUS_UART2>;
 			status = "disabled";
 		};
+
+		codec: codec@1c23c00 {
+			#sound-dai-cells = <0>;
+			compatible = "allwinner,suniv-f1c100s-codec";
+			reg = <0x01c23c00 0x400>;
+			interrupts = <21>;
+			clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_CODEC>;
+			clock-names = "apb", "codec";
+			dmas = <&dma SUN4I_DMA_NORMAL 12>,
+			       <&dma SUN4I_DMA_NORMAL 12>;
+			dma-names = "rx", "tx";
+			resets = <&ccu RST_BUS_CODEC>;
+			status = "disabled";
+		};
 	};
 };
diff --git a/dts/upstream/src/arm/amlogic/meson.dtsi b/dts/upstream/src/arm/amlogic/meson.dtsi
index 8cb0fc78b2a..28ec2c821cd 100644
--- a/dts/upstream/src/arm/amlogic/meson.dtsi
+++ b/dts/upstream/src/arm/amlogic/meson.dtsi
@@ -255,8 +255,6 @@
 
 		usb0: usb@c9040000 {
 			compatible = "snps,dwc2";
-			#address-cells = <1>;
-			#size-cells = <0>;
 			reg = <0xc9040000 0x40000>;
 			interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 			phys = <&usb0_phy>;
@@ -270,8 +268,6 @@
 
 		usb1: usb@c90c0000 {
 			compatible = "snps,dwc2";
-			#address-cells = <1>;
-			#size-cells = <0>;
 			reg = <0xc90c0000 0x40000>;
 			interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 			phys = <&usb1_phy>;
diff --git a/dts/upstream/src/arm/aspeed/aspeed-bmc-ampere-mtjefferson.dts b/dts/upstream/src/arm/aspeed/aspeed-bmc-ampere-mtjefferson.dts
new file mode 100644
index 00000000000..c435359a4bd
--- /dev/null
+++ b/dts/upstream/src/arm/aspeed/aspeed-bmc-ampere-mtjefferson.dts
@@ -0,0 +1,622 @@
+// SPDX-License-Identifier: GPL-2.0-only
+// Copyright 2024 Ampere Computing LLC.
+
+/dts-v1/;
+
+#include "aspeed-g6.dtsi"
+#include <dt-bindings/i2c/i2c.h>
+#include <dt-bindings/gpio/aspeed-gpio.h>
+
+/ {
+	model = "Ampere Mt. Jefferson BMC";
+	compatible = "ampere,mtjefferson-bmc", "aspeed,ast2600";
+
+	aliases {
+		i2c20 = &i2c4_bus70_chn0;
+		i2c22 = &i2c4_bus70_chn2;
+
+		/*
+		 *  I2C OCP alias port
+		 */
+		i2c30 = &ocpslot;
+
+		/*
+		 *  I2C NVMe alias port
+		 */
+		i2c48 = &nvmeslot_0;
+		i2c49 = &nvmeslot_1;
+		i2c50 = &nvmeslot_2;
+		i2c51 = &nvmeslot_3;
+		i2c52 = &nvmeslot_4;
+		i2c53 = &nvmeslot_5;
+		i2c54 = &nvmeslot_6;
+		i2c55 = &nvmeslot_7;
+		i2c56 = &nvmeslot_8;
+		i2c57 = &nvmeslot_9;
+		i2c58 = &nvmeslot_10;
+		i2c59 = &nvmeslot_11;
+	};
+
+	chosen {
+		stdout-path = &uart5;
+	};
+
+	memory@80000000 {
+		device_type = "memory";
+		reg = <0x80000000 0x80000000>;
+	};
+
+	reserved-memory {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+
+		gfx_memory: framebuffer {
+			size = <0x01000000>;
+			alignment = <0x01000000>;
+			compatible = "shared-dma-pool";
+			reusable;
+		};
+
+		video_engine_memory: video {
+			size = <0x04000000>;
+			alignment = <0x01000000>;
+			compatible = "shared-dma-pool";
+			reusable;
+		};
+
+		vga_memory: region@bf000000 {
+			no-map;
+			compatible = "shared-dma-pool";
+			reg = <0xbf000000 0x01000000>;  /* 16M */
+		};
+	};
+
+	voltage_mon_reg: voltage-mon-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "ltc2497_reg";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-always-on;
+	};
+
+	leds {
+		compatible = "gpio-leds";
+		led-bmc-ready {
+			gpios = <&gpio0 ASPEED_GPIO(W, 5) (GPIO_ACTIVE_HIGH | GPIO_TRANSITORY)>;
+		};
+
+		led-sw-heartbeat {
+			gpios = <&gpio0 ASPEED_GPIO(N, 3) GPIO_ACTIVE_HIGH>;
+		};
+
+		led-identify {
+			gpios = <&gpio0 ASPEED_GPIO(S, 3) GPIO_ACTIVE_HIGH>;
+		};
+
+		led-fault {
+			gpios = <&gpio0 ASPEED_GPIO(P, 4) GPIO_ACTIVE_HIGH>;
+		};
+	};
+
+	iio-hwmon {
+		compatible = "iio-hwmon";
+		io-channels =   <&adc0 0>, <&adc0 1>, <&adc0 2>,
+				<&adc_i2c_2 0>, <&adc_i2c_2 1>,
+				<&adc_i2c_2 2>, <&adc_i2c_2 3>,
+				<&adc_i2c_2 4>, <&adc_i2c_2 5>,
+				<&adc_i2c_2 6>, <&adc_i2c_2 7>,
+				<&adc_i2c_2 8>, <&adc_i2c_2 9>,
+				<&adc_i2c_2 10>, <&adc_i2c_2 11>,
+				<&adc_i2c_2 12>, <&adc_i2c_2 13>,
+				<&adc_i2c_2 14>, <&adc_i2c_2 15>,
+				<&adc_i2c_0 0>, <&adc_i2c_0 1>,
+				<&adc_i2c_0 2>, <&adc_i2c_0 3>,
+				<&adc_i2c_0 4>, <&adc_i2c_0 5>,
+				<&adc_i2c_0 6>, <&adc_i2c_0 7>,
+				<&adc_i2c_0 8>, <&adc_i2c_0 9>,
+				<&adc_i2c_0 10>, <&adc_i2c_0 11>,
+				<&adc_i2c_0 12>;
+	};
+};
+
+&mdio0 {
+	status = "okay";
+
+	ethphy0: ethernet-phy@0 {
+		compatible = "ethernet-phy-ieee802.3-c22";
+		reg = <0>;
+	};
+};
+
+&mac0 {
+	status = "okay";
+
+	phy-mode = "rgmii";
+	phy-handle = <&ethphy0>;
+
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_rgmii1_default>;
+};
+
+&mac3 {
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_rmii4_default>;
+	use-ncsi;
+};
+
+&fmc {
+	status = "okay";
+	flash@0 {
+		status = "okay";
+		m25p,fast-read;
+		label = "bmc";
+		spi-max-frequency = <50000000>;
+#include "openbmc-flash-layout-64.dtsi"
+	};
+
+	flash@1 {
+		status = "okay";
+		m25p,fast-read;
+		label = "alt-bmc";
+		spi-max-frequency = <50000000>;
+#include "openbmc-flash-layout-64-alt.dtsi"
+	};
+};
+
+&spi1 {
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_spi1_default>;
+
+	flash@0 {
+		status = "okay";
+		m25p,fast-read;
+		label = "pnor";
+		spi-max-frequency = <20000000>;
+	};
+};
+
+&uart1 {
+	status = "okay";
+};
+
+&uart2 {
+	status = "okay";
+};
+
+&i2c0 {
+	status = "okay";
+};
+
+&i2c1 {
+	status = "okay";
+};
+
+&i2c2 {
+	status = "okay";
+};
+
+&i2c3 {
+	status = "okay";
+	bus-frequency = <1000000>;
+	multi-master;
+	mctp-controller;
+
+	mctp@10 {
+		compatible = "mctp-i2c-controller";
+		reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>;
+	};
+};
+
+&i2c4 {
+	status = "okay";
+	eeprom@50 {
+		compatible = "atmel,24c64";
+		reg = <0x50>;
+		pagesize = <32>;
+	};
+
+	i2c-mux@70 {
+		compatible = "nxp,pca9545";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <0x70>;
+		i2c-mux-idle-disconnect;
+
+		i2c4_bus70_chn0: i2c@0 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x0>;
+
+			eeprom@52 {
+				compatible = "atmel,24c256";
+				reg = <0x52>;
+				pagesize = <32>;
+			};
+			temperature-sensor@48 {
+				compatible = "ti,tmp75";
+				reg = <0x48>;
+			};
+			temperature-sensor@49 {
+				compatible = "ti,tmp75";
+				reg = <0x49>;
+			};
+			temperature-sensor@4a{
+				compatible = "ti,tmp75";
+				reg = <0x4a>;
+			};
+			temperature-sensor@4b {
+				compatible = "ti,tmp464";
+				reg = <0x4b>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				channel@0 {
+					reg = <0x0>;
+					status = "disabled";
+				};
+				channel@1 {
+					reg = <0x1>;
+					status = "disabled";
+				};
+				channel@2 {
+					reg = <0x2>;
+					status = "disabled";
+				};
+				channel@3 {
+					reg = <0x3>;
+					status = "disabled";
+				};
+				channel@4 {
+					reg = <0x4>;
+				};
+			};
+			temperature-sensor@4d {
+				compatible = "ti,tmp75";
+				reg = <0x4d>;
+			};
+			temperature-sensor@4e {
+				compatible = "ti,tmp75";
+				reg = <0x4e>;
+			};
+			temperature-sensor@4f {
+				compatible = "ti,tmp75";
+				reg = <0x4f>;
+			};
+			temperature-sensor@28 {
+				compatible = "nuvoton,nct7802";
+				reg = <0x28>;
+
+				#address-cells = <1>;
+				#size-cells = <0>;
+				channel@1 { /* RTD1 */
+					reg = <1>;
+					sensor-type = "temperature";
+					temperature-mode = "thermistor";
+				};
+			};
+			adc_i2c_0: adc@14 {
+				compatible = "lltc,ltc2497";
+				reg = <0x14>;
+				vref-supply = <&voltage_mon_reg>;
+				#io-channel-cells = <1>;
+			};
+		};
+
+		i2c4_bus70_chn2: i2c@2 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x2>;
+
+			adc_i2c_2: adc@14 {
+				compatible = "lltc,ltc2497";
+				reg = <0x14>;
+				vref-supply = <&voltage_mon_reg>;
+				#io-channel-cells = <1>;
+			};
+		};
+	};
+};
+
+&i2c5 {
+	status = "okay";
+	i2c-mux@70 {
+		compatible = "nxp,pca9548";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <0x70>;
+		i2c-mux-idle-disconnect;
+
+		i2c@0 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x0>;
+
+			i2c-mux@71 {
+				compatible = "nxp,pca9548";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				reg = <0x71>;
+				i2c-mux-idle-disconnect;
+
+				nvmeslot_8: i2c@0 {
+					#address-cells = <1>;
+					#size-cells = <0>;
+					reg = <0x0>;
+				};
+				nvmeslot_9: i2c@1 {
+					#address-cells = <1>;
+					#size-cells = <0>;
+					reg = <0x1>;
+				};
+				nvmeslot_10: i2c@2 {
+					#address-cells = <1>;
+					#size-cells = <0>;
+					reg = <0x2>;
+				};
+				nvmeslot_11: i2c@3 {
+					#address-cells = <1>;
+					#size-cells = <0>;
+					reg = <0x3>;
+				};
+			};
+
+			i2c-mux@72 {
+				compatible = "nxp,pca9548";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				reg = <0x72>;
+				i2c-mux-idle-disconnect;
+
+				nvmeslot_4: i2c@4 {
+					#address-cells = <1>;
+					#size-cells = <0>;
+					reg = <0x4>;
+				};
+				nvmeslot_5: i2c@5 {
+					#address-cells = <1>;
+					#size-cells = <0>;
+					reg = <0x5>;
+				};
+				nvmeslot_6: i2c@6 {
+					#address-cells = <1>;
+					#size-cells = <0>;
+					reg = <0x6>;
+				};
+				nvmeslot_7: i2c@7 {
+					#address-cells = <1>;
+					#size-cells = <0>;
+					reg = <0x7>;
+				};
+			};
+
+			i2c-mux@74 {
+				compatible = "nxp,pca9548";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				reg = <0x74>;
+				i2c-mux-idle-disconnect;
+
+				ocpslot: i2c@0 {
+					#address-cells = <1>;
+					#size-cells = <0>;
+					reg = <0x0>;
+
+					ocpslot_temp: temperature-sensor@1f {
+						compatible = "ti,tmp421";
+						reg = <0x1f>;
+						#address-cells = <1>;
+						#size-cells = <0>;
+
+						channel@0 {
+							reg = <0x0>;
+							status = "disabled";
+						};
+						channel@1 {
+							reg = <0x1>;
+						};
+					};
+				};
+
+				nvmeslot_0: i2c@4 {
+					#address-cells = <1>;
+					#size-cells = <0>;
+					reg = <0x4>;
+				};
+				nvmeslot_1: i2c@5 {
+					#address-cells = <1>;
+					#size-cells = <0>;
+					reg = <0x5>;
+				};
+				nvmeslot_2: i2c@6 {
+					#address-cells = <1>;
+					#size-cells = <0>;
+					reg = <0x6>;
+				};
+				nvmeslot_3: i2c@7 {
+					#address-cells = <1>;
+					#size-cells = <0>;
+					reg = <0x7>;
+				};
+			};
+		};
+	};
+};
+
+&i2c6 {
+	status = "okay";
+
+	rtc@51 {
+		compatible = "nxp,pcf8563";
+		reg = <0x51>;
+	};
+};
+
+&i2c7 {
+	status = "okay";
+
+	temperature-sensor@4f {
+		compatible = "ti,tmp75";
+		reg = <0x4f>;
+	};
+};
+
+&i2c8 {
+	status = "okay";
+
+	fan-controller@5c {
+		compatible = "onnn,adt7462";
+		reg = <0x5c>;
+	};
+};
+
+&i2c9 {
+	status = "okay";
+
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	eeprom@50 {
+		compatible = "atmel,24c02";
+		reg = <0x50>;
+	};
+
+	eeprom@52 {
+		compatible = "atmel,24c02";
+		reg = <0x52>;
+	};
+
+	temperature-sensor@18 {
+		compatible = "jedec,jc-42.4-temp";
+		reg = <0x18>;
+	};
+
+	temperature-sensor@1a {
+		compatible = "jedec,jc-42.4-temp";
+		reg = <0x1a>;
+	};
+};
+
+&i2c10 {
+	status = "okay";
+};
+
+&i2c11 {
+	status = "okay";
+	ssif-bmc@10 {
+		compatible = "ssif-bmc";
+		reg = <0x10>;
+	};
+};
+
+&i2c14 {
+	status = "okay";
+	eeprom@50 {
+		compatible = "atmel,24c64";
+		reg = <0x50>;
+		pagesize = <32>;
+	};
+
+	bmc_ast2600_cpu: temperature-sensor@48 {
+		compatible = "ti,tmp75";
+		reg = <0x48>;
+	};
+};
+
+&i2c15 {
+	status = "okay";
+	gpio_expander1: gpio-expander@22 {
+		compatible = "nxp,pca9535";
+		reg = <0x22>;
+		gpio-controller;
+		#gpio-cells = <2>;
+		gpio-line-names =
+			"presence-ocp1","presence-ocp2",
+			"","",
+			"","",
+			"","",
+			"","",
+			"","",
+			"","",
+			"","";
+	};
+};
+
+&adc0 {
+	status = "okay";
+
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_adc0_default &pinctrl_adc1_default
+		&pinctrl_adc2_default>;
+};
+
+&vhub {
+	status = "okay";
+};
+
+&video {
+	status = "okay";
+	memory-region = <&video_engine_memory>;
+};
+
+&gpio0 {
+	gpio-line-names =
+	/*A0-A7*/	"","","","","cpu-type-detect","i2c2-reset-n","i2c6-reset-n","i2c5-reset-n",
+	/*B0-B7*/	"","","","","host0-sysreset-n","host0-pmin-n","fru-rd-complete",
+			"chassis-id-sel",
+	/*C0-C7*/	"s0-vrd-fault-n","","bmc-debug-mode","","cpld-3v3-irq-n","","vrd-sel",
+			"spd-sel",
+	/*D0-D7*/	"presence-ps0","presence-ps1","hsc-12vmain-alt2-n","ext-high-temp-n",
+			"","","","",
+	/*E0-E7*/	"eth-phy-rst-n","eth-phy-int-n","","","","","","",
+	/*F0-F7*/	"s0-pcp-oc-warn-n","","power-chassis-control",
+			"cpu-bios-recover","s0-heartbeat","hs-scout-proc-hot","s0-vr-hot-n","",
+	/*G0-G7*/	"","","hsc-12vmain-alt1-n","","","bp-cpld-program-en","led-fp-sta-gr",
+			"led-fp-sta-amb",
+	/*H0-H7*/	"jtag-program-sel","jtag-cmpl2","wd-disable-n","power-chassis-good","","",
+			"","",
+	/*I0-I7*/	"","","","","","","power-button","rtc-battery-voltage-read-enable",
+	/*J0-J7*/	"","","","","","","","",
+	/*K0-K7*/	"","","","","","","","",
+	/*L0-L7*/	"","","","","reset-button","","","",
+	/*M0-M7*/	"nmi-n","s0-ddr-save","soc-spi-nor-access","presence-cpu0","s0-rtc-lock",
+			"","","",
+	/*N0-N7*/	"hpm-fw-recovery","hpm-stby-rst-n","jtag-sel-s0","led-sw-hb",
+			"jtag-dbgr-prsnt-n","","","",
+	/*O0-O7*/	"","","","","","","","",
+	/*P0-P7*/	"ps0-ac-loss-n","ps1-ac-loss-n","","","led-fault","user-mode","jtag-srst-n",
+			"led-bmc-hb",
+	/*Q0-Q7*/	"","","","","","","","",
+	/*R0-R7*/	"","","","","","","","",
+	/*S0-S7*/	"","","identify-button","led-identify","","spi-nor-access","host0-ready","",
+	/*T0-T7*/	"","","","","","","","",
+	/*U0-U7*/	"","","","","","","","",
+	/*V0-V7*/	"s0-hightemp-n","s0-fault-alert","s0-sys-auth-failure-n",
+			"host0-reboot-ack-n","s0-fw-boot-ok","host0-shd-req-n",
+			"host0-shd-ack-n","s0-overtemp-n",
+	/*W0-W7*/	"ocp-aux-pwren","ocp-main-pwren","ocp-pgood","",
+			"bmc-ok","bmc-ready","spi0-program-sel","spi0-backup-sel",
+	/*X0-X7*/	"","","","","","","","",
+	/*Y0-Y7*/	"","","","vrd-prg-en-n","","","","host0-special-boot",
+	/*Z0-Z7*/	"","ps0-pgood","ps1-pgood","","","","","";
+
+	ocp-aux-pwren-hog {
+		gpio-hog;
+		gpios = <ASPEED_GPIO(W, 0) GPIO_ACTIVE_HIGH>;
+		output-high;
+		line-name = "ocp-aux-pwren";
+	};
+
+};
+
+&gpio1 {
+	gpio-line-names =
+	/*18A0-18A7*/	"","","","","","","","",
+	/*18B0-18B7*/	"","","","","s0-soc-pgood","vga-ft-press-n","emmc-rst-n","s01-uart1-sel",
+	/*18C0-18C7*/	"uart1-mode0","uart1-mode1","uart2-mode0","uart2-mode1",
+			"","","","",
+	/*18D0-18D7*/	"","","","","","","","",
+	/*18E0-18E3*/	"","","","";
+};
diff --git a/dts/upstream/src/arm/aspeed/aspeed-bmc-ampere-mtmitchell.dts b/dts/upstream/src/arm/aspeed/aspeed-bmc-ampere-mtmitchell.dts
index 0295f5adcfb..2b336aa0146 100644
--- a/dts/upstream/src/arm/aspeed/aspeed-bmc-ampere-mtmitchell.dts
+++ b/dts/upstream/src/arm/aspeed/aspeed-bmc-ampere-mtmitchell.dts
@@ -677,6 +677,12 @@
 		#size-cells = <0>;
 		#gpio-cells = <2>;
 
+		gpio-line-names =
+		"ext-vref-sel","","presence-hdd-bp5-n","presence-hdd-bp6-n",
+		"","bmc-riser-en-n","bmc-ocp1-en-n","bmc-ocp0-en-n",
+		"","","","",
+		"","","","";
+
 		bmc-ocp0-en-hog {
 			gpio-hog;
 			gpios = <7 GPIO_ACTIVE_LOW>;
@@ -684,6 +690,16 @@
 			line-name = "bmc-ocp0-en-n";
 		};
 	};
+
+	fan-controller0@20 {
+		compatible = "maxim,max31790";
+		reg = <0x20>;
+	};
+
+	fan-controller1@2f {
+		compatible = "maxim,max31790";
+		reg = <0x2f>;
+	};
 };
 
 &i2c9 {
@@ -958,7 +974,7 @@
 			"fan-fault","psu-fault",
 			"","",
 			"","",
-			"","",
+			"gpi0","gpi1",
 			"","",
 			"","",
 			"","",
diff --git a/dts/upstream/src/arm/aspeed/aspeed-bmc-facebook-catalina.dts b/dts/upstream/src/arm/aspeed/aspeed-bmc-facebook-catalina.dts
index 82835e96317..c151984289b 100644
--- a/dts/upstream/src/arm/aspeed/aspeed-bmc-facebook-catalina.dts
+++ b/dts/upstream/src/arm/aspeed/aspeed-bmc-facebook-catalina.dts
@@ -50,14 +50,14 @@
 		i2c45 = &i2c0mux5ch1;
 		i2c46 = &i2c0mux5ch2;
 		i2c47 = &i2c0mux5ch3;
-		i2c48 = &i2c30mux0ch0;
-		i2c49 = &i2c30mux0ch1;
-		i2c50 = &i2c30mux0ch2;
-		i2c51 = &i2c30mux0ch3;
-		i2c52 = &i2c30mux0ch4;
-		i2c53 = &i2c30mux0ch5;
-		i2c54 = &i2c30mux0ch6;
-		i2c55 = &i2c30mux0ch7;
+		i2c48 = &i2c5mux0ch0;
+		i2c49 = &i2c5mux0ch1;
+		i2c50 = &i2c5mux0ch2;
+		i2c51 = &i2c5mux0ch3;
+		i2c52 = &i2c5mux0ch4;
+		i2c53 = &i2c5mux0ch5;
+		i2c54 = &i2c5mux0ch6;
+		i2c55 = &i2c5mux0ch7;
 	};
 
 	chosen {
@@ -153,6 +153,13 @@
 	status = "okay";
 };
 
+&mac2 {
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_ncsi3_default>;
+	use-ncsi;
+};
+
 &mac3 {
 	status = "okay";
 	pinctrl-names = "default";
@@ -185,6 +192,7 @@
 		reg = <0x71>;
 		#address-cells = <1>;
 		#size-cells = <0>;
+		i2c-mux-idle-disconnect;
 
 		i2c0mux0ch0: i2c@0 {
 			#address-cells = <1>;
@@ -213,6 +221,7 @@
 		reg = <0x72>;
 		#address-cells = <1>;
 		#size-cells = <0>;
+		i2c-mux-idle-disconnect;
 
 		i2c0mux1ch0: i2c@0 {
 			#address-cells = <1>;
@@ -242,79 +251,6 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <2>;
-			i2c-mux@70 {
-				compatible = "nxp,pca9548";
-				reg = <0x70>;
-				#address-cells = <1>;
-				#size-cells = <0>;
-
-				i2c30mux0ch0: i2c@0 {
-					#address-cells = <1>;
-					#size-cells = <0>;
-					reg = <0>;
-				};
-				i2c30mux0ch1: i2c@1 {
-					#address-cells = <1>;
-					#size-cells = <0>;
-					reg = <1>;
-				};
-				i2c30mux0ch2: i2c@2 {
-					#address-cells = <1>;
-					#size-cells = <0>;
-					reg = <2>;
-				};
-				i2c30mux0ch3: i2c@3 {
-					#address-cells = <1>;
-					#size-cells = <0>;
-					reg = <3>;
-				};
-				i2c30mux0ch4: i2c@4 {
-					#address-cells = <1>;
-					#size-cells = <0>;
-					reg = <4>;
-				};
-				i2c30mux0ch5: i2c@5 {
-					#address-cells = <1>;
-					#size-cells = <0>;
-					reg = <5>;
-				};
-				i2c30mux0ch6: i2c@6 {
-					#address-cells = <1>;
-					#size-cells = <0>;
-					reg = <6>;
-					// HDD FRU EEPROM
-					eeprom@52 {
-						compatible = "atmel,24c64";
-						reg = <0x52>;
-					};
-				};
-				i2c30mux0ch7: i2c@7 {
-					#address-cells = <1>;
-					#size-cells = <0>;
-					reg = <7>;
-
-					power-sensor@40 {
-						compatible = "ti,ina230";
-						reg = <0x40>;
-						shunt-resistor = <2000>;
-					};
-					power-sensor@41 {
-						compatible = "ti,ina230";
-						reg = <0x41>;
-						shunt-resistor = <2000>;
-					};
-					power-sensor@44 {
-						compatible = "ti,ina230";
-						reg = <0x44>;
-						shunt-resistor = <2000>;
-					};
-					power-sensor@45 {
-						compatible = "ti,ina230";
-						reg = <0x45>;
-						shunt-resistor = <2000>;
-					};
-				};
-			};
 		};
 		i2c0mux1ch3: i2c@3 {
 			#address-cells = <1>;
@@ -328,6 +264,7 @@
 		reg = <0x73>;
 		#address-cells = <1>;
 		#size-cells = <0>;
+		i2c-mux-idle-disconnect;
 
 		i2c0mux2ch0: i2c@0 {
 			#address-cells = <1>;
@@ -356,6 +293,7 @@
 		reg = <0x75>;
 		#address-cells = <1>;
 		#size-cells = <0>;
+		i2c-mux-idle-disconnect;
 
 		i2c0mux3ch0: i2c@0 {
 			#address-cells = <1>;
@@ -384,6 +322,7 @@
 		reg = <0x76>;
 		#address-cells = <1>;
 		#size-cells = <0>;
+		i2c-mux-idle-disconnect;
 
 		i2c0mux4ch0: i2c@0 {
 			#address-cells = <1>;
@@ -426,6 +365,7 @@
 		reg = <0x77>;
 		#address-cells = <1>;
 		#size-cells = <0>;
+		i2c-mux-idle-disconnect;
 
 		i2c0mux5ch0: i2c@0 {
 			#address-cells = <1>;
@@ -512,12 +452,12 @@
 			power-monitor@42 {
 				compatible = "lltc,ltc4287";
 				reg = <0x42>;
-				shunt-resistor-micro-ohms = <200>;
+				shunt-resistor-micro-ohms = <100>;
 			};
 			power-monitor@43 {
 				compatible = "lltc,ltc4287";
 				reg = <0x43>;
-				shunt-resistor-micro-ohms = <200>;
+				shunt-resistor-micro-ohms = <100>;
 			};
 		};
 		i2c1mux0ch5: i2c@5 {
@@ -593,8 +533,6 @@
 		reg = <0x20>;
 		gpio-controller;
 		#gpio-cells = <2>;
-		interrupt-parent = <&gpio0>;
-		interrupts = <ASPEED_GPIO(B, 4) IRQ_TYPE_LEVEL_LOW>;
 	};
 
 	// Module 1 IOEXP
@@ -603,8 +541,6 @@
 		reg = <0x21>;
 		gpio-controller;
 		#gpio-cells = <2>;
-		interrupt-parent = <&gpio0>;
-		interrupts = <ASPEED_GPIO(B, 4) IRQ_TYPE_LEVEL_LOW>;
 	};
 
 	// HMC IOEXP
@@ -613,8 +549,6 @@
 		reg = <0x27>;
 		gpio-controller;
 		#gpio-cells = <2>;
-		interrupt-parent = <&gpio0>;
-		interrupts = <ASPEED_GPIO(B, 4) IRQ_TYPE_LEVEL_LOW>;
 	};
 
 	// Module 0 EEPROM
@@ -640,6 +574,81 @@
 
 &i2c5 {
 	status = "okay";
+
+	i2c-mux@70 {
+		compatible = "nxp,pca9548";
+		reg = <0x70>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		i2c-mux-idle-disconnect;
+
+		i2c5mux0ch0: i2c@0 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0>;
+		};
+		i2c5mux0ch1: i2c@1 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <1>;
+		};
+		i2c5mux0ch2: i2c@2 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <2>;
+		};
+		i2c5mux0ch3: i2c@3 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <3>;
+		};
+		i2c5mux0ch4: i2c@4 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <4>;
+		};
+		i2c5mux0ch5: i2c@5 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <5>;
+		};
+		i2c5mux0ch6: i2c@6 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <6>;
+			// HDD FRU EEPROM
+			eeprom@52 {
+				compatible = "atmel,24c64";
+				reg = <0x52>;
+			};
+		};
+		i2c5mux0ch7: i2c@7 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <7>;
+
+			power-sensor@40 {
+				compatible = "ti,ina230";
+				reg = <0x40>;
+				shunt-resistor = <2000>;
+			};
+			power-sensor@41 {
+				compatible = "ti,ina230";
+				reg = <0x41>;
+				shunt-resistor = <2000>;
+			};
+			power-sensor@44 {
+				compatible = "ti,ina230";
+				reg = <0x44>;
+				shunt-resistor = <2000>;
+			};
+			power-sensor@45 {
+				compatible = "ti,ina230";
+				reg = <0x45>;
+				shunt-resistor = <2000>;
+			};
+		};
+	};
 };
 
 &i2c6 {
@@ -834,9 +843,9 @@
 	};
 
 	// OCP NIC1 FRU EEPROM
-	eeprom@50 {
+	eeprom@52 {
 		compatible = "atmel,24c64";
-		reg = <0x50>;
+		reg = <0x52>;
 	};
 };
 
diff --git a/dts/upstream/src/arm/aspeed/aspeed-bmc-facebook-harma.dts b/dts/upstream/src/arm/aspeed/aspeed-bmc-facebook-harma.dts
index cf3f807a38f..9cb511a846e 100644
--- a/dts/upstream/src/arm/aspeed/aspeed-bmc-facebook-harma.dts
+++ b/dts/upstream/src/arm/aspeed/aspeed-bmc-facebook-harma.dts
@@ -135,10 +135,6 @@
 	use-ncsi;
 };
 
-&rtc {
-	status = "okay";
-};
-
 &fmc {
 	status = "okay";
 
@@ -397,12 +393,6 @@
 		reg = <0x31>;
 		gpio-controller;
 		#gpio-cells = <2>;
-
-		gpio-line-names =
-		"","","","",
-		"","","presence-cmm","",
-		"","","","",
-		"","","","";
 	};
 
 	// PTTV FRU
@@ -426,12 +416,6 @@
 		reg = <0x31>;
 		gpio-controller;
 		#gpio-cells = <2>;
-
-		gpio-line-names =
-		"","","","",
-		"","","presence-cmm","",
-		"","","","",
-		"","","","";
 	};
 
 	// Aegis FRU
@@ -506,6 +490,11 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <3>;
+
+			rtc@51 {
+				compatible = "nxp,pcf8563";
+				reg = <0x51>;
+			};
 		};
 	};
 };
@@ -565,7 +554,7 @@
 	/*B0-B7*/	"","","","",
 			"bmc-spi-mux-select-0","led-identify","","",
 	/*C0-C7*/	"reset-cause-platrst","","","","",
-			"cpu0-err-alert","","",
+			"power-hsc-good","power-chassis-good","",
 	/*D0-D7*/	"","","sol-uart-select","","","","","",
 	/*E0-E7*/	"","","","","","","","",
 	/*F0-F7*/	"","","","","","","","",
@@ -584,14 +573,16 @@
 	/*O0-O7*/	"","","","","","","","",
 	/*P0-P7*/	"power-button","power-host-control",
 			"reset-button","","led-power","","","",
-	/*Q0-Q7*/	"","","","","","power-chassis-control","","",
+	/*Q0-Q7*/
+			"","","","",
+			"","power-chassis-control","","uart-switch-button",
 	/*R0-R7*/	"","","","","","","","",
 	/*S0-S7*/	"","","","","","","","",
 	/*T0-T7*/	"","","","","","","","",
 	/*U0-U7*/	"","","","","","","led-identify-gate","",
 	/*V0-V7*/	"","","","",
 			"rtc-battery-voltage-read-enable","",
-			"power-chassis-good","",
+			"","",
 	/*W0-W7*/	"","","","","","","","",
 	/*X0-X7*/	"","","","","","","","",
 	/*Y0-Y7*/	"","","","","","","","",
@@ -672,7 +663,7 @@
 	"presence-asic-modules-0","rt-cpu0-p1-force-enable",
 	"presence-asic-modules-1","bios-debug-msg-disable",
 	"","uart-control-buffer-select",
-	"","ac-control-n",
+	"presence-cmm","ac-control-n",
 	/*G0-G3 line 96-103*/
 	"FM_CPU_CORETYPE2","",
 	"FM_CPU_CORETYPE1","",
@@ -684,7 +675,7 @@
 	"FM_BOARD_REV_ID2","",
 	"FM_BOARD_REV_ID1","",
 	/*H0-H3 line 112-119*/
-	"FM_BOARD_REV_ID0","",
+	"FM_BOARD_REV_ID0","reset-control-cmos-clear",
 	"","","","","","",
 	/*H4-H7 line 120-127*/
 	"","",
@@ -699,7 +690,7 @@
 	/*I4-I7 line 136-143*/
 	"","","","","","","","",
 	/*J0-J3 line 144-151*/
-	"","","","","","","","",
+	"","","power-card-enable","","","","","",
 	/*J4-J7 line 152-159*/
 	"SLOT_ID_BCB_0","",
 	"SLOT_ID_BCB_1","",
@@ -715,9 +706,15 @@
 	"cpu0-thermtrip-alert","",
 	"reset-cause-pcie","",
 	/*L4-L7 line 184-191*/
-	"pvdd11-ocp-alert","","","","","","","",
+	"pvdd11-ocp-alert","",
+	"power-fault-n","",
+	"asic0-card-type-detection0-n","",
+	"asic0-card-type-detection1-n","",
 	/*M0-M3 line 192-199*/
-	"","","","","","","","",
+	"asic0-card-type-detection2-n","",
+	"uart-switch-lsb","",
+	"uart-switch-msb","",
+	"","",
 	/*M4-M7 line 200-207*/
 	"","","","","","","","",
 	/*N0-N3 line 208-215*/
diff --git a/dts/upstream/src/arm/aspeed/aspeed-bmc-facebook-minerva.dts b/dts/upstream/src/arm/aspeed/aspeed-bmc-facebook-minerva.dts
index 41e2246cfbd..ef96b17becb 100644
--- a/dts/upstream/src/arm/aspeed/aspeed-bmc-facebook-minerva.dts
+++ b/dts/upstream/src/arm/aspeed/aspeed-bmc-facebook-minerva.dts
@@ -23,6 +23,32 @@
 		i2c19 = &imux19;
 		i2c20 = &imux20;
 		i2c21 = &imux21;
+		i2c22 = &imux22;
+		i2c23 = &imux23;
+		i2c24 = &imux24;
+		i2c25 = &imux25;
+		i2c26 = &imux26;
+		i2c27 = &imux27;
+		i2c28 = &imux28;
+		i2c29 = &imux29;
+		i2c30 = &imux30;
+		i2c31 = &imux31;
+		i2c32 = &imux32;
+		i2c33 = &imux33;
+		i2c34 = &imux34;
+		i2c35 = &imux35;
+		i2c36 = &imux36;
+		i2c37 = &imux37;
+		i2c38 = &imux38;
+		i2c39 = &imux39;
+		i2c40 = &imux40;
+		i2c41 = &imux41;
+		i2c42 = &imux42;
+		i2c43 = &imux43;
+		i2c44 = &imux44;
+		i2c45 = &imux45;
+		i2c46 = &imux46;
+		i2c47 = &imux47;
 
 		spi1 = &spi_gpio;
 	};
@@ -75,6 +101,11 @@
 			gpios = <&leds_gpio 10 GPIO_ACTIVE_LOW>;
 			default-state = "off";
 		};
+
+		led-5 {
+			label = "bmc_ready_noled";
+			gpios = <&sgpiom0 141 (GPIO_ACTIVE_HIGH|GPIO_TRANSITORY)>;
+		};
 	};
 
 	spi_gpio: spi {
@@ -182,6 +213,63 @@
 		gpio-controller;
 		#gpio-cells = <2>;
 	};
+
+	gpio@11 {
+		compatible = "nxp,pca9555";
+		reg = <0x11>;
+		gpio-controller;
+		#gpio-cells = <2>;
+		interrupt-parent = <&sgpiom0>;
+		interrupts = <238 IRQ_TYPE_LEVEL_LOW>;
+
+		gpio-line-names =
+		"PWRGD_P24V_SMPWROK", "P1V5_PWROK",
+		"P3V3_PWROK", "P5V_PWROK",
+		"P12V_SCM_PWROK", "P12V_PWROK",
+		"P24V_PWROK", "P48V_HSC_PWROK",
+		"ERR_GPIO_IRQ", "TMP75_ALERT_N",
+		"BMC_PWROK", "P12V_INA230_ALERT_N",
+		"P24V_INA230_ALERT_N","",
+		"P48V_HSC_ALERT_N", "P1V05_PWROK";
+	};
+
+	gpio@12 {
+		compatible = "nxp,pca9555";
+		reg = <0x12>;
+		gpio-controller;
+		#gpio-cells = <2>;
+		interrupt-parent = <&sgpiom0>;
+		interrupts = <240 IRQ_TYPE_LEVEL_LOW>;
+
+		gpio-line-names =
+		"P1V05_PWR_FAIL", "P1V5_PWR_FAIL",
+		"P24V_PWR_FAIL", "P24V_SM_PWR_FAIL",
+		"IRQ_NW0/1/2_N", "IRQ_NW3/4/5_N",
+		"RTC_INT_N_R", "ERR_GPIO_IRQ",
+		"", "",
+		"", "",
+		"", "",
+		"", "";
+	};
+
+	gpio@13 {
+		compatible = "nxp,pca9555";
+		reg = <0x13>;
+		gpio-controller;
+		#gpio-cells = <2>;
+		interrupt-parent = <&sgpiom0>;
+		interrupts = <242 IRQ_TYPE_LEVEL_LOW>;
+
+		gpio-line-names =
+		"", "",
+		"", "",
+		"", "",
+		"", "",
+		"RACKMON_A_1", "RACKMON_A_2",
+		"RACKMON_B_1", "RACKMON_B_2",
+		"", "",
+		"", "";
+	};
 };
 
 &i2c1 {
@@ -213,10 +301,11 @@
 		#size-cells = <0>;
 		i2c-mux-idle-disconnect;
 
-		imux16: i2c@0 {
+		// FCB 1
+		imux16: i2c@1 {
 			#address-cells = <1>;
 			#size-cells = <0>;
-			reg = <0>;
+			reg = <1>;
 
 			eeprom@50 {
 				compatible = "atmel,24c128";
@@ -258,12 +347,88 @@
 				compatible = "ti,tmp75";
 				reg = <0x4b>;
 			};
-		};
 
-		imux17: i2c@1 {
+			gpio@11 {
+				compatible = "nxp,pca9555";
+				reg = <0x11>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				interrupt-parent = <&sgpiom0>;
+				interrupts = <218 IRQ_TYPE_LEVEL_LOW>;
+
+				gpio-line-names =
+				"P48V_FAN1_PWRGD_R", "P48V_FAN2_PWRGD_R",
+				"P48V_FAN3_PWRGD_R", "P48V_FAN4_PWRGD_R",
+				"FCB_1_P48V_ZONE0_PWRGD_R", "FCB_1_P48V_ZONE1_PWRGD_R",
+				"FCB_1_PWRGD_P3V3_R", "",
+				"", "",
+				"", "",
+				"", "",
+				"", "";
+			};
+
+			gpio@12 {
+				compatible = "nxp,pca9555";
+				reg = <0x12>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				interrupt-parent = <&sgpiom0>;
+				interrupts = <218 IRQ_TYPE_LEVEL_LOW>;
+
+				gpio-line-names =
+				"INA238_FAN1_ALERT_N", "INA238_FAN2_ALERT_N",
+				"INA238_FAN3_ALERT_N", "INA238_FAN4_ALERT_N",
+				"FCB_1_TMP75_ALERT_N", "",
+				"", "",
+				"FAN1_PRSNT", "FAN2_PRSNT",
+				"FAN3_PRSNT", "FAN4_PRSNT",
+				"", "",
+				"", "";
+			};
+
+			gpio@13 {
+				compatible = "nxp,pca9555";
+				reg = <0x13>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				interrupt-parent = <&sgpiom0>;
+				interrupts = <218 IRQ_TYPE_LEVEL_LOW>;
+
+				gpio-line-names =
+				"FAN1_IL_TACH_ALERT", "FAN1_OL_TACH_ALERT",
+				"FAN2_IL_TACH_ALERT", "FAN2_OL_TACH_ALERT",
+				"FAN3_IL_TACH_ALERT", "FAN3_OL_TACH_ALERT",
+				"FAN4_IL_TACH_ALERT", "FAN4_IL_TACH_ALERT",
+				"", "",
+				"", "",
+				"", "",
+				"", "";
+			};
+
+			gpio@17 {
+				compatible = "nxp,pca9555";
+				reg = <0x17>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				interrupt-parent = <&sgpiom0>;
+				interrupts = <218 IRQ_TYPE_LEVEL_LOW>;
+
+				gpio-line-names =
+				"FCB_1_P1V0_POWER_FAIL", "FCB_1_P1V8_POWER_FAIL",
+				"FCB_1_P48V_ZONE0_POWER_FAIL", "FAN1_POWER_FAIL",
+				"FAN2_POWER_FAIL", "FAN3_POWER_FAIL",
+				"FAN4_POWER_FAIL", "",
+				"", "",
+				"", "",
+				"", "",
+				"", "";
+			};
+		};
+		// FCB 2
+		imux17: i2c@0 {
 			#address-cells = <1>;
 			#size-cells = <0>;
-			reg = <1>;
+			reg = <0>;
 
 			eeprom@50 {
 				compatible = "atmel,24c128";
@@ -305,12 +470,88 @@
 				compatible = "ti,tmp75";
 				reg = <0x4b>;
 			};
-		};
 
-		imux18: i2c@2 {
+			gpio@11 {
+				compatible = "nxp,pca9555";
+				reg = <0x11>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				interrupt-parent = <&sgpiom0>;
+				interrupts = <220 IRQ_TYPE_LEVEL_LOW>;
+
+				gpio-line-names =
+				"P48V_FAN5_PWRGD_R", "P48V_FAN6_PWRGD_R",
+				"P48V_FAN7_PWRGD_R", "P48V_FAN8_PWRGD_R",
+				"FCB_2_P48V_ZONE0_PWRGD_R", "FCB_2_P48V_ZONE1_PWRGD_R",
+				"FCB_2_PWRGD_P3V3_R", "",
+				"", "",
+				"", "",
+				"", "",
+				"", "";
+			};
+
+			gpio@12 {
+				compatible = "nxp,pca9555";
+				reg = <0x12>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				interrupt-parent = <&sgpiom0>;
+				interrupts = <220 IRQ_TYPE_LEVEL_LOW>;
+
+				gpio-line-names =
+				"INA238_FAN5_ALERT_N", "INA238_FAN6_ALERT_N",
+				"INA238_FAN7_ALERT_N", "INA238_FAN8_ALERT_N",
+				"FCB_2_TMP75_ALERT_N", "",
+				"", "",
+				"FAN5_PRSNT", "FAN6_PRSNT",
+				"FAN7_PRSNT", "FAN8_PRSNT",
+				"", "",
+				"", "";
+			};
+
+			gpio@13 {
+				compatible = "nxp,pca9555";
+				reg = <0x13>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				interrupt-parent = <&sgpiom0>;
+				interrupts = <220 IRQ_TYPE_LEVEL_LOW>;
+
+				gpio-line-names =
+				"FAN5_IL_TACH_ALERT", "FAN5_OL_TACH_ALERT",
+				"FAN6_IL_TACH_ALERT", "FAN6_OL_TACH_ALERT",
+				"FAN7_IL_TACH_ALERT", "FAN7_OL_TACH_ALERT",
+				"FAN8_IL_TACH_ALERT", "FAN8_IL_TACH_ALERT",
+				"", "",
+				"", "",
+				"", "",
+				"", "";
+			};
+
+			gpio@17 {
+				compatible = "nxp,pca9555";
+				reg = <0x17>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				interrupt-parent = <&sgpiom0>;
+				interrupts = <220 IRQ_TYPE_LEVEL_LOW>;
+
+				gpio-line-names =
+				"FCB_2_P1V0_POWER_FAIL", "FCB_2_P1V8_POWER_FAIL",
+				"FCB_2_P48V_ZONE0_POWER_FAIL", "FAN5_POWER_FAIL",
+				"FAN6_POWER_FAIL", "FAN7_POWER_FAIL",
+				"FAN8_POWER_FAIL", "",
+				"", "",
+				"", "",
+				"", "",
+				"", "";
+			};
+		};
+		// FCB 3
+		imux18: i2c@3 {
 			#address-cells = <1>;
 			#size-cells = <0>;
-			reg = <2>;
+			reg = <3>;
 
 			eeprom@50 {
 				compatible = "atmel,24c128";
@@ -352,12 +593,88 @@
 				compatible = "ti,tmp75";
 				reg = <0x4b>;
 			};
-		};
 
-		imux19: i2c@3 {
+			gpio@11 {
+				compatible = "nxp,pca9555";
+				reg = <0x11>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				interrupt-parent = <&sgpiom0>;
+				interrupts = <230 IRQ_TYPE_LEVEL_LOW>;
+
+				gpio-line-names =
+				"P48V_FAN9_PWRGD_R", "P48V_FAN10_PWRGD_R",
+				"P48V_FAN11_PWRGD_R", "P48V_FAN12_PWRGD_R",
+				"FCB_3_P48V_ZONE0_PWRGD_R", "FCB_3_P48V_ZONE1_PWRGD_R",
+				"FCB_3_PWRGD_P3V3_R", "",
+				"", "",
+				"", "",
+				"", "",
+				"", "";
+			};
+
+			gpio@12 {
+				compatible = "nxp,pca9555";
+				reg = <0x12>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				interrupt-parent = <&sgpiom0>;
+				interrupts = <230 IRQ_TYPE_LEVEL_LOW>;
+
+				gpio-line-names =
+				"INA238_FAN9_ALERT_N", "INA238_FAN10_ALERT_N",
+				"INA238_FAN11_ALERT_N", "INA238_FAN12_ALERT_N",
+				"FCB_3_TMP75_ALERT_N", "",
+				"", "",
+				"FAN9_PRSNT", "FAN10_PRSNT",
+				"FAN11_PRSNT", "FAN12_PRSNT",
+				"", "",
+				"", "";
+			};
+
+			gpio@13 {
+				compatible = "nxp,pca9555";
+				reg = <0x13>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				interrupt-parent = <&sgpiom0>;
+				interrupts = <230 IRQ_TYPE_LEVEL_LOW>;
+
+				gpio-line-names =
+				"FAN9_IL_TACH_ALERT", "FAN9_OL_TACH_ALERT",
+				"FAN10_IL_TACH_ALERT", "FAN10_OL_TACH_ALERT",
+				"FAN11_IL_TACH_ALERT", "FAN11_OL_TACH_ALERT",
+				"FAN12_IL_TACH_ALERT", "FAN12_IL_TACH_ALERT",
+				"", "",
+				"", "",
+				"", "",
+				"", "";
+			};
+
+			gpio@17 {
+				compatible = "nxp,pca9555";
+				reg = <0x17>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				interrupt-parent = <&sgpiom0>;
+				interrupts = <230 IRQ_TYPE_LEVEL_LOW>;
+
+				gpio-line-names =
+				"FCB_3_P1V0_POWER_FAIL", "FCB_3_P1V8_POWER_FAIL",
+				"FCB_3_P48V_ZONE0_POWER_FAIL", "FAN9_POWER_FAIL",
+				"FAN10_POWER_FAIL", "FAN11_POWER_FAIL",
+				"FAN12_POWER_FAIL", "",
+				"", "",
+				"", "",
+				"", "",
+				"", "";
+			};
+		};
+		// FCB 4
+		imux19: i2c@2 {
 			#address-cells = <1>;
 			#size-cells = <0>;
-			reg = <3>;
+			reg = <2>;
 
 			eeprom@50 {
 				compatible = "atmel,24c128";
@@ -399,9 +716,85 @@
 				compatible = "ti,tmp75";
 				reg = <0x4b>;
 			};
-		};
 
-		imux20: i2c@5 {
+			gpio@11 {
+				compatible = "nxp,pca9555";
+				reg = <0x11>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				interrupt-parent = <&sgpiom0>;
+				interrupts = <232 IRQ_TYPE_LEVEL_LOW>;
+
+				gpio-line-names =
+				"P48V_FAN13_PWRGD_R", "P48V_FAN14_PWRGD_R",
+				"P48V_FAN15_PWRGD_R", "P48V_FAN16_PWRGD_R",
+				"FCB_4_P48V_ZONE0_PWRGD_R", "FCB_4_P48V_ZONE1_PWRGD_R",
+				"FCB_4_PWRGD_P3V3_R", "",
+				"", "",
+				"", "",
+				"", "",
+				"", "";
+			};
+
+			gpio@12 {
+				compatible = "nxp,pca9555";
+				reg = <0x12>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				interrupt-parent = <&sgpiom0>;
+				interrupts = <232 IRQ_TYPE_LEVEL_LOW>;
+
+				gpio-line-names =
+				"INA238_FAN13_ALERT_N", "INA238_FAN14_ALERT_N",
+				"INA238_FAN15_ALERT_N", "INA238_FAN16_ALERT_N",
+				"FCB_4_TMP75_ALERT_N", "",
+				"", "",
+				"FAN13_PRSNT", "FAN14_PRSNT",
+				"FAN15_PRSNT", "FAN16_PRSNT",
+				"", "",
+				"", "";
+			};
+
+			gpio@13 {
+				compatible = "nxp,pca9555";
+				reg = <0x13>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				interrupt-parent = <&sgpiom0>;
+				interrupts = <232 IRQ_TYPE_LEVEL_LOW>;
+
+				gpio-line-names =
+				"FAN13_IL_TACH_ALERT", "FAN13_OL_TACH_ALERT",
+				"FAN14_IL_TACH_ALERT", "FAN14_OL_TACH_ALERT",
+				"FAN15_IL_TACH_ALERT", "FAN15_OL_TACH_ALERT",
+				"FAN16_IL_TACH_ALERT", "FAN16_IL_TACH_ALERT",
+				"", "",
+				"", "",
+				"", "",
+				"", "";
+			};
+
+			gpio@17 {
+				compatible = "nxp,pca9555";
+				reg = <0x17>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				interrupt-parent = <&sgpiom0>;
+				interrupts = <232 IRQ_TYPE_LEVEL_LOW>;
+
+				gpio-line-names =
+				"FCB_4_P1V0_POWER_FAIL", "FCB_4_P1V8_POWER_FAIL",
+				"FCB_4_P48V_ZONE0_POWER_FAIL", "FAN13_POWER_FAIL",
+				"FAN14_POWER_FAIL", "FAN15_POWER_FAIL",
+				"FAN16_POWER_FAIL", "",
+				"", "",
+				"", "",
+				"", "",
+				"", "";
+			};
+		};
+		// FCB 5
+		imux20: i2c@4 {
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <4>;
@@ -445,9 +838,85 @@
 				compatible = "ti,tmp75";
 				reg = <0x4b>;
 			};
-		};
 
-		imux21: i2c@4 {
+			gpio@11 {
+				compatible = "nxp,pca9555";
+				reg = <0x11>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				interrupt-parent = <&sgpiom0>;
+				interrupts = <254 IRQ_TYPE_LEVEL_LOW>;
+
+				gpio-line-names =
+				"P48V_FAN20_PWRGD_R", "P48V_FAN19_PWRGD_R",
+				"P48V_FAN18_PWRGD_R", "P48V_FAN17_PWRGD_R",
+				"FCB_5_P48V_ZONE0_PWRGD_R", "FCB_5_P48V_ZONE1_PWRGD_R",
+				"FCB_5_PWRGD_P3V3_R", "",
+				"", "",
+				"", "",
+				"", "",
+				"", "";
+			};
+
+			gpio@12 {
+				compatible = "nxp,pca9555";
+				reg = <0x12>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				interrupt-parent = <&sgpiom0>;
+				interrupts = <254 IRQ_TYPE_LEVEL_LOW>;
+
+				gpio-line-names =
+				"INA238_FAN20_ALERT_N", "INA238_FAN19_ALERT_N",
+				"INA238_FAN18_ALERT_N", "INA238_FAN17_ALERT_N",
+				"FCB_5_TMP75_ALERT_N", "",
+				"", "",
+				"FAN20_PRSNT", "FAN19_PRSNT",
+				"FAN18_PRSNT", "FAN17_PRSNT",
+				"", "",
+				"", "";
+			};
+
+			gpio@13 {
+				compatible = "nxp,pca9555";
+				reg = <0x13>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				interrupt-parent = <&sgpiom0>;
+				interrupts = <254 IRQ_TYPE_LEVEL_LOW>;
+
+				gpio-line-names =
+				"FAN20_IL_TACH_ALERT", "FAN20_OL_TACH_ALERT",
+				"FAN19_IL_TACH_ALERT", "FAN19_OL_TACH_ALERT",
+				"FAN18_IL_TACH_ALERT", "FAN18_OL_TACH_ALERT",
+				"FAN17_IL_TACH_ALERT", "FAN17_OL_TACH_ALERT",
+				"", "",
+				"", "",
+				"", "",
+				"", "";
+			};
+
+			gpio@17 {
+				compatible = "nxp,pca9555";
+				reg = <0x17>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				interrupt-parent = <&sgpiom0>;
+				interrupts = <254 IRQ_TYPE_LEVEL_LOW>;
+
+				gpio-line-names =
+				"FCB_5_P1V0_POWER_FAIL", "FCB_5_P1V8_POWER_FAIL",
+				"FCB_5_P48V_ZONE0_POWER_FAIL", "FAN20_POWER_FAIL",
+				"FAN19_POWER_FAIL", "FAN18_POWER_FAIL",
+				"FAN17_POWER_FAIL", "",
+				"", "",
+				"", "",
+				"", "",
+				"", "";
+			};
+		};
+		// FCB 6
+		imux21: i2c@5 {
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <5>;
@@ -491,24 +960,316 @@
 				compatible = "ti,tmp75";
 				reg = <0x4b>;
 			};
+
+			gpio@11 {
+				compatible = "nxp,pca9555";
+				reg = <0x11>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				interrupt-parent = <&sgpiom0>;
+				interrupts = <252 IRQ_TYPE_LEVEL_LOW>;
+
+				gpio-line-names =
+				"P48V_FAN24_PWRGD_R", "P48V_FAN23_PWRGD_R",
+				"P48V_FAN22_PWRGD_R", "P48V_FAN21_PWRGD_R",
+				"FCB_6_P48V_ZONE0_PWRGD_R", "FCB_6_P48V_ZONE1_PWRGD_R",
+				"FCB_6_PWRGD_P3V3_R", "",
+				"", "",
+				"", "",
+				"", "",
+				"", "";
+			};
+
+			gpio@12 {
+				compatible = "nxp,pca9555";
+				reg = <0x12>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				interrupt-parent = <&sgpiom0>;
+				interrupts = <252 IRQ_TYPE_LEVEL_LOW>;
+
+				gpio-line-names =
+				"INA238_FAN24_ALERT_N", "INA238_FAN23_ALERT_N",
+				"INA238_FAN22_ALERT_N", "INA238_FAN21_ALERT_N",
+				"FCB_6_TMP75_ALERT_N", "",
+				"", "",
+				"FAN24_PRSNT", "FAN23_PRSNT",
+				"FAN22_PRSNT", "FAN21_PRSNT",
+				"", "",
+				"", "";
+			};
+
+			gpio@13 {
+				compatible = "nxp,pca9555";
+				reg = <0x13>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				interrupt-parent = <&sgpiom0>;
+				interrupts = <252 IRQ_TYPE_LEVEL_LOW>;
+
+				gpio-line-names =
+				"FAN24_IL_TACH_ALERT", "FAN24_OL_TACH_ALERT",
+				"FAN23_IL_TACH_ALERT", "FAN23_OL_TACH_ALERT",
+				"FAN22_IL_TACH_ALERT", "FAN22_OL_TACH_ALERT",
+				"FAN21_IL_TACH_ALERT", "FAN21_OL_TACH_ALERT",
+				"", "",
+				"", "",
+				"", "",
+				"", "";
+			};
+
+			gpio@17 {
+				compatible = "nxp,pca9555";
+				reg = <0x17>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				interrupt-parent = <&sgpiom0>;
+				interrupts = <252 IRQ_TYPE_LEVEL_LOW>;
+
+				gpio-line-names =
+				"FCB_6_P1V0_POWER_FAIL", "FCB_6_P1V8_POWER_FAIL",
+				"FCB_6_P48V_ZONE0_POWER_FAIL", "FAN24_POWER_FAIL",
+				"FAN23_POWER_FAIL", "FAN22_POWER_FAIL",
+				"FAN21_POWER_FAIL", "",
+				"", "",
+				"", "",
+				"", "",
+				"", "";
+			};
+		};
+
+		imux22: i2c@6 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <6>;
+		};
+
+		imux23: i2c@7 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <7>;
 		};
 	};
 };
 
 &i2c3 {
 	status = "okay";
+
+	i2c-mux@72 {
+		compatible = "nxp,pca9545";
+		reg = <0x72>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		imux24: i2c@0 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0>;
+
+			eeprom@50 {
+				compatible = "atmel,24c64";
+				reg = <0x50>;
+			};
+		};
+
+		imux25: i2c@1 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <1>;
+
+			eeprom@50 {
+				compatible = "atmel,24c64";
+				reg = <0x50>;
+			};
+		};
+
+		imux26: i2c@2 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <2>;
+
+			eeprom@50 {
+				compatible = "atmel,24c64";
+				reg = <0x50>;
+			};
+		};
+
+		imux27: i2c@3 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <3>;
+
+			eeprom@50 {
+				compatible = "atmel,24c64";
+				reg = <0x50>;
+			};
+		};
+	};
 };
 
 &i2c4 {
 	status = "okay";
+
+	i2c-mux@72 {
+		compatible = "nxp,pca9545";
+		reg = <0x72>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		imux28: i2c@0 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0>;
+
+			eeprom@50 {
+				compatible = "atmel,24c64";
+				reg = <0x50>;
+			};
+		};
+
+		imux29: i2c@1 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <1>;
+
+			eeprom@50 {
+				compatible = "atmel,24c64";
+				reg = <0x50>;
+			};
+		};
+
+		imux30: i2c@2 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <2>;
+
+			eeprom@50 {
+				compatible = "atmel,24c64";
+				reg = <0x50>;
+			};
+		};
+
+		imux31: i2c@3 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <3>;
+
+			eeprom@50 {
+				compatible = "atmel,24c64";
+				reg = <0x50>;
+			};
+		};
+	};
 };
 
 &i2c5 {
 	status = "okay";
+
+	i2c-mux@72 {
+		compatible = "nxp,pca9545";
+		reg = <0x72>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		imux32: i2c@0 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0>;
+
+			eeprom@50 {
+				compatible = "atmel,24c64";
+				reg = <0x50>;
+			};
+		};
+
+		imux33: i2c@1 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <1>;
+
+			eeprom@50 {
+				compatible = "atmel,24c64";
+				reg = <0x50>;
+			};
+		};
+
+		imux34: i2c@2 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <2>;
+
+			eeprom@50 {
+				compatible = "atmel,24c64";
+				reg = <0x50>;
+			};
+		};
+
+		imux35: i2c@3 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <3>;
+
+			eeprom@50 {
+				compatible = "atmel,24c64";
+				reg = <0x50>;
+			};
+		};
+	};
 };
 
 &i2c6 {
 	status = "okay";
+
+	i2c-mux@72 {
+		compatible = "nxp,pca9545";
+		reg = <0x72>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		imux36: i2c@0 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0>;
+
+			eeprom@50 {
+				compatible = "atmel,24c64";
+				reg = <0x50>;
+			};
+		};
+
+		imux37: i2c@1 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <1>;
+
+			eeprom@50 {
+				compatible = "atmel,24c64";
+				reg = <0x50>;
+			};
+		};
+
+		imux38: i2c@2 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <2>;
+
+			eeprom@50 {
+				compatible = "atmel,24c64";
+				reg = <0x50>;
+			};
+		};
+
+		imux39: i2c@3 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <3>;
+
+			eeprom@50 {
+				compatible = "atmel,24c64";
+				reg = <0x50>;
+			};
+		};
+	};
 };
 
 &i2c7 {
@@ -531,14 +1292,111 @@
 		compatible = "nxp,pcf8563";
 		reg = <0x51>;
 	};
+
+	rtc@68 {
+		compatible = "dallas,ds1339";
+		reg = <0x68>;
+	};
 };
 
 &i2c12 {
 	status = "okay";
+
+	i2c-mux@70 {
+		compatible = "nxp,pca9545";
+		reg = <0x70>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		imux40: i2c@0 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0>;
+
+			eeprom@50 {
+				compatible = "atmel,24c64";
+				reg = <0x50>;
+			};
+		};
+
+		imux41: i2c@1 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <1>;
+
+			eeprom@50 {
+				compatible = "atmel,24c64";
+				reg = <0x50>;
+			};
+		};
+
+		imux42: i2c@2 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <2>;
+
+			eeprom@50 {
+				compatible = "atmel,24c64";
+				reg = <0x50>;
+			};
+		};
+
+		imux43: i2c@3 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <3>;
+		};
+	};
 };
 
 &i2c13 {
 	status = "okay";
+
+	i2c-mux@70 {
+		compatible = "nxp,pca9545";
+		reg = <0x70>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		imux44: i2c@0 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0>;
+
+			eeprom@50 {
+				compatible = "atmel,24c64";
+				reg = <0x50>;
+			};
+		};
+
+		imux45: i2c@1 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <1>;
+
+			eeprom@50 {
+				compatible = "atmel,24c64";
+				reg = <0x50>;
+			};
+		};
+
+		imux46: i2c@2 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <2>;
+
+			eeprom@50 {
+				compatible = "atmel,24c64";
+				reg = <0x50>;
+			};
+		};
+
+		imux47: i2c@3 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <3>;
+		};
+	};
 };
 
 &i2c14 {
@@ -627,7 +1485,6 @@
 	gpio-line-names =
 	/*"input pin","output pin"*/
 	/*A0 - A7*/
-	"PRSNT_MTIA_BLADE0_N","PWREN_MTIA_BLADE0_EN_N",
 	"PRSNT_MTIA_BLADE1_N","PWREN_MTIA_BLADE1_EN_N",
 	"PRSNT_MTIA_BLADE2_N","PWREN_MTIA_BLADE2_EN_N",
 	"PRSNT_MTIA_BLADE3_N","PWREN_MTIA_BLADE3_EN_N",
@@ -635,8 +1492,8 @@
 	"PRSNT_MTIA_BLADE5_N","PWREN_MTIA_BLADE5_EN_N",
 	"PRSNT_MTIA_BLADE6_N","PWREN_MTIA_BLADE6_EN_N",
 	"PRSNT_MTIA_BLADE7_N","PWREN_MTIA_BLADE7_EN_N",
-	/*B0 - B7*/
 	"PRSNT_MTIA_BLADE8_N","PWREN_MTIA_BLADE8_EN_N",
+	/*B0 - B7*/
 	"PRSNT_MTIA_BLADE9_N","PWREN_MTIA_BLADE9_EN_N",
 	"PRSNT_MTIA_BLADE10_N","PWREN_MTIA_BLADE10_EN_N",
 	"PRSNT_MTIA_BLADE11_N","PWREN_MTIA_BLADE11_EN_N",
@@ -644,80 +1501,80 @@
 	"PRSNT_MTIA_BLADE13_N","PWREN_MTIA_BLADE13_EN_N",
 	"PRSNT_MTIA_BLADE14_N","PWREN_MTIA_BLADE14_EN_N",
 	"PRSNT_MTIA_BLADE15_N","PWREN_MTIA_BLADE15_EN_N",
+	"PRSNT_MTIA_BLADE16_N","PWREN_MTIA_BLADE16_EN_N",
 	/*C0 - C7*/
-	"PRSNT_NW_BLADE0_N","PWREN_NW_BLADE0_EN_N",
 	"PRSNT_NW_BLADE1_N","PWREN_NW_BLADE1_EN_N",
 	"PRSNT_NW_BLADE2_N","PWREN_NW_BLADE2_EN_N",
 	"PRSNT_NW_BLADE3_N","PWREN_NW_BLADE3_EN_N",
 	"PRSNT_NW_BLADE4_N","PWREN_NW_BLADE4_EN_N",
 	"PRSNT_NW_BLADE5_N","PWREN_NW_BLADE5_EN_N",
-	"PRSNT_FCB_TOP_0_N","PWREN_MTIA_BLADE0_HSC_EN_N",
-	"PRSNT_FCB_TOP_1_N","PWREN_MTIA_BLADE1_HSC_EN_N",
+	"PRSNT_NW_BLADE6_N","PWREN_NW_BLADE6_EN_N",
+	"PRSNT_FCB_1_N","PWREN_MTIA_BLADE1_HSC_EN_N",
+	"PRSNT_FCB_2_N","PWREN_MTIA_BLADE2_HSC_EN_N",
 	/*D0 - D7*/
-	"PRSNT_FCB_MIDDLE_0_N","PWREN_MTIA_BLADE2_HSC_EN_N",
-	"PRSNT_FCB_MIDDLE_1_N","PWREN_MTIA_BLADE3_HSC_EN_N",
-	"PRSNT_FCB_BOTTOM_1_N","PWREN_MTIA_BLADE4_HSC_EN_N",
-	"PRSNT_FCB_BOTTOM_0_N","PWREN_MTIA_BLADE5_HSC_EN_N",
-	"PWRGD_MTIA_BLADE0_PWROK_N","PWREN_MTIA_BLADE6_HSC_EN_N",
+	"PRSNT_FCB_3_N","PWREN_MTIA_BLADE3_HSC_EN_N",
+	"PRSNT_FCB_4_N","PWREN_MTIA_BLADE4_HSC_EN_N",
+	"PRSNT_FCB_6_N","PWREN_MTIA_BLADE5_HSC_EN_N",
+	"PRSNT_FCB_5_N","PWREN_MTIA_BLADE6_HSC_EN_N",
 	"PWRGD_MTIA_BLADE1_PWROK_N","PWREN_MTIA_BLADE7_HSC_EN_N",
 	"PWRGD_MTIA_BLADE2_PWROK_N","PWREN_MTIA_BLADE8_HSC_EN_N",
 	"PWRGD_MTIA_BLADE3_PWROK_N","PWREN_MTIA_BLADE9_HSC_EN_N",
-	/*E0 - E7*/
 	"PWRGD_MTIA_BLADE4_PWROK_N","PWREN_MTIA_BLADE10_HSC_EN_N",
+	/*E0 - E7*/
 	"PWRGD_MTIA_BLADE5_PWROK_N","PWREN_MTIA_BLADE11_HSC_EN_N",
 	"PWRGD_MTIA_BLADE6_PWROK_N","PWREN_MTIA_BLADE12_HSC_EN_N",
 	"PWRGD_MTIA_BLADE7_PWROK_N","PWREN_MTIA_BLADE13_HSC_EN_N",
 	"PWRGD_MTIA_BLADE8_PWROK_N","PWREN_MTIA_BLADE14_HSC_EN_N",
 	"PWRGD_MTIA_BLADE9_PWROK_N","PWREN_MTIA_BLADE15_HSC_EN_N",
-	"PWRGD_MTIA_BLADE10_PWROK_N","PWREN_NW_BLADE0_HSC_EN_N",
+	"PWRGD_MTIA_BLADE10_PWROK_N","PWREN_MTIA_BLADE16_HSC_EN_N",
 	"PWRGD_MTIA_BLADE11_PWROK_N","PWREN_NW_BLADE1_HSC_EN_N",
-	/*F0 - F7*/
 	"PWRGD_MTIA_BLADE12_PWROK_N","PWREN_NW_BLADE2_HSC_EN_N",
+	/*F0 - F7*/
 	"PWRGD_MTIA_BLADE13_PWROK_N","PWREN_NW_BLADE3_HSC_EN_N",
 	"PWRGD_MTIA_BLADE14_PWROK_N","PWREN_NW_BLADE4_HSC_EN_N",
 	"PWRGD_MTIA_BLADE15_PWROK_N","PWREN_NW_BLADE5_HSC_EN_N",
-	"PWRGD_NW_BLADE0_PWROK_N","PWREN_FCB_TOP_0_EN_N",
-	"PWRGD_NW_BLADE1_PWROK_N","PWREN_FCB_TOP_1_EN_N",
-	"PWRGD_NW_BLADE2_PWROK_N","PWREN_FCB_MIDDLE_0_EN_N",
-	"PWRGD_NW_BLADE3_PWROK_N","PWREN_FCB_MIDDLE_1_EN_N",
+	"PWRGD_MTIA_BLADE16_PWROK_N","PWREN_NW_BLADE6_HSC_EN_N",
+	"PWRGD_NW_BLADE1_PWROK_N","PWREN_SGPIO_FCB_2_EN_N",
+	"PWRGD_NW_BLADE2_PWROK_N","PWREN_SGPIO_FCB_1_EN_N",
+	"PWRGD_NW_BLADE3_PWROK_N","PWREN_SGPIO_FCB_4_EN_N",
+	"PWRGD_NW_BLADE4_PWROK_N","PWREN_SGPIO_FCB_3_EN_N",
 	/*G0 - G7*/
-	"PWRGD_NW_BLADE4_PWROK_N","PWREN_FCB_BOTTOM_1_EN_N",
-	"PWRGD_NW_BLADE5_PWROK_N","PWREN_FCB_BOTTOM_0_EN_N",
-	"PWRGD_FCB_TOP_0_PWROK_N","FM_CMM_AC_CYCLE_N",
-	"PWRGD_FCB_TOP_1_PWROK_N","MGMT_SFP_TX_DIS",
-	"PWRGD_FCB_MIDDLE_0_PWROK_N","FM_MDIO_SW_SEL",
-	"PWRGD_FCB_MIDDLE_1_PWROK_N","FM_P24V_SMPWR_EN",
-	"PWRGD_FCB_BOTTOM_1_PWROK_N","",
-	"PWRGD_FCB_BOTTOM_0_PWROK_N","",
+	"PWRGD_NW_BLADE5_PWROK_N","PWREN_SGPIO_FCB_5_EN_N",
+	"PWRGD_NW_BLADE6_PWROK_N","PWREN_SGPIO_FCB_6_EN_N",
+	"PWRGD_FCB_1","FM_BMC_RST_RTCRST_R",
+	"PWRGD_FCB_2","",
+	"PWRGD_FCB_3","FM_MDIO_SW_SEL",
+	"PWRGD_FCB_4","FM_P24V_SMPWR_EN",
+	"PWRGD_FCB_6","",
+	"PWRGD_FCB_5","",
 	/*H0 - H7*/
-	"LEAK_DETECT_MTIA_BLADE0_N","",
 	"LEAK_DETECT_MTIA_BLADE1_N","",
 	"LEAK_DETECT_MTIA_BLADE2_N","",
 	"LEAK_DETECT_MTIA_BLADE3_N","",
 	"LEAK_DETECT_MTIA_BLADE4_N","",
 	"LEAK_DETECT_MTIA_BLADE5_N","",
 	"LEAK_DETECT_MTIA_BLADE6_N","",
-	"LEAK_DETECT_MTIA_BLADE7_N","",
+	"LEAK_DETECT_MTIA_BLADE7_N","ERR_INJECT_CMM_PWR_FAIL_N",
+	"LEAK_DETECT_MTIA_BLADE8_N","",
 	/*I0 - I7*/
-	"LEAK_DETECT_MTIA_BLADE8_N","RST_I2CRST_FCB_BOTTOM_1_N",
-	"LEAK_DETECT_MTIA_BLADE9_N","RST_I2CRST_FCB_BOTTOM_0_N",
-	"LEAK_DETECT_MTIA_BLADE10_N","RST_I2CRST_FCB_MIDDLE_0_N",
-	"LEAK_DETECT_MTIA_BLADE11_N","RST_I2CRST_FCB_MIDDLE_1_N",
-	"LEAK_DETECT_MTIA_BLADE12_N","RST_I2CRST_FCB_TOP_0_N",
-	"LEAK_DETECT_MTIA_BLADE13_N","RST_I2CRST_FCB_TOP_1_N",
-	"LEAK_DETECT_MTIA_BLADE14_N","BMC_READY",
-	"LEAK_DETECT_MTIA_BLADE15_N","FM_88E6393X_BIN_UPDATE_EN_N",
+	"LEAK_DETECT_MTIA_BLADE9_N","RST_I2CRST_FCB_5_N",
+	"LEAK_DETECT_MTIA_BLADE10_N","RST_I2CRST_FCB_6_N",
+	"LEAK_DETECT_MTIA_BLADE11_N","RST_I2CRST_FCB_4_N",
+	"LEAK_DETECT_MTIA_BLADE12_N","RST_I2CRST_FCB_3_N",
+	"LEAK_DETECT_MTIA_BLADE13_N","RST_I2CRST_FCB_2_N",
+	"LEAK_DETECT_MTIA_BLADE14_N","RST_I2CRST_FCB_1_N",
+	"LEAK_DETECT_MTIA_BLADE15_N","BMC_READY",
+	"LEAK_DETECT_MTIA_BLADE16_N","FM_88E6393X_BIN_UPDATE_EN_N",
 	/*J0 - J7*/
-	"LEAK_DETECT_NW_BLADE0_N","WATER_VALVE_CLOSED_N",
-	"LEAK_DETECT_NW_BLADE1_N","",
+	"LEAK_DETECT_NW_BLADE1_N","WATER_VALVE_CLOSED_N",
 	"LEAK_DETECT_NW_BLADE2_N","",
 	"LEAK_DETECT_NW_BLADE3_N","",
 	"LEAK_DETECT_NW_BLADE4_N","",
 	"LEAK_DETECT_NW_BLADE5_N","",
-	"PWRGD_MTIA_BLADE0_HSC_PWROK_N","",
+	"LEAK_DETECT_NW_BLADE6_N","",
 	"PWRGD_MTIA_BLADE1_HSC_PWROK_N","",
-	/*K0 - K7*/
 	"PWRGD_MTIA_BLADE2_HSC_PWROK_N","",
+	/*K0 - K7*/
 	"PWRGD_MTIA_BLADE3_HSC_PWROK_N","",
 	"PWRGD_MTIA_BLADE4_HSC_PWROK_N","",
 	"PWRGD_MTIA_BLADE5_HSC_PWROK_N","",
@@ -725,49 +1582,50 @@
 	"PWRGD_MTIA_BLADE7_HSC_PWROK_N","",
 	"PWRGD_MTIA_BLADE8_HSC_PWROK_N","",
 	"PWRGD_MTIA_BLADE9_HSC_PWROK_N","",
-	/*L0 - L7*/
 	"PWRGD_MTIA_BLADE10_HSC_PWROK_N","",
+	/*L0 - L7*/
 	"PWRGD_MTIA_BLADE11_HSC_PWROK_N","",
 	"PWRGD_MTIA_BLADE12_HSC_PWROK_N","",
 	"PWRGD_MTIA_BLADE13_HSC_PWROK_N","",
 	"PWRGD_MTIA_BLADE14_HSC_PWROK_N","",
 	"PWRGD_MTIA_BLADE15_HSC_PWROK_N","",
-	"PWRGD_NW_BLADE0_HSC_PWROK_N","",
+	"PWRGD_MTIA_BLADE16_HSC_PWROK_N","",
 	"PWRGD_NW_BLADE1_HSC_PWROK_N","",
-	/*M0 - M7*/
 	"PWRGD_NW_BLADE2_HSC_PWROK_N","",
+	/*M0 - M7*/
 	"PWRGD_NW_BLADE3_HSC_PWROK_N","",
 	"PWRGD_NW_BLADE4_HSC_PWROK_N","",
 	"PWRGD_NW_BLADE5_HSC_PWROK_N","",
+	"PWRGD_NW_BLADE6_HSC_PWROK_N","",
 	"RPU_READY","",
 	"IT_GEAR_RPU_LINK_N","",
 	"IT_GEAR_LEAK","",
 	"WATER_VALVE_CLOSED_N","",
 	/*N0 - N7*/
-	"VALVE_STS0","",
-	"VALVE_STS1","",
-	"PCA9555_IRQ0_N","",
+	"VALVE_STATUS_0","",
+	"VALVE_STATUS_1","",
 	"PCA9555_IRQ1_N","",
+	"PCA9555_IRQ2_N","",
 	"CR_TOGGLE_BOOT_N","",
-	"IRQ_FCB_TOP0_N","",
-	"IRQ_FCB_TOP1_N","",
+	"IRQ_FCB_1_N","",
+	"IRQ_FCB_2_N","",
 	"CMM_CABLE_CARTRIDGE_PRSNT_BOT_N","",
 	/*O0 - O7*/
 	"CMM_CABLE_CARTRIDGE_PRSNT_TOP_N","",
 	"BOT_BCB_CABLE_PRSNT_N","",
 	"TOP_BCB_CABLE_PRSNT_N","",
-	"IRQ_FCB_MID0_N","",
-	"IRQ_FCB_MID1_N","",
+	"IRQ_FCB_3_N","",
+	"IRQ_FCB_4_N","",
 	"CHASSIS_LEAK0_DETECT_N","",
 	"CHASSIS_LEAK1_DETECT_N","",
-	"VALVE_RMON_A_1","",
+	"PCA9555_IRQ3_N","",
 	/*P0 - P7*/
-	"VALVE_RMON_A_2","",
-	"VALVE_RMON_B_1","",
-	"VALVE_RMON_B_2","",
+	"PCA9555_IRQ4_N","",
+	"PCA9555_IRQ5_N","",
+	"CMM_AC_PWR_BTN_N","",
 	"RPU_READY_SPARE","",
 	"IT_GEAR_LEAK_SPARE","",
 	"IT_GEAR_RPU_LINK_SPARE_N","",
-	"IRQ_FCB_BOT0_N","",
-	"IRQ_FCB_BOT0_N","";
+	"IRQ_FCB_6_N","",
+	"IRQ_FCB_5_N","";
 };
diff --git a/dts/upstream/src/arm/aspeed/aspeed-bmc-facebook-yosemite4.dts b/dts/upstream/src/arm/aspeed/aspeed-bmc-facebook-yosemite4.dts
index 98477792aa0..29f224bccd6 100644
--- a/dts/upstream/src/arm/aspeed/aspeed-bmc-facebook-yosemite4.dts
+++ b/dts/upstream/src/arm/aspeed/aspeed-bmc-facebook-yosemite4.dts
@@ -17,6 +17,27 @@
 		serial6 = &uart7;
 		serial7 = &uart8;
 		serial8 = &uart9;
+
+		i2c16 = &imux16;
+		i2c17 = &imux17;
+		i2c18 = &imux18;
+		i2c19 = &imux19;
+		i2c20 = &imux20;
+		i2c21 = &imux21;
+		i2c22 = &imux22;
+		i2c23 = &imux23;
+		i2c24 = &imux24;
+		i2c25 = &imux25;
+		i2c26 = &imux26;
+		i2c27 = &imux27;
+		i2c28 = &imux28;
+		i2c29 = &imux29;
+		i2c30 = &imux30;
+		i2c31 = &imux31;
+		i2c32 = &imux32;
+		i2c33 = &imux33;
+		i2c34 = &imux34;
+		i2c35 = &imux35;
 	};
 
 	chosen {
@@ -32,7 +53,25 @@
 		compatible = "iio-hwmon";
 		io-channels = <&adc0 0>, <&adc0 1>, <&adc0 2>, <&adc0 3>,
 				<&adc0 4>, <&adc0 5>, <&adc0 6>, <&adc0 7>,
-				<&adc1 0>, <&adc1 1>;
+				<&adc1 0>, <&adc1 1>, <&adc1 7>;
+	};
+
+	spi {
+		compatible = "spi-gpio";
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		sck-gpios = <&gpio0 ASPEED_GPIO(X, 3) GPIO_ACTIVE_HIGH>;
+		mosi-gpios = <&gpio0 ASPEED_GPIO(X, 4) GPIO_ACTIVE_HIGH>;
+		miso-gpios = <&gpio0 ASPEED_GPIO(X, 5) GPIO_ACTIVE_HIGH>;
+		cs-gpios = <&gpio0 ASPEED_GPIO(X, 0) GPIO_ACTIVE_LOW>;
+		num-chipselects = <1>;
+
+		tpm@0 {
+			compatible = "infineon,slb9670", "tcg,tpm_tis-spi";
+			reg = <0>;
+			spi-max-frequency = <33000000>;
+		};
 	};
 };
 
@@ -83,6 +122,13 @@
 	aspeed,ext-pulse-duration = <256>;
 };
 
+&wdt2 {
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_wdtrst2_default>;
+	aspeed,reset-type = "system";
+};
+
 &mac2 {
 	status = "okay";
 	pinctrl-names = "default";
@@ -105,15 +151,17 @@
 		status = "okay";
 		m25p,fast-read;
 		label = "bmc";
-		spi-rx-bus-width = <4>;
+		spi-tx-bus-width = <2>;
+		spi-rx-bus-width = <2>;
 		spi-max-frequency = <50000000>;
-#include "openbmc-flash-layout-64.dtsi"
+#include "openbmc-flash-layout-128.dtsi"
 	};
 	flash@1 {
 		status = "okay";
 		m25p,fast-read;
-		label = "bmc2";
-		spi-rx-bus-width = <4>;
+		label = "alt-bmc";
+		spi-tx-bus-width = <2>;
+		spi-rx-bus-width = <2>;
 		spi-max-frequency = <50000000>;
 	};
 };
@@ -129,9 +177,38 @@
 		reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>;
 	};
 
+	gpio@21 {
+		compatible = "nxp,pca9506";
+		reg = <0x21>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	gpio@22 {
+		compatible = "nxp,pca9506";
+		reg = <0x22>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	gpio@23 {
+		compatible = "nxp,pca9506";
+		reg = <0x23>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	gpio@24 {
+		compatible = "nxp,pca9506";
+		reg = <0x24>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
 	power-sensor@40 {
-		compatible = "adi,adm1278";
+		compatible = "adi,adm1281";
 		reg = <0x40>;
+		shunt-resistor-micro-ohms = <500>;
 	};
 };
 
@@ -146,9 +223,38 @@
 		reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>;
 	};
 
+	gpio@21 {
+		compatible = "nxp,pca9506";
+		reg = <0x21>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	gpio@22 {
+		compatible = "nxp,pca9506";
+		reg = <0x22>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	gpio@23 {
+		compatible = "nxp,pca9506";
+		reg = <0x23>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	gpio@24 {
+		compatible = "nxp,pca9506";
+		reg = <0x24>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
 	power-sensor@40 {
-		compatible = "adi,adm1278";
+		compatible = "adi,adm1281";
 		reg = <0x40>;
+		shunt-resistor-micro-ohms = <500>;
 	};
 };
 
@@ -163,9 +269,38 @@
 		reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>;
 	};
 
+	gpio@21 {
+		compatible = "nxp,pca9506";
+		reg = <0x21>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	gpio@22 {
+		compatible = "nxp,pca9506";
+		reg = <0x22>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	gpio@23 {
+		compatible = "nxp,pca9506";
+		reg = <0x23>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	gpio@24 {
+		compatible = "nxp,pca9506";
+		reg = <0x24>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
 	power-sensor@40 {
-		compatible = "adi,adm1278";
+		compatible = "adi,adm1281";
 		reg = <0x40>;
+		shunt-resistor-micro-ohms = <500>;
 	};
 };
 
@@ -180,9 +315,38 @@
 		reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>;
 	};
 
+	gpio@21 {
+		compatible = "nxp,pca9506";
+		reg = <0x21>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	gpio@22 {
+		compatible = "nxp,pca9506";
+		reg = <0x22>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	gpio@23 {
+		compatible = "nxp,pca9506";
+		reg = <0x23>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	gpio@24 {
+		compatible = "nxp,pca9506";
+		reg = <0x24>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
 	power-sensor@40 {
-		compatible = "adi,adm1278";
+		compatible = "adi,adm1281";
 		reg = <0x40>;
+		shunt-resistor-micro-ohms = <500>;
 	};
 };
 
@@ -197,9 +361,38 @@
 		reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>;
 	};
 
+	gpio@21 {
+		compatible = "nxp,pca9506";
+		reg = <0x21>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	gpio@22 {
+		compatible = "nxp,pca9506";
+		reg = <0x22>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	gpio@23 {
+		compatible = "nxp,pca9506";
+		reg = <0x23>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	gpio@24 {
+		compatible = "nxp,pca9506";
+		reg = <0x24>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
 	power-sensor@40 {
-		compatible = "adi,adm1278";
+		compatible = "adi,adm1281";
 		reg = <0x40>;
+		shunt-resistor-micro-ohms = <500>;
 	};
 };
 
@@ -214,9 +407,38 @@
 		reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>;
 	};
 
+	gpio@21 {
+		compatible = "nxp,pca9506";
+		reg = <0x21>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	gpio@22 {
+		compatible = "nxp,pca9506";
+		reg = <0x22>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	gpio@23 {
+		compatible = "nxp,pca9506";
+		reg = <0x23>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	gpio@24 {
+		compatible = "nxp,pca9506";
+		reg = <0x24>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
 	power-sensor@40 {
-		compatible = "adi,adm1278";
+		compatible = "adi,adm1281";
 		reg = <0x40>;
+		shunt-resistor-micro-ohms = <500>;
 	};
 };
 
@@ -231,9 +453,38 @@
 		reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>;
 	};
 
+	gpio@21 {
+		compatible = "nxp,pca9506";
+		reg = <0x21>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	gpio@22 {
+		compatible = "nxp,pca9506";
+		reg = <0x22>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	gpio@23 {
+		compatible = "nxp,pca9506";
+		reg = <0x23>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	gpio@24 {
+		compatible = "nxp,pca9506";
+		reg = <0x24>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
 	power-sensor@40 {
-		compatible = "adi,adm1278";
+		compatible = "adi,adm1281";
 		reg = <0x40>;
+		shunt-resistor-micro-ohms = <500>;
 	};
 };
 
@@ -248,48 +499,363 @@
 		reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>;
 	};
 
+	gpio@21 {
+		compatible = "nxp,pca9506";
+		reg = <0x21>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	gpio@22 {
+		compatible = "nxp,pca9506";
+		reg = <0x22>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	gpio@23 {
+		compatible = "nxp,pca9506";
+		reg = <0x23>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	gpio@24 {
+		compatible = "nxp,pca9506";
+		reg = <0x24>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
 	power-sensor@40 {
-		compatible = "adi,adm1278";
+		compatible = "adi,adm1281";
 		reg = <0x40>;
+		shunt-resistor-micro-ohms = <500>;
 	};
 };
 
 &i2c8 {
+	#address-cells = <1>;
+	#size-cells = <0>;
 	status = "okay";
 	bus-frequency = <400000>;
 	i2c-mux@70 {
 		compatible = "nxp,pca9544";
-		idle-state = <0>;
-		i2c-mux-idle-disconnect;
 		reg = <0x70>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		i2c-mux-idle-disconnect;
+
+		imux16: i2c@0 {
+			reg = <0>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			gpio@49 {
+				compatible = "nxp,pca9537";
+				reg = <0x49>;
+				gpio-controller;
+				#gpio-cells = <2>;
+			};
+
+			eeprom@50 {
+				compatible = "atmel,24c128";
+				reg = <0x50>;
+			};
+
+			eeprom@51 {
+				compatible = "atmel,24c128";
+				reg = <0x51>;
+			};
+
+			eeprom@54 {
+				compatible = "atmel,24c128";
+				reg = <0x54>;
+			};
+		};
+
+		imux17: i2c@1 {
+			reg = <1>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			gpio@49 {
+				compatible = "nxp,pca9537";
+				reg = <0x49>;
+				gpio-controller;
+				#gpio-cells = <2>;
+			};
+
+			eeprom@50 {
+				compatible = "atmel,24c128";
+				reg = <0x50>;
+			};
+
+			eeprom@51 {
+				compatible = "atmel,24c128";
+				reg = <0x51>;
+			};
+
+			eeprom@54 {
+				compatible = "atmel,24c128";
+				reg = <0x54>;
+			};
+		};
+
+		imux18: i2c@2 {
+			reg = <2>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			gpio@49 {
+				compatible = "nxp,pca9537";
+				reg = <0x49>;
+				gpio-controller;
+				#gpio-cells = <2>;
+			};
+
+			eeprom@50 {
+				compatible = "atmel,24c128";
+				reg = <0x50>;
+			};
+
+			eeprom@51 {
+				compatible = "atmel,24c128";
+				reg = <0x51>;
+			};
+
+			eeprom@54 {
+				compatible = "atmel,24c128";
+				reg = <0x54>;
+			};
+		};
+
+		imux19: i2c@3 {
+			reg = <3>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			gpio@49 {
+				compatible = "nxp,pca9537";
+				reg = <0x49>;
+				gpio-controller;
+				#gpio-cells = <2>;
+			};
+
+			eeprom@50 {
+				compatible = "atmel,24c128";
+				reg = <0x50>;
+			};
+
+			eeprom@51 {
+				compatible = "atmel,24c128";
+				reg = <0x51>;
+			};
+
+			eeprom@54 {
+				compatible = "atmel,24c128";
+				reg = <0x54>;
+			};
+		};
 	};
 };
 
 &i2c9 {
+	#address-cells = <1>;
+	#size-cells = <0>;
 	status = "okay";
 	bus-frequency = <400000>;
 	i2c-mux@71 {
 		compatible = "nxp,pca9544";
-		idle-state = <0>;
-		i2c-mux-idle-disconnect;
 		reg = <0x71>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		i2c-mux-idle-disconnect;
+
+		imux20: i2c@0 {
+			reg = <0>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			gpio@49 {
+				compatible = "nxp,pca9537";
+				reg = <0x49>;
+				gpio-controller;
+				#gpio-cells = <2>;
+			};
+
+			eeprom@50 {
+				compatible = "atmel,24c128";
+				reg = <0x50>;
+			};
+
+			eeprom@51 {
+				compatible = "atmel,24c128";
+				reg = <0x51>;
+			};
+
+			eeprom@54 {
+				compatible = "atmel,24c128";
+				reg = <0x54>;
+			};
+		};
+
+		imux21: i2c@1 {
+			reg = <1>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			gpio@49 {
+				compatible = "nxp,pca9537";
+				reg = <0x49>;
+				gpio-controller;
+				#gpio-cells = <2>;
+			};
+
+			eeprom@50 {
+				compatible = "atmel,24c128";
+				reg = <0x50>;
+			};
+
+			eeprom@51 {
+				compatible = "atmel,24c128";
+				reg = <0x51>;
+			};
+
+			eeprom@54 {
+				compatible = "atmel,24c128";
+				reg = <0x54>;
+			};
+		};
+
+		imux22: i2c@2 {
+			reg = <2>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			gpio@49 {
+				compatible = "nxp,pca9537";
+				reg = <0x49>;
+				gpio-controller;
+				#gpio-cells = <2>;
+			};
+
+			eeprom@50 {
+				compatible = "atmel,24c128";
+				reg = <0x50>;
+			};
+
+			eeprom@51 {
+				compatible = "atmel,24c128";
+				reg = <0x51>;
+			};
+
+			eeprom@54 {
+				compatible = "atmel,24c128";
+				reg = <0x54>;
+			};
+		};
+
+		imux23: i2c@3 {
+			reg = <3>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			gpio@49 {
+				compatible = "nxp,pca9537";
+				reg = <0x49>;
+				gpio-controller;
+				#gpio-cells = <2>;
+			};
+
+			eeprom@50 {
+				compatible = "atmel,24c128";
+				reg = <0x50>;
+			};
+
+			eeprom@51 {
+				compatible = "atmel,24c128";
+				reg = <0x51>;
+			};
+
+			eeprom@54 {
+				compatible = "atmel,24c128";
+				reg = <0x54>;
+			};
+		};
 	};
 };
 
 &i2c10 {
+	#address-cells = <1>;
+	#size-cells = <0>;
 	status = "okay";
 	bus-frequency = <400000>;
+	i2c-mux@74 {
+		compatible = "nxp,pca9544";
+		reg = <0x74>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		i2c-mux-idle-disconnect;
+
+		imux28: i2c@0 {
+			reg = <0>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			gpio@20 {
+				compatible = "nxp,pca9506";
+				reg = <0x20>;
+				gpio-controller;
+				#gpio-cells = <2>;
+			};
+
+			gpio@21 {
+				compatible = "nxp,pca9506";
+				reg = <0x21>;
+				gpio-controller;
+				#gpio-cells = <2>;
+			};
+
+			gpio@22 {
+				compatible = "nxp,pca9506";
+				reg = <0x22>;
+				gpio-controller;
+				#gpio-cells = <2>;
+			};
+
+			gpio@23 {
+				compatible = "nxp,pca9506";
+				reg = <0x23>;
+				gpio-controller;
+				#gpio-cells = <2>;
+			};
+
+			gpio@24 {
+				compatible = "nxp,pca9506";
+				reg = <0x24>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				gpio-line-names = "","","","",
+						  "NIC0_MAIN_PWR_EN",
+						  "NIC1_MAIN_PWR_EN",
+						  "NIC2_MAIN_PWR_EN",
+						  "NIC3_MAIN_PWR_EN",
+						  "","","","","","","","",
+						  "","","","","","","","",
+						  "","","","","","","","";
+			};
+		};
+
+		imux29: i2c@1 {
+			reg = <1>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+	};
 };
 
 &i2c11 {
 	status = "okay";
 	power-sensor@10 {
-		compatible = "adi, adm1272";
+		compatible = "adi,adm1272";
 		reg = <0x10>;
 	};
 
 	power-sensor@12 {
-		compatible = "adi, adm1272";
+		compatible = "adi,adm1272";
 		reg = <0x12>;
 	};
 
@@ -298,6 +864,20 @@
 		reg = <0x20>;
 		gpio-controller;
 		#gpio-cells = <2>;
+		interrupt-parent = <&gpio0>;
+		interrupts = <98 IRQ_TYPE_LEVEL_LOW>;
+		gpio-line-names = "P48V_OCP_GPIO1", "P48V_OCP_GPIO2",
+				  "P48V_OCP_GPIO3", "FAN_BOARD_0_REVISION_0_R",
+				  "FAN_BOARD_0_REVISION_1_R",
+				  "FAN_BOARD_1_REVISION_0_R",
+				  "FAN_BOARD_1_REVISION_1_R", "RST_MUX_R_N",
+				  "RST_LED_CONTROL_FAN_BOARD_0_N",
+				  "RST_LED_CONTROL_FAN_BOARD_1_N",
+				  "RST_IOEXP_FAN_BOARD_0_N",
+				  "RST_IOEXP_FAN_BOARD_1_N",
+				  "PWRGD_LOAD_SWITCH_FAN_BOARD_0_R",
+				  "PWRGD_LOAD_SWITCH_FAN_BOARD_1_R",
+				  "", "";
 	};
 
 	gpio@21 {
@@ -305,6 +885,19 @@
 		reg = <0x21>;
 		gpio-controller;
 		#gpio-cells = <2>;
+		interrupt-parent = <&gpio0>;
+		interrupts = <98 IRQ_TYPE_LEVEL_LOW>;
+		gpio-line-names = "HSC_OCP_SLOT_ODD_GPIO1",
+				  "HSC_OCP_SLOT_ODD_GPIO2",
+				  "HSC_OCP_SLOT_ODD_GPIO3",
+				  "HSC_OCP_SLOT_EVEN_GPIO1",
+				  "HSC_OCP_SLOT_EVEN_GPIO2",
+				  "HSC_OCP_SLOT_EVEN_GPIO3",
+				  "ADC_TYPE_0_R", "ADC_TYPE_1_R",
+				  "MEDUSA_BOARD_REV_0", "MEDUSA_BOARD_REV_1",
+				  "MEDUSA_BOARD_REV_2", "MEDUSA_BOARD_TYPE",
+				  "DELTA_MODULE_TYPE", "P12V_HSC_TYPE",
+				  "", "";
 	};
 
 	gpio@22 {
@@ -312,6 +905,16 @@
 		reg = <0x22>;
 		gpio-controller;
 		#gpio-cells = <2>;
+		interrupt-parent = <&gpio0>;
+		interrupts = <98 IRQ_TYPE_LEVEL_LOW>;
+		gpio-line-names = "CARD_TYPE_SLOT1", "CARD_TYPE_SLOT2",
+				  "CARD_TYPE_SLOT3", "CARD_TYPE_SLOT4",
+				  "CARD_TYPE_SLOT5", "CARD_TYPE_SLOT6",
+				  "CARD_TYPE_SLOT7", "CARD_TYPE_SLOT8",
+				  "OC_P48V_HSC_0_N", "FLT_P48V_HSC_0_N",
+				  "OC_P48V_HSC_1_N", "FLT_P48V_HSC_1_N",
+				  "EN_P48V_AUX_0", "EN_P48V_AUX_1",
+				  "PWRGD_P12V_AUX_0", "PWRGD_P12V_AUX_1";
 	};
 
 	gpio@23 {
@@ -319,6 +922,16 @@
 		reg = <0x23>;
 		gpio-controller;
 		#gpio-cells = <2>;
+		interrupt-parent = <&gpio0>;
+		interrupts = <98 IRQ_TYPE_LEVEL_LOW>;
+		gpio-line-names = "HSC1_ALERT1_R_N", "HSC2_ALERT1_R_N",
+				  "HSC3_ALERT1_R_N", "HSC4_ALERT1_R_N",
+				  "HSC5_ALERT1_R_N", "HSC6_ALERT1_R_N",
+				  "HSC7_ALERT1_R_N", "HSC8_ALERT1_R_N",
+				  "HSC1_ALERT2_R_N", "HSC2_ALERT2_R_N",
+				  "HSC3_ALERT2_R_N", "HSC4_ALERT2_R_N",
+				  "HSC5_ALERT2_R_N", "HSC6_ALERT2_R_N",
+				  "HSC7_ALERT2_R_N", "HSC8_ALERT2_R_N";
 	};
 
 	temperature-sensor@48 {
@@ -331,39 +944,84 @@
 		reg = <0x49>;
 	};
 
-	temperature-sensor@4a {
-		compatible = "ti,tmp75";
-		reg = <0x4a>;
-	};
-
-	temperature-sensor@4b {
-		compatible = "ti,tmp75";
-		reg = <0x4b>;
-	};
-
 	eeprom@54 {
-		compatible = "atmel,24c256";
+		compatible = "atmel,24c128";
 		reg = <0x54>;
 	};
 };
 
 &i2c12 {
+	#address-cells = <1>;
+	#size-cells = <0>;
 	status = "okay";
 	bus-frequency = <400000>;
 
-	temperature-sensor@48 {
-		compatible = "ti,tmp75";
-		reg = <0x48>;
-	};
+	i2c-mux@70 {
+		compatible = "nxp,pca9544";
+		reg = <0x70>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		i2c-mux-idle-disconnect;
 
-	eeprom@50 {
-		compatible = "atmel,24c128";
-		reg = <0x50>;
-	};
+		imux34: i2c@0 {
+			reg = <0>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			temperature-sensor@48 {
+				compatible = "ti,tmp75";
+				reg = <0x48>;
+			};
+
+			eeprom@50 {
+				compatible = "atmel,24c128";
+				reg = <0x50>;
+			};
+
+			eeprom@54 {
+				compatible = "atmel,24c64";
+				reg = <0x54>;
+			};
+
+			rtc@6f {
+				compatible = "nuvoton,nct3018y";
+				reg = <0x6f>;
+			};
 
-	rtc@6f {
-		compatible = "nuvoton,nct3018y";
-		reg = <0x6f>;
+			gpio@20 {
+				compatible = "nxp,pca9506";
+				reg = <0x20>;
+				gpio-controller;
+				#gpio-cells = <2>;
+			};
+
+			gpio@21 {
+				compatible = "nxp,pca9506";
+				reg = <0x21>;
+				gpio-controller;
+				#gpio-cells = <2>;
+			};
+
+			gpio@22 {
+				compatible = "nxp,pca9506";
+				reg = <0x22>;
+				gpio-controller;
+				#gpio-cells = <2>;
+			};
+
+			gpio@23 {
+				compatible = "nxp,pca9506";
+				reg = <0x23>;
+				gpio-controller;
+				#gpio-cells = <2>;
+			};
+		};
+
+		imux35: i2c@1 {
+			reg = <1>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
 	};
 };
 
@@ -380,24 +1038,26 @@
 };
 
 &i2c14 {
+	#address-cells = <1>;
+	#size-cells = <0>;
 	status = "okay";
 	bus-frequency = <400000>;
 	adc@1d {
 		compatible = "ti,adc128d818";
 		reg = <0x1d>;
-		ti,mode = /bits/ 8 <2>;
+		ti,mode = /bits/ 8 <1>;
 	};
 
-	adc@35 {
+	adc@36 {
 		compatible = "ti,adc128d818";
-		reg = <0x35>;
-		ti,mode = /bits/ 8 <2>;
+		reg = <0x36>;
+		ti,mode = /bits/ 8 <1>;
 	};
 
 	adc@37 {
 		compatible = "ti,adc128d818";
 		reg = <0x37>;
-		ti,mode = /bits/ 8 <2>;
+		ti,mode = /bits/ 8 <1>;
 	};
 
 	power-sensor@40 {
@@ -440,43 +1100,67 @@
 		reg = <0x51>;
 	};
 
-	i2c-mux@71 {
-		compatible = "nxp,pca9846";
+	i2c-mux@73 {
+		compatible = "nxp,pca9544";
+		reg = <0x73>;
 		#address-cells = <1>;
 		#size-cells = <0>;
-
-		idle-state = <0>;
 		i2c-mux-idle-disconnect;
-		reg = <0x71>;
 
-		i2c@0 {
+		imux32: i2c@0 {
+			reg = <0>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			adc@35 {
+				compatible = "maxim,max11617";
+				reg = <0x35>;
+			};
+		};
+
+		imux33: i2c@1 {
+			reg = <1>;
 			#address-cells = <1>;
 			#size-cells = <0>;
+			adc@35 {
+				compatible = "maxim,max11617";
+				reg = <0x35>;
+			};
+		};
+	};
+
+	i2c-mux@74 {
+		compatible = "nxp,pca9546";
+		reg = <0x74>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		i2c-mux-idle-disconnect;
+
+		imux30: i2c@0 {
 			reg = <0>;
+			#address-cells = <1>;
+			#size-cells = <0>;
 
 			adc@1f {
 				compatible = "ti,adc128d818";
 				reg = <0x1f>;
-				ti,mode = /bits/ 8 <2>;
+				ti,mode = /bits/ 8 <1>;
 			};
 
 			pwm@20{
-				compatible = "max31790";
+				compatible = "maxim,max31790";
 				reg = <0x20>;
-				#address-cells = <1>;
-				#size-cells = <0>;
 			};
 
 			gpio@22{
 				compatible = "ti,tca6424";
 				reg = <0x22>;
+				gpio-controller;
+				#gpio-cells = <2>;
 			};
 
-			pwm@23{
-				compatible = "max31790";
-				reg = <0x23>;
-				#address-cells = <1>;
-				#size-cells = <0>;
+			pwm@2f{
+				compatible = "maxim,max31790";
+				reg = <0x2f>;
 			};
 
 			adc@33 {
@@ -499,34 +1183,32 @@
 			};
 		};
 
-		i2c@1 {
+		imux31: i2c@1 {
+			reg = <1>;
 			#address-cells = <1>;
 			#size-cells = <0>;
-			reg = <0>;
 
 			adc@1f {
 				compatible = "ti,adc128d818";
 				reg = <0x1f>;
-				ti,mode = /bits/ 8 <2>;
+				ti,mode = /bits/ 8 <1>;
 			};
 
 			pwm@20{
-				compatible = "max31790";
+				compatible = "maxim,max31790";
 				reg = <0x20>;
-				#address-cells = <1>;
-				#size-cells = <0>;
 			};
 
 			gpio@22{
 				compatible = "ti,tca6424";
 				reg = <0x22>;
+				gpio-controller;
+				#gpio-cells = <2>;
 			};
 
-			pwm@23{
-				compatible = "max31790";
-				reg = <0x23>;
-				#address-cells = <1>;
-				#size-cells = <0>;
+			pwm@2f{
+				compatible = "maxim,max31790";
+				reg = <0x2f>;
 			};
 
 			adc@33 {
@@ -549,56 +1231,89 @@
 			};
 		};
 	};
+};
 
-	i2c-mux@73 {
+&i2c15 {
+	#address-cells = <1>;
+	#size-cells = <0>;
+	status = "okay";
+	multi-master;
+	bus-frequency = <400000>;
+
+	mctp@10 {
+		compatible = "mctp-i2c-controller";
+		reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>;
+	};
+
+	i2c-mux@72 {
 		compatible = "nxp,pca9544";
+		reg = <0x72>;
 		#address-cells = <1>;
 		#size-cells = <0>;
 
-		idle-state = <0>;
-		i2c-mux-idle-disconnect;
-		reg = <0x73>;
-
-		i2c@0 {
+		imux24: i2c@0 {
+			reg = <0>;
 			#address-cells = <1>;
 			#size-cells = <0>;
-			reg = <0>;
+			mctp-controller;
+			temperature-sensor@1f {
+				compatible = "ti,tmp421";
+				reg = <0x1f>;
+			};
 
-			adc@35 {
-				compatible = "maxim,max11617";
-				reg = <0x35>;
+			eeprom@50 {
+				compatible = "atmel,24c64";
+				reg = <0x50>;
 			};
 		};
 
-		i2c@1 {
+		imux25: i2c@1 {
+			reg = <1>;
 			#address-cells = <1>;
 			#size-cells = <0>;
-			reg = <0>;
+			mctp-controller;
+			temperature-sensor@1f {
+				compatible = "ti,tmp421";
+				reg = <0x1f>;
+			};
 
-			adc@35 {
-				compatible = "maxim,max11617";
-				reg = <0x35>;
+			eeprom@50 {
+				compatible = "atmel,24c64";
+				reg = <0x50>;
 			};
 		};
-	};
-};
 
-&i2c15 {
-	status = "okay";
-	mctp-controller;
-	multi-master;
-	bus-frequency = <400000>;
+		imux26: i2c@2 {
+			reg = <2>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			mctp-controller;
+			temperature-sensor@1f {
+				compatible = "ti,tmp421";
+				reg = <0x1f>;
+			};
 
-	mctp@10 {
-		compatible = "mctp-i2c-controller";
-		reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>;
-	};
+			eeprom@50 {
+				compatible = "atmel,24c64";
+				reg = <0x50>;
+			};
+		};
 
-	i2c-mux@72 {
-		compatible = "nxp,pca9544";
-		idle-state = <0>;
-		i2c-mux-idle-disconnect;
-		reg = <0x72>;
+		imux27: i2c@3 {
+			reg = <3>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			mctp-controller;
+			temperature-sensor@1f {
+				compatible = "ti,tmp421";
+				reg = <0x1f>;
+			};
+
+			eeprom@50 {
+				compatible = "atmel,24c64";
+				reg = <0x50>;
+			};
+		};
 	};
 };
 
@@ -612,10 +1327,10 @@
 
 &adc1 {
 	status = "okay";
-	pinctrl-0 = <&pinctrl_adc8_default &pinctrl_adc9_default>;
+	pinctrl-0 = <&pinctrl_adc8_default &pinctrl_adc9_default
+			&pinctrl_adc15_default>;
 };
 
-
 &ehci0 {
 	status = "okay";
 };
diff --git a/dts/upstream/src/arm/aspeed/aspeed-bmc-ibm-blueridge.dts b/dts/upstream/src/arm/aspeed/aspeed-bmc-ibm-blueridge.dts
index dfe5cc3edb5..bc4c4623542 100644
--- a/dts/upstream/src/arm/aspeed/aspeed-bmc-ibm-blueridge.dts
+++ b/dts/upstream/src/arm/aspeed/aspeed-bmc-ibm-blueridge.dts
@@ -207,7 +207,8 @@
 	/*F0-F7*/	"","","rtc-battery-voltage-read-enable","reset-cause-pinhole","","",
 			"factory-reset-toggle","",
 	/*G0-G7*/	"","","","","","","","",
-	/*H0-H7*/	"","bmc-ingraham0","rear-enc-id0","rear-enc-fault0","","","","",
+	/*H0-H7*/	"","led-bmc-ingraham0","led-rear-enc-id0","led-rear-enc-fault0","","","",
+			"",
 	/*I0-I7*/	"","","","","","","bmc-secure-boot","",
 	/*J0-J7*/	"","","","","","","","",
 	/*K0-K7*/	"","","","","","","","",
@@ -215,7 +216,7 @@
 	/*M0-M7*/	"","","","","","","","",
 	/*N0-N7*/	"","","","","","","","",
 	/*O0-O7*/	"","","","usb-power","","","","",
-	/*P0-P7*/	"","","","","pcieslot-power","","","",
+	/*P0-P7*/	"","","","","led-pcieslot-power","","","",
 	/*Q0-Q7*/	"cfam-reset","","regulator-standby-faulted","","","","","",
 	/*R0-R7*/	"bmc-tpm-reset","power-chassis-control","power-chassis-good","","","","",
 			"",
@@ -739,7 +740,7 @@
 			type = <PCA955X_TYPE_LED>;
 		};
 
-		led@10 {
+		led@a {
 			reg = <10>;
 			default-state = "keep";
 			label = "ddimm10";
@@ -747,7 +748,7 @@
 			type = <PCA955X_TYPE_LED>;
 		};
 
-		led@11 {
+		led@b {
 			reg = <11>;
 			default-state = "keep";
 			label = "ddimm11";
@@ -755,7 +756,7 @@
 			type = <PCA955X_TYPE_LED>;
 		};
 
-		led@12 {
+		led@c {
 			reg = <12>;
 			default-state = "keep";
 			label = "ddimm12";
@@ -763,7 +764,7 @@
 			type = <PCA955X_TYPE_LED>;
 		};
 
-		led@13 {
+		led@d {
 			reg = <13>;
 			default-state = "keep";
 			label = "ddimm13";
@@ -771,7 +772,7 @@
 			type = <PCA955X_TYPE_LED>;
 		};
 
-		led@14 {
+		led@e {
 			reg = <14>;
 			default-state = "keep";
 			label = "ddimm14";
@@ -779,7 +780,7 @@
 			type = <PCA955X_TYPE_LED>;
 		};
 
-		led@15 {
+		led@f {
 			reg = <15>;
 			default-state = "keep";
 			label = "ddimm15";
@@ -876,7 +877,7 @@
 			type = <PCA955X_TYPE_LED>;
 		};
 
-		led@10 {
+		led@a {
 			reg = <10>;
 			default-state = "keep";
 			label = "ddimm26";
@@ -884,7 +885,7 @@
 			type = <PCA955X_TYPE_LED>;
 		};
 
-		led@11 {
+		led@b {
 			reg = <11>;
 			default-state = "keep";
 			label = "ddimm27";
@@ -892,7 +893,7 @@
 			type = <PCA955X_TYPE_LED>;
 		};
 
-		led@12 {
+		led@c {
 			reg = <12>;
 			default-state = "keep";
 			label = "ddimm28";
@@ -900,7 +901,7 @@
 			type = <PCA955X_TYPE_LED>;
 		};
 
-		led@13 {
+		led@d {
 			reg = <13>;
 			default-state = "keep";
 			label = "ddimm29";
@@ -908,7 +909,7 @@
 			type = <PCA955X_TYPE_LED>;
 		};
 
-		led@14 {
+		led@e {
 			reg = <14>;
 			default-state = "keep";
 			label = "ddimm30";
@@ -916,7 +917,7 @@
 			type = <PCA955X_TYPE_LED>;
 		};
 
-		led@15 {
+		led@f {
 			reg = <15>;
 			default-state = "keep";
 			label = "ddimm31";
@@ -1005,7 +1006,7 @@
 			type = <PCA955X_TYPE_LED>;
 		};
 
-		led@10 {
+		led@a {
 			reg = <10>;
 			default-state = "keep";
 			label = "pcieslot7";
@@ -1013,7 +1014,7 @@
 			type = <PCA955X_TYPE_LED>;
 		};
 
-		led@11 {
+		led@b {
 			reg = <11>;
 			default-state = "keep";
 			label = "pcieslot8";
@@ -1021,7 +1022,7 @@
 			type = <PCA955X_TYPE_LED>;
 		};
 
-		led@12 {
+		led@c {
 			reg = <12>;
 			default-state = "keep";
 			label = "pcieslot9";
@@ -1029,7 +1030,7 @@
 			type = <PCA955X_TYPE_LED>;
 		};
 
-		led@13 {
+		led@d {
 			reg = <13>;
 			default-state = "keep";
 			label = "pcieslot10";
@@ -1037,7 +1038,7 @@
 			type = <PCA955X_TYPE_LED>;
 		};
 
-		led@14 {
+		led@e {
 			reg = <14>;
 			default-state = "keep";
 			label = "pcieslot11";
@@ -1045,7 +1046,7 @@
 			type = <PCA955X_TYPE_LED>;
 		};
 
-		led@15 {
+		led@f {
 			reg = <15>;
 			default-state = "keep";
 			label = "tpm-wilson";
@@ -1231,8 +1232,9 @@
 		#gpio-cells = <2>;
 
 		gpio-line-names =
-			"", "", "", "", "", "", "", "",
-			"", "", "", "", "", "", "power-config-full-load", "";
+			"", "", "", "", "", "", "P10_DCM0_PRES", "P10_DCM1_PRES",
+			"", "", "", "", "PRESENT_VRM_DCM0_N", "PRESENT_VRM_DCM1_N",
+			"power-config-full-load", "";
 	};
 
 	led-controller@61 {
diff --git a/dts/upstream/src/arm/aspeed/aspeed-bmc-ibm-everest.dts b/dts/upstream/src/arm/aspeed/aspeed-bmc-ibm-everest.dts
index 513077a1f4b..9961508ee87 100644
--- a/dts/upstream/src/arm/aspeed/aspeed-bmc-ibm-everest.dts
+++ b/dts/upstream/src/arm/aspeed/aspeed-bmc-ibm-everest.dts
@@ -353,6 +353,33 @@
 			"presence-base-op",
 			"";
 	};
+
+	led-controller@63 {
+		compatible = "nxp,pca9552";
+		reg = <0x63>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		gpio-line-names =
+			"presence-vrm-c12",
+			"presence-vrm-c13",
+			"presence-vrm-c15",
+			"presence-vrm-c16",
+			"presence-vrm-c17",
+			"presence-vrm-c18",
+			"presence-vrm-c20",
+			"presence-vrm-c21",
+			"presence-vrm-c54",
+			"presence-vrm-c55",
+			"presence-vrm-c57",
+			"presence-vrm-c58",
+			"presence-vrm-c59",
+			"presence-vrm-c60",
+			"presence-vrm-c62",
+			"presence-vrm-c63";
+	};
 };
 
 &i2c1 {
diff --git a/dts/upstream/src/arm/aspeed/aspeed-bmc-ibm-fuji.dts b/dts/upstream/src/arm/aspeed/aspeed-bmc-ibm-fuji.dts
index c24e464e5fa..9a43fc7bceb 100644
--- a/dts/upstream/src/arm/aspeed/aspeed-bmc-ibm-fuji.dts
+++ b/dts/upstream/src/arm/aspeed/aspeed-bmc-ibm-fuji.dts
@@ -355,6 +355,33 @@
 			"presence-base-op",
 			"";
 	};
+
+	led-controller@63 {
+		compatible = "nxp,pca9552";
+		reg = <0x63>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		gpio-line-names =
+			"presence-vrm-c12",
+			"presence-vrm-c13",
+			"presence-vrm-c15",
+			"presence-vrm-c16",
+			"presence-vrm-c17",
+			"presence-vrm-c18",
+			"presence-vrm-c20",
+			"presence-vrm-c21",
+			"presence-vrm-c54",
+			"presence-vrm-c55",
+			"presence-vrm-c57",
+			"presence-vrm-c58",
+			"presence-vrm-c59",
+			"presence-vrm-c60",
+			"presence-vrm-c62",
+			"presence-vrm-c63";
+	};
 };
 
 &i2c1 {
@@ -949,7 +976,7 @@
 			type = <PCA955X_TYPE_LED>;
 		};
 
-		led@10 {
+		led@a {
 			reg = <10>;
 			default-state = "keep";
 			label = "pcieslot-c10";
@@ -957,7 +984,7 @@
 			type = <PCA955X_TYPE_LED>;
 		};
 
-		led@11 {
+		led@b {
 			reg = <11>;
 			default-state = "keep";
 			label = "pcieslot-c11";
@@ -1058,7 +1085,7 @@
 			type = <PCA955X_TYPE_LED>;
 		};
 
-		led@10 {
+		led@a {
 			reg = <10>;
 			default-state = "keep";
 			label = "ddimm10";
@@ -1066,7 +1093,7 @@
 			type = <PCA955X_TYPE_LED>;
 		};
 
-		led@11 {
+		led@b {
 			reg = <11>;
 			default-state = "keep";
 			label = "ddimm11";
@@ -1074,7 +1101,7 @@
 			type = <PCA955X_TYPE_LED>;
 		};
 
-		led@12 {
+		led@c {
 			reg = <12>;
 			default-state = "keep";
 			label = "ddimm12";
@@ -1082,7 +1109,7 @@
 			type = <PCA955X_TYPE_LED>;
 		};
 
-		led@13 {
+		led@d {
 			reg = <13>;
 			default-state = "keep";
 			label = "ddimm13";
@@ -1090,7 +1117,7 @@
 			type = <PCA955X_TYPE_LED>;
 		};
 
-		led@14 {
+		led@e {
 			reg = <14>;
 			default-state = "keep";
 			label = "ddimm14";
@@ -1098,7 +1125,7 @@
 			type = <PCA955X_TYPE_LED>;
 		};
 
-		led@15 {
+		led@f {
 			reg = <15>;
 			default-state = "keep";
 			label = "ddimm15";
@@ -1195,7 +1222,7 @@
 			type = <PCA955X_TYPE_LED>;
 		};
 
-		led@10 {
+		led@a {
 			reg = <10>;
 			default-state = "keep";
 			label = "ddimm26";
@@ -1203,7 +1230,7 @@
 			type = <PCA955X_TYPE_LED>;
 		};
 
-		led@11 {
+		led@b {
 			reg = <11>;
 			default-state = "keep";
 			label = "ddimm27";
@@ -1211,7 +1238,7 @@
 			type = <PCA955X_TYPE_LED>;
 		};
 
-		led@12 {
+		led@c {
 			reg = <12>;
 			default-state = "keep";
 			label = "ddimm28";
@@ -1219,7 +1246,7 @@
 			type = <PCA955X_TYPE_LED>;
 		};
 
-		led@13 {
+		led@d {
 			reg = <13>;
 			default-state = "keep";
 			label = "ddimm29";
@@ -1227,7 +1254,7 @@
 			type = <PCA955X_TYPE_LED>;
 		};
 
-		led@14 {
+		led@e {
 			reg = <14>;
 			default-state = "keep";
 			label = "ddimm30";
@@ -1235,7 +1262,7 @@
 			type = <PCA955X_TYPE_LED>;
 		};
 
-		led@15 {
+		led@f {
 			reg = <15>;
 			default-state = "keep";
 			label = "ddimm31";
@@ -1332,7 +1359,7 @@
 			type = <PCA955X_TYPE_LED>;
 		};
 
-		led@10 {
+		led@a {
 			reg = <10>;
 			default-state = "keep";
 			label = "ddimm42";
@@ -1340,7 +1367,7 @@
 			type = <PCA955X_TYPE_LED>;
 		};
 
-		led@11 {
+		led@b {
 			reg = <11>;
 			default-state = "keep";
 			label = "ddimm43";
@@ -1348,7 +1375,7 @@
 			type = <PCA955X_TYPE_LED>;
 		};
 
-		led@12 {
+		led@c {
 			reg = <12>;
 			default-state = "keep";
 			label = "ddimm44";
@@ -1356,7 +1383,7 @@
 			type = <PCA955X_TYPE_LED>;
 		};
 
-		led@13 {
+		led@d {
 			reg = <13>;
 			default-state = "keep";
 			label = "ddimm45";
@@ -1364,7 +1391,7 @@
 			type = <PCA955X_TYPE_LED>;
 		};
 
-		led@14 {
+		led@e {
 			reg = <14>;
 			default-state = "keep";
 			label = "ddimm46";
@@ -1372,7 +1399,7 @@
 			type = <PCA955X_TYPE_LED>;
 		};
 
-		led@15 {
+		led@f {
 			reg = <15>;
 			default-state = "keep";
 			label = "ddimm47";
@@ -1469,7 +1496,7 @@
 			type = <PCA955X_TYPE_LED>;
 		};
 
-		led@10 {
+		led@a {
 			reg = <10>;
 			default-state = "keep";
 			label = "ddimm58";
@@ -1477,7 +1504,7 @@
 			type = <PCA955X_TYPE_LED>;
 		};
 
-		led@11 {
+		led@b {
 			reg = <11>;
 			default-state = "keep";
 			label = "ddimm59";
@@ -1485,7 +1512,7 @@
 			type = <PCA955X_TYPE_LED>;
 		};
 
-		led@12 {
+		led@c {
 			reg = <12>;
 			default-state = "keep";
 			label = "ddimm60";
@@ -1493,7 +1520,7 @@
 			type = <PCA955X_TYPE_LED>;
 		};
 
-		led@13 {
+		led@d {
 			reg = <13>;
 			default-state = "keep";
 			label = "ddimm61";
@@ -1501,7 +1528,7 @@
 			type = <PCA955X_TYPE_LED>;
 		};
 
-		led@14 {
+		led@e {
 			reg = <14>;
 			default-state = "keep";
 			label = "ddimm62";
@@ -1509,7 +1536,7 @@
 			type = <PCA955X_TYPE_LED>;
 		};
 
-		led@15 {
+		led@f {
 			reg = <15>;
 			default-state = "keep";
 			label = "ddimm63";
@@ -1598,7 +1625,7 @@
 			type = <PCA955X_TYPE_LED>;
 		};
 
-		led@10 {
+		led@a {
 			reg = <10>;
 			default-state = "keep";
 			label = "vrm6";
@@ -1606,7 +1633,7 @@
 			type = <PCA955X_TYPE_LED>;
 		};
 
-		led@11 {
+		led@b {
 			reg = <11>;
 			default-state = "keep";
 			label = "vrm7";
@@ -1614,7 +1641,7 @@
 			type = <PCA955X_TYPE_LED>;
 		};
 
-		led@12 {
+		led@c {
 			reg = <12>;
 			default-state = "keep";
 			label = "vrm12";
@@ -1622,7 +1649,7 @@
 			type = <PCA955X_TYPE_LED>;
 		};
 
-		led@13 {
+		led@d {
 			reg = <13>;
 			default-state = "keep";
 			label = "vrm13";
@@ -1630,7 +1657,7 @@
 			type = <PCA955X_TYPE_LED>;
 		};
 
-		led@14 {
+		led@e {
 			reg = <14>;
 			default-state = "keep";
 			label = "vrm14";
@@ -1638,7 +1665,7 @@
 			type = <PCA955X_TYPE_LED>;
 		};
 
-		led@15 {
+		led@f {
 			reg = <15>;
 			default-state = "keep";
 			label = "vrm15";
@@ -1727,7 +1754,7 @@
 			type = <PCA955X_TYPE_LED>;
 		};
 
-		led@10 {
+		led@a {
 			reg = <10>;
 			default-state = "keep";
 			label = "vrm2";
@@ -1735,7 +1762,7 @@
 			type = <PCA955X_TYPE_LED>;
 		};
 
-		led@11 {
+		led@b {
 			reg = <11>;
 			default-state = "keep";
 			label = "vrm3";
@@ -1743,7 +1770,7 @@
 			type = <PCA955X_TYPE_LED>;
 		};
 
-		led@12 {
+		led@c {
 			reg = <12>;
 			default-state = "keep";
 			label = "vrm8";
@@ -1751,7 +1778,7 @@
 			type = <PCA955X_TYPE_LED>;
 		};
 
-		led@13 {
+		led@d {
 			reg = <13>;
 			default-state = "keep";
 			label = "vrm9";
@@ -1759,7 +1786,7 @@
 			type = <PCA955X_TYPE_LED>;
 		};
 
-		led@14 {
+		led@e {
 			reg = <14>;
 			default-state = "keep";
 			label = "vrm10";
@@ -1767,7 +1794,7 @@
 			type = <PCA955X_TYPE_LED>;
 		};
 
-		led@15 {
+		led@f {
 			reg = <15>;
 			default-state = "keep";
 			label = "vrm11";
@@ -2118,7 +2145,7 @@
 					type = <PCA955X_TYPE_LED>;
 				};
 
-				led@10 {
+				led@a {
 					reg = <10>;
 					default-state = "keep";
 					label = "fan0";
@@ -2126,7 +2153,7 @@
 					type = <PCA955X_TYPE_LED>;
 				};
 
-				led@11 {
+				led@b {
 					reg = <11>;
 					default-state = "keep";
 					label = "fan1";
@@ -2134,7 +2161,7 @@
 					type = <PCA955X_TYPE_LED>;
 				};
 
-				led@12 {
+				led@c {
 					reg = <12>;
 					default-state = "keep";
 					label = "fan2";
@@ -2142,7 +2169,7 @@
 					type = <PCA955X_TYPE_LED>;
 				};
 
-				led@13 {
+				led@d {
 					reg = <13>;
 					default-state = "keep";
 					label = "fan3";
diff --git a/dts/upstream/src/arm/aspeed/aspeed-bmc-ibm-rainier.dts b/dts/upstream/src/arm/aspeed/aspeed-bmc-ibm-rainier.dts
index 0776b72c219..638a2c1c789 100644
--- a/dts/upstream/src/arm/aspeed/aspeed-bmc-ibm-rainier.dts
+++ b/dts/upstream/src/arm/aspeed/aspeed-bmc-ibm-rainier.dts
@@ -109,22 +109,22 @@
 		compatible = "gpio-leds";
 
 		/* BMC Card fault LED at the back */
-		bmc-ingraham0 {
+		led-bmc-ingraham0 {
 			gpios = <&gpio0 ASPEED_GPIO(H, 1) GPIO_ACTIVE_LOW>;
 		};
 
 		/* Enclosure ID LED at the back */
-		rear-enc-id0 {
+		led-rear-enc-id0 {
 			gpios = <&gpio0 ASPEED_GPIO(H, 2) GPIO_ACTIVE_LOW>;
 		};
 
 		/* Enclosure fault LED at the back */
-		rear-enc-fault0 {
+		led-rear-enc-fault0 {
 			gpios = <&gpio0 ASPEED_GPIO(H, 3) GPIO_ACTIVE_LOW>;
 		};
 
 		/* PCIE slot power LED */
-		pcieslot-power {
+		led-pcieslot-power {
 			gpios = <&gpio0 ASPEED_GPIO(P, 4) GPIO_ACTIVE_LOW>;
 		};
 	};
@@ -203,7 +203,7 @@
 	/*E0-E7*/	"","","","","","","","",
 	/*F0-F7*/	"","","rtc-battery-voltage-read-enable","reset-cause-pinhole","","","factory-reset-toggle","",
 	/*G0-G7*/	"","","","","","","","",
-	/*H0-H7*/	"","bmc-ingraham0","rear-enc-id0","rear-enc-fault0","","","","",
+	/*H0-H7*/	"","led-bmc-ingraham0","led-rear-enc-id0","led-rear-enc-fault0","","","","",
 	/*I0-I7*/	"","","","","","","bmc-secure-boot","",
 	/*J0-J7*/	"","","","","","","","",
 	/*K0-K7*/	"","","","","","","","",
@@ -211,7 +211,7 @@
 	/*M0-M7*/	"","","","","","","","",
 	/*N0-N7*/	"","","","","","","","",
 	/*O0-O7*/	"","","","usb-power","","","","",
-	/*P0-P7*/	"","","","","pcieslot-power","","","",
+	/*P0-P7*/	"","","","","led-pcieslot-power","","","",
 	/*Q0-Q7*/	"cfam-reset","","regulator-standby-faulted","","","","","",
 	/*R0-R7*/	"bmc-tpm-reset","power-chassis-control","power-chassis-good","","","","","",
 	/*S0-S7*/	"presence-ps0","presence-ps1","presence-ps2","presence-ps3",
@@ -1280,8 +1280,9 @@
 		#gpio-cells = <2>;
 
 		gpio-line-names =
-			"", "", "", "", "", "", "", "",
-			"", "", "", "", "", "", "power-config-full-load", "";
+			"", "", "", "", "", "", "P10_DCM0_PRES", "P10_DCM1_PRES",
+			"", "", "", "", "PRESENT_VRM_DCM0_N", "PRESENT_VRM_DCM1_N",
+			"power-config-full-load", "";
 	};
 
 	pca_pres2: pca9552@61 {
diff --git a/dts/upstream/src/arm/aspeed/aspeed-bmc-ibm-sbp1.dts b/dts/upstream/src/arm/aspeed/aspeed-bmc-ibm-sbp1.dts
new file mode 100644
index 00000000000..8d98be3d5f2
--- /dev/null
+++ b/dts/upstream/src/arm/aspeed/aspeed-bmc-ibm-sbp1.dts
@@ -0,0 +1,6086 @@
+// SPDX-License-Identifier: GPL-2.0+
+// Copyright 2024 IBM Corp.
+/dts-v1/;
+#include <dt-bindings/gpio/aspeed-gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/i2c/i2c.h>
+#include "aspeed-g6.dtsi"
+
+/ {
+	model = "IBM SBP1";
+	compatible = "ibm,sbp1-bmc", "aspeed,ast2600";
+
+	chosen {
+		stdout-path = &uart1;
+	};
+
+	memory@80000000 {
+		reg = <0x80000000 0x20000000>;
+		device_type = "memory";
+	};
+
+	reserved-memory {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+
+		gfx_memory: framebuffer {
+			size = <0x01000000>;
+			alignment = <0x01000000>;
+			compatible = "shared-dma-pool";
+			reusable;
+		};
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		led-power {
+			label = "LED_BMC_READY";
+			gpios = <&gpio0 ASPEED_GPIO(H, 1) GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_GREEN>;
+			default-state = "off";
+			retain-state-suspended;
+			panic-indicator;
+		};
+
+		led-id-tpm {
+			label = "LED_ID_TPM";
+			gpios = <&smb_pex_vr_ctrl 12 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-bat {
+			label = "LED_ID_BAT";
+			gpios = <&smb_pex_vr_ctrl 16 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-mgmt-port2 {
+			label = "LED_ID_MGMT_PORT2";
+			gpios = <&smb_pex_vr_ctrl 17 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-mgmt-port1 {
+			label = "LED_ID_MGMT_PORT1";
+			gpios = <&smb_pex_vr_ctrl 18 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-nic1-port1 {
+			label = "LED_ID_NIC1_PORT1";
+			gpios = <&smb_pex_vr_ctrl 22 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-nic1-port2 {
+			label = "LED_ID_NIC1_PORT2";
+			gpios = <&smb_pex_vr_ctrl 23 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-nic2-port1 {
+			label = "LED_ID_NIC2_PORT1";
+			gpios = <&smb_pex_vr_ctrl 24 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-nic2-port2 {
+			label = "LED_ID_NIC2_PORT2";
+			gpios = <&smb_pex_vr_ctrl 25 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-m2-ssd2 {
+			label = "LED_ID_M2_SSD2";
+			gpios = <&smb_pex_vr_ctrl 36 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-m2-ssd1 {
+			label = "LED_ID_M2_SSD1";
+			gpios = <&smb_pex_vr_ctrl 37 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-dwr-frnt-p {
+			label = "LED_ID_DWR_FRNT_P";
+			gpios = <&smb_svc_pex_cpu3_led 37 GPIO_ACTIVE_HIGH>;
+			color = <LED_COLOR_ID_BLUE>;
+
+			default-state = "on";
+			retain-state-suspended;
+			retain-state-shutdown;
+		};
+
+		led-pwr-dwr-frnt {
+			label = "LED_PWR_DWR_FRNT";
+			gpios = <&smb_svc_pex_cpu3_led 36 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_GREEN>;
+
+			retain-state-suspended;
+			retain-state-shutdown;
+		};
+
+		led-pwr-dwr-back {
+			label = "LED_PWR_DWR_BACK";
+			gpios = <&smb_pex_vr_ctrl 34 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_GREEN>;
+
+			retain-state-suspended;
+			retain-state-shutdown;
+		};
+
+		led-id-dwr-back-p {
+			label = "LED_ID_DWR_BACK_P";
+			gpios = <&smb_pex_vr_ctrl 35 GPIO_ACTIVE_HIGH>;
+			color = <LED_COLOR_ID_BLUE>;
+
+			default-state = "on";
+			retain-state-suspended;
+			retain-state-shutdown;
+		};
+
+		led-id-cpu0 {
+			label = "LED_ID_CPU0";
+			gpios = <&smb_svc_pex_cpu0_led 39 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-cpu1 {
+			label = "LED_ID_CPU1";
+			gpios = <&smb_svc_pex_cpu1_led 39 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-cpu2 {
+			label = "LED_ID_CPU2";
+			gpios = <&smb_svc_pex_cpu2_led 39 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-cpu3 {
+			label = "LED_ID_CPU3";
+			gpios = <&smb_svc_pex_cpu3_led 39 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-dimm-c0e2 {
+			label = "LED_ID_DIMM_C0E2";
+			gpios = <&smb_svc_pex_cpu0_led 20 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-dimm-c0e1 {
+			label = "LED_ID_DIMM_C0E1";
+			gpios = <&smb_svc_pex_cpu0_led 21 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-dimm-c0f2 {
+			label = "LED_ID_DIMM_C0F2";
+			gpios = <&smb_svc_pex_cpu0_led 22 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-dimm-c0f1 {
+			label = "LED_ID_DIMM_C0F1";
+			gpios = <&smb_svc_pex_cpu0_led 23 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-dimm-c0g2 {
+			label = "LED_ID_DIMM_C0G2";
+			gpios = <&smb_svc_pex_cpu0_led 24 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-dimm-c0g1 {
+			label = "LED_ID_DIMM_C0G1";
+			gpios = <&smb_svc_pex_cpu0_led 25 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-dimm-c0h2 {
+			label = "LED_ID_DIMM_C0H2";
+			gpios = <&smb_svc_pex_cpu0_led 26 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-dimm-c0h1 {
+			label = "LED_ID_DIMM_C0H1";
+			gpios = <&smb_svc_pex_cpu0_led 27 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-dimm-c0a2 {
+			label = "LED_ID_DIMM_C0A2";
+			gpios = <&smb_svc_pex_cpu0_led 28 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-dimm-c0a1 {
+			label = "LED_ID_DIMM_C0A1";
+			gpios = <&smb_svc_pex_cpu0_led 29 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-dimm-c0b2 {
+			label = "LED_ID_DIMM_C0B2";
+			gpios = <&smb_svc_pex_cpu0_led 30 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-dimm-c0b1 {
+			label = "LED_ID_DIMM_C0B1";
+			gpios = <&smb_svc_pex_cpu0_led 31 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-dimm-c0c2 {
+			label = "LED_ID_DIMM_C0C2";
+			gpios = <&smb_svc_pex_cpu0_led 32 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-dimm-c0c1 {
+			label = "LED_ID_DIMM_C0C1";
+			gpios = <&smb_svc_pex_cpu0_led 33 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-dimm-c0d2 {
+			label = "LED_ID_DIMM_C0D2";
+			gpios = <&smb_svc_pex_cpu0_led 34 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-dimm-c0d1 {
+			label = "LED_ID_DIMM_C0D1";
+			gpios = <&smb_svc_pex_cpu0_led 35 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-dimm-c1e2 {
+			label = "LED_ID_DIMM_C1E2";
+			gpios = <&smb_svc_pex_cpu1_led 20 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-dimm-c1e1 {
+			label = "LED_ID_DIMM_C1E1";
+			gpios = <&smb_svc_pex_cpu1_led 21 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-dimm-c1f2 {
+			label = "LED_ID_DIMM_C1F2";
+			gpios = <&smb_svc_pex_cpu1_led 22 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-dimm-c1f1 {
+			label = "LED_ID_DIMM_C1F1";
+			gpios = <&smb_svc_pex_cpu1_led 23 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-dimm-c1g2 {
+			label = "LED_ID_DIMM_C1G2";
+			gpios = <&smb_svc_pex_cpu1_led 24 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-dimm-c1g1 {
+			label = "LED_ID_DIMM_C1G1";
+			gpios = <&smb_svc_pex_cpu1_led 25 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-dimm-c1h2 {
+			label = "LED_ID_DIMM_C1H2";
+			gpios = <&smb_svc_pex_cpu1_led 26 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-dimm-c1h1 {
+			label = "LED_ID_DIMM_C1H1";
+			gpios = <&smb_svc_pex_cpu1_led 27 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-dimm-c1a2 {
+			label = "LED_ID_DIMM_C1A2";
+			gpios = <&smb_svc_pex_cpu1_led 28 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-dimm-c1a1 {
+			label = "LED_ID_DIMM_C1A1";
+			gpios = <&smb_svc_pex_cpu1_led 29 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-dimm-c1b2 {
+			label = "LED_ID_DIMM_C1B2";
+			gpios = <&smb_svc_pex_cpu1_led 30 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-dimm-c1b1 {
+			label = "LED_ID_DIMM_C1B1";
+			gpios = <&smb_svc_pex_cpu1_led 31 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-dimm-c1c2 {
+			label = "LED_ID_DIMM_C1C2";
+			gpios = <&smb_svc_pex_cpu1_led 32 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-dimm-c1c1 {
+			label = "LED_ID_DIMM_C1C1";
+			gpios = <&smb_svc_pex_cpu1_led 33 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-dimm-c1d2 {
+			label = "LED_ID_DIMM_C1D2";
+			gpios = <&smb_svc_pex_cpu1_led 34 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-dimm-c1d1 {
+			label = "LED_ID_DIMM_C1D1";
+			gpios = <&smb_svc_pex_cpu1_led 35 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-dimm-c2e2 {
+			label = "LED_ID_DIMM_C2E2";
+			gpios = <&smb_svc_pex_cpu2_led 20 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-dimm-c2e1 {
+			label = "LED_ID_DIMM_C2E1";
+			gpios = <&smb_svc_pex_cpu2_led 21 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-dimm-c2f2 {
+			label = "LED_ID_DIMM_C2F2";
+			gpios = <&smb_svc_pex_cpu2_led 22 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-dimm-c2f1 {
+			label = "LED_ID_DIMM_C2F1";
+			gpios = <&smb_svc_pex_cpu2_led 23 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-dimm-c2g2 {
+			label = "LED_ID_DIMM_C2G2";
+			gpios = <&smb_svc_pex_cpu2_led 24 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-dimm-c2g1 {
+			label = "LED_ID_DIMM_C2G1";
+			gpios = <&smb_svc_pex_cpu2_led 25 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-dimm-c2h2 {
+			label = "LED_ID_DIMM_C2H2";
+			gpios = <&smb_svc_pex_cpu2_led 26 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-dimm-c2h1 {
+			label = "LED_ID_DIMM_C2H1";
+			gpios = <&smb_svc_pex_cpu2_led 27 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-dimm-c2a2 {
+			label = "LED_ID_DIMM_C2A2";
+			gpios = <&smb_svc_pex_cpu2_led 28 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-dimm-c2a1 {
+			label = "LED_ID_DIMM_C2A1";
+			gpios = <&smb_svc_pex_cpu2_led 29 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-dimm-c2b2 {
+			label = "LED_ID_DIMM_C2B2";
+			gpios = <&smb_svc_pex_cpu2_led 30 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-dimm-c2b1 {
+			label = "LED_ID_DIMM_C2B1";
+			gpios = <&smb_svc_pex_cpu2_led 31 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-dimm-c2c2 {
+			label = "LED_ID_DIMM_C2C2";
+			gpios = <&smb_svc_pex_cpu2_led 32 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-dimm-c2c1 {
+			label = "LED_ID_DIMM_C2C1";
+			gpios = <&smb_svc_pex_cpu2_led 33 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-dimm-c2d2 {
+			label = "LED_ID_DIMM_C2D2";
+			gpios = <&smb_svc_pex_cpu2_led 34 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-dimm-c2d1 {
+			label = "LED_ID_DIMM_C2D1";
+			gpios = <&smb_svc_pex_cpu2_led 35 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-dimm-c3e2 {
+			label = "LED_ID_DIMM_C3E2";
+			gpios = <&smb_svc_pex_cpu3_led 20 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-dimm-c3e1 {
+			label = "LED_ID_DIMM_C3E1";
+			gpios = <&smb_svc_pex_cpu3_led 21 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-dimm-c3f2 {
+			label = "LED_ID_DIMM_C3F2";
+			gpios = <&smb_svc_pex_cpu3_led 22 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-dimm-c3f1 {
+			label = "LED_ID_DIMM_C3F1";
+			gpios = <&smb_svc_pex_cpu3_led 23 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-dimm-c3g2 {
+			label = "LED_ID_DIMM_C3G2";
+			gpios = <&smb_svc_pex_cpu3_led 24 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-dimm-c3g1 {
+			label = "LED_ID_DIMM_C3G1";
+			gpios = <&smb_svc_pex_cpu3_led 25 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-dimm-c3h2 {
+			label = "LED_ID_DIMM_C3H2";
+			gpios = <&smb_svc_pex_cpu3_led 26 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-dimm-c3h1 {
+			label = "LED_ID_DIMM_C3H1";
+			gpios = <&smb_svc_pex_cpu3_led 27 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-dimm-c3a2 {
+			label = "LED_ID_DIMM_C3A2";
+			gpios = <&smb_svc_pex_cpu3_led 28 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-dimm-c3a1 {
+			label = "LED_ID_DIMM_C3A1";
+			gpios = <&smb_svc_pex_cpu3_led 29 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-dimm-c3b2 {
+			label = "LED_ID_DIMM_C3B2";
+			gpios = <&smb_svc_pex_cpu3_led 30 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-dimm-c3b1 {
+			label = "LED_ID_DIMM_C3B1";
+			gpios = <&smb_svc_pex_cpu3_led 31 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-dimm-c3c2 {
+			label = "LED_ID_DIMM_C3C2";
+			gpios = <&smb_svc_pex_cpu3_led 32 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-dimm-c3c1 {
+			label = "LED_ID_DIMM_C3C1";
+			gpios = <&smb_svc_pex_cpu3_led 33 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-dimm-c3d2 {
+			label = "LED_ID_DIMM_C3D2";
+			gpios = <&smb_svc_pex_cpu3_led 34 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-dimm-c3d1 {
+			label = "LED_ID_DIMM_C3D1";
+			gpios = <&smb_svc_pex_cpu3_led 35 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-dimm-rssd01 {
+			label = "LED_ID_RSSD01";
+			gpios = <&smb_svc_pex_rssd01_16 0 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-dimm-rssd02 {
+			label = "LED_ID_RSSD02";
+			gpios = <&smb_svc_pex_rssd01_16 1 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-dimm-rssd03 {
+			label = "LED_ID_RSSD03";
+			gpios = <&smb_svc_pex_rssd01_16 2 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-dimm-rssd04 {
+			label = "LED_ID_RSSD04";
+			gpios = <&smb_svc_pex_rssd01_16 3 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-dimm-rssd05 {
+			label = "LED_ID_RSSD05";
+			gpios = <&smb_svc_pex_rssd01_16 4 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-dimm-rssd06 {
+			label = "LED_ID_RSSD06";
+			gpios = <&smb_svc_pex_rssd01_16 5 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-dimm-rssd07 {
+			label = "LED_ID_RSSD07";
+			gpios = <&smb_svc_pex_rssd01_16 6 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-dimm-rssd08 {
+			label = "LED_ID_RSSD08";
+			gpios = <&smb_svc_pex_rssd01_16 7 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-dimm-rssd09 {
+			label = "LED_ID_RSSD09";
+			gpios = <&smb_svc_pex_rssd01_16 8 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-dimm-rssd10 {
+			label = "LED_ID_RSSD10";
+			gpios = <&smb_svc_pex_rssd01_16 9 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-dimm-rssd11 {
+			label = "LED_ID_RSSD11";
+			gpios = <&smb_svc_pex_rssd01_16 10 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-dimm-rssd12 {
+			label = "LED_ID_RSSD12";
+			gpios = <&smb_svc_pex_rssd01_16 11 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-dimm-rssd13 {
+			label = "LED_ID_RSSD13";
+			gpios = <&smb_svc_pex_rssd01_16 12 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-dimm-rssd14 {
+			label = "LED_ID_RSSD14";
+			gpios = <&smb_svc_pex_rssd01_16 13 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-dimm-rssd15 {
+			label = "LED_ID_RSSD15";
+			gpios = <&smb_svc_pex_rssd01_16 14 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-dimm-rssd16 {
+			label = "LED_ID_RSSD16";
+			gpios = <&smb_svc_pex_rssd01_16 15 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-dimm-rssd17 {
+			label = "LED_ID_RSSD17";
+			gpios = <&smb_svc_pex_rssd17_32 0 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-dimm-rssd18 {
+			label = "LED_ID_RSSD18";
+			gpios = <&smb_svc_pex_rssd17_32 1 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-dimm-rssd19 {
+			label = "LED_ID_RSSD19";
+			gpios = <&smb_svc_pex_rssd17_32 2 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-dimm-rssd20 {
+			label = "LED_ID_RSSD20";
+			gpios = <&smb_svc_pex_rssd17_32 3 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-dimm-rssd21 {
+			label = "LED_ID_RSSD21";
+			gpios = <&smb_svc_pex_rssd17_32 4 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-dimm-rssd22 {
+			label = "LED_ID_RSSD22";
+			gpios = <&smb_svc_pex_rssd17_32 5 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-dimm-rssd23 {
+			label = "LED_ID_RSSD23";
+			gpios = <&smb_svc_pex_rssd17_32 6 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-dimm-rssd24 {
+			label = "LED_ID_RSSD24";
+			gpios = <&smb_svc_pex_rssd17_32 7 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-dimm-rssd25 {
+			label = "LED_ID_RSSD25";
+			gpios = <&smb_svc_pex_rssd17_32 8 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-dimm-rssd26 {
+			label = "LED_ID_RSSD26";
+			gpios = <&smb_svc_pex_rssd17_32 9 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-dimm-rssd27 {
+			label = "LED_ID_RSSD27";
+			gpios = <&smb_svc_pex_rssd17_32 10 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-dimm-rssd28 {
+			label = "LED_ID_RSSD28";
+			gpios = <&smb_svc_pex_rssd17_32 11 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-dimm-rssd29 {
+			label = "LED_ID_RSSD29";
+			gpios = <&smb_svc_pex_rssd17_32 12 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-dimm-rssd30 {
+			label = "LED_ID_RSSD30";
+			gpios = <&smb_svc_pex_rssd17_32 13 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-dimm-rssd31 {
+			label = "LED_ID_RSSD31";
+			gpios = <&smb_svc_pex_rssd17_32 14 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-dimm-rssd32 {
+			label = "LED_ID_RSSD32";
+			gpios = <&smb_svc_pex_rssd17_32 15 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-fan-asm01 {
+			label = "LED_ID_FAN_ASM01";
+			gpios = <&smb_svc_pex_rssd01_16 32 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-fan-asm02 {
+			label = "LED_ID_FAN_ASM02";
+			gpios = <&smb_svc_pex_rssd01_16 33 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-fan-asm03 {
+			label = "LED_ID_FAN_ASM03";
+			gpios = <&smb_svc_pex_rssd01_16 34 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-fan-asm04 {
+			label = "LED_ID_FAN_ASM04";
+			gpios = <&smb_svc_pex_rssd01_16 35 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-fan-asm05 {
+			label = "LED_ID_FAN_ASM05";
+			gpios = <&smb_svc_pex_rssd01_16 36 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-fan-asm06 {
+			label = "LED_ID_FAN_ASM06";
+			gpios = <&smb_svc_pex_rssd01_16 37 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-fan-asm07 {
+			label = "LED_ID_FAN_ASM07";
+			gpios = <&smb_svc_pex_rssd17_32 32 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-fan-asm08 {
+			label = "LED_ID_FAN_ASM08";
+			gpios = <&smb_svc_pex_rssd17_32 33 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-fan-asm09 {
+			label = "LED_ID_FAN_ASM09";
+			gpios = <&smb_svc_pex_rssd17_32 34 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-fan-asm10 {
+			label = "LED_ID_FAN_ASM10";
+			gpios = <&smb_svc_pex_rssd17_32 35 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-fan-asm11 {
+			label = "LED_ID_FAN_ASM11";
+			gpios = <&smb_svc_pex_rssd17_32 36 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+
+		led-id-fan-asm12 {
+			label = "LED_ID_FAN_ASM12";
+			gpios = <&smb_svc_pex_rssd17_32 37 GPIO_ACTIVE_LOW>;
+			color = <LED_COLOR_ID_YELLOW>;
+		};
+	};
+
+	iio-hwmon {
+		compatible = "iio-hwmon";
+		io-channels = <&p12v_vd 0>, <&p5v_aux_vd 0>, <&p5v_bmc_aux_vd 0>, <&p3v3_aux_vd 0>,
+			<&p3v3_bmc_aux_vd 0>, <&p1v8_bmc_aux_vd 0>, <&adc1 4>, <&adc0 2>, <&adc1 0>,
+			<&p2V5_aux_vd 0>, <&p3v3_rtc_vd 0>;
+	};
+
+	p12v_vd: voltage-divider1 {
+		compatible = "voltage-divider";
+		io-channels = <&adc1 3>;
+		#io-channel-cells = <1>;
+
+		/*
+		 * Scale the system voltage by 1127/127 to fit the ADC range.
+		 * Use small nominator to prevent integer overflow.
+		 */
+		output-ohms = <15>;
+		full-ohms = <133>;
+	};
+
+	p5v_aux_vd: voltage-divider2 {
+		compatible = "voltage-divider";
+		io-channels = <&adc1 5>;
+		#io-channel-cells = <1>;
+
+		/*
+		 * Scale the system voltage by 1365/365 to fit the ADC range.
+		 * Use small nominator to prevent integer overflow.
+		 */
+		output-ohms = <50>;
+		full-ohms = <187>;
+	};
+
+	p5v_bmc_aux_vd: voltage-divider3 {
+		compatible = "voltage-divider";
+		io-channels = <&adc0 3>;
+		#io-channel-cells = <1>;
+
+		/*
+		 * Scale the system voltage by 1365/365 to fit the ADC range.
+		 * Use small nominator to prevent integer overflow.
+		 */
+		output-ohms = <50>;
+		full-ohms = <187>;
+	};
+
+	p3v3_aux_vd: voltage-divider4 {
+		compatible = "voltage-divider";
+		io-channels = <&adc1 2>;
+		#io-channel-cells = <1>;
+
+		/*
+		 * Scale the system voltage by 1698/698 to fit the ADC range.
+		 * Use small nominator to prevent integer overflow.
+		 */
+		output-ohms = <14>;
+		full-ohms = <34>;
+	};
+
+	p3v3_bmc_aux_vd: voltage-divider5 {
+		compatible = "voltage-divider";
+		io-channels = <&adc0 7>;
+		#io-channel-cells = <1>;
+
+		/*
+		 * Scale the system voltage by 1698/698 to fit the ADC range.
+		 * Use small nominator to prevent integer overflow.
+		 */
+		output-ohms = <14>;
+		full-ohms = <34>;
+	};
+
+	p1v8_bmc_aux_vd: voltage-divider6 {
+		compatible = "voltage-divider";
+		io-channels = <&adc0 6>;
+		#io-channel-cells = <1>;
+
+		/*
+		 * Scale the system voltage by 4000/3000 to fit the ADC range.
+		 * Use small nominator to prevent integer overflow.
+		 */
+		output-ohms = <3>;
+		full-ohms = <4>;
+	};
+
+	p2V5_aux_vd: voltage-divider7 {
+		compatible = "voltage-divider";
+		io-channels = <&adc1 1>;
+		#io-channel-cells = <1>;
+
+		/*
+		 * Scale the system voltage by 2100/1100 to fit the ADC range.
+		 * Use small nominator to prevent integer overflow.
+		 */
+		output-ohms = <11>;
+		full-ohms = <21>;
+	};
+
+	p3v3_rtc_vd: voltage-divider8 {
+		compatible = "voltage-divider";
+		io-channels = <&adc1 7>;
+		#io-channel-cells = <1>;
+
+		/*
+		 * Scale the system voltage by 231000/100000 to fit the ADC range.
+		 * Use small nominator to prevent integer overflow.
+		 */
+		output-ohms = <100>;
+		full-ohms = <231>;
+	};
+
+	thermistor0: thermistor-0 {
+		compatible = "epcos,b57891s0103";
+		pullup-uv = <3300000>;
+		pullup-ohm = <10000>;
+		pulldown-ohm = <0>;
+		io-channels = <&adc0 0>;
+		#thermal-sensor-cells = <0>;
+	};
+
+	thermistor1: thermistor-1 {
+		compatible = "epcos,b57891s0103";
+		pullup-uv = <3300000>;
+		pullup-ohm = <10000>;
+		pulldown-ohm = <0>;
+		io-channels = <&adc0 1>;
+		#thermal-sensor-cells = <0>;
+	};
+
+	thermistor2: thermistor-2 {
+		compatible = "epcos,b57891s0103";
+		pullup-uv = <3300000>;
+		pullup-ohm = <10000>;
+		pulldown-ohm = <0>;
+		io-channels = <&adc0 4>;
+		#thermal-sensor-cells = <0>;
+	};
+
+	thermistor3: thermistor-3 {
+		compatible = "epcos,b57891s0103";
+		pullup-uv = <3300000>;
+		pullup-ohm = <10000>;
+		pulldown-ohm = <0>;
+		io-channels = <&adc0 5>;
+		#thermal-sensor-cells = <0>;
+	};
+
+	p12v: fixedregulator-p12v {
+		compatible = "regulator-fixed";
+		regulator-name = "p12v";
+		regulator-min-microvolt = <12000000>;
+		regulator-max-microvolt = <12000000>;
+		regulator-always-on;
+		regulator-boot-on;
+	};
+
+	p3v3_bmc_aux: fixedregulator-p3v3-bmc-aux {
+		compatible = "regulator-fixed";
+		regulator-name = "p3v3_bmc_aux";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-always-on;
+		regulator-boot-on;
+	};
+
+	p1v8_bmc_aux: fixedregulator-p1v8-bmc-aux {
+		compatible = "regulator-fixed";
+		regulator-name = "p1v8_bmc_aux";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+		regulator-always-on;
+	};
+
+	p1v2_bmc_aux: fixedregulator-p1v2-bmc-aux {
+		compatible = "regulator-fixed";
+		regulator-name = "p1v2_bmc_aux";
+		regulator-min-microvolt = <1200000>;
+		regulator-max-microvolt = <1200000>;
+		regulator-always-on;
+		regulator-boot-on;
+	};
+
+	p12v-a-consumer {
+		compatible = "regulator-output";
+		vout-supply = <&p12v_a>;
+	};
+
+	p12v-b-consumer {
+		compatible = "regulator-output";
+		vout-supply = <&p12v_b>;
+	};
+
+	p12v-c-consumer {
+		compatible = "regulator-output";
+		vout-supply = <&p12v_c>;
+	};
+
+	p12v-d-consumer {
+		compatible = "regulator-output";
+		vout-supply = <&p12v_d>;
+	};
+
+	pvccinfaon-cpu0-consumer {
+		compatible = "regulator-output";
+		vout-supply = <&pvccinfaon_cpu0>;
+	};
+
+	pvccfa-ehv-cpu0-consumer {
+		compatible = "regulator-output";
+		vout-supply = <&pvccfa_ehv_cpu0>;
+	};
+
+	pvnn-main-cpu0-consumer {
+		compatible = "regulator-output";
+		vout-supply = <&pvnn_main_cpu0>;
+	};
+
+	pvccin-cpu0-consumer {
+		compatible = "regulator-output";
+		vout-supply = <&pvccin_cpu0>;
+	};
+
+	pvccfa-ehv-fivra-cpu0-consumer {
+		compatible = "regulator-output";
+		vout-supply = <&pvccfa_ehv_fivra_cpu0>;
+	};
+
+	pvccd-hv-cpu0-consumer {
+		compatible = "regulator-output";
+		vout-supply = <&pvccd_hv_cpu0>;
+	};
+
+	pvpp-hbm-cpu0-consumer {
+		compatible = "regulator-output";
+		vout-supply = <&pvpp_hbm_cpu0>;
+	};
+
+	pvccinfaon-cpu1-consumer {
+		compatible = "regulator-output";
+		vout-supply = <&pvccinfaon_cpu1>;
+	};
+
+	pvccfa-ehv-cpu1-consumer {
+		compatible = "regulator-output";
+		vout-supply = <&pvccfa_ehv_cpu1>;
+	};
+
+	pvnn-main-cpu1-consumer {
+		compatible = "regulator-output";
+		vout-supply = <&pvnn_main_cpu1>;
+	};
+
+	pvccin-cpu1-consumer {
+		compatible = "regulator-output";
+		vout-supply = <&pvccin_cpu1>;
+	};
+
+	pvccfa-ehv-fivra-cpu1-consumer {
+		compatible = "regulator-output";
+		vout-supply = <&pvccfa_ehv_fivra_cpu1>;
+	};
+
+	pvccd-hv-cpu1-consumer {
+		compatible = "regulator-output";
+		vout-supply = <&pvccd_hv_cpu1>;
+	};
+
+	pvpp-hbm-cpu1-consumer {
+		compatible = "regulator-output";
+		vout-supply = <&pvpp_hbm_cpu1>;
+	};
+
+	pvccinfaon-cpu2-consumer {
+		compatible = "regulator-output";
+		vout-supply = <&pvccinfaon_cpu2>;
+	};
+
+	pvccfa-ehv-cpu2-consumer {
+		compatible = "regulator-output";
+		vout-supply = <&pvccfa_ehv_cpu2>;
+	};
+
+	pvnn-main-cpu2-consumer {
+		compatible = "regulator-output";
+		vout-supply = <&pvnn_main_cpu2>;
+	};
+
+	pvccin-cpu2-consumer {
+		compatible = "regulator-output";
+		vout-supply = <&pvccin_cpu2>;
+	};
+
+	pvccfa-ehv-fivra-cpu2-consumer {
+		compatible = "regulator-output";
+		vout-supply = <&pvccfa_ehv_fivra_cpu2>;
+	};
+
+	pvccd-hv-cpu2-consumer {
+		compatible = "regulator-output";
+		vout-supply = <&pvccd_hv_cpu2>;
+	};
+
+	pvpp-hbm-cpu2-consumer {
+		compatible = "regulator-output";
+		vout-supply = <&pvpp_hbm_cpu2>;
+	};
+
+	pvccinfaon-cpu3-consumer {
+		compatible = "regulator-output";
+		vout-supply = <&pvccinfaon_cpu3>;
+	};
+
+	pvccfa-ehv-cpu3-consumer {
+		compatible = "regulator-output";
+		vout-supply = <&pvccfa_ehv_cpu3>;
+	};
+
+	pvnn-main-cpu3-consumer {
+		compatible = "regulator-output";
+		vout-supply = <&pvnn_main_cpu3>;
+	};
+
+	pvccin-cpu3-consumer {
+		compatible = "regulator-output";
+		vout-supply = <&pvccin_cpu3>;
+	};
+
+	pvccfa-ehv-fivra-cpu3-consumer {
+		compatible = "regulator-output";
+		vout-supply = <&pvccfa_ehv_fivra_cpu3>;
+	};
+
+	pvccd-hv-cpu3-consumer {
+		compatible = "regulator-output";
+		vout-supply = <&pvccd_hv_cpu3>;
+	};
+
+	pvpp-hbm-cpu3-consumer {
+		compatible = "regulator-output";
+		vout-supply = <&pvpp_hbm_cpu3>;
+	};
+
+	p1v05-pch-aux-consumer {
+		compatible = "regulator-output";
+		vout-supply = <&p1v05_pch_aux>;
+	};
+
+	p1v8-pch-aux-consumer {
+		compatible = "regulator-output";
+		vout-supply = <&p1v8_pch_aux>;
+	};
+
+	p3v3-pch-consumer {
+		compatible = "regulator-output";
+		vout-supply = <&p3v3_pch>;
+	};
+
+	p5v-consumer {
+		compatible = "regulator-output";
+		vout-supply = <&p5v>;
+	};
+
+	smb-m2-ssb-ssd2 {
+		compatible = "regulator-output";
+		vout-supply = <&sw0_smb_m2_ssb_ssd2>;
+	};
+
+	smb-m2-ssb-ssd1 {
+		compatible = "regulator-output";
+		vout-supply = <&sw0_smb_m2_ssb_ssd1>;
+	};
+
+	ssb-rssd01-sw0 {
+		compatible = "regulator-output";
+		vout-supply = <&sw0_ssb_rssd01>;
+	};
+
+	ssb-rssd01-sw1 {
+		compatible = "regulator-output";
+		vout-supply = <&sw1_ssb_rssd01>;
+	};
+
+	ssb-rssd02-sw0 {
+		compatible = "regulator-output";
+		vout-supply = <&sw0_ssb_rssd02>;
+	};
+
+	ssb-rssd02-sw1 {
+		compatible = "regulator-output";
+		vout-supply = <&sw1_ssb_rssd02>;
+	};
+
+	ssb-rssd03-sw0 {
+		compatible = "regulator-output";
+		vout-supply = <&sw0_ssb_rssd03>;
+	};
+
+	ssb-rssd03-sw1 {
+		compatible = "regulator-output";
+		vout-supply = <&sw1_ssb_rssd03>;
+	};
+
+	ssb-rssd04-sw0 {
+		compatible = "regulator-output";
+		vout-supply = <&sw0_ssb_rssd04>;
+	};
+
+	ssb-rssd04-sw1 {
+		compatible = "regulator-output";
+		vout-supply = <&sw1_ssb_rssd04>;
+	};
+
+	ssb-rssd05-sw0 {
+		compatible = "regulator-output";
+		vout-supply = <&sw0_ssb_rssd05>;
+	};
+
+	ssb-rssd05-sw1 {
+		compatible = "regulator-output";
+		vout-supply = <&sw1_ssb_rssd05>;
+	};
+
+	ssb-rssd06-sw0 {
+		compatible = "regulator-output";
+		vout-supply = <&sw0_ssb_rssd06>;
+	};
+
+	ssb-rssd06-sw1 {
+		compatible = "regulator-output";
+		vout-supply = <&sw1_ssb_rssd06>;
+	};
+
+	ssb-rssd07-sw0 {
+		compatible = "regulator-output";
+		vout-supply = <&sw0_ssb_rssd07>;
+	};
+
+	ssb-rssd07-sw1 {
+		compatible = "regulator-output";
+		vout-supply = <&sw1_ssb_rssd07>;
+	};
+
+	ssb-rssd08-sw0 {
+		compatible = "regulator-output";
+		vout-supply = <&sw0_ssb_rssd08>;
+	};
+
+	ssb-rssd08-sw1 {
+		compatible = "regulator-output";
+		vout-supply = <&sw1_ssb_rssd08>;
+	};
+
+	ssb-rssd09-sw0 {
+		compatible = "regulator-output";
+		vout-supply = <&sw0_ssb_rssd09>;
+	};
+
+	ssb-rssd09-sw1 {
+		compatible = "regulator-output";
+		vout-supply = <&sw1_ssb_rssd09>;
+	};
+
+	ssb-rssd10-sw0 {
+		compatible = "regulator-output";
+		vout-supply = <&sw0_ssb_rssd10>;
+	};
+
+	ssb-rssd10-sw1 {
+		compatible = "regulator-output";
+		vout-supply = <&sw1_ssb_rssd10>;
+	};
+
+	ssb-rssd11-sw0 {
+		compatible = "regulator-output";
+		vout-supply = <&sw0_ssb_rssd11>;
+	};
+
+	ssb-rssd11-sw1 {
+		compatible = "regulator-output";
+		vout-supply = <&sw1_ssb_rssd11>;
+	};
+
+	ssb-rssd12-sw0 {
+		compatible = "regulator-output";
+		vout-supply = <&sw0_ssb_rssd12>;
+	};
+
+	ssb-rssd12-sw1 {
+		compatible = "regulator-output";
+		vout-supply = <&sw1_ssb_rssd12>;
+	};
+
+	ssb-rssd13-sw0 {
+		compatible = "regulator-output";
+		vout-supply = <&sw0_ssb_rssd13>;
+	};
+
+	ssb-rssd13-sw1 {
+		compatible = "regulator-output";
+		vout-supply = <&sw1_ssb_rssd13>;
+	};
+
+	ssb-rssd14-sw0 {
+		compatible = "regulator-output";
+		vout-supply = <&sw0_ssb_rssd14>;
+	};
+
+	ssb-rssd14-sw1 {
+		compatible = "regulator-output";
+		vout-supply = <&sw1_ssb_rssd14>;
+	};
+
+	ssb-rssd15-sw0 {
+		compatible = "regulator-output";
+		vout-supply = <&sw0_ssb_rssd15>;
+	};
+
+	ssb-rssd15-sw1 {
+		compatible = "regulator-output";
+		vout-supply = <&sw1_ssb_rssd15>;
+	};
+
+	ssb-rssd16-sw0 {
+		compatible = "regulator-output";
+		vout-supply = <&sw0_ssb_rssd16>;
+	};
+
+	ssb-rssd16-sw1 {
+		compatible = "regulator-output";
+		vout-supply = <&sw1_ssb_rssd16>;
+	};
+
+	ssb-rssd17-sw0 {
+		compatible = "regulator-output";
+		vout-supply = <&sw0_ssb_rssd17>;
+	};
+
+	ssb-rssd17-sw1 {
+		compatible = "regulator-output";
+		vout-supply = <&sw1_ssb_rssd17>;
+	};
+
+	ssb-rssd18-sw0 {
+		compatible = "regulator-output";
+		vout-supply = <&sw0_ssb_rssd18>;
+	};
+
+	ssb-rssd18-sw1 {
+		compatible = "regulator-output";
+		vout-supply = <&sw1_ssb_rssd18>;
+	};
+
+	ssb-rssd19-sw0 {
+		compatible = "regulator-output";
+		vout-supply = <&sw0_ssb_rssd19>;
+	};
+
+	ssb-rssd19-sw1 {
+		compatible = "regulator-output";
+		vout-supply = <&sw1_ssb_rssd19>;
+	};
+
+	ssb-rssd20-sw0 {
+		compatible = "regulator-output";
+		vout-supply = <&sw0_ssb_rssd20>;
+	};
+
+	ssb-rssd20-sw1 {
+		compatible = "regulator-output";
+		vout-supply = <&sw1_ssb_rssd20>;
+	};
+
+	ssb-rssd21-sw0 {
+		compatible = "regulator-output";
+		vout-supply = <&sw0_ssb_rssd21>;
+	};
+
+	ssb-rssd21-sw1 {
+		compatible = "regulator-output";
+		vout-supply = <&sw1_ssb_rssd21>;
+	};
+
+	ssb-rssd22-sw0 {
+		compatible = "regulator-output";
+		vout-supply = <&sw0_ssb_rssd22>;
+	};
+
+	ssb-rssd22-sw1 {
+		compatible = "regulator-output";
+		vout-supply = <&sw1_ssb_rssd22>;
+	};
+
+	ssb-rssd23-sw0 {
+		compatible = "regulator-output";
+		vout-supply = <&sw0_ssb_rssd23>;
+	};
+
+	ssb-rssd23-sw1 {
+		compatible = "regulator-output";
+		vout-supply = <&sw1_ssb_rssd23>;
+	};
+
+	ssb-rssd24-sw0 {
+		compatible = "regulator-output";
+		vout-supply = <&sw0_ssb_rssd24>;
+	};
+
+	ssb-rssd24-sw1 {
+		compatible = "regulator-output";
+		vout-supply = <&sw1_ssb_rssd24>;
+	};
+
+	ssb-rssd25-sw0 {
+		compatible = "regulator-output";
+		vout-supply = <&sw0_ssb_rssd25>;
+	};
+
+	ssb-rssd25-sw1 {
+		compatible = "regulator-output";
+		vout-supply = <&sw1_ssb_rssd25>;
+	};
+
+	ssb-rssd26-sw0 {
+		compatible = "regulator-output";
+		vout-supply = <&sw0_ssb_rssd26>;
+	};
+
+	ssb-rssd26-sw1 {
+		compatible = "regulator-output";
+		vout-supply = <&sw1_ssb_rssd26>;
+	};
+
+	ssb-rssd27-sw0 {
+		compatible = "regulator-output";
+		vout-supply = <&sw0_ssb_rssd27>;
+	};
+
+	ssb-rssd27-sw1 {
+		compatible = "regulator-output";
+		vout-supply = <&sw1_ssb_rssd27>;
+	};
+
+	ssb-rssd28-sw0 {
+		compatible = "regulator-output";
+		vout-supply = <&sw0_ssb_rssd28>;
+	};
+
+	ssb-rssd28-sw1 {
+		compatible = "regulator-output";
+		vout-supply = <&sw1_ssb_rssd28>;
+	};
+
+	ssb-rssd29-sw0 {
+		compatible = "regulator-output";
+		vout-supply = <&sw0_ssb_rssd29>;
+	};
+
+	ssb-rssd29-sw1 {
+		compatible = "regulator-output";
+		vout-supply = <&sw1_ssb_rssd29>;
+	};
+
+	ssb-rssd30-sw0 {
+		compatible = "regulator-output";
+		vout-supply = <&sw0_ssb_rssd30>;
+	};
+
+	ssb-rssd30-sw1 {
+		compatible = "regulator-output";
+		vout-supply = <&sw1_ssb_rssd30>;
+	};
+
+	ssb-rssd31-sw0 {
+		compatible = "regulator-output";
+		vout-supply = <&sw0_ssb_rssd31>;
+	};
+
+	ssb-rssd31-sw1 {
+		compatible = "regulator-output";
+		vout-supply = <&sw1_ssb_rssd31>;
+	};
+
+	ssb-rssd32-sw0 {
+		compatible = "regulator-output";
+		vout-supply = <&sw0_ssb_rssd32>;
+	};
+
+	ssb-rssd32-sw1 {
+		compatible = "regulator-output";
+		vout-supply = <&sw1_ssb_rssd32>;
+	};
+
+	p3v3-nic-consumer {
+		compatible = "regulator-output";
+		vout-supply = <&p3v3_nic>;
+	};
+
+	p1v8-nic-consumer {
+		compatible = "regulator-output";
+		vout-supply = <&p1v8_nic>;
+	};
+
+	p1v2-nic-consumer {
+		compatible = "regulator-output";
+		vout-supply = <&p1v2_nic>;
+	};
+
+	pvcore-nic1-consumer {
+		compatible = "regulator-output";
+		vout-supply = <&pvcore_nic1>;
+	};
+
+	pvcore-nic2-consumer {
+		compatible = "regulator-output";
+		vout-supply = <&pvcore_nic2>;
+	};
+};
+
+&peci0 {
+	status = "okay";
+};
+
+&vuart1 {
+	status = "okay";
+};
+
+&lpc_snoop {
+	status = "okay";
+	snoop-ports = <0x80>, <0x81>;
+};
+
+&fmc {
+	status = "okay";
+	flash@0 {
+		status = "okay";
+		m25p,fast-read;
+		label = "bmc";
+		spi-tx-bus-width = <1>;
+		spi-rx-bus-width = <4>;
+#include "openbmc-flash-layout-64.dtsi"
+	};
+
+	flash@1 {
+		status = "okay";
+		m25p,fast-read;
+		label = "alt-bmc";
+		spi-tx-bus-width = <1>;
+		spi-rx-bus-width = <4>;
+#include "openbmc-flash-layout-64-alt.dtsi"
+	};
+};
+
+&uart1 {
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_txd1_default
+			&pinctrl_rxd1_default
+			&pinctrl_nrts1_default
+			&pinctrl_ndtr1_default
+			&pinctrl_ndsr1_default
+			&pinctrl_ncts1_default
+			&pinctrl_ndcd1_default
+			&pinctrl_nri1_default>;
+};
+
+&uart5 {
+	status = "disabled";
+};
+
+&gpio1 {
+	status = "disabled";
+};
+
+&video {
+	status = "okay";
+};
+
+&vhub {
+	status = "okay";
+};
+
+&pinctrl {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_vgahs_default &pinctrl_vgavs_default>;
+};
+
+&mdio2 {
+	status = "okay";
+
+	ethphy2: ethernet-phy@0 {
+		compatible = "ethernet-phy-ieee802.3-c22";
+		reg = <0>;
+		reset-gpios = <&gpio0 ASPEED_GPIO(V, 7) GPIO_ACTIVE_LOW>;
+		reset-assert-us = <10000>;
+		reset-deassert-us = <300>;
+	};
+};
+
+&mdio3 {
+	status = "okay";
+
+	ethphy3: ethernet-phy@0 {
+		compatible = "ethernet-phy-ieee802.3-c22";
+		reg = <0>;
+		reset-gpios = <&gpio0 ASPEED_GPIO(G, 2) GPIO_ACTIVE_LOW>;
+		reset-assert-us = <10000>;
+		reset-deassert-us = <300>;
+	};
+};
+
+&mac2 {
+	status = "okay";
+
+	phy-mode = "rgmii";
+	phy-handle = <&ethphy2>;
+
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_rgmii3_default>;
+};
+
+&mac3 {
+	status = "okay";
+
+	phy-mode = "rgmii";
+	phy-handle = <&ethphy3>;
+
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_rgmii4_default>;
+};
+
+&adc0 {
+	status = "okay";
+	vref-supply = <&p1v8_bmc_aux>;
+
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_adc0_default
+		     &pinctrl_adc1_default
+		     &pinctrl_adc2_default
+		     &pinctrl_adc3_default
+		     &pinctrl_adc4_default
+		     &pinctrl_adc5_default
+		     &pinctrl_adc6_default
+		     &pinctrl_adc7_default>;
+};
+
+&adc1 {
+	status = "okay";
+	vref-supply = <&p1v8_bmc_aux>;
+	aspeed,battery-sensing;
+
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_adc8_default
+		     &pinctrl_adc9_default
+		     &pinctrl_adc10_default
+		     &pinctrl_adc11_default
+		     &pinctrl_adc12_default
+		     &pinctrl_adc13_default
+		     &pinctrl_adc15_default>;
+};
+
+&kcs3 {
+	status = "okay";
+	aspeed,lpc-io-reg = <0xca2>;
+};
+
+&gpio0 {
+	status = "okay";
+	gpio-line-names =
+	/* A0 - A7 */
+	"", "", "", "", "", "", "", "",
+	/* B0 - B7 */
+	"", "", "FM_ADR_TRIGGER_R_N", "RST_PLTRST_BUF_N", "BMC_TPM_RESET_N", "BMC_TPM_IRQ_N",
+	"PCH_TPM_RESET_N", "PCH_TPM_IRQ_N",
+	/* C0 - C7 */
+	"", "", "", "", "", "", "", "",
+	/* D0 - D7 */
+	"", "", "", "", "", "", "", "",
+	/* E0 - E7 */
+	"", "", "", "", "", "", "", "",
+	/* F0 - F7 */
+	"", "", "", "BMC_MUX_CPU1_RST_INT_N", "BMC_MUX_CPU2_RST_INT_N", "", "", "",
+	/* G0 - G7 */
+	"FM_SSD_CLK_DRVR1_EN", "FM_CK440Q_DEV_EN", "BMC_MAC1_RESET_N", "FM_DB2000_DEV_EN",
+	"FM_CPU_RMCA_LVT3_N", "FM_CPU_CATERR_LVT3_N", "FM_DBP_PRESENT_N", "",
+	/* H0 - H7 */
+	"SMB_SVC_PEX_RSSD17_32_INT", "LED_BMC_RDY", "RST_DBP_N", "", "", "", "", "",
+	/* I0 - I7 */
+	"JTAG_MUX_MODE_SEL", "JTAG_MUX_TRANS_ENBL", "JTAG_MUX_LSP_SEL5", "JTAG_MUX_MSTR_SEL",
+	"JTAG_MUX_LSP_SEL3", "", "JTAG_MUX_ENBL_N", "JTAG_MUX_RST_N",
+	/* J0 - J7 */
+	"", "", "", "", "", "", "", "",
+	/* K0 - K7 */
+	"", "", "", "", "", "", "", "",
+	/* L0 - L7 */
+	"", "", "", "", "RST_RTCRST_N", "RST_SRTCRST_N", "", "",
+	/* M0 - M7 */
+	"BMC_UART1_CTS_N", "BMC_UART1_DCD_N", "BMC_UART1_DSR_N", "BMC_UART1_RI_N",
+	"BMC_UART1_DTR_N", "BMC_UART1_RTS_N", "", "",
+	/* N0 - N7 */
+	"IRQ_BMC_PCH_NMI", "", "FM_PCH_BMC_THERMTRIP_N", "FM_BIOS_POST_CMPLT_N", "RST_PLTRST_N",
+	"FM_FLASH_SEC_OVRD", "FM_SMI_ACTIVE_N", "PWRGD_DBP",
+	/* O0 - O7 */
+	"CATERR_CPU2_EN", "H_LVT1_THERMTRIP_N", "CATERR_CPU3_EN", "SMB_SVC_PEX_CPU0_LED_INT",
+	"H_LVT1_MEMTRIP_N", "", "CATERR_CPU1_EN", "FM_PCH_ADR_COMPLETE_N",
+	/* P0 - P7 */
+	"PWRGD_SYS_PWROK", "PWRGD_PCH_PWROK", "BMC_MUX_CPU3_RST_INT_N", "BMC_MUX_SVC_RSSD_INT",
+	"FM_SLPS4_N", "IRQ_SML0_ALERT_N", "FM_SLPS3_N", "LED_BMC_HB",
+	/* Q0 - Q7 */
+	"", "PEX_BMC_RST", "PEX_VR_CTRL_RST", "PEX_NIC_RST", "PEX_CPU0_LED_RST", "PEX_CPU1_LED_RST",
+	"PEX_CPU2_LED_RST", "PEX_CPU3_LED_RST",
+	/* R0 - R7 */
+	"BMC_MUX_FANSSB_RSSD17_32_RST_INT_N", "BMC_MUX_FANPWM_RSSD01_16_RST_INT_N",
+	"BMC_MUX_SVC_VR_RST_INT_N", "BMC_MUX_NIC_RST_INT_N", "BMC_MUX_SVC_EXP_RST_INT_N",
+	"FM_CPU_ERR2_LVT3_N", "BMC_MUX_CPU0_RST_INT_N", "BMC_MUX_M2_RST_INT_N",
+	/* S0 - S7 */
+	"SMB_SVC_PEX_RSSD01_16_INT", "RST_PCH_RSMRST_R_N", "", "", "BMC_ROT_FPGA_RESET_N",
+	"FM_SSD_CLK_DRVR0_EN", "", "",
+	/* T0 - T7 */
+	"", "", "", "", "", "", "", "",
+	/* U0 - U7 */
+	"", "", "", "", "", "", "", "",
+	/* V0 - V7 */
+	"BMC_PEX_IRQ_INT", "RTC_BATT_TEST", "SMB_PEX_VR_CTRL_INT", "SMB_SVC_PEX_CPU3_LED_INT",
+	"PWRGD_CPUPWRGD", "SMB_SVC_PEX_CPU2_LED_INT", "SMB_SVC_PEX_CPU1_LED_INT",
+	"BMC_MAC0_RESET_N",
+	/* W0 - W7 */
+	"", "", "", "", "", "", "", "",
+	/* X0 - X7 */
+	"", "", "", "", "", "", "", "",
+	/* Y0 - Y7 */
+	"FM_THROTTLE_N", "FM_PASSWORD_CLEAR_N", "H_LVT3_CATERR_DLY_N", "FM_CPU_OL_INT_R_N", "", "",
+	"", "",
+	/* Z0 - Z7 */
+	"FM_CPU_ERR0_LVT3_N", "FM_CPU_ERR1_LVT3_N", "BMC_MUX_VR_PCH_CPU_RST_INT_N",
+	"JTAG_MUX_LSP_SEL1", "", "JTAG_MUX_LSP_SEL4", "JTAG_MUX_LSP_SEL2", "";
+
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_gpio0_unbiased_default>;
+};
+
+&pinctrl {
+	pinctrl_gpio0_unbiased_default: gpio_default {
+		pins = "AB15", "AD14", "R23", "A18", "AD24", "AD15", "AE14", "AC15", "U25", "AA24",
+		       "V24", "W26", "AA23", "V26", "U24", "V25", "AE15", "C15", "F15";
+		bias-disable;
+	};
+};
+
+&i2c1 {
+	status = "okay";
+
+	bmc_mux_nic: mux@77 {
+		compatible = "maxim,max7357";
+		reg = <0x77>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reset-gpios = <&gpio0 ASPEED_GPIO(R, 3) (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>;
+		vdd-supply = <&p3v3_aux>;
+
+		i2c@0 {
+			reg = <0>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			smb_pex_nic: pinctrl@20 {
+				compatible = "cypress,cy8c9540";
+				reg = <0x20>;
+				gpio-controller;
+				#gpio-cells = <2>;
+
+				interrupt-parent = <&smb_pex_vr_ctrl>;
+				interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+
+				vdd-supply = <&p3v3_aux>;
+				reset-gpios = <&gpio0 ASPEED_GPIO(Q, 3) GPIO_ACTIVE_HIGH>;
+
+				gpio-reserved-ranges = <19 1>, <22 6>, <30 6>, <38 2>;
+
+				gpio-line-names =
+				/* GPORT0 */
+				"IRQ_NIC2_OVT_WRNG", "FM_NIC2_ALLSTANDBY_N", "IRQ_NIC2_OVT_SHTDN",
+				"SMB_VR_PVCORE_NIC2_ALERT_N", "FM_NIC2_PERST1_N",
+				"SMB_NIC2_ALERT_N", "FM_NIC2_PERST3_N", "FM_NIC2_PERST2_N",
+				/* GPORT1 */
+				"FM_NIC1_RST_N", "FM_NIC1_PERST0_N", "FM_NIC1_PERST2_N",
+				"FM_NIC1_PERST3_N", "SMB_NIC1_ALERT_N", "FM_NIC1_PERST1_N",
+				"SMB_VR_PVCORE_NIC1_ALERT_N", "IRQ_NIC1_OVT_SHTDN",
+				/* GPORT2 */
+				"SMB_VR_P3V3_NIC_ALERT_N", "FM_NIC2_FLASH_PRSNT",
+				"FM_NIC1_FLASH_PRSNT", "",
+				/* GPORT3 */
+				"FM_NIC2_PERST0_N", "FM_NIC2_RST_N", "", "", "", "", "", "",
+				/* GPORT4 */
+				"FM_NIC1_ALLSTANDBY_N", "IRQ_NIC1_OVT_WRNG", "", "", "", "", "", "",
+				/* GPORT5 */
+				"SMB_VR_P1V8_NIC_ALERT_N", "SMB_VR_P1V2_NIC_ALERT_N", "", "";
+
+				pinctrl-0 = <&U62160_pins>;
+				pinctrl-names = "default";
+				U62160_pins: cfg-pins {
+					pins = "gp03", "gp16", "gp20", "gp50", "gp51";
+					function = "gpio";
+					input-enable;
+					bias-pull-up;
+				};
+			};
+		};
+
+		i2c@1 {
+			reg = <1>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		i2c@2 {
+			reg = <2>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			pvcore_nic2: ir38263-pvcore-nic2@40 {
+				compatible = "infineon,ir38263";
+				reg = <0x40>;
+
+				regulator-name = "pvcore_nic2";
+				regulator-enable-ramp-delay = <2000>;
+				vin-supply = <&p12v>;
+			};
+		};
+
+		i2c@3 {
+			reg = <3>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			pvcore_nic1: ir38263-pvcore-nic1@40 {
+				compatible = "infineon,ir38263";
+				reg = <0x40>;
+
+				regulator-name = "pvcore_nic1";
+				regulator-enable-ramp-delay = <2000>;
+				vin-supply = <&p12v>;
+			};
+		};
+
+		i2c@4 {
+			reg = <4>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		i2c@5 {
+			reg = <5>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			p3v3_nic: ir38263-p3v3-nic@40 {
+				compatible = "infineon,ir38263";
+				reg = <0x40>;
+
+				regulator-name = "p3v3_nic";
+				regulator-enable-ramp-delay = <2000>;
+				vin-supply = <&p12v>;
+			};
+		};
+
+		i2c@6 {
+			reg = <6>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			p1v2_nic: ir38263-p1v2-nic@40 {
+				compatible = "infineon,ir38263";
+				reg = <0x40>;
+
+				regulator-name = "p1v2_nic";
+				regulator-enable-ramp-delay = <2000>;
+				vin-supply = <&p12v>;
+			};
+		};
+
+		i2c@7 {
+			reg = <7>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			p1v8_nic: ir38263-p1v8-nic@40 {
+				compatible = "infineon,ir38263";
+				reg = <0x40>;
+
+				regulator-name = "p1v8_nic";
+				regulator-enable-ramp-delay = <2000>;
+				vin-supply = <&p12v>;
+			};
+		};
+	};
+};
+
+&i2c2 {
+	status = "okay";
+};
+
+&i2c3 {
+	status = "okay";
+
+	i2cmux1: mux@77 {
+		compatible = "maxim,max7357";
+		reg = <0x77>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		reset-gpios = <&gpio0 ASPEED_GPIO(R, 7) (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>;
+		vdd-supply = <&p3v3_aux>;
+
+		i2c@0 {
+			reg = <0>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		i2c@1 {
+			reg = <1>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		i2c@2 {
+			reg = <2>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		i2c@3 {
+			reg = <3>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			smb_m2_ssb_ssd1: regulator@3a {
+				compatible = "maxim,max5978";
+				reg = <0x3a>;
+				vss1-supply = <&p3v3_aux>;
+
+				interrupt-parent = <&smb_pex_vr_ctrl>;
+				interrupts = <30 IRQ_TYPE_LEVEL_LOW>;
+				leds {
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					led@0 {
+						reg = <0>;
+						label = "m2_ssb_ssd1:green:power";
+						default-state = "off";
+					};
+				};
+
+				regulators {
+					sw0_smb_m2_ssb_ssd1: sw0 {
+						shunt-resistor-micro-ohms = <12000>;
+						regulator-over-current-protection;
+						regulator-oc-protection-microamp = <2800000>;
+						regulator-name = "p3v3_m2_ssd1";
+						regulator-enable-ramp-delay = <10000>;
+					};
+				};
+			};
+		};
+
+		i2c@4 {
+			reg = <4>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		i2c@5 {
+			reg = <5>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			smb_m2_ssb_ssd2: regulator@3a {
+				compatible = "maxim,max5978";
+				reg = <0x3a>;
+
+				interrupt-parent = <&smb_pex_vr_ctrl>;
+				interrupts = <39 IRQ_TYPE_LEVEL_LOW>;
+				vss1-supply = <&p3v3_aux>;
+				leds {
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					led@0 {
+						reg = <0>;
+						label = "m2_ssb_ssd2:green:power";
+						default-state = "off";
+					};
+				};
+
+				regulators {
+					sw0_smb_m2_ssb_ssd2: sw0 {
+						shunt-resistor-micro-ohms = <12000>;
+						regulator-over-current-protection;
+						regulator-oc-protection-microamp = <2800000>;
+						regulator-name = "p3v3_m2_ssd2";
+						regulator-enable-ramp-delay = <10000>;
+					};
+				};
+			};
+		};
+
+		i2c@6 {
+			reg = <1>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		i2c@7 {
+			reg = <1>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+	};
+};
+
+&i2c4 {
+	status = "okay";
+	multi-master;
+	bus-frequency = <1000000>;
+
+	bmc-slave@10 {
+		compatible = "ipmb-dev";
+		reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>;
+
+		i2c-protocol;
+	};
+};
+
+&i2c5 {
+	status = "okay";
+
+	i2cmux2: mux@77 {
+		compatible = "maxim,max7357";
+		reg = <0x77>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		reset-gpios = <&gpio0 ASPEED_GPIO(Z, 2) (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>;
+		vdd-supply = <&p3v3_aux>;
+
+		i2c@1 {
+			reg = <1>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			p1v05_pch_aux: ir38263-p1v05-pch-aux@40 {
+				compatible = "infineon,ir38263";
+				reg = <0x40>;
+
+				regulator-name = "p1v05_pch_aux";
+				regulator-enable-ramp-delay = <2000>;
+				vin-supply = <&p12v>;
+			};
+		};
+
+		i2c@2 {
+			reg = <2>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			p1v8_pch_aux: ir38060-p1v8-pch-aux@40 {
+				compatible = "infineon,ir38060";
+				reg = <0x40>;
+
+				regulator-name = "p1v8_pch_aux";
+				regulator-enable-ramp-delay = <2000>;
+				vin-supply = <&p12v>;
+			};
+		};
+
+		i2c@4 {
+			reg = <4>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		i2c@5 {
+			reg = <5>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		i2c@6 {
+			reg = <6>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		i2c@7 {
+			reg = <7>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+	};
+};
+
+&i2c14 {
+	status = "okay";
+
+	i2cmux13: mux@77 {
+		compatible = "maxim,max7357";
+		reg = <0x77>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		reset-gpios = <&gpio0 ASPEED_GPIO(R, 6) (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>;
+		vdd-supply = <&p3v3_aux>;
+
+		i2c@0 {
+			reg = <0>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			smb_pex_cpu0_event: pinctrl@20 {
+				compatible = "cypress,cy8c9540";
+				reg = <0x20>;
+				gpio-controller;
+				#gpio-cells = <2>;
+
+				interrupt-parent = <&smb_pex_vr_ctrl>;
+				interrupts = <10 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+
+				vdd-supply = <&p3v3_aux>;
+				reset-gpios = <&smb_svc_pex_cpu0_led 16 GPIO_ACTIVE_HIGH>;
+
+				gpio-reserved-ranges = <14 2>, <21 1>, <25 3>, <33 1>;
+
+				gpio-line-names =
+				/* GPORT0 */
+				"PWRGD_CHD_CPU0", "PWRGD_CHC_CPU0",
+				"PWRGD_CHB_CPU0", "PWRGD_CHA_CPU0",
+				"PWRGD_CHE_CPU0", "PWRGD_CHF_CPU0",
+				"PWRGD_CHG_CPU0", "PWRGD_CHH_CPU0",
+				/* GPORT1 */
+				"SMB_VR_PVPP_HBM_CPU0_ALERT_N", "SMB_VR_PVCCINFAON_CPU0_ALERT_N",
+				"SMB_VR_PVNN_MAIN_CPU0_ALERT_N", "SMB_VR_PVCCD_HV_CPU0_ALERT_N",
+				"SMB_VR_PVCCIN_CPU0_ALERT_N", "SEL_SMB_DIMM_CPU0",
+				"", "",
+				/* GPORT2 */
+				"PWRGD_LVC3_CPU0_AB_DRAM_G", "PWRGD_LVC3_CPU0_CD_DRAM_G",
+				"PWRGD_LVC3_CPU0_EF_DRAM_G", "PWRGD_LVC3_CPU0_GH_DRAM_G",
+				/* GPORT3 */
+				"FM_CPU0_DISABLE_COD_N", "",
+				"RST_LVC3_CPU0_RESET_N", "PWRGD_LVC3_CPU0_PWRGOOD",
+				"PWRGD_PLT_AUX_CPU0_LVT3", "",
+				"", "",
+				/* GPORT4 */
+				"H_LVT3_CPU0_PROCHOT_N", "H_LVT3_CPU0_MEMHOT_IN_N",
+				"H_LVT3_CPU0_MEMHOT_OUT_N", "H_LVT3_CPU0_MEMTRIP_OUT_N",
+				"H_LVT3_CPU0_THERMTRIP_OUT_N", "",
+				"H_LVT3_CPU0_NMI", "FM_S3M_CPU0_CD_INIT_ERROR",
+				/* GPORT5 */
+				"FM_CPU0_PKG_ID0", "FM_CPU0_PKG_ID1",
+				"FM_CPU0_PROC_ID0", "FM_CPU0_PROC_ID1";
+
+				pinctrl-0 = <&U62080_pins>;
+				pinctrl-names = "default";
+				U62080_pins: cfg-pins {
+					pins = "gp10", "gp11", "gp12", "gp13", "gp14";
+					function = "gpio";
+					input-enable;
+					bias-pull-up;
+				};
+			};
+		};
+
+		i2c@1 {
+			reg = <1>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		i2c@2 {
+			reg = <2>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			pvccinfaon-pvccfa-cpu0@58 {
+				compatible = "mps,mp2971";
+				reg = <0x58>;
+				interrupt-parent = <&smb_pex_cpu0_event>;
+				interrupts = <9 IRQ_TYPE_LEVEL_LOW>;
+
+				regulators {
+					pvccinfaon_cpu0: vout0 {
+						regulator-name = "pvccinfaon_cpu0";
+						regulator-enable-ramp-delay = <200>;
+					};
+					pvccfa_ehv_cpu0: vout1 {
+						regulator-name = "pvccfa_ehv_cpu0";
+						regulator-enable-ramp-delay = <200>;
+					};
+				};
+			};
+			tda38640-pvnn-main-cpu0@40 {
+				compatible = "infineon,tda38640";
+				reg = <0x40>;
+				interrupt-parent = <&smb_pex_cpu0_event>;
+				interrupts = <10 IRQ_TYPE_LEVEL_LOW>;
+
+				regulators {
+					pvnn_main_cpu0: vout {
+						regulator-name = "pvnn_main_cpu0";
+						regulator-enable-ramp-delay = <200>;
+					};
+				};
+			};
+		};
+
+		i2c@3 {
+			reg = <3>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			mp2973-pvccin-pvccfa-cpu0@58 {
+				compatible = "mps,mp2973";
+				reg = <0x58>;
+				interrupt-parent = <&smb_pex_cpu0_event>;
+				interrupts = <12 IRQ_TYPE_LEVEL_LOW>;
+
+				regulators {
+					pvccin_cpu0: vout0 {
+						regulator-name = "pvccin_cpu0";
+						regulator-enable-ramp-delay = <200>;
+					};
+					pvccfa_ehv_fivra_cpu0: vout1 {
+						regulator-name = "pvccfa_ehv_fivra_cpu0";
+						regulator-enable-ramp-delay = <200>;
+					};
+				};
+			};
+		};
+
+		i2c@4 {
+			reg = <4>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			tda38640-pvccd-hv-cpu0@40 {
+				compatible = "infineon,tda38640";
+				reg = <0x40>;
+				interrupt-parent = <&smb_pex_cpu0_event>;
+				interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
+				infineon,en-pin-fixed-level;
+
+				regulators {
+					pvccd_hv_cpu0: vout {
+						regulator-name = "pvccd_hv_cpu0";
+						regulator-enable-ramp-delay = <200>;
+					};
+				};
+			};
+		};
+
+		i2c@5 {
+			reg = <5>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			tda38640-pvpp-hbm-cpu0@40 {
+				compatible = "infineon,tda38640";
+				reg = <0x40>;
+				interrupt-parent = <&smb_pex_cpu0_event>;
+				interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
+
+				regulators {
+					pvpp_hbm_cpu0: vout {
+						regulator-name = "pvpp_hbm_cpu0";
+						regulator-enable-ramp-delay = <200>;
+					};
+				};
+			};
+		};
+
+		i2c@6 {
+			reg = <6>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		i2c@7 {
+			reg = <7>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+	};
+};
+
+&i2c7 {
+	status = "okay";
+
+	i2cmux4: mux@77 {
+		compatible = "maxim,max7357";
+		reg = <0x77>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		reset-gpios = <&gpio0 ASPEED_GPIO(F, 3) (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>;
+		vdd-supply = <&p3v3_aux>;
+
+		i2c@0 {
+			reg = <0>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			smb_pex_cpu1_event: pinctrl@20 {
+				compatible = "cypress,cy8c9540";
+				reg = <0x20>;
+				gpio-controller;
+				#gpio-cells = <2>;
+
+				interrupt-parent = <&smb_pex_vr_ctrl>;
+				interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+
+				vdd-supply = <&p3v3_aux>;
+				reset-gpios = <&smb_svc_pex_cpu1_led 16 GPIO_ACTIVE_HIGH>;
+
+				gpio-reserved-ranges = <14 2>, <21 1>, <25 3>, <33 1>;
+
+				gpio-line-names =
+				/* GPORT0 */
+				"PWRGD_CHD_CPU1", "PWRGD_CHC_CPU1",
+				"PWRGD_CHB_CPU1", "PWRGD_CHA_CPU1",
+				"PWRGD_CHE_CPU1", "PWRGD_CHF_CPU1",
+				"PWRGD_CHG_CPU1", "PWRGD_CHH_CPU1",
+				/* GPORT1 */
+				"SMB_VR_PVPP_HBM_CPU1_ALERT_N", "SMB_VR_PVCCINFAON_CPU1_ALERT_N",
+				"SMB_VR_PVNN_MAIN_CPU1_ALERT_N", "SMB_VR_PVCCD_HV_CPU1_ALERT_N",
+				"SMB_VR_PVCCIN_CPU1_ALERT_N", "SEL_SMB_DIMM_CPU1",
+				"", "",
+				/* GPORT2 */
+				"PWRGD_LVC3_CPU1_AB_DRAM_G", "PWRGD_LVC3_CPU1_CD_DRAM_G",
+				"PWRGD_LVC3_CPU1_EF_DRAM_G", "PWRGD_LVC3_CPU1_GH_DRAM_G",
+				/* GPORT3 */
+				"FM_CPU1_DISABLE_COD_N", "",
+				"RST_LVC3_CPU1_RESET_N", "PWRGD_LVC3_CPU1_PWRGOOD",
+				"PWRGD_PLT_AUX_CPU1_LVT3", "",
+				"", "",
+				/* GPORT4 */
+				"H_LVT3_CPU1_PROCHOT_N", "H_LVT3_CPU1_MEMHOT_IN_N",
+				"H_LVT3_CPU1_MEMHOT_OUT_N", "H_LVT3_CPU1_MEMTRIP_OUT_N",
+				"H_LVT3_CPU1_THERMTRIP_OUT_N", "",
+				"H_LVT3_CPU1_NMI", "FM_S3M_CPU1_CD_INIT_ERROR",
+				/* GPORT5 */
+				"FM_CPU1_PKG_ID0", "FM_CPU1_PKG_ID1",
+				"FM_CPU1_PROC_ID0", "FM_CPU1_PROC_ID1";
+
+				pinctrl-0 = <&U62090_pins>;
+				pinctrl-names = "default";
+				U62090_pins: cfg-pins {
+					pins = "gp10", "gp11", "gp12", "gp13", "gp14";
+					function = "gpio";
+					input-enable;
+					bias-pull-up;
+				};
+			};
+		};
+
+		i2c@1 {
+			reg = <1>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		i2c@2 {
+			reg = <2>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			pvccinfaon-pvccfa-cpu1@58 {
+				compatible = "mps,mp2971";
+				reg = <0x58>;
+				interrupt-parent = <&smb_pex_cpu1_event>;
+				interrupts = <9 IRQ_TYPE_LEVEL_LOW>;
+
+				regulators {
+					pvccinfaon_cpu1: vout0 {
+						regulator-name = "pvccinfaon_cpu1";
+						regulator-enable-ramp-delay = <200>;
+					};
+					pvccfa_ehv_cpu1: vout1 {
+						regulator-name = "pvccfa_ehv_cpu1";
+						regulator-enable-ramp-delay = <200>;
+					};
+				};
+			};
+			tda38640-pvnn-main-cpu1@40 {
+				compatible = "infineon,tda38640";
+				reg = <0x40>;
+				interrupt-parent = <&smb_pex_cpu1_event>;
+				interrupts = <10 IRQ_TYPE_LEVEL_LOW>;
+
+				regulators {
+					pvnn_main_cpu1: vout {
+						regulator-name = "pvnn_main_cpu1";
+						regulator-enable-ramp-delay = <200>;
+					};
+				};
+			};
+		};
+
+		i2c@3 {
+			reg = <3>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			mp2973-pvccin-pvccfa-cpu1@58 {
+				compatible = "mps,mp2973";
+				reg = <0x58>;
+				interrupt-parent = <&smb_pex_cpu1_event>;
+				interrupts = <12 IRQ_TYPE_LEVEL_LOW>;
+
+				regulators {
+					pvccin_cpu1: vout0 {
+						regulator-name = "pvccin_cpu1";
+						regulator-enable-ramp-delay = <200>;
+					};
+					pvccfa_ehv_fivra_cpu1: vout1 {
+						regulator-name = "pvccfa_ehv_fivra_cpu1";
+						regulator-enable-ramp-delay = <200>;
+					};
+				};
+			};
+		};
+
+		i2c@4 {
+			reg = <4>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			tda38640-pvccd-hv-cpu1@40 {
+				compatible = "infineon,tda38640";
+				reg = <0x40>;
+				interrupt-parent = <&smb_pex_cpu1_event>;
+				interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
+				infineon,en-pin-fixed-level;
+
+				regulators {
+					pvccd_hv_cpu1: vout {
+						regulator-name = "pvccd_hv_cpu1";
+						regulator-enable-ramp-delay = <200>;
+					};
+				};
+			};
+		};
+
+		i2c@5 {
+			reg = <5>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			tda38640-pvpp-hbm-cpu1@40 {
+				compatible = "infineon,tda38640";
+				reg = <0x40>;
+				interrupt-parent = <&smb_pex_cpu1_event>;
+				interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
+
+				regulators {
+					pvpp_hbm_cpu1: vout {
+						regulator-name = "pvpp_hbm_cpu1";
+						regulator-enable-ramp-delay = <200>;
+					};
+				};
+			};
+		};
+
+		i2c@6 {
+			reg = <6>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		i2c@7 {
+			reg = <7>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+	};
+};
+
+&i2c6 {
+	status = "okay";
+
+	i2cmux3: mux@77 {
+		compatible = "maxim,max7357";
+		reg = <0x77>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		vdd-supply = <&p3v3_aux>;
+
+		i2c@0 {
+			reg = <0>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			smb_pex_cpu2_event: pinctrl@20 {
+				compatible = "cypress,cy8c9540";
+				reg = <0x20>;
+				gpio-controller;
+				#gpio-cells = <2>;
+
+				interrupt-parent = <&smb_pex_vr_ctrl>;
+				interrupts = <3 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+
+				vdd-supply = <&p3v3_aux>;
+				reset-gpios = <&smb_svc_pex_cpu2_led 16 GPIO_ACTIVE_HIGH>;
+
+				gpio-reserved-ranges = <14 2>, <21 1>, <25 3>, <33 1>;
+
+				gpio-line-names =
+				/* GPORT0 */
+				"PWRGD_CHD_CPU2", "PWRGD_CHC_CPU2",
+				"PWRGD_CHB_CPU2", "PWRGD_CHA_CPU2",
+				"PWRGD_CHE_CPU2", "PWRGD_CHF_CPU2",
+				"PWRGD_CHG_CPU2", "PWRGD_CHH_CPU2",
+				/* GPORT1 */
+				"SMB_VR_PVPP_HBM_CPU2_ALERT_N", "SMB_VR_PVCCINFAON_CPU2_ALERT_N",
+				"SMB_VR_PVNN_MAIN_CPU2_ALERT_N", "SMB_VR_PVCCD_HV_CPU2_ALERT_N",
+				"SMB_VR_PVCCIN_CPU2_ALERT_N", "SEL_SMB_DIMM_CPU2",
+				"", "",
+				/* GPORT2 */
+				"PWRGD_LVC3_CPU2_AB_DRAM_G", "PWRGD_LVC3_CPU2_CD_DRAM_G",
+				"PWRGD_LVC3_CPU2_EF_DRAM_G", "PWRGD_LVC3_CPU2_GH_DRAM_G",
+				/* GPORT3 */
+				"FM_CPU2_DISABLE_COD_N", "",
+				"RST_LVC3_CPU2_RESET_N", "PWRGD_LVC3_CPU2_PWRGOOD",
+				"PWRGD_PLT_AUX_CPU2_LVT3", "",
+				"", "",
+				/* GPORT4 */
+				"H_LVT3_CPU2_PROCHOT_N", "H_LVT3_CPU2_MEMHOT_IN_N",
+				"H_LVT3_CPU2_MEMHOT_OUT_N", "H_LVT3_CPU2_MEMTRIP_OUT_N",
+				"H_LVT3_CPU2_THERMTRIP_OUT_N", "",
+				"H_LVT3_CPU2_NMI", "FM_S3M_CPU2_CD_INIT_ERROR",
+				/* GPORT5 */
+				"FM_CPU2_PKG_ID0", "FM_CPU2_PKG_ID1",
+				"FM_CPU2_PROC_ID0", "FM_CPU2_PROC_ID1";
+
+				pinctrl-0 = <&U62100_pins>;
+				pinctrl-names = "default";
+				U62100_pins: cfg-pins {
+					pins = "gp10", "gp11", "gp12", "gp13", "gp14";
+					function = "gpio";
+					input-enable;
+					bias-pull-up;
+				};
+			};
+		};
+
+		i2c@1 {
+			reg = <1>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		i2c@2 {
+			reg = <2>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			pvccinfaon-pvccfa-cpu2@58 {
+				compatible = "mps,mp2971";
+				reg = <0x58>;
+				interrupt-parent = <&smb_pex_cpu2_event>;
+				interrupts = <9 IRQ_TYPE_LEVEL_LOW>;
+
+				regulators {
+					pvccinfaon_cpu2: vout0 {
+						regulator-name = "pvccinfaon_cpu2";
+						regulator-enable-ramp-delay = <200>;
+					};
+					pvccfa_ehv_cpu2: vout1 {
+						regulator-name = "pvccfa_ehv_cpu2";
+						regulator-enable-ramp-delay = <200>;
+					};
+				};
+			};
+			tda38640-pvnn-main-cpu2@40 {
+				compatible = "infineon,tda38640";
+				reg = <0x40>;
+				interrupt-parent = <&smb_pex_cpu2_event>;
+				interrupts = <10 IRQ_TYPE_LEVEL_LOW>;
+
+				regulators {
+					pvnn_main_cpu2: vout {
+						regulator-name = "pvnn_main_cpu2";
+						regulator-enable-ramp-delay = <200>;
+					};
+				};
+			};
+		};
+
+		i2c@3 {
+			reg = <3>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			mp2973-pvccin-pvccfa-cpu2@58 {
+				compatible = "mps,mp2973";
+				reg = <0x58>;
+				interrupt-parent = <&smb_pex_cpu2_event>;
+				interrupts = <12 IRQ_TYPE_LEVEL_LOW>;
+
+				regulators {
+					pvccin_cpu2: vout0 {
+						regulator-name = "pvccin_cpu2";
+						regulator-enable-ramp-delay = <200>;
+					};
+					pvccfa_ehv_fivra_cpu2: vout1 {
+						regulator-name = "pvccfa_ehv_fivra_cpu2";
+						regulator-enable-ramp-delay = <200>;
+					};
+				};
+			};
+		};
+
+		i2c@4 {
+			reg = <4>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			tda38640-pvccd-hv-cpu2@40 {
+				compatible = "infineon,tda38640";
+				reg = <0x40>;
+				interrupt-parent = <&smb_pex_cpu2_event>;
+				interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
+				infineon,en-pin-fixed-level;
+
+				regulators {
+					pvccd_hv_cpu2: vout {
+						regulator-name = "pvccd_hv_cpu2";
+						regulator-enable-ramp-delay = <200>;
+					};
+				};
+			};
+		};
+
+		i2c@5 {
+			reg = <5>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			tda38640-pvpp-hbm-cpu2@40 {
+				compatible = "infineon,tda38640";
+				reg = <0x40>;
+				interrupt-parent = <&smb_pex_cpu2_event>;
+				interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
+
+				regulators {
+					pvpp_hbm_cpu2: vout {
+						regulator-name = "pvpp_hbm_cpu2";
+						regulator-enable-ramp-delay = <200>;
+					};
+				};
+			};
+		};
+
+		i2c@6 {
+			reg = <6>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		i2c@7 {
+			reg = <7>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+	};
+};
+
+&i2c12 {
+	status = "okay";
+
+	i2cmux22: mux@77 {
+		compatible = "maxim,max7357";
+		reg = <0x77>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		reset-gpios = <&gpio0 ASPEED_GPIO(P, 2) (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>;
+		vdd-supply = <&p3v3_aux>;
+
+		i2c@0 {
+			reg = <0>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			smb_pex_cpu3_event: pinctrl@20 {
+				compatible = "cypress,cy8c9540";
+				reg = <0x20>;
+				gpio-controller;
+				#gpio-cells = <2>;
+
+				interrupt-parent = <&smb_pex_vr_ctrl>;
+				interrupts = <11 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+
+				vdd-supply = <&p3v3_aux>;
+				reset-gpios = <&smb_svc_pex_cpu3_led 16 GPIO_ACTIVE_HIGH>;
+
+				gpio-reserved-ranges = <14 2>, <21 1>, <25 3>, <33 1>;
+
+				gpio-line-names =
+				/* GPORT0 */
+				"PWRGD_CHD_CPU3", "PWRGD_CHC_CPU3",
+				"PWRGD_CHB_CPU3", "PWRGD_CHA_CPU3",
+				"PWRGD_CHE_CPU3", "PWRGD_CHF_CPU3",
+				"PWRGD_CHG_CPU3", "PWRGD_CHH_CPU3",
+				/* GPORT1 */
+				"SMB_VR_PVPP_HBM_CPU3_ALERT_N", "SMB_VR_PVCCINFAON_CPU3_ALERT_N",
+				"SMB_VR_PVNN_MAIN_CPU3_ALERT_N", "SMB_VR_PVCCD_HV_CPU3_ALERT_N",
+				"SMB_VR_PVCCIN_CPU3_ALERT_N", "SEL_SMB_DIMM_CPU3",
+				"", "",
+				/* GPORT2 */
+				"PWRGD_LVC3_CPU3_AB_DRAM_G", "PWRGD_LVC3_CPU3_CD_DRAM_G",
+				"PWRGD_LVC3_CPU3_EF_DRAM_G", "PWRGD_LVC3_CPU3_GH_DRAM_G",
+				/* GPORT3 */
+				"FM_CPU3_DISABLE_COD_N", "",
+				"RST_LVC3_CPU3_RESET_N", "PWRGD_LVC3_CPU3_PWRGOOD",
+				"PWRGD_PLT_AUX_CPU3_LVT3", "",
+				"", "",
+				/* GPORT4 */
+				"H_LVT3_CPU3_PROCHOT_N", "H_LVT3_CPU3_MEMHOT_IN_N",
+				"H_LVT3_CPU3_MEMHOT_OUT_N", "H_LVT3_CPU3_MEMTRIP_OUT_N",
+				"H_LVT3_CPU3_THERMTRIP_OUT_N", "",
+				"H_LVT3_CPU3_NMI", "FM_S3M_CPU3_CD_INIT_ERROR",
+				/* GPORT5 */
+				"FM_CPU3_PKG_ID0", "FM_CPU3_PKG_ID1",
+				"FM_CPU3_PROC_ID0", "FM_CPU3_PROC_ID1";
+
+				pinctrl-0 = <&U62110_pins>;
+				pinctrl-names = "default";
+				U62110_pins: cfg-pins {
+					pins = "gp10", "gp11", "gp12", "gp13", "gp14";
+					function = "gpio";
+					input-enable;
+					bias-pull-up;
+				};
+			};
+		};
+
+		i2c@1 {
+			reg = <1>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		i2c@2 {
+			reg = <2>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			pvccinfaon-pvccfa-cpu3@58 {
+				compatible = "mps,mp2971";
+				reg = <0x58>;
+				interrupt-parent = <&smb_pex_cpu3_event>;
+				interrupts = <9 IRQ_TYPE_LEVEL_LOW>;
+
+				regulators {
+					pvccinfaon_cpu3: vout0 {
+						regulator-name = "pvccinfaon_cpu3";
+						regulator-enable-ramp-delay = <200>;
+					};
+					pvccfa_ehv_cpu3: vout1 {
+						regulator-name = "pvccfa_ehv_cpu3";
+						regulator-enable-ramp-delay = <200>;
+					};
+				};
+			};
+			tda38640-pvnn-main-cpu3@40 {
+				compatible = "infineon,tda38640";
+				reg = <0x40>;
+				interrupt-parent = <&smb_pex_cpu3_event>;
+				interrupts = <10 IRQ_TYPE_LEVEL_LOW>;
+
+				regulators {
+					pvnn_main_cpu3: vout {
+						regulator-name = "pvnn_main_cpu3";
+						regulator-enable-ramp-delay = <200>;
+					};
+				};
+			};
+		};
+
+		i2c@3 {
+			reg = <3>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			mp2973-pvccin-pvccfa-cpu3@58 {
+				compatible = "mps,mp2973";
+				reg = <0x58>;
+				interrupt-parent = <&smb_pex_cpu3_event>;
+				interrupts = <12 IRQ_TYPE_LEVEL_LOW>;
+
+				regulators {
+					pvccin_cpu3: vout0 {
+						regulator-name = "pvccin_cpu3";
+						regulator-enable-ramp-delay = <200>;
+					};
+					pvccfa_ehv_fivra_cpu3: vout1 {
+						regulator-name = "pvccfa_ehv_fivra_cpu3";
+						regulator-enable-ramp-delay = <200>;
+					};
+				};
+			};
+		};
+
+		i2c@4 {
+			reg = <4>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			tda38640-pvccd-hv-cpu3@40 {
+				compatible = "infineon,tda38640";
+				reg = <0x40>;
+				interrupt-parent = <&smb_pex_cpu3_event>;
+				interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
+				infineon,en-pin-fixed-level;
+
+				regulators {
+					pvccd_hv_cpu3: vout {
+						regulator-name = "pvccd_hv_cpu3";
+						regulator-enable-ramp-delay = <200>;
+					};
+				};
+			};
+		};
+
+		i2c@5 {
+			reg = <5>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			tda38640-pvpp-hbm-cpu3@40 {
+				compatible = "infineon,tda38640";
+				reg = <0x40>;
+				interrupt-parent = <&smb_pex_cpu3_event>;
+				interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
+
+				regulators {
+					pvpp_hbm_cpu3: vout {
+						regulator-name = "pvpp_hbm_cpu3";
+						regulator-enable-ramp-delay = <200>;
+					};
+				};
+			};
+		};
+
+		i2c@6 {
+			reg = <6>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		i2c@7 {
+			reg = <7>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+	};
+};
+
+&i2c15 {
+	status = "okay";
+
+	i2cmux14: mux@77 {
+		compatible = "maxim,max7357";
+		reg = <0x77>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		reset-gpios = <&gpio0 ASPEED_GPIO(R, 1) (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>;
+		vdd-supply = <&p3v3_aux>;
+
+		i2c@0 {
+			reg = <0>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			i2cmux15: mux@70 {
+				compatible = "maxim,max7357";
+				reg = <0x70>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				reset-gpios = <&bmc_pex_irq 11 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>;
+				vdd-supply = <&p3v3_aux>;
+			};
+		};
+
+		i2c@1 {
+			reg = <1>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			i2cmux16: mux@70 {
+				compatible = "maxim,max7357";
+				reg = <0x70>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				reset-gpios = <&bmc_pex_irq 2 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>;
+				vdd-supply = <&p3v3_aux>;
+			};
+		};
+
+		i2c@2 {
+			reg = <2>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			i2cmux17: mux@70 {
+				compatible = "maxim,max7357";
+				reg = <0x70>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				reset-gpios = <&bmc_pex_irq 0 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>;
+				vdd-supply = <&p3v3_aux>;
+			};
+		};
+
+		i2c@3 {
+			reg = <3>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			i2cmux18: mux@70 {
+				compatible = "maxim,max7357";
+				reg = <0x70>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				reset-gpios = <&bmc_pex_irq 3 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>;
+				vdd-supply = <&p3v3_aux>;
+			};
+		};
+
+		i2c@4 {
+			reg = <4>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			i2cmux19: mux@70 {
+				compatible = "maxim,max7357";
+				reg = <0x70>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				reset-gpios = <&bmc_pex_irq 9 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>;
+				vdd-supply = <&p3v3_aux>;
+			};
+		};
+
+		i2c@5 {
+			reg = <5>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			smb_pex_rssd17_32: pinctrl@20 {
+				compatible = "cypress,cy8c9560";
+				reg = <0x20>;
+				gpio-controller;
+				#gpio-cells = <2>;
+
+				interrupt-parent = <&bmc_pex_irq>;
+				interrupts = <13 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+
+				vdd-supply = <&p3v3_aux>;
+				reset-gpios = <&bmc_pex_irq 19 GPIO_ACTIVE_HIGH>;
+
+				gpio-reserved-ranges = <48 12>;
+
+				gpio-line-names =
+				/* GPORT0 */
+				"RSSD17_SMBRST_N", "RSSD18_SMBRST_N",
+				"RSSD19_SMBRST_N", "RSSD20_SMBRST_N",
+				"RSSD21_SMBRST_N", "RSSD22_SMBRST_N",
+				"RSSD23_SMBRST_N", "RSSD24_SMBRST_N",
+				/* GPORT1 */
+				"RSSD25_SMBRST_N", "RSSD26_SMBRST_N",
+				"RSSD27_SMBRST_N", "RSSD28_SMBRST_N",
+				"RSSD29_SMBRST_N", "RSSD30_SMBRST_N",
+				"RSSD31_SMBRST_N", "RSSD32_SMBRST_N",
+				/* GPORT2 */
+				"RSSD17_PWRDIS", "RSSD18_PWRDIS",
+				"RSSD19_PWRDIS", "RSSD20_PWRDIS",
+				/* GPORT3 */
+				"RSSD21_PWRDIS", "RSSD22_PWRDIS",
+				"RSSD23_PWRDIS", "RSSD24_PWRDIS",
+				"RSSD25_PWRDIS", "RSSD26_PWRDIS",
+				"RSSD27_PWRDIS", "RSSD28_PWRDIS",
+				/* GPORT4 */
+				"RSSD29_PWRDIS", "RSSD30_PWRDIS",
+				"RSSD31_PWRDIS", "RSSD32_PWRDIS",
+				"RSSD17_RESET_N", "RSSD18_RESET_N",
+				"RSSD19_RESET_N", "RSSD20_RESET_N",
+				/* GPORT5 */
+				"RSSD21_RESET_N", "RSSD22_RESET_N",
+				"RSSD23_RESET_N", "RSSD24_RESET_N",
+				"RSSD25_RESET_N", "RSSD26_RESET_N",
+				"RSSD27_RESET_N", "RSSD28_RESET_N",
+				/* GPORT6 */
+				"RSSD29_RESET_N", "RSSD30_RESET_N",
+				"RSSD31_RESET_N", "RSSD32_RESET_N",
+				"", "",
+				"", "",
+				/* GPORT7 */
+				"", "",
+				"", "",
+				"", "",
+				"", "";
+			};
+		};
+
+		i2c@6 {
+			reg = <6>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			i2cmux20: mux@70 {
+				compatible = "maxim,max7357";
+				reg = <0x70>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				reset-gpios = <&bmc_pex_irq 4 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>;
+				vdd-supply = <&p3v3_aux>;
+
+				i2c@0 {
+					reg = <0>;
+					#address-cells = <1>;
+					#size-cells = <0>;
+				};
+				i2c@1 {
+					reg = <1>;
+					#address-cells = <1>;
+					#size-cells = <0>;
+				};
+				i2c@2 {
+					reg = <2>;
+					#address-cells = <1>;
+					#size-cells = <0>;
+				};
+				i2c@3 {
+					reg = <3>;
+					#address-cells = <1>;
+					#size-cells = <0>;
+				};
+				i2c@4 {
+					reg = <4>;
+					#address-cells = <1>;
+					#size-cells = <0>;
+				};
+				i2c@5 {
+					reg = <5>;
+					#address-cells = <1>;
+					#size-cells = <0>;
+				};
+				i2c@6 {
+					reg = <6>;
+					#address-cells = <1>;
+					#size-cells = <0>;
+				};
+				i2c@7 {
+					reg = <7>;
+					#address-cells = <1>;
+					#size-cells = <0>;
+				};
+			};
+		};
+
+		i2c@7 {
+			reg = <7>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			i2cmux21: mux@70 {
+				compatible = "maxim,max7357";
+				reg = <0x70>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				reset-gpios = <&bmc_pex_irq 5 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>;
+				vdd-supply = <&p3v3_aux>;
+
+				i2c@0 {
+					reg = <0>;
+					#address-cells = <1>;
+					#size-cells = <0>;
+				};
+				i2c@1 {
+					reg = <1>;
+					#address-cells = <1>;
+					#size-cells = <0>;
+				};
+				i2c@2 {
+					reg = <2>;
+					#address-cells = <1>;
+					#size-cells = <0>;
+				};
+				i2c@3 {
+					reg = <3>;
+					#address-cells = <1>;
+					#size-cells = <0>;
+				};
+				i2c@4 {
+					reg = <4>;
+					#address-cells = <1>;
+					#size-cells = <0>;
+				};
+				i2c@5 {
+					reg = <5>;
+					#address-cells = <1>;
+					#size-cells = <0>;
+				};
+				i2c@6 {
+					reg = <6>;
+					#address-cells = <1>;
+					#size-cells = <0>;
+				};
+				i2c@7 {
+					reg = <7>;
+					#address-cells = <1>;
+					#size-cells = <0>;
+				};
+			};
+		};
+	};
+};
+
+&i2c8 {
+	status = "okay";
+
+	i2cmux5: mux@77 {
+		compatible = "maxim,max7357";
+		reg = <0x77>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		reset-gpios = <&gpio0 ASPEED_GPIO(R, 0) (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>;
+		vdd-supply = <&p3v3_aux>;
+
+		i2c@0 {
+			reg = <0>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			i2cmux6: mux@70 {
+				compatible = "maxim,max7357";
+				reg = <0x70>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				reset-gpios = <&bmc_pex_irq 16 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>;
+				vdd-supply = <&p3v3_aux>;
+			};
+		};
+
+		i2c@1 {
+			reg = <1>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			i2cmux7: mux@70 {
+				compatible = "maxim,max7357";
+				reg = <0x70>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				reset-gpios = <&bmc_pex_irq 7 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>;
+				vdd-supply = <&p3v3_aux>;
+			};
+		};
+
+		i2c@2 {
+			reg = <2>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			i2cmux8: mux@70 {
+				compatible = "maxim,max7357";
+				reg = <0x70>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				reset-gpios = <&bmc_pex_irq 1 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>;
+				vdd-supply = <&p3v3_aux>;
+			};
+		};
+
+		i2c@3 {
+			reg = <3>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			i2cmux9: mux@70 {
+				compatible = "maxim,max7357";
+				reg = <0x70>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				reset-gpios = <&bmc_pex_irq 10 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>;
+				vdd-supply = <&p3v3_aux>;
+			};
+		};
+
+		i2c@4 {
+			reg = <4>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			i2cmux10: mux@70 {
+				compatible = "maxim,max7357";
+				reg = <0x70>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				reset-gpios = <&bmc_pex_irq 15 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>;
+				vdd-supply = <&p3v3_aux>;
+			};
+		};
+
+		i2c@5 {
+			reg = <5>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			smb_pex_rssd_01_16: pinctrl@20 {
+				compatible = "cypress,cy8c9560";
+				reg = <0x20>;
+				gpio-controller;
+				#gpio-cells = <2>;
+
+				interrupt-parent = <&bmc_pex_irq>;
+				interrupts = <6 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+
+				vdd-supply = <&p3v3_aux>;
+				reset-gpios = <&bmc_pex_irq 18 GPIO_ACTIVE_HIGH>;
+
+				gpio-reserved-ranges = <48 12>;
+
+				gpio-line-names =
+				/* GPORT0 */
+				"RSSD01_SMBRST_N", "RSSD02_SMBRST_N",
+				"RSSD03_SMBRST_N", "RSSD04_SMBRST_N",
+				"RSSD05_SMBRST_N", "RSSD06_SMBRST_N",
+				"RSSD07_SMBRST_N", "RSSD08_SMBRST_N",
+				/* GPORT1 */
+				"RSSD09_SMBRST_N", "RSSD10_SMBRST_N",
+				"RSSD11_SMBRST_N", "RSSD12_SMBRST_N",
+				"RSSD13_SMBRST_N", "RSSD14_SMBRST_N",
+				"RSSD15_SMBRST_N", "RSSD16_SMBRST_N",
+				/* GPORT2 */
+				"RSSD01_PWRDIS", "RSSD02_PWRDIS",
+				"RSSD03_PWRDIS", "RSSD04_PWRDIS",
+				/* GPORT3 */
+				"RSSD05_PWRDIS", "RSSD06_PWRDIS",
+				"RSSD07_PWRDIS", "RSSD08_PWRDIS",
+				"RSSD09_PWRDIS", "RSSD10_PWRDIS",
+				"RSSD11_PWRDIS", "RSSD12_PWRDIS",
+				/* GPORT4 */
+				"RSSD13_PWRDIS", "RSSD14_PWRDIS",
+				"RSSD15_PWRDIS", "RSSD16_PWRDIS",
+				"RSSD01_RESET_N", "RSSD02_RESET_N",
+				"RSSD03_RESET_N", "RSSD04_RESET_N",
+				/* GPORT5 */
+				"RSSD05_RESET_N", "RSSD06_RESET_N",
+				"RSSD07_RESET_N", "RSSD08_RESET_N",
+				"RSSD09_RESET_N", "RSSD10_RESET_N",
+				"RSSD11_RESET_N", "RSSD12_RESET_N",
+				/* GPORT6 */
+				"RSSD13_RESET_N", "RSSD14_RESET_N",
+				"RSSD15_RESET_N", "RSSD16_RESET_N",
+				"", "",
+				"", "",
+				/* GPORT7 */
+				"", "",
+				"", "",
+				"", "",
+				"", "";
+			};
+		};
+
+		i2c@6 {
+			reg = <6>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			i2cmux11: mux@70 {
+				compatible = "maxim,max7357";
+				reg = <0x70>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				reset-gpios = <&bmc_pex_irq 12 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>;
+				vdd-supply = <&p3v3_aux>;
+
+				i2c@0 {
+					reg = <0>;
+					#address-cells = <1>;
+					#size-cells = <0>;
+				};
+				i2c@1 {
+					reg = <1>;
+					#address-cells = <1>;
+					#size-cells = <0>;
+				};
+				i2c@2 {
+					reg = <2>;
+					#address-cells = <1>;
+					#size-cells = <0>;
+				};
+				i2c@3 {
+					reg = <3>;
+					#address-cells = <1>;
+					#size-cells = <0>;
+				};
+				i2c@4 {
+					reg = <4>;
+					#address-cells = <1>;
+					#size-cells = <0>;
+				};
+				i2c@5 {
+					reg = <5>;
+					#address-cells = <1>;
+					#size-cells = <0>;
+				};
+				i2c@6 {
+					reg = <6>;
+					#address-cells = <1>;
+					#size-cells = <0>;
+				};
+				i2c@7 {
+					reg = <7>;
+					#address-cells = <1>;
+					#size-cells = <0>;
+				};
+			};
+		};
+
+		i2c@7 {
+			reg = <7>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			i2cmux12: mux@70 {
+				compatible = "maxim,max7357";
+				reg = <0x70>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				reset-gpios = <&bmc_pex_irq 14 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>;
+				vdd-supply = <&p3v3_aux>;
+
+				i2c@0 {
+					reg = <0>;
+					#address-cells = <1>;
+					#size-cells = <0>;
+				};
+				i2c@1 {
+					reg = <1>;
+					#address-cells = <1>;
+					#size-cells = <0>;
+				};
+				i2c@2 {
+					reg = <2>;
+					#address-cells = <1>;
+					#size-cells = <0>;
+				};
+				i2c@3 {
+					reg = <3>;
+					#address-cells = <1>;
+					#size-cells = <0>;
+				};
+				i2c@4 {
+					reg = <4>;
+					#address-cells = <1>;
+					#size-cells = <0>;
+				};
+				i2c@5 {
+					reg = <5>;
+					#address-cells = <1>;
+					#size-cells = <0>;
+				};
+				i2c@6 {
+					reg = <6>;
+					#address-cells = <1>;
+					#size-cells = <0>;
+				};
+				i2c@7 {
+					reg = <7>;
+					#address-cells = <1>;
+					#size-cells = <0>;
+				};
+			};
+		};
+	};
+};
+
+&i2c13 {
+	status = "okay";
+
+	i2cmux23: mux@77 {
+		compatible = "maxim,max7357";
+		reg = <0x77>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		reset-gpios = <&gpio0 ASPEED_GPIO(R, 4) (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>;
+		vdd-supply = <&p3v3_bmc_aux>;
+	};
+};
+
+&i2cmux23 {
+	i2c@0 {
+		reg = <0>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		smb_pex_vr_ctrl: pinctrl@20 {
+			compatible = "cypress,cy8c9540";
+			reg = <0x20>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			interrupt-parent = <&gpio0>;
+			interrupts = <ASPEED_GPIO(V, 2) IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			vdd-supply = <&p3v3_bmc_aux>;
+			reset-gpios = <&gpio0 ASPEED_GPIO(Q, 2) GPIO_ACTIVE_HIGH>;
+			gpio-line-names =
+			/* GPORT0 */
+			"BCM0_INPUT_DISABLE_N", "SMB_VR_P3V3_AUX_ALERT_N",
+			"SMB_PEX_CPU1_EVENT_INT", "SMB_PEX_CPU2_EVENT_INT",
+			"DPIC0_VOLTAGE_DETECTB_N", "DPIC0_VOLTAGE_DETECTA_N",
+			"DPIC1_VOLTAGE_DETECTA_N", "DPIC1_VOLTAGE_DETECTB_N",
+			/* GPORT1 */
+			"SMB_PEX_NIC_INT", "SMB_VR_P1V05_PCH_AUX_ALERT_N",
+			"SMB_PEX_CPU0_EVENT_INT", "SMB_PEX_CPU3_EVENT_INT",
+			"LED_ID_TPM", "PLUG_DETECT_TPM",
+			"PLUG_DETECT_M2_SSD_CARRIER1", "RST_M2_SSD1_PERST_N",
+			/* GPORT2 */
+			"LED_ID_BAT", "LED_ID_MGMT_PORT2",
+			"LED_ID_MGMT_PORT1", "SMB_VR_P5V_AUX_ALERT_N",
+			/* GPORT3 */
+			"SMB_VR_AUX_SSB_ALERT_N", "BCM1_INPUT_DISABLE_N",
+			"LED_ID_NIC1_PORT1", "LED_ID_NIC1_PORT2",
+			"LED_ID_NIC2_PORT1", "LED_ID_NIC2_PORT2",
+			"RST_M2_SSD2_PERST_N", "PLUG_DETECT_M2_SSD2",
+			/* GPORT4 */
+			"PLUG_DETECT_BAT", "PLUG_DETECT_M2_SSD1",
+			"M2_SSD1_SSB_ALERT_N", "BCM2_INPUT_DISABLE_N",
+			"SMB_VR_P1V8_PCH_AUX_ALERT_N", "BCM3_INPUT_DISABLE_N",
+			"LED_PWR_DWR_BACK", "LED_ID_DWR_BACK_P",
+			/* GPORT5 */
+			"LED_ID_M2_SSD2", "LED_ID_M2_SSD1",
+			"PLUG_DETECT_M2_SSD_CARRIER2", "M2_SSD2_SSB_ALERT_N";
+
+			pinctrl-0 = <&U62120_input &U62120_input_pullup>;
+			pinctrl-names = "default";
+			U62120_input: input-pins {
+				pins = "gp10";
+				function = "gpio";
+				input-enable;
+				bias-disable;
+			};
+			U62120_input_pullup: input-pullup-pins {
+				pins = "gp01", "gp02", "gp03", "gp11", "gp12", "gp13",
+				"gp23", "gp30", "gp40", "gp42", "gp44", "gp53";
+				function = "gpio";
+				input-enable;
+				bias-pull-up;
+			};
+		};
+	};
+	i2c@1 {
+		reg = <1>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		bmc_pex_irq: pinctrl@20 {
+			compatible = "cypress,cy8c9520";
+			reg = <0x20>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			interrupt-parent = <&gpio0>;
+			interrupts = <ASPEED_GPIO(V, 0) IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			vdd-supply = <&p3v3_aux>;
+			reset-gpios = <&gpio0 ASPEED_GPIO(Q, 1) GPIO_ACTIVE_HIGH>;
+			gpio-line-names =
+			/* GPORT0 */
+			"SMB_MUX_PWM_FANGRP2_RST_INT_N", "SMB_MUX_SSB_FANGRP2_RST_INT_N",
+			"SMB_MUX_PWM_FANGRP1_RST_INT_N", "SMB_MUX_SSB_RSSD01_08_RST_INT_N",
+			"SMB_MUX_RSSD01_08_RST_INT_N", "SMB_MUX_RSSD09_16_RST_INT_N",
+			"SMB_PEX_RSSD01_16_INT", "SMB_MUX_SSB_FANGRP1_RST_INT_N",
+			/* GPORT1 */
+			"SMB_SVC_PEX_FAN_ALERT_INT", "SMB_MUX_SSB_RSSD09_16_RST_INT_N",
+			"SMB_MUX_SSB_RSSD17_24_RST_INT_N", "SMB_MUX_PWM_FANGRP0_RST_INT_N",
+			"SMB_MUX_RSSD17_24_RST_INT_N", "SMB_PEX_RSSD17_32_INT",
+			"SMB_MUX_RSSD25_32_RST_INT_N", "SMB_MUX_SSB_RSSD25_32_RST_INT_N",
+			/* GPORT2 */
+			"SMB_MUX_SSB_FANGRP0_RST_INT_N", "PEX_FAN_ALERT_RST",
+			"PEX_RSSD01_16_RST", "PEX_RSSD17_32_RST";
+			pinctrl-0 = <&U60000_pins>;
+			pinctrl-names = "default";
+			U60000_pins: cfg-pins {
+				pins = "gp06", "gp10", "gp15";
+				function = "gpio";
+				input-enable;
+				bias-disable;
+			};
+		};
+	};
+	i2c@2 {
+		reg = <2>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		i2cmux24: mux@70 {
+			compatible = "maxim,max7357";
+			reg = <0x70>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			vdd-supply = <&p3v3_bmc_aux>;
+		};
+	};
+	i2c@3 {
+		reg = <3>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		eeprom@51 {
+			compatible = "atmel,24c32";
+			reg = <0x51>;
+			pagesize = <32>;
+			vcc-supply = <&p3v3_bmc_aux>;
+		};
+	};
+	i2c@7 {
+		reg = <7>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		i2cmux25: mux@70 {
+			compatible = "maxim,max7357";
+			reg = <0x70>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+	};
+};
+
+&i2cmux25 {
+	reset-gpios = <&gpio0 ASPEED_GPIO(R, 2) (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>;
+	vdd-supply = <&p3v3_bmc_aux>;
+	i2c@1 {
+		reg = <1>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		p5v_aux: ir38263-p5v-aux@40 {
+			compatible = "infineon,ir38263";
+			reg = <0x40>;
+
+			regulator-name = "p5v_aux";
+			regulator-enable-ramp-delay = <2000>;
+			vin-supply = <&p12v>;
+			vbus-supply = <&p3v3_bmc_aux>;
+			regulator-always-on;
+			regulator-boot-on;
+		};
+	};
+	i2c@2 {
+		reg = <2>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		p3v3_aux: ir38263-p3v3-aux@40 {
+			compatible = "infineon,ir38263";
+			reg = <0x40>;
+
+			vin-supply = <&p12v>;
+			regulator-name = "p3v3_aux";
+			/*
+			 * 2msec for regulator + 18msec for board capacitance
+			 * Note: Every IC has a PTC which slowly charges the bypass
+			 * cap.
+			 */
+			regulator-enable-ramp-delay = <200000>;
+		};
+	};
+	i2c@3 {
+		reg = <3>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		aux_ssb: regulator@3a {
+			compatible = "maxim,max5970";
+			reg = <0x3a>;
+			interrupt-parent = <&smb_pex_vr_ctrl>;
+			interrupts = <20 IRQ_TYPE_LEVEL_LOW>;
+			vss1-supply = <&p5v_aux>;
+			vss2-supply = <&p3v3_aux>;
+			regulators {
+				p5v: sw0 {
+					regulator-name = "p5v";
+					shunt-resistor-micro-ohms = <12000>;
+					regulator-over-current-protection;
+					regulator-oc-protection-microamp = <3400000>;
+					regulator-enable-ramp-delay = <100000>;
+				};
+				p3v3_pch: sw1 {
+					regulator-name = "p3v3_pch";
+					shunt-resistor-micro-ohms = <12000>;
+					regulator-over-current-protection;
+					regulator-oc-protection-microamp = <3400000>;
+					regulator-enable-ramp-delay = <100000>;
+				};
+			};
+		};
+	};
+	i2c@4 {
+		reg = <4>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		pli1209bc_p12v_a: regulator@5f {
+			compatible = "vicor,pli1209bc";
+			reg = <0x5f>;
+			regulators {
+				p12v_a: vout2 {
+					regulator-name = "bcm0";
+					regulator-boot-on;
+				};
+			};
+		};
+	};
+	i2c@5 {
+		reg = <5>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		pli1209bc_p12v_b: regulator@5f {
+			compatible = "vicor,pli1209bc";
+			reg = <0x5f>;
+			regulators {
+				p12v_b: vout2 {
+					regulator-name = "bcm1";
+					regulator-boot-on;
+				};
+			};
+		};
+	};
+	i2c@6 {
+		reg = <6>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		pli1209bc_p12v_c: regulator@5f {
+			compatible = "vicor,pli1209bc";
+			reg = <0x5f>;
+			regulators {
+				p12v_c: vout2 {
+					regulator-name = "bcm2";
+					regulator-boot-on;
+				};
+			};
+		};
+	};
+	i2c@7 {
+		reg = <7>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		pli1209bc_p12v_d: regulator@5f {
+			compatible = "vicor,pli1209bc";
+			reg = <0x5f>;
+			regulators {
+				p12v_d: vout2 {
+					regulator-name = "bcm3";
+					regulator-boot-on;
+				};
+			};
+		};
+	};
+};
+
+&i2cmux24 {
+
+	reset-gpios = <&gpio0 ASPEED_GPIO(P, 3) (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>;
+
+	i2c@0 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <0>;
+		smb_svc_pex_rssd01_16: pinctrl@20 {
+			compatible = "cypress,cy8c9560";
+			reg = <0x20>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			interrupt-parent = <&gpio0>;
+			interrupts = <ASPEED_GPIO(S, 0) IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			vdd-supply = <&p3v3_bmc_aux>;
+			reset-gpios = <&smb_svc_pex_cpu0_led 17 GPIO_ACTIVE_HIGH>;
+			gpio-line-names =
+			/* GPORT0 */
+			"LED_ID_RSSD01", "LED_ID_RSSD02",
+			"LED_ID_RSSD03", "LED_ID_RSSD04",
+			"LED_ID_RSSD05", "LED_ID_RSSD06",
+			"LED_ID_RSSD07", "LED_ID_RSSD08",
+			/* GPORT1 */
+			"LED_ID_RSSD09", "LED_ID_RSSD10",
+			"LED_ID_RSSD11", "LED_ID_RSSD12",
+			"LED_ID_RSSD13", "LED_ID_RSSD14",
+			"LED_ID_RSSD15", "LED_ID_RSSD16",
+			/* GPORT2 */
+			"RSSD01_PRESENT_N", "RSSD02_PRESENT_N",
+			"RSSD03_PRESENT_N", "RSSD04_PRESENT_N",
+			/* GPORT3 */
+			"RSSD05_PRESENT_N", "RSSD06_PRESENT_N",
+			"RSSD07_PRESENT_N", "RSSD08_PRESENT_N",
+			"RSSD09_PRESENT_N", "RSSD10_PRESENT_N",
+			"RSSD11_PRESENT_N", "RSSD12_PRESENT_N",
+			/* GPORT4 */
+			"RSSD13_PRESENT_N", "RSSD14_PRESENT_N",
+			"RSSD15_PRESENT_N", "RSSD16_PRESENT_N",
+			"LED_ID_FAN_ASM01", "LED_ID_FAN_ASM02",
+			"LED_ID_FAN_ASM03", "LED_ID_FAN_ASM04",
+			/* GPORT5 */
+			"LED_ID_FAN_ASM05", "LED_ID_FAN_ASM06",
+			"PLUG_DETECT_FAN_ASM01", "PLUG_DETECT_FAN_ASM02",
+			"PLUG_DETECT_FAN_ASM03", "PLUG_DETECT_FAN_ASM04",
+			"PLUG_DETECT_FAN_ASM05", "PLUG_DETECT_FAN_ASM06",
+			/* GPORT6 */
+			"SSB_RSSD01_ALERT_N", "SSB_RSSD02_ALERT_N",
+			"SSB_RSSD03_ALERT_N", "SSB_RSSD04_ALERT_N",
+			"SSB_RSSD05_ALERT_N", "SSB_RSSD06_ALERT_N",
+			"SSB_RSSD07_ALERT_N", "SSB_RSSD08_ALERT_N",
+			/* GPORT7 */
+			"SSB_RSSD09_ALERT_N", "SSB_RSSD10_ALERT_N",
+			"SSB_RSSD11_ALERT_N", "SSB_RSSD12_ALERT_N",
+			"SSB_RSSD13_ALERT_N", "SSB_RSSD14_ALERT_N",
+			"SSB_RSSD15_ALERT_N", "SSB_RSSD16_ALERT_N";
+			pinctrl-0 = <&U65200_pins>;
+			pinctrl-names = "default";
+			U65200_pins: cfg-pins {
+				pins =  "gp60", "gp61", "gp62",
+				"gp63", "gp64", "gp65", "gp66",
+				"gp67", "gp70", "gp71", "gp72",
+				"gp73", "gp74", "gp75", "gp76", "gp77";
+				function = "gpio";
+				input-enable;
+				bias-pull-up;
+			};
+		};
+	};
+	i2c@1 {
+		reg = <1>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		smb_svc_pex_rssd17_32: pinctrl@20 {
+			compatible = "cypress,cy8c9560";
+			reg = <0x20>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			interrupt-parent = <&gpio0>;
+			interrupts = <ASPEED_GPIO(H, 0) IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			vdd-supply = <&p3v3_bmc_aux>;
+			reset-gpios = <&smb_svc_pex_cpu1_led 17 GPIO_ACTIVE_HIGH>;
+			gpio-line-names =
+			/* GPORT0 */
+			"LED_ID_RSSD17", "LED_ID_RSSD18",
+			"LED_ID_RSSD19", "LED_ID_RSSD20",
+			"LED_ID_RSSD21", "LED_ID_RSSD22",
+			"LED_ID_RSSD23", "LED_ID_RSSD24",
+			/* GPORT1 */
+			"LED_ID_RSSD25", "LED_ID_RSSD26",
+			"LED_ID_RSSD27", "LED_ID_RSSD28",
+			"LED_ID_RSSD29", "LED_ID_RSSD30",
+			"LED_ID_RSSD31", "LED_ID_RSSD32",
+			/* GPORT2 */
+			"RSSD17_PRESENT_N", "RSSD18_PRESENT_N",
+			"RSSD19_PRESENT_N", "RSSD20_PRESENT_N",
+			/* GPORT3 */
+			"RSSD21_PRESENT_N", "RSSD22_PRESENT_N",
+			"RSSD23_PRESENT_N", "RSSD24_PRESENT_N",
+			"RSSD25_PRESENT_N", "RSSD26_PRESENT_N",
+			"RSSD27_PRESENT_N", "RSSD28_PRESENT_N",
+			/* GPORT4 */
+			"RSSD29_PRESENT_N", "RSSD30_PRESENT_N",
+			"RSSD31_PRESENT_N", "RSSD32_PRESENT_N",
+			"LED_ID_FAN_ASM07", "LED_ID_FAN_ASM08",
+			"LED_ID_FAN_ASM09", "LED_ID_FAN_ASM10",
+			/* GPORT5 */
+			"LED_ID_FAN_ASM11", "LED_ID_FAN_ASM12",
+			"PLUG_DETECT_FAN_ASM07", "PLUG_DETECT_FAN_ASM08",
+			"PLUG_DETECT_FAN_ASM09", "PLUG_DETECT_FAN_ASM10",
+			"PLUG_DETECT_FAN_ASM11", "PLUG_DETECT_FAN_ASM12",
+			/* GPORT6 */
+			"SSB_RSSD17_ALERT_N", "SSB_RSSD18_ALERT_N",
+			"SSB_RSSD19_ALERT_N", "SSB_RSSD20_ALERT_N",
+			"SSB_RSSD21_ALERT_N", "SSB_RSSD22_ALERT_N",
+			"SSB_RSSD23_ALERT_N", "SSB_RSSD24_ALERT_N",
+			/* GPORT7 */
+			"SSB_RSSD25_ALERT_N", "SSB_RSSD26_ALERT_N",
+			"SSB_RSSD27_ALERT_N", "SSB_RSSD28_ALERT_N",
+			"SSB_RSSD29_ALERT_N", "SSB_RSSD30_ALERT_N",
+			"SSB_RSSD31_ALERT_N", "SSB_RSSD32_ALERT_N";
+			pinctrl-0 = <&U65300_pins>;
+			pinctrl-names = "default";
+			U65300_pins: cfg-pins {
+				pins = "gp60", "gp61", "gp62",
+				"gp63", "gp64", "gp65", "gp66",
+				"gp67", "gp70", "gp71", "gp72",
+				"gp73", "gp74", "gp75", "gp76",
+				"gp77";
+				function = "gpio";
+				input-enable;
+				bias-pull-up;
+			};
+		};
+	};
+	i2c@2 {
+		reg = <2>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		smb_svc_pex_cpu1_led: pinctrl@20 {
+			compatible = "cypress,cy8c9540";
+			reg = <0x20>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			interrupt-parent = <&gpio0>;
+			interrupts = <ASPEED_GPIO(V, 6) IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			vdd-supply = <&p3v3_bmc_aux>;
+			reset-gpios = <&gpio0 ASPEED_GPIO(Q, 5) GPIO_ACTIVE_HIGH>;
+			gpio-reserved-ranges = <18 2>, <36 2>;
+			gpio-line-names =
+			/* GPORT0 */
+			"PLUG_DETECT_DIMM_C1E2", "PLUG_DETECT_DIMM_C1E1",
+			"PLUG_DETECT_DIMM_C1F2", "PLUG_DETECT_DIMM_C1F1",
+			"PLUG_DETECT_DIMM_C1G2", "PLUG_DETECT_DIMM_C1G1",
+			"PLUG_DETECT_DIMM_C1H2", "PLUG_DETECT_DIMM_C1H1",
+			/* GPORT1 */
+			"PLUG_DETECT_DIMM_C1D1", "PLUG_DETECT_DIMM_C1D2",
+			"PLUG_DETECT_DIMM_C1C1", "PLUG_DETECT_DIMM_C1C2",
+			"PLUG_DETECT_DIMM_C1B1", "PLUG_DETECT_DIMM_C1B2",
+			"PLUG_DETECT_DIMM_C1A1", "PLUG_DETECT_DIMM_C1A2",
+			/* GPORT2 */
+			"PEX_CPU1_EVENT_RST", "SVC_PEX_RSSD17_32_RST",
+			"", "",
+			/* GPORT3 */
+			"LED_ID_DIMM_C1E2", "LED_ID_DIMM_C1E1",
+			"LED_ID_DIMM_C1F2", "LED_ID_DIMM_C1F1",
+			"LED_ID_DIMM_C1G2", "LED_ID_DIMM_C1G1",
+			"LED_ID_DIMM_C1H2", "LED_ID_DIMM_C1H1",
+			/* GPORT4 */
+			"LED_ID_DIMM_C1A2", "LED_ID_DIMM_C1A1",
+			"LED_ID_DIMM_C1B2", "LED_ID_DIMM_C1B1",
+			"LED_ID_DIMM_C1C2", "LED_ID_DIMM_C1C1",
+			"LED_ID_DIMM_C1D2", "LED_ID_DIMM_C1D1",
+			/* GPORT5 */
+			"", "",
+			"FM_CPU1_SKTOCC_N", "LED_ID_CPU1";
+		};
+	};
+	i2c@3 {
+		reg = <3>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		smb_svc_pex_fan_alert: pinctrl@20 {
+			compatible = "cypress,cy8c9560";
+			reg = <0x20>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			interrupt-parent = <&bmc_pex_irq>;
+			interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			vdd-supply = <&p3v3_aux>;
+			reset-gpios = <&bmc_pex_irq 17 GPIO_ACTIVE_HIGH>;
+			gpio-reserved-ranges = <24 3>, <51 9>;
+			gpio-line-names =
+			/* GPORT0 */
+			"FAN01_SSB_ALERT_N", "FAN02_SSB_ALERT_N",
+			"FAN03_SSB_ALERT_N", "FAN04_SSB_ALERT_N",
+			"FAN05_SSB_ALERT_N", "FAN06_SSB_ALERT_N",
+			"FAN07_SSB_ALERT_N", "FAN08_SSB_ALERT_N",
+			/* GPORT1 */
+			"FAN09_SSB_ALERT_N", "FAN10_SSB_ALERT_N",
+			"FAN11_SSB_ALERT_N", "FAN12_SSB_ALERT_N",
+			"FAN13_SSB_ALERT_N", "FAN14_SSB_ALERT_N",
+			"FAN15_SSB_ALERT_N", "FAN16_SSB_ALERT_N",
+			/* GPORT2 */
+			"FAN17_SSB_ALERT_N", "FAN18_SSB_ALERT_N",
+			"FAN19_SSB_ALERT_N", "FAN20_SSB_ALERT_N",
+			/* GPORT3 */
+			"FAN21_SSB_ALERT_N", "FAN22_SSB_ALERT_N",
+			"FAN23_SSB_ALERT_N", "FAN24_SSB_ALERT_N",
+			"", "",
+			"", "FAN01_PWM_ALERT_N",
+			/* GPORT4 */
+			"FAN02_PWM_ALERT_N", "FAN03_PWM_ALERT_N",
+			"FAN04_PWM_ALERT_N", "FAN05_PWM_ALERT_N",
+			"FAN06_PWM_ALERT_N", "FAN07_PWM_ALERT_N",
+			"FAN08_PWM_ALERT_N", "FAN09_PWM_ALERT_N",
+			/* GPORT5 */
+			"FAN10_PWM_ALERT_N", "FAN11_PWM_ALERT_N",
+			"FAN12_PWM_ALERT_N", "FAN13_PWM_ALERT_N",
+			"FAN14_PWM_ALERT_N", "FAN15_PWM_ALERT_N",
+			"FAN16_PWM_ALERT_N", "FAN17_PWM_ALERT_N",
+			/* GPORT6 */
+			"FAN18_PWM_ALERT_N", "FAN19_PWM_ALERT_N",
+			"FAN20_PWM_ALERT_N", "FAN21_PWM_ALERT_N",
+			"FAN22_PWM_ALERT_N", "FAN23_PWM_ALERT_N",
+			"FAN24_PWM_ALERT_N", "",
+			/* GPORT7 */
+			"", "",
+			"", "",
+			"", "",
+			"", "";
+			pinctrl-0 = <&U65600_pins>;
+			pinctrl-names = "default";
+			U65600_pins: cfg-pins {
+				pins = "gp00", "gp01", "gp02",
+				"gp03", "gp04", "gp05", "gp06",
+				"gp07", "gp10", "gp11", "gp12",
+				"gp13", "gp14", "gp15", "gp16",
+				"gp17", "gp20", "gp21", "gp22",
+				"gp23", "gp30", "gp31", "gp32",
+				"gp33", "gp37", "gp40", "gp41",
+				"gp42", "gp43", "gp44", "gp45",
+				"gp46", "gp47", "gp50", "gp51",
+				"gp52", "gp53", "gp54", "gp55",
+				"gp56", "gp57", "gp60", "gp61",
+				"gp62", "gp63", "gp64", "gp65",
+				"gp66";
+				function = "gpio";
+				input-enable;
+				bias-pull-up;
+			};
+		};
+	};
+	i2c@4 {
+		reg = <4>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		smb_svc_pex_cpu2_led: pinctrl@20 {
+			compatible = "cypress,cy8c9540";
+			reg = <0x20>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			interrupt-parent = <&gpio0>;
+			interrupts = <ASPEED_GPIO(V, 5) IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			vdd-supply = <&p3v3_bmc_aux>;
+			reset-gpios = <&gpio0 ASPEED_GPIO(Q, 6) GPIO_ACTIVE_HIGH>;
+			gpio-reserved-ranges = <17 3>, <36 2>;
+			gpio-line-names =
+			/* GPORT0 */
+			"PLUG_DETECT_DIMM_C2E2", "PLUG_DETECT_DIMM_C2E1",
+			"PLUG_DETECT_DIMM_C2F2", "PLUG_DETECT_DIMM_C2F1",
+			"PLUG_DETECT_DIMM_C2G2", "PLUG_DETECT_DIMM_C2G1",
+			"PLUG_DETECT_DIMM_C2H2", "PLUG_DETECT_DIMM_C2H1",
+			/* GPORT1 */
+			"PLUG_DETECT_DIMM_C2D1", "PLUG_DETECT_DIMM_C2D2",
+			"PLUG_DETECT_DIMM_C2C1", "PLUG_DETECT_DIMM_C2C2",
+			"PLUG_DETECT_DIMM_C2B1", "PLUG_DETECT_DIMM_C2B2",
+			"PLUG_DETECT_DIMM_C2A1", "PLUG_DETECT_DIMM_C2A2",
+			/* GPORT2 */
+			"PEX_CPU2_EVENT_RST", "",
+			"", "",
+			/* GPORT3 */
+			"LED_ID_DIMM_C2E2", "LED_ID_DIMM_C2E1",
+			"LED_ID_DIMM_C2F2", "LED_ID_DIMM_C2F1",
+			"LED_ID_DIMM_C2G2", "LED_ID_DIMM_C2G1",
+			"LED_ID_DIMM_C2H2", "LED_ID_DIMM_C2H1",
+			/* GPORT4 */
+			"LED_ID_DIMM_C2A2", "LED_ID_DIMM_C2A1",
+			"LED_ID_DIMM_C2B2", "LED_ID_DIMM_C2B1",
+			"LED_ID_DIMM_C2C2", "LED_ID_DIMM_C2C1",
+			"LED_ID_DIMM_C2D2", "LED_ID_DIMM_C2D1",
+			/* GPORT5 */
+			"", "",
+			"FM_CPU2_SKTOCC_N", "LED_ID_CPU2";
+		};
+	};
+	i2c@5 {
+		reg = <5>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		smb_svc_pex_cpu3_led: pinctrl@20 {
+			compatible = "cypress,cy8c9540";
+			reg = <0x20>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			interrupt-parent = <&gpio0>;
+			interrupts = <ASPEED_GPIO(V, 3) IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			vdd-supply = <&p3v3_bmc_aux>;
+			reset-gpios = <&gpio0 ASPEED_GPIO(Q, 7) GPIO_ACTIVE_HIGH>;
+			gpio-reserved-ranges = <17 3>;
+			gpio-line-names =
+			/* GPORT0 */
+			"PLUG_DETECT_DIMM_C3E2", "PLUG_DETECT_DIMM_C3E1",
+			"PLUG_DETECT_DIMM_C3F2", "PLUG_DETECT_DIMM_C3F1",
+			"PLUG_DETECT_DIMM_C3G2", "PLUG_DETECT_DIMM_C3G1",
+			"PLUG_DETECT_DIMM_C3H2", "PLUG_DETECT_DIMM_C3H1",
+			/* GPORT1 */
+			"PLUG_DETECT_DIMM_C3D1", "PLUG_DETECT_DIMM_C3D2",
+			"PLUG_DETECT_DIMM_C3C1", "PLUG_DETECT_DIMM_C3C2",
+			"PLUG_DETECT_DIMM_C3B1", "PLUG_DETECT_DIMM_C3B2",
+			"PLUG_DETECT_DIMM_C3A1", "PLUG_DETECT_DIMM_C3A2",
+			/* GPORT2 */
+			"PEX_CPU3_EVENT_RST", "",
+			"", "",
+			/* GPORT3 */
+			"LED_ID_DIMM_C3E2", "LED_ID_DIMM_C3E1",
+			"LED_ID_DIMM_C3F2", "LED_ID_DIMM_C3F1",
+			"LED_ID_DIMM_C3G2", "LED_ID_DIMM_C3G1",
+			"LED_ID_DIMM_C3H2", "LED_ID_DIMM_C3H1",
+			/* GPORT4 */
+			"LED_ID_DIMM_C3A2", "LED_ID_DIMM_C3A1",
+			"LED_ID_DIMM_C3B2", "LED_ID_DIMM_C3B1",
+			"LED_ID_DIMM_C3C2", "LED_ID_DIMM_C3C1",
+			"LED_ID_DIMM_C3D2", "LED_ID_DIMM_C3D1",
+			/* GPORT5 */
+			"LED_PWR_DWR_FRNT", "LED_ID_DWR_FRNT_P",
+			"FM_CPU3_SKTOCC_N", "LED_ID_CPU3";
+		};
+	};
+	i2c@6 {
+		reg = <6>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		smb_svc_pex_cpu0_led: pinctrl@20 {
+			compatible = "cypress,cy8c9540";
+			reg = <0x20>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			interrupt-parent = <&gpio0>;
+			interrupts = <ASPEED_GPIO(O, 3) IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			vdd-supply = <&p3v3_bmc_aux>;
+			reset-gpios = <&gpio0 ASPEED_GPIO(Q, 4) GPIO_ACTIVE_HIGH>;
+			gpio-reserved-ranges = <18 2>, <36 2>;
+			gpio-line-names =
+			/* GPORT0 */
+			"PLUG_DETECT_DIMM_C0E2", "PLUG_DETECT_DIMM_C0E1",
+			"PLUG_DETECT_DIMM_C0F2", "PLUG_DETECT_DIMM_C0F1",
+			"PLUG_DETECT_DIMM_C0G2", "PLUG_DETECT_DIMM_C0G1",
+			"PLUG_DETECT_DIMM_C0H2", "PLUG_DETECT_DIMM_C0H1",
+			/* GPORT1 */
+			"PLUG_DETECT_DIMM_C0D1", "PLUG_DETECT_DIMM_C0D2",
+			"PLUG_DETECT_DIMM_C0C1", "PLUG_DETECT_DIMM_C0C2",
+			"PLUG_DETECT_DIMM_C0B1", "PLUG_DETECT_DIMM_C0B2",
+			"PLUG_DETECT_DIMM_C0A1", "PLUG_DETECT_DIMM_C0A2",
+			/* GPORT2 */
+			"PEX_CPU0_EVENT_RST", "SVC_PEX_RSSD01_16_RST",
+			"", "",
+			/* GPORT3 */
+			"LED_ID_DIMM_C0E2", "LED_ID_DIMM_C0E1",
+			"LED_ID_DIMM_C0F2", "LED_ID_DIMM_C0F1",
+			"LED_ID_DIMM_C0G2", "LED_ID_DIMM_C0G1",
+			"LED_ID_DIMM_C0H2", "LED_ID_DIMM_C0H1",
+			/* GPORT4 */
+			"LED_ID_DIMM_C0A2", "LED_ID_DIMM_C0A1",
+			"LED_ID_DIMM_C0B2", "LED_ID_DIMM_C0B1",
+			"LED_ID_DIMM_C0C2", "LED_ID_DIMM_C0C1",
+			"LED_ID_DIMM_C0D2", "LED_ID_DIMM_C0D1",
+			/* GPORT5 */
+			"", "",
+			"FM_CPU0_SKTOCC_N", "LED_ID_CPU0";
+		};
+	};
+};
+
+&i2c9 {
+	status = "okay";
+
+	p1v2_bmc_aux_mon: pmic@60 {
+		compatible = "maxim,max8952";
+		reg = <0x60>;
+		max8952,default-mode = <3>;
+		max8952,dvs-mode-microvolt = <1100000>, <1100000>,
+					     <1100000>, <1100000>;
+		max8952,sync-freq = <0>;
+		max8952,ramp-speed = <0>;
+		regulator-always-on;
+		regulator-boot-on;
+	};
+};
+
+&i2cmux8 {
+	i2c@0 {
+		reg = <0>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		fan10_ssb: regulator@3a {
+			compatible = "maxim,max5978";
+			reg = <0x3a>;
+			vss1-supply = <&p12v>;
+			interrupt-parent = <&smb_svc_pex_fan_alert>;
+			interrupts = <9 IRQ_TYPE_LEVEL_LOW>;
+
+			regulators {
+				sw0_fan10_ssb: sw0 {
+					regulator-name = "fan10_supply";
+					shunt-resistor-micro-ohms = <10000>;
+					regulator-over-current-protection;
+					regulator-oc-protection-microamp = <3400000>;
+					regulator-enable-ramp-delay = <1000>;
+				};
+			};
+		};
+
+	};
+	i2c@1 {
+		reg = <1>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		fan12_ssb: regulator@3a {
+			compatible = "maxim,max5978";
+			reg = <0x3a>;
+			vss1-supply = <&p12v>;
+			interrupt-parent = <&smb_svc_pex_fan_alert>;
+			interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
+
+			regulators {
+				sw0_fan12_ssb: sw0 {
+					regulator-name = "fan12_supply";
+					shunt-resistor-micro-ohms = <10000>;
+					regulator-over-current-protection;
+					regulator-oc-protection-microamp = <3400000>;
+					regulator-enable-ramp-delay = <1000>;
+				};
+			};
+		};
+
+	};
+	i2c@2 {
+		reg = <2>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		fan14_ssb: regulator@3a {
+			compatible = "maxim,max5978";
+			reg = <0x3a>;
+			vss1-supply = <&p12v>;
+			interrupt-parent = <&smb_svc_pex_fan_alert>;
+			interrupts = <13 IRQ_TYPE_LEVEL_LOW>;
+
+			regulators {
+				sw0_fan14_ssb: sw0 {
+					regulator-name = "fan14_supply";
+					shunt-resistor-micro-ohms = <10000>;
+					regulator-over-current-protection;
+					regulator-oc-protection-microamp = <3400000>;
+					regulator-enable-ramp-delay = <1000>;
+				};
+			};
+		};
+	};
+	i2c@3 {
+		reg = <3>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		fan16_ssb: regulator@3a {
+			compatible = "maxim,max5978";
+			reg = <0x3a>;
+			vss1-supply = <&p12v>;
+			interrupt-parent = <&smb_svc_pex_fan_alert>;
+			interrupts = <15 IRQ_TYPE_LEVEL_LOW>;
+
+			regulators {
+				sw0_fan16_ssb: sw0 {
+					regulator-name = "fan16_supply";
+					shunt-resistor-micro-ohms = <10000>;
+					regulator-over-current-protection;
+					regulator-oc-protection-microamp = <3400000>;
+					regulator-enable-ramp-delay = <1000>;
+				};
+			};
+		};
+	};
+	i2c@4 {
+		reg = <4>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		fan18_ssb: regulator@3a {
+			compatible = "maxim,max5978";
+			reg = <0x3a>;
+			vss1-supply = <&p12v>;
+			interrupt-parent = <&smb_svc_pex_fan_alert>;
+			interrupts = <17 IRQ_TYPE_LEVEL_LOW>;
+
+			regulators {
+				sw0_fan18_ssb: sw0 {
+					regulator-name = "fan18_supply";
+					shunt-resistor-micro-ohms = <10000>;
+					regulator-over-current-protection;
+					regulator-oc-protection-microamp = <3400000>;
+					regulator-enable-ramp-delay = <1000>;
+				};
+			};
+		};
+	};
+	i2c@5 {
+		reg = <5>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		fan20_ssb: regulator@3a {
+			compatible = "maxim,max5978";
+			reg = <0x3a>;
+			vss1-supply = <&p12v>;
+			interrupt-parent = <&smb_svc_pex_fan_alert>;
+			interrupts = <19 IRQ_TYPE_LEVEL_LOW>;
+
+			regulators {
+				sw0_fan20_ssb: sw0 {
+					regulator-name = "fan20_supply";
+					shunt-resistor-micro-ohms = <10000>;
+					regulator-over-current-protection;
+					regulator-oc-protection-microamp = <3400000>;
+					regulator-enable-ramp-delay = <1000>;
+				};
+			};
+		};
+	};
+	i2c@6 {
+		reg = <6>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		fan22_ssb: regulator@3a {
+			compatible = "maxim,max5978";
+			reg = <0x3a>;
+			vss1-supply = <&p12v>;
+			interrupt-parent = <&smb_svc_pex_fan_alert>;
+			interrupts = <21 IRQ_TYPE_LEVEL_LOW>;
+
+			regulators {
+				sw0_fan22_ssb: sw0 {
+					regulator-name = "fan22_supply";
+					shunt-resistor-micro-ohms = <10000>;
+					regulator-over-current-protection;
+					regulator-oc-protection-microamp = <3400000>;
+					regulator-enable-ramp-delay = <1000>;
+				};
+			};
+		};
+	};
+	i2c@7 {
+		reg = <7>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		fan24_ssb: regulator@3a {
+			compatible = "maxim,max5978";
+			reg = <0x3a>;
+			vss1-supply = <&p12v>;
+			interrupt-parent = <&smb_svc_pex_fan_alert>;
+			interrupts = <23 IRQ_TYPE_LEVEL_LOW>;
+
+			regulators {
+				sw0_fan24_ssb: sw0 {
+					regulator-name = "fan24_supply";
+					shunt-resistor-micro-ohms = <10000>;
+					regulator-over-current-protection;
+					regulator-oc-protection-microamp = <3400000>;
+					regulator-enable-ramp-delay = <1000>;
+				};
+			};
+		};
+	};
+};
+
+&i2cmux7 {
+	i2c@0 {
+		reg = <0>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		fan17_ssb: regulator@3a {
+			compatible = "maxim,max5978";
+			reg = <0x3a>;
+			vss1-supply = <&p12v>;
+			interrupt-parent = <&smb_svc_pex_fan_alert>;
+			interrupts = <16 IRQ_TYPE_LEVEL_LOW>;
+
+			regulators {
+				sw0_fan17_ssb: sw0 {
+					regulator-name = "fan17_supply";
+					shunt-resistor-micro-ohms = <10000>;
+					regulator-over-current-protection;
+					regulator-oc-protection-microamp = <3400000>;
+					regulator-enable-ramp-delay = <1000>;
+				};
+			};
+		};
+	};
+	i2c@1 {
+		reg = <1>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		fan19_ssb: regulator@3a {
+			compatible = "maxim,max5978";
+			reg = <0x3a>;
+			vss1-supply = <&p12v>;
+			interrupt-parent = <&smb_svc_pex_fan_alert>;
+			interrupts = <18 IRQ_TYPE_LEVEL_LOW>;
+
+			regulators {
+				sw0_fan19_ssb: sw0 {
+					regulator-name = "fan19_supply";
+					shunt-resistor-micro-ohms = <10000>;
+					regulator-over-current-protection;
+					regulator-oc-protection-microamp = <3400000>;
+					regulator-enable-ramp-delay = <1000>;
+				};
+			};
+		};
+	};
+	i2c@2 {
+		reg = <2>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		fan21_ssb: regulator@3a {
+			compatible = "maxim,max5978";
+			reg = <0x3a>;
+			vss1-supply = <&p12v>;
+			interrupt-parent = <&smb_svc_pex_fan_alert>;
+			interrupts = <20 IRQ_TYPE_LEVEL_LOW>;
+
+			regulators {
+				sw0_fan21_ssb: sw0 {
+					regulator-name = "fan21_supply";
+					shunt-resistor-micro-ohms = <10000>;
+					regulator-over-current-protection;
+					regulator-oc-protection-microamp = <3400000>;
+					regulator-enable-ramp-delay = <1000>;
+				};
+			};
+		};
+	};
+	i2c@3 {
+		reg = <3>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		fan23_ssb: regulator@3a {
+			compatible = "maxim,max5978";
+			reg = <0x3a>;
+			vss1-supply = <&p12v>;
+			interrupt-parent = <&smb_svc_pex_fan_alert>;
+			interrupts = <22 IRQ_TYPE_LEVEL_LOW>;
+
+			regulators {
+				sw0_fan23_ssb: sw0 {
+					regulator-name = "fan23_supply";
+					shunt-resistor-micro-ohms = <10000>;
+					regulator-over-current-protection;
+					regulator-oc-protection-microamp = <3400000>;
+					regulator-enable-ramp-delay = <1000>;
+				};
+			};
+		};
+	};
+	i2c@4 {
+		reg = <4>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		fan02_ssb: regulator@3a {
+			compatible = "maxim,max5978";
+			reg = <0x3a>;
+			vss1-supply = <&p12v>;
+			interrupt-parent = <&smb_svc_pex_fan_alert>;
+			interrupts = <1 IRQ_TYPE_LEVEL_LOW>;
+
+			regulators {
+				sw0_fan02_ssb: sw0 {
+					regulator-name = "fan02_supply";
+					shunt-resistor-micro-ohms = <10000>;
+					regulator-over-current-protection;
+					regulator-oc-protection-microamp = <3400000>;
+					regulator-enable-ramp-delay = <1000>;
+				};
+			};
+		};
+	};
+	i2c@5 {
+		reg = <5>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		fan04_ssb: regulator@3a {
+			compatible = "maxim,max5978";
+			reg = <0x3a>;
+			vss1-supply = <&p12v>;
+			interrupt-parent = <&smb_svc_pex_fan_alert>;
+			interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
+
+			regulators {
+				sw0_fan04_ssb: sw0 {
+					regulator-name = "fan04_supply";
+					shunt-resistor-micro-ohms = <10000>;
+					regulator-over-current-protection;
+					regulator-oc-protection-microamp = <3400000>;
+					regulator-enable-ramp-delay = <1000>;
+				};
+			};
+		};
+	};
+	i2c@6 {
+		reg = <6>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		fan06_ssb: regulator@3a {
+			compatible = "maxim,max5978";
+			reg = <0x3a>;
+			vss1-supply = <&p12v>;
+			interrupt-parent = <&smb_svc_pex_fan_alert>;
+			interrupts = <5 IRQ_TYPE_LEVEL_LOW>;
+
+			regulators {
+				sw0_fan06_ssb: sw0 {
+					regulator-name = "fan06_supply";
+					shunt-resistor-micro-ohms = <10000>;
+					regulator-over-current-protection;
+					regulator-oc-protection-microamp = <3400000>;
+					regulator-enable-ramp-delay = <1000>;
+				};
+			};
+		};
+	};
+	i2c@7 {
+		reg = <7>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		fan08_ssb: regulator@3a {
+			compatible = "maxim,max5978";
+			reg = <0x3a>;
+			vss1-supply = <&p12v>;
+			interrupt-parent = <&smb_svc_pex_fan_alert>;
+			interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
+
+			regulators {
+				sw0_fan08_ssb: sw0 {
+					regulator-name = "fan08_supply";
+					shunt-resistor-micro-ohms = <10000>;
+					regulator-over-current-protection;
+					regulator-oc-protection-microamp = <3400000>;
+					regulator-enable-ramp-delay = <1000>;
+				};
+			};
+		};
+	};
+};
+
+&i2cmux6 {
+	i2c@0 {
+		reg = <0>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		fan01_ssb: regulator@3a {
+			compatible = "maxim,max5978";
+			reg = <0x3a>;
+			vss1-supply = <&p12v>;
+			interrupt-parent = <&smb_svc_pex_fan_alert>;
+			interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+
+			regulators {
+				sw0_fan01_ssb: sw0 {
+					regulator-name = "fan01_supply";
+					shunt-resistor-micro-ohms = <10000>;
+					regulator-over-current-protection;
+					regulator-oc-protection-microamp = <3400000>;
+					regulator-enable-ramp-delay = <1000>;
+				};
+			};
+		};
+	};
+	i2c@1 {
+		reg = <1>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		fan03_ssb: regulator@3a {
+			compatible = "maxim,max5978";
+			reg = <0x3a>;
+			vss1-supply = <&p12v>;
+			interrupt-parent = <&smb_svc_pex_fan_alert>;
+			interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
+
+			regulators {
+				sw0_fan03_ssb: sw0 {
+					regulator-name = "fan03_supply";
+
+					shunt-resistor-micro-ohms = <10000>;
+					regulator-over-current-protection;
+					regulator-oc-protection-microamp = <3400000>;
+					regulator-enable-ramp-delay = <1000>;
+				};
+			};
+		};
+	};
+	i2c@2 {
+		reg = <2>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		fan05_ssb: regulator@3a {
+			compatible = "maxim,max5978";
+			reg = <0x3a>;
+			vss1-supply = <&p12v>;
+			interrupt-parent = <&smb_svc_pex_fan_alert>;
+			interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
+
+			regulators {
+				sw0_fan05_ssb: sw0 {
+					regulator-name = "fan05_supply";
+					shunt-resistor-micro-ohms = <10000>;
+					regulator-over-current-protection;
+					regulator-oc-protection-microamp = <3400000>;
+					regulator-enable-ramp-delay = <1000>;
+				};
+			};
+		};
+	};
+	i2c@3 {
+		reg = <3>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		fan07_ssb: regulator@3a {
+			compatible = "maxim,max5978";
+			reg = <0x3a>;
+			vss1-supply = <&p12v>;
+			interrupt-parent = <&smb_svc_pex_fan_alert>;
+			interrupts = <6 IRQ_TYPE_LEVEL_LOW>;
+
+			regulators {
+				sw0_fan07_ssb: sw0 {
+					regulator-name = "fan07_supply";
+					shunt-resistor-micro-ohms = <10000>;
+					regulator-over-current-protection;
+					regulator-oc-protection-microamp = <3400000>;
+					regulator-enable-ramp-delay = <1000>;
+				};
+			};
+		};
+	};
+	i2c@4 {
+		reg = <4>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		fan09_ssb: regulator@3a {
+			compatible = "maxim,max5978";
+			reg = <0x3a>;
+			vss1-supply = <&p12v>;
+			interrupt-parent = <&smb_svc_pex_fan_alert>;
+			interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
+
+			regulators {
+				sw0_fan09_ssb: sw0 {
+					regulator-name = "fan09_supply";
+					shunt-resistor-micro-ohms = <10000>;
+					regulator-over-current-protection;
+					regulator-oc-protection-microamp = <3400000>;
+					regulator-enable-ramp-delay = <1000>;
+				};
+			};
+		};
+	};
+	i2c@5 {
+		reg = <5>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		fan11_ssb: regulator@3a {
+			compatible = "maxim,max5978";
+			reg = <0x3a>;
+			vss1-supply = <&p12v>;
+			interrupt-parent = <&smb_svc_pex_fan_alert>;
+			interrupts = <10 IRQ_TYPE_LEVEL_LOW>;
+
+			regulators {
+				sw0_fan11_ssb: sw0 {
+					regulator-name = "fan11_supply";
+					shunt-resistor-micro-ohms = <10000>;
+					regulator-over-current-protection;
+					regulator-oc-protection-microamp = <3400000>;
+					regulator-enable-ramp-delay = <1000>;
+				};
+			};
+		};
+	};
+	i2c@6 {
+		reg = <6>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		fan13_ssb: regulator@3a {
+			compatible = "maxim,max5978";
+			reg = <0x3a>;
+			vss1-supply = <&p12v>;
+			interrupt-parent = <&smb_svc_pex_fan_alert>;
+			interrupts = <12 IRQ_TYPE_LEVEL_LOW>;
+
+			regulators {
+				sw0_fan13_ssb: sw0 {
+					regulator-name = "fan13_supply";
+					shunt-resistor-micro-ohms = <10000>;
+					regulator-over-current-protection;
+					regulator-oc-protection-microamp = <3400000>;
+					regulator-enable-ramp-delay = <1000>;
+				};
+			};
+		};
+	};
+	i2c@7 {
+		reg = <7>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		fan15_ssb: regulator@3a {
+			compatible = "maxim,max5978";
+			reg = <0x3a>;
+			vss1-supply = <&p12v>;
+			interrupt-parent = <&smb_svc_pex_fan_alert>;
+			interrupts = <14 IRQ_TYPE_LEVEL_LOW>;
+
+			regulators {
+				sw0_fan15_ssb: sw0 {
+					regulator-name = "fan15_supply";
+					shunt-resistor-micro-ohms = <10000>;
+					regulator-over-current-protection;
+					regulator-oc-protection-microamp = <3400000>;
+					regulator-enable-ramp-delay = <1000>;
+				};
+			};
+		};
+
+	};
+};
+
+&i2cmux9 {
+	i2c@0 {
+		reg = <0>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		ssb_rssd19: regulator@3a {
+			compatible = "maxim,max5970";
+			reg = <0x3a>;
+			interrupt-parent = <&smb_svc_pex_rssd17_32>;
+			interrupts = <46 IRQ_TYPE_LEVEL_LOW>;
+
+			vss1-supply = <&p3v3_aux>;
+			vss2-supply = <&p12v>;
+
+			leds {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				led@0 {
+					reg = <0>;
+					label = "rssd19:green:power";
+					default-state = "off";
+				};
+			};
+
+			regulators {
+				sw0_ssb_rssd19: sw0 {
+					regulator-name = "rssd19_12v";
+					shunt-resistor-micro-ohms = <9000>;
+					regulator-over-current-protection;
+					regulator-oc-protection-microamp = <4500000>;
+					regulator-enable-ramp-delay = <1000>;
+				};
+				sw1_ssb_rssd19: sw1 {
+					regulator-name = "rssd19_3v3";
+					shunt-resistor-micro-ohms = <100000>;
+					regulator-over-current-protection;
+					regulator-oc-protection-microamp = <410000>;
+					regulator-enable-ramp-delay = <1000>;
+				};
+			};
+		};
+	};
+	i2c@1 {
+		reg = <1>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		ssb_rssd18: regulator@3a {
+			compatible = "maxim,max5970";
+			reg = <0x3a>;
+			interrupt-parent = <&smb_svc_pex_rssd17_32>;
+			interrupts = <45 IRQ_TYPE_LEVEL_LOW>;
+
+			vss1-supply = <&p3v3_aux>;
+			vss2-supply = <&p12v>;
+
+			leds {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				led@0 {
+					reg = <0>;
+					label = "rssd18:green:power";
+					default-state = "off";
+				};
+			};
+
+			regulators {
+				sw0_ssb_rssd18: sw0 {
+					regulator-name = "rssd18_12v";
+					shunt-resistor-micro-ohms = <9000>;
+					regulator-over-current-protection;
+					regulator-oc-protection-microamp = <4500000>;
+					regulator-enable-ramp-delay = <1000>;
+				};
+				sw1_ssb_rssd18: sw1 {
+					regulator-name = "rssd18_3v3";
+					shunt-resistor-micro-ohms = <100000>;
+					regulator-over-current-protection;
+					regulator-oc-protection-microamp = <410000>;
+					regulator-enable-ramp-delay = <1000>;
+				};
+			};
+		};
+	};
+	i2c@2 {
+		reg = <2>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		ssb_rssd17: regulator@3a {
+			compatible = "maxim,max5970";
+			reg = <0x3a>;
+			interrupt-parent = <&smb_svc_pex_rssd17_32>;
+			interrupts = <44 IRQ_TYPE_LEVEL_LOW>;
+
+			vss1-supply = <&p3v3_aux>;
+			vss2-supply = <&p12v>;
+
+			leds {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				led@0 {
+					reg = <0>;
+					label = "rssd17:green:power";
+					default-state = "off";
+				};
+			};
+
+			regulators {
+				sw0_ssb_rssd17: sw0 {
+					regulator-name = "rssd17_12v";
+					shunt-resistor-micro-ohms = <9000>;
+					regulator-over-current-protection;
+					regulator-oc-protection-microamp = <4500000>;
+					regulator-enable-ramp-delay = <1000>;
+				};
+				sw1_ssb_rssd17: sw1 {
+					regulator-name = "rssd17_3v3";
+					shunt-resistor-micro-ohms = <100000>;
+					regulator-over-current-protection;
+					regulator-oc-protection-microamp = <410000>;
+					regulator-enable-ramp-delay = <1000>;
+				};
+			};
+		};
+	};
+	i2c@3 {
+		reg = <3>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		ssb_rssd20: regulator@3a {
+			compatible = "maxim,max5970";
+			reg = <0x3a>;
+			interrupt-parent = <&smb_svc_pex_rssd17_32>;
+			interrupts = <47 IRQ_TYPE_LEVEL_LOW>;
+
+			vss1-supply = <&p3v3_aux>;
+			vss2-supply = <&p12v>;
+
+			leds {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				led@0 {
+					reg = <0>;
+					label = "rssd20:green:power";
+					default-state = "off";
+				};
+			};
+
+			regulators {
+				sw0_ssb_rssd20: sw0 {
+					regulator-name = "rssd20_12v";
+					shunt-resistor-micro-ohms = <9000>;
+					regulator-over-current-protection;
+					regulator-oc-protection-microamp = <4500000>;
+					regulator-enable-ramp-delay = <1000>;
+				};
+				sw1_ssb_rssd20: sw1 {
+					regulator-name = "rssd20_3v3";
+					shunt-resistor-micro-ohms = <100000>;
+					regulator-over-current-protection;
+					regulator-oc-protection-microamp = <410000>;
+					regulator-enable-ramp-delay = <1000>;
+				};
+			};
+		};
+	};
+	i2c@4 {
+		reg = <4>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		ssb_rssd21: regulator@3a {
+			compatible = "maxim,max5970";
+			reg = <0x3a>;
+			interrupt-parent = <&smb_svc_pex_rssd17_32>;
+			interrupts = <48 IRQ_TYPE_LEVEL_LOW>;
+
+			vss1-supply = <&p3v3_aux>;
+			vss2-supply = <&p12v>;
+
+			leds {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				led@0 {
+					reg = <0>;
+					label = "rssd21:green:power";
+					default-state = "off";
+				};
+			};
+
+			regulators {
+				sw0_ssb_rssd21: sw0 {
+					regulator-name = "rssd21_12v";
+					shunt-resistor-micro-ohms = <9000>;
+					regulator-over-current-protection;
+					regulator-oc-protection-microamp = <4500000>;
+					regulator-enable-ramp-delay = <1000>;
+				};
+				sw1_ssb_rssd21: sw1 {
+					regulator-name = "rssd21_3v3";
+					shunt-resistor-micro-ohms = <100000>;
+					regulator-over-current-protection;
+					regulator-oc-protection-microamp = <410000>;
+					regulator-enable-ramp-delay = <1000>;
+				};
+			};
+		};
+	};
+	i2c@5 {
+		reg = <5>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		ssb_rssd22: regulator@3a {
+			compatible = "maxim,max5970";
+			reg = <0x3a>;
+			interrupt-parent = <&smb_svc_pex_rssd17_32>;
+			interrupts = <49 IRQ_TYPE_LEVEL_LOW>;
+
+			vss1-supply = <&p3v3_aux>;
+			vss2-supply = <&p12v>;
+
+			leds {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				led@0 {
+					reg = <0>;
+					label = "rssd22:green:power";
+					default-state = "off";
+				};
+			};
+
+			regulators {
+				sw0_ssb_rssd22: sw0 {
+					regulator-name = "rssd22_12v";
+					shunt-resistor-micro-ohms = <9000>;
+					regulator-over-current-protection;
+					regulator-oc-protection-microamp = <4500000>;
+					regulator-enable-ramp-delay = <1000>;
+				};
+				sw1_ssb_rssd22: sw1 {
+					regulator-name = "rssd22_3v3";
+					shunt-resistor-micro-ohms = <100000>;
+					regulator-over-current-protection;
+					regulator-oc-protection-microamp = <410000>;
+					regulator-enable-ramp-delay = <1000>;
+				};
+			};
+		};
+	};
+	i2c@6 {
+		reg = <6>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		ssb_rssd24: regulator@3a {
+			compatible = "maxim,max5970";
+			reg = <0x3a>;
+			interrupt-parent = <&smb_svc_pex_rssd17_32>;
+			interrupts = <51 IRQ_TYPE_LEVEL_LOW>;
+
+			vss1-supply = <&p3v3_aux>;
+			vss2-supply = <&p12v>;
+
+			leds {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				led@0 {
+					reg = <0>;
+					label = "rssd24:green:power";
+					default-state = "off";
+				};
+			};
+
+			regulators {
+				sw0_ssb_rssd24: sw0 {
+					regulator-name = "rssd24_12v";
+					shunt-resistor-micro-ohms = <9000>;
+					regulator-over-current-protection;
+					regulator-oc-protection-microamp = <4500000>;
+					regulator-enable-ramp-delay = <1000>;
+				};
+				sw1_ssb_rssd24: sw1 {
+					regulator-name = "rssd24_3v3";
+					shunt-resistor-micro-ohms = <100000>;
+					regulator-over-current-protection;
+					regulator-oc-protection-microamp = <410000>;
+					regulator-enable-ramp-delay = <1000>;
+				};
+			};
+		};
+	};
+	i2c@7 {
+		reg = <7>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		ssb_rssd23: regulator@3a {
+			compatible = "maxim,max5970";
+			reg = <0x3a>;
+			interrupt-parent = <&smb_svc_pex_rssd17_32>;
+			interrupts = <50 IRQ_TYPE_LEVEL_LOW>;
+
+			vss1-supply = <&p3v3_aux>;
+			vss2-supply = <&p12v>;
+
+			leds {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				led@0 {
+					reg = <0>;
+					label = "rssd23:green:power";
+					default-state = "off";
+				};
+			};
+
+			regulators {
+				sw0_ssb_rssd23: sw0 {
+					regulator-name = "rssd23_12v";
+					shunt-resistor-micro-ohms = <9000>;
+					regulator-over-current-protection;
+					regulator-oc-protection-microamp = <4500000>;
+					regulator-enable-ramp-delay = <1000>;
+				};
+				sw1_ssb_rssd23: sw1 {
+					regulator-name = "rssd23_3v3";
+					shunt-resistor-micro-ohms = <100000>;
+					regulator-over-current-protection;
+					regulator-oc-protection-microamp = <410000>;
+					regulator-enable-ramp-delay = <1000>;
+				};
+			};
+		};
+	};
+};
+
+&i2cmux10 {
+	i2c@0 {
+		reg = <0>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		ssb_rssd25: regulator@3a {
+			compatible = "maxim,max5970";
+			reg = <0x3a>;
+			interrupt-parent = <&smb_svc_pex_rssd17_32>;
+			interrupts = <52 IRQ_TYPE_LEVEL_LOW>;
+
+			vss1-supply = <&p3v3_aux>;
+			vss2-supply = <&p12v>;
+
+			leds {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				led@0 {
+					reg = <0>;
+					label = "rssd25:green:power";
+					default-state = "off";
+				};
+			};
+
+			regulators {
+				sw0_ssb_rssd25: sw0 {
+					regulator-name = "rssd25_12v";
+					shunt-resistor-micro-ohms = <9000>;
+					regulator-over-current-protection;
+					regulator-oc-protection-microamp = <4500000>;
+					regulator-enable-ramp-delay = <1000>;
+				};
+				sw1_ssb_rssd25: sw1 {
+					regulator-name = "rssd25_3v3";
+					shunt-resistor-micro-ohms = <100000>;
+					regulator-over-current-protection;
+					regulator-oc-protection-microamp = <410000>;
+					regulator-enable-ramp-delay = <1000>;
+				};
+			};
+		};
+	};
+	i2c@1 {
+		reg = <1>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		ssb_rssd26: regulator@3a {
+			compatible = "maxim,max5970";
+			reg = <0x3a>;
+			interrupt-parent = <&smb_svc_pex_rssd17_32>;
+			interrupts = <53 IRQ_TYPE_LEVEL_LOW>;
+
+			vss1-supply = <&p3v3_aux>;
+			vss2-supply = <&p12v>;
+
+			leds {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				led@0 {
+					reg = <0>;
+					label = "rssd26:green:power";
+					default-state = "off";
+				};
+			};
+
+			regulators {
+				sw0_ssb_rssd26: sw0 {
+					regulator-name = "rssd26_12v";
+					shunt-resistor-micro-ohms = <9000>;
+					regulator-over-current-protection;
+					regulator-oc-protection-microamp = <4500000>;
+					regulator-enable-ramp-delay = <1000>;
+				};
+				sw1_ssb_rssd26: sw1 {
+					regulator-name = "rssd26_3v3";
+					shunt-resistor-micro-ohms = <100000>;
+					regulator-over-current-protection;
+					regulator-oc-protection-microamp = <410000>;
+					regulator-enable-ramp-delay = <1000>;
+				};
+			};
+		};
+	};
+	i2c@2 {
+		reg = <2>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		ssb_rssd27: regulator@3a {
+			compatible = "maxim,max5970";
+			reg = <0x3a>;
+			interrupt-parent = <&smb_svc_pex_rssd17_32>;
+			interrupts = <54 IRQ_TYPE_LEVEL_LOW>;
+
+			vss1-supply = <&p3v3_aux>;
+			vss2-supply = <&p12v>;
+
+			leds {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				led@0 {
+					reg = <0>;
+					label = "rssd27:green:power";
+					default-state = "off";
+				};
+			};
+
+			regulators {
+				sw0_ssb_rssd27: sw0 {
+					regulator-name = "rssd27_12v";
+					shunt-resistor-micro-ohms = <9000>;
+					regulator-over-current-protection;
+					regulator-oc-protection-microamp = <4500000>;
+					regulator-enable-ramp-delay = <1000>;
+				};
+				sw1_ssb_rssd27: sw1 {
+					regulator-name = "rssd27_3v3";
+					shunt-resistor-micro-ohms = <100000>;
+					regulator-over-current-protection;
+					regulator-oc-protection-microamp = <410000>;
+					regulator-enable-ramp-delay = <1000>;
+				};
+			};
+		};
+	};
+	i2c@3 {
+		reg = <3>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		ssb_rssd32: regulator@3a {
+			compatible = "maxim,max5970";
+			reg = <0x3a>;
+			interrupt-parent = <&smb_svc_pex_rssd17_32>;
+			interrupts = <59 IRQ_TYPE_LEVEL_LOW>;
+
+			vss1-supply = <&p3v3_aux>;
+			vss2-supply = <&p12v>;
+
+			leds {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				led@0 {
+					reg = <0>;
+					label = "rssd32:green:power";
+					default-state = "off";
+				};
+			};
+
+			regulators {
+				sw0_ssb_rssd32: sw0 {
+					regulator-name = "rssd32_12v";
+					shunt-resistor-micro-ohms = <9000>;
+					regulator-over-current-protection;
+					regulator-oc-protection-microamp = <4500000>;
+					regulator-enable-ramp-delay = <1000>;
+				};
+				sw1_ssb_rssd32: sw1 {
+					regulator-name = "rssd32_3v3";
+					shunt-resistor-micro-ohms = <100000>;
+					regulator-over-current-protection;
+					regulator-oc-protection-microamp = <410000>;
+					regulator-enable-ramp-delay = <1000>;
+				};
+			};
+		};
+	};
+	i2c@4 {
+		reg = <4>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		ssb_rssd31: regulator@3a {
+			compatible = "maxim,max5970";
+			reg = <0x3a>;
+			interrupt-parent = <&smb_svc_pex_rssd17_32>;
+			interrupts = <58 IRQ_TYPE_LEVEL_LOW>;
+
+			vss1-supply = <&p3v3_aux>;
+			vss2-supply = <&p12v>;
+
+			leds {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				led@0 {
+					reg = <0>;
+					label = "rssd31:green:power";
+					default-state = "off";
+				};
+			};
+
+			regulators {
+				sw0_ssb_rssd31: sw0 {
+					regulator-name = "rssd31_12v";
+					shunt-resistor-micro-ohms = <9000>;
+					regulator-over-current-protection;
+					regulator-oc-protection-microamp = <4500000>;
+					regulator-enable-ramp-delay = <1000>;
+				};
+				sw1_ssb_rssd31: sw1 {
+					regulator-name = "rssd31_3v3";
+					shunt-resistor-micro-ohms = <100000>;
+					regulator-over-current-protection;
+					regulator-oc-protection-microamp = <410000>;
+					regulator-enable-ramp-delay = <1000>;
+				};
+			};
+		};
+	};
+	i2c@5 {
+		reg = <5>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		ssb_rssd30: regulator@3a {
+			compatible = "maxim,max5970";
+			reg = <0x3a>;
+			interrupt-parent = <&smb_svc_pex_rssd17_32>;
+			interrupts = <57 IRQ_TYPE_LEVEL_LOW>;
+
+			vss1-supply = <&p3v3_aux>;
+			vss2-supply = <&p12v>;
+
+			leds {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				led@0 {
+					reg = <0>;
+					label = "rssd30:green:power";
+					default-state = "off";
+				};
+			};
+
+			regulators {
+				sw0_ssb_rssd30: sw0 {
+					regulator-name = "rssd30_12v";
+					shunt-resistor-micro-ohms = <9000>;
+					regulator-over-current-protection;
+					regulator-oc-protection-microamp = <4500000>;
+					regulator-enable-ramp-delay = <1000>;
+				};
+				sw1_ssb_rssd30: sw1 {
+					regulator-name = "rssd30_3v3";
+					shunt-resistor-micro-ohms = <100000>;
+					regulator-over-current-protection;
+					regulator-oc-protection-microamp = <410000>;
+					regulator-enable-ramp-delay = <1000>;
+				};
+			};
+		};
+	};
+	i2c@6 {
+		reg = <6>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		ssb_rssd29: regulator@3a {
+			compatible = "maxim,max5970";
+			reg = <0x3a>;
+			interrupt-parent = <&smb_svc_pex_rssd17_32>;
+			interrupts = <56 IRQ_TYPE_LEVEL_LOW>;
+
+			vss1-supply = <&p3v3_aux>;
+			vss2-supply = <&p12v>;
+
+			leds {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				led@0 {
+					reg = <0>;
+					label = "rssd29:green:power";
+					default-state = "off";
+				};
+			};
+
+			regulators {
+				sw0_ssb_rssd29: sw0 {
+					regulator-name = "rssd29_12v";
+					shunt-resistor-micro-ohms = <9000>;
+					regulator-over-current-protection;
+					regulator-oc-protection-microamp = <4500000>;
+					regulator-enable-ramp-delay = <1000>;
+				};
+				sw1_ssb_rssd29: sw1 {
+					regulator-name = "rssd29_3v3";
+					shunt-resistor-micro-ohms = <100000>;
+					regulator-over-current-protection;
+					regulator-oc-protection-microamp = <410000>;
+					regulator-enable-ramp-delay = <1000>;
+				};
+			};
+		};
+	};
+	i2c@7 {
+		reg = <7>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		ssb_rssd28: regulator@3a {
+			compatible = "maxim,max5970";
+			reg = <0x3a>;
+			interrupt-parent = <&smb_svc_pex_rssd17_32>;
+			interrupts = <55 IRQ_TYPE_LEVEL_LOW>;
+
+			vss1-supply = <&p3v3_aux>;
+			vss2-supply = <&p12v>;
+
+			leds {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				led@0 {
+					reg = <0>;
+					label = "rssd28:green:power";
+					default-state = "off";
+				};
+			};
+
+			regulators {
+				sw0_ssb_rssd28: sw0 {
+					regulator-name = "rssd28_12v";
+					shunt-resistor-micro-ohms = <9000>;
+					regulator-over-current-protection;
+					regulator-oc-protection-microamp = <4500000>;
+					regulator-enable-ramp-delay = <1000>;
+				};
+				sw1_ssb_rssd28: sw1 {
+					regulator-name = "rssd28_3v3";
+					shunt-resistor-micro-ohms = <100000>;
+					regulator-over-current-protection;
+					regulator-oc-protection-microamp = <410000>;
+					regulator-enable-ramp-delay = <1000>;
+				};
+			};
+		};
+	};
+};
+
+&i2cmux18 {
+	i2c@0 {
+		reg = <0>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		ssb_rssd03: regulator@3a {
+			compatible = "maxim,max5970";
+			reg = <0x3a>;
+			interrupt-parent = <&smb_svc_pex_rssd01_16>;
+			interrupts = <46 IRQ_TYPE_LEVEL_LOW>;
+
+			vss1-supply = <&p3v3_aux>;
+			vss2-supply = <&p12v>;
+
+			leds {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				led@0 {
+					reg = <0>;
+					label = "rssd03:green:power";
+					default-state = "off";
+				};
+			};
+
+			regulators {
+				sw0_ssb_rssd03: sw0 {
+					regulator-name = "rssd03_12v";
+					shunt-resistor-micro-ohms = <9000>;
+					regulator-over-current-protection;
+					regulator-oc-protection-microamp = <4500000>;
+					regulator-enable-ramp-delay = <1000>;
+				};
+				sw1_ssb_rssd03: sw1 {
+					regulator-name = "rssd03_3v3";
+					shunt-resistor-micro-ohms = <100000>;
+					regulator-over-current-protection;
+					regulator-oc-protection-microamp = <410000>;
+					regulator-enable-ramp-delay = <1000>;
+				};
+			};
+		};
+	};
+	i2c@1 {
+		reg = <1>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		ssb_rssd02: regulator@3a {
+			compatible = "maxim,max5970";
+			reg = <0x3a>;
+			interrupt-parent = <&smb_svc_pex_rssd01_16>;
+			interrupts = <45 IRQ_TYPE_LEVEL_LOW>;
+
+			vss1-supply = <&p3v3_aux>;
+			vss2-supply = <&p12v>;
+
+			leds {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				led@0 {
+					reg = <0>;
+					label = "rssd02:green:power";
+					default-state = "off";
+				};
+			};
+
+			regulators {
+				sw0_ssb_rssd02: sw0 {
+					regulator-name = "rssd02_12v";
+					shunt-resistor-micro-ohms = <9000>;
+					regulator-over-current-protection;
+					regulator-oc-protection-microamp = <4500000>;
+					regulator-enable-ramp-delay = <1000>;
+				};
+				sw1_ssb_rssd02: sw1 {
+					regulator-name = "rssd02_3v3";
+					shunt-resistor-micro-ohms = <100000>;
+					regulator-over-current-protection;
+					regulator-oc-protection-microamp = <410000>;
+					regulator-enable-ramp-delay = <1000>;
+				};
+			};
+		};
+	};
+	i2c@2 {
+		reg = <2>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		ssb_rssd01: regulator@3a {
+			compatible = "maxim,max5970";
+			reg = <0x3a>;
+			interrupt-parent = <&smb_svc_pex_rssd01_16>;
+			interrupts = <44 IRQ_TYPE_LEVEL_LOW>;
+
+			vss1-supply = <&p3v3_aux>;
+			vss2-supply = <&p12v>;
+
+			leds {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				led@0 {
+					reg = <0>;
+					label = "rssd01:green:power";
+					default-state = "off";
+				};
+			};
+
+			regulators {
+				sw0_ssb_rssd01: sw0 {
+					regulator-name = "rssd01_12v";
+					shunt-resistor-micro-ohms = <9000>;
+					regulator-over-current-protection;
+					regulator-oc-protection-microamp = <4500000>;
+					regulator-enable-ramp-delay = <1000>;
+				};
+				sw1_ssb_rssd01: sw1 {
+					regulator-name = "rssd01_3v3";
+					shunt-resistor-micro-ohms = <100000>;
+					regulator-over-current-protection;
+					regulator-oc-protection-microamp = <410000>;
+					regulator-enable-ramp-delay = <1000>;
+				};
+			};
+		};
+	};
+	i2c@3 {
+		reg = <3>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		ssb_rssd04: regulator@3a {
+			compatible = "maxim,max5970";
+			reg = <0x3a>;
+			interrupt-parent = <&smb_svc_pex_rssd01_16>;
+			interrupts = <47 IRQ_TYPE_LEVEL_LOW>;
+
+			vss1-supply = <&p3v3_aux>;
+			vss2-supply = <&p12v>;
+
+			leds {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				led@0 {
+					reg = <0>;
+					label = "rssd04:green:power";
+					default-state = "off";
+				};
+			};
+
+			regulators {
+				sw0_ssb_rssd04: sw0 {
+					regulator-name = "rssd04_12v";
+					shunt-resistor-micro-ohms = <9000>;
+					regulator-over-current-protection;
+					regulator-oc-protection-microamp = <4500000>;
+					regulator-enable-ramp-delay = <1000>;
+				};
+				sw1_ssb_rssd04: sw1 {
+					regulator-name = "rssd04_3v3";
+					shunt-resistor-micro-ohms = <100000>;
+					regulator-over-current-protection;
+					regulator-oc-protection-microamp = <410000>;
+					regulator-enable-ramp-delay = <1000>;
+				};
+			};
+		};
+	};
+	i2c@4 {
+		reg = <4>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		ssb_rssd05: regulator@3a {
+			compatible = "maxim,max5970";
+			reg = <0x3a>;
+			interrupt-parent = <&smb_svc_pex_rssd01_16>;
+			interrupts = <48 IRQ_TYPE_LEVEL_LOW>;
+
+			vss1-supply = <&p3v3_aux>;
+			vss2-supply = <&p12v>;
+
+			leds {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				led@0 {
+					reg = <0>;
+					label = "rssd05:green:power";
+					default-state = "off";
+				};
+			};
+
+			regulators {
+				sw0_ssb_rssd05: sw0 {
+					regulator-name = "rssd05_12v";
+					shunt-resistor-micro-ohms = <9000>;
+					regulator-over-current-protection;
+					regulator-oc-protection-microamp = <4500000>;
+					regulator-enable-ramp-delay = <1000>;
+				};
+				sw1_ssb_rssd05: sw1 {
+					regulator-name = "rssd05_3v3";
+					shunt-resistor-micro-ohms = <100000>;
+					regulator-over-current-protection;
+					regulator-oc-protection-microamp = <410000>;
+					regulator-enable-ramp-delay = <1000>;
+				};
+			};
+		};
+	};
+	i2c@5 {
+		reg = <5>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		ssb_rssd08: regulator@3a {
+			compatible = "maxim,max5970";
+			reg = <0x3a>;
+			interrupt-parent = <&smb_svc_pex_rssd01_16>;
+			interrupts = <51 IRQ_TYPE_LEVEL_LOW>;
+
+			vss1-supply = <&p3v3_aux>;
+			vss2-supply = <&p12v>;
+
+			leds {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				led@0 {
+					reg = <0>;
+					label = "rssd08:green:power";
+					default-state = "off";
+				};
+			};
+
+			regulators {
+				sw0_ssb_rssd08: sw0 {
+					regulator-name = "rssd08_12v";
+					shunt-resistor-micro-ohms = <9000>;
+					regulator-over-current-protection;
+					regulator-oc-protection-microamp = <4500000>;
+					regulator-enable-ramp-delay = <1000>;
+				};
+				sw1_ssb_rssd08: sw1 {
+					regulator-name = "rssd08_3v3";
+					shunt-resistor-micro-ohms = <100000>;
+					regulator-over-current-protection;
+					regulator-oc-protection-microamp = <410000>;
+					regulator-enable-ramp-delay = <1000>;
+				};
+			};
+		};
+	};
+	i2c@6 {
+		reg = <6>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		ssb_rssd07: regulator@3a {
+			compatible = "maxim,max5970";
+			reg = <0x3a>;
+			interrupt-parent = <&smb_svc_pex_rssd01_16>;
+			interrupts = <50 IRQ_TYPE_LEVEL_LOW>;
+
+			vss1-supply = <&p3v3_aux>;
+			vss2-supply = <&p12v>;
+
+			leds {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				led@0 {
+					reg = <0>;
+					label = "rssd07:green:power";
+					default-state = "off";
+				};
+			};
+
+			regulators {
+				sw0_ssb_rssd07: sw0 {
+					regulator-name = "rssd07_12v";
+					shunt-resistor-micro-ohms = <9000>;
+					regulator-over-current-protection;
+					regulator-oc-protection-microamp = <4500000>;
+					regulator-enable-ramp-delay = <1000>;
+				};
+				sw1_ssb_rssd07: sw1 {
+					regulator-name = "rssd07_3v3";
+					shunt-resistor-micro-ohms = <100000>;
+					regulator-over-current-protection;
+					regulator-oc-protection-microamp = <410000>;
+					regulator-enable-ramp-delay = <1000>;
+				};
+			};
+		};
+	};
+	i2c@7 {
+		reg = <7>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		ssb_rssd06: regulator@3a {
+			compatible = "maxim,max5970";
+			reg = <0x3a>;
+			interrupt-parent = <&smb_svc_pex_rssd01_16>;
+			interrupts = <49 IRQ_TYPE_LEVEL_LOW>;
+
+			vss1-supply = <&p3v3_aux>;
+			vss2-supply = <&p12v>;
+
+			leds {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				led@0 {
+					reg = <0>;
+					label = "rssd06:green:power";
+					default-state = "off";
+				};
+			};
+
+			regulators {
+				sw0_ssb_rssd06: sw0 {
+					regulator-name = "rssd06_12v";
+					shunt-resistor-micro-ohms = <9000>;
+					regulator-over-current-protection;
+					regulator-oc-protection-microamp = <4500000>;
+					regulator-enable-ramp-delay = <1000>;
+				};
+				sw1_ssb_rssd06: sw1 {
+					regulator-name = "rssd06_3v3";
+					shunt-resistor-micro-ohms = <100000>;
+					regulator-over-current-protection;
+					regulator-oc-protection-microamp = <410000>;
+					regulator-enable-ramp-delay = <1000>;
+				};
+			};
+		};
+	};
+};
+
+&i2cmux19 {
+	i2c@0 {
+		reg = <0>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		ssb_rssd14: regulator@3a {
+			compatible = "maxim,max5970";
+			reg = <0x3a>;
+			interrupt-parent = <&smb_svc_pex_rssd01_16>;
+			interrupts = <57 IRQ_TYPE_LEVEL_LOW>;
+
+			vss1-supply = <&p3v3_aux>;
+			vss2-supply = <&p12v>;
+
+			leds {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				led@0 {
+					reg = <0>;
+					label = "rssd14:green:power";
+					default-state = "off";
+				};
+			};
+
+			regulators {
+				sw0_ssb_rssd14: sw0 {
+					regulator-name = "rssd14_12v";
+					shunt-resistor-micro-ohms = <9000>;
+					regulator-over-current-protection;
+					regulator-oc-protection-microamp = <4500000>;
+					regulator-enable-ramp-delay = <1000>;
+				};
+				sw1_ssb_rssd14: sw1 {
+					regulator-name = "rssd14_3v3";
+					shunt-resistor-micro-ohms = <100000>;
+					regulator-over-current-protection;
+					regulator-oc-protection-microamp = <410000>;
+					regulator-enable-ramp-delay = <1000>;
+				};
+			};
+		};
+	};
+	i2c@1 {
+		reg = <1>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		ssb_rssd13: regulator@3a {
+			compatible = "maxim,max5970";
+			reg = <0x3a>;
+			interrupt-parent = <&smb_svc_pex_rssd01_16>;
+			interrupts = <56 IRQ_TYPE_LEVEL_LOW>;
+
+			vss1-supply = <&p3v3_aux>;
+			vss2-supply = <&p12v>;
+
+			leds {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				led@0 {
+					reg = <0>;
+					label = "rssd13:green:power";
+					default-state = "off";
+				};
+			};
+
+			regulators {
+				sw0_ssb_rssd13: sw0 {
+					regulator-name = "rssd13_12v";
+					shunt-resistor-micro-ohms = <9000>;
+					regulator-over-current-protection;
+					regulator-oc-protection-microamp = <4500000>;
+					regulator-enable-ramp-delay = <1000>;
+				};
+				sw1_ssb_rssd13: sw1 {
+					regulator-name = "rssd13_3v3";
+					shunt-resistor-micro-ohms = <100000>;
+					regulator-over-current-protection;
+					regulator-oc-protection-microamp = <410000>;
+					regulator-enable-ramp-delay = <1000>;
+				};
+			};
+		};
+	};
+	i2c@2 {
+		reg = <2>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		ssb_rssd12: regulator@3a {
+			compatible = "maxim,max5970";
+			reg = <0x3a>;
+			interrupt-parent = <&smb_svc_pex_rssd01_16>;
+			interrupts = <55 IRQ_TYPE_LEVEL_LOW>;
+
+			vss1-supply = <&p3v3_aux>;
+			vss2-supply = <&p12v>;
+
+			leds {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				led@0 {
+					reg = <0>;
+					label = "rssd12:green:power";
+					default-state = "off";
+				};
+			};
+
+			regulators {
+				sw0_ssb_rssd12: sw0 {
+					regulator-name = "rssd12_12v";
+					shunt-resistor-micro-ohms = <9000>;
+					regulator-over-current-protection;
+					regulator-oc-protection-microamp = <4500000>;
+					regulator-enable-ramp-delay = <1000>;
+				};
+				sw1_ssb_rssd12: sw1 {
+					regulator-name = "rssd12_3v3";
+					shunt-resistor-micro-ohms = <100000>;
+					regulator-over-current-protection;
+					regulator-oc-protection-microamp = <410000>;
+					regulator-enable-ramp-delay = <1000>;
+				};
+			};
+		};
+	};
+	i2c@3 {
+		reg = <3>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		ssb_rssd11: regulator@3a {
+			compatible = "maxim,max5970";
+			reg = <0x3a>;
+			interrupt-parent = <&smb_svc_pex_rssd01_16>;
+			interrupts = <54 IRQ_TYPE_LEVEL_LOW>;
+
+			vss1-supply = <&p3v3_aux>;
+			vss2-supply = <&p12v>;
+
+			leds {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				led@0 {
+					reg = <0>;
+					label = "rssd11:green:power";
+					default-state = "off";
+				};
+			};
+
+			regulators {
+				sw0_ssb_rssd11: sw0 {
+					regulator-name = "rssd11_12v";
+					shunt-resistor-micro-ohms = <9000>;
+					regulator-over-current-protection;
+					regulator-oc-protection-microamp = <4500000>;
+					regulator-enable-ramp-delay = <1000>;
+				};
+				sw1_ssb_rssd11: sw1 {
+					regulator-name = "rssd11_3v3";
+					shunt-resistor-micro-ohms = <100000>;
+					regulator-over-current-protection;
+					regulator-oc-protection-microamp = <410000>;
+					regulator-enable-ramp-delay = <1000>;
+				};
+			};
+		};
+	};
+	i2c@4 {
+		reg = <4>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		ssb_rssd10: regulator@3a {
+			compatible = "maxim,max5970";
+			reg = <0x3a>;
+			interrupt-parent = <&smb_svc_pex_rssd01_16>;
+			interrupts = <53 IRQ_TYPE_LEVEL_LOW>;
+
+			vss1-supply = <&p3v3_aux>;
+			vss2-supply = <&p12v>;
+
+			leds {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				led@0 {
+					reg = <0>;
+					label = "rssd10:green:power";
+					default-state = "off";
+				};
+			};
+
+			regulators {
+				sw0_ssb_rssd10: sw0 {
+					regulator-name = "rssd10_12v";
+					shunt-resistor-micro-ohms = <9000>;
+					regulator-over-current-protection;
+					regulator-oc-protection-microamp = <4500000>;
+					regulator-enable-ramp-delay = <1000>;
+				};
+				sw1_ssb_rssd10: sw1 {
+					regulator-name = "rssd10_3v3";
+					shunt-resistor-micro-ohms = <100000>;
+					regulator-over-current-protection;
+					regulator-oc-protection-microamp = <410000>;
+					regulator-enable-ramp-delay = <1000>;
+				};
+			};
+		};
+	};
+	i2c@5 {
+		reg = <5>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		ssb_rssd09: regulator@3a {
+			compatible = "maxim,max5970";
+			reg = <0x3a>;
+			interrupt-parent = <&smb_svc_pex_rssd01_16>;
+			interrupts = <52 IRQ_TYPE_LEVEL_LOW>;
+
+			vss1-supply = <&p3v3_aux>;
+			vss2-supply = <&p12v>;
+
+			leds {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				led@0 {
+					reg = <0>;
+					label = "rssd09:green:power";
+					default-state = "off";
+				};
+			};
+
+			regulators {
+				sw0_ssb_rssd09: sw0 {
+					regulator-name = "rssd09_12v";
+					shunt-resistor-micro-ohms = <9000>;
+					regulator-over-current-protection;
+					regulator-oc-protection-microamp = <4500000>;
+					regulator-enable-ramp-delay = <1000>;
+				};
+				sw1_ssb_rssd09: sw1 {
+					regulator-name = "rssd09_3v3";
+					shunt-resistor-micro-ohms = <100000>;
+					regulator-over-current-protection;
+					regulator-oc-protection-microamp = <410000>;
+					regulator-enable-ramp-delay = <1000>;
+				};
+			};
+		};
+	};
+	i2c@6 {
+		reg = <6>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		ssb_rssd15: regulator@3a {
+			compatible = "maxim,max5970";
+			reg = <0x3a>;
+			interrupt-parent = <&smb_svc_pex_rssd01_16>;
+			interrupts = <58 IRQ_TYPE_LEVEL_LOW>;
+
+			vss1-supply = <&p3v3_aux>;
+			vss2-supply = <&p12v>;
+
+			leds {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				led@0 {
+					reg = <0>;
+					label = "rssd15:green:power";
+					default-state = "off";
+				};
+			};
+
+			regulators {
+				sw0_ssb_rssd15: sw0 {
+					regulator-name = "rssd15_12v";
+					shunt-resistor-micro-ohms = <9000>;
+					regulator-over-current-protection;
+					regulator-oc-protection-microamp = <4500000>;
+					regulator-enable-ramp-delay = <1000>;
+				};
+				sw1_ssb_rssd15: sw1 {
+					regulator-name = "rssd15_3v3";
+					shunt-resistor-micro-ohms = <100000>;
+					regulator-over-current-protection;
+					regulator-oc-protection-microamp = <410000>;
+					regulator-enable-ramp-delay = <1000>;
+				};
+			};
+		};
+	};
+	i2c@7 {
+		reg = <7>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		ssb_rssd16: regulator@3a {
+			compatible = "maxim,max5970";
+			reg = <0x3a>;
+			interrupt-parent = <&smb_svc_pex_rssd01_16>;
+			interrupts = <59 IRQ_TYPE_LEVEL_LOW>;
+
+			vss1-supply = <&p3v3_aux>;
+			vss2-supply = <&p12v>;
+
+			leds {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				led@0 {
+					reg = <0>;
+					label = "rssd16:green:power";
+					default-state = "off";
+				};
+			};
+
+			regulators {
+				sw0_ssb_rssd16: sw0 {
+					regulator-name = "rssd16_12v";
+					shunt-resistor-micro-ohms = <9000>;
+					regulator-over-current-protection;
+					regulator-oc-protection-microamp = <4500000>;
+					regulator-enable-ramp-delay = <1000>;
+				};
+				sw1_ssb_rssd16: sw1 {
+					regulator-name = "rssd16_3v3";
+					shunt-resistor-micro-ohms = <100000>;
+					regulator-over-current-protection;
+					regulator-oc-protection-microamp = <410000>;
+					regulator-enable-ramp-delay = <1000>;
+				};
+			};
+		};
+	};
+};
diff --git a/dts/upstream/src/arm/aspeed/aspeed-bmc-ibm-system1.dts b/dts/upstream/src/arm/aspeed/aspeed-bmc-ibm-system1.dts
index f3efecc7eb8..360b9ce3c85 100644
--- a/dts/upstream/src/arm/aspeed/aspeed-bmc-ibm-system1.dts
+++ b/dts/upstream/src/arm/aspeed/aspeed-bmc-ibm-system1.dts
@@ -370,17 +370,17 @@
 	/*K0-K7*/	"","","","","","","","",
 	/*L0-L7*/	"","","","","","","","bmc-ready",
 	/*M0-M7*/	"","","","","","","","",
-	/*N0-N7*/	"","","","","","","","",
+	/*N0-N7*/	"fpga-debug-enable","","","","","","","",
 	/*O0-O7*/	"","","","","","","","",
 	/*P0-P7*/	"","","","","","","","bmc-hb",
-	/*Q0-Q7*/	"","","","","","","","",
+	/*Q0-Q7*/	"","","","","","","pch-ready","",
 	/*R0-R7*/	"","","","","","","","",
 	/*S0-S7*/	"","","","","","","rear-enc-fault0","rear-enc-id0",
 	/*T0-T7*/	"","","","","","","","",
 	/*U0-U7*/	"","","","","","","","",
 	/*V0-V7*/	"","rtc-battery-voltage-read-enable","","power-chassis-control","","","","",
 	/*W0-W7*/	"","","","","","","","",
-	/*X0-X7*/	"","power-chassis-good","","","","","","",
+	/*X0-X7*/	"fpga-pgood","power-chassis-good","pch-pgood","","","","","",
 	/*Y0-Y7*/	"","","","","","","","",
 	/*Z0-Z7*/	"","","","","","","","";
 };
@@ -398,6 +398,12 @@
 	clk-phase-mmc-hs200 = <180>, <180>;
 };
 
+&sgpiom0 {
+	status = "okay";
+	ngpios = <128>;
+	bus-frequency = <1000000>;
+};
+
 &ibt {
 	status = "okay";
 };
@@ -464,6 +470,15 @@
 	aspeed,lpc-interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
 };
 
+&peci0 {
+	status = "okay";
+};
+
+&lpc_snoop {
+	status = "okay";
+	snoop-ports = <0x80>, <0x81>;
+};
+
 &i2c0 {
 	status = "okay";
 
@@ -666,22 +681,22 @@
 	status = "okay";
 
 	power-supply@58 {
-		compatible = "ibm,cffps";
+		compatible = "intel,crps185";
 		reg = <0x58>;
 	};
 
 	power-supply@59 {
-		compatible = "ibm,cffps";
+		compatible = "intel,crps185";
 		reg = <0x59>;
 	};
 
 	power-supply@5a {
-		compatible = "ibm,cffps";
+		compatible = "intel,crps185";
 		reg = <0x5a>;
 	};
 
 	power-supply@5b {
-		compatible = "ibm,cffps";
+		compatible = "intel,crps185";
 		reg = <0x5b>;
 	};
 };
@@ -1007,6 +1022,7 @@
 
 &i2c8 {
 	status = "okay";
+	bus-frequency = <400000>;
 
 	i2c-mux@71 {
 		compatible = "nxp,pca9548";
@@ -1468,6 +1484,7 @@
 
 &i2c15 {
 	status = "okay";
+	bus-frequency = <400000>;
 
 	i2c-mux@71 {
 		compatible = "nxp,pca9548";
diff --git a/dts/upstream/src/arm/aspeed/aspeed-bmc-quanta-s6q.dts b/dts/upstream/src/arm/aspeed/aspeed-bmc-quanta-s6q.dts
index 983853eedae..fd361cf073c 100644
--- a/dts/upstream/src/arm/aspeed/aspeed-bmc-quanta-s6q.dts
+++ b/dts/upstream/src/arm/aspeed/aspeed-bmc-quanta-s6q.dts
@@ -381,7 +381,7 @@
 			#size-cells = <0>;
 			reg = <5>;
 
-			U190_fru@51 {
+			eeprom@51 {
 				compatible = "atmel,24c128";
 				reg = <0x51>;
 				pagesize = <32>;
@@ -460,7 +460,7 @@
 	status = "okay";
 
 	/* MB FRU (U173) @ 0xA2 */
-	mb_fru: mb_fru@51 {
+	mb_fru: eeprom@51 {
 		compatible = "atmel,24c128";
 		reg = <0x51>;
 		pagesize = <32>;
@@ -472,7 +472,7 @@
 		reg = <0x4a>;
 	};
 
-	FP_U4_fru@52 {
+	eeprom@52 {
 		compatible = "atmel,24c02";
 		reg = <0x52>;
 		pagesize = <16>;
@@ -593,7 +593,7 @@
 	status = "okay";
 
 	/* SCM FRU (U19) @ 0xA2 */
-	scm_fru: scm_fru@51 {
+	scm_fru: eeprom@51 {
 		compatible = "atmel,24c128";
 		reg = <0x51>;
 		pagesize = <32>;
diff --git a/dts/upstream/src/arm/aspeed/aspeed-bmc-vegman-rx20.dts b/dts/upstream/src/arm/aspeed/aspeed-bmc-vegman-rx20.dts
index b8f0b08018a..98f3e043770 100644
--- a/dts/upstream/src/arm/aspeed/aspeed-bmc-vegman-rx20.dts
+++ b/dts/upstream/src/arm/aspeed/aspeed-bmc-vegman-rx20.dts
@@ -154,7 +154,7 @@
 					#address-cells = <1>;
 					#size-cells = <0>;
 					reg = <7>;
-					at24@50 {
+					eeprom@50 {
 						compatible = "atmel,24c64";
 						reg = <0x50>;
 						pagesize = <32>;
@@ -196,7 +196,7 @@
 					#address-cells = <1>;
 					#size-cells = <0>;
 					reg = <7>;
-					at24@50 {
+					eeprom@50 {
 						compatible = "atmel,24c64";
 						reg = <0x50>;
 						pagesize = <32>;
@@ -205,7 +205,7 @@
 					};
 				};
 			};
-			at24@50 {
+			eeprom@50 {
 				compatible = "atmel,24c64";
 				reg = <0x50>;
 				pagesize = <32>;
diff --git a/dts/upstream/src/arm/aspeed/aspeed-bmc-vegman.dtsi b/dts/upstream/src/arm/aspeed/aspeed-bmc-vegman.dtsi
index 1a5b25b2ea2..16815eede71 100644
--- a/dts/upstream/src/arm/aspeed/aspeed-bmc-vegman.dtsi
+++ b/dts/upstream/src/arm/aspeed/aspeed-bmc-vegman.dtsi
@@ -291,7 +291,7 @@
 	/* SMB_BMC_MGMT_LVC3 */
 	status = "okay";
 
-	at24@50 {
+	eeprom@50 {
 		compatible = "atmel,24c64";
 		reg = <0x50>;
 		pagesize = <32>;
diff --git a/dts/upstream/src/arm/broadcom/bcm2711-rpi.dtsi b/dts/upstream/src/arm/broadcom/bcm2711-rpi.dtsi
index 6bf4241fe3b..c78ed064d16 100644
--- a/dts/upstream/src/arm/broadcom/bcm2711-rpi.dtsi
+++ b/dts/upstream/src/arm/broadcom/bcm2711-rpi.dtsi
@@ -1,7 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0
 #include "bcm2835-rpi.dtsi"
 
-#include <dt-bindings/power/raspberrypi-power.h>
 #include <dt-bindings/reset/raspberrypi,firmware-reset.h>
 
 / {
@@ -101,7 +100,3 @@
 &vchiq {
 	interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 };
-
-&xhci {
-	power-domains = <&power RPI_POWER_DOMAIN_USB>;
-};
diff --git a/dts/upstream/src/arm/broadcom/bcm2711.dtsi b/dts/upstream/src/arm/broadcom/bcm2711.dtsi
index e4e42af21ef..c06d9f5e53c 100644
--- a/dts/upstream/src/arm/broadcom/bcm2711.dtsi
+++ b/dts/upstream/src/arm/broadcom/bcm2711.dtsi
@@ -134,7 +134,7 @@
 			clocks = <&clocks BCM2835_CLOCK_UART>,
 				 <&clocks BCM2835_CLOCK_VPU>;
 			clock-names = "uartclk", "apb_pclk";
-			arm,primecell-periphid = <0x00241011>;
+			arm,primecell-periphid = <0x00341011>;
 			status = "disabled";
 		};
 
@@ -145,7 +145,7 @@
 			clocks = <&clocks BCM2835_CLOCK_UART>,
 				 <&clocks BCM2835_CLOCK_VPU>;
 			clock-names = "uartclk", "apb_pclk";
-			arm,primecell-periphid = <0x00241011>;
+			arm,primecell-periphid = <0x00341011>;
 			status = "disabled";
 		};
 
@@ -156,7 +156,7 @@
 			clocks = <&clocks BCM2835_CLOCK_UART>,
 				 <&clocks BCM2835_CLOCK_VPU>;
 			clock-names = "uartclk", "apb_pclk";
-			arm,primecell-periphid = <0x00241011>;
+			arm,primecell-periphid = <0x00341011>;
 			status = "disabled";
 		};
 
@@ -167,7 +167,7 @@
 			clocks = <&clocks BCM2835_CLOCK_UART>,
 				 <&clocks BCM2835_CLOCK_VPU>;
 			clock-names = "uartclk", "apb_pclk";
-			arm,primecell-periphid = <0x00241011>;
+			arm,primecell-periphid = <0x00341011>;
 			status = "disabled";
 		};
 
@@ -451,8 +451,6 @@
 					  IRQ_TYPE_LEVEL_LOW)>,
 			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) |
 					  IRQ_TYPE_LEVEL_LOW)>;
-		/* This only applies to the ARMv7 stub */
-		arm,cpu-registers-not-fw-configured;
 	};
 
 	cpus: cpus {
@@ -610,6 +608,7 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
+			power-domains = <&pm BCM2835_POWER_DOMAIN_USB>;
 			/* DWC2 and this IP block share the same USB PHY,
 			 * enabling both at the same time results in lockups.
 			 * So keep this node disabled and let the bootloader
@@ -1177,6 +1176,7 @@
 };
 
 &uart0 {
+	arm,primecell-periphid = <0x00341011>;
 	interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
 };
 
diff --git a/dts/upstream/src/arm/broadcom/bcm4709-asus-rt-ac3200.dts b/dts/upstream/src/arm/broadcom/bcm4709-asus-rt-ac3200.dts
index 53cb0c58f6d..3da2daee0c8 100644
--- a/dts/upstream/src/arm/broadcom/bcm4709-asus-rt-ac3200.dts
+++ b/dts/upstream/src/arm/broadcom/bcm4709-asus-rt-ac3200.dts
@@ -124,19 +124,19 @@
 		};
 
 		port@1 {
-			label = "lan1";
+			label = "lan4";
 		};
 
 		port@2 {
-			label = "lan2";
+			label = "lan3";
 		};
 
 		port@3 {
-			label = "lan3";
+			label = "lan2";
 		};
 
 		port@4 {
-			label = "lan4";
+			label = "lan1";
 		};
 	};
 };
diff --git a/dts/upstream/src/arm/broadcom/bcm47094-asus-rt-ac5300.dts b/dts/upstream/src/arm/broadcom/bcm47094-asus-rt-ac5300.dts
index 6c666dc7ad2..01ec8c03686 100644
--- a/dts/upstream/src/arm/broadcom/bcm47094-asus-rt-ac5300.dts
+++ b/dts/upstream/src/arm/broadcom/bcm47094-asus-rt-ac5300.dts
@@ -126,11 +126,11 @@
 
 	ports {
 		port@0 {
-			label = "lan4";
+			label = "wan";
 		};
 
 		port@1 {
-			label = "lan3";
+			label = "lan1";
 		};
 
 		port@2 {
@@ -138,11 +138,11 @@
 		};
 
 		port@3 {
-			label = "lan1";
+			label = "lan3";
 		};
 
 		port@4 {
-			label = "wan";
+			label = "lan4";
 		};
 	};
 };
diff --git a/dts/upstream/src/arm/broadcom/bcm53015-meraki-mr26.dts b/dts/upstream/src/arm/broadcom/bcm53015-meraki-mr26.dts
index 0bf5106f701..08abfdc63d1 100644
--- a/dts/upstream/src/arm/broadcom/bcm53015-meraki-mr26.dts
+++ b/dts/upstream/src/arm/broadcom/bcm53015-meraki-mr26.dts
@@ -59,6 +59,9 @@
 
 &gmac0 {
 	status = "okay";
+
+	nvmem-cells = <&macaddr_board_config_66>;
+	nvmem-cell-names = "mac-address";
 };
 
 &gmac1 {
@@ -102,8 +105,25 @@
 		};
 
 		partition@800000 {
+			compatible = "linux,ubi";
 			label = "ubi";
 			reg = <0x800000 0x7780000>;
+
+			volumes {
+				ubi-volume-board-config {
+					volname = "board-config";
+
+					nvmem-layout {
+						compatible = "fixed-layout";
+						#address-cells = <1>;
+						#size-cells = <1>;
+
+						macaddr_board_config_66: macaddr@66 {
+							reg = <0x66 0x6>;
+						};
+					};
+				};
+			};
 		};
 	};
 };
diff --git a/dts/upstream/src/arm/broadcom/bcm53340-ubnt-unifi-switch8.dts b/dts/upstream/src/arm/broadcom/bcm53340-ubnt-unifi-switch8.dts
index 975f854f652..08cf1220b65 100644
--- a/dts/upstream/src/arm/broadcom/bcm53340-ubnt-unifi-switch8.dts
+++ b/dts/upstream/src/arm/broadcom/bcm53340-ubnt-unifi-switch8.dts
@@ -32,7 +32,6 @@
 
 &qspi {
 	status = "okay";
-	bspi-sel = <0>;
 
 	flash: flash@0 {
 		compatible = "m25p80";
diff --git a/dts/upstream/src/arm/broadcom/bcm6846-genexis-xg6846b.dts b/dts/upstream/src/arm/broadcom/bcm6846-genexis-xg6846b.dts
new file mode 100644
index 00000000000..a3616fb7b3a
--- /dev/null
+++ b/dts/upstream/src/arm/broadcom/bcm6846-genexis-xg6846b.dts
@@ -0,0 +1,244 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2024 Linus Walleij <linus.walleij@linaro.org>
+ */
+
+/dts-v1/;
+
+#include "bcm6846.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
+
+/ {
+	model = "Genexis XG6846B Ethernet layer 2/3 router";
+	compatible = "genexis,xg6846b", "brcm,bcm6846", "brcm,bcmbca";
+
+	aliases {
+		serial0 = &uart0;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	/* Micron D9PTK 256 MB RAM */
+	memory@0 {
+		device_type = "memory";
+		reg = <0x0 0x10000000>;
+	};
+
+	reserved-memory {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+
+		secondary-boot@0 {
+			no-map;
+			reg = <0x00000000 0x00008000>;
+		};
+		pmc3-firmware@8000 {
+			no-map;
+			reg = <0x00008000 0x00100000>;
+		};
+	};
+
+	gpio-keys {
+		compatible = "gpio-keys-polled";
+		poll-interval = <20000>;
+
+		/* Called "canyon rescue button" in the vendor DTB */
+		button-restart {
+			label = "Reset";
+			linux,code = <KEY_RESTART>;
+			gpios = <&gpio0 41 GPIO_ACTIVE_LOW>;
+		};
+	};
+};
+
+&gpio0 {
+	status = "okay";
+};
+
+&gpio1 {
+	status = "okay";
+};
+
+&gpio2 {
+	status = "okay";
+	/* Totally 79 GPIOs are available */
+	ngpios = <15>;
+};
+
+&uart0 {
+	status = "okay";
+};
+
+&leds {
+	status = "okay";
+	brcm,serial-shift-bits = <16>;
+
+	led@0 {
+		reg = <0>;
+		active-low;
+		function = "ext";
+		color = <LED_COLOR_ID_GREEN>;
+	};
+
+	led@1 {
+		reg = <1>;
+		active-low;
+		function = "ext";
+		color = <LED_COLOR_ID_AMBER>;
+	};
+
+	led@3 {
+		reg = <3>;
+		active-low;
+		function = LED_FUNCTION_WAN;
+		color = <LED_COLOR_ID_AMBER>;
+	};
+
+	led@4 {
+		reg = <4>;
+		active-low;
+		function = LED_FUNCTION_WAN;
+		color = <LED_COLOR_ID_GREEN>;
+	};
+
+	led@5 {
+		reg = <5>;
+		active-low;
+		function = LED_FUNCTION_POWER;
+		color = <LED_COLOR_ID_GREEN>;
+	};
+
+	led@6 {
+		reg = <6>;
+		active-low;
+		function = LED_FUNCTION_POWER;
+		color = <LED_COLOR_ID_RED>;
+	};
+
+	led@15 {
+		reg = <15>;
+		active-low;
+		function = LED_FUNCTION_USB;
+		color = <LED_COLOR_ID_GREEN>;
+	};
+
+	led@7 {
+		/* Activity 03 */
+		reg = <7>;
+		active-low;
+		function = "lan1";
+		color = <LED_COLOR_ID_AMBER>;
+	};
+
+	led@8 {
+		/* Activity 04 */
+		reg = <8>;
+		active-low;
+		function = "lan1";
+		color = <LED_COLOR_ID_GREEN>;
+	};
+
+	led@9 {
+		/* Activity 03 */
+		reg = <9>;
+		active-low;
+		function = "lan2";
+		color = <LED_COLOR_ID_AMBER>;
+	};
+
+	led@10 {
+		/* Activity 04 */
+		reg = <10>;
+		active-low;
+		function = "lan2";
+		color = <LED_COLOR_ID_GREEN>;
+	};
+
+	led@11 {
+		/* Activity 03 */
+		reg = <11>;
+		active-low;
+		function = "lan3";
+		color = <LED_COLOR_ID_AMBER>;
+	};
+
+	led@12 {
+		/* Activity 04 */
+		reg = <12>;
+		active-low;
+		function = "lan3";
+		color = <LED_COLOR_ID_GREEN>;
+	};
+
+	led@13 {
+		/* Activity 03 */
+		reg = <13>;
+		active-low;
+		function = "lan4";
+		color = <LED_COLOR_ID_AMBER>;
+	};
+
+	led@14 {
+		/* Activity 04 */
+		reg = <14>;
+		active-low;
+		function = "lan4";
+		color = <LED_COLOR_ID_GREEN>;
+	};
+};
+
+&hsspi {
+	status = "okay";
+};
+
+&nand_controller {
+	brcm,wp-not-connected;
+	status = "okay";
+};
+
+&nandcs {
+	nand-on-flash-bbt;
+	brcm,nand-ecc-use-strap;
+
+	/* Winbond W29N02GV, 256MB with 128KB erase blocks */
+	partitions {
+		compatible = "fixed-partitions";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		loader@0 {
+			label = "loader";
+			reg = <0x00000000 0x00400000>;
+		};
+		image@400000 {
+			label = "image";
+			reg = <0x00400000 0x0fb00000>;
+		};
+		/* 0x00ff0000-0x00ffffff: bad block list */
+	};
+};
+
+&mdio {
+	status = "okay";
+
+	phy1: ethernet-phy@1 {
+		reg = <1>;
+	};
+	phy2: ethernet-phy@2 {
+		reg = <2>;
+	};
+	phy3: ethernet-phy@3 {
+		reg = <3>;
+	};
+	phy4: ethernet-phy@4 {
+		reg = <4>;
+	};
+	phy21: ethernet-phy@21 {
+		reg = <21>;
+	};
+};
diff --git a/dts/upstream/src/arm/broadcom/bcm6846.dtsi b/dts/upstream/src/arm/broadcom/bcm6846.dtsi
index ee361cb00b7..e0e06af3fe8 100644
--- a/dts/upstream/src/arm/broadcom/bcm6846.dtsi
+++ b/dts/upstream/src/arm/broadcom/bcm6846.dtsi
@@ -99,6 +99,91 @@
 		#size-cells = <1>;
 		ranges = <0 0xff800000 0x800000>;
 
+		watchdog@480 {
+			compatible = "brcm,bcm6345-wdt";
+			reg = <0x480 0x10>;
+		};
+
+		/* GPIOs 0 .. 31 */
+		gpio0: gpio@500 {
+			compatible = "brcm,bcm6345-gpio";
+			reg = <0x500 0x04>, <0x520 0x04>;
+			reg-names = "dirout", "dat";
+			gpio-controller;
+			#gpio-cells = <2>;
+			status = "disabled";
+		};
+
+		/* GPIOs 32 .. 63 */
+		gpio1: gpio@504 {
+			compatible = "brcm,bcm6345-gpio";
+			reg = <0x504 0x04>, <0x524 0x04>;
+			reg-names = "dirout", "dat";
+			gpio-controller;
+			#gpio-cells = <2>;
+			status = "disabled";
+		};
+
+		/* GPIOs 64 .. 95 */
+		gpio2: gpio@508 {
+			compatible = "brcm,bcm6345-gpio";
+			reg = <0x508 0x04>, <0x528 0x04>;
+			reg-names = "dirout", "dat";
+			gpio-controller;
+			#gpio-cells = <2>;
+			status = "disabled";
+		};
+
+		/* GPIOs 96 .. 127 */
+		gpio3: gpio@50c {
+			compatible = "brcm,bcm6345-gpio";
+			reg = <0x50c 0x04>, <0x52c 0x04>;
+			reg-names = "dirout", "dat";
+			gpio-controller;
+			#gpio-cells = <2>;
+			status = "disabled";
+		};
+
+		/* GPIOs 128 .. 159 */
+		gpio4: gpio@510 {
+			compatible = "brcm,bcm6345-gpio";
+			reg = <0x510 0x04>, <0x530 0x04>;
+			reg-names = "dirout", "dat";
+			gpio-controller;
+			#gpio-cells = <2>;
+			status = "disabled";
+		};
+
+		/* GPIOs 160 .. 191 */
+		gpio5: gpio@514 {
+			compatible = "brcm,bcm6345-gpio";
+			reg = <0x514 0x04>, <0x534 0x04>;
+			reg-names = "dirout", "dat";
+			gpio-controller;
+			#gpio-cells = <2>;
+			status = "disabled";
+		};
+
+		/* GPIOs 192 .. 223 */
+		gpio6: gpio@518 {
+			compatible = "brcm,bcm6345-gpio";
+			reg = <0x518 0x04>, <0x538 0x04>;
+			reg-names = "dirout", "dat";
+			gpio-controller;
+			#gpio-cells = <2>;
+			status = "disabled";
+		};
+
+		/* GPIOs 224 .. 255 */
+		gpio7: gpio@51c {
+			compatible = "brcm,bcm6345-gpio";
+			reg = <0x51c 0x04>, <0x53c 0x04>;
+			reg-names = "dirout", "dat";
+			gpio-controller;
+			#gpio-cells = <2>;
+			status = "disabled";
+		};
+
 		uart0: serial@640 {
 			compatible = "brcm,bcm6345-uart";
 			reg = <0x640 0x1b>;
@@ -108,6 +193,19 @@
 			status = "disabled";
 		};
 
+		rng@b80 {
+			compatible = "brcm,iproc-rng200";
+			reg = <0xb80 0x28>;
+		};
+
+		leds: led-controller@800 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "brcm,bcm63138-leds";
+			reg = <0x800 0xdc>;
+			status = "disabled";
+		};
+
 		hsspi: spi@1000 {
 			#address-cells = <1>;
 			#size-cells = <0>;
@@ -133,5 +231,27 @@
 				reg = <0>;
 			};
 		};
+
+		mdio: mdio@2060 {
+			compatible = "brcm,bcm6846-mdio";
+			reg = <0x02060 0x10>, <0x5a068 0x4>;
+			reg-names = "mdio", "mdio_indir_rw";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		pl081_dma: dma-controller@59000 {
+			compatible = "arm,pl081", "arm,primecell";
+			// The magic B105F00D info is missing
+			arm,primecell-periphid = <0x00041081>;
+			reg = <0x59000 0x1000>;
+			interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
+			memcpy-burst-size = <256>;
+			memcpy-bus-width = <32>;
+			clocks = <&periph_clk>;
+			clock-names = "apb_pclk";
+			#dma-cells = <2>;
+		};
 	};
 };
diff --git a/dts/upstream/src/arm/broadcom/bcm953012hr.dts b/dts/upstream/src/arm/broadcom/bcm953012hr.dts
index b070b69466b..b728cd54715 100644
--- a/dts/upstream/src/arm/broadcom/bcm953012hr.dts
+++ b/dts/upstream/src/arm/broadcom/bcm953012hr.dts
@@ -74,7 +74,6 @@
 &spi_nor {
 	status = "okay";
 	spi-max-frequency = <62500000>;
-	m25p,default-addr-width = <3>;
 
 	#address-cells = <1>;
 	#size-cells = <1>;
diff --git a/dts/upstream/src/arm/broadcom/bcm953012k.dts b/dts/upstream/src/arm/broadcom/bcm953012k.dts
index f1e6bcaa1ed..27c0992f185 100644
--- a/dts/upstream/src/arm/broadcom/bcm953012k.dts
+++ b/dts/upstream/src/arm/broadcom/bcm953012k.dts
@@ -84,7 +84,6 @@
 &spi_nor {
 	status = "okay";
 	spi-max-frequency = <62500000>;
-	m25p,default-addr-width = <3>;
 
 	#address-cells = <1>;
 	#size-cells = <1>;
diff --git a/dts/upstream/src/arm/broadcom/bcm958522er.dts b/dts/upstream/src/arm/broadcom/bcm958522er.dts
index 15f023656df..2f20f86bd31 100644
--- a/dts/upstream/src/arm/broadcom/bcm958522er.dts
+++ b/dts/upstream/src/arm/broadcom/bcm958522er.dts
@@ -135,7 +135,6 @@
 
 &qspi {
 	status = "okay";
-	bspi-sel = <0>;
 	flash: flash@0 {
 		#address-cells = <1>;
 		#size-cells = <1>;
diff --git a/dts/upstream/src/arm/broadcom/bcm958525er.dts b/dts/upstream/src/arm/broadcom/bcm958525er.dts
index 9b9c225a1fb..980c03f74a1 100644
--- a/dts/upstream/src/arm/broadcom/bcm958525er.dts
+++ b/dts/upstream/src/arm/broadcom/bcm958525er.dts
@@ -135,7 +135,6 @@
 
 &qspi {
 	status = "okay";
-	bspi-sel = <0>;
 	flash: flash@0 {
 		#address-cells = <1>;
 		#size-cells = <1>;
diff --git a/dts/upstream/src/arm/broadcom/bcm958525xmc.dts b/dts/upstream/src/arm/broadcom/bcm958525xmc.dts
index ca931145273..440bb2d617f 100644
--- a/dts/upstream/src/arm/broadcom/bcm958525xmc.dts
+++ b/dts/upstream/src/arm/broadcom/bcm958525xmc.dts
@@ -151,7 +151,6 @@
 
 &qspi {
 	status = "okay";
-	bspi-sel = <0>;
 	flash: flash@0 {
 		#address-cells = <1>;
 		#size-cells = <1>;
diff --git a/dts/upstream/src/arm/broadcom/bcm958622hr.dts b/dts/upstream/src/arm/broadcom/bcm958622hr.dts
index 9db3c851451..116f3a7c3bc 100644
--- a/dts/upstream/src/arm/broadcom/bcm958622hr.dts
+++ b/dts/upstream/src/arm/broadcom/bcm958622hr.dts
@@ -139,7 +139,6 @@
 
 &qspi {
 	status = "okay";
-	bspi-sel = <0>;
 	flash: flash@0 {
 		#address-cells = <1>;
 		#size-cells = <1>;
diff --git a/dts/upstream/src/arm/broadcom/bcm958623hr.dts b/dts/upstream/src/arm/broadcom/bcm958623hr.dts
index 32786e7c4e1..fc6ab73ecf5 100644
--- a/dts/upstream/src/arm/broadcom/bcm958623hr.dts
+++ b/dts/upstream/src/arm/broadcom/bcm958623hr.dts
@@ -143,7 +143,6 @@
 
 &qspi {
 	status = "okay";
-	bspi-sel = <0>;
 	flash: flash@0 {
 		#address-cells = <1>;
 		#size-cells = <1>;
diff --git a/dts/upstream/src/arm/broadcom/bcm958625hr.dts b/dts/upstream/src/arm/broadcom/bcm958625hr.dts
index 74263d98de7..a9b6aa04d57 100644
--- a/dts/upstream/src/arm/broadcom/bcm958625hr.dts
+++ b/dts/upstream/src/arm/broadcom/bcm958625hr.dts
@@ -150,7 +150,6 @@
 
 &qspi {
 	status = "okay";
-	bspi-sel = <0>;
 	flash: flash@0 {
 		#address-cells = <1>;
 		#size-cells = <1>;
diff --git a/dts/upstream/src/arm/broadcom/bcm958625k.dts b/dts/upstream/src/arm/broadcom/bcm958625k.dts
index 69ebc7a913a..7996116fc92 100644
--- a/dts/upstream/src/arm/broadcom/bcm958625k.dts
+++ b/dts/upstream/src/arm/broadcom/bcm958625k.dts
@@ -154,7 +154,6 @@
 
 &qspi {
 	status = "okay";
-	bspi-sel = <0>;
 	flash: flash@0 {
 		#address-cells = <1>;
 		#size-cells = <1>;
diff --git a/dts/upstream/src/arm/broadcom/bcm988312hr.dts b/dts/upstream/src/arm/broadcom/bcm988312hr.dts
index e96bc3f2d5c..663a3f27b6e 100644
--- a/dts/upstream/src/arm/broadcom/bcm988312hr.dts
+++ b/dts/upstream/src/arm/broadcom/bcm988312hr.dts
@@ -139,7 +139,6 @@
 
 &qspi {
 	status = "okay";
-	bspi-sel = <0>;
 	flash: flash@0 {
 		#address-cells = <1>;
 		#size-cells = <1>;
diff --git a/dts/upstream/src/arm/intel/socfpga/socfpga_arria10.dtsi b/dts/upstream/src/arm/intel/socfpga/socfpga_arria10.dtsi
index 6b6e77596ff..b108265e9bd 100644
--- a/dts/upstream/src/arm/intel/socfpga/socfpga_arria10.dtsi
+++ b/dts/upstream/src/arm/intel/socfpga/socfpga_arria10.dtsi
@@ -440,7 +440,7 @@
 			clocks = <&l4_mp_clk>, <&peri_emac_ptp_clk>;
 			clock-names = "stmmaceth", "ptp_ref";
 			resets = <&rst EMAC0_RESET>, <&rst EMAC0_OCP_RESET>;
-			reset-names = "stmmaceth", "ahb";
+			reset-names = "stmmaceth", "stmmaceth-ocp";
 			snps,axi-config = <&socfpga_axi_setup>;
 			status = "disabled";
 		};
@@ -460,7 +460,7 @@
 			clocks = <&l4_mp_clk>, <&peri_emac_ptp_clk>;
 			clock-names = "stmmaceth", "ptp_ref";
 			resets = <&rst EMAC1_RESET>, <&rst EMAC1_OCP_RESET>;
-			reset-names = "stmmaceth", "ahb";
+			reset-names = "stmmaceth", "stmmaceth-ocp";
 			snps,axi-config = <&socfpga_axi_setup>;
 			status = "disabled";
 		};
@@ -480,7 +480,7 @@
 			clocks = <&l4_mp_clk>, <&peri_emac_ptp_clk>;
 			clock-names = "stmmaceth", "ptp_ref";
 			resets = <&rst EMAC2_RESET>, <&rst EMAC2_OCP_RESET>;
-			reset-names = "stmmaceth", "ahb";
+			reset-names = "stmmaceth", "stmmaceth-ocp";
 			snps,axi-config = <&socfpga_axi_setup>;
 			status = "disabled";
 		};
diff --git a/dts/upstream/src/arm/intel/socfpga/socfpga_cyclone5_mcvevk.dts b/dts/upstream/src/arm/intel/socfpga/socfpga_cyclone5_mcvevk.dts
index ceaec29770c..c1e1264bcb0 100644
--- a/dts/upstream/src/arm/intel/socfpga/socfpga_cyclone5_mcvevk.dts
+++ b/dts/upstream/src/arm/intel/socfpga/socfpga_cyclone5_mcvevk.dts
@@ -50,8 +50,6 @@
 
 	stmpe1: stmpe811@41 {
 		compatible = "st,stmpe811";
-		#address-cells = <1>;
-		#size-cells = <0>;
 		reg = <0x41>;
 		id = <0>;
 		blocks = <0x5>;
diff --git a/dts/upstream/src/arm/intel/socfpga/socfpga_cyclone5_socdk.dts b/dts/upstream/src/arm/intel/socfpga/socfpga_cyclone5_socdk.dts
index d37a982e857..97622febc44 100644
--- a/dts/upstream/src/arm/intel/socfpga/socfpga_cyclone5_socdk.dts
+++ b/dts/upstream/src/arm/intel/socfpga/socfpga_cyclone5_socdk.dts
@@ -151,12 +151,6 @@
 
 &spi0 {
 	status = "okay";
-
-	spidev@0 {
-		compatible = "rohm,dh2228fv";
-		reg = <0>;
-		spi-max-frequency = <1000000>;
-	};
 };
 
 &usb1 {
diff --git a/dts/upstream/src/arm/marvell/mmp2-olpc-xo-1-75.dts b/dts/upstream/src/arm/marvell/mmp2-olpc-xo-1-75.dts
index 55ea87870af..86c425b72fa 100644
--- a/dts/upstream/src/arm/marvell/mmp2-olpc-xo-1-75.dts
+++ b/dts/upstream/src/arm/marvell/mmp2-olpc-xo-1-75.dts
@@ -113,8 +113,8 @@
 			  "Headphones", "HPOR",
 			  "MIC2", "Mic Jack";
 		widgets = "Headphone", "Headphones", "Microphone", "Mic Jack";
-		hp-det-gpio = <&gpio 97 GPIO_ACTIVE_HIGH>;
-		mic-det-gpio = <&gpio 96 GPIO_ACTIVE_HIGH>;
+		hp-det-gpios = <&gpio 97 GPIO_ACTIVE_HIGH>;
+		mic-det-gpios = <&gpio 96 GPIO_ACTIVE_HIGH>;
 	};
 
 	soc {
diff --git a/dts/upstream/src/arm/mediatek/mt7623.dtsi b/dts/upstream/src/arm/mediatek/mt7623.dtsi
index 814586abc29..fd7a89cc337 100644
--- a/dts/upstream/src/arm/mediatek/mt7623.dtsi
+++ b/dts/upstream/src/arm/mediatek/mt7623.dtsi
@@ -308,7 +308,7 @@
 		clock-names = "spi", "wrap";
 	};
 
-	cir: cir@10013000 {
+	cir: ir-receiver@10013000 {
 		compatible = "mediatek,mt7623-cir";
 		reg = <0 0x10013000 0 0x1000>;
 		interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_LOW>;
diff --git a/dts/upstream/src/arm/microchip/at91-sam9x75_curiosity.dts b/dts/upstream/src/arm/microchip/at91-sam9x75_curiosity.dts
index 87b6ea97590..1a6a909a504 100644
--- a/dts/upstream/src/arm/microchip/at91-sam9x75_curiosity.dts
+++ b/dts/upstream/src/arm/microchip/at91-sam9x75_curiosity.dts
@@ -88,8 +88,6 @@
 };
 
 &i2c6 {
-	#address-cells = <1>;
-	#size-cells = <0>;
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_flx6_default>;
 	i2c-analog-filter;
@@ -200,6 +198,52 @@
 	};
 };
 
+&flx7 {
+	atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_TWI>;
+	status = "okay";
+};
+
+&i2c7 {
+	dmas = <0>, <0>;
+	i2c-analog-filter;
+	i2c-digital-filter;
+	i2c-digital-filter-width-ns = <35>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_flx7_default>;
+	status = "okay";
+
+	power-monitor@10 {
+		compatible = "microchip,pac1934";
+		reg = <0x10>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		channel@1 {
+			reg = <0x1>;
+			shunt-resistor-micro-ohms = <10000>;
+			label = "VDD3V3";
+		};
+
+		channel@2 {
+			reg = <0x2>;
+			shunt-resistor-micro-ohms = <10000>;
+			label = "DCDC4";
+		};
+
+		channel@3 {
+			reg = <0x3>;
+			shunt-resistor-micro-ohms = <10000>;
+			label = "VDDCORE";
+		};
+
+		channel@4 {
+			reg = <0x4>;
+			shunt-resistor-micro-ohms = <10000>;
+			label = "VDDIODDR";
+		};
+	};
+};
+
 &i2s {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_i2s_default>;
@@ -233,6 +277,12 @@
 				<AT91_PIOA 24 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>,
 				<AT91_PIOA 25 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;
 		};
+
+		pinctrl_flx7_default: flx7-default {
+			atmel,pins =
+				<AT91_PIOC 0 AT91_PERIPH_C AT91_PINCTRL_PULL_UP>,
+				<AT91_PIOC 1 AT91_PERIPH_C AT91_PINCTRL_PULL_UP>;
+		};
 	};
 
 	gpio-keys {
diff --git a/dts/upstream/src/arm/microchip/at91-sama5d27_wlsom1_ek.dts b/dts/upstream/src/arm/microchip/at91-sama5d27_wlsom1_ek.dts
index 15239834d88..35a933eec57 100644
--- a/dts/upstream/src/arm/microchip/at91-sama5d27_wlsom1_ek.dts
+++ b/dts/upstream/src/arm/microchip/at91-sama5d27_wlsom1_ek.dts
@@ -197,6 +197,7 @@
 
 &sdmmc0 {
 	bus-width = <4>;
+	no-1-8-v;
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_sdmmc0_default>;
 	status = "okay";
diff --git a/dts/upstream/src/arm/microchip/at91-sama5d29_curiosity.dts b/dts/upstream/src/arm/microchip/at91-sama5d29_curiosity.dts
index b6684bf67d3..7be21578154 100644
--- a/dts/upstream/src/arm/microchip/at91-sama5d29_curiosity.dts
+++ b/dts/upstream/src/arm/microchip/at91-sama5d29_curiosity.dts
@@ -514,6 +514,7 @@
 
 &sdmmc0 {
 	bus-width = <4>;
+	no-1-8-v;
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_sdmmc0_default>;
 	disable-wp;
diff --git a/dts/upstream/src/arm/microchip/at91-sama7d65_curiosity.dts b/dts/upstream/src/arm/microchip/at91-sama7d65_curiosity.dts
new file mode 100644
index 00000000000..0f86360fb73
--- /dev/null
+++ b/dts/upstream/src/arm/microchip/at91-sama7d65_curiosity.dts
@@ -0,0 +1,89 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ *  at91-sama7d65_curiosity.dts - Device Tree file for SAMA7D65 Curiosity board
+ *
+ *  Copyright (c) 2024 Microchip Technology Inc. and its subsidiaries
+ *
+ *  Author: Romain Sioen <romain.sioen@microchip.com>
+ *
+ */
+/dts-v1/;
+#include "sama7d65-pinfunc.h"
+#include "sama7d65.dtsi"
+#include <dt-bindings/mfd/atmel-flexcom.h>
+#include <dt-bindings/pinctrl/at91.h>
+
+/ {
+	model = "Microchip SAMA7D65 Curiosity";
+	compatible = "microchip,sama7d65-curiosity", "microchip,sama7d65",
+		     "microchip,sama7d6", "microchip,sama7";
+
+	aliases {
+		serial0 = &uart6;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	memory@60000000 {
+		device_type = "memory";
+		reg = <0x60000000 0x40000000>;
+	};
+};
+
+&flx6 {
+	atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_USART>;
+	status = "okay";
+};
+
+&uart6 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart6_default>;
+	status = "okay";
+};
+
+&main_xtal {
+	clock-frequency = <24000000>;
+};
+
+&pioa {
+	pinctrl_sdmmc1_default: sdmmc1-default {
+		cmd-data {
+			pinmux = <PIN_PB22__SDMMC1_CMD>,
+				 <PIN_PB24__SDMMC1_DAT0>,
+				 <PIN_PB25__SDMMC1_DAT1>,
+				 <PIN_PB26__SDMMC1_DAT2>,
+				 <PIN_PB27__SDMMC1_DAT3>;
+			slew-rate = <0>;
+			bias-disable;
+		};
+
+		ck-cd-rstn-vddsel {
+			pinmux = <PIN_PB23__SDMMC1_CK>,
+				 <PIN_PB21__SDMMC1_RSTN>,
+				 <PIN_PB30__SDMMC1_1V8SEL>,
+				 <PIN_PB29__SDMMC1_CD>,
+				 <PIN_PB28__SDMMC1_WP>;
+			slew-rate = <0>;
+			bias-disable;
+		};
+	};
+
+	pinctrl_uart6_default: uart6-default {
+		pinmux = <PIN_PD18__FLEXCOM6_IO0>,
+			 <PIN_PD19__FLEXCOM6_IO1>;
+		bias-disable;
+	};
+};
+
+&sdmmc1 {
+	bus-width = <4>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_sdmmc1_default>;
+	status = "okay";
+};
+
+&slow_xtal {
+	clock-frequency = <32768>;
+};
diff --git a/dts/upstream/src/arm/microchip/sam9x60.dtsi b/dts/upstream/src/arm/microchip/sam9x60.dtsi
index 36944e18a32..b8b2c1ddf3f 100644
--- a/dts/upstream/src/arm/microchip/sam9x60.dtsi
+++ b/dts/upstream/src/arm/microchip/sam9x60.dtsi
@@ -197,6 +197,8 @@
 					compatible = "microchip,sam9x60-spi", "atmel,at91rm9200-spi";
 					reg = <0x400 0x200>;
 					interrupts = <13 IRQ_TYPE_LEVEL_HIGH 7>;
+					#address-cells = <1>;
+					#size-cells = <0>;
 					clocks = <&pmc PMC_TYPE_PERIPHERAL 13>;
 					clock-names = "spi_clk";
 					dmas = <&dma0
@@ -268,6 +270,8 @@
 					compatible = "microchip,sam9x60-spi", "atmel,at91rm9200-spi";
 					reg = <0x400 0x200>;
 					interrupts = <14 IRQ_TYPE_LEVEL_HIGH 7>;
+					#address-cells = <1>;
+					#size-cells = <0>;
 					clocks = <&pmc PMC_TYPE_PERIPHERAL 14>;
 					clock-names = "spi_clk";
 					dmas = <&dma0
@@ -768,6 +772,8 @@
 					compatible = "microchip,sam9x60-spi", "atmel,at91rm9200-spi";
 					reg = <0x400 0x200>;
 					interrupts = <5 IRQ_TYPE_LEVEL_HIGH 7>;
+					#address-cells = <1>;
+					#size-cells = <0>;
 					clocks = <&pmc PMC_TYPE_PERIPHERAL 5>;
 					clock-names = "spi_clk";
 					dmas = <&dma0
@@ -839,6 +845,8 @@
 					compatible = "microchip,sam9x60-spi", "atmel,at91rm9200-spi";
 					reg = <0x400 0x200>;
 					interrupts = <6 IRQ_TYPE_LEVEL_HIGH 7>;
+					#address-cells = <1>;
+					#size-cells = <0>;
 					clocks = <&pmc PMC_TYPE_PERIPHERAL 6>;
 					clock-names = "spi_clk";
 					dmas = <&dma0
@@ -910,6 +918,8 @@
 					compatible = "microchip,sam9x60-spi", "atmel,at91rm9200-spi";
 					reg = <0x400 0x200>;
 					interrupts = <7 IRQ_TYPE_LEVEL_HIGH 7>;
+					#address-cells = <1>;
+					#size-cells = <0>;
 					clocks = <&pmc PMC_TYPE_PERIPHERAL 7>;
 					clock-names = "spi_clk";
 					dmas = <&dma0
@@ -981,6 +991,8 @@
 					compatible = "microchip,sam9x60-spi", "atmel,at91rm9200-spi";
 					reg = <0x400 0x200>;
 					interrupts = <8 IRQ_TYPE_LEVEL_HIGH 7>;
+					#address-cells = <1>;
+					#size-cells = <0>;
 					clocks = <&pmc PMC_TYPE_PERIPHERAL 8>;
 					clock-names = "spi_clk";
 					dmas = <&dma0
diff --git a/dts/upstream/src/arm/microchip/sam9x7.dtsi b/dts/upstream/src/arm/microchip/sam9x7.dtsi
index beb1f34b38d..b217a908f52 100644
--- a/dts/upstream/src/arm/microchip/sam9x7.dtsi
+++ b/dts/upstream/src/arm/microchip/sam9x7.dtsi
@@ -132,6 +132,8 @@
 				compatible = "microchip,sam9x7-spi", "atmel,at91rm9200-spi";
 				reg = <0x400 0x200>;
 				interrupts = <13 IRQ_TYPE_LEVEL_HIGH 7>;
+				#address-cells = <1>;
+				#size-cells = <0>;
 				clocks = <&pmc PMC_TYPE_PERIPHERAL 13>;
 				clock-names = "spi_clk";
 				dmas = <&dma0
@@ -151,6 +153,8 @@
 				compatible = "microchip,sam9x7-i2c", "microchip,sam9x60-i2c";
 				reg = <0x600 0x200>;
 				interrupts = <13 IRQ_TYPE_LEVEL_HIGH 7>;
+				#address-cells = <1>;
+				#size-cells = <0>;
 				clocks = <&pmc PMC_TYPE_PERIPHERAL 13>;
 				dmas = <&dma0
 					(AT91_XDMAC_DT_MEM_IF(0) |
@@ -201,6 +205,8 @@
 				compatible = "microchip,sam9x7-spi", "atmel,at91rm9200-spi";
 				reg = <0x400 0x200>;
 				interrupts = <14 IRQ_TYPE_LEVEL_HIGH 7>;
+				#address-cells = <1>;
+				#size-cells = <0>;
 				clocks = <&pmc PMC_TYPE_PERIPHERAL 14>;
 				clock-names = "spi_clk";
 				dmas = <&dma0
@@ -220,6 +226,8 @@
 				compatible = "microchip,sam9x7-i2c", "microchip,sam9x60-i2c";
 				reg = <0x600 0x200>;
 				interrupts = <14 IRQ_TYPE_LEVEL_HIGH 7>;
+				#address-cells = <1>;
+				#size-cells = <0>;
 				clocks = <&pmc PMC_TYPE_PERIPHERAL 14>;
 				dmas = <&dma0
 					(AT91_XDMAC_DT_MEM_IF(0) |
@@ -312,6 +320,8 @@
 				compatible = "microchip,sam9x7-i2c", "microchip,sam9x60-i2c";
 				reg = <0x600 0x200>;
 				interrupts = <32 IRQ_TYPE_LEVEL_HIGH 7>;
+				#address-cells = <1>;
+				#size-cells = <0>;
 				clocks = <&pmc PMC_TYPE_PERIPHERAL 32>;
 				dmas = <&dma0
 					(AT91_XDMAC_DT_MEM_IF(0) |
@@ -362,6 +372,8 @@
 				compatible = "microchip,sam9x7-i2c", "microchip,sam9x60-i2c";
 				reg = <0x600 0x200>;
 				interrupts = <33 IRQ_TYPE_LEVEL_HIGH 7>;
+				#address-cells = <1>;
+				#size-cells = <0>;
 				clocks = <&pmc PMC_TYPE_PERIPHERAL 33>;
 				dmas = <&dma0
 					(AT91_XDMAC_DT_MEM_IF(0) |
@@ -533,6 +545,8 @@
 				compatible = "microchip,sam9x7-i2c", "microchip,sam9x60-i2c";
 				reg = <0x600 0x200>;
 				interrupts = <9 IRQ_TYPE_LEVEL_HIGH 7>;
+				#address-cells = <1>;
+				#size-cells = <0>;
 				clocks = <&pmc PMC_TYPE_PERIPHERAL 9>;
 				dmas = <&dma0
 					(AT91_XDMAC_DT_MEM_IF(0) |
@@ -583,6 +597,8 @@
 				compatible = "microchip,sam9x7-i2c", "microchip,sam9x60-i2c";
 				reg = <0x600 0x200>;
 				interrupts = <10 IRQ_TYPE_LEVEL_HIGH 7>;
+				#address-cells = <1>;
+				#size-cells = <0>;
 				clocks = <&pmc PMC_TYPE_PERIPHERAL 10>;
 				dmas = <&dma0
 					(AT91_XDMAC_DT_MEM_IF(0) |
@@ -633,6 +649,8 @@
 				compatible = "microchip,sam9x7-i2c", "microchip,sam9x60-i2c";
 				reg = <0x600 0x200>;
 				interrupts = <11 IRQ_TYPE_LEVEL_HIGH 7>;
+				#address-cells = <1>;
+				#size-cells = <0>;
 				clocks = <&pmc PMC_TYPE_PERIPHERAL 11>;
 				dmas = <&dma0
 					(AT91_XDMAC_DT_MEM_IF(0) |
@@ -683,6 +701,8 @@
 				compatible = "microchip,sam9x7-spi", "atmel,at91rm9200-spi";
 				reg = <0x400 0x200>;
 				interrupts = <5 IRQ_TYPE_LEVEL_HIGH 7>;
+				#address-cells = <1>;
+				#size-cells = <0>;
 				clocks = <&pmc PMC_TYPE_PERIPHERAL 5>;
 				clock-names = "spi_clk";
 				dmas = <&dma0
@@ -702,6 +722,8 @@
 				compatible = "microchip,sam9x7-i2c", "microchip,sam9x60-i2c";
 				reg = <0x600 0x200>;
 				interrupts = <5 IRQ_TYPE_LEVEL_HIGH 7>;
+				#address-cells = <1>;
+				#size-cells = <0>;
 				clocks = <&pmc PMC_TYPE_PERIPHERAL 5>;
 				dmas = <&dma0
 					(AT91_XDMAC_DT_MEM_IF(0) |
@@ -752,6 +774,8 @@
 				compatible = "microchip,sam9x7-spi", "atmel,at91rm9200-spi";
 				reg = <0x400 0x200>;
 				interrupts = <6 IRQ_TYPE_LEVEL_HIGH 7>;
+				#address-cells = <1>;
+				#size-cells = <0>;
 				clocks = <&pmc PMC_TYPE_PERIPHERAL 6>;
 				clock-names = "spi_clk";
 				dmas = <&dma0
@@ -771,6 +795,8 @@
 				compatible = "microchip,sam9x7-i2c", "microchip,sam9x60-i2c";
 				reg = <0x600 0x200>;
 				interrupts = <6 IRQ_TYPE_LEVEL_HIGH 7>;
+				#address-cells = <1>;
+				#size-cells = <0>;
 				clocks = <&pmc PMC_TYPE_PERIPHERAL 6>;
 				dmas = <&dma0
 					(AT91_XDMAC_DT_MEM_IF(0) |
@@ -821,6 +847,8 @@
 				compatible = "microchip,sam9x7-spi", "atmel,at91rm9200-spi";
 				reg = <0x400 0x200>;
 				interrupts = <7 IRQ_TYPE_LEVEL_HIGH 7>;
+				#address-cells = <1>;
+				#size-cells = <0>;
 				clocks = <&pmc PMC_TYPE_PERIPHERAL 7>;
 				clock-names = "spi_clk";
 				dmas = <&dma0
@@ -840,6 +868,8 @@
 				compatible = "microchip,sam9x7-i2c", "microchip,sam9x60-i2c";
 				reg = <0x600 0x200>;
 				interrupts = <7 IRQ_TYPE_LEVEL_HIGH 7>;
+				#address-cells = <1>;
+				#size-cells = <0>;
 				clocks = <&pmc PMC_TYPE_PERIPHERAL 7>;
 				dmas = <&dma0
 					(AT91_XDMAC_DT_MEM_IF(0) |
@@ -890,6 +920,8 @@
 				compatible = "microchip,sam9x7-spi", "atmel,at91rm9200-spi";
 				reg = <0x400 0x200>;
 				interrupts = <8 IRQ_TYPE_LEVEL_HIGH 7>;
+				#address-cells = <1>;
+				#size-cells = <0>;
 				clocks = <&pmc PMC_TYPE_PERIPHERAL 8>;
 				clock-names = "spi_clk";
 				dmas = <&dma0
@@ -909,6 +941,8 @@
 				compatible = "microchip,sam9x7-i2c", "microchip,sam9x60-i2c";
 				reg = <0x600 0x200>;
 				interrupts = <8 IRQ_TYPE_LEVEL_HIGH 7>;
+				#address-cells = <1>;
+				#size-cells = <0>;
 				clocks = <&pmc PMC_TYPE_PERIPHERAL 8>;
 				dmas = <&dma0
 					(AT91_XDMAC_DT_MEM_IF(0) |
@@ -984,6 +1018,8 @@
 				compatible = "microchip,sam9x7-i2c", "microchip,sam9x60-i2c";
 				reg = <0x600 0x200>;
 				interrupts = <15 IRQ_TYPE_LEVEL_HIGH 7>;
+				#address-cells = <1>;
+				#size-cells = <0>;
 				clocks = <&pmc PMC_TYPE_PERIPHERAL 15>;
 				dmas = <&dma0
 					(AT91_XDMAC_DT_MEM_IF(0) |
@@ -1034,6 +1070,8 @@
 				compatible = "microchip,sam9x7-i2c", "microchip,sam9x60-i2c";
 				reg = <0x600 0x200>;
 				interrupts = <16 IRQ_TYPE_LEVEL_HIGH 7>;
+				#address-cells = <1>;
+				#size-cells = <0>;
 				clocks = <&pmc PMC_TYPE_PERIPHERAL 16>;
 				dmas = <&dma0
 					(AT91_XDMAC_DT_MEM_IF(0) |
diff --git a/dts/upstream/src/arm/microchip/sama7d65-pinfunc.h b/dts/upstream/src/arm/microchip/sama7d65-pinfunc.h
new file mode 100644
index 00000000000..c591f333cac
--- /dev/null
+++ b/dts/upstream/src/arm/microchip/sama7d65-pinfunc.h
@@ -0,0 +1,947 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+#define PINMUX_PIN(no, func, ioset) \
+(((no) & 0xffff) | (((func) & 0xf) << 16) | (((ioset) & 0xff) << 20))
+
+#define PIN_PA0				0
+#define PIN_PA0__GPIO			PINMUX_PIN(PIN_PA0, 0, 0)
+#define PIN_PA0__SDMMC0_CK		PINMUX_PIN(PIN_PA0, 1, 1)
+#define PIN_PA0__FLEXCOM3_IO0		PINMUX_PIN(PIN_PA0, 2, 1)
+#define PIN_PA0__NWER0			PINMUX_PIN(PIN_PA0, 3, 1)
+
+#define PIN_PA1				1
+#define PIN_PA1__GPIO			PINMUX_PIN(PIN_PA1, 0, 0)
+#define PIN_PA1__SDMMC0_CMD		PINMUX_PIN(PIN_PA1, 1, 1)
+#define PIN_PA1__FLEXCOM3_IO1		PINMUX_PIN(PIN_PA1, 2, 1)
+#define PIN_PA1__A21			PINMUX_PIN(PIN_PA1, 3, 1)
+
+#define PIN_PA2				2
+#define PIN_PA2__GPIO			PINMUX_PIN(PIN_PA2, 0, 0)
+#define PIN_PA2__SDMMC0_RSTN		PINMUX_PIN(PIN_PA2, 1, 1)
+#define PIN_PA2__FLEXCOM3_IO2		PINMUX_PIN(PIN_PA2, 2, 1)
+#define PIN_PA2__A22			PINMUX_PIN(PIN_PA2, 3, 1)
+
+#define PIN_PA3				3
+#define PIN_PA3__GPIO			PINMUX_PIN(PIN_PA3, 0, 0)
+#define PIN_PA3__SDMMC0_DAT0		PINMUX_PIN(PIN_PA3, 1, 1)
+#define PIN_PA3__FLEXCOM3_IO3		PINMUX_PIN(PIN_PA3, 2, 1)
+#define PIN_PA3__D0			PINMUX_PIN(PIN_PA3, 3, 1)
+
+#define PIN_PA4				4
+#define PIN_PA4__GPIO			PINMUX_PIN(PIN_PA4, 0, 0)
+#define PIN_PA4__SDMMC0_DAT1		PINMUX_PIN(PIN_PA4, 1, 1)
+#define PIN_PA4__FLEXCOM3_IO4		PINMUX_PIN(PIN_PA4, 2, 1)
+#define PIN_PA4__D1			PINMUX_PIN(PIN_PA4, 3, 1)
+
+#define PIN_PA5				5
+#define PIN_PA5__GPIO			PINMUX_PIN(PIN_PA5, 0, 0)
+#define PIN_PA5__SDMMC0_DAT4		PINMUX_PIN(PIN_PA5, 1, 1)
+#define PIN_PA5__FLEXCOM2_IO0		PINMUX_PIN(PIN_PA5, 2, 3)
+#define PIN_PA5__D4			PINMUX_PIN(PIN_PA5, 3, 1)
+#define PIN_PA5__TCLK4			PINMUX_PIN(PIN_PA5, 6, 3)
+
+#define PIN_PA6				6
+#define PIN_PA6__GPIO			PINMUX_PIN(PIN_PA6, 0, 0)
+#define PIN_PA6__SDMMC0_DAT5		PINMUX_PIN(PIN_PA6, 1, 1)
+#define PIN_PA6__FLEXCOM2_IO1		PINMUX_PIN(PIN_PA6, 2, 3)
+#define PIN_PA6__D5			PINMUX_PIN(PIN_PA6, 3, 1)
+#define PIN_PA6__TIOB4			PINMUX_PIN(PIN_PA6, 6, 3)
+
+#define PIN_PA7				7
+#define PIN_PA7__GPIO			PINMUX_PIN(PIN_PA7, 0, 0)
+#define PIN_PA7__SDMMC0_DAT6		PINMUX_PIN(PIN_PA7, 1, 1)
+#define PIN_PA7__FLEXCOM2_IO2		PINMUX_PIN(PIN_PA7, 2, 3)
+#define PIN_PA7__D6			PINMUX_PIN(PIN_PA7, 3, 1)
+#define PIN_PA7__TIOA4			PINMUX_PIN(PIN_PA7, 6, 3)
+
+#define PIN_PA8				8
+#define PIN_PA8__GPIO			PINMUX_PIN(PIN_PA8, 0, 0)
+#define PIN_PA8__SDMMC0_DAT7		PINMUX_PIN(PIN_PA8, 1, 1)
+#define PIN_PA8__FLEXCOM2_IO3		PINMUX_PIN(PIN_PA8, 2, 3)
+#define PIN_PA8__D7			PINMUX_PIN(PIN_PA8, 3, 1)
+#define PIN_PA8__TIOA5			PINMUX_PIN(PIN_PA8, 6, 3)
+
+#define PIN_PA9				9
+#define PIN_PA9__GPIO			PINMUX_PIN(PIN_PA9, 0, 0)
+#define PIN_PA9__SDMMC0_DAT2		PINMUX_PIN(PIN_PA9, 1, 1)
+#define PIN_PA9__FLEXCOM0_IO2		PINMUX_PIN(PIN_PA9, 2, 1)
+#define PIN_PA9__D2			PINMUX_PIN(PIN_PA9, 3, 1)
+#define PIN_PA9__TIOB5			PINMUX_PIN(PIN_PA9, 6, 3)
+
+#define PIN_PA10			10
+#define PIN_PA10__GPIO			PINMUX_PIN(PIN_PA10, 0, 0)
+#define PIN_PA10__SDMMC0_DAT3		PINMUX_PIN(PIN_PA10, 1, 1)
+#define PIN_PA10__FLEXCOM0_IO3		PINMUX_PIN(PIN_PA10, 2, 1)
+#define PIN_PA10__D3			PINMUX_PIN(PIN_PA10, 3, 1)
+#define PIN_PA10__TCLK5			PINMUX_PIN(PIN_PA10, 6, 3)
+
+#define PIN_PA11			11
+#define PIN_PA11__GPIO			PINMUX_PIN(PIN_PA11, 0, 0)
+#define PIN_PA11__SDMMC0_DS		PINMUX_PIN(PIN_PA11, 1, 1)
+#define PIN_PA11__FLEXCOM0_IO4		PINMUX_PIN(PIN_PA11, 2, 1)
+#define PIN_PA11__NANDRDY		PINMUX_PIN(PIN_PA11, 3, 1)
+#define PIN_PA11__TIOB3			PINMUX_PIN(PIN_PA11, 6, 3)
+
+#define PIN_PA12			12
+#define PIN_PA12__GPIO			PINMUX_PIN(PIN_PA12, 0, 0)
+#define PIN_PA12__FLEXCOM0_IO0		PINMUX_PIN(PIN_PA12, 2, 1)
+#define PIN_PA12__NRD			PINMUX_PIN(PIN_PA12, 3, 1)
+#define PIN_PA12__PCK0			PINMUX_PIN(PIN_PA12, 4, 1)
+#define PIN_PA12__EXT_IRQ0		PINMUX_PIN(PIN_PA12, 5, 1)
+#define PIN_PA12__TIOA3			PINMUX_PIN(PIN_PA12, 6, 3)
+
+#define PIN_PA13			13
+#define PIN_PA13__GPIO			PINMUX_PIN(PIN_PA13, 0, 0)
+#define PIN_PA13__FLEXCOM0_IO1		PINMUX_PIN(PIN_PA13, 2, 1)
+#define PIN_PA13__NCS0			PINMUX_PIN(PIN_PA13, 3, 1)
+#define PIN_PA13__PCK1			PINMUX_PIN(PIN_PA13, 4, 1)
+#define PIN_PA13__TCLK3			PINMUX_PIN(PIN_PA13, 6, 3)
+
+#define PIN_PA14			14
+#define PIN_PA14__GPIO			PINMUX_PIN(PIN_PA14, 0, 0)
+#define PIN_PA14__FLEXCOM4_IO4		PINMUX_PIN(PIN_PA14, 1, 1)
+#define PIN_PA14__SDMMC0_WP		PINMUX_PIN(PIN_PA14, 2, 1)
+#define PIN_PA14__FLEXCOM3_IO0		PINMUX_PIN(PIN_PA14, 3, 4)
+
+#define PIN_PA15			15
+#define PIN_PA15__GPIO			PINMUX_PIN(PIN_PA15, 0, 0)
+#define PIN_PA15__FLEXCOM4_IO3		PINMUX_PIN(PIN_PA15, 1, 1)
+#define PIN_PA15__SDMMC0_1V8SEL		PINMUX_PIN(PIN_PA15, 2, 1)
+#define PIN_PA15__FLEXCOM3_IO1		PINMUX_PIN(PIN_PA15, 3, 4)
+
+#define PIN_PA16			16
+#define PIN_PA16__GPIO			PINMUX_PIN(PIN_PA16, 0, 0)
+#define PIN_PA16__FLEXCOM4_IO2		PINMUX_PIN(PIN_PA16, 1, 1)
+#define PIN_PA16__SDMMCo_CD		PINMUX_PIN(PIN_PA16, 2, 1)
+#define PIN_PA16__PCK2			PINMUX_PIN(PIN_PA16, 4, 1)
+#define PIN_PA16__EXT_IRQ1		PINMUX_PIN(PIN_PA16, 5, 1)
+
+#define PIN_PA17			17
+#define PIN_PA17__GPIO			PINMUX_PIN(PIN_PA17, 0, 0)
+#define PIN_PA17__FLEXCOM4_IO1		PINMUX_PIN(PIN_PA17, 1, 1)
+
+#define PIN_PA18			18
+#define PIN_PA18__GPIO			PINMUX_PIN(PIN_PA18, 0, 0)
+#define PIN_PA18__FLEXCOM4_IO0		PINMUX_PIN(PIN_PA18, 1, 1)
+
+#define PIN_PA19			19
+#define PIN_PA19__GPIO			PINMUX_PIN(PIN_PA19, 0, 0)
+#define PIN_PA19__TK0			PINMUX_PIN(PIN_PA19, 1, 1)
+#define PIN_PA19__FLEXCOM4_IO5		PINMUX_PIN(PIN_PA19, 3, 1)
+#define PIN_PA19__PWML0			PINMUX_PIN(PIN_PA19, 4, 3)
+
+#define PIN_PA20			20
+#define PIN_PA20__GPIO			PINMUX_PIN(PIN_PA20, 0, 0)
+#define PIN_PA20__TD0			PINMUX_PIN(PIN_PA20, 1, 1)
+#define PIN_PA20__FLEXCOM3_IO4		PINMUX_PIN(PIN_PA20, 2, 2)
+#define PIN_PA20__FLEXCOM4_IO6		PINMUX_PIN(PIN_PA20, 3, 1)
+#define PIN_PA20__PWMH0			PINMUX_PIN(PIN_PA20, 4, 3)
+
+#define PIN_PA21			21
+#define PIN_PA21__GPIO			PINMUX_PIN(PIN_PA21, 0, 0)
+#define PIN_PA21__TF0			PINMUX_PIN(PIN_PA21, 1, 1)
+#define PIN_PA21__FLEXCOM3_IO3		PINMUX_PIN(PIN_PA21, 2, 2)
+#define PIN_PA21__PWML1			PINMUX_PIN(PIN_PA21, 4, 3)
+
+#define PIN_PA22			22
+#define PIN_PA22__GPIO			PINMUX_PIN(PIN_PA22, 0, 0)
+#define PIN_PA22__RD0			PINMUX_PIN(PIN_PA22, 1, 1)
+#define PIN_PA22__FLEXCOM3_IO2		PINMUX_PIN(PIN_PA22, 2, 2)
+#define PIN_PA22__PDMC0_DS1		PINMUX_PIN(PIN_PA22, 3, 1)
+#define PIN_PA22__PWMH1			PINMUX_PIN(PIN_PA22, 4, 3)
+
+#define PIN_PA23			23
+#define PIN_PA23__GPIO			PINMUX_PIN(PIN_PA23, 0, 0)
+#define PIN_PA23__RK0			PINMUX_PIN(PIN_PA23, 1, 1)
+#define PIN_PA23__FLEXCOM3_IO1		PINMUX_PIN(PIN_PA23, 2, 2)
+#define PIN_PA23__PDMC0_CLK		PINMUX_PIN(PIN_PA23, 3, 1)
+#define PIN_PA23__PWML2			PINMUX_PIN(PIN_PA23, 4, 3)
+
+#define PIN_PA24			24
+#define PIN_PA24__GPIO			PINMUX_PIN(PIN_PA24, 0, 0)
+#define PIN_PA24__RF0			PINMUX_PIN(PIN_PA24, 1, 1)
+#define PIN_PA24__FLEXCOM3_IO0		PINMUX_PIN(PIN_PA24, 2, 2)
+#define PIN_PA24__PDMC0_DS0		PINMUX_PIN(PIN_PA24, 3, 1)
+#define PIN_PA24__PWMH2			PINMUX_PIN(PIN_PA24, 4, 3)
+
+#define PIN_PA25			25
+#define PIN_PA25__GPIO			PINMUX_PIN(PIN_PA25, 0, 0)
+#define PIN_PA25__G0_TXCTL		PINMUX_PIN(PIN_PA25, 1, 1)
+#define PIN_PA25__FLEXCOM6_IO2		PINMUX_PIN(PIN_PA25, 2, 1)
+
+#define PIN_PA26			26
+#define PIN_PA26__GPIO			PINMUX_PIN(PIN_PA26, 0, 0)
+#define PIN_PA26__G0_TX0		PINMUX_PIN(PIN_PA26, 1, 1)
+#define PIN_PA26__FLEXCOM6_IO3		PINMUX_PIN(PIN_PA26, 2, 1)
+
+#define PIN_PA27			27
+#define PIN_PA27__GPIO			PINMUX_PIN(PIN_PA27, 0, 0)
+#define PIN_PA27__G0_TX1		PINMUX_PIN(PIN_PA27, 1, 1)
+#define PIN_PA27__FLEXCOM6_IO4		PINMUX_PIN(PIN_PA27, 2, 1)
+
+#define PIN_PA28			28
+#define PIN_PA28__GPIO			PINMUX_PIN(PIN_PA28, 0, 0)
+#define PIN_PA28__G0_RXCTL		PINMUX_PIN(PIN_PA28, 1, 1)
+#define PIN_PA28__FLEXCOM6_IO0		PINMUX_PIN(PIN_PA28, 2, 1)
+
+#define PIN_PA29			29
+#define PIN_PA29__GPIO			PINMUX_PIN(PIN_PA29, 0, 0)
+#define PIN_PA29__G0_RX0		PINMUX_PIN(PIN_PA29, 1, 1)
+#define PIN_PA29__FLEXCOM6_IO1		PINMUX_PIN(PIN_PA29, 2, 1)
+
+#define PIN_PA30			30
+#define PIN_PA30__GPIO			PINMUX_PIN(PIN_PA30, 0, 0)
+#define PIN_PA30__G0_RX1		PINMUX_PIN(PIN_PA30, 1, 1)
+#define PIN_PA30__FLEXCOM8_IO0		PINMUX_PIN(PIN_PA30, 2, 1)
+
+#define PIN_PA31			31
+#define PIN_PA31__GPIO			PINMUX_PIN(PIN_PA31, 0, 0)
+#define PIN_PA31__G0_MDC		PINMUX_PIN(PIN_PA31, 1, 1)
+#define PIN_PA31__FLEXCOM8_IO1		PINMUX_PIN(PIN_PA31, 2, 1)
+
+#define PIN_PB0				32
+#define PIN_PB0__GPIO			PINMUX_PIN(PIN_PB0, 0, 0)
+#define PIN_PB0__G0_MDIO		PINMUX_PIN(PIN_PB0, 1, 1)
+#define PIN_PB0__FLEXCOM8_IO3		PINMUX_PIN(PIN_PB0, 2, 2)
+
+#define PIN_PB1				33
+#define PIN_PB1__GPIO			PINMUX_PIN(PIN_PB1, 0, 0)
+#define PIN_PB1__G0_REFCK		PINMUX_PIN(PIN_PB1, 1, 2)
+#define PIN_PB1__FLEXCOM8_IO2		PINMUX_PIN(PIN_PB1, 2, 1)
+
+#define PIN_PB2				34
+#define PIN_PB2__GPIO			PINMUX_PIN(PIN_PB2, 0, 0)
+#define PIN_PB2__G0_RX2			PINMUX_PIN(PIN_PB2, 1, 1)
+#define PIN_PB2__FLEXCOM8_IO4		PINMUX_PIN(PIN_PB2, 2, 1)
+#define PIN_PB2__G0_RXER		PINMUX_PIN(PIN_PB2, 3, 2)
+#define PIN_PB2__RK0			PINMUX_PIN(PIN_PB2, 4, 2)
+
+#define PIN_PB3				35
+#define PIN_PB3__GPIO			PINMUX_PIN(PIN_PB3, 0, 0)
+#define PIN_PB3__G0_RXCK		PINMUX_PIN(PIN_PB3, 1, 1)
+#define PIN_PB3__FLEXCOM10_IO2		PINMUX_PIN(PIN_PB3, 2, 2)
+#define PIN_PB3__TK0			PINMUX_PIN(PIN_PB3, 4, 2)
+
+#define PIN_PB4				36
+#define PIN_PB4__GPIO			PINMUX_PIN(PIN_PB4, 0, 0)
+#define PIN_PB4__G0_TX2			PINMUX_PIN(PIN_PB4, 1, 1)
+#define PIN_PB4__FLEXCOM10_IO3		PINMUX_PIN(PIN_PB4, 2, 2)
+#define PIN_PB4__TF0			PINMUX_PIN(PIN_PB4, 4, 2)
+
+#define PIN_PB5				37
+#define PIN_PB5__GPIO			PINMUX_PIN(PIN_PB5, 0, 0)
+#define PIN_PB5__G0_TX3			PINMUX_PIN(PIN_PB5, 1, 1)
+#define PIN_PB5__FLEXCOM10_IO4		PINMUX_PIN(PIN_PB5, 2, 1)
+#define PIN_PB5__TD0			PINMUX_PIN(PIN_PB5, 4, 2)
+
+#define PIN_PB6				38
+#define PIN_PB6__GPIO			PINMUX_PIN(PIN_PB6, 0, 0)
+#define PIN_PB6__G0_RX3			PINMUX_PIN(PIN_PB6, 1, 1)
+#define PIN_PB6__FLEXCOM10_IO0		PINMUX_PIN(PIN_PB6, 2, 2)
+#define PIN_PB6__RD0			PINMUX_PIN(PIN_PB6, 4, 2)
+
+#define PIN_PB7				39
+#define PIN_PB7__GPIO			PINMUX_PIN(PIN_PB7, 0, 0)
+#define PIN_PB7__G0_TSUCOMP		PINMUX_PIN(PIN_PB7, 1, 1)
+#define PIN_PB7__FLEXCOM10_IO1		PINMUX_PIN(PIN_PB7, 2, 2)
+#define PIN_PB7__ADTRG			PINMUX_PIN(PIN_PB7, 3, 1)
+#define PIN_PB7__RF0			PINMUX_PIN(PIN_PB7, 4, 2)
+
+#define PIN_PB8				40
+#define PIN_PB8__GPIO			PINMUX_PIN(PIN_PB8, 0, 0)
+#define PIN_PB8__QSPI0_IO3		PINMUX_PIN(PIN_PB8, 1, 1)
+#define PIN_PB8__PCK3			PINMUX_PIN(PIN_PB8, 2, 1)
+#define PIN_PB8__FLEXCOM2_IO1		PINMUX_PIN(PIN_PB8, 4, 2)
+
+#define PIN_PB9				41
+#define PIN_PB9__GPIO			PINMUX_PIN(PIN_PB9, 0, 0)
+#define PIN_PB9__QSPI0_IO2		PINMUX_PIN(PIN_PB9, 1, 1)
+#define PIN_PB9__FLEXCOM2_IO0		PINMUX_PIN(PIN_PB9, 4, 2)
+#define PIN_PB9__PWMEXTRG0		PINMUX_PIN(PIN_PB9, 5, 1)
+
+#define PIN_PB10			42
+#define PIN_PB10__GPIO			PINMUX_PIN(PIN_PB10, 0, 0)
+#define PIN_PB10__QSPI0_IO1		PINMUX_PIN(PIN_PB10, 1, 1)
+#define PIN_PB10__FLEXCOM2_IO4		PINMUX_PIN(PIN_PB10, 4, 2)
+#define PIN_PB10__PWMEXTRG1		PINMUX_PIN(PIN_PB10, 5, 1)
+
+#define PIN_PB11			43
+#define PIN_PB11__GPIO			PINMUX_PIN(PIN_PB11, 0, 0)
+#define PIN_PB11__QSPI0_IO0		PINMUX_PIN(PIN_PB11, 1, 1)
+#define PIN_PB11__FLEXCOM2_IO5		PINMUX_PIN(PIN_PB11, 4, 2)
+#define PIN_PB11__PWML3			PINMUX_PIN(PIN_PB11, 5, 1)
+#define PIN_PB11__TIOB3			PINMUX_PIN(PIN_PB11, 6, 2)
+
+#define PIN_PB12			44
+#define PIN_PB12__GPIO			PINMUX_PIN(PIN_PB12, 0, 0)
+#define PIN_PB12__QSPI0_CS		PINMUX_PIN(PIN_PB12, 1, 1)
+#define PIN_PB12__FLEXCOM2_IO3		PINMUX_PIN(PIN_PB12, 4, 2)
+#define PIN_PB12__PWMFI1		PINMUX_PIN(PIN_PB12, 6, 1)
+#define PIN_PB12__TIOA3			PINMUX_PIN(PIN_PB12, 6, 2)
+
+#define PIN_PB13			45
+#define PIN_PB13__GPIO			PINMUX_PIN(PIN_PB13, 0, 0)
+#define PIN_PB13__QSPI0_SCK		PINMUX_PIN(PIN_PB13, 1, 1)
+#define PIN_PB13__FLEXCOM2_IO2		PINMUX_PIN(PIN_PB13, 4, 2)
+#define PIN_PB13__PWMFI0		PINMUX_PIN(PIN_PB13, 5, 1)
+#define PIN_PB13__TCLK3			PINMUX_PIN(PIN_PB13, 6, 2)
+
+#define PIN_PB14			46
+#define PIN_PB14__GPIO			PINMUX_PIN(PIN_PB14, 0, 0)
+#define PIN_PB14__QSPI0_SCKN		PINMUX_PIN(PIN_PB14, 1, 1)
+#define PIN_PB14__QSPI1_SCK		PINMUX_PIN(PIN_PB14, 2, 1)
+#define PIN_PB14__I2SMCC0_CK		PINMUX_PIN(PIN_PB14, 3, 3)
+#define PIN_PB14__FLEXCOM10_IO5		PINMUX_PIN(PIN_PB14, 4, 1)
+#define PIN_PB14__PWMH3			PINMUX_PIN(PIN_PB14, 5, 1)
+#define PIN_PB14__FLEXCOM2_IO1		PINMUX_PIN(PIN_PB14, 7, 4)
+
+#define PIN_PB15			47
+#define PIN_PB15__GPIO			PINMUX_PIN(PIN_PB15, 0, 0)
+#define PIN_PB15__QSPI0_IO4		PINMUX_PIN(PIN_PB15, 1, 1)
+#define PIN_PB15__QSPI1_IO0		PINMUX_PIN(PIN_PB15, 2, 1)
+#define PIN_PB15__I2SMCC0_WS		PINMUX_PIN(PIN_PB15, 3, 3)
+#define PIN_PB15__FLEXCOM10_IO6		PINMUX_PIN(PIN_PB15, 4, 1)
+#define PIN_PB15__PWML0			PINMUX_PIN(PIN_PB15, 5, 1)
+#define PIN_PB15__TCLK4			PINMUX_PIN(PIN_PB15, 6, 2)
+#define PIN_PB15__FLEXCOM2_IO0		PINMUX_PIN(PIN_PB15, 7, 4)
+
+#define PIN_PB16			48
+#define PIN_PB16__GPIO			PINMUX_PIN(PIN_PB16, 0, 0)
+#define PIN_PB16__QSPI0_IO5		PINMUX_PIN(PIN_PB16, 1, 1)
+#define PIN_PB16__QSPI1_IO1		PINMUX_PIN(PIN_PB16, 2, 1)
+#define PIN_PB16__I2SMCC0_DIN0		PINMUX_PIN(PIN_PB16, 3, 3)
+#define PIN_PB16__FLEXCOM10_IO4		PINMUX_PIN(PIN_PB16, 4, 1)
+#define PIN_PB16__PWMH0			PINMUX_PIN(PIN_PB16, 5, 1)
+#define PIN_PB16__TIOB4			PINMUX_PIN(PIN_PB16, 6, 2)
+
+#define PIN_PB17			49
+#define PIN_PB17__GPIO			PINMUX_PIN(PIN_PB17, 0, 0)
+#define PIN_PB17__QSPI0_IO6		PINMUX_PIN(PIN_PB17, 1, 1)
+#define PIN_PB17__QSPI1_IO2		PINMUX_PIN(PIN_PB17, 2, 1)
+#define PIN_PB17__I2SMCC0_DOUT0		PINMUX_PIN(PIN_PB17, 3, 3)
+#define PIN_PB17__FLEXCOM10_IO3		PINMUX_PIN(PIN_PB17, 4, 1)
+#define PIN_PB17__PWML1			PINMUX_PIN(PIN_PB17, 5, 1)
+#define PIN_PB17__TIOA4			PINMUX_PIN(PIN_PB17, 6, 2)
+
+#define PIN_PB18			50
+#define PIN_PB18__GPIO			PINMUX_PIN(PIN_PB18, 0, 0)
+#define PIN_PB18__QSPI0_IO7		PINMUX_PIN(PIN_PB18, 1, 1)
+#define PIN_PB18__QSPI1_IO3		PINMUX_PIN(PIN_PB18, 2, 1)
+#define PIN_PB18__I2SMCC0_MCK		PINMUX_PIN(PIN_PB18, 3, 3)
+#define PIN_PB18__FLEXCOM10_IO2		PINMUX_PIN(PIN_PB18, 4, 1)
+#define PIN_PB18__PWMH1			PINMUX_PIN(PIN_PB18, 5, 1)
+#define PIN_PB18__TIOA5			PINMUX_PIN(PIN_PB18, 6, 2)
+
+#define PIN_PB19			51
+#define PIN_PB19__GPIO			PINMUX_PIN(PIN_PB19, 0, 0)
+#define PIN_PB19__QSPI0_DQS		PINMUX_PIN(PIN_PB19, 1, 1)
+#define PIN_PB19__EXT_IRQ1		PINMUX_PIN(PIN_PB19, 2, 2)
+#define PIN_PB19__PCK4			PINMUX_PIN(PIN_PB19, 3, 1)
+#define PIN_PB19__FLEXCOM10_IO1		PINMUX_PIN(PIN_PB19, 4, 1)
+#define PIN_PB19__PWML2			PINMUX_PIN(PIN_PB19, 5, 1)
+#define PIN_PB19__TIOB5			PINMUX_PIN(PIN_PB19, 6, 2)
+
+#define PIN_PB20			52
+#define PIN_PB20__GPIO			PINMUX_PIN(PIN_PB20, 0, 0)
+#define PIN_PB20__QSPI0_INT		PINMUX_PIN(PIN_PB20, 1, 1)
+#define PIN_PB20__QSPI1_CS		PINMUX_PIN(PIN_PB20, 2, 1)
+#define PIN_PB20__FLEXCOM10_IO0		PINMUX_PIN(PIN_PB20, 4, 1)
+#define PIN_PB20__PWMH2			PINMUX_PIN(PIN_PB20, 5, 1)
+#define PIN_PB20__TCLK5			PINMUX_PIN(PIN_PB20, 6, 2)
+
+#define PIN_PB21			53
+#define PIN_PB21__GPIO			PINMUX_PIN(PIN_PB21, 0, 0)
+#define PIN_PB21__SDMMC1_RSTN		PINMUX_PIN(PIN_PB21, 1, 1)
+#define PIN_PB21__FLEXCOM6_IO4		PINMUX_PIN(PIN_PB21, 2, 2)
+#define PIN_PB21__TIOB2			PINMUX_PIN(PIN_PB21, 3, 2)
+#define PIN_PB21__ADTRG			PINMUX_PIN(PIN_PB21, 4, 2)
+#define PIN_PB21__EXT_IRQ0		PINMUX_PIN(PIN_PB21, 5, 2)
+
+#define PIN_PB22			54
+#define PIN_PB22__GPIO			PINMUX_PIN(PIN_PB22, 0, 0)
+#define PIN_PB22__SDMMC1_CMD		PINMUX_PIN(PIN_PB22, 1, 1)
+#define PIN_PB22__FLEXCOM6_IO3		PINMUX_PIN(PIN_PB22, 2, 2)
+#define PIN_PB22__TCLK2			PINMUX_PIN(PIN_PB22, 3, 2)
+
+#define PIN_PB23			55
+#define PIN_PB23__GPIO			PINMUX_PIN(PIN_PB23, 0, 0)
+#define PIN_PB23__SDMMC1_CK		PINMUX_PIN(PIN_PB23, 1, 1)
+#define PIN_PB23__FLEXCOM6_IO2		PINMUX_PIN(PIN_PB23, 2, 2)
+#define PIN_PB23__TIOA2			PINMUX_PIN(PIN_PB23, 3, 2)
+
+#define PIN_PB24			56
+#define PIN_PB24__GPIO			PINMUX_PIN(PIN_PB24, 0, 0)
+#define PIN_PB24__SDMMC1_DAT0		PINMUX_PIN(PIN_PB24, 1, 1)
+#define PIN_PB24__FLEXCOM6_IO0		PINMUX_PIN(PIN_PB24, 2, 2)
+
+#define PIN_PB25			57
+#define PIN_PB25__GPIO			PINMUX_PIN(PIN_PB25, 0, 0)
+#define PIN_PB25__SDMMC1_DAT1		PINMUX_PIN(PIN_PB25, 1, 1)
+#define PIN_PB25__FLEXCOM6_IO1		PINMUX_PIN(PIN_PB25, 2, 2)
+#define PIN_PB25__TIOB2			PINMUX_PIN(PIN_PB25, 3, 1)
+
+#define PIN_PB26			58
+#define PIN_PB26__GPIO			PINMUX_PIN(PIN_PB26, 0, 0)
+#define PIN_PB26__SDMMC1_DAT2		PINMUX_PIN(PIN_PB26, 1, 1)
+#define PIN_PB26__FLEXCOM8_IO0		PINMUX_PIN(PIN_PB26, 2, 3)
+#define PIN_PB26__TCLK2			PINMUX_PIN(PIN_PB26, 3, 1)
+
+#define PIN_PB27			59
+#define PIN_PB27__GPIO			PINMUX_PIN(PIN_PB27, 0, 0)
+#define PIN_PB27__SDMMC1_DAT3		PINMUX_PIN(PIN_PB27, 1, 1)
+#define PIN_PB27__FLEXCOM8_IO1		PINMUX_PIN(PIN_PB27, 2, 3)
+#define PIN_PB27__TIOA2			PINMUX_PIN(PIN_PB27, 3, 1)
+
+#define PIN_PB28			60
+#define PIN_PB28__GPIO			PINMUX_PIN(PIN_PB28, 0, 0)
+#define PIN_PB28__SDMMC1_WP		PINMUX_PIN(PIN_PB28, 1, 1)
+#define PIN_PB28__FLEXCOM1_IO0		PINMUX_PIN(PIN_PB28, 3, 3)
+#define PIN_PB28__D15			PINMUX_PIN(PIN_PB28, 5, 1)
+
+#define PIN_PB29			61
+#define PIN_PB29__GPIO			PINMUX_PIN(PIN_PB29, 0, 0)
+#define PIN_PB29__SDMMC1_CD		PINMUX_PIN(PIN_PB29, 1, 1)
+#define PIN_PB29__I2SMCC0_MCK		PINMUX_PIN(PIN_PB29, 2, 1)
+#define PIN_PB29__FLEXCOM1_IO1		PINMUX_PIN(PIN_PB29, 3, 3)
+#define PIN_PB29__D14			PINMUX_PIN(PIN_PB29, 5, 2)
+
+#define PIN_PB30			62
+#define PIN_PB30__GPIO			PINMUX_PIN(PIN_PB30, 0, 0)
+#define PIN_PB30__SDMMC1_1V8SEL		PINMUX_PIN(PIN_PB30, 1, 1)
+#define PIN_PB30__I2SMCC1_MCK		PINMUX_PIN(PIN_PB30, 2, 2)
+#define PIN_PB30__FLEXCOM1_IO2		PINMUX_PIN(PIN_PB30, 3, 3)
+#define PIN_PB30__TIOA1			PINMUX_PIN(PIN_PB30, 4, 1)
+#define PIN_PB30__NCS1			PINMUX_PIN(PIN_PB30, 5, 1)
+
+#define PIN_PB31			63
+#define PIN_PB31__GPIO			PINMUX_PIN(PIN_PB31, 0, 0)
+#define PIN_PB31__PCK7			PINMUX_PIN(PIN_PB31, 1, 2)
+#define PIN_PB31__I2SMCC1_DIN1		PINMUX_PIN(PIN_PB31, 2, 1)
+#define PIN_PB31__FLEXCOM1_IO3		PINMUX_PIN(PIN_PB31, 3, 3)
+#define PIN_PB31__TCLK1			PINMUX_PIN(PIN_PB31, 4, 1)
+#define PIN_PB31__NWE			PINMUX_PIN(PIN_PB31, 5, 2)
+
+#define PIN_PC0				64
+#define PIN_PC0__GPIO			PINMUX_PIN(PIN_PC0, 0, 0)
+#define PIN_PC0__PCK6			PINMUX_PIN(PIN_PC0, 1, 2)
+#define PIN_PC0__I2SMCC1_DIN2		PINMUX_PIN(PIN_PC0, 2, 1)
+#define PIN_PC0__FLEXCOM9_IO4		PINMUX_PIN(PIN_PC0, 3, 2)
+#define PIN_PC0__TIOB1			PINMUX_PIN(PIN_PC0, 4, 1)
+#define PIN_PC0__NWR1			PINMUX_PIN(PIN_PC0, 5, 1)
+
+#define PIN_PC1				65
+#define PIN_PC1__GPIO			PINMUX_PIN(PIN_PC1, 0, 0)
+#define PIN_PC1__PCK5			PINMUX_PIN(PIN_PC1, 1, 1)
+#define PIN_PC1__FLEXCOM9_IO2		PINMUX_PIN(PIN_PC1, 3, 2)
+#define PIN_PC1__SMCK			PINMUX_PIN(PIN_PC1, 5, 1)
+
+#define PIN_PC2				66
+#define PIN_PC2__GPIO			PINMUX_PIN(PIN_PC2, 0, 0)
+#define PIN_PC2__EXT_IRQ0		PINMUX_PIN(PIN_PC2, 1, 3)
+#define PIN_PC2__FLEXCOM9_IO3		PINMUX_PIN(PIN_PC2, 3, 2)
+#define PIN_PC2__A11			PINMUX_PIN(PIN_PC2, 5, 1)
+
+#define PIN_PC3				67
+#define PIN_PC3__GPIO			PINMUX_PIN(PIN_PC3, 0, 0)
+#define PIN_PC3__SPDIF_RX		PINMUX_PIN(PIN_PC3, 1, 2)
+#define PIN_PC3__FLEXCOM9_IO0		PINMUX_PIN(PIN_PC3, 3, 2)
+#define PIN_PC3__FLEXCOM0_IO4		PINMUX_PIN(PIN_PC3, 4, 2)
+#define PIN_PC3__A10			PINMUX_PIN(PIN_PC3, 5, 1)
+
+#define PIN_PC4				68
+#define PIN_PC4__GPIO			PINMUX_PIN(PIN_PC4, 0, 0)
+#define PIN_PC4__SPDIF_TX		PINMUX_PIN(PIN_PC4, 1, 2)
+#define PIN_PC4__FLEXCOM9_IO1		PINMUX_PIN(PIN_PC4, 3, 2)
+#define PIN_PC4__FLEXCOM0_IO3		PINMUX_PIN(PIN_PC4, 4, 2)
+#define PIN_PC4__D0			PINMUX_PIN(PIN_PC4, 5, 2)
+
+#define PIN_PC5				69
+#define PIN_PC5__GPIO			PINMUX_PIN(PIN_PC5, 0, 0)
+#define PIN_PC5__I3CC_SDASPUE		PINMUX_PIN(PIN_PC5, 1, 1)
+#define PIN_PC5__I2SMCC1_DIN3		PINMUX_PIN(PIN_PC5, 2, 1)
+#define PIN_PC5__FLEXCOM0_IO2		PINMUX_PIN(PIN_PC5, 4, 2)
+#define PIN_PC5__D1			PINMUX_PIN(PIN_PC5, 5, 2)
+
+#define PIN_PC6				70
+#define PIN_PC6__GPIO			PINMUX_PIN(PIN_PC6, 0, 0)
+#define PIN_PC6__I3CC_SCL		PINMUX_PIN(PIN_PC6, 1, 1)
+#define PIN_PC6__FLEXCOM0_IO1		PINMUX_PIN(PIN_PC6, 4, 2)
+#define PIN_PC6__D4			PINMUX_PIN(PIN_PC6, 5, 2)
+
+#define PIN_PC7				71
+#define PIN_PC7__GPIO			PINMUX_PIN(PIN_PC7, 0, 0)
+#define PIN_PC7__I3CC_SDA		PINMUX_PIN(PIN_PC7, 1, 1)
+#define PIN_PC7__FLEXCOM0_IO0		PINMUX_PIN(PIN_PC7, 4, 2)
+#define PIN_PC7__D5			PINMUX_PIN(PIN_PC7, 5, 2)
+
+#define PIN_PC8				72
+#define PIN_PC8__GPIO			PINMUX_PIN(PIN_PC8, 0, 0)
+#define PIN_PC8__I2SMCC0_DIN1		PINMUX_PIN(PIN_PC8, 1, 1)
+#define PIN_PC8__PDMC0_DS1		PINMUX_PIN(PIN_PC8, 2, 2)
+#define PIN_PC8__I2SMCC1_DOUT1		PINMUX_PIN(PIN_PC8, 3, 1)
+#define PIN_PC8__FLEXCOM9_IO0		PINMUX_PIN(PIN_PC8, 4, 1)
+#define PIN_PC8__D6			PINMUX_PIN(PIN_PC8, 5, 2)
+
+#define PIN_PC9				73
+#define PIN_PC9__GPIO			PINMUX_PIN(PIN_PC9, 0, 0)
+#define PIN_PC9__I2SMCC0_DIN2		PINMUX_PIN(PIN_PC9, 1, 1)
+#define PIN_PC9__PDMC0_CLK		PINMUX_PIN(PIN_PC9, 2, 2)
+#define PIN_PC9__I2SMCC1_DOUT2		PINMUX_PIN(PIN_PC9, 3, 1)
+#define PIN_PC9__FLEXCOM9_IO1		PINMUX_PIN(PIN_PC9, 4, 1)
+#define PIN_PC9__D7			PINMUX_PIN(PIN_PC9, 5, 2)
+
+#define PIN_PC10			74
+#define PIN_PC10__GPIO			PINMUX_PIN(PIN_PC10, 0, 0)
+#define PIN_PC10__I2SMCC0_DIN3		PINMUX_PIN(PIN_PC10, 1, 1)
+#define PIN_PC10__PDMC0_DS0		PINMUX_PIN(PIN_PC10, 2, 2)
+#define PIN_PC10__I2SMCC1_DOUT3		PINMUX_PIN(PIN_PC10, 3, 1)
+#define PIN_PC10__FLEXCOM9_IO2		PINMUX_PIN(PIN_PC10, 4, 1)
+#define PIN_PC10__D2			PINMUX_PIN(PIN_PC10, 5, 2)
+
+#define PIN_PC11			75
+#define PIN_PC11__GPIO			PINMUX_PIN(PIN_PC11, 0, 0)
+#define PIN_PC11__I2SMCC0_DOUT1		PINMUX_PIN(PIN_PC11, 1, 1)
+#define PIN_PC11__PDMC1_DS0		PINMUX_PIN(PIN_PC11, 2, 1)
+#define PIN_PC11__FLEXCOM9_IO3		PINMUX_PIN(PIN_PC11, 4, 1)
+#define PIN_PC10__D3			PINMUX_PIN(PIN_PC10, 5, 2)
+
+#define PIN_PC12			76
+#define PIN_PC12__GPIO			PINMUX_PIN(PIN_PC12, 0, 0)
+#define PIN_PC12__I2SMCC0_DOUT2		PINMUX_PIN(PIN_PC12, 1, 1)
+#define PIN_PC12__PDMC1_CLK		PINMUX_PIN(PIN_PC12, 2, 1)
+#define PIN_PC12__FLEXCOM9_IO4		PINMUX_PIN(PIN_PC12, 4, 1)
+#define PIN_PC12__A9			PINMUX_PIN(PIN_PC12, 5, 1)
+
+#define PIN_PC13			77
+#define PIN_PC13__GPIO			PINMUX_PIN(PIN_PC13, 0, 0)
+#define PIN_PC13__I2SMCC0_DOUT3		PINMUX_PIN(PIN_PC13, 1, 1)
+#define PIN_PC13__PDMC1_DS1		PINMUX_PIN(PIN_PC13, 2, 1)
+#define PIN_PC13__A8			PINMUX_PIN(PIN_PC13, 5, 1)
+
+#define PIN_PC14			78
+#define PIN_PC14__GPIO			PINMUX_PIN(PIN_PC14, 0, 0)
+#define PIN_PC14__I2SMCC1_DIN0		PINMUX_PIN(PIN_PC14, 1, 1)
+#define PIN_PC14__SPDIF_RX		PINMUX_PIN(PIN_PC14, 2, 3)
+#define PIN_PC14__FLEXCOM1_IO0		PINMUX_PIN(PIN_PC14, 3, 2)
+#define PIN_PC14__A7			PINMUX_PIN(PIN_PC14, 5, 1)
+
+#define PIN_PC15			79
+#define PIN_PC15__GPIO			PINMUX_PIN(PIN_PC15, 0, 0)
+#define PIN_PC15__I2SMCC1_WS		PINMUX_PIN(PIN_PC15, 1, 1)
+#define PIN_PC15__PDMC1_DS1		PINMUX_PIN(PIN_PC15, 2, 2)
+#define PIN_PC15__FLEXCOM1_IO1		PINMUX_PIN(PIN_PC15, 3, 2)
+#define PIN_PC15__A6			PINMUX_PIN(PIN_PC15, 5, 1)
+
+#define PIN_PC16			80
+#define PIN_PC16__GPIO			PINMUX_PIN(PIN_PC16, 0, 0)
+#define PIN_PC16__I2SMCC1_CK		PINMUX_PIN(PIN_PC16, 1, 1)
+#define PIN_PC16__PDMC1_CLK		PINMUX_PIN(PIN_PC16, 2, 2)
+#define PIN_PC16__FLEXCOM1_IO2		PINMUX_PIN(PIN_PC16, 3, 2)
+#define PIN_PC16__TIOA1			PINMUX_PIN(PIN_PC16, 4, 2)
+#define PIN_PC16__A5			PINMUX_PIN(PIN_PC16, 5, 1)
+
+#define PIN_PC17			81
+#define PIN_PC17__GPIO			PINMUX_PIN(PIN_PC17, 0, 0)
+#define PIN_PC17__I2SMCC1_DOUT0		PINMUX_PIN(PIN_PC17, 1, 1)
+#define PIN_PC17__PDMC1_DS0		PINMUX_PIN(PIN_PC17, 2, 2)
+#define PIN_PC17__FLEXCOM1_IO3		PINMUX_PIN(PIN_PC17, 3, 2)
+#define PIN_PC17__TCLK1			PINMUX_PIN(PIN_PC17, 4, 2)
+#define PIN_PC17__A4			PINMUX_PIN(PIN_PC17, 5, 1)
+
+#define PIN_PC18			82
+#define PIN_PC18__GPIO			PINMUX_PIN(PIN_PC18, 0, 0)
+#define PIN_PC18__I2SMCC0_DIN0		PINMUX_PIN(PIN_PC18, 1, 1)
+#define PIN_PC18__SPDIF_TX		PINMUX_PIN(PIN_PC18, 2, 3)
+#define PIN_PC18__FLEXCOM1_IO4		PINMUX_PIN(PIN_PC18, 3, 2)
+#define PIN_PC18__TIOB1			PINMUX_PIN(PIN_PC18, 4, 2)
+#define PIN_PC18__A3			PINMUX_PIN(PIN_PC18, 5, 1)
+
+#define PIN_PC19			83
+#define PIN_PC19__GPIO			PINMUX_PIN(PIN_PC19, 0, 0)
+#define PIN_PC19__I2SMCC0_WS		PINMUX_PIN(PIN_PC19, 1, 1)
+#define PIN_PC19__PCK6			PINMUX_PIN(PIN_PC19, 2, 1)
+#define PIN_PC19__A2			PINMUX_PIN(PIN_PC19, 5, 1)
+
+#define PIN_PC20			84
+#define PIN_PC20__GPIO			PINMUX_PIN(PIN_PC20, 0, 0)
+#define PIN_PC20__I2SMCC0_DOUT0		PINMUX_PIN(PIN_PC20, 1, 1)
+#define PIN_PC20__A1			PINMUX_PIN(PIN_PC20, 5, 1)
+
+#define PIN_PC21			85
+#define PIN_PC21__GPIO			PINMUX_PIN(PIN_PC21, 0, 0)
+#define PIN_PC21__I2SMCC0_CK		PINMUX_PIN(PIN_PC21, 1, 1)
+#define PIN_PC21__PCK7			PINMUX_PIN(PIN_PC21, 2, 1)
+#define PIN_PC21__A0			PINMUX_PIN(PIN_PC21, 5, 1)
+
+#define PIN_PC22			86
+#define PIN_PC22__GPIO			PINMUX_PIN(PIN_PC22, 0, 0)
+#define PIN_PC22__NTRST			PINMUX_PIN(PIN_PC22, 1, 1)
+#define PIN_PC22__NWAIT			PINMUX_PIN(PIN_PC22, 5, 1)
+
+#define PIN_PC23			87
+#define PIN_PC23__GPIO			PINMUX_PIN(PIN_PC23, 0, 0)
+#define PIN_PC23__TCK_SWCLK		PINMUX_PIN(PIN_PC23, 1, 1)
+
+#define PIN_PC24			88
+#define PIN_PC24__GPIO			PINMUX_PIN(PIN_PC24, 0, 0)
+#define PIN_PC24__TMS_SWDIO		PINMUX_PIN(PIN_PC24, 1, 1)
+
+#define PIN_PC25			89
+#define PIN_PC25__GPIO			PINMUX_PIN(PIN_PC25, 0, 0)
+#define PIN_PC25__TDI			PINMUX_PIN(PIN_PC25, 1, 1)
+
+#define PIN_PC26			90
+#define PIN_PC26__GPIO			PINMUX_PIN(PIN_PC26, 0, 0)
+#define PIN_PC26__TDO			PINMUX_PIN(PIN_PC26, 1, 1)
+#define PIN_PC26__A15			PINMUX_PIN(PIN_PC26, 5, 1)
+
+#define PIN_PC27			91
+#define PIN_PC27__GPIO			PINMUX_PIN(PIN_PC27, 0, 0)
+#define PIN_PC27__SDMMC2_CMD		PINMUX_PIN(PIN_PC27, 1, 1)
+#define PIN_PC27__FLEXCOM8_IO0		PINMUX_PIN(PIN_PC27, 2, 2)
+#define PIN_PC27__TD1			PINMUX_PIN(PIN_PC27, 4, 2)
+#define PIN_PC27__D8			PINMUX_PIN(PIN_PC27, 5, 1)
+
+#define PIN_PC28			92
+#define PIN_PC28__GPIO			PINMUX_PIN(PIN_PC28, 0, 0)
+#define PIN_PC28__SDMMC2_CK		PINMUX_PIN(PIN_PC28, 1, 1)
+#define PIN_PC28__FLEXCOM8_IO1		PINMUX_PIN(PIN_PC28, 2, 2)
+#define PIN_PC28__TF1			PINMUX_PIN(PIN_PC28, 4, 2)
+#define PIN_PC28__D9			PINMUX_PIN(PIN_PC28, 5, 1)
+
+#define PIN_PC29			93
+#define PIN_PC29__GPIO			PINMUX_PIN(PIN_PC29, 0, 0)
+#define PIN_PC29__SDMMC2_DAT0		PINMUX_PIN(PIN_PC29, 1, 1)
+#define PIN_PC29__FLEXCOM8_IO2		PINMUX_PIN(PIN_PC29, 2, 2)
+#define PIN_PC29__TK1			PINMUX_PIN(PIN_PC29, 4, 2)
+#define PIN_PC29__D10			PINMUX_PIN(PIN_PC29, 5, 1)
+#define PIN_PC29__TCLK0			PINMUX_PIN(PIN_PC29, 6, 1)
+
+#define PIN_PC30			94
+#define PIN_PC30__GPIO			PINMUX_PIN(PIN_PC30, 0, 0)
+#define PIN_PC30__SDMMC2_DAT1		PINMUX_PIN(PIN_PC30, 1, 1)
+#define PIN_PC30__FLEXCOM8_IO3		PINMUX_PIN(PIN_PC30, 2, 2)
+#define PIN_PC30__RD1			PINMUX_PIN(PIN_PC30, 4, 2)
+#define PIN_PC30__D11			PINMUX_PIN(PIN_PC30, 5, 1)
+#define PIN_PC30__TIOA0			PINMUX_PIN(PIN_PC30, 6, 1)
+
+#define PIN_PC31			95
+#define PIN_PC31__GPIO			PINMUX_PIN(PIN_PC31, 0, 0)
+#define PIN_PC31__SDMMC2_DAT2		PINMUX_PIN(PIN_PC31, 1, 1)
+#define PIN_PC31__FLEXCOM8_IO4		PINMUX_PIN(PIN_PC31, 2, 2)
+#define PIN_PC31__PCK0			PINMUX_PIN(PIN_PC31, 3, 2)
+#define PIN_PC31__RK1			PINMUX_PIN(PIN_PC31, 4, 2)
+#define PIN_PC31__D12			PINMUX_PIN(PIN_PC31, 5, 1)
+#define PIN_PC31__TIOB0			PINMUX_PIN(PIN_PC31, 6, 1)
+
+#define PIN_PD0				96
+#define PIN_PD0__GPIO			PINMUX_PIN(PIN_PD0, 0, 0)
+#define PIN_PD0__SDMMC2_DAT3		PINMUX_PIN(PIN_PD0, 1, 1)
+#define PIN_PD0__PCK1			PINMUX_PIN(PIN_PD0, 3, 2)
+#define PIN_PD0__RF1			PINMUX_PIN(PIN_PD0, 4, 2)
+#define PIN_PD0__D13			PINMUX_PIN(PIN_PD0, 5, 1)
+
+#define PIN_PD1				97
+#define PIN_PD1__GPIO			PINMUX_PIN(PIN_PD1, 0, 0)
+#define PIN_PD1__SDMMC2_WP		PINMUX_PIN(PIN_PD1, 1, 1)
+#define PIN_PD1__FLEXCOM1_IO5		PINMUX_PIN(PIN_PD1, 2, 1)
+#define PIN_PD1__LCDC_HSYNC		PINMUX_PIN(PIN_PD1, 3, 2)
+#define PIN_PD1__FLEXCOM3_IO0		PINMUX_PIN(PIN_PD1, 4, 3)
+
+#define PIN_PD2				98
+#define PIN_PD2__GPIO			PINMUX_PIN(PIN_PD2, 0, 0)
+#define PIN_PD2__SDMMC2_CD		PINMUX_PIN(PIN_PD2, 1, 1)
+#define PIN_PD2__FLEXCOM1_IO6		PINMUX_PIN(PIN_PD2, 2, 1)
+#define PIN_PD2__LCDC_VSYNC		PINMUX_PIN(PIN_PD2, 3, 2)
+#define PIN_PD2__FLEXCOM3_IO1		PINMUX_PIN(PIN_PD2, 4, 3)
+
+#define PIN_PD3				99
+#define PIN_PD3__GPIO			PINMUX_PIN(PIN_PD3, 0, 0)
+#define PIN_PD3__SDMMC2_1V8SEL		PINMUX_PIN(PIN_PD3, 1, 1)
+#define PIN_PD3__FLEXCOM1_IO4		PINMUX_PIN(PIN_PD3, 2, 1)
+#define PIN_PD3__TIOA0			PINMUX_PIN(PIN_PD3, 3, 2)
+#define PIN_PD3__FLEXCOM3_IO2		PINMUX_PIN(PIN_PD3, 4, 3)
+#define PIN_PD3__EXT_IRQ1		PINMUX_PIN(PIN_PD3, 5, 3)
+
+#define PIN_PD4				100
+#define PIN_PD4__GPIO			PINMUX_PIN(PIN_PD4, 0, 0)
+#define PIN_PD4__LCDC_HSYNC		PINMUX_PIN(PIN_PD4, 1, 1)
+#define PIN_PD4__FLEXCOM1_IO2		PINMUX_PIN(PIN_PD4, 2, 1)
+#define PIN_PD4__TIOB0			PINMUX_PIN(PIN_PD4, 3, 2)
+#define PIN_PD4__FLEXCOM7_IO1		PINMUX_PIN(PIN_PD4, 4, 3)
+
+#define PIN_PD5				101
+#define PIN_PD5__GPIO			PINMUX_PIN(PIN_PD5, 0, 0)
+#define PIN_PD5__LCDC_VSYNC		PINMUX_PIN(PIN_PD5, 1, 1)
+#define PIN_PD5__FLEXCOM1_IO3		PINMUX_PIN(PIN_PD5, 2, 1)
+#define PIN_PD5__TCLK0			PINMUX_PIN(PIN_PD5, 3, 2)
+#define PIN_PD5__FLEXCOM7_IO0		PINMUX_PIN(PIN_PD5, 4, 3)
+
+#define PIN_PD6				102
+#define PIN_PD6__GPIO			PINMUX_PIN(PIN_PD6, 0, 0)
+#define PIN_PD6__LCDC_PWM		PINMUX_PIN(PIN_PD6, 1, 1)
+#define PIN_PD6__FLEXCOM1_IO1		PINMUX_PIN(PIN_PD6, 2, 1)
+#define PIN_PD6__FLEXCOM7_IO2		PINMUX_PIN(PIN_PD6, 4, 3)
+
+#define PIN_PD7				103
+#define PIN_PD7__GPIO			PINMUX_PIN(PIN_PD7, 0, 0)
+#define PIN_PD7__LCDC_DISP		PINMUX_PIN(PIN_PD7, 1, 1)
+#define PIN_PD7__FLEXCOM1_IO0		PINMUX_PIN(PIN_PD7, 2, 1)
+#define PIN_PD7__FLEXCOM7_IO3		PINMUX_PIN(PIN_PD7, 4, 3)
+
+#define PIN_PD8				104
+#define PIN_PD8__GPIO			PINMUX_PIN(PIN_PD8, 0, 0)
+#define PIN_PD8__CANTX0			PINMUX_PIN(PIN_PD8, 1, 1)
+#define PIN_PD8__FLEXCOM7_IO0		PINMUX_PIN(PIN_PD8, 2, 1)
+
+#define PIN_PD9				105
+#define PIN_PD9__GPIO			PINMUX_PIN(PIN_PD9, 0, 0)
+#define PIN_PD9__CANRX0			PINMUX_PIN(PIN_PD9, 1, 1)
+#define PIN_PD9__FLEXCOM7_IO1		PINMUX_PIN(PIN_PD9, 2, 1)
+
+#define PIN_PD10			106
+#define PIN_PD10__GPIO			PINMUX_PIN(PIN_PD10, 0, 0)
+#define PIN_PD10__CANTX1		PINMUX_PIN(PIN_PD10, 1, 1)
+#define PIN_PD10__FLEXCOM7_IO2		PINMUX_PIN(PIN_PD10, 2, 1)
+#define PIN_PD10__TIOA1			PINMUX_PIN(PIN_PD10, 3, 3)
+
+#define PIN_PD11			107
+#define PIN_PD11__GPIO			PINMUX_PIN(PIN_PD11, 0, 0)
+#define PIN_PD11__CANRX1		PINMUX_PIN(PIN_PD11, 1, 1)
+#define PIN_PD11__FLEXCOM7_IO3		PINMUX_PIN(PIN_PD11, 2, 1)
+#define PIN_PD11__TCLK1			PINMUX_PIN(PIN_PD11, 3, 3)
+
+#define PIN_PD12			108
+#define PIN_PD12__GPIO			PINMUX_PIN(PIN_PD12, 0, 0)
+#define PIN_PD12__CANTX2		PINMUX_PIN(PIN_PD12, 1, 1)
+#define PIN_PD12__FLEXCOM7_IO4		PINMUX_PIN(PIN_PD12, 2, 1)
+#define PIN_PD12__TIOB1			PINMUX_PIN(PIN_PD12, 3, 3)
+#define PIN_PD12__PCK2			PINMUX_PIN(PIN_PD12, 4, 2)
+#define PIN_PD12__FLEXCOM3_IO3		PINMUX_PIN(PIN_PD12, 5, 3)
+
+#define PIN_PD13			109
+#define PIN_PD13__GPIO			PINMUX_PIN(PIN_PD13, 0, 0)
+#define PIN_PD13__CANRX2		PINMUX_PIN(PIN_PD13, 1, 1)
+#define PIN_PD13__FLEXCOM5_IO4		PINMUX_PIN(PIN_PD13, 2, 1)
+#define PIN_PD13__TIOA2			PINMUX_PIN(PIN_PD13, 3, 3)
+#define PIN_PD13__PCK3			PINMUX_PIN(PIN_PD13, 4, 2)
+
+#define PIN_PD14			110
+#define PIN_PD14__GPIO			PINMUX_PIN(PIN_PD14, 0, 0)
+#define PIN_PD14__CANTX3		PINMUX_PIN(PIN_PD14, 1, 1)
+#define PIN_PD14__FLEXCOM5_IO2		PINMUX_PIN(PIN_PD14, 2, 1)
+#define PIN_PD14__TIOB2			PINMUX_PIN(PIN_PD14, 3, 3)
+
+#define PIN_PD15			111
+#define PIN_PD15__GPIO			PINMUX_PIN(PIN_PD15, 0, 0)
+#define PIN_PD15__CANRX3		PINMUX_PIN(PIN_PD15, 1, 1)
+#define PIN_PD15__FLEXCOM5_IO3		PINMUX_PIN(PIN_PD15, 2, 1)
+#define PIN_PD15__TCLK2			PINMUX_PIN(PIN_PD15, 3, 3)
+
+#define PIN_PD16			112
+#define PIN_PD16__GPIO			PINMUX_PIN(PIN_PD16, 0, 0)
+#define PIN_PD16__CANTX4		PINMUX_PIN(PIN_PD16, 1, 1)
+#define PIN_PD16__FLEXCOM5_IO0		PINMUX_PIN(PIN_PD16, 2, 1)
+
+#define PIN_PD17			113
+#define PIN_PD17__GPIO			PINMUX_PIN(PIN_PD17, 0, 0)
+#define PIN_PD17__CANRX4		PINMUX_PIN(PIN_PD17, 1, 1)
+#define PIN_PD17__FLEXCOM5_IO1		PINMUX_PIN(PIN_PD17, 2, 1)
+
+#define PIN_PD18			114
+#define PIN_PD18__GPIO			PINMUX_PIN(PIN_PD18, 0, 0)
+#define PIN_PD18__FLEXCOM6_IO0		PINMUX_PIN(PIN_PD18, 2, 4)
+#define PIN_PD18__CANTX1		PINMUX_PIN(PIN_PD18, 3, 2)
+#define PIN_PD18__PCK4			PINMUX_PIN(PIN_PD18, 4, 2)
+
+#define PIN_PD19			115
+#define PIN_PD19__GPIO			PINMUX_PIN(PIN_PD19, 0, 0)
+#define PIN_PD19__FLEXCOM6_IO1		PINMUX_PIN(PIN_PD19, 2, 4)
+#define PIN_PD19__CANRX1		PINMUX_PIN(PIN_PD19, 3, 2)
+#define PIN_PD19__PCK2			PINMUX_PIN(PIN_PD19, 4, 3)
+
+#define PIN_PD20			116
+#define PIN_PD20__GPIO			PINMUX_PIN(PIN_PD20, 0, 0)
+#define PIN_PD20__PFLEXCOM6_IO2		PINMUX_PIN(PIN_PD20, 2, 4)
+#define PIN_PD20__I2SMCC1_MCK		PINMUX_PIN(PIN_PD20, 3, 2)
+#define PIN_PD20__PCK3			PINMUX_PIN(PIN_PD20, 4, 3)
+
+#define PIN_PD21			117
+#define PIN_PD21__GPIO			PINMUX_PIN(PIN_PD21, 0, 0)
+#define PIN_PD21__G1_TXCTL		PINMUX_PIN(PIN_PD21, 1, 2)
+#define PIN_PD21__FLEXCOM6_IO2		PINMUX_PIN(PIN_PD21, 2, 3)
+#define PIN_PD21__TK1			PINMUX_PIN(PIN_PD21, 3, 1)
+
+#define PIN_PD22			118
+#define PIN_PD22__GPIO			PINMUX_PIN(PIN_PD22, 0, 0)
+#define PIN_PD22__G1_TX0		PINMUX_PIN(PIN_PD22, 1, 1)
+#define PIN_PD22__FLEXCOM6_IO3		PINMUX_PIN(PIN_PD22, 2, 3)
+#define PIN_PD22__TF1			PINMUX_PIN(PIN_PD22, 3, 1)
+
+#define PIN_PD23			119
+#define PIN_PD23__GPIO			PINMUX_PIN(PIN_PD23, 0, 0)
+#define PIN_PD23__G1_TX1		PINMUX_PIN(PIN_PD23, 1, 1)
+#define PIN_PD23__FLEXCOM6_IO4		PINMUX_PIN(PIN_PD23, 2, 3)
+#define PIN_PD23__TD1			PINMUX_PIN(PIN_PD23, 3, 1)
+
+#define PIN_PD24			120
+#define PIN_PD24__GPIO			PINMUX_PIN(PIN_PD24, 0, 0)
+#define PIN_PD24__G1_RXCTL		PINMUX_PIN(PIN_PD24, 1, 1)
+#define PIN_PD24__FLEXCOM6_IO0		PINMUX_PIN(PIN_PD24, 2, 3)
+#define PIN_PD24__RD1			PINMUX_PIN(PIN_PD24, 3, 1)
+#define PIN_PD24__PDMC0_DS1		PINMUX_PIN(PIN_PD24, 5, 3)
+
+#define PIN_PD25			121
+#define PIN_PD25__GPIO			PINMUX_PIN(PIN_PD25, 0, 0)
+#define PIN_PD25__G1_MDC		PINMUX_PIN(PIN_PD25, 1, 1)
+#define PIN_PD25__FLEXCOM6_IO1		PINMUX_PIN(PIN_PD25, 2, 3)
+#define PIN_PD25__RK1			PINMUX_PIN(PIN_PD25, 3, 1)
+#define PIN_PD25__PDMC0_CLK		PINMUX_PIN(PIN_PD25, 5, 3)
+
+#define PIN_PD26			122
+#define PIN_PD26__GPIO			PINMUX_PIN(PIN_PD26, 0, 0)
+#define PIN_PD26__G1_MDIO		PINMUX_PIN(PIN_PD26, 1, 1)
+#define PIN_PD26__FLEXCOM7_IO4		PINMUX_PIN(PIN_PD26, 2, 2)
+#define PIN_PD26__RF1			PINMUX_PIN(PIN_PD26, 3, 1)
+#define PIN_PD26__I2SMCC1_DIN2		PINMUX_PIN(PIN_PD26, 4, 2)
+#define PIN_PD26__PDMC0_DS0		PINMUX_PIN(PIN_PD26, 5, 3)
+
+#define PIN_PD27			123
+#define PIN_PD27__GPIO			PINMUX_PIN(PIN_PD27, 0, 0)
+#define PIN_PD27__G1_RX0		PINMUX_PIN(PIN_PD27, 1, 1)
+#define PIN_PD27__FLEXCOM7_IO0		PINMUX_PIN(PIN_PD27, 2, 2)
+#define PIN_PD27__SPDIF_RX		PINMUX_PIN(PIN_PD27, 3, 1)
+#define PIN_PD27__I2SMCC1_DIN3		PINMUX_PIN(PIN_PD27, 4, 2)
+
+#define PIN_PD28			124
+#define PIN_PD28__GPIO			PINMUX_PIN(PIN_PD28, 0, 0)
+#define PIN_PD28__G1_RX1		PINMUX_PIN(PIN_PD28, 1, 1)
+#define PIN_PD28__FLEXCOM7_IO1		PINMUX_PIN(PIN_PD28, 2, 2)
+#define PIN_PD28__SPDIF_TX		PINMUX_PIN(PIN_PD28, 3, 1)
+#define PIN_PD28__I2SMCC1_DIN1		PINMUX_PIN(PIN_PD28, 4, 2)
+
+#define PIN_PD29			125
+#define PIN_PD29__GPIO			PINMUX_PIN(PIN_PD29, 0, 0)
+#define PIN_PD29__G1_REFCK		PINMUX_PIN(PIN_PD29, 1, 2)
+#define PIN_PD29__FLEXCOM7_IO2		PINMUX_PIN(PIN_PD29, 2, 2)
+#define PIN_PD29__I2SMCC1_DOUT3		PINMUX_PIN(PIN_PD29, 3, 2)
+
+#define PIN_PD30			126
+#define PIN_PD30__GPIO			PINMUX_PIN(PIN_PD30, 0, 0)
+#define PIN_PD30__G1_RX2		PINMUX_PIN(PIN_PD30, 1, 1)
+#define PIN_PD30__FLEXCOM7_IO3		PINMUX_PIN(PIN_PD30, 2, 2)
+#define PIN_PD30__I2SMCC1_DOUT1		PINMUX_PIN(PIN_PD30, 3, 2)
+#define PIN_PD30__PDMC1_DS1		PINMUX_PIN(PIN_PD30, 4, 3)
+#define PIN_PD30__G1_RXER		PINMUX_PIN(PIN_PD30, 5, 2)
+
+#define PIN_PD31			127
+#define PIN_PD31__GPIO			PINMUX_PIN(PIN_PD31, 0, 0)
+#define PIN_PD31__G1_RX3		PINMUX_PIN(PIN_PD31, 1, 1)
+#define PIN_PD31__FLEXCOM5_IO4		PINMUX_PIN(PIN_PD31, 2, 2)
+#define PIN_PD31__I2SMCC1_DOUT2		PINMUX_PIN(PIN_PD31, 3, 3)
+#define PIN_PD31__PDMC1_DS0		PINMUX_PIN(PIN_PD31, 4, 3)
+
+#define PIN_PE0				128
+#define PIN_PE0__GPIO			PINMUX_PIN(PIN_PE0, 0, 0)
+#define PIN_PE0__G1_TX2			PINMUX_PIN(PIN_PE0, 1, 1)
+#define PIN_PE0__FLEXCOM5_IO2		PINMUX_PIN(PIN_PE0, 2, 2)
+#define PIN_PE0__I2SMCC1_DIN0		PINMUX_PIN(PIN_PE0, 3, 2)
+#define PIN_PE0__PDMC1_CLK		PINMUX_PIN(PIN_PE0, 4, 3)
+
+#define PIN_PE1				129
+#define PIN_PE1__GPIO			PINMUX_PIN(PIN_PE1, 0, 0)
+#define PIN_PE1__G1_TX3			PINMUX_PIN(PIN_PE1, 1, 1)
+#define PIN_PE1__FLEXCOM5_IO3		PINMUX_PIN(PIN_PE1, 2, 2)
+#define PIN_PE1__I2SMCC1_WS		PINMUX_PIN(PIN_PE1, 3, 2)
+#define PIN_PE1__PDMC0_DS1		PINMUX_PIN(PIN_PE1, 4, 4)
+
+#define PIN_PE2				130
+#define PIN_PE2__GPIO			PINMUX_PIN(PIN_PE2, 0, 0)
+#define PIN_PE2__G1_RXCK		PINMUX_PIN(PIN_PE2, 1, 1)
+#define PIN_PE2__FLEXCOM5_IO1		PINMUX_PIN(PIN_PE2, 2, 2)
+#define PIN_PE2__I2SMCC1_CK		PINMUX_PIN(PIN_PE2, 3, 2)
+#define PIN_PE2__PDMC0_CLK		PINMUX_PIN(PIN_PE2, 4, 4)
+
+#define PIN_PE3				131
+#define PIN_PE3__GPIO			PINMUX_PIN(PIN_PE3, 0, 0)
+#define PIN_PE3__G1_TSUCOMP		PINMUX_PIN(PIN_PE3, 1, 1)
+#define PIN_PE3__FLEXCOM5_IO0		PINMUX_PIN(PIN_PE3, 2, 2)
+#define PIN_PE3__I2SMCC1_DOUT0		PINMUX_PIN(PIN_PE3, 3, 2)
+#define PIN_PE3__PDMC0_DS0		PINMUX_PIN(PIN_PE3, 4, 4)
+
+#define PIN_PE4				132
+#define PIN_PE4__GPIO			PINMUX_PIN(PIN_PE4, 0, 0)
+#define PIN_PE4__LCDC_DAT0		PINMUX_PIN(PIN_PE4, 1, 1)
+#define PIN_PE4__FLEXCOM2_IO2		PINMUX_PIN(PIN_PE4, 2, 1)
+#define PIN_PE4__PWML0			PINMUX_PIN(PIN_PE4, 3, 2)
+#define PIN_PE4__TIOA3			PINMUX_PIN(PIN_PE4, 4, 1)
+#define PIN_PE4__I2SMCC0_DIN1		PINMUX_PIN(PIN_PE4, 5, 2)
+
+#define PIN_PE5				133
+#define PIN_PE5__GPIO			PINMUX_PIN(PIN_PE5, 0, 0)
+#define PIN_PE5__LCDC_DAT1		PINMUX_PIN(PIN_PE5, 1, 1)
+#define PIN_PE5__FLEXCOM2_IO3		PINMUX_PIN(PIN_PE5, 2, 1)
+#define PIN_PE5__PWMH0			PINMUX_PIN(PIN_PE5, 3, 2)
+#define PIN_PE5__TIOB3			PINMUX_PIN(PIN_PE5, 4, 1)
+#define PIN_PE5__I2SMCC0_DIN2		PINMUX_PIN(PIN_PE5, 5, 2)
+
+#define PIN_PE6				134
+#define PIN_PE6__GPIO			PINMUX_PIN(PIN_PE6, 0, 0)
+#define PIN_PE6__LCDC_DAT2		PINMUX_PIN(PIN_PE6, 1, 1)
+#define PIN_PE6__FLEXCOM2_IO4		PINMUX_PIN(PIN_PE6, 2, 1)
+#define PIN_PE6__PWML1			PINMUX_PIN(PIN_PE6, 3, 2)
+#define PIN_PE6__TCLK3			PINMUX_PIN(PIN_PE6, 4, 1)
+#define PIN_PE6__I2SMCC0_DIN3		PINMUX_PIN(PIN_PE6, 5, 2)
+
+#define PIN_PE7				135
+#define PIN_PE7__GPIO			PINMUX_PIN(PIN_PE7, 0, 0)
+#define PIN_PE7__LCDC_DAT3		PINMUX_PIN(PIN_PE7, 1, 1)
+#define PIN_PE7__FLEXCOM2_IO5		PINMUX_PIN(PIN_PE7, 2, 1)
+#define PIN_PE7__PWMH1			PINMUX_PIN(PIN_PE7, 3, 2)
+#define PIN_PE7__TIOA4			PINMUX_PIN(PIN_PE7, 4, 1)
+#define PIN_PE7__I2SMCC0_DOUT1		PINMUX_PIN(PIN_PE7, 5, 2)
+
+#define PIN_PE8				136
+#define PIN_PE8__GPIO			PINMUX_PIN(PIN_PE8, 0, 0)
+#define PIN_PE8__LCDC_DAT4		PINMUX_PIN(PIN_PE8, 1, 1)
+#define PIN_PE8__FLEXCOM2_IO0		PINMUX_PIN(PIN_PE8, 2, 1)
+#define PIN_PE8__PWML2			PINMUX_PIN(PIN_PE8, 3, 2)
+#define PIN_PE8__TIOB4			PINMUX_PIN(PIN_PE8, 4, 1)
+#define PIN_PE8__I2SMCC0_CK		PINMUX_PIN(PIN_PE8, 5, 2)
+
+#define PIN_PE9				137
+#define PIN_PE9__GPIO			PINMUX_PIN(PIN_PE9, 0, 0)
+#define PIN_PE9__LCDC_DAT5		PINMUX_PIN(PIN_PE9, 1, 1)
+#define PIN_PE9__FLEXCOM2_IO1		PINMUX_PIN(PIN_PE9, 2, 1)
+#define PIN_PE9__PWMH2			PINMUX_PIN(PIN_PE9, 3, 2)
+#define PIN_PE9__TCLK4			PINMUX_PIN(PIN_PE9, 4, 1)
+#define PIN_PE9__I2SMCC0_WS		PINMUX_PIN(PIN_PE9, 5, 2)
+
+#define PIN_PE10			138
+#define PIN_PE10__GPIO			PINMUX_PIN(PIN_PE10, 0, 0)
+#define PIN_PE10__LCDC_DAT6		PINMUX_PIN(PIN_PE10, 1, 1)
+#define PIN_PE10__FLEXCOM2_IO6		PINMUX_PIN(PIN_PE10, 2, 1)
+#define PIN_PE10__PWML3			PINMUX_PIN(PIN_PE10, 3, 2)
+#define PIN_PE10__TIOA5			PINMUX_PIN(PIN_PE10, 4, 1)
+#define PIN_PE10__I2SMCC0_DOUT2		PINMUX_PIN(PIN_PE10, 5, 2)
+
+#define PIN_PE11			139
+#define PIN_PE11__GPIO			PINMUX_PIN(PIN_PE11, 0, 0)
+#define PIN_PE11__LCDC_DAT7		PINMUX_PIN(PIN_PE11, 1, 1)
+#define PIN_PE11__PWMH3			PINMUX_PIN(PIN_PE11, 3, 2)
+#define PIN_PE11__TIOB5			PINMUX_PIN(PIN_PE11, 4, 1)
+#define PIN_PE11__I2SMCC0_DOUT3		PINMUX_PIN(PIN_PE11, 5, 2)
+
+#define PIN_PE12			140
+#define PIN_PE12__GPIO			PINMUX_PIN(PIN_PE12, 0, 0)
+#define PIN_PE12__LCDC_DEN		PINMUX_PIN(PIN_PE12, 1, 1)
+#define PIN_PE12__PCK3			PINMUX_PIN(PIN_PE12, 2, 4)
+#define PIN_PE12__PWMEXTRG0		PINMUX_PIN(PIN_PE12, 3, 2)
+#define PIN_PE12__TCLK5			PINMUX_PIN(PIN_PE12, 4, 1)
+#define PIN_PE12__I2SMCC0_DIN0		PINMUX_PIN(PIN_PE12, 5, 2)
+
+#define PIN_PE13			141
+#define PIN_PE13__GPIO			PINMUX_PIN(PIN_PE13, 0, 0)
+#define PIN_PE13__LCDC_PCK		PINMUX_PIN(PIN_PE13, 1, 1)
+#define PIN_PE13__PCK4			PINMUX_PIN(PIN_PE13, 2, 3)
+#define PIN_PE13__PWMEXTRG1		PINMUX_PIN(PIN_PE13, 3, 2)
+#define PIN_PE13__I2SMCC0DOUT0		PINMUX_PIN(PIN_PE13, 5, 2)
diff --git a/dts/upstream/src/arm/microchip/sama7d65.dtsi b/dts/upstream/src/arm/microchip/sama7d65.dtsi
new file mode 100644
index 00000000000..854b30d15dc
--- /dev/null
+++ b/dts/upstream/src/arm/microchip/sama7d65.dtsi
@@ -0,0 +1,144 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ *  sama7d65.dtsi - Device Tree Include file for SAMA7D65 SoC
+ *
+ *  Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
+ *
+ *  Author: Ryan Wanner <Ryan.Wanner@microchip.com>
+ *
+ */
+
+#include <dt-bindings/clock/at91.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/mfd/at91-usart.h>
+
+/ {
+	model = "Microchip SAMA7D65 family SoC";
+	compatible = "microchip,sama7d65";
+	#address-cells = <1>;
+	#size-cells = <1>;
+	interrupt-parent = <&gic>;
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu0: cpu@0 {
+			compatible = "arm,cortex-a7";
+			reg = <0x0>;
+			device_type = "cpu";
+			clocks = <&pmc PMC_TYPE_CORE PMC_CPUPLL>;
+			clock-names = "cpu";
+		};
+	};
+
+	clocks {
+		main_xtal: clock-mainxtal {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+		};
+
+		slow_xtal: clock-slowxtal {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+		};
+	};
+
+	soc {
+		compatible = "simple-bus";
+		ranges;
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		pioa: pinctrl@e0014000 {
+			compatible = "microchip,sama7d65-pinctrl", "microchip,sama7g5-pinctrl";
+			reg = <0xe0014000 0x800>;
+			interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&pmc PMC_TYPE_PERIPHERAL 10>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
+
+		pmc: clock-controller@e0018000 {
+			compatible = "microchip,sama7d65-pmc", "syscon";
+			reg = <0xe0018000 0x200>;
+			interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+			#clock-cells = <2>;
+			clocks = <&clk32k 1>, <&clk32k 0>, <&main_xtal>;
+			clock-names = "td_slck", "md_slck", "main_xtal";
+		};
+
+		clk32k: clock-controller@e001d500 {
+			compatible = "microchip,sama7d65-sckc", "microchip,sam9x60-sckc";
+			reg = <0xe001d500 0x4>;
+			clocks = <&slow_xtal>;
+			#clock-cells = <1>;
+		};
+
+		sdmmc1: mmc@e1208000 {
+			compatible = "microchip,sama7d65-sdhci", "microchip,sam9x60-sdhci";
+			reg = <0xe1208000 0x400>;
+			interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&pmc PMC_TYPE_PERIPHERAL 76>, <&pmc PMC_TYPE_GCK 76>;
+			clock-names = "hclock", "multclk";
+			assigned-clocks = <&pmc PMC_TYPE_GCK 76>;
+			assigned-clock-rates = <200000000>;
+			assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_MCK1>;
+			status = "disabled";
+		};
+
+		pit64b0: timer@e1800000 {
+			compatible = "microchip,sama7d65-pit64b", "microchip,sam9x60-pit64b";
+			reg = <0xe1800000 0x100>;
+			interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&pmc PMC_TYPE_PERIPHERAL 66>, <&pmc PMC_TYPE_GCK 66>;
+			clock-names = "pclk", "gclk";
+		};
+
+		pit64b1: timer@e1804000 {
+			compatible = "microchip,sama7d65-pit64b", "microchip,sam9x60-pit64b";
+			reg = <0xe1804000 0x100>;
+			interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&pmc PMC_TYPE_PERIPHERAL 67>, <&pmc PMC_TYPE_GCK 67>;
+			clock-names = "pclk", "gclk";
+		};
+
+		flx6: flexcom@e2020000 {
+			compatible = "microchip,sama7d65-flexcom", "atmel,sama5d2-flexcom";
+			reg = <0xe2020000 0x200>;
+			ranges = <0x0 0xe2020000 0x800>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			clocks = <&pmc PMC_TYPE_PERIPHERAL 40>;
+			status = "disabled";
+
+			uart6: serial@200 {
+				compatible = "microchip,sama7d65-usart", "atmel,at91sam9260-usart";
+				reg = <0x200 0x200>;
+				interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 40>;
+				clock-names = "usart";
+				atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
+				atmel,fifo-size = <16>;
+				status = "disabled";
+			};
+		};
+
+		gic: interrupt-controller@e8c11000 {
+			compatible = "arm,cortex-a7-gic";
+			reg = <0xe8c11000 0x1000>,
+			      <0xe8c12000 0x2000>;
+			#interrupt-cells = <3>;
+			#address-cells = <0>;
+			interrupt-controller;
+		};
+	};
+};
diff --git a/dts/upstream/src/arm/nuvoton/nuvoton-npcm730-gbs.dts b/dts/upstream/src/arm/nuvoton/nuvoton-npcm730-gbs.dts
index 9f64c85e1c2..c3501786d60 100644
--- a/dts/upstream/src/arm/nuvoton/nuvoton-npcm730-gbs.dts
+++ b/dts/upstream/src/arm/nuvoton/nuvoton-npcm730-gbs.dts
@@ -661,7 +661,7 @@
 	clock-frequency = <100000>;
 	status = "okay";
 
-	mb_fru@50 {
+	eeprom@50 {
 		compatible = "atmel,24c64";
 		reg = <0x50>;
 	};
@@ -704,7 +704,7 @@
 				reg = <0x5d>;
 				status = "okay";
 			};
-			fan_fru@51 {
+			eeprom@51 {
 				compatible = "atmel,24c64";
 				reg = <0x51>;
 			};
@@ -714,7 +714,7 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <3>;
-			hsbp_fru@52 {
+			eeprom@52 {
 				compatible = "atmel,24c64";
 				reg = <0x52>;
 				status = "okay";
diff --git a/dts/upstream/src/arm/nuvoton/nuvoton-npcm750-runbmc-olympus.dts b/dts/upstream/src/arm/nuvoton/nuvoton-npcm750-runbmc-olympus.dts
index 087f4ac4318..f67ede14820 100644
--- a/dts/upstream/src/arm/nuvoton/nuvoton-npcm750-runbmc-olympus.dts
+++ b/dts/upstream/src/arm/nuvoton/nuvoton-npcm750-runbmc-olympus.dts
@@ -824,7 +824,7 @@
 		reg = <0x4a>;
 		status = "okay";
 	};
-	m24128_fru@51 {
+	eeprom@51 {
 		compatible = "atmel,24c128";
 		reg = <0x51>;
 		pagesize = <64>;
diff --git a/dts/upstream/src/arm/nvidia/tegra124-nyan.dtsi b/dts/upstream/src/arm/nvidia/tegra124-nyan.dtsi
index 8125c1b3e8d..974c76f007d 100644
--- a/dts/upstream/src/arm/nvidia/tegra124-nyan.dtsi
+++ b/dts/upstream/src/arm/nvidia/tegra124-nyan.dtsi
@@ -716,6 +716,7 @@
 		regulator-name = "+5V_USB_HS";
 		regulator-min-microvolt = <5000000>;
 		regulator-max-microvolt = <5000000>;
+		regulator-boot-on;
 		gpio = <&gpio TEGRA_GPIO(N, 4) GPIO_ACTIVE_HIGH>;
 		enable-active-high;
 		gpio-open-drain;
@@ -727,6 +728,7 @@
 		regulator-name = "+5V_USB_SS";
 		regulator-min-microvolt = <5000000>;
 		regulator-max-microvolt = <5000000>;
+		regulator-boot-on;
 		gpio = <&gpio TEGRA_GPIO(N, 5) GPIO_ACTIVE_HIGH>;
 		enable-active-high;
 		gpio-open-drain;
diff --git a/dts/upstream/src/arm/nxp/imx/imx51-zii-rdu1.dts b/dts/upstream/src/arm/nxp/imx/imx51-zii-rdu1.dts
index 7cd17b43b4b..06545a6052f 100644
--- a/dts/upstream/src/arm/nxp/imx/imx51-zii-rdu1.dts
+++ b/dts/upstream/src/arm/nxp/imx/imx51-zii-rdu1.dts
@@ -160,7 +160,7 @@
 		};
 	};
 
-	mdio_gpio: mdio-gpio {
+	mdio_gpio: mdio {
 		compatible = "virtual,mdio-gpio";
 		pinctrl-names = "default";
 		pinctrl-0 = <&pinctrl_swmdio>;
diff --git a/dts/upstream/src/arm/nxp/imx/imx51-zii-scu2-mezz.dts b/dts/upstream/src/arm/nxp/imx/imx51-zii-scu2-mezz.dts
index 625f9ac671a..26eb7a9506e 100644
--- a/dts/upstream/src/arm/nxp/imx/imx51-zii-scu2-mezz.dts
+++ b/dts/upstream/src/arm/nxp/imx/imx51-zii-scu2-mezz.dts
@@ -37,7 +37,7 @@
 		regulator-max-microvolt = <5000000>;
 	};
 
-	mdio_gpio: mdio-gpio {
+	mdio_gpio: mdio {
 		compatible = "virtual,mdio-gpio";
 		pinctrl-names = "default";
 		pinctrl-0 = <&pinctrl_swmdio>;
diff --git a/dts/upstream/src/arm/nxp/imx/imx6q-bx50v3.dtsi b/dts/upstream/src/arm/nxp/imx/imx6q-bx50v3.dtsi
index c1ae7c47b44..aa1adcc7401 100644
--- a/dts/upstream/src/arm/nxp/imx/imx6q-bx50v3.dtsi
+++ b/dts/upstream/src/arm/nxp/imx/imx6q-bx50v3.dtsi
@@ -94,7 +94,7 @@
 		mdio-gpio0 = &mdio0;
 	};
 
-	mdio0: mdio-gpio {
+	mdio0: mdio {
 		compatible = "virtual,mdio-gpio";
 		gpios = <&gpio2 5 GPIO_ACTIVE_HIGH>, /* mdc */
 			<&gpio2 7 GPIO_ACTIVE_HIGH>; /* mdio */
diff --git a/dts/upstream/src/arm/nxp/imx/imx6qdl-apalis.dtsi b/dts/upstream/src/arm/nxp/imx/imx6qdl-apalis.dtsi
index 1c72da41701..88be29166c1 100644
--- a/dts/upstream/src/arm/nxp/imx/imx6qdl-apalis.dtsi
+++ b/dts/upstream/src/arm/nxp/imx/imx6qdl-apalis.dtsi
@@ -108,6 +108,11 @@
 		};
 	};
 
+	poweroff {
+		compatible = "regulator-poweroff";
+		cpu-supply = <&vgen2_reg>;
+	};
+
 	reg_module_3v3: regulator-module-3v3 {
 		compatible = "regulator-fixed";
 		regulator-always-on;
@@ -236,10 +241,6 @@
 	status = "disabled";
 };
 
-&clks {
-	fsl,pmic-stby-poweroff;
-};
-
 /* Apalis SPI1 */
 &ecspi1 {
 	cs-gpios = <&gpio5 25 GPIO_ACTIVE_LOW>;
@@ -527,7 +528,6 @@
 
 	pmic: pmic@8 {
 		compatible = "fsl,pfuze100";
-		fsl,pmic-stby-poweroff;
 		reg = <0x08>;
 
 		regulators {
@@ -691,7 +691,7 @@
 
 	adv_7280: adv7280@21 {
 		compatible = "adi,adv7280";
-		adv,force-bt656-4;
+		adi,force-bt656-4;
 		pinctrl-names = "default";
 		pinctrl-0 = <&pinctrl_ipu1_csi0>;
 		reg = <0x21>;
diff --git a/dts/upstream/src/arm/nxp/imx/imx6qdl-sabresd.dtsi b/dts/upstream/src/arm/nxp/imx/imx6qdl-sabresd.dtsi
index dc8298f6db3..960e83f5e90 100644
--- a/dts/upstream/src/arm/nxp/imx/imx6qdl-sabresd.dtsi
+++ b/dts/upstream/src/arm/nxp/imx/imx6qdl-sabresd.dtsi
@@ -113,8 +113,8 @@
 			"DMICDAT", "DMIC";
 		mux-int-port = <2>;
 		mux-ext-port = <3>;
-		hp-det-gpio = <&gpio7 8 GPIO_ACTIVE_LOW>;
-		mic-det-gpio = <&gpio1 9 GPIO_ACTIVE_LOW>;
+		hp-det-gpios = <&gpio7 8 GPIO_ACTIVE_LOW>;
+		mic-det-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
 	};
 
 	backlight_lvds: backlight-lvds {
@@ -804,6 +804,7 @@
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_usbotg>;
 	disable-over-current;
+	dr_mode = "otg";
 	status = "okay";
 };
 
diff --git a/dts/upstream/src/arm/nxp/imx/imx6qdl.dtsi b/dts/upstream/src/arm/nxp/imx/imx6qdl.dtsi
index d2200c9db25..45bcfd7faf9 100644
--- a/dts/upstream/src/arm/nxp/imx/imx6qdl.dtsi
+++ b/dts/upstream/src/arm/nxp/imx/imx6qdl.dtsi
@@ -711,8 +711,8 @@
 				reg_vdd3p0: regulator-3p0 {
 					compatible = "fsl,anatop-regulator";
 					regulator-name = "vdd3p0";
-					regulator-min-microvolt = <2800000>;
-					regulator-max-microvolt = <3150000>;
+					regulator-min-microvolt = <2625000>;
+					regulator-max-microvolt = <3400000>;
 					regulator-always-on;
 					anatop-reg-offset = <0x120>;
 					anatop-vol-bit-shift = <8>;
@@ -806,6 +806,7 @@
 				reg = <0x020c9000 0x1000>;
 				interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>;
 				clocks = <&clks IMX6QDL_CLK_USBPHY1>;
+				phy-3p0-supply = <&reg_vdd3p0>;
 				fsl,anatop = <&anatop>;
 			};
 
@@ -814,6 +815,7 @@
 				reg = <0x020ca000 0x1000>;
 				interrupts = <0 45 IRQ_TYPE_LEVEL_HIGH>;
 				clocks = <&clks IMX6QDL_CLK_USBPHY2>;
+				phy-3p0-supply = <&reg_vdd3p0>;
 				fsl,anatop = <&anatop>;
 			};
 
diff --git a/dts/upstream/src/arm/nxp/imx/imx6sl-evk.dts b/dts/upstream/src/arm/nxp/imx/imx6sl-evk.dts
index 55cdfa7ea20..036705b783f 100644
--- a/dts/upstream/src/arm/nxp/imx/imx6sl-evk.dts
+++ b/dts/upstream/src/arm/nxp/imx/imx6sl-evk.dts
@@ -108,7 +108,7 @@
 			"IN3R", "AMIC";
 		mux-int-port = <2>;
 		mux-ext-port = <3>;
-		hp-det-gpio = <&gpio4 19 GPIO_ACTIVE_LOW>;
+		hp-det-gpios = <&gpio4 19 GPIO_ACTIVE_LOW>;
 	};
 
 	panel {
diff --git a/dts/upstream/src/arm/nxp/imx/imx6sl.dtsi b/dts/upstream/src/arm/nxp/imx/imx6sl.dtsi
index 941a2f18505..7381fb7f891 100644
--- a/dts/upstream/src/arm/nxp/imx/imx6sl.dtsi
+++ b/dts/upstream/src/arm/nxp/imx/imx6sl.dtsi
@@ -546,8 +546,8 @@
 				reg_vdd3p0: regulator-3p0 {
 					compatible = "fsl,anatop-regulator";
 					regulator-name = "vdd3p0";
-					regulator-min-microvolt = <2800000>;
-					regulator-max-microvolt = <3150000>;
+					regulator-min-microvolt = <2625000>;
+					regulator-max-microvolt = <3400000>;
 					regulator-always-on;
 					anatop-reg-offset = <0x120>;
 					anatop-vol-bit-shift = <8>;
@@ -640,6 +640,7 @@
 				reg = <0x020c9000 0x1000>;
 				interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>;
 				clocks = <&clks IMX6SL_CLK_USBPHY1>;
+				phy-3p0-supply = <&reg_vdd3p0>;
 				fsl,anatop = <&anatop>;
 			};
 
@@ -648,6 +649,7 @@
 				reg = <0x020ca000 0x1000>;
 				interrupts = <0 45 IRQ_TYPE_LEVEL_HIGH>;
 				clocks = <&clks IMX6SL_CLK_USBPHY2>;
+				phy-3p0-supply = <&reg_vdd3p0>;
 				fsl,anatop = <&anatop>;
 			};
 
diff --git a/dts/upstream/src/arm/nxp/imx/imx6sll-evk.dts b/dts/upstream/src/arm/nxp/imx/imx6sll-evk.dts
index 05d6827ea2a..81440148679 100644
--- a/dts/upstream/src/arm/nxp/imx/imx6sll-evk.dts
+++ b/dts/upstream/src/arm/nxp/imx/imx6sll-evk.dts
@@ -157,7 +157,7 @@
 			"IN3R", "AMIC";
 		mux-int-port = <2>;
 		mux-ext-port = <3>;
-		hp-det-gpio = <&gpio4 24 GPIO_ACTIVE_LOW>;
+		hp-det-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>;
 	};
 };
 
diff --git a/dts/upstream/src/arm/nxp/imx/imx6sx-sdb.dtsi b/dts/upstream/src/arm/nxp/imx/imx6sx-sdb.dtsi
index 1beac42c1a2..67cf09e63a6 100644
--- a/dts/upstream/src/arm/nxp/imx/imx6sx-sdb.dtsi
+++ b/dts/upstream/src/arm/nxp/imx/imx6sx-sdb.dtsi
@@ -167,7 +167,7 @@
 			"IN3R", "AMIC";
 		mux-int-port = <2>;
 		mux-ext-port = <6>;
-		hp-det-gpio = <&gpio1 17 GPIO_ACTIVE_LOW>;
+		hp-det-gpios = <&gpio1 17 GPIO_ACTIVE_LOW>;
 	};
 
 	panel {
diff --git a/dts/upstream/src/arm/nxp/imx/imx6sx.dtsi b/dts/upstream/src/arm/nxp/imx/imx6sx.dtsi
index a9550f115f8..5132b575b00 100644
--- a/dts/upstream/src/arm/nxp/imx/imx6sx.dtsi
+++ b/dts/upstream/src/arm/nxp/imx/imx6sx.dtsi
@@ -637,8 +637,8 @@
 				reg_vdd3p0: regulator-3p0 {
 					compatible = "fsl,anatop-regulator";
 					regulator-name = "vdd3p0";
-					regulator-min-microvolt = <2800000>;
-					regulator-max-microvolt = <3150000>;
+					regulator-min-microvolt = <2625000>;
+					regulator-max-microvolt = <3400000>;
 					regulator-always-on;
 					anatop-reg-offset = <0x120>;
 					anatop-vol-bit-shift = <8>;
@@ -731,6 +731,7 @@
 				reg = <0x020c9000 0x1000>;
 				interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 				clocks = <&clks IMX6SX_CLK_USBPHY1>;
+				phy-3p0-supply = <&reg_vdd3p0>;
 				fsl,anatop = <&anatop>;
 			};
 
@@ -739,6 +740,7 @@
 				reg = <0x020ca000 0x1000>;
 				interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 				clocks = <&clks IMX6SX_CLK_USBPHY2>;
+				phy-3p0-supply = <&reg_vdd3p0>;
 				fsl,anatop = <&anatop>;
 			};
 
diff --git a/dts/upstream/src/arm/nxp/imx/imx6ul-14x14-evk.dtsi b/dts/upstream/src/arm/nxp/imx/imx6ul-14x14-evk.dtsi
index b74ee8948a7..0e839bbfea0 100644
--- a/dts/upstream/src/arm/nxp/imx/imx6ul-14x14-evk.dtsi
+++ b/dts/upstream/src/arm/nxp/imx/imx6ul-14x14-evk.dtsi
@@ -68,7 +68,7 @@
 		audio-cpu = <&sai2>;
 		audio-codec = <&codec>;
 		audio-asrc = <&asrc>;
-		hp-det-gpio = <&gpio5 4 0>;
+		hp-det-gpios = <&gpio5 4 0>;
 		audio-routing =
 			"Headphone Jack", "HP_L",
 			"Headphone Jack", "HP_R",
diff --git a/dts/upstream/src/arm/nxp/imx/imx7-mba7.dtsi b/dts/upstream/src/arm/nxp/imx/imx7-mba7.dtsi
index e1c401f468e..576a7df505d 100644
--- a/dts/upstream/src/arm/nxp/imx/imx7-mba7.dtsi
+++ b/dts/upstream/src/arm/nxp/imx/imx7-mba7.dtsi
@@ -87,34 +87,6 @@
 			      <&adc2 0>, <&adc2 1>, <&adc2 2>, <&adc2 3>;
 	};
 
-	reg_sd1_vmmc: regulator-sd1-vmmc {
-		compatible = "regulator-fixed";
-		regulator-name = "VCC3V3_SD1";
-		regulator-min-microvolt = <3300000>;
-		regulator-max-microvolt = <3300000>;
-		regulator-always-on;
-	};
-
-	reg_fec1_pwdn: regulator-fec1-pwdn {
-		compatible = "regulator-fixed";
-		regulator-name = "PWDN_FEC1";
-		regulator-min-microvolt = <3300000>;
-		regulator-max-microvolt = <3300000>;
-		regulator-always-on;
-		gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
-		enable-active-high;
-	};
-
-	reg_fec2_pwdn: regulator-fec2-pwdn {
-		compatible = "regulator-fixed";
-		regulator-name = "PWDN_FEC2";
-		regulator-min-microvolt = <3300000>;
-		regulator-max-microvolt = <3300000>;
-		regulator-always-on;
-		gpio = <&gpio2 31 GPIO_ACTIVE_HIGH>;
-		enable-active-high;
-	};
-
 	reg_usb_otg1_vbus: regulator-usb-otg1-vbus {
 		compatible = "regulator-fixed";
 		regulator-name = "VBUS_USBOTG1";
@@ -141,6 +113,7 @@
 		gpio = <&pca9555 12 GPIO_ACTIVE_HIGH>;
 		enable-active-high;
 		regulator-always-on;
+		vin-supply = <&reg_mba_5v>;
 	};
 
 	reg_mpcie_3v3: regulator-mpcie-3v3 {
@@ -151,6 +124,7 @@
 		gpio = <&pca9555 10 GPIO_ACTIVE_HIGH>;
 		enable-active-high;
 		regulator-always-on;
+		vin-supply = <&reg_mba_3v3>;
 	};
 
 	reg_mba_12v0: regulator-mba-12v0 {
@@ -162,13 +136,18 @@
 		enable-active-high;
 	};
 
-	reg_lvds_transmitter: regulator-lvds-transmitter {
+	reg_mba_5v: regulator-mba-5v {
 		compatible = "regulator-fixed";
-		regulator-name = "#SHTDN_LVDS";
+		regulator-name = "VCC5V";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+	};
+
+	reg_mba_3v3: regulator-mba-3v3 {
+		compatible = "regulator-fixed";
+		regulator-name = "VCC3V3";
 		regulator-min-microvolt = <3300000>;
 		regulator-max-microvolt = <3300000>;
-		gpio = <&pca9555 1 GPIO_ACTIVE_HIGH>;
-		enable-active-high;
 	};
 
 	reg_vref_1v8: regulator-vref-1v8 {
@@ -186,14 +165,7 @@
 		regulator-min-microvolt = <3300000>;
 		regulator-max-microvolt = <3300000>;
 		regulator-always-on;
-	};
-
-	reg_vcc_3v3: regulator-vcc-3v3 {
-		compatible = "regulator-fixed";
-		regulator-name = "VCC3V3";
-		regulator-min-microvolt = <3300000>;
-		regulator-max-microvolt = <3300000>;
-		regulator-always-on;
+		vin-supply = <&reg_mba_3v3>;
 	};
 
 	sound {
@@ -239,7 +211,6 @@
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_enet1>;
 	phy-mode = "rgmii-id";
-	phy-supply = <&reg_fec1_pwdn>;
 	phy-handle = <&ethphy1_0>;
 	fsl,magic-packet;
 	status = "okay";
@@ -260,6 +231,8 @@
 			reset-gpios = <&gpio7 15 GPIO_ACTIVE_LOW>;
 			reset-assert-us = <1000>;
 			reset-deassert-us = <500>;
+			interrupt-parent = <&gpio1>;
+			interrupts = <9 IRQ_TYPE_EDGE_FALLING>;
 		};
 	};
 };
@@ -318,7 +291,7 @@
 	lm75: temperature-sensor@49 {
 		compatible = "national,lm75a";
 		reg = <0x49>;
-		vs-supply = <&reg_vcc_3v3>;
+		vs-supply = <&reg_mba_3v3>;
 	};
 };
 
@@ -351,7 +324,7 @@
 		interrupts = <12 IRQ_TYPE_EDGE_FALLING>;
 		interrupt-controller;
 		#interrupt-cells = <2>;
-		vcc-supply = <&reg_vcc_3v3>;
+		vcc-supply = <&reg_mba_3v3>;
 	};
 };
 
@@ -668,7 +641,7 @@
 	pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_usdhc1_gpio>;
 	cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
 	wp-gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
-	vmmc-supply = <&reg_sd1_vmmc>;
+	vmmc-supply = <&reg_mba_3v3>;
 	bus-width = <4>;
 	no-1-8-v;
 	no-sdio;
diff --git a/dts/upstream/src/arm/nxp/imx/imx7-tqma7.dtsi b/dts/upstream/src/arm/nxp/imx/imx7-tqma7.dtsi
index 028961eb710..aa8f65cd4ad 100644
--- a/dts/upstream/src/arm/nxp/imx/imx7-tqma7.dtsi
+++ b/dts/upstream/src/arm/nxp/imx/imx7-tqma7.dtsi
@@ -135,6 +135,7 @@
 	lm75a: temperature-sensor@48 {
 		compatible = "national,lm75a";
 		reg = <0x48>;
+		vs-supply = <&vgen4_reg>;
 	};
 
 	/* NXP SE97BTP with temperature sensor + eeprom, TQMa7x 02xx */
@@ -150,7 +151,6 @@
 		reg = <0x50>;
 		pagesize = <32>;
 		vcc-supply = <&vgen4_reg>;
-		status = "okay";
 	};
 
 	at24c02: eeprom@56 {
@@ -158,7 +158,6 @@
 		reg = <0x56>;
 		pagesize = <16>;
 		vcc-supply = <&vgen4_reg>;
-		status = "okay";
 	};
 
 	ds1339: rtc@68 {
diff --git a/dts/upstream/src/arm/nxp/imx/imx7d-mba7.dts b/dts/upstream/src/arm/nxp/imx/imx7d-mba7.dts
index 0443faa3dfa..e3ee16f1aaa 100644
--- a/dts/upstream/src/arm/nxp/imx/imx7d-mba7.dts
+++ b/dts/upstream/src/arm/nxp/imx/imx7d-mba7.dts
@@ -21,7 +21,6 @@
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_enet2>;
 	phy-mode = "rgmii-id";
-	phy-supply = <&reg_fec2_pwdn>;
 	phy-handle = <&ethphy2_0>;
 	fsl,magic-packet;
 	status = "okay";
@@ -42,6 +41,8 @@
 			reset-gpios = <&gpio2 28 GPIO_ACTIVE_LOW>;
 			reset-assert-us = <1000>;
 			reset-deassert-us = <500>;
+			interrupt-parent = <&gpio2>;
+			interrupts = <31 IRQ_TYPE_EDGE_FALLING>;
 		};
 	};
 };
diff --git a/dts/upstream/src/arm/nxp/imx/imx7d-sdb.dts b/dts/upstream/src/arm/nxp/imx/imx7d-sdb.dts
index f712537fca1..6cde8463690 100644
--- a/dts/upstream/src/arm/nxp/imx/imx7d-sdb.dts
+++ b/dts/upstream/src/arm/nxp/imx/imx7d-sdb.dts
@@ -169,7 +169,7 @@
 		model = "wm8960-audio";
 		audio-cpu = <&sai1>;
 		audio-codec = <&codec>;
-		hp-det-gpio = <&gpio2 28 GPIO_ACTIVE_HIGH>;
+		hp-det-gpios = <&gpio2 28 GPIO_ACTIVE_HIGH>;
 		audio-routing =
 			"Headphone Jack", "HP_L",
 			"Headphone Jack", "HP_R",
diff --git a/dts/upstream/src/arm/qcom/qcom-sdx55.dtsi b/dts/upstream/src/arm/qcom/qcom-sdx55.dtsi
index d0f6120b665..39530eb580e 100644
--- a/dts/upstream/src/arm/qcom/qcom-sdx55.dtsi
+++ b/dts/upstream/src/arm/qcom/qcom-sdx55.dtsi
@@ -427,8 +427,9 @@
 			interrupt-names = "global",
 					  "doorbell";
 
-			interconnects = <&system_noc MASTER_PCIE &mc_virt SLAVE_EBI_CH0>;
-			interconnect-names = "pcie-mem";
+			interconnects = <&system_noc MASTER_PCIE &mc_virt SLAVE_EBI_CH0>,
+					<&mem_noc MASTER_AMPSS_M0 &system_noc SLAVE_PCIE_0>;
+			interconnect-names = "pcie-mem", "cpu-pcie";
 
 			resets = <&gcc GCC_PCIE_BCR>;
 			reset-names = "core";
@@ -613,6 +614,8 @@
 				iommus = <&apps_smmu 0x1a0 0x0>;
 				snps,dis_u2_susphy_quirk;
 				snps,dis_enblslpm_quirk;
+				snps,dis-u1-entry-quirk;
+				snps,dis-u2-entry-quirk;
 				phys = <&usb_hsphy>, <&usb_qmpphy>;
 				phy-names = "usb2-phy", "usb3-phy";
 			};
diff --git a/dts/upstream/src/arm/qcom/qcom-sdx65.dtsi b/dts/upstream/src/arm/qcom/qcom-sdx65.dtsi
index 3bc67bb8c1e..6b23ee676c9 100644
--- a/dts/upstream/src/arm/qcom/qcom-sdx65.dtsi
+++ b/dts/upstream/src/arm/qcom/qcom-sdx65.dtsi
@@ -335,6 +335,10 @@
 				     <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-names = "global", "doorbell";
 
+			interconnects = <&system_noc MASTER_PCIE_0 &mc_virt SLAVE_EBI1>,
+					<&mem_noc MASTER_APPSS_PROC &system_noc SLAVE_PCIE_0>;
+			interconnect-names = "pcie-mem", "cpu-pcie";
+
 			resets = <&gcc GCC_PCIE_BCR>;
 			reset-names = "core";
 
@@ -526,6 +530,8 @@
 				iommus = <&apps_smmu 0x1a0 0x0>;
 				snps,dis_u2_susphy_quirk;
 				snps,dis_enblslpm_quirk;
+				snps,dis-u1-entry-quirk;
+				snps,dis-u2-entry-quirk;
 				phys = <&usb_hsphy>, <&usb_qmpphy>;
 				phy-names = "usb2-phy", "usb3-phy";
 			};
diff --git a/dts/upstream/src/arm/renesas/r7s72100.dtsi b/dts/upstream/src/arm/renesas/r7s72100.dtsi
index b831bbc431e..1a866dbaf5e 100644
--- a/dts/upstream/src/arm/renesas/r7s72100.dtsi
+++ b/dts/upstream/src/arm/renesas/r7s72100.dtsi
@@ -238,6 +238,8 @@
 				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-names = "error", "rx", "tx";
 			clocks = <&mstp10_clks R7S72100_CLK_SPI0>;
+			dmas = <&dmac 0x2d21>, <&dmac 0x2d22>;
+			dma-names = "tx", "rx";
 			power-domains = <&cpg_clocks>;
 			num-cs = <1>;
 			#address-cells = <1>;
@@ -253,6 +255,8 @@
 				     <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-names = "error", "rx", "tx";
 			clocks = <&mstp10_clks R7S72100_CLK_SPI1>;
+			dmas = <&dmac 0x2d25>, <&dmac 0x2d26>;
+			dma-names = "tx", "rx";
 			power-domains = <&cpg_clocks>;
 			num-cs = <1>;
 			#address-cells = <1>;
@@ -268,6 +272,8 @@
 				     <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-names = "error", "rx", "tx";
 			clocks = <&mstp10_clks R7S72100_CLK_SPI2>;
+			dmas = <&dmac 0x2d29>, <&dmac 0x2d2a>;
+			dma-names = "tx", "rx";
 			power-domains = <&cpg_clocks>;
 			num-cs = <1>;
 			#address-cells = <1>;
@@ -283,6 +289,8 @@
 				     <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-names = "error", "rx", "tx";
 			clocks = <&mstp10_clks R7S72100_CLK_SPI3>;
+			dmas = <&dmac 0x2d2d>, <&dmac 0x2d2e>;
+			dma-names = "tx", "rx";
 			power-domains = <&cpg_clocks>;
 			num-cs = <1>;
 			#address-cells = <1>;
@@ -298,6 +306,8 @@
 				     <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-names = "error", "rx", "tx";
 			clocks = <&mstp10_clks R7S72100_CLK_SPI4>;
+			dmas = <&dmac 0x2d31>, <&dmac 0x2d32>;
+			dma-names = "tx", "rx";
 			power-domains = <&cpg_clocks>;
 			num-cs = <1>;
 			#address-cells = <1>;
diff --git a/dts/upstream/src/arm/samsung/exynos4212-tab3.dtsi b/dts/upstream/src/arm/samsung/exynos4212-tab3.dtsi
index 9bc05961577..70e3091062f 100644
--- a/dts/upstream/src/arm/samsung/exynos4212-tab3.dtsi
+++ b/dts/upstream/src/arm/samsung/exynos4212-tab3.dtsi
@@ -300,12 +300,31 @@
 		regulator-max-microvolt = <2800000>;
 	};
 
+	earmic_bias_reg: voltage-regulator-6 {
+		compatible = "regulator-fixed";
+		regulator-name = "EAR_MICBIAS_LDO_2.8V";
+		regulator-min-microvolt = <2800000>;
+		regulator-max-microvolt = <2800000>;
+		gpio = <&gpm0 0 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+	};
+
 	sound: sound {
 		compatible = "samsung,midas-audio";
 		model = "TAB3";
 		mic-bias-supply = <&mic_bias_reg>;
 		submic-bias-supply = <&submic_bias_reg>;
 
+		lineout-sel-gpios = <&gpj1 2 GPIO_ACTIVE_HIGH>;
+
+		headset-mic-bias-supply = <&earmic_bias_reg>;
+		headset-detect-gpios = <&gpx0 4 GPIO_ACTIVE_LOW>;
+		headset-key-gpios = <&gpx3 6 GPIO_ACTIVE_LOW>;
+		samsung,headset-4pole-threshold-microvolt = <710 2000>;
+		samsung,headset-button-threshold-microvolt = <0 130 260>;
+		io-channel-names = "headset-detect";
+		io-channels = <&adc 0>;
+
 		audio-routing = "HP", "HPOUT1L",
 				"HP", "HPOUT1R",
 
@@ -351,6 +370,11 @@
 	};
 };
 
+&adc {
+	vdd-supply = <&ldo3_reg>;
+	status = "okay";
+};
+
 &bus_acp {
 	devfreq = <&bus_dmc>;
 	status = "okay";
@@ -511,12 +535,11 @@
 	wm1811: audio-codec@1a {
 		compatible = "wlf,wm1811";
 		reg = <0x1a>;
-		clocks = <&pmu_system_controller 0>;
-		clock-names = "MCLK1";
+		clocks = <&pmu_system_controller 0>,
+			 <&s5m8767_osc S2MPS11_CLK_BT>;
+		clock-names = "MCLK1", "MCLK2";
 		interrupt-controller;
 		#interrupt-cells = <2>;
-		interrupt-parent = <&gpx3>;
-		interrupts = <6 IRQ_TYPE_LEVEL_HIGH>;
 
 		gpio-controller;
 		#gpio-cells = <2>;
diff --git a/dts/upstream/src/arm/st/stih410-b2260.dts b/dts/upstream/src/arm/st/stih410-b2260.dts
index 240b6204000..736b1e059b0 100644
--- a/dts/upstream/src/arm/st/stih410-b2260.dts
+++ b/dts/upstream/src/arm/st/stih410-b2260.dts
@@ -206,5 +206,9 @@
 		sata1: sata@9b28000 {
 			status = "okay";
 		};
+
+		gpu: gpu@9f00000 {
+			status = "okay";
+		};
 	};
 };
diff --git a/dts/upstream/src/arm/st/stih410.dtsi b/dts/upstream/src/arm/st/stih410.dtsi
index a69231854f7..d56343f44fd 100644
--- a/dts/upstream/src/arm/st/stih410.dtsi
+++ b/dts/upstream/src/arm/st/stih410.dtsi
@@ -285,5 +285,39 @@
 			resets = <&softreset STIH407_LPM_SOFTRESET>;
 			hdmi-phandle = <&sti_hdmi>;
 		};
+
+		gpu: gpu@9f00000 {
+			compatible = "st,stih410-mali", "arm,mali-400";
+			reg = <0x9f00000 0x10000>;
+			/* LIMA driver needs 2 clocks, use the same for both */
+			clocks = <&clk_s_c0_flexgen CLK_ICN_GPU>,
+				 <&clk_s_c0_flexgen CLK_ICN_GPU>;
+			clock-names = "bus", "core";
+			assigned-clocks = <&clk_s_c0_flexgen CLK_ICN_GPU>;
+			assigned-clock-rates = <400000000>;
+			resets = <&softreset STIH407_GPU_SOFTRESET>;
+			interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "gp",
+					  "gpmmu",
+					  "pp0",
+					  "ppmmu0",
+					  "pp1",
+					  "ppmmu1",
+					  "pp2",
+					  "ppmmu2",
+					  "pp3",
+					  "ppmmu3";
+
+			status = "disabled";
+		};
 	};
 };
diff --git a/dts/upstream/src/arm/st/stm32mp131.dtsi b/dts/upstream/src/arm/st/stm32mp131.dtsi
index e1a764d269d..0019d12c3d3 100644
--- a/dts/upstream/src/arm/st/stm32mp131.dtsi
+++ b/dts/upstream/src/arm/st/stm32mp131.dtsi
@@ -261,6 +261,11 @@
 			dma-names = "up";
 			status = "disabled";
 
+			counter {
+				compatible = "st,stm32-timer-counter";
+				status = "disabled";
+			};
+
 			timer@5 {
 				compatible = "st,stm32h7-timer-trigger";
 				reg = <5>;
@@ -281,6 +286,11 @@
 			dma-names = "up";
 			status = "disabled";
 
+			counter {
+				compatible = "st,stm32-timer-counter";
+				status = "disabled";
+			};
+
 			timer@6 {
 				compatible = "st,stm32h7-timer-trigger";
 				reg = <6>;
@@ -1196,6 +1206,11 @@
 				access-controllers = <&etzpc 23>;
 				status = "disabled";
 
+				counter {
+					compatible = "st,stm32-timer-counter";
+					status = "disabled";
+				};
+
 				pwm {
 					compatible = "st,stm32-pwm";
 					#pwm-cells = <3>;
@@ -1221,6 +1236,11 @@
 				access-controllers = <&etzpc 24>;
 				status = "disabled";
 
+				counter {
+					compatible = "st,stm32-timer-counter";
+					status = "disabled";
+				};
+
 				pwm {
 					compatible = "st,stm32-pwm";
 					#pwm-cells = <3>;
@@ -1246,6 +1266,11 @@
 				access-controllers = <&etzpc 25>;
 				status = "disabled";
 
+				counter {
+					compatible = "st,stm32-timer-counter";
+					status = "disabled";
+				};
+
 				pwm {
 					compatible = "st,stm32-pwm";
 					#pwm-cells = <3>;
@@ -1276,6 +1301,11 @@
 				access-controllers = <&etzpc 26>;
 				status = "disabled";
 
+				counter {
+					compatible = "st,stm32-timer-counter";
+					status = "disabled";
+				};
+
 				pwm {
 					compatible = "st,stm32-pwm";
 					#pwm-cells = <3>;
@@ -1304,6 +1334,11 @@
 				access-controllers = <&etzpc 27>;
 				status = "disabled";
 
+				counter {
+					compatible = "st,stm32-timer-counter";
+					status = "disabled";
+				};
+
 				pwm {
 					compatible = "st,stm32-pwm";
 					#pwm-cells = <3>;
@@ -1332,6 +1367,11 @@
 				access-controllers = <&etzpc 28>;
 				status = "disabled";
 
+				counter {
+					compatible = "st,stm32-timer-counter";
+					status = "disabled";
+				};
+
 				pwm {
 					compatible = "st,stm32-pwm";
 					#pwm-cells = <3>;
diff --git a/dts/upstream/src/arm/st/stm32mp135f-dk.dts b/dts/upstream/src/arm/st/stm32mp135f-dk.dts
index 3a276589fef..19a32f7d4d7 100644
--- a/dts/upstream/src/arm/st/stm32mp135f-dk.dts
+++ b/dts/upstream/src/arm/st/stm32mp135f-dk.dts
@@ -440,6 +440,9 @@
 	/delete-property/dmas;
 	/delete-property/dma-names;
 	status = "disabled";
+	counter {
+		status = "okay";
+	};
 	pwm {
 		/* PWM output on pin 7 of the expansion connector (CN8.7) using TIM3_CH4 func */
 		pinctrl-0 = <&pwm3_pins_a>;
@@ -456,6 +459,9 @@
 	/delete-property/dmas;
 	/delete-property/dma-names;
 	status = "disabled";
+	counter {
+		status = "okay";
+	};
 	pwm {
 		/* PWM output on pin 31 of the expansion connector (CN8.31) using TIM4_CH2 func */
 		pinctrl-0 = <&pwm4_pins_a>;
@@ -472,6 +478,9 @@
 	/delete-property/dmas;
 	/delete-property/dma-names;
 	status = "disabled";
+	counter {
+		status = "okay";
+	};
 	pwm {
 		/* PWM output on pin 32 of the expansion connector (CN8.32) using TIM8_CH3 func */
 		pinctrl-0 = <&pwm8_pins_a>;
@@ -486,6 +495,9 @@
 
 &timers14 {
 	status = "disabled";
+	counter {
+		status = "okay";
+	};
 	pwm {
 		/* PWM output on pin 33 of the expansion connector (CN8.33) using TIM14_CH1 func */
 		pinctrl-0 = <&pwm14_pins_a>;
diff --git a/dts/upstream/src/arm/st/stm32mp13xx-dhcor-som.dtsi b/dts/upstream/src/arm/st/stm32mp13xx-dhcor-som.dtsi
index 5edbc790d1d..6236ce2a696 100644
--- a/dts/upstream/src/arm/st/stm32mp13xx-dhcor-som.dtsi
+++ b/dts/upstream/src/arm/st/stm32mp13xx-dhcor-som.dtsi
@@ -85,8 +85,8 @@
 
 			vddcpu: buck1 { /* VDD_CPU_1V2 */
 				regulator-name = "vddcpu";
-				regulator-min-microvolt = <1250000>;
-				regulator-max-microvolt = <1250000>;
+				regulator-min-microvolt = <1350000>;
+				regulator-max-microvolt = <1350000>;
 				regulator-always-on;
 				regulator-initial-mode = <0>;
 				regulator-over-current-protection;
@@ -201,17 +201,17 @@
 		pagesize = <64>;
 	};
 
-	eeprom0wl: eeprom@58 {
-		compatible = "st,24256e-wl";	/* ST M24256E WL page of 0x50 */
-		pagesize = <64>;
-		reg = <0x58>;
-	};
-
 	rv3032: rtc@51 {
 		compatible = "microcrystal,rv3032";
 		reg = <0x51>;
 		interrupts-extended = <&gpioi 0 IRQ_TYPE_EDGE_FALLING>;
 	};
+
+	eeprom0wl: eeprom@58 {
+		compatible = "st,24256e-wl";	/* ST M24256E WL page of 0x50 */
+		pagesize = <64>;
+		reg = <0x58>;
+	};
 };
 
 &iwdg2 {
diff --git a/dts/upstream/src/arm/st/stm32mp151.dtsi b/dts/upstream/src/arm/st/stm32mp151.dtsi
index b28dc90926b..b9a87fbe971 100644
--- a/dts/upstream/src/arm/st/stm32mp151.dtsi
+++ b/dts/upstream/src/arm/st/stm32mp151.dtsi
@@ -129,7 +129,7 @@
 			reg = <0x4c001000 0x400>;
 			st,proc-id = <0>;
 			interrupts-extended =
-				<&exti 61 1>,
+				<&exti 61 IRQ_TYPE_LEVEL_HIGH>,
 				<&intc GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-names = "rx", "tx";
 			clocks = <&rcc IPCC>;
@@ -578,6 +578,11 @@
 				access-controllers = <&etzpc 20>;
 				status = "disabled";
 
+				counter {
+					compatible = "st,stm32-timer-counter";
+					status = "disabled";
+				};
+
 				timer@5 {
 					compatible = "st,stm32h7-timer-trigger";
 					reg = <5>;
@@ -599,6 +604,11 @@
 				access-controllers = <&etzpc 21>;
 				status = "disabled";
 
+				counter {
+					compatible = "st,stm32-timer-counter";
+					status = "disabled";
+				};
+
 				timer@6 {
 					compatible = "st,stm32h7-timer-trigger";
 					reg = <6>;
@@ -618,6 +628,11 @@
 				access-controllers = <&etzpc 22>;
 				status = "disabled";
 
+				counter {
+					compatible = "st,stm32-timer-counter";
+					status = "disabled";
+				};
+
 				pwm {
 					compatible = "st,stm32-pwm";
 					#pwm-cells = <3>;
@@ -643,6 +658,11 @@
 				access-controllers = <&etzpc 23>;
 				status = "disabled";
 
+				counter {
+					compatible = "st,stm32-timer-counter";
+					status = "disabled";
+				};
+
 				pwm {
 					compatible = "st,stm32-pwm";
 					#pwm-cells = <3>;
@@ -668,6 +688,11 @@
 				access-controllers = <&etzpc 24>;
 				status = "disabled";
 
+				counter {
+					compatible = "st,stm32-timer-counter";
+					status = "disabled";
+				};
+
 				pwm {
 					compatible = "st,stm32-pwm";
 					#pwm-cells = <3>;
@@ -1116,6 +1141,11 @@
 				access-controllers = <&etzpc 54>;
 				status = "disabled";
 
+				counter {
+					compatible = "st,stm32-timer-counter";
+					status = "disabled";
+				};
+
 				pwm {
 					compatible = "st,stm32-pwm";
 					#pwm-cells = <3>;
@@ -1144,11 +1174,17 @@
 				access-controllers = <&etzpc 55>;
 				status = "disabled";
 
+				counter {
+					compatible = "st,stm32-timer-counter";
+					status = "disabled";
+				};
+
 				pwm {
 					compatible = "st,stm32-pwm";
 					#pwm-cells = <3>;
 					status = "disabled";
 				};
+
 				timer@15 {
 					compatible = "st,stm32h7-timer-trigger";
 					reg = <15>;
@@ -1171,6 +1207,11 @@
 				access-controllers = <&etzpc 56>;
 				status = "disabled";
 
+				counter {
+					compatible = "st,stm32-timer-counter";
+					status = "disabled";
+				};
+
 				pwm {
 					compatible = "st,stm32-pwm";
 					#pwm-cells = <3>;
diff --git a/dts/upstream/src/arm/st/stm32mp153c-lxa-tac-gen3.dts b/dts/upstream/src/arm/st/stm32mp153c-lxa-tac-gen3.dts
new file mode 100644
index 00000000000..a40b0eae8da
--- /dev/null
+++ b/dts/upstream/src/arm/st/stm32mp153c-lxa-tac-gen3.dts
@@ -0,0 +1,267 @@
+// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
+/*
+ * Copyright (C) 2020 STMicroelectronics - All Rights Reserved
+ * Copyright (C) 2021 Rouven Czerwinski, Pengutronix
+ * Copyright (C) 2023, 2024 Leonard Göhrs, Pengutronix
+ */
+
+/dts-v1/;
+
+#include "stm32mp153.dtsi"
+#include "stm32mp15xc-lxa-tac.dtsi"
+
+/ {
+	model = "Linux Automation Test Automation Controller (TAC) Gen 3";
+	compatible = "lxa,stm32mp153c-tac-gen3", "oct,stm32mp153x-osd32", "st,stm32mp153";
+
+	backlight: backlight {
+		compatible = "pwm-backlight";
+		power-supply = <&v3v3>;
+
+		brightness-levels = <0 31 63 95 127 159 191 223 255>;
+		default-brightness-level = <7>;
+		pwms = <&led_pwm 3 1000000 0>;
+	};
+
+	reg_iobus_12v: regulator-iobus-12v {
+		compatible = "regulator-fixed";
+		vin-supply = <&reg_12v>;
+		gpio = <&gpioh 13 GPIO_ACTIVE_LOW>;
+		regulator-max-microvolt = <12000000>;
+		regulator-min-microvolt = <12000000>;
+		regulator-name = "12V_IOBUS";
+	};
+
+	led-controller-1 {
+		compatible = "pwm-leds-multicolor";
+
+		multi-led {
+			color = <LED_COLOR_ID_RGB>;
+			function = LED_FUNCTION_STATUS;
+			max-brightness = <65535>;
+
+			led-red {
+				active-low;
+				color = <LED_COLOR_ID_RED>;
+				pwms = <&led_pwm 0 1000000 0>;
+			};
+
+			led-green {
+				active-low;
+				color = <LED_COLOR_ID_GREEN>;
+				pwms = <&led_pwm 2 1000000 0>;
+			};
+
+			led-blue {
+				active-low;
+				color = <LED_COLOR_ID_BLUE>;
+				pwms = <&led_pwm 1 1000000 0>;
+			};
+		};
+	};
+
+	led-controller-2 {
+		compatible = "gpio-leds";
+
+		led-5 {
+			label = "tac:green:iobus";
+			gpios = <&gpiog 1 GPIO_ACTIVE_HIGH>;
+		};
+
+		led-6 {
+			label = "tac:green:can";
+			gpios = <&gpiof 3 GPIO_ACTIVE_HIGH>;
+		};
+
+		led-7 {
+			label = "tac:green:out0";
+			gpios = <&gpiob 8 GPIO_ACTIVE_HIGH>;
+		};
+
+		led-8 {
+			label = "tac:green:out1";
+			gpios = <&gpiog 3 GPIO_ACTIVE_HIGH>;
+		};
+
+		led-9 {
+			label = "tac:green:uarttx";
+			gpios = <&gpiod 3 GPIO_ACTIVE_HIGH>;
+		};
+
+		led-10 {
+			label = "tac:green:uartrx";
+			gpios = <&gpiof 6 GPIO_ACTIVE_HIGH>;
+		};
+
+		led-11 {
+			label = "tac:green:usbh1";
+			gpios = <&gpioc 8 GPIO_ACTIVE_HIGH>;
+		};
+
+		led-12 {
+			label = "tac:green:usbh2";
+			gpios = <&gpiod 6 GPIO_ACTIVE_HIGH>;
+		};
+
+		led-13 {
+			label = "tac:green:usbh3";
+			gpios = <&gpiob 9 GPIO_ACTIVE_HIGH>;
+		};
+
+		led-14 {
+			label = "tac:green:usbg";
+			gpios = <&gpiod 14 GPIO_ACTIVE_HIGH>;
+			linux,default-trigger = "usb-gadget";
+		};
+
+		led-15 {
+			label = "tac:green:dutpwr";
+			gpios = <&gpioa 15 GPIO_ACTIVE_HIGH>;
+		};
+	};
+};
+
+&adc {
+	pinctrl-names = "default";
+	pinctrl-0 = <&board_adc1_ain_pins>;
+	vdd-supply = <&vdd>;
+	vdda-supply = <&vdda>;
+	vref-supply = <&vrefbuf>;
+	status = "okay";
+
+	adc1: adc@0 {
+		st,adc-channels = <2 5 9 10 13 14 15 18>;
+		st,min-sample-time-nsecs = <5000>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "okay";
+
+		channel@2 {
+			reg = <2>;
+			label = "OUT_0_FB";
+		};
+
+		channel@5 {
+			reg = <5>;
+			label = "IOBUS_CURR_FB";
+		};
+
+		channel@9 {
+			reg = <9>;
+			label = "IOBUS_VOLT_FB";
+		};
+
+		channel@10 {
+			reg = <10>;
+			label = "OUT_1_FB";
+		};
+
+		channel@13 {
+			reg = <13>;
+			label = "HOST_CURR_FB";
+		};
+
+		channel@14 {
+			reg = <14>;
+			label = "HOST_3_CURR_FB";
+		};
+
+		channel@15 {
+			reg = <15>;
+			label = "HOST_1_CURR_FB";
+		};
+
+		channel@18 {
+			reg = <18>;
+			label = "HOST_2_CURR_FB";
+		};
+	};
+
+	adc2: adc@100 {
+		st,adc-channels = <12>;
+		st,min-sample-time-nsecs = <500000>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "okay";
+
+		channel@12 {
+			reg = <12>;
+			label = "TEMP_INTERNAL";
+		};
+	};
+};
+
+&gpioa {
+	gpio-line-names = "", "", "", "", "",              /*  0 */
+	"ETH_GPIO1", "ETH_INT", "", "", "",                /*  5 */
+	"", "", "", "BOOTROM_LED", "ETH_LAB_LEDRP",        /* 10 */
+	"";                                                /* 15 */
+};
+
+&gpioc {
+	gpio-line-names = "", "DUT_PWR_DISCH", "", "", "", /*  0 */
+	"", "", "", "", "",                                /*  5 */
+	"", "";                                            /* 10 */
+};
+
+&gpioe {
+	gpio-line-names = "TP35", "", "", "", "CAN_1_120R", /*  0 */
+	"", "", "USER_BTN2", "DUT_PWR_EN", "UART_TX_EN",    /*  5 */
+	"UART_RX_EN", "TP24", "", "TP25", "TP26",           /* 10 */
+	"TP27";                                             /* 15 */
+};
+
+&gpiog {
+	gpio-line-names = "ETH_RESET", "", "", "", "",               /*  0 */
+	"IOBUS_FLT_FB", "", "USER_LED2", "ETH1_PPS_A", "CAN_0_120R", /*  5 */
+	"POWER_ADC_RESET", "", "", "", "",                           /* 10 */
+	"";                                                          /* 15 */
+};
+
+&m_can2 {
+	termination-gpios = <&gpioe 4 GPIO_ACTIVE_HIGH>;
+	termination-ohms = <120>;
+};
+
+&pinctrl {
+	board_adc1_ain_pins: board-adc1-ain-0 {
+		pins {
+			pinmux = <STM32_PINMUX('F', 11, ANALOG)>, /* ADC1_INP2 */
+				 <STM32_PINMUX('B', 1, ANALOG)>, /* ADC1_INP5 */
+				 <STM32_PINMUX('B', 0, ANALOG)>, /* ADC1_INP9 */
+				 <STM32_PINMUX('C', 0, ANALOG)>, /* ADC1_INP10 */
+				 <STM32_PINMUX('C', 3, ANALOG)>, /* ADC1_INP13 */
+				 <STM32_PINMUX('A', 2, ANALOG)>, /* ADC1_INP14 */
+				 <STM32_PINMUX('A', 3, ANALOG)>, /* ADC1_INP15 */
+				 <STM32_PINMUX('A', 4, ANALOG)>; /* ADC1_INP18 */
+		};
+	};
+};
+
+&spi2 {
+	adc@0 {
+		compatible = "ti,lmp92064";
+		reg = <0>;
+
+		reset-gpios = <&gpiog 10 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+		shunt-resistor-micro-ohms = <15000>;
+		spi-max-frequency = <5000000>;
+		vdd-supply = <&reg_pb_3v3>;
+		vdig-supply = <&reg_pb_3v3>;
+	};
+};
+
+&timers8 {
+	/* spare dmas for other usage */
+	/delete-property/dmas;
+	/delete-property/dma-names;
+
+	status = "okay";
+
+	led_pwm: pwm {
+		pinctrl-names = "default", "sleep";
+		pinctrl-0 = <&pwm8_pins_b>;
+		pinctrl-1 = <&pwm8_sleep_pins_b>;
+		status = "okay";
+	};
+};
diff --git a/dts/upstream/src/arm/st/stm32mp157c-ev1.dts b/dts/upstream/src/arm/st/stm32mp157c-ev1.dts
index 9eb9a1bf4f2..8f99c30f1af 100644
--- a/dts/upstream/src/arm/st/stm32mp157c-ev1.dts
+++ b/dts/upstream/src/arm/st/stm32mp157c-ev1.dts
@@ -306,6 +306,9 @@
 	/delete-property/dmas;
 	/delete-property/dma-names;
 	status = "disabled";
+	counter {
+		status = "okay";
+	};
 	pwm {
 		pinctrl-0 = <&pwm2_pins_a>;
 		pinctrl-1 = <&pwm2_sleep_pins_a>;
@@ -321,6 +324,9 @@
 	/delete-property/dmas;
 	/delete-property/dma-names;
 	status = "disabled";
+	counter {
+		status = "okay";
+	};
 	pwm {
 		pinctrl-0 = <&pwm8_pins_a>;
 		pinctrl-1 = <&pwm8_sleep_pins_a>;
@@ -336,6 +342,9 @@
 	/delete-property/dmas;
 	/delete-property/dma-names;
 	status = "disabled";
+	counter {
+		status = "okay";
+	};
 	pwm {
 		pinctrl-0 = <&pwm12_pins_a>;
 		pinctrl-1 = <&pwm12_sleep_pins_a>;
diff --git a/dts/upstream/src/arm/st/stm32mp157c-lxa-tac-gen1.dts b/dts/upstream/src/arm/st/stm32mp157c-lxa-tac-gen1.dts
index 81f254fb88b..e72e42eb0eb 100644
--- a/dts/upstream/src/arm/st/stm32mp157c-lxa-tac-gen1.dts
+++ b/dts/upstream/src/arm/st/stm32mp157c-lxa-tac-gen1.dts
@@ -35,6 +35,76 @@
 	};
 };
 
+&adc {
+	pinctrl-names = "default";
+	pinctrl-0 = <&adc1_ain_pins_a>;
+	vdd-supply = <&vdd>;
+	vdda-supply = <&vdda>;
+	vref-supply = <&vrefbuf>;
+	status = "okay";
+
+	adc1: adc@0 {
+		st,adc-channels = <0 1 2 5 9 10 13 15>;
+		st,min-sample-time-nsecs = <5000>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "okay";
+
+		channel@0 {
+			reg = <0>;
+			label = "HOST_2_CURR_FB";
+		};
+
+		channel@1 {
+			reg = <1>;
+			label = "HOST_3_CURR_FB";
+		};
+
+		channel@2 {
+			reg = <2>;
+			label = "OUT_0_FB";
+		};
+
+		channel@5 {
+			reg = <5>;
+			label = "IOBUS_CURR_FB";
+		};
+
+		channel@9 {
+			reg = <9>;
+			label = "IOBUS_VOLT_FB";
+		};
+
+		channel@10 {
+			reg = <10>;
+			label = "OUT_1_FB";
+		};
+
+		channel@13 {
+			reg = <13>;
+			label = "HOST_CURR_FB";
+		};
+
+		channel@15 {
+			reg = <15>;
+			label = "HOST_1_CURR_FB";
+		};
+	};
+
+	adc2: adc@100 {
+		st,adc-channels = <12>;
+		st,min-sample-time-nsecs = <500000>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "okay";
+
+		channel@12 {
+			reg = <12>;
+			label = "TEMP_INTERNAL";
+		};
+	};
+};
+
 &gpioa {
 	gpio-line-names = "", "", "STACK_CS2", "", "STACK_CS3", /*  0 */
 	"ETH_GPIO1", "ETH_INT", "", "", "",                     /*  5 */
@@ -48,6 +118,20 @@
 	"", "";                                        /* 10 */
 };
 
+&gpioe {
+	gpio-line-names = "TP35", "", "", "", "CAN_1_120R", /*  0 */
+	"", "", "USER_BTN2", "TP48", "UART_TX_EN",          /*  5 */
+	"UART_RX_EN", "TP24", "", "TP25", "TP26",           /* 10 */
+	"TP27";                                             /* 15 */
+};
+
+&gpiog {
+	gpio-line-names = "ETH_RESET", "", "", "", "",               /*  0 */
+	"IOBUS_FLT_FB", "", "USER_LED2", "ETH1_PPS_A", "CAN_0_120R", /*  5 */
+	"TP49", "", "", "", "",                                      /* 10 */
+	"";                                                          /* 15 */
+};
+
 &gpu {
 	status = "disabled";
 };
diff --git a/dts/upstream/src/arm/st/stm32mp157c-lxa-tac-gen2.dts b/dts/upstream/src/arm/st/stm32mp157c-lxa-tac-gen2.dts
index 4cc17703166..2ae281725a4 100644
--- a/dts/upstream/src/arm/st/stm32mp157c-lxa-tac-gen2.dts
+++ b/dts/upstream/src/arm/st/stm32mp157c-lxa-tac-gen2.dts
@@ -121,6 +121,76 @@
 	};
 };
 
+&adc {
+	pinctrl-names = "default";
+	pinctrl-0 = <&adc1_ain_pins_a>;
+	vdd-supply = <&vdd>;
+	vdda-supply = <&vdda>;
+	vref-supply = <&vrefbuf>;
+	status = "okay";
+
+	adc1: adc@0 {
+		st,adc-channels = <0 1 2 5 9 10 13 15>;
+		st,min-sample-time-nsecs = <5000>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "okay";
+
+		channel@0 {
+			reg = <0>;
+			label = "HOST_2_CURR_FB";
+		};
+
+		channel@1 {
+			reg = <1>;
+			label = "HOST_3_CURR_FB";
+		};
+
+		channel@2 {
+			reg = <2>;
+			label = "OUT_0_FB";
+		};
+
+		channel@5 {
+			reg = <5>;
+			label = "IOBUS_CURR_FB";
+		};
+
+		channel@9 {
+			reg = <9>;
+			label = "IOBUS_VOLT_FB";
+		};
+
+		channel@10 {
+			reg = <10>;
+			label = "OUT_1_FB";
+		};
+
+		channel@13 {
+			reg = <13>;
+			label = "HOST_CURR_FB";
+		};
+
+		channel@15 {
+			reg = <15>;
+			label = "HOST_1_CURR_FB";
+		};
+	};
+
+	adc2: adc@100 {
+		st,adc-channels = <12>;
+		st,min-sample-time-nsecs = <500000>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "okay";
+
+		channel@12 {
+			reg = <12>;
+			label = "TEMP_INTERNAL";
+		};
+	};
+};
+
 &gpioa {
 	gpio-line-names = "", "", "DUT_PWR_EN", "", "STACK_CS3", /*  0 */
 	"ETH_GPIO1", "ETH_INT", "", "", "",                      /*  5 */
@@ -134,6 +204,20 @@
 	"", "";                                            /* 10 */
 };
 
+&gpioe {
+	gpio-line-names = "TP35", "", "", "", "CAN_1_120R", /*  0 */
+	"", "", "USER_BTN2", "TP48", "UART_TX_EN",          /*  5 */
+	"UART_RX_EN", "TP24", "", "TP25", "TP26",           /* 10 */
+	"TP27";                                             /* 15 */
+};
+
+&gpiog {
+	gpio-line-names = "ETH_RESET", "", "", "", "",               /*  0 */
+	"IOBUS_FLT_FB", "", "USER_LED2", "ETH1_PPS_A", "CAN_0_120R", /*  5 */
+	"TP49", "", "", "", "",                                      /* 10 */
+	"";                                                          /* 15 */
+};
+
 &gpu {
 	status = "disabled";
 };
diff --git a/dts/upstream/src/arm/st/stm32mp15xc-lxa-tac.dtsi b/dts/upstream/src/arm/st/stm32mp15xc-lxa-tac.dtsi
index c87fd96cbd9..be0c355d310 100644
--- a/dts/upstream/src/arm/st/stm32mp15xc-lxa-tac.dtsi
+++ b/dts/upstream/src/arm/st/stm32mp15xc-lxa-tac.dtsi
@@ -16,12 +16,20 @@
 
 / {
 	aliases {
+		can0 = &m_can1;
+		can1 = &m_can2;
 		ethernet0 = &ethernet0;
 		ethernet1 = &port_uplink;
 		ethernet2 = &port_dut;
+		i2c0 = &i2c1;
+		i2c1 = &i2c4;
+		i2c2 = &i2c5;
 		mmc1 = &sdmmc2;
 		serial0 = &uart4;
 		serial1 = &usart3;
+		spi0 = &spi2;
+		spi1 = &spi4;
+		spi2 = &spi5;
 	};
 
 	chosen {
@@ -142,76 +150,6 @@
 baseboard_eeprom: &sip_eeprom {
 };
 
-&adc {
-	pinctrl-names = "default";
-	pinctrl-0 = <&adc1_ain_pins_a>;
-	vdd-supply = <&vdd>;
-	vdda-supply = <&vdda>;
-	vref-supply = <&vrefbuf>;
-	status = "okay";
-
-	adc1: adc@0 {
-		st,adc-channels = <0 1 2 5 9 10 13 15>;
-		st,min-sample-time-nsecs = <5000>;
-		#address-cells = <1>;
-		#size-cells = <0>;
-		status = "okay";
-
-		channel@0 {
-			reg = <0>;
-			label = "HOST_2_CURR_FB";
-		};
-
-		channel@1 {
-			reg = <1>;
-			label = "HOST_3_CURR_FB";
-		};
-
-		channel@2 {
-			reg = <2>;
-			label = "OUT_0_FB";
-		};
-
-		channel@5 {
-			reg = <5>;
-			label = "IOBUS_CURR_FB";
-		};
-
-		channel@9 {
-			reg = <9>;
-			label = "IOBUS_VOLT_FB";
-		};
-
-		channel@10 {
-			reg = <10>;
-			label = "OUT_1_FB";
-		};
-
-		channel@13 {
-			reg = <13>;
-			label = "HOST_CURR_FB";
-		};
-
-		channel@15 {
-			reg = <15>;
-			label = "HOST_1_CURR_FB";
-		};
-	};
-
-	adc2: adc@100 {
-		st,adc-channels = <12>;
-		st,min-sample-time-nsecs = <500000>;
-		#address-cells = <1>;
-		#size-cells = <0>;
-		status = "okay";
-
-		channel@12 {
-			reg = <12>;
-			label = "TEMP_INTERNAL";
-		};
-	};
-};
-
 &crc1 {
 	status = "okay";
 };
@@ -265,13 +203,6 @@ baseboard_eeprom: &sip_eeprom {
 	"ETH_LAB_LEDRN";                          /* 15 */
 };
 
-&gpioe {
-	gpio-line-names = "TP35", "", "", "", "CAN_1_120R", /*  0 */
-	"", "", "USER_BTN2", "TP48", "UART_TX_EN",          /*  5 */
-	"UART_RX_EN", "TP24", "", "TP25", "TP26",           /* 10 */
-	"TP27";                                             /* 15 */
-};
-
 &gpiof {
 	gpio-line-names = "TP36", "TP37", "", "", "OLED_CS", /*  0 */
 	"", "", "", "", "",                                  /*  5 */
@@ -279,13 +210,6 @@ baseboard_eeprom: &sip_eeprom {
 	"";                                                  /* 15 */
 };
 
-&gpiog {
-	gpio-line-names = "ETH_RESET", "", "", "", "",               /*  0 */
-	"IOBUS_FLT_FB", "", "USER_LED2", "ETH1_PPS_A", "CAN_0_120R", /*  5 */
-	"TP49", "", "", "", "",                                      /* 10 */
-	"";                                                          /* 15 */
-};
-
 &gpioh {
 	gpio-line-names = "", "", "OUT_1", "OUT_0", "OLED_RESET", /*  0 */
 	"", "", "", "", "",                                       /*  5 */
@@ -379,10 +303,6 @@ baseboard_eeprom: &sip_eeprom {
 	};
 };
 
-&rtc {
-	status = "okay";
-};
-
 &sdmmc2 {
 	pinctrl-names = "default", "opendrain", "sleep";
 	pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_b>;
@@ -576,6 +496,10 @@ baseboard_eeprom: &sip_eeprom {
 	vusb_d-supply = <&vdd_usb>;
 	vusb_a-supply = <&reg18>;
 
+	g-rx-fifo-size = <512>;
+	g-np-tx-fifo-size = <32>;
+	g-tx-fifo-size = <128 128 64 16 16 16 16 16>;
+
 	dr_mode = "peripheral";
 
 	status = "okay";
diff --git a/dts/upstream/src/arm/st/stm32mp15xx-dhcom-drc02.dtsi b/dts/upstream/src/arm/st/stm32mp15xx-dhcom-drc02.dtsi
index bb4f8a0b937..abe2dfe7063 100644
--- a/dts/upstream/src/arm/st/stm32mp15xx-dhcom-drc02.dtsi
+++ b/dts/upstream/src/arm/st/stm32mp15xx-dhcom-drc02.dtsi
@@ -6,18 +6,6 @@
 #include <dt-bindings/input/input.h>
 #include <dt-bindings/pwm/pwm.h>
 
-/ {
-	aliases {
-		serial0 = &uart4;
-		serial1 = &usart3;
-		serial2 = &uart8;
-	};
-
-	chosen {
-		stdout-path = "serial0:115200n8";
-	};
-};
-
 &adc {
 	status = "disabled";
 };
diff --git a/dts/upstream/src/arm/st/stm32mp15xx-dhcom-pdk2.dtsi b/dts/upstream/src/arm/st/stm32mp15xx-dhcom-pdk2.dtsi
index 171d7c7658f..0fb4e55843b 100644
--- a/dts/upstream/src/arm/st/stm32mp15xx-dhcom-pdk2.dtsi
+++ b/dts/upstream/src/arm/st/stm32mp15xx-dhcom-pdk2.dtsi
@@ -7,16 +7,6 @@
 #include <dt-bindings/pwm/pwm.h>
 
 / {
-	aliases {
-		serial0 = &uart4;
-		serial1 = &usart3;
-		serial2 = &uart8;
-	};
-
-	chosen {
-		stdout-path = "serial0:115200n8";
-	};
-
 	clk_ext_audio_codec: clock-codec {
 		compatible = "fixed-clock";
 		#clock-cells = <0>;
diff --git a/dts/upstream/src/arm/st/stm32mp15xx-dhcom-picoitx.dtsi b/dts/upstream/src/arm/st/stm32mp15xx-dhcom-picoitx.dtsi
index b5bc53accd6..01c693cc034 100644
--- a/dts/upstream/src/arm/st/stm32mp15xx-dhcom-picoitx.dtsi
+++ b/dts/upstream/src/arm/st/stm32mp15xx-dhcom-picoitx.dtsi
@@ -7,16 +7,6 @@
 #include <dt-bindings/pwm/pwm.h>
 
 / {
-	aliases {
-		serial0 = &uart4;
-		serial1 = &usart3;
-		serial2 = &uart8;
-	};
-
-	chosen {
-		stdout-path = "serial0:115200n8";
-	};
-
 	led {
 		compatible = "gpio-leds";
 
diff --git a/dts/upstream/src/arm/st/stm32mp15xx-dhcom-som.dtsi b/dts/upstream/src/arm/st/stm32mp15xx-dhcom-som.dtsi
index 74a11ccc533..142d4a8731f 100644
--- a/dts/upstream/src/arm/st/stm32mp15xx-dhcom-som.dtsi
+++ b/dts/upstream/src/arm/st/stm32mp15xx-dhcom-som.dtsi
@@ -14,6 +14,13 @@
 		ethernet1 = &ksz8851;
 		rtc0 = &hwrtc;
 		rtc1 = &rtc;
+		serial0 = &uart4;
+		serial1 = &uart8;
+		serial2 = &usart3;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
 	};
 
 	memory@c0000000 {
diff --git a/dts/upstream/src/arm/st/stm32mp15xx-dkx.dtsi b/dts/upstream/src/arm/st/stm32mp15xx-dkx.dtsi
index f7634c51efb..a5511b1f0ce 100644
--- a/dts/upstream/src/arm/st/stm32mp15xx-dkx.dtsi
+++ b/dts/upstream/src/arm/st/stm32mp15xx-dkx.dtsi
@@ -570,6 +570,9 @@
 	/delete-property/dmas;
 	/delete-property/dma-names;
 	status = "disabled";
+	counter {
+		status = "okay";
+	};
 	pwm {
 		pinctrl-0 = <&pwm1_pins_a>;
 		pinctrl-1 = <&pwm1_sleep_pins_a>;
@@ -585,6 +588,9 @@
 	/delete-property/dmas;
 	/delete-property/dma-names;
 	status = "disabled";
+	counter {
+		status = "okay";
+	};
 	pwm {
 		pinctrl-0 = <&pwm3_pins_a>;
 		pinctrl-1 = <&pwm3_sleep_pins_a>;
@@ -600,6 +606,9 @@
 	/delete-property/dmas;
 	/delete-property/dma-names;
 	status = "disabled";
+	counter {
+		status = "okay";
+	};
 	pwm {
 		pinctrl-0 = <&pwm4_pins_a &pwm4_pins_b>;
 		pinctrl-1 = <&pwm4_sleep_pins_a &pwm4_sleep_pins_b>;
@@ -615,6 +624,9 @@
 	/delete-property/dmas;
 	/delete-property/dma-names;
 	status = "disabled";
+	counter {
+		status = "okay";
+	};
 	pwm {
 		pinctrl-0 = <&pwm5_pins_a>;
 		pinctrl-1 = <&pwm5_sleep_pins_a>;
@@ -630,6 +642,9 @@
 	/delete-property/dmas;
 	/delete-property/dma-names;
 	status = "disabled";
+	counter {
+		status = "okay";
+	};
 	timer@5 {
 		status = "okay";
 	};
@@ -639,6 +654,9 @@
 	/delete-property/dmas;
 	/delete-property/dma-names;
 	status = "disabled";
+	counter {
+		status = "okay";
+	};
 	pwm {
 		pinctrl-0 = <&pwm12_pins_a>;
 		pinctrl-1 = <&pwm12_sleep_pins_a>;
diff --git a/dts/upstream/src/arm/ti/omap/am437x-l4.dtsi b/dts/upstream/src/arm/ti/omap/am437x-l4.dtsi
index 824b9415ebb..fd4634f8c62 100644
--- a/dts/upstream/src/arm/ti/omap/am437x-l4.dtsi
+++ b/dts/upstream/src/arm/ti/omap/am437x-l4.dtsi
@@ -180,8 +180,7 @@
 			      <0x9058 0x4>;
 			reg-names = "rev", "sysc", "syss";
 			ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
-					 SYSC_OMAP2_SOFTRESET |
-					 SYSC_OMAP2_AUTOIDLE)>;
+					 SYSC_OMAP2_SOFTRESET)>;
 			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 					<SYSC_IDLE_NO>,
 					<SYSC_IDLE_SMART>,
@@ -698,8 +697,7 @@
 			      <0x22058 0x4>;
 			reg-names = "rev", "sysc", "syss";
 			ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
-					 SYSC_OMAP2_SOFTRESET |
-					 SYSC_OMAP2_AUTOIDLE)>;
+					 SYSC_OMAP2_SOFTRESET)>;
 			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 					<SYSC_IDLE_NO>,
 					<SYSC_IDLE_SMART>,
@@ -726,8 +724,7 @@
 			      <0x24058 0x4>;
 			reg-names = "rev", "sysc", "syss";
 			ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
-					 SYSC_OMAP2_SOFTRESET |
-					 SYSC_OMAP2_AUTOIDLE)>;
+					 SYSC_OMAP2_SOFTRESET)>;
 			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 					<SYSC_IDLE_NO>,
 					<SYSC_IDLE_SMART>,
@@ -1385,8 +1382,7 @@
 			      <0xa6058 0x4>;
 			reg-names = "rev", "sysc", "syss";
 			ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
-					 SYSC_OMAP2_SOFTRESET |
-					 SYSC_OMAP2_AUTOIDLE)>;
+					 SYSC_OMAP2_SOFTRESET)>;
 			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 					<SYSC_IDLE_NO>,
 					<SYSC_IDLE_SMART>,
@@ -1413,8 +1409,7 @@
 			      <0xa8058 0x4>;
 			reg-names = "rev", "sysc", "syss";
 			ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
-					 SYSC_OMAP2_SOFTRESET |
-					 SYSC_OMAP2_AUTOIDLE)>;
+					 SYSC_OMAP2_SOFTRESET)>;
 			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 					<SYSC_IDLE_NO>,
 					<SYSC_IDLE_SMART>,
@@ -1441,8 +1436,7 @@
 			      <0xaa058 0x4>;
 			reg-names = "rev", "sysc", "syss";
 			ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
-					 SYSC_OMAP2_SOFTRESET |
-					 SYSC_OMAP2_AUTOIDLE)>;
+					 SYSC_OMAP2_SOFTRESET)>;
 			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 					<SYSC_IDLE_NO>,
 					<SYSC_IDLE_SMART>,
diff --git a/dts/upstream/src/arm/ti/omap/dra7-l4.dtsi b/dts/upstream/src/arm/ti/omap/dra7-l4.dtsi
index 6e67d99832a..ba7fdaae9c6 100644
--- a/dts/upstream/src/arm/ti/omap/dra7-l4.dtsi
+++ b/dts/upstream/src/arm/ti/omap/dra7-l4.dtsi
@@ -12,6 +12,7 @@
 	ranges = <0x00000000 0x4a000000 0x100000>,	/* segment 0 */
 		 <0x00100000 0x4a100000 0x100000>,	/* segment 1 */
 		 <0x00200000 0x4a200000 0x100000>;	/* segment 2 */
+	dma-ranges;
 
 	segment@0 {					/* 0x4a000000 */
 		compatible = "simple-pm-bus";
@@ -557,6 +558,7 @@
 			 <0x0007e000 0x0017e000 0x001000>,	/* ap 124 */
 			 <0x00059000 0x00159000 0x001000>,	/* ap 125 */
 			 <0x0005a000 0x0015a000 0x001000>;	/* ap 126 */
+		dma-ranges;
 
 		target-module@2000 {			/* 0x4a102000, ap 27 3c.0 */
 			compatible = "ti,sysc";
diff --git a/dts/upstream/src/arm/ti/omap/omap3-gta04.dtsi b/dts/upstream/src/arm/ti/omap/omap3-gta04.dtsi
index 2ee3ddd6402..1b18ed8c1f7 100644
--- a/dts/upstream/src/arm/ti/omap/omap3-gta04.dtsi
+++ b/dts/upstream/src/arm/ti/omap/omap3-gta04.dtsi
@@ -446,6 +446,7 @@
 	pinctrl-names = "default";
 	pinctrl-0 = <
 			&hsusb2_2_pins
+			&mcspi3hog_pins
 	>;
 
 	hsusb2_2_pins: hsusb2-2-pins {
@@ -459,6 +460,15 @@
 		>;
 	};
 
+	mcspi3hog_pins: mcspi3hog-pins {
+		pinctrl-single,pins = <
+			OMAP3630_CORE2_IOPAD(0x25dc, PIN_OUTPUT_PULLDOWN | MUX_MODE4)	/* etk_d0 */
+			OMAP3630_CORE2_IOPAD(0x25de, PIN_OUTPUT_PULLDOWN | MUX_MODE4)	/* etk_d1 */
+			OMAP3630_CORE2_IOPAD(0x25e0, PIN_OUTPUT_PULLDOWN | MUX_MODE4)	/* etk_d2 */
+			OMAP3630_CORE2_IOPAD(0x25e2, PIN_OUTPUT_PULLDOWN | MUX_MODE4)	/* etk_d3 */
+		>;
+	};
+
 	spi_gpio_pins: spi-gpio-pinmux-pins {
 		pinctrl-single,pins = <
 			OMAP3630_CORE2_IOPAD(0x25d8, PIN_OUTPUT | MUX_MODE4) /* clk */
@@ -591,8 +601,10 @@
 		interrupts = <0 IRQ_TYPE_EDGE_FALLING>; /* GPIO_160 */
 		gpios = <&gpio6 0 GPIO_ACTIVE_LOW>;	/* GPIO_160 */
 		ti,x-plate-ohms = <600>;
-		touchscreen-size-x = <480>;
-		touchscreen-size-y = <640>;
+		touchscreen-size-x = <0xf00>;
+		touchscreen-size-y = <0xf00>;
+		touchscreen-min-x = <0x100>;
+		touchscreen-min-y = <0x100>;
 		touchscreen-max-pressure = <1000>;
 		touchscreen-fuzz-x = <3>;
 		touchscreen-fuzz-y = <8>;
diff --git a/dts/upstream/src/arm64/airoha/en7581.dtsi b/dts/upstream/src/arm64/airoha/en7581.dtsi
index 55eb1762fb1..f584409e72c 100644
--- a/dts/upstream/src/arm64/airoha/en7581.dtsi
+++ b/dts/upstream/src/arm64/airoha/en7581.dtsi
@@ -2,6 +2,7 @@
 
 #include <dt-bindings/interrupt-controller/irq.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/en7523-clk.h>
 
 / {
 	interrupt-parent = <&gic>;
@@ -142,6 +143,13 @@
 			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
 		};
 
+		scuclk: clock-controller@1fa20000 {
+			compatible = "airoha,en7581-scu";
+			reg = <0x0 0x1fb00000 0x0 0x970>;
+			#clock-cells = <1>;
+			#reset-cells = <1>;
+		};
+
 		uart1: serial@1fbf0000 {
 			compatible = "ns16550";
 			reg = <0x0 0x1fbf0000 0x0 0x30>;
diff --git a/dts/upstream/src/arm64/allwinner/sun50i-a100.dtsi b/dts/upstream/src/arm64/allwinner/sun50i-a100.dtsi
index 29ac7716c7a..a24adba201a 100644
--- a/dts/upstream/src/arm64/allwinner/sun50i-a100.dtsi
+++ b/dts/upstream/src/arm64/allwinner/sun50i-a100.dtsi
@@ -101,6 +101,39 @@
 		#size-cells = <1>;
 		ranges = <0 0 0 0x3fffffff>;
 
+		syscon: syscon@3000000 {
+			compatible = "allwinner,sun50i-a100-system-control",
+				     "allwinner,sun50i-a64-system-control";
+			reg = <0x03000000 0x1000>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges;
+
+			sram_a1: sram@20000 {
+				compatible = "mmio-sram";
+				reg = <0x00020000 0x4000>;
+				#address-cells = <1>;
+				#size-cells = <1>;
+				ranges = <0 0x00020000 0x4000>;
+			};
+
+			sram_c: sram@24000 {
+				compatible = "mmio-sram";
+				reg = <0x024000 0x21000>;
+				#address-cells = <1>;
+				#size-cells = <1>;
+				ranges = <0 0x024000 0x21000>;
+			};
+
+			sram_a2: sram@100000 {
+				compatible = "mmio-sram";
+				reg = <0x0100000 0x14000>;
+				#address-cells = <1>;
+				#size-cells = <1>;
+				ranges = <0 0x0100000 0x14000>;
+			};
+		};
+
 		ccu: clock@3001000 {
 			compatible = "allwinner,sun50i-a100-ccu";
 			reg = <0x03001000 0x1000>;
diff --git a/dts/upstream/src/arm64/allwinner/sun50i-a64-pinebook.dts b/dts/upstream/src/arm64/allwinner/sun50i-a64-pinebook.dts
index 379c2c8466f..86d44349e09 100644
--- a/dts/upstream/src/arm64/allwinner/sun50i-a64-pinebook.dts
+++ b/dts/upstream/src/arm64/allwinner/sun50i-a64-pinebook.dts
@@ -390,6 +390,8 @@
 &tcon0 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&lcd_rgb666_pins>;
+	assigned-clocks = <&ccu CLK_TCON0>;
+	assigned-clock-parents = <&ccu CLK_PLL_VIDEO0_2X>;
 
 	status = "okay";
 };
diff --git a/dts/upstream/src/arm64/allwinner/sun50i-a64-teres-i.dts b/dts/upstream/src/arm64/allwinner/sun50i-a64-teres-i.dts
index b407e1dd08a..ec055510af8 100644
--- a/dts/upstream/src/arm64/allwinner/sun50i-a64-teres-i.dts
+++ b/dts/upstream/src/arm64/allwinner/sun50i-a64-teres-i.dts
@@ -369,6 +369,8 @@
 &tcon0 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&lcd_rgb666_pins>;
+	assigned-clocks = <&ccu CLK_TCON0>;
+	assigned-clock-parents = <&ccu CLK_PLL_VIDEO0_2X>;
 
 	status = "okay";
 };
diff --git a/dts/upstream/src/arm64/allwinner/sun50i-a64.dtsi b/dts/upstream/src/arm64/allwinner/sun50i-a64.dtsi
index a5c3920e0f0..0fecf0abb20 100644
--- a/dts/upstream/src/arm64/allwinner/sun50i-a64.dtsi
+++ b/dts/upstream/src/arm64/allwinner/sun50i-a64.dtsi
@@ -445,6 +445,8 @@
 			clock-names = "ahb", "tcon-ch0";
 			clock-output-names = "tcon-data-clock";
 			#clock-cells = <0>;
+			assigned-clocks = <&ccu CLK_TCON0>;
+			assigned-clock-parents = <&ccu CLK_PLL_MIPI>;
 			resets = <&ccu RST_BUS_TCON0>, <&ccu RST_BUS_LVDS>;
 			reset-names = "lcd", "lvds";
 
diff --git a/dts/upstream/src/arm64/allwinner/sun50i-h313-tanix-tx1.dts b/dts/upstream/src/arm64/allwinner/sun50i-h313-tanix-tx1.dts
index bafd3e80310..17e6aef67aa 100644
--- a/dts/upstream/src/arm64/allwinner/sun50i-h313-tanix-tx1.dts
+++ b/dts/upstream/src/arm64/allwinner/sun50i-h313-tanix-tx1.dts
@@ -6,6 +6,7 @@
 /dts-v1/;
 
 #include "sun50i-h616.dtsi"
+#include "sun50i-h616-cpu-opp.dtsi"
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
diff --git a/dts/upstream/src/arm64/altera/socfpga_stratix10_swvp.dts b/dts/upstream/src/arm64/altera/socfpga_stratix10_swvp.dts
index 0d837d3e65a..34ccf8138f7 100644
--- a/dts/upstream/src/arm64/altera/socfpga_stratix10_swvp.dts
+++ b/dts/upstream/src/arm64/altera/socfpga_stratix10_swvp.dts
@@ -63,7 +63,6 @@
 	status = "okay";
 	phy-mode = "rgmii";
 	phy-addr = <0xffffffff>;
-	snps,max-mtu = <0x0>;
 };
 
 &gmac1 {
diff --git a/dts/upstream/src/arm64/amlogic/meson-gxbb-p20x.dtsi b/dts/upstream/src/arm64/amlogic/meson-gxbb-p20x.dtsi
index 52d57773a77..1736bd2e96e 100644
--- a/dts/upstream/src/arm64/amlogic/meson-gxbb-p20x.dtsi
+++ b/dts/upstream/src/arm64/amlogic/meson-gxbb-p20x.dtsi
@@ -178,9 +178,8 @@
 	vmmc-supply = <&vddao_3v3>;
 	vqmmc-supply = <&vddio_boot>;
 
-	brcmf: wifi@1 {
+	sdio: wifi@1 {
 		reg = <1>;
-		compatible = "brcm,bcm4329-fmac";
 	};
 };
 
diff --git a/dts/upstream/src/arm64/amlogic/meson-gxl-s905d-p230.dts b/dts/upstream/src/arm64/amlogic/meson-gxl-s905d-p230.dts
index c1470416faa..7dffeb5931c 100644
--- a/dts/upstream/src/arm64/amlogic/meson-gxl-s905d-p230.dts
+++ b/dts/upstream/src/arm64/amlogic/meson-gxl-s905d-p230.dts
@@ -102,8 +102,7 @@
 };
 
 &sd_emmc_a {
-	brcmf: wifi@1 {
+	sdio: wifi@1 {
 		reg = <1>;
-		compatible = "brcm,bcm4329-fmac";
 	};
 };
diff --git a/dts/upstream/src/arm64/amlogic/meson-gxl-s905d-p231.dts b/dts/upstream/src/arm64/amlogic/meson-gxl-s905d-p231.dts
index 92c425d0259..ff9145d4909 100644
--- a/dts/upstream/src/arm64/amlogic/meson-gxl-s905d-p231.dts
+++ b/dts/upstream/src/arm64/amlogic/meson-gxl-s905d-p231.dts
@@ -21,8 +21,7 @@
 };
 
 &sd_emmc_a {
-	brcmf: wifi@1 {
+	sdio: wifi@1 {
 		reg = <1>;
-		compatible = "brcm,bcm4329-fmac";
 	};
 };
diff --git a/dts/upstream/src/arm64/amlogic/meson-gxl-s905x-p212.dtsi b/dts/upstream/src/arm64/amlogic/meson-gxl-s905x-p212.dtsi
index 7e7dc87ede2..b52a830efcc 100644
--- a/dts/upstream/src/arm64/amlogic/meson-gxl-s905x-p212.dtsi
+++ b/dts/upstream/src/arm64/amlogic/meson-gxl-s905x-p212.dtsi
@@ -134,9 +134,8 @@
 	vmmc-supply = <&vddao_3v3>;
 	vqmmc-supply = <&vddio_boot>;
 
-	brcmf: wifi@1 {
+	sdio: wifi@1 {
 		reg = <1>;
-		compatible = "brcm,bcm4329-fmac";
 	};
 };
 
diff --git a/dts/upstream/src/arm64/amlogic/meson-gxm-q200.dts b/dts/upstream/src/arm64/amlogic/meson-gxm-q200.dts
index d4858afa0e9..feb31207773 100644
--- a/dts/upstream/src/arm64/amlogic/meson-gxm-q200.dts
+++ b/dts/upstream/src/arm64/amlogic/meson-gxm-q200.dts
@@ -72,8 +72,7 @@
 };
 
 &sd_emmc_a {
-	brcmf: wifi@1 {
+	sdio: wifi@1 {
 		reg = <1>;
-		compatible = "brcm,bcm4329-fmac";
 	};
 };
diff --git a/dts/upstream/src/arm64/amlogic/meson-gxm-q201.dts b/dts/upstream/src/arm64/amlogic/meson-gxm-q201.dts
index d02b80d7737..6c8bec1853a 100644
--- a/dts/upstream/src/arm64/amlogic/meson-gxm-q201.dts
+++ b/dts/upstream/src/arm64/amlogic/meson-gxm-q201.dts
@@ -21,8 +21,7 @@
 };
 
 &sd_emmc_a {
-	brcmf: wifi@1 {
+	sdio: wifi@1 {
 		reg = <1>;
-		compatible = "brcm,bcm4329-fmac";
 	};
 };
diff --git a/dts/upstream/src/arm64/blaize/blaize-blzp1600-cb2.dts b/dts/upstream/src/arm64/blaize/blaize-blzp1600-cb2.dts
new file mode 100644
index 00000000000..7e3cef2ed35
--- /dev/null
+++ b/dts/upstream/src/arm64/blaize/blaize-blzp1600-cb2.dts
@@ -0,0 +1,83 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2024 Blaize, Inc. All rights reserved.
+ */
+
+/dts-v1/;
+
+#include "blaize-blzp1600-som.dtsi"
+
+/ {
+	model = "Blaize BLZP1600 SoM1600P CB2 Development Board";
+
+	compatible = "blaize,blzp1600-cb2", "blaize,blzp1600";
+
+	aliases {
+		serial0 = &uart0;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200";
+	};
+};
+
+&i2c0 {
+	clock-frequency = <100000>;
+	status = "okay";
+};
+
+&i2c1 {
+	clock-frequency = <100000>;
+	status = "okay";
+};
+
+&i2c3 {
+	clock-frequency = <100000>;
+	status = "okay";
+
+	gpio_expander: gpio@74 {
+		compatible = "ti,tca9539";
+		reg = <0x74>;
+		gpio-controller;
+		#gpio-cells = <2>;
+		gpio-line-names = "RSP_PIN_7",	/* GPIO_0 */
+				  "RSP_PIN_11",	/* GPIO_1 */
+				  "RSP_PIN_13",	/* GPIO_2 */
+				  "RSP_PIN_15",	/* GPIO_3 */
+				  "RSP_PIN_27",	/* GPIO_4 */
+				  "RSP_PIN_29",	/* GPIO_5 */
+				  "RSP_PIN_31",	/* GPIO_6 */
+				  "RSP_PIN_33",	/* GPIO_7 */
+				  "RSP_PIN_37",	/* GPIO_8 */
+				  "RSP_PIN_16",	/* GPIO_9 */
+				  "RSP_PIN_18",	/* GPIO_10 */
+				  "RSP_PIN_22",	/* GPIO_11 */
+				  "RSP_PIN_28",	/* GPIO_12 */
+				  "RSP_PIN_32",	/* GPIO_13 */
+				  "RSP_PIN_36",	/* GPIO_14 */
+				  "TP31";	/* GPIO_15 */
+	};
+
+	gpio_expander_m2: gpio@75 {
+		compatible = "ti,tca9539";
+		reg = <0x75>;
+		gpio-controller;
+		#gpio-cells = <2>;
+		gpio-line-names = "M2_W_DIS1_N",	/* GPIO_0 */
+				  "M2_W_DIS2_N",	/* GPIO_1 */
+				  "M2_UART_WAKE_N",	/* GPIO_2 */
+				  "M2_COEX3",		/* GPIO_3 */
+				  "M2_COEX_RXD",	/* GPIO_4 */
+				  "M2_COEX_TXD",	/* GPIO_5 */
+				  "M2_VENDOR_PIN40",	/* GPIO_6 */
+				  "M2_VENDOR_PIN42",	/* GPIO_7 */
+				  "M2_VENDOR_PIN38",	/* GPIO_8 */
+				  "M2_SDIO_RST_N",	/* GPIO_9 */
+				  "M2_SDIO_WAKE_N",	/* GPIO_10 */
+				  "M2_PETN1",		/* GPIO_11 */
+				  "M2_PERP1",		/* GPIO_12 */
+				  "M2_PERN1",		/* GPIO_13 */
+				  "UIM_SWP",		/* GPIO_14 */
+				  "UART1_TO_RSP";	/* GPIO_15 */
+	};
+};
diff --git a/dts/upstream/src/arm64/blaize/blaize-blzp1600-som.dtsi b/dts/upstream/src/arm64/blaize/blaize-blzp1600-som.dtsi
new file mode 100644
index 00000000000..bfdff5953ed
--- /dev/null
+++ b/dts/upstream/src/arm64/blaize/blaize-blzp1600-som.dtsi
@@ -0,0 +1,23 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2024 Blaize, Inc. All rights reserved.
+ */
+
+#include "blaize-blzp1600.dtsi"
+
+/ {
+	memory@0 {
+		device_type = "memory";
+		reg = <0x0 0x0 0x1 0x0>;
+	};
+};
+
+/* i2c4 bus is available only on the SoM, not on the board */
+&i2c4 {
+	clock-frequency = <100000>;
+	status = "okay";
+};
+
+&uart0 {
+	status = "okay";
+};
diff --git a/dts/upstream/src/arm64/blaize/blaize-blzp1600.dtsi b/dts/upstream/src/arm64/blaize/blaize-blzp1600.dtsi
new file mode 100644
index 00000000000..7d399e6a532
--- /dev/null
+++ b/dts/upstream/src/arm64/blaize/blaize-blzp1600.dtsi
@@ -0,0 +1,205 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2024 Blaize, Inc. All rights reserved.
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+	interrupt-parent = <&gic>;
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	cpus {
+		#address-cells = <2>;
+		#size-cells = <0>;
+
+		cpu0: cpu@0 {
+			compatible = "arm,cortex-a53";
+			reg = <0x0 0x0>;
+			device_type = "cpu";
+			enable-method = "psci";
+			next-level-cache = <&l2>;
+		};
+
+		cpu1: cpu@1 {
+			compatible = "arm,cortex-a53";
+			reg = <0x0 0x1>;
+			device_type = "cpu";
+			enable-method = "psci";
+			next-level-cache = <&l2>;
+		};
+
+		l2: l2-cache0 {
+			compatible = "cache";
+			cache-level = <2>;
+			cache-unified;
+		};
+	};
+
+	firmware {
+		scmi {
+			compatible = "arm,scmi-smc";
+			arm,smc-id = <0x82002000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			shmem = <&scmi0_shm>;
+
+			scmi_clk: protocol@14 {
+				reg = <0x14>;
+				#clock-cells = <1>;
+			};
+
+			scmi_rst: protocol@16 {
+				reg = <0x16>;
+				#reset-cells = <1>;
+			};
+		};
+	};
+
+	pmu {
+		compatible = "arm,cortex-a53-pmu";
+		interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-affinity = <&cpu0>, <&cpu1>;
+	};
+
+	psci {
+		compatible = "arm,psci-1.0", "arm,psci-0.2";
+		method = "smc";
+	};
+
+	reserved-memory {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		/* SCMI reserved buffer space on DDR space */
+		scmi0_shm: scmi-shmem@800 {
+			compatible = "arm,scmi-shmem";
+			reg = <0x0 0x800 0x0 0x80>;
+		};
+	};
+
+	timer {
+		compatible = "arm,armv8-timer";
+		interrupts = /* Physical Secure PPI */
+			     <GIC_PPI 13 (GIC_CPU_MASK_RAW(0x3) |
+					  IRQ_TYPE_LEVEL_LOW)>,
+			     /* Physical Non-Secure PPI */
+			     <GIC_PPI 14 (GIC_CPU_MASK_RAW(0x3) |
+					  IRQ_TYPE_LEVEL_LOW)>,
+			     /* Hypervisor PPI */
+			     <GIC_PPI 10 (GIC_CPU_MASK_RAW(0x3) |
+					  IRQ_TYPE_LEVEL_LOW)>,
+			     /* Virtual PPI */
+			     <GIC_PPI 11 (GIC_CPU_MASK_RAW(0x3) |
+					  IRQ_TYPE_LEVEL_LOW)>;
+	};
+
+	soc@200000000 {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0x0 0x2 0x0 0x850000>;
+
+		gic: interrupt-controller@410000 {
+			compatible = "arm,gic-400";
+			reg = <0x410000 0x20000>,
+			      <0x420000 0x20000>,
+			      <0x440000 0x20000>,
+			      <0x460000 0x20000>;
+			#interrupt-cells = <3>;
+			#address-cells = <0>;
+			interrupt-controller;
+			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_RAW(0x3) |
+						 IRQ_TYPE_LEVEL_LOW)>;
+		};
+
+		uart0: serial@4d0000 {
+			compatible = "ns16550a";
+			reg = <0x4d0000 0x1000>;
+			clocks = <&scmi_clk 59>;
+			resets = <&scmi_rst 59>;
+			reg-shift = <2>;
+			interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+			status = "disabled";
+		};
+
+		uart1: serial@4e0000 {
+			compatible = "ns16550a";
+			reg = <0x4e0000 0x1000>;
+			clocks = <&scmi_clk 60>;
+			resets = <&scmi_rst 60>;
+			reg-shift = <2>;
+			interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
+			status = "disabled";
+		};
+
+		i2c0: i2c@4f0000 {
+			compatible = "snps,designware-i2c";
+			reg = <0x4f0000 0x1000>;
+			interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&scmi_clk 54>;
+			resets = <&scmi_rst 54>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		i2c1: i2c@500000 {
+			compatible = "snps,designware-i2c";
+			reg = <0x500000 0x1000>;
+			interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&scmi_clk 55>;
+			resets = <&scmi_rst 55>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		i2c2: i2c@510000 {
+			compatible = "snps,designware-i2c";
+			reg = <0x510000 0x1000>;
+			interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&scmi_clk 56>;
+			resets = <&scmi_rst 56>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		i2c3: i2c@520000 {
+			compatible = "snps,designware-i2c";
+			reg = <0x520000 0x1000>;
+			interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&scmi_clk 57>;
+			resets = <&scmi_rst 57>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		i2c4: i2c@530000 {
+			compatible = "snps,designware-i2c";
+			reg = <0x530000 0x1000>;
+			interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&scmi_clk 58>;
+			resets = <&scmi_rst 58>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		arm_cc712: crypto@550000 {
+			compatible = "arm,cryptocell-712-ree";
+			reg = <0x550000 0x1000>;
+			interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&scmi_clk 7>;
+		};
+	};
+};
diff --git a/dts/upstream/src/arm64/broadcom/bcm2712-d-rpi-5-b.dts b/dts/upstream/src/arm64/broadcom/bcm2712-d-rpi-5-b.dts
new file mode 100644
index 00000000000..7de24d60bcd
--- /dev/null
+++ b/dts/upstream/src/arm64/broadcom/bcm2712-d-rpi-5-b.dts
@@ -0,0 +1,37 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/dts-v1/;
+
+#include "bcm2712-rpi-5-b.dts"
+
+&gio_aon {
+	brcm,gpio-bank-widths = <15 6>;
+
+	gpio-line-names =
+		"RP1_SDA", // AON_GPIO_00
+		"RP1_SCL", // AON_GPIO_01
+		"RP1_RUN", // AON_GPIO_02
+		"SD_IOVDD_SEL", // AON_GPIO_03
+		"SD_PWR_ON", // AON_GPIO_04
+		"SD_CDET_N", // AON_GPIO_05
+		"SD_FLG_N", // AON_GPIO_06
+		"", // AON_GPIO_07
+		"2712_WAKE", // AON_GPIO_08
+		"2712_STAT_LED", // AON_GPIO_09
+		"", // AON_GPIO_10
+		"", // AON_GPIO_11
+		"PMIC_INT", // AON_GPIO_12
+		"UART_TX_FS", // AON_GPIO_13
+		"UART_RX_FS", // AON_GPIO_14
+		"", // AON_GPIO_15
+		"", // AON_GPIO_16
+
+		// Pad bank0 out to 32 entries
+		"", "", "", "", "", "", "", "", "", "", "", "", "", "", "",
+
+		"HDMI0_SCL", // AON_SGPIO_00
+		"HDMI0_SDA", // AON_SGPIO_01
+		"HDMI1_SCL", // AON_SGPIO_02
+		"HDMI1_SDA", // AON_SGPIO_03
+		"PMIC_SCL", // AON_SGPIO_04
+		"PMIC_SDA"; // AON_SGPIO_05
+};
diff --git a/dts/upstream/src/arm64/broadcom/bcm2712-rpi-5-b.dts b/dts/upstream/src/arm64/broadcom/bcm2712-rpi-5-b.dts
index 2bdbb678024..fbc56309660 100644
--- a/dts/upstream/src/arm64/broadcom/bcm2712-rpi-5-b.dts
+++ b/dts/upstream/src/arm64/broadcom/bcm2712-rpi-5-b.dts
@@ -62,3 +62,45 @@
 	sd-uhs-ddr50;
 	sd-uhs-sdr104;
 };
+
+&soc {
+	firmware: firmware {
+		compatible = "raspberrypi,bcm2835-firmware", "simple-mfd";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		mboxes = <&mailbox>;
+		dma-ranges;
+
+		firmware_clocks: clocks {
+			compatible = "raspberrypi,firmware-clocks";
+			#clock-cells = <1>;
+		};
+
+		reset: reset {
+			compatible = "raspberrypi,firmware-reset";
+			#reset-cells = <1>;
+		};
+	};
+
+	power: power {
+		compatible = "raspberrypi,bcm2835-power";
+		firmware = <&firmware>;
+		#power-domain-cells = <1>;
+	};
+};
+
+&hvs {
+	clocks = <&firmware_clocks 4>, <&firmware_clocks 16>;
+	clock-names = "core", "disp";
+};
+
+&hdmi0 {
+	clocks = <&firmware_clocks 13>, <&firmware_clocks 14>, <&dvp 0>, <&clk_27MHz>;
+	clock-names = "hdmi", "bvb", "audio", "cec";
+};
+
+&hdmi1 {
+	clocks = <&firmware_clocks 13>, <&firmware_clocks 14>, <&dvp 1>, <&clk_27MHz>;
+	clock-names = "hdmi", "bvb", "audio", "cec";
+};
diff --git a/dts/upstream/src/arm64/broadcom/bcm2712.dtsi b/dts/upstream/src/arm64/broadcom/bcm2712.dtsi
index 26a29e5e507..9e610a89a33 100644
--- a/dts/upstream/src/arm64/broadcom/bcm2712.dtsi
+++ b/dts/upstream/src/arm64/broadcom/bcm2712.dtsi
@@ -221,18 +221,13 @@
 			#mbox-cells = <0>;
 		};
 
-		local_intc: interrupt-controller@7cd00000 {
-			compatible = "brcm,bcm2836-l1-intc";
-			reg = <0x7cd00000 0x100>;
-		};
-
 		uart10: serial@7d001000 {
 			compatible = "arm,pl011", "arm,primecell";
 			reg = <0x7d001000 0x200>;
 			interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&clk_uart>, <&clk_vpu>;
 			clock-names = "uartclk", "apb_pclk";
-			arm,primecell-periphid = <0x00241011>;
+			arm,primecell-periphid = <0x00341011>;
 			status = "disabled";
 		};
 
@@ -265,6 +260,172 @@
 			interrupt-controller;
 			#interrupt-cells = <3>;
 		};
+
+		aon_intr: interrupt-controller@7d510600 {
+			compatible = "brcm,bcm2711-l2-intc", "brcm,l2-intc";
+			reg = <0x7d510600 0x30>;
+			interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-controller;
+			#interrupt-cells = <1>;
+		};
+
+		pixelvalve0: pixelvalve@7c410000 {
+			compatible = "brcm,bcm2712-pixelvalve0";
+			reg = <0x7c410000 0x100>;
+			interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
+		};
+
+		pixelvalve1: pixelvalve@7c411000 {
+			compatible = "brcm,bcm2712-pixelvalve1";
+			reg = <0x7c411000 0x100>;
+			interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
+		};
+
+		mop: mop@7c500000 {
+			compatible = "brcm,bcm2712-mop";
+			reg = <0x7c500000 0x28>;
+			interrupt-parent = <&disp_intr>;
+			interrupts = <1>;
+		};
+
+		moplet: moplet@7c501000 {
+			compatible = "brcm,bcm2712-moplet";
+			reg = <0x7c501000 0x20>;
+			interrupt-parent = <&disp_intr>;
+			interrupts = <0>;
+		};
+
+		disp_intr: interrupt-controller@7c502000 {
+			compatible = "brcm,bcm2711-l2-intc", "brcm,l2-intc";
+			reg = <0x7c502000 0x30>;
+			interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-controller;
+			#interrupt-cells = <1>;
+		};
+
+		dvp: clock@7c700000 {
+			compatible = "brcm,brcm2711-dvp";
+			reg = <0x7c700000 0x10>;
+			clocks = <&clk_108MHz>;
+			#clock-cells = <1>;
+			#reset-cells = <1>;
+		};
+
+		ddc0: i2c@7d508200 {
+			compatible = "brcm,brcmstb-i2c";
+			reg = <0x7d508200 0x58>;
+			interrupt-parent = <&bsc_irq>;
+			interrupts = <1>;
+			clock-frequency = <97500>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		ddc1: i2c@7d508280 {
+			compatible = "brcm,brcmstb-i2c";
+			reg = <0x7d508280 0x58>;
+			interrupt-parent = <&bsc_irq>;
+			interrupts = <2>;
+			clock-frequency = <97500>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		bsc_irq: interrupt-controller@7d508380 {
+			compatible = "brcm,bcm7271-l2-intc";
+			reg = <0x7d508380 0x10>;
+			interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-controller;
+			#interrupt-cells = <1>;
+		};
+
+		main_irq: interrupt-controller@7d508400 {
+			compatible = "brcm,bcm7271-l2-intc";
+			reg = <0x7d508400 0x10>;
+			interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-controller;
+			#interrupt-cells = <1>;
+		};
+
+		hdmi0: hdmi@7c701400 {
+			compatible = "brcm,bcm2712-hdmi0";
+			reg = <0x7c701400 0x300>,
+			      <0x7c701000 0x200>,
+			      <0x7c701d00 0x300>,
+			      <0x7c702000 0x80>,
+			      <0x7c703800 0x200>,
+			      <0x7c704000 0x800>,
+			      <0x7c700100 0x80>,
+			      <0x7d510800 0x100>,
+			      <0x7c720000 0x100>;
+			reg-names = "hdmi",
+				    "dvp",
+				    "phy",
+				    "rm",
+				    "packet",
+				    "metadata",
+				    "csc",
+				    "cec",
+				    "hd";
+			resets = <&dvp 1>;
+			interrupt-parent = <&aon_intr>;
+			interrupts = <1>, <2>, <3>,
+				     <7>, <8>;
+			interrupt-names = "cec-tx", "cec-rx", "cec-low",
+					  "hpd-connected", "hpd-removed";
+			ddc = <&ddc0>;
+		};
+
+		hdmi1: hdmi@7c706400 {
+			compatible = "brcm,bcm2712-hdmi1";
+			reg = <0x7c706400 0x300>,
+			      <0x7c706000 0x200>,
+			      <0x7c706d00 0x300>,
+			      <0x7c707000 0x80>,
+			      <0x7c708800 0x200>,
+			      <0x7c709000 0x800>,
+			      <0x7c700180 0x80>,
+			      <0x7d511000 0x100>,
+			      <0x7c720000 0x100>;
+			reg-names = "hdmi",
+				    "dvp",
+				    "phy",
+				    "rm",
+				    "packet",
+				    "metadata",
+				    "csc",
+				    "cec",
+				    "hd";
+			resets = <&dvp 2>;
+			interrupt-parent = <&aon_intr>;
+			interrupts = <11>, <12>, <13>,
+				     <14>, <15>;
+			interrupt-names = "cec-tx", "cec-rx", "cec-low",
+					  "hpd-connected", "hpd-removed";
+			ddc = <&ddc1>;
+		};
+	};
+
+	axi: axi {
+		compatible = "simple-bus";
+		#address-cells = <2>;
+		#size-cells = <2>;
+
+		ranges = <0x00 0x00000000  0x00 0x00000000  0x10 0x00000000>,
+			 <0x10 0x00000000  0x10 0x00000000  0x01 0x00000000>,
+			 <0x14 0x00000000  0x14 0x00000000  0x04 0x00000000>,
+			 <0x18 0x00000000  0x18 0x00000000  0x04 0x00000000>,
+			 <0x1c 0x00000000  0x1c 0x00000000  0x04 0x00000000>;
+
+		dma-ranges = <0x00 0x00000000  0x00 0x00000000  0x10 0x00000000>,
+			     <0x10 0x00000000  0x10 0x00000000  0x01 0x00000000>,
+			     <0x14 0x00000000  0x14 0x00000000  0x04 0x00000000>,
+			     <0x18 0x00000000  0x18 0x00000000  0x04 0x00000000>,
+			     <0x1c 0x00000000  0x1c 0x00000000  0x04 0x00000000>;
+
+		vc4: gpu {
+			compatible = "brcm,bcm2712-vc6";
+		};
 	};
 
 	timer {
@@ -280,4 +441,26 @@
 			     <GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(4) |
 					  IRQ_TYPE_LEVEL_LOW)>;
 	};
+
+	clk_27MHz: clk-27M {
+		#clock-cells = <0>;
+		compatible = "fixed-clock";
+		clock-frequency = <27000000>;
+		clock-output-names = "27MHz-clock";
+	};
+
+	clk_108MHz: clk-108M {
+		#clock-cells = <0>;
+		compatible = "fixed-clock";
+		clock-frequency = <108000000>;
+		clock-output-names = "108MHz-clock";
+	};
+
+	hvs: hvs@107c580000 {
+		compatible = "brcm,bcm2712-hvs";
+		reg = <0x10 0x7c580000 0x0 0x1a000>;
+		interrupt-parent = <&disp_intr>;
+		interrupts = <2>, <9>, <16>;
+		interrupt-names = "ch0-eof", "ch1-eof", "ch2-eof";
+	};
 };
diff --git a/dts/upstream/src/arm64/broadcom/bcmbca/bcm4906-netgear-r8000p.dts b/dts/upstream/src/arm64/broadcom/bcmbca/bcm4906-netgear-r8000p.dts
index 999d9373024..a5f9ec92bd5 100644
--- a/dts/upstream/src/arm64/broadcom/bcmbca/bcm4906-netgear-r8000p.dts
+++ b/dts/upstream/src/arm64/broadcom/bcmbca/bcm4906-netgear-r8000p.dts
@@ -144,16 +144,20 @@
 		#size-cells = <1>;
 
 		partition@0 {
-			compatible = "nvmem-cells";
 			label = "cferom";
 			reg = <0x0 0x100000>;
-
 			#address-cells = <1>;
 			#size-cells = <1>;
 			ranges = <0 0x0 0x100000>;
 
-			base_mac_addr: mac@106a0 {
-				reg = <0x106a0 0x6>;
+			nvmem-layout {
+				compatible = "fixed-layout";
+				#address-cells = <1>;
+				#size-cells = <1>;
+
+				base_mac_addr: mac@106a0 {
+					reg = <0x106a0 0x6>;
+				};
 			};
 		};
 
diff --git a/dts/upstream/src/arm64/broadcom/bcmbca/bcm4906-zyxel-ex3510b.dts b/dts/upstream/src/arm64/broadcom/bcmbca/bcm4906-zyxel-ex3510b.dts
new file mode 100644
index 00000000000..54e453bd09f
--- /dev/null
+++ b/dts/upstream/src/arm64/broadcom/bcmbca/bcm4906-zyxel-ex3510b.dts
@@ -0,0 +1,196 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
+
+#include "bcm4906.dtsi"
+
+/ {
+	compatible = "zyxel,ex3510b", "brcm,bcm4906", "brcm,bcm4908", "brcm,bcmbca";
+	model = "Zyxel EX3510-B";
+
+	memory@0 {
+		device_type = "memory";
+		reg = <0x0 0x0 0x0 0x20000000>;
+	};
+
+	gpio-keys-polled {
+		compatible = "gpio-keys-polled";
+		poll-interval = <100>;
+
+		key-wps {
+			label = "WPS";
+			linux,code = <KEY_WPS_BUTTON>;
+			gpios = <&gpio0 22 GPIO_ACTIVE_LOW>;
+		};
+
+		key-reset {
+			label = "Reset";
+			linux,code = <KEY_RESTART>;
+			gpios = <&gpio0 23 GPIO_ACTIVE_LOW>;
+		};
+	};
+};
+
+&leds {
+	pinctrl-0 = <&pins_led_0_a>, <&pins_led_2_a>, <&pins_led_3_a>,
+		    <&pins_led_4_a>, <&pins_led_10_a>, <&pins_led_12_a>,
+		    <&pins_led_14_a>, <&pins_led_15_a>, <&pins_led_21_a>;
+	pinctrl-names = "default";
+
+	led@0 {
+		reg = <0x0>;
+		function = LED_FUNCTION_POWER;
+		color = <LED_COLOR_ID_RED>;
+	};
+
+	led@2 {
+		reg = <0x2>;
+		function = LED_FUNCTION_WAN_ONLINE;
+		color = <LED_COLOR_ID_GREEN>;
+	};
+
+	led@3 {
+		reg = <0x3>;
+		function = LED_FUNCTION_WAN_ONLINE;
+		color = <LED_COLOR_ID_RED>;
+	};
+
+	led@4 {
+		reg = <0x4>;
+		function = LED_FUNCTION_USB;
+		color = <LED_COLOR_ID_GREEN>;
+		trigger-sources = <&ohci_port1>, <&ohci_port2>,
+				  <&ehci_port1>, <&ehci_port2>,
+				  <&xhci_port1>, <&xhci_port2>;
+		linux,default-trigger = "usbport";
+	};
+
+	led@a {
+		reg = <0xa>;
+		function = LED_FUNCTION_POWER;
+		color = <LED_COLOR_ID_GREEN>;
+		linux,default-trigger = "default-on";
+	};
+
+	led@c {
+		reg = <0xc>;
+		function = LED_FUNCTION_LAN;
+		color = <LED_COLOR_ID_GREEN>;
+		active-low;
+	};
+
+	led@e {
+		reg = <0xe>;
+		function = LED_FUNCTION_WPS;
+		color = <LED_COLOR_ID_GREEN>;
+		active-low;
+	};
+
+	led@f {
+		reg = <0xf>;
+		function = LED_FUNCTION_WPS;
+		color = <LED_COLOR_ID_RED>;
+		active-low;
+	};
+
+	led@15 {
+		reg = <0x15>;
+		function = LED_FUNCTION_WAN;
+		color = <LED_COLOR_ID_GREEN>;
+		active-low;
+	};
+};
+
+&enet {
+	nvmem-cells = <&base_mac_addr>;
+	nvmem-cell-names = "mac-address";
+};
+
+&usb_phy {
+	brcm,ioc = <1>;
+	brcm,ipp = <1>;
+	status = "okay";
+};
+
+&ehci {
+	status = "okay";
+};
+
+&ohci {
+	status = "okay";
+};
+
+&xhci {
+	status = "okay";
+};
+
+&ports {
+	port@0 {
+		label = "lan1";
+	};
+
+	port@1 {
+		label = "lan2";
+	};
+
+	port@2 {
+		label = "lan3";
+	};
+
+	port@3 {
+		label = "lan4";
+	};
+
+	port@7 {
+		reg = <7>;
+		phy-mode = "internal";
+		phy-handle = <&phy12>;
+		label = "wan";
+	};
+};
+
+&nand_controller {
+	status = "okay";
+};
+
+&nandcs {
+	brcm,nand-oob-sector-size = <27>;
+	nand-ecc-strength = <8>;
+	nand-ecc-step-size = <512>;
+	nand-on-flash-bbt;
+
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	partitions {
+		compatible = "brcm,bcm4908-partitions";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		partition@0 {
+			compatible = "nvmem-cells";
+			label = "cferom";
+			reg = <0x0 0x100000>;
+			read-only;
+
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			base_mac_addr: mac@106a0 {
+				reg = <0x106a0 0x6>;
+			};
+		};
+
+		partition@100000 {
+			compatible = "brcm,bcm4908-firmware";
+			reg = <0x100000 0x5f80000>;
+		};
+
+		partition@6080000 {
+			compatible = "brcm,bcm4908-firmware";
+			reg = <0x6080000 0x5f80000>;
+		};
+	};
+};
diff --git a/dts/upstream/src/arm64/broadcom/bcmbca/bcm4908.dtsi b/dts/upstream/src/arm64/broadcom/bcmbca/bcm4908.dtsi
index 8b924812322..613ba7ee43d 100644
--- a/dts/upstream/src/arm64/broadcom/bcmbca/bcm4908.dtsi
+++ b/dts/upstream/src/arm64/broadcom/bcmbca/bcm4908.dtsi
@@ -30,7 +30,7 @@
 			compatible = "brcm,brahma-b53";
 			reg = <0x0>;
 			enable-method = "spin-table";
-			cpu-release-addr = <0x0 0xfff8>;
+			cpu-release-addr = <0x0 0xff8>;
 			next-level-cache = <&l2>;
 		};
 
@@ -39,7 +39,7 @@
 			compatible = "brcm,brahma-b53";
 			reg = <0x1>;
 			enable-method = "spin-table";
-			cpu-release-addr = <0x0 0xfff8>;
+			cpu-release-addr = <0x0 0xff8>;
 			next-level-cache = <&l2>;
 		};
 
@@ -48,7 +48,7 @@
 			compatible = "brcm,brahma-b53";
 			reg = <0x2>;
 			enable-method = "spin-table";
-			cpu-release-addr = <0x0 0xfff8>;
+			cpu-release-addr = <0x0 0xff8>;
 			next-level-cache = <&l2>;
 		};
 
@@ -57,7 +57,7 @@
 			compatible = "brcm,brahma-b53";
 			reg = <0x3>;
 			enable-method = "spin-table";
-			cpu-release-addr = <0x0 0xfff8>;
+			cpu-release-addr = <0x0 0xff8>;
 			next-level-cache = <&l2>;
 		};
 
@@ -68,6 +68,16 @@
 		};
 	};
 
+	reserved-memory {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		cfe-stub@0 {
+			reg = <0x0 0x0 0x0 0x1000>;
+		};
+	};
+
 	axi@81000000 {
 		compatible = "simple-bus";
 		#address-cells = <1>;
diff --git a/dts/upstream/src/arm64/broadcom/northstar2/ns2-svk.dts b/dts/upstream/src/arm64/broadcom/northstar2/ns2-svk.dts
index f43cfe66b6a..5939d342aec 100644
--- a/dts/upstream/src/arm64/broadcom/northstar2/ns2-svk.dts
+++ b/dts/upstream/src/arm64/broadcom/northstar2/ns2-svk.dts
@@ -137,7 +137,6 @@
 		spi-cpha;
 		spi-cpol;
 		pl022,interface = <0>;
-		pl022,slave-tx-disable = <0>;
 		pl022,com-mode = <0>;
 		pl022,rx-level-trig = <1>;
 		pl022,tx-level-trig = <1>;
@@ -200,7 +199,6 @@
 };
 
 &qspi {
-	bspi-sel = <0>;
 	flash: flash@0 {
 		#address-cells = <1>;
 		#size-cells = <1>;
diff --git a/dts/upstream/src/arm64/broadcom/northstar2/ns2-xmc.dts b/dts/upstream/src/arm64/broadcom/northstar2/ns2-xmc.dts
index c50df1d0279..0e134a94e14 100644
--- a/dts/upstream/src/arm64/broadcom/northstar2/ns2-xmc.dts
+++ b/dts/upstream/src/arm64/broadcom/northstar2/ns2-xmc.dts
@@ -151,7 +151,6 @@
 		#size-cells = <1>;
 		compatible = "m25p80";
 		spi-max-frequency = <62500000>;
-		m25p,default-addr-width = <3>;
 		reg = <0x0 0x0>;
 
 		partition@0 {
diff --git a/dts/upstream/src/arm64/broadcom/northstar2/ns2.dtsi b/dts/upstream/src/arm64/broadcom/northstar2/ns2.dtsi
index cfd9fd23a1c..5a4b81faff2 100644
--- a/dts/upstream/src/arm64/broadcom/northstar2/ns2.dtsi
+++ b/dts/upstream/src/arm64/broadcom/northstar2/ns2.dtsi
@@ -134,7 +134,6 @@
 		brcm,pcie-ob;
 		brcm,pcie-ob-oarr-size;
 		brcm,pcie-ob-axi-offset = <0x00000000>;
-		brcm,pcie-ob-window-size = <256>;
 
 		status = "disabled";
 
@@ -165,7 +164,6 @@
 		brcm,pcie-ob;
 		brcm,pcie-ob-oarr-size;
 		brcm,pcie-ob-axi-offset = <0x30000000>;
-		brcm,pcie-ob-window-size = <256>;
 
 		status = "disabled";
 
diff --git a/dts/upstream/src/arm64/exynos/exynos850-e850-96.dts b/dts/upstream/src/arm64/exynos/exynos850-e850-96.dts
index f074df8982b..7d70a32e75b 100644
--- a/dts/upstream/src/arm64/exynos/exynos850-e850-96.dts
+++ b/dts/upstream/src/arm64/exynos/exynos850-e850-96.dts
@@ -45,17 +45,9 @@
 		};
 	};
 
-	/*
-	 * RAM: 4 GiB (eMCP):
-	 *   - 2 GiB at 0x80000000
-	 *   - 2 GiB at 0x880000000
-	 *
-	 * 0xbab00000..0xbfffffff: secure memory (85 MiB).
-	 */
 	memory@80000000 {
 		device_type = "memory";
-		reg = <0x0 0x80000000 0x3ab00000>,
-		      <0x0 0xc0000000 0x40000000>,
+		reg = <0x0 0x80000000 0x80000000>,
 		      <0x8 0x80000000 0x80000000>;
 	};
 
@@ -146,6 +138,11 @@
 		#size-cells = <1>;
 		ranges;
 
+		secure_mem: memory@bab00000 {
+			reg = <0x0 0xbab00000 0x5500000>;
+			no-map;
+		};
+
 		ramoops@f0000000 {
 			compatible = "ramoops";
 			reg = <0x0 0xf0000000 0x200000>;
diff --git a/dts/upstream/src/arm64/exynos/exynos8895.dtsi b/dts/upstream/src/arm64/exynos/exynos8895.dtsi
index 9f9ac535987..36657abfc61 100644
--- a/dts/upstream/src/arm64/exynos/exynos8895.dtsi
+++ b/dts/upstream/src/arm64/exynos/exynos8895.dtsi
@@ -38,7 +38,17 @@
 				     <&cpu3>;
 	};
 
-	/* There's no PMU model for the Mongoose cores */
+	mongoose-m2-pmu {
+		compatible = "samsung,mongoose-pmu";
+		interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-affinity = <&cpu4>,
+				     <&cpu5>,
+				     <&cpu6>,
+				     <&cpu7>;
+	};
 
 	cpus {
 		#address-cells = <1>;
@@ -218,6 +228,19 @@
 				      "usi1", "usi2", "usi3";
 		};
 
+		serial_0: serial@10430000 {
+			compatible = "samsung,exynos8895-uart";
+			reg = <0x10430000 0x100>;
+			clocks = <&cmu_peric0 CLK_GOUT_PERIC0_UART_DBG_PCLK>,
+				 <&cmu_peric0 CLK_GOUT_PERIC0_UART_DBG_EXT_UCLK>;
+			clock-names = "uart", "clk_uart_baud0";
+			interrupts = <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&uart0_bus>;
+			samsung,uart-fifosize = <256>;
+			status = "disabled";
+		};
+
 		pinctrl_peric0: pinctrl@104d0000 {
 			compatible = "samsung,exynos8895-pinctrl";
 			reg = <0x104d0000 0x1000>;
@@ -250,12 +273,69 @@
 				      "usi10", "usi11", "usi12", "usi13";
 		};
 
+		serial_1: serial@10830000 {
+			compatible = "samsung,exynos8895-uart";
+			reg = <0x10830000 0x100>;
+			clocks = <&cmu_peric1 CLK_GOUT_PERIC1_UART_BT_PCLK>,
+				 <&cmu_peric1 CLK_GOUT_PERIC1_UART_BT_EXT_UCLK>;
+			clock-names = "uart", "clk_uart_baud0";
+			interrupts = <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&uart1_bus>;
+			samsung,uart-fifosize = <256>;
+			status = "disabled";
+		};
+
 		pinctrl_peric1: pinctrl@10980000 {
 			compatible = "samsung,exynos8895-pinctrl";
 			reg = <0x10980000 0x1000>;
 			interrupts = <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>;
 		};
 
+		hsi2c_1: i2c@10990000 {
+			compatible = "samsung,exynos8895-hsi2c";
+			reg = <0x10990000 0x1000>;
+			clocks = <&cmu_peric1 CLK_GOUT_PERIC1_HSI2C_CAM0_IPCLK>;
+			clock-names = "hsi2c";
+			interrupts = <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>;
+			pinctrl-0 = <&hsi2c1_bus>;
+			pinctrl-names = "default";
+			status = "disabled";
+		};
+
+		hsi2c_2: i2c@109a0000 {
+			compatible = "samsung,exynos8895-hsi2c";
+			reg = <0x109a0000 0x1000>;
+			clocks = <&cmu_peric1 CLK_GOUT_PERIC1_HSI2C_CAM1_IPCLK>;
+			clock-names = "hsi2c";
+			interrupts = <GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>;
+			pinctrl-0 = <&hsi2c2_bus>;
+			pinctrl-names = "default";
+			status = "disabled";
+		};
+
+		hsi2c_3: i2c@109b0000 {
+			compatible = "samsung,exynos8895-hsi2c";
+			reg = <0x109b0000 0x1000>;
+			clocks = <&cmu_peric1 CLK_GOUT_PERIC1_HSI2C_CAM2_IPCLK>;
+			clock-names = "hsi2c";
+			interrupts = <GIC_SPI 433 IRQ_TYPE_LEVEL_HIGH>;
+			pinctrl-0 = <&hsi2c3_bus>;
+			pinctrl-names = "default";
+			status = "disabled";
+		};
+
+		hsi2c_4: i2c@109c0000 {
+			compatible = "samsung,exynos8895-hsi2c";
+			reg = <0x109c0000 0x1000>;
+			clocks = <&cmu_peric1 CLK_GOUT_PERIC1_HSI2C_CAM3_IPCLK>;
+			clock-names = "hsi2c";
+			interrupts = <GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>;
+			pinctrl-0 = <&hsi2c4_bus>;
+			pinctrl-names = "default";
+			status = "disabled";
+		};
+
 		spi_0: spi@109d0000 {
 			compatible = "samsung,exynos8895-spi",
 				     "samsung,exynos850-spi";
diff --git a/dts/upstream/src/arm64/exynos/exynos9810-pinctrl.dtsi b/dts/upstream/src/arm64/exynos/exynos9810-pinctrl.dtsi
new file mode 100644
index 00000000000..88091bf09e4
--- /dev/null
+++ b/dts/upstream/src/arm64/exynos/exynos9810-pinctrl.dtsi
@@ -0,0 +1,503 @@
+// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
+/*
+ * Samsung's Exynos 9810 SoC pin-mux and pin-config device tree source
+ *
+ * Copyright (c) 2024 Markuss Broks <markuss.broks@gmail.com>
+ * Copyright (c) 2024 Maksym Holovach <nergzd@nergzd723.xyz>
+ */
+
+#include "exynos-pinctrl.h"
+
+&pinctrl_alive {
+	etc1: etc1-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	gpa0: gpa0-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		interrupt-parent = <&gic>;
+		interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
+		#interrupt-cells = <2>;
+	};
+
+	gpa1: gpa1-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		interrupt-parent = <&gic>;
+		interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
+		#interrupt-cells = <2>;
+	};
+
+	gpa2: gpa2-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		interrupt-parent = <&gic>;
+		interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
+		#interrupt-cells = <2>;
+	};
+
+	gpa3: gpa3-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		interrupt-parent = <&gic>;
+		interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
+		#interrupt-cells = <2>;
+	};
+
+	gpa4: gpa4-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	gpq0: gpq0-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+};
+
+&pinctrl_aud {
+	gpb0: gpb0-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	gpb1: gpb1-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	gpb2: gpb2-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+};
+
+&pinctrl_chub {
+	gph0: gph0-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	gph1: gph1-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+};
+
+&pinctrl_cmgp {
+	gpm0: gpm0-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+
+		interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+	};
+
+	gpm1: gpm1-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+
+		interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+	};
+
+	gpm2: gpm2-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+
+		interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+	};
+
+	gpm3: gpm3-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+
+		interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+	};
+
+	gpm4: gpm4-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+
+		interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
+	};
+
+	gpm5: gpm5-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+
+		interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+	};
+
+	gpm6: gpm6-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+
+		interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
+	};
+
+	gpm7: gpm7-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+
+		interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
+	};
+
+	gpm10: gpm10-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+
+		interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
+	};
+
+	gpm11: gpm11-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+
+		interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
+	};
+
+	gpm12: gpm12-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+
+		interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
+	};
+
+	gpm13: gpm13-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+
+		interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
+	};
+
+	gpm14: gpm14-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+
+		interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
+	};
+
+	gpm15: gpm15-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+
+		interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
+	};
+
+	gpm16: gpm16-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+
+		interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
+	};
+
+	gpm17: gpm17-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+
+		interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
+	};
+
+	gpm40: gpm40-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+
+		interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+	};
+
+	gpm41: gpm41-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+
+		interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
+	};
+
+	gpm42: gpm42-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+
+		interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
+	};
+
+	gpm43: gpm43-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+
+		interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
+	};
+};
+
+&pinctrl_fsys0 {
+	gpf0: gpf0-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+};
+
+&pinctrl_fsys1 {
+	gpf1: gpf1-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	gpf2: gpf2-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+};
+
+&pinctrl_peric0 {
+	gpg0: gpg0-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	gpg1: gpg1-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	gpg2: gpg2-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	gpp0: gpp0-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	gpp1: gpp1-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	gpp2: gpp2-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	gpp3: gpp3-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+};
+
+&pinctrl_peric1 {
+	gpc0: gpc0-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	gpc1: gpc1-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	gpd0: gpd0-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	gpg3: gpg3-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	gpp4: gpp4-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	gpp5: gpp5-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	gpp6: gpp6-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+};
+
+&pinctrl_vts {
+	gpt0: gpt0-gpio-bank {
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+};
diff --git a/dts/upstream/src/arm64/exynos/exynos9810-starlte.dts b/dts/upstream/src/arm64/exynos/exynos9810-starlte.dts
new file mode 100644
index 00000000000..fc0ddfee4cd
--- /dev/null
+++ b/dts/upstream/src/arm64/exynos/exynos9810-starlte.dts
@@ -0,0 +1,119 @@
+// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
+/*
+ * Samsung Galaxy S9 (starlte/SM-G960F) device tree source
+ *
+ * Copyright (c) 2024 Markuss Broks <markuss.broks@gmail.com>
+ * Copyright (c) 2024 Maksym Holovach <nergzd@nergzd723.xyz>
+ */
+
+/dts-v1/;
+#include "exynos9810.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+
+/ {
+	model = "Samsung Galaxy S9 (SM-G960F)";
+	compatible = "samsung,starlte", "samsung,exynos9810";
+	chassis-type = "handset";
+
+	chosen {
+		#address-cells = <2>;
+		#size-cells = <1>;
+		ranges;
+
+		framebuffer@cc000000 {
+			compatible = "simple-framebuffer";
+			reg = <0x0 0xcc000000 (1440 * 2960 * 4)>;
+			width = <1440>;
+			height = <2960>;
+			stride = <(1440 * 4)>;
+			format = "a8r8g8b8";
+		};
+	};
+
+	gpio-keys {
+		compatible = "gpio-keys";
+
+		pinctrl-0 = <&key_power &key_voldown &key_volup &key_wink>;
+		pinctrl-names = "default";
+
+		power-key {
+			label = "Power";
+			linux,code = <KEY_POWER>;
+			gpios = <&gpa2 4 GPIO_ACTIVE_LOW>;
+			wakeup-source;
+		};
+
+		voldown-key {
+			label = "Volume Down";
+			linux,code = <KEY_VOLUMEDOWN>;
+			gpios = <&gpa0 4 GPIO_ACTIVE_LOW>;
+		};
+
+		volup-key {
+			label = "Volume Up";
+			linux,code = <KEY_VOLUMEUP>;
+			gpios = <&gpa0 3 GPIO_ACTIVE_LOW>;
+		};
+
+		/* In stock firmware used for assistant. Map it as a camera button for now */
+		wink-key {
+			label = "Camera";
+			linux,code = <KEY_CAMERA>;
+			gpios = <&gpa0 6 GPIO_ACTIVE_LOW>;
+		};
+	};
+
+	memory@80000000 {
+		device_type = "memory";
+		reg = <0x0 0x80000000 0x3c800000>,
+		      <0x0 0xc0000000 0x20000000>,
+		      <0x0 0xe1900000 0x1e700000>,
+		      <0x8 0x80000000 0x80000000>;
+	};
+
+	reserved-memory {
+		#address-cells = <2>;
+		#size-cells = <1>;
+		ranges;
+
+		framebuffer@cc000000 {
+			reg = <0x0 0xcc000000 (1440 * 2960 * 4)>;
+			no-map;
+		};
+	};
+};
+
+&oscclk {
+	clock-frequency = <26000000>;
+};
+
+&pinctrl_alive {
+	key_power: key-power-pins {
+		samsung,pins = "gpa2-4";
+		samsung,pin-function = <EXYNOS_PIN_FUNC_EINT>;
+		samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+		samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
+	};
+
+	key_voldown: key-voldown-pins {
+		samsung,pins = "gpa0-4";
+		samsung,pin-function = <EXYNOS_PIN_FUNC_EINT>;
+		samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+		samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
+	};
+
+	key_volup: key-volup-pins {
+		samsung,pins = "gpa0-3";
+		samsung,pin-function = <EXYNOS_PIN_FUNC_EINT>;
+		samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+		samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
+	};
+
+	key_wink: key-wink-pins {
+		samsung,pins = "gpa0-6";
+		samsung,pin-function = <EXYNOS_PIN_FUNC_EINT>;
+		samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+		samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
+	};
+};
diff --git a/dts/upstream/src/arm64/exynos/exynos9810.dtsi b/dts/upstream/src/arm64/exynos/exynos9810.dtsi
new file mode 100644
index 00000000000..01eba31f7ca
--- /dev/null
+++ b/dts/upstream/src/arm64/exynos/exynos9810.dtsi
@@ -0,0 +1,273 @@
+// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
+/*
+ * Samsung Exynos 9810 SoC device tree source
+ *
+ * Copyright (c) 2024 Markuss Broks <markuss.broks@gmail.com>
+ * Copyright (c) 2024 Maksym Holovach <nergzd@nergzd723.xyz>
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+	compatible = "samsung,exynos9810";
+	#address-cells = <2>;
+	#size-cells = <1>;
+
+	interrupt-parent = <&gic>;
+
+	aliases {
+		pinctrl0 = &pinctrl_alive;
+		pinctrl1 = &pinctrl_aud;
+		pinctrl2 = &pinctrl_chub;
+		pinctrl3 = &pinctrl_cmgp;
+		pinctrl4 = &pinctrl_fsys0;
+		pinctrl5 = &pinctrl_fsys1;
+		pinctrl6 = &pinctrl_peric0;
+		pinctrl7 = &pinctrl_peric1;
+		pinctrl8 = &pinctrl_vts;
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu-map {
+			cluster0 {
+				core0 {
+					cpu = <&cpu0>;
+				};
+				core1 {
+					cpu = <&cpu1>;
+				};
+				core2 {
+					cpu = <&cpu2>;
+				};
+				core3 {
+					cpu = <&cpu3>;
+				};
+			};
+
+			cluster1 {
+				core0 {
+					cpu = <&cpu4>;
+				};
+				core1 {
+					cpu = <&cpu5>;
+				};
+				core2 {
+					cpu = <&cpu6>;
+				};
+				core3 {
+					cpu = <&cpu7>;
+				};
+			};
+		};
+
+		cpu0: cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a55";
+			reg = <0x0>;
+			enable-method = "psci";
+		};
+
+		cpu1: cpu@1 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a55";
+			reg = <0x1>;
+			enable-method = "psci";
+		};
+
+		cpu2: cpu@2 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a55";
+			reg = <0x2>;
+			enable-method = "psci";
+		};
+
+		cpu3: cpu@3 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a55";
+			reg = <0x3>;
+			enable-method = "psci";
+		};
+
+		cpu4: cpu@100 {
+			device_type = "cpu";
+			compatible = "samsung,mongoose-m3";
+			reg = <0x100>;
+			enable-method = "psci";
+		};
+
+		cpu5: cpu@101 {
+			device_type = "cpu";
+			compatible = "samsung,mongoose-m3";
+			reg = <0x101>;
+			enable-method = "psci";
+		};
+
+		cpu6: cpu@102 {
+			device_type = "cpu";
+			compatible = "samsung,mongoose-m3";
+			reg = <0x102>;
+			enable-method = "psci";
+		};
+
+		cpu7: cpu@103 {
+			device_type = "cpu";
+			compatible = "samsung,mongoose-m3";
+			reg = <0x103>;
+			enable-method = "psci";
+		};
+	};
+
+	oscclk: osc-clock {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-output-names = "oscclk";
+	};
+
+	pmu-a55 {
+		compatible = "arm,cortex-a55-pmu";
+		interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-affinity = <&cpu0>,
+				     <&cpu1>,
+				     <&cpu2>,
+				     <&cpu3>;
+	};
+
+	pmu-mongoose-m3 {
+		compatible = "samsung,mongoose-pmu";
+		interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-affinity = <&cpu4>,
+				     <&cpu5>,
+				     <&cpu6>,
+				     <&cpu7>;
+	};
+
+	psci {
+		compatible = "arm,psci";
+		method = "smc";
+		cpu_off = <0x84000002>;
+		cpu_on = <0xc4000003>;
+		cpu_suspend = <0xc4000001>;
+	};
+
+	soc: soc@0 {
+		compatible = "simple-bus";
+		ranges = <0x0 0x0 0x0 0x20000000>;
+
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		chipid@10000000 {
+			compatible = "samsung,exynos9810-chipid",
+				     "samsung,exynos850-chipid";
+			reg = <0x10000000 0x100>;
+		};
+
+		gic: interrupt-controller@10101000 {
+			compatible = "arm,gic-400";
+			reg = <0x10101000 0x1000>,
+			      <0x10102000 0x1000>,
+			      <0x10104000 0x2000>,
+			      <0x10106000 0x2000>;
+			#interrupt-cells = <3>;
+			interrupt-controller;
+			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) |
+						 IRQ_TYPE_LEVEL_HIGH)>;
+			#address-cells = <0>;
+			#size-cells = <1>;
+		};
+
+		pinctrl_peric0: pinctrl@10430000 {
+			compatible = "samsung,exynos9810-pinctrl";
+			reg = <0x10430000 0x1000>;
+			interrupts = <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>;
+		};
+
+		pinctrl_peric1: pinctrl@10830000 {
+			compatible = "samsung,exynos9810-pinctrl";
+			reg = <0x10830000 0x1000>;
+			interrupts = <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>;
+		};
+
+		pinctrl_fsys0: pinctrl@11050000 {
+			compatible = "samsung,exynos9810-pinctrl";
+			reg = <0x11050000 0x1000>;
+			interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
+		};
+
+		pinctrl_fsys1: pinctrl@11430000 {
+			compatible = "samsung,exynos9810-pinctrl";
+			reg = <0x11430000 0x1000>;
+			interrupts = <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>;
+		};
+
+		pinctrl_vts: pinctrl@13880000 {
+			compatible = "samsung,exynos9810-pinctrl";
+			reg = <0x13880000 0x1000>;
+		};
+
+		pinctrl_chub: pinctrl@13a80000 {
+			compatible = "samsung,exynos9810-pinctrl";
+			reg = <0x13a80000 0x1000>;
+			interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
+		};
+
+		pinctrl_alive: pinctrl@14050000 {
+			compatible = "samsung,exynos9810-pinctrl";
+			reg = <0x14050000 0x1000>;
+
+			wakeup-interrupt-controller {
+				compatible = "samsung,exynos9810-wakeup-eint",
+					     "samsung,exynos850-wakeup-eint",
+					     "samsung,exynos7-wakeup-eint";
+			};
+		};
+
+		pmu_system_controller: system-controller@14060000 {
+			compatible = "samsung,exynos9810-pmu",
+				     "samsung,exynos7-pmu", "syscon";
+			reg = <0x14060000 0x10000>;
+		};
+
+		pinctrl_cmgp: pinctrl@14220000 {
+			compatible = "samsung,exynos9810-pinctrl";
+			reg = <0x14220000 0x1000>;
+
+			wakeup-interrupt-controller {
+				compatible = "samsung,exynos9810-wakeup-eint",
+					     "samsung,exynos850-wakeup-eint",
+					     "samsung,exynos7-wakeup-eint";
+			};
+		};
+
+		pinctrl_aud: pinctrl@17c60000 {
+			compatible = "samsung,exynos9810-pinctrl";
+			reg = <0x17c60000 0x1000>;
+		};
+	};
+
+	timer {
+		compatible = "arm,armv8-timer";
+		/* Hypervisor Virtual Timer interrupt is not wired to GIC */
+		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
+		/*
+		 * Non-updatable, broken stock Samsung bootloader does not
+		 * configure CNTFRQ_EL0
+		 */
+		clock-frequency = <26000000>;
+	};
+};
+
+#include "exynos9810-pinctrl.dtsi"
+#include "arm/samsung/exynos-syscon-restart.dtsi"
diff --git a/dts/upstream/src/arm64/exynos/exynos990-r8s.dts b/dts/upstream/src/arm64/exynos/exynos990-r8s.dts
new file mode 100644
index 00000000000..6bae3c0ecc1
--- /dev/null
+++ b/dts/upstream/src/arm64/exynos/exynos990-r8s.dts
@@ -0,0 +1,115 @@
+// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
+/*
+ * Samsung Galaxy S20 FE (r8s/SM-G780F) device tree source
+ *
+ * Copyright (c) 2024, Denzeel Oliva <wachiturroxd150@gmail.com>
+ */
+
+/dts-v1/;
+#include "exynos990.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+	model = "Samsung Galaxy S20 FE";
+	compatible = "samsung,r8s", "samsung,exynos990";
+
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	chosen {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		framebuffer0: framebuffer@f1000000 {
+			compatible = "simple-framebuffer";
+			reg = <0 0xf1000000 0 (1080 * 2400 * 4)>;
+			width = <1080>;
+			height = <2400>;
+			stride = <(1080 * 4)>;
+			format = "a8r8g8b8";
+		};
+	};
+
+	memory@80000000 {
+		device_type = "memory";
+		reg = <0x0 0x80000000 0x0 0x3ab00000>,
+		      /* Memory hole */
+		      <0x0 0xc1200000 0x0 0x1ee00000>,
+		      /* Memory hole */
+		      <0x0 0xe1900000 0x0 0x1e700000>,
+		      /* Memory hole - last block */
+		      <0x8 0x80000000 0x0 0xc0000000>;
+	};
+
+	reserved-memory {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		cont_splash_mem: framebuffer@f1000000 {
+			reg = <0 0xf1000000 0 0x13c6800>;
+			no-map;
+		};
+
+		abox_reserved: audio@f7fb0000 {
+			reg = <0 0xf7fb0000 0 0x2a50000>;
+			no-map;
+		};
+	};
+
+	gpio-keys {
+		compatible = "gpio-keys";
+
+		pinctrl-0 = <&key_power &key_voldown &key_volup>;
+		pinctrl-names = "default";
+
+		power-key {
+			label = "Power";
+			linux,code = <KEY_POWER>;
+			gpios = <&gpa2 4 GPIO_ACTIVE_LOW>;
+			wakeup-source;
+		};
+
+		voldown-key {
+			label = "Volume Down";
+			linux,code = <KEY_VOLUMEDOWN>;
+			gpios = <&gpa0 4 GPIO_ACTIVE_LOW>;
+		};
+
+		volup-key {
+			label = "Volume Up";
+			linux,code = <KEY_VOLUMEUP>;
+			gpios = <&gpa0 3 GPIO_ACTIVE_LOW>;
+		};
+	};
+};
+
+&oscclk {
+	clock-frequency = <26000000>;
+};
+
+&pinctrl_alive {
+	key_power: key-power-pins {
+		samsung,pins = "gpa2-4";
+		samsung,pin-function = <EXYNOS_PIN_FUNC_EINT>;
+		samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+		samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
+	};
+
+	key_voldown: key-voldown-pins {
+		samsung,pins = "gpa0-4";
+		samsung,pin-function = <EXYNOS_PIN_FUNC_EINT>;
+		samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+		samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
+	};
+
+	key_volup: key-volup-pins {
+		samsung,pins = "gpa0-3";
+		samsung,pin-function = <EXYNOS_PIN_FUNC_EINT>;
+		samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+		samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
+	};
+};
diff --git a/dts/upstream/src/arm64/exynos/exynos990-x1s-common.dtsi b/dts/upstream/src/arm64/exynos/exynos990-x1s-common.dtsi
new file mode 100644
index 00000000000..55fa8e9e05d
--- /dev/null
+++ b/dts/upstream/src/arm64/exynos/exynos990-x1s-common.dtsi
@@ -0,0 +1,98 @@
+// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
+/*
+ * Samsung Galaxy S20 Series device tree source
+ *
+ * Copyright (c) 2024, Umer Uddin <umer.uddin@mentallysanemainliners.org>
+ */
+
+/dts-v1/;
+#include "exynos990.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+	chosen {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		framebuffer0: framebuffer@f1000000 {
+			compatible = "simple-framebuffer";
+			reg = <0 0xf1000000 0 (1440 * 3200 * 4)>;
+			width = <1440>;
+			height = <3200>;
+			stride = <(1440 * 4)>;
+			format = "a8r8g8b8";
+		};
+	};
+
+	reserved-memory {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		cont_splash_mem: framebuffer@f1000000 {
+			reg = <0 0xf1000000 0 0x1194000>;
+			no-map;
+		};
+
+		abox_reserved: audio@f7fb0000 {
+			reg = <0 0xf7fb0000 0 0x2a50000>;
+			no-map;
+		};
+	};
+
+	gpio-keys {
+		compatible = "gpio-keys";
+
+		pinctrl-0 = <&key_power &key_voldown &key_volup>;
+		pinctrl-names = "default";
+
+		power-key {
+			label = "Power";
+			linux,code = <KEY_POWER>;
+			gpios = <&gpa2 4 GPIO_ACTIVE_LOW>;
+			wakeup-source;
+		};
+
+		voldown-key {
+			label = "Volume Down";
+			linux,code = <KEY_VOLUMEDOWN>;
+			gpios = <&gpa0 4 GPIO_ACTIVE_LOW>;
+		};
+
+		volup-key {
+			label = "Volume Up";
+			linux,code = <KEY_VOLUMEUP>;
+			gpios = <&gpa0 3 GPIO_ACTIVE_LOW>;
+		};
+	};
+};
+
+&oscclk {
+	clock-frequency = <26000000>;
+};
+
+&pinctrl_alive {
+	key_power: key-power-pins {
+		samsung,pins = "gpa2-4";
+		samsung,pin-function = <EXYNOS_PIN_FUNC_EINT>;
+		samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+		samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
+	};
+
+	key_voldown: key-voldown-pins {
+		samsung,pins = "gpa0-4";
+		samsung,pin-function = <EXYNOS_PIN_FUNC_EINT>;
+		samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+		samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
+	};
+
+	key_volup: key-volup-pins {
+		samsung,pins = "gpa0-3";
+		samsung,pin-function = <EXYNOS_PIN_FUNC_EINT>;
+		samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+		samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
+	};
+};
diff --git a/dts/upstream/src/arm64/exynos/exynos990-x1s.dts b/dts/upstream/src/arm64/exynos/exynos990-x1s.dts
new file mode 100644
index 00000000000..1ae881015e0
--- /dev/null
+++ b/dts/upstream/src/arm64/exynos/exynos990-x1s.dts
@@ -0,0 +1,28 @@
+// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
+/*
+ * Samsung Galaxy S20 5G (x1s/SM-G981B) device tree source
+ *
+ * Copyright (c) 2024, Umer Uddin <umer.uddin@mentallysanemainliners.org>
+ */
+
+/dts-v1/;
+#include "exynos990-x1s-common.dtsi"
+
+/ {
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	model = "Samsung Galaxy S20 5G";
+	compatible = "samsung,x1s", "samsung,exynos990";
+
+	memory@80000000 {
+		device_type = "memory";
+		reg = <0x0 0x80000000 0x0 0x3ab00000>,
+		      /* Memory hole */
+		      <0x0 0xc1200000 0x0 0x1ee00000>,
+		      /* Memory hole */
+		      <0x0 0xe1900000 0x0 0x1e700000>,
+		      /* Memory hole */
+		      <0x8 0x80000000 0x2 0x7e800000>;
+	};
+};
diff --git a/dts/upstream/src/arm64/exynos/exynos990-x1slte.dts b/dts/upstream/src/arm64/exynos/exynos990-x1slte.dts
new file mode 100644
index 00000000000..d3720996ba9
--- /dev/null
+++ b/dts/upstream/src/arm64/exynos/exynos990-x1slte.dts
@@ -0,0 +1,28 @@
+// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
+/*
+ * Samsung Galaxy S20 (x1slte/SM-G980F) device tree source
+ *
+ * Copyright (c) 2024, Umer Uddin <umer.uddin@mentallysanemainliners.org>
+ */
+
+/dts-v1/;
+#include "exynos990-x1s-common.dtsi"
+
+/ {
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	model = "Samsung Galaxy S20";
+	compatible = "samsung,x1slte", "samsung,exynos990";
+
+	memory@80000000 {
+		device_type = "memory";
+		reg = <0x0 0x80000000 0x0 0x3ab00000>,
+		      /* Memory hole */
+		      <0x0 0xc1200000 0x0 0x1ee00000>,
+		      /* Memory hole */
+		      <0x0 0xe1900000 0x0 0x1e700000>,
+		      /* Memory hole */
+		      <0x8 0x80000000 0x1 0x7ec00000>;
+	};
+};
diff --git a/dts/upstream/src/arm64/exynos/exynos990.dtsi b/dts/upstream/src/arm64/exynos/exynos990.dtsi
index c1986f00e44..9d017dbed95 100644
--- a/dts/upstream/src/arm64/exynos/exynos990.dtsi
+++ b/dts/upstream/src/arm64/exynos/exynos990.dtsi
@@ -5,6 +5,7 @@
  * Copyright (c) 2024, Igor Belwon <igor.belwon@mentallysanemainliners.org>
  */
 
+#include <dt-bindings/clock/samsung,exynos990.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 
 / {
@@ -46,7 +47,14 @@
 				     <&cpu5>;
 	};
 
-	/* There's no PMU model for cluster2, which are the Mongoose cores. */
+	mongoose-m5-pmu {
+		compatible = "samsung,mongoose-pmu";
+		interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>;
+
+		interrupt-affinity = <&cpu6>,
+				     <&cpu7>;
+	};
 
 	cpus {
 		#address-cells = <1>;
@@ -199,6 +207,23 @@
 			interrupts = <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>;
 		};
 
+		cmu_hsi0: clock-controller@10a00000 {
+			compatible = "samsung,exynos990-cmu-hsi0";
+			reg = <0x10a00000 0x8000>;
+			#clock-cells = <1>;
+
+			clocks = <&oscclk>,
+				 <&cmu_top CLK_DOUT_CMU_HSI0_BUS>,
+				 <&cmu_top CLK_DOUT_CMU_HSI0_USB31DRD>,
+				 <&cmu_top CLK_DOUT_CMU_HSI0_USBDP_DEBUG>,
+				 <&cmu_top CLK_DOUT_CMU_HSI0_DPGTC>;
+			clock-names = "oscclk",
+				      "bus",
+				      "usb31drd",
+				      "usbdp_debug",
+				      "dpgtc";
+		};
+
 		pinctrl_hsi1: pinctrl@13040000 {
 			compatible = "samsung,exynos990-pinctrl";
 			reg = <0x13040000 0x1000>;
@@ -227,10 +252,33 @@
 			};
 		};
 
+		pmu_system_controller: system-controller@15860000 {
+			compatible = "samsung,exynos990-pmu",
+				     "samsung,exynos7-pmu", "syscon";
+			reg = <0x15860000 0x10000>;
+
+			reboot: syscon-reboot {
+				compatible = "syscon-reboot";
+				regmap = <&pmu_system_controller>;
+				offset = <0x3a00>; /* SWRESET */
+				mask = <0x2>; /* SWRESET_TRIGGER */
+				value = <0x2>;
+			};
+		};
+
 		pinctrl_cmgp: pinctrl@15c30000 {
 			compatible = "samsung,exynos990-pinctrl";
 			reg = <0x15c30000 0x1000>;
 		};
+
+		cmu_top: clock-controller@1a330000 {
+			compatible = "samsung,exynos990-cmu-top";
+			reg = <0x1a330000 0x8000>;
+			#clock-cells = <1>;
+
+			clocks = <&oscclk>;
+			clock-names = "oscclk";
+		};
 	};
 
 	timer {
diff --git a/dts/upstream/src/arm64/exynos/exynosautov920.dtsi b/dts/upstream/src/arm64/exynos/exynosautov920.dtsi
index c759134c909..eb446cdc4ab 100644
--- a/dts/upstream/src/arm64/exynos/exynosautov920.dtsi
+++ b/dts/upstream/src/arm64/exynos/exynosautov920.dtsi
@@ -183,6 +183,26 @@
 				      "noc";
 		};
 
+		watchdog_cl0: watchdog@10060000 {
+			compatible = "samsung,exynosautov920-wdt";
+			reg = <0x10060000 0x100>;
+			interrupts = <GIC_SPI 953 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&xtcxo>, <&xtcxo>;
+			clock-names = "watchdog", "watchdog_src";
+			samsung,syscon-phandle = <&pmu_system_controller>;
+			samsung,cluster-index = <0>;
+		};
+
+		watchdog_cl1: watchdog@10070000 {
+			compatible = "samsung,exynosautov920-wdt";
+			reg = <0x10070000 0x100>;
+			interrupts = <GIC_SPI 952 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&xtcxo>, <&xtcxo>;
+			clock-names = "watchdog", "watchdog_src";
+			samsung,syscon-phandle = <&pmu_system_controller>;
+			samsung,cluster-index = <1>;
+		};
+
 		gic: interrupt-controller@10400000 {
 			compatible = "arm,gic-v3";
 			#interrupt-cells = <3>;
@@ -193,6 +213,69 @@
 			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
 		};
 
+		spdma0: dma-controller@10180000 {
+			compatible = "arm,pl330", "arm,primecell";
+			reg = <0x10180000 0x1000>;
+			interrupts = <GIC_SPI 918 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cmu_misc CLK_MOUT_MISC_NOC_USER>;
+			clock-names = "apb_pclk";
+			#dma-cells = <1>;
+		};
+
+		spdma1: dma-controller@10190000 {
+			compatible = "arm,pl330", "arm,primecell";
+			reg = <0x10190000 0x1000>;
+			interrupts = <GIC_SPI 917 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cmu_misc CLK_MOUT_MISC_NOC_USER>;
+			clock-names = "apb_pclk";
+			#dma-cells = <1>;
+		};
+
+		pdma0: dma-controller@101a0000 {
+			compatible = "arm,pl330", "arm,primecell";
+			reg = <0x101a0000 0x1000>;
+			interrupts = <GIC_SPI 916 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cmu_misc CLK_MOUT_MISC_NOC_USER>;
+			clock-names = "apb_pclk";
+			#dma-cells = <1>;
+		};
+
+		pdma1: dma-controller@101b0000 {
+			compatible = "arm,pl330", "arm,primecell";
+			reg = <0x101b0000 0x1000>;
+			interrupts = <GIC_SPI 915 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cmu_misc CLK_MOUT_MISC_NOC_USER>;
+			clock-names = "apb_pclk";
+			#dma-cells = <1>;
+		};
+
+		pdma2: dma-controller@101c0000 {
+			compatible = "arm,pl330", "arm,primecell";
+			reg = <0x101c0000 0x1000>;
+			interrupts = <GIC_SPI 914 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cmu_misc CLK_MOUT_MISC_NOC_USER>;
+			clock-names = "apb_pclk";
+			#dma-cells = <1>;
+		};
+
+		pdma3: dma-controller@101d0000 {
+			compatible = "arm,pl330", "arm,primecell";
+			reg = <0x101d0000 0x1000>;
+			interrupts = <GIC_SPI 913 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cmu_misc CLK_MOUT_MISC_NOC_USER>;
+			clock-names = "apb_pclk";
+			#dma-cells = <1>;
+		};
+
+		pdma4: dma-controller@101e0000 {
+			compatible = "arm,pl330", "arm,primecell";
+			reg = <0x101e0000 0x1000>;
+			interrupts = <GIC_SPI 912 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cmu_misc CLK_MOUT_MISC_NOC_USER>;
+			clock-names = "apb_pclk";
+			#dma-cells = <1>;
+		};
+
 		cmu_peric0: clock-controller@10800000 {
 			compatible = "samsung,exynosautov920-cmu-peric0";
 			reg = <0x10800000 0x8000>;
diff --git a/dts/upstream/src/arm64/exynos/google/gs101-oriole.dts b/dts/upstream/src/arm64/exynos/google/gs101-oriole.dts
index 387fb779bd2..e58881c61d5 100644
--- a/dts/upstream/src/arm64/exynos/google/gs101-oriole.dts
+++ b/dts/upstream/src/arm64/exynos/google/gs101-oriole.dts
@@ -10,6 +10,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/usb/pd.h>
 #include "gs101-pinctrl.h"
 #include "gs101.dtsi"
 
@@ -90,6 +91,89 @@
 &hsi2c_12 {
 	status = "okay";
 	/* TODO: add the devices once drivers exist */
+
+	usb-typec@25 {
+		compatible = "maxim,max77759-tcpci", "maxim,max33359";
+		reg = <0x25>;
+		interrupts-extended = <&gpa8 2 IRQ_TYPE_LEVEL_LOW>;
+		pinctrl-0 = <&typec_int>;
+		pinctrl-names = "default";
+
+		connector {
+			compatible = "usb-c-connector";
+			label = "USB-C";
+			data-role = "dual";
+			power-role = "dual";
+			self-powered;
+			try-power-role = "sink";
+			op-sink-microwatt = <2600000>;
+			slow-charger-loop;
+			/*
+			 * max77759 operating in reverse boost mode (0xA) can
+			 * source up to 1.5A while extboost can only do ~1A.
+			 * Since extboost is the primary path, advertise 900mA.
+			 */
+			source-pdos = <PDO_FIXED(5000, 900,
+						 (PDO_FIXED_SUSPEND
+						  | PDO_FIXED_USB_COMM
+						  | PDO_FIXED_DATA_SWAP
+						  | PDO_FIXED_DUAL_ROLE))>;
+			sink-pdos = <PDO_FIXED(5000, 3000,
+					       (PDO_FIXED_DATA_SWAP
+						| PDO_FIXED_USB_COMM
+						| PDO_FIXED_HIGHER_CAP
+						| PDO_FIXED_DUAL_ROLE))
+				     PDO_FIXED(9000, 2200, 0)
+				     PDO_PPS_APDO(5000, 11000, 3000)>;
+			sink-vdos = <VDO_IDH(1, 1, IDH_PTYPE_PERIPH, 0,
+					     IDH_PTYPE_DFP_HOST, 2, 0x18d1)
+				     VDO_CERT(0x0)
+				     VDO_PRODUCT(0x4ee1, 0x0)
+				     VDO_UFP(UFP_VDO_VER1_2,
+					     (DEV_USB2_CAPABLE
+					      | DEV_USB3_CAPABLE),
+					     UFP_RECEPTACLE, 0,
+					     AMA_VCONN_NOT_REQ, 0,
+					     UFP_ALTMODE_NOT_SUPP,
+					     UFP_USB32_GEN1)
+				     /* padding */ 0
+				     VDO_DFP(DFP_VDO_VER1_1,
+					     (HOST_USB2_CAPABLE
+					      | HOST_USB3_CAPABLE),
+					     DFP_RECEPTACLE, 0)>;
+			sink-vdos-v1 = <VDO_IDH(1, 1, IDH_PTYPE_PERIPH, 0,
+						0, 0, 0x18d1)
+					VDO_CERT(0x0)
+					VDO_PRODUCT(0x4ee1, 0x0)>;
+			/*
+			 * Until bootloader is updated to set those two when
+			 * console is enabled, we disable PD here.
+			 */
+			pd-disable;
+			typec-power-opmode = "default";
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					reg = <0>;
+
+					usbc0_orien_sw: endpoint {
+						remote-endpoint = <&usbdrd31_phy_orien_switch>;
+					};
+				};
+
+				port@1 {
+					reg = <1>;
+
+					usbc0_role_sw: endpoint {
+						remote-endpoint = <&usbdrd31_dwc3_role_switch>;
+					};
+				};
+			};
+		};
+	};
 };
 
 &pinctrl_far_alive {
@@ -106,6 +190,13 @@
 		samsung,pin-pud = <GS101_PIN_PULL_NONE>;
 		samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
 	};
+
+	typec_int: typec-int-pins {
+		samsung,pins = "gpa8-2";
+		samsung,pin-function = <GS101_PIN_FUNC_EINT>;
+		samsung,pin-pud = <GS101_PIN_PULL_UP>;
+		samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
+	};
 };
 
 &pinctrl_gpio_alive {
@@ -142,9 +233,16 @@
 	role-switch-default-mode = "peripheral";
 	maximum-speed = "super-speed-plus";
 	status = "okay";
+
+	port {
+		usbdrd31_dwc3_role_switch: endpoint {
+			remote-endpoint = <&usbc0_role_sw>;
+		};
+	};
 };
 
 &usbdrd31_phy {
+	orientation-switch;
 	/* TODO: Update these once PMIC is implemented */
 	pll-supply = <&reg_placeholder>;
 	dvdd-usb20-supply = <&reg_placeholder>;
@@ -153,6 +251,12 @@
 	vdda-usbdp-supply = <&reg_placeholder>;
 	vddh-usbdp-supply = <&reg_placeholder>;
 	status = "okay";
+
+	port {
+		usbdrd31_phy_orien_switch: endpoint {
+			remote-endpoint = <&usbc0_orien_sw>;
+		};
+	};
 };
 
 &usi_uart {
diff --git a/dts/upstream/src/arm64/exynos/google/gs101.dtsi b/dts/upstream/src/arm64/exynos/google/gs101.dtsi
index 302c5beb224..c5335dd59df 100644
--- a/dts/upstream/src/arm64/exynos/google/gs101.dtsi
+++ b/dts/upstream/src/arm64/exynos/google/gs101.dtsi
@@ -1267,7 +1267,7 @@
 
 		usbdrd31_phy: phy@11100000 {
 			compatible = "google,gs101-usb31drd-phy";
-			reg = <0x11100000 0x0100>,
+			reg = <0x11100000 0x0200>,
 			      <0x110f0000 0x0800>,
 			      <0x110e0000 0x2800>;
 			reg-names = "phy", "pcs", "pma";
@@ -1302,6 +1302,9 @@
 				interrupts = <GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH 0>;
 				phys = <&usbdrd31_phy 0>, <&usbdrd31_phy 1>;
 				phy-names = "usb2-phy", "usb3-phy";
+				snps,has-lpm-erratum;
+				snps,dis_u2_susphy_quirk;
+				snps,dis_u3_susphy_quirk;
 				status = "disabled";
 			};
 		};
diff --git a/dts/upstream/src/arm64/freescale/imx8mm-phg.dts b/dts/upstream/src/arm64/freescale/imx8mm-phg.dts
index 75bbedc6164..a134b183364 100644
--- a/dts/upstream/src/arm64/freescale/imx8mm-phg.dts
+++ b/dts/upstream/src/arm64/freescale/imx8mm-phg.dts
@@ -82,7 +82,7 @@
 	};
 
 	panel {
-		compatible = "panel-lvds";
+		compatible = "auo,g084sn05", "panel-lvds";
 		width-mm = <170>;
 		height-mm = <28>;
 		data-mapping = "jeida-18";
diff --git a/dts/upstream/src/arm64/freescale/imx8mm-verdin-dahlia.dtsi b/dts/upstream/src/arm64/freescale/imx8mm-verdin-dahlia.dtsi
index ce20de25980..3d0b1496813 100644
--- a/dts/upstream/src/arm64/freescale/imx8mm-verdin-dahlia.dtsi
+++ b/dts/upstream/src/arm64/freescale/imx8mm-verdin-dahlia.dtsi
@@ -16,10 +16,10 @@
 			"Headphone Jack", "HPOUTR",
 			"IN2L", "Line In Jack",
 			"IN2R", "Line In Jack",
-			"Headphone Jack", "MICBIAS",
-			"IN1L", "Headphone Jack";
+			"Microphone Jack", "MICBIAS",
+			"IN1L", "Microphone Jack";
 		simple-audio-card,widgets =
-			"Microphone", "Headphone Jack",
+			"Microphone", "Microphone Jack",
 			"Headphone", "Headphone Jack",
 			"Line", "Line In Jack";
 
diff --git a/dts/upstream/src/arm64/freescale/imx8mn-bsh-smm-s2-display.dtsi b/dts/upstream/src/arm64/freescale/imx8mn-bsh-smm-s2-display.dtsi
index 7675583a6b6..98dec3c4206 100644
--- a/dts/upstream/src/arm64/freescale/imx8mn-bsh-smm-s2-display.dtsi
+++ b/dts/upstream/src/arm64/freescale/imx8mn-bsh-smm-s2-display.dtsi
@@ -4,6 +4,34 @@
  */
 
 / {
+	chosen {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		framebuffer-panel0 {
+			compatible = "simple-framebuffer";
+			clocks = <&clk IMX8MN_CLK_DISP_PIXEL_ROOT>, /* lcdif */
+				 <&clk IMX8MN_CLK_DISP_APB_ROOT>,
+				 <&clk IMX8MN_CLK_DISP_AXI_ROOT>,
+				 <&clk IMX8MN_VIDEO_PLL1>,
+				 <&clk IMX8MN_CLK_DISP_AXI_ROOT>, /* pgc_dispmix */
+				 <&clk IMX8MN_CLK_DISP_APB_ROOT>,
+				 <&clk IMX8MN_CLK_DISP_AXI>,
+				 <&clk IMX8MN_CLK_DISP_APB>,
+				 <&clk IMX8MN_SYS_PLL2_1000M>,
+				 <&clk IMX8MN_SYS_PLL1_800M>,
+				 <&clk IMX8MN_CLK_DSI_CORE>, /* mipi_disi */
+				 <&clk IMX8MN_CLK_DSI_PHY_REF>;
+
+			power-domains = <&disp_blk_ctrl IMX8MN_DISPBLK_PD_LCDIF>,
+					<&disp_blk_ctrl IMX8MN_DISPBLK_PD_MIPI_DSI>;
+			dvdd-supply = <&reg_3v3_dvdd>;
+			avdd-supply = <&reg_v3v3_avdd>;
+			status = "disabled";
+		};
+	};
+
 	backlight: backlight {
 		compatible = "pwm-backlight";
 		pwms = <&pwm1 0 700000 0>;	/* 700000 ns = 1337Hz */
diff --git a/dts/upstream/src/arm64/freescale/imx8mp-aristainetos3-adpismarc.dts b/dts/upstream/src/arm64/freescale/imx8mp-aristainetos3-adpismarc.dts
new file mode 100644
index 00000000000..6a688510dad
--- /dev/null
+++ b/dts/upstream/src/arm64/freescale/imx8mp-aristainetos3-adpismarc.dts
@@ -0,0 +1,37 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2024 Heiko Schocher <hs@denx.de>
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include "imx8mp-aristainetos3a-som-v1.dtsi"
+
+&{/} {
+	model = "Aristainetos3 ADLink PI SMARC carrier";
+	compatible = "abb,imx8mp-aristanetos3-adpismarc",
+		     "abb,imx8mp-aristanetos3-som",
+		     "fsl,imx8mp";
+};
+
+&flexcan1 {
+	status = "okay";
+};
+
+&i2c2 {
+	gpio8: pinctrl@3e {
+		compatible = "semtech,sx1509q";
+		reg = <0x3e>;
+
+		#gpio-cells = <2>;
+		#interrupt-cells = <2>;
+		semtech,probe-reset;
+		gpio-controller;
+		interrupt-controller;
+		interrupt-parent = <&gpio6>;
+		interrupts = <1 IRQ_TYPE_EDGE_FALLING>;
+	};
+
+};
diff --git a/dts/upstream/src/arm64/freescale/imx8mp-aristainetos3-helios-lvds.dtso b/dts/upstream/src/arm64/freescale/imx8mp-aristainetos3-helios-lvds.dtso
new file mode 100644
index 00000000000..9d1f3b4ccc7
--- /dev/null
+++ b/dts/upstream/src/arm64/freescale/imx8mp-aristainetos3-helios-lvds.dtso
@@ -0,0 +1,113 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2024 Heiko Schocher <hs@denx.de>
+ */
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/pwm/pwm.h>
+
+/dts-v1/;
+/plugin/;
+
+&{/} {
+	model = "Aristainetos3 helios carrier with LVDS";
+	compatible = "abb,imx8mp-aristanetos3-helios",
+		     "abb,imx8mp-aristanetos3-som",
+		     "fsl,imx8mp";
+
+	panel_lvds: panel-lvds {
+		compatible = "lg,lb070wv8";
+		power-supply = <&reg_vcc_disp>;
+		backlight = <&lvds_backlight>;
+
+		port {
+			in_lvds0: endpoint {
+				remote-endpoint = <&ldb_lvds_ch0>;
+			};
+		};
+	};
+
+	reg_vcc_disp: regulator-disp {
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_lcd0_vcc_en>;
+		compatible = "regulator-fixed";
+		regulator-name = "disp_power_en_2v8";
+		regulator-min-microvolt = <2800000>;
+		regulator-max-microvolt = <2800000>;
+		gpio = <&gpio1 13 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+		regulator-boot-on;
+		regulator-always-on;
+	};
+};
+
+&gpio3 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_gpio3_hog>;
+
+	lvdssel-hog {
+		gpio-hog;
+		gpios = <23 GPIO_ACTIVE_HIGH>;
+		output-low;
+		line-name = "LVDSSEL";
+	};
+};
+
+&hdmi_blk_ctrl {
+	status = "disabled";
+};
+
+&hdmi_pvi {
+	status = "disabled";
+};
+
+&hdmi_tx {
+	status = "disabled";
+};
+
+&hdmi_tx_phy {
+	status = "disabled";
+};
+
+&irqsteer_hdmi {
+	status = "disabled";
+};
+
+&ldb_lvds_ch0 {
+	remote-endpoint = <&in_lvds0>;
+};
+
+&lcdif1 {
+	status = "disabled";
+};
+
+&lcdif2 {
+	status = "okay";
+};
+
+&lcdif3 {
+	status = "disabled";
+};
+
+&lvds_backlight {
+	status = "okay";
+};
+
+&lvds_bridge {
+	/* IMX8MP_CLK_MEDIA_LDB = IMX8MP_CLK_MEDIA_DISP2_PIX * 7 */
+	assigned-clock-rates = <232820000>;
+	status = "okay";
+};
+
+&media_blk_ctrl {
+	/*
+	 * currently it is not possible to let display clocks configure
+	 * automatically, so we need to set them manually
+	 */
+	assigned-clock-rates = <500000000>, <200000000>, <0>,
+		/* IMX8MP_CLK_MEDIA_DISP2_PIX = pixelclk of lvds panel */
+		<33260000>, <0>,
+		/* IMX8MP_VIDEO_PLL1 = IMX8MP_CLK_MEDIA_LDB * 2 */
+		<465640000>;
+};
diff --git a/dts/upstream/src/arm64/freescale/imx8mp-aristainetos3-helios.dts b/dts/upstream/src/arm64/freescale/imx8mp-aristainetos3-helios.dts
new file mode 100644
index 00000000000..a4e649a8239
--- /dev/null
+++ b/dts/upstream/src/arm64/freescale/imx8mp-aristainetos3-helios.dts
@@ -0,0 +1,98 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2024 Heiko Schocher <hs@denx.de>
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/gpio/gpio.h>
+#include "imx8mp-aristainetos3a-som-v1.dtsi"
+
+&{/} {
+	model = "Aristainetos3 helios carrier";
+	compatible = "abb,imx8mp-aristanetos3-helios",
+		     "abb,imx8mp-aristanetos3-som",
+		     "fsl,imx8mp";
+
+	led-controller {
+		compatible = "gpio-leds";
+
+		led-0 {
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_RED>;
+			function-enumerator = <20>;
+			gpios = <&pca6416 12 GPIO_ACTIVE_LOW>;
+			default-state = "off";
+		};
+
+		led-1 {
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_YELLOW>;
+			function-enumerator = <20>;
+			gpios = <&pca6416 13 GPIO_ACTIVE_LOW>;
+			default-state = "off";
+		};
+
+		led-2 {
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_GREEN>;
+			function-enumerator = <20>;
+			gpios = <&pca6416 14 GPIO_ACTIVE_LOW>;
+			default-state = "off";
+		};
+
+		led-3 {
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_BLUE>;
+			function-enumerator = <20>;
+			gpios = <&pca6416 15 GPIO_ACTIVE_LOW>;
+			default-state = "off";
+		};
+	};
+};
+
+&ethphy1 {
+	status = "disabled";
+};
+
+&fec {
+	status = "disabled";
+};
+
+&i2c1 {
+	eeprom@57 {
+		compatible = "atmel,24c64";
+		reg = <0x57>;
+	};
+};
+
+&i2c3 {
+	pca6416: gpio@20 {
+		compatible = "ti,tca6416";
+		reg = <0x20>;
+		gpio-controller;
+		#gpio-cells = <2>;
+		gpio-line-names = "DIN0_CON",
+			"DIN1_CON",
+			"DIN2_CON",
+			"DIN3_CON",
+			"DIN4_CON",
+			"DIN5_CON",
+			"DIN6_CON",
+			"DIN7_CON",
+			"PM102_RES",
+			"COMx_RES",
+			"BPL_RES",
+			"PC_RES",
+			"LED_RED",
+			"LED_YELLOW",
+			"LED_GREEN",
+			"LED_BLUE";
+	};
+
+	rtc@68 {
+		compatible = "st,m41t00";
+		reg = <0x68>;
+	};
+};
diff --git a/dts/upstream/src/arm64/freescale/imx8mp-aristainetos3-proton2s.dts b/dts/upstream/src/arm64/freescale/imx8mp-aristainetos3-proton2s.dts
new file mode 100644
index 00000000000..2a736dbe96b
--- /dev/null
+++ b/dts/upstream/src/arm64/freescale/imx8mp-aristainetos3-proton2s.dts
@@ -0,0 +1,161 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2024 Heiko Schocher <hs@denx.de>
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/leds/common.h>
+#include "imx8mp-aristainetos3a-som-v1.dtsi"
+
+&{/} {
+	model = "Aristainetos3 proton2s carrier";
+	compatible = "abb,imx8mp-aristanetos3-proton2s",
+		     "abb,imx8mp-aristanetos3-som",
+		     "fsl,imx8mp";
+
+	watchdog {
+		/* MAX6371KA */
+		compatible = "linux,wdt-gpio";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_watchdog_gpio>;
+		always-running;
+		gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>;
+		hw_algo = "level";
+		/* Reset triggers in 3..9 seconds */
+		hw_margin_ms = <1500>;
+	};
+};
+
+&ethphy1 {
+	status = "disabled";
+};
+
+&eqos {
+	max-speed = <100>;
+};
+
+&ecspi1{
+	pinctrl-0 = <&pinctrl_ecspi1>;
+	cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
+};
+
+&fec {
+	status = "disabled";
+};
+
+&gpio1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_gpio_proton2s>;
+
+	gpio-line-names =
+		"", "", "", "", "", "", "", "POWER",
+		"", "", "", "", "", "", "", "",
+		"", "", "", "", "", "", "", "",
+		"", "", "", "", "", "", "", "";
+};
+
+&gpio6 {
+	gpio-line-names =
+		"RELAY0", "RELAY1", "RELAY2", "HEATER",
+		"FAN", "SPARE",	"CLEAR", "FAULT",
+		"", "", "", "", "", "", "", "", "";
+};
+
+&i2c2 {
+	tlc59108@40 {
+		compatible = "ti,tlc59108";
+		reg = <0x40>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		led@0 {
+			reg = <0x0>;
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_RED>;
+			function-enumerator = <20>;
+		};
+
+		led@1 {
+			reg = <0x1>;
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_GREEN>;
+			function-enumerator = <20>;
+		};
+
+		led@2 {
+			reg = <0x2>;
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_GREEN>;
+			function-enumerator = <21>;
+		};
+
+		led@3 {
+			reg = <0x3>;
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_RED>;
+			function-enumerator = <21>;
+		};
+
+		led@4 {
+			reg = <0x4>;
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_BLUE>;
+			function-enumerator = <21>;
+		};
+
+		led@5 {
+			reg = <0x5>;
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_RED>;
+			function-enumerator = <22>;
+		};
+
+		led@6 {
+			reg = <0x6>;
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_GREEN>;
+			function-enumerator = <22>;
+		};
+
+		led@7 {
+			reg = <0x7>;
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_BLUE>;
+			function-enumerator = <22>;
+		};
+	};
+
+	rtc1: rtc@68 {
+		compatible = "dallas,ds1339";
+		reg = <0x68>;
+	};
+};
+
+&uart1 {
+	pinctrl-0 = <&pinctrl_uart1>;
+};
+
+&uart2 {
+	pinctrl-0 = <&pinctrl_uart2>;
+};
+
+&uart3 {
+	pinctrl-0 = <&pinctrl_uart3>;
+};
+
+&uart4 {
+	linux,rs485-enabled-at-boot-time;
+	rs485-rts-active-low;
+	rs485-rts-delay = <0 0>;
+	rts-gpios = <&gpio3 9 GPIO_ACTIVE_HIGH>;
+};
+
+&usdhc1 {
+	status = "disabled";
+};
+
+&wdog1 {
+	status = "okay";
+};
diff --git a/dts/upstream/src/arm64/freescale/imx8mp-aristainetos3a-som-v1.dtsi b/dts/upstream/src/arm64/freescale/imx8mp-aristainetos3a-som-v1.dtsi
new file mode 100644
index 00000000000..231e480acfd
--- /dev/null
+++ b/dts/upstream/src/arm64/freescale/imx8mp-aristainetos3a-som-v1.dtsi
@@ -0,0 +1,1107 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2024 Heiko Schocher <hs@denx.de>
+ */
+
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/net/ti-dp83867.h>
+#include <dt-bindings/phy/phy-imx8-pcie.h>
+#include <dt-bindings/pwm/pwm.h>
+#include "imx8mp.dtsi"
+
+/ {
+	model = "ADLINK LEC-iMX8MP-Q-N-4G-32G";
+	compatible = "abb,imx8mp-aristanetos3-som", "fsl,imx8mp";
+
+	aliases {
+		ethernet0 = &eqos;
+		ethernet1 = &fec;
+		mmc0 = &usdhc3;	/* eMMC */
+		mmc1 = &usdhc2;	/* MicroSD */
+	};
+
+	chosen {
+		bootargs = "console=ttymxc1,115200 earlycon=ec_imx6q,0x30890000,115200";
+		stdout-path = &uart2;
+	};
+
+	connector {
+		compatible = "usb-c-connector";
+		label = "USB-C";
+
+		port {
+			usb_dr_connector: endpoint {
+				remote-endpoint = <&usb3_dwc>;
+			};
+		};
+	};
+
+	gpio-leds {
+		compatible = "gpio-leds";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_gpio_led>;
+
+		led-0 {
+			function = LED_FUNCTION_STATUS;
+			color = <LED_COLOR_ID_YELLOW>;
+			function-enumerator = <0>;
+			gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>;
+			default-state = "on";
+		};
+	};
+
+	lvds_backlight: backlight {
+		compatible = "pwm-backlight";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_lvds_bklt_en>;
+		pwms = <&pwm2 0 50000 0>;
+		enable-gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>;
+		brightness-levels = <0 100>;
+		num-interpolated-steps = <100>;
+		default-brightness-level = <80>;
+		status = "disabled";
+	};
+
+	memory@40000000 {
+		device_type = "memory";
+		/* Memory size 512 MiB..8 GiB will be filled by U-Boot */
+		reg = <0x0 0x40000000 0 0x08000000>;
+	};
+
+	pcie0_refclk: clock-pcie-ref {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <100000000>;
+	};
+
+	reg_can1_stby: regulator-can1-stby {
+		compatible = "regulator-fixed";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_flexcan1_reg>;
+		gpio = <&gpio5 5 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+		regulator-max-microvolt = <3300000>;
+		regulator-min-microvolt = <3300000>;
+		regulator-name = "can1-stby";
+	};
+
+	reg_can2_stby: regulator-can2-stby {
+		compatible = "regulator-fixed";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_flexcan2_reg>;
+		enable-active-high;
+		gpio = <&gpio4 27 GPIO_ACTIVE_HIGH>;
+		regulator-max-microvolt = <3300000>;
+		regulator-min-microvolt = <3300000>;
+		regulator-name = "can2-stby";
+	};
+
+	reg_dp83867_2v5: regulator-enet {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpio = <&gpio7 15 GPIO_ACTIVE_HIGH>;
+		regulator-max-microvolt = <1800000>;
+		regulator-min-microvolt = <1800000>;
+		regulator-name = "enet_2v5";
+		regulator-boot-on;
+		regulator-always-on;
+	};
+
+	reg_usb1_host_vbus: regulator-usb1-vbus {
+		compatible = "regulator-fixed";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_usb1_vbus>;
+		enable-active-high;
+		gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>;
+		regulator-max-microvolt = <5000000>;
+		regulator-min-microvolt = <5000000>;
+		regulator-name = "usb1_host_vbus";
+		regulator-always-on;
+	};
+
+	reg_usdhc2_vmmc: regulator-usdhc2-vmmc {
+		compatible = "regulator-fixed";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_usdhc2_vmmc>;
+		enable-active-high;
+		gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; /* SD2_RESET */
+		regulator-max-microvolt = <3300000>;
+		regulator-min-microvolt = <3300000>;
+		regulator-name = "VDD_3V3_SD";
+		off-on-delay-us = <12000>;
+		startup-delay-us = <100>;
+		vin-supply = <&buck4>;
+	};
+};
+
+&A53_0 {
+	cpu-supply = <&buck2>;
+};
+
+&A53_1 {
+	cpu-supply = <&buck2>;
+};
+
+&A53_2 {
+	cpu-supply = <&buck2>;
+};
+
+&A53_3 {
+	cpu-supply = <&buck2>;
+};
+
+&clk {
+	clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>,
+		 <&clk_ext3>, <&clk_ext4>;
+	clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2",
+		      "clk_ext3", "clk_ext4";
+	assigned-clocks = <&clk IMX8MP_CLK_A53_SRC>,
+			  <&clk IMX8MP_CLK_A53_CORE>,
+			  <&clk IMX8MP_CLK_NOC>,
+			  <&clk IMX8MP_CLK_NOC_IO>,
+			  <&clk IMX8MP_CLK_GIC>,
+			  <&clk IMX8MP_CLK_AUDIO_AHB>,
+			  <&clk IMX8MP_CLK_AUDIO_AXI_SRC>,
+			  <&clk IMX8MP_AUDIO_PLL1>,
+			  <&clk IMX8MP_AUDIO_PLL2>,
+			  <&clk IMX8MP_VIDEO_PLL1>;
+};
+
+&ecspi1{
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_ecspi1_cs2>;
+	cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW &gpio1 6 GPIO_ACTIVE_LOW>;
+	status = "okay";
+};
+
+&ecspi2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_ecspi2>;
+	cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
+	status = "okay";
+};
+
+/* eth0 */
+&eqos {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_eqos_rgmii>;
+	phy-handle = <&ethphy0>;
+	phy-mode = "rgmii-id";
+	snps,force_thresh_dma_mode;
+	snps,mtl-tx-config = <&mtl_tx_setup>;
+	snps,mtl-rx-config = <&mtl_rx_setup>;
+	status = "okay";
+
+	mdio {
+		compatible = "snps,dwmac-mdio";
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		ethphy0: eqos-ethernet-phy@0 {
+			compatible = "ethernet-phy-ieee802.3-c22";
+			reg = <0>;
+			ti,rx-internal-delay = <DP83867_RGMIIDCTL_1_75_NS>;
+			ti,tx-internal-delay = <DP83867_RGMIIDCTL_1_75_NS>;
+			ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
+			ti,min-output-impedance;
+			ti,dp83867-rxctrl-strap-quirk;
+			interrupt-parent = <&gpio4>;
+			interrupts = <21 IRQ_TYPE_EDGE_FALLING>;
+			reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
+		};
+	};
+
+	mtl_tx_setup: tx-queues-config {
+		snps,tx-queues-to-use = <5>;
+
+		queue0 {
+			snps,dcb-algorithm;
+			snps,priority = <0x1>;
+		};
+
+		queue1 {
+			snps,dcb-algorithm;
+			snps,priority = <0x2>;
+		};
+
+		queue2 {
+			snps,dcb-algorithm;
+			snps,priority = <0x4>;
+		};
+
+		queue3 {
+			snps,dcb-algorithm;
+			snps,priority = <0x8>;
+		};
+
+		queue4 {
+			snps,dcb-algorithm;
+			snps,priority = <0xf0>;
+		};
+	};
+
+	mtl_rx_setup: rx-queues-config {
+		snps,rx-queues-to-use = <5>;
+
+		queue0 {
+			snps,dcb-algorithm;
+			snps,priority = <0x1>;
+			snps,map-to-dma-channel = <0>;
+		};
+
+		queue1 {
+			snps,dcb-algorithm;
+			snps,priority = <0x2>;
+			snps,map-to-dma-channel = <1>;
+		};
+
+		queue2 {
+			snps,dcb-algorithm;
+			snps,priority = <0x4>;
+			snps,map-to-dma-channel = <2>;
+		};
+
+		queue3 {
+			snps,dcb-algorithm;
+			snps,priority = <0x8>;
+			snps,map-to-dma-channel = <3>;
+		};
+
+		queue4 {
+			snps,dcb-algorithm;
+			snps,priority = <0xf0>;
+			snps,map-to-dma-channel = <4>;
+		};
+	};
+};
+
+/* eth1 */
+&fec {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_fec_rgmii>;
+	phy-handle = <&ethphy1>;
+	phy-mode = "rgmii-id";
+	fsl,magic-packet;
+	status = "okay";
+
+	mdio {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		ethphy1: ethernet-phy@1 {
+			compatible = "ethernet-phy-ieee802.3-c22";
+			reg = <1>;
+			interrupt-parent = <&gpio4>;
+			interrupts = <3 IRQ_TYPE_EDGE_FALLING>;
+			reset-gpio = <&gpio4 2 GPIO_ACTIVE_LOW>;
+			ti,rx-internal-delay = <DP83867_RGMIIDCTL_1_75_NS>;
+			ti,tx-internal-delay = <DP83867_RGMIIDCTL_1_75_NS>;
+			ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
+			ti,min-output-impedance;
+			ti,dp83867-rxctrl-strap-quirk;
+			eee-broken-1000t;
+		};
+	};
+};
+
+&flexcan1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_flexcan1>;
+	xceiver-supply = <&reg_can1_stby>;
+	status = "disabled";
+};
+
+&flexcan2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_flexcan2>;
+	xceiver-supply = <&reg_can1_stby>;
+	status = "disabled";
+};
+
+&hdmi_blk_ctrl {
+	status = "okay";
+};
+
+&hdmi_pvi {
+	status = "okay";
+};
+
+&hdmi_tx {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_hdmi>;
+	status = "okay";
+};
+
+&hdmi_tx_phy {
+	status = "okay";
+};
+
+&i2c1 {
+	clock-frequency = <100000>;
+	pinctrl-names = "default", "gpio";
+	pinctrl-0 = <&pinctrl_i2c1>;
+	pinctrl-1 = <&pinctrl_i2c1_gpio>;
+	scl-gpios = <&gpio5 14 GPIO_ACTIVE_HIGH>;
+	sda-gpios = <&gpio5 15 GPIO_ACTIVE_HIGH>;
+	status = "okay";
+
+	pmic: pmic@25 {
+		compatible = "nxp,pca9450c";
+		reg = <0x25>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_pmic>;
+		interrupt-parent = <&gpio1>;
+		interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
+
+		/*
+		 * i.MX 8M Plus Data Sheet for Consumer Products
+		 * 3.1.4 Operating ranges
+		 * MIMX8ML8CVNKZAB
+		 */
+		regulators {
+			buck1: BUCK1 {	/* VDD_SOC (dual-phase with BUCK3) */
+				regulator-name = "buck1";
+				regulator-min-microvolt = <600000>;
+				regulator-max-microvolt = <2187500>;
+				regulator-ramp-delay = <3125>;
+				regulator-always-on;
+				regulator-boot-on;
+			};
+
+			buck2: BUCK2 {	/* VDD_ARM */
+				regulator-name = "buck2";
+				nxp,dvs-run-voltage = <950000>;
+				nxp,dvs-standby-voltage = <850000>;
+				regulator-min-microvolt = <600000>;
+				regulator-max-microvolt = <2187500>;
+				regulator-ramp-delay = <3125>;
+				regulator-always-on;
+				regulator-boot-on;
+			};
+
+			buck4: BUCK4 {	/* VDD_3V3 */
+				regulator-name = "buck4";
+				regulator-min-microvolt = <600000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+				regulator-boot-on;
+			};
+
+			buck5: BUCK5 {	/* VDD_1V8 */
+				regulator-name = "buck5";
+				regulator-min-microvolt = <600000>;
+				regulator-max-microvolt = <3400000>;
+				regulator-always-on;
+				regulator-boot-on;
+			};
+
+			buck6: BUCK6 {	/* NVCC_DRAM_1V1 */
+				regulator-name = "buck6";
+				regulator-min-microvolt = <600000>;
+				regulator-max-microvolt = <3400000>;
+				regulator-always-on;
+				regulator-boot-on;
+			};
+
+			ldo1: LDO1 {	/* NVCC_SNVS_1V8 */
+				regulator-name = "ldo1";
+				regulator-min-microvolt = <1600000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+				regulator-boot-on;
+			};
+
+			ldo2: LDO2 {	/* VDDA_1V8 */
+				regulator-name = "ldo2";
+				regulator-min-microvolt = <800000>;
+				regulator-max-microvolt = <1150000>;
+				regulator-always-on;
+				regulator-boot-on;
+			};
+
+			ldo3: LDO3 {	/* VDDA_1V8 */
+				regulator-name = "ldo3";
+				regulator-min-microvolt = <800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+				regulator-boot-on;
+			};
+
+			ldo4: LDO4 {	/* PMIC_LDO4 */
+				regulator-name = "ldo4";
+				regulator-min-microvolt = <800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+				regulator-boot-on;
+			};
+
+			ldo5: LDO5 {	/* NVCC_SD2 */
+				regulator-name = "ldo5";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+			};
+		};
+	};
+};
+
+&i2c2 {
+	clock-frequency = <400000>;
+	pinctrl-names = "default", "gpio";
+	pinctrl-0 = <&pinctrl_i2c2>;
+	pinctrl-1 = <&pinctrl_i2c2_gpio>;
+	scl-gpios = <&gpio5 16 GPIO_ACTIVE_HIGH>;
+	sda-gpios = <&gpio5 17 GPIO_ACTIVE_HIGH>;
+	status = "okay";
+};
+
+&i2c3 {
+	clock-frequency = <100000>;
+	pinctrl-names = "default", "gpio";
+	pinctrl-0 = <&pinctrl_i2c3>;
+	pinctrl-1 = <&pinctrl_i2c3_gpio>;
+	scl-gpios = <&gpio5 18 GPIO_ACTIVE_HIGH>;
+	sda-gpios = <&gpio5 19 GPIO_ACTIVE_HIGH>;
+	status = "okay";
+};
+
+&i2c5 {
+	#address-cells = <1>;
+	clock-frequency = <100000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_i2c5>;
+	status = "okay";
+};
+
+&i2c6 {
+	clock-frequency = <100000>;
+	pinctrl-names = "default", "gpio";
+	pinctrl-0 = <&pinctrl_i2c6>;
+	pinctrl-1 = <&pinctrl_i2c6_gpio>;
+	scl-gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>;
+	sda-gpios = <&gpio3 20 GPIO_ACTIVE_HIGH>;
+	status = "okay";
+
+	/* TPM - ST33TPHF2XI2C U2301 */
+	tpm: tpm@2e {
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_tpm_irq>;
+		compatible = "st,st33ktpm2xi2c", "tcg,tpm-tis-i2c";
+		reg = <0x2e>;
+
+		label = "tpm";
+		interrupt-parent = <&gpio3>;
+		interrupts = <14 IRQ_TYPE_LEVEL_LOW>;
+		reset-gpios = <&gpio6 11 GPIO_ACTIVE_LOW>;
+		status = "okay";
+	};
+
+	/* SX1509(0) U2605 */
+	gpio6: pinctrl@3f {
+		compatible = "semtech,sx1509q";
+		reg = <0x3f>;
+		#gpio-cells = <2>;
+		#interrupt-cells = <2>;
+		semtech,probe-reset;
+		gpio-controller;
+		interrupt-controller;
+		interrupt-parent = <&gpio1>;
+		interrupts = <12 IRQ_TYPE_EDGE_FALLING>;
+	};
+
+	/* RTC U2607 */
+	rtc0: rtc@51 {
+		compatible = "nxp,pcf8563";
+		reg = <0x51>;
+		#clock-cells = <0>;
+	};
+
+	/* SX1509(1) U2606 */
+	gpio7: pinctrl@70 {
+		compatible = "semtech,sx1509q";
+		reg = <0x70>;
+		#gpio-cells = <2>;
+		#interrupt-cells = <2>;
+		semtech,probe-reset;
+		gpio-controller;
+		interrupt-controller;
+		interrupt-parent = <&gpio4>;
+		interrupts = <19 IRQ_TYPE_EDGE_FALLING>;
+
+		gpio6-cfg {
+			pins = "gpio6";
+			output-high;
+		};
+
+		gpio7-cfg {
+			pins = "gpio7";
+			output-high;
+		};
+	};
+};
+
+&irqsteer_hdmi {
+	status = "okay";
+};
+
+&lcdif1 {
+	status = "disabled";
+};
+
+&lcdif2 {
+	status = "disabled";
+};
+
+/* HDMI */
+&lcdif3 {
+	status = "okay";
+
+};
+
+&lvds_bridge {
+	status = "disabled";
+};
+
+&mipi_dsi {
+	status = "disabled";
+};
+
+&pcie{
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_pcie>;
+	reset-gpio = <&gpio4 20 GPIO_ACTIVE_LOW>;
+	fsl,tx-deemph-gen1 = <0x1f>;
+	fsl,max-link-speed = <3>;
+	status = "okay";
+};
+
+&pcie_phy{
+	fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
+	clocks = <&pcie0_refclk>;
+	clock-names = "ref";
+	status = "okay";
+};
+
+&pwm1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_pwm1>;
+	status = "okay";
+};
+
+&pwm2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_pwm2>;
+	#pwm-cells = <3>;
+	status = "okay";
+};
+
+&snvs_pwrkey {
+	status = "okay";
+};
+
+&uart1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart1>;
+	status = "okay";
+};
+
+&uart2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart2>;
+	status = "okay";
+};
+
+&uart3 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart3>;
+	status = "okay";
+};
+
+&uart4 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart4>;
+	status = "okay";
+};
+
+&usb3_phy0 {
+	status = "okay";
+};
+
+&usb3_0 {
+	status = "okay";
+};
+
+&usb_dwc3_0 {
+	adp-disable;
+	hnp-disable;
+	srp-disable;
+	dr_mode = "otg";
+	usb-role-switch;
+	role-switch-default-mode = "peripheral";
+	status = "okay";
+
+	port {
+		usb3_dwc: endpoint {
+			remote-endpoint = <&usb_dr_connector>;
+		};
+	};
+};
+
+&usb3_phy1 {
+	status = "okay";
+};
+
+&usb3_1 {
+	status = "okay";
+};
+
+&usb_dwc3_1 {
+	dr_mode = "host";
+	status = "okay";
+};
+
+&usdhc1 {
+	pinctrl-names = "default", "state_100mhz", "state_200mhz";
+	pinctrl-0 = <&pinctrl_usdhc1>;
+	pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
+	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
+	bus-width = <4>;
+	non-removable;
+	status = "okay";
+};
+
+/* SD slot */
+&usdhc2 {
+	pinctrl-names = "default", "state_100mhz", "state_200mhz";
+	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
+	pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
+	pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
+	cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
+	vmmc-supply = <&reg_usdhc2_vmmc>;
+	bus-width = <4>;
+	status = "okay";
+};
+
+/* eMMC */
+&usdhc3 {
+	pinctrl-names = "default", "state_100mhz", "state_200mhz";
+	pinctrl-0 = <&pinctrl_usdhc3>;
+	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
+	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
+	vmmc-supply = <&buck4>;
+	vqmmc-supply = <&buck5>;
+	bus-width = <8>;
+	non-removable;
+	status = "okay";
+};
+
+&wdog1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_wdog>;
+	fsl,ext-reset-output;
+	status = "okay";
+};
+
+&iomuxc {
+	pinctrl_ecspi1: aristainetos3-ecspi1-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_ECSPI1_SCLK__ECSPI1_SCLK		0x82
+			MX8MP_IOMUXC_ECSPI1_MOSI__ECSPI1_MOSI		0x82
+			MX8MP_IOMUXC_ECSPI1_MISO__ECSPI1_MISO		0x82
+			MX8MP_IOMUXC_ECSPI1_SS0__GPIO5_IO09		0x40000
+		>;
+	};
+
+	pinctrl_ecspi1_cs2: aristainetos3-ecspi1-cs2-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06		0x40000
+		>;
+	};
+
+	pinctrl_ecspi2: aristainetos3-ecspi2-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK		0x82
+			MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI		0x82
+			MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO		0x82
+			MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13		0x40000
+		>;
+	};
+
+	pinctrl_eqos_rgmii: aristainetos3-eqos-rgmii-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC				0x3
+			MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO				0x3
+			MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0			0x91
+			MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1			0x91
+			MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2			0x91
+			MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3			0x91
+			MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK	0x91
+			MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL			0x91
+			MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0			0x1f
+			MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1			0x1f
+			MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2			0x1f
+			MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3			0x1f
+			MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL			0x1f
+			MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK	0x1f
+			MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22				0x19
+		>;
+	};
+
+	pinctrl_fec_rgmii: aristainetos3-fec-rgmii-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC		0x3
+			MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO		0x3
+			MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0		0x91
+			MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1		0x91
+			MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2		0x91
+			MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3		0x91
+			MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC		0x91
+			MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL	0x91
+			MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0		0x1f
+			MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1		0x1f
+			MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2		0x1f
+			MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3		0x1f
+			MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL	0x1f
+			MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC		0x1f
+			MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02		0x19
+		>;
+	};
+
+	pinctrl_flexcan1: aristainetos3-flexcan1-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_SPDIF_RX__CAN1_RX			0x154
+			MX8MP_IOMUXC_SPDIF_TX__CAN1_TX			0x154
+		>;
+	};
+
+	pinctrl_flexcan1_reg: aristainetos3-flexcan1-reg-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_SPDIF_EXT_CLK__GPIO5_IO05  0x154
+		>;
+	};
+
+	pinctrl_flexcan2: aristainetos3-flexcan2-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_SAI5_MCLK__CAN2_RX         0x154
+			MX8MP_IOMUXC_SAI5_RXD3__CAN2_TX         0x154
+		>;
+	};
+
+	pinctrl_flexcan2_reg: aristainetos3-flexcan2-reg-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27      0x154
+		>;
+	};
+
+	pinctrl_gpio3_hog: aristainetos3-gpio3-hog-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_SAI5_RXD2__GPIO3_IO23	0xd6
+		>;
+	};
+
+	pinctrl_gpio_led: aristainetos3-gpio-led-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16	0x19
+		>;
+	};
+
+	pinctrl_gpio_proton2s: aristainetos3-gpio-proton2s-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07	0x19
+		>;
+	};
+
+	pinctrl_hdmi: aristainetos3-hdmi-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_HDMI_DDC_SCL__HDMIMIX_HDMI_SCL	0x400001c3
+			MX8MP_IOMUXC_HDMI_DDC_SDA__HDMIMIX_HDMI_SDA	0x400001c3
+			MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD		0x40000019
+			MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_HDMI_CEC		0x40000019
+		>;
+	};
+
+	pinctrl_i2c1: aristainetos3-i2c1-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL		0x400001c3
+			MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA		0x400001c3
+		>;
+	};
+
+	pinctrl_i2c1_gpio: aristainetos3-i2c1-gpio-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14	0x1c3
+			MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15	0x1c3
+		>;
+	};
+
+	pinctrl_i2c2: aristainetos3-i2c2-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL		0x400001c3
+			MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA		0x400001c3
+		>;
+	};
+
+	pinctrl_i2c2_gpio: aristainetos3-i2c2-gpio-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16	0x1c3
+			MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17	0x1c3
+		>;
+	};
+
+	pinctrl_i2c3: aristainetos3-i2c3-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL		0x400001c3
+			MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA		0x400001c3
+		>;
+	};
+
+	pinctrl_i2c3_gpio: aristainetos3-i2c3-gpio-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18	0x1c3
+			MX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19	0x1c3
+		>;
+	};
+
+	pinctrl_i2c5: aristainetos3-i2c5-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_SAI5_RXD0__I2C5_SCL	0x400001c3
+			MX8MP_IOMUXC_SAI5_MCLK__I2C5_SDA	0x400001c3
+		>;
+	};
+
+	pinctrl_i2c6: aristainetos3-i2c6-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_SAI5_RXFS__I2C6_SCL	0x400001c3
+			MX8MP_IOMUXC_SAI5_RXC__I2C6_SDA		0x400001c3
+		>;
+	};
+
+	pinctrl_i2c6_gpio: aristainetos3-i2c6-gpio-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_SAI5_RXFS__GPIO3_IO19	0x1c3
+			MX8MP_IOMUXC_SAI5_RXC__GPIO3_IO20	0x1c3
+		>;
+	};
+
+	pinctrl_lcd0_vcc_en: aristainetos3-lcd0-vcc-en-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_GPIO1_IO13__GPIO1_IO13	0xd6
+		>;
+	};
+
+	pinctrl_lvds_bklt_en: aristainetos3-lvds-bklt-en-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10	0xd6
+		>;
+	};
+
+	pinctrl_pcie: aristainetos3-pcie-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_I2C4_SCL__PCIE_CLKREQ_B	0x61
+			MX8MP_IOMUXC_SAI1_MCLK__GPIO4_IO20	0x41
+		>;
+	};
+
+	pinctrl_pmic: aristainetos3-pmic-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03	0x41
+		>;
+	};
+
+	pinctrl_pwm1: aristainetos3-pwm1-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_GPIO1_IO01__PWM1_OUT	0x116
+		>;
+	};
+
+	pinctrl_pwm2: aristainetos3-pwm2-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_GPIO1_IO11__PWM2_OUT	0x116
+		>;
+	};
+
+	pinctrl_tpm_irq: aristainetos3-tpm-irq-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_NAND_DQS__GPIO3_IO14	0xd6
+		>;
+	};
+
+	pinctrl_uart1: aristainetos3-uart1-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX	0x140
+			MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX	0x140
+		>;
+	};
+
+	pinctrl_uart2: aristainetos3-uart2-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX	0x140
+			MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX	0x140
+			MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06	0x140
+			MX8MP_IOMUXC_SD1_DATA5__UART2_DCE_CTS	0x140
+		>;
+	};
+
+	pinctrl_uart3: aristainetos3-uart3-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_NAND_ALE__UART3_DCE_RX	0x140
+			MX8MP_IOMUXC_NAND_CE0_B__UART3_DCE_TX	0x140
+		>;
+	};
+
+	pinctrl_uart4: aristainetos3-uart4-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX    0x140
+			MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX    0x140
+			MX8MP_IOMUXC_NAND_DATA03__GPIO3_IO09	0x140
+			MX8MP_IOMUXC_NAND_DATA02__UART4_DCE_CTS 0x140
+		>;
+	};
+
+	pinctrl_usb1_vbus: aristainetos3-usb1-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_GPIO1_IO14__GPIO1_IO14	0x19
+		>;
+	};
+
+	pinctrl_usdhc1: aristainetos3-usdhc1-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK	0x190
+			MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD	0x1d0
+			MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0	0x1d0
+			MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1	0x1d0
+			MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2	0x1d0
+			MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3	0x1d0
+		>;
+	};
+
+	pinctrl_usdhc1_100mhz: aristainetos3-usdhc1-100mhz-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK	0x194
+			MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD	0x1d4
+			MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0	0x1d4
+			MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1	0x1d4
+			MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2	0x1d4
+			MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3	0x1d4
+		>;
+	};
+
+	pinctrl_usdhc1_200mhz: aristainetos3-usdhc1-200mhz-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK	0x196
+			MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD	0x1d6
+			MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0	0x1d6
+			MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1	0x1d6
+			MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2	0x1d6
+			MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3	0x1d6
+		>;
+	};
+
+	pinctrl_usdhc2: aristainetos3-usdhc2-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK	0x190
+			MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD	0x1d0
+			MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0	0x1d0
+			MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1	0x1d0
+			MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2	0x1d0
+			MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3	0x1d0
+			MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT	0xc1
+
+		>;
+	};
+
+	pinctrl_usdhc2_100mhz: aristainetos3-usdhc2-100mhz-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK	0x194
+			MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD	0x1d4
+			MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0	0x1d4
+			MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1	0x1d4
+			MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2	0x1d4
+			MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3	0x1d4
+			MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
+		>;
+	};
+
+	pinctrl_usdhc2_200mhz: aristainetos3-usdhc2-200mhz-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK	0x196
+			MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD	0x1d6
+			MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0	0x1d6
+			MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1	0x1d6
+			MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2	0x1d6
+			MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3	0x1d6
+			MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
+		>;
+	};
+
+	pinctrl_usdhc2_gpio: aristainetos3-usdhc2-gpio-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12	0x40000080
+		>;
+	};
+
+	pinctrl_usdhc2_vmmc: aristainetos3-usdhc2-vmmc-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19	0x41
+		>;
+	};
+
+	pinctrl_usdhc3: aristainetos3-usdhc3-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK	0x190
+			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD	0x1d0
+			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0	0x1d0
+			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1	0x1d0
+			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2	0x1d0
+			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3	0x1d0
+			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4	0x1d0
+			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5	0x1d0
+			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6	0x1d0
+			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7	0x1d0
+			MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE	0x190
+		>;
+	};
+
+	pinctrl_usdhc3_100mhz: aristainetos3-usdhc3-100mhz-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK	0x194
+			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD	0x1d4
+			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0	0x1d4
+			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1	0x1d4
+			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2	0x1d4
+			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3	0x1d4
+			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4	0x1d4
+			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5	0x1d4
+			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6	0x1d4
+			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7	0x1d4
+			MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE	0x194
+		>;
+	};
+
+	pinctrl_usdhc3_200mhz: aristainetos3-usdhc3-200mhz-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK	0x196
+			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD	0x1d6
+			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0	0x1d6
+			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1	0x1d6
+			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2	0x1d6
+			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3	0x1d6
+			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4	0x1d6
+			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5	0x1d6
+			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6	0x1d6
+			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7	0x1d6
+			MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE	0x196
+		>;
+	};
+
+	pinctrl_watchdog_gpio: aristainetos3-wdog-gpio-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06	0x19
+		>;
+	};
+
+	pinctrl_wdog: aristainetos3-wdog-grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B	0xc6
+		>;
+	};
+};
diff --git a/dts/upstream/src/arm64/freescale/imx8mp-evk-imx-lvds-hdmi-common.dtsi b/dts/upstream/src/arm64/freescale/imx8mp-evk-imx-lvds-hdmi-common.dtsi
new file mode 100644
index 00000000000..44b30e9b3fd
--- /dev/null
+++ b/dts/upstream/src/arm64/freescale/imx8mp-evk-imx-lvds-hdmi-common.dtsi
@@ -0,0 +1,29 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2024 NXP
+ */
+
+/dts-v1/;
+/plugin/;
+
+&{/} {
+	lvds-hdmi-connector {
+		compatible = "hdmi-connector";
+		label = "J2";
+		type = "a";
+
+		port {
+			lvds2hdmi_connector_in: endpoint {
+				remote-endpoint = <&it6263_out>;
+			};
+		};
+	};
+};
+
+&lcdif2 {
+	status = "okay";
+};
+
+&lvds_bridge {
+	status = "okay";
+};
diff --git a/dts/upstream/src/arm64/freescale/imx8mp-evk-lvds0-imx-dlvds-hdmi-channel0.dtso b/dts/upstream/src/arm64/freescale/imx8mp-evk-lvds0-imx-dlvds-hdmi-channel0.dtso
new file mode 100644
index 00000000000..4008d2fd36d
--- /dev/null
+++ b/dts/upstream/src/arm64/freescale/imx8mp-evk-lvds0-imx-dlvds-hdmi-channel0.dtso
@@ -0,0 +1,44 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2024 NXP
+ */
+
+#include "imx8mp-evk-lvds0-imx-lvds-hdmi-common.dtsi"
+
+&it6263 {
+	ports {
+		port@0 {
+			reg = <0>;
+			dual-lvds-odd-pixels;
+
+			it6263_lvds_link1: endpoint {
+				remote-endpoint = <&ldb_lvds_ch0>;
+			};
+		};
+
+		port@1 {
+			reg = <1>;
+			dual-lvds-even-pixels;
+
+			it6263_lvds_link2: endpoint {
+				remote-endpoint = <&ldb_lvds_ch1>;
+			};
+		};
+	};
+};
+
+&lvds_bridge {
+	ports {
+		port@1 {
+			ldb_lvds_ch0: endpoint {
+				remote-endpoint = <&it6263_lvds_link1>;
+			};
+		};
+
+		port@2 {
+			ldb_lvds_ch1: endpoint {
+				remote-endpoint = <&it6263_lvds_link2>;
+			};
+		};
+	};
+};
diff --git a/dts/upstream/src/arm64/freescale/imx8mp-evk-lvds0-imx-lvds-hdmi-common.dtsi b/dts/upstream/src/arm64/freescale/imx8mp-evk-lvds0-imx-lvds-hdmi-common.dtsi
new file mode 100644
index 00000000000..6eae7477abf
--- /dev/null
+++ b/dts/upstream/src/arm64/freescale/imx8mp-evk-lvds0-imx-lvds-hdmi-common.dtsi
@@ -0,0 +1,43 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2024 NXP
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include "imx8mp-evk-imx-lvds-hdmi-common.dtsi"
+
+&i2c2 {
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	it6263: hdmi@4c {
+		compatible = "ite,it6263";
+		reg = <0x4c>;
+		data-mapping = "jeida-24";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_lvds_en>;
+		reset-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;
+		ivdd-supply = <&reg_buck5>;
+		ovdd-supply = <&reg_vext_3v3>;
+		txavcc18-supply = <&reg_buck5>;
+		txavcc33-supply = <&reg_vext_3v3>;
+		pvcc1-supply = <&reg_buck5>;
+		pvcc2-supply = <&reg_buck5>;
+		avcc-supply = <&reg_vext_3v3>;
+		anvdd-supply = <&reg_buck5>;
+		apvdd-supply = <&reg_buck5>;
+
+		ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@2 {
+				reg = <2>;
+
+				it6263_out: endpoint {
+					remote-endpoint = <&lvds2hdmi_connector_in>;
+				};
+			};
+		};
+	};
+};
diff --git a/dts/upstream/src/arm64/freescale/imx8mp-evk-lvds0-imx-lvds-hdmi.dtso b/dts/upstream/src/arm64/freescale/imx8mp-evk-lvds0-imx-lvds-hdmi.dtso
new file mode 100644
index 00000000000..9e11f261ad1
--- /dev/null
+++ b/dts/upstream/src/arm64/freescale/imx8mp-evk-lvds0-imx-lvds-hdmi.dtso
@@ -0,0 +1,28 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2024 NXP
+ */
+
+#include "imx8mp-evk-lvds0-imx-lvds-hdmi-common.dtsi"
+
+&it6263 {
+	ports {
+		port@0 {
+			reg = <0>;
+
+			it6263_lvds_link1: endpoint {
+				remote-endpoint = <&ldb_lvds_ch0>;
+			};
+		};
+	};
+};
+
+&lvds_bridge {
+	ports {
+		port@1 {
+			ldb_lvds_ch0: endpoint {
+				remote-endpoint = <&it6263_lvds_link1>;
+			};
+		};
+	};
+};
diff --git a/dts/upstream/src/arm64/freescale/imx8mp-evk-lvds1-imx-dlvds-hdmi-channel0.dtso b/dts/upstream/src/arm64/freescale/imx8mp-evk-lvds1-imx-dlvds-hdmi-channel0.dtso
new file mode 100644
index 00000000000..af2e73e36a1
--- /dev/null
+++ b/dts/upstream/src/arm64/freescale/imx8mp-evk-lvds1-imx-dlvds-hdmi-channel0.dtso
@@ -0,0 +1,44 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2024 NXP
+ */
+
+#include "imx8mp-evk-lvds1-imx-lvds-hdmi-common.dtsi"
+
+&it6263 {
+	ports {
+		port@0 {
+			reg = <0>;
+			dual-lvds-even-pixels;
+
+			it6263_lvds_link1: endpoint {
+				remote-endpoint = <&ldb_lvds_ch1>;
+			};
+		};
+
+		port@1 {
+			reg = <1>;
+			dual-lvds-odd-pixels;
+
+			it6263_lvds_link2: endpoint {
+				remote-endpoint = <&ldb_lvds_ch0>;
+			};
+		};
+	};
+};
+
+&lvds_bridge {
+	ports {
+		port@1 {
+			ldb_lvds_ch0: endpoint {
+				remote-endpoint = <&it6263_lvds_link2>;
+			};
+		};
+
+		port@2 {
+			ldb_lvds_ch1: endpoint {
+				remote-endpoint = <&it6263_lvds_link1>;
+			};
+		};
+	};
+};
diff --git a/dts/upstream/src/arm64/freescale/imx8mp-evk-lvds1-imx-lvds-hdmi-common.dtsi b/dts/upstream/src/arm64/freescale/imx8mp-evk-lvds1-imx-lvds-hdmi-common.dtsi
new file mode 100644
index 00000000000..8cc9d361c2a
--- /dev/null
+++ b/dts/upstream/src/arm64/freescale/imx8mp-evk-lvds1-imx-lvds-hdmi-common.dtsi
@@ -0,0 +1,43 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2024 NXP
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include "imx8mp-evk-imx-lvds-hdmi-common.dtsi"
+
+&i2c3 {
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	it6263: hdmi@4c {
+		compatible = "ite,it6263";
+		reg = <0x4c>;
+		data-mapping = "jeida-24";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_lvds_en>;
+		reset-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;
+		ivdd-supply = <&reg_buck5>;
+		ovdd-supply = <&reg_vext_3v3>;
+		txavcc18-supply = <&reg_buck5>;
+		txavcc33-supply = <&reg_vext_3v3>;
+		pvcc1-supply = <&reg_buck5>;
+		pvcc2-supply = <&reg_buck5>;
+		avcc-supply = <&reg_vext_3v3>;
+		anvdd-supply = <&reg_buck5>;
+		apvdd-supply = <&reg_buck5>;
+
+		ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@2 {
+				reg = <2>;
+
+				it6263_out: endpoint {
+					remote-endpoint = <&lvds2hdmi_connector_in>;
+				};
+			};
+		};
+	};
+};
diff --git a/dts/upstream/src/arm64/freescale/imx8mp-evk-lvds1-imx-lvds-hdmi.dtso b/dts/upstream/src/arm64/freescale/imx8mp-evk-lvds1-imx-lvds-hdmi.dtso
new file mode 100644
index 00000000000..527a893a71b
--- /dev/null
+++ b/dts/upstream/src/arm64/freescale/imx8mp-evk-lvds1-imx-lvds-hdmi.dtso
@@ -0,0 +1,28 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2024 NXP
+ */
+
+#include "imx8mp-evk-lvds1-imx-lvds-hdmi-common.dtsi"
+
+&it6263 {
+	ports {
+		port@0 {
+			reg = <0>;
+
+			it6263_lvds_link1: endpoint {
+				remote-endpoint = <&ldb_lvds_ch1>;
+			};
+		};
+	};
+};
+
+&lvds_bridge {
+	ports {
+		port@2 {
+			ldb_lvds_ch1: endpoint {
+				remote-endpoint = <&it6263_lvds_link1>;
+			};
+		};
+	};
+};
diff --git a/dts/upstream/src/arm64/freescale/imx8mp-evk.dts b/dts/upstream/src/arm64/freescale/imx8mp-evk.dts
index d26930f1a9e..68e12a752ed 100644
--- a/dts/upstream/src/arm64/freescale/imx8mp-evk.dts
+++ b/dts/upstream/src/arm64/freescale/imx8mp-evk.dts
@@ -938,6 +938,12 @@
 		>;
 	};
 
+	pinctrl_lvds_en: lvdsengrp {
+		fsl,pins = <
+			MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10	0x1c0
+		>;
+	};
+
 	pinctrl_pcie0: pcie0grp {
 		fsl,pins = <
 			MX8MP_IOMUXC_I2C4_SCL__PCIE_CLKREQ_B	0x60 /* open drain, pull up */
diff --git a/dts/upstream/src/arm64/freescale/imx8mp-skov-revb-mi1010ait-1cp1.dts b/dts/upstream/src/arm64/freescale/imx8mp-skov-revb-mi1010ait-1cp1.dts
index 30962922b36..2c75da5f064 100644
--- a/dts/upstream/src/arm64/freescale/imx8mp-skov-revb-mi1010ait-1cp1.dts
+++ b/dts/upstream/src/arm64/freescale/imx8mp-skov-revb-mi1010ait-1cp1.dts
@@ -52,7 +52,7 @@
 
 &lvds_bridge {
 	/* IMX8MP_CLK_MEDIA_LDB = IMX8MP_CLK_MEDIA_DISP2_PIX * 7 */
-	assigned-clock-rates = <482300000>;
+	assigned-clock-rates = <490000000>;
 	status = "okay";
 
 	ports {
@@ -70,10 +70,10 @@
 	 */
 	assigned-clock-rates = <500000000>, <200000000>, <0>,
 		/* IMX8MP_CLK_MEDIA_DISP2_PIX = pixelclk of lvds panel */
-		<68900000>,
+		<70000000>,
 		<500000000>,
-		/* IMX8MP_VIDEO_PLL1 = IMX8MP_CLK_MEDIA_LDB * 2 */
-		<964600000>;
+		/* IMX8MP_VIDEO_PLL1 = IMX8MP_CLK_MEDIA_LDB */
+		<490000000>;
 };
 
 &pwm4 {
diff --git a/dts/upstream/src/arm64/freescale/imx8mp-tqma8mpql.dtsi b/dts/upstream/src/arm64/freescale/imx8mp-tqma8mpql.dtsi
index 336785a9fba..3ddc5aaa7c5 100644
--- a/dts/upstream/src/arm64/freescale/imx8mp-tqma8mpql.dtsi
+++ b/dts/upstream/src/arm64/freescale/imx8mp-tqma8mpql.dtsi
@@ -1,7 +1,8 @@
 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
 /*
- * Copyright 2021-2022 TQ-Systems GmbH
- * Author: Alexander Stein <alexander.stein@tq-group.com>
+ * Copyright 2021-2025 TQ-Systems GmbH <linux@ew.tq-group.com>,
+ * D-82229 Seefeld, Germany.
+ * Author: Alexander Stein
  */
 
 #include "imx8mp.dtsi"
@@ -23,15 +24,6 @@
 		regulator-max-microvolt = <3300000>;
 		regulator-always-on;
 	};
-
-	/* e-MMC IO, needed for HS modes */
-	reg_vcc1v8: regulator-vcc1v8 {
-		compatible = "regulator-fixed";
-		regulator-name = "VCC1V8";
-		regulator-min-microvolt = <1800000>;
-		regulator-max-microvolt = <1800000>;
-		regulator-always-on;
-	};
 };
 
 &A53_0 {
@@ -197,7 +189,7 @@
 	no-sd;
 	no-sdio;
 	vmmc-supply = <&reg_vcc3v3>;
-	vqmmc-supply = <&reg_vcc1v8>;
+	vqmmc-supply = <&buck5_reg>;
 	status = "okay";
 };
 
diff --git a/dts/upstream/src/arm64/freescale/imx8mp-verdin-dahlia.dtsi b/dts/upstream/src/arm64/freescale/imx8mp-verdin-dahlia.dtsi
index da8902c5f7e..1493319aa74 100644
--- a/dts/upstream/src/arm64/freescale/imx8mp-verdin-dahlia.dtsi
+++ b/dts/upstream/src/arm64/freescale/imx8mp-verdin-dahlia.dtsi
@@ -28,10 +28,10 @@
 			"Headphone Jack", "HPOUTR",
 			"IN2L", "Line In Jack",
 			"IN2R", "Line In Jack",
-			"Headphone Jack", "MICBIAS",
-			"IN1L", "Headphone Jack";
+			"Microphone Jack", "MICBIAS",
+			"IN1L", "Microphone Jack";
 		simple-audio-card,widgets =
-			"Microphone", "Headphone Jack",
+			"Microphone", "Microphone Jack",
 			"Headphone", "Headphone Jack",
 			"Line", "Line In Jack";
 
diff --git a/dts/upstream/src/arm64/freescale/imx8mq-librem5-devkit.dts b/dts/upstream/src/arm64/freescale/imx8mq-librem5-devkit.dts
index b268ba7a0e1..9d8e7231b7c 100644
--- a/dts/upstream/src/arm64/freescale/imx8mq-librem5-devkit.dts
+++ b/dts/upstream/src/arm64/freescale/imx8mq-librem5-devkit.dts
@@ -172,7 +172,7 @@
 			"Headphones", "HP_OUT",
 			"Builtin Speaker", "Speaker Amp OUTR",
 			"Speaker Amp INR", "LINE_OUT";
-		simple-audio-card,hp-det-gpio = <&gpio3 20 GPIO_ACTIVE_HIGH>;
+		simple-audio-card,hp-det-gpios = <&gpio3 20 GPIO_ACTIVE_HIGH>;
 
 		simple-audio-card,cpu {
 			sound-dai = <&sai2>;
diff --git a/dts/upstream/src/arm64/freescale/imx8mq-librem5.dtsi b/dts/upstream/src/arm64/freescale/imx8mq-librem5.dtsi
index 1b39514d5c1..bb37a32ce46 100644
--- a/dts/upstream/src/arm64/freescale/imx8mq-librem5.dtsi
+++ b/dts/upstream/src/arm64/freescale/imx8mq-librem5.dtsi
@@ -241,7 +241,7 @@
 			"Headset Mic", "MICBIAS",
 			"IN3R", "Headset Mic",
 			"DMICDAT", "Digital Mic";
-		simple-audio-card,hp-det-gpio = <&gpio3 9 GPIO_ACTIVE_HIGH>;
+		simple-audio-card,hp-det-gpios = <&gpio3 9 GPIO_ACTIVE_HIGH>;
 
 		simple-audio-card,cpu {
 			sound-dai = <&sai2>;
diff --git a/dts/upstream/src/arm64/freescale/imx8mq-zii-ultra.dtsi b/dts/upstream/src/arm64/freescale/imx8mq-zii-ultra.dtsi
index 0c960efd9b3..c7bbba45f36 100644
--- a/dts/upstream/src/arm64/freescale/imx8mq-zii-ultra.dtsi
+++ b/dts/upstream/src/arm64/freescale/imx8mq-zii-ultra.dtsi
@@ -517,8 +517,6 @@
 		eeprom@a4 {
 			compatible = "zii,rave-sp-eeprom";
 			reg = <0xa4 0x4000>;
-			#address-cells = <1>;
-			#size-cells = <1>;
 			zii,eeprom-name = "main-eeprom";
 		};
 	};
diff --git a/dts/upstream/src/arm64/freescale/imx93-11x11-evk.dts b/dts/upstream/src/arm64/freescale/imx93-11x11-evk.dts
index 0e12dcd0d4d..8491eb53120 100644
--- a/dts/upstream/src/arm64/freescale/imx93-11x11-evk.dts
+++ b/dts/upstream/src/arm64/freescale/imx93-11x11-evk.dts
@@ -595,6 +595,9 @@
 };
 
 &wdog3 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_wdog>;
+	fsl,ext-reset-output;
 	status = "okay";
 };
 
@@ -932,4 +935,9 @@
 		>;
 	};
 
+	pinctrl_wdog: wdoggrp {
+		fsl,pins = <
+			MX93_PAD_WDOG_ANY__WDOG1_WDOG_ANY	0x31e
+		>;
+	};
 };
diff --git a/dts/upstream/src/arm64/freescale/imx93-14x14-evk.dts b/dts/upstream/src/arm64/freescale/imx93-14x14-evk.dts
index 236a44c1782..f556b6569a6 100644
--- a/dts/upstream/src/arm64/freescale/imx93-14x14-evk.dts
+++ b/dts/upstream/src/arm64/freescale/imx93-14x14-evk.dts
@@ -219,6 +219,89 @@
 		interrupt-parent = <&gpio3>;
 		interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
 	};
+
+	pmic@25 {
+		compatible = "nxp,pca9452";
+		reg = <0x25>;
+		interrupt-parent = <&pcal6524>;
+		interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
+
+		regulators {
+			buck1: BUCK1 {
+				regulator-name = "BUCK1";
+				regulator-min-microvolt = <610000>;
+				regulator-max-microvolt = <950000>;
+				regulator-boot-on;
+				regulator-always-on;
+				regulator-ramp-delay = <3125>;
+			};
+
+			buck2: BUCK2 {
+				regulator-name = "BUCK2";
+				regulator-min-microvolt = <600000>;
+				regulator-max-microvolt = <670000>;
+				regulator-boot-on;
+				regulator-always-on;
+				regulator-ramp-delay = <3125>;
+			};
+
+			buck4: BUCK4{
+				regulator-name = "BUCK4";
+				regulator-min-microvolt = <1620000>;
+				regulator-max-microvolt = <3400000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			buck5: BUCK5{
+				regulator-name = "BUCK5";
+				regulator-min-microvolt = <1620000>;
+				regulator-max-microvolt = <3400000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			buck6: BUCK6 {
+				regulator-name = "BUCK6";
+				regulator-min-microvolt = <1060000>;
+				regulator-max-microvolt = <1140000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			ldo1: LDO1 {
+				regulator-name = "LDO1";
+				regulator-min-microvolt = <1620000>;
+				regulator-max-microvolt = <1980000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			ldo3: LDO3 {
+				regulator-name = "LDO3";
+				regulator-min-microvolt = <1710000>;
+				regulator-max-microvolt = <1890000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			ldo4: LDO4 {
+				regulator-name = "LDO4";
+				regulator-min-microvolt = <800000>;
+				regulator-max-microvolt = <840000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			ldo5: LDO5 {
+				regulator-name = "LDO5";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+		};
+	};
 };
 
 &lpi2c3 {
@@ -284,6 +367,9 @@
 };
 
 &wdog3 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_wdog>;
+	fsl,ext-reset-output;
 	status = "okay";
 };
 
@@ -465,4 +551,10 @@
 			MX93_PAD_SD2_VSELECT__USDHC2_VSELECT	0x51e
 		>;
 	};
+
+	pinctrl_wdog: wdoggrp {
+		fsl,pins = <
+			MX93_PAD_WDOG_ANY__WDOG1_WDOG_ANY	0x31e
+		>;
+	};
 };
diff --git a/dts/upstream/src/arm64/freescale/imx93-9x9-qsb.dts b/dts/upstream/src/arm64/freescale/imx93-9x9-qsb.dts
index 20ec5b3c21f..75e67115d52 100644
--- a/dts/upstream/src/arm64/freescale/imx93-9x9-qsb.dts
+++ b/dts/upstream/src/arm64/freescale/imx93-9x9-qsb.dts
@@ -221,6 +221,11 @@
 		>;
 	};
 
+	p3t1085: temperature-sensor@48 {
+		compatible = "nxp,p3t1085";
+		reg = <0x48>;
+	};
+
 	ptn5110: tcpc@50 {
 		compatible = "nxp,ptn5110", "tcpci";
 		reg = <0x50>;
@@ -454,6 +459,9 @@
 };
 
 &wdog3 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_wdog>;
+	fsl,ext-reset-output;
 	status = "okay";
 };
 
@@ -641,4 +649,10 @@
 			MX93_PAD_SD2_VSELECT__USDHC2_VSELECT	0x51e
 		>;
 	};
+
+	pinctrl_wdog: wdoggrp {
+		fsl,pins = <
+			MX93_PAD_WDOG_ANY__WDOG1_WDOG_ANY	0x31e
+		>;
+	};
 };
diff --git a/dts/upstream/src/arm64/freescale/imx93-tqma9352-mba93xxca.dts b/dts/upstream/src/arm64/freescale/imx93-tqma9352-mba93xxca.dts
index 599df32976e..8e939d716aa 100644
--- a/dts/upstream/src/arm64/freescale/imx93-tqma9352-mba93xxca.dts
+++ b/dts/upstream/src/arm64/freescale/imx93-tqma9352-mba93xxca.dts
@@ -627,8 +627,8 @@
 		fsl,pins = <
 			/* PD | FSEL_2 | DSE X4 */
 			MX93_PAD_ENET1_MDC__ENET_QOS_MDC			0x51e
-			/* SION | HYS | FSEL_2 | DSE X4 */
-			MX93_PAD_ENET1_MDIO__ENET_QOS_MDIO			0x4000111e
+			/* SION | HYS | ODE | FSEL_2 | DSE X4 */
+			MX93_PAD_ENET1_MDIO__ENET_QOS_MDIO			0x4000191e
 			/* HYS | FSEL_0 | DSE no drive */
 			MX93_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0			0x1000
 			MX93_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1			0x1000
@@ -659,8 +659,8 @@
 		fsl,pins = <
 			/* PD | FSEL_2 | DSE X4 */
 			MX93_PAD_ENET2_MDC__ENET1_MDC			0x51e
-			/* SION | HYS | FSEL_2 | DSE X4 */
-			MX93_PAD_ENET2_MDIO__ENET1_MDIO			0x4000111e
+			/* SION | HYS | ODE | FSEL_2 | DSE X4 */
+			MX93_PAD_ENET2_MDIO__ENET1_MDIO			0x4000191e
 			/* HYS | FSEL_0 | DSE no drive */
 			MX93_PAD_ENET2_RD0__ENET1_RGMII_RD0		0x1000
 			MX93_PAD_ENET2_RD1__ENET1_RGMII_RD1		0x1000
diff --git a/dts/upstream/src/arm64/freescale/imx93-tqma9352-mba93xxla.dts b/dts/upstream/src/arm64/freescale/imx93-tqma9352-mba93xxla.dts
index 0b4b3bb866d..2e953a05c59 100644
--- a/dts/upstream/src/arm64/freescale/imx93-tqma9352-mba93xxla.dts
+++ b/dts/upstream/src/arm64/freescale/imx93-tqma9352-mba93xxla.dts
@@ -597,8 +597,8 @@
 		fsl,pins = <
 			/* PD | FSEL_2 | DSE X4 */
 			MX93_PAD_ENET1_MDC__ENET_QOS_MDC			0x51e
-			/* SION | HYS | FSEL_2 | DSE X4 */
-			MX93_PAD_ENET1_MDIO__ENET_QOS_MDIO			0x4000111e
+			/* SION | HYS | ODE | FSEL_2 | DSE X4 */
+			MX93_PAD_ENET1_MDIO__ENET_QOS_MDIO			0x4000191e
 			/* HYS | FSEL_0 | DSE no drive */
 			MX93_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0			0x1000
 			MX93_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1			0x1000
@@ -629,8 +629,8 @@
 		fsl,pins = <
 			/* PD | FSEL_2 | DSE X4 */
 			MX93_PAD_ENET2_MDC__ENET1_MDC			0x51e
-			/* SION | HYS | FSEL_2 | DSE X4 */
-			MX93_PAD_ENET2_MDIO__ENET1_MDIO			0x4000111e
+			/* SION | HYS | ODE | FSEL_2 | DSE X4 */
+			MX93_PAD_ENET2_MDIO__ENET1_MDIO			0x4000191e
 			/* HYS | FSEL_0 | DSE no drive */
 			MX93_PAD_ENET2_RD0__ENET1_RGMII_RD0		0x1000
 			MX93_PAD_ENET2_RD1__ENET1_RGMII_RD1		0x1000
diff --git a/dts/upstream/src/arm64/freescale/imx93.dtsi b/dts/upstream/src/arm64/freescale/imx93.dtsi
index 688488de8cd..56766fdb0b1 100644
--- a/dts/upstream/src/arm64/freescale/imx93.dtsi
+++ b/dts/upstream/src/arm64/freescale/imx93.dtsi
@@ -925,7 +925,7 @@
 				reg-names = "ram", "regs", "rxfifo", "txfifo";
 				interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
 					     <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>;
-				clocks = <&clk IMX93_CLK_BUS_WAKEUP>,
+				clocks = <&clk IMX93_CLK_SPDIF_IPG>,
 					 <&clk IMX93_CLK_SPDIF_GATE>,
 					 <&clk IMX93_CLK_DUMMY>,
 					 <&clk IMX93_CLK_AUD_XCVR_GATE>;
diff --git a/dts/upstream/src/arm64/freescale/imx95-19x19-evk.dts b/dts/upstream/src/arm64/freescale/imx95-19x19-evk.dts
index 6086cb7fa5a..8bc066c3760 100644
--- a/dts/upstream/src/arm64/freescale/imx95-19x19-evk.dts
+++ b/dts/upstream/src/arm64/freescale/imx95-19x19-evk.dts
@@ -22,6 +22,7 @@
 	compatible = "fsl,imx95-19x19-evk", "fsl,imx95";
 
 	aliases {
+		ethernet0 = &enetc_port0;
 		gpio0 = &gpio1;
 		gpio1 = &gpio2;
 		gpio2 = &gpio3;
@@ -193,6 +194,14 @@
 	};
 };
 
+&enetc_port0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_enetc0>;
+	phy-handle = <&ethphy0>;
+	phy-mode = "rgmii-id";
+	status = "okay";
+};
+
 &flexspi1 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_flexspi1>;
@@ -338,6 +347,25 @@
 	status = "okay";
 };
 
+&netcmix_blk_ctrl {
+	status = "okay";
+};
+
+&netc_blk_ctrl {
+	status = "okay";
+};
+
+&netc_emdio {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_emdio>;
+	status = "okay";
+
+	ethphy0: ethernet-phy@1 {
+		reg = <1>;
+		realtek,clkout-disable;
+	};
+};
+
 &pcie0 {
 	pinctrl-0 = <&pinctrl_pcie0>;
 	pinctrl-names = "default";
@@ -429,6 +457,30 @@
 };
 
 &scmi_iomuxc {
+	pinctrl_emdio: emdiogrp{
+		fsl,pins = <
+			IMX95_PAD_ENET1_MDC__NETCMIX_TOP_NETC_MDC		0x57e
+			IMX95_PAD_ENET1_MDIO__NETCMIX_TOP_NETC_MDIO		0x97e
+		>;
+	};
+
+	pinctrl_enetc0: enetc0grp {
+		fsl,pins = <
+			IMX95_PAD_ENET1_TD3__NETCMIX_TOP_ETH0_RGMII_TD3		0x57e
+			IMX95_PAD_ENET1_TD2__NETCMIX_TOP_ETH0_RGMII_TD2		0x57e
+			IMX95_PAD_ENET1_TD1__NETCMIX_TOP_ETH0_RGMII_TD1		0x57e
+			IMX95_PAD_ENET1_TD0__NETCMIX_TOP_ETH0_RGMII_TD0		0x57e
+			IMX95_PAD_ENET1_TX_CTL__NETCMIX_TOP_ETH0_RGMII_TX_CTL	0x57e
+			IMX95_PAD_ENET1_TXC__NETCMIX_TOP_ETH0_RGMII_TX_CLK	0x58e
+			IMX95_PAD_ENET1_RX_CTL__NETCMIX_TOP_ETH0_RGMII_RX_CTL	0x57e
+			IMX95_PAD_ENET1_RXC__NETCMIX_TOP_ETH0_RGMII_RX_CLK	0x58e
+			IMX95_PAD_ENET1_RD0__NETCMIX_TOP_ETH0_RGMII_RD0		0x57e
+			IMX95_PAD_ENET1_RD1__NETCMIX_TOP_ETH0_RGMII_RD1		0x57e
+			IMX95_PAD_ENET1_RD2__NETCMIX_TOP_ETH0_RGMII_RD2		0x57e
+			IMX95_PAD_ENET1_RD3__NETCMIX_TOP_ETH0_RGMII_RD3		0x57e
+		>;
+	};
+
 	pinctrl_flexspi1: flexspi1grp {
 		fsl,pins = <
 			IMX95_PAD_XSPI1_SS0_B__FLEXSPI1_A_SS0_B			0x3fe
diff --git a/dts/upstream/src/arm64/freescale/imx95.dtsi b/dts/upstream/src/arm64/freescale/imx95.dtsi
index e9c7a8265d7..6b8470cb346 100644
--- a/dts/upstream/src/arm64/freescale/imx95.dtsi
+++ b/dts/upstream/src/arm64/freescale/imx95.dtsi
@@ -1697,6 +1697,99 @@
 			status = "disabled";
 		};
 
+		netc_blk_ctrl: system-controller@4cde0000 {
+			compatible = "nxp,imx95-netc-blk-ctrl";
+			reg = <0x0 0x4cde0000 0x0 0x10000>,
+			      <0x0 0x4cdf0000 0x0 0x10000>,
+			      <0x0 0x4c81000c 0x0 0x18>;
+			reg-names = "ierb", "prb", "netcmix";
+			#address-cells = <2>;
+			#size-cells = <2>;
+			ranges;
+			power-domains = <&scmi_devpd IMX95_PD_NETC>;
+			assigned-clocks = <&scmi_clk IMX95_CLK_ENET>,
+					  <&scmi_clk IMX95_CLK_ENETREF>;
+			assigned-clock-parents = <&scmi_clk IMX95_CLK_SYSPLL1_PFD2>,
+						 <&scmi_clk IMX95_CLK_SYSPLL1_PFD0>;
+			assigned-clock-rates = <666666666>, <250000000>;
+			clocks = <&scmi_clk IMX95_CLK_ENET>;
+			clock-names = "ipg";
+			status = "disabled";
+
+			netc_bus0: pcie@4ca00000 {
+				compatible = "pci-host-ecam-generic";
+				reg = <0x0 0x4ca00000 0x0 0x100000>;
+				#address-cells = <3>;
+				#size-cells = <2>;
+				device_type = "pci";
+				bus-range = <0x0 0x0>;
+				msi-map = <0x0 &its 0x60 0x1>,	//ENETC0 PF
+					  <0x10 &its 0x61 0x1>, //ENETC0 VF0
+					  <0x20 &its 0x62 0x1>, //ENETC0 VF1
+					  <0x40 &its 0x63 0x1>, //ENETC1 PF
+					  <0x80 &its 0x64 0x1>, //ENETC2 PF
+					  <0x90 &its 0x65 0x1>, //ENETC2 VF0
+					  <0xa0 &its 0x66 0x1>, //ENETC2 VF1
+					  <0xc0 &its 0x67 0x1>; //NETC Timer
+					 /* ENETC0~2 and Timer BAR0 - non-prefetchable memory */
+				ranges = <0x82000000 0x0 0x4cc00000  0x0 0x4cc00000  0x0 0xe0000
+					 /* Timer BAR2 - prefetchable memory */
+					 0xc2000000 0x0 0x4cd00000  0x0 0x4cd00000  0x0 0x10000
+					 /* ENETC0~2: VF0-1 BAR0 - non-prefetchable memory */
+					 0x82000000 0x0 0x4cd20000  0x0 0x4cd20000  0x0 0x60000
+					 /* ENETC0~2: VF0-1 BAR2 - prefetchable memory */
+					 0xc2000000 0x0 0x4cd80000  0x0 0x4cd80000  0x0 0x60000>;
+
+				enetc_port0: ethernet@0,0 {
+					compatible = "pci1131,e101";
+					reg = <0x000000 0 0 0 0>;
+					clocks = <&scmi_clk IMX95_CLK_ENETREF>;
+					clock-names = "ref";
+					status = "disabled";
+				};
+
+				enetc_port1: ethernet@8,0 {
+					compatible = "pci1131,e101";
+					reg = <0x004000 0 0 0 0>;
+					clocks = <&scmi_clk IMX95_CLK_ENETREF>;
+					clock-names = "ref";
+					status = "disabled";
+				};
+
+				enetc_port2: ethernet@10,0 {
+					compatible = "pci1131,e101";
+					reg = <0x008000 0 0 0 0>;
+					status = "disabled";
+				};
+
+				netc_timer: ethernet@18,0 {
+					reg = <0x00c000 0 0 0 0>;
+					status = "disabled";
+				};
+			};
+
+			netc_bus1: pcie@4cb00000 {
+				compatible = "pci-host-ecam-generic";
+				reg = <0x0 0x4cb00000 0x0 0x100000>;
+				#address-cells = <3>;
+				#size-cells = <2>;
+				device_type = "pci";
+				bus-range = <0x1 0x1>;
+					 /* EMDIO BAR0 - non-prefetchable memory */
+				ranges = <0x82000000 0x0 0x4cce0000  0x0 0x4cce0000  0x0 0x20000
+					 /* EMDIO BAR2 - prefetchable memory */
+					 0xc2000000 0x0 0x4cd10000  0x0 0x4cd10000  0x0 0x10000>;
+
+				netc_emdio: mdio@0,0 {
+					compatible = "pci1131,ee00";
+					reg = <0x010000 0 0 0 0>;
+					#address-cells = <1>;
+					#size-cells = <0>;
+					status = "disabled";
+				};
+			};
+		};
+
 		ddr-pmu@4e090dc0 {
 			compatible = "fsl,imx95-ddr-pmu", "fsl,imx93-ddr-pmu";
 			reg = <0x0 0x4e090dc0 0x0 0x200>;
diff --git a/dts/upstream/src/arm64/hisilicon/hi6220.dtsi b/dts/upstream/src/arm64/hisilicon/hi6220.dtsi
index a589954c29e..f8b56d44385 100644
--- a/dts/upstream/src/arm64/hisilicon/hi6220.dtsi
+++ b/dts/upstream/src/arm64/hisilicon/hi6220.dtsi
@@ -727,8 +727,6 @@
 			compatible = "arm,pl022", "arm,primecell";
 			reg = <0x0 0xf7106000 0x0 0x1000>;
 			interrupts = <0 50 4>;
-			bus-id = <0>;
-			enable-dma = <0>;
 			clocks = <&sys_ctrl HI6220_SPI_CLK>, <&sys_ctrl HI6220_SPI_CLK>;
 			clock-names = "sspclk", "apb_pclk";
 			pinctrl-names = "default";
diff --git a/dts/upstream/src/arm64/intel/socfpga_agilex.dtsi b/dts/upstream/src/arm64/intel/socfpga_agilex.dtsi
index 2a5eeb21da4..1235ba5a986 100644
--- a/dts/upstream/src/arm64/intel/socfpga_agilex.dtsi
+++ b/dts/upstream/src/arm64/intel/socfpga_agilex.dtsi
@@ -101,10 +101,13 @@
 		compatible = "arm,gic-400", "arm,cortex-a15-gic";
 		#interrupt-cells = <3>;
 		interrupt-controller;
+		interrupt-parent = <&intc>;
 		reg = <0x0 0xfffc1000 0x0 0x1000>,
 		      <0x0 0xfffc2000 0x0 0x2000>,
 		      <0x0 0xfffc4000 0x0 0x2000>,
 		      <0x0 0xfffc6000 0x0 0x2000>;
+		/* VGIC maintenance interrupt */
+		interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
 	};
 
 	clocks {
diff --git a/dts/upstream/src/arm64/intel/socfpga_agilex5.dtsi b/dts/upstream/src/arm64/intel/socfpga_agilex5.dtsi
index 1162978329c..51c6e19e40b 100644
--- a/dts/upstream/src/arm64/intel/socfpga_agilex5.dtsi
+++ b/dts/upstream/src/arm64/intel/socfpga_agilex5.dtsi
@@ -222,6 +222,26 @@
 			status = "disabled";
 		};
 
+		gpio0: gpio@ffc03200 {
+			compatible = "snps,dw-apb-gpio";
+			reg = <0xffc03200 0x100>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			resets = <&rst GPIO0_RESET>;
+			status = "disabled";
+
+			porta: gpio-controller@0 {
+				compatible = "snps,dw-apb-gpio-port";
+				reg = <0>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				snps,nr-gpios = <24>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+				interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
+			};
+		};
+
 		gpio1: gpio@10c03300 {
 			compatible = "snps,dw-apb-gpio";
 			reg = <0x10c03300 0x100>;
@@ -314,7 +334,7 @@
 			reg-io-width = <4>;
 			num-cs = <4>;
 			clocks = <&clkmgr AGILEX5_L4_MAIN_CLK>;
-			dmas = <&dmac0 2>, <&dmac0 3>;
+			dmas = <&dmac0 16>, <&dmac0 17>;
 			dma-names = "tx", "rx";
 			status = "disabled";
 
@@ -331,6 +351,8 @@
 			reg-io-width = <4>;
 			num-cs = <4>;
 			clocks = <&clkmgr AGILEX5_L4_MAIN_CLK>;
+			dmas = <&dmac0 20>, <&dmac0 21>;
+			dma-names = "tx", "rx";
 			status = "disabled";
 		};
 
diff --git a/dts/upstream/src/arm64/marvell/armada-7040-db.dts b/dts/upstream/src/arm64/marvell/armada-7040-db.dts
index 1e0ab35cc68..2b5e45d2c5a 100644
--- a/dts/upstream/src/arm64/marvell/armada-7040-db.dts
+++ b/dts/upstream/src/arm64/marvell/armada-7040-db.dts
@@ -214,6 +214,7 @@
 
 	sata-port@1 {
 		phys = <&cp0_comphy3 1>;
+		status = "okay";
 	};
 };
 
diff --git a/dts/upstream/src/arm64/marvell/armada-7040-mochabin.dts b/dts/upstream/src/arm64/marvell/armada-7040-mochabin.dts
index 7af949092b9..6bdc4f1e693 100644
--- a/dts/upstream/src/arm64/marvell/armada-7040-mochabin.dts
+++ b/dts/upstream/src/arm64/marvell/armada-7040-mochabin.dts
@@ -433,11 +433,13 @@
 	/* 7 + 12 SATA connector (J24) */
 	sata-port@0 {
 		phys = <&cp0_comphy2 0>;
+		status = "okay";
 	};
 
 	/* M.2-2250 B-key (J39) */
 	sata-port@1 {
 		phys = <&cp0_comphy3 1>;
+		status = "okay";
 	};
 };
 
diff --git a/dts/upstream/src/arm64/marvell/armada-8040-clearfog-gt-8k.dts b/dts/upstream/src/arm64/marvell/armada-8040-clearfog-gt-8k.dts
index 7005a32a6e1..225a54ab688 100644
--- a/dts/upstream/src/arm64/marvell/armada-8040-clearfog-gt-8k.dts
+++ b/dts/upstream/src/arm64/marvell/armada-8040-clearfog-gt-8k.dts
@@ -475,6 +475,7 @@
 
 	sata-port@1 {
 		phys = <&cp1_comphy0 1>;
+		status = "okay";
 	};
 };
 
diff --git a/dts/upstream/src/arm64/marvell/armada-8040-db.dts b/dts/upstream/src/arm64/marvell/armada-8040-db.dts
index 2ec19d364e6..9d45e881a97 100644
--- a/dts/upstream/src/arm64/marvell/armada-8040-db.dts
+++ b/dts/upstream/src/arm64/marvell/armada-8040-db.dts
@@ -145,9 +145,12 @@
 
 	sata-port@0 {
 		phys = <&cp0_comphy1 0>;
+		status = "okay";
 	};
+
 	sata-port@1 {
 		phys = <&cp0_comphy3 1>;
+		status = "okay";
 	};
 };
 
@@ -304,11 +307,9 @@
 
 	sata-port@0 {
 		phys = <&cp1_comphy1 0>;
-		phy-names = "cp1-sata0-0-phy";
 	};
 	sata-port@1 {
 		phys = <&cp1_comphy3 1>;
-		phy-names = "cp1-sata0-1-phy";
 	};
 };
 
diff --git a/dts/upstream/src/arm64/marvell/armada-8040-mcbin.dtsi b/dts/upstream/src/arm64/marvell/armada-8040-mcbin.dtsi
index e88ff5b179c..0d4a5fd9503 100644
--- a/dts/upstream/src/arm64/marvell/armada-8040-mcbin.dtsi
+++ b/dts/upstream/src/arm64/marvell/armada-8040-mcbin.dtsi
@@ -245,6 +245,7 @@
 	/* CPM Lane 5 - U29 */
 	sata-port@1 {
 		phys = <&cp0_comphy5 1>;
+		status = "okay";
 	};
 };
 
@@ -344,13 +345,11 @@
 	/* CPS Lane 1 - U32 */
 	sata-port@0 {
 		phys = <&cp1_comphy1 0>;
-		phy-names = "cp1-sata0-0-phy";
 	};
 
 	/* CPS Lane 3 - U31 */
 	sata-port@1 {
 		phys = <&cp1_comphy3 1>;
-		phy-names = "cp1-sata0-1-phy";
 	};
 };
 
diff --git a/dts/upstream/src/arm64/marvell/armada-8040-puzzle-m801.dts b/dts/upstream/src/arm64/marvell/armada-8040-puzzle-m801.dts
index 3e5e0651ce6..9c25a88581e 100644
--- a/dts/upstream/src/arm64/marvell/armada-8040-puzzle-m801.dts
+++ b/dts/upstream/src/arm64/marvell/armada-8040-puzzle-m801.dts
@@ -408,10 +408,12 @@
 
 	sata-port@0 {
 		phys = <&cp0_comphy2 0>;
+		status = "okay";
 	};
 
 	sata-port@1 {
 		phys = <&cp0_comphy5 1>;
+		status = "okay";
 	};
 };
 
diff --git a/dts/upstream/src/arm64/marvell/armada-cp11x.dtsi b/dts/upstream/src/arm64/marvell/armada-cp11x.dtsi
index 7e595ac8004..161beec0b6b 100644
--- a/dts/upstream/src/arm64/marvell/armada-cp11x.dtsi
+++ b/dts/upstream/src/arm64/marvell/armada-cp11x.dtsi
@@ -347,10 +347,12 @@
 
 			sata-port@0 {
 				reg = <0>;
+				status = "disabled";
 			};
 
 			sata-port@1 {
 				reg = <1>;
+				status = "disabled";
 			};
 		};
 
diff --git a/dts/upstream/src/arm64/marvell/cn9130-crb-B.dts b/dts/upstream/src/arm64/marvell/cn9130-crb-B.dts
index 0904cb0309a..34194745f79 100644
--- a/dts/upstream/src/arm64/marvell/cn9130-crb-B.dts
+++ b/dts/upstream/src/arm64/marvell/cn9130-crb-B.dts
@@ -28,6 +28,7 @@
 		status = "okay";
 		/* Generic PHY, providing serdes lanes */
 		phys = <&cp0_comphy2 0>;
+		status = "okay";
 	};
 };
 
diff --git a/dts/upstream/src/arm64/marvell/cn9131-cf-solidwan.dts b/dts/upstream/src/arm64/marvell/cn9131-cf-solidwan.dts
index b1ea7dcaed1..47234d0858d 100644
--- a/dts/upstream/src/arm64/marvell/cn9131-cf-solidwan.dts
+++ b/dts/upstream/src/arm64/marvell/cn9131-cf-solidwan.dts
@@ -435,7 +435,7 @@
 	managed = "in-band-status";
 	phy-mode = "sgmii";
 	phy = <&cp1_phy0>;
-	phys = <&cp0_comphy3 1>;
+	phys = <&cp1_comphy3 1>;
 	status = "okay";
 };
 
@@ -444,7 +444,7 @@
 	managed = "in-band-status";
 	phy-mode = "sgmii";
 	phy = <&cp1_phy1>;
-	phys = <&cp0_comphy5 2>;
+	phys = <&cp1_comphy5 2>;
 	status = "okay";
 };
 
diff --git a/dts/upstream/src/arm64/marvell/cn9131-db.dtsi b/dts/upstream/src/arm64/marvell/cn9131-db.dtsi
index ad7360c8304..626042fce7e 100644
--- a/dts/upstream/src/arm64/marvell/cn9131-db.dtsi
+++ b/dts/upstream/src/arm64/marvell/cn9131-db.dtsi
@@ -127,6 +127,7 @@
 	sata-port@1 {
 		/* Generic PHY, providing serdes lanes */
 		phys = <&cp1_comphy5 1>;
+		status = "okay";
 	};
 };
 
diff --git a/dts/upstream/src/arm64/marvell/cn9132-db.dtsi b/dts/upstream/src/arm64/marvell/cn9132-db.dtsi
index e753cfdac69..f91fc69905b 100644
--- a/dts/upstream/src/arm64/marvell/cn9132-db.dtsi
+++ b/dts/upstream/src/arm64/marvell/cn9132-db.dtsi
@@ -175,6 +175,7 @@
 	sata-port@0 {
 		/* Generic PHY, providing serdes lanes */
 		phys = <&cp2_comphy2 0>;
+		status = "okay";
 	};
 };
 
diff --git a/dts/upstream/src/arm64/mediatek/mt2712-evb.dts b/dts/upstream/src/arm64/mediatek/mt2712-evb.dts
index c84c47c1352..0449686bd06 100644
--- a/dts/upstream/src/arm64/mediatek/mt2712-evb.dts
+++ b/dts/upstream/src/arm64/mediatek/mt2712-evb.dts
@@ -115,6 +115,7 @@
 	pinctrl-names = "default", "sleep";
 	pinctrl-0 = <&eth_default>;
 	pinctrl-1 = <&eth_sleep>;
+	mediatek,mac-wol;
 	status = "okay";
 
 	mdio {
diff --git a/dts/upstream/src/arm64/mediatek/mt6359.dtsi b/dts/upstream/src/arm64/mediatek/mt6359.dtsi
index 8e1b8c85c6e..150ad84d5d2 100644
--- a/dts/upstream/src/arm64/mediatek/mt6359.dtsi
+++ b/dts/upstream/src/arm64/mediatek/mt6359.dtsi
@@ -8,6 +8,7 @@
 		compatible = "mediatek,mt6359";
 		interrupt-controller;
 		#interrupt-cells = <2>;
+		#sound-dai-cells = <1>;
 
 		pmic_adc: adc {
 			compatible = "mediatek,mt6359-auxadc";
diff --git a/dts/upstream/src/arm64/mediatek/mt7986a-bananapi-bpi-r3-sata.dtso b/dts/upstream/src/arm64/mediatek/mt7986a-bananapi-bpi-r3-sata.dtso
new file mode 100644
index 00000000000..f7dd5298197
--- /dev/null
+++ b/dts/upstream/src/arm64/mediatek/mt7986a-bananapi-bpi-r3-sata.dtso
@@ -0,0 +1,34 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2021 MediaTek Inc.
+ * Author: Frank Wunderlich <frank-w@public-files.de>
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/gpio/gpio.h>
+
+&{/} {
+	compatible = "bananapi,bpi-r3", "mediatek,mt7986a";
+
+	reg_sata12v: regulator-sata12v {
+		compatible = "regulator-fixed";
+		regulator-name = "sata12v";
+		regulator-min-microvolt = <12000000>;
+		regulator-max-microvolt = <12000000>;
+		gpio = <&pio 8 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+		regulator-always-on;
+	};
+
+	reg_sata5v: regulator-sata5v {
+		compatible = "regulator-fixed";
+		regulator-name = "sata5v";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		regulator-always-on;
+		vin-supply = <&reg_sata12v>;
+	};
+
+};
diff --git a/dts/upstream/src/arm64/mediatek/mt7988a-bananapi-bpi-r4-emmc.dtso b/dts/upstream/src/arm64/mediatek/mt7988a-bananapi-bpi-r4-emmc.dtso
new file mode 100644
index 00000000000..3e320b2f83d
--- /dev/null
+++ b/dts/upstream/src/arm64/mediatek/mt7988a-bananapi-bpi-r4-emmc.dtso
@@ -0,0 +1,33 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2021 MediaTek Inc.
+ * Author: Frank Wunderlich <frank-w@public-files.de>
+ */
+
+/dts-v1/;
+/plugin/;
+
+/ {
+	compatible = "bananapi,bpi-r4", "mediatek,mt7988a";
+};
+
+&{/soc/mmc@11230000} {
+	pinctrl-names = "default", "state_uhs";
+	pinctrl-0 = <&mmc0_pins_emmc_51>;
+	pinctrl-1 = <&mmc0_pins_emmc_51>;
+	bus-width = <8>;
+	max-frequency = <200000000>;
+	cap-mmc-highspeed;
+	mmc-hs200-1_8v;
+	mmc-hs400-1_8v;
+	hs400-ds-delay = <0x12814>;
+	vqmmc-supply = <&reg_1p8v>;
+	vmmc-supply = <&reg_3p3v>;
+	non-removable;
+	no-sd;
+	no-sdio;
+	#address-cells = <1>;
+	#size-cells = <0>;
+	status = "okay";
+};
+
diff --git a/dts/upstream/src/arm64/mediatek/mt7988a-bananapi-bpi-r4-sd.dtso b/dts/upstream/src/arm64/mediatek/mt7988a-bananapi-bpi-r4-sd.dtso
new file mode 100644
index 00000000000..663c6345dd3
--- /dev/null
+++ b/dts/upstream/src/arm64/mediatek/mt7988a-bananapi-bpi-r4-sd.dtso
@@ -0,0 +1,31 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2023 MediaTek Inc.
+ * Author: Frank Wunderlich <frank-w@public-files.de>
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+	compatible = "bananapi,bpi-r4", "mediatek,mt7988a";
+};
+
+&{/soc/mmc@11230000} {
+	pinctrl-names = "default", "state_uhs";
+	pinctrl-0 = <&mmc0_pins_sdcard>;
+	pinctrl-1 = <&mmc0_pins_sdcard>;
+	cd-gpios = <&pio 12 GPIO_ACTIVE_LOW>;
+	bus-width = <4>;
+	max-frequency = <52000000>;
+	cap-sd-highspeed;
+	vmmc-supply = <&reg_3p3v>;
+	vqmmc-supply = <&reg_3p3v>;
+	no-mmc;
+	#address-cells = <1>;
+	#size-cells = <0>;
+	status = "okay";
+};
+
diff --git a/dts/upstream/src/arm64/mediatek/mt7988a-bananapi-bpi-r4.dts b/dts/upstream/src/arm64/mediatek/mt7988a-bananapi-bpi-r4.dts
index efc4ad0b08b..6623112c24c 100644
--- a/dts/upstream/src/arm64/mediatek/mt7988a-bananapi-bpi-r4.dts
+++ b/dts/upstream/src/arm64/mediatek/mt7988a-bananapi-bpi-r4.dts
@@ -2,10 +2,408 @@
 
 /dts-v1/;
 
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/regulator/richtek,rt5190a-regulator.h>
+
 #include "mt7988a.dtsi"
 
 / {
 	compatible = "bananapi,bpi-r4", "mediatek,mt7988a";
 	model = "Banana Pi BPI-R4";
 	chassis-type = "embedded";
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	reg_1p8v: regulator-1p8v {
+		compatible = "regulator-fixed";
+		regulator-name = "fixed-1.8V";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+		regulator-boot-on;
+		regulator-always-on;
+	};
+
+	reg_3p3v: regulator-3p3v {
+		compatible = "regulator-fixed";
+		regulator-name = "fixed-3.3V";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-boot-on;
+		regulator-always-on;
+	};
+};
+
+&cpu0 {
+	proc-supply = <&rt5190_buck3>;
+};
+
+&cpu1 {
+	proc-supply = <&rt5190_buck3>;
+};
+
+&cpu2 {
+	proc-supply = <&rt5190_buck3>;
+};
+
+&cpu3 {
+	proc-supply = <&rt5190_buck3>;
+};
+
+&cpu_thermal {
+	trips {
+		cpu_trip_hot: hot {
+			temperature = <120000>;
+			hysteresis = <2000>;
+			type = "hot";
+		};
+
+		cpu_trip_active_high: active-high {
+			temperature = <115000>;
+			hysteresis = <2000>;
+			type = "active";
+		};
+
+		cpu_trip_active_med: active-med {
+			temperature = <85000>;
+			hysteresis = <2000>;
+			type = "active";
+		};
+
+		cpu_trip_active_low: active-low {
+			temperature = <40000>;
+			hysteresis = <2000>;
+			type = "active";
+		};
+	};
+};
+
+&i2c0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c0_pins>;
+	status = "okay";
+
+	rt5190a_64: rt5190a@64 {
+		compatible = "richtek,rt5190a";
+		reg = <0x64>;
+		vin2-supply = <&rt5190_buck1>;
+		vin3-supply = <&rt5190_buck1>;
+		vin4-supply = <&rt5190_buck1>;
+
+		regulators {
+			rt5190_buck1: buck1 {
+				regulator-name = "rt5190a-buck1";
+				regulator-min-microvolt = <5090000>;
+				regulator-max-microvolt = <5090000>;
+				regulator-allowed-modes =
+				<RT5190A_OPMODE_AUTO>, <RT5190A_OPMODE_FPWM>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+			buck2 {
+				regulator-name = "vcore";
+				regulator-min-microvolt = <600000>;
+				regulator-max-microvolt = <1400000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+			rt5190_buck3: buck3 {
+				regulator-name = "vproc";
+				regulator-min-microvolt = <600000>;
+				regulator-max-microvolt = <1400000>;
+				regulator-boot-on;
+			};
+			buck4 {
+				regulator-name = "rt5190a-buck4";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-allowed-modes =
+				<RT5190A_OPMODE_AUTO>, <RT5190A_OPMODE_FPWM>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+			ldo {
+				regulator-name = "rt5190a-ldo";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+		};
+	};
+};
+
+&i2c2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c2_1_pins>;
+	status = "okay";
+
+	pca9545: i2c-mux@70 {
+		compatible = "nxp,pca9545";
+		reg = <0x70>;
+		reset-gpios = <&pio 5 GPIO_ACTIVE_LOW>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		i2c@0 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0>;
+
+			pcf8563: rtc@51 {
+				compatible = "nxp,pcf8563";
+				reg = <0x51>;
+				#clock-cells = <0>;
+			};
+
+			eeprom@57 {
+				compatible = "atmel,24c02";
+				reg = <0x57>;
+				size = <256>;
+			};
+
+		};
+
+		i2c_sfp1: i2c@1 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <1>;
+		};
+
+		i2c_sfp2: i2c@2 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <2>;
+		};
+	};
+};
+
+/* mPCIe SIM2 */
+&pcie0 {
+	status = "okay";
+};
+
+/* mPCIe SIM3 */
+&pcie1 {
+	status = "okay";
+};
+
+/* M.2 key-B SIM1 */
+&pcie2 {
+	status = "okay";
+};
+
+/* M.2 key-M SSD */
+&pcie3 {
+	status = "okay";
+};
+
+&pio {
+	mdio0_pins: mdio0-pins {
+		mux {
+			function = "eth";
+			groups = "mdc_mdio0";
+		};
+
+		conf {
+			pins = "SMI_0_MDC", "SMI_0_MDIO";
+			drive-strength = <8>;
+		};
+	};
+
+	i2c0_pins: i2c0-g0-pins {
+		mux {
+			function = "i2c";
+			groups = "i2c0_1";
+		};
+	};
+
+	i2c1_pins: i2c1-g0-pins {
+		mux {
+			function = "i2c";
+			groups = "i2c1_0";
+		};
+	};
+
+	i2c1_sfp_pins: i2c1-sfp-g0-pins {
+		mux {
+			function = "i2c";
+			groups = "i2c1_sfp";
+		};
+	};
+
+	i2c2_0_pins: i2c2-g0-pins {
+		mux {
+			function = "i2c";
+			groups = "i2c2_0";
+		};
+	};
+
+	i2c2_1_pins: i2c2-g1-pins {
+		mux {
+			function = "i2c";
+			groups = "i2c2_1";
+		};
+	};
+
+	gbe0_led0_pins: gbe0-led0-pins {
+		mux {
+			function = "led";
+			groups = "gbe0_led0";
+		};
+	};
+
+	gbe1_led0_pins: gbe1-led0-pins {
+		mux {
+			function = "led";
+			groups = "gbe1_led0";
+		};
+	};
+
+	gbe2_led0_pins: gbe2-led0-pins {
+		mux {
+			function = "led";
+			groups = "gbe2_led0";
+		};
+	};
+
+	gbe3_led0_pins: gbe3-led0-pins {
+		mux {
+			function = "led";
+			groups = "gbe3_led0";
+		};
+	};
+
+	gbe0_led1_pins: gbe0-led1-pins {
+		mux {
+			function = "led";
+			groups = "gbe0_led1";
+		};
+	};
+
+	gbe1_led1_pins: gbe1-led1-pins {
+		mux {
+			function = "led";
+			groups = "gbe1_led1";
+		};
+	};
+
+	gbe2_led1_pins: gbe2-led1-pins {
+		mux {
+			function = "led";
+			groups = "gbe2_led1";
+		};
+	};
+
+	gbe3_led1_pins: gbe3-led1-pins {
+		mux {
+			function = "led";
+			groups = "gbe3_led1";
+		};
+	};
+
+	i2p5gbe_led0_pins: 2p5gbe-led0-pins {
+		mux {
+			function = "led";
+			groups = "2p5gbe_led0";
+		};
+	};
+
+	i2p5gbe_led1_pins: 2p5gbe-led1-pins {
+		mux {
+			function = "led";
+			groups = "2p5gbe_led1";
+		};
+	};
+
+	mmc0_pins_emmc_45: mmc0-emmc-45-pins {
+		mux {
+			function = "flash";
+			groups = "emmc_45";
+		};
+	};
+
+	mmc0_pins_emmc_51: mmc0-emmc-51-pins {
+		mux {
+			function = "flash";
+			groups = "emmc_51";
+		};
+	};
+
+	mmc0_pins_sdcard: mmc0-sdcard-pins {
+		mux {
+			function = "flash";
+			groups = "sdcard";
+		};
+	};
+
+	uart0_pins: uart0-pins {
+		mux {
+			function = "uart";
+			groups =  "uart0";
+		};
+	};
+
+	snfi_pins: snfi-pins {
+		mux {
+			function = "flash";
+			groups = "snfi";
+		};
+	};
+
+	spi0_pins: spi0-pins {
+		mux {
+			function = "spi";
+			groups = "spi0";
+		};
+	};
+
+	spi0_flash_pins: spi0-flash-pins {
+		mux {
+			function = "spi";
+			groups = "spi0", "spi0_wp_hold";
+		};
+	};
+
+	spi1_pins: spi1-pins {
+		mux {
+			function = "spi";
+			groups = "spi1";
+		};
+	};
+
+	spi2_pins: spi2-pins {
+		mux {
+			function = "spi";
+			groups = "spi2";
+		};
+	};
+
+	spi2_flash_pins: spi2-flash-pins {
+		mux {
+			function = "spi";
+			groups = "spi2", "spi2_wp_hold";
+		};
+	};
+};
+
+&pwm {
+	status = "okay";
+};
+
+&serial0 {
+	status = "okay";
+};
+
+&ssusb1 {
+	status = "okay";
+};
+
+&tphy {
+	status = "okay";
+};
+
+&watchdog {
+	status = "okay";
 };
diff --git a/dts/upstream/src/arm64/mediatek/mt7988a.dtsi b/dts/upstream/src/arm64/mediatek/mt7988a.dtsi
index c9649b81527..88b56a24efc 100644
--- a/dts/upstream/src/arm64/mediatek/mt7988a.dtsi
+++ b/dts/upstream/src/arm64/mediatek/mt7988a.dtsi
@@ -3,6 +3,8 @@
 #include <dt-bindings/clock/mediatek,mt7988-clk.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/phy/phy.h>
+#include <dt-bindings/pinctrl/mt65xx.h>
+#include <dt-bindings/reset/mediatek,mt7988-resets.h>
 
 / {
 	compatible = "mediatek,mt7988a";
@@ -14,32 +16,70 @@
 		#address-cells = <1>;
 		#size-cells = <0>;
 
-		cpu@0 {
+		cpu0: cpu@0 {
 			compatible = "arm,cortex-a73";
 			reg = <0x0>;
 			device_type = "cpu";
 			enable-method = "psci";
+			clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>,
+				 <&topckgen CLK_TOP_XTAL>;
+			clock-names = "cpu", "intermediate";
+			operating-points-v2 = <&cluster0_opp>;
 		};
 
-		cpu@1 {
+		cpu1: cpu@1 {
 			compatible = "arm,cortex-a73";
 			reg = <0x1>;
 			device_type = "cpu";
 			enable-method = "psci";
+			clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>,
+				 <&topckgen CLK_TOP_XTAL>;
+			clock-names = "cpu", "intermediate";
+			operating-points-v2 = <&cluster0_opp>;
 		};
 
-		cpu@2 {
+		cpu2: cpu@2 {
 			compatible = "arm,cortex-a73";
 			reg = <0x2>;
 			device_type = "cpu";
 			enable-method = "psci";
+			clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>,
+				 <&topckgen CLK_TOP_XTAL>;
+			clock-names = "cpu", "intermediate";
+			operating-points-v2 = <&cluster0_opp>;
 		};
 
-		cpu@3 {
+		cpu3: cpu@3 {
 			compatible = "arm,cortex-a73";
 			reg = <0x3>;
 			device_type = "cpu";
 			enable-method = "psci";
+			clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>,
+				 <&topckgen CLK_TOP_XTAL>;
+			clock-names = "cpu", "intermediate";
+			operating-points-v2 = <&cluster0_opp>;
+		};
+
+		cluster0_opp: opp-table-0 {
+			compatible = "operating-points-v2";
+			opp-shared;
+
+			opp-800000000 {
+				opp-hz = /bits/ 64 <800000000>;
+				opp-microvolt = <850000>;
+			};
+			opp-1100000000 {
+				opp-hz = /bits/ 64 <1100000000>;
+				opp-microvolt = <850000>;
+			};
+			opp-1500000000 {
+				opp-hz = /bits/ 64 <1500000000>;
+				opp-microvolt = <850000>;
+			};
+			opp-1800000000 {
+				opp-hz = /bits/ 64 <1800000000>;
+				opp-microvolt = <900000>;
+			};
 		};
 	};
 
@@ -61,6 +101,18 @@
 		method = "smc";
 	};
 
+	reserved-memory {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		/* 320 KiB reserved for ARM Trusted Firmware (BL31 and BL32) */
+		secmon@43000000 {
+			reg = <0 0x43000000 0 0x50000>;
+			no-map;
+		};
+	};
+
 	soc {
 		compatible = "simple-bus";
 		ranges;
@@ -84,6 +136,7 @@
 			compatible = "mediatek,mt7988-infracfg", "syscon";
 			reg = <0 0x10001000 0 0x1000>;
 			#clock-cells = <1>;
+			#reset-cells = <1>;
 		};
 
 		topckgen: clock-controller@1001b000 {
@@ -99,13 +152,66 @@
 			#reset-cells = <1>;
 		};
 
-		clock-controller@1001e000 {
+		apmixedsys: clock-controller@1001e000 {
 			compatible = "mediatek,mt7988-apmixedsys";
 			reg = <0 0x1001e000 0 0x1000>;
 			#clock-cells = <1>;
 		};
 
-		pwm@10048000 {
+		pio: pinctrl@1001f000 {
+			compatible = "mediatek,mt7988-pinctrl";
+			reg = <0 0x1001f000 0 0x1000>,
+			      <0 0x11c10000 0 0x1000>,
+			      <0 0x11d00000 0 0x1000>,
+			      <0 0x11d20000 0 0x1000>,
+			      <0 0x11e00000 0 0x1000>,
+			      <0 0x11f00000 0 0x1000>,
+			      <0 0x1000b000 0 0x1000>;
+			reg-names = "gpio", "iocfg_tr",
+				    "iocfg_br", "iocfg_rb",
+				    "iocfg_lb", "iocfg_tl", "eint";
+			gpio-controller;
+			#gpio-cells = <2>;
+			gpio-ranges = <&pio 0 0 84>;
+			interrupt-controller;
+			interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-parent = <&gic>;
+			#interrupt-cells = <2>;
+
+			pcie0_pins: pcie0-pins {
+				mux {
+					function = "pcie";
+					groups = "pcie_2l_0_pereset", "pcie_clk_req_n0_0",
+						 "pcie_wake_n0_0";
+				};
+			};
+
+			pcie1_pins: pcie1-pins {
+				mux {
+					function = "pcie";
+					groups = "pcie_2l_1_pereset", "pcie_clk_req_n1",
+						 "pcie_wake_n1_0";
+				};
+			};
+
+			pcie2_pins: pcie2-pins {
+				mux {
+					function = "pcie";
+					groups = "pcie_1l_0_pereset", "pcie_clk_req_n2_0",
+						 "pcie_wake_n2_0";
+				};
+			};
+
+			pcie3_pins: pcie3-pins {
+				mux {
+					function = "pcie";
+					groups = "pcie_1l_1_pereset", "pcie_clk_req_n3",
+						 "pcie_wake_n3_0";
+				};
+			};
+		};
+
+		pwm: pwm@10048000 {
 			compatible = "mediatek,mt7988-pwm";
 			reg = <0 0x10048000 0 0x1000>;
 			clocks = <&infracfg CLK_INFRA_66M_PWM_BCK>,
@@ -124,7 +230,13 @@
 			status = "disabled";
 		};
 
-		serial@11000000 {
+		mcusys: mcusys@100e0000 {
+			compatible = "mediatek,mt7988-mcusys", "syscon";
+			reg = <0 0x100e0000 0 0x1000>;
+			#clock-cells = <1>;
+		};
+
+		serial0: serial@11000000 {
 			compatible = "mediatek,mt7988-uart", "mediatek,mt6577-uart";
 			reg = <0 0x11000000 0 0x100>;
 			interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
@@ -157,11 +269,12 @@
 			status = "disabled";
 		};
 
-		i2c@11003000 {
+		i2c0: i2c@11003000 {
 			compatible = "mediatek,mt7981-i2c";
 			reg = <0 0x11003000 0 0x1000>,
 			      <0 0x10217080 0 0x80>;
 			interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
+			clock-div = <1>;
 			clocks = <&infracfg CLK_INFRA_I2C_BCK>,
 				 <&infracfg CLK_INFRA_66M_AP_DMA_BCK>;
 			clock-names = "main", "dma";
@@ -170,11 +283,12 @@
 			status = "disabled";
 		};
 
-		i2c@11004000 {
+		i2c1: i2c@11004000 {
 			compatible = "mediatek,mt7981-i2c";
 			reg = <0 0x11004000 0 0x1000>,
 			      <0 0x10217100 0 0x80>;
 			interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
+			clock-div = <1>;
 			clocks = <&infracfg CLK_INFRA_I2C_BCK>,
 				 <&infracfg CLK_INFRA_66M_AP_DMA_BCK>;
 			clock-names = "main", "dma";
@@ -183,11 +297,12 @@
 			status = "disabled";
 		};
 
-		i2c@11005000 {
+		i2c2: i2c@11005000 {
 			compatible = "mediatek,mt7981-i2c";
 			reg = <0 0x11005000 0 0x1000>,
 			      <0 0x10217180 0 0x80>;
 			interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
+			clock-div = <1>;
 			clocks = <&infracfg CLK_INFRA_I2C_BCK>,
 				 <&infracfg CLK_INFRA_66M_AP_DMA_BCK>;
 			clock-names = "main", "dma";
@@ -196,6 +311,17 @@
 			status = "disabled";
 		};
 
+		lvts: lvts@1100a000 {
+			compatible = "mediatek,mt7988-lvts-ap";
+			#thermal-sensor-cells = <1>;
+			reg = <0 0x1100a000 0 0x1000>;
+			clocks = <&infracfg CLK_INFRA_26M_THERM_SYSTEM>;
+			interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
+			resets = <&infracfg MT7988_INFRA_RST1_THERM_CTRL_SWRST>;
+			nvmem-cells = <&lvts_calibration>;
+			nvmem-cell-names = "lvts-calib-data-1";
+		};
+
 		usb@11190000 {
 			compatible = "mediatek,mt7988-xhci", "mediatek,mtk-xhci";
 			reg = <0 0x11190000 0 0x2e00>,
@@ -208,9 +334,10 @@
 				 <&infracfg CLK_INFRA_133M_USB_HCK>,
 				 <&infracfg CLK_INFRA_USB_XHCI>;
 			clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", "xhci_ck";
+			status = "disabled";
 		};
 
-		usb@11200000 {
+		ssusb1: usb@11200000 {
 			compatible = "mediatek,mt7988-xhci", "mediatek,mtk-xhci";
 			reg = <0 0x11200000 0 0x2e00>,
 			      <0 0x11203e00 0 0x0100>;
@@ -222,6 +349,203 @@
 				 <&infracfg CLK_INFRA_133M_USB_HCK_CK_P1>,
 				 <&infracfg CLK_INFRA_USB_XHCI_CK_P1>;
 			clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", "xhci_ck";
+			phys = <&tphyu2port0 PHY_TYPE_USB2>,
+			       <&tphyu3port0 PHY_TYPE_USB3>;
+			status = "disabled";
+		};
+
+		mmc0: mmc@11230000 {
+			compatible = "mediatek,mt7988-mmc";
+			reg = <0 0x11230000 0 0x1000>,
+			      <0 0x11D60000 0 0x1000>;
+			interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&infracfg CLK_INFRA_MSDC400>,
+				 <&infracfg CLK_INFRA_MSDC2_HCK>,
+				 <&infracfg CLK_INFRA_66M_MSDC_0_HCK>,
+				 <&infracfg CLK_INFRA_133M_MSDC_0_HCK>;
+			assigned-clocks = <&topckgen CLK_TOP_EMMC_250M_SEL>,
+					  <&topckgen CLK_TOP_EMMC_400M_SEL>;
+			assigned-clock-parents = <&topckgen CLK_TOP_NET1PLL_D5_D2>,
+						 <&apmixedsys CLK_APMIXED_MSDCPLL>;
+			clock-names = "source", "hclk", "axi_cg", "ahb_cg";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		pcie2: pcie@11280000 {
+			compatible = "mediatek,mt7986-pcie",
+				     "mediatek,mt8192-pcie";
+			device_type = "pci";
+			#address-cells = <3>;
+			#size-cells = <2>;
+			reg = <0 0x11280000 0 0x2000>;
+			reg-names = "pcie-mac";
+			linux,pci-domain = <3>;
+			interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
+			bus-range = <0x00 0xff>;
+			ranges = <0x81000000 0x00 0x20000000 0x00
+				  0x20000000 0x00 0x00200000>,
+				 <0x82000000 0x00 0x20200000 0x00
+				  0x20200000 0x00 0x07e00000>;
+			clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P2>,
+				 <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P2>,
+				 <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P2>,
+				 <&infracfg CLK_INFRA_133M_PCIE_CK_P2>;
+			clock-names = "pl_250m", "tl_26m", "peri_26m",
+				      "top_133m";
+			pinctrl-names = "default";
+			pinctrl-0 = <&pcie2_pins>;
+			status = "disabled";
+
+			#interrupt-cells = <1>;
+			interrupt-map-mask = <0 0 0 0x7>;
+			interrupt-map = <0 0 0 1 &pcie_intc2 0>,
+					<0 0 0 2 &pcie_intc2 1>,
+					<0 0 0 3 &pcie_intc2 2>,
+					<0 0 0 4 &pcie_intc2 3>;
+			pcie_intc2: interrupt-controller {
+				#address-cells = <0>;
+				#interrupt-cells = <1>;
+				interrupt-controller;
+			};
+		};
+
+		pcie3: pcie@11290000 {
+			compatible = "mediatek,mt7986-pcie",
+				     "mediatek,mt8192-pcie";
+			device_type = "pci";
+			#address-cells = <3>;
+			#size-cells = <2>;
+			reg = <0 0x11290000 0 0x2000>;
+			reg-names = "pcie-mac";
+			linux,pci-domain = <2>;
+			interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
+			bus-range = <0x00 0xff>;
+			ranges = <0x81000000 0x00 0x28000000 0x00
+				  0x28000000 0x00 0x00200000>,
+				 <0x82000000 0x00 0x28200000 0x00
+				  0x28200000 0x00 0x07e00000>;
+			clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P3>,
+				 <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P3>,
+				 <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P3>,
+				 <&infracfg CLK_INFRA_133M_PCIE_CK_P3>;
+			clock-names = "pl_250m", "tl_26m", "peri_26m",
+				      "top_133m";
+			pinctrl-names = "default";
+			pinctrl-0 = <&pcie3_pins>;
+			status = "disabled";
+
+			#interrupt-cells = <1>;
+			interrupt-map-mask = <0 0 0 0x7>;
+			interrupt-map = <0 0 0 1 &pcie_intc3 0>,
+					<0 0 0 2 &pcie_intc3 1>,
+					<0 0 0 3 &pcie_intc3 2>,
+					<0 0 0 4 &pcie_intc3 3>;
+			pcie_intc3: interrupt-controller {
+				#address-cells = <0>;
+				#interrupt-cells = <1>;
+				interrupt-controller;
+			};
+		};
+
+		pcie0: pcie@11300000 {
+			compatible = "mediatek,mt7986-pcie",
+				     "mediatek,mt8192-pcie";
+			device_type = "pci";
+			#address-cells = <3>;
+			#size-cells = <2>;
+			reg = <0 0x11300000 0 0x2000>;
+			reg-names = "pcie-mac";
+			linux,pci-domain = <0>;
+			interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
+			bus-range = <0x00 0xff>;
+			ranges = <0x81000000 0x00 0x30000000 0x00
+				  0x30000000 0x00 0x00200000>,
+				 <0x82000000 0x00 0x30200000 0x00
+				  0x30200000 0x00 0x07e00000>;
+			clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P0>,
+				 <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P0>,
+				 <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P0>,
+				 <&infracfg CLK_INFRA_133M_PCIE_CK_P0>;
+			clock-names = "pl_250m", "tl_26m", "peri_26m",
+				      "top_133m";
+			pinctrl-names = "default";
+			pinctrl-0 = <&pcie0_pins>;
+			status = "disabled";
+
+			#interrupt-cells = <1>;
+			interrupt-map-mask = <0 0 0 0x7>;
+			interrupt-map = <0 0 0 1 &pcie_intc0 0>,
+					<0 0 0 2 &pcie_intc0 1>,
+					<0 0 0 3 &pcie_intc0 2>,
+					<0 0 0 4 &pcie_intc0 3>;
+			pcie_intc0: interrupt-controller {
+				#address-cells = <0>;
+				#interrupt-cells = <1>;
+				interrupt-controller;
+			};
+		};
+
+		pcie1: pcie@11310000 {
+			compatible = "mediatek,mt7986-pcie",
+				     "mediatek,mt8192-pcie";
+			device_type = "pci";
+			#address-cells = <3>;
+			#size-cells = <2>;
+			reg = <0 0x11310000 0 0x2000>;
+			reg-names = "pcie-mac";
+			linux,pci-domain = <1>;
+			interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
+			bus-range = <0x00 0xff>;
+			ranges = <0x81000000 0x00 0x38000000 0x00
+				  0x38000000 0x00 0x00200000>,
+				 <0x82000000 0x00 0x38200000 0x00
+				  0x38200000 0x00 0x07e00000>;
+			clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P1>,
+				 <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P1>,
+				 <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P1>,
+				 <&infracfg CLK_INFRA_133M_PCIE_CK_P1>;
+			clock-names = "pl_250m", "tl_26m", "peri_26m",
+				      "top_133m";
+			pinctrl-names = "default";
+			pinctrl-0 = <&pcie1_pins>;
+			status = "disabled";
+
+			#interrupt-cells = <1>;
+			interrupt-map-mask = <0 0 0 0x7>;
+			interrupt-map = <0 0 0 1 &pcie_intc1 0>,
+					<0 0 0 2 &pcie_intc1 1>,
+					<0 0 0 3 &pcie_intc1 2>,
+					<0 0 0 4 &pcie_intc1 3>;
+			pcie_intc1: interrupt-controller {
+				#address-cells = <0>;
+				#interrupt-cells = <1>;
+				interrupt-controller;
+			};
+		};
+
+		tphy: t-phy@11c50000 {
+			compatible = "mediatek,mt7986-tphy",
+				     "mediatek,generic-tphy-v2";
+			#address-cells = <2>;
+			#size-cells = <2>;
+			ranges;
+			status = "disabled";
+
+			tphyu2port0: usb-phy@11c50000 {
+				reg = <0 0x11c50000 0 0x700>;
+				clocks = <&infracfg CLK_INFRA_USB_UTMI_CK_P1>;
+				clock-names = "ref";
+				#phy-cells = <1>;
+			};
+
+			tphyu3port0: usb-phy@11c50700 {
+				reg = <0 0x11c50700 0 0x900>;
+				clocks = <&infracfg CLK_INFRA_USB_PIPE_CK_P1>;
+				clock-names = "ref";
+				#phy-cells = <1>;
+			};
 		};
 
 		clock-controller@11f40000 {
@@ -236,6 +560,10 @@
 			reg = <0 0x11f50000 0 0x1000>;
 			#address-cells = <1>;
 			#size-cells = <1>;
+
+			lvts_calibration: calib@918 {
+				reg = <0x918 0x28>;
+			};
 		};
 
 		clock-controller@15000000 {
@@ -253,6 +581,21 @@
 		};
 	};
 
+	thermal-zones {
+		cpu_thermal: cpu-thermal {
+			polling-delay-passive = <1000>;
+			polling-delay = <1000>;
+			thermal-sensors = <&lvts 0>;
+			trips {
+				cpu_trip_crit: crit {
+					temperature = <125000>;
+					hysteresis = <2000>;
+					type = "critical";
+				};
+			};
+		};
+	};
+
 	timer {
 		compatible = "arm,armv8-timer";
 		interrupt-parent = <&gic>;
diff --git a/dts/upstream/src/arm64/mediatek/mt8173-elm.dtsi b/dts/upstream/src/arm64/mediatek/mt8173-elm.dtsi
index eee64461421..b5d4b5baf47 100644
--- a/dts/upstream/src/arm64/mediatek/mt8173-elm.dtsi
+++ b/dts/upstream/src/arm64/mediatek/mt8173-elm.dtsi
@@ -931,7 +931,7 @@
 		interrupt-controller;
 		#interrupt-cells = <2>;
 
-		clock: mt6397clock {
+		clock: clocks {
 			compatible = "mediatek,mt6397-clk";
 			#clock-cells = <1>;
 		};
@@ -942,11 +942,10 @@
 			#gpio-cells = <2>;
 		};
 
-		regulator: mt6397regulator {
+		regulators {
 			compatible = "mediatek,mt6397-regulator";
 
 			mt6397_vpca15_reg: buck_vpca15 {
-				regulator-compatible = "buck_vpca15";
 				regulator-name = "vpca15";
 				regulator-min-microvolt = < 700000>;
 				regulator-max-microvolt = <1350000>;
@@ -956,7 +955,6 @@
 			};
 
 			mt6397_vpca7_reg: buck_vpca7 {
-				regulator-compatible = "buck_vpca7";
 				regulator-name = "vpca7";
 				regulator-min-microvolt = < 700000>;
 				regulator-max-microvolt = <1350000>;
@@ -966,7 +964,6 @@
 			};
 
 			mt6397_vsramca15_reg: buck_vsramca15 {
-				regulator-compatible = "buck_vsramca15";
 				regulator-name = "vsramca15";
 				regulator-min-microvolt = < 700000>;
 				regulator-max-microvolt = <1350000>;
@@ -975,7 +972,6 @@
 			};
 
 			mt6397_vsramca7_reg: buck_vsramca7 {
-				regulator-compatible = "buck_vsramca7";
 				regulator-name = "vsramca7";
 				regulator-min-microvolt = < 700000>;
 				regulator-max-microvolt = <1350000>;
@@ -984,7 +980,6 @@
 			};
 
 			mt6397_vcore_reg: buck_vcore {
-				regulator-compatible = "buck_vcore";
 				regulator-name = "vcore";
 				regulator-min-microvolt = < 700000>;
 				regulator-max-microvolt = <1350000>;
@@ -993,7 +988,6 @@
 			};
 
 			mt6397_vgpu_reg: buck_vgpu {
-				regulator-compatible = "buck_vgpu";
 				regulator-name = "vgpu";
 				regulator-min-microvolt = < 700000>;
 				regulator-max-microvolt = <1350000>;
@@ -1002,7 +996,6 @@
 			};
 
 			mt6397_vdrm_reg: buck_vdrm {
-				regulator-compatible = "buck_vdrm";
 				regulator-name = "vdrm";
 				regulator-min-microvolt = <1200000>;
 				regulator-max-microvolt = <1400000>;
@@ -1011,7 +1004,6 @@
 			};
 
 			mt6397_vio18_reg: buck_vio18 {
-				regulator-compatible = "buck_vio18";
 				regulator-name = "vio18";
 				regulator-min-microvolt = <1620000>;
 				regulator-max-microvolt = <1980000>;
@@ -1020,18 +1012,15 @@
 			};
 
 			mt6397_vtcxo_reg: ldo_vtcxo {
-				regulator-compatible = "ldo_vtcxo";
 				regulator-name = "vtcxo";
 				regulator-always-on;
 			};
 
 			mt6397_va28_reg: ldo_va28 {
-				regulator-compatible = "ldo_va28";
 				regulator-name = "va28";
 			};
 
 			mt6397_vcama_reg: ldo_vcama {
-				regulator-compatible = "ldo_vcama";
 				regulator-name = "vcama";
 				regulator-min-microvolt = <1800000>;
 				regulator-max-microvolt = <1800000>;
@@ -1039,18 +1028,15 @@
 			};
 
 			mt6397_vio28_reg: ldo_vio28 {
-				regulator-compatible = "ldo_vio28";
 				regulator-name = "vio28";
 				regulator-always-on;
 			};
 
 			mt6397_vusb_reg: ldo_vusb {
-				regulator-compatible = "ldo_vusb";
 				regulator-name = "vusb";
 			};
 
 			mt6397_vmc_reg: ldo_vmc {
-				regulator-compatible = "ldo_vmc";
 				regulator-name = "vmc";
 				regulator-min-microvolt = <1800000>;
 				regulator-max-microvolt = <3300000>;
@@ -1058,7 +1044,6 @@
 			};
 
 			mt6397_vmch_reg: ldo_vmch {
-				regulator-compatible = "ldo_vmch";
 				regulator-name = "vmch";
 				regulator-min-microvolt = <3000000>;
 				regulator-max-microvolt = <3300000>;
@@ -1066,7 +1051,6 @@
 			};
 
 			mt6397_vemc_3v3_reg: ldo_vemc3v3 {
-				regulator-compatible = "ldo_vemc3v3";
 				regulator-name = "vemc_3v3";
 				regulator-min-microvolt = <3000000>;
 				regulator-max-microvolt = <3300000>;
@@ -1074,7 +1058,6 @@
 			};
 
 			mt6397_vgp1_reg: ldo_vgp1 {
-				regulator-compatible = "ldo_vgp1";
 				regulator-name = "vcamd";
 				regulator-min-microvolt = <1800000>;
 				regulator-max-microvolt = <1800000>;
@@ -1082,7 +1065,6 @@
 			};
 
 			mt6397_vgp2_reg: ldo_vgp2 {
-				regulator-compatible = "ldo_vgp2";
 				regulator-name = "vcamio";
 				regulator-min-microvolt = <3300000>;
 				regulator-max-microvolt = <3300000>;
@@ -1090,7 +1072,6 @@
 			};
 
 			mt6397_vgp3_reg: ldo_vgp3 {
-				regulator-compatible = "ldo_vgp3";
 				regulator-name = "vcamaf";
 				regulator-min-microvolt = <1800000>;
 				regulator-max-microvolt = <1800000>;
@@ -1098,7 +1079,6 @@
 			};
 
 			mt6397_vgp4_reg: ldo_vgp4 {
-				regulator-compatible = "ldo_vgp4";
 				regulator-name = "vgp4";
 				regulator-min-microvolt = <1200000>;
 				regulator-max-microvolt = <3300000>;
@@ -1106,7 +1086,6 @@
 			};
 
 			mt6397_vgp5_reg: ldo_vgp5 {
-				regulator-compatible = "ldo_vgp5";
 				regulator-name = "vgp5";
 				regulator-min-microvolt = <1200000>;
 				regulator-max-microvolt = <3000000>;
@@ -1114,7 +1093,6 @@
 			};
 
 			mt6397_vgp6_reg: ldo_vgp6 {
-				regulator-compatible = "ldo_vgp6";
 				regulator-name = "vgp6";
 				regulator-min-microvolt = <3300000>;
 				regulator-max-microvolt = <3300000>;
@@ -1123,7 +1101,6 @@
 			};
 
 			mt6397_vibr_reg: ldo_vibr {
-				regulator-compatible = "ldo_vibr";
 				regulator-name = "vibr";
 				regulator-min-microvolt = <1300000>;
 				regulator-max-microvolt = <3300000>;
@@ -1131,7 +1108,7 @@
 			};
 		};
 
-		rtc: mt6397rtc {
+		rtc: rtc {
 			compatible = "mediatek,mt6397-rtc";
 		};
 	};
diff --git a/dts/upstream/src/arm64/mediatek/mt8173-evb.dts b/dts/upstream/src/arm64/mediatek/mt8173-evb.dts
index bb4671c18e3..9fffed0ef4b 100644
--- a/dts/upstream/src/arm64/mediatek/mt8173-evb.dts
+++ b/dts/upstream/src/arm64/mediatek/mt8173-evb.dts
@@ -307,11 +307,10 @@
 		interrupt-controller;
 		#interrupt-cells = <2>;
 
-		mt6397regulator: mt6397regulator {
+		regulators {
 			compatible = "mediatek,mt6397-regulator";
 
 			mt6397_vpca15_reg: buck_vpca15 {
-				regulator-compatible = "buck_vpca15";
 				regulator-name = "vpca15";
 				regulator-min-microvolt = < 700000>;
 				regulator-max-microvolt = <1350000>;
@@ -320,7 +319,6 @@
 			};
 
 			mt6397_vpca7_reg: buck_vpca7 {
-				regulator-compatible = "buck_vpca7";
 				regulator-name = "vpca7";
 				regulator-min-microvolt = < 700000>;
 				regulator-max-microvolt = <1350000>;
@@ -329,7 +327,6 @@
 			};
 
 			mt6397_vsramca15_reg: buck_vsramca15 {
-				regulator-compatible = "buck_vsramca15";
 				regulator-name = "vsramca15";
 				regulator-min-microvolt = < 700000>;
 				regulator-max-microvolt = <1350000>;
@@ -338,7 +335,6 @@
 			};
 
 			mt6397_vsramca7_reg: buck_vsramca7 {
-				regulator-compatible = "buck_vsramca7";
 				regulator-name = "vsramca7";
 				regulator-min-microvolt = < 700000>;
 				regulator-max-microvolt = <1350000>;
@@ -347,7 +343,6 @@
 			};
 
 			mt6397_vcore_reg: buck_vcore {
-				regulator-compatible = "buck_vcore";
 				regulator-name = "vcore";
 				regulator-min-microvolt = < 700000>;
 				regulator-max-microvolt = <1350000>;
@@ -356,7 +351,6 @@
 			};
 
 			mt6397_vgpu_reg: buck_vgpu {
-				regulator-compatible = "buck_vgpu";
 				regulator-name = "vgpu";
 				regulator-min-microvolt = < 700000>;
 				regulator-max-microvolt = <1350000>;
@@ -365,7 +359,6 @@
 			};
 
 			mt6397_vdrm_reg: buck_vdrm {
-				regulator-compatible = "buck_vdrm";
 				regulator-name = "vdrm";
 				regulator-min-microvolt = <1200000>;
 				regulator-max-microvolt = <1400000>;
@@ -374,7 +367,6 @@
 			};
 
 			mt6397_vio18_reg: buck_vio18 {
-				regulator-compatible = "buck_vio18";
 				regulator-name = "vio18";
 				regulator-min-microvolt = <1620000>;
 				regulator-max-microvolt = <1980000>;
@@ -383,19 +375,16 @@
 			};
 
 			mt6397_vtcxo_reg: ldo_vtcxo {
-				regulator-compatible = "ldo_vtcxo";
 				regulator-name = "vtcxo";
 				regulator-always-on;
 			};
 
 			mt6397_va28_reg: ldo_va28 {
-				regulator-compatible = "ldo_va28";
 				regulator-name = "va28";
 				regulator-always-on;
 			};
 
 			mt6397_vcama_reg: ldo_vcama {
-				regulator-compatible = "ldo_vcama";
 				regulator-name = "vcama";
 				regulator-min-microvolt = <1500000>;
 				regulator-max-microvolt = <2800000>;
@@ -403,18 +392,15 @@
 			};
 
 			mt6397_vio28_reg: ldo_vio28 {
-				regulator-compatible = "ldo_vio28";
 				regulator-name = "vio28";
 				regulator-always-on;
 			};
 
 			mt6397_vusb_reg: ldo_vusb {
-				regulator-compatible = "ldo_vusb";
 				regulator-name = "vusb";
 			};
 
 			mt6397_vmc_reg: ldo_vmc {
-				regulator-compatible = "ldo_vmc";
 				regulator-name = "vmc";
 				regulator-min-microvolt = <1800000>;
 				regulator-max-microvolt = <3300000>;
@@ -422,7 +408,6 @@
 			};
 
 			mt6397_vmch_reg: ldo_vmch {
-				regulator-compatible = "ldo_vmch";
 				regulator-name = "vmch";
 				regulator-min-microvolt = <3000000>;
 				regulator-max-microvolt = <3300000>;
@@ -430,7 +415,6 @@
 			};
 
 			mt6397_vemc_3v3_reg: ldo_vemc3v3 {
-				regulator-compatible = "ldo_vemc3v3";
 				regulator-name = "vemc_3v3";
 				regulator-min-microvolt = <3000000>;
 				regulator-max-microvolt = <3300000>;
@@ -438,7 +422,6 @@
 			};
 
 			mt6397_vgp1_reg: ldo_vgp1 {
-				regulator-compatible = "ldo_vgp1";
 				regulator-name = "vcamd";
 				regulator-min-microvolt = <1220000>;
 				regulator-max-microvolt = <3300000>;
@@ -446,7 +429,6 @@
 			};
 
 			mt6397_vgp2_reg: ldo_vgp2 {
-				regulator-compatible = "ldo_vgp2";
 				regulator-name = "vcamio";
 				regulator-min-microvolt = <1000000>;
 				regulator-max-microvolt = <3300000>;
@@ -454,7 +436,6 @@
 			};
 
 			mt6397_vgp3_reg: ldo_vgp3 {
-				regulator-compatible = "ldo_vgp3";
 				regulator-name = "vcamaf";
 				regulator-min-microvolt = <1200000>;
 				regulator-max-microvolt = <3300000>;
@@ -462,7 +443,6 @@
 			};
 
 			mt6397_vgp4_reg: ldo_vgp4 {
-				regulator-compatible = "ldo_vgp4";
 				regulator-name = "vgp4";
 				regulator-min-microvolt = <1200000>;
 				regulator-max-microvolt = <3300000>;
@@ -470,7 +450,6 @@
 			};
 
 			mt6397_vgp5_reg: ldo_vgp5 {
-				regulator-compatible = "ldo_vgp5";
 				regulator-name = "vgp5";
 				regulator-min-microvolt = <1200000>;
 				regulator-max-microvolt = <3000000>;
@@ -478,7 +457,6 @@
 			};
 
 			mt6397_vgp6_reg: ldo_vgp6 {
-				regulator-compatible = "ldo_vgp6";
 				regulator-name = "vgp6";
 				regulator-min-microvolt = <1200000>;
 				regulator-max-microvolt = <3300000>;
@@ -486,7 +464,6 @@
 			};
 
 			mt6397_vibr_reg: ldo_vibr {
-				regulator-compatible = "ldo_vibr";
 				regulator-name = "vibr";
 				regulator-min-microvolt = <1300000>;
 				regulator-max-microvolt = <3300000>;
diff --git a/dts/upstream/src/arm64/mediatek/mt8183-kukui-jacuzzi-damu.dts b/dts/upstream/src/arm64/mediatek/mt8183-kukui-jacuzzi-damu.dts
index 65860b33c01..3935d83a047 100644
--- a/dts/upstream/src/arm64/mediatek/mt8183-kukui-jacuzzi-damu.dts
+++ b/dts/upstream/src/arm64/mediatek/mt8183-kukui-jacuzzi-damu.dts
@@ -26,6 +26,10 @@
 	hid-descr-addr = <0x0001>;
 };
 
+&mt6358codec {
+	mediatek,dmic-mode = <1>; /* one-wire */
+};
+
 &qca_wifi {
 	qcom,ath10k-calibration-variant = "GO_DAMU";
 };
diff --git a/dts/upstream/src/arm64/mediatek/mt8183-kukui-jacuzzi-kenzo.dts b/dts/upstream/src/arm64/mediatek/mt8183-kukui-jacuzzi-kenzo.dts
index e8241587949..561770fcf69 100644
--- a/dts/upstream/src/arm64/mediatek/mt8183-kukui-jacuzzi-kenzo.dts
+++ b/dts/upstream/src/arm64/mediatek/mt8183-kukui-jacuzzi-kenzo.dts
@@ -12,3 +12,18 @@
 	chassis-type = "laptop";
 	compatible = "google,juniper-sku17", "google,juniper", "mediatek,mt8183";
 };
+
+&i2c0 {
+	touchscreen@40 {
+		compatible = "hid-over-i2c";
+		reg = <0x40>;
+
+		pinctrl-names = "default";
+		pinctrl-0 = <&touchscreen_pins>;
+
+		interrupts-extended = <&pio 155 IRQ_TYPE_LEVEL_LOW>;
+
+		post-power-on-delay-ms = <70>;
+		hid-descr-addr = <0x0001>;
+	};
+};
diff --git a/dts/upstream/src/arm64/mediatek/mt8183-kukui-jacuzzi-willow.dtsi b/dts/upstream/src/arm64/mediatek/mt8183-kukui-jacuzzi-willow.dtsi
index 76d33540166..c942e461a17 100644
--- a/dts/upstream/src/arm64/mediatek/mt8183-kukui-jacuzzi-willow.dtsi
+++ b/dts/upstream/src/arm64/mediatek/mt8183-kukui-jacuzzi-willow.dtsi
@@ -6,6 +6,21 @@
 /dts-v1/;
 #include "mt8183-kukui-jacuzzi.dtsi"
 
+&i2c0 {
+	touchscreen@40 {
+		compatible = "hid-over-i2c";
+		reg = <0x40>;
+
+		pinctrl-names = "default";
+		pinctrl-0 = <&touchscreen_pins>;
+
+		interrupts-extended = <&pio 155 IRQ_TYPE_LEVEL_LOW>;
+
+		post-power-on-delay-ms = <70>;
+		hid-descr-addr = <0x0001>;
+	};
+};
+
 &i2c2 {
 	trackpad@2c {
 		compatible = "hid-over-i2c";
diff --git a/dts/upstream/src/arm64/mediatek/mt8183-kukui-jacuzzi.dtsi b/dts/upstream/src/arm64/mediatek/mt8183-kukui-jacuzzi.dtsi
index 49e053b932e..80888bd4ad8 100644
--- a/dts/upstream/src/arm64/mediatek/mt8183-kukui-jacuzzi.dtsi
+++ b/dts/upstream/src/arm64/mediatek/mt8183-kukui-jacuzzi.dtsi
@@ -39,8 +39,6 @@
 	pp3300_panel: pp3300-panel {
 		compatible = "regulator-fixed";
 		regulator-name = "pp3300_panel";
-		regulator-min-microvolt = <3300000>;
-		regulator-max-microvolt = <3300000>;
 		pinctrl-names = "default";
 		pinctrl-0 = <&pp3300_panel_pins>;
 
diff --git a/dts/upstream/src/arm64/mediatek/mt8183-kukui.dtsi b/dts/upstream/src/arm64/mediatek/mt8183-kukui.dtsi
index 4b974bb781b..e1495f1900a 100644
--- a/dts/upstream/src/arm64/mediatek/mt8183-kukui.dtsi
+++ b/dts/upstream/src/arm64/mediatek/mt8183-kukui.dtsi
@@ -269,11 +269,6 @@
 	};
 };
 
-&dpi0 {
-	/* TODO Re-enable after DP to Type-C port muxing can be described */
-	status = "disabled";
-};
-
 &gic {
 	mediatek,broken-save-restore-fw;
 };
@@ -944,13 +939,13 @@
 };
 
 &thermal_zones {
-	tboard1 {
+	tboard1-thermal {
 		polling-delay = <1000>; /* milliseconds */
 		polling-delay-passive = <0>; /* milliseconds */
 		thermal-sensors = <&tboard_thermistor1>;
 	};
 
-	tboard2 {
+	tboard2-thermal {
 		polling-delay = <1000>; /* milliseconds */
 		polling-delay-passive = <0>; /* milliseconds */
 		thermal-sensors = <&tboard_thermistor2>;
diff --git a/dts/upstream/src/arm64/mediatek/mt8183-pumpkin.dts b/dts/upstream/src/arm64/mediatek/mt8183-pumpkin.dts
index 61a6f66914b..dbdee604eda 100644
--- a/dts/upstream/src/arm64/mediatek/mt8183-pumpkin.dts
+++ b/dts/upstream/src/arm64/mediatek/mt8183-pumpkin.dts
@@ -522,10 +522,6 @@
 	status = "okay";
 };
 
-&dsi0 {
-	status = "disabled";
-};
-
 &dpi0 {
 	pinctrl-names = "default", "sleep";
 	pinctrl-0 = <&dpi_func_pins>;
diff --git a/dts/upstream/src/arm64/mediatek/mt8183.dtsi b/dts/upstream/src/arm64/mediatek/mt8183.dtsi
index 1afeeb1155f..0aa34e5bbaa 100644
--- a/dts/upstream/src/arm64/mediatek/mt8183.dtsi
+++ b/dts/upstream/src/arm64/mediatek/mt8183.dtsi
@@ -1024,7 +1024,8 @@
 		};
 
 		keyboard: keyboard@10010000 {
-			compatible = "mediatek,mt6779-keypad";
+			compatible = "mediatek,mt8183-keypad",
+				     "mediatek,mt6779-keypad";
 			reg = <0 0x10010000 0 0x1000>;
 			interrupts = <GIC_SPI 186 IRQ_TYPE_EDGE_FALLING>;
 			clocks = <&clk26m>;
@@ -1834,6 +1835,7 @@
 			resets = <&mmsys MT8183_MMSYS_SW0_RST_B_DISP_DSI0>;
 			phys = <&mipi_tx0>;
 			phy-names = "dphy";
+			status = "disabled";
 		};
 
 		dpi0: dpi@14015000 {
@@ -1845,6 +1847,7 @@
 				 <&mmsys CLK_MM_DPI_MM>,
 				 <&apmixedsys CLK_APMIXED_TVDPLL>;
 			clock-names = "pixel", "engine", "pll";
+			status = "disabled";
 
 			port {
 				dpi_out: endpoint { };
diff --git a/dts/upstream/src/arm64/mediatek/mt8186-corsola-chinchou-sku0.dts b/dts/upstream/src/arm64/mediatek/mt8186-corsola-chinchou-sku0.dts
new file mode 100644
index 00000000000..5d012bc4ff0
--- /dev/null
+++ b/dts/upstream/src/arm64/mediatek/mt8186-corsola-chinchou-sku0.dts
@@ -0,0 +1,18 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright 2024 Google LLC
+ */
+
+/dts-v1/;
+#include "mt8186-corsola-chinchou.dtsi"
+
+/ {
+	model = "Google chinchou CZ1104CM2A/CZ1204CM2A";
+	compatible = "google,chinchou-sku0", "google,chinchou-sku2",
+			"google,chinchou-sku4", "google,chinchou-sku5",
+			"google,chinchou", "mediatek,mt8186";
+};
+
+&gpio_keys {
+	status = "disabled";
+};
diff --git a/dts/upstream/src/arm64/mediatek/mt8186-corsola-chinchou-sku1.dts b/dts/upstream/src/arm64/mediatek/mt8186-corsola-chinchou-sku1.dts
new file mode 100644
index 00000000000..9d6e62af694
--- /dev/null
+++ b/dts/upstream/src/arm64/mediatek/mt8186-corsola-chinchou-sku1.dts
@@ -0,0 +1,35 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright 2024 Google LLC
+ */
+
+/dts-v1/;
+#include "mt8186-corsola-chinchou.dtsi"
+
+/ {
+	model = "Google chinchou CZ1104FM2A/CZ1204FM2A/CZ1104CM2A/CZ1204CM2A";
+	compatible = "google,chinchou-sku1", "google,chinchou-sku3",
+			"google,chinchou-sku6", "google,chinchou-sku7",
+			"google,chinchou-sku17", "google,chinchou-sku20",
+			"google,chinchou-sku22", "google,chinchou-sku23",
+			"google,chinchou", "mediatek,mt8186";
+};
+
+&gpio_keys {
+	status = "disabled";
+};
+
+&i2c1 {
+	i2c-scl-internal-delay-ns = <10000>;
+
+	touchscreen: touchscreen@41 {
+		compatible = "ilitek,ili2901";
+		reg = <0x41>;
+		interrupts-extended = <&pio 12 IRQ_TYPE_LEVEL_LOW>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&touchscreen_pins>;
+		reset-gpios = <&pio 60 GPIO_ACTIVE_LOW>;
+		vccio-supply = <&pp1800_tchscr_report_disable>;
+		vcc33-supply = <&pp3300_z2>;
+	};
+};
diff --git a/dts/upstream/src/arm64/mediatek/mt8186-corsola-chinchou-sku16.dts b/dts/upstream/src/arm64/mediatek/mt8186-corsola-chinchou-sku16.dts
new file mode 100644
index 00000000000..eb377de1fcd
--- /dev/null
+++ b/dts/upstream/src/arm64/mediatek/mt8186-corsola-chinchou-sku16.dts
@@ -0,0 +1,29 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright 2024 Google LLC
+ */
+
+/dts-v1/;
+#include "mt8186-corsola-chinchou.dtsi"
+
+/ {
+	model = "Google chinchou CZ1104FM2A/CZ1204FM2A";
+	compatible = "google,chinchou-sku16", "google,chinchou-sku18",
+			"google,chinchou-sku19", "google,chinchou-sku21",
+			"google,chinchou", "mediatek,mt8186";
+};
+
+&i2c1 {
+	i2c-scl-internal-delay-ns = <10000>;
+
+	touchscreen: touchscreen@41 {
+		compatible = "ilitek,ili2901";
+		reg = <0x41>;
+		interrupts-extended = <&pio 12 IRQ_TYPE_LEVEL_LOW>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&touchscreen_pins>;
+		reset-gpios = <&pio 60 GPIO_ACTIVE_LOW>;
+		vccio-supply = <&pp1800_tchscr_report_disable>;
+		vcc33-supply = <&pp3300_z2>;
+	};
+};
diff --git a/dts/upstream/src/arm64/mediatek/mt8186-corsola-chinchou.dtsi b/dts/upstream/src/arm64/mediatek/mt8186-corsola-chinchou.dtsi
new file mode 100644
index 00000000000..80079215702
--- /dev/null
+++ b/dts/upstream/src/arm64/mediatek/mt8186-corsola-chinchou.dtsi
@@ -0,0 +1,321 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright 2024 Google LLC
+ */
+
+/dts-v1/;
+#include "mt8186-corsola.dtsi"
+
+/ {
+	/delete-node/ speaker-codec;
+
+	pp1000_edpbrdg: regulator-pp1000-edpbrdg {
+		compatible = "regulator-fixed";
+		regulator-name = "pp1000_edpbrdg";
+		pinctrl-names = "default";
+		pinctrl-0 = <&en_pp1000_edpbrdg>;
+		enable-active-high;
+		regulator-boot-on;
+		gpio = <&pio 29 GPIO_ACTIVE_HIGH>;
+		vin-supply = <&pp3300_z2>;
+	};
+
+	pp1800_edpbrdg_dx: regulator-pp1800-edpbrdg-dx {
+		compatible = "regulator-fixed";
+		regulator-name = "pp1800_edpbrdg_dx";
+		pinctrl-names = "default";
+		pinctrl-0 = <&en_pp1800_edpbrdg>;
+		enable-active-high;
+		regulator-boot-on;
+		gpio = <&pio 30 GPIO_ACTIVE_HIGH>;
+		vin-supply = <&mt6366_vio18_reg>;
+	};
+
+	pp3300_edp_dx: regulator-pp3300-edp-dx {
+		compatible = "regulator-fixed";
+		regulator-name = "pp3300_edp_dx";
+		pinctrl-names = "default";
+		pinctrl-0 = <&en_pp3300_edpbrdg>;
+		enable-active-high;
+		regulator-boot-on;
+		gpio = <&pio 31 GPIO_ACTIVE_HIGH>;
+		vin-supply = <&pp3300_z2>;
+	};
+
+	pp1800_tchscr_report_disable: regulator-pp1800-tchscr-report-disable {
+		compatible = "regulator-fixed";
+		regulator-name = "pp1800_tchscr_report_disable";
+		pinctrl-names = "default";
+		regulator-boot-on;
+		pinctrl-0 = <&touch_pin_report>;
+		gpio = <&pio 37 GPIO_ACTIVE_LOW>;
+	};
+};
+
+&dsi_out {
+	remote-endpoint = <&anx7625_in>;
+};
+
+&i2c0 {
+	clock-frequency = <400000>;
+
+	anx_bridge: anx7625@58 {
+		compatible = "analogix,anx7625";
+		reg = <0x58>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&anx7625_pins>;
+		enable-gpios = <&pio 96 GPIO_ACTIVE_HIGH>;
+		reset-gpios = <&pio 98 GPIO_ACTIVE_HIGH>;
+		vdd10-supply = <&pp1000_edpbrdg>;
+		vdd18-supply = <&pp1800_edpbrdg_dx>;
+		vdd33-supply = <&pp3300_edp_dx>;
+		analogix,lane0-swing = /bits/ 8 <0x70 0x30>;
+		analogix,lane1-swing = /bits/ 8 <0x70 0x30>;
+
+		ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@0 {
+				reg = <0>;
+
+				anx7625_in: endpoint {
+					remote-endpoint = <&dsi_out>;
+					data-lanes = <0 1 2 3>;
+				};
+			};
+
+			port@1 {
+				reg = <1>;
+
+				anx7625_out: endpoint {
+					remote-endpoint = <&panel_in>;
+				};
+			};
+		};
+
+		aux-bus {
+			panel: panel {
+				compatible = "edp-panel";
+				power-supply = <&pp3300_disp_x>;
+				backlight = <&backlight_lcd0>;
+
+				port {
+					panel_in: endpoint {
+						remote-endpoint = <&anx7625_out>;
+					};
+				};
+			};
+		};
+	};
+};
+
+&i2c2 {
+	/delete-node/ trackpad@15;
+
+	touchpad@15 {
+		compatible = "hid-over-i2c";
+		reg = <0x15>;
+		interrupts-extended = <&pio 11 IRQ_TYPE_LEVEL_LOW>;
+		post-power-on-delay-ms = <10>;
+		hid-descr-addr = <0x0001>;
+		vdd-supply = <&pp3300_s3>;
+		wakeup-source;
+	};
+};
+
+&i2c5 {
+	clock-frequency = <400000>;
+	/delete-node/ codec@1a;
+
+	rt5650: rt5650@1a {
+		compatible = "realtek,rt5650";
+		reg = <0x1a>;
+		avdd-supply = <&mt6366_vio18_reg>;
+		cpvdd-supply = <&mt6366_vio18_reg>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&speaker_codec_pins_default>;
+		cbj-sleeve-gpios = <&pio 150 GPIO_ACTIVE_HIGH>;
+		interrupt-parent = <&pio>;
+		interrupts = <17 IRQ_TYPE_EDGE_BOTH>;
+		#sound-dai-cells = <0>;
+		realtek,dmic1-data-pin = <2>;
+		realtek,jd-mode = <2>;
+	};
+};
+
+&i2c_tunnel {
+	/delete-node/ sbs-battery@b;
+
+	battery: sbs-battery@f {
+		compatible = "sbs,sbs-battery";
+		reg = <0xf>;
+		sbs,i2c-retry-count = <2>;
+		sbs,poll-retry-count = <1>;
+	};
+};
+
+&keyboard_controller {
+	keypad,num-columns = <15>;
+
+	function-row-physmap = <
+		MATRIX_KEY(0x00, 0x02, 0)        /* T1 */
+		MATRIX_KEY(0x03, 0x02, 0)        /* T2 */
+		MATRIX_KEY(0x02, 0x02, 0)        /* T3 */
+		MATRIX_KEY(0x01, 0x02, 0)        /* T4 */
+		MATRIX_KEY(0x03, 0x04, 0)        /* T5 */
+		MATRIX_KEY(0x02, 0x04, 0)        /* T6 */
+		MATRIX_KEY(0x01, 0x04, 0)        /* T7 */
+		MATRIX_KEY(0x02, 0x09, 0)        /* T8 */
+		MATRIX_KEY(0x01, 0x09, 0)        /* T9 */
+		MATRIX_KEY(0x00, 0x04, 0)        /* T10 */
+		MATRIX_KEY(0x00, 0x01, 0)        /* T11 */
+		MATRIX_KEY(0x01, 0x05, 0)        /* T12 */
+	>;
+
+	linux,keymap = <
+		CROS_STD_MAIN_KEYMAP
+		MATRIX_KEY(0x00, 0x02, KEY_BACK)           /* T1 */
+		MATRIX_KEY(0x03, 0x02, KEY_REFRESH)        /* T2 */
+		MATRIX_KEY(0x02, 0x02, KEY_ZOOM)           /* T3 */
+		MATRIX_KEY(0x01, 0x02, KEY_SCALE)          /* T4 */
+		MATRIX_KEY(0x03, 0x04, KEY_SYSRQ)          /* T5 */
+		MATRIX_KEY(0x02, 0x04, KEY_BRIGHTNESSDOWN) /* T6 */
+		MATRIX_KEY(0x01, 0x04, KEY_BRIGHTNESSUP)   /* T7 */
+		MATRIX_KEY(0x02, 0x09, KEY_MUTE)           /* T8 */
+		MATRIX_KEY(0x01, 0x09, KEY_VOLUMEDOWN)	   /* T9 */
+		MATRIX_KEY(0x00, 0x04, KEY_VOLUMEUP)	   /* T10 */
+		MATRIX_KEY(0x00, 0x01, KEY_MICMUTE)        /* T11 */
+		MATRIX_KEY(0x01, 0x05, KEY_CONTROLPANEL)   /* T12 */
+		MATRIX_KEY(0x03, 0x05, KEY_PREVIOUSSONG)   /* T13 */
+		MATRIX_KEY(0x00, 0x09, KEY_PLAYPAUSE)	   /* T14 */
+		MATRIX_KEY(0x00, 0x0b, KEY_NEXTSONG)	   /* T15 */
+		MATRIX_KEY(0x03, 0x00, KEY_LEFTMETA)	   /* Search*/
+		MATRIX_KEY(0x01, 0x0e, KEY_LEFTCTRL)	   /* Left Control*/
+		MATRIX_KEY(0x06, 0x0d, KEY_LEFTALT)        /* Left ALT*/
+		MATRIX_KEY(0x03, 0x0e, KEY_RIGHTCTRL)      /* Right Control*/
+		MATRIX_KEY(0x06, 0x0a, KEY_BACKSLASH)      /* BACKSLASH*/
+	>;
+};
+
+&mmc1_pins_default {
+	pins-clk {
+		drive-strength = <8>;
+	};
+
+	pins-cmd-dat {
+		drive-strength = <8>;
+	};
+};
+
+&mmc1_pins_uhs {
+	pins-clk {
+		drive-strength = <8>;
+	};
+
+	pins-cmd-dat {
+		drive-strength = <8>;
+	};
+};
+
+&pen_insert {
+	wakeup-event-action = <EV_ACT_ANY>;
+};
+
+&pio {
+	anx7625_pins: anx7625-pins {
+		pins-int {
+			pinmux = <PINMUX_GPIO9__FUNC_GPIO9>;
+			input-enable;
+			bias-disable;
+		};
+
+		pins-reset {
+			pinmux = <PINMUX_GPIO98__FUNC_GPIO98>;
+			output-low;
+		};
+
+		pins-power-en {
+			pinmux = <PINMUX_GPIO96__FUNC_GPIO96>;
+			output-low;
+		};
+	};
+
+	en_pp1000_edpbrdg: pp1000-edpbrdg-en-pins {
+		pins-vreg-en {
+			pinmux = <PINMUX_GPIO29__FUNC_GPIO29>;
+			output-low;
+		};
+	};
+
+	en_pp1800_edpbrdg: pp1800-edpbrdg-en-pins {
+		pins-vreg-en {
+			pinmux = <PINMUX_GPIO30__FUNC_GPIO30>;
+			output-low;
+		};
+	};
+
+	en_pp3300_edpbrdg: pp3300-edpbrdg-en-pins {
+		pins-vreg-en {
+			pinmux = <PINMUX_GPIO31__FUNC_GPIO31>;
+			output-low;
+		};
+	};
+
+	touch_pin_report: pin-report-pins {
+		pins-touch-en {
+			pinmux = <PINMUX_GPIO37__FUNC_GPIO37>;
+			output-low;
+		};
+	};
+};
+
+&sound {
+	compatible = "mediatek,mt8186-mt6366-rt5650-sound";
+	model = "mt8186_rt5650";
+	mediatek,adsp = <&adsp>;
+
+	audio-routing =
+		"Headphone", "HPOL",
+		"Headphone", "HPOR",
+		"IN1P", "Headset Mic",
+		"IN1N", "Headset Mic",
+		"Speakers", "SPOL",
+		"Speakers", "SPOR",
+		"HDMI1", "TX";
+
+	hs-playback-dai-link {
+		codec {
+			sound-dai = <&rt5650>;
+		};
+	};
+
+	hs-capture-dai-link {
+		codec {
+			sound-dai = <&rt5650>;
+		};
+	};
+
+	spk-share-dai-link {
+	};
+
+	spk-hdmi-playback-dai-link {
+		codec {
+			sound-dai = <&it6505dptx>;
+		};
+	};
+};
+
+&touchscreen_pins {
+	/delete-node/ pins-report-sw;
+};
+
+&wifi_enable_pin {
+	pins-wifi-enable {
+		pinmux = <PINMUX_GPIO51__FUNC_GPIO51>;
+	};
+};
+
+&wifi_pwrseq {
+	reset-gpios = <&pio 51 GPIO_ACTIVE_LOW>;
+};
diff --git a/dts/upstream/src/arm64/mediatek/mt8186-corsola-starmie-sku0.dts b/dts/upstream/src/arm64/mediatek/mt8186-corsola-starmie-sku0.dts
new file mode 100644
index 00000000000..23e194579bf
--- /dev/null
+++ b/dts/upstream/src/arm64/mediatek/mt8186-corsola-starmie-sku0.dts
@@ -0,0 +1,31 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright 2023 Google LLC
+ */
+
+/dts-v1/;
+#include "mt8186-corsola-starmie.dtsi"
+
+/ {
+	model = "Google Starmie sku0 board";
+	compatible = "google,starmie-sku0", "google,starmie-sku2",
+		     "google,starmie-sku3", "google,starmie",
+		     "mediatek,mt8186";
+};
+
+&panel {
+	compatible = "starry,ili9882t";
+};
+
+&i2c1 {
+	touchscreen: touchscreen@41 {
+		compatible = "ilitek,ili9882t";
+		reg = <0x41>;
+		interrupts-extended = <&pio 12 IRQ_TYPE_LEVEL_LOW>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&touchscreen_pins>;
+		panel = <&panel>;
+		reset-gpios = <&pio 60 GPIO_ACTIVE_LOW>;
+		vccio-supply = <&mt6366_vio18_reg>;
+	};
+};
diff --git a/dts/upstream/src/arm64/mediatek/mt8186-corsola-starmie-sku1.dts b/dts/upstream/src/arm64/mediatek/mt8186-corsola-starmie-sku1.dts
new file mode 100644
index 00000000000..214b972c935
--- /dev/null
+++ b/dts/upstream/src/arm64/mediatek/mt8186-corsola-starmie-sku1.dts
@@ -0,0 +1,31 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright 2023 Google LLC
+ */
+
+/dts-v1/;
+#include "mt8186-corsola-starmie.dtsi"
+
+/ {
+	model = "Google Starmie sku1 board";
+	compatible = "google,starmie-sku1", "google,starmie-sku4",
+		     "google,starmie", "mediatek,mt8186";
+};
+
+&panel {
+	compatible = "starry,himax83102-j02", "himax,hx83102";
+};
+
+&i2c1 {
+	touchscreen_himax: touchscreen@4f {
+		compatible = "hid-over-i2c";
+		reg = <0x4f>;
+		interrupts-extended = <&pio 12 IRQ_TYPE_LEVEL_LOW>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&touchscreen_pins>;
+		vdd-supply = <&mt6366_vio18_reg>;
+		panel = <&panel>;
+		post-power-on-delay-ms = <450>;
+		hid-descr-addr = <0x0001>;
+	};
+};
diff --git a/dts/upstream/src/arm64/mediatek/mt8186-corsola-starmie.dtsi b/dts/upstream/src/arm64/mediatek/mt8186-corsola-starmie.dtsi
new file mode 100644
index 00000000000..5ea8bdc00e8
--- /dev/null
+++ b/dts/upstream/src/arm64/mediatek/mt8186-corsola-starmie.dtsi
@@ -0,0 +1,472 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright 2023 Google LLC
+ */
+
+/dts-v1/;
+#include "mt8186-corsola.dtsi"
+
+/ {
+	en_pp6000_mipi_disp_150ma: en-pp6000-mipi-disp-150ma {
+		compatible = "regulator-fixed";
+		regulator-name = "en_pp6000_mipi_disp_150ma";
+		gpio = <&pio 154 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+		pinctrl-names = "default";
+		pinctrl-0 = <&en_pp6000_mipi_disp_150ma_fixed_pins>;
+	};
+
+	/*
+	 * Starmie does not have 3.3V display regulator. It is replaced
+	 * with 6V module for enabling panel, re-using eDP GPIOs.
+	 */
+	/delete-node/ pp3300_disp_x;
+	en_pp6000_mipi_disp: en-regulator-pp6000-mipi-disp {
+		compatible = "regulator-fixed";
+		pinctrl-names = "default";
+		pinctrl-0 = <&edp_panel_fixed_pins>;
+		gpios = <&pio 153 GPIO_ACTIVE_HIGH>;
+		regulator-name = "en_pp6000_mipi_disp";
+		enable-active-high;
+		regulator-enable-ramp-delay = <3000>;
+		vin-supply = <&pp3300_z2>;
+	};
+
+	tboard_thermistor1: thermal-sensor1 {
+		compatible = "generic-adc-thermal";
+		#thermal-sensor-cells = <0>;
+		io-channels = <&auxadc 0>;
+		io-channel-names = "sensor-channel";
+		temperature-lookup-table = <    (-5000) 1492
+						0 1413
+						5000 1324
+						10000 1227
+						15000 1121
+						20000 1017
+						25000 900
+						30000 797
+						35000 698
+						40000 606
+						45000 522
+						50000 449
+						55000 383
+						60000 327
+						65000 278
+						70000 236
+						75000 201
+						80000 171
+						85000 145
+						90000 163
+						95000 124
+						100000 91
+						105000 78
+						110000 67
+						115000 58
+						120000 50
+						125000 44>;
+	};
+
+	tboard_thermistor2: thermal-sensor2 {
+		compatible = "generic-adc-thermal";
+		#thermal-sensor-cells = <0>;
+		io-channels = <&auxadc 1>;
+		io-channel-names = "sensor-channel";
+		temperature-lookup-table = <    (-5000) 1492
+						0 1413
+						5000 1324
+						10000 1227
+						15000 1121
+						20000 1017
+						25000 900
+						30000 797
+						35000 698
+						40000 606
+						45000 522
+						50000 449
+						55000 383
+						60000 327
+						65000 278
+						70000 236
+						75000 201
+						80000 171
+						85000 145
+						90000 163
+						95000 124
+						100000 91
+						105000 78
+						110000 67
+						115000 58
+						120000 50
+						125000 44>;
+	};
+};
+
+/*
+ * Starmie does not have EC keyboard. Remove default keyboard controller
+ * and replace it with the driver for side switches.
+ */
+/delete-node/ &keyboard_controller;
+
+&cros_ec {
+	cbas: cbas {
+		compatible = "google,cros-cbas";
+	};
+
+	keyboard-controller {
+		compatible = "google,cros-ec-keyb-switches";
+	};
+};
+
+&dsi0 {
+	#address-cells = <1>;
+	#size-cells = <0>;
+	panel: panel@0 {
+		/* compatible will be set in board dts */
+		reg = <0>;
+		enable-gpios = <&pio 98 0>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&panel_default_pins>;
+		avdd-supply = <&en_pp6000_mipi_disp>;
+		avee-supply = <&en_pp6000_mipi_disp_150ma>;
+		pp1800-supply = <&mt6366_vio18_reg>;
+		backlight = <&backlight_lcd0>;
+		rotation = <270>;
+		port {
+			panel_in: endpoint {
+				remote-endpoint = <&dsi_out>;
+			};
+		};
+	};
+};
+
+&dsi_out {
+	remote-endpoint = <&panel_in>;
+};
+
+&i2c0 {
+	status = "disabled";
+};
+
+&i2c2 {
+	status = "disabled";
+};
+
+&i2c4 {
+	status = "disabled";
+};
+
+&i2c5 {
+	clock-frequency = <400000>;
+};
+
+&mmc1_pins_default {
+	pins-clk {
+		drive-strength = <8>;
+	};
+
+	pins-cmd-dat {
+		drive-strength = <8>;
+	};
+};
+
+&mmc1_pins_uhs {
+	pins-clk {
+		drive-strength = <8>;
+	};
+
+	pins-cmd-dat {
+		drive-strength = <8>;
+	};
+};
+
+&pen_insert {
+	wakeup-event-action = <EV_ACT_ANY>;
+};
+
+&pio {
+	/* 185 lines */
+	gpio-line-names = "TP",
+			  "TP",
+			  "TP",
+			  "I2S0_HP_DI",
+			  "I2S3_DP_SPKR_DO",
+			  "SAR_INT_ODL",
+			  "BT_WAKE_AP_ODL",
+			  "WIFI_INT_ODL",
+			  "DPBRDG_INT_ODL",
+			  "NC",
+			  "EC_AP_HPD_OD",
+			  "NC",
+			  "TCHSCR_INT_1V8_ODL",
+			  "EC_AP_INT_ODL",
+			  "EC_IN_RW_ODL",
+			  "GSC_AP_INT_ODL",
+			  /*
+			   * AP_FLASH_WP_L is crossystem ABI. Rev1 schematics
+			   * call it AP_WP_ODL.
+			   */
+			  "AP_FLASH_WP_L",
+			  "HP_INT_ODL",
+			  "PEN_EJECT_OD",
+			  "NC",
+			  "NC",
+			  "UCAM_SEN_EN",
+			  "NC",
+			  "NC",
+			  "NC",
+			  "I2S2_DP_SPK_MCK",
+			  "I2S2_DP_SPKR_BCK",
+			  "I2S2_DP_SPKR_LRCK",
+			  "NC",
+			  "NC",
+			  "NC",
+			  "NC",
+			  "UART_GSC_TX_AP_RX",
+			  "UART_AP_TX_GSC_RX",
+			  "UART_DBGCON_TX_ADSP_RX",
+			  "UART_ADSP_TX_DBGCON_RX",
+			  "NC",
+			  "TCHSCR_REPORT_DISABLE",
+			  "NC",
+			  "EN_PP1800_DPBRDG",
+			  "SPI_AP_CLK_EC",
+			  "SPI_AP_CS_EC_L",
+			  "SPI_AP_DO_EC_DI",
+			  "SPI_AP_DI_EC_DO",
+			  "SPI_AP_CLK_GSC",
+			  "SPI_AP_CS_GSC_L",
+			  "SPI_AP_DO_GSC_DI",
+			  "SPI_AP_DI_GSC_DO",
+			  "UART_DBGCON_TX_SCP_RX",
+			  "UART_SCP_TX_DBGCON_RX",
+			  "EN_PP1200_CAM_X",
+			  "WLAN_MODULE_RST_L",
+			  "NC",
+			  "NC",
+			  "NC",
+			  "NC",
+			  "I2S1_HP_DO",
+			  "I2S1_HP_BCK",
+			  "I2S1_HP_LRCK",
+			  "I2S1_HP_MCK",
+			  "TCHSCR_RST_1V8_L",
+			  "SPI_AP_CLK_ROM",
+			  "SPI_AP_CS_ROM_L",
+			  "SPI_AP_DO_ROM_DI",
+			  "SPI_AP_DI_ROM_DO",
+			  "NC",
+			  "NC",
+			  "EMMC_STRB",
+			  "EMMC_CLK",
+			  "EMMC_CMD",
+			  "EMMC_RST_L",
+			  "EMMC_DATA0",
+			  "EMMC_DATA1",
+			  "EMMC_DATA2",
+			  "EMMC_DATA3",
+			  "EMMC_DATA4",
+			  "EMMC_DATA5",
+			  "EMMC_DATA6",
+			  "EMMC_DATA7",
+			  "AP_KPCOL0",
+			  "NC",
+			  "NC",
+			  "NC",
+			  "TP",
+			  "SDIO_CLK",
+			  "SDIO_CMD",
+			  "SDIO_DATA0",
+			  "SDIO_DATA1",
+			  "SDIO_DATA2",
+			  "SDIO_DATA3",
+			  "NC",
+			  "NC",
+			  "NC",
+			  "NC",
+			  "NC",
+			  "NC",
+			  "NC",
+			  "MIPI_BL_PWM_1V8",
+			  "DISP_RST_1V8_L",
+			  "MIPI_DPI_CLK",
+			  "MIPI_DPI_VSYNC",
+			  "MIPI_DPI_HSYNC",
+			  "MIPI_DPI_DE",
+			  "MIPI_DPI_D0",
+			  "MIPI_DPI_D1",
+			  "MIPI_DPI_D2",
+			  "MIPI_DPI_D3",
+			  "MIPI_DPI_D4",
+			  "MIPI_DPI_D5",
+			  "MIPI_DPI_D6",
+			  "MIPI_DPI_DA7",
+			  "MIPI_DPI_D8",
+			  "MIPI_DPI_D9",
+			  "MIPI_DPI_D10",
+			  "MIPI_DPI_D11",
+			  "PCM_BT_CLK",
+			  "PCM_BT_SYNC",
+			  "PCM_BT_DI",
+			  "PCM_BT_DO",
+			  "JTAG_TMS_TP",
+			  "JTAG_TCK_TP",
+			  "JTAG_TDI_TP",
+			  "JTAG_TDO_TP",
+			  "JTAG_TRSTN_TP",
+			  "NC",
+			  "NC",
+			  "UCAM_DET_ODL",
+			  "NC",
+			  "NC",
+			  "AP_I2C_TCHSCR_SCL_1V8",
+			  "AP_I2C_TCHSCR_SDA_1V8",
+			  "NC",
+			  "NC",
+			  "AP_I2C_DPBRDG_SCL_1V8",
+			  "AP_I2C_DPBRDG_SDA_1V8",
+			  "NC",
+			  "NC",
+			  "AP_I2C_AUD_SCL_1V8",
+			  "AP_I2C_AUD_SDA_1V8",
+			  "AP_I2C_DISP_SCL_1V8",
+			  "AP_I2C_DISP_SDA_1V8",
+			  "NC",
+			  "NC",
+			  "NC",
+			  "NC",
+			  "SCP_I2C_SENSOR_SCL_1V8",
+			  "SCP_I2C_SENSOR_SDA_1V8",
+			  "AP_EC_WARM_RST_REQ",
+			  "AP_XHCI_INIT_DONE",
+			  "USB3_HUB_RST_L",
+			  "EN_SPKR",
+			  "BEEP_ON",
+			  "AP_DISP_BKLTEN",
+			  "EN_PP6000_MIPI_DISP",
+			  "EN_PP6000_MIPI_DISP_150MA",
+			  "BT_KILL_1V8_L",
+			  "WIFI_KILL_1V8_L",
+			  "PWRAP_SPI0_CSN",
+			  "PWRAP_SPI0_CK",
+			  "PWRAP_SPI0_MO",
+			  "PWRAP_SPI0_MI",
+			  "SRCLKENA0",
+			  "SRCLKENA1",
+			  "SCP_VREQ_VAO",
+			  "AP_RTC_CLK32K",
+			  "AP_PMIC_WDTRST_L",
+			  "AUD_CLK_MOSI",
+			  "AUD_SYNC_MOSI",
+			  "AUD_DAT_MOSI0",
+			  "AUD_DAT_MOSI1",
+			  "AUD_CLK_MISO",
+			  "AUD_SYNC_MISO",
+			  "AUD_DAT_MISO0",
+			  "AUD_DAT_MISO1",
+			  "NC",
+			  "NC",
+			  "NC",
+			  "DPBRDG_RST_L",
+			  "LTE_W_DISABLE_L",
+			  "LTE_SAR_DETECT_L",
+			  "EN_PP3300_LTE_X",
+			  "LTE_PWR_OFF_L",
+			  "LTE_RESET_L",
+			  "TP",
+			  "TP";
+
+	dpi_default_pins: dpi-default-pins {
+		pins-cmd-dat {
+			pinmux = <PINMUX_GPIO103__FUNC_GPIO103>,
+				 <PINMUX_GPIO104__FUNC_GPIO104>,
+				 <PINMUX_GPIO105__FUNC_GPIO105>,
+				 <PINMUX_GPIO106__FUNC_GPIO106>,
+				 <PINMUX_GPIO107__FUNC_GPIO107>,
+				 <PINMUX_GPIO108__FUNC_GPIO108>,
+				 <PINMUX_GPIO109__FUNC_GPIO109>,
+				 <PINMUX_GPIO110__FUNC_GPIO110>,
+				 <PINMUX_GPIO111__FUNC_GPIO111>,
+				 <PINMUX_GPIO112__FUNC_GPIO112>,
+				 <PINMUX_GPIO113__FUNC_GPIO113>,
+				 <PINMUX_GPIO114__FUNC_GPIO114>,
+				 <PINMUX_GPIO101__FUNC_GPIO101>,
+				 <PINMUX_GPIO100__FUNC_GPIO100>,
+				 <PINMUX_GPIO102__FUNC_GPIO102>,
+				 <PINMUX_GPIO99__FUNC_GPIO99>;
+			drive-strength = <10>;
+			output-low;
+		};
+	};
+
+	dpi_func_pins: dpi-func-pins {
+		pins-cmd-dat {
+			pinmux = <PINMUX_GPIO103__FUNC_DPI_DATA0>,
+				 <PINMUX_GPIO104__FUNC_DPI_DATA1>,
+				 <PINMUX_GPIO105__FUNC_DPI_DATA2>,
+				 <PINMUX_GPIO106__FUNC_DPI_DATA3>,
+				 <PINMUX_GPIO107__FUNC_DPI_DATA4>,
+				 <PINMUX_GPIO108__FUNC_DPI_DATA5>,
+				 <PINMUX_GPIO109__FUNC_DPI_DATA6>,
+				 <PINMUX_GPIO110__FUNC_DPI_DATA7>,
+				 <PINMUX_GPIO111__FUNC_DPI_DATA8>,
+				 <PINMUX_GPIO112__FUNC_DPI_DATA9>,
+				 <PINMUX_GPIO113__FUNC_DPI_DATA10>,
+				 <PINMUX_GPIO114__FUNC_DPI_DATA11>,
+				 <PINMUX_GPIO101__FUNC_DPI_HSYNC>,
+				 <PINMUX_GPIO100__FUNC_DPI_VSYNC>,
+				 <PINMUX_GPIO102__FUNC_DPI_DE>,
+				 <PINMUX_GPIO99__FUNC_DPI_PCLK>;
+			drive-strength = <10>;
+		};
+	};
+
+	en_pp6000_mipi_disp_150ma_fixed_pins: en_pp6000-mipi-disp-150ma-fixed-pins {
+		pins-en {
+			pinmux = <PINMUX_GPIO154__FUNC_GPIO154>;
+			output-low;
+		};
+	};
+
+	panel_default_pins: panel-default-pins {
+		pins-en {
+			pinmux = <PINMUX_GPIO98__FUNC_GPIO98>;
+			output-low;
+		};
+	};
+};
+
+&usb_c1 {
+	status = "disabled";
+};
+
+&thermal_zones {
+	tboard1-thermal {
+		polling-delay = <1000>; /* milliseconds */
+		polling-delay-passive = <0>; /* milliseconds */
+		thermal-sensors = <&tboard_thermistor1>;
+	};
+
+	tboard2-thermal {
+		polling-delay = <1000>; /* milliseconds */
+		polling-delay-passive = <0>; /* milliseconds */
+		thermal-sensors = <&tboard_thermistor2>;
+	};
+};
+
+&wifi_pwrseq {
+	reset-gpios = <&pio 51 1>;
+};
+
+/*
+ * Battery on Starmie is using a different address than default.
+ * Remove old node to reuse "battery" alias.
+ */
+/delete-node/ &battery;
+&i2c_tunnel {
+	battery: sbs-battery@f {
+		compatible = "sbs,sbs-battery";
+		reg = <0xf>;
+		sbs,i2c-retry-count = <2>;
+		sbs,poll-retry-count = <1>;
+	};
+};
diff --git a/dts/upstream/src/arm64/mediatek/mt8186-corsola.dtsi b/dts/upstream/src/arm64/mediatek/mt8186-corsola.dtsi
index cfcc7909dfe..cebb134331f 100644
--- a/dts/upstream/src/arm64/mediatek/mt8186-corsola.dtsi
+++ b/dts/upstream/src/arm64/mediatek/mt8186-corsola.dtsi
@@ -424,6 +424,7 @@
 		ovdd-supply = <&mt6366_vsim2_reg>;
 		pwr18-supply = <&pp1800_dpbrdg_dx>;
 		reset-gpios = <&pio 177 GPIO_ACTIVE_LOW>;
+		extcon = <&usbc_extcon>;
 
 		ports {
 			#address-cells = <1>;
@@ -1275,7 +1276,7 @@
 		interrupts-extended = <&pio 201 IRQ_TYPE_LEVEL_HIGH>;
 		#interrupt-cells = <2>;
 
-		mt6366codec: codec {
+		mt6366codec: audio-codec {
 			compatible = "mediatek,mt6366-sound", "mediatek,mt6358-sound";
 			Avdd-supply = <&mt6366_vaud28_reg>;
 			mediatek,dmic-mode = <1>; /* one-wire */
@@ -1656,6 +1657,11 @@
 				try-power-role = "source";
 			};
 		};
+
+		usbc_extcon: extcon0 {
+			compatible = "google,extcon-usbc-cros-ec";
+			google,usb-port-id = <0>;
+		};
 	};
 };
 
diff --git a/dts/upstream/src/arm64/mediatek/mt8186.dtsi b/dts/upstream/src/arm64/mediatek/mt8186.dtsi
index d3c3c2a40ad..b91f88ffae0 100644
--- a/dts/upstream/src/arm64/mediatek/mt8186.dtsi
+++ b/dts/upstream/src/arm64/mediatek/mt8186.dtsi
@@ -1577,6 +1577,8 @@
 			#address-cells = <2>;
 			#size-cells = <2>;
 			ranges;
+			wakeup-source;
+			mediatek,syscon-wakeup = <&pericfg 0x420 2>;
 			status = "disabled";
 
 			usb_host0: usb@11200000 {
@@ -1590,8 +1592,6 @@
 					 <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_XHCI>;
 				clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", "xhci_ck";
 				interrupts = <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH 0>;
-				mediatek,syscon-wakeup = <&pericfg 0x420 2>;
-				wakeup-source;
 				status = "disabled";
 			};
 		};
@@ -1643,6 +1643,8 @@
 			#address-cells = <2>;
 			#size-cells = <2>;
 			ranges;
+			wakeup-source;
+			mediatek,syscon-wakeup = <&pericfg 0x424 2>;
 			status = "disabled";
 
 			usb_host1: usb@11280000 {
@@ -1656,8 +1658,6 @@
 					 <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_XHCI>;
 				clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck","xhci_ck";
 				interrupts = <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH 0>;
-				mediatek,syscon-wakeup = <&pericfg 0x424 2>;
-				wakeup-source;
 				status = "disabled";
 			};
 		};
diff --git a/dts/upstream/src/arm64/mediatek/mt8188-geralt-ciri-sku0.dts b/dts/upstream/src/arm64/mediatek/mt8188-geralt-ciri-sku0.dts
new file mode 100644
index 00000000000..79d6d12394b
--- /dev/null
+++ b/dts/upstream/src/arm64/mediatek/mt8188-geralt-ciri-sku0.dts
@@ -0,0 +1,32 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright 2023 Google LLC
+ */
+/dts-v1/;
+#include "mt8188-geralt-ciri.dtsi"
+
+/ {
+	model = "Google Ciri sku0 board";
+	compatible = "google,ciri-sku0", "google,ciri", "mediatek,mt8188";
+};
+
+&dsi_panel {
+	compatible = "boe,nv110wum-l60", "himax,hx83102";
+};
+
+&sound {
+	compatible = "mediatek,mt8188-rt5682s";
+	model = "mt8188_m98390_5682";
+
+	audio-routing =
+		"ETDM1_OUT", "ETDM_SPK_PIN",
+		"ETDM2_OUT", "ETDM_HP_PIN",
+		"ETDM1_IN", "ETDM_SPK_PIN",
+		"ETDM2_IN", "ETDM_HP_PIN",
+		"ADDA Capture", "MTKAIF_PIN",
+		"Headphone Jack", "HPOL",
+		"Headphone Jack", "HPOR",
+		"IN1P", "Headset Mic",
+		"Left Spk", "Front Left BE_OUT",
+		"Right Spk", "Front Right BE_OUT";
+};
diff --git a/dts/upstream/src/arm64/mediatek/mt8188-geralt-ciri-sku1.dts b/dts/upstream/src/arm64/mediatek/mt8188-geralt-ciri-sku1.dts
new file mode 100644
index 00000000000..ef5ea9d12b1
--- /dev/null
+++ b/dts/upstream/src/arm64/mediatek/mt8188-geralt-ciri-sku1.dts
@@ -0,0 +1,59 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright 2023 Google LLC
+ */
+/dts-v1/;
+#include "mt8188-geralt-ciri.dtsi"
+
+/ {
+	model = "Google Ciri sku1 board";
+	compatible = "google,ciri-sku1", "google,ciri", "mediatek,mt8188";
+};
+
+&dsi_panel {
+	compatible = "ivo,t109nw41", "himax,hx83102";
+};
+
+&i2c0 {
+	/delete-node/ audio-codec@1a;
+
+	es8326: audio-codec@19 {
+		compatible = "everest,es8326";
+		reg = <0x19>;
+		interrupts-extended = <&pio 108 IRQ_TYPE_LEVEL_LOW>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&audio_codec_pins>;
+		#sound-dai-cells = <0>;
+		everest,jack-pol = [0e];
+		everest,interrupt-clk = [00];
+	};
+};
+
+&sound {
+	compatible = "mediatek,mt8188-es8326";
+	model = "mt8188_m98390_8326";
+
+	audio-routing =
+		"ETDM1_OUT", "ETDM_SPK_PIN",
+		"ETDM2_OUT", "ETDM_HP_PIN",
+		"ETDM1_IN", "ETDM_SPK_PIN",
+		"ETDM2_IN", "ETDM_HP_PIN",
+		"ADDA Capture", "MTKAIF_PIN",
+		"Headphone Jack", "HPOL",
+		"Headphone Jack", "HPOR",
+		"MIC1", "Headset Mic",
+		"Left Spk", "Front Left BE_OUT",
+		"Right Spk", "Front Right BE_OUT";
+
+	dai-link-2 {
+		codec {
+			sound-dai = <&es8326>;
+		};
+	};
+
+	dai-link-3 {
+		codec {
+			sound-dai = <&es8326>;
+		};
+	};
+};
diff --git a/dts/upstream/src/arm64/mediatek/mt8188-geralt-ciri-sku2.dts b/dts/upstream/src/arm64/mediatek/mt8188-geralt-ciri-sku2.dts
new file mode 100644
index 00000000000..ef56786fc2b
--- /dev/null
+++ b/dts/upstream/src/arm64/mediatek/mt8188-geralt-ciri-sku2.dts
@@ -0,0 +1,59 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright 2024 Google LLC
+ */
+/dts-v1/;
+#include "mt8188-geralt-ciri.dtsi"
+
+/ {
+	model = "Google Ciri sku2 board";
+	compatible = "google,ciri-sku2", "google,ciri", "mediatek,mt8188";
+};
+
+&dsi_panel {
+	compatible = "boe,nv110wum-l60", "himax,hx83102";
+};
+
+&i2c0 {
+	/delete-node/ audio-codec@1a;
+
+	es8326: audio-codec@19 {
+		compatible = "everest,es8326";
+		reg = <0x19>;
+		interrupts-extended = <&pio 108 IRQ_TYPE_LEVEL_LOW>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&audio_codec_pins>;
+		#sound-dai-cells = <0>;
+		everest,jack-pol = [0e];
+		everest,interrupt-clk = [00];
+	};
+};
+
+&sound {
+	compatible = "mediatek,mt8188-es8326";
+	model = "mt8188_m98390_8326";
+
+	audio-routing =
+		"ETDM1_OUT", "ETDM_SPK_PIN",
+		"ETDM2_OUT", "ETDM_HP_PIN",
+		"ETDM1_IN", "ETDM_SPK_PIN",
+		"ETDM2_IN", "ETDM_HP_PIN",
+		"ADDA Capture", "MTKAIF_PIN",
+		"Headphone Jack", "HPOL",
+		"Headphone Jack", "HPOR",
+		"MIC1", "Headset Mic",
+		"Left Spk", "Front Left BE_OUT",
+		"Right Spk", "Front Right BE_OUT";
+
+	dai-link-2 {
+		codec {
+			sound-dai = <&es8326>;
+		};
+	};
+
+	dai-link-3 {
+		codec {
+			sound-dai = <&es8326>;
+		};
+	};
+};
diff --git a/dts/upstream/src/arm64/mediatek/mt8188-geralt-ciri-sku3.dts b/dts/upstream/src/arm64/mediatek/mt8188-geralt-ciri-sku3.dts
new file mode 100644
index 00000000000..524f7f0064c
--- /dev/null
+++ b/dts/upstream/src/arm64/mediatek/mt8188-geralt-ciri-sku3.dts
@@ -0,0 +1,32 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright 2024 Google LLC
+ */
+/dts-v1/;
+#include "mt8188-geralt-ciri.dtsi"
+
+/ {
+	model = "Google Ciri sku3 board";
+	compatible = "google,ciri-sku3", "google,ciri", "mediatek,mt8188";
+};
+
+&dsi_panel {
+	compatible = "ivo,t109nw41", "himax,hx83102";
+};
+
+&sound {
+	compatible = "mediatek,mt8188-rt5682s";
+	model = "mt8188_m98390_5682";
+
+	audio-routing =
+		"ETDM1_OUT", "ETDM_SPK_PIN",
+		"ETDM2_OUT", "ETDM_HP_PIN",
+		"ETDM1_IN", "ETDM_SPK_PIN",
+		"ETDM2_IN", "ETDM_HP_PIN",
+		"ADDA Capture", "MTKAIF_PIN",
+		"Headphone Jack", "HPOL",
+		"Headphone Jack", "HPOR",
+		"IN1P", "Headset Mic",
+		"Left Spk", "Front Left BE_OUT",
+		"Right Spk", "Front Right BE_OUT";
+};
diff --git a/dts/upstream/src/arm64/mediatek/mt8188-geralt-ciri-sku4.dts b/dts/upstream/src/arm64/mediatek/mt8188-geralt-ciri-sku4.dts
new file mode 100644
index 00000000000..ea953d7e154
--- /dev/null
+++ b/dts/upstream/src/arm64/mediatek/mt8188-geralt-ciri-sku4.dts
@@ -0,0 +1,48 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright 2024 Google LLC
+ */
+/dts-v1/;
+#include "mt8188-geralt-ciri.dtsi"
+
+/ {
+	model = "Google Ciri sku4 board (rev4)";
+	compatible = "google,ciri-sku4", "google,ciri", "mediatek,mt8188";
+};
+
+&dsi_panel {
+	compatible = "boe,nv110wum-l60", "himax,hx83102";
+};
+
+&i2c0 {
+	/delete-node/ amplifier@38;
+	/delete-node/ amplifier@39;
+
+	tas2563: amplifier@4f {
+		compatible = "ti,tas2563", "ti,tas2781";
+		reg = <0x4f>, <0x4c>; /* left / right channel */
+		reset-gpios = <&pio 118 GPIO_ACTIVE_HIGH>;
+		#sound-dai-cells = <0>;
+	};
+};
+
+&sound {
+	compatible = "mediatek,mt8188-rt5682s";
+	model = "mt8188_tas2563_5682";
+
+	audio-routing =
+		"ETDM1_OUT", "ETDM_SPK_PIN",
+		"ETDM2_OUT", "ETDM_HP_PIN",
+		"ETDM1_IN", "ETDM_SPK_PIN",
+		"ETDM2_IN", "ETDM_HP_PIN",
+		"ADDA Capture", "MTKAIF_PIN",
+		"Headphone Jack", "HPOL",
+		"Headphone Jack", "HPOR",
+		"IN1P", "Headset Mic";
+
+	dai-link-1 {
+		codec {
+			sound-dai = <&tas2563>;
+		};
+	};
+};
diff --git a/dts/upstream/src/arm64/mediatek/mt8188-geralt-ciri-sku5.dts b/dts/upstream/src/arm64/mediatek/mt8188-geralt-ciri-sku5.dts
new file mode 100644
index 00000000000..bf87201ccf2
--- /dev/null
+++ b/dts/upstream/src/arm64/mediatek/mt8188-geralt-ciri-sku5.dts
@@ -0,0 +1,72 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright 2024 Google LLC
+ */
+/dts-v1/;
+#include "mt8188-geralt-ciri.dtsi"
+
+/ {
+	model = "Google Ciri sku5 board (rev4)";
+	compatible = "google,ciri-sku5", "google,ciri", "mediatek,mt8188";
+};
+
+&dsi_panel {
+	compatible = "ivo,t109nw41", "himax,hx83102";
+};
+
+&i2c0 {
+	/delete-node/ audio-codec@1a;
+	/delete-node/ amplifier@38;
+	/delete-node/ amplifier@39;
+
+	es8326: audio-codec@19 {
+		compatible = "everest,es8326";
+		reg = <0x19>;
+		interrupts-extended = <&pio 108 IRQ_TYPE_LEVEL_LOW>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&audio_codec_pins>;
+		#sound-dai-cells = <0>;
+		everest,jack-pol = [0e];
+		everest,interrupt-clk = [00];
+	};
+
+	tas2563: amplifier@4f {
+		compatible = "ti,tas2563", "ti,tas2781";
+		reg = <0x4f>, <0x4c>; /* left / right channel */
+		reset-gpios = <&pio 118 GPIO_ACTIVE_HIGH>;
+		#sound-dai-cells = <0>;
+	};
+};
+
+&sound {
+	compatible = "mediatek,mt8188-es8326";
+	model = "mt8188_tas2563_8326";
+
+	audio-routing =
+		"ETDM1_OUT", "ETDM_SPK_PIN",
+		"ETDM2_OUT", "ETDM_HP_PIN",
+		"ETDM1_IN", "ETDM_SPK_PIN",
+		"ETDM2_IN", "ETDM_HP_PIN",
+		"ADDA Capture", "MTKAIF_PIN",
+		"Headphone Jack", "HPOL",
+		"Headphone Jack", "HPOR",
+		"MIC1", "Headset Mic";
+
+	dai-link-1 {
+		codec {
+			sound-dai = <&tas2563>;
+		};
+	};
+
+	dai-link-2 {
+		codec {
+			sound-dai = <&es8326>;
+		};
+	};
+
+	dai-link-3 {
+		codec {
+			sound-dai = <&es8326>;
+		};
+	};
+};
diff --git a/dts/upstream/src/arm64/mediatek/mt8188-geralt-ciri-sku6.dts b/dts/upstream/src/arm64/mediatek/mt8188-geralt-ciri-sku6.dts
new file mode 100644
index 00000000000..17d7359dfb6
--- /dev/null
+++ b/dts/upstream/src/arm64/mediatek/mt8188-geralt-ciri-sku6.dts
@@ -0,0 +1,72 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright 2024 Google LLC
+ */
+/dts-v1/;
+#include "mt8188-geralt-ciri.dtsi"
+
+/ {
+	model = "Google Ciri sku6 board (rev4)";
+	compatible = "google,ciri-sku6", "google,ciri", "mediatek,mt8188";
+};
+
+&dsi_panel {
+	compatible = "boe,nv110wum-l60", "himax,hx83102";
+};
+
+&i2c0 {
+	/delete-node/ audio-codec@1a;
+	/delete-node/ amplifier@38;
+	/delete-node/ amplifier@39;
+
+	es8326: audio-codec@19 {
+		compatible = "everest,es8326";
+		reg = <0x19>;
+		interrupts-extended = <&pio 108 IRQ_TYPE_LEVEL_LOW>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&audio_codec_pins>;
+		#sound-dai-cells = <0>;
+		everest,jack-pol = [0e];
+		everest,interrupt-clk = [00];
+	};
+
+	tas2563: amplifier@4f {
+		compatible = "ti,tas2563", "ti,tas2781";
+		reg = <0x4f>, <0x4c>; /* left / right channel */
+		reset-gpios = <&pio 118 GPIO_ACTIVE_HIGH>;
+		#sound-dai-cells = <0>;
+	};
+};
+
+&sound {
+	compatible = "mediatek,mt8188-es8326";
+	model = "mt8188_tas2563_8326";
+
+	audio-routing =
+		"ETDM1_OUT", "ETDM_SPK_PIN",
+		"ETDM2_OUT", "ETDM_HP_PIN",
+		"ETDM1_IN", "ETDM_SPK_PIN",
+		"ETDM2_IN", "ETDM_HP_PIN",
+		"ADDA Capture", "MTKAIF_PIN",
+		"Headphone Jack", "HPOL",
+		"Headphone Jack", "HPOR",
+		"MIC1", "Headset Mic";
+
+	dai-link-1 {
+		codec {
+			sound-dai = <&tas2563>;
+		};
+	};
+
+	dai-link-2 {
+		codec {
+			sound-dai = <&es8326>;
+		};
+	};
+
+	dai-link-3 {
+		codec {
+			sound-dai = <&es8326>;
+		};
+	};
+};
diff --git a/dts/upstream/src/arm64/mediatek/mt8188-geralt-ciri-sku7.dts b/dts/upstream/src/arm64/mediatek/mt8188-geralt-ciri-sku7.dts
new file mode 100644
index 00000000000..825015b452d
--- /dev/null
+++ b/dts/upstream/src/arm64/mediatek/mt8188-geralt-ciri-sku7.dts
@@ -0,0 +1,48 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright 2024 Google LLC
+ */
+/dts-v1/;
+#include "mt8188-geralt-ciri.dtsi"
+
+/ {
+	model = "Google Ciri sku7 board (rev4)";
+	compatible = "google,ciri-sku7", "google,ciri", "mediatek,mt8188";
+};
+
+&dsi_panel {
+	compatible = "ivo,t109nw41", "himax,hx83102";
+};
+
+&i2c0 {
+	/delete-node/ amplifier@38;
+	/delete-node/ amplifier@39;
+
+	tas2563: amplifier@4f {
+		compatible = "ti,tas2563", "ti,tas2781";
+		reg = <0x4f>, <0x4c>; /* left / right channel */
+		reset-gpios = <&pio 118 GPIO_ACTIVE_HIGH>;
+		#sound-dai-cells = <0>;
+	};
+};
+
+&sound {
+	compatible = "mediatek,mt8188-rt5682s";
+	model = "mt8188_tas2563_5682";
+
+	audio-routing =
+		"ETDM1_OUT", "ETDM_SPK_PIN",
+		"ETDM2_OUT", "ETDM_HP_PIN",
+		"ETDM1_IN", "ETDM_SPK_PIN",
+		"ETDM2_IN", "ETDM_HP_PIN",
+		"ADDA Capture", "MTKAIF_PIN",
+		"Headphone Jack", "HPOL",
+		"Headphone Jack", "HPOR",
+		"IN1P", "Headset Mic";
+
+	dai-link-1 {
+		codec {
+			sound-dai = <&tas2563>;
+		};
+	};
+};
diff --git a/dts/upstream/src/arm64/mediatek/mt8188-geralt-ciri.dtsi b/dts/upstream/src/arm64/mediatek/mt8188-geralt-ciri.dtsi
new file mode 100644
index 00000000000..6815c435a57
--- /dev/null
+++ b/dts/upstream/src/arm64/mediatek/mt8188-geralt-ciri.dtsi
@@ -0,0 +1,316 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright 2023 Google LLC
+ */
+/dts-v1/;
+#include "mt8188-geralt.dtsi"
+
+&aud_etdm_hp_on {
+	pins-mclk {
+		pinmux = <PINMUX_GPIO114__FUNC_O_I2SO2_MCK>;
+	};
+};
+
+&aud_etdm_hp_off {
+	pins-mclk {
+		pinmux = <PINMUX_GPIO114__FUNC_B_GPIO114>;
+		bias-pull-down;
+		input-enable;
+	};
+};
+
+&i2c0 {
+	rt5682s: audio-codec@1a {
+		compatible = "realtek,rt5682s";
+		reg = <0x1a>;
+		interrupts-extended = <&pio 108 IRQ_TYPE_EDGE_BOTH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&audio_codec_pins>;
+		#sound-dai-cells = <1>;
+
+		AVDD-supply = <&mt6359_vio18_ldo_reg>;
+		DBVDD-supply = <&mt6359_vio18_ldo_reg>;
+		LDO1-IN-supply = <&mt6359_vio18_ldo_reg>;
+		MICVDD-supply = <&pp3300_s3>;
+		realtek,jd-src = <1>;
+	};
+
+	max98390_38: amplifier@38 {
+		compatible = "maxim,max98390";
+		reg = <0x38>;
+		sound-name-prefix = "Front Right";
+		reset-gpios = <&pio 118 GPIO_ACTIVE_LOW>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&speaker_en>;
+		#sound-dai-cells = <0>;
+	};
+
+	max98390_39: amplifier@39 {
+		compatible = "maxim,max98390";
+		reg = <0x39>;
+		sound-name-prefix = "Front Left";
+		#sound-dai-cells = <0>;
+	};
+};
+
+&i2c_tunnel {
+	/*
+	 * The virtual battery I2C addr is 0xf on Ciri, so we describe it
+	 * manually instead of including 'arm/cros-ec-sbs.dtsi'.
+	 **/
+	battery: sbs-battery@f {
+		compatible = "sbs,sbs-battery";
+		reg = <0xf>;
+		sbs,i2c-retry-count = <2>;
+		sbs,poll-retry-count = <1>;
+	};
+};
+
+&mipi_tx_config0 {
+	drive-strength-microamp = <5200>;
+};
+
+&mt6359_vm18_ldo_reg {
+	regulator-min-microvolt = <1800000>;
+	regulator-max-microvolt = <1900000>;
+	regulator-microvolt-offset = <100000>;
+};
+
+&sound {
+	dai-link-0 {
+		link-name = "ETDM1_IN_BE";
+		dai-format = "i2s";
+		mediatek,clk-provider = "cpu";
+	};
+
+	dai-link-1 {
+		link-name = "ETDM1_OUT_BE";
+		dai-format = "i2s";
+		mediatek,clk-provider = "cpu";
+
+		codec {
+			sound-dai = <&max98390_38>,
+				    <&max98390_39>;
+		};
+	};
+
+	dai-link-2 {
+		link-name = "ETDM2_IN_BE";
+		mediatek,clk-provider = "cpu";
+
+		codec {
+			sound-dai = <&rt5682s 0>;
+		};
+	};
+
+	dai-link-3 {
+		link-name = "ETDM2_OUT_BE";
+		mediatek,clk-provider = "cpu";
+
+		codec {
+			sound-dai = <&rt5682s 0>;
+		};
+	};
+
+	dai-link-4 {
+		link-name = "DPTX_BE";
+
+		codec {
+			sound-dai = <&dp_tx>;
+		};
+	};
+};
+
+&pio {
+	gpio-line-names =
+		"GSC_AP_INT_ODL",
+		"AP_DISP_BKLTEN",
+		"",
+		"EN_PPVAR_MIPI_DISP",
+		"EN_PPVAR_MIPI_DISP_150MA",
+		"TCHSCR_RST_1V8_L",
+		"",
+		"",
+		"",
+		"",
+		"",
+		"I2S_SPKR_DATAOUT",
+		"EN_PP3300_WLAN_X",
+		"WIFI_KILL_1V8_L",
+		"BT_KILL_1V8_L",
+		"AP_FLASH_WP_L", /* ... is crossystem ABI. Rev1 schematics call it AP_WP_ODL. */
+		"",
+		"",
+		"WCAM_PWDN_L",
+		"WCAM_RST_L",
+		"UCAM_PWDM_L",
+		"UCAM_RST_L",
+		"WCAM_24M_CLK",
+		"UCAM_24M_CLK",
+		"MT6319_INT",
+		"DISP_RST_1V8_L",
+		"DSIO_DSI_TE",
+		"",
+		"TP",
+		"MIPI_BL_PWM_1V8",
+		"",
+		"UART_AP_TX_GSC_RX",
+		"UART_GSC_TX_AP_RX",
+		"UART_SSPM_TX_DBGCON_RX",
+		"UART_DBGCON_TX_SSPM_RX",
+		"UART_ADSP_TX_DBGCON_RX",
+		"UART_DBGCON_TX_ADSP_RX",
+		"JTAG_AP_TMS",
+		"JTAG_AP_TCK",
+		"JTAG_AP_TDI",
+		"JTAG_AP_TDO",
+		"JTAG_AP_TRST",
+		"AP_KPCOL0",
+		"TP",
+		"",
+		"TP",
+		"EC_AP_HPD_OD",
+		"PCIE_WAKE_1V8_ODL",
+		"PCIE_RST_1V8_L",
+		"PCIE_CLKREQ_1V8_ODL",
+		"",
+		"",
+		"",
+		"",
+		"",
+		"AP_I2C_AUD_SCL_1V8",
+		"AP_I2C_AUD_SDA_1V8",
+		"AP_I2C_TPM_SCL_1V8",
+		"AP_I2C_TPM_SDA_1V8",
+		"AP_I2C_TCHSCR_SCL_1V8",
+		"AP_I2C_TCHSCR_SDA_1V8",
+		"AP_I2C_PMIC_SAR_SCL_1V8",
+		"AP_I2C_PMIC_SAR_SDA_1V8",
+		"AP_I2C_EC_HID_KB_SCL_1V8",
+		"AP_I2C_EC_HID_KB_SDA_1V8",
+		"AP_I2C_UCAM_SCL_1V8",
+		"AP_I2C_UCAM_SDA_1V8",
+		"AP_I2C_WCAM_SCL_1V8",
+		"AP_I2C_WCAM_SDA_1V8",
+		"SPI_AP_CS_EC_L",
+		"SPI_AP_CLK_EC",
+		"SPI_AP_DO_EC_DI",
+		"SPI_AP_DI_EC_DO",
+		"TP",
+		"TP",
+		"SPI_AP_CS_TCHSCR_L",
+		"SPI_AP_CLK_TCHSCR",
+		"SPI_AP_DO_TCHSCR_DI",
+		"SPI_AP_DI_TCHSCR_DO",
+		"TP",
+		"TP",
+		"TP",
+		"TP",
+		"",
+		"",
+		"",
+		"TP",
+		"",
+		"",
+		"",
+		"",
+		"",
+		"PWRAP_SPI_CS_L",
+		"PWRAP_SPI_CK",
+		"PWRAP_SPI_MOSI",
+		"PWRAP_SPI_MISO",
+		"SRCLKENA0",
+		"SRCLKENA1",
+		"SCP_VREQ_VAO",
+		"AP_RTC_CLK32K",
+		"AP_PMIC_WDTRST_L",
+		"AUD_CLK_MOSI",
+		"AUD_SYNC_MOSI",
+		"AUD_DAT_MOSI0",
+		"AUD_DAT_MOSI1",
+		"AUD_DAT_MISO0",
+		"AUD_DAT_MISO1",
+		"",
+		"HP_INT_ODL",
+		"SPKR_INT_ODL",
+		"I2S_HP_DATAIN",
+		"EN_SPKR",
+		"I2S_SPKR_MCLK",
+		"I2S_SPKR_BCLK",
+		"I2S_HP_MCLK",
+		"I2S_HP_BCLK",
+		"I2S_HP_LRCK",
+		"I2S_HP_DATAOUT",
+		"RST_SPKR_L",
+		"I2S_SPKR_LRCK",
+		"I2S_SPKR_DATAIN",
+		"",
+		"",
+		"",
+		"",
+		"SPI_AP_CLK_ROM",
+		"SPI_AP_CS_ROM_L",
+		"SPI_AP_DO_ROM_DI",
+		"SPI_AP_DI_ROM_DO",
+		"TP",
+		"TP",
+		"",
+		"",
+		"",
+		"",
+		"",
+		"",
+		"",
+		"",
+		"EN_PP2800A_UCAM_X",
+		"EN_PP1200_UCAM_X",
+		"EN_PP2800A_WCAM_X",
+		"EN_PP1100_WCAM_X",
+		"TCHSCR_INT_1V8_L",
+		"",
+		"MT7921_PMU_EN_1V8",
+		"",
+		"AP_EC_WARM_RST_REQ",
+		"EC_AP_HID_INT_ODL",
+		"EC_AP_INT_ODL",
+		"AP_XHCI_INIT_DONE",
+		"EMMC_DAT7",
+		"EMMC_DAT6",
+		"EMMC_DAT5",
+		"EMMC_DAT4",
+		"EMMC_RST_L",
+		"EMMC_CMD",
+		"EMMC_CLK",
+		"EMMC_DAT3",
+		"EMMC_DAT2",
+		"EMMC_DAT1",
+		"EMMC_DAT0",
+		"EMMC_DSL",
+		"",
+		"",
+		"",
+		"",
+		"",
+		"",
+		"",
+		"",
+		"USB3_HUB_RST_L",
+		"EC_AP_RSVD0_ODL",
+		"",
+		"",
+		"SPMI_SCL",
+		"SPMI_SDA";
+
+	audio_codec_pins: audio-codec-pins {
+		pins-hp-int-odl {
+			pinmux = <PINMUX_GPIO108__FUNC_B_GPIO108>;
+			input-enable;
+		};
+	};
+
+	speaker_en: speaker-en-pins {
+		pins-en-spkr {
+			pinmux = <PINMUX_GPIO111__FUNC_B_GPIO111>;
+		};
+	};
+};
diff --git a/dts/upstream/src/arm64/mediatek/mt8188-geralt.dtsi b/dts/upstream/src/arm64/mediatek/mt8188-geralt.dtsi
new file mode 100644
index 00000000000..b6abecbcfa8
--- /dev/null
+++ b/dts/upstream/src/arm64/mediatek/mt8188-geralt.dtsi
@@ -0,0 +1,1156 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2022 MediaTek Inc.
+ */
+/dts-v1/;
+#include <dt-bindings/gpio/gpio.h>
+#include "mt8188.dtsi"
+#include "mt6359.dtsi"
+
+/ {
+	aliases {
+		i2c0 = &i2c0;
+		i2c1 = &i2c1;
+		i2c2 = &i2c2;
+		i2c3 = &i2c3;
+		i2c4 = &i2c4;
+		i2c5 = &i2c5;
+		i2c6 = &i2c6;
+		mmc0 = &mmc0;
+		serial0 = &uart0;
+	};
+
+	backlight_lcd0: backlight-lcd0 {
+		compatible = "pwm-backlight";
+		brightness-levels = <0 1023>;
+		default-brightness-level = <576>;
+		enable-gpios = <&pio 1 GPIO_ACTIVE_HIGH>;
+		num-interpolated-steps = <1023>;
+		power-supply = <&ppvar_sys>;
+		pwms = <&disp_pwm0 0 500000>;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	dmic-codec {
+		compatible = "dmic-codec";
+		num-channels = <2>;
+		wakeup-delay-ms = <100>;
+	};
+
+	memory@40000000 {
+		device_type = "memory";
+		/* The size will be filled in by the bootloader */
+		reg = <0 0x40000000 0 0>;
+	};
+
+	/* system wide LDO 1.8V power rail */
+	pp1800_ldo_z1: regulator-pp1800-ldo-z1 {
+		compatible = "regulator-fixed";
+		regulator-name = "pp1800_ldo_z1";
+		/* controlled by PP3300_Z1 */
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+		vin-supply = <&pp3300_z1>;
+	};
+
+	/* separately switched 3.3V power rail */
+	pp3300_s3: regulator-pp3300-s3 {
+		compatible = "regulator-fixed";
+		regulator-name = "pp3300_s3";
+		/* controlled by PMIC */
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		vin-supply = <&pp3300_z1>;
+	};
+
+	/* system wide 3.3V power rail */
+	pp3300_z1: regulator-pp3300-z1 {
+		compatible = "regulator-fixed";
+		regulator-name = "pp3300_z1";
+		/* controlled by PP3300_LDO_Z5 & EN_PWR_Z1 */
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		vin-supply = <&ppvar_sys>;
+	};
+
+	pp3300_wlan: regulator-pp3300-wlan {
+		compatible = "regulator-fixed";
+		regulator-name = "pp3300_wlan";
+		regulator-always-on;
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		enable-active-high;
+		gpio = <&pio 12 GPIO_ACTIVE_HIGH>;
+		pinctrl-0 = <&wlan_en>;
+		pinctrl-names = "default";
+		vin-supply = <&pp3300_z1>;
+	};
+
+	/* system wide 4.2V power rail */
+	pp4200_s5: regulator-pp4200-s5 {
+		compatible = "regulator-fixed";
+		regulator-name = "pp4200_s5";
+		/* controlled by EC */
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <4200000>;
+		regulator-max-microvolt = <4200000>;
+		vin-supply = <&ppvar_sys>;
+	};
+
+	/* system wide 5.0V power rail */
+	pp5000_z1: regulator-pp5000-z1 {
+		compatible = "regulator-fixed";
+		regulator-name = "pp5000_z1";
+		/* controlled by EC */
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		vin-supply = <&ppvar_sys>;
+	};
+
+	pp5000_usb_vbus: regulator-pp5000-usb-vbus {
+		compatible = "regulator-fixed";
+		regulator-name = "pp5000_usb_vbus";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		enable-active-high;
+		gpio = <&pio 150 GPIO_ACTIVE_HIGH>;
+		vin-supply = <&pp5000_z1>;
+	};
+
+	/* system wide semi-regulated power rail from battery or USB */
+	ppvar_sys: regulator-ppvar-sys {
+		compatible = "regulator-fixed";
+		regulator-name = "ppvar_sys";
+		regulator-always-on;
+		regulator-boot-on;
+	};
+
+	ppvar_mipi_disp_avdd: regulator-ppvar-mipi-disp-avdd {
+		compatible = "regulator-fixed";
+		regulator-name = "ppvar_mipi_disp_avdd";
+		enable-active-high;
+		gpio = <&pio 3 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&mipi_disp_avdd_en>;
+		vin-supply = <&pp5000_z1>;
+	};
+
+	ppvar_mipi_disp_avee: regulator-ppvar-mipi-disp-avee {
+		compatible = "regulator-fixed";
+		regulator-name = "ppvar_mipi_disp_avee";
+		regulator-enable-ramp-delay = <10000>;
+		enable-active-high;
+		gpio = <&pio 4 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&mipi_disp_avee_en>;
+		vin-supply = <&pp5000_z1>;
+	};
+
+	reserved_memory: reserved-memory {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		apu_mem: memory@55000000 {
+			compatible = "shared-dma-pool";
+			reg = <0 0x55000000 0 0x1400000>;
+		};
+
+		adsp_mem: memory@60000000 {
+			compatible = "shared-dma-pool";
+			reg = <0 0x60000000 0 0xf00000>;
+			no-map;
+		};
+
+		afe_dma_mem: memory@60f00000 {
+			compatible = "shared-dma-pool";
+			reg = <0 0x60f00000 0 0x100000>;
+			no-map;
+		};
+
+		adsp_dma_mem: memory@61000000 {
+			compatible = "shared-dma-pool";
+			reg = <0 0x61000000 0 0x100000>;
+			no-map;
+		};
+	};
+};
+
+&adsp {
+	memory-region = <&adsp_dma_mem>, <&adsp_mem>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&adsp_uart_pins>;
+	status = "okay";
+};
+
+&afe {
+	memory-region = <&afe_dma_mem>;
+	mediatek,etdm-out1-cowork-source = <0>; /* in1 */
+	mediatek,etdm-in2-cowork-source = <3>; /* out2 */
+	status = "okay";
+};
+
+&auxadc {
+	status = "okay";
+};
+
+&cam_vcore {
+	domain-supply = <&mt6359_vproc1_buck_reg>;
+};
+
+/*
+ * Geralt is the reference design and doesn't have target TDP.
+ * Ciri is (currently) the only device following Geralt, and its
+ * TDP target is 90 degrees.
+ **/
+&cpu_little0_alert0 {
+	temperature = <90000>;
+	hysteresis = <2000>;
+	type = "passive";
+};
+
+&cpu_little1_alert0 {
+	temperature = <90000>;
+	hysteresis = <2000>;
+	type = "passive";
+};
+
+&cpu_little2_alert0 {
+	temperature = <90000>;
+	hysteresis = <2000>;
+	type = "passive";
+};
+
+&cpu_little3_alert0 {
+	temperature = <90000>;
+	hysteresis = <2000>;
+	type = "passive";
+};
+
+&cpu_big0_alert0 {
+	temperature = <90000>;
+	hysteresis = <2000>;
+	type = "passive";
+};
+
+&cpu_big1_alert0 {
+	temperature = <90000>;
+	hysteresis = <2000>;
+	type = "passive";
+};
+
+&disp_dsi0 {
+	#address-cells = <1>;
+	#size-cells = <0>;
+	status = "okay";
+
+	dsi_panel: panel@0 {
+		/* Compatible string for different panels can be found in each device dts */
+		reg = <0>;
+		enable-gpios = <&pio 25 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&mipi_dsi_pins>;
+
+		backlight = <&backlight_lcd0>;
+		avdd-supply = <&ppvar_mipi_disp_avdd>;
+		avee-supply = <&ppvar_mipi_disp_avee>;
+		pp1800-supply = <&mt6359_vm18_ldo_reg>;
+		rotation = <270>;
+
+		status = "okay";
+
+		port {
+			dsi_panel_in: endpoint {
+				remote-endpoint = <&dsi_out>;
+			};
+		};
+	};
+
+	port {
+		dsi_out: endpoint {
+			remote-endpoint = <&dsi_panel_in>;
+		};
+	};
+};
+
+&disp_pwm0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&disp_pwm0_pins>;
+	status = "okay";
+};
+
+&disp_pwm1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&disp_pwm1_pins>;
+};
+
+&dp_intf1 {
+	status = "okay";
+
+	port {
+		dp_intf1_out: endpoint {
+			remote-endpoint = <&dptx_in>;
+		};
+	};
+};
+
+&dp_tx {
+	pinctrl-names = "default";
+	pinctrl-0 = <&dp_tx_hpd>;
+	#sound-dai-cells = <0>;
+	status = "okay";
+
+	ports {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		port@0 {
+			reg = <0>;
+			dptx_in: endpoint {
+				remote-endpoint = <&dp_intf1_out>;
+			};
+		};
+
+		port@1 {
+			reg = <1>;
+			dptx_out: endpoint {
+				data-lanes = <0 1 2 3>;
+			};
+		};
+	};
+};
+
+&gpu {
+	mali-supply = <&mt6359_vproc2_buck_reg>;
+	status = "okay";
+};
+
+&i2c0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c0_pins>;
+	clock-frequency = <400000>;
+	status = "okay";
+};
+
+&i2c1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c1_pins>;
+	clock-frequency = <400000>;
+	status = "okay";
+
+	tpm@50 {
+		compatible = "google,cr50";
+		reg = <0x50>;
+		interrupts-extended = <&pio 0 IRQ_TYPE_EDGE_RISING>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&gsc_int>;
+	};
+};
+
+&i2c2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c2_pins>;
+	clock-frequency = <400000>;
+	status = "okay";
+};
+
+&i2c3 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c3_pins>;
+	clock-frequency = <400000>;
+	status = "okay";
+};
+
+&i2c4 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c4_pins>;
+	clock-frequency = <400000>;
+	status = "okay";
+};
+
+&i2c5 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c5_pins>;
+	clock-frequency = <400000>;
+	status = "okay";
+};
+
+&i2c6 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c6_pins>;
+	clock-frequency = <400000>;
+	status = "okay";
+};
+
+&mfg0 {
+	domain-supply = <&mt6359_vproc2_buck_reg>;
+};
+
+&mfg1 {
+	domain-supply = <&mt6359_vsram_others_ldo_reg>;
+};
+
+&mipi_tx_config0 {
+	status = "okay";
+};
+
+&mmc0 {
+	bus-width = <8>;
+	cap-mmc-highspeed;
+	cap-mmc-hw-reset;
+	hs400-ds-delay = <0x1481b>;
+	max-frequency = <200000000>;
+	mmc-hs200-1_8v;
+	mmc-hs400-1_8v;
+	mmc-hs400-enhanced-strobe;
+	no-sd;
+	no-sdio;
+	non-removable;
+	pinctrl-names = "default", "state_uhs";
+	pinctrl-0 = <&mmc0_pins_default>;
+	pinctrl-1 = <&mmc0_pins_uhs>;
+	supports-cqe;
+	vmmc-supply = <&mt6359_vemc_1_ldo_reg>;
+	vqmmc-supply = <&mt6359_vufs_ldo_reg>;
+	status = "okay";
+};
+
+&mt6359codec {
+	mediatek,dmic-mode = <1>; /* one-wire */
+	mediatek,mic-type-0 = <2>; /* DMIC */
+	mediatek,mic-type-2 = <2>; /* DMIC */
+};
+
+&mt6359_vcore_buck_reg {
+	regulator-always-on;
+};
+
+&mt6359_vgpu11_buck_reg {
+	regulator-always-on;
+};
+
+&mt6359_vgpu11_sshub_buck_reg {
+	regulator-min-microvolt = <550000>;
+	regulator-max-microvolt = <550000>;
+	regulator-always-on;
+};
+
+&mt6359_vio28_ldo_reg {
+	/delete-property/ regulator-always-on;
+};
+
+&mt6359_vm18_ldo_reg {
+	/delete-property/ regulator-always-on;
+};
+
+&mt6359_vmodem_buck_reg {
+	regulator-min-microvolt = <775000>;
+	regulator-max-microvolt = <775000>;
+};
+
+&mt6359_vpa_buck_reg {
+	regulator-max-microvolt = <3100000>;
+};
+
+&mt6359_vproc2_buck_reg {
+	/*
+	 * Called "ppvar_dvdd_gpu" in the schematic. Renamed to
+	 * "ppvar_dvdd_vgpu" here to match mtk-regulator-coupler requirements.
+	 */
+	regulator-name = "ppvar_dvdd_vgpu";
+	regulator-min-microvolt = <550000>;
+	regulator-max-microvolt = <800000>;
+	regulator-coupled-with = <&mt6359_vsram_others_ldo_reg>;
+	regulator-coupled-max-spread = <6250>;
+};
+
+&mt6359_vpu_buck_reg {
+	regulator-always-on;
+};
+
+&mt6359_vrf12_ldo_reg {
+	regulator-always-on;
+};
+
+&mt6359_vsram_md_ldo_reg {
+	regulator-min-microvolt = <800000>;
+	regulator-max-microvolt = <800000>;
+};
+
+&mt6359_vsram_others_ldo_reg {
+	regulator-name = "pp0850_dvdd_sram_gpu";
+	regulator-min-microvolt = <750000>;
+	regulator-max-microvolt = <800000>;
+	regulator-coupled-with = <&mt6359_vproc2_buck_reg>;
+	regulator-coupled-max-spread = <6250>;
+};
+
+&mt6359_vufs_ldo_reg {
+	regulator-always-on;
+};
+
+&nor_flash {
+	pinctrl-names = "default";
+	pinctrl-0 = <&nor_pins>;
+	status = "okay";
+
+	flash@0 {
+		compatible = "jedec,spi-nor";
+		reg = <0>;
+		spi-max-frequency = <52000000>;
+	};
+};
+
+&pcie {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pcie_pins>;
+	status = "okay";
+};
+
+&pciephy {
+	status = "okay";
+};
+
+&pio {
+	gpio-line-names =
+		"gsc_int",
+		"AP_DISP_BKLTEN",
+		"",
+		"EN_PPVAR_MIPI_DISP",
+		"EN_PPVAR_MIPI_DISP_150MA",
+		"TCHSCR_RST_1V8_L",
+		"TCHSRC_REPORT_DISABLE",
+		"",
+		"",
+		"",
+		"",
+		"I2S_SPKR_DATAOUT",
+		"EN_PP3300_WLAN_X",
+		"WIFI_KILL_1V8_L",
+		"BT_KILL_1V8_L",
+		"AP_FLASH_WP_L", /* ... is crossystem ABI. Rev1 schematics call it AP_WP_ODL. */
+		"",
+		"EDP_HPD_1V8",
+		"WCAM_PWDN_L",
+		"WCAM_RST_L",
+		"UCAM_PWDM_L",
+		"UCAM_RST_L",
+		"WCAM_24M_CLK",
+		"UCAM_24M_CLK",
+		"MT6319_INT",
+		"DISP_RST_1V8_L",
+		"DSIO_DSI_TE",
+		"EN_PP3300_EDP_DISP_X",
+		"TP",
+		"MIPI_BL_PWM_1V8",
+		"EDP_BL_PWM_1V8",
+		"UART_AP_TX_GSC_RX",
+		"UART_GSC_TX_AP_RX",
+		"UART_SSPM_TX_DBGCON_RX",
+		"UART_DBGCON_TX_SSPM_RX",
+		"UART_ADSP_TX_DBGCON_RX",
+		"UART_DBGCON_TX_ADSP_RX",
+		"JTAG_AP_TMS",
+		"JTAG_AP_TCK",
+		"JTAG_AP_TDI",
+		"JTAG_AP_TDO",
+		"JTAG_AP_TRST",
+		"AP_KPCOL0",
+		"TP",
+		"BEEP_ON_OD",
+		"TP",
+		"EC_AP_HPD_OD",
+		"PCIE_WAKE_1V8_ODL",
+		"PCIE_RST_1V8_L",
+		"PCIE_CLKREQ_1V8_ODL",
+		"",
+		"",
+		"",
+		"",
+		"",
+		"AP_I2C_AUD_SCL_1V8",
+		"AP_I2C_AUD_SDA_1V8",
+		"AP_I2C_TPM_SCL_1V8",
+		"AP_I2C_TPM_SDA_1V8",
+		"AP_I2C_TCHSCR_SCL_1V8",
+		"AP_I2C_TCHSCR_SDA_1V8",
+		"AP_I2C_PMIC_SAR_SCL_1V8",
+		"AP_I2C_PMIC_SAR_SDA_1V8",
+		"AP_I2C_EC_HID_KB_SCL_1V8",
+		"AP_I2C_EC_HID_KB_SDA_1V8",
+		"AP_I2C_UCAM_SCL_1V8",
+		"AP_I2C_UCAM_SDA_1V8",
+		"AP_I2C_WCAM_SCL_1V8",
+		"AP_I2C_WCAM_SDA_1V8",
+		"SPI_AP_CS_EC_L",
+		"SPI_AP_CLK_EC",
+		"SPI_AP_DO_EC_DI",
+		"SPI_AP_DI_EC_DO",
+		"TP",
+		"TP",
+		"SPI_AP_CS_TCHSCR_L",
+		"SPI_AP_CLK_TCHSCR",
+		"SPI_AP_DO_TCHSCR_DI",
+		"SPI_AP_DI_TCHSCR_DO",
+		"TP",
+		"TP",
+		"TP",
+		"TP",
+		"",
+		"",
+		"",
+		"TP",
+		"",
+		"SAR_INT_ODL",
+		"",
+		"",
+		"",
+		"PWRAP_SPI_CS_L",
+		"PWRAP_SPI_CK",
+		"PWRAP_SPI_MOSI",
+		"PWRAP_SPI_MISO",
+		"SRCLKENA0",
+		"SRCLKENA1",
+		"SCP_VREQ_VAO",
+		"AP_RTC_CLK32K",
+		"AP_PMIC_WDTRST_L",
+		"AUD_CLK_MOSI",
+		"AUD_SYNC_MOSI",
+		"AUD_DAT_MOSI0",
+		"AUD_DAT_MOSI1",
+		"AUD_DAT_MISO0",
+		"AUD_DAT_MISO1",
+		"SD_CD_ODL",
+		"HP_INT_ODL",
+		"SPKR_INT_ODL",
+		"I2S_HP_DATAIN",
+		"EN_SPKR",
+		"I2S_SPKR_MCLK",
+		"I2S_SPKR_BCLK",
+		"I2S_HP_MCLK",
+		"I2S_HP_BCLK",
+		"I2S_HP_LRCK",
+		"I2S_HP_DATAOUT",
+		"RST_SPKR_L",
+		"I2S_SPKR_LRCK",
+		"I2S_SPKR_DATAIN",
+		"",
+		"",
+		"",
+		"",
+		"SPI_AP_CLK_ROM",
+		"SPI_AP_CS_ROM_L",
+		"SPI_AP_DO_ROM_DI",
+		"SPI_AP_DI_ROM_DO",
+		"TP",
+		"TP",
+		"",
+		"",
+		"",
+		"",
+		"",
+		"",
+		"",
+		"",
+		"EN_PP2800A_UCAM_X",
+		"EN_PP1200_UCAM_X",
+		"EN_PP2800A_WCAM_X",
+		"EN_PP1100_WCAM_X",
+		"TCHSCR_INT_1V8_L",
+		"EN_PP3300_MIPI_TCHSCR_X",
+		"MT7921_PMU_EN_1V8",
+		"EN_PP3300_EDP_TCHSCR_X",
+		"AP_EC_WARM_RST_REQ",
+		"EC_AP_HID_INT_ODL",
+		"EC_AP_INT_ODL",
+		"AP_XHCI_INIT_DONE",
+		"EMMC_DAT7",
+		"EMMC_DAT6",
+		"EMMC_DAT5",
+		"EMMC_DAT4",
+		"EMMC_RST_L",
+		"EMMC_CMD",
+		"EMMC_CLK",
+		"EMMC_DAT3",
+		"EMMC_DAT2",
+		"EMMC_DAT1",
+		"EMMC_DAT0",
+		"EMMC_DSL",
+		"SD_CMD",
+		"SD_CLK",
+		"SD_DAT0",
+		"SD_DAT1",
+		"SD_DAT2",
+		"SD_DAT3",
+		"",
+		"",
+		"USB3_HUB_RST_L",
+		"EC_AP_RSVD0_ODL",
+		"",
+		"",
+		"SPMI_SCL",
+		"SPMI_SDA";
+
+	adsp_uart_pins: adsp-uart-pins {
+		pins-bus {
+			pinmux = <PINMUX_GPIO35__FUNC_O_ADSP_UTXD0>,
+				 <PINMUX_GPIO36__FUNC_I1_ADSP_URXD0>;
+		};
+	};
+
+	aud_etdm_hp_on: aud-etdm-hp-on-pins {
+		pins-bus {
+			pinmux = <PINMUX_GPIO110__FUNC_I0_I2SIN_D0>,
+				 <PINMUX_GPIO115__FUNC_B0_I2SO2_BCK>,
+				 <PINMUX_GPIO116__FUNC_B0_I2SO2_WS>,
+				 <PINMUX_GPIO117__FUNC_O_I2SO2_D0>;
+		};
+	};
+
+	aud_etdm_hp_off: aud-etdm-hp-off-pins {
+		pins-bus {
+			pinmux = <PINMUX_GPIO110__FUNC_B_GPIO110>,
+				 <PINMUX_GPIO115__FUNC_B_GPIO115>,
+				 <PINMUX_GPIO116__FUNC_B_GPIO116>,
+				 <PINMUX_GPIO117__FUNC_B_GPIO117>;
+			bias-pull-down;
+			input-enable;
+		};
+	};
+
+	aud_etdm_spk_on: aud-etdm-spk-on-pins {
+		pins-bus {
+			pinmux = <PINMUX_GPIO11__FUNC_O_I2SO1_D0>,
+				 <PINMUX_GPIO113__FUNC_B0_TDMIN_BCK>,
+				 <PINMUX_GPIO119__FUNC_B0_TDMIN_LRCK>,
+				 <PINMUX_GPIO120__FUNC_I0_TDMIN_DI>;
+			drive-strength = <8>;
+		};
+	};
+
+	aud_etdm_spk_off: aud-etdm-spk-off-pins {
+		pins-bus {
+			pinmux = <PINMUX_GPIO11__FUNC_B_GPIO11>,
+				 <PINMUX_GPIO113__FUNC_B_GPIO113>,
+				 <PINMUX_GPIO119__FUNC_B_GPIO119>,
+				 <PINMUX_GPIO120__FUNC_B_GPIO120>;
+			bias-pull-down;
+			input-enable;
+		};
+	};
+
+	aud_mtkaif_on: aud-mtkaif-on-pins {
+		pins-bus {
+			pinmux = <PINMUX_GPIO101__FUNC_O_AUD_CLK_MOSI>,
+				 <PINMUX_GPIO102__FUNC_O_AUD_SYNC_MOSI>,
+				 <PINMUX_GPIO103__FUNC_O_AUD_DAT_MOSI0>,
+				 <PINMUX_GPIO104__FUNC_O_AUD_DAT_MOSI1>,
+				 <PINMUX_GPIO105__FUNC_I0_AUD_DAT_MISO0>,
+				 <PINMUX_GPIO106__FUNC_I0_AUD_DAT_MISO1>;
+		};
+	};
+
+	aud_mtkaif_off: aud-mtkaif-off-pins {
+		pins-bus {
+			pinmux = <PINMUX_GPIO101__FUNC_B_GPIO101>,
+				 <PINMUX_GPIO102__FUNC_B_GPIO102>,
+				 <PINMUX_GPIO103__FUNC_B_GPIO103>,
+				 <PINMUX_GPIO104__FUNC_B_GPIO104>,
+				 <PINMUX_GPIO105__FUNC_B_GPIO105>,
+				 <PINMUX_GPIO106__FUNC_B_GPIO106>;
+			bias-pull-down;
+			input-enable;
+		};
+	};
+
+	cros_ec_int: cros-ec-int-pins {
+		pins-ec-ap-int-odl {
+			pinmux = <PINMUX_GPIO149__FUNC_B_GPIO149>;
+			input-enable;
+		};
+	};
+
+	disp_pwm0_pins: disp-pwm0-pins {
+		pins-disp-pwm0 {
+			pinmux = <PINMUX_GPIO29__FUNC_O_DISP_PWM0>;
+			output-high;
+		};
+	};
+
+	disp_pwm1_pins: disp-pwm1-pins {
+		pins-disp-pwm1 {
+			pinmux = <PINMUX_GPIO30__FUNC_O_DISP_PWM1>;
+			output-high;
+		};
+	};
+
+	dp_tx_hpd: dp-tx-hpd-pins {
+		pins-dp-tx-hpd {
+			pinmux = <PINMUX_GPIO46__FUNC_I0_DP_TX_HPD>;
+		};
+	};
+
+	gsc_int: gsc-int-pins {
+		pins-gsc-ap-int-odl {
+			pinmux = <PINMUX_GPIO0__FUNC_B_GPIO0>;
+			input-enable;
+		};
+	};
+
+	i2c0_pins: i2c0-pins {
+		pins-bus {
+			pinmux = <PINMUX_GPIO56__FUNC_B1_SDA0>,
+				 <PINMUX_GPIO55__FUNC_B1_SCL0>;
+		};
+	};
+
+	i2c1_pins: i2c1-pins {
+		pins-bus {
+			pinmux = <PINMUX_GPIO58__FUNC_B1_SDA1>,
+				 <PINMUX_GPIO57__FUNC_B1_SCL1>;
+		};
+	};
+
+	i2c2_pins: i2c2-pins {
+		pins-bus {
+			pinmux = <PINMUX_GPIO60__FUNC_B1_SDA2>,
+				 <PINMUX_GPIO59__FUNC_B1_SCL2>;
+			bias-disable;
+			drive-strength = <12>;
+		};
+	};
+
+	i2c3_pins: i2c3-pins {
+		pins-bus {
+			pinmux = <PINMUX_GPIO62__FUNC_B1_SDA3>,
+				 <PINMUX_GPIO61__FUNC_B1_SCL3>;
+		};
+	};
+
+	i2c4_pins: i2c4-pins {
+		pins-bus {
+			pinmux = <PINMUX_GPIO64__FUNC_B1_SDA4>,
+				 <PINMUX_GPIO63__FUNC_B1_SCL4>;
+		};
+	};
+
+	i2c5_pins: i2c5-pins {
+		pins-bus {
+			pinmux = <PINMUX_GPIO66__FUNC_B1_SDA5>,
+				 <PINMUX_GPIO65__FUNC_B1_SCL5>;
+		};
+	};
+
+	i2c6_pins: i2c6-pins {
+		pins-bus {
+			pinmux = <PINMUX_GPIO68__FUNC_B1_SDA6>,
+				 <PINMUX_GPIO67__FUNC_B1_SCL6>;
+		};
+	};
+
+	mipi_disp_avdd_en: mipi-disp-avdd-en-pins {
+		pins-en-ppvar-mipi-disp {
+			pinmux = <PINMUX_GPIO3__FUNC_B_GPIO3>;
+			output-low;
+		};
+	};
+
+	mipi_disp_avee_en: mipi-disp-avee-en-pins {
+		pins-en-ppvar-mipi-disp-150ma {
+			pinmux = <PINMUX_GPIO4__FUNC_B_GPIO4>;
+			output-low;
+		};
+	};
+
+	mipi_dsi_pins: mipi-dsi-pins {
+		pins-bus {
+			pinmux = <PINMUX_GPIO1__FUNC_B_GPIO1>,
+				 <PINMUX_GPIO25__FUNC_B_GPIO25>;
+			output-low;
+		};
+	};
+
+	mmc0_pins_default: mmc0-default-pins {
+		pins-bus {
+			pinmux = <PINMUX_GPIO161__FUNC_B1_MSDC0_DAT0>,
+				 <PINMUX_GPIO160__FUNC_B1_MSDC0_DAT1>,
+				 <PINMUX_GPIO159__FUNC_B1_MSDC0_DAT2>,
+				 <PINMUX_GPIO158__FUNC_B1_MSDC0_DAT3>,
+				 <PINMUX_GPIO154__FUNC_B1_MSDC0_DAT4>,
+				 <PINMUX_GPIO153__FUNC_B1_MSDC0_DAT5>,
+				 <PINMUX_GPIO152__FUNC_B1_MSDC0_DAT6>,
+				 <PINMUX_GPIO151__FUNC_B1_MSDC0_DAT7>,
+				 <PINMUX_GPIO156__FUNC_B1_MSDC0_CMD>;
+			input-enable;
+			drive-strength = <6>;
+			bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
+		};
+
+		pins-clk {
+			pinmux = <PINMUX_GPIO157__FUNC_B1_MSDC0_CLK>;
+			drive-strength = <6>;
+			bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
+		};
+
+		pins-rst {
+			pinmux = <PINMUX_GPIO155__FUNC_O_MSDC0_RSTB>;
+			drive-strength = <6>;
+			bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
+		};
+	};
+
+	mmc0_pins_uhs: mmc0-uhs-pins {
+		pins-bus {
+			pinmux = <PINMUX_GPIO161__FUNC_B1_MSDC0_DAT0>,
+				 <PINMUX_GPIO160__FUNC_B1_MSDC0_DAT1>,
+				 <PINMUX_GPIO159__FUNC_B1_MSDC0_DAT2>,
+				 <PINMUX_GPIO158__FUNC_B1_MSDC0_DAT3>,
+				 <PINMUX_GPIO154__FUNC_B1_MSDC0_DAT4>,
+				 <PINMUX_GPIO153__FUNC_B1_MSDC0_DAT5>,
+				 <PINMUX_GPIO152__FUNC_B1_MSDC0_DAT6>,
+				 <PINMUX_GPIO151__FUNC_B1_MSDC0_DAT7>,
+				 <PINMUX_GPIO156__FUNC_B1_MSDC0_CMD>;
+			input-enable;
+			drive-strength = <8>;
+			bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
+		};
+
+		pins-clk {
+			pinmux = <PINMUX_GPIO157__FUNC_B1_MSDC0_CLK>;
+			drive-strength = <8>;
+			bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
+		};
+
+		pins-ds {
+			pinmux = <PINMUX_GPIO162__FUNC_B0_MSDC0_DSL>;
+			drive-strength = <8>;
+			bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
+		};
+
+		pins-rst {
+			pinmux = <PINMUX_GPIO155__FUNC_O_MSDC0_RSTB>;
+			drive-strength = <8>;
+			bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
+		};
+	};
+
+	nor_pins: nor-default-pins {
+		pins-clk {
+			pinmux = <PINMUX_GPIO127__FUNC_B0_SPINOR_IO0>,
+				 <PINMUX_GPIO125__FUNC_O_SPINOR_CK>,
+				 <PINMUX_GPIO128__FUNC_B0_SPINOR_IO1>;
+			bias-pull-down;
+		};
+
+		pins-cs {
+			pinmux = <PINMUX_GPIO126__FUNC_O_SPINOR_CS>;
+			bias-pull-up;
+		};
+	};
+
+	pcie_pins: pcie-default-pins {
+		pins-bus {
+			pinmux = <PINMUX_GPIO47__FUNC_I1_WAKEN>,
+				 <PINMUX_GPIO48__FUNC_O_PERSTN>,
+				 <PINMUX_GPIO49__FUNC_B1_CLKREQN>;
+		};
+	};
+
+	spi0_pins: spi0-pins {
+		pins-bus {
+			pinmux = <PINMUX_GPIO69__FUNC_O_SPIM0_CSB>,
+				 <PINMUX_GPIO70__FUNC_O_SPIM0_CLK>,
+				 <PINMUX_GPIO71__FUNC_B0_SPIM0_MOSI>,
+				 <PINMUX_GPIO72__FUNC_B0_SPIM0_MISO>;
+			bias-disable;
+		};
+	};
+
+	spi1_pins_default: spi1-default-pins {
+		pins-bus {
+			pinmux = <PINMUX_GPIO75__FUNC_O_SPIM1_CSB>,
+				 <PINMUX_GPIO76__FUNC_O_SPIM1_CLK>,
+				 <PINMUX_GPIO77__FUNC_B0_SPIM1_MOSI>,
+				 <PINMUX_GPIO78__FUNC_B0_SPIM1_MISO>;
+			bias-disable;
+		};
+	};
+
+	spi1_pins_sleep: spi1-sleep-pins {
+		pins-bus {
+			pinmux = <PINMUX_GPIO75__FUNC_B_GPIO75>,
+				 <PINMUX_GPIO76__FUNC_B_GPIO76>,
+				 <PINMUX_GPIO77__FUNC_B_GPIO77>,
+				 <PINMUX_GPIO78__FUNC_B_GPIO78>;
+			bias-pull-down;
+			input-enable;
+		};
+	};
+
+	spi2_pins: spi2-pins {
+		pins-bus {
+			pinmux = <PINMUX_GPIO79__FUNC_O_SPIM2_CSB>,
+				 <PINMUX_GPIO80__FUNC_O_SPIM2_CLK>,
+				 <PINMUX_GPIO81__FUNC_B0_SPIM2_MOSI>,
+				 <PINMUX_GPIO82__FUNC_B0_SPIM2_MISO>;
+			bias-disable;
+		};
+	};
+
+	uart0_pins: uart0-pins {
+		pins-bus {
+			pinmux = <PINMUX_GPIO31__FUNC_O_UTXD0>,
+				 <PINMUX_GPIO32__FUNC_I1_URXD0>;
+			bias-pull-up;
+		};
+	};
+
+	wlan_en: wlan-en-pins {
+		pins-en-pp3300-wlan {
+			pinmux = <PINMUX_GPIO12__FUNC_B_GPIO12>;
+			output-low;
+		};
+	};
+};
+
+&pmic {
+	interrupts-extended = <&pio 222 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&sound {
+	pinctrl-names = "aud_etdm_hp_on", "aud_etdm_hp_off",
+			"aud_etdm_spk_on", "aud_etdm_spk_off",
+			"aud_mtkaif_on", "aud_mtkaif_off";
+	pinctrl-0 = <&aud_etdm_hp_on>;
+	pinctrl-1 = <&aud_etdm_hp_off>;
+	pinctrl-2 = <&aud_etdm_spk_on>;
+	pinctrl-3 = <&aud_etdm_spk_off>;
+	pinctrl-4 = <&aud_mtkaif_on>;
+	pinctrl-5 = <&aud_mtkaif_off>;
+	mediatek,adsp = <&adsp>;
+	/* The audio-routing is defined in each board dts */
+
+	status = "okay";
+};
+
+&spi0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&spi0_pins>;
+	status = "okay";
+
+	cros_ec: ec@0 {
+		compatible = "google,cros-ec-spi";
+		reg = <0>;
+		interrupts-extended = <&pio 149 IRQ_TYPE_LEVEL_LOW>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&cros_ec_int>;
+		spi-max-frequency = <3000000>;
+
+		i2c_tunnel: i2c-tunnel {
+			compatible = "google,cros-ec-i2c-tunnel";
+			google,remote-bus = <1>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		cbas {
+			compatible = "google,cros-cbas";
+		};
+	};
+};
+
+&spi1 {
+	pinctrl-names = "default", "sleep";
+	pinctrl-0 = <&spi1_pins_default>;
+	pinctrl-1 = <&spi1_pins_sleep>;
+	status = "okay";
+};
+
+&spi2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&spi2_pins>;
+	status = "okay";
+};
+
+&uart0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart0_pins>;
+	status = "okay";
+};
+
+&u3phy0 {
+	status = "okay";
+};
+
+&u3phy1 {
+	status = "okay";
+};
+
+&u3phy2 {
+	status = "okay";
+};
+
+/* USB detachable base */
+&xhci0 {
+	/* controlled by EC */
+	vbus-supply = <&pp3300_z1>;
+	status = "okay";
+};
+
+/* USB3 hub */
+&xhci1 {
+	vusb33-supply = <&pp3300_s3>;
+	vbus-supply = <&pp5000_usb_vbus>;
+	status = "okay";
+};
+
+/* USB BT */
+&xhci2 {
+	/* no power supply since MT7921's power is controlled by PCIe */
+	/* MT7921's USB BT has issues with USB2 LPM */
+	usb2-lpm-disable;
+	status = "okay";
+};
+
+#include <arm/cros-ec-keyboard.dtsi>
+
+&keyboard_controller {
+	function-row-physmap = <
+		MATRIX_KEY(0x00, 0x02, 0)	/* T1 */
+		MATRIX_KEY(0x03, 0x02, 0)	/* T2 */
+		MATRIX_KEY(0x02, 0x02, 0)	/* T3 */
+		MATRIX_KEY(0x01, 0x02, 0)	/* T4 */
+		MATRIX_KEY(0x03, 0x04, 0)	/* T5 */
+		MATRIX_KEY(0x02, 0x04, 0)	/* T6 */
+		MATRIX_KEY(0x01, 0x04, 0)	/* T7 */
+		MATRIX_KEY(0x02, 0x09, 0)	/* T8 */
+		MATRIX_KEY(0x01, 0x09, 0)	/* T9 */
+		MATRIX_KEY(0x00, 0x04, 0)	/* T10 */
+	>;
+
+	linux,keymap = <
+		MATRIX_KEY(0x00, 0x02, KEY_BACK)
+		MATRIX_KEY(0x03, 0x02, KEY_REFRESH)
+		MATRIX_KEY(0x02, 0x02, KEY_ZOOM)
+		MATRIX_KEY(0x01, 0x02, KEY_SCALE)
+		MATRIX_KEY(0x03, 0x04, KEY_BRIGHTNESSDOWN)
+		MATRIX_KEY(0x02, 0x04, KEY_BRIGHTNESSUP)
+		MATRIX_KEY(0x01, 0x04, KEY_MICMUTE)
+		MATRIX_KEY(0x02, 0x09, KEY_MUTE)
+		MATRIX_KEY(0x01, 0x09, KEY_VOLUMEDOWN)
+		MATRIX_KEY(0x00, 0x04, KEY_VOLUMEUP)
+		CROS_STD_MAIN_KEYMAP
+	>;
+};
diff --git a/dts/upstream/src/arm64/mediatek/mt8188.dtsi b/dts/upstream/src/arm64/mediatek/mt8188.dtsi
index faccc7f1625..338120930b8 100644
--- a/dts/upstream/src/arm64/mediatek/mt8188.dtsi
+++ b/dts/upstream/src/arm64/mediatek/mt8188.dtsi
@@ -2125,6 +2125,11 @@
 				reg = <0x1ac 0x40>;
 			};
 
+			gpu_speedbin: gpu-speedbin@581 {
+				reg = <0x581 0x1>;
+				bits = <0 3>;
+			};
+
 			socinfo-data1@7a0 {
 				reg = <0x7a0 0x4>;
 			};
@@ -2143,6 +2148,8 @@
 				     <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH 0>,
 				     <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH 0>;
 			interrupt-names = "job", "mmu", "gpu";
+			nvmem-cells = <&gpu_speedbin>;
+			nvmem-cell-names = "speed-bin";
 			operating-points-v2 = <&gpu_opp_table>;
 			power-domains = <&spm MT8188_POWER_DOMAIN_MFG2>,
 					<&spm MT8188_POWER_DOMAIN_MFG3>,
@@ -2488,7 +2495,7 @@
 		};
 
 		ovl0: ovl@1c000000 {
-			compatible = "mediatek,mt8188-disp-ovl", "mediatek,mt8183-disp-ovl";
+			compatible = "mediatek,mt8188-disp-ovl", "mediatek,mt8195-disp-ovl";
 			reg = <0 0x1c000000 0 0x1000>;
 			clocks = <&vdosys0 CLK_VDO0_DISP_OVL0>;
 			interrupts = <GIC_SPI 636 IRQ_TYPE_LEVEL_HIGH 0>;
diff --git a/dts/upstream/src/arm64/mediatek/mt8192-asurada-hayato-r5-sku2.dts b/dts/upstream/src/arm64/mediatek/mt8192-asurada-hayato-r5-sku2.dts
deleted file mode 100644
index cd86ad9ba28..00000000000
--- a/dts/upstream/src/arm64/mediatek/mt8192-asurada-hayato-r5-sku2.dts
+++ /dev/null
@@ -1,65 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
-/*
- * Copyright 2022 Google LLC
- */
-/dts-v1/;
-#include "mt8192-asurada.dtsi"
-
-/ {
-	model = "Google Hayato rev5";
-	chassis-type = "convertible";
-	compatible = "google,hayato-rev5-sku2", "google,hayato-sku2",
-		     "google,hayato", "mediatek,mt8192";
-};
-
-&keyboard_controller {
-	function-row-physmap = <
-		MATRIX_KEY(0x00, 0x02, 0)	/* T1 */
-		MATRIX_KEY(0x03, 0x02, 0)	/* T2 */
-		MATRIX_KEY(0x02, 0x02, 0)	/* T3 */
-		MATRIX_KEY(0x01, 0x02, 0)	/* T4 */
-		MATRIX_KEY(0x03, 0x04, 0)	/* T5 */
-		MATRIX_KEY(0x02, 0x04, 0)	/* T6 */
-		MATRIX_KEY(0x01, 0x04, 0)	/* T7 */
-		MATRIX_KEY(0x02, 0x09, 0)	/* T8 */
-		MATRIX_KEY(0x01, 0x09, 0)	/* T9 */
-		MATRIX_KEY(0x00, 0x04, 0)	/* T10 */
-	>;
-	linux,keymap = <
-		MATRIX_KEY(0x00, 0x02, KEY_BACK)
-		MATRIX_KEY(0x03, 0x02, KEY_FORWARD)
-		MATRIX_KEY(0x02, 0x02, KEY_REFRESH)
-		MATRIX_KEY(0x01, 0x02, KEY_FULL_SCREEN)
-		MATRIX_KEY(0x03, 0x04, KEY_SCALE)
-		MATRIX_KEY(0x02, 0x04, KEY_BRIGHTNESSDOWN)
-		MATRIX_KEY(0x01, 0x04, KEY_BRIGHTNESSUP)
-		MATRIX_KEY(0x02, 0x09, KEY_MUTE)
-		MATRIX_KEY(0x01, 0x09, KEY_VOLUMEDOWN)
-		MATRIX_KEY(0x00, 0x04, KEY_VOLUMEUP)
-
-		CROS_STD_MAIN_KEYMAP
-	>;
-};
-
-&rt5682 {
-	compatible = "realtek,rt5682s";
-};
-
-&sound {
-	compatible = "mediatek,mt8192_mt6359_rt1015p_rt5682s";
-
-	speaker-codecs {
-		sound-dai = <&rt1015p>;
-	};
-
-	headset-codec {
-		sound-dai = <&rt5682 0>;
-	};
-};
-
-&touchscreen {
-	compatible = "hid-over-i2c";
-	post-power-on-delay-ms = <10>;
-	hid-descr-addr = <0x0001>;
-	vdd-supply = <&pp3300_u>;
-};
diff --git a/dts/upstream/src/arm64/mediatek/mt8192-asurada-spherion-r4.dts b/dts/upstream/src/arm64/mediatek/mt8192-asurada-spherion-r4.dts
deleted file mode 100644
index 5e9e598bab9..00000000000
--- a/dts/upstream/src/arm64/mediatek/mt8192-asurada-spherion-r4.dts
+++ /dev/null
@@ -1,78 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
-/*
- * Copyright 2022 Google LLC
- */
-/dts-v1/;
-#include "mt8192-asurada.dtsi"
-#include <dt-bindings/leds/common.h>
-
-/ {
-	model = "Google Spherion (rev4)";
-	chassis-type = "laptop";
-	compatible = "google,spherion-rev4", "google,spherion",
-		     "mediatek,mt8192";
-
-	pwmleds {
-		compatible = "pwm-leds";
-
-		led {
-			function = LED_FUNCTION_KBD_BACKLIGHT;
-			color = <LED_COLOR_ID_WHITE>;
-			pwms = <&cros_ec_pwm 0>;
-			max-brightness = <1023>;
-		};
-	};
-};
-
-&cros_ec_pwm {
-	status = "okay";
-};
-
-&keyboard_controller {
-	function-row-physmap = <
-		MATRIX_KEY(0x00, 0x02, 0)	/* T1 */
-		MATRIX_KEY(0x03, 0x02, 0)	/* T2 */
-		MATRIX_KEY(0x02, 0x02, 0)	/* T3 */
-		MATRIX_KEY(0x01, 0x02, 0)	/* T4 */
-		MATRIX_KEY(0x03, 0x04, 0)	/* T5 */
-		MATRIX_KEY(0x02, 0x04, 0)	/* T6 */
-		MATRIX_KEY(0x01, 0x04, 0)	/* T7 */
-		MATRIX_KEY(0x02, 0x09, 0)	/* T8 */
-		MATRIX_KEY(0x01, 0x09, 0)	/* T9 */
-		MATRIX_KEY(0x00, 0x04, 0)	/* T10 */
-	>;
-	linux,keymap = <
-		MATRIX_KEY(0x00, 0x02, KEY_BACK)
-		MATRIX_KEY(0x03, 0x02, KEY_REFRESH)
-		MATRIX_KEY(0x02, 0x02, KEY_FULL_SCREEN)
-		MATRIX_KEY(0x01, 0x02, KEY_SCALE)
-		MATRIX_KEY(0x03, 0x04, KEY_SYSRQ)
-		MATRIX_KEY(0x02, 0x04, KEY_BRIGHTNESSDOWN)
-		MATRIX_KEY(0x01, 0x04, KEY_BRIGHTNESSUP)
-		MATRIX_KEY(0x02, 0x09, KEY_MUTE)
-		MATRIX_KEY(0x01, 0x09, KEY_VOLUMEDOWN)
-		MATRIX_KEY(0x00, 0x04, KEY_VOLUMEUP)
-
-		CROS_STD_MAIN_KEYMAP
-	>;
-};
-
-&rt5682 {
-	compatible = "realtek,rt5682s";
-};
-
-&sound {
-	compatible = "mediatek,mt8192_mt6359_rt1015p_rt5682s";
-
-	speaker-codecs {
-		sound-dai = <&rt1015p>;
-	};
-
-	headset-codec {
-		sound-dai = <&rt5682 0>;
-	};
-};
-
-&touchscreen {
-	compatible = "elan,ekth3500";
-};
diff --git a/dts/upstream/src/arm64/mediatek/mt8192-asurada.dtsi b/dts/upstream/src/arm64/mediatek/mt8192-asurada.dtsi
index 8dda8b63765..dd0d07fbe61 100644
--- a/dts/upstream/src/arm64/mediatek/mt8192-asurada.dtsi
+++ b/dts/upstream/src/arm64/mediatek/mt8192-asurada.dtsi
@@ -1418,7 +1418,6 @@
 
 		regulators {
 			mt6315_6_vbuck1: vbuck1 {
-				regulator-compatible = "vbuck1";
 				regulator-name = "Vbcpu";
 				regulator-min-microvolt = <400000>;
 				regulator-max-microvolt = <1193750>;
@@ -1428,7 +1427,6 @@
 			};
 
 			mt6315_6_vbuck3: vbuck3 {
-				regulator-compatible = "vbuck3";
 				regulator-name = "Vlcpu";
 				regulator-min-microvolt = <400000>;
 				regulator-max-microvolt = <1193750>;
@@ -1445,7 +1443,6 @@
 
 		regulators {
 			mt6315_7_vbuck1: vbuck1 {
-				regulator-compatible = "vbuck1";
 				regulator-name = "Vgpu";
 				regulator-min-microvolt = <400000>;
 				regulator-max-microvolt = <800000>;
diff --git a/dts/upstream/src/arm64/mediatek/mt8195-cherry.dtsi b/dts/upstream/src/arm64/mediatek/mt8195-cherry.dtsi
index 2c7b2223ee7..5056e07399e 100644
--- a/dts/upstream/src/arm64/mediatek/mt8195-cherry.dtsi
+++ b/dts/upstream/src/arm64/mediatek/mt8195-cherry.dtsi
@@ -1285,7 +1285,6 @@
 
 		regulators {
 			mt6315_6_vbuck1: vbuck1 {
-				regulator-compatible = "vbuck1";
 				regulator-name = "Vbcpu";
 				regulator-min-microvolt = <400000>;
 				regulator-max-microvolt = <1193750>;
@@ -1303,7 +1302,6 @@
 
 		regulators {
 			mt6315_7_vbuck1: vbuck1 {
-				regulator-compatible = "vbuck1";
 				regulator-name = "Vgpu";
 				regulator-min-microvolt = <400000>;
 				regulator-max-microvolt = <1193750>;
diff --git a/dts/upstream/src/arm64/mediatek/mt8195-demo.dts b/dts/upstream/src/arm64/mediatek/mt8195-demo.dts
index 31d424b8fc7..1f59b5786b8 100644
--- a/dts/upstream/src/arm64/mediatek/mt8195-demo.dts
+++ b/dts/upstream/src/arm64/mediatek/mt8195-demo.dts
@@ -109,6 +109,7 @@
 	pinctrl-names = "default", "sleep";
 	pinctrl-0 = <&eth_default_pins>;
 	pinctrl-1 = <&eth_sleep_pins>;
+	mediatek,mac-wol;
 	status = "okay";
 
 	mdio {
@@ -137,7 +138,6 @@
 			richtek,vinovp-microvolt = <14500000>;
 
 			otg_vbus_regulator: usb-otg-vbus-regulator {
-				regulator-compatible = "usb-otg-vbus";
 				regulator-name = "usb-otg-vbus";
 				regulator-min-microvolt = <4425000>;
 				regulator-max-microvolt = <5825000>;
@@ -149,7 +149,6 @@
 			LDO_VIN3-supply = <&mt6360_buck2>;
 
 			mt6360_buck1: buck1 {
-				regulator-compatible = "BUCK1";
 				regulator-name = "mt6360,buck1";
 				regulator-min-microvolt = <300000>;
 				regulator-max-microvolt = <1300000>;
@@ -160,7 +159,6 @@
 			};
 
 			mt6360_buck2: buck2 {
-				regulator-compatible = "BUCK2";
 				regulator-name = "mt6360,buck2";
 				regulator-min-microvolt = <300000>;
 				regulator-max-microvolt = <1300000>;
@@ -171,7 +169,6 @@
 			};
 
 			mt6360_ldo1: ldo1 {
-				regulator-compatible = "LDO1";
 				regulator-name = "mt6360,ldo1";
 				regulator-min-microvolt = <1200000>;
 				regulator-max-microvolt = <3600000>;
@@ -180,7 +177,6 @@
 			};
 
 			mt6360_ldo2: ldo2 {
-				regulator-compatible = "LDO2";
 				regulator-name = "mt6360,ldo2";
 				regulator-min-microvolt = <1200000>;
 				regulator-max-microvolt = <3600000>;
@@ -189,7 +185,6 @@
 			};
 
 			mt6360_ldo3: ldo3 {
-				regulator-compatible = "LDO3";
 				regulator-name = "mt6360,ldo3";
 				regulator-min-microvolt = <1200000>;
 				regulator-max-microvolt = <3600000>;
@@ -198,7 +193,6 @@
 			};
 
 			mt6360_ldo5: ldo5 {
-				regulator-compatible = "LDO5";
 				regulator-name = "mt6360,ldo5";
 				regulator-min-microvolt = <2700000>;
 				regulator-max-microvolt = <3600000>;
@@ -207,7 +201,6 @@
 			};
 
 			mt6360_ldo6: ldo6 {
-				regulator-compatible = "LDO6";
 				regulator-name = "mt6360,ldo6";
 				regulator-min-microvolt = <500000>;
 				regulator-max-microvolt = <2100000>;
@@ -216,7 +209,6 @@
 			};
 
 			mt6360_ldo7: ldo7 {
-				regulator-compatible = "LDO7";
 				regulator-name = "mt6360,ldo7";
 				regulator-min-microvolt = <500000>;
 				regulator-max-microvolt = <2100000>;
diff --git a/dts/upstream/src/arm64/mediatek/mt8195.dtsi b/dts/upstream/src/arm64/mediatek/mt8195.dtsi
index ade685ed219..f013dbad9dc 100644
--- a/dts/upstream/src/arm64/mediatek/mt8195.dtsi
+++ b/dts/upstream/src/arm64/mediatek/mt8195.dtsi
@@ -1611,9 +1611,6 @@
 			phy-names = "pcie-phy";
 			power-domains = <&spm MT8195_POWER_DOMAIN_PCIE_MAC_P1>;
 
-			resets = <&infracfg_ao MT8195_INFRA_RST2_PCIE_P1_SWRST>;
-			reset-names = "mac";
-
 			#interrupt-cells = <1>;
 			interrupt-map-mask = <0 0 0 7>;
 			interrupt-map = <0 0 0 1 &pcie_intc1 0>,
@@ -3138,7 +3135,7 @@
 		};
 
 		ovl0: ovl@1c000000 {
-			compatible = "mediatek,mt8195-disp-ovl", "mediatek,mt8183-disp-ovl";
+			compatible = "mediatek,mt8195-disp-ovl";
 			reg = <0 0x1c000000 0 0x1000>;
 			interrupts = <GIC_SPI 636 IRQ_TYPE_LEVEL_HIGH 0>;
 			power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
diff --git a/dts/upstream/src/arm64/mediatek/mt8365-evk.dts b/dts/upstream/src/arm64/mediatek/mt8365-evk.dts
index 7d90112a7e2..44c61094c4d 100644
--- a/dts/upstream/src/arm64/mediatek/mt8365-evk.dts
+++ b/dts/upstream/src/arm64/mediatek/mt8365-evk.dts
@@ -21,6 +21,7 @@
 
 	aliases {
 		serial0 = &uart0;
+		ethernet = &ethernet;
 	};
 
 	chosen {
diff --git a/dts/upstream/src/arm64/mediatek/mt8365.dtsi b/dts/upstream/src/arm64/mediatek/mt8365.dtsi
index 9c91fe8ea0f..2bf8c9d02b6 100644
--- a/dts/upstream/src/arm64/mediatek/mt8365.dtsi
+++ b/dts/upstream/src/arm64/mediatek/mt8365.dtsi
@@ -449,7 +449,8 @@
 		};
 
 		keypad: keypad@10010000 {
-			compatible = "mediatek,mt6779-keypad";
+			compatible = "mediatek,mt8365-keypad",
+				     "mediatek,mt6779-keypad";
 			reg = <0 0x10010000 0 0x1000>;
 			wakeup-source;
 			interrupts = <GIC_SPI 124 IRQ_TYPE_EDGE_FALLING>;
diff --git a/dts/upstream/src/arm64/mediatek/mt8390-genio-700-evk.dts b/dts/upstream/src/arm64/mediatek/mt8390-genio-700-evk.dts
index 13f2e0e3fa8..04e4a2f7379 100644
--- a/dts/upstream/src/arm64/mediatek/mt8390-genio-700-evk.dts
+++ b/dts/upstream/src/arm64/mediatek/mt8390-genio-700-evk.dts
@@ -93,6 +93,24 @@
 			compatible = "shared-dma-pool";
 			reg = <0 0x57000000 0 0x1400000>; /* 20 MB */
 		};
+
+		adsp_mem: memory@60000000 {
+			compatible = "shared-dma-pool";
+			reg = <0 0x60000000 0 0xf00000>;
+			no-map;
+		};
+
+		afe_dma_mem: memory@60f00000 {
+			compatible = "shared-dma-pool";
+			reg = <0 0x60f00000 0 0x100000>;
+			no-map;
+		};
+
+		adsp_dma_mem: memory@61000000 {
+			compatible = "shared-dma-pool";
+			reg = <0 0x61000000 0 0x100000>;
+			no-map;
+		};
 	};
 
 	common_fixed_5v: regulator-0 {
@@ -210,6 +228,16 @@
 	};
 };
 
+&adsp {
+	memory-region = <&adsp_dma_mem>, <&adsp_mem>;
+	status = "okay";
+};
+
+&afe {
+	memory-region = <&afe_dma_mem>;
+	status = "okay";
+};
+
 &gpu {
 	mali-supply = <&mt6359_vproc2_buck_reg>;
 	status = "okay";
@@ -932,6 +960,26 @@
 	status = "okay";
 };
 
+&sound {
+	compatible = "mediatek,mt8390-mt6359-evk", "mediatek,mt8188-mt6359-evb";
+	model = "mt8390-evk";
+	pinctrl-names = "default";
+	pinctrl-0 = <&audio_default_pins>;
+	audio-routing =
+		"Headphone", "Headphone L",
+		"Headphone", "Headphone R";
+	mediatek,adsp = <&adsp>;
+	status = "okay";
+
+	dai-link-0 {
+		link-name = "DL_SRC_BE";
+
+		codec {
+			sound-dai = <&pmic 0>;
+		};
+	};
+};
+
 &spi2 {
 	pinctrl-0 = <&spi2_pins>;
 	pinctrl-names = "default";
diff --git a/dts/upstream/src/arm64/mediatek/mt8395-genio-1200-evk.dts b/dts/upstream/src/arm64/mediatek/mt8395-genio-1200-evk.dts
index 5f16fb82058..5950194c9cc 100644
--- a/dts/upstream/src/arm64/mediatek/mt8395-genio-1200-evk.dts
+++ b/dts/upstream/src/arm64/mediatek/mt8395-genio-1200-evk.dts
@@ -835,7 +835,6 @@
 
 		regulators {
 			mt6315_6_vbuck1: vbuck1 {
-				regulator-compatible = "vbuck1";
 				regulator-name = "Vbcpu";
 				regulator-min-microvolt = <300000>;
 				regulator-max-microvolt = <1193750>;
@@ -852,7 +851,6 @@
 
 		regulators {
 			mt6315_7_vbuck1: vbuck1 {
-				regulator-compatible = "vbuck1";
 				regulator-name = "Vgpu";
 				regulator-min-microvolt = <546000>;
 				regulator-max-microvolt = <787000>;
diff --git a/dts/upstream/src/arm64/mediatek/mt8395-kontron-3-5-sbc-i1200.dts b/dts/upstream/src/arm64/mediatek/mt8395-kontron-3-5-sbc-i1200.dts
index e2e75b8ff91..4985b65925a 100644
--- a/dts/upstream/src/arm64/mediatek/mt8395-kontron-3-5-sbc-i1200.dts
+++ b/dts/upstream/src/arm64/mediatek/mt8395-kontron-3-5-sbc-i1200.dts
@@ -271,6 +271,7 @@
 	pinctrl-names = "default", "sleep";
 	pinctrl-0 = <&eth_default_pins>;
 	pinctrl-1 = <&eth_sleep_pins>;
+	mediatek,mac-wol;
 	status = "okay";
 
 	mdio {
diff --git a/dts/upstream/src/arm64/mediatek/mt8395-radxa-nio-12l.dts b/dts/upstream/src/arm64/mediatek/mt8395-radxa-nio-12l.dts
index 14ec970c4e4..41dc34837b0 100644
--- a/dts/upstream/src/arm64/mediatek/mt8395-radxa-nio-12l.dts
+++ b/dts/upstream/src/arm64/mediatek/mt8395-radxa-nio-12l.dts
@@ -812,7 +812,6 @@
 
 		regulators {
 			mt6315_6_vbuck1: vbuck1 {
-				regulator-compatible = "vbuck1";
 				regulator-name = "Vbcpu";
 				regulator-min-microvolt = <300000>;
 				regulator-max-microvolt = <1193750>;
@@ -829,7 +828,6 @@
 
 		regulators {
 			mt6315_7_vbuck1: vbuck1 {
-				regulator-compatible = "vbuck1";
 				regulator-name = "Vgpu";
 				regulator-min-microvolt = <300000>;
 				regulator-max-microvolt = <1193750>;
diff --git a/dts/upstream/src/arm64/mediatek/mt8516.dtsi b/dts/upstream/src/arm64/mediatek/mt8516.dtsi
index d0b03dc4d3f..b5e75375946 100644
--- a/dts/upstream/src/arm64/mediatek/mt8516.dtsi
+++ b/dts/upstream/src/arm64/mediatek/mt8516.dtsi
@@ -144,10 +144,10 @@
 		#size-cells = <2>;
 		ranges;
 
-		/* 128 KiB reserved for ARM Trusted Firmware (BL31) */
+		/* 192 KiB reserved for ARM Trusted Firmware (BL31) */
 		bl31_secmon_reserved: secmon@43000000 {
 			no-map;
-			reg = <0 0x43000000 0 0x20000>;
+			reg = <0 0x43000000 0 0x30000>;
 		};
 	};
 
@@ -206,7 +206,7 @@
 			compatible = "mediatek,mt8516-wdt",
 				     "mediatek,mt6589-wdt";
 			reg = <0 0x10007000 0 0x1000>;
-			interrupts = <GIC_SPI 198 IRQ_TYPE_EDGE_FALLING>;
+			interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>;
 			#reset-cells = <1>;
 		};
 
@@ -220,6 +220,17 @@
 			clock-names = "clk13m", "bus";
 		};
 
+		keypad: keypad@10002000 {
+			compatible = "mediatek,mt8516-keypad",
+				     "mediatek,mt6779-keypad";
+			reg = <0 0x10002000 0 0x1000>;
+			wakeup-source;
+			interrupts = <GIC_SPI 149 IRQ_TYPE_EDGE_FALLING>;
+			clocks = <&clk26m>;
+			clock-names = "kpd";
+			status = "disabled";
+		};
+
 		syscfg_pctl: syscfg-pctl@10005000 {
 			compatible = "syscon";
 			reg = <0 0x10005000 0 0x1000>;
@@ -268,7 +279,7 @@
 			interrupt-parent = <&gic>;
 			interrupt-controller;
 			reg = <0 0x10310000 0 0x1000>,
-			      <0 0x10320000 0 0x1000>,
+			      <0 0x1032f000 0 0x2000>,
 			      <0 0x10340000 0 0x2000>,
 			      <0 0x10360000 0 0x2000>;
 			interrupts = <GIC_PPI 9
@@ -344,6 +355,7 @@
 			reg = <0 0x11009000 0 0x90>,
 			      <0 0x11000180 0 0x80>;
 			interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_LOW>;
+			clock-div = <2>;
 			clocks = <&topckgen CLK_TOP_I2C0>,
 				 <&topckgen CLK_TOP_APDMA>;
 			clock-names = "main", "dma";
@@ -358,6 +370,7 @@
 			reg = <0 0x1100a000 0 0x90>,
 			      <0 0x11000200 0 0x80>;
 			interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_LOW>;
+			clock-div = <2>;
 			clocks = <&topckgen CLK_TOP_I2C1>,
 				 <&topckgen CLK_TOP_APDMA>;
 			clock-names = "main", "dma";
@@ -372,6 +385,7 @@
 			reg = <0 0x1100b000 0 0x90>,
 			      <0 0x11000280 0 0x80>;
 			interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>;
+			clock-div = <2>;
 			clocks = <&topckgen CLK_TOP_I2C2>,
 				 <&topckgen CLK_TOP_APDMA>;
 			clock-names = "main", "dma";
diff --git a/dts/upstream/src/arm64/mediatek/pumpkin-common.dtsi b/dts/upstream/src/arm64/mediatek/pumpkin-common.dtsi
index ec8dfb3d1c6..a356db5fcc5 100644
--- a/dts/upstream/src/arm64/mediatek/pumpkin-common.dtsi
+++ b/dts/upstream/src/arm64/mediatek/pumpkin-common.dtsi
@@ -47,7 +47,6 @@
 };
 
 &i2c0 {
-	clock-div = <2>;
 	pinctrl-names = "default";
 	pinctrl-0 = <&i2c0_pins_a>;
 	status = "okay";
@@ -156,7 +155,6 @@
 };
 
 &i2c2 {
-	clock-div = <2>;
 	pinctrl-names = "default";
 	pinctrl-0 = <&i2c2_pins_a>;
 	status = "okay";
diff --git a/dts/upstream/src/arm64/nvidia/tegra234.dtsi b/dts/upstream/src/arm64/nvidia/tegra234.dtsi
index 984c85eab41..2601b43b2d8 100644
--- a/dts/upstream/src/arm64/nvidia/tegra234.dtsi
+++ b/dts/upstream/src/arm64/nvidia/tegra234.dtsi
@@ -3815,7 +3815,7 @@
 			compatible = "nvidia,tegra234-sce-fabric";
 			reg = <0x0 0xb600000 0x0 0x40000>;
 			interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
-			status = "okay";
+			status = "disabled";
 		};
 
 		rce-fabric@be00000 {
@@ -3900,7 +3900,7 @@
 			assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
 			resets = <&bpmp TEGRA234_RESET_SPI2>;
 			reset-names = "spi";
-			dmas = <&gpcdma 19>, <&gpcdma 19>;
+			dmas = <&gpcdma 16>, <&gpcdma 16>;
 			dma-names = "rx", "tx";
 			dma-coherent;
 			status = "disabled";
@@ -3995,7 +3995,7 @@
 		};
 
 		dce-fabric@de00000 {
-			compatible = "nvidia,tegra234-sce-fabric";
+			compatible = "nvidia,tegra234-dce-fabric";
 			reg = <0x0 0xde00000 0x0 0x40000>;
 			interrupts = <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>;
 			status = "okay";
@@ -4018,6 +4018,8 @@
 			#redistributor-regions = <1>;
 			#interrupt-cells = <3>;
 			interrupt-controller;
+
+			#address-cells = <0>;
 		};
 
 		smmu_iso: iommu@10000000 {
diff --git a/dts/upstream/src/arm64/qcom/ipq5332.dtsi b/dts/upstream/src/arm64/qcom/ipq5332.dtsi
index d3c3e215a15..ca3da95730b 100644
--- a/dts/upstream/src/arm64/qcom/ipq5332.dtsi
+++ b/dts/upstream/src/arm64/qcom/ipq5332.dtsi
@@ -180,7 +180,7 @@
 		};
 
 		rng: rng@e3000 {
-			compatible = "qcom,prng-ee";
+			compatible = "qcom,ipq5332-trng", "qcom,trng";
 			reg = <0x000e3000 0x1000>;
 			clocks = <&gcc GCC_PRNG_AHB_CLK>;
 			clock-names = "core";
diff --git a/dts/upstream/src/arm64/qcom/ipq5424-rdp466.dts b/dts/upstream/src/arm64/qcom/ipq5424-rdp466.dts
new file mode 100644
index 00000000000..b6e4bb3328b
--- /dev/null
+++ b/dts/upstream/src/arm64/qcom/ipq5424-rdp466.dts
@@ -0,0 +1,169 @@
+// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
+/*
+ * IPQ5424 RDP466 board device tree source
+ *
+ * Copyright (c) 2024 The Linux Foundation. All rights reserved.
+ */
+
+/dts-v1/;
+
+#include "ipq5424.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. IPQ5424 RDP466";
+	compatible = "qcom,ipq5424-rdp466", "qcom,ipq5424";
+
+	aliases {
+		serial0 = &uart1;
+	};
+
+	vreg_misc_3p3: regulator-usb-3p3 {
+		compatible = "regulator-fixed";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-boot-on;
+		regulator-always-on;
+		regulator-name = "usb_hs_vdda_3p3";
+	};
+
+	vreg_misc_1p8: regulator-usb-1p8 {
+		compatible = "regulator-fixed";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+		regulator-boot-on;
+		regulator-always-on;
+		regulator-name = "vdda_1p8_usb";
+	};
+
+	vreg_misc_0p925: regulator-usb-0p925 {
+		compatible = "regulator-fixed";
+		regulator-min-microvolt = <925000>;
+		regulator-max-microvolt = <925000>;
+		regulator-boot-on;
+		regulator-always-on;
+		regulator-name = "vdd_core_usb";
+	};
+};
+
+&dwc_0 {
+	dr_mode = "host";
+};
+
+&dwc_1 {
+	dr_mode = "host";
+};
+
+&qusb_phy_0 {
+	vdd-supply = <&vreg_misc_0p925>;
+	vdda-pll-supply = <&vreg_misc_1p8>;
+	vdda-phy-dpdm-supply = <&vreg_misc_3p3>;
+
+	status = "okay";
+};
+
+&qusb_phy_1 {
+	vdd-supply = <&vreg_misc_0p925>;
+	vdda-pll-supply = <&vreg_misc_1p8>;
+	vdda-phy-dpdm-supply = <&vreg_misc_3p3>;
+
+	status = "okay";
+};
+
+&sleep_clk {
+	clock-frequency = <32000>;
+};
+
+&spi0 {
+	pinctrl-0 = <&spi0_default_state>;
+	pinctrl-names = "default";
+	status = "okay";
+
+	flash@0 {
+		compatible = "micron,n25q128a11", "jedec,spi-nor";
+		reg = <0>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		spi-max-frequency = <50000000>;
+	};
+};
+
+&ssphy_0 {
+	vdda-pll-supply = <&vreg_misc_1p8>;
+	vdda-phy-supply = <&vreg_misc_0p925>;
+
+	status = "okay";
+};
+
+&tlmm {
+	spi0_default_state: spi0-default-state {
+		clk-pins {
+			pins = "gpio6";
+			function = "spi0_clk";
+			drive-strength = <8>;
+			bias-pull-down;
+		};
+
+		cs-pins {
+			pins = "gpio7";
+			function = "spi0_cs";
+			drive-strength = <8>;
+			bias-pull-up;
+		};
+
+		miso-pins {
+			pins = "gpio8";
+			function = "spi0_miso";
+			drive-strength = <8>;
+			bias-pull-down;
+		};
+
+		mosi-pins {
+			pins = "gpio9";
+			function = "spi0_mosi";
+			drive-strength = <8>;
+			bias-pull-down;
+		};
+	};
+
+	sdc_default_state: sdc-default-state {
+		clk-pins {
+			pins = "gpio5";
+			function = "sdc_clk";
+			drive-strength = <8>;
+			bias-disable;
+		};
+
+		cmd-pins {
+			pins = "gpio4";
+			function = "sdc_cmd";
+			drive-strength = <8>;
+			bias-pull-up;
+		};
+
+		data-pins {
+			pins = "gpio0", "gpio1", "gpio2", "gpio3";
+			function = "sdc_data";
+			drive-strength = <8>;
+			bias-pull-up;
+		};
+	};
+};
+
+&uart1 {
+	pinctrl-0 = <&uart1_pins>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
+&usb2 {
+	status = "okay";
+};
+
+&usb3 {
+	status = "okay";
+};
+
+&xo_board {
+	clock-frequency = <24000000>;
+};
+
diff --git a/dts/upstream/src/arm64/qcom/ipq5424.dtsi b/dts/upstream/src/arm64/qcom/ipq5424.dtsi
new file mode 100644
index 00000000000..7034d378b1e
--- /dev/null
+++ b/dts/upstream/src/arm64/qcom/ipq5424.dtsi
@@ -0,0 +1,519 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * IPQ5424 device tree source
+ *
+ * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved.
+ * Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/qcom,ipq5424-gcc.h>
+#include <dt-bindings/reset/qcom,ipq5424-gcc.h>
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+	#address-cells = <2>;
+	#size-cells = <2>;
+	interrupt-parent = <&intc>;
+
+	clocks {
+		sleep_clk: sleep-clk {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+		};
+
+		xo_board: xo-board-clk {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+		};
+	};
+
+	cpus: cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu0: cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a55";
+			reg = <0x0>;
+			enable-method = "psci";
+			next-level-cache = <&l2_0>;
+			l2_0: l2-cache {
+				compatible = "cache";
+				cache-level = <2>;
+				cache-unified;
+				next-level-cache = <&l3_0>;
+
+				l3_0: l3-cache {
+					compatible = "cache";
+					cache-level = <3>;
+					cache-unified;
+				};
+			};
+		};
+
+		cpu1: cpu@100 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a55";
+			enable-method = "psci";
+			reg = <0x100>;
+			next-level-cache = <&l2_100>;
+
+			l2_100: l2-cache {
+				compatible = "cache";
+				cache-level = <2>;
+				cache-unified;
+				next-level-cache = <&l3_0>;
+			};
+		};
+
+		cpu2: cpu@200 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a55";
+			enable-method = "psci";
+			reg = <0x200>;
+			next-level-cache = <&l2_200>;
+
+			l2_200: l2-cache {
+				compatible = "cache";
+				cache-level = <2>;
+				cache-unified;
+				next-level-cache = <&l3_0>;
+			};
+		};
+
+		cpu3: cpu@300 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a55";
+			enable-method = "psci";
+			reg = <0x300>;
+			next-level-cache = <&l2_300>;
+
+			l2_300: l2-cache {
+				compatible = "cache";
+				cache-level = <2>;
+				cache-unified;
+				next-level-cache = <&l3_0>;
+			};
+		};
+	};
+
+	firmware {
+		scm {
+			compatible = "qcom,scm-ipq5424", "qcom,scm";
+			qcom,dload-mode = <&tcsr 0x25100>;
+		};
+	};
+
+	memory@80000000 {
+		device_type = "memory";
+		/* We expect the bootloader to fill in the size */
+		reg = <0x0 0x80000000 0x0 0x0>;
+	};
+
+	pmu-a55 {
+		compatible = "arm,cortex-a55-pmu";
+		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
+	};
+
+	pmu-dsu {
+		compatible = "arm,dsu-pmu";
+		interrupts = <GIC_SPI 50 IRQ_TYPE_EDGE_RISING>;
+		cpus = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
+	};
+
+	psci {
+		compatible = "arm,psci-1.0";
+		method = "smc";
+	};
+
+	reserved-memory {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		tz@8a600000 {
+			reg = <0x0 0x8a600000 0x0 0x200000>;
+			no-map;
+		};
+
+		smem@8a800000 {
+			compatible = "qcom,smem";
+			reg = <0x0 0x8a800000 0x0 0x32000>;
+			no-map;
+
+			hwlocks = <&tcsr_mutex 3>;
+		};
+	};
+
+	soc@0 {
+		compatible = "simple-bus";
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges = <0 0 0 0 0x10 0>;
+
+		rng: rng@4c3000 {
+			compatible = "qcom,ipq5424-trng", "qcom,trng";
+			reg = <0 0x004c3000 0 0x1000>;
+			clocks = <&gcc GCC_PRNG_AHB_CLK>;
+			clock-names = "core";
+		};
+
+		system-cache-controller@800000 {
+			compatible = "qcom,ipq5424-llcc";
+			reg = <0 0x00800000 0 0x200000>;
+			reg-names = "llcc0_base";
+			interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
+		};
+
+		tlmm: pinctrl@1000000 {
+			compatible = "qcom,ipq5424-tlmm";
+			reg = <0 0x01000000 0 0x300000>;
+			interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			gpio-ranges = <&tlmm 0 0 50>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+
+			uart1_pins: uart1-state {
+				pins = "gpio43", "gpio44";
+				function = "uart1";
+				drive-strength = <8>;
+				bias-pull-up;
+			};
+		};
+
+		gcc: clock-controller@1800000 {
+			compatible = "qcom,ipq5424-gcc";
+			reg = <0 0x01800000 0 0x40000>;
+			clocks = <&xo_board>,
+				 <&sleep_clk>,
+				 <0>,
+				 <0>,
+				 <0>,
+				 <0>,
+				 <0>;
+			#clock-cells = <1>;
+			#reset-cells = <1>;
+			#interconnect-cells = <1>;
+		};
+
+		tcsr_mutex: hwlock@1905000 {
+			compatible = "qcom,tcsr-mutex";
+			reg = <0 0x01905000 0 0x20000>;
+			#hwlock-cells = <1>;
+		};
+
+		tcsr: syscon@1937000 {
+			compatible = "qcom,tcsr-ipq5424", "syscon";
+			reg = <0 0x01937000 0 0x2a000>;
+		};
+
+		qupv3: geniqup@1ac0000 {
+			compatible = "qcom,geni-se-qup";
+			reg = <0 0x01ac0000 0 0x2000>;
+			ranges;
+			clocks = <&gcc GCC_QUPV3_AHB_MST_CLK>,
+				 <&gcc GCC_QUPV3_AHB_SLV_CLK>;
+			clock-names = "m-ahb", "s-ahb";
+			#address-cells = <2>;
+			#size-cells = <2>;
+
+			uart1: serial@1a84000 {
+				compatible = "qcom,geni-debug-uart";
+				reg = <0 0x01a84000 0 0x4000>;
+				clocks = <&gcc GCC_QUPV3_UART1_CLK>;
+				clock-names = "se";
+				interrupts = <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>;
+			};
+
+			spi0: spi@1a90000 {
+				compatible = "qcom,geni-spi";
+				reg = <0 0x01a90000 0 0x4000>;
+				clocks = <&gcc GCC_QUPV3_SPI0_CLK>;
+				clock-names = "se";
+				interrupts = <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				status = "disabled";
+			};
+
+			spi1: spi@1a94000 {
+				compatible = "qcom,geni-spi";
+				reg = <0 0x01a94000 0 0x4000>;
+				clocks = <&gcc GCC_QUPV3_SPI1_CLK>;
+				clock-names = "se";
+				interrupts = <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				status = "disabled";
+			};
+		};
+
+		sdhc: mmc@7804000 {
+			compatible = "qcom,ipq5424-sdhci", "qcom,sdhci-msm-v5";
+			reg = <0 0x07804000 0 0x1000>, <0 0x07805000 0 0x1000>;
+			reg-names = "hc", "cqhci";
+
+			interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "hc_irq", "pwr_irq";
+
+			clocks = <&gcc GCC_SDCC1_AHB_CLK>,
+				 <&gcc GCC_SDCC1_APPS_CLK>,
+				 <&xo_board>;
+			clock-names = "iface", "core", "xo";
+
+			status = "disabled";
+		};
+
+		intc: interrupt-controller@f200000 {
+			compatible = "arm,gic-v3";
+			reg = <0 0xf200000 0 0x10000>, /* GICD */
+			      <0 0xf240000 0 0x80000>; /* GICR * 4 regions */
+			#interrupt-cells = <0x3>;
+			interrupt-controller;
+			#redistributor-regions = <1>;
+			redistributor-stride = <0x0 0x20000>;
+			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+			mbi-ranges = <672 128>;
+			msi-controller;
+		};
+
+		watchdog@f410000 {
+			compatible = "qcom,apss-wdt-ipq5424", "qcom,kpss-wdt";
+			reg = <0 0x0f410000 0 0x1000>;
+			interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>;
+			clocks = <&sleep_clk>;
+		};
+
+		qusb_phy_1: phy@71000 {
+			compatible = "qcom,ipq5424-qusb2-phy";
+			reg = <0 0x00071000 0 0x180>;
+			#phy-cells = <0>;
+
+			clocks = <&gcc GCC_USB1_PHY_CFG_AHB_CLK>,
+				<&xo_board>;
+			clock-names = "cfg_ahb", "ref";
+
+			resets = <&gcc GCC_QUSB2_1_PHY_BCR>;
+			status = "disabled";
+		};
+
+		usb2: usb2@1e00000 {
+			compatible = "qcom,ipq5424-dwc3", "qcom,dwc3";
+			reg = <0 0x01ef8800 0 0x400>;
+			#address-cells = <2>;
+			#size-cells = <2>;
+			ranges;
+
+			clocks = <&gcc GCC_USB1_MASTER_CLK>,
+				 <&gcc GCC_USB1_SLEEP_CLK>,
+				 <&gcc GCC_USB1_MOCK_UTMI_CLK>,
+				 <&gcc GCC_USB1_PHY_CFG_AHB_CLK>,
+				 <&gcc GCC_CNOC_USB_CLK>;
+
+			clock-names = "core",
+				      "sleep",
+				      "mock_utmi",
+				      "iface",
+				      "cfg_noc";
+
+			assigned-clocks = <&gcc GCC_USB1_MASTER_CLK>,
+					  <&gcc GCC_USB1_MOCK_UTMI_CLK>;
+			assigned-clock-rates = <200000000>,
+					       <24000000>;
+
+			interrupts-extended = <&intc GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
+					      <&intc GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
+					      <&intc GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>,
+					      <&intc GIC_SPI 388 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "pwr_event",
+					  "qusb2_phy",
+					  "dm_hs_phy_irq",
+					  "dp_hs_phy_irq";
+
+			resets = <&gcc GCC_USB1_BCR>;
+			qcom,select-utmi-as-pipe-clk;
+			status = "disabled";
+
+			dwc_1: usb@1e00000 {
+				compatible = "snps,dwc3";
+				reg = <0 0x01e00000 0 0xe000>;
+				clocks = <&gcc GCC_USB1_MOCK_UTMI_CLK>;
+				clock-names = "ref";
+				interrupts = <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>;
+				phys = <&qusb_phy_1>;
+				phy-names = "usb2-phy";
+				tx-fifo-resize;
+				snps,is-utmi-l1-suspend;
+				snps,hird-threshold = /bits/ 8 <0x0>;
+				snps,dis_u2_susphy_quirk;
+				snps,dis_u3_susphy_quirk;
+			};
+		};
+
+		qusb_phy_0: phy@7b000 {
+			compatible = "qcom,ipq5424-qusb2-phy";
+			reg = <0 0x0007b000 0 0x180>;
+			#phy-cells = <0>;
+
+			clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
+				<&xo_board>;
+			clock-names = "cfg_ahb", "ref";
+
+			resets = <&gcc GCC_QUSB2_0_PHY_BCR>;
+			status = "disabled";
+		};
+
+		ssphy_0: phy@7d000 {
+			compatible = "qcom,ipq5424-qmp-usb3-phy";
+			reg = <0 0x0007d000 0 0xa00>;
+			#phy-cells = <0>;
+
+			clocks = <&gcc GCC_USB0_AUX_CLK>,
+				 <&xo_board>,
+				 <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
+				 <&gcc GCC_USB0_PIPE_CLK>;
+			clock-names = "aux",
+				      "ref",
+				      "cfg_ahb",
+				      "pipe";
+
+			resets = <&gcc GCC_USB0_PHY_BCR>,
+				 <&gcc GCC_USB3PHY_0_PHY_BCR>;
+			reset-names = "phy",
+				      "phy_phy";
+
+			#clock-cells = <0>;
+			clock-output-names = "usb0_pipe_clk";
+
+			status = "disabled";
+		};
+
+		usb3: usb3@8a00000 {
+			compatible = "qcom,ipq5424-dwc3", "qcom,dwc3";
+			reg = <0 0x08af8800 0 0x400>;
+
+			#address-cells = <2>;
+			#size-cells = <2>;
+			ranges;
+
+			clocks = <&gcc GCC_USB0_MASTER_CLK>,
+				 <&gcc GCC_USB0_SLEEP_CLK>,
+				 <&gcc GCC_USB0_MOCK_UTMI_CLK>,
+				 <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
+				 <&gcc GCC_CNOC_USB_CLK>;
+
+			clock-names = "core",
+				      "sleep",
+				      "mock_utmi",
+				      "iface",
+				      "cfg_noc";
+
+			assigned-clocks = <&gcc GCC_USB0_MASTER_CLK>,
+					  <&gcc GCC_USB0_MOCK_UTMI_CLK>;
+			assigned-clock-rates = <200000000>,
+					       <24000000>;
+
+			interrupts-extended = <&intc GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
+					      <&intc GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>,
+					      <&intc GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
+					      <&intc GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "pwr_event",
+					  "qusb2_phy",
+					  "dm_hs_phy_irq",
+					  "dp_hs_phy_irq";
+
+			resets = <&gcc GCC_USB_BCR>;
+			status = "disabled";
+
+			dwc_0: usb@8a00000 {
+				compatible = "snps,dwc3";
+				reg = <0 0x08a00000 0 0xcd00>;
+				clocks = <&gcc GCC_USB0_MOCK_UTMI_CLK>;
+				clock-names = "ref";
+				interrupts = <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>;
+				phys = <&qusb_phy_0>, <&ssphy_0>;
+				phy-names = "usb2-phy", "usb3-phy";
+				tx-fifo-resize;
+				snps,is-utmi-l1-suspend;
+				snps,hird-threshold = /bits/ 8 <0x0>;
+				snps,dis_u2_susphy_quirk;
+				snps,dis_u3_susphy_quirk;
+				snps,dis-u1-entry-quirk;
+				snps,dis-u2-entry-quirk;
+			};
+		};
+
+		timer@f420000 {
+			compatible = "arm,armv7-timer-mem";
+			reg = <0 0xf420000 0 0x1000>;
+			ranges = <0 0 0 0x10000000>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			frame@f421000 {
+				reg = <0xf421000 0x1000>,
+				      <0xf422000 0x1000>;
+				interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+				frame-number = <0>;
+			};
+
+			frame@f423000 {
+				reg = <0xf423000 0x1000>;
+				interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+				frame-number = <1>;
+				status = "disabled";
+			};
+
+			frame@f425000 {
+				reg = <0xf425000 0x1000>,
+				      <0xf426000 0x1000>;
+				interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+				frame-number = <2>;
+				status = "disabled";
+			};
+
+			frame@f427000 {
+				reg = <0xf427000 0x1000>;
+				interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+				frame-number = <3>;
+				status = "disabled";
+			};
+
+			frame@f429000 {
+				reg = <0xf429000 0x1000>;
+				interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+				frame-number = <4>;
+				status = "disabled";
+			};
+
+			frame@f42b000 {
+				reg = <0xf42b000 0x1000>;
+				interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
+				frame-number = <5>;
+				status = "disabled";
+			};
+
+			frame@f42d000 {
+				reg = <0xf42d000 0x1000>;
+				interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+				frame-number = <6>;
+				status = "disabled";
+			};
+		};
+
+	};
+
+	timer {
+		compatible = "arm,armv8-timer";
+		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
+			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
+			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
+			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>,
+			     <GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>;
+	};
+};
diff --git a/dts/upstream/src/arm64/qcom/ipq9574-rdp-common.dtsi b/dts/upstream/src/arm64/qcom/ipq9574-rdp-common.dtsi
index 91e104b0f86..ae12f069f26 100644
--- a/dts/upstream/src/arm64/qcom/ipq9574-rdp-common.dtsi
+++ b/dts/upstream/src/arm64/qcom/ipq9574-rdp-common.dtsi
@@ -3,7 +3,7 @@
  * IPQ9574 RDP board common device tree source
  *
  * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved.
- * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2023-2024, Qualcomm Innovation Center, Inc. All rights reserved.
  */
 
 /dts-v1/;
@@ -164,6 +164,26 @@
 	status = "okay";
 };
 
+/*
+ * The bootstrap pins for the board select the XO clock frequency
+ * (48 MHZ or 96 MHZ used for different RDP type board). This setting
+ * automatically enables the right dividers, to ensure the reference
+ * clock output from WiFi to the CMN PLL is 48 MHZ.
+ */
+&ref_48mhz_clk {
+	clock-div = <1>;
+	clock-mult = <1>;
+};
+
+/*
+ * The frequency of xo_board_clk is fixed to 24 MHZ, which is routed
+ * from WiFi output clock 48 MHZ divided by 2.
+ */
 &xo_board_clk {
-	clock-frequency = <24000000>;
+	clock-div = <2>;
+	clock-mult = <1>;
+};
+
+&xo_clk {
+	clock-frequency = <48000000>;
 };
diff --git a/dts/upstream/src/arm64/qcom/ipq9574-rdp433.dts b/dts/upstream/src/arm64/qcom/ipq9574-rdp433.dts
index 1bb8d96c9a8..165ebbb5951 100644
--- a/dts/upstream/src/arm64/qcom/ipq9574-rdp433.dts
+++ b/dts/upstream/src/arm64/qcom/ipq9574-rdp433.dts
@@ -8,6 +8,7 @@
 
 /dts-v1/;
 
+#include <dt-bindings/gpio/gpio.h>
 #include "ipq9574-rdp-common.dtsi"
 
 / {
@@ -15,6 +16,45 @@
 	compatible = "qcom,ipq9574-ap-al02-c7", "qcom,ipq9574";
 };
 
+&pcie1_phy {
+	status = "okay";
+};
+
+&pcie1 {
+	pinctrl-0 = <&pcie1_default>;
+	pinctrl-names = "default";
+
+	perst-gpios = <&tlmm 26 GPIO_ACTIVE_LOW>;
+	wake-gpios = <&tlmm 27 GPIO_ACTIVE_LOW>;
+	status = "okay";
+};
+
+&pcie2_phy {
+	status = "okay";
+};
+
+&pcie2 {
+	pinctrl-0 = <&pcie2_default>;
+	pinctrl-names = "default";
+
+	perst-gpios = <&tlmm 29 GPIO_ACTIVE_LOW>;
+	wake-gpios = <&tlmm 30 GPIO_ACTIVE_LOW>;
+	status = "okay";
+};
+
+&pcie3_phy {
+	status = "okay";
+};
+
+&pcie3 {
+	pinctrl-0 = <&pcie3_default>;
+	pinctrl-names = "default";
+
+	perst-gpios = <&tlmm 32 GPIO_ACTIVE_LOW>;
+	wake-gpios = <&tlmm 33 GPIO_ACTIVE_LOW>;
+	status = "okay";
+};
+
 &sdhc_1 {
 	pinctrl-0 = <&sdc_default_state>;
 	pinctrl-names = "default";
@@ -28,6 +68,79 @@
 };
 
 &tlmm {
+
+	pcie1_default: pcie1-default-state {
+		clkreq-n-pins {
+			pins = "gpio25";
+			function = "pcie1_clk";
+			drive-strength = <6>;
+			bias-pull-up;
+		};
+
+		perst-n-pins {
+			pins = "gpio26";
+			function = "gpio";
+			drive-strength = <8>;
+			bias-pull-down;
+			output-low;
+		};
+
+		wake-n-pins {
+			pins = "gpio27";
+			function = "pcie1_wake";
+			drive-strength = <6>;
+			bias-pull-up;
+		};
+	};
+
+	pcie2_default: pcie2-default-state {
+		clkreq-n-pins {
+			pins = "gpio28";
+			function = "pcie2_clk";
+			drive-strength = <6>;
+			bias-pull-up;
+		};
+
+		perst-n-pins {
+			pins = "gpio29";
+			function = "gpio";
+			drive-strength = <8>;
+			bias-pull-down;
+			output-low;
+		};
+
+		wake-n-pins {
+			pins = "gpio30";
+			function = "pcie2_wake";
+			drive-strength = <6>;
+			bias-pull-up;
+		};
+	};
+
+	pcie3_default: pcie3-default-state {
+		clkreq-n-pins {
+			pins = "gpio31";
+			function = "pcie3_clk";
+			drive-strength = <6>;
+			bias-pull-up;
+		};
+
+		perst-n-pins {
+			pins = "gpio32";
+			function = "gpio";
+			drive-strength = <8>;
+			bias-pull-up;
+			output-low;
+		};
+
+		wake-n-pins {
+			pins = "gpio33";
+			function = "pcie3_wake";
+			drive-strength = <6>;
+			bias-pull-up;
+		};
+	};
+
 	sdc_default_state: sdc-default-state {
 		clk-pins {
 			pins = "gpio5";
diff --git a/dts/upstream/src/arm64/qcom/ipq9574.dtsi b/dts/upstream/src/arm64/qcom/ipq9574.dtsi
index d1fd35ebc4a..94229002897 100644
--- a/dts/upstream/src/arm64/qcom/ipq9574.dtsi
+++ b/dts/upstream/src/arm64/qcom/ipq9574.dtsi
@@ -3,10 +3,11 @@
  * IPQ9574 SoC device tree source
  *
  * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved.
- * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2023-2024, Qualcomm Innovation Center, Inc. All rights reserved.
  */
 
 #include <dt-bindings/clock/qcom,apss-ipq.h>
+#include <dt-bindings/clock/qcom,ipq-cmn-pll.h>
 #include <dt-bindings/clock/qcom,ipq9574-gcc.h>
 #include <dt-bindings/interconnect/qcom,ipq9574.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
@@ -19,12 +20,24 @@
 	#size-cells = <2>;
 
 	clocks {
+		ref_48mhz_clk: ref-48mhz-clk {
+			compatible = "fixed-factor-clock";
+			clocks = <&xo_clk>;
+			#clock-cells = <0>;
+		};
+
 		sleep_clk: sleep-clk {
 			compatible = "fixed-clock";
 			#clock-cells = <0>;
 		};
 
 		xo_board_clk: xo-board-clk {
+			compatible = "fixed-factor-clock";
+			clocks = <&ref_48mhz_clk>;
+			#clock-cells = <0>;
+		};
+
+		xo_clk: xo-clk {
 			compatible = "fixed-clock";
 			#clock-cells = <0>;
 		};
@@ -226,8 +239,54 @@
 			reg = <0x00060000 0x6000>;
 		};
 
+		pcie0_phy: phy@84000 {
+			compatible = "qcom,ipq9574-qmp-gen3x1-pcie-phy";
+			reg = <0x00084000 0x1000>;
+
+			clocks = <&gcc GCC_PCIE0_AUX_CLK>,
+				 <&gcc GCC_PCIE0_AHB_CLK>,
+				 <&gcc GCC_PCIE0_PIPE_CLK>;
+			clock-names = "aux", "cfg_ahb", "pipe";
+
+			assigned-clocks = <&gcc GCC_PCIE0_AUX_CLK>;
+			assigned-clock-rates = <20000000>;
+
+			resets = <&gcc GCC_PCIE0_PHY_BCR>,
+				 <&gcc GCC_PCIE0PHY_PHY_BCR>;
+			reset-names = "phy", "common";
+
+			#clock-cells = <0>;
+			clock-output-names = "gcc_pcie0_pipe_clk_src";
+
+			#phy-cells = <0>;
+			status = "disabled";
+		};
+
+		pcie2_phy: phy@8c000 {
+			compatible = "qcom,ipq9574-qmp-gen3x2-pcie-phy";
+			reg = <0x0008c000 0x2000>;
+
+			clocks = <&gcc GCC_PCIE2_AUX_CLK>,
+				 <&gcc GCC_PCIE2_AHB_CLK>,
+				 <&gcc GCC_PCIE2_PIPE_CLK>;
+			clock-names = "aux", "cfg_ahb", "pipe";
+
+			assigned-clocks = <&gcc GCC_PCIE2_AUX_CLK>;
+			assigned-clock-rates = <20000000>;
+
+			resets = <&gcc GCC_PCIE2_PHY_BCR>,
+				 <&gcc GCC_PCIE2PHY_PHY_BCR>;
+			reset-names = "phy", "common";
+
+			#clock-cells = <0>;
+			clock-output-names = "gcc_pcie2_pipe_clk_src";
+
+			#phy-cells = <0>;
+			status = "disabled";
+		};
+
 		rng: rng@e3000 {
-			compatible = "qcom,prng-ee";
+			compatible = "qcom,ipq9574-trng", "qcom,trng";
 			reg = <0x000e3000 0x1000>;
 			clocks = <&gcc GCC_PRNG_AHB_CLK>;
 			clock-names = "core";
@@ -243,6 +302,64 @@
 			status = "disabled";
 		};
 
+		pcie3_phy: phy@f4000 {
+			compatible = "qcom,ipq9574-qmp-gen3x2-pcie-phy";
+			reg = <0x000f4000 0x2000>;
+
+			clocks = <&gcc GCC_PCIE3_AUX_CLK>,
+				 <&gcc GCC_PCIE3_AHB_CLK>,
+				 <&gcc GCC_PCIE3_PIPE_CLK>;
+			clock-names = "aux", "cfg_ahb", "pipe";
+
+			assigned-clocks = <&gcc GCC_PCIE3_AUX_CLK>;
+			assigned-clock-rates = <20000000>;
+
+			resets = <&gcc GCC_PCIE3_PHY_BCR>,
+				 <&gcc GCC_PCIE3PHY_PHY_BCR>;
+			reset-names = "phy", "common";
+
+			#clock-cells = <0>;
+			clock-output-names = "gcc_pcie3_pipe_clk_src";
+
+			#phy-cells = <0>;
+			status = "disabled";
+		};
+
+		pcie1_phy: phy@fc000 {
+			compatible = "qcom,ipq9574-qmp-gen3x1-pcie-phy";
+			reg = <0x000fc000 0x1000>;
+
+			clocks = <&gcc GCC_PCIE1_AUX_CLK>,
+				 <&gcc GCC_PCIE1_AHB_CLK>,
+				 <&gcc GCC_PCIE1_PIPE_CLK>;
+			clock-names = "aux", "cfg_ahb", "pipe";
+
+			assigned-clocks = <&gcc GCC_PCIE1_AUX_CLK>;
+			assigned-clock-rates = <20000000>;
+
+			resets = <&gcc GCC_PCIE1_PHY_BCR>,
+				 <&gcc GCC_PCIE1PHY_PHY_BCR>;
+			reset-names = "phy", "common";
+
+			#clock-cells = <0>;
+			clock-output-names = "gcc_pcie1_pipe_clk_src";
+
+			#phy-cells = <0>;
+			status = "disabled";
+		};
+
+		cmn_pll: clock-controller@9b000 {
+			compatible = "qcom,ipq9574-cmn-pll";
+			reg = <0x0009b000 0x800>;
+			clocks = <&ref_48mhz_clk>,
+				 <&gcc GCC_CMN_12GPLL_AHB_CLK>,
+				 <&gcc GCC_CMN_12GPLL_SYS_CLK>;
+			clock-names = "ref", "ahb", "sys";
+			#clock-cells = <1>;
+			assigned-clocks = <&cmn_pll CMN_PLL_CLK>;
+			assigned-clock-rates-u64 = /bits/ 64 <12000000000>;
+		};
+
 		qfprom: efuse@a4000 {
 			compatible = "qcom,ipq9574-qfprom", "qcom,qfprom";
 			reg = <0x000a4000 0x5a1>;
@@ -309,10 +426,10 @@
 			clocks = <&xo_board_clk>,
 				 <&sleep_clk>,
 				 <0>,
-				 <0>,
-				 <0>,
-				 <0>,
-				 <0>,
+				 <&pcie0_phy>,
+				 <&pcie1_phy>,
+				 <&pcie2_phy>,
+				 <&pcie3_phy>,
 				 <0>;
 			#clock-cells = <1>;
 			#reset-cells = <1>;
@@ -756,6 +873,326 @@
 				status = "disabled";
 			};
 		};
+
+		pcie1: pcie@10000000 {
+			compatible = "qcom,pcie-ipq9574";
+			reg =  <0x10000000 0xf1d>,
+			       <0x10000f20 0xa8>,
+			       <0x10001000 0x1000>,
+			       <0x000f8000 0x4000>,
+			       <0x10100000 0x1000>;
+			reg-names = "dbi", "elbi", "atu", "parf", "config";
+			device_type = "pci";
+			linux,pci-domain = <1>;
+			bus-range = <0x00 0xff>;
+			num-lanes = <1>;
+			#address-cells = <3>;
+			#size-cells = <2>;
+
+			ranges = <0x01000000 0x0 0x00000000 0x10200000 0x0 0x100000>,
+				 <0x02000000 0x0 0x10300000 0x10300000 0x0 0x7d00000>;
+
+			interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "msi0",
+					  "msi1",
+					  "msi2",
+					  "msi3",
+					  "msi4",
+					  "msi5",
+					  "msi6",
+					  "msi7";
+
+			#interrupt-cells = <1>;
+			interrupt-map-mask = <0 0 0 0x7>;
+			interrupt-map = <0 0 0 1 &intc 0 0 35 IRQ_TYPE_LEVEL_HIGH>,
+					<0 0 0 2 &intc 0 0 49 IRQ_TYPE_LEVEL_HIGH>,
+					<0 0 0 3 &intc 0 0 84 IRQ_TYPE_LEVEL_HIGH>,
+					<0 0 0 4 &intc 0 0 85 IRQ_TYPE_LEVEL_HIGH>;
+
+			clocks = <&gcc GCC_PCIE1_AXI_M_CLK>,
+				 <&gcc GCC_PCIE1_AXI_S_CLK>,
+				 <&gcc GCC_PCIE1_AXI_S_BRIDGE_CLK>,
+				 <&gcc GCC_PCIE1_RCHNG_CLK>,
+				 <&gcc GCC_PCIE1_AHB_CLK>,
+				 <&gcc GCC_PCIE1_AUX_CLK>;
+			clock-names = "axi_m",
+				      "axi_s",
+				      "axi_bridge",
+				      "rchng",
+				      "ahb",
+				      "aux";
+
+			resets = <&gcc GCC_PCIE1_PIPE_ARES>,
+				 <&gcc GCC_PCIE1_CORE_STICKY_ARES>,
+				 <&gcc GCC_PCIE1_AXI_S_STICKY_ARES>,
+				 <&gcc GCC_PCIE1_AXI_S_ARES>,
+				 <&gcc GCC_PCIE1_AXI_M_STICKY_ARES>,
+				 <&gcc GCC_PCIE1_AXI_M_ARES>,
+				 <&gcc GCC_PCIE1_AUX_ARES>,
+				 <&gcc GCC_PCIE1_AHB_ARES>;
+			reset-names = "pipe",
+				      "sticky",
+				      "axi_s_sticky",
+				      "axi_s",
+				      "axi_m_sticky",
+				      "axi_m",
+				      "aux",
+				      "ahb";
+
+			phys = <&pcie1_phy>;
+			phy-names = "pciephy";
+			interconnects = <&gcc MASTER_ANOC_PCIE1 &gcc SLAVE_ANOC_PCIE1>,
+					<&gcc MASTER_SNOC_PCIE1 &gcc SLAVE_SNOC_PCIE1>;
+			interconnect-names = "pcie-mem", "cpu-pcie";
+			status = "disabled";
+		};
+
+		pcie3: pcie@18000000 {
+			compatible = "qcom,pcie-ipq9574";
+			reg =  <0x18000000 0xf1d>,
+			       <0x18000f20 0xa8>,
+			       <0x18001000 0x1000>,
+			       <0x000f0000 0x4000>,
+			       <0x18100000 0x1000>;
+			reg-names = "dbi", "elbi", "atu", "parf", "config";
+			device_type = "pci";
+			linux,pci-domain = <3>;
+			bus-range = <0x00 0xff>;
+			num-lanes = <2>;
+			#address-cells = <3>;
+			#size-cells = <2>;
+
+			ranges = <0x01000000 0x0 0x00000000 0x18200000 0x0 0x100000>,
+				 <0x02000000 0x0 0x18300000 0x18300000 0x0 0x7d00000>;
+
+			interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "msi0",
+					  "msi1",
+					  "msi2",
+					  "msi3",
+					  "msi4",
+					  "msi5",
+					  "msi6",
+					  "msi7";
+
+			#interrupt-cells = <1>;
+			interrupt-map-mask = <0 0 0 0x7>;
+			interrupt-map = <0 0 0 1 &intc 0 0 189 IRQ_TYPE_LEVEL_HIGH>,
+					<0 0 0 2 &intc 0 0 190 IRQ_TYPE_LEVEL_HIGH>,
+					<0 0 0 3 &intc 0 0 191 IRQ_TYPE_LEVEL_HIGH>,
+					<0 0 0 4 &intc 0 0 192 IRQ_TYPE_LEVEL_HIGH>;
+
+			clocks = <&gcc GCC_PCIE3_AXI_M_CLK>,
+				 <&gcc GCC_PCIE3_AXI_S_CLK>,
+				 <&gcc GCC_PCIE3_AXI_S_BRIDGE_CLK>,
+				 <&gcc GCC_PCIE3_RCHNG_CLK>,
+				 <&gcc GCC_PCIE3_AHB_CLK>,
+				 <&gcc GCC_PCIE3_AUX_CLK>;
+			clock-names = "axi_m",
+				      "axi_s",
+				      "axi_bridge",
+				      "rchng",
+				      "ahb",
+				      "aux";
+
+			resets = <&gcc GCC_PCIE3_PIPE_ARES>,
+				 <&gcc GCC_PCIE3_CORE_STICKY_ARES>,
+				 <&gcc GCC_PCIE3_AXI_S_STICKY_ARES>,
+				 <&gcc GCC_PCIE3_AXI_S_ARES>,
+				 <&gcc GCC_PCIE3_AXI_M_STICKY_ARES>,
+				 <&gcc GCC_PCIE3_AXI_M_ARES>,
+				 <&gcc GCC_PCIE3_AUX_ARES>,
+				 <&gcc GCC_PCIE3_AHB_ARES>;
+			reset-names = "pipe",
+				      "sticky",
+				      "axi_s_sticky",
+				      "axi_s",
+				      "axi_m_sticky",
+				      "axi_m",
+				      "aux",
+				      "ahb";
+
+			phys = <&pcie3_phy>;
+			phy-names = "pciephy";
+			interconnects = <&gcc MASTER_ANOC_PCIE3 &gcc SLAVE_ANOC_PCIE3>,
+					<&gcc MASTER_SNOC_PCIE3 &gcc SLAVE_SNOC_PCIE3>;
+			interconnect-names = "pcie-mem", "cpu-pcie";
+			status = "disabled";
+		};
+
+		pcie2: pcie@20000000 {
+			compatible = "qcom,pcie-ipq9574";
+			reg =  <0x20000000 0xf1d>,
+			       <0x20000f20 0xa8>,
+			       <0x20001000 0x1000>,
+			       <0x00088000 0x4000>,
+			       <0x20100000 0x1000>;
+			reg-names = "dbi", "elbi", "atu", "parf", "config";
+			device_type = "pci";
+			linux,pci-domain = <2>;
+			bus-range = <0x00 0xff>;
+			num-lanes = <2>;
+			#address-cells = <3>;
+			#size-cells = <2>;
+
+			ranges = <0x01000000 0x0 0x00000000 0x20200000 0x0 0x100000>,
+				 <0x02000000 0x0 0x20300000 0x20300000 0x0 0x7d00000>;
+
+			interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "msi0",
+					  "msi1",
+					  "msi2",
+					  "msi3",
+					  "msi4",
+					  "msi5",
+					  "msi6",
+					  "msi7";
+
+			#interrupt-cells = <1>;
+			interrupt-map-mask = <0 0 0 0x7>;
+			interrupt-map = <0 0 0 1 &intc 0 0 164 IRQ_TYPE_LEVEL_HIGH>,
+					<0 0 0 2 &intc 0 0 165 IRQ_TYPE_LEVEL_HIGH>,
+					<0 0 0 3 &intc 0 0 186 IRQ_TYPE_LEVEL_HIGH>,
+					<0 0 0 4 &intc 0 0 187 IRQ_TYPE_LEVEL_HIGH>;
+
+			clocks = <&gcc GCC_PCIE2_AXI_M_CLK>,
+				 <&gcc GCC_PCIE2_AXI_S_CLK>,
+				 <&gcc GCC_PCIE2_AXI_S_BRIDGE_CLK>,
+				 <&gcc GCC_PCIE2_RCHNG_CLK>,
+				 <&gcc GCC_PCIE2_AHB_CLK>,
+				 <&gcc GCC_PCIE2_AUX_CLK>;
+			clock-names = "axi_m",
+				      "axi_s",
+				      "axi_bridge",
+				      "rchng",
+				      "ahb",
+				      "aux";
+
+			resets = <&gcc GCC_PCIE2_PIPE_ARES>,
+				 <&gcc GCC_PCIE2_CORE_STICKY_ARES>,
+				 <&gcc GCC_PCIE2_AXI_S_STICKY_ARES>,
+				 <&gcc GCC_PCIE2_AXI_S_ARES>,
+				 <&gcc GCC_PCIE2_AXI_M_STICKY_ARES>,
+				 <&gcc GCC_PCIE2_AXI_M_ARES>,
+				 <&gcc GCC_PCIE2_AUX_ARES>,
+				 <&gcc GCC_PCIE2_AHB_ARES>;
+			reset-names = "pipe",
+				      "sticky",
+				      "axi_s_sticky",
+				      "axi_s",
+				      "axi_m_sticky",
+				      "axi_m",
+				      "aux",
+				      "ahb";
+
+			phys = <&pcie2_phy>;
+			phy-names = "pciephy";
+			interconnects = <&gcc MASTER_ANOC_PCIE2 &gcc SLAVE_ANOC_PCIE2>,
+					<&gcc MASTER_SNOC_PCIE2 &gcc SLAVE_SNOC_PCIE2>;
+			interconnect-names = "pcie-mem", "cpu-pcie";
+			status = "disabled";
+		};
+
+		pcie0: pci@28000000 {
+			compatible = "qcom,pcie-ipq9574";
+			reg =  <0x28000000 0xf1d>,
+			       <0x28000f20 0xa8>,
+			       <0x28001000 0x1000>,
+			       <0x00080000 0x4000>,
+			       <0x28100000 0x1000>;
+			reg-names = "dbi", "elbi", "atu", "parf", "config";
+			device_type = "pci";
+			linux,pci-domain = <0>;
+			bus-range = <0x00 0xff>;
+			num-lanes = <1>;
+			#address-cells = <3>;
+			#size-cells = <2>;
+
+			ranges = <0x01000000 0x0 0x00000000 0x28200000 0x0 0x100000>,
+				 <0x02000000 0x0 0x28300000 0x28300000 0x0 0x7d00000>;
+			interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "msi0",
+					  "msi1",
+					  "msi2",
+					  "msi3",
+					  "msi4",
+					  "msi5",
+					  "msi6",
+					  "msi7";
+
+			#interrupt-cells = <1>;
+			interrupt-map-mask = <0 0 0 0x7>;
+			interrupt-map = <0 0 0 1 &intc 0 0 75 IRQ_TYPE_LEVEL_HIGH>,
+					<0 0 0 2 &intc 0 0 78 IRQ_TYPE_LEVEL_HIGH>,
+					<0 0 0 3 &intc 0 0 79 IRQ_TYPE_LEVEL_HIGH>,
+					<0 0 0 4 &intc 0 0 83 IRQ_TYPE_LEVEL_HIGH>;
+
+			clocks = <&gcc GCC_PCIE0_AXI_M_CLK>,
+				 <&gcc GCC_PCIE0_AXI_S_CLK>,
+				 <&gcc GCC_PCIE0_AXI_S_BRIDGE_CLK>,
+				 <&gcc GCC_PCIE0_RCHNG_CLK>,
+				 <&gcc GCC_PCIE0_AHB_CLK>,
+				 <&gcc GCC_PCIE0_AUX_CLK>;
+			clock-names = "axi_m",
+				      "axi_s",
+				      "axi_bridge",
+				      "rchng",
+				      "ahb",
+				      "aux";
+
+			resets = <&gcc GCC_PCIE0_PIPE_ARES>,
+				 <&gcc GCC_PCIE0_CORE_STICKY_ARES>,
+				 <&gcc GCC_PCIE0_AXI_S_STICKY_ARES>,
+				 <&gcc GCC_PCIE0_AXI_S_ARES>,
+				 <&gcc GCC_PCIE0_AXI_M_STICKY_ARES>,
+				 <&gcc GCC_PCIE0_AXI_M_ARES>,
+				 <&gcc GCC_PCIE0_AUX_ARES>,
+				 <&gcc GCC_PCIE0_AHB_ARES>;
+			reset-names = "pipe",
+				      "sticky",
+				      "axi_s_sticky",
+				      "axi_s",
+				      "axi_m_sticky",
+				      "axi_m",
+				      "aux",
+				      "ahb";
+
+			phys = <&pcie0_phy>;
+			phy-names = "pciephy";
+			interconnects = <&gcc MASTER_ANOC_PCIE0 &gcc SLAVE_ANOC_PCIE0>,
+					<&gcc MASTER_SNOC_PCIE0 &gcc SLAVE_SNOC_PCIE0>;
+			interconnect-names = "pcie-mem", "cpu-pcie";
+			status = "disabled";
+		};
+
 	};
 
 	thermal-zones {
diff --git a/dts/upstream/src/arm64/qcom/msm8916-samsung-serranove.dts b/dts/upstream/src/arm64/qcom/msm8916-samsung-serranove.dts
index 5ce8f1350ab..caad1dead2e 100644
--- a/dts/upstream/src/arm64/qcom/msm8916-samsung-serranove.dts
+++ b/dts/upstream/src/arm64/qcom/msm8916-samsung-serranove.dts
@@ -321,6 +321,41 @@
 	status = "okay";
 };
 
+&gpu {
+	status = "okay";
+};
+
+&mdss {
+	status = "okay";
+};
+
+&mdss_dsi0 {
+	pinctrl-names = "default", "sleep";
+	pinctrl-0 = <&mdss_default>;
+	pinctrl-1 = <&mdss_sleep>;
+
+	panel@0 {
+		compatible = "samsung,s6e88a0-ams427ap24";
+		reg = <0>;
+
+		vdd3-supply = <&pm8916_l17>;
+		vci-supply = <&pm8916_l6>;
+		reset-gpios = <&tlmm 25 GPIO_ACTIVE_LOW>;
+		flip-horizontal;
+
+		port {
+			panel_in: endpoint {
+				remote-endpoint = <&mdss_dsi0_out>;
+			};
+		};
+	};
+};
+
+&mdss_dsi0_out {
+	data-lanes = <0 1>;
+	remote-endpoint = <&panel_in>;
+};
+
 &mpss_mem {
 	reg = <0x0 0x86800000 0x0 0x5a00000>;
 };
@@ -330,6 +365,13 @@
 	linux,code = <KEY_VOLUMEDOWN>;
 };
 
+&pm8916_rpm_regulators {
+	pm8916_l17: l17 {
+		regulator-min-microvolt = <2850000>;
+		regulator-max-microvolt = <2850000>;
+	};
+};
+
 &pm8916_vib {
 	status = "okay";
 };
@@ -425,6 +467,22 @@
 		bias-disable;
 	};
 
+	mdss_default: mdss-default-state {
+		pins = "gpio25";
+		function = "gpio";
+
+		drive-strength = <8>;
+		bias-disable;
+	};
+
+	mdss_sleep: mdss-sleep-state {
+		pins = "gpio25";
+		function = "gpio";
+
+		drive-strength = <2>;
+		bias-pull-down;
+	};
+
 	muic_i2c_default: muic-i2c-default-state {
 		pins = "gpio105", "gpio106";
 		function = "gpio";
diff --git a/dts/upstream/src/arm64/qcom/msm8916.dtsi b/dts/upstream/src/arm64/qcom/msm8916.dtsi
index 5e558bcc9d8..8f35c9af187 100644
--- a/dts/upstream/src/arm64/qcom/msm8916.dtsi
+++ b/dts/upstream/src/arm64/qcom/msm8916.dtsi
@@ -125,7 +125,7 @@
 		sleep_clk: sleep-clk {
 			compatible = "fixed-clock";
 			#clock-cells = <0>;
-			clock-frequency = <32768>;
+			clock-frequency = <32764>;
 		};
 	};
 
diff --git a/dts/upstream/src/arm64/qcom/msm8917-xiaomi-riva.dts b/dts/upstream/src/arm64/qcom/msm8917-xiaomi-riva.dts
new file mode 100644
index 00000000000..f1d22535fed
--- /dev/null
+++ b/dts/upstream/src/arm64/qcom/msm8917-xiaomi-riva.dts
@@ -0,0 +1,333 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2023, Barnabas Czeman
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/arm/qcom,ids.h>
+#include <dt-bindings/gpio/gpio.h>
+#include "msm8917.dtsi"
+#include "pm8937.dtsi"
+
+/delete-node/ &qseecom_mem;
+
+/ {
+	model = "Xiaomi Redmi 5A (riva)";
+	compatible = "xiaomi,riva", "qcom,msm8917";
+	chassis-type = "handset";
+
+	qcom,msm-id = <QCOM_ID_MSM8917 0>;
+	qcom,board-id = <0x1000b 2>, <0x2000b 2>;
+
+	battery: battery {
+		compatible = "simple-battery";
+		charge-full-design-microamp-hours = <3000000>;
+		energy-full-design-microwatt-hours = <11500000>;
+		constant-charge-current-max-microamp = <1000000>;
+		constant-charge-voltage-max-microvolt = <4400000>;
+		precharge-current-microamp = <256000>;
+		charge-term-current-microamp = <60000>;
+		voltage-min-design-microvolt = <3400000>;
+	};
+
+	chosen {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		stdout-path = "framebuffer0";
+
+		framebuffer0: framebuffer@90001000 {
+			compatible = "simple-framebuffer";
+			reg = <0x0 0x90001000 0x0 (720 * 1280 * 3)>;
+			width = <720>;
+			height = <1280>;
+			stride = <(720 * 3)>;
+			format = "r8g8b8";
+
+			clocks = <&gcc GCC_MDSS_AHB_CLK>,
+				 <&gcc GCC_MDSS_AXI_CLK>,
+				 <&gcc GCC_MDSS_VSYNC_CLK>,
+				 <&gcc GCC_MDSS_MDP_CLK>,
+				 <&gcc GCC_MDSS_BYTE0_CLK>,
+				 <&gcc GCC_MDSS_PCLK0_CLK>,
+				 <&gcc GCC_MDSS_ESC0_CLK>;
+			power-domains = <&gcc MDSS_GDSC>;
+		};
+	};
+
+	gpio-keys {
+		compatible = "gpio-keys";
+
+		pinctrl-0 = <&gpio_keys_default>;
+		pinctrl-names = "default";
+
+		key-volup {
+			label = "Volume Up";
+			linux,code = <KEY_VOLUMEUP>;
+			gpios = <&tlmm 91 GPIO_ACTIVE_LOW>;
+			debounce-interval = <15>;
+		};
+	};
+
+	vph_pwr: regulator-vph-pwr {
+		compatible = "regulator-fixed";
+		regulator-name = "vph_pwr";
+		regulator-min-microvolt = <3700000>;
+		regulator-max-microvolt = <3700000>;
+		regulator-always-on;
+		regulator-boot-on;
+	};
+
+	reserved-memory {
+		qseecom_mem: qseecom@84a00000 {
+			reg = <0x0 0x84a00000 0x0 0x1900000>;
+			no-map;
+		};
+
+		framebuffer_mem: memory@90001000 {
+			reg = <0x0 0x90001000 0x0 (720 * 1280 * 3)>;
+			no-map;
+		};
+	};
+};
+
+&blsp1_i2c3 {
+	status = "okay";
+
+	touchscreen@38 {
+		compatible = "edt,edt-ft5306";
+		reg = <0x38>;
+		interrupts-extended = <&tlmm 65 IRQ_TYPE_LEVEL_LOW>;
+		reset-gpios = <&tlmm 64 GPIO_ACTIVE_LOW>;
+		pinctrl-0 = <&tsp_int_rst_default>;
+		pinctrl-names = "default";
+		vcc-supply = <&pm8937_l10>;
+		iovcc-supply = <&pm8937_l5>;
+		touchscreen-size-x = <720>;
+		touchscreen-size-y = <1280>;
+	};
+};
+
+&blsp2_i2c1 {
+	status = "okay";
+
+	bq27426@55 {
+		compatible = "ti,bq27426";
+		reg = <0x55>;
+		monitored-battery = <&battery>;
+	};
+
+	bq25601@6b{
+		compatible = "ti,bq25601";
+		reg = <0x6b>;
+		interrupts-extended = <&tlmm 61 IRQ_TYPE_EDGE_FALLING>;
+		pinctrl-0 = <&bq25601_int_default>;
+		pinctrl-names = "default";
+		input-voltage-limit-microvolt = <4400000>;
+		input-current-limit-microamp = <1000000>;
+		monitored-battery = <&battery>;
+	};
+};
+
+&pm8937_resin {
+	linux,code = <KEY_VOLUMEDOWN>;
+
+	status = "okay";
+};
+
+&rpm_requests {
+	regulators-0 {
+		compatible = "qcom,rpm-pm8937-regulators";
+
+		vdd_s1-supply = <&vph_pwr>;
+		vdd_s2-supply = <&vph_pwr>;
+		vdd_s3-supply = <&vph_pwr>;
+		vdd_s4-supply = <&vph_pwr>;
+
+		vdd_l1_l19-supply = <&pm8937_s3>;
+		vdd_l2_l23-supply = <&pm8937_s3>;
+		vdd_l3-supply = <&pm8937_s3>;
+		vdd_l4_l5_l6_l7_l16-supply = <&pm8937_s4>;
+		vdd_l8_l11_l12_l17_l22-supply = <&vph_pwr>;
+		vdd_l9_l10_l13_l14_l15_l18-supply = <&vph_pwr>;
+
+		pm8937_s1: s1 {
+			regulator-min-microvolt = <1000000>;
+			regulator-max-microvolt = <1225000>;
+		};
+
+		pm8937_s3: s3 {
+			regulator-min-microvolt = <1300000>;
+			regulator-max-microvolt = <1300000>;
+		};
+
+		pm8937_s4: s4 {
+			regulator-min-microvolt = <2050000>;
+			regulator-max-microvolt = <2050000>;
+		};
+
+		pm8937_l2: l2 {
+			regulator-min-microvolt = <1200000>;
+			regulator-max-microvolt = <1200000>;
+		};
+
+		pm8937_l5: l5 {
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+		};
+
+		pm8937_l6: l6 {
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+		};
+
+		pm8937_l7: l7 {
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+		};
+
+		pm8937_l8: l8 {
+			regulator-min-microvolt = <2850000>;
+			regulator-max-microvolt = <2900000>;
+		};
+
+		pm8937_l9: l9 {
+			regulator-min-microvolt = <3000000>;
+			regulator-max-microvolt = <3300000>;
+		};
+
+		pm8937_l10: l10 {
+			regulator-min-microvolt = <2800000>;
+			regulator-max-microvolt = <3000000>;
+		};
+
+		pm8937_l11: l11 {
+			regulator-min-microvolt = <2950000>;
+			regulator-max-microvolt = <2950000>;
+			regulator-allow-set-load;
+			regulator-system-load = <200000>;
+		};
+
+		pm8937_l12: l12 {
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <2950000>;
+		};
+
+		pm8937_l13: l13 {
+			regulator-min-microvolt = <3075000>;
+			regulator-max-microvolt = <3075000>;
+		};
+
+		pm8937_l14: l14 {
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <3300000>;
+		};
+
+		pm8937_l15: l15 {
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <3300000>;
+		};
+
+		pm8937_l16: l16 {
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+		};
+
+		pm8937_l17: l17 {
+			regulator-min-microvolt = <2800000>;
+			regulator-max-microvolt = <2900000>;
+		};
+
+		pm8937_l19: l19 {
+			regulator-min-microvolt = <1225000>;
+			regulator-max-microvolt = <1350000>;
+		};
+
+		pm8937_l22: l22 {
+			regulator-min-microvolt = <2800000>;
+			regulator-max-microvolt = <2800000>;
+		};
+
+		pm8937_l23: l23 {
+			regulator-min-microvolt = <1200000>;
+			regulator-max-microvolt = <1200000>;
+		};
+	};
+
+};
+
+&sdhc_1 {
+	vmmc-supply = <&pm8937_l8>;
+	vqmmc-supply = <&pm8937_l5>;
+
+	status = "okay";
+};
+
+&sdhc_2 {
+	cd-gpios = <&tlmm 67 GPIO_ACTIVE_LOW>;
+	vmmc-supply = <&pm8937_l11>;
+	vqmmc-supply = <&pm8937_l12>;
+	pinctrl-0 = <&sdc2_default &sdc2_cd_default>;
+	pinctrl-1 = <&sdc2_sleep &sdc2_cd_default>;
+	pinctrl-names = "default", "sleep";
+
+	status = "okay";
+};
+
+&sleep_clk {
+	clock-frequency = <32768>;
+};
+
+&tlmm {
+	bq25601_int_default: bq25601-int-default-state {
+		pins = "gpio61";
+		function = "gpio";
+		drive-strength = <2>;
+		bias-pull-up;
+	};
+
+	gpio_keys_default: gpio-keys-default-state {
+		pins = "gpio91";
+		function = "gpio";
+		drive-strength = <2>;
+		bias-pull-up;
+	};
+
+	sdc2_cd_default: sdc2-cd-default-state {
+		pins = "gpio67";
+		function = "gpio";
+		drive-strength = <2>;
+		bias-disable;
+	};
+
+	tsp_int_rst_default: tsp-int-rst-default-state {
+		pins = "gpio64", "gpio65";
+		function = "gpio";
+		drive-strength = <8>;
+		bias-pull-up;
+	};
+};
+
+&wcnss {
+	vddpx-supply = <&pm8937_l5>;
+
+	status = "okay";
+};
+
+&wcnss_iris {
+	compatible = "qcom,wcn3620";
+	vddxo-supply = <&pm8937_l7>;
+	vddrfa-supply = <&pm8937_l19>;
+	vddpa-supply = <&pm8937_l9>;
+	vdddig-supply = <&pm8937_l5>;
+};
+
+&wcnss_mem {
+	status = "okay";
+};
+
+&xo_board {
+	clock-frequency = <19200000>;
+};
diff --git a/dts/upstream/src/arm64/qcom/msm8917.dtsi b/dts/upstream/src/arm64/qcom/msm8917.dtsi
new file mode 100644
index 00000000000..7bf58dd0146
--- /dev/null
+++ b/dts/upstream/src/arm64/qcom/msm8917.dtsi
@@ -0,0 +1,1954 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
+#include <dt-bindings/clock/qcom,gcc-msm8917.h>
+#include <dt-bindings/clock/qcom,rpmcc.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/power/qcom-rpmpd.h>
+#include <dt-bindings/thermal/thermal.h>
+
+/ {
+	interrupt-parent = <&intc>;
+
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	chosen { };
+
+	clocks {
+		sleep_clk: sleep-clk {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+		};
+
+		xo_board: xo-board {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+		};
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu0: cpu@100 {
+			compatible = "arm,cortex-a53";
+			reg = <0x100>;
+			device_type = "cpu";
+			next-level-cache = <&l2_0>;
+			enable-method = "psci";
+			clocks = <&apcs>;
+			operating-points-v2 = <&cpu_opp_table>;
+			#cooling-cells = <2>;
+			power-domains = <&cpu_pd0>;
+			power-domain-names = "psci";
+
+			l2_0: l2-cache {
+				compatible = "cache";
+				cache-level = <2>;
+				cache-unified;
+			};
+		};
+
+		cpu1: cpu@101 {
+			compatible = "arm,cortex-a53";
+			reg = <0x101>;
+			device_type = "cpu";
+			next-level-cache = <&l2_0>;
+			enable-method = "psci";
+			clocks = <&apcs>;
+			operating-points-v2 = <&cpu_opp_table>;
+			#cooling-cells = <2>;
+			power-domains = <&cpu_pd1>;
+			power-domain-names = "psci";
+		};
+
+		cpu2: cpu@102 {
+			compatible = "arm,cortex-a53";
+			reg = <0x102>;
+			device_type = "cpu";
+			next-level-cache = <&l2_0>;
+			enable-method = "psci";
+			clocks = <&apcs>;
+			operating-points-v2 = <&cpu_opp_table>;
+			#cooling-cells = <2>;
+			power-domains = <&cpu_pd2>;
+			power-domain-names = "psci";
+		};
+
+		cpu3: cpu@103 {
+			compatible = "arm,cortex-a53";
+			reg = <0x103>;
+			device_type = "cpu";
+			next-level-cache = <&l2_0>;
+			enable-method = "psci";
+			clocks = <&apcs>;
+			operating-points-v2 = <&cpu_opp_table>;
+			#cooling-cells = <2>;
+			power-domains = <&cpu_pd3>;
+			power-domain-names = "psci";
+		};
+
+		cpu-map {
+			cluster0 {
+				core0 {
+					cpu = <&cpu0>;
+				};
+
+				core1 {
+					cpu = <&cpu1>;
+				};
+
+				core2 {
+					cpu = <&cpu2>;
+				};
+
+				core3 {
+					cpu = <&cpu3>;
+				};
+			};
+		};
+
+		domain-idle-states {
+			cluster_sleep_0: cluster-sleep-0 {
+				compatible = "domain-idle-state";
+				arm,psci-suspend-param = <0x41000053>;
+				entry-latency-us = <700>;
+				exit-latency-us = <1000>;
+				min-residency-us = <6500>;
+			};
+		};
+
+		idle-states {
+			entry-method = "psci";
+
+			cpu_sleep_0: cpu-sleep-0 {
+				compatible = "arm,idle-state";
+				idle-state-name = "standalone-power-collapse";
+				arm,psci-suspend-param = <0x40000003>;
+				entry-latency-us = <125>;
+				exit-latency-us = <180>;
+				min-residency-us = <595>;
+				local-timer-stop;
+			};
+		};
+
+		cpu_opp_table: opp-table-cpu {
+			compatible = "operating-points-v2";
+			opp-shared;
+
+			opp-960000000 {
+				opp-hz = /bits/ 64 <960000000>;
+			};
+
+			opp-1094400000 {
+				opp-hz = /bits/ 64 <1094400000>;
+			};
+
+			opp-1248000000 {
+				opp-hz = /bits/ 64 <1248000000>;
+			};
+
+			opp-1401600000 {
+				opp-hz = /bits/ 64 <1401600000>;
+			};
+		};
+	};
+
+	firmware {
+		scm: scm {
+			compatible = "qcom,scm-msm8916", "qcom,scm";
+			clocks = <&gcc GCC_CRYPTO_CLK>,
+				 <&gcc GCC_CRYPTO_AXI_CLK>,
+				 <&gcc GCC_CRYPTO_AHB_CLK>;
+			clock-names = "core", "bus", "iface";
+			#reset-cells = <1>;
+
+			qcom,dload-mode = <&tcsr 0x6100>;
+		};
+	};
+
+	memory@80000000 {
+		/* We expect the bootloader to fill in the reg */
+		reg = <0 0x80000000 0 0>;
+		device_type = "memory";
+	};
+
+	pmu {
+		compatible = "arm,cortex-a53-pmu";
+		interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+	};
+
+	psci {
+		compatible = "arm,psci-1.0";
+		method = "smc";
+
+		cluster_pd: power-domain-cluster {
+			#power-domain-cells = <0>;
+			domain-idle-states = <&cluster_sleep_0>;
+		};
+
+		cpu_pd0: power-domain-cpu0 {
+			#power-domain-cells = <0>;
+			power-domains = <&cluster_pd>;
+			domain-idle-states = <&cpu_sleep_0>;
+		};
+
+		cpu_pd1: power-domain-cpu1 {
+			#power-domain-cells = <0>;
+			power-domains = <&cluster_pd>;
+			domain-idle-states = <&cpu_sleep_0>;
+		};
+
+		cpu_pd2: power-domain-cpu2 {
+			#power-domain-cells = <0>;
+			power-domains = <&cluster_pd>;
+			domain-idle-states = <&cpu_sleep_0>;
+		};
+
+		cpu_pd3: power-domain-cpu3 {
+			#power-domain-cells = <0>;
+			power-domains = <&cluster_pd>;
+			domain-idle-states = <&cpu_sleep_0>;
+		};
+	};
+
+	rpm: remoteproc {
+		compatible = "qcom,msm8917-rpm-proc", "qcom,rpm-proc";
+
+		smd-edge {
+			interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
+			qcom,ipc = <&apcs 8 0>;
+			qcom,smd-edge = <15>;
+
+			rpm_requests: rpm-requests {
+				compatible = "qcom,rpm-msm8917", "qcom,smd-rpm";
+				qcom,smd-channels = "rpm_requests";
+
+				rpmcc: clock-controller {
+					compatible = "qcom,rpmcc-msm8917", "qcom,rpmcc";
+					#clock-cells = <1>;
+					clocks = <&xo_board>;
+					clock-names = "xo";
+				};
+
+				rpmpd: power-controller {
+					compatible = "qcom,msm8917-rpmpd";
+					#power-domain-cells = <1>;
+					operating-points-v2 = <&rpmpd_opp_table>;
+
+					rpmpd_opp_table: opp-table {
+						compatible = "operating-points-v2";
+
+						rpmpd_opp_ret: opp1 {
+							opp-level = <RPM_SMD_LEVEL_RETENTION>;
+						};
+
+						rpmpd_opp_ret_plus: opp2 {
+							opp-level = <RPM_SMD_LEVEL_RETENTION_PLUS>;
+						};
+
+						rpmpd_opp_min_svs: opp3 {
+							opp-level = <RPM_SMD_LEVEL_MIN_SVS>;
+						};
+
+						rpmpd_opp_low_svs: opp4 {
+							opp-level = <RPM_SMD_LEVEL_LOW_SVS>;
+						};
+
+						rpmpd_opp_svs: opp5 {
+							opp-level = <RPM_SMD_LEVEL_SVS>;
+						};
+
+						rpmpd_opp_svs_plus: opp6 {
+							opp-level = <RPM_SMD_LEVEL_SVS_PLUS>;
+						};
+
+						rpmpd_opp_nom: opp7 {
+							opp-level = <RPM_SMD_LEVEL_NOM>;
+						};
+
+						rpmpd_opp_nom_plus: opp8 {
+							opp-level = <RPM_SMD_LEVEL_NOM_PLUS>;
+						};
+
+						rpmpd_opp_turbo: opp9 {
+							opp-level = <RPM_SMD_LEVEL_TURBO>;
+						};
+					};
+				};
+			};
+		};
+	};
+
+	reserved-memory {
+		ranges;
+		#address-cells = <2>;
+		#size-cells = <2>;
+
+		qseecom_mem: qseecom@85b00000 {
+			reg = <0x0 0x85b00000 0x0 0x800000>;
+			no-map;
+		};
+
+		smem@86300000 {
+			compatible = "qcom,smem";
+			reg = <0x0 0x86300000 0x0 0x100000>;
+			no-map;
+
+			hwlocks = <&tcsr_mutex 3>;
+			qcom,rpm-msg-ram = <&rpm_msg_ram>;
+		};
+
+		reserved@86400000 {
+			reg = <0x0 0x86400000 0x0 0x400000>;
+			no-map;
+		};
+
+		rmtfs@92100000 {
+			compatible = "qcom,rmtfs-mem";
+			reg = <0x0 0x92100000 0x0 0x180000>;
+			no-map;
+
+			qcom,client-id = <1>;
+		};
+
+		adsp_mem: adsp {
+			size = <0x0 0x1100000>;
+			alignment = <0x0 0x100000>;
+			alloc-ranges = <0x0 0x86800000 0x0 0x8000000>;
+			no-map;
+			status = "disabled";
+		};
+
+		mba_mem: mba {
+			size = <0x0 0x100000>;
+			alignment = <0x0 0x100000>;
+			alloc-ranges = <0x0 0x86800000 0x0 0x8000000>;
+			no-map;
+			status = "disabled";
+		};
+
+		venus_mem: venus {
+			size = <0x0 0x400000>;
+			alignment = <0x0 0x100000>;
+			alloc-ranges = <0x0 0x86800000 0x0 0x8000000>;
+			no-map;
+			status = "disabled";
+		};
+
+		wcnss_mem: wcnss {
+			size = <0x0 0x700000>;
+			alignment = <0x0 0x100000>;
+			alloc-ranges = <0x0 0x86800000 0x0 0x8000000>;
+			no-map;
+			status = "disabled";
+		};
+	};
+
+	smp2p-adsp {
+		compatible = "qcom,smp2p";
+		qcom,smem = <443>, <429>;
+
+		interrupts = <GIC_SPI 291 IRQ_TYPE_EDGE_RISING>;
+
+		mboxes = <&apcs 10>;
+
+		qcom,local-pid = <0>;
+		qcom,remote-pid = <2>;
+
+		adsp_smp2p_out: master-kernel {
+			qcom,entry-name = "master-kernel";
+
+			#qcom,smem-state-cells = <1>;
+		};
+
+		adsp_smp2p_in: slave-kernel {
+			qcom,entry-name = "slave-kernel";
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+	};
+
+	smp2p-modem {
+		compatible = "qcom,smp2p";
+		qcom,smem = <435>, <428>;
+
+		interrupts = <GIC_SPI 27 IRQ_TYPE_EDGE_RISING>;
+
+		mboxes = <&apcs 14>;
+
+		qcom,local-pid = <0>;
+		qcom,remote-pid = <1>;
+
+		modem_smp2p_out: master-kernel {
+			qcom,entry-name = "master-kernel";
+
+			#qcom,smem-state-cells = <1>;
+		};
+
+		modem_smp2p_in: slave-kernel {
+			qcom,entry-name = "slave-kernel";
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+	};
+
+	smp2p-wcnss {
+		compatible = "qcom,smp2p";
+		qcom,smem = <451>, <431>;
+
+		interrupts = <GIC_SPI 143 IRQ_TYPE_EDGE_RISING>;
+
+		mboxes = <&apcs 18>;
+
+		qcom,local-pid = <0>;
+		qcom,remote-pid = <4>;
+
+		wcnss_smp2p_out: master-kernel {
+			qcom,entry-name = "master-kernel";
+
+			#qcom,smem-state-cells = <1>;
+		};
+
+		wcnss_smp2p_in: slave-kernel {
+			qcom,entry-name = "slave-kernel";
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+	};
+
+	smsm {
+		compatible = "qcom,smsm";
+
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		mboxes = <0>, <&apcs 13>, <0>, <&apcs 19>;
+
+		apps_smsm: apps@0 {
+			reg = <0>;
+
+			#qcom,smem-state-cells = <1>;
+		};
+
+		hexagon_smsm: hexagon@1 {
+			reg = <1>;
+			interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		wcnss_smsm: wcnss@6 {
+			reg = <6>;
+			interrupts = <GIC_SPI 144 IRQ_TYPE_EDGE_RISING>;
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+	};
+
+	soc: soc@0 {
+		compatible = "simple-bus";
+		ranges = <0 0 0 0xffffffff>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		rpm_msg_ram: sram@60000 {
+			compatible = "qcom,rpm-msg-ram";
+			reg = <0x00060000 0x8000>;
+		};
+
+		usb_hs_phy: phy@6c000 {
+			compatible = "qcom,usb-hs-28nm-femtophy";
+			reg = <0x0006c000 0x200>;
+			#phy-cells = <0>;
+			clocks = <&xo_board>,
+				 <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>,
+				 <&gcc GCC_USB2A_PHY_SLEEP_CLK>;
+			clock-names = "ref", "ahb", "sleep";
+			resets = <&gcc GCC_QUSB2_PHY_BCR>,
+				 <&gcc GCC_USB2_HS_PHY_ONLY_BCR>;
+			reset-names = "phy", "por";
+			status = "disabled";
+		};
+
+		qfprom: qfprom@a4000 {
+			compatible = "qcom,msm8917-qfprom", "qcom,qfprom";
+			reg = <0x000a4000 0x1000>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			tsens_base1: base1@1d8 {
+				reg = <0x1d8 1>;
+				bits = <0 8>;
+			};
+
+			tsens_s5_p1: s5-p1@1d9 {
+				reg = <0x1d9 1>;
+				bits = <0 6>;
+			};
+
+			tsens_s5_p2: s5-p2@1d9 {
+				reg = <0x1d9 2>;
+				bits = <6 6>;
+			};
+
+			tsens_s6_p1: s6-p1@1da {
+				reg = <0x1da 2>;
+				bits = <4 6>;
+			};
+
+			tsens_s6_p2: s6-p2@1db {
+				reg = <0x1db 1>;
+				bits = <2 6>;
+			};
+
+			tsens_s7_p1: s7-p1@1dc {
+				reg = <0x1dc 1>;
+				bits = <0 6>;
+			};
+
+			tsens_s7_p2: s7-p2@1dc {
+				reg = <0x1dc 2>;
+				bits = <6 6>;
+			};
+
+			tsens_s8_p1: s8-p1@1dd {
+				reg = <0x1dd 2>;
+				bits = <4 6>;
+			};
+
+			tsens_s8_p2: s8-p2@1de {
+				reg = <0x1de 1>;
+				bits = <2 6>;
+			};
+
+			tsens_base2: base2@1df {
+				reg = <0x1df 1>;
+				bits = <0 8>;
+			};
+
+			tsens_mode: mode@210 {
+				reg = <0x210 1>;
+				bits = <0 3>;
+			};
+
+			tsens_s0_p1: s0-p1@210 {
+				reg = <0x210 2>;
+				bits = <3 6>;
+			};
+
+			tsens_s0_p2: s0-p2@211 {
+				reg = <0x211 1>;
+				bits = <1 6>;
+			};
+
+			tsens_s1_p1: s1-p1@211 {
+				reg = <0x211 2>;
+				bits = <7 6>;
+			};
+
+			tsens_s1_p2: s1-p2@212 {
+				reg = <0x212 2>;
+				bits = <5 6>;
+			};
+
+			tsens_s2_p1: s2-p1@213 {
+				reg = <0x213 2>;
+				bits = <3 6>;
+			};
+
+			tsens_s2_p2: s2-p2@214 {
+				reg = <0x214 1>;
+				bits = <1 6>;
+			};
+
+			tsens_s3_p1: s3-p1@214 {
+				reg = <0x214 2>;
+				bits = <7 6>;
+			};
+
+			tsens_s3_p2: s3-p2@215 {
+				reg = <0x215 2>;
+				bits = <5 6>;
+			};
+
+			tsens_s4_p1: s4-p1@216 {
+				reg = <0x216 2>;
+				bits = <3 6>;
+			};
+
+			tsens_s4_p2: s4-p2@217 {
+				reg = <0x217 1>;
+				bits = <1 6>;
+			};
+
+			tsens_s9_p1: s9-p1@230{
+				reg = <0x230 1>;
+				bits = <0 6>;
+			};
+
+			tsens_s9_p2: s9-p2@230 {
+				reg = <0x230 2>;
+				bits = <6 6>;
+			};
+
+			tsens_s10_p1: s10-p1@231 {
+				reg = <0x231 2>;
+				bits = <4 6>;
+			};
+
+			tsens_s10_p2: s10-p2@232 {
+				reg = <0x232 1>;
+				bits = <2 6>;
+			};
+		};
+
+		rng@e3000 {
+			compatible = "qcom,prng";
+			reg = <0x000e3000 0x1000>;
+			clocks = <&gcc GCC_PRNG_AHB_CLK>;
+			clock-names = "core";
+		};
+
+		tsens: thermal-sensor@4a9000 {
+			compatible = "qcom,msm8937-tsens", "qcom,tsens-v1";
+			reg = <0x004a9000 0x1000>,
+			      <0x004a8000 0x1000>;
+			interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "uplow";
+			nvmem-cells = <&tsens_mode>,
+				      <&tsens_base1>, <&tsens_base2>,
+				      <&tsens_s0_p1>, <&tsens_s0_p2>,
+				      <&tsens_s1_p1>, <&tsens_s1_p2>,
+				      <&tsens_s2_p1>, <&tsens_s2_p2>,
+				      <&tsens_s3_p1>, <&tsens_s3_p2>,
+				      <&tsens_s4_p1>, <&tsens_s4_p2>,
+				      <&tsens_s5_p1>, <&tsens_s5_p2>,
+				      <&tsens_s6_p1>, <&tsens_s6_p2>,
+				      <&tsens_s7_p1>, <&tsens_s7_p2>,
+				      <&tsens_s8_p1>, <&tsens_s8_p2>,
+				      <&tsens_s9_p1>, <&tsens_s9_p2>,
+				      <&tsens_s10_p1>, <&tsens_s10_p2>;
+			nvmem-cell-names = "mode",
+					   "base1", "base2",
+					   "s0_p1", "s0_p2",
+					   "s1_p1", "s1_p2",
+					   "s2_p1", "s2_p2",
+					   "s3_p1", "s3_p2",
+					   "s4_p1", "s4_p2",
+					   "s5_p1", "s5_p2",
+					   "s6_p1", "s6_p2",
+					   "s7_p1", "s7_p2",
+					   "s8_p1", "s8_p2",
+					   "s9_p1", "s9_p2",
+					   "s10_p1", "s10_p2";
+			#qcom,sensors = <11>;
+			#thermal-sensor-cells = <1>;
+		};
+
+		restart@4ab000 {
+			compatible = "qcom,pshold";
+			reg = <0x004ab000 0x4>;
+		};
+
+		tlmm: pinctrl@1000000 {
+			compatible = "qcom,msm8917-pinctrl";
+			reg = <0x01000000 0x300000>;
+			interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
+			gpio-controller;
+			gpio-ranges = <&tlmm 0 0 134>;
+			#gpio-cells = <2>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+
+			blsp1_i2c2_default: blsp1-i2c2-default-state {
+				pins = "gpio6", "gpio7";
+				function = "blsp_i2c2";
+				drive-strength = <2>;
+				bias-disable;
+			};
+
+			blsp1_i2c2_sleep: blsp1-i2c2-sleep-state {
+				pins = "gpio6", "gpio7";
+				function = "gpio";
+				drive-strength = <2>;
+				bias-disable;
+			};
+
+			blsp1_i2c3_default: blsp1-i2c3-default-state {
+				pins = "gpio10", "gpio11";
+				function = "blsp_i2c3";
+				drive-strength = <2>;
+				bias-disable;
+			};
+
+			blsp1_i2c3_sleep: blsp1-i2c3-sleep-state {
+				pins = "gpio10", "gpio11";
+				function = "gpio";
+				drive-strength = <2>;
+				bias-disable;
+			};
+
+			blsp1_i2c4_default: blsp1-i2c4-default-state {
+				pins = "gpio14", "gpio15";
+				function = "blsp_i2c4";
+				drive-strength = <2>;
+				bias-disable;
+			};
+
+			blsp1_i2c4_sleep: blsp1-i2c4-sleep-state {
+				pins = "gpio14", "gpio15";
+				function = "gpio";
+				drive-strength = <2>;
+				bias-disable;
+			};
+
+			blsp2_i2c1_default: blsp2-i2c1-default-state {
+				pins = "gpio18", "gpio19";
+				function = "blsp_i2c5";
+				drive-strength = <2>;
+				bias-disable;
+			};
+
+			blsp2_i2c1_sleep: blsp2-i2c1-sleep-state {
+				pins = "gpio18", "gpio19";
+				function = "gpio";
+				drive-strength = <2>;
+				bias-disable;
+			};
+
+			blsp1_spi3_default: blsp1-spi3-default-state {
+				cs-pins {
+					pins = "gpio10";
+					function = "blsp_spi3";
+					drive-strength = <2>;
+					bias-disable;
+				};
+
+				spi-pins {
+					pins = "gpio8", "gpio9", "gpio11";
+					function = "blsp_spi3";
+					drive-strength = <12>;
+					bias-disable;
+				};
+			};
+
+			blsp1_spi3_sleep: blsp1-spi3-sleep-state {
+				cs-pins {
+					pins = "gpio10";
+					function = "gpio";
+					drive-strength = <2>;
+					bias-disable;
+				};
+
+				spi-pins {
+					pins = "gpio8", "gpio9", "gpio11";
+					function = "gpio";
+					drive-strength = <2>;
+					bias-pull-down;
+				};
+			};
+
+			blsp2_spi2_default: blsp2-spi2-default-state {
+				cs0-pins {
+					pins = "gpio47";
+					function = "blsp_spi6";
+					drive-strength = <16>;
+					bias-disable;
+				};
+
+				cs1-pins {
+					pins = "gpio22";
+					function = "blsp_spi6";
+					drive-strength = <16>;
+					bias-disable;
+				};
+
+				spi-pins {
+					pins = "gpio20", "gpio21", "gpio23";
+					function = "blsp_spi6";
+					drive-strength = <16>;
+					bias-disable;
+				};
+			};
+
+			blsp2_spi2_sleep: blsp2-spi2-sleep-state {
+				cs0-pins {
+					pins = "gpio47";
+					function = "gpio";
+					drive-strength = <2>;
+					bias-disable;
+				};
+
+				cs1-pins {
+					pins = "gpio22";
+					function = "gpio";
+					drive-strength = <2>;
+					bias-disable;
+				};
+
+				spi-pins {
+					pins = "gpio20", "gpio21", "gpio23";
+					function = "gpio";
+					drive-strength = <2>;
+					bias-pull-down;
+				};
+			};
+
+			blsp1_uart1_default: blsp1-uart1-default-state {
+				pins = "gpio0", "gpio1", "gpio2", "gpio3";
+				function = "blsp_uart1";
+				drive-strength = <2>;
+				bias-disable;
+			};
+
+			blsp1_uart1_sleep: blsp1-uart1-sleep-state {
+				pins = "gpio0", "gpio1", "gpio2", "gpio3";
+				function = "gpio";
+				drive-strength = <2>;
+				bias-disable;
+			};
+
+			blsp1_uart2_default: blsp1-uart2-default-state {
+				pins = "gpio4", "gpio5";
+				function = "blsp_uart2";
+				drive-strength = <2>;
+				bias-disable;
+			};
+
+			blsp1_uart2_sleep: blsp1-uart2-sleep-state {
+				pins = "gpio4", "gpio5";
+				function = "gpio";
+				drive-strength = <2>;
+				bias-pull-down;
+			};
+
+			sdc1_default: sdc1-default-state {
+				clk-pins {
+					pins = "sdc1_clk";
+					bias-disable;
+					drive-strength = <16>;
+				};
+
+				cmd-pins {
+					pins = "sdc1_cmd";
+					bias-pull-up;
+					drive-strength = <10>;
+				};
+
+				data-pins {
+					pins = "sdc1_data";
+					bias-pull-up;
+					drive-strength = <10>;
+				};
+
+				rclk-pins {
+					pins = "sdc1_rclk";
+					bias-pull-down;
+				};
+			};
+
+			sdc1_sleep: sdc1-sleep-state {
+				clk-pins {
+					pins = "sdc1_clk";
+					bias-disable;
+					drive-strength = <2>;
+				};
+
+				cmd-pins {
+					pins = "sdc1_cmd";
+					bias-pull-up;
+					drive-strength = <2>;
+				};
+
+				data-pins {
+					pins = "sdc1_data";
+					bias-pull-up;
+					drive-strength = <2>;
+				};
+
+				rclk-pins {
+					pins = "sdc1_rclk";
+					bias-pull-down;
+				};
+			};
+
+			sdc2_default: sdc2-default-state {
+				clk-pins {
+					pins = "sdc2_clk";
+					bias-disable;
+					drive-strength = <16>;
+				};
+
+				cmd-pins {
+					pins = "sdc2_cmd";
+					bias-pull-up;
+					drive-strength = <10>;
+				};
+
+				data-pins {
+					pins = "sdc2_data";
+					bias-pull-up;
+					drive-strength = <10>;
+				};
+			};
+
+			sdc2_sleep: sdc2-sleep-state {
+				clk-pins {
+					pins = "sdc2_clk";
+					bias-disable;
+					drive-strength = <2>;
+				};
+
+				cmd-pins {
+					pins = "sdc2_cmd";
+					bias-pull-up;
+					drive-strength = <2>;
+				};
+
+				data-pins {
+					pins = "sdc2_data";
+					bias-pull-up;
+					drive-strength = <2>;
+				};
+			};
+
+			wcnss_pin_a: wcnss-active-state {
+				wcss-wlan-pins {
+					pins = "gpio79", "gpio80";
+					function = "wcss_wlan";
+					drive-strength = <6>;
+					bias-pull-up;
+
+				};
+
+				wcss-wlan0-pins {
+					pins = "gpio78";
+					function = "wcss_wlan0";
+					drive-strength = <6>;
+					bias-pull-up;
+
+				};
+
+				wcss-wlan1-pins {
+					pins = "gpio77";
+					function = "wcss_wlan1";
+					drive-strength = <6>;
+					bias-pull-up;
+
+				};
+
+				wcss-wlan2-pins {
+					pins = "gpio76";
+					function = "wcss_wlan2";
+					drive-strength = <6>;
+					bias-pull-up;
+
+				};
+			};
+		};
+
+		gcc: clock-controller@1800000 {
+			compatible = "qcom,gcc-msm8917";
+			reg = <0x01800000 0x80000>;
+			#clock-cells = <1>;
+			#reset-cells = <1>;
+			#power-domain-cells = <1>;
+			clocks = <&xo_board>,
+				 <&sleep_clk>,
+				 <&mdss_dsi0_phy 1>,
+				 <&mdss_dsi0_phy 0>;
+			clock-names = "xo",
+				      "sleep_clk",
+				      "dsi0pll",
+				      "dsi0pllbyte";
+		};
+
+		tcsr_mutex: hwlock@1905000 {
+			compatible = "qcom,tcsr-mutex";
+			reg = <0x01905000 0x20000>;
+			#hwlock-cells = <1>;
+		};
+
+		tcsr: syscon@1937000 {
+			compatible = "qcom,tcsr-msm8917", "syscon";
+			reg = <0x01937000 0x30000>;
+		};
+
+		mdss: display-subsystem@1a00000 {
+			compatible = "qcom,mdss";
+			reg = <0x01a00000 0x1000>,
+			      <0x01ab0000 0x1040>;
+			reg-names = "mdss_phys", "vbif_phys";
+			ranges;
+
+			power-domains = <&gcc MDSS_GDSC>;
+
+			clocks = <&gcc GCC_MDSS_AHB_CLK>,
+				 <&gcc GCC_MDSS_AXI_CLK>,
+				 <&gcc GCC_MDSS_VSYNC_CLK>;
+			clock-names = "iface",
+				      "bus",
+				      "vsync";
+
+			interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
+
+			interrupt-controller;
+			#interrupt-cells = <1>;
+
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			status = "disabled";
+
+			mdp: display-controller@1a01000 {
+				compatible = "qcom,msm8917-mdp5", "qcom,mdp5";
+				reg = <0x01a01000 0x89000>;
+				reg-names = "mdp_phys";
+
+				interrupt-parent = <&mdss>;
+				interrupts = <0>;
+
+				power-domains = <&gcc MDSS_GDSC>;
+
+				clocks = <&gcc GCC_MDSS_AHB_CLK>,
+					 <&gcc GCC_MDSS_AXI_CLK>,
+					 <&gcc GCC_MDSS_MDP_CLK>,
+					 <&gcc GCC_MDSS_VSYNC_CLK>;
+				clock-names = "iface",
+					      "bus",
+					      "core",
+					      "vsync";
+
+				iommus = <&apps_iommu 0x15>;
+
+				ports {
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					port@0 {
+						reg = <0>;
+
+						mdp5_intf1_out: endpoint {
+							remote-endpoint = <&mdss_dsi0_in>;
+						};
+					};
+				};
+			};
+
+			mdss_dsi0: dsi@1a94000 {
+				compatible = "qcom,mdss-dsi-ctrl";
+				reg = <0x01a94000 0x300>;
+				reg-names = "dsi_ctrl";
+
+				interrupt-parent = <&mdss>;
+				interrupts = <4>;
+
+				assigned-clocks = <&gcc BYTE0_CLK_SRC>,
+						  <&gcc PCLK0_CLK_SRC>;
+				assigned-clock-parents = <&mdss_dsi0_phy 0>,
+							 <&mdss_dsi0_phy 1>;
+
+				clocks = <&gcc GCC_MDSS_MDP_CLK>,
+					 <&gcc GCC_MDSS_AHB_CLK>,
+					 <&gcc GCC_MDSS_AXI_CLK>,
+					 <&gcc GCC_MDSS_BYTE0_CLK>,
+					 <&gcc GCC_MDSS_PCLK0_CLK>,
+					 <&gcc GCC_MDSS_ESC0_CLK>;
+				clock-names = "mdp_core",
+					      "iface",
+					      "bus",
+					      "byte",
+					      "pixel",
+					      "core";
+				phys = <&mdss_dsi0_phy>;
+
+				operating-points-v2 = <&mdss_dsi0_opp_table>;
+				power-domains = <&rpmpd MSM8917_VDDCX>;
+
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				ports {
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					port@0 {
+						reg = <0>;
+
+						mdss_dsi0_in: endpoint {
+							remote-endpoint = <&mdp5_intf1_out>;
+						};
+					};
+
+					port@1 {
+						reg = <1>;
+
+						mdss_dsi0_out: endpoint {
+						};
+					};
+				};
+
+				mdss_dsi0_opp_table: opp-table {
+					compatible = "operating-points-v2";
+
+					opp-125000000 {
+						opp-hz = /bits/ 64 <125000000>;
+						required-opps = <&rpmpd_opp_svs>;
+					};
+
+					opp-187500000 {
+						opp-hz = /bits/ 64 <187500000>;
+						required-opps = <&rpmpd_opp_nom>;
+					};
+				};
+			};
+
+			mdss_dsi0_phy: phy@1a94a00 {
+				compatible = "qcom,dsi-phy-28nm-8937";
+				reg = <0x01a94a00 0xd4>,
+				      <0x01a94400 0x280>,
+				      <0x01a94b80 0x30>;
+				reg-names = "dsi_pll",
+					    "dsi_phy",
+					    "dsi_phy_regulator";
+
+				#clock-cells = <1>;
+				#phy-cells = <0>;
+
+				clocks = <&gcc GCC_MDSS_AHB_CLK>,
+					 <&xo_board>;
+				clock-names = "iface", "ref";
+			};
+		};
+
+		apps_iommu: iommu@1e20000 {
+			compatible = "qcom,msm8917-iommu", "qcom,msm-iommu-v1";
+			ranges = <0 0x01e20000 0x20000>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			#iommu-cells = <1>;
+
+			clocks = <&gcc GCC_SMMU_CFG_CLK>,
+				 <&gcc GCC_APSS_TCU_CLK>;
+			clock-names = "iface", "bus";
+
+			qcom,iommu-secure-id = <17>;
+
+			/* VFE */
+			iommu-ctx@14000 {
+				compatible = "qcom,msm-iommu-v1-ns";
+				reg = <0x14000 0x1000>;
+				interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
+			};
+
+			/* MDP_0 */
+			iommu-ctx@15000 {
+				compatible = "qcom,msm-iommu-v1-ns";
+				reg = <0x15000 0x1000>;
+				interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
+			};
+
+			/* VENUS_NS */
+			iommu-ctx@16000 {
+				compatible = "qcom,msm-iommu-v1-ns";
+				reg = <0x16000 0x1000>;
+				interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
+			};
+		};
+
+		gpu_iommu: iommu@1f08000 {
+			compatible = "qcom,msm8917-iommu", "qcom,msm-iommu-v1";
+			ranges = <0 0x01f08000 0x10000>;
+
+			#address-cells = <1>;
+			#size-cells = <1>;
+			#iommu-cells = <1>;
+
+			clocks = <&gcc GCC_SMMU_CFG_CLK>,
+				 <&gcc GCC_GFX_TCU_CLK>;
+			clock-names = "iface", "bus";
+			qcom,iommu-secure-id = <18>;
+
+			iommu-ctx@0 {
+				compatible = "qcom,msm-iommu-v2-ns";
+				reg = <0 0x1000>;
+				interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
+			};
+		};
+
+		gpu: gpu@1c00000 {
+			compatible = "qcom,adreno-306.32", "qcom,adreno";
+			reg = <0x01c00000 0x20000>;
+			reg-names = "kgsl_3d0_reg_memory";
+			interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "kgsl_3d0_irq";
+			clock-names = "core",
+				      "iface",
+				      "mem_iface",
+				      "alt_mem_iface",
+				      "gfx3d";
+			clocks = <&gcc GCC_OXILI_GFX3D_CLK>,
+				 <&gcc GCC_OXILI_AHB_CLK>,
+				 <&gcc GCC_BIMC_GFX_CLK>,
+				 <&gcc GCC_BIMC_GPU_CLK>,
+				 <&gcc GFX3D_CLK_SRC>;
+			power-domains = <&gcc OXILI_GX_GDSC>;
+			operating-points-v2 = <&gpu_opp_table>;
+			#cooling-cells = <2>;
+
+			iommus = <&gpu_iommu 0>;
+
+			status = "disabled";
+
+			gpu_opp_table: opp-table {
+				compatible = "operating-points-v2";
+
+				opp-19200000 {
+					opp-hz = /bits/ 64 <19200000>;
+				};
+
+				opp-270000000 {
+					opp-hz = /bits/ 64 <270000000>;
+				};
+
+				opp-400000000 {
+					opp-hz = /bits/ 64 <400000000>;
+				};
+
+				opp-484800000 {
+					opp-hz = /bits/ 64 <484800000>;
+				};
+
+				opp-523200000 {
+					opp-hz = /bits/ 64 <523200000>;
+				};
+
+				opp-598000000 {
+					opp-hz = /bits/ 64 <598000000>;
+				};
+			};
+		};
+
+		spmi_bus: spmi@200f000 {
+			compatible = "qcom,spmi-pmic-arb";
+			reg = <0x0200f000 0x001000>,
+			      <0x02400000 0x800000>,
+			      <0x02c00000 0x800000>,
+			      <0x03800000 0x200000>,
+			      <0x0200a000 0x002100>;
+			reg-names = "core",
+				    "chnls",
+				    "obsrvr",
+				    "intr",
+				    "cnfg";
+			interrupt-names = "periph_irq";
+			interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
+			qcom,ee = <0>;
+			qcom,channel = <0>;
+			#address-cells = <2>;
+			#size-cells = <0>;
+			interrupt-controller;
+			#interrupt-cells = <4>;
+		};
+
+		bam_dmux_dma: dma-controller@4044000 {
+			compatible = "qcom,bam-v1.7.0";
+			reg = <0x04044000 0x19000>;
+			interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
+			#dma-cells = <1>;
+			qcom,ee = <0>;
+
+			num-channels = <6>;
+			qcom,num-ees = <1>;
+			qcom,powered-remotely;
+
+			status = "disabled";
+		};
+
+		sdhc_1: mmc@7824900 {
+			compatible = "qcom,sdhci-msm-v4";
+			reg = <0x07824900 0x500>,
+			      <0x07824000 0x800>;
+			reg-names = "hc", "core";
+
+			interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "hc_irq", "pwr_irq";
+			clocks = <&gcc GCC_SDCC1_AHB_CLK>,
+				 <&gcc GCC_SDCC1_APPS_CLK>,
+				 <&xo_board>;
+			clock-names = "iface", "core", "xo";
+			pinctrl-0 = <&sdc1_default>;
+			pinctrl-1 = <&sdc1_sleep>;
+			pinctrl-names = "default", "sleep";
+			power-domains = <&rpmpd MSM8917_VDDCX>;
+			mmc-hs200-1_8v;
+			mmc-hs400-1_8v;
+			mmc-ddr-1_8v;
+			bus-width = <8>;
+			non-removable;
+			status = "disabled";
+		};
+
+		sdhc_2: mmc@7864900 {
+			compatible = "qcom,sdhci-msm-v4";
+			reg = <0x07864900 0x500>,
+			      <0x07864000 0x800>;
+			reg-names = "hc", "core";
+
+			interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "hc_irq", "pwr_irq";
+			clocks = <&gcc GCC_SDCC2_AHB_CLK>,
+				 <&gcc GCC_SDCC2_APPS_CLK>,
+				 <&xo_board>;
+			clock-names = "iface", "core", "xo";
+			pinctrl-0 = <&sdc2_default>;
+			pinctrl-1 = <&sdc2_sleep>;
+			pinctrl-names = "default", "sleep";
+			power-domains = <&rpmpd MSM8917_VDDCX>;
+			bus-width = <4>;
+			status = "disabled";
+		};
+
+		blsp1_dma: dma-controller@7884000 {
+			compatible = "qcom,bam-v1.7.0";
+			reg = <0x07884000 0x1f000>;
+			interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&gcc GCC_BLSP1_AHB_CLK>;
+			clock-names = "bam_clk";
+			qcom,controlled-remotely;
+			#dma-cells = <1>;
+			num-channels = <12>;
+			qcom,num-ees = <4>;
+			qcom,ee = <0>;
+		};
+
+		blsp2_dma: dma-controller@7ac4000 {
+			compatible = "qcom,bam-v1.7.0";
+			reg = <0x07ac4000 0x1d000>;
+			interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&gcc GCC_BLSP2_AHB_CLK>;
+			clock-names = "bam_clk";
+			qcom,controlled-remotely;
+			#dma-cells = <1>;
+			num-channels = <10>;
+			qcom,num-ees = <4>;
+			qcom,ee = <0>;
+		};
+
+		blsp1_uart1: serial@78af000 {
+			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
+			reg = <0x078af000 0x200>;
+			interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>,
+				 <&gcc GCC_BLSP1_AHB_CLK>;
+			clock-names = "core", "iface";
+			dmas = <&blsp1_dma 0>, <&blsp1_dma 1>;
+			dma-names = "tx", "rx";
+			pinctrl-0 = <&blsp1_uart1_default>;
+			pinctrl-1 = <&blsp1_uart1_sleep>;
+			pinctrl-names = "default", "sleep";
+			status = "disabled";
+		};
+
+		blsp1_uart2: serial@78b0000 {
+			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
+			reg = <0x078b0000 0x200>;
+			interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
+				 <&gcc GCC_BLSP1_AHB_CLK>;
+			clock-names = "core", "iface";
+			dmas = <&blsp1_dma 2>, <&blsp1_dma 3>;
+			dma-names = "tx", "rx";
+			pinctrl-0 = <&blsp1_uart2_default>;
+			pinctrl-1 = <&blsp1_uart2_sleep>;
+			pinctrl-names = "default", "sleep";
+			status = "disabled";
+		};
+
+		blsp1_i2c2: i2c@78b6000 {
+			compatible = "qcom,i2c-qup-v2.2.1";
+			reg = <0x078b6000 0x600>;
+			interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>,
+				 <&gcc GCC_BLSP1_AHB_CLK>;
+			clock-names = "core", "iface";
+			dmas = <&blsp1_dma 6>, <&blsp1_dma 7>;
+			dma-names = "tx", "rx";
+			pinctrl-0 = <&blsp1_i2c2_default>;
+			pinctrl-1 = <&blsp1_i2c2_sleep>;
+			pinctrl-names = "default", "sleep";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		blsp1_i2c3: i2c@78b7000 {
+			compatible = "qcom,i2c-qup-v2.2.1";
+			reg = <0x078b7000 0x600>;
+			interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>,
+				 <&gcc GCC_BLSP1_AHB_CLK>;
+			clock-names = "core", "iface";
+			dmas = <&blsp1_dma 8>, <&blsp1_dma 9>;
+			dma-names = "tx", "rx";
+			pinctrl-0 = <&blsp1_i2c3_default>;
+			pinctrl-1 = <&blsp1_i2c3_sleep>;
+			pinctrl-names = "default", "sleep";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		blsp1_spi3: spi@78b7000 {
+			compatible = "qcom,spi-qup-v2.2.1";
+			reg = <0x078b7000 0x600>;
+			interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>,
+				 <&gcc GCC_BLSP1_AHB_CLK>;
+			clock-names = "core", "iface";
+			dmas = <&blsp1_dma 8>, <&blsp1_dma 9>;
+			dma-names = "tx", "rx";
+			pinctrl-0 = <&blsp1_spi3_default>;
+			pinctrl-1 = <&blsp1_spi3_sleep>;
+			pinctrl-names = "default", "sleep";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		blsp1_i2c4: i2c@78b8000 {
+			compatible = "qcom,i2c-qup-v2.2.1";
+			reg = <0x078b8000 0x500>;
+			interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>,
+				 <&gcc GCC_BLSP1_AHB_CLK>;
+			clock-names = "core", "iface";
+			dmas = <&blsp1_dma 10>, <&blsp1_dma 11>;
+			dma-names = "tx", "rx";
+			pinctrl-0 = <&blsp1_i2c4_default>;
+			pinctrl-1 = <&blsp1_i2c4_sleep>;
+			pinctrl-names = "default", "sleep";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		blsp2_i2c1: i2c@7af5000 {
+			compatible = "qcom,i2c-qup-v2.2.1";
+			reg = <0x07af5000 0x600>;
+			interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>,
+				 <&gcc GCC_BLSP2_AHB_CLK>;
+			clock-names = "core", "iface";
+			dmas = <&blsp2_dma 4>, <&blsp2_dma 5>;
+			dma-names = "tx", "rx";
+			pinctrl-0 = <&blsp2_i2c1_default>;
+			pinctrl-1 = <&blsp2_i2c1_sleep>;
+			pinctrl-names = "default", "sleep";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		blsp2_spi2: spi@7af6000 {
+			compatible = "qcom,spi-qup-v2.2.1";
+			reg = <0x07af6000 0x600>;
+			interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&gcc GCC_BLSP2_QUP2_SPI_APPS_CLK>,
+				 <&gcc GCC_BLSP2_AHB_CLK>;
+			clock-names = "core", "iface";
+			dmas = <&blsp2_dma 6>, <&blsp2_dma 7>;
+			dma-names = "tx", "rx";
+			pinctrl-0 = <&blsp2_spi2_default>;
+			pinctrl-1 = <&blsp2_spi2_sleep>;
+			pinctrl-names = "default", "sleep";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		usb: usb@78db000 {
+			compatible = "qcom,ci-hdrc";
+			reg = <0x078db000 0x200>,
+			      <0x078db200 0x200>;
+			interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&gcc GCC_USB_HS_AHB_CLK>,
+				 <&gcc GCC_USB_HS_SYSTEM_CLK>;
+			clock-names = "iface", "core";
+			assigned-clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>;
+			assigned-clock-rates = <80000000>;
+			resets = <&gcc GCC_USB_HS_BCR>;
+			reset-names = "core";
+			phy_type = "ulpi";
+			dr_mode = "otg";
+			hnp-disable;
+			srp-disable;
+			adp-disable;
+			ahb-burst-config = <0>;
+			phy-names = "usb-phy";
+			phys = <&usb_hs_phy>;
+			status = "disabled";
+			#reset-cells = <1>;
+		};
+
+		wcnss: remoteproc@a204000 {
+			compatible = "qcom,pronto-v3-pil", "qcom,pronto";
+			reg = <0x0a204000 0x2000>,
+			      <0x0a202000 0x1000>,
+			      <0x0a21b000 0x3000>;
+			reg-names = "ccu", "dxe", "pmu";
+
+			memory-region = <&wcnss_mem>;
+
+			interrupts-extended = <&intc GIC_SPI 149 IRQ_TYPE_EDGE_RISING>,
+					      <&wcnss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
+					      <&wcnss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
+					      <&wcnss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
+					      <&wcnss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
+			interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack";
+
+			power-domains = <&rpmpd MSM8917_VDDCX>,
+					<&rpmpd MSM8917_VDDMX>;
+			power-domain-names = "cx", "mx";
+
+			qcom,smem-states = <&wcnss_smp2p_out 0>;
+			qcom,smem-state-names = "stop";
+
+			pinctrl-0 = <&wcnss_pin_a>;
+			pinctrl-names = "default";
+
+			status = "disabled";
+
+			wcnss_iris: iris {
+				clocks = <&rpmcc RPM_SMD_RF_CLK2>;
+				clock-names = "xo";
+			};
+
+			smd-edge {
+				interrupts = <GIC_SPI 142 IRQ_TYPE_EDGE_RISING>;
+
+				mboxes = <&apcs 17>;
+				qcom,smd-edge = <6>;
+				qcom,remote-pid = <4>;
+
+				label = "pronto";
+
+				wcnss_ctrl: wcnss {
+					compatible = "qcom,wcnss";
+					qcom,smd-channels = "WCNSS_CTRL";
+
+					qcom,mmio = <&wcnss>;
+
+					wcnss_bt: bluetooth {
+						compatible = "qcom,wcnss-bt";
+					};
+
+					wcnss_wifi: wifi {
+						compatible = "qcom,wcnss-wlan";
+
+						interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
+							     <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
+						interrupt-names = "tx", "rx";
+
+						qcom,smem-states = <&apps_smsm 10>, <&apps_smsm 9>;
+						qcom,smem-state-names = "tx-enable",
+									"tx-rings-empty";
+					};
+				};
+			};
+		};
+
+		intc: interrupt-controller@b000000 {
+			compatible = "qcom,msm-qgic2";
+			reg = <0x0b000000 0x1000>,
+			      <0x0b002000 0x1000>;
+			interrupt-controller;
+			#interrupt-cells = <3>;
+		};
+
+		apcs: mailbox@b011000 {
+			compatible = "qcom,msm8939-apcs-kpss-global", "syscon";
+			reg = <0x0b011000 0x1000>;
+			#mbox-cells = <1>;
+			clocks = <&a53pll>, <&gcc GPLL0_EARLY>, <&rpmcc RPM_SMD_XO_CLK_SRC>;
+			clock-names = "pll", "aux", "ref";
+			#clock-cells = <0>;
+		};
+
+		a53pll: clock@b016000 {
+			compatible = "qcom,msm8939-a53pll";
+			reg = <0x0b016000 0x40>;
+			clocks = <&xo_board>;
+			clock-names = "xo";
+			#clock-cells = <0>;
+			operating-points-v2 = <&pll_opp_table>;
+
+			pll_opp_table: opp-table {
+				compatible = "operating-points-v2";
+
+				opp-960000000 {
+					opp-hz = /bits/ 64 <960000000>;
+				};
+
+				opp-1094400000 {
+					opp-hz = /bits/ 64 <1094400000>;
+				};
+
+				opp-1248000000 {
+					opp-hz = /bits/ 64 <1248000000>;
+				};
+
+				opp-1401600000 {
+					opp-hz = /bits/ 64 <1401600000>;
+				};
+			};
+		};
+
+		watchdog@b017000 {
+			compatible = "qcom,apss-wdt-qcs404", "qcom,kpss-wdt";
+			reg = <0x0b017000 0x1000>;
+			clocks = <&sleep_clk>;
+		};
+
+		timer@b120000 {
+			compatible = "arm,armv7-timer-mem";
+			reg = <0x0b120000 0x1000>;
+			ranges;
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			frame@b121000 {
+				reg = <0x0b121000 0x1000>,
+				      <0x0b122000 0x1000>;
+				frame-number = <0>;
+				interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+			};
+
+			frame@b123000 {
+				reg = <0x0b123000 0x1000>;
+				frame-number = <1>;
+				interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+				status = "disabled";
+			};
+
+			frame@b124000 {
+				reg = <0x0b124000 0x1000>;
+				frame-number = <2>;
+				interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+				status = "disabled";
+			};
+
+			frame@b125000 {
+				reg = <0x0b125000 0x1000>;
+				frame-number = <3>;
+				interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+				status = "disabled";
+			};
+
+			frame@b126000 {
+				reg = <0x0b126000 0x1000>;
+				frame-number = <4>;
+				interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+				status = "disabled";
+			};
+
+			frame@b127000 {
+				reg = <0x0b127000 0x1000>;
+				frame-number = <5>;
+				interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
+				status = "disabled";
+			};
+
+			frame@b128000 {
+				reg = <0x0b128000 0x1000>;
+				frame-number = <6>;
+				interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+				status = "disabled";
+			};
+		};
+	};
+
+	timer {
+		compatible = "arm,armv8-timer";
+		interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+	};
+
+	thermal_zones: thermal-zones {
+		aoss-thermal {
+			polling-delay-passive = <250>;
+
+			thermal-sensors = <&tsens 0>;
+
+			trips {
+				aoss_alert0: trip-point0 {
+					temperature = <85000>;
+					hysteresis = <2000>;
+					type = "hot";
+				};
+			};
+		};
+
+		camera-thermal {
+			polling-delay-passive = <250>;
+
+			thermal-sensors = <&tsens 3>;
+
+			trips {
+				camera_alert0: trip-point0 {
+					temperature = <85000>;
+					hysteresis = <2000>;
+					type = "hot";
+				};
+			};
+		};
+
+		cpuss1-thermal {
+			polling-delay-passive = <250>;
+
+			thermal-sensors = <&tsens 4>;
+
+			cooling-maps {
+				map0 {
+					trip = <&cpuss1_alert0>;
+					cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+				};
+			};
+
+			trips {
+				cpuss1_alert0: trip-point0 {
+					temperature = <75000>;
+					hysteresis = <2000>;
+					type = "passive";
+				};
+
+				cpuss1_alert1: trip-point1 {
+					temperature = <85000>;
+					hysteresis = <2000>;
+					type = "hot";
+				};
+
+				cpuss1_crit: cpuss1-crit {
+					temperature = <100000>;
+					hysteresis = <2000>;
+					type = "critical";
+				};
+			};
+		};
+
+		cpu0-thermal {
+			polling-delay-passive = <250>;
+
+			thermal-sensors = <&tsens 5>;
+
+			cooling-maps {
+				map0 {
+					trip = <&cpu0_alert1>;
+					cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+				};
+			};
+
+			trips {
+				cpu0_alert0: trip-point0 {
+					temperature = <75000>;
+					hysteresis = <2000>;
+					type = "passive";
+				};
+
+				cpu0_alert1: trip-point1 {
+					temperature = <85000>;
+					hysteresis = <2000>;
+					type = "hot";
+				};
+
+				cpu0_crit: cpu-crit {
+					temperature = <100000>;
+					hysteresis = <2000>;
+					type = "critical";
+				};
+			};
+		};
+
+		cpu1-thermal {
+			polling-delay-passive = <250>;
+
+			thermal-sensors = <&tsens 6>;
+
+			cooling-maps {
+				map0 {
+					trip = <&cpu1_alert1>;
+					cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+				};
+			};
+
+			trips {
+				cpu1_alert0: trip-point0 {
+					temperature = <75000>;
+					hysteresis = <2000>;
+					type = "hot";
+				};
+
+				cpu1_alert1: trip-point1 {
+					temperature = <85000>;
+					hysteresis = <2000>;
+					type = "passive";
+				};
+
+				cpu1_crit: cpu-crit {
+					temperature = <100000>;
+					hysteresis = <2000>;
+					type = "critical";
+				};
+			};
+		};
+
+		cpu2-thermal {
+			polling-delay-passive = <250>;
+
+			thermal-sensors = <&tsens 7>;
+
+			cooling-maps {
+				map0 {
+					trip = <&cpu2_alert1>;
+					cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+				};
+			};
+
+			trips {
+				cpu2_alert0: trip-point0 {
+					temperature = <75000>;
+					hysteresis = <2000>;
+					type = "hot";
+				};
+
+				cpu2_alert1: trip-point1 {
+					temperature = <85000>;
+					hysteresis = <2000>;
+					type = "passive";
+				};
+
+				cpu2_crit: cpu-crit {
+					temperature = <100000>;
+					hysteresis = <2000>;
+					type = "critical";
+				};
+			};
+		};
+
+		cpu3-thermal {
+			polling-delay-passive = <250>;
+
+			thermal-sensors = <&tsens 8>;
+
+			cooling-maps {
+				map0 {
+					trip = <&cpu3_alert1>;
+					cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+				};
+			};
+
+			trips {
+				cpu3_alert0: trip-point0 {
+					temperature = <75000>;
+					hysteresis = <2000>;
+					type = "hot";
+				};
+
+				cpu3_alert1: trip-point1 {
+					temperature = <85000>;
+					hysteresis = <2000>;
+					type = "passive";
+				};
+
+				cpu3_crit: cpu-crit {
+					temperature = <100000>;
+					hysteresis = <2000>;
+					type = "critical";
+				};
+			};
+		};
+
+		gpu-thermal {
+			polling-delay-passive = <250>;
+
+			thermal-sensors = <&tsens 9>;
+
+			cooling-maps {
+				map0 {
+					trip = <&gpu_alert>;
+					cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+				};
+			};
+
+			trips {
+				gpu_alert: trip-point0 {
+					temperature = <70000>;
+					hysteresis = <2000>;
+					type = "passive";
+				};
+
+				gpu_crit: gpu-crit {
+					temperature = <90000>;
+					hysteresis = <2000>;
+					type = "critical";
+				};
+			};
+
+		};
+
+		mdm-core-thermal {
+			polling-delay-passive = <250>;
+
+			thermal-sensors = <&tsens 1>;
+
+			trips {
+				mdm_core_alert0: trip-point0 {
+					temperature = <85000>;
+					hysteresis = <2000>;
+					type = "hot";
+				};
+			};
+		};
+
+		q6-thermal {
+			polling-delay-passive = <250>;
+
+			thermal-sensors = <&tsens 2>;
+
+			trips {
+				q6_alert0: trip-point0 {
+					temperature = <85000>;
+					hysteresis = <2000>;
+					type = "hot";
+				};
+			};
+		};
+	};
+};
diff --git a/dts/upstream/src/arm64/qcom/msm8939.dtsi b/dts/upstream/src/arm64/qcom/msm8939.dtsi
index 7a6f1eeaa3f..7cd5660de1b 100644
--- a/dts/upstream/src/arm64/qcom/msm8939.dtsi
+++ b/dts/upstream/src/arm64/qcom/msm8939.dtsi
@@ -34,7 +34,7 @@
 		sleep_clk: sleep-clk {
 			compatible = "fixed-clock";
 			#clock-cells = <0>;
-			clock-frequency = <32768>;
+			clock-frequency = <32764>;
 		};
 	};
 
diff --git a/dts/upstream/src/arm64/qcom/msm8994-huawei-angler-rev-101.dts b/dts/upstream/src/arm64/qcom/msm8994-huawei-angler-rev-101.dts
index 29e79ae0849..1aca11daf83 100644
--- a/dts/upstream/src/arm64/qcom/msm8994-huawei-angler-rev-101.dts
+++ b/dts/upstream/src/arm64/qcom/msm8994-huawei-angler-rev-101.dts
@@ -2,12 +2,13 @@
 /*
  * Copyright (c) 2015, Huawei Inc. All rights reserved.
  * Copyright (c) 2016, The Linux Foundation. All rights reserved.
- * Copyright (c) 2021-2023, Petr Vorel <petr.vorel@gmail.com>
+ * Copyright (c) 2021-2024, Petr Vorel <petr.vorel@gmail.com>
  */
 
 /dts-v1/;
 
 #include "msm8994.dtsi"
+#include "pm8994.dtsi"
 
 / {
 	model = "Huawei Nexus 6P";
@@ -46,6 +47,24 @@
 			no-map;
 		};
 	};
+
+	gpio-keys {
+		compatible = "gpio-keys";
+		autorepeat;
+
+		button-vol-up {
+			label = "volume up";
+			gpios = <&pm8994_gpios 3 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_VOLUMEUP>;
+			wakeup-source;
+			debounce-interval = <15>;
+		};
+	};
+};
+
+&pm8994_resin {
+	linux,code = <KEY_VOLUMEDOWN>;
+	status = "okay";
 };
 
 &blsp1_uart2 {
diff --git a/dts/upstream/src/arm64/qcom/msm8994-msft-lumia-octagon.dtsi b/dts/upstream/src/arm64/qcom/msm8994-msft-lumia-octagon.dtsi
index 10cd244dea4..4c983b10dd9 100644
--- a/dts/upstream/src/arm64/qcom/msm8994-msft-lumia-octagon.dtsi
+++ b/dts/upstream/src/arm64/qcom/msm8994-msft-lumia-octagon.dtsi
@@ -387,11 +387,6 @@
 
 		interrupts = <&tlmm 96 IRQ_TYPE_EDGE_FALLING>;
 
-		button_num = <8>;
-		touchpad_num = <0>;
-		wheel_num = <0>;
-		slider_num = <0>;
-
 		vcc-supply = <&vreg_l18a_2p85>;
 	};
 
diff --git a/dts/upstream/src/arm64/qcom/msm8994.dtsi b/dts/upstream/src/arm64/qcom/msm8994.dtsi
index 1acb0f15951..b5cbdd620bb 100644
--- a/dts/upstream/src/arm64/qcom/msm8994.dtsi
+++ b/dts/upstream/src/arm64/qcom/msm8994.dtsi
@@ -34,7 +34,7 @@
 		sleep_clk: sleep-clk {
 			compatible = "fixed-clock";
 			#clock-cells = <0>;
-			clock-frequency = <32768>;
+			clock-frequency = <32764>;
 			clock-output-names = "sleep_clk";
 		};
 	};
@@ -437,6 +437,15 @@
 			#size-cells = <1>;
 			ranges;
 
+			interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "pwr_event",
+					  "qusb2_phy",
+					  "hs_phy_irq",
+					  "ss_phy_irq";
+
 			clocks = <&gcc GCC_USB30_MASTER_CLK>,
 				 <&gcc GCC_SYS_NOC_USB3_AXI_CLK>,
 				 <&gcc GCC_USB30_SLEEP_CLK>,
diff --git a/dts/upstream/src/arm64/qcom/msm8996-xiaomi-gemini.dts b/dts/upstream/src/arm64/qcom/msm8996-xiaomi-gemini.dts
index f8e9d90afab..dbad8f57f2f 100644
--- a/dts/upstream/src/arm64/qcom/msm8996-xiaomi-gemini.dts
+++ b/dts/upstream/src/arm64/qcom/msm8996-xiaomi-gemini.dts
@@ -64,7 +64,7 @@
 		};
 
 		led@1 {
-			reg = <0>;
+			reg = <1>;
 			chan-name = "button-backlight1";
 			led-cur = /bits/ 8 <0x32>;
 			max-cur = /bits/ 8 <0xc8>;
diff --git a/dts/upstream/src/arm64/qcom/msm8996.dtsi b/dts/upstream/src/arm64/qcom/msm8996.dtsi
index b379623c1b8..4719e1fc70d 100644
--- a/dts/upstream/src/arm64/qcom/msm8996.dtsi
+++ b/dts/upstream/src/arm64/qcom/msm8996.dtsi
@@ -3065,9 +3065,14 @@
 			#size-cells = <1>;
 			ranges;
 
-			interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
+			interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
-			interrupt-names = "hs_phy_irq", "ss_phy_irq";
+			interrupt-names = "pwr_event",
+					  "qusb2_phy",
+					  "hs_phy_irq",
+					  "ss_phy_irq";
 
 			clocks = <&gcc GCC_SYS_NOC_USB3_AXI_CLK>,
 				 <&gcc GCC_USB30_MASTER_CLK>,
diff --git a/dts/upstream/src/arm64/qcom/pm660l.dtsi b/dts/upstream/src/arm64/qcom/pm660l.dtsi
index 0094e0ef058..3f8b9eafe16 100644
--- a/dts/upstream/src/arm64/qcom/pm660l.dtsi
+++ b/dts/upstream/src/arm64/qcom/pm660l.dtsi
@@ -70,6 +70,12 @@
 			status = "disabled";
 		};
 
+		pm660l_flash: led-controller@d300 {
+			compatible = "qcom,pm660l-flash-led", "qcom,spmi-flash-led";
+			reg = <0xd300>;
+			status = "disabled";
+		};
+
 		pm660l_wled: leds@d800 {
 			compatible = "qcom,pm660l-wled";
 			reg = <0xd800>, <0xd900>;
diff --git a/dts/upstream/src/arm64/qcom/pm8150.dtsi b/dts/upstream/src/arm64/qcom/pm8150.dtsi
index a74a7ff660d..d2568686a09 100644
--- a/dts/upstream/src/arm64/qcom/pm8150.dtsi
+++ b/dts/upstream/src/arm64/qcom/pm8150.dtsi
@@ -49,8 +49,6 @@
 		pon: pon@800 {
 			compatible = "qcom,pm8998-pon";
 			reg = <0x0800>;
-			mode-bootloader = <0x2>;
-			mode-recovery = <0x1>;
 
 			pon_pwrkey: pwrkey {
 				compatible = "qcom,pm8941-pwrkey";
diff --git a/dts/upstream/src/arm64/qcom/pm8937.dtsi b/dts/upstream/src/arm64/qcom/pm8937.dtsi
new file mode 100644
index 00000000000..42b3575b36f
--- /dev/null
+++ b/dts/upstream/src/arm64/qcom/pm8937.dtsi
@@ -0,0 +1,150 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2023, Dang Huynh <danct12@riseup.net>
+ */
+
+#include <dt-bindings/iio/qcom,spmi-vadc.h>
+#include <dt-bindings/input/linux-event-codes.h>
+#include <dt-bindings/spmi/spmi.h>
+
+/ {
+	thermal-zones {
+		pm8937-thermal {
+			polling-delay-passive = <0>;
+			polling-delay = <0>;
+			thermal-sensors = <&pm8937_temp>;
+
+			trips {
+				trip0 {
+					temperature = <105000>;
+					hysteresis = <0>;
+					type = "passive";
+				};
+
+				trip1 {
+					temperature = <125000>;
+					hysteresis = <0>;
+					type = "hot";
+				};
+
+				trip2 {
+					temperature = <145000>;
+					hysteresis = <0>;
+					type = "critical";
+				};
+			};
+		};
+	};
+};
+
+&spmi_bus {
+	pmic@0 {
+		compatible = "qcom,pm8937", "qcom,spmi-pmic";
+		reg = <0x0 SPMI_USID>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		pon@800 {
+			compatible = "qcom,pm8916-pon";
+			reg = <0x800>;
+			mode-bootloader = <0x2>;
+			mode-recovery = <0x1>;
+
+			pm8937_pwrkey: pwrkey {
+				compatible = "qcom,pm8941-pwrkey";
+				interrupts = <0 0x8 0 IRQ_TYPE_EDGE_BOTH>;
+				debounce = <15625>;
+				bias-pull-up;
+				linux,code = <KEY_POWER>;
+			};
+
+			pm8937_resin: resin {
+				compatible = "qcom,pm8941-resin";
+				interrupts = <0 0x8 1 IRQ_TYPE_EDGE_BOTH>;
+				debounce = <15625>;
+				bias-pull-up;
+				status = "disabled";
+			};
+		};
+
+		pm8937_gpios: gpio@c000 {
+			compatible = "qcom,pm8937-gpio", "qcom,spmi-gpio";
+			reg = <0xc000>;
+			gpio-controller;
+			gpio-ranges = <&pm8937_gpios 0 0 8>;
+			#gpio-cells = <2>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		pm8937_mpps: mpps@a000 {
+			compatible = "qcom,pm8937-mpp", "qcom,spmi-mpp";
+			reg = <0xa000>;
+			gpio-controller;
+			gpio-ranges = <&pm8937_mpps 0 0 4>;
+			#gpio-cells = <2>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		pm8937_temp: temp-alarm@2400 {
+			compatible = "qcom,spmi-temp-alarm";
+			reg = <0x2400>;
+			interrupts = <0 0x24 0 IRQ_TYPE_EDGE_RISING>;
+			io-channels = <&pm8937_vadc VADC_DIE_TEMP>;
+			io-channel-names = "thermal";
+			#thermal-sensor-cells = <0>;
+		};
+
+		pm8937_vadc: adc@3100 {
+			compatible = "qcom,spmi-vadc";
+			reg = <0x3100>;
+			interrupts = <0 0x31 0 IRQ_TYPE_EDGE_RISING>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			#io-channel-cells = <1>;
+
+			channel@8 {
+				reg = <VADC_DIE_TEMP>;
+			};
+
+			channel@9 {
+				reg = <VADC_REF_625MV>;
+			};
+
+			channel@a {
+				reg = <VADC_REF_1250MV>;
+			};
+
+			channel@c {
+				reg = <VADC_SPARE1>;
+			};
+
+			channel@e {
+				reg = <VADC_GND_REF>;
+			};
+
+			channel@f {
+				reg = <VADC_VDD_VADC>;
+			};
+		};
+
+		rtc@6000 {
+			compatible = "qcom,pm8941-rtc";
+			reg = <0x6000>, <0x6100>;
+			reg-names = "rtc", "alarm";
+			interrupts = <0x0 0x61 0x1 IRQ_TYPE_EDGE_RISING>;
+		};
+	};
+
+	pmic@1 {
+		compatible = "qcom,pm8937", "qcom,spmi-pmic";
+		reg = <0x1 SPMI_USID>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		pm8937_spmi_regulators: regulators {
+			compatible = "qcom,pm8937-regulators";
+		};
+	};
+};
diff --git a/dts/upstream/src/arm64/qcom/pmd8028.dtsi b/dts/upstream/src/arm64/qcom/pmd8028.dtsi
new file mode 100644
index 00000000000..a00913e28a4
--- /dev/null
+++ b/dts/upstream/src/arm64/qcom/pmd8028.dtsi
@@ -0,0 +1,62 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/spmi/spmi.h>
+
+/ {
+	thermal-zones {
+		pmd8028-thermal {
+			polling-delay-passive = <100>;
+			thermal-sensors = <&pmd8028_temp_alarm>;
+
+			trips {
+				pmd8028_trip0: trip0 {
+					temperature = <95000>;
+					hysteresis = <0>;
+					type = "passive";
+				};
+
+				pmd8028_trip1: trip1 {
+					temperature = <115000>;
+					hysteresis = <0>;
+					type = "hot";
+				};
+
+				pmd8028_trip2: trip2 {
+					temperature = <145000>;
+					hysteresis = <0>;
+					type = "critical";
+				};
+			};
+		};
+	};
+};
+
+&spmi_bus {
+	pmd8028: pmic@4 {
+		compatible = "qcom,pmd8028", "qcom,spmi-pmic";
+		reg = <0x4 SPMI_USID>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		pmd8028_temp_alarm: temp-alarm@a00 {
+			compatible = "qcom,spmi-temp-alarm";
+			reg = <0xa00>;
+			interrupts = <0x4 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
+			#thermal-sensor-cells = <0>;
+		};
+
+		pmd8028_gpios: gpio@8800 {
+			compatible = "qcom,pmd8028-gpio", "qcom,spmi-gpio";
+			reg = <0x8800>;
+			gpio-controller;
+			gpio-ranges = <&pmd8028_gpios 0 0 4>;
+			#gpio-cells = <2>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+	};
+};
diff --git a/dts/upstream/src/arm64/qcom/pmi8950.dtsi b/dts/upstream/src/arm64/qcom/pmi8950.dtsi
index 4aff437263a..3d3b1cd97cc 100644
--- a/dts/upstream/src/arm64/qcom/pmi8950.dtsi
+++ b/dts/upstream/src/arm64/qcom/pmi8950.dtsi
@@ -84,6 +84,23 @@
 		#address-cells = <1>;
 		#size-cells = <0>;
 
+		labibb {
+			compatible = "qcom,pmi8950-lab-ibb",
+				     "qcom,pmi8998-lab-ibb";
+
+			ibb: ibb {
+				interrupts = <0x3 0xdc 0x2 IRQ_TYPE_EDGE_RISING>,
+					     <0x3 0xdc 0x0 IRQ_TYPE_LEVEL_LOW>;
+				interrupt-names = "sc-err", "ocp";
+			};
+
+			lab: lab {
+				interrupts = <0x3 0xde 0x1 IRQ_TYPE_EDGE_RISING>,
+					     <0x3 0xde 0x0 IRQ_TYPE_LEVEL_LOW>;
+				interrupt-names = "sc-err", "ocp";
+			};
+		};
+
 		pmi8950_pwm: pwm {
 			compatible = "qcom,pmi8950-pwm";
 			#pwm-cells = <2>;
diff --git a/dts/upstream/src/arm64/qcom/pmih0108.dtsi b/dts/upstream/src/arm64/qcom/pmih0108.dtsi
new file mode 100644
index 00000000000..1c875995d88
--- /dev/null
+++ b/dts/upstream/src/arm64/qcom/pmih0108.dtsi
@@ -0,0 +1,68 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/spmi/spmi.h>
+
+/ {
+	thermal-zones {
+		pmih0108-thermal {
+			polling-delay-passive = <100>;
+			thermal-sensors = <&pmih0108_temp_alarm>;
+
+			trips {
+				trip0 {
+					temperature = <95000>;
+					hysteresis = <0>;
+					type = "passive";
+				};
+
+				trip1 {
+					temperature = <115000>;
+					hysteresis = <0>;
+					type = "hot";
+				};
+
+				trip2 {
+					temperature = <145000>;
+					hysteresis = <0>;
+					type = "critical";
+				};
+			};
+		};
+	};
+};
+
+&spmi_bus {
+	pmih0108: pmic@7 {
+		compatible = "qcom,pmih0108", "qcom,spmi-pmic";
+		reg = <0x7 SPMI_USID>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		pmih0108_temp_alarm: temp-alarm@a00 {
+			compatible = "qcom,spmi-temp-alarm";
+			reg = <0xa00>;
+			interrupts = <0x7 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
+			#thermal-sensor-cells = <0>;
+		};
+
+		pmih0108_gpios: gpio@8800 {
+			compatible = "qcom,pmih0108-gpio", "qcom,spmi-gpio";
+			reg = <0x8800>;
+			gpio-controller;
+			gpio-ranges = <&pmih0108_gpios 0 0 18>;
+			#gpio-cells = <2>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		pmih0108_eusb2_repeater: phy@fd00 {
+			compatible = "qcom,pm8550b-eusb2-repeater";
+			reg = <0xfd00>;
+			#phy-cells = <0>;
+		};
+	};
+};
diff --git a/dts/upstream/src/arm64/qcom/pmk8350.dtsi b/dts/upstream/src/arm64/qcom/pmk8350.dtsi
index f0ed15458dd..565752af220 100644
--- a/dts/upstream/src/arm64/qcom/pmk8350.dtsi
+++ b/dts/upstream/src/arm64/qcom/pmk8350.dtsi
@@ -76,6 +76,14 @@
 			status = "disabled";
 		};
 
+		pmk8350_sdam_1: nvram@7000 {
+			compatible = "qcom,spmi-sdam";
+			reg = <0x7000>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0 0x7000 0x100>;
+		};
+
 		pmk8350_sdam_2: nvram@7100 {
 			compatible = "qcom,spmi-sdam";
 			reg = <0x7100>;
@@ -89,6 +97,70 @@
 			};
 		};
 
+		pmk8350_sdam_5: nvram@7400 {
+			compatible = "qcom,spmi-sdam";
+			reg = <0x7400>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0 0x7400 0x100>;
+		};
+
+		pmk8350_sdam_13: nvram@7c00 {
+			compatible = "qcom,spmi-sdam";
+			reg = <0x7c00>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0 0x7c00 0x100>;
+		};
+
+		pmk8350_sdam_14: nvram@7d00 {
+			compatible = "qcom,spmi-sdam";
+			reg = <0x7d00>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0 0x7d00 0x100>;
+		};
+
+		pmk8350_sdam_21: nvram@8400 {
+			compatible = "qcom,spmi-sdam";
+			reg = <0x8400>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0 0x8400 0x100>;
+		};
+
+		pmk8350_sdam_22: nvram@8500 {
+			compatible = "qcom,spmi-sdam";
+			reg = <0x8500>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0 0x8500 0x100>;
+		};
+
+		pmk8350_sdam_23: nvram@8600 {
+			compatible = "qcom,spmi-sdam";
+			reg = <0x8600>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0 0x8600 0x100>;
+		};
+
+		pmk8350_sdam_41: nvram@9800 {
+			compatible = "qcom,spmi-sdam";
+			reg = <0x9800>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0 0x9800 0x100>;
+		};
+
+		pmk8350_sdam_46: nvram@9d00 {
+			compatible = "qcom,spmi-sdam";
+			reg = <0x9d00>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0 0x9d00 0x100>;
+		};
+
 		pmk8350_gpios: gpio@b000 {
 			compatible = "qcom,pmk8350-gpio", "qcom,spmi-gpio";
 			reg = <0xb000>;
diff --git a/dts/upstream/src/arm64/qcom/qcm6490-fairphone-fp5.dts b/dts/upstream/src/arm64/qcom/qcm6490-fairphone-fp5.dts
index fdc62f1b1c5..769c66cb5d1 100644
--- a/dts/upstream/src/arm64/qcom/qcm6490-fairphone-fp5.dts
+++ b/dts/upstream/src/arm64/qcom/qcm6490-fairphone-fp5.dts
@@ -108,6 +108,36 @@
 		};
 	};
 
+	vreg_afvdd_2p8: regulator-afvdd-2p8 {
+		compatible = "regulator-fixed";
+		regulator-name = "AFVDD_2P8";
+		regulator-min-microvolt = <2800000>;
+		regulator-max-microvolt = <2800000>;
+		gpio = <&tlmm 68 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+		vin-supply = <&vreg_bob>;
+	};
+
+	vreg_ois_avdd0_1p8: regulator-ois-avdd0-1p8 {
+		compatible = "regulator-fixed";
+		regulator-name = "OIS_AVDD0_1P8";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+		gpio = <&tlmm 157 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+		vin-supply = <&vreg_bob>;
+	};
+
+	vreg_ois_dvdd_1p1: regulator-ois-dvdd-1p1 {
+		compatible = "regulator-fixed";
+		regulator-name = "OIS_DVDD_1P1";
+		regulator-min-microvolt = <1100000>;
+		regulator-max-microvolt = <1100000>;
+		gpio = <&tlmm 97 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+		vin-supply = <&vreg_s8b>;
+	};
+
 	reserved-memory {
 		cont_splash_mem: cont-splash@e1000000 {
 			reg = <0x0 0xe1000000 0x0 0x2300000>;
@@ -134,36 +164,6 @@
 		};
 	};
 
-	ois_avdd0_1p8: regulator-ois-avdd0-1p8 {
-		compatible = "regulator-fixed";
-		regulator-name = "OIS_AVDD0_1P8";
-		regulator-min-microvolt = <1800000>;
-		regulator-max-microvolt = <1800000>;
-		gpio = <&tlmm 157 GPIO_ACTIVE_HIGH>;
-		enable-active-high;
-		vin-supply = <&vreg_bob>;
-	};
-
-	ois_dvdd_1p1: regulator-ois-dvdd-1p1 {
-		compatible = "regulator-fixed";
-		regulator-name = "OIS_DVDD_1P1";
-		regulator-min-microvolt = <1100000>;
-		regulator-max-microvolt = <1100000>;
-		gpio = <&tlmm 97 GPIO_ACTIVE_HIGH>;
-		enable-active-high;
-		vin-supply = <&vreg_s8b>;
-	};
-
-	afvdd_2p8: regulator-afvdd-2p8 {
-		compatible = "regulator-fixed";
-		regulator-name = "AFVDD_2P8";
-		regulator-min-microvolt = <2800000>;
-		regulator-max-microvolt = <2800000>;
-		gpio = <&tlmm 68 GPIO_ACTIVE_HIGH>;
-		enable-active-high;
-		vin-supply = <&vreg_bob>;
-	};
-
 	thermal-zones {
 		camera-thermal {
 			polling-delay-passive = <0>;
@@ -556,6 +556,47 @@
 	};
 };
 
+&cci0 {
+	status = "okay";
+};
+
+&cci0_i2c0 {
+	/* IMX800 @ 1a */
+
+	eeprom@50 {
+		compatible = "puya,p24c256c", "atmel,24c256";
+		reg = <0x50>;
+		vcc-supply = <&vreg_l6p>;
+		read-only;
+	};
+};
+
+&cci0_i2c1 {
+	/* IMX858 @ 29 */
+
+	eeprom@54 {
+		compatible = "giantec,gt24p128f", "atmel,24c128";
+		reg = <0x54>;
+		vcc-supply = <&vreg_l6p>;
+		read-only;
+	};
+};
+
+&cci1 {
+	status = "okay";
+};
+
+&cci1_i2c1 {
+	/* S5KJN1SQ03 @ 10 */
+
+	eeprom@51 {
+		compatible = "giantec,gt24p128f", "atmel,24c128";
+		reg = <0x51>;
+		vcc-supply = <&vreg_l6p>;
+		read-only;
+	};
+};
+
 &dispcc {
 	/* Disable for now so simple-framebuffer continues working */
 	status = "disabled";
diff --git a/dts/upstream/src/arm64/qcom/qcm6490-idp.dts b/dts/upstream/src/arm64/qcom/qcm6490-idp.dts
index c5fb153614e..9209efcc49b 100644
--- a/dts/upstream/src/arm64/qcom/qcm6490-idp.dts
+++ b/dts/upstream/src/arm64/qcom/qcm6490-idp.dts
@@ -258,6 +258,8 @@
 			regulator-name = "vreg_l6b_1p2";
 			regulator-min-microvolt = <1140000>;
 			regulator-max-microvolt = <1260000>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM RPMH_REGULATOR_MODE_HPM>;
 			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
 		};
 
@@ -265,6 +267,8 @@
 			regulator-name = "vreg_l7b_2p952";
 			regulator-min-microvolt = <2400000>;
 			regulator-max-microvolt = <3544000>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM RPMH_REGULATOR_MODE_HPM>;
 			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
 		};
 
@@ -279,6 +283,8 @@
 			regulator-name = "vreg_l9b_1p2";
 			regulator-min-microvolt = <1200000>;
 			regulator-max-microvolt = <1304000>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM RPMH_REGULATOR_MODE_HPM>;
 			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
 		};
 
@@ -467,6 +473,8 @@
 			regulator-name = "vreg_l10c_0p88";
 			regulator-min-microvolt = <720000>;
 			regulator-max-microvolt = <1050000>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM RPMH_REGULATOR_MODE_HPM>;
 			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
 		};
 
diff --git a/dts/upstream/src/arm64/qcom/qcm6490-shift-otter.dts b/dts/upstream/src/arm64/qcom/qcm6490-shift-otter.dts
index 4667e47a74b..75930f95769 100644
--- a/dts/upstream/src/arm64/qcom/qcm6490-shift-otter.dts
+++ b/dts/upstream/src/arm64/qcom/qcm6490-shift-otter.dts
@@ -942,8 +942,6 @@
 
 	qcom,squelch-detector-bp = <(-2090)>;
 
-	orientation-switch;
-
 	status = "okay";
 };
 
diff --git a/dts/upstream/src/arm64/qcom/qcs404.dtsi b/dts/upstream/src/arm64/qcom/qcs404.dtsi
index 215ba146207..5a9df6b1230 100644
--- a/dts/upstream/src/arm64/qcom/qcs404.dtsi
+++ b/dts/upstream/src/arm64/qcom/qcs404.dtsi
@@ -28,7 +28,7 @@
 		sleep_clk: sleep-clk {
 			compatible = "fixed-clock";
 			#clock-cells = <0>;
-			clock-frequency = <32768>;
+			clock-frequency = <32764>;
 		};
 	};
 
@@ -694,6 +694,8 @@
 				snps,has-lpm-erratum;
 				snps,hird-threshold = /bits/ 8 <0x10>;
 				snps,usb3_lpm_capable;
+				snps,dis-u1-entry-quirk;
+				snps,dis-u2-entry-quirk;
 				dr_mode = "otg";
 			};
 		};
@@ -731,6 +733,8 @@
 				snps,has-lpm-erratum;
 				snps,hird-threshold = /bits/ 8 <0x10>;
 				snps,usb3_lpm_capable;
+				snps,dis-u1-entry-quirk;
+				snps,dis-u2-entry-quirk;
 				dr_mode = "peripheral";
 			};
 		};
diff --git a/dts/upstream/src/arm64/qcom/qcs615-ride.dts b/dts/upstream/src/arm64/qcom/qcs615-ride.dts
new file mode 100644
index 00000000000..2b5aa3c6686
--- /dev/null
+++ b/dts/upstream/src/arm64/qcom/qcs615-ride.dts
@@ -0,0 +1,343 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
+#include <dt-bindings/gpio/gpio.h>
+#include "qcs615.dtsi"
+#include "pm8150.dtsi"
+/ {
+	model = "Qualcomm Technologies, Inc. QCS615 Ride";
+	compatible = "qcom,qcs615-ride", "qcom,qcs615";
+	chassis-type = "embedded";
+
+	aliases {
+		mmc0 = &sdhc_1;
+		mmc1 = &sdhc_2;
+		serial0 = &uart0;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	clocks {
+		sleep_clk: sleep-clk {
+			compatible = "fixed-clock";
+			clock-frequency = <32000>;
+			#clock-cells = <0>;
+		};
+
+		xo_board_clk: xo-board-clk {
+			compatible = "fixed-clock";
+			clock-frequency = <38400000>;
+			#clock-cells = <0>;
+		};
+	};
+
+	regulator-usb2-vbus {
+		compatible = "regulator-fixed";
+		regulator-name = "USB2_VBUS";
+		gpio = <&pm8150_gpios 10 GPIO_ACTIVE_HIGH>;
+		pinctrl-0 = <&usb2_en>;
+		pinctrl-names = "default";
+		enable-active-high;
+		regulator-always-on;
+	};
+};
+
+&apps_rsc {
+	regulators-0 {
+		compatible = "qcom,pm8150-rpmh-regulators";
+		qcom,pmic-id = "a";
+
+		vreg_s3a: smps3 {
+			regulator-name = "vreg_s3a";
+			regulator-min-microvolt = <600000>;
+			regulator-max-microvolt = <650000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_s4a: smps4 {
+			regulator-name = "vreg_s4a";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1829000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_s5a: smps5 {
+			regulator-name = "vreg_s5a";
+			regulator-min-microvolt = <1896000>;
+			regulator-max-microvolt = <2040000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_s6a: smps6 {
+			regulator-name = "vreg_s6a";
+			regulator-min-microvolt = <1304000>;
+			regulator-max-microvolt = <1404000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l1a: ldo1 {
+			regulator-name = "vreg_l1a";
+			regulator-min-microvolt = <488000>;
+			regulator-max-microvolt = <852000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l2a: ldo2 {
+			regulator-name = "vreg_l2a";
+			regulator-min-microvolt = <1650000>;
+			regulator-max-microvolt = <3100000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l3a: ldo3 {
+			regulator-name = "vreg_l3a";
+			regulator-min-microvolt = <1000000>;
+			regulator-max-microvolt = <1248000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l5a: ldo5 {
+			regulator-name = "vreg_l5a";
+			regulator-min-microvolt = <875000>;
+			regulator-max-microvolt = <975000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l7a: ldo7 {
+			regulator-name = "vreg_l7a";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1900000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l8a: ldo8 {
+			regulator-name = "vreg_l8a";
+			regulator-min-microvolt = <1150000>;
+			regulator-max-microvolt = <1350000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l10a: ldo10 {
+			regulator-name = "vreg_l10a";
+			regulator-min-microvolt = <2950000>;
+			regulator-max-microvolt = <3312000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l11a: ldo11 {
+			regulator-name = "vreg_l11a";
+			regulator-min-microvolt = <1232000>;
+			regulator-max-microvolt = <1260000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l12a: ldo12 {
+			regulator-name = "vreg_l12a";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1890000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l13a: ldo13 {
+			regulator-name = "vreg_l13a";
+			regulator-min-microvolt = <3000000>;
+			regulator-max-microvolt = <3230000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l15a: ldo15 {
+			regulator-name = "vreg_l15a";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1904000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l16a: ldo16 {
+			regulator-name = "vreg_l16a";
+			regulator-min-microvolt = <3000000>;
+			regulator-max-microvolt = <3312000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l17a: ldo17 {
+			regulator-name = "vreg_l17a";
+			regulator-min-microvolt = <2950000>;
+			regulator-max-microvolt = <3312000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+	};
+};
+
+&gcc {
+	clocks = <&rpmhcc RPMH_CXO_CLK>,
+		 <&rpmhcc RPMH_CXO_CLK_A>,
+		 <&sleep_clk>;
+};
+
+&pm8150_gpios {
+	usb2_en: usb2-en-state {
+		pins = "gpio10";
+		function = "normal";
+		output-enable;
+		power-source = <0>;
+	};
+};
+
+&pon_pwrkey {
+	status = "okay";
+};
+
+&pon_resin {
+	linux,code = <KEY_VOLUMEDOWN>;
+
+	status = "okay";
+};
+
+&qupv3_id_0 {
+	status = "okay";
+};
+
+&rpmhcc {
+	clocks = <&xo_board_clk>;
+};
+
+&sdhc_1 {
+	pinctrl-0 = <&sdc1_state_on>;
+	pinctrl-1 = <&sdc1_state_off>;
+	pinctrl-names = "default", "sleep";
+
+	bus-width = <8>;
+	mmc-ddr-1_8v;
+	mmc-hs200-1_8v;
+	mmc-hs400-1_8v;
+	mmc-hs400-enhanced-strobe;
+	vmmc-supply = <&vreg_l17a>;
+	vqmmc-supply = <&vreg_s4a>;
+
+	non-removable;
+	no-sd;
+	no-sdio;
+
+	status = "okay";
+};
+
+&sdhc_2 {
+	pinctrl-0 = <&sdc2_state_on>;
+	pinctrl-1 = <&sdc2_state_off>;
+	pinctrl-names = "default", "sleep";
+
+	bus-width = <4>;
+	cd-gpios = <&tlmm 99 GPIO_ACTIVE_LOW>;
+
+	vmmc-supply = <&vreg_l10a>;
+	vqmmc-supply = <&vreg_s4a>;
+
+	status = "okay";
+};
+
+&uart0 {
+	status = "okay";
+};
+
+&usb_1_hsphy {
+	vdd-supply = <&vreg_l5a>;
+	vdda-pll-supply = <&vreg_l12a>;
+	vdda-phy-dpdm-supply = <&vreg_l13a>;
+
+	status = "okay";
+};
+
+&usb_qmpphy {
+	vdda-phy-supply = <&vreg_l5a>;
+	vdda-pll-supply = <&vreg_l12a>;
+
+	status = "okay";
+};
+
+&usb_1 {
+	status = "okay";
+};
+
+&usb_1_dwc3 {
+	dr_mode = "peripheral";
+};
+
+&usb_hsphy_2 {
+	vdd-supply = <&vreg_l5a>;
+	vdda-pll-supply = <&vreg_l12a>;
+	vdda-phy-dpdm-supply = <&vreg_l13a>;
+
+	status = "okay";
+};
+
+&usb_2 {
+	status = "okay";
+};
+
+&usb_2_dwc3 {
+	dr_mode = "host";
+};
+
+&ufs_mem_hc {
+	reset-gpios = <&tlmm 123 GPIO_ACTIVE_LOW>;
+	vcc-supply = <&vreg_l17a>;
+	vcc-max-microamp = <600000>;
+	vccq2-supply = <&vreg_s4a>;
+	vccq2-max-microamp = <600000>;
+
+	status = "okay";
+};
+
+&ufs_mem_phy {
+	vdda-phy-supply = <&vreg_l5a>;
+	vdda-pll-supply = <&vreg_l12a>;
+
+	status = "okay";
+};
+
+&watchdog {
+	clocks = <&sleep_clk>;
+};
diff --git a/dts/upstream/src/arm64/qcom/qcs615.dtsi b/dts/upstream/src/arm64/qcom/qcs615.dtsi
new file mode 100644
index 00000000000..f4abfad474e
--- /dev/null
+++ b/dts/upstream/src/arm64/qcom/qcs615.dtsi
@@ -0,0 +1,3670 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#include <dt-bindings/clock/qcom,qcs615-gcc.h>
+#include <dt-bindings/clock/qcom,rpmh.h>
+#include <dt-bindings/dma/qcom-gpi.h>
+#include <dt-bindings/interconnect/qcom,icc.h>
+#include <dt-bindings/interconnect/qcom,qcs615-rpmh.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/power/qcom-rpmpd.h>
+#include <dt-bindings/power/qcom,rpmhpd.h>
+#include <dt-bindings/soc/qcom,rpmh-rsc.h>
+
+/ {
+	interrupt-parent = <&intc>;
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	cpus {
+		#address-cells = <2>;
+		#size-cells = <0>;
+
+		cpu0: cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a55";
+			reg = <0x0 0x0>;
+			enable-method = "psci";
+			power-domains = <&cpu_pd0>;
+			power-domain-names = "psci";
+			capacity-dmips-mhz = <1024>;
+			dynamic-power-coefficient = <100>;
+			next-level-cache = <&l2_0>;
+			#cooling-cells = <2>;
+
+			l2_0: l2-cache {
+			      compatible = "cache";
+			      cache-level = <2>;
+			      cache-unified;
+			      next-level-cache = <&l3_0>;
+			};
+		};
+
+		cpu1: cpu@100 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a55";
+			reg = <0x0 0x100>;
+			enable-method = "psci";
+			power-domains = <&cpu_pd1>;
+			power-domain-names = "psci";
+			capacity-dmips-mhz = <1024>;
+			dynamic-power-coefficient = <100>;
+			next-level-cache = <&l2_100>;
+
+			l2_100: l2-cache {
+			      compatible = "cache";
+			      cache-level = <2>;
+			      cache-unified;
+			      next-level-cache = <&l3_0>;
+			};
+		};
+
+		cpu2: cpu@200 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a55";
+			reg = <0x0 0x200>;
+			enable-method = "psci";
+			power-domains = <&cpu_pd2>;
+			power-domain-names = "psci";
+			capacity-dmips-mhz = <1024>;
+			dynamic-power-coefficient = <100>;
+			next-level-cache = <&l2_200>;
+
+			l2_200: l2-cache {
+			      compatible = "cache";
+			      cache-level = <2>;
+			      cache-unified;
+			      next-level-cache = <&l3_0>;
+			};
+		};
+
+		cpu3: cpu@300 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a55";
+			reg = <0x0 0x300>;
+			enable-method = "psci";
+			power-domains = <&cpu_pd3>;
+			power-domain-names = "psci";
+			capacity-dmips-mhz = <1024>;
+			dynamic-power-coefficient = <100>;
+			next-level-cache = <&l2_300>;
+
+			l2_300: l2-cache {
+			      compatible = "cache";
+			      cache-level = <2>;
+			      cache-unified;
+			      next-level-cache = <&l3_0>;
+			};
+		};
+
+		cpu4: cpu@400 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a55";
+			reg = <0x0 0x400>;
+			enable-method = "psci";
+			power-domains = <&cpu_pd4>;
+			power-domain-names = "psci";
+			capacity-dmips-mhz = <1024>;
+			dynamic-power-coefficient = <100>;
+			next-level-cache = <&l2_400>;
+
+			l2_400: l2-cache {
+			      compatible = "cache";
+			      cache-level = <2>;
+			      cache-unified;
+			      next-level-cache = <&l3_0>;
+			};
+		};
+
+		cpu5: cpu@500 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a55";
+			reg = <0x0 0x500>;
+			enable-method = "psci";
+			power-domains = <&cpu_pd5>;
+			power-domain-names = "psci";
+			capacity-dmips-mhz = <1024>;
+			dynamic-power-coefficient = <100>;
+			next-level-cache = <&l2_500>;
+
+			l2_500: l2-cache {
+			      compatible = "cache";
+			      cache-level = <2>;
+			      cache-unified;
+			      next-level-cache = <&l3_0>;
+			};
+		};
+
+		cpu6: cpu@600 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a76";
+			reg = <0x0 0x600>;
+			enable-method = "psci";
+			power-domains = <&cpu_pd6>;
+			power-domain-names = "psci";
+			capacity-dmips-mhz = <1740>;
+			dynamic-power-coefficient = <404>;
+			next-level-cache = <&l2_600>;
+			#cooling-cells = <2>;
+
+			l2_600: l2-cache {
+			      compatible = "cache";
+			      cache-level = <2>;
+			      cache-unified;
+			      next-level-cache = <&l3_0>;
+			};
+		};
+
+		cpu7: cpu@700 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a76";
+			reg = <0x0 0x700>;
+			enable-method = "psci";
+			power-domains = <&cpu_pd7>;
+			power-domain-names = "psci";
+			capacity-dmips-mhz = <1740>;
+			dynamic-power-coefficient = <404>;
+			next-level-cache = <&l2_700>;
+
+			l2_700: l2-cache {
+			      compatible = "cache";
+			      cache-level = <2>;
+			      cache-unified;
+			      next-level-cache = <&l3_0>;
+			};
+		};
+
+		cpu-map {
+			cluster0 {
+				core0 {
+					cpu = <&cpu0>;
+				};
+
+				core1 {
+					cpu = <&cpu1>;
+				};
+
+				core2 {
+					cpu = <&cpu2>;
+				};
+
+				core3 {
+					cpu = <&cpu3>;
+				};
+
+				core4 {
+					cpu = <&cpu4>;
+				};
+
+				core5 {
+					cpu = <&cpu5>;
+				};
+
+				core6 {
+					cpu = <&cpu6>;
+				};
+
+				core7 {
+					cpu = <&cpu7>;
+				};
+			};
+		};
+
+		l3_0: l3-cache {
+			compatible = "cache";
+			cache-level = <3>;
+			cache-unified;
+		};
+	};
+
+	dummy_eud: dummy-sink {
+		compatible = "arm,coresight-dummy-sink";
+
+		in-ports {
+			port {
+				eud_in: endpoint {
+					remote-endpoint = <&replicator_swao_out1>;
+				};
+			};
+		};
+	};
+
+	idle-states {
+		entry-method = "psci";
+
+		little_cpu_sleep_0: cpu-sleep-0-0 {
+			compatible = "arm,idle-state";
+			idle-state-name = "silver-power-collapse";
+			arm,psci-suspend-param = <0x40000003>;
+			entry-latency-us = <549>;
+			exit-latency-us = <901>;
+			min-residency-us = <1774>;
+			local-timer-stop;
+		};
+
+		little_cpu_sleep_1: cpu-sleep-0-1 {
+			compatible = "arm,idle-state";
+			idle-state-name = "silver-rail-power-collapse";
+			arm,psci-suspend-param = <0x40000004>;
+			entry-latency-us = <702>;
+			exit-latency-us = <915>;
+			min-residency-us = <4001>;
+			local-timer-stop;
+		};
+
+		big_cpu_sleep_0: cpu-sleep-1-0 {
+			compatible = "arm,idle-state";
+			idle-state-name = "gold-power-collapse";
+			arm,psci-suspend-param = <0x40000003>;
+			entry-latency-us = <523>;
+			exit-latency-us = <1244>;
+			min-residency-us = <2207>;
+			local-timer-stop;
+		};
+
+		big_cpu_sleep_1: cpu-sleep-1-1 {
+			compatible = "arm,idle-state";
+			idle-state-name = "gold-rail-power-collapse";
+			arm,psci-suspend-param = <0x40000004>;
+			entry-latency-us = <526>;
+			exit-latency-us = <1854>;
+			min-residency-us = <5555>;
+			local-timer-stop;
+		};
+	};
+
+	domain-idle-states {
+		cluster_sleep_0: cluster-sleep-0 {
+			compatible = "domain-idle-state";
+			arm,psci-suspend-param = <0x41000044>;
+			entry-latency-us = <2752>;
+			exit-latency-us = <3048>;
+			min-residency-us = <6118>;
+		};
+
+		cluster_sleep_1: cluster-sleep-1 {
+			compatible = "domain-idle-state";
+			arm,psci-suspend-param = <0x41001344>;
+			entry-latency-us = <3263>;
+			exit-latency-us = <4562>;
+			min-residency-us = <8467>;
+		};
+
+		cluster_sleep_2: cluster-sleep-2 {
+			compatible = "domain-idle-state";
+			arm,psci-suspend-param = <0x4100b344>;
+			entry-latency-us = <3638>;
+			exit-latency-us = <6562>;
+			min-residency-us = <9826>;
+		};
+	};
+
+	memory@80000000 {
+		device_type = "memory";
+		/* We expect the bootloader to fill in the size */
+		reg = <0 0x80000000 0 0>;
+	};
+
+	firmware {
+		scm {
+			compatible = "qcom,scm-qcs615", "qcom,scm";
+			qcom,dload-mode = <&tcsr 0x13000>;
+		};
+	};
+
+	camnoc_virt: interconnect-0 {
+		compatible = "qcom,qcs615-camnoc-virt";
+		#interconnect-cells = <2>;
+		qcom,bcm-voters = <&apps_bcm_voter>;
+	};
+
+	ipa_virt: interconnect-1 {
+		compatible = "qcom,qcs615-ipa-virt";
+		#interconnect-cells = <2>;
+		qcom,bcm-voters = <&apps_bcm_voter>;
+	};
+
+	mc_virt: interconnect-2 {
+		compatible = "qcom,qcs615-mc-virt";
+		#interconnect-cells = <2>;
+		qcom,bcm-voters = <&apps_bcm_voter>;
+	};
+
+	qup_opp_table: opp-table-qup {
+		compatible = "operating-points-v2";
+		opp-shared;
+
+		opp-75000000 {
+			opp-hz = /bits/ 64 <75000000>;
+			required-opps = <&rpmhpd_opp_low_svs>;
+		};
+
+		opp-100000000 {
+			opp-hz = /bits/ 64 <100000000>;
+			required-opps = <&rpmhpd_opp_svs>;
+		};
+
+		opp-128000000 {
+			opp-hz = /bits/ 64 <128000000>;
+			required-opps = <&rpmhpd_opp_nom>;
+		};
+	};
+
+	psci {
+		compatible = "arm,psci-1.0";
+		method = "smc";
+
+		cpu_pd0: power-domain-cpu0 {
+			#power-domain-cells = <0>;
+			power-domains = <&cluster_pd>;
+			domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>;
+		};
+
+		cpu_pd1: power-domain-cpu1 {
+			#power-domain-cells = <0>;
+			power-domains = <&cluster_pd>;
+			domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>;
+		};
+
+		cpu_pd2: power-domain-cpu2 {
+			#power-domain-cells = <0>;
+			power-domains = <&cluster_pd>;
+			domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>;
+		};
+
+		cpu_pd3: power-domain-cpu3 {
+			#power-domain-cells = <0>;
+			power-domains = <&cluster_pd>;
+			domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>;
+		};
+
+		cpu_pd4: power-domain-cpu4 {
+			#power-domain-cells = <0>;
+			power-domains = <&cluster_pd>;
+			domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>;
+		};
+
+		cpu_pd5: power-domain-cpu5 {
+			#power-domain-cells = <0>;
+			power-domains = <&cluster_pd>;
+			domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>;
+		};
+
+		cpu_pd6: power-domain-cpu6 {
+			#power-domain-cells = <0>;
+			power-domains = <&cluster_pd>;
+			domain-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>;
+		};
+
+		cpu_pd7: power-domain-cpu7 {
+			#power-domain-cells = <0>;
+			power-domains = <&cluster_pd>;
+			domain-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>;
+		};
+
+		cluster_pd: power-domain-cluster {
+			#power-domain-cells = <0>;
+			domain-idle-states = <&cluster_sleep_0
+					      &cluster_sleep_1
+					      &cluster_sleep_2>;
+		};
+	};
+
+	reserved-memory {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		smem_region: smem@86000000 {
+			compatible = "qcom,smem";
+			reg = <0x0 0x86000000 0x0 0x200000>;
+			no-map;
+			hwlocks = <&tcsr_mutex 3>;
+		};
+	};
+
+	soc: soc@0 {
+		compatible = "simple-bus";
+		ranges = <0 0 0 0 0x10 0>;
+		dma-ranges = <0 0 0 0 0x10 0>;
+		#address-cells = <2>;
+		#size-cells = <2>;
+
+		gcc: clock-controller@100000 {
+			compatible = "qcom,qcs615-gcc";
+			reg = <0 0x00100000 0 0x1f0000>;
+
+			#clock-cells = <1>;
+			#reset-cells = <1>;
+			#power-domain-cells = <1>;
+		};
+
+		qfprom: efuse@780000 {
+			compatible = "qcom,qcs615-qfprom", "qcom,qfprom";
+			reg = <0x0 0x00780000 0x0 0x7000>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			qusb2_hstx_trim: hstx-trim@1f8 {
+				reg = <0x1fb 0x1>;
+				bits = <1 4>;
+			};
+		};
+
+		sdhc_1: mmc@7c4000 {
+			compatible = "qcom,qcs615-sdhci", "qcom,sdhci-msm-v5";
+			reg = <0x0 0x007c4000 0x0 0x1000>,
+			      <0x0 0x007c5000 0x0 0x1000>,
+			      <0x0 0x007c8000 0x0 0x8000>;
+			reg-names = "hc",
+				    "cqhci",
+				    "ice";
+
+			interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "hc_irq",
+					  "pwr_irq";
+
+			clocks = <&gcc GCC_SDCC1_AHB_CLK>,
+				 <&gcc GCC_SDCC1_APPS_CLK>,
+				 <&rpmhcc RPMH_CXO_CLK>,
+				 <&gcc GCC_SDCC1_ICE_CORE_CLK>;
+			clock-names = "iface",
+				      "core",
+				      "xo",
+				      "ice";
+
+			resets = <&gcc GCC_SDCC1_BCR>;
+
+			power-domains = <&rpmhpd RPMHPD_CX>;
+			operating-points-v2 = <&sdhc1_opp_table>;
+			iommus = <&apps_smmu 0x02c0 0x0>;
+			interconnects = <&aggre1_noc MASTER_SDCC_1 QCOM_ICC_TAG_ALWAYS
+					 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
+					<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+					 &config_noc SLAVE_SDCC_1 QCOM_ICC_TAG_ACTIVE_ONLY>;
+			interconnect-names = "sdhc-ddr",
+					     "cpu-sdhc";
+
+			qcom,dll-config = <0x000f642c>;
+			qcom,ddr-config = <0x80040868>;
+			supports-cqe;
+			dma-coherent;
+
+			status = "disabled";
+
+			sdhc1_opp_table: opp-table {
+				compatible = "operating-points-v2";
+
+				opp-50000000 {
+					opp-hz = /bits/ 64 <50000000>;
+					required-opps = <&rpmhpd_opp_low_svs>;
+				};
+
+				opp-100000000 {
+					opp-hz = /bits/ 64 <100000000>;
+					required-opps = <&rpmhpd_opp_svs>;
+				};
+
+				opp-200000000 {
+					opp-hz = /bits/ 64 <200000000>;
+					required-opps = <&rpmhpd_opp_svs_l1>;
+				};
+
+				opp-384000000 {
+					opp-hz = /bits/ 64 <384000000>;
+					required-opps = <&rpmhpd_opp_nom>;
+				};
+			};
+		};
+
+		gpi_dma0: dma-controller@800000  {
+			compatible = "qcom,qcs615-gpi-dma", "qcom,sdm845-gpi-dma";
+			reg = <0x0 0x800000 0x0 0x60000>;
+			#dma-cells = <3>;
+			interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>;
+			dma-channels = <8>;
+			dma-channel-mask = <0xf>;
+			iommus = <&apps_smmu 0xd6 0x0>;
+			status = "disabled";
+		};
+
+		qupv3_id_0: geniqup@8c0000 {
+			compatible = "qcom,geni-se-qup";
+			reg = <0x0 0x008c0000 0x0 0x6000>;
+			ranges;
+			clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
+				 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
+			clock-names = "m-ahb",
+				      "s-ahb";
+			iommus = <&apps_smmu 0xc3 0x0>;
+			#address-cells = <2>;
+			#size-cells = <2>;
+			status = "disabled";
+
+			uart0: serial@880000 {
+				compatible = "qcom,geni-debug-uart";
+				reg = <0x0 0x00880000 0x0 0x4000>;
+				clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
+				clock-names = "se";
+				pinctrl-0 = <&qup_uart0_tx>, <&qup_uart0_rx>;
+				pinctrl-names = "default";
+				interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
+				interconnects = <&aggre1_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
+						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
+						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+						 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>;
+				interconnect-names = "qup-core",
+						     "qup-config";
+				power-domains = <&rpmhpd RPMHPD_CX>;
+				status = "disabled";
+			};
+
+			i2c1: i2c@884000 {
+				compatible = "qcom,geni-i2c";
+				reg = <0x0 0x884000 0x0 0x4000>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
+				clock-names = "se";
+				pinctrl-0 = <&qup_i2c1_data_clk>;
+				pinctrl-names = "default";
+				interconnects = <&aggre1_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
+						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
+						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+						 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
+						<&aggre1_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
+						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+				interconnect-names = "qup-core",
+						     "qup-config",
+						     "qup-memory";
+				power-domains = <&rpmhpd RPMHPD_CX>;
+				dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
+				       <&gpi_dma0 1 1 QCOM_GPI_I2C>;
+				dma-names = "tx",
+					    "rx";
+				status = "disabled";
+			};
+
+			i2c2: i2c@888000 {
+				compatible = "qcom,geni-i2c";
+				reg = <0x0 0x888000 0x0 0x4000>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
+				clock-names = "se";
+				pinctrl-0 = <&qup_i2c2_data_clk>;
+				pinctrl-names = "default";
+				interconnects = <&aggre1_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
+						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
+						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+						 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
+						<&aggre1_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
+						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+				interconnect-names = "qup-core",
+						     "qup-config",
+						     "qup-memory";
+				power-domains = <&rpmhpd RPMHPD_CX>;
+				dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
+				       <&gpi_dma0 1 2 QCOM_GPI_I2C>;
+				dma-names = "tx",
+					    "rx";
+				status = "disabled";
+			};
+
+			spi2: spi@888000 {
+				compatible = "qcom,geni-spi";
+				reg = <0x0 0x00888000 0x0 0x4000>;
+				interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
+				clock-names = "se";
+				pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>;
+				pinctrl-names = "default";
+				interconnects = <&aggre1_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
+						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
+						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+						 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>;
+				interconnect-names = "qup-core",
+						     "qup-config";
+				power-domains = <&rpmhpd RPMHPD_CX>;
+				dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>,
+				       <&gpi_dma0 1 2 QCOM_GPI_SPI>;
+				dma-names = "tx",
+					    "rx";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				status = "disabled";
+			};
+
+			uart2: serial@888000 {
+				compatible = "qcom,geni-uart";
+				reg = <0x0 0x00888000 0x0 0x4000>;
+				interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
+				clock-names = "se";
+				pinctrl-0 = <&qup_uart2_cts>, <&qup_uart2_rts>,
+					    <&qup_uart2_tx>, <&qup_uart2_rx>;
+				pinctrl-names = "default";
+				interconnects = <&aggre1_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
+						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
+						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+						 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>;
+				interconnect-names = "qup-core",
+						     "qup-config";
+				power-domains = <&rpmhpd RPMHPD_CX>;
+				status = "disabled";
+			};
+
+			i2c3: i2c@88c000 {
+				compatible = "qcom,geni-i2c";
+				reg = <0x0 0x88c000 0x0 0x4000>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
+				clock-names = "se";
+				pinctrl-0 = <&qup_i2c3_data_clk>;
+				pinctrl-names = "default";
+				interconnects = <&aggre1_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
+						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
+						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+						 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
+						<&aggre1_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
+						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+				interconnect-names = "qup-core",
+						     "qup-config",
+						     "qup-memory";
+				power-domains = <&rpmhpd RPMHPD_CX>;
+				dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>,
+				       <&gpi_dma0 1 3 QCOM_GPI_I2C>;
+				dma-names = "tx",
+					    "rx";
+				status = "disabled";
+			};
+		};
+
+		gpi_dma1: dma-controller@a00000 {
+			compatible = "qcom,qcs615-gpi-dma", "qcom,sdm845-gpi-dma";
+			reg = <0x0 0xa00000 0x0 0x60000>;
+			#dma-cells = <3>;
+			interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>;
+			dma-channels = <8>;
+			dma-channel-mask = <0xf>;
+			iommus = <&apps_smmu 0x376 0x0>;
+			status = "disabled";
+		};
+
+		qupv3_id_1: geniqup@ac0000 {
+			compatible = "qcom,geni-se-qup";
+			reg = <0x0 0xac0000 0x0 0x2000>;
+			ranges;
+			clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
+				 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
+			clock-names = "m-ahb",
+				      "s-ahb";
+			iommus = <&apps_smmu 0x363 0x0>;
+			#address-cells = <2>;
+			#size-cells = <2>;
+			status = "disabled";
+
+			i2c4: i2c@a80000 {
+				compatible = "qcom,geni-i2c";
+				reg = <0x0 0xa80000 0x0 0x4000>;
+				clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
+				clock-names = "se";
+				pinctrl-0 = <&qup_i2c4_data_clk>;
+				pinctrl-names = "default";
+				interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				interconnects = <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS
+						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
+						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+						 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
+						<&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS
+						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+				interconnect-names = "qup-core",
+						     "qup-config",
+						     "qup-memory";
+				power-domains = <&rpmhpd RPMHPD_CX>;
+				required-opps = <&rpmhpd_opp_low_svs>;
+				dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
+				       <&gpi_dma1 1 0 QCOM_GPI_I2C>;
+				dma-names = "tx",
+					    "rx";
+				status = "disabled";
+			};
+
+			spi4: spi@a80000 {
+				compatible = "qcom,geni-spi";
+				reg = <0x0 0xa80000 0x0 0x4000>;
+				clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
+				clock-names = "se";
+				pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>;
+				pinctrl-names = "default";
+				interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				interconnects = <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS
+						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
+						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+						 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>;
+				interconnect-names = "qup-core",
+						     "qup-config";
+				power-domains = <&rpmhpd RPMHPD_CX>;
+				operating-points-v2 = <&qup_opp_table>;
+				dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>,
+				       <&gpi_dma1 1 0 QCOM_GPI_SPI>;
+				dma-names = "tx",
+					    "rx";
+				status = "disabled";
+			};
+
+			uart4: serial@a80000 {
+				compatible = "qcom,geni-uart";
+				reg = <0x0 0xa80000 0x0 0x4000>;
+				clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
+				clock-names = "se";
+				pinctrl-0 = <&qup_uart4_cts>, <&qup_uart4_rts>,
+					    <&qup_uart4_tx>, <&qup_uart4_rx>;
+				pinctrl-names = "default";
+				interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
+				interconnects = <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS
+						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
+						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+						 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>;
+				interconnect-names = "qup-core",
+						     "qup-config";
+				power-domains = <&rpmhpd RPMHPD_CX>;
+				operating-points-v2 = <&qup_opp_table>;
+				status = "disabled";
+			};
+
+			i2c5: i2c@a84000 {
+				compatible = "qcom,geni-i2c";
+				reg = <0x0 0xa84000 0x0 0x4000>;
+				clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
+				clock-names = "se";
+				pinctrl-0 = <&qup_i2c5_data_clk>;
+				pinctrl-names = "default";
+				interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				interconnects = <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS
+						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
+						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+						 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
+						<&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS
+						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+				interconnect-names = "qup-core",
+						     "qup-config",
+						     "qup-memory";
+				power-domains = <&rpmhpd RPMHPD_CX>;
+				required-opps = <&rpmhpd_opp_low_svs>;
+				dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
+				       <&gpi_dma1 1 1 QCOM_GPI_I2C>;
+				dma-names = "tx",
+					    "rx";
+				status = "disabled";
+			};
+
+			i2c6: i2c@a88000 {
+				compatible = "qcom,geni-i2c";
+				reg = <0x0 0xa88000 0x0 0x4000>;
+				clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
+				clock-names = "se";
+				pinctrl-0 = <&qup_i2c6_data_clk>;
+				pinctrl-names = "default";
+				interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				interconnects = <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS
+						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
+						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+						 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
+						<&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS
+						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+				interconnect-names = "qup-core",
+						     "qup-config",
+						     "qup-memory";
+				power-domains = <&rpmhpd RPMHPD_CX>;
+				required-opps = <&rpmhpd_opp_low_svs>;
+				dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
+				       <&gpi_dma1 1 2 QCOM_GPI_I2C>;
+				dma-names = "tx",
+					    "rx";
+				status = "disabled";
+			};
+
+			spi6: spi@a88000 {
+				compatible = "qcom,geni-spi";
+				reg = <0x0 0xa88000 0x0 0x4000>;
+				clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
+				clock-names = "se";
+				pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>;
+				pinctrl-names = "default";
+				interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				interconnects = <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS
+						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
+						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+						 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>;
+				interconnect-names = "qup-core",
+						     "qup-config";
+				power-domains = <&rpmhpd RPMHPD_CX>;
+				operating-points-v2 = <&qup_opp_table>;
+				dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>,
+				       <&gpi_dma1 1 2 QCOM_GPI_SPI>;
+				dma-names = "tx",
+					    "rx";
+				status = "disabled";
+			};
+
+			uart6: serial@a88000 {
+				compatible = "qcom,geni-uart";
+				reg = <0x0 0xa88000 0x0 0x4000>;
+				clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
+				clock-names = "se";
+				pinctrl-0 = <&qup_uart6_cts>, <&qup_uart6_rts>,
+					    <&qup_uart6_tx>, <&qup_uart6_rx>;
+				pinctrl-names = "default";
+				interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
+				interconnects = <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS
+						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
+						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+						 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>;
+				interconnect-names = "qup-core",
+						     "qup-config";
+				power-domains = <&rpmhpd RPMHPD_CX>;
+				operating-points-v2 = <&qup_opp_table>;
+				status = "disabled";
+			};
+
+			i2c7: i2c@a8c000 {
+				compatible = "qcom,geni-i2c";
+				reg = <0x0 0xa8c000 0x0 0x4000>;
+				clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
+				clock-names = "se";
+				pinctrl-0 = <&qup_i2c7_data_clk>;
+				pinctrl-names = "default";
+				interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				interconnects = <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS
+						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
+						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+						 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
+						<&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS
+						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+				interconnect-names = "qup-core",
+						     "qup-config",
+						     "qup-memory";
+				power-domains = <&rpmhpd RPMHPD_CX>;
+				required-opps = <&rpmhpd_opp_low_svs>;
+				dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
+				       <&gpi_dma1 1 3 QCOM_GPI_I2C>;
+				dma-names = "tx",
+					    "rx";
+				status = "disabled";
+			};
+
+			spi7: spi@a8c000 {
+				compatible = "qcom,geni-spi";
+				reg = <0x0 0xa8c000 0x0 0x4000>;
+				clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
+				clock-names = "se";
+				pinctrl-0 = <&qup_spi7_data_clk>, <&qup_spi7_cs>;
+				pinctrl-names = "default";
+				interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				interconnects = <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS
+						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
+						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+						 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>;
+				interconnect-names = "qup-core",
+						     "qup-config";
+				power-domains = <&rpmhpd RPMHPD_CX>;
+				operating-points-v2 = <&qup_opp_table>;
+				dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>,
+				       <&gpi_dma1 1 3 QCOM_GPI_SPI>;
+				dma-names = "tx",
+					    "rx";
+				status = "disabled";
+			};
+
+			uart7: serial@a8c000 {
+				compatible = "qcom,geni-uart";
+				reg = <0x0 0xa8c000 0x0 0x4000>;
+				clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
+				clock-names = "se";
+				pinctrl-0 = <&qup_uart7_cts>, <&qup_uart7_rts>,
+					    <&qup_uart7_tx>, <&qup_uart7_rx>;
+				pinctrl-names = "default";
+				interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
+				interconnects = <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS
+						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
+						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+						 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>;
+				interconnect-names = "qup-core",
+						     "qup-config";
+				power-domains = <&rpmhpd RPMHPD_CX>;
+				operating-points-v2 = <&qup_opp_table>;
+				status = "disabled";
+			};
+		};
+
+		config_noc: interconnect@1500000 {
+			reg = <0x0 0x01500000 0x0 0x5080>;
+			compatible = "qcom,qcs615-config-noc";
+			#interconnect-cells = <2>;
+			qcom,bcm-voters = <&apps_bcm_voter>;
+		};
+
+		system_noc: interconnect@1620000 {
+			reg = <0x0 0x01620000 0x0 0x1f300>;
+			compatible = "qcom,qcs615-system-noc";
+			#interconnect-cells = <2>;
+			qcom,bcm-voters = <&apps_bcm_voter>;
+		};
+
+		aggre1_noc: interconnect@1700000 {
+			reg = <0x0 0x01700000 0x0 0x3f200>;
+			compatible = "qcom,qcs615-aggre1-noc";
+			#interconnect-cells = <2>;
+			qcom,bcm-voters = <&apps_bcm_voter>;
+		};
+
+		mmss_noc: interconnect@1740000 {
+			reg = <0x0 0x01740000 0x0 0x1c100>;
+			compatible = "qcom,qcs615-mmss-noc";
+			#interconnect-cells = <2>;
+			qcom,bcm-voters = <&apps_bcm_voter>;
+		};
+
+		ufs_mem_hc: ufshc@1d84000 {
+			compatible = "qcom,qcs615-ufshc", "qcom,ufshc", "jedec,ufs-2.0";
+			reg = <0x0 0x01d84000 0x0 0x3000>,
+			      <0x0 0x01d90000 0x0 0x8000>;
+			reg-names = "std",
+				    "ice";
+
+			interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
+
+			clocks = <&gcc GCC_UFS_PHY_AXI_CLK>,
+				 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
+				 <&gcc GCC_UFS_PHY_AHB_CLK>,
+				 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
+				 <&gcc GCC_UFS_PHY_ICE_CORE_CLK>,
+				 <&rpmhcc RPMH_CXO_CLK>,
+				 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
+				 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>;
+			clock-names = "core_clk",
+				      "bus_aggr_clk",
+				      "iface_clk",
+				      "core_clk_unipro",
+				      "core_clk_ice",
+				      "ref_clk",
+				      "tx_lane0_sync_clk",
+				      "rx_lane0_sync_clk";
+
+			resets = <&gcc GCC_UFS_PHY_BCR>;
+			reset-names = "rst";
+
+			operating-points-v2 = <&ufs_opp_table>;
+			interconnects = <&aggre1_noc MASTER_UFS_MEM QCOM_ICC_TAG_ALWAYS
+					 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
+					<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+					 &config_noc SLAVE_UFS_MEM_CFG QCOM_ICC_TAG_ACTIVE_ONLY>;
+			interconnect-names = "ufs-ddr",
+					     "cpu-ufs";
+
+			power-domains = <&gcc UFS_PHY_GDSC>;
+
+			iommus = <&apps_smmu 0x300 0x0>;
+			dma-coherent;
+
+			lanes-per-direction = <1>;
+
+			phys = <&ufs_mem_phy>;
+			phy-names = "ufsphy";
+
+			#reset-cells = <1>;
+
+			status = "disabled";
+
+			ufs_opp_table: opp-table {
+				compatible = "operating-points-v2";
+
+				opp-50000000 {
+					opp-hz = /bits/ 64 <50000000>,
+						 /bits/ 64 <0>,
+						 /bits/ 64 <0>,
+						 /bits/ 64 <37500000>,
+						 /bits/ 64 <75000000>,
+						 /bits/ 64 <0>,
+						 /bits/ 64 <0>,
+						 /bits/ 64 <0>;
+					required-opps = <&rpmhpd_opp_low_svs>;
+				};
+
+				opp-100000000 {
+					opp-hz = /bits/ 64 <100000000>,
+						 /bits/ 64 <0>,
+						 /bits/ 64 <0>,
+						 /bits/ 64 <75000000>,
+						 /bits/ 64 <150000000>,
+						 /bits/ 64 <0>,
+						 /bits/ 64 <0>,
+						 /bits/ 64 <0>;
+					required-opps = <&rpmhpd_opp_svs>;
+				};
+
+				opp-200000000 {
+					opp-hz = /bits/ 64 <200000000>,
+						 /bits/ 64 <0>,
+						 /bits/ 64 <0>,
+						 /bits/ 64 <150000000>,
+						 /bits/ 64 <300000000>,
+						 /bits/ 64 <0>,
+						 /bits/ 64 <0>,
+						 /bits/ 64 <0>;
+					required-opps = <&rpmhpd_opp_nom>;
+				};
+			};
+		};
+
+		ufs_mem_phy: phy@1d87000 {
+			compatible = "qcom,qcs615-qmp-ufs-phy", "qcom,sm6115-qmp-ufs-phy";
+			reg = <0x0 0x01d87000 0x0 0xe00>;
+			clocks = <&rpmhcc RPMH_CXO_CLK>,
+				 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>,
+				 <&gcc GCC_UFS_MEM_CLKREF_CLK>;
+			clock-names = "ref",
+				      "ref_aux",
+				      "qref";
+
+			power-domains = <&gcc UFS_PHY_GDSC>;
+
+			resets = <&ufs_mem_hc 0>;
+			reset-names = "ufsphy";
+
+			#clock-cells = <1>;
+			#phy-cells = <0>;
+
+			status = "disabled";
+		};
+
+		tcsr_mutex: hwlock@1f40000 {
+			compatible = "qcom,tcsr-mutex";
+			reg = <0x0 0x01f40000 0x0 0x20000>;
+			#hwlock-cells = <1>;
+		};
+
+		tcsr: syscon@1fc0000 {
+			compatible = "qcom,qcs615-tcsr", "syscon";
+			reg = <0x0 0x01fc0000 0x0 0x30000>;
+		};
+
+		tlmm: pinctrl@3100000 {
+			compatible = "qcom,qcs615-tlmm";
+			reg = <0x0 0x03100000 0x0 0x300000>,
+			      <0x0 0x03500000 0x0 0x300000>,
+			      <0x0 0x03d00000 0x0 0x300000>;
+			reg-names = "east",
+				    "west",
+				    "south";
+			interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
+			gpio-ranges = <&tlmm 0 0 124>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			wakeup-parent = <&pdc>;
+
+			qup_i2c1_data_clk: qup-i2c1-data-clk-state {
+				pins = "gpio4", "gpio5";
+				function = "qup0";
+
+			};
+
+			qup_i2c2_data_clk: qup-i2c2-data-clk-state {
+				pins = "gpio0", "gpio1";
+				function = "qup0";
+			};
+
+			qup_i2c3_data_clk: qup-i2c3-data-clk-state {
+				pins = "gpio18", "gpio19";
+				function = "qup0";
+			};
+
+			qup_i2c4_data_clk: qup-i2c4-data-clk-state {
+				pins = "gpio20", "gpio21";
+				function = "qup1";
+			};
+
+			qup_i2c5_data_clk: qup-i2c5-data-clk-state {
+				pins = "gpio14", "gpio15";
+				function = "qup1";
+			};
+
+			qup_i2c6_data_clk: qup-i2c6-data-clk-state {
+				pins = "gpio6", "gpio7";
+				function = "qup1";
+			};
+
+			qup_i2c7_data_clk: qup-i2c7-data-clk-state {
+				pins = "gpio10", "gpio11";
+				function = "qup1";
+			};
+
+			qup_spi2_data_clk: qup-spi2-data-clk-state {
+				pins = "gpio0", "gpio1", "gpio2";
+				function = "qup0";
+			};
+
+			qup_spi2_cs: qup-spi2-cs-state {
+				pins = "gpio3";
+				function = "qup0";
+			};
+
+			qup_spi2_cs_gpio: qup-spi2-cs-gpio-state {
+				pins = "gpio3";
+				function = "gpio";
+			};
+
+			qup_spi4_data_clk: qup-spi4-data-clk-state {
+				pins = "gpio20", "gpio21", "gpio22";
+				function = "qup1";
+			};
+
+			qup_spi4_cs: qup-spi4-cs-state {
+				pins = "gpio23";
+				function = "qup1";
+			};
+
+			qup_spi4_cs_gpio: qup-spi4-cs-gpio-state {
+				pins = "gpio23";
+				function = "gpio";
+			};
+
+			qup_spi6_data_clk: qup-spi6-data-clk-state {
+				pins = "gpio6", "gpio7", "gpio8";
+				function = "qup1";
+			};
+
+			qup_spi6_cs: qup-spi6-cs-state {
+				pins = "gpio9";
+				function = "qup1";
+			};
+
+			qup_spi6_cs_gpio: qup-spi6-cs-gpio-state {
+				pins = "gpio9";
+				function = "gpio";
+			};
+
+			qup_spi7_data_clk: qup-spi7-data-clk-state {
+				pins = "gpio10", "gpio11", "gpio12";
+				function = "qup1";
+			};
+
+			qup_spi7_cs: qup-spi7-cs-state {
+				pins = "gpio13";
+				function = "qup1";
+			};
+
+			qup_spi7_cs_gpio: qup-spi7-cs-gpio-state {
+				pins = "gpio13";
+				function = "gpio";
+			};
+
+			qup_uart0_tx: qup-uart0-tx-state {
+				pins = "gpio16";
+				function = "qup0";
+			};
+
+			qup_uart0_rx: qup-uart0-rx-state {
+				pins = "gpio17";
+				function = "qup0";
+			};
+
+			qup_uart2_cts: qup-uart2-cts-state {
+				pins = "gpio0";
+				function = "qup0";
+			};
+
+			qup_uart2_rts: qup-uart2-rts-state {
+				pins = "gpio1";
+				function = "qup0";
+			};
+
+			qup_uart2_tx: qup-uart2-tx-state {
+				pins = "gpio2";
+				function = "qup0";
+			};
+
+			qup_uart2_rx: qup-uart2-rx-state {
+				pins = "gpio3";
+				function = "qup0";
+			};
+
+			qup_uart4_cts: qup-uart4-cts-state {
+				pins = "gpio20";
+				function = "qup1";
+			};
+
+			qup_uart4_rts: qup-uart4-rts-state {
+				pins = "gpio21";
+				function = "qup1";
+			};
+
+			qup_uart4_tx: qup-uart4-tx-state {
+				pins = "gpio22";
+				function = "qup1";
+			};
+
+			qup_uart4_rx: qup-uart4-rx-state {
+				pins = "gpio23";
+				function = "qup1";
+			};
+
+			qup_uart6_cts: qup-uart6-cts-state {
+				pins = "gpio6";
+				function = "qup1";
+			};
+
+			qup_uart6_rts: qup-uart6-rts-state {
+				pins = "gpio7";
+				function = "qup1";
+			};
+
+			qup_uart6_tx: qup-uart6-tx-state {
+				pins = "gpio8";
+				function = "qup1";
+			};
+
+			qup_uart6_rx: qup-uart6-rx-state {
+				pins = "gpio9";
+				function = "qup1";
+			};
+
+			qup_uart7_cts: qup-uart7-cts-state {
+				pins = "gpio10";
+				function = "qup1";
+			};
+
+			qup_uart7_rts: qup-uart7-rts-state {
+				pins = "gpio11";
+				function = "qup1";
+			};
+
+			qup_uart7_tx: qup-uart7-tx-state {
+				pins = "gpio12";
+				function = "qup1";
+			};
+
+			qup_uart7_rx: qup-uart7-rx-state {
+				pins = "gpio13";
+				function = "qup1";
+			};
+
+			sdc1_state_on: sdc1-on-state {
+				clk-pins {
+					pins = "sdc1_clk";
+					bias-disable;
+					drive-strength = <16>;
+				};
+
+				cmd-pins {
+					pins = "sdc1_cmd";
+					bias-pull-up;
+					drive-strength = <10>;
+				};
+
+				data-pins {
+					pins = "sdc1_data";
+					bias-pull-up;
+					drive-strength = <10>;
+				};
+
+				rclk-pins {
+					pins = "sdc1_rclk";
+					bias-pull-down;
+				};
+			};
+
+			sdc1_state_off: sdc1-off-state {
+				clk-pins {
+					pins = "sdc1_clk";
+					bias-disable;
+					drive-strength = <2>;
+				};
+
+				cmd-pins {
+					pins = "sdc1_cmd";
+					bias-pull-up;
+					drive-strength = <2>;
+				};
+
+				data-pins {
+					pins = "sdc1_data";
+					bias-pull-up;
+					drive-strength = <2>;
+				};
+
+				rclk-pins {
+					pins = "sdc1_rclk";
+					bias-pull-down;
+				};
+			};
+
+			sdc2_state_on: sdc2-on-state {
+				clk-pins {
+					pins = "sdc2_clk";
+					bias-disable;
+					drive-strength = <16>;
+				};
+
+				cmd-pins {
+					pins = "sdc2_cmd";
+					bias-pull-up;
+					drive-strength = <10>;
+				};
+
+				data-pins {
+					pins = "sdc2_data";
+					bias-pull-up;
+					drive-strength = <10>;
+				};
+			};
+
+			sdc2_state_off: sdc2-off-state {
+				clk-pins {
+					pins = "sdc2_clk";
+					bias-disable;
+					drive-strength = <2>;
+				};
+
+				cmd-pins {
+					pins = "sdc2_cmd";
+					bias-pull-up;
+					drive-strength = <2>;
+				};
+
+				data-pins {
+					pins = "sdc2_data";
+					bias-pull-up;
+					drive-strength = <2>;
+				};
+			};
+		};
+
+		stm@6002000 {
+			compatible = "arm,coresight-stm", "arm,primecell";
+			reg = <0x0 0x06002000 0x0 0x1000>,
+			      <0x0 0x16280000 0x0 0x180000>;
+			reg-names = "stm-base",
+				    "stm-stimulus-base";
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			out-ports {
+				port {
+					stm_out: endpoint {
+						remote-endpoint = <&funnel_in0_in7>;
+					};
+				};
+			};
+		};
+
+		tpda@6004000 {
+			compatible = "qcom,coresight-tpda", "arm,primecell";
+			reg = <0x0 0x06004000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			in-ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					reg = <0>;
+
+					tpda_qdss_in0: endpoint {
+						remote-endpoint = <&tpdm_center_out>;
+					};
+				};
+
+				port@4 {
+					reg = <4>;
+
+					tpda_qdss_in4: endpoint {
+						remote-endpoint = <&funnel_monaq_out>;
+					};
+				};
+
+				port@5 {
+					reg = <5>;
+
+					tpda_qdss_in5: endpoint {
+						remote-endpoint = <&funnel_ddr_0_out>;
+					};
+				};
+
+				port@6 {
+					reg = <6>;
+
+					tpda_qdss_in6: endpoint {
+						remote-endpoint = <&funnel_turing_out>;
+					};
+				};
+
+				port@7 {
+					reg = <7>;
+
+					tpda_qdss_in7: endpoint {
+						remote-endpoint = <&tpdm_vsense_out>;
+					};
+				};
+
+				port@8 {
+					reg = <8>;
+
+					tpda_qdss_in8: endpoint {
+						remote-endpoint = <&tpdm_dcc_out>;
+					};
+				};
+
+				port@9 {
+					reg = <9>;
+
+					tpda_qdss_in9: endpoint {
+						remote-endpoint = <&tpdm_prng_out>;
+					};
+				};
+
+				port@b {
+					reg = <11>;
+
+					tpda_qdss_in11: endpoint {
+						remote-endpoint = <&tpdm_qm_out>;
+					};
+				};
+
+				port@c {
+					reg = <12>;
+
+					tpda_qdss_in12: endpoint {
+						remote-endpoint = <&tpdm_west_out>;
+					};
+				};
+
+				port@d {
+					reg = <13>;
+
+					tpda_qdss_in13: endpoint {
+						remote-endpoint = <&tpdm_pimem_out>;
+					};
+				};
+			};
+
+			out-ports {
+				port {
+					tpda_qdss_out: endpoint {
+						remote-endpoint = <&funnel_qatb_in>;
+					};
+				};
+			};
+		};
+
+		funnel@6005000 {
+			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+			reg = <0x0 0x06005000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			in-ports {
+				port {
+					funnel_qatb_in: endpoint {
+						remote-endpoint = <&tpda_qdss_out>;
+					};
+				};
+			};
+
+			out-ports {
+				port {
+					funnel_qatb_out: endpoint {
+						remote-endpoint = <&funnel_in0_in6>;
+					};
+				};
+			};
+		};
+
+		cti@6010000 {
+			compatible = "arm,coresight-cti", "arm,primecell";
+			reg = <0x0 0x06010000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+		};
+
+		cti@6011000 {
+			compatible = "arm,coresight-cti", "arm,primecell";
+			reg = <0x0 0x06011000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+		};
+
+		cti@6012000 {
+			compatible = "arm,coresight-cti", "arm,primecell";
+			reg = <0x0 0x06012000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+		};
+
+		cti@6013000 {
+			compatible = "arm,coresight-cti", "arm,primecell";
+			reg = <0x0 0x06013000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+		};
+
+		cti@6014000 {
+			compatible = "arm,coresight-cti", "arm,primecell";
+			reg = <0x0 0x06014000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+		};
+
+		cti@6015000 {
+			compatible = "arm,coresight-cti", "arm,primecell";
+			reg = <0x0 0x06015000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+		};
+
+		cti@6016000 {
+			compatible = "arm,coresight-cti", "arm,primecell";
+			reg = <0x0 0x06016000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+		};
+
+		cti@6017000 {
+			compatible = "arm,coresight-cti", "arm,primecell";
+			reg = <0x0 0x06017000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+		};
+
+		cti@6018000 {
+			compatible = "arm,coresight-cti", "arm,primecell";
+			reg = <0x0 0x06018000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+		};
+
+		cti@6019000 {
+			compatible = "arm,coresight-cti", "arm,primecell";
+			reg = <0x0 0x06019000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+		};
+
+		cti@601a000 {
+			compatible = "arm,coresight-cti", "arm,primecell";
+			reg = <0x0 0x0601a000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+		};
+
+		cti@601b000 {
+			compatible = "arm,coresight-cti", "arm,primecell";
+			reg = <0x0 0x0601b000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+		};
+
+		cti@601c000 {
+			compatible = "arm,coresight-cti", "arm,primecell";
+			reg = <0x0 0x0601c000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+		};
+
+		cti@601d000 {
+			compatible = "arm,coresight-cti", "arm,primecell";
+			reg = <0x0 0x0601d000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+		};
+
+		cti@601e000 {
+			compatible = "arm,coresight-cti", "arm,primecell";
+			reg = <0x0 0x0601e000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+		};
+
+		cti@601f000 {
+			compatible = "arm,coresight-cti", "arm,primecell";
+			reg = <0x0 0x0601f000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+		};
+
+		funnel@6041000 {
+			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+			reg = <0x0 0x06041000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			in-ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@6 {
+					reg = <6>;
+
+					funnel_in0_in6: endpoint {
+						remote-endpoint = <&funnel_qatb_out>;
+					};
+				};
+
+				port@7 {
+					reg = <7>;
+
+					funnel_in0_in7: endpoint {
+						remote-endpoint = <&stm_out>;
+					};
+				};
+			};
+
+			out-ports {
+				port {
+					funnel_in0_out: endpoint {
+						remote-endpoint = <&funnel_merg_in0>;
+					};
+				};
+			};
+		};
+
+		funnel@6042000 {
+			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+			reg = <0x0 0x06042000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			in-ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@3 {
+					reg = <3>;
+
+					funnel_in1_in3: endpoint {
+						remote-endpoint = <&replicator_swao_out0>;
+					};
+				};
+
+				port@4 {
+					reg = <4>;
+
+					funnel_in1_in4: endpoint {
+						remote-endpoint = <&tpdm_wcss_out>;
+					};
+				};
+
+				port@7 {
+					reg = <7>;
+
+					funnel_in1_in7: endpoint {
+						remote-endpoint = <&funnel_apss_merg_out>;
+					};
+				};
+			};
+
+			out-ports {
+				port {
+					funnel_in1_out: endpoint {
+						remote-endpoint = <&funnel_merg_in1>;
+					};
+				};
+			};
+		};
+
+		funnel@6045000 {
+			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+			reg = <0x0 0x06045000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			in-ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					reg = <0>;
+
+					funnel_merg_in0: endpoint {
+						remote-endpoint = <&funnel_in0_out>;
+					};
+				};
+
+				port@1 {
+					reg = <1>;
+
+					funnel_merg_in1: endpoint {
+						remote-endpoint = <&funnel_in1_out>;
+					};
+				};
+			};
+
+			out-ports {
+				port {
+					funnel_merg_out: endpoint {
+						remote-endpoint = <&tmc_etf_in>;
+					};
+				};
+			};
+		};
+
+		replicator@6046000 {
+			compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
+			reg = <0x0 0x06046000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			in-ports {
+				port {
+					replicator0_in: endpoint {
+						remote-endpoint= <&tmc_etf_out>;
+					};
+				};
+			};
+
+			out-ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@1 {
+					reg = <1>;
+
+					replicator0_out1: endpoint {
+						remote-endpoint= <&replicator1_in>;
+					};
+				};
+			};
+		};
+
+		tmc@6047000 {
+			compatible = "arm,coresight-tmc", "arm,primecell";
+			reg = <0x0 0x06047000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			in-ports {
+				port {
+					tmc_etf_in: endpoint {
+						remote-endpoint = <&funnel_merg_out>;
+					};
+				};
+			};
+
+			out-ports {
+				port {
+					tmc_etf_out: endpoint {
+						remote-endpoint = <&replicator0_in>;
+					};
+				};
+			};
+		};
+
+		replicator@604a000 {
+			compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
+			reg = <0x0 0x0604a000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			in-ports {
+				port {
+					replicator1_in: endpoint {
+						remote-endpoint= <&replicator0_out1>;
+					};
+				};
+			};
+
+			out-ports {
+				port {
+					replicator1_out: endpoint {
+						remote-endpoint= <&funnel_swao_in6>;
+					};
+				};
+			};
+		};
+
+		cti@683b000 {
+			compatible = "arm,coresight-cti", "arm,primecell";
+			reg = <0x0 0x0683b000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+		};
+
+		tpdm@6840000 {
+			compatible = "qcom,coresight-tpdm", "arm,primecell";
+			reg = <0x0 0x06840000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			qcom,cmb-element-bits = <64>;
+			qcom,cmb-msrs-num = <32>;
+			status = "disabled";
+
+			out-ports {
+				port {
+					tpdm_vsense_out: endpoint {
+						remote-endpoint = <&tpda_qdss_in7>;
+					};
+				};
+			};
+		};
+
+		tpdm@684c000 {
+			compatible = "qcom,coresight-tpdm", "arm,primecell";
+			reg = <0x0 0x0684c000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			qcom,cmb-element-bits = <32>;
+			qcom,cmb-msrs-num = <32>;
+
+			out-ports {
+				port {
+					tpdm_prng_out: endpoint {
+						remote-endpoint = <&tpda_qdss_in9>;
+					};
+				};
+			};
+		};
+
+		tpdm@6850000 {
+			compatible = "qcom,coresight-tpdm", "arm,primecell";
+			reg = <0x0 0x06850000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			qcom,cmb-element-bits = <64>;
+			qcom,cmb-msrs-num = <32>;
+			qcom,dsb-element-bits = <32>;
+			qcom,dsb-msrs-num = <32>;
+
+			out-ports {
+				port {
+					tpdm_pimem_out: endpoint {
+						remote-endpoint = <&tpda_qdss_in13>;
+					};
+				};
+			};
+		};
+
+		tpdm@6860000 {
+			compatible = "qcom,coresight-tpdm", "arm,primecell";
+			reg = <0x0 0x06860000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			qcom,dsb-element-bits = <32>;
+			qcom,dsb-msrs-num = <32>;
+
+			out-ports {
+				port {
+					tpdm_turing_out: endpoint {
+						remote-endpoint = <&funnel_turing_in>;
+					};
+				};
+			};
+		};
+
+		funnel@6861000 {
+			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+			reg = <0x0 0x06861000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			in-ports {
+				port {
+					funnel_turing_in: endpoint {
+						remote-endpoint = <&tpdm_turing_out>;
+					};
+				};
+			};
+
+			out-ports {
+				port {
+					funnel_turing_out: endpoint {
+						remote-endpoint = <&tpda_qdss_in6>;
+					};
+				};
+			};
+		};
+
+		cti@6867000 {
+			compatible = "arm,coresight-cti", "arm,primecell";
+			reg = <0x0 0x06867000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+		};
+
+		tpdm@6870000 {
+			compatible = "qcom,coresight-tpdm", "arm,primecell";
+			reg = <0x0 0x06870000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			qcom,cmb-element-bits = <32>;
+			qcom,cmb-msrs-num = <32>;
+			status = "disabled";
+
+			out-ports {
+				port {
+					tpdm_dcc_out: endpoint {
+						remote-endpoint = <&tpda_qdss_in8>;
+					};
+				};
+			};
+		};
+
+		tpdm@699c000 {
+			compatible = "qcom,coresight-tpdm", "arm,primecell";
+			reg = <0x0 0x0699c000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			qcom,cmb-element-bits = <32>;
+			qcom,cmb-msrs-num = <32>;
+			qcom,dsb-element-bits = <32>;
+			qcom,dsb-msrs-num = <32>;
+			status = "disabled";
+
+			out-ports {
+				port {
+					tpdm_wcss_out: endpoint {
+						remote-endpoint = <&funnel_in1_in4>;
+					};
+				};
+			};
+		};
+
+		tpdm@69c0000 {
+			compatible = "qcom,coresight-tpdm", "arm,primecell";
+			reg = <0x0 0x069c0000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			qcom,dsb-element-bits = <32>;
+			qcom,dsb-msrs-num = <32>;
+
+			out-ports {
+				port {
+					tpdm_monaq_out: endpoint {
+						remote-endpoint = <&funnel_monaq_in>;
+					};
+				};
+			};
+		};
+
+		funnel@69c3000 {
+			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+			reg = <0x0 0x069c3000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			in-ports {
+				port {
+					funnel_monaq_in: endpoint {
+						remote-endpoint = <&tpdm_monaq_out>;
+					};
+				};
+			};
+
+			out-ports {
+				port {
+					funnel_monaq_out: endpoint {
+						remote-endpoint = <&tpda_qdss_in4>;
+					};
+				};
+			};
+		};
+
+		tpdm@69d0000 {
+			compatible = "qcom,coresight-tpdm", "arm,primecell";
+			reg = <0x0 0x069d0000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			qcom,dsb-element-bits = <32>;
+			qcom,dsb-msrs-num = <32>;
+			status = "disabled";
+
+			out-ports {
+				port {
+					tpdm_qm_out: endpoint {
+						remote-endpoint = <&tpda_qdss_in11>;
+					};
+				};
+			};
+		};
+
+		tpdm@6a00000 {
+			compatible = "qcom,coresight-tpdm", "arm,primecell";
+			reg = <0x0 0x06a00000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			qcom,dsb-element-bits = <32>;
+			qcom,dsb-msrs-num = <32>;
+			status = "disabled";
+
+			out-ports {
+				port {
+					tpdm_ddr_out: endpoint {
+						remote-endpoint = <&funnel_ddr_0_in>;
+					};
+				};
+			};
+		};
+
+		cti@6a02000 {
+			compatible = "arm,coresight-cti", "arm,primecell";
+			reg = <0x0 0x06a02000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+		};
+
+		cti@6a03000 {
+			compatible = "arm,coresight-cti", "arm,primecell";
+			reg = <0x0 0x06a03000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+		};
+
+		cti@6a10000 {
+			compatible = "arm,coresight-cti", "arm,primecell";
+			reg = <0x0 0x06a10000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+		};
+
+		cti@6a11000 {
+			compatible = "arm,coresight-cti", "arm,primecell";
+			reg = <0x0 0x06a11000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+		};
+
+		funnel@6a05000 {
+			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+			reg = <0x0 0x06a05000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			in-ports {
+				port {
+					funnel_ddr_0_in: endpoint {
+						remote-endpoint = <&tpdm_ddr_out>;
+					};
+				};
+			};
+
+			out-ports {
+				port {
+					funnel_ddr_0_out: endpoint {
+						remote-endpoint = <&tpda_qdss_in5>;
+					};
+				};
+			};
+		};
+
+		tpda@6b01000 {
+			compatible = "qcom,coresight-tpda", "arm,primecell";
+			reg = <0x0 0x06b01000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			in-ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					reg = <0>;
+
+					tpda_swao_in0: endpoint {
+						remote-endpoint = <&tpdm_swao0_out>;
+					};
+				};
+
+				port@1 {
+					reg = <1>;
+
+					tpda_swao_in1: endpoint {
+						remote-endpoint = <&tpdm_swao1_out>;
+					};
+
+				};
+			};
+
+			out-ports {
+				port {
+					tpda_swao_out: endpoint {
+						remote-endpoint = <&funnel_swao_in7>;
+					};
+				};
+			};
+		};
+
+		tpdm@6b02000 {
+			compatible = "qcom,coresight-tpdm", "arm,primecell";
+			reg = <0x0 0x06b02000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			qcom,cmb-element-bits = <64>;
+			qcom,cmb-msrs-num = <32>;
+			status = "disabled";
+
+			out-ports {
+				port {
+					tpdm_swao0_out: endpoint {
+						remote-endpoint = <&tpda_swao_in0>;
+					};
+				};
+			};
+		};
+
+		tpdm@6b03000 {
+			compatible = "qcom,coresight-tpdm", "arm,primecell";
+			reg = <0x0 0x06b03000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			qcom,dsb-element-bits = <32>;
+			qcom,dsb-msrs-num = <32>;
+			status = "disabled";
+
+			out-ports {
+				port {
+					tpdm_swao1_out: endpoint {
+						remote-endpoint = <&tpda_swao_in1>;
+					};
+				};
+			};
+		};
+
+		cti@6b04000 {
+			compatible = "arm,coresight-cti", "arm,primecell";
+			reg = <0x0 0x06b04000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+		};
+
+		cti@6b05000 {
+			compatible = "arm,coresight-cti", "arm,primecell";
+			reg = <0x0 0x06b05000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+		};
+
+		cti@6b06000 {
+			compatible = "arm,coresight-cti", "arm,primecell";
+			reg = <0x0 0x06b06000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+		};
+
+		cti@6b07000 {
+			compatible = "arm,coresight-cti", "arm,primecell";
+			reg = <0x0 0x06b07000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+		};
+
+		funnel@6b08000 {
+			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+			reg = <0x0 0x06b08000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			in-ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@6 {
+					reg = <6>;
+
+					funnel_swao_in6: endpoint {
+						remote-endpoint= <&replicator1_out>;
+					};
+				};
+
+				port@7 {
+					reg = <7>;
+
+					funnel_swao_in7: endpoint {
+						remote-endpoint= <&tpda_swao_out>;
+					};
+				};
+			};
+
+			out-ports {
+				port {
+					funnel_swao_out: endpoint {
+						remote-endpoint = <&tmc_etf_swao_in>;
+					};
+				};
+			};
+		};
+
+		tmc@6b09000 {
+			compatible = "arm,coresight-tmc", "arm,primecell";
+			reg = <0x0 0x06b09000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			in-ports {
+				port {
+					tmc_etf_swao_in: endpoint {
+						remote-endpoint= <&funnel_swao_out>;
+					};
+				};
+			};
+
+			out-ports {
+				port {
+					tmc_etf_swao_out: endpoint {
+						remote-endpoint= <&replicator_swao_in>;
+					};
+				};
+			};
+		};
+
+		replicator@6b0a000 {
+			compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
+			reg = <0x0 0x06b0a000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			in-ports {
+				port {
+					replicator_swao_in: endpoint {
+						remote-endpoint = <&tmc_etf_swao_out>;
+					};
+				};
+			};
+
+			out-ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					reg = <0>;
+
+					replicator_swao_out0: endpoint {
+						remote-endpoint = <&funnel_in1_in3>;
+					};
+				};
+
+				port@1 {
+					reg = <1>;
+
+					replicator_swao_out1: endpoint {
+						remote-endpoint = <&eud_in>;
+					};
+				};
+			};
+		};
+
+		cti@6b21000 {
+			compatible = "arm,coresight-cti", "arm,primecell";
+			reg = <0x0 0x06b21000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+		};
+
+		tpdm@6b48000 {
+			compatible = "qcom,coresight-tpdm", "arm,primecell";
+			reg = <0x0 0x06b48000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			qcom,dsb-element-bits = <32>;
+			qcom,dsb-msrs-num = <32>;
+
+			out-ports {
+				port {
+					tpdm_west_out: endpoint {
+						remote-endpoint = <&tpda_qdss_in12>;
+					};
+				};
+			};
+		};
+
+		cti@6c13000 {
+			compatible = "arm,coresight-cti", "arm,primecell";
+			reg = <0x0 0x06c13000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+		};
+
+		cti@6c20000 {
+			compatible = "arm,coresight-cti", "arm,primecell";
+			reg = <0x0 0x06c20000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+			status = "disabled";
+		};
+
+		tpdm@6c28000 {
+			compatible = "qcom,coresight-tpdm", "arm,primecell";
+			reg = <0x0 0x06c28000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			qcom,dsb-element-bits = <32>;
+			qcom,dsb-msrs-num = <32>;
+
+			out-ports {
+				port {
+					tpdm_center_out: endpoint {
+						remote-endpoint = <&tpda_qdss_in0>;
+					};
+				};
+			};
+		};
+
+		cti@6c29000 {
+			compatible = "arm,coresight-cti", "arm,primecell";
+			reg = <0x0 0x06c29000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+		};
+
+		cti@6c2a000 {
+			compatible = "arm,coresight-cti", "arm,primecell";
+			reg = <0x0 0x06c2a000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+		};
+
+		cti@7020000 {
+			compatible = "arm,coresight-cti", "arm,primecell";
+			reg = <0x0 0x07020000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+		};
+
+		etm@7040000 {
+			compatible = "arm,primecell";
+			reg = <0x0 0x07040000 0x0 0x1000>;
+			cpu = <&cpu0>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			arm,coresight-loses-context-with-cpu;
+			qcom,skip-power-up;
+
+			out-ports {
+				port {
+					etm0_out: endpoint {
+						remote-endpoint = <&funnel_apss_in0>;
+					};
+				};
+			};
+		};
+
+		cti@7120000 {
+			compatible = "arm,coresight-cti", "arm,primecell";
+			reg = <0x0 0x07120000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+		};
+
+		etm@7140000 {
+			compatible = "arm,primecell";
+			reg = <0x0 0x07140000 0x0 0x1000>;
+			cpu = <&cpu1>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			arm,coresight-loses-context-with-cpu;
+			qcom,skip-power-up;
+
+			out-ports {
+				port {
+					etm1_out: endpoint {
+						remote-endpoint = <&funnel_apss_in1>;
+					};
+				};
+			};
+		};
+
+		cti@7220000 {
+			compatible = "arm,coresight-cti", "arm,primecell";
+			reg = <0x0 0x07220000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+		};
+
+		etm@7240000 {
+			compatible = "arm,primecell";
+			reg = <0x0 0x07240000 0x0 0x1000>;
+			cpu = <&cpu2>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			arm,coresight-loses-context-with-cpu;
+			qcom,skip-power-up;
+
+			out-ports {
+				port {
+					etm2_out: endpoint {
+						remote-endpoint = <&funnel_apss_in2>;
+					};
+				};
+			};
+		};
+
+		cti@7320000 {
+			compatible = "arm,coresight-cti", "arm,primecell";
+			reg = <0x0 0x07320000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+		};
+
+		etm@7340000 {
+			compatible = "arm,primecell";
+			reg = <0x0 0x07340000 0x0 0x1000>;
+			cpu = <&cpu3>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			arm,coresight-loses-context-with-cpu;
+			qcom,skip-power-up;
+
+			out-ports {
+				port {
+					etm3_out: endpoint {
+						remote-endpoint = <&funnel_apss_in3>;
+					};
+				};
+			};
+		};
+
+		cti@7420000 {
+			compatible = "arm,coresight-cti", "arm,primecell";
+			reg = <0x0 0x07420000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+		};
+
+		etm@7440000 {
+			compatible = "arm,primecell";
+			reg = <0x0 0x07440000 0x0 0x1000>;
+			cpu = <&cpu4>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			arm,coresight-loses-context-with-cpu;
+			qcom,skip-power-up;
+
+			out-ports {
+				port {
+					etm4_out: endpoint {
+						remote-endpoint = <&funnel_apss_in4>;
+					};
+				};
+			};
+		};
+
+		cti@7520000 {
+			compatible = "arm,coresight-cti", "arm,primecell";
+			reg = <0x0 0x07520000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+		};
+
+		etm@7540000 {
+			compatible = "arm,primecell";
+			reg = <0x0 0x07540000 0x0 0x1000>;
+			cpu = <&cpu5>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			arm,coresight-loses-context-with-cpu;
+			qcom,skip-power-up;
+
+			out-ports {
+				port {
+					etm5_out: endpoint {
+						remote-endpoint = <&funnel_apss_in5>;
+					};
+				};
+			};
+		};
+
+		cti@7620000 {
+			compatible = "arm,coresight-cti", "arm,primecell";
+			reg = <0x0 0x07620000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+		};
+
+		etm@7640000 {
+			compatible = "arm,primecell";
+			reg = <0x0 0x07640000 0x0 0x1000>;
+			cpu = <&cpu6>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			arm,coresight-loses-context-with-cpu;
+			qcom,skip-power-up;
+
+			out-ports {
+				port {
+					etm6_out: endpoint {
+						remote-endpoint = <&funnel_apss_in6>;
+					};
+				};
+			};
+		};
+
+		cti@7720000 {
+			compatible = "arm,coresight-cti", "arm,primecell";
+			reg = <0x0 0x07720000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+		};
+
+		etm@7740000 {
+			compatible = "arm,primecell";
+			reg = <0x0 0x07740000 0x0 0x1000>;
+			cpu = <&cpu7>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			arm,coresight-loses-context-with-cpu;
+			qcom,skip-power-up;
+
+			out-ports {
+				port {
+					etm7_out: endpoint {
+						remote-endpoint = <&funnel_apss_in7>;
+					};
+				};
+			};
+		};
+
+		funnel@7800000 {
+			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+			reg = <0x0 0x07800000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			in-ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					reg = <0>;
+
+					funnel_apss_in0: endpoint {
+						remote-endpoint = <&etm0_out>;
+					};
+				};
+
+				port@1 {
+					reg = <1>;
+
+					funnel_apss_in1: endpoint {
+						remote-endpoint = <&etm1_out>;
+					};
+				};
+
+				port@2 {
+					reg = <2>;
+
+					funnel_apss_in2: endpoint {
+						remote-endpoint = <&etm2_out>;
+					};
+				};
+
+				port@3 {
+					reg = <3>;
+
+					funnel_apss_in3: endpoint {
+						remote-endpoint = <&etm3_out>;
+					};
+				};
+
+				port@4 {
+					reg = <4>;
+
+					funnel_apss_in4: endpoint {
+						remote-endpoint = <&etm4_out>;
+					};
+				};
+
+				port@5 {
+					reg = <5>;
+
+					funnel_apss_in5: endpoint {
+						remote-endpoint = <&etm5_out>;
+					};
+				};
+
+				port@6 {
+					reg = <6>;
+
+					funnel_apss_in6: endpoint {
+						remote-endpoint = <&etm6_out>;
+					};
+				};
+
+				port@7 {
+					reg = <7>;
+
+					funnel_apss_in7: endpoint {
+						remote-endpoint = <&etm7_out>;
+					};
+				};
+			};
+
+			out-ports {
+				port {
+					funnel_apss_out: endpoint {
+						remote-endpoint = <&funnel_apss_merg_in0>;
+					};
+				};
+			};
+		};
+
+		funnel@7810000 {
+			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+			reg = <0x0 0x07810000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			in-ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					reg = <0>;
+
+					funnel_apss_merg_in0: endpoint {
+						remote-endpoint = <&funnel_apss_out>;
+					};
+				};
+
+				port@2 {
+					reg = <2>;
+
+					funnel_apss_merg_in2: endpoint {
+						remote-endpoint = <&tpda_olc_out>;
+					};
+				};
+
+				port@3 {
+					reg = <3>;
+
+					funnel_apss_merg_in3: endpoint {
+						remote-endpoint = <&tpda_llm_silver_out>;
+					};
+				};
+
+				port@4 {
+					reg = <4>;
+
+					funnel_apss_merg_in4: endpoint {
+						remote-endpoint = <&tpda_llm_gold_out>;
+					};
+				};
+
+				port@5 {
+					reg = <5>;
+
+					funnel_apss_merg_in5: endpoint {
+						remote-endpoint = <&tpda_apss_out>;
+					};
+				};
+			};
+
+			out-ports {
+				port {
+					funnel_apss_merg_out: endpoint {
+						remote-endpoint = <&funnel_in1_in7>;
+					};
+				};
+			};
+		};
+
+		tpdm@7830000 {
+			compatible = "qcom,coresight-tpdm", "arm,primecell";
+			reg = <0x0 0x07830000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			qcom,cmb-element-bits = <64>;
+			qcom,cmb-msrs-num = <32>;
+
+			out-ports {
+				port {
+					tpdm_olc_out: endpoint {
+						remote-endpoint = <&tpda_olc_in>;
+					};
+				};
+			};
+		};
+
+		tpda@7832000 {
+			compatible = "qcom,coresight-tpda", "arm,primecell";
+			reg = <0x0 0x07832000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			in-ports {
+				port {
+					tpda_olc_in: endpoint {
+						remote-endpoint = <&tpdm_olc_out>;
+					};
+				};
+			};
+
+			out-ports {
+				port {
+					tpda_olc_out: endpoint {
+						remote-endpoint = <&funnel_apss_merg_in2>;
+					};
+				};
+			};
+		};
+
+		tpdm@7860000 {
+			compatible = "qcom,coresight-tpdm", "arm,primecell";
+			reg = <0x0 0x07860000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			qcom,dsb-element-bits = <32>;
+			qcom,dsb-msrs-num = <32>;
+
+			out-ports {
+				port {
+					tpdm_apss_out: endpoint {
+						remote-endpoint = <&tpda_apss_in>;
+					};
+				};
+			};
+		};
+
+		tpda@7862000 {
+			compatible = "qcom,coresight-tpda", "arm,primecell";
+			reg = <0x0 0x07862000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			in-ports {
+				port {
+					tpda_apss_in: endpoint {
+						remote-endpoint = <&tpdm_apss_out>;
+					};
+				};
+			};
+
+			out-ports {
+				port {
+					tpda_apss_out: endpoint {
+						remote-endpoint = <&funnel_apss_merg_in5>;
+					};
+				};
+			};
+		};
+
+		tpdm@78a0000 {
+			compatible = "qcom,coresight-tpdm", "arm,primecell";
+			reg = <0x0 0x078a0000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			qcom,cmb-element-bits = <32>;
+			qcom,cmb-msrs-num = <32>;
+
+			out-ports {
+				port {
+					tpdm_llm_silver_out: endpoint {
+						remote-endpoint = <&tpda_llm_silver_in>;
+					};
+				};
+			};
+		};
+
+		tpdm@78b0000 {
+			compatible = "qcom,coresight-tpdm", "arm,primecell";
+			reg = <0x0 0x078b0000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			qcom,cmb-element-bits = <32>;
+			qcom,cmb-msrs-num = <32>;
+
+			out-ports {
+				port {
+					tpdm_llm_gold_out: endpoint {
+						remote-endpoint = <&tpda_llm_gold_in>;
+					};
+				};
+			};
+		};
+
+		tpda@78c0000 {
+			compatible = "qcom,coresight-tpda", "arm,primecell";
+			reg = <0x0 0x078c0000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			in-ports {
+				port {
+					tpda_llm_silver_in: endpoint {
+						remote-endpoint = <&tpdm_llm_silver_out>;
+					};
+				};
+			};
+
+			out-ports {
+				port {
+					tpda_llm_silver_out: endpoint {
+						remote-endpoint = <&funnel_apss_merg_in3>;
+					};
+				};
+			};
+		};
+
+		tpda@78d0000 {
+			compatible = "qcom,coresight-tpda", "arm,primecell";
+			reg = <0x0 0x078d0000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			in-ports {
+				port {
+					tpda_llm_gold_in: endpoint {
+						remote-endpoint = <&tpdm_llm_gold_out>;
+					};
+				};
+			};
+
+			out-ports {
+				port {
+					tpda_llm_gold_out: endpoint {
+						remote-endpoint = <&funnel_apss_merg_in4>;
+					};
+				};
+			};
+		};
+
+		cti@78e0000 {
+			compatible = "arm,coresight-cti", "arm,primecell";
+			reg = <0x0 0x078e0000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+		};
+
+		cti@78f0000 {
+			compatible = "arm,coresight-cti", "arm,primecell";
+			reg = <0x0 0x078f0000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+		};
+
+		cti@7900000 {
+			compatible = "arm,coresight-cti", "arm,primecell";
+			reg = <0x0 0x07900000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+		};
+
+		pmu@90b6300 {
+			compatible = "qcom,qcs615-cpu-bwmon", "qcom,sdm845-bwmon";
+			reg = <0x0 0x090b6300 0x0 0x600>;
+			interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>;
+			interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+					 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>;
+
+			operating-points-v2 = <&cpu_bwmon_opp_table>;
+
+			cpu_bwmon_opp_table: opp-table {
+				compatible = "operating-points-v2";
+
+				opp-0 {
+					opp-peak-kBps = <12896000>;
+				};
+
+				opp-1 {
+					opp-peak-kBps = <14928000>;
+				};
+			};
+		};
+
+		pmu@90cd000 {
+			compatible = "qcom,qcs615-llcc-bwmon", "qcom,sc7280-llcc-bwmon";
+			reg = <0x0 0x090cd000 0x0 0x1000>;
+			interrupts = <GIC_SPI 667 IRQ_TYPE_LEVEL_HIGH>;
+			interconnects = <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY
+					 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>;
+
+			operating-points-v2 = <&llcc_bwmon_opp_table>;
+
+			llcc_bwmon_opp_table: opp-table {
+				compatible = "operating-points-v2";
+
+				opp-0 {
+					opp-peak-kBps = <800000>;
+				};
+
+				opp-1 {
+					opp-peak-kBps = <1200000>;
+				};
+
+				opp-2 {
+					opp-peak-kBps = <1804800>;
+				};
+
+				opp-3 {
+					opp-peak-kBps = <2188800>;
+				};
+
+				opp-4 {
+					opp-peak-kBps = <2726400>;
+				};
+
+				opp-5 {
+					opp-peak-kBps = <3072000>;
+				};
+
+				opp-6 {
+					opp-peak-kBps = <4070400>;
+				};
+
+				opp-7 {
+					opp-peak-kBps = <5414400>;
+				};
+
+				opp-8 {
+					opp-peak-kBps = <6220800>;
+				};
+			};
+		};
+
+		sdhc_2: mmc@8804000 {
+			compatible = "qcom,qcs615-sdhci", "qcom,sdhci-msm-v5";
+			reg = <0x0 0x08804000 0x0 0x1000>;
+			reg-names = "hc";
+
+			interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "hc_irq",
+					  "pwr_irq";
+
+			clocks = <&gcc GCC_SDCC2_AHB_CLK>,
+				 <&gcc GCC_SDCC2_APPS_CLK>,
+				 <&rpmhcc RPMH_CXO_CLK>;
+			clock-names = "iface",
+				      "core",
+				      "xo";
+
+			power-domains = <&rpmhpd RPMHPD_CX>;
+			operating-points-v2 = <&sdhc2_opp_table>;
+			iommus = <&apps_smmu 0x02a0 0x0>;
+			resets = <&gcc GCC_SDCC2_BCR>;
+			interconnects = <&aggre1_noc MASTER_SDCC_2 QCOM_ICC_TAG_ALWAYS
+					 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
+					<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+					 &config_noc SLAVE_SDCC_2 QCOM_ICC_TAG_ACTIVE_ONLY>;
+			interconnect-names = "sdhc-ddr",
+					     "cpu-sdhc";
+
+			qcom,dll-config = <0x0007642c>;
+			qcom,ddr-config = <0x80040868>;
+			dma-coherent;
+
+			status = "disabled";
+
+			sdhc2_opp_table: opp-table {
+				compatible = "operating-points-v2";
+
+				opp-50000000 {
+					opp-hz = /bits/ 64 <50000000>;
+					required-opps = <&rpmhpd_opp_low_svs>;
+				};
+
+				opp-100000000 {
+					opp-hz = /bits/ 64 <100000000>;
+					required-opps = <&rpmhpd_opp_svs>;
+				};
+
+				opp-202000000 {
+					opp-hz = /bits/ 64 <202000000>;
+					required-opps = <&rpmhpd_opp_nom>;
+				};
+			};
+		};
+
+		dc_noc: interconnect@9160000 {
+			reg = <0x0 0x09160000 0x0 0x3200>;
+			compatible = "qcom,qcs615-dc-noc";
+			#interconnect-cells = <2>;
+			qcom,bcm-voters = <&apps_bcm_voter>;
+		};
+
+		llcc: system-cache-controller@9200000 {
+			compatible = "qcom,qcs615-llcc";
+			reg = <0x0 0x09200000 0x0 0x50000>,
+			      <0x0 0x09600000 0x0 0x50000>;
+			reg-names = "llcc0_base",
+				    "llcc_broadcast_base";
+		};
+
+		gem_noc: interconnect@9680000 {
+			reg = <0x0 0x09680000 0x0 0x3e200>;
+			compatible = "qcom,qcs615-gem-noc";
+			#interconnect-cells = <2>;
+			qcom,bcm-voters = <&apps_bcm_voter>;
+		};
+
+		pdc: interrupt-controller@b220000 {
+			compatible = "qcom,qcs615-pdc", "qcom,pdc";
+			reg = <0x0 0x0b220000 0x0 0x30000>,
+			      <0x0 0x17c000f0 0x0 0x64>;
+			qcom,pdc-ranges = <0 480 94>, <94 609 31>, <125 63 1>;
+			interrupt-parent = <&intc>;
+			#interrupt-cells = <2>;
+			interrupt-controller;
+		};
+
+		aoss_qmp: power-controller@c300000 {
+			compatible = "qcom,qcs615-aoss-qmp", "qcom,aoss-qmp";
+			reg = <0x0 0x0c300000 0x0 0x400>;
+			interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>;
+			mboxes = <&apss_shared 0>;
+
+			#clock-cells = <0>;
+			#power-domain-cells = <1>;
+		};
+
+		sram@c3f0000 {
+			compatible = "qcom,rpmh-stats";
+			reg = <0x0 0x0c3f0000 0x0 0x400>;
+		};
+
+		apps_smmu: iommu@15000000 {
+			compatible = "qcom,qcs615-smmu-500", "qcom,smmu-500", "arm,mmu-500";
+			reg = <0x0 0x15000000 0x0 0x80000>;
+			#iommu-cells = <2>;
+			#global-interrupts = <1>;
+			dma-coherent;
+
+			interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>;
+		};
+
+		spmi_bus: spmi@c440000 {
+			compatible = "qcom,spmi-pmic-arb";
+			reg = <0x0 0x0c440000 0x0 0x1100>,
+			      <0x0 0x0c600000 0x0 0x2000000>,
+			      <0x0 0x0e600000 0x0 0x100000>,
+			      <0x0 0x0e700000 0x0 0xa0000>,
+			      <0x0 0x0c40a000 0x0 0x26000>;
+			reg-names = "core",
+				    "chnls",
+				    "obsrvr",
+				    "intr",
+				    "cnfg";
+			interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "periph_irq";
+			interrupt-controller;
+			#interrupt-cells = <4>;
+			#address-cells = <2>;
+			#size-cells = <0>;
+			cell-index = <0>;
+			qcom,channel = <0>;
+			qcom,ee = <0>;
+		};
+
+		intc: interrupt-controller@17a00000 {
+			compatible = "arm,gic-v3";
+			reg = <0x0 0x17a00000 0x0 0x10000>,     /* GICD */
+			      <0x0 0x17a60000 0x0 0x100000>;    /* GICR * 8 */
+			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+			#interrupt-cells = <3>;
+			interrupt-controller;
+			#redistributor-regions = <1>;
+			redistributor-stride = <0x0 0x20000>;
+		};
+
+		apss_shared: mailbox@17c00000 {
+			compatible = "qcom,qcs615-apss-shared",
+				     "qcom,sdm845-apss-shared";
+			reg = <0x0 0x17c00000 0x0 0x1000>;
+			#mbox-cells = <1>;
+		};
+
+		watchdog: watchdog@17c10000 {
+			compatible = "qcom,apss-wdt-qcs615", "qcom,kpss-wdt";
+			reg = <0x0 0x17c10000 0x0 0x1000>;
+			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
+		};
+
+		timer@17c20000 {
+			compatible = "arm,armv7-timer-mem";
+			reg = <0x0 0x17c20000 0x0 0x1000>;
+			ranges = <0 0 0 0x20000000>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			frame@17c21000 {
+				reg = <0x17c21000 0x1000>,
+				      <0x17c22000 0x1000>;
+				frame-number = <0>;
+				interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+			};
+
+			frame@17c23000 {
+				reg = <0x17c23000 0x1000>;
+				frame-number = <1>;
+				interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+				status = "disabled";
+			};
+
+			frame@17c25000 {
+				reg = <0x17c25000 0x1000>;
+				frame-number = <2>;
+				interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+				status = "disabled";
+			};
+
+			frame@17c27000 {
+				reg = <0x17c27000 0x1000>;
+				frame-number = <3>;
+				interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+				status = "disabled";
+			};
+
+			frame@17c29000 {
+				reg = <0x17c29000 0x1000>;
+				frame-number = <4>;
+				interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+				status = "disabled";
+			};
+
+			frame@17c2b000 {
+				reg = <0x17c2b000 0x1000>;
+				frame-number = <5>;
+				interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
+				status = "disabled";
+			};
+
+			frame@17c2d000 {
+				reg = <0x17c2d000 0x1000>;
+				frame-number = <6>;
+				interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+				status = "disabled";
+			};
+		};
+
+		apps_rsc: rsc@18200000 {
+			compatible = "qcom,rpmh-rsc";
+			reg = <0x0 0x18200000 0x0 0x10000>,
+			      <0x0 0x18210000 0x0 0x10000>,
+			      <0x0 0x18220000 0x0 0x10000>;
+			reg-names = "drv-0",
+				    "drv-1",
+				    "drv-2";
+
+			interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
+
+			qcom,drv-id = <2>;
+			qcom,tcs-offset = <0xd00>;
+			qcom,tcs-config = <ACTIVE_TCS    2>,
+					  <SLEEP_TCS     3>,
+					  <WAKE_TCS      3>,
+					  <CONTROL_TCS   1>;
+
+			label = "apps_rsc";
+			power-domains = <&cluster_pd>;
+
+			apps_bcm_voter: bcm-voter {
+				compatible = "qcom,bcm-voter";
+			};
+
+			rpmhcc: clock-controller {
+				compatible = "qcom,qcs615-rpmh-clk";
+				clock-names = "xo";
+
+				#clock-cells = <1>;
+			};
+
+			rpmhpd: power-controller {
+				compatible = "qcom,qcs615-rpmhpd";
+				#power-domain-cells = <1>;
+				operating-points-v2 = <&rpmhpd_opp_table>;
+
+				rpmhpd_opp_table: opp-table {
+					compatible = "operating-points-v2";
+
+					rpmhpd_opp_ret: opp-0 {
+						opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
+					};
+
+					rpmhpd_opp_min_svs: opp-1 {
+						opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
+					};
+
+					rpmhpd_opp_low_svs: opp-2 {
+						opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
+					};
+
+					rpmhpd_opp_svs: opp-3 {
+						opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
+					};
+
+					rpmhpd_opp_svs_l1: opp-4 {
+						opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
+					};
+
+					rpmhpd_opp_nom: opp-5 {
+						opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
+					};
+
+					rpmhpd_opp_nom_l1: opp-6 {
+						opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
+					};
+
+					rpmhpd_opp_nom_l2: opp-7 {
+						opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
+					};
+
+					rpmhpd_opp_turbo: opp-8 {
+						opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
+					};
+
+					rpmhpd_opp_turbo_l1: opp-9 {
+						opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
+					};
+				};
+			};
+		};
+
+		usb_1_hsphy: phy@88e2000 {
+			compatible = "qcom,qcs615-qusb2-phy";
+			reg = <0x0 0x88e2000 0x0 0x180>;
+
+			clocks = <&gcc GCC_AHB2PHY_WEST_CLK>, <&rpmhcc RPMH_CXO_CLK>;
+			clock-names = "cfg_ahb", "ref";
+
+			resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
+			nvmem-cells = <&qusb2_hstx_trim>;
+
+			#phy-cells = <0>;
+
+			status = "disabled";
+		};
+
+		usb_hsphy_2: phy@88e3000 {
+			compatible = "qcom,qcs615-qusb2-phy";
+			reg = <0x0 0x088e3000 0x0 0x180>;
+
+			clocks = <&gcc GCC_AHB2PHY_WEST_CLK>,
+				 <&rpmhcc RPMH_CXO_CLK>;
+			clock-names = "cfg_ahb",
+				      "ref";
+
+			resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
+
+			#phy-cells = <0>;
+
+			status = "disabled";
+		};
+
+		usb_qmpphy: phy@88e6000 {
+			compatible = "qcom,qcs615-qmp-usb3-phy";
+			reg = <0x0 0x88e6000 0x0 0x1000>;
+
+			clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
+				 <&gcc GCC_USB3_PRIM_CLKREF_CLK>,
+				 <&gcc GCC_AHB2PHY_WEST_CLK>,
+				 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
+			clock-names = "aux",
+				      "ref",
+				      "cfg_ahb",
+				      "pipe";
+
+			resets = <&gcc GCC_USB3_PHY_PRIM_SP0_BCR>,
+				 <&gcc GCC_USB3PHY_PHY_PRIM_SP0_BCR>;
+			reset-names = "phy", "phy_phy";
+
+			qcom,tcsr-reg = <&tcsr 0xb244>;
+
+			clock-output-names = "usb3_phy_pipe_clk_src";
+			#clock-cells = <0>;
+
+			#phy-cells = <0>;
+
+			status = "disabled";
+		};
+
+		usb_1: usb@a6f8800 {
+			compatible = "qcom,qcs615-dwc3", "qcom,dwc3";
+			reg = <0x0 0x0a6f8800 0x0 0x400>;
+
+			clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
+				 <&gcc GCC_USB30_PRIM_MASTER_CLK>,
+				 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
+				 <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
+				 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
+				 <&gcc GCC_USB3_PRIM_CLKREF_CLK>;
+			clock-names = "cfg_noc",
+				      "core",
+				      "iface",
+				      "sleep",
+				      "mock_utmi",
+				      "xo";
+
+			assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
+					  <&gcc GCC_USB30_PRIM_MASTER_CLK>;
+			assigned-clock-rates = <19200000>, <200000000>;
+
+			interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
+					      <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
+					      <&pdc 9 IRQ_TYPE_EDGE_BOTH>,
+					      <&pdc 8 IRQ_TYPE_EDGE_BOTH>,
+					      <&pdc 6 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "pwr_event",
+					  "hs_phy_irq",
+					  "dp_hs_phy_irq",
+					  "dm_hs_phy_irq",
+					  "ss_phy_irq";
+
+			power-domains = <&gcc USB30_PRIM_GDSC>;
+			required-opps = <&rpmhpd_opp_nom>;
+
+			resets = <&gcc GCC_USB30_PRIM_BCR>;
+
+			#address-cells = <2>;
+			#size-cells = <2>;
+			ranges;
+
+			status = "disabled";
+
+			usb_1_dwc3: usb@a600000 {
+				compatible = "snps,dwc3";
+				reg = <0x0 0x0a600000 0x0 0xcd00>;
+
+				iommus = <&apps_smmu 0x140 0x0>;
+				interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
+
+				phys = <&usb_1_hsphy>, <&usb_qmpphy>;
+				phy-names = "usb2-phy", "usb3-phy";
+
+				snps,dis-u1-entry-quirk;
+				snps,dis-u2-entry-quirk;
+				snps,dis_u2_susphy_quirk;
+				snps,dis_enblslpm_quirk;
+				snps,has-lpm-erratum;
+				snps,hird-threshold = /bits/ 8 <0x10>;
+				snps,usb3_lpm_capable;
+			};
+		};
+
+		usb_2: usb@a8f8800 {
+			compatible = "qcom,qcs615-dwc3", "qcom,dwc3";
+			reg = <0x0 0x0a8f8800 0x0 0x400>;
+
+			clocks = <&gcc GCC_CFG_NOC_USB2_SEC_AXI_CLK>,
+				 <&gcc GCC_USB20_SEC_MASTER_CLK>,
+				 <&gcc GCC_AGGRE_USB2_SEC_AXI_CLK>,
+				 <&gcc GCC_USB20_SEC_SLEEP_CLK>,
+				 <&gcc GCC_USB20_SEC_MOCK_UTMI_CLK>,
+				 <&gcc GCC_USB2_PRIM_CLKREF_CLK>;
+			clock-names = "cfg_noc",
+				      "core",
+				      "iface",
+				      "sleep",
+				      "mock_utmi",
+				      "xo";
+
+			assigned-clocks = <&gcc GCC_USB20_SEC_MOCK_UTMI_CLK>,
+					  <&gcc GCC_USB20_SEC_MASTER_CLK>;
+			assigned-clock-rates = <19200000>, <200000000>;
+
+			interrupts-extended = <&intc GIC_SPI 663 IRQ_TYPE_LEVEL_HIGH>,
+					      <&intc GIC_SPI 662 IRQ_TYPE_LEVEL_HIGH>,
+					      <&pdc 11 IRQ_TYPE_EDGE_BOTH>,
+					      <&pdc 10 IRQ_TYPE_EDGE_BOTH>;
+			interrupt-names = "pwr_event",
+					  "hs_phy_irq",
+					  "dp_hs_phy_irq",
+					  "dm_hs_phy_irq";
+
+			power-domains = <&gcc USB20_SEC_GDSC>;
+			required-opps = <&rpmhpd_opp_nom>;
+
+			resets = <&gcc GCC_USB20_SEC_BCR>;
+
+			qcom,select-utmi-as-pipe-clk;
+
+			#address-cells = <2>;
+			#size-cells = <2>;
+			ranges;
+
+			status = "disabled";
+
+			usb_2_dwc3: usb@a800000 {
+				compatible = "snps,dwc3";
+				reg = <0x0 0x0a800000 0x0 0xcd00>;
+
+				iommus = <&apps_smmu 0xe0 0x0>;
+				interrupts = <GIC_SPI 664 IRQ_TYPE_LEVEL_HIGH>;
+
+				phys = <&usb_hsphy_2>;
+				phy-names = "usb2-phy";
+
+				snps,dis_u2_susphy_quirk;
+				snps,dis_enblslpm_quirk;
+				snps,has-lpm-erratum;
+				snps,hird-threshold = /bits/ 8 <0x10>;
+
+				maximum-speed = "high-speed";
+			};
+		};
+	};
+
+	arch_timer: timer {
+		compatible = "arm,armv8-timer";
+		interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
+	};
+};
diff --git a/dts/upstream/src/arm64/qcom/qcs6490-rb3gen2.dts b/dts/upstream/src/arm64/qcom/qcs6490-rb3gen2.dts
index 27695bd5422..7a36c90ad4e 100644
--- a/dts/upstream/src/arm64/qcom/qcs6490-rb3gen2.dts
+++ b/dts/upstream/src/arm64/qcom/qcs6490-rb3gen2.dts
@@ -9,6 +9,7 @@
 #define PM7250B_SID 8
 #define PM7250B_SID1 9
 
+#include <dt-bindings/leds/common.h>
 #include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
 #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
 #include "sc7280.dtsi"
@@ -744,6 +745,46 @@
 	};
 };
 
+&pm8350c_pwm {
+	nvmem = <&pmk8350_sdam_21>,
+		<&pmk8350_sdam_22>;
+	nvmem-names = "lpg_chan_sdam",
+		      "lut_sdam";
+
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	status = "okay";
+
+	led@1 {
+		reg = <1>;
+		color = <LED_COLOR_ID_GREEN>;
+		function = LED_FUNCTION_INDICATOR;
+		function-enumerator = <3>;
+		linux,default-trigger = "none";
+		default-state = "off";
+		panic-indicator;
+	};
+
+	led@2 {
+		reg = <2>;
+		color = <LED_COLOR_ID_GREEN>;
+		function = LED_FUNCTION_INDICATOR;
+		function-enumerator = <2>;
+		linux,default-trigger = "none";
+		default-state = "off";
+	};
+
+	led@3 {
+		reg = <3>;
+		color = <LED_COLOR_ID_GREEN>;
+		function = LED_FUNCTION_INDICATOR;
+		function-enumerator = <1>;
+		linux,default-trigger = "none";
+		default-state = "off";
+	};
+};
+
 &pmk8350_rtc {
 	status = "okay";
 };
diff --git a/dts/upstream/src/arm64/qcom/qcs8300-ride.dts b/dts/upstream/src/arm64/qcom/qcs8300-ride.dts
new file mode 100644
index 00000000000..b5c9f89b343
--- /dev/null
+++ b/dts/upstream/src/arm64/qcom/qcs8300-ride.dts
@@ -0,0 +1,370 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
+
+#include "qcs8300.dtsi"
+/ {
+	model = "Qualcomm Technologies, Inc. QCS8300 Ride";
+	compatible = "qcom,qcs8300-ride", "qcom,qcs8300";
+	chassis-type = "embedded";
+
+	aliases {
+		serial0 = &uart7;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+};
+
+&apps_rsc {
+	regulators-0 {
+		compatible = "qcom,pmm8654au-rpmh-regulators";
+		qcom,pmic-id = "a";
+
+		vreg_s4a: smps4 {
+			regulator-name = "vreg_s4a";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_s9a: smps9 {
+			regulator-name = "vreg_s9a";
+			regulator-min-microvolt = <1352000>;
+			regulator-max-microvolt = <1352000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l3a: ldo3 {
+			regulator-name = "vreg_l3a";
+			regulator-min-microvolt = <1200000>;
+			regulator-max-microvolt = <1200000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l4a: ldo4 {
+			regulator-name = "vreg_l4a";
+			regulator-min-microvolt = <880000>;
+			regulator-max-microvolt = <912000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l5a: ldo5 {
+			regulator-name = "vreg_l5a";
+			regulator-min-microvolt = <1200000>;
+			regulator-max-microvolt = <1200000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l6a: ldo6 {
+			regulator-name = "vreg_l6a";
+			regulator-min-microvolt = <880000>;
+			regulator-max-microvolt = <912000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l7a: ldo7 {
+			regulator-name = "vreg_l7a";
+			regulator-min-microvolt = <880000>;
+			regulator-max-microvolt = <912000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l8a: ldo8 {
+			regulator-name = "vreg_l8a";
+			regulator-min-microvolt = <2504000>;
+			regulator-max-microvolt = <2960000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l9a: ldo9 {
+			regulator-name = "vreg_l9a";
+			regulator-min-microvolt = <2970000>;
+			regulator-max-microvolt = <3072000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+	};
+
+	regulators-1 {
+		compatible = "qcom,pmm8654au-rpmh-regulators";
+		qcom,pmic-id = "c";
+
+		vreg_s5c: smps5 {
+			regulator-name = "vreg_s5c";
+			regulator-min-microvolt = <1104000>;
+			regulator-max-microvolt = <1104000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l1c: ldo1 {
+			regulator-name = "vreg_l1c";
+			regulator-min-microvolt = <300000>;
+			regulator-max-microvolt = <500000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l2c: ldo2 {
+			regulator-name = "vreg_l2c";
+			regulator-min-microvolt = <900000>;
+			regulator-max-microvolt = <904000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l4c: ldo4 {
+			regulator-name = "vreg_l4c";
+			regulator-min-microvolt = <1200000>;
+			regulator-max-microvolt = <1200000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l6c: ldo6 {
+			regulator-name = "vreg_l6c";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l7c: ldo7 {
+			regulator-name = "vreg_l7c";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l8c: ldo8 {
+			regulator-name = "vreg_l8c";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l9c: ldo9 {
+			regulator-name = "vreg_l9c";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+	};
+};
+
+&ethernet0 {
+	phy-mode = "2500base-x";
+	phy-handle = <&phy0>;
+
+	pinctrl-0 = <&ethernet0_default>;
+	pinctrl-names = "default";
+
+	snps,mtl-rx-config = <&mtl_rx_setup>;
+	snps,mtl-tx-config = <&mtl_tx_setup>;
+	snps,ps-speed = <1000>;
+
+	status = "okay";
+
+	mdio {
+		compatible = "snps,dwmac-mdio";
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		phy0: phy@8 {
+			compatible = "ethernet-phy-id31c3.1c33";
+			reg = <0x8>;
+			device_type = "ethernet-phy";
+			interrupts-extended = <&tlmm 4 IRQ_TYPE_EDGE_FALLING>;
+			reset-gpios = <&tlmm 31 GPIO_ACTIVE_LOW>;
+			reset-assert-us = <11000>;
+			reset-deassert-us = <70000>;
+		};
+	};
+
+	mtl_rx_setup: rx-queues-config {
+		snps,rx-queues-to-use = <4>;
+		snps,rx-sched-sp;
+
+		queue0 {
+			snps,dcb-algorithm;
+			snps,map-to-dma-channel = <0x0>;
+			snps,route-up;
+			snps,priority = <0x1>;
+		};
+
+		queue1 {
+			snps,dcb-algorithm;
+			snps,map-to-dma-channel = <0x1>;
+			snps,route-ptp;
+		};
+
+		queue2 {
+			snps,avb-algorithm;
+			snps,map-to-dma-channel = <0x2>;
+			snps,route-avcp;
+		};
+
+		queue3 {
+			snps,avb-algorithm;
+			snps,map-to-dma-channel = <0x3>;
+			snps,priority = <0xc>;
+		};
+	};
+
+	mtl_tx_setup: tx-queues-config {
+		snps,tx-queues-to-use = <4>;
+		snps,tx-sched-sp;
+
+		queue0 {
+			snps,dcb-algorithm;
+		};
+
+		queue1 {
+			snps,dcb-algorithm;
+		};
+
+		queue2 {
+			snps,avb-algorithm;
+			snps,send_slope = <0x1000>;
+			snps,idle_slope = <0x1000>;
+			snps,high_credit = <0x3e800>;
+			snps,low_credit = <0xffc18000>;
+		};
+
+		queue3 {
+			snps,avb-algorithm;
+			snps,send_slope = <0x1000>;
+			snps,idle_slope = <0x1000>;
+			snps,high_credit = <0x3e800>;
+			snps,low_credit = <0xffc18000>;
+		};
+	};
+};
+
+&qupv3_id_0 {
+	status = "okay";
+};
+
+&remoteproc_adsp {
+	firmware-name = "qcom/qcs8300/adsp.mbn";
+	status = "okay";
+};
+
+&remoteproc_cdsp {
+	firmware-name = "qcom/qcs8300/cdsp0.mbn";
+	status = "okay";
+};
+
+&remoteproc_gpdsp {
+	firmware-name = "qcom/qcs8300/gpdsp0.mbn";
+	status = "okay";
+};
+
+&serdes0 {
+	phy-supply = <&vreg_l5a>;
+	status = "okay";
+};
+
+&tlmm {
+	ethernet0_default: ethernet0-default-state {
+		ethernet0_mdc: ethernet0-mdc-pins {
+			pins = "gpio5";
+			function = "emac0_mdc";
+			drive-strength = <16>;
+			bias-pull-up;
+		};
+
+		ethernet0_mdio: ethernet0-mdio-pins {
+			pins = "gpio6";
+			function = "emac0_mdio";
+			drive-strength = <16>;
+			bias-pull-up;
+		};
+	};
+};
+
+&uart7 {
+	status = "okay";
+};
+
+&ufs_mem_hc {
+	reset-gpios = <&tlmm 133 GPIO_ACTIVE_LOW>;
+	vcc-supply = <&vreg_l8a>;
+	vcc-max-microamp = <1100000>;
+	vccq-supply = <&vreg_l4c>;
+	vccq-max-microamp = <1200000>;
+	status = "okay";
+};
+
+&ufs_mem_phy {
+	vdda-phy-supply = <&vreg_l4a>;
+	vdda-pll-supply = <&vreg_l5a>;
+	status = "okay";
+};
+
+&usb_1_hsphy {
+	vdda-pll-supply = <&vreg_l7a>;
+	vdda18-supply = <&vreg_l7c>;
+	vdda33-supply = <&vreg_l9a>;
+
+	status = "okay";
+};
+
+&usb_qmpphy {
+	vdda-phy-supply = <&vreg_l7a>;
+	vdda-pll-supply = <&vreg_l5a>;
+
+	status = "okay";
+};
+
+&usb_1 {
+	status = "okay";
+};
+
+&usb_1_dwc3 {
+	dr_mode = "peripheral";
+};
diff --git a/dts/upstream/src/arm64/qcom/qcs8300.dtsi b/dts/upstream/src/arm64/qcom/qcs8300.dtsi
new file mode 100644
index 00000000000..4a057f7c0d9
--- /dev/null
+++ b/dts/upstream/src/arm64/qcom/qcs8300.dtsi
@@ -0,0 +1,3548 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#include <dt-bindings/clock/qcom,qcs8300-gcc.h>
+#include <dt-bindings/clock/qcom,rpmh.h>
+#include <dt-bindings/clock/qcom,sa8775p-camcc.h>
+#include <dt-bindings/clock/qcom,sa8775p-dispcc.h>
+#include <dt-bindings/clock/qcom,sa8775p-gpucc.h>
+#include <dt-bindings/clock/qcom,sa8775p-videocc.h>
+#include <dt-bindings/firmware/qcom,scm.h>
+#include <dt-bindings/interconnect/qcom,icc.h>
+#include <dt-bindings/interconnect/qcom,qcs8300-rpmh.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/mailbox/qcom-ipcc.h>
+#include <dt-bindings/power/qcom,rpmhpd.h>
+#include <dt-bindings/power/qcom-rpmpd.h>
+#include <dt-bindings/soc/qcom,rpmh-rsc.h>
+
+/ {
+	interrupt-parent = <&intc>;
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	clocks {
+		xo_board_clk: xo-board-clk {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <38400000>;
+		};
+
+		sleep_clk: sleep-clk {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <32000>;
+		};
+	};
+
+	cpus {
+		#address-cells = <2>;
+		#size-cells = <0>;
+
+		cpu0: cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a78c";
+			reg = <0x0 0x0>;
+			enable-method = "psci";
+			next-level-cache = <&l2_0>;
+			power-domains = <&cpu_pd0>;
+			power-domain-names = "psci";
+			capacity-dmips-mhz = <1946>;
+			dynamic-power-coefficient = <472>;
+
+			l2_0: l2-cache {
+				compatible = "cache";
+				cache-level = <2>;
+				cache-unified;
+				next-level-cache = <&l3_0>;
+			};
+		};
+
+		cpu1: cpu@100 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a78c";
+			reg = <0x0 0x100>;
+			enable-method = "psci";
+			next-level-cache = <&l2_1>;
+			power-domains = <&cpu_pd1>;
+			power-domain-names = "psci";
+			capacity-dmips-mhz = <1946>;
+			dynamic-power-coefficient = <472>;
+
+			l2_1: l2-cache {
+				compatible = "cache";
+				cache-level = <2>;
+				cache-unified;
+				next-level-cache = <&l3_0>;
+			};
+		};
+
+		cpu2: cpu@200 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a78c";
+			reg = <0x0 0x200>;
+			enable-method = "psci";
+			next-level-cache = <&l2_2>;
+			power-domains = <&cpu_pd2>;
+			power-domain-names = "psci";
+			capacity-dmips-mhz = <1946>;
+			dynamic-power-coefficient = <507>;
+
+			l2_2: l2-cache {
+				compatible = "cache";
+				cache-level = <2>;
+				cache-unified;
+				next-level-cache = <&l3_0>;
+			};
+		};
+
+		cpu3: cpu@300 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a78c";
+			reg = <0x0 0x300>;
+			enable-method = "psci";
+			next-level-cache = <&l2_3>;
+			power-domains = <&cpu_pd3>;
+			power-domain-names = "psci";
+			capacity-dmips-mhz = <1946>;
+			dynamic-power-coefficient = <507>;
+
+			l2_3: l2-cache {
+				compatible = "cache";
+				cache-level = <2>;
+				cache-unified;
+				next-level-cache = <&l3_0>;
+			};
+		};
+
+		cpu4: cpu@10000 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a55";
+			reg = <0x0 0x10000>;
+			enable-method = "psci";
+			next-level-cache = <&l2_4>;
+			power-domains = <&cpu_pd4>;
+			power-domain-names = "psci";
+			capacity-dmips-mhz = <1024>;
+			dynamic-power-coefficient = <100>;
+
+			l2_4: l2-cache {
+				compatible = "cache";
+				cache-level = <2>;
+				cache-unified;
+				next-level-cache = <&l3_1>;
+			};
+		};
+
+		cpu5: cpu@10100 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a55";
+			reg = <0x0 0x10100>;
+			enable-method = "psci";
+			next-level-cache = <&l2_5>;
+			power-domains = <&cpu_pd5>;
+			power-domain-names = "psci";
+			capacity-dmips-mhz = <1024>;
+			dynamic-power-coefficient = <100>;
+
+			l2_5: l2-cache {
+				compatible = "cache";
+				cache-level = <2>;
+				cache-unified;
+				next-level-cache = <&l3_1>;
+			};
+		};
+
+		cpu6: cpu@10200 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a55";
+			reg = <0x0 0x10200>;
+			enable-method = "psci";
+			next-level-cache = <&l2_6>;
+			power-domains = <&cpu_pd6>;
+			power-domain-names = "psci";
+			capacity-dmips-mhz = <1024>;
+			dynamic-power-coefficient = <100>;
+
+			l2_6: l2-cache {
+				compatible = "cache";
+				cache-level = <2>;
+				cache-unified;
+				next-level-cache = <&l3_1>;
+			};
+		};
+
+		cpu7: cpu@10300 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a55";
+			reg = <0x0 0x10300>;
+			enable-method = "psci";
+			next-level-cache = <&l2_7>;
+			power-domains = <&cpu_pd7>;
+			power-domain-names = "psci";
+			capacity-dmips-mhz = <1024>;
+			dynamic-power-coefficient = <100>;
+
+			l2_7: l2-cache {
+				compatible = "cache";
+				cache-level = <2>;
+				cache-unified;
+				next-level-cache = <&l3_1>;
+			};
+		};
+
+		cpu-map {
+			cluster0 {
+				core0 {
+					cpu = <&cpu0>;
+				};
+
+				core1 {
+					cpu = <&cpu1>;
+				};
+
+				core2 {
+					cpu = <&cpu2>;
+				};
+
+				core3 {
+					cpu = <&cpu3>;
+				};
+			};
+
+			cluster1 {
+				core0 {
+					cpu = <&cpu4>;
+				};
+
+				core1 {
+					cpu = <&cpu5>;
+				};
+
+				core2 {
+					cpu = <&cpu6>;
+				};
+
+				core3 {
+					cpu = <&cpu7>;
+				};
+			};
+		};
+
+		l3_0: l3-cache-0 {
+			compatible = "cache";
+			cache-level = <3>;
+			cache-unified;
+		};
+
+		l3_1: l3-cache-1 {
+			compatible = "cache";
+			cache-level = <3>;
+			cache-unified;
+		};
+
+		idle-states {
+			entry-method = "psci";
+
+			little_cpu_sleep_0: cpu-sleep-0-0 {
+				compatible = "arm,idle-state";
+				idle-state-name = "silver-power-collapse";
+				arm,psci-suspend-param = <0x40000003>;
+				entry-latency-us = <449>;
+				exit-latency-us = <801>;
+				min-residency-us = <1574>;
+				local-timer-stop;
+			};
+
+			little_cpu_sleep_1: cpu-sleep-0-1 {
+				compatible = "arm,idle-state";
+				idle-state-name = "silver-rail-power-collapse";
+				arm,psci-suspend-param = <0x40000004>;
+				entry-latency-us = <602>;
+				exit-latency-us = <961>;
+				min-residency-us = <4288>;
+				local-timer-stop;
+			};
+
+			big_cpu_sleep_0: cpu-sleep-1-0 {
+				compatible = "arm,idle-state";
+				idle-state-name = "gold-power-collapse";
+				arm,psci-suspend-param = <0x40000003>;
+				entry-latency-us = <549>;
+				exit-latency-us = <901>;
+				min-residency-us = <1774>;
+				local-timer-stop;
+			};
+
+			big_cpu_sleep_1: cpu-sleep-1-1 {
+				compatible = "arm,idle-state";
+				idle-state-name = "gold-rail-power-collapse";
+				arm,psci-suspend-param = <0x40000004>;
+				entry-latency-us = <702>;
+				exit-latency-us = <1061>;
+				min-residency-us = <4488>;
+				local-timer-stop;
+			};
+		};
+
+		domain-idle-states {
+			silver_cluster_sleep: cluster-sleep-0 {
+				compatible = "domain-idle-state";
+				arm,psci-suspend-param = <0x41000044>;
+				entry-latency-us = <2552>;
+				exit-latency-us = <2848>;
+				min-residency-us = <5908>;
+			};
+
+			gold_cluster_sleep: cluster-sleep-1 {
+				compatible = "domain-idle-state";
+				arm,psci-suspend-param = <0x41000044>;
+				entry-latency-us = <2752>;
+				exit-latency-us = <3048>;
+				min-residency-us = <6118>;
+			};
+
+			system_sleep: domain-sleep {
+				compatible = "domain-idle-state";
+				arm,psci-suspend-param = <0x42000144>;
+				entry-latency-us = <3263>;
+				exit-latency-us = <6562>;
+				min-residency-us = <9987>;
+			};
+		};
+	};
+
+	dummy_eud: dummy-sink {
+		compatible = "arm,coresight-dummy-sink";
+
+		in-ports {
+			port {
+				eud_in: endpoint {
+					remote-endpoint = <&swao_rep_out1>;
+				};
+			};
+		};
+	};
+
+	firmware {
+		scm: scm {
+			compatible = "qcom,scm-qcs8300", "qcom,scm";
+			qcom,dload-mode = <&tcsr 0x13000>;
+		};
+	};
+
+	memory@80000000 {
+		device_type = "memory";
+		/* We expect the bootloader to fill in the size */
+		reg = <0x0 0x80000000 0x0 0x0>;
+	};
+
+	clk_virt: interconnect-0 {
+		compatible = "qcom,qcs8300-clk-virt";
+		#interconnect-cells = <2>;
+		qcom,bcm-voters = <&apps_bcm_voter>;
+	};
+
+	mc_virt: interconnect-1 {
+		compatible = "qcom,qcs8300-mc-virt";
+		#interconnect-cells = <2>;
+		qcom,bcm-voters = <&apps_bcm_voter>;
+	};
+
+	pmu-a55 {
+		compatible = "arm,cortex-a55-pmu";
+		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
+	};
+
+	pmu-a78 {
+		compatible = "arm,cortex-a78-pmu";
+		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
+	};
+
+	psci {
+		compatible = "arm,psci-1.0";
+		method = "smc";
+
+		cpu_pd0: power-domain-cpu0 {
+			#power-domain-cells = <0>;
+			power-domains = <&cluster_pd0>;
+			domain-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>;
+		};
+
+		cpu_pd1: power-domain-cpu1 {
+			#power-domain-cells = <0>;
+			power-domains = <&cluster_pd0>;
+			domain-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>;
+		};
+
+		cpu_pd2: power-domain-cpu2 {
+			#power-domain-cells = <0>;
+			power-domains = <&cluster_pd0>;
+			domain-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>;
+		};
+
+		cpu_pd3: power-domain-cpu3 {
+			#power-domain-cells = <0>;
+			power-domains = <&cluster_pd0>;
+			domain-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>;
+		};
+
+		cpu_pd4: power-domain-cpu4 {
+			#power-domain-cells = <0>;
+			power-domains = <&cluster_pd1>;
+			domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>;
+		};
+
+		cpu_pd5: power-domain-cpu5 {
+			#power-domain-cells = <0>;
+			power-domains = <&cluster_pd1>;
+			domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>;
+		};
+
+		cpu_pd6: power-domain-cpu6 {
+			#power-domain-cells = <0>;
+			power-domains = <&cluster_pd1>;
+			domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>;
+		};
+
+		cpu_pd7: power-domain-cpu7 {
+			#power-domain-cells = <0>;
+			power-domains = <&cluster_pd1>;
+			domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>;
+		};
+
+		cluster_pd0: power-domain-cluster0 {
+			#power-domain-cells = <0>;
+			power-domains = <&system_pd>;
+			domain-idle-states = <&gold_cluster_sleep>;
+		};
+
+		cluster_pd1: power-domain-cluster1 {
+			#power-domain-cells = <0>;
+			power-domains = <&system_pd>;
+			domain-idle-states = <&silver_cluster_sleep>;
+		};
+
+		system_pd: power-domain-system {
+			#power-domain-cells = <0>;
+			domain-idle-states = <&system_sleep>;
+		};
+	};
+
+	reserved-memory {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		aop_image_mem: aop-image-region@90800000 {
+			reg = <0x0 0x90800000 0x0 0x60000>;
+			no-map;
+		};
+
+		aop_cmd_db_mem: aop-cmd-db-region@90860000 {
+			compatible = "qcom,cmd-db";
+			reg = <0x0 0x90860000 0x0 0x20000>;
+			no-map;
+		};
+
+		smem_mem: smem@90900000 {
+			compatible = "qcom,smem";
+			reg = <0x0 0x90900000 0x0 0x200000>;
+			no-map;
+			hwlocks = <&tcsr_mutex 3>;
+		};
+
+		lpass_machine_learning_mem: lpass-machine-learning-region@93b00000 {
+			reg = <0x0 0x93b00000 0x0 0xf00000>;
+			no-map;
+		};
+
+		adsp_rpc_remote_heap_mem: adsp-rpc-remote-heap-region@94a00000 {
+			reg = <0x0 0x94a00000 0x0 0x800000>;
+			no-map;
+		};
+
+		camera_mem: camera-region@95200000 {
+			reg = <0x0 0x95200000 0x0 0x500000>;
+			no-map;
+		};
+
+		adsp_mem: adsp-region@95c00000 {
+			no-map;
+			reg = <0x0 0x95c00000 0x0 0x1e00000>;
+		};
+
+		q6_adsp_dtb_mem: q6-adsp-dtb-region@97a00000 {
+			reg = <0x0 0x97a00000 0x0 0x80000>;
+			no-map;
+		};
+
+		q6_gpdsp_dtb_mem: q6-gpdsp-dtb-region@97a80000 {
+			reg = <0x0 0x97a80000 0x0 0x80000>;
+			no-map;
+		};
+
+		gpdsp_mem: gpdsp-region@97b00000 {
+			reg = <0x0 0x97b00000 0x0 0x1e00000>;
+			no-map;
+		};
+
+		q6_cdsp_dtb_mem: q6-cdsp-dtb-region@99900000 {
+			reg = <0x0 0x99900000 0x0 0x80000>;
+			no-map;
+		};
+
+		cdsp_mem: cdsp-region@99980000 {
+			reg = <0x0 0x99980000 0x0 0x1e00000>;
+			no-map;
+		};
+
+		gpu_microcode_mem: gpu-microcode-region@9b780000 {
+			reg = <0x0 0x9b780000 0x0 0x2000>;
+			no-map;
+		};
+
+		cvp_mem: cvp-region@9b782000 {
+			reg = <0x0 0x9b782000 0x0 0x700000>;
+			no-map;
+		};
+
+		video_mem: video-region@9be82000 {
+			reg = <0x0 0x9be82000 0x0 0x700000>;
+			no-map;
+		};
+	};
+
+	smp2p-adsp {
+		compatible = "qcom,smp2p";
+		interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
+					     IPCC_MPROC_SIGNAL_SMP2P
+					     IRQ_TYPE_EDGE_RISING>;
+		mboxes = <&ipcc IPCC_CLIENT_LPASS
+				IPCC_MPROC_SIGNAL_SMP2P>;
+
+		qcom,smem = <443>, <429>;
+		qcom,local-pid = <0>;
+		qcom,remote-pid = <2>;
+
+		smp2p_adsp_in: slave-kernel {
+			qcom,entry-name = "slave-kernel";
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		smp2p_adsp_out: master-kernel {
+			qcom,entry-name = "master-kernel";
+			#qcom,smem-state-cells = <1>;
+		};
+	};
+
+	smp2p-cdsp {
+		compatible = "qcom,smp2p";
+		interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
+					     IPCC_MPROC_SIGNAL_SMP2P
+					     IRQ_TYPE_EDGE_RISING>;
+		mboxes = <&ipcc IPCC_CLIENT_CDSP
+				IPCC_MPROC_SIGNAL_SMP2P>;
+
+		qcom,smem = <94>, <432>;
+		qcom,local-pid = <0>;
+		qcom,remote-pid = <5>;
+
+		smp2p_cdsp_in: slave-kernel {
+			qcom,entry-name = "slave-kernel";
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		smp2p_cdsp_out: master-kernel {
+			qcom,entry-name = "master-kernel";
+			#qcom,smem-state-cells = <1>;
+		};
+	};
+
+	smp2p-gpdsp {
+		compatible = "qcom,smp2p";
+		interrupts-extended = <&ipcc IPCC_CLIENT_GPDSP0
+					     IPCC_MPROC_SIGNAL_SMP2P
+					     IRQ_TYPE_EDGE_RISING>;
+		mboxes = <&ipcc IPCC_CLIENT_GPDSP0
+				IPCC_MPROC_SIGNAL_SMP2P>;
+
+		qcom,smem = <617>, <616>;
+		qcom,local-pid = <0>;
+		qcom,remote-pid = <17>;
+
+		smp2p_gpdsp_in: slave-kernel {
+			qcom,entry-name = "slave-kernel";
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		smp2p_gpdsp_out: master-kernel {
+			qcom,entry-name = "master-kernel";
+			#qcom,smem-state-cells = <1>;
+		};
+	};
+
+	soc: soc@0 {
+		compatible = "simple-bus";
+		ranges = <0 0 0 0 0x10 0>;
+		#address-cells = <2>;
+		#size-cells = <2>;
+
+		gcc: clock-controller@100000 {
+			compatible = "qcom,qcs8300-gcc";
+			reg = <0x0 0x00100000 0x0 0xc7018>;
+			#clock-cells = <1>;
+			#reset-cells = <1>;
+			#power-domain-cells = <1>;
+			clocks = <&rpmhcc RPMH_CXO_CLK>,
+				 <&sleep_clk>,
+				 <0>,
+				 <0>,
+				 <0>,
+				 <0>,
+				 <0>,
+				 <0>,
+				 <0>,
+				 <0>;
+		};
+
+		ipcc: mailbox@408000 {
+			compatible = "qcom,qcs8300-ipcc", "qcom,ipcc";
+			reg = <0x0 0x408000 0x0 0x1000>;
+			interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-controller;
+			#interrupt-cells = <3>;
+			#mbox-cells = <2>;
+		};
+
+		qfprom: efuse@784000 {
+			compatible = "qcom,qcs8300-qfprom", "qcom,qfprom";
+			reg = <0x0 0x00784000 0x0 0x1200>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+		};
+
+		qupv3_id_0: geniqup@9c0000 {
+			compatible = "qcom,geni-se-qup";
+			reg = <0x0 0x9c0000 0x0 0x2000>;
+			ranges;
+			clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
+				 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
+			clock-names = "m-ahb",
+				      "s-ahb";
+			#address-cells = <2>;
+			#size-cells = <2>;
+			status = "disabled";
+
+			uart7: serial@99c000 {
+				compatible = "qcom,geni-debug-uart";
+				reg = <0x0 0x0099c000 0x0 0x4000>;
+				clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
+				clock-names = "se";
+				pinctrl-0 = <&qup_uart7_default>;
+				pinctrl-names = "default";
+				interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
+				interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
+						 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
+						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+						 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>;
+				interconnect-names = "qup-core",
+						     "qup-config";
+				status = "disabled";
+			};
+		};
+
+		rng: rng@10d2000 {
+			compatible = "qcom,qcs8300-trng", "qcom,trng";
+			reg = <0x0 0x010d2000 0x0 0x1000>;
+		};
+
+		config_noc: interconnect@14c0000 {
+			compatible = "qcom,qcs8300-config-noc";
+			reg = <0x0 0x014c0000 0x0 0x13080>;
+			#interconnect-cells = <2>;
+			qcom,bcm-voters = <&apps_bcm_voter>;
+		};
+
+		system_noc: interconnect@1680000 {
+			compatible = "qcom,qcs8300-system-noc";
+			reg = <0x0 0x01680000 0x0 0x15080>;
+			#interconnect-cells = <2>;
+			qcom,bcm-voters = <&apps_bcm_voter>;
+		};
+
+		aggre1_noc: interconnect@16c0000 {
+			compatible = "qcom,qcs8300-aggre1-noc";
+			reg = <0x0 0x016c0000 0x0 0x17080>;
+			#interconnect-cells = <2>;
+			qcom,bcm-voters = <&apps_bcm_voter>;
+		};
+
+		aggre2_noc: interconnect@1700000 {
+			compatible = "qcom,qcs8300-aggre2-noc";
+			reg = <0x0 0x01700000 0x0 0x1a080>;
+			#interconnect-cells = <2>;
+			qcom,bcm-voters = <&apps_bcm_voter>;
+		};
+
+		pcie_anoc: interconnect@1760000 {
+			compatible = "qcom,qcs8300-pcie-anoc";
+			reg = <0x0 0x01760000 0x0 0xc080>;
+			#interconnect-cells = <2>;
+			qcom,bcm-voters = <&apps_bcm_voter>;
+		};
+
+		gpdsp_anoc: interconnect@1780000 {
+			compatible = "qcom,qcs8300-gpdsp-anoc";
+			reg = <0x0 0x01780000 0x0 0xd080>;
+			#interconnect-cells = <2>;
+			qcom,bcm-voters = <&apps_bcm_voter>;
+		};
+
+		mmss_noc: interconnect@17a0000 {
+			compatible = "qcom,qcs8300-mmss-noc";
+			reg = <0x0 0x017a0000 0x0 0x40000>;
+			#interconnect-cells = <2>;
+			qcom,bcm-voters = <&apps_bcm_voter>;
+		};
+
+		ufs_mem_hc: ufs@1d84000 {
+			compatible = "qcom,qcs8300-ufshc", "qcom,ufshc", "jedec,ufs-2.0";
+			reg = <0x0 0x01d84000 0x0 0x3000>;
+			interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
+			phys = <&ufs_mem_phy>;
+			phy-names = "ufsphy";
+			lanes-per-direction = <2>;
+			#reset-cells = <1>;
+			resets = <&gcc GCC_UFS_PHY_BCR>;
+			reset-names = "rst";
+
+			power-domains = <&gcc GCC_UFS_PHY_GDSC>;
+			required-opps = <&rpmhpd_opp_nom>;
+
+			iommus = <&apps_smmu 0x100 0x0>;
+			dma-coherent;
+
+			interconnects = <&aggre1_noc MASTER_UFS_MEM QCOM_ICC_TAG_ALWAYS
+					 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
+					<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+					 &config_noc SLAVE_UFS_MEM_CFG QCOM_ICC_TAG_ALWAYS>;
+			interconnect-names = "ufs-ddr",
+					     "cpu-ufs";
+
+			clocks = <&gcc GCC_UFS_PHY_AXI_CLK>,
+				 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
+				 <&gcc GCC_UFS_PHY_AHB_CLK>,
+				 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
+				 <&rpmhcc RPMH_CXO_CLK>,
+				 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
+				 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
+				 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
+			clock-names = "core_clk",
+				      "bus_aggr_clk",
+				      "iface_clk",
+				      "core_clk_unipro",
+				      "ref_clk",
+				      "tx_lane0_sync_clk",
+				      "rx_lane0_sync_clk",
+				      "rx_lane1_sync_clk";
+			freq-table-hz = <75000000 300000000>,
+					<0 0>,
+					<0 0>,
+					<75000000 300000000>,
+					<0 0>,
+					<0 0>,
+					<0 0>,
+					<0 0>;
+			qcom,ice = <&ice>;
+			status = "disabled";
+		};
+
+		ufs_mem_phy: phy@1d87000 {
+			compatible = "qcom,qcs8300-qmp-ufs-phy", "qcom,sa8775p-qmp-ufs-phy";
+			reg = <0x0 0x01d87000 0x0 0xe10>;
+			/*
+			 * Yes, GCC_EDP_REF_CLKREF_EN is correct in qref. It
+			 * enables the CXO clock to eDP *and* UFS PHY.
+			 */
+			clocks = <&rpmhcc RPMH_CXO_CLK>,
+				 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>,
+				 <&gcc GCC_EDP_REF_CLKREF_EN>;
+			clock-names = "ref",
+				      "ref_aux",
+				      "qref";
+			power-domains = <&gcc GCC_UFS_PHY_GDSC>;
+
+			resets = <&ufs_mem_hc 0>;
+			reset-names = "ufsphy";
+
+			#phy-cells = <0>;
+			status = "disabled";
+		};
+
+		cryptobam: dma-controller@1dc4000 {
+			compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
+			reg = <0x0 0x01dc4000 0x0 0x28000>;
+			interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
+			#dma-cells = <1>;
+			qcom,ee = <0>;
+			qcom,controlled-remotely;
+			num-channels = <20>;
+			qcom,num-ees = <4>;
+			iommus = <&apps_smmu 0x480 0x00>,
+				 <&apps_smmu 0x481 0x00>;
+		};
+
+		crypto: crypto@1dfa000 {
+			compatible = "qcom,qcs8300-qce", "qcom,qce";
+			reg = <0x0 0x01dfa000 0x0 0x6000>;
+			dmas = <&cryptobam 4>, <&cryptobam 5>;
+			dma-names = "rx", "tx";
+			iommus = <&apps_smmu 0x480 0x00>,
+				 <&apps_smmu 0x481 0x00>;
+			interconnects = <&aggre2_noc MASTER_CRYPTO_CORE0 QCOM_ICC_TAG_ALWAYS
+					 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+			interconnect-names = "memory";
+		};
+
+		ice: crypto@1d88000 {
+			compatible = "qcom,qcs8300-inline-crypto-engine",
+				     "qcom,inline-crypto-engine";
+			reg = <0x0 0x01d88000 0x0 0x18000>;
+			clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
+		};
+
+		tcsr_mutex: hwlock@1f40000 {
+			compatible = "qcom,tcsr-mutex";
+			reg = <0x0 0x01f40000 0x0 0x20000>;
+			#hwlock-cells = <1>;
+		};
+
+		tcsr: syscon@1fc0000 {
+			compatible = "qcom,qcs8300-tcsr", "syscon";
+			reg = <0x0 0x1fc0000 0x0 0x30000>;
+		};
+
+		remoteproc_adsp: remoteproc@3000000 {
+			compatible = "qcom,qcs8300-adsp-pas", "qcom,sa8775p-adsp-pas";
+			reg = <0x0 0x3000000 0x0 0x00100>;
+
+			interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>,
+					      <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
+					      <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
+					      <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
+					      <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>;
+			interrupt-names = "wdog",
+					  "fatal",
+					  "ready",
+					  "handover",
+					  "stop-ack";
+
+			clocks = <&rpmhcc RPMH_CXO_CLK>;
+			clock-names = "xo";
+
+			power-domains = <&rpmhpd RPMHPD_LCX>,
+					<&rpmhpd RPMHPD_LMX>;
+			power-domain-names = "lcx",
+					     "lmx";
+
+			memory-region = <&adsp_mem>;
+
+			qcom,qmp = <&aoss_qmp>;
+
+			qcom,smem-states = <&smp2p_adsp_out 0>;
+			qcom,smem-state-names = "stop";
+
+			status = "disabled";
+
+			remoteproc_adsp_glink: glink-edge {
+				interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
+							     IPCC_MPROC_SIGNAL_GLINK_QMP
+							     IRQ_TYPE_EDGE_RISING>;
+				mboxes = <&ipcc IPCC_CLIENT_LPASS
+						IPCC_MPROC_SIGNAL_GLINK_QMP>;
+
+				label = "lpass";
+				qcom,remote-pid = <2>;
+
+				fastrpc {
+					compatible = "qcom,fastrpc";
+					qcom,glink-channels = "fastrpcglink-apps-dsp";
+					label = "adsp";
+					memory-region = <&adsp_rpc_remote_heap_mem>;
+					qcom,vmids = <QCOM_SCM_VMID_LPASS
+						      QCOM_SCM_VMID_ADSP_HEAP>;
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					compute-cb@3 {
+						compatible = "qcom,fastrpc-compute-cb";
+						reg = <3>;
+						iommus = <&apps_smmu 0x2003 0x0>;
+						dma-coherent;
+					};
+
+					compute-cb@4 {
+						compatible = "qcom,fastrpc-compute-cb";
+						reg = <4>;
+						iommus = <&apps_smmu 0x2004 0x0>;
+						dma-coherent;
+					};
+
+					compute-cb@5 {
+						compatible = "qcom,fastrpc-compute-cb";
+						reg = <5>;
+						iommus = <&apps_smmu 0x2005 0x0>;
+						dma-coherent;
+					};
+				};
+			};
+		};
+
+		lpass_ag_noc: interconnect@3c40000 {
+			compatible = "qcom,qcs8300-lpass-ag-noc";
+			reg = <0x0 0x03c40000 0x0 0x17200>;
+			#interconnect-cells = <2>;
+			qcom,bcm-voters = <&apps_bcm_voter>;
+		};
+
+		stm@4002000 {
+			compatible = "arm,coresight-stm", "arm,primecell";
+			reg = <0x0 0x04002000 0x0 0x1000>,
+			      <0x0 0x16280000 0x0 0x180000>;
+			reg-names = "stm-base",
+				    "stm-stimulus-base";
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			out-ports {
+				port {
+					stm_out: endpoint {
+						remote-endpoint = <&funnel0_in7>;
+					};
+				};
+			};
+		};
+
+		tpda@4004000 {
+			compatible = "qcom,coresight-tpda", "arm,primecell";
+			reg = <0x0 0x04004000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			in-ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@1 {
+					reg = <1>;
+
+					qdss_tpda_in1: endpoint {
+						remote-endpoint = <&qdss_tpdm1_out>;
+					};
+				};
+			};
+
+			out-ports {
+				port {
+					qdss_tpda_out: endpoint {
+						remote-endpoint = <&funnel0_in6>;
+					};
+				};
+			};
+		};
+
+		tpdm@400f000 {
+			compatible = "qcom,coresight-tpdm", "arm,primecell";
+			reg = <0x0 0x0400f000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			qcom,cmb-element-bits = <32>;
+			qcom,cmb-msrs-num = <32>;
+
+			out-ports {
+				port {
+					qdss_tpdm1_out: endpoint {
+						remote-endpoint = <&qdss_tpda_in1>;
+					};
+				};
+			};
+		};
+
+		funnel@4041000 {
+			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+			reg = <0x0 0x04041000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			in-ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@6 {
+					reg = <6>;
+
+					funnel0_in6: endpoint {
+						remote-endpoint = <&qdss_tpda_out>;
+					};
+				};
+
+				port@7 {
+					reg = <7>;
+
+					funnel0_in7: endpoint {
+						remote-endpoint = <&stm_out>;
+					};
+				};
+			};
+
+			out-ports {
+				port {
+					funnel0_out: endpoint {
+						remote-endpoint = <&qdss_funnel_in0>;
+					};
+				};
+			};
+		};
+
+		funnel@4042000 {
+			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+			reg = <0x0 0x04042000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			in-ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@4 {
+					reg = <4>;
+
+					funnel1_in4: endpoint {
+						remote-endpoint = <&apss_funnel1_out>;
+					};
+				};
+
+				port@5 {
+					reg = <5>;
+
+					funnel1_in5: endpoint {
+						remote-endpoint = <&dlct0_funnel_out>;
+					};
+				};
+
+				port@6 {
+					reg = <6>;
+
+					funnel1_in6: endpoint {
+						remote-endpoint = <&dlmm_funnel_out>;
+					};
+				};
+
+				port@7 {
+					reg = <7>;
+
+					funnel1_in7: endpoint {
+						remote-endpoint = <&dlst_ch_funnel_out>;
+					};
+				};
+			};
+
+			out-ports {
+				port {
+					funnel1_out: endpoint {
+						remote-endpoint = <&qdss_funnel_in1>;
+					};
+				};
+			};
+		};
+
+		funnel@4045000 {
+			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+			reg = <0x0 0x04045000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			in-ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					reg = <0>;
+
+					qdss_funnel_in0: endpoint {
+						remote-endpoint = <&funnel0_out>;
+					};
+				};
+
+				port@1 {
+					reg = <1>;
+
+					qdss_funnel_in1: endpoint {
+						remote-endpoint = <&funnel1_out>;
+					};
+				};
+			};
+
+			out-ports {
+				port {
+					qdss_funnel_out: endpoint {
+						remote-endpoint = <&aoss_funnel_in7>;
+					};
+				};
+			};
+		};
+
+		tpdm@4841000 {
+			compatible = "qcom,coresight-tpdm", "arm,primecell";
+			reg = <0x0 0x04841000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			qcom,cmb-element-bits = <32>;
+			qcom,cmb-msrs-num = <32>;
+
+			out-ports {
+				port {
+					prng_tpdm_out: endpoint {
+						remote-endpoint = <&dlct0_tpda_in19>;
+					};
+				};
+			};
+		};
+
+		tpdm@4850000 {
+			compatible = "qcom,coresight-tpdm", "arm,primecell";
+			reg = <0x0 0x04850000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			qcom,cmb-element-bits = <64>;
+			qcom,cmb-msrs-num = <32>;
+			qcom,dsb-element-bits = <32>;
+			qcom,dsb-msrs-num = <32>;
+
+			out-ports {
+				port {
+					pimem_tpdm_out: endpoint {
+						remote-endpoint = <&dlct0_tpda_in25>;
+					};
+				};
+			};
+		};
+
+		tpdm@4860000 {
+			compatible = "qcom,coresight-tpdm", "arm,primecell";
+			reg = <0x0 0x04860000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			qcom,dsb-element-bits = <32>;
+			qcom,dsb-msrs-num = <32>;
+
+			out-ports {
+				port {
+					dlst_ch_tpdm0_out: endpoint {
+						remote-endpoint = <&dlst_ch_tpda_in8>;
+					};
+				};
+			};
+		};
+
+		tpda@4864000 {
+			compatible = "qcom,coresight-tpda", "arm,primecell";
+			reg = <0x0 0x04864000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			in-ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@8 {
+					reg = <8>;
+
+					dlst_ch_tpda_in8: endpoint {
+						remote-endpoint = <&dlst_ch_tpdm0_out>;
+					};
+				};
+			};
+
+			out-ports {
+				port {
+					dlst_ch_tpda_out: endpoint {
+						remote-endpoint = <&dlst_ch_funnel_in0>;
+					};
+				};
+			};
+		};
+
+		funnel@4865000 {
+			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+			reg = <0x0 0x04865000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			in-ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					reg = <0>;
+
+					dlst_ch_funnel_in0: endpoint {
+						remote-endpoint = <&dlst_ch_tpda_out>;
+					};
+				};
+
+				port@4 {
+					reg = <4>;
+
+					dlst_ch_funnel_in4: endpoint {
+						remote-endpoint = <&dlst_funnel_out>;
+					};
+				};
+
+				port@6 {
+					reg = <6>;
+
+					dlst_ch_funnel_in6: endpoint {
+						remote-endpoint = <&gdsp_funnel_out>;
+					};
+				};
+			};
+
+			out-ports {
+				port {
+					dlst_ch_funnel_out: endpoint {
+						remote-endpoint = <&funnel1_in7>;
+					};
+				};
+			};
+		};
+
+		tpdm@4980000 {
+			compatible = "qcom,coresight-tpdm", "arm,primecell";
+			reg = <0x0 0x04980000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			qcom,dsb-element-bits = <32>;
+			qcom,dsb-msrs-num = <32>;
+
+			out-ports {
+				port {
+					turing2_tpdm_out: endpoint {
+						remote-endpoint = <&turing2_funnel_in0>;
+					};
+				};
+			};
+		};
+
+		funnel@4983000 {
+			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+			reg = <0x0 0x04983000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			in-ports {
+				port {
+					turing2_funnel_in0: endpoint {
+						remote-endpoint = <&turing2_tpdm_out>;
+					};
+				};
+			};
+
+			out-ports {
+				port {
+					turing2_funnel_out0: endpoint {
+						remote-endpoint = <&gdsp_tpda_in5>;
+					};
+				};
+			};
+		};
+
+		tpdm@4ac0000 {
+			compatible = "qcom,coresight-tpdm", "arm,primecell";
+			reg = <0x0 0x04ac0000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			qcom,dsb-element-bits = <32>;
+			qcom,dsb-msrs-num = <32>;
+
+			out-ports {
+				port {
+					dlmm_tpdm0_out: endpoint {
+						remote-endpoint = <&dlmm_tpda_in27>;
+					};
+				};
+			};
+		};
+
+		tpda@4ac4000 {
+			compatible = "qcom,coresight-tpda", "arm,primecell";
+			reg = <0x0 0x04ac4000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			in-ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@1b {
+					reg = <27>;
+
+					dlmm_tpda_in27: endpoint {
+						remote-endpoint = <&dlmm_tpdm0_out>;
+					};
+				};
+			};
+
+			out-ports {
+				port {
+					dlmm_tpda_out: endpoint {
+						remote-endpoint = <&dlmm_funnel_in0>;
+					};
+				};
+			};
+		};
+
+		funnel@4ac5000 {
+			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+			reg = <0x0 0x04ac5000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			in-ports {
+				port {
+					dlmm_funnel_in0: endpoint {
+						remote-endpoint = <&dlmm_tpda_out>;
+					};
+				};
+			};
+
+			out-ports {
+				port {
+					dlmm_funnel_out: endpoint {
+						remote-endpoint = <&funnel1_in6>;
+					};
+				};
+			};
+		};
+
+		tpdm@4ad0000 {
+			compatible = "qcom,coresight-tpdm", "arm,primecell";
+			reg = <0x0 0x04ad0000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			qcom,dsb-element-bits = <32>;
+			qcom,dsb-msrs-num = <32>;
+
+			out-ports {
+				port {
+					dlct0_tpdm0_out: endpoint {
+						remote-endpoint = <&dlct0_tpda_in26>;
+					};
+				};
+			};
+		};
+
+		tpda@4ad3000 {
+			compatible = "qcom,coresight-tpda", "arm,primecell";
+			reg = <0x0 0x04ad3000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			in-ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@13 {
+					reg = <19>;
+
+					dlct0_tpda_in19: endpoint {
+						remote-endpoint = <&prng_tpdm_out>;
+					};
+				};
+
+				port@19 {
+					reg = <25>;
+
+					dlct0_tpda_in25: endpoint {
+						remote-endpoint = <&pimem_tpdm_out>;
+					};
+				};
+
+				port@1a {
+					reg = <26>;
+
+					dlct0_tpda_in26: endpoint {
+						remote-endpoint = <&dlct0_tpdm0_out>;
+					};
+				};
+			};
+
+			out-ports {
+				port {
+					dlct0_tpda_out: endpoint {
+						remote-endpoint = <&dlct0_funnel_in0>;
+					};
+				};
+			};
+		};
+
+		funnel@4ad4000 {
+			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+			reg = <0x0 0x04ad4000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			in-ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					reg = <0>;
+
+					dlct0_funnel_in0: endpoint {
+						remote-endpoint = <&dlct0_tpda_out>;
+					};
+				};
+
+				port@4 {
+					reg = <4>;
+
+					dlct0_funnel_in4: endpoint {
+						remote-endpoint = <&ddr_funnel5_out>;
+					};
+				};
+			};
+
+			out-ports {
+				port {
+					dlct0_funnel_out: endpoint {
+						remote-endpoint = <&funnel1_in5>;
+					};
+				};
+			};
+		};
+
+		funnel@4b04000 {
+			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+			reg = <0x0 0x04b04000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			in-ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@6 {
+					reg = <6>;
+
+					aoss_funnel_in6: endpoint {
+						remote-endpoint = <&aoss_tpda_out>;
+					};
+				};
+
+				port@7 {
+					reg = <7>;
+
+					aoss_funnel_in7: endpoint {
+						remote-endpoint = <&qdss_funnel_out>;
+					};
+				};
+			};
+
+			out-ports {
+				port {
+					aoss_funnel_out: endpoint {
+						remote-endpoint = <&etf0_in>;
+					};
+				};
+			};
+		};
+
+		tmc_etf: tmc@4b05000 {
+			compatible = "arm,coresight-tmc", "arm,primecell";
+			reg = <0x0 0x04b05000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			in-ports {
+				port {
+					etf0_in: endpoint {
+						remote-endpoint = <&aoss_funnel_out>;
+					};
+				};
+			};
+
+			out-ports {
+				port {
+					etf0_out: endpoint {
+						remote-endpoint = <&swao_rep_in>;
+					};
+				};
+			};
+		};
+
+		replicator@4b06000 {
+			compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
+			reg = <0x0 0x04b06000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			in-ports {
+				port {
+					swao_rep_in: endpoint {
+						remote-endpoint = <&etf0_out>;
+					};
+				};
+			};
+
+			out-ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@1 {
+					reg = <1>;
+
+					swao_rep_out1: endpoint {
+						remote-endpoint = <&eud_in>;
+					};
+				};
+			};
+		};
+
+		tpda@4b08000 {
+			compatible = "qcom,coresight-tpda", "arm,primecell";
+			reg = <0x0 0x04b08000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			in-ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					reg = <0>;
+
+					aoss_tpda_in0: endpoint {
+						remote-endpoint = <&aoss_tpdm0_out>;
+					};
+				};
+
+				port@1 {
+					reg = <1>;
+
+					aoss_tpda_in1: endpoint {
+						remote-endpoint = <&aoss_tpdm1_out>;
+					};
+				};
+
+				port@2 {
+					reg = <2>;
+
+					aoss_tpda_in2: endpoint {
+						remote-endpoint = <&aoss_tpdm2_out>;
+					};
+				};
+
+				port@3 {
+					reg = <3>;
+
+					aoss_tpda_in3: endpoint {
+						remote-endpoint = <&aoss_tpdm3_out>;
+					};
+				};
+
+				port@4 {
+					reg = <4>;
+
+					aoss_tpda_in4: endpoint {
+						remote-endpoint = <&aoss_tpdm4_out>;
+					};
+				};
+			};
+
+			out-ports {
+				port {
+					aoss_tpda_out: endpoint {
+						remote-endpoint = <&aoss_funnel_in6>;
+					};
+				};
+			};
+		};
+
+		tpdm@4b09000 {
+			compatible = "qcom,coresight-tpdm", "arm,primecell";
+			reg = <0x0 0x04b09000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			qcom,cmb-element-bits = <64>;
+			qcom,cmb-msrs-num = <32>;
+
+			out-ports {
+				port {
+					aoss_tpdm0_out: endpoint {
+						remote-endpoint = <&aoss_tpda_in0>;
+					};
+				};
+			};
+		};
+
+		tpdm@4b0a000 {
+			compatible = "qcom,coresight-tpdm", "arm,primecell";
+			reg = <0x0 0x04b0a000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			qcom,cmb-element-bits = <64>;
+			qcom,cmb-msrs-num = <32>;
+
+			out-ports {
+				port {
+					aoss_tpdm1_out: endpoint {
+						remote-endpoint = <&aoss_tpda_in1>;
+					};
+				};
+			};
+		};
+
+		tpdm@4b0b000 {
+			compatible = "qcom,coresight-tpdm", "arm,primecell";
+			reg = <0x0 0x04b0b000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			qcom,cmb-element-bits = <64>;
+			qcom,cmb-msrs-num = <32>;
+
+			out-ports {
+				port {
+					aoss_tpdm2_out: endpoint {
+						remote-endpoint = <&aoss_tpda_in2>;
+					};
+				};
+			};
+		};
+
+		tpdm@4b0c000 {
+			compatible = "qcom,coresight-tpdm", "arm,primecell";
+			reg = <0x0 0x04b0c000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			qcom,cmb-element-bits = <64>;
+			qcom,cmb-msrs-num = <32>;
+
+			out-ports {
+				port {
+					aoss_tpdm3_out: endpoint {
+						remote-endpoint = <&aoss_tpda_in3>;
+					};
+				};
+			};
+		};
+
+		tpdm@4b0d000 {
+			compatible = "qcom,coresight-tpdm", "arm,primecell";
+			reg = <0x0 0x04b0d000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			qcom,dsb-element-bits = <32>;
+			qcom,dsb-msrs-num = <32>;
+
+			out-ports {
+				port {
+					aoss_tpdm4_out: endpoint {
+						remote-endpoint = <&aoss_tpda_in4>;
+					};
+				};
+			};
+		};
+
+		cti@4b13000 {
+			compatible = "arm,coresight-cti", "arm,primecell";
+			reg = <0x0 0x04b13000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+		};
+
+		tpdm@4b80000 {
+			compatible = "qcom,coresight-tpdm", "arm,primecell";
+			reg = <0x0 0x04b80000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			qcom,dsb-element-bits = <32>;
+			qcom,dsb-msrs-num = <32>;
+
+			out-ports {
+				port {
+					turing0_tpdm0_out: endpoint {
+						remote-endpoint = <&turing0_tpda_in0>;
+					};
+				};
+			};
+		};
+
+		tpda@4b86000 {
+			compatible = "qcom,coresight-tpda", "arm,primecell";
+			reg = <0x0 0x04b86000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			in-ports {
+				port {
+					turing0_tpda_in0: endpoint {
+						remote-endpoint = <&turing0_tpdm0_out>;
+					};
+				};
+			};
+
+			out-ports {
+				port {
+					turing0_tpda_out: endpoint {
+						remote-endpoint = <&turing0_funnel_in0>;
+					};
+				};
+			};
+		};
+
+		funnel@4b87000 {
+			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+			reg = <0x0 0x04b87000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			in-ports {
+				port {
+					turing0_funnel_in0: endpoint {
+						remote-endpoint = <&turing0_tpda_out>;
+					};
+				};
+			};
+
+			out-ports {
+				port {
+					turing0_funnel_out: endpoint {
+						remote-endpoint = <&gdsp_funnel_in4>;
+					};
+				};
+			};
+		};
+
+		cti@4b8b000 {
+			compatible = "arm,coresight-cti", "arm,primecell";
+			reg = <0x0 0x04b8b000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+		};
+
+		tpdm@4c40000 {
+			compatible = "qcom,coresight-tpdm", "arm,primecell";
+			reg = <0x0 0x04c40000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			qcom,dsb-element-bits = <32>;
+			qcom,dsb-msrs-num = <32>;
+
+			out-ports {
+				port {
+					gdsp_tpdm0_out: endpoint {
+						remote-endpoint = <&gdsp_tpda_in8>;
+					};
+				};
+			};
+		};
+
+		tpda@4c44000 {
+			compatible = "qcom,coresight-tpda", "arm,primecell";
+			reg = <0x0 0x04c44000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			in-ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@5 {
+					reg = <5>;
+
+					gdsp_tpda_in5: endpoint {
+						remote-endpoint = <&turing2_funnel_out0>;
+					};
+				};
+
+				port@8 {
+					reg = <8>;
+
+					gdsp_tpda_in8: endpoint {
+						remote-endpoint = <&gdsp_tpdm0_out>;
+					};
+				};
+			};
+
+			out-ports {
+				port {
+					gdsp_tpda_out: endpoint {
+						remote-endpoint = <&gdsp_funnel_in0>;
+					};
+				};
+			};
+		};
+
+		funnel@4c45000 {
+			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+			reg = <0x0 0x04c45000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			in-ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					reg = <0>;
+
+					gdsp_funnel_in0: endpoint {
+						remote-endpoint = <&gdsp_tpda_out>;
+					};
+				};
+
+				port@4 {
+					reg = <4>;
+
+					gdsp_funnel_in4: endpoint {
+						remote-endpoint = <&turing0_funnel_out>;
+					};
+				};
+			};
+
+			out-ports {
+				port {
+					gdsp_funnel_out: endpoint {
+						remote-endpoint = <&dlst_ch_funnel_in6>;
+					};
+				};
+			};
+		};
+
+		tpdm@4c50000 {
+			compatible = "qcom,coresight-tpdm", "arm,primecell";
+			reg = <0x0 0x04c50000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			qcom,dsb-element-bits = <32>;
+			qcom,dsb-msrs-num = <32>;
+
+			out-ports {
+				port {
+					dlst_tpdm0_out: endpoint {
+						remote-endpoint = <&dlst_tpda_in8>;
+					};
+				};
+			};
+		};
+
+		tpda@4c54000 {
+			compatible = "qcom,coresight-tpda", "arm,primecell";
+			reg = <0x0 0x04c54000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			in-ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@8 {
+					reg = <8>;
+
+					dlst_tpda_in8: endpoint {
+						remote-endpoint = <&dlst_tpdm0_out>;
+					};
+				};
+			};
+
+			out-ports {
+				port {
+					dlst_tpda_out: endpoint {
+						remote-endpoint = <&dlst_funnel_in0>;
+					};
+				};
+			};
+		};
+
+		funnel@4c55000 {
+			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+			reg = <0x0 0x04c55000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			in-ports {
+				port {
+					dlst_funnel_in0: endpoint {
+						remote-endpoint = <&dlst_tpda_out>;
+					};
+				};
+			};
+
+			out-ports {
+				port {
+					dlst_funnel_out: endpoint {
+						remote-endpoint = <&dlst_ch_funnel_in4>;
+					};
+				};
+			};
+		};
+
+		tpdm@4e00000 {
+			compatible = "qcom,coresight-tpdm", "arm,primecell";
+			reg = <0x0 0x04e00000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			qcom,dsb-element-bits = <32>;
+			qcom,dsb-msrs-num = <32>;
+			qcom,cmb-element-bits = <32>;
+			qcom,cmb-msrs-num = <32>;
+
+			out-ports {
+				port {
+					ddr_tpdm3_out: endpoint {
+						remote-endpoint = <&ddr_tpda_in4>;
+					};
+				};
+			};
+		};
+
+		tpda@4e03000 {
+			compatible = "qcom,coresight-tpda", "arm,primecell";
+			reg = <0x0 0x04e03000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			in-ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					reg = <0>;
+
+					ddr_tpda_in0: endpoint {
+						remote-endpoint = <&ddr_funnel0_out0>;
+					};
+				};
+
+				port@1 {
+					reg = <1>;
+
+					ddr_tpda_in1: endpoint {
+						remote-endpoint = <&ddr_funnel1_out0>;
+					};
+				};
+
+				port@4 {
+					reg = <4>;
+
+					ddr_tpda_in4: endpoint {
+						remote-endpoint = <&ddr_tpdm3_out>;
+					};
+				};
+			};
+
+			out-ports {
+				port {
+					ddr_tpda_out: endpoint {
+						remote-endpoint = <&ddr_funnel5_in0>;
+					};
+				};
+			};
+		};
+
+		funnel@4e04000 {
+			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+			reg = <0x0 0x04e04000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			in-ports {
+				port {
+					ddr_funnel5_in0: endpoint {
+						remote-endpoint = <&ddr_tpda_out>;
+					};
+				};
+			};
+
+			out-ports {
+				port {
+					ddr_funnel5_out: endpoint {
+						remote-endpoint = <&dlct0_funnel_in4>;
+					};
+				};
+			};
+		};
+
+		tpdm@4e10000 {
+			compatible = "qcom,coresight-tpdm", "arm,primecell";
+			reg = <0x0 0x04e10000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			qcom,dsb-element-bits = <32>;
+			qcom,dsb-msrs-num = <32>;
+
+			out-ports {
+				port {
+					ddr_tpdm0_out: endpoint {
+						remote-endpoint = <&ddr_funnel0_in0>;
+					};
+				};
+			};
+		};
+
+		funnel@4e12000 {
+			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+			reg = <0x0 0x04e12000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			in-ports {
+				port {
+					ddr_funnel0_in0: endpoint {
+						remote-endpoint = <&ddr_tpdm0_out>;
+					};
+				};
+			};
+
+			out-ports {
+				port {
+					ddr_funnel0_out0: endpoint {
+						remote-endpoint = <&ddr_tpda_in0>;
+					};
+				};
+			};
+		};
+
+		tpdm@4e20000 {
+			compatible = "qcom,coresight-tpdm", "arm,primecell";
+			reg = <0x0 0x04e20000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			qcom,dsb-element-bits = <32>;
+			qcom,dsb-msrs-num = <32>;
+
+			out-ports {
+				port {
+					ddr_tpdm1_out: endpoint {
+						remote-endpoint = <&ddr_funnel1_in0>;
+					};
+				};
+			};
+		};
+
+		funnel@4e22000 {
+			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+			reg = <0x0 0x04e22000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			in-ports {
+				port {
+					ddr_funnel1_in0: endpoint {
+						remote-endpoint = <&ddr_tpdm1_out>;
+					};
+				};
+			};
+
+			out-ports {
+				port {
+					ddr_funnel1_out0: endpoint {
+						remote-endpoint = <&ddr_tpda_in1>;
+					};
+				};
+			};
+		};
+
+		etm@6040000 {
+			compatible = "arm,primecell";
+			reg = <0x0 0x06040000 0x0 0x1000>;
+			cpu = <&cpu0>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			arm,coresight-loses-context-with-cpu;
+			qcom,skip-power-up;
+
+			out-ports {
+				port {
+					etm0_out: endpoint {
+						remote-endpoint = <&apss_funnel0_in0>;
+					};
+				};
+			};
+		};
+
+		etm@6140000 {
+			compatible = "arm,primecell";
+			reg = <0x0 0x06140000 0x0 0x1000>;
+			cpu = <&cpu1>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			arm,coresight-loses-context-with-cpu;
+			qcom,skip-power-up;
+
+			out-ports {
+				port {
+					etm1_out: endpoint {
+						remote-endpoint = <&apss_funnel0_in1>;
+					};
+				};
+			};
+		};
+
+		etm@6240000 {
+			compatible = "arm,primecell";
+			reg = <0x0 0x06240000 0x0 0x1000>;
+			cpu = <&cpu2>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			arm,coresight-loses-context-with-cpu;
+			qcom,skip-power-up;
+
+			out-ports {
+				port {
+					etm2_out: endpoint {
+						remote-endpoint = <&apss_funnel0_in2>;
+					};
+				};
+			};
+		};
+
+		etm@6340000 {
+			compatible = "arm,primecell";
+			reg = <0x0 0x06340000 0x0 0x1000>;
+			cpu = <&cpu3>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			arm,coresight-loses-context-with-cpu;
+			qcom,skip-power-up;
+
+			out-ports {
+				port {
+					etm3_out: endpoint {
+						remote-endpoint = <&apss_funnel0_in3>;
+					};
+				};
+			};
+		};
+
+		etm@6440000 {
+			compatible = "arm,primecell";
+			reg = <0x0 0x06440000 0x0 0x1000>;
+			cpu = <&cpu4>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			arm,coresight-loses-context-with-cpu;
+			qcom,skip-power-up;
+
+			out-ports {
+				port {
+					etm4_out: endpoint {
+						remote-endpoint = <&apss_funnel0_in4>;
+					};
+				};
+			};
+		};
+
+		etm@6540000 {
+			compatible = "arm,primecell";
+			reg = <0x0 0x06540000 0x0 0x1000>;
+			cpu = <&cpu5>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			arm,coresight-loses-context-with-cpu;
+			qcom,skip-power-up;
+
+			out-ports {
+				port {
+					etm5_out: endpoint {
+						remote-endpoint = <&apss_funnel0_in5>;
+					};
+				};
+			};
+		};
+
+		etm@6640000 {
+			compatible = "arm,primecell";
+			reg = <0x0 0x06640000 0x0 0x1000>;
+			cpu = <&cpu6>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			arm,coresight-loses-context-with-cpu;
+			qcom,skip-power-up;
+
+			out-ports {
+				port {
+					etm6_out: endpoint {
+						remote-endpoint = <&apss_funnel0_in6>;
+					};
+				};
+			};
+		};
+
+		etm@6740000 {
+			compatible = "arm,primecell";
+			reg = <0x0 0x06740000 0x0 0x1000>;
+			cpu = <&cpu7>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			arm,coresight-loses-context-with-cpu;
+			qcom,skip-power-up;
+
+			out-ports {
+				port {
+					etm7_out: endpoint {
+						remote-endpoint = <&apss_funnel0_in7>;
+					};
+				};
+			};
+		};
+
+		funnel@6800000 {
+			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+			reg = <0x0 0x06800000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			in-ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					reg = <0>;
+
+					apss_funnel0_in0: endpoint {
+						remote-endpoint = <&etm0_out>;
+					};
+				};
+
+				port@1 {
+					reg = <1>;
+
+					apss_funnel0_in1: endpoint {
+						remote-endpoint = <&etm1_out>;
+					};
+				};
+
+				port@2 {
+					reg = <2>;
+
+					apss_funnel0_in2: endpoint {
+						remote-endpoint = <&etm2_out>;
+					};
+				};
+
+				port@3 {
+					reg = <3>;
+
+					apss_funnel0_in3: endpoint {
+						remote-endpoint = <&etm3_out>;
+					};
+				};
+
+				port@4 {
+					reg = <4>;
+
+					apss_funnel0_in4: endpoint {
+						remote-endpoint = <&etm4_out>;
+					};
+				};
+
+				port@5 {
+					reg = <5>;
+
+					apss_funnel0_in5: endpoint {
+						remote-endpoint = <&etm5_out>;
+					};
+				};
+
+				port@6 {
+					reg = <6>;
+
+					apss_funnel0_in6: endpoint {
+						remote-endpoint = <&etm6_out>;
+					};
+				};
+
+				port@7 {
+					reg = <7>;
+
+					apss_funnel0_in7: endpoint {
+						remote-endpoint = <&etm7_out>;
+					};
+				};
+			};
+
+			out-ports {
+				port {
+					apss_funnel0_out: endpoint {
+						remote-endpoint = <&apss_funnel1_in0>;
+					};
+				};
+			};
+		};
+
+		funnel@6810000 {
+			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+			reg = <0x0 0x06810000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			in-ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					reg = <0>;
+
+					apss_funnel1_in0: endpoint {
+						remote-endpoint = <&apss_funnel0_out>;
+					};
+				};
+
+				port@3 {
+					reg = <3>;
+
+					apss_funnel1_in3: endpoint {
+						remote-endpoint = <&apss_tpda_out>;
+					};
+				};
+			};
+
+			out-ports {
+				port {
+					apss_funnel1_out: endpoint {
+						remote-endpoint = <&funnel1_in4>;
+					};
+				};
+			};
+		};
+
+		cti@682b000 {
+			compatible = "arm,coresight-cti", "arm,primecell";
+			reg = <0x0 0x0682b000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+		};
+
+		tpdm@6860000 {
+			compatible = "qcom,coresight-tpdm", "arm,primecell";
+			reg = <0x0 0x06860000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			qcom,cmb-element-bits = <64>;
+			qcom,cmb-msrs-num = <32>;
+
+			out-ports {
+				port {
+					apss_tpdm3_out: endpoint {
+						remote-endpoint = <&apss_tpda_in3>;
+					};
+				};
+			};
+		};
+
+		tpdm@6861000 {
+			compatible = "qcom,coresight-tpdm", "arm,primecell";
+			reg = <0x0 0x06861000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			qcom,dsb-element-bits = <32>;
+			qcom,dsb-msrs-num = <32>;
+
+			out-ports {
+				port {
+					apss_tpdm4_out: endpoint {
+						remote-endpoint = <&apss_tpda_in4>;
+					};
+				};
+			};
+		};
+
+		tpda@6863000 {
+			compatible = "qcom,coresight-tpda", "arm,primecell";
+			reg = <0x0 0x06863000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			in-ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					reg = <0>;
+
+					apss_tpda_in0: endpoint {
+						remote-endpoint = <&apss_tpdm0_out>;
+					};
+				};
+
+				port@1 {
+					reg = <1>;
+
+					apss_tpda_in1: endpoint {
+						remote-endpoint = <&apss_tpdm1_out>;
+					};
+				};
+
+				port@2 {
+					reg = <2>;
+
+					apss_tpda_in2: endpoint {
+						remote-endpoint = <&apss_tpdm2_out>;
+					};
+				};
+
+				port@3 {
+					reg = <3>;
+
+					apss_tpda_in3: endpoint {
+						remote-endpoint = <&apss_tpdm3_out>;
+					};
+				};
+
+				port@4 {
+					reg = <4>;
+
+					apss_tpda_in4: endpoint {
+						remote-endpoint = <&apss_tpdm4_out>;
+					};
+				};
+			};
+
+			out-ports {
+				port {
+					apss_tpda_out: endpoint {
+						remote-endpoint = <&apss_funnel1_in3>;
+					};
+				};
+			};
+		};
+
+		tpdm@68a0000 {
+			compatible = "qcom,coresight-tpdm", "arm,primecell";
+			reg = <0x0 0x068a0000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			qcom,cmb-element-bits = <32>;
+			qcom,cmb-msrs-num = <32>;
+
+			out-ports {
+				port {
+					apss_tpdm1_out: endpoint {
+						remote-endpoint = <&apss_tpda_in1>;
+					};
+				};
+			};
+		};
+
+		tpdm@68b0000 {
+			compatible = "qcom,coresight-tpdm", "arm,primecell";
+			reg = <0x0 0x068b0000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			qcom,cmb-element-bits = <32>;
+			qcom,cmb-msrs-num = <32>;
+
+			out-ports {
+				port {
+					apss_tpdm0_out: endpoint {
+						remote-endpoint = <&apss_tpda_in0>;
+					};
+				};
+			};
+		};
+
+		tpdm@68c0000 {
+			compatible = "qcom,coresight-tpdm", "arm,primecell";
+			reg = <0x0 0x068c0000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			qcom,dsb-element-bits = <32>;
+			qcom,dsb-msrs-num = <32>;
+
+			out-ports {
+				port {
+					apss_tpdm2_out: endpoint {
+						remote-endpoint = <&apss_tpda_in2>;
+					};
+				};
+			};
+		};
+
+		cti@68e0000 {
+			compatible = "arm,coresight-cti", "arm,primecell";
+			reg = <0x0 0x068e0000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+		};
+
+		cti@68f0000 {
+			compatible = "arm,coresight-cti", "arm,primecell";
+			reg = <0x0 0x068f0000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+		};
+
+		cti@6900000 {
+			compatible = "arm,coresight-cti", "arm,primecell";
+			reg = <0x0 0x06900000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+		};
+
+		usb_1_hsphy: phy@8904000 {
+			compatible = "qcom,qcs8300-usb-hs-phy",
+				     "qcom,usb-snps-hs-7nm-phy";
+			reg = <0x0 0x08904000 0x0 0x400>;
+
+			clocks = <&rpmhcc RPMH_CXO_CLK>;
+			clock-names = "ref";
+
+			resets = <&gcc GCC_USB2_PHY_PRIM_BCR>;
+
+			#phy-cells = <0>;
+
+			status = "disabled";
+		};
+
+		usb_2_hsphy: phy@8906000 {
+			compatible = "qcom,qcs8300-usb-hs-phy",
+				     "qcom,usb-snps-hs-7nm-phy";
+			reg = <0x0 0x08906000 0x0 0x400>;
+
+			clocks = <&rpmhcc RPMH_CXO_CLK>;
+			clock-names = "ref";
+
+			resets = <&gcc GCC_USB2_PHY_SEC_BCR>;
+
+			#phy-cells = <0>;
+
+			status = "disabled";
+		};
+
+		usb_qmpphy: phy@8907000 {
+			compatible = "qcom,qcs8300-qmp-usb3-uni-phy";
+			reg = <0x0 0x08907000 0x0 0x2000>;
+
+			clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
+				 <&gcc GCC_USB_CLKREF_EN>,
+				 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
+				 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
+			clock-names = "aux",
+				      "ref",
+				      "com_aux",
+				      "pipe";
+
+			resets = <&gcc GCC_USB3_PHY_PRIM_BCR>,
+				 <&gcc GCC_USB3PHY_PHY_PRIM_BCR>;
+			reset-names = "phy", "phy_phy";
+
+			power-domains = <&gcc GCC_USB30_PRIM_GDSC>;
+
+			#clock-cells = <0>;
+			clock-output-names = "usb3_prim_phy_pipe_clk_src";
+
+			#phy-cells = <0>;
+
+			status = "disabled";
+		};
+
+		serdes0: phy@8909000 {
+			compatible = "qcom,qcs8300-dwmac-sgmii-phy", "qcom,sa8775p-dwmac-sgmii-phy";
+			reg = <0x0 0x08909000 0x0 0x00000e10>;
+			clocks = <&gcc GCC_SGMI_CLKREF_EN>;
+			clock-names = "sgmi_ref";
+			#phy-cells = <0>;
+			status = "disabled";
+		};
+
+		gpucc: clock-controller@3d90000 {
+			compatible = "qcom,qcs8300-gpucc";
+			reg = <0x0 0x03d90000 0x0 0xa000>;
+			clocks = <&rpmhcc RPMH_CXO_CLK>,
+				 <&gcc GCC_GPU_GPLL0_CLK_SRC>,
+				 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
+			clock-names = "bi_tcxo",
+				      "gcc_gpu_gpll0_clk_src",
+				      "gcc_gpu_gpll0_div_clk_src";
+			#clock-cells = <1>;
+			#reset-cells = <1>;
+			#power-domain-cells = <1>;
+		};
+
+		pmu@9091000 {
+			compatible = "qcom,qcs8300-llcc-bwmon", "qcom,sc7280-llcc-bwmon";
+			reg = <0x0 0x9091000 0x0 0x1000>;
+
+			interrupts = <GIC_SPI 620 IRQ_TYPE_LEVEL_HIGH>;
+
+			interconnects = <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY
+					 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>;
+
+			operating-points-v2 = <&llcc_bwmon_opp_table>;
+
+			llcc_bwmon_opp_table: opp-table {
+				compatible = "operating-points-v2";
+
+				opp-0 {
+					opp-peak-kBps = <762000>;
+				};
+
+				opp-1 {
+					opp-peak-kBps = <1720000>;
+				};
+
+				opp-2 {
+					opp-peak-kBps = <2086000>;
+				};
+
+				opp-3 {
+					opp-peak-kBps = <2601000>;
+				};
+
+				opp-4 {
+					opp-peak-kBps = <2929000>;
+				};
+
+				opp-5 {
+					opp-peak-kBps = <5931000>;
+				};
+
+				opp-6 {
+					opp-peak-kBps = <6515000>;
+				};
+
+				opp-7 {
+					opp-peak-kBps = <7984000>;
+				};
+
+				opp-8 {
+					opp-peak-kBps = <10437000>;
+				};
+
+				opp-9 {
+					opp-peak-kBps = <12195000>;
+				};
+			};
+		};
+
+		pmu@90b5400 {
+			compatible = "qcom,qcs8300-cpu-bwmon", "qcom,sdm845-bwmon";
+			reg = <0x0 0x90b5400 0x0 0x600>;
+			interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>;
+			interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+					 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>;
+
+			operating-points-v2 = <&cpu_bwmon_opp_table>;
+
+			cpu_bwmon_opp_table: opp-table {
+				compatible = "operating-points-v2";
+
+				opp-0 {
+					opp-peak-kBps = <9155000>;
+				};
+
+				opp-1 {
+					opp-peak-kBps = <12298000>;
+				};
+
+				opp-2 {
+					opp-peak-kBps = <14236000>;
+				};
+
+				opp-3 {
+					opp-peak-kBps = <16265000>;
+				};
+			};
+		};
+
+		pmu@90b6400 {
+			compatible = "qcom,qcs8300-cpu-bwmon", "qcom,sdm845-bwmon";
+			reg = <0x0 0x90b6400 0x0 0x600>;
+			interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>;
+			interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+					 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>;
+
+			operating-points-v2 = <&cpu_bwmon_opp_table>;
+		};
+
+		dc_noc: interconnect@90e0000 {
+			compatible = "qcom,qcs8300-dc-noc";
+			reg = <0x0 0x090e0000 0x0 0x5080>;
+			#interconnect-cells = <2>;
+			qcom,bcm-voters = <&apps_bcm_voter>;
+		};
+
+		gem_noc: interconnect@9100000 {
+			compatible = "qcom,qcs8300-gem-noc";
+			reg = <0x0 0x9100000 0x0 0xf7080>;
+			#interconnect-cells = <2>;
+			qcom,bcm-voters = <&apps_bcm_voter>;
+		};
+
+		llcc: system-cache-controller@9200000 {
+			compatible = "qcom,qcs8300-llcc";
+			reg = <0x0 0x09200000 0x0 0x80000>,
+			      <0x0 0x09300000 0x0 0x80000>,
+			      <0x0 0x09400000 0x0 0x80000>,
+			      <0x0 0x09500000 0x0 0x80000>,
+			      <0x0 0x09a00000 0x0 0x80000>;
+			reg-names = "llcc0_base",
+				    "llcc1_base",
+				    "llcc2_base",
+				    "llcc3_base",
+				    "llcc_broadcast_base";
+			interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
+		};
+
+		usb_1: usb@a6f8800 {
+			compatible = "qcom,qcs8300-dwc3", "qcom,dwc3";
+			reg = <0x0 0x0a6f8800 0x0 0x400>;
+
+			clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
+				 <&gcc GCC_USB30_PRIM_MASTER_CLK>,
+				 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
+				 <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
+				 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>;
+			clock-names = "cfg_noc",
+				      "core",
+				      "iface",
+				      "sleep",
+				      "mock_utmi";
+
+			assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
+					  <&gcc GCC_USB30_PRIM_MASTER_CLK>;
+			assigned-clock-rates = <19200000>, <200000000>;
+
+			interrupts-extended = <&intc GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>,
+					      <&intc GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
+					      <&pdc 14 IRQ_TYPE_EDGE_BOTH>,
+					      <&pdc 15 IRQ_TYPE_EDGE_BOTH>,
+					      <&pdc 12 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "pwr_event",
+					  "hs_phy_irq",
+					  "dp_hs_phy_irq",
+					  "dm_hs_phy_irq",
+					  "ss_phy_irq";
+
+			power-domains = <&gcc GCC_USB30_PRIM_GDSC>;
+			required-opps = <&rpmhpd_opp_nom>;
+
+			resets = <&gcc GCC_USB30_PRIM_BCR>;
+			interconnects = <&aggre1_noc MASTER_USB3_0 QCOM_ICC_TAG_ALWAYS
+					 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
+					<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+					 &config_noc SLAVE_USB3_0 QCOM_ICC_TAG_ALWAYS>;
+			interconnect-names = "usb-ddr", "apps-usb";
+
+			wakeup-source;
+
+			#address-cells = <2>;
+			#size-cells = <2>;
+			ranges;
+
+			status = "disabled";
+
+			usb_1_dwc3: usb@a600000 {
+				compatible = "snps,dwc3";
+				reg = <0x0 0x0a600000 0x0 0xe000>;
+				interrupts = <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>;
+				iommus = <&apps_smmu 0x80 0x0>;
+				phys = <&usb_1_hsphy>, <&usb_qmpphy>;
+				phy-names = "usb2-phy", "usb3-phy";
+				snps,dis_enblslpm_quirk;
+				snps,dis-u1-entry-quirk;
+				snps,dis-u2-entry-quirk;
+				snps,dis_u2_susphy_quirk;
+				snps,dis_u3_susphy_quirk;
+			};
+		};
+
+		usb_2: usb@a4f8800 {
+			compatible = "qcom,qcs8300-dwc3", "qcom,dwc3";
+			reg = <0x0 0x0a4f8800 0x0 0x400>;
+
+			clocks = <&gcc GCC_CFG_NOC_USB2_PRIM_AXI_CLK>,
+				 <&gcc GCC_USB20_MASTER_CLK>,
+				 <&gcc GCC_AGGRE_USB2_PRIM_AXI_CLK>,
+				 <&gcc GCC_USB20_SLEEP_CLK>,
+				 <&gcc GCC_USB20_MOCK_UTMI_CLK>;
+			clock-names = "cfg_noc",
+				      "core",
+				      "iface",
+				      "sleep",
+				      "mock_utmi";
+
+			assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>,
+					  <&gcc GCC_USB20_MASTER_CLK>;
+			assigned-clock-rates = <19200000>, <120000000>;
+
+			interrupts-extended = <&intc GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>,
+					      <&intc GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>,
+					      <&pdc 10 IRQ_TYPE_EDGE_BOTH>,
+					      <&pdc 9 IRQ_TYPE_EDGE_BOTH>;
+			interrupt-names = "pwr_event",
+					  "hs_phy_irq",
+					  "dp_hs_phy_irq",
+					  "dm_hs_phy_irq";
+
+			power-domains = <&gcc GCC_USB20_PRIM_GDSC>;
+			required-opps = <&rpmhpd_opp_nom>;
+
+			resets = <&gcc GCC_USB20_PRIM_BCR>;
+
+			interconnects = <&aggre1_noc MASTER_USB2 QCOM_ICC_TAG_ALWAYS
+					 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
+					<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+					 &config_noc SLAVE_USB2 QCOM_ICC_TAG_ALWAYS>;
+			interconnect-names = "usb-ddr", "apps-usb";
+
+			qcom,select-utmi-as-pipe-clk;
+			wakeup-source;
+
+			#address-cells = <2>;
+			#size-cells = <2>;
+			ranges;
+
+			status = "disabled";
+
+			usb_2_dwc3: usb@a400000 {
+				compatible = "snps,dwc3";
+				reg = <0x0 0x0a400000 0x0 0xe000>;
+
+				interrupts = <GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>;
+				iommus = <&apps_smmu 0x20 0x0>;
+
+				phys = <&usb_2_hsphy>;
+				phy-names = "usb2-phy";
+				maximum-speed = "high-speed";
+
+				snps,dis-u1-entry-quirk;
+				snps,dis-u2-entry-quirk;
+				snps,dis_u2_susphy_quirk;
+				snps,dis_u3_susphy_quirk;
+				snps,dis_enblslpm_quirk;
+			};
+		};
+
+		videocc: clock-controller@abf0000 {
+			compatible = "qcom,qcs8300-videocc";
+			reg = <0x0 0x0abf0000 0x0 0x10000>;
+			clocks = <&gcc GCC_VIDEO_AHB_CLK>,
+				 <&rpmhcc RPMH_CXO_CLK>,
+				 <&rpmhcc RPMH_CXO_CLK_A>,
+				 <&sleep_clk>;
+			power-domains = <&rpmhpd RPMHPD_MMCX>;
+			#clock-cells = <1>;
+			#reset-cells = <1>;
+			#power-domain-cells = <1>;
+		};
+
+		camcc: clock-controller@ade0000 {
+			compatible = "qcom,qcs8300-camcc";
+			reg = <0x0 0x0ade0000 0x0 0x20000>;
+			clocks = <&gcc GCC_CAMERA_AHB_CLK>,
+				 <&rpmhcc RPMH_CXO_CLK>,
+				 <&rpmhcc RPMH_CXO_CLK_A>,
+				 <&sleep_clk>;
+			power-domains = <&rpmhpd RPMHPD_MMCX>;
+			#clock-cells = <1>;
+			#reset-cells = <1>;
+			#power-domain-cells = <1>;
+		};
+
+		dispcc: clock-controller@af00000 {
+			compatible = "qcom,sa8775p-dispcc0";
+			reg = <0x0 0x0af00000 0x0 0x20000>;
+			clocks = <&gcc GCC_DISP_AHB_CLK>,
+				 <&rpmhcc RPMH_CXO_CLK>,
+				 <&rpmhcc RPMH_CXO_CLK_A>,
+				 <&sleep_clk>,
+				 <0>, <0>, <0>, <0>,
+				 <0>, <0>, <0>, <0>;
+			power-domains = <&rpmhpd RPMHPD_MMCX>;
+			#clock-cells = <1>;
+			#reset-cells = <1>;
+			#power-domain-cells = <1>;
+		};
+
+		pdc: interrupt-controller@b220000 {
+			compatible = "qcom,qcs8300-pdc", "qcom,pdc";
+			reg = <0x0 0xb220000 0x0 0x30000>,
+			      <0x0 0x17c000f0 0x0 0x64>;
+			interrupt-parent = <&intc>;
+			#interrupt-cells = <2>;
+			interrupt-controller;
+			qcom,pdc-ranges = <0 480 40>,
+					  <40 140 14>,
+					  <54 263 1>,
+					  <55 306 4>,
+					  <59 312 3>,
+					  <62 374 2>,
+					  <64 434 2>,
+					  <66 438 2>,
+					  <70 520 1>,
+					  <73 523 1>,
+					  <118 568 6>,
+					  <124 609 3>,
+					  <159 638 1>,
+					  <160 720 3>,
+					  <169 728 30>,
+					  <199 416 2>,
+					  <201 449 1>,
+					  <202 89 1>,
+					  <203 451 1>,
+					  <204 462 1>,
+					  <205 264 1>,
+					  <206 579 1>,
+					  <207 653 1>,
+					  <208 656 1>,
+					  <209 659 1>,
+					  <210 122 1>,
+					  <211 699 1>,
+					  <212 705 1>,
+					  <213 450 1>,
+					  <214 643 2>,
+					  <216 646 5>,
+					  <221 390 5>,
+					  <226 700 2>,
+					  <228 440 1>,
+					  <229 663 1>,
+					  <230 524 2>,
+					  <232 612 3>,
+					  <235 723 5>;
+		};
+
+		aoss_qmp: power-management@c300000 {
+			compatible = "qcom,qcs8300-aoss-qmp", "qcom,aoss-qmp";
+			reg = <0x0 0x0c300000 0x0 0x400>;
+			interrupts-extended = <&ipcc IPCC_CLIENT_AOP
+					       IPCC_MPROC_SIGNAL_GLINK_QMP
+					       IRQ_TYPE_EDGE_RISING>;
+			mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>;
+			#clock-cells = <0>;
+		};
+
+		tlmm: pinctrl@f100000 {
+			compatible = "qcom,qcs8300-tlmm";
+			reg = <0x0 0x0f100000 0x0 0x300000>;
+			interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			gpio-ranges = <&tlmm 0 0 134>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			wakeup-parent = <&pdc>;
+
+			qup_uart7_default: qup-uart7-state {
+				/* TX, RX */
+				pins = "gpio43", "gpio44";
+				function = "qup0_se7";
+			};
+		};
+
+		sram: sram@146d8000 {
+			compatible = "qcom,qcs8300-imem", "syscon", "simple-mfd";
+			reg = <0x0 0x146d8000 0x0 0x1000>;
+			ranges = <0x0 0x0 0x146d8000 0x1000>;
+
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			pil-reloc@94c {
+				compatible = "qcom,pil-reloc-info";
+				reg = <0x94c 0xc8>;
+			};
+		};
+
+		apps_smmu: iommu@15000000 {
+			compatible = "qcom,qcs8300-smmu-500", "qcom,smmu-500", "arm,mmu-500";
+
+			reg = <0x0 0x15000000 0x0 0x100000>;
+			#iommu-cells = <2>;
+			#global-interrupts = <2>;
+			dma-coherent;
+
+			interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI  98 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI  99 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 706 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 708 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 709 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 710 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 711 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 712 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 713 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 714 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 715 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 912 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 911 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 910 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 909 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 908 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 907 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 906 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 905 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 904 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 903 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 902 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 901 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 900 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 899 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 898 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 896 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 895 IRQ_TYPE_LEVEL_HIGH>;
+		};
+
+		intc: interrupt-controller@17a00000 {
+			compatible = "arm,gic-v3";
+			reg = <0x0 0x17a00000 0x0 0x10000>,
+			      <0x0 0x17a60000 0x0 0x100000>;
+			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+			#interrupt-cells = <3>;
+			interrupt-controller;
+			#redistributor-regions = <1>;
+			redistributor-stride = <0x0 0x20000>;
+		};
+
+		watchdog@17c10000 {
+			compatible = "qcom,apss-wdt-qcs8300", "qcom,kpss-wdt";
+			reg = <0x0 0x17c10000 0x0 0x1000>;
+			clocks = <&sleep_clk>;
+			interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>;
+		};
+
+		timer@17c20000 {
+			compatible = "arm,armv7-timer-mem";
+			reg = <0x0 0x17c20000 0x0 0x1000>;
+			ranges = <0x0 0x0 0x0 0x20000000>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			frame@17c21000 {
+				reg = <0x17c21000 0x1000>,
+				      <0x17c22000 0x1000>;
+				frame-number = <0>;
+				interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+			};
+
+			frame@17c23000 {
+				reg = <0x17c23000 0x1000>;
+				frame-number = <1>;
+				interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+				status = "disabled";
+			};
+
+			frame@17c25000 {
+				reg = <0x17c25000 0x1000>;
+				frame-number = <2>;
+				interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+				status = "disabled";
+			};
+
+			frame@17c27000 {
+				reg = <0x17c27000 0x1000>;
+				frame-number = <3>;
+				interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+				status = "disabled";
+			};
+
+			frame@17c29000 {
+				reg = <0x17c29000 0x1000>;
+				frame-number = <4>;
+				interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+				status = "disabled";
+			};
+
+			frame@17c2b000 {
+				reg = <0x17c2b000 0x1000>;
+				frame-number = <5>;
+				interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
+				status = "disabled";
+			};
+
+			frame@17c2d000 {
+				reg = <0x17c2d000 0x1000>;
+				frame-number = <6>;
+				interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+				status = "disabled";
+			};
+		};
+
+		apps_rsc: rsc@18200000 {
+			compatible = "qcom,rpmh-rsc";
+			reg = <0x0 0x18200000 0x0 0x10000>,
+			      <0x0 0x18210000 0x0 0x10000>,
+			      <0x0 0x18220000 0x0 0x10000>;
+			reg-names = "drv-0",
+				    "drv-1",
+				    "drv-2";
+			interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
+
+			power-domains = <&system_pd>;
+			label = "apps_rsc";
+
+			qcom,tcs-offset = <0xd00>;
+			qcom,drv-id = <2>;
+			qcom,tcs-config = <ACTIVE_TCS 2>,
+					  <SLEEP_TCS 3>,
+					  <WAKE_TCS 3>,
+					  <CONTROL_TCS 0>;
+
+			apps_bcm_voter: bcm-voter {
+				compatible = "qcom,bcm-voter";
+			};
+
+			rpmhcc: clock-controller {
+				compatible = "qcom,sa8775p-rpmh-clk";
+				#clock-cells = <1>;
+				clocks = <&xo_board_clk>;
+				clock-names = "xo";
+			};
+
+			rpmhpd: power-controller {
+				compatible = "qcom,qcs8300-rpmhpd";
+				#power-domain-cells = <1>;
+				operating-points-v2 = <&rpmhpd_opp_table>;
+
+				rpmhpd_opp_table: opp-table {
+					compatible = "operating-points-v2";
+
+					rpmhpd_opp_ret: opp-0 {
+						opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
+					};
+
+					rpmhpd_opp_min_svs: opp-1 {
+						opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
+					};
+
+					rpmhpd_opp_low_svs: opp-2 {
+						opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
+					};
+
+					rpmhpd_opp_svs: opp-3 {
+						opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
+					};
+
+					rpmhpd_opp_svs_l1: opp-4 {
+						opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
+					};
+
+					rpmhpd_opp_nom: opp-5 {
+						opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
+					};
+
+					rpmhpd_opp_nom_l1: opp-6 {
+						opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
+					};
+
+					rpmhpd_opp_nom_l2: opp-7 {
+						opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
+					};
+
+					rpmhpd_opp_turbo: opp-8 {
+						opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
+					};
+
+					rpmhpd_opp_turbo_l1: opp-9 {
+						opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
+					};
+				};
+			};
+		};
+
+		remoteproc_gpdsp: remoteproc@20c00000 {
+			compatible = "qcom,qcs8300-gpdsp-pas", "qcom,sa8775p-gpdsp0-pas";
+			reg = <0x0 0x20c00000 0x0 0x10000>;
+
+			interrupts-extended = <&intc GIC_SPI 768 IRQ_TYPE_EDGE_RISING>,
+					      <&smp2p_gpdsp_in 0 0>,
+					      <&smp2p_gpdsp_in 1 0>,
+					      <&smp2p_gpdsp_in 2 0>,
+					      <&smp2p_gpdsp_in 3 0>;
+			interrupt-names = "wdog",
+					  "fatal",
+					  "ready",
+					  "handover",
+					  "stop-ack";
+
+			clocks = <&rpmhcc RPMH_CXO_CLK>;
+			clock-names = "xo";
+
+			power-domains = <&rpmhpd RPMHPD_CX>,
+					<&rpmhpd RPMHPD_MXC>;
+			power-domain-names = "cx",
+					     "mxc";
+
+			interconnects = <&gpdsp_anoc MASTER_DSP0 QCOM_ICC_TAG_ALWAYS
+					 &config_noc SLAVE_CLK_CTL QCOM_ICC_TAG_ALWAYS>;
+
+			memory-region = <&gpdsp_mem>;
+
+			qcom,qmp = <&aoss_qmp>;
+
+			qcom,smem-states = <&smp2p_gpdsp_out 0>;
+			qcom,smem-state-names = "stop";
+
+			status = "disabled";
+
+			glink-edge {
+				interrupts-extended = <&ipcc IPCC_CLIENT_GPDSP0
+							     IPCC_MPROC_SIGNAL_GLINK_QMP
+							     IRQ_TYPE_EDGE_RISING>;
+				mboxes = <&ipcc IPCC_CLIENT_GPDSP0
+						IPCC_MPROC_SIGNAL_GLINK_QMP>;
+
+				label = "gpdsp";
+				qcom,remote-pid = <17>;
+			};
+		};
+
+		ethernet0: ethernet@23040000 {
+			compatible = "qcom,qcs8300-ethqos", "qcom,sa8775p-ethqos";
+			reg = <0x0 0x23040000 0x0 0x00010000>,
+			      <0x0 0x23056000 0x0 0x00000100>;
+			reg-names = "stmmaceth", "rgmii";
+
+			interrupts = <GIC_SPI 946 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 783 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "macirq", "sfty";
+
+			clocks = <&gcc GCC_EMAC0_AXI_CLK>,
+				 <&gcc GCC_EMAC0_SLV_AHB_CLK>,
+				 <&gcc GCC_EMAC0_PTP_CLK>,
+				 <&gcc GCC_EMAC0_PHY_AUX_CLK>;
+			clock-names = "stmmaceth",
+				      "pclk",
+				      "ptp_ref",
+				      "phyaux";
+			power-domains = <&gcc GCC_EMAC0_GDSC>;
+
+			phys = <&serdes0>;
+			phy-names = "serdes";
+
+			iommus = <&apps_smmu 0x120 0xf>;
+			dma-coherent;
+
+			snps,tso;
+			snps,pbl = <32>;
+			rx-fifo-depth = <16384>;
+			tx-fifo-depth = <20480>;
+
+			status = "disabled";
+		};
+
+		nspa_noc: interconnect@260c0000 {
+			compatible = "qcom,qcs8300-nspa-noc";
+			reg = <0x0 0x260c0000 0x0 0x16080>;
+			#interconnect-cells = <2>;
+			qcom,bcm-voters = <&apps_bcm_voter>;
+		};
+
+		remoteproc_cdsp: remoteproc@26300000 {
+			compatible = "qcom,qcs8300-cdsp-pas", "qcom,sa8775p-cdsp0-pas";
+			reg = <0x0 0x26300000 0x0 0x10000>;
+
+			interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
+					      <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>,
+					      <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>,
+					      <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>,
+					      <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>;
+			interrupt-names = "wdog",
+					  "fatal",
+					  "ready",
+					  "handover",
+					  "stop-ack";
+
+			clocks = <&rpmhcc RPMH_CXO_CLK>;
+			clock-names = "xo";
+
+			power-domains = <&rpmhpd RPMHPD_CX>,
+					<&rpmhpd RPMHPD_MXC>,
+					<&rpmhpd RPMHPD_NSP0>;
+
+			power-domain-names = "cx",
+					     "mxc",
+					     "nsp";
+
+			interconnects = <&nspa_noc MASTER_CDSP_PROC QCOM_ICC_TAG_ALWAYS
+					 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+
+			memory-region = <&cdsp_mem>;
+
+			qcom,qmp = <&aoss_qmp>;
+
+			qcom,smem-states = <&smp2p_cdsp_out 0>;
+			qcom,smem-state-names = "stop";
+
+			status = "disabled";
+
+			glink-edge {
+				interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
+							     IPCC_MPROC_SIGNAL_GLINK_QMP
+							     IRQ_TYPE_EDGE_RISING>;
+				mboxes = <&ipcc IPCC_CLIENT_CDSP
+						IPCC_MPROC_SIGNAL_GLINK_QMP>;
+
+				label = "cdsp";
+				qcom,remote-pid = <5>;
+
+				fastrpc {
+					compatible = "qcom,fastrpc";
+					qcom,glink-channels = "fastrpcglink-apps-dsp";
+					label = "cdsp";
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					compute-cb@1 {
+						compatible = "qcom,fastrpc-compute-cb";
+						reg = <1>;
+						iommus = <&apps_smmu 0x19c1 0x0440>,
+							 <&apps_smmu 0x1961 0x0400>;
+						dma-coherent;
+					};
+
+					compute-cb@2 {
+						compatible = "qcom,fastrpc-compute-cb";
+						reg = <2>;
+						iommus = <&apps_smmu 0x19c2 0x0440>,
+							 <&apps_smmu 0x1962 0x0400>;
+						dma-coherent;
+					};
+
+					compute-cb@3 {
+						compatible = "qcom,fastrpc-compute-cb";
+						reg = <3>;
+						iommus = <&apps_smmu 0x19c3 0x0440>,
+							 <&apps_smmu 0x1963 0x0400>;
+						dma-coherent;
+					};
+
+					compute-cb@4 {
+						compatible = "qcom,fastrpc-compute-cb";
+						reg = <4>;
+						iommus = <&apps_smmu 0x19c4 0x0440>,
+							 <&apps_smmu 0x1964 0x0400>;
+						dma-coherent;
+					};
+				};
+			};
+		};
+	};
+
+	timer {
+		compatible = "arm,armv8-timer";
+		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
+	};
+};
diff --git a/dts/upstream/src/arm64/qcom/qcs8550-aim300.dtsi b/dts/upstream/src/arm64/qcom/qcs8550-aim300.dtsi
index f6960e2d466..e6ac529e6b7 100644
--- a/dts/upstream/src/arm64/qcom/qcs8550-aim300.dtsi
+++ b/dts/upstream/src/arm64/qcom/qcs8550-aim300.dtsi
@@ -367,7 +367,7 @@
 };
 
 &sleep_clk {
-	clock-frequency = <32000>;
+	clock-frequency = <32764>;
 };
 
 &ufs_mem_hc {
diff --git a/dts/upstream/src/arm64/qcom/qdu1000-idp.dts b/dts/upstream/src/arm64/qcom/qdu1000-idp.dts
index e65305f8136..d125fc77ae1 100644
--- a/dts/upstream/src/arm64/qcom/qdu1000-idp.dts
+++ b/dts/upstream/src/arm64/qcom/qdu1000-idp.dts
@@ -22,20 +22,6 @@
 		stdout-path = "serial0:115200n8";
 	};
 
-	clocks {
-		xo_board: xo-board-clk {
-			compatible = "fixed-clock";
-			clock-frequency = <19200000>;
-			#clock-cells = <0>;
-		};
-
-		sleep_clk: sleep-clk {
-			compatible = "fixed-clock";
-			clock-frequency = <32000>;
-			#clock-cells = <0>;
-		};
-	};
-
 	ppvar_sys: ppvar-sys-regulator {
 		compatible = "regulator-fixed";
 		regulator-name = "ppvar_sys";
@@ -239,6 +225,11 @@
 	};
 };
 
+&pon {
+	mode-bootloader = <0x2>;
+	mode-recovery = <0x1>;
+};
+
 &qup_i2c1_data_clk {
 	drive-strength = <2>;
 	bias-pull-up;
diff --git a/dts/upstream/src/arm64/qcom/qdu1000.dtsi b/dts/upstream/src/arm64/qcom/qdu1000.dtsi
index 47c0dd31aaf..f973aa8f747 100644
--- a/dts/upstream/src/arm64/qcom/qdu1000.dtsi
+++ b/dts/upstream/src/arm64/qcom/qdu1000.dtsi
@@ -21,6 +21,20 @@
 
 	chosen: chosen { };
 
+	clocks {
+		xo_board: xo-board-clk {
+			compatible = "fixed-clock";
+			clock-frequency = <19200000>;
+			#clock-cells = <0>;
+		};
+
+		sleep_clk: sleep-clk {
+			compatible = "fixed-clock";
+			clock-frequency = <32764>;
+			#clock-cells = <0>;
+		};
+	};
+
 	cpus {
 		#address-cells = <2>;
 		#size-cells = <0>;
@@ -1009,6 +1023,8 @@
 				iommus = <&apps_smmu 0xc0 0x0>;
 				snps,dis_u2_susphy_quirk;
 				snps,dis_enblslpm_quirk;
+				snps,dis-u1-entry-quirk;
+				snps,dis-u2-entry-quirk;
 				phys = <&usb_1_hsphy>,
 				       <&usb_1_qmpphy>;
 				phy-names = "usb2-phy",
diff --git a/dts/upstream/src/arm64/qcom/qrb4210-rb2.dts b/dts/upstream/src/arm64/qcom/qrb4210-rb2.dts
index a9540e92d3e..52db1884780 100644
--- a/dts/upstream/src/arm64/qcom/qrb4210-rb2.dts
+++ b/dts/upstream/src/arm64/qcom/qrb4210-rb2.dts
@@ -6,6 +6,8 @@
 /dts-v1/;
 
 #include <dt-bindings/leds/common.h>
+#include <dt-bindings/sound/qcom,q6afe.h>
+#include <dt-bindings/sound/qcom,q6asm.h>
 #include <dt-bindings/usb/pd.h>
 #include "sm4250.dtsi"
 #include "pm6125.dtsi"
@@ -103,6 +105,55 @@
 		};
 	};
 
+	sound {
+		compatible = "qcom,qrb4210-rb2-sndcard";
+		pinctrl-0 = <&lpi_i2s2_active>;
+		pinctrl-names = "default";
+		model = "Qualcomm-RB2-WSA8815-Speakers-DMIC0";
+		audio-routing = "MM_DL1", "MultiMedia1 Playback",
+				"MM_DL2", "MultiMedia2 Playback";
+
+		mm1-dai-link {
+			link-name = "MultiMedia1";
+
+			cpu {
+				sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA1>;
+			};
+		};
+
+		mm2-dai-link {
+			link-name = "MultiMedia2";
+
+			cpu {
+				sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA2>;
+			};
+		};
+
+		mm3-dai-link {
+			link-name = "MultiMedia3";
+
+			cpu {
+				sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA3>;
+			};
+		};
+
+		hdmi-dai-link {
+			link-name = "HDMI Playback";
+
+			cpu {
+				sound-dai = <&q6afedai SECONDARY_MI2S_RX>;
+			};
+
+			platform {
+				sound-dai = <&q6routing>;
+			};
+
+			codec {
+				sound-dai = <&lt9611_codec 0>;
+			};
+		};
+	};
+
 	vreg_hdmi_out_1p2: regulator-hdmi-out-1p2 {
 		compatible = "regulator-fixed";
 		regulator-name = "VREG_HDMI_OUT_1P2";
@@ -318,6 +369,14 @@
 	status = "okay";
 };
 
+/* SECONDARY I2S uses 1 I2S SD Line for audio on LT9611UXC HDMI Bridge */
+&q6afedai {
+	dai@20 {
+		reg = <SECONDARY_MI2S_RX>;
+		qcom,sd-lines = <0>;
+	};
+};
+
 &qupv3_id_0 {
 	status = "okay";
 };
@@ -545,7 +604,7 @@
 };
 
 &sleep_clk {
-	clock-frequency = <32000>;
+	clock-frequency = <32764>;
 };
 
 &tlmm {
diff --git a/dts/upstream/src/arm64/qcom/qrb5165-rb5.dts b/dts/upstream/src/arm64/qcom/qrb5165-rb5.dts
index 52eef88e882..7afa5acac3f 100644
--- a/dts/upstream/src/arm64/qcom/qrb5165-rb5.dts
+++ b/dts/upstream/src/arm64/qcom/qrb5165-rb5.dts
@@ -964,6 +964,11 @@
 	};
 };
 
+&pon {
+	mode-bootloader = <0x2>;
+	mode-recovery = <0x1>;
+};
+
 &pon_pwrkey {
 	status = "okay";
 };
diff --git a/dts/upstream/src/arm64/qcom/qru1000-idp.dts b/dts/upstream/src/arm64/qcom/qru1000-idp.dts
index 1c781d9e24c..439f5c327dc 100644
--- a/dts/upstream/src/arm64/qcom/qru1000-idp.dts
+++ b/dts/upstream/src/arm64/qcom/qru1000-idp.dts
@@ -22,20 +22,6 @@
 		stdout-path = "serial0:115200n8";
 	};
 
-	clocks {
-		xo_board: xo-board-clk {
-			compatible = "fixed-clock";
-			clock-frequency = <19200000>;
-			#clock-cells = <0>;
-		};
-
-		sleep_clk: sleep-clk {
-			compatible = "fixed-clock";
-			clock-frequency = <32000>;
-			#clock-cells = <0>;
-		};
-	};
-
 	ppvar_sys: ppvar-sys-regulator {
 		compatible = "regulator-fixed";
 		regulator-name = "ppvar_sys";
@@ -239,6 +225,11 @@
 	};
 };
 
+&pon {
+	mode-bootloader = <0x2>;
+	mode-recovery = <0x1>;
+};
+
 &qup_i2c1_data_clk {
 	drive-strength = <2>;
 	bias-pull-up;
diff --git a/dts/upstream/src/arm64/qcom/sa8775p-ride.dtsi b/dts/upstream/src/arm64/qcom/sa8775p-ride.dtsi
index 3fc62e12368..175f8b1e3b2 100644
--- a/dts/upstream/src/arm64/qcom/sa8775p-ride.dtsi
+++ b/dts/upstream/src/arm64/qcom/sa8775p-ride.dtsi
@@ -104,6 +104,30 @@
 			};
 		};
 	};
+
+	dp0-connector {
+		compatible = "dp-connector";
+		label = "eDP0";
+		type = "full-size";
+
+		port {
+			dp0_connector_in: endpoint {
+				remote-endpoint = <&mdss0_dp0_out>;
+			};
+		};
+	};
+
+	dp1-connector {
+		compatible = "dp-connector";
+		label = "eDP1";
+		type = "full-size";
+
+		port {
+			dp1_connector_in: endpoint {
+				remote-endpoint = <&mdss0_dp1_out>;
+			};
+		};
+	};
 };
 
 &apps_rsc {
@@ -498,6 +522,50 @@
 	status = "okay";
 };
 
+&mdss0 {
+	status = "okay";
+};
+
+&mdss0_dp0 {
+	pinctrl-0 = <&dp0_hot_plug_det>;
+	pinctrl-names = "default";
+
+	status = "okay";
+};
+
+&mdss0_dp0_out {
+	data-lanes = <0 1 2 3>;
+	link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>;
+	remote-endpoint = <&dp0_connector_in>;
+};
+
+&mdss0_dp0_phy {
+	vdda-phy-supply = <&vreg_l1c>;
+	vdda-pll-supply = <&vreg_l4a>;
+
+	status = "okay";
+};
+
+&mdss0_dp1 {
+	pinctrl-0 = <&dp1_hot_plug_det>;
+	pinctrl-names = "default";
+
+	status = "okay";
+};
+
+&mdss0_dp1_out {
+	data-lanes = <0 1 2 3>;
+	link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>;
+	remote-endpoint = <&dp1_connector_in>;
+};
+
+&mdss0_dp1_phy {
+	vdda-phy-supply = <&vreg_l1c>;
+	vdda-pll-supply = <&vreg_l4a>;
+
+	status = "okay";
+};
+
 &pmm8654au_0_gpios {
 	gpio-line-names = "DS_EN",
 			  "POFF_COMPLETE",
@@ -608,7 +676,7 @@
 };
 
 &sleep_clk {
-	clock-frequency = <32764>;
+	clock-frequency = <32000>;
 };
 
 &spi16 {
@@ -618,6 +686,18 @@
 };
 
 &tlmm {
+	dp0_hot_plug_det: dp0-hot-plug-det-state {
+		pins = "gpio101";
+		function = "edp0_hot";
+		bias-disable;
+	};
+
+	dp1_hot_plug_det: dp1-hot-plug-det-state {
+		pins = "gpio102";
+		function = "edp1_hot";
+		bias-disable;
+	};
+
 	ethernet0_default: ethernet0-default-state {
 		ethernet0_mdc: ethernet0-mdc-pins {
 			pins = "gpio8";
diff --git a/dts/upstream/src/arm64/qcom/sa8775p.dtsi b/dts/upstream/src/arm64/qcom/sa8775p.dtsi
index 9da62d7c4d2..3394ae2d130 100644
--- a/dts/upstream/src/arm64/qcom/sa8775p.dtsi
+++ b/dts/upstream/src/arm64/qcom/sa8775p.dtsi
@@ -7,6 +7,7 @@
 #include <dt-bindings/interconnect/qcom,icc.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/clock/qcom,rpmh.h>
+#include <dt-bindings/clock/qcom,sa8775p-dispcc.h>
 #include <dt-bindings/clock/qcom,sa8775p-gcc.h>
 #include <dt-bindings/clock/qcom,sa8775p-gpucc.h>
 #include <dt-bindings/dma/qcom-gpi.h>
@@ -44,6 +45,8 @@
 			compatible = "qcom,kryo";
 			reg = <0x0 0x0>;
 			enable-method = "psci";
+			power-domains = <&cpu_pd0>;
+			power-domain-names = "psci";
 			qcom,freq-domain = <&cpufreq_hw 0>;
 			next-level-cache = <&l2_0>;
 			capacity-dmips-mhz = <1024>;
@@ -66,6 +69,8 @@
 			compatible = "qcom,kryo";
 			reg = <0x0 0x100>;
 			enable-method = "psci";
+			power-domains = <&cpu_pd1>;
+			power-domain-names = "psci";
 			qcom,freq-domain = <&cpufreq_hw 0>;
 			next-level-cache = <&l2_1>;
 			capacity-dmips-mhz = <1024>;
@@ -83,6 +88,8 @@
 			compatible = "qcom,kryo";
 			reg = <0x0 0x200>;
 			enable-method = "psci";
+			power-domains = <&cpu_pd2>;
+			power-domain-names = "psci";
 			qcom,freq-domain = <&cpufreq_hw 0>;
 			next-level-cache = <&l2_2>;
 			capacity-dmips-mhz = <1024>;
@@ -100,6 +107,8 @@
 			compatible = "qcom,kryo";
 			reg = <0x0 0x300>;
 			enable-method = "psci";
+			power-domains = <&cpu_pd3>;
+			power-domain-names = "psci";
 			qcom,freq-domain = <&cpufreq_hw 0>;
 			next-level-cache = <&l2_3>;
 			capacity-dmips-mhz = <1024>;
@@ -117,6 +126,8 @@
 			compatible = "qcom,kryo";
 			reg = <0x0 0x10000>;
 			enable-method = "psci";
+			power-domains = <&cpu_pd4>;
+			power-domain-names = "psci";
 			qcom,freq-domain = <&cpufreq_hw 1>;
 			next-level-cache = <&l2_4>;
 			capacity-dmips-mhz = <1024>;
@@ -140,6 +151,8 @@
 			compatible = "qcom,kryo";
 			reg = <0x0 0x10100>;
 			enable-method = "psci";
+			power-domains = <&cpu_pd5>;
+			power-domain-names = "psci";
 			qcom,freq-domain = <&cpufreq_hw 1>;
 			next-level-cache = <&l2_5>;
 			capacity-dmips-mhz = <1024>;
@@ -157,6 +170,8 @@
 			compatible = "qcom,kryo";
 			reg = <0x0 0x10200>;
 			enable-method = "psci";
+			power-domains = <&cpu_pd6>;
+			power-domain-names = "psci";
 			qcom,freq-domain = <&cpufreq_hw 1>;
 			next-level-cache = <&l2_6>;
 			capacity-dmips-mhz = <1024>;
@@ -174,6 +189,8 @@
 			compatible = "qcom,kryo";
 			reg = <0x0 0x10300>;
 			enable-method = "psci";
+			power-domains = <&cpu_pd7>;
+			power-domain-names = "psci";
 			qcom,freq-domain = <&cpufreq_hw 1>;
 			next-level-cache = <&l2_7>;
 			capacity-dmips-mhz = <1024>;
@@ -854,8 +871,8 @@
 			#mbox-cells = <2>;
 		};
 
-		gpi_dma2: qcom,gpi-dma@800000  {
-			compatible = "qcom,sm6350-gpi-dma";
+		gpi_dma2: dma-controller@800000  {
+			compatible = "qcom,sa8775p-gpi-dma", "qcom,sm6350-gpi-dma";
 			reg = <0x0 0x00800000 0x0 0x60000>;
 			#dma-cells = <3>;
 			interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>,
@@ -1345,8 +1362,8 @@
 
 		};
 
-		gpi_dma0: qcom,gpi-dma@900000  {
-			compatible = "qcom,sm6350-gpi-dma";
+		gpi_dma0: dma-controller@900000  {
+			compatible = "qcom,sa8775p-gpi-dma", "qcom,sm6350-gpi-dma";
 			reg = <0x0 0x00900000 0x0 0x60000>;
 			#dma-cells = <3>;
 			interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
@@ -1770,8 +1787,8 @@
 			};
 		};
 
-		gpi_dma1: qcom,gpi-dma@a00000  {
-			compatible = "qcom,sm6350-gpi-dma";
+		gpi_dma1: dma-controller@a00000  {
+			compatible = "qcom,sa8775p-gpi-dma", "qcom,sm6350-gpi-dma";
 			reg = <0x0 0x00a00000 0x0 0x60000>;
 			#dma-cells = <3>;
 			interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
@@ -2225,8 +2242,8 @@
 			};
 		};
 
-		gpi_dma3: qcom,gpi-dma@b00000  {
-			compatible = "qcom,sm6350-gpi-dma";
+		gpi_dma3: dma-controller@b00000  {
+			compatible = "qcom,sa8775p-gpi-dma", "qcom,sm6350-gpi-dma";
 			reg = <0x0 0x00b00000 0x0 0x58000>;
 			#dma-cells = <3>;
 			interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>,
@@ -3412,6 +3429,8 @@
 				iommus = <&apps_smmu 0x080 0x0>;
 				phys = <&usb_0_hsphy>, <&usb_0_qmpphy>;
 				phy-names = "usb2-phy", "usb3-phy";
+				snps,dis-u1-entry-quirk;
+				snps,dis-u2-entry-quirk;
 			};
 		};
 
@@ -3501,6 +3520,8 @@
 				iommus = <&apps_smmu 0x0a0 0x0>;
 				phys = <&usb_1_hsphy>, <&usb_1_qmpphy>;
 				phy-names = "usb2-phy", "usb3-phy";
+				snps,dis-u1-entry-quirk;
+				snps,dis-u2-entry-quirk;
 			};
 		};
 
@@ -3564,6 +3585,8 @@
 				iommus = <&apps_smmu 0x020 0x0>;
 				phys = <&usb_2_hsphy>;
 				phy-names = "usb2-phy";
+				snps,dis-u1-entry-quirk;
+				snps,dis-u2-entry-quirk;
 			};
 		};
 
@@ -3760,6 +3783,353 @@
 			interrupts = <GIC_SPI 580 IRQ_TYPE_LEVEL_HIGH>;
 		};
 
+		videocc: clock-controller@abf0000 {
+			compatible = "qcom,sa8775p-videocc";
+			reg = <0x0 0x0abf0000 0x0 0x10000>;
+			clocks = <&gcc GCC_VIDEO_AHB_CLK>,
+				 <&rpmhcc RPMH_CXO_CLK>,
+				 <&rpmhcc RPMH_CXO_CLK_A>,
+				 <&sleep_clk>;
+			power-domains = <&rpmhpd SA8775P_MMCX>;
+			#clock-cells = <1>;
+			#reset-cells = <1>;
+			#power-domain-cells = <1>;
+		};
+
+		camcc: clock-controller@ade0000 {
+			compatible = "qcom,sa8775p-camcc";
+			reg = <0x0 0x0ade0000 0x0 0x20000>;
+			clocks = <&gcc GCC_CAMERA_AHB_CLK>,
+				 <&rpmhcc RPMH_CXO_CLK>,
+				 <&rpmhcc RPMH_CXO_CLK_A>,
+				 <&sleep_clk>;
+			power-domains = <&rpmhpd SA8775P_MMCX>;
+			#clock-cells = <1>;
+			#reset-cells = <1>;
+			#power-domain-cells = <1>;
+		};
+
+		mdss0: display-subsystem@ae00000 {
+			compatible = "qcom,sa8775p-mdss";
+			reg = <0x0 0x0ae00000 0x0 0x1000>;
+			reg-names = "mdss";
+
+			/* same path used twice */
+			interconnects = <&mmss_noc MASTER_MDP0 QCOM_ICC_TAG_ACTIVE_ONLY
+					 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
+					<&mmss_noc MASTER_MDP1 QCOM_ICC_TAG_ACTIVE_ONLY
+					 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
+					<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+					 &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>;
+			interconnect-names = "mdp0-mem",
+					     "mdp1-mem",
+					     "cpu-cfg";
+
+			resets = <&dispcc0 MDSS_DISP_CC_MDSS_CORE_BCR>;
+
+			power-domains = <&dispcc0 MDSS_DISP_CC_MDSS_CORE_GDSC>;
+
+			clocks = <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>,
+				 <&gcc GCC_DISP_HF_AXI_CLK>,
+				 <&dispcc0 MDSS_DISP_CC_MDSS_MDP_CLK>;
+
+			interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-controller;
+			#interrupt-cells = <1>;
+
+			iommus = <&apps_smmu 0x1000 0x402>;
+
+			#address-cells = <2>;
+			#size-cells = <2>;
+			ranges;
+
+			status = "disabled";
+
+			mdss0_mdp: display-controller@ae01000 {
+				compatible = "qcom,sa8775p-dpu";
+				reg = <0x0 0x0ae01000 0x0 0x8f000>,
+				      <0x0 0x0aeb0000 0x0 0x2008>;
+				reg-names = "mdp", "vbif";
+
+				clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
+					 <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>,
+					 <&dispcc0 MDSS_DISP_CC_MDSS_MDP_LUT_CLK>,
+					 <&dispcc0 MDSS_DISP_CC_MDSS_MDP_CLK>,
+					 <&dispcc0 MDSS_DISP_CC_MDSS_VSYNC_CLK>;
+				clock-names = "bus",
+					      "iface",
+					      "lut",
+					      "core",
+					      "vsync";
+
+				assigned-clocks = <&dispcc0 MDSS_DISP_CC_MDSS_VSYNC_CLK>;
+				assigned-clock-rates = <19200000>;
+
+				operating-points-v2 = <&mdss0_mdp_opp_table>;
+				power-domains = <&rpmhpd SA8775P_MMCX>;
+
+				interrupt-parent = <&mdss0>;
+				interrupts = <0>;
+
+				ports {
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					port@0 {
+						reg = <0>;
+
+						dpu_intf0_out: endpoint {
+							remote-endpoint = <&mdss0_dp0_in>;
+						};
+					};
+
+					port@1 {
+						reg = <1>;
+
+						dpu_intf4_out: endpoint {
+							remote-endpoint = <&mdss0_dp1_in>;
+						};
+					};
+				};
+
+				mdss0_mdp_opp_table: opp-table {
+					compatible = "operating-points-v2";
+
+					opp-375000000 {
+						opp-hz = /bits/ 64 <375000000>;
+						required-opps = <&rpmhpd_opp_svs_l1>;
+					};
+
+					opp-500000000 {
+						opp-hz = /bits/ 64 <500000000>;
+						required-opps = <&rpmhpd_opp_nom>;
+					};
+
+					opp-575000000 {
+						opp-hz = /bits/ 64 <575000000>;
+						required-opps = <&rpmhpd_opp_turbo>;
+					};
+
+					opp-650000000 {
+						opp-hz = /bits/ 64 <650000000>;
+						required-opps = <&rpmhpd_opp_turbo_l1>;
+					};
+				};
+			};
+
+			mdss0_dp0_phy: phy@aec2a00 {
+				compatible = "qcom,sa8775p-edp-phy";
+
+				reg = <0x0 0x0aec2a00 0x0 0x200>,
+				      <0x0 0x0aec2200 0x0 0xd0>,
+				      <0x0 0x0aec2600 0x0 0xd0>,
+				      <0x0 0x0aec2000 0x0 0x1c8>;
+
+				clocks = <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK>,
+					 <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>;
+				clock-names = "aux",
+					      "cfg_ahb";
+
+				#clock-cells = <1>;
+				#phy-cells = <0>;
+
+				status = "disabled";
+			};
+
+			mdss0_dp1_phy: phy@aec5a00 {
+				compatible = "qcom,sa8775p-edp-phy";
+
+				reg = <0x0 0x0aec5a00 0x0 0x200>,
+				      <0x0 0x0aec5200 0x0 0xd0>,
+				      <0x0 0x0aec5600 0x0 0xd0>,
+				      <0x0 0x0aec5000 0x0 0x1c8>;
+
+				clocks = <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_AUX_CLK>,
+					 <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>;
+				clock-names = "aux",
+					      "cfg_ahb";
+
+				#clock-cells = <1>;
+				#phy-cells = <0>;
+
+				status = "disabled";
+			};
+
+			mdss0_dp0: displayport-controller@af54000 {
+				compatible = "qcom,sa8775p-dp";
+
+				reg = <0x0 0x0af54000 0x0 0x104>,
+				      <0x0 0x0af54200 0x0 0x0c0>,
+				      <0x0 0x0af55000 0x0 0x770>,
+				      <0x0 0x0af56000 0x0 0x09c>,
+				      <0x0 0x0af57000 0x0 0x09c>;
+
+				interrupt-parent = <&mdss0>;
+				interrupts = <12>;
+
+				clocks = <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>,
+					 <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK>,
+					 <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK>,
+					 <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>,
+					 <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK>;
+				clock-names = "core_iface",
+					      "core_aux",
+					      "ctrl_link",
+					      "ctrl_link_iface",
+					      "stream_pixel";
+				assigned-clocks = <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
+						  <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>;
+				assigned-clock-parents = <&mdss0_dp0_phy 0>, <&mdss0_dp0_phy 1>;
+				phys = <&mdss0_dp0_phy>;
+				phy-names = "dp";
+
+				operating-points-v2 = <&dp_opp_table>;
+				power-domains = <&rpmhpd SA8775P_MMCX>;
+
+				#sound-dai-cells = <0>;
+
+				status = "disabled";
+
+				ports {
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					port@0 {
+						reg = <0>;
+
+						mdss0_dp0_in: endpoint {
+							remote-endpoint = <&dpu_intf0_out>;
+						};
+					};
+
+					port@1 {
+						reg = <1>;
+
+						mdss0_dp0_out: endpoint { };
+					};
+				};
+
+				dp_opp_table: opp-table {
+					compatible = "operating-points-v2";
+
+					opp-160000000 {
+						opp-hz = /bits/ 64 <160000000>;
+						required-opps = <&rpmhpd_opp_low_svs>;
+					};
+
+					opp-270000000 {
+						opp-hz = /bits/ 64 <270000000>;
+						required-opps = <&rpmhpd_opp_svs>;
+					};
+
+					opp-540000000 {
+						opp-hz = /bits/ 64 <540000000>;
+						required-opps = <&rpmhpd_opp_svs_l1>;
+					};
+
+					opp-810000000 {
+						opp-hz = /bits/ 64 <810000000>;
+						required-opps = <&rpmhpd_opp_nom>;
+					};
+				};
+			};
+
+			mdss0_dp1: displayport-controller@af5c000 {
+				compatible = "qcom,sa8775p-dp";
+
+				reg = <0x0 0x0af5c000 0x0 0x104>,
+				      <0x0 0x0af5c200 0x0 0x0c0>,
+				      <0x0 0x0af5d000 0x0 0x770>,
+				      <0x0 0x0af5e000 0x0 0x09c>,
+				      <0x0 0x0af5f000 0x0 0x09c>;
+
+				interrupt-parent = <&mdss0>;
+				interrupts = <13>;
+
+				clocks = <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>,
+					 <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_AUX_CLK>,
+					 <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_LINK_CLK>,
+					 <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_LINK_INTF_CLK>,
+					 <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_PIXEL0_CLK>;
+				clock-names = "core_iface",
+					      "core_aux",
+					      "ctrl_link",
+					      "ctrl_link_iface",
+					      "stream_pixel";
+				assigned-clocks = <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_LINK_CLK_SRC>,
+						  <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>;
+				assigned-clock-parents = <&mdss0_dp1_phy 0>, <&mdss0_dp1_phy 1>;
+				phys = <&mdss0_dp1_phy>;
+				phy-names = "dp";
+
+				operating-points-v2 = <&dp1_opp_table>;
+				power-domains = <&rpmhpd SA8775P_MMCX>;
+
+				#sound-dai-cells = <0>;
+
+				status = "disabled";
+
+				ports {
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					port@0 {
+						reg = <0>;
+
+						mdss0_dp1_in: endpoint {
+							remote-endpoint = <&dpu_intf4_out>;
+						};
+					};
+
+					port@1 {
+						reg = <1>;
+
+						mdss0_dp1_out: endpoint { };
+					};
+				};
+
+				dp1_opp_table: opp-table {
+					compatible = "operating-points-v2";
+
+					opp-160000000 {
+						opp-hz = /bits/ 64 <160000000>;
+						required-opps = <&rpmhpd_opp_low_svs>;
+					};
+
+					opp-270000000 {
+						opp-hz = /bits/ 64 <270000000>;
+						required-opps = <&rpmhpd_opp_svs>;
+					};
+
+					opp-540000000 {
+						opp-hz = /bits/ 64 <540000000>;
+						required-opps = <&rpmhpd_opp_svs_l1>;
+					};
+
+					opp-810000000 {
+						opp-hz = /bits/ 64 <810000000>;
+						required-opps = <&rpmhpd_opp_nom>;
+					};
+				};
+			};
+		};
+
+		dispcc0: clock-controller@af00000 {
+			compatible = "qcom,sa8775p-dispcc0";
+			reg = <0x0 0x0af00000 0x0 0x20000>;
+			clocks = <&gcc GCC_DISP_AHB_CLK>,
+				 <&rpmhcc RPMH_CXO_CLK>,
+				 <&rpmhcc RPMH_CXO_CLK_A>,
+				 <&sleep_clk>,
+				 <&mdss0_dp0_phy 0>, <&mdss0_dp0_phy 1>,
+				 <&mdss0_dp1_phy 0>, <&mdss0_dp1_phy 1>,
+				 <0>, <0>, <0>, <0>;
+			power-domains = <&rpmhpd SA8775P_MMCX>;
+			#clock-cells = <1>;
+			#reset-cells = <1>;
+			#power-domain-cells = <1>;
+		};
+
 		pdc: interrupt-controller@b220000 {
 			compatible = "qcom,sa8775p-pdc", "qcom,pdc";
 			reg = <0x0 0x0b220000 0x0 0x30000>,
@@ -4382,6 +4752,22 @@
 			};
 		};
 
+		dispcc1: clock-controller@22100000 {
+			compatible = "qcom,sa8775p-dispcc1";
+			reg = <0x0 0x22100000 0x0 0x20000>;
+			clocks = <&gcc GCC_DISP_AHB_CLK>,
+				 <&rpmhcc RPMH_CXO_CLK>,
+				 <&rpmhcc RPMH_CXO_CLK_A>,
+				 <&sleep_clk>,
+				 <0>, <0>, <0>, <0>,
+				 <0>, <0>, <0>, <0>;
+			power-domains = <&rpmhpd SA8775P_MMCX>;
+			#clock-cells = <1>;
+			#reset-cells = <1>;
+			#power-domain-cells = <1>;
+			status = "disabled";
+		};
+
 		ethernet1: ethernet@23000000 {
 			compatible = "qcom,sa8775p-ethqos";
 			reg = <0x0 0x23000000 0x0 0x10000>,
diff --git a/dts/upstream/src/arm64/qcom/sar2130p-qar2130p.dts b/dts/upstream/src/arm64/qcom/sar2130p-qar2130p.dts
new file mode 100644
index 00000000000..74778a5b19b
--- /dev/null
+++ b/dts/upstream/src/arm64/qcom/sar2130p-qar2130p.dts
@@ -0,0 +1,558 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2024, Linaro Limited
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
+#include "sar2130p.dtsi"
+#include "pm8150.dtsi"
+
+/ {
+	model = "Qualcomm Snapdragon AR2 Gen1 Smart Viewer Development Kit";
+	compatible = "qcom,qar2130p", "qcom,sar2130p";
+	chassis-type = "embedded";
+
+	aliases {
+		serial0 = &uart11;
+		serial1 = &uart7;
+		i2c0 = &i2c8;
+		i2c1 = &i2c10;
+		mmc1 = &sdhc_1;
+		spi0 = &spi0;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	vph_pwr: regulator-vph-pwr {
+		compatible = "regulator-fixed";
+		regulator-name = "vph_pwr";
+		regulator-min-microvolt = <3700000>;
+		regulator-max-microvolt = <3700000>;
+		regulator-always-on;
+	};
+
+	/* pm3003a on I2C0, should not be controlled */
+	vreg_ext_1p3: regulator-ext-1p3 {
+		compatible = "regulator-fixed";
+		regulator-name = "vph_ext_1p3";
+		regulator-min-microvolt = <1300000>;
+		regulator-max-microvolt = <1300000>;
+		regulator-always-on;
+		vin-supply = <&vph_pwr>;
+	};
+
+	/* EBI rail, used as LDO input, can not be part of PMIC config */
+	vreg_s10a_0p89: regulator-s10a-0p89 {
+		compatible = "regulator-fixed";
+		regulator-name = "vph_s10a_0p89";
+		regulator-min-microvolt = <890000>;
+		regulator-max-microvolt = <890000>;
+		regulator-always-on;
+		vin-supply = <&vph_pwr>;
+	};
+
+	thermal-zones {
+		sar2130p-thermal {
+			thermal-sensors = <&pm8150_adc_tm 1>;
+
+			trips {
+				active-config0 {
+					temperature = <100000>;
+					hysteresis = <1000>;
+					type = "critical";
+				};
+			};
+		};
+
+		wifi-thermal {
+			thermal-sensors = <&pm8150_adc_tm 2>;
+
+			trips {
+				active-config0 {
+					temperature = <52000>;
+					hysteresis = <4000>;
+					type = "passive";
+				};
+			};
+		};
+
+		xo-thermal {
+			thermal-sensors = <&pm8150_adc_tm 0>;
+
+			trips {
+				active-config0 {
+					temperature = <50000>;
+					hysteresis = <4000>;
+					type = "passive";
+				};
+			};
+		};
+	};
+
+	wcn7850-pmu {
+		compatible = "qcom,wcn7850-pmu";
+
+		pinctrl-0 = <&wlan_en_state>, <&bt_en_state>;
+		pinctrl-names = "default";
+
+		wlan-enable-gpios = <&tlmm 45 GPIO_ACTIVE_HIGH>;
+		bt-enable-gpios = <&tlmm 46 GPIO_ACTIVE_HIGH>;
+
+		vdd-supply = <&vreg_s4a_0p95>;
+		vddio-supply = <&vreg_l15a_1p8>;
+		vddaon-supply = <&vreg_s4a_0p95>;
+		vdddig-supply = <&vreg_s4a_0p95>;
+		vddrfa1p2-supply = <&vreg_s4a_0p95>;
+		vddrfa1p8-supply = <&vreg_s5a_1p88>;
+
+		regulators {
+			vreg_pmu_rfa_cmn: ldo0 {
+				regulator-name = "vreg_pmu_rfa_cmn";
+			};
+
+			vreg_pmu_aon_0p59: ldo1 {
+				regulator-name = "vreg_pmu_aon_0p59";
+			};
+
+			vreg_pmu_wlcx_0p8: ldo2 {
+				regulator-name = "vreg_pmu_wlcx_0p8";
+			};
+
+			vreg_pmu_wlmx_0p85: ldo3 {
+				regulator-name = "vreg_pmu_wlmx_0p85";
+			};
+
+			vreg_pmu_btcmx_0p85: ldo4 {
+				regulator-name = "vreg_pmu_btcmx_0p85";
+			};
+
+			vreg_pmu_rfa_0p8: ldo5 {
+				regulator-name = "vreg_pmu_rfa_0p8";
+			};
+
+			vreg_pmu_rfa_1p2: ldo6 {
+				regulator-name = "vreg_pmu_rfa_1p2";
+			};
+
+			vreg_pmu_rfa_1p8: ldo7 {
+				regulator-name = "vreg_pmu_rfa_1p8";
+			};
+
+			vreg_pmu_pcie_0p9: ldo8 {
+				regulator-name = "vreg_pmu_pcie_0p9";
+			};
+
+			vreg_pmu_pcie_1p8: ldo9 {
+				regulator-name = "vreg_pmu_pcie_1p8";
+			};
+		};
+	};
+};
+
+&apps_rsc {
+	regulators-0 {
+		compatible = "qcom,pm8150-rpmh-regulators";
+		qcom,pmic-id = "a";
+
+		vdd-s1-supply = <&vph_pwr>;
+		vdd-s2-supply = <&vph_pwr>;
+		vdd-s3-supply = <&vph_pwr>;
+		vdd-s4-supply = <&vph_pwr>;
+		vdd-s5-supply = <&vph_pwr>;
+		vdd-s6-supply = <&vph_pwr>;
+		vdd-s7-supply = <&vph_pwr>;
+		vdd-s8-supply = <&vph_pwr>;
+		vdd-s9-supply = <&vph_pwr>;
+		vdd-s10-supply = <&vph_pwr>;
+		vdd-l1-l8-l11-supply = <&vreg_s4a_0p95>;
+		vdd-l3-l4-l5-l18-supply = <&vreg_ext_1p3>;
+		vdd-l6-l9-supply = <&vreg_s10a_0p89>;
+		vdd-l7-l12-l14-l15-supply = <&vreg_s5a_1p88>;
+
+		vreg_s4a_0p95: smps6 {
+			regulator-name = "vreg_s4a_0p95";
+			regulator-min-microvolt = <950000>;
+			regulator-max-microvolt = <1170000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_s5a_1p88: smps5 {
+			regulator-name = "vreg_s5a_1p88";
+			regulator-min-microvolt = <1856000>;
+			regulator-max-microvolt = <2040000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l1a_0p91: ldo1 {
+			regulator-name = "vreg_l1a_0p91";
+			regulator-min-microvolt = <912000>;
+			regulator-max-microvolt = <920000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l2a_3p1: ldo2 {
+			regulator-name = "vreg_l2a_3p1";
+			regulator-min-microvolt = <3080000>;
+			regulator-max-microvolt = <3544000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l3a_1p2: ldo3 {
+			regulator-name = "vreg_l3a_1p2";
+			regulator-min-microvolt = <1200000>;
+			regulator-max-microvolt = <1304000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		/* ldo4 1.26 - system ? */
+
+		vreg_l5a_1p13: ldo5 {
+			regulator-name = "vreg_l5a_1p13";
+			regulator-min-microvolt = <1128000>;
+			regulator-max-microvolt = <1170000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l6a_0p6: ldo6 {
+			regulator-name = "vreg_l6a_0p6";
+			regulator-min-microvolt = <600000>;
+			regulator-max-microvolt = <650000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l7a_1p8: ldo7 {
+			regulator-name = "vreg_l7a_1p8";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1950000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l8a_0p88: ldo8 {
+			regulator-name = "vreg_l8a_0p88";
+			regulator-min-microvolt = <880000>;
+			regulator-max-microvolt = <950000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		/* ldo9 - LCX */
+
+		vreg_l10a_2p95: ldo10 {
+			regulator-name = "vreg_l10a_2p95";
+			regulator-min-microvolt = <2952000>;
+			regulator-max-microvolt = <3544000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		/* ldo11 - LMX */
+
+		vreg_l12a_1p8: ldo12 {
+			regulator-name = "vreg_l12a_1p8";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1880000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		/* no ldo13 */
+
+		vreg_l14a_1p8: ldo14 {
+			regulator-name = "vreg_l14a_1p8";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1880000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l15a_1p8: ldo15 {
+			regulator-name = "vreg_l15a_1p8";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		/* no ldo16 - system */
+
+		vreg_l17a_3p26: ldo17 {
+			regulator-name = "vreg_l17a_3p26";
+			regulator-min-microvolt = <3200000>;
+			regulator-max-microvolt = <3544000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l18a_1p2: ldo18 {
+			regulator-name = "vreg_l18a_1p2";
+			regulator-min-microvolt = <1200000>;
+			regulator-max-microvolt = <1304000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+	};
+
+};
+
+&gpi_dma0 {
+	status = "okay";
+};
+
+&gpi_dma1 {
+	status = "okay";
+};
+
+&gpu {
+	status = "okay";
+};
+
+&gpu_zap_shader {
+	firmware-name = "qcom/sar2130p/a620_zap.mbn";
+};
+
+&pon_pwrkey {
+	status = "okay";
+};
+
+&pon_resin {
+	linux,code = <KEY_VOLUMEDOWN>;
+
+	status = "okay";
+};
+
+&qupv3_id_0 {
+	status = "okay";
+};
+
+&qupv3_id_1 {
+	status = "okay";
+};
+
+&i2c4 {
+	clock-frequency = <400000>;
+
+	status = "okay";
+};
+
+&i2c8 {
+	clock-frequency = <400000>;
+
+	status = "okay";
+
+	ptn3222: redriver@4f {
+		compatible = "nxp,ptn3222";
+		reg = <0x4f>;
+
+		reset-gpios = <&tlmm 99 GPIO_ACTIVE_LOW>;
+
+		vdd3v3-supply = <&vreg_l2a_3p1>;
+		vdd1v8-supply = <&vreg_l15a_1p8>;
+
+		#phy-cells = <0>;
+	};
+};
+
+&i2c10 {
+	clock-frequency = <400000>;
+
+	status = "okay";
+};
+
+&pcie0 {
+	perst-gpios = <&tlmm 55 GPIO_ACTIVE_LOW>;
+	wake-gpios = <&tlmm 57 GPIO_ACTIVE_HIGH>;
+
+	pinctrl-0 = <&pcie0_default_state>;
+	pinctrl-names = "default";
+
+	status = "okay";
+};
+
+&pcieport0 {
+	wifi@0 {
+		compatible = "pci17cb,1107";
+		reg = <0x10000 0x0 0x0 0x0 0x0>;
+
+		vddaon-supply = <&vreg_pmu_aon_0p59>;
+		vddwlcx-supply = <&vreg_pmu_wlcx_0p8>;
+		vddwlmx-supply = <&vreg_pmu_wlmx_0p85>;
+		vddrfacmn-supply = <&vreg_pmu_rfa_cmn>;
+		vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>;
+		vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>;
+		vddrfa1p8-supply = <&vreg_pmu_rfa_1p8>;
+		vddpcie0p9-supply = <&vreg_pmu_pcie_0p9>;
+		vddpcie1p8-supply = <&vreg_pmu_pcie_1p8>;
+	};
+};
+
+&pcie0_phy {
+	vdda-phy-supply = <&vreg_l8a_0p88>;
+	vdda-pll-supply = <&vreg_l3a_1p2>;
+
+	status = "okay";
+};
+
+&pm8150_adc {
+	channel@4c {
+		reg = <ADC5_XO_THERM_100K_PU>;
+		qcom,ratiometric;
+		qcom,hw-settle-time = <200>;
+		label = "xo_therm";
+	};
+
+	channel@4d {
+		reg = <ADC5_AMUX_THM1_100K_PU>;
+		qcom,ratiometric;
+		qcom,hw-settle-time = <200>;
+		qcom,pre-scaling = <1 1>;
+		label = "skin_therm";
+	};
+
+	channel@4e {
+		/* msm-5.10 uses ADC5_AMUX_THM2 / 0x0e, although there is a pullup */
+		reg = <ADC5_AMUX_THM2_100K_PU>;
+		qcom,hw-settle-time = <200>;
+		qcom,pre-scaling = <1 1>;
+		label = "wifi_therm";
+	};
+};
+
+&pm8150_adc_tm {
+	status = "okay";
+
+	xo-therm@0 {
+		reg = <0>;
+		io-channels = <&pm8150_adc ADC5_XO_THERM_100K_PU>;
+		qcom,ratiometric;
+		qcom,hw-settle-time-us = <200>;
+	};
+
+	skin-therm@1 {
+		reg = <1>;
+		io-channels = <&pm8150_adc ADC5_AMUX_THM1_100K_PU>;
+		qcom,ratiometric;
+		qcom,hw-settle-time-us = <200>;
+	};
+
+	wifi-therm@2 {
+		reg = <2>;
+		/* msm-5.10 uses ADC5_AMUX_THM2, although there is a pullup */
+		io-channels = <&pm8150_adc ADC5_AMUX_THM2_100K_PU>;
+		qcom,hw-settle-time-us = <200>;
+	};
+};
+
+&remoteproc_adsp {
+	firmware-name = "qcom/sar2130p/adsp.mbn";
+
+	status = "okay";
+};
+
+&sdhc_1 {
+	vmmc-supply = <&vreg_l10a_2p95>;
+	vqmmc-supply = <&vreg_l7a_1p8>;
+
+	status = "okay";
+};
+
+&tlmm {
+	bt_en_state: bt-enable-state {
+		pins = "gpio46";
+		function = "gpio";
+		drive-strength = <16>;
+		bias-disable;
+	};
+
+	pcie0_default_state: pcie0-default-state {
+		perst-pins {
+			pins = "gpio55";
+			function = "gpio";
+			drive-strength = <2>;
+			bias-pull-down;
+		};
+
+		clkreq-pins {
+			pins = "gpio56";
+			function = "pcie0_clkreqn";
+			drive-strength = <2>;
+			bias-pull-up;
+		};
+
+		wake-pins {
+			pins = "gpio57";
+			function = "gpio";
+			drive-strength = <2>;
+			bias-pull-up;
+		};
+	};
+
+	pcie1_default_state: pcie1-default-state {
+		perst-pins {
+			pins = "gpio58";
+			function = "gpio";
+			drive-strength = <2>;
+			bias-pull-down;
+		};
+
+		clkreq-pins {
+			pins = "gpio59";
+			function = "pcie1_clkreqn";
+			drive-strength = <2>;
+			bias-pull-up;
+		};
+
+		wake-pins {
+			pins = "gpio60";
+			function = "gpio";
+			drive-strength = <2>;
+			bias-pull-up;
+		};
+	};
+
+	wlan_en_state: wlan-enable-state {
+		pins = "gpio45";
+		function = "gpio";
+		drive-strength = <16>;
+		bias-disable;
+	};
+};
+
+&uart7 {
+	status = "okay";
+
+	bluetooth {
+		compatible = "qcom,wcn7850-bt";
+
+		vddrfacmn-supply = <&vreg_pmu_rfa_cmn>;
+		vddaon-supply = <&vreg_pmu_aon_0p59>;
+		vddwlcx-supply = <&vreg_pmu_wlcx_0p8>;
+		vddwlmx-supply = <&vreg_pmu_wlmx_0p85>;
+		vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>;
+		vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>;
+		vddrfa1p8-supply = <&vreg_pmu_rfa_1p8>;
+
+		max-speed = <3200000>;
+	};
+};
+
+&uart11 {
+	status = "okay";
+};
+
+&usb_1 {
+	status = "okay";
+};
+
+&usb_1_hsphy {
+	vdd-supply = <&vreg_l8a_0p88>;
+	vdda12-supply = <&vreg_l3a_1p2>;
+
+	phys = <&ptn3222>;
+
+	status = "okay";
+};
+
+&usb_dp_qmpphy {
+	vdda-phy-supply = <&vreg_l3a_1p2>;
+	vdda-pll-supply = <&vreg_l1a_0p91>;
+
+	status = "okay";
+};
diff --git a/dts/upstream/src/arm64/qcom/sar2130p.dtsi b/dts/upstream/src/arm64/qcom/sar2130p.dtsi
new file mode 100644
index 00000000000..dd832e6816b
--- /dev/null
+++ b/dts/upstream/src/arm64/qcom/sar2130p.dtsi
@@ -0,0 +1,3123 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2024, Linaro Limited
+ */
+
+#include <dt-bindings/clock/qcom,rpmh.h>
+#include <dt-bindings/clock/qcom,sar2130p-gcc.h>
+#include <dt-bindings/clock/qcom,sar2130p-gpucc.h>
+#include <dt-bindings/clock/qcom,sm8550-tcsr.h>
+#include <dt-bindings/dma/qcom-gpi.h>
+#include <dt-bindings/interconnect/qcom,icc.h>
+#include <dt-bindings/interconnect/qcom,sar2130p-rpmh.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/mailbox/qcom-ipcc.h>
+#include <dt-bindings/phy/phy-qcom-qmp.h>
+#include <dt-bindings/power/qcom-rpmpd.h>
+#include <dt-bindings/power/qcom,rpmhpd.h>
+#include <dt-bindings/soc/qcom,gpr.h>
+#include <dt-bindings/soc/qcom,rpmh-rsc.h>
+#include <dt-bindings/thermal/thermal.h>
+
+/ {
+	interrupt-parent = <&intc>;
+
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	chosen { };
+
+	clocks {
+		xo_board: xo-board {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <19200000>;
+		};
+
+		sleep_clk: sleep-clk {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <32764>;
+		};
+	};
+
+	cpus {
+		#address-cells = <2>;
+		#size-cells = <0>;
+
+		cpu0: cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a55";
+			reg = <0x0 0x0>;
+			clocks = <&cpufreq_hw 0>;
+			enable-method = "psci";
+			next-level-cache = <&l2_0>;
+			qcom,freq-domain = <&cpufreq_hw 0>;
+			power-domains = <&cpu_pd0>;
+			power-domain-names = "psci";
+			#cooling-cells = <2>;
+
+			l2_0: l2-cache {
+				compatible = "cache";
+				cache-level = <2>;
+				cache-unified;
+				next-level-cache = <&l3_0>;
+
+				l3_0: l3-cache {
+					compatible = "cache";
+					cache-level = <3>;
+					cache-unified;
+				};
+			};
+		};
+
+		cpu1: cpu@100 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a55";
+			reg = <0x0 0x100>;
+			clocks = <&cpufreq_hw 0>;
+			enable-method = "psci";
+			next-level-cache = <&l2_100>;
+			qcom,freq-domain = <&cpufreq_hw 0>;
+			power-domains = <&cpu_pd1>;
+			power-domain-names = "psci";
+			#cooling-cells = <2>;
+
+			l2_100: l2-cache {
+				compatible = "cache";
+				cache-level = <2>;
+				cache-unified;
+				next-level-cache = <&l3_0>;
+			};
+		};
+
+		cpu2: cpu@200 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a55";
+			reg = <0x0 0x200>;
+			clocks = <&cpufreq_hw 0>;
+			enable-method = "psci";
+			next-level-cache = <&l2_200>;
+			qcom,freq-domain = <&cpufreq_hw 0>;
+			power-domains = <&cpu_pd2>;
+			power-domain-names = "psci";
+			#cooling-cells = <2>;
+
+			l2_200: l2-cache {
+				compatible = "cache";
+				cache-level = <2>;
+				cache-unified;
+				next-level-cache = <&l3_0>;
+			};
+		};
+
+		cpu3: cpu@300 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a55";
+			reg = <0x0 0x300>;
+			clocks = <&cpufreq_hw 0>;
+			enable-method = "psci";
+			next-level-cache = <&l2_300>;
+			qcom,freq-domain = <&cpufreq_hw 0>;
+			power-domains = <&cpu_pd3>;
+			power-domain-names = "psci";
+			#cooling-cells = <2>;
+
+			l2_300: l2-cache {
+				compatible = "cache";
+				cache-level = <2>;
+				cache-unified;
+				next-level-cache = <&l3_0>;
+			};
+		};
+
+		cpu-map {
+			cluster0 {
+				core0 {
+					cpu = <&cpu0>;
+				};
+
+				core1 {
+					cpu = <&cpu1>;
+				};
+
+				core2 {
+					cpu = <&cpu2>;
+				};
+
+				core3 {
+					cpu = <&cpu3>;
+				};
+			};
+		};
+
+		idle-states {
+			entry-method = "psci";
+
+			cpu_sleep_0: cpu-sleep-0-0 {
+				compatible = "arm,idle-state";
+				idle-state-name = "silver-power-collapse";
+				arm,psci-suspend-param = <0x40000003>;
+				entry-latency-us = <549>;
+				exit-latency-us = <901>;
+				min-residency-us = <1774>;
+				local-timer-stop;
+			};
+
+			cpu_sleep_1: cpu-sleep-0-1 {
+				compatible = "arm,idle-state";
+				idle-state-name = "silver-rail-power-collapse";
+				arm,psci-suspend-param = <0x40000004>;
+				entry-latency-us = <702>;
+				exit-latency-us = <915>;
+				min-residency-us = <4001>;
+				local-timer-stop;
+			};
+		};
+
+		domain-idle-states {
+			cluster_sleep_0: cluster-sleep-0 {
+				compatible = "domain-idle-state";
+				arm,psci-suspend-param = <0x41000044>;
+				entry-latency-us = <2752>;
+				exit-latency-us = <3048>;
+				min-residency-us = <6118>;
+			};
+
+			cluster_sleep_1: cluster-sleep-1 {
+				compatible = "domain-idle-state";
+				arm,psci-suspend-param = <0x41002344>;
+				entry-latency-us = <3263>;
+				exit-latency-us = <4562>;
+				min-residency-us = <8467>;
+			};
+
+			cluster_sleep_2: cluster-sleep-2 {
+				compatible = "domain-idle-state";
+				arm,psci-suspend-param = <0x4100c344>;
+				entry-latency-us = <3638>;
+				exit-latency-us = <6562>;
+				min-residency-us = <9862>;
+			};
+		};
+	};
+
+	firmware {
+		scm: scm {
+			compatible = "qcom,scm-sar2130p", "qcom,scm";
+			qcom,dload-mode = <&tcsr_mutex 0x13000>;
+			interconnects = <&system_noc MASTER_CRYPTO QCOM_ICC_TAG_ALWAYS
+					 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+		};
+	};
+
+	clk_virt: interconnect-0 {
+		compatible = "qcom,sar2130p-clk-virt";
+		#interconnect-cells = <2>;
+		qcom,bcm-voters = <&apps_bcm_voter>;
+	};
+
+	mc_virt: interconnect-1 {
+		compatible = "qcom,sar2130p-mc-virt";
+		#interconnect-cells = <2>;
+		qcom,bcm-voters = <&apps_bcm_voter>;
+	};
+
+	memory@80000000 {
+		device_type = "memory";
+		/* We expect the bootloader to fill in the size */
+		reg = <0x0 0x80000000 0x0 0x0>;
+	};
+
+	pmu {
+		compatible = "arm,armv8-pmuv3";
+		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
+	};
+
+	psci {
+		compatible = "arm,psci-1.0";
+		method = "smc";
+
+		cpu_pd0: power-domain-cpu0 {
+			#power-domain-cells = <0>;
+			power-domains = <&cluster_pd>;
+			domain-idle-states = <&cpu_sleep_0>, <&cpu_sleep_1>;
+		};
+
+		cpu_pd1: power-domain-cpu1 {
+			#power-domain-cells = <0>;
+			power-domains = <&cluster_pd>;
+			domain-idle-states = <&cpu_sleep_0>, <&cpu_sleep_1>;
+		};
+
+		cpu_pd2: power-domain-cpu2 {
+			#power-domain-cells = <0>;
+			power-domains = <&cluster_pd>;
+			domain-idle-states = <&cpu_sleep_0>, <&cpu_sleep_1>;
+		};
+
+		cpu_pd3: power-domain-cpu3 {
+			#power-domain-cells = <0>;
+			power-domains = <&cluster_pd>;
+			domain-idle-states = <&cpu_sleep_0>, <&cpu_sleep_1>;
+		};
+
+		cluster_pd: power-domain-cpu-cluster0 {
+			#power-domain-cells = <0>;
+			domain-idle-states = <&cluster_sleep_0>, <&cluster_sleep_1>, <&cluster_sleep_2>;
+		};
+	};
+
+	reserved_memory: reserved-memory {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		hyp_mem: hyp@80000000 {
+			reg = <0x0 0x80000000 0x0 0x600000>;
+			no-map;
+		};
+
+		xbl_dt_log_mem: xbl-dt-log@80600000 {
+			reg = <0x0 0x80600000 0x0 0x40000>;
+			no-map;
+		};
+
+		xbl_ramdump_mem: xbl-ramdump@80640000 {
+			reg = <0x0 0x80640000 0x0 0x1c0000>;
+			no-map;
+		};
+
+		aop_image_mem: aop-image@80800000 {
+			reg = <0x0 0x80800000 0x0 0x60000>;
+			no-map;
+		};
+
+		aop_cmd_db_mem: aop-cmd-db@80860000 {
+			compatible = "qcom,cmd-db";
+			reg = <0x0 0x80860000 0x0 0x20000>;
+			no-map;
+		};
+
+		aop_config_mem: aop-config@80880000 {
+			reg = <0x0 0x80880000 0x0 0x20000>;
+			no-map;
+		};
+
+		tme_crash_dump_mem: tme-crash-dump@808a0000 {
+			reg = <0x0 0x808a0000 0x0 0x40000>;
+			no-map;
+		};
+
+		tme_log_mem: tme-log@808e0000 {
+			reg = <0x0 0x808e0000 0x0 0x4000>;
+			no-map;
+		};
+
+		uefi_log_mem: uefi-log@808e4000 {
+			reg = <0x0 0x808e4000 0x0 0x10000>;
+			no-map;
+		};
+
+		secdata_apss_mem: secdata-apss@808ff000 {
+			reg = <0x0 0x808ff000 0x0 0x1000>;
+			no-map;
+		};
+
+		smem: smem@80900000 {
+			compatible = "qcom,smem";
+			reg = <0x0 0x80900000 0x0 0x200000>;
+			hwlocks = <&tcsr_mutex 3>;
+			no-map;
+		};
+
+		cpucp_fw_mem: cpucp-fw@80b00000 {
+			reg = <0x0 0x80b00000 0x0 0x100000>;
+			no-map;
+		};
+
+		helios_ram_dump_mem: helios-ram-dump@80c00000 {
+			reg = <0x0 0x80c00000 0x0 0xe00000>;
+			no-map;
+		};
+
+		camera_mem: camera@84e00000 {
+			reg = <0x0 0x84e00000 0x0 0x800000>;
+			no-map;
+		};
+
+		video_mem: video@86f00000 {
+			reg = <0x0 0x86f00000 0x0 0x500000>;
+			no-map;
+		};
+
+		adsp_mem: adsp@87600000 {
+			reg = <0x0 0x87600000 0x0 0x1e00000>;
+			no-map;
+		};
+
+		cdsp_mem: cdsp@89400000 {
+			reg = <0x0 0x89400000 0x0 0xf00000>;
+			no-map;
+		};
+
+		ipa_fw_mem: ipa-fw@8a300000 {
+			reg = <0x0 0x8a300000 0x0 0x10000>;
+			no-map;
+		};
+
+		ipa_gsi_mem: ipa-gsi@8a3a0000 {
+			reg = <0x0 0x8a310000 0x0 0xa000>;
+			no-map;
+		};
+
+		gpu_micro_code_mem: gpu-micro-code@8a31a000 {
+			reg = <0x0 0x8a31a000 0x0 0x2000>;
+			no-map;
+		};
+
+		cvp_mem: cvp@8a400000 {
+			reg = <0x0 0x8a400000 0x0 0x700000>;
+			no-map;
+		};
+
+		xbl_sc_mem: xbl-sc@a6e00000 {
+			no-map;
+			reg = <0x0 0xa6e00000 0x0 0x40000>;
+		};
+
+		global_sync_mem: global-sync@a6f00000 {
+			no-map;
+			reg = <0x0 0xa6f00000 0x0 0x100000>;
+		};
+
+		tz_stat_mem: tz-stat@e8800000 {
+			no-map;
+			reg = <0x0 0xe8800000 0x0 0x100000>;
+		};
+
+		tags_mem: tags@e8900000 {
+			no-map;
+			reg = <0x0 0xe8900000 0x0 0x500000>;
+		};
+
+		qtee_mem: qtee@e8e00000 {
+			no-map;
+			reg = <0x0 0xe8e00000 0x0 0x500000>;
+		};
+
+		trusted_apps_mem: trusted-apps@e9300000 {
+			no-map;
+			reg = <0x0 0xe9300000 0x0 0xc00000>;
+		};
+	};
+
+	smp2p-adsp {
+		compatible = "qcom,smp2p";
+		qcom,smem = <443>, <429>;
+		interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
+					     IPCC_MPROC_SIGNAL_SMP2P
+					     IRQ_TYPE_EDGE_RISING>;
+		mboxes = <&ipcc IPCC_CLIENT_LPASS
+				IPCC_MPROC_SIGNAL_SMP2P>;
+
+		qcom,local-pid = <0>;
+		qcom,remote-pid = <2>;
+
+		smp2p_adsp_out: master-kernel {
+			qcom,entry-name = "master-kernel";
+			#qcom,smem-state-cells = <1>;
+		};
+
+		smp2p_adsp_in: slave-kernel {
+			qcom,entry-name = "slave-kernel";
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+	};
+
+	smp2p-cdsp {
+		compatible = "qcom,smp2p";
+		qcom,smem = <94>, <432>;
+		interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
+					     IPCC_MPROC_SIGNAL_SMP2P
+					     IRQ_TYPE_EDGE_RISING>;
+		mboxes = <&ipcc IPCC_CLIENT_CDSP
+				IPCC_MPROC_SIGNAL_SMP2P>;
+
+		qcom,local-pid = <0>;
+		qcom,remote-pid = <5>;
+
+		smp2p_cdsp_out: master-kernel {
+			qcom,entry-name = "master-kernel";
+			#qcom,smem-state-cells = <1>;
+		};
+
+		smp2p_cdsp_in: slave-kernel {
+			qcom,entry-name = "slave-kernel";
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+	};
+
+	soc: soc@0 {
+		compatible = "simple-bus";
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges = <0 0 0 0 0x10 0>;
+		dma-ranges = <0 0 0 0 0x10 0>;
+
+		gcc: clock-controller@100000 {
+			compatible = "qcom,sar2130p-gcc";
+			reg = <0x0 0x00100000 0x0 0x1f4200>;
+			#clock-cells = <1>;
+			#reset-cells = <1>;
+			#power-domain-cells = <1>;
+			clocks = <&rpmhcc RPMH_CXO_CLK>,
+				 <&sleep_clk>,
+				 <&pcie0_phy>,
+				 <&pcie1_phy>,
+				 <&usb_dp_qmpphy QMP_USB43DP_USB3_PIPE_CLK>;
+		};
+
+		sdhc_1: mmc@7c4000 {
+			compatible = "qcom,sar2130p-sdhci", "qcom,sdhci-msm-v5";
+			reg = <0x0 0x007c4000 0x0 0x1000>,
+			      <0x0 0x007c5000 0x0 0x1000>;
+			reg-names = "hc", "cqhci";
+
+			iommus = <&apps_smmu 0x160 0x0>;
+			interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "hc_irq", "pwr_irq";
+
+			clocks = <&gcc GCC_SDCC1_AHB_CLK>,
+				 <&gcc GCC_SDCC1_APPS_CLK>,
+				 <&rpmhcc RPMH_CXO_CLK>;
+			clock-names = "iface", "core", "xo";
+			interconnects = <&system_noc MASTER_SDCC_1 QCOM_ICC_TAG_ALWAYS
+					 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
+					<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+					 &config_noc SLAVE_SDCC_1 QCOM_ICC_TAG_ALWAYS>;
+			interconnect-names = "sdhc-ddr","cpu-sdhc";
+			power-domains = <&rpmhpd RPMHPD_CX>;
+			operating-points-v2 = <&sdhc1_opp_table>;
+
+			pinctrl-0 = <&sdc1_default>;
+			pinctrl-1 = <&sdc1_sleep>;
+			pinctrl-names = "default", "sleep";
+
+			bus-width = <8>;
+			non-removable;
+			supports-cqe;
+
+			mmc-ddr-1_8v;
+			mmc-hs200-1_8v;
+			mmc-hs400-1_8v;
+			mmc-hs400-enhanced-strobe;
+
+			status = "disabled";
+
+			sdhc1_opp_table: opp-table {
+				compatible = "operating-points-v2";
+
+				opp-100000000 {
+					opp-hz = /bits/ 64 <100000000>;
+					required-opps = <&rpmhpd_opp_low_svs>;
+					opp-peak-kBps = <500000 200000>;
+					opp-avg-kBps = <104000 0>;
+				};
+
+				opp-384000000 {
+					opp-hz = /bits/ 64 <384000000>;
+					required-opps = <&rpmhpd_opp_nom>;
+					opp-peak-kBps = <2500000 1000000>;
+					opp-avg-kBps = <400000 0>;
+				};
+			};
+		};
+
+		gpi_dma0: dma-controller@900000 {
+			compatible = "qcom,sar2130p-gpi-dma", "qcom,sm6350-gpi-dma";
+			reg = <0x0 0x00900000 0x0 0x60000>;
+			interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>;
+			#dma-cells = <3>;
+			dma-channels = <12>;
+			dma-channel-mask = <0x7e>;
+			iommus = <&apps_smmu 0x76 0x0>;
+
+			status = "disabled";
+		};
+
+		qupv3_id_0: geniqup@9c0000 {
+			compatible = "qcom,geni-se-qup";
+			reg = <0x0 0x009c0000 0x0 0x2000>;
+			clock-names = "m-ahb", "s-ahb";
+			clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
+				 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
+			iommus = <&apps_smmu 0x63 0x0>;
+			interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
+					 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>;
+			interconnect-names = "qup-core";
+			#address-cells = <2>;
+			#size-cells = <2>;
+			ranges;
+
+			status = "disabled";
+
+			i2c0: i2c@980000 {
+				compatible = "qcom,geni-i2c";
+				reg = <0x0 0x00980000 0x0 0x4000>;
+				clock-names = "se";
+				clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
+				pinctrl-0 = <&qup_i2c0_data_clk>;
+				pinctrl-names = "default";
+				interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
+						 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
+						<&system_noc MASTER_A2NOC_SNOC QCOM_ICC_TAG_ALWAYS
+						 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>,
+						<&system_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
+						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+				interconnect-names = "qup-core", "qup-config", "qup-memory";
+				dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
+				       <&gpi_dma0 1 0 QCOM_GPI_I2C>;
+				dma-names = "tx", "rx";
+
+				status = "disabled";
+			};
+
+			spi0: spi@980000 {
+				compatible = "qcom,geni-spi";
+				reg = <0x0 0x00980000 0x0 0x4000>;
+				clock-names = "se";
+				clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
+				interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
+				pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs0>;
+				pinctrl-names = "default";
+				interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
+						 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
+						<&system_noc MASTER_A2NOC_SNOC QCOM_ICC_TAG_ALWAYS
+						 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>,
+						<&system_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
+						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+				interconnect-names = "qup-core", "qup-config", "qup-memory";
+				dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
+				       <&gpi_dma0 1 0 QCOM_GPI_SPI>;
+				dma-names = "tx", "rx";
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				status = "disabled";
+			};
+
+			i2c1: i2c@984000 {
+				compatible = "qcom,geni-i2c";
+				reg = <0x0 0x00984000 0x0 0x4000>;
+				clock-names = "se";
+				clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
+				pinctrl-0 = <&qup_i2c1_data_clk>;
+				pinctrl-names = "default";
+				interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
+						 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
+						<&system_noc MASTER_A2NOC_SNOC QCOM_ICC_TAG_ALWAYS
+						 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>,
+						<&system_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
+						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+				interconnect-names = "qup-core", "qup-config", "qup-memory";
+				dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
+				       <&gpi_dma0 1 1 QCOM_GPI_I2C>;
+				dma-names = "tx", "rx";
+
+				status = "disabled";
+			};
+
+			spi1: spi@984000 {
+				compatible = "qcom,geni-spi";
+				reg = <0x0 0x00984000 0x0 0x4000>;
+				clock-names = "se";
+				clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
+				interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
+				pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>;
+				pinctrl-names = "default";
+				interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
+						 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
+						<&system_noc MASTER_A2NOC_SNOC QCOM_ICC_TAG_ALWAYS
+						 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>,
+						<&system_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
+						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+				interconnect-names = "qup-core", "qup-config", "qup-memory";
+				dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
+				       <&gpi_dma0 1 1 QCOM_GPI_SPI>;
+				dma-names = "tx", "rx";
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				status = "disabled";
+			};
+
+			i2c2: i2c@988000 {
+				compatible = "qcom,geni-i2c";
+				reg = <0x0 0x00988000 0x0 0x4000>;
+				clock-names = "se";
+				clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
+				pinctrl-0 = <&qup_i2c2_data_clk>;
+				pinctrl-names = "default";
+				interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
+						 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
+						<&system_noc MASTER_A2NOC_SNOC QCOM_ICC_TAG_ALWAYS
+						 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>,
+						<&system_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
+						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+				interconnect-names = "qup-core", "qup-config", "qup-memory";
+				dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
+				       <&gpi_dma0 1 2 QCOM_GPI_I2C>;
+				dma-names = "tx", "rx";
+
+				status = "disabled";
+			};
+
+			spi2: spi@988000 {
+				compatible = "qcom,geni-spi";
+				reg = <0x0 0x00988000 0x0 0x4000>;
+				clock-names = "se";
+				clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
+				interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
+				pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>;
+				pinctrl-names = "default";
+				interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
+						 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
+						<&system_noc MASTER_A2NOC_SNOC QCOM_ICC_TAG_ALWAYS
+						 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>,
+						<&system_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
+						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+				interconnect-names = "qup-core", "qup-config", "qup-memory";
+				dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>,
+				       <&gpi_dma0 1 2 QCOM_GPI_SPI>;
+				dma-names = "tx", "rx";
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				status = "disabled";
+			};
+
+
+			i2c3: i2c@98c000 {
+				compatible = "qcom,geni-i2c";
+				reg = <0x0 0x0098c000 0x0 0x4000>;
+				clock-names = "se";
+				clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
+				pinctrl-0 = <&qup_i2c3_data_clk>;
+				pinctrl-names = "default";
+				interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
+						 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
+						<&system_noc MASTER_A2NOC_SNOC QCOM_ICC_TAG_ALWAYS
+						 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>,
+						<&system_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
+						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+				interconnect-names = "qup-core", "qup-config", "qup-memory";
+				dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>,
+				       <&gpi_dma0 1 3 QCOM_GPI_I2C>;
+				dma-names = "tx", "rx";
+
+				status = "disabled";
+			};
+
+			spi3: spi@98c000 {
+				compatible = "qcom,geni-spi";
+				reg = <0x0 0x0098c000 0x0 0x4000>;
+				clock-names = "se";
+				clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
+				interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
+				pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs0>;
+				pinctrl-names = "default";
+				interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
+						 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
+						<&system_noc MASTER_A2NOC_SNOC QCOM_ICC_TAG_ALWAYS
+						 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>,
+						<&system_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
+						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+				interconnect-names = "qup-core", "qup-config", "qup-memory";
+				dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>,
+				       <&gpi_dma0 1 3 QCOM_GPI_SPI>;
+				dma-names = "tx", "rx";
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				status = "disabled";
+			};
+
+			i2c4: i2c@990000 {
+				compatible = "qcom,geni-i2c";
+				reg = <0x0 0x00990000 0x0 0x4000>;
+				clock-names = "se";
+				clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
+				pinctrl-0 = <&qup_i2c4_data_clk>;
+				pinctrl-names = "default";
+				interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
+						 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
+						<&system_noc MASTER_A2NOC_SNOC QCOM_ICC_TAG_ALWAYS
+						 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>,
+						<&system_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
+						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+				interconnect-names = "qup-core", "qup-config", "qup-memory";
+				dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
+				       <&gpi_dma0 1 4 QCOM_GPI_I2C>;
+				dma-names = "tx", "rx";
+
+				status = "disabled";
+			};
+
+			spi4: spi@990000 {
+				compatible = "qcom,geni-spi";
+				reg = <0x0 0x00990000 0x0 0x4000>;
+				clock-names = "se";
+				clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
+				interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
+				pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs0>;
+				pinctrl-names = "default";
+				interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
+						 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
+						<&system_noc MASTER_A2NOC_SNOC QCOM_ICC_TAG_ALWAYS
+						 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>,
+						<&system_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
+						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+				interconnect-names = "qup-core", "qup-config", "qup-memory";
+				dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>,
+				       <&gpi_dma0 1 4 QCOM_GPI_SPI>;
+				dma-names = "tx", "rx";
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				status = "disabled";
+			};
+
+			i2c5: i2c@994000 {
+				compatible = "qcom,geni-i2c";
+				reg = <0x0 0x00994000 0x0 0x4000>;
+				clock-names = "se";
+				clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
+				pinctrl-0 = <&qup_i2c5_data_clk>;
+				pinctrl-names = "default";
+				interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
+						 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
+						<&system_noc MASTER_A2NOC_SNOC QCOM_ICC_TAG_ALWAYS
+						 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>,
+						<&system_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
+						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+				interconnect-names = "qup-core", "qup-config", "qup-memory";
+				dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>,
+				       <&gpi_dma0 1 5 QCOM_GPI_I2C>;
+				dma-names = "tx", "rx";
+
+				status = "disabled";
+			};
+
+			spi5: spi@994000 {
+				compatible = "qcom,geni-spi";
+				reg = <0x0 0x00994000 0x0 0x4000>;
+				clock-names = "se";
+				clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
+				interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
+				pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>;
+				pinctrl-names = "default";
+				interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
+						 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
+						<&system_noc MASTER_A2NOC_SNOC QCOM_ICC_TAG_ALWAYS
+						 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>,
+						<&system_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
+						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+				interconnect-names = "qup-core", "qup-config", "qup-memory";
+				dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>,
+				       <&gpi_dma0 1 5 QCOM_GPI_SPI>;
+				dma-names = "tx", "rx";
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				status = "disabled";
+			};
+		};
+
+		gpi_dma1: dma-controller@a00000 {
+			compatible = "qcom,sar2130p-gpi-dma", "qcom,sm6350-gpi-dma";
+			#dma-cells = <3>;
+			reg = <0x0 0x00a00000 0x0 0x60000>;
+			interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>;
+			dma-channels = <12>;
+			dma-channel-mask = <0x7e>;
+			iommus = <&apps_smmu 0x16 0x0>;
+
+			status = "disabled";
+		};
+
+		qupv3_id_1: geniqup@ac0000 {
+			compatible = "qcom,geni-se-qup";
+			reg = <0x0 0x00ac0000 0x0 0x6000>;
+			clock-names = "m-ahb", "s-ahb";
+			clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
+				 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
+			iommus = <&apps_smmu 0x3 0x0>;
+			interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
+					 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>;
+			interconnect-names = "qup-core";
+			#address-cells = <2>;
+			#size-cells = <2>;
+			ranges;
+
+			status = "disabled";
+
+			i2c6: i2c@a80000 {
+				compatible = "qcom,geni-i2c";
+				reg = <0x0 0x00a80000 0x0 0x4000>;
+				clock-names = "se";
+				clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
+				pinctrl-0 = <&qup_i2c6_data_clk>;
+				pinctrl-names = "default";
+				interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
+						 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
+						<&system_noc MASTER_A2NOC_SNOC QCOM_ICC_TAG_ALWAYS
+						 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>,
+						<&system_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
+						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+				interconnect-names = "qup-core", "qup-config", "qup-memory";
+				dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
+				       <&gpi_dma1 1 0 QCOM_GPI_I2C>;
+				dma-names = "tx", "rx";
+
+				status = "disabled";
+			};
+
+			spi6: spi@a80000 {
+				compatible = "qcom,geni-spi";
+				reg = <0x0 0x00a80000 0x0 0x4000>;
+				clock-names = "se";
+				clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
+				interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
+				pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>;
+				pinctrl-names = "default";
+				interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
+						 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
+						<&system_noc MASTER_A2NOC_SNOC QCOM_ICC_TAG_ALWAYS
+						 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>,
+						<&system_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
+						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+				interconnect-names = "qup-core", "qup-config", "qup-memory";
+				dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>,
+				       <&gpi_dma1 1 0 QCOM_GPI_SPI>;
+				dma-names = "tx", "rx";
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				status = "disabled";
+			};
+
+			i2c7: i2c@a84000 {
+				compatible = "qcom,geni-i2c";
+				reg = <0x0 0x00a84000 0x0 0x4000>;
+				clock-names = "se";
+				clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
+				pinctrl-0 = <&qup_i2c7_data_clk>;
+				pinctrl-names = "default";
+				interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
+						 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
+						<&system_noc MASTER_A2NOC_SNOC QCOM_ICC_TAG_ALWAYS
+						 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>,
+						<&system_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
+						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+				interconnect-names = "qup-core", "qup-config", "qup-memory";
+				dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
+				       <&gpi_dma1 1 1 QCOM_GPI_I2C>;
+				dma-names = "tx", "rx";
+
+				status = "disabled";
+			};
+
+			spi7: spi@a84000 {
+				compatible = "qcom,geni-spi";
+				reg = <0x0 0x00a84000 0x0 0x4000>;
+				clock-names = "se";
+				clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
+				interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
+				pinctrl-0 = <&qup_spi7_data_clk>, <&qup_spi7_cs>;
+				pinctrl-names = "default";
+				interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
+						 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
+						<&system_noc MASTER_A2NOC_SNOC QCOM_ICC_TAG_ALWAYS
+						 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>,
+						<&system_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
+						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+				interconnect-names = "qup-core", "qup-config", "qup-memory";
+				dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
+				       <&gpi_dma1 1 1 QCOM_GPI_SPI>;
+				dma-names = "tx", "rx";
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				status = "disabled";
+			};
+
+			uart7: serial@a84000 {
+				compatible = "qcom,geni-uart";
+				reg = <0x0 0x00a84000 0x0 0x4000>;
+				clock-names = "se";
+				clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
+				pinctrl-0 = <&qup_uart7_default>;
+				pinctrl-names = "default";
+				interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
+				interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
+						 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
+						<&system_noc MASTER_A2NOC_SNOC QCOM_ICC_TAG_ALWAYS
+						 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>;
+				interconnect-names = "qup-core", "qup-config";
+
+				status = "disabled";
+			};
+
+			i2c8: i2c@a88000 {
+				compatible = "qcom,geni-i2c";
+				reg = <0x0 0x00a88000 0x0 0x4000>;
+				clock-names = "se";
+				clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
+				pinctrl-0 = <&qup_i2c8_data_clk>;
+				pinctrl-names = "default";
+				interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
+						 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
+						<&system_noc MASTER_A2NOC_SNOC QCOM_ICC_TAG_ALWAYS
+						 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>,
+						<&system_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
+						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+				interconnect-names = "qup-core", "qup-config", "qup-memory";
+				dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
+				       <&gpi_dma1 1 2 QCOM_GPI_I2C>;
+				dma-names = "tx", "rx";
+
+				status = "disabled";
+			};
+
+			spi8: spi@a88000 {
+				compatible = "qcom,geni-spi";
+				reg = <0x0 0x00a88000 0x0 0x4000>;
+				clock-names = "se";
+				clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
+				interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
+				pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>;
+				pinctrl-names = "default";
+				interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
+						 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
+						<&system_noc MASTER_A2NOC_SNOC QCOM_ICC_TAG_ALWAYS
+						 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>,
+						<&system_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
+						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+				interconnect-names = "qup-core", "qup-config", "qup-memory";
+				dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>,
+				       <&gpi_dma1 1 2 QCOM_GPI_SPI>;
+				dma-names = "tx", "rx";
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				status = "disabled";
+			};
+
+			i2c9: i2c@a8c000 {
+				compatible = "qcom,geni-i2c";
+				reg = <0x0 0x00a8c000 0x0 0x4000>;
+				clock-names = "se";
+				clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
+				pinctrl-0 = <&qup_i2c9_data_clk>;
+				pinctrl-names = "default";
+				interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
+						 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
+						<&system_noc MASTER_A2NOC_SNOC QCOM_ICC_TAG_ALWAYS
+						 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>,
+						<&system_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
+						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+				interconnect-names = "qup-core", "qup-config", "qup-memory";
+				dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
+				       <&gpi_dma1 1 3 QCOM_GPI_I2C>;
+				dma-names = "tx", "rx";
+
+				status = "disabled";
+			};
+
+			spi9: spi@a8c000 {
+				compatible = "qcom,geni-spi";
+				reg = <0x0 0x00a8c000 0x0 0x4000>;
+				clock-names = "se";
+				clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
+				interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
+				pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>;
+				pinctrl-names = "default";
+				interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
+						 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
+						<&system_noc MASTER_A2NOC_SNOC QCOM_ICC_TAG_ALWAYS
+						 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>,
+						<&system_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
+						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+				interconnect-names = "qup-core", "qup-config", "qup-memory";
+				dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>,
+				       <&gpi_dma1 1 3 QCOM_GPI_SPI>;
+				dma-names = "tx", "rx";
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				status = "disabled";
+			};
+
+			i2c10: i2c@a90000 {
+				compatible = "qcom,geni-i2c";
+				reg = <0x0 0x00a90000 0x0 0x4000>;
+				clock-names = "se";
+				clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
+				pinctrl-0 = <&qup_i2c10_data_clk>;
+				pinctrl-names = "default";
+				interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
+						 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
+						<&system_noc MASTER_A2NOC_SNOC QCOM_ICC_TAG_ALWAYS
+						 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>,
+						<&system_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
+						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+				interconnect-names = "qup-core", "qup-config", "qup-memory";
+				dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
+				       <&gpi_dma1 1 4 QCOM_GPI_I2C>;
+				dma-names = "tx", "rx";
+
+				status = "disabled";
+			};
+
+			spi10: spi@a90000 {
+				compatible = "qcom,geni-spi";
+				reg = <0x0 0x00a90000 0x0 0x4000>;
+				clock-names = "se";
+				clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
+				interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
+				pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>;
+				pinctrl-names = "default";
+				interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
+						 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
+						<&system_noc MASTER_A2NOC_SNOC QCOM_ICC_TAG_ALWAYS
+						 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>,
+						<&system_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
+						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+				interconnect-names = "qup-core", "qup-config", "qup-memory";
+				dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>,
+				       <&gpi_dma1 1 4 QCOM_GPI_SPI>;
+				dma-names = "tx", "rx";
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				status = "disabled";
+			};
+
+			i2c11: i2c@a94000 {
+				compatible = "qcom,geni-i2c";
+				reg = <0x0 0x00a94000 0x0 0x4000>;
+				clock-names = "se";
+				clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
+				pinctrl-0 = <&qup_i2c11_data_clk>;
+				pinctrl-names = "default";
+				interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
+						 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
+						<&system_noc MASTER_A2NOC_SNOC QCOM_ICC_TAG_ALWAYS
+						 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>,
+						<&system_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
+						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+				interconnect-names = "qup-core", "qup-config", "qup-memory";
+				dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>,
+				       <&gpi_dma1 1 5 QCOM_GPI_I2C>;
+				dma-names = "tx", "rx";
+
+				status = "disabled";
+			};
+
+			spi11: spi@a94000 {
+				compatible = "qcom,geni-spi";
+				reg = <0x0 0x00a94000 0x0 0x4000>;
+				clock-names = "se";
+				clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
+				interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
+				pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>;
+				pinctrl-names = "default";
+				interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
+						 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
+						<&system_noc MASTER_A2NOC_SNOC QCOM_ICC_TAG_ALWAYS
+						 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>,
+						<&system_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
+						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+				interconnect-names = "qup-core", "qup-config", "qup-memory";
+				dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>,
+				       <&gpi_dma1 1 5 QCOM_GPI_SPI>;
+				dma-names = "tx", "rx";
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				status = "disabled";
+			};
+
+			uart11: serial@a94000 {
+				compatible = "qcom,geni-debug-uart";
+				reg = <0x0 0x00a94000 0x0 0x4000>;
+				clock-names = "se";
+				clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
+				pinctrl-0 = <&qup_uart11_default>;
+				pinctrl-names = "default";
+				interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
+				interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
+						 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
+						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+						 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>;
+				interconnect-names = "qup-core",
+						     "qup-config";
+
+				status = "disabled";
+			};
+		};
+
+		config_noc: interconnect@1500000 {
+			compatible = "qcom,sar2130p-config-noc";
+			reg = <0x0 0x01500000 0x0 0x10>;
+			#interconnect-cells = <2>;
+			qcom,bcm-voters = <&apps_bcm_voter>;
+		};
+
+		system_noc: interconnect@1680000 {
+			compatible = "qcom,sar2130p-system-noc";
+			reg = <0x0 0x01680000 0x0 0x29080>;
+			clocks = <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>;
+			#interconnect-cells = <2>;
+			qcom,bcm-voters = <&apps_bcm_voter>;
+		};
+
+		pcie_noc: interconnect@16c0000 {
+			compatible = "qcom,sar2130p-pcie-anoc";
+			reg = <0x0 0x016c0000 0x0 0xa080>;
+			clocks = <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>,
+				 <&gcc GCC_CFG_NOC_PCIE_ANOC_AHB_CLK>;
+			#interconnect-cells = <2>;
+			qcom,bcm-voters = <&apps_bcm_voter>;
+		};
+
+		mmss_noc: interconnect@1740000 {
+			compatible = "qcom,sar2130p-mmss-noc";
+			reg = <0x0 0x01740000 0x0 0x1f100>;
+			#interconnect-cells = <2>;
+			qcom,bcm-voters = <&apps_bcm_voter>;
+		};
+
+		pcie0: pcie@1c00000 {
+			device_type = "pci";
+			compatible = "qcom,sar2130p-pcie", "qcom,pcie-sm8550";
+			reg = <0x0 0x01c00000 0x0 0x3000>,
+			      <0x0 0x60000000 0x0 0xf1d>,
+			      <0x0 0x60000f20 0x0 0xa8>,
+			      <0x0 0x60001000 0x0 0x1000>,
+			      <0x0 0x60100000 0x0 0x100000>,
+			      <0x0 0x01c0c000 0x0 0x1000>;
+			reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
+			#address-cells = <3>;
+			#size-cells = <2>;
+			ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
+				 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>;
+			bus-range = <0x00 0xff>;
+
+			dma-coherent;
+
+			linux,pci-domain = <0>;
+			num-lanes = <2>;
+
+			interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "msi0",
+					  "msi1",
+					  "msi2",
+					  "msi3",
+					  "msi4",
+					  "msi5",
+					  "msi6",
+					  "msi7";
+			#interrupt-cells = <1>;
+			interrupt-map-mask = <0 0 0 0x7>;
+			interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
+					<0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
+					<0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
+					<0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
+
+			clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
+				 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
+				 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
+				 <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
+				 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
+				 <&gcc GCC_DDRSS_PCIE_SF_CLK>,
+				 <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>;
+			clock-names = "aux",
+				      "cfg",
+				      "bus_master",
+				      "bus_slave",
+				      "slave_q2a",
+				      "ddrss_sf_tbu",
+				      "noc_aggr";
+
+			interconnects = <&pcie_noc MASTER_PCIE_0 QCOM_ICC_TAG_ALWAYS
+					 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
+					<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+					 &config_noc SLAVE_PCIE_0 QCOM_ICC_TAG_ALWAYS>;
+			interconnect-names = "pcie-mem", "cpu-pcie";
+
+			iommu-map = <0x0   &apps_smmu 0x1c00 0x1>,
+				    <0x100 &apps_smmu 0x1c01 0x1>;
+
+			resets = <&gcc GCC_PCIE_0_BCR>;
+			reset-names = "pci";
+
+			power-domains = <&gcc PCIE_0_GDSC>;
+
+			phys = <&pcie0_phy>;
+			phy-names = "pciephy";
+
+			status = "disabled";
+
+			pcieport0: pcie@0 {
+				device_type = "pci";
+				reg = <0x0 0x0 0x0 0x0 0x0>;
+				bus-range = <0x01 0xff>;
+
+				#address-cells = <3>;
+				#size-cells = <2>;
+				ranges;
+			};
+		};
+
+		pcie0_phy: phy@1c06000 {
+			compatible = "qcom,sar2130p-qmp-gen3x2-pcie-phy";
+			reg = <0x0 0x01c06000 0x0 0x2000>;
+
+			clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
+				 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
+				 <&tcsr TCSR_PCIE_0_CLKREF_EN>,
+				 <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>,
+				 <&gcc GCC_PCIE_0_PIPE_CLK>;
+			clock-names = "aux", "cfg_ahb", "ref", "rchng",
+				      "pipe";
+
+			resets = <&gcc GCC_PCIE_0_PHY_BCR>;
+			reset-names = "phy";
+
+			assigned-clocks = <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>;
+			assigned-clock-rates = <100000000>;
+
+			power-domains = <&gcc PCIE_0_PHY_GDSC>;
+
+			#clock-cells = <0>;
+			clock-output-names = "pcie0_pipe_clk";
+
+			#phy-cells = <0>;
+
+			status = "disabled";
+		};
+
+		pcie1: pcie@1c08000 {
+			device_type = "pci";
+			compatible = "qcom,sar2130p-pcie", "qcom,pcie-sm8550";
+			reg = <0x0 0x01c08000 0x0 0x3000>,
+			      <0x0 0x40000000 0x0 0xf1d>,
+			      <0x0 0x40000f20 0x0 0xa8>,
+			      <0x0 0x40001000 0x0 0x1000>,
+			      <0x0 0x40100000 0x0 0x100000>,
+			      <0x0 0x01c0b000 0x0 0x1000>;
+			reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
+			#address-cells = <3>;
+			#size-cells = <2>;
+			ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
+				 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
+			bus-range = <0x00 0xff>;
+
+			dma-coherent;
+
+			linux,pci-domain = <1>;
+			num-lanes = <2>;
+
+			interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "msi0",
+					  "msi1",
+					  "msi2",
+					  "msi3",
+					  "msi4",
+					  "msi5",
+					  "msi6",
+					  "msi7";
+			#interrupt-cells = <1>;
+			interrupt-map-mask = <0 0 0 0x7>;
+			interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
+					<0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
+					<0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
+					<0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
+
+			clocks = <&gcc GCC_PCIE_1_AUX_CLK>,
+				 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
+				 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
+				 <&gcc GCC_PCIE_1_SLV_AXI_CLK>,
+				 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>,
+				 <&gcc GCC_DDRSS_PCIE_SF_CLK>,
+				 <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>,
+				 <&gcc GCC_CFG_NOC_PCIE_ANOC_AHB_CLK>,
+				 <&gcc GCC_QMIP_PCIE_AHB_CLK>;
+			clock-names = "aux",
+				      "cfg",
+				      "bus_master",
+				      "bus_slave",
+				      "slave_q2a",
+				      "ddrss_sf_tbu",
+				      "noc_aggr",
+				      "cnoc_sf_axi",
+				      "qmip_pcie_ahb";
+
+			assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
+			assigned-clock-rates = <19200000>;
+
+			interconnects = <&pcie_noc MASTER_PCIE_1 QCOM_ICC_TAG_ALWAYS
+					 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
+					<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+					 &config_noc SLAVE_PCIE_1 QCOM_ICC_TAG_ALWAYS>;
+			interconnect-names = "pcie-mem", "cpu-pcie";
+
+			iommu-map = <0x0   &apps_smmu 0x1e00 0x1>,
+				    <0x100 &apps_smmu 0x1e01 0x1>;
+
+			resets = <&gcc GCC_PCIE_1_BCR>,
+				<&gcc GCC_PCIE_1_LINK_DOWN_BCR>;
+			reset-names = "pci", "link_down";
+
+			power-domains = <&gcc PCIE_1_GDSC>;
+
+			phys = <&pcie1_phy>;
+			phy-names = "pciephy";
+
+			status = "disabled";
+
+			pcie@0 {
+				device_type = "pci";
+				reg = <0x0 0x0 0x0 0x0 0x0>;
+				bus-range = <0x01 0xff>;
+
+				#address-cells = <3>;
+				#size-cells = <2>;
+				ranges;
+			};
+		};
+
+		pcie1_phy: phy@1c0e000 {
+			compatible = "qcom,sar2130p-qmp-gen3x2-pcie-phy";
+			reg = <0x0 0x01c0e000 0x0 0x2000>;
+
+			clocks = <&gcc GCC_PCIE_1_AUX_CLK>,
+				 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
+				 <&tcsr TCSR_PCIE_1_CLKREF_EN>,
+				 <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>,
+				 <&gcc GCC_PCIE_1_PIPE_CLK>;
+			clock-names = "aux", "cfg_ahb", "ref", "rchng",
+				      "pipe";
+
+			resets = <&gcc GCC_PCIE_1_PHY_BCR>;
+			reset-names = "phy";
+
+			assigned-clocks = <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>;
+			assigned-clock-rates = <100000000>;
+
+			power-domains = <&gcc PCIE_1_PHY_GDSC>;
+
+			#clock-cells = <0>;
+			clock-output-names = "pcie1_pipe_clk";
+
+			#phy-cells = <0>;
+
+			status = "disabled";
+		};
+
+		tcsr_mutex: hwlock@1f40000 {
+			compatible = "qcom,tcsr-mutex";
+			reg = <0x0 0x01f40000 0x0 0x20000>;
+
+			#hwlock-cells = <1>;
+		};
+
+		tcsr: clock-controller@1fc0000 {
+			compatible = "qcom,sar2130p-tcsr", "syscon";
+			reg = <0x0 0x01fc0000 0x0 0x30000>;
+			clocks = <&rpmhcc RPMH_CXO_CLK>;
+			#clock-cells = <1>;
+			#reset-cells = <1>;
+		};
+
+		remoteproc_adsp: remoteproc@3000000 {
+			compatible = "qcom,sar2130p-adsp-pas";
+			reg = <0x0 0x03000000 0x0 0x10000>;
+
+			interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>,
+					      <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
+					      <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
+					      <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
+					      <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>;
+			interrupt-names = "wdog", "fatal", "ready",
+					  "handover", "stop-ack";
+
+			clocks = <&rpmhcc RPMH_CXO_CLK>;
+			clock-names = "xo";
+
+			power-domains = <&rpmhpd RPMHPD_LCX>,
+					<&rpmhpd RPMHPD_LMX>;
+			power-domain-names = "lcx", "lmx";
+
+			memory-region = <&adsp_mem>;
+
+			qcom,qmp = <&aoss_qmp>;
+
+			qcom,smem-states = <&smp2p_adsp_out 0>;
+			qcom,smem-state-names = "stop";
+
+			status = "disabled";
+
+			remoteproc_adsp_glink: glink-edge {
+				interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
+							     IPCC_MPROC_SIGNAL_GLINK_QMP
+							     IRQ_TYPE_EDGE_RISING>;
+				mboxes = <&ipcc IPCC_CLIENT_LPASS
+						IPCC_MPROC_SIGNAL_GLINK_QMP>;
+
+				label = "lpass";
+				qcom,remote-pid = <2>;
+
+				gpr {
+					compatible = "qcom,gpr";
+					qcom,glink-channels = "adsp_apps";
+					qcom,domain = <GPR_DOMAIN_ID_ADSP>;
+					qcom,intents = <512 20>;
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					q6apm: service@1 {
+						compatible = "qcom,q6apm";
+						reg = <GPR_APM_MODULE_IID>;
+						#sound-dai-cells = <0>;
+						qcom,protection-domain = "avs/audio",
+									 "msm/adsp/audio_pd";
+
+						q6apmdai: dais {
+							compatible = "qcom,q6apm-dais";
+							iommus = <&apps_smmu 0x1801 0x0>;
+						};
+
+						q6apmbedai: bedais {
+							compatible = "qcom,q6apm-lpass-dais";
+							#sound-dai-cells = <1>;
+						};
+					};
+
+					q6prm: service@2 {
+						compatible = "qcom,q6prm";
+						reg = <GPR_PRM_MODULE_IID>;
+						qcom,protection-domain = "avs/audio",
+									 "msm/adsp/audio_pd";
+
+						q6prmcc: clock-controller {
+							compatible = "qcom,q6prm-lpass-clocks";
+							#clock-cells = <2>;
+						};
+					};
+				};
+
+				fastrpc {
+					compatible = "qcom,fastrpc";
+					qcom,glink-channels = "fastrpcglink-apps-dsp";
+					label = "adsp";
+					qcom,non-secure-domain;
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					compute-cb@3 {
+						compatible = "qcom,fastrpc-compute-cb";
+						reg = <3>;
+						iommus = <&apps_smmu 0x1803 0x0>;
+					};
+
+					compute-cb@4 {
+						compatible = "qcom,fastrpc-compute-cb";
+						reg = <4>;
+						iommus = <&apps_smmu 0x1804 0x0>;
+					};
+
+					compute-cb@5 {
+						compatible = "qcom,fastrpc-compute-cb";
+						reg = <5>;
+						iommus = <&apps_smmu 0x1805 0x0>;
+					};
+
+					compute-cb@6 {
+						compatible = "qcom,fastrpc-compute-cb";
+						reg = <6>;
+						iommus = <&apps_smmu 0x1806 0x0>;
+					};
+				};
+			};
+		};
+
+		gpu: gpu@3d00000 {
+			compatible = "qcom,adreno-621.0", "qcom,adreno";
+			reg = <0x0 0x03d00000 0x0 0x40000>,
+			      <0x0 0x03d9e000 0x0 0x2000>,
+			      <0x0 0x03d61000 0x0 0x800>;
+			reg-names = "kgsl_3d0_reg_memory",
+				    "cx_mem",
+				    "cx_dbgc";
+
+			interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
+
+			iommus = <&adreno_smmu 0 0x401>;
+
+			operating-points-v2 = <&gpu_opp_table>;
+
+			qcom,gmu = <&gmu>;
+
+			nvmem-cells = <&gpu_speed_bin>;
+			nvmem-cell-names = "speed_bin";
+			#cooling-cells = <2>;
+
+			status = "disabled";
+
+			gpu_zap_shader: zap-shader {
+				memory-region = <&gpu_micro_code_mem>;
+			};
+
+			gpu_opp_table: opp-table {
+				compatible = "operating-points-v2";
+
+				opp-843000000 {
+					opp-hz = /bits/ 64 <843000000>;
+					opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
+					opp-supported-hw = <0x1>;
+				};
+
+				opp-780000000 {
+					opp-hz = /bits/ 64 <780000000>;
+					opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
+					opp-supported-hw = <0x1>;
+				};
+
+				opp-644000000 {
+					opp-hz = /bits/ 64 <644000000>;
+					opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
+					opp-supported-hw = <0x3>;
+				};
+
+				opp-570000000 {
+					opp-hz = /bits/ 64 <570000000>;
+					opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
+					opp-supported-hw = <0x3>;
+				};
+
+				opp-450000000 {
+					opp-hz = /bits/ 64 <450000000>;
+					opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
+					opp-supported-hw = <0x3>;
+				};
+
+				opp-320000000 {
+					opp-hz = /bits/ 64 <320000000>;
+					opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
+					opp-supported-hw = <0x3>;
+				};
+
+				opp-235000000 {
+					opp-hz = /bits/ 64 <235000000>;
+					opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
+					opp-supported-hw = <0x3>;
+				};
+			};
+		};
+
+		gmu: gmu@3d6a000 {
+			compatible = "qcom,adreno-gmu-621.0", "qcom,adreno-gmu";
+			reg = <0x0 0x03d6a000 0x0 0x35000>,
+			      <0x0 0x03de0000 0x0 0x10000>,
+			      <0x0 0x0b290000 0x0 0x10000>;
+			reg-names = "gmu", "rscc", "gmu_pdc";
+
+			interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "hfi", "gmu";
+
+			clocks = <&gpucc GPU_CC_AHB_CLK>,
+				 <&gpucc GPU_CC_CX_GMU_CLK>,
+				 <&gpucc GPU_CC_CXO_CLK>,
+				 <&gcc GCC_DDRSS_GPU_AXI_CLK>,
+				 <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
+				 <&gpucc GPU_CC_HUB_CX_INT_CLK>;
+			clock-names = "ahb",
+				      "gmu",
+				      "cxo",
+				      "axi",
+				      "memnoc",
+				      "hub";
+
+			power-domains = <&gpucc GPU_CX_GDSC>,
+					<&gpucc GPU_GX_GDSC>;
+			power-domain-names = "cx",
+					     "gx";
+
+			iommus = <&adreno_smmu 5 0x400>;
+
+			qcom,qmp = <&aoss_qmp>;
+
+			operating-points-v2 = <&gmu_opp_table>;
+
+			gmu_opp_table: opp-table {
+				compatible = "operating-points-v2";
+
+				opp-220000000 {
+					opp-hz = /bits/ 64 <220000000>;
+					opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
+				};
+
+				opp-550000000 {
+					opp-hz = /bits/ 64 <550000000>;
+					opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
+				};
+			};
+		};
+
+		gpucc: clock-controller@3d90000 {
+			compatible = "qcom,sar2130p-gpucc";
+			reg = <0x0 0x03d90000 0x0 0xa000>;
+
+			clocks = <&rpmhcc RPMH_CXO_CLK>,
+				 <&gcc GCC_GPU_GPLL0_CLK_SRC>,
+				 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
+
+			#clock-cells = <1>;
+			#reset-cells = <1>;
+			#power-domain-cells = <1>;
+		};
+
+		adreno_smmu: iommu@3da0000 {
+			compatible = "qcom,sar2130p-smmu-500", "qcom,adreno-smmu",
+				     "qcom,smmu-500", "arm,mmu-500";
+			reg = <0x0 0x03da0000 0x0 0x10000>;
+			#iommu-cells = <2>;
+			#global-interrupts = <1>;
+			interrupts = <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>;
+
+			clocks = <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>,
+				 <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
+				 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>,
+				 <&gpucc GPU_CC_AHB_CLK>;
+			clock-names = "hlos",
+				      "bus",
+				      "iface",
+				      "ahb";
+			power-domains = <&gpucc GPU_CX_GDSC>;
+			dma-coherent;
+		};
+
+		usb_1_hsphy: phy@88e3000 {
+			compatible = "qcom,sar2130p-snps-eusb2-phy",
+				     "qcom,sm8550-snps-eusb2-phy";
+			reg = <0x0 0x088e3000 0x0 0x154>;
+			#phy-cells = <0>;
+
+			clocks = <&tcsr TCSR_USB2_CLKREF_EN>;
+			clock-names = "ref";
+
+			resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
+
+			status = "disabled";
+		};
+
+		usb_dp_qmpphy: phy@88e8000 {
+			compatible = "qcom,sar2130p-qmp-usb3-dp-phy";
+			reg = <0x0 0x088e8000 0x0 0x3000>;
+
+			clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
+				 <&rpmhcc RPMH_CXO_CLK>,
+				 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
+				 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
+			clock-names = "aux", "ref", "com_aux", "usb3_pipe";
+
+			power-domains = <&gcc USB3_PHY_GDSC>;
+
+			resets = <&gcc GCC_USB3_PHY_PRIM_BCR>,
+				 <&gcc GCC_USB3_DP_PHY_PRIM_BCR>;
+			reset-names = "phy", "common";
+
+			#clock-cells = <1>;
+			#phy-cells = <1>;
+
+			orientation-switch;
+
+			status = "disabled";
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					reg = <0>;
+
+					usb_dp_qmpphy_out: endpoint {
+					};
+				};
+
+				port@1 {
+					reg = <1>;
+
+					usb_dp_qmpphy_usb_ss_in: endpoint {
+						remote-endpoint = <&usb_1_dwc3_ss>;
+					};
+				};
+
+				port@2 {
+					reg = <2>;
+
+					usb_dp_qmpphy_dp_in: endpoint {
+					};
+				};
+			};
+		};
+
+		usb_1: usb@a6f8800 {
+			compatible = "qcom,sar2130p-dwc3", "qcom,dwc3";
+			reg = <0x0 0x0a6f8800 0x0 0x400>;
+			#address-cells = <2>;
+			#size-cells = <2>;
+			ranges;
+
+			clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
+				 <&gcc GCC_USB30_PRIM_MASTER_CLK>,
+				 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
+				 <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
+				 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
+				 <&tcsr TCSR_USB3_CLKREF_EN>;
+			clock-names = "cfg_noc",
+				      "core",
+				      "iface",
+				      "sleep",
+				      "mock_utmi",
+				      "xo";
+
+			assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
+					  <&gcc GCC_USB30_PRIM_MASTER_CLK>;
+			assigned-clock-rates = <19200000>, <200000000>;
+
+			interrupts-extended = <&intc GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>,
+					      <&intc GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>,
+					      <&pdc 14 IRQ_TYPE_EDGE_BOTH>,
+					      <&pdc 15 IRQ_TYPE_EDGE_BOTH>,
+					      <&pdc 17 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "pwr_event",
+					  "hs_phy_irq",
+					  "dp_hs_phy_irq",
+					  "dm_hs_phy_irq",
+					  "ss_phy_irq";
+
+			power-domains = <&gcc USB30_PRIM_GDSC>;
+			required-opps = <&rpmhpd_opp_nom>;
+
+			resets = <&gcc GCC_USB30_PRIM_BCR>;
+
+			interconnects = <&system_noc MASTER_USB3_0 QCOM_ICC_TAG_ALWAYS
+					 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
+					<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+					 &config_noc SLAVE_USB3_0 QCOM_ICC_TAG_ALWAYS>;
+			interconnect-names = "usb-ddr", "apps-usb";
+
+			status = "disabled";
+
+			usb_1_dwc3: usb@a600000 {
+				compatible = "snps,dwc3";
+				reg = <0x0 0x0a600000 0x0 0xcd00>;
+				interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>;
+				iommus = <&apps_smmu 0x20 0x0>;
+				phys = <&usb_1_hsphy>,
+				       <&usb_dp_qmpphy QMP_USB43DP_USB3_PHY>;
+				phy-names = "usb2-phy", "usb3-phy";
+
+				snps,has-lpm-erratum;
+				snps,hird-threshold = /bits/ 8 <0x0>;
+				snps,is-utmi-l1-suspend;
+				snps,dis-u1-entry-quirk;
+				snps,dis-u2-entry-quirk;
+				snps,dis_u2_susphy_quirk;
+				snps,dis_u3_susphy_quirk;
+				snps,parkmode-disable-ss-quirk;
+
+				tx-fifo-resize;
+				dma-coherent;
+				usb-role-switch;
+
+				ports {
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					port@0 {
+						reg = <0>;
+
+						usb_1_dwc3_hs: endpoint {
+						};
+					};
+
+					port@1 {
+						reg = <1>;
+
+						usb_1_dwc3_ss: endpoint {
+							remote-endpoint = <&usb_dp_qmpphy_usb_ss_in>;
+						};
+					};
+				};
+			};
+		};
+
+		pdc: interrupt-controller@b220000 {
+			compatible = "qcom,sar2130p-pdc", "qcom,pdc";
+			reg = <0x0 0x0b220000 0x0 0x30000>, <0x0 0x174000f0 0x0 0x64>;
+			qcom,pdc-ranges = <0 480 94>,
+					  <94 609 31>,
+					  <125 63 1>,
+					  <126 716 12>;
+			#interrupt-cells = <2>;
+			interrupt-parent = <&intc>;
+			interrupt-controller;
+		};
+
+		aoss_qmp: power-management@c300000 {
+			compatible = "qcom,sar2130p-aoss-qmp", "qcom,aoss-qmp";
+			reg = <0x0 0x0c300000 0x0 0x400>;
+			interrupt-parent = <&ipcc>;
+			interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP
+						     IRQ_TYPE_EDGE_RISING>;
+			mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>;
+
+			#clock-cells = <0>;
+		};
+
+		tsens0: thermal-sensor@c263000 {
+			compatible = "qcom,sar2130p-tsens", "qcom,tsens-v2";
+			reg = <0x0 0x0c263000 0x0 0x1000>, /* TM */
+			      <0x0 0x0c222000 0x0 0x1000>; /* SROT */
+			#qcom,sensors = <16>;
+			interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "uplow", "critical";
+			#thermal-sensor-cells = <1>;
+		};
+
+		sram@c3f0000 {
+			compatible = "qcom,rpmh-stats";
+			reg = <0x0 0x0c3f0000 0x0 0x400>;
+		};
+
+		arbiter@c400000 {
+			compatible = "qcom,sar2130p-spmi-pmic-arb",
+				     "qcom,x1e80100-spmi-pmic-arb";
+			reg = <0x0 0x0c400000 0x0 0x3000>,
+			      <0x0 0x0c500000 0x0 0x400000>,
+			      <0x0 0x0c440000 0x0 0x80000>;
+			reg-names = "core", "chnls", "obsrvr";
+
+			qcom,ee = <0>;
+			qcom,channel = <0>;
+
+			#address-cells = <2>;
+			#size-cells = <2>;
+			ranges;
+
+			spmi_bus: spmi@c42d000 {
+				reg = <0x0 0x0c42d000 0x0 0x4000>,
+				      <0x0 0x0c4c0000 0x0 0x10000>;
+				reg-names = "cnfg", "intr";
+
+				interrupt-names = "periph_irq";
+				interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-controller;
+				#interrupt-cells = <4>;
+
+				#address-cells = <2>;
+				#size-cells = <0>;
+			};
+		};
+
+		ipcc: mailbox@ed18000 {
+			compatible = "qcom,sar2130p-ipcc", "qcom,ipcc";
+			reg = <0x0 0x0ed18000 0x0 0x1000>;
+
+			interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-controller;
+			#interrupt-cells = <3>;
+
+			#mbox-cells = <2>;
+		};
+
+		tlmm: pinctrl@f100000 {
+			compatible = "qcom,sar2130p-tlmm";
+			reg = <0x0 0x0f100000 0x0 0x300000>;
+			interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			gpio-ranges = <&tlmm 0 0 156>;
+			wakeup-parent = <&pdc>;
+
+			qup_i2c0_data_clk: qup-i2c0-data-clk-state {
+				/* SDA, SCL */
+				pins = "gpio0", "gpio1";
+				function = "qup0";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+
+			qup_i2c1_data_clk: qup-i2c1-data-clk-state {
+				/* SDA, SCL */
+				pins = "gpio2", "gpio3";
+				function = "qup1";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+
+			qup_i2c2_data_clk: qup-i2c2-data-clk-state {
+				/* SDA, SCL */
+				pins = "gpio22", "gpio23";
+				function = "qup2";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+
+			qup_i2c3_data_clk: qup-i2c3-data-clk-state {
+				/* SDA, SCL */
+				pins = "gpio16", "gpio17";
+				function = "qup3";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+
+			qup_i2c4_data_clk: qup-i2c4-data-clk-state {
+				/* SDA, SCL */
+				pins = "gpio20", "gpio21";
+				function = "qup4";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+
+			qup_i2c5_data_clk: qup-i2c5-data-clk-state {
+				/* SDA, SCL */
+				pins = "gpio95", "gpio96";
+				function = "qup5";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+
+			qup_i2c6_data_clk: qup-i2c6-data-clk-state {
+				/* SDA, SCL */
+				pins = "gpio91", "gpio92";
+				function = "qup6";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+
+			qup_i2c7_data_clk: qup-i2c7-data-clk-state {
+				/* SDA, SCL */
+				pins = "gpio8", "gpio9";
+				function = "qup7";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+
+			qup_i2c8_data_clk: qup-i2c8-data-clk-state {
+				/* SDA, SCL */
+				pins = "gpio8", "gpio9";
+				function = "qup8";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+
+			qup_i2c9_data_clk: qup-i2c9-data-clk-state {
+				/* SDA, SCL */
+				pins = "gpio109", "gpio110";
+				function = "qup9";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+
+			qup_i2c10_data_clk: qup-i2c10-data-clk-state {
+				/* SDA, SCL */
+				pins = "gpio4", "gpio5";
+				function = "qup10";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+
+			qup_i2c11_data_clk: qup-i2c11-data-clk-state {
+				/* SDA, SCL */
+				pins = "gpio28", "gpio30";
+				function = "qup11";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+
+			qup_spi0_cs0: qup-spi0-cs0-state {
+				pins = "gpio3";
+				function = "qup0";
+				drive-strength = <2>;
+				bias-disable;
+			};
+
+			qup_spi0_cs1: qup-spi0-cs1-state {
+				pins = "gpio93";
+				function = "qup0";
+				drive-strength = <2>;
+				bias-disable;
+			};
+
+			qup_spi0_data_clk: qup-spi0-data-clk-state {
+				/* MISO, MOSI, CLK */
+				pins = "gpio0", "gpio1", "gpio2";
+				function = "qup0";
+				drive-strength = <2>;
+				bias-disable;
+			};
+
+			qup_spi1_cs: qup-spi1-cs-state {
+				pins = "gpio62";
+				function = "qup1";
+				drive-strength = <2>;
+				bias-disable;
+			};
+
+			qup_spi1_data_clk: qup-spi1-data-clk-state {
+				/* MISO, MOSI, CLK */
+				pins = "gpio2", "gpio3", "gpio61";
+				function = "qup1";
+				drive-strength = <2>;
+				bias-disable;
+			};
+
+			qup_spi2_cs: qup-spi2-cs-state {
+				pins = "gpio13";
+				function = "qup2";
+				drive-strength = <2>;
+				bias-disable;
+			};
+
+			qup_spi2_data_clk: qup-spi2-data-clk-state {
+				/* MISO, MOSI, CLK */
+				pins = "gpio22", "gpio23", "gpio12";
+				function = "qup2";
+				drive-strength = <2>;
+				bias-disable;
+			};
+
+			qup_spi3_cs0: qup-spi3-cs0-state {
+				pins = "gpio19";
+				function = "qup3";
+				drive-strength = <2>;
+				bias-disable;
+			};
+
+			qup_spi3_cs1: qup-spi3-cs1-state {
+				pins = "gpio41";
+				function = "qup3";
+				drive-strength = <2>;
+				bias-disable;
+			};
+
+			qup_spi3_data_clk: qup-spi3-data-clk-state {
+				/* MISO, MOSI, CLK */
+				pins = "gpio16", "gpio17", "gpio18";
+				function = "qup3";
+				drive-strength = <2>;
+				bias-disable;
+			};
+
+			qup_spi4_cs0: qup-spi4-cs0-state {
+				pins = "gpio23";
+				function = "qup4";
+				drive-strength = <2>;
+				bias-disable;
+			};
+
+			qup_spi4_cs1: qup-spi4-cs1-state {
+				pins = "gpio94";
+				function = "qup4";
+				drive-strength = <2>;
+				bias-disable;
+			};
+
+			qup_spi4_data_clk: qup-spi4-data-clk-state {
+				/* MISO, MOSI, CLK */
+				pins = "gpio20", "gpio21", "gpio22";
+				function = "qup4";
+				drive-strength = <2>;
+				bias-disable;
+			};
+
+			qup_spi5_cs: qup-spi5-cs-state {
+				pins = "gpio98";
+				function = "qup5";
+				drive-strength = <2>;
+				bias-disable;
+			};
+
+			qup_spi5_data_clk: qup-spi5-data-clk-state {
+				/* MISO, MOSI, CLK */
+				pins = "gpio95", "gpio96", "gpio97";
+				function = "qup5";
+				drive-strength = <2>;
+				bias-disable;
+			};
+
+			qup_spi6_cs: qup-spi6-cs-state {
+				pins = "gpio63";
+				function = "qup6";
+				drive-strength = <2>;
+				bias-disable;
+			};
+
+			qup_spi6_data_clk: qup-spi6-data-clk-state {
+				/* MISO, MOSI, CLK */
+				pins = "gpio91", "gpio92", "gpio64";
+				function = "qup6";
+				drive-strength = <2>;
+				bias-disable;
+			};
+
+			qup_spi7_cs: qup-spi7-cs-state {
+				pins = "gpio27";
+				function = "qup7";
+				drive-strength = <2>;
+				bias-disable;
+			};
+
+			qup_spi7_data_clk: qup-spi7-data-clk-state {
+				/* MISO, MOSI, CLK */
+				pins = "gpio24", "gpio25", "gpio26";
+				function = "qup7";
+				drive-strength = <2>;
+				bias-disable;
+			};
+
+			qup_spi8_cs: qup-spi8-cs-state {
+				pins = "gpio11";
+				function = "qup8";
+				drive-strength = <2>;
+				bias-disable;
+			};
+
+			qup_spi8_data_clk: qup-spi8-data-clk-state {
+				/* MISO, MOSI, CLK */
+				pins = "gpio8", "gpio9", "gpio10";
+				function = "qup8";
+				drive-strength = <2>;
+				bias-disable;
+			};
+
+			qup_spi9_cs: qup-spi9-cs-state {
+				pins = "gpio35";
+				function = "qup9";
+				drive-strength = <2>;
+				bias-disable;
+			};
+
+			qup_spi9_data_clk: qup-spi9-data-clk-state {
+				/* MISO, MOSI, CLK */
+				pins = "gpio109", "gpio110", "gpio34";
+				function = "qup9";
+				drive-strength = <2>;
+				bias-disable;
+			};
+
+			qup_spi10_cs: qup-spi10-cs-state {
+				pins = "gpio7";
+				function = "qup10";
+				drive-strength = <2>;
+				bias-disable;
+			};
+
+			qup_spi10_data_clk: qup-spi10-data-clk-state {
+				/* MISO, MOSI, CLK */
+				pins = "gpio4", "gpio5", "gpio6";
+				function = "qup10";
+				drive-strength = <2>;
+				bias-disable;
+			};
+
+			qup_spi11_cs: qup-spi11-cs-state {
+				pins = "gpio15";
+				function = "qup11";
+				drive-strength = <2>;
+				bias-disable;
+			};
+
+			qup_spi11_data_clk: qup-spi11-data-clk-state {
+				/* MISO, MOSI, CLK */
+				pins = "gpio28", "gpio30", "gpio14";
+				function = "qup11";
+				drive-strength = <2>;
+				bias-disable;
+			};
+
+			qup_uart7_default: qup-uart7-default-state {
+				cts-pins {
+					pins = "gpio24";
+					function = "qup7";
+					drive-strength = <2>;
+					bias-disable;
+				};
+
+				rts-pins {
+					pins = "gpio25";
+					function = "qup7";
+					drive-strength = <2>;
+					bias-pull-down;
+				};
+
+				rx-pins {
+					pins = "gpio27";
+					function = "qup7";
+					drive-strength = <2>;
+					bias-pull-down;
+				};
+
+				tx-pins {
+					pins = "gpio26";
+					function = "qup7";
+					drive-strength = <2>;
+					bias-pull-up;
+				};
+			};
+
+			qup_uart11_default: qup-uart11-default-state {
+				pins = "gpio14", "gpio15";
+				function = "qup11";
+				drive-strength = <2>;
+				bias-disable;
+			};
+
+			sdc1_default: sdc1-default-state {
+				clk-pins {
+					pins = "sdc1_clk";
+					drive-strength = <16>;
+					bias-disable;
+				};
+
+				cmd-pins {
+					pins = "sdc1_cmd";
+					drive-strength = <10>;
+					bias-pull-up;
+				};
+
+				data-pins {
+					pins = "sdc1_data";
+					drive-strength = <10>;
+					bias-pull-up;
+				};
+
+				rclk-pins {
+					pins = "sdc1_rclk";
+					bias-pull-down;
+				};
+			};
+
+			sdc1_sleep: sdc1-sleep-state {
+				clk-pins {
+					pins = "sdc1_clk";
+					drive-strength = <2>;
+					bias-disable;
+				};
+
+				cmd-pins {
+					pins = "sdc1_cmd";
+					drive-strength = <2>;
+					bias-pull-up;
+				};
+
+				data-pins {
+					pins = "sdc1_data";
+					drive-strength = <2>;
+					bias-pull-up;
+				};
+
+				rclk-pins {
+					pins = "sdc1_rclk";
+					bias-pull-down;
+				};
+			};
+		};
+
+		apps_smmu: iommu@15000000 {
+			compatible = "qcom,sar2130p-smmu-500", "qcom,smmu-500", "arm,mmu-500";
+			reg = <0x0 0x15000000 0x0 0x100000>;
+			#iommu-cells = <2>;
+			#global-interrupts = <1>;
+			interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>;
+			dma-coherent;
+		};
+
+		intc: interrupt-controller@17200000 {
+			compatible = "arm,gic-v3";
+			#interrupt-cells = <3>;
+			interrupt-controller;
+			#redistributor-regions = <1>;
+			redistributor-stride = <0x0 0x20000>;
+			reg = <0x0 0x17200000 0x0 0x10000>,
+			      <0x0 0x17260000 0x0 0x100000>;
+			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+			#address-cells = <2>;
+			#size-cells = <2>;
+			ranges;
+
+			gic_its: msi-controller@17240000 {
+				compatible = "arm,gic-v3-its";
+				reg = <0x0 0x17240000 0x0 0x20000>;
+				msi-controller;
+				#msi-cells = <1>;
+			};
+		};
+
+		apps_rsc: rsc@17a00000 {
+			label = "apps_rsc";
+			compatible = "qcom,rpmh-rsc";
+			reg = <0x0 0x17a00000 0x0 0x10000>,
+			      <0x0 0x17a10000 0x0 0x10000>,
+			      <0x0 0x17a20000 0x0 0x10000>;
+			reg-names = "drv-0", "drv-1", "drv-2";
+			interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
+			qcom,tcs-offset = <0xd00>;
+			qcom,drv-id = <2>;
+			qcom,tcs-config = <ACTIVE_TCS  3>, <SLEEP_TCS   2>,
+					  <WAKE_TCS    2>, <CONTROL_TCS 0>;
+			power-domains = <&cluster_pd>;
+
+			apps_bcm_voter: bcm-voter {
+				compatible = "qcom,bcm-voter";
+			};
+
+			rpmhcc: clock-controller {
+				compatible = "qcom,sar2130p-rpmh-clk";
+				#clock-cells = <1>;
+				clock-names = "xo";
+				clocks = <&xo_board>;
+			};
+
+			rpmhpd: power-controller {
+				compatible = "qcom,sar2130p-rpmhpd";
+				#power-domain-cells = <1>;
+				operating-points-v2 = <&rpmhpd_opp_table>;
+
+				rpmhpd_opp_table: opp-table {
+					compatible = "operating-points-v2";
+
+					rpmhpd_opp_ret: opp1 {
+						opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
+					};
+
+					rpmhpd_opp_min_svs: opp2 {
+						opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
+					};
+
+					rpmhpd_opp_low_svs_d1: opp3 {
+						opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
+					};
+
+					rpmhpd_opp_low_svs: opp4 {
+						opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
+					};
+
+					rpmhpd_opp_svs: opp5 {
+						opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
+					};
+
+					rpmhpd_opp_svs_l1: opp6 {
+						opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
+					};
+
+					rpmhpd_opp_nom: opp7 {
+						opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
+					};
+
+					rpmhpd_opp_turbo: opp8 {
+						opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
+					};
+
+					rpmhpd_opp_turbo_l1: opp9 {
+						opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
+					};
+				};
+			};
+		};
+
+		cpufreq_hw: cpufreq@17d91000 {
+			compatible = "qcom,sar2130p-cpufreq-epss", "qcom,cpufreq-epss";
+			reg = <0x0 0x17d91000 0x0 0x1000>;
+			reg-names = "freq-domain0";
+			clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
+			clock-names = "xo", "alternate";
+			interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "dcvsh-irq-0";
+			#freq-domain-cells = <1>;
+			#clock-cells = <1>;
+		};
+
+		gem_noc: interconnect@19100000 {
+			compatible = "qcom,sar2130p-gem-noc";
+			reg = <0x0 0x19100000 0x0 0xa2080>;
+			#interconnect-cells = <2>;
+			qcom,bcm-voters = <&apps_bcm_voter>;
+		};
+
+		/*
+		 * Bootloader expects just cache-controller node instead of
+		 * the typical system-cache-controller
+		 */
+		llcc: cache-controller@19200000 {
+			compatible = "qcom,sar2130p-llcc";
+			reg = <0x0 0x19200000 0x0 0x80000>,
+			      <0x0 0x19300000 0x0 0x80000>,
+			      <0x0 0x19a00000 0x0 0x80000>,
+			      <0x0 0x19c00000 0x0 0x80000>,
+			      <0x0 0x19af0000 0x0 0x80000>,
+			      <0x0 0x19cf0000 0x0 0x80000>;
+			reg-names = "llcc0_base",
+				    "llcc1_base",
+				    "llcc_broadcast_base",
+				    "llcc_broadcast_and_base",
+				    "llcc_scratchpad_broadcast_base",
+				    "llcc_scratchpad_broadcast_and_base";
+			interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
+		};
+
+		qfprom: qfprom@221c8000 {
+			compatible = "qcom,sar2130p-qfprom", "qcom,qfprom";
+			reg = <0x0 0x221c8000 0x0 0x1000>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			read-only;
+
+			gpu_speed_bin: gpu-speed-bin@119 {
+				reg = <0x119 0x2>;
+				bits = <5 8>;
+			};
+		};
+
+		nsp_noc: interconnect@320c0000 {
+			compatible = "qcom,sar2130p-nsp-noc";
+			reg = <0x0 0x320c0000 0x0 0x10>;
+			#interconnect-cells = <2>;
+			qcom,bcm-voters = <&apps_bcm_voter>;
+		};
+
+		lpass_ag_noc: interconnect@3c40000 {
+			compatible = "qcom,sar2130p-lpass-ag-noc";
+			reg = <0x0 0x3c40000 0x0 0x10>;
+			#interconnect-cells = <1>;
+			qcom,bcm-voters = <&apps_bcm_voter>;
+		};
+	};
+
+	timer {
+		compatible = "arm,armv8-timer";
+
+		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
+			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
+			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
+			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
+	};
+
+	thermal-zones {
+		aoss0-thermal {
+			thermal-sensors = <&tsens0 0>;
+
+			trips {
+				trip-point0 {
+					temperature = <115000>;
+					hysteresis = <5000>;
+					type = "hot";
+				};
+
+				aoss0-critical {
+					temperature = <125000>;
+					hysteresis = <0>;
+					type = "critical";
+				};
+
+			};
+		};
+
+		cpu0-thermal {
+			thermal-sensors = <&tsens0 1>;
+
+			trips {
+				cpu0_alert0: trip-point0 {
+					temperature = <110000>;
+					hysteresis = <10000>;
+					type = "passive";
+				};
+
+				cpu0_alert1: trip-point1 {
+					temperature = <115000>;
+					hysteresis = <5000>;
+					type = "passive";
+				};
+
+				cpu0-critical {
+					temperature = <125000>;
+					hysteresis = <1000>;
+					type = "critical";
+				};
+			};
+
+			cooling-maps {
+				map0 {
+					trip = <&cpu0_alert0>;
+					cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+				};
+
+				map1 {
+					trip = <&cpu0_alert1>;
+					cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+				};
+			};
+		};
+
+		cpu1-thermal {
+			thermal-sensors = <&tsens0 2>;
+
+			trips {
+				cpu1_alert0: trip-point0 {
+					temperature = <110000>;
+					hysteresis = <10000>;
+					type = "passive";
+				};
+
+				cpu1_alert1: trip-point1 {
+					temperature = <115000>;
+					hysteresis = <5000>;
+					type = "passive";
+				};
+
+				cpu1-critical {
+					temperature = <125000>;
+					hysteresis = <1000>;
+					type = "critical";
+				};
+			};
+
+			cooling-maps {
+				map0 {
+					trip = <&cpu1_alert0>;
+					cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+				};
+
+				map1 {
+					trip = <&cpu1_alert1>;
+					cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+				};
+			};
+		};
+
+		cpu2-thermal {
+			thermal-sensors = <&tsens0 3>;
+
+			trips {
+				cpu2_alert0: trip-point0 {
+					temperature = <110000>;
+					hysteresis = <10000>;
+					type = "passive";
+				};
+
+				cpu2_alert1: trip-point1 {
+					temperature = <115000>;
+					hysteresis = <5000>;
+					type = "passive";
+				};
+
+				cpu2-critical {
+					temperature = <125000>;
+					hysteresis = <1000>;
+					type = "critical";
+				};
+			};
+
+			cooling-maps {
+				map0 {
+					trip = <&cpu2_alert0>;
+					cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+				};
+
+				map1 {
+					trip = <&cpu2_alert1>;
+					cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+				};
+			};
+		};
+
+		cpu3-thermal {
+			thermal-sensors = <&tsens0 4>;
+
+			trips {
+				cpu3_alert0: trip-point0 {
+					temperature = <110000>;
+					hysteresis = <10000>;
+					type = "passive";
+				};
+
+				cpu3_alert1: rip-point1 {
+					temperature = <115000>;
+					hysteresis = <5000>;
+					type = "passive";
+				};
+
+				cpu3-critical {
+					temperature = <125000>;
+					hysteresis = <1000>;
+					type = "critical";
+				};
+			};
+
+			cooling-maps {
+				map0 {
+					trip = <&cpu3_alert0>;
+					cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+				};
+
+				map1 {
+					trip = <&cpu3_alert1>;
+					cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+				};
+			};
+		};
+
+		gpuss0-thermal {
+			polling-delay-passive = <250>;
+
+			thermal-sensors = <&tsens0 5>;
+
+			cooling-maps {
+				map0 {
+					trip = <&gpu0_alert0>;
+					cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+				};
+			};
+
+			trips {
+				gpu0_alert0: trip-point0 {
+					temperature = <85000>;
+					hysteresis = <1000>;
+					type = "passive";
+				};
+
+				trip-point1 {
+					temperature = <90000>;
+					hysteresis = <1000>;
+					type = "hot";
+				};
+
+				trip-point2 {
+					temperature = <115000>;
+					hysteresis = <1000>;
+					type = "critical";
+				};
+			};
+		};
+
+		gpuss1-thermal {
+			polling-delay-passive = <250>;
+
+			thermal-sensors = <&tsens0 6>;
+
+			cooling-maps {
+				map0 {
+					trip = <&gpu1_alert0>;
+					cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+				};
+			};
+
+			trips {
+				gpu1_alert0: trip-point0 {
+					temperature = <85000>;
+					hysteresis = <1000>;
+					type = "passive";
+				};
+
+				trip-point1 {
+					temperature = <90000>;
+					hysteresis = <1000>;
+					type = "hot";
+				};
+
+				trip-point2 {
+					temperature = <115000>;
+					hysteresis = <1000>;
+					type = "critical";
+				};
+			};
+		};
+
+		nspss0-thermal {
+			thermal-sensors = <&tsens0 7>;
+
+			trips {
+				trip-point0 {
+					temperature = <95000>;
+					hysteresis = <5000>;
+					type = "hot";
+				};
+
+				trip-point1 {
+					temperature = <115000>;
+					hysteresis = <5000>;
+					type = "hot";
+				};
+
+				nspss1-critical {
+					temperature = <125000>;
+					hysteresis = <1000>;
+					type = "critical";
+				};
+			};
+		};
+
+		nspss1-thermal {
+			thermal-sensors = <&tsens0 8>;
+
+			trips {
+				trip-point0 {
+					temperature = <95000>;
+					hysteresis = <5000>;
+					type = "hot";
+				};
+
+				trip-point1 {
+					temperature = <115000>;
+					hysteresis = <5000>;
+					type = "hot";
+				};
+
+				nspss2-critical {
+					temperature = <125000>;
+					hysteresis = <1000>;
+					type = "critical";
+				};
+			};
+		};
+
+		nspss2-thermal {
+			thermal-sensors = <&tsens0 9>;
+
+			trips {
+				trip-point0 {
+					temperature = <95000>;
+					hysteresis = <5000>;
+					type = "hot";
+				};
+
+				trip-point1 {
+					temperature = <115000>;
+					hysteresis = <5000>;
+					type = "hot";
+				};
+
+				nspss2-critical {
+					temperature = <125000>;
+					hysteresis = <1000>;
+					type = "critical";
+				};
+			};
+		};
+
+		video-thermal {
+			thermal-sensors = <&tsens0 10>;
+
+			trips {
+				trip-point0 {
+					temperature = <115000>;
+					hysteresis = <5000>;
+					type = "hot";
+				};
+
+				video-critical {
+					temperature = <125000>;
+					hysteresis = <0>;
+					type = "critical";
+				};
+			};
+		};
+
+		ddr-thermal {
+			thermal-sensors = <&tsens0 11>;
+
+			trips {
+				trip-point0 {
+					temperature = <115000>;
+					hysteresis = <5000>;
+					type = "hot";
+				};
+
+				ddr-critical {
+					temperature = <125000>;
+					hysteresis = <0>;
+					type = "critical";
+				};
+			};
+		};
+
+		camera0-thermal {
+			thermal-sensors = <&tsens0 12>;
+
+			trips {
+				trip-point0 {
+					temperature = <115000>;
+					hysteresis = <5000>;
+					type = "hot";
+				};
+
+				camera0-critical {
+					temperature = <125000>;
+					hysteresis = <0>;
+					type = "critical";
+				};
+			};
+		};
+
+		camera1-thermal {
+			thermal-sensors = <&tsens0 13>;
+
+			trips {
+				trip-point0 {
+					temperature = <115000>;
+					hysteresis = <5000>;
+					type = "hot";
+				};
+
+				camera1-critical {
+					temperature = <125000>;
+					hysteresis = <0>;
+					type = "critical";
+				};
+			};
+		};
+
+		mdmss-thermal {
+			thermal-sensors = <&tsens0 14>;
+
+			trips {
+				trip-point0 {
+					temperature = <115000>;
+					hysteresis = <5000>;
+					type = "hot";
+				};
+
+				mdmss-critical {
+					temperature = <125000>;
+					hysteresis = <0>;
+					type = "critical";
+				};
+			};
+		};
+	};
+};
diff --git a/dts/upstream/src/arm64/qcom/sc7180-trogdor-pompom.dtsi b/dts/upstream/src/arm64/qcom/sc7180-trogdor-pompom.dtsi
index ac8d4589e3f..f7300ffbb45 100644
--- a/dts/upstream/src/arm64/qcom/sc7180-trogdor-pompom.dtsi
+++ b/dts/upstream/src/arm64/qcom/sc7180-trogdor-pompom.dtsi
@@ -12,11 +12,11 @@
 
 / {
 	thermal-zones {
-		5v-choke-thermal {
+		choke-5v-thermal {
 			thermal-sensors = <&pm6150_adc_tm 1>;
 
 			trips {
-				5v-choke-crit {
+				choke-5v-crit {
 					temperature = <125000>;
 					hysteresis = <1000>;
 					type = "critical";
diff --git a/dts/upstream/src/arm64/qcom/sc7180-trogdor-quackingstick.dtsi b/dts/upstream/src/arm64/qcom/sc7180-trogdor-quackingstick.dtsi
index 00229b1515e..ff8996b4de4 100644
--- a/dts/upstream/src/arm64/qcom/sc7180-trogdor-quackingstick.dtsi
+++ b/dts/upstream/src/arm64/qcom/sc7180-trogdor-quackingstick.dtsi
@@ -78,6 +78,7 @@
 		pinctrl-names = "default";
 		pinctrl-0 = <&lcd_rst>;
 		avdd-supply = <&ppvar_lcd>;
+		avee-supply = <&ppvar_lcd>;
 		pp1800-supply = <&v1p8_disp>;
 		pp3300-supply = <&pp3300_dx_edp>;
 		backlight = <&backlight>;
diff --git a/dts/upstream/src/arm64/qcom/sc7180.dtsi b/dts/upstream/src/arm64/qcom/sc7180.dtsi
index 76fe314d2ad..87c432c12a2 100644
--- a/dts/upstream/src/arm64/qcom/sc7180.dtsi
+++ b/dts/upstream/src/arm64/qcom/sc7180.dtsi
@@ -580,55 +580,55 @@
 		compatible = "arm,psci-1.0";
 		method = "smc";
 
-		cpu_pd0: cpu0 {
+		cpu_pd0: power-domain-cpu0 {
 			#power-domain-cells = <0>;
 			power-domains = <&cluster_pd>;
 			domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>;
 		};
 
-		cpu_pd1: cpu1 {
+		cpu_pd1: power-domain-cpu1 {
 			#power-domain-cells = <0>;
 			power-domains = <&cluster_pd>;
 			domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>;
 		};
 
-		cpu_pd2: cpu2 {
+		cpu_pd2: power-domain-cpu2 {
 			#power-domain-cells = <0>;
 			power-domains = <&cluster_pd>;
 			domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>;
 		};
 
-		cpu_pd3: cpu3 {
+		cpu_pd3: power-domain-cpu3 {
 			#power-domain-cells = <0>;
 			power-domains = <&cluster_pd>;
 			domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>;
 		};
 
-		cpu_pd4: cpu4 {
+		cpu_pd4: power-domain-cpu4 {
 			#power-domain-cells = <0>;
 			power-domains = <&cluster_pd>;
 			domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>;
 		};
 
-		cpu_pd5: cpu5 {
+		cpu_pd5: power-domain-cpu5 {
 			#power-domain-cells = <0>;
 			power-domains = <&cluster_pd>;
 			domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>;
 		};
 
-		cpu_pd6: cpu6 {
+		cpu_pd6: power-domain-cpu6 {
 			#power-domain-cells = <0>;
 			power-domains = <&cluster_pd>;
 			domain-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>;
 		};
 
-		cpu_pd7: cpu7 {
+		cpu_pd7: power-domain-cpu7 {
 			#power-domain-cells = <0>;
 			power-domains = <&cluster_pd>;
 			domain-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>;
 		};
 
-		cluster_pd: cpu-cluster0 {
+		cluster_pd: power-domain-cluster {
 			#power-domain-cells = <0>;
 			domain-idle-states = <&cluster_sleep_pc
 					      &cluster_sleep_cx_ret
@@ -3064,6 +3064,8 @@
 				snps,dis_u2_susphy_quirk;
 				snps,dis_enblslpm_quirk;
 				snps,parkmode-disable-ss-quirk;
+				snps,dis-u1-entry-quirk;
+				snps,dis-u2-entry-quirk;
 				phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>;
 				phy-names = "usb2-phy", "usb3-phy";
 				maximum-speed = "super-speed";
diff --git a/dts/upstream/src/arm64/qcom/sc7280.dtsi b/dts/upstream/src/arm64/qcom/sc7280.dtsi
index 55db1c83ef5..0f2caf36910 100644
--- a/dts/upstream/src/arm64/qcom/sc7280.dtsi
+++ b/dts/upstream/src/arm64/qcom/sc7280.dtsi
@@ -83,7 +83,7 @@
 
 		sleep_clk: sleep-clk {
 			compatible = "fixed-clock";
-			clock-frequency = <32000>;
+			clock-frequency = <32764>;
 			#clock-cells = <0>;
 		};
 	};
@@ -3715,6 +3715,8 @@
 				iommus = <&apps_smmu 0xa0 0x0>;
 				snps,dis_u2_susphy_quirk;
 				snps,dis_enblslpm_quirk;
+				snps,dis-u1-entry-quirk;
+				snps,dis-u2-entry-quirk;
 				phys = <&usb_2_hsphy>;
 				phy-names = "usb2-phy";
 				maximum-speed = "high-speed";
@@ -4244,6 +4246,8 @@
 				snps,dis_u2_susphy_quirk;
 				snps,dis_enblslpm_quirk;
 				snps,parkmode-disable-ss-quirk;
+				snps,dis-u1-entry-quirk;
+				snps,dis-u2-entry-quirk;
 				phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>;
 				phy-names = "usb2-phy", "usb3-phy";
 				maximum-speed = "super-speed";
diff --git a/dts/upstream/src/arm64/qcom/sc8180x-lenovo-flex-5g.dts b/dts/upstream/src/arm64/qcom/sc8180x-lenovo-flex-5g.dts
index 62de4774c55..21c2d25a294 100644
--- a/dts/upstream/src/arm64/qcom/sc8180x-lenovo-flex-5g.dts
+++ b/dts/upstream/src/arm64/qcom/sc8180x-lenovo-flex-5g.dts
@@ -681,10 +681,6 @@
 	status = "okay";
 };
 
-&xo_board_clk {
-	clock-frequency = <38400000>;
-};
-
 /* PINCTRL */
 
 &pmc8180c_gpios {
diff --git a/dts/upstream/src/arm64/qcom/sc8180x-primus.dts b/dts/upstream/src/arm64/qcom/sc8180x-primus.dts
index 79b4d293ea1..7a4bd695547 100644
--- a/dts/upstream/src/arm64/qcom/sc8180x-primus.dts
+++ b/dts/upstream/src/arm64/qcom/sc8180x-primus.dts
@@ -773,10 +773,6 @@
 	status = "okay";
 };
 
-&xo_board_clk {
-	clock-frequency = <38400000>;
-};
-
 /* PINCTRL */
 
 &pmc8180c_gpios {
diff --git a/dts/upstream/src/arm64/qcom/sc8180x.dtsi b/dts/upstream/src/arm64/qcom/sc8180x.dtsi
index 745a7d0b838..28693a3bfc7 100644
--- a/dts/upstream/src/arm64/qcom/sc8180x.dtsi
+++ b/dts/upstream/src/arm64/qcom/sc8180x.dtsi
@@ -2762,6 +2762,8 @@
 				iommus = <&apps_smmu 0x60 0>;
 				snps,dis_u2_susphy_quirk;
 				snps,dis_enblslpm_quirk;
+				snps,dis-u1-entry-quirk;
+				snps,dis-u2-entry-quirk;
 				phys = <&usb_mp_hsphy0>,
 				       <&usb_mp_qmpphy0>,
 				       <&usb_mp_hsphy1>,
@@ -2825,6 +2827,8 @@
 				iommus = <&apps_smmu 0x140 0>;
 				snps,dis_u2_susphy_quirk;
 				snps,dis_enblslpm_quirk;
+				snps,dis-u1-entry-quirk;
+				snps,dis-u2-entry-quirk;
 				phys = <&usb_prim_hsphy>, <&usb_prim_qmpphy QMP_USB43DP_USB3_PHY>;
 				phy-names = "usb2-phy", "usb3-phy";
 
@@ -2902,6 +2906,8 @@
 				iommus = <&apps_smmu 0x160 0>;
 				snps,dis_u2_susphy_quirk;
 				snps,dis_enblslpm_quirk;
+				snps,dis-u1-entry-quirk;
+				snps,dis-u2-entry-quirk;
 				phys = <&usb_sec_hsphy>, <&usb_sec_qmpphy QMP_USB43DP_USB3_PHY>;
 				phy-names = "usb2-phy", "usb3-phy";
 
diff --git a/dts/upstream/src/arm64/qcom/sc8280xp-huawei-gaokun3.dts b/dts/upstream/src/arm64/qcom/sc8280xp-huawei-gaokun3.dts
new file mode 100644
index 00000000000..09b95f89ee5
--- /dev/null
+++ b/dts/upstream/src/arm64/qcom/sc8280xp-huawei-gaokun3.dts
@@ -0,0 +1,1318 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2021, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2022, Linaro Limited
+ *
+ * Copyright (c) 2024, Tianyu Gao <gty0622@gmail.com>
+ * Copyright (c) 2024, Xuecong Chen <chenxuecong2009@outlook.com>
+ *
+ * Copyright (c) 2024, Pengyu Luo <mitltlatltl@gmail.com>
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/iio/qcom,spmi-adc7-pm8350.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/gpio-keys.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
+#include <dt-bindings/phy/phy.h>
+
+#include "sc8280xp.dtsi"
+#include "sc8280xp-pmics.dtsi"
+
+/ {
+	chassis-type = "tablet";
+	model = "Matebook E Go";
+	compatible = "huawei,gaokun3", "qcom,sc8280xp";
+
+	aliases {
+		i2c4 = &i2c4;
+		serial1 = &uart2;
+	};
+
+	chosen {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		framebuffer0: framebuffer@c6200000 {
+			compatible = "simple-framebuffer";
+			reg = <0x0 0xc6200000 0x0 0x02400000>;
+			width = <1600>;
+			height = <2560>;
+			stride = <(1600 * 4)>;
+			format = "a8r8g8b8";
+		};
+	};
+
+	wcd938x: audio-codec {
+		compatible = "qcom,wcd9380-codec";
+
+		pinctrl-0 = <&wcd_default>;
+		pinctrl-names = "default";
+
+		reset-gpios = <&tlmm 106 GPIO_ACTIVE_LOW>;
+
+		vdd-buck-supply = <&vreg_s10b>;
+		vdd-rxtx-supply = <&vreg_s10b>;
+		vdd-io-supply = <&vreg_s10b>;
+		vdd-mic-bias-supply = <&vreg_bob>;
+
+		qcom,micbias1-microvolt = <1800000>;
+		qcom,micbias2-microvolt = <1800000>;
+		qcom,micbias3-microvolt = <1800000>;
+		qcom,micbias4-microvolt = <1800000>;
+		qcom,mbhc-buttons-vthreshold-microvolt = <75000 150000 237000 500000 500000 500000 500000 500000>;
+		qcom,mbhc-headset-vthreshold-microvolt = <1700000>;
+		qcom,mbhc-headphone-vthreshold-microvolt = <50000>;
+		qcom,rx-device = <&wcd_rx>;
+		qcom,tx-device = <&wcd_tx>;
+
+		#sound-dai-cells = <1>;
+	};
+
+	gpio-keys {
+		compatible = "gpio-keys";
+
+		pinctrl-0 = <&mode_pin_active>, <&vol_up_n>;
+		pinctrl-names = "default";
+
+		key-vol-up {
+			label = "Volume Up";
+			gpios = <&pmc8280_1_gpios 6 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_VOLUMEUP>;
+			debounce-interval = <15>;
+			linux,can-disable;
+			wakeup-source;
+		};
+
+		switch-mode {
+			label = "Tablet Mode Switch";
+			gpios = <&tlmm 26 GPIO_ACTIVE_HIGH>;
+			linux,input-type = <EV_SW>;
+			linux,code = <SW_TABLET_MODE>;
+			debounce-interval = <10>;
+			wakeup-source;
+		};
+	};
+
+	vreg_misc_3p3: regulator-misc-3p3 {
+		compatible = "regulator-fixed";
+
+		regulator-name = "VCC3B";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+
+		gpio = <&pmc8280_1_gpios 1 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+
+		pinctrl-0 = <&misc_3p3_reg_en>;
+		pinctrl-names = "default";
+
+		regulator-boot-on;
+		regulator-always-on;
+	};
+
+	vreg_nvme: regulator-nvme {
+		compatible = "regulator-fixed";
+
+		regulator-name = "VCC3_SSD";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+
+		gpio = <&tlmm 135 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+
+		pinctrl-0 = <&nvme_reg_en>;
+		pinctrl-names = "default";
+
+		regulator-boot-on;
+	};
+
+	vreg_vph_pwr: regulator-vph-pwr {
+		compatible = "regulator-fixed";
+
+		regulator-name = "VPH_VCC3R9";
+		regulator-min-microvolt = <3900000>;
+		regulator-max-microvolt = <3900000>;
+
+		regulator-always-on;
+	};
+
+	vreg_wlan: regulator-wlan {
+		compatible = "regulator-fixed";
+
+		regulator-name = "VCC_WLAN_3R9";
+		regulator-min-microvolt = <3900000>;
+		regulator-max-microvolt = <3900000>;
+
+		gpio = <&pmr735a_gpios 1 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+
+		pinctrl-0 = <&hastings_reg_en>;
+		pinctrl-names = "default";
+
+		regulator-boot-on;
+	};
+
+	reserved-memory {
+		gpu_mem: gpu-mem@8bf00000 {
+			reg = <0 0x8bf00000 0 0x2000>;
+			no-map;
+		};
+
+		linux,cma {
+			compatible = "shared-dma-pool";
+			size = <0x0 0x8000000>;
+			reusable;
+			linux,cma-default;
+		};
+	};
+
+	thermal-zones {
+		skin-temp-thermal {
+			polling-delay-passive = <250>;
+
+			thermal-sensors = <&pmk8280_adc_tm 5>;
+
+			trips {
+				skin_temp_alert0: trip-point0 {
+					temperature = <55000>;
+					hysteresis = <1000>;
+					type = "passive";
+				};
+
+				skin_temp_alert1: trip-point1 {
+					temperature = <58000>;
+					hysteresis = <1000>;
+					type = "passive";
+				};
+
+				skin-temp-crit {
+					temperature = <73000>;
+					hysteresis = <1000>;
+					type = "critical";
+				};
+			};
+
+			cooling-maps {
+				map0 {
+					trip = <&skin_temp_alert0>;
+					cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+				};
+
+				map1 {
+					trip = <&skin_temp_alert1>;
+					cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+				};
+			};
+		};
+	};
+
+	wcn6855-pmu {
+		compatible = "qcom,wcn6855-pmu";
+
+		pinctrl-names = "default";
+		pinctrl-0 = <&bt_default>, <&wlan_en>;
+
+		wlan-enable-gpios = <&tlmm 134 GPIO_ACTIVE_HIGH>;
+		bt-enable-gpios = <&tlmm 133 GPIO_ACTIVE_HIGH>;
+		swctrl-gpios = <&tlmm 132 GPIO_ACTIVE_HIGH>;
+
+		vddio-supply = <&vreg_s10b>;
+		vddaon-supply = <&vreg_s12b>;
+		vddpmu-supply = <&vreg_s12b>;
+		vddpmumx-supply = <&vreg_s12b>;
+		vddpmucx-supply = <&vreg_s12b>;
+		vddrfa0p95-supply = <&vreg_s12b>;
+		vddrfa1p3-supply = <&vreg_s11b>;
+		vddrfa1p9-supply = <&vreg_s1c>;
+		vddpcie1p3-supply = <&vreg_s11b>;
+		vddpcie1p9-supply = <&vreg_s1c>;
+
+		regulators {
+			vreg_pmu_rfa_cmn_0p8: ldo0 {
+				regulator-name = "vreg_pmu_rfa_cmn_0p8";
+			};
+
+			vreg_pmu_aon_0p8: ldo1 {
+				regulator-name = "vreg_pmu_aon_0p8";
+			};
+
+			vreg_pmu_wlcx_0p8: ldo2 {
+				regulator-name = "vreg_pmu_wlcx_0p8";
+			};
+
+			vreg_pmu_wlmx_0p8: ldo3 {
+				regulator-name = "vreg_pmu_wlmx_0p8";
+			};
+
+			vreg_pmu_btcmx_0p8: ldo4 {
+				regulator-name = "vreg_pmu_btcmx_0p8";
+			};
+
+			vreg_pmu_pcie_1p8: ldo5 {
+				regulator-name = "vreg_pmu_pcie_1p8";
+			};
+
+			vreg_pmu_pcie_0p9: ldo6 {
+				regulator-name = "vreg_pmu_pcie_0p9";
+			};
+
+			vreg_pmu_rfa_0p8: ldo7 {
+				regulator-name = "vreg_pmu_rfa_0p8";
+			};
+
+			vreg_pmu_rfa_1p2: ldo8 {
+				regulator-name = "vreg_pmu_rfa_1p2";
+			};
+
+			vreg_pmu_rfa_1p7: ldo9 {
+				regulator-name = "vreg_pmu_rfa_1p7";
+			};
+		};
+	};
+};
+
+&apps_rsc {
+	regulators-0 {
+		compatible = "qcom,pm8350-rpmh-regulators";
+		qcom,pmic-id = "b";
+
+		vdd-l1-l4-supply = <&vreg_s12b>;
+		vdd-l2-l7-supply = <&vreg_bob>;
+		vdd-l3-l5-supply = <&vreg_s11b>;
+		vdd-l6-l9-l10-supply = <&vreg_s12b>;
+		vdd-l8-supply = <&vreg_s12b>;
+
+		vreg_s10b: smps10 {
+			regulator-name = "vreg_s10b";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-always-on;
+		};
+
+		vreg_s11b: smps11 {
+			regulator-name = "vreg_s11b";
+			regulator-min-microvolt = <1272000>;
+			regulator-max-microvolt = <1272000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_s12b: smps12 {
+			regulator-name = "vreg_s12b";
+			regulator-min-microvolt = <984000>;
+			regulator-max-microvolt = <984000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l1b: ldo1 {
+			regulator-name = "vreg_l1b";
+			regulator-min-microvolt = <912000>;
+			regulator-max-microvolt = <912000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l2b: ldo2 {
+			regulator-name = "vreg_l2b";
+			regulator-min-microvolt = <1904000>;
+			regulator-max-microvolt = <1904000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l3b: ldo3 {
+			regulator-name = "vreg_l3b";
+			regulator-min-microvolt = <1200000>;
+			regulator-max-microvolt = <1200000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-boot-on;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l4b: ldo4 {
+			regulator-name = "vreg_l4b";
+			regulator-min-microvolt = <912000>;
+			regulator-max-microvolt = <912000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l5b: ldo5 {
+			regulator-name = "vreg_l5b";
+			regulator-min-microvolt = <1200000>;
+			regulator-max-microvolt = <1200000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l6b: ldo6 {
+			regulator-name = "vreg_l6b";
+			regulator-min-microvolt = <880000>;
+			regulator-max-microvolt = <880000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-boot-on;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l7b: ldo7 {
+			regulator-name = "vreg_l7b";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-boot-on;
+		};
+
+		vreg_l9b: ldo9 {
+			regulator-name = "vreg_l9b";
+			regulator-min-microvolt = <912000>;
+			regulator-max-microvolt = <912000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+	};
+
+	regulators-1 {
+		compatible = "qcom,pm8350c-rpmh-regulators";
+		qcom,pmic-id = "c";
+
+		vdd-bob-supply = <&vreg_vph_pwr>;
+		vdd-l1-l12-supply = <&vreg_s1c>;
+		vdd-l2-l8-supply = <&vreg_s1c>;
+		vdd-l3-l4-l5-l7-l13-supply = <&vreg_bob>;
+		vdd-l6-l9-l11-supply = <&vreg_bob>;
+		vdd-l10-supply = <&vreg_s11b>;
+
+		vreg_s1c: smps1 {
+			regulator-name = "vreg_s1c";
+			regulator-min-microvolt = <1880000>;
+			regulator-max-microvolt = <1900000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-always-on;
+		};
+
+		vreg_l1c: ldo1 {
+			regulator-name = "vreg_l1c";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l2c: ldo2 {
+			regulator-name = "vreg_l2c";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l8c: ldo8 {
+			regulator-name = "vreg_l8c";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l12c: ldo12 {
+			regulator-name = "vreg_l12c";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l13c: ldo13 {
+			regulator-name = "vreg_l13c";
+			regulator-min-microvolt = <3072000>;
+			regulator-max-microvolt = <3072000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_bob: bob {
+			regulator-name = "vreg_bob";
+			regulator-min-microvolt = <3008000>;
+			regulator-max-microvolt = <3960000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
+			regulator-always-on;
+		};
+	};
+
+	regulators-2 {
+		compatible = "qcom,pm8350-rpmh-regulators";
+		qcom,pmic-id = "d";
+
+		vdd-l1-l4-supply = <&vreg_s11b>;
+		vdd-l2-l7-supply = <&vreg_bob>;
+		vdd-l3-l5-supply = <&vreg_s11b>;
+		vdd-l6-l9-l10-supply = <&vreg_s12b>;
+		vdd-l8-supply = <&vreg_s12b>;
+
+		vreg_l2d: ldo2 {
+			regulator-name = "vreg_l2d";
+			regulator-min-microvolt = <3072000>;
+			regulator-max-microvolt = <3072000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l3d: ldo3 {
+			regulator-name = "vreg_l3d";
+			regulator-min-microvolt = <1200000>;
+			regulator-max-microvolt = <1200000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l4d: ldo4 {
+			regulator-name = "vreg_l4d";
+			regulator-min-microvolt = <1200000>;
+			regulator-max-microvolt = <1200000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l6d: ldo6 {
+			regulator-name = "vreg_l6d";
+			regulator-min-microvolt = <880000>;
+			regulator-max-microvolt = <880000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l7d: ldo7 {
+			regulator-name = "vreg_l7d";
+			regulator-min-microvolt = <3072000>;
+			regulator-max-microvolt = <3072000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l8d: ldo8 {
+			regulator-name = "vreg_l8d";
+			regulator-min-microvolt = <912000>;
+			regulator-max-microvolt = <912000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l9d: ldo9 {
+			regulator-name = "vreg_l9d";
+			regulator-min-microvolt = <912000>;
+			regulator-max-microvolt = <912000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l10d: ldo10 {
+			regulator-name = "vreg_l10d";
+			regulator-min-microvolt = <912000>;
+			regulator-max-microvolt = <912000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+	};
+};
+
+&dispcc0 {
+	status = "okay";
+};
+
+&gpu {
+	status = "okay";
+
+	zap-shader {
+		memory-region = <&gpu_mem>;
+		firmware-name = "qcom/sc8280xp/HUAWEI/gaokun3/qcdxkmsuc8280.mbn";
+	};
+};
+
+&i2c4 {
+	clock-frequency = <400000>;
+
+	pinctrl-0 = <&i2c4_default>;
+	pinctrl-names = "default";
+
+	status = "okay";
+
+	touchscreen@4f {
+		compatible = "hid-over-i2c";
+		reg = <0x4f>;
+
+		hid-descr-addr = <0x1>;
+		interrupts-extended = <&tlmm 175 IRQ_TYPE_LEVEL_LOW>;
+
+		vdd-supply = <&vreg_misc_3p3>;
+		vddl-supply = <&vreg_s10b>;
+
+		pinctrl-0 = <&ts0_default>;
+		pinctrl-names = "default";
+	};
+
+};
+
+&mdss0 {
+	status = "okay";
+};
+
+&mdss0_dp0 {
+	status = "okay";
+};
+
+&mdss0_dp0_out {
+	data-lanes = <0 1>;
+	remote-endpoint = <&usb_0_qmpphy_dp_in>;
+};
+
+&mdss0_dp1 {
+	status = "okay";
+};
+
+&mdss0_dp1_out {
+	data-lanes = <0 1>;
+	remote-endpoint = <&usb_1_qmpphy_dp_in>;
+};
+
+&pcie2a {
+	perst-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>;
+	wake-gpios = <&tlmm 145 GPIO_ACTIVE_LOW>;
+
+	vddpe-3v3-supply = <&vreg_nvme>;
+
+	pinctrl-0 = <&pcie2a_default>;
+	pinctrl-names = "default";
+
+	status = "okay";
+};
+
+&pcie2a_phy {
+	vdda-phy-supply = <&vreg_l6d>;
+	vdda-pll-supply = <&vreg_l4d>;
+
+	status = "okay";
+};
+
+&pcie4 {
+	max-link-speed = <2>;
+
+	perst-gpios = <&tlmm 141 GPIO_ACTIVE_LOW>;
+	wake-gpios = <&tlmm 139 GPIO_ACTIVE_LOW>;
+
+	vddpe-3v3-supply = <&vreg_wlan>;
+
+	pinctrl-0 = <&pcie4_default>;
+	pinctrl-names = "default";
+
+	status = "okay";
+};
+
+&pcie4_port0 {
+	wifi@0 {
+		compatible = "pci17cb,1103";
+		reg = <0x10000 0x0 0x0 0x0 0x0>;
+
+		vddrfacmn-supply = <&vreg_pmu_rfa_cmn_0p8>;
+		vddaon-supply = <&vreg_pmu_aon_0p8>;
+		vddwlcx-supply = <&vreg_pmu_wlcx_0p8>;
+		vddwlmx-supply = <&vreg_pmu_wlmx_0p8>;
+		vddpcie1p8-supply = <&vreg_pmu_pcie_1p8>;
+		vddpcie0p9-supply = <&vreg_pmu_pcie_0p9>;
+		vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>;
+		vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>;
+		vddrfa1p8-supply = <&vreg_pmu_rfa_1p7>;
+	};
+};
+
+&pcie4_phy {
+	vdda-phy-supply = <&vreg_l6d>;
+	vdda-pll-supply = <&vreg_l4d>;
+
+	status = "okay";
+};
+
+&pmk8280_adc_tm {
+	status = "okay";
+
+	sys-therm@0 {
+		reg = <0>;
+		io-channels = <&pmk8280_vadc PM8350_ADC7_AMUX_THM1_100K_PU(1)>;
+		qcom,hw-settle-time-us = <200>;
+		qcom,avg-samples = <2>;
+		qcom,ratiometric;
+	};
+
+	sys-therm@1 {
+		reg = <1>;
+		io-channels = <&pmk8280_vadc PM8350_ADC7_AMUX_THM2_100K_PU(1)>;
+		qcom,hw-settle-time-us = <200>;
+		qcom,avg-samples = <2>;
+		qcom,ratiometric;
+	};
+
+	sys-therm@2 {
+		reg = <2>;
+		io-channels = <&pmk8280_vadc PM8350_ADC7_AMUX_THM3_100K_PU(1)>;
+		qcom,hw-settle-time-us = <200>;
+		qcom,avg-samples = <2>;
+		qcom,ratiometric;
+	};
+
+	sys-therm@3 {
+		reg = <3>;
+		io-channels = <&pmk8280_vadc PM8350_ADC7_AMUX_THM4_100K_PU(1)>;
+		qcom,hw-settle-time-us = <200>;
+		qcom,avg-samples = <2>;
+		qcom,ratiometric;
+	};
+
+	sys-therm@4 {
+		reg = <4>;
+		io-channels = <&pmk8280_vadc PM8350_ADC7_AMUX_THM1_100K_PU(3)>;
+		qcom,hw-settle-time-us = <200>;
+		qcom,avg-samples = <2>;
+		qcom,ratiometric;
+	};
+
+	sys-therm@5 {
+		reg = <5>;
+		io-channels = <&pmk8280_vadc PM8350_ADC7_AMUX_THM2_100K_PU(3)>;
+		qcom,hw-settle-time-us = <200>;
+		qcom,avg-samples = <2>;
+		qcom,ratiometric;
+	};
+
+	sys-therm@6 {
+		reg = <6>;
+		io-channels = <&pmk8280_vadc PM8350_ADC7_AMUX_THM3_100K_PU(3)>;
+		qcom,hw-settle-time-us = <200>;
+		qcom,avg-samples = <2>;
+		qcom,ratiometric;
+	};
+
+	sys-therm@7 {
+		reg = <7>;
+		io-channels = <&pmk8280_vadc PM8350_ADC7_AMUX_THM4_100K_PU(3)>;
+		qcom,hw-settle-time-us = <200>;
+		qcom,avg-samples = <2>;
+		qcom,ratiometric;
+	};
+};
+
+&pmk8280_pon_pwrkey {
+	status = "okay";
+};
+
+&pmk8280_pon_resin {
+	status = "okay";
+	linux,code = <KEY_VOLUMEDOWN>;
+};
+
+&pmk8280_rtc {
+	nvmem-cells = <&rtc_offset>;
+	nvmem-cell-names = "offset";
+
+	status = "okay";
+};
+
+&pmk8280_sdam_6 {
+	status = "okay";
+
+	rtc_offset: rtc-offset@bc {
+		reg = <0xbc 0x4>;
+	};
+};
+
+&pmk8280_vadc {
+	channel@144 {
+		reg = <PM8350_ADC7_AMUX_THM1_100K_PU(1)>;
+		qcom,hw-settle-time = <200>;
+		qcom,ratiometric;
+		label = "sys_therm1";
+	};
+
+	channel@145 {
+		reg = <PM8350_ADC7_AMUX_THM2_100K_PU(1)>;
+		qcom,hw-settle-time = <200>;
+		qcom,ratiometric;
+		label = "sys_therm2";
+	};
+
+	channel@146 {
+		reg = <PM8350_ADC7_AMUX_THM3_100K_PU(1)>;
+		qcom,hw-settle-time = <200>;
+		qcom,ratiometric;
+		label = "sys_therm3";
+	};
+
+	channel@147 {
+		reg = <PM8350_ADC7_AMUX_THM4_100K_PU(1)>;
+		qcom,hw-settle-time = <200>;
+		qcom,ratiometric;
+		label = "sys_therm4";
+	};
+
+	channel@344 {
+		reg = <PM8350_ADC7_AMUX_THM1_100K_PU(3)>;
+		qcom,hw-settle-time = <200>;
+		qcom,ratiometric;
+		label = "sys_therm5";
+	};
+
+	channel@345 {
+		reg = <PM8350_ADC7_AMUX_THM2_100K_PU(3)>;
+		qcom,hw-settle-time = <200>;
+		qcom,ratiometric;
+		label = "sys_therm6";
+	};
+
+	channel@346 {
+		reg = <PM8350_ADC7_AMUX_THM3_100K_PU(3)>;
+		qcom,hw-settle-time = <200>;
+		qcom,ratiometric;
+		label = "sys_therm7";
+	};
+
+	channel@347 {
+		reg = <PM8350_ADC7_AMUX_THM4_100K_PU(3)>;
+		qcom,hw-settle-time = <200>;
+		qcom,ratiometric;
+		label = "sys_therm8";
+	};
+};
+
+&qup0 {
+	status = "okay";
+};
+
+&qup1 {
+	status = "okay";
+};
+
+&qup2 {
+	status = "okay";
+};
+
+&remoteproc_adsp {
+	firmware-name = "qcom/sc8280xp/HUAWEI/gaokun3/qcadsp8280.mbn";
+
+	status = "okay";
+};
+
+&remoteproc_nsp0 {
+	firmware-name = "qcom/sc8280xp/HUAWEI/gaokun3/qccdsp8280.mbn";
+
+	status = "okay";
+};
+
+&rxmacro {
+	status = "okay";
+};
+
+&sound {
+	compatible = "qcom,sc8280xp-sndcard";
+	model = "SC8280XP-HUAWEI-MATEBOOKEGO";
+	audio-routing = "SpkrLeft IN", "WSA_SPK1 OUT",
+			"SpkrRight IN", "WSA_SPK2 OUT",
+			"IN1_HPHL", "HPHL_OUT",
+			"IN2_HPHR", "HPHR_OUT",
+			"AMIC2", "MIC BIAS2",
+			"VA DMIC0", "MIC BIAS1",
+			"VA DMIC1", "MIC BIAS1",
+			"VA DMIC2", "MIC BIAS3",
+			"VA DMIC0", "VA MIC BIAS1",
+			"VA DMIC1", "VA MIC BIAS1",
+			"VA DMIC2", "VA MIC BIAS3",
+			"TX SWR_ADC1", "ADC2_OUTPUT";
+
+	wcd-playback-dai-link {
+		link-name = "WCD Playback";
+
+		cpu {
+			sound-dai = <&q6apmbedai RX_CODEC_DMA_RX_0>;
+		};
+
+		codec {
+			sound-dai = <&wcd938x 0>, <&swr1 0>, <&rxmacro 0>;
+		};
+
+		platform {
+			sound-dai = <&q6apm>;
+		};
+	};
+
+	wcd-capture-dai-link {
+		link-name = "WCD Capture";
+
+		cpu {
+			sound-dai = <&q6apmbedai TX_CODEC_DMA_TX_3>;
+		};
+
+		codec {
+			sound-dai = <&wcd938x 1>, <&swr2 0>, <&txmacro 0>;
+		};
+
+		platform {
+			sound-dai = <&q6apm>;
+		};
+	};
+
+	wsa-dai-link {
+		link-name = "WSA Playback";
+
+		cpu {
+			sound-dai = <&q6apmbedai WSA_CODEC_DMA_RX_0>;
+		};
+
+		codec {
+			sound-dai = <&left_spkr>, <&right_spkr>, <&swr0 0>, <&wsamacro 0>;
+		};
+
+		platform {
+			sound-dai = <&q6apm>;
+		};
+	};
+
+	va-dai-link {
+		link-name = "VA Capture";
+
+		cpu {
+			sound-dai = <&q6apmbedai VA_CODEC_DMA_TX_0>;
+		};
+
+		platform {
+			sound-dai = <&q6apm>;
+		};
+
+		codec {
+			sound-dai = <&vamacro 0>;
+		};
+	};
+};
+
+&swr0 {
+	status = "okay";
+
+	left_spkr: wsa8830-left@0,1 {
+		compatible = "sdw10217020200";
+		reg = <0 1>;
+		pinctrl-0 = <&spkr_1_sd_n_default>;
+		pinctrl-names = "default";
+		powerdown-gpios = <&tlmm 178 GPIO_ACTIVE_LOW>;
+		#thermal-sensor-cells = <0>;
+		sound-name-prefix = "SpkrLeft";
+		#sound-dai-cells = <0>;
+		vdd-supply = <&vreg_s10b>;
+	};
+
+	right_spkr: wsa8830-right@0,2 {
+		compatible = "sdw10217020200";
+		reg = <0 2>;
+		pinctrl-0 = <&spkr_2_sd_n_default>;
+		pinctrl-names = "default";
+		powerdown-gpios = <&tlmm 179 GPIO_ACTIVE_LOW>;
+		#thermal-sensor-cells = <0>;
+		sound-name-prefix = "SpkrRight";
+		#sound-dai-cells = <0>;
+		vdd-supply = <&vreg_s10b>;
+	};
+};
+
+&swr1 {
+	status = "okay";
+
+	wcd_rx: wcd9380-rx@0,4 {
+		compatible = "sdw20217010d00";
+		reg = <0 4>;
+		qcom,rx-port-mapping = <1 2 3 4 5>;
+	};
+};
+
+&swr2 {
+	status = "okay";
+
+	wcd_tx: wcd9380-tx@0,3 {
+		compatible = "sdw20217010d00";
+		reg = <0 3>;
+		qcom,tx-port-mapping = <1 1 2 3>;
+	};
+};
+
+&txmacro {
+	status = "okay";
+};
+
+&uart2 {
+	pinctrl-0 = <&uart2_default>;
+	pinctrl-names = "default";
+
+	status = "okay";
+
+	bluetooth {
+		compatible = "qcom,wcn6855-bt";
+
+		vddrfacmn-supply = <&vreg_pmu_rfa_cmn_0p8>;
+		vddaon-supply = <&vreg_pmu_aon_0p8>;
+		vddwlcx-supply = <&vreg_pmu_wlcx_0p8>;
+		vddwlmx-supply = <&vreg_pmu_wlmx_0p8>;
+		vddbtcmx-supply = <&vreg_pmu_btcmx_0p8>;
+		vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>;
+		vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>;
+		vddrfa1p8-supply = <&vreg_pmu_rfa_1p7>;
+
+		max-speed = <3200000>;
+	};
+};
+
+&usb_0 {
+	status = "okay";
+};
+
+&usb_0_dwc3 {
+	dr_mode = "host";
+};
+
+&usb_0_hsphy {
+	vdda-pll-supply = <&vreg_l9d>;
+	vdda18-supply = <&vreg_l1c>;
+	vdda33-supply = <&vreg_l7d>;
+
+	status = "okay";
+};
+
+&usb_0_qmpphy {
+	vdda-phy-supply = <&vreg_l9d>;
+	vdda-pll-supply = <&vreg_l4d>;
+
+	orientation-switch;
+
+	status = "okay";
+};
+
+&usb_0_qmpphy_dp_in {
+	remote-endpoint = <&mdss0_dp0_out>;
+};
+
+&usb_1 {
+	status = "okay";
+};
+
+&usb_1_dwc3 {
+	dr_mode = "host";
+};
+
+&usb_1_hsphy {
+	vdda-pll-supply = <&vreg_l4b>;
+	vdda18-supply = <&vreg_l1c>;
+	vdda33-supply = <&vreg_l13c>;
+
+	status = "okay";
+};
+
+&usb_1_qmpphy {
+	vdda-phy-supply = <&vreg_l4b>;
+	vdda-pll-supply = <&vreg_l3b>;
+
+	orientation-switch;
+
+	status = "okay";
+};
+
+&usb_1_qmpphy_dp_in {
+	remote-endpoint = <&mdss0_dp1_out>;
+};
+
+&usb_2 {
+	status = "okay";
+};
+
+&usb_2_hsphy0 {
+	vdda-pll-supply = <&vreg_l1b>;
+	vdda18-supply = <&vreg_l1c>;
+	vdda33-supply = <&vreg_l7d>;
+
+	status = "okay";
+};
+
+&usb_2_hsphy1 {
+	vdda-pll-supply = <&vreg_l8d>;
+	vdda18-supply = <&vreg_l1c>;
+	vdda33-supply = <&vreg_l7d>;
+
+	status = "okay";
+};
+
+&usb_2_hsphy2 {
+	vdda-pll-supply = <&vreg_l10d>;
+	vdda18-supply = <&vreg_l8c>;
+	vdda33-supply = <&vreg_l2d>;
+
+	status = "okay";
+};
+
+&usb_2_hsphy3 {
+	vdda-pll-supply = <&vreg_l10d>;
+	vdda18-supply = <&vreg_l8c>;
+	vdda33-supply = <&vreg_l2d>;
+
+	status = "okay";
+};
+
+&usb_2_qmpphy0 {
+	vdda-phy-supply = <&vreg_l1b>;
+	vdda-pll-supply = <&vreg_l4d>;
+
+	status = "okay";
+};
+
+&usb_2_qmpphy1 {
+	vdda-phy-supply = <&vreg_l8d>;
+	vdda-pll-supply = <&vreg_l4d>;
+
+	status = "okay";
+};
+
+&vamacro {
+	pinctrl-0 = <&dmic01_default>, <&dmic23_default>;
+	pinctrl-names = "default";
+
+	vdd-micb-supply = <&vreg_s10b>;
+
+	qcom,dmic-sample-rate = <4800000>;
+
+	status = "okay";
+};
+
+&wsamacro {
+	status = "okay";
+};
+
+&xo_board_clk {
+	clock-frequency = <38400000>;
+};
+
+/* PINCTRL */
+
+&lpass_tlmm {
+	status = "okay";
+};
+
+&pmc8280_1_gpios {
+	misc_3p3_reg_en: misc-3p3-reg-en-state {
+		pins = "gpio1";
+		function = "normal";
+	};
+
+	vol_up_n: vol-up-n-state {
+		pins = "gpio6";
+		function = "normal";
+		power-source = <1>;
+		input-enable;
+		bias-pull-up;
+	};
+};
+
+&pmr735a_gpios {
+	hastings_reg_en: hastings-reg-en-state {
+		pins = "gpio1";
+		function = "normal";
+	};
+};
+
+&tlmm {
+
+	gpio-reserved-ranges = <70 2>, <74 6>, <83 4>, <125 2>, <128 2>, <154 4>;
+
+	bt_default: bt-default-state {
+		hstp-bt-en-pins {
+			pins = "gpio133";
+			function = "gpio";
+			drive-strength = <16>;
+			bias-disable;
+		};
+
+		hstp-sw-ctrl-pins {
+			pins = "gpio132";
+			function = "gpio";
+			bias-pull-down;
+		};
+	};
+
+	i2c4_default: i2c4-default-state {
+		pins = "gpio171", "gpio172";
+		function = "qup4";
+		drive-strength = <16>;
+		bias-disable;
+	};
+
+	mode_pin_active: mode-pin-state {
+		pins = "gpio26";
+		function = "gpio";
+		bias-disable;
+	};
+
+	nvme_reg_en: nvme-reg-en-state {
+		pins = "gpio135";
+		function = "gpio";
+		drive-strength = <2>;
+		bias-disable;
+	};
+
+	pcie2a_default: pcie2a-default-state {
+		clkreq-n-pins {
+			pins = "gpio142";
+			function = "pcie2a_clkreq";
+			drive-strength = <2>;
+			bias-pull-up;
+		};
+
+		perst-n-pins {
+			pins = "gpio143";
+			function = "gpio";
+			drive-strength = <2>;
+			bias-disable;
+		};
+
+		wake-n-pins {
+		       pins = "gpio145";
+		       function = "gpio";
+		       drive-strength = <2>;
+		       bias-pull-up;
+	       };
+	};
+
+	pcie4_default: pcie4-default-state {
+		clkreq-n-pins {
+			pins = "gpio140";
+			function = "pcie4_clkreq";
+			drive-strength = <2>;
+			bias-pull-up;
+		};
+
+		perst-n-pins {
+			pins = "gpio141";
+			function = "gpio";
+			drive-strength = <2>;
+			bias-disable;
+		};
+
+		wake-n-pins {
+			pins = "gpio139";
+			function = "gpio";
+			drive-strength = <2>;
+			bias-pull-up;
+		};
+	};
+
+	spkr_1_sd_n_default: spkr-1-sd-n-default-state {
+		perst-n-pins {
+			pins = "gpio178";
+			function = "gpio";
+			drive-strength = <16>;
+			bias-disable;
+			output-high;
+		};
+	};
+
+	spkr_2_sd_n_default: spkr-2-sd-n-default-state {
+		perst-n-pins {
+			pins = "gpio179";
+			function = "gpio";
+			drive-strength = <16>;
+			bias-disable;
+			output-high;
+		};
+	};
+
+	ts0_default: ts0-default-state {
+		int-n-pins {
+			pins = "gpio175";
+			function = "gpio";
+			drive-strength = <2>;
+			bias-disable;
+		};
+
+		reset-n-pins {
+			pins = "gpio99";
+			function = "gpio";
+			drive-strength = <2>;
+			bias-disable;
+			output-high;
+		};
+	};
+
+	uart2_default: uart2-default-state {
+		cts-pins {
+			pins = "gpio121";
+			function = "qup2";
+			bias-bus-hold;
+		};
+
+		rts-pins {
+			pins = "gpio122";
+			function = "qup2";
+			drive-strength = <2>;
+			bias-disable;
+		};
+
+		rx-pins {
+			pins = "gpio124";
+			function = "qup2";
+			bias-pull-up;
+		};
+
+		tx-pins {
+			pins = "gpio123";
+			function = "qup2";
+			drive-strength = <2>;
+			bias-disable;
+		};
+	};
+
+	wcd_default: wcd-default-state {
+		reset-pins {
+			pins = "gpio106";
+			function = "gpio";
+			bias-disable;
+		};
+	};
+
+	wlan_en: wlan-en-state {
+		pins = "gpio134";
+		function = "gpio";
+		drive-strength = <8>;
+		bias-pull-down;
+	};
+};
diff --git a/dts/upstream/src/arm64/qcom/sc8280xp-microsoft-blackrock.dts b/dts/upstream/src/arm64/qcom/sc8280xp-microsoft-blackrock.dts
new file mode 100644
index 00000000000..fa9d9410505
--- /dev/null
+++ b/dts/upstream/src/arm64/qcom/sc8280xp-microsoft-blackrock.dts
@@ -0,0 +1,1325 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2021, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2022, Linaro Limited
+ * Copyright (c) 2023, Merck Hung <merckhung@gmail.com>
+ * Copyright (c) 2023, 2024 Jens Glathe <jens.glathe@oldschoolsolutions.biz>
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/iio/qcom,spmi-adc7-pm8350.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/gpio-keys.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
+
+#include "sc8280xp.dtsi"
+#include "sc8280xp-pmics.dtsi"
+
+/ {
+	model = "Windows Dev Kit 2023";
+	compatible = "microsoft,blackrock", "qcom,sc8280xp";
+	chassis-type = "desktop";
+
+	aliases {
+		i2c4 = &i2c4;
+		i2c21 = &i2c21;
+		serial1 = &uart2;
+	};
+
+	wcd938x: audio-codec {
+		compatible = "qcom,wcd9380-codec";
+
+		pinctrl-0 = <&wcd_default>;
+		pinctrl-names = "default";
+
+		reset-gpios = <&tlmm 106 GPIO_ACTIVE_LOW>;
+
+		vdd-buck-supply = <&vreg_s10b>;
+		vdd-rxtx-supply = <&vreg_s10b>;
+		vdd-io-supply = <&vreg_s10b>;
+		vdd-mic-bias-supply = <&vreg_bob>;
+
+		qcom,micbias1-microvolt = <1800000>;
+		qcom,micbias2-microvolt = <1800000>;
+		qcom,micbias3-microvolt = <1800000>;
+		qcom,micbias4-microvolt = <1800000>;
+		qcom,mbhc-buttons-vthreshold-microvolt = <75000 150000 237000 500000 500000 500000 500000 500000>;
+		qcom,mbhc-headset-vthreshold-microvolt = <1700000>;
+		qcom,mbhc-headphone-vthreshold-microvolt = <50000>;
+		qcom,rx-device = <&wcd_rx>;
+		qcom,tx-device = <&wcd_tx>;
+
+		#sound-dai-cells = <1>;
+	};
+
+	dp3_connector: connector {
+		compatible = "dp-connector";
+		label = "DP-3";
+		type = "mini";
+
+		dp-pwr-supply = <&vreg_misc_3p3>;
+
+		port {
+			dp1_connector_in: endpoint {
+				remote-endpoint = <&mdss0_dp2_phy_out>;
+			};
+		};
+	};
+
+	pmic-glink {
+		compatible = "qcom,sc8280xp-pmic-glink", "qcom,pmic-glink";
+
+		#address-cells = <1>;
+		#size-cells = <0>;
+		orientation-gpios = <&tlmm 166 GPIO_ACTIVE_HIGH>,
+				    <&tlmm 49 GPIO_ACTIVE_HIGH>;
+
+		/* Left-side rear port */
+		connector@0 {
+			compatible = "usb-c-connector";
+			reg = <0>;
+			power-role = "source";
+			data-role = "dual";
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					reg = <0>;
+
+					pmic_glink_con0_hs: endpoint {
+						remote-endpoint = <&usb_0_dwc3_hs>;
+					};
+				};
+
+				port@1 {
+					reg = <1>;
+
+					pmic_glink_con0_ss: endpoint {
+						remote-endpoint = <&usb_0_qmpphy_out>;
+					};
+				};
+
+				port@2 {
+					reg = <2>;
+
+					pmic_glink_con0_sbu: endpoint {
+						remote-endpoint = <&usb0_sbu_mux>;
+					};
+				};
+			};
+		};
+
+		/* Left-side front port */
+		connector@1 {
+			compatible = "usb-c-connector";
+			reg = <1>;
+			power-role = "source";
+			data-role = "dual";
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					reg = <0>;
+
+					pmic_glink_con1_hs: endpoint {
+						remote-endpoint = <&usb_1_dwc3_hs>;
+					};
+				};
+
+				port@1 {
+					reg = <1>;
+
+					pmic_glink_con1_ss: endpoint {
+						remote-endpoint = <&usb_1_qmpphy_out>;
+					};
+				};
+
+				port@2 {
+					reg = <2>;
+
+					pmic_glink_con1_sbu: endpoint {
+						remote-endpoint = <&usb1_sbu_mux>;
+					};
+				};
+			};
+		};
+	};
+
+	vreg_misc_3p3: regulator-misc-3p3 {
+		compatible = "regulator-fixed";
+
+		regulator-name = "VCC3B";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+
+		gpio = <&pmc8280_1_gpios 1 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+
+		pinctrl-0 = <&misc_3p3_reg_en>;
+		pinctrl-names = "default";
+
+		regulator-boot-on;
+		regulator-always-on;
+	};
+
+	vreg_nvme: regulator-nvme {
+		compatible = "regulator-fixed";
+
+		regulator-name = "VCC3_SSD";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+
+		gpio = <&tlmm 135 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+
+		pinctrl-0 = <&nvme_reg_en>;
+		pinctrl-names = "default";
+
+		regulator-boot-on;
+	};
+
+	vreg_vph_pwr: regulator-vph-pwr {
+		compatible = "regulator-fixed";
+
+		regulator-name = "VPH_VCC3R9";
+		regulator-min-microvolt = <3900000>;
+		regulator-max-microvolt = <3900000>;
+
+		regulator-always-on;
+	};
+
+	vreg_wlan: regulator-wlan {
+		compatible = "regulator-fixed";
+
+		regulator-name = "VCC_WLAN_3R9";
+		regulator-min-microvolt = <3900000>;
+		regulator-max-microvolt = <3900000>;
+
+		gpio = <&pmr735a_gpios 1 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+
+		pinctrl-0 = <&hastings_reg_en>;
+		pinctrl-names = "default";
+
+		regulator-boot-on;
+	};
+
+	vreg_wwan: regulator-wwan {
+		compatible = "regulator-fixed";
+
+		regulator-name = "VCC3B_WAN";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+
+		gpio = <&pmc8280_2_gpios 1 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+
+		pinctrl-0 = <&wwan_sw_en>;
+		pinctrl-names = "default";
+
+		regulator-boot-on;
+	};
+
+	reserved-memory {
+		gpu_mem: gpu-mem@8bf00000 {
+			reg = <0 0x8bf00000 0 0x2000>;
+			no-map;
+		};
+
+		linux,cma {
+			compatible = "shared-dma-pool";
+			size = <0x0 0x8000000>;
+			reusable;
+			linux,cma-default;
+		};
+	};
+
+	usb0-sbu-mux {
+		compatible = "pericom,pi3usb102", "gpio-sbu-mux";
+
+		enable-gpios = <&tlmm 101 GPIO_ACTIVE_LOW>;
+		select-gpios = <&tlmm 164 GPIO_ACTIVE_HIGH>;
+
+		pinctrl-0 = <&usb0_sbu_default>;
+		pinctrl-names = "default";
+
+		mode-switch;
+		orientation-switch;
+
+		port {
+			usb0_sbu_mux: endpoint {
+				remote-endpoint = <&pmic_glink_con0_sbu>;
+			};
+		};
+	};
+
+	usb1-sbu-mux {
+		compatible = "pericom,pi3usb102", "gpio-sbu-mux";
+
+		enable-gpios = <&tlmm 48 GPIO_ACTIVE_LOW>;
+		select-gpios = <&tlmm 47 GPIO_ACTIVE_HIGH>;
+
+		pinctrl-0 = <&usb1_sbu_default>;
+		pinctrl-names = "default";
+
+		mode-switch;
+		orientation-switch;
+
+		port {
+			usb1_sbu_mux: endpoint {
+				remote-endpoint = <&pmic_glink_con1_sbu>;
+			};
+		};
+	};
+
+	wcn6855-pmu {
+		compatible = "qcom,wcn6855-pmu";
+
+		pinctrl-0 = <&bt_default>, <&wlan_en>;
+		pinctrl-names = "default";
+
+		wlan-enable-gpios = <&tlmm 134 GPIO_ACTIVE_HIGH>;
+		bt-enable-gpios = <&tlmm 133 GPIO_ACTIVE_HIGH>;
+		swctrl-gpios = <&tlmm 132 GPIO_ACTIVE_HIGH>;
+
+		vddio-supply = <&vreg_s10b>;
+		vddaon-supply = <&vreg_s12b>;
+		vddpmu-supply = <&vreg_s12b>;
+		vddpmumx-supply = <&vreg_s12b>;
+		vddpmucx-supply = <&vreg_s12b>;
+		vddrfa0p95-supply = <&vreg_s12b>;
+		vddrfa1p3-supply = <&vreg_s11b>;
+		vddrfa1p9-supply = <&vreg_s1c>;
+		vddpcie1p3-supply = <&vreg_s11b>;
+		vddpcie1p9-supply = <&vreg_s1c>;
+
+		regulators {
+			vreg_pmu_rfa_cmn_0p8: ldo0 {
+				regulator-name = "vreg_pmu_rfa_cmn_0p8";
+			};
+
+			vreg_pmu_aon_0p8: ldo1 {
+				regulator-name = "vreg_pmu_aon_0p8";
+			};
+
+			vreg_pmu_wlcx_0p8: ldo2 {
+				regulator-name = "vreg_pmu_wlcx_0p8";
+			};
+
+			vreg_pmu_wlmx_0p8: ldo3 {
+				regulator-name = "vreg_pmu_wlmx_0p8";
+			};
+
+			vreg_pmu_btcmx_0p8: ldo4 {
+				regulator-name = "vreg_pmu_btcmx_0p8";
+			};
+
+			vreg_pmu_pcie_1p8: ldo5 {
+				regulator-name = "vreg_pmu_pcie_1p8";
+			};
+
+			vreg_pmu_pcie_0p9: ldo6 {
+				regulator-name = "vreg_pmu_pcie_0p9";
+			};
+
+			vreg_pmu_rfa_0p8: ldo7 {
+				regulator-name = "vreg_pmu_rfa_0p8";
+			};
+
+			vreg_pmu_rfa_1p2: ldo8 {
+				regulator-name = "vreg_pmu_rfa_1p2";
+			};
+
+			vreg_pmu_rfa_1p7: ldo9 {
+				regulator-name = "vreg_pmu_rfa_1p7";
+			};
+		};
+	};
+};
+
+&apps_rsc {
+	regulators-0 {
+		compatible = "qcom,pm8350-rpmh-regulators";
+		qcom,pmic-id = "b";
+
+		vdd-s10-supply = <&vreg_vph_pwr>;
+		vdd-s11-supply = <&vreg_vph_pwr>;
+		vdd-s12-supply = <&vreg_vph_pwr>;
+		vdd-l1-l4-supply = <&vreg_s12b>;
+		vdd-l2-l7-supply = <&vreg_bob>;
+		vdd-l3-l5-supply = <&vreg_s11b>;
+		vdd-l6-l9-l10-supply = <&vreg_s12b>;
+		vdd-l8-supply = <&vreg_s12b>;
+
+		vreg_s10b: smps10 {
+			regulator-name = "vreg_s10b";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-always-on;
+		};
+
+		vreg_s11b: smps11 {
+			regulator-name = "vreg_s11b";
+			regulator-min-microvolt = <1272000>;
+			regulator-max-microvolt = <1272000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_s12b: smps12 {
+			regulator-name = "vreg_s12b";
+			regulator-min-microvolt = <984000>;
+			regulator-max-microvolt = <984000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l1b: ldo1 {
+			regulator-name = "vreg_l1b";
+			regulator-min-microvolt = <912000>;
+			regulator-max-microvolt = <912000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l3b: ldo3 {
+			regulator-name = "vreg_l3b";
+			regulator-min-microvolt = <1200000>;
+			regulator-max-microvolt = <1200000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-boot-on;
+		};
+
+		vreg_l4b: ldo4 {
+			regulator-name = "vreg_l4b";
+			regulator-min-microvolt = <912000>;
+			regulator-max-microvolt = <912000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l6b: ldo6 {
+			regulator-name = "vreg_l6b";
+			regulator-min-microvolt = <880000>;
+			regulator-max-microvolt = <880000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-boot-on;
+		};
+	};
+
+	regulators-1 {
+		compatible = "qcom,pm8350c-rpmh-regulators";
+		qcom,pmic-id = "c";
+
+		vdd-bob-supply = <&vreg_vph_pwr>;
+		vdd-l1-l12-supply = <&vreg_s1c>;
+		vdd-l2-l8-supply = <&vreg_s1c>;
+		vdd-l3-l4-l5-l7-l13-supply = <&vreg_bob>;
+		vdd-l6-l9-l11-supply = <&vreg_bob>;
+		vdd-l10-supply = <&vreg_s11b>;
+
+		vreg_s1c: smps1 {
+			regulator-name = "vreg_s1c";
+			regulator-min-microvolt = <1880000>;
+			regulator-max-microvolt = <1900000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-always-on;
+		};
+
+		vreg_l1c: ldo1 {
+			regulator-name = "vreg_l1c";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l6c: ldo6 {
+			regulator-name = "vreg_l6c";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <2960000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l7c: ldo7 {
+			regulator-name = "vreg_l7c";
+			regulator-min-microvolt = <2504000>;
+			regulator-max-microvolt = <2504000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l8c: ldo8 {
+			regulator-name = "vreg_l8c";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l9c: ldo9 {
+			regulator-name = "vreg_l9c";
+			regulator-min-microvolt = <2960000>;
+			regulator-max-microvolt = <2960000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l12c: ldo12 {
+			regulator-name = "vreg_l12c";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l13c: ldo13 {
+			regulator-name = "vreg_l13c";
+			regulator-min-microvolt = <3072000>;
+			regulator-max-microvolt = <3072000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_bob: bob {
+			regulator-name = "vreg_bob";
+			regulator-min-microvolt = <3008000>;
+			regulator-max-microvolt = <3960000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
+			regulator-always-on;
+		};
+	};
+
+	regulators-2 {
+		compatible = "qcom,pm8350-rpmh-regulators";
+		qcom,pmic-id = "d";
+
+		vdd-l1-l4-supply = <&vreg_s11b>;
+		vdd-l2-l7-supply = <&vreg_bob>;
+		vdd-l3-l5-supply = <&vreg_s11b>;
+		vdd-l6-l9-l10-supply = <&vreg_s12b>;
+		vdd-l8-supply = <&vreg_s12b>;
+
+		vreg_l2d: ldo2 {
+			regulator-name = "vreg_l2d";
+			regulator-min-microvolt = <3072000>;
+			regulator-max-microvolt = <3072000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l3d: ldo3 {
+			regulator-name = "vreg_l3d";
+			regulator-min-microvolt = <1200000>;
+			regulator-max-microvolt = <1200000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+				 RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l4d: ldo4 {
+			regulator-name = "vreg_l4d";
+			regulator-min-microvolt = <1200000>;
+			regulator-max-microvolt = <1200000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l6d: ldo6 {
+			regulator-name = "vreg_l6d";
+			regulator-min-microvolt = <880000>;
+			regulator-max-microvolt = <880000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l7d: ldo7 {
+			regulator-name = "vreg_l7d";
+			regulator-min-microvolt = <3072000>;
+			regulator-max-microvolt = <3072000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l8d: ldo8 {
+			regulator-name = "vreg_l8d";
+			regulator-min-microvolt = <912000>;
+			regulator-max-microvolt = <912000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l9d: ldo9 {
+			regulator-name = "vreg_l9d";
+			regulator-min-microvolt = <912000>;
+			regulator-max-microvolt = <912000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l10d: ldo10 {
+			regulator-name = "vreg_l10d";
+			regulator-min-microvolt = <912000>;
+			regulator-max-microvolt = <912000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+	};
+};
+
+&dispcc0 {
+	status = "okay";
+};
+
+&gpu {
+	status = "okay";
+
+	zap-shader {
+		memory-region = <&gpu_mem>;
+		firmware-name = "qcom/sc8280xp/microsoft/blackrock/qcdxkmsuc8280.mbn";
+	};
+};
+
+&mdss0 {
+	status = "okay";
+};
+
+&mdss0_dp0 {
+	status = "okay";
+};
+
+&mdss0_dp0_out {
+	data-lanes = <0 1>;
+	remote-endpoint = <&usb_0_qmpphy_dp_in>;
+};
+
+&mdss0_dp1 {
+	status = "okay";
+};
+
+&mdss0_dp1_out {
+	data-lanes = <0 1>;
+	remote-endpoint = <&usb_1_qmpphy_dp_in>;
+};
+
+&mdss0_dp2 {
+	compatible = "qcom,sc8280xp-dp";
+
+	data-lanes = <0 1 2 3>;
+
+	status = "okay";
+
+	ports {
+		port@1 {
+			reg = <1>;
+			mdss0_dp2_phy_out: endpoint {
+				remote-endpoint = <&dp1_connector_in>;
+			};
+		};
+	};
+};
+
+&mdss0_dp2_phy {
+	compatible = "qcom,sc8280xp-dp-phy";
+
+	vdda-phy-supply = <&vreg_l3b>;
+	vdda-pll-supply = <&vreg_l6b>;
+
+	status = "okay";
+};
+
+&pcie2a {
+	perst-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>;
+	wake-gpios = <&tlmm 145 GPIO_ACTIVE_LOW>;
+
+	vddpe-3v3-supply = <&vreg_nvme>;
+
+	pinctrl-0 = <&pcie2a_default>;
+	pinctrl-names = "default";
+
+	status = "okay";
+};
+
+&pcie2a_phy {
+	vdda-phy-supply = <&vreg_l4d>;
+	vdda-pll-supply = <&vreg_l6d>;
+
+	status = "okay";
+};
+
+&pcie4 {
+	max-link-speed = <2>;
+
+	perst-gpios = <&tlmm 141 GPIO_ACTIVE_LOW>;
+	wake-gpios = <&tlmm 139 GPIO_ACTIVE_LOW>;
+
+	vddpe-3v3-supply = <&vreg_wlan>;
+
+	pinctrl-0 = <&pcie4_default>;
+	pinctrl-names = "default";
+
+	status = "okay";
+};
+
+&pcie4_port0 {
+	wifi@0 {
+		compatible = "pci17cb,1103";
+		reg = <0x10000 0x0 0x0 0x0 0x0>;
+
+		vddrfacmn-supply = <&vreg_pmu_rfa_cmn_0p8>;
+		vddaon-supply = <&vreg_pmu_aon_0p8>;
+		vddwlcx-supply = <&vreg_pmu_wlcx_0p8>;
+		vddwlmx-supply = <&vreg_pmu_wlmx_0p8>;
+		vddpcie1p8-supply = <&vreg_pmu_pcie_1p8>;
+		vddpcie0p9-supply = <&vreg_pmu_pcie_0p9>;
+		vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>;
+		vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>;
+		vddrfa1p8-supply = <&vreg_pmu_rfa_1p7>;
+
+		qcom,ath11k-calibration-variant = "MS_Volterra";
+	};
+};
+
+&pcie4_phy {
+	vdda-phy-supply = <&vreg_l4d>;
+	vdda-pll-supply = <&vreg_l6d>;
+
+	status = "okay";
+};
+
+&pmc8280c_lpg {
+	status = "okay";
+};
+
+&pmk8280_adc_tm {
+	status = "okay";
+
+	sys-therm@0 {
+		reg = <0>;
+		io-channels = <&pmk8280_vadc PM8350_ADC7_AMUX_THM1_100K_PU(1)>;
+		qcom,hw-settle-time-us = <200>;
+		qcom,avg-samples = <2>;
+		qcom,ratiometric;
+	};
+
+	sys-therm@1 {
+		reg = <1>;
+		io-channels = <&pmk8280_vadc PM8350_ADC7_AMUX_THM2_100K_PU(1)>;
+		qcom,hw-settle-time-us = <200>;
+		qcom,avg-samples = <2>;
+		qcom,ratiometric;
+	};
+
+	sys-therm@2 {
+		reg = <2>;
+		io-channels = <&pmk8280_vadc PM8350_ADC7_AMUX_THM3_100K_PU(1)>;
+		qcom,hw-settle-time-us = <200>;
+		qcom,avg-samples = <2>;
+		qcom,ratiometric;
+	};
+
+	sys-therm@3 {
+		reg = <3>;
+		io-channels = <&pmk8280_vadc PM8350_ADC7_AMUX_THM4_100K_PU(1)>;
+		qcom,hw-settle-time-us = <200>;
+		qcom,avg-samples = <2>;
+		qcom,ratiometric;
+	};
+
+	sys-therm@4 {
+		reg = <4>;
+		io-channels = <&pmk8280_vadc PM8350_ADC7_AMUX_THM1_100K_PU(3)>;
+		qcom,hw-settle-time-us = <200>;
+		qcom,avg-samples = <2>;
+		qcom,ratiometric;
+	};
+
+	sys-therm@5 {
+		reg = <5>;
+		io-channels = <&pmk8280_vadc PM8350_ADC7_AMUX_THM2_100K_PU(3)>;
+		qcom,hw-settle-time-us = <200>;
+		qcom,avg-samples = <2>;
+		qcom,ratiometric;
+	};
+
+	sys-therm@6 {
+		reg = <6>;
+		io-channels = <&pmk8280_vadc PM8350_ADC7_AMUX_THM3_100K_PU(3)>;
+		qcom,hw-settle-time-us = <200>;
+		qcom,avg-samples = <2>;
+		qcom,ratiometric;
+	};
+
+	sys-therm@7 {
+		reg = <7>;
+		io-channels = <&pmk8280_vadc PM8350_ADC7_AMUX_THM4_100K_PU(3)>;
+		qcom,hw-settle-time-us = <200>;
+		qcom,avg-samples = <2>;
+		qcom,ratiometric;
+	};
+};
+
+&pmk8280_pon_pwrkey {
+	status = "okay";
+};
+
+&pmk8280_pon_resin {
+	status = "okay";
+};
+
+&pmk8280_rtc {
+	nvmem-cells = <&rtc_offset>;
+	nvmem-cell-names = "offset";
+
+	status = "okay";
+};
+
+&pmk8280_sdam_6 {
+	status = "okay";
+
+	rtc_offset: rtc-offset@bc {
+		reg = <0xbc 0x4>;
+	};
+};
+
+&pmk8280_vadc {
+	channel@144 {
+		reg = <PM8350_ADC7_AMUX_THM1_100K_PU(1)>;
+		qcom,hw-settle-time = <200>;
+		qcom,ratiometric;
+		label = "sys_therm1";
+	};
+
+	channel@145 {
+		reg = <PM8350_ADC7_AMUX_THM2_100K_PU(1)>;
+		qcom,hw-settle-time = <200>;
+		qcom,ratiometric;
+		label = "sys_therm2";
+	};
+
+	channel@146 {
+		reg = <PM8350_ADC7_AMUX_THM3_100K_PU(1)>;
+		qcom,hw-settle-time = <200>;
+		qcom,ratiometric;
+		label = "sys_therm3";
+	};
+
+	channel@147 {
+		reg = <PM8350_ADC7_AMUX_THM4_100K_PU(1)>;
+		qcom,hw-settle-time = <200>;
+		qcom,ratiometric;
+		label = "sys_therm4";
+	};
+
+	channel@344 {
+		reg = <PM8350_ADC7_AMUX_THM1_100K_PU(3)>;
+		qcom,hw-settle-time = <200>;
+		qcom,ratiometric;
+		label = "sys_therm5";
+	};
+
+	channel@345 {
+		reg = <PM8350_ADC7_AMUX_THM2_100K_PU(3)>;
+		qcom,hw-settle-time = <200>;
+		qcom,ratiometric;
+		label = "sys_therm6";
+	};
+
+	channel@346 {
+		reg = <PM8350_ADC7_AMUX_THM3_100K_PU(3)>;
+		qcom,hw-settle-time = <200>;
+		qcom,ratiometric;
+		label = "sys_therm7";
+	};
+
+	channel@347 {
+		reg = <PM8350_ADC7_AMUX_THM4_100K_PU(3)>;
+		qcom,hw-settle-time = <200>;
+		qcom,ratiometric;
+		label = "sys_therm8";
+	};
+};
+
+&qup0 {
+	status = "okay";
+};
+
+&qup1 {
+	status = "okay";
+};
+
+&qup2 {
+	status = "okay";
+};
+
+&remoteproc_adsp {
+	firmware-name = "qcom/sc8280xp/microsoft/blackrock/qcadsp8280.mbn";
+
+	status = "okay";
+};
+
+&remoteproc_nsp0 {
+	firmware-name = "qcom/sc8280xp/microsoft/blackrock/qccdsp8280.mbn";
+
+	status = "okay";
+};
+
+&rxmacro {
+	status = "okay";
+};
+
+&sound {
+	compatible = "qcom,sc8280xp-sndcard";
+	model = "microsoft/blackrock";
+
+	wcd-playback-dai-link {
+		link-name = "WCD Playback";
+
+		cpu {
+			sound-dai = <&q6apmbedai RX_CODEC_DMA_RX_0>;
+		};
+
+		codec {
+			sound-dai = <&wcd938x 0>, <&swr1 0>, <&rxmacro 0>;
+		};
+
+		platform {
+			sound-dai = <&q6apm>;
+		};
+	};
+
+	wcd-capture-dai-link {
+		link-name = "WCD Capture";
+
+		cpu {
+			sound-dai = <&q6apmbedai TX_CODEC_DMA_TX_3>;
+		};
+
+		codec {
+			sound-dai = <&wcd938x 1>, <&swr2 0>, <&txmacro 0>;
+		};
+
+		platform {
+			sound-dai = <&q6apm>;
+		};
+	};
+
+	wsa-dai-link {
+		link-name = "WSA Playback";
+
+		cpu {
+			sound-dai = <&q6apmbedai WSA_CODEC_DMA_RX_0>;
+		};
+
+		codec {
+			sound-dai = <&swr0 0>, <&wsamacro 0>;
+		};
+
+		platform {
+			sound-dai = <&q6apm>;
+		};
+	};
+
+	va-dai-link {
+		link-name = "VA Capture";
+
+		cpu {
+			sound-dai = <&q6apmbedai VA_CODEC_DMA_TX_0>;
+		};
+
+		platform {
+			sound-dai = <&q6apm>;
+		};
+
+		codec {
+			sound-dai = <&vamacro 0>;
+		};
+	};
+};
+
+&swr0 {
+	status = "okay";
+};
+
+&swr1 {
+	status = "okay";
+
+	wcd_rx: wcd9380-rx@0,4 {
+		compatible = "sdw20217010d00";
+		reg = <0 4>;
+		qcom,rx-port-mapping = <1 2 3 4 5>;
+	};
+};
+
+&swr2 {
+	status = "okay";
+
+	wcd_tx: wcd9380-tx@0,3 {
+		compatible = "sdw20217010d00";
+		reg = <0 3>;
+		qcom,tx-port-mapping = <1 1 2 3>;
+	};
+};
+
+&txmacro {
+	status = "okay";
+};
+
+&uart2 {
+	pinctrl-0 = <&uart2_default>;
+	pinctrl-names = "default";
+
+	status = "okay";
+
+	bluetooth {
+		compatible = "qcom,wcn6855-bt";
+
+		vddrfacmn-supply = <&vreg_pmu_rfa_cmn_0p8>;
+		vddaon-supply = <&vreg_pmu_aon_0p8>;
+		vddwlcx-supply = <&vreg_pmu_wlcx_0p8>;
+		vddwlmx-supply = <&vreg_pmu_wlmx_0p8>;
+		vddbtcmx-supply = <&vreg_pmu_btcmx_0p8>;
+		vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>;
+		vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>;
+		vddrfa1p8-supply = <&vreg_pmu_rfa_1p7>;
+
+		max-speed = <3200000>;
+	};
+};
+
+&usb_0 {
+	status = "okay";
+};
+
+&usb_0_dwc3 {
+	dr_mode = "host";
+};
+
+&usb_0_dwc3_hs {
+	remote-endpoint = <&pmic_glink_con0_hs>;
+};
+
+&usb_0_hsphy {
+	vdda-pll-supply = <&vreg_l9d>;
+	vdda18-supply = <&vreg_l1c>;
+	vdda33-supply = <&vreg_l7d>;
+
+	status = "okay";
+};
+
+&usb_0_qmpphy {
+	vdda-phy-supply = <&vreg_l4d>;
+	vdda-pll-supply = <&vreg_l9d>;
+
+	orientation-switch;
+
+	status = "okay";
+};
+
+&usb_0_qmpphy_dp_in {
+	remote-endpoint = <&mdss0_dp0_out>;
+};
+
+&usb_0_qmpphy_out {
+	remote-endpoint = <&pmic_glink_con0_ss>;
+};
+
+&usb_1 {
+	status = "okay";
+};
+
+&usb_1_dwc3 {
+	dr_mode = "host";
+};
+
+&usb_1_dwc3_hs {
+	remote-endpoint = <&pmic_glink_con1_hs>;
+};
+
+&usb_1_hsphy {
+	vdda-pll-supply = <&vreg_l4b>;
+	vdda18-supply = <&vreg_l1c>;
+	vdda33-supply = <&vreg_l13c>;
+
+	status = "okay";
+};
+
+&usb_1_qmpphy {
+	vdda-phy-supply = <&vreg_l3b>;
+	vdda-pll-supply = <&vreg_l4b>;
+
+	orientation-switch;
+
+	status = "okay";
+};
+
+&usb_1_qmpphy_dp_in {
+	remote-endpoint = <&mdss0_dp1_out>;
+};
+
+&usb_1_qmpphy_out {
+	remote-endpoint = <&pmic_glink_con1_ss>;
+};
+
+&usb_2 {
+	pinctrl-0 = <&usb2_en_state>;
+	pinctrl-names = "default";
+
+	status = "okay";
+};
+
+&usb_2_dwc3 {
+	phys = <&usb_2_hsphy0>, <&usb_2_qmpphy0>;
+	phy-names = "usb2-0", "usb3-0";
+};
+
+&usb_2_hsphy0 {
+	vdda-pll-supply = <&vreg_l1b>;
+	vdda18-supply = <&vreg_l1c>;
+	vdda33-supply = <&vreg_l7d>;
+
+	status = "okay";
+};
+
+&usb_2_qmpphy0 {
+	vdda-phy-supply = <&vreg_l1b>;
+	vdda-pll-supply = <&vreg_l4d>;
+
+	status = "okay";
+};
+
+&vamacro {
+	pinctrl-0 = <&dmic01_default>, <&dmic23_default>;
+	pinctrl-names = "default";
+
+	vdd-micb-supply = <&vreg_s10b>;
+
+	qcom,dmic-sample-rate = <4800000>;
+
+	status = "okay";
+};
+
+&wsamacro {
+	status = "okay";
+};
+
+&xo_board_clk {
+	clock-frequency = <38400000>;
+};
+
+/* PINCTRL */
+
+&lpass_tlmm {
+	status = "okay";
+};
+
+&pmc8280_1_gpios {
+	misc_3p3_reg_en: misc-3p3-reg-en-state {
+		pins = "gpio1";
+		function = "normal";
+	};
+
+	edp_bl_en: edp-bl-en-state {
+		pins = "gpio8";
+		function = "normal";
+	};
+
+	edp_bl_reg_en: edp-bl-reg-en-state {
+		pins = "gpio9";
+		function = "normal";
+	};
+};
+
+&pmc8280_2_gpios {
+	wwan_sw_en: wwan-sw-en-state {
+		pins = "gpio1";
+		function = "normal";
+	};
+};
+
+&pmc8280c_gpios {
+	edp_bl_pwm: edp-bl-pwm-state {
+		pins = "gpio8";
+		function = "func1";
+	};
+};
+
+&pmr735a_gpios {
+	hastings_reg_en: hastings-reg-en-state {
+		pins = "gpio1";
+		function = "normal";
+	};
+};
+
+&tlmm {
+	bt_default: bt-default-state {
+		hstp-bt-en-pins {
+			pins = "gpio133";
+			function = "gpio";
+			drive-strength = <16>;
+			bias-disable;
+		};
+
+		hstp-sw-ctrl-pins {
+			pins = "gpio132";
+			function = "gpio";
+			bias-pull-down;
+		};
+	};
+
+	nvme_reg_en: nvme-reg-en-state {
+		pins = "gpio135";
+		function = "gpio";
+		drive-strength = <2>;
+		bias-disable;
+	};
+
+	pcie2a_default: pcie2a-default-state {
+		clkreq-n-pins {
+			pins = "gpio142";
+			function = "pcie2a_clkreq";
+			drive-strength = <2>;
+			bias-pull-up;
+		};
+
+		perst-n-pins {
+			pins = "gpio143";
+			function = "gpio";
+			drive-strength = <2>;
+			bias-disable;
+		};
+
+		wake-n-pins {
+			pins = "gpio145";
+			function = "gpio";
+			drive-strength = <2>;
+			bias-pull-up;
+		};
+	};
+
+	pcie3a_default: pcie3a-default-state {
+		clkreq-n-pins {
+			pins = "gpio150";
+			function = "pcie3a_clkreq";
+			drive-strength = <2>;
+			bias-pull-up;
+		};
+
+		perst-n-pins {
+			pins = "gpio151";
+			function = "gpio";
+			drive-strength = <2>;
+			bias-disable;
+		};
+
+		wake-n-pins {
+			pins = "gpio148";
+			function = "gpio";
+			drive-strength = <2>;
+			bias-pull-up;
+		};
+	};
+
+	pcie4_default: pcie4-default-state {
+		clkreq-n-pins {
+			pins = "gpio140";
+			function = "pcie4_clkreq";
+			drive-strength = <2>;
+			bias-pull-up;
+		};
+
+		perst-n-pins {
+			pins = "gpio141";
+			function = "gpio";
+			drive-strength = <2>;
+			bias-disable;
+		};
+
+		wake-n-pins {
+			pins = "gpio139";
+			function = "gpio";
+			drive-strength = <2>;
+			bias-pull-up;
+		};
+	};
+
+	uart2_default: uart2-default-state {
+		cts-pins {
+			pins = "gpio121";
+			function = "qup2";
+			bias-bus-hold;
+		};
+
+		rts-pins {
+			pins = "gpio122";
+			function = "qup2";
+			drive-strength = <2>;
+			bias-disable;
+		};
+
+		rx-pins {
+			pins = "gpio124";
+			function = "qup2";
+			bias-pull-up;
+		};
+
+		tx-pins {
+			pins = "gpio123";
+			function = "qup2";
+			drive-strength = <2>;
+			bias-disable;
+		};
+	};
+
+	usb0_sbu_default: usb0-sbu-state {
+		oe-n-pins {
+			pins = "gpio101";
+			function = "gpio";
+			bias-disable;
+			drive-strength = <16>;
+			output-high;
+		};
+
+		sel-pins {
+			pins = "gpio164";
+			function = "gpio";
+			bias-disable;
+			drive-strength = <16>;
+		};
+	};
+
+	usb1_sbu_default: usb1-sbu-state {
+		oe-n-pins {
+			pins = "gpio48";
+			function = "gpio";
+			bias-disable;
+			drive-strength = <16>;
+			output-high;
+		};
+
+		sel-pins {
+			pins = "gpio47";
+			function = "gpio";
+			bias-disable;
+			drive-strength = <16>;
+		};
+	};
+
+	usb2_en_state: usb2-en-state {
+		/* TS3USB221A USB2.0 mux select */
+		pins = "gpio24";
+		function = "gpio";
+		drive-strength = <2>;
+		bias-disable;
+		output-low;
+	};
+
+	wcd_default: wcd-default-state {
+		reset-pins {
+			pins = "gpio106";
+			function = "gpio";
+			bias-disable;
+		};
+	};
+
+	wlan_en: wlan-en-state {
+		pins = "gpio134";
+		function = "gpio";
+		drive-strength = <8>;
+		bias-pull-down;
+	};
+};
diff --git a/dts/upstream/src/arm64/qcom/sc8280xp.dtsi b/dts/upstream/src/arm64/qcom/sc8280xp.dtsi
index ef06d1ac084..01501acb179 100644
--- a/dts/upstream/src/arm64/qcom/sc8280xp.dtsi
+++ b/dts/upstream/src/arm64/qcom/sc8280xp.dtsi
@@ -2743,7 +2743,7 @@
 
 		remoteproc_adsp: remoteproc@3000000 {
 			compatible = "qcom,sc8280xp-adsp-pas";
-			reg = <0 0x03000000 0 0x100>;
+			reg = <0 0x03000000 0 0x10000>;
 
 			interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
 					      <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
@@ -3536,6 +3536,8 @@
 					    "usb2-2",
 					    "usb2-3";
 				dr_mode = "host";
+				snps,dis-u1-entry-quirk;
+				snps,dis-u2-entry-quirk;
 			};
 		};
 
@@ -3593,6 +3595,8 @@
 				iommus = <&apps_smmu 0x820 0x0>;
 				phys = <&usb_0_hsphy>, <&usb_0_qmpphy QMP_USB43DP_USB3_PHY>;
 				phy-names = "usb2-phy", "usb3-phy";
+				snps,dis-u1-entry-quirk;
+				snps,dis-u2-entry-quirk;
 
 				ports {
 					#address-cells = <1>;
@@ -3670,6 +3674,8 @@
 				iommus = <&apps_smmu 0x860 0x0>;
 				phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>;
 				phy-names = "usb2-phy", "usb3-phy";
+				snps,dis-u1-entry-quirk;
+				snps,dis-u2-entry-quirk;
 
 				ports {
 					#address-cells = <1>;
@@ -3900,26 +3906,26 @@
 				    "vfe3",
 				    "csid3";
 
-			interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 478 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 479 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 758 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 759 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 760 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 761 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 762 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 764 IRQ_TYPE_LEVEL_HIGH>;
+			interrupts = <GIC_SPI 359 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 360 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 448 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 464 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 465 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 466 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 467 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 468 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 469 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 477 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 478 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 479 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 640 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 641 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 758 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 759 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 760 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 761 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 762 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 764 IRQ_TYPE_EDGE_RISING>;
 			interrupt-names = "csid1_lite",
 					  "vfe_lite1",
 					  "csiphy3",
@@ -5254,7 +5260,7 @@
 
 		remoteproc_nsp0: remoteproc@1b300000 {
 			compatible = "qcom,sc8280xp-nsp0-pas";
-			reg = <0 0x1b300000 0 0x100>;
+			reg = <0 0x1b300000 0 0x10000>;
 
 			interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
 					      <&smp2p_nsp0_in 0 IRQ_TYPE_EDGE_RISING>,
@@ -5385,7 +5391,7 @@
 
 		remoteproc_nsp1: remoteproc@21300000 {
 			compatible = "qcom,sc8280xp-nsp1-pas";
-			reg = <0 0x21300000 0 0x100>;
+			reg = <0 0x21300000 0 0x10000>;
 
 			interrupts-extended = <&intc GIC_SPI 887 IRQ_TYPE_EDGE_RISING>,
 					      <&smp2p_nsp1_in 0 IRQ_TYPE_EDGE_RISING>,
diff --git a/dts/upstream/src/arm64/qcom/sdm450-lenovo-tbx605f.dts b/dts/upstream/src/arm64/qcom/sdm450-lenovo-tbx605f.dts
index c509bbfe5d3..735a21df8cc 100644
--- a/dts/upstream/src/arm64/qcom/sdm450-lenovo-tbx605f.dts
+++ b/dts/upstream/src/arm64/qcom/sdm450-lenovo-tbx605f.dts
@@ -46,6 +46,18 @@
 		};
 	};
 
+	backlight: gpio-backlight {
+		compatible = "gpio-backlight";
+
+		gpios = <&tlmm 16 GPIO_ACTIVE_HIGH>;
+
+		default-on;
+
+		pinctrl-names = "default";
+		pinctrl-0 = <&backlight_enable_active>;
+		pinctrl-1 = <&backlight_enable_sleep>;
+	};
+
 	gpio-keys {
 		compatible = "gpio-keys";
 		key-volume-up {
@@ -63,6 +75,49 @@
 	};
 };
 
+&mdss {
+	status = "okay";
+};
+
+&mdss_dsi0 {
+	vdda-supply = <&pm8953_s3>;
+	vddio-supply = <&pm8953_l6>;
+
+	status = "okay";
+
+	panel@0 {
+		compatible = "boe,tv101wum-ll2";
+		reg = <0>;
+
+		vsp-supply = <&lab>;
+		vsn-supply = <&ibb>;
+		reset-gpios = <&tlmm 61 GPIO_ACTIVE_LOW>;
+
+		backlight = <&backlight>;
+
+		pinctrl-names = "default";
+		pinctrl-0 = <&panel_reset_active>;
+		pinctrl-1 = <&panel_reset_sleep>;
+
+		port {
+			panel_in: endpoint {
+				remote-endpoint = <&mdss_dsi0_out>;
+			};
+		};
+	};
+};
+
+&mdss_dsi0_out {
+	remote-endpoint = <&panel_in>;
+	data-lanes = <0 1 2 3>;
+};
+
+&mdss_dsi0_phy {
+	vcca-supply = <&pm8953_l3>;
+
+	status = "okay";
+};
+
 &hsusb_phy {
 	vdd-supply = <&pm8953_l3>;
 	vdda-pll-supply = <&pm8953_l7>;
@@ -90,6 +145,18 @@
 	};
 };
 
+&ibb {
+	regulator-min-microvolt = <4600000>;
+	regulator-max-microvolt = <6000000>;
+	qcom,discharge-resistor-kohms = <32>;
+};
+
+&lab {
+	regulator-min-microvolt = <4600000>;
+	regulator-max-microvolt = <6000000>;
+	qcom,soft-start-us = <800>;
+};
+
 &pm8953_resin {
 	linux,code = <KEY_VOLUMEDOWN>;
 	status = "okay";
@@ -237,6 +304,36 @@
 &tlmm {
 	gpio-reserved-ranges = <0 4>, <135 4>;
 
+	backlight_enable_active: backlight-enable-active-state {
+		pins = "gpio16";
+		function = "gpio";
+		drive-strength = <8>;
+		bias-disable;
+		output-high;
+	};
+
+	backlight_enable_sleep: backlight-enable-sleep-state {
+		pins = "gpio16";
+		function = "gpio";
+		drive-strength = <2>;
+		bias-pull-down;
+	};
+
+	panel_reset_active: panel-reset-active-state {
+		pins = "gpio61";
+		function = "gpio";
+		drive-strength = <8>;
+		bias-disable;
+		output-high;
+	};
+
+	panel_reset_sleep: panel-reset-sleep-state {
+		pins = "gpio61";
+		function = "gpio";
+		drive-strength = <2>;
+		bias-pull-down;
+	};
+
 	ts_int_active: ts-int-active-state {
 		pins = "gpio65";
 		function = "gpio";
diff --git a/dts/upstream/src/arm64/qcom/sdm630.dtsi b/dts/upstream/src/arm64/qcom/sdm630.dtsi
index 19420cfdadf..a2c079bac1a 100644
--- a/dts/upstream/src/arm64/qcom/sdm630.dtsi
+++ b/dts/upstream/src/arm64/qcom/sdm630.dtsi
@@ -1300,6 +1300,8 @@
 				snps,dis_u2_susphy_quirk;
 				snps,dis_enblslpm_quirk;
 				snps,parkmode-disable-ss-quirk;
+				snps,dis-u1-entry-quirk;
+				snps,dis-u2-entry-quirk;
 
 				phys = <&qusb2phy0>, <&usb3_qmpphy>;
 				phy-names = "usb2-phy", "usb3-phy";
@@ -1505,6 +1507,8 @@
 				interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
 				snps,dis_u2_susphy_quirk;
 				snps,dis_enblslpm_quirk;
+				snps,dis-u1-entry-quirk;
+				snps,dis-u2-entry-quirk;
 
 				/* This is the HS-only host */
 				maximum-speed = "high-speed";
diff --git a/dts/upstream/src/arm64/qcom/sdm670-google-sargo.dts b/dts/upstream/src/arm64/qcom/sdm670-google-sargo.dts
index 176b0119fe6..74b5d9c68eb 100644
--- a/dts/upstream/src/arm64/qcom/sdm670-google-sargo.dts
+++ b/dts/upstream/src/arm64/qcom/sdm670-google-sargo.dts
@@ -10,6 +10,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 #include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
 #include <dt-bindings/power/qcom-rpmpd.h>
 #include "sdm670.dtsi"
@@ -49,20 +50,6 @@
 		};
 	};
 
-	clocks {
-		sleep_clk: sleep-clk {
-			compatible = "fixed-clock";
-			#clock-cells = <0>;
-			clock-frequency = <32764>;
-		};
-
-		xo_board: xo-board {
-			compatible = "fixed-clock";
-			#clock-cells = <0>;
-			clock-frequency = <38400000>;
-		};
-	};
-
 	gpio-keys {
 		compatible = "gpio-keys";
 		autorepeat;
@@ -407,6 +394,15 @@
 	status = "okay";
 };
 
+&gpu {
+	status = "okay";
+
+	zap-shader {
+		memory-region = <&gpu_mem>;
+		firmware-name = "qcom/sdm670/sargo/a615_zap.mbn";
+	};
+};
+
 &i2c9 {
 	clock-frequency = <100000>;
 	status = "okay";
@@ -482,6 +478,19 @@
 	status = "okay";
 };
 
+&pm660l_flash {
+	status = "okay";
+
+	led-0 {
+		function = LED_FUNCTION_FLASH;
+		color = <LED_COLOR_ID_WHITE>;
+		led-sources = <1>, <2>;
+		led-max-microamp = <500000>;
+		flash-max-microamp = <1500000>;
+		flash-max-timeout-us = <1280000>;
+	};
+};
+
 &pm660l_gpios {
 	vol_up_pin: vol-up-state {
 		pins = "gpio7";
diff --git a/dts/upstream/src/arm64/qcom/sdm670.dtsi b/dts/upstream/src/arm64/qcom/sdm670.dtsi
index c93dd06c0b7..279e62ec543 100644
--- a/dts/upstream/src/arm64/qcom/sdm670.dtsi
+++ b/dts/upstream/src/arm64/qcom/sdm670.dtsi
@@ -8,6 +8,7 @@
 
 #include <dt-bindings/clock/qcom,dispcc-sdm845.h>
 #include <dt-bindings/clock/qcom,gcc-sdm845.h>
+#include <dt-bindings/clock/qcom,gpucc-sdm845.h>
 #include <dt-bindings/clock/qcom,rpmh.h>
 #include <dt-bindings/dma/qcom-gpi.h>
 #include <dt-bindings/gpio/gpio.h>
@@ -28,6 +29,20 @@
 
 	chosen { };
 
+	clocks {
+		sleep_clk: sleep-clk {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <32764>;
+		};
+
+		xo_board: xo-board {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <38400000>;
+		};
+	};
+
 	cpus {
 		#address-cells = <2>;
 		#size-cells = <0>;
@@ -617,6 +632,11 @@
 			#address-cells = <1>;
 			#size-cells = <1>;
 
+			gpu_speed_bin: gpu_speed_bin@1a2 {
+				reg = <0x1a2 0x2>;
+				bits = <5 8>;
+			};
+
 			qusb2_hstx_trim: hstx-trim@1eb {
 				reg = <0x1eb 0x1>;
 				bits = <1 4>;
@@ -1299,6 +1319,180 @@
 			};
 		};
 
+		gpu: gpu@5000000 {
+			compatible = "qcom,adreno-615.0", "qcom,adreno";
+
+			reg = <0 0x05000000 0 0x40000>, <0 0x0509e000 0 0x10>;
+			reg-names = "kgsl_3d0_reg_memory", "cx_mem";
+
+			/*
+			 * Look ma, no clocks! The GPU clocks and power are
+			 * controlled entirely by the GMU
+			 */
+
+			interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
+
+			iommus = <&adreno_smmu 0>;
+
+			operating-points-v2 = <&gpu_opp_table>;
+
+			qcom,gmu = <&gmu>;
+
+			interconnects = <&mem_noc MASTER_GRAPHICS_3D 0 &mem_noc SLAVE_EBI_CH0 0>;
+			interconnect-names = "gfx-mem";
+
+			nvmem-cells = <&gpu_speed_bin>;
+			nvmem-cell-names = "speed_bin";
+
+			status = "disabled";
+
+			gpu_opp_table: opp-table {
+				compatible = "operating-points-v2";
+
+				opp-780000000 {
+					opp-hz = /bits/ 64 <780000000>;
+					opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
+					opp-peak-kBps = <7216000>;
+					opp-supported-hw = <0x8>;
+				};
+
+				opp-750000000 {
+					opp-hz = /bits/ 64 <750000000>;
+					opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
+					opp-peak-kBps = <7216000>;
+					opp-supported-hw = <0x8>;
+				};
+
+				opp-700000000 {
+					opp-hz = /bits/ 64 <700000000>;
+					opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
+					opp-peak-kBps = <7216000>;
+					opp-supported-hw = <0x4>;
+				};
+
+				opp-650000000 {
+					opp-hz = /bits/ 64 <650000000>;
+					opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
+					opp-peak-kBps = <7216000>;
+					opp-supported-hw = <0xc>;
+				};
+
+				opp-565000000 {
+					opp-hz = /bits/ 64 <565000000>;
+					opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
+					opp-peak-kBps = <7216000>;
+					opp-supported-hw = <0xc>;
+				};
+
+				opp-504000000 {
+					opp-hz = /bits/ 64 <504000000>;
+					opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
+					opp-peak-kBps = <7216000>;
+					opp-supported-hw = <0x2>;
+				};
+
+				opp-430000000 {
+					opp-hz = /bits/ 64 <430000000>;
+					opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
+					opp-peak-kBps = <7216000>;
+					opp-supported-hw = <0xf>;
+				};
+
+				opp-355000000 {
+					opp-hz = /bits/ 64 <355000000>;
+					opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
+					opp-peak-kBps = <6220000>;
+					opp-supported-hw = <0xf>;
+				};
+
+				opp-267000000 {
+					opp-hz = /bits/ 64 <267000000>;
+					opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
+					opp-peak-kBps = <4068000>;
+					opp-supported-hw = <0xf>;
+				};
+
+				opp-180000000 {
+					opp-hz = /bits/ 64 <180000000>;
+					opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
+					opp-peak-kBps = <1804000>;
+					opp-supported-hw = <0xf>;
+				};
+			};
+		};
+
+		adreno_smmu: iommu@5040000 {
+			compatible = "qcom,sdm670-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2";
+			reg = <0 0x05040000 0 0x10000>;
+			#iommu-cells = <1>;
+			#global-interrupts = <2>;
+			interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 366 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 367 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 368 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 369 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 370 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 371 IRQ_TYPE_EDGE_RISING>;
+			clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
+				 <&gcc GCC_GPU_CFG_AHB_CLK>;
+			clock-names = "bus", "iface";
+
+			power-domains = <&gpucc GPU_CX_GDSC>;
+		};
+
+		gmu: gmu@506a000 {
+			compatible = "qcom,adreno-gmu-615.0", "qcom,adreno-gmu";
+
+			reg = <0 0x0506a000 0 0x30000>,
+			      <0 0x0b280000 0 0x10000>,
+			      <0 0x0b480000 0 0x10000>;
+			reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq";
+
+			interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "hfi", "gmu";
+
+			clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
+				 <&gpucc GPU_CC_CXO_CLK>,
+				 <&gcc GCC_DDRSS_GPU_AXI_CLK>,
+				 <&gcc GCC_GPU_MEMNOC_GFX_CLK>;
+			clock-names = "gmu", "cxo", "axi", "memnoc";
+
+			power-domains = <&gpucc GPU_CX_GDSC>,
+					<&gpucc GPU_GX_GDSC>;
+			power-domain-names = "cx", "gx";
+
+			iommus = <&adreno_smmu 5>;
+
+			operating-points-v2 = <&gmu_opp_table>;
+
+			gmu_opp_table: opp-table {
+				compatible = "operating-points-v2";
+
+				opp-200000000 {
+					opp-hz = /bits/ 64 <200000000>;
+					opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
+				};
+			};
+		};
+
+		gpucc: clock-controller@5090000 {
+			compatible = "qcom,sdm845-gpucc";
+			reg = <0 0x05090000 0 0x9000>;
+			#clock-cells = <1>;
+			#reset-cells = <1>;
+			#power-domain-cells = <1>;
+			clocks = <&rpmhcc RPMH_CXO_CLK>,
+				 <&gcc GCC_GPU_GPLL0_CLK_SRC>,
+				 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
+			clock-names = "bi_tcxo",
+				      "gcc_gpu_gpll0_clk_src",
+				      "gcc_gpu_gpll0_div_clk_src";
+		};
+
 		usb_1_hsphy: phy@88e2000 {
 			compatible = "qcom,sdm670-qusb2-phy", "qcom,qusb2-v2-phy";
 			reg = <0 0x088e2000 0 0x400>;
@@ -1400,6 +1594,16 @@
 			#interrupt-cells = <4>;
 		};
 
+		camcc: clock-controller@ad00000 {
+			compatible = "qcom,sdm670-camcc", "qcom,sdm845-camcc";
+			reg = <0 0x0ad00000 0 0x10000>;
+			clocks = <&rpmhcc RPMH_CXO_CLK>;
+			clock-names = "bi_tcxo";
+			#clock-cells = <1>;
+			#reset-cells = <1>;
+			#power-domain-cells = <1>;
+		};
+
 		mdss: display-subsystem@ae00000 {
 			compatible = "qcom,sdm670-mdss";
 			reg = <0 0x0ae00000 0 0x1000>;
diff --git a/dts/upstream/src/arm64/qcom/sdm845-db845c-navigation-mezzanine.dtso b/dts/upstream/src/arm64/qcom/sdm845-db845c-navigation-mezzanine.dtso
index 0a87df806ca..59970082da4 100644
--- a/dts/upstream/src/arm64/qcom/sdm845-db845c-navigation-mezzanine.dtso
+++ b/dts/upstream/src/arm64/qcom/sdm845-db845c-navigation-mezzanine.dtso
@@ -79,45 +79,3 @@
 		};
 	};
 };
-
-&cci_i2c1 {
-	#address-cells = <1>;
-	#size-cells = <0>;
-
-	camera@60 {
-		compatible = "ovti,ov7251";
-
-		/* I2C address as per ov7251.txt linux documentation */
-		reg = <0x60>;
-
-		/* CAM3_RST_N */
-		enable-gpios = <&tlmm 21 GPIO_ACTIVE_HIGH>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&cam3_default>;
-
-		clocks = <&clock_camcc CAM_CC_MCLK3_CLK>;
-		clock-names = "xclk";
-		clock-frequency = <24000000>;
-
-		/*
-		 * The &vreg_s4a_1p8 trace always powered on.
-		 *
-		 * The 2.8V vdda-supply regulator is enabled when the
-		 * vreg_s4a_1p8 trace is pulled high.
-		 * It too is represented by a fixed regulator.
-		 *
-		 * No 1.2V vddd-supply regulator is used.
-		 */
-		vdddo-supply = <&vreg_lvs1a_1p8>;
-		vdda-supply = <&cam3_avdd_2v8>;
-
-		status = "disabled";
-
-		port {
-			ov7251_ep: endpoint {
-				data-lanes = <0 1>;
-/*				remote-endpoint = <&csiphy3_ep>; */
-			};
-		};
-	};
-};
diff --git a/dts/upstream/src/arm64/qcom/sdm845-shift-axolotl.dts b/dts/upstream/src/arm64/qcom/sdm845-shift-axolotl.dts
index 486ce175e6b..ddb82ecb0a9 100644
--- a/dts/upstream/src/arm64/qcom/sdm845-shift-axolotl.dts
+++ b/dts/upstream/src/arm64/qcom/sdm845-shift-axolotl.dts
@@ -452,7 +452,6 @@
 		irq-gpio = <&tlmm 125 GPIO_TRANSITORY>;
 		touchscreen-size-x = <1080>;
 		touchscreen-size-y = <2160>;
-		focaltech,max-touch-number = <5>;
 	};
 };
 
diff --git a/dts/upstream/src/arm64/qcom/sdm845.dtsi b/dts/upstream/src/arm64/qcom/sdm845.dtsi
index 1ed794638a7..d0314cdf0b9 100644
--- a/dts/upstream/src/arm64/qcom/sdm845.dtsi
+++ b/dts/upstream/src/arm64/qcom/sdm845.dtsi
@@ -4139,6 +4139,8 @@
 				snps,dis_u2_susphy_quirk;
 				snps,dis_enblslpm_quirk;
 				snps,parkmode-disable-ss-quirk;
+				snps,dis-u1-entry-quirk;
+				snps,dis-u2-entry-quirk;
 				phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>;
 				phy-names = "usb2-phy", "usb3-phy";
 
@@ -4215,6 +4217,8 @@
 				snps,dis_u2_susphy_quirk;
 				snps,dis_enblslpm_quirk;
 				snps,parkmode-disable-ss-quirk;
+				snps,dis-u1-entry-quirk;
+				snps,dis-u2-entry-quirk;
 				phys = <&usb_2_hsphy>, <&usb_2_qmpphy>;
 				phy-names = "usb2-phy", "usb3-phy";
 			};
@@ -4326,16 +4330,16 @@
 				"vfe1",
 				"vfe_lite";
 
-			interrupts = <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>,
-				<GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>,
-				<GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>,
-				<GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>,
-				<GIC_SPI 478 IRQ_TYPE_LEVEL_HIGH>,
-				<GIC_SPI 479 IRQ_TYPE_LEVEL_HIGH>,
-				<GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>,
-				<GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>,
-				<GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>,
-				<GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>;
+			interrupts = <GIC_SPI 464 IRQ_TYPE_EDGE_RISING>,
+				<GIC_SPI 466 IRQ_TYPE_EDGE_RISING>,
+				<GIC_SPI 468 IRQ_TYPE_EDGE_RISING>,
+				<GIC_SPI 477 IRQ_TYPE_EDGE_RISING>,
+				<GIC_SPI 478 IRQ_TYPE_EDGE_RISING>,
+				<GIC_SPI 479 IRQ_TYPE_EDGE_RISING>,
+				<GIC_SPI 448 IRQ_TYPE_EDGE_RISING>,
+				<GIC_SPI 465 IRQ_TYPE_EDGE_RISING>,
+				<GIC_SPI 467 IRQ_TYPE_EDGE_RISING>,
+				<GIC_SPI 469 IRQ_TYPE_EDGE_RISING>;
 			interrupt-names = "csid0",
 				"csid1",
 				"csid2",
@@ -5159,7 +5163,6 @@
 				     <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>;
-			dma-coherent;
 		};
 
 		anoc_1_tbu: tbu@150c5000 {
diff --git a/dts/upstream/src/arm64/qcom/sdx75.dtsi b/dts/upstream/src/arm64/qcom/sdx75.dtsi
index 5f7e59ecf1c..b0a8a0fe5f3 100644
--- a/dts/upstream/src/arm64/qcom/sdx75.dtsi
+++ b/dts/upstream/src/arm64/qcom/sdx75.dtsi
@@ -34,7 +34,7 @@
 
 		sleep_clk: sleep-clk {
 			compatible = "fixed-clock";
-			clock-frequency = <32000>;
+			clock-frequency = <32764>;
 			#clock-cells = <0>;
 		};
 	};
@@ -893,7 +893,7 @@
 
 		remoteproc_mpss: remoteproc@4080000 {
 			compatible = "qcom,sdx75-mpss-pas";
-			reg = <0 0x04080000 0 0x4040>;
+			reg = <0 0x04080000 0 0x10000>;
 
 			interrupts-extended = <&intc GIC_SPI 250 IRQ_TYPE_EDGE_RISING>,
 					      <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>,
@@ -1037,6 +1037,8 @@
 				iommus = <&apps_smmu 0x80 0x0>;
 				snps,dis_u2_susphy_quirk;
 				snps,dis_enblslpm_quirk;
+				snps,dis-u1-entry-quirk;
+				snps,dis-u2-entry-quirk;
 				phys = <&usb_hsphy>,
 				       <&usb_qmpphy>;
 				phy-names = "usb2-phy",
diff --git a/dts/upstream/src/arm64/qcom/sm4250.dtsi b/dts/upstream/src/arm64/qcom/sm4250.dtsi
index a0ed61925e1..cd8c8e59976 100644
--- a/dts/upstream/src/arm64/qcom/sm4250.dtsi
+++ b/dts/upstream/src/arm64/qcom/sm4250.dtsi
@@ -36,3 +36,42 @@
 &cpu7 {
 	compatible = "qcom,kryo240";
 };
+
+&lpass_tlmm {
+	compatible = "qcom,sm4250-lpass-lpi-pinctrl";
+	gpio-ranges = <&lpass_tlmm 0 0 27>;
+
+	lpi_i2s2_active: lpi-i2s2-active-state {
+		sck-pins {
+			pins = "gpio10";
+			function = "i2s2_clk";
+			bias-disable;
+			drive-strength = <8>;
+			output-high;
+		};
+
+		ws-pins {
+			pins = "gpio11";
+			function = "i2s2_ws";
+			bias-disable;
+			drive-strength = <8>;
+			output-high;
+		};
+
+		data-pins {
+			pins = "gpio12";
+			function = "i2s2_data";
+			bias-disable;
+			drive-strength = <8>;
+			output-high;
+		};
+
+		ext-mclk1-pins {
+			pins = "gpio18";
+			function = "ext_mclk1_a";
+			bias-disable;
+			drive-strength = <16>;
+			output-high;
+		};
+	};
+};
diff --git a/dts/upstream/src/arm64/qcom/sm4450.dtsi b/dts/upstream/src/arm64/qcom/sm4450.dtsi
index a0de5fe16fa..27453771aa6 100644
--- a/dts/upstream/src/arm64/qcom/sm4450.dtsi
+++ b/dts/upstream/src/arm64/qcom/sm4450.dtsi
@@ -29,7 +29,7 @@
 
 		sleep_clk: sleep-clk {
 			compatible = "fixed-clock";
-			clock-frequency = <32000>;
+			clock-frequency = <32764>;
 			#clock-cells = <0>;
 		};
 
diff --git a/dts/upstream/src/arm64/qcom/sm6115.dtsi b/dts/upstream/src/arm64/qcom/sm6115.dtsi
index 9b23534c456..94c081bf7a8 100644
--- a/dts/upstream/src/arm64/qcom/sm6115.dtsi
+++ b/dts/upstream/src/arm64/qcom/sm6115.dtsi
@@ -14,6 +14,9 @@
 #include <dt-bindings/interconnect/qcom,sm6115.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/power/qcom-rpmpd.h>
+#include <dt-bindings/soc/qcom,apr.h>
+#include <dt-bindings/sound/qcom,q6asm.h>
+#include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h>
 #include <dt-bindings/thermal/thermal.h>
 
 / {
@@ -808,6 +811,20 @@
 			};
 		};
 
+		lpass_tlmm: pinctrl@a7c0000 {
+			compatible = "qcom,sm6115-lpass-lpi-pinctrl";
+			reg = <0x0 0x0a7c0000 0x0 0x20000>,
+			      <0x0 0x0a950000 0x0 0x10000>;
+
+			clocks = <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
+			clock-names = "audio";
+
+			gpio-controller;
+			#gpio-cells = <2>;
+			gpio-ranges = <&lpass_tlmm 0 0 19>;
+
+		};
+
 		gcc: clock-controller@1400000 {
 			compatible = "qcom,gcc-sm6115";
 			reg = <0x0 0x01400000 0x0 0x1f0000>;
@@ -2027,7 +2044,7 @@
 
 		remoteproc_mpss: remoteproc@6080000 {
 			compatible = "qcom,sm6115-mpss-pas";
-			reg = <0x0 0x06080000 0x0 0x100>;
+			reg = <0x0 0x06080000 0x0 0x10000>;
 
 			interrupts-extended = <&intc GIC_SPI 307 IRQ_TYPE_EDGE_RISING>,
 					      <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
@@ -2670,9 +2687,9 @@
 			};
 		};
 
-		remoteproc_adsp: remoteproc@ab00000 {
+		remoteproc_adsp: remoteproc@a400000 {
 			compatible = "qcom,sm6115-adsp-pas";
-			reg = <0x0 0x0ab00000 0x0 0x100>;
+			reg = <0x0 0x0a400000 0x0 0x4040>;
 
 			interrupts-extended = <&intc GIC_SPI 282 IRQ_TYPE_EDGE_RISING>,
 					      <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
@@ -2701,6 +2718,76 @@
 				qcom,remote-pid = <2>;
 				mboxes = <&apcs_glb 8>;
 
+				apr {
+					compatible = "qcom,apr-v2";
+					qcom,glink-channels = "apr_audio_svc";
+					qcom,domain = <APR_DOMAIN_ADSP>;
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					service@3 {
+						reg = <APR_SVC_ADSP_CORE>;
+						compatible = "qcom,q6core";
+						qcom,protection-domain = "avs/audio",
+									 "msm/adsp/audio_pd";
+					};
+
+					q6afe: service@4 {
+						compatible = "qcom,q6afe";
+						reg = <APR_SVC_AFE>;
+						qcom,protection-domain = "avs/audio",
+									 "msm/adsp/audio_pd";
+						q6afedai: dais {
+							compatible = "qcom,q6afe-dais";
+							#address-cells = <1>;
+							#size-cells = <0>;
+							#sound-dai-cells = <1>;
+						};
+
+						q6afecc: clock-controller {
+							compatible = "qcom,q6afe-clocks";
+							#clock-cells = <2>;
+						};
+					};
+
+					q6asm: service@7 {
+						compatible = "qcom,q6asm";
+						reg = <APR_SVC_ASM>;
+						qcom,protection-domain = "avs/audio",
+									 "msm/adsp/audio_pd";
+						q6asmdai: dais {
+							compatible = "qcom,q6asm-dais";
+							#address-cells = <1>;
+							#size-cells = <0>;
+							#sound-dai-cells = <1>;
+							iommus = <&apps_smmu 0x1c1 0x0>;
+
+							dai@0 {
+								reg = <MSM_FRONTEND_DAI_MULTIMEDIA1>;
+							};
+
+							dai@1 {
+								reg = <MSM_FRONTEND_DAI_MULTIMEDIA2>;
+							};
+
+							dai@2 {
+								reg = <MSM_FRONTEND_DAI_MULTIMEDIA3>;
+							};
+						};
+					};
+
+					q6adm: service@8 {
+						compatible = "qcom,q6adm";
+						reg = <APR_SVC_ADM>;
+						qcom,protection-domain = "avs/audio",
+									 "msm/adsp/audio_pd";
+						q6routing: routing {
+							compatible = "qcom,q6adm-routing";
+							#sound-dai-cells = <0>;
+						};
+					};
+				};
+
 				fastrpc {
 					compatible = "qcom,fastrpc";
 					qcom,glink-channels = "fastrpcglink-apps-dsp";
@@ -2744,7 +2831,7 @@
 
 		remoteproc_cdsp: remoteproc@b300000 {
 			compatible = "qcom,sm6115-cdsp-pas";
-			reg = <0x0 0x0b300000 0x0 0x100000>;
+			reg = <0x0 0x0b300000 0x0 0x4040>;
 
 			interrupts-extended = <&intc GIC_SPI 265 IRQ_TYPE_EDGE_RISING>,
 					      <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
diff --git a/dts/upstream/src/arm64/qcom/sm6125.dtsi b/dts/upstream/src/arm64/qcom/sm6125.dtsi
index 17d528d6393..350d807a622 100644
--- a/dts/upstream/src/arm64/qcom/sm6125.dtsi
+++ b/dts/upstream/src/arm64/qcom/sm6125.dtsi
@@ -28,7 +28,7 @@
 		sleep_clk: sleep-clk {
 			compatible = "fixed-clock";
 			#clock-cells = <0>;
-			clock-frequency = <32000>;
+			clock-frequency = <32764>;
 			clock-output-names = "sleep_clk";
 		};
 	};
@@ -1209,6 +1209,8 @@
 				phy-names = "usb2-phy";
 				snps,dis_u2_susphy_quirk;
 				snps,dis_enblslpm_quirk;
+				snps,dis-u1-entry-quirk;
+				snps,dis-u2-entry-quirk;
 				maximum-speed = "high-speed";
 				dr_mode = "peripheral";
 			};
diff --git a/dts/upstream/src/arm64/qcom/sm6350.dtsi b/dts/upstream/src/arm64/qcom/sm6350.dtsi
index 8d697280249..00ad1d09a19 100644
--- a/dts/upstream/src/arm64/qcom/sm6350.dtsi
+++ b/dts/upstream/src/arm64/qcom/sm6350.dtsi
@@ -936,7 +936,7 @@
 				power-domains = <&rpmhpd SM6350_CX>;
 				operating-points-v2 = <&qup_opp_table>;
 				interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
-						<&aggre1_noc MASTER_QUP_0 0 &clk_virt SLAVE_EBI_CH0 0>;
+						<&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>;
 				interconnect-names = "qup-core", "qup-config";
 				status = "disabled";
 			};
@@ -1283,7 +1283,7 @@
 
 		adsp: remoteproc@3000000 {
 			compatible = "qcom,sm6350-adsp-pas";
-			reg = <0 0x03000000 0 0x100>;
+			reg = <0x0 0x03000000 0x0 0x10000>;
 
 			interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>,
 					      <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
@@ -1503,7 +1503,7 @@
 
 		mpss: remoteproc@4080000 {
 			compatible = "qcom,sm6350-mpss-pas";
-			reg = <0x0 0x04080000 0x0 0x4040>;
+			reg = <0x0 0x04080000 0x0 0x10000>;
 
 			interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_EDGE_RISING>,
 					      <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
@@ -1924,6 +1924,8 @@
 				snps,has-lpm-erratum;
 				snps,hird-threshold = /bits/ 8 <0x10>;
 				snps,parkmode-disable-ss-quirk;
+				snps,dis-u1-entry-quirk;
+				snps,dis-u2-entry-quirk;
 				phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>;
 				phy-names = "usb2-phy", "usb3-phy";
 				usb-role-switch;
diff --git a/dts/upstream/src/arm64/qcom/sm6375.dtsi b/dts/upstream/src/arm64/qcom/sm6375.dtsi
index e0b1c54e98c..0faa3a40ff8 100644
--- a/dts/upstream/src/arm64/qcom/sm6375.dtsi
+++ b/dts/upstream/src/arm64/qcom/sm6375.dtsi
@@ -29,7 +29,7 @@
 
 		sleep_clk: sleep-clk {
 			compatible = "fixed-clock";
-			clock-frequency = <32000>;
+			clock-frequency = <32764>;
 			#clock-cells = <0>;
 		};
 	};
@@ -1516,9 +1516,9 @@
 			#power-domain-cells = <1>;
 		};
 
-		remoteproc_mss: remoteproc@6000000 {
+		remoteproc_mss: remoteproc@6080000 {
 			compatible = "qcom,sm6375-mpss-pas";
-			reg = <0 0x06000000 0 0x4040>;
+			reg = <0x0 0x06080000 0x0 0x10000>;
 
 			interrupts-extended = <&intc GIC_SPI 307 IRQ_TYPE_EDGE_RISING>,
 					      <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>,
@@ -1559,7 +1559,7 @@
 
 		remoteproc_adsp: remoteproc@a400000 {
 			compatible = "qcom,sm6375-adsp-pas";
-			reg = <0 0x0a400000 0 0x100>;
+			reg = <0 0x0a400000 0 0x10000>;
 
 			interrupts-extended = <&intc GIC_SPI 282 IRQ_TYPE_EDGE_RISING>,
 					      <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
@@ -1595,9 +1595,9 @@
 			};
 		};
 
-		remoteproc_cdsp: remoteproc@b000000 {
+		remoteproc_cdsp: remoteproc@b300000 {
 			compatible = "qcom,sm6375-cdsp-pas";
-			reg = <0x0 0x0b000000 0x0 0x100000>;
+			reg = <0x0 0x0b300000 0x0 0x10000>;
 
 			interrupts-extended = <&intc GIC_SPI 265 IRQ_TYPE_EDGE_RISING>,
 					      <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>,
diff --git a/dts/upstream/src/arm64/qcom/sm7225-fairphone-fp4.dts b/dts/upstream/src/arm64/qcom/sm7225-fairphone-fp4.dts
index 2ee2561b57b..52b16a4fdc4 100644
--- a/dts/upstream/src/arm64/qcom/sm7225-fairphone-fp4.dts
+++ b/dts/upstream/src/arm64/qcom/sm7225-fairphone-fp4.dts
@@ -32,7 +32,7 @@
 	chassis-type = "handset";
 
 	/* required for bootloader to select correct board */
-	qcom,msm-id = <434 0x10000>, <459 0x10000>;
+	qcom,msm-id = <459 0x10000>;
 	qcom,board-id = <8 32>;
 
 	aliases {
diff --git a/dts/upstream/src/arm64/qcom/sm8150-hdk.dts b/dts/upstream/src/arm64/qcom/sm8150-hdk.dts
index bac08f00b30..6ea883b1edf 100644
--- a/dts/upstream/src/arm64/qcom/sm8150-hdk.dts
+++ b/dts/upstream/src/arm64/qcom/sm8150-hdk.dts
@@ -578,6 +578,11 @@
 	};
 };
 
+&pon {
+	mode-bootloader = <0x2>;
+	mode-recovery = <0x1>;
+};
+
 &pon_pwrkey {
 	status = "okay";
 };
diff --git a/dts/upstream/src/arm64/qcom/sm8150-microsoft-surface-duo.dts b/dts/upstream/src/arm64/qcom/sm8150-microsoft-surface-duo.dts
index b039773c446..9a3d0ac6c42 100644
--- a/dts/upstream/src/arm64/qcom/sm8150-microsoft-surface-duo.dts
+++ b/dts/upstream/src/arm64/qcom/sm8150-microsoft-surface-duo.dts
@@ -376,8 +376,8 @@
 		pinctrl-0 = <&da7280_intr_default>;
 
 		dlg,actuator-type = "LRA";
-		dlg,dlg,const-op-mode = <1>;
-		dlg,dlg,periodic-op-mode = <1>;
+		dlg,const-op-mode = <1>;
+		dlg,periodic-op-mode = <1>;
 		dlg,nom-microvolt = <2000000>;
 		dlg,abs-max-microvolt = <2000000>;
 		dlg,imax-microamp = <129000>;
@@ -430,6 +430,11 @@
 	/* MAX34417 @ 0x1e */
 };
 
+&pon {
+	mode-bootloader = <0x2>;
+	mode-recovery = <0x1>;
+};
+
 &pon_pwrkey {
 	status = "okay";
 };
diff --git a/dts/upstream/src/arm64/qcom/sm8150-mtp.dts b/dts/upstream/src/arm64/qcom/sm8150-mtp.dts
index 256a1ba9494..2e1c7afe0aa 100644
--- a/dts/upstream/src/arm64/qcom/sm8150-mtp.dts
+++ b/dts/upstream/src/arm64/qcom/sm8150-mtp.dts
@@ -358,6 +358,11 @@
 	status = "okay";
 };
 
+&pon {
+	mode-bootloader = <0x2>;
+	mode-recovery = <0x1>;
+};
+
 &pon_pwrkey {
 	status = "okay";
 };
diff --git a/dts/upstream/src/arm64/qcom/sm8150-sony-xperia-kumano.dtsi b/dts/upstream/src/arm64/qcom/sm8150-sony-xperia-kumano.dtsi
index ae0ca48b89a..70fd6455518 100644
--- a/dts/upstream/src/arm64/qcom/sm8150-sony-xperia-kumano.dtsi
+++ b/dts/upstream/src/arm64/qcom/sm8150-sony-xperia-kumano.dtsi
@@ -601,6 +601,11 @@
 	};
 };
 
+&pon {
+	mode-bootloader = <0x2>;
+	mode-recovery = <0x1>;
+};
+
 &pon_pwrkey {
 	status = "okay";
 };
diff --git a/dts/upstream/src/arm64/qcom/sm8150.dtsi b/dts/upstream/src/arm64/qcom/sm8150.dtsi
index cedae8d03a5..4dbda54b47a 100644
--- a/dts/upstream/src/arm64/qcom/sm8150.dtsi
+++ b/dts/upstream/src/arm64/qcom/sm8150.dtsi
@@ -3658,6 +3658,8 @@
 				iommus = <&apps_smmu 0x140 0>;
 				snps,dis_u2_susphy_quirk;
 				snps,dis_enblslpm_quirk;
+				snps,dis-u1-entry-quirk;
+				snps,dis-u2-entry-quirk;
 				phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>;
 				phy-names = "usb2-phy", "usb3-phy";
 
@@ -3735,6 +3737,8 @@
 				iommus = <&apps_smmu 0x160 0>;
 				snps,dis_u2_susphy_quirk;
 				snps,dis_enblslpm_quirk;
+				snps,dis-u1-entry-quirk;
+				snps,dis-u2-entry-quirk;
 				phys = <&usb_2_hsphy>, <&usb_2_qmpphy>;
 				phy-names = "usb2-phy", "usb3-phy";
 			};
diff --git a/dts/upstream/src/arm64/qcom/sm8250-hdk.dts b/dts/upstream/src/arm64/qcom/sm8250-hdk.dts
index 1bbb71e1a4f..f5c193c6c5f 100644
--- a/dts/upstream/src/arm64/qcom/sm8250-hdk.dts
+++ b/dts/upstream/src/arm64/qcom/sm8250-hdk.dts
@@ -373,6 +373,11 @@
 	status = "okay";
 };
 
+&pon {
+	mode-bootloader = <0x2>;
+	mode-recovery = <0x1>;
+};
+
 &pon_pwrkey {
 	status = "okay";
 };
diff --git a/dts/upstream/src/arm64/qcom/sm8250-mtp.dts b/dts/upstream/src/arm64/qcom/sm8250-mtp.dts
index 21b2ca1def8..7f592bd3024 100644
--- a/dts/upstream/src/arm64/qcom/sm8250-mtp.dts
+++ b/dts/upstream/src/arm64/qcom/sm8250-mtp.dts
@@ -627,6 +627,11 @@
 	};
 };
 
+&pon {
+	mode-bootloader = <0x2>;
+	mode-recovery = <0x1>;
+};
+
 &qupv3_id_0 {
 	status = "okay";
 };
diff --git a/dts/upstream/src/arm64/qcom/sm8250-sony-xperia-edo.dtsi b/dts/upstream/src/arm64/qcom/sm8250-sony-xperia-edo.dtsi
index f6870d3f288..d8289b2698f 100644
--- a/dts/upstream/src/arm64/qcom/sm8250-sony-xperia-edo.dtsi
+++ b/dts/upstream/src/arm64/qcom/sm8250-sony-xperia-edo.dtsi
@@ -591,6 +591,11 @@
 	};
 };
 
+&pon {
+	mode-bootloader = <0x2>;
+	mode-recovery = <0x1>;
+};
+
 &pon_pwrkey {
 	status = "okay";
 };
diff --git a/dts/upstream/src/arm64/qcom/sm8250-xiaomi-elish-common.dtsi b/dts/upstream/src/arm64/qcom/sm8250-xiaomi-elish-common.dtsi
index 3596dd328c3..813b009b7bd 100644
--- a/dts/upstream/src/arm64/qcom/sm8250-xiaomi-elish-common.dtsi
+++ b/dts/upstream/src/arm64/qcom/sm8250-xiaomi-elish-common.dtsi
@@ -30,6 +30,10 @@
 	qcom,msm-id = <QCOM_ID_SM8250 0x20001>; /* SM8250 v2.1 */
 	qcom,board-id = <0x10008 0>;
 
+	aliases {
+		serial0 = &uart6;
+	};
+
 	chosen {
 		#address-cells = <2>;
 		#size-cells = <2>;
@@ -97,6 +101,67 @@
 		};
 	};
 
+	qca6390-pmu {
+		compatible = "qcom,qca6390-pmu";
+
+		pinctrl-names = "default";
+		pinctrl-0 = <&bt_en_state>, <&wlan_en_state>;
+
+		vddaon-supply = <&vreg_s6a_0p95>;
+		vddpmu-supply = <&vreg_s6a_0p95>;
+		vddrfa0p95-supply = <&vreg_s6a_0p95>;
+		vddrfa1p3-supply = <&vreg_s8c_1p35>;
+		vddrfa1p9-supply = <&vreg_s5a_1p9>;
+		vddpcie1p3-supply = <&vreg_s8c_1p35>;
+		vddpcie1p9-supply = <&vreg_s5a_1p9>;
+		vddio-supply = <&vreg_s4a_1p8>;
+
+		wlan-enable-gpios = <&tlmm 20 GPIO_ACTIVE_HIGH>;
+		bt-enable-gpios = <&tlmm 21 GPIO_ACTIVE_HIGH>;
+
+		regulators {
+			vreg_pmu_rfa_cmn: ldo0 {
+				regulator-name = "vreg_pmu_rfa_cmn";
+			};
+
+			vreg_pmu_aon_0p59: ldo1 {
+				regulator-name = "vreg_pmu_aon_0p59";
+			};
+
+			vreg_pmu_wlcx_0p8: ldo2 {
+				regulator-name = "vreg_pmu_wlcx_0p8";
+			};
+
+			vreg_pmu_wlmx_0p85: ldo3 {
+				regulator-name = "vreg_pmu_wlmx_0p85";
+			};
+
+			vreg_pmu_btcmx_0p85: ldo4 {
+				regulator-name = "vreg_pmu_btcmx_0p85";
+			};
+
+			vreg_pmu_rfa_0p8: ldo5 {
+				regulator-name = "vreg_pmu_rfa_0p8";
+			};
+
+			vreg_pmu_rfa_1p2: ldo6 {
+				regulator-name = "vreg_pmu_rfa_1p2";
+			};
+
+			vreg_pmu_rfa_1p7: ldo7 {
+				regulator-name = "vreg_pmu_rfa_1p7";
+			};
+
+			vreg_pmu_pcie_0p9: ldo8 {
+				regulator-name = "vreg_pmu_pcie_0p9";
+			};
+
+			vreg_pmu_pcie_1p8: ldo9 {
+				regulator-name = "vreg_pmu_pcie_1p8";
+			};
+		};
+	};
+
 	vph_pwr: vph-pwr-regulator {
 		compatible = "regulator-fixed";
 		regulator-name = "vph_pwr";
@@ -619,6 +684,25 @@
 	status = "okay";
 };
 
+&pcieport0 {
+	wifi@0 {
+		compatible = "pci17cb,1101";
+		reg = <0x10000 0x0 0x0 0x0 0x0>;
+
+		vddrfacmn-supply = <&vreg_pmu_rfa_cmn>;
+		vddaon-supply = <&vreg_pmu_aon_0p59>;
+		vddwlcx-supply = <&vreg_pmu_wlcx_0p8>;
+		vddwlmx-supply = <&vreg_pmu_wlmx_0p85>;
+		vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>;
+		vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>;
+		vddrfa1p7-supply = <&vreg_pmu_rfa_1p7>;
+		vddpcie0p9-supply = <&vreg_pmu_pcie_0p9>;
+		vddpcie1p8-supply = <&vreg_pmu_pcie_1p8>;
+
+		qcom,ath11k-calibration-variant = "Xiaomi_Pad_5Pro";
+	};
+};
+
 &pm8150_gpios {
 	vol_up_n: vol-up-n-state {
 		pins = "gpio6";
@@ -673,6 +757,11 @@
 	status = "okay";
 };
 
+&pon {
+	mode-bootloader = <0x2>;
+	mode-recovery = <0x1>;
+};
+
 &pon_pwrkey {
 	status = "okay";
 };
@@ -701,6 +790,37 @@
 
 &tlmm {
 	gpio-reserved-ranges = <40 4>;
+
+	bt_en_state: bt-default-state {
+		pins = "gpio21";
+		function = "gpio";
+		drive-strength = <16>;
+		output-low;
+		bias-pull-up;
+	};
+
+	wlan_en_state: wlan-default-state {
+		pins = "gpio20";
+		function = "gpio";
+		drive-strength = <16>;
+		output-low;
+		bias-pull-up;
+	};
+};
+
+&uart6 {
+	status = "okay";
+
+	bluetooth {
+		compatible = "qcom,qca6390-bt";
+
+		vddrfacmn-supply = <&vreg_pmu_rfa_cmn>;
+		vddaon-supply = <&vreg_pmu_aon_0p59>;
+		vddbtcmx-supply = <&vreg_pmu_btcmx_0p85>;
+		vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>;
+		vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>;
+		vddrfa1p7-supply = <&vreg_pmu_rfa_1p7>;
+	};
 };
 
 &usb_1 {
diff --git a/dts/upstream/src/arm64/qcom/sm8250-xiaomi-pipa.dts b/dts/upstream/src/arm64/qcom/sm8250-xiaomi-pipa.dts
index 86e1f7fd1c2..668078ea4f0 100644
--- a/dts/upstream/src/arm64/qcom/sm8250-xiaomi-pipa.dts
+++ b/dts/upstream/src/arm64/qcom/sm8250-xiaomi-pipa.dts
@@ -554,6 +554,11 @@
 	};
 };
 
+&pon {
+	mode-bootloader = <0x2>;
+	mode-recovery = <0x1>;
+};
+
 &pon_pwrkey {
 	status = "okay";
 };
diff --git a/dts/upstream/src/arm64/qcom/sm8250.dtsi b/dts/upstream/src/arm64/qcom/sm8250.dtsi
index 48318ed1ce9..c2937b4d9f1 100644
--- a/dts/upstream/src/arm64/qcom/sm8250.dtsi
+++ b/dts/upstream/src/arm64/qcom/sm8250.dtsi
@@ -84,7 +84,7 @@
 
 		sleep_clk: sleep-clk {
 			compatible = "fixed-clock";
-			clock-frequency = <32768>;
+			clock-frequency = <32764>;
 			#clock-cells = <0>;
 		};
 	};
@@ -4207,6 +4207,8 @@
 				iommus = <&apps_smmu 0x0 0x0>;
 				snps,dis_u2_susphy_quirk;
 				snps,dis_enblslpm_quirk;
+				snps,dis-u1-entry-quirk;
+				snps,dis-u2-entry-quirk;
 				phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>;
 				phy-names = "usb2-phy", "usb3-phy";
 
@@ -4294,6 +4296,8 @@
 				iommus = <&apps_smmu 0x20 0>;
 				snps,dis_u2_susphy_quirk;
 				snps,dis_enblslpm_quirk;
+				snps,dis-u1-entry-quirk;
+				snps,dis-u2-entry-quirk;
 				phys = <&usb_2_hsphy>, <&usb_2_qmpphy>;
 				phy-names = "usb2-phy", "usb3-phy";
 			};
@@ -4481,20 +4485,20 @@
 				    "vfe_lite0",
 				    "vfe_lite1";
 
-			interrupts = <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 478 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 479 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
+			interrupts = <GIC_SPI 477 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 478 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 479 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 448 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 86 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 89 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 464 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 466 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 468 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 359 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 465 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 467 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 469 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 360 IRQ_TYPE_EDGE_RISING>;
 			interrupt-names = "csiphy0",
 					  "csiphy1",
 					  "csiphy2",
diff --git a/dts/upstream/src/arm64/qcom/sm8350-hdk.dts b/dts/upstream/src/arm64/qcom/sm8350-hdk.dts
index 796cbb58ef6..f9de0e49fa2 100644
--- a/dts/upstream/src/arm64/qcom/sm8350-hdk.dts
+++ b/dts/upstream/src/arm64/qcom/sm8350-hdk.dts
@@ -925,3 +925,10 @@
 		};
 	};
 };
+
+&ipa {
+	qcom,gsi-loader = "self";
+	memory-region = <&pil_ipa_fw_mem>;
+	status = "okay";
+	firmware-name = "qcom/sm8350/ipa_fws.mbn";
+};
diff --git a/dts/upstream/src/arm64/qcom/sm8350.dtsi b/dts/upstream/src/arm64/qcom/sm8350.dtsi
index 877905dfd86..69da30f35ba 100644
--- a/dts/upstream/src/arm64/qcom/sm8350.dtsi
+++ b/dts/upstream/src/arm64/qcom/sm8350.dtsi
@@ -42,7 +42,7 @@
 
 		sleep_clk: sleep-clk {
 			compatible = "fixed-clock";
-			clock-frequency = <32000>;
+			clock-frequency = <32764>;
 			#clock-cells = <0>;
 		};
 	};
@@ -1876,6 +1876,142 @@
 			reg = <0x0 0x1fc0000 0x0 0x30000>;
 		};
 
+		adsp: remoteproc@3000000 {
+			compatible = "qcom,sm8350-adsp-pas";
+			reg = <0x0 0x03000000 0x0 0x10000>;
+
+			interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>,
+					      <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
+					      <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
+					      <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
+					      <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>;
+			interrupt-names = "wdog", "fatal", "ready",
+					  "handover", "stop-ack";
+
+			clocks = <&rpmhcc RPMH_CXO_CLK>;
+			clock-names = "xo";
+
+			power-domains = <&rpmhpd RPMHPD_LCX>,
+					<&rpmhpd RPMHPD_LMX>;
+			power-domain-names = "lcx", "lmx";
+
+			memory-region = <&pil_adsp_mem>;
+
+			qcom,qmp = <&aoss_qmp>;
+
+			qcom,smem-states = <&smp2p_adsp_out 0>;
+			qcom,smem-state-names = "stop";
+
+			status = "disabled";
+
+			glink-edge {
+				interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
+							     IPCC_MPROC_SIGNAL_GLINK_QMP
+							     IRQ_TYPE_EDGE_RISING>;
+				mboxes = <&ipcc IPCC_CLIENT_LPASS
+						IPCC_MPROC_SIGNAL_GLINK_QMP>;
+
+				label = "lpass";
+				qcom,remote-pid = <2>;
+
+				apr {
+					compatible = "qcom,apr-v2";
+					qcom,glink-channels = "apr_audio_svc";
+					qcom,domain = <APR_DOMAIN_ADSP>;
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					service@3 {
+						reg = <APR_SVC_ADSP_CORE>;
+						compatible = "qcom,q6core";
+						qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
+					};
+
+					q6afe: service@4 {
+						compatible = "qcom,q6afe";
+						reg = <APR_SVC_AFE>;
+						qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
+
+						q6afedai: dais {
+							compatible = "qcom,q6afe-dais";
+							#address-cells = <1>;
+							#size-cells = <0>;
+							#sound-dai-cells = <1>;
+						};
+
+						q6afecc: clock-controller {
+							compatible = "qcom,q6afe-clocks";
+							#clock-cells = <2>;
+						};
+					};
+
+					q6asm: service@7 {
+						compatible = "qcom,q6asm";
+						reg = <APR_SVC_ASM>;
+						qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
+
+						q6asmdai: dais {
+							compatible = "qcom,q6asm-dais";
+							#address-cells = <1>;
+							#size-cells = <0>;
+							#sound-dai-cells = <1>;
+							iommus = <&apps_smmu 0x1801 0x0>;
+
+							dai@0 {
+								reg = <0>;
+							};
+
+							dai@1 {
+								reg = <1>;
+							};
+
+							dai@2 {
+								reg = <2>;
+							};
+						};
+					};
+
+					q6adm: service@8 {
+						compatible = "qcom,q6adm";
+						reg = <APR_SVC_ADM>;
+						qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
+
+						q6routing: routing {
+							compatible = "qcom,q6adm-routing";
+							#sound-dai-cells = <0>;
+						};
+					};
+				};
+
+				fastrpc {
+					compatible = "qcom,fastrpc";
+					qcom,glink-channels = "fastrpcglink-apps-dsp";
+					label = "adsp";
+					qcom,non-secure-domain;
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					compute-cb@3 {
+						compatible = "qcom,fastrpc-compute-cb";
+						reg = <3>;
+						iommus = <&apps_smmu 0x1803 0x0>;
+					};
+
+					compute-cb@4 {
+						compatible = "qcom,fastrpc-compute-cb";
+						reg = <4>;
+						iommus = <&apps_smmu 0x1804 0x0>;
+					};
+
+					compute-cb@5 {
+						compatible = "qcom,fastrpc-compute-cb";
+						reg = <5>;
+						iommus = <&apps_smmu 0x1805 0x0>;
+					};
+				};
+			};
+		};
+
 		lpass_tlmm: pinctrl@33c0000 {
 			compatible = "qcom,sm8350-lpass-lpi-pinctrl";
 			reg = <0 0x033c0000 0 0x20000>,
@@ -2078,7 +2214,7 @@
 
 		mpss: remoteproc@4080000 {
 			compatible = "qcom,sm8350-mpss-pas";
-			reg = <0x0 0x04080000 0x0 0x4040>;
+			reg = <0x0 0x04080000 0x0 0x10000>;
 
 			interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>,
 					      <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>,
@@ -2360,6 +2496,115 @@
 			qcom,bcm-voters = <&apps_bcm_voter>;
 		};
 
+		cdsp: remoteproc@a300000 {
+			compatible = "qcom,sm8350-cdsp-pas";
+			reg = <0x0 0x0a300000 0x0 0x10000>;
+
+			interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
+					      <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>,
+					      <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>,
+					      <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>,
+					      <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>;
+			interrupt-names = "wdog", "fatal", "ready",
+					  "handover", "stop-ack";
+
+			clocks = <&rpmhcc RPMH_CXO_CLK>;
+			clock-names = "xo";
+
+			power-domains = <&rpmhpd RPMHPD_CX>,
+					<&rpmhpd RPMHPD_MXC>;
+			power-domain-names = "cx", "mxc";
+
+			interconnects = <&compute_noc MASTER_CDSP_PROC 0 &mc_virt SLAVE_EBI1 0>;
+
+			memory-region = <&pil_cdsp_mem>;
+
+			qcom,qmp = <&aoss_qmp>;
+
+			qcom,smem-states = <&smp2p_cdsp_out 0>;
+			qcom,smem-state-names = "stop";
+
+			status = "disabled";
+
+			glink-edge {
+				interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
+							     IPCC_MPROC_SIGNAL_GLINK_QMP
+							     IRQ_TYPE_EDGE_RISING>;
+				mboxes = <&ipcc IPCC_CLIENT_CDSP
+						IPCC_MPROC_SIGNAL_GLINK_QMP>;
+
+				label = "cdsp";
+				qcom,remote-pid = <5>;
+
+				fastrpc {
+					compatible = "qcom,fastrpc";
+					qcom,glink-channels = "fastrpcglink-apps-dsp";
+					label = "cdsp";
+					qcom,non-secure-domain;
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					compute-cb@1 {
+						compatible = "qcom,fastrpc-compute-cb";
+						reg = <1>;
+						iommus = <&apps_smmu 0x2161 0x0400>,
+							 <&apps_smmu 0x1181 0x0420>;
+					};
+
+					compute-cb@2 {
+						compatible = "qcom,fastrpc-compute-cb";
+						reg = <2>;
+						iommus = <&apps_smmu 0x2162 0x0400>,
+							 <&apps_smmu 0x1182 0x0420>;
+					};
+
+					compute-cb@3 {
+						compatible = "qcom,fastrpc-compute-cb";
+						reg = <3>;
+						iommus = <&apps_smmu 0x2163 0x0400>,
+							 <&apps_smmu 0x1183 0x0420>;
+					};
+
+					compute-cb@4 {
+						compatible = "qcom,fastrpc-compute-cb";
+						reg = <4>;
+						iommus = <&apps_smmu 0x2164 0x0400>,
+							 <&apps_smmu 0x1184 0x0420>;
+					};
+
+					compute-cb@5 {
+						compatible = "qcom,fastrpc-compute-cb";
+						reg = <5>;
+						iommus = <&apps_smmu 0x2165 0x0400>,
+							 <&apps_smmu 0x1185 0x0420>;
+					};
+
+					compute-cb@6 {
+						compatible = "qcom,fastrpc-compute-cb";
+						reg = <6>;
+						iommus = <&apps_smmu 0x2166 0x0400>,
+							 <&apps_smmu 0x1186 0x0420>;
+					};
+
+					compute-cb@7 {
+						compatible = "qcom,fastrpc-compute-cb";
+						reg = <7>;
+						iommus = <&apps_smmu 0x2167 0x0400>,
+							 <&apps_smmu 0x1187 0x0420>;
+					};
+
+					compute-cb@8 {
+						compatible = "qcom,fastrpc-compute-cb";
+						reg = <8>;
+						iommus = <&apps_smmu 0x2168 0x0400>,
+							 <&apps_smmu 0x1188 0x0420>;
+					};
+
+					/* note: secure cb9 in downstream */
+				};
+			};
+		};
+
 		usb_1: usb@a6f8800 {
 			compatible = "qcom,sm8350-dwc3", "qcom,dwc3";
 			reg = <0 0x0a6f8800 0 0x400>;
@@ -2409,6 +2654,8 @@
 				iommus = <&apps_smmu 0x0 0x0>;
 				snps,dis_u2_susphy_quirk;
 				snps,dis_enblslpm_quirk;
+				snps,dis-u1-entry-quirk;
+				snps,dis-u2-entry-quirk;
 				phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>;
 				phy-names = "usb2-phy", "usb3-phy";
 
@@ -2485,6 +2732,8 @@
 				iommus = <&apps_smmu 0x20 0x0>;
 				snps,dis_u2_susphy_quirk;
 				snps,dis_enblslpm_quirk;
+				snps,dis-u1-entry-quirk;
+				snps,dis-u2-entry-quirk;
 				phys = <&usb_2_hsphy>, <&usb_2_qmpphy>;
 				phy-names = "usb2-phy", "usb3-phy";
 			};
@@ -3285,142 +3534,6 @@
 			dma-coherent;
 		};
 
-		adsp: remoteproc@17300000 {
-			compatible = "qcom,sm8350-adsp-pas";
-			reg = <0 0x17300000 0 0x100>;
-
-			interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>,
-					      <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
-					      <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
-					      <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
-					      <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>;
-			interrupt-names = "wdog", "fatal", "ready",
-					  "handover", "stop-ack";
-
-			clocks = <&rpmhcc RPMH_CXO_CLK>;
-			clock-names = "xo";
-
-			power-domains = <&rpmhpd RPMHPD_LCX>,
-					<&rpmhpd RPMHPD_LMX>;
-			power-domain-names = "lcx", "lmx";
-
-			memory-region = <&pil_adsp_mem>;
-
-			qcom,qmp = <&aoss_qmp>;
-
-			qcom,smem-states = <&smp2p_adsp_out 0>;
-			qcom,smem-state-names = "stop";
-
-			status = "disabled";
-
-			glink-edge {
-				interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
-							     IPCC_MPROC_SIGNAL_GLINK_QMP
-							     IRQ_TYPE_EDGE_RISING>;
-				mboxes = <&ipcc IPCC_CLIENT_LPASS
-						IPCC_MPROC_SIGNAL_GLINK_QMP>;
-
-				label = "lpass";
-				qcom,remote-pid = <2>;
-
-				apr {
-					compatible = "qcom,apr-v2";
-					qcom,glink-channels = "apr_audio_svc";
-					qcom,domain = <APR_DOMAIN_ADSP>;
-					#address-cells = <1>;
-					#size-cells = <0>;
-
-					service@3 {
-						reg = <APR_SVC_ADSP_CORE>;
-						compatible = "qcom,q6core";
-						qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
-					};
-
-					q6afe: service@4 {
-						compatible = "qcom,q6afe";
-						reg = <APR_SVC_AFE>;
-						qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
-
-						q6afedai: dais {
-							compatible = "qcom,q6afe-dais";
-							#address-cells = <1>;
-							#size-cells = <0>;
-							#sound-dai-cells = <1>;
-						};
-
-						q6afecc: clock-controller {
-							compatible = "qcom,q6afe-clocks";
-							#clock-cells = <2>;
-						};
-					};
-
-					q6asm: service@7 {
-						compatible = "qcom,q6asm";
-						reg = <APR_SVC_ASM>;
-						qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
-
-						q6asmdai: dais {
-							compatible = "qcom,q6asm-dais";
-							#address-cells = <1>;
-							#size-cells = <0>;
-							#sound-dai-cells = <1>;
-							iommus = <&apps_smmu 0x1801 0x0>;
-
-							dai@0 {
-								reg = <0>;
-							};
-
-							dai@1 {
-								reg = <1>;
-							};
-
-							dai@2 {
-								reg = <2>;
-							};
-						};
-					};
-
-					q6adm: service@8 {
-						compatible = "qcom,q6adm";
-						reg = <APR_SVC_ADM>;
-						qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
-
-						q6routing: routing {
-							compatible = "qcom,q6adm-routing";
-							#sound-dai-cells = <0>;
-						};
-					};
-				};
-
-				fastrpc {
-					compatible = "qcom,fastrpc";
-					qcom,glink-channels = "fastrpcglink-apps-dsp";
-					label = "adsp";
-					qcom,non-secure-domain;
-					#address-cells = <1>;
-					#size-cells = <0>;
-
-					compute-cb@3 {
-						compatible = "qcom,fastrpc-compute-cb";
-						reg = <3>;
-						iommus = <&apps_smmu 0x1803 0x0>;
-					};
-
-					compute-cb@4 {
-						compatible = "qcom,fastrpc-compute-cb";
-						reg = <4>;
-						iommus = <&apps_smmu 0x1804 0x0>;
-					};
-
-					compute-cb@5 {
-						compatible = "qcom,fastrpc-compute-cb";
-						reg = <5>;
-						iommus = <&apps_smmu 0x1805 0x0>;
-					};
-				};
-			};
-		};
-
 		intc: interrupt-controller@17a00000 {
 			compatible = "arm,gic-v3";
 			#interrupt-cells = <3>;
@@ -3589,115 +3702,6 @@
 			#freq-domain-cells = <1>;
 			#clock-cells = <1>;
 		};
-
-		cdsp: remoteproc@98900000 {
-			compatible = "qcom,sm8350-cdsp-pas";
-			reg = <0 0x98900000 0 0x1400000>;
-
-			interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
-					      <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>,
-					      <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>,
-					      <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>,
-					      <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>;
-			interrupt-names = "wdog", "fatal", "ready",
-					  "handover", "stop-ack";
-
-			clocks = <&rpmhcc RPMH_CXO_CLK>;
-			clock-names = "xo";
-
-			power-domains = <&rpmhpd RPMHPD_CX>,
-					<&rpmhpd RPMHPD_MXC>;
-			power-domain-names = "cx", "mxc";
-
-			interconnects = <&compute_noc MASTER_CDSP_PROC 0 &mc_virt SLAVE_EBI1 0>;
-
-			memory-region = <&pil_cdsp_mem>;
-
-			qcom,qmp = <&aoss_qmp>;
-
-			qcom,smem-states = <&smp2p_cdsp_out 0>;
-			qcom,smem-state-names = "stop";
-
-			status = "disabled";
-
-			glink-edge {
-				interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
-							     IPCC_MPROC_SIGNAL_GLINK_QMP
-							     IRQ_TYPE_EDGE_RISING>;
-				mboxes = <&ipcc IPCC_CLIENT_CDSP
-						IPCC_MPROC_SIGNAL_GLINK_QMP>;
-
-				label = "cdsp";
-				qcom,remote-pid = <5>;
-
-				fastrpc {
-					compatible = "qcom,fastrpc";
-					qcom,glink-channels = "fastrpcglink-apps-dsp";
-					label = "cdsp";
-					qcom,non-secure-domain;
-					#address-cells = <1>;
-					#size-cells = <0>;
-
-					compute-cb@1 {
-						compatible = "qcom,fastrpc-compute-cb";
-						reg = <1>;
-						iommus = <&apps_smmu 0x2161 0x0400>,
-							 <&apps_smmu 0x1181 0x0420>;
-					};
-
-					compute-cb@2 {
-						compatible = "qcom,fastrpc-compute-cb";
-						reg = <2>;
-						iommus = <&apps_smmu 0x2162 0x0400>,
-							 <&apps_smmu 0x1182 0x0420>;
-					};
-
-					compute-cb@3 {
-						compatible = "qcom,fastrpc-compute-cb";
-						reg = <3>;
-						iommus = <&apps_smmu 0x2163 0x0400>,
-							 <&apps_smmu 0x1183 0x0420>;
-					};
-
-					compute-cb@4 {
-						compatible = "qcom,fastrpc-compute-cb";
-						reg = <4>;
-						iommus = <&apps_smmu 0x2164 0x0400>,
-							 <&apps_smmu 0x1184 0x0420>;
-					};
-
-					compute-cb@5 {
-						compatible = "qcom,fastrpc-compute-cb";
-						reg = <5>;
-						iommus = <&apps_smmu 0x2165 0x0400>,
-							 <&apps_smmu 0x1185 0x0420>;
-					};
-
-					compute-cb@6 {
-						compatible = "qcom,fastrpc-compute-cb";
-						reg = <6>;
-						iommus = <&apps_smmu 0x2166 0x0400>,
-							 <&apps_smmu 0x1186 0x0420>;
-					};
-
-					compute-cb@7 {
-						compatible = "qcom,fastrpc-compute-cb";
-						reg = <7>;
-						iommus = <&apps_smmu 0x2167 0x0400>,
-							 <&apps_smmu 0x1187 0x0420>;
-					};
-
-					compute-cb@8 {
-						compatible = "qcom,fastrpc-compute-cb";
-						reg = <8>;
-						iommus = <&apps_smmu 0x2168 0x0400>,
-							 <&apps_smmu 0x1188 0x0420>;
-					};
-
-					/* note: secure cb9 in downstream */
-				};
-			};
-		};
 	};
 
 	thermal_zones: thermal-zones {
diff --git a/dts/upstream/src/arm64/qcom/sm8450.dtsi b/dts/upstream/src/arm64/qcom/sm8450.dtsi
index 53147aa6f7e..9c809fc5fa4 100644
--- a/dts/upstream/src/arm64/qcom/sm8450.dtsi
+++ b/dts/upstream/src/arm64/qcom/sm8450.dtsi
@@ -43,7 +43,7 @@
 		sleep_clk: sleep-clk {
 			compatible = "fixed-clock";
 			#clock-cells = <0>;
-			clock-frequency = <32000>;
+			clock-frequency = <32764>;
 		};
 	};
 
@@ -287,6 +287,192 @@
 		};
 	};
 
+	ete-0 {
+		compatible = "arm,embedded-trace-extension";
+		cpu = <&cpu0>;
+
+		out-ports {
+			port {
+				ete0_out_funnel_ete: endpoint {
+					remote-endpoint = <&funnel_ete_in_ete0>;
+				};
+			};
+		};
+	};
+
+	ete-1 {
+		compatible = "arm,embedded-trace-extension";
+		cpu = <&cpu1>;
+
+		out-ports {
+			port {
+				ete1_out_funnel_ete: endpoint {
+					remote-endpoint = <&funnel_ete_in_ete1>;
+				};
+			};
+		};
+	};
+
+	ete-2 {
+		compatible = "arm,embedded-trace-extension";
+		cpu = <&cpu2>;
+
+		out-ports {
+			port {
+				ete2_out_funnel_ete: endpoint {
+					remote-endpoint = <&funnel_ete_in_ete2>;
+				};
+			};
+		};
+	};
+
+	ete-3 {
+		compatible = "arm,embedded-trace-extension";
+		cpu = <&cpu3>;
+
+		out-ports {
+			port {
+				ete3_out_funnel_ete: endpoint {
+					remote-endpoint = <&funnel_ete_in_ete3>;
+				};
+			};
+		};
+	};
+
+	ete-4 {
+		compatible = "arm,embedded-trace-extension";
+		cpu = <&cpu4>;
+
+		out-ports {
+			port {
+				ete4_out_funnel_ete: endpoint {
+					remote-endpoint = <&funnel_ete_in_ete4>;
+				};
+			};
+		};
+	};
+
+	ete-5 {
+		compatible = "arm,embedded-trace-extension";
+		cpu = <&cpu5>;
+
+		out-ports {
+			port {
+				ete5_out_funnel_ete: endpoint {
+					remote-endpoint = <&funnel_ete_in_ete5>;
+				};
+			};
+		};
+	};
+
+	ete-6 {
+		compatible = "arm,embedded-trace-extension";
+		cpu = <&cpu6>;
+
+		out-ports {
+			port {
+				ete6_out_funnel_ete: endpoint {
+					remote-endpoint = <&funnel_ete_in_ete6>;
+				};
+			};
+		};
+	};
+
+	ete-7 {
+		compatible = "arm,embedded-trace-extension";
+		cpu = <&cpu7>;
+
+		out-ports {
+			port {
+				ete7_out_funnel_ete: endpoint {
+					remote-endpoint = <&funnel_ete_in_ete7>;
+				};
+			};
+		};
+	};
+
+	funnel-ete {
+		compatible = "arm,coresight-static-funnel";
+
+		out-ports {
+			port {
+				funnel_ete_out_funnel_apss: endpoint {
+					remote-endpoint =
+						<&funnel_apss_in_funnel_ete>;
+				};
+			};
+		};
+
+		in-ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@0 {
+				reg = <0>;
+				funnel_ete_in_ete0: endpoint {
+					remote-endpoint =
+						<&ete0_out_funnel_ete>;
+				};
+			};
+
+			port@1 {
+				reg = <1>;
+				funnel_ete_in_ete1: endpoint {
+					remote-endpoint =
+						<&ete1_out_funnel_ete>;
+				};
+			};
+
+			port@2 {
+				reg = <2>;
+				funnel_ete_in_ete2: endpoint {
+					remote-endpoint =
+						<&ete2_out_funnel_ete>;
+				};
+			};
+
+			port@3 {
+				reg = <3>;
+				funnel_ete_in_ete3: endpoint {
+					remote-endpoint =
+						<&ete3_out_funnel_ete>;
+				};
+			};
+
+			port@4 {
+				reg = <4>;
+				funnel_ete_in_ete4: endpoint {
+					remote-endpoint =
+						<&ete4_out_funnel_ete>;
+				};
+			};
+
+			port@5 {
+				reg = <5>;
+				funnel_ete_in_ete5: endpoint {
+					remote-endpoint =
+						<&ete5_out_funnel_ete>;
+				};
+			};
+
+			port@6 {
+				reg = <6>;
+				funnel_ete_in_ete6: endpoint {
+					remote-endpoint =
+						<&ete6_out_funnel_ete>;
+				};
+			};
+
+			port@7 {
+				reg = <7>;
+				funnel_ete_in_ete7: endpoint {
+					remote-endpoint =
+						<&ete7_out_funnel_ete>;
+				};
+			};
+		};
+	};
+
 	firmware {
 		scm: scm {
 			compatible = "qcom,scm-sm8450", "qcom,scm";
@@ -2496,6 +2682,112 @@
 			};
 		};
 
+		remoteproc_adsp: remoteproc@3000000 {
+			compatible = "qcom,sm8450-adsp-pas";
+			reg = <0x0 0x03000000 0x0 0x10000>;
+
+			interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>,
+					      <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
+					      <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
+					      <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
+					      <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>;
+			interrupt-names = "wdog", "fatal", "ready",
+					  "handover", "stop-ack";
+
+			clocks = <&rpmhcc RPMH_CXO_CLK>;
+			clock-names = "xo";
+
+			power-domains = <&rpmhpd RPMHPD_LCX>,
+					<&rpmhpd RPMHPD_LMX>;
+			power-domain-names = "lcx", "lmx";
+
+			memory-region = <&adsp_mem>;
+
+			qcom,qmp = <&aoss_qmp>;
+
+			qcom,smem-states = <&smp2p_adsp_out 0>;
+			qcom,smem-state-names = "stop";
+
+			status = "disabled";
+
+			remoteproc_adsp_glink: glink-edge {
+				interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
+							     IPCC_MPROC_SIGNAL_GLINK_QMP
+							     IRQ_TYPE_EDGE_RISING>;
+				mboxes = <&ipcc IPCC_CLIENT_LPASS
+						IPCC_MPROC_SIGNAL_GLINK_QMP>;
+
+				label = "lpass";
+				qcom,remote-pid = <2>;
+
+				gpr {
+					compatible = "qcom,gpr";
+					qcom,glink-channels = "adsp_apps";
+					qcom,domain = <GPR_DOMAIN_ID_ADSP>;
+					qcom,intents = <512 20>;
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					q6apm: service@1 {
+						compatible = "qcom,q6apm";
+						reg = <GPR_APM_MODULE_IID>;
+						#sound-dai-cells = <0>;
+						qcom,protection-domain = "avs/audio",
+									 "msm/adsp/audio_pd";
+
+						q6apmdai: dais {
+							compatible = "qcom,q6apm-dais";
+							iommus = <&apps_smmu 0x1801 0x0>;
+						};
+
+						q6apmbedai: bedais {
+							compatible = "qcom,q6apm-lpass-dais";
+							#sound-dai-cells = <1>;
+						};
+					};
+
+					q6prm: service@2 {
+						compatible = "qcom,q6prm";
+						reg = <GPR_PRM_MODULE_IID>;
+						qcom,protection-domain = "avs/audio",
+									 "msm/adsp/audio_pd";
+
+						q6prmcc: clock-controller {
+							compatible = "qcom,q6prm-lpass-clocks";
+							#clock-cells = <2>;
+						};
+					};
+				};
+
+				fastrpc {
+					compatible = "qcom,fastrpc";
+					qcom,glink-channels = "fastrpcglink-apps-dsp";
+					label = "adsp";
+					qcom,non-secure-domain;
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					compute-cb@3 {
+						compatible = "qcom,fastrpc-compute-cb";
+						reg = <3>;
+						iommus = <&apps_smmu 0x1803 0x0>;
+					};
+
+					compute-cb@4 {
+						compatible = "qcom,fastrpc-compute-cb";
+						reg = <4>;
+						iommus = <&apps_smmu 0x1804 0x0>;
+					};
+
+					compute-cb@5 {
+						compatible = "qcom,fastrpc-compute-cb";
+						reg = <5>;
+						iommus = <&apps_smmu 0x1805 0x0>;
+					};
+				};
+			};
+		};
+
 		wsa2macro: codec@31e0000 {
 			compatible = "qcom,sm8450-lpass-wsa-macro";
 			reg = <0 0x031e0000 0 0x1000>;
@@ -2692,115 +2984,9 @@
 			status = "disabled";
 		};
 
-		remoteproc_adsp: remoteproc@30000000 {
-			compatible = "qcom,sm8450-adsp-pas";
-			reg = <0 0x30000000 0 0x100>;
-
-			interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>,
-					      <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
-					      <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
-					      <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
-					      <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>;
-			interrupt-names = "wdog", "fatal", "ready",
-					  "handover", "stop-ack";
-
-			clocks = <&rpmhcc RPMH_CXO_CLK>;
-			clock-names = "xo";
-
-			power-domains = <&rpmhpd RPMHPD_LCX>,
-					<&rpmhpd RPMHPD_LMX>;
-			power-domain-names = "lcx", "lmx";
-
-			memory-region = <&adsp_mem>;
-
-			qcom,qmp = <&aoss_qmp>;
-
-			qcom,smem-states = <&smp2p_adsp_out 0>;
-			qcom,smem-state-names = "stop";
-
-			status = "disabled";
-
-			remoteproc_adsp_glink: glink-edge {
-				interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
-							     IPCC_MPROC_SIGNAL_GLINK_QMP
-							     IRQ_TYPE_EDGE_RISING>;
-				mboxes = <&ipcc IPCC_CLIENT_LPASS
-						IPCC_MPROC_SIGNAL_GLINK_QMP>;
-
-				label = "lpass";
-				qcom,remote-pid = <2>;
-
-				gpr {
-					compatible = "qcom,gpr";
-					qcom,glink-channels = "adsp_apps";
-					qcom,domain = <GPR_DOMAIN_ID_ADSP>;
-					qcom,intents = <512 20>;
-					#address-cells = <1>;
-					#size-cells = <0>;
-
-					q6apm: service@1 {
-						compatible = "qcom,q6apm";
-						reg = <GPR_APM_MODULE_IID>;
-						#sound-dai-cells = <0>;
-						qcom,protection-domain = "avs/audio",
-									 "msm/adsp/audio_pd";
-
-						q6apmdai: dais {
-							compatible = "qcom,q6apm-dais";
-							iommus = <&apps_smmu 0x1801 0x0>;
-						};
-
-						q6apmbedai: bedais {
-							compatible = "qcom,q6apm-lpass-dais";
-							#sound-dai-cells = <1>;
-						};
-					};
-
-					q6prm: service@2 {
-						compatible = "qcom,q6prm";
-						reg = <GPR_PRM_MODULE_IID>;
-						qcom,protection-domain = "avs/audio",
-									 "msm/adsp/audio_pd";
-
-						q6prmcc: clock-controller {
-							compatible = "qcom,q6prm-lpass-clocks";
-							#clock-cells = <2>;
-						};
-					};
-				};
-
-				fastrpc {
-					compatible = "qcom,fastrpc";
-					qcom,glink-channels = "fastrpcglink-apps-dsp";
-					label = "adsp";
-					qcom,non-secure-domain;
-					#address-cells = <1>;
-					#size-cells = <0>;
-
-					compute-cb@3 {
-						compatible = "qcom,fastrpc-compute-cb";
-						reg = <3>;
-						iommus = <&apps_smmu 0x1803 0x0>;
-					};
-
-					compute-cb@4 {
-						compatible = "qcom,fastrpc-compute-cb";
-						reg = <4>;
-						iommus = <&apps_smmu 0x1804 0x0>;
-					};
-
-					compute-cb@5 {
-						compatible = "qcom,fastrpc-compute-cb";
-						reg = <5>;
-						iommus = <&apps_smmu 0x1805 0x0>;
-					};
-				};
-			};
-		};
-
 		remoteproc_cdsp: remoteproc@32300000 {
 			compatible = "qcom,sm8450-cdsp-pas";
-			reg = <0 0x32300000 0 0x1400000>;
+			reg = <0 0x32300000 0 0x10000>;
 
 			interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
 					      <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>,
@@ -2907,7 +3093,7 @@
 
 		remoteproc_mpss: remoteproc@4080000 {
 			compatible = "qcom,sm8450-mpss-pas";
-			reg = <0x0 0x04080000 0x0 0x4040>;
+			reg = <0x0 0x04080000 0x0 0x10000>;
 
 			interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>,
 					      <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>,
@@ -4144,6 +4330,546 @@
 			};
 		};
 
+		stm@10002000 {
+			compatible = "arm,coresight-stm", "arm,primecell";
+			reg = <0x0 0x10002000 0x0 0x1000>,
+				<0x0 0x16280000 0x0 0x180000>;
+			reg-names = "stm-base", "stm-stimulus-base";
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			out-ports {
+				port {
+					stm_out_funnel_in0: endpoint {
+						remote-endpoint =
+							<&funnel_in0_in_stm>;
+					};
+				};
+			};
+		};
+
+		funnel@10041000 {
+			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+			reg = <0x0 0x10041000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			in-ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@7 {
+					reg = <7>;
+					funnel_in0_in_stm: endpoint {
+						remote-endpoint =
+							<&stm_out_funnel_in0>;
+					};
+				};
+			};
+
+			out-ports {
+				port {
+					funnel_in0_out_funnel_qdss: endpoint {
+						remote-endpoint =
+							<&funnel_qdss_in_funnel_in0>;
+					};
+				};
+			};
+		};
+
+		funnel@10042000 {
+			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+
+			reg = <0x0 0x10042000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			in-ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@4 {
+					reg = <4>;
+					funnel_in1_in_funnel_apss: endpoint {
+						remote-endpoint =
+							<&funnel_apss_out_funnel_in1>;
+					};
+				};
+
+				port@6 {
+					reg = <6>;
+					funnel_in1_in_funnel_dl_center: endpoint {
+						remote-endpoint =
+							<&funnel_dl_center_out_funnel_in1>;
+					};
+				};
+			};
+
+			out-ports {
+				port {
+					funnel_in1_out_funnel_qdss: endpoint {
+						remote-endpoint =
+							<&funnel_qdss_in_funnel_in1>;
+					};
+				};
+			};
+		};
+
+		funnel@10045000 {
+			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+			reg = <0x0 0x10045000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			in-ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					reg = <0>;
+					funnel_qdss_in_funnel_in0: endpoint {
+						remote-endpoint =
+							<&funnel_in0_out_funnel_qdss>;
+					};
+				};
+
+				port@1 {
+					reg = <1>;
+					funnel_qdss_in_funnel_in1: endpoint {
+						remote-endpoint =
+							<&funnel_in1_out_funnel_qdss>;
+					};
+				};
+			};
+
+			out-ports {
+				port {
+					funnel_qdss_out_funnel_aoss: endpoint {
+						remote-endpoint =
+							<&funnel_aoss_in_funnel_qdss>;
+					};
+				};
+			};
+		};
+
+		replicator@10046000 {
+			compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
+			reg = <0x0 0x10046000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			in-ports {
+				port {
+					replicator_qdss_in_replicator_swao: endpoint {
+						remote-endpoint =
+							<&replicator_swao_out_replicator_qdss>;
+					};
+				};
+			};
+
+			out-ports {
+
+				port {
+					replicator_qdss_out_replicator_etr: endpoint {
+						remote-endpoint =
+							<&replicator_etr_in_replicator_qdss>;
+					};
+				};
+			};
+		};
+
+		tmc_etr: tmc@10048000 {
+			compatible = "arm,coresight-tmc", "arm,primecell";
+			reg = <0x0 0x10048000 0x0 0x1000>;
+
+			iommus = <&apps_smmu 0x0600 0>;
+			arm,buffer-size = <0x10000>;
+
+			arm,scatter-gather;
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			in-ports {
+				port {
+					tmc_etr_in_replicator_etr: endpoint {
+						remote-endpoint =
+							<&replicator_etr_out_tmc_etr>;
+					};
+				};
+			};
+		};
+
+		replicator@1004e000 {
+			compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
+			reg = <0x0 0x1004e000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			in-ports {
+				port {
+					replicator_etr_in_replicator_qdss: endpoint {
+						remote-endpoint =
+							<&replicator_qdss_out_replicator_etr>;
+					};
+				};
+			};
+
+			out-ports {
+
+				port {
+
+					replicator_etr_out_tmc_etr: endpoint {
+						remote-endpoint =
+							<&tmc_etr_in_replicator_etr>;
+					};
+				};
+			};
+		};
+
+		funnel@10b04000 {
+			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+
+			reg = <0x0 0x10b04000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			in-ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@6 {
+					reg = <6>;
+					funnel_aoss_in_tpda_aoss: endpoint {
+						remote-endpoint =
+							<&tpda_aoss_out_funnel_aoss>;
+					};
+				};
+
+				port@7 {
+					reg = <7>;
+					funnel_aoss_in_funnel_qdss: endpoint {
+						remote-endpoint =
+							<&funnel_qdss_out_funnel_aoss>;
+					};
+				};
+			};
+
+			out-ports {
+				port {
+					funnel_aoss_out_tmc_etf: endpoint {
+						remote-endpoint =
+							<&tmc_etf_in_funnel_aoss>;
+					};
+				};
+			};
+		};
+
+		tmc@10b05000 {
+			compatible = "arm,coresight-tmc", "arm,primecell";
+			reg = <0x0 0x10b05000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			in-ports {
+				port {
+					tmc_etf_in_funnel_aoss: endpoint {
+						remote-endpoint =
+							<&funnel_aoss_out_tmc_etf>;
+					};
+				};
+			};
+
+			out-ports {
+				port {
+					tmc_etf_out_replicator_swao: endpoint {
+						remote-endpoint =
+							<&replicator_swao_in_tmc_etf>;
+					};
+				};
+			};
+		};
+
+		replicator@10b06000 {
+			compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
+			reg = <0x0 0x10b06000 0x0 0x1000>;
+
+			qcom,replicator-loses-context;
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			in-ports {
+				port {
+					replicator_swao_in_tmc_etf: endpoint {
+						remote-endpoint =
+							<&tmc_etf_out_replicator_swao>;
+					};
+				};
+			};
+
+			out-ports {
+
+				port {
+					replicator_swao_out_replicator_qdss: endpoint {
+						remote-endpoint =
+							<&replicator_qdss_in_replicator_swao>;
+					};
+				};
+			};
+		};
+
+		tpda@10b08000 {
+			compatible = "qcom,coresight-tpda", "arm,primecell";
+
+			reg = <0x0 0x10b08000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			in-ports {
+
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					reg = <0>;
+					tpda_aoss_in_tpdm_swao_prio_0: endpoint {
+						remote-endpoint =
+							<&tpdm_swao_prio_0_out_tpda_aoss>;
+					};
+				};
+
+				port@4 {
+					reg = <4>;
+					tpda_aoss_in_tpdm_swao: endpoint {
+						remote-endpoint =
+							<&tpdm_swao_out_tpda_aoss>;
+					};
+				};
+			};
+
+			out-ports {
+
+				port {
+					tpda_aoss_out_funnel_aoss: endpoint {
+						remote-endpoint =
+							<&funnel_aoss_in_tpda_aoss>;
+					};
+				};
+			};
+		};
+
+		tpdm@10b09000 {
+			compatible = "qcom,coresight-tpdm", "arm,primecell";
+			reg = <0x0 0x10b09000 0x0 0x1000>;
+
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			out-ports {
+				port {
+					tpdm_swao_prio_0_out_tpda_aoss: endpoint {
+						remote-endpoint =
+							<&tpda_aoss_in_tpdm_swao_prio_0>;
+					};
+				};
+			};
+		};
+
+		tpdm@10b0d000 {
+			compatible = "qcom,coresight-tpdm", "arm,primecell";
+			reg = <0x0 0x10b0d000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			out-ports {
+				port {
+					tpdm_swao_out_tpda_aoss: endpoint {
+						remote-endpoint =
+							<&tpda_aoss_in_tpdm_swao>;
+					};
+				};
+			};
+		};
+
+		tpdm@10c28000 {
+			compatible = "qcom,coresight-tpdm", "arm,primecell";
+			reg = <0x0 0x10c28000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			out-ports {
+				port {
+					tpdm_dlct_out_tpda_dl_center_26: endpoint {
+						remote-endpoint =
+							<&tpda_dl_center_26_in_tpdm_dlct>;
+					};
+				};
+			};
+		};
+
+		tpdm@10c29000 {
+			compatible = "qcom,coresight-tpdm", "arm,primecell";
+			reg = <0x0 0x10c29000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			out-ports {
+				port {
+					tpdm_ipcc_out_tpda_dl_center_27: endpoint {
+						remote-endpoint =
+							<&tpda_dl_center_27_in_tpdm_ipcc>;
+					};
+				};
+			};
+		};
+
+		cti@10c2a000 {
+			compatible = "arm,coresight-cti", "arm,primecell";
+			reg = <0x0 0x10c2a000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+		};
+
+		cti@10c2b000 {
+			compatible = "arm,coresight-cti", "arm,primecell";
+			reg = <0x0 0x10c2b000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+		};
+
+		tpda@10c2e000 {
+			compatible = "qcom,coresight-tpda", "arm,primecell";
+			reg = <0x0 0x10c2e000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			in-ports {
+
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@1a {
+					reg = <26>;
+					tpda_dl_center_26_in_tpdm_dlct: endpoint {
+						remote-endpoint =
+							<&tpdm_dlct_out_tpda_dl_center_26>;
+					};
+				};
+
+				port@1b {
+					reg = <27>;
+					tpda_dl_center_27_in_tpdm_ipcc: endpoint {
+						remote-endpoint =
+							<&tpdm_ipcc_out_tpda_dl_center_27>;
+					};
+				};
+			};
+
+			out-ports {
+
+				port {
+					tpda_dl_center_out_funnel_dl_center: endpoint {
+						remote-endpoint =
+							<&funnel_dl_center_in_tpda_dl_center>;
+					};
+				};
+			};
+		};
+
+		funnel@10c2f000 {
+			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+			reg = <0x0 0x10c2f000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			in-ports {
+
+				port {
+					funnel_dl_center_in_tpda_dl_center: endpoint {
+						remote-endpoint =
+							<&tpda_dl_center_out_funnel_dl_center>;
+					};
+				};
+			};
+
+			out-ports {
+				port {
+					funnel_dl_center_out_funnel_in1: endpoint {
+						remote-endpoint =
+							<&funnel_in1_in_funnel_dl_center>;
+					};
+				};
+			};
+		};
+
+		funnel@13810000 {
+			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+
+			reg = <0x0 0x13810000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			in-ports {
+
+				port {
+					funnel_apss_in_funnel_ete: endpoint {
+						remote-endpoint =
+							<&funnel_ete_out_funnel_apss>;
+					};
+				};
+			};
+
+			out-ports {
+				port {
+					funnel_apss_out_funnel_in1: endpoint {
+						remote-endpoint =
+							<&funnel_in1_in_funnel_apss>;
+					};
+				};
+			};
+		};
+
+		cti@138e0000 {
+			compatible = "arm,coresight-cti", "arm,primecell";
+			reg = <0x0 0x138e0000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+		};
+
+		cti@138f0000 {
+			compatible = "arm,coresight-cti", "arm,primecell";
+			reg = <0x0 0x138f0000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+		};
+
+		cti@13900000 {
+			compatible = "arm,coresight-cti", "arm,primecell";
+			reg = <0x0 0x13900000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+		};
+
 		sram@146aa000 {
 			compatible = "qcom,sm8450-imem", "syscon", "simple-mfd";
 			reg = <0 0x146aa000 0 0x1000>;
@@ -4672,6 +5398,8 @@
 				iommus = <&apps_smmu 0x0 0x0>;
 				snps,dis_u2_susphy_quirk;
 				snps,dis_enblslpm_quirk;
+				snps,dis-u1-entry-quirk;
+				snps,dis-u2-entry-quirk;
 				phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>;
 				phy-names = "usb2-phy", "usb3-phy";
 
diff --git a/dts/upstream/src/arm64/qcom/sm8550-hdk.dts b/dts/upstream/src/arm64/qcom/sm8550-hdk.dts
index 01c92160260..29bc1ddfc7b 100644
--- a/dts/upstream/src/arm64/qcom/sm8550-hdk.dts
+++ b/dts/upstream/src/arm64/qcom/sm8550-hdk.dts
@@ -1172,7 +1172,7 @@
 };
 
 &sleep_clk {
-	clock-frequency = <32000>;
+	clock-frequency = <32764>;
 };
 
 &swr0 {
diff --git a/dts/upstream/src/arm64/qcom/sm8550-mtp.dts b/dts/upstream/src/arm64/qcom/sm8550-mtp.dts
index ab447fc252f..5648ab60ba4 100644
--- a/dts/upstream/src/arm64/qcom/sm8550-mtp.dts
+++ b/dts/upstream/src/arm64/qcom/sm8550-mtp.dts
@@ -825,7 +825,7 @@
 };
 
 &sleep_clk {
-	clock-frequency = <32000>;
+	clock-frequency = <32764>;
 };
 
 &swr0 {
diff --git a/dts/upstream/src/arm64/qcom/sm8550-qrd.dts b/dts/upstream/src/arm64/qcom/sm8550-qrd.dts
index 6052dd922ec..3a6cb279130 100644
--- a/dts/upstream/src/arm64/qcom/sm8550-qrd.dts
+++ b/dts/upstream/src/arm64/qcom/sm8550-qrd.dts
@@ -1005,7 +1005,7 @@
 };
 
 &sleep_clk {
-	clock-frequency = <32000>;
+	clock-frequency = <32764>;
 };
 
 &swr0 {
diff --git a/dts/upstream/src/arm64/qcom/sm8550-samsung-q5q.dts b/dts/upstream/src/arm64/qcom/sm8550-samsung-q5q.dts
index 3c5d8d26704..e8383faac57 100644
--- a/dts/upstream/src/arm64/qcom/sm8550-samsung-q5q.dts
+++ b/dts/upstream/src/arm64/qcom/sm8550-samsung-q5q.dts
@@ -565,7 +565,7 @@
 };
 
 &sleep_clk {
-	clock-frequency = <32000>;
+	clock-frequency = <32764>;
 };
 
 &tlmm {
diff --git a/dts/upstream/src/arm64/qcom/sm8550-sony-xperia-yodo-pdx234.dts b/dts/upstream/src/arm64/qcom/sm8550-sony-xperia-yodo-pdx234.dts
index 85d487ef80a..d90dc7b37c4 100644
--- a/dts/upstream/src/arm64/qcom/sm8550-sony-xperia-yodo-pdx234.dts
+++ b/dts/upstream/src/arm64/qcom/sm8550-sony-xperia-yodo-pdx234.dts
@@ -722,7 +722,7 @@
 };
 
 &sleep_clk {
-	clock-frequency = <32000>;
+	clock-frequency = <32764>;
 };
 
 &tlmm {
diff --git a/dts/upstream/src/arm64/qcom/sm8550.dtsi b/dts/upstream/src/arm64/qcom/sm8550.dtsi
index e7774d32fb6..eac8de4005d 100644
--- a/dts/upstream/src/arm64/qcom/sm8550.dtsi
+++ b/dts/upstream/src/arm64/qcom/sm8550.dtsi
@@ -14,6 +14,7 @@
 #include <dt-bindings/firmware/qcom,scm.h>
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/interconnect/qcom,icc.h>
 #include <dt-bindings/interconnect/qcom,sm8550-rpmh.h>
 #include <dt-bindings/mailbox/qcom-ipcc.h>
 #include <dt-bindings/power/qcom-rpmpd.h>
@@ -1734,7 +1735,8 @@
 				     <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
+				     <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-names = "msi0",
 					  "msi1",
 					  "msi2",
@@ -1742,7 +1744,8 @@
 					  "msi4",
 					  "msi5",
 					  "msi6",
-					  "msi7";
+					  "msi7",
+					  "global";
 			#interrupt-cells = <1>;
 			interrupt-map-mask = <0 0 0 0x7>;
 			interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
@@ -1850,7 +1853,8 @@
 				     <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
+				     <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-names = "msi0",
 					  "msi1",
 					  "msi2",
@@ -1858,7 +1862,8 @@
 					  "msi4",
 					  "msi5",
 					  "msi6",
-					  "msi7";
+					  "msi7",
+					  "global";
 			#interrupt-cells = <1>;
 			interrupt-map-mask = <0 0 0 0x7>;
 			interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
@@ -2114,6 +2119,10 @@
 			qcom,gmu = <&gmu>;
 			#cooling-cells = <2>;
 
+			interconnects = <&gem_noc MASTER_GFX3D QCOM_ICC_TAG_ALWAYS
+					 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+			interconnect-names = "gfx-mem";
+
 			status = "disabled";
 
 			zap-shader {
@@ -2127,41 +2136,49 @@
 				opp-680000000 {
 					opp-hz = /bits/ 64 <680000000>;
 					opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
+					opp-peak-kBps = <16500000>;
 				};
 
 				opp-615000000 {
 					opp-hz = /bits/ 64 <615000000>;
 					opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
+					opp-peak-kBps = <12449218>;
 				};
 
 				opp-550000000 {
 					opp-hz = /bits/ 64 <550000000>;
 					opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
+					opp-peak-kBps = <10687500>;
 				};
 
 				opp-475000000 {
 					opp-hz = /bits/ 64 <475000000>;
 					opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>;
+					opp-peak-kBps = <6074218>;
 				};
 
 				opp-401000000 {
 					opp-hz = /bits/ 64 <401000000>;
 					opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
+					opp-peak-kBps = <6074218>;
 				};
 
 				opp-348000000 {
 					opp-hz = /bits/ 64 <348000000>;
 					opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>;
+					opp-peak-kBps = <6074218>;
 				};
 
 				opp-295000000 {
 					opp-hz = /bits/ 64 <295000000>;
 					opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
+					opp-peak-kBps = <6074218>;
 				};
 
 				opp-220000000 {
 					opp-hz = /bits/ 64 <220000000>;
 					opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>;
+					opp-peak-kBps = <2136718>;
 				};
 			};
 		};
@@ -2314,7 +2331,7 @@
 
 		remoteproc_mpss: remoteproc@4080000 {
 			compatible = "qcom,sm8550-mpss-pas";
-			reg = <0x0 0x04080000 0x0 0x4040>;
+			reg = <0x0 0x04080000 0x0 0x10000>;
 
 			interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>,
 					      <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>,
@@ -2354,6 +2371,137 @@
 			};
 		};
 
+		remoteproc_adsp: remoteproc@6800000 {
+			compatible = "qcom,sm8550-adsp-pas";
+			reg = <0x0 0x06800000 0x0 0x10000>;
+
+			interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>,
+					      <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
+					      <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
+					      <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
+					      <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>;
+			interrupt-names = "wdog", "fatal", "ready",
+					  "handover", "stop-ack";
+
+			clocks = <&rpmhcc RPMH_CXO_CLK>;
+			clock-names = "xo";
+
+			power-domains = <&rpmhpd RPMHPD_LCX>,
+					<&rpmhpd RPMHPD_LMX>;
+			power-domain-names = "lcx", "lmx";
+
+			interconnects = <&lpass_lpicx_noc MASTER_LPASS_PROC 0 &mc_virt SLAVE_EBI1 0>;
+
+			memory-region = <&adspslpi_mem>, <&q6_adsp_dtb_mem>;
+
+			qcom,qmp = <&aoss_qmp>;
+
+			qcom,smem-states = <&smp2p_adsp_out 0>;
+			qcom,smem-state-names = "stop";
+
+			status = "disabled";
+
+			remoteproc_adsp_glink: glink-edge {
+				interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
+							     IPCC_MPROC_SIGNAL_GLINK_QMP
+							     IRQ_TYPE_EDGE_RISING>;
+				mboxes = <&ipcc IPCC_CLIENT_LPASS
+						IPCC_MPROC_SIGNAL_GLINK_QMP>;
+
+				label = "lpass";
+				qcom,remote-pid = <2>;
+
+				fastrpc {
+					compatible = "qcom,fastrpc";
+					qcom,glink-channels = "fastrpcglink-apps-dsp";
+					label = "adsp";
+					qcom,non-secure-domain;
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					compute-cb@3 {
+						compatible = "qcom,fastrpc-compute-cb";
+						reg = <3>;
+						iommus = <&apps_smmu 0x1003 0x80>,
+							 <&apps_smmu 0x1063 0x0>;
+						dma-coherent;
+					};
+
+					compute-cb@4 {
+						compatible = "qcom,fastrpc-compute-cb";
+						reg = <4>;
+						iommus = <&apps_smmu 0x1004 0x80>,
+							 <&apps_smmu 0x1064 0x0>;
+						dma-coherent;
+					};
+
+					compute-cb@5 {
+						compatible = "qcom,fastrpc-compute-cb";
+						reg = <5>;
+						iommus = <&apps_smmu 0x1005 0x80>,
+							 <&apps_smmu 0x1065 0x0>;
+						dma-coherent;
+					};
+
+					compute-cb@6 {
+						compatible = "qcom,fastrpc-compute-cb";
+						reg = <6>;
+						iommus = <&apps_smmu 0x1006 0x80>,
+							 <&apps_smmu 0x1066 0x0>;
+						dma-coherent;
+					};
+
+					compute-cb@7 {
+						compatible = "qcom,fastrpc-compute-cb";
+						reg = <7>;
+						iommus = <&apps_smmu 0x1007 0x80>,
+							 <&apps_smmu 0x1067 0x0>;
+						dma-coherent;
+					};
+				};
+
+				gpr {
+					compatible = "qcom,gpr";
+					qcom,glink-channels = "adsp_apps";
+					qcom,domain = <GPR_DOMAIN_ID_ADSP>;
+					qcom,intents = <512 20>;
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					q6apm: service@1 {
+						compatible = "qcom,q6apm";
+						reg = <GPR_APM_MODULE_IID>;
+						#sound-dai-cells = <0>;
+						qcom,protection-domain = "avs/audio",
+									 "msm/adsp/audio_pd";
+
+						q6apmdai: dais {
+							compatible = "qcom,q6apm-dais";
+							iommus = <&apps_smmu 0x1001 0x80>,
+								 <&apps_smmu 0x1061 0x0>;
+						};
+
+						q6apmbedai: bedais {
+							compatible = "qcom,q6apm-lpass-dais";
+							#sound-dai-cells = <1>;
+						};
+					};
+
+					q6prm: service@2 {
+						compatible = "qcom,q6prm";
+						reg = <GPR_PRM_MODULE_IID>;
+						qcom,protection-domain = "avs/audio",
+									 "msm/adsp/audio_pd";
+
+						q6prmcc: clock-controller {
+							compatible = "qcom,q6prm-lpass-clocks";
+							#clock-cells = <2>;
+						};
+					};
+				};
+			};
+		};
+
 		lpass_wsa2macro: codec@6aa0000 {
 			compatible = "qcom,sm8550-lpass-wsa-macro";
 			reg = <0 0x06aa0000 0 0x1000>;
@@ -2872,9 +3020,8 @@
 
 			power-domains = <&dispcc MDSS_GDSC>;
 
-			interconnects = <&mmss_noc MASTER_MDP 0 &gem_noc SLAVE_LLCC 0>,
-					<&mc_virt MASTER_LLCC 0 &mc_virt SLAVE_EBI1 0>;
-			interconnect-names = "mdp0-mem", "mdp1-mem";
+			interconnects = <&mmss_noc MASTER_MDP 0 &mc_virt SLAVE_EBI1 0>;
+			interconnect-names = "mdp0-mem";
 
 			iommus = <&apps_smmu 0x1c00 0x2>;
 
@@ -4576,137 +4723,6 @@
 			interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
 		};
 
-		remoteproc_adsp: remoteproc@30000000 {
-			compatible = "qcom,sm8550-adsp-pas";
-			reg = <0x0 0x30000000 0x0 0x100>;
-
-			interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>,
-					      <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
-					      <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
-					      <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
-					      <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>;
-			interrupt-names = "wdog", "fatal", "ready",
-					  "handover", "stop-ack";
-
-			clocks = <&rpmhcc RPMH_CXO_CLK>;
-			clock-names = "xo";
-
-			power-domains = <&rpmhpd RPMHPD_LCX>,
-					<&rpmhpd RPMHPD_LMX>;
-			power-domain-names = "lcx", "lmx";
-
-			interconnects = <&lpass_lpicx_noc MASTER_LPASS_PROC 0 &mc_virt SLAVE_EBI1 0>;
-
-			memory-region = <&adspslpi_mem>, <&q6_adsp_dtb_mem>;
-
-			qcom,qmp = <&aoss_qmp>;
-
-			qcom,smem-states = <&smp2p_adsp_out 0>;
-			qcom,smem-state-names = "stop";
-
-			status = "disabled";
-
-			remoteproc_adsp_glink: glink-edge {
-				interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
-							     IPCC_MPROC_SIGNAL_GLINK_QMP
-							     IRQ_TYPE_EDGE_RISING>;
-				mboxes = <&ipcc IPCC_CLIENT_LPASS
-						IPCC_MPROC_SIGNAL_GLINK_QMP>;
-
-				label = "lpass";
-				qcom,remote-pid = <2>;
-
-				fastrpc {
-					compatible = "qcom,fastrpc";
-					qcom,glink-channels = "fastrpcglink-apps-dsp";
-					label = "adsp";
-					qcom,non-secure-domain;
-					#address-cells = <1>;
-					#size-cells = <0>;
-
-					compute-cb@3 {
-						compatible = "qcom,fastrpc-compute-cb";
-						reg = <3>;
-						iommus = <&apps_smmu 0x1003 0x80>,
-							 <&apps_smmu 0x1063 0x0>;
-						dma-coherent;
-					};
-
-					compute-cb@4 {
-						compatible = "qcom,fastrpc-compute-cb";
-						reg = <4>;
-						iommus = <&apps_smmu 0x1004 0x80>,
-							 <&apps_smmu 0x1064 0x0>;
-						dma-coherent;
-					};
-
-					compute-cb@5 {
-						compatible = "qcom,fastrpc-compute-cb";
-						reg = <5>;
-						iommus = <&apps_smmu 0x1005 0x80>,
-							 <&apps_smmu 0x1065 0x0>;
-						dma-coherent;
-					};
-
-					compute-cb@6 {
-						compatible = "qcom,fastrpc-compute-cb";
-						reg = <6>;
-						iommus = <&apps_smmu 0x1006 0x80>,
-							 <&apps_smmu 0x1066 0x0>;
-						dma-coherent;
-					};
-
-					compute-cb@7 {
-						compatible = "qcom,fastrpc-compute-cb";
-						reg = <7>;
-						iommus = <&apps_smmu 0x1007 0x80>,
-							 <&apps_smmu 0x1067 0x0>;
-						dma-coherent;
-					};
-				};
-
-				gpr {
-					compatible = "qcom,gpr";
-					qcom,glink-channels = "adsp_apps";
-					qcom,domain = <GPR_DOMAIN_ID_ADSP>;
-					qcom,intents = <512 20>;
-					#address-cells = <1>;
-					#size-cells = <0>;
-
-					q6apm: service@1 {
-						compatible = "qcom,q6apm";
-						reg = <GPR_APM_MODULE_IID>;
-						#sound-dai-cells = <0>;
-						qcom,protection-domain = "avs/audio",
-									 "msm/adsp/audio_pd";
-
-						q6apmdai: dais {
-							compatible = "qcom,q6apm-dais";
-							iommus = <&apps_smmu 0x1001 0x80>,
-								 <&apps_smmu 0x1061 0x0>;
-						};
-
-						q6apmbedai: bedais {
-							compatible = "qcom,q6apm-lpass-dais";
-							#sound-dai-cells = <1>;
-						};
-					};
-
-					q6prm: service@2 {
-						compatible = "qcom,q6prm";
-						reg = <GPR_PRM_MODULE_IID>;
-						qcom,protection-domain = "avs/audio",
-									 "msm/adsp/audio_pd";
-
-						q6prmcc: clock-controller {
-							compatible = "qcom,q6prm-lpass-clocks";
-							#clock-cells = <2>;
-						};
-					};
-				};
-			};
-		};
-
 		nsp_noc: interconnect@320c0000 {
 			compatible = "qcom,sm8550-nsp-noc";
 			reg = <0 0x320c0000 0 0xe080>;
@@ -4716,7 +4732,7 @@
 
 		remoteproc_cdsp: remoteproc@32300000 {
 			compatible = "qcom,sm8550-cdsp-pas";
-			reg = <0x0 0x32300000 0x0 0x1400000>;
+			reg = <0x0 0x32300000 0x0 0x10000>;
 
 			interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
 					      <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>,
diff --git a/dts/upstream/src/arm64/qcom/sm8650-hdk.dts b/dts/upstream/src/arm64/qcom/sm8650-hdk.dts
index f00bdff4280..d0912735b54 100644
--- a/dts/upstream/src/arm64/qcom/sm8650-hdk.dts
+++ b/dts/upstream/src/arm64/qcom/sm8650-hdk.dts
@@ -1113,7 +1113,7 @@
 };
 
 &sleep_clk {
-	clock-frequency = <32000>;
+	clock-frequency = <32764>;
 };
 
 &swr0 {
diff --git a/dts/upstream/src/arm64/qcom/sm8650-mtp.dts b/dts/upstream/src/arm64/qcom/sm8650-mtp.dts
index 0db2cb03f25..76ef43c10f7 100644
--- a/dts/upstream/src/arm64/qcom/sm8650-mtp.dts
+++ b/dts/upstream/src/arm64/qcom/sm8650-mtp.dts
@@ -730,7 +730,7 @@
 };
 
 &sleep_clk {
-	clock-frequency = <32000>;
+	clock-frequency = <32764>;
 };
 
 &swr0 {
diff --git a/dts/upstream/src/arm64/qcom/sm8650-qrd.dts b/dts/upstream/src/arm64/qcom/sm8650-qrd.dts
index c5e8c3c2df9..71033fba21b 100644
--- a/dts/upstream/src/arm64/qcom/sm8650-qrd.dts
+++ b/dts/upstream/src/arm64/qcom/sm8650-qrd.dts
@@ -1041,7 +1041,7 @@
 };
 
 &sleep_clk {
-	clock-frequency = <32000>;
+	clock-frequency = <32764>;
 };
 
 &spi4 {
diff --git a/dts/upstream/src/arm64/qcom/sm8650.dtsi b/dts/upstream/src/arm64/qcom/sm8650.dtsi
index 25e47505adc..86684cb9a93 100644
--- a/dts/upstream/src/arm64/qcom/sm8650.dtsi
+++ b/dts/upstream/src/arm64/qcom/sm8650.dtsi
@@ -365,6 +365,40 @@
 		};
 	};
 
+	ete0 {
+		compatible = "arm,embedded-trace-extension";
+
+		cpu = <&cpu0>;
+
+		out-ports {
+			port {
+				ete0_out_funnel_ete: endpoint {
+					remote-endpoint = <&funnel_ete_in_ete0>;
+				};
+			};
+		};
+	};
+
+	funnel-ete {
+		compatible = "arm,coresight-static-funnel";
+
+		in-ports {
+			port {
+				funnel_ete_in_ete0: endpoint {
+					remote-endpoint = <&ete0_out_funnel_ete>;
+				};
+			};
+		};
+
+		out-ports {
+			port {
+				funnel_ete_out_funnel_apss: endpoint {
+					remote-endpoint = <&funnel_apss_in_funnel_ete>;
+				};
+			};
+		};
+	};
+
 	firmware {
 		scm: scm {
 			compatible = "qcom,scm-sm8650", "qcom,scm";
@@ -2233,7 +2267,8 @@
 				     <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
+				     <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-names = "msi0",
 					  "msi1",
 					  "msi2",
@@ -2241,7 +2276,8 @@
 					  "msi4",
 					  "msi5",
 					  "msi6",
-					  "msi7";
+					  "msi7",
+					  "global";
 
 			clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
 				 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
@@ -2365,7 +2401,8 @@
 				     <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
+				     <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-names = "msi0",
 					  "msi1",
 					  "msi2",
@@ -2373,7 +2410,8 @@
 					  "msi4",
 					  "msi5",
 					  "msi6",
-					  "msi7";
+					  "msi7",
+					  "global";
 
 			clocks = <&gcc GCC_PCIE_1_AUX_CLK>,
 				 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
@@ -2636,6 +2674,10 @@
 			qcom,gmu = <&gmu>;
 			#cooling-cells = <2>;
 
+			interconnects = <&gem_noc MASTER_GFX3D QCOM_ICC_TAG_ALWAYS
+					 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+			interconnect-names = "gfx-mem";
+
 			status = "disabled";
 
 			zap-shader {
@@ -2649,56 +2691,67 @@
 				opp-231000000 {
 					opp-hz = /bits/ 64 <231000000>;
 					opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>;
+					opp-peak-kBps = <2136718>;
 				};
 
 				opp-310000000 {
 					opp-hz = /bits/ 64 <310000000>;
 					opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
+					opp-peak-kBps = <2136718>;
 				};
 
 				opp-366000000 {
 					opp-hz = /bits/ 64 <366000000>;
 					opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>;
+					opp-peak-kBps = <6074218>;
 				};
 
 				opp-422000000 {
 					opp-hz = /bits/ 64 <422000000>;
 					opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
+					opp-peak-kBps = <8171875>;
 				};
 
 				opp-500000000 {
 					opp-hz = /bits/ 64 <500000000>;
 					opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>;
+					opp-peak-kBps = <8171875>;
 				};
 
 				opp-578000000 {
 					opp-hz = /bits/ 64 <578000000>;
 					opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
+					opp-peak-kBps = <8171875>;
 				};
 
 				opp-629000000 {
 					opp-hz = /bits/ 64 <629000000>;
 					opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
+					opp-peak-kBps = <10687500>;
 				};
 
 				opp-680000000 {
 					opp-hz = /bits/ 64 <680000000>;
 					opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
+					opp-peak-kBps = <12449218>;
 				};
 
 				opp-720000000 {
 					opp-hz = /bits/ 64 <720000000>;
 					opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
+					opp-peak-kBps = <12449218>;
 				};
 
 				opp-770000000 {
 					opp-hz = /bits/ 64 <770000000>;
 					opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
+					opp-peak-kBps = <12449218>;
 				};
 
 				opp-834000000 {
 					opp-hz = /bits/ 64 <834000000>;
 					opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
+					opp-peak-kBps = <14398437>;
 				};
 			};
 		};
@@ -2853,7 +2906,7 @@
 
 		remoteproc_mpss: remoteproc@4080000 {
 			compatible = "qcom,sm8650-mpss-pas";
-			reg = <0 0x04080000 0 0x4040>;
+			reg = <0x0 0x04080000 0x0 0x10000>;
 
 			interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>,
 					      <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>,
@@ -2904,6 +2957,154 @@
 			};
 		};
 
+		remoteproc_adsp: remoteproc@6800000 {
+			compatible = "qcom,sm8650-adsp-pas";
+			reg = <0x0 0x06800000 0x0 0x10000>;
+
+			interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>,
+					      <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
+					      <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
+					      <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
+					      <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>;
+			interrupt-names = "wdog",
+					  "fatal",
+					  "ready",
+					  "handover",
+					  "stop-ack";
+
+			clocks = <&rpmhcc RPMH_CXO_CLK>;
+			clock-names = "xo";
+
+			interconnects = <&lpass_lpicx_noc MASTER_LPASS_PROC QCOM_ICC_TAG_ALWAYS
+					 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+
+			power-domains = <&rpmhpd RPMHPD_LCX>,
+					<&rpmhpd RPMHPD_LMX>;
+			power-domain-names = "lcx",
+					     "lmx";
+
+			memory-region = <&adspslpi_mem>, <&q6_adsp_dtb_mem>;
+
+			qcom,qmp = <&aoss_qmp>;
+
+			qcom,smem-states = <&smp2p_adsp_out 0>;
+			qcom,smem-state-names = "stop";
+
+			status = "disabled";
+
+			remoteproc_adsp_glink: glink-edge {
+				interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
+							     IPCC_MPROC_SIGNAL_GLINK_QMP
+							     IRQ_TYPE_EDGE_RISING>;
+
+				mboxes = <&ipcc IPCC_CLIENT_LPASS
+						IPCC_MPROC_SIGNAL_GLINK_QMP>;
+
+				qcom,remote-pid = <2>;
+
+				label = "lpass";
+
+				fastrpc {
+					compatible = "qcom,fastrpc";
+
+					qcom,glink-channels = "fastrpcglink-apps-dsp";
+
+					label = "adsp";
+
+					qcom,non-secure-domain;
+
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					compute-cb@3 {
+						compatible = "qcom,fastrpc-compute-cb";
+						reg = <3>;
+
+						iommus = <&apps_smmu 0x1003 0x80>,
+							 <&apps_smmu 0x1043 0x20>;
+						dma-coherent;
+					};
+
+					compute-cb@4 {
+						compatible = "qcom,fastrpc-compute-cb";
+						reg = <4>;
+
+						iommus = <&apps_smmu 0x1004 0x80>,
+							 <&apps_smmu 0x1044 0x20>;
+						dma-coherent;
+					};
+
+					compute-cb@5 {
+						compatible = "qcom,fastrpc-compute-cb";
+						reg = <5>;
+
+						iommus = <&apps_smmu 0x1005 0x80>,
+							 <&apps_smmu 0x1045 0x20>;
+						dma-coherent;
+					};
+
+					compute-cb@6 {
+						compatible = "qcom,fastrpc-compute-cb";
+						reg = <6>;
+
+						iommus = <&apps_smmu 0x1006 0x80>,
+							 <&apps_smmu 0x1046 0x20>;
+						dma-coherent;
+					};
+
+					compute-cb@7 {
+						compatible = "qcom,fastrpc-compute-cb";
+						reg = <7>;
+
+						iommus = <&apps_smmu 0x1007 0x40>,
+							 <&apps_smmu 0x1067 0x0>,
+							 <&apps_smmu 0x1087 0x0>;
+						dma-coherent;
+					};
+				};
+
+				gpr {
+					compatible = "qcom,gpr";
+					qcom,glink-channels = "adsp_apps";
+					qcom,domain = <GPR_DOMAIN_ID_ADSP>;
+					qcom,intents = <512 20>;
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					q6apm: service@1 {
+						compatible = "qcom,q6apm";
+						reg = <GPR_APM_MODULE_IID>;
+						#sound-dai-cells = <0>;
+						qcom,protection-domain = "avs/audio",
+									 "msm/adsp/audio_pd";
+
+						q6apmbedai: bedais {
+							compatible = "qcom,q6apm-lpass-dais";
+							#sound-dai-cells = <1>;
+						};
+
+						q6apmdai: dais {
+							compatible = "qcom,q6apm-dais";
+							iommus = <&apps_smmu 0x1001 0x80>,
+								 <&apps_smmu 0x1061 0x0>;
+						};
+					};
+
+					q6prm: service@2 {
+						compatible = "qcom,q6prm";
+						reg = <GPR_PRM_MODULE_IID>;
+						qcom,protection-domain = "avs/audio",
+									 "msm/adsp/audio_pd";
+
+						q6prmcc: clock-controller {
+							compatible = "qcom,q6prm-lpass-clocks";
+							#clock-cells = <2>;
+						};
+					};
+				};
+			};
+		};
+
 		lpass_wsa2macro: codec@6aa0000 {
 			compatible = "qcom,sm8650-lpass-wsa-macro", "qcom,sm8550-lpass-wsa-macro";
 			reg = <0 0x06aa0000 0 0x1000>;
@@ -3455,11 +3656,8 @@
 			resets = <&dispcc DISP_CC_MDSS_CORE_BCR>;
 
 			interconnects = <&mmss_noc MASTER_MDP QCOM_ICC_TAG_ALWAYS
-					 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>,
-					<&mc_virt MASTER_LLCC QCOM_ICC_TAG_ALWAYS
 					 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
-			interconnect-names = "mdp0-mem",
-					     "mdp1-mem";
+			interconnect-names = "mdp0-mem";
 
 			power-domains = <&dispcc MDSS_GDSC>;
 
@@ -4854,6 +5052,138 @@
 			};
 		};
 
+		funnel@10042000 {
+			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+
+			reg = <0x0 0x10042000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			in-ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@4 {
+					reg = <4>;
+
+					funnel_in1_in_funnel_apss: endpoint {
+						remote-endpoint = <&funnel_apss_out_funnel_in1>;
+					};
+				};
+			};
+
+			out-ports {
+				port {
+					funnel_in1_out_funnel_qdss: endpoint {
+						remote-endpoint = <&funnel_qdss_in_funnel_in1>;
+					};
+				};
+			};
+		};
+
+		funnel@10045000 {
+			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+
+			reg = <0x0 0x10045000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			in-ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@1 {
+					reg = <1>;
+
+					funnel_qdss_in_funnel_in1: endpoint {
+						remote-endpoint = <&funnel_in1_out_funnel_qdss>;
+					};
+				};
+			};
+
+			out-ports {
+				port {
+					funnel_qdss_out_funnel_aoss: endpoint {
+						remote-endpoint = <&funnel_aoss_in_funnel_qdss>;
+					};
+				};
+			};
+		};
+
+		funnel@10b04000 {
+			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+
+			reg = <0x0 0x10b04000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			in-ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@7 {
+					reg = <7>;
+
+					funnel_aoss_in_funnel_qdss: endpoint {
+						remote-endpoint = <&funnel_qdss_out_funnel_aoss>;
+					};
+				};
+			};
+
+			out-ports {
+				port {
+					funnel_aoss_out_tmc_etf: endpoint {
+						remote-endpoint = <&tmc_etf_in_funnel_aoss>;
+					};
+				};
+			};
+		};
+
+		tmc@10b05000 {
+			compatible = "arm,coresight-tmc", "arm,primecell";
+
+			reg = <0x0 0x10b05000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			in-ports {
+				port {
+					tmc_etf_in_funnel_aoss: endpoint {
+						remote-endpoint = <&funnel_aoss_out_tmc_etf>;
+					};
+				};
+			};
+		};
+
+		funnel@13810000 {
+			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+
+			reg = <0x0 0x13810000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			in-ports {
+				port {
+					funnel_apss_in_funnel_ete: endpoint {
+						remote-endpoint = <&funnel_ete_out_funnel_apss>;
+					};
+				};
+			};
+
+			out-ports {
+				port {
+					funnel_apss_out_funnel_in1: endpoint {
+						remote-endpoint = <&funnel_in1_in_funnel_apss>;
+					};
+				};
+			};
+		};
+
 		apps_smmu: iommu@15000000 {
 			compatible = "qcom,sm8650-smmu-500", "qcom,smmu-500", "arm,mmu-500";
 			reg = <0 0x15000000 0 0x100000>;
@@ -5322,154 +5652,6 @@
 			interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
 		};
 
-		remoteproc_adsp: remoteproc@30000000 {
-			compatible = "qcom,sm8650-adsp-pas";
-			reg = <0 0x30000000 0 0x100>;
-
-			interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>,
-					      <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
-					      <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
-					      <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
-					      <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>;
-			interrupt-names = "wdog",
-					  "fatal",
-					  "ready",
-					  "handover",
-					  "stop-ack";
-
-			clocks = <&rpmhcc RPMH_CXO_CLK>;
-			clock-names = "xo";
-
-			interconnects = <&lpass_lpicx_noc MASTER_LPASS_PROC QCOM_ICC_TAG_ALWAYS
-					 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
-
-			power-domains = <&rpmhpd RPMHPD_LCX>,
-					<&rpmhpd RPMHPD_LMX>;
-			power-domain-names = "lcx",
-					     "lmx";
-
-			memory-region = <&adspslpi_mem>, <&q6_adsp_dtb_mem>;
-
-			qcom,qmp = <&aoss_qmp>;
-
-			qcom,smem-states = <&smp2p_adsp_out 0>;
-			qcom,smem-state-names = "stop";
-
-			status = "disabled";
-
-			remoteproc_adsp_glink: glink-edge {
-				interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
-							     IPCC_MPROC_SIGNAL_GLINK_QMP
-							     IRQ_TYPE_EDGE_RISING>;
-
-				mboxes = <&ipcc IPCC_CLIENT_LPASS
-						IPCC_MPROC_SIGNAL_GLINK_QMP>;
-
-				qcom,remote-pid = <2>;
-
-				label = "lpass";
-
-				fastrpc {
-					compatible = "qcom,fastrpc";
-
-					qcom,glink-channels = "fastrpcglink-apps-dsp";
-
-					label = "adsp";
-
-					qcom,non-secure-domain;
-
-					#address-cells = <1>;
-					#size-cells = <0>;
-
-					compute-cb@3 {
-						compatible = "qcom,fastrpc-compute-cb";
-						reg = <3>;
-
-						iommus = <&apps_smmu 0x1003 0x80>,
-							 <&apps_smmu 0x1043 0x20>;
-						dma-coherent;
-					};
-
-					compute-cb@4 {
-						compatible = "qcom,fastrpc-compute-cb";
-						reg = <4>;
-
-						iommus = <&apps_smmu 0x1004 0x80>,
-							 <&apps_smmu 0x1044 0x20>;
-						dma-coherent;
-					};
-
-					compute-cb@5 {
-						compatible = "qcom,fastrpc-compute-cb";
-						reg = <5>;
-
-						iommus = <&apps_smmu 0x1005 0x80>,
-							 <&apps_smmu 0x1045 0x20>;
-						dma-coherent;
-					};
-
-					compute-cb@6 {
-						compatible = "qcom,fastrpc-compute-cb";
-						reg = <6>;
-
-						iommus = <&apps_smmu 0x1006 0x80>,
-							 <&apps_smmu 0x1046 0x20>;
-						dma-coherent;
-					};
-
-					compute-cb@7 {
-						compatible = "qcom,fastrpc-compute-cb";
-						reg = <7>;
-
-						iommus = <&apps_smmu 0x1007 0x40>,
-							 <&apps_smmu 0x1067 0x0>,
-							 <&apps_smmu 0x1087 0x0>;
-						dma-coherent;
-					};
-				};
-
-				gpr {
-					compatible = "qcom,gpr";
-					qcom,glink-channels = "adsp_apps";
-					qcom,domain = <GPR_DOMAIN_ID_ADSP>;
-					qcom,intents = <512 20>;
-					#address-cells = <1>;
-					#size-cells = <0>;
-
-					q6apm: service@1 {
-						compatible = "qcom,q6apm";
-						reg = <GPR_APM_MODULE_IID>;
-						#sound-dai-cells = <0>;
-						qcom,protection-domain = "avs/audio",
-									 "msm/adsp/audio_pd";
-
-						q6apmbedai: bedais {
-							compatible = "qcom,q6apm-lpass-dais";
-							#sound-dai-cells = <1>;
-						};
-
-						q6apmdai: dais {
-							compatible = "qcom,q6apm-dais";
-							iommus = <&apps_smmu 0x1001 0x80>,
-								 <&apps_smmu 0x1061 0x0>;
-						};
-					};
-
-					q6prm: service@2 {
-						compatible = "qcom,q6prm";
-						reg = <GPR_PRM_MODULE_IID>;
-						qcom,protection-domain = "avs/audio",
-									 "msm/adsp/audio_pd";
-
-						q6prmcc: clock-controller {
-							compatible = "qcom,q6prm-lpass-clocks";
-							#clock-cells = <2>;
-						};
-					};
-				};
-			};
-		};
-
 		nsp_noc: interconnect@320c0000 {
 			compatible = "qcom,sm8650-nsp-noc";
 			reg = <0 0x320c0000 0 0xf080>;
@@ -5481,7 +5663,7 @@
 
 		remoteproc_cdsp: remoteproc@32300000 {
 			compatible = "qcom,sm8650-cdsp-pas";
-			reg = <0 0x32300000 0 0x1400000>;
+			reg = <0x0 0x32300000 0x0 0x10000>;
 
 			interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
 					      <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>,
@@ -5622,7 +5804,7 @@
 
 					/* note: secure cb9 in downstream */
 
-					compute-cb@10 {
+					compute-cb@12 {
 						compatible = "qcom,fastrpc-compute-cb";
 						reg = <12>;
 
@@ -5632,7 +5814,7 @@
 						dma-coherent;
 					};
 
-					compute-cb@11 {
+					compute-cb@13 {
 						compatible = "qcom,fastrpc-compute-cb";
 						reg = <13>;
 
@@ -5642,7 +5824,7 @@
 						dma-coherent;
 					};
 
-					compute-cb@12 {
+					compute-cb@14 {
 						compatible = "qcom,fastrpc-compute-cb";
 						reg = <14>;
 
diff --git a/dts/upstream/src/arm64/qcom/sm8750-mtp.dts b/dts/upstream/src/arm64/qcom/sm8750-mtp.dts
new file mode 100644
index 00000000000..9e3aacad7bd
--- /dev/null
+++ b/dts/upstream/src/arm64/qcom/sm8750-mtp.dts
@@ -0,0 +1,794 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
+#include "sm8750.dtsi"
+#include "pm8010.dtsi"
+#include "pm8550.dtsi"
+#define PMK8550VE_SID 8
+#include "pm8550ve.dtsi"
+#include "pmd8028.dtsi"
+#include "pmih0108.dtsi"
+#include "pmk8550.dtsi"
+#include "pmr735d_a.dtsi"
+#include "sm8750-pmics.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. SM8750 MTP";
+	compatible = "qcom,sm8750-mtp", "qcom,sm8750";
+	chassis-type = "handset";
+
+
+	aliases {
+		serial0 = &uart7;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	clocks {
+		xo_board: xo-board {
+			compatible = "fixed-clock";
+			clock-frequency = <76800000>;
+			#clock-cells = <0>;
+		};
+
+		sleep_clk: sleep-clk {
+			compatible = "fixed-clock";
+			clock-frequency = <32000>;
+			#clock-cells = <0>;
+		};
+
+		bi_tcxo_div2: bi-tcxo-div2-clk {
+			compatible = "fixed-factor-clock";
+			#clock-cells = <0>;
+
+			clocks = <&rpmhcc RPMH_CXO_CLK>;
+			clock-mult = <1>;
+			clock-div = <2>;
+		};
+
+		bi_tcxo_ao_div2: bi-tcxo-ao-div2-clk {
+			compatible = "fixed-factor-clock";
+			#clock-cells = <0>;
+
+			clocks = <&rpmhcc RPMH_CXO_CLK_A>;
+			clock-mult = <1>;
+			clock-div = <2>;
+		};
+	};
+
+	gpio-keys {
+		compatible = "gpio-keys";
+
+		pinctrl-0 = <&volume_up_n>;
+		pinctrl-names = "default";
+
+		key-volume-up {
+			label = "Volume Up";
+			linux,code = <KEY_VOLUMEUP>;
+			gpios = <&pm8550_gpios 6 GPIO_ACTIVE_LOW>;
+			debounce-interval = <15>;
+			linux,can-disable;
+			wakeup-source;
+		};
+	};
+
+	vph_pwr: vph-pwr-regulator {
+		compatible = "regulator-fixed";
+
+		regulator-name = "vph_pwr";
+		regulator-min-microvolt = <3700000>;
+		regulator-max-microvolt = <3700000>;
+
+		regulator-always-on;
+		regulator-boot-on;
+	};
+};
+
+&apps_rsc {
+	regulators-0 {
+		compatible = "qcom,pm8550-rpmh-regulators";
+
+		vdd-bob1-supply = <&vph_pwr>;
+		vdd-bob2-supply = <&vph_pwr>;
+		vdd-l1-l4-l10-supply = <&vreg_s3g_1p8>;
+		vdd-l2-l13-l14-supply = <&vreg_bob1>;
+		vdd-l3-supply = <&vreg_s7i_1p2>;
+		vdd-l5-l16-supply = <&vreg_bob1>;
+		vdd-l6-l7-supply = <&vreg_bob1>;
+		vdd-l8-l9-supply = <&vreg_bob1>;
+		vdd-l11-supply = <&vreg_s7i_1p2>;
+		vdd-l12-supply = <&vreg_s3g_1p8>;
+		vdd-l15-supply = <&vreg_s3g_1p8>;
+		vdd-l17-supply = <&vreg_bob2>;
+
+		qcom,pmic-id = "b";
+
+		vreg_bob1: bob1 {
+			regulator-name = "vreg_bob1";
+			regulator-min-microvolt = <3008000>;
+			regulator-max-microvolt = <4000000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_bob2: bob2 {
+			regulator-name = "vreg_bob2";
+			regulator-min-microvolt = <2704000>;
+			regulator-max-microvolt = <3008000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l1b_1p8: ldo1 {
+			regulator-name = "vreg_l1b_1p8";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l2b_3p0: ldo2 {
+			regulator-name = "vreg_l2b_3p0";
+			regulator-min-microvolt = <3008000>;
+			regulator-max-microvolt = <3048000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l4b_1p8: ldo4 {
+			regulator-name = "vreg_l4b_1p8";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l5b_3p1: ldo5 {
+			regulator-name = "vreg_l5b_3p1";
+			regulator-min-microvolt = <3100000>;
+			regulator-max-microvolt = <3148000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l6b_1p8: ldo6 {
+			regulator-name = "vreg_l6b_1p8";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <3008000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l7b_1p8: ldo7 {
+			regulator-name = "vreg_l7b_1p8";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <3008000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+
+		};
+
+		vreg_l8b_1p8: ldo8 {
+			regulator-name = "vreg_l8b_1p8";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <3008000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l9b_2p9: ldo9 {
+			regulator-name = "vreg_l9b_2p9";
+			regulator-min-microvolt = <2960000>;
+			regulator-max-microvolt = <3008000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l10b_1p8: ldo10 {
+			regulator-name = "vreg_l10b_1p8";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l11b_1p0: ldo11 {
+			regulator-name = "vreg_l11b_1p0";
+			regulator-min-microvolt = <1064000>;
+			regulator-max-microvolt = <1292000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l12b_1p8: ldo12 {
+			regulator-name = "vreg_l12b_1p8";
+			regulator-min-microvolt = <1200000>;
+			regulator-max-microvolt = <1800000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l13b_3p0: ldo13 {
+			regulator-name = "vreg_l13b_3p0";
+			regulator-min-microvolt = <3000000>;
+			regulator-max-microvolt = <3000000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l14b_3p2: ldo14 {
+			regulator-name = "vreg_l14b_3p2";
+			regulator-min-microvolt = <3200000>;
+			regulator-max-microvolt = <3200000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l15b_1p8: ldo15 {
+			regulator-name = "vreg_l15b_1p8";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l16b_2p8: ldo16 {
+			regulator-name = "vreg_l16b_2p8";
+			regulator-min-microvolt = <2800000>;
+			regulator-max-microvolt = <2800000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l17b_2p5: ldo17 {
+			regulator-name = "vreg_l17b_2p5";
+			regulator-min-microvolt = <2504000>;
+			regulator-max-microvolt = <2504000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+	};
+
+	regulators-1 {
+		compatible = "qcom,pm8550ve-rpmh-regulators";
+
+		vdd-l1-supply = <&vreg_s7i_1p2>;
+		vdd-l2-supply = <&vreg_s1d_0p97>;
+		vdd-l3-supply = <&vreg_s1d_0p97>;
+		vdd-s1-supply = <&vph_pwr>;
+		vdd-s3-supply = <&vph_pwr>;
+		vdd-s4-supply = <&vph_pwr>;
+
+		qcom,pmic-id = "d";
+
+		vreg_s1d_0p97: smps1 {
+			regulator-name = "vreg_s1d_0p97";
+			regulator-min-microvolt = <880000>;
+			regulator-max-microvolt = <1100000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_s3d_1p2: smps3 {
+			regulator-name = "vreg_s3d_1p2";
+			regulator-min-microvolt = <1200000>;
+			regulator-max-microvolt = <1300000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_s4d_0p85: smps4 {
+			regulator-name = "vreg_s4d_0p85";
+			regulator-min-microvolt = <500000>;
+			regulator-max-microvolt = <1036000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l1d_1p2: ldo1 {
+			regulator-name = "vreg_l1d_1p2";
+			regulator-min-microvolt = <1200000>;
+			regulator-max-microvolt = <1200000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l2d_0p88: ldo2 {
+			regulator-name = "vreg_l2d_0p88";
+			regulator-min-microvolt = <880000>;
+			regulator-max-microvolt = <912000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l3d_0p88: ldo3 {
+			regulator-name = "vreg_l3d_0p88";
+			regulator-min-microvolt = <880000>;
+			regulator-max-microvolt = <920000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+	};
+
+	regulators-2 {
+		compatible = "qcom,pm8550ve-rpmh-regulators";
+
+		vdd-l1-supply = <&vreg_s1d_0p97>;
+		vdd-l2-supply = <&vreg_s7i_1p2>;
+		vdd-l3-supply = <&vreg_s3g_1p8>;
+		vdd-s5-supply = <&vph_pwr>;
+
+		qcom,pmic-id = "f";
+
+		vreg_s5f_0p5: smps5 {
+			regulator-name = "vreg_s5f_0p5";
+			regulator-min-microvolt = <500000>;
+			regulator-max-microvolt = <1000000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l1f_0p88: ldo1 {
+			regulator-name = "vreg_l1f_0p88";
+			regulator-min-microvolt = <880000>;
+			regulator-max-microvolt = <920000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l2f_1p2: ldo2 {
+			regulator-name = "vreg_l2f_1p2";
+			regulator-min-microvolt = <1200000>;
+			regulator-max-microvolt = <1200000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l3f_1p8: ldo3 {
+			regulator-name = "vreg_l3f_1p8";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+	};
+
+	regulators-3 {
+		compatible = "qcom,pm8550ve-rpmh-regulators";
+
+		vdd-l1-supply = <&vreg_s1d_0p97>;
+		vdd-l2-supply = <&vreg_s3g_1p8>;
+		vdd-l3-supply = <&vreg_s7i_1p2>;
+		vdd-s1-supply = <&vph_pwr>;
+		vdd-s3-supply = <&vph_pwr>;
+
+		qcom,pmic-id = "g";
+
+		vreg_s1g_0p5: smps1 {
+			regulator-name = "vreg_s1g_0p5";
+			regulator-min-microvolt = <300000>;
+			regulator-max-microvolt = <700000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_s3g_1p8: smps3 {
+			regulator-name = "vreg_s3g_1p8";
+			regulator-min-microvolt = <1856000>;
+			regulator-max-microvolt = <2000000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_s4g_0p75: smps4 {
+			regulator-name = "vreg_s4g_0p75";
+			regulator-min-microvolt = <300000>;
+			regulator-max-microvolt = <900000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l1g_0p91: ldo1 {
+			regulator-name = "vreg_l1g_0p91";
+			regulator-min-microvolt = <912000>;
+			regulator-max-microvolt = <936000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l2g_1p8: ldo2 {
+			regulator-name = "vreg_l2g_1p8";
+			regulator-min-microvolt = <1200000>;
+			regulator-max-microvolt = <1860000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l3g_1p2: ldo3 {
+			regulator-name = "vreg_l3g_1p2";
+			regulator-min-microvolt = <1200000>;
+			regulator-max-microvolt = <1256000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+	};
+
+	regulators-4 {
+		compatible = "qcom,pm8550ve-rpmh-regulators";
+
+		vdd-l1-supply = <&vreg_s7i_1p2>;
+		vdd-l2-supply = <&vreg_s7i_1p2>;
+		vdd-l3-supply = <&vreg_s1d_0p97>;
+		vdd-s7-supply = <&vph_pwr>;
+		vdd-s8-supply = <&vph_pwr>;
+
+		qcom,pmic-id = "i";
+
+		vreg_s7i_1p2: smps7 {
+			regulator-name = "vreg_s7i_1p2";
+			regulator-min-microvolt = <1224000>;
+			regulator-max-microvolt = <1340000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_s8i_0p9: smps8 {
+			regulator-name = "vreg_s8i_0p9";
+			regulator-min-microvolt = <900000>;
+			regulator-max-microvolt = <972000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l1i_1p2: ldo1 {
+			regulator-name = "vreg_l1i_1p2";
+			regulator-min-microvolt = <1200000>;
+			regulator-max-microvolt = <1200000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l2i_1p2: ldo2 {
+			regulator-name = "vreg_l2i_1p2";
+			regulator-min-microvolt = <1200000>;
+			regulator-max-microvolt = <1200000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l3i_0p88: ldo3 {
+			regulator-name = "vreg_l3i_0p88";
+			regulator-min-microvolt = <880000>;
+			regulator-max-microvolt = <912000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+	};
+
+	regulators-5 {
+		compatible = "qcom,pm8550vs-rpmh-regulators";
+
+		vdd-l1-supply = <&vreg_s1d_0p97>;
+		vdd-l2-supply = <&vreg_s7i_1p2>;
+		vdd-s2-supply = <&vph_pwr>;
+		vdd-s3-supply = <&vph_pwr>;
+		vdd-s4-supply = <&vph_pwr>;
+
+		qcom,pmic-id = "j";
+
+		vreg_s2j_1p1: smps2 {
+			regulator-name = "vreg_s2j_1p1";
+			regulator-min-microvolt = <1000000>;
+			regulator-max-microvolt = <1100000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_s3j_1p1: smps3 {
+			regulator-name = "vreg_s3j_1p1";
+			regulator-min-microvolt = <1000000>;
+			regulator-max-microvolt = <1100000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l1j_0p91: ldo1 {
+			regulator-name = "vreg_l1j_0p91";
+			regulator-min-microvolt = <880000>;
+			regulator-max-microvolt = <920000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l2j_1p2: ldo2 {
+			regulator-name = "vreg_l2j_1p2";
+			regulator-min-microvolt = <1200000>;
+			regulator-max-microvolt = <1200000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+	};
+
+	regulators-6 {
+		compatible = "qcom,pm8010-rpmh-regulators";
+		qcom,pmic-id = "m";
+
+		vdd-l1-l2-supply = <&vreg_s7i_1p2>;
+		vdd-l3-l4-supply = <&vreg_bob2>;
+		vdd-l5-supply = <&vreg_s3g_1p8>;
+		vdd-l6-supply = <&vreg_bob1>;
+		vdd-l7-supply = <&vreg_bob1>;
+
+		vreg_l1m_1p1: ldo1 {
+			regulator-name = "vreg_l1m_1p1";
+			regulator-min-microvolt = <1104000>;
+			regulator-max-microvolt = <1104000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l2m_1p056: ldo2 {
+			regulator-name = "vreg_l2m_1p056";
+			regulator-min-microvolt = <1056000>;
+			regulator-max-microvolt = <1056000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l3m_2p8: ldo3 {
+			regulator-name = "vreg_l3m_2p8";
+			regulator-min-microvolt = <2800000>;
+			regulator-max-microvolt = <2800000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l4m_2p8: ldo4 {
+			regulator-name = "vreg_l4m_2p8";
+			regulator-min-microvolt = <2800000>;
+			regulator-max-microvolt = <2800000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l5m_1p8: ldo5 {
+			regulator-name = "vreg_l5m_1p8";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l6m_2p8: ldo6 {
+			regulator-name = "vreg_l6m_2p8";
+			regulator-min-microvolt = <2800000>;
+			regulator-max-microvolt = <2800000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l7m_2p96: ldo7 {
+			regulator-name = "vreg_l7m_2p96";
+			regulator-min-microvolt = <2960000>;
+			regulator-max-microvolt = <2960000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+	};
+
+	regulators-7 {
+		compatible = "qcom,pm8010-rpmh-regulators";
+		qcom,pmic-id = "n";
+
+		vdd-l1-l2-supply = <&vreg_s7i_1p2>;
+		vdd-l3-l4-supply = <&vreg_s3g_1p8>;
+		vdd-l5-supply = <&vreg_bob2>;
+		vdd-l6-supply = <&vreg_bob2>;
+		vdd-l7-supply = <&vreg_bob1>;
+
+		vreg_l1n_1p1: ldo1 {
+			regulator-name = "vreg_l1n_1p1";
+			regulator-min-microvolt = <1104000>;
+			regulator-max-microvolt = <1104000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l2n_1p1: ldo2 {
+			regulator-name = "vreg_l2n_1p1";
+			regulator-min-microvolt = <1104000>;
+			regulator-max-microvolt = <1104000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l3n_1p8: ldo3 {
+			regulator-name = "vreg_l3n_1p8";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l4n_1p8: ldo4 {
+			regulator-name = "vreg_l4n_1p8";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l5n_2p8: ldo5 {
+			regulator-name = "vreg_l5n_2p8";
+			regulator-min-microvolt = <2800000>;
+			regulator-max-microvolt = <2800000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l6n_2p8: ldo6 {
+			regulator-name = "vreg_l6n_2p8";
+			regulator-min-microvolt = <2800000>;
+			regulator-max-microvolt = <2800000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l7n_3p3: ldo7 {
+			regulator-name = "vreg_l7n_3p3";
+			regulator-min-microvolt = <3304000>;
+			regulator-max-microvolt = <3304000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+	};
+};
+
+&pm8550_flash {
+	status = "okay";
+
+	led-0 {
+		function = LED_FUNCTION_FLASH;
+		color = <LED_COLOR_ID_YELLOW>;
+		led-sources = <1>, <4>;
+		led-max-microamp = <500000>;
+		flash-max-microamp = <2000000>;
+		flash-max-timeout-us = <1280000>;
+		function-enumerator = <0>;
+	};
+
+	led-1 {
+		function = LED_FUNCTION_FLASH;
+		color = <LED_COLOR_ID_WHITE>;
+		led-sources = <2>, <3>;
+		led-max-microamp = <500000>;
+		flash-max-microamp = <2000000>;
+		flash-max-timeout-us = <1280000>;
+		function-enumerator = <1>;
+	};
+};
+
+&pm8550_gpios {
+	volume_up_n: volume-up-n-state {
+		pins = "gpio6";
+		function = "normal";
+		bias-pull-up;
+		input-enable;
+		power-source = <1>;
+	};
+};
+
+&pm8550_pwm {
+	status = "okay";
+
+	multi-led {
+		color = <LED_COLOR_ID_RGB>;
+		function = LED_FUNCTION_STATUS;
+
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		led@1 {
+			reg = <1>;
+			color = <LED_COLOR_ID_RED>;
+		};
+
+		led@2 {
+			reg = <2>;
+			color = <LED_COLOR_ID_GREEN>;
+		};
+
+		led@3 {
+			reg = <3>;
+			color = <LED_COLOR_ID_BLUE>;
+		};
+	};
+};
+
+&pon_pwrkey {
+	status = "okay";
+};
+
+&pon_resin {
+	linux,code = <KEY_VOLUMEDOWN>;
+
+	status = "okay";
+};
+
+&pmih0108_eusb2_repeater {
+	status = "okay";
+
+	vdd18-supply = <&vreg_l15b_1p8>;
+	vdd3-supply = <&vreg_l5b_3p1>;
+};
+
+&qupv3_1 {
+	status = "okay";
+};
+
+&tlmm {
+	/* reserved for secure world */
+	gpio-reserved-ranges = <36 4>, <74 1>;
+};
+
+&uart7 {
+	status = "okay";
+};
diff --git a/dts/upstream/src/arm64/qcom/sm8750-pmics.dtsi b/dts/upstream/src/arm64/qcom/sm8750-pmics.dtsi
new file mode 100644
index 00000000000..6eb8d78937c
--- /dev/null
+++ b/dts/upstream/src/arm64/qcom/sm8750-pmics.dtsi
@@ -0,0 +1,188 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+/ {
+	thermal-zones {
+		pm8550ve-d-thermal {
+			polling-delay-passive = <100>;
+
+			thermal-sensors = <&pm8550ve_d_temp_alarm>;
+
+			trips {
+				trip0 {
+					temperature = <95000>;
+					hysteresis = <0>;
+					type = "passive";
+				};
+
+				trip1 {
+					temperature = <115000>;
+					hysteresis = <0>;
+					type = "hot";
+				};
+			};
+		};
+
+		pm8550ve-f-thermal {
+			polling-delay-passive = <100>;
+
+			thermal-sensors = <&pm8550ve_f_temp_alarm>;
+
+			trips {
+				trip0 {
+					temperature = <95000>;
+					hysteresis = <0>;
+					type = "passive";
+				};
+
+				trip1 {
+					temperature = <115000>;
+					hysteresis = <0>;
+					type = "hot";
+				};
+			};
+		};
+
+		pm8550ve-g-thermal {
+			polling-delay-passive = <100>;
+
+			thermal-sensors = <&pm8550ve_g_temp_alarm>;
+
+			trips {
+				trip0 {
+					temperature = <95000>;
+					hysteresis = <0>;
+					type = "passive";
+				};
+
+				trip1 {
+					temperature = <115000>;
+					hysteresis = <0>;
+					type = "hot";
+				};
+			};
+		};
+
+		pm8550vs-j-thermal {
+			polling-delay-passive = <100>;
+
+			thermal-sensors = <&pm8550vs_j_temp_alarm>;
+
+			trips {
+				trip0 {
+					temperature = <95000>;
+					hysteresis = <0>;
+					type = "passive";
+				};
+
+				trip1 {
+					temperature = <115000>;
+					hysteresis = <0>;
+					type = "hot";
+				};
+			};
+		};
+	};
+};
+
+&spmi_bus {
+	/* PM8550VE */
+	pm8550ve_d: pmic@3 {
+		compatible = "qcom,pm8550ve", "qcom,spmi-pmic";
+		reg = <0x3 SPMI_USID>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		pm8550ve_d_temp_alarm: temp-alarm@a00 {
+			compatible = "qcom,spmi-temp-alarm";
+			reg = <0xa00>;
+			interrupts = <0x3 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
+			#thermal-sensor-cells = <0>;
+		};
+
+		pm8550ve_d_gpios: gpio@8800 {
+			compatible = "qcom,pm8550ve-gpio", "qcom,spmi-gpio";
+			reg = <0x8800>;
+			gpio-controller;
+			gpio-ranges = <&pm8550ve_d_gpios 0 0 8>;
+			#gpio-cells = <2>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+	};
+
+	pm8550ve_f: pmic@5 {
+		compatible = "qcom,pm8550ve", "qcom,spmi-pmic";
+		reg = <0x5 SPMI_USID>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		pm8550ve_f_temp_alarm: temp-alarm@a00 {
+			compatible = "qcom,spmi-temp-alarm";
+			reg = <0xa00>;
+			interrupts = <0x5 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
+			#thermal-sensor-cells = <0>;
+		};
+
+		pm8550ve_f_gpios: gpio@8800 {
+			compatible = "qcom,pm8550ve-gpio", "qcom,spmi-gpio";
+			reg = <0x8800>;
+			gpio-controller;
+			gpio-ranges = <&pm8550ve_f_gpios 0 0 6>;
+			#gpio-cells = <2>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+	};
+
+	pm8550ve_g: pmic@6 {
+		compatible = "qcom,pm8550ve", "qcom,spmi-pmic";
+		reg = <0x6 SPMI_USID>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		pm8550ve_g_temp_alarm: temp-alarm@a00 {
+			compatible = "qcom,spmi-temp-alarm";
+			reg = <0xa00>;
+			interrupts = <0x6 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
+			#thermal-sensor-cells = <0>;
+		};
+
+		pm8550ve_g_gpios: gpio@8800 {
+			compatible = "qcom,pm8550ve-gpio", "qcom,spmi-gpio";
+			reg = <0x8800>;
+			gpio-controller;
+			gpio-ranges = <&pm8550ve_g_gpios 0 0 8>;
+			#gpio-cells = <2>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+	};
+
+	/* PM8550VS */
+	pm8550vs_j: pmic@9 {
+		compatible = "qcom,pm8550vs", "qcom,spmi-pmic";
+		reg = <0x9 SPMI_USID>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		pm8550vs_j_temp_alarm: temp-alarm@a00 {
+			compatible = "qcom,spmi-temp-alarm";
+			reg = <0xa00>;
+			interrupts = <0x9 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
+			#thermal-sensor-cells = <0>;
+		};
+
+		pm8550vs_j_gpios: gpio@8800 {
+			compatible = "qcom,pm8550vs-gpio", "qcom,spmi-gpio";
+			reg = <0x8800>;
+			gpio-controller;
+			gpio-ranges = <&pm8550vs_j_gpios 0 0 6>;
+			#gpio-cells = <2>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+	};
+};
diff --git a/dts/upstream/src/arm64/qcom/sm8750-qrd.dts b/dts/upstream/src/arm64/qcom/sm8750-qrd.dts
new file mode 100644
index 00000000000..f77efab0aef
--- /dev/null
+++ b/dts/upstream/src/arm64/qcom/sm8750-qrd.dts
@@ -0,0 +1,792 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
+#include "sm8750.dtsi"
+#include "pm8010.dtsi"
+#include "pm8550.dtsi"
+#define PMK8550VE_SID 8
+#include "pm8550ve.dtsi"
+#include "pmd8028.dtsi"
+#include "pmih0108.dtsi"
+#include "pmk8550.dtsi"
+#include "pmr735d_a.dtsi"
+#include "sm8750-pmics.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. SM8750 QRD";
+	compatible = "qcom,sm8750-qrd", "qcom,sm8750";
+	chassis-type = "handset";
+
+	aliases {
+		serial0 = &uart7;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	clocks {
+		xo_board: xo-board {
+			compatible = "fixed-clock";
+			clock-frequency = <76800000>;
+			#clock-cells = <0>;
+		};
+
+		sleep_clk: sleep-clk {
+			compatible = "fixed-clock";
+			clock-frequency = <32000>;
+			#clock-cells = <0>;
+		};
+
+		bi_tcxo_div2: bi-tcxo-div2-clk {
+			compatible = "fixed-factor-clock";
+			#clock-cells = <0>;
+
+			clocks = <&rpmhcc RPMH_CXO_CLK>;
+			clock-mult = <1>;
+			clock-div = <2>;
+		};
+
+		bi_tcxo_ao_div2: bi-tcxo-ao-div2-clk {
+			compatible = "fixed-factor-clock";
+			#clock-cells = <0>;
+
+			clocks = <&rpmhcc RPMH_CXO_CLK_A>;
+			clock-mult = <1>;
+			clock-div = <2>;
+		};
+	};
+
+	gpio-keys {
+		compatible = "gpio-keys";
+
+		pinctrl-0 = <&volume_up_n>;
+		pinctrl-names = "default";
+
+		key-volume-up {
+			label = "Volume Up";
+			linux,code = <KEY_VOLUMEUP>;
+			gpios = <&pm8550_gpios 6 GPIO_ACTIVE_LOW>;
+			debounce-interval = <15>;
+			linux,can-disable;
+			wakeup-source;
+		};
+	};
+
+	vph_pwr: vph-pwr-regulator {
+		compatible = "regulator-fixed";
+
+		regulator-name = "vph_pwr";
+		regulator-min-microvolt = <3700000>;
+		regulator-max-microvolt = <3700000>;
+
+		regulator-always-on;
+		regulator-boot-on;
+	};
+};
+
+&apps_rsc {
+	regulators-0 {
+		compatible = "qcom,pm8550-rpmh-regulators";
+
+		vdd-bob1-supply = <&vph_pwr>;
+		vdd-bob2-supply = <&vph_pwr>;
+		vdd-l1-l4-l10-supply = <&vreg_s3g_1p8>;
+		vdd-l2-l13-l14-supply = <&vreg_bob1>;
+		vdd-l3-supply = <&vreg_s7i_1p2>;
+		vdd-l5-l16-supply = <&vreg_bob1>;
+		vdd-l6-l7-supply = <&vreg_bob1>;
+		vdd-l8-l9-supply = <&vreg_bob1>;
+		vdd-l11-supply = <&vreg_s7i_1p2>;
+		vdd-l12-supply = <&vreg_s3g_1p8>;
+		vdd-l15-supply = <&vreg_s3g_1p8>;
+		vdd-l17-supply = <&vreg_bob2>;
+
+		qcom,pmic-id = "b";
+
+		vreg_bob1: bob1 {
+			regulator-name = "vreg_bob1";
+			regulator-min-microvolt = <3008000>;
+			regulator-max-microvolt = <4000000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_bob2: bob2 {
+			regulator-name = "vreg_bob2";
+			regulator-min-microvolt = <2704000>;
+			regulator-max-microvolt = <3008000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l1b_1p8: ldo1 {
+			regulator-name = "vreg_l1b_1p8";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l2b_3p0: ldo2 {
+			regulator-name = "vreg_l2b_3p0";
+			regulator-min-microvolt = <3008000>;
+			regulator-max-microvolt = <3048000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l4b_1p8: ldo4 {
+			regulator-name = "vreg_l4b_1p8";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l5b_3p1: ldo5 {
+			regulator-name = "vreg_l5b_3p1";
+			regulator-min-microvolt = <3100000>;
+			regulator-max-microvolt = <3148000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l6b_1p8: ldo6 {
+			regulator-name = "vreg_l6b_1p8";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <3008000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l7b_1p8: ldo7 {
+			regulator-name = "vreg_l7b_1p8";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <3008000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l8b_1p8: ldo8 {
+			regulator-name = "vreg_l8b_1p8";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <3008000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l9b_2p9: ldo9 {
+			regulator-name = "vreg_l9b_2p9";
+			regulator-min-microvolt = <2960000>;
+			regulator-max-microvolt = <3008000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l10b_1p8: ldo10 {
+			regulator-name = "vreg_l10b_1p8";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l11b_1p0: ldo11 {
+			regulator-name = "vreg_l11b_1p0";
+			regulator-min-microvolt = <1064000>;
+			regulator-max-microvolt = <1292000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l12b_1p8: ldo12 {
+			regulator-name = "vreg_l12b_1p8";
+			regulator-min-microvolt = <1200000>;
+			regulator-max-microvolt = <1800000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l13b_3p0: ldo13 {
+			regulator-name = "vreg_l13b_3p0";
+			regulator-min-microvolt = <3000000>;
+			regulator-max-microvolt = <3000000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l14b_3p2: ldo14 {
+			regulator-name = "vreg_l14b_3p2";
+			regulator-min-microvolt = <3200000>;
+			regulator-max-microvolt = <3200000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l15b_1p8: ldo15 {
+			regulator-name = "vreg_l15b_1p8";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l16b_2p8: ldo16 {
+			regulator-name = "vreg_l16b_2p8";
+			regulator-min-microvolt = <2800000>;
+			regulator-max-microvolt = <2800000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l17b_2p5: ldo17 {
+			regulator-name = "vreg_l17b_2p5";
+			regulator-min-microvolt = <2504000>;
+			regulator-max-microvolt = <2504000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+	};
+
+	regulators-1 {
+		compatible = "qcom,pm8550ve-rpmh-regulators";
+
+		vdd-l1-supply = <&vreg_s7i_1p2>;
+		vdd-l2-supply = <&vreg_s1d_0p97>;
+		vdd-l3-supply = <&vreg_s1d_0p97>;
+		vdd-s1-supply = <&vph_pwr>;
+		vdd-s3-supply = <&vph_pwr>;
+		vdd-s4-supply = <&vph_pwr>;
+
+		qcom,pmic-id = "d";
+
+		vreg_s1d_0p97: smps1 {
+			regulator-name = "vreg_s1d_0p97";
+			regulator-min-microvolt = <880000>;
+			regulator-max-microvolt = <1100000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_s3d_1p2: smps3 {
+			regulator-name = "vreg_s3d_1p2";
+			regulator-min-microvolt = <1200000>;
+			regulator-max-microvolt = <1300000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_s4d_0p85: smps4 {
+			regulator-name = "vreg_s4d_0p85";
+			regulator-min-microvolt = <500000>;
+			regulator-max-microvolt = <1036000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l1d_1p2: ldo1 {
+			regulator-name = "vreg_l1d_1p2";
+			regulator-min-microvolt = <1200000>;
+			regulator-max-microvolt = <1200000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l2d_0p88: ldo2 {
+			regulator-name = "vreg_l2d_0p88";
+			regulator-min-microvolt = <880000>;
+			regulator-max-microvolt = <912000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l3d_0p88: ldo3 {
+			regulator-name = "vreg_l3d_0p88";
+			regulator-min-microvolt = <880000>;
+			regulator-max-microvolt = <920000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+	};
+
+	regulators-2 {
+		compatible = "qcom,pm8550ve-rpmh-regulators";
+
+		vdd-l1-supply = <&vreg_s1d_0p97>;
+		vdd-l2-supply = <&vreg_s7i_1p2>;
+		vdd-l3-supply = <&vreg_s3g_1p8>;
+		vdd-s5-supply = <&vph_pwr>;
+
+		qcom,pmic-id = "f";
+
+		vreg_s5f_0p5: smps5 {
+			regulator-name = "vreg_s5f_0p5";
+			regulator-min-microvolt = <500000>;
+			regulator-max-microvolt = <1000000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l1f_0p88: ldo1 {
+			regulator-name = "vreg_l1f_0p88";
+			regulator-min-microvolt = <880000>;
+			regulator-max-microvolt = <920000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l2f_1p2: ldo2 {
+			regulator-name = "vreg_l2f_1p2";
+			regulator-min-microvolt = <1200000>;
+			regulator-max-microvolt = <1200000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l3f_1p8: ldo3 {
+			regulator-name = "vreg_l3f_1p8";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+	};
+
+	regulators-3 {
+		compatible = "qcom,pm8550ve-rpmh-regulators";
+
+		vdd-l1-supply = <&vreg_s1d_0p97>;
+		vdd-l2-supply = <&vreg_s3g_1p8>;
+		vdd-l3-supply = <&vreg_s7i_1p2>;
+		vdd-s1-supply = <&vph_pwr>;
+		vdd-s3-supply = <&vph_pwr>;
+
+		qcom,pmic-id = "g";
+
+		vreg_s1g_0p5: smps1 {
+			regulator-name = "vreg_s1g_0p5";
+			regulator-min-microvolt = <300000>;
+			regulator-max-microvolt = <700000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_s3g_1p8: smps3 {
+			regulator-name = "vreg_s3g_1p8";
+			regulator-min-microvolt = <1856000>;
+			regulator-max-microvolt = <2000000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_s4g_0p75: smps4 {
+			regulator-name = "vreg_s4g_0p75";
+			regulator-min-microvolt = <300000>;
+			regulator-max-microvolt = <900000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l1g_0p91: ldo1 {
+			regulator-name = "vreg_l1g_0p91";
+			regulator-min-microvolt = <912000>;
+			regulator-max-microvolt = <936000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l2g_1p8: ldo2 {
+			regulator-name = "vreg_l2g_1p8";
+			regulator-min-microvolt = <1200000>;
+			regulator-max-microvolt = <1860000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l3g_1p2: ldo3 {
+			regulator-name = "vreg_l3g_1p2";
+			regulator-min-microvolt = <1200000>;
+			regulator-max-microvolt = <1256000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+	};
+
+	regulators-4 {
+		compatible = "qcom,pm8550ve-rpmh-regulators";
+
+		vdd-l1-supply = <&vreg_s7i_1p2>;
+		vdd-l2-supply = <&vreg_s7i_1p2>;
+		vdd-l3-supply = <&vreg_s1d_0p97>;
+		vdd-s7-supply = <&vph_pwr>;
+		vdd-s8-supply = <&vph_pwr>;
+
+		qcom,pmic-id = "i";
+
+		vreg_s7i_1p2: smps7 {
+			regulator-name = "vreg_s7i_1p2";
+			regulator-min-microvolt = <1224000>;
+			regulator-max-microvolt = <1340000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_s8i_0p9: smps8 {
+			regulator-name = "vreg_s8i_0p9";
+			regulator-min-microvolt = <900000>;
+			regulator-max-microvolt = <972000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l1i_1p2: ldo1 {
+			regulator-name = "vreg_l1i_1p2";
+			regulator-min-microvolt = <1200000>;
+			regulator-max-microvolt = <1200000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l2i_1p2: ldo2 {
+			regulator-name = "vreg_l2i_1p2";
+			regulator-min-microvolt = <1200000>;
+			regulator-max-microvolt = <1200000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l3i_0p88: ldo3 {
+			regulator-name = "vreg_l3i_0p88";
+			regulator-min-microvolt = <880000>;
+			regulator-max-microvolt = <912000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+	};
+
+	regulators-5 {
+		compatible = "qcom,pm8550vs-rpmh-regulators";
+
+		vdd-l1-supply = <&vreg_s1d_0p97>;
+		vdd-l2-supply = <&vreg_s7i_1p2>;
+		vdd-s2-supply = <&vph_pwr>;
+		vdd-s3-supply = <&vph_pwr>;
+
+		qcom,pmic-id = "j";
+
+		vreg_s2j_1p1: smps2 {
+			regulator-name = "vreg_s2j_1p1";
+			regulator-min-microvolt = <1000000>;
+			regulator-max-microvolt = <1100000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_s3j_1p1: smps3 {
+			regulator-name = "vreg_s3j_1p1";
+			regulator-min-microvolt = <1000000>;
+			regulator-max-microvolt = <1100000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+
+		vreg_l1j_0p91: ldo1 {
+			regulator-name = "vreg_l1j_0p91";
+			regulator-min-microvolt = <880000>;
+			regulator-max-microvolt = <920000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l2j_1p2: ldo2 {
+			regulator-name = "vreg_l2j_1p2";
+			regulator-min-microvolt = <1200000>;
+			regulator-max-microvolt = <1200000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+	};
+
+	regulators-6 {
+		compatible = "qcom,pm8010-rpmh-regulators";
+		qcom,pmic-id = "m";
+
+		vdd-l1-l2-supply = <&vreg_s7i_1p2>;
+		vdd-l3-l4-supply = <&vreg_s3g_1p8>;
+		vdd-l5-supply = <&vreg_s3g_1p8>;
+		vdd-l6-supply = <&vreg_bob1>;
+		vdd-l7-supply = <&vreg_bob1>;
+
+		vreg_l1m_1p1: ldo1 {
+			regulator-name = "vreg_l1m_1p1";
+			regulator-min-microvolt = <1104000>;
+			regulator-max-microvolt = <1104000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l2m_1p056: ldo2 {
+			regulator-name = "vreg_l2m_1p056";
+			regulator-min-microvolt = <1056000>;
+			regulator-max-microvolt = <1056000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l3m_2p8: ldo3 {
+			regulator-name = "vreg_l3m_2p8";
+			regulator-min-microvolt = <2800000>;
+			regulator-max-microvolt = <2800000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l4m_2p8: ldo4 {
+			regulator-name = "vreg_l4m_2p8";
+			regulator-min-microvolt = <2800000>;
+			regulator-max-microvolt = <2800000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l5m_1p8: ldo5 {
+			regulator-name = "vreg_l5m_1p8";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l6m_2p8: ldo6 {
+			regulator-name = "vreg_l6m_2p8";
+			regulator-min-microvolt = <2800000>;
+			regulator-max-microvolt = <2800000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l7m_2p96: ldo7 {
+			regulator-name = "vreg_l7m_2p96";
+			regulator-min-microvolt = <2960000>;
+			regulator-max-microvolt = <2960000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+	};
+
+	regulators-7 {
+		compatible = "qcom,pm8010-rpmh-regulators";
+		qcom,pmic-id = "n";
+
+		vdd-l1-l2-supply = <&vreg_s7i_1p2>;
+		vdd-l3-l4-supply = <&vreg_s7i_1p2>;
+		vdd-l5-supply = <&vreg_bob2>;
+		vdd-l6-supply = <&vreg_bob2>;
+		vdd-l7-supply = <&vreg_bob1>;
+
+		vreg_l1n_1p1: ldo1 {
+			regulator-name = "vreg_l1n_1p1";
+			regulator-min-microvolt = <1104000>;
+			regulator-max-microvolt = <1104000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l2n_1p1: ldo2 {
+			regulator-name = "vreg_l2n_1p1";
+			regulator-min-microvolt = <1104000>;
+			regulator-max-microvolt = <1104000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l3n_1p8: ldo3 {
+			regulator-name = "vreg_l3n_1p8";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l4n_1p8: ldo4 {
+			regulator-name = "vreg_l4n_1p8";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l5n_2p8: ldo5 {
+			regulator-name = "vreg_l5n_2p8";
+			regulator-min-microvolt = <2800000>;
+			regulator-max-microvolt = <2800000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l6n_2p8: ldo6 {
+			regulator-name = "vreg_l6n_2p8";
+			regulator-min-microvolt = <2800000>;
+			regulator-max-microvolt = <2800000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l7n_3p3: ldo7 {
+			regulator-name = "vreg_l7n_3p3";
+			regulator-min-microvolt = <3304000>;
+			regulator-max-microvolt = <3304000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+	};
+};
+
+&pm8550_flash {
+	status = "okay";
+
+	led-0 {
+		function = LED_FUNCTION_FLASH;
+		color = <LED_COLOR_ID_YELLOW>;
+		led-sources = <1>, <4>;
+		led-max-microamp = <500000>;
+		flash-max-microamp = <2000000>;
+		flash-max-timeout-us = <1280000>;
+		function-enumerator = <0>;
+	};
+
+	led-1 {
+		function = LED_FUNCTION_FLASH;
+		color = <LED_COLOR_ID_WHITE>;
+		led-sources = <2>, <3>;
+		led-max-microamp = <500000>;
+		flash-max-microamp = <2000000>;
+		flash-max-timeout-us = <1280000>;
+		function-enumerator = <1>;
+	};
+};
+
+&pm8550_gpios {
+	volume_up_n: volume-up-n-state {
+		pins = "gpio6";
+		function = "normal";
+		bias-pull-up;
+		input-enable;
+		power-source = <1>;
+	};
+};
+
+&pm8550_pwm {
+	status = "okay";
+
+	multi-led {
+		color = <LED_COLOR_ID_RGB>;
+		function = LED_FUNCTION_STATUS;
+
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		led@1 {
+			reg = <1>;
+			color = <LED_COLOR_ID_RED>;
+		};
+
+		led@2 {
+			reg = <2>;
+			color = <LED_COLOR_ID_GREEN>;
+		};
+
+		led@3 {
+			reg = <3>;
+			color = <LED_COLOR_ID_BLUE>;
+		};
+	};
+};
+
+&pon_pwrkey {
+	status = "okay";
+};
+
+&pon_resin {
+	linux,code = <KEY_VOLUMEDOWN>;
+
+	status = "okay";
+};
+
+&pmih0108_eusb2_repeater {
+	status = "okay";
+
+	vdd18-supply = <&vreg_l15b_1p8>;
+	vdd3-supply = <&vreg_l5b_3p1>;
+};
+
+&qupv3_1 {
+	status = "okay";
+};
+
+&tlmm {
+	/* reserved for secure world */
+	gpio-reserved-ranges = <36 4>, <74 1>;
+};
+
+&uart7 {
+	status = "okay";
+};
diff --git a/dts/upstream/src/arm64/qcom/sm8750.dtsi b/dts/upstream/src/arm64/qcom/sm8750.dtsi
new file mode 100644
index 00000000000..3bbd7d18598
--- /dev/null
+++ b/dts/upstream/src/arm64/qcom/sm8750.dtsi
@@ -0,0 +1,2907 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#include <dt-bindings/clock/qcom,rpmh.h>
+#include <dt-bindings/clock/qcom,sm8750-gcc.h>
+#include <dt-bindings/clock/qcom,sm8750-tcsr.h>
+#include <dt-bindings/dma/qcom-gpi.h>
+#include <dt-bindings/interconnect/qcom,icc.h>
+#include <dt-bindings/interconnect/qcom,sm8750-rpmh.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/power/qcom,rpmhpd.h>
+#include <dt-bindings/power/qcom-rpmpd.h>
+#include <dt-bindings/soc/qcom,rpmh-rsc.h>
+
+/ {
+	interrupt-parent = <&intc>;
+
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	cpus {
+		#address-cells = <2>;
+		#size-cells = <0>;
+
+		cpu0: cpu@0 {
+			device_type = "cpu";
+			compatible = "qcom,oryon";
+			reg = <0x0 0x0>;
+			enable-method = "psci";
+			next-level-cache = <&l2_0>;
+			power-domains = <&cpu_pd0>;
+			power-domain-names = "psci";
+
+			l2_0: l2-cache {
+				compatible = "cache";
+				cache-level = <2>;
+				cache-unified;
+			};
+		};
+
+		cpu1: cpu@100 {
+			device_type = "cpu";
+			compatible = "qcom,oryon";
+			reg = <0x0 0x100>;
+			enable-method = "psci";
+			next-level-cache = <&l2_0>;
+			power-domains = <&cpu_pd1>;
+			power-domain-names = "psci";
+		};
+
+		cpu2: cpu@200 {
+			device_type = "cpu";
+			compatible = "qcom,oryon";
+			reg = <0x0 0x200>;
+			enable-method = "psci";
+			next-level-cache = <&l2_0>;
+			power-domains = <&cpu_pd2>;
+			power-domain-names = "psci";
+		};
+
+		cpu3: cpu@300 {
+			device_type = "cpu";
+			compatible = "qcom,oryon";
+			reg = <0x0 0x300>;
+			enable-method = "psci";
+			next-level-cache = <&l2_0>;
+			power-domains = <&cpu_pd3>;
+			power-domain-names = "psci";
+		};
+
+		cpu4: cpu@400 {
+			device_type = "cpu";
+			compatible = "qcom,oryon";
+			reg = <0x0 0x400>;
+			enable-method = "psci";
+			next-level-cache = <&l2_0>;
+			power-domains = <&cpu_pd4>;
+			power-domain-names = "psci";
+		};
+
+		cpu5: cpu@500 {
+			device_type = "cpu";
+			compatible = "qcom,oryon";
+			reg = <0x0 0x500>;
+			enable-method = "psci";
+			next-level-cache = <&l2_0>;
+			power-domains = <&cpu_pd5>;
+			power-domain-names = "psci";
+		};
+
+		cpu6: cpu@10000 {
+			device_type = "cpu";
+			compatible = "qcom,oryon";
+			reg = <0x0 0x10000>;
+			enable-method = "psci";
+			next-level-cache = <&L2_1>;
+			power-domains = <&cpu_pd6>;
+			power-domain-names = "psci";
+
+			L2_1: l2-cache {
+				compatible = "cache";
+				cache-level = <2>;
+				cache-unified;
+			};
+		};
+
+		cpu7: cpu@10100 {
+			device_type = "cpu";
+			compatible = "qcom,oryon";
+			reg = <0x0 0x10100>;
+			enable-method = "psci";
+			next-level-cache = <&L2_1>;
+			power-domains = <&cpu_pd7>;
+			power-domain-names = "psci";
+		};
+
+		cpu-map {
+			cluster0 {
+				core0 {
+					cpu = <&cpu0>;
+				};
+
+				core1 {
+					cpu = <&cpu1>;
+				};
+
+				core2 {
+					cpu = <&cpu2>;
+				};
+
+				core3 {
+					cpu = <&cpu3>;
+				};
+
+				core4 {
+					cpu = <&cpu4>;
+				};
+
+				core5 {
+					cpu = <&cpu5>;
+				};
+			};
+
+			cluster1 {
+				core0 {
+					cpu = <&cpu6>;
+				};
+
+				core1 {
+					cpu = <&cpu7>;
+				};
+			};
+		};
+
+		idle-states {
+			entry-method = "psci";
+
+			cluster0_c4: cpu-sleep-0 {
+				compatible = "arm,idle-state";
+				idle-state-name = "ret";
+				arm,psci-suspend-param = <0x00000004>;
+				entry-latency-us = <93>;
+				exit-latency-us = <129>;
+				min-residency-us = <560>;
+			};
+
+			cluster1_c4: cpu-sleep-1 {
+				compatible = "arm,idle-state";
+				idle-state-name = "ret";
+				arm,psci-suspend-param = <0x00000004>;
+				entry-latency-us = <172>;
+				exit-latency-us = <130>;
+				min-residency-us = <686>;
+			};
+
+		};
+
+		domain-idle-states {
+			cluster_cl5: cluster-sleep-0 {
+				compatible = "domain-idle-state";
+				arm,psci-suspend-param = <0x01000054>;
+				entry-latency-us = <2150>;
+				exit-latency-us = <1983>;
+				min-residency-us = <9144>;
+			};
+
+			domain_ss3: domain-sleep-0 {
+				compatible = "domain-idle-state";
+				arm,psci-suspend-param = <0x0200c354>;
+				entry-latency-us = <2800>;
+				exit-latency-us = <4400>;
+				min-residency-us = <10150>;
+			};
+		};
+	};
+
+	firmware {
+		scm: scm {
+			compatible = "qcom,scm-sm8750", "qcom,scm";
+			interconnects = <&aggre2_noc MASTER_CRYPTO QCOM_ICC_TAG_ALWAYS
+					 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+		};
+	};
+
+	clk_virt: interconnect-0 {
+		compatible = "qcom,sm8750-clk-virt";
+		#interconnect-cells = <2>;
+		qcom,bcm-voters = <&apps_bcm_voter>;
+	};
+
+	mc_virt: interconnect-1 {
+		compatible = "qcom,sm8750-mc-virt";
+		#interconnect-cells = <2>;
+		qcom,bcm-voters = <&apps_bcm_voter>;
+	};
+
+	memory@a0000000 {
+		device_type = "memory";
+		/* We expect the bootloader to fill in the size */
+		reg = <0x0 0xa0000000 0x0 0x0>;
+	};
+
+	pmu {
+		compatible = "arm,armv8-pmuv3";
+		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
+	};
+
+	psci {
+		compatible = "arm,psci-1.0";
+		method = "smc";
+
+		cpu_pd0: power-domain-cpu0 {
+			#power-domain-cells = <0>;
+			power-domains = <&cluster_pd>;
+			domain-idle-states = <&cluster0_c4>;
+		};
+
+		cpu_pd1: power-domain-cpu1 {
+			#power-domain-cells = <0>;
+			power-domains = <&cluster_pd>;
+			domain-idle-states = <&cluster0_c4>;
+		};
+
+		cpu_pd2: power-domain-cpu2 {
+			#power-domain-cells = <0>;
+			power-domains = <&cluster_pd>;
+			domain-idle-states = <&cluster0_c4>;
+		};
+
+		cpu_pd3: power-domain-cpu3 {
+			#power-domain-cells = <0>;
+			power-domains = <&cluster_pd>;
+			domain-idle-states = <&cluster0_c4>;
+		};
+
+		cpu_pd4: power-domain-cpu4 {
+			#power-domain-cells = <0>;
+			power-domains = <&cluster_pd>;
+			domain-idle-states = <&cluster0_c4>;
+		};
+
+		cpu_pd5: power-domain-cpu5 {
+			#power-domain-cells = <0>;
+			power-domains = <&cluster_pd>;
+			domain-idle-states = <&cluster0_c4>;
+		};
+
+		cpu_pd6: power-domain-cpu6 {
+			#power-domain-cells = <0>;
+			power-domains = <&cluster_pd>;
+			domain-idle-states = <&cluster1_c4>;
+		};
+
+		cpu_pd7: power-domain-cpu7 {
+			#power-domain-cells = <0>;
+			power-domains = <&cluster_pd>;
+			domain-idle-states = <&cluster1_c4>;
+		};
+
+		cluster_pd: power-domain-cluster {
+			#power-domain-cells = <0>;
+			domain-idle-states = <&cluster_cl5>;
+			power-domains = <&system_pd>;
+		};
+
+		system_pd: power-domain-system {
+			#power-domain-cells = <0>;
+			domain-idle-states = <&domain_ss3>;
+		};
+	};
+
+	reserved-memory {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		gunyah_hyp_mem: gunyah-hyp@80000000 {
+			reg = <0x0 0x80000000 0x0 0xe00000>;
+			no-map;
+		};
+
+		cpusys_vm_mem: cpusys-vm-mem@80e00000 {
+			reg = <0x0 0x80e00000 0x0 0x40000>;
+			no-map;
+		};
+
+		cpucp_mem: cpucp@81200000 {
+			reg = <0x0 0x81200000 0x0 0x200000>;
+			no-map;
+		};
+
+		xbl_dtlog_mem: xbl-dtlog@81a00000 {
+			reg = <0x0 0x81a00000 0x0 0x40000>;
+			no-map;
+		};
+
+		aop_image_mem: aop-image@81c00000 {
+			reg = <0x0 0x81c00000 0x0 0x60000>;
+			no-map;
+		};
+
+		aop_cmd_db_mem: aop-cmd-db@81c60000 {
+			compatible = "qcom,cmd-db";
+			reg = <0x0 0x81c60000 0x0 0x20000>;
+			no-map;
+		};
+
+		/* Merged aop_config, tme_crash_dump, tme_log and uefi_log regions */
+		aop_tme_uefi_merged_mem: aop-tme-uefi-merged@81c80000 {
+			reg = <0x0 0x81c80000 0x0 0x74000>;
+			no-map;
+		};
+
+		/* Secdata region can be reused by apps */
+
+		smem_mem: smem@81d00000 {
+			compatible = "qcom,smem";
+			reg = <0x0 0x81d00000 0x0 0x200000>;
+			hwlocks = <&tcsr_mutex 3>;
+			no-map;
+		};
+
+		pdp_ns_shared_mem: pdp-ns-shared@81f00000 {
+			reg = <0x0 0x81f00000 0x0 0x100000>;
+			no-map;
+		};
+
+		cpucp_scandump_mem: cpucp-scandump@82000000 {
+			reg = <0x0 0x82000000 0x0 0x380000>;
+			no-map;
+		};
+
+		adsp_mhi_mem: adsp-mhi@82380000 {
+			reg = <0x0 0x82380000 0x0 0x20000>;
+			no-map;
+		};
+
+		soccp_sdi_mem: soccp-sdi@823a0000 {
+			reg = <0x0 0x823a0000 0x0 0x40000>;
+			no-map;
+		};
+
+		pmic_minii_dump_mem: pmic-minii-dump@823e0000 {
+			reg = <0x0 0x823e0000 0x0 0x80000>;
+			no-map;
+		};
+
+		pvmfw_mem: pvmfw@824a0000 {
+			reg = <0x0 0x824a0000 0x0 0x100000>;
+			no-map;
+		};
+
+		global_sync_mem: global-sync@82600000 {
+			reg = <0x0 0x82600000 0x0 0x100000>;
+			no-map;
+		};
+
+		tz_stat_mem: tz-stat@82700000 {
+			reg = <0x0 0x82700000 0x0 0x100000>;
+			no-map;
+		};
+
+		qdss_mem: qdss@82800000 {
+			reg = <0x0 0x82800000 0x0 0x2000000>;
+			no-map;
+		};
+
+		dsm_partition_1_mem: dsm-partition-1@84a00000 {
+			reg = <0x0 0x84a00000 0x0 0x4900000>;
+			no-map;
+		};
+
+		dsm_partition_2_mem: dsm-partition-2@89300000 {
+			reg = <0x0 0x89300000 0x0 0xa80000>;
+			no-map;
+		};
+
+		mpss_mem: mpss@8ba00000 {
+			reg = <0x0 0x8ba00000 0x0 0xf600000>;
+			no-map;
+		};
+
+		q6_mpss_dtb_mem: q6-mpss-dtb@9b000000 {
+			reg = <0x0 0x9b000000 0x0 0x80000>;
+			no-map;
+		};
+
+		ipa_fw_mem: ipa-fw@9b080000 {
+			reg = <0x0 0x9b080000 0x0 0x10000>;
+			no-map;
+		};
+
+		ipa_gsi_mem: ipa-gsi@9b090000 {
+			reg = <0x0 0x9b090000 0x0 0xa000>;
+			no-map;
+		};
+
+		gpu_micro_code_mem: gpu-micro-code@9b09a000 {
+			reg = <0x0 0x9b09a000 0x0 0x2000>;
+			no-map;
+		};
+
+		spss_region_mem: spss@9b0a0000  {
+			reg = <0x0 0x9b0a0000 0x0 0x1e0000>;
+			no-map;
+		};
+
+		/* First part of the "SPU secure shared memory" region */
+		spu_tz_shared_mem: spu-tz-shared@9b280000 {
+			reg = <0x0 0x9b280000 0x0 0x40000>;
+			no-map;
+		};
+
+		/* Second part of the "SPU secure shared memory" region */
+		spu_modem_shared_mem: spu-modem-shared@9b2c0000 {
+			reg = <0x0 0x9b2c0000 0x0 0x40000>;
+			no-map;
+		};
+
+		camera_mem: camera@9b300000 {
+			reg = <0x0 0x9b300000 0x0 0x800000>;
+			no-map;
+		};
+
+		camera_2_mem: camera-2@9bb00000 {
+			reg = <0x0 0x9bb00000 0x0 0x800000>;
+			no-map;
+		};
+
+		video_mem: video@9c300000 {
+			reg = <0x0 0x9c300000 0x0 0x800000>;
+			no-map;
+		};
+
+		cvp_mem: cvp@9cb00000 {
+			reg = <0x0 0x9cb00000 0x0 0x700000>;
+			no-map;
+		};
+
+		cdsp_mem: cdsp@9d200000 {
+			reg = <0x0 0x9d200000 0x0 0x1900000>;
+			no-map;
+		};
+
+		q6_cdsp_dtb_mem: q6-cdsp-dtb@9eb00000 {
+			reg = <0x0 0x9eb00000 0x0 0x80000>;
+			no-map;
+		};
+
+		soccp_mem: soccp@9ec00000 {
+			reg = <0x0 0x9ec00000 0x0 0x180000>;
+			no-map;
+		};
+
+		q6_adsp_dtb_mem: q6-adsp-dtb@9ed80000 {
+			reg = <0x0 0x9ed80000 0x0 0x80000>;
+			no-map;
+		};
+
+		adspslpi_mem: adspslpi@9ee00000 {
+			reg = <0x0 0x9ee00000 0x0 0x3a80000>;
+			no-map;
+		};
+
+		xbl_ramdump_mem: xbl-ramdump@b8000000 {
+			reg = <0x0 0xb8000000 0x0 0x1c0000>;
+			no-map;
+		};
+
+		hwfence_shbuf: hwfence-shbuf@d4e23000 {
+			no-map;
+			reg = <0x0 0xd4e23000 0x0 0x2dd000>;
+		};
+
+		/* Merged tz_reserved, xbl_sc, and qtee regions */
+		tz_merged_mem: tz-merged@d8000000 {
+			reg = <0x0 0xd8000000 0x0 0x600000>;
+			no-map;
+		};
+
+		trust_ui_vm_mem: trust-ui-vm@f3800000 {
+			reg = <0x0 0xf3800000 0x0 0x4400000>;
+			no-map;
+		};
+
+		oem_vm_mem: oem-vm@f7c00000 {
+			reg = <0x0 0xf7c00000 0x0 0x4c00000>;
+			no-map;
+		};
+
+		llcc_lpi_mem: llcc-lpi@ff800000 {
+			reg = <0x0 0xff800000 0x0 0x800000>;
+			no-map;
+		};
+	};
+
+	soc: soc@0 {
+		compatible = "simple-bus";
+
+		#address-cells = <2>;
+		#size-cells = <2>;
+		dma-ranges = <0 0 0 0 0x10 0>;
+		ranges = <0 0 0 0 0x10 0>;
+
+		gcc: clock-controller@100000 {
+			compatible = "qcom,sm8750-gcc";
+			reg = <0x0 0x00100000 0x0 0x1f4200>;
+
+			clocks = <&bi_tcxo_div2>,
+				 <0>,
+				 <&sleep_clk>,
+				 <0>,
+				 <0>,
+				 <0>,
+				 <0>,
+				 <0>;
+
+			#clock-cells = <1>;
+			#reset-cells = <1>;
+			#power-domain-cells = <1>;
+		};
+
+		gpi_dma2: dma-controller@800000 {
+			compatible = "qcom,sm8750-gpi-dma", "qcom,sm6350-gpi-dma";
+			reg = <0x0 0x00800000 0x0 0x60000>;
+
+			interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>;
+
+			dma-channels = <12>;
+			dma-channel-mask = <0x1e>;
+			#dma-cells = <3>;
+
+			iommus = <&apps_smmu 0x436 0x0>;
+
+			status = "disabled";
+		};
+
+		qupv3_2: geniqup@8c0000 {
+			compatible = "qcom,geni-se-qup";
+			reg = <0x0 0x008c0000 0x0 0x2000>;
+
+			clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
+				 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
+			clock-names = "m-ahb",
+				      "s-ahb";
+
+			iommus = <&apps_smmu 0x423 0x0>;
+
+			#address-cells = <2>;
+			#size-cells = <2>;
+			ranges;
+
+			status = "disabled";
+
+			i2c8: i2c@880000 {
+				compatible = "qcom,geni-i2c";
+				reg = <0x0 0x00880000 0x0 0x4000>;
+
+				interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
+
+				clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
+				clock-names = "se";
+
+				interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
+						 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
+						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+						 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
+						<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
+						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+				interconnect-names = "qup-core",
+						     "qup-config",
+						     "qup-memory";
+
+				dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>,
+				       <&gpi_dma2 1 0 QCOM_GPI_I2C>;
+				dma-names = "tx",
+					    "rx";
+
+				pinctrl-0 = <&qup_i2c8_data_clk>;
+				pinctrl-names = "default";
+
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				status = "disabled";
+			};
+
+			spi8: spi@880000 {
+				compatible = "qcom,geni-spi";
+				reg = <0x0 0x00880000 0x0 0x4000>;
+
+				interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
+
+				clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
+				clock-names = "se";
+
+				interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
+						 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
+						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+						 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
+						<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
+						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+				interconnect-names = "qup-core",
+						     "qup-config",
+						     "qup-memory";
+
+				dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>,
+				       <&gpi_dma2 1 0 QCOM_GPI_SPI>;
+				dma-names = "tx",
+					    "rx";
+
+				pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>;
+				pinctrl-names = "default";
+
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				status = "disabled";
+			};
+
+			i2c9: i2c@884000 {
+				compatible = "qcom,geni-i2c";
+				reg = <0x0 0x00884000 0x0 0x4000>;
+
+				interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
+
+				clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
+				clock-names = "se";
+
+				interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
+						 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
+						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+						 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
+						<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
+						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+				interconnect-names = "qup-core",
+						     "qup-config",
+						     "qup-memory";
+
+				dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>,
+				       <&gpi_dma2 1 1 QCOM_GPI_I2C>;
+				dma-names = "tx",
+					    "rx";
+
+				pinctrl-0 = <&qup_i2c9_data_clk>;
+				pinctrl-names = "default";
+
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				status = "disabled";
+			};
+
+			spi9: spi@884000 {
+				compatible = "qcom,geni-spi";
+				reg = <0x0 0x00884000 0x0 0x4000>;
+
+				interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
+
+				clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
+				clock-names = "se";
+
+				interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
+						 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
+						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+						 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
+						<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
+						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+				interconnect-names = "qup-core",
+						     "qup-config",
+						     "qup-memory";
+
+				dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>,
+				       <&gpi_dma2 1 1 QCOM_GPI_SPI>;
+				dma-names = "tx",
+					    "rx";
+
+				pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>;
+				pinctrl-names = "default";
+
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				status = "disabled";
+			};
+
+			i2c10: i2c@888000 {
+				compatible = "qcom,geni-i2c";
+				reg = <0x0 0x00888000 0x0 0x4000>;
+
+				interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
+
+				clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
+				clock-names = "se";
+
+				interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
+						 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
+						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+						 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
+						<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
+						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+				interconnect-names = "qup-core",
+						     "qup-config",
+						     "qup-memory";
+
+				dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>,
+				       <&gpi_dma2 1 2 QCOM_GPI_I2C>;
+				dma-names = "tx",
+					    "rx";
+
+				pinctrl-0 = <&qup_i2c10_data_clk>;
+				pinctrl-names = "default";
+
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				status = "disabled";
+			};
+
+			spi10: spi@888000 {
+				compatible = "qcom,geni-spi";
+				reg = <0x0 0x00888000 0x0 0x4000>;
+
+				interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
+
+				clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
+				clock-names = "se";
+
+				interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
+						 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
+						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+						 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
+						<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
+						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+				interconnect-names = "qup-core",
+						     "qup-config",
+						     "qup-memory";
+
+				dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>,
+				       <&gpi_dma2 1 2 QCOM_GPI_SPI>;
+				dma-names = "tx",
+					    "rx";
+
+				pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>;
+				pinctrl-names = "default";
+
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				status = "disabled";
+			};
+
+			i2c11: i2c@88c000 {
+				compatible = "qcom,geni-i2c";
+				reg = <0x0 0x0088c000 0x0 0x4000>;
+
+				interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
+
+				clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
+				clock-names = "se";
+
+				interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
+						 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
+						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+						 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
+						<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
+						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+				interconnect-names = "qup-core",
+						     "qup-config",
+						     "qup-memory";
+
+				dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>,
+				       <&gpi_dma2 1 3 QCOM_GPI_I2C>;
+				dma-names = "tx",
+					    "rx";
+
+				pinctrl-0 = <&qup_i2c11_data_clk>;
+				pinctrl-names = "default";
+
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				status = "disabled";
+			};
+
+			spi11: spi@88c000 {
+				compatible = "qcom,geni-spi";
+				reg = <0x0 0x0088c000 0x0 0x4000>;
+
+				interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
+
+				clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
+				clock-names = "se";
+
+				interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
+						 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
+						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+						 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
+						<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
+						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+				interconnect-names = "qup-core",
+						     "qup-config",
+						     "qup-memory";
+
+				dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>,
+				       <&gpi_dma2 1 3 QCOM_GPI_SPI>;
+				dma-names = "tx",
+					    "rx";
+
+				pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>;
+				pinctrl-names = "default";
+
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				status = "disabled";
+			};
+
+			i2c12: i2c@890000 {
+				compatible = "qcom,geni-i2c";
+				reg = <0x0 0x00890000 0x0 0x4000>;
+
+				interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
+
+				clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
+				clock-names = "se";
+
+				interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
+						 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
+						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+						 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
+						<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
+						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+				interconnect-names = "qup-core",
+						     "qup-config",
+						     "qup-memory";
+
+				dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>,
+				       <&gpi_dma2 1 4 QCOM_GPI_I2C>;
+				dma-names = "tx",
+					    "rx";
+
+				pinctrl-0 = <&qup_i2c12_data_clk>;
+				pinctrl-names = "default";
+
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				status = "disabled";
+			};
+
+			spi12: spi@890000 {
+				compatible = "qcom,geni-spi";
+				reg = <0x0 0x00890000 0x0 0x4000>;
+
+				interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
+
+				clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
+				clock-names = "se";
+
+				interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
+						 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
+						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+						 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
+						<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
+						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+				interconnect-names = "qup-core",
+						     "qup-config",
+						     "qup-memory";
+
+				dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>,
+				       <&gpi_dma2 1 4 QCOM_GPI_SPI>;
+				dma-names = "tx",
+					    "rx";
+
+				pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>;
+				pinctrl-names = "default";
+
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				status = "disabled";
+			};
+
+			i2c13: i2c@894000 {
+				compatible = "qcom,geni-i2c";
+				reg = <0x0 0x00894000 0x0 0x4000>;
+
+				interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
+
+				clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
+				clock-names = "se";
+
+				interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
+						 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
+						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+						 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
+						<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
+						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+				interconnect-names = "qup-core",
+						     "qup-config",
+						     "qup-memory";
+
+				dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>,
+				       <&gpi_dma2 1 5 QCOM_GPI_I2C>;
+				dma-names = "tx",
+					    "rx";
+
+				pinctrl-0 = <&qup_i2c13_data_clk>;
+				pinctrl-names = "default";
+
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				status = "disabled";
+			};
+
+			spi13: spi@894000 {
+				compatible = "qcom,geni-spi";
+				reg = <0x0 0x00894000 0x0 0x4000>;
+
+				interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
+
+				clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
+				clock-names = "se";
+
+				interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
+						 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
+						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+						 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
+						<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
+						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+				interconnect-names = "qup-core",
+						     "qup-config",
+						     "qup-memory";
+
+				dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>,
+				       <&gpi_dma2 1 5 QCOM_GPI_SPI>;
+				dma-names = "tx",
+					    "rx";
+
+				pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>;
+				pinctrl-names = "default";
+
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				status = "disabled";
+			};
+
+			uart14: serial@898000 {
+				compatible = "qcom,geni-uart";
+				reg = <0x0 0x00898000 0x0 0x4000>;
+
+				interrupts = <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>;
+
+				clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
+				clock-names = "se";
+
+				interconnects =	<&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
+						 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
+						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+						 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>;
+				interconnect-names = "qup-core",
+						     "qup-config";
+
+				pinctrl-0 = <&qup_uart14_default>;
+				pinctrl-names = "default";
+
+				status = "disabled";
+			};
+
+			i2c15: i2c@89c000 {
+				compatible = "qcom,geni-i2c";
+				reg = <0x0 0x0089c000 0x0 0x4000>;
+
+				interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>;
+
+				clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>;
+				clock-names = "se";
+
+				interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
+						 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
+						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+						 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
+						<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
+						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+				interconnect-names = "qup-core",
+						     "qup-config",
+						     "qup-memory";
+
+				dmas = <&gpi_dma2 0 7 QCOM_GPI_I2C>,
+				       <&gpi_dma2 1 7 QCOM_GPI_I2C>;
+				dma-names = "tx",
+					    "rx";
+
+				pinctrl-0 = <&qup_i2c15_data_clk>;
+				pinctrl-names = "default";
+
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				status = "disabled";
+			};
+
+			spi15: spi@89c000 {
+				compatible = "qcom,geni-spi";
+				reg = <0x0 0x0089c000 0x0 0x4000>;
+
+				interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>;
+
+				clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>;
+				clock-names = "se";
+
+				interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
+						 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
+						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+						 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
+						<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
+						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+				interconnect-names = "qup-core",
+						     "qup-config",
+						     "qup-memory";
+
+				dmas = <&gpi_dma2 0 7 QCOM_GPI_SPI>,
+				       <&gpi_dma2 1 7 QCOM_GPI_SPI>;
+				dma-names = "tx",
+					    "rx";
+
+				pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>;
+				pinctrl-names = "default";
+
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				status = "disabled";
+			};
+		};
+
+		i2c_master_hub_0: geniqup@9c0000 {
+			compatible = "qcom,geni-se-i2c-master-hub";
+			reg = <0x0 0x009c0000 0x0 0x2000>;
+
+			clocks = <&gcc GCC_QUPV3_I2C_S_AHB_CLK>;
+			clock-names = "s-ahb";
+
+			#address-cells = <2>;
+			#size-cells = <2>;
+			ranges;
+
+			status = "disabled";
+
+			i2c_hub_0: i2c@980000 {
+				compatible = "qcom,geni-i2c-master-hub";
+				reg = <0x0 0x00980000 0x0 0x4000>;
+
+				interrupts = <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>;
+
+				clocks = <&gcc GCC_QUPV3_I2C_S0_CLK>,
+					 <&gcc GCC_QUPV3_I2C_CORE_CLK>;
+				clock-names = "se",
+					      "core";
+
+				interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
+						 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
+						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+						 &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>;
+				interconnect-names = "qup-core",
+						     "qup-config";
+
+				pinctrl-0 = <&hub_i2c0_data_clk>;
+				pinctrl-names = "default";
+
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				status = "disabled";
+			};
+
+			i2c_hub_1: i2c@984000 {
+				compatible = "qcom,geni-i2c-master-hub";
+				reg = <0x0 0x00984000 0x0 0x4000>;
+
+				interrupts = <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>;
+
+				clocks = <&gcc GCC_QUPV3_I2C_S1_CLK>,
+					 <&gcc GCC_QUPV3_I2C_CORE_CLK>;
+				clock-names = "se",
+					      "core";
+
+				interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
+						 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
+						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+						 &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>;
+				interconnect-names = "qup-core",
+						     "qup-config";
+
+				pinctrl-0 = <&hub_i2c1_data_clk>;
+				pinctrl-names = "default";
+
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				status = "disabled";
+			};
+
+			i2c_hub_2: i2c@988000 {
+				compatible = "qcom,geni-i2c-master-hub";
+				reg = <0x0 0x00988000 0x0 0x4000>;
+
+				interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>;
+
+				clocks = <&gcc GCC_QUPV3_I2C_S2_CLK>,
+					 <&gcc GCC_QUPV3_I2C_CORE_CLK>;
+				clock-names = "se",
+					      "core";
+
+				interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
+						 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
+						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+						 &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>;
+				interconnect-names = "qup-core",
+						     "qup-config";
+
+				pinctrl-0 = <&hub_i2c2_data_clk>;
+				pinctrl-names = "default";
+
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				status = "disabled";
+			};
+
+			i2c_hub_3: i2c@98c000 {
+				compatible = "qcom,geni-i2c-master-hub";
+				reg = <0x0 0x0098c000 0x0 0x4000>;
+
+				interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>;
+
+				clocks = <&gcc GCC_QUPV3_I2C_S3_CLK>,
+					 <&gcc GCC_QUPV3_I2C_CORE_CLK>;
+				clock-names = "se",
+					      "core";
+
+				interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
+						 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
+						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+						 &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>;
+				interconnect-names = "qup-core",
+						     "qup-config";
+
+				pinctrl-0 = <&hub_i2c3_data_clk>;
+				pinctrl-names = "default";
+
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				status = "disabled";
+			};
+
+			i2c_hub_4: i2c@990000 {
+				compatible = "qcom,geni-i2c-master-hub";
+				reg = <0x0 0x00990000 0x0 0x4000>;
+
+				interrupts = <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>;
+
+				clocks = <&gcc GCC_QUPV3_I2C_S4_CLK>,
+					 <&gcc GCC_QUPV3_I2C_CORE_CLK>;
+				clock-names = "se",
+					      "core";
+
+				interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
+						 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
+						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+						 &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>;
+				interconnect-names = "qup-core",
+						     "qup-config";
+
+				pinctrl-0 = <&hub_i2c4_data_clk>;
+				pinctrl-names = "default";
+
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				status = "disabled";
+			};
+
+			i2c_hub_5: i2c@994000 {
+				compatible = "qcom,geni-i2c-master-hub";
+				reg = <0x0 0x00994000 0x0 0x4000>;
+
+				interrupts = <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>;
+
+				clocks = <&gcc GCC_QUPV3_I2C_S5_CLK>,
+					 <&gcc GCC_QUPV3_I2C_CORE_CLK>;
+				clock-names = "se",
+					      "core";
+
+				interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
+						 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
+						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+						 &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>;
+				interconnect-names = "qup-core",
+						     "qup-config";
+
+				pinctrl-0 = <&hub_i2c5_data_clk>;
+				pinctrl-names = "default";
+
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				status = "disabled";
+			};
+
+			i2c_hub_6: i2c@998000 {
+				compatible = "qcom,geni-i2c-master-hub";
+				reg = <0x0 0x00998000 0x0 0x4000>;
+
+				interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>;
+
+				clocks = <&gcc GCC_QUPV3_I2C_S6_CLK>,
+					 <&gcc GCC_QUPV3_I2C_CORE_CLK>;
+				clock-names = "se",
+					      "core";
+
+				interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
+						 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
+						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+						 &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>;
+				interconnect-names = "qup-core",
+						     "qup-config";
+
+				pinctrl-0 = <&hub_i2c6_data_clk>;
+				pinctrl-names = "default";
+
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				status = "disabled";
+			};
+
+			i2c_hub_7: i2c@99c000 {
+				compatible = "qcom,geni-i2c-master-hub";
+				reg = <0x0 0x0099c000 0x0 0x4000>;
+
+				interrupts = <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>;
+
+				clocks = <&gcc GCC_QUPV3_I2C_S7_CLK>,
+					 <&gcc GCC_QUPV3_I2C_CORE_CLK>;
+				clock-names = "se",
+					      "core";
+
+				interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
+						 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
+						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+						 &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>;
+				interconnect-names = "qup-core",
+						     "qup-config";
+
+				pinctrl-0 = <&hub_i2c7_data_clk>;
+				pinctrl-names = "default";
+
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				status = "disabled";
+			};
+
+			i2c_hub_8: i2c@9a0000 {
+				compatible = "qcom,geni-i2c-master-hub";
+				reg = <0x0 0x009a0000 0x0 0x4000>;
+
+				interrupts = <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>;
+
+				clocks = <&gcc GCC_QUPV3_I2C_S8_CLK>,
+					 <&gcc GCC_QUPV3_I2C_CORE_CLK>;
+				clock-names = "se",
+					      "core";
+
+				interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
+						 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
+						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+						 &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>;
+				interconnect-names = "qup-core",
+						     "qup-config";
+
+				pinctrl-0 = <&hub_i2c8_data_clk>;
+				pinctrl-names = "default";
+
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				status = "disabled";
+			};
+
+			i2c_hub_9: i2c@9a4000 {
+				compatible = "qcom,geni-i2c-master-hub";
+				reg = <0x0 0x009a4000 0x0 0x4000>;
+
+				interrupts = <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>;
+
+				clocks = <&gcc GCC_QUPV3_I2C_S9_CLK>,
+					 <&gcc GCC_QUPV3_I2C_CORE_CLK>;
+				clock-names = "se",
+					      "core";
+
+				interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
+						 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
+						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+						 &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>;
+				interconnect-names = "qup-core",
+						     "qup-config";
+
+				pinctrl-0 = <&hub_i2c9_data_clk>;
+				pinctrl-names = "default";
+
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				status = "disabled";
+			};
+		};
+
+		gpi_dma1: dma-controller@a00000 {
+			compatible = "qcom,sm8750-gpi-dma", "qcom,sm6350-gpi-dma";
+			reg = <0x0 0x00a00000 0x0 0x60000>;
+
+			interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>;
+
+			dma-channels = <12>;
+			dma-channel-mask = <0x1e>;
+			#dma-cells = <3>;
+
+			iommus = <&apps_smmu 0xb6 0x0>;
+
+			status = "disabled";
+		};
+
+		qupv3_1: geniqup@ac0000 {
+			compatible = "qcom,geni-se-qup";
+			reg = <0x0 0x00ac0000 0x0 0x2000>;
+
+			clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
+				 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
+			clock-names = "m-ahb",
+				      "s-ahb";
+
+			iommus = <&apps_smmu 0xa3 0x0>;
+
+			#address-cells = <2>;
+			#size-cells = <2>;
+			ranges;
+
+			status = "disabled";
+
+			i2c0: i2c@a80000 {
+				compatible = "qcom,geni-i2c";
+				reg = <0x0 0x00a80000 0x0 0x4000>;
+
+				interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
+
+				clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
+				clock-names = "se";
+
+				interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
+						 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
+						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+						 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
+						<&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
+						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+				interconnect-names = "qup-core",
+						     "qup-config",
+						     "qup-memory";
+
+				dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
+				       <&gpi_dma1 1 0 QCOM_GPI_I2C>;
+				dma-names = "tx",
+					    "rx";
+
+				pinctrl-0 = <&qup_i2c0_data_clk>;
+				pinctrl-names = "default";
+
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				status = "disabled";
+			};
+
+			spi0: spi@a80000 {
+				compatible = "qcom,geni-spi";
+				reg = <0x0 0x00a80000 0x0 0x4000>;
+
+				interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
+
+				clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
+				clock-names = "se";
+
+				interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
+						 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
+						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+						 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
+						<&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
+						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+				interconnect-names = "qup-core",
+						     "qup-config",
+						     "qup-memory";
+
+				dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>,
+				       <&gpi_dma1 1 0 QCOM_GPI_SPI>;
+				dma-names = "tx",
+					    "rx";
+
+				pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>;
+				pinctrl-names = "default";
+
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				status = "disabled";
+			};
+
+			i2c1: i2c@a84000 {
+				compatible = "qcom,geni-i2c";
+				reg = <0x0 0x00a84000 0x0 0x4000>;
+
+				interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
+
+				clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
+				clock-names = "se";
+
+				interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
+						 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
+						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+						 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
+						<&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
+						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+				interconnect-names = "qup-core",
+						     "qup-config",
+						     "qup-memory";
+
+				dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
+				       <&gpi_dma1 1 1 QCOM_GPI_I2C>;
+				dma-names = "tx",
+					    "rx";
+
+				pinctrl-0 = <&qup_i2c1_data_clk>;
+				pinctrl-names = "default";
+
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				status = "disabled";
+			};
+
+			spi1: spi@a84000 {
+				compatible = "qcom,geni-spi";
+				reg = <0x0 0x00a84000 0x0 0x4000>;
+
+				interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
+
+				clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
+				clock-names = "se";
+
+				interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
+						 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
+						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+						 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
+						<&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
+						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+				interconnect-names = "qup-core",
+						     "qup-config",
+						     "qup-memory";
+
+				dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
+				       <&gpi_dma1 1 1 QCOM_GPI_SPI>;
+				dma-names = "tx",
+					    "rx";
+
+				pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>;
+				pinctrl-names = "default";
+
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				status = "disabled";
+			};
+
+			i2c2: i2c@a88000 {
+				compatible = "qcom,geni-i2c";
+				reg = <0x0 0x00a88000 0x0 0x4000>;
+
+				interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
+
+				clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
+				clock-names = "se";
+
+				interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
+						 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
+						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+						 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
+						<&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
+						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+				interconnect-names = "qup-core",
+						     "qup-config",
+						     "qup-memory";
+
+				dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
+				       <&gpi_dma1 1 2 QCOM_GPI_I2C>;
+				dma-names = "tx",
+					    "rx";
+
+				pinctrl-0 = <&qup_i2c2_data_clk>;
+				pinctrl-names = "default";
+
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				status = "disabled";
+			};
+
+			spi2: spi@a88000 {
+				compatible = "qcom,geni-spi";
+				reg = <0x0 0x00a88000 0x0 0x4000>;
+
+				interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
+
+				clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
+				clock-names = "se";
+
+				interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
+						 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
+						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+						 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
+						<&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
+						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+				interconnect-names = "qup-core",
+						     "qup-config",
+						     "qup-memory";
+
+				dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>,
+				       <&gpi_dma1 1 2 QCOM_GPI_SPI>;
+				dma-names = "tx",
+					    "rx";
+
+				pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>;
+				pinctrl-names = "default";
+
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				status = "disabled";
+			};
+
+			i2c3: i2c@a8c000 {
+				compatible = "qcom,geni-i2c";
+				reg = <0x0 0x00a8c000 0x0 0x4000>;
+
+				interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
+
+				clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
+				clock-names = "se";
+
+				interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
+						 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
+						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+						 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
+						<&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
+						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+				interconnect-names = "qup-core",
+						     "qup-config",
+						     "qup-memory";
+
+				dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
+				       <&gpi_dma1 1 3 QCOM_GPI_I2C>;
+				dma-names = "tx",
+					    "rx";
+
+				pinctrl-0 = <&qup_i2c3_data_clk>;
+				pinctrl-names = "default";
+
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				status = "disabled";
+			};
+
+			spi3: spi@a8c000 {
+				compatible = "qcom,geni-spi";
+				reg = <0x0 0x00a8c000 0x0 0x4000>;
+
+				interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
+
+				clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
+				clock-names = "se";
+
+				interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
+						 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
+						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+						 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
+						<&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
+						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+				interconnect-names = "qup-core",
+						     "qup-config",
+						     "qup-memory";
+
+				dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>,
+				       <&gpi_dma1 1 3 QCOM_GPI_SPI>;
+				dma-names = "tx",
+					    "rx";
+
+				pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>;
+				pinctrl-names = "default";
+
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				status = "disabled";
+			};
+
+			i2c4: i2c@a90000 {
+				compatible = "qcom,geni-i2c";
+				reg = <0x0 0x00a90000 0x0 0x4000>;
+
+				interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
+
+				clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
+				clock-names = "se";
+
+				interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
+						 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
+						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+						 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
+						<&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
+						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+				interconnect-names = "qup-core",
+						     "qup-config",
+						     "qup-memory";
+
+				dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
+				       <&gpi_dma1 1 4 QCOM_GPI_I2C>;
+				dma-names = "tx",
+					    "rx";
+
+				pinctrl-0 = <&qup_i2c4_data_clk>;
+				pinctrl-names = "default";
+
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				status = "disabled";
+			};
+
+			spi4: spi@a90000 {
+				compatible = "qcom,geni-spi";
+				reg = <0x0 0x00a90000 0x0 0x4000>;
+
+				interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
+
+				clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
+				clock-names = "se";
+
+				interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
+						 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
+						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+						 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
+						<&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
+						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+				interconnect-names = "qup-core",
+						     "qup-config",
+						     "qup-memory";
+
+				dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>,
+				       <&gpi_dma1 1 4 QCOM_GPI_SPI>;
+				dma-names = "tx",
+					    "rx";
+
+				pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>;
+				pinctrl-names = "default";
+
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				status = "disabled";
+			};
+
+			i2c5: i2c@a94000 {
+				compatible = "qcom,geni-i2c";
+				reg = <0x0 0x00a94000 0x0 0x4000>;
+
+				interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
+
+				clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
+				clock-names = "se";
+
+				interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
+						 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
+						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+						 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
+						<&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
+						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+				interconnect-names = "qup-core",
+						     "qup-config",
+						     "qup-memory";
+
+				dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>,
+				       <&gpi_dma1 1 5 QCOM_GPI_I2C>;
+				dma-names = "tx",
+					    "rx";
+
+				pinctrl-0 = <&qup_i2c5_data_clk>;
+				pinctrl-names = "default";
+
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				status = "disabled";
+			};
+
+			spi5: spi@a94000 {
+				compatible = "qcom,geni-spi";
+				reg = <0x0 0x00a94000 0x0 0x4000>;
+
+				interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
+
+				clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
+				clock-names = "se";
+
+				interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
+						 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
+						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+						 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
+						<&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
+						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+				interconnect-names = "qup-core",
+						     "qup-config",
+						     "qup-memory";
+
+				dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>,
+				       <&gpi_dma1 1 5 QCOM_GPI_SPI>;
+				dma-names = "tx",
+					    "rx";
+
+				pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>;
+				pinctrl-names = "default";
+
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				status = "disabled";
+			};
+
+			i2c6: i2c@a98000 {
+				compatible = "qcom,geni-i2c";
+				reg = <0x0 0x00a98000 0x0 0x4000>;
+
+				interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>;
+
+				clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
+				clock-names = "se";
+
+				interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
+						 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
+						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+						 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
+						<&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
+						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+				interconnect-names = "qup-core",
+						     "qup-config",
+						     "qup-memory";
+
+				dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>,
+				       <&gpi_dma1 1 6 QCOM_GPI_I2C>;
+				dma-names = "tx",
+					    "rx";
+
+				pinctrl-0 = <&qup_i2c6_data_clk>;
+				pinctrl-names = "default";
+
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				status = "disabled";
+			};
+
+			spi6: spi@a98000 {
+				compatible = "qcom,geni-spi";
+				reg = <0x0 0x00a98000 0x0 0x4000>;
+
+				interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>;
+
+				clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
+				clock-names = "se";
+
+				interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
+						 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
+						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+						 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
+						<&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
+						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+				interconnect-names = "qup-core",
+						     "qup-config",
+						     "qup-memory";
+
+				dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>,
+				       <&gpi_dma1 1 6 QCOM_GPI_SPI>;
+				dma-names = "tx",
+					    "rx";
+
+				pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>;
+				pinctrl-names = "default";
+
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				status = "disabled";
+			};
+
+			uart7: serial@a9c000 {
+				compatible = "qcom,geni-debug-uart";
+				reg = <0x0 0x00a9c000 0x0 0x4000>;
+
+				interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>;
+
+				clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
+				clock-names = "se";
+
+				interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
+						 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
+						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+						 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>;
+				interconnect-names = "qup-core",
+						     "qup-config";
+
+
+				pinctrl-0 = <&qup_uart7_default>;
+				pinctrl-names = "default";
+
+				status = "disabled";
+			};
+		};
+
+		cnoc_main: interconnect@1500000 {
+			compatible = "qcom,sm8750-cnoc-main";
+			reg = <0x0 0x01500000 0x0 0x16080>;
+			qcom,bcm-voters = <&apps_bcm_voter>;
+			#interconnect-cells = <2>;
+		};
+
+		config_noc: interconnect@1600000 {
+			compatible = "qcom,sm8750-config-noc";
+			reg = <0x0 0x01600000 0x0 0x6200>;
+			qcom,bcm-voters = <&apps_bcm_voter>;
+			#interconnect-cells = <2>;
+		};
+
+		system_noc: interconnect@1680000 {
+			compatible = "qcom,sm8750-system-noc";
+			reg = <0x0 0x01680000 0x0 0x1d080>;
+			qcom,bcm-voters = <&apps_bcm_voter>;
+			#interconnect-cells = <2>;
+		};
+
+		pcie_noc: interconnect@16c0000 {
+			compatible = "qcom,sm8750-pcie-anoc";
+			reg = <0x0 0x016c0000 0x0 0x11400>;
+			qcom,bcm-voters = <&apps_bcm_voter>;
+			#interconnect-cells = <2>;
+			clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
+				 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>;
+
+		};
+
+		aggre1_noc: interconnect@16e0000 {
+			compatible = "qcom,sm8750-aggre1-noc";
+			reg = <0x0 0x016e0000 0x0 0x16400>;
+			qcom,bcm-voters = <&apps_bcm_voter>;
+			#interconnect-cells = <2>;
+			clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
+				 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>;
+
+		};
+
+		aggre2_noc: interconnect@1700000 {
+			compatible = "qcom,sm8750-aggre2-noc";
+			reg = <0x0 0x01700000 0x0 0x1f400>;
+			qcom,bcm-voters = <&apps_bcm_voter>;
+			#interconnect-cells = <2>;
+			clocks = <&rpmhcc RPMH_IPA_CLK>;
+		};
+
+		mmss_noc: interconnect@1780000 {
+			compatible = "qcom,sm8750-mmss-noc";
+			reg = <0x0 0x01780000 0x0 0x5b800>;
+			qcom,bcm-voters = <&apps_bcm_voter>;
+			#interconnect-cells = <2>;
+		};
+
+		tcsr_mutex: hwlock@1f40000 {
+			compatible = "qcom,tcsr-mutex";
+			reg = <0x0 0x01f40000 0x0 0x20000>;
+			#hwlock-cells = <1>;
+		};
+
+		lpass_ag_noc: interconnect@7e40000 {
+			compatible = "qcom,sm8750-lpass-ag-noc";
+			reg = <0x0 0x07e40000 0x0 0xe080>;
+			qcom,bcm-voters = <&apps_bcm_voter>;
+			#interconnect-cells = <2>;
+		};
+
+		lpass_lpiaon_noc: interconnect@7400000 {
+			compatible = "qcom,sm8750-lpass-lpiaon-noc";
+			reg = <0x0 0x07400000 0x0 0x19080>;
+			qcom,bcm-voters = <&apps_bcm_voter>;
+			#interconnect-cells = <2>;
+		};
+
+		lpass_lpicx_noc: interconnect@7420000 {
+			compatible = "qcom,sm8750-lpass-lpicx-noc";
+			reg = <0x0 0x07420000 0x0 0x44080>;
+			qcom,bcm-voters = <&apps_bcm_voter>;
+			#interconnect-cells = <2>;
+		};
+
+		pdc: interrupt-controller@b220000 {
+			compatible = "qcom,sm8750-pdc", "qcom,pdc";
+			reg = <0x0 0x0b220000 0x0 0x10000>, <0x0 0x164400f0 0x0 0x64>;
+
+			qcom,pdc-ranges = <0 745 51>, <51 527 47>,
+					  <98 609 32>, <130 717 12>,
+					  <142 251 5>, <147 796 16>;
+			#interrupt-cells = <2>;
+			interrupt-parent = <&intc>;
+			interrupt-controller;
+		};
+
+		spmi_bus: spmi@c400000 {
+			compatible = "qcom,spmi-pmic-arb";
+			reg = <0x0 0x0c400000 0x0 0x3000>,
+			      <0x0 0x0c500000 0x0 0x400000>,
+			      <0x0 0x0c440000 0x0 0x80000>,
+			      <0x0 0x0c4c0000 0x0 0x10000>,
+			      <0x0 0x0c42d000 0x0 0x4000>;
+			reg-names = "core",
+				    "chnls",
+				    "obsrvr",
+				    "intr",
+				    "cnfg";
+
+			interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "periph_irq";
+
+			qcom,ee = <0>;
+			qcom,channel = <0>;
+			qcom,bus-id = <0>;
+
+			interrupt-controller;
+			#interrupt-cells = <4>;
+
+			#address-cells = <2>;
+			#size-cells = <0>;
+		};
+
+		tlmm: pinctrl@f100000 {
+			compatible = "qcom,sm8750-tlmm";
+			reg = <0x0 0x0f100000 0x0 0x102000>;
+
+			interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
+
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+
+			gpio-ranges = <&tlmm 0 0 216>;
+			wakeup-parent = <&pdc>;
+
+			hub_i2c0_data_clk: hub-i2c0-data-clk-state {
+				/* SDA, SCL */
+				pins = "gpio64", "gpio65";
+				function = "i2chub0_se0";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+
+			hub_i2c1_data_clk: hub-i2c1-data-clk-state {
+				/* SDA, SCL */
+				pins = "gpio66", "gpio67";
+				function = "i2chub0_se1";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+
+			hub_i2c2_data_clk: hub-i2c2-data-clk-state {
+				/* SDA, SCL */
+				pins = "gpio68", "gpio69";
+				function = "i2chub0_se2";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+
+			hub_i2c3_data_clk: hub-i2c3-data-clk-state {
+				/* SDA, SCL */
+				pins = "gpio70", "gpio71";
+				function = "i2chub0_se3";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+
+			hub_i2c4_data_clk: hub-i2c4-data-clk-state {
+				/* SDA, SCL */
+				pins = "gpio72", "gpio73";
+				function = "i2chub0_se4";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+
+			hub_i2c5_data_clk: hub-i2c5-data-clk-state {
+				/* SDA, SCL */
+				pins = "gpio74", "gpio75";
+				function = "i2chub0_se5";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+
+			hub_i2c6_data_clk: hub-i2c6-data-clk-state {
+				/* SDA, SCL */
+				pins = "gpio76", "gpio77";
+				function = "i2chub0_se6";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+
+			hub_i2c7_data_clk: hub-i2c7-data-clk-state {
+				/* SDA, SCL */
+				pins = "gpio82", "gpio83";
+				function = "i2chub0_se7";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+
+			hub_i2c8_data_clk: hub-i2c8-data-clk-state {
+				/* SDA, SCL */
+				pins = "gpio206", "gpio207";
+				function = "i2chub0_se8";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+
+			hub_i2c9_data_clk: hub-i2c9-data-clk-state {
+				/* SDA, SCL */
+				pins = "gpio80", "gpio81";
+				function = "i2chub0_se9";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+
+			pcie0_default_state: pcie0-default-state {
+				perst-pins {
+					pins = "gpio102";
+					function = "gpio";
+					drive-strength = <2>;
+					bias-pull-down;
+				};
+
+				clkreq-pins {
+					pins = "gpio103";
+					function = "pcie0_clk_req_n";
+					drive-strength = <2>;
+					bias-pull-up;
+				};
+
+				wake-pins {
+					pins = "gpio104";
+					function = "gpio";
+					drive-strength = <2>;
+					bias-pull-up;
+				};
+			};
+
+			qup_i2c0_data_clk: qup-i2c0-data-clk-state {
+				/* SDA, SCL */
+				pins = "gpio32", "gpio33";
+				function = "qup1_se0";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+
+			qup_i2c1_data_clk: qup-i2c1-data-clk-state {
+				/* SDA, SCL */
+				pins = "gpio36", "gpio37";
+				function = "qup1_se1";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+
+			qup_i2c2_data_clk: qup-i2c2-data-clk-state {
+				/* SDA, SCL */
+				pins = "gpio40", "gpio41";
+				function = "qup1_se2";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+
+			qup_i2c3_data_clk: qup-i2c3-data-clk-state {
+				/* SDA, SCL */
+				pins = "gpio44", "gpio45";
+				function = "qup1_se3";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+
+			qup_i2c4_data_clk: qup-i2c4-data-clk-state {
+				/* SDA, SCL */
+				pins = "gpio48", "gpio49";
+				function = "qup1_se4";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+
+			qup_i2c5_data_clk: qup-i2c5-data-clk-state {
+				/* SDA, SCL */
+				pins = "gpio52", "gpio53";
+				function = "qup1_se5";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+
+			qup_i2c6_data_clk: qup-i2c6-data-clk-state {
+				/* SDA, SCL */
+				pins = "gpio56", "gpio57";
+				function = "qup1_se6";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+
+			qup_i2c8_data_clk: qup-i2c8-data-clk-state {
+				/* SDA, SCL */
+				pins = "gpio0", "gpio1";
+				function = "qup2_se0";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+
+			qup_i2c9_data_clk: qup-i2c9-data-clk-state {
+				/* SDA, SCL */
+				pins = "gpio4", "gpio5";
+				function = "qup2_se1";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+
+			qup_i2c10_data_clk: qup-i2c10-data-clk-state {
+				/* SDA, SCL */
+				pins = "gpio8", "gpio9";
+				function = "qup2_se2";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+
+			qup_i2c11_data_clk: qup-i2c11-data-clk-state {
+				/* SDA, SCL */
+				pins = "gpio12", "gpio13";
+				function = "qup2_se3";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+
+			qup_i2c12_data_clk: qup-i2c12-data-clk-state {
+				/* SDA, SCL */
+				pins = "gpio16", "gpio17";
+				function = "qup2_se4";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+
+			qup_i2c13_data_clk: qup-i2c13-data-clk-state {
+				/* SDA, SCL */
+				pins = "gpio20", "gpio21";
+				function = "qup2_se5";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+
+			qup_i2c15_data_clk: qup-i2c15-data-clk-state {
+				/* SDA, SCL */
+				pins = "gpio28", "gpio29";
+				function = "qup2_se7";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+
+			qup_spi0_cs: qup-spi0-cs-state {
+				pins = "gpio35";
+				function = "qup1_se0";
+				drive-strength = <6>;
+				bias-disable;
+			};
+
+			qup_spi0_data_clk: qup-spi0-data-clk-state {
+				/* MISO, MOSI, CLK */
+				pins = "gpio32", "gpio33", "gpio34";
+				function = "qup1_se0";
+				drive-strength = <6>;
+				bias-disable;
+			};
+
+			qup_spi1_cs: qup-spi1-cs-state {
+				pins = "gpio39";
+				function = "qup1_se1";
+				drive-strength = <6>;
+				bias-disable;
+			};
+
+			qup_spi1_data_clk: qup-spi1-data-clk-state {
+				/* MISO, MOSI, CLK */
+				pins = "gpio36", "gpio37", "gpio38";
+				function = "qup1_se1";
+				drive-strength = <6>;
+				bias-disable;
+			};
+
+			qup_spi2_cs: qup-spi2-cs-state {
+				pins = "gpio43";
+				function = "qup1_se2";
+				drive-strength = <6>;
+				bias-disable;
+			};
+
+			qup_spi2_data_clk: qup-spi2-data-clk-state {
+				/* MISO, MOSI, CLK */
+				pins = "gpio40", "gpio41", "gpio42";
+				function = "qup1_se2";
+				drive-strength = <6>;
+				bias-disable;
+			};
+
+			qup_spi3_cs: qup-spi3-cs-state {
+				pins = "gpio47";
+				function = "qup1_se3";
+				drive-strength = <6>;
+				bias-disable;
+			};
+
+			qup_spi3_data_clk: qup-spi3-data-clk-state {
+				/* MISO, MOSI, CLK */
+				pins = "gpio44", "gpio45", "gpio46";
+				function = "qup1_se3";
+				drive-strength = <6>;
+				bias-disable;
+			};
+
+			qup_spi4_cs: qup-spi4-cs-state {
+				pins = "gpio51";
+				function = "qup1_se4";
+				drive-strength = <6>;
+				bias-disable;
+			};
+
+			qup_spi4_data_clk: qup-spi4-data-clk-state {
+				/* MISO, MOSI, CLK */
+				pins = "gpio48", "gpio49", "gpio50";
+				function = "qup1_se4";
+				drive-strength = <6>;
+				bias-disable;
+			};
+
+			qup_spi5_cs: qup-spi5-cs-state {
+				pins = "gpio55";
+				function = "qup1_se5";
+				drive-strength = <6>;
+				bias-disable;
+			};
+
+			qup_spi5_data_clk: qup-spi5-data-clk-state {
+				/* MISO, MOSI, CLK */
+				pins = "gpio52", "gpio53", "gpio54";
+				function = "qup1_se5";
+				drive-strength = <6>;
+				bias-disable;
+			};
+
+			qup_spi6_cs: qup-spi6-cs-state {
+				pins = "gpio59";
+				function = "qup1_se6";
+				drive-strength = <6>;
+				bias-disable;
+			};
+
+			qup_spi6_data_clk: qup-spi6-data-clk-state {
+				/* MISO, MOSI, CLK */
+				pins = "gpio56", "gpio57", "gpio58";
+				function = "qup1_se6";
+				drive-strength = <6>;
+				bias-disable;
+			};
+
+			qup_spi8_cs: qup-spi8-cs-state {
+				pins = "gpio3";
+				function = "qup2_se0";
+				drive-strength = <6>;
+				bias-disable;
+			};
+
+			qup_spi8_data_clk: qup-spi8-data-clk-state {
+				/* MISO, MOSI, CLK */
+				pins = "gpio0", "gpio1", "gpio2";
+				function = "qup2_se0";
+				drive-strength = <6>;
+				bias-disable;
+			};
+
+			qup_spi9_cs: qup-spi9-cs-state {
+				pins = "gpio7";
+				function = "qup2_se1";
+				drive-strength = <6>;
+				bias-disable;
+			};
+
+			qup_spi9_data_clk: qup-spi9-data-clk-state {
+				/* MISO, MOSI, CLK */
+				pins = "gpio4", "gpio5", "gpio6";
+				function = "qup2_se1";
+				drive-strength = <6>;
+				bias-disable;
+			};
+
+			qup_spi10_cs: qup-spi10-cs-state {
+				pins = "gpio11";
+				function = "qup2_se2";
+				drive-strength = <6>;
+				bias-disable;
+			};
+
+			qup_spi10_data_clk: qup-spi10-data-clk-state {
+				/* MISO, MOSI, CLK */
+				pins = "gpio8", "gpio9", "gpio10";
+				function = "qup2_se2";
+				drive-strength = <6>;
+				bias-disable;
+			};
+
+			qup_spi11_cs: qup-spi11-cs-state {
+				pins = "gpio15";
+				function = "qup2_se3";
+				drive-strength = <6>;
+				bias-disable;
+			};
+
+			qup_spi11_data_clk: qup-spi11-data-clk-state {
+				/* MISO, MOSI, CLK */
+				pins = "gpio12", "gpio13", "gpio14";
+				function = "qup2_se3";
+				drive-strength = <6>;
+				bias-disable;
+			};
+
+			qup_spi12_cs: qup-spi12-cs-state {
+				pins = "gpio19";
+				function = "qup2_se4";
+				drive-strength = <6>;
+				bias-disable;
+			};
+
+			qup_spi12_data_clk: qup-spi12-data-clk-state {
+				/* MISO, MOSI, CLK */
+				pins = "gpio16", "gpio17", "gpio18";
+				function = "qup2_se4";
+				drive-strength = <6>;
+				bias-disable;
+			};
+
+			qup_spi13_cs: qup-spi13-cs-state {
+				pins = "gpio23";
+				function = "qup2_se5";
+				drive-strength = <6>;
+				bias-pull-up;
+			};
+
+			qup_spi13_data_clk: qup-spi13-data-clk-state {
+				/* MISO, MOSI, CLK */
+				pins = "gpio20", "gpio21", "gpio22";
+				function = "qup2_se5";
+				drive-strength = <6>;
+				bias-disable;
+			};
+
+			qup_spi15_cs: qup-spi15-cs-state {
+				pins = "gpio31";
+				function = "qup2_se7";
+				drive-strength = <6>;
+				bias-disable;
+			};
+
+			qup_spi15_data_clk: qup-spi15-data-clk-state {
+				/* MISO, MOSI, CLK */
+				pins = "gpio28", "gpio29", "gpio30";
+				function = "qup2_se7";
+				drive-strength = <6>;
+				bias-disable;
+			};
+
+			qup_uart7_default: qup-uart7-default-state {
+				/* TX, RX */
+				pins = "gpio62", "gpio63";
+				function = "qup1_se7";
+				drive-strength = <2>;
+				bias-disable;
+			};
+
+			qup_uart14_default: qup-uart14-default-state {
+				/* TX, RX */
+				pins = "gpio26", "gpio27";
+				function = "qup2_se6";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+
+			qup_uart14_cts_rts: qup-uart14-cts-rts-state {
+				/* CTS, RTS */
+				pins = "gpio24", "gpio25";
+				function = "qup2_se6";
+				drive-strength = <2>;
+				bias-pull-down;
+			};
+
+			sdc2_sleep: sdc2-sleep-state {
+				clk-pins {
+					pins = "sdc2_clk";
+					drive-strength = <2>;
+					bias-disable;
+				};
+
+				cmd-pins {
+					pins = "sdc2_cmd";
+					drive-strength = <2>;
+					bias-pull-up;
+				};
+
+				data-pins {
+					pins = "sdc2_data";
+					drive-strength = <2>;
+					bias-pull-up;
+				};
+			};
+
+			sdc2_default: sdc2-default-state {
+				clk-pins {
+					pins = "sdc2_clk";
+					drive-strength = <16>;
+					bias-disable;
+				};
+
+				cmd-pins {
+					pins = "sdc2_cmd";
+					drive-strength = <10>;
+					bias-pull-up;
+				};
+
+				data-pins {
+					pins = "sdc2_data";
+					drive-strength = <10>;
+					bias-pull-up;
+				};
+			};
+		};
+
+		tcsrcc: clock-controller@f204008 {
+			compatible = "qcom,sm8750-tcsr", "syscon";
+			reg = <0x0 0x0f204008 0x0 0x3004>;
+
+			clocks = <&rpmhcc RPMH_CXO_CLK>;
+
+			#clock-cells = <1>;
+			#reset-cells = <1>;
+		};
+
+		apps_smmu: iommu@15000000 {
+			compatible = "qcom,sm8750-smmu-500", "qcom,smmu-500", "arm,mmu-500";
+			reg = <0x0 0x15000000 0x0 0x100000>;
+
+			interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 490 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 491 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 492 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 493 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 494 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 495 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 497 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 498 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 499 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 500 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 501 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 502 IRQ_TYPE_LEVEL_HIGH>;
+
+			#iommu-cells = <2>;
+			#global-interrupts = <1>;
+
+			dma-coherent;
+		};
+
+		intc: interrupt-controller@16000000 {
+			compatible = "arm,gic-v3";
+			reg = <0x0 0x16000000 0x0 0x10000>,
+			      <0x0 0x16080000 0x0 0x200000>;
+
+			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+
+			#interrupt-cells = <3>;
+			interrupt-controller;
+
+			#redistributor-regions = <1>;
+			redistributor-stride = <0x0 0x40000>;
+
+			#address-cells = <2>;
+			#size-cells = <2>;
+			ranges;
+
+			gic_its: msi-controller@16040000 {
+				compatible = "arm,gic-v3-its";
+				reg = <0x0 0x16040000 0x0 0x20000>;
+
+				msi-controller;
+				#msi-cells = <1>;
+			};
+		};
+
+		apps_rsc: rsc@16500000 {
+			compatible = "qcom,rpmh-rsc";
+			reg = <0x0 0x16500000 0x0 0x10000>,
+			      <0x0 0x16510000 0x0 0x10000>,
+			      <0x0 0x16520000 0x0 0x10000>;
+			reg-names = "drv-0",
+				    "drv-1",
+				    "drv-2";
+
+			interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
+			qcom,tcs-offset = <0xd00>;
+			qcom,drv-id = <2>;
+			qcom,tcs-config = <ACTIVE_TCS    3>, <SLEEP_TCS     2>,
+					  <WAKE_TCS      2>, <CONTROL_TCS   0>;
+
+			label = "apps_rsc";
+
+			power-domains = <&system_pd>;
+
+			apps_bcm_voter: bcm-voter {
+				compatible = "qcom,bcm-voter";
+			};
+
+			rpmhcc: clock-controller {
+				compatible = "qcom,sm8750-rpmh-clk";
+
+				clocks = <&xo_board>;
+				clock-names = "xo";
+
+				#clock-cells = <1>;
+			};
+
+			rpmhpd: power-controller {
+				compatible = "qcom,sm8750-rpmhpd";
+
+				operating-points-v2 = <&rpmhpd_opp_table>;
+
+				#power-domain-cells = <1>;
+
+				rpmhpd_opp_table: opp-table {
+					compatible = "operating-points-v2";
+
+					rpmhpd_opp_ret: opp-16 {
+						opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
+					};
+
+					rpmhpd_opp_min_svs: opp-48 {
+						opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
+					};
+
+					rpmhpd_opp_low_svs_d3: opp-50 {
+						opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D3>;
+					};
+
+					rpmhpd_opp_low_svs_d2: opp-52 {
+						opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>;
+					};
+
+					rpmhpd_opp_low_svs_d1: opp-56 {
+						opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
+					};
+
+					rpmhpd_opp_low_svs_d0: opp-60 {
+						opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>;
+					};
+
+					rpmhpd_opp_low_svs: opp-64 {
+						opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
+					};
+
+					rpmhpd_opp_low_svs_l1: opp-80 {
+						opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>;
+					};
+
+					rpmhpd_opp_svs: opp-128 {
+						opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
+					};
+
+					rpmhpd_opp_svs_l0: opp-144 {
+						opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
+					};
+
+					rpmhpd_opp_svs_l1: opp-192 {
+						opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
+					};
+
+					rpmhpd_opp_svs_l2: opp-224 {
+						opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
+					};
+
+					rpmhpd_opp_nom: opp-256 {
+						opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
+					};
+
+					rpmhpd_opp_nom_l1: opp-320 {
+						opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
+					};
+
+					rpmhpd_opp_nom_l2: opp-336 {
+						opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
+					};
+
+					rpmhpd_opp_turbo: opp-384 {
+						opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
+					};
+
+					rpmhpd_opp_turbo_l1: opp-416 {
+						opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
+					};
+
+					rpmhpd_opp_turbo_l2: opp-432 {
+						opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L2>;
+					};
+
+					rpmhpd_opp_turbo_l3: opp-448 {
+						opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L3>;
+					};
+
+					rpmhpd_opp_turbo_l4: opp-452 {
+						opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L4>;
+					};
+
+					rpmhpd_opp_super_turbo_no_cpr: opp-480 {
+						opp-level =
+							<RPMH_REGULATOR_LEVEL_SUPER_TURBO_NO_CPR>;
+					};
+				};
+			};
+		};
+
+		timer@16800000 {
+			compatible = "arm,armv7-timer-mem";
+			reg = <0x0 0x16800000 0x0 0x1000>;
+
+			#address-cells = <2>;
+			#size-cells = <1>;
+			ranges = <0 0 0 0 0x20000000>;
+
+			frame@16801000 {
+				reg = <0x0 0x16801000 0x1000>,
+				      <0x0 0x16802000 0x1000>;
+
+				interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+
+				frame-number = <0>;
+			};
+
+			frame@16803000 {
+				reg = <0x0 0x16803000 0x1000>;
+
+				interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+
+				frame-number = <1>;
+
+				status = "disabled";
+			};
+
+			frame@16805000 {
+				reg = <0x0 0x16805000 0x1000>;
+
+				interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+
+				frame-number = <2>;
+
+				status = "disabled";
+			};
+
+			frame@16807000 {
+				reg = <0x0 0x16807000 0x1000>;
+
+				interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+
+				frame-number = <3>;
+
+				status = "disabled";
+			};
+
+			frame@16809000 {
+				reg = <0x0 0x16809000 0x1000>;
+
+				interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+
+				frame-number = <4>;
+
+				status = "disabled";
+			};
+
+			frame@1680b000 {
+				reg = <0x0 0x1680b000 0x1000>;
+
+				interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
+
+				frame-number = <5>;
+
+				status = "disabled";
+			};
+
+			frame@1680d000 {
+				reg = <0x0 0x1680d000 0x1000>;
+
+				interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+
+				frame-number = <6>;
+
+				status = "disabled";
+			};
+		};
+
+		gem_noc: interconnect@24100000 {
+			compatible = "qcom,sm8750-gem-noc";
+			reg = <0x0 0x24100000 0x0 0x14b080>;
+			qcom,bcm-voters = <&apps_bcm_voter>;
+			#interconnect-cells = <2>;
+		};
+
+		nsp_noc: interconnect@320c0000 {
+			compatible = "qcom,sm8750-nsp-noc";
+			reg = <0x0 0x320c0000 0x0 0x13080>;
+			qcom,bcm-voters = <&apps_bcm_voter>;
+			#interconnect-cells = <2>;
+		};
+	};
+
+	timer {
+		compatible = "arm,armv8-timer";
+
+		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
+			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
+			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
+			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
+	};
+};
diff --git a/dts/upstream/src/arm64/qcom/x1e001de-devkit.dts b/dts/upstream/src/arm64/qcom/x1e001de-devkit.dts
new file mode 100644
index 00000000000..5e3970b26e2
--- /dev/null
+++ b/dts/upstream/src/arm64/qcom/x1e001de-devkit.dts
@@ -0,0 +1,1371 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
+
+#include "x1e80100.dtsi"
+#include "x1e80100-pmics.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. X1E001DE Snapdragon Devkit for Windows";
+	compatible = "qcom,x1e001de-devkit", "qcom,x1e001de", "qcom,x1e80100";
+
+	aliases {
+		serial0 = &uart21;
+	};
+
+	wcd938x: audio-codec {
+		compatible = "qcom,wcd9385-codec";
+
+		pinctrl-names = "default";
+		pinctrl-0 = <&wcd_default>;
+
+		qcom,micbias1-microvolt = <1800000>;
+		qcom,micbias2-microvolt = <1800000>;
+		qcom,micbias3-microvolt = <1800000>;
+		qcom,micbias4-microvolt = <1800000>;
+		qcom,mbhc-buttons-vthreshold-microvolt = <75000 150000 237000 500000 500000 500000 500000 500000>;
+		qcom,mbhc-headset-vthreshold-microvolt = <1700000>;
+		qcom,mbhc-headphone-vthreshold-microvolt = <50000>;
+		qcom,rx-device = <&wcd_rx>;
+		qcom,tx-device = <&wcd_tx>;
+
+		reset-gpios = <&tlmm 191 GPIO_ACTIVE_LOW>;
+
+		vdd-buck-supply = <&vreg_l15b_1p8>;
+		vdd-rxtx-supply = <&vreg_l15b_1p8>;
+		vdd-io-supply = <&vreg_l15b_1p8>;
+		vdd-mic-bias-supply = <&vreg_bob1>;
+
+		#sound-dai-cells = <1>;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	pmic-glink {
+		compatible = "qcom,x1e80100-pmic-glink",
+			     "qcom,sm8550-pmic-glink",
+			     "qcom,pmic-glink";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		orientation-gpios = <&tlmm 121 GPIO_ACTIVE_HIGH>,
+				    <&tlmm 123 GPIO_ACTIVE_HIGH>,
+				    <&tlmm 125 GPIO_ACTIVE_HIGH>;
+
+		/* Back panel port closer to the RJ45 connector */
+		connector@0 {
+			compatible = "usb-c-connector";
+			reg = <0>;
+			power-role = "dual";
+			data-role = "dual";
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					reg = <0>;
+
+					pmic_glink_ss0_hs_in: endpoint {
+						remote-endpoint = <&usb_1_ss0_dwc3_hs>;
+					};
+				};
+
+				port@1 {
+					reg = <1>;
+
+					pmic_glink_ss0_ss_in: endpoint {
+						remote-endpoint = <&retimer_ss0_ss_out>;
+					};
+				};
+
+				port@2 {
+					reg = <2>;
+
+					pmic_glink_ss0_con_sbu_in: endpoint {
+						remote-endpoint = <&retimer_ss0_con_sbu_out>;
+					};
+				};
+			};
+		};
+
+		/* Back panel port closer to the audio jack */
+		connector@1 {
+			compatible = "usb-c-connector";
+			reg = <1>;
+			power-role = "dual";
+			data-role = "host";
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					reg = <0>;
+
+					pmic_glink_ss1_hs_in: endpoint {
+						remote-endpoint = <&usb_1_ss1_dwc3_hs>;
+					};
+				};
+
+				port@1 {
+					reg = <1>;
+
+					pmic_glink_ss1_ss_in: endpoint {
+						remote-endpoint = <&retimer_ss1_ss_out>;
+					};
+				};
+
+				port@2 {
+					reg = <2>;
+
+					pmic_glink_ss1_con_sbu_in: endpoint {
+						remote-endpoint = <&retimer_ss1_con_sbu_out>;
+					};
+				};
+			};
+		};
+
+		/* Front panel port */
+		connector@2 {
+			compatible = "usb-c-connector";
+			reg = <2>;
+			power-role = "dual";
+			data-role = "host";
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					reg = <0>;
+
+					pmic_glink_ss2_hs_in: endpoint {
+						remote-endpoint = <&usb_1_ss2_dwc3_hs>;
+					};
+				};
+
+				port@1 {
+					reg = <1>;
+
+					pmic_glink_ss2_ss_in: endpoint {
+						remote-endpoint = <&retimer_ss2_ss_out>;
+					};
+				};
+
+				port@2 {
+					reg = <2>;
+
+					pmic_glink_ss2_con_sbu_in: endpoint {
+						remote-endpoint = <&retimer_ss2_con_sbu_out>;
+					};
+				};
+			};
+		};
+	};
+
+	reserved-memory {
+		linux,cma {
+			compatible = "shared-dma-pool";
+			size = <0x0 0x8000000>;
+			reusable;
+			linux,cma-default;
+		};
+	};
+
+	sound {
+		compatible = "qcom,x1e80100-sndcard";
+		model = "X1E001DE-DEVKIT";
+		audio-routing = "IN1_HPHL", "HPHL_OUT",
+				"IN2_HPHR", "HPHR_OUT",
+				"AMIC2", "MIC BIAS2",
+				"TX SWR_INPUT1", "ADC2_OUTPUT";
+
+		wcd-playback-dai-link {
+			link-name = "WCD Playback";
+
+			cpu {
+				sound-dai = <&q6apmbedai RX_CODEC_DMA_RX_0>;
+			};
+
+			codec {
+				sound-dai = <&wcd938x 0>, <&swr1 0>, <&lpass_rxmacro 0>;
+			};
+
+			platform {
+				sound-dai = <&q6apm>;
+			};
+		};
+
+		wcd-capture-dai-link {
+			link-name = "WCD Capture";
+
+			cpu {
+				sound-dai = <&q6apmbedai TX_CODEC_DMA_TX_3>;
+			};
+
+			codec {
+				sound-dai = <&wcd938x 1>, <&swr2 1>, <&lpass_txmacro 0>;
+			};
+
+			platform {
+				sound-dai = <&q6apm>;
+			};
+		};
+	};
+
+	vreg_nvme: regulator-nvme {
+		compatible = "regulator-fixed";
+
+		regulator-name = "VREG_NVME_3P3";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+
+		gpio = <&tlmm 18 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+
+		pinctrl-names = "default";
+		pinctrl-0 = <&nvme_reg_en>;
+
+		regulator-boot-on;
+	};
+
+	vreg_rtmr0_1p15: regulator-rtmr0-1p15 {
+		compatible = "regulator-fixed";
+
+		regulator-name = "VREG_RTMR0_1P15";
+		regulator-min-microvolt = <1150000>;
+		regulator-max-microvolt = <1150000>;
+
+		gpio = <&pmc8380_5_gpios 8 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+
+		pinctrl-0 = <&usb0_pwr_1p15_en>;
+		pinctrl-names = "default";
+
+		regulator-boot-on;
+	};
+
+	vreg_rtmr0_1p8: regulator-rtmr0-1p8 {
+		compatible = "regulator-fixed";
+
+		regulator-name = "VREG_RTMR0_1P8";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+
+		gpio = <&pm8550ve_9_gpios 8 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+
+		pinctrl-0 = <&usb0_1p8_reg_en>;
+		pinctrl-names = "default";
+
+		regulator-boot-on;
+	};
+
+	vreg_rtmr0_3p3: regulator-rtmr0-3p3 {
+		compatible = "regulator-fixed";
+
+		regulator-name = "VREG_RTMR0_3P3";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+
+		gpio = <&pm8550_gpios 11 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+
+		pinctrl-0 = <&usb0_3p3_reg_en>;
+		pinctrl-names = "default";
+
+		regulator-boot-on;
+	};
+
+	vreg_rtmr1_1p15: regulator-rtmr1-1p15 {
+		compatible = "regulator-fixed";
+
+		regulator-name = "VREG_RTMR1_1P15";
+		regulator-min-microvolt = <1150000>;
+		regulator-max-microvolt = <1150000>;
+
+		gpio = <&tlmm 188 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+
+		pinctrl-0 = <&rtmr1_1p15_reg_en>;
+		pinctrl-names = "default";
+
+		regulator-boot-on;
+	};
+
+	vreg_rtmr1_1p8: regulator-rtmr1-1p8 {
+		compatible = "regulator-fixed";
+
+		regulator-name = "VREG_RTMR1_1P8";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+
+		gpio = <&tlmm 175 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+
+		pinctrl-0 = <&rtmr1_1p8_reg_en>;
+		pinctrl-names = "default";
+
+		regulator-boot-on;
+	};
+
+	vreg_rtmr1_3p3: regulator-rtmr1-3p3 {
+		compatible = "regulator-fixed";
+
+		regulator-name = "VREG_RTMR1_3P3";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+
+		gpio = <&tlmm 186 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+
+		pinctrl-0 = <&rtmr1_3p3_reg_en>;
+		pinctrl-names = "default";
+
+		regulator-boot-on;
+	};
+
+	vreg_rtmr2_1p15: regulator-rtmr2-1p15 {
+		compatible = "regulator-fixed";
+
+		regulator-name = "VREG_RTMR2_1P15";
+		regulator-min-microvolt = <1150000>;
+		regulator-max-microvolt = <1150000>;
+
+		gpio = <&tlmm 189 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+
+		pinctrl-0 = <&rtmr2_1p15_reg_en>;
+		pinctrl-names = "default";
+
+		regulator-boot-on;
+	};
+
+	vreg_rtmr2_1p8: regulator-rtmr2-1p8 {
+		compatible = "regulator-fixed";
+
+		regulator-name = "VREG_RTMR2_1P8";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+
+		gpio = <&tlmm 126 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+
+		pinctrl-0 = <&rtmr2_1p8_reg_en>;
+		pinctrl-names = "default";
+
+		regulator-boot-on;
+	};
+
+	vreg_rtmr2_3p3: regulator-rtmr2-3p3 {
+		compatible = "regulator-fixed";
+
+		regulator-name = "VREG_RTMR2_3P3";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+
+		gpio = <&tlmm 187 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+
+		pinctrl-0 = <&rtmr2_3p3_reg_en>;
+		pinctrl-names = "default";
+
+		regulator-boot-on;
+	};
+
+	vph_pwr: regulator-vph-pwr {
+		compatible = "regulator-fixed";
+
+		regulator-name = "vph_pwr";
+		regulator-min-microvolt = <3700000>;
+		regulator-max-microvolt = <3700000>;
+
+		regulator-always-on;
+		regulator-boot-on;
+	};
+
+	vreg_wwan: regulator-wwan {
+		compatible = "regulator-fixed";
+
+		regulator-name = "SDX_VPH_PWR";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+
+		gpio = <&tlmm 221 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+
+		pinctrl-0 = <&wwan_sw_en>;
+		pinctrl-names = "default";
+
+		regulator-boot-on;
+	};
+};
+
+&apps_rsc {
+	regulators-0 {
+		compatible = "qcom,pm8550-rpmh-regulators";
+		qcom,pmic-id = "b";
+
+		vdd-bob1-supply = <&vph_pwr>;
+		vdd-bob2-supply = <&vph_pwr>;
+		vdd-l1-l4-l10-supply = <&vreg_s4c_1p8>;
+		vdd-l2-l13-l14-supply = <&vreg_bob1>;
+		vdd-l5-l16-supply = <&vreg_bob1>;
+		vdd-l6-l7-supply = <&vreg_bob2>;
+		vdd-l8-l9-supply = <&vreg_bob1>;
+		vdd-l12-supply = <&vreg_s5j_1p2>;
+		vdd-l15-supply = <&vreg_s4c_1p8>;
+		vdd-l17-supply = <&vreg_bob2>;
+
+		vreg_bob1: bob1 {
+			regulator-name = "vreg_bob1";
+			regulator-min-microvolt = <3008000>;
+			regulator-max-microvolt = <3960000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_bob2: bob2 {
+			regulator-name = "vreg_bob2";
+			regulator-min-microvolt = <2504000>;
+			regulator-max-microvolt = <3008000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l1b_1p8: ldo1 {
+			regulator-name = "vreg_l1b_1p8";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l2b_3p0: ldo2 {
+			regulator-name = "vreg_l2b_3p0";
+			regulator-min-microvolt = <3072000>;
+			regulator-max-microvolt = <3100000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l4b_1p8: ldo4 {
+			regulator-name = "vreg_l4b_1p8";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l5b_3p0: ldo5 {
+			regulator-name = "vreg_l5b_3p0";
+			regulator-min-microvolt = <3000000>;
+			regulator-max-microvolt = <3000000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l6b_1p8: ldo6 {
+			regulator-name = "vreg_l6b_1p8";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <2960000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l7b_2p8: ldo7 {
+			regulator-name = "vreg_l7b_2p8";
+			regulator-min-microvolt = <2800000>;
+			regulator-max-microvolt = <2800000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l8b_3p0: ldo8 {
+			regulator-name = "vreg_l8b_3p0";
+			regulator-min-microvolt = <3072000>;
+			regulator-max-microvolt = <3072000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l9b_2p9: ldo9 {
+			regulator-name = "vreg_l9b_2p9";
+			regulator-min-microvolt = <2960000>;
+			regulator-max-microvolt = <2960000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l10b_1p8: ldo10 {
+			regulator-name = "vreg_l10b_1p8";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l12b_1p2: ldo12 {
+			regulator-name = "vreg_l12b_1p2";
+			regulator-min-microvolt = <1200000>;
+			regulator-max-microvolt = <1200000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l13b_3p0: ldo13 {
+			regulator-name = "vreg_l13b_3p0";
+			regulator-min-microvolt = <3072000>;
+			regulator-max-microvolt = <3100000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l14b_3p0: ldo14 {
+			regulator-name = "vreg_l14b_3p0";
+			regulator-min-microvolt = <3072000>;
+			regulator-max-microvolt = <3072000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l15b_1p8: ldo15 {
+			regulator-name = "vreg_l15b_1p8";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l16b_2p9: ldo16 {
+			regulator-name = "vreg_l16b_2p9";
+			regulator-min-microvolt = <2912000>;
+			regulator-max-microvolt = <2912000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l17b_2p5: ldo17 {
+			regulator-name = "vreg_l17b_2p5";
+			regulator-min-microvolt = <2504000>;
+			regulator-max-microvolt = <2504000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+	};
+
+	regulators-1 {
+		compatible = "qcom,pm8550ve-rpmh-regulators";
+		qcom,pmic-id = "c";
+
+		vdd-l1-supply = <&vreg_s5j_1p2>;
+		vdd-l2-supply = <&vreg_s1f_0p7>;
+		vdd-l3-supply = <&vreg_s1f_0p7>;
+		vdd-s4-supply = <&vph_pwr>;
+
+		vreg_s4c_1p8: smps4 {
+			regulator-name = "vreg_s4c_1p8";
+			regulator-min-microvolt = <1856000>;
+			regulator-max-microvolt = <2000000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l1c_1p2: ldo1 {
+			regulator-name = "vreg_l1c_1p2";
+			regulator-min-microvolt = <1200000>;
+			regulator-max-microvolt = <1200000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l2c_0p8: ldo2 {
+			regulator-name = "vreg_l2c_0p8";
+			regulator-min-microvolt = <880000>;
+			regulator-max-microvolt = <920000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l3c_0p8: ldo3 {
+			regulator-name = "vreg_l3c_0p8";
+			regulator-min-microvolt = <880000>;
+			regulator-max-microvolt = <920000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+	};
+
+	regulators-2 {
+		compatible = "qcom,pmc8380-rpmh-regulators";
+		qcom,pmic-id = "d";
+
+		vdd-l1-supply = <&vreg_s1f_0p7>;
+		vdd-l2-supply = <&vreg_s1f_0p7>;
+		vdd-l3-supply = <&vreg_s4c_1p8>;
+		vdd-s1-supply = <&vph_pwr>;
+
+		vreg_l1d_0p8: ldo1 {
+			regulator-name = "vreg_l1d_0p8";
+			regulator-min-microvolt = <880000>;
+			regulator-max-microvolt = <920000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l2d_0p9: ldo2 {
+			regulator-name = "vreg_l2d_0p9";
+			regulator-min-microvolt = <912000>;
+			regulator-max-microvolt = <920000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l3d_1p8: ldo3 {
+			regulator-name = "vreg_l3d_1p8";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+	};
+
+	regulators-3 {
+		compatible = "qcom,pmc8380-rpmh-regulators";
+		qcom,pmic-id = "e";
+
+		vdd-l2-supply = <&vreg_s1f_0p7>;
+		vdd-l3-supply = <&vreg_s5j_1p2>;
+
+		vreg_l2e_0p8: ldo2 {
+			regulator-name = "vreg_l2e_0p8";
+			regulator-min-microvolt = <880000>;
+			regulator-max-microvolt = <920000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l3e_1p2: ldo3 {
+			regulator-name = "vreg_l3e_1p2";
+			regulator-min-microvolt = <1200000>;
+			regulator-max-microvolt = <1200000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+	};
+
+	regulators-4 {
+		compatible = "qcom,pmc8380-rpmh-regulators";
+		qcom,pmic-id = "f";
+
+		vdd-l1-supply = <&vreg_s5j_1p2>;
+		vdd-l2-supply = <&vreg_s5j_1p2>;
+		vdd-l3-supply = <&vreg_s5j_1p2>;
+		vdd-s1-supply = <&vph_pwr>;
+
+		vreg_s1f_0p7: smps1 {
+			regulator-name = "vreg_s1f_0p7";
+			regulator-min-microvolt = <700000>;
+			regulator-max-microvolt = <1100000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l1f_1p0: ldo1 {
+			regulator-name = "vreg_l1f_1p0";
+			regulator-min-microvolt = <1024000>;
+			regulator-max-microvolt = <1024000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l2f_1p0: ldo2 {
+			regulator-name = "vreg_l2f_1p0";
+			regulator-min-microvolt = <1024000>;
+			regulator-max-microvolt = <1024000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l3f_1p0: ldo3 {
+			regulator-name = "vreg_l3f_1p0";
+			regulator-min-microvolt = <1024000>;
+			regulator-max-microvolt = <1024000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+	};
+
+	regulators-6 {
+		compatible = "qcom,pm8550ve-rpmh-regulators";
+		qcom,pmic-id = "i";
+
+		vdd-l1-supply = <&vreg_s4c_1p8>;
+		vdd-l2-supply = <&vreg_s5j_1p2>;
+		vdd-l3-supply = <&vreg_s1f_0p7>;
+		vdd-s1-supply = <&vph_pwr>;
+		vdd-s2-supply = <&vph_pwr>;
+
+		vreg_s1i_0p9: smps1 {
+			regulator-name = "vreg_s1i_0p9";
+			regulator-min-microvolt = <900000>;
+			regulator-max-microvolt = <920000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_s2i_1p0: smps2 {
+			regulator-name = "vreg_s2i_1p0";
+			regulator-min-microvolt = <1000000>;
+			regulator-max-microvolt = <1100000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l1i_1p8: ldo1 {
+			regulator-name = "vreg_l1i_1p8";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l2i_1p2: ldo2 {
+			regulator-name = "vreg_l2i_1p2";
+			regulator-min-microvolt = <1200000>;
+			regulator-max-microvolt = <1200000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l3i_0p8: ldo3 {
+			regulator-name = "vreg_l3i_0p8";
+			regulator-min-microvolt = <880000>;
+			regulator-max-microvolt = <920000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+	};
+
+	regulators-7 {
+		compatible = "qcom,pm8550ve-rpmh-regulators";
+		qcom,pmic-id = "j";
+
+		vdd-l1-supply = <&vreg_s1f_0p7>;
+		vdd-l2-supply = <&vreg_s5j_1p2>;
+		vdd-l3-supply = <&vreg_s1f_0p7>;
+		vdd-s5-supply = <&vph_pwr>;
+
+		vreg_s5j_1p2: smps5 {
+			regulator-name = "vreg_s5j_1p2";
+			regulator-min-microvolt = <1256000>;
+			regulator-max-microvolt = <1304000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l1j_0p8: ldo1 {
+			regulator-name = "vreg_l1j_0p8";
+			regulator-min-microvolt = <880000>;
+			regulator-max-microvolt = <920000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l2j_1p2: ldo2 {
+			regulator-name = "vreg_l2j_1p2";
+			regulator-min-microvolt = <1200000>;
+			regulator-max-microvolt = <1200000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l3j_0p8: ldo3 {
+			regulator-name = "vreg_l3j_0p8";
+			regulator-min-microvolt = <880000>;
+			regulator-max-microvolt = <920000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+	};
+};
+
+&gpu {
+	status = "okay";
+
+	zap-shader {
+		firmware-name = "qcom/x1e80100/Thundercomm/DEVKIT/qcdxkmsuc8380.mbn";
+	};
+};
+
+&i2c1 {
+	clock-frequency = <400000>;
+
+	status = "okay";
+
+	typec-mux@8 {
+		compatible = "parade,ps8830";
+		reg = <0x08>;
+
+		clocks = <&rpmhcc RPMH_RF_CLK5>;
+		clock-names = "xo";
+
+		vdd-supply = <&vreg_rtmr2_1p15>;
+		vdd33-supply = <&vreg_rtmr2_3p3>;
+		vdd33-cap-supply = <&vreg_rtmr2_3p3>;
+		vddar-supply = <&vreg_rtmr2_1p15>;
+		vddat-supply = <&vreg_rtmr2_1p15>;
+		vddio-supply = <&vreg_rtmr2_1p8>;
+
+		reset-gpios = <&tlmm 185 GPIO_ACTIVE_HIGH>;
+
+		orientation-switch;
+		retimer-switch;
+
+		ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@0 {
+				reg = <0>;
+
+				retimer_ss2_ss_out: endpoint {
+					remote-endpoint = <&pmic_glink_ss2_ss_in>;
+				};
+			};
+
+			port@1 {
+				reg = <1>;
+
+				retimer_ss2_ss_in: endpoint {
+					remote-endpoint = <&usb_1_ss2_qmpphy_out>;
+				};
+			};
+
+			port@2 {
+				reg = <2>;
+
+				retimer_ss2_con_sbu_out: endpoint {
+					remote-endpoint = <&pmic_glink_ss2_con_sbu_in>;
+				};
+			};
+		};
+	};
+};
+
+&i2c3 {
+	clock-frequency = <400000>;
+
+	status = "okay";
+
+	typec-mux@8 {
+		compatible = "parade,ps8830";
+		reg = <0x08>;
+
+		clocks = <&rpmhcc RPMH_RF_CLK3>;
+		clock-names = "xo";
+
+		vdd-supply = <&vreg_rtmr0_1p15>;
+		vdd33-supply = <&vreg_rtmr0_3p3>;
+		vdd33-cap-supply = <&vreg_rtmr0_3p3>;
+		vddar-supply = <&vreg_rtmr0_1p15>;
+		vddat-supply = <&vreg_rtmr0_1p15>;
+		vddio-supply = <&vreg_rtmr0_1p8>;
+
+		reset-gpios = <&pm8550_gpios 10 GPIO_ACTIVE_HIGH>;
+
+		retimer-switch;
+		orientation-switch;
+
+		ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@0 {
+				reg = <0>;
+
+				retimer_ss0_ss_out: endpoint {
+					remote-endpoint = <&pmic_glink_ss0_ss_in>;
+				};
+			};
+
+			port@1 {
+				reg = <1>;
+
+				retimer_ss0_ss_in: endpoint {
+					remote-endpoint = <&usb_1_ss0_qmpphy_out>;
+				};
+			};
+
+			port@2 {
+				reg = <2>;
+
+				retimer_ss0_con_sbu_out: endpoint {
+					remote-endpoint = <&pmic_glink_ss0_con_sbu_in>;
+				};
+			};
+		};
+	};
+};
+
+&i2c7 {
+	clock-frequency = <400000>;
+
+	status = "okay";
+
+	typec-mux@8 {
+		compatible = "parade,ps8830";
+		reg = <0x8>;
+
+		clocks = <&rpmhcc RPMH_RF_CLK4>;
+		clock-names = "xo";
+
+		vdd-supply = <&vreg_rtmr1_1p15>;
+		vdd33-supply = <&vreg_rtmr1_3p3>;
+		vdd33-cap-supply = <&vreg_rtmr1_3p3>;
+		vddar-supply = <&vreg_rtmr1_1p15>;
+		vddat-supply = <&vreg_rtmr1_1p15>;
+		vddio-supply = <&vreg_rtmr1_1p8>;
+
+		reset-gpios = <&tlmm 176 GPIO_ACTIVE_HIGH>;
+
+		retimer-switch;
+		orientation-switch;
+
+		ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@0 {
+				reg = <0>;
+
+				retimer_ss1_ss_out: endpoint {
+					remote-endpoint = <&pmic_glink_ss1_ss_in>;
+				};
+			};
+
+			port@1 {
+				reg = <1>;
+
+				retimer_ss1_ss_in: endpoint {
+					remote-endpoint = <&usb_1_ss1_qmpphy_out>;
+				};
+			};
+
+			port@2 {
+				reg = <2>;
+
+				retimer_ss1_con_sbu_out: endpoint {
+					remote-endpoint = <&pmic_glink_ss1_con_sbu_in>;
+				};
+			};
+		};
+	};
+};
+
+&mdss {
+	status = "okay";
+};
+
+&mdss_dp0 {
+	status = "okay";
+};
+
+&mdss_dp0_out {
+	data-lanes = <0 1>;
+};
+
+&mdss_dp1 {
+	status = "okay";
+};
+
+&mdss_dp1_out {
+	data-lanes = <0 1>;
+};
+
+&mdss_dp2 {
+	status = "okay";
+};
+
+&mdss_dp2_out {
+	data-lanes = <0 1>;
+};
+
+&pcie4 {
+	perst-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>;
+	wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;
+
+	pinctrl-0 = <&pcie4_default>;
+	pinctrl-names = "default";
+
+	status = "okay";
+};
+
+&pcie4_phy {
+	vdda-phy-supply = <&vreg_l3i_0p8>;
+	vdda-pll-supply = <&vreg_l3e_1p2>;
+
+	status = "okay";
+};
+
+&pcie5 {
+	perst-gpios = <&tlmm 149 GPIO_ACTIVE_LOW>;
+	wake-gpios = <&tlmm 151 GPIO_ACTIVE_LOW>;
+
+	vddpe-3v3-supply = <&vreg_wwan>;
+
+	pinctrl-0 = <&pcie5_default>;
+	pinctrl-names = "default";
+
+	status = "okay";
+};
+
+&pcie5_phy {
+	vdda-phy-supply = <&vreg_l3i_0p8>;
+	vdda-pll-supply = <&vreg_l3e_1p2>;
+
+	status = "okay";
+};
+
+&pcie6a {
+	perst-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>;
+	wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>;
+
+	vddpe-3v3-supply = <&vreg_nvme>;
+
+	pinctrl-names = "default";
+	pinctrl-0 = <&pcie6a_default>;
+
+	status = "okay";
+};
+
+&pcie6a_phy {
+	vdda-phy-supply = <&vreg_l1d_0p8>;
+	vdda-pll-supply = <&vreg_l2j_1p2>;
+
+	status = "okay";
+};
+
+&pm8550_gpios {
+	usb0_3p3_reg_en: usb0-3p3-reg-en-state {
+		pins = "gpio11";
+		function = "normal";
+	};
+};
+
+&pmc8380_5_gpios {
+	usb0_pwr_1p15_en: usb0-pwr-1p15-en-state {
+		pins = "gpio8";
+		function = "normal";
+	};
+};
+
+&pm8550ve_9_gpios {
+	usb0_1p8_reg_en: usb0-1p8-reg-en-state {
+		pins = "gpio8";
+		function = "normal";
+	};
+};
+
+&qupv3_0 {
+	status = "okay";
+};
+
+&qupv3_1 {
+	status = "okay";
+};
+
+&qupv3_2 {
+	status = "okay";
+};
+
+&remoteproc_adsp {
+	firmware-name = "qcom/x1e80100/Thundercomm/DEVKIT/qcadsp8380.mbn",
+			"qcom/x1e80100/Thundercomm/DEVKIT/adsp_dtbs.elf";
+
+	status = "okay";
+};
+
+&remoteproc_cdsp {
+	firmware-name = "qcom/x1e80100/Thundercomm/DEVKIT/qccdsp8380.mbn",
+			"qcom/x1e80100/Thundercomm/DEVKIT/cdsp_dtbs.elf";
+
+	status = "okay";
+};
+
+&sdhc_2 {
+	cd-gpios = <&tlmm 71 GPIO_ACTIVE_LOW>;
+	pinctrl-0 = <&sdc2_default &sdc2_card_det_n>;
+	pinctrl-1 = <&sdc2_sleep &sdc2_card_det_n>;
+	pinctrl-names = "default", "sleep";
+	vmmc-supply = <&vreg_l9b_2p9>;
+	vqmmc-supply = <&vreg_l6b_1p8>;
+	bus-width = <4>;
+	no-sdio;
+	no-mmc;
+	status = "okay";
+};
+
+&smb2360_0 {
+	status = "okay";
+};
+
+&smb2360_0_eusb2_repeater {
+	vdd18-supply = <&vreg_l3d_1p8>;
+	vdd3-supply = <&vreg_l2b_3p0>;
+};
+
+&smb2360_1 {
+	status = "okay";
+};
+
+&smb2360_1_eusb2_repeater {
+	vdd18-supply = <&vreg_l3d_1p8>;
+	vdd3-supply = <&vreg_l14b_3p0>;
+};
+
+&smb2360_2 {
+	status = "okay";
+};
+
+&smb2360_2_eusb2_repeater {
+	vdd18-supply = <&vreg_l3d_1p8>;
+	vdd3-supply = <&vreg_l8b_3p0>;
+};
+
+&swr1 {
+	status = "okay";
+
+	/* WCD9385 RX */
+	wcd_rx: codec@0,4 {
+		compatible = "sdw20217010d00";
+		reg = <0 4>;
+		qcom,rx-port-mapping = <1 2 3 4 5>;
+	};
+};
+
+&swr2 {
+	status = "okay";
+
+	/* WCD9385 TX */
+	wcd_tx: codec@0,3 {
+		compatible = "sdw20217010d00";
+		reg = <0 3>;
+		qcom,tx-port-mapping = <2 2 3 4>;
+	};
+};
+
+&tlmm {
+	gpio-reserved-ranges = <44 4>; /* SPI (TPM) */
+
+	nvme_reg_en: nvme-reg-en-state {
+		pins = "gpio18";
+		function = "gpio";
+		drive-strength = <2>;
+		bias-disable;
+	};
+
+	pcie4_default: pcie4-default-state {
+		clkreq-n-pins {
+			pins = "gpio147";
+			function = "pcie4_clk";
+			drive-strength = <2>;
+			bias-pull-up;
+		};
+
+		perst-n-pins {
+			pins = "gpio146";
+			function = "gpio";
+			drive-strength = <2>;
+			bias-disable;
+		};
+
+		wake-n-pins {
+			pins = "gpio148";
+			function = "gpio";
+			drive-strength = <2>;
+			bias-pull-up;
+		};
+	};
+
+	pcie5_default: pcie5-default-state {
+		clkreq-n-pins {
+			pins = "gpio150";
+			function = "pcie5_clk";
+			drive-strength = <2>;
+			bias-pull-up;
+		};
+
+		perst-n-pins {
+			pins = "gpio149";
+			function = "gpio";
+			drive-strength = <2>;
+			bias-disable;
+		};
+
+		wake-n-pins {
+			pins = "gpio151";
+			function = "gpio";
+			drive-strength = <2>;
+			bias-pull-up;
+		};
+	};
+
+	pcie6a_default: pcie6a-default-state {
+		clkreq-n-pins {
+			pins = "gpio153";
+			function = "pcie6a_clk";
+			drive-strength = <2>;
+			bias-pull-up;
+		};
+
+		perst-n-pins {
+			pins = "gpio152";
+			function = "gpio";
+			drive-strength = <2>;
+			bias-disable;
+		};
+
+		wake-n-pins {
+			pins = "gpio154";
+			function = "gpio";
+			drive-strength = <2>;
+			bias-pull-up;
+		};
+	};
+
+	rtmr1_1p15_reg_en: rtmr1-1p15-reg-en-state {
+		pins = "gpio188";
+		function = "gpio";
+		drive-strength = <2>;
+		bias-disable;
+	};
+
+	rtmr1_1p8_reg_en: rtmr1-1p8-reg-en-state {
+		pins = "gpio175";
+		function = "gpio";
+		drive-strength = <2>;
+		bias-disable;
+	};
+
+	rtmr1_3p3_reg_en: rtmr1-3p3-reg-en-state {
+		pins = "gpio186";
+		function = "gpio";
+		drive-strength = <2>;
+		bias-disable;
+	};
+
+	rtmr2_1p15_reg_en: rtmr2-1p15-reg-en-state {
+		pins = "gpio189";
+		function = "gpio";
+		drive-strength = <2>;
+		bias-disable;
+	};
+
+	rtmr2_1p8_reg_en: rtmr2-1p8-reg-en-state {
+		pins = "gpio126";
+		function = "gpio";
+		drive-strength = <2>;
+		bias-disable;
+	};
+
+	rtmr2_3p3_reg_en: rtmr2-3p3-reg-en-state {
+		pins = "gpio187";
+		function = "gpio";
+		drive-strength = <2>;
+		bias-disable;
+	};
+
+	sdc2_card_det_n: sdc2-card-det-state {
+		pins = "gpio71";
+		function = "gpio";
+		drive-strength = <2>;
+		bias-pull-up;
+	};
+
+	wcd_default: wcd-reset-n-active-state {
+		pins = "gpio191";
+		function = "gpio";
+		drive-strength = <16>;
+		bias-disable;
+		output-low;
+	};
+
+	wwan_sw_en: wwan-sw-en-state {
+		pins = "gpio221";
+		function = "gpio";
+		drive-strength = <4>;
+		bias-disable;
+	};
+};
+
+&uart21 {
+	compatible = "qcom,geni-debug-uart";
+	status = "okay";
+};
+
+&usb_1_ss0_hsphy {
+	vdd-supply = <&vreg_l3j_0p8>;
+	vdda12-supply = <&vreg_l2j_1p2>;
+
+	phys = <&smb2360_0_eusb2_repeater>;
+
+	status = "okay";
+};
+
+&usb_1_ss0_qmpphy {
+	vdda-phy-supply = <&vreg_l2j_1p2>;
+	vdda-pll-supply = <&vreg_l1j_0p8>;
+
+	status = "okay";
+};
+
+&usb_1_ss0 {
+	status = "okay";
+};
+
+&usb_1_ss0_dwc3 {
+	dr_mode = "otg";
+	usb-role-switch;
+};
+
+&usb_1_ss0_dwc3_hs {
+	remote-endpoint = <&pmic_glink_ss0_hs_in>;
+};
+
+&usb_1_ss0_qmpphy_out {
+	remote-endpoint = <&retimer_ss0_ss_in>;
+};
+
+&usb_1_ss1_hsphy {
+	vdd-supply = <&vreg_l3j_0p8>;
+	vdda12-supply = <&vreg_l2j_1p2>;
+
+	phys = <&smb2360_1_eusb2_repeater>;
+
+	status = "okay";
+};
+
+&usb_1_ss1_qmpphy {
+	vdda-phy-supply = <&vreg_l2j_1p2>;
+	vdda-pll-supply = <&vreg_l2d_0p9>;
+
+	status = "okay";
+};
+
+&usb_1_ss1 {
+	status = "okay";
+};
+
+&usb_1_ss1_dwc3 {
+	dr_mode = "host";
+};
+
+&usb_1_ss1_dwc3_hs {
+	remote-endpoint = <&pmic_glink_ss1_hs_in>;
+};
+
+&usb_1_ss1_qmpphy_out {
+	remote-endpoint = <&retimer_ss1_ss_in>;
+};
+
+&usb_1_ss2_hsphy {
+	vdd-supply = <&vreg_l3j_0p8>;
+	vdda12-supply = <&vreg_l2j_1p2>;
+
+	phys = <&smb2360_2_eusb2_repeater>;
+
+	status = "okay";
+};
+
+&usb_1_ss2_qmpphy {
+	vdda-phy-supply = <&vreg_l2j_1p2>;
+	vdda-pll-supply = <&vreg_l2d_0p9>;
+
+	status = "okay";
+};
+
+&usb_1_ss2 {
+	status = "okay";
+};
+
+&usb_1_ss2_dwc3 {
+	dr_mode = "host";
+};
+
+&usb_1_ss2_dwc3_hs {
+	remote-endpoint = <&pmic_glink_ss2_hs_in>;
+};
+
+&usb_1_ss2_qmpphy_out {
+	remote-endpoint = <&retimer_ss2_ss_in>;
+};
diff --git a/dts/upstream/src/arm64/qcom/x1e78100-lenovo-thinkpad-t14s.dts b/dts/upstream/src/arm64/qcom/x1e78100-lenovo-thinkpad-t14s.dts
index 66513fc8e67..b2c2347f54f 100644
--- a/dts/upstream/src/arm64/qcom/x1e78100-lenovo-thinkpad-t14s.dts
+++ b/dts/upstream/src/arm64/qcom/x1e78100-lenovo-thinkpad-t14s.dts
@@ -19,6 +19,32 @@
 	compatible = "lenovo,thinkpad-t14s", "qcom,x1e78100", "qcom,x1e80100";
 	chassis-type = "laptop";
 
+	wcd938x: audio-codec {
+		compatible = "qcom,wcd9385-codec";
+
+		pinctrl-0 = <&wcd_default>;
+		pinctrl-names = "default";
+
+		qcom,micbias1-microvolt = <1800000>;
+		qcom,micbias2-microvolt = <1800000>;
+		qcom,micbias3-microvolt = <1800000>;
+		qcom,micbias4-microvolt = <1800000>;
+		qcom,mbhc-buttons-vthreshold-microvolt = <75000 150000 237000 500000 500000 500000 500000 500000>;
+		qcom,mbhc-headset-vthreshold-microvolt = <1700000>;
+		qcom,mbhc-headphone-vthreshold-microvolt = <50000>;
+		qcom,rx-device = <&wcd_rx>;
+		qcom,tx-device = <&wcd_tx>;
+
+		reset-gpios = <&tlmm 191 GPIO_ACTIVE_LOW>;
+
+		vdd-buck-supply = <&vreg_l15b_1p8>;
+		vdd-rxtx-supply = <&vreg_l15b_1p8>;
+		vdd-io-supply = <&vreg_l15b_1p8>;
+		vdd-mic-bias-supply = <&vreg_bob1>;
+
+		#sound-dai-cells = <1>;
+	};
+
 	gpio-keys {
 		compatible = "gpio-keys";
 
@@ -153,6 +179,85 @@
 		regulator-always-on;
 		regulator-boot-on;
 	};
+
+	sound {
+		compatible = "qcom,x1e80100-sndcard";
+		model = "X1E80100-LENOVO-Thinkpad-T14s";
+		audio-routing = "SpkrLeft IN", "WSA WSA_SPK1 OUT",
+				"SpkrRight IN", "WSA WSA_SPK2 OUT",
+				"IN1_HPHL", "HPHL_OUT",
+				"IN2_HPHR", "HPHR_OUT",
+				"AMIC2", "MIC BIAS2",
+				"VA DMIC0", "MIC BIAS1",
+				"VA DMIC1", "MIC BIAS1",
+				"VA DMIC0", "VA MIC BIAS1",
+				"VA DMIC1", "VA MIC BIAS1",
+				"TX SWR_INPUT1", "ADC2_OUTPUT";
+
+		wcd-playback-dai-link {
+			link-name = "WCD Playback";
+
+			cpu {
+				sound-dai = <&q6apmbedai RX_CODEC_DMA_RX_0>;
+			};
+
+			codec {
+				sound-dai = <&wcd938x 0>, <&swr1 0>, <&lpass_rxmacro 0>;
+			};
+
+			platform {
+				sound-dai = <&q6apm>;
+			};
+		};
+
+		wcd-capture-dai-link {
+			link-name = "WCD Capture";
+
+			cpu {
+				sound-dai = <&q6apmbedai TX_CODEC_DMA_TX_3>;
+			};
+
+			codec {
+				sound-dai = <&wcd938x 1>, <&swr2 1>, <&lpass_txmacro 0>;
+			};
+
+			platform {
+				sound-dai = <&q6apm>;
+			};
+		};
+
+		wsa-dai-link {
+			link-name = "WSA Playback";
+
+			cpu {
+				sound-dai = <&q6apmbedai WSA_CODEC_DMA_RX_0>;
+			};
+
+			codec {
+				sound-dai = <&left_spkr>, <&right_spkr>, <&swr0 0>, <&lpass_wsamacro 0>;
+			};
+
+			platform {
+				sound-dai = <&q6apm>;
+			};
+		};
+
+		va-dai-link {
+			link-name = "VA Capture";
+
+			cpu {
+				sound-dai = <&q6apmbedai VA_CODEC_DMA_TX_0>;
+			};
+
+			codec {
+				sound-dai = <&lpass_vamacro 0>;
+			};
+
+			platform {
+				sound-dai = <&q6apm>;
+			};
+		};
+	};
 };
 
 &apps_rsc {
@@ -185,6 +290,13 @@
 			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
 		};
 
+		vreg_l1b_1p8: ldo1 {
+			regulator-name = "vreg_l1b_1p8";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
 		vreg_l2b_3p0: ldo2 {
 			regulator-name = "vreg_l2b_3p0";
 			regulator-min-microvolt = <3072000>;
@@ -495,6 +607,54 @@
 	};
 };
 
+&i2c5 {
+	clock-frequency = <400000>;
+
+	status = "okay";
+
+	eusb5_repeater: redriver@43 {
+		compatible = "nxp,ptn3222";
+		reg = <0x43>;
+		#phy-cells = <0>;
+
+		vdd3v3-supply = <&vreg_l13b_3p0>;
+		vdd1v8-supply = <&vreg_l4b_1p8>;
+
+		reset-gpios = <&tlmm 7 GPIO_ACTIVE_LOW>;
+
+		pinctrl-0 = <&eusb5_reset_n>;
+		pinctrl-names = "default";
+	};
+
+	eusb3_repeater: redriver@47 {
+		compatible = "nxp,ptn3222";
+		reg = <0x47>;
+		#phy-cells = <0>;
+
+		vdd3v3-supply = <&vreg_l13b_3p0>;
+		vdd1v8-supply = <&vreg_l4b_1p8>;
+
+		reset-gpios = <&tlmm 6 GPIO_ACTIVE_LOW>;
+
+		pinctrl-0 = <&eusb3_reset_n>;
+		pinctrl-names = "default";
+	};
+
+	eusb6_repeater: redriver@4f {
+		compatible = "nxp,ptn3222";
+		reg = <0x4f>;
+		#phy-cells = <0>;
+
+		vdd3v3-supply = <&vreg_l13b_3p0>;
+		vdd1v8-supply = <&vreg_l4b_1p8>;
+
+		reset-gpios = <&tlmm 184 GPIO_ACTIVE_LOW>;
+
+		pinctrl-0 = <&eusb6_reset_n>;
+		pinctrl-names = "default";
+	};
+};
+
 &i2c8 {
 	clock-frequency = <400000>;
 
@@ -515,6 +675,24 @@
 	/* TODO: second-sourced touchscreen @ 0x41 */
 };
 
+&lpass_tlmm {
+	spkr_01_sd_n_active: spkr-01-sd-n-active-state {
+		pins = "gpio12";
+		function = "gpio";
+		drive-strength = <16>;
+		bias-disable;
+		output-low;
+	};
+};
+
+&lpass_vamacro {
+	pinctrl-0 = <&dmic01_default>;
+	pinctrl-names = "default";
+
+	vdd-micb-supply = <&vreg_l1b_1p8>;
+	qcom,dmic-sample-rate = <4800000>;
+};
+
 &mdss {
 	status = "okay";
 };
@@ -635,22 +813,107 @@
 	status = "okay";
 };
 
+&smb2360_0 {
+	status = "okay";
+};
+
 &smb2360_0_eusb2_repeater {
 	vdd18-supply = <&vreg_l3d_1p8>;
 	vdd3-supply = <&vreg_l2b_3p0>;
 };
 
+&smb2360_1 {
+	status = "okay";
+};
+
 &smb2360_1_eusb2_repeater {
 	vdd18-supply = <&vreg_l3d_1p8>;
 	vdd3-supply = <&vreg_l14b_3p0>;
 };
 
+&swr0 {
+	status = "okay";
+
+	pinctrl-0 = <&wsa_swr_active>, <&spkr_01_sd_n_active>;
+	pinctrl-names = "default";
+
+	/* WSA8845, Left Speaker */
+	left_spkr: speaker@0,0 {
+		compatible = "sdw20217020400";
+		reg = <0 0>;
+		reset-gpios = <&lpass_tlmm 12 GPIO_ACTIVE_LOW>;
+		#sound-dai-cells = <0>;
+		sound-name-prefix = "SpkrLeft";
+		vdd-1p8-supply = <&vreg_l15b_1p8>;
+		vdd-io-supply = <&vreg_l12b_1p2>;
+		qcom,port-mapping = <1 2 3 7 10 13>;
+	};
+
+	/* WSA8845, Right Speaker */
+	right_spkr: speaker@0,1 {
+		compatible = "sdw20217020400";
+		reg = <0 1>;
+		reset-gpios = <&lpass_tlmm 12 GPIO_ACTIVE_LOW>;
+		#sound-dai-cells = <0>;
+		sound-name-prefix = "SpkrRight";
+		vdd-1p8-supply = <&vreg_l15b_1p8>;
+		vdd-io-supply = <&vreg_l12b_1p2>;
+		qcom,port-mapping = <4 5 6 7 11 13>;
+	};
+};
+
+&swr1 {
+	status = "okay";
+
+	/* WCD9385 RX */
+	wcd_rx: codec@0,4 {
+		compatible = "sdw20217010d00";
+		reg = <0 4>;
+		qcom,rx-port-mapping = <1 2 3 4 5>;
+	};
+};
+
+&swr2 {
+	status = "okay";
+
+	/* WCD9385 TX */
+	wcd_tx: codec@0,3 {
+		compatible = "sdw20217010d00";
+		reg = <0 3>;
+		qcom,tx-port-mapping = <2 2 3 4>;
+	};
+};
+
 &tlmm {
 	gpio-reserved-ranges = <34 2>, /* Unused */
 			       <44 4>, /* SPI (TPM) */
 			       <72 2>, /* Secure EC I2C connection (?) */
 			       <238 1>; /* UFS Reset */
 
+	eusb3_reset_n: eusb3-reset-n-state {
+		pins = "gpio6";
+		function = "gpio";
+		drive-strength = <2>;
+		bias-disable;
+		output-low;
+	};
+
+	eusb5_reset_n: eusb5-reset-n-state {
+		pins = "gpio7";
+		function = "gpio";
+		drive-strength = <2>;
+		bias-disable;
+		output-low;
+	};
+
+	eusb6_reset_n: eusb6-reset-n-state {
+		pins = "gpio184";
+		function = "gpio";
+		drive-strength = <2>;
+		bias-disable;
+		output-low;
+	};
+
 	tpad_default: tpad-default-state {
 		pins = "gpio3";
 		function = "gpio";
@@ -763,7 +1026,7 @@
 };
 
 &usb_1_ss0_qmpphy {
-	vdda-phy-supply = <&vreg_l3e_1p2>;
+	vdda-phy-supply = <&vreg_l2j_1p2>;
 	vdda-pll-supply = <&vreg_l1j_0p8>;
 
 	status = "okay";
@@ -795,7 +1058,7 @@
 };
 
 &usb_1_ss1_qmpphy {
-	vdda-phy-supply = <&vreg_l3e_1p2>;
+	vdda-phy-supply = <&vreg_l2j_1p2>;
 	vdda-pll-supply = <&vreg_l2d_0p9>;
 
 	status = "okay";
@@ -816,3 +1079,56 @@
 &usb_1_ss1_qmpphy_out {
 	remote-endpoint = <&pmic_glink_ss1_ss_in>;
 };
+
+&usb_2 {
+	status = "okay";
+};
+
+&usb_2_dwc3 {
+	dr_mode = "host";
+};
+
+&usb_2_hsphy {
+	vdd-supply = <&vreg_l2e_0p8>;
+	vdda12-supply = <&vreg_l3e_1p2>;
+
+	phys = <&eusb5_repeater>;
+
+	status = "okay";
+};
+
+&usb_mp {
+	status = "okay";
+};
+
+&usb_mp_hsphy0 {
+	vdd-supply = <&vreg_l2e_0p8>;
+	vdda12-supply = <&vreg_l3e_1p2>;
+
+	phys = <&eusb6_repeater>;
+
+	status = "okay";
+};
+
+&usb_mp_hsphy1 {
+	vdd-supply = <&vreg_l2e_0p8>;
+	vdda12-supply = <&vreg_l3e_1p2>;
+
+	phys = <&eusb3_repeater>;
+
+	status = "okay";
+};
+
+&usb_mp_qmpphy0 {
+	vdda-phy-supply = <&vreg_l3e_1p2>;
+	vdda-pll-supply = <&vreg_l3c_0p8>;
+
+	status = "okay";
+};
+
+&usb_mp_qmpphy1 {
+	vdda-phy-supply = <&vreg_l3e_1p2>;
+	vdda-pll-supply = <&vreg_l3c_0p8>;
+
+	status = "okay";
+};
diff --git a/dts/upstream/src/arm64/qcom/x1e80100-asus-vivobook-s15.dts b/dts/upstream/src/arm64/qcom/x1e80100-asus-vivobook-s15.dts
index 8515c254e15..53781f9b13a 100644
--- a/dts/upstream/src/arm64/qcom/x1e80100-asus-vivobook-s15.dts
+++ b/dts/upstream/src/arm64/qcom/x1e80100-asus-vivobook-s15.dts
@@ -7,7 +7,9 @@
 /dts-v1/;
 
 #include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/gpio-keys.h>
 #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
+#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
 
 #include "x1e80100.dtsi"
 #include "x1e80100-pmics.dtsi"
@@ -17,6 +19,20 @@
 	compatible = "asus,vivobook-s15", "qcom,x1e80100";
 	chassis-type = "laptop";
 
+	gpio-keys {
+		compatible = "gpio-keys";
+		pinctrl-0 = <&hall_int_n_default>;
+		pinctrl-names = "default";
+
+		switch-lid {
+			gpios = <&tlmm 92 GPIO_ACTIVE_LOW>;
+			linux,input-type = <EV_SW>;
+			linux,code = <SW_LID>;
+			wakeup-source;
+			wakeup-event-action = <EV_ACT_DEASSERTED>;
+		};
+	};
+
 	pmic-glink {
 		compatible = "qcom,x1e80100-pmic-glink",
 			     "qcom,sm8550-pmic-glink",
@@ -328,6 +344,14 @@
 	};
 };
 
+&gpu {
+	status = "okay";
+
+	zap-shader {
+		firmware-name = "qcom/x1e80100/ASUSTeK/vivobook-s15/qcdxkmsuc8380.mbn";
+	};
+};
+
 &i2c0 {
 	clock-frequency = <400000>;
 	status = "okay";
@@ -399,9 +423,13 @@
 
 	aux-bus {
 		panel {
-			compatible = "edp-panel";
+			compatible = "samsung,atna56ac03", "samsung,atna33xc20";
+			enable-gpios = <&pmc8380_3_gpios 4 GPIO_ACTIVE_HIGH>;
 			power-supply = <&vreg_edp_3p3>;
 
+			pinctrl-0 = <&edp_bl_en>;
+			pinctrl-names = "default";
+
 			port {
 				edp_panel_in: endpoint {
 					remote-endpoint = <&mdss_dp3_out>;
@@ -467,6 +495,18 @@
 	status = "okay";
 };
 
+&pmc8380_3_gpios {
+	edp_bl_en: edp-bl-en-state {
+		pins = "gpio4";
+		function = "normal";
+		power-source = <1>; /* 1.8 V */
+		qcom,drive-strength = <PMIC_GPIO_STRENGTH_MED>;
+		bias-pull-down;
+		input-disable;
+		output-enable;
+	};
+};
+
 &qupv3_0 {
 	status = "okay";
 };
@@ -493,11 +533,19 @@
 	status = "okay";
 };
 
+&smb2360_0 {
+	status = "okay";
+};
+
 &smb2360_0_eusb2_repeater {
 	vdd18-supply = <&vreg_l3d_1p8>;
 	vdd3-supply = <&vreg_l2b_3p0>;
 };
 
+&smb2360_1 {
+	status = "okay";
+};
+
 &smb2360_1_eusb2_repeater {
 	vdd18-supply = <&vreg_l3d_1p8>;
 	vdd3-supply = <&vreg_l14b_3p0>;
@@ -515,6 +563,12 @@
 		bias-disable;
 	};
 
+	hall_int_n_default: hall-int-n-state {
+		pins = "gpio92";
+		function = "gpio";
+		bias-disable;
+	};
+
 	kybd_default: kybd-default-state {
 		pins = "gpio67";
 		function = "gpio";
@@ -591,7 +645,7 @@
 };
 
 &usb_1_ss0_qmpphy {
-	vdda-phy-supply = <&vreg_l3e_1p2>;
+	vdda-phy-supply = <&vreg_l2j_1p2>;
 	vdda-pll-supply = <&vreg_l1j_0p8>;
 
 	status = "okay";
@@ -623,7 +677,7 @@
 };
 
 &usb_1_ss1_qmpphy {
-	vdda-phy-supply = <&vreg_l3e_1p2>;
+	vdda-phy-supply = <&vreg_l2j_1p2>;
 	vdda-pll-supply = <&vreg_l2d_0p9>;
 
 	status = "okay";
diff --git a/dts/upstream/src/arm64/qcom/x1e80100-crd.dts b/dts/upstream/src/arm64/qcom/x1e80100-crd.dts
index d51a9bdcf67..ff5b3472faf 100644
--- a/dts/upstream/src/arm64/qcom/x1e80100-crd.dts
+++ b/dts/upstream/src/arm64/qcom/x1e80100-crd.dts
@@ -932,11 +932,19 @@
 	status = "okay";
 };
 
+&smb2360_0 {
+	status = "okay";
+};
+
 &smb2360_0_eusb2_repeater {
 	vdd18-supply = <&vreg_l3d_1p8>;
 	vdd3-supply = <&vreg_l2b_3p0>;
 };
 
+&smb2360_1 {
+	status = "okay";
+};
+
 &smb2360_1_eusb2_repeater {
 	vdd18-supply = <&vreg_l3d_1p8>;
 	vdd3-supply = <&vreg_l14b_3p0>;
@@ -1187,7 +1195,7 @@
 };
 
 &usb_1_ss0_qmpphy {
-	vdda-phy-supply = <&vreg_l3e_1p2>;
+	vdda-phy-supply = <&vreg_l2j_1p2>;
 	vdda-pll-supply = <&vreg_l1j_0p8>;
 
 	status = "okay";
@@ -1219,7 +1227,7 @@
 };
 
 &usb_1_ss1_qmpphy {
-	vdda-phy-supply = <&vreg_l3e_1p2>;
+	vdda-phy-supply = <&vreg_l2j_1p2>;
 	vdda-pll-supply = <&vreg_l2d_0p9>;
 
 	status = "okay";
@@ -1251,7 +1259,7 @@
 };
 
 &usb_1_ss2_qmpphy {
-	vdda-phy-supply = <&vreg_l3e_1p2>;
+	vdda-phy-supply = <&vreg_l2j_1p2>;
 	vdda-pll-supply = <&vreg_l2d_0p9>;
 
 	status = "okay";
diff --git a/dts/upstream/src/arm64/qcom/x1e80100-dell-xps13-9345.dts b/dts/upstream/src/arm64/qcom/x1e80100-dell-xps13-9345.dts
index 05624226faf..86e87f03b0e 100644
--- a/dts/upstream/src/arm64/qcom/x1e80100-dell-xps13-9345.dts
+++ b/dts/upstream/src/arm64/qcom/x1e80100-dell-xps13-9345.dts
@@ -89,7 +89,15 @@
 					reg = <1>;
 
 					pmic_glink_ss0_ss_in: endpoint {
-						remote-endpoint = <&usb_1_ss0_qmpphy_out>;
+						remote-endpoint = <&retimer_ss0_ss_out>;
+					};
+				};
+
+				port@2 {
+					reg = <2>;
+
+					pmic_glink_ss0_con_sbu_in: endpoint {
+						remote-endpoint = <&retimer_ss0_con_sbu_out>;
 					};
 				};
 			};
@@ -118,7 +126,15 @@
 					reg = <1>;
 
 					pmic_glink_ss1_ss_in: endpoint {
-						remote-endpoint = <&usb_1_ss1_qmpphy_out>;
+						remote-endpoint = <&retimer_ss1_ss_out>;
+					};
+				};
+
+				port@2 {
+					reg = <2>;
+
+					pmic_glink_ss1_con_sbu_in: endpoint {
+						remote-endpoint = <&retimer_ss1_con_sbu_out>;
 					};
 				};
 			};
@@ -166,6 +182,102 @@
 		regulator-boot-on;
 	};
 
+	vreg_rtmr0_1p15: regulator-rtmr0-1p15 {
+		compatible = "regulator-fixed";
+
+		regulator-name = "VREG_RTMR0_1P15";
+		regulator-min-microvolt = <1150000>;
+		regulator-max-microvolt = <1150000>;
+
+		gpio = <&pmc8380_5_gpios 8 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+
+		pinctrl-0 = <&rtmr0_1p15_reg_en>;
+		pinctrl-names = "default";
+
+		regulator-boot-on;
+	};
+
+	vreg_rtmr0_1p8: regulator-rtmr0-1p8 {
+		compatible = "regulator-fixed";
+
+		regulator-name = "VREG_RTMR0_1P8";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+
+		gpio = <&pm8550ve_9_gpios 8 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+
+		pinctrl-0 = <&rtmr0_1p8_reg_en>;
+		pinctrl-names = "default";
+
+		regulator-boot-on;
+	};
+
+	vreg_rtmr0_3p3: regulator-rtmr0-3p3 {
+		compatible = "regulator-fixed";
+
+		regulator-name = "VREG_RTMR0_3P3";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+
+		gpio = <&pm8550_gpios 11 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+
+		pinctrl-0 = <&rtmr0_3p3_reg_en>;
+		pinctrl-names = "default";
+
+		regulator-boot-on;
+	};
+
+	vreg_rtmr1_1p15: regulator-rtmr1-1p15 {
+		compatible = "regulator-fixed";
+
+		regulator-name = "VREG_RTMR1_1P15";
+		regulator-min-microvolt = <1150000>;
+		regulator-max-microvolt = <1150000>;
+
+		gpio = <&tlmm 188 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+
+		pinctrl-0 = <&rtmr1_1p15_reg_en>;
+		pinctrl-names = "default";
+
+		regulator-boot-on;
+	};
+
+	vreg_rtmr1_1p8: regulator-rtmr1-1p8 {
+		compatible = "regulator-fixed";
+
+		regulator-name = "VREG_RTMR1_1P8";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+
+		gpio = <&tlmm 175 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+
+		pinctrl-0 = <&rtmr1_1p8_reg_en>;
+		pinctrl-names = "default";
+
+		regulator-boot-on;
+	};
+
+	vreg_rtmr1_3p3: regulator-rtmr1-3p3 {
+		compatible = "regulator-fixed";
+
+		regulator-name = "VREG_RTMR1_3P3";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+
+		gpio = <&tlmm 186 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+
+		pinctrl-0 = <&rtmr1_3p3_reg_en>;
+		pinctrl-names = "default";
+
+		regulator-boot-on;
+	};
+
 	vreg_vph_pwr: regulator-vph-pwr {
 		compatible = "regulator-fixed";
 
@@ -492,9 +604,60 @@
 
 &i2c3 {
 	clock-frequency = <400000>;
-	status = "disabled";
-	/* PS8830 Retimer @0x8 */
-	/* Unknown device @0x9 */
+	status = "okay";
+
+	/* Right-side USB Type-C port */
+	typec-mux@8 {
+		compatible = "parade,ps8830";
+		reg = <0x08>;
+
+		clocks = <&rpmhcc RPMH_RF_CLK3>;
+		clock-names = "xo";
+
+		vdd-supply = <&vreg_rtmr0_1p15>;
+		vdd33-supply = <&vreg_rtmr0_3p3>;
+		vdd33-cap-supply = <&vreg_rtmr0_3p3>;
+		vddar-supply = <&vreg_rtmr0_1p15>;
+		vddat-supply = <&vreg_rtmr0_1p15>;
+		vddio-supply = <&vreg_rtmr0_1p8>;
+
+		reset-gpios = <&pm8550_gpios 10 GPIO_ACTIVE_LOW>;
+
+		pinctrl-0 = <&rtmr0_default>;
+		pinctrl-names = "default";
+
+		retimer-switch;
+		orientation-switch;
+
+		ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@0 {
+				reg = <0>;
+
+				retimer_ss0_ss_out: endpoint {
+					remote-endpoint = <&pmic_glink_ss0_ss_in>;
+				};
+			};
+
+			port@1 {
+				reg = <1>;
+
+				retimer_ss0_ss_in: endpoint {
+					remote-endpoint = <&usb_1_ss0_qmpphy_out>;
+				};
+			};
+
+			port@2 {
+				reg = <2>;
+
+				retimer_ss0_con_sbu_out: endpoint {
+					remote-endpoint = <&pmic_glink_ss0_con_sbu_in>;
+				};
+			};
+		};
+	};
 };
 
 &i2c5 {
@@ -505,9 +668,61 @@
 
 &i2c7 {
 	clock-frequency = <400000>;
-	status = "disabled";
-	/* PS8830 Retimer @0x8 */
-	/* Unknown device @0x9 */
+	status = "okay";
+
+	/* Left-side USB Type-C port */
+	typec-mux@8 {
+		compatible = "parade,ps8830";
+		reg = <0x8>;
+
+		clocks = <&rpmhcc RPMH_RF_CLK4>;
+		clock-names = "xo";
+
+		vdd-supply = <&vreg_rtmr1_1p15>;
+		vdd33-supply = <&vreg_rtmr1_3p3>;
+		vdd33-cap-supply = <&vreg_rtmr1_3p3>;
+		vddar-supply = <&vreg_rtmr1_1p15>;
+		vddat-supply = <&vreg_rtmr1_1p15>;
+		vddio-supply = <&vreg_rtmr1_1p8>;
+
+		reset-gpios = <&tlmm 176 GPIO_ACTIVE_LOW>;
+
+		pinctrl-0 = <&rtmr1_default>;
+		pinctrl-names = "default";
+
+		retimer-switch;
+		orientation-switch;
+
+		ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@0 {
+				reg = <0>;
+
+				retimer_ss1_ss_out: endpoint {
+					remote-endpoint = <&pmic_glink_ss1_ss_in>;
+				};
+			};
+
+			port@1 {
+				reg = <1>;
+
+				retimer_ss1_ss_in: endpoint {
+					remote-endpoint = <&usb_1_ss1_qmpphy_out>;
+				};
+			};
+
+			port@2 {
+				reg = <2>;
+
+				retimer_ss1_con_sbu_out: endpoint {
+					remote-endpoint = <&pmic_glink_ss1_con_sbu_in>;
+				};
+			};
+
+		};
+	};
 };
 
 &i2c8 {
@@ -634,6 +849,36 @@
 	status = "okay";
 };
 
+&pm8550_gpios {
+	rtmr0_default: rtmr0-reset-n-active-state {
+		pins = "gpio10";
+		function = "normal";
+		power-source = <1>; /* 1.8V */
+	};
+
+	rtmr0_3p3_reg_en: rtmr0-3p3-reg-en-state {
+		pins = "gpio11";
+		function = "normal";
+		power-source = <1>; /* 1.8V */
+	};
+};
+
+&pmc8380_5_gpios {
+	rtmr0_1p15_reg_en: rtmr0-1p15-reg-en-state {
+		pins = "gpio8";
+		function = "normal";
+		power-source = <1>; /* 1.8V */
+	};
+};
+
+&pm8550ve_9_gpios {
+	rtmr0_1p8_reg_en: rtmr0-1p8-reg-en-state {
+		pins = "gpio8";
+		function = "normal";
+		power-source = <1>; /* 1.8V */
+	};
+};
+
 &qupv3_0 {
 	status = "okay";
 };
@@ -660,11 +905,19 @@
 	status = "okay";
 };
 
+&smb2360_0 {
+	status = "okay";
+};
+
 &smb2360_0_eusb2_repeater {
 	vdd18-supply = <&vreg_l3d_1p8>;
 	vdd3-supply = <&vreg_l2b_3p0>;
 };
 
+&smb2360_1 {
+	status = "okay";
+};
+
 &smb2360_1_eusb2_repeater {
 	vdd18-supply = <&vreg_l3d_1p8>;
 	vdd3-supply = <&vreg_l14b_3p0>;
@@ -762,6 +1015,34 @@
 		};
 	};
 
+	rtmr1_1p15_reg_en: rtmr1-1p15-reg-en-state {
+		pins = "gpio188";
+		function = "gpio";
+		drive-strength = <2>;
+		bias-disable;
+	};
+
+	rtmr1_1p8_reg_en: rtmr1-1p8-reg-en-state {
+		pins = "gpio175";
+		function = "gpio";
+		drive-strength = <2>;
+		bias-disable;
+	};
+
+	rtmr1_3p3_reg_en: rtmr1-3p3-reg-en-state {
+		pins = "gpio186";
+		function = "gpio";
+		drive-strength = <2>;
+		bias-disable;
+	};
+
+	rtmr1_default: rtmr1-reset-n-active-state {
+		pins = "gpio176";
+		function = "gpio";
+		drive-strength = <2>;
+		bias-disable;
+	};
+
 	tpad_default: tpad-default-state {
 		disable-pins {
 			pins = "gpio38";
@@ -820,7 +1101,7 @@
 };
 
 &usb_1_ss0_qmpphy {
-	vdda-phy-supply = <&vreg_l3e_1p2>;
+	vdda-phy-supply = <&vreg_l2j_1p2>;
 	vdda-pll-supply = <&vreg_l1j_0p9>;
 
 	status = "okay";
@@ -839,7 +1120,7 @@
 };
 
 &usb_1_ss0_qmpphy_out {
-	remote-endpoint = <&pmic_glink_ss0_ss_in>;
+	remote-endpoint = <&retimer_ss0_ss_in>;
 };
 
 &usb_1_ss1_hsphy {
@@ -852,7 +1133,7 @@
 };
 
 &usb_1_ss1_qmpphy {
-	vdda-phy-supply = <&vreg_l3e_1p2>;
+	vdda-phy-supply = <&vreg_l2j_1p2>;
 	vdda-pll-supply = <&vreg_l2d_0p9>;
 
 	status = "okay";
@@ -871,5 +1152,5 @@
 };
 
 &usb_1_ss1_qmpphy_out {
-	remote-endpoint = <&pmic_glink_ss1_ss_in>;
+	remote-endpoint = <&retimer_ss1_ss_in>;
 };
diff --git a/dts/upstream/src/arm64/qcom/x1e80100-hp-omnibook-x14.dts b/dts/upstream/src/arm64/qcom/x1e80100-hp-omnibook-x14.dts
new file mode 100644
index 00000000000..cd860a246c4
--- /dev/null
+++ b/dts/upstream/src/arm64/qcom/x1e80100-hp-omnibook-x14.dts
@@ -0,0 +1,1693 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2024, Xilin Wu <wuxilin123@gmail.com>
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/gpio-keys.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
+#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
+
+#include "x1e80100.dtsi"
+#include "x1e80100-pmics.dtsi"
+
+/ {
+	model = "HP Omnibook X 14";
+	compatible = "hp,omnibook-x14", "qcom,x1e80100";
+	chassis-type = "laptop";
+
+	aliases {
+		serial0 = &uart21;
+		serial1 = &uart14;
+	};
+
+	wcd938x: audio-codec {
+		compatible = "qcom,wcd9385-codec";
+
+		pinctrl-names = "default";
+		pinctrl-0 = <&wcd_default>;
+
+		qcom,micbias1-microvolt = <1800000>;
+		qcom,micbias2-microvolt = <1800000>;
+		qcom,micbias3-microvolt = <1800000>;
+		qcom,micbias4-microvolt = <1800000>;
+		qcom,mbhc-buttons-vthreshold-microvolt = <75000 150000 237000 500000 500000 500000 500000 500000>;
+		qcom,mbhc-headset-vthreshold-microvolt = <1700000>;
+		qcom,mbhc-headphone-vthreshold-microvolt = <50000>;
+		qcom,rx-device = <&wcd_rx>;
+		qcom,tx-device = <&wcd_tx>;
+
+		reset-gpios = <&tlmm 191 GPIO_ACTIVE_LOW>;
+
+		vdd-buck-supply = <&vreg_l15b_1p8>;
+		vdd-rxtx-supply = <&vreg_l15b_1p8>;
+		vdd-io-supply = <&vreg_l15b_1p8>;
+		vdd-mic-bias-supply = <&vreg_bob1>;
+
+		#sound-dai-cells = <1>;
+	};
+
+	backlight: backlight {
+		compatible = "pwm-backlight";
+		pwms = <&pmk8550_pwm 0 5000000>;
+
+		brightness-levels = <0 2048 4096 8192 16384 65535>;
+		num-interpolated-steps = <20>;
+		default-brightness-level = <80>;
+
+		enable-gpios = <&pmc8380_3_gpios 4 GPIO_ACTIVE_HIGH>;
+		power-supply = <&vreg_edp_bl>;
+
+		pinctrl-0 = <&edp_bl_en>, <&edp_bl_pwm>;
+		pinctrl-names = "default";
+	};
+
+	gpio-keys {
+		compatible = "gpio-keys";
+
+		pinctrl-0 = <&hall_int_n_default>;
+		pinctrl-names = "default";
+
+		switch-lid {
+			gpios = <&tlmm 92 GPIO_ACTIVE_LOW>;
+			linux,input-type = <EV_SW>;
+			linux,code = <SW_LID>;
+			wakeup-source;
+			wakeup-event-action = <EV_ACT_DEASSERTED>;
+		};
+	};
+
+	pmic-glink {
+		compatible = "qcom,x1e80100-pmic-glink",
+			     "qcom,sm8550-pmic-glink",
+			     "qcom,pmic-glink";
+		orientation-gpios = <&tlmm 121 GPIO_ACTIVE_HIGH>,
+				    <&tlmm 123 GPIO_ACTIVE_HIGH>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		/* Left-side port, closer to the screen */
+		connector@0 {
+			compatible = "usb-c-connector";
+			reg = <0>;
+			power-role = "dual";
+			data-role = "dual";
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					reg = <0>;
+
+					pmic_glink_ss0_hs_in: endpoint {
+						remote-endpoint = <&usb_1_ss0_dwc3_hs>;
+					};
+				};
+
+				port@1 {
+					reg = <1>;
+
+					pmic_glink_ss0_ss_in: endpoint {
+						remote-endpoint = <&retimer_ss0_ss_out>;
+					};
+				};
+
+				port@2 {
+					reg = <2>;
+
+					pmic_glink_ss0_con_sbu_in: endpoint {
+						remote-endpoint = <&retimer_ss0_con_sbu_out>;
+					};
+				};
+			};
+		};
+
+		/* Left-side port, farther from the screen */
+		connector@1 {
+			compatible = "usb-c-connector";
+			reg = <1>;
+			power-role = "dual";
+			data-role = "dual";
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					reg = <0>;
+
+					pmic_glink_ss1_hs_in: endpoint {
+						remote-endpoint = <&usb_1_ss1_dwc3_hs>;
+					};
+				};
+
+				port@1 {
+					reg = <1>;
+
+					pmic_glink_ss1_ss_in: endpoint {
+						remote-endpoint = <&retimer_ss1_ss_out>;
+					};
+				};
+
+				port@2 {
+					reg = <2>;
+
+					pmic_glink_ss1_con_sbu_in: endpoint {
+						remote-endpoint = <&retimer_ss1_con_sbu_out>;
+					};
+				};
+			};
+		};
+	};
+
+	reserved-memory {
+		linux,cma {
+			compatible = "shared-dma-pool";
+			size = <0x0 0x8000000>;
+			reusable;
+			linux,cma-default;
+		};
+	};
+
+	sound {
+		compatible = "qcom,x1e80100-sndcard";
+		model = "X1E80100-HP-OMNIBOOK-X14";
+		audio-routing = "SpkrLeft IN", "WSA WSA_SPK1 OUT",
+				"SpkrRight IN", "WSA WSA_SPK2 OUT",
+				"IN1_HPHL", "HPHL_OUT",
+				"IN2_HPHR", "HPHR_OUT",
+				"AMIC2", "MIC BIAS2",
+				"VA DMIC0", "MIC BIAS3",
+				"VA DMIC1", "MIC BIAS3",
+				"VA DMIC2", "MIC BIAS1",
+				"VA DMIC3", "MIC BIAS1",
+				"VA DMIC0", "VA MIC BIAS3",
+				"VA DMIC1", "VA MIC BIAS3",
+				"VA DMIC2", "VA MIC BIAS1",
+				"VA DMIC3", "VA MIC BIAS1",
+				"TX SWR_INPUT1", "ADC2_OUTPUT";
+
+		wcd-playback-dai-link {
+			link-name = "WCD Playback";
+
+			cpu {
+				sound-dai = <&q6apmbedai RX_CODEC_DMA_RX_0>;
+			};
+
+			codec {
+				sound-dai = <&wcd938x 0>, <&swr1 0>, <&lpass_rxmacro 0>;
+			};
+
+			platform {
+				sound-dai = <&q6apm>;
+			};
+		};
+
+		wcd-capture-dai-link {
+			link-name = "WCD Capture";
+
+			cpu {
+				sound-dai = <&q6apmbedai TX_CODEC_DMA_TX_3>;
+			};
+
+			codec {
+				sound-dai = <&wcd938x 1>, <&swr2 1>, <&lpass_txmacro 0>;
+			};
+
+			platform {
+				sound-dai = <&q6apm>;
+			};
+		};
+
+		wsa-dai-link {
+			link-name = "WSA Playback";
+
+			cpu {
+				sound-dai = <&q6apmbedai WSA_CODEC_DMA_RX_0>;
+			};
+
+			codec {
+				sound-dai = <&left_spkr>, <&right_spkr>, <&swr0 0>, <&lpass_wsamacro 0>;
+			};
+
+			platform {
+				sound-dai = <&q6apm>;
+			};
+		};
+
+		va-dai-link {
+			link-name = "VA Capture";
+
+			cpu {
+				sound-dai = <&q6apmbedai VA_CODEC_DMA_TX_0>;
+			};
+
+			codec {
+				sound-dai = <&lpass_vamacro 0>;
+			};
+
+			platform {
+				sound-dai = <&q6apm>;
+			};
+		};
+	};
+
+	vreg_edp_3p3: regulator-edp-3p3 {
+		compatible = "regulator-fixed";
+
+		regulator-name = "VREG_EDP_3P3";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+
+		gpio = <&tlmm 70 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+
+		pinctrl-0 = <&edp_reg_en>;
+		pinctrl-names = "default";
+
+		regulator-boot-on;
+	};
+
+	vreg_edp_bl: regulator-edp-bl {
+		compatible = "regulator-fixed";
+
+		regulator-name = "VBL9";
+		regulator-min-microvolt = <3600000>;
+		regulator-max-microvolt = <3600000>;
+
+		gpio = <&pmc8380_3_gpios 10 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+
+		pinctrl-names = "default";
+		pinctrl-0 = <&edp_bl_reg_en>;
+
+		regulator-boot-on;
+	};
+
+	vreg_misc_3p3: regulator-misc-3p3 {
+		compatible = "regulator-fixed";
+
+		regulator-name = "VREG_MISC_3P3";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+
+		gpio = <&pm8550ve_8_gpios 6 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+
+		pinctrl-names = "default";
+		pinctrl-0 = <&misc_3p3_reg_en>;
+
+		regulator-boot-on;
+		regulator-always-on;
+	};
+
+	vreg_nvme: regulator-nvme {
+		compatible = "regulator-fixed";
+
+		regulator-name = "VREG_NVME_3P3";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+
+		gpio = <&tlmm 18 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+
+		pinctrl-0 = <&nvme_reg_en>;
+		pinctrl-names = "default";
+
+		regulator-boot-on;
+	};
+
+	vreg_rtmr0_1p15: regulator-rtmr0-1p15 {
+		compatible = "regulator-fixed";
+
+		regulator-name = "VREG_RTMR0_1P15";
+		regulator-min-microvolt = <1150000>;
+		regulator-max-microvolt = <1150000>;
+
+		gpio = <&pmc8380_5_gpios 8 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+
+		pinctrl-0 = <&usb0_pwr_1p15_reg_en>;
+		pinctrl-names = "default";
+
+		regulator-boot-on;
+	};
+
+	vreg_rtmr0_1p8: regulator-rtmr0-1p8 {
+		compatible = "regulator-fixed";
+
+		regulator-name = "VREG_RTMR0_1P8";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+
+		gpio = <&pm8550ve_9_gpios 8 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+
+		pinctrl-0 = <&usb0_1p8_reg_en>;
+		pinctrl-names = "default";
+
+		regulator-boot-on;
+	};
+
+	vreg_rtmr0_3p3: regulator-rtmr0-3p3 {
+		compatible = "regulator-fixed";
+
+		regulator-name = "VREG_RTMR0_3P3";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+
+		gpio = <&pm8550_gpios 11 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+
+		pinctrl-0 = <&usb0_3p3_reg_en>;
+		pinctrl-names = "default";
+
+		regulator-boot-on;
+	};
+
+	vreg_rtmr1_1p15: regulator-rtmr1-1p15 {
+		compatible = "regulator-fixed";
+
+		regulator-name = "VREG_RTMR1_1P15";
+		regulator-min-microvolt = <1150000>;
+		regulator-max-microvolt = <1150000>;
+
+		gpio = <&tlmm 188 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+
+		pinctrl-0 = <&usb1_pwr_1p15_reg_en>;
+		pinctrl-names = "default";
+
+		regulator-boot-on;
+	};
+
+	vreg_rtmr1_1p8: regulator-rtmr1-1p8 {
+		compatible = "regulator-fixed";
+
+		regulator-name = "VREG_RTMR1_1P8";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+
+		gpio = <&tlmm 175 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+
+		pinctrl-0 = <&usb1_pwr_1p8_reg_en>;
+		pinctrl-names = "default";
+
+		regulator-boot-on;
+	};
+
+	vreg_rtmr1_3p3: regulator-rtmr1-3p3 {
+		compatible = "regulator-fixed";
+
+		regulator-name = "VREG_RTMR1_3P3";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+
+		gpio = <&tlmm 186 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+
+		pinctrl-0 = <&usb1_pwr_3p3_reg_en>;
+		pinctrl-names = "default";
+
+		regulator-boot-on;
+	};
+
+	vreg_vph_pwr: regulator-vph-pwr {
+		compatible = "regulator-fixed";
+
+		regulator-name = "vreg_vph_pwr";
+		regulator-min-microvolt = <3700000>;
+		regulator-max-microvolt = <3700000>;
+
+		regulator-always-on;
+		regulator-boot-on;
+	};
+
+	vreg_wcn_3p3: regulator-wcn-3p3 {
+		compatible = "regulator-fixed";
+
+		regulator-name = "VREG_WCN_3P3";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+
+		gpio = <&tlmm 214 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+
+		pinctrl-0 = <&wcn_sw_en>;
+		pinctrl-names = "default";
+
+		regulator-boot-on;
+	};
+
+	/*
+	 * TODO: These two regulators are actually part of the removable M.2
+	 * card and not the CRD mainboard. Need to describe this differently.
+	 * Functionally it works correctly, because all we need to do is to
+	 * turn on the actual 3.3V supply above.
+	 */
+	vreg_wcn_0p95: regulator-wcn-0p95 {
+		compatible = "regulator-fixed";
+
+		regulator-name = "VREG_WCN_0P95";
+		regulator-min-microvolt = <950000>;
+		regulator-max-microvolt = <950000>;
+
+		vin-supply = <&vreg_wcn_3p3>;
+	};
+
+	vreg_wcn_1p9: regulator-wcn-1p9 {
+		compatible = "regulator-fixed";
+
+		regulator-name = "VREG_WCN_1P9";
+		regulator-min-microvolt = <1900000>;
+		regulator-max-microvolt = <1900000>;
+
+		vin-supply = <&vreg_wcn_3p3>;
+	};
+
+	wcn6855-pmu {
+		compatible = "qcom,wcn6855-pmu";
+
+		vddaon-supply = <&vreg_wcn_0p95>;
+		vddio-supply = <&vreg_wcn_1p9>;
+		vddpcie1p3-supply = <&vreg_wcn_1p9>;
+		vddpcie1p9-supply = <&vreg_wcn_1p9>;
+		vddpmu-supply = <&vreg_wcn_0p95>;
+		vddpmumx-supply = <&vreg_wcn_0p95>;
+		vddpmucx-supply = <&vreg_wcn_0p95>;
+		vddrfa0p95-supply = <&vreg_wcn_0p95>;
+		vddrfa1p3-supply = <&vreg_wcn_1p9>;
+		vddrfa1p9-supply = <&vreg_wcn_1p9>;
+
+		wlan-enable-gpios = <&tlmm 117 GPIO_ACTIVE_HIGH>;
+		bt-enable-gpios = <&tlmm 116 GPIO_ACTIVE_HIGH>;
+
+		pinctrl-0 = <&wcn_wlan_bt_en>;
+		pinctrl-names = "default";
+
+		regulators {
+			vreg_pmu_rfa_cmn_0p8: ldo0 {
+				regulator-name = "vreg_pmu_rfa_cmn_0p8";
+			};
+
+			vreg_pmu_aon_0p8: ldo1 {
+				regulator-name = "vreg_pmu_aon_0p8";
+			};
+
+			vreg_pmu_wlcx_0p8: ldo2 {
+				regulator-name = "vreg_pmu_wlcx_0p8";
+			};
+
+			vreg_pmu_wlmx_0p8: ldo3 {
+				regulator-name = "vreg_pmu_wlmx_0p8";
+			};
+
+			vreg_pmu_btcmx_0p8: ldo4 {
+				regulator-name = "vreg_pmu_btcmx_0p8";
+			};
+
+			vreg_pmu_pcie_1p8: ldo5 {
+				regulator-name = "vreg_pmu_pcie_1p8";
+			};
+
+			vreg_pmu_pcie_0p9: ldo6 {
+				regulator-name = "vreg_pmu_pcie_0p9";
+			};
+
+			vreg_pmu_rfa_0p8: ldo7 {
+				regulator-name = "vreg_pmu_rfa_0p8";
+			};
+
+			vreg_pmu_rfa_1p2: ldo8 {
+				regulator-name = "vreg_pmu_rfa_1p2";
+			};
+
+			vreg_pmu_rfa_1p7: ldo9 {
+				regulator-name = "vreg_pmu_rfa_1p7";
+			};
+		};
+	};
+};
+
+&apps_rsc {
+	regulators-0 {
+		compatible = "qcom,pm8550-rpmh-regulators";
+		qcom,pmic-id = "b";
+
+		vdd-bob1-supply = <&vreg_vph_pwr>;
+		vdd-bob2-supply = <&vreg_vph_pwr>;
+		vdd-l1-l4-l10-supply = <&vreg_s4c_1p8>;
+		vdd-l2-l13-l14-supply = <&vreg_bob1>;
+		vdd-l5-l16-supply = <&vreg_bob1>;
+		vdd-l6-l7-supply = <&vreg_bob2>;
+		vdd-l8-l9-supply = <&vreg_bob1>;
+		vdd-l12-supply = <&vreg_s5j_1p2>;
+		vdd-l15-supply = <&vreg_s4c_1p8>;
+		vdd-l17-supply = <&vreg_bob2>;
+
+		vreg_bob1: bob1 {
+			regulator-name = "vreg_bob1";
+			regulator-min-microvolt = <3008000>;
+			regulator-max-microvolt = <3960000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_bob2: bob2 {
+			regulator-name = "vreg_bob2";
+			regulator-min-microvolt = <2504000>;
+			regulator-max-microvolt = <3008000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l1b_1p8: ldo1 {
+			regulator-name = "vreg_l1b_1p8";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l2b_3p0: ldo2 {
+			regulator-name = "vreg_l2b_3p0";
+			regulator-min-microvolt = <3072000>;
+			regulator-max-microvolt = <3100000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l4b_1p8: ldo4 {
+			regulator-name = "vreg_l4b_1p8";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l5b_3p0: ldo5 {
+			regulator-name = "vreg_l5b_3p0";
+			regulator-min-microvolt = <3000000>;
+			regulator-max-microvolt = <3000000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l6b_1p8: ldo6 {
+			regulator-name = "vreg_l6b_1p8";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <2960000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l7b_2p8: ldo7 {
+			regulator-name = "vreg_l7b_2p8";
+			regulator-min-microvolt = <2800000>;
+			regulator-max-microvolt = <2800000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l8b_3p0: ldo8 {
+			regulator-name = "vreg_l8b_3p0";
+			regulator-min-microvolt = <3072000>;
+			regulator-max-microvolt = <3072000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l9b_2p9: ldo9 {
+			regulator-name = "vreg_l9b_2p9";
+			regulator-min-microvolt = <2960000>;
+			regulator-max-microvolt = <2960000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l10b_1p8: ldo10 {
+			regulator-name = "vreg_l10b_1p8";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l12b_1p2: ldo12 {
+			regulator-name = "vreg_l12b_1p2";
+			regulator-min-microvolt = <1200000>;
+			regulator-max-microvolt = <1200000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l13b_3p0: ldo13 {
+			regulator-name = "vreg_l13b_3p0";
+			regulator-min-microvolt = <3072000>;
+			regulator-max-microvolt = <3100000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l14b_3p0: ldo14 {
+			regulator-name = "vreg_l14b_3p0";
+			regulator-min-microvolt = <3072000>;
+			regulator-max-microvolt = <3072000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l15b_1p8: ldo15 {
+			regulator-name = "vreg_l15b_1p8";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l16b_2p9: ldo16 {
+			regulator-name = "vreg_l16b_2p9";
+			regulator-min-microvolt = <2912000>;
+			regulator-max-microvolt = <2912000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l17b_2p5: ldo17 {
+			regulator-name = "vreg_l17b_2p5";
+			regulator-min-microvolt = <2504000>;
+			regulator-max-microvolt = <2504000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+	};
+
+	regulators-1 {
+		compatible = "qcom,pm8550ve-rpmh-regulators";
+		qcom,pmic-id = "c";
+
+		vdd-l1-supply = <&vreg_s5j_1p2>;
+		vdd-l2-supply = <&vreg_s1f_0p7>;
+		vdd-l3-supply = <&vreg_s1f_0p7>;
+		vdd-s4-supply = <&vreg_vph_pwr>;
+
+		vreg_s4c_1p8: smps4 {
+			regulator-name = "vreg_s4c_1p8";
+			regulator-min-microvolt = <1856000>;
+			regulator-max-microvolt = <2000000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l1c_1p2: ldo1 {
+			regulator-name = "vreg_l1c_1p2";
+			regulator-min-microvolt = <1200000>;
+			regulator-max-microvolt = <1200000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l2c_0p8: ldo2 {
+			regulator-name = "vreg_l2c_0p8";
+			regulator-min-microvolt = <880000>;
+			regulator-max-microvolt = <920000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l3c_0p8: ldo3 {
+			regulator-name = "vreg_l3c_0p8";
+			regulator-min-microvolt = <880000>;
+			regulator-max-microvolt = <920000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+	};
+
+	regulators-2 {
+		compatible = "qcom,pmc8380-rpmh-regulators";
+		qcom,pmic-id = "d";
+
+		vdd-l1-supply = <&vreg_s1f_0p7>;
+		vdd-l2-supply = <&vreg_s1f_0p7>;
+		vdd-l3-supply = <&vreg_s4c_1p8>;
+		vdd-s1-supply = <&vreg_vph_pwr>;
+
+		vreg_l1d_0p8: ldo1 {
+			regulator-name = "vreg_l1d_0p8";
+			regulator-min-microvolt = <880000>;
+			regulator-max-microvolt = <920000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l2d_0p9: ldo2 {
+			regulator-name = "vreg_l2d_0p9";
+			regulator-min-microvolt = <912000>;
+			regulator-max-microvolt = <920000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l3d_1p8: ldo3 {
+			regulator-name = "vreg_l3d_1p8";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+	};
+
+	regulators-3 {
+		compatible = "qcom,pmc8380-rpmh-regulators";
+		qcom,pmic-id = "e";
+
+		vdd-l2-supply = <&vreg_s1f_0p7>;
+		vdd-l3-supply = <&vreg_s5j_1p2>;
+
+		vreg_l2e_0p8: ldo2 {
+			regulator-name = "vreg_l2e_0p8";
+			regulator-min-microvolt = <880000>;
+			regulator-max-microvolt = <920000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l3e_1p2: ldo3 {
+			regulator-name = "vreg_l3e_1p2";
+			regulator-min-microvolt = <1200000>;
+			regulator-max-microvolt = <1200000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+	};
+
+	regulators-4 {
+		compatible = "qcom,pmc8380-rpmh-regulators";
+		qcom,pmic-id = "f";
+
+		vdd-l1-supply = <&vreg_s5j_1p2>;
+		vdd-l2-supply = <&vreg_s5j_1p2>;
+		vdd-l3-supply = <&vreg_s5j_1p2>;
+		vdd-s1-supply = <&vreg_vph_pwr>;
+
+		vreg_s1f_0p7: smps1 {
+			regulator-name = "vreg_s1f_0p7";
+			regulator-min-microvolt = <700000>;
+			regulator-max-microvolt = <1100000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l1f_1p0: ldo1 {
+			regulator-name = "vreg_l1f_1p0";
+			regulator-min-microvolt = <1024000>;
+			regulator-max-microvolt = <1024000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l2f_1p0: ldo2 {
+			regulator-name = "vreg_l2f_1p0";
+			regulator-min-microvolt = <1024000>;
+			regulator-max-microvolt = <1024000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l3f_1p0: ldo3 {
+			regulator-name = "vreg_l3f_1p0";
+			regulator-min-microvolt = <1024000>;
+			regulator-max-microvolt = <1024000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+	};
+
+	regulators-6 {
+		compatible = "qcom,pm8550ve-rpmh-regulators";
+		qcom,pmic-id = "i";
+
+		vdd-l1-supply = <&vreg_s4c_1p8>;
+		vdd-l2-supply = <&vreg_s5j_1p2>;
+		vdd-l3-supply = <&vreg_s1f_0p7>;
+		vdd-s1-supply = <&vreg_vph_pwr>;
+		vdd-s2-supply = <&vreg_vph_pwr>;
+
+		vreg_s1i_0p9: smps1 {
+			regulator-name = "vreg_s1i_0p9";
+			regulator-min-microvolt = <900000>;
+			regulator-max-microvolt = <920000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_s2i_1p0: smps2 {
+			regulator-name = "vreg_s2i_1p0";
+			regulator-min-microvolt = <1000000>;
+			regulator-max-microvolt = <1100000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l1i_1p8: ldo1 {
+			regulator-name = "vreg_l1i_1p8";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l2i_1p2: ldo2 {
+			regulator-name = "vreg_l2i_1p2";
+			regulator-min-microvolt = <1200000>;
+			regulator-max-microvolt = <1200000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l3i_0p8: ldo3 {
+			regulator-name = "vreg_l3i_0p8";
+			regulator-min-microvolt = <880000>;
+			regulator-max-microvolt = <920000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+	};
+
+	regulators-7 {
+		compatible = "qcom,pm8550ve-rpmh-regulators";
+		qcom,pmic-id = "j";
+
+		vdd-l1-supply = <&vreg_s1f_0p7>;
+		vdd-l2-supply = <&vreg_s5j_1p2>;
+		vdd-l3-supply = <&vreg_s1f_0p7>;
+		vdd-s5-supply = <&vreg_vph_pwr>;
+
+		vreg_s5j_1p2: smps5 {
+			regulator-name = "vreg_s5j_1p2";
+			regulator-min-microvolt = <1256000>;
+			regulator-max-microvolt = <1304000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l1j_0p8: ldo1 {
+			regulator-name = "vreg_l1j_0p8";
+			regulator-min-microvolt = <880000>;
+			regulator-max-microvolt = <920000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l2j_1p2: ldo2 {
+			regulator-name = "vreg_l2j_1p2";
+			regulator-min-microvolt = <1200000>;
+			regulator-max-microvolt = <1200000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l3j_0p8: ldo3 {
+			regulator-name = "vreg_l3j_0p8";
+			regulator-min-microvolt = <880000>;
+			regulator-max-microvolt = <920000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+	};
+};
+
+&gpu {
+	status = "okay";
+
+	zap-shader {
+		firmware-name = "qcom/x1e80100/hp/omnibook-x14/qcdxkmsuc8380.mbn";
+	};
+};
+
+&i2c0 {
+	clock-frequency = <400000>;
+
+	status = "okay";
+
+	keyboard@3a {
+		compatible = "hid-over-i2c";
+		reg = <0x3a>;
+
+		hid-descr-addr = <0x1>;
+		interrupts-extended = <&tlmm 67 IRQ_TYPE_LEVEL_LOW>;
+
+		vdd-supply = <&vreg_misc_3p3>;
+		vddl-supply = <&vreg_l12b_1p2>;
+
+		pinctrl-0 = <&kybd_default>;
+		pinctrl-names = "default";
+
+		wakeup-source;
+	};
+
+	touchpad@15 {
+		compatible = "hid-over-i2c";
+		reg = <0x15>;
+
+		hid-descr-addr = <0x1>;
+		interrupts-extended = <&tlmm 3 IRQ_TYPE_LEVEL_LOW>;
+
+		vdd-supply = <&vreg_misc_3p3>;
+		vddl-supply = <&vreg_l12b_1p2>;
+
+		pinctrl-0 = <&tpad_default>;
+		pinctrl-names = "default";
+
+		wakeup-source;
+	};
+};
+
+&i2c1 {
+	clock-frequency = <400000>;
+
+	status = "okay";
+
+	/* type-c PS8830 Retimer #2 0x8 */
+	/* is active on Windows */
+};
+
+&i2c3 {
+	clock-frequency = <400000>;
+
+	status = "okay";
+
+	typec-mux@8 {
+		compatible = "parade,ps8830";
+		reg = <0x08>;
+
+		clocks = <&rpmhcc RPMH_RF_CLK3>;
+
+		vdd-supply = <&vreg_rtmr0_1p15>;
+		vdd33-supply = <&vreg_rtmr0_3p3>;
+		vdd33-cap-supply = <&vreg_rtmr0_3p3>;
+		vddar-supply = <&vreg_rtmr0_1p15>;
+		vddat-supply = <&vreg_rtmr0_1p15>;
+		vddio-supply = <&vreg_rtmr0_1p8>;
+
+		reset-gpios = <&pm8550_gpios 10 GPIO_ACTIVE_LOW>;
+
+		pinctrl-0 = <&rtmr0_default>;
+		pinctrl-names = "default";
+
+		orientation-switch;
+		retimer-switch;
+
+		ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@0 {
+				reg = <0>;
+
+				retimer_ss0_ss_out: endpoint {
+					remote-endpoint = <&pmic_glink_ss0_ss_in>;
+				};
+			};
+
+			port@1 {
+				reg = <1>;
+
+				retimer_ss0_ss_in: endpoint {
+					remote-endpoint = <&usb_1_ss0_qmpphy_out>;
+				};
+			};
+
+			port@2 {
+				reg = <2>;
+
+				retimer_ss0_con_sbu_out: endpoint {
+					remote-endpoint = <&pmic_glink_ss0_con_sbu_in>;
+				};
+			};
+		};
+	};
+};
+
+&i2c4 {
+	clock-frequency = <400000>;
+
+	status = "okay";
+
+	/* is active on Windows */
+};
+
+&i2c5 {
+	clock-frequency = <400000>;
+	status = "okay";
+
+	eusb3_repeater: redriver@47 {
+		compatible = "nxp,ptn3222";
+		reg = <0x47>;
+		#phy-cells = <0>;
+
+		vdd3v3-supply = <&vreg_l13b_3p0>;
+		vdd1v8-supply = <&vreg_l4b_1p8>;
+
+		reset-gpios = <&tlmm 6 GPIO_ACTIVE_LOW>;
+
+		pinctrl-0 = <&eusb3_reset_n>;
+		pinctrl-names = "default";
+
+	};
+};
+
+&i2c7 {
+	clock-frequency = <400000>;
+
+	status = "okay";
+
+	typec-mux@8 {
+		compatible = "parade,ps8830";
+		reg = <0x8>;
+
+		clocks = <&rpmhcc RPMH_RF_CLK4>;
+
+		vdd-supply = <&vreg_rtmr1_1p15>;
+		vdd33-supply = <&vreg_rtmr1_3p3>;
+		vdd33-cap-supply = <&vreg_rtmr1_3p3>;
+		vddar-supply = <&vreg_rtmr1_1p15>;
+		vddat-supply = <&vreg_rtmr1_1p15>;
+		vddio-supply = <&vreg_rtmr1_1p8>;
+
+		reset-gpios = <&tlmm 176 GPIO_ACTIVE_LOW>;
+
+		pinctrl-0 = <&rtmr1_default>;
+		pinctrl-names = "default";
+
+		orientation-switch;
+		retimer-switch;
+
+		ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@0 {
+				reg = <0>;
+
+				retimer_ss1_ss_out: endpoint {
+					remote-endpoint = <&pmic_glink_ss1_ss_in>;
+				};
+			};
+
+			port@1 {
+				reg = <1>;
+
+				retimer_ss1_ss_in: endpoint {
+					remote-endpoint = <&usb_1_ss1_qmpphy_out>;
+				};
+			};
+
+			port@2 {
+				reg = <2>;
+
+				retimer_ss1_con_sbu_out: endpoint {
+					remote-endpoint = <&pmic_glink_ss1_con_sbu_in>;
+				};
+			};
+
+		};
+	};
+};
+
+&i2c8 {
+	clock-frequency = <400000>;
+
+	status = "okay";
+
+	touchscreen@10 {
+		compatible = "hid-over-i2c";
+		reg = <0x10>;
+
+		hid-descr-addr = <0x1>;
+		interrupts-extended = <&tlmm 51 IRQ_TYPE_LEVEL_LOW>;
+
+		vdd-supply = <&vreg_misc_3p3>;
+		vddl-supply = <&vreg_l15b_1p8>;
+
+		pinctrl-0 = <&ts0_default>;
+		pinctrl-names = "default";
+	};
+};
+
+&i2c9 {
+	clock-frequency = <400000>;
+
+	status = "okay";
+
+	/* is active on Windows */
+};
+
+&lpass_tlmm {
+	spkr_01_sd_n_active: spkr-01-sd-n-active-state {
+		pins = "gpio12";
+		function = "gpio";
+		drive-strength = <16>;
+		bias-disable;
+		output-low;
+	};
+};
+
+&lpass_vamacro {
+	pinctrl-0 = <&dmic01_default>, <&dmic23_default>;
+	pinctrl-names = "default";
+
+	vdd-micb-supply = <&vreg_l1b_1p8>;
+	qcom,dmic-sample-rate = <4800000>;
+};
+
+&mdss {
+	status = "okay";
+};
+
+&mdss_dp0 {
+	status = "okay";
+};
+
+&mdss_dp0_out {
+	data-lanes = <0 1>;
+};
+
+&mdss_dp1 {
+	status = "okay";
+};
+
+&mdss_dp1_out {
+	data-lanes = <0 1>;
+};
+
+&mdss_dp3 {
+	compatible = "qcom,x1e80100-dp";
+	/delete-property/ #sound-dai-cells;
+
+	status = "okay";
+
+	aux-bus {
+		panel {
+			compatible = "edp-panel";
+			power-supply = <&vreg_edp_3p3>;
+
+			backlight = <&backlight>;
+
+			port {
+				edp_panel_in: endpoint {
+					remote-endpoint = <&mdss_dp3_out>;
+				};
+			};
+		};
+	};
+
+	ports {
+		port@1 {
+			reg = <1>;
+
+			mdss_dp3_out: endpoint {
+				data-lanes = <0 1 2 3>;
+				link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>;
+
+				remote-endpoint = <&edp_panel_in>;
+			};
+		};
+	};
+};
+
+&mdss_dp3_phy {
+	vdda-phy-supply = <&vreg_l3j_0p8>;
+	vdda-pll-supply = <&vreg_l2j_1p2>;
+
+	status = "okay";
+};
+
+&pcie4 {
+	perst-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>;
+	wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;
+
+	pinctrl-0 = <&pcie4_default>;
+	pinctrl-names = "default";
+
+	status = "okay";
+};
+
+&pcie4_phy {
+	vdda-phy-supply = <&vreg_l3i_0p8>;
+	vdda-pll-supply = <&vreg_l3e_1p2>;
+
+	status = "okay";
+};
+
+&pcie4_port0 {
+	wifi@0 {
+		compatible = "pci17cb,1107";
+		reg = <0x10000 0x0 0x0 0x0 0x0>;
+
+		vddaon-supply = <&vreg_pmu_aon_0p8>;
+		vddpcie0p9-supply = <&vreg_pmu_pcie_0p9>;
+		vddpcie1p8-supply = <&vreg_pmu_pcie_1p8>;
+		vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>;
+		vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>;
+		vddrfa1p8-supply = <&vreg_pmu_rfa_1p7>;
+		vddrfacmn-supply = <&vreg_pmu_rfa_cmn_0p8>;
+		vddwlcx-supply = <&vreg_pmu_wlcx_0p8>;
+		vddwlmx-supply = <&vreg_pmu_wlmx_0p8>;
+	};
+};
+
+&pcie6a {
+	perst-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>;
+	wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>;
+
+	vddpe-3v3-supply = <&vreg_nvme>;
+
+	pinctrl-0 = <&pcie6a_default>;
+	pinctrl-names = "default";
+
+	status = "okay";
+};
+
+&pcie6a_phy {
+	vdda-phy-supply = <&vreg_l1d_0p8>;
+	vdda-pll-supply = <&vreg_l2j_1p2>;
+
+	status = "okay";
+};
+
+&pm8550_gpios {
+	rtmr0_default: rtmr0-reset-n-active-state {
+		pins = "gpio10";
+		function = "normal";
+		power-source = <1>; /* 1.8V */
+		bias-disable;
+		input-disable;
+		output-enable;
+	};
+
+	usb0_3p3_reg_en: usb0-3p3-reg-en-state {
+		pins = "gpio11";
+		function = "normal";
+		power-source = <1>; /* 1.8V */
+		bias-disable;
+		input-disable;
+		output-enable;
+	};
+};
+
+&pm8550ve_8_gpios {
+	misc_3p3_reg_en: misc-3p3-reg-en-state {
+		pins = "gpio6";
+		function = "normal";
+		bias-disable;
+		drive-push-pull;
+		input-disable;
+		output-enable;
+		power-source = <1>; /* 1.8 V */
+		qcom,drive-strength = <PMIC_GPIO_STRENGTH_LOW>;
+	};
+};
+
+&pm8550ve_9_gpios {
+	usb0_1p8_reg_en: usb0-1p8-reg-en-state {
+		pins = "gpio8";
+		function = "normal";
+		power-source = <1>; /* 1.8V */
+		bias-disable;
+		input-disable;
+		output-enable;
+	};
+};
+
+&pmc8380_3_gpios {
+	edp_bl_en: edp-bl-en-state {
+		pins = "gpio4";
+		function = "normal";
+		power-source = <1>; /* 1.8V */
+		input-disable;
+		output-enable;
+	};
+
+	edp_bl_reg_en: edp-bl-reg-en-state {
+		pins = "gpio10";
+		function = "normal";
+	};
+
+};
+
+&pmk8550_gpios {
+	edp_bl_pwm: edp-bl-pwm-state {
+		pins = "gpio5";
+		function = "func3";
+	};
+};
+
+&pmk8550_pwm {
+	status = "okay";
+};
+
+&pmc8380_5_gpios {
+	usb0_pwr_1p15_reg_en: usb0-pwr-1p15-reg-en-state {
+		pins = "gpio8";
+		function = "normal";
+		power-source = <1>; /* 1.8V */
+		bias-disable;
+		input-disable;
+		output-enable;
+	};
+};
+
+&qupv3_0 {
+	status = "okay";
+};
+
+&qupv3_1 {
+	status = "okay";
+};
+
+&qupv3_2 {
+	status = "okay";
+};
+
+&remoteproc_adsp {
+	firmware-name = "qcom/x1e80100/hp/omnibook-x14/qcadsp8380.mbn",
+			"qcom/x1e80100/hp/omnibook-x14/adsp_dtbs.elf";
+
+	status = "okay";
+};
+
+&remoteproc_cdsp {
+	firmware-name = "qcom/x1e80100/hp/omnibook-x14/qccdsp8380.mbn",
+			"qcom/x1e80100/hp/omnibook-x14/cdsp_dtbs.elf";
+
+	status = "okay";
+};
+
+&smb2360_0_eusb2_repeater {
+	vdd18-supply = <&vreg_l3d_1p8>;
+	vdd3-supply = <&vreg_l2b_3p0>;
+
+	status = "okay";
+};
+
+&smb2360_1_eusb2_repeater {
+	vdd18-supply = <&vreg_l3d_1p8>;
+	vdd3-supply = <&vreg_l14b_3p0>;
+
+	status = "okay";
+};
+
+&swr0 {
+	pinctrl-0 = <&wsa_swr_active>, <&spkr_01_sd_n_active>;
+	pinctrl-names = "default";
+
+	status = "okay";
+
+	/* WSA8845, Left Speaker */
+	left_spkr: speaker@0,0 {
+		compatible = "sdw20217020400";
+		reg = <0 0>;
+		reset-gpios = <&lpass_tlmm 12 GPIO_ACTIVE_LOW>;
+		#sound-dai-cells = <0>;
+		sound-name-prefix = "SpkrLeft";
+		vdd-1p8-supply = <&vreg_l15b_1p8>;
+		vdd-io-supply = <&vreg_l12b_1p2>;
+		qcom,port-mapping = <1 2 3 7 10 13>;
+	};
+
+	/* WSA8845, Right Speaker */
+	right_spkr: speaker@0,1 {
+		compatible = "sdw20217020400";
+		reg = <0 1>;
+		reset-gpios = <&lpass_tlmm 12 GPIO_ACTIVE_LOW>;
+		#sound-dai-cells = <0>;
+		sound-name-prefix = "SpkrRight";
+		vdd-1p8-supply = <&vreg_l15b_1p8>;
+		vdd-io-supply = <&vreg_l12b_1p2>;
+		qcom,port-mapping = <4 5 6 7 11 13>;
+	};
+};
+
+&swr1 {
+	status = "okay";
+
+	/* WCD9385 RX */
+	wcd_rx: codec@0,4 {
+		compatible = "sdw20217010d00";
+		reg = <0 4>;
+		qcom,rx-port-mapping = <1 2 3 4 5>;
+	};
+};
+
+&swr2 {
+	status = "okay";
+
+	/* WCD9385 TX */
+	wcd_tx: codec@0,3 {
+		compatible = "sdw20217010d00";
+		reg = <0 3>;
+		qcom,tx-port-mapping = <2 2 3 4>;
+	};
+};
+
+&tlmm {
+	gpio-reserved-ranges = <34 2>, /* Unused */
+			       <44 4>, /* SPI (TPM) */
+			       <72 2>, /* Secure EC I2C connection (?) */
+			       <238 1>; /* UFS Reset */
+
+	bt_en_default: bt-en-sleep {
+		pins = "gpio116";
+		function = "gpio";
+		output-low;
+		bias-disable;
+		drive-strength = <16>;
+	};
+
+	edp_reg_en: edp-reg-en-state {
+		pins = "gpio70";
+		function = "gpio";
+		drive-strength = <16>;
+		bias-disable;
+	};
+
+	eusb3_reset_n: eusb3-reset-n-state {
+		pins = "gpio6";
+		function = "gpio";
+		drive-strength = <2>;
+		bias-disable;
+		output-low;
+	};
+
+	hall_int_n_default: hall-int-n-state {
+		pins = "gpio92";
+		function = "gpio";
+		bias-disable;
+	};
+
+	kybd_default: kybd-default-state {
+		pins = "gpio67";
+		function = "gpio";
+		bias-pull-up;
+	};
+
+	nvme_reg_en: nvme-reg-en-state {
+		pins = "gpio18";
+		function = "gpio";
+		drive-strength = <2>;
+		bias-disable;
+	};
+
+	pcie4_default: pcie4-default-state {
+		clkreq-n-pins {
+			pins = "gpio147";
+			function = "pcie4_clk";
+			drive-strength = <2>;
+			bias-pull-up;
+		};
+
+		perst-n-pins {
+			pins = "gpio146";
+			function = "gpio";
+			drive-strength = <2>;
+			bias-disable;
+		};
+
+		wake-n-pins {
+			pins = "gpio148";
+			function = "gpio";
+			drive-strength = <2>;
+			bias-pull-up;
+		};
+	};
+
+	pcie6a_default: pcie6a-default-state {
+		clkreq-n-pins {
+			pins = "gpio153";
+			function = "pcie6a_clk";
+			drive-strength = <2>;
+			bias-pull-up;
+		};
+
+		perst-n-pins {
+			pins = "gpio152";
+			function = "gpio";
+			drive-strength = <2>;
+			bias-disable;
+		};
+
+		wake-n-pins {
+			pins = "gpio154";
+			function = "gpio";
+			drive-strength = <2>;
+			bias-pull-up;
+		};
+	};
+
+	rtmr1_default: rtmr1-reset-n-active-state {
+		pins = "gpio176";
+		function = "gpio";
+		drive-strength = <2>;
+		bias-disable;
+	};
+
+	tpad_default: tpad-default-state {
+		pins = "gpio3";
+		function = "gpio";
+		bias-pull-up;
+	};
+
+	ts0_default: ts0-default-state {
+		int-n-pins {
+			pins = "gpio51";
+			function = "gpio";
+			bias-pull-up;
+		};
+
+		reset-n-pins {
+			pins = "gpio48";
+			function = "gpio";
+			output-high;
+			drive-strength = <16>;
+		};
+	};
+
+	usb1_pwr_1p15_reg_en: usb1-pwr-1p15-reg-en-state {
+		pins = "gpio188";
+		function = "gpio";
+		drive-strength = <2>;
+		bias-disable;
+	};
+
+	usb1_pwr_1p8_reg_en: usb1-pwr-1p8-reg-en-state {
+		pins = "gpio175";
+		function = "gpio";
+		drive-strength = <2>;
+		bias-disable;
+	};
+
+	usb1_pwr_3p3_reg_en: usb1-pwr-3p3-reg-en-state {
+		pins = "gpio186";
+		function = "gpio";
+		drive-strength = <2>;
+		bias-disable;
+	};
+
+	wcd_default: wcd-reset-n-active-state {
+		pins = "gpio191";
+		function = "gpio";
+		drive-strength = <16>;
+		bias-disable;
+		output-low;
+	};
+
+	wcn_sw_en: wcn-sw-en-state {
+		pins = "gpio214";
+		function = "gpio";
+		drive-strength = <2>;
+		bias-disable;
+	};
+
+	wcn_wlan_bt_en: wcn-wlan-bt-en-state {
+		pins = "gpio116", "gpio117";
+		function = "gpio";
+		drive-strength = <2>;
+		bias-disable;
+	};
+};
+
+&uart14 {
+	status = "okay";
+
+	bluetooth {
+		compatible = "qcom,wcn6855-bt";
+		max-speed = <3200000>;
+
+		vddrfacmn-supply = <&vreg_pmu_rfa_cmn_0p8>;
+		vddaon-supply = <&vreg_pmu_aon_0p8>;
+		vddwlcx-supply = <&vreg_pmu_wlcx_0p8>;
+		vddwlmx-supply = <&vreg_pmu_wlmx_0p8>;
+		vddbtcmx-supply = <&vreg_pmu_btcmx_0p8>;
+		vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>;
+		vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>;
+		vddrfa1p8-supply = <&vreg_pmu_rfa_1p7>;
+	};
+};
+
+&usb_1_ss0_hsphy {
+	vdd-supply = <&vreg_l3j_0p8>;
+	vdda12-supply = <&vreg_l2j_1p2>;
+
+	phys = <&smb2360_0_eusb2_repeater>;
+
+	status = "okay";
+};
+
+&usb_1_ss0_qmpphy {
+	vdda-phy-supply = <&vreg_l3e_1p2>;
+	vdda-pll-supply = <&vreg_l1j_0p8>;
+
+	status = "okay";
+};
+
+&usb_1_ss0 {
+	status = "okay";
+};
+
+&usb_1_ss0_dwc3 {
+	dr_mode = "host";
+};
+
+&usb_1_ss0_dwc3_hs {
+	remote-endpoint = <&pmic_glink_ss0_hs_in>;
+};
+
+&usb_1_ss0_qmpphy_out {
+	remote-endpoint = <&retimer_ss0_ss_in>;
+};
+
+&usb_1_ss1_hsphy {
+	vdd-supply = <&vreg_l3j_0p8>;
+	vdda12-supply = <&vreg_l2j_1p2>;
+
+	phys = <&smb2360_1_eusb2_repeater>;
+
+	status = "okay";
+};
+
+&usb_1_ss1_qmpphy {
+	vdda-phy-supply = <&vreg_l3e_1p2>;
+	vdda-pll-supply = <&vreg_l2d_0p9>;
+
+	status = "okay";
+};
+
+&usb_1_ss1 {
+	status = "okay";
+};
+
+&usb_1_ss1_dwc3 {
+	dr_mode = "host";
+};
+
+&usb_1_ss1_dwc3_hs {
+	remote-endpoint = <&pmic_glink_ss1_hs_in>;
+};
+
+&usb_1_ss1_qmpphy_out {
+	remote-endpoint = <&retimer_ss1_ss_in>;
+};
+
+&usb_mp {
+	status = "okay";
+};
+
+&usb_mp_dwc3 {
+	phys = <&usb_mp_hsphy0>, <&usb_mp_qmpphy0>;
+	phy-names = "usb2-0", "usb3-0";
+};
+
+&usb_mp_hsphy0 {
+	vdd-supply = <&vreg_l2e_0p8>;
+	vdda12-supply = <&vreg_l3e_1p2>;
+
+	phys = <&eusb3_repeater>;
+
+	status = "okay";
+};
+
+&usb_mp_qmpphy0 {
+	vdda-phy-supply = <&vreg_l3e_1p2>;
+	vdda-pll-supply = <&vreg_l3c_0p8>;
+
+	status = "okay";
+};
diff --git a/dts/upstream/src/arm64/qcom/x1e80100-lenovo-yoga-slim7x.dts b/dts/upstream/src/arm64/qcom/x1e80100-lenovo-yoga-slim7x.dts
index ca5a808f2c7..a3d53f2ba2c 100644
--- a/dts/upstream/src/arm64/qcom/x1e80100-lenovo-yoga-slim7x.dts
+++ b/dts/upstream/src/arm64/qcom/x1e80100-lenovo-yoga-slim7x.dts
@@ -6,6 +6,7 @@
 /dts-v1/;
 
 #include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/gpio-keys.h>
 #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
 
 #include "x1e80100.dtsi"
@@ -23,6 +24,21 @@
 		stdout-path = "serial0:115200n8";
 	};
 
+	gpio-keys {
+		compatible = "gpio-keys";
+
+		pinctrl-0 = <&hall_int_n_default>;
+		pinctrl-names = "default";
+
+		switch-lid {
+			gpios = <&tlmm 92 GPIO_ACTIVE_LOW>;
+			linux,input-type = <EV_SW>;
+			linux,code = <SW_LID>;
+			wakeup-source;
+			wakeup-event-action = <EV_ACT_DEASSERTED>;
+		};
+	};
+
 	pmic-glink {
 		compatible = "qcom,x1e80100-pmic-glink",
 			     "qcom,sm8550-pmic-glink",
@@ -717,11 +733,19 @@
 	status = "okay";
 };
 
+&smb2360_0 {
+	status = "okay";
+};
+
 &smb2360_0_eusb2_repeater {
 	vdd18-supply = <&vreg_l3d_1p8>;
 	vdd3-supply = <&vreg_l2b_3p0>;
 };
 
+&smb2360_1 {
+	status = "okay";
+};
+
 &smb2360_1_eusb2_repeater {
 	vdd18-supply = <&vreg_l3d_1p8>;
 	vdd3-supply = <&vreg_l14b_3p0>;
@@ -811,6 +835,28 @@
 		bias-disable;
 	};
 
+	hall_int_n_default: hall-int-n-state {
+		lid-n-pins {
+			pins = "gpio92";
+			function = "gpio";
+			bias-disable;
+		};
+
+		/*
+		 * Pins 71 and 92 seem to be bridged together (pin 71 and 92 show the same
+		 * events). By default, pin 71 is set as output-high, which blocks any
+		 * event on pin 92. Output-disable on pin 71 is necessary to get events on
+		 * pin 92.
+		 * The purpose of pin 71 is not yet known; lid-pull is a supposition.
+		 */
+		lid-pull-n-pins {
+			pins = "gpio71";
+			function = "gpio";
+			bias-pull-up;
+			output-disable;
+		};
+	};
+
 	kybd_default: kybd-default-state {
 		pins = "gpio67";
 		function = "gpio";
@@ -908,7 +954,7 @@
 };
 
 &usb_1_ss0_qmpphy {
-	vdda-phy-supply = <&vreg_l3e_1p2>;
+	vdda-phy-supply = <&vreg_l2j_1p2>;
 	vdda-pll-supply = <&vreg_l1j_0p8>;
 
 	status = "okay";
@@ -940,7 +986,7 @@
 };
 
 &usb_1_ss1_qmpphy {
-	vdda-phy-supply = <&vreg_l3e_1p2>;
+	vdda-phy-supply = <&vreg_l2j_1p2>;
 	vdda-pll-supply = <&vreg_l2d_0p9>;
 
 	status = "okay";
@@ -972,7 +1018,7 @@
 };
 
 &usb_1_ss2_qmpphy {
-	vdda-phy-supply = <&vreg_l3e_1p2>;
+	vdda-phy-supply = <&vreg_l2j_1p2>;
 	vdda-pll-supply = <&vreg_l2d_0p9>;
 
 	status = "okay";
diff --git a/dts/upstream/src/arm64/qcom/x1e80100-microsoft-romulus.dtsi b/dts/upstream/src/arm64/qcom/x1e80100-microsoft-romulus.dtsi
index 6835fdeef3a..5867953c735 100644
--- a/dts/upstream/src/arm64/qcom/x1e80100-microsoft-romulus.dtsi
+++ b/dts/upstream/src/arm64/qcom/x1e80100-microsoft-romulus.dtsi
@@ -22,6 +22,33 @@
 		i2c7 = &i2c7;
 	};
 
+	wcd938x: audio-codec {
+		compatible = "qcom,wcd9385-codec";
+
+		reset-gpios = <&tlmm 191 GPIO_ACTIVE_LOW>;
+
+		qcom,micbias1-microvolt = <1800000>;
+		qcom,micbias2-microvolt = <1800000>;
+		qcom,micbias3-microvolt = <1800000>;
+		qcom,micbias4-microvolt = <1800000>;
+		qcom,mbhc-buttons-vthreshold-microvolt = <75000 150000 237000 500000 500000 500000 500000 500000>;
+		qcom,mbhc-headset-vthreshold-microvolt = <1700000>;
+		qcom,mbhc-headphone-vthreshold-microvolt = <50000>;
+		qcom,rx-device = <&wcd_rx>;
+		qcom,tx-device = <&wcd_tx>;
+
+
+		vdd-buck-supply = <&vreg_l15b>;
+		vdd-rxtx-supply = <&vreg_l15b>;
+		vdd-io-supply = <&vreg_l15b>;
+		vdd-mic-bias-supply = <&vreg_bob1>;
+
+		pinctrl-0 = <&wcd_default>;
+		pinctrl-names = "default";
+
+		#sound-dai-cells = <1>;
+	};
+
 	backlight: backlight {
 		compatible = "pwm-backlight";
 		pwms = <&pmk8550_pwm 0 5000000>;
@@ -97,7 +124,15 @@
 					reg = <1>;
 
 					pmic_glink_ss0_ss_in: endpoint {
-						remote-endpoint = <&usb_1_ss0_qmpphy_out>;
+						remote-endpoint = <&retimer_ss0_ss_out>;
+					};
+				};
+
+				port@2 {
+					reg = <2>;
+
+					pmic_glink_ss0_con_sbu_in: endpoint {
+						remote-endpoint = <&retimer_ss0_con_sbu_out>;
 					};
 				};
 			};
@@ -126,7 +161,15 @@
 					reg = <1>;
 
 					pmic_glink_ss1_ss_in: endpoint {
-						remote-endpoint = <&usb_1_ss1_qmpphy_out>;
+						remote-endpoint = <&retimer_ss1_ss_out>;
+					};
+				};
+
+				port@2 {
+					reg = <2>;
+
+					pmic_glink_ss1_con_sbu_in: endpoint {
+						remote-endpoint = <&retimer_ss1_con_sbu_out>;
 					};
 				};
 			};
@@ -158,6 +201,109 @@
 		regulator-boot-on;
 	};
 
+	vreg_rtmr0_1p15: regulator-rtmr0-1p15 {
+		compatible = "regulator-fixed";
+
+		regulator-name = "VREG_RTMR0_1P15";
+
+		regulator-min-microvolt = <1150000>;
+		regulator-max-microvolt = <1150000>;
+
+		gpio = <&pmc8380_5_gpios 8 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+
+		pinctrl-0 = <&rtmr0_1p15_reg_en>;
+		pinctrl-names = "default";
+
+		regulator-boot-on;
+	};
+
+	vreg_rtmr0_1p8: regulator-rtmr0-1p8 {
+		compatible = "regulator-fixed";
+
+		regulator-name = "VREG_RTMR0_1P8";
+
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+
+		gpio = <&pm8550ve_9_gpios 8 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+
+		pinctrl-0 = <&rtmr0_1p8_reg_en>;
+		pinctrl-names = "default";
+
+		regulator-boot-on;
+	};
+
+	vreg_rtmr0_3p3: regulator-rtmr0-3p3 {
+		compatible = "regulator-fixed";
+
+		regulator-name = "VREG_RTMR0_3P3";
+
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+
+		gpio = <&pm8550_gpios 11 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+
+		pinctrl-0 = <&rtmr0_3p3_reg_en>;
+		pinctrl-names = "default";
+
+		regulator-boot-on;
+	};
+
+	vreg_rtmr1_1p15: regulator-rtmr1-1p15 {
+		compatible = "regulator-fixed";
+
+		regulator-name = "VREG_RTMR1_1P15";
+
+		regulator-min-microvolt = <1150000>;
+		regulator-max-microvolt = <1150000>;
+
+		gpio = <&tlmm 188 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+
+		pinctrl-0 = <&rtmr1_1p15_reg_en>;
+		pinctrl-names = "default";
+
+		regulator-boot-on;
+	};
+
+	vreg_rtmr1_1p8: regulator-rtmr1-1p8 {
+		compatible = "regulator-fixed";
+
+		regulator-name = "VREG_RTMR1_1P8";
+
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+
+		gpio = <&tlmm 175 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+
+		pinctrl-0 = <&rtmr1_1p8_reg_en>;
+		pinctrl-names = "default";
+
+		regulator-boot-on;
+	};
+
+	vreg_rtmr1_3p3: regulator-rtmr1-3p3 {
+		compatible = "regulator-fixed";
+
+		regulator-name = "VREG_RTMR1_3P3";
+
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+
+		gpio = <&tlmm 186 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+
+		pinctrl-0 = <&rtmr1_3p3_reg_en>;
+		pinctrl-names = "default";
+
+		regulator-boot-on;
+	};
+
+
 	vreg_nvme: regulator-nvme {
 		compatible = "regulator-fixed";
 
@@ -184,6 +330,86 @@
 		regulator-always-on;
 		regulator-boot-on;
 	};
+
+	sound {
+		compatible = "qcom,x1e80100-sndcard";
+		model = "X1E80100-Romulus";
+		audio-routing = "SpkrLeft IN", "WSA WSA_SPK1 OUT",
+				"SpkrRight IN", "WSA WSA_SPK2 OUT",
+				"IN1_HPHL", "HPHL_OUT",
+				"IN2_HPHR", "HPHR_OUT",
+				"AMIC2", "MIC BIAS2",
+				"VA DMIC0", "MIC BIAS3",
+				"VA DMIC1", "MIC BIAS3",
+				"VA DMIC0", "VA MIC BIAS3",
+				"VA DMIC1", "VA MIC BIAS3",
+				"TX SWR_INPUT1", "ADC2_OUTPUT";
+
+		va-dai-link {
+			link-name = "VA Capture";
+
+			cpu {
+				sound-dai = <&q6apmbedai VA_CODEC_DMA_TX_0>;
+			};
+
+			codec {
+				sound-dai = <&lpass_vamacro 0>;
+			};
+
+			platform {
+				sound-dai = <&q6apm>;
+			};
+		};
+
+		wcd-capture-dai-link {
+			link-name = "WCD Capture";
+
+			cpu {
+				sound-dai = <&q6apmbedai TX_CODEC_DMA_TX_3>;
+			};
+
+			codec {
+				sound-dai = <&wcd938x 1>, <&swr2 1>, <&lpass_txmacro 0>;
+			};
+
+			platform {
+				sound-dai = <&q6apm>;
+			};
+		};
+
+		wcd-playback-dai-link {
+			link-name = "WCD Playback";
+
+			cpu {
+				sound-dai = <&q6apmbedai RX_CODEC_DMA_RX_0>;
+			};
+
+			codec {
+				sound-dai = <&wcd938x 0>, <&swr1 0>, <&lpass_rxmacro 0>;
+			};
+
+			platform {
+				sound-dai = <&q6apm>;
+			};
+		};
+
+		wsa-dai-link {
+			link-name = "WSA Playback";
+
+			cpu {
+				sound-dai = <&q6apmbedai WSA_CODEC_DMA_RX_0>;
+			};
+
+			codec {
+				sound-dai = <&left_spkr>, <&right_spkr>,
+					    <&swr0 0>, <&lpass_wsamacro 0>;
+			};
+
+			platform {
+				sound-dai = <&q6apm>;
+			};
+		};
+	};
 };
 
 &apps_rsc {
@@ -558,7 +784,59 @@
 
 	status = "okay";
 
-	/* PS8830 USB retimer @8 */
+	/* Left-side rear port */
+	typec-mux@8 {
+		compatible = "parade,ps8830";
+		reg = <0x8>;
+
+		reset-gpios = <&pm8550_gpios 10 GPIO_ACTIVE_LOW>;
+
+		clocks = <&rpmhcc RPMH_RF_CLK3>;
+		clock-names = "xo";
+
+		vdd-supply = <&vreg_rtmr0_1p15>;
+		vdd33-supply = <&vreg_rtmr0_3p3>;
+		vdd33-cap-supply = <&vreg_rtmr0_3p3>;
+		vddar-supply = <&vreg_rtmr0_1p15>;
+		vddat-supply = <&vreg_rtmr0_1p15>;
+		vddio-supply = <&vreg_rtmr0_1p8>;
+
+		pinctrl-0 = <&rtmr0_default>;
+		pinctrl-names = "default";
+
+		retimer-switch;
+		orientation-switch;
+
+		ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@0 {
+				reg = <0>;
+
+				retimer_ss0_ss_out: endpoint {
+					remote-endpoint = <&pmic_glink_ss0_ss_in>;
+				};
+			};
+
+			port@1 {
+				reg = <1>;
+
+				retimer_ss0_ss_in: endpoint {
+					remote-endpoint = <&usb_1_ss0_qmpphy_out>;
+				};
+			};
+
+			port@2 {
+				reg = <2>;
+
+				retimer_ss0_con_sbu_out: endpoint {
+					remote-endpoint = <&pmic_glink_ss0_con_sbu_in>;
+				};
+			};
+		};
+	};
+
 };
 
 &i2c4 {
@@ -592,7 +870,74 @@
 
 	status = "okay";
 
-	/* PS8830 USB retimer @8 */
+	/* Left-side front port */
+	typec-mux@8 {
+		compatible = "parade,ps8830";
+		reg = <0x8>;
+
+		reset-gpios = <&tlmm 176 GPIO_ACTIVE_LOW>;
+
+		clocks = <&rpmhcc RPMH_RF_CLK4>;
+		clock-names = "xo";
+
+		vdd-supply = <&vreg_rtmr1_1p15>;
+		vdd33-supply = <&vreg_rtmr1_3p3>;
+		vdd33-cap-supply = <&vreg_rtmr1_3p3>;
+		vddar-supply = <&vreg_rtmr1_1p15>;
+		vddat-supply = <&vreg_rtmr1_1p15>;
+		vddio-supply = <&vreg_rtmr1_1p8>;
+
+		retimer-switch;
+		orientation-switch;
+
+		ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@0 {
+				reg = <0>;
+
+				retimer_ss1_ss_out: endpoint {
+					remote-endpoint = <&pmic_glink_ss1_ss_in>;
+				};
+			};
+
+			port@1 {
+				reg = <1>;
+
+				retimer_ss1_ss_in: endpoint {
+					remote-endpoint = <&usb_1_ss1_qmpphy_out>;
+				};
+			};
+
+			port@2 {
+				reg = <2>;
+
+				retimer_ss1_con_sbu_out: endpoint {
+					remote-endpoint = <&pmic_glink_ss1_con_sbu_in>;
+				};
+			};
+		};
+	};
+};
+
+&lpass_tlmm {
+	spkr_01_sd_n_active: spkr-01-sd-n-active-state {
+		pins = "gpio12";
+		function = "gpio";
+		drive-strength = <16>;
+		bias-disable;
+		output-low;
+	};
+};
+
+&lpass_vamacro {
+	qcom,dmic-sample-rate = <4800000>;
+
+	vdd-micb-supply = <&vreg_l1b>;
+
+	pinctrl-0 = <&dmic01_default>;
+	pinctrl-names = "default";
 };
 
 &mdss {
@@ -641,6 +986,25 @@
 	status = "okay";
 };
 
+&pcie3 {
+	perst-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>;
+	wake-gpios = <&tlmm 145 GPIO_ACTIVE_HIGH>;
+
+	pinctrl-0 = <&pcie3_default>;
+	pinctrl-names = "default";
+
+	/* The RTS5261 chip on the other side only does Gen1x1 anyway */
+	max-link-speed = <1>;
+	status = "okay";
+};
+
+&pcie3_phy {
+	vdda-phy-supply = <&vreg_l3c>;
+	vdda-pll-supply = <&vreg_l3e>;
+
+	status = "okay";
+};
+
 &pcie4 {
 	status = "okay";
 };
@@ -671,6 +1035,28 @@
 	status = "okay";
 };
 
+&pm8550_gpios {
+	rtmr0_default: rtmr0-reset-n-active-state {
+		pins = "gpio10";
+		function = "normal";
+		power-source = <1>; /* 1.8V */
+	};
+
+	rtmr0_3p3_reg_en: rtmr0-3p3-reg-en-state {
+		pins = "gpio11";
+		function = "normal";
+		power-source = <1>; /* 1.8V */
+	};
+};
+
+&pm8550ve_9_gpios {
+	rtmr0_1p8_reg_en: rtmr0-1p8-reg-en-state {
+		pins = "gpio8";
+		function = "normal";
+		power-source = <1>; /* 1.8V */
+	};
+};
+
 &pmc8380_3_gpios {
 	edp_bl_en: edp-bl-en-state {
 		pins = "gpio4";
@@ -681,6 +1067,14 @@
 	};
 };
 
+&pmc8380_5_gpios {
+	rtmr0_1p15_reg_en: rtmr0-1p15-reg-en-state {
+		pins = "gpio8";
+		function = "normal";
+		power-source = <1>; /* 1.8V */
+	};
+};
+
 &pmk8550_pwm {
 	status = "okay";
 };
@@ -706,23 +1100,31 @@
 
 &remoteproc_adsp {
 	firmware-name = "qcom/x1e80100/microsoft/Romulus/qcadsp8380.mbn",
-			"qcom/x1e80100/microsoft/Romulus/adsp_dtb.mbn";
+			"qcom/x1e80100/microsoft/Romulus/adsp_dtbs.elf";
 
 	status = "okay";
 };
 
 &remoteproc_cdsp {
 	firmware-name = "qcom/x1e80100/microsoft/Romulus/qccdsp8380.mbn",
-			"qcom/x1e80100/microsoft/Romulus/cdsp_dtb.mbn";
+			"qcom/x1e80100/microsoft/Romulus/cdsp_dtbs.elf";
 
 	status = "okay";
 };
 
+&smb2360_0 {
+	status = "okay";
+};
+
 &smb2360_0_eusb2_repeater {
 	vdd18-supply = <&vreg_l3d>;
 	vdd3-supply = <&vreg_l2b>;
 };
 
+&smb2360_1 {
+	status = "okay";
+};
+
 &smb2360_1_eusb2_repeater {
 	vdd18-supply = <&vreg_l3d>;
 	vdd3-supply = <&vreg_l14b>;
@@ -737,6 +1139,59 @@
 	vdd3-supply = <&vreg_l8b>;
 };
 
+&swr0 {
+	pinctrl-0 = <&wsa_swr_active>, <&spkr_01_sd_n_active>;
+	pinctrl-names = "default";
+
+	status = "okay";
+
+	/* WSA8845, Left speaker */
+	left_spkr: speaker@0,0 {
+		compatible = "sdw20217020400";
+		reg = <0 0>;
+		reset-gpios = <&lpass_tlmm 12 GPIO_ACTIVE_LOW>;
+		#sound-dai-cells = <0>;
+		sound-name-prefix = "SpkrLeft";
+		vdd-1p8-supply = <&vreg_l15b>;
+		vdd-io-supply = <&vreg_l12b>;
+		qcom,port-mapping = <1 2 3 7 10 13>;
+	};
+
+	/* WSA8845, Right speaker */
+	right_spkr: speaker@0,1 {
+		compatible = "sdw20217020400";
+		reg = <0 1>;
+		reset-gpios = <&lpass_tlmm 12 GPIO_ACTIVE_LOW>;
+		#sound-dai-cells = <0>;
+		sound-name-prefix = "SpkrRight";
+		vdd-1p8-supply = <&vreg_l15b>;
+		vdd-io-supply = <&vreg_l12b>;
+		qcom,port-mapping = <4 5 6 7 11 13>;
+	};
+};
+
+&swr1 {
+	status = "okay";
+
+	/* WCD9385 RX */
+	wcd_rx: codec@0,4 {
+		compatible = "sdw20217010d00";
+		reg = <0 4>;
+		qcom,rx-port-mapping = <1 2 3 4 5>;
+	};
+};
+
+&swr2 {
+	status = "okay";
+
+	/* WCD9385 TX */
+	wcd_tx: codec@0,3 {
+		compatible = "sdw20217010d00";
+		reg = <0 3>;
+		qcom,tx-port-mapping = <2 2 3 4>;
+	};
+};
+
 &tlmm {
 	gpio-reserved-ranges = <44 4>, /* SPI (TPM) */
 			       <238 1>; /* UFS Reset */
@@ -767,6 +1222,29 @@
 		bias-disable;
 	};
 
+	pcie3_default: pcie3-default-state {
+		perst-n-pins {
+			pins = "gpio143";
+			function = "gpio";
+			drive-strength = <2>;
+			bias-disable;
+		};
+
+		clkreq-n-pins {
+			pins = "gpio144";
+			function = "pcie3_clk";
+			drive-strength = <2>;
+			bias-pull-up;
+		};
+
+		wake-n-pins {
+			pins = "gpio145";
+			function = "gpio";
+			drive-strength = <2>;
+			bias-pull-up;
+		};
+	};
+
 	pcie6a_default: pcie6a-default-state {
 		perst-n-pins {
 			pins = "gpio152";
@@ -790,6 +1268,35 @@
 		};
 	};
 
+	rtmr1_1p8_reg_en: rtmr1-1p8-reg-en-state {
+		pins = "gpio175";
+		function = "gpio";
+		drive-strength = <2>;
+		bias-disable;
+	};
+
+	rtmr1_3p3_reg_en: rtmr1-3p3-reg-en-state {
+		pins = "gpio186";
+		function = "gpio";
+		drive-strength = <2>;
+		bias-disable;
+	};
+
+	rtmr1_1p15_reg_en: rtmr1-1p15-reg-en-state {
+		pins = "gpio188";
+		function = "gpio";
+		drive-strength = <2>;
+		bias-disable;
+	};
+
+	wcd_default: wcd-reset-n-active-state {
+		pins = "gpio191";
+		function = "gpio";
+		drive-strength = <16>;
+		bias-disable;
+		output-low;
+	};
+
 	cam_indicator_en: cam-indicator-en-state {
 		pins = "gpio225";
 		function = "gpio";
@@ -823,7 +1330,7 @@
 };
 
 &usb_1_ss0_qmpphy {
-	vdda-phy-supply = <&vreg_l3e>;
+	vdda-phy-supply = <&vreg_l2j>;
 	vdda-pll-supply = <&vreg_l1j>;
 
 	status = "okay";
@@ -842,7 +1349,7 @@
 };
 
 &usb_1_ss0_qmpphy_out {
-	remote-endpoint = <&pmic_glink_ss0_ss_in>;
+	remote-endpoint = <&retimer_ss0_ss_in>;
 };
 
 &usb_1_ss1_hsphy {
@@ -855,7 +1362,7 @@
 };
 
 &usb_1_ss1_qmpphy {
-	vdda-phy-supply = <&vreg_l3e>;
+	vdda-phy-supply = <&vreg_l2j>;
 	vdda-pll-supply = <&vreg_l2d>;
 
 	status = "okay";
@@ -874,7 +1381,7 @@
 };
 
 &usb_1_ss1_qmpphy_out {
-	remote-endpoint = <&pmic_glink_ss1_ss_in>;
+	remote-endpoint = <&retimer_ss1_ss_in>;
 };
 
 /* MP0 goes to the Surface Connector, MP1 goes to the USB-A port */
diff --git a/dts/upstream/src/arm64/qcom/x1e80100-pmics.dtsi b/dts/upstream/src/arm64/qcom/x1e80100-pmics.dtsi
index 5b54ee79f04..d7a2a2b8fc6 100644
--- a/dts/upstream/src/arm64/qcom/x1e80100-pmics.dtsi
+++ b/dts/upstream/src/arm64/qcom/x1e80100-pmics.dtsi
@@ -491,6 +491,8 @@
 		#address-cells = <1>;
 		#size-cells = <0>;
 
+		status = "disabled";
+
 		smb2360_0_eusb2_repeater: phy@fd00 {
 			compatible = "qcom,smb2360-eusb2-repeater";
 			reg = <0xfd00>;
@@ -504,6 +506,8 @@
 		#address-cells = <1>;
 		#size-cells = <0>;
 
+		status = "disabled";
+
 		smb2360_1_eusb2_repeater: phy@fd00 {
 			compatible = "qcom,smb2360-eusb2-repeater";
 			reg = <0xfd00>;
diff --git a/dts/upstream/src/arm64/qcom/x1e80100-qcp.dts b/dts/upstream/src/arm64/qcom/x1e80100-qcp.dts
index 5ef030c60ab..ec594628304 100644
--- a/dts/upstream/src/arm64/qcom/x1e80100-qcp.dts
+++ b/dts/upstream/src/arm64/qcom/x1e80100-qcp.dts
@@ -84,6 +84,14 @@
 						remote-endpoint = <&usb_1_ss0_qmpphy_out>;
 					};
 				};
+
+				port@2 {
+					reg = <2>;
+
+					pmic_glink_ss0_sbu: endpoint {
+						remote-endpoint = <&usb_1_ss0_sbu_mux>;
+					};
+				};
 			};
 		};
 
@@ -112,6 +120,14 @@
 						remote-endpoint = <&usb_1_ss1_qmpphy_out>;
 					};
 				};
+
+				port@2 {
+					reg = <2>;
+
+					pmic_glink_ss1_sbu: endpoint {
+						remote-endpoint = <&usb_1_ss1_sbu_mux>;
+					};
+				};
 			};
 		};
 
@@ -140,6 +156,14 @@
 						remote-endpoint = <&usb_1_ss2_qmpphy_out>;
 					};
 				};
+
+				port@2 {
+					reg = <2>;
+
+					pmic_glink_ss2_sbu: endpoint {
+						remote-endpoint = <&usb_1_ss2_sbu_mux>;
+					};
+				};
 			};
 		};
 	};
@@ -256,6 +280,63 @@
 
 		regulator-boot-on;
 	};
+
+	usb-1-ss0-sbu-mux {
+		compatible = "onnn,fsusb42", "gpio-sbu-mux";
+
+		enable-gpios = <&tlmm 168 GPIO_ACTIVE_LOW>;
+		select-gpios = <&tlmm 167 GPIO_ACTIVE_HIGH>;
+
+		pinctrl-0 = <&usb_1_ss0_sbu_default>;
+		pinctrl-names = "default";
+
+		mode-switch;
+		orientation-switch;
+
+		port {
+			usb_1_ss0_sbu_mux: endpoint {
+				remote-endpoint = <&pmic_glink_ss0_sbu>;
+			};
+		};
+	};
+
+	usb-1-ss1-sbu-mux {
+		compatible = "onnn,fsusb42", "gpio-sbu-mux";
+
+		enable-gpios = <&tlmm 179 GPIO_ACTIVE_LOW>;
+		select-gpios = <&tlmm 178 GPIO_ACTIVE_HIGH>;
+
+		pinctrl-0 = <&usb_1_ss1_sbu_default>;
+		pinctrl-names = "default";
+
+		mode-switch;
+		orientation-switch;
+
+		port {
+			usb_1_ss1_sbu_mux: endpoint {
+				remote-endpoint = <&pmic_glink_ss1_sbu>;
+			};
+		};
+	};
+
+	usb-1-ss2-sbu-mux {
+		compatible = "onnn,fsusb42", "gpio-sbu-mux";
+
+		enable-gpios = <&tlmm 171 GPIO_ACTIVE_LOW>;
+		select-gpios = <&tlmm 170 GPIO_ACTIVE_HIGH>;
+
+		pinctrl-0 = <&usb_1_ss2_sbu_default>;
+		pinctrl-names = "default";
+
+		mode-switch;
+		orientation-switch;
+
+		port {
+			usb_1_ss2_sbu_mux: endpoint {
+				remote-endpoint = <&pmic_glink_ss2_sbu>;
+			};
+		};
+	};
 };
 
 &apps_rsc {
@@ -616,6 +697,40 @@
 	};
 };
 
+&i2c5 {
+	clock-frequency = <400000>;
+
+	status = "okay";
+
+	eusb3_repeater: redriver@47 {
+		compatible = "nxp,ptn3222";
+		reg = <0x47>;
+		#phy-cells = <0>;
+
+		vdd3v3-supply = <&vreg_l13b_3p0>;
+		vdd1v8-supply = <&vreg_l4b_1p8>;
+
+		reset-gpios = <&tlmm 6 GPIO_ACTIVE_LOW>;
+
+		pinctrl-0 = <&eusb3_reset_n>;
+		pinctrl-names = "default";
+	};
+
+	eusb6_repeater: redriver@4f {
+		compatible = "nxp,ptn3222";
+		reg = <0x4f>;
+		#phy-cells = <0>;
+
+		vdd3v3-supply = <&vreg_l13b_3p0>;
+		vdd1v8-supply = <&vreg_l4b_1p8>;
+
+		reset-gpios = <&tlmm 184 GPIO_ACTIVE_LOW>;
+
+		pinctrl-0 = <&eusb6_reset_n>;
+		pinctrl-names = "default";
+	};
+};
+
 &lpass_tlmm {
 	spkr_01_sd_n_active: spkr-01-sd-n-active-state {
 		pins = "gpio12";
@@ -630,6 +745,30 @@
 	status = "okay";
 };
 
+&mdss_dp0 {
+	status = "okay";
+};
+
+&mdss_dp0_out {
+	data-lanes = <0 1>;
+};
+
+&mdss_dp1 {
+	status = "okay";
+};
+
+&mdss_dp1_out {
+	data-lanes = <0 1>;
+};
+
+&mdss_dp2 {
+	status = "okay";
+};
+
+&mdss_dp2_out {
+	data-lanes = <0 1>;
+};
+
 &mdss_dp3 {
 	compatible = "qcom,x1e80100-dp";
 	/delete-property/ #sound-dai-cells;
@@ -731,11 +870,32 @@
 	status = "okay";
 };
 
+&smb2360_0 {
+	status = "okay";
+};
+
+&sdhc_2 {
+	cd-gpios = <&tlmm 71 GPIO_ACTIVE_LOW>;
+	pinctrl-0 = <&sdc2_default &sdc2_card_det_n>;
+	pinctrl-1 = <&sdc2_sleep &sdc2_card_det_n>;
+	pinctrl-names = "default", "sleep";
+	vmmc-supply = <&vreg_l9b_2p9>;
+	vqmmc-supply = <&vreg_l6b_1p8>;
+	bus-width = <4>;
+	no-sdio;
+	no-mmc;
+	status = "okay";
+};
+
 &smb2360_0_eusb2_repeater {
 	vdd18-supply = <&vreg_l3d_1p8>;
 	vdd3-supply = <&vreg_l2b_3p0>;
 };
 
+&smb2360_1 {
+	status = "okay";
+};
+
 &smb2360_1_eusb2_repeater {
 	vdd18-supply = <&vreg_l3d_1p8>;
 	vdd3-supply = <&vreg_l14b_3p0>;
@@ -819,6 +979,22 @@
 		bias-disable;
 	};
 
+	eusb3_reset_n: eusb3-reset-n-state {
+		pins = "gpio6";
+		function = "gpio";
+		drive-strength = <2>;
+		bias-disable;
+		output-low;
+	};
+
+	eusb6_reset_n: eusb6-reset-n-state {
+		pins = "gpio184";
+		function = "gpio";
+		drive-strength = <2>;
+		bias-disable;
+		output-low;
+	};
+
 	nvme_reg_en: nvme-reg-en-state {
 		pins = "gpio18";
 		function = "gpio";
@@ -872,6 +1048,86 @@
 		};
 	};
 
+	sdc2_card_det_n: sdc2-card-det-state {
+		pins = "gpio71";
+		function = "gpio";
+		drive-strength = <2>;
+		bias-pull-up;
+	};
+
+	usb_1_ss0_sbu_default: usb-1-ss0-sbu-state {
+		mode-pins {
+			pins = "gpio166";
+			function = "gpio";
+			bias-disable;
+			drive-strength = <2>;
+			output-high;
+		};
+
+		oe-n-pins {
+			pins = "gpio168";
+			function = "gpio";
+			bias-disable;
+			drive-strength = <2>;
+		};
+
+		sel-pins {
+			pins = "gpio167";
+			function = "gpio";
+			bias-disable;
+			drive-strength = <2>;
+		};
+
+	};
+
+	usb_1_ss1_sbu_default: usb-1-ss1-sbu-state {
+		mode-pins {
+			pins = "gpio177";
+			function = "gpio";
+			bias-disable;
+			drive-strength = <2>;
+			output-high;
+		};
+
+		oe-n-pins {
+			pins = "gpio179";
+			function = "gpio";
+			bias-disable;
+			drive-strength = <2>;
+		};
+
+		sel-pins {
+			pins = "gpio178";
+			function = "gpio";
+			bias-disable;
+			drive-strength = <2>;
+		};
+	};
+
+	usb_1_ss2_sbu_default: usb-1-ss2-sbu-state {
+		mode-pins {
+			pins = "gpio169";
+			function = "gpio";
+			bias-disable;
+			drive-strength = <2>;
+			output-high;
+		};
+
+		oe-n-pins {
+			pins = "gpio171";
+			function = "gpio";
+			bias-disable;
+			drive-strength = <2>;
+		};
+
+		sel-pins {
+			pins = "gpio170";
+			function = "gpio";
+			bias-disable;
+			drive-strength = <2>;
+		};
+	};
+
 	wcd_default: wcd-reset-n-active-state {
 		pins = "gpio191";
 		function = "gpio";
@@ -896,7 +1152,7 @@
 };
 
 &usb_1_ss0_qmpphy {
-	vdda-phy-supply = <&vreg_l3e_1p2>;
+	vdda-phy-supply = <&vreg_l2j_1p2>;
 	vdda-pll-supply = <&vreg_l1j_0p8>;
 
 	status = "okay";
@@ -928,7 +1184,7 @@
 };
 
 &usb_1_ss1_qmpphy {
-	vdda-phy-supply = <&vreg_l3e_1p2>;
+	vdda-phy-supply = <&vreg_l2j_1p2>;
 	vdda-pll-supply = <&vreg_l2d_0p9>;
 
 	status = "okay";
@@ -960,7 +1216,7 @@
 };
 
 &usb_1_ss2_qmpphy {
-	vdda-phy-supply = <&vreg_l3e_1p2>;
+	vdda-phy-supply = <&vreg_l2j_1p2>;
 	vdda-pll-supply = <&vreg_l2d_0p9>;
 
 	status = "okay";
@@ -981,3 +1237,39 @@
 &usb_1_ss2_qmpphy_out {
 	remote-endpoint = <&pmic_glink_ss2_ss_in>;
 };
+
+&usb_mp {
+	status = "okay";
+};
+
+&usb_mp_hsphy0 {
+	vdd-supply = <&vreg_l2e_0p8>;
+	vdda12-supply = <&vreg_l3e_1p2>;
+
+	phys = <&eusb6_repeater>;
+
+	status = "okay";
+};
+
+&usb_mp_hsphy1 {
+	vdd-supply = <&vreg_l2e_0p8>;
+	vdda12-supply = <&vreg_l3e_1p2>;
+
+	phys = <&eusb3_repeater>;
+
+	status = "okay";
+};
+
+&usb_mp_qmpphy0 {
+	vdda-phy-supply = <&vreg_l3e_1p2>;
+	vdda-pll-supply = <&vreg_l3c_0p8>;
+
+	status = "okay";
+};
+
+&usb_mp_qmpphy1 {
+	vdda-phy-supply = <&vreg_l3e_1p2>;
+	vdda-pll-supply = <&vreg_l3c_0p8>;
+
+	status = "okay";
+};
diff --git a/dts/upstream/src/arm64/qcom/x1e80100.dtsi b/dts/upstream/src/arm64/qcom/x1e80100.dtsi
index 7e4f46ad8ed..4936fa5b98f 100644
--- a/dts/upstream/src/arm64/qcom/x1e80100.dtsi
+++ b/dts/upstream/src/arm64/qcom/x1e80100.dtsi
@@ -38,7 +38,7 @@
 
 		sleep_clk: sleep-clk {
 			compatible = "fixed-clock";
-			clock-frequency = <32000>;
+			clock-frequency = <32764>;
 			#clock-cells = <0>;
 		};
 
@@ -303,6 +303,18 @@
 		};
 	};
 
+	dummy-sink {
+		compatible = "arm,coresight-dummy-sink";
+
+		in-ports {
+			port {
+				eud_in: endpoint {
+					remote-endpoint = <&swao_rep_out1>;
+				};
+			};
+		};
+	};
+
 	firmware {
 		scm: scm {
 			compatible = "qcom,scm-x1e80100", "qcom,scm";
@@ -677,6 +689,34 @@
 		};
 	};
 
+	qup_opp_table_100mhz: opp-table-qup100mhz {
+		compatible = "operating-points-v2";
+
+		opp-75000000 {
+			opp-hz = /bits/ 64 <75000000>;
+			required-opps = <&rpmhpd_opp_low_svs>;
+		};
+
+		opp-100000000 {
+			opp-hz = /bits/ 64 <100000000>;
+			required-opps = <&rpmhpd_opp_svs>;
+		};
+	};
+
+	qup_opp_table_120mhz: opp-table-qup120mhz {
+		compatible = "operating-points-v2";
+
+		opp-75000000 {
+			opp-hz = /bits/ 64 <75000000>;
+			required-opps = <&rpmhpd_opp_low_svs>;
+		};
+
+		opp-120000000 {
+			opp-hz = /bits/ 64 <120000000>;
+			required-opps = <&rpmhpd_opp_svs>;
+		};
+	};
+
 	smp2p-adsp {
 		compatible = "qcom,smp2p";
 
@@ -743,7 +783,7 @@
 
 			clocks = <&bi_tcxo_div2>,
 				 <&sleep_clk>,
-				 <0>,
+				 <&pcie3_phy>,
 				 <&pcie4_phy>,
 				 <&pcie5_phy>,
 				 <&pcie6a_phy>,
@@ -831,6 +871,9 @@
 						     "qup-config",
 						     "qup-memory";
 
+				power-domains = <&rpmhpd RPMHPD_CX>;
+				required-opps = <&rpmhpd_opp_low_svs>;
+
 				dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>,
 				       <&gpi_dma2 1 0 QCOM_GPI_I2C>;
 				dma-names = "tx",
@@ -864,6 +907,9 @@
 						     "qup-config",
 						     "qup-memory";
 
+				power-domains = <&rpmhpd RPMHPD_CX>;
+				operating-points-v2 = <&qup_opp_table_120mhz>;
+
 				dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>,
 				       <&gpi_dma2 1 0 QCOM_GPI_SPI>;
 				dma-names = "tx",
@@ -897,6 +943,9 @@
 						     "qup-config",
 						     "qup-memory";
 
+				power-domains = <&rpmhpd RPMHPD_CX>;
+				required-opps = <&rpmhpd_opp_low_svs>;
+
 				dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>,
 				       <&gpi_dma2 1 1 QCOM_GPI_I2C>;
 				dma-names = "tx",
@@ -930,6 +979,9 @@
 						     "qup-config",
 						     "qup-memory";
 
+				power-domains = <&rpmhpd RPMHPD_CX>;
+				operating-points-v2 = <&qup_opp_table_120mhz>;
+
 				dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>,
 				       <&gpi_dma2 1 1 QCOM_GPI_SPI>;
 				dma-names = "tx",
@@ -963,6 +1015,9 @@
 						     "qup-config",
 						     "qup-memory";
 
+				power-domains = <&rpmhpd RPMHPD_CX>;
+				required-opps = <&rpmhpd_opp_low_svs>;
+
 				dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>,
 				       <&gpi_dma2 1 2 QCOM_GPI_I2C>;
 				dma-names = "tx",
@@ -996,6 +1051,9 @@
 						     "qup-config",
 						     "qup-memory";
 
+				power-domains = <&rpmhpd RPMHPD_CX>;
+				operating-points-v2 = <&qup_opp_table_100mhz>;
+
 				dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>,
 				       <&gpi_dma2 1 2 QCOM_GPI_SPI>;
 				dma-names = "tx",
@@ -1029,6 +1087,9 @@
 						     "qup-config",
 						     "qup-memory";
 
+				power-domains = <&rpmhpd RPMHPD_CX>;
+				required-opps = <&rpmhpd_opp_low_svs>;
+
 				dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>,
 				       <&gpi_dma2 1 3 QCOM_GPI_I2C>;
 				dma-names = "tx",
@@ -1062,6 +1123,9 @@
 						     "qup-config",
 						     "qup-memory";
 
+				power-domains = <&rpmhpd RPMHPD_CX>;
+				operating-points-v2 = <&qup_opp_table_100mhz>;
+
 				dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>,
 				       <&gpi_dma2 1 3 QCOM_GPI_SPI>;
 				dma-names = "tx",
@@ -1095,6 +1159,9 @@
 						     "qup-config",
 						     "qup-memory";
 
+				power-domains = <&rpmhpd RPMHPD_CX>;
+				required-opps = <&rpmhpd_opp_low_svs>;
+
 				dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>,
 				       <&gpi_dma2 1 4 QCOM_GPI_I2C>;
 				dma-names = "tx",
@@ -1128,6 +1195,9 @@
 						     "qup-config",
 						     "qup-memory";
 
+				power-domains = <&rpmhpd RPMHPD_CX>;
+				operating-points-v2 = <&qup_opp_table_100mhz>;
+
 				dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>,
 				       <&gpi_dma2 1 4 QCOM_GPI_SPI>;
 				dma-names = "tx",
@@ -1161,6 +1231,9 @@
 						     "qup-config",
 						     "qup-memory";
 
+				power-domains = <&rpmhpd RPMHPD_CX>;
+				required-opps = <&rpmhpd_opp_low_svs>;
+
 				dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>,
 				       <&gpi_dma2 1 5 QCOM_GPI_I2C>;
 				dma-names = "tx",
@@ -1194,6 +1267,9 @@
 						     "qup-config",
 						     "qup-memory";
 
+				power-domains = <&rpmhpd RPMHPD_CX>;
+				operating-points-v2 = <&qup_opp_table_100mhz>;
+
 				dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>,
 				       <&gpi_dma2 1 5 QCOM_GPI_SPI>;
 				dma-names = "tx",
@@ -1224,6 +1300,9 @@
 				interconnect-names = "qup-core",
 						     "qup-config";
 
+				power-domains = <&rpmhpd RPMHPD_CX>;
+				operating-points-v2 = <&qup_opp_table_100mhz>;
+
 				pinctrl-0 = <&qup_uart21_default>;
 				pinctrl-names = "default";
 
@@ -1249,6 +1328,9 @@
 						     "qup-config",
 						     "qup-memory";
 
+				power-domains = <&rpmhpd RPMHPD_CX>;
+				required-opps = <&rpmhpd_opp_low_svs>;
+
 				dmas = <&gpi_dma2 0 6 QCOM_GPI_I2C>,
 				       <&gpi_dma2 1 6 QCOM_GPI_I2C>;
 				dma-names = "tx",
@@ -1282,6 +1364,9 @@
 						     "qup-config",
 						     "qup-memory";
 
+				power-domains = <&rpmhpd RPMHPD_CX>;
+				operating-points-v2 = <&qup_opp_table_100mhz>;
+
 				dmas = <&gpi_dma2 0 6 QCOM_GPI_SPI>,
 				       <&gpi_dma2 1 6 QCOM_GPI_SPI>;
 				dma-names = "tx",
@@ -1315,6 +1400,9 @@
 						     "qup-config",
 						     "qup-memory";
 
+				power-domains = <&rpmhpd RPMHPD_CX>;
+				required-opps = <&rpmhpd_opp_low_svs>;
+
 				dmas = <&gpi_dma2 0 7 QCOM_GPI_I2C>,
 				       <&gpi_dma2 1 7 QCOM_GPI_I2C>;
 				dma-names = "tx",
@@ -1348,6 +1436,9 @@
 						     "qup-config",
 						     "qup-memory";
 
+				power-domains = <&rpmhpd RPMHPD_CX>;
+				operating-points-v2 = <&qup_opp_table_100mhz>;
+
 				dmas = <&gpi_dma2 0 7 QCOM_GPI_SPI>,
 				       <&gpi_dma2 1 7 QCOM_GPI_SPI>;
 				dma-names = "tx",
@@ -1425,6 +1516,9 @@
 						     "qup-config",
 						     "qup-memory";
 
+				power-domains = <&rpmhpd RPMHPD_CX>;
+				required-opps = <&rpmhpd_opp_low_svs>;
+
 				dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
 				       <&gpi_dma1 1 0 QCOM_GPI_I2C>;
 				dma-names = "tx",
@@ -1458,6 +1552,9 @@
 						     "qup-config",
 						     "qup-memory";
 
+				power-domains = <&rpmhpd RPMHPD_CX>;
+				operating-points-v2 = <&qup_opp_table_120mhz>;
+
 				dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>,
 				       <&gpi_dma1 1 0 QCOM_GPI_SPI>;
 				dma-names = "tx",
@@ -1491,6 +1588,9 @@
 						     "qup-config",
 						     "qup-memory";
 
+				power-domains = <&rpmhpd RPMHPD_CX>;
+				required-opps = <&rpmhpd_opp_low_svs>;
+
 				dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
 				       <&gpi_dma1 1 1 QCOM_GPI_I2C>;
 				dma-names = "tx",
@@ -1524,6 +1624,9 @@
 						     "qup-config",
 						     "qup-memory";
 
+				power-domains = <&rpmhpd RPMHPD_CX>;
+				operating-points-v2 = <&qup_opp_table_120mhz>;
+
 				dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
 				       <&gpi_dma1 1 1 QCOM_GPI_SPI>;
 				dma-names = "tx",
@@ -1557,6 +1660,9 @@
 						     "qup-config",
 						     "qup-memory";
 
+				power-domains = <&rpmhpd RPMHPD_CX>;
+				required-opps = <&rpmhpd_opp_low_svs>;
+
 				dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
 				       <&gpi_dma1 1 2 QCOM_GPI_I2C>;
 				dma-names = "tx",
@@ -1590,6 +1696,9 @@
 						     "qup-config",
 						     "qup-memory";
 
+				power-domains = <&rpmhpd RPMHPD_CX>;
+				operating-points-v2 = <&qup_opp_table_100mhz>;
+
 				dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>,
 				       <&gpi_dma1 1 2 QCOM_GPI_SPI>;
 				dma-names = "tx",
@@ -1623,6 +1732,9 @@
 						     "qup-config",
 						     "qup-memory";
 
+				power-domains = <&rpmhpd RPMHPD_CX>;
+				required-opps = <&rpmhpd_opp_low_svs>;
+
 				dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
 				       <&gpi_dma1 1 3 QCOM_GPI_I2C>;
 				dma-names = "tx",
@@ -1656,6 +1768,9 @@
 						     "qup-config",
 						     "qup-memory";
 
+				power-domains = <&rpmhpd RPMHPD_CX>;
+				operating-points-v2 = <&qup_opp_table_100mhz>;
+
 				dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>,
 				       <&gpi_dma1 1 3 QCOM_GPI_SPI>;
 				dma-names = "tx",
@@ -1689,6 +1804,9 @@
 						     "qup-config",
 						     "qup-memory";
 
+				power-domains = <&rpmhpd RPMHPD_CX>;
+				required-opps = <&rpmhpd_opp_low_svs>;
+
 				dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
 				       <&gpi_dma1 1 4 QCOM_GPI_I2C>;
 				dma-names = "tx",
@@ -1722,6 +1840,9 @@
 						     "qup-config",
 						     "qup-memory";
 
+				power-domains = <&rpmhpd RPMHPD_CX>;
+				operating-points-v2 = <&qup_opp_table_100mhz>;
+
 				dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>,
 				       <&gpi_dma1 1 4 QCOM_GPI_SPI>;
 				dma-names = "tx",
@@ -1755,6 +1876,9 @@
 						     "qup-config",
 						     "qup-memory";
 
+				power-domains = <&rpmhpd RPMHPD_CX>;
+				required-opps = <&rpmhpd_opp_low_svs>;
+
 				dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>,
 				       <&gpi_dma1 1 5 QCOM_GPI_I2C>;
 				dma-names = "tx",
@@ -1788,6 +1912,9 @@
 						     "qup-config",
 						     "qup-memory";
 
+				power-domains = <&rpmhpd RPMHPD_CX>;
+				operating-points-v2 = <&qup_opp_table_100mhz>;
+
 				dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>,
 				       <&gpi_dma1 1 5 QCOM_GPI_SPI>;
 				dma-names = "tx",
@@ -1821,6 +1948,9 @@
 						     "qup-config",
 						     "qup-memory";
 
+				power-domains = <&rpmhpd RPMHPD_CX>;
+				required-opps = <&rpmhpd_opp_low_svs>;
+
 				dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>,
 				       <&gpi_dma1 1 6 QCOM_GPI_I2C>;
 				dma-names = "tx",
@@ -1854,6 +1984,9 @@
 						     "qup-config",
 						     "qup-memory";
 
+				power-domains = <&rpmhpd RPMHPD_CX>;
+				operating-points-v2 = <&qup_opp_table_100mhz>;
+
 				dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>,
 				       <&gpi_dma1 1 6 QCOM_GPI_SPI>;
 				dma-names = "tx",
@@ -1868,6 +2001,31 @@
 				status = "disabled";
 			};
 
+			uart14: serial@a98000 {
+				compatible = "qcom,geni-uart";
+				reg = <0 0x00a98000 0 0x4000>;
+
+				interrupts = <GIC_SPI 806 IRQ_TYPE_LEVEL_HIGH>;
+
+				clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
+				clock-names = "se";
+
+				interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
+						 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
+						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+						 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>;
+				interconnect-names = "qup-core",
+						     "qup-config";
+
+				power-domains = <&rpmhpd RPMHPD_CX>;
+				operating-points-v2 = <&qup_opp_table_100mhz>;
+
+				pinctrl-0 = <&qup_uart14_default>;
+				pinctrl-names = "default";
+
+				status = "disabled";
+			};
+
 			i2c15: i2c@a9c000 {
 				compatible = "qcom,geni-i2c";
 				reg = <0 0x00a9c000 0 0x4000>;
@@ -1887,6 +2045,9 @@
 						     "qup-config",
 						     "qup-memory";
 
+				power-domains = <&rpmhpd RPMHPD_CX>;
+				required-opps = <&rpmhpd_opp_low_svs>;
+
 				dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C>,
 				       <&gpi_dma1 1 7 QCOM_GPI_I2C>;
 				dma-names = "tx",
@@ -1920,6 +2081,9 @@
 						     "qup-config",
 						     "qup-memory";
 
+				power-domains = <&rpmhpd RPMHPD_CX>;
+				operating-points-v2 = <&qup_opp_table_100mhz>;
+
 				dmas = <&gpi_dma1 0 7 QCOM_GPI_SPI>,
 				       <&gpi_dma1 1 7 QCOM_GPI_SPI>;
 				dma-names = "tx",
@@ -1996,6 +2160,9 @@
 						     "qup-config",
 						     "qup-memory";
 
+				power-domains = <&rpmhpd RPMHPD_CX>;
+				required-opps = <&rpmhpd_opp_low_svs>;
+
 				dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
 				       <&gpi_dma0 1 0 QCOM_GPI_I2C>;
 				dma-names = "tx",
@@ -2029,6 +2196,9 @@
 						     "qup-config",
 						     "qup-memory";
 
+				power-domains = <&rpmhpd RPMHPD_CX>;
+				operating-points-v2 = <&qup_opp_table_120mhz>;
+
 				dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
 				       <&gpi_dma0 1 0 QCOM_GPI_SPI>;
 				dma-names = "tx",
@@ -2062,6 +2232,9 @@
 						     "qup-config",
 						     "qup-memory";
 
+				power-domains = <&rpmhpd RPMHPD_CX>;
+				required-opps = <&rpmhpd_opp_low_svs>;
+
 				dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
 				       <&gpi_dma0 1 1 QCOM_GPI_I2C>;
 				dma-names = "tx",
@@ -2095,6 +2268,9 @@
 						     "qup-config",
 						     "qup-memory";
 
+				power-domains = <&rpmhpd RPMHPD_CX>;
+				operating-points-v2 = <&qup_opp_table_120mhz>;
+
 				dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
 				       <&gpi_dma0 1 1 QCOM_GPI_SPI>;
 				dma-names = "tx",
@@ -2128,6 +2304,9 @@
 						     "qup-config",
 						     "qup-memory";
 
+				power-domains = <&rpmhpd RPMHPD_CX>;
+				required-opps = <&rpmhpd_opp_low_svs>;
+
 				dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
 				       <&gpi_dma0 1 2 QCOM_GPI_I2C>;
 				dma-names = "tx",
@@ -2158,6 +2337,9 @@
 				interconnect-names = "qup-core",
 						     "qup-config";
 
+				power-domains = <&rpmhpd RPMHPD_CX>;
+				operating-points-v2 = <&qup_opp_table_100mhz>;
+
 				pinctrl-0 = <&qup_uart2_default>;
 				pinctrl-names = "default";
 
@@ -2183,6 +2365,9 @@
 						     "qup-config",
 						     "qup-memory";
 
+				power-domains = <&rpmhpd RPMHPD_CX>;
+				operating-points-v2 = <&qup_opp_table_100mhz>;
+
 				dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>,
 				       <&gpi_dma0 1 2 QCOM_GPI_SPI>;
 				dma-names = "tx",
@@ -2216,6 +2401,9 @@
 						     "qup-config",
 						     "qup-memory";
 
+				power-domains = <&rpmhpd RPMHPD_CX>;
+				required-opps = <&rpmhpd_opp_low_svs>;
+
 				dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>,
 				       <&gpi_dma0 1 3 QCOM_GPI_I2C>;
 				dma-names = "tx",
@@ -2249,6 +2437,9 @@
 						     "qup-config",
 						     "qup-memory";
 
+				power-domains = <&rpmhpd RPMHPD_CX>;
+				operating-points-v2 = <&qup_opp_table_100mhz>;
+
 				dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>,
 				       <&gpi_dma0 1 3 QCOM_GPI_SPI>;
 				dma-names = "tx",
@@ -2282,6 +2473,9 @@
 						     "qup-config",
 						     "qup-memory";
 
+				power-domains = <&rpmhpd RPMHPD_CX>;
+				required-opps = <&rpmhpd_opp_low_svs>;
+
 				dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
 				       <&gpi_dma0 1 4 QCOM_GPI_I2C>;
 				dma-names = "tx",
@@ -2315,6 +2509,9 @@
 						     "qup-config",
 						     "qup-memory";
 
+				power-domains = <&rpmhpd RPMHPD_CX>;
+				operating-points-v2 = <&qup_opp_table_100mhz>;
+
 				dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>,
 				       <&gpi_dma0 1 4 QCOM_GPI_SPI>;
 				dma-names = "tx",
@@ -2348,6 +2545,9 @@
 						     "qup-config",
 						     "qup-memory";
 
+				power-domains = <&rpmhpd RPMHPD_CX>;
+				required-opps = <&rpmhpd_opp_low_svs>;
+
 				dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>,
 				       <&gpi_dma0 1 5 QCOM_GPI_I2C>;
 				dma-names = "tx",
@@ -2381,6 +2581,9 @@
 						     "qup-config",
 						     "qup-memory";
 
+				power-domains = <&rpmhpd RPMHPD_CX>;
+				operating-points-v2 = <&qup_opp_table_100mhz>;
+
 				dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>,
 				       <&gpi_dma0 1 5 QCOM_GPI_SPI>;
 				dma-names = "tx",
@@ -2414,6 +2617,9 @@
 						     "qup-config",
 						     "qup-memory";
 
+				power-domains = <&rpmhpd RPMHPD_CX>;
+				required-opps = <&rpmhpd_opp_low_svs>;
+
 				dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>,
 				       <&gpi_dma0 1 6 QCOM_GPI_I2C>;
 				dma-names = "tx",
@@ -2447,6 +2653,9 @@
 						     "qup-config",
 						     "qup-memory";
 
+				power-domains = <&rpmhpd RPMHPD_CX>;
+				operating-points-v2 = <&qup_opp_table_100mhz>;
+
 				dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>,
 				       <&gpi_dma0 1 6 QCOM_GPI_SPI>;
 				dma-names = "tx",
@@ -2480,6 +2689,9 @@
 						     "qup-config",
 						     "qup-memory";
 
+				power-domains = <&rpmhpd RPMHPD_CX>;
+				required-opps = <&rpmhpd_opp_low_svs>;
+
 				dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>,
 				       <&gpi_dma0 1 7 QCOM_GPI_I2C>;
 				dma-names = "tx",
@@ -2513,6 +2725,9 @@
 						     "qup-config",
 						     "qup-memory";
 
+				power-domains = <&rpmhpd RPMHPD_CX>;
+				operating-points-v2 = <&qup_opp_table_100mhz>;
+
 				dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>,
 				       <&gpi_dma0 1 7 QCOM_GPI_SPI>;
 				dma-names = "tx",
@@ -2906,6 +3121,208 @@
 			#interconnect-cells = <2>;
 		};
 
+		pcie3: pcie@1bd0000 {
+			device_type = "pci";
+			compatible = "qcom,pcie-x1e80100";
+			reg = <0x0 0x01bd0000 0x0 0x3000>,
+			      <0x0 0x78000000 0x0 0xf1d>,
+			      <0x0 0x78000f40 0x0 0xa8>,
+			      <0x0 0x78001000 0x0 0x1000>,
+			      <0x0 0x78100000 0x0 0x100000>,
+			      <0x0 0x01bd3000 0x0 0x1000>;
+			reg-names = "parf",
+				    "dbi",
+				    "elbi",
+				    "atu",
+				    "config",
+				    "mhi";
+			#address-cells = <3>;
+			#size-cells = <2>;
+			ranges = <0x01000000 0x0 0x00000000 0x0 0x78200000 0x0 0x100000>,
+				 <0x02000000 0x0 0x78300000 0x0 0x78300000 0x0 0x3d00000>,
+				 <0x03000000 0x7 0x40000000 0x7 0x40000000 0x0 0x40000000>;
+			bus-range = <0x00 0xff>;
+
+			dma-coherent;
+
+			linux,pci-domain = <3>;
+			num-lanes = <8>;
+
+			interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 769 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 671 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "msi0",
+					  "msi1",
+					  "msi2",
+					  "msi3",
+					  "msi4",
+					  "msi5",
+					  "msi6",
+					  "msi7",
+					  "global";
+
+			#interrupt-cells = <1>;
+			interrupt-map-mask = <0 0 0 0x7>;
+			interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
+					<0 0 0 2 &intc 0 0 GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>,
+					<0 0 0 3 &intc 0 0 GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>,
+					<0 0 0 4 &intc 0 0 GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
+
+			clocks = <&gcc GCC_PCIE_3_AUX_CLK>,
+				 <&gcc GCC_PCIE_3_CFG_AHB_CLK>,
+				 <&gcc GCC_PCIE_3_MSTR_AXI_CLK>,
+				 <&gcc GCC_PCIE_3_SLV_AXI_CLK>,
+				 <&gcc GCC_PCIE_3_SLV_Q2A_AXI_CLK>,
+				 <&gcc GCC_CFG_NOC_PCIE_ANOC_NORTH_AHB_CLK>,
+				 <&gcc GCC_CNOC_PCIE_NORTH_SF_AXI_CLK>;
+			clock-names = "aux",
+				      "cfg",
+				      "bus_master",
+				      "bus_slave",
+				      "slave_q2a",
+				      "noc_aggr",
+				      "cnoc_sf_axi";
+
+			assigned-clocks = <&gcc GCC_PCIE_3_AUX_CLK>;
+			assigned-clock-rates = <19200000>;
+
+			interconnects = <&pcie_north_anoc MASTER_PCIE_3 QCOM_ICC_TAG_ALWAYS
+					 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
+					<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+					 &cnoc_main SLAVE_PCIE_3 QCOM_ICC_TAG_ALWAYS>;
+			interconnect-names = "pcie-mem",
+					     "cpu-pcie";
+
+			resets = <&gcc GCC_PCIE_3_BCR>,
+				 <&gcc GCC_PCIE_3_LINK_DOWN_BCR>;
+			reset-names = "pci",
+				      "link_down";
+
+			power-domains = <&gcc GCC_PCIE_3_GDSC>;
+
+			phys = <&pcie3_phy>;
+			phy-names = "pciephy";
+
+			operating-points-v2 = <&pcie3_opp_table>;
+
+			status = "disabled";
+
+			pcie3_opp_table: opp-table {
+				compatible = "operating-points-v2";
+
+				/* GEN 1 x1 */
+				opp-2500000 {
+					opp-hz = /bits/ 64 <2500000>;
+					required-opps = <&rpmhpd_opp_low_svs>;
+					opp-peak-kBps = <250000 1>;
+				};
+
+				/* GEN 1 x2 and GEN 2 x1 */
+				opp-5000000 {
+					opp-hz = /bits/ 64 <5000000>;
+					required-opps = <&rpmhpd_opp_low_svs>;
+					opp-peak-kBps = <500000 1>;
+				};
+
+				/* GEN 1 x4 and GEN 2 x2 */
+				opp-10000000 {
+					opp-hz = /bits/ 64 <10000000>;
+					required-opps = <&rpmhpd_opp_low_svs>;
+					opp-peak-kBps = <1000000 1>;
+				};
+
+				/* GEN 1 x8 and GEN 2 x4 */
+				opp-20000000 {
+					opp-hz = /bits/ 64 <20000000>;
+					required-opps = <&rpmhpd_opp_low_svs>;
+					opp-peak-kBps = <2000000 1>;
+				};
+
+				/* GEN 2 x8 */
+				opp-40000000 {
+					opp-hz = /bits/ 64 <40000000>;
+					required-opps = <&rpmhpd_opp_low_svs>;
+					opp-peak-kBps = <4000000 1>;
+				};
+
+				/* GEN 3 x1 */
+				opp-8000000 {
+					opp-hz = /bits/ 64 <8000000>;
+					required-opps = <&rpmhpd_opp_svs>;
+					opp-peak-kBps = <984500 1>;
+				};
+
+				/* GEN 3 x2 and GEN 4 x1 */
+				opp-16000000 {
+					opp-hz = /bits/ 64 <16000000>;
+					required-opps = <&rpmhpd_opp_svs>;
+					opp-peak-kBps = <1969000 1>;
+				};
+
+				/* GEN 3 x4 and GEN 4 x2 */
+				opp-32000000 {
+					opp-hz = /bits/ 64 <32000000>;
+					required-opps = <&rpmhpd_opp_svs>;
+					opp-peak-kBps = <3938000 1>;
+				};
+
+				/* GEN 3 x8 and GEN 4 x4 */
+				opp-64000000 {
+					opp-hz = /bits/ 64 <64000000>;
+					required-opps = <&rpmhpd_opp_svs>;
+					opp-peak-kBps = <7876000 1>;
+				};
+
+				/* GEN 4 x8 */
+				opp-128000000 {
+					opp-hz = /bits/ 64 <128000000>;
+					required-opps = <&rpmhpd_opp_svs>;
+					opp-peak-kBps = <15753000 1>;
+				};
+			};
+		};
+
+		pcie3_phy: phy@1be0000 {
+			compatible = "qcom,x1e80100-qmp-gen4x8-pcie-phy";
+			reg = <0 0x01be0000 0 0x10000>;
+
+			clocks = <&gcc GCC_PCIE_3_PHY_AUX_CLK>,
+				 <&gcc GCC_PCIE_3_CFG_AHB_CLK>,
+				 <&tcsr TCSR_PCIE_8L_CLKREF_EN>,
+				 <&gcc GCC_PCIE_3_PHY_RCHNG_CLK>,
+				 <&gcc GCC_PCIE_3_PIPE_CLK>,
+				 <&gcc GCC_PCIE_3_PIPEDIV2_CLK>;
+			clock-names = "aux",
+				      "cfg_ahb",
+				      "ref",
+				      "rchng",
+				      "pipe",
+				      "pipediv2";
+
+			resets = <&gcc GCC_PCIE_3_PHY_BCR>,
+				 <&gcc GCC_PCIE_3_NOCSR_COM_PHY_BCR>;
+			reset-names = "phy",
+				      "phy_nocsr";
+
+			assigned-clocks = <&gcc GCC_PCIE_3_PHY_RCHNG_CLK>;
+			assigned-clock-rates = <100000000>;
+
+			power-domains = <&gcc GCC_PCIE_3_PHY_GDSC>;
+
+			#clock-cells = <0>;
+			clock-output-names = "pcie3_pipe_clk";
+
+			#phy-cells = <0>;
+
+			status = "disabled";
+		};
+
 		pcie6a: pci@1bf8000 {
 			device_type = "pci";
 			compatible = "qcom,pcie-x1e80100";
@@ -3518,6 +3935,143 @@
 			#interconnect-cells = <2>;
 		};
 
+		remoteproc_adsp: remoteproc@6800000 {
+			compatible = "qcom,x1e80100-adsp-pas";
+			reg = <0x0 0x06800000 0x0 0x10000>;
+
+			interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>,
+					      <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
+					      <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
+					      <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
+					      <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>;
+			interrupt-names = "wdog",
+					  "fatal",
+					  "ready",
+					  "handover",
+					  "stop-ack";
+
+			clocks = <&rpmhcc RPMH_CXO_CLK>;
+			clock-names = "xo";
+
+			power-domains = <&rpmhpd RPMHPD_LCX>,
+					<&rpmhpd RPMHPD_LMX>;
+			power-domain-names = "lcx",
+					     "lmx";
+
+			interconnects = <&lpass_lpicx_noc MASTER_LPASS_PROC QCOM_ICC_TAG_ALWAYS
+					 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+
+			memory-region = <&adspslpi_mem>,
+					<&q6_adsp_dtb_mem>;
+
+			qcom,qmp = <&aoss_qmp>;
+
+			qcom,smem-states = <&smp2p_adsp_out 0>;
+			qcom,smem-state-names = "stop";
+
+			status = "disabled";
+
+			glink-edge {
+				interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
+							     IPCC_MPROC_SIGNAL_GLINK_QMP
+							     IRQ_TYPE_EDGE_RISING>;
+				mboxes = <&ipcc IPCC_CLIENT_LPASS
+						IPCC_MPROC_SIGNAL_GLINK_QMP>;
+
+				label = "lpass";
+				qcom,remote-pid = <2>;
+
+				fastrpc {
+					compatible = "qcom,fastrpc";
+					qcom,glink-channels = "fastrpcglink-apps-dsp";
+					label = "adsp";
+					qcom,non-secure-domain;
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					compute-cb@3 {
+						compatible = "qcom,fastrpc-compute-cb";
+						reg = <3>;
+						iommus = <&apps_smmu 0x1003 0x80>,
+							 <&apps_smmu 0x1063 0x0>;
+						dma-coherent;
+					};
+
+					compute-cb@4 {
+						compatible = "qcom,fastrpc-compute-cb";
+						reg = <4>;
+						iommus = <&apps_smmu 0x1004 0x80>,
+							 <&apps_smmu 0x1064 0x0>;
+						dma-coherent;
+					};
+
+					compute-cb@5 {
+						compatible = "qcom,fastrpc-compute-cb";
+						reg = <5>;
+						iommus = <&apps_smmu 0x1005 0x80>,
+							 <&apps_smmu 0x1065 0x0>;
+						dma-coherent;
+					};
+
+					compute-cb@6 {
+						compatible = "qcom,fastrpc-compute-cb";
+						reg = <6>;
+						iommus = <&apps_smmu 0x1006 0x80>,
+							 <&apps_smmu 0x1066 0x0>;
+						dma-coherent;
+					};
+
+					compute-cb@7 {
+						compatible = "qcom,fastrpc-compute-cb";
+						reg = <7>;
+						iommus = <&apps_smmu 0x1007 0x80>,
+							 <&apps_smmu 0x1067 0x0>;
+						dma-coherent;
+					};
+				};
+
+				gpr {
+					compatible = "qcom,gpr";
+					qcom,glink-channels = "adsp_apps";
+					qcom,domain = <GPR_DOMAIN_ID_ADSP>;
+					qcom,intents = <512 20>;
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					q6apm: service@1 {
+						compatible = "qcom,q6apm";
+						reg = <GPR_APM_MODULE_IID>;
+						#sound-dai-cells = <0>;
+						qcom,protection-domain = "avs/audio",
+									 "msm/adsp/audio_pd";
+
+						q6apmbedai: bedais {
+							compatible = "qcom,q6apm-lpass-dais";
+							#sound-dai-cells = <1>;
+						};
+
+						q6apmdai: dais {
+							compatible = "qcom,q6apm-dais";
+							iommus = <&apps_smmu 0x1001 0x80>,
+								 <&apps_smmu 0x1061 0x0>;
+						};
+					};
+
+					q6prm: service@2 {
+						compatible = "qcom,q6prm";
+						reg = <GPR_PRM_MODULE_IID>;
+						qcom,protection-domain = "avs/audio",
+									 "msm/adsp/audio_pd";
+
+						q6prmcc: clock-controller {
+							compatible = "qcom,q6prm-lpass-clocks";
+							#clock-cells = <2>;
+						};
+					};
+				};
+			};
+		};
+
 		lpass_wsa2macro: codec@6aa0000 {
 			compatible = "qcom,x1e80100-lpass-wsa-macro", "qcom,sm8550-lpass-wsa-macro";
 			reg = <0 0x06aa0000 0 0x1000>;
@@ -3892,6 +4446,112 @@
 			#interconnect-cells = <2>;
 		};
 
+		sdhc_2: mmc@8804000 {
+			compatible = "qcom,x1e80100-sdhci", "qcom,sdhci-msm-v5";
+			reg = <0 0x08804000 0 0x1000>;
+
+			interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "hc_irq", "pwr_irq";
+
+			clocks = <&gcc GCC_SDCC2_AHB_CLK>,
+				 <&gcc GCC_SDCC2_APPS_CLK>,
+				 <&rpmhcc RPMH_CXO_CLK>;
+			clock-names = "iface", "core", "xo";
+			iommus = <&apps_smmu 0x520 0>;
+			qcom,dll-config = <0x0007642c>;
+			qcom,ddr-config = <0x80040868>;
+			power-domains = <&rpmhpd RPMHPD_CX>;
+			operating-points-v2 = <&sdhc2_opp_table>;
+
+			interconnects = <&aggre2_noc MASTER_SDCC_2 QCOM_ICC_TAG_ALWAYS
+					 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
+					<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+					 &config_noc SLAVE_SDCC_2 QCOM_ICC_TAG_ACTIVE_ONLY>;
+			interconnect-names = "sdhc-ddr", "cpu-sdhc";
+			bus-width = <4>;
+			dma-coherent;
+
+			status = "disabled";
+
+			sdhc2_opp_table: opp-table {
+				compatible = "operating-points-v2";
+
+				opp-19200000 {
+					opp-hz = /bits/ 64 <19200000>;
+					required-opps = <&rpmhpd_opp_min_svs>;
+				};
+
+				opp-50000000 {
+					opp-hz = /bits/ 64 <50000000>;
+					required-opps = <&rpmhpd_opp_low_svs>;
+				};
+
+				opp-100000000 {
+					opp-hz = /bits/ 64 <100000000>;
+					required-opps = <&rpmhpd_opp_svs>;
+				};
+
+				opp-202000000 {
+					opp-hz = /bits/ 64 <202000000>;
+					required-opps = <&rpmhpd_opp_svs_l1>;
+				};
+			};
+		};
+
+		sdhc_4: mmc@8844000 {
+			compatible = "qcom,x1e80100-sdhci", "qcom,sdhci-msm-v5";
+			reg = <0 0x08844000 0 0x1000>;
+
+			interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "hc_irq", "pwr_irq";
+
+			clocks = <&gcc GCC_SDCC4_AHB_CLK>,
+				 <&gcc GCC_SDCC4_APPS_CLK>,
+				 <&rpmhcc RPMH_CXO_CLK>;
+			clock-names = "iface", "core", "xo";
+			iommus = <&apps_smmu 0x160 0>;
+			qcom,dll-config = <0x0007642c>;
+			qcom,ddr-config = <0x80040868>;
+			power-domains = <&rpmhpd RPMHPD_CX>;
+			operating-points-v2 = <&sdhc4_opp_table>;
+
+			interconnects = <&aggre2_noc MASTER_SDCC_4 QCOM_ICC_TAG_ALWAYS
+					 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
+					<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+					 &config_noc SLAVE_SDCC_4 QCOM_ICC_TAG_ACTIVE_ONLY>;
+			interconnect-names = "sdhc-ddr", "cpu-sdhc";
+			bus-width = <4>;
+			dma-coherent;
+
+			status = "disabled";
+
+			sdhc4_opp_table: opp-table {
+				compatible = "operating-points-v2";
+
+				opp-19200000 {
+					opp-hz = /bits/ 64 <19200000>;
+					required-opps = <&rpmhpd_opp_min_svs>;
+				};
+
+				opp-50000000 {
+					opp-hz = /bits/ 64 <50000000>;
+					required-opps = <&rpmhpd_opp_low_svs>;
+				};
+
+				opp-100000000 {
+					opp-hz = /bits/ 64 <100000000>;
+					required-opps = <&rpmhpd_opp_svs>;
+				};
+
+				opp-202000000 {
+					opp-hz = /bits/ 64 <202000000>;
+					required-opps = <&rpmhpd_opp_svs_l1>;
+				};
+			};
+		};
+
 		usb_2_hsphy: phy@88e0000 {
 			compatible = "qcom,x1e80100-snps-eusb2-phy",
 				     "qcom,sm8550-snps-eusb2-phy";
@@ -4063,6 +4723,8 @@
 				snps,dis_u2_susphy_quirk;
 				snps,dis_enblslpm_quirk;
 				snps,usb3_lpm_capable;
+				snps,dis-u1-entry-quirk;
+				snps,dis-u2-entry-quirk;
 
 				dma-coherent;
 
@@ -4118,7 +4780,7 @@
 					  <&gcc GCC_USB20_MASTER_CLK>;
 			assigned-clock-rates = <19200000>, <200000000>;
 
-			interrupts-extended = <&intc GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
+			interrupts-extended = <&intc GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
 					      <&pdc 50 IRQ_TYPE_EDGE_BOTH>,
 					      <&pdc 49 IRQ_TYPE_EDGE_BOTH>;
 			interrupt-names = "pwr_event",
@@ -4144,11 +4806,13 @@
 			usb_2_dwc3: usb@a200000 {
 				compatible = "snps,dwc3";
 				reg = <0 0x0a200000 0 0xcd00>;
-				interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;
+				interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
 				iommus = <&apps_smmu 0x14e0 0x0>;
 				phys = <&usb_2_hsphy>;
 				phy-names = "usb2-phy";
 				maximum-speed = "high-speed";
+				snps,dis-u1-entry-quirk;
+				snps,dis-u2-entry-quirk;
 
 				ports {
 					#address-cells = <1>;
@@ -4245,6 +4909,8 @@
 				snps,dis_u2_susphy_quirk;
 				snps,dis_enblslpm_quirk;
 				snps,usb3_lpm_capable;
+				snps,dis-u1-entry-quirk;
+				snps,dis-u2-entry-quirk;
 
 				dma-coherent;
 			};
@@ -4316,6 +4982,8 @@
 				snps,dis_u2_susphy_quirk;
 				snps,dis_enblslpm_quirk;
 				snps,usb3_lpm_capable;
+				snps,dis-u1-entry-quirk;
+				snps,dis-u2-entry-quirk;
 
 				dma-coherent;
 
@@ -4414,6 +5082,8 @@
 				snps,dis_u2_susphy_quirk;
 				snps,dis_enblslpm_quirk;
 				snps,usb3_lpm_capable;
+				snps,dis-u1-entry-quirk;
+				snps,dis-u2-entry-quirk;
 
 				dma-coherent;
 
@@ -5629,6 +6299,34 @@
 				};
 			};
 
+			qup_uart14_default: qup-uart14-default-state {
+				cts-pins {
+					pins = "gpio56";
+					function = "qup1_se6";
+					bias-bus-hold;
+				};
+
+				rts-pins {
+					pins = "gpio57";
+					function = "qup1_se6";
+					drive-strength = <2>;
+					bias-disable;
+				};
+
+				tx-pins {
+					pins = "gpio58";
+					function = "qup1_se6";
+					drive-strength = <2>;
+					bias-disable;
+				};
+
+				rx-pins {
+					pins = "gpio59";
+					function = "qup1_se6";
+					bias-pull-up;
+				};
+			};
+
 			qup_uart21_default: qup-uart21-default-state {
 				tx-pins {
 					pins = "gpio86";
@@ -5644,6 +6342,1487 @@
 					bias-disable;
 				};
 			};
+
+			sdc2_default: sdc2-default-state {
+				clk-pins {
+					pins = "sdc2_clk";
+					drive-strength = <16>;
+					bias-disable;
+				};
+
+				cmd-pins {
+					pins = "sdc2_cmd";
+					drive-strength = <10>;
+					bias-pull-up;
+				};
+
+				data-pins {
+					pins = "sdc2_data";
+					drive-strength = <10>;
+					bias-pull-up;
+				};
+			};
+
+			sdc2_sleep: sdc2-sleep-state {
+				clk-pins {
+					pins = "sdc2_clk";
+					drive-strength = <2>;
+					bias-disable;
+				};
+
+				cmd-pins {
+					pins = "sdc2_cmd";
+					drive-strength = <2>;
+					bias-pull-up;
+				};
+
+				data-pins {
+					pins = "sdc2_data";
+					drive-strength = <2>;
+					bias-pull-up;
+				};
+			};
+		};
+
+		stm@10002000 {
+			compatible = "arm,coresight-stm", "arm,primecell";
+			reg = <0x0 0x10002000 0x0 0x1000>,
+			      <0x0 0x16280000 0x0 0x180000>;
+			reg-names = "stm-base",
+				    "stm-stimulus-base";
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			out-ports {
+				port {
+					stm_out: endpoint {
+						remote-endpoint = <&funnel0_in7>;
+					};
+				};
+			};
+		};
+
+		tpdm@10003000 {
+			compatible = "qcom,coresight-tpdm", "arm,primecell";
+			reg = <0x0 0x10003000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			qcom,cmb-element-bits = <32>;
+			qcom,cmb-msrs-num = <32>;
+			status = "disabled";
+
+			out-ports {
+				port {
+					dcc_tpdm_out: endpoint {
+						remote-endpoint = <&qdss_tpda_in0>;
+					};
+				};
+			};
+		};
+
+		tpda@10004000 {
+			compatible = "qcom,coresight-tpda", "arm,primecell";
+			reg = <0x0 0x10004000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			in-ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					reg = <0>;
+
+					qdss_tpda_in0: endpoint {
+						remote-endpoint = <&dcc_tpdm_out>;
+					};
+				};
+
+				port@1 {
+					reg = <1>;
+
+					qdss_tpda_in1: endpoint {
+						remote-endpoint = <&qdss_tpdm_out>;
+					};
+				};
+			};
+
+			out-ports {
+				port {
+					qdss_tpda_out: endpoint {
+						remote-endpoint = <&funnel0_in6>;
+					};
+				};
+			};
+		};
+
+		tpdm@1000f000 {
+			compatible = "qcom,coresight-tpdm", "arm,primecell";
+			reg = <0x0 0x1000f000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			qcom,cmb-element-bits = <32>;
+			qcom,cmb-msrs-num = <32>;
+
+			out-ports {
+				port {
+					qdss_tpdm_out: endpoint {
+						remote-endpoint = <&qdss_tpda_in1>;
+					};
+				};
+			};
+		};
+
+		funnel@10041000 {
+			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+			reg = <0x0 0x10041000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			in-ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@6 {
+					reg = <6>;
+
+					funnel0_in6: endpoint {
+						remote-endpoint = <&qdss_tpda_out>;
+					};
+				};
+
+				port@7 {
+					reg = <7>;
+
+					funnel0_in7: endpoint {
+						remote-endpoint = <&stm_out>;
+					};
+				};
+			};
+
+			out-ports {
+				port {
+					funnel0_out: endpoint {
+						remote-endpoint = <&qdss_funnel_in0>;
+					};
+				};
+			};
+		};
+
+		funnel@10042000 {
+			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+			reg = <0x0 0x10042000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			in-ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@2 {
+					reg = <2>;
+
+					funnel1_in2: endpoint {
+						remote-endpoint = <&tmess_funnel_out>;
+					};
+				};
+
+				port@5 {
+					reg = <5>;
+
+					funnel1_in5: endpoint {
+						remote-endpoint = <&dlst_funnel_out>;
+					};
+				};
+
+				port@6 {
+					reg = <6>;
+
+					funnel1_in6: endpoint {
+						remote-endpoint = <&dlct1_funnel_out>;
+					};
+				};
+			};
+
+			out-ports {
+				port {
+					funnel1_out: endpoint {
+						remote-endpoint = <&qdss_funnel_in1>;
+					};
+				};
+			};
+		};
+
+		funnel@10045000 {
+			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+			reg = <0x0 0x10045000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			in-ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					reg = <0>;
+
+					qdss_funnel_in0: endpoint {
+						remote-endpoint = <&funnel0_out>;
+					};
+				};
+
+				port@1 {
+					reg = <1>;
+
+					qdss_funnel_in1: endpoint {
+						remote-endpoint = <&funnel1_out>;
+					};
+				};
+			};
+
+			out-ports {
+				port {
+					qdss_funnel_out: endpoint {
+						remote-endpoint = <&aoss_funnel_in7>;
+					};
+				};
+			};
+		};
+
+		tpdm@10800000 {
+			compatible = "qcom,coresight-tpdm", "arm,primecell";
+			reg = <0x0 0x10800000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			qcom,cmb-element-bits = <64>;
+			qcom,cmb-msrs-num = <32>;
+
+			out-ports {
+				port {
+					mxa_tpdm_out: endpoint {
+						remote-endpoint = <&dlct2_tpda_in15>;
+					};
+				};
+			};
+		};
+
+		tpdm@1082c000 {
+			compatible = "qcom,coresight-tpdm", "arm,primecell";
+			reg = <0x0 0x1082c000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			qcom,dsb-element-bits = <32>;
+			qcom,dsb-msrs-num = <32>;
+
+			out-ports {
+				port {
+					gcc_tpdm_out: endpoint {
+						remote-endpoint = <&dlct1_tpda_in21>;
+					};
+				};
+			};
+		};
+
+		tpdm@10841000 {
+			compatible = "qcom,coresight-tpdm", "arm,primecell";
+			reg = <0x0 0x10841000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			qcom,cmb-element-bits = <32>;
+			qcom,cmb-msrs-num = <32>;
+
+			out-ports {
+				port {
+					prng_tpdm_out: endpoint {
+						remote-endpoint = <&dlct1_tpda_in19>;
+					};
+				};
+			};
+		};
+
+		tpdm@10844000 {
+			compatible = "qcom,coresight-tpdm", "arm,primecell";
+			reg = <0x0 0x10844000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			qcom,dsb-element-bits = <32>;
+			qcom,dsb-msrs-num = <32>;
+
+			out-ports {
+				port {
+					lpass_cx_tpdm_out: endpoint {
+						remote-endpoint = <&lpass_cx_funnel_in0>;
+					};
+				};
+			};
+		};
+
+		funnel@10846000 {
+			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+			reg = <0x0 0x10846000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			in-ports {
+				port {
+					lpass_cx_funnel_in0: endpoint {
+						remote-endpoint = <&lpass_cx_tpdm_out>;
+					};
+				};
+			};
+
+			out-ports {
+				port {
+					lpass_cx_funnel_out: endpoint {
+						remote-endpoint = <&dlct1_tpda_in4>;
+					};
+				};
+			};
+		};
+
+		cti@1098b000 {
+			compatible = "arm,coresight-cti", "arm,primecell";
+			reg = <0x0 0x1098b000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+		};
+
+		tpdm@109d0000 {
+			compatible = "qcom,coresight-tpdm", "arm,primecell";
+			reg = <0x0 0x109d0000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			qcom,dsb-element-bits = <32>;
+			qcom,dsb-msrs-num = <32>;
+			status = "disabled";
+
+			out-ports {
+				port {
+					qm_tpdm_out: endpoint {
+						remote-endpoint = <&dlct1_tpda_in20>;
+					};
+				};
+			};
+		};
+
+		tpdm@10ac0000 {
+			compatible = "qcom,coresight-tpdm", "arm,primecell";
+			reg = <0x0 0x10ac0000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			qcom,dsb-element-bits = <32>;
+			qcom,dsb-msrs-num = <32>;
+			status = "disabled";
+
+			out-ports {
+				port {
+					dlst_tpdm0_out: endpoint {
+						remote-endpoint = <&dlst_tpda_in8>;
+					};
+				};
+			};
+		};
+
+		tpdm@10ac1000 {
+			compatible = "qcom,coresight-tpdm", "arm,primecell";
+			reg = <0x0 0x10ac1000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			qcom,cmb-element-bits = <64>;
+			qcom,cmb-msrs-num = <32>;
+
+			out-ports {
+				port {
+					dlst_tpdm1_out: endpoint {
+						remote-endpoint = <&dlst_tpda_in9>;
+					};
+				};
+			};
+		};
+
+		tpda@10ac4000 {
+			compatible = "qcom,coresight-tpda", "arm,primecell";
+			reg = <0x0 0x10ac4000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			in-ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@8 {
+					reg = <8>;
+
+					dlst_tpda_in8: endpoint {
+						remote-endpoint = <&dlst_tpdm0_out>;
+					};
+				};
+
+				port@9 {
+					reg = <9>;
+
+					dlst_tpda_in9: endpoint {
+						remote-endpoint = <&dlst_tpdm1_out>;
+					};
+				};
+			};
+
+			out-ports {
+				port {
+					dlst_tpda_out: endpoint {
+						remote-endpoint = <&dlst_funnel_in0>;
+					};
+				};
+			};
+		};
+
+		funnel@10ac5000 {
+			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+			reg = <0x0 0x10ac5000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			in-ports {
+				port {
+					dlst_funnel_in0: endpoint {
+						remote-endpoint = <&dlst_tpda_out>;
+					};
+				};
+			};
+
+			out-ports {
+				port {
+					dlst_funnel_out: endpoint {
+						remote-endpoint = <&funnel1_in5>;
+					};
+				};
+			};
+		};
+
+		funnel@10b04000 {
+			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+			reg = <0x0 0x10b04000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			in-ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@3 {
+					reg = <3>;
+
+					aoss_funnel_in3: endpoint {
+						remote-endpoint = <&ddr_lpi_funnel_out>;
+					};
+				};
+
+				port@6 {
+					reg = <6>;
+
+					aoss_funnel_in6: endpoint {
+						remote-endpoint = <&aoss_tpda_out>;
+					};
+				};
+
+				port@7 {
+					reg = <7>;
+
+					aoss_funnel_in7: endpoint {
+						remote-endpoint = <&qdss_funnel_out>;
+					};
+				};
+			};
+
+			out-ports {
+				port {
+					aoss_funnel_out: endpoint {
+						remote-endpoint = <&etf0_in>;
+					};
+				};
+			};
+		};
+
+		etf0: tmc@10b05000 {
+			compatible = "arm,coresight-tmc", "arm,primecell";
+			reg = <0x0 0x10b05000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			in-ports {
+				port {
+					etf0_in: endpoint {
+						remote-endpoint = <&aoss_funnel_out>;
+					};
+				};
+			};
+
+			out-ports {
+				port {
+					etf0_out: endpoint {
+						remote-endpoint = <&swao_rep_in>;
+					};
+				};
+			};
+		};
+
+		replicator@10b06000 {
+			compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
+			reg = <0x0 0x10b06000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			in-ports {
+				port {
+					swao_rep_in: endpoint {
+						remote-endpoint = <&etf0_out>;
+					};
+				};
+			};
+
+			out-ports {
+				port {
+					swao_rep_out1: endpoint {
+						remote-endpoint = <&eud_in>;
+					};
+				};
+			};
+		};
+
+		tpda@10b08000 {
+			compatible = "qcom,coresight-tpda", "arm,primecell";
+			reg = <0x0 0x10b08000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			in-ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					reg = <0>;
+
+					aoss_tpda_in0: endpoint {
+						remote-endpoint = <&aoss_tpdm0_out>;
+					};
+				};
+
+				port@1 {
+					reg = <1>;
+
+					aoss_tpda_in1: endpoint {
+						remote-endpoint = <&aoss_tpdm1_out>;
+					};
+				};
+
+				port@2 {
+					reg = <2>;
+
+					aoss_tpda_in2: endpoint {
+						remote-endpoint = <&aoss_tpdm2_out>;
+					};
+				};
+
+				port@3 {
+					reg = <3>;
+
+					aoss_tpda_in3: endpoint {
+						remote-endpoint = <&aoss_tpdm3_out>;
+					};
+				};
+
+				port@4 {
+					reg = <4>;
+
+					aoss_tpda_in4: endpoint {
+						remote-endpoint = <&aoss_tpdm4_out>;
+					};
+				};
+			};
+
+			out-ports {
+				port {
+					aoss_tpda_out: endpoint {
+						remote-endpoint = <&aoss_funnel_in6>;
+					};
+				};
+			};
+		};
+
+		tpdm@10b09000 {
+			compatible = "qcom,coresight-tpdm", "arm,primecell";
+			reg = <0x0 0x10b09000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			qcom,cmb-element-bits = <64>;
+			qcom,cmb-msrs-num = <32>;
+
+			out-ports {
+				port {
+					aoss_tpdm0_out: endpoint {
+						remote-endpoint = <&aoss_tpda_in0>;
+					};
+				};
+			};
+		};
+
+		tpdm@10b0a000 {
+			compatible = "qcom,coresight-tpdm", "arm,primecell";
+			reg = <0x0 0x10b0a000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			qcom,cmb-element-bits = <64>;
+			qcom,cmb-msrs-num = <32>;
+
+			out-ports {
+				port {
+					aoss_tpdm1_out: endpoint {
+						remote-endpoint = <&aoss_tpda_in1>;
+					};
+				};
+			};
+		};
+
+		tpdm@10b0b000 {
+			compatible = "qcom,coresight-tpdm", "arm,primecell";
+			reg = <0x0 0x10b0b000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			qcom,cmb-element-bits = <64>;
+			qcom,cmb-msrs-num = <32>;
+
+			out-ports {
+				port {
+					aoss_tpdm2_out: endpoint {
+						remote-endpoint = <&aoss_tpda_in2>;
+					};
+				};
+			};
+		};
+
+		tpdm@10b0c000 {
+			compatible = "qcom,coresight-tpdm", "arm,primecell";
+			reg = <0x0 0x10b0c000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			qcom,cmb-element-bits = <64>;
+			qcom,cmb-msrs-num = <32>;
+
+			out-ports {
+				port {
+					aoss_tpdm3_out: endpoint {
+						remote-endpoint = <&aoss_tpda_in3>;
+					};
+				};
+			};
+		};
+
+		tpdm@10b0d000 {
+			compatible = "qcom,coresight-tpdm", "arm,primecell";
+			reg = <0x0 0x10b0d000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			qcom,dsb-element-bits = <32>;
+			qcom,dsb-msrs-num = <32>;
+
+			out-ports {
+				port {
+					aoss_tpdm4_out: endpoint {
+						remote-endpoint = <&aoss_tpda_in4>;
+					};
+				};
+			};
+		};
+
+		tpdm@10b20000 {
+			compatible = "qcom,coresight-tpdm", "arm,primecell";
+			reg = <0x0 0x10b20000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			qcom,dsb-element-bits = <32>;
+			qcom,dsb-msrs-num = <32>;
+			status = "disabled";
+
+			out-ports {
+				port {
+					lpicc_tpdm_out: endpoint {
+						remote-endpoint = <&ddr_lpi_tpda_in>;
+					};
+				};
+			};
+		};
+
+		tpda@10b23000 {
+			compatible = "qcom,coresight-tpda", "arm,primecell";
+			reg = <0x0 0x10b23000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+			status = "disabled";
+
+			in-ports {
+				port {
+					ddr_lpi_tpda_in: endpoint {
+						remote-endpoint = <&lpicc_tpdm_out>;
+					};
+				};
+			};
+
+			out-ports {
+				port {
+					ddr_lpi_tpda_out: endpoint {
+						remote-endpoint = <&ddr_lpi_funnel_in0>;
+					};
+				};
+			};
+		};
+
+		funnel@10b24000 {
+			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+			reg = <0x0 0x10b24000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+			status = "disabled";
+
+			in-ports {
+				port {
+					ddr_lpi_funnel_in0: endpoint {
+						remote-endpoint = <&ddr_lpi_tpda_out>;
+					};
+				};
+			};
+
+			out-ports {
+				port {
+					ddr_lpi_funnel_out: endpoint {
+						remote-endpoint = <&aoss_funnel_in3>;
+					};
+				};
+			};
+		};
+
+		tpdm@10c08000 {
+			compatible = "qcom,coresight-tpdm", "arm,primecell";
+			reg = <0x0 0x10c08000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			qcom,dsb-element-bits = <32>;
+			qcom,dsb-msrs-num = <32>;
+
+			out-ports {
+				port {
+					mm_tpdm_out: endpoint {
+						remote-endpoint = <&mm_funnel_in4>;
+					};
+				};
+			};
+		};
+
+		funnel@10c0b000 {
+			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+			reg = <0x0 0x10c0b000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			in-ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@4 {
+					reg = <4>;
+
+					mm_funnel_in4: endpoint {
+						remote-endpoint = <&mm_tpdm_out>;
+					};
+				};
+			};
+
+			out-ports {
+				port {
+					mm_funnel_out: endpoint {
+						remote-endpoint = <&dlct2_tpda_in4>;
+					};
+				};
+			};
+		};
+
+		tpdm@10c28000 {
+			compatible = "qcom,coresight-tpdm", "arm,primecell";
+			reg = <0x0 0x10c28000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			qcom,dsb-element-bits = <32>;
+			qcom,dsb-msrs-num = <32>;
+
+			out-ports {
+				port {
+					dlct1_tpdm_out: endpoint {
+						remote-endpoint = <&dlct1_tpda_in26>;
+					};
+				};
+			};
+		};
+
+		tpdm@10c29000 {
+			compatible = "qcom,coresight-tpdm", "arm,primecell";
+			reg = <0x0 0x10c29000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			qcom,cmb-element-bits = <64>;
+			qcom,cmb-msrs-num = <32>;
+
+			out-ports {
+				port {
+					ipcc_tpdm_out: endpoint {
+						remote-endpoint = <&dlct1_tpda_in27>;
+					};
+				};
+			};
+		};
+
+		tpda@10c2b000 {
+			compatible = "qcom,coresight-tpda", "arm,primecell";
+			reg = <0x0 0x10c2b000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			in-ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@4 {
+					reg = <4>;
+
+					dlct1_tpda_in4: endpoint {
+						remote-endpoint = <&lpass_cx_funnel_out>;
+					};
+				};
+
+				port@13 {
+					reg = <19>;
+
+					dlct1_tpda_in19: endpoint {
+						remote-endpoint = <&prng_tpdm_out>;
+					};
+				};
+
+				port@14 {
+					reg = <20>;
+
+					dlct1_tpda_in20: endpoint {
+						remote-endpoint = <&qm_tpdm_out>;
+					};
+				};
+
+				port@15 {
+					reg = <21>;
+
+					dlct1_tpda_in21: endpoint {
+						remote-endpoint = <&gcc_tpdm_out>;
+					};
+				};
+
+				port@1a {
+					reg = <26>;
+
+					dlct1_tpda_in26: endpoint {
+						remote-endpoint = <&dlct1_tpdm_out>;
+					};
+				};
+
+				port@1b {
+					reg = <27>;
+
+					dlct1_tpda_in27: endpoint {
+						remote-endpoint = <&ipcc_tpdm_out>;
+					};
+				};
+			};
+
+			out-ports {
+				port {
+					dlct1_tpda_out: endpoint {
+						remote-endpoint = <&dlct1_funnel_in0>;
+					};
+				};
+			};
+		};
+
+		funnel@10c2c000 {
+			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+			reg = <0x0 0x10c2c000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			in-ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					reg = <0>;
+
+					dlct1_funnel_in0: endpoint {
+						remote-endpoint = <&dlct1_tpda_out>;
+					};
+				};
+
+				port@4 {
+					reg = <4>;
+
+					dlct1_funnel_in4: endpoint {
+						remote-endpoint = <&dlct2_funnel_out>;
+					};
+				};
+
+				port@5 {
+					reg = <5>;
+
+					dlct1_funnel_in5: endpoint {
+						remote-endpoint = <&ddr_funnel0_out>;
+					};
+				};
+			};
+
+			out-ports {
+				port {
+					dlct1_funnel_out: endpoint {
+						remote-endpoint = <&funnel1_in6>;
+					};
+				};
+			};
+		};
+
+		tpdm@10c38000 {
+			compatible = "qcom,coresight-tpdm", "arm,primecell";
+			reg = <0x0 0x10c38000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			qcom,cmb-element-bits = <64>;
+			qcom,cmb-msrs-num = <32>;
+
+			out-ports {
+				port {
+					dlct2_tpdm0_out: endpoint {
+						remote-endpoint = <&dlct2_tpda_in16>;
+					};
+				};
+			};
+		};
+
+		tpdm@10c39000 {
+			compatible = "qcom,coresight-tpdm", "arm,primecell";
+			reg = <0x0 0x10c39000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			qcom,cmb-element-bits = <64>;
+			qcom,cmb-msrs-num = <32>;
+
+			out-ports {
+				port {
+					dlct2_tpdm1_out: endpoint {
+						remote-endpoint = <&dlct2_tpda_in17>;
+					};
+				};
+			};
+		};
+
+		tpda@10c3c000 {
+			compatible = "qcom,coresight-tpda", "arm,primecell";
+			reg = <0x0 0x10c3c000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			in-ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@4 {
+					reg = <4>;
+
+					dlct2_tpda_in4: endpoint {
+						remote-endpoint = <&mm_funnel_out>;
+					};
+				};
+
+				port@f {
+					reg = <15>;
+
+					dlct2_tpda_in15: endpoint {
+						remote-endpoint = <&mxa_tpdm_out>;
+					};
+				};
+
+				port@10 {
+					reg = <16>;
+
+					dlct2_tpda_in16: endpoint {
+						remote-endpoint = <&dlct2_tpdm0_out>;
+					};
+				};
+
+				port@11 {
+					reg = <17>;
+
+					dlct2_tpda_in17: endpoint {
+						remote-endpoint = <&dlct2_tpdm1_out>;
+					};
+				};
+			};
+
+			out-ports {
+				port {
+					dlct2_tpda_out: endpoint {
+						remote-endpoint = <&dlct2_funnel_in0>;
+					};
+				};
+			};
+		};
+
+		funnel@10c3d000 {
+			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+			reg = <0x0 0x10c3d000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			in-ports {
+				port {
+					dlct2_funnel_in0: endpoint {
+						remote-endpoint = <&dlct2_tpda_out>;
+					};
+				};
+			};
+
+			out-ports {
+				port {
+					dlct2_funnel_out: endpoint {
+						remote-endpoint = <&dlct1_funnel_in4>;
+					};
+				};
+			};
+		};
+
+		tpdm@10cc1000 {
+			compatible = "qcom,coresight-tpdm", "arm,primecell";
+			reg = <0x0 0x10cc1000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			qcom,cmb-element-bits = <64>;
+			qcom,cmb-msrs-num = <32>;
+			qcom,dsb-element-bits = <32>;
+			qcom,dsb-msrs-num = <32>;
+			status = "disabled";
+
+			out-ports {
+				port {
+					tmess_tpdm1_out: endpoint {
+						remote-endpoint = <&tmess_tpda_in2>;
+					};
+				};
+			};
+		};
+
+		tpda@10cc4000 {
+			compatible = "qcom,coresight-tpda", "arm,primecell";
+			reg = <0x0 0x10cc4000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			in-ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@2 {
+					reg = <2>;
+
+					tmess_tpda_in2: endpoint {
+						remote-endpoint = <&tmess_tpdm1_out>;
+					};
+				};
+			};
+
+			out-ports {
+				port {
+					tmess_tpda_out: endpoint {
+						remote-endpoint = <&tmess_funnel_in0>;
+					};
+				};
+			};
+		};
+
+		funnel@10cc5000 {
+			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+			reg = <0x0 0x10cc5000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			in-ports {
+				port {
+					tmess_funnel_in0: endpoint {
+						remote-endpoint = <&tmess_tpda_out>;
+					};
+				};
+			};
+
+			out-ports {
+				port {
+					tmess_funnel_out: endpoint {
+						remote-endpoint = <&funnel1_in2>;
+					};
+				};
+			};
+		};
+
+		funnel@10d04000 {
+			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+			reg = <0x0 0x10d04000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			in-ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@6 {
+					reg = <6>;
+
+					ddr_funnel0_in6: endpoint {
+						remote-endpoint = <&ddr_funnel1_out>;
+					};
+				};
+			};
+
+			out-ports {
+				port {
+					ddr_funnel0_out: endpoint {
+						remote-endpoint = <&dlct1_funnel_in5>;
+					};
+				};
+			};
+		};
+
+		tpdm@10d08000 {
+			compatible = "qcom,coresight-tpdm", "arm,primecell";
+			reg = <0x0 0x10d08000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			qcom,cmb-element-bits = <32>;
+			qcom,cmb-msrs-num = <32>;
+
+			out-ports {
+				port {
+					llcc0_tpdm_out: endpoint {
+						remote-endpoint = <&llcc_tpda_in0>;
+					};
+				};
+			};
+		};
+
+		tpdm@10d09000 {
+			compatible = "qcom,coresight-tpdm", "arm,primecell";
+			reg = <0x0 0x10d09000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			qcom,cmb-element-bits = <32>;
+			qcom,cmb-msrs-num = <32>;
+
+			out-ports {
+				port {
+					llcc1_tpdm_out: endpoint {
+						remote-endpoint = <&llcc_tpda_in1>;
+					};
+				};
+			};
+		};
+
+		tpdm@10d0a000 {
+			compatible = "qcom,coresight-tpdm", "arm,primecell";
+			reg = <0x0 0x10d0a000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			qcom,cmb-element-bits = <32>;
+			qcom,cmb-msrs-num = <32>;
+
+			out-ports {
+				port {
+					llcc2_tpdm_out: endpoint {
+						remote-endpoint = <&llcc_tpda_in2>;
+					};
+				};
+			};
+		};
+
+		tpdm@10d0b000 {
+			compatible = "qcom,coresight-tpdm", "arm,primecell";
+			reg = <0x0 0x10d0b000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			qcom,cmb-element-bits = <32>;
+			qcom,cmb-msrs-num = <32>;
+
+			out-ports {
+				port {
+					llcc3_tpdm_out: endpoint {
+						remote-endpoint = <&llcc_tpda_in3>;
+					};
+				};
+			};
+		};
+
+		tpdm@10d0c000 {
+			compatible = "qcom,coresight-tpdm", "arm,primecell";
+			reg = <0x0 0x10d0c000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			qcom,cmb-element-bits = <32>;
+			qcom,cmb-msrs-num = <32>;
+
+			out-ports {
+				port {
+					llcc4_tpdm_out: endpoint {
+						remote-endpoint = <&llcc_tpda_in4>;
+					};
+				};
+			};
+		};
+
+		tpdm@10d0d000 {
+			compatible = "qcom,coresight-tpdm", "arm,primecell";
+			reg = <0x0 0x10d0d000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			qcom,cmb-element-bits = <32>;
+			qcom,cmb-msrs-num = <32>;
+
+			out-ports {
+				port {
+					llcc5_tpdm_out: endpoint {
+						remote-endpoint = <&llcc_tpda_in5>;
+					};
+				};
+			};
+		};
+
+		tpdm@10d0e000 {
+			compatible = "qcom,coresight-tpdm", "arm,primecell";
+			reg = <0x0 0x10d0e000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			qcom,cmb-element-bits = <32>;
+			qcom,cmb-msrs-num = <32>;
+
+			out-ports {
+				port {
+					llcc6_tpdm_out: endpoint {
+						remote-endpoint = <&llcc_tpda_in6>;
+					};
+				};
+			};
+		};
+
+		tpdm@10d0f000 {
+			compatible = "qcom,coresight-tpdm", "arm,primecell";
+			reg = <0x0 0x10d0f000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			qcom,cmb-element-bits = <32>;
+			qcom,cmb-msrs-num = <32>;
+
+			out-ports {
+				port {
+					llcc7_tpdm_out: endpoint {
+						remote-endpoint = <&llcc_tpda_in7>;
+					};
+				};
+			};
+		};
+
+		tpda@10d12000 {
+			compatible = "qcom,coresight-tpda", "arm,primecell";
+			reg = <0x0 0x10d12000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			in-ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					reg = <0>;
+
+					llcc_tpda_in0: endpoint {
+						remote-endpoint = <&llcc0_tpdm_out>;
+					};
+				};
+
+				port@1 {
+					reg = <1>;
+
+					llcc_tpda_in1: endpoint {
+						remote-endpoint = <&llcc1_tpdm_out>;
+					};
+				};
+
+				port@2 {
+					reg = <2>;
+
+					llcc_tpda_in2: endpoint {
+						remote-endpoint = <&llcc2_tpdm_out>;
+					};
+				};
+
+				port@3 {
+					reg = <3>;
+
+					llcc_tpda_in3: endpoint {
+						remote-endpoint = <&llcc3_tpdm_out>;
+					};
+				};
+
+				port@4 {
+					reg = <4>;
+
+					llcc_tpda_in4: endpoint {
+						remote-endpoint = <&llcc4_tpdm_out>;
+					};
+				};
+
+				port@5 {
+					reg = <5>;
+
+					llcc_tpda_in5: endpoint {
+						remote-endpoint = <&llcc5_tpdm_out>;
+					};
+				};
+
+				port@6 {
+					reg = <6>;
+
+					llcc_tpda_in6: endpoint {
+						remote-endpoint = <&llcc6_tpdm_out>;
+					};
+				};
+
+				port@7 {
+					reg = <7>;
+
+					llcc_tpda_in7: endpoint {
+						remote-endpoint = <&llcc7_tpdm_out>;
+					};
+				};
+			};
+
+			out-ports {
+				port {
+					llcc_tpda_out: endpoint {
+						remote-endpoint = <&ddr_funnel1_in0>;
+					};
+				};
+			};
+		};
+
+		funnel@10d13000 {
+			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+			reg = <0x0 0x10d13000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			in-ports {
+				port {
+					ddr_funnel1_in0: endpoint {
+						remote-endpoint = <&llcc_tpda_out>;
+					};
+				};
+			};
+
+			out-ports {
+				port {
+					ddr_funnel1_out: endpoint {
+						remote-endpoint = <&ddr_funnel0_in6>;
+					};
+				};
+			};
 		};
 
 		apps_smmu: iommu@15000000 {
@@ -6111,146 +8290,9 @@
 			interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
 		};
 
-		remoteproc_adsp: remoteproc@30000000 {
-			compatible = "qcom,x1e80100-adsp-pas";
-			reg = <0 0x30000000 0 0x100>;
-
-			interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>,
-					      <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
-					      <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
-					      <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
-					      <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>;
-			interrupt-names = "wdog",
-					  "fatal",
-					  "ready",
-					  "handover",
-					  "stop-ack";
-
-			clocks = <&rpmhcc RPMH_CXO_CLK>;
-			clock-names = "xo";
-
-			power-domains = <&rpmhpd RPMHPD_LCX>,
-					<&rpmhpd RPMHPD_LMX>;
-			power-domain-names = "lcx",
-					     "lmx";
-
-			interconnects = <&lpass_lpicx_noc MASTER_LPASS_PROC QCOM_ICC_TAG_ALWAYS
-					 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
-
-			memory-region = <&adspslpi_mem>,
-					<&q6_adsp_dtb_mem>;
-
-			qcom,qmp = <&aoss_qmp>;
-
-			qcom,smem-states = <&smp2p_adsp_out 0>;
-			qcom,smem-state-names = "stop";
-
-			status = "disabled";
-
-			glink-edge {
-				interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
-							     IPCC_MPROC_SIGNAL_GLINK_QMP
-							     IRQ_TYPE_EDGE_RISING>;
-				mboxes = <&ipcc IPCC_CLIENT_LPASS
-						IPCC_MPROC_SIGNAL_GLINK_QMP>;
-
-				label = "lpass";
-				qcom,remote-pid = <2>;
-
-				fastrpc {
-					compatible = "qcom,fastrpc";
-					qcom,glink-channels = "fastrpcglink-apps-dsp";
-					label = "adsp";
-					qcom,non-secure-domain;
-					#address-cells = <1>;
-					#size-cells = <0>;
-
-					compute-cb@3 {
-						compatible = "qcom,fastrpc-compute-cb";
-						reg = <3>;
-						iommus = <&apps_smmu 0x1003 0x80>,
-							 <&apps_smmu 0x1063 0x0>;
-						dma-coherent;
-					};
-
-					compute-cb@4 {
-						compatible = "qcom,fastrpc-compute-cb";
-						reg = <4>;
-						iommus = <&apps_smmu 0x1004 0x80>,
-							 <&apps_smmu 0x1064 0x0>;
-						dma-coherent;
-					};
-
-					compute-cb@5 {
-						compatible = "qcom,fastrpc-compute-cb";
-						reg = <5>;
-						iommus = <&apps_smmu 0x1005 0x80>,
-							 <&apps_smmu 0x1065 0x0>;
-						dma-coherent;
-					};
-
-					compute-cb@6 {
-						compatible = "qcom,fastrpc-compute-cb";
-						reg = <6>;
-						iommus = <&apps_smmu 0x1006 0x80>,
-							 <&apps_smmu 0x1066 0x0>;
-						dma-coherent;
-					};
-
-					compute-cb@7 {
-						compatible = "qcom,fastrpc-compute-cb";
-						reg = <7>;
-						iommus = <&apps_smmu 0x1007 0x80>,
-							 <&apps_smmu 0x1067 0x0>;
-						dma-coherent;
-					};
-				};
-
-				gpr {
-					compatible = "qcom,gpr";
-					qcom,glink-channels = "adsp_apps";
-					qcom,domain = <GPR_DOMAIN_ID_ADSP>;
-					qcom,intents = <512 20>;
-					#address-cells = <1>;
-					#size-cells = <0>;
-
-					q6apm: service@1 {
-						compatible = "qcom,q6apm";
-						reg = <GPR_APM_MODULE_IID>;
-						#sound-dai-cells = <0>;
-						qcom,protection-domain = "avs/audio",
-									 "msm/adsp/audio_pd";
-
-						q6apmbedai: bedais {
-							compatible = "qcom,q6apm-lpass-dais";
-							#sound-dai-cells = <1>;
-						};
-
-						q6apmdai: dais {
-							compatible = "qcom,q6apm-dais";
-							iommus = <&apps_smmu 0x1001 0x80>,
-								 <&apps_smmu 0x1061 0x0>;
-						};
-					};
-
-					q6prm: service@2 {
-						compatible = "qcom,q6prm";
-						reg = <GPR_PRM_MODULE_IID>;
-						qcom,protection-domain = "avs/audio",
-									 "msm/adsp/audio_pd";
-
-						q6prmcc: clock-controller {
-							compatible = "qcom,q6prm-lpass-clocks";
-							#clock-cells = <2>;
-						};
-					};
-				};
-			};
-		};
-
 		remoteproc_cdsp: remoteproc@32300000 {
 			compatible = "qcom,x1e80100-cdsp-pas";
-			reg = <0 0x32300000 0 0x1400000>;
+			reg = <0x0 0x32300000 0x0 0x10000>;
 
 			interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
 					      <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>,
diff --git a/dts/upstream/src/arm64/renesas/r8a779a0-falcon-ethernet.dtsi b/dts/upstream/src/arm64/renesas/r8a779a0-falcon-ethernet.dtsi
index e11bf9ace77..2a8537e1387 100644
--- a/dts/upstream/src/arm64/renesas/r8a779a0-falcon-ethernet.dtsi
+++ b/dts/upstream/src/arm64/renesas/r8a779a0-falcon-ethernet.dtsi
@@ -5,6 +5,121 @@
  * Copyright (C) 2021 Glider bv
  */
 
+/ {
+	aliases {
+		ethernet1 = &avb1;
+		ethernet2 = &avb2;
+		ethernet3 = &avb3;
+		ethernet4 = &avb4;
+		ethernet5 = &avb5;
+	};
+};
+
+&avb1 {
+	pinctrl-0 = <&avb1_pins>;
+	pinctrl-names = "default";
+	phy-handle = <&avb1_phy>;
+	status = "okay";
+
+	mdio {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		reset-gpios = <&gpio5 15 GPIO_ACTIVE_LOW>;
+		reset-post-delay-us = <4000>;
+
+		avb1_phy: ethernet-phy@7 {
+			compatible = "ethernet-phy-ieee802.3-c45";
+			reg = <7>;
+			interrupts-extended = <&gpio5 16 IRQ_TYPE_LEVEL_LOW>;
+		};
+	};
+};
+
+&avb2 {
+	pinctrl-0 = <&avb2_pins>;
+	pinctrl-names = "default";
+	phy-handle = <&avb2_phy>;
+	status = "okay";
+
+	mdio {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		reset-gpios = <&gpio6 15 GPIO_ACTIVE_LOW>;
+		reset-post-delay-us = <4000>;
+
+		avb2_phy: ethernet-phy@7 {
+			compatible = "ethernet-phy-ieee802.3-c45";
+			reg = <7>;
+			interrupts-extended = <&gpio6 16 IRQ_TYPE_LEVEL_LOW>;
+		};
+	};
+};
+
+&avb3 {
+	pinctrl-0 = <&avb3_pins>;
+	pinctrl-names = "default";
+	phy-handle = <&avb3_phy>;
+	status = "okay";
+
+	mdio {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		reset-gpios = <&gpio7 15 GPIO_ACTIVE_LOW>;
+		reset-post-delay-us = <4000>;
+
+		avb3_phy: ethernet-phy@7 {
+			compatible = "ethernet-phy-ieee802.3-c45";
+			reg = <7>;
+			interrupts-extended = <&gpio7 16 IRQ_TYPE_LEVEL_LOW>;
+		};
+	};
+};
+
+&avb4 {
+	pinctrl-0 = <&avb4_pins>;
+	pinctrl-names = "default";
+	phy-handle = <&avb4_phy>;
+	status = "okay";
+
+	mdio {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		reset-gpios = <&gpio8 15 GPIO_ACTIVE_LOW>;
+		reset-post-delay-us = <4000>;
+
+		avb4_phy: ethernet-phy@7 {
+			compatible = "ethernet-phy-ieee802.3-c45";
+			reg = <7>;
+			interrupts-extended = <&gpio8 16 IRQ_TYPE_LEVEL_LOW>;
+		};
+	};
+};
+
+&avb5 {
+	pinctrl-0 = <&avb5_pins>;
+	pinctrl-names = "default";
+	phy-handle = <&avb5_phy>;
+	status = "okay";
+
+	mdio {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		reset-gpios = <&gpio9 15 GPIO_ACTIVE_LOW>;
+		reset-post-delay-us = <4000>;
+
+		avb5_phy: ethernet-phy@7 {
+			compatible = "ethernet-phy-ieee802.3-c45";
+			reg = <7>;
+			interrupts-extended = <&gpio9 16 IRQ_TYPE_LEVEL_LOW>;
+		};
+	};
+};
+
 &i2c0 {
 	eeprom@53 {
 		compatible = "rohm,br24g01", "atmel,24c01";
@@ -13,3 +128,130 @@
 		pagesize = <8>;
 	};
 };
+
+&pfc {
+	avb1_pins: avb1 {
+		mux {
+			groups = "avb1_link", "avb1_mdio", "avb1_rgmii",
+				 "avb1_txcrefclk";
+			function = "avb1";
+		};
+
+		link {
+			groups = "avb1_link";
+			bias-disable;
+		};
+
+		mdio {
+			groups = "avb1_mdio";
+			drive-strength = <24>;
+			bias-disable;
+		};
+
+		rgmii {
+			groups = "avb1_rgmii";
+			drive-strength = <24>;
+			bias-disable;
+		};
+	};
+
+	avb2_pins: avb2 {
+		mux {
+			groups = "avb2_link", "avb2_mdio", "avb2_rgmii",
+				 "avb2_txcrefclk";
+			function = "avb2";
+		};
+
+		link {
+			groups = "avb2_link";
+			bias-disable;
+		};
+
+		mdio {
+			groups = "avb2_mdio";
+			drive-strength = <24>;
+			bias-disable;
+		};
+
+		rgmii {
+			groups = "avb2_rgmii";
+			drive-strength = <24>;
+			bias-disable;
+		};
+	};
+
+	avb3_pins: avb3 {
+		mux {
+			groups = "avb3_link", "avb3_mdio", "avb3_rgmii",
+				 "avb3_txcrefclk";
+			function = "avb3";
+		};
+
+		link {
+			groups = "avb3_link";
+			bias-disable;
+		};
+
+		mdio {
+			groups = "avb3_mdio";
+			drive-strength = <24>;
+			bias-disable;
+		};
+
+		rgmii {
+			groups = "avb3_rgmii";
+			drive-strength = <24>;
+			bias-disable;
+		};
+	};
+
+	avb4_pins: avb4 {
+		mux {
+			groups = "avb4_link", "avb4_mdio", "avb4_rgmii",
+				 "avb4_txcrefclk";
+			function = "avb4";
+		};
+
+		link {
+			groups = "avb4_link";
+			bias-disable;
+		};
+
+		mdio {
+			groups = "avb4_mdio";
+			drive-strength = <24>;
+			bias-disable;
+		};
+
+		rgmii {
+			groups = "avb4_rgmii";
+			drive-strength = <24>;
+			bias-disable;
+		};
+	};
+
+	avb5_pins: avb5 {
+		mux {
+			groups = "avb5_link", "avb5_mdio", "avb5_rgmii",
+				 "avb5_txcrefclk";
+			function = "avb5";
+		};
+
+		link {
+			groups = "avb5_link";
+			bias-disable;
+		};
+
+		mdio {
+			groups = "avb5_mdio";
+			drive-strength = <24>;
+			bias-disable;
+		};
+
+		rgmii {
+			groups = "avb5_rgmii";
+			drive-strength = <24>;
+			bias-disable;
+		};
+	};
+};
diff --git a/dts/upstream/src/arm64/renesas/r8a779a0.dtsi b/dts/upstream/src/arm64/renesas/r8a779a0.dtsi
index 7156b1a542e..fe6d97859e4 100644
--- a/dts/upstream/src/arm64/renesas/r8a779a0.dtsi
+++ b/dts/upstream/src/arm64/renesas/r8a779a0.dtsi
@@ -765,8 +765,6 @@
 			rx-internal-delay-ps = <0>;
 			tx-internal-delay-ps = <0>;
 			iommus = <&ipmmu_ds1 1>;
-			#address-cells = <1>;
-			#size-cells = <0>;
 			status = "disabled";
 		};
 
@@ -814,8 +812,6 @@
 			rx-internal-delay-ps = <0>;
 			tx-internal-delay-ps = <0>;
 			iommus = <&ipmmu_ds1 2>;
-			#address-cells = <1>;
-			#size-cells = <0>;
 			status = "disabled";
 		};
 
@@ -863,8 +859,6 @@
 			rx-internal-delay-ps = <0>;
 			tx-internal-delay-ps = <0>;
 			iommus = <&ipmmu_ds1 3>;
-			#address-cells = <1>;
-			#size-cells = <0>;
 			status = "disabled";
 		};
 
@@ -912,8 +906,6 @@
 			rx-internal-delay-ps = <0>;
 			tx-internal-delay-ps = <0>;
 			iommus = <&ipmmu_ds1 4>;
-			#address-cells = <1>;
-			#size-cells = <0>;
 			status = "disabled";
 		};
 
@@ -961,8 +953,6 @@
 			rx-internal-delay-ps = <0>;
 			tx-internal-delay-ps = <0>;
 			iommus = <&ipmmu_ds1 11>;
-			#address-cells = <1>;
-			#size-cells = <0>;
 			status = "disabled";
 		};
 
diff --git a/dts/upstream/src/arm64/renesas/r8a779g0.dtsi b/dts/upstream/src/arm64/renesas/r8a779g0.dtsi
index 61c6b8022ff..104f740d20d 100644
--- a/dts/upstream/src/arm64/renesas/r8a779g0.dtsi
+++ b/dts/upstream/src/arm64/renesas/r8a779g0.dtsi
@@ -2453,6 +2453,46 @@
 			};
 		};
 
+		fcpvx0: fcp@fedb0000 {
+			compatible = "renesas,fcpv";
+			reg = <0 0xfedb0000 0 0x200>;
+			clocks = <&cpg CPG_MOD 1100>;
+			power-domains = <&sysc R8A779G0_PD_A3ISP0>;
+			resets = <&cpg 1100>;
+			iommus = <&ipmmu_vi1 24>;
+		};
+
+		fcpvx1: fcp@fedb8000 {
+			compatible = "renesas,fcpv";
+			reg = <0 0xfedb8000 0 0x200>;
+			clocks = <&cpg CPG_MOD 1101>;
+			power-domains = <&sysc R8A779G0_PD_A3ISP1>;
+			resets = <&cpg 1101>;
+			iommus = <&ipmmu_vi1 25>;
+		};
+
+		vspx0: vsp@fedd0000 {
+			compatible = "renesas,vsp2";
+			reg = <0 0xfedd0000 0 0x8000>;
+			interrupts = <GIC_SPI 556 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 1028>;
+			power-domains = <&sysc R8A779G0_PD_A3ISP0>;
+			resets = <&cpg 1028>;
+
+			renesas,fcp = <&fcpvx0>;
+		};
+
+		vspx1: vsp@fedd8000 {
+			compatible = "renesas,vsp2";
+			reg = <0 0xfedd8000 0 0x8000>;
+			interrupts = <GIC_SPI 557 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 1029>;
+			power-domains = <&sysc R8A779G0_PD_A3ISP1>;
+			resets = <&cpg 1029>;
+
+			renesas,fcp = <&fcpvx1>;
+		};
+
 		prr: chipid@fff00044 {
 			compatible = "renesas,prr";
 			reg = <0 0xfff00044 0 4>;
diff --git a/dts/upstream/src/arm64/renesas/r8a779g2-white-hawk-single.dts b/dts/upstream/src/arm64/renesas/r8a779g2-white-hawk-single.dts
index 0062362b0ba..48befde3893 100644
--- a/dts/upstream/src/arm64/renesas/r8a779g2-white-hawk-single.dts
+++ b/dts/upstream/src/arm64/renesas/r8a779g2-white-hawk-single.dts
@@ -7,70 +7,10 @@
 
 /dts-v1/;
 #include "r8a779g2.dtsi"
-#include "white-hawk-cpu-common.dtsi"
-#include "white-hawk-common.dtsi"
+#include "white-hawk-single.dtsi"
 
 / {
 	model = "Renesas White Hawk Single board based on r8a779g2";
 	compatible = "renesas,white-hawk-single", "renesas,r8a779g2",
 		     "renesas,r8a779g0";
 };
-
-&hscif0 {
-	uart-has-rtscts;
-};
-
-&hscif0_pins {
-	groups = "hscif0_data", "hscif0_ctrl";
-	function = "hscif0";
-};
-
-&pfc {
-	tsn0_pins: tsn0 {
-		mux {
-			groups = "tsn0_link", "tsn0_mdio", "tsn0_rgmii",
-				 "tsn0_txcrefclk";
-			function = "tsn0";
-		};
-
-		link {
-			groups = "tsn0_link";
-			bias-disable;
-		};
-
-		mdio {
-			groups = "tsn0_mdio";
-			drive-strength = <24>;
-			bias-disable;
-		};
-
-		rgmii {
-			groups = "tsn0_rgmii";
-			drive-strength = <24>;
-			bias-disable;
-		};
-	};
-};
-
-&tsn0 {
-	pinctrl-0 = <&tsn0_pins>;
-	pinctrl-names = "default";
-	phy-mode = "rgmii";
-	phy-handle = <&phy3>;
-	status = "okay";
-
-	mdio {
-		#address-cells = <1>;
-		#size-cells = <0>;
-
-		reset-gpios = <&gpio1 23 GPIO_ACTIVE_LOW>;
-		reset-post-delay-us = <4000>;
-
-		phy3: ethernet-phy@0 {
-			compatible = "ethernet-phy-id002b.0980",
-				     "ethernet-phy-ieee802.3-c22";
-			reg = <0>;
-			interrupts-extended = <&gpio4 3 IRQ_TYPE_LEVEL_LOW>;
-		};
-	};
-};
diff --git a/dts/upstream/src/arm64/renesas/r8a779g3-white-hawk-single.dts b/dts/upstream/src/arm64/renesas/r8a779g3-white-hawk-single.dts
new file mode 100644
index 00000000000..cd466d85885
--- /dev/null
+++ b/dts/upstream/src/arm64/renesas/r8a779g3-white-hawk-single.dts
@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Device Tree Source for the R-Car V4H ES3.0 White Hawk Single board
+ *
+ * Copyright (C) 2024 Glider bv
+ */
+
+/dts-v1/;
+#include "r8a779g3.dtsi"
+#include "white-hawk-single.dtsi"
+
+/ {
+	model = "Renesas White Hawk Single board based on r8a779g3";
+	compatible = "renesas,white-hawk-single", "renesas,r8a779g3",
+		     "renesas,r8a779g0";
+};
diff --git a/dts/upstream/src/arm64/renesas/r8a779g3.dtsi b/dts/upstream/src/arm64/renesas/r8a779g3.dtsi
new file mode 100644
index 00000000000..0295858a026
--- /dev/null
+++ b/dts/upstream/src/arm64/renesas/r8a779g3.dtsi
@@ -0,0 +1,12 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Device Tree Source for the R-Car V4H (R8A779G3) SoC
+ *
+ * Copyright (C) 2024 Glider bv
+ */
+
+#include "r8a779g0.dtsi"
+
+/ {
+	compatible = "renesas,r8a779g3", "renesas,r8a779g0";
+};
diff --git a/dts/upstream/src/arm64/renesas/r8a779h0-gray-hawk-single.dts b/dts/upstream/src/arm64/renesas/r8a779h0-gray-hawk-single.dts
index 58eabcc7e0e..18fd52f55de 100644
--- a/dts/upstream/src/arm64/renesas/r8a779h0-gray-hawk-single.dts
+++ b/dts/upstream/src/arm64/renesas/r8a779h0-gray-hawk-single.dts
@@ -30,6 +30,7 @@
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
 #include <dt-bindings/leds/common.h>
+#include <dt-bindings/media/video-interfaces.h>
 
 #include "r8a779h0.dtsi"
 
@@ -59,6 +60,12 @@
 		stdout-path = "serial0:921600n8";
 	};
 
+	sn65dsi86_refclk: clk-x6 {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <38400000>;
+	};
+
 	keys {
 		compatible = "gpio-keys";
 
@@ -132,22 +139,43 @@
 		#clock-cells = <0>;
 	};
 
+	mini-dp-con {
+		compatible = "dp-connector";
+		label = "CN5";
+		type = "mini";
+
+		port {
+			mini_dp_con_in: endpoint {
+				remote-endpoint = <&sn65dsi86_out0>;
+			};
+		};
+	};
+
+	reg_1p2v: regulator-1p2v {
+		compatible = "regulator-fixed";
+		regulator-name = "fixed-1.2V";
+		regulator-min-microvolt = <1200000>;
+		regulator-max-microvolt = <1200000>;
+		regulator-boot-on;
+		regulator-always-on;
+	};
+
 	reg_1p8v: regulator-1p8v {
-			compatible = "regulator-fixed";
-			regulator-name = "fixed-1.8V";
-			regulator-min-microvolt = <1800000>;
-			regulator-max-microvolt = <1800000>;
-			regulator-boot-on;
-			regulator-always-on;
+		compatible = "regulator-fixed";
+		regulator-name = "fixed-1.8V";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+		regulator-boot-on;
+		regulator-always-on;
 	};
 
 	reg_3p3v: regulator-3p3v {
-			compatible = "regulator-fixed";
-			regulator-name = "fixed-3.3V";
-			regulator-min-microvolt = <3300000>;
-			regulator-max-microvolt = <3300000>;
-			regulator-boot-on;
-			regulator-always-on;
+		compatible = "regulator-fixed";
+		regulator-name = "fixed-3.3V";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-boot-on;
+		regulator-always-on;
 	};
 
 	sound_mux: sound-mux {
@@ -205,6 +233,65 @@
 	};
 };
 
+&dsi0 {
+	status = "okay";
+
+	ports {
+		port@1 {
+			reg = <1>;
+
+			dsi0_out: endpoint {
+				remote-endpoint = <&sn65dsi86_in0>;
+				data-lanes = <1 2 3 4>;
+			};
+		};
+	};
+};
+
+&du {
+	status = "okay";
+};
+
+&csi40 {
+	status = "okay";
+
+	ports {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		port@0 {
+			reg = <0>;
+
+			csi40_in: endpoint {
+				bus-type = <MEDIA_BUS_TYPE_CSI2_DPHY>;
+				clock-lanes = <0>;
+				data-lanes = <1 2 3 4>;
+				remote-endpoint = <&max96724_out0>;
+			};
+		};
+	};
+};
+
+&csi41 {
+	status = "okay";
+
+	ports {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		port@0 {
+			reg = <0>;
+
+			csi41_in: endpoint {
+				bus-type = <MEDIA_BUS_TYPE_CSI2_DPHY>;
+				clock-lanes = <0>;
+				data-lanes = <1 2 3 4>;
+				remote-endpoint = <&max96724_out1>;
+			};
+		};
+	};
+};
+
 &extal_clk {
 	clock-frequency = <16666666>;
 };
@@ -255,6 +342,20 @@
 		#interrupt-cells = <2>;
 	};
 
+	io_expander_b: gpio@21 {
+		compatible = "onnn,pca9654";
+		reg = <0x21>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	io_expander_c: gpio@22 {
+		compatible = "onnn,pca9654";
+		reg = <0x22>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
 	eeprom@50 {
 		compatible = "rohm,br24g01", "atmel,24c01";
 		label = "cpu-board";
@@ -284,6 +385,97 @@
 	};
 };
 
+&i2c1 {
+	pinctrl-0 = <&i2c1_pins>;
+	pinctrl-names = "default";
+
+	status = "okay";
+	clock-frequency = <400000>;
+
+	bridge@2c {
+		pinctrl-0 = <&irq0_pins>;
+		pinctrl-names = "default";
+
+		compatible = "ti,sn65dsi86";
+		reg = <0x2c>;
+
+		clocks = <&sn65dsi86_refclk>;
+		clock-names = "refclk";
+
+		interrupts-extended = <&intc_ex 0 IRQ_TYPE_LEVEL_HIGH>;
+
+		enable-gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>;
+
+		vccio-supply = <&reg_1p8v>;
+		vpll-supply = <&reg_1p8v>;
+		vcca-supply = <&reg_1p2v>;
+		vcc-supply = <&reg_1p2v>;
+
+		ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@0 {
+				reg = <0>;
+
+				sn65dsi86_in0: endpoint {
+					remote-endpoint = <&dsi0_out>;
+				};
+			};
+
+			port@1 {
+				reg = <1>;
+
+				sn65dsi86_out0: endpoint {
+					remote-endpoint = <&mini_dp_con_in>;
+				};
+			};
+		};
+	};
+
+	gmsl0: gmsl-deserializer@4e {
+		compatible = "maxim,max96724";
+		reg = <0x4e>;
+		enable-gpios = <&io_expander_b 0 GPIO_ACTIVE_HIGH>;
+
+		ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@4 {
+				reg = <4>;
+				max96724_out0: endpoint {
+					bus-type = <MEDIA_BUS_TYPE_CSI2_DPHY>;
+					clock-lanes = <0>;
+					data-lanes = <1 2 3 4>;
+					remote-endpoint = <&csi40_in>;
+				};
+			};
+		};
+	};
+
+	gmsl1: gmsl-deserializer@4f {
+		compatible = "maxim,max96724";
+		reg = <0x4f>;
+		enable-gpios = <&io_expander_c 0 GPIO_ACTIVE_HIGH>;
+
+		ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@4 {
+				reg = <4>;
+				max96724_out1: endpoint {
+					bus-type = <MEDIA_BUS_TYPE_CSI2_DPHY>;
+					clock-lanes = <0>;
+					data-lanes = <1 2 3 4>;
+					remote-endpoint = <&csi41_in>;
+				};
+			};
+		};
+	};
+};
+
 &i2c3 {
 	pinctrl-0 = <&i2c3_pins>;
 	pinctrl-names = "default";
@@ -307,6 +499,14 @@
 	};
 };
 
+&isp0 {
+	status = "okay";
+};
+
+&isp1 {
+	status = "okay";
+};
+
 &mmc0 {
 	pinctrl-0 = <&mmc_pins>;
 	pinctrl-1 = <&mmc_pins>;
@@ -388,11 +588,21 @@
 		function = "i2c0";
 	};
 
+	i2c1_pins: i2c1 {
+		groups = "i2c1";
+		function = "i2c1";
+	};
+
 	i2c3_pins: i2c3 {
 		groups = "i2c3";
 		function = "i2c3";
 	};
 
+	irq0_pins: irq0_pins {
+		groups = "intc_ex_irq0_a";
+		function = "intc_ex";
+	};
+
 	keys_pins: keys {
 		pins = "GP_5_0", "GP_5_1", "GP_5_2";
 		bias-pull-up;
@@ -494,3 +704,67 @@
 &scif_clk2 {
 	clock-frequency = <24000000>;
 };
+
+&vin00 {
+	status = "okay";
+};
+
+&vin01 {
+	status = "okay";
+};
+
+&vin02 {
+	status = "okay";
+};
+
+&vin03 {
+	status = "okay";
+};
+
+&vin04 {
+	status = "okay";
+};
+
+&vin05 {
+	status = "okay";
+};
+
+&vin06 {
+	status = "okay";
+};
+
+&vin07 {
+	status = "okay";
+};
+
+&vin08 {
+	status = "okay";
+};
+
+&vin09 {
+	status = "okay";
+};
+
+&vin10 {
+	status = "okay";
+};
+
+&vin11 {
+	status = "okay";
+};
+
+&vin12 {
+	status = "okay";
+};
+
+&vin13 {
+	status = "okay";
+};
+
+&vin14 {
+	status = "okay";
+};
+
+&vin15 {
+	status = "okay";
+};
diff --git a/dts/upstream/src/arm64/renesas/r8a779h0.dtsi b/dts/upstream/src/arm64/renesas/r8a779h0.dtsi
index facfff4b9cd..d0c01c0fdda 100644
--- a/dts/upstream/src/arm64/renesas/r8a779h0.dtsi
+++ b/dts/upstream/src/arm64/renesas/r8a779h0.dtsi
@@ -1900,6 +1900,50 @@
 			};
 		};
 
+		fcpvd0: fcp@fea10000 {
+			compatible = "renesas,fcpv";
+			reg = <0 0xfea10000 0 0x200>;
+			clocks = <&cpg CPG_MOD 508>;
+			power-domains = <&sysc R8A779H0_PD_C4>;
+			resets = <&cpg 508>;
+		};
+
+		vspd0: vsp@fea20000 {
+			compatible = "renesas,vsp2";
+			reg = <0 0xfea20000 0 0x8000>;
+			interrupts = <GIC_SPI 546 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 830>;
+			power-domains = <&sysc R8A779H0_PD_C4>;
+			resets = <&cpg 830>;
+			renesas,fcp = <&fcpvd0>;
+		};
+
+		du: display@feb00000 {
+			compatible = "renesas,du-r8a779h0";
+			reg = <0 0xfeb00000 0 0x40000>;
+			interrupts = <GIC_SPI 523 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 411>;
+			clock-names = "du.0";
+			power-domains = <&sysc R8A779H0_PD_C4>;
+			resets = <&cpg 411>;
+			reset-names = "du.0";
+			renesas,vsps = <&vspd0 0>;
+
+			status = "disabled";
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					reg = <0>;
+					du_out_dsi0: endpoint {
+						remote-endpoint = <&dsi0_in>;
+					};
+				};
+			};
+		};
+
 		isp0: isp@fed00000 {
 			compatible = "renesas,r8a779h0-isp",
 				     "renesas,rcar-gen4-isp";
@@ -2068,6 +2112,35 @@
 			};
 		};
 
+		dsi0: dsi-encoder@fed80000 {
+			compatible = "renesas,r8a779h0-dsi-csi2-tx";
+			reg = <0 0xfed80000 0 0x10000>;
+			clocks = <&cpg CPG_MOD 415>,
+				 <&cpg CPG_CORE R8A779H0_CLK_DSIEXT>,
+				 <&cpg CPG_CORE R8A779H0_CLK_DSIREF>;
+			clock-names = "fck", "dsi", "pll";
+			power-domains = <&sysc R8A779H0_PD_C4>;
+			resets = <&cpg 415>;
+
+			status = "disabled";
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					reg = <0>;
+					dsi0_in: endpoint {
+						remote-endpoint = <&du_out_dsi0>;
+					};
+				};
+
+				port@1 {
+					reg = <1>;
+				};
+			};
+		};
+
 		prr: chipid@fff00044 {
 			compatible = "renesas,prr";
 			reg = <0 0xfff00044 0 4>;
diff --git a/dts/upstream/src/arm64/renesas/r9a08g045.dtsi b/dts/upstream/src/arm64/renesas/r9a08g045.dtsi
index be8a0a768c6..a9b98db9ef9 100644
--- a/dts/upstream/src/arm64/renesas/r9a08g045.dtsi
+++ b/dts/upstream/src/arm64/renesas/r9a08g045.dtsi
@@ -14,6 +14,20 @@
 	#address-cells = <2>;
 	#size-cells = <2>;
 
+	audio_clk1: audio1-clk {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		/* This value must be overridden by boards that provide it. */
+		clock-frequency = <0>;
+	};
+
+	audio_clk2: audio2-clk {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		/* This value must be overridden by boards that provide it. */
+		clock-frequency = <0>;
+	};
+
 	cpus {
 		#address-cells = <1>;
 		#size-cells = <0>;
@@ -73,6 +87,96 @@
 			status = "disabled";
 		};
 
+		scif1: serial@1004bc00 {
+			compatible = "renesas,scif-r9a08g045", "renesas,scif-r9a07g044";
+			reg = <0 0x1004bc00 0 0x400>;
+			interrupts = <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "eri", "rxi", "txi",
+					  "bri", "dri", "tei";
+			clocks = <&cpg CPG_MOD R9A08G045_SCIF1_CLK_PCK>;
+			clock-names = "fck";
+			power-domains = <&cpg>;
+			resets = <&cpg R9A08G045_SCIF1_RST_SYSTEM_N>;
+			status = "disabled";
+		};
+
+		scif2: serial@1004c000 {
+			compatible = "renesas,scif-r9a08g045", "renesas,scif-r9a07g044";
+			reg = <0 0x1004c000 0 0x400>;
+			interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "eri", "rxi", "txi",
+					  "bri", "dri", "tei";
+			clocks = <&cpg CPG_MOD R9A08G045_SCIF2_CLK_PCK>;
+			clock-names = "fck";
+			power-domains = <&cpg>;
+			resets = <&cpg R9A08G045_SCIF2_RST_SYSTEM_N>;
+			status = "disabled";
+		};
+
+		scif3: serial@1004c400 {
+			compatible = "renesas,scif-r9a08g045", "renesas,scif-r9a07g044";
+			reg = <0 0x1004c400 0 0x400>;
+			interrupts = <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "eri", "rxi", "txi",
+					  "bri", "dri", "tei";
+			clocks = <&cpg CPG_MOD R9A08G045_SCIF3_CLK_PCK>;
+			clock-names = "fck";
+			power-domains = <&cpg>;
+			resets = <&cpg R9A08G045_SCIF3_RST_SYSTEM_N>;
+			status = "disabled";
+		};
+
+		scif4: serial@1004c800 {
+			compatible = "renesas,scif-r9a08g045", "renesas,scif-r9a07g044";
+			reg = <0 0x1004c800 0 0x400>;
+			interrupts = <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "eri", "rxi", "txi",
+					  "bri", "dri", "tei";
+			clocks = <&cpg CPG_MOD R9A08G045_SCIF4_CLK_PCK>;
+			clock-names = "fck";
+			power-domains = <&cpg>;
+			resets = <&cpg R9A08G045_SCIF4_RST_SYSTEM_N>;
+			status = "disabled";
+		};
+
+		scif5: serial@1004e000 {
+			compatible = "renesas,scif-r9a08g045", "renesas,scif-r9a07g044";
+			reg = <0 0x1004e000 0 0x400>;
+			interrupts = <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "eri", "rxi", "txi",
+					  "bri", "dri", "tei";
+			clocks = <&cpg CPG_MOD R9A08G045_SCIF5_CLK_PCK>;
+			clock-names = "fck";
+			power-domains = <&cpg>;
+			resets = <&cpg R9A08G045_SCIF5_RST_SYSTEM_N>;
+			status = "disabled";
+		};
+
 		rtc: rtc@1004ec00 {
 			compatible = "renesas,r9a08g045-rtca3", "renesas,rz-rtca3";
 			reg = <0 0x1004ec00 0 0x400>;
@@ -87,6 +191,59 @@
 			status = "disabled";
 		};
 
+		adc: adc@10058000 {
+			compatible = "renesas,r9a08g045-adc";
+			reg = <0 0x10058000 0 0x1000>;
+			interrupts = <GIC_SPI 312 IRQ_TYPE_EDGE_RISING>;
+			clocks = <&cpg CPG_MOD R9A08G045_ADC_ADCLK>,
+				 <&cpg CPG_MOD R9A08G045_ADC_PCLK>;
+			clock-names = "adclk", "pclk";
+			resets = <&cpg R9A08G045_ADC_PRESETN>,
+				 <&cpg R9A08G045_ADC_ADRST_N>;
+			reset-names = "presetn", "adrst-n";
+			power-domains = <&cpg>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			#io-channel-cells = <1>;
+			status = "disabled";
+
+			channel@0 {
+				reg = <0>;
+			};
+
+			channel@1 {
+				reg = <1>;
+			};
+
+			channel@2 {
+				reg = <2>;
+			};
+
+			channel@3 {
+				reg = <3>;
+			};
+
+			channel@4 {
+				reg = <4>;
+			};
+
+			channel@5 {
+				reg = <5>;
+			};
+
+			channel@6 {
+				reg = <6>;
+			};
+
+			channel@7 {
+				reg = <7>;
+			};
+
+			channel@8 {
+				reg = <8>;
+			};
+		};
+
 		vbattb: clock-controller@1005c000 {
 			compatible = "renesas,r9a08g045-vbattb";
 			reg = <0 0x1005c000 0 0x1000>;
@@ -187,6 +344,86 @@
 			status = "disabled";
 		};
 
+		ssi0: ssi@100a8000 {
+			compatible = "renesas,r9a08g045-ssi",
+				     "renesas,rz-ssi";
+			reg = <0 0x100a8000 0 0x400>;
+			interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 241 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 242 IRQ_TYPE_EDGE_RISING>;
+			interrupt-names = "int_req", "dma_rx", "dma_tx";
+			clocks = <&cpg CPG_MOD R9A08G045_SSI0_PCLK2>,
+				 <&cpg CPG_MOD R9A08G045_SSI0_PCLK_SFR>,
+				 <&audio_clk1>, <&audio_clk2>;
+			clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2";
+			resets = <&cpg R9A08G045_SSI0_RST_M2_REG>;
+			dmas = <&dmac 0x2665>, <&dmac 0x2666>;
+			dma-names = "tx", "rx";
+			power-domains = <&cpg>;
+			#sound-dai-cells = <0>;
+			status = "disabled";
+		};
+
+		ssi1: ssi@100a8400 {
+			compatible = "renesas,r9a08g045-ssi",
+				     "renesas,rz-ssi";
+			reg = <0 0x100a8400 0 0x400>;
+			interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 244 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 245 IRQ_TYPE_EDGE_RISING>;
+			interrupt-names = "int_req", "dma_rx", "dma_tx";
+			clocks = <&cpg CPG_MOD R9A08G045_SSI1_PCLK2>,
+				 <&cpg CPG_MOD R9A08G045_SSI1_PCLK_SFR>,
+				 <&audio_clk1>, <&audio_clk2>;
+			clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2";
+			resets = <&cpg R9A08G045_SSI1_RST_M2_REG>;
+			dmas = <&dmac 0x2669>, <&dmac 0x266a>;
+			dma-names = "tx", "rx";
+			power-domains = <&cpg>;
+			#sound-dai-cells = <0>;
+			status = "disabled";
+		};
+
+		ssi2: ssi@100a8800 {
+			compatible = "renesas,r9a08g045-ssi",
+				     "renesas,rz-ssi";
+			reg = <0 0x100a8800 0 0x400>;
+			interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 247 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 248 IRQ_TYPE_EDGE_RISING>;
+			interrupt-names = "int_req", "dma_rx", "dma_tx";
+			clocks = <&cpg CPG_MOD R9A08G045_SSI2_PCLK2>,
+				 <&cpg CPG_MOD R9A08G045_SSI2_PCLK_SFR>,
+				 <&audio_clk1>, <&audio_clk2>;
+			clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2";
+			resets = <&cpg R9A08G045_SSI2_RST_M2_REG>;
+			dmas = <&dmac 0x266d>, <&dmac 0x266e>;
+			dma-names = "tx", "rx";
+			power-domains = <&cpg>;
+			#sound-dai-cells = <0>;
+			status = "disabled";
+		};
+
+		ssi3: ssi@100a8c00 {
+			compatible = "renesas,r9a08g045-ssi",
+				     "renesas,rz-ssi";
+			reg = <0 0x100a8c00 0 0x400>;
+			interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 250 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 251 IRQ_TYPE_EDGE_RISING>;
+			interrupt-names = "int_req", "dma_rx", "dma_tx";
+			clocks = <&cpg CPG_MOD R9A08G045_SSI3_PCLK2>,
+				 <&cpg CPG_MOD R9A08G045_SSI3_PCLK_SFR>,
+				 <&audio_clk1>, <&audio_clk2>;
+			clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2";
+			resets = <&cpg R9A08G045_SSI3_RST_M2_REG>;
+			dmas = <&dmac 0x2671>, <&dmac 0x2672>;
+			dma-names = "tx", "rx";
+			power-domains = <&cpg>;
+			#sound-dai-cells = <0>;
+			status = "disabled";
+		};
+
 		cpg: clock-controller@11010000 {
 			compatible = "renesas,r9a08g045-cpg";
 			reg = <0 0x11010000 0 0x10000>;
diff --git a/dts/upstream/src/arm64/renesas/r9a09g047.dtsi b/dts/upstream/src/arm64/renesas/r9a09g047.dtsi
new file mode 100644
index 00000000000..200e9ea8919
--- /dev/null
+++ b/dts/upstream/src/arm64/renesas/r9a09g047.dtsi
@@ -0,0 +1,387 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Device Tree Source for the RZ/G3E SoC
+ *
+ * Copyright (C) 2024 Renesas Electronics Corp.
+ */
+
+#include <dt-bindings/clock/renesas,r9a09g047-cpg.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+	compatible = "renesas,r9a09g047";
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	audio_extal_clk: audio-clk {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		/* This value must be overridden by the board */
+		clock-frequency = <0>;
+	};
+
+	/*
+	 * The default cluster table is based on the assumption that the PLLCA55 clock
+	 * frequency is set to 1.7GHz. The PLLCA55 clock frequency can be set to
+	 * 1.7/1.6/1.5/1.1 GHz based on the BOOTPLLCA_0/1 pins (and additionally can be
+	 * clocked to 1.8GHz as well). The table below should be overridden in the board
+	 * DTS based on the PLLCA55 clock frequency.
+	 */
+	cluster0_opp: opp-table-0 {
+		compatible = "operating-points-v2";
+
+		opp-1700000000 {
+			opp-hz = /bits/ 64 <1700000000>;
+			opp-microvolt = <900000>;
+			clock-latency-ns = <300000>;
+		};
+		opp-850000000 {
+			opp-hz = /bits/ 64 <850000000>;
+			opp-microvolt = <800000>;
+			clock-latency-ns = <300000>;
+		};
+		opp-425000000 {
+			opp-hz = /bits/ 64 <425000000>;
+			opp-microvolt = <800000>;
+			clock-latency-ns = <300000>;
+		};
+		opp-212500000 {
+			opp-hz = /bits/ 64 <212500000>;
+			opp-microvolt = <800000>;
+			clock-latency-ns = <300000>;
+			opp-suspend;
+		};
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu0: cpu@0 {
+			compatible = "arm,cortex-a55";
+			reg = <0>;
+			device_type = "cpu";
+			next-level-cache = <&L3_CA55>;
+			enable-method = "psci";
+			clocks = <&cpg CPG_CORE R9A09G047_CA55_0_CORECLK0>;
+			operating-points-v2 = <&cluster0_opp>;
+		};
+
+		cpu1: cpu@100 {
+			compatible = "arm,cortex-a55";
+			reg = <0x100>;
+			device_type = "cpu";
+			next-level-cache = <&L3_CA55>;
+			enable-method = "psci";
+			clocks = <&cpg CPG_CORE R9A09G047_CA55_0_CORECLK1>;
+			operating-points-v2 = <&cluster0_opp>;
+		};
+
+		cpu2: cpu@200 {
+			compatible = "arm,cortex-a55";
+			reg = <0x200>;
+			device_type = "cpu";
+			next-level-cache = <&L3_CA55>;
+			enable-method = "psci";
+			clocks = <&cpg CPG_CORE R9A09G047_CA55_0_CORECLK2>;
+			operating-points-v2 = <&cluster0_opp>;
+		};
+
+		cpu3: cpu@300 {
+			compatible = "arm,cortex-a55";
+			reg = <0x300>;
+			device_type = "cpu";
+			next-level-cache = <&L3_CA55>;
+			enable-method = "psci";
+			clocks = <&cpg CPG_CORE R9A09G047_CA55_0_CORECLK3>;
+			operating-points-v2 = <&cluster0_opp>;
+		};
+
+		L3_CA55: cache-controller-0 {
+			compatible = "cache";
+			cache-unified;
+			cache-size = <0x100000>;
+			cache-level = <3>;
+		};
+	};
+
+	psci {
+		compatible = "arm,psci-1.0", "arm,psci-0.2";
+		method = "smc";
+	};
+
+	qextal_clk: qextal-clk {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		/* This value must be overridden by the board */
+		clock-frequency = <0>;
+	};
+
+	rtxin_clk: rtxin-clk {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		/* This value must be overridden by the board */
+		clock-frequency = <0>;
+	};
+
+	soc: soc {
+		compatible = "simple-bus";
+		interrupt-parent = <&gic>;
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		pinctrl: pinctrl@10410000 {
+			compatible = "renesas,r9a09g047-pinctrl";
+			reg = <0 0x10410000 0 0x10000>;
+			clocks = <&cpg CPG_CORE R9A09G047_IOTOP_0_SHCLK>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			gpio-ranges = <&pinctrl 0 0 232>;
+			#interrupt-cells = <2>;
+			interrupt-controller;
+			power-domains = <&cpg>;
+			resets = <&cpg 0xa5>, <&cpg 0xa6>;
+		};
+
+		cpg: clock-controller@10420000 {
+			compatible = "renesas,r9a09g047-cpg";
+			reg = <0 0x10420000 0 0x10000>;
+			clocks = <&audio_extal_clk>, <&rtxin_clk>, <&qextal_clk>;
+			clock-names = "audio_extal", "rtxin", "qextal";
+			#clock-cells = <2>;
+			#reset-cells = <1>;
+			#power-domain-cells = <0>;
+		};
+
+		scif0: serial@11c01400 {
+			compatible = "renesas,scif-r9a09g047", "renesas,scif-r9a09g057";
+			reg = <0 0x11c01400 0 0x400>;
+			interrupts = <GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 532 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 534 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 536 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 537 IRQ_TYPE_EDGE_RISING>;
+			interrupt-names = "eri", "rxi", "txi", "bri", "dri",
+					  "tei", "tei-dri", "rxi-edge", "txi-edge";
+			clocks = <&cpg CPG_MOD 0x8f>;
+			clock-names = "fck";
+			power-domains = <&cpg>;
+			resets = <&cpg 0x95>;
+			status = "disabled";
+		};
+
+		i2c0: i2c@14400400 {
+			compatible = "renesas,riic-r9a09g047", "renesas,riic-r9a09g057";
+			reg = <0 0x14400400 0 0x400>;
+			interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 507 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 506 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "tei", "ri", "ti", "spi", "sti",
+					  "naki", "ali", "tmoi";
+			clocks = <&cpg CPG_MOD 0x94>;
+			resets = <&cpg 0x98>;
+			power-domains = <&cpg>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		i2c1: i2c@14400800 {
+			compatible = "renesas,riic-r9a09g047", "renesas,riic-r9a09g057";
+			reg = <0 0x14400800 0 0x400>;
+			interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 509 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 508 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "tei", "ri", "ti", "spi", "sti",
+					  "naki", "ali", "tmoi";
+			clocks = <&cpg CPG_MOD 0x95>;
+			resets = <&cpg 0x99>;
+			power-domains = <&cpg>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		i2c2: i2c@14400c00 {
+			compatible = "renesas,riic-r9a09g047", "renesas,riic-r9a09g057";
+			reg = <0 0x14400c00 0 0x400>;
+			interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 511 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 510 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "tei", "ri", "ti", "spi", "sti",
+					  "naki", "ali", "tmoi";
+			clocks = <&cpg CPG_MOD 0x96>;
+			resets = <&cpg 0x9a>;
+			power-domains = <&cpg>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		i2c3: i2c@14401000 {
+			compatible = "renesas,riic-r9a09g047", "renesas,riic-r9a09g057";
+			reg = <0 0x14401000 0 0x400>;
+			interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 513 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 512 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "tei", "ri", "ti", "spi", "sti",
+					  "naki", "ali", "tmoi";
+			clocks = <&cpg CPG_MOD 0x97>;
+			resets = <&cpg 0x9b>;
+			power-domains = <&cpg>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		i2c4: i2c@14401400 {
+			compatible = "renesas,riic-r9a09g047", "renesas,riic-r9a09g057";
+			reg = <0 0x14401400 0 0x400>;
+			interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 515 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 514 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "tei", "ri", "ti", "spi", "sti",
+					  "naki", "ali", "tmoi";
+			clocks = <&cpg CPG_MOD 0x98>;
+			resets = <&cpg 0x9c>;
+			power-domains = <&cpg>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		i2c5: i2c@14401800 {
+			compatible = "renesas,riic-r9a09g047", "renesas,riic-r9a09g057";
+			reg = <0 0x14401800 0 0x400>;
+			interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 517 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 516 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "tei", "ri", "ti", "spi", "sti",
+					  "naki", "ali", "tmoi";
+			clocks = <&cpg CPG_MOD 0x99>;
+			resets = <&cpg 0x9d>;
+			power-domains = <&cpg>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		i2c6: i2c@14401c00 {
+			compatible = "renesas,riic-r9a09g047", "renesas,riic-r9a09g057";
+			reg = <0 0x14401c00 0 0x400>;
+			interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 519 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 518 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "tei", "ri", "ti", "spi", "sti",
+					  "naki", "ali", "tmoi";
+			clocks = <&cpg CPG_MOD 0x9a>;
+			resets = <&cpg 0x9e>;
+			power-domains = <&cpg>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		i2c7: i2c@14402000 {
+			compatible = "renesas,riic-r9a09g047", "renesas,riic-r9a09g057";
+			reg = <0 0x14402000 0 0x400>;
+			interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 521 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 520 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "tei", "ri", "ti", "spi", "sti",
+					  "naki", "ali", "tmoi";
+			clocks = <&cpg CPG_MOD 0x9b>;
+			resets = <&cpg 0x9f>;
+			power-domains = <&cpg>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		i2c8: i2c@11c01000 {
+			compatible = "renesas,riic-r9a09g047", "renesas,riic-r9a09g057";
+			reg = <0 0x11c01000 0 0x400>;
+			interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 523 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 522 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "tei", "ri", "ti", "spi", "sti",
+					  "naki", "ali", "tmoi";
+			clocks = <&cpg CPG_MOD 0x93>;
+			resets = <&cpg 0xa0>;
+			power-domains = <&cpg>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		gic: interrupt-controller@14900000 {
+			compatible = "arm,gic-v3";
+			reg = <0x0 0x14900000 0 0x20000>,
+			      <0x0 0x14940000 0 0x80000>;
+			#interrupt-cells = <3>;
+			#address-cells = <0>;
+			interrupt-controller;
+			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
+		};
+	};
+
+	timer {
+		compatible = "arm,armv8-timer";
+		interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
+				      <&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
+				      <&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
+				      <&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>,
+				      <&gic GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>;
+		interrupt-names = "sec-phys", "phys", "virt", "hyp-phys", "hyp-virt";
+	};
+};
diff --git a/dts/upstream/src/arm64/renesas/r9a09g047e37.dtsi b/dts/upstream/src/arm64/renesas/r9a09g047e37.dtsi
new file mode 100644
index 00000000000..e50d9159e83
--- /dev/null
+++ b/dts/upstream/src/arm64/renesas/r9a09g047e37.dtsi
@@ -0,0 +1,18 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Device Tree Source for the RZ/G3E R9A09G047E37 SoC specific parts
+ *
+ * Copyright (C) 2024 Renesas Electronics Corp.
+ */
+
+/dts-v1/;
+#include "r9a09g047.dtsi"
+
+/ {
+	compatible = "renesas,r9a09g047e37", "renesas,r9a09g047";
+
+	cpus {
+		/delete-node/ cpu@200;
+		/delete-node/ cpu@300;
+	};
+};
diff --git a/dts/upstream/src/arm64/renesas/r9a09g047e57-smarc.dts b/dts/upstream/src/arm64/renesas/r9a09g047e57-smarc.dts
new file mode 100644
index 00000000000..c063d47e295
--- /dev/null
+++ b/dts/upstream/src/arm64/renesas/r9a09g047e57-smarc.dts
@@ -0,0 +1,31 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Device Tree Source for the RZ/G3E SMARC EVK board
+ *
+ * Copyright (C) 2024 Renesas Electronics Corp.
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/pinctrl/renesas,r9a09g047-pinctrl.h>
+#include "r9a09g047e57.dtsi"
+#include "rzg3e-smarc-som.dtsi"
+#include "renesas-smarc2.dtsi"
+
+/ {
+	model = "Renesas SMARC EVK version 2 based on r9a09g047e57";
+	compatible = "renesas,smarc2-evk", "renesas,rzg3e-smarcm",
+		     "renesas,r9a09g047e57", "renesas,r9a09g047";
+};
+
+&pinctrl {
+	scif_pins: scif {
+		pins = "SCIF_TXD", "SCIF_RXD";
+		renesas,output-impedance = <1>;
+	};
+};
+
+&scif0 {
+	pinctrl-0 = <&scif_pins>;
+	pinctrl-names = "default";
+};
diff --git a/dts/upstream/src/arm64/renesas/r9a09g047e57.dtsi b/dts/upstream/src/arm64/renesas/r9a09g047e57.dtsi
new file mode 100644
index 00000000000..98a5faebd47
--- /dev/null
+++ b/dts/upstream/src/arm64/renesas/r9a09g047e57.dtsi
@@ -0,0 +1,13 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Device Tree Source for the RZ/G3E R9A09G047E57 SoC specific parts
+ *
+ * Copyright (C) 2024 Renesas Electronics Corp.
+ */
+
+/dts-v1/;
+#include "r9a09g047.dtsi"
+
+/ {
+	compatible = "renesas,r9a09g047e57", "renesas,r9a09g047";
+};
diff --git a/dts/upstream/src/arm64/renesas/r9a09g057h44-rzv2h-evk.dts b/dts/upstream/src/arm64/renesas/r9a09g057h44-rzv2h-evk.dts
index 4703da8e9cf..0b705c987b6 100644
--- a/dts/upstream/src/arm64/renesas/r9a09g057h44-rzv2h-evk.dts
+++ b/dts/upstream/src/arm64/renesas/r9a09g057h44-rzv2h-evk.dts
@@ -7,7 +7,7 @@
 
 /dts-v1/;
 
-#include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
+#include <dt-bindings/pinctrl/renesas,r9a09g057-pinctrl.h>
 #include <dt-bindings/gpio/gpio.h>
 #include "r9a09g057.dtsi"
 
@@ -56,7 +56,7 @@
 	vqmmc_sdhi1: regulator-vccq-sdhi1 {
 		compatible = "regulator-gpio";
 		regulator-name = "SDHI1 VccQ";
-		gpios = <&pinctrl RZG2L_GPIO(10, 2) GPIO_ACTIVE_HIGH>;
+		gpios = <&pinctrl RZV2H_GPIO(A, 2) GPIO_ACTIVE_HIGH>;
 		regulator-min-microvolt = <1800000>;
 		regulator-max-microvolt = <3300000>;
 		gpios-states = <0>;
@@ -158,38 +158,38 @@
 
 &pinctrl {
 	i2c0_pins: i2c0 {
-		pinmux = <RZG2L_PORT_PINMUX(3, 0, 1)>, /* I2C0_SDA */
-			 <RZG2L_PORT_PINMUX(3, 1, 1)>; /* I2C0_SCL */
+		pinmux = <RZV2H_PORT_PINMUX(3, 0, 1)>, /* I2C0_SDA */
+			 <RZV2H_PORT_PINMUX(3, 1, 1)>; /* I2C0_SCL */
 	};
 
 	i2c1_pins: i2c1 {
-		pinmux = <RZG2L_PORT_PINMUX(3, 2, 1)>, /* I2C1_SDA */
-			 <RZG2L_PORT_PINMUX(3, 3, 1)>; /* I2C1_SCL */
+		pinmux = <RZV2H_PORT_PINMUX(3, 2, 1)>, /* I2C1_SDA */
+			 <RZV2H_PORT_PINMUX(3, 3, 1)>; /* I2C1_SCL */
 	};
 
 	i2c2_pins: i2c2 {
-		pinmux = <RZG2L_PORT_PINMUX(2, 0, 4)>, /* I2C2_SDA */
-			 <RZG2L_PORT_PINMUX(2, 1, 4)>; /* I2C2_SCL */
+		pinmux = <RZV2H_PORT_PINMUX(2, 0, 4)>, /* I2C2_SDA */
+			 <RZV2H_PORT_PINMUX(2, 1, 4)>; /* I2C2_SCL */
 	};
 
 	i2c3_pins: i2c3 {
-		pinmux = <RZG2L_PORT_PINMUX(3, 6, 1)>, /* I2C3_SDA */
-			 <RZG2L_PORT_PINMUX(3, 7, 1)>; /* I2C3_SCL */
+		pinmux = <RZV2H_PORT_PINMUX(3, 6, 1)>, /* I2C3_SDA */
+			 <RZV2H_PORT_PINMUX(3, 7, 1)>; /* I2C3_SCL */
 	};
 
 	i2c6_pins: i2c6 {
-		pinmux = <RZG2L_PORT_PINMUX(4, 4, 1)>, /* I2C6_SDA */
-			 <RZG2L_PORT_PINMUX(4, 5, 1)>; /* I2C6_SCL */
+		pinmux = <RZV2H_PORT_PINMUX(4, 4, 1)>, /* I2C6_SDA */
+			 <RZV2H_PORT_PINMUX(4, 5, 1)>; /* I2C6_SCL */
 	};
 
 	i2c7_pins: i2c7 {
-		pinmux = <RZG2L_PORT_PINMUX(4, 6, 1)>, /* I2C7_SDA */
-			 <RZG2L_PORT_PINMUX(4, 7, 1)>; /* I2C7_SCL */
+		pinmux = <RZV2H_PORT_PINMUX(4, 6, 1)>, /* I2C7_SDA */
+			 <RZV2H_PORT_PINMUX(4, 7, 1)>; /* I2C7_SCL */
 	};
 
 	i2c8_pins: i2c8 {
-		pinmux = <RZG2L_PORT_PINMUX(0, 6, 1)>, /* I2C8_SDA */
-			 <RZG2L_PORT_PINMUX(0, 7, 1)>; /* I2C8_SCL */
+		pinmux = <RZV2H_PORT_PINMUX(0, 6, 1)>, /* I2C8_SDA */
+			 <RZV2H_PORT_PINMUX(0, 7, 1)>; /* I2C8_SCL */
 	};
 
 	scif_pins: scif {
@@ -199,7 +199,7 @@
 
 	sd1-pwr-en-hog {
 		gpio-hog;
-		gpios = <RZG2L_GPIO(10, 3) GPIO_ACTIVE_HIGH>;
+		gpios = <RZV2H_GPIO(A, 3) GPIO_ACTIVE_HIGH>;
 		output-high;
 		line-name = "sd1_pwr_en";
 	};
@@ -219,7 +219,7 @@
 		};
 
 		sd1_cd {
-			pinmux = <RZG2L_PORT_PINMUX(9, 4, 14)>; /* SD1_CD */
+			pinmux = <RZV2H_PORT_PINMUX(9, 4, 14)>; /* SD1_CD */
 		};
 	};
 };
diff --git a/dts/upstream/src/arm64/renesas/renesas-smarc2.dtsi b/dts/upstream/src/arm64/renesas/renesas-smarc2.dtsi
new file mode 100644
index 00000000000..e378d55e6e9
--- /dev/null
+++ b/dts/upstream/src/arm64/renesas/renesas-smarc2.dtsi
@@ -0,0 +1,24 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Device Tree Source for the RZ SMARC Carrier-II Board.
+ *
+ * Copyright (C) 2024 Renesas Electronics Corp.
+ */
+
+/ {
+	model = "Renesas RZ SMARC Carrier-II Board";
+	compatible = "renesas,smarc2-evk";
+
+	chosen {
+		bootargs = "ignore_loglevel";
+		stdout-path = "serial3:115200n8";
+	};
+
+	aliases {
+		serial3 = &scif0;
+	};
+};
+
+&scif0 {
+	status = "okay";
+};
diff --git a/dts/upstream/src/arm64/renesas/rzg3e-smarc-som.dtsi b/dts/upstream/src/arm64/renesas/rzg3e-smarc-som.dtsi
new file mode 100644
index 00000000000..6b583ae2ac5
--- /dev/null
+++ b/dts/upstream/src/arm64/renesas/rzg3e-smarc-som.dtsi
@@ -0,0 +1,28 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Device Tree Source for the R9A09G047E57 SMARC SoM board.
+ *
+ * Copyright (C) 2024 Renesas Electronics Corp.
+ */
+
+/ {
+	compatible = "renesas,rzg3e-smarcm", "renesas,r9a09g047e57", "renesas,r9a09g047";
+
+	memory@48000000 {
+		device_type = "memory";
+		/* First 128MB is reserved for secure area. */
+		reg = <0x0 0x48000000 0x0 0xf8000000>;
+	};
+};
+
+&audio_extal_clk {
+	clock-frequency = <48000000>;
+};
+
+&qextal_clk {
+	clock-frequency = <24000000>;
+};
+
+&rtxin_clk {
+	clock-frequency = <32768>;
+};
diff --git a/dts/upstream/src/arm64/renesas/rzg3s-smarc-som.dtsi b/dts/upstream/src/arm64/renesas/rzg3s-smarc-som.dtsi
index 2ed01d39155..ef12c1c462a 100644
--- a/dts/upstream/src/arm64/renesas/rzg3s-smarc-som.dtsi
+++ b/dts/upstream/src/arm64/renesas/rzg3s-smarc-som.dtsi
@@ -43,11 +43,6 @@
 #endif
 	};
 
-	chosen {
-		bootargs = "ignore_loglevel";
-		stdout-path = "serial0:115200n8";
-	};
-
 	memory@48000000 {
 		device_type = "memory";
 		/* First 128MB is reserved for secure area. */
@@ -63,7 +58,6 @@
 		enable-active-high;
 	};
 
-#if SW_CONFIG2 == SW_ON
 	vccq_sdhi0: regulator1 {
 		compatible = "regulator-gpio";
 		regulator-name = "SDHI0 VccQ";
@@ -73,8 +67,8 @@
 		gpios-states = <1>;
 		states = <3300000 1>, <1800000 0>;
 	};
-#else
-	reg_1p8v: regulator1 {
+
+	reg_1p8v: regulator2 {
 		compatible = "regulator-fixed";
 		regulator-name = "fixed-1.8V";
 		regulator-min-microvolt = <1800000>;
@@ -82,9 +76,17 @@
 		regulator-boot-on;
 		regulator-always-on;
 	};
-#endif
 
-	vcc_sdhi2: regulator2 {
+	reg_3p3v: regulator3 {
+		compatible = "regulator-fixed";
+		regulator-name = "fixed-3.3V";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-boot-on;
+		regulator-always-on;
+	};
+
+	vcc_sdhi2: regulator4 {
 		compatible = "regulator-fixed";
 		regulator-name = "SDHI2 Vcc";
 		regulator-min-microvolt = <3300000>;
@@ -92,6 +94,16 @@
 		gpios = <&pinctrl RZG2L_GPIO(8, 1) GPIO_ACTIVE_HIGH>;
 		enable-active-high;
 	};
+
+	x3_clk: x3-clock {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <24000000>;
+	};
+};
+
+&adc {
+	status = "okay";
 };
 
 #if SW_CONFIG3 == SW_ON
@@ -152,6 +164,30 @@
 
 &i2c1 {
 	status = "okay";
+
+	versa3: clock-generator@68 {
+		compatible = "renesas,5l35023";
+		reg = <0x68>;
+		clocks = <&x3_clk>;
+		#clock-cells = <1>;
+		assigned-clocks = <&versa3 0>,
+				  <&versa3 1>,
+				  <&versa3 2>,
+				  <&versa3 3>,
+				  <&versa3 4>,
+				  <&versa3 5>;
+		assigned-clock-rates = <24000000>,
+				       <12288000>,
+				       <11289600>,
+				       <25000000>,
+				       <100000000>,
+				       <100000000>;
+		renesas,settings = [
+		  80 00 11 19 4c 42 dc 2f 06 7d 20 1a 5f 1e f2 27
+		  00 40 00 00 00 00 00 00 06 0c 19 02 3f f0 90 86
+		  a0 80 30 30 9c
+		];
+	};
 };
 
 #if SW_CONFIG2 == SW_ON
diff --git a/dts/upstream/src/arm64/renesas/rzg3s-smarc.dtsi b/dts/upstream/src/arm64/renesas/rzg3s-smarc.dtsi
index 4509151344c..81b4ffd1417 100644
--- a/dts/upstream/src/arm64/renesas/rzg3s-smarc.dtsi
+++ b/dts/upstream/src/arm64/renesas/rzg3s-smarc.dtsi
@@ -12,10 +12,15 @@
 / {
 	aliases {
 		i2c0 = &i2c0;
-		serial0 = &scif0;
+		serial3 = &scif0;
 		mmc1 = &sdhi1;
 	};
 
+	chosen {
+		bootargs = "ignore_loglevel";
+		stdout-path = "serial3:115200n8";
+	};
+
 	keys {
 		compatible = "gpio-keys";
 
@@ -44,6 +49,23 @@
 		};
 	};
 
+	snd_rzg3s: sound {
+		compatible = "simple-audio-card";
+		simple-audio-card,format = "i2s";
+		simple-audio-card,bitclock-master = <&cpu_dai>;
+		simple-audio-card,frame-master = <&cpu_dai>;
+		simple-audio-card,mclk-fs = <256>;
+
+		cpu_dai: simple-audio-card,cpu {
+			sound-dai = <&ssi3>;
+		};
+
+		codec_dai: simple-audio-card,codec {
+			sound-dai = <&da7212>;
+			clocks = <&versa3 1>;
+		};
+	};
+
 	vcc_sdhi1: regulator-vcc-sdhi1 {
 		compatible = "regulator-fixed";
 		regulator-name = "SDHI1 Vcc";
@@ -64,13 +86,56 @@
 	};
 };
 
+&audio_clk2 {
+	clock-frequency = <12288000>;
+};
+
 &i2c0 {
 	status = "okay";
 
 	clock-frequency = <1000000>;
+
+	da7212: codec@1a {
+		compatible = "dlg,da7212";
+		reg = <0x1a>;
+
+		clocks = <&versa3 1>;
+		clock-names = "mclk";
+
+		#sound-dai-cells = <0>;
+
+		dlg,micbias1-lvl = <2500>;
+		dlg,micbias2-lvl = <2500>;
+		dlg,dmic-data-sel = "lrise_rfall";
+		dlg,dmic-samplephase = "between_clkedge";
+		dlg,dmic-clkrate = <3000000>;
+
+		VDDA-supply = <&reg_1p8v>;
+		VDDSP-supply = <&reg_3p3v>;
+		VDDMIC-supply = <&reg_3p3v>;
+		VDDIO-supply = <&reg_1p8v>;
+	};
+};
+
+&i2c1 {
+	status = "okay";
+
+	clock-frequency = <400000>;
+
+	power-monitor@44 {
+		compatible = "renesas,isl28022";
+		reg = <0x44>;
+		shunt-resistor-micro-ohms = <8000>;
+		renesas,average-samples = <32>;
+	};
 };
 
 &pinctrl {
+	audio_clock_pins: audio-clock {
+		pins = "AUDIO_CLK1", "AUDIO_CLK2";
+		input-enable;
+	};
+
 	key-1-gpio-hog {
 		gpio-hog;
 		gpios = <RZG2L_GPIO(18, 0) GPIO_ACTIVE_LOW>;
@@ -128,6 +193,13 @@
 			pinmux = <RZG2L_PORT_PINMUX(0, 2, 1)>; /* SD1_CD */
 		};
 	};
+
+	ssi3_pins: ssi3 {
+		pinmux = <RZG2L_PORT_PINMUX(18, 2, 8)>, /* BCK */
+			 <RZG2L_PORT_PINMUX(18, 3, 8)>, /* RCK */
+			 <RZG2L_PORT_PINMUX(18, 4, 8)>, /* TXD */
+			 <RZG2L_PORT_PINMUX(18, 5, 8)>; /* RXD */
+	};
 };
 
 &scif0 {
@@ -148,3 +220,12 @@
 	max-frequency = <125000000>;
 	status = "okay";
 };
+
+&ssi3 {
+	clocks = <&cpg CPG_MOD R9A08G045_SSI3_PCLK2>,
+		 <&cpg CPG_MOD R9A08G045_SSI3_PCLK_SFR>,
+		 <&versa3 2>, <&audio_clk2>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&ssi3_pins>, <&audio_clock_pins>;
+	status = "okay";
+};
diff --git a/dts/upstream/src/arm64/renesas/ulcb-kf.dtsi b/dts/upstream/src/arm64/renesas/ulcb-kf.dtsi
index 5c211ed8304..2a157d1efb3 100644
--- a/dts/upstream/src/arm64/renesas/ulcb-kf.dtsi
+++ b/dts/upstream/src/arm64/renesas/ulcb-kf.dtsi
@@ -4,8 +4,24 @@
  *
  * Copyright (C) 2017 Renesas Electronics Corp.
  * Copyright (C) 2017 Cogent Embedded, Inc.
+ *
+ * Sample Audio settings:
+ *
+ *	> amixer set "DVC Out" 1%
+ *	> amixer set "DVC In"  20%
+ *
+ *	// if you use xxxx-mix+split.dtsi
+ *	> amixer -D hw:1 set "pcm3168a DAC1" 50%
+ *	> amixer -D hw:1 set "pcm3168a DAC2" 50%
+ *	> amixer -D hw:1 set "pcm3168a DAC3" 50%
+ *	> amixer -D hw:1 set "pcm3168a DAC4" 50%
+ *
+ *	// else
+ *	> amixer -D hw:1 set "DAC1" 50%
+ *	> amixer -D hw:1 set "DAC2" 50%
+ *	> amixer -D hw:1 set "DAC3" 50%
+ *	> amixer -D hw:1 set "DAC4" 50%
  */
-
 / {
 	aliases {
 		serial1 = &hscif0;
diff --git a/dts/upstream/src/arm64/renesas/ulcb.dtsi b/dts/upstream/src/arm64/renesas/ulcb.dtsi
index cb11abba7be..0c58d816c37 100644
--- a/dts/upstream/src/arm64/renesas/ulcb.dtsi
+++ b/dts/upstream/src/arm64/renesas/ulcb.dtsi
@@ -4,6 +4,11 @@
  *
  * Copyright (C) 2016 Renesas Electronics Corp.
  * Copyright (C) 2016 Cogent Embedded, Inc.
+ *
+ * Sample Audio settings:
+ *
+ *	> amixer set "DVC Out" 1%
+ *	> amixer set "DVC In"  20%
  */
 
 #include <dt-bindings/gpio/gpio.h>
diff --git a/dts/upstream/src/arm64/renesas/r8a779g0-white-hawk-ard-audio-da7212.dtso b/dts/upstream/src/arm64/renesas/white-hawk-ard-audio-da7212.dtso
index e6cf304c77e..c27b9b3d4e5 100644
--- a/dts/upstream/src/arm64/renesas/r8a779g0-white-hawk-ard-audio-da7212.dtso
+++ b/dts/upstream/src/arm64/renesas/white-hawk-ard-audio-da7212.dtso
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0
 /*
- * Device Tree Source for the White Hawk board with ARD-AUDIO-DA7212 Board
+ * Device Tree Source for White Hawk (Single) board with ARD-AUDIO-DA7212 board
  *
  * You can find and buy "ARD-AUDIO-DA7212" at Digi-Key
  *
@@ -27,12 +27,12 @@
  * +----------------------------+
  * |Breakout board		|
  * |				|	+---------------+
- * |CN34 (I2C CN)		|	|J1		|
+ * |CN(30)34 (I2C CN)		|	|J1		|
  * |	I2C0_SCL	   pin3 |<----->| pin20 SCL	|
  * |	I2C0_SDA	   pin5 |<----->| pin18 SDA	|
  * |				|	+---------------+
  * |				|	+-----------------------+
- * |CN4 (Power)		        |	|J7			|
+ * |CN(300)4 (Power)	        |	|J7			|
  * |	3v3 (v)		   pin9 |<----->| pin4  / pin8  3.3v	|
  * |	GND (v)	    pin3 / pin4 |<----->| pin12 / pin14 GND	|
  * +----------------------------+	+-----------------------+
diff --git a/dts/upstream/src/arm64/renesas/white-hawk-csi-dsi.dtsi b/dts/upstream/src/arm64/renesas/white-hawk-csi-dsi.dtsi
index 3006b0a64f4..9017c4475a7 100644
--- a/dts/upstream/src/arm64/renesas/white-hawk-csi-dsi.dtsi
+++ b/dts/upstream/src/arm64/renesas/white-hawk-csi-dsi.dtsi
@@ -21,6 +21,7 @@
 				bus-type = <MEDIA_BUS_TYPE_CSI2_CPHY>;
 				clock-lanes = <0>;
 				data-lanes = <1 2 3>;
+				line-orders = <0 3 0>;
 				remote-endpoint = <&max96712_out0>;
 			};
 		};
@@ -41,6 +42,7 @@
 				bus-type = <MEDIA_BUS_TYPE_CSI2_CPHY>;
 				clock-lanes = <0>;
 				data-lanes = <1 2 3>;
+				line-orders = <0 3 0>;
 				remote-endpoint = <&max96712_out1>;
 			};
 		};
diff --git a/dts/upstream/src/arm64/renesas/white-hawk-single.dtsi b/dts/upstream/src/arm64/renesas/white-hawk-single.dtsi
new file mode 100644
index 00000000000..20e8232f2f3
--- /dev/null
+++ b/dts/upstream/src/arm64/renesas/white-hawk-single.dtsi
@@ -0,0 +1,73 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Device Tree Source for the White Hawk Single board
+ *
+ * Copyright (C) 2023-2024 Glider bv
+ */
+
+#include "white-hawk-cpu-common.dtsi"
+#include "white-hawk-common.dtsi"
+
+/ {
+	model = "Renesas White Hawk Single board";
+	compatible = "renesas,white-hawk-single";
+};
+
+&hscif0 {
+	uart-has-rtscts;
+};
+
+&hscif0_pins {
+	groups = "hscif0_data", "hscif0_ctrl";
+	function = "hscif0";
+};
+
+&pfc {
+	tsn0_pins: tsn0 {
+		mux {
+			groups = "tsn0_link", "tsn0_mdio", "tsn0_rgmii",
+				 "tsn0_txcrefclk";
+			function = "tsn0";
+		};
+
+		link {
+			groups = "tsn0_link";
+			bias-disable;
+		};
+
+		mdio {
+			groups = "tsn0_mdio";
+			drive-strength = <24>;
+			bias-disable;
+		};
+
+		rgmii {
+			groups = "tsn0_rgmii";
+			drive-strength = <24>;
+			bias-disable;
+		};
+	};
+};
+
+&tsn0 {
+	pinctrl-0 = <&tsn0_pins>;
+	pinctrl-names = "default";
+	phy-mode = "rgmii";
+	phy-handle = <&phy3>;
+	status = "okay";
+
+	mdio {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		reset-gpios = <&gpio1 23 GPIO_ACTIVE_LOW>;
+		reset-post-delay-us = <4000>;
+
+		phy3: ethernet-phy@0 {
+			compatible = "ethernet-phy-id002b.0980",
+				     "ethernet-phy-ieee802.3-c22";
+			reg = <0>;
+			interrupts-extended = <&gpio4 3 IRQ_TYPE_LEVEL_LOW>;
+		};
+	};
+};
diff --git a/dts/upstream/src/arm64/rockchip/px30-ringneck-haikou.dts b/dts/upstream/src/arm64/rockchip/px30-ringneck-haikou.dts
index e4517f47d51..1a59e8b1dc4 100644
--- a/dts/upstream/src/arm64/rockchip/px30-ringneck-haikou.dts
+++ b/dts/upstream/src/arm64/rockchip/px30-ringneck-haikou.dts
@@ -194,6 +194,13 @@
 			  <3 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
 		};
 	};
+
+	uart {
+		uart5_rts_pin: uart5-rts-pin {
+			rockchip,pins =
+			  <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
 };
 
 &pwm0 {
@@ -222,11 +229,15 @@
 };
 
 &uart0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart0_xfer>;
 	status = "okay";
 };
 
 &uart5 {
-	pinctrl-0 = <&uart5_xfer>;
+	/* Add pinmux for rts-gpios (uart5_rts_pin) */
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart5_xfer &uart5_rts_pin>;
 	rts-gpios = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>;
 	status = "okay";
 };
diff --git a/dts/upstream/src/arm64/rockchip/px30-ringneck.dtsi b/dts/upstream/src/arm64/rockchip/px30-ringneck.dtsi
index ae050cc6cd0..e80412abec0 100644
--- a/dts/upstream/src/arm64/rockchip/px30-ringneck.dtsi
+++ b/dts/upstream/src/arm64/rockchip/px30-ringneck.dtsi
@@ -396,6 +396,12 @@
 	status = "okay";
 };
 
+&uart5 {
+	/delete-property/ dmas;
+	/delete-property/ dma-names;
+	pinctrl-0 = <&uart5_xfer>;
+};
+
 /* Mule UCAN */
 &usb_host0_ehci {
 	status = "okay";
diff --git a/dts/upstream/src/arm64/rockchip/rk3328-a1.dts b/dts/upstream/src/arm64/rockchip/rk3328-a1.dts
index 8dfeaf1f8eb..f7c4578865c 100644
--- a/dts/upstream/src/arm64/rockchip/rk3328-a1.dts
+++ b/dts/upstream/src/arm64/rockchip/rk3328-a1.dts
@@ -110,7 +110,6 @@
 	phy-supply = <&vcc_io>;
 	pinctrl-names = "default";
 	pinctrl-0 = <&rgmiim1_pins>;
-	snps,aal;
 	snps,pbl = <0x4>;
 	tx_delay = <0x26>;
 	rx_delay = <0x11>;
diff --git a/dts/upstream/src/arm64/rockchip/rk3328-nanopi-r2.dtsi b/dts/upstream/src/arm64/rockchip/rk3328-nanopi-r2.dtsi
index 1715d311e1f..691d17022af 100644
--- a/dts/upstream/src/arm64/rockchip/rk3328-nanopi-r2.dtsi
+++ b/dts/upstream/src/arm64/rockchip/rk3328-nanopi-r2.dtsi
@@ -142,7 +142,6 @@
 	phy-supply = <&vcc_io_33>;
 	pinctrl-0 = <&rgmiim1_pins>;
 	pinctrl-names = "default";
-	snps,aal;
 
 	mdio {
 		compatible = "snps,dwmac-mdio";
diff --git a/dts/upstream/src/arm64/rockchip/rk3328-orangepi-r1-plus-lts.dts b/dts/upstream/src/arm64/rockchip/rk3328-orangepi-r1-plus-lts.dts
index 67c246ad8b8..ec2ce894da1 100644
--- a/dts/upstream/src/arm64/rockchip/rk3328-orangepi-r1-plus-lts.dts
+++ b/dts/upstream/src/arm64/rockchip/rk3328-orangepi-r1-plus-lts.dts
@@ -17,8 +17,7 @@
 
 &gmac2io {
 	phy-handle = <&yt8531c>;
-	tx_delay = <0x19>;
-	rx_delay = <0x05>;
+	phy-mode = "rgmii-id";
 	status = "okay";
 
 	mdio {
diff --git a/dts/upstream/src/arm64/rockchip/rk3328-orangepi-r1-plus.dts b/dts/upstream/src/arm64/rockchip/rk3328-orangepi-r1-plus.dts
index 324a8e951f7..846b931e16d 100644
--- a/dts/upstream/src/arm64/rockchip/rk3328-orangepi-r1-plus.dts
+++ b/dts/upstream/src/arm64/rockchip/rk3328-orangepi-r1-plus.dts
@@ -15,6 +15,7 @@
 
 &gmac2io {
 	phy-handle = <&rtl8211e>;
+	phy-mode = "rgmii";
 	tx_delay = <0x24>;
 	rx_delay = <0x18>;
 	status = "okay";
diff --git a/dts/upstream/src/arm64/rockchip/rk3328-orangepi-r1-plus.dtsi b/dts/upstream/src/arm64/rockchip/rk3328-orangepi-r1-plus.dtsi
index 82021ffb0a4..09508e324a2 100644
--- a/dts/upstream/src/arm64/rockchip/rk3328-orangepi-r1-plus.dtsi
+++ b/dts/upstream/src/arm64/rockchip/rk3328-orangepi-r1-plus.dtsi
@@ -109,11 +109,9 @@
 	assigned-clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_EXT>;
 	assigned-clock-parents = <&gmac_clk>, <&gmac_clk>;
 	clock_in_out = "input";
-	phy-mode = "rgmii";
 	phy-supply = <&vcc_io>;
 	pinctrl-0 = <&rgmiim1_pins>;
 	pinctrl-names = "default";
-	snps,aal;
 
 	mdio {
 		compatible = "snps,dwmac-mdio";
diff --git a/dts/upstream/src/arm64/rockchip/rk3328-rock-pi-e.dts b/dts/upstream/src/arm64/rockchip/rk3328-rock-pi-e.dts
index 425de197ddb..6310b58de77 100644
--- a/dts/upstream/src/arm64/rockchip/rk3328-rock-pi-e.dts
+++ b/dts/upstream/src/arm64/rockchip/rk3328-rock-pi-e.dts
@@ -153,9 +153,6 @@
 	phy-supply = <&vcc_io>;
 	pinctrl-names = "default";
 	pinctrl-0 = <&rgmiim1_pins>;
-	snps,aal;
-	snps,rxpbl = <0x4>;
-	snps,txpbl = <0x4>;
 	tx_delay = <0x26>;
 	rx_delay = <0x11>;
 	status = "okay";
diff --git a/dts/upstream/src/arm64/rockchip/rk3328-rock64.dts b/dts/upstream/src/arm64/rockchip/rk3328-rock64.dts
index 745d3e99641..e550b6eeeff 100644
--- a/dts/upstream/src/arm64/rockchip/rk3328-rock64.dts
+++ b/dts/upstream/src/arm64/rockchip/rk3328-rock64.dts
@@ -144,7 +144,6 @@
 	phy-mode = "rgmii";
 	pinctrl-names = "default";
 	pinctrl-0 = <&rgmiim1_pins>;
-	snps,force_thresh_dma_mode;
 	snps,reset-gpio = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
 	snps,reset-active-low;
 	snps,reset-delays-us = <0 10000 50000>;
diff --git a/dts/upstream/src/arm64/rockchip/rk3399-gru-chromebook.dtsi b/dts/upstream/src/arm64/rockchip/rk3399-gru-chromebook.dtsi
index 988e6ca32fa..a9ea4b0daa0 100644
--- a/dts/upstream/src/arm64/rockchip/rk3399-gru-chromebook.dtsi
+++ b/dts/upstream/src/arm64/rockchip/rk3399-gru-chromebook.dtsi
@@ -22,11 +22,11 @@
 	};
 
 	/* EC turns on w/ pp900_usb_en */
-	pp900_usb: pp900-ap {
+	pp900_usb: regulator-pp900-ap {
 	};
 
 	/* EC turns on w/ pp900_pcie_en */
-	pp900_pcie: pp900-ap {
+	pp900_pcie: regulator-pp900-ap {
 	};
 
 	pp3000: regulator-pp3000 {
@@ -126,7 +126,7 @@
 	};
 
 	/* Always on; plain and simple */
-	pp3000_ap: pp3000_emmc: pp3000 {
+	pp3000_ap: pp3000_emmc: regulator-pp3000 {
 	};
 
 	pp1500_ap_io: regulator-pp1500-ap-io {
@@ -160,7 +160,7 @@
 	};
 
 	/* EC turns on w/ pp3300_usb_en_l */
-	pp3300_usb: pp3300 {
+	pp3300_usb: regulator-pp3300 {
 	};
 
 	/* gpio is shared with pp1800_pcie and pinctrl is set there */
diff --git a/dts/upstream/src/arm64/rockchip/rk3399-gru-scarlet.dtsi b/dts/upstream/src/arm64/rockchip/rk3399-gru-scarlet.dtsi
index 19b23b43896..5e068377a0a 100644
--- a/dts/upstream/src/arm64/rockchip/rk3399-gru-scarlet.dtsi
+++ b/dts/upstream/src/arm64/rockchip/rk3399-gru-scarlet.dtsi
@@ -92,7 +92,7 @@
 	};
 
 	/* EC turns on pp1800_s3_en */
-	pp1800_s3: pp1800 {
+	pp1800_s3: regulator-pp1800 {
 	};
 
 	/* pp3300 children, sorted by name */
@@ -109,11 +109,11 @@
 	};
 
 	/* EC turns on pp3300_s0_en */
-	pp3300_s0: pp3300 {
+	pp3300_s0: regulator-pp3300 {
 	};
 
 	/* EC turns on pp3300_s3_en */
-	pp3300_s3: pp3300 {
+	pp3300_s3: regulator-pp3300 {
 	};
 
 	/*
diff --git a/dts/upstream/src/arm64/rockchip/rk3399-gru.dtsi b/dts/upstream/src/arm64/rockchip/rk3399-gru.dtsi
index 6d9e60b0122..7eca1da78cf 100644
--- a/dts/upstream/src/arm64/rockchip/rk3399-gru.dtsi
+++ b/dts/upstream/src/arm64/rockchip/rk3399-gru.dtsi
@@ -189,39 +189,39 @@
 	};
 
 	/* EC turns on w/ pp900_ddrpll_en */
-	pp900_ddrpll: pp900-ap {
+	pp900_ddrpll: regulator-pp900-ap {
 	};
 
 	/* EC turns on w/ pp900_pll_en */
-	pp900_pll: pp900-ap {
+	pp900_pll: regulator-pp900-ap {
 	};
 
 	/* EC turns on w/ pp900_pmu_en */
-	pp900_pmu: pp900-ap {
+	pp900_pmu: regulator-pp900-ap {
 	};
 
 	/* EC turns on w/ pp1800_s0_en_l */
-	pp1800_ap_io: pp1800_emmc: pp1800_nfc: pp1800_s0: pp1800 {
+	pp1800_ap_io: pp1800_emmc: pp1800_nfc: pp1800_s0: regulator-pp1800 {
 	};
 
 	/* EC turns on w/ pp1800_avdd_en_l */
-	pp1800_avdd: pp1800 {
+	pp1800_avdd: regulator-pp1800 {
 	};
 
 	/* EC turns on w/ pp1800_lid_en_l */
-	pp1800_lid: pp1800_mic: pp1800 {
+	pp1800_lid: pp1800_mic: regulator-pp1800 {
 	};
 
 	/* EC turns on w/ lpddr_pwr_en */
-	pp1800_lpddr: pp1800 {
+	pp1800_lpddr: regulator-pp1800 {
 	};
 
 	/* EC turns on w/ pp1800_pmu_en_l */
-	pp1800_pmu: pp1800 {
+	pp1800_pmu: regulator-pp1800 {
 	};
 
 	/* EC turns on w/ pp1800_usb_en_l */
-	pp1800_usb: pp1800 {
+	pp1800_usb: regulator-pp1800 {
 	};
 
 	pp3000_sd_slot: regulator-pp3000-sd-slot {
@@ -259,11 +259,11 @@
 	};
 
 	/* EC turns on w/ pp3300_trackpad_en_l */
-	pp3300_trackpad: pp3300-trackpad {
+	pp3300_trackpad: regulator-pp3300-trackpad {
 	};
 
 	/* EC turns on w/ usb_a_en */
-	pp5000_usb_a_vbus: pp5000 {
+	pp5000_usb_a_vbus: regulator-pp5000 {
 	};
 
 	ap_rtc_clk: ap-rtc-clk {
diff --git a/dts/upstream/src/arm64/rockchip/rk3399-nanopi-r4s.dtsi b/dts/upstream/src/arm64/rockchip/rk3399-nanopi-r4s.dtsi
index b1c9bd0e63e..8d94d9f91a5 100644
--- a/dts/upstream/src/arm64/rockchip/rk3399-nanopi-r4s.dtsi
+++ b/dts/upstream/src/arm64/rockchip/rk3399-nanopi-r4s.dtsi
@@ -115,7 +115,7 @@
 };
 
 &u2phy1_host {
-	status = "disabled";
+	phy-supply = <&vdd_5v>;
 };
 
 &uart0 {
diff --git a/dts/upstream/src/arm64/rockchip/rk3399-puma.dtsi b/dts/upstream/src/arm64/rockchip/rk3399-puma.dtsi
index d12e661dfd9..995b30a7aae 100644
--- a/dts/upstream/src/arm64/rockchip/rk3399-puma.dtsi
+++ b/dts/upstream/src/arm64/rockchip/rk3399-puma.dtsi
@@ -182,7 +182,7 @@
 	snps,reset-active-low;
 	snps,reset-delays-us = <0 10000 50000>;
 	tx_delay = <0x10>;
-	rx_delay = <0x10>;
+	rx_delay = <0x23>;
 	status = "okay";
 };
 
diff --git a/dts/upstream/src/arm64/rockchip/rk3399-rockpro64.dtsi b/dts/upstream/src/arm64/rockchip/rk3399-rockpro64.dtsi
index 69a9d617064..51c6aa26d82 100644
--- a/dts/upstream/src/arm64/rockchip/rk3399-rockpro64.dtsi
+++ b/dts/upstream/src/arm64/rockchip/rk3399-rockpro64.dtsi
@@ -227,6 +227,16 @@
 		vin-supply = <&vcc12v_dcin>;
 	};
 
+	vcca_0v9: regulator-vcca-0v9 {
+		compatible = "regulator-fixed";
+		regulator-name = "vcca_0v9";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <900000>;
+		regulator-max-microvolt = <900000>;
+		vin-supply = <&vcc3v3_sys>;
+	};
+
 	vdd_log: regulator-vdd-log {
 		compatible = "pwm-regulator";
 		pwms = <&pwm2 0 25000 1>;
@@ -312,6 +322,8 @@
 };
 
 &hdmi {
+	avdd-0v9-supply = <&vcca_0v9>;
+	avdd-1v8-supply = <&vcc1v8_dvp>;
 	ddc-i2c-bus = <&i2c3>;
 	pinctrl-names = "default";
 	pinctrl-0 = <&hdmi_cec>;
@@ -661,6 +673,8 @@
 	num-lanes = <4>;
 	pinctrl-names = "default";
 	pinctrl-0 = <&pcie_perst>;
+	vpcie0v9-supply = <&vcca_0v9>;
+	vpcie1v8-supply = <&vcca_1v8>;
 	vpcie12v-supply = <&vcc12v_dcin>;
 	vpcie3v3-supply = <&vcc3v3_pcie>;
 	status = "okay";
diff --git a/dts/upstream/src/arm64/rockchip/rk3566-bigtreetech-cb2-manta.dts b/dts/upstream/src/arm64/rockchip/rk3566-bigtreetech-cb2-manta.dts
new file mode 100644
index 00000000000..97415d099d8
--- /dev/null
+++ b/dts/upstream/src/arm64/rockchip/rk3566-bigtreetech-cb2-manta.dts
@@ -0,0 +1,10 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+/dts-v1/;
+
+#include "rk3566-bigtreetech-cb2.dtsi"
+
+/ {
+	model = "BigTreeTech CB2";
+	compatible = "bigtreetech,cb2-manta", "bigtreetech,cb2", "rockchip,rk3566";
+};
diff --git a/dts/upstream/src/arm64/rockchip/rk3566-bigtreetech-cb2.dtsi b/dts/upstream/src/arm64/rockchip/rk3566-bigtreetech-cb2.dtsi
new file mode 100644
index 00000000000..a4835147176
--- /dev/null
+++ b/dts/upstream/src/arm64/rockchip/rk3566-bigtreetech-cb2.dtsi
@@ -0,0 +1,904 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pwm/pwm.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+#include <dt-bindings/soc/rockchip,vop2.h>
+#include <dt-bindings/leds/common.h>
+#include "rk3566.dtsi"
+
+/ {
+	aliases {
+		ethernet0 = &gmac1;
+		mmc0 = &sdhci;
+		mmc1 = &sdmmc0;
+	};
+
+	chosen: chosen {
+		stdout-path = "serial2:1500000n8";
+	};
+
+	ext_cam_clk: clock-25000000-cam {
+		compatible = "fixed-clock";
+		clock-frequency = <25000000>;
+		clock-output-names = "ext_cam_clk";
+		#clock-cells = <0>;
+	};
+
+	can_mcp2515_osc: clock-8000000-mcp2515 {
+		compatible = "fixed-clock";
+		clock-frequency = <8000000>;
+		#clock-cells = <0>;
+	};
+
+	hdmi-con {
+		compatible = "hdmi-connector";
+		type = "a";
+
+		port {
+			hdmi_con_in: endpoint {
+				remote-endpoint = <&hdmi_out_con>;
+			};
+		};
+	};
+
+	leds: leds {
+		compatible = "gpio-leds";
+
+		led-0 {
+			color = <LED_COLOR_ID_BLUE>;
+			function = LED_FUNCTION_POWER;
+			gpios = <&gpio4 RK_PA1 GPIO_ACTIVE_LOW>;
+			linux,default-trigger = "default-on";
+			pinctrl-names = "default";
+			pinctrl-0 =<&blue_led>;
+		};
+
+		led-1 {
+			color = <LED_COLOR_ID_GREEN>;
+			function = LED_FUNCTION_HEARTBEAT;
+			gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_LOW>;
+			linux,default-trigger = "heartbeat";
+			pinctrl-names = "default";
+			pinctrl-0 =<&heartbeat_led>;
+		};
+	};
+
+	fan: pwm-fan {
+		compatible = "pwm-fan";
+		#cooling-cells = <2>;
+		cooling-levels = <0 50 100 150 200 255>;
+		pwms = <&pwm7 0 50000 0>;
+	};
+
+	rk809-sound {
+		compatible = "simple-audio-card";
+		simple-audio-card,format = "i2s";
+		simple-audio-card,name = "Analog RK809";
+		simple-audio-card,mclk-fs = <256>;
+
+		simple-audio-card,cpu {
+			sound-dai = <&i2s1_8ch>;
+		};
+
+		simple-audio-card,codec {
+			sound-dai = <&rk809>;
+		};
+	};
+
+	sdio_pwrseq: sdio-pwrseq {
+		compatible = "mmc-pwrseq-simple";
+		clocks = <&rk809 1>;
+		clock-names = "ext_clock";
+		pinctrl-names = "default";
+		pinctrl-0 = <&wifi_enable_h>;
+		post-power-on-delay-ms = <200>;
+		reset-gpios = <&gpio0 RK_PD3 GPIO_ACTIVE_LOW>;
+	};
+
+	vbus: regulator-vbus {
+		compatible = "regulator-fixed";
+		regulator-name = "vbus";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+	};
+
+	vcc12v_dcin: regulator-vcc12v-dcin {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc12v_dcin";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <12000000>;
+		regulator-max-microvolt = <12000000>;
+	};
+
+	vcc3v3_pcie: regulator-vcc3v3-pcie {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc3v3_pcie";
+		enable-active-high;
+		gpios = <&gpio0 RK_PB1 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pcie_drv>;
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		vin-supply = <&vcc12v_dcin>;
+	};
+
+	vcc3v3_sys: regulator-vcc3v3-sys {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc3v3_sys";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		vin-supply = <&vbus>;
+	};
+
+	vcc5v0_host: regulator-vcc5v0-host {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&vcc5v0_host_en>;
+		regulator-name = "vcc5v0_host3";
+		regulator-always-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+	};
+
+	vcc5v0_otg: regulator-vcc5v0-otg {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpios = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&vcc5v0_otg_en>;
+		regulator-name = "vcc5v0_otg3";
+		regulator-always-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+	};
+
+	vcc5v0_sys: regulator-vcc5v0-sys {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc5v0_sys";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		vin-supply = <&vbus>;
+	};
+
+	vcc5v0_usb: regulator-vcc5v0-usb {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc5v0_usb";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		vin-supply = <&vbus>;
+	};
+
+	vcc5v0_usb2b: regulator-vcc5v0-usb2b {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpio = <&gpio0 RK_PC4 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&vcc5v0_usb2b_en>;
+		regulator-name = "vcc5v0_usb2b";
+		regulator-always-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+	};
+
+	vcc5v0_usb2t: regulator-vcc5v0-usb2t {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpios = <&gpio0 RK_PD5 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&vcc5v0_usb2t_en>;
+		regulator-name = "vcc5v0_usb2t";
+		regulator-always-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+	};
+
+	vcc_5v: regulator-vcc-5v {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc_5v";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		vin-supply = <&vcc12v_dcin>;
+	};
+
+	vcc_sd: regulator-vcc-sd {
+		compatible = "regulator-fixed";
+		regulator-max-microvolt = <3300000>;
+		regulator-min-microvolt = <3300000>;
+		regulator-name = "vcc_sd";
+		vin-supply = <&vcc3v3_sys>;
+	};
+};
+
+&combphy1 {
+	status = "okay";
+};
+
+&combphy2 {
+	status = "okay";
+};
+
+&cpu0 {
+	cpu-supply = <&vdd_cpu>;
+};
+
+&cpu1 {
+	cpu-supply = <&vdd_cpu>;
+};
+
+&cpu2 {
+	cpu-supply = <&vdd_cpu>;
+};
+
+&cpu3 {
+	cpu-supply = <&vdd_cpu>;
+};
+
+&gmac1 {
+	assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
+	assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru CLK_MAC1_2TOP>;
+	assigned-clock-rates = <0>, <125000000>;
+	clock_in_out = "input";
+	phy-handle = <&rgmii_phy0>;
+	phy-mode = "rgmii-id";
+	pinctrl-names = "default";
+	pinctrl-0 = <&gmac1m0_miim
+			&gmac1m0_tx_bus2
+			&gmac1m0_rx_bus2
+			&gmac1m0_rgmii_clk
+			&gmac1m0_clkinout
+			&gmac1m0_rgmii_bus>;
+	status = "okay";
+};
+
+&mdio1 {
+	rgmii_phy0: phy@0 {
+		compatible = "ethernet-phy-ieee802.3-c22";
+		reset-delay-us = <20000>;
+		reset-gpios = <&gpio0 RK_PC5 GPIO_ACTIVE_LOW>;
+		reset-post-delay-us = <100000>;
+		reg = <0x0>;
+	};
+};
+
+&gpu {
+	mali-supply = <&vdd_gpu>;
+	status = "okay";
+};
+
+&hdmi {
+	avdd-0v9-supply = <&vdda0v9_image>;
+	avdd-1v8-supply = <&vcca1v8_image>;
+	status = "okay";
+};
+
+&hdmi_in {
+	hdmi_in_vp0: endpoint {
+		remote-endpoint = <&vp0_out_hdmi>;
+	};
+};
+
+&hdmi_out {
+	hdmi_out_con: endpoint {
+		remote-endpoint = <&hdmi_con_in>;
+	};
+};
+
+&hdmi_sound {
+	status = "okay";
+};
+
+&i2c0 {
+	status = "okay";
+
+	vdd_cpu: regulator@1c {
+		compatible = "tcs,tcs4525";
+		reg = <0x1c>;
+		regulator-name = "vdd_cpu";
+		regulator-min-microvolt = <712500>;
+		regulator-max-microvolt = <1390000>;
+		regulator-initial-mode = <1>;
+		regulator-ramp-delay = <2300>;
+		regulator-boot-on;
+		regulator-always-on;
+		vin-supply = <&vcc5v0_sys>;
+		fcs,suspend-voltage-selector = <1>;
+
+		regulator-state-mem {
+			regulator-off-in-suspend;
+		};
+	};
+
+	rk809: pmic@20 {
+		compatible = "rockchip,rk809";
+		reg = <0x20>;
+		interrupt-parent = <&gpio0>;
+		interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
+		assigned-clocks = <&cru I2S1_MCLKOUT_TX>;
+		assigned-clock-parents = <&cru CLK_I2S1_8CH_TX>;
+		#clock-cells = <1>;
+		clock-names = "mclk";
+		clocks = <&cru I2S1_MCLKOUT_TX>;
+		pinctrl-names = "default", "pmic-sleep",
+				"pmic-power-off", "pmic-reset";
+		pinctrl-0 = <&pmic_int>, <&i2s1m0_mclk>;
+		#sound-dai-cells = <0>;
+		system-power-controller;
+		wakeup-source;
+
+		vcc1-supply = <&vcc3v3_sys>;
+		vcc2-supply = <&vcc3v3_sys>;
+		vcc3-supply = <&vcc3v3_sys>;
+		vcc4-supply = <&vcc3v3_sys>;
+		vcc5-supply = <&vcc3v3_sys>;
+		vcc6-supply = <&vcc3v3_sys>;
+		vcc7-supply = <&vcc3v3_sys>;
+		vcc8-supply = <&vcc3v3_sys>;
+		vcc9-supply = <&vcc3v3_sys>;
+
+		regulators {
+			vdd_logic: DCDC_REG1 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <500000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-ramp-delay = <6001>;
+				regulator-initial-mode = <0x2>;
+				regulator-name = "vdd_logic";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdd_gpu: DCDC_REG2 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <500000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-ramp-delay = <6001>;
+				regulator-initial-mode = <0x2>;
+				regulator-name = "vdd_gpu";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_ddr: DCDC_REG3 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-initial-mode = <0x2>;
+				regulator-name = "vcc_ddr";
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+				};
+			};
+
+			vdd_npu: DCDC_REG4 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <500000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-ramp-delay = <6001>;
+				regulator-initial-mode = <0x2>;
+				regulator-name = "vdd_npu";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdda0v9_image: LDO_REG1 {
+				regulator-boot-on;
+				regulator-always-on;
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <900000>;
+				regulator-name = "vdda0v9_image";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdda_0v9: LDO_REG2 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <900000>;
+				regulator-name = "vdda_0v9";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdda0v9_pmu: LDO_REG3 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <900000>;
+				regulator-name = "vdda0v9_pmu";
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <900000>;
+				};
+			};
+
+			vccio_acodec: LDO_REG4 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3000000>;
+				regulator-max-microvolt = <3000000>;
+				regulator-name = "vccio_acodec";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vccio_sd: LDO_REG5 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-name = "vccio_sd";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc3v3_pmu: LDO_REG6 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-name = "vcc3v3_pmu";
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <3300000>;
+				};
+			};
+
+			vcca_1v8: LDO_REG7 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-name = "vcca_1v8";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcca1v8_pmu: LDO_REG8 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-name = "vcca1v8_pmu";
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			vcca1v8_image: LDO_REG9 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-name = "vcca1v8_image";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_1v8: DCDC_REG5 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-name = "vcc_1v8";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_3v3: SWITCH_REG1 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-name = "vcc_3v3";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc3v3_sd: SWITCH_REG2 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-name = "vcc3v3_sd";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+		};
+
+		codec {
+			rockchip,mic-in-differential;
+		};
+	};
+};
+
+&i2c2 {
+	pinctrl-0 = <&i2c2m1_xfer>;
+};
+
+&i2c3 {
+	status = "okay";
+
+	tft_tp: touchscreen@48 {
+		compatible = "ti,tsc2007";
+		reg = <0x48>;
+		status = "okay";
+		ti,x-plate-ohms = <660>;
+		ti,rt-thr = <3000>;
+		ti,fuzzx = <32>;
+		ti,fuzzy = <16>;
+	};
+};
+
+&i2s0_8ch {
+	status = "okay";
+};
+
+&i2s1_8ch {
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2s1m0_sclktx &i2s1m0_lrcktx &i2s1m0_sdi0 &i2s1m0_sdo0>;
+	rockchip,trcm-sync-tx-only;
+	status = "okay";
+};
+
+&spi1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&spi1m1_cs0 &spi1m1_pins>;
+
+	can_mcp2515: can@0 {
+		compatible = "microchip,mcp2515";
+		reg = <0x00>;
+		clocks = <&can_mcp2515_osc>;
+		interrupt-parent = <&gpio4>;
+		interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&mcp2515_int_pin>;
+		spi-max-frequency = <10000000>;
+		vdd-supply = <&vcc3v3_sys>;
+		xceiver-supply = <&vcc3v3_sys>;
+	};
+};
+
+&spi3 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&spi3m1_cs0 &spi3m1_pins>;
+};
+
+&pcie2x1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pcie_reset_h>;
+	reset-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>;
+	vpcie3v3-supply = <&vcc3v3_pcie>;
+	status = "okay";
+};
+
+&pinctrl {
+	bt {
+		bt_enable: bt-enable-h {
+			rockchip,pins = <2 RK_PB7 RK_FUNC_GPIO &pcfg_pull_down>;
+		};
+
+		bt_host_wake: bt-host-wake-l {
+			rockchip,pins = <2 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>;
+		};
+
+		bt_wake: bt-wake-l {
+			rockchip,pins = <2 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	pcie {
+		pcie_drv: pcie-drv {
+			rockchip,pins = <4 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		pcie_reset_h: pcie-reset-h {
+			rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	pmic {
+		pmic_int: pmic-int {
+			rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+	};
+
+	sdio-pwrseq {
+		wifi_enable_h: wifi-enable-h {
+			rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		wifi_host_wake: wifi-host-wake-l {
+			rockchip,pins = <2 RK_PB1 RK_FUNC_GPIO &pcfg_pull_down>;
+		};
+	};
+
+	usb {
+		vcc5v0_host_en: vcc5v0-host-en {
+			rockchip,pins = <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		vcc5v0_otg_en: vcc5v0-otg-en {
+			rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		vcc5v0_usb2t_en: vcc5v0-usb2t-en {
+			rockchip,pins = <3 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		vcc5v0_usb2b_en: vcc5v0-usb2b-en {
+			rockchip,pins = <4 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	work-led {
+		heartbeat_led: led-heartbeat {
+			rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		blue_led: led-blue {
+			rockchip,pins = <4 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	mcp2515 {
+		mcp2515_int_pin: mcp2515-int-pin {
+			rockchip,pins = <4 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+	};
+};
+
+&pmu_io_domains {
+	pmuio1-supply = <&vcc3v3_pmu>;
+	pmuio2-supply = <&vcc3v3_pmu>;
+	vccio1-supply = <&vcc_3v3>;
+	vccio2-supply = <&vcc_1v8>;
+	vccio3-supply = <&vccio_sd>;
+	vccio4-supply = <&vcc_1v8>;
+	vccio5-supply = <&vcc_3v3>;
+	vccio6-supply = <&vcc_3v3>;
+	vccio7-supply = <&vcc_3v3>;
+	status = "okay";
+};
+
+&pwm0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pwm0m1_pins>;
+};
+
+&pwm12 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pwm12m1_pins>;
+};
+
+&pwm13 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pwm13m1_pins>;
+};
+
+&pwm14 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pwm14m1_pins>;
+};
+
+&pwm15 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pwm15m1_pins>;
+};
+
+&saradc {
+	vref-supply = <&vcca_1v8>;
+	status = "okay";
+};
+
+&sdhci {
+	bus-width = <8>;
+	max-frequency = <200000000>;
+	non-removable;
+	pinctrl-names = "default";
+	pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd>;
+	status = "okay";
+};
+
+&sdmmc0 {
+	max-frequency = <150000000>;
+	bus-width = <4>;
+	cap-mmc-highspeed;
+	cap-sd-highspeed;
+	disable-wp;
+	pinctrl-names = "default";
+	pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
+	vmmc-supply = <&vcc_sd>;
+	vqmmc-supply = <&vccio_sd>;
+	status = "okay";
+};
+
+&sdmmc1 {
+	/* WiFi & BT combo module AMPAK AP6256 */
+	#address-cells = <1>;
+	#size-cells = <0>;
+	bus-width = <4>;
+	cap-sd-highspeed;
+	cap-sdio-irq;
+	disable-wp;
+	keep-power-in-suspend;
+	max-frequency = <150000000>;
+	mmc-pwrseq = <&sdio_pwrseq>;
+	non-removable;
+	pinctrl-names = "default";
+	pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_cmd &sdmmc1_clk>;
+	rockchip,default-sample-phase = <90>;
+	status = "okay";
+
+	sdio-wifi@1 {
+		compatible = "brcm,bcm4329-fmac";
+		reg = <1>;
+		interrupt-parent = <&gpio2>;
+		interrupts = <9 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "host-wake";
+		pinctrl-names = "default";
+		pinctrl-0 = <&wifi_host_wake>;
+		brcm,drive-strength = <10>;
+	};
+};
+
+&sfc {
+	#address-cells = <1>;
+	#size-cells = <0>;
+	status = "okay";
+};
+
+&tsadc {
+	status = "okay";
+};
+
+&uart1 {
+	dma-names = "tx","rx";
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart1m0_xfer &uart1m0_ctsn &uart1m0_rtsn>;
+	uart-has-rtscts;
+	status = "okay";
+
+	bluetooth {
+		compatible = "brcm,bcm4345c5";
+		clocks = <&rk809 1>;
+		clock-names = "lpo";
+		device-wakeup-gpios = <&gpio2 RK_PC0 GPIO_ACTIVE_HIGH>;
+		host-wakeup-gpios = <&gpio2 RK_PC1 GPIO_ACTIVE_HIGH>;
+		shutdown-gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&bt_host_wake &bt_wake &bt_enable>;
+		vbat-supply = <&vcc3v3_sys>;
+		vddio-supply = <&vcca1v8_pmu>;
+	};
+};
+
+&uart2 {
+	status = "okay";
+};
+
+&uart5 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart5m1_xfer>;
+};
+
+&uart7 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart7m2_xfer>;
+};
+
+&usb2phy0 {
+	status = "okay";
+};
+
+&usb2phy0_host {
+	phy-supply = <&vcc5v0_host>;
+	status = "okay";
+};
+
+&usb2phy0_otg {
+	phy-supply = <&vcc5v0_otg>;
+	status = "okay";
+};
+
+&usb2phy1 {
+	status = "okay";
+};
+
+&usb2phy1_host {
+	phy-supply = <&vcc5v0_usb2t>;
+	status = "okay";
+};
+
+&usb2phy1_otg {
+	phy-supply = <&vcc5v0_usb2b>;
+	status = "okay";
+};
+
+&usb_host0_ehci {
+	status = "okay";
+};
+
+&usb_host0_ohci {
+	status = "okay";
+};
+
+&usb_host0_xhci {
+	dr_mode = "host";
+	extcon = <&usb2phy0>;
+	status = "okay";
+};
+
+&usb_host1_ehci {
+	status = "okay";
+};
+
+&usb_host1_ohci {
+	status = "okay";
+};
+
+&usb_host1_xhci {
+	status = "okay";
+};
+
+&vop {
+	assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
+	assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
+	status = "okay";
+};
+
+&vop_mmu {
+	status = "okay";
+};
+
+&vp0 {
+	vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
+		reg = <ROCKCHIP_VOP2_EP_HDMI0>;
+		remote-endpoint = <&hdmi_in_vp0>;
+	};
+};
diff --git a/dts/upstream/src/arm64/rockchip/rk3566-bigtreetech-pi2.dts b/dts/upstream/src/arm64/rockchip/rk3566-bigtreetech-pi2.dts
new file mode 100644
index 00000000000..7cd444caa18
--- /dev/null
+++ b/dts/upstream/src/arm64/rockchip/rk3566-bigtreetech-pi2.dts
@@ -0,0 +1,10 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+/dts-v1/;
+
+#include "rk3566-bigtreetech-cb2.dtsi"
+
+/ {
+	model = "BigTreeTech Pi 2";
+	compatible = "bigtreetech,pi2", "rockchip,rk3566";
+};
diff --git a/dts/upstream/src/arm64/rockchip/rk3566-lubancat-1.dts b/dts/upstream/src/arm64/rockchip/rk3566-lubancat-1.dts
index 61dd71c259a..ddf84c2a19c 100644
--- a/dts/upstream/src/arm64/rockchip/rk3566-lubancat-1.dts
+++ b/dts/upstream/src/arm64/rockchip/rk3566-lubancat-1.dts
@@ -512,7 +512,6 @@
 
 &sdmmc0 {
 	max-frequency = <150000000>;
-	supports-sd;
 	bus-width = <4>;
 	cap-mmc-highspeed;
 	cap-sd-highspeed;
diff --git a/dts/upstream/src/arm64/rockchip/rk3568-mecsbc.dts b/dts/upstream/src/arm64/rockchip/rk3568-mecsbc.dts
index c491dc4d494..b1f185a5890 100644
--- a/dts/upstream/src/arm64/rockchip/rk3568-mecsbc.dts
+++ b/dts/upstream/src/arm64/rockchip/rk3568-mecsbc.dts
@@ -206,12 +206,6 @@
 	};
 };
 
-&i2c2 {
-	status = "okay";
-	pinctrl-names = "default";
-	pinctrl-0 = <&i2c2m0_xfer>;
-};
-
 &i2c3 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&i2c3m0_xfer>;
@@ -357,6 +351,19 @@
 	status = "okay";
 };
 
+&spi0 {
+	/* use hardware chipselect on cs0 (cs1 unconnected) */
+	pinctrl-names = "default";
+	pinctrl-0 = <&spi0m0_pins>, <&spi0m0_cs0>;
+	status = "okay";
+
+	fram@0 {
+		compatible = "fujitsu,mb85rs128ty";
+		reg = <0>;
+		spi-max-frequency = <33000000>;
+	};
+};
+
 &tsadc {
 	rockchip,hw-tshut-mode = <1>;
 	rockchip,hw-tshut-polarity = <0>;
diff --git a/dts/upstream/src/arm64/rockchip/rk3568-qnap-ts433.dts b/dts/upstream/src/arm64/rockchip/rk3568-qnap-ts433.dts
index e601d9271ba..7bd32d230ad 100644
--- a/dts/upstream/src/arm64/rockchip/rk3568-qnap-ts433.dts
+++ b/dts/upstream/src/arm64/rockchip/rk3568-qnap-ts433.dts
@@ -50,6 +50,7 @@
 			color = <LED_COLOR_ID_GREEN>;
 			function = LED_FUNCTION_DISK;
 			gpios = <&gpio1 RK_PD5 GPIO_ACTIVE_LOW>;
+			label = "hdd1:green:disk";
 			linux,default-trigger = "disk-activity";
 			pinctrl-names = "default";
 			pinctrl-0 = <&hdd1_led_pin>;
@@ -59,6 +60,7 @@
 			color = <LED_COLOR_ID_GREEN>;
 			function = LED_FUNCTION_DISK;
 			gpios = <&gpio1 RK_PD6 GPIO_ACTIVE_LOW>;
+			label = "hdd2:green:disk";
 			linux,default-trigger = "disk-activity";
 			pinctrl-names = "default";
 			pinctrl-0 = <&hdd2_led_pin>;
@@ -68,6 +70,7 @@
 			color = <LED_COLOR_ID_GREEN>;
 			function = LED_FUNCTION_DISK;
 			gpios = <&gpio1 RK_PD7 GPIO_ACTIVE_LOW>;
+			label = "hdd3:green:disk";
 			linux,default-trigger = "disk-activity";
 			pinctrl-names = "default";
 			pinctrl-0 = <&hdd3_led_pin>;
@@ -77,6 +80,7 @@
 			color = <LED_COLOR_ID_GREEN>;
 			function = LED_FUNCTION_DISK;
 			gpios = <&gpio2 RK_PA0 GPIO_ACTIVE_LOW>;
+			label = "hdd4:green:disk";
 			linux,default-trigger = "disk-activity";
 			pinctrl-names = "default";
 			pinctrl-0 = <&hdd4_led_pin>;
@@ -483,6 +487,54 @@
 	};
 };
 
+/*
+ * The MCU can provide system temperature too, but only by polling and of
+ * course also cannot set trip points. So attach to the cpu thermal-zone
+ * instead to control the fan.
+ */
+&cpu_thermal {
+	trips {
+		case_fan0: case-fan0 {
+			hysteresis = <2000>;
+			temperature = <35000>;
+			type = "active";
+		};
+
+		case_fan1: case-fan1 {
+			hysteresis = <2000>;
+			temperature = <45000>;
+			type = "active";
+		};
+
+		case_fan2: case-fan2 {
+			hysteresis = <2000>;
+			temperature = <65000>;
+			type = "active";
+		};
+	};
+
+	cooling-maps {
+		/*
+		 * Always provide some air movement, due to small case
+		 * full of harddrives.
+		 */
+		map1 {
+			cooling-device = <&fan THERMAL_NO_LIMIT 1>;
+			trip = <&case_fan0>;
+		};
+
+		map2 {
+			cooling-device = <&fan 2 3>;
+			trip = <&case_fan1>;
+		};
+
+		map3 {
+			cooling-device = <&fan 4 THERMAL_NO_LIMIT>;
+			trip = <&case_fan2>;
+		};
+	};
+};
+
 &pcie30phy {
 	data-lanes = <1 2>;
 	status = "okay";
@@ -582,6 +634,15 @@
  */
 &uart0 {
 	status = "okay";
+
+	mcu {
+		compatible = "qnap,ts433-mcu";
+
+		fan: fan-0 {
+			#cooling-cells = <2>;
+			cooling-levels = <0 64 89 128 166 204 221 238>;
+		};
+	};
 };
 
 /*
diff --git a/dts/upstream/src/arm64/rockchip/rk3568-wolfvision-pf5.dts b/dts/upstream/src/arm64/rockchip/rk3568-wolfvision-pf5.dts
index e8243c90854..bb33fabae16 100644
--- a/dts/upstream/src/arm64/rockchip/rk3568-wolfvision-pf5.dts
+++ b/dts/upstream/src/arm64/rockchip/rk3568-wolfvision-pf5.dts
@@ -53,7 +53,7 @@
 
 	pdm_codec: pdm-codec {
 		compatible = "dmic-codec";
-		num-channels = <1>;
+		num-channels = <2>;
 		#sound-dai-cells = <0>;
 	};
 
@@ -167,6 +167,10 @@
 	};
 };
 
+&hdmi_sound {
+	status = "okay";
+};
+
 &i2c0 {
 	status = "okay";
 
@@ -414,6 +418,10 @@
 	pinctrl-0 = <&i2c4m1_xfer>;
 };
 
+&i2s0_8ch {
+	status = "okay";
+};
+
 &pdm {
 	pinctrl-0 = <&pdmm0_clk
 		     &pdmm0_sdi0>;
diff --git a/dts/upstream/src/arm64/rockchip/rk3576-evb1-v10.dts b/dts/upstream/src/arm64/rockchip/rk3576-evb1-v10.dts
new file mode 100644
index 00000000000..782ca000a64
--- /dev/null
+++ b/dts/upstream/src/arm64/rockchip/rk3576-evb1-v10.dts
@@ -0,0 +1,731 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2024 Rockchip Electronics Co., Ltd.
+ *
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+#include "rk3576.dtsi"
+
+/ {
+	model = "Rockchip RK3576 EVB V10 Board";
+	compatible = "rockchip,rk3576-evb1-v10", "rockchip,rk3576";
+
+	aliases {
+		ethernet0 = &gmac0;
+		ethernet1 = &gmac1;
+	};
+
+	chosen: chosen {
+		stdout-path = "serial0:1500000n8";
+	};
+
+	adc_keys: adc-keys {
+		compatible = "adc-keys";
+		io-channels = <&saradc 1>;
+		io-channel-names = "buttons";
+		keyup-threshold-microvolt = <1800000>;
+		poll-interval = <100>;
+
+		button-back {
+			label = "back";
+			linux,code = <KEY_BACK>;
+			press-threshold-microvolt = <1235000>;
+		};
+
+		button-menu {
+			label = "menu";
+			linux,code = <KEY_MENU>;
+			press-threshold-microvolt = <890000>;
+		};
+
+		button-vol-down {
+			label = "volume down";
+			linux,code = <KEY_VOLUMEDOWN>;
+			press-threshold-microvolt = <417000>;
+		};
+
+		button-vol-up {
+			label = "volume up";
+			linux,code = <KEY_VOLUMEUP>;
+			press-threshold-microvolt = <17000>;
+		};
+	};
+
+	leds: leds {
+		compatible = "gpio-leds";
+
+		work_led: led-0 {
+			gpios = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>;
+			linux,default-trigger = "heartbeat";
+		};
+	};
+
+	vbus5v0_typec: regulator-vbus5v0-typec {
+		compatible = "regulator-fixed";
+		regulator-name = "vbus5v0_typec";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		enable-active-high;
+		gpio = <&gpio0 RK_PD1 GPIO_ACTIVE_HIGH>;
+		vin-supply = <&vcc5v0_device>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&usb_otg0_pwren>;
+	};
+
+	vcc12v_dcin: regulator-vcc12v-dcin {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc12v_dcin";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <12000000>;
+		regulator-max-microvolt = <12000000>;
+	};
+
+	vcc1v2_ufs_vccq_s0: regulator-vcc1v2-ufs-vccq-s0 {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc1v2_ufs_vccq_s0";
+		regulator-boot-on;
+		regulator-always-on;
+		regulator-min-microvolt = <1200000>;
+		regulator-max-microvolt = <1200000>;
+		vin-supply = <&vcc_sys>;
+	};
+
+	vcc1v8_ufs_vccq2_s0: regulator-vcc1v8-ufs-vccq2-s0 {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc1v8_ufs_vccq2_s0";
+		regulator-boot-on;
+		regulator-always-on;
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+		vin-supply = <&vcc_1v8_s3>;
+	};
+
+	vcc3v3_lcd_n: regulator-vcc3v3-lcd0-n {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc3v3_lcd0_n";
+		regulator-boot-on;
+		enable-active-high;
+		gpio = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>;
+		vin-supply = <&vcc_3v3_s0>;
+	};
+
+	vcc3v3_pcie0: regulator-vcc3v3-pcie0 {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc3v3_pcie1";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		enable-active-high;
+		gpios = <&gpio3 RK_PD4 GPIO_ACTIVE_HIGH>;
+		startup-delay-us = <5000>;
+		vin-supply = <&vcc12v_dcin>;
+	};
+
+	vcc3v3_rtc_s5: regulator-vcc3v3-rtc-s5 {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc3v3_rtc_s5";
+		regulator-boot-on;
+		regulator-always-on;
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		vin-supply = <&vcc_sys>;
+	};
+
+	vcc5v0_device: regulator-vcc5v0-device {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc5v0_device";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		vin-supply = <&vcc12v_dcin>;
+	};
+
+	vcc5v0_host: regulator-vcc5v0-host {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc5v0_host";
+		regulator-boot-on;
+		regulator-always-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		enable-active-high;
+		gpio = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>;
+		vin-supply = <&vcc5v0_device>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&usb_host_pwren>;
+	};
+
+	vcc_sys: regulator-vcc5v0-sys {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc_sys";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		vin-supply = <&vcc12v_dcin>;
+	};
+
+	vcc_1v1_nldo_s3: regulator-vcc-1v1-nldo-s3 {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc_1v1_nldo_s3";
+		regulator-boot-on;
+		regulator-always-on;
+		regulator-min-microvolt = <1100000>;
+		regulator-max-microvolt = <1100000>;
+		vin-supply = <&vcc_sys>;
+	};
+
+	vcc_1v8_s0: regulator-vcc-1v8-s0 {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc_1v8_s0";
+		regulator-boot-on;
+		regulator-always-on;
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+		vin-supply = <&vcc_1v8_s3>;
+	};
+
+	vcc_2v0_pldo_s3: regulator-vcc-2v0-pldo-s3 {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc_2v0_pldo_s3";
+		regulator-boot-on;
+		regulator-always-on;
+		regulator-min-microvolt = <2000000>;
+		regulator-max-microvolt = <2000000>;
+		vin-supply = <&vcc_sys>;
+	};
+
+	vcc_3v3_s0: regulator-vcc-3v3-s0 {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc_3v3_s0";
+		regulator-boot-on;
+		regulator-always-on;
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		vin-supply = <&vcc_3v3_s3>;
+	};
+
+	vcc_ufs_s0: regulator-vcc-ufs-s0 {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc_ufs_s0";
+		regulator-boot-on;
+		regulator-always-on;
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		vin-supply = <&vcc_sys>;
+	};
+};
+
+&cpu_l0 {
+	cpu-supply = <&vdd_cpu_lit_s0>;
+};
+
+&cpu_b0 {
+	cpu-supply = <&vdd_cpu_big_s0>;
+};
+
+&combphy1_psu {
+	status = "okay";
+};
+
+&gmac0 {
+	clock_in_out = "output";
+	phy-mode = "rgmii-rxid";
+	phy-handle = <&rgmii_phy0>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&eth0m0_miim
+		     &eth0m0_tx_bus2
+		     &eth0m0_rx_bus2
+		     &eth0m0_rgmii_clk
+		     &eth0m0_rgmii_bus
+		     &ethm0_clk0_25m_out>;
+	snps,reset-gpio = <&gpio2 RK_PB5 GPIO_ACTIVE_LOW>;
+	snps,reset-active-low;
+	snps,reset-delays-us = <0 20000 100000>;
+	tx_delay = <0x21>;
+	status = "okay";
+};
+
+&gmac1 {
+	clock_in_out = "output";
+	phy-handle = <&rgmii_phy1>;
+	phy-mode = "rgmii-rxid";
+	pinctrl-names = "default";
+	pinctrl-0 = <&eth1m0_miim
+		     &eth1m0_tx_bus2
+		     &eth1m0_rx_bus2
+		     &eth1m0_rgmii_clk
+		     &eth1m0_rgmii_bus
+		     &ethm0_clk1_25m_out>;
+	snps,reset-gpio = <&gpio3 RK_PA3 GPIO_ACTIVE_LOW>;
+	snps,reset-active-low;
+	snps,reset-delays-us = <0 20000 100000>;
+	tx_delay = <0x20>;
+	status = "okay";
+};
+
+&i2c1 {
+	status = "okay";
+
+	rk806: pmic@23 {
+		compatible = "rockchip,rk806";
+		reg = <0x23>;
+		interrupt-parent = <&gpio0>;
+		interrupts = <6 IRQ_TYPE_LEVEL_LOW>;
+		gpio-controller;
+		#gpio-cells = <2>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>,
+			    <&rk806_dvs2_null>, <&rk806_dvs3_null>;
+		system-power-controller;
+
+		vcc1-supply = <&vcc_sys>;
+		vcc2-supply = <&vcc_sys>;
+		vcc3-supply = <&vcc_sys>;
+		vcc4-supply = <&vcc_sys>;
+		vcc5-supply = <&vcc_sys>;
+		vcc6-supply = <&vcc_sys>;
+		vcc7-supply = <&vcc_sys>;
+		vcc8-supply = <&vcc_sys>;
+		vcc9-supply = <&vcc_sys>;
+		vcc10-supply = <&vcc_sys>;
+		vcc11-supply = <&vcc_2v0_pldo_s3>;
+		vcc12-supply = <&vcc_sys>;
+		vcc13-supply = <&vcc_1v1_nldo_s3>;
+		vcc14-supply = <&vcc_1v1_nldo_s3>;
+		vcca-supply = <&vcc_sys>;
+
+		rk806_dvs1_null: dvs1-null-pins {
+			pins = "gpio_pwrctrl1";
+			function = "pin_fun0";
+		};
+
+		rk806_dvs2_null: dvs2-null-pins {
+			pins = "gpio_pwrctrl2";
+			function = "pin_fun0";
+		};
+
+		rk806_dvs3_null: dvs3-null-pins {
+			pins = "gpio_pwrctrl3";
+			function = "pin_fun0";
+		};
+
+		rk806_dvs1_slp: dvs1-slp-pins {
+			pins = "gpio_pwrctrl1";
+			function = "pin_fun1";
+		};
+
+		rk806_dvs1_pwrdn: dvs1-pwrdn-pins {
+			pins = "gpio_pwrctrl1";
+			function = "pin_fun2";
+		};
+
+		rk806_dvs1_rst: dvs1-rst-pins {
+			pins = "gpio_pwrctrl1";
+			function = "pin_fun3";
+		};
+
+		rk806_dvs2_slp: dvs2-slp-pins {
+			pins = "gpio_pwrctrl2";
+			function = "pin_fun1";
+		};
+
+		rk806_dvs2_pwrdn: dvs2-pwrdn-pins {
+			pins = "gpio_pwrctrl2";
+			function = "pin_fun2";
+		};
+
+		rk806_dvs2_rst: dvs2-rst-pins {
+			pins = "gpio_pwrctrl2";
+			function = "pin_fun3";
+		};
+
+		rk806_dvs2_dvs: dvs2-dvs-pins {
+			pins = "gpio_pwrctrl2";
+			function = "pin_fun4";
+		};
+
+		rk806_dvs2_gpio: dvs2-gpio-pins {
+			pins = "gpio_pwrctrl2";
+			function = "pin_fun5";
+		};
+
+		rk806_dvs3_slp: dvs3-slp-pins {
+			pins = "gpio_pwrctrl3";
+			function = "pin_fun1";
+		};
+
+		rk806_dvs3_pwrdn: dvs3-pwrdn-pins {
+			pins = "gpio_pwrctrl3";
+			function = "pin_fun2";
+		};
+
+		rk806_dvs3_rst: dvs3-rst-pins {
+			pins = "gpio_pwrctrl3";
+			function = "pin_fun3";
+		};
+
+		rk806_dvs3_dvs: dvs3-dvs-pins {
+			pins = "gpio_pwrctrl3";
+			function = "pin_fun4";
+		};
+
+		rk806_dvs3_gpio: dvs3-gpio-pins {
+			pins = "gpio_pwrctrl3";
+			function = "pin_fun5";
+		};
+
+		regulators {
+			vdd_cpu_big_s0: dcdc-reg1 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <550000>;
+				regulator-max-microvolt = <950000>;
+				regulator-ramp-delay = <12500>;
+				regulator-name = "vdd_cpu_big_s0";
+				regulator-enable-ramp-delay = <400>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdd_npu_s0: dcdc-reg2 {
+				regulator-boot-on;
+				regulator-min-microvolt = <550000>;
+				regulator-max-microvolt = <950000>;
+				regulator-ramp-delay = <12500>;
+				regulator-name = "vdd_npu_s0";
+				regulator-enable-ramp-delay = <400>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdd_cpu_lit_s0: dcdc-reg3 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <550000>;
+				regulator-max-microvolt = <950000>;
+				regulator-ramp-delay = <12500>;
+				regulator-name = "vdd_cpu_lit_s0";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+					regulator-suspend-microvolt = <750000>;
+				};
+			};
+
+			vcc_3v3_s3: dcdc-reg4 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-name = "vcc_3v3_s3";
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <3300000>;
+				};
+			};
+
+			vdd_gpu_s0: dcdc-reg5 {
+				regulator-boot-on;
+				regulator-min-microvolt = <550000>;
+				regulator-max-microvolt = <900000>;
+				regulator-ramp-delay = <12500>;
+				regulator-name = "vdd_gpu_s0";
+				regulator-enable-ramp-delay = <400>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+					regulator-suspend-microvolt = <850000>;
+				};
+			};
+
+			vddq_ddr_s0: dcdc-reg6 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-name = "vddq_ddr_s0";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdd_logic_s0: dcdc-reg7 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <550000>;
+				regulator-max-microvolt = <800000>;
+				regulator-name = "vdd_logic_s0";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_1v8_s3: dcdc-reg8 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-name = "vcc_1v8_s3";
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			vdd2_ddr_s3: dcdc-reg9 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-name = "vdd2_ddr_s3";
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+				};
+			};
+
+			vdd_ddr_s0: dcdc-reg10 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <550000>;
+				regulator-max-microvolt = <1200000>;
+				regulator-name = "vdd_ddr_s0";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcca_1v8_s0: pldo-reg1 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-name = "vcca_1v8_s0";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcca1v8_pldo2_s0: pldo-reg2 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-name = "vcca1v8_pldo2_s0";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdda_1v2_s0: pldo-reg3 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1200000>;
+				regulator-max-microvolt = <1200000>;
+				regulator-name = "vdda_1v2_s0";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcca_3v3_s0: pldo-reg4 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-name = "vcca_3v3_s0";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vccio_sd_s0: pldo-reg5 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-name = "vccio_sd_s0";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcca1v8_pldo6_s3: pldo-reg6 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-name = "vcca1v8_pldo6_s3";
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			vdd_0v75_s3: nldo-reg1 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <550000>;
+				regulator-max-microvolt = <750000>;
+				regulator-name = "vdd_0v75_s3";
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <750000>;
+				};
+			};
+
+			vdda_ddr_pll_s0: nldo-reg2 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <850000>;
+				regulator-max-microvolt = <850000>;
+				regulator-name = "vdda_ddr_pll_s0";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdda0v75_hdmi_s0: nldo-reg3 {
+				regulator-boot-on;
+				regulator-min-microvolt = <837500>;
+				regulator-max-microvolt = <837500>;
+				regulator-name = "vdda0v75_hdmi_s0";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdda_0v85_s0: nldo-reg4 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <850000>;
+				regulator-max-microvolt = <850000>;
+				regulator-name = "vdda_0v85_s0";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdda_0v75_s0: nldo-reg5 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <750000>;
+				regulator-max-microvolt = <750000>;
+				regulator-name = "vdda_0v75_s0";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+		};
+	};
+};
+
+&mdio0 {
+	rgmii_phy0: phy@1 {
+		compatible = "ethernet-phy-ieee802.3-c22";
+		reg = <0x1>;
+		clocks = <&cru REFCLKO25M_GMAC0_OUT>;
+	};
+};
+
+&mdio1 {
+	rgmii_phy1: phy@1 {
+		compatible = "ethernet-phy-ieee802.3-c22";
+		reg = <0x1>;
+		clocks = <&cru REFCLKO25M_GMAC1_OUT>;
+	};
+};
+
+&pinctrl {
+	usb {
+		usb_host_pwren: usb-host-pwren {
+			rockchip,pins = <0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		usb_otg0_pwren: usb-otg0-pwren {
+			rockchip,pins = <0 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		usbc0_int: usbc0-int {
+			rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+	};
+};
+
+&sdmmc {
+	bus-width = <4>;
+	cap-mmc-highspeed;
+	cap-sd-highspeed;
+	disable-wp;
+	max-frequency = <200000000>;
+	no-sdio;
+	no-mmc;
+	sd-uhs-sdr104;
+	vqmmc-supply = <&vccio_sd_s0>;
+	status = "okay";
+};
+
+&saradc {
+	vref-supply = <&vcca_1v8_s0>;
+	status = "okay";
+};
+
+&u2phy0 {
+	status = "okay";
+};
+
+&u2phy0_otg {
+	phy-supply = <&vbus5v0_typec>;
+	status = "okay";
+};
+
+&u2phy1 {
+	status = "okay";
+};
+
+&u2phy1_otg {
+	phy-supply = <&vcc5v0_host>;
+	status = "okay";
+};
+
+&uart0 {
+	status = "okay";
+};
+
+&usbdp_phy {
+	rockchip,dp-lane-mux = <2 3>;
+	status = "okay";
+};
+
+&usb_drd0_dwc3 {
+	dr_mode = "host";
+	status = "okay";
+};
+
+&usb_drd1_dwc3 {
+	dr_mode = "host";
+	status = "okay";
+};
diff --git a/dts/upstream/src/arm64/rockchip/rk3576.dtsi b/dts/upstream/src/arm64/rockchip/rk3576.dtsi
index 436232ffe4d..4dde954043e 100644
--- a/dts/upstream/src/arm64/rockchip/rk3576.dtsi
+++ b/dts/upstream/src/arm64/rockchip/rk3576.dtsi
@@ -445,6 +445,58 @@
 		#size-cells = <2>;
 		ranges;
 
+		usb_drd0_dwc3: usb@23000000 {
+			compatible = "rockchip,rk3576-dwc3", "snps,dwc3";
+			reg = <0x0 0x23000000 0x0 0x400000>;
+			clocks = <&cru CLK_REF_USB3OTG0>,
+				 <&cru CLK_SUSPEND_USB3OTG0>,
+				 <&cru ACLK_USB3OTG0>;
+			clock-names = "ref_clk", "suspend_clk", "bus_clk";
+			interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>;
+			power-domains = <&power RK3576_PD_USB>;
+			resets = <&cru SRST_A_USB3OTG0>;
+			dr_mode = "otg";
+			phys = <&u2phy0_otg>, <&usbdp_phy PHY_TYPE_USB3>;
+			phy-names = "usb2-phy", "usb3-phy";
+			phy_type = "utmi_wide";
+			snps,dis_enblslpm_quirk;
+			snps,dis-u1-entry-quirk;
+			snps,dis-u2-entry-quirk;
+			snps,dis-u2-freeclk-exists-quirk;
+			snps,dis-del-phy-power-chg-quirk;
+			snps,dis-tx-ipgap-linecheck-quirk;
+			snps,parkmode-disable-hs-quirk;
+			snps,parkmode-disable-ss-quirk;
+			status = "disabled";
+		};
+
+		usb_drd1_dwc3: usb@23400000 {
+			compatible = "rockchip,rk3576-dwc3", "snps,dwc3";
+			reg = <0x0 0x23400000 0x0 0x400000>;
+			clocks = <&cru CLK_REF_USB3OTG1>,
+				 <&cru CLK_SUSPEND_USB3OTG1>,
+				 <&cru ACLK_USB3OTG1>;
+			clock-names = "ref_clk", "suspend_clk", "bus_clk";
+			interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>;
+			power-domains = <&power RK3576_PD_PHP>;
+			resets = <&cru SRST_A_USB3OTG1>;
+			dr_mode = "otg";
+			phys = <&u2phy1_otg>, <&combphy1_psu PHY_TYPE_USB3>;
+			phy-names = "usb2-phy", "usb3-phy";
+			phy_type = "utmi_wide";
+			snps,dis_enblslpm_quirk;
+			snps,dis-u1-entry-quirk;
+			snps,dis-u2-entry-quirk;
+			snps,dis-u2-freeclk-exists-quirk;
+			snps,dis-del-phy-power-chg-quirk;
+			snps,dis-tx-ipgap-linecheck-quirk;
+			snps,dis_rxdet_inp3_quirk;
+			snps,parkmode-disable-hs-quirk;
+			snps,parkmode-disable-ss-quirk;
+			dma-coherent;
+			status = "disabled";
+		};
+
 		sys_grf: syscon@2600a000 {
 			compatible = "rockchip,rk3576-sys-grf", "syscon";
 			reg = <0x0 0x2600a000 0x0 0x2000>;
@@ -515,6 +567,65 @@
 			reg = <0x0 0x2602c000 0x0 0x2000>;
 		};
 
+		usb2phy_grf: syscon@2602e000 {
+			compatible = "rockchip,rk3576-usb2phy-grf", "syscon", "simple-mfd";
+			reg = <0x0 0x2602e000 0x0 0x4000>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			u2phy0: usb2-phy@0 {
+				compatible = "rockchip,rk3576-usb2phy";
+				reg = <0x0 0x10>;
+				resets = <&cru SRST_OTGPHY_0>, <&cru SRST_P_USBPHY_GRF_0>;
+				reset-names = "phy", "apb";
+				clocks = <&cru CLK_PHY_REF_SRC>,
+					 <&cru ACLK_MMU2>,
+					 <&cru ACLK_SLV_MMU2>;
+				clock-names = "phyclk", "aclk", "aclk_slv";
+				clock-output-names = "usb480m_phy0";
+				#clock-cells = <0>;
+				status = "disabled";
+
+				u2phy0_otg: otg-port {
+					#phy-cells = <0>;
+					interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>,
+						     <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>,
+						     <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
+					interrupt-names = "otg-bvalid", "otg-id", "linestate";
+					status = "disabled";
+				};
+			};
+
+			u2phy1: usb2-phy@2000 {
+				compatible = "rockchip,rk3576-usb2phy";
+				reg = <0x2000 0x10>;
+				resets = <&cru SRST_OTGPHY_1>, <&cru SRST_P_USBPHY_GRF_1>;
+				reset-names = "phy", "apb";
+				clocks = <&cru CLK_PHY_REF_SRC>,
+					 <&cru ACLK_MMU1>,
+					 <&cru ACLK_SLV_MMU1>;
+				clock-names = "phyclk", "aclk", "aclk_slv";
+				clock-output-names = "usb480m_phy1";
+				#clock-cells = <0>;
+				status = "disabled";
+
+				u2phy1_otg: otg-port {
+					#phy-cells = <0>;
+					interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>,
+						     <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>,
+						     <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
+					interrupt-names = "otg-bvalid", "otg-id", "linestate";
+					status = "disabled";
+				};
+			};
+		};
+
+		vo1_grf: syscon@26036000 {
+			compatible = "rockchip,rk3576-vo1-grf", "syscon";
+			reg = <0x0 0x26036000 0x0 0x100>;
+			clocks = <&cru PCLK_VO1_ROOT>;
+		};
+
 		sdgmac_grf: syscon@26038000 {
 			compatible = "rockchip,rk3576-sdgmac-grf", "syscon";
 			reg = <0x0 0x26038000 0x0 0x1000>;
@@ -1587,6 +1698,64 @@
 			status = "disabled";
 		};
 
+		combphy0_ps: phy@2b050000 {
+			compatible = "rockchip,rk3576-naneng-combphy";
+			reg = <0x0 0x2b050000 0x0 0x100>;
+			#phy-cells = <1>;
+			clocks = <&cru CLK_REF_PCIE0_PHY>,
+				 <&cru PCLK_PCIE2_COMBOPHY0>,
+				 <&cru PCLK_PCIE0>;
+			clock-names = "ref", "apb", "pipe";
+			assigned-clocks = <&cru CLK_REF_PCIE0_PHY>;
+			assigned-clock-rates = <100000000>;
+			resets = <&cru SRST_PCIE0_PIPE_PHY>,
+				 <&cru SRST_P_PCIE2_COMBOPHY0>;
+			reset-names = "phy", "apb";
+			rockchip,pipe-grf = <&php_grf>;
+			rockchip,pipe-phy-grf = <&pipe_phy0_grf>;
+			status = "disabled";
+		};
+
+		combphy1_psu: phy@2b060000 {
+			compatible = "rockchip,rk3576-naneng-combphy";
+			reg = <0x0 0x2b060000 0x0 0x100>;
+			#phy-cells = <1>;
+			clocks = <&cru CLK_REF_PCIE1_PHY>,
+				 <&cru PCLK_PCIE2_COMBOPHY1>,
+				 <&cru PCLK_PCIE1>;
+			clock-names = "ref", "apb", "pipe";
+			assigned-clocks = <&cru CLK_REF_PCIE1_PHY>;
+			assigned-clock-rates = <100000000>;
+			resets = <&cru SRST_PCIE1_PIPE_PHY>,
+				 <&cru SRST_P_PCIE2_COMBOPHY1>;
+			reset-names = "phy", "apb";
+			rockchip,pipe-grf = <&php_grf>;
+			rockchip,pipe-phy-grf = <&pipe_phy1_grf>;
+			status = "disabled";
+		};
+
+		usbdp_phy: phy@2b010000 {
+			compatible = "rockchip,rk3576-usbdp-phy";
+			reg = <0x0 0x2b010000 0x0 0x10000>;
+			#phy-cells = <1>;
+			clocks = <&cru CLK_PHY_REF_SRC >,
+				 <&cru CLK_USBDP_COMBO_PHY_IMMORTAL>,
+				 <&cru PCLK_USBDPPHY>,
+				 <&u2phy0>;
+			clock-names = "refclk", "immortal", "pclk", "utmi";
+			resets = <&cru SRST_USBDP_COMBO_PHY_INIT>,
+				 <&cru SRST_USBDP_COMBO_PHY_CMN>,
+				 <&cru SRST_USBDP_COMBO_PHY_LANE>,
+				 <&cru SRST_USBDP_COMBO_PHY_PCS>,
+				 <&cru SRST_P_USBDPPHY>;
+			reset-names = "init", "cmn", "lane", "pcs_apb", "pma_apb";
+			rockchip,u2phy-grf = <&usb2phy_grf>;
+			rockchip,usb-grf = <&usb_grf>;
+			rockchip,usbdpphy-grf = <&usbdpphy_grf>;
+			rockchip,vo-grf = <&vo1_grf>;
+			status = "disabled";
+		};
+
 		sram: sram@3ff88000 {
 			compatible = "mmio-sram";
 			reg = <0x0 0x3ff88000 0x0 0x78000>;
diff --git a/dts/upstream/src/arm64/rockchip/rk3582-radxa-e52c.dts b/dts/upstream/src/arm64/rockchip/rk3582-radxa-e52c.dts
new file mode 100644
index 00000000000..e04f21d8c83
--- /dev/null
+++ b/dts/upstream/src/arm64/rockchip/rk3582-radxa-e52c.dts
@@ -0,0 +1,743 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2024 Radxa Computer (Shenzhen) Co., Ltd.
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+#include <dt-bindings/pwm/pwm.h>
+#include "rk3588s.dtsi"
+
+/ {
+	model = "Radxa E52C";
+	compatible = "radxa,e52c", "rockchip,rk3582", "rockchip,rk3588s";
+
+	aliases {
+		mmc0 = &sdhci;
+		mmc1 = &sdmmc;
+	};
+
+	chosen {
+		stdout-path = "serial2:1500000n8";
+	};
+
+	keys-0 {
+		compatible = "adc-keys";
+		io-channels = <&saradc 0>;
+		io-channel-names = "buttons";
+		keyup-threshold-microvolt = <18000>;
+		poll-interval = <100>;
+
+		button-0 {
+			label = "Maskrom";
+			linux,code = <KEY_VENDOR>;
+			press-threshold-microvolt = <0>;
+		};
+	};
+
+	keys-1 {
+		compatible = "gpio-keys";
+		pinctrl-names = "default";
+		pinctrl-0 = <&btn_0>;
+
+		button-1 {
+			label = "User";
+			gpios = <&gpio4 RK_PB3 GPIO_ACTIVE_LOW>;
+			linux,code = <BTN_0>;
+			wakeup-source;
+		};
+	};
+
+	leds-0 {
+		compatible = "gpio-leds";
+		pinctrl-names = "default";
+		pinctrl-0 = <&led_0>;
+
+		led-0 {
+			color = <LED_COLOR_ID_GREEN>;
+			default-state = "on";
+			function = LED_FUNCTION_STATUS;
+			gpios = <&gpio3 RK_PC4 GPIO_ACTIVE_HIGH>;
+			linux,default-trigger = "heartbeat";
+		};
+	};
+
+	leds-1 {
+		compatible = "pwm-leds";
+
+		led-1 {
+			color = <LED_COLOR_ID_GREEN>;
+			default-state = "on";
+			function = LED_FUNCTION_LAN;
+			linux,default-trigger = "netdev";
+			pwms = <&pwm14 0 1000000 PWM_POLARITY_INVERTED>;
+			max-brightness = <255>;
+		};
+
+		led-2 {
+			color = <LED_COLOR_ID_GREEN>;
+			default-state = "on";
+			function = LED_FUNCTION_WAN;
+			linux,default-trigger = "netdev";
+			pwms = <&pwm11 0 1000000 PWM_POLARITY_INVERTED>;
+			max-brightness = <255>;
+		};
+	};
+
+	vcc_1v1_nldo_s3: regulator-1v1 {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc_1v1_nldo_s3";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <1100000>;
+		regulator-max-microvolt = <1100000>;
+		vin-supply = <&vcc_sysin>;
+	};
+
+	vcc_3v3_pmu: regulator-3v3-0 {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc_3v3_pmu";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		vin-supply = <&vcc_3v3_s3>;
+	};
+
+	vcc_3v3_s0: regulator-3v3-1 {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc_3v3_s0";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		vin-supply = <&vcc_3v3_s3>;
+	};
+
+	vcca: regulator-4v0 {
+		compatible = "regulator-fixed";
+		regulator-name = "vcca";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <4000000>;
+		regulator-max-microvolt = <4000000>;
+		vin-supply = <&vcc_sysin>;
+	};
+
+	vcc5v0_usb_otg0: regulator-5v0-0 {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpio = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&usb_otg_pwren_h>;
+		regulator-name = "vcc5v0_usb_otg0";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		vin-supply = <&vcc_sysin>;
+	};
+
+	vcc_5v0: regulator-5v0-1 {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpio = <&gpio4 RK_PA3 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&vcc_5v0_pwren_h>;
+		regulator-name = "vcc_5v0";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		vin-supply = <&vcc_sysin>;
+	};
+
+	vcc_sysin: regulator-5v0-2 {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc_sysin";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+	};
+};
+
+&combphy0_ps {
+	status = "okay";
+};
+
+&combphy2_psu {
+	status = "okay";
+};
+
+/*
+ * In the Rockchip RK3582 SoC, some CPU cores end up disabled
+ * and unused because they're marked in the efuses as defective.
+ * The disabling in the DT is performed by the boot loader.
+ */
+&cpu_b0 {
+	cpu-supply = <&vdd_cpu_big0_s0>;
+};
+
+&cpu_b1 {
+	cpu-supply = <&vdd_cpu_big0_s0>;
+};
+
+&cpu_b2 {
+	cpu-supply = <&vdd_cpu_big1_s0>;
+};
+
+&cpu_b3 {
+	cpu-supply = <&vdd_cpu_big1_s0>;
+};
+
+&cpu_l0 {
+	cpu-supply = <&vdd_cpu_lit_s0>;
+};
+
+&cpu_l1 {
+	cpu-supply = <&vdd_cpu_lit_s0>;
+};
+
+&cpu_l2 {
+	cpu-supply = <&vdd_cpu_lit_s0>;
+};
+
+&cpu_l3 {
+	cpu-supply = <&vdd_cpu_lit_s0>;
+};
+
+&i2c0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c0m2_xfer>;
+	status = "okay";
+
+	vdd_cpu_big0_s0: regulator@42 {
+		compatible = "rockchip,rk8602";
+		reg = <0x42>;
+		fcs,suspend-voltage-selector = <1>;
+		regulator-name = "vdd_cpu_big0_s0";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <550000>;
+		regulator-max-microvolt = <1050000>;
+		regulator-ramp-delay = <2300>;
+		vin-supply = <&vcc_sysin>;
+
+		regulator-state-mem {
+			regulator-off-in-suspend;
+		};
+	};
+
+	vdd_cpu_big1_s0: regulator@43 {
+		compatible = "rockchip,rk8603", "rockchip,rk8602";
+		reg = <0x43>;
+		fcs,suspend-voltage-selector = <1>;
+		regulator-name = "vdd_cpu_big1_s0";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <550000>;
+		regulator-max-microvolt = <1050000>;
+		regulator-ramp-delay = <2300>;
+		vin-supply = <&vcc_sysin>;
+
+		regulator-state-mem {
+			regulator-off-in-suspend;
+		};
+	};
+
+	eeprom@50 {
+		compatible = "belling,bl24c16a", "atmel,24c16";
+		reg = <0x50>;
+		pagesize = <16>;
+		vcc-supply = <&vcc_3v3_pmu>;
+	};
+};
+
+&i2c2 {
+	status = "okay";
+
+	vdd_npu_s0: regulator@42 {
+		compatible = "rockchip,rk8602";
+		reg = <0x42>;
+		fcs,suspend-voltage-selector = <1>;
+		regulator-name = "vdd_npu_s0";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <550000>;
+		regulator-max-microvolt = <950000>;
+		regulator-ramp-delay = <2300>;
+		vin-supply = <&vcc_sysin>;
+
+		regulator-state-mem {
+			regulator-off-in-suspend;
+		};
+	};
+};
+
+&i2c5 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c5m2_xfer>;
+	status = "okay";
+
+	rtc@51 {
+		compatible = "haoyu,hym8563";
+		reg = <0x51>;
+		#clock-cells = <0>;
+		clock-output-names = "rtcic_32kout";
+		interrupt-parent = <&gpio0>;
+		interrupts = <RK_PB0 IRQ_TYPE_LEVEL_LOW>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&rtc_int_l>;
+		wakeup-source;
+	};
+};
+
+&pcie2x1l1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pcie20x1_1_perstn_m1>;
+	reset-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>;
+	vpcie3v3-supply = <&vcc_3v3_s3>;
+	status = "okay";
+};
+
+&pcie2x1l2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pcie20x1_2_perstn_m0>;
+	reset-gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_HIGH>;
+	vpcie3v3-supply = <&vcc_3v3_s3>;
+	status = "okay";
+};
+
+&pinctrl {
+	keys {
+		btn_0: button-0 {
+			rockchip,pins = <4 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	leds {
+		led_0: led-0 {
+			rockchip,pins = <3 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	pcie {
+		pcie20x1_1_perstn_m1: pcie-1 {
+			rockchip,pins = <4 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		pcie20x1_2_perstn_m0: pcie-2 {
+			rockchip,pins = <3 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	regulators {
+		vcc_5v0_pwren_h: regulator-5v0-1 {
+			rockchip,pins = <4 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	rtc {
+		rtc_int_l: rtc-0 {
+			rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	usb {
+		usb_otg_pwren_h: regulator-5v0-0 {
+			rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+};
+
+&pwm11 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pwm11m1_pins>;
+	status = "okay";
+};
+
+&pwm14 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pwm14m1_pins>;
+	status = "okay";
+};
+
+&saradc {
+	vref-supply = <&vcca_1v8_s0>;
+	status = "okay";
+};
+
+&sdhci {
+	bus-width = <8>;
+	cap-mmc-highspeed;
+	mmc-hs400-1_8v;
+	mmc-hs400-enhanced-strobe;
+	no-sd;
+	no-sdio;
+	non-removable;
+	vmmc-supply = <&vcc_3v3_s0>;
+	vqmmc-supply = <&vcc_1v8_s3>;
+	status = "okay";
+};
+
+&sdmmc {
+	bus-width = <4>;
+	cap-mmc-highspeed;
+	cap-sd-highspeed;
+	cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
+	disable-wp;
+	no-sdio;
+	sd-uhs-sdr104;
+	vmmc-supply = <&vcc_3v3_s3>;
+	vqmmc-supply = <&vccio_sd_s0>;
+	status = "okay";
+};
+
+&spi2 {
+	status = "okay";
+	assigned-clocks = <&cru CLK_SPI2>;
+	assigned-clock-rates = <200000000>;
+	num-cs = <1>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>;
+
+	pmic@0 {
+		compatible = "rockchip,rk806";
+		reg = <0>;
+		gpio-controller;
+		#gpio-cells = <2>;
+		interrupt-parent = <&gpio0>;
+		interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>,
+			    <&rk806_dvs2_null>, <&rk806_dvs3_null>;
+		spi-max-frequency = <1000000>;
+		system-power-controller;
+
+		vcc1-supply = <&vcc_sysin>;
+		vcc2-supply = <&vcc_sysin>;
+		vcc3-supply = <&vcc_sysin>;
+		vcc4-supply = <&vcc_sysin>;
+		vcc5-supply = <&vcc_sysin>;
+		vcc6-supply = <&vcc_sysin>;
+		vcc7-supply = <&vcc_sysin>;
+		vcc8-supply = <&vcc_sysin>;
+		vcc9-supply = <&vcc_sysin>;
+		vcc10-supply = <&vcc_sysin>;
+		vcc11-supply = <&vcc_2v0_pldo_s3>;
+		vcc12-supply = <&vcc_sysin>;
+		vcc13-supply = <&vcc_1v1_nldo_s3>;
+		vcc14-supply = <&vcc_1v1_nldo_s3>;
+		vcca-supply = <&vcca>;
+
+		rk806_dvs1_null: dvs1-null-pins {
+			pins = "gpio_pwrctrl1";
+			function = "pin_fun0";
+		};
+
+		rk806_dvs2_null: dvs2-null-pins {
+			pins = "gpio_pwrctrl2";
+			function = "pin_fun0";
+		};
+
+		rk806_dvs3_null: dvs3-null-pins {
+			pins = "gpio_pwrctrl3";
+			function = "pin_fun0";
+		};
+
+		regulators {
+			vdd_gpu_s0: dcdc-reg1 {
+				regulator-name = "vdd_gpu_s0";
+				regulator-boot-on;
+				regulator-min-microvolt = <550000>;
+				regulator-max-microvolt = <950000>;
+				regulator-ramp-delay = <12500>;
+				regulator-enable-ramp-delay = <400>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdd_cpu_lit_s0: dcdc-reg2 {
+				regulator-name = "vdd_cpu_lit_s0";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <550000>;
+				regulator-max-microvolt = <950000>;
+				regulator-ramp-delay = <12500>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdd_logic_s0: dcdc-reg3 {
+				regulator-name = "vdd_logic_s0";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <675000>;
+				regulator-max-microvolt = <750000>;
+				regulator-ramp-delay = <12500>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <750000>;
+				};
+			};
+
+			vdd_vdenc_s0: dcdc-reg4 {
+				regulator-name = "vdd_vdenc_s0";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <550000>;
+				regulator-max-microvolt = <950000>;
+				regulator-ramp-delay = <12500>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdd_ddr_s0: dcdc-reg5 {
+				regulator-name = "vdd_ddr_s0";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <675000>;
+				regulator-max-microvolt = <900000>;
+				regulator-ramp-delay = <12500>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+					regulator-suspend-microvolt = <850000>;
+				};
+			};
+
+			vdd2_ddr_s3: dcdc-reg6 {
+				regulator-name = "vdd2_ddr_s3";
+				regulator-always-on;
+				regulator-boot-on;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+				};
+			};
+
+			vcc_2v0_pldo_s3: dcdc-reg7 {
+				regulator-name = "vcc_2v0_pldo_s3";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <2000000>;
+				regulator-max-microvolt = <2000000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <2000000>;
+				};
+			};
+
+			vcc_3v3_s3: dcdc-reg8 {
+				regulator-name = "vcc_3v3_s3";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <3300000>;
+				};
+			};
+
+			vddq_ddr_s0: dcdc-reg9 {
+				regulator-name = "vddq_ddr_s0";
+				regulator-always-on;
+				regulator-boot-on;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_1v8_s3: dcdc-reg10 {
+				regulator-name = "vcc_1v8_s3";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			vcc_1v8_s0: pldo-reg1 {
+				regulator-name = "vcc_1v8_s0";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			vcca_1v8_s0: pldo-reg2 {
+				regulator-name = "vcca_1v8_s0";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			vdda_1v2_s0: pldo-reg3 {
+				regulator-name = "vdda_1v2_s0";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1200000>;
+				regulator-max-microvolt = <1200000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcca_3v3_s0: pldo-reg4 {
+				regulator-name = "vcca_3v3_s0";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <3300000>;
+				};
+			};
+
+			vccio_sd_s0: pldo-reg5 {
+				regulator-name = "vccio_sd_s0";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			pldo6_s3: pldo-reg6 {
+				regulator-name = "pldo6_s3";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			vdd_0v75_s3: nldo-reg1 {
+				regulator-name = "vdd_0v75_s3";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <750000>;
+				regulator-max-microvolt = <750000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <750000>;
+				};
+			};
+
+			vdda_ddr_pll_s0: nldo-reg2 {
+				regulator-name = "vdda_ddr_pll_s0";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <850000>;
+				regulator-max-microvolt = <850000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <850000>;
+				};
+			};
+
+			vdda_0v75_s0: nldo-reg3 {
+				regulator-name = "vdda_0v75_s0";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <750000>;
+				regulator-max-microvolt = <750000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <750000>;
+				};
+			};
+
+			vdda_0v85_s0: nldo-reg4 {
+				regulator-name = "vdda_0v85_s0";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <850000>;
+				regulator-max-microvolt = <850000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdd_0v75_s0: nldo-reg5 {
+				regulator-name = "vdd_0v75_s0";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <750000>;
+				regulator-max-microvolt = <750000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+		};
+	};
+};
+
+&tsadc {
+	status = "okay";
+};
+
+&u2phy0 {
+	status = "okay";
+};
+
+&u2phy0_otg {
+	phy-supply = <&vcc5v0_usb_otg0>;
+	status = "okay";
+};
+
+&uart2 {
+	pinctrl-0 = <&uart2m0_xfer>;
+	status = "okay";
+};
+
+&usb_host0_xhci {
+	dr_mode = "host";
+	status = "okay";
+};
+
+&usbdp_phy0 {
+	status = "okay";
+};
diff --git a/dts/upstream/src/arm64/rockchip/rk3588-base.dtsi b/dts/upstream/src/arm64/rockchip/rk3588-base.dtsi
index a337f3fb837..c3abdfb04f8 100644
--- a/dts/upstream/src/arm64/rockchip/rk3588-base.dtsi
+++ b/dts/upstream/src/arm64/rockchip/rk3588-base.dtsi
@@ -549,22 +549,21 @@
 	mmu600_pcie: iommu@fc900000 {
 		compatible = "arm,smmu-v3";
 		reg = <0x0 0xfc900000 0x0 0x200000>;
-		interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH 0>,
-			     <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH 0>,
-			     <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH 0>,
-			     <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH 0>;
+		interrupts = <GIC_SPI 369 IRQ_TYPE_EDGE_RISING 0>,
+			     <GIC_SPI 371 IRQ_TYPE_EDGE_RISING 0>,
+			     <GIC_SPI 374 IRQ_TYPE_EDGE_RISING 0>,
+			     <GIC_SPI 367 IRQ_TYPE_EDGE_RISING 0>;
 		interrupt-names = "eventq", "gerror", "priq", "cmdq-sync";
 		#iommu-cells = <1>;
-		status = "disabled";
 	};
 
 	mmu600_php: iommu@fcb00000 {
 		compatible = "arm,smmu-v3";
 		reg = <0x0 0xfcb00000 0x0 0x200000>;
-		interrupts = <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH 0>,
-			     <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH 0>,
-			     <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH 0>,
-			     <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH 0>;
+		interrupts = <GIC_SPI 381 IRQ_TYPE_EDGE_RISING 0>,
+			     <GIC_SPI 383 IRQ_TYPE_EDGE_RISING 0>,
+			     <GIC_SPI 386 IRQ_TYPE_EDGE_RISING 0>,
+			     <GIC_SPI 379 IRQ_TYPE_EDGE_RISING 0>;
 		interrupt-names = "eventq", "gerror", "priq", "cmdq-sync";
 		#iommu-cells = <1>;
 		status = "disabled";
@@ -1686,6 +1685,7 @@
 		linux,pci-domain = <3>;
 		max-link-speed = <2>;
 		msi-map = <0x3000 &its0 0x3000 0x1000>;
+		iommu-map = <0x3000 &mmu600_pcie 0x3000 0x1000>;
 		num-lanes = <1>;
 		phys = <&combphy2_psu PHY_TYPE_PCIE>;
 		phy-names = "pcie-phy";
@@ -1737,6 +1737,7 @@
 		linux,pci-domain = <4>;
 		max-link-speed = <2>;
 		msi-map = <0x4000 &its0 0x4000 0x1000>;
+		iommu-map = <0x4000 &mmu600_pcie 0x4000 0x1000>;
 		num-lanes = <1>;
 		phys = <&combphy0_ps PHY_TYPE_PCIE>;
 		phy-names = "pcie-phy";
@@ -2667,9 +2668,9 @@
 		rockchip,hw-tshut-temp = <120000>;
 		rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */
 		rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */
-		pinctrl-0 = <&tsadc_gpio_func>;
-		pinctrl-1 = <&tsadc_shut>;
-		pinctrl-names = "gpio", "otpout";
+		pinctrl-0 = <&tsadc_shut_org>;
+		pinctrl-1 = <&tsadc_gpio_func>;
+		pinctrl-names = "default", "sleep";
 		#thermal-sensor-cells = <1>;
 		status = "disabled";
 	};
diff --git a/dts/upstream/src/arm64/rockchip/rk3588-coolpi-cm5-genbook.dts b/dts/upstream/src/arm64/rockchip/rk3588-coolpi-cm5-genbook.dts
index 92f0ed83c99..bc6b43a7715 100644
--- a/dts/upstream/src/arm64/rockchip/rk3588-coolpi-cm5-genbook.dts
+++ b/dts/upstream/src/arm64/rockchip/rk3588-coolpi-cm5-genbook.dts
@@ -113,7 +113,7 @@
 		compatible = "regulator-fixed";
 		regulator-name = "vcc3v3_lcd";
 		enable-active-high;
-		gpio = <&gpio1 RK_PC4 GPIO_ACTIVE_HIGH>;
+		gpio = <&gpio0 RK_PC4 GPIO_ACTIVE_HIGH>;
 		pinctrl-names = "default";
 		pinctrl-0 = <&lcdpwr_en>;
 		vin-supply = <&vcc3v3_sys>;
@@ -241,7 +241,7 @@
 &pinctrl {
 	lcd {
 		lcdpwr_en: lcdpwr-en {
-			rockchip,pins = <1 RK_PC4 RK_FUNC_GPIO &pcfg_pull_down>;
+			rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_down>;
 		};
 
 		bl_en: bl-en {
diff --git a/dts/upstream/src/arm64/rockchip/rk3588-edgeble-neu6a-io.dtsi b/dts/upstream/src/arm64/rockchip/rk3588-edgeble-neu6a-io.dtsi
index 05ae9bdcfbb..7125790bbed 100644
--- a/dts/upstream/src/arm64/rockchip/rk3588-edgeble-neu6a-io.dtsi
+++ b/dts/upstream/src/arm64/rockchip/rk3588-edgeble-neu6a-io.dtsi
@@ -10,6 +10,15 @@
 		stdout-path = "serial2:1500000n8";
 	};
 
+	/* Unnamed gated oscillator: 100MHz,3.3V,3225 */
+	pcie30_port0_refclk: pcie30_port1_refclk: pcie-oscillator {
+		compatible = "gated-fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <100000000>;
+		clock-output-names = "pcie30_refclk";
+		vdd-supply = <&vcc3v3_pi6c_05>;
+	};
+
 	vcc3v3_pcie2x1l0: regulator-vcc3v3-pcie2x1l0 {
 		compatible = "regulator-fixed";
 		regulator-name = "vcc3v3_pcie2x1l0";
@@ -19,26 +28,26 @@
 		vin-supply = <&vcc_3v3_s3>;
 	};
 
-	vcc3v3_pcie3x2: regulator-vcc3v3-pcie3x2 {
+	vcc3v3_bkey: regulator-vcc3v3-bkey {
 		compatible = "regulator-fixed";
 		enable-active-high;
 		gpios = <&gpio2 RK_PC4 GPIO_ACTIVE_HIGH>; /* PCIE_4G_PWEN */
 		pinctrl-names = "default";
-		pinctrl-0 = <&pcie3x2_vcc3v3_en>;
-		regulator-name = "vcc3v3_pcie3x2";
+		pinctrl-0 = <&pcie_4g_pwen>;
+		regulator-name = "vcc3v3_bkey";
 		regulator-min-microvolt = <3300000>;
 		regulator-max-microvolt = <3300000>;
 		startup-delay-us = <5000>;
 		vin-supply = <&vcc5v0_sys>;
 	};
 
-	vcc3v3_pcie3x4: regulator-vcc3v3-pcie3x4 {
+	vcc3v3_pcie30: vcc3v3_pi6c_05: regulator-vcc3v3-pi6c-05 {
 		compatible = "regulator-fixed";
 		enable-active-high;
 		gpios = <&gpio2 RK_PC5 GPIO_ACTIVE_HIGH>; /* PCIE30x4_PWREN_H */
 		pinctrl-names = "default";
-		pinctrl-0 = <&pcie3x4_vcc3v3_en>;
-		regulator-name = "vcc3v3_pcie3x4";
+		pinctrl-0 = <&pcie30x4_pwren_h>;
+		regulator-name = "vcc3v3_pcie30";
 		regulator-min-microvolt = <3300000>;
 		regulator-max-microvolt = <3300000>;
 		startup-delay-us = <5000>;
@@ -98,24 +107,52 @@
 };
 
 &pcie30phy {
+	data-lanes = <1 1 2 2>;
+	/* separate clock lines from the clock generator to phy and devices */
+	rockchip,rx-common-refclk-mode = <0 0 0 0>;
 	status = "okay";
 };
 
-/* B-Key and E-Key */
+/* M-Key */
 &pcie3x2 {
+	/*
+	 * The board has a "pcie_refclk" oscillator that needs enabling,
+	 * so add it to the list of clocks.
+	 */
+	clocks = <&cru ACLK_PCIE_2L_MSTR>, <&cru ACLK_PCIE_2L_SLV>,
+		 <&cru ACLK_PCIE_2L_DBI>, <&cru PCLK_PCIE_2L>,
+		 <&cru CLK_PCIE_AUX1>, <&cru CLK_PCIE2L_PIPE>,
+		 <&pcie30_port1_refclk>;
+	clock-names = "aclk_mst", "aclk_slv",
+		      "aclk_dbi", "pclk",
+		      "aux", "pipe",
+		      "ref";
+	num-lanes = <2>;
 	pinctrl-names = "default";
-	pinctrl-0 = <&pcie3x2_rst>;
-	reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; /* PCIE30X4_PERSTn_M1_L */
-	vpcie3v3-supply = <&vcc3v3_pcie3x2>;
+	pinctrl-0 = <&pcie30x2_perstn_m1_l>;
+	reset-gpios = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>; /* PCIE30X2_PERSTn_M1_L */
+	vpcie3v3-supply = <&vcc3v3_pcie30>;
 	status = "okay";
 };
 
-/* M-Key */
+/* B-Key and E-Key */
 &pcie3x4 {
+	/*
+	 * The board has a "pcie_refclk" oscillator that needs enabling,
+	 * so add it to the list of clocks.
+	 */
+	clocks = <&cru ACLK_PCIE_4L_MSTR>, <&cru ACLK_PCIE_4L_SLV>,
+		 <&cru ACLK_PCIE_4L_DBI>, <&cru PCLK_PCIE_4L>,
+		 <&cru CLK_PCIE_AUX0>, <&cru CLK_PCIE4L_PIPE>,
+		 <&pcie30_port0_refclk>;
+	clock-names = "aclk_mst", "aclk_slv",
+		      "aclk_dbi", "pclk",
+		      "aux", "pipe",
+		      "ref";
 	pinctrl-names = "default";
-	pinctrl-0 = <&pcie3x4_rst>;
-	reset-gpios = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>; /* PCIE30X2_PERSTn_M1_L */
-	vpcie3v3-supply = <&vcc3v3_pcie3x4>;
+	pinctrl-0 = <&pcie30x4_perstn_m1_l>;
+	reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; /* PCIE30X4_PERSTn_M1_L */
+	vpcie3v3-supply = <&vcc3v3_bkey>;
 	status = "okay";
 };
 
@@ -127,20 +164,20 @@
 	};
 
 	pcie3 {
-		pcie3x2_rst: pcie3x2-rst {
-			rockchip,pins = <4 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>;
+		pcie30x2_perstn_m1_l: pcie30x2-perstn-m1-l {
+			rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
 		};
 
-		pcie3x2_vcc3v3_en: pcie3x2-vcc3v3-en {
-			rockchip,pins = <2 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>;
+		pcie_4g_pwen: pcie-4g-pwen {
+			rockchip,pins = <2 RK_PC4 RK_FUNC_GPIO &pcfg_pull_down>;
 		};
 
-		pcie3x4_rst: pcie3x4-rst {
-			rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
+		pcie30x4_perstn_m1_l: pcie30x4-perstn-m1-l {
+			rockchip,pins = <4 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>;
 		};
 
-		pcie3x4_vcc3v3_en: pcie3x4-vcc3v3-en {
-			rockchip,pins = <2 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
+		pcie30x4_pwren_h: pcie30x4-pwren-h {
+			rockchip,pins = <2 RK_PC5 RK_FUNC_GPIO &pcfg_pull_down>;
 		};
 	};
 
diff --git a/dts/upstream/src/arm64/rockchip/rk3588-evb1-v10.dts b/dts/upstream/src/arm64/rockchip/rk3588-evb1-v10.dts
index d6e464cdc53..ba49f0bbaac 100644
--- a/dts/upstream/src/arm64/rockchip/rk3588-evb1-v10.dts
+++ b/dts/upstream/src/arm64/rockchip/rk3588-evb1-v10.dts
@@ -206,6 +206,28 @@
 		pinctrl-0 = <&vcc3v3_pcie30_en>;
 	};
 
+	vcc3v3_pciewl_vbat: regulator-vcc3v3-pciewl-vbat {
+		compatible = "regulator-fixed";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-name = "wlan-vbat";
+		vin-supply = <&vcc_3v3_s0>;
+	};
+
+	vcc3v3_wlan: regulator-vcc3v3-wlan {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpios = <&gpio3 RK_PB1 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&wifi_pwren>;
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-name = "wlan-en";
+		vin-supply = <&vcc3v3_pciewl_vbat>;
+	};
+
 	vcc5v0_host: regulator-vcc5v0-host {
 		compatible = "regulator-fixed";
 		regulator-name = "vcc5v0_host";
@@ -249,12 +271,26 @@
 		regulator-max-microvolt = <5000000>;
 		vin-supply = <&vcc5v0_usbdcin>;
 	};
+
+	vccio_wl: regulator-vccio-wl {
+		compatible = "regulator-fixed";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+		regulator-name = "wlan-vddio";
+		vin-supply = <&vcc_1v8_s0>;
+	};
 };
 
 &combphy0_ps {
 	status = "okay";
 };
 
+&combphy1_ps {
+	status = "okay";
+};
+
 &combphy2_psu {
 	status = "okay";
 };
@@ -440,6 +476,30 @@
 	};
 };
 
+&pcie2x1l0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pcie2_0_rst>, <&pcie2_0_wake>, <&pcie2_0_clkreq>, <&wifi_host_wake_irq>;
+	reset-gpios = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>;
+	vpcie3v3-supply = <&vcc3v3_wlan>;
+	status = "okay";
+
+	pcie@0,0 {
+		reg = <0x200000 0 0 0 0>;
+		#address-cells = <3>;
+		#size-cells = <2>;
+		ranges;
+		device_type = "pci";
+		bus-range = <0x20 0x2f>;
+
+		wifi: wifi@0,0 {
+			compatible = "pci14e4,449d";
+			reg = <0x210000 0 0 0 0>;
+			clocks = <&hym8563>;
+			clock-names = "lpo";
+		};
+	};
+};
+
 &pcie2x1l1 {
 	reset-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>;
 	pinctrl-names = "default";
@@ -494,6 +554,18 @@
 	};
 
 	pcie2 {
+		pcie2_0_rst: pcie2-0-rst {
+			rockchip,pins = <4 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		pcie2_0_wake: pcie2-0-wake {
+			rockchip,pins = <4 RK_PA4 4 &pcfg_pull_none>;
+		};
+
+		pcie2_0_clkreq: pcie2-0-clkreq {
+			rockchip,pins = <4 RK_PA3 4 &pcfg_pull_none>;
+		};
+
 		pcie2_1_rst: pcie2-1-rst {
 			rockchip,pins = <4 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
 		};
@@ -524,6 +596,16 @@
 			rockchip,pins = <3 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up>;
 		};
 	};
+
+	wlan {
+		wifi_host_wake_irq: wifi-host-wake-irq {
+			rockchip,pins = <3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_down>;
+		};
+
+		wifi_pwren: wifi-pwren {
+			rockchip,pins = <3 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+	};
 };
 
 &pwm2 {
diff --git a/dts/upstream/src/arm64/rockchip/rk3588-extra.dtsi b/dts/upstream/src/arm64/rockchip/rk3588-extra.dtsi
index 0ce0934ec6b..840b638af1c 100644
--- a/dts/upstream/src/arm64/rockchip/rk3588-extra.dtsi
+++ b/dts/upstream/src/arm64/rockchip/rk3588-extra.dtsi
@@ -162,6 +162,7 @@
 		linux,pci-domain = <0>;
 		max-link-speed = <3>;
 		msi-map = <0x0000 &its1 0x0000 0x1000>;
+		iommu-map = <0x0000 &mmu600_pcie 0x0000 0x1000>;
 		num-lanes = <4>;
 		phys = <&pcie30phy>;
 		phy-names = "pcie-phy";
@@ -248,6 +249,7 @@
 		linux,pci-domain = <1>;
 		max-link-speed = <3>;
 		msi-map = <0x1000 &its1 0x1000 0x1000>;
+		iommu-map = <0x1000 &mmu600_pcie 0x1000 0x1000>;
 		num-lanes = <2>;
 		phys = <&pcie30phy>;
 		phy-names = "pcie-phy";
@@ -297,6 +299,7 @@
 		linux,pci-domain = <2>;
 		max-link-speed = <2>;
 		msi-map = <0x2000 &its0 0x2000 0x1000>;
+		iommu-map = <0x2000 &mmu600_pcie 0x2000 0x1000>;
 		num-lanes = <1>;
 		phys = <&combphy1_ps PHY_TYPE_PCIE>;
 		phy-names = "pcie-phy";
diff --git a/dts/upstream/src/arm64/rockchip/rk3588-firefly-core-3588j.dtsi b/dts/upstream/src/arm64/rockchip/rk3588-firefly-core-3588j.dtsi
new file mode 100644
index 00000000000..42c523b553c
--- /dev/null
+++ b/dts/upstream/src/arm64/rockchip/rk3588-firefly-core-3588j.dtsi
@@ -0,0 +1,443 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+
+#include "rk3588.dtsi"
+
+/ {
+	compatible = "firefly,core-3588j", "rockchip,rk3588";
+
+	aliases {
+		mmc0 = &sdhci;
+	};
+};
+
+&cpu_b0 {
+	cpu-supply = <&vdd_cpu_big0_s0>;
+};
+
+&cpu_b1 {
+	cpu-supply = <&vdd_cpu_big0_s0>;
+};
+
+&cpu_b2 {
+	cpu-supply = <&vdd_cpu_big1_s0>;
+};
+
+&cpu_b3 {
+	cpu-supply = <&vdd_cpu_big1_s0>;
+};
+
+&cpu_l0 {
+	cpu-supply = <&vdd_cpu_lit_s0>;
+};
+
+&cpu_l1 {
+	cpu-supply = <&vdd_cpu_lit_s0>;
+};
+
+&cpu_l2 {
+	cpu-supply = <&vdd_cpu_lit_s0>;
+};
+
+&cpu_l3 {
+	cpu-supply = <&vdd_cpu_lit_s0>;
+};
+
+&i2c0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c0m2_xfer>;
+	status = "okay";
+
+	vdd_cpu_big0_s0: regulator@42 {
+		compatible = "rockchip,rk8602";
+		reg = <0x42>;
+		fcs,suspend-voltage-selector = <1>;
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <550000>;
+		regulator-max-microvolt = <1050000>;
+		regulator-name = "vdd_cpu_big0_s0";
+		regulator-ramp-delay = <2300>;
+		vin-supply = <&vcc5v0_sys>;
+
+		regulator-state-mem {
+			regulator-off-in-suspend;
+		};
+	};
+
+	vdd_cpu_big1_s0: regulator@43 {
+		compatible = "rockchip,rk8603", "rockchip,rk8602";
+		reg = <0x43>;
+		fcs,suspend-voltage-selector = <1>;
+		regulator-name = "vdd_cpu_big1_s0";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <550000>;
+		regulator-max-microvolt = <1050000>;
+		regulator-ramp-delay = <2300>;
+		vin-supply = <&vcc5v0_sys>;
+
+		regulator-state-mem {
+			regulator-off-in-suspend;
+		};
+	};
+};
+
+&i2c1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c1m2_xfer>;
+	status = "okay";
+
+	vdd_npu_s0: vdd_npu_mem_s0: regulator@42 {
+		compatible = "rockchip,rk8602";
+		reg = <0x42>;
+		fcs,suspend-voltage-selector = <1>;
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <550000>;
+		regulator-max-microvolt = <950000>;
+		regulator-name = "vdd_npu_s0";
+		regulator-ramp-delay = <2300>;
+		vin-supply = <&vcc5v0_sys>;
+
+		regulator-state-mem {
+			regulator-off-in-suspend;
+		};
+	};
+};
+
+&sdhci {
+	bus-width = <8>;
+	no-sdio;
+	no-sd;
+	non-removable;
+	mmc-hs400-1_8v;
+	mmc-hs400-enhanced-strobe;
+	status = "okay";
+};
+
+&spi2 {
+	assigned-clocks = <&cru CLK_SPI2>;
+	assigned-clock-rates = <200000000>;
+	num-cs = <1>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>;
+	status = "okay";
+
+	pmic@0 {
+		compatible = "rockchip,rk806";
+		reg = <0x0>;
+		interrupt-parent = <&gpio0>;
+		interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
+		gpio-controller;
+		#gpio-cells = <2>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>,
+			    <&rk806_dvs2_null>, <&rk806_dvs3_null>;
+		spi-max-frequency = <1000000>;
+		system-power-controller;
+
+		vcc1-supply = <&vcc5v0_sys>;
+		vcc2-supply = <&vcc5v0_sys>;
+		vcc3-supply = <&vcc5v0_sys>;
+		vcc4-supply = <&vcc5v0_sys>;
+		vcc5-supply = <&vcc5v0_sys>;
+		vcc6-supply = <&vcc5v0_sys>;
+		vcc7-supply = <&vcc5v0_sys>;
+		vcc8-supply = <&vcc5v0_sys>;
+		vcc9-supply = <&vcc5v0_sys>;
+		vcc10-supply = <&vcc5v0_sys>;
+		vcc11-supply = <&vcc_2v0_pldo_s3>;
+		vcc12-supply = <&vcc5v0_sys>;
+		vcc13-supply = <&vcc_1v1_nldo_s3>;
+		vcc14-supply = <&vcc_1v1_nldo_s3>;
+		vcca-supply = <&vcc5v0_sys>;
+
+		rk806_dvs1_null: dvs1-null-pins {
+			pins = "gpio_pwrctrl1";
+			function = "pin_fun0";
+		};
+
+		rk806_dvs2_null: dvs2-null-pins {
+			pins = "gpio_pwrctrl2";
+			function = "pin_fun0";
+		};
+
+		rk806_dvs3_null: dvs3-null-pins {
+			pins = "gpio_pwrctrl3";
+			function = "pin_fun0";
+		};
+
+		regulators {
+			vdd_gpu_s0: vdd_gpu_mem_s0: dcdc-reg1 {
+				regulator-boot-on;
+				regulator-min-microvolt = <550000>;
+				regulator-max-microvolt = <950000>;
+				regulator-ramp-delay = <12500>;
+				regulator-name = "vdd_gpu_s0";
+				regulator-enable-ramp-delay = <400>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdd_cpu_lit_s0: vdd_cpu_lit_mem_s0: dcdc-reg2 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <550000>;
+				regulator-max-microvolt = <950000>;
+				regulator-ramp-delay = <12500>;
+				regulator-name = "vdd_cpu_lit_s0";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdd_log_s0: dcdc-reg3 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <675000>;
+				regulator-max-microvolt = <750000>;
+				regulator-ramp-delay = <12500>;
+				regulator-name = "vdd_log_s0";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+					regulator-suspend-microvolt = <750000>;
+				};
+			};
+
+			vdd_vdenc_s0: vdd_vdenc_mem_s0: dcdc-reg4 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <550000>;
+				regulator-max-microvolt = <950000>;
+				regulator-ramp-delay = <12500>;
+				regulator-name = "vdd_vdenc_s0";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdd_ddr_s0: dcdc-reg5 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <675000>;
+				regulator-max-microvolt = <900000>;
+				regulator-ramp-delay = <12500>;
+				regulator-name = "vdd_ddr_s0";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+					regulator-suspend-microvolt = <850000>;
+				};
+			};
+
+			vdd2_ddr_s3: dcdc-reg6 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-name = "vdd2_ddr_s3";
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+				};
+			};
+
+			vcc_2v0_pldo_s3: dcdc-reg7 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <2000000>;
+				regulator-max-microvolt = <2000000>;
+				regulator-name = "vdd_2v0_pldo_s3";
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <2000000>;
+				};
+			};
+
+			vcc_3v3_s3: dcdc-reg8 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-name = "vcc_3v3_s3";
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <3300000>;
+				};
+			};
+
+			vddq_ddr_s0: dcdc-reg9 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-name = "vddq_ddr_s0";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_1v8_s3: dcdc-reg10 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-name = "vcc_1v8_s3";
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			avcc_1v8_s0: pldo-reg1 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-name = "avcc_1v8_s0";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_1v8_s0: pldo-reg2 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-name = "vcc_1v8_s0";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			avdd_1v2_s0: pldo-reg3 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1200000>;
+				regulator-max-microvolt = <1200000>;
+				regulator-name = "avdd_1v2_s0";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			avcc_3v3_s0: pldo-reg4 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-name = "avcc_3v3_s0";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vccio_sd_s0: pldo-reg5 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-name = "vccio_sd_s0";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			pldo6_s3: pldo-reg6 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-name = "pldo6_s3";
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			vdd_0v75_s3: nldo-reg1 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <750000>;
+				regulator-max-microvolt = <750000>;
+				regulator-name = "vdd_0v75_s3";
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <750000>;
+				};
+			};
+
+			avdd_ddr_pll_s0: nldo-reg2 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <850000>;
+				regulator-max-microvolt = <850000>;
+				regulator-name = "avdd_ddr_pll_s0";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+					regulator-suspend-microvolt = <850000>;
+				};
+			};
+
+			avdd_0v75_s0: nldo-reg3 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <750000>;
+				regulator-max-microvolt = <750000>;
+				regulator-name = "avdd_0v75_s0";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			avdd_0v85_s0: nldo-reg4 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <850000>;
+				regulator-max-microvolt = <850000>;
+				regulator-name = "avdd_0v85_s0";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdd_0v75_s0: nldo-reg5 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <750000>;
+				regulator-max-microvolt = <750000>;
+				regulator-name = "vdd_0v75_s0";
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+		};
+	};
+};
+
+/* rk3588 preferred debug out */
+&uart2 {
+	pinctrl-0 = <&uart2m0_xfer>;
+	status = "okay";
+};
diff --git a/dts/upstream/src/arm64/rockchip/rk3588-firefly-itx-3588j.dts b/dts/upstream/src/arm64/rockchip/rk3588-firefly-itx-3588j.dts
new file mode 100644
index 00000000000..2be5251d3e3
--- /dev/null
+++ b/dts/upstream/src/arm64/rockchip/rk3588-firefly-itx-3588j.dts
@@ -0,0 +1,702 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+#include <dt-bindings/pwm/pwm.h>
+#include <dt-bindings/soc/rockchip,vop2.h>
+#include "dt-bindings/usb/pd.h"
+
+#include "rk3588-firefly-core-3588j.dtsi"
+
+/ {
+	model = "Firefly ITX-3588J";
+	compatible = "firefly,itx-3588j", "firefly,core-3588j", "rockchip,rk3588";
+
+	aliases {
+		ethernet0 = &gmac0;
+		ethernet1 = &gmac1;
+	};
+
+	chosen {
+		stdout-path = "serial2:1500000n8";
+	};
+
+	/*
+	 * there are also a "Reset" and "Mask ROM" button, but the needed
+	 * settings are unknown at this time
+	 */
+	adc-keys-0 {
+		compatible = "adc-keys";
+		io-channels = <&saradc 1>;
+		io-channel-names = "buttons";
+		keyup-threshold-microvolt = <1800000>;
+		poll-interval = <100>;
+
+		button-recovery {
+			label = "Recovery";
+			linux,code = <KEY_VENDOR>;
+			press-threshold-microvolt = <2000>;
+		};
+	};
+
+	analog-sound {
+		compatible = "simple-audio-card";
+		pinctrl-0 = <&hp_detect>;
+		pinctrl-names = "default";
+		simple-audio-card,aux-devs = <&amp_headphones>, <&amp_speaker>;
+		simple-audio-card,format = "i2s";
+		simple-audio-card,hp-det-gpios = <&gpio1 RK_PC4 GPIO_ACTIVE_LOW>;
+		simple-audio-card,mclk-fs = <384>;
+		simple-audio-card,name = "rockchip_es8323";
+		simple-audio-card,pin-switches = "Headphones", "Speaker";
+		simple-audio-card,routing =
+			"Speaker Amplifier INL", "LOUT2",
+			"Speaker Amplifier INR", "ROUT2",
+			"Speaker", "Speaker Amplifier OUTL",
+			"Speaker", "Speaker Amplifier OUTR",
+			"Headphones Amplifier INL", "LOUT1",
+			"Headphones Amplifier INR", "ROUT1",
+			"Headphones", "Headphones Amplifier OUTL",
+			"Headphones", "Headphones Amplifier OUTR",
+			"LINPUT1", "Microphone Jack",
+			"RINPUT1", "Microphone Jack",
+			"LINPUT2", "Onboard Microphone",
+			"RINPUT2", "Onboard Microphone";
+		simple-audio-card,widgets =
+			"Microphone", "Microphone Jack",
+			"Microphone", "Onboard Microphone",
+			"Headphone", "Headphones",
+			"Speaker", "Speaker";
+
+		simple-audio-card,cpu {
+			sound-dai = <&i2s0_8ch>;
+		};
+
+		simple-audio-card,codec {
+			sound-dai = <&es8323>;
+			system-clock-frequency = <12288000>;
+		};
+	};
+
+	/*
+	 * this does not seem to be a proper "amplifier" but is just
+	 * a way to control the GPIO pins to switch on or off the given
+	 * sound output device
+	 */
+	amp_headphones: headphones-audio-amplifier {
+		compatible = "simple-audio-amplifier";
+		enable-gpios = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&headphone_amplifier_en>;
+		sound-name-prefix = "Headphones Amplifier";
+	};
+
+	amp_speaker: speaker-audio-amplifier {
+		compatible = "simple-audio-amplifier";
+		enable-gpios = <&gpio3 RK_PB2 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&speaker_amplifier_en>;
+		sound-name-prefix = "Speaker Amplifier";
+	};
+
+	fan: pwm-fan {
+		compatible = "pwm-fan";
+		#cooling-cells = <2>;
+		cooling-levels = <0 120 150 180 210 240 255>;
+		fan-supply = <&vcc12v_dcin>;
+		pwms = <&pwm15 0 50000 1>;
+	};
+
+	hdmi0-con {
+		compatible = "hdmi-connector";
+		type = "a";
+
+		port {
+			hdmi0_con_in: endpoint {
+				remote-endpoint = <&hdmi0_out_con>;
+			};
+		};
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		/*
+		 * There is also a Power LED control @ RK_PB3 on
+		 * GPIO1 but for some reason it doesn't seem to work right
+		 */
+
+		user_led: led-1 {
+			gpios = <&pca9555 3 GPIO_ACTIVE_HIGH>;
+			linux,default-trigger = "disk-activity";
+		};
+	};
+
+	pcie30_avdd0v75: regulator-pcie30-avdd0v75 {
+		compatible = "regulator-fixed";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <750000>;
+		regulator-max-microvolt = <750000>;
+		regulator-name = "pcie30_avdd0v75";
+		vin-supply = <&avdd_0v75_s0>;
+	};
+
+	vbus5v0_typec_pwr_en: regulator-vbus5v0-typec-pwr-en {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpios = <&pca9555 12 GPIO_ACTIVE_HIGH>;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		regulator-name = "vbus5v0_typec_pwr_en";
+	};
+
+	vcc12v_dcin: regulator-vcc12v-dcin {
+		compatible = "regulator-fixed";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <12000000>;
+		regulator-max-microvolt = <12000000>;
+		regulator-name = "vcc12v_dcin";
+	};
+
+	vcc3v3_pcie30: regulator-vcc3v3-pcie30 {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpios = <&gpio2 RK_PC5 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pcie3_vcc3v3_en>;
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-name = "vcc3v3_pcie30";
+		startup-delay-us = <5000>;
+		vin-supply = <&vcc12v_dcin>;
+	};
+
+	vcc5v0_host: regulator-vcc5v0-host {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpios = <&pca9555 5 GPIO_ACTIVE_HIGH>;
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		regulator-name = "vcc5v0_host";
+		vin-supply = <&vcc5v0_usb>;
+	};
+
+	vcc5v0_host3: regulator-vcc5v0-host3 {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpios = <&pca9555 7 GPIO_ACTIVE_HIGH>;
+		regulator-name = "vcc5v0_host3";
+		regulator-boot-on;
+		regulator-always-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		vin-supply = <&vcc5v0_usb>;
+	};
+
+	vcc5v0_sys: regulator-vcc5v0-sys {
+		compatible = "regulator-fixed";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		regulator-name = "vcc5v0_sys";
+		vin-supply = <&vcc12v_dcin>;
+	};
+
+	vcc5v0_usb: regulator-vcc5v0-usb {
+		compatible = "regulator-fixed";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		regulator-name = "vcc5v0_usb";
+		vin-supply = <&vcc12v_dcin>;
+	};
+
+	vcc_1v1_nldo_s3: regulator-vcc-1v1-nldo-s3 {
+		compatible = "regulator-fixed";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <1100000>;
+		regulator-max-microvolt = <1100000>;
+		regulator-name = "vcc_1v1_nldo_s3";
+		vin-supply = <&vcc5v0_sys>;
+	};
+
+	vcc_fan_pwr_en: regulator-vcc-fan-pwr-en {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpios = <&pca9555 11 GPIO_ACTIVE_HIGH>;
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-name = "vcc_fan_pwr_en";
+	};
+
+	vcc_hub_reset: regulator-vcc-hub-reset {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpios = <&pca9555 4 GPIO_ACTIVE_HIGH>;
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-name = "vcc_hub_reset";
+	};
+
+	vcc_hub3_reset: regulator-vcc-hub3-reset {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpios = <&pca9555 6 GPIO_ACTIVE_HIGH>;
+		regulator-always-on;
+		regulator-name = "vcc_hub3_reset";
+	};
+
+	vcc_sata_pwr_en: regulator-vcc-sata-pwr-en {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpios = <&pca9555 10 GPIO_ACTIVE_HIGH>;
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-name = "vcc_sata_pwr_en";
+	};
+};
+
+&avcc_1v8_s0 {
+	regulator-state-mem {
+		regulator-on-in-suspend;
+	};
+};
+
+&combphy0_ps {
+	status = "okay";
+};
+
+&combphy1_ps {
+	status = "okay";
+};
+
+&combphy2_psu {
+	status = "okay";
+};
+
+&gmac0 {
+	clock_in_out = "output";
+	phy-handle = <&rgmii_phy0>;
+	phy-mode = "rgmii-rxid";
+	pinctrl-names = "default";
+	pinctrl-0 = <&gmac0_miim
+		     &gmac0_tx_bus2
+		     &gmac0_rx_bus2
+		     &gmac0_rgmii_clk
+		     &gmac0_rgmii_bus>;
+	tx_delay = <0x45>;
+	rx_delay = <0x4a>;
+	status = "okay";
+};
+
+&gmac1 {
+	clock_in_out = "output";
+	phy-handle = <&rgmii_phy1>;
+	phy-mode = "rgmii-rxid";
+	pinctrl-names = "default";
+	pinctrl-0 = <&gmac1_miim
+		     &gmac1_tx_bus2
+		     &gmac1_rx_bus2
+		     &gmac1_rgmii_clk
+		     &gmac1_rgmii_bus>;
+	tx_delay = <0x42>;
+	rx_delay = <0x4f>;
+	status = "okay";
+};
+
+&gpu {
+	mali-supply = <&vdd_gpu_s0>;
+	sram-supply = <&vdd_gpu_mem_s0>;
+	status = "okay";
+};
+
+&hdmi0 {
+	status = "okay";
+};
+
+&hdmi0_in {
+	hdmi0_in_vp0: endpoint {
+		remote-endpoint = <&vp0_out_hdmi0>;
+	};
+};
+
+&hdmi0_out {
+	hdmi0_out_con: endpoint {
+		remote-endpoint = <&hdmi0_con_in>;
+	};
+};
+
+&hdptxphy_hdmi0 {
+	status = "okay";
+};
+
+&i2c3 {
+	status = "okay";
+
+	/*
+	 * in the Firefly BSP source this was confusingly called an
+	 * "ES8388" - it actually seems to be an ES8323 and the drivers
+	 * for that work best
+	 */
+	es8323: audio-codec@11 {
+		compatible = "everest,es8323";
+		reg = <0x11>;
+		assigned-clocks = <&cru I2S0_8CH_MCLKOUT>;
+		assigned-clock-rates = <12288000>;
+		clocks = <&cru I2S0_8CH_MCLKOUT>;
+		clock-names = "mclk";
+		#sound-dai-cells = <0>;
+	};
+};
+
+&i2c6 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c6m0_xfer>;
+	status = "okay";
+
+	pca9555: gpio@21 {
+		compatible = "nxp,pca9555";
+		reg = <0x21>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	usbc0: usb-typec@22 {
+		compatible = "fcs,fusb302";
+		reg = <0x22>;
+		interrupt-parent = <&gpio0>;
+		interrupts = <RK_PD3 IRQ_TYPE_LEVEL_LOW>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&usbc0_int>;
+		vbus-supply = <&vbus5v0_typec_pwr_en>;
+
+		usb_con: connector {
+			compatible = "usb-c-connector";
+			label = "USB-C";
+			data-role = "dual";
+			op-sink-microwatt = <1000000>;
+			power-role = "dual";
+			sink-pdos =
+				<PDO_FIXED(5000, 1000, PDO_FIXED_USB_COMM)>;
+			source-pdos =
+				<PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
+			try-power-role = "source";
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					reg = <0>;
+
+					usbc0_orien_sw: endpoint {
+						remote-endpoint = <&usbdp_phy0_orientation_switch>;
+					};
+				};
+
+				port@1 {
+					reg = <1>;
+
+					usbc0_role_sw: endpoint {
+						remote-endpoint = <&dwc3_0_role_switch>;
+					};
+				};
+
+				port@2 {
+					reg = <2>;
+
+					dp_altmode_mux: endpoint {
+						remote-endpoint = <&usbdp_phy0_dp_altmode_mux>;
+					};
+				};
+			};
+		};
+	};
+
+	hym8563: rtc@51 {
+		compatible = "haoyu,hym8563";
+		reg = <0x51>;
+		interrupt-parent = <&gpio0>;
+		interrupts = <RK_PB0 IRQ_TYPE_LEVEL_LOW>;
+		#clock-cells = <0>;
+		clock-output-names = "hym8563";
+		pinctrl-names = "default";
+		pinctrl-0 = <&hym8563_int>;
+		wakeup-source;
+	};
+};
+
+&i2s0_8ch {
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2s0_lrck
+		     &i2s0_mclk
+		     &i2s0_sclk
+		     &i2s0_sdi0
+		     &i2s0_sdo0>;
+	status = "okay";
+};
+
+&mdio0 {
+	rgmii_phy0: ethernet-phy@1 {
+		compatible = "ethernet-phy-ieee802.3-c22";
+		reg = <0x1>;
+	};
+};
+
+&mdio1 {
+	rgmii_phy1: ethernet-phy@1 {
+		compatible = "ethernet-phy-ieee802.3-c22";
+		reg = <0x1>;
+	};
+};
+
+&pcie2x1l0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pcie2_0_rst>;
+	reset-gpios = <&gpio1 RK_PB4 GPIO_ACTIVE_HIGH>;
+	status = "okay";
+};
+
+&pcie30phy {
+	status = "okay";
+};
+
+&pcie3x4 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pcie3_rst>;
+	reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>;
+	vpcie3v3-supply = <&vcc3v3_pcie30>;
+	status = "okay";
+};
+
+&pinctrl {
+	dp {
+		dp1_hpd: dp1-hpd {
+			 rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	hym8563 {
+		hym8563_int: hym8563-int {
+			rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+	};
+
+	gpio-leds {
+		sys_led_pin: sys-led-pin {
+			rockchip,pins =
+				<1 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	pcie2 {
+		pcie2_0_rst: pcie2-0-rst {
+			rockchip,pins = <1 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	pcie3 {
+		pcie3_rst: pcie3-rst {
+			rockchip,pins = <4 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		pcie3_vcc3v3_en: pcie3-vcc3v3-en {
+			rockchip,pins = <2 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	sound {
+		hp_detect: hp-detect {
+			rockchip,pins = <1 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		headphone_amplifier_en: headphone-amplifier-en {
+			rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		speaker_amplifier_en: speaker-amplifier-en {
+			rockchip,pins = <3 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	usb {
+		usbc0_int: usbc0-int {
+			rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+	};
+};
+
+&pwm15 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pwm15m2_pins>;
+	status = "okay";
+};
+
+&sata0 {
+	status = "okay";
+};
+
+&sata1 {
+	status = "okay";
+};
+
+&sata2 {
+	status = "okay";
+};
+
+/* uart/232/485 */
+&uart0 {
+	pinctrl-0 = <&uart0m2_xfer>;
+	status = "okay";
+};
+
+&uart1 {
+	pinctrl-0 = <&uart1m1_xfer>;
+	status = "okay";
+};
+
+/* usb enable */
+&u2phy0 {
+	status = "okay";
+};
+
+&u2phy0_otg {
+	status = "okay";
+};
+
+&u2phy1 {
+	status = "okay";
+};
+
+&u2phy1_otg {
+	phy-supply = <&vcc5v0_host>;
+	status = "okay";
+};
+
+&u2phy2 {
+	status = "okay";
+};
+
+&u2phy2_host {
+	phy-supply = <&vcc5v0_host>;
+	status = "okay";
+};
+
+&u2phy3 {
+	status = "okay";
+};
+
+&u2phy3_host {
+	phy-supply = <&vcc5v0_host>;
+	status = "okay";
+};
+
+&usb_host0_ehci {
+	status = "okay";
+};
+
+&usb_host0_ohci {
+	status = "okay";
+};
+
+&usb_host1_ehci {
+	status = "okay";
+};
+
+&usb_host1_ohci {
+	status = "okay";
+};
+
+&usb_host0_xhci {
+	usb-role-switch;
+	dr_mode = "otg";
+	status = "okay";
+
+	port {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		dwc3_0_role_switch: endpoint@0 {
+			reg = <0>;
+			remote-endpoint = <&usbc0_role_sw>;
+		};
+	};
+};
+
+&usb_host1_xhci {
+	dr_mode = "host";
+	status = "okay";
+};
+
+&usb_host2_xhci {
+	status = "okay";
+};
+
+&usbdp_phy0 {
+	orientation-switch;
+	sbu1-dc-gpios = <&gpio4 RK_PA6 GPIO_ACTIVE_HIGH>;
+	sbu2-dc-gpios = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>;
+	status = "okay";
+
+	port {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		usbdp_phy0_orientation_switch: endpoint@0 {
+			reg = <0>;
+			remote-endpoint = <&usbc0_orien_sw>;
+		};
+
+		usbdp_phy0_dp_altmode_mux: endpoint@1 {
+			reg = <1>;
+			remote-endpoint = <&dp_altmode_mux>;
+		};
+	};
+};
+
+&usbdp_phy1 {
+	rockchip,dp-lane-mux = <2 3>;
+	status = "okay";
+};
+
+&vcc_1v8_s0 {
+	regulator-state-mem {
+		regulator-on-in-suspend;
+		regulator-suspend-microvolt = <1800000>;
+	};
+};
+
+/* for fan when deep sleep */
+&vdd_log_s0 {
+	regulator-state-mem {
+		regulator-on-in-suspend;
+		regulator-suspend-microvolt = <750000>;
+	};
+};
+
+/* display generator */
+&vop_mmu {
+	status = "okay";
+};
+
+&vop {
+	status = "okay";
+};
+
+&vp0 {
+	vp0_out_hdmi0: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
+		reg = <ROCKCHIP_VOP2_EP_HDMI0>;
+		remote-endpoint = <&hdmi0_in_vp0>;
+	};
+};
diff --git a/dts/upstream/src/arm64/rockchip/rk3588-h96-max-v58.dts b/dts/upstream/src/arm64/rockchip/rk3588-h96-max-v58.dts
new file mode 100644
index 00000000000..4791b77f357
--- /dev/null
+++ b/dts/upstream/src/arm64/rockchip/rk3588-h96-max-v58.dts
@@ -0,0 +1,802 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/soc/rockchip,vop2.h>
+#include "rk3588.dtsi"
+
+/ {
+	model = "H96 Max V58 TV Box";
+	compatible = "haochuangyi,h96-max-v58", "rockchip,rk3588";
+
+	aliases {
+		ethernet0 = &gmac1;
+		mmc0 = &sdhci;
+	};
+
+	adc-keys {
+		compatible = "adc-keys";
+		io-channels = <&saradc 1>;
+		io-channel-names = "buttons";
+		keyup-threshold-microvolt = <1800000>;
+		poll-interval = <100>;
+
+		button-function {
+			label = "Reset";
+			linux,code = <KEY_VENDOR>;
+			press-threshold-microvolt = <1750>;
+		};
+	};
+
+	chosen {
+		stdout-path = "serial2:1500000n8";
+	};
+
+	hdmi0-con {
+		compatible = "hdmi-connector";
+		type = "a";
+
+		port {
+			hdmi0_con_in: endpoint {
+				remote-endpoint = <&hdmi0_out_con>;
+			};
+		};
+	};
+
+	ir-receiver {
+		compatible = "gpio-ir-receiver";
+		gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_LOW>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&ir_receiver_pin>;
+	};
+
+	leds {
+		compatible = "gpio-leds";
+		pinctrl-names = "default";
+		pinctrl-0 = <&led_pins>;
+
+		led {
+			color = <LED_COLOR_ID_BLUE>;
+			function = LED_FUNCTION_STATUS;
+			gpios = <&gpio3 RK_PD4 GPIO_ACTIVE_HIGH>;
+			linux,default-trigger = "heartbeat";
+		};
+	};
+
+	vcc_1v1_nldo_s3: regulator-1v1 {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc_1v1_nldo_s3";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <1100000>;
+		regulator-max-microvolt = <1100000>;
+		vin-supply = <&vcc5v0_sys>;
+	};
+
+	pcie_3v3: regulator-3v3-pcie {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpios = <&gpio4 RK_PA1 GPIO_ACTIVE_HIGH>;
+		pinctrl-0 = <&pcie2_0_pow>;
+		pinctrl-names = "default";
+		regulator-name = "pcie_3v3";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		vin-supply = <&vcc5v0_sys>;
+	};
+
+	wl_en_3v3: regulator-3v3-wlen {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpios = <&gpio0 RK_PC4 GPIO_ACTIVE_HIGH>;
+		pinctrl-0 = <&wl_en>;
+		pinctrl-names = "default";
+		/*
+		 * Needs to be brought up before the PCIe driver is probed,
+		 * otherwise detecting the WLAN module requires rescanning
+		 * the bus, and even then it fails half of the time during
+		 * firmware load
+		 */
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-name = "wl_en_3v3";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		vin-supply = <&vcc5v0_sys>;
+	};
+
+	vcc5v0_host: regulator-5v0-host {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc5v0_host";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		enable-active-high;
+		gpios = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>;
+		pinctrl-0 = <&vcc5v0_host_en>;
+		pinctrl-names = "default";
+		vin-supply = <&vcc5v0_sys>;
+	};
+
+	vcc5v0_otg: regulator-5v0-otg {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc5v0_otg";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		enable-active-high;
+		gpios = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>;
+		pinctrl-0 = <&vcc5v0_otg_en>;
+		pinctrl-names = "default";
+		vin-supply = <&vcc5v0_sys>;
+	};
+
+	vcc5v0_sys: regulator-5v0-sys {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc5v0_sys";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+	};
+};
+
+&combphy0_ps {
+	status = "okay";
+};
+
+&combphy1_ps {
+	status = "okay";
+};
+
+&combphy2_psu {
+	status = "okay";
+};
+
+&cpu_b0 {
+	cpu-supply = <&vdd_cpu_big0_s0>;
+};
+
+&cpu_b1 {
+	cpu-supply = <&vdd_cpu_big0_s0>;
+};
+
+&cpu_b2 {
+	cpu-supply = <&vdd_cpu_big1_s0>;
+};
+
+&cpu_b3 {
+	cpu-supply = <&vdd_cpu_big1_s0>;
+};
+
+&cpu_l0 {
+	cpu-supply = <&vdd_cpu_lit_s0>;
+};
+
+&cpu_l1 {
+	cpu-supply = <&vdd_cpu_lit_s0>;
+};
+
+&cpu_l2 {
+	cpu-supply = <&vdd_cpu_lit_s0>;
+};
+
+&cpu_l3 {
+	cpu-supply = <&vdd_cpu_lit_s0>;
+};
+
+&gpu {
+	mali-supply = <&vdd_gpu_s0>;
+	status = "okay";
+};
+
+&hdmi0 {
+	status = "okay";
+};
+
+&hdmi0_in {
+	hdmi0_in_vp0: endpoint {
+		remote-endpoint = <&vp0_out_hdmi0>;
+	};
+};
+
+&hdmi0_out {
+	hdmi0_out_con: endpoint {
+		remote-endpoint = <&hdmi0_con_in>;
+	};
+};
+
+&hdptxphy_hdmi0 {
+	status = "okay";
+};
+
+&i2c0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c0m2_xfer>;
+	status = "okay";
+
+	vdd_cpu_big0_s0: regulator@42 {
+		compatible = "rockchip,rk8602";
+		reg = <0x42>;
+		fcs,suspend-voltage-selector = <1>;
+		regulator-name = "vdd_cpu_big0_s0";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <550000>;
+		regulator-max-microvolt = <1050000>;
+		regulator-ramp-delay = <2300>;
+		vin-supply = <&vcc5v0_sys>;
+
+		regulator-state-mem {
+			regulator-off-in-suspend;
+		};
+	};
+
+	vdd_cpu_big1_s0: regulator@43 {
+		compatible = "rockchip,rk8603", "rockchip,rk8602";
+		reg = <0x43>;
+		fcs,suspend-voltage-selector = <1>;
+		regulator-name = "vdd_cpu_big1_s0";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <550000>;
+		regulator-max-microvolt = <1050000>;
+		regulator-ramp-delay = <2300>;
+		vin-supply = <&vcc5v0_sys>;
+
+		regulator-state-mem {
+			regulator-off-in-suspend;
+		};
+	};
+};
+
+&i2c6 {
+	status = "okay";
+
+	hym8563: rtc@51 {
+		compatible = "haoyu,hym8563";
+		reg = <0x51>;
+		#clock-cells = <0>;
+		clock-output-names = "hym8563";
+		pinctrl-names = "default";
+		pinctrl-0 = <&hym8563_int>;
+		interrupt-parent = <&gpio0>;
+		interrupts = <RK_PB0 IRQ_TYPE_LEVEL_LOW>;
+		wakeup-source;
+	};
+};
+
+&gmac1 {
+	clock_in_out = "output";
+	phy-handle = <&rgmii_phy1>;
+	phy-mode = "rgmii-id";
+	pinctrl-0 = <&gmac1_miim
+		     &gmac1_tx_bus2
+		     &gmac1_rx_bus2
+		     &gmac1_rgmii_clk
+		     &gmac1_rgmii_bus>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
+&mdio1 {
+	rgmii_phy1: ethernet-phy@1 {
+		/* RTL8211F */
+		compatible = "ethernet-phy-id001c.c916";
+		reg = <0x1>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&rtl8211f_rst>;
+		reset-assert-us = <20000>;
+		reset-deassert-us = <100000>;
+		reset-gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
+	};
+};
+
+&pcie2x1l0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pcie2_0_rst>;
+	reset-gpios = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>;
+	status = "okay";
+
+	pcie@0,0 {
+		reg = <0x200000 0 0 0 0>;
+		#address-cells = <3>;
+		#size-cells = <2>;
+		ranges;
+		device_type = "pci";
+		bus-range = <0x20 0x2f>;
+
+		wifi: wifi@0,0 {
+			compatible = "pci14e4,449d";
+			reg = <0x210000 0 0 0 0>;
+			clocks = <&hym8563>;
+			clock-names = "lpo";
+		};
+	};
+};
+
+&pinctrl {
+	hym8563 {
+		hym8563_int: hym8563-int {
+			rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	ir-receiver {
+		ir_receiver_pin: ir-receiver-pin {
+			rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	leds {
+		led_pins: led-pins {
+			rockchip,pins = <3 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	pcie2 {
+		pcie2_0_rst: pcie2-0-rst {
+			rockchip,pins = <4 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		pcie2_0_pow: pcie2-0-pow {
+			rockchip,pins = <4 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	rtl8211f {
+		rtl8211f_rst: rtl8211f-rst {
+			rockchip,pins = <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+	};
+
+	usb {
+		vcc5v0_host_en: vcc5v0-host-en {
+			rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		vcc5v0_otg_en: vcc5v0-otg-en {
+			rockchip,pins = <4 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	wifibt {
+		wl_en: wl-en {
+			rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+
+		wl_wake_host: wl-wake-host {
+			rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+
+		bt_en: bt-en {
+			rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+
+		bt_wake: bt-wake {
+			rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+
+		bt_wake_host: bt-wake-host {
+			rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_down>;
+		};
+	};
+};
+
+&saradc {
+	vref-supply = <&avcc_1v8_s0>;
+	status = "okay";
+};
+
+&sdhci {
+	bus-width = <8>;
+	no-sdio;
+	no-sd;
+	non-removable;
+	mmc-hs400-1_8v;
+	mmc-hs400-enhanced-strobe;
+	status = "okay";
+};
+
+&spi2 {
+	assigned-clocks = <&cru CLK_SPI2>;
+	assigned-clock-rates = <200000000>;
+	num-cs = <1>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>;
+	status = "okay";
+
+	pmic@0 {
+		compatible = "rockchip,rk806";
+		reg = <0x0>;
+		interrupt-parent = <&gpio0>;
+		interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>,
+			    <&rk806_dvs2_null>, <&rk806_dvs3_null>;
+		spi-max-frequency = <1000000>;
+		system-power-controller;
+
+		vcc1-supply = <&vcc5v0_sys>;
+		vcc2-supply = <&vcc5v0_sys>;
+		vcc3-supply = <&vcc5v0_sys>;
+		vcc4-supply = <&vcc5v0_sys>;
+		vcc5-supply = <&vcc5v0_sys>;
+		vcc6-supply = <&vcc5v0_sys>;
+		vcc7-supply = <&vcc5v0_sys>;
+		vcc8-supply = <&vcc5v0_sys>;
+		vcc9-supply = <&vcc5v0_sys>;
+		vcc10-supply = <&vcc5v0_sys>;
+		vcc11-supply = <&vcc_2v0_pldo_s3>;
+		vcc12-supply = <&vcc5v0_sys>;
+		vcc13-supply = <&vcc_1v1_nldo_s3>;
+		vcc14-supply = <&vcc_1v1_nldo_s3>;
+		vcca-supply = <&vcc5v0_sys>;
+
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		rk806_dvs1_null: dvs1-null-pins {
+			pins = "gpio_pwrctrl1";
+			function = "pin_fun0";
+		};
+
+		rk806_dvs2_null: dvs2-null-pins {
+			pins = "gpio_pwrctrl2";
+			function = "pin_fun0";
+		};
+
+		rk806_dvs3_null: dvs3-null-pins {
+			pins = "gpio_pwrctrl3";
+			function = "pin_fun0";
+		};
+
+		regulators {
+			vdd_gpu_s0: vdd_gpu_mem_s0: dcdc-reg1 {
+				regulator-name = "vdd_gpu_s0";
+				regulator-boot-on;
+				regulator-min-microvolt = <550000>;
+				regulator-max-microvolt = <950000>;
+				regulator-ramp-delay = <12500>;
+				regulator-enable-ramp-delay = <400>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdd_cpu_lit_s0: vdd_cpu_lit_mem_s0: dcdc-reg2 {
+				regulator-name = "vdd_cpu_lit_s0";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <550000>;
+				regulator-max-microvolt = <950000>;
+				regulator-ramp-delay = <12500>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdd_log_s0: dcdc-reg3 {
+				regulator-name = "vdd_log_s0";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <675000>;
+				regulator-max-microvolt = <750000>;
+				regulator-ramp-delay = <12500>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+					regulator-suspend-microvolt = <750000>;
+				};
+			};
+
+			vdd_vdenc_s0: vdd_vdenc_mem_s0: dcdc-reg4 {
+				regulator-name = "vdd_vdenc_s0";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <550000>;
+				regulator-max-microvolt = <950000>;
+				regulator-ramp-delay = <12500>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdd_ddr_s0: dcdc-reg5 {
+				regulator-name = "vdd_ddr_s0";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <675000>;
+				regulator-max-microvolt = <900000>;
+				regulator-ramp-delay = <12500>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+					regulator-suspend-microvolt = <850000>;
+				};
+			};
+
+			vdd2_ddr_s3: dcdc-reg6 {
+				regulator-name = "vdd2_ddr_s3";
+				regulator-always-on;
+				regulator-boot-on;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+				};
+			};
+
+			vcc_2v0_pldo_s3: dcdc-reg7 {
+				regulator-name = "vdd_2v0_pldo_s3";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <2000000>;
+				regulator-max-microvolt = <2000000>;
+				regulator-ramp-delay = <12500>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <2000000>;
+				};
+			};
+
+			vcc_3v3_s3: dcdc-reg8 {
+				regulator-name = "vcc_3v3_s3";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <3300000>;
+				};
+			};
+
+			vddq_ddr_s0: dcdc-reg9 {
+				regulator-name = "vddq_ddr_s0";
+				regulator-always-on;
+				regulator-boot-on;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_1v8_s3: dcdc-reg10 {
+				regulator-name = "vcc_1v8_s3";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			avcc_1v8_s0: pldo-reg1 {
+				regulator-name = "avcc_1v8_s0";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_1v8_s0: pldo-reg2 {
+				regulator-name = "vcc_1v8_s0";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			avdd_1v2_s0: pldo-reg3 {
+				regulator-name = "avdd_1v2_s0";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1200000>;
+				regulator-max-microvolt = <1200000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_3v3_s0: pldo-reg4 {
+				regulator-name = "vcc_3v3_s0";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-ramp-delay = <12500>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vccio_sd_s0: pldo-reg5 {
+				regulator-name = "vccio_sd_s0";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-ramp-delay = <12500>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			pldo6_s3: pldo-reg6 {
+				regulator-name = "pldo6_s3";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			vdd_0v75_s3: nldo-reg1 {
+				regulator-name = "vdd_0v75_s3";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <750000>;
+				regulator-max-microvolt = <750000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <750000>;
+				};
+			};
+
+			vdd_ddr_pll_s0: nldo-reg2 {
+				regulator-name = "vdd_ddr_pll_s0";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <850000>;
+				regulator-max-microvolt = <850000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+					regulator-suspend-microvolt = <850000>;
+				};
+			};
+
+			avdd_0v75_s0: nldo-reg3 {
+				regulator-name = "avdd_0v75_s0";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <750000>;
+				regulator-max-microvolt = <750000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdd_0v85_s0: nldo-reg4 {
+				regulator-name = "vdd_0v85_s0";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <850000>;
+				regulator-max-microvolt = <850000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdd_0v75_s0: nldo-reg5 {
+				regulator-name = "vdd_0v75_s0";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <750000>;
+				regulator-max-microvolt = <750000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+		};
+	};
+};
+
+&tsadc {
+	status = "okay";
+};
+
+&u2phy0 {
+	status = "okay";
+};
+
+&u2phy0_otg {
+	phy-supply = <&vcc5v0_otg>;
+	status = "okay";
+};
+
+&u2phy1 {
+	status = "okay";
+};
+
+&u2phy1_otg {
+	phy-supply = <&vcc5v0_host>;
+	status = "okay";
+};
+
+&uart2 {
+	pinctrl-0 = <&uart2m0_xfer>;
+	status = "okay";
+};
+
+&uart9 {
+	pinctrl-0 = <&uart9m0_xfer &uart9m0_ctsn &uart9m0_rtsn>;
+	pinctrl-names = "default";
+	uart-has-rtscts;
+	status = "okay";
+
+	bluetooth {
+		compatible = "brcm,bcm43438-bt";
+		clocks = <&hym8563>;
+		clock-names = "lpo";
+		device-wakeup-gpios = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>;
+		interrupt-parent = <&gpio0>;
+		interrupts = <RK_PA0 IRQ_TYPE_EDGE_FALLING>;
+		pinctrl-0 = <&bt_en>, <&bt_wake_host>, <&bt_wake>;
+		pinctrl-names = "default";
+		shutdown-gpios = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>;
+	};
+};
+
+&usbdp_phy0 {
+	status = "okay";
+};
+
+&usbdp_phy1 {
+	status = "okay";
+};
+
+&usb_host0_xhci {
+	dr_mode = "host";
+	status = "okay";
+};
+
+&usb_host1_xhci {
+	dr_mode = "host";
+	status = "okay";
+};
+
+&vop_mmu {
+	status = "okay";
+};
+
+&vop {
+	status = "okay";
+};
+
+&vp0 {
+	vp0_out_hdmi0: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
+		reg = <ROCKCHIP_VOP2_EP_HDMI0>;
+		remote-endpoint = <&hdmi0_in_vp0>;
+	};
+};
diff --git a/dts/upstream/src/arm64/rockchip/rk3588-jaguar.dts b/dts/upstream/src/arm64/rockchip/rk3588-jaguar.dts
index 90f823b2c21..7f457ab7801 100644
--- a/dts/upstream/src/arm64/rockchip/rk3588-jaguar.dts
+++ b/dts/upstream/src/arm64/rockchip/rk3588-jaguar.dts
@@ -503,7 +503,6 @@
 	non-removable;
 	pinctrl-names = "default";
 	pinctrl-0 = <&emmc_bus8 &emmc_cmd &emmc_clk &emmc_data_strobe>;
-	supports-cqe;
 	vmmc-supply = <&vcc_3v3_s3>;
 	vqmmc-supply = <&vcc_1v8_s3>;
 	status = "okay";
diff --git a/dts/upstream/src/arm64/rockchip/rk3588-orangepi-5-compact.dtsi b/dts/upstream/src/arm64/rockchip/rk3588-orangepi-5-compact.dtsi
new file mode 100644
index 00000000000..87090cb9802
--- /dev/null
+++ b/dts/upstream/src/arm64/rockchip/rk3588-orangepi-5-compact.dtsi
@@ -0,0 +1,151 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+#include "rk3588-orangepi-5.dtsi"
+
+/ {
+	model = "Xunlong Orange Pi 5 Max";
+	compatible = "xunlong,orangepi-5-max", "rockchip,rk3588";
+
+	vcc5v0_usb30_otg: vcc5v0-usb30-otg-regulator {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		/* USB_OTG_PWREN */
+		gpios = <&gpio4 RK_PB3 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&usb_otg_pwren>;
+		regulator-name = "vcc5v0_usb30_otg";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		vin-supply = <&vcc5v0_sys>;
+	};
+};
+
+&headphone_amp {
+	/* PHONE_CTL */
+	enable-gpios = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>;
+};
+
+&analog_sound {
+	pinctrl-names = "default";
+	pinctrl-0 = <&hp_detect>;
+	simple-audio-card,aux-devs = <&headphone_amp>;
+	simple-audio-card,hp-det-gpios = <&gpio3 RK_PD2 GPIO_ACTIVE_HIGH>;
+
+	simple-audio-card,routing =
+		"Headphones", "LOUT1",
+		"Headphones", "ROUT1",
+		"LINPUT1", "Microphone Jack",
+		"RINPUT1", "Microphone Jack",
+		"LINPUT2", "Onboard Microphone",
+		"RINPUT2", "Onboard Microphone";
+	simple-audio-card,widgets =
+		"Microphone", "Microphone Jack",
+		"Microphone", "Onboard Microphone",
+		"Headphone", "Headphones";
+};
+
+&fan {
+	/* FAN_CTL_H */
+	pwms = <&pwm9 0 50000 0>;
+};
+
+&hym8563 {
+	interrupt-parent = <&gpio0>;
+	interrupts = <RK_PC4 IRQ_TYPE_LEVEL_LOW>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&rtc_int_l>;
+};
+
+&led_blue_pwm {
+	/* PWM_LED1 */
+	pwms = <&pwm4 0 25000 0>;
+	status = "okay";
+};
+
+&led_green_pwm {
+	/* PWM_LED2 */
+	pwms = <&pwm5 0 25000 0>;
+};
+
+/* phy2 */
+&pcie2x1l1 {
+	reset-gpios = <&gpio4 RK_PD4 GPIO_ACTIVE_HIGH>;
+	vpcie3v3-supply = <&vcc3v3_pcie_eth>;
+	status = "okay";
+};
+
+&pinctrl {
+	hym8563 {
+		rtc_int_l: hym8563-int {
+			rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	sound {
+		hp_detect: hp-detect {
+			rockchip,pins = <3 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	usb {
+		usb_host_pwren: usb-host-pwren {
+			rockchip,pins = <3 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+};
+
+&pwm4 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pwm4m0_pins>;
+	status = "okay";
+};
+
+&pwm5 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pwm5m1_pins>;
+	status = "okay";
+};
+
+&pwm9 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pwm9m2_pins>;
+	status = "okay";
+};
+
+&sfc {
+	pinctrl-names = "default";
+	pinctrl-0 = <&fspim2_pins>;
+};
+
+&u2phy0_otg {
+	phy-supply = <&vcc5v0_usb30_otg>;
+};
+
+&u2phy1_otg {
+	phy-supply = <&vcc5v0_usb20>;
+};
+
+&usb_host0_xhci {
+	dr_mode = "host";
+};
+
+/* pcie eth. not a real regulator. 33VAUX */
+&vcc3v3_pcie_eth {
+	/* Ethernet_power_en */
+	gpios = <&gpio0 RK_PD3 GPIO_ACTIVE_LOW>;
+};
+
+/*
+ * Represents the vcc5v0_usb20 and vcc5v0_usb30 in the schematic,
+ * both regulators share the same enable gpio
+ */
+&vcc5v0_usb20 {
+	/* USB_HOST_PWREN */
+	gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_HIGH>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&usb_host_pwren>;
+};
diff --git a/dts/upstream/src/arm64/rockchip/rk3588-orangepi-5-max.dts b/dts/upstream/src/arm64/rockchip/rk3588-orangepi-5-max.dts
new file mode 100644
index 00000000000..ce44549babf
--- /dev/null
+++ b/dts/upstream/src/arm64/rockchip/rk3588-orangepi-5-max.dts
@@ -0,0 +1,60 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+#include <dt-bindings/soc/rockchip,vop2.h>
+#include "rk3588-orangepi-5-compact.dtsi"
+
+/ {
+	model = "Xunlong Orange Pi 5 Max";
+	compatible = "xunlong,orangepi-5-max", "rockchip,rk3588";
+
+	hdmi0-con {
+		compatible = "hdmi-connector";
+		type = "a";
+
+		port {
+			hdmi0_con_in: endpoint {
+				remote-endpoint = <&hdmi0_out_con>;
+			};
+		};
+	};
+};
+
+&hdmi0 {
+	status = "okay";
+};
+
+&hdmi0_in {
+	hdmi0_in_vp0: endpoint {
+		remote-endpoint = <&vp0_out_hdmi0>;
+	};
+};
+
+&hdmi0_out {
+	hdmi0_out_con: endpoint {
+		remote-endpoint = <&hdmi0_con_in>;
+	};
+};
+
+&hdptxphy_hdmi0 {
+	status = "okay";
+};
+
+&pinctrl {
+
+	usb {
+		usb_otg_pwren: usb-otg-pwren {
+			rockchip,pins = <4 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+};
+
+&vp0 {
+	vp0_out_hdmi0: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
+		reg = <ROCKCHIP_VOP2_EP_HDMI0>;
+		remote-endpoint = <&hdmi0_in_vp0>;
+	};
+};
diff --git a/dts/upstream/src/arm64/rockchip/rk3588-orangepi-5-plus.dts b/dts/upstream/src/arm64/rockchip/rk3588-orangepi-5-plus.dts
index 9f5a38b290b..255e33c5dbd 100644
--- a/dts/upstream/src/arm64/rockchip/rk3588-orangepi-5-plus.dts
+++ b/dts/upstream/src/arm64/rockchip/rk3588-orangepi-5-plus.dts
@@ -6,86 +6,15 @@
 /dts-v1/;
 
 #include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/input/input.h>
 #include <dt-bindings/pinctrl/rockchip.h>
 #include <dt-bindings/soc/rockchip,vop2.h>
 #include <dt-bindings/usb/pd.h>
-#include "rk3588.dtsi"
+#include "rk3588-orangepi-5.dtsi"
 
 / {
 	model = "Xunlong Orange Pi 5 Plus";
 	compatible = "xunlong,orangepi-5-plus", "rockchip,rk3588";
 
-	aliases {
-		mmc0 = &sdhci;
-		mmc1 = &sdmmc;
-	};
-
-	chosen {
-		stdout-path = "serial2:1500000n8";
-	};
-
-	adc-keys-0 {
-		compatible = "adc-keys";
-		io-channels = <&saradc 0>;
-		io-channel-names = "buttons";
-		keyup-threshold-microvolt = <1800000>;
-		poll-interval = <100>;
-
-		button-maskrom {
-			label = "Mask Rom";
-			linux,code = <KEY_SETUP>;
-			press-threshold-microvolt = <2000>;
-		};
-	};
-
-	adc-keys-1 {
-		compatible = "adc-keys";
-		io-channels = <&saradc 1>;
-		io-channel-names = "buttons";
-		keyup-threshold-microvolt = <1800000>;
-		poll-interval = <100>;
-
-		button-recovery {
-			label = "Recovery";
-			linux,code = <KEY_VENDOR>;
-			press-threshold-microvolt = <2000>;
-		};
-	};
-
-	speaker_amp: speaker-audio-amplifier {
-		compatible = "simple-audio-amplifier";
-		enable-gpios = <&gpio3 RK_PC0 GPIO_ACTIVE_HIGH>;
-		sound-name-prefix = "Speaker Amp";
-	};
-
-	headphone_amp: headphones-audio-amplifier {
-		compatible = "simple-audio-amplifier";
-		enable-gpios = <&gpio3 RK_PA7 GPIO_ACTIVE_HIGH>;
-		sound-name-prefix = "Headphones Amp";
-	};
-
-	ir-receiver {
-		compatible = "gpio-ir-receiver";
-		gpios = <&gpio4 RK_PB3 GPIO_ACTIVE_LOW>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&ir_receiver_pin>;
-	};
-
-	gpio-leds {
-		compatible = "gpio-leds";
-		pinctrl-names = "default";
-		pinctrl-0 = <&blue_led_pin>;
-
-		led {
-			color = <LED_COLOR_ID_BLUE>;
-			function = LED_FUNCTION_INDICATOR;
-			function-enumerator = <1>;
-			gpios = <&gpio3 RK_PA6 GPIO_ACTIVE_HIGH>;
-		};
-	};
-
 	hdmi0-con {
 		compatible = "hdmi-connector";
 		type = "a";
@@ -97,24 +26,11 @@
 		};
 	};
 
-	fan: pwm-fan {
-		compatible = "pwm-fan";
-		cooling-levels = <0 70 75 80 100>;
-		fan-supply = <&vcc5v0_sys>;
-		pwms = <&pwm3 0 50000 0>;
-		#cooling-cells = <2>;
-	};
-
-	pwm-leds {
-		compatible = "pwm-leds";
-
-		led {
-			color = <LED_COLOR_ID_GREEN>;
-			function = LED_FUNCTION_INDICATOR;
-			function-enumerator = <2>;
-			max-brightness = <255>;
-			pwms = <&pwm2 0 25000 0>;
-		};
+	ir-receiver {
+		compatible = "gpio-ir-receiver";
+		gpios = <&gpio4 RK_PB3 GPIO_ACTIVE_LOW>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&ir_receiver_pin>;
 	};
 
 	rfkill {
@@ -124,160 +40,73 @@
 		shutdown-gpios = <&gpio0 RK_PC4 GPIO_ACTIVE_HIGH>;
 	};
 
-	sound {
-		compatible = "simple-audio-card";
-		pinctrl-names = "default";
-		pinctrl-0 = <&hp_detect>;
-		simple-audio-card,name = "Analog";
-		simple-audio-card,aux-devs = <&speaker_amp>, <&headphone_amp>;
-		simple-audio-card,format = "i2s";
-		simple-audio-card,mclk-fs = <256>;
-		simple-audio-card,hp-det-gpios = <&gpio1 RK_PD3 GPIO_ACTIVE_LOW>;
-		simple-audio-card,bitclock-master = <&daicpu>;
-		simple-audio-card,frame-master = <&daicpu>;
-		/*TODO: SARADC_IN3 is used as MIC detection / key input */
-
-		simple-audio-card,widgets =
-			"Microphone", "Onboard Microphone",
-			"Microphone", "Microphone Jack",
-			"Speaker", "Speaker",
-			"Headphone", "Headphones";
-
-		simple-audio-card,routing =
-			"Headphones", "LOUT1",
-			"Headphones", "ROUT1",
-			"Speaker", "LOUT2",
-			"Speaker", "ROUT2",
-
-			"Headphones", "Headphones Amp OUTL",
-			"Headphones", "Headphones Amp OUTR",
-			"Headphones Amp INL", "LOUT1",
-			"Headphones Amp INR", "ROUT1",
-
-			"Speaker", "Speaker Amp OUTL",
-			"Speaker", "Speaker Amp OUTR",
-			"Speaker Amp INL", "LOUT2",
-			"Speaker Amp INR", "ROUT2",
-
-			/* single ended signal to LINPUT1 */
-			"LINPUT1", "Microphone Jack",
-			"RINPUT1", "Microphone Jack",
-			/* differential signal */
-			"LINPUT2", "Onboard Microphone",
-			"RINPUT2", "Onboard Microphone";
-
-		daicpu: simple-audio-card,cpu {
-			sound-dai = <&i2s0_8ch>;
-			system-clock-frequency = <12288000>;
-		};
-
-		daicodec: simple-audio-card,codec {
-			sound-dai = <&es8388>;
-			system-clock-frequency = <12288000>;
-		};
-	};
-
-	vcc3v3_pcie30: regulator-vcc3v3-pcie30 {
-		compatible = "regulator-fixed";
-		enable-active-high;
-		gpios = <&gpio2 RK_PB6 GPIO_ACTIVE_HIGH>;
-		regulator-name = "vcc3v3_pcie30";
-		regulator-min-microvolt = <3300000>;
-		regulator-max-microvolt = <3300000>;
-		startup-delay-us = <5000>;
-		vin-supply = <&vcc5v0_sys>;
-	};
-
-	vcc3v3_pcie_eth: regulator-vcc3v3-pcie-eth {
-		compatible = "regulator-fixed";
-		gpios = <&gpio3 RK_PB4 GPIO_ACTIVE_LOW>;
-		regulator-name = "vcc3v3_pcie_eth";
-		regulator-min-microvolt = <3300000>;
-		regulator-max-microvolt = <3300000>;
-		startup-delay-us = <50000>;
-		vin-supply = <&vcc5v0_sys>;
-	};
-
-	vcc3v3_wf: regulator-vcc3v3-wf {
-		compatible = "regulator-fixed";
-		enable-active-high;
-		gpios = <&gpio2 RK_PC5 GPIO_ACTIVE_HIGH>;
-		regulator-name = "vcc3v3_wf";
-		regulator-min-microvolt = <3300000>;
-		regulator-max-microvolt = <3300000>;
-		startup-delay-us = <50000>;
-		vin-supply = <&vcc5v0_sys>;
-	};
-
-	vcc5v0_sys: regulator-vcc5v0-sys {
-		compatible = "regulator-fixed";
-		regulator-name = "vcc5v0_sys";
-		regulator-always-on;
-		regulator-boot-on;
-		regulator-min-microvolt = <5000000>;
-		regulator-max-microvolt = <5000000>;
-	};
-
-	vcc5v0_usb20: regulator-vcc5v0-usb20 {
+	vbus5v0_typec: regulator-vbus-typec {
 		compatible = "regulator-fixed";
 		enable-active-high;
-		gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_HIGH>;
+		gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>;
 		pinctrl-names = "default";
-		pinctrl-0 = <&vcc5v0_usb20_en>;
-		regulator-name = "vcc5v0_usb20";
+		pinctrl-0 = <&typec5v_pwren>;
+		regulator-name = "vbus5v0_typec";
 		regulator-min-microvolt = <5000000>;
 		regulator-max-microvolt = <5000000>;
 		vin-supply = <&vcc5v0_sys>;
 	};
 };
 
-&combphy0_ps {
-	status = "okay";
-};
-
-&combphy1_ps {
+&speaker_amp {
+	enable-gpios = <&gpio3 RK_PC0 GPIO_ACTIVE_HIGH>;
 	status = "okay";
 };
 
-&combphy2_psu {
-	status = "okay";
+&headphone_amp {
+	enable-gpios = <&gpio3 RK_PA7 GPIO_ACTIVE_HIGH>;
 };
 
-&cpu_b0 {
-	cpu-supply = <&vdd_cpu_big0_s0>;
-};
-
-&cpu_b1 {
-	cpu-supply = <&vdd_cpu_big0_s0>;
-};
-
-&cpu_b2 {
-	cpu-supply = <&vdd_cpu_big1_s0>;
-};
-
-&cpu_b3 {
-	cpu-supply = <&vdd_cpu_big1_s0>;
-};
-
-&cpu_l0 {
-	cpu-supply = <&vdd_cpu_lit_s0>;
+&analog_sound {
+	pinctrl-names = "default";
+	pinctrl-0 = <&hp_detect>;
+	simple-audio-card,aux-devs = <&speaker_amp>, <&headphone_amp>;
+	simple-audio-card,hp-det-gpios = <&gpio1 RK_PD3 GPIO_ACTIVE_LOW>;
+	simple-audio-card,widgets =
+		"Microphone", "Onboard Microphone",
+		"Microphone", "Microphone Jack",
+		"Speaker", "Speaker",
+		"Headphone", "Headphones";
+
+	simple-audio-card,routing =
+		"Headphones", "LOUT1",
+		"Headphones", "ROUT1",
+		"Speaker", "LOUT2",
+		"Speaker", "ROUT2",
+
+		"Headphones", "Headphones Amp OUTL",
+		"Headphones", "Headphones Amp OUTR",
+		"Headphones Amp INL", "LOUT1",
+		"Headphones Amp INR", "ROUT1",
+
+		"Speaker", "Speaker Amp OUTL",
+		"Speaker", "Speaker Amp OUTR",
+		"Speaker Amp INL", "LOUT2",
+		"Speaker Amp INR", "ROUT2",
+
+		/* single ended signal to LINPUT1 */
+		"LINPUT1", "Microphone Jack",
+		"RINPUT1", "Microphone Jack",
+		/* differential signal */
+		"LINPUT2", "Onboard Microphone",
+		"RINPUT2", "Onboard Microphone";
 };
 
-&cpu_l1 {
-	cpu-supply = <&vdd_cpu_lit_s0>;
+&combphy0_ps {
+	status = "okay";
 };
 
-&cpu_l2 {
-	cpu-supply = <&vdd_cpu_lit_s0>;
+&combphy1_ps {
+	status = "okay";
 };
 
-&cpu_l3 {
-	cpu-supply = <&vdd_cpu_lit_s0>;
-};
-
-&gpu {
-	mali-supply = <&vdd_gpu_s0>;
-	status = "okay";
+&fan {
+	pwms = <&pwm3 0 50000 0>;
 };
 
 &hdmi0 {
@@ -300,128 +129,73 @@
 	status = "okay";
 };
 
-&i2c0 {
+&hym8563 {
+	interrupt-parent = <&gpio0>;
+	interrupts = <RK_PB0 IRQ_TYPE_LEVEL_LOW>;
 	pinctrl-names = "default";
-	pinctrl-0 = <&i2c0m2_xfer>;
-	status = "okay";
-
-	vdd_cpu_big0_s0: regulator@42 {
-		compatible = "rockchip,rk8602";
-		reg = <0x42>;
-		fcs,suspend-voltage-selector = <1>;
-		regulator-name = "vdd_cpu_big0_s0";
-		regulator-always-on;
-		regulator-boot-on;
-		regulator-min-microvolt = <550000>;
-		regulator-max-microvolt = <1050000>;
-		regulator-ramp-delay = <2300>;
-		vin-supply = <&vcc5v0_sys>;
-
-		regulator-state-mem {
-			regulator-off-in-suspend;
-		};
-	};
-
-	vdd_cpu_big1_s0: regulator@43 {
-		compatible = "rockchip,rk8603", "rockchip,rk8602";
-		reg = <0x43>;
-		fcs,suspend-voltage-selector = <1>;
-		regulator-name = "vdd_cpu_big1_s0";
-		regulator-always-on;
-		regulator-boot-on;
-		regulator-min-microvolt = <550000>;
-		regulator-max-microvolt = <1050000>;
-		regulator-ramp-delay = <2300>;
-		vin-supply = <&vcc5v0_sys>;
-
-		regulator-state-mem {
-			regulator-off-in-suspend;
-		};
-	};
+	pinctrl-0 = <&hym8563_int>;
 };
 
 &i2c6 {
-	clock-frequency = <400000>;
-	status = "okay";
-
-	hym8563: rtc@51 {
-		compatible = "haoyu,hym8563";
-		reg = <0x51>;
+	usbc0: usb-typec@22 {
+		compatible = "fcs,fusb302";
+		reg = <0x22>;
 		interrupt-parent = <&gpio0>;
-		interrupts = <RK_PB0 IRQ_TYPE_LEVEL_LOW>;
-		#clock-cells = <0>;
-		clock-output-names = "hym8563";
+		interrupts = <RK_PD3 IRQ_TYPE_LEVEL_LOW>;
 		pinctrl-names = "default";
-		pinctrl-0 = <&hym8563_int>;
-		wakeup-source;
-	};
-};
-
-&i2c7 {
-	status = "okay";
-
-	/* PLDO2 vcca 1.8V, BUCK8 gated by PLDO2 being enabled */
-	es8388: audio-codec@11 {
-		compatible = "everest,es8388";
-		reg = <0x11>;
-		clocks = <&cru I2S0_8CH_MCLKOUT>;
-		AVDD-supply = <&vcc_1v8_s0>;
-		DVDD-supply = <&vcc_1v8_s0>;
-		HPVDD-supply = <&vcc_3v3_s0>;
-		PVDD-supply = <&vcc_3v3_s0>;
-		assigned-clocks = <&cru I2S0_8CH_MCLKOUT>;
-		assigned-clock-rates = <12288000>;
-		#sound-dai-cells = <0>;
-	};
-};
-
-&i2s0_8ch {
-	pinctrl-names = "default";
-	pinctrl-0 = <&i2s0_lrck
-		     &i2s0_mclk
-		     &i2s0_sclk
-		     &i2s0_sdi0
-		     &i2s0_sdo0>;
-	status = "okay";
-};
+		pinctrl-0 = <&usbc0_int>;
+		vbus-supply = <&vbus5v0_typec>;
+		status = "okay";
+
+		usb_con: connector {
+			compatible = "usb-c-connector";
+			data-role = "dual";
+			label = "USB-C";
+			power-role = "dual";
+			op-sink-microwatt = <10>;
+			source-pdos = <PDO_FIXED(5000, 1400, PDO_FIXED_USB_COMM)>;
+			sink-pdos = <PDO_FIXED(5000, 10, PDO_FIXED_USB_COMM)>;
+			try-power-role = "source";
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					reg = <0>;
+
+					usbc0_hs: endpoint {
+						remote-endpoint = <&usb_host0_xhci_drd_sw>;
+					};
+				};
 
-&i2s2_2ch {
-	pinctrl-names = "default";
-	pinctrl-0 = <&i2s2m0_lrck
-		     &i2s2m0_sclk
-		     &i2s2m0_sdi
-		     &i2s2m0_sdo>;
-	status = "okay";
-};
+				port@1 {
+					reg = <1>;
 
-&package_thermal {
-	polling-delay = <1000>;
+					usbc0_ss: endpoint {
+						remote-endpoint = <&usbdp_phy0_typec_ss>;
+					};
+				};
 
-	cooling-maps {
-		map0 {
-			trip = <&package_fan0>;
-			cooling-device = <&fan THERMAL_NO_LIMIT 1>;
-		};
+				port@2 {
+					reg = <2>;
 
-		map1 {
-			trip = <&package_fan1>;
-			cooling-device = <&fan 2 THERMAL_NO_LIMIT>;
+					usbc0_sbu: endpoint {
+						remote-endpoint = <&usbdp_phy0_typec_sbu>;
+					};
+				};
+			};
 		};
 	};
+};
 
-	trips {
-		package_fan0: package-fan0 {
-			temperature = <55000>;
-			hysteresis = <2000>;
-			type = "active";
-		};
+&led_blue_gpio {
+	gpios = <&gpio3 RK_PA6 GPIO_ACTIVE_HIGH>;
+	status = "okay";
+};
 
-		package_fan1: package-fan1 {
-			temperature = <65000>;
-			hysteresis = <2000>;
-			type = "active";
-		};
-	};
+&led_green_pwm {
+	pwms = <&pwm2 0 25000 0>;
 };
 
 /* phy1 - M.KEY socket */
@@ -445,16 +219,6 @@
 	status = "okay";
 };
 
-&pcie30phy {
-	status = "okay";
-};
-
-&pcie3x4 {
-	reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>;
-	vpcie3v3-supply = <&vcc3v3_pcie30>;
-	status = "okay";
-};
-
 &pinctrl {
 	hym8563 {
 		hym8563_int: hym8563-int {
@@ -485,6 +249,16 @@
 			rockchip,pins = <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
 		};
 	};
+
+	usb-typec {
+		usbc0_int: usbc0-int {
+			rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+
+		typec5v_pwren: typec5v-pwren {
+			rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
 };
 
 &pwm2 {
@@ -498,434 +272,68 @@
 	status = "okay";
 };
 
-&saradc {
-	vref-supply = <&vcc_1v8_s0>;
-	status = "okay";
-};
-
-&sdhci {
-	bus-width = <8>;
-	no-sdio;
-	no-sd;
-	non-removable;
-	max-frequency = <200000000>;
-	mmc-hs400-1_8v;
-	mmc-hs400-enhanced-strobe;
-	status = "okay";
-};
-
-&sdmmc {
-	bus-width = <4>;
-	cap-sd-highspeed;
-	cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
-	disable-wp;
-	max-frequency = <150000000>;
-	no-sdio;
-	no-mmc;
-	sd-uhs-sdr104;
-	vmmc-supply = <&vcc_3v3_s3>;
-	vqmmc-supply = <&vccio_sd_s0>;
+&recovery_button {
 	status = "okay";
 };
 
 &sfc {
 	pinctrl-names = "default";
 	pinctrl-0 = <&fspim1_pins>;
-	status = "okay";
+};
 
-	spi_flash: flash@0 {
-		compatible = "jedec,spi-nor";
-		reg = <0x0>;
-		spi-max-frequency = <100000000>;
-		spi-rx-bus-width = <4>;
-		spi-tx-bus-width = <1>;
-	};
+&u2phy1_otg {
+	phy-supply = <&vcc5v0_sys>;
 };
 
-&spi2 {
-	assigned-clocks = <&cru CLK_SPI2>;
-	assigned-clock-rates = <200000000>;
-	num-cs = <1>;
-	pinctrl-names = "default";
-	pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>;
+&uart9 {
+	pinctrl-0 = <&uart9m0_xfer>;
 	status = "okay";
+};
 
-	pmic@0 {
-		compatible = "rockchip,rk806";
-		reg = <0x0>;
-		interrupt-parent = <&gpio0>;
-		interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>,
-			    <&rk806_dvs2_null>, <&rk806_dvs3_null>;
-		spi-max-frequency = <1000000>;
-		system-power-controller;
-
-		vcc1-supply = <&vcc5v0_sys>;
-		vcc2-supply = <&vcc5v0_sys>;
-		vcc3-supply = <&vcc5v0_sys>;
-		vcc4-supply = <&vcc5v0_sys>;
-		vcc5-supply = <&vcc5v0_sys>;
-		vcc6-supply = <&vcc5v0_sys>;
-		vcc7-supply = <&vcc5v0_sys>;
-		vcc8-supply = <&vcc5v0_sys>;
-		vcc9-supply = <&vcc5v0_sys>;
-		vcc10-supply = <&vcc5v0_sys>;
-		vcc11-supply = <&vcc_2v0_pldo_s3>;
-		vcc12-supply = <&vcc5v0_sys>;
-		vcc13-supply = <&vdd2_ddr_s3>;
-		vcc14-supply = <&vdd2_ddr_s3>;
-		vcca-supply = <&vcc5v0_sys>;
-
-		gpio-controller;
-		#gpio-cells = <2>;
-
-		rk806_dvs1_null: dvs1-null-pins {
-			pins = "gpio_pwrctrl1";
-			function = "pin_fun0";
-		};
+&usbdp_phy0 {
+	mode-switch;
+	orientation-switch;
+	sbu1-dc-gpios = <&gpio4 RK_PA6 GPIO_ACTIVE_HIGH>;
+	sbu2-dc-gpios = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>;
 
-		rk806_dvs2_null: dvs2-null-pins {
-			pins = "gpio_pwrctrl2";
-			function = "pin_fun0";
-		};
+	port {
+		#address-cells = <1>;
+		#size-cells = <0>;
 
-		rk806_dvs3_null: dvs3-null-pins {
-			pins = "gpio_pwrctrl3";
-			function = "pin_fun0";
+		usbdp_phy0_typec_ss: endpoint@0 {
+			reg = <0>;
+			remote-endpoint = <&usbc0_ss>;
 		};
 
-		regulators {
-			vdd_gpu_s0: dcdc-reg1 {
-				regulator-name = "vdd_gpu_s0";
-				regulator-boot-on;
-				regulator-enable-ramp-delay = <400>;
-				regulator-min-microvolt = <550000>;
-				regulator-max-microvolt = <950000>;
-				regulator-ramp-delay = <12500>;
-
-				regulator-state-mem {
-					regulator-off-in-suspend;
-				};
-			};
-
-			vdd_cpu_lit_s0: dcdc-reg2 {
-				regulator-name = "vdd_cpu_lit_s0";
-				regulator-always-on;
-				regulator-boot-on;
-				regulator-min-microvolt = <550000>;
-				regulator-max-microvolt = <950000>;
-				regulator-ramp-delay = <12500>;
-
-				regulator-state-mem {
-					regulator-off-in-suspend;
-				};
-			};
-
-			vdd_log_s0: dcdc-reg3 {
-				regulator-name = "vdd_log_s0";
-				regulator-always-on;
-				regulator-boot-on;
-				regulator-min-microvolt = <675000>;
-				regulator-max-microvolt = <825000>;
-				regulator-ramp-delay = <12500>;
-
-				regulator-state-mem {
-					regulator-off-in-suspend;
-					regulator-suspend-microvolt = <750000>;
-				};
-			};
-
-			vdd_vdenc_s0: dcdc-reg4 {
-				regulator-name = "vdd_vdenc_s0";
-				regulator-always-on;
-				regulator-boot-on;
-				regulator-min-microvolt = <550000>;
-				regulator-max-microvolt = <825000>;
-				regulator-ramp-delay = <12500>;
-
-				regulator-state-mem {
-					regulator-off-in-suspend;
-				};
-			};
-
-			vdd_ddr_s0: dcdc-reg5 {
-				regulator-name = "vdd_ddr_s0";
-				regulator-always-on;
-				regulator-boot-on;
-				regulator-min-microvolt = <675000>;
-				regulator-max-microvolt = <900000>;
-				regulator-ramp-delay = <12500>;
-
-				regulator-state-mem {
-					regulator-off-in-suspend;
-					regulator-suspend-microvolt = <850000>;
-				};
-			};
-
-			vdd2_ddr_s3: dcdc-reg6 {
-				regulator-name = "vdd2_ddr_s3";
-				regulator-always-on;
-				regulator-boot-on;
-
-				regulator-state-mem {
-					regulator-on-in-suspend;
-				};
-			};
-
-			vcc_2v0_pldo_s3: dcdc-reg7 {
-				regulator-name = "vdd_2v0_pldo_s3";
-				regulator-always-on;
-				regulator-boot-on;
-				regulator-min-microvolt = <2000000>;
-				regulator-max-microvolt = <2000000>;
-				regulator-ramp-delay = <12500>;
-
-				regulator-state-mem {
-					regulator-on-in-suspend;
-					regulator-suspend-microvolt = <2000000>;
-				};
-			};
-
-			vcc_3v3_s3: dcdc-reg8 {
-				regulator-name = "vcc_3v3_s3";
-				regulator-always-on;
-				regulator-boot-on;
-				regulator-min-microvolt = <3300000>;
-				regulator-max-microvolt = <3300000>;
-
-				regulator-state-mem {
-					regulator-on-in-suspend;
-					regulator-suspend-microvolt = <3300000>;
-				};
-			};
-
-			vddq_ddr_s0: dcdc-reg9 {
-				regulator-name = "vddq_ddr_s0";
-				regulator-always-on;
-				regulator-boot-on;
-
-				regulator-state-mem {
-					regulator-off-in-suspend;
-				};
-			};
-
-			vcc_1v8_s3: dcdc-reg10 {
-				regulator-name = "vcc_1v8_s3";
-				regulator-always-on;
-				regulator-boot-on;
-				regulator-min-microvolt = <1800000>;
-				regulator-max-microvolt = <1800000>;
-
-				regulator-state-mem {
-					regulator-on-in-suspend;
-					regulator-suspend-microvolt = <1800000>;
-				};
-			};
-
-			avcc_1v8_s0: pldo-reg1 {
-				regulator-name = "avcc_1v8_s0";
-				regulator-always-on;
-				regulator-boot-on;
-				regulator-min-microvolt = <1800000>;
-				regulator-max-microvolt = <1800000>;
-
-				regulator-state-mem {
-					regulator-off-in-suspend;
-					regulator-suspend-microvolt = <1800000>;
-				};
-			};
-
-			/* shorted to avcc_1v8_s0 on the board */
-			vcc_1v8_s0: pldo-reg2 {
-				regulator-name = "vcc_1v8_s0";
-				regulator-always-on;
-				regulator-boot-on;
-				regulator-min-microvolt = <1800000>;
-				regulator-max-microvolt = <1800000>;
-
-				regulator-state-mem {
-					regulator-off-in-suspend;
-					regulator-suspend-microvolt = <1800000>;
-				};
-			};
-
-			avdd_1v2_s0: pldo-reg3 {
-				regulator-name = "avdd_1v2_s0";
-				regulator-always-on;
-				regulator-boot-on;
-				regulator-min-microvolt = <1200000>;
-				regulator-max-microvolt = <1200000>;
-
-				regulator-state-mem {
-					regulator-off-in-suspend;
-				};
-			};
-
-			vcc_3v3_s0: pldo-reg4 {
-				regulator-name = "vcc_3v3_s0";
-				regulator-always-on;
-				regulator-boot-on;
-				regulator-min-microvolt = <3300000>;
-				regulator-max-microvolt = <3300000>;
-				regulator-ramp-delay = <12500>;
-
-				regulator-state-mem {
-					regulator-off-in-suspend;
-				};
-			};
-
-			vccio_sd_s0: pldo-reg5 {
-				regulator-name = "vccio_sd_s0";
-				regulator-always-on;
-				regulator-boot-on;
-				regulator-min-microvolt = <1800000>;
-				regulator-max-microvolt = <3300000>;
-				regulator-ramp-delay = <12500>;
-
-				regulator-state-mem {
-					regulator-off-in-suspend;
-				};
-			};
-
-			pldo6_s3: pldo-reg6 {
-				regulator-name = "pldo6_s3";
-				regulator-always-on;
-				regulator-boot-on;
-				regulator-min-microvolt = <1800000>;
-				regulator-max-microvolt = <1800000>;
-
-				regulator-state-mem {
-					regulator-on-in-suspend;
-					regulator-suspend-microvolt = <1800000>;
-				};
-			};
-
-			vdd_0v75_s3: nldo-reg1 {
-				regulator-name = "vdd_0v75_s3";
-				regulator-always-on;
-				regulator-boot-on;
-				regulator-min-microvolt = <750000>;
-				regulator-max-microvolt = <750000>;
-
-				regulator-state-mem {
-					regulator-on-in-suspend;
-					regulator-suspend-microvolt = <750000>;
-				};
-			};
-
-			vdd_ddr_pll_s0: nldo-reg2 {
-				regulator-name = "vdd_ddr_pll_s0";
-				regulator-always-on;
-				regulator-boot-on;
-				regulator-min-microvolt = <850000>;
-				regulator-max-microvolt = <850000>;
-
-				regulator-state-mem {
-					regulator-off-in-suspend;
-					regulator-suspend-microvolt = <850000>;
-				};
-			};
-
-			avdd_0v75_s0: nldo-reg3 {
-				regulator-name = "avdd_0v75_s0";
-				regulator-always-on;
-				regulator-boot-on;
-				/*
-				 * The schematic mentions that actual setting
-				 * should be 0.8375V. RK3588 datasheet specifies
-				 * maximum as 0.825V. So we set datasheet max
-				 * here.
-				 */
-				regulator-min-microvolt = <825000>;
-				regulator-max-microvolt = <825000>;
-
-				regulator-state-mem {
-					regulator-off-in-suspend;
-				};
-			};
-
-			vdd_0v85_s0: nldo-reg4 {
-				regulator-name = "vdd_0v85_s0";
-				regulator-always-on;
-				regulator-boot-on;
-				regulator-min-microvolt = <850000>;
-				regulator-max-microvolt = <850000>;
-
-				regulator-state-mem {
-					regulator-off-in-suspend;
-				};
-			};
-
-			vdd_0v75_s0: nldo-reg5 {
-				regulator-name = "vdd_0v75_s0";
-				regulator-always-on;
-				regulator-boot-on;
-				regulator-min-microvolt = <750000>;
-				regulator-max-microvolt = <750000>;
-
-				regulator-state-mem {
-					regulator-off-in-suspend;
-				};
-			};
+		usbdp_phy0_typec_sbu: endpoint@1 {
+			reg = <1>;
+			remote-endpoint = <&usbc0_sbu>;
 		};
 	};
 };
 
-&tsadc {
-	status = "okay";
-};
+&usb_host0_xhci {
+	usb-role-switch;
 
-&u2phy2 {
-	status = "okay";
-};
-
-&u2phy3 {
-	status = "okay";
-};
-
-&u2phy2_host {
-	phy-supply = <&vcc5v0_usb20>;
-	status = "okay";
-};
-
-&u2phy3_host {
-	phy-supply = <&vcc5v0_usb20>;
-	status = "okay";
-};
-
-&uart2 {
-	pinctrl-0 = <&uart2m0_xfer>;
-	status = "okay";
-};
-
-&uart9 {
-	pinctrl-0 = <&uart9m0_xfer>;
-	status = "okay";
-};
-
-&usb_host0_ehci {
-	status = "okay";
-};
-
-&usb_host0_ohci {
-	status = "okay";
-};
-
-&usb_host1_ehci {
-	status = "okay";
+	port {
+		usb_host0_xhci_drd_sw: endpoint {
+			remote-endpoint = <&usbc0_hs>;
+		};
+	};
 };
 
-&usb_host1_ohci {
-	status = "okay";
+&vcc3v3_pcie_eth {
+	gpios = <&gpio3 RK_PB4 GPIO_ACTIVE_LOW>;
 };
 
-&vop_mmu {
+&vcc3v3_wf {
 	status = "okay";
 };
 
-&vop {
-	status = "okay";
+&vcc5v0_usb20 {
+	gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_HIGH>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&vcc5v0_usb20_en>;
 };
 
 &vp0 {
diff --git a/dts/upstream/src/arm64/rockchip/rk3588-orangepi-5.dtsi b/dts/upstream/src/arm64/rockchip/rk3588-orangepi-5.dtsi
new file mode 100644
index 00000000000..a98e804a094
--- /dev/null
+++ b/dts/upstream/src/arm64/rockchip/rk3588-orangepi-5.dtsi
@@ -0,0 +1,805 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2023 Ondřej Jirman <megi@xff.cz>
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+#include <dt-bindings/usb/pd.h>
+#include "rk3588.dtsi"
+
+/ {
+	aliases {
+		mmc0 = &sdhci;
+		mmc1 = &sdmmc;
+	};
+
+	chosen {
+		stdout-path = "serial2:1500000n8";
+	};
+
+	adc-keys-0 {
+		compatible = "adc-keys";
+		io-channels = <&saradc 0>;
+		io-channel-names = "buttons";
+		keyup-threshold-microvolt = <1800000>;
+		poll-interval = <100>;
+
+		button-maskrom {
+			label = "Mask Rom";
+			linux,code = <KEY_SETUP>;
+			press-threshold-microvolt = <2000>;
+		};
+	};
+
+	recovery_button: adc-keys-1 {
+		compatible = "adc-keys";
+		io-channels = <&saradc 1>;
+		io-channel-names = "buttons";
+		keyup-threshold-microvolt = <1800000>;
+		poll-interval = <100>;
+		status = "disabled";
+
+		button-recovery {
+			label = "Recovery";
+			linux,code = <KEY_VENDOR>;
+			press-threshold-microvolt = <2000>;
+		};
+	};
+
+	speaker_amp: speaker-audio-amplifier {
+		compatible = "simple-audio-amplifier";
+		sound-name-prefix = "Speaker Amp";
+		status = "disabled";
+	};
+
+	headphone_amp: headphones-audio-amplifier {
+		compatible = "simple-audio-amplifier";
+		sound-name-prefix = "Headphones Amp";
+	};
+
+	gpio-leds {
+		compatible = "gpio-leds";
+
+		led_blue_gpio: led {
+			color = <LED_COLOR_ID_BLUE>;
+			function = LED_FUNCTION_INDICATOR;
+			function-enumerator = <1>;
+			status = "disabled";
+		};
+	};
+
+	fan: pwm-fan {
+		compatible = "pwm-fan";
+		cooling-levels = <0 70 75 80 100>;
+		fan-supply = <&vcc5v0_sys>;
+		#cooling-cells = <2>;
+	};
+
+	pwm-leds {
+		compatible = "pwm-leds";
+
+		led_blue_pwm: led-1 {
+			color = <LED_COLOR_ID_BLUE>;
+			function = LED_FUNCTION_STATUS;
+			linux,default-trigger = "heartbeat";
+			max-brightness = <255>;
+			status = "disabled";
+		};
+
+		led_green_pwm: led-2 {
+			color = <LED_COLOR_ID_GREEN>;
+			function = LED_FUNCTION_INDICATOR;
+			function-enumerator = <2>;
+			max-brightness = <255>;
+		};
+	};
+
+	rfkill {
+		compatible = "rfkill-gpio";
+		label = "rfkill-pcie-wlan";
+		radio-type = "wlan";
+		shutdown-gpios = <&gpio0 RK_PC4 GPIO_ACTIVE_HIGH>;
+	};
+
+	analog_sound: sound {
+		compatible = "simple-audio-card";
+		simple-audio-card,name = "Analog";
+		simple-audio-card,format = "i2s";
+		simple-audio-card,mclk-fs = <256>;
+		simple-audio-card,bitclock-master = <&daicpu>;
+		simple-audio-card,frame-master = <&daicpu>;
+		/*TODO: SARADC_IN3 is used as MIC detection / key input */
+
+		daicpu: simple-audio-card,cpu {
+			sound-dai = <&i2s0_8ch>;
+			system-clock-frequency = <12288000>;
+		};
+
+		daicodec: simple-audio-card,codec {
+			sound-dai = <&es8388>;
+			system-clock-frequency = <12288000>;
+		};
+	};
+
+	vcc3v3_pcie30: regulator-vcc3v3-pcie30 {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpios = <&gpio2 RK_PB6 GPIO_ACTIVE_HIGH>;
+		regulator-name = "vcc3v3_pcie30";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		startup-delay-us = <5000>;
+		vin-supply = <&vcc5v0_sys>;
+	};
+
+	vcc3v3_pcie_eth: regulator-vcc3v3-pcie-eth {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc3v3_pcie_eth";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		startup-delay-us = <50000>;
+		vin-supply = <&vcc_3v3_s3>;
+	};
+
+	vcc3v3_wf: regulator-vcc3v3-wf {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpios = <&gpio2 RK_PC5 GPIO_ACTIVE_HIGH>;
+		regulator-name = "vcc3v3_wf";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		startup-delay-us = <50000>;
+		vin-supply = <&vcc5v0_sys>;
+		status = "disabled";
+	};
+
+	vcc5v0_sys: regulator-vcc5v0-sys {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc5v0_sys";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+	};
+
+	vcc5v0_usb20: regulator-vcc5v0-usb20 {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		regulator-name = "vcc5v0_usb20";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		vin-supply = <&vcc5v0_sys>;
+	};
+};
+
+&combphy2_psu {
+	status = "okay";
+};
+
+&cpu_b0 {
+	cpu-supply = <&vdd_cpu_big0_s0>;
+};
+
+&cpu_b1 {
+	cpu-supply = <&vdd_cpu_big0_s0>;
+};
+
+&cpu_b2 {
+	cpu-supply = <&vdd_cpu_big1_s0>;
+};
+
+&cpu_b3 {
+	cpu-supply = <&vdd_cpu_big1_s0>;
+};
+
+&cpu_l0 {
+	cpu-supply = <&vdd_cpu_lit_s0>;
+};
+
+&cpu_l1 {
+	cpu-supply = <&vdd_cpu_lit_s0>;
+};
+
+&cpu_l2 {
+	cpu-supply = <&vdd_cpu_lit_s0>;
+};
+
+&cpu_l3 {
+	cpu-supply = <&vdd_cpu_lit_s0>;
+};
+
+&gpu {
+	mali-supply = <&vdd_gpu_s0>;
+	status = "okay";
+};
+
+&i2c0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c0m2_xfer>;
+	status = "okay";
+
+	vdd_cpu_big0_s0: regulator@42 {
+		compatible = "rockchip,rk8602";
+		reg = <0x42>;
+		fcs,suspend-voltage-selector = <1>;
+		regulator-name = "vdd_cpu_big0_s0";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <550000>;
+		regulator-max-microvolt = <1050000>;
+		regulator-ramp-delay = <2300>;
+		vin-supply = <&vcc5v0_sys>;
+
+		regulator-state-mem {
+			regulator-off-in-suspend;
+		};
+	};
+
+	vdd_cpu_big1_s0: regulator@43 {
+		compatible = "rockchip,rk8603", "rockchip,rk8602";
+		reg = <0x43>;
+		fcs,suspend-voltage-selector = <1>;
+		regulator-name = "vdd_cpu_big1_s0";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <550000>;
+		regulator-max-microvolt = <1050000>;
+		regulator-ramp-delay = <2300>;
+		vin-supply = <&vcc5v0_sys>;
+
+		regulator-state-mem {
+			regulator-off-in-suspend;
+		};
+	};
+};
+
+&i2c6 {
+	clock-frequency = <400000>;
+	status = "okay";
+
+	hym8563: rtc@51 {
+		compatible = "haoyu,hym8563";
+		reg = <0x51>;
+		#clock-cells = <0>;
+		clock-output-names = "hym8563";
+		wakeup-source;
+	};
+};
+
+&i2c7 {
+	status = "okay";
+
+	/* PLDO2 vcca 1.8V, BUCK8 gated by PLDO2 being enabled */
+	es8388: audio-codec@11 {
+		compatible = "everest,es8388";
+		reg = <0x11>;
+		clocks = <&cru I2S0_8CH_MCLKOUT>;
+		AVDD-supply = <&vcc_3v3_s0>;
+		DVDD-supply = <&vcc_1v8_s0>;
+		HPVDD-supply = <&vcc_3v3_s0>;
+		PVDD-supply = <&vcc_1v8_s0>;
+		assigned-clocks = <&cru I2S0_8CH_MCLKOUT>;
+		assigned-clock-rates = <12288000>;
+		#sound-dai-cells = <0>;
+	};
+};
+
+&i2s0_8ch {
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2s0_lrck
+		     &i2s0_mclk
+		     &i2s0_sclk
+		     &i2s0_sdi0
+		     &i2s0_sdo0>;
+	status = "okay";
+};
+
+&i2s2_2ch {
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2s2m0_lrck
+		     &i2s2m0_sclk
+		     &i2s2m0_sdi
+		     &i2s2m0_sdo>;
+	status = "okay";
+};
+
+&package_thermal {
+	polling-delay = <1000>;
+
+	cooling-maps {
+		map0 {
+			trip = <&package_fan0>;
+			cooling-device = <&fan THERMAL_NO_LIMIT 1>;
+		};
+
+		map1 {
+			trip = <&package_fan1>;
+			cooling-device = <&fan 2 THERMAL_NO_LIMIT>;
+		};
+	};
+
+	trips {
+		package_fan0: package-fan0 {
+			temperature = <55000>;
+			hysteresis = <2000>;
+			type = "active";
+		};
+
+		package_fan1: package-fan1 {
+			temperature = <65000>;
+			hysteresis = <2000>;
+			type = "active";
+		};
+	};
+};
+
+&pcie30phy {
+	status = "okay";
+};
+
+&pcie3x4 {
+	reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>;
+	vpcie3v3-supply = <&vcc3v3_pcie30>;
+	status = "okay";
+};
+
+&saradc {
+	vref-supply = <&vcc_1v8_s0>;
+	status = "okay";
+};
+
+&sdhci {
+	bus-width = <8>;
+	no-sdio;
+	no-sd;
+	non-removable;
+	max-frequency = <200000000>;
+	mmc-hs400-1_8v;
+	mmc-hs400-enhanced-strobe;
+	status = "okay";
+};
+
+&sdmmc {
+	bus-width = <4>;
+	cap-sd-highspeed;
+	cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
+	disable-wp;
+	max-frequency = <150000000>;
+	no-sdio;
+	no-mmc;
+	sd-uhs-sdr104;
+	vmmc-supply = <&vcc_3v3_s3>;
+	vqmmc-supply = <&vccio_sd_s0>;
+	status = "okay";
+};
+
+&sfc {
+	status = "okay";
+
+	spi_flash: flash@0 {
+		compatible = "jedec,spi-nor";
+		reg = <0x0>;
+		spi-max-frequency = <100000000>;
+		spi-rx-bus-width = <4>;
+		spi-tx-bus-width = <1>;
+	};
+};
+
+&spi2 {
+	assigned-clocks = <&cru CLK_SPI2>;
+	assigned-clock-rates = <200000000>;
+	num-cs = <1>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>;
+	status = "okay";
+
+	pmic@0 {
+		compatible = "rockchip,rk806";
+		reg = <0x0>;
+		interrupt-parent = <&gpio0>;
+		interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>,
+			    <&rk806_dvs2_null>, <&rk806_dvs3_null>;
+		spi-max-frequency = <1000000>;
+		system-power-controller;
+
+		vcc1-supply = <&vcc5v0_sys>;
+		vcc2-supply = <&vcc5v0_sys>;
+		vcc3-supply = <&vcc5v0_sys>;
+		vcc4-supply = <&vcc5v0_sys>;
+		vcc5-supply = <&vcc5v0_sys>;
+		vcc6-supply = <&vcc5v0_sys>;
+		vcc7-supply = <&vcc5v0_sys>;
+		vcc8-supply = <&vcc5v0_sys>;
+		vcc9-supply = <&vcc5v0_sys>;
+		vcc10-supply = <&vcc5v0_sys>;
+		vcc11-supply = <&vcc_2v0_pldo_s3>;
+		vcc12-supply = <&vcc5v0_sys>;
+		vcc13-supply = <&vdd2_ddr_s3>;
+		vcc14-supply = <&vdd2_ddr_s3>;
+		vcca-supply = <&vcc5v0_sys>;
+
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		rk806_dvs1_null: dvs1-null-pins {
+			pins = "gpio_pwrctrl1";
+			function = "pin_fun0";
+		};
+
+		rk806_dvs2_null: dvs2-null-pins {
+			pins = "gpio_pwrctrl2";
+			function = "pin_fun0";
+		};
+
+		rk806_dvs3_null: dvs3-null-pins {
+			pins = "gpio_pwrctrl3";
+			function = "pin_fun0";
+		};
+
+		regulators {
+			vdd_gpu_s0: dcdc-reg1 {
+				regulator-name = "vdd_gpu_s0";
+				regulator-boot-on;
+				regulator-enable-ramp-delay = <400>;
+				regulator-min-microvolt = <550000>;
+				regulator-max-microvolt = <950000>;
+				regulator-ramp-delay = <12500>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdd_cpu_lit_s0: dcdc-reg2 {
+				regulator-name = "vdd_cpu_lit_s0";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <550000>;
+				regulator-max-microvolt = <950000>;
+				regulator-ramp-delay = <12500>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdd_log_s0: dcdc-reg3 {
+				regulator-name = "vdd_log_s0";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <675000>;
+				regulator-max-microvolt = <825000>;
+				regulator-ramp-delay = <12500>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+					regulator-suspend-microvolt = <750000>;
+				};
+			};
+
+			vdd_vdenc_s0: dcdc-reg4 {
+				regulator-name = "vdd_vdenc_s0";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <550000>;
+				regulator-max-microvolt = <825000>;
+				regulator-ramp-delay = <12500>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdd_ddr_s0: dcdc-reg5 {
+				regulator-name = "vdd_ddr_s0";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <675000>;
+				regulator-max-microvolt = <900000>;
+				regulator-ramp-delay = <12500>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+					regulator-suspend-microvolt = <850000>;
+				};
+			};
+
+			vdd2_ddr_s3: dcdc-reg6 {
+				regulator-name = "vdd2_ddr_s3";
+				regulator-always-on;
+				regulator-boot-on;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+				};
+			};
+
+			vcc_2v0_pldo_s3: dcdc-reg7 {
+				regulator-name = "vdd_2v0_pldo_s3";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <2000000>;
+				regulator-max-microvolt = <2000000>;
+				regulator-ramp-delay = <12500>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <2000000>;
+				};
+			};
+
+			vcc_3v3_s3: dcdc-reg8 {
+				regulator-name = "vcc_3v3_s3";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <3300000>;
+				};
+			};
+
+			vddq_ddr_s0: dcdc-reg9 {
+				regulator-name = "vddq_ddr_s0";
+				regulator-always-on;
+				regulator-boot-on;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_1v8_s3: dcdc-reg10 {
+				regulator-name = "vcc_1v8_s3";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			avcc_1v8_s0: pldo-reg1 {
+				regulator-name = "avcc_1v8_s0";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			/* shorted to avcc_1v8_s0 on the board */
+			vcc_1v8_s0: pldo-reg2 {
+				regulator-name = "vcc_1v8_s0";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			avdd_1v2_s0: pldo-reg3 {
+				regulator-name = "avdd_1v2_s0";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1200000>;
+				regulator-max-microvolt = <1200000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_3v3_s0: pldo-reg4 {
+				regulator-name = "vcc_3v3_s0";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-ramp-delay = <12500>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vccio_sd_s0: pldo-reg5 {
+				regulator-name = "vccio_sd_s0";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-ramp-delay = <12500>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			pldo6_s3: pldo-reg6 {
+				regulator-name = "pldo6_s3";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			vdd_0v75_s3: nldo-reg1 {
+				regulator-name = "vdd_0v75_s3";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <750000>;
+				regulator-max-microvolt = <750000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <750000>;
+				};
+			};
+
+			vdd_ddr_pll_s0: nldo-reg2 {
+				regulator-name = "vdd_ddr_pll_s0";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <850000>;
+				regulator-max-microvolt = <850000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+					regulator-suspend-microvolt = <850000>;
+				};
+			};
+
+			avdd_0v75_s0: nldo-reg3 {
+				regulator-name = "avdd_0v75_s0";
+				regulator-always-on;
+				regulator-boot-on;
+				/*
+				 * The schematic mentions that actual setting
+				 * should be 0.8375V. RK3588 datasheet specifies
+				 * maximum as 0.825V. So we set datasheet max
+				 * here.
+				 */
+				regulator-min-microvolt = <825000>;
+				regulator-max-microvolt = <825000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdd_0v85_s0: nldo-reg4 {
+				regulator-name = "vdd_0v85_s0";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <850000>;
+				regulator-max-microvolt = <850000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdd_0v75_s0: nldo-reg5 {
+				regulator-name = "vdd_0v75_s0";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <750000>;
+				regulator-max-microvolt = <750000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+		};
+	};
+};
+
+&tsadc {
+	status = "okay";
+};
+
+&u2phy0 {
+	status = "okay";
+};
+
+&u2phy0_otg {
+	status = "okay";
+};
+
+&u2phy1 {
+	status = "okay";
+};
+
+&u2phy1_otg {
+	status = "okay";
+};
+
+&u2phy2 {
+	status = "okay";
+};
+
+&u2phy3 {
+	status = "okay";
+};
+
+&u2phy2_host {
+	phy-supply = <&vcc5v0_usb20>;
+	status = "okay";
+};
+
+&u2phy3_host {
+	phy-supply = <&vcc5v0_usb20>;
+	status = "okay";
+};
+
+&uart2 {
+	pinctrl-0 = <&uart2m0_xfer>;
+	status = "okay";
+};
+
+&usbdp_phy0 {
+	status = "okay";
+};
+
+&usbdp_phy1 {
+	status = "okay";
+};
+
+&usb_host0_ehci {
+	status = "okay";
+};
+
+&usb_host0_ohci {
+	status = "okay";
+};
+
+&usb_host0_xhci {
+	status = "okay";
+};
+
+&usb_host1_ehci {
+	status = "okay";
+};
+
+&usb_host1_ohci {
+	status = "okay";
+};
+
+&usb_host1_xhci {
+	dr_mode = "host";
+	status = "okay";
+};
+
+&vop_mmu {
+	status = "okay";
+};
+
+&vop {
+	status = "okay";
+};
diff --git a/dts/upstream/src/arm64/rockchip/rk3588-rock-5-itx.dts b/dts/upstream/src/arm64/rockchip/rk3588-rock-5-itx.dts
index 6d68f70284e..2a059020946 100644
--- a/dts/upstream/src/arm64/rockchip/rk3588-rock-5-itx.dts
+++ b/dts/upstream/src/arm64/rockchip/rk3588-rock-5-itx.dts
@@ -690,10 +690,9 @@
 
 &sdhci {
 	bus-width = <8>;
-	max-frequency = <200000000>;
+	max-frequency = <150000000>;
 	mmc-hs400-1_8v;
 	mmc-hs400-enhanced-strobe;
-	mmc-hs200-1_8v;
 	no-sdio;
 	no-sd;
 	non-removable;
diff --git a/dts/upstream/src/arm64/rockchip/rk3588-rock-5b-pcie-ep.dtso b/dts/upstream/src/arm64/rockchip/rk3588-rock-5b-pcie-ep.dtso
index 672d748fcc6..f229cb49da6 100644
--- a/dts/upstream/src/arm64/rockchip/rk3588-rock-5b-pcie-ep.dtso
+++ b/dts/upstream/src/arm64/rockchip/rk3588-rock-5b-pcie-ep.dtso
@@ -23,3 +23,7 @@
 	vpcie3v3-supply = <&vcc3v3_pcie30>;
 	status = "okay";
 };
+
+&mmu600_pcie {
+	status = "disabled";
+};
diff --git a/dts/upstream/src/arm64/rockchip/rk3588-tiger.dtsi b/dts/upstream/src/arm64/rockchip/rk3588-tiger.dtsi
index 81a6a05ce13..e8fa449517c 100644
--- a/dts/upstream/src/arm64/rockchip/rk3588-tiger.dtsi
+++ b/dts/upstream/src/arm64/rockchip/rk3588-tiger.dtsi
@@ -386,7 +386,6 @@
 	non-removable;
 	pinctrl-names = "default";
 	pinctrl-0 = <&emmc_bus8 &emmc_cmd &emmc_clk &emmc_data_strobe>;
-	supports-cqe;
 	vmmc-supply = <&vcc_3v3_s3>;
 	vqmmc-supply = <&vcc_1v8_s3>;
 	status = "okay";
diff --git a/dts/upstream/src/arm64/rockchip/rk3588s-nanopi-r6.dtsi b/dts/upstream/src/arm64/rockchip/rk3588s-nanopi-r6.dtsi
index c9749cb5007..d2eddea1840 100644
--- a/dts/upstream/src/arm64/rockchip/rk3588s-nanopi-r6.dtsi
+++ b/dts/upstream/src/arm64/rockchip/rk3588s-nanopi-r6.dtsi
@@ -775,6 +775,15 @@
 	status = "okay";
 };
 
+&u2phy0 {
+	status = "okay";
+};
+
+&u2phy0_otg {
+	phy-supply = <&vcc5v0_usb_otg0>;
+	status = "okay";
+};
+
 &u2phy2 {
 	status = "okay";
 };
@@ -797,6 +806,15 @@
 	status = "okay";
 };
 
+&usb_host0_xhci {
+	dr_mode = "host";
+	status = "okay";
+};
+
+&usbdp_phy0 {
+	status = "okay";
+};
+
 &vop {
 	status = "okay";
 };
diff --git a/dts/upstream/src/arm64/socionext/uniphier-ld11-global.dts b/dts/upstream/src/arm64/socionext/uniphier-ld11-global.dts
index a251c434354..de219570bbc 100644
--- a/dts/upstream/src/arm64/socionext/uniphier-ld11-global.dts
+++ b/dts/upstream/src/arm64/socionext/uniphier-ld11-global.dts
@@ -61,7 +61,7 @@
 			&i2s_port4
 			&spdif_port0
 			&comp_spdif_port0>;
-		hp-det-gpio = <&gpio UNIPHIER_GPIO_IRQ(0) GPIO_ACTIVE_LOW>;
+		hp-det-gpios = <&gpio UNIPHIER_GPIO_IRQ(0) GPIO_ACTIVE_LOW>;
 	};
 
 	spdif-out {
diff --git a/dts/upstream/src/arm64/socionext/uniphier-ld20-global.dts b/dts/upstream/src/arm64/socionext/uniphier-ld20-global.dts
index 79f6db2455c..20e5fb724fa 100644
--- a/dts/upstream/src/arm64/socionext/uniphier-ld20-global.dts
+++ b/dts/upstream/src/arm64/socionext/uniphier-ld20-global.dts
@@ -61,7 +61,7 @@
 			&i2s_port4
 			&spdif_port0
 			&comp_spdif_port0>;
-		hp-det-gpio = <&gpio UNIPHIER_GPIO_IRQ(0) GPIO_ACTIVE_LOW>;
+		hp-det-gpios = <&gpio UNIPHIER_GPIO_IRQ(0) GPIO_ACTIVE_LOW>;
 	};
 
 	spdif-out {
diff --git a/dts/upstream/src/arm64/sprd/sc2731.dtsi b/dts/upstream/src/arm64/sprd/sc2731.dtsi
index 12136e68dad..458685b8246 100644
--- a/dts/upstream/src/arm64/sprd/sc2731.dtsi
+++ b/dts/upstream/src/arm64/sprd/sc2731.dtsi
@@ -94,17 +94,17 @@
 			nvmem-cells = <&adc_big_scale>, <&adc_small_scale>;
 		};
 
-		fuel-gauge@a00 {
+		pmic_fgu: fuel-gauge@a00 {
 			compatible = "sprd,sc2731-fgu";
 			reg = <0xa00>;
-			bat-detect-gpio = <&pmic_eic 9 GPIO_ACTIVE_HIGH>;
+			battery-detect-gpios = <&pmic_eic 9 GPIO_ACTIVE_HIGH>;
 			io-channels = <&pmic_adc 3>, <&pmic_adc 6>;
 			io-channel-names = "bat-temp", "charge-vol";
-			monitored-battery = <&bat>;
 			nvmem-cell-names = "fgu_calib";
 			nvmem-cells = <&fgu_calib>;
 			interrupt-parent = <&sc2731_pmic>;
 			interrupts = <4>;
+			status = "disabled";
 		};
 
 		vibrator@ec8 {
diff --git a/dts/upstream/src/arm64/sprd/sc9863a.dtsi b/dts/upstream/src/arm64/sprd/sc9863a.dtsi
index e5a2857721e..e97000e560e 100644
--- a/dts/upstream/src/arm64/sprd/sc9863a.dtsi
+++ b/dts/upstream/src/arm64/sprd/sc9863a.dtsi
@@ -163,18 +163,18 @@
 		ap_clk: clock-controller@21500000 {
 			compatible = "sprd,sc9863a-ap-clk";
 			reg = <0 0x21500000 0 0x1000>;
-			clocks = <&ext_32k>, <&ext_26m>;
-			clock-names = "ext-32k", "ext-26m";
+			clocks = <&ext_26m>, <&ext_32k>;
+			clock-names = "ext-26m", "ext-32k";
 			#clock-cells = <1>;
 		};
 
 		aon_clk: clock-controller@402d0000 {
 			compatible = "sprd,sc9863a-aon-clk";
 			reg = <0 0x402d0000 0 0x1000>;
-			clocks = <&ext_26m>, <&rco_100m>,
-				 <&ext_32k>, <&ext_4m>;
-			clock-names = "ext-26m", "rco-100m",
-				      "ext-32k", "ext-4m";
+			clocks = <&ext_26m>, <&ext_32k>,
+				 <&ext_4m>, <&rco_100m>;
+			clock-names = "ext-26m", "ext-32k",
+				      "ext-4m", "rco-100m";
 			#clock-cells = <1>;
 		};
 
@@ -288,7 +288,7 @@
 				};
 			};
 
-			in-port {
+			in-ports {
 				port {
 					etf_little_in: endpoint {
 						remote-endpoint =
diff --git a/dts/upstream/src/arm64/sprd/sp9860g-1h10.dts b/dts/upstream/src/arm64/sprd/sp9860g-1h10.dts
index 095b24a3131..b1fa817ece1 100644
--- a/dts/upstream/src/arm64/sprd/sp9860g-1h10.dts
+++ b/dts/upstream/src/arm64/sprd/sp9860g-1h10.dts
@@ -71,8 +71,8 @@
 		compatible = "simple-battery";
 		charge-full-design-microamp-hours = <1900000>;
 		charge-term-current-microamp = <120000>;
-		constant_charge_voltage_max_microvolt = <4350000>;
-		internal-resistance-micro-ohms = <250000>;
+		constant-charge-voltage-max-microvolt = <4350000>;
+		factory-internal-resistance-micro-ohms = <250000>;
 		ocv-capacity-celsius = <20>;
 		ocv-capacity-table-0 = <4185000 100>, <4113000 95>, <4066000 90>,
 			<4022000 85>, <3983000 80>, <3949000 75>,
@@ -84,6 +84,11 @@
 	};
 };
 
+&pmic_fgu {
+	monitored-battery = <&bat>;
+	status = "okay";
+};
+
 &uart0 {
 	status = "okay";
 };
diff --git a/dts/upstream/src/arm64/st/stm32mp251.dtsi b/dts/upstream/src/arm64/st/stm32mp251.dtsi
index 6fe12e3bd7d..f3c6cdfd700 100644
--- a/dts/upstream/src/arm64/st/stm32mp251.dtsi
+++ b/dts/upstream/src/arm64/st/stm32mp251.dtsi
@@ -7,6 +7,7 @@
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/reset/st,stm32mp25-rcc.h>
 #include <dt-bindings/regulator/st,stm32mp25-regulator.h>
+#include <dt-bindings/phy/phy.h>
 
 / {
 	#address-cells = <2>;
@@ -237,6 +238,21 @@
 			#access-controller-cells = <1>;
 			ranges;
 
+			i2s2: audio-controller@400b0000 {
+				compatible = "st,stm32mp25-i2s";
+				reg = <0x400b0000 0x400>;
+				#sound-dai-cells = <0>;
+				interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&rcc CK_BUS_SPI2>, <&rcc CK_KER_SPI2>;
+				clock-names = "pclk", "i2sclk";
+				resets = <&rcc SPI2_R>;
+				dmas = <&hpdma 51 0x43 0x12>,
+				       <&hpdma 52 0x43 0x21>;
+				dma-names = "rx", "tx";
+				access-controllers = <&rifsc 23>;
+				status = "disabled";
+			};
+
 			spi2: spi@400b0000 {
 				#address-cells = <1>;
 				#size-cells = <0>;
@@ -252,6 +268,21 @@
 				status = "disabled";
 			};
 
+			i2s3: audio-controller@400c0000 {
+				compatible = "st,stm32mp25-i2s";
+				reg = <0x400c0000 0x400>;
+				#sound-dai-cells = <0>;
+				interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&rcc CK_BUS_SPI3>, <&rcc CK_KER_SPI3>;
+				clock-names = "pclk", "i2sclk";
+				resets = <&rcc SPI3_R>;
+				dmas = <&hpdma 53 0x43 0x12>,
+				       <&hpdma 54 0x43 0x21>;
+				dma-names = "rx", "tx";
+				access-controllers = <&rifsc 24>;
+				status = "disabled";
+			};
+
 			spi3: spi@400c0000 {
 				#address-cells = <1>;
 				#size-cells = <0>;
@@ -267,6 +298,20 @@
 				status = "disabled";
 			};
 
+			spdifrx: audio-controller@400d0000 {
+				compatible = "st,stm32h7-spdifrx";
+				#sound-dai-cells = <0>;
+				reg = <0x400d0000 0x400>;
+				clocks = <&rcc CK_KER_SPDIFRX>;
+				clock-names = "kclk";
+				interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
+				dmas = <&hpdma 71 0x43 0x212>,
+				       <&hpdma 72 0x43 0x212>;
+				dma-names = "rx", "rx-ctrl";
+				access-controllers = <&rifsc 30>;
+				status = "disabled";
+			};
+
 			usart2: serial@400e0000 {
 				compatible = "st,stm32h7-uart";
 				reg = <0x400e0000 0x400>;
@@ -439,6 +484,21 @@
 				status = "disabled";
 			};
 
+			i2s1: audio-controller@40230000 {
+				compatible = "st,stm32mp25-i2s";
+				reg = <0x40230000 0x400>;
+				#sound-dai-cells = <0>;
+				interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&rcc CK_BUS_SPI1>, <&rcc CK_KER_SPI1>;
+				clock-names = "pclk", "i2sclk";
+				resets = <&rcc SPI1_R>;
+				dmas = <&hpdma 49 0x43 0x12>,
+				       <&hpdma 50 0x43 0x21>;
+				dma-names = "rx", "tx";
+				access-controllers = <&rifsc 22>;
+				status = "disabled";
+			};
+
 			spi1: spi@40230000 {
 				#address-cells = <1>;
 				#size-cells = <0>;
@@ -484,6 +544,108 @@
 				status = "disabled";
 			};
 
+			sai1: sai@40290000 {
+				compatible = "st,stm32mp25-sai";
+				reg = <0x40290000 0x4>, <0x4029a3f0 0x10>;
+				ranges = <0 0x40290000 0x400>;
+				#address-cells = <1>;
+				#size-cells = <1>;
+				clocks = <&rcc CK_BUS_SAI1>;
+				clock-names = "pclk";
+				interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
+				resets = <&rcc SAI1_R>;
+				access-controllers = <&rifsc 49>;
+				status = "disabled";
+
+				sai1a: audio-controller@40290004 {
+					compatible = "st,stm32-sai-sub-a";
+					reg = <0x4 0x20>;
+					#sound-dai-cells = <0>;
+					clocks = <&rcc CK_KER_SAI1>;
+					clock-names = "sai_ck";
+					dmas = <&hpdma 73 0x43 0x21>;
+					status = "disabled";
+				};
+
+				sai1b: audio-controller@40290024 {
+					compatible = "st,stm32-sai-sub-b";
+					reg = <0x24 0x20>;
+					#sound-dai-cells = <0>;
+					clocks = <&rcc CK_KER_SAI1>;
+					clock-names = "sai_ck";
+					dmas = <&hpdma 74 0x43 0x12>;
+					status = "disabled";
+				};
+			};
+
+			sai2: sai@402a0000 {
+				compatible = "st,stm32mp25-sai";
+				reg = <0x402a0000 0x4>, <0x402aa3f0 0x10>;
+				ranges = <0 0x402a0000 0x400>;
+				#address-cells = <1>;
+				#size-cells = <1>;
+				clocks = <&rcc CK_BUS_SAI2>;
+				clock-names = "pclk";
+				interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
+				resets = <&rcc SAI2_R>;
+				access-controllers = <&rifsc 50>;
+				status = "disabled";
+
+				sai2a: audio-controller@402a0004 {
+					compatible = "st,stm32-sai-sub-a";
+					reg = <0x4 0x20>;
+					#sound-dai-cells = <0>;
+					clocks = <&rcc CK_KER_SAI2>;
+					clock-names = "sai_ck";
+					dmas = <&hpdma 75 0x43 0x21>;
+					status = "disabled";
+				};
+
+				sai2b: audio-controller@402a0024 {
+					compatible = "st,stm32-sai-sub-b";
+					reg = <0x24 0x20>;
+					#sound-dai-cells = <0>;
+					clocks = <&rcc CK_KER_SAI2>;
+					clock-names = "sai_ck";
+					dmas = <&hpdma 76 0x43 0x12>;
+					status = "disabled";
+				};
+			};
+
+			sai3: sai@402b0000 {
+				compatible = "st,stm32mp25-sai";
+				reg = <0x402b0000 0x4>, <0x402ba3f0 0x10>;
+				ranges = <0 0x402b0000 0x400>;
+				#address-cells = <1>;
+				#size-cells = <1>;
+				clocks = <&rcc CK_BUS_SAI3>;
+				clock-names = "pclk";
+				interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
+				resets = <&rcc SAI3_R>;
+				access-controllers = <&rifsc 51>;
+				status = "disabled";
+
+				sai3a: audio-controller@402b0004 {
+					compatible = "st,stm32-sai-sub-a";
+					reg = <0x4 0x20>;
+					#sound-dai-cells = <0>;
+					clocks = <&rcc CK_KER_SAI3>;
+					clock-names = "sai_ck";
+					dmas = <&hpdma 77 0x43 0x21>;
+					status = "disabled";
+				};
+
+				sai3b: audio-controller@502b0024 {
+					compatible = "st,stm32-sai-sub-b";
+					reg = <0x24 0x20>;
+					#sound-dai-cells = <0>;
+					clocks = <&rcc CK_KER_SAI3>;
+					clock-names = "sai_ck";
+					dmas = <&hpdma 78 0x43 0x12>;
+					status = "disabled";
+				};
+			};
+
 			uart9: serial@402c0000 {
 				compatible = "st,stm32h7-uart";
 				reg = <0x402c0000 0x400>;
@@ -508,6 +670,40 @@
 				status = "disabled";
 			};
 
+			sai4: sai@40340000 {
+				compatible = "st,stm32mp25-sai";
+				reg = <0x40340000 0x4>, <0x4034a3f0 0x10>;
+				ranges = <0 0x40340000 0x400>;
+				#address-cells = <1>;
+				#size-cells = <1>;
+				clocks = <&rcc CK_BUS_SAI4>;
+				clock-names = "pclk";
+				interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
+				resets = <&rcc SAI4_R>;
+				access-controllers = <&rifsc 52>;
+				status = "disabled";
+
+				sai4a: audio-controller@40340004 {
+					compatible = "st,stm32-sai-sub-a";
+					reg = <0x4 0x20>;
+					#sound-dai-cells = <0>;
+					clocks = <&rcc CK_KER_SAI4>;
+					clock-names = "sai_ck";
+					dmas = <&hpdma 79 0x63 0x21>;
+					status = "disabled";
+				};
+
+				sai4b: audio-controller@40340024 {
+					compatible = "st,stm32-sai-sub-b";
+					reg = <0x24 0x20>;
+					#sound-dai-cells = <0>;
+					clocks = <&rcc CK_KER_SAI4>;
+					clock-names = "sai_ck";
+					dmas = <&hpdma 80 0x43 0x12>;
+					status = "disabled";
+				};
+			};
+
 			spi6: spi@40350000 {
 				#address-cells = <1>;
 				#size-cells = <0>;
@@ -603,6 +799,44 @@
 				status = "disabled";
 			};
 
+			csi: csi@48020000 {
+				compatible = "st,stm32mp25-csi";
+				reg = <0x48020000 0x2000>;
+				interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
+				resets = <&rcc CSI_R>;
+				clocks = <&rcc CK_KER_CSI>, <&rcc CK_KER_CSITXESC>,
+					 <&rcc CK_KER_CSIPHY>;
+				clock-names = "pclk", "txesc", "csi2phy";
+				access-controllers = <&rifsc 86>;
+				status = "disabled";
+			};
+
+			dcmipp: dcmipp@48030000 {
+				compatible = "st,stm32mp25-dcmipp";
+				reg = <0x48030000 0x1000>;
+				interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>;
+				resets = <&rcc DCMIPP_R>;
+				clocks = <&rcc CK_BUS_DCMIPP>, <&rcc CK_KER_CSI>;
+				clock-names = "kclk", "mclk";
+				access-controllers = <&rifsc 87>;
+				status = "disabled";
+			};
+
+			combophy: phy@480c0000 {
+				compatible = "st,stm32mp25-combophy";
+				reg = <0x480c0000 0x1000>;
+				#phy-cells = <1>;
+				clocks = <&rcc CK_BUS_USB3PCIEPHY>, <&rcc CK_KER_USB3PCIEPHY>;
+				clock-names = "apb", "ker";
+				resets = <&rcc USB3PCIEPHY_R>;
+				reset-names = "phy";
+				access-controllers = <&rifsc 67>;
+				power-domains = <&CLUSTER_PD>;
+				wakeup-source;
+				interrupts-extended = <&exti1 45 IRQ_TYPE_EDGE_FALLING>;
+				status = "disabled";
+			};
+
 			sdmmc1: mmc@48220000 {
 				compatible = "st,stm32mp25-sdmmc2", "arm,pl18x", "arm,primecell";
 				arm,primecell-periphid = <0x00353180>;
diff --git a/dts/upstream/src/arm64/st/stm32mp257f-ev1.dts b/dts/upstream/src/arm64/st/stm32mp257f-ev1.dts
index 6f393b08278..1b88485a62a 100644
--- a/dts/upstream/src/arm64/st/stm32mp257f-ev1.dts
+++ b/dts/upstream/src/arm64/st/stm32mp257f-ev1.dts
@@ -27,6 +27,44 @@
 		stdout-path = "serial0:115200n8";
 	};
 
+	clocks {
+		clk_ext_camera: clk-ext-camera {
+			#clock-cells = <0>;
+			compatible = "fixed-clock";
+			clock-frequency = <24000000>;
+		};
+
+		pad_clk: pad-clk {
+			#clock-cells = <0>;
+			compatible = "fixed-clock";
+			clock-frequency = <100000000>;
+		};
+	};
+
+	imx335_2v9: regulator-2v9 {
+		compatible = "regulator-fixed";
+		regulator-name = "imx335-avdd";
+		regulator-min-microvolt = <2900000>;
+		regulator-max-microvolt = <2900000>;
+		regulator-always-on;
+	};
+
+	imx335_1v8: regulator-1v8 {
+		compatible = "regulator-fixed";
+		regulator-name = "imx335-ovdd";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+		regulator-always-on;
+	};
+
+	imx335_1v2: regulator-1v2 {
+		compatible = "regulator-fixed";
+		regulator-name = "imx335-dvdd";
+		regulator-min-microvolt = <1200000>;
+		regulator-max-microvolt = <1200000>;
+		regulator-always-on;
+	};
+
 	memory@80000000 {
 		device_type = "memory";
 		reg = <0x0 0x80000000 0x1 0x0>;
@@ -50,6 +88,46 @@
 	status = "okay";
 };
 
+&combophy {
+	clocks = <&rcc CK_BUS_USB3PCIEPHY>, <&rcc CK_KER_USB3PCIEPHY>, <&pad_clk>;
+	clock-names = "apb", "ker", "pad";
+	status = "okay";
+};
+
+&csi {
+	vdd-supply =  <&scmi_vddcore>;
+	vdda18-supply = <&scmi_v1v8>;
+	status = "okay";
+	ports {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		port@0 {
+			reg = <0>;
+			csi_sink: endpoint {
+				remote-endpoint = <&imx335_ep>;
+				data-lanes = <1 2>;
+				bus-type = <4>;
+			};
+		};
+		port@1 {
+			reg = <1>;
+			csi_source: endpoint {
+				remote-endpoint = <&dcmipp_0>;
+			};
+		};
+	};
+};
+
+&dcmipp {
+	status = "okay";
+	port {
+		dcmipp_0: endpoint {
+			remote-endpoint = <&csi_source>;
+			bus-type = <4>;
+		};
+	};
+};
+
 &ethernet2 {
 	pinctrl-names = "default", "sleep";
 	pinctrl-0 = <&eth2_rgmii_pins_a>;
@@ -81,6 +159,25 @@
 	i2c-scl-falling-time-ns = <13>;
 	clock-frequency = <400000>;
 	status = "okay";
+
+	imx335: camera@1a {
+		compatible = "sony,imx335";
+		reg = <0x1a>;
+		clocks = <&clk_ext_camera>;
+		avdd-supply = <&imx335_2v9>;
+		ovdd-supply = <&imx335_1v8>;
+		dvdd-supply = <&imx335_1v2>;
+		reset-gpios = <&gpioi 7 (GPIO_ACTIVE_LOW | GPIO_PUSH_PULL)>;
+
+		port {
+			imx335_ep: endpoint {
+				remote-endpoint = <&csi_sink>;
+				clock-lanes = <0>;
+				data-lanes = <1 2>;
+				link-frequencies = /bits/ 64 <594000000>;
+			};
+		};
+	};
 };
 
 &i2c8 {
diff --git a/dts/upstream/src/arm64/ti/k3-am62-main.dtsi b/dts/upstream/src/arm64/ti/k3-am62-main.dtsi
index 7cd727d10a5..7d355aa73ea 100644
--- a/dts/upstream/src/arm64/ti/k3-am62-main.dtsi
+++ b/dts/upstream/src/arm64/ti/k3-am62-main.dtsi
@@ -23,7 +23,6 @@
 		interrupt-controller;
 		reg = <0x00 0x01800000 0x00 0x10000>,	/* GICD */
 		      <0x00 0x01880000 0x00 0xc0000>,	/* GICR */
-		      <0x00 0x01880000 0x00 0xc0000>,   /* GICR */
 		      <0x01 0x00000000 0x00 0x2000>,    /* GICC */
 		      <0x01 0x00010000 0x00 0x1000>,    /* GICH */
 		      <0x01 0x00020000 0x00 0x2000>;    /* GICV */
diff --git a/dts/upstream/src/arm64/ti/k3-am62-phycore-som.dtsi b/dts/upstream/src/arm64/ti/k3-am62-phycore-som.dtsi
index 5952874fe42..2ef4cbaec78 100644
--- a/dts/upstream/src/arm64/ti/k3-am62-phycore-som.dtsi
+++ b/dts/upstream/src/arm64/ti/k3-am62-phycore-som.dtsi
@@ -95,6 +95,16 @@
 		regulator-boot-on;
 	};
 
+	vddshv_3v3: regulator-vddshv-3v3 {
+		compatible = "regulator-fixed";
+		regulator-name = "VDDSHV0";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		vin-supply = <&vdd_3v3>;
+		regulator-always-on;
+		regulator-boot-on;
+	};
+
 	leds {
 		compatible = "gpio-leds";
 		pinctrl-names = "default";
@@ -313,6 +323,7 @@
 		compatible = "atmel,24c32";
 		pagesize = <32>;
 		reg = <0x50>;
+		vcc-supply = <&vddshv_3v3>;
 	};
 
 	i2c_som_rtc: rtc@52 {
diff --git a/dts/upstream/src/arm64/ti/k3-am625-beagleplay.dts b/dts/upstream/src/arm64/ti/k3-am625-beagleplay.dts
index ee96f4f6deb..75c80290b12 100644
--- a/dts/upstream/src/arm64/ti/k3-am625-beagleplay.dts
+++ b/dts/upstream/src/arm64/ti/k3-am625-beagleplay.dts
@@ -610,7 +610,7 @@
 		reg = <1>;
 		reset-gpios = <&main_gpio1 5 GPIO_ACTIVE_LOW>;
 		reset-assert-us = <25>;
-		reset-deassert-us = <60000>; /* T2 */
+		reset-deassert-us = <35>;
 	};
 };
 
diff --git a/dts/upstream/src/arm64/ti/k3-am625-sk.dts b/dts/upstream/src/arm64/ti/k3-am625-sk.dts
index ae81ebb39d0..2fbfa371934 100644
--- a/dts/upstream/src/arm64/ti/k3-am625-sk.dts
+++ b/dts/upstream/src/arm64/ti/k3-am625-sk.dts
@@ -219,13 +219,6 @@
 	};
 };
 
-&mailbox0_cluster0 {
-	mbox_m4_0: mbox-m4-0 {
-		ti,mbox-rx = <0 0 0>;
-		ti,mbox-tx = <1 0 0>;
-	};
-};
-
 &fss {
 	bootph-all;
 };
diff --git a/dts/upstream/src/arm64/ti/k3-am62a-main.dtsi b/dts/upstream/src/arm64/ti/k3-am62a-main.dtsi
index a93e2cd7b8c..a1daba7b1fa 100644
--- a/dts/upstream/src/arm64/ti/k3-am62a-main.dtsi
+++ b/dts/upstream/src/arm64/ti/k3-am62a-main.dtsi
@@ -18,7 +18,6 @@
 		compatible = "arm,gic-v3";
 		reg = <0x00 0x01800000 0x00 0x10000>,	/* GICD */
 		      <0x00 0x01880000 0x00 0xc0000>,	/* GICR */
-		      <0x00 0x01880000 0x00 0xc0000>,   /* GICR */
 		      <0x01 0x00000000 0x00 0x2000>,    /* GICC */
 		      <0x01 0x00010000 0x00 0x1000>,    /* GICH */
 		      <0x01 0x00020000 0x00 0x2000>;    /* GICV */
diff --git a/dts/upstream/src/arm64/ti/k3-am62a-wakeup.dtsi b/dts/upstream/src/arm64/ti/k3-am62a-wakeup.dtsi
index 0b1dd5390cd..b2c8f535174 100644
--- a/dts/upstream/src/arm64/ti/k3-am62a-wakeup.dtsi
+++ b/dts/upstream/src/arm64/ti/k3-am62a-wakeup.dtsi
@@ -2,9 +2,11 @@
 /*
  * Device Tree Source for AM62A SoC Family Wakeup Domain peripherals
  *
- * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2022-2025 Texas Instruments Incorporated - https://www.ti.com/
  */
 
+#include <dt-bindings/bus/ti-sysc.h>
+
 &cbass_wakeup {
 	wkup_conf: bus@43000000 {
 		compatible = "simple-bus";
@@ -38,14 +40,34 @@
 		};
 	};
 
-	wkup_uart0: serial@2b300000 {
-		compatible = "ti,am64-uart", "ti,am654-uart";
-		reg = <0x00 0x2b300000 0x00 0x100>;
-		interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
+	target-module@2b300050 {
+		compatible = "ti,sysc-omap2", "ti,sysc";
+		reg = <0 0x2b300050 0 0x4>,
+		      <0 0x2b300054 0 0x4>,
+		      <0 0x2b300058 0 0x4>;
+		reg-names = "rev", "sysc", "syss";
+		ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
+				 SYSC_OMAP2_SOFTRESET |
+				 SYSC_OMAP2_AUTOIDLE)>;
+		ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+				<SYSC_IDLE_NO>,
+				<SYSC_IDLE_SMART>,
+				<SYSC_IDLE_SMART_WKUP>;
+		ti,syss-mask = <1>;
+		ti,no-reset-on-init;
 		power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>;
 		clocks = <&k3_clks 114 0>;
-		clock-names = "fclk";
-		status = "disabled";
+		clock-names = "fck";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0 0 0x2b300000 0x100000>;
+
+		wkup_uart0: serial@0 {
+			compatible = "ti,am64-uart", "ti,am654-uart";
+			reg = <0 0x100>;
+			interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
+			status = "disabled";
+	       };
 	};
 
 	wkup_i2c0: i2c@2b200000 {
diff --git a/dts/upstream/src/arm64/ti/k3-am62p-j722s-common-main.dtsi b/dts/upstream/src/arm64/ti/k3-am62p-j722s-common-main.dtsi
index 41e1c24b114..6e3beb5c2e0 100644
--- a/dts/upstream/src/arm64/ti/k3-am62p-j722s-common-main.dtsi
+++ b/dts/upstream/src/arm64/ti/k3-am62p-j722s-common-main.dtsi
@@ -651,6 +651,7 @@
 			interrupt-names = "host", "peripheral";
 			maximum-speed = "high-speed";
 			dr_mode = "otg";
+			bootph-all;
 			snps,usb2-gadget-lpm-disable;
 			snps,usb2-lpm-disable;
 		};
@@ -768,6 +769,7 @@
 		#mbox-cells = <1>;
 		ti,mbox-num-users = <4>;
 		ti,mbox-num-fifos = <16>;
+		status = "disabled";
 	};
 
 	mailbox0_cluster1: mailbox@29010000 {
@@ -777,6 +779,7 @@
 		#mbox-cells = <1>;
 		ti,mbox-num-users = <4>;
 		ti,mbox-num-fifos = <16>;
+		status = "disabled";
 	};
 
 	mailbox0_cluster2: mailbox@29020000 {
@@ -786,6 +789,7 @@
 		#mbox-cells = <1>;
 		ti,mbox-num-users = <4>;
 		ti,mbox-num-fifos = <16>;
+		status = "disabled";
 	};
 
 	mailbox0_cluster3: mailbox@29030000 {
@@ -795,6 +799,7 @@
 		#mbox-cells = <1>;
 		ti,mbox-num-users = <4>;
 		ti,mbox-num-fifos = <16>;
+		status = "disabled";
 	};
 
 	ecap0: pwm@23100000 {
diff --git a/dts/upstream/src/arm64/ti/k3-am62p5-sk.dts b/dts/upstream/src/arm64/ti/k3-am62p5-sk.dts
index 7f3dc39e12b..ad71d2f27f5 100644
--- a/dts/upstream/src/arm64/ti/k3-am62p5-sk.dts
+++ b/dts/upstream/src/arm64/ti/k3-am62p5-sk.dts
@@ -621,6 +621,8 @@
 };
 
 &mailbox0_cluster0 {
+	status = "okay";
+
 	mbox_r5_0: mbox-r5-0 {
 		ti,mbox-rx = <0 0 0>;
 		ti,mbox-tx = <1 0 0>;
@@ -628,6 +630,8 @@
 };
 
 &mailbox0_cluster1 {
+	status = "okay";
+
 	mbox_mcu_r5_0: mbox-mcu-r5-0 {
 		ti,mbox-rx = <0 0 0>;
 		ti,mbox-tx = <1 0 0>;
diff --git a/dts/upstream/src/arm64/ti/k3-am62x-phyboard-lyra.dtsi b/dts/upstream/src/arm64/ti/k3-am62x-phyboard-lyra.dtsi
index d364c247833..922cad14c9f 100644
--- a/dts/upstream/src/arm64/ti/k3-am62x-phyboard-lyra.dtsi
+++ b/dts/upstream/src/arm64/ti/k3-am62x-phyboard-lyra.dtsi
@@ -112,6 +112,25 @@
 		regulator-boot-on;
 	};
 
+	vcc_3v3_hdmi: regulator-vcc-3v3-hdmi {
+		compatible = "regulator-fixed";
+		regulator-name = "VCC_3V3_HDMI";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		vin-supply = <&vcc_3v3_sw>;
+		regulator-always-on;
+		regulator-boot-on;
+	};
+
+	vcc_1v2_hdmi: regulator-vcc-1v2-hdmi {
+		compatible = "regulator-fixed";
+		regulator-name = "HDMI_CVCC";
+		regulator-min-microvolt = <1200000>;
+		regulator-max-microvolt = <1200000>;
+		regulator-always-on;
+		regulator-boot-on;
+	};
+
 	vcc_3v3_mmc: regulator-vcc-3v3-mmc {
 		compatible = "regulator-fixed";
 		regulator-name = "VCC_3V3_MMC";
@@ -367,6 +386,9 @@
 		pinctrl-names = "default";
 		pinctrl-0 = <&hdmi_int_pins_default>;
 
+		iovcc-supply = <&vcc_3v3_hdmi>;
+		cvcc12-supply = <&vcc_1v2_hdmi>;
+
 		ports {
 			#address-cells = <1>;
 			#size-cells = <0>;
@@ -376,6 +398,7 @@
 
 				sii9022_in: endpoint {
 					remote-endpoint = <&dpi1_out>;
+					bus-width = <16>;
 				};
 			};
 
@@ -393,6 +416,7 @@
 		compatible = "atmel,24c02";
 		pagesize = <16>;
 		reg = <0x51>;
+		vcc-supply = <&vcc_3v3_mmc>;
 	};
 };
 
diff --git a/dts/upstream/src/arm64/ti/k3-am62x-sk-common.dtsi b/dts/upstream/src/arm64/ti/k3-am62x-sk-common.dtsi
index 6957b3e44c8..2f129e8cd5b 100644
--- a/dts/upstream/src/arm64/ti/k3-am62x-sk-common.dtsi
+++ b/dts/upstream/src/arm64/ti/k3-am62x-sk-common.dtsi
@@ -256,7 +256,7 @@
 
 	main_usb1_pins_default: main-usb1-default-pins {
 		pinctrl-single,pins = <
-			AM62X_IOPAD(0x0258, PIN_OUTPUT, 0) /* (F18/E16) USB1_DRVVBUS */
+			AM62X_IOPAD(0x0258, PIN_OUTPUT | PIN_DS_PULLUD_ENABLE | PIN_DS_PULL_UP, 0) /* (F18/E16) USB1_DRVVBUS */
 		>;
 	};
 
@@ -315,6 +315,10 @@
 	};
 };
 
+&cpsw_mac_syscon {
+	bootph-all;
+};
+
 &wkup_uart0 {
 	/* WKUP UART0 is used by DM firmware */
 	bootph-pre-ram;
diff --git a/dts/upstream/src/arm64/ti/k3-am64-main.dtsi b/dts/upstream/src/arm64/ti/k3-am64-main.dtsi
index c66289a4362..324eb44c258 100644
--- a/dts/upstream/src/arm64/ti/k3-am64-main.dtsi
+++ b/dts/upstream/src/arm64/ti/k3-am64-main.dtsi
@@ -1227,6 +1227,15 @@
 		#address-cells = <1>;
 		#size-cells = <1>;
 		ranges = <0x0 0x00 0x30000000 0x80000>;
+		clocks = <&k3_clks 81 0>,  /* icssg0_core_clk */
+			 <&k3_clks 81 3>,  /* icssg0_iep_clk */
+			 <&k3_clks 81 16>, /* icssg0_rgmii_mhz_250_clk */
+			 <&k3_clks 81 17>, /* icssg0_rgmii_mhz_50_clk */
+			 <&k3_clks 81 18>, /* icssg0_rgmii_mhz_5_clk */
+			 <&k3_clks 81 19>, /* icssg0_uart_clk */
+			 <&k3_clks 81 20>; /* icssg0_iclk */
+		assigned-clocks = <&k3_clks 81 0>;
+		assigned-clock-parents = <&k3_clks 81 2>;
 
 		icssg0_mem: memories@0 {
 			reg = <0x0 0x2000>,
@@ -1252,7 +1261,7 @@
 					clocks = <&k3_clks 81 0>,  /* icssg0_core_clk */
 						 <&k3_clks 81 20>; /* icssg0_iclk */
 					assigned-clocks = <&icssg0_coreclk_mux>;
-					assigned-clock-parents = <&k3_clks 81 20>;
+					assigned-clock-parents = <&k3_clks 81 0>;
 				};
 
 				icssg0_iepclk_mux: iepclk-mux@30 {
@@ -1397,6 +1406,15 @@
 		#address-cells = <1>;
 		#size-cells = <1>;
 		ranges = <0x0 0x00 0x30080000 0x80000>;
+		clocks = <&k3_clks 82 0>,  /* icssg1_core_clk */
+			 <&k3_clks 82 3>,  /* icssg1_iep_clk */
+			 <&k3_clks 82 16>, /* icssg1_rgmii_mhz_250_clk */
+			 <&k3_clks 82 17>, /* icssg1_rgmii_mhz_50_clk */
+			 <&k3_clks 82 18>, /* icssg1_rgmii_mhz_5_clk */
+			 <&k3_clks 82 19>, /* icssg1_uart_clk */
+			 <&k3_clks 82 20>; /* icssg1_iclk */
+		assigned-clocks = <&k3_clks 82 0>;
+		assigned-clock-parents = <&k3_clks 82 2>;
 
 		icssg1_mem: memories@0 {
 			reg = <0x0 0x2000>,
@@ -1422,7 +1440,7 @@
 					clocks = <&k3_clks 82 0>,   /* icssg1_core_clk */
 						 <&k3_clks 82 20>;  /* icssg1_iclk */
 					assigned-clocks = <&icssg1_coreclk_mux>;
-					assigned-clock-parents = <&k3_clks 82 20>;
+					assigned-clock-parents = <&k3_clks 82 0>;
 				};
 
 				icssg1_iepclk_mux: iepclk-mux@30 {
diff --git a/dts/upstream/src/arm64/ti/k3-am642-hummingboard-t-pcie.dtso b/dts/upstream/src/arm64/ti/k3-am642-hummingboard-t-pcie.dts
index bd9a5caf20d..023b2a6aaa5 100644
--- a/dts/upstream/src/arm64/ti/k3-am642-hummingboard-t-pcie.dtso
+++ b/dts/upstream/src/arm64/ti/k3-am642-hummingboard-t-pcie.dts
@@ -2,17 +2,19 @@
 /*
  * Copyright (C) 2023 Josua Mayer <josua@solid-run.com>
  *
- * Overlay for SolidRun AM642 HummingBoard-T to enable PCI-E.
+ * DTS for SolidRun AM642 HummingBoard-T,
+ * running on Cortex A53, with PCI-E.
+ *
  */
 
-/dts-v1/;
-/plugin/;
-
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/phy/phy.h>
+#include "k3-am642-hummingboard-t.dts"
 
 #include "k3-serdes.h"
 
+/ {
+	model = "SolidRun AM642 HummingBoard-T with PCI-E";
+};
+
 &pcie0_rc {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pcie0_default_pins>;
diff --git a/dts/upstream/src/arm64/ti/k3-am642-hummingboard-t-usb3.dtso b/dts/upstream/src/arm64/ti/k3-am642-hummingboard-t-usb3.dts
index ffcc3bd3c7b..ee9bd618f37 100644
--- a/dts/upstream/src/arm64/ti/k3-am642-hummingboard-t-usb3.dtso
+++ b/dts/upstream/src/arm64/ti/k3-am642-hummingboard-t-usb3.dts
@@ -2,16 +2,19 @@
 /*
  * Copyright (C) 2023 Josua Mayer <josua@solid-run.com>
  *
- * Overlay for SolidRun AM642 HummingBoard-T to enable USB-3.1.
+ * DTS for SolidRun AM642 HummingBoard-T,
+ * running on Cortex A53, with USB-3.1 Gen 1.
+ *
  */
 
-/dts-v1/;
-/plugin/;
-
-#include <dt-bindings/phy/phy.h>
+#include "k3-am642-hummingboard-t.dts"
 
 #include "k3-serdes.h"
 
+/ {
+	model = "SolidRun AM642 HummingBoard-T with USB-3.1 Gen 1";
+};
+
 &serdes0 {
 	#address-cells = <1>;
 	#size-cells = <0>;
diff --git a/dts/upstream/src/arm64/ti/k3-am642-tqma64xxl-mbax4xxl.dts b/dts/upstream/src/arm64/ti/k3-am642-tqma64xxl-mbax4xxl.dts
index e06a3b178b3..8f64d6272b1 100644
--- a/dts/upstream/src/arm64/ti/k3-am642-tqma64xxl-mbax4xxl.dts
+++ b/dts/upstream/src/arm64/ti/k3-am642-tqma64xxl-mbax4xxl.dts
@@ -201,8 +201,6 @@
 		reset-gpios = <&main_gpio0 44 GPIO_ACTIVE_LOW>;
 		reset-assert-us = <1000>;
 		reset-deassert-us = <1000>;
-		ti,rx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
-		ti,tx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
 		ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
 		ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
 	};
@@ -230,8 +228,6 @@
 		reset-gpios = <&main_gpio1 47 GPIO_ACTIVE_LOW>;
 		reset-assert-us = <1000>;
 		reset-deassert-us = <1000>;
-		ti,rx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
-		ti,tx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
 		ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
 		ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
 	};
@@ -242,8 +238,6 @@
 		reset-gpios = <&main_gpio1 51 GPIO_ACTIVE_LOW>;
 		reset-assert-us = <1000>;
 		reset-deassert-us = <1000>;
-		ti,rx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
-		ti,tx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
 		ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
 		ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
 	};
diff --git a/dts/upstream/src/arm64/ti/k3-am67a-beagley-ai.dts b/dts/upstream/src/arm64/ti/k3-am67a-beagley-ai.dts
index 44dfbdf8927..9be6bba28c2 100644
--- a/dts/upstream/src/arm64/ti/k3-am67a-beagley-ai.dts
+++ b/dts/upstream/src/arm64/ti/k3-am67a-beagley-ai.dts
@@ -50,11 +50,71 @@
 			no-map;
 		};
 
+		wkup_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 {
+			compatible = "shared-dma-pool";
+			reg = <0x00 0xa0000000 0x00 0x100000>;
+			no-map;
+		};
+
 		wkup_r5fss0_core0_memory_region: r5f-memory@a0100000 {
 			compatible = "shared-dma-pool";
 			reg = <0x00 0xa0100000 0x00 0xf00000>;
 			no-map;
 		};
+
+		mcu_r5fss0_core0_dma_memory_region: mcu-r5fss-dma-memory-region@a1000000 {
+			compatible = "shared-dma-pool";
+			reg = <0x00 0xa1000000 0x00 0x100000>;
+			no-map;
+		};
+
+		mcu_r5fss0_core0_memory_region: mcu-r5fss-memory-region@a1100000 {
+			compatible = "shared-dma-pool";
+			reg = <0x00 0xa1100000 0x00 0xf00000>;
+			no-map;
+		};
+
+		main_r5fss0_core0_dma_memory_region: main-r5fss-dma-memory-region@a2000000 {
+			compatible = "shared-dma-pool";
+			reg = <0x00 0xa2000000 0x00 0x100000>;
+			no-map;
+		};
+
+		main_r5fss0_core0_memory_region: main-r5fss-memory-region@a2100000 {
+			compatible = "shared-dma-pool";
+			reg = <0x00 0xa2100000 0x00 0xf00000>;
+			no-map;
+		};
+
+		c7x_0_dma_memory_region: c7x-dma-memory@a3000000 {
+			compatible = "shared-dma-pool";
+			reg = <0x00 0xa3000000 0x00 0x100000>;
+			no-map;
+		};
+
+		c7x_0_memory_region: c7x-memory@a3100000 {
+			compatible = "shared-dma-pool";
+			reg = <0x00 0xa3100000 0x00 0xf00000>;
+			no-map;
+		};
+
+		c7x_1_dma_memory_region: c7x-dma-memory@a4000000 {
+			compatible = "shared-dma-pool";
+			reg = <0x00 0xa4000000 0x00 0x100000>;
+			no-map;
+		};
+
+		c7x_1_memory_region: c7x-memory@a4100000 {
+			compatible = "shared-dma-pool";
+			reg = <0x00 0xa4100000 0x00 0xf00000>;
+			no-map;
+		};
+
+		rtos_ipc_memory_region: ipc-memories@a5000000 {
+			reg = <0x00 0xa5000000 0x00 0x1c00000>;
+			alignment = <0x1000>;
+			no-map;
+		};
 	};
 
 	vsys_5v0: regulator-1 {
@@ -391,3 +451,101 @@
 	ti,fails-without-test-cd;
 	status = "okay";
 };
+
+&mailbox0_cluster0 {
+	status = "okay";
+
+	mbox_wkup_r5_0: mbox-wkup-r5-0 {
+		ti,mbox-rx = <0 0 0>;
+		ti,mbox-tx = <1 0 0>;
+	};
+};
+
+&mailbox0_cluster1 {
+	status = "okay";
+
+	mbox_mcu_r5_0: mbox-mcu-r5-0 {
+		ti,mbox-rx = <0 0 0>;
+		ti,mbox-tx = <1 0 0>;
+	};
+};
+
+&mailbox0_cluster2 {
+	status = "okay";
+
+	mbox_c7x_0: mbox-c7x-0 {
+		ti,mbox-rx = <0 0 0>;
+		ti,mbox-tx = <1 0 0>;
+	};
+};
+
+&mailbox0_cluster3 {
+	status = "okay";
+
+	mbox_main_r5_0: mbox-main-r5-0 {
+		ti,mbox-rx = <0 0 0>;
+		ti,mbox-tx = <1 0 0>;
+	};
+
+	mbox_c7x_1: mbox-c7x-1 {
+		ti,mbox-rx = <2 0 0>;
+		ti,mbox-tx = <3 0 0>;
+	};
+};
+
+/* Timers are used by Remoteproc firmware */
+&main_timer0 {
+	status = "reserved";
+};
+
+&main_timer1 {
+	status = "reserved";
+};
+
+&main_timer2 {
+	status = "reserved";
+};
+
+&wkup_r5fss0 {
+	status = "okay";
+};
+
+&wkup_r5fss0_core0 {
+	mboxes = <&mailbox0_cluster0 &mbox_wkup_r5_0>;
+	memory-region = <&wkup_r5fss0_core0_dma_memory_region>,
+			<&wkup_r5fss0_core0_memory_region>;
+};
+
+&mcu_r5fss0 {
+	status = "okay";
+};
+
+&mcu_r5fss0_core0 {
+	mboxes = <&mailbox0_cluster1 &mbox_mcu_r5_0>;
+	memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
+			<&mcu_r5fss0_core0_memory_region>;
+};
+
+&main_r5fss0 {
+	status = "okay";
+};
+
+&main_r5fss0_core0 {
+	mboxes = <&mailbox0_cluster3 &mbox_main_r5_0>;
+	memory-region = <&main_r5fss0_core0_dma_memory_region>,
+			<&main_r5fss0_core0_memory_region>;
+};
+
+&c7x_0 {
+	mboxes = <&mailbox0_cluster2 &mbox_c7x_0>;
+	memory-region = <&c7x_0_dma_memory_region>,
+			<&c7x_0_memory_region>;
+	status = "okay";
+};
+
+&c7x_1 {
+	mboxes = <&mailbox0_cluster3 &mbox_c7x_1>;
+	memory-region = <&c7x_1_dma_memory_region>,
+			<&c7x_1_memory_region>;
+	status = "okay";
+};
diff --git a/dts/upstream/src/arm64/ti/k3-am68-sk-base-board-pcie1-ep.dtso b/dts/upstream/src/arm64/ti/k3-am68-sk-base-board-pcie1-ep.dtso
new file mode 100644
index 00000000000..455736e378c
--- /dev/null
+++ b/dts/upstream/src/arm64/ti/k3-am68-sk-base-board-pcie1-ep.dtso
@@ -0,0 +1,53 @@
+// SPDX-License-Identifier: GPL-2.0-only OR MIT
+/**
+ * DT Overlay for enabling PCIE1 instance in Endpoint Configuration with the
+ * AM68-SK board.
+ *
+ * AM68-SK Board Product Link: https://www.ti.com/tool/SK-AM68
+ *
+ * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/soc/ti,sci_pm_domain.h>
+
+#include "k3-pinctrl.h"
+
+/*
+ * Since Root Complex and Endpoint modes are mutually exclusive
+ * disable Root Complex mode.
+ */
+&pcie1_rc {
+	status = "disabled";
+};
+
+&cbass_main {
+	#address-cells = <2>;
+	#size-cells = <2>;
+	interrupt-parent = <&gic500>;
+
+	pcie1_ep: pcie-ep@2910000 {
+		compatible = "ti,j7200-pcie-ep", "ti,j721e-pcie-ep";
+		reg = <0x00 0x02910000 0x00 0x1000>,
+		      <0x00 0x02917000 0x00 0x400>,
+		      <0x00 0x0d800000 0x00 0x00800000>,
+		      <0x00 0x18000000 0x00 0x08000000>;
+		reg-names = "intd_cfg", "user_cfg", "reg", "mem";
+		interrupt-names = "link_state";
+		interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>;
+		max-link-speed = <3>;
+		num-lanes = <2>;
+		power-domains = <&k3_pds 276 TI_SCI_PD_EXCLUSIVE>;
+		clocks = <&k3_clks 276 41>;
+		clock-names = "fck";
+		max-functions = /bits/ 8 <6>;
+		max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>;
+		dma-coherent;
+		phys = <&serdes0_pcie_link>;
+		phy-names = "pcie-phy";
+		ti,syscon-pcie-ctrl = <&scm_conf 0x074>;
+	};
+};
diff --git a/dts/upstream/src/arm64/ti/k3-am69-sk-pcie0-ep.dtso b/dts/upstream/src/arm64/ti/k3-am69-sk-pcie0-ep.dtso
new file mode 100644
index 00000000000..9a5bcf282a9
--- /dev/null
+++ b/dts/upstream/src/arm64/ti/k3-am69-sk-pcie0-ep.dtso
@@ -0,0 +1,53 @@
+// SPDX-License-Identifier: GPL-2.0-only OR MIT
+/**
+ * DT Overlay for enabling PCIE0 instances of PCIe in Endpoint Configuration
+ * on AM69-SK.
+ *
+ * AM69-SK Product Link: https://www.ti.com/tool/SK-AM69
+ *
+ * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/soc/ti,sci_pm_domain.h>
+
+#include "k3-pinctrl.h"
+
+/*
+ * Since Root Complex and Endpoint modes are mutually exclusive
+ * disable Root Complex mode.
+ */
+&pcie0_rc {
+	status = "disabled";
+};
+
+&cbass_main {
+	#address-cells = <2>;
+	#size-cells = <2>;
+	interrupt-parent = <&gic500>;
+
+	pcie0_ep: pcie-ep@2900000 {
+		compatible = "ti,j784s4-pcie-ep";
+		reg = <0x00 0x02900000 0x00 0x1000>,
+		      <0x00 0x02907000 0x00 0x400>,
+		      <0x00 0x0d000000 0x00 0x00800000>,
+		      <0x00 0x10000000 0x00 0x08000000>;
+		reg-names = "intd_cfg", "user_cfg", "reg", "mem";
+		interrupt-names = "link_state";
+		interrupts = <GIC_SPI 318 IRQ_TYPE_EDGE_RISING>;
+		max-link-speed = <3>;
+		num-lanes = <4>;
+		power-domains = <&k3_pds 332 TI_SCI_PD_EXCLUSIVE>;
+		clocks = <&k3_clks 332 0>;
+		clock-names = "fck";
+		max-functions = /bits/ 8 <6>;
+		max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>;
+		dma-coherent;
+		phys = <&serdes1_pcie_link>;
+		phy-names = "pcie-phy";
+		ti,syscon-pcie-ctrl = <&pcie0_ctrl 0x0>;
+	};
+};
diff --git a/dts/upstream/src/arm64/ti/k3-am69-sk.dts b/dts/upstream/src/arm64/ti/k3-am69-sk.dts
index 1e36965a140..b85227052f9 100644
--- a/dts/upstream/src/arm64/ti/k3-am69-sk.dts
+++ b/dts/upstream/src/arm64/ti/k3-am69-sk.dts
@@ -484,6 +484,12 @@
 		>;
 	};
 
+	main_usbss0_pins_default: main-usbss0-default-pins {
+		pinctrl-single,pins = <
+			J784S4_IOPAD(0x0ec, PIN_OUTPUT, 6) /* (AN37) TIMER_IO1.USB0_DRVVBUS */
+		>;
+	};
+
 };
 
 &wkup_pmx0 {
@@ -755,6 +761,7 @@
 				regulator-max-microvolt = <1100000>;
 				regulator-boot-on;
 				regulator-always-on;
+				bootph-all;
 			};
 
 			bucka3: buck3 {
@@ -763,6 +770,7 @@
 				regulator-max-microvolt = <850000>;
 				regulator-boot-on;
 				regulator-always-on;
+				bootph-all;
 			};
 
 			bucka4: buck4 {
@@ -771,6 +779,7 @@
 				regulator-max-microvolt = <1800000>;
 				regulator-boot-on;
 				regulator-always-on;
+				bootph-all;
 			};
 
 			bucka5: buck5 {
@@ -779,6 +788,7 @@
 				regulator-max-microvolt = <850000>;
 				regulator-boot-on;
 				regulator-always-on;
+				bootph-all;
 			};
 
 			ldoa1: ldo1 {
@@ -787,6 +797,7 @@
 				regulator-max-microvolt = <1800000>;
 				regulator-boot-on;
 				regulator-always-on;
+				bootph-all;
 			};
 
 			ldoa2: ldo2 {
@@ -795,6 +806,7 @@
 				regulator-max-microvolt = <3300000>;
 				regulator-boot-on;
 				regulator-always-on;
+				bootph-all;
 			};
 
 			ldoa3: ldo3 {
@@ -803,6 +815,7 @@
 				regulator-max-microvolt = <800000>;
 				regulator-boot-on;
 				regulator-always-on;
+				bootph-all;
 			};
 
 			ldoa4: ldo4 {
@@ -811,6 +824,7 @@
 				regulator-max-microvolt = <1800000>;
 				regulator-boot-on;
 				regulator-always-on;
+				bootph-all;
 			};
 		};
 	};
@@ -1299,6 +1313,14 @@
 		cdns,phy-type = <PHY_TYPE_PCIE>;
 		resets = <&serdes_wiz0 1>, <&serdes_wiz0 2>, <&serdes_wiz0 3>;
 	};
+
+	serdes0_usb_link: phy@3 {
+		reg = <3>;
+		cdns,num-lanes = <1>;
+		#phy-cells = <0>;
+		cdns,phy-type = <PHY_TYPE_USB3>;
+		resets = <&serdes_wiz0 4>;
+	};
 };
 
 &serdes_wiz1 {
@@ -1339,3 +1361,22 @@
 	phy-names = "pcie-phy";
 	num-lanes = <1>;
 };
+
+&usb_serdes_mux {
+	idle-states = <0>; /* USB0 to SERDES0 */
+};
+
+&usbss0 {
+	status = "okay";
+	pinctrl-0 = <&main_usbss0_pins_default>;
+	pinctrl-names = "default";
+	ti,vbus-divider;
+};
+
+&usb0 {
+	status = "okay";
+	dr_mode = "otg";
+	maximum-speed = "super-speed";
+	phys = <&serdes0_usb_link>;
+	phy-names = "cdns3,usb3-phy";
+};
diff --git a/dts/upstream/src/arm64/ti/k3-j7200-common-proc-board.dts b/dts/upstream/src/arm64/ti/k3-j7200-common-proc-board.dts
index db43e7e10b7..f684ce6ad9a 100644
--- a/dts/upstream/src/arm64/ti/k3-j7200-common-proc-board.dts
+++ b/dts/upstream/src/arm64/ti/k3-j7200-common-proc-board.dts
@@ -409,6 +409,10 @@
 		      <J7200_SERDES0_LANE2_QSGMII_LANE1>, <J7200_SERDES0_LANE3_IP4_UNUSED>;
 };
 
+&mcu_spi1 {
+	mux-controls = <&spi1_linkdis 0>;
+};
+
 &usb_serdes_mux {
 	idle-states = <1>; /* USB0 to SERDES lane 3 */
 	bootph-all;
diff --git a/dts/upstream/src/arm64/ti/k3-j7200-mcu-wakeup.dtsi b/dts/upstream/src/arm64/ti/k3-j7200-mcu-wakeup.dtsi
index 6a845386587..56ab144fea0 100644
--- a/dts/upstream/src/arm64/ti/k3-j7200-mcu-wakeup.dtsi
+++ b/dts/upstream/src/arm64/ti/k3-j7200-mcu-wakeup.dtsi
@@ -184,6 +184,13 @@
 			reg = <0x4040 0x4>;
 			#phy-cells = <1>;
 		};
+
+		spi1_linkdis: mux-controller@4060 {
+			compatible = "reg-mux";
+			reg = <0x4060 0x4>;
+			#mux-control-cells = <1>;
+			mux-reg-masks = <0x0 0x1>;
+		};
 	};
 
 	wkup_conf: bus@43000000 {
diff --git a/dts/upstream/src/arm64/ti/k3-j721e-evm-pcie1-ep.dtso b/dts/upstream/src/arm64/ti/k3-j721e-evm-pcie1-ep.dtso
new file mode 100644
index 00000000000..a8cccdcf3e3
--- /dev/null
+++ b/dts/upstream/src/arm64/ti/k3-j721e-evm-pcie1-ep.dtso
@@ -0,0 +1,53 @@
+// SPDX-License-Identifier: GPL-2.0-only OR MIT
+/**
+ * DT Overlay for enabling PCIE1 instance in Endpoint Configuration with the
+ * J7 common processor board.
+ *
+ * J7 Common Processor Board Product Link: https://www.ti.com/tool/J721EXCPXEVM
+ *
+ * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/soc/ti,sci_pm_domain.h>
+
+#include "k3-pinctrl.h"
+
+/*
+ * Since Root Complex and Endpoint modes are mutually exclusive
+ * disable Root Complex mode.
+ */
+&pcie1_rc {
+	status = "disabled";
+};
+
+&cbass_main {
+	#address-cells = <2>;
+	#size-cells = <2>;
+	interrupt-parent = <&gic500>;
+
+	pcie1_ep: pcie-ep@2910000 {
+		compatible = "ti,j721e-pcie-ep";
+		reg = <0x00 0x02910000 0x00 0x1000>,
+		      <0x00 0x02917000 0x00 0x400>,
+		      <0x00 0x0d800000 0x00 0x00800000>,
+		      <0x00 0x18000000 0x00 0x08000000>;
+		reg-names = "intd_cfg", "user_cfg", "reg", "mem";
+		interrupt-names = "link_state";
+		interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>;
+		max-link-speed = <3>;
+		num-lanes = <2>;
+		power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>;
+		clocks = <&k3_clks 240 1>;
+		clock-names = "fck";
+		max-functions = /bits/ 8 <6>;
+		max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>;
+		dma-coherent;
+		phys = <&serdes1_pcie_link>;
+		phy-names = "pcie-phy";
+		ti,syscon-pcie-ctrl = <&scm_conf 0x4074>;
+	};
+};
diff --git a/dts/upstream/src/arm64/ti/k3-j722s-evm.dts b/dts/upstream/src/arm64/ti/k3-j722s-evm.dts
index a00f4a7d20d..d184e9c1a0a 100644
--- a/dts/upstream/src/arm64/ti/k3-j722s-evm.dts
+++ b/dts/upstream/src/arm64/ti/k3-j722s-evm.dts
@@ -359,6 +359,13 @@
 			J722S_IOPAD(0x00a0, PIN_OUTPUT, 1) /* (N24) GPMC0_WPn.AUDIO_EXT_REFCLK1 */
 		>;
 	};
+
+	pmic_irq_pins_default: pmic-irq-default-pins {
+		pinctrl-single,pins = <
+			J722S_IOPAD(0x030, PIN_INPUT, 7) /* (K23) GPIO0_12 */
+		>;
+	};
+
 };
 
 &cpsw3g {
@@ -406,6 +413,13 @@
 
 &mcu_pmx0 {
 
+	mcu_i2c0_pins_default: mcu-i2c0-default-pins {
+		pinctrl-single,pins = <
+			J722S_MCU_IOPAD(0x048, PIN_INPUT, 0) /* (E11) MCU_I2C0_SDA */
+			J722S_MCU_IOPAD(0x044, PIN_INPUT, 0) /* (B13) MCU_I2C0_SCL */
+		>;
+	};
+
 	mcu_mcan0_pins_default: mcu-mcan0-default-pins {
 		pinctrl-single,pins = <
 			J722S_MCU_IOPAD(0x038, PIN_INPUT, 0) /* (D8) MCU_MCAN0_RX */
@@ -459,6 +473,87 @@
 	clock-frequency = <400000>;
 	status = "okay";
 	bootph-all;
+
+	tps65224: pmic@48 {
+		compatible = "ti,tps65224-q1";
+		reg = <0x48>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pmic_irq_pins_default>;
+		interrupt-parent = <&main_gpio0>;
+		interrupts = <0 IRQ_TYPE_EDGE_FALLING>;
+		ti,primary-pmic;
+
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		buck12-supply = <&vsys_io_3v3>;
+		buck3-supply = <&vsys_io_3v3>;
+		buck4-supply = <&vsys_io_3v3>;
+
+		ldo1-supply = <&vsys_io_3v3>;
+		ldo2-supply = <&vsys_io_3v3>;
+		ldo3-supply = <&vsys_io_3v3>;
+
+		regulators {
+
+			buck1: buck1 {
+				regulator-name = "vcc1v8_io_buck1";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-boot-on;
+				regulator-always-on;
+				bootph-all;
+			};
+
+			buck2: buck2 {
+				regulator-name = "vcc1v1_ddr_buck2";
+				regulator-min-microvolt = <1100000>;
+				regulator-max-microvolt = <1100000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			buck3: buck3 {
+				regulator-name = "vcc0v85_ram_buck3";
+				regulator-min-microvolt = <850000>;
+				regulator-max-microvolt = <850000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			buck4: buck4 {
+				regulator-name = "vcc0v75_ioret_buck4";
+				regulator-min-microvolt = <750000>;
+				regulator-max-microvolt = <750000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			ldo1: ldo1 {
+				regulator-name = "vdda1v8_pll_ldo1";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			ldo2: ldo2 {
+				regulator-name = "dvdd3v3_ldo2";
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			ldo3: ldo3 {
+				regulator-name = "vdd1v85_phy_ldo3";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+	       };
+	};
 };
 
 &k3_clks {
@@ -812,3 +907,10 @@
 &mcu_gpio0 {
 	status = "okay";
 };
+
+&mcu_i2c0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&mcu_i2c0_pins_default>;
+	clock-frequency = <400000>;
+	status = "okay";
+};
diff --git a/dts/upstream/src/arm64/ti/k3-j784s4-j742s2-evm-common.dtsi b/dts/upstream/src/arm64/ti/k3-j784s4-j742s2-evm-common.dtsi
index b2e2b9f507a..2664f74a9c7 100644
--- a/dts/upstream/src/arm64/ti/k3-j784s4-j742s2-evm-common.dtsi
+++ b/dts/upstream/src/arm64/ti/k3-j784s4-j742s2-evm-common.dtsi
@@ -635,6 +635,7 @@
 				regulator-max-microvolt = <1100000>;
 				regulator-boot-on;
 				regulator-always-on;
+				bootph-all;
 			};
 
 			bucka3: buck3 {
@@ -643,6 +644,7 @@
 				regulator-max-microvolt = <850000>;
 				regulator-boot-on;
 				regulator-always-on;
+				bootph-all;
 			};
 
 			bucka4: buck4 {
@@ -651,6 +653,7 @@
 				regulator-max-microvolt = <1800000>;
 				regulator-boot-on;
 				regulator-always-on;
+				bootph-all;
 			};
 
 			bucka5: buck5 {
@@ -659,6 +662,7 @@
 				regulator-max-microvolt = <850000>;
 				regulator-boot-on;
 				regulator-always-on;
+				bootph-all;
 			};
 
 			ldoa1: ldo1 {
@@ -667,6 +671,7 @@
 				regulator-max-microvolt = <1800000>;
 				regulator-boot-on;
 				regulator-always-on;
+				bootph-all;
 			};
 
 			ldoa2: ldo2 {
@@ -675,6 +680,7 @@
 				regulator-max-microvolt = <3300000>;
 				regulator-boot-on;
 				regulator-always-on;
+				bootph-all;
 			};
 
 			ldoa3: ldo3 {
@@ -683,6 +689,7 @@
 				regulator-max-microvolt = <800000>;
 				regulator-boot-on;
 				regulator-always-on;
+				bootph-all;
 			};
 
 			ldoa4: ldo4 {
@@ -691,6 +698,7 @@
 				regulator-max-microvolt = <1800000>;
 				regulator-boot-on;
 				regulator-always-on;
+				bootph-all;
 			};
 		};
 	};
diff --git a/dts/upstream/src/arm64/ti/k3-j784s4-j742s2-main-common.dtsi b/dts/upstream/src/arm64/ti/k3-j784s4-j742s2-main-common.dtsi
index 7721852c1f6..83bbf94b58d 100644
--- a/dts/upstream/src/arm64/ti/k3-j784s4-j742s2-main-common.dtsi
+++ b/dts/upstream/src/arm64/ti/k3-j784s4-j742s2-main-common.dtsi
@@ -224,7 +224,7 @@
 	};
 
 	main_pmx0: pinctrl@11c000 {
-		compatible = "pinctrl-single";
+		compatible = "ti,j7200-padconf", "pinctrl-single";
 		/* Proxy 0 addressing */
 		reg = <0x00 0x11c000 0x00 0x120>;
 		#pinctrl-cells = <1>;
@@ -234,7 +234,7 @@
 
 	/* TIMERIO pad input CTRLMMR_TIMER*_CTRL registers */
 	main_timerio_input: pinctrl@104200 {
-		compatible = "pinctrl-single";
+		compatible = "ti,j7200-padconf", "pinctrl-single";
 		reg = <0x00 0x104200 0x00 0x50>;
 		#pinctrl-cells = <1>;
 		pinctrl-single,register-width = <32>;
@@ -243,7 +243,7 @@
 
 	/* TIMERIO pad output CTCTRLMMR_TIMERIO*_CTRL registers */
 	main_timerio_output: pinctrl@104280 {
-		compatible = "pinctrl-single";
+		compatible = "ti,j7200-padconf", "pinctrl-single";
 		reg = <0x00 0x104280 0x00 0x20>;
 		#pinctrl-cells = <1>;
 		pinctrl-single,register-width = <32>;
@@ -2040,7 +2040,7 @@
 		#address-cells = <1>;
 		#size-cells = <0>;
 		power-domains = <&k3_pds 376 TI_SCI_PD_EXCLUSIVE>;
-		clocks = <&k3_clks 376 1>;
+		clocks = <&k3_clks 376 0>;
 		status = "disabled";
 	};
 
@@ -2051,7 +2051,7 @@
 		#address-cells = <1>;
 		#size-cells = <0>;
 		power-domains = <&k3_pds 377 TI_SCI_PD_EXCLUSIVE>;
-		clocks = <&k3_clks 377 1>;
+		clocks = <&k3_clks 377 0>;
 		status = "disabled";
 	};
 
@@ -2062,7 +2062,7 @@
 		#address-cells = <1>;
 		#size-cells = <0>;
 		power-domains = <&k3_pds 378 TI_SCI_PD_EXCLUSIVE>;
-		clocks = <&k3_clks 378 1>;
+		clocks = <&k3_clks 378 0>;
 		status = "disabled";
 	};
 
@@ -2073,7 +2073,7 @@
 		#address-cells = <1>;
 		#size-cells = <0>;
 		power-domains = <&k3_pds 379 TI_SCI_PD_EXCLUSIVE>;
-		clocks = <&k3_clks 379 1>;
+		clocks = <&k3_clks 379 0>;
 		status = "disabled";
 	};
 
@@ -2084,7 +2084,7 @@
 		#address-cells = <1>;
 		#size-cells = <0>;
 		power-domains = <&k3_pds 380 TI_SCI_PD_EXCLUSIVE>;
-		clocks = <&k3_clks 380 1>;
+		clocks = <&k3_clks 380 0>;
 		status = "disabled";
 	};
 
@@ -2095,7 +2095,7 @@
 		#address-cells = <1>;
 		#size-cells = <0>;
 		power-domains = <&k3_pds 381 TI_SCI_PD_EXCLUSIVE>;
-		clocks = <&k3_clks 381 1>;
+		clocks = <&k3_clks 381 0>;
 		status = "disabled";
 	};
 
@@ -2106,7 +2106,7 @@
 		#address-cells = <1>;
 		#size-cells = <0>;
 		power-domains = <&k3_pds 382 TI_SCI_PD_EXCLUSIVE>;
-		clocks = <&k3_clks 382 1>;
+		clocks = <&k3_clks 382 0>;
 		status = "disabled";
 	};
 
@@ -2117,7 +2117,7 @@
 		#address-cells = <1>;
 		#size-cells = <0>;
 		power-domains = <&k3_pds 383 TI_SCI_PD_EXCLUSIVE>;
-		clocks = <&k3_clks 383 1>;
+		clocks = <&k3_clks 383 0>;
 		status = "disabled";
 	};
 
diff --git a/dts/upstream/src/arm64/ti/k3-j784s4-j742s2-mcu-wakeup-common.dtsi b/dts/upstream/src/arm64/ti/k3-j784s4-j742s2-mcu-wakeup-common.dtsi
index 9638130caec..52e2965a3bf 100644
--- a/dts/upstream/src/arm64/ti/k3-j784s4-j742s2-mcu-wakeup-common.dtsi
+++ b/dts/upstream/src/arm64/ti/k3-j784s4-j742s2-mcu-wakeup-common.dtsi
@@ -76,7 +76,7 @@
 	};
 
 	wkup_pmx0: pinctrl@4301c000 {
-		compatible = "pinctrl-single";
+		compatible = "ti,j7200-padconf", "pinctrl-single";
 		/* Proxy 0 addressing */
 		reg = <0x00 0x4301c000 0x00 0x034>;
 		#pinctrl-cells = <1>;
@@ -85,7 +85,7 @@
 	};
 
 	wkup_pmx1: pinctrl@4301c038 {
-		compatible = "pinctrl-single";
+		compatible = "ti,j7200-padconf", "pinctrl-single";
 		/* Proxy 0 addressing */
 		reg = <0x00 0x4301c038 0x00 0x02c>;
 		#pinctrl-cells = <1>;
@@ -94,7 +94,7 @@
 	};
 
 	wkup_pmx2: pinctrl@4301c068 {
-		compatible = "pinctrl-single";
+		compatible = "ti,j7200-padconf", "pinctrl-single";
 		/* Proxy 0 addressing */
 		reg = <0x00 0x4301c068 0x00 0x120>;
 		#pinctrl-cells = <1>;
@@ -103,7 +103,7 @@
 	};
 
 	wkup_pmx3: pinctrl@4301c190 {
-		compatible = "pinctrl-single";
+		compatible = "ti,j7200-padconf", "pinctrl-single";
 		/* Proxy 0 addressing */
 		reg = <0x00 0x4301c190 0x00 0x004>;
 		#pinctrl-cells = <1>;
@@ -125,7 +125,7 @@
 
 	/* MCU_TIMERIO pad input CTRLMMR_MCU_TIMER*_CTRL registers */
 	mcu_timerio_input: pinctrl@40f04200 {
-		compatible = "pinctrl-single";
+		compatible = "ti,j7200-padconf", "pinctrl-single";
 		reg = <0x00 0x40f04200 0x00 0x28>;
 		#pinctrl-cells = <1>;
 		pinctrl-single,register-width = <32>;
@@ -136,7 +136,7 @@
 
 	/* MCU_TIMERIO pad output CTRLMMR_MCU_TIMERIO*_CTRL registers */
 	mcu_timerio_output: pinctrl@40f04280 {
-		compatible = "pinctrl-single";
+		compatible = "ti,j7200-padconf", "pinctrl-single";
 		reg = <0x00 0x40f04280 0x00 0x28>;
 		#pinctrl-cells = <1>;
 		pinctrl-single,register-width = <32>;
diff --git a/dts/upstream/src/arm64/ti/k3-pinctrl.h b/dts/upstream/src/arm64/ti/k3-pinctrl.h
index 22b8d73cfd3..cac7cccc111 100644
--- a/dts/upstream/src/arm64/ti/k3-pinctrl.h
+++ b/dts/upstream/src/arm64/ti/k3-pinctrl.h
@@ -12,6 +12,12 @@
 #define PULLTYPESEL_SHIFT	(17)
 #define RXACTIVE_SHIFT		(18)
 #define DEBOUNCE_SHIFT		(11)
+#define FORCE_DS_EN_SHIFT	(15)
+#define DS_EN_SHIFT		(24)
+#define DS_OUT_DIS_SHIFT	(25)
+#define DS_OUT_VAL_SHIFT	(26)
+#define DS_PULLUD_EN_SHIFT	(27)
+#define DS_PULLTYPE_SEL_SHIFT	(28)
 
 #define PULL_DISABLE		(1 << PULLUDEN_SHIFT)
 #define PULL_ENABLE		(0 << PULLUDEN_SHIFT)
@@ -38,6 +44,19 @@
 #define PIN_DEBOUNCE_CONF5	(5 << DEBOUNCE_SHIFT)
 #define PIN_DEBOUNCE_CONF6	(6 << DEBOUNCE_SHIFT)
 
+#define PIN_DS_FORCE_DISABLE		(0 << FORCE_DS_EN_SHIFT)
+#define PIN_DS_FORCE_ENABLE		(1 << FORCE_DS_EN_SHIFT)
+#define PIN_DS_IO_OVERRIDE_DISABLE	(0 << DS_IO_OVERRIDE_EN_SHIFT)
+#define PIN_DS_IO_OVERRIDE_ENABLE	(1 << DS_IO_OVERRIDE_EN_SHIFT)
+#define PIN_DS_OUT_ENABLE		(0 << DS_OUT_DIS_SHIFT)
+#define PIN_DS_OUT_DISABLE		(1 << DS_OUT_DIS_SHIFT)
+#define PIN_DS_OUT_VALUE_ZERO		(0 << DS_OUT_VAL_SHIFT)
+#define PIN_DS_OUT_VALUE_ONE		(1 << DS_OUT_VAL_SHIFT)
+#define PIN_DS_PULLUD_ENABLE		(0 << DS_PULLUD_EN_SHIFT)
+#define PIN_DS_PULLUD_DISABLE		(1 << DS_PULLUD_EN_SHIFT)
+#define PIN_DS_PULL_DOWN		(0 << DS_PULLTYPE_SEL_SHIFT)
+#define PIN_DS_PULL_UP			(1 << DS_PULLTYPE_SEL_SHIFT)
+
 /* Default mux configuration for gpio-ranges to use with pinctrl */
 #define PIN_GPIO_RANGE_IOPAD	(PIN_INPUT | 7)
 
diff --git a/dts/upstream/src/arm64/xilinx/zynqmp.dtsi b/dts/upstream/src/arm64/xilinx/zynqmp.dtsi
index 467f084c646..e11d282462b 100644
--- a/dts/upstream/src/arm64/xilinx/zynqmp.dtsi
+++ b/dts/upstream/src/arm64/xilinx/zynqmp.dtsi
@@ -1306,11 +1306,14 @@
 				      "dp_vtc_pixel_clk_in";
 			power-domains = <&zynqmp_firmware PD_DP>;
 			resets = <&zynqmp_reset ZYNQMP_RESET_DP>;
-			dma-names = "vid0", "vid1", "vid2", "gfx0";
+			dma-names = "vid0", "vid1", "vid2", "gfx0",
+				    "aud0", "aud1";
 			dmas = <&zynqmp_dpdma ZYNQMP_DPDMA_VIDEO0>,
 			       <&zynqmp_dpdma ZYNQMP_DPDMA_VIDEO1>,
 			       <&zynqmp_dpdma ZYNQMP_DPDMA_VIDEO2>,
-			       <&zynqmp_dpdma ZYNQMP_DPDMA_GRAPHICS>;
+			       <&zynqmp_dpdma ZYNQMP_DPDMA_GRAPHICS>,
+			       <&zynqmp_dpdma ZYNQMP_DPDMA_AUDIO0>,
+			       <&zynqmp_dpdma ZYNQMP_DPDMA_AUDIO1>;
 
 			ports {
 				#address-cells = <1>;
diff --git a/dts/upstream/src/mips/mobileye/eyeq5.dtsi b/dts/upstream/src/mips/mobileye/eyeq5.dtsi
index 5d73e8320b8..a84e6e72061 100644
--- a/dts/upstream/src/mips/mobileye/eyeq5.dtsi
+++ b/dts/upstream/src/mips/mobileye/eyeq5.dtsi
@@ -49,6 +49,28 @@
 		mhm_reserved_0: the-mhm-reserved-0@0 {
 			reg = <0x8 0x00000000 0x0 0x0000800>;
 		};
+
+		nvram@461fe00 {
+			compatible = "mobileye,eyeq5-bootloader-config", "nvmem-rmem";
+			reg = <0x0 0x0461fe00 0x0 0x200>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			no-map;
+
+			nvmem-layout {
+				compatible = "fixed-layout";
+				#address-cells = <1>;
+				#size-cells = <1>;
+
+				eth0_mac: mac@7c {
+					reg = <0x7c 0x6>;
+				};
+
+				eth1_mac: mac@82 {
+					reg = <0x82 0x6>;
+				};
+			};
+		};
 	};
 
 	aliases {
diff --git a/dts/upstream/src/riscv/allwinner/sun20i-d1s.dtsi b/dts/upstream/src/riscv/allwinner/sun20i-d1s.dtsi
index 64c3c2e6cbe..6367112e614 100644
--- a/dts/upstream/src/riscv/allwinner/sun20i-d1s.dtsi
+++ b/dts/upstream/src/riscv/allwinner/sun20i-d1s.dtsi
@@ -27,7 +27,8 @@
 			riscv,isa = "rv64imafdc";
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
-					       "zifencei", "zihpm";
+					       "zifencei", "zihpm", "xtheadvector";
+			thead,vlenb = <128>;
 			#cooling-cells = <2>;
 
 			cpu0_intc: interrupt-controller {
diff --git a/dts/upstream/src/riscv/spacemit/k1-bananapi-f3.dts b/dts/upstream/src/riscv/spacemit/k1-bananapi-f3.dts
new file mode 100644
index 00000000000..1d617b40a2d
--- /dev/null
+++ b/dts/upstream/src/riscv/spacemit/k1-bananapi-f3.dts
@@ -0,0 +1,26 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (C) 2024 Yangyu Chen <cyy@cyyself.name>
+ */
+
+#include "k1.dtsi"
+#include "k1-pinctrl.dtsi"
+
+/ {
+	model = "Banana Pi BPI-F3";
+	compatible = "bananapi,bpi-f3", "spacemit,k1";
+
+	aliases {
+		serial0 = &uart0;
+	};
+
+	chosen {
+		stdout-path = "serial0";
+	};
+};
+
+&uart0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart0_2_cfg>;
+	status = "okay";
+};
diff --git a/dts/upstream/src/riscv/spacemit/k1-pinctrl.dtsi b/dts/upstream/src/riscv/spacemit/k1-pinctrl.dtsi
new file mode 100644
index 00000000000..a8eac5517f8
--- /dev/null
+++ b/dts/upstream/src/riscv/spacemit/k1-pinctrl.dtsi
@@ -0,0 +1,20 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (c) 2024 Yixun Lan <dlan@gentoo.org>
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+
+#define K1_PADCONF(pin, func) (((pin) << 16) | (func))
+
+&pinctrl {
+	uart0_2_cfg: uart0-2-cfg {
+		uart0-2-pins {
+			pinmux = <K1_PADCONF(68, 2)>,
+				 <K1_PADCONF(69, 2)>;
+
+			bias-pull-up = <0>;
+			drive-strength = <32>;
+		};
+	};
+};
diff --git a/dts/upstream/src/riscv/spacemit/k1.dtsi b/dts/upstream/src/riscv/spacemit/k1.dtsi
new file mode 100644
index 00000000000..c670ebf8fa1
--- /dev/null
+++ b/dts/upstream/src/riscv/spacemit/k1.dtsi
@@ -0,0 +1,452 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (C) 2024 Yangyu Chen <cyy@cyyself.name>
+ */
+
+/dts-v1/;
+/ {
+	#address-cells = <2>;
+	#size-cells = <2>;
+	model = "SpacemiT K1";
+	compatible = "spacemit,k1";
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		timebase-frequency = <24000000>;
+
+		cpu-map {
+			cluster0 {
+				core0 {
+					cpu = <&cpu_0>;
+				};
+				core1 {
+					cpu = <&cpu_1>;
+				};
+				core2 {
+					cpu = <&cpu_2>;
+				};
+				core3 {
+					cpu = <&cpu_3>;
+				};
+			};
+
+			cluster1 {
+				core0 {
+					cpu = <&cpu_4>;
+				};
+				core1 {
+					cpu = <&cpu_5>;
+				};
+				core2 {
+					cpu = <&cpu_6>;
+				};
+				core3 {
+					cpu = <&cpu_7>;
+				};
+			};
+		};
+
+		cpu_0: cpu@0 {
+			compatible = "spacemit,x60", "riscv";
+			device_type = "cpu";
+			reg = <0>;
+			riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
+			riscv,isa-base = "rv64i";
+			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
+					       "zicbop", "zicboz", "zicntr", "zicond", "zicsr",
+					       "zifencei", "zihintpause", "zihpm", "zfh", "zba",
+					       "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
+					       "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt";
+			riscv,cbom-block-size = <64>;
+			riscv,cbop-block-size = <64>;
+			riscv,cboz-block-size = <64>;
+			i-cache-block-size = <64>;
+			i-cache-size = <32768>;
+			i-cache-sets = <128>;
+			d-cache-block-size = <64>;
+			d-cache-size = <32768>;
+			d-cache-sets = <128>;
+			next-level-cache = <&cluster0_l2_cache>;
+			mmu-type = "riscv,sv39";
+
+			cpu0_intc: interrupt-controller {
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+				#interrupt-cells = <1>;
+			};
+		};
+
+		cpu_1: cpu@1 {
+			compatible = "spacemit,x60", "riscv";
+			device_type = "cpu";
+			reg = <1>;
+			riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
+			riscv,isa-base = "rv64i";
+			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
+					       "zicbop", "zicboz", "zicntr", "zicond", "zicsr",
+					       "zifencei", "zihintpause", "zihpm", "zfh", "zba",
+					       "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
+					       "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt";
+			riscv,cbom-block-size = <64>;
+			riscv,cbop-block-size = <64>;
+			riscv,cboz-block-size = <64>;
+			i-cache-block-size = <64>;
+			i-cache-size = <32768>;
+			i-cache-sets = <128>;
+			d-cache-block-size = <64>;
+			d-cache-size = <32768>;
+			d-cache-sets = <128>;
+			next-level-cache = <&cluster0_l2_cache>;
+			mmu-type = "riscv,sv39";
+
+			cpu1_intc: interrupt-controller {
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+				#interrupt-cells = <1>;
+			};
+		};
+
+		cpu_2: cpu@2 {
+			compatible = "spacemit,x60", "riscv";
+			device_type = "cpu";
+			reg = <2>;
+			riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
+			riscv,isa-base = "rv64i";
+			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
+					       "zicbop", "zicboz", "zicntr", "zicond", "zicsr",
+					       "zifencei", "zihintpause", "zihpm", "zfh", "zba",
+					       "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
+					       "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt";
+			riscv,cbom-block-size = <64>;
+			riscv,cbop-block-size = <64>;
+			riscv,cboz-block-size = <64>;
+			i-cache-block-size = <64>;
+			i-cache-size = <32768>;
+			i-cache-sets = <128>;
+			d-cache-block-size = <64>;
+			d-cache-size = <32768>;
+			d-cache-sets = <128>;
+			next-level-cache = <&cluster0_l2_cache>;
+			mmu-type = "riscv,sv39";
+
+			cpu2_intc: interrupt-controller {
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+				#interrupt-cells = <1>;
+			};
+		};
+
+		cpu_3: cpu@3 {
+			compatible = "spacemit,x60", "riscv";
+			device_type = "cpu";
+			reg = <3>;
+			riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
+			riscv,isa-base = "rv64i";
+			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
+					       "zicbop", "zicboz", "zicntr", "zicond", "zicsr",
+					       "zifencei", "zihintpause", "zihpm", "zfh", "zba",
+					       "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
+					       "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt";
+			riscv,cbom-block-size = <64>;
+			riscv,cbop-block-size = <64>;
+			riscv,cboz-block-size = <64>;
+			i-cache-block-size = <64>;
+			i-cache-size = <32768>;
+			i-cache-sets = <128>;
+			d-cache-block-size = <64>;
+			d-cache-size = <32768>;
+			d-cache-sets = <128>;
+			next-level-cache = <&cluster0_l2_cache>;
+			mmu-type = "riscv,sv39";
+
+			cpu3_intc: interrupt-controller {
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+				#interrupt-cells = <1>;
+			};
+		};
+
+		cpu_4: cpu@4 {
+			compatible = "spacemit,x60", "riscv";
+			device_type = "cpu";
+			reg = <4>;
+			riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
+			riscv,isa-base = "rv64i";
+			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
+					       "zicbop", "zicboz", "zicntr", "zicond", "zicsr",
+					       "zifencei", "zihintpause", "zihpm", "zfh", "zba",
+					       "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
+					       "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt";
+			riscv,cbom-block-size = <64>;
+			riscv,cbop-block-size = <64>;
+			riscv,cboz-block-size = <64>;
+			i-cache-block-size = <64>;
+			i-cache-size = <32768>;
+			i-cache-sets = <128>;
+			d-cache-block-size = <64>;
+			d-cache-size = <32768>;
+			d-cache-sets = <128>;
+			next-level-cache = <&cluster1_l2_cache>;
+			mmu-type = "riscv,sv39";
+
+			cpu4_intc: interrupt-controller {
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+				#interrupt-cells = <1>;
+			};
+		};
+
+		cpu_5: cpu@5 {
+			compatible = "spacemit,x60", "riscv";
+			device_type = "cpu";
+			reg = <5>;
+			riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
+			riscv,isa-base = "rv64i";
+			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
+					       "zicbop", "zicboz", "zicntr", "zicond", "zicsr",
+					       "zifencei", "zihintpause", "zihpm", "zfh", "zba",
+					       "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
+					       "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt";
+			riscv,cbom-block-size = <64>;
+			riscv,cbop-block-size = <64>;
+			riscv,cboz-block-size = <64>;
+			i-cache-block-size = <64>;
+			i-cache-size = <32768>;
+			i-cache-sets = <128>;
+			d-cache-block-size = <64>;
+			d-cache-size = <32768>;
+			d-cache-sets = <128>;
+			next-level-cache = <&cluster1_l2_cache>;
+			mmu-type = "riscv,sv39";
+
+			cpu5_intc: interrupt-controller {
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+				#interrupt-cells = <1>;
+			};
+		};
+
+		cpu_6: cpu@6 {
+			compatible = "spacemit,x60", "riscv";
+			device_type = "cpu";
+			reg = <6>;
+			riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
+			riscv,isa-base = "rv64i";
+			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
+					       "zicbop", "zicboz", "zicntr", "zicond", "zicsr",
+					       "zifencei", "zihintpause", "zihpm", "zfh", "zba",
+					       "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
+					       "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt";
+			riscv,cbom-block-size = <64>;
+			riscv,cbop-block-size = <64>;
+			riscv,cboz-block-size = <64>;
+			i-cache-block-size = <64>;
+			i-cache-size = <32768>;
+			i-cache-sets = <128>;
+			d-cache-block-size = <64>;
+			d-cache-size = <32768>;
+			d-cache-sets = <128>;
+			next-level-cache = <&cluster1_l2_cache>;
+			mmu-type = "riscv,sv39";
+
+			cpu6_intc: interrupt-controller {
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+				#interrupt-cells = <1>;
+			};
+		};
+
+		cpu_7: cpu@7 {
+			compatible = "spacemit,x60", "riscv";
+			device_type = "cpu";
+			reg = <7>;
+			riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
+			riscv,isa-base = "rv64i";
+			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
+					       "zicbop", "zicboz", "zicntr", "zicond", "zicsr",
+					       "zifencei", "zihintpause", "zihpm", "zfh", "zba",
+					       "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
+					       "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt";
+			riscv,cbom-block-size = <64>;
+			riscv,cbop-block-size = <64>;
+			riscv,cboz-block-size = <64>;
+			i-cache-block-size = <64>;
+			i-cache-size = <32768>;
+			i-cache-sets = <128>;
+			d-cache-block-size = <64>;
+			d-cache-size = <32768>;
+			d-cache-sets = <128>;
+			next-level-cache = <&cluster1_l2_cache>;
+			mmu-type = "riscv,sv39";
+
+			cpu7_intc: interrupt-controller {
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+				#interrupt-cells = <1>;
+			};
+		};
+
+		cluster0_l2_cache: l2-cache0 {
+			compatible = "cache";
+			cache-block-size = <64>;
+			cache-level = <2>;
+			cache-size = <524288>;
+			cache-sets = <512>;
+			cache-unified;
+		};
+
+		cluster1_l2_cache: l2-cache1 {
+			compatible = "cache";
+			cache-block-size = <64>;
+			cache-level = <2>;
+			cache-size = <524288>;
+			cache-sets = <512>;
+			cache-unified;
+		};
+	};
+
+	soc {
+		compatible = "simple-bus";
+		interrupt-parent = <&plic>;
+		#address-cells = <2>;
+		#size-cells = <2>;
+		dma-noncoherent;
+		ranges;
+
+		uart0: serial@d4017000 {
+			compatible = "spacemit,k1-uart", "intel,xscale-uart";
+			reg = <0x0 0xd4017000 0x0 0x100>;
+			interrupts = <42>;
+			clock-frequency = <14857000>;
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			status = "disabled";
+		};
+
+		uart2: serial@d4017100 {
+			compatible = "spacemit,k1-uart", "intel,xscale-uart";
+			reg = <0x0 0xd4017100 0x0 0x100>;
+			interrupts = <44>;
+			clock-frequency = <14857000>;
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			status = "disabled";
+		};
+
+		uart3: serial@d4017200 {
+			compatible = "spacemit,k1-uart", "intel,xscale-uart";
+			reg = <0x0 0xd4017200 0x0 0x100>;
+			interrupts = <45>;
+			clock-frequency = <14857000>;
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			status = "disabled";
+		};
+
+		uart4: serial@d4017300 {
+			compatible = "spacemit,k1-uart", "intel,xscale-uart";
+			reg = <0x0 0xd4017300 0x0 0x100>;
+			interrupts = <46>;
+			clock-frequency = <14857000>;
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			status = "disabled";
+		};
+
+		uart5: serial@d4017400 {
+			compatible = "spacemit,k1-uart", "intel,xscale-uart";
+			reg = <0x0 0xd4017400 0x0 0x100>;
+			interrupts = <47>;
+			clock-frequency = <14857000>;
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			status = "disabled";
+		};
+
+		uart6: serial@d4017500 {
+			compatible = "spacemit,k1-uart", "intel,xscale-uart";
+			reg = <0x0 0xd4017500 0x0 0x100>;
+			interrupts = <48>;
+			clock-frequency = <14857000>;
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			status = "disabled";
+		};
+
+		uart7: serial@d4017600 {
+			compatible = "spacemit,k1-uart", "intel,xscale-uart";
+			reg = <0x0 0xd4017600 0x0 0x100>;
+			interrupts = <49>;
+			clock-frequency = <14857000>;
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			status = "disabled";
+		};
+
+		uart8: serial@d4017700 {
+			compatible = "spacemit,k1-uart", "intel,xscale-uart";
+			reg = <0x0 0xd4017700 0x0 0x100>;
+			interrupts = <50>;
+			clock-frequency = <14857000>;
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			status = "disabled";
+		};
+
+		uart9: serial@d4017800 {
+			compatible = "spacemit,k1-uart", "intel,xscale-uart";
+			reg = <0x0 0xd4017800 0x0 0x100>;
+			interrupts = <51>;
+			clock-frequency = <14857000>;
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			status = "disabled";
+		};
+
+		pinctrl: pinctrl@d401e000 {
+			compatible = "spacemit,k1-pinctrl";
+			reg = <0x0 0xd401e000 0x0 0x400>;
+		};
+
+		plic: interrupt-controller@e0000000 {
+			compatible = "spacemit,k1-plic", "sifive,plic-1.0.0";
+			reg = <0x0 0xe0000000 0x0 0x4000000>;
+			interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>,
+					      <&cpu1_intc 11>, <&cpu1_intc 9>,
+					      <&cpu2_intc 11>, <&cpu2_intc 9>,
+					      <&cpu3_intc 11>, <&cpu3_intc 9>,
+					      <&cpu4_intc 11>, <&cpu4_intc 9>,
+					      <&cpu5_intc 11>, <&cpu5_intc 9>,
+					      <&cpu6_intc 11>, <&cpu6_intc 9>,
+					      <&cpu7_intc 11>, <&cpu7_intc 9>;
+			interrupt-controller;
+			#address-cells = <0>;
+			#interrupt-cells = <1>;
+			riscv,ndev = <159>;
+		};
+
+		clint: timer@e4000000 {
+			compatible = "spacemit,k1-clint", "sifive,clint0";
+			reg = <0x0 0xe4000000 0x0 0x10000>;
+			interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>,
+					      <&cpu1_intc 3>, <&cpu1_intc 7>,
+					      <&cpu2_intc 3>, <&cpu2_intc 7>,
+					      <&cpu3_intc 3>, <&cpu3_intc 7>,
+					      <&cpu4_intc 3>, <&cpu4_intc 7>,
+					      <&cpu5_intc 3>, <&cpu5_intc 7>,
+					      <&cpu6_intc 3>, <&cpu6_intc 7>,
+					      <&cpu7_intc 3>, <&cpu7_intc 7>;
+		};
+
+		sec_uart1: serial@f0612000 {
+			compatible = "spacemit,k1-uart", "intel,xscale-uart";
+			reg = <0x0 0xf0612000 0x0 0x100>;
+			interrupts = <43>;
+			clock-frequency = <14857000>;
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			status = "reserved"; /* for TEE usage */
+		};
+	};
+};
diff --git a/dts/upstream/src/riscv/starfive/jh7110-milkv-mars.dts b/dts/upstream/src/riscv/starfive/jh7110-milkv-mars.dts
index 0d248b671d4..3bd62ab7852 100644
--- a/dts/upstream/src/riscv/starfive/jh7110-milkv-mars.dts
+++ b/dts/upstream/src/riscv/starfive/jh7110-milkv-mars.dts
@@ -53,7 +53,23 @@
 	status = "okay";
 };
 
+&sysgpio {
+	usb0_pins: usb0-0 {
+		vbus-pins {
+			pinmux = <GPIOMUX(25, GPOUT_SYS_USB_DRIVE_VBUS,
+					      GPOEN_ENABLE,
+					      GPI_NONE)>;
+			bias-disable;
+			input-disable;
+			input-schmitt-disable;
+			slew-rate = <0>;
+		};
+	};
+};
+
 &usb0 {
-	dr_mode = "peripheral";
+	dr_mode = "host";
+	pinctrl-names = "default";
+	pinctrl-0 = <&usb0_pins>;
 	status = "okay";
 };
diff --git a/dts/upstream/src/riscv/starfive/jh7110-pine64-star64.dts b/dts/upstream/src/riscv/starfive/jh7110-pine64-star64.dts
index fe4a490ecc6..b764d4d92fd 100644
--- a/dts/upstream/src/riscv/starfive/jh7110-pine64-star64.dts
+++ b/dts/upstream/src/riscv/starfive/jh7110-pine64-star64.dts
@@ -80,7 +80,23 @@
 	status = "okay";
 };
 
+&sysgpio {
+	usb0_pins: usb0-0 {
+		vbus-pins {
+			pinmux = <GPIOMUX(25,  GPOUT_SYS_USB_DRIVE_VBUS,
+					       GPOEN_ENABLE,
+					       GPI_NONE)>;
+			bias-disable;
+			input-disable;
+			input-schmitt-disable;
+			slew-rate = <0>;
+		};
+	};
+};
+
 &usb0 {
-	dr_mode = "peripheral";
+	dr_mode = "host";
+	pinctrl-names = "default";
+	pinctrl-0 = <&usb0_pins>;
 	status = "okay";
 };
diff --git a/dts/upstream/src/riscv/starfive/jh7110-pinfunc.h b/dts/upstream/src/riscv/starfive/jh7110-pinfunc.h
index 256de17f526..ae49c908e7f 100644
--- a/dts/upstream/src/riscv/starfive/jh7110-pinfunc.h
+++ b/dts/upstream/src/riscv/starfive/jh7110-pinfunc.h
@@ -89,7 +89,7 @@
 #define GPOUT_SYS_SDIO1_DATA1			59
 #define GPOUT_SYS_SDIO1_DATA2			60
 #define GPOUT_SYS_SDIO1_DATA3			61
-#define GPOUT_SYS_SDIO1_DATA4			63
+#define GPOUT_SYS_SDIO1_DATA4			62
 #define GPOUT_SYS_SDIO1_DATA5			63
 #define GPOUT_SYS_SDIO1_DATA6			64
 #define GPOUT_SYS_SDIO1_DATA7			65
diff --git a/dts/upstream/src/riscv/thead/th1520.dtsi b/dts/upstream/src/riscv/thead/th1520.dtsi
index acfe030e803..52733641776 100644
--- a/dts/upstream/src/riscv/thead/th1520.dtsi
+++ b/dts/upstream/src/riscv/thead/th1520.dtsi
@@ -599,6 +599,22 @@
 			status = "disabled";
 		};
 
+		mbox_910t: mailbox@ffffc38000 {
+			compatible = "thead,th1520-mbox";
+			reg = <0xff 0xffc38000 0x0 0x6000>,
+			      <0xff 0xffc40000 0x0 0x6000>,
+			      <0xff 0xffc4c000 0x0 0x2000>,
+			      <0xff 0xffc54000 0x0 0x2000>;
+			reg-names = "local", "remote-icu0", "remote-icu1", "remote-icu2";
+			clocks = <&clk CLK_MBOX0>, <&clk CLK_MBOX1>, <&clk CLK_MBOX2>,
+				 <&clk CLK_MBOX3>;
+			clock-names = "clk-local", "clk-remote-icu0", "clk-remote-icu1",
+				      "clk-remote-icu2";
+			interrupt-parent = <&plic>;
+			interrupts = <28 IRQ_TYPE_LEVEL_HIGH>;
+			#mbox-cells = <1>;
+		};
+
 		gpio@fffff41000 {
 			compatible = "snps,dw-apb-gpio";
 			reg = <0xff 0xfff41000 0x0 0x1000>;
diff --git a/env/mmc.c b/env/mmc.c
index 379f5ec9be7..2ef15fb72e7 100644
--- a/env/mmc.c
+++ b/env/mmc.c
@@ -40,18 +40,6 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-/*
- * In case the environment is redundant, stored in eMMC hardware boot
- * partition and the environment and redundant environment offsets are
- * identical, store the environment and redundant environment in both
- * eMMC boot partitions, one copy in each.
- * */
-#if (defined(CONFIG_SYS_REDUNDAND_ENVIRONMENT) && \
-     (CONFIG_SYS_MMC_ENV_PART == 1) && \
-     (CONFIG_ENV_OFFSET == CONFIG_ENV_OFFSET_REDUND))
-#define ENV_MMC_HWPART_REDUND	1
-#endif
-
 #if CONFIG_IS_ENABLED(OF_CONTROL)
 
 static int mmc_env_partition_by_name(struct blk_desc *desc, const char *str,
@@ -217,6 +205,23 @@ static inline s64 mmc_offset(struct mmc *mmc, int copy)
 }
 #endif
 
+static bool mmc_env_is_redundant_in_both_boot_hwparts(struct mmc *mmc)
+{
+	/*
+	 * In case the environment is redundant, stored in eMMC hardware boot
+	 * partition and the environment and redundant environment offsets are
+	 * identical, store the environment and redundant environment in both
+	 * eMMC boot partitions, one copy in each.
+	 */
+	if (!IS_ENABLED(CONFIG_SYS_REDUNDAND_ENVIRONMENT))
+		return false;
+
+	if (CONFIG_SYS_MMC_ENV_PART != 1)
+		return false;
+
+	return mmc_offset(mmc, 0) == mmc_offset(mmc, 1);
+}
+
 __weak int mmc_get_env_addr(struct mmc *mmc, int copy, u32 *env_addr)
 {
 	s64 offset = mmc_offset(mmc, copy);
@@ -336,7 +341,7 @@ static int env_mmc_save(void)
 		if (gd->env_valid == ENV_VALID)
 			copy = 1;
 
-		if (IS_ENABLED(ENV_MMC_HWPART_REDUND)) {
+		if (mmc_env_is_redundant_in_both_boot_hwparts(mmc)) {
 			ret = mmc_set_env_part(mmc, copy + 1);
 			if (ret)
 				goto fini;
@@ -409,7 +414,7 @@ static int env_mmc_erase(void)
 	if (IS_ENABLED(CONFIG_SYS_REDUNDAND_ENVIRONMENT)) {
 		copy = 1;
 
-		if (IS_ENABLED(ENV_MMC_HWPART_REDUND)) {
+		if (mmc_env_is_redundant_in_both_boot_hwparts(mmc)) {
 			ret = mmc_set_env_part(mmc, copy + 1);
 			if (ret)
 				goto fini;
@@ -443,13 +448,7 @@ static inline int read_env(struct mmc *mmc, unsigned long size,
 	return (n == blk_cnt) ? 0 : -1;
 }
 
-#if defined(ENV_IS_EMBEDDED)
-static int env_mmc_load(void)
-{
-	return 0;
-}
-#elif defined(CONFIG_SYS_REDUNDAND_ENVIRONMENT)
-static int env_mmc_load(void)
+static int env_mmc_load_redundant(void)
 {
 	struct mmc *mmc;
 	u32 offset1, offset2;
@@ -477,7 +476,7 @@ static int env_mmc_load(void)
 		goto fini;
 	}
 
-	if (IS_ENABLED(ENV_MMC_HWPART_REDUND)) {
+	if (mmc_env_is_redundant_in_both_boot_hwparts(mmc)) {
 		ret = mmc_set_env_part(mmc, 1);
 		if (ret)
 			goto fini;
@@ -485,7 +484,7 @@ static int env_mmc_load(void)
 
 	read1_fail = read_env(mmc, CONFIG_ENV_SIZE, offset1, tmp_env1);
 
-	if (IS_ENABLED(ENV_MMC_HWPART_REDUND)) {
+	if (mmc_env_is_redundant_in_both_boot_hwparts(mmc)) {
 		ret = mmc_set_env_part(mmc, 2);
 		if (ret)
 			goto fini;
@@ -505,8 +504,8 @@ err:
 
 	return ret;
 }
-#else /* ! CONFIG_SYS_REDUNDAND_ENVIRONMENT */
-static int env_mmc_load(void)
+
+static int env_mmc_load_singular(void)
 {
 	ALLOC_CACHE_ALIGN_BUFFER(char, buf, CONFIG_ENV_SIZE);
 	struct mmc *mmc;
@@ -551,7 +550,16 @@ err:
 
 	return ret;
 }
-#endif /* CONFIG_SYS_REDUNDAND_ENVIRONMENT */
+
+static int env_mmc_load(void)
+{
+	if (IS_ENABLED(CONFIG_ENV_IS_EMBEDDED))
+		return 0;
+	else if (IS_ENABLED(CONFIG_SYS_REDUNDAND_ENVIRONMENT))
+		return env_mmc_load_redundant();
+	else
+		return env_mmc_load_singular();
+}
 
 U_BOOT_ENV_LOCATION(mmc) = {
 	.location	= ENVL_MMC,
diff --git a/fs/Kconfig b/fs/Kconfig
index 5e83cb27059..e0b0b901e1d 100644
--- a/fs/Kconfig
+++ b/fs/Kconfig
@@ -8,6 +8,8 @@ source "fs/btrfs/Kconfig"
 
 source "fs/cbfs/Kconfig"
 
+source "fs/exfat/Kconfig"
+
 source "fs/ext4/Kconfig"
 
 source "fs/fat/Kconfig"
diff --git a/fs/Makefile b/fs/Makefile
index 1c2ff180bda..ce5e74257a0 100644
--- a/fs/Makefile
+++ b/fs/Makefile
@@ -16,6 +16,7 @@ obj-y				+= fs.o
 obj-$(CONFIG_FS_BTRFS) += btrfs/
 obj-$(CONFIG_FS_CBFS) += cbfs/
 obj-$(CONFIG_CMD_CRAMFS) += cramfs/
+obj-$(CONFIG_FS_EXFAT) += exfat/
 obj-$(CONFIG_FS_EXT4) += ext4/
 obj-$(CONFIG_FS_FAT) += fat/
 obj-$(CONFIG_FS_JFFS2) += jffs2/
diff --git a/fs/exfat/Kconfig b/fs/exfat/Kconfig
new file mode 100644
index 00000000000..bce61e8fcc7
--- /dev/null
+++ b/fs/exfat/Kconfig
@@ -0,0 +1,5 @@
+config FS_EXFAT
+	bool "Enable EXFAT filesystem support"
+	imply CMD_FS_GENERIC if CMDLINE
+	help
+	  This provides read/write support for EXFAT filesystem.
diff --git a/fs/exfat/Makefile b/fs/exfat/Makefile
new file mode 100644
index 00000000000..550c0683d65
--- /dev/null
+++ b/fs/exfat/Makefile
@@ -0,0 +1,13 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-$(CONFIG_FS_EXFAT) += \
+	cluster.o \
+	io.o \
+	lookup.o \
+	mount.o \
+	node.o \
+	repair.o \
+	time.o \
+	utf.o \
+	utils.o
diff --git a/fs/exfat/byteorder.h b/fs/exfat/byteorder.h
new file mode 100644
index 00000000000..98b93c700c3
--- /dev/null
+++ b/fs/exfat/byteorder.h
@@ -0,0 +1,68 @@
+/*
+	byteorder.h (12.01.10)
+	Endianness stuff. exFAT uses little-endian byte order.
+
+	Free exFAT implementation.
+	Copyright (C) 2010-2023  Andrew Nayenko
+
+	This program is free software; you can redistribute it and/or modify
+	it under the terms of the GNU General Public License as published by
+	the Free Software Foundation, either version 2 of the License, or
+	(at your option) any later version.
+
+	This program is distributed in the hope that it will be useful,
+	but WITHOUT ANY WARRANTY; without even the implied warranty of
+	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+	GNU General Public License for more details.
+
+	You should have received a copy of the GNU General Public License along
+	with this program; if not, write to the Free Software Foundation, Inc.,
+	51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+*/
+
+#ifndef BYTEORDER_H_INCLUDED
+#define BYTEORDER_H_INCLUDED
+
+#include "platform.h"
+#include <stdint.h>
+#include <stddef.h>
+
+typedef struct { uint16_t __u16; } le16_t;
+typedef struct { uint32_t __u32; } le32_t;
+typedef struct { uint64_t __u64; } le64_t;
+
+#if EXFAT_BYTE_ORDER == EXFAT_LITTLE_ENDIAN
+
+static inline uint16_t le16_to_cpu(le16_t v) { return v.__u16; }
+static inline uint32_t le32_to_cpu(le32_t v) { return v.__u32; }
+static inline uint64_t le64_to_cpu(le64_t v) { return v.__u64; }
+
+static inline le16_t cpu_to_le16(uint16_t v) { le16_t t = {v}; return t; }
+static inline le32_t cpu_to_le32(uint32_t v) { le32_t t = {v}; return t; }
+static inline le64_t cpu_to_le64(uint64_t v) { le64_t t = {v}; return t; }
+
+typedef size_t bitmap_t;
+
+#elif EXFAT_BYTE_ORDER == EXFAT_BIG_ENDIAN
+
+static inline uint16_t le16_to_cpu(le16_t v)
+	{ return exfat_bswap16(v.__u16); }
+static inline uint32_t le32_to_cpu(le32_t v)
+	{ return exfat_bswap32(v.__u32); }
+static inline uint64_t le64_to_cpu(le64_t v)
+	{ return exfat_bswap64(v.__u64); }
+
+static inline le16_t cpu_to_le16(uint16_t v)
+	{ le16_t t = {exfat_bswap16(v)}; return t; }
+static inline le32_t cpu_to_le32(uint32_t v)
+	{ le32_t t = {exfat_bswap32(v)}; return t; }
+static inline le64_t cpu_to_le64(uint64_t v)
+	{ le64_t t = {exfat_bswap64(v)}; return t; }
+
+typedef unsigned char bitmap_t;
+
+#else
+#error Wow! You have a PDP machine?!
+#endif
+
+#endif /* ifndef BYTEORDER_H_INCLUDED */
diff --git a/fs/exfat/cluster.c b/fs/exfat/cluster.c
new file mode 100644
index 00000000000..4ee6135fd84
--- /dev/null
+++ b/fs/exfat/cluster.c
@@ -0,0 +1,496 @@
+/*
+	cluster.c (03.09.09)
+	exFAT file system implementation library.
+
+	Free exFAT implementation.
+	Copyright (C) 2010-2023  Andrew Nayenko
+
+	This program is free software; you can redistribute it and/or modify
+	it under the terms of the GNU General Public License as published by
+	the Free Software Foundation, either version 2 of the License, or
+	(at your option) any later version.
+
+	This program is distributed in the hope that it will be useful,
+	but WITHOUT ANY WARRANTY; without even the implied warranty of
+	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+	GNU General Public License for more details.
+
+	You should have received a copy of the GNU General Public License along
+	with this program; if not, write to the Free Software Foundation, Inc.,
+	51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+*/
+
+#include "exfat.h"
+#include <errno.h>
+#include <string.h>
+#include <inttypes.h>
+
+/*
+ * Sector to absolute offset.
+ */
+static off_t s2o(const struct exfat* ef, off_t sector)
+{
+	return sector << ef->sb->sector_bits;
+}
+
+/*
+ * Cluster to sector.
+ */
+static off_t c2s(const struct exfat* ef, cluster_t cluster)
+{
+	if (cluster < EXFAT_FIRST_DATA_CLUSTER)
+		exfat_bug("invalid cluster number %u", cluster);
+	return le32_to_cpu(ef->sb->cluster_sector_start) +
+		((off_t) (cluster - EXFAT_FIRST_DATA_CLUSTER) << ef->sb->spc_bits);
+}
+
+/*
+ * Cluster to absolute offset.
+ */
+off_t exfat_c2o(const struct exfat* ef, cluster_t cluster)
+{
+	return s2o(ef, c2s(ef, cluster));
+}
+
+/*
+ * Sector to cluster.
+ */
+static cluster_t s2c(const struct exfat* ef, off_t sector)
+{
+	return ((sector - le32_to_cpu(ef->sb->cluster_sector_start)) >>
+			ef->sb->spc_bits) + EXFAT_FIRST_DATA_CLUSTER;
+}
+
+/*
+ * Size in bytes to size in clusters (rounded upwards).
+ */
+static uint32_t bytes2clusters(const struct exfat* ef, uint64_t bytes)
+{
+	uint64_t cluster_size = CLUSTER_SIZE(*ef->sb);
+	return DIV_ROUND_UP(bytes, cluster_size);
+}
+
+cluster_t exfat_next_cluster(const struct exfat* ef,
+		const struct exfat_node* node, cluster_t cluster)
+{
+	le32_t next;
+	off_t fat_offset;
+
+	if (cluster < EXFAT_FIRST_DATA_CLUSTER)
+		exfat_bug("bad cluster 0x%x", cluster);
+
+	if (node->is_contiguous)
+		return cluster + 1;
+	fat_offset = s2o(ef, le32_to_cpu(ef->sb->fat_sector_start))
+		+ cluster * sizeof(cluster_t);
+	if (exfat_pread(ef->dev, &next, sizeof(next), fat_offset) < 0)
+		return EXFAT_CLUSTER_BAD; /* the caller should handle this and print
+		                             appropriate error message */
+	return le32_to_cpu(next);
+}
+
+cluster_t exfat_advance_cluster(const struct exfat* ef,
+		struct exfat_node* node, uint32_t count)
+{
+	uint32_t i;
+
+	if (node->fptr_index > count)
+	{
+		node->fptr_index = 0;
+		node->fptr_cluster = node->start_cluster;
+	}
+
+	for (i = node->fptr_index; i < count; i++)
+	{
+		node->fptr_cluster = exfat_next_cluster(ef, node, node->fptr_cluster);
+		if (CLUSTER_INVALID(*ef->sb, node->fptr_cluster))
+			break; /* the caller should handle this and print appropriate 
+			          error message */
+	}
+	node->fptr_index = count;
+	return node->fptr_cluster;
+}
+
+static cluster_t find_bit_and_set(bitmap_t* bitmap, size_t start, size_t end)
+{
+	const size_t start_index = start / sizeof(bitmap_t) / 8;
+	const size_t end_index = DIV_ROUND_UP(end, sizeof(bitmap_t) * 8);
+	size_t i;
+	size_t start_bitindex;
+	size_t end_bitindex;
+	size_t c;
+
+	for (i = start_index; i < end_index; i++)
+	{
+		if (bitmap[i] == (bitmap_t) ~((bitmap_t) 0))
+			continue;
+		start_bitindex = MAX(i * sizeof(bitmap_t) * 8, start);
+		end_bitindex = MIN((i + 1) * sizeof(bitmap_t) * 8, end);
+		for (c = start_bitindex; c < end_bitindex; c++)
+			if (BMAP_GET(bitmap, c) == 0)
+			{
+				BMAP_SET(bitmap, c);
+				return c + EXFAT_FIRST_DATA_CLUSTER;
+			}
+	}
+	return EXFAT_CLUSTER_END;
+}
+
+static int flush_nodes(struct exfat* ef, struct exfat_node* node)
+{
+	struct exfat_node* p;
+
+	for (p = node->child; p != NULL; p = p->next)
+	{
+		int rc = flush_nodes(ef, p);
+		if (rc != 0)
+			return rc;
+	}
+	return exfat_flush_node(ef, node);
+}
+
+int exfat_flush_nodes(struct exfat* ef)
+{
+	return flush_nodes(ef, ef->root);
+}
+
+int exfat_flush(struct exfat* ef)
+{
+	if (ef->cmap.dirty)
+	{
+		if (exfat_pwrite(ef->dev, ef->cmap.chunk,
+				BMAP_SIZE(ef->cmap.chunk_size),
+				exfat_c2o(ef, ef->cmap.start_cluster)) < 0)
+		{
+			exfat_error("failed to write clusters bitmap");
+			return -EIO;
+		}
+		ef->cmap.dirty = false;
+	}
+
+	return 0;
+}
+
+static bool set_next_cluster(const struct exfat* ef, bool contiguous,
+		cluster_t current, cluster_t next)
+{
+	off_t fat_offset;
+	le32_t next_le32;
+
+	if (contiguous)
+		return true;
+	fat_offset = s2o(ef, le32_to_cpu(ef->sb->fat_sector_start))
+		+ current * sizeof(cluster_t);
+	next_le32 = cpu_to_le32(next);
+	if (exfat_pwrite(ef->dev, &next_le32, sizeof(next_le32), fat_offset) < 0)
+	{
+		exfat_error("failed to write the next cluster %#x after %#x", next,
+				current);
+		return false;
+	}
+	return true;
+}
+
+static cluster_t allocate_cluster(struct exfat* ef, cluster_t hint)
+{
+	cluster_t cluster;
+
+	hint -= EXFAT_FIRST_DATA_CLUSTER;
+	if (hint >= ef->cmap.chunk_size)
+		hint = 0;
+
+	cluster = find_bit_and_set(ef->cmap.chunk, hint, ef->cmap.chunk_size);
+	if (cluster == EXFAT_CLUSTER_END)
+		cluster = find_bit_and_set(ef->cmap.chunk, 0, hint);
+	if (cluster == EXFAT_CLUSTER_END)
+	{
+		exfat_error("no free space left");
+		return EXFAT_CLUSTER_END;
+	}
+
+	ef->cmap.dirty = true;
+	return cluster;
+}
+
+static void free_cluster(struct exfat* ef, cluster_t cluster)
+{
+	if (cluster - EXFAT_FIRST_DATA_CLUSTER >= ef->cmap.size)
+		exfat_bug("caller must check cluster validity (%#x, %#x)", cluster,
+				ef->cmap.size);
+
+	BMAP_CLR(ef->cmap.chunk, cluster - EXFAT_FIRST_DATA_CLUSTER);
+	ef->cmap.dirty = true;
+}
+
+static bool make_noncontiguous(const struct exfat* ef, cluster_t first,
+		cluster_t last)
+{
+	cluster_t c;
+
+	for (c = first; c < last; c++)
+		if (!set_next_cluster(ef, false, c, c + 1))
+			return false;
+	return true;
+}
+
+static int shrink_file(struct exfat* ef, struct exfat_node* node,
+		uint32_t current, uint32_t difference);
+
+static int grow_file(struct exfat* ef, struct exfat_node* node,
+		uint32_t current, uint32_t difference)
+{
+	cluster_t previous;
+	cluster_t next;
+	uint32_t allocated = 0;
+
+	if (difference == 0)
+		exfat_bug("zero clusters count passed");
+
+	if (node->start_cluster != EXFAT_CLUSTER_FREE)
+	{
+		/* get the last cluster of the file */
+		previous = exfat_advance_cluster(ef, node, current - 1);
+		if (CLUSTER_INVALID(*ef->sb, previous))
+		{
+			exfat_error("invalid cluster 0x%x while growing", previous);
+			return -EIO;
+		}
+	}
+	else
+	{
+		if (node->fptr_index != 0)
+			exfat_bug("non-zero pointer index (%u)", node->fptr_index);
+		/* file does not have clusters (i.e. is empty), allocate
+		   the first one for it */
+		previous = allocate_cluster(ef, 0);
+		if (CLUSTER_INVALID(*ef->sb, previous))
+			return -ENOSPC;
+		node->fptr_cluster = node->start_cluster = previous;
+		allocated = 1;
+		/* file consists of only one cluster, so it's contiguous */
+		node->is_contiguous = true;
+	}
+
+	while (allocated < difference)
+	{
+		next = allocate_cluster(ef, previous + 1);
+		if (CLUSTER_INVALID(*ef->sb, next))
+		{
+			if (allocated != 0)
+				shrink_file(ef, node, current + allocated, allocated);
+			return -ENOSPC;
+		}
+		if (next != previous + 1 && node->is_contiguous)
+		{
+			/* it's a pity, but we are not able to keep the file contiguous
+			   anymore */
+			if (!make_noncontiguous(ef, node->start_cluster, previous))
+				return -EIO;
+			node->is_contiguous = false;
+			node->is_dirty = true;
+		}
+		if (!set_next_cluster(ef, node->is_contiguous, previous, next))
+			return -EIO;
+		previous = next;
+		allocated++;
+	}
+
+	if (!set_next_cluster(ef, node->is_contiguous, previous,
+			EXFAT_CLUSTER_END))
+		return -EIO;
+	return 0;
+}
+
+static int shrink_file(struct exfat* ef, struct exfat_node* node,
+		uint32_t current, uint32_t difference)
+{
+	cluster_t previous;
+	cluster_t next;
+
+	if (difference == 0)
+		exfat_bug("zero difference passed");
+	if (node->start_cluster == EXFAT_CLUSTER_FREE)
+		exfat_bug("unable to shrink empty file (%u clusters)", current);
+	if (current < difference)
+		exfat_bug("file underflow (%u < %u)", current, difference);
+
+	/* crop the file */
+	if (current > difference)
+	{
+		cluster_t last = exfat_advance_cluster(ef, node,
+				current - difference - 1);
+		if (CLUSTER_INVALID(*ef->sb, last))
+		{
+			exfat_error("invalid cluster 0x%x while shrinking", last);
+			return -EIO;
+		}
+		previous = exfat_next_cluster(ef, node, last);
+		if (!set_next_cluster(ef, node->is_contiguous, last,
+				EXFAT_CLUSTER_END))
+			return -EIO;
+	}
+	else
+	{
+		previous = node->start_cluster;
+		node->start_cluster = EXFAT_CLUSTER_FREE;
+		node->is_dirty = true;
+	}
+	node->fptr_index = 0;
+	node->fptr_cluster = node->start_cluster;
+
+	/* free remaining clusters */
+	while (difference--)
+	{
+		if (CLUSTER_INVALID(*ef->sb, previous))
+		{
+			exfat_error("invalid cluster 0x%x while freeing after shrink",
+					previous);
+			return -EIO;
+		}
+
+		next = exfat_next_cluster(ef, node, previous);
+		if (!set_next_cluster(ef, node->is_contiguous, previous,
+				EXFAT_CLUSTER_FREE))
+			return -EIO;
+		free_cluster(ef, previous);
+		previous = next;
+	}
+	return 0;
+}
+
+static bool erase_raw(struct exfat* ef, size_t size, off_t offset)
+{
+	if (exfat_pwrite(ef->dev, ef->zero_cluster, size, offset) < 0)
+	{
+		exfat_error("failed to erase %zu bytes at %"PRId64, size, offset);
+		return false;
+	}
+	return true;
+}
+
+static int erase_range(struct exfat* ef, struct exfat_node* node,
+		uint64_t begin, uint64_t end)
+{
+	uint64_t cluster_boundary;
+	cluster_t cluster;
+
+	if (begin >= end)
+		return 0;
+
+	cluster_boundary = (begin | (CLUSTER_SIZE(*ef->sb) - 1)) + 1;
+	cluster = exfat_advance_cluster(ef, node,
+			begin / CLUSTER_SIZE(*ef->sb));
+	if (CLUSTER_INVALID(*ef->sb, cluster))
+	{
+		exfat_error("invalid cluster 0x%x while erasing", cluster);
+		return -EIO;
+	}
+	/* erase from the beginning to the closest cluster boundary */
+	if (!erase_raw(ef, MIN(cluster_boundary, end) - begin,
+			exfat_c2o(ef, cluster) + begin % CLUSTER_SIZE(*ef->sb)))
+		return -EIO;
+	/* erase whole clusters */
+	while (cluster_boundary < end)
+	{
+		cluster = exfat_next_cluster(ef, node, cluster);
+		/* the cluster cannot be invalid because we have just allocated it */
+		if (CLUSTER_INVALID(*ef->sb, cluster))
+			exfat_bug("invalid cluster 0x%x after allocation", cluster);
+		if (!erase_raw(ef, CLUSTER_SIZE(*ef->sb), exfat_c2o(ef, cluster)))
+			return -EIO;
+		cluster_boundary += CLUSTER_SIZE(*ef->sb);
+	}
+	return 0;
+}
+
+int exfat_truncate(struct exfat* ef, struct exfat_node* node, uint64_t size,
+		bool erase)
+{
+	uint32_t c1 = bytes2clusters(ef, node->size);
+	uint32_t c2 = bytes2clusters(ef, size);
+	int rc = 0;
+
+	if (node->references == 0 && node->parent)
+		exfat_bug("no references, node changes can be lost");
+
+	if (node->size == size)
+		return 0;
+
+	if (c1 < c2)
+		rc = grow_file(ef, node, c1, c2 - c1);
+	else if (c1 > c2)
+		rc = shrink_file(ef, node, c1, c1 - c2);
+
+	if (rc != 0)
+		return rc;
+
+	if (erase)
+	{
+		rc = erase_range(ef, node, node->valid_size, size);
+		if (rc != 0)
+			return rc;
+		node->valid_size = size;
+	}
+	else
+	{
+		node->valid_size = MIN(node->valid_size, size);
+	}
+
+	exfat_update_mtime(node);
+	node->size = size;
+	node->is_dirty = true;
+	return 0;
+}
+
+uint32_t exfat_count_free_clusters(const struct exfat* ef)
+{
+	uint32_t free_clusters = 0;
+	uint32_t i;
+
+	for (i = 0; i < ef->cmap.size; i++)
+		if (BMAP_GET(ef->cmap.chunk, i) == 0)
+			free_clusters++;
+	return free_clusters;
+}
+
+static int find_used_clusters(const struct exfat* ef,
+		cluster_t* a, cluster_t* b)
+{
+	const cluster_t end = le32_to_cpu(ef->sb->cluster_count);
+
+	/* find first used cluster */
+	for (*a = *b + 1; *a < end; (*a)++)
+		if (BMAP_GET(ef->cmap.chunk, *a - EXFAT_FIRST_DATA_CLUSTER))
+			break;
+	if (*a >= end)
+		return 1;
+
+	/* find last contiguous used cluster */
+	for (*b = *a; *b < end; (*b)++)
+		if (BMAP_GET(ef->cmap.chunk, *b - EXFAT_FIRST_DATA_CLUSTER) == 0)
+		{
+			(*b)--;
+			break;
+		}
+
+	return 0;
+}
+
+int exfat_find_used_sectors(const struct exfat* ef, off_t* a, off_t* b)
+{
+	cluster_t ca, cb;
+
+	if (*a == 0 && *b == 0)
+		ca = cb = EXFAT_FIRST_DATA_CLUSTER - 1;
+	else
+	{
+		ca = s2c(ef, *a);
+		cb = s2c(ef, *b);
+	}
+	if (find_used_clusters(ef, &ca, &cb) != 0)
+		return 1;
+	if (*a != 0 || *b != 0)
+		*a = c2s(ef, ca);
+	*b = c2s(ef, cb) + (CLUSTER_SIZE(*ef->sb) - 1) / SECTOR_SIZE(*ef->sb);
+	return 0;
+}
diff --git a/fs/exfat/compiler.h b/fs/exfat/compiler.h
new file mode 100644
index 00000000000..48658280839
--- /dev/null
+++ b/fs/exfat/compiler.h
@@ -0,0 +1,69 @@
+/*
+	compiler.h (09.06.13)
+	Compiler-specific definitions. Note that unknown compiler is not a
+	showstopper.
+
+	Free exFAT implementation.
+	Copyright (C) 2010-2023  Andrew Nayenko
+
+	This program is free software; you can redistribute it and/or modify
+	it under the terms of the GNU General Public License as published by
+	the Free Software Foundation, either version 2 of the License, or
+	(at your option) any later version.
+
+	This program is distributed in the hope that it will be useful,
+	but WITHOUT ANY WARRANTY; without even the implied warranty of
+	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+	GNU General Public License for more details.
+
+	You should have received a copy of the GNU General Public License along
+	with this program; if not, write to the Free Software Foundation, Inc.,
+	51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+*/
+
+#ifndef COMPILER_H_INCLUDED
+#define COMPILER_H_INCLUDED
+
+#if __STDC_VERSION__ < 199901L
+#error C99-compliant compiler is required
+#endif
+
+#if defined(__clang__)
+
+#define PRINTF __attribute__((format(printf, 1, 2)))
+#define NORETURN __attribute__((noreturn))
+#define PACKED __attribute__((packed))
+#define UNUSED __attribute__((unused))
+#if __has_extension(c_static_assert)
+#define USE_C11_STATIC_ASSERT
+#endif
+
+#elif defined(__GNUC__)
+
+#define PRINTF __attribute__((format(printf, 1, 2)))
+#define NORETURN __attribute__((noreturn))
+#define PACKED __attribute__((packed))
+#define UNUSED __attribute__((unused))
+#if __GNUC__ > 4 || (__GNUC__ == 4 && __GNUC_MINOR__ >= 6)
+#define USE_C11_STATIC_ASSERT
+#endif
+
+#else
+
+#define PRINTF
+#define NORETURN
+#define PACKED
+#define UNUSED
+
+#endif
+
+#ifdef USE_C11_STATIC_ASSERT
+#define STATIC_ASSERT(cond) _Static_assert(cond, #cond)
+#else
+#define CONCAT2(a, b) a ## b
+#define CONCAT1(a, b) CONCAT2(a, b)
+#define STATIC_ASSERT(cond) \
+	extern void CONCAT1(static_assert, __LINE__)(int x[(cond) ? 1 : -1])
+#endif
+
+#endif /* ifndef COMPILER_H_INCLUDED */
diff --git a/fs/exfat/exfat.h b/fs/exfat/exfat.h
new file mode 100644
index 00000000000..cce3e3021ca
--- /dev/null
+++ b/fs/exfat/exfat.h
@@ -0,0 +1,259 @@
+/*
+	exfat.h (29.08.09)
+	Definitions of structures and constants used in exFAT file system
+	implementation.
+
+	Free exFAT implementation.
+	Copyright (C) 2010-2023  Andrew Nayenko
+
+	This program is free software; you can redistribute it and/or modify
+	it under the terms of the GNU General Public License as published by
+	the Free Software Foundation, either version 2 of the License, or
+	(at your option) any later version.
+
+	This program is distributed in the hope that it will be useful,
+	but WITHOUT ANY WARRANTY; without even the implied warranty of
+	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+	GNU General Public License for more details.
+
+	You should have received a copy of the GNU General Public License along
+	with this program; if not, write to the Free Software Foundation, Inc.,
+	51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+*/
+
+#ifndef EXFAT_H_INCLUDED
+#define EXFAT_H_INCLUDED
+
+#ifndef ANDROID
+/* Android.bp is used instead of autotools when targeting Android */
+#include "config.h"
+#endif
+#include "compiler.h"
+#include "exfatfs.h"
+#include <stdio.h>
+#include <stdlib.h>
+#include <time.h>
+#include <stdbool.h>
+#ifndef __UBOOT__
+#include <sys/stat.h>
+#include <sys/types.h>
+#endif
+
+#define EXFAT_NAME_MAX 255
+/* UTF-16 encodes code points up to U+FFFF as single 16-bit code units.
+   UTF-8 uses up to 3 bytes (i.e. 8-bit code units) to encode code points
+   up to U+FFFF. One additional character is for null terminator. */
+#define EXFAT_UTF8_NAME_BUFFER_MAX (EXFAT_NAME_MAX * 3 + 1)
+#define EXFAT_UTF8_ENAME_BUFFER_MAX (EXFAT_ENAME_MAX * 3 + 1)
+
+#define SECTOR_SIZE(sb) (1 << (sb).sector_bits)
+#define CLUSTER_SIZE(sb) (SECTOR_SIZE(sb) << (sb).spc_bits)
+#define CLUSTER_INVALID(sb, c) ((c) < EXFAT_FIRST_DATA_CLUSTER || \
+	(c) - EXFAT_FIRST_DATA_CLUSTER >= le32_to_cpu((sb).cluster_count))
+
+#define MIN(a, b) ((a) < (b) ? (a) : (b))
+#define MAX(a, b) ((a) > (b) ? (a) : (b))
+#ifndef __UBOOT__
+#define DIV_ROUND_UP(x, d) (((x) + (d) - 1) / (d))
+#endif
+#define ROUND_UP(x, d) (DIV_ROUND_UP(x, d) * (d))
+
+#define BMAP_SIZE(count) (ROUND_UP(count, sizeof(bitmap_t) * 8) / 8)
+#define BMAP_BLOCK(index) ((index) / sizeof(bitmap_t) / 8)
+#define BMAP_MASK(index) ((bitmap_t) 1 << ((index) % (sizeof(bitmap_t) * 8)))
+#define BMAP_GET(bitmap, index) \
+	((bitmap)[BMAP_BLOCK(index)] & BMAP_MASK(index))
+#define BMAP_SET(bitmap, index) \
+	((bitmap)[BMAP_BLOCK(index)] |= BMAP_MASK(index))
+#define BMAP_CLR(bitmap, index) \
+	((bitmap)[BMAP_BLOCK(index)] &= ~BMAP_MASK(index))
+
+#define EXFAT_REPAIR(hook, ef, ...) \
+	(exfat_ask_to_fix(ef) && exfat_fix_ ## hook(ef, __VA_ARGS__))
+
+/* The size of off_t type must be 64 bits. File systems larger than 2 GB will
+   be corrupted with 32-bit off_t. */
+STATIC_ASSERT(sizeof(off_t) == 8);
+
+struct exfat_node
+{
+	struct exfat_node* parent;
+	struct exfat_node* child;
+	struct exfat_node* next;
+	struct exfat_node* prev;
+
+	int references;
+	uint32_t fptr_index;
+	cluster_t fptr_cluster;
+	off_t entry_offset;
+	cluster_t start_cluster;
+	uint16_t attrib;
+	uint8_t continuations;
+	bool is_contiguous : 1;
+	bool is_cached : 1;
+	bool is_dirty : 1;
+	bool is_unlinked : 1;
+	uint64_t valid_size;
+	uint64_t size;
+	time_t mtime, atime;
+	le16_t name[EXFAT_NAME_MAX + 1];
+};
+
+enum exfat_mode
+{
+	EXFAT_MODE_RO,
+	EXFAT_MODE_RW,
+	EXFAT_MODE_ANY,
+};
+
+struct exfat_dev;
+
+struct exfat
+{
+	struct exfat_dev* dev;
+	struct exfat_super_block* sb;
+	uint16_t* upcase;
+	struct exfat_node* root;
+	struct
+	{
+		cluster_t start_cluster;
+		uint32_t size;				/* in bits */
+		bitmap_t* chunk;
+		uint32_t chunk_size;		/* in bits */
+		bool dirty;
+	}
+	cmap;
+	char label[EXFAT_UTF8_ENAME_BUFFER_MAX];
+	void* zero_cluster;
+	int dmask, fmask;
+	uid_t uid;
+	gid_t gid;
+	int ro;
+	bool noatime;
+	enum { EXFAT_REPAIR_NO, EXFAT_REPAIR_ASK, EXFAT_REPAIR_YES } repair;
+};
+
+/* in-core nodes iterator */
+struct exfat_iterator
+{
+	struct exfat_node* parent;
+	struct exfat_node* current;
+};
+
+struct exfat_human_bytes
+{
+	uint64_t value;
+	const char* unit;
+};
+
+extern int exfat_errors;
+extern int exfat_errors_fixed;
+
+#ifdef __UBOOT__
+#define exfat_bug(fmt, args...)		log_crit(fmt, ##args)
+#define exfat_error(fmt, args...)	log_err(fmt, ##args)
+#define exfat_warn(fmt, args...)	log_warning(fmt, ##args)
+#define exfat_debug(fmt, args...)	log_debug(fmt, ##args)
+#else
+void exfat_bug(const char* format, ...) PRINTF NORETURN;
+void exfat_error(const char* format, ...) PRINTF;
+void exfat_warn(const char* format, ...) PRINTF;
+void exfat_debug(const char* format, ...) PRINTF;
+#endif
+
+struct exfat_dev* exfat_open(const char* spec, enum exfat_mode mode);
+int exfat_close(struct exfat_dev* dev);
+int exfat_fsync(struct exfat_dev* dev);
+enum exfat_mode exfat_get_mode(const struct exfat_dev* dev);
+off_t exfat_get_size(const struct exfat_dev* dev);
+off_t exfat_seek(struct exfat_dev* dev, off_t offset, int whence);
+ssize_t exfat_read(struct exfat_dev* dev, void* buffer, size_t size);
+ssize_t exfat_write(struct exfat_dev* dev, const void* buffer, size_t size);
+ssize_t exfat_pread(struct exfat_dev* dev, void* buffer, size_t size,
+		off_t offset);
+ssize_t exfat_pwrite(struct exfat_dev* dev, const void* buffer, size_t size,
+		off_t offset);
+ssize_t exfat_generic_pread(const struct exfat* ef, struct exfat_node* node,
+		void* buffer, size_t size, off_t offset);
+ssize_t exfat_generic_pwrite(struct exfat* ef, struct exfat_node* node,
+		const void* buffer, size_t size, off_t offset);
+
+int exfat_opendir(struct exfat* ef, struct exfat_node* dir,
+		struct exfat_iterator* it);
+void exfat_closedir(struct exfat* ef, struct exfat_iterator* it);
+struct exfat_node* exfat_readdir(struct exfat_iterator* it);
+int exfat_lookup(struct exfat* ef, struct exfat_node** node,
+		const char* path);
+int exfat_split(struct exfat* ef, struct exfat_node** parent,
+		struct exfat_node** node, le16_t* name, const char* path);
+
+off_t exfat_c2o(const struct exfat* ef, cluster_t cluster);
+cluster_t exfat_next_cluster(const struct exfat* ef,
+		const struct exfat_node* node, cluster_t cluster);
+cluster_t exfat_advance_cluster(const struct exfat* ef,
+		struct exfat_node* node, uint32_t count);
+int exfat_flush_nodes(struct exfat* ef);
+int exfat_flush(struct exfat* ef);
+int exfat_truncate(struct exfat* ef, struct exfat_node* node, uint64_t size,
+		bool erase);
+uint32_t exfat_count_free_clusters(const struct exfat* ef);
+int exfat_find_used_sectors(const struct exfat* ef, off_t* a, off_t* b);
+
+void exfat_stat(const struct exfat* ef, const struct exfat_node* node,
+		struct stat* stbuf);
+void exfat_get_name(const struct exfat_node* node,
+		char buffer[EXFAT_UTF8_NAME_BUFFER_MAX]);
+uint16_t exfat_start_checksum(const struct exfat_entry_meta1* entry);
+uint16_t exfat_add_checksum(const void* entry, uint16_t sum);
+le16_t exfat_calc_checksum(const struct exfat_entry* entries, int n);
+uint32_t exfat_vbr_start_checksum(const void* sector, size_t size);
+uint32_t exfat_vbr_add_checksum(const void* sector, size_t size, uint32_t sum);
+le16_t exfat_calc_name_hash(const struct exfat* ef, const le16_t* name,
+		size_t length);
+void exfat_humanize_bytes(uint64_t value, struct exfat_human_bytes* hb);
+void exfat_print_info(const struct exfat_super_block* sb,
+		uint32_t free_clusters);
+bool exfat_match_option(const char* options, const char* option_name);
+
+int exfat_utf16_to_utf8(char* output, const le16_t* input, size_t outsize,
+		size_t insize);
+int exfat_utf8_to_utf16(le16_t* output, const char* input, size_t outsize,
+		size_t insize);
+size_t exfat_utf16_length(const le16_t* str);
+
+struct exfat_node* exfat_get_node(struct exfat_node* node);
+void exfat_put_node(struct exfat* ef, struct exfat_node* node);
+int exfat_cleanup_node(struct exfat* ef, struct exfat_node* node);
+int exfat_cache_directory(struct exfat* ef, struct exfat_node* dir);
+void exfat_reset_cache(struct exfat* ef);
+int exfat_flush_node(struct exfat* ef, struct exfat_node* node);
+int exfat_unlink(struct exfat* ef, struct exfat_node* node);
+int exfat_rmdir(struct exfat* ef, struct exfat_node* node);
+int exfat_mknod(struct exfat* ef, const char* path);
+int exfat_mkdir(struct exfat* ef, const char* path);
+int exfat_rename(struct exfat* ef, const char* old_path, const char* new_path);
+void exfat_utimes(struct exfat_node* node, const struct timespec tv[2]);
+void exfat_update_atime(struct exfat_node* node);
+void exfat_update_mtime(struct exfat_node* node);
+const char* exfat_get_label(struct exfat* ef);
+int exfat_set_label(struct exfat* ef, const char* label);
+
+int exfat_soil_super_block(const struct exfat* ef);
+int exfat_mount(struct exfat* ef, const char* spec, const char* options);
+void exfat_unmount(struct exfat* ef);
+
+time_t exfat_exfat2unix(le16_t date, le16_t time, uint8_t centisec,
+		uint8_t tzoffset);
+void exfat_unix2exfat(time_t unix_time, le16_t* date, le16_t* time,
+		uint8_t* centisec, uint8_t* tzoffset);
+void exfat_tzset(void);
+
+bool exfat_ask_to_fix(const struct exfat* ef);
+bool exfat_fix_invalid_vbr_checksum(const struct exfat* ef, void* sector,
+		uint32_t vbr_checksum);
+bool exfat_fix_invalid_node_checksum(const struct exfat* ef,
+		struct exfat_node* node);
+bool exfat_fix_unknown_entry(struct exfat* ef, struct exfat_node* dir,
+		const struct exfat_entry* entry, off_t offset);
+
+#endif /* ifndef EXFAT_H_INCLUDED */
diff --git a/fs/exfat/exfatfs.h b/fs/exfat/exfatfs.h
new file mode 100644
index 00000000000..fa59aab47b6
--- /dev/null
+++ b/fs/exfat/exfatfs.h
@@ -0,0 +1,200 @@
+/*
+	exfatfs.h (29.08.09)
+	Definitions of structures and constants used in exFAT file system.
+
+	Free exFAT implementation.
+	Copyright (C) 2010-2023  Andrew Nayenko
+
+	This program is free software; you can redistribute it and/or modify
+	it under the terms of the GNU General Public License as published by
+	the Free Software Foundation, either version 2 of the License, or
+	(at your option) any later version.
+
+	This program is distributed in the hope that it will be useful,
+	but WITHOUT ANY WARRANTY; without even the implied warranty of
+	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+	GNU General Public License for more details.
+
+	You should have received a copy of the GNU General Public License along
+	with this program; if not, write to the Free Software Foundation, Inc.,
+	51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+*/
+
+#ifndef EXFATFS_H_INCLUDED
+#define EXFATFS_H_INCLUDED
+
+#ifdef __UBOOT__
+#include <linux/stat.h>
+#include <linux/types.h>
+#include <log.h>
+#include <stdint.h>
+#include <vsprintf.h>
+
+struct timespec {
+	time_t	tv_sec;		/* seconds */
+	long	tv_nsec;	/* nanoseconds */
+};
+
+#define time(t)		1741234567	/* Thu Mar  6 05:16:07 CET 2025 */
+#define geteuid(n)	1000
+#define getegid(n)	1000
+#define strtol(n, e, b)	simple_strtol(n, e, b)
+#define off_t		unsigned long long
+#endif
+
+#include "byteorder.h"
+#include "compiler.h"
+
+typedef uint32_t cluster_t;		/* cluster number */
+
+#define EXFAT_FIRST_DATA_CLUSTER 2
+#define EXFAT_LAST_DATA_CLUSTER 0xfffffff6
+
+#define EXFAT_CLUSTER_FREE         0 /* free cluster */
+#define EXFAT_CLUSTER_BAD 0xfffffff7 /* cluster contains bad sector */
+#define EXFAT_CLUSTER_END 0xffffffff /* final cluster of file or directory */
+
+#define EXFAT_STATE_MOUNTED 2
+
+struct exfat_super_block
+{
+	uint8_t jump[3];				/* 0x00 jmp and nop instructions */
+	uint8_t oem_name[8];			/* 0x03 "EXFAT   " */
+	uint8_t	__unused1[53];			/* 0x0B always 0 */
+	le64_t sector_start;			/* 0x40 partition first sector */
+	le64_t sector_count;			/* 0x48 partition sectors count */
+	le32_t fat_sector_start;		/* 0x50 FAT first sector */
+	le32_t fat_sector_count;		/* 0x54 FAT sectors count */
+	le32_t cluster_sector_start;	/* 0x58 first cluster sector */
+	le32_t cluster_count;			/* 0x5C total clusters count */
+	le32_t rootdir_cluster;			/* 0x60 first cluster of the root dir */
+	le32_t volume_serial;			/* 0x64 volume serial number */
+	struct							/* 0x68 FS version */
+	{
+		uint8_t minor;
+		uint8_t major;
+	}
+	version;
+	le16_t volume_state;			/* 0x6A volume state flags */
+	uint8_t sector_bits;			/* 0x6C sector size as (1 << n) */
+	uint8_t spc_bits;				/* 0x6D sectors per cluster as (1 << n) */
+	uint8_t fat_count;				/* 0x6E always 1 */
+	uint8_t drive_no;				/* 0x6F always 0x80 */
+	uint8_t allocated_percent;		/* 0x70 percentage of allocated space */
+	uint8_t __unused2[397];			/* 0x71 always 0 */
+	le16_t boot_signature;			/* the value of 0xAA55 */
+}
+PACKED;
+STATIC_ASSERT(sizeof(struct exfat_super_block) == 512);
+
+#define EXFAT_ENTRY_VALID     0x80
+#define EXFAT_ENTRY_CONTINUED 0x40
+#define EXFAT_ENTRY_OPTIONAL  0x20
+
+#define EXFAT_ENTRY_BITMAP    (0x01 | EXFAT_ENTRY_VALID)
+#define EXFAT_ENTRY_UPCASE    (0x02 | EXFAT_ENTRY_VALID)
+#define EXFAT_ENTRY_LABEL     (0x03 | EXFAT_ENTRY_VALID)
+#define EXFAT_ENTRY_FILE      (0x05 | EXFAT_ENTRY_VALID)
+#define EXFAT_ENTRY_FILE_INFO (0x00 | EXFAT_ENTRY_VALID | EXFAT_ENTRY_CONTINUED)
+#define EXFAT_ENTRY_FILE_NAME (0x01 | EXFAT_ENTRY_VALID | EXFAT_ENTRY_CONTINUED)
+#define EXFAT_ENTRY_FILE_TAIL (0x00 | EXFAT_ENTRY_VALID \
+                                    | EXFAT_ENTRY_CONTINUED \
+                                    | EXFAT_ENTRY_OPTIONAL)
+
+struct exfat_entry					/* common container for all entries */
+{
+	uint8_t type;					/* any of EXFAT_ENTRY_xxx */
+	uint8_t data[31];
+}
+PACKED;
+STATIC_ASSERT(sizeof(struct exfat_entry) == 32);
+
+#define EXFAT_ENAME_MAX 15
+
+struct exfat_entry_bitmap			/* allocated clusters bitmap */
+{
+	uint8_t type;					/* EXFAT_ENTRY_BITMAP */
+	uint8_t __unknown1[19];
+	le32_t start_cluster;
+	le64_t size;					/* in bytes */
+}
+PACKED;
+STATIC_ASSERT(sizeof(struct exfat_entry_bitmap) == 32);
+
+#define EXFAT_UPCASE_CHARS 0x10000
+
+struct exfat_entry_upcase			/* upper case translation table */
+{
+	uint8_t type;					/* EXFAT_ENTRY_UPCASE */
+	uint8_t __unknown1[3];
+	le32_t checksum;
+	uint8_t __unknown2[12];
+	le32_t start_cluster;
+	le64_t size;					/* in bytes */
+}
+PACKED;
+STATIC_ASSERT(sizeof(struct exfat_entry_upcase) == 32);
+
+struct exfat_entry_label			/* volume label */
+{
+	uint8_t type;					/* EXFAT_ENTRY_LABEL */
+	uint8_t length;					/* number of characters */
+	le16_t name[EXFAT_ENAME_MAX];	/* in UTF-16LE */
+}
+PACKED;
+STATIC_ASSERT(sizeof(struct exfat_entry_label) == 32);
+
+#define EXFAT_ATTRIB_RO     0x01
+#define EXFAT_ATTRIB_HIDDEN 0x02
+#define EXFAT_ATTRIB_SYSTEM 0x04
+#define EXFAT_ATTRIB_VOLUME 0x08
+#define EXFAT_ATTRIB_DIR    0x10
+#define EXFAT_ATTRIB_ARCH   0x20
+
+struct exfat_entry_meta1			/* file or directory info (part 1) */
+{
+	uint8_t type;					/* EXFAT_ENTRY_FILE */
+	uint8_t continuations;
+	le16_t checksum;
+	le16_t attrib;					/* combination of EXFAT_ATTRIB_xxx */
+	le16_t __unknown1;
+	le16_t crtime, crdate;			/* creation date and time */
+	le16_t mtime, mdate;			/* latest modification date and time */
+	le16_t atime, adate;			/* latest access date and time */
+	uint8_t crtime_cs;				/* creation time in cs (centiseconds) */
+	uint8_t mtime_cs;				/* latest modification time in cs */
+	uint8_t crtime_tzo, mtime_tzo, atime_tzo;	/* timezone offset encoded */
+	uint8_t __unknown2[7];
+}
+PACKED;
+STATIC_ASSERT(sizeof(struct exfat_entry_meta1) == 32);
+
+#define EXFAT_FLAG_ALWAYS1		(1u << 0)
+#define EXFAT_FLAG_CONTIGUOUS	(1u << 1)
+
+struct exfat_entry_meta2			/* file or directory info (part 2) */
+{
+	uint8_t type;					/* EXFAT_ENTRY_FILE_INFO */
+	uint8_t flags;					/* combination of EXFAT_FLAG_xxx */
+	uint8_t __unknown1;
+	uint8_t name_length;
+	le16_t name_hash;
+	le16_t __unknown2;
+	le64_t valid_size;				/* in bytes, less or equal to size */
+	uint8_t __unknown3[4];
+	le32_t start_cluster;
+	le64_t size;					/* in bytes */
+}
+PACKED;
+STATIC_ASSERT(sizeof(struct exfat_entry_meta2) == 32);
+
+struct exfat_entry_name				/* file or directory name */
+{
+	uint8_t type;					/* EXFAT_ENTRY_FILE_NAME */
+	uint8_t __unknown;
+	le16_t name[EXFAT_ENAME_MAX];	/* in UTF-16LE */
+}
+PACKED;
+STATIC_ASSERT(sizeof(struct exfat_entry_name) == 32);
+
+#endif /* ifndef EXFATFS_H_INCLUDED */
diff --git a/fs/exfat/io.c b/fs/exfat/io.c
new file mode 100644
index 00000000000..81e82829c72
--- /dev/null
+++ b/fs/exfat/io.c
@@ -0,0 +1,1000 @@
+/*
+	io.c (02.09.09)
+	exFAT file system implementation library.
+
+	Free exFAT implementation.
+	Copyright (C) 2010-2023  Andrew Nayenko
+
+	This program is free software; you can redistribute it and/or modify
+	it under the terms of the GNU General Public License as published by
+	the Free Software Foundation, either version 2 of the License, or
+	(at your option) any later version.
+
+	This program is distributed in the hope that it will be useful,
+	but WITHOUT ANY WARRANTY; without even the implied warranty of
+	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+	GNU General Public License for more details.
+
+	You should have received a copy of the GNU General Public License along
+	with this program; if not, write to the Free Software Foundation, Inc.,
+	51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+*/
+
+#include "exfat.h"
+#include <inttypes.h>
+#ifndef __UBOOT__
+#include <sys/types.h>
+#include <sys/stat.h>
+#include <fcntl.h>
+#include <unistd.h>
+#include <string.h>
+#include <errno.h>
+#if defined(__APPLE__)
+#include <sys/disk.h>
+#elif defined(__OpenBSD__)
+#include <sys/param.h>
+#include <sys/disklabel.h>
+#include <sys/dkio.h>
+#include <sys/ioctl.h>
+#elif defined(__NetBSD__)
+#include <sys/ioctl.h>
+#elif __linux__
+#include <sys/mount.h>
+#endif
+#ifdef USE_UBLIO
+#include <sys/uio.h>
+#include <ublio.h>
+#endif
+#else
+#include <fs.h>
+#include <fs_internal.h>
+
+static struct exfat_ctxt {
+	struct disk_partition	cur_part_info;
+	struct blk_desc		*cur_dev;
+	struct exfat		ef;
+} ctxt;
+#endif
+
+struct exfat_dev
+{
+	int fd;
+	enum exfat_mode mode;
+	off_t size; /* in bytes */
+#ifdef USE_UBLIO
+	off_t pos;
+	ublio_filehandle_t ufh;
+#endif
+#ifdef __UBOOT__
+	struct exfat_ctxt *ctxt;
+#endif
+};
+
+#ifndef __UBOOT__
+static bool is_open(int fd)
+{
+	return fcntl(fd, F_GETFD) != -1;
+}
+
+static int open_ro(const char* spec)
+{
+	return open(spec, O_RDONLY);
+}
+
+static int open_rw(const char* spec)
+{
+	int fd = open(spec, O_RDWR);
+#ifdef __linux__
+	int ro = 0;
+
+	/*
+	   This ioctl is needed because after "blockdev --setro" kernel still
+	   allows to open the device in read-write mode but fails writes.
+	*/
+	if (fd != -1 && ioctl(fd, BLKROGET, &ro) == 0 && ro)
+	{
+		close(fd);
+		errno = EROFS;
+		return -1;
+	}
+#endif
+	return fd;
+}
+
+struct exfat_dev* exfat_open(const char* spec, enum exfat_mode mode)
+{
+	struct exfat_dev* dev;
+	struct stat stbuf;
+#ifdef USE_UBLIO
+	struct ublio_param up;
+#endif
+
+	/* The system allocates file descriptors sequentially. If we have been
+	   started with stdin (0), stdout (1) or stderr (2) closed, the system
+	   will give us descriptor 0, 1 or 2 later when we open block device,
+	   FUSE communication pipe, etc. As a result, functions using stdin,
+	   stdout or stderr will actually work with a different thing and can
+	   corrupt it. Protect descriptors 0, 1 and 2 from such misuse. */
+	while (!is_open(STDIN_FILENO)
+		|| !is_open(STDOUT_FILENO)
+		|| !is_open(STDERR_FILENO))
+	{
+		/* we don't need those descriptors, let them leak */
+		if (open("/dev/null", O_RDWR) == -1)
+		{
+			exfat_error("failed to open /dev/null");
+			return NULL;
+		}
+	}
+
+	dev = malloc(sizeof(struct exfat_dev));
+	if (dev == NULL)
+	{
+		exfat_error("failed to allocate memory for device structure");
+		return NULL;
+	}
+
+	switch (mode)
+	{
+	case EXFAT_MODE_RO:
+		dev->fd = open_ro(spec);
+		if (dev->fd == -1)
+		{
+			free(dev);
+			exfat_error("failed to open '%s' in read-only mode: %s", spec,
+					strerror(errno));
+			return NULL;
+		}
+		dev->mode = EXFAT_MODE_RO;
+		break;
+	case EXFAT_MODE_RW:
+		dev->fd = open_rw(spec);
+		if (dev->fd == -1)
+		{
+			free(dev);
+			exfat_error("failed to open '%s' in read-write mode: %s", spec,
+					strerror(errno));
+			return NULL;
+		}
+		dev->mode = EXFAT_MODE_RW;
+		break;
+	case EXFAT_MODE_ANY:
+		dev->fd = open_rw(spec);
+		if (dev->fd != -1)
+		{
+			dev->mode = EXFAT_MODE_RW;
+			break;
+		}
+		dev->fd = open_ro(spec);
+		if (dev->fd != -1)
+		{
+			dev->mode = EXFAT_MODE_RO;
+			exfat_warn("'%s' is write-protected, mounting read-only", spec);
+			break;
+		}
+		free(dev);
+		exfat_error("failed to open '%s': %s", spec, strerror(errno));
+		return NULL;
+	}
+
+	if (fstat(dev->fd, &stbuf) != 0)
+	{
+		close(dev->fd);
+		free(dev);
+		exfat_error("failed to fstat '%s'", spec);
+		return NULL;
+	}
+	if (!S_ISBLK(stbuf.st_mode) &&
+		!S_ISCHR(stbuf.st_mode) &&
+		!S_ISREG(stbuf.st_mode))
+	{
+		close(dev->fd);
+		free(dev);
+		exfat_error("'%s' is neither a device, nor a regular file", spec);
+		return NULL;
+	}
+
+#if defined(__APPLE__)
+	if (!S_ISREG(stbuf.st_mode))
+	{
+		uint32_t block_size = 0;
+		uint64_t blocks = 0;
+
+		if (ioctl(dev->fd, DKIOCGETBLOCKSIZE, &block_size) != 0)
+		{
+			close(dev->fd);
+			free(dev);
+			exfat_error("failed to get block size");
+			return NULL;
+		}
+		if (ioctl(dev->fd, DKIOCGETBLOCKCOUNT, &blocks) != 0)
+		{
+			close(dev->fd);
+			free(dev);
+			exfat_error("failed to get blocks count");
+			return NULL;
+		}
+		dev->size = blocks * block_size;
+	}
+	else
+#elif defined(__OpenBSD__)
+	if (!S_ISREG(stbuf.st_mode))
+	{
+		struct disklabel lab;
+		struct partition* pp;
+		char* partition;
+
+		if (ioctl(dev->fd, DIOCGDINFO, &lab) == -1)
+		{
+			close(dev->fd);
+			free(dev);
+			exfat_error("failed to get disklabel");
+			return NULL;
+		}
+
+		/* Don't need to check that partition letter is valid as we won't get
+		   this far otherwise. */
+		partition = strchr(spec, '\0') - 1;
+		pp = &(lab.d_partitions[*partition - 'a']);
+		dev->size = DL_GETPSIZE(pp) * lab.d_secsize;
+
+		if (pp->p_fstype != FS_NTFS)
+			exfat_warn("partition type is not 0x07 (NTFS/exFAT); "
+					"you can fix this with fdisk(8)");
+	}
+	else
+#elif defined(__NetBSD__)
+	if (!S_ISREG(stbuf.st_mode))
+	{
+		off_t size;
+
+		if (ioctl(dev->fd, DIOCGMEDIASIZE, &size) == -1)
+		{
+			close(dev->fd);
+			free(dev);
+			exfat_error("failed to get media size");
+			return NULL;
+		}
+		dev->size = size;
+	}
+	else
+#endif
+	{
+		/* works for Linux, FreeBSD, Solaris */
+		dev->size = exfat_seek(dev, 0, SEEK_END);
+		if (dev->size <= 0)
+		{
+			close(dev->fd);
+			free(dev);
+			exfat_error("failed to get size of '%s'", spec);
+			return NULL;
+		}
+		if (exfat_seek(dev, 0, SEEK_SET) == -1)
+		{
+			close(dev->fd);
+			free(dev);
+			exfat_error("failed to seek to the beginning of '%s'", spec);
+			return NULL;
+		}
+	}
+
+#ifdef USE_UBLIO
+	memset(&up, 0, sizeof(struct ublio_param));
+	up.up_blocksize = 256 * 1024;
+	up.up_items = 64;
+	up.up_grace = 32;
+	up.up_priv = &dev->fd;
+
+	dev->pos = 0;
+	dev->ufh = ublio_open(&up);
+	if (dev->ufh == NULL)
+	{
+		close(dev->fd);
+		free(dev);
+		exfat_error("failed to initialize ublio");
+		return NULL;
+	}
+#endif
+
+	return dev;
+}
+
+int exfat_close(struct exfat_dev* dev)
+{
+	int rc = 0;
+
+#ifdef USE_UBLIO
+	if (ublio_close(dev->ufh) != 0)
+	{
+		exfat_error("failed to close ublio");
+		rc = -EIO;
+	}
+#endif
+	if (close(dev->fd) != 0)
+	{
+		exfat_error("failed to close device: %s", strerror(errno));
+		rc = -EIO;
+	}
+	free(dev);
+	return rc;
+}
+
+int exfat_fsync(struct exfat_dev* dev)
+{
+	int rc = 0;
+
+#ifdef USE_UBLIO
+	if (ublio_fsync(dev->ufh) != 0)
+	{
+		exfat_error("ublio fsync failed");
+		rc = -EIO;
+	}
+#endif
+	if (fsync(dev->fd) != 0)
+	{
+		exfat_error("fsync failed: %s", strerror(errno));
+		rc = -EIO;
+	}
+	return rc;
+}
+
+enum exfat_mode exfat_get_mode(const struct exfat_dev* dev)
+{
+	return dev->mode;
+}
+
+off_t exfat_get_size(const struct exfat_dev* dev)
+{
+	return dev->size;
+}
+
+off_t exfat_seek(struct exfat_dev* dev, off_t offset, int whence)
+{
+#ifdef USE_UBLIO
+	/* XXX SEEK_CUR will be handled incorrectly */
+	return dev->pos = lseek(dev->fd, offset, whence);
+#else
+	return lseek(dev->fd, offset, whence);
+#endif
+}
+
+ssize_t exfat_read(struct exfat_dev* dev, void* buffer, size_t size)
+{
+#ifdef USE_UBLIO
+	ssize_t result = ublio_pread(dev->ufh, buffer, size, dev->pos);
+	if (result >= 0)
+		dev->pos += size;
+	return result;
+#else
+	return read(dev->fd, buffer, size);
+#endif
+}
+
+ssize_t exfat_write(struct exfat_dev* dev, const void* buffer, size_t size)
+{
+#ifdef USE_UBLIO
+	ssize_t result = ublio_pwrite(dev->ufh, (void*) buffer, size, dev->pos);
+	if (result >= 0)
+		dev->pos += size;
+	return result;
+#else
+	return write(dev->fd, buffer, size);
+#endif
+}
+
+ssize_t exfat_pread(struct exfat_dev* dev, void* buffer, size_t size,
+		off_t offset)
+{
+#ifdef USE_UBLIO
+	return ublio_pread(dev->ufh, buffer, size, offset);
+#else
+	return pread(dev->fd, buffer, size, offset);
+#endif
+}
+
+ssize_t exfat_pwrite(struct exfat_dev* dev, const void* buffer, size_t size,
+		off_t offset)
+{
+#ifdef USE_UBLIO
+	return ublio_pwrite(dev->ufh, (void*) buffer, size, offset);
+#else
+	return pwrite(dev->fd, buffer, size, offset);
+#endif
+}
+#else	/* U-Boot */
+struct exfat_dev* exfat_open(const char* spec, enum exfat_mode mode)
+{
+	struct exfat_dev* dev;
+
+	dev = malloc(sizeof(struct exfat_dev));
+	if (!dev) {
+		exfat_error("failed to allocate memory for device structure");
+		return NULL;
+	}
+	dev->mode = EXFAT_MODE_RW;
+	dev->size = ctxt.cur_part_info.size * ctxt.cur_part_info.blksz;
+	dev->ctxt = &ctxt;
+
+	return dev;
+}
+
+int exfat_close(struct exfat_dev* dev)
+{
+	free(dev);
+	return 0;
+}
+
+int exfat_fsync(struct exfat_dev* dev)
+{
+	return 0;
+}
+
+enum exfat_mode exfat_get_mode(const struct exfat_dev* dev)
+{
+	return dev->mode;
+}
+
+off_t exfat_get_size(const struct exfat_dev* dev)
+{
+	return dev->size;
+}
+
+ssize_t exfat_pread(struct exfat_dev* dev, void* buffer, size_t size,
+		off_t offset)
+{
+	lbaint_t sect = offset >> ctxt.cur_dev->log2blksz;
+	int off = offset & (ctxt.cur_dev->blksz - 1);
+
+	if (!ctxt.cur_dev)
+		return -EIO;
+
+	if (fs_devread(ctxt.cur_dev, &ctxt.cur_part_info, sect,
+		       off, size, buffer))
+		return 0;
+	return -EIO;
+}
+
+ssize_t exfat_pwrite(struct exfat_dev* dev, const void* buffer, size_t size,
+		off_t offset)
+{
+	lbaint_t sect = offset >> ctxt.cur_dev->log2blksz;
+	int off = offset & (ctxt.cur_dev->blksz - 1);
+
+	if (!ctxt.cur_dev)
+		return -EIO;
+
+	if (fs_devwrite(ctxt.cur_dev, &ctxt.cur_part_info, sect,
+		       off, size, buffer))
+		return 0;
+	return -EIO;
+}
+#endif
+
+ssize_t exfat_generic_pread(const struct exfat* ef, struct exfat_node* node,
+		void* buffer, size_t size, off_t offset)
+{
+	uint64_t uoffset = offset;
+	cluster_t cluster;
+	char* bufp = buffer;
+	off_t lsize, loffset, remainder;
+
+	if (offset < 0)
+		return -EINVAL;
+	if (uoffset >= node->size)
+		return 0;
+	if (size == 0)
+		return 0;
+
+	if (uoffset + size > node->valid_size)
+	{
+		ssize_t bytes = 0;
+
+		if (uoffset < node->valid_size)
+		{
+			bytes = exfat_generic_pread(ef, node, buffer,
+					node->valid_size - uoffset, offset);
+			if (bytes < 0 || (size_t) bytes < node->valid_size - uoffset)
+				return bytes;
+		}
+		memset(buffer + bytes, 0,
+				MIN(size - bytes, node->size - node->valid_size));
+		return MIN(size, node->size - uoffset);
+	}
+
+	cluster = exfat_advance_cluster(ef, node, uoffset / CLUSTER_SIZE(*ef->sb));
+	if (CLUSTER_INVALID(*ef->sb, cluster))
+	{
+		exfat_error("invalid cluster 0x%x while reading", cluster);
+		return -EIO;
+	}
+
+	loffset = uoffset % CLUSTER_SIZE(*ef->sb);
+	remainder = MIN(size, node->size - uoffset);
+	while (remainder > 0)
+	{
+		if (CLUSTER_INVALID(*ef->sb, cluster))
+		{
+			exfat_error("invalid cluster 0x%x while reading", cluster);
+			return -EIO;
+		}
+		lsize = MIN(CLUSTER_SIZE(*ef->sb) - loffset, remainder);
+		if (exfat_pread(ef->dev, bufp, lsize,
+					exfat_c2o(ef, cluster) + loffset) < 0)
+		{
+			exfat_error("failed to read cluster %#x", cluster);
+			return -EIO;
+		}
+		bufp += lsize;
+		loffset = 0;
+		remainder -= lsize;
+		cluster = exfat_next_cluster(ef, node, cluster);
+	}
+	if (!(node->attrib & EXFAT_ATTRIB_DIR) && !ef->ro && !ef->noatime)
+		exfat_update_atime(node);
+	return MIN(size, node->size - uoffset) - remainder;
+}
+
+ssize_t exfat_generic_pwrite(struct exfat* ef, struct exfat_node* node,
+		const void* buffer, size_t size, off_t offset)
+{
+	uint64_t uoffset = offset;
+	int rc;
+	cluster_t cluster;
+	const char* bufp = buffer;
+	off_t lsize, loffset, remainder;
+
+	if (offset < 0)
+		return -EINVAL;
+	if (uoffset > node->size)
+	{
+		rc = exfat_truncate(ef, node, uoffset, true);
+		if (rc != 0)
+			return rc;
+	}
+	if (uoffset + size > node->size)
+	{
+		rc = exfat_truncate(ef, node, uoffset + size, false);
+		if (rc != 0)
+			return rc;
+	}
+	if (size == 0)
+		return 0;
+
+	cluster = exfat_advance_cluster(ef, node, uoffset / CLUSTER_SIZE(*ef->sb));
+	if (CLUSTER_INVALID(*ef->sb, cluster))
+	{
+		exfat_error("invalid cluster 0x%x while writing", cluster);
+		return -EIO;
+	}
+
+	loffset = uoffset % CLUSTER_SIZE(*ef->sb);
+	remainder = size;
+	while (remainder > 0)
+	{
+		if (CLUSTER_INVALID(*ef->sb, cluster))
+		{
+			exfat_error("invalid cluster 0x%x while writing", cluster);
+			return -EIO;
+		}
+		lsize = MIN(CLUSTER_SIZE(*ef->sb) - loffset, remainder);
+		if (exfat_pwrite(ef->dev, bufp, lsize,
+				exfat_c2o(ef, cluster) + loffset) < 0)
+		{
+			exfat_error("failed to write cluster %#x", cluster);
+			return -EIO;
+		}
+		bufp += lsize;
+		loffset = 0;
+		remainder -= lsize;
+		node->valid_size = MAX(node->valid_size, uoffset + size - remainder);
+		cluster = exfat_next_cluster(ef, node, cluster);
+	}
+	if (!(node->attrib & EXFAT_ATTRIB_DIR))
+		/* directory's mtime should be updated by the caller only when it
+		   creates or removes something in this directory */
+		exfat_update_mtime(node);
+	return size - remainder;
+}
+
+#ifdef __UBOOT__
+struct exfat_dir_stream {
+	struct fs_dir_stream fs_dirs;
+	struct fs_dirent dirent;
+
+	struct exfat_node* node;
+	struct exfat_iterator it;
+	/* State tracker flags for emulated . and .. dirents */
+	bool dot;
+	bool dotdot;
+};
+
+int exfat_fs_probe(struct blk_desc *fs_dev_desc,
+		struct disk_partition *fs_partition)
+{
+	int ret;
+
+	ctxt.cur_dev = fs_dev_desc;
+	ctxt.cur_part_info = *fs_partition;
+
+	ret = exfat_mount(&ctxt.ef, NULL, "");
+	if (ret)
+		goto error;
+
+	return 0;
+error:
+	ctxt.cur_dev = NULL;
+	return ret;
+}
+
+#define PATH_MAX FS_DIRENT_NAME_LEN
+
+/* Adapted from uclibc 1.0.35 */
+static char *exfat_realpath(const char *path, char got_path[])
+{
+	char copy_path[PATH_MAX];
+	char *max_path, *new_path;
+	size_t path_len;
+
+	if (path == NULL)
+		return NULL;
+
+	if (*path == '\0')
+		return NULL;
+
+	/* Make a copy of the source path since we may need to modify it. */
+	path_len = strlen(path);
+	if (path_len >= PATH_MAX - 2)
+		return NULL;
+
+	/* Copy so that path is at the end of copy_path[] */
+	strcpy(copy_path + (PATH_MAX-1) - path_len, path);
+	path = copy_path + (PATH_MAX-1) - path_len;
+	max_path = got_path + PATH_MAX - 2; /* points to last non-NUL char */
+	new_path = got_path;
+	*new_path++ = '/';
+	path++;
+
+	/* Expand each slash-separated pathname component. */
+	while (*path != '\0') {
+		/* Ignore stray "/". */
+		if (*path == '/') {
+			path++;
+			continue;
+		}
+
+		if (*path == '.') {
+			/* Ignore ".". */
+			if (path[1] == '\0' || path[1] == '/') {
+				path++;
+				continue;
+			}
+
+			if (path[1] == '.') {
+				if (path[2] == '\0' || path[2] == '/') {
+					path += 2;
+					/* Ignore ".." at root. */
+					if (new_path == got_path + 1)
+						continue;
+					/* Handle ".." by backing up. */
+					while ((--new_path)[-1] != '/')
+						;
+					continue;
+				}
+			}
+		}
+
+		/* Safely copy the next pathname component. */
+		while (*path != '\0' && *path != '/') {
+			if (new_path > max_path)
+				return NULL;
+			*new_path++ = *path++;
+		}
+
+		*new_path++ = '/';
+	}
+
+	/* Delete trailing slash but don't whomp a lone slash. */
+	if (new_path != got_path + 1 && new_path[-1] == '/')
+		new_path--;
+
+	/* Make sure it's null terminated. */
+	*new_path = '\0';
+	return got_path;
+}
+
+int exfat_lookup_realpath(struct exfat* ef, struct exfat_node** node,
+			  const char* path)
+{
+	char input_path[FS_DIRENT_NAME_LEN];
+	char real_path[FS_DIRENT_NAME_LEN];
+	char *name;
+
+	/* Input is always absolute path */
+	snprintf(input_path, FS_DIRENT_NAME_LEN, "/%s", path);
+	name = exfat_realpath(input_path, real_path);
+	if (!name)
+		return -EINVAL;
+
+	return exfat_lookup(ef, node, real_path);
+}
+
+int exfat_fs_opendir(const char *filename, struct fs_dir_stream **dirsp)
+{
+	struct exfat_dir_stream *dirs;
+	int err;
+
+	dirs = calloc(1, sizeof(*dirs));
+	if (!dirs)
+		return -ENOMEM;
+
+	err = exfat_lookup_realpath(&ctxt.ef, &dirs->node, filename);
+	if (err)
+		goto err_out;
+
+	if (!(dirs->node->attrib & EXFAT_ATTRIB_DIR)) {
+		err = -ENOTDIR;
+		goto err_out;
+	}
+
+	err = exfat_opendir(&ctxt.ef, dirs->node, &dirs->it);
+	if (err)
+		goto err_out;
+
+	*dirsp = &dirs->fs_dirs;
+
+	return 0;
+err_out:
+	free(dirs);
+	return err;
+}
+
+int exfat_fs_readdir(struct fs_dir_stream *fs_dirs, struct fs_dirent **dentp)
+{
+	struct exfat_dir_stream *dirs =
+		container_of(fs_dirs, struct exfat_dir_stream, fs_dirs);
+	struct fs_dirent *dent = &dirs->dirent;
+	struct exfat_node* node;
+
+	/* Emulate current directory ./ */
+	if (!dirs->dot) {
+		dirs->dot = true;
+		snprintf(dent->name, FS_DIRENT_NAME_LEN, ".");
+		dent->type = FS_DT_DIR;
+		*dentp = dent;
+		return 0;
+	}
+
+	/* Emulate parent directory ../ */
+	if (!dirs->dotdot) {
+		dirs->dotdot = true;
+		snprintf(dent->name, FS_DIRENT_NAME_LEN, "..");
+		dent->type = FS_DT_DIR;
+		*dentp = dent;
+		return 0;
+	}
+
+	/* Read actual directory content */
+	node = exfat_readdir(&dirs->it);
+	if (!node) {	/* No more content, reset . and .. emulation */
+		dirs->dot = false;
+		dirs->dotdot = false;
+		return 1;
+	}
+
+	exfat_get_name(node, dent->name);
+	if (node->attrib & EXFAT_ATTRIB_DIR) {
+		dent->type = FS_DT_DIR;
+	} else {
+		dent->type = FS_DT_REG;
+		dent->size = node->size;
+	}
+
+	*dentp = dent;
+
+	return 0;
+}
+
+void exfat_fs_closedir(struct fs_dir_stream *fs_dirs)
+{
+	free(fs_dirs);
+}
+
+int exfat_fs_ls(const char *dirname)
+{
+	struct exfat_node *dnode, *node;
+	char name[FS_DIRENT_NAME_LEN];
+	int nfiles = 0, ndirs = 2;
+	struct exfat_iterator it;
+	int err;
+
+	err = exfat_lookup_realpath(&ctxt.ef, &dnode, dirname);
+	if (err)
+		return err;
+
+	if (!(dnode->attrib & EXFAT_ATTRIB_DIR)) {
+		err = -ENOTDIR;
+		goto err_out;
+	}
+
+	err = exfat_opendir(&ctxt.ef, dnode, &it);
+	if (err)
+		goto err_out;
+
+	printf("            ./\n");
+	printf("            ../\n");
+
+	/* Read actual directory content */
+	while ((node = exfat_readdir(&it))) {
+		exfat_get_name(node, name);
+		if (node->attrib & EXFAT_ATTRIB_DIR) {
+			printf("            %s/\n", name);
+			ndirs++;
+		} else {
+			printf(" %8lld   %s\n", node->size, name);
+			nfiles++;
+		}
+		exfat_put_node(&ctxt.ef, node);
+	}
+
+	printf("\n%d file(s), %d dir(s)\n\n", nfiles, ndirs);
+
+	exfat_closedir(&ctxt.ef, &it);
+
+err_out:
+	exfat_put_node(&ctxt.ef, dnode);
+	return err;
+}
+
+int exfat_fs_exists(const char *filename)
+{
+	struct exfat_node* node;
+	int err;
+
+	err = exfat_lookup_realpath(&ctxt.ef, &node, filename);
+	if (err)
+		return err;
+
+	exfat_put_node(&ctxt.ef, node);
+
+	return 0;
+}
+
+int exfat_fs_size(const char *filename, loff_t *size)
+{
+	struct exfat_node* node;
+	int err;
+
+	err = exfat_lookup_realpath(&ctxt.ef, &node, filename);
+	if (err)
+		return err;
+
+	*size = node->size;
+
+	exfat_put_node(&ctxt.ef, node);
+
+	return 0;
+}
+
+int exfat_fs_read(const char *filename, void *buf, loff_t offset, loff_t len,
+	       loff_t *actread)
+{
+	struct exfat_node* node;
+	ssize_t sz;
+	int err;
+
+	err = exfat_lookup_realpath(&ctxt.ef, &node, filename);
+	if (err)
+		return err;
+
+	if (!len)
+		len = node->size;
+
+	sz = exfat_generic_pread(&ctxt.ef, node, buf, len, offset);
+	if (sz < 0) {
+		*actread = 0;
+		err = -EINVAL;
+		goto exit;
+	}
+
+	*actread = sz;
+
+	exfat_put_node(&ctxt.ef, node);
+
+	return exfat_flush_node(&ctxt.ef, node);
+exit:
+	exfat_put_node(&ctxt.ef, node);
+	return err;
+}
+
+int exfat_fs_unlink(const char *filename)
+{
+	struct exfat_node* node;
+	int err;
+
+	err = exfat_lookup_realpath(&ctxt.ef, &node, filename);
+	if (err) {
+		printf("%s: doesn't exist (%d)\n", filename, err);
+		return err;
+	}
+
+	if (node->attrib & EXFAT_ATTRIB_DIR) {
+		err = exfat_rmdir(&ctxt.ef, node);
+		if (err == -ENOTEMPTY)
+			printf("Error: directory is not empty: %d\n", err);
+	} else {
+		err = exfat_unlink(&ctxt.ef, node);
+	}
+
+	if (err)
+		goto exit;
+
+	exfat_put_node(&ctxt.ef, node);
+
+	return exfat_cleanup_node(&ctxt.ef, node);
+exit:
+	exfat_put_node(&ctxt.ef, node);
+	return err;
+}
+
+int exfat_fs_mkdir(const char *dirname)
+{
+	if (!strcmp(dirname, ".") || !strcmp(dirname, ".."))
+		return -EINVAL;
+
+	return exfat_mkdir(&ctxt.ef, dirname);
+}
+
+int exfat_fs_write(const char *filename, void *buf, loff_t offset,
+		   loff_t len, loff_t *actwrite)
+{
+	struct exfat_node* node;
+	ssize_t sz;
+	int err;
+
+	/*
+	 * Ignore -EEXIST error here, if the file exists,
+	 * this write should act as an append to offset.
+	 */
+	err = exfat_mknod(&ctxt.ef, filename);
+	if (err && err != -EEXIST)
+		return err;
+
+	err = exfat_lookup_realpath(&ctxt.ef, &node, filename);
+	if (err)
+		return err;
+
+	/* Write into directories is not allowed. */
+	if (node->attrib & EXFAT_ATTRIB_DIR)
+		return -EISDIR;
+
+	/* Write past end of file is not allowed. */
+	if (offset > node->size) {
+		err = -EINVAL;
+		goto exit;
+	}
+
+	sz = exfat_generic_pwrite(&ctxt.ef, node, buf, len, offset);
+	if (sz < 0) {
+		*actwrite = 0;
+		err = -EINVAL;
+		goto exit;
+	}
+
+	err = exfat_truncate(&ctxt.ef, node, offset + sz, false);
+	if (err)
+		goto exit;
+
+	*actwrite = sz;
+
+	err = exfat_flush_node(&ctxt.ef, node);
+exit:
+	exfat_put_node(&ctxt.ef, node);
+	return err;
+}
+
+void exfat_fs_close(void)
+{
+	exfat_unmount(&ctxt.ef);
+	ctxt.cur_dev = NULL;
+}
+#endif	/* __U_BOOT__ */
diff --git a/fs/exfat/lookup.c b/fs/exfat/lookup.c
new file mode 100644
index 00000000000..9867aab95f3
--- /dev/null
+++ b/fs/exfat/lookup.c
@@ -0,0 +1,225 @@
+/*
+	lookup.c (02.09.09)
+	exFAT file system implementation library.
+
+	Free exFAT implementation.
+	Copyright (C) 2010-2023  Andrew Nayenko
+
+	This program is free software; you can redistribute it and/or modify
+	it under the terms of the GNU General Public License as published by
+	the Free Software Foundation, either version 2 of the License, or
+	(at your option) any later version.
+
+	This program is distributed in the hope that it will be useful,
+	but WITHOUT ANY WARRANTY; without even the implied warranty of
+	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+	GNU General Public License for more details.
+
+	You should have received a copy of the GNU General Public License along
+	with this program; if not, write to the Free Software Foundation, Inc.,
+	51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+*/
+
+#include "exfat.h"
+#include <string.h>
+#include <errno.h>
+#include <inttypes.h>
+
+int exfat_opendir(struct exfat* ef, struct exfat_node* dir,
+		struct exfat_iterator* it)
+{
+	int rc;
+
+	exfat_get_node(dir);
+	it->parent = dir;
+	it->current = NULL;
+	rc = exfat_cache_directory(ef, dir);
+	if (rc != 0)
+		exfat_put_node(ef, dir);
+	return rc;
+}
+
+void exfat_closedir(struct exfat* ef, struct exfat_iterator* it)
+{
+	exfat_put_node(ef, it->parent);
+	it->parent = NULL;
+	it->current = NULL;
+}
+
+struct exfat_node* exfat_readdir(struct exfat_iterator* it)
+{
+	if (it->current == NULL)
+		it->current = it->parent->child;
+	else
+		it->current = it->current->next;
+
+	if (it->current != NULL)
+		return exfat_get_node(it->current);
+	else
+		return NULL;
+}
+
+static int compare_char(struct exfat* ef, uint16_t a, uint16_t b)
+{
+	return (int) ef->upcase[a] - (int) ef->upcase[b];
+}
+
+static int compare_name(struct exfat* ef, const le16_t* a, const le16_t* b)
+{
+	while (le16_to_cpu(*a) && le16_to_cpu(*b))
+	{
+		int rc = compare_char(ef, le16_to_cpu(*a), le16_to_cpu(*b));
+		if (rc != 0)
+			return rc;
+		a++;
+		b++;
+	}
+	return compare_char(ef, le16_to_cpu(*a), le16_to_cpu(*b));
+}
+
+static int lookup_name(struct exfat* ef, struct exfat_node* parent,
+		struct exfat_node** node, const char* name, size_t n)
+{
+	struct exfat_iterator it;
+	le16_t buffer[EXFAT_NAME_MAX + 1];
+	int rc;
+
+	*node = NULL;
+
+	rc = exfat_utf8_to_utf16(buffer, name, EXFAT_NAME_MAX + 1, n);
+	if (rc != 0)
+		return rc;
+
+	rc = exfat_opendir(ef, parent, &it);
+	if (rc != 0)
+		return rc;
+	while ((*node = exfat_readdir(&it)))
+	{
+		if (compare_name(ef, buffer, (*node)->name) == 0)
+		{
+			exfat_closedir(ef, &it);
+			return 0;
+		}
+		exfat_put_node(ef, *node);
+	}
+	exfat_closedir(ef, &it);
+	return -ENOENT;
+}
+
+static size_t get_comp(const char* path, const char** comp)
+{
+	const char* end;
+
+	*comp = path + strspn(path, "/");				/* skip leading slashes */
+	end = strchr(*comp, '/');
+	if (end == NULL)
+		return strlen(*comp);
+	else
+		return end - *comp;
+}
+
+int exfat_lookup(struct exfat* ef, struct exfat_node** node,
+		const char* path)
+{
+	struct exfat_node* parent;
+	const char* p;
+	size_t n;
+	int rc;
+
+	/* start from the root directory */
+	parent = *node = exfat_get_node(ef->root);
+	for (p = path; (n = get_comp(p, &p)); p += n)
+	{
+		if (n == 1 && *p == '.')				/* skip "." component */
+			continue;
+		rc = lookup_name(ef, parent, node, p, n);
+		if (rc != 0)
+		{
+			exfat_put_node(ef, parent);
+			return rc;
+		}
+		exfat_put_node(ef, parent);
+		parent = *node;
+	}
+	return 0;
+}
+
+static bool is_last_comp(const char* comp, size_t length)
+{
+	const char* p = comp + length;
+
+	return get_comp(p, &p) == 0;
+}
+
+static bool is_allowed(const char* comp, size_t length)
+{
+	size_t i;
+
+	for (i = 0; i < length; i++)
+		switch (comp[i])
+		{
+		case 0x01 ... 0x1f:
+		case '/':
+		case '\\':
+		case ':':
+		case '*':
+		case '?':
+		case '"':
+		case '<':
+		case '>':
+		case '|':
+			return false;
+		}
+	return true;
+}
+
+int exfat_split(struct exfat* ef, struct exfat_node** parent,
+		struct exfat_node** node, le16_t* name, const char* path)
+{
+	const char* p;
+	size_t n;
+	int rc;
+
+	memset(name, 0, (EXFAT_NAME_MAX + 1) * sizeof(le16_t));
+	*parent = *node = exfat_get_node(ef->root);
+	for (p = path; (n = get_comp(p, &p)); p += n)
+	{
+		if (n == 1 && *p == '.')
+			continue;
+		if (is_last_comp(p, n))
+		{
+			if (!is_allowed(p, n))
+			{
+				/* contains characters that are not allowed */
+				exfat_put_node(ef, *parent);
+				return -ENOENT;
+			}
+			rc = exfat_utf8_to_utf16(name, p, EXFAT_NAME_MAX + 1, n);
+			if (rc != 0)
+			{
+				exfat_put_node(ef, *parent);
+				return rc;
+			}
+
+			rc = lookup_name(ef, *parent, node, p, n);
+			if (rc != 0 && rc != -ENOENT)
+			{
+				exfat_put_node(ef, *parent);
+				return rc;
+			}
+			return 0;
+		}
+		rc = lookup_name(ef, *parent, node, p, n);
+		if (rc != 0)
+		{
+			exfat_put_node(ef, *parent);
+			return rc;
+		}
+		exfat_put_node(ef, *parent);
+		*parent = *node;
+	}
+	exfat_bug("impossible");
+#ifdef __UBOOT__
+	return 0;
+#endif
+}
diff --git a/fs/exfat/mount.c b/fs/exfat/mount.c
new file mode 100644
index 00000000000..0ff297af67b
--- /dev/null
+++ b/fs/exfat/mount.c
@@ -0,0 +1,380 @@
+/*
+	mount.c (22.10.09)
+	exFAT file system implementation library.
+
+	Free exFAT implementation.
+	Copyright (C) 2010-2023  Andrew Nayenko
+
+	This program is free software; you can redistribute it and/or modify
+	it under the terms of the GNU General Public License as published by
+	the Free Software Foundation, either version 2 of the License, or
+	(at your option) any later version.
+
+	This program is distributed in the hope that it will be useful,
+	but WITHOUT ANY WARRANTY; without even the implied warranty of
+	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+	GNU General Public License for more details.
+
+	You should have received a copy of the GNU General Public License along
+	with this program; if not, write to the Free Software Foundation, Inc.,
+	51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+*/
+
+#include "exfat.h"
+#include <string.h>
+#include <stdlib.h>
+#include <errno.h>
+#include <inttypes.h>
+#ifndef __UBOOT__
+#include <unistd.h>
+#include <sys/types.h>
+#endif
+
+static uint64_t rootdir_size(const struct exfat* ef)
+{
+	uint32_t clusters = 0;
+	uint32_t clusters_max = le32_to_cpu(ef->sb->cluster_count);
+	cluster_t rootdir_cluster = le32_to_cpu(ef->sb->rootdir_cluster);
+
+	/* Iterate all clusters of the root directory to calculate its size.
+	   It can't be contiguous because there is no flag to indicate this. */
+	do
+	{
+		if (clusters == clusters_max) /* infinite loop detected */
+		{
+			exfat_error("root directory cannot occupy all %d clusters",
+					clusters);
+			return 0;
+		}
+		if (CLUSTER_INVALID(*ef->sb, rootdir_cluster))
+		{
+			exfat_error("bad cluster %#x while reading root directory",
+					rootdir_cluster);
+			return 0;
+		}
+		rootdir_cluster = exfat_next_cluster(ef, ef->root, rootdir_cluster);
+		clusters++;
+	}
+	while (rootdir_cluster != EXFAT_CLUSTER_END);
+
+	return (uint64_t) clusters * CLUSTER_SIZE(*ef->sb);
+}
+
+static const char* get_option(const char* options, const char* option_name)
+{
+	const char* p;
+	size_t length = strlen(option_name);
+
+	for (p = strstr(options, option_name); p; p = strstr(p + 1, option_name))
+		if ((p == options || p[-1] == ',') && p[length] == '=')
+			return p + length + 1;
+	return NULL;
+}
+
+static int get_int_option(const char* options, const char* option_name,
+		int base, int default_value)
+{
+	const char* p = get_option(options, option_name);
+
+	if (p == NULL)
+		return default_value;
+	return strtol(p, NULL, base);
+}
+
+static void parse_options(struct exfat* ef, const char* options)
+{
+	int opt_umask;
+
+	opt_umask = get_int_option(options, "umask", 8, 0);
+	ef->dmask = get_int_option(options, "dmask", 8, opt_umask);
+	ef->fmask = get_int_option(options, "fmask", 8, opt_umask);
+
+	ef->uid = get_int_option(options, "uid", 10, geteuid());
+	ef->gid = get_int_option(options, "gid", 10, getegid());
+
+	ef->noatime = exfat_match_option(options, "noatime");
+
+	switch (get_int_option(options, "repair", 10, 0))
+	{
+	case 1:
+		ef->repair = EXFAT_REPAIR_ASK;
+		break;
+	case 2:
+		ef->repair = EXFAT_REPAIR_YES;
+		break;
+	default:
+		ef->repair = EXFAT_REPAIR_NO;
+		break;
+	}
+}
+
+static bool verify_vbr_checksum(const struct exfat* ef, void* sector)
+{
+	off_t sector_size = SECTOR_SIZE(*ef->sb);
+	uint32_t vbr_checksum;
+	size_t i;
+
+	if (exfat_pread(ef->dev, sector, sector_size, 0) < 0)
+	{
+		exfat_error("failed to read boot sector");
+		return false;
+	}
+	vbr_checksum = exfat_vbr_start_checksum(sector, sector_size);
+	for (i = 1; i < 11; i++)
+	{
+		if (exfat_pread(ef->dev, sector, sector_size, i * sector_size) < 0)
+		{
+			exfat_error("failed to read VBR sector");
+			return false;
+		}
+		vbr_checksum = exfat_vbr_add_checksum(sector, sector_size,
+				vbr_checksum);
+	}
+	if (exfat_pread(ef->dev, sector, sector_size, i * sector_size) < 0)
+	{
+		exfat_error("failed to read VBR checksum sector");
+		return false;
+	}
+	for (i = 0; i < sector_size / sizeof(vbr_checksum); i++)
+		if (le32_to_cpu(((const le32_t*) sector)[i]) != vbr_checksum)
+		{
+			exfat_error("invalid VBR checksum 0x%x (expected 0x%x)",
+					le32_to_cpu(((const le32_t*) sector)[i]), vbr_checksum);
+			if (!EXFAT_REPAIR(invalid_vbr_checksum, ef, sector, vbr_checksum))
+				return false;
+		}
+	return true;
+}
+
+static int commit_super_block(const struct exfat* ef)
+{
+	if (exfat_pwrite(ef->dev, ef->sb, sizeof(struct exfat_super_block), 0) < 0)
+	{
+		exfat_error("failed to write super block");
+		return 1;
+	}
+	return exfat_fsync(ef->dev);
+}
+
+int exfat_soil_super_block(const struct exfat* ef)
+{
+	if (ef->ro)
+		return 0;
+
+	ef->sb->volume_state = cpu_to_le16(
+			le16_to_cpu(ef->sb->volume_state) | EXFAT_STATE_MOUNTED);
+	return commit_super_block(ef);
+}
+
+static void exfat_free(struct exfat* ef)
+{
+	exfat_close(ef->dev);	/* first of all, close the descriptor */
+	ef->dev = NULL;			/* struct exfat_dev is freed by exfat_close() */
+	free(ef->root);
+	ef->root = NULL;
+	free(ef->zero_cluster);
+	ef->zero_cluster = NULL;
+	free(ef->cmap.chunk);
+	ef->cmap.chunk = NULL;
+	free(ef->upcase);
+	ef->upcase = NULL;
+	free(ef->sb);
+	ef->sb = NULL;
+}
+
+int exfat_mount(struct exfat* ef, const char* spec, const char* options)
+{
+	int rc;
+	enum exfat_mode mode;
+
+	exfat_tzset();
+	memset(ef, 0, sizeof(struct exfat));
+
+	parse_options(ef, options);
+
+	if (exfat_match_option(options, "ro"))
+		mode = EXFAT_MODE_RO;
+	else if (exfat_match_option(options, "ro_fallback"))
+		mode = EXFAT_MODE_ANY;
+	else
+		mode = EXFAT_MODE_RW;
+	ef->dev = exfat_open(spec, mode);
+	if (ef->dev == NULL)
+		return -ENODEV;
+	if (exfat_get_mode(ef->dev) == EXFAT_MODE_RO)
+	{
+		if (mode == EXFAT_MODE_ANY)
+			ef->ro = -1;
+		else
+			ef->ro = 1;
+	}
+
+	ef->sb = malloc(sizeof(struct exfat_super_block));
+	if (ef->sb == NULL)
+	{
+		exfat_error("failed to allocate memory for the super block");
+		exfat_free(ef);
+		return -ENOMEM;
+	}
+	memset(ef->sb, 0, sizeof(struct exfat_super_block));
+
+	if (exfat_pread(ef->dev, ef->sb, sizeof(struct exfat_super_block), 0) < 0)
+	{
+		exfat_error("failed to read boot sector");
+		exfat_free(ef);
+		return -EIO;
+	}
+	if (memcmp(ef->sb->oem_name, "EXFAT   ", 8) != 0)
+	{
+#ifndef __UBOOT__
+		exfat_error(
+#else
+		exfat_debug(
+#endif
+		"exFAT file system is not found");
+		exfat_free(ef);
+		return -EIO;
+	}
+	/* sector cannot be smaller than 512 bytes */
+	if (ef->sb->sector_bits < 9)
+	{
+		exfat_error("too small sector size: 2^%hhd", ef->sb->sector_bits);
+		exfat_free(ef);
+		return -EIO;
+	}
+	/* officially exFAT supports cluster size up to 32 MB */
+	if ((int) ef->sb->sector_bits + (int) ef->sb->spc_bits > 25)
+	{
+		exfat_error("too big cluster size: 2^(%hhd+%hhd)",
+				ef->sb->sector_bits, ef->sb->spc_bits);
+		exfat_free(ef);
+		return -EIO;
+	}
+	ef->zero_cluster = malloc(CLUSTER_SIZE(*ef->sb));
+	if (ef->zero_cluster == NULL)
+	{
+		exfat_error("failed to allocate zero sector");
+		exfat_free(ef);
+		return -ENOMEM;
+	}
+	/* use zero_cluster as a temporary buffer for VBR checksum verification */
+	if (!verify_vbr_checksum(ef, ef->zero_cluster))
+	{
+		exfat_free(ef);
+		return -EIO;
+	}
+	memset(ef->zero_cluster, 0, CLUSTER_SIZE(*ef->sb));
+	if (ef->sb->version.major != 1 || ef->sb->version.minor != 0)
+	{
+		exfat_error("unsupported exFAT version: %hhu.%hhu",
+				ef->sb->version.major, ef->sb->version.minor);
+		exfat_free(ef);
+		return -EIO;
+	}
+	if (ef->sb->fat_count != 1)
+	{
+		exfat_error("unsupported FAT count: %hhu", ef->sb->fat_count);
+		exfat_free(ef);
+		return -EIO;
+	}
+	if (le64_to_cpu(ef->sb->sector_count) * SECTOR_SIZE(*ef->sb) >
+			(uint64_t) exfat_get_size(ef->dev))
+	{
+		/* this can cause I/O errors later but we don't fail mounting to let
+		   user rescue data */
+		exfat_warn("file system in sectors is larger than device: "
+				"%"PRIu64" * %d > %"PRIu64,
+				le64_to_cpu(ef->sb->sector_count), SECTOR_SIZE(*ef->sb),
+				exfat_get_size(ef->dev));
+	}
+	if ((off_t) le32_to_cpu(ef->sb->cluster_count) * CLUSTER_SIZE(*ef->sb) >
+			exfat_get_size(ef->dev))
+	{
+		exfat_error("file system in clusters is larger than device: "
+				"%u * %d > %"PRIu64,
+				le32_to_cpu(ef->sb->cluster_count), CLUSTER_SIZE(*ef->sb),
+				exfat_get_size(ef->dev));
+		exfat_free(ef);
+		return -EIO;
+	}
+	if (le16_to_cpu(ef->sb->volume_state) & EXFAT_STATE_MOUNTED)
+		exfat_warn("volume was not unmounted cleanly");
+
+	ef->root = malloc(sizeof(struct exfat_node));
+	if (ef->root == NULL)
+	{
+		exfat_error("failed to allocate root node");
+		exfat_free(ef);
+		return -ENOMEM;
+	}
+	memset(ef->root, 0, sizeof(struct exfat_node));
+	ef->root->attrib = EXFAT_ATTRIB_DIR;
+	ef->root->start_cluster = le32_to_cpu(ef->sb->rootdir_cluster);
+	ef->root->fptr_cluster = ef->root->start_cluster;
+	ef->root->name[0] = cpu_to_le16('\0');
+	ef->root->valid_size = ef->root->size = rootdir_size(ef);
+	if (ef->root->size == 0)
+	{
+		exfat_free(ef);
+		return -EIO;
+	}
+	/* exFAT does not have time attributes for the root directory */
+	ef->root->mtime = 0;
+	ef->root->atime = 0;
+	/* always keep at least 1 reference to the root node */
+	exfat_get_node(ef->root);
+
+	rc = exfat_cache_directory(ef, ef->root);
+	if (rc != 0)
+		goto error;
+	if (ef->upcase == NULL)
+	{
+		exfat_error("upcase table is not found");
+		goto error;
+	}
+	if (ef->cmap.chunk == NULL)
+	{
+		exfat_error("clusters bitmap is not found");
+		goto error;
+	}
+
+	return 0;
+
+error:
+	exfat_put_node(ef, ef->root);
+	exfat_reset_cache(ef);
+	exfat_free(ef);
+	return -EIO;
+}
+
+static void finalize_super_block(struct exfat* ef)
+{
+	if (ef->ro)
+		return;
+
+	ef->sb->volume_state = cpu_to_le16(
+			le16_to_cpu(ef->sb->volume_state) & ~EXFAT_STATE_MOUNTED);
+
+	/* Some implementations set the percentage of allocated space to 0xff
+	   on FS creation and never update it. In this case leave it as is. */
+	if (ef->sb->allocated_percent != 0xff)
+	{
+		uint32_t free, total;
+
+		free = exfat_count_free_clusters(ef);
+		total = le32_to_cpu(ef->sb->cluster_count);
+		ef->sb->allocated_percent = ((total - free) * 100 + total / 2) / total;
+	}
+
+	commit_super_block(ef);	/* ignore return code */
+}
+
+void exfat_unmount(struct exfat* ef)
+{
+	exfat_flush_nodes(ef);	/* ignore return code */
+	exfat_flush(ef);		/* ignore return code */
+	exfat_put_node(ef, ef->root);
+	exfat_reset_cache(ef);
+	finalize_super_block(ef);
+	exfat_free(ef);			/* will close the descriptor */
+}
diff --git a/fs/exfat/node.c b/fs/exfat/node.c
new file mode 100644
index 00000000000..88b1357189c
--- /dev/null
+++ b/fs/exfat/node.c
@@ -0,0 +1,1243 @@
+/*
+	node.c (09.10.09)
+	exFAT file system implementation library.
+
+	Free exFAT implementation.
+	Copyright (C) 2010-2023  Andrew Nayenko
+
+	This program is free software; you can redistribute it and/or modify
+	it under the terms of the GNU General Public License as published by
+	the Free Software Foundation, either version 2 of the License, or
+	(at your option) any later version.
+
+	This program is distributed in the hope that it will be useful,
+	but WITHOUT ANY WARRANTY; without even the implied warranty of
+	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+	GNU General Public License for more details.
+
+	You should have received a copy of the GNU General Public License along
+	with this program; if not, write to the Free Software Foundation, Inc.,
+	51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+*/
+
+#include "exfat.h"
+#include <errno.h>
+#include <string.h>
+#include <inttypes.h>
+
+#define EXFAT_ENTRY_NONE (-1)
+
+struct exfat_node* exfat_get_node(struct exfat_node* node)
+{
+	/* if we switch to multi-threaded mode we will need atomic
+	   increment here and atomic decrement in exfat_put_node() */
+	node->references++;
+	return node;
+}
+
+void exfat_put_node(struct exfat* ef, struct exfat_node* node)
+{
+	char buffer[EXFAT_UTF8_NAME_BUFFER_MAX];
+
+	--node->references;
+	if (node->references < 0)
+	{
+		exfat_get_name(node, buffer);
+		exfat_bug("reference counter of '%s' is below zero", buffer);
+	}
+	else if (node->references == 0 && node != ef->root)
+	{
+		if (node->is_dirty)
+		{
+			exfat_get_name(node, buffer);
+			exfat_warn("dirty node '%s' with zero references", buffer);
+		}
+	}
+}
+
+/**
+ * This function must be called on rmdir and unlink (after the last
+ * exfat_put_node()) to free clusters.
+ */
+int exfat_cleanup_node(struct exfat* ef, struct exfat_node* node)
+{
+	int rc = 0;
+
+	if (node->references != 0)
+		exfat_bug("unable to cleanup a node with %d references",
+				node->references);
+
+	if (node->is_unlinked)
+	{
+		/* free all clusters and node structure itself */
+		rc = exfat_truncate(ef, node, 0, true);
+		/* free the node even in case of error or its memory will be lost */
+		free(node);
+	}
+	return rc;
+}
+
+static int read_entries(struct exfat* ef, struct exfat_node* dir,
+		struct exfat_entry* entries, int n, off_t offset)
+{
+	ssize_t size;
+
+	if (!(dir->attrib & EXFAT_ATTRIB_DIR))
+		exfat_bug("attempted to read entries from a file");
+
+	size = exfat_generic_pread(ef, dir, entries,
+			sizeof(struct exfat_entry[n]), offset);
+	if (size == (ssize_t) sizeof(struct exfat_entry) * n)
+		return 0; /* success */
+	if (size == 0)
+		return -ENOENT;
+	if (size < 0)
+		return -EIO;
+	exfat_error("read %zd bytes instead of %zu bytes", size,
+			sizeof(struct exfat_entry[n]));
+	return -EIO;
+}
+
+static int write_entries(struct exfat* ef, struct exfat_node* dir,
+		const struct exfat_entry* entries, int n, off_t offset)
+{
+	ssize_t size;
+
+	if (!(dir->attrib & EXFAT_ATTRIB_DIR))
+		exfat_bug("attempted to write entries into a file");
+
+	size = exfat_generic_pwrite(ef, dir, entries,
+			sizeof(struct exfat_entry[n]), offset);
+	if (size == (ssize_t) sizeof(struct exfat_entry) * n)
+		return 0; /* success */
+	if (size < 0)
+		return -EIO;
+	exfat_error("wrote %zd bytes instead of %zu bytes", size,
+			sizeof(struct exfat_entry[n]));
+	return -EIO;
+}
+
+static struct exfat_node* allocate_node(void)
+{
+	struct exfat_node* node = malloc(sizeof(struct exfat_node));
+	if (node == NULL)
+	{
+		exfat_error("failed to allocate node");
+		return NULL;
+	}
+	memset(node, 0, sizeof(struct exfat_node));
+	return node;
+}
+
+static void init_node_meta1(struct exfat_node* node,
+		const struct exfat_entry_meta1* meta1)
+{
+	node->attrib = le16_to_cpu(meta1->attrib);
+	node->continuations = meta1->continuations;
+	node->mtime = exfat_exfat2unix(meta1->mdate, meta1->mtime,
+			meta1->mtime_cs, meta1->mtime_tzo);
+	/* there is no centiseconds field for atime */
+	node->atime = exfat_exfat2unix(meta1->adate, meta1->atime,
+			0, meta1->atime_tzo);
+}
+
+static void init_node_meta2(struct exfat_node* node,
+		const struct exfat_entry_meta2* meta2)
+{
+	node->valid_size = le64_to_cpu(meta2->valid_size);
+	node->size = le64_to_cpu(meta2->size);
+	node->start_cluster = le32_to_cpu(meta2->start_cluster);
+	node->fptr_cluster = node->start_cluster;
+	node->is_contiguous = ((meta2->flags & EXFAT_FLAG_CONTIGUOUS) != 0);
+}
+
+static void init_node_name(struct exfat_node* node,
+		const struct exfat_entry* entries, int n)
+{
+	int i;
+
+	for (i = 0; i < n; i++)
+		memcpy(node->name + i * EXFAT_ENAME_MAX,
+				((const struct exfat_entry_name*) &entries[i])->name,
+				EXFAT_ENAME_MAX * sizeof(le16_t));
+}
+
+static bool check_entries(const struct exfat_entry* entry, int n)
+{
+	int previous = EXFAT_ENTRY_NONE;
+	int current;
+	int i;
+
+	/* check transitions between entries types */
+	for (i = 0; i < n + 1; previous = current, i++)
+	{
+		bool valid = false;
+
+		current = (i < n) ? entry[i].type : EXFAT_ENTRY_NONE;
+		switch (previous)
+		{
+		case EXFAT_ENTRY_NONE:
+			valid = (current == EXFAT_ENTRY_FILE);
+			break;
+		case EXFAT_ENTRY_FILE:
+			valid = (current == EXFAT_ENTRY_FILE_INFO);
+			break;
+		case EXFAT_ENTRY_FILE_INFO:
+			valid = (current == EXFAT_ENTRY_FILE_NAME);
+			break;
+		case EXFAT_ENTRY_FILE_NAME:
+			valid = (current == EXFAT_ENTRY_FILE_NAME ||
+			         current == EXFAT_ENTRY_NONE ||
+			         current >= EXFAT_ENTRY_FILE_TAIL);
+			break;
+		case EXFAT_ENTRY_FILE_TAIL ... 0xff:
+			valid = (current >= EXFAT_ENTRY_FILE_TAIL ||
+			         current == EXFAT_ENTRY_NONE);
+			break;
+		}
+
+		if (!valid)
+		{
+			exfat_error("unexpected entry type %#x after %#x at %d/%d",
+					current, previous, i, n);
+			return false;
+		}
+	}
+	return true;
+}
+
+static bool check_node(const struct exfat* ef, struct exfat_node* node,
+		le16_t actual_checksum, const struct exfat_entry_meta1* meta1)
+{
+	int cluster_size = CLUSTER_SIZE(*ef->sb);
+	uint64_t clusters_heap_size =
+			(uint64_t) le32_to_cpu(ef->sb->cluster_count) * cluster_size;
+	char buffer[EXFAT_UTF8_NAME_BUFFER_MAX];
+	bool ret = true;
+
+	/*
+	   Validate checksum first. If it's invalid all other fields probably
+	   contain just garbage.
+	*/
+	if (le16_to_cpu(actual_checksum) != le16_to_cpu(meta1->checksum))
+	{
+		exfat_get_name(node, buffer);
+		exfat_error("'%s' has invalid checksum (%#hx != %#hx)", buffer,
+				le16_to_cpu(actual_checksum), le16_to_cpu(meta1->checksum));
+		if (!EXFAT_REPAIR(invalid_node_checksum, ef, node))
+			ret = false;
+	}
+
+	/*
+	   exFAT does not support sparse files but allows files with uninitialized
+	   clusters. For such files valid_size means initialized data size and
+	   cannot be greater than file size. See SetFileValidData() function
+	   description in MSDN.
+	*/
+	if (node->valid_size > node->size)
+	{
+		exfat_get_name(node, buffer);
+		exfat_error("'%s' has valid size (%"PRIu64") greater than size "
+				"(%"PRIu64")", buffer, node->valid_size, node->size);
+		ret = false;
+	}
+
+	/*
+	   Empty file must have zero start cluster. Non-empty file must start
+	   with a valid cluster. Directories cannot be empty (i.e. must always
+	   have a valid start cluster), but we will check this later while
+	   reading that directory to give user a chance to read this directory.
+	*/
+	if (node->size == 0 && node->start_cluster != EXFAT_CLUSTER_FREE)
+	{
+		exfat_get_name(node, buffer);
+		exfat_error("'%s' is empty but start cluster is %#x", buffer,
+				node->start_cluster);
+		ret = false;
+	}
+	if (node->size > 0 && CLUSTER_INVALID(*ef->sb, node->start_cluster))
+	{
+		exfat_get_name(node, buffer);
+		exfat_error("'%s' points to invalid cluster %#x", buffer,
+				node->start_cluster);
+		ret = false;
+	}
+
+	/* File or directory cannot be larger than clusters heap. */
+	if (node->size > clusters_heap_size)
+	{
+		exfat_get_name(node, buffer);
+		exfat_error("'%s' is larger than clusters heap: %"PRIu64" > %"PRIu64,
+				buffer, node->size, clusters_heap_size);
+		ret = false;
+	}
+
+	/* Empty file or directory must be marked as non-contiguous. */
+	if (node->size == 0 && node->is_contiguous)
+	{
+		exfat_get_name(node, buffer);
+		exfat_error("'%s' is empty but marked as contiguous (%#hx)", buffer,
+				node->attrib);
+		ret = false;
+	}
+
+	/* Directory size must be aligned on at cluster boundary. */
+	if ((node->attrib & EXFAT_ATTRIB_DIR) && node->size % cluster_size != 0)
+	{
+		exfat_get_name(node, buffer);
+		exfat_error("'%s' directory size %"PRIu64" is not divisible by %d", buffer,
+				node->size, cluster_size);
+		ret = false;
+	}
+
+	return ret;
+}
+
+static int parse_file_entries(struct exfat* ef, struct exfat_node* node,
+		const struct exfat_entry* entries, int n)
+{
+	const struct exfat_entry_meta1* meta1;
+	const struct exfat_entry_meta2* meta2;
+	int mandatory_entries;
+
+	if (!check_entries(entries, n))
+		return -EIO;
+
+	meta1 = (const struct exfat_entry_meta1*) &entries[0];
+	if (meta1->continuations < 2)
+	{
+		exfat_error("too few continuations (%hhu)", meta1->continuations);
+		return -EIO;
+	}
+	meta2 = (const struct exfat_entry_meta2*) &entries[1];
+	if (meta2->flags & ~(EXFAT_FLAG_ALWAYS1 | EXFAT_FLAG_CONTIGUOUS))
+	{
+		exfat_error("unknown flags in meta2 (%#hhx)", meta2->flags);
+		return -EIO;
+	}
+	mandatory_entries = 2 + DIV_ROUND_UP(meta2->name_length, EXFAT_ENAME_MAX);
+	if (meta1->continuations < mandatory_entries - 1)
+	{
+		exfat_error("too few continuations (%hhu < %d)",
+				meta1->continuations, mandatory_entries - 1);
+		return -EIO;
+	}
+
+	init_node_meta1(node, meta1);
+	init_node_meta2(node, meta2);
+	init_node_name(node, entries + 2, mandatory_entries - 2);
+
+	if (!check_node(ef, node, exfat_calc_checksum(entries, n), meta1))
+		return -EIO;
+
+	return 0;
+}
+
+static int parse_file_entry(struct exfat* ef, struct exfat_node* parent,
+		struct exfat_node** node, off_t* offset, int n)
+{
+	struct exfat_entry entries[n];
+	int rc;
+
+	rc = read_entries(ef, parent, entries, n, *offset);
+	if (rc != 0)
+		return rc;
+
+	/* a new node has zero references */
+	*node = allocate_node();
+	if (*node == NULL)
+		return -ENOMEM;
+	(*node)->entry_offset = *offset;
+
+	rc = parse_file_entries(ef, *node, entries, n);
+	if (rc != 0)
+	{
+		free(*node);
+		return rc;
+	}
+
+	*offset += sizeof(struct exfat_entry[n]);
+	return 0;
+}
+
+static void decompress_upcase(uint16_t* output, const le16_t* source,
+		size_t size)
+{
+	size_t si;
+	size_t oi;
+
+	for (oi = 0; oi < EXFAT_UPCASE_CHARS; oi++)
+		output[oi] = oi;
+
+	for (si = 0, oi = 0; si < size && oi < EXFAT_UPCASE_CHARS; si++)
+	{
+		uint16_t ch = le16_to_cpu(source[si]);
+
+		if (ch == 0xffff && si + 1 < size)	/* indicates a run */
+			oi += le16_to_cpu(source[++si]);
+		else
+			output[oi++] = ch;
+	}
+}
+
+/*
+ * Read one entry in a directory at offset position and build a new node
+ * structure.
+ */
+static int readdir(struct exfat* ef, struct exfat_node* parent,
+		struct exfat_node** node, off_t* offset)
+{
+	int rc;
+	struct exfat_entry entry;
+	const struct exfat_entry_meta1* meta1;
+	const struct exfat_entry_upcase* upcase;
+	const struct exfat_entry_bitmap* bitmap;
+	const struct exfat_entry_label* label;
+	uint64_t upcase_size = 0;
+	le16_t* upcase_comp = NULL;
+	le16_t label_name[EXFAT_ENAME_MAX];
+
+	for (;;)
+	{
+		rc = read_entries(ef, parent, &entry, 1, *offset);
+		if (rc != 0)
+			return rc;
+
+		switch (entry.type)
+		{
+		case EXFAT_ENTRY_FILE:
+			meta1 = (const struct exfat_entry_meta1*) &entry;
+			return parse_file_entry(ef, parent, node, offset,
+					1 + meta1->continuations);
+
+		case EXFAT_ENTRY_UPCASE:
+			if (ef->upcase != NULL)
+				break;
+			upcase = (const struct exfat_entry_upcase*) &entry;
+			if (CLUSTER_INVALID(*ef->sb, le32_to_cpu(upcase->start_cluster)))
+			{
+				exfat_error("invalid cluster 0x%x in upcase table",
+						le32_to_cpu(upcase->start_cluster));
+				return -EIO;
+			}
+			upcase_size = le64_to_cpu(upcase->size);
+			if (upcase_size == 0 ||
+				upcase_size > EXFAT_UPCASE_CHARS * sizeof(uint16_t) ||
+				upcase_size % sizeof(uint16_t) != 0)
+			{
+				exfat_error("bad upcase table size (%"PRIu64" bytes)",
+						upcase_size);
+				return -EIO;
+			}
+			upcase_comp = malloc(upcase_size);
+			if (upcase_comp == NULL)
+			{
+				exfat_error("failed to allocate upcase table (%"PRIu64" bytes)",
+						upcase_size);
+				return -ENOMEM;
+			}
+
+			/* read compressed upcase table */
+			if (exfat_pread(ef->dev, upcase_comp, upcase_size,
+					exfat_c2o(ef, le32_to_cpu(upcase->start_cluster))) < 0)
+			{
+				free(upcase_comp);
+				exfat_error("failed to read upper case table "
+						"(%"PRIu64" bytes starting at cluster %#x)",
+						upcase_size,
+						le32_to_cpu(upcase->start_cluster));
+				return -EIO;
+			}
+
+			/* decompress upcase table */
+			ef->upcase = calloc(EXFAT_UPCASE_CHARS, sizeof(uint16_t));
+			if (ef->upcase == NULL)
+			{
+				free(upcase_comp);
+				exfat_error("failed to allocate decompressed upcase table");
+				return -ENOMEM;
+			}
+			decompress_upcase(ef->upcase, upcase_comp,
+					upcase_size / sizeof(uint16_t));
+			free(upcase_comp);
+			break;
+
+		case EXFAT_ENTRY_BITMAP:
+			bitmap = (const struct exfat_entry_bitmap*) &entry;
+			ef->cmap.start_cluster = le32_to_cpu(bitmap->start_cluster);
+			if (CLUSTER_INVALID(*ef->sb, ef->cmap.start_cluster))
+			{
+				exfat_error("invalid cluster 0x%x in clusters bitmap",
+						ef->cmap.start_cluster);
+				return -EIO;
+			}
+			ef->cmap.size = le32_to_cpu(ef->sb->cluster_count);
+			if (le64_to_cpu(bitmap->size) < DIV_ROUND_UP(ef->cmap.size, 8))
+			{
+				exfat_error("invalid clusters bitmap size: %"PRIu64
+						" (expected at least %u)",
+						le64_to_cpu(bitmap->size),
+						DIV_ROUND_UP(ef->cmap.size, 8));
+				return -EIO;
+			}
+			/* FIXME bitmap can be rather big, up to 512 MB */
+			ef->cmap.chunk_size = ef->cmap.size;
+			ef->cmap.chunk = malloc(BMAP_SIZE(ef->cmap.chunk_size));
+			if (ef->cmap.chunk == NULL)
+			{
+				exfat_error("failed to allocate clusters bitmap chunk "
+						"(%"PRIu64" bytes)", le64_to_cpu(bitmap->size));
+				return -ENOMEM;
+			}
+
+			if (exfat_pread(ef->dev, ef->cmap.chunk,
+					BMAP_SIZE(ef->cmap.chunk_size),
+					exfat_c2o(ef, ef->cmap.start_cluster)) < 0)
+			{
+				exfat_error("failed to read clusters bitmap "
+						"(%"PRIu64" bytes starting at cluster %#x)",
+						le64_to_cpu(bitmap->size), ef->cmap.start_cluster);
+				return -EIO;
+			}
+			break;
+
+		case EXFAT_ENTRY_LABEL:
+			label = (const struct exfat_entry_label*) &entry;
+			if (label->length > EXFAT_ENAME_MAX)
+			{
+				exfat_error("too long label (%hhu chars)", label->length);
+				return -EIO;
+			}
+			/* copy to a temporary buffer to avoid unaligned access to a
+			   packed member */
+			memcpy(label_name, label->name, sizeof(label_name));
+			if (exfat_utf16_to_utf8(ef->label, label_name,
+						sizeof(ef->label), EXFAT_ENAME_MAX) != 0)
+				return -EIO;
+			break;
+
+		default:
+			if (!(entry.type & EXFAT_ENTRY_VALID))
+				break; /* deleted entry, ignore it */
+
+			exfat_error("unknown entry type %#hhx", entry.type);
+			if (!EXFAT_REPAIR(unknown_entry, ef, parent, &entry, *offset))
+				return -EIO;
+		}
+		*offset += sizeof(entry);
+	}
+	/* we never reach here */
+}
+
+int exfat_cache_directory(struct exfat* ef, struct exfat_node* dir)
+{
+	off_t offset = 0;
+	int rc;
+	struct exfat_node* node;
+	struct exfat_node* current = NULL;
+
+	if (dir->is_cached)
+		return 0; /* already cached */
+
+	while ((rc = readdir(ef, dir, &node, &offset)) == 0)
+	{
+		node->parent = dir;
+		if (current != NULL)
+		{
+			current->next = node;
+			node->prev = current;
+		}
+		else
+			dir->child = node;
+
+		current = node;
+	}
+
+	if (rc != -ENOENT)
+	{
+		/* rollback */
+		for (current = dir->child; current; current = node)
+		{
+			node = current->next;
+			free(current);
+		}
+		dir->child = NULL;
+		return rc;
+	}
+
+	dir->is_cached = true;
+	return 0;
+}
+
+static void tree_attach(struct exfat_node* dir, struct exfat_node* node)
+{
+	node->parent = dir;
+	if (dir->child)
+	{
+		dir->child->prev = node;
+		node->next = dir->child;
+	}
+	dir->child = node;
+}
+
+static void tree_detach(struct exfat_node* node)
+{
+	if (node->prev)
+		node->prev->next = node->next;
+	else /* this is the first node in the list */
+		node->parent->child = node->next;
+	if (node->next)
+		node->next->prev = node->prev;
+	node->parent = NULL;
+	node->prev = NULL;
+	node->next = NULL;
+}
+
+static void reset_cache(struct exfat* ef, struct exfat_node* node)
+{
+	char buffer[EXFAT_UTF8_NAME_BUFFER_MAX];
+
+	while (node->child)
+	{
+		struct exfat_node* p = node->child;
+		reset_cache(ef, p);
+		tree_detach(p);
+		free(p);
+	}
+	node->is_cached = false;
+	if (node->references != 0)
+	{
+		exfat_get_name(node, buffer);
+		exfat_warn("non-zero reference counter (%d) for '%s'",
+				node->references, buffer);
+	}
+	if (node != ef->root && node->is_dirty)
+	{
+		exfat_get_name(node, buffer);
+		exfat_bug("node '%s' is dirty", buffer);
+	}
+	while (node->references)
+		exfat_put_node(ef, node);
+}
+
+void exfat_reset_cache(struct exfat* ef)
+{
+	reset_cache(ef, ef->root);
+}
+
+int exfat_flush_node(struct exfat* ef, struct exfat_node* node)
+{
+	struct exfat_entry entries[1 + node->continuations];
+	struct exfat_entry_meta1* meta1 = (struct exfat_entry_meta1*) &entries[0];
+	struct exfat_entry_meta2* meta2 = (struct exfat_entry_meta2*) &entries[1];
+	int rc;
+	le16_t edate, etime;
+
+	if (!node->is_dirty)
+		return 0; /* no need to flush */
+
+	if (ef->ro)
+		exfat_bug("unable to flush node to read-only FS");
+
+	if (node->parent == NULL)
+		return 0; /* do not flush unlinked node */
+
+	rc = read_entries(ef, node->parent, entries, 1 + node->continuations,
+			node->entry_offset);
+	if (rc != 0)
+		return rc;
+	if (!check_entries(entries, 1 + node->continuations))
+		return -EIO;
+
+	meta1->attrib = cpu_to_le16(node->attrib);
+	exfat_unix2exfat(node->mtime, &edate, &etime,
+			&meta1->mtime_cs, &meta1->mtime_tzo);
+	meta1->mdate = edate;
+	meta1->mtime = etime;
+	exfat_unix2exfat(node->atime, &edate, &etime,
+			NULL, &meta1->atime_tzo);
+	meta1->adate = edate;
+	meta1->atime = etime;
+	meta2->valid_size = cpu_to_le64(node->valid_size);
+	meta2->size = cpu_to_le64(node->size);
+	meta2->start_cluster = cpu_to_le32(node->start_cluster);
+	meta2->flags = EXFAT_FLAG_ALWAYS1;
+	/* empty files must not be marked as contiguous */
+	if (node->size != 0 && node->is_contiguous)
+		meta2->flags |= EXFAT_FLAG_CONTIGUOUS;
+	/* name hash remains unchanged, no need to recalculate it */
+
+	meta1->checksum = exfat_calc_checksum(entries, 1 + node->continuations);
+	rc = write_entries(ef, node->parent, entries, 1 + node->continuations,
+			node->entry_offset);
+	if (rc != 0)
+		return rc;
+
+	node->is_dirty = false;
+	return exfat_flush(ef);
+}
+
+static int erase_entries(struct exfat* ef, struct exfat_node* dir, int n,
+		off_t offset)
+{
+	struct exfat_entry entries[n];
+	int rc;
+	int i;
+
+	rc = read_entries(ef, dir, entries, n, offset);
+	if (rc != 0)
+		return rc;
+	for (i = 0; i < n; i++)
+		entries[i].type &= ~EXFAT_ENTRY_VALID;
+	return write_entries(ef, dir, entries, n, offset);
+}
+
+static int erase_node(struct exfat* ef, struct exfat_node* node)
+{
+	int rc;
+
+	exfat_get_node(node->parent);
+	rc = erase_entries(ef, node->parent, 1 + node->continuations,
+			node->entry_offset);
+	if (rc != 0)
+	{
+		exfat_put_node(ef, node->parent);
+		return rc;
+	}
+	rc = exfat_flush_node(ef, node->parent);
+	exfat_put_node(ef, node->parent);
+	return rc;
+}
+
+static int shrink_directory(struct exfat* ef, struct exfat_node* dir,
+		off_t deleted_offset)
+{
+	const struct exfat_node* node;
+	const struct exfat_node* last_node;
+	uint64_t entries = 0;
+	uint64_t new_size;
+
+	if (!(dir->attrib & EXFAT_ATTRIB_DIR))
+		exfat_bug("attempted to shrink a file");
+	if (!dir->is_cached)
+		exfat_bug("attempted to shrink uncached directory");
+
+	for (last_node = node = dir->child; node; node = node->next)
+	{
+		if (deleted_offset < node->entry_offset)
+		{
+			/* there are other entries after the removed one, no way to shrink
+			   this directory */
+			return 0;
+		}
+		if (last_node->entry_offset < node->entry_offset)
+			last_node = node;
+	}
+
+	if (last_node)
+	{
+		/* offset of the last entry */
+		entries += last_node->entry_offset / sizeof(struct exfat_entry);
+		/* two subentries with meta info */
+		entries += 2;
+		/* subentries with file name */
+		entries += DIV_ROUND_UP(exfat_utf16_length(last_node->name),
+				EXFAT_ENAME_MAX);
+	}
+
+	new_size = DIV_ROUND_UP(entries * sizeof(struct exfat_entry),
+				 CLUSTER_SIZE(*ef->sb)) * CLUSTER_SIZE(*ef->sb);
+	if (new_size == 0) /* directory always has at least 1 cluster */
+		new_size = CLUSTER_SIZE(*ef->sb);
+	if (new_size == dir->size)
+		return 0;
+	return exfat_truncate(ef, dir, new_size, true);
+}
+
+static int delete(struct exfat* ef, struct exfat_node* node)
+{
+	struct exfat_node* parent = node->parent;
+	off_t deleted_offset = node->entry_offset;
+	int rc;
+
+	exfat_get_node(parent);
+	rc = erase_node(ef, node);
+	if (rc != 0)
+	{
+		exfat_put_node(ef, parent);
+		return rc;
+	}
+	tree_detach(node);
+	rc = shrink_directory(ef, parent, deleted_offset);
+	node->is_unlinked = true;
+	if (rc != 0)
+	{
+		exfat_flush_node(ef, parent);
+		exfat_put_node(ef, parent);
+		return rc;
+	}
+	exfat_update_mtime(parent);
+	rc = exfat_flush_node(ef, parent);
+	exfat_put_node(ef, parent);
+	return rc;
+}
+
+int exfat_unlink(struct exfat* ef, struct exfat_node* node)
+{
+	if (node->attrib & EXFAT_ATTRIB_DIR)
+		return -EISDIR;
+	return delete(ef, node);
+}
+
+int exfat_rmdir(struct exfat* ef, struct exfat_node* node)
+{
+	int rc;
+
+	if (!(node->attrib & EXFAT_ATTRIB_DIR))
+		return -ENOTDIR;
+	/* check that directory is empty */
+	rc = exfat_cache_directory(ef, node);
+	if (rc != 0)
+		return rc;
+	if (node->child)
+		return -ENOTEMPTY;
+	return delete(ef, node);
+}
+
+static int check_slot(struct exfat* ef, struct exfat_node* dir, off_t offset,
+		int n)
+{
+	struct exfat_entry entries[n];
+	int rc;
+	int i;
+
+	/* Root directory contains entries, that don't have any nodes associated
+	   with them (clusters bitmap, upper case table, label). We need to be
+	   careful not to overwrite them. */
+	if (dir != ef->root)
+		return 0;
+
+	rc = read_entries(ef, dir, entries, n, offset);
+	if (rc != 0)
+		return rc;
+	for (i = 0; i < n; i++)
+		if (entries[i].type & EXFAT_ENTRY_VALID)
+			return -EINVAL;
+	return 0;
+}
+
+static int find_slot(struct exfat* ef, struct exfat_node* dir,
+		off_t* offset, int n)
+{
+	bitmap_t* dmap;
+	struct exfat_node* p;
+	size_t i;
+	int contiguous = 0;
+
+	if (!dir->is_cached)
+		exfat_bug("directory is not cached");
+
+	/* build a bitmap of valid entries in the directory */
+	dmap = calloc(BMAP_SIZE(dir->size / sizeof(struct exfat_entry)),
+			sizeof(bitmap_t));
+	if (dmap == NULL)
+	{
+		exfat_error("failed to allocate directory bitmap (%"PRIu64")",
+				dir->size / sizeof(struct exfat_entry));
+		return -ENOMEM;
+	}
+	for (p = dir->child; p != NULL; p = p->next)
+		for (i = 0; i < 1u + p->continuations; i++)
+			BMAP_SET(dmap, p->entry_offset / sizeof(struct exfat_entry) + i);
+
+	/* find a slot in the directory entries bitmap */
+	for (i = 0; i < dir->size / sizeof(struct exfat_entry); i++)
+	{
+		if (BMAP_GET(dmap, i) == 0)
+		{
+			if (contiguous++ == 0)
+				*offset = (off_t) i * sizeof(struct exfat_entry);
+			if (contiguous == n)
+			{
+				int rc;
+
+				/* suitable slot is found, check that it's not occupied */
+				rc = check_slot(ef, dir, *offset, n);
+				if (rc == -EINVAL)
+				{
+					/* slot at (i-n) is occupied, go back and check (i-n+1) */
+					i -= contiguous - 1;
+					contiguous = 0;
+				}
+				else
+				{
+					/* slot is free or an error occurred */
+					free(dmap);
+					return rc;
+				}
+			}
+		}
+		else
+			contiguous = 0;
+	}
+	free(dmap);
+
+	/* no suitable slots found, extend the directory */
+	if (contiguous == 0)
+		*offset = dir->size;
+	return exfat_truncate(ef, dir,
+			ROUND_UP(dir->size + sizeof(struct exfat_entry[n - contiguous]),
+					CLUSTER_SIZE(*ef->sb)),
+			true);
+}
+
+static int commit_entry(struct exfat* ef, struct exfat_node* dir,
+		const le16_t* name, off_t offset, uint16_t attrib)
+{
+	struct exfat_node* node;
+	const size_t name_length = exfat_utf16_length(name);
+	const int name_entries = DIV_ROUND_UP(name_length, EXFAT_ENAME_MAX);
+	struct exfat_entry entries[2 + name_entries];
+	struct exfat_entry_meta1* meta1 = (struct exfat_entry_meta1*) &entries[0];
+	struct exfat_entry_meta2* meta2 = (struct exfat_entry_meta2*) &entries[1];
+	int i;
+	int rc;
+	le16_t edate, etime;
+
+	memset(entries, 0, sizeof(struct exfat_entry[2]));
+
+	meta1->type = EXFAT_ENTRY_FILE;
+	meta1->continuations = 1 + name_entries;
+	meta1->attrib = cpu_to_le16(attrib);
+	exfat_unix2exfat(time(NULL), &edate, &etime,
+			&meta1->crtime_cs, &meta1->crtime_tzo);
+	meta1->adate = meta1->mdate = meta1->crdate = edate;
+	meta1->atime = meta1->mtime = meta1->crtime = etime;
+	meta1->mtime_cs = meta1->crtime_cs; /* there is no atime_cs */
+	meta1->atime_tzo = meta1->mtime_tzo = meta1->crtime_tzo;
+
+	meta2->type = EXFAT_ENTRY_FILE_INFO;
+	meta2->flags = EXFAT_FLAG_ALWAYS1;
+	meta2->name_length = name_length;
+	meta2->name_hash = exfat_calc_name_hash(ef, name, name_length);
+	meta2->start_cluster = cpu_to_le32(EXFAT_CLUSTER_FREE);
+
+	for (i = 0; i < name_entries; i++)
+	{
+		struct exfat_entry_name* name_entry;
+
+		name_entry = (struct exfat_entry_name*) &entries[2 + i];
+		name_entry->type = EXFAT_ENTRY_FILE_NAME;
+		name_entry->__unknown = 0;
+		memcpy(name_entry->name, name + i * EXFAT_ENAME_MAX,
+				EXFAT_ENAME_MAX * sizeof(le16_t));
+	}
+
+	meta1->checksum = exfat_calc_checksum(entries, 2 + name_entries);
+	rc = write_entries(ef, dir, entries, 2 + name_entries, offset);
+	if (rc != 0)
+		return rc;
+
+	node = allocate_node();
+	if (node == NULL)
+		return -ENOMEM;
+	node->entry_offset = offset;
+	memcpy(node->name, name, name_length * sizeof(le16_t));
+	init_node_meta1(node, meta1);
+	init_node_meta2(node, meta2);
+
+	tree_attach(dir, node);
+	return 0;
+}
+
+static int create(struct exfat* ef, const char* path, uint16_t attrib)
+{
+	struct exfat_node* dir;
+	struct exfat_node* existing;
+	off_t offset = -1;
+	le16_t name[EXFAT_NAME_MAX + 1];
+	int rc;
+
+	rc = exfat_split(ef, &dir, &existing, name, path);
+	if (rc != 0)
+		return rc;
+	if (existing != NULL)
+	{
+		exfat_put_node(ef, existing);
+		exfat_put_node(ef, dir);
+		return -EEXIST;
+	}
+
+	rc = find_slot(ef, dir, &offset,
+			2 + DIV_ROUND_UP(exfat_utf16_length(name), EXFAT_ENAME_MAX));
+	if (rc != 0)
+	{
+		exfat_put_node(ef, dir);
+		return rc;
+	}
+	rc = commit_entry(ef, dir, name, offset, attrib);
+	if (rc != 0)
+	{
+		exfat_put_node(ef, dir);
+		return rc;
+	}
+	exfat_update_mtime(dir);
+	rc = exfat_flush_node(ef, dir);
+	exfat_put_node(ef, dir);
+	return rc;
+}
+
+int exfat_mknod(struct exfat* ef, const char* path)
+{
+	return create(ef, path, EXFAT_ATTRIB_ARCH);
+}
+
+int exfat_mkdir(struct exfat* ef, const char* path)
+{
+	int rc;
+	struct exfat_node* node;
+
+	rc = create(ef, path, EXFAT_ATTRIB_DIR);
+	if (rc != 0)
+		return rc;
+	rc = exfat_lookup(ef, &node, path);
+	if (rc != 0)
+		return 0;
+	/* directories always have at least one cluster */
+	rc = exfat_truncate(ef, node, CLUSTER_SIZE(*ef->sb), true);
+	if (rc != 0)
+	{
+		delete(ef, node);
+		exfat_put_node(ef, node);
+		return rc;
+	}
+	rc = exfat_flush_node(ef, node);
+	if (rc != 0)
+	{
+		delete(ef, node);
+		exfat_put_node(ef, node);
+		return rc;
+	}
+	exfat_put_node(ef, node);
+	return 0;
+}
+
+static int rename_entry(struct exfat* ef, struct exfat_node* dir,
+		struct exfat_node* node, const le16_t* name, off_t new_offset)
+{
+	const size_t name_length = exfat_utf16_length(name);
+	const int name_entries = DIV_ROUND_UP(name_length, EXFAT_ENAME_MAX);
+	struct exfat_entry entries[2 + name_entries];
+	struct exfat_entry_meta1* meta1 = (struct exfat_entry_meta1*) &entries[0];
+	struct exfat_entry_meta2* meta2 = (struct exfat_entry_meta2*) &entries[1];
+	int rc;
+	int i;
+
+	rc = read_entries(ef, node->parent, entries, 2, node->entry_offset);
+	if (rc != 0)
+		return rc;
+
+	meta1->continuations = 1 + name_entries;
+	meta2->name_length = name_length;
+	meta2->name_hash = exfat_calc_name_hash(ef, name, name_length);
+
+	rc = erase_node(ef, node);
+	if (rc != 0)
+		return rc;
+
+	node->entry_offset = new_offset;
+	node->continuations = 1 + name_entries;
+
+	for (i = 0; i < name_entries; i++)
+	{
+		struct exfat_entry_name* name_entry;
+
+		name_entry = (struct exfat_entry_name*) &entries[2 + i];
+		name_entry->type = EXFAT_ENTRY_FILE_NAME;
+		name_entry->__unknown = 0;
+		memcpy(name_entry->name, name + i * EXFAT_ENAME_MAX,
+				EXFAT_ENAME_MAX * sizeof(le16_t));
+	}
+
+	meta1->checksum = exfat_calc_checksum(entries, 2 + name_entries);
+	rc = write_entries(ef, dir, entries, 2 + name_entries, new_offset);
+	if (rc != 0)
+		return rc;
+
+	memcpy(node->name, name, (EXFAT_NAME_MAX + 1) * sizeof(le16_t));
+	tree_detach(node);
+	tree_attach(dir, node);
+	return 0;
+}
+
+int exfat_rename(struct exfat* ef, const char* old_path, const char* new_path)
+{
+	struct exfat_node* node;
+	struct exfat_node* existing;
+	struct exfat_node* dir;
+	off_t offset = -1;
+	le16_t name[EXFAT_NAME_MAX + 1];
+	int rc;
+
+	rc = exfat_lookup(ef, &node, old_path);
+	if (rc != 0)
+		return rc;
+
+	rc = exfat_split(ef, &dir, &existing, name, new_path);
+	if (rc != 0)
+	{
+		exfat_put_node(ef, node);
+		return rc;
+	}
+
+	/* check that target is not a subdirectory of the source */
+	if (node->attrib & EXFAT_ATTRIB_DIR)
+	{
+		struct exfat_node* p;
+
+		for (p = dir; p; p = p->parent)
+			if (node == p)
+			{
+				if (existing != NULL)
+					exfat_put_node(ef, existing);
+				exfat_put_node(ef, dir);
+				exfat_put_node(ef, node);
+				return -EINVAL;
+			}
+	}
+
+	if (existing != NULL)
+	{
+		/* remove target if it's not the same node as source */
+		if (existing != node)
+		{
+			if (existing->attrib & EXFAT_ATTRIB_DIR)
+			{
+				if (node->attrib & EXFAT_ATTRIB_DIR)
+					rc = exfat_rmdir(ef, existing);
+				else
+					rc = -ENOTDIR;
+			}
+			else
+			{
+				if (!(node->attrib & EXFAT_ATTRIB_DIR))
+					rc = exfat_unlink(ef, existing);
+				else
+					rc = -EISDIR;
+			}
+			exfat_put_node(ef, existing);
+			if (rc != 0)
+			{
+				/* free clusters even if something went wrong; otherwise they
+				   will be just lost */
+				exfat_cleanup_node(ef, existing);
+				exfat_put_node(ef, dir);
+				exfat_put_node(ef, node);
+				return rc;
+			}
+			rc = exfat_cleanup_node(ef, existing);
+			if (rc != 0)
+			{
+				exfat_put_node(ef, dir);
+				exfat_put_node(ef, node);
+				return rc;
+			}
+		}
+		else
+			exfat_put_node(ef, existing);
+	}
+
+	rc = find_slot(ef, dir, &offset,
+			2 + DIV_ROUND_UP(exfat_utf16_length(name), EXFAT_ENAME_MAX));
+	if (rc != 0)
+	{
+		exfat_put_node(ef, dir);
+		exfat_put_node(ef, node);
+		return rc;
+	}
+	rc = rename_entry(ef, dir, node, name, offset);
+	if (rc != 0)
+	{
+		exfat_put_node(ef, dir);
+		exfat_put_node(ef, node);
+		return rc;
+	}
+	rc = exfat_flush_node(ef, dir);
+	exfat_put_node(ef, dir);
+	exfat_put_node(ef, node);
+	/* node itself is not marked as dirty, no need to flush it */
+	return rc;
+}
+
+void exfat_utimes(struct exfat_node* node, const struct timespec tv[2])
+{
+	node->atime = tv[0].tv_sec;
+	node->mtime = tv[1].tv_sec;
+	node->is_dirty = true;
+}
+
+void exfat_update_atime(struct exfat_node* node)
+{
+	node->atime = time(NULL);
+	node->is_dirty = true;
+}
+
+void exfat_update_mtime(struct exfat_node* node)
+{
+	node->mtime = time(NULL);
+	node->is_dirty = true;
+}
+
+const char* exfat_get_label(struct exfat* ef)
+{
+	return ef->label;
+}
+
+static int find_label(struct exfat* ef, off_t* offset)
+{
+	struct exfat_entry entry;
+	int rc;
+
+	for (*offset = 0; ; *offset += sizeof(entry))
+	{
+		rc = read_entries(ef, ef->root, &entry, 1, *offset);
+		if (rc != 0)
+			return rc;
+
+		if (entry.type == EXFAT_ENTRY_LABEL)
+			return 0;
+	}
+}
+
+int exfat_set_label(struct exfat* ef, const char* label)
+{
+	le16_t label_utf16[EXFAT_ENAME_MAX + 1];
+	int rc;
+	off_t offset;
+	struct exfat_entry_label entry;
+
+	memset(label_utf16, 0, sizeof(label_utf16));
+	rc = exfat_utf8_to_utf16(label_utf16, label, EXFAT_ENAME_MAX + 1,
+			strlen(label));
+	if (rc != 0)
+		return rc;
+
+	rc = find_label(ef, &offset);
+	if (rc == -ENOENT)
+		rc = find_slot(ef, ef->root, &offset, 1);
+	if (rc != 0)
+		return rc;
+
+	entry.type = EXFAT_ENTRY_LABEL;
+	entry.length = exfat_utf16_length(label_utf16);
+	memcpy(entry.name, label_utf16, sizeof(entry.name));
+	if (entry.length == 0)
+		entry.type ^= EXFAT_ENTRY_VALID;
+
+	rc = write_entries(ef, ef->root, (struct exfat_entry*) &entry, 1, offset);
+	if (rc != 0)
+		return rc;
+
+	strcpy(ef->label, label);
+	return 0;
+}
diff --git a/fs/exfat/platform.h b/fs/exfat/platform.h
new file mode 100644
index 00000000000..668857607bf
--- /dev/null
+++ b/fs/exfat/platform.h
@@ -0,0 +1,75 @@
+/*
+	platform.h (14.05.13)
+	OS-specific code (libc-specific in fact). Note that systems with the
+	same kernel can use different libc implementations.
+
+	Free exFAT implementation.
+	Copyright (C) 2010-2023  Andrew Nayenko
+
+	This program is free software; you can redistribute it and/or modify
+	it under the terms of the GNU General Public License as published by
+	the Free Software Foundation, either version 2 of the License, or
+	(at your option) any later version.
+
+	This program is distributed in the hope that it will be useful,
+	but WITHOUT ANY WARRANTY; without even the implied warranty of
+	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+	GNU General Public License for more details.
+
+	You should have received a copy of the GNU General Public License along
+	with this program; if not, write to the Free Software Foundation, Inc.,
+	51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+*/
+
+#ifndef PLATFORM_H_INCLUDED
+#define PLATFORM_H_INCLUDED
+
+#if defined(__linux__) || defined(__GLIBC__) || defined(__GNU__)
+
+#ifndef __UBOOT__
+#include <endian.h>
+#include <byteswap.h>
+#endif
+#define exfat_bswap16(x) bswap_16(x)
+#define exfat_bswap32(x) bswap_32(x)
+#define exfat_bswap64(x) bswap_64(x)
+#define EXFAT_BYTE_ORDER __BYTE_ORDER
+#define EXFAT_LITTLE_ENDIAN __LITTLE_ENDIAN
+#define EXFAT_BIG_ENDIAN __BIG_ENDIAN
+
+#elif defined(__APPLE__)
+
+#include <machine/endian.h>
+#include <libkern/OSByteOrder.h>
+#define exfat_bswap16(x) OSSwapInt16(x)
+#define exfat_bswap32(x) OSSwapInt32(x)
+#define exfat_bswap64(x) OSSwapInt64(x)
+#define EXFAT_BYTE_ORDER BYTE_ORDER
+#define EXFAT_LITTLE_ENDIAN LITTLE_ENDIAN
+#define EXFAT_BIG_ENDIAN BIG_ENDIAN
+
+#elif defined(__FreeBSD__) || defined(__DragonFly__) || defined(__NetBSD__) || defined(__OpenBSD__)
+
+#include <sys/endian.h>
+#define exfat_bswap16(x) bswap16(x)
+#define exfat_bswap32(x) bswap32(x)
+#define exfat_bswap64(x) bswap64(x)
+#define EXFAT_BYTE_ORDER _BYTE_ORDER
+#define EXFAT_LITTLE_ENDIAN _LITTLE_ENDIAN
+#define EXFAT_BIG_ENDIAN _BIG_ENDIAN
+
+#elif defined(__sun)
+
+#include <endian.h>
+#define exfat_bswap16(x) bswap_16(x)
+#define exfat_bswap32(x) bswap_32(x)
+#define exfat_bswap64(x) bswap_64(x)
+#define EXFAT_BYTE_ORDER __BYTE_ORDER
+#define EXFAT_LITTLE_ENDIAN __LITTLE_ENDIAN
+#define EXFAT_BIG_ENDIAN __BIG_ENDIAN
+
+#else 
+#error Unknown platform
+#endif
+
+#endif /* ifndef PLATFORM_H_INCLUDED */
diff --git a/fs/exfat/repair.c b/fs/exfat/repair.c
new file mode 100644
index 00000000000..9c91239b899
--- /dev/null
+++ b/fs/exfat/repair.c
@@ -0,0 +1,115 @@
+/*
+	repair.c (09.03.17)
+	exFAT file system implementation library.
+
+	Free exFAT implementation.
+	Copyright (C) 2010-2023  Andrew Nayenko
+
+	This program is free software; you can redistribute it and/or modify
+	it under the terms of the GNU General Public License as published by
+	the Free Software Foundation, either version 2 of the License, or
+	(at your option) any later version.
+
+	This program is distributed in the hope that it will be useful,
+	but WITHOUT ANY WARRANTY; without even the implied warranty of
+	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+	GNU General Public License for more details.
+
+	You should have received a copy of the GNU General Public License along
+	with this program; if not, write to the Free Software Foundation, Inc.,
+	51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+*/
+
+#include "exfat.h"
+#ifndef __UBOOT__
+#include <strings.h>
+#endif
+
+int exfat_errors_fixed;
+
+bool exfat_ask_to_fix(const struct exfat* ef)
+{
+	const char* question = "Fix (Y/N)?";
+#ifndef __UBOOT__
+	char answer[8];
+	bool yeah, nope;
+#endif
+
+	switch (ef->repair)
+	{
+	case EXFAT_REPAIR_NO:
+		return false;
+	case EXFAT_REPAIR_YES:
+		printf("%s %s", question, "Y\n");
+		return true;
+	case EXFAT_REPAIR_ASK:
+#ifndef __UBOOT__
+		do
+		{
+			printf("%s ", question);
+			fflush(stdout);
+			if (fgets(answer, sizeof(answer), stdin))
+			{
+				yeah = strcasecmp(answer, "Y\n") == 0;
+				nope = strcasecmp(answer, "N\n") == 0;
+			}
+			else
+			{
+				yeah = false;
+				nope = true;
+			}
+		}
+		while (!yeah && !nope);
+		return yeah;
+#else
+	default:
+		/* Do not attempt to repair FS in U-Boot. */
+		return false;
+#endif
+	}
+	exfat_bug("invalid repair option value: %d", ef->repair);
+#ifdef __UBOOT__
+	return false;
+#endif
+}
+
+bool exfat_fix_invalid_vbr_checksum(const struct exfat* ef, void* sector,
+		uint32_t vbr_checksum)
+{
+	size_t i;
+	off_t sector_size = SECTOR_SIZE(*ef->sb);
+
+	for (i = 0; i < sector_size / sizeof(vbr_checksum); i++)
+		((le32_t*) sector)[i] = cpu_to_le32(vbr_checksum);
+	if (exfat_pwrite(ef->dev, sector, sector_size, 11 * sector_size) < 0)
+	{
+		exfat_error("failed to write correct VBR checksum");
+		return false;
+	}
+	exfat_errors_fixed++;
+	return true;
+}
+
+bool exfat_fix_invalid_node_checksum(UNUSED const struct exfat* ef,
+		struct exfat_node* node)
+{
+	/* checksum will be rewritten by exfat_flush_node() */
+	node->is_dirty = true;
+
+	exfat_errors_fixed++;
+	return true;
+}
+
+bool exfat_fix_unknown_entry(struct exfat* ef, struct exfat_node* dir,
+		const struct exfat_entry* entry, off_t offset)
+{
+	struct exfat_entry deleted = *entry;
+
+	deleted.type &= ~EXFAT_ENTRY_VALID;
+	if (exfat_generic_pwrite(ef, dir, &deleted, sizeof(struct exfat_entry),
+			offset) != sizeof(struct exfat_entry))
+		return false;
+
+	exfat_errors_fixed++;
+	return true;
+}
diff --git a/fs/exfat/time.c b/fs/exfat/time.c
new file mode 100644
index 00000000000..f2217dd7986
--- /dev/null
+++ b/fs/exfat/time.c
@@ -0,0 +1,175 @@
+/*
+	time.c (03.02.12)
+	exFAT file system implementation library.
+
+	Free exFAT implementation.
+	Copyright (C) 2010-2023  Andrew Nayenko
+
+	This program is free software; you can redistribute it and/or modify
+	it under the terms of the GNU General Public License as published by
+	the Free Software Foundation, either version 2 of the License, or
+	(at your option) any later version.
+
+	This program is distributed in the hope that it will be useful,
+	but WITHOUT ANY WARRANTY; without even the implied warranty of
+	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+	GNU General Public License for more details.
+
+	You should have received a copy of the GNU General Public License along
+	with this program; if not, write to the Free Software Foundation, Inc.,
+	51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+*/
+
+#include "exfat.h"
+
+/* timezone offset from UTC in seconds; positive for western timezones,
+   negative for eastern ones */
+static long exfat_timezone;
+
+#define SEC_IN_MIN 60ll
+#define SEC_IN_HOUR (60 * SEC_IN_MIN)
+#define SEC_IN_DAY (24 * SEC_IN_HOUR)
+#define SEC_IN_YEAR (365 * SEC_IN_DAY) /* not leap year */
+/* Unix epoch started at 0:00:00 UTC 1 January 1970 */
+#define UNIX_EPOCH_YEAR 1970
+/* exFAT epoch started at 0:00:00 UTC 1 January 1980 */
+#define EXFAT_EPOCH_YEAR 1980
+/* number of years from Unix epoch to exFAT epoch */
+#define EPOCH_DIFF_YEAR (EXFAT_EPOCH_YEAR - UNIX_EPOCH_YEAR)
+/* number of days from Unix epoch to exFAT epoch (considering leap days) */
+#define EPOCH_DIFF_DAYS (EPOCH_DIFF_YEAR * 365 + EPOCH_DIFF_YEAR / 4)
+/* number of seconds from Unix epoch to exFAT epoch (considering leap days) */
+#define EPOCH_DIFF_SEC (EPOCH_DIFF_DAYS * SEC_IN_DAY)
+/* number of leap years passed from exFAT epoch to the specified year
+   (excluding the specified year itself) */
+#define LEAP_YEARS(year) ((EXFAT_EPOCH_YEAR + (year) - 1) / 4 \
+		- (EXFAT_EPOCH_YEAR - 1) / 4)
+/* checks whether the specified year is leap */
+#define IS_LEAP_YEAR(year) ((EXFAT_EPOCH_YEAR + (year)) % 4 == 0)
+
+static const time_t days_in_year[] =
+{
+	/* Jan  Feb  Mar  Apr  May  Jun  Jul  Aug  Sep  Oct  Nov  Dec */
+	0,   0,  31,  59,  90, 120, 151, 181, 212, 243, 273, 304, 334
+};
+
+time_t exfat_exfat2unix(le16_t date, le16_t time, uint8_t centisec,
+		uint8_t tzoffset)
+{
+	time_t unix_time = EPOCH_DIFF_SEC;
+	uint16_t ndate = le16_to_cpu(date);
+	uint16_t ntime = le16_to_cpu(time);
+
+	uint16_t day    = ndate & 0x1f;      /* 5 bits, 1-31 */
+	uint16_t month  = ndate >> 5 & 0xf;  /* 4 bits, 1-12 */
+	uint16_t year   = ndate >> 9;        /* 7 bits, 1-127 (+1980) */
+
+	uint16_t twosec = ntime & 0x1f;      /* 5 bits, 0-29 (2 sec granularity) */
+	uint16_t min    = ntime >> 5 & 0x3f; /* 6 bits, 0-59 */
+	uint16_t hour   = ntime >> 11;       /* 5 bits, 0-23 */
+
+	if (day == 0 || month == 0 || month > 12)
+	{
+		exfat_error("bad date %u-%02hu-%02hu",
+				year + EXFAT_EPOCH_YEAR, month, day);
+		return 0;
+	}
+	if (hour > 23 || min > 59 || twosec > 29)
+	{
+		exfat_error("bad time %hu:%02hu:%02u",
+				hour, min, twosec * 2);
+		return 0;
+	}
+	if (centisec > 199)
+	{
+		exfat_error("bad centiseconds count %hhu", centisec);
+		return 0;
+	}
+
+	/* every 4th year between 1904 and 2096 is leap */
+	unix_time += year * SEC_IN_YEAR + LEAP_YEARS(year) * SEC_IN_DAY;
+	unix_time += days_in_year[month] * SEC_IN_DAY;
+	/* if it's leap year and February has passed we should add 1 day */
+	if ((EXFAT_EPOCH_YEAR + year) % 4 == 0 && month > 2)
+		unix_time += SEC_IN_DAY;
+	unix_time += (day - 1) * SEC_IN_DAY;
+
+	unix_time += hour * SEC_IN_HOUR;
+	unix_time += min * SEC_IN_MIN;
+	/* exFAT represents time with 2 sec granularity */
+	unix_time += twosec * 2;
+	unix_time += centisec / 100;
+
+	/* exFAT stores timestamps in local time, so we correct it to UTC */
+	if (tzoffset & 0x80)
+		/* lower 7 bits are signed timezone offset in 15 minute increments */
+		unix_time -= (int8_t)(tzoffset << 1) * 15 * 60 / 2;
+	else
+		/* timezone offset not present, assume our local timezone */
+		unix_time += exfat_timezone;
+
+	return unix_time;
+}
+
+void exfat_unix2exfat(time_t unix_time, le16_t* date, le16_t* time,
+		uint8_t* centisec, uint8_t* tzoffset)
+{
+	time_t shift = EPOCH_DIFF_SEC + exfat_timezone;
+	uint16_t day, month, year;
+	uint16_t twosec, min, hour;
+	int days;
+	int i;
+
+	/* time before exFAT epoch cannot be represented */
+	if (unix_time < shift)
+		unix_time = shift;
+
+	unix_time -= shift;
+
+	days = unix_time / SEC_IN_DAY;
+	year = (4 * days) / (4 * 365 + 1);
+	days -= year * 365 + LEAP_YEARS(year);
+	month = 0;
+	for (i = 1; i <= 12; i++)
+	{
+		int leap_day = (IS_LEAP_YEAR(year) && i == 2);
+		int leap_sub = (IS_LEAP_YEAR(year) && i >= 3);
+
+		if (i == 12 || days - leap_sub < days_in_year[i + 1] + leap_day)
+		{
+			month = i;
+			days -= days_in_year[i] + leap_sub;
+			break;
+		}
+	}
+	day = days + 1;
+
+	hour = (unix_time % SEC_IN_DAY) / SEC_IN_HOUR;
+	min = (unix_time % SEC_IN_HOUR) / SEC_IN_MIN;
+	twosec = (unix_time % SEC_IN_MIN) / 2;
+
+	*date = cpu_to_le16(day | (month << 5) | (year << 9));
+	*time = cpu_to_le16(twosec | (min << 5) | (hour << 11));
+	if (centisec)
+		*centisec = (unix_time % 2) * 100;
+
+	/* record our local timezone offset in exFAT (15 minute increment) format */
+	*tzoffset = (uint8_t)(-exfat_timezone / 60 / 15) | 0x80;
+}
+
+void exfat_tzset(void)
+{
+#ifndef __UBOOT__
+	time_t now;
+	struct tm* utc;
+
+	tzset();
+	now = time(NULL);
+	utc = gmtime(&now);
+	/* gmtime() always sets tm_isdst to 0 because daylight savings never
+	   affect UTC. Setting tm_isdst to -1 makes mktime() to determine whether
+	   summer time is in effect. */
+	utc->tm_isdst = -1;
+	exfat_timezone = mktime(utc) - now;
+#endif
+}
diff --git a/fs/exfat/utf.c b/fs/exfat/utf.c
new file mode 100644
index 00000000000..8a28e7621ca
--- /dev/null
+++ b/fs/exfat/utf.c
@@ -0,0 +1,254 @@
+/*
+	utf.c (13.09.09)
+	exFAT file system implementation library.
+
+	Free exFAT implementation.
+	Copyright (C) 2010-2023  Andrew Nayenko
+
+	This program is free software; you can redistribute it and/or modify
+	it under the terms of the GNU General Public License as published by
+	the Free Software Foundation, either version 2 of the License, or
+	(at your option) any later version.
+
+	This program is distributed in the hope that it will be useful,
+	but WITHOUT ANY WARRANTY; without even the implied warranty of
+	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+	GNU General Public License for more details.
+
+	You should have received a copy of the GNU General Public License along
+	with this program; if not, write to the Free Software Foundation, Inc.,
+	51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+*/
+
+#include "exfat.h"
+#include <errno.h>
+
+static char* wchar_to_utf8(char* output, u32 wc, size_t outsize)
+{
+	if (wc <= 0x7f)
+	{
+		if (outsize < 1)
+			return NULL;
+		*output++ = (char) wc;
+	}
+	else if (wc <= 0x7ff)
+	{
+		if (outsize < 2)
+			return NULL;
+		*output++ = 0xc0 | (wc >> 6);
+		*output++ = 0x80 | (wc & 0x3f);
+	}
+	else if (wc <= 0xffff)
+	{
+		if (outsize < 3)
+			return NULL;
+		*output++ = 0xe0 | (wc >> 12);
+		*output++ = 0x80 | ((wc >> 6) & 0x3f);
+		*output++ = 0x80 | (wc & 0x3f);
+	}
+	else if (wc <= 0x1fffff)
+	{
+		if (outsize < 4)
+			return NULL;
+		*output++ = 0xf0 | (wc >> 18);
+		*output++ = 0x80 | ((wc >> 12) & 0x3f);
+		*output++ = 0x80 | ((wc >> 6) & 0x3f);
+		*output++ = 0x80 | (wc & 0x3f);
+	}
+	else if (wc <= 0x3ffffff)
+	{
+		if (outsize < 5)
+			return NULL;
+		*output++ = 0xf8 | (wc >> 24);
+		*output++ = 0x80 | ((wc >> 18) & 0x3f);
+		*output++ = 0x80 | ((wc >> 12) & 0x3f);
+		*output++ = 0x80 | ((wc >> 6) & 0x3f);
+		*output++ = 0x80 | (wc & 0x3f);
+	}
+	else if (wc <= 0x7fffffff)
+	{
+		if (outsize < 6)
+			return NULL;
+		*output++ = 0xfc | (wc >> 30);
+		*output++ = 0x80 | ((wc >> 24) & 0x3f);
+		*output++ = 0x80 | ((wc >> 18) & 0x3f);
+		*output++ = 0x80 | ((wc >> 12) & 0x3f);
+		*output++ = 0x80 | ((wc >> 6) & 0x3f);
+		*output++ = 0x80 | (wc & 0x3f);
+	}
+	else
+		return NULL;
+
+	return output;
+}
+
+static const le16_t* utf16_to_wchar(const le16_t* input, u32* wc,
+		size_t insize)
+{
+	if ((le16_to_cpu(input[0]) & 0xfc00) == 0xd800)
+	{
+		if (insize < 2 || (le16_to_cpu(input[1]) & 0xfc00) != 0xdc00)
+			return NULL;
+		*wc = ((u32) (le16_to_cpu(input[0]) & 0x3ff) << 10);
+		*wc |= (le16_to_cpu(input[1]) & 0x3ff);
+		*wc += 0x10000;
+		return input + 2;
+	}
+	else
+	{
+		*wc = le16_to_cpu(*input);
+		return input + 1;
+	}
+}
+
+int exfat_utf16_to_utf8(char* output, const le16_t* input, size_t outsize,
+		size_t insize)
+{
+	const le16_t* iptr = input;
+	const le16_t* iend = input + insize;
+	char* optr = output;
+	const char* oend = output + outsize;
+	u32 wc;
+
+	while (iptr < iend)
+	{
+		iptr = utf16_to_wchar(iptr, &wc, iend - iptr);
+		if (iptr == NULL)
+		{
+			exfat_error("illegal UTF-16 sequence");
+			return -EILSEQ;
+		}
+		optr = wchar_to_utf8(optr, wc, oend - optr);
+		if (optr == NULL)
+		{
+			exfat_error("name is too long");
+			return -ENAMETOOLONG;
+		}
+		if (wc == 0)
+			return 0;
+	}
+	if (optr >= oend)
+	{
+		exfat_error("name is too long");
+		return -ENAMETOOLONG;
+	}
+	*optr = '\0';
+	return 0;
+}
+
+static const char* utf8_to_wchar(const char* input, u32* wc,
+		size_t insize)
+{
+	size_t size;
+	size_t i;
+
+	if (insize == 0)
+		exfat_bug("no input for utf8_to_wchar");
+
+	if ((input[0] & 0x80) == 0)
+	{
+		*wc = (u32) input[0];
+		return input + 1;
+	}
+	else if ((input[0] & 0xe0) == 0xc0)
+	{
+		*wc = ((u32) input[0] & 0x1f) << 6;
+		size = 2;
+	}
+	else if ((input[0] & 0xf0) == 0xe0)
+	{
+		*wc = ((u32) input[0] & 0x0f) << 12;
+		size = 3;
+	}
+	else if ((input[0] & 0xf8) == 0xf0)
+	{
+		*wc = ((u32) input[0] & 0x07) << 18;
+		size = 4;
+	}
+	else if ((input[0] & 0xfc) == 0xf8)
+	{
+		*wc = ((u32) input[0] & 0x03) << 24;
+		size = 5;
+	}
+	else if ((input[0] & 0xfe) == 0xfc)
+	{
+		*wc = ((u32) input[0] & 0x01) << 30;
+		size = 6;
+	}
+	else
+		return NULL;
+
+	if (insize < size)
+		return NULL;
+
+	/* the first byte is handled above */
+	for (i = 1; i < size; i++)
+	{
+		if ((input[i] & 0xc0) != 0x80)
+			return NULL;
+		*wc |= (input[i] & 0x3f) << ((size - i - 1) * 6);
+	}
+
+	return input + size;
+}
+
+static le16_t* wchar_to_utf16(le16_t* output, u32 wc, size_t outsize)
+{
+	if (wc <= 0xffff) /* if character is from BMP */
+	{
+		if (outsize == 0)
+			return NULL;
+		output[0] = cpu_to_le16(wc);
+		return output + 1;
+	}
+	if (outsize < 2)
+		return NULL;
+	wc -= 0x10000;
+	output[0] = cpu_to_le16(0xd800 | ((wc >> 10) & 0x3ff));
+	output[1] = cpu_to_le16(0xdc00 | (wc & 0x3ff));
+	return output + 2;
+}
+
+int exfat_utf8_to_utf16(le16_t* output, const char* input, size_t outsize,
+		size_t insize)
+{
+	const char* iptr = input;
+	const char* iend = input + insize;
+	le16_t* optr = output;
+	const le16_t* oend = output + outsize;
+	u32 wc;
+
+	while (iptr < iend)
+	{
+		iptr = utf8_to_wchar(iptr, &wc, iend - iptr);
+		if (iptr == NULL)
+		{
+			exfat_error("illegal UTF-8 sequence");
+			return -EILSEQ;
+		}
+		optr = wchar_to_utf16(optr, wc, oend - optr);
+		if (optr == NULL)
+		{
+			exfat_error("name is too long");
+			return -ENAMETOOLONG;
+		}
+		if (wc == 0)
+			break;
+	}
+	if (optr >= oend)
+	{
+		exfat_error("name is too long");
+		return -ENAMETOOLONG;
+	}
+	*optr = cpu_to_le16(0);
+	return 0;
+}
+
+size_t exfat_utf16_length(const le16_t* str)
+{
+	size_t i = 0;
+
+	while (le16_to_cpu(str[i]))
+		i++;
+	return i;
+}
diff --git a/fs/exfat/utils.c b/fs/exfat/utils.c
new file mode 100644
index 00000000000..0d97b65dcab
--- /dev/null
+++ b/fs/exfat/utils.c
@@ -0,0 +1,192 @@
+/*
+	utils.c (04.09.09)
+	exFAT file system implementation library.
+
+	Free exFAT implementation.
+	Copyright (C) 2010-2023  Andrew Nayenko
+
+	This program is free software; you can redistribute it and/or modify
+	it under the terms of the GNU General Public License as published by
+	the Free Software Foundation, either version 2 of the License, or
+	(at your option) any later version.
+
+	This program is distributed in the hope that it will be useful,
+	but WITHOUT ANY WARRANTY; without even the implied warranty of
+	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+	GNU General Public License for more details.
+
+	You should have received a copy of the GNU General Public License along
+	with this program; if not, write to the Free Software Foundation, Inc.,
+	51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+*/
+
+#include "exfat.h"
+#include <string.h>
+#include <stdio.h>
+#include <inttypes.h>
+
+void exfat_stat(const struct exfat* ef, const struct exfat_node* node,
+		struct stat* stbuf)
+{
+	memset(stbuf, 0, sizeof(struct stat));
+	if (node->attrib & EXFAT_ATTRIB_DIR)
+		stbuf->st_mode = S_IFDIR | (0777 & ~ef->dmask);
+	else
+		stbuf->st_mode = S_IFREG | (0777 & ~ef->fmask);
+	stbuf->st_nlink = 1;
+	stbuf->st_uid = ef->uid;
+	stbuf->st_gid = ef->gid;
+	stbuf->st_size = node->size;
+	stbuf->st_blocks = ROUND_UP(node->size, CLUSTER_SIZE(*ef->sb)) / 512;
+	stbuf->st_mtime = node->mtime;
+	stbuf->st_atime = node->atime;
+	/* set ctime to mtime to ensure we don't break programs that rely on ctime
+	   (e.g. rsync) */
+	stbuf->st_ctime = node->mtime;
+}
+
+void exfat_get_name(const struct exfat_node* node,
+		char buffer[EXFAT_UTF8_NAME_BUFFER_MAX])
+{
+	if (exfat_utf16_to_utf8(buffer, node->name, EXFAT_UTF8_NAME_BUFFER_MAX,
+				EXFAT_NAME_MAX) != 0)
+		exfat_bug("failed to convert name to UTF-8");
+}
+
+static uint16_t add_checksum_byte(uint16_t sum, uint8_t byte)
+{
+	return ((sum << 15) | (sum >> 1)) + byte;
+}
+
+static uint16_t add_checksum_bytes(uint16_t sum, const void* buffer, size_t n)
+{
+	size_t i;
+
+	for (i = 0; i < n; i++)
+		sum = add_checksum_byte(sum, ((const uint8_t*) buffer)[i]);
+	return sum;
+}
+
+uint16_t exfat_start_checksum(const struct exfat_entry_meta1* entry)
+{
+	uint16_t sum = 0;
+	size_t i;
+
+	for (i = 0; i < sizeof(struct exfat_entry); i++)
+		if (i != 2 && i != 3) /* skip checksum field itself */
+			sum = add_checksum_byte(sum, ((const uint8_t*) entry)[i]);
+	return sum;
+}
+
+uint16_t exfat_add_checksum(const void* entry, uint16_t sum)
+{
+	return add_checksum_bytes(sum, entry, sizeof(struct exfat_entry));
+}
+
+le16_t exfat_calc_checksum(const struct exfat_entry* entries, int n)
+{
+	uint16_t checksum;
+	int i;
+
+	checksum = exfat_start_checksum((const struct exfat_entry_meta1*) entries);
+	for (i = 1; i < n; i++)
+		checksum = exfat_add_checksum(entries + i, checksum);
+	return cpu_to_le16(checksum);
+}
+
+uint32_t exfat_vbr_start_checksum(const void* sector, size_t size)
+{
+	size_t i;
+	uint32_t sum = 0;
+
+	for (i = 0; i < size; i++)
+		/* skip volume_state and allocated_percent fields */
+		if (i != 0x6a && i != 0x6b && i != 0x70)
+			sum = ((sum << 31) | (sum >> 1)) + ((const uint8_t*) sector)[i];
+	return sum;
+}
+
+uint32_t exfat_vbr_add_checksum(const void* sector, size_t size, uint32_t sum)
+{
+	size_t i;
+
+	for (i = 0; i < size; i++)
+		sum = ((sum << 31) | (sum >> 1)) + ((const uint8_t*) sector)[i];
+	return sum;
+}
+
+le16_t exfat_calc_name_hash(const struct exfat* ef, const le16_t* name,
+		size_t length)
+{
+	size_t i;
+	uint16_t hash = 0;
+
+	for (i = 0; i < length; i++)
+	{
+		uint16_t c = le16_to_cpu(name[i]);
+
+		/* convert to upper case */
+		c = ef->upcase[c];
+
+		hash = ((hash << 15) | (hash >> 1)) + (c & 0xff);
+		hash = ((hash << 15) | (hash >> 1)) + (c >> 8);
+	}
+	return cpu_to_le16(hash);
+}
+
+void exfat_humanize_bytes(uint64_t value, struct exfat_human_bytes* hb)
+{
+	size_t i;
+	/* 16 EB (minus 1 byte) is the largest size that can be represented by
+	   uint64_t */
+	const char* units[] = {"bytes", "KB", "MB", "GB", "TB", "PB", "EB"};
+	uint64_t divisor = 1;
+	uint64_t temp = 0;
+
+	for (i = 0; ; i++, divisor *= 1024)
+	{
+		temp = (value + divisor / 2) / divisor;
+
+		if (temp == 0)
+			break;
+		if (temp / 1024 * 1024 == temp)
+			continue;
+		if (temp < 10240)
+			break;
+	}
+	hb->value = temp;
+	hb->unit = units[i];
+}
+
+void exfat_print_info(const struct exfat_super_block* sb,
+		uint32_t free_clusters)
+{
+	struct exfat_human_bytes hb;
+	off_t total_space = le64_to_cpu(sb->sector_count) * SECTOR_SIZE(*sb);
+	off_t avail_space = (off_t) free_clusters * CLUSTER_SIZE(*sb);
+
+	printf("File system version           %hhu.%hhu\n",
+			sb->version.major, sb->version.minor);
+	exfat_humanize_bytes(SECTOR_SIZE(*sb), &hb);
+	printf("Sector size          %10"PRIu64" %s\n", hb.value, hb.unit);
+	exfat_humanize_bytes(CLUSTER_SIZE(*sb), &hb);
+	printf("Cluster size         %10"PRIu64" %s\n", hb.value, hb.unit);
+	exfat_humanize_bytes(total_space, &hb);
+	printf("Volume size          %10"PRIu64" %s\n", hb.value, hb.unit);
+	exfat_humanize_bytes(total_space - avail_space, &hb);
+	printf("Used space           %10"PRIu64" %s\n", hb.value, hb.unit);
+	exfat_humanize_bytes(avail_space, &hb);
+	printf("Available space      %10"PRIu64" %s\n", hb.value, hb.unit);
+}
+
+bool exfat_match_option(const char* options, const char* option_name)
+{
+	const char* p;
+	size_t length = strlen(option_name);
+
+	for (p = strstr(options, option_name); p; p = strstr(p + 1, option_name))
+		if ((p == options || p[-1] == ',') &&
+				(p[length] == ',' || p[length] == '\0'))
+			return true;
+	return false;
+}
diff --git a/fs/fat/Kconfig b/fs/fat/Kconfig
index 9bb11eac9f7..19d52238713 100644
--- a/fs/fat/Kconfig
+++ b/fs/fat/Kconfig
@@ -13,6 +13,13 @@ config FAT_WRITE
 	  This provides support for creating and writing new files to an
 	  existing FAT filesystem partition.
 
+config FAT_RENAME
+	bool "Enable filesystem rename support"
+	depends on FAT_WRITE
+	help
+	  This provides support for renaming and moving files within a
+	  FAT filesystem partition.
+
 config FS_FAT_MAX_CLUSTSIZE
 	int "Set maximum possible clustersize"
 	default 65536
diff --git a/fs/fat/fat_write.c b/fs/fat/fat_write.c
index ea877ee9171..0b924541187 100644
--- a/fs/fat/fat_write.c
+++ b/fs/fat/fat_write.c
@@ -1216,6 +1216,124 @@ static void fill_dentry(fsdata *mydata, dir_entry *dentptr,
 }
 
 /**
+ * fat_itr_parent() - modifies the iterator to the parent directory of the
+ * current iterator.
+ *
+ * @itr:	iterator positioned anywhere in a directory
+ * @Return:	0 if the iterator is in the parent directory, -errno otherwise
+ */
+static int fat_itr_parent(fat_itr *itr)
+{
+	int ret;
+
+	if (itr->is_root)
+		return -EIO;
+
+	/* ensure iterator is at the first directory entry */
+	ret = fat_move_to_cluster(itr, itr->start_clust);
+	if (ret)
+		return ret;
+
+	return fat_itr_resolve(itr, "..", TYPE_DIR);
+}
+
+/**
+ * update_parent_dir_props - updates the modified time for the parent directory
+ *
+ * @dir_itr:	iterator positioned anywhere in a directory whose parent
+ * should be updated
+ * @Return:	0 for success, -errno otherwise
+ */
+static int update_parent_dir_props(fat_itr *dir_itr)
+{
+	int ret = 0;
+
+	fat_itr itr;
+	fsdata fsdata = { .fatbuf = NULL, }, *mydata = &fsdata;
+	__u32 target_clust = dir_itr->start_clust;
+
+	/* Short circuit if no RTC because it only updates timestamps */
+	if (!CONFIG_IS_ENABLED(DM_RTC))
+		return ret;
+
+	/* duplicate fsdata */
+	itr = *dir_itr;
+	fsdata = *itr.fsdata;
+
+	/* allocate local fat buffer */
+	fsdata.fatbuf = malloc_cache_aligned(FATBUFSIZE);
+	if (!fsdata.fatbuf) {
+		log_debug("Error: allocating memory\n");
+		ret = -ENOMEM;
+		return ret;
+	}
+
+	fsdata.fatbufnum = -1;
+	itr.fsdata = &fsdata;
+
+	if (!itr.is_root) {
+		ret = fat_itr_parent(&itr);
+		if (ret)
+			goto exit;
+
+		while (fat_itr_next(&itr)) {
+			if (START(itr.dent) == target_clust)
+				goto update;
+		}
+
+		/* dent not found */
+		ret = -EIO;
+		goto exit;
+update:
+		dentry_set_time(itr.dent);
+		ret = flush_dir(&itr);
+	}
+
+exit:
+	free(fsdata.fatbuf);
+
+	return ret;
+}
+
+/**
+ * create_link() - inserts a directory entry for a file or directory
+ *
+ * @itr:	directory iterator
+ * @basename:	file name
+ * @clust:	cluster number the new directory entry should point to. Use 0
+ * if no cluster is assigned yet
+ * @size:	file size
+ * @attr:	file attributes
+ * Return:	0 for success
+ */
+static int create_link(fat_itr *itr, char *basename, __u32 clust, __u32 size,
+		       __u8 attr)
+{
+	char shortname[SHORT_NAME_SIZE];
+	int ndent;
+	int ret;
+
+	/* Check if long name is needed */
+	ndent = set_name(itr, basename, shortname);
+	if (ndent < 0)
+		return ndent;
+	ret = fat_find_empty_dentries(itr, ndent);
+	if (ret)
+		return ret;
+	if (ndent > 1) {
+		/* Set long name entries */
+		ret = fill_dir_slot(itr, basename, shortname);
+		if (ret)
+			return ret;
+	}
+
+	fill_dentry(itr->fsdata, itr->dent, shortname, clust, size, attr);
+	ret = update_parent_dir_props(itr);
+
+	return ret;
+}
+
+/**
  * find_directory_entry() - find a directory entry by filename
  *
  * @itr:	directory iterator
@@ -1420,35 +1538,15 @@ int file_fat_write_at(const char *filename, loff_t pos, void *buffer,
 		/* Update change date */
 		dentry_set_time(retdent);
 	} else {
-		/* Create a new file */
-		char shortname[SHORT_NAME_SIZE];
-		int ndent;
-
 		if (pos) {
 			/* No hole allowed */
 			ret = -EINVAL;
 			goto exit;
 		}
 
-		/* Check if long name is needed */
-		ndent = set_name(itr, basename, shortname);
-		if (ndent < 0) {
-			ret = ndent;
-			goto exit;
-		}
-		ret = fat_find_empty_dentries(itr, ndent);
+		ret = create_link(itr, basename, 0, size, ATTR_ARCH);
 		if (ret)
 			goto exit;
-		if (ndent > 1) {
-			/* Set long name entries */
-			ret = fill_dir_slot(itr, basename, shortname);
-			if (ret)
-				goto exit;
-		}
-
-		/* Set short name entry */
-		fill_dentry(itr->fsdata, itr->dent, shortname, 0, size,
-			    ATTR_ARCH);
 
 		retdent = itr->dent;
 	}
@@ -1565,6 +1663,36 @@ static int delete_long_name(fat_itr *itr)
 }
 
 /**
+ * delete_dentry_link() - deletes a directory entry, but not the cluster chain
+ * it points to
+ *
+ * @itr:	the first directory entry (if a longname) to remove
+ * Return:	0 for success
+ */
+static int delete_dentry_link(fat_itr *itr)
+{
+	int ret;
+
+	itr->dent = itr->dent_start;
+	itr->remaining = itr->dent_rem;
+	/* Delete long name */
+	if ((itr->dent->attr & ATTR_VFAT) == ATTR_VFAT &&
+	    (itr->dent->nameext.name[0] & LAST_LONG_ENTRY_MASK)) {
+		ret = delete_long_name(itr);
+		if (ret)
+			return ret;
+	}
+	/* Delete short name */
+	delete_single_dentry(itr);
+
+	ret = flush_dir(itr);
+	if (ret)
+		return ret;
+
+	return update_parent_dir_props(itr);
+}
+
+/**
  * delete_dentry_long() - remove directory entry
  *
  * @itr:	directory iterator
@@ -1589,21 +1717,7 @@ static int delete_dentry_long(fat_itr *itr)
 		if (ret)
 			return ret;
 	}
-	itr->dent = itr->dent_start;
-	itr->remaining = itr->dent_rem;
-	dent = itr->dent_start;
-	/* Delete long name */
-	if ((dent->attr & ATTR_VFAT) == ATTR_VFAT &&
-	    (dent->nameext.name[0] & LAST_LONG_ENTRY_MASK)) {
-		int ret;
-
-		ret = delete_long_name(itr);
-		if (ret)
-			return ret;
-	}
-	/* Delete short name */
-	delete_single_dentry(itr);
-	return flush_dir(itr);
+	return delete_dentry_link(itr);
 }
 
 int fat_unlink(const char *filename)
@@ -1725,9 +1839,6 @@ int fat_mkdir(const char *dirname)
 		ret = -EEXIST;
 		goto exit;
 	} else {
-		char shortname[SHORT_NAME_SIZE];
-		int ndent;
-
 		if (itr->is_root) {
 			/* root dir cannot have "." or ".." */
 			if (!strcmp(l_dirname, ".") ||
@@ -1737,25 +1848,9 @@ int fat_mkdir(const char *dirname)
 			}
 		}
 
-		/* Check if long name is needed */
-		ndent = set_name(itr, basename, shortname);
-		if (ndent < 0) {
-			ret = ndent;
-			goto exit;
-		}
-		ret = fat_find_empty_dentries(itr, ndent);
+		ret = create_link(itr, basename, 0, 0, ATTR_DIR | ATTR_ARCH);
 		if (ret)
 			goto exit;
-		if (ndent > 1) {
-			/* Set long name entries */
-			ret = fill_dir_slot(itr, basename, shortname);
-			if (ret)
-				goto exit;
-		}
-
-		/* Set attribute as archive for regular file */
-		fill_dentry(itr->fsdata, itr->dent, shortname, 0, 0,
-			    ATTR_DIR | ATTR_ARCH);
 
 		retdent = itr->dent;
 	}
@@ -1813,3 +1908,272 @@ exit:
 	free(dotdent);
 	return ret;
 }
+
+/**
+ * check_path_prefix() - ensures one path does not contains another path as a
+ * prefix.
+ *
+ * for example: path foo/bar/baz/qux contains the path prefix foo/bar/baz
+ *
+ * note: the iterator may be pointing to any directory entry in the directory
+ *
+ * @prefix_clust:	start cluster of the final directory in the prefix path
+ * (the start cluster of 'baz' in the above example)
+ * @path_itr:	iterator of the path to check (an iterator pointing to any
+ * direntry in 'qux' in the above example)
+ * Return:	-errno on error, 0 if path_itr does not have the directory
+ * at prefix_clust as an ancestor.
+ */
+static int check_path_prefix(loff_t prefix_clust, fat_itr *path_itr)
+{
+	fat_itr itr;
+	fsdata fsdata = { .fatbuf = NULL, }, *mydata = &fsdata;
+	int ret;
+
+	/* duplicate fsdata */
+	itr = *path_itr;
+	fsdata = *itr.fsdata;
+
+	/* allocate local fat buffer */
+	fsdata.fatbuf = malloc_cache_aligned(FATBUFSIZE);
+	if (!fsdata.fatbuf) {
+		log_debug("Error: allocating memory\n");
+		ret = -ENOMEM;
+		goto exit;
+	}
+
+	fsdata.fatbufnum = -1;
+	itr.fsdata = &fsdata;
+
+	/* ensure iterator is at the first directory entry */
+	ret = fat_move_to_cluster(&itr, itr.start_clust);
+	if (ret)
+		goto exit;
+
+	while (1) {
+		if (prefix_clust == itr.start_clust) {
+			ret = -EINVAL;
+			goto exit;
+		}
+
+		if (itr.is_root) {
+			ret = 0;
+			goto exit;
+		}
+
+		/* Should not occur in a well-formed FAT filesystem besides the root */
+		if (fat_itr_parent(&itr)) {
+			log_debug("FAT filesystem corrupt!\n");
+			log_debug("dir @ clust %u has no parent direntry\n",
+				  itr.start_clust);
+			ret = -EIO;
+			goto exit;
+		}
+	}
+
+exit:
+	free(fsdata.fatbuf);
+	return ret;
+}
+
+/**
+ * fat_rename - rename/move a file or directory
+ *
+ * @old_path:	path to the existing file/directory
+ * @new_path:	new path/name for the rename/move
+ * Return:	0 on success, -errno otherwise
+ */
+int fat_rename(const char *old_path, const char *new_path)
+{
+	fat_itr *old_itr = NULL, *new_itr = NULL;
+	fsdata old_datablock = { .fatbuf = NULL, };
+	fsdata new_datablock = { .fatbuf = NULL, };
+	/* used for START macro */
+	fsdata *mydata = &old_datablock;
+	int ret = -EIO, is_old_dir;
+	char *old_path_copy, *old_dirname, *old_basename;
+	char *new_path_copy, *new_dirname, *new_basename;
+	char l_new_basename[VFAT_MAXLEN_BYTES];
+	__u32 old_clust;
+	dir_entry *found_existing;
+	/* only set if found_existing != NULL */
+	__u32 new_clust;
+
+	old_path_copy = strdup(old_path);
+	new_path_copy = strdup(new_path);
+	old_itr = malloc_cache_aligned(sizeof(fat_itr));
+	new_itr = malloc_cache_aligned(sizeof(fat_itr));
+	if (!old_path_copy || !new_path_copy || !old_itr || !new_itr) {
+		log_debug("Error: out of memory\n");
+		ret = -ENOMEM;
+		goto exit;
+	}
+	split_filename(old_path_copy, &old_dirname, &old_basename);
+	split_filename(new_path_copy, &new_dirname, &new_basename);
+
+	if (normalize_longname(l_new_basename, new_basename)) {
+		log_debug("FAT: illegal filename (%s)\n", new_basename);
+		ret = -EINVAL;
+		goto exit;
+	}
+
+	if (!strcmp(old_basename, ".") || !strcmp(old_basename, "..") ||
+	    !strcmp(old_basename, "") || !strcmp(l_new_basename, ".") ||
+	    !strcmp(l_new_basename, "..") || !strcmp(l_new_basename, "")) {
+		ret = -EINVAL;
+		goto exit;
+	}
+
+	/* checking for old_path == new_path is deferred until they're resolved */
+
+	/* resolve old_path */
+	ret = fat_itr_root(old_itr, &old_datablock);
+	if (ret)
+		goto exit;
+
+	ret = fat_itr_resolve(old_itr, old_dirname, TYPE_DIR);
+	if (ret) {
+		log_debug("%s doesn't exist (%d)\n", old_dirname, ret);
+		ret = -ENOENT;
+		goto exit;
+	}
+
+	if (!find_directory_entry(old_itr, old_basename)) {
+		log_debug("%s doesn't exist (%d)\n", old_basename, -ENOENT);
+		ret = -ENOENT;
+		goto exit;
+	}
+
+	/* store clust old_path points to, to relink later */
+	total_sector = old_datablock.total_sect;
+	old_clust = START(old_itr->dent);
+	is_old_dir = fat_itr_isdir(old_itr);
+
+	/* resolve new_path*/
+	ret = fat_itr_root(new_itr, &new_datablock);
+	if (ret)
+		goto exit;
+
+	ret = fat_itr_resolve(new_itr, new_dirname, TYPE_DIR);
+	if (ret) {
+		log_debug("%s doesn't exist (%d)\n", new_dirname, ret);
+		ret = -ENOENT;
+		goto exit;
+	}
+
+	found_existing = find_directory_entry(new_itr, l_new_basename);
+
+	if (found_existing) {
+		/* store cluster of new_path since it may need to be deleted */
+		new_clust = START(new_itr->dent);
+
+		/* old_path is new_path, noop */
+		if (old_clust == new_clust) {
+			ret = 0;
+			goto exit;
+		}
+
+		if (fat_itr_isdir(new_itr) != is_old_dir) {
+			if (is_old_dir)
+				ret = -ENOTDIR;
+			else
+				ret = -EISDIR;
+			goto exit;
+		}
+	}
+
+	if (is_old_dir) {
+		ret = check_path_prefix(old_clust, new_itr);
+		if (ret)
+			goto exit;
+	}
+
+	/* create/update dentry to point to old_path's data cluster */
+	if (found_existing) {
+		struct nameext new_name = new_itr->dent->nameext;
+		__u8 lcase = new_itr->dent->lcase;
+
+		if (is_old_dir) {
+			int n_entries = fat_dir_entries(new_itr);
+
+			if (n_entries < 0) {
+				ret = n_entries;
+				goto exit;
+			}
+			if (n_entries > 2) {
+				log_debug("Error: directory is not empty: %d\n",
+					  n_entries);
+				ret = -ENOTEMPTY;
+				goto exit;
+			}
+		}
+
+		*new_itr->dent = *old_itr->dent;
+		new_itr->dent->nameext = new_name;
+		new_itr->dent->lcase = lcase;
+
+		ret = update_parent_dir_props(new_itr);
+		if (ret)
+			goto exit;
+	} else {
+		/* reset iterator to the start of the directory */
+		ret = fat_move_to_cluster(new_itr, new_itr->start_clust);
+		if (ret)
+			goto exit;
+
+		ret = create_link(new_itr, l_new_basename, old_clust,
+				  old_itr->dent->size,
+				  old_itr->dent->attr | ATTR_ARCH);
+		if (ret)
+			goto exit;
+	}
+
+	ret = flush_dir(new_itr);
+	if (ret)
+		goto exit;
+
+	/* with new_path data cluster unreferenced, clear it */
+	if (found_existing) {
+		ret = clear_fatent(&new_datablock, new_clust);
+		if (ret)
+			goto exit;
+	}
+
+	/* update moved directory so the parent is new_path */
+	if (is_old_dir) {
+		__u32 clust = new_itr->start_clust;
+		dir_entry *dent;
+
+		fat_itr_child(new_itr, new_itr);
+		dent = find_directory_entry(new_itr, "..");
+		if (!dent) {
+			log_debug("FAT filesystem corrupt!\n");
+			log_debug("dir %s has no parent direntry\n",
+				  l_new_basename);
+			ret = -EIO;
+			goto exit;
+		}
+		set_start_cluster(&new_datablock, dent, clust);
+		ret = flush_dir(new_itr);
+		if (ret)
+			goto exit;
+		/* restore directory location to update parent props below */
+		fat_itr_child(new_itr, new_itr);
+	}
+
+	/* refresh old in case write happened to the same block. */
+	ret = fat_move_to_cluster(old_itr, old_itr->dent_clust);
+	if (ret)
+		goto exit;
+
+	ret = delete_dentry_link(old_itr);
+exit:
+	free(new_datablock.fatbuf);
+	free(old_datablock.fatbuf);
+	free(new_itr);
+	free(old_itr);
+	free(new_path_copy);
+	free(old_path_copy);
+
+	return ret;
+}
diff --git a/fs/fs.c b/fs/fs.c
index 1ed7c0f2d2c..0b62217fd59 100644
--- a/fs/fs.c
+++ b/fs/fs.c
@@ -32,6 +32,7 @@
 #include <efi_loader.h>
 #include <squashfs.h>
 #include <erofs.h>
+#include <exfat.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -143,6 +144,12 @@ static inline int fs_mkdir_unsupported(const char *dirname)
 	return -1;
 }
 
+static inline int fs_rename_unsupported(const char *old_path,
+					const char *new_path)
+{
+	return -1;
+}
+
 struct fstype_info {
 	int fstype;
 	char *name;
@@ -183,6 +190,7 @@ struct fstype_info {
 	int (*unlink)(const char *filename);
 	int (*mkdir)(const char *dirname);
 	int (*ln)(const char *filename, const char *target);
+	int (*rename)(const char *old_path, const char *new_path);
 };
 
 static struct fstype_info fstypes[] = {
@@ -211,6 +219,11 @@ static struct fstype_info fstypes[] = {
 		.readdir = fat_readdir,
 		.closedir = fat_closedir,
 		.ln = fs_ln_unsupported,
+#if CONFIG_IS_ENABLED(FAT_RENAME) && !IS_ENABLED(CONFIG_XPL_BUILD)
+		.rename = fat_rename,
+#else
+		.rename = fs_rename_unsupported,
+#endif
 	},
 #endif
 
@@ -238,6 +251,7 @@ static struct fstype_info fstypes[] = {
 		.closedir = ext4fs_closedir,
 		.unlink = fs_unlink_unsupported,
 		.mkdir = fs_mkdir_unsupported,
+		.rename = fs_rename_unsupported,
 	},
 #endif
 #if IS_ENABLED(CONFIG_SANDBOX) && !IS_ENABLED(CONFIG_XPL_BUILD)
@@ -257,6 +271,7 @@ static struct fstype_info fstypes[] = {
 		.unlink = fs_unlink_unsupported,
 		.mkdir = fs_mkdir_unsupported,
 		.ln = fs_ln_unsupported,
+		.rename = fs_rename_unsupported,
 	},
 #endif
 #if CONFIG_IS_ENABLED(SEMIHOSTING)
@@ -276,6 +291,7 @@ static struct fstype_info fstypes[] = {
 		.unlink = fs_unlink_unsupported,
 		.mkdir = fs_mkdir_unsupported,
 		.ln = fs_ln_unsupported,
+		.rename = fs_rename_unsupported,
 	},
 #endif
 #ifndef CONFIG_XPL_BUILD
@@ -296,6 +312,7 @@ static struct fstype_info fstypes[] = {
 		.unlink = fs_unlink_unsupported,
 		.mkdir = fs_mkdir_unsupported,
 		.ln = fs_ln_unsupported,
+		.rename = fs_rename_unsupported,
 	},
 #endif
 #endif
@@ -317,6 +334,7 @@ static struct fstype_info fstypes[] = {
 		.unlink = fs_unlink_unsupported,
 		.mkdir = fs_mkdir_unsupported,
 		.ln = fs_ln_unsupported,
+		.rename = fs_rename_unsupported,
 	},
 #endif
 #endif
@@ -339,6 +357,7 @@ static struct fstype_info fstypes[] = {
 		.ln = fs_ln_unsupported,
 		.unlink = fs_unlink_unsupported,
 		.mkdir = fs_mkdir_unsupported,
+		.rename = fs_rename_unsupported,
 	},
 #endif
 #if IS_ENABLED(CONFIG_FS_EROFS)
@@ -360,6 +379,28 @@ static struct fstype_info fstypes[] = {
 		.ln = fs_ln_unsupported,
 		.unlink = fs_unlink_unsupported,
 		.mkdir = fs_mkdir_unsupported,
+		.rename = fs_rename_unsupported,
+	},
+#endif
+#if IS_ENABLED(CONFIG_FS_EXFAT)
+	{
+		.fstype = FS_TYPE_EXFAT,
+		.name = "exfat",
+		.null_dev_desc_ok = false,
+		.probe = exfat_fs_probe,
+		.opendir = exfat_fs_opendir,
+		.readdir = exfat_fs_readdir,
+		.ls = exfat_fs_ls,
+		.read = exfat_fs_read,
+		.size = exfat_fs_size,
+		.close = exfat_fs_close,
+		.closedir = exfat_fs_closedir,
+		.exists = exfat_fs_exists,
+		.uuid = fs_uuid_unsupported,
+		.write = exfat_fs_write,
+		.ln = fs_ln_unsupported,
+		.unlink = exfat_fs_unlink,
+		.mkdir = exfat_fs_mkdir,
 	},
 #endif
 	{
@@ -378,6 +419,7 @@ static struct fstype_info fstypes[] = {
 		.unlink = fs_unlink_unsupported,
 		.mkdir = fs_mkdir_unsupported,
 		.ln = fs_ln_unsupported,
+		.rename = fs_rename_unsupported,
 	},
 };
 
@@ -713,6 +755,22 @@ int fs_ln(const char *fname, const char *target)
 	return ret;
 }
 
+int fs_rename(const char *old_path, const char *new_path)
+{
+	struct fstype_info *info = fs_get_info(fs_type);
+	int ret;
+
+	ret = info->rename(old_path, new_path);
+
+	if (ret < 0) {
+		log_debug("Unable to rename %s -> %s\n", old_path, new_path);
+		ret = -1;
+	}
+	fs_close();
+
+	return ret;
+}
+
 int do_size(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[],
 	    int fstype)
 {
@@ -975,6 +1033,65 @@ int do_ln(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[],
 	return 0;
 }
 
+int do_mv(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[],
+	  int fstype)
+{
+	struct fs_dir_stream *dirs;
+	char *src = argv[3];
+	char *dst = argv[4];
+	char *new_dst = NULL;
+	int ret = 1;
+
+	if (argc != 5) {
+		ret = CMD_RET_USAGE;
+		goto exit;
+	}
+
+	if (fs_set_blk_dev(argv[1], argv[2], fstype))
+		goto exit;
+
+	dirs = fs_opendir(dst);
+	/* dirs being valid means dst points to an existing directory.
+	 * mv should copy the file/dir (keeping the same name) into the
+	 * directory
+	 */
+	if (dirs) {
+		char *src_name = strrchr(src, '/');
+		int dst_len;
+
+		if (src_name)
+			src_name += 1;
+		else
+			src_name = src;
+
+		dst_len = strlen(dst);
+		new_dst = calloc(1, dst_len + strlen(src_name) + 2);
+		strcpy(new_dst, dst);
+
+		/* If there is already a trailing slash, don't add another */
+		if (new_dst[dst_len - 1] != '/') {
+			new_dst[dst_len] = '/';
+			dst_len += 1;
+		}
+
+		strcpy(new_dst + dst_len, src_name);
+		dst = new_dst;
+	}
+	fs_closedir(dirs);
+
+	if (fs_set_blk_dev(argv[1], argv[2], fstype))
+		goto exit;
+
+	if (fs_rename(src, dst))
+		goto exit;
+
+	ret = 0;
+
+exit:
+	free(new_dst);
+	return ret;
+}
+
 int do_fs_types(struct cmd_tbl *cmdtp, int flag, int argc, char * const argv[])
 {
 	struct fstype_info *drv = fstypes;
diff --git a/fs/fs_internal.c b/fs/fs_internal.c
index 51c1719361b..ab4847ac257 100644
--- a/fs/fs_internal.c
+++ b/fs/fs_internal.c
@@ -92,3 +92,105 @@ int fs_devread(struct blk_desc *blk, struct disk_partition *partition,
 	}
 	return 1;
 }
+
+int fs_devwrite(struct blk_desc *blk, struct disk_partition *partition,
+	        lbaint_t sector, int byte_offset, int byte_len, const char *buf)
+{
+	unsigned block_len;
+	int log2blksz;
+	ALLOC_CACHE_ALIGN_BUFFER(char, sec_buf, (blk ? blk->blksz : 0));
+	if (blk == NULL) {
+		log_err("** Invalid Block Device Descriptor (NULL)\n");
+		return 0;
+	}
+	log2blksz = blk->log2blksz;
+
+	/* Check partition boundaries */
+	if ((sector + ((byte_offset + byte_len - 1) >> log2blksz))
+	    >= partition->size) {
+		log_debug("read outside partition " LBAFU "\n", sector);
+		return 0;
+	}
+
+	/* Get the read to the beginning of a partition */
+	sector += byte_offset >> log2blksz;
+	byte_offset &= blk->blksz - 1;
+
+	log_debug(" <" LBAFU ", %d, %d>\n", sector, byte_offset, byte_len);
+
+	if (byte_offset != 0) {
+		int readlen;
+		/* read first part which isn't aligned with start of sector */
+		if (blk_dread(blk, partition->start + sector, 1,
+			      (void *)sec_buf) != 1) {
+			log_err(" ** %s read error **\n", __func__);
+			return 0;
+		}
+
+		readlen = min((int)blk->blksz - byte_offset,
+			      byte_len);
+		memcpy(sec_buf + byte_offset, buf, readlen);
+
+		if (blk_dwrite(blk, partition->start + sector, 1,
+			      (void *)sec_buf) != 1) {
+			log_err(" ** %s write error **\n", __func__);
+			return 0;
+		}
+		buf += readlen;
+		byte_len -= readlen;
+		sector++;
+	}
+
+	if (byte_len == 0)
+		return 1;
+
+	/* write sector aligned part */
+	block_len = byte_len & ~(blk->blksz - 1);
+
+	if (block_len == 0) {
+		if (blk_dread(blk, partition->start + sector, 1,
+			  (void *)sec_buf) != 1) {
+			log_err(" ** %s read error **\n", __func__);
+			return 0;
+		}
+
+		memcpy(sec_buf, buf, byte_len);
+
+		if (blk_dwrite(blk, partition->start + sector, 1,
+			      (void *)sec_buf) != 1) {
+			log_err(" ** %s write error **\n", __func__);
+			return 0;
+		}
+
+		return 1;
+	}
+
+	if (blk_dwrite(blk, partition->start + sector,
+		       block_len >> log2blksz, (void *)buf) !=
+			block_len >> log2blksz) {
+		log_err(" ** %s write error - block\n", __func__);
+		return 0;
+	}
+	block_len = byte_len & ~(blk->blksz - 1);
+	buf += block_len;
+	byte_len -= block_len;
+	sector += block_len / blk->blksz;
+
+	if (byte_len != 0) {
+		/* read rest of data which are not in whole sector */
+		if (blk_dread(blk, partition->start + sector, 1,
+			      (void *)sec_buf) != 1) {
+			log_err("* %s read error - last part **\n", __func__);
+			return 0;
+		}
+
+		memcpy(sec_buf, buf, byte_len);
+
+		if (blk_dwrite(blk, partition->start + sector, 1,
+			      (void *)sec_buf) != 1) {
+			log_err(" ** %s write error - last part **\n", __func__);
+			return 0;
+		}
+	}
+	return 1;
+}
diff --git a/include/acpi/acpi_table.h b/include/acpi/acpi_table.h
index b8b1f1338c6..8ef19adc990 100644
--- a/include/acpi/acpi_table.h
+++ b/include/acpi/acpi_table.h
@@ -36,7 +36,7 @@ struct acpi_ctx;
  * RSDP (Root System Description Pointer)
  * Note: ACPI 1.0 didn't have length, xsdt_address, and ext_checksum
  */
-struct acpi_rsdp {
+struct __packed acpi_rsdp {
 	char signature[8];	/* RSDP signature */
 	u8 checksum;		/* Checksum of the first 20 bytes */
 	char oem_id[6];		/* OEM ID */
diff --git a/include/asm-generic/global_data.h b/include/asm-generic/global_data.h
index 789adf2c3f9..506ee51cdb0 100644
--- a/include/asm-generic/global_data.h
+++ b/include/asm-generic/global_data.h
@@ -23,7 +23,7 @@
 #include <board_f.h>
 #include <event_internal.h>
 #include <fdtdec.h>
-#include <membuff.h>
+#include <membuf.h>
 #include <linux/list.h>
 #include <linux/build_bug.h>
 #include <asm-offsets.h>
@@ -316,14 +316,14 @@ struct global_data {
 	 *
 	 * This buffer is used to collect output during console recording.
 	 */
-	struct membuff console_out;
+	struct membuf console_out;
 	/**
 	 * @console_in: input buffer for console recording
 	 *
 	 * If console recording is activated, this buffer can be used to
 	 * emulate input.
 	 */
-	struct membuff console_in;
+	struct membuf console_in;
 #endif
 #if CONFIG_IS_ENABLED(VIDEO)
 	/**
diff --git a/include/asm-generic/sections.h b/include/asm-generic/sections.h
index 3fd5c772a1a..024b1adde27 100644
--- a/include/asm-generic/sections.h
+++ b/include/asm-generic/sections.h
@@ -23,6 +23,7 @@ extern char __kprobes_text_start[], __kprobes_text_end[];
 extern char __entry_text_start[], __entry_text_end[];
 extern char __initdata_begin[], __initdata_end[];
 extern char __start_rodata[], __end_rodata[];
+extern char __start_data[], __end_data[];
 extern char __efi_helloworld_begin[];
 extern char __efi_helloworld_end[];
 extern char __efi_var_file_begin[];
@@ -63,6 +64,7 @@ static inline int arch_is_kernel_data(unsigned long addr)
 
 /* Start of U-Boot text region */
 extern char __text_start[];
+extern char __text_end[];
 
 /* This marks the text region which must be relocated */
 extern char __image_copy_start[], __image_copy_end[];
diff --git a/include/blkmap.h b/include/blkmap.h
index d53095437fa..57555fda4fb 100644
--- a/include/blkmap.h
+++ b/include/blkmap.h
@@ -7,6 +7,7 @@
 #ifndef _BLKMAP_H
 #define _BLKMAP_H
 
+#include <blk.h>
 #include <dm/lists.h>
 
 /**
@@ -60,10 +61,12 @@ int blkmap_map_mem(struct udevice *dev, lbaint_t blknr, lbaint_t blkcnt,
  * @blknr: Start block number of the mapping
  * @blkcnt: Number of blocks to map
  * @paddr: The target physical memory address of the mapping
+ * @preserve: Mapping intended to be preserved for subsequent stages,
+ *		like the OS (e.g. ISO installer)
  * Returns: 0 on success, negative error code on failure
  */
 int blkmap_map_pmem(struct udevice *dev, lbaint_t blknr, lbaint_t blkcnt,
-		    phys_addr_t paddr);
+		    phys_addr_t paddr, bool preserve);
 
 /**
  * blkmap_from_label() - Find blkmap from label
@@ -102,4 +105,32 @@ int blkmap_destroy(struct udevice *dev);
 int blkmap_create_ramdisk(const char *label, ulong image_addr, ulong image_size,
 			  struct udevice **devp);
 
+/**
+ * blkmap_get_preserved_pmem_slices() - Look for memory mapped preserved slices
+ * @cb: Callback function to call for the blkmap slice
+ * @ctx: Argument to be passed to the callback function
+ *
+ * The function is used to iterate through all the blkmap slices, looking
+ * specifically for memory mapped blkmap mapping which has been
+ * created with the preserve attribute. The function looks for such slices
+ * with the relevant attributes and then calls the callback function which
+ * then does additional configuration as needed. The callback function is
+ * invoked for all the discovered slices, unless there is an error returned
+ * by the callback, in which case the function returns that error.
+ *
+ * The callback function has the following arguments
+ * @ctx:	Argument to be passed to the callback function
+ * @addr:	Start address of the memory mapped slice
+ * @size:	Size of the memory mapped slice
+ *
+ * Typically, the callback will perform some configuration needed for the
+ * information passed on to it. An example of this would be setting up the
+ * pmem node in a device-tree(passed through the ctx argument) with the
+ * parameters passed on to the callback.
+ *
+ * Return: 0 on success, negative error on failure
+ */
+int blkmap_get_preserved_pmem_slices(int (*cb)(void *ctx, u64 addr,
+					       u64 size), void *ctx);
+
 #endif	/* _BLKMAP_H */
diff --git a/include/bloblist.h b/include/bloblist.h
index 52ba0ddcf84..f32faf78560 100644
--- a/include/bloblist.h
+++ b/include/bloblist.h
@@ -467,9 +467,8 @@ int bloblist_reloc(void *to, uint to_size);
  * If CONFIG_BLOBLIST_ALLOC is selected, it allocates memory for a bloblist of
  * size CONFIG_BLOBLIST_SIZE.
  *
- * If CONFIG_BLOBLIST_PASSAGE is selected, it uses the bloblist in the incoming
- * standard passage. The size is detected automatically so CONFIG_BLOBLIST_SIZE
- * can be 0.
+ * If CONFIG_BLOBLIST_PASSAGE_MANDATORY is selected, bloblist in the incoming
+ * standard passage is mandatorily required.
  *
  * Sets GD_FLG_BLOBLIST_READY in global_data flags on success
  *
@@ -481,7 +480,7 @@ int bloblist_init(void);
 /**
  * bloblist_maybe_init() - Init the bloblist system if not already done
  *
- * Calls bloblist_init() if the GD_FLG_BLOBLIST_READY flag is not et
+ * Calls bloblist_init() if the GD_FLG_BLOBLIST_READY flag is not set
  *
  * Return: 0 if OK, -ve on error
  */
@@ -501,19 +500,18 @@ static inline int bloblist_maybe_init(void)
  * @rfdt:  Register that holds the FDT base address.
  * @rzero: Register that must be zero.
  * @rsig:  Register that holds signature and register conventions version.
+ * @xlist: Register that holds the transfer list.
  * Return: 0 if OK, -EIO if the bloblist is not compliant to the register
  *	   conventions.
  */
-int bloblist_check_reg_conv(ulong rfdt, ulong rzero, ulong rsig);
+int bloblist_check_reg_conv(ulong rfdt, ulong rzero, ulong rsig, ulong xlist);
 
 /**
- * xferlist_from_boot_arg() - Get bloblist from the boot args and relocate it
- *			      to the specified address.
+ * xferlist_from_boot_arg() - Get bloblist from the boot args.
  *
- * @addr: Address for the bloblist
- * @size: Size of space reserved for the bloblist
+ * @addr: Address of the bloblist
  * Return: 0 if OK, else on error
  */
-int xferlist_from_boot_arg(ulong addr, ulong size);
+int xferlist_from_boot_arg(ulong *addr);
 
 #endif /* __BLOBLIST_H */
diff --git a/include/bootflow.h b/include/bootflow.h
index 480cf8a5af1..d408b8c85bd 100644
--- a/include/bootflow.h
+++ b/include/bootflow.h
@@ -160,6 +160,7 @@ struct bootflow_img {
  * before using it
  * @BOOTFLOWIF_ALL: Return bootflows with errors as well
  * @BOOTFLOWIF_HUNT: Hunt for new bootdevs using the bootdrv hunters
+ * @BOOTFLOWIF_ONLY_BOOTABLE: Only consider partitions marked 'bootable'
  *
  * Internal flags:
  * @BOOTFLOWIF_SINGLE_DEV: (internal) Just scan one bootdev
@@ -176,6 +177,7 @@ enum bootflow_iter_flags_t {
 	BOOTFLOWIF_SHOW			= 1 << 1,
 	BOOTFLOWIF_ALL			= 1 << 2,
 	BOOTFLOWIF_HUNT			= 1 << 3,
+	BOOTFLOWIF_ONLY_BOOTABLE	= BIT(4),
 
 	/*
 	 * flags used internally by standard boot - do not set these when
diff --git a/include/bootstd.h b/include/bootstd.h
index 3398e48e88b..2bc464756dd 100644
--- a/include/bootstd.h
+++ b/include/bootstd.h
@@ -22,6 +22,9 @@ struct udevice;
  * This is attached to the (only) bootstd device, so there is only one instance
  * of this struct. It provides overall information about bootdevs and bootflows.
  *
+ * TODO(sjg@chromium.org): Convert prefixes, bootdev_order and env_order to use
+ *	alist
+ *
  * @prefixes: NULL-terminated list of prefixes to use for bootflow filenames,
  *	e.g. "/", "/boot/"; NULL if none
  * @bootdev_order: Order to use for bootdevs (or NULL if none), with each item
diff --git a/include/cadence-nand.h b/include/cadence-nand.h
new file mode 100644
index 00000000000..27ed217b1ed
--- /dev/null
+++ b/include/cadence-nand.h
@@ -0,0 +1,529 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Cadence NAND flash controller driver
+ *
+ * Copyright (C) 2019 Cadence
+ *
+ * Author: Piotr Sroka <piotrs@cadence.com>
+ *
+ */
+
+#ifndef _CADENCE_NAND_H_
+#define _CADENCE_NAND_H_
+#include <clk.h>
+#include <reset.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/rawnand.h>
+
+/*
+ * HPNFC can work in 3 modes:
+ * -  PIO - can work in master or slave DMA
+ * -  CDMA - needs Master DMA for accessing command descriptors.
+ * -  Generic mode - can use only slave DMA.
+ * CDMA and PIO modes can be used to execute only base commands.
+ * CDMA and PIO modes can be used to execute only base commands.
+ * Generic mode can be used to execute any command
+ * on NAND flash memory. Driver uses CDMA mode for
+ * block erasing, page reading, page programing.
+ * Generic mode is used for executing rest of commands.
+ */
+
+#define DMA_DATA_SIZE_ALIGN 8
+
+/* Register definition. */
+/*
+ * Command register 0.
+ * Writing data to this register will initiate a new transaction
+ * of the NF controller.
+ */
+#define CMD_REG0            0x0000
+/* Command type field mask. */
+#define CMD_REG0_CT         GENMASK(31, 30)
+/* Command type CDMA. */
+#define CMD_REG0_CT_CDMA    0uL
+/* Command type generic. */
+#define CMD_REG0_CT_GEN     3uL
+/* Command thread number field mask. */
+#define CMD_REG0_TN         GENMASK(27, 24)
+
+/* Command register 2. */
+#define CMD_REG2            0x0008
+/* Command register 3. */
+#define CMD_REG3            0x000C
+/* Pointer register to select which thread status will be selected. */
+#define CMD_STATUS_PTR      0x0010
+/* Command status register for selected thread. */
+#define CMD_STATUS          0x0014
+
+/* Interrupt status register. */
+#define INTR_STATUS             0x0110
+#define INTR_STATUS_SDMA_ERR    BIT(22)
+#define INTR_STATUS_SDMA_TRIGG  BIT(21)
+#define INTR_STATUS_UNSUPP_CMD  BIT(19)
+#define INTR_STATUS_DDMA_TERR   BIT(18)
+#define INTR_STATUS_CDMA_TERR   BIT(17)
+#define INTR_STATUS_CDMA_IDL    BIT(16)
+
+/* Interrupt enable register. */
+#define INTR_ENABLE             0x0114
+#define INTR_ENABLE_INTR_EN     BIT(31)
+
+/* Controller internal state. */
+#define CTRL_STATUS             0x0118
+#define CTRL_STATUS_INIT_COMP   BIT(9)
+#define CTRL_STATUS_CTRL_BUSY   BIT(8)
+
+/* Command Engine threads state. */
+#define TRD_STATUS              0x0120
+
+/* Command Engine interrupt thread error status. */
+#define TRD_ERR_INT_STATUS      0x0128
+/* Command Engine interrupt thread error enable. */
+#define TRD_ERR_INT_STATUS_EN   0x0130
+/* Command Engine interrupt thread complete status. */
+#define TRD_COMP_INT_STATUS     0x0138
+
+/*
+ * Transfer config 0 register.
+ * Configures data transfer parameters.
+ */
+#define TRAN_CFG_0              0x0400
+/* Offset value from the beginning of the page. */
+#define TRAN_CFG_0_OFFSET       GENMASK(31, 16)
+/* Numbers of sectors to transfer within singlNF device's page. */
+#define TRAN_CFG_0_SEC_CNT      GENMASK(7, 0)
+
+/*
+ * Transfer config 1 register.
+ * Configures data transfer parameters.
+ */
+#define TRAN_CFG_1                   0x0404
+/* Size of last data sector. */
+#define TRAN_CFG_1_LAST_SEC_SIZE     GENMASK(31, 16)
+/* Size of not-last data sector. */
+#define TRAN_CFG_1_SECTOR_SIZE       GENMASK(15, 0)
+
+/* ECC engine configuration register 0. */
+#define ECC_CONFIG_0                 0x0428
+/* Correction strength. */
+#define ECC_CONFIG_0_CORR_STR        GENMASK(10, 8)
+/* Enable erased pages detection mechanism. */
+#define ECC_CONFIG_0_ERASE_DET_EN    BIT(1)
+/* Enable controller ECC check bits generation and correction. */
+#define ECC_CONFIG_0_ECC_EN          BIT(0)
+
+/* ECC engine configuration register 1. */
+#define ECC_CONFIG_1            0x042C
+
+/* Multiplane settings register. */
+#define MULTIPLANE_CFG          0x0434
+/* Cache operation settings. */
+#define CACHE_CFG               0x0438
+
+/* Transferred data block size for the slave DMA module. */
+#define SDMA_SIZE               0x0440
+
+/* Thread number associated with transferred data block
+ * for the slave DMA module.
+ */
+#define SDMA_TRD_NUM            0x0444
+/* Thread number mask. */
+#define SDMA_TRD_NUM_SDMA_TRD   GENMASK(2, 0)
+
+#define CONTROL_DATA_CTRL       0x0494
+/* Thread number mask. */
+#define CONTROL_DATA_CTRL_SIZE  GENMASK(15, 0)
+
+#define CTRL_VERSION            0x800
+#define CTRL_VERSION_REV        GENMASK(7, 0)
+
+/* Available hardware features of the controller. */
+#define CTRL_FEATURES                0x804
+/* Support for NV-DDR2/3 work mode. */
+#define CTRL_FEATURES_NVDDR_2_3      BIT(28)
+/* Support for NV-DDR work mode. */
+#define CTRL_FEATURES_NVDDR          BIT(27)
+/* Support for asynchronous work mode. */
+#define CTRL_FEATURES_ASYNC          BIT(26)
+/* Support for asynchronous work mode. */
+#define CTRL_FEATURES_N_BANKS        GENMASK(25, 24)
+/* Slave and Master DMA data width. */
+#define CTRL_FEATURES_DMA_DWITH64    BIT(21)
+/* Availability of Control Data feature.*/
+#define CTRL_FEATURES_CONTROL_DATA   BIT(10)
+
+/* BCH Engine identification register 0 - correction strengths. */
+#define BCH_CFG_0               0x838
+#define BCH_CFG_0_CORR_CAP_0    GENMASK(7, 0)
+#define BCH_CFG_0_CORR_CAP_1    GENMASK(15, 8)
+#define BCH_CFG_0_CORR_CAP_2    GENMASK(23, 16)
+#define BCH_CFG_0_CORR_CAP_3    GENMASK(31, 24)
+
+/* BCH Engine identification register 1 - correction strengths. */
+#define BCH_CFG_1               0x83C
+#define BCH_CFG_1_CORR_CAP_4    GENMASK(7, 0)
+#define BCH_CFG_1_CORR_CAP_5    GENMASK(15, 8)
+#define BCH_CFG_1_CORR_CAP_6    GENMASK(23, 16)
+#define BCH_CFG_1_CORR_CAP_7    GENMASK(31, 24)
+
+/* BCH Engine identification register 2 - sector sizes. */
+#define BCH_CFG_2               0x840
+#define BCH_CFG_2_SECT_0        GENMASK(15, 0)
+#define BCH_CFG_2_SECT_1        GENMASK(31, 16)
+
+/* BCH Engine identification register 3. */
+#define BCH_CFG_3               0x844
+#define BCH_CFG_3_METADATA_SIZE GENMASK(23, 16)
+
+/* Ready/Busy# line status. */
+#define RBN_SETINGS             0x1004
+
+/* Common settings. */
+#define COMMON_SET              0x1008
+/* 16 bit device connected to the NAND Flash interface. */
+#define COMMON_SET_DEVICE_16BIT BIT(8)
+
+/* Skip_bytes registers. */
+#define SKIP_BYTES_CONF             0x100C
+#define SKIP_BYTES_MARKER_VALUE     GENMASK(31, 16)
+#define SKIP_BYTES_NUM_OF_BYTES     GENMASK(7, 0)
+
+#define SKIP_BYTES_OFFSET           0x1010
+#define SKIP_BYTES_OFFSET_VALUE     GENMASK(23, 0)
+
+/* Timings configuration. */
+#define ASYNC_TOGGLE_TIMINGS        0x101c
+#define ASYNC_TOGGLE_TIMINGS_TRH    GENMASK(28, 24)
+#define ASYNC_TOGGLE_TIMINGS_TRP    GENMASK(20, 16)
+#define ASYNC_TOGGLE_TIMINGS_TWH    GENMASK(12, 8)
+#define ASYNC_TOGGLE_TIMINGS_TWP    GENMASK(4, 0)
+
+#define TIMINGS0                    0x1024
+#define TIMINGS0_TADL               GENMASK(31, 24)
+#define TIMINGS0_TCCS               GENMASK(23, 16)
+#define TIMINGS0_TWHR               GENMASK(15, 8)
+#define TIMINGS0_TRHW               GENMASK(7, 0)
+
+#define TIMINGS1                    0x1028
+#define TIMINGS1_TRHZ               GENMASK(31, 24)
+#define TIMINGS1_TWB                GENMASK(23, 16)
+#define TIMINGS1_TVDLY              GENMASK(7, 0)
+
+#define TIMINGS2                    0x102c
+#define TIMINGS2_TFEAT              GENMASK(25, 16)
+#define TIMINGS2_CS_HOLD_TIME       GENMASK(13, 8)
+#define TIMINGS2_CS_SETUP_TIME      GENMASK(5, 0)
+
+/* Configuration of the resynchronization of slave DLL of PHY. */
+#define DLL_PHY_CTRL                    0x1034
+#define DLL_PHY_CTRL_DLL_RST_N          BIT(24)
+#define DLL_PHY_CTRL_EXTENDED_WR_MODE   BIT(17)
+#define DLL_PHY_CTRL_EXTENDED_RD_MODE   BIT(16)
+#define DLL_PHY_CTRL_RS_HIGH_WAIT_CNT   GENMASK(11, 8)
+#define DLL_PHY_CTRL_RS_IDLE_CNT        GENMASK(7, 0)
+
+/* TODO: - Identify better way to handle PHY address */
+#define PHY_OFFSET                      0x10000
+
+/* Register controlling DQ related timing. */
+#define PHY_DQ_TIMING                   PHY_OFFSET + 0x2000
+/* Register controlling DSQ related timing.  */
+#define PHY_DQS_TIMING                  PHY_OFFSET + 0x2004
+#define PHY_DQS_TIMING_DQS_SEL_OE_END   GENMASK(3, 0)
+#define PHY_DQS_TIMING_PHONY_DQS_SEL    BIT(16)
+#define PHY_DQS_TIMING_USE_PHONY_DQS    BIT(20)
+
+/* Register controlling the gate and loopback control related timing. */
+#define PHY_GATE_LPBK_CTRL              PHY_OFFSET + 0x2008
+#define PHY_GATE_LPBK_CTRL_RDS          GENMASK(24, 19)
+
+/* Register holds the control for the master DLL logic. */
+#define PHY_DLL_MASTER_CTRL             PHY_OFFSET + 0x200C
+#define PHY_DLL_MASTER_CTRL_BYPASS_MODE BIT(23)
+
+/* Register holds the control for the slave DLL logic. */
+#define PHY_DLL_SLAVE_CTRL              PHY_OFFSET + 0x2010
+
+/* This register handles the global control settings for the PHY. */
+#define PHY_CTRL                        PHY_OFFSET + 0x2080
+#define PHY_CTRL_SDR_DQS                BIT(14)
+#define PHY_CTRL_PHONY_DQS              GENMASK(9, 4)
+
+/*
+ * This register handles the global control settings
+ * for the termination selects for reads.
+ */
+#define PHY_TSEL                PHY_OFFSET + 0x2084
+
+/* Generic command layout. */
+#define GCMD_LAY_CS             GENMASK_ULL(11, 8)
+/*
+ * This bit informs the minicotroller if it has to wait for tWB
+ * after sending the last CMD/ADDR/DATA in the sequence.
+ */
+#define GCMD_LAY_TWB            BIT_ULL(6)
+/* Type of generic instruction. */
+#define GCMD_LAY_INSTR          GENMASK_ULL(5, 0)
+
+/* Generic CMD sequence type. */
+#define GCMD_LAY_INSTR_CMD      0
+/* Generic ADDR sequence type. */
+#define GCMD_LAY_INSTR_ADDR     1
+/* Generic data transfer sequence type. */
+#define GCMD_LAY_INSTR_DATA     2
+
+/* Input part of generic command type of input is command. */
+#define GCMD_LAY_INPUT_CMD          GENMASK_ULL(23, 16)
+
+/* Generic command address sequence - address fields. */
+#define GCMD_LAY_INPUT_ADDR         GENMASK_ULL(63, 16)
+/* Generic command address sequence - address size. */
+#define GCMD_LAY_INPUT_ADDR_SIZE    GENMASK_ULL(13, 11)
+
+/* Transfer direction field of generic command data sequence. */
+#define GCMD_DIR            BIT_ULL(11)
+/* Read transfer direction of generic command data sequence. */
+#define GCMD_DIR_READ       0
+/* Write transfer direction of generic command data sequence. */
+#define GCMD_DIR_WRITE      1
+
+/* ECC enabled flag of generic command data sequence - ECC enabled. */
+#define GCMD_ECC_EN             BIT_ULL(12)
+/* Generic command data sequence - sector size. */
+#define GCMD_SECT_SIZE          GENMASK_ULL(31, 16)
+/* Generic command data sequence - sector count. */
+#define GCMD_SECT_CNT           GENMASK_ULL(39, 32)
+/* Generic command data sequence - last sector size. */
+#define GCMD_LAST_SIZE          GENMASK_ULL(55, 40)
+
+/* CDMA descriptor fields. */
+/* Erase command type of CDMA descriptor. */
+#define CDMA_CT_ERASE           0x1000
+/* Program page command type of CDMA descriptor. */
+#define CDMA_CT_WR              0x2100
+/* Read page command type of CDMA descriptor. */
+#define CDMA_CT_RD              0x2200
+
+/* Flash pointer memory shift. */
+#define CDMA_CFPTR_MEM_SHIFT    24
+/* Flash pointer memory mask. */
+#define CDMA_CFPTR_MEM          GENMASK(26, 24)
+
+/*
+ * Command DMA descriptor flags. If set causes issue interrupt after
+ * the completion of descriptor processing.
+ */
+#define CDMA_CF_INT         BIT(8)
+/*
+ * Command DMA descriptor flags - the next descriptor
+ * address field is valid and descriptor processing should continue.
+ */
+#define CDMA_CF_CONT        BIT(9)
+/* DMA master flag of command DMA descriptor. */
+#define CDMA_CF_DMA_MASTER  BIT(10)
+
+/* Operation complete status of command descriptor. */
+#define CDMA_CS_COMP        BIT(15)
+/* Operation complete status of command descriptor. */
+/* Command descriptor status - operation fail. */
+#define CDMA_CS_FAIL        BIT(14)
+/* Command descriptor status - page erased. */
+#define CDMA_CS_ERP         BIT(11)
+/* Command descriptor status - timeout occurred. */
+#define CDMA_CS_TOUT        BIT(10)
+/*
+ * Maximum amount of correction applied to one ECC sector.
+ * It is part of command descriptor status.
+ */
+#define CDMA_CS_MAXERR      GENMASK(9, 2)
+/* Command descriptor status - uncorrectable ECC error. */
+#define CDMA_CS_UNCE        BIT(1)
+/* Command descriptor status - descriptor error. */
+#define CDMA_CS_ERR         BIT(0)
+
+/* Status of operation - OK. */
+#define STAT_OK             0
+/* Status of operation - FAIL. */
+#define STAT_FAIL           2
+/* Status of operation - uncorrectable ECC error. */
+#define STAT_ECC_UNCORR     3
+/* Status of operation - page erased. */
+#define STAT_ERASED         5
+/* Status of operation - correctable ECC error. */
+#define STAT_ECC_CORR       6
+/* Status of operation - unsuspected state. */
+#define STAT_UNKNOWN        7
+/* Status of operation - operation is not completed yet. */
+#define STAT_BUSY           0xFF
+
+#define BCH_MAX_NUM_CORR_CAPS       8
+#define BCH_MAX_NUM_SECTOR_SIZES    2
+
+#define ONE_CYCLE                   1
+#define TIMEOUT_US                  1000000
+
+struct cadence_nand_timings {
+	u32 async_toggle_timings;
+	u32 timings0;
+	u32 timings1;
+	u32 timings2;
+	u32 dll_phy_ctrl;
+	u32 phy_ctrl;
+	u32 phy_dqs_timing;
+	u32 phy_gate_lpbk_ctrl;
+};
+
+/* Command DMA descriptor. */
+struct cadence_nand_cdma_desc {
+	/* Next descriptor address. */
+	u64 next_pointer;
+
+	/* Flash address is a 32-bit address comprising of BANK and ROW ADDR. */
+	u32 flash_pointer;
+	/*field appears in HPNFC version 13*/
+	u16 bank;
+	u16 rsvd0;
+
+	/* Operation the controller needs to perform. */
+	u16 command_type;
+	u16 rsvd1;
+	/* Flags for operation of this command. */
+	u16 command_flags;
+	u16 rsvd2;
+
+	/* System/host memory address required for data DMA commands. */
+	u64 memory_pointer;
+
+	/* Status of operation. */
+	u32 status;
+	u32 rsvd3;
+
+	/* Address pointer to sync buffer location. */
+	u64 sync_flag_pointer;
+
+	/* Controls the buffer sync mechanism. */
+	u32 sync_arguments;
+	u32 rsvd4;
+
+	/* Control data pointer. */
+	u64 ctrl_data_ptr;
+};
+
+/* Interrupt status. */
+struct cadence_nand_irq_status {
+	/* Thread operation complete status. */
+	u32 trd_status;
+	/* Thread operation error. */
+	u32 trd_error;
+	/* Controller status. */
+	u32 status;
+};
+
+/* Cadence NAND flash controller capabilities get from driver data. */
+struct cadence_nand_dt_devdata {
+	/* Skew value of the output signals of the NAND Flash interface. */
+	u32 if_skew;
+	/* It informs if slave DMA interface is connected to DMA engine. */
+	unsigned int has_dma:1;
+};
+
+/* Cadence NAND flash controller capabilities read from registers. */
+struct cdns_nand_caps {
+	/* Maximum number of banks supported by hardware. */
+	u8 max_banks;
+	/* Slave and Master DMA data width in bytes (4 or 8). */
+	u8 data_dma_width;
+	/* Control Data feature supported. */
+	bool data_control_supp;
+	/* Is PHY type DLL. */
+	bool is_phy_type_dll;
+};
+
+struct cadence_nand_info {
+	struct nand_hw_control controller;
+	struct udevice *dev;
+	struct reset_ctl softphy_reset;
+	struct reset_ctl nand_reset;
+	struct cadence_nand_cdma_desc *cdma_desc;
+	/* IP capability. */
+	const struct cadence_nand_dt_devdata *caps1;
+	struct cdns_nand_caps caps2;
+	u8 ctrl_rev;
+	dma_addr_t dma_cdma_desc;
+	/* command interface buffers */
+	u8 *buf;
+	u32 buf_size;
+	u8 *stat;
+	u8 cmd;
+	u32 buf_index;
+
+	u8 curr_corr_str_idx;
+
+	/* Register interface. */
+	void __iomem *reg;
+
+	struct {
+	void __iomem *virt;
+	dma_addr_t dma;
+	} io;
+
+	int irq;
+	/* Interrupts that have happened. */
+	struct cadence_nand_irq_status irq_status;
+	/* Interrupts we are waiting for. */
+	struct cadence_nand_irq_status irq_mask;
+
+	int ecc_strengths[BCH_MAX_NUM_CORR_CAPS];
+	struct nand_ecc_step_info ecc_stepinfos[BCH_MAX_NUM_SECTOR_SIZES];
+	struct nand_ecc_caps ecc_caps;
+
+	int curr_trans_type;
+
+	struct clk clk;
+	u32 nf_clk_rate;
+	/*
+	 * Estimated Board delay. The value includes the total
+	 * round trip delay for the signals and is used for deciding on values
+	 * associated with data read capture.
+	 */
+	u32 board_delay;
+
+	struct nand_chip *selected_chip;
+
+	unsigned long assigned_cs;
+	struct list_head chips;
+	u8 bch_metadata_size;
+};
+
+struct cdns_nand_chip {
+	struct cadence_nand_timings timings;
+	struct nand_chip chip;
+	u8 nsels;
+	struct list_head node;
+
+	/*
+	 * part of oob area of NAND flash memory page.
+	 * This part is available for user to read or write.
+	 */
+	u32 avail_oob_size;
+
+	/* Sector size. There are few sectors per mtd->writesize */
+	u32 sector_size;
+	u32 sector_count;
+
+	/* Offset of BBM. */
+	u8 bbm_offs;
+	/* Number of bytes reserved for BBM. */
+	u8 bbm_len;
+	/* ECC strength index. */
+	u8 corr_str_idx;
+
+	u8 cs[];
+};
+
+struct ecc_info {
+	int (*calc_ecc_bytes)(int step_size, int strength);
+	int max_step_size;
+};
+
+#endif /*_CADENCE_NAND_H_*/
diff --git a/include/clk.h b/include/clk.h
index 045e923a529..a6ef4e02692 100644
--- a/include/clk.h
+++ b/include/clk.h
@@ -351,6 +351,15 @@ static inline int clk_get_by_name_nodev_optional(ofnode node, const char *name,
 }
 
 /**
+ * clk_resolve_parent_clk - Determine name of clock udevice based on clock-names
+ * @dev:	The client udevice.
+ * @name:	The name of the clock to look up.
+ *
+ * Return name of the clock udevice which represents clock with clock-names name.
+ */
+const char *clk_resolve_parent_clk(struct udevice *dev, const char *name);
+
+/**
  * enum clk_defaults_stage - What stage clk_set_defaults() is called at
  * @CLK_DEFAULTS_PRE: Called before probe. Setting of defaults for clocks owned
  *                    by this clock driver will be defered until after probing.
diff --git a/include/config_distro_bootcmd.h b/include/config_distro_bootcmd.h
index 0a4e4b8ff85..8ac3a4feeb8 100644
--- a/include/config_distro_bootcmd.h
+++ b/include/config_distro_bootcmd.h
@@ -112,7 +112,7 @@
 #define BOOTEFI_NAME "bootarm.efi"
 #elif defined(CONFIG_X86_RUN_32BIT)
 #define BOOTEFI_NAME "bootia32.efi"
-#elif defined(CONFIG_X86_RUN_64BIT)
+#elif defined(CONFIG_X86_64)
 #define BOOTEFI_NAME "bootx64.efi"
 #elif defined(CONFIG_ARCH_RV32I)
 #define BOOTEFI_NAME "bootriscv32.efi"
diff --git a/include/configs/am335x_guardian.h b/include/configs/am335x_guardian.h
index 96efd38594a..385dec2ff4f 100644
--- a/include/configs/am335x_guardian.h
+++ b/include/configs/am335x_guardian.h
@@ -63,11 +63,6 @@
 		  "fi; " \
 		  "setenv extrabootargs $extrabootargs \"swi_attached\"; " \
 		"fi;" \
-		"run bootcmd_ubifs0;\0" \
-	"altbootcmd=" \
-		"setenv boot_syslinux_conf \"extlinux/extlinux-rollback.conf\"; " \
-		"run distro_bootcmd; " \
-		"setenv boot_syslinux_conf \"extlinux/extlinux.conf\"; " \
 		"run bootcmd_ubifs0;\0"
 
 #endif /* ! CONFIG_XPL_BUILD */
diff --git a/include/configs/am57xx_evm.h b/include/configs/am57xx_evm.h
index aa31f3b05a0..266b77fbf68 100644
--- a/include/configs/am57xx_evm.h
+++ b/include/configs/am57xx_evm.h
@@ -37,20 +37,4 @@
 
 /* CPSW Ethernet */
 
-/*
- * Default to using SPI for environment, etc.
- * 0x000000 - 0x040000 : QSPI.SPL (256KiB)
- * 0x040000 - 0x140000 : QSPI.u-boot (1MiB)
- * 0x140000 - 0x1C0000 : QSPI.u-boot-spl-os (512KiB)
- * 0x1C0000 - 0x1D0000 : QSPI.u-boot-env (64KiB)
- * 0x1D0000 - 0x1E0000 : QSPI.u-boot-env.backup1 (64KiB)
- * 0x1E0000 - 0x9E0000 : QSPI.kernel (8MiB)
- * 0x9E0000 - 0x2000000 : USERLAND
- */
-#define CFG_SYS_SPI_KERNEL_OFFS      0x1E0000
-#define CFG_SYS_SPI_ARGS_OFFS        0x140000
-#define CFG_SYS_SPI_ARGS_SIZE        0x80000
-
-/* SPI SPL */
-
 #endif /* __CONFIG_AM57XX_EVM_H */
diff --git a/include/configs/an7581.h b/include/configs/an7581.h
new file mode 100644
index 00000000000..64f04c9d9a5
--- /dev/null
+++ b/include/configs/an7581.h
@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Configuration for Airoha AN7581
+ */
+
+#ifndef __AN7581_H
+#define __AN7581_H
+
+#include <linux/sizes.h>
+
+#define CFG_SYS_UBOOT_BASE		CONFIG_TEXT_BASE
+
+#define CFG_SYS_INIT_RAM_ADDR           CONFIG_TEXT_BASE
+#define CFG_SYS_INIT_RAM_SIZE           SZ_2M
+
+/* DRAM */
+#define CFG_SYS_SDRAM_BASE		0x80000000
+
+#endif
diff --git a/include/configs/beagley_ai.h b/include/configs/beagley_ai.h
new file mode 100644
index 00000000000..a7072a094c5
--- /dev/null
+++ b/include/configs/beagley_ai.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Configuration header file for BeagleY-AI
+ *
+ * Copyright (C) 2025 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#ifndef __CONFIG_BEAGLEY_AI_H
+#define __CONFIG_BEAGLEY_AI_H
+
+/* Now for the remaining common defines */
+#include <configs/ti_armv7_common.h>
+
+#endif /* __CONFIG_BEAGLEY_AI_H */
diff --git a/include/configs/bk4r1.h b/include/configs/bk4r1.h
index 5df8d03c706..6d24c5decd5 100644
--- a/include/configs/bk4r1.h
+++ b/include/configs/bk4r1.h
@@ -16,8 +16,6 @@
 #define BK4_EXTRA_ENV_SETTINGS \
 	"bootlimit=3\0" \
 	"eraseuserdata=false\0" \
-	"altbootcmd=led 5 on; " \
-		"boot\0" \
 	"set_gpio103=mw 0x400ff0c4 0x0080; mw 0x4004819C 0x000011bf\0" \
 	"set_gpio102=mw 0x400ff0c4 0x40; mw 0x40048198 0x000011bf\0" \
 	"set_gpio96=mw 0x40048180 0x282; mw 0x400ff0c4 0x1\0"\
diff --git a/include/configs/brppt2.h b/include/configs/brppt2.h
index d01f0d37316..93559a171ae 100644
--- a/include/configs/brppt2.h
+++ b/include/configs/brppt2.h
@@ -64,7 +64,6 @@ BUR_COMMON_ENV \
 " do echo \"### booting ${target} ###\"; run b_${target};" \
 " if test ${b_break} = 1; then; exit; fi; done\0" \
 "loaddev=mmc 0\0" \
-"altbootcmd=setenv b_mode 0; run b_default;\0" \
 "bootlimit=1\0" \
 "net2nor=sf probe && dhcp &&" \
 " tftp ${loadaddr} SPL && sf erase 0 +${filesize} &&" \
diff --git a/include/configs/display5.h b/include/configs/display5.h
index 51fa2b03a2e..19d71d6066f 100644
--- a/include/configs/display5.h
+++ b/include/configs/display5.h
@@ -29,11 +29,6 @@
  * 0x1F00000 - 0x2000000 : SPI.factory  (1MiB)
  */
 
-/* Below values are "dummy" - only to avoid build break */
-#define CFG_SYS_SPI_KERNEL_OFFS      0x150000
-#define CFG_SYS_SPI_ARGS_OFFS        0x140000
-#define CFG_SYS_SPI_ARGS_SIZE        0x10000
-
 #define CFG_MXC_UART_BASE		UART5_BASE
 
 /* MMC Configs */
@@ -170,7 +165,6 @@
 	"display=tianma-tm070-800x480\0" \
 	"board=display5\0" \
 	"mmcdev=0\0" \
-	"altbootcmd=run recovery\0" \
 	"bootdelay=1\0" \
 	"baudrate=115200\0" \
 	"ethact=FEC\0" \
diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h
index 96dcd731cb6..3c960ca2ce2 100644
--- a/include/configs/dra7xx_evm.h
+++ b/include/configs/dra7xx_evm.h
@@ -47,22 +47,6 @@
 
 #include <configs/ti_omap5_common.h>
 
-/*
- * Default to using SPI for environment, etc.
- * 0x000000 - 0x040000 : QSPI.SPL (256KiB)
- * 0x040000 - 0x140000 : QSPI.u-boot (1MiB)
- * 0x140000 - 0x1C0000 : QSPI.u-boot-spl-os (512KiB)
- * 0x1C0000 - 0x1D0000 : QSPI.u-boot-env (64KiB)
- * 0x1D0000 - 0x1E0000 : QSPI.u-boot-env.backup1 (64KiB)
- * 0x1E0000 - 0x9E0000 : QSPI.kernel (8MiB)
- * 0x9E0000 - 0x2000000 : USERLAND
- */
-#define CFG_SYS_SPI_KERNEL_OFFS	0x1E0000
-#define CFG_SYS_SPI_ARGS_OFFS	0x140000
-#define CFG_SYS_SPI_ARGS_SIZE	0x80000
-
-/* SPI SPL */
-
 /* NAND support */
 #ifdef CONFIG_MTD_RAW_NAND
 /* NAND: device related configs */
diff --git a/include/configs/ge_b1x5v2.h b/include/configs/ge_b1x5v2.h
index f3d85c9c11e..5e3f67124c0 100644
--- a/include/configs/ge_b1x5v2.h
+++ b/include/configs/ge_b1x5v2.h
@@ -82,14 +82,6 @@
 	"doboot=" \
 		"echo Booting from mmc:${mmcdev}:${mmcpart} ...; " \
 		"run helix;\0" \
-	"altbootcmd=" \
-		"setenv mmcpart 1; run hasfirstboot || setenv mmcpart 2; " \
-		"run hasfirstboot || setenv mmcpart 0; " \
-		"if test ${mmcpart} != 0; then " \
-			"setenv bootcause REVERT; " \
-			"run swappartitions loadimage doboot; " \
-		"fi; " \
-		"run failbootcmd\0" \
 	"tryboot=" \
 		"setenv mmcpart 1; run hasfirstboot || setenv mmcpart 2; " \
 		"run loadimage || run swappartitions && run loadimage || " \
diff --git a/include/configs/ge_bx50v3.h b/include/configs/ge_bx50v3.h
index 07b36706e56..c8ef048bd43 100644
--- a/include/configs/ge_bx50v3.h
+++ b/include/configs/ge_bx50v3.h
@@ -67,14 +67,6 @@
 		"Try again, or contact GE Service for support.\"; " \
 		"bootcount reset; " \
 		"while true; do sleep 1; done; \0" \
-	"altbootcmd=" \
-		"run doquiet; " \
-		"setenv partnum 1; run hasfirstboot || setenv partnum 2; " \
-		"run hasfirstboot || setenv partnum 0; " \
-		"if test ${partnum} != 0; then " \
-			"run swappartitions loadimage doboot; " \
-		"fi; " \
-		"run failbootcmd\0" \
 	"loadimage=" \
 		"ext2load ${dev} ${devnum}:${partnum} ${loadaddr} ${image}\0" \
 	"doboot=" \
diff --git a/include/configs/imx6-engicam.h b/include/configs/imx6-engicam.h
index 786b70fe064..3d5701c636c 100644
--- a/include/configs/imx6-engicam.h
+++ b/include/configs/imx6-engicam.h
@@ -47,7 +47,6 @@
 	"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
 	"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
 	"loadfit=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${fit_image}\0" \
-	"altbootcmd=run recoveryboot\0"\
 	"fitboot=echo Booting FIT image from mmc ...; " \
 		"run mmcargs; " \
 		"bootm ${loadaddr}\0" \
diff --git a/include/configs/imx6q-bosch-acc.h b/include/configs/imx6q-bosch-acc.h
index 64ddbf711d3..84da8250684 100644
--- a/include/configs/imx6q-bosch-acc.h
+++ b/include/configs/imx6q-bosch-acc.h
@@ -42,8 +42,7 @@
 	"env_persisted=0\0" \
 	"env_persist=if test ${env_persisted} != 1; " \
 		"then env set env_persisted 1; run save_env; fi;\0" \
-	"save_env=env save; env save\0" \
-	"altbootcmd=run handle_ustate; run switch_bootset; run save_env; run bootcmd\0"
+	"save_env=env save; env save\0"
 
 #define CFG_ENV_FLAGS_LIST_STATIC \
 	"bootset:bw," \
diff --git a/include/configs/imx8mm-mx8menlo.h b/include/configs/imx8mm-mx8menlo.h
index 7058d632d67..626ccae7205 100644
--- a/include/configs/imx8mm-mx8menlo.h
+++ b/include/configs/imx8mm-mx8menlo.h
@@ -18,14 +18,6 @@
 	"devtype=mmc\0"							\
 	"devnum=1\0"							\
 	"distro_bootpart=1\0"						\
-	"altbootcmd="							\
-		"mmc partconf 0 mmcpart ; "				\
-		"if test ${mmcpart} -eq 1 ; then "			\
-			"mmc partconf 0 1 2 0 ; "			\
-		"else "							\
-			"mmc partconf 0 1 1 0 ; "			\
-		"fi ; "							\
-		"boot\0"						\
 	"boot_file=fitImage\0"						\
 	"console=ttymxc0\0"						\
 	"fdt_addr=0x43000000\0"						\
diff --git a/include/configs/imx8mm_data_modul_edm_sbc.h b/include/configs/imx8mm_data_modul_edm_sbc.h
index 57ecb5e2190..5ce4219912f 100644
--- a/include/configs/imx8mm_data_modul_edm_sbc.h
+++ b/include/configs/imx8mm_data_modul_edm_sbc.h
@@ -34,7 +34,6 @@
 #define CFG_SYS_FSL_ESDHC_ADDR	0
 
 #define CFG_EXTRA_ENV_SETTINGS						\
-	"altbootcmd=run bootcmd\0"					\
 	"bootlimit=3\0"							\
 	"devtype=mmc\0"							\
 	"devpart=1\0"							\
diff --git a/include/configs/imx8mp_data_modul_edm_sbc.h b/include/configs/imx8mp_data_modul_edm_sbc.h
index de5bdd30e18..58a03b35ac4 100644
--- a/include/configs/imx8mp_data_modul_edm_sbc.h
+++ b/include/configs/imx8mp_data_modul_edm_sbc.h
@@ -24,7 +24,6 @@
 #define FEC_QUIRK_ENET_MAC
 
 #define CFG_EXTRA_ENV_SETTINGS						\
-	"altbootcmd=run bootcmd\0"					\
 	"bootlimit=3\0"							\
 	"devtype=mmc\0"							\
 	"devpart=1\0"							\
diff --git a/include/configs/imx8mp_dhcom_pdk2.h b/include/configs/imx8mp_dhcom_pdk2.h
index c848fce8bda..f3e239d780f 100644
--- a/include/configs/imx8mp_dhcom_pdk2.h
+++ b/include/configs/imx8mp_dhcom_pdk2.h
@@ -28,7 +28,6 @@
 #define CFG_SYS_FSL_ESDHC_ADDR	0
 
 #define CFG_EXTRA_ENV_SETTINGS						\
-	"altbootcmd=run bootcmd ; reset\0"				\
 	"bootlimit=3\0"							\
 	"dfu_alt_info="							\
 		/* RAM block at DRAM offset 256..768 MiB */		\
diff --git a/include/configs/imxrt1020-evk.h b/include/configs/imxrt1020-evk.h
index cd6af93454b..aec12082b95 100644
--- a/include/configs/imxrt1020-evk.h
+++ b/include/configs/imxrt1020-evk.h
@@ -9,8 +9,6 @@
 
 #include <asm/arch/imx-regs.h>
 
-#define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE	1
-
 #define PHYS_SDRAM			0x80000000
 #define PHYS_SDRAM_SIZE			(32 * 1024 * 1024)
 
diff --git a/include/configs/imxrt1050-evk.h b/include/configs/imxrt1050-evk.h
index c520c2fc203..5b8d6a7ac05 100644
--- a/include/configs/imxrt1050-evk.h
+++ b/include/configs/imxrt1050-evk.h
@@ -9,8 +9,6 @@
 
 #include <asm/arch/imx-regs.h>
 
-#define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE	1
-
 #define PHYS_SDRAM			0x80000000
 #define PHYS_SDRAM_SIZE			(32 * 1024 * 1024)
 
diff --git a/include/configs/imxrt1170-evk.h b/include/configs/imxrt1170-evk.h
index 1ccaa15bc11..f821212765c 100644
--- a/include/configs/imxrt1170-evk.h
+++ b/include/configs/imxrt1170-evk.h
@@ -10,8 +10,6 @@
 
 #include <asm/arch/imx-regs.h>
 
-#define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE	1
-
 /*
  * Configuration of the external SDRAM memory
  */
diff --git a/include/configs/m53menlo.h b/include/configs/m53menlo.h
index 1ea4fa59fd5..a6aafb51854 100644
--- a/include/configs/m53menlo.h
+++ b/include/configs/m53menlo.h
@@ -93,13 +93,6 @@
 	"splashfile=boot/usplash.bmp.gz\0"				\
 	"splashimage=0x88000000\0"					\
 	"splashpos=m,m\0"						\
-	"altbootcmd="							\
-		"if test ${mmcpart} -eq 1 ; then "			\
-			"setenv mmcpart 2 ; "				\
-		"else "							\
-			"setenv mmcpart 1 ; "				\
-		"fi ; "							\
-		"boot\0"						\
 	"stdout=serial,vidconsole\0"					\
 	"stderr=serial,vidconsole\0"					\
 	"addcons="							\
diff --git a/include/configs/mocha.h b/include/configs/mocha.h
new file mode 100644
index 00000000000..1c2eb906085
--- /dev/null
+++ b/include/configs/mocha.h
@@ -0,0 +1,25 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2010-2013, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Copyright (c) 2024, Svyatoslav Ryhel <clamor95@gmail.com>
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include "tegra124-common.h"
+
+/* High-level configuration options */
+#define CFG_TEGRA_BOARD_STRING		"Xiaomi Mocha"
+
+/* Board-specific serial config */
+#define CFG_SYS_NS16550_COM1		NV_PA_APB_UARTD_BASE
+
+#ifdef CONFIG_TEGRA_SUPPORT_NON_SECURE
+  #define CFG_PRAM                     0x38400 /* 225 MB */
+#endif
+
+#include "tegra-common-post.h"
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/mx53ppd.h b/include/configs/mx53ppd.h
index 6d1f669de50..3707de254e1 100644
--- a/include/configs/mx53ppd.h
+++ b/include/configs/mx53ppd.h
@@ -59,14 +59,6 @@
 		"Try again, or contact GE Service for support.\"; " \
 		"bootcount reset; " \
 		"while true; do sleep 1; done; \0" \
-	"altbootcmd=" \
-		"run doquiet; " \
-		"setenv partnum 1; run hasfirstboot || setenv partnum 2; " \
-		"run hasfirstboot || setenv partnum 0; " \
-		"if test ${partnum} != 0; then " \
-			"run swappartitions loadimage doboot; " \
-		"fi; " \
-		"run failbootcmd\0" \
 	"loadimage=" \
 		"ext2load ${dev} ${devnum}:${partnum} ${loadaddr} ${image}\0" \
 	"doboot=" \
diff --git a/include/configs/ouya.h b/include/configs/ouya.h
new file mode 100644
index 00000000000..cc86c1002e3
--- /dev/null
+++ b/include/configs/ouya.h
@@ -0,0 +1,23 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ *  (C) Copyright 2010,2012
+ *  NVIDIA Corporation <www.nvidia.com>
+ *
+ *  (C) Copyright 2025
+ *  Svyatoslav Ryhel <clamor95@gmail.com>
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include "tegra30-common.h"
+
+/* High-level configuration options */
+#define CFG_TEGRA_BOARD_STRING		"Ouya Game Console"
+
+/* Board-specific serial config */
+#define CFG_SYS_NS16550_COM1		NV_PA_APB_UARTD_BASE
+
+#include "tegra-common-post.h"
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/phycore_am62ax.h b/include/configs/phycore_am62ax.h
index 661ba8f73ca..4f612d2c2ce 100644
--- a/include/configs/phycore_am62ax.h
+++ b/include/configs/phycore_am62ax.h
@@ -12,4 +12,8 @@
 /* DDR Configuration */
 #define CFG_SYS_SDRAM_BASE		0x80000000
 
+#define PHYCORE_AM6XX_FW_NAME_TIBOOT3	u"PHYCORE_AM62AX_TIBOOT3"
+#define PHYCORE_AM6XX_FW_NAME_SPL	u"PHYCORE_AM62AX_SPL"
+#define PHYCORE_AM6XX_FW_NAME_UBOOT	u"PHYCORE_AM62AX_UBOOT"
+
 #endif /* __PHYCORE_AM62AX_H */
diff --git a/include/configs/sandbox.h b/include/configs/sandbox.h
index 2372485c84e..db2ac7f83bb 100644
--- a/include/configs/sandbox.h
+++ b/include/configs/sandbox.h
@@ -6,7 +6,7 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
-#define CFG_MALLOC_F_ADDR		0x0010000
+#define CFG_MALLOC_F_ADDR		0x000f4000
 
 /* Size of our emulated memory */
 #define SB_CONCAT(x, y) x ## y
diff --git a/include/configs/siemens-am33x-common.h b/include/configs/siemens-am33x-common.h
index 74b7fe85800..a918dc1350c 100644
--- a/include/configs/siemens-am33x-common.h
+++ b/include/configs/siemens-am33x-common.h
@@ -128,7 +128,6 @@
 	"verify=no \0" \
 	"project_dir=targetdir\0" \
 	"upgrade_available=0\0" \
-	"altbootcmd=run bootcmd\0" \
 	"partitionset_active=A\0" \
 	"loadaddr=0x82000000\0" \
 	"kloadaddr=0x81000000\0" \
diff --git a/include/configs/siemens-env-common.h b/include/configs/siemens-env-common.h
index 36fa5d936f7..c028823e1eb 100644
--- a/include/configs/siemens-env-common.h
+++ b/include/configs/siemens-env-common.h
@@ -183,7 +183,6 @@
 	"rootfs_name=/dev/mmcblk0\0" \
 	"upgrade_available=0\0" \
 	"bootlimit=3\0" \
-	"altbootcmd=run bootcmd\0" \
 	"optargs=\0" \
 
 /**********************************************************************/
diff --git a/include/configs/sifive-unleashed.h b/include/configs/sifive-unleashed.h
index 2996b375723..cd8d0438ba6 100644
--- a/include/configs/sifive-unleashed.h
+++ b/include/configs/sifive-unleashed.h
@@ -11,7 +11,6 @@
 
 #include <linux/sizes.h>
 
-#define CFG_SYS_SDRAM_BASE		0x80000000
 
 #define RISCV_MMODE_TIMERBASE		0x2000000
 #define RISCV_MMODE_TIMEROFF		0xbff8
diff --git a/include/configs/sifive-unmatched.h b/include/configs/sifive-unmatched.h
index 27e0912665b..e0064edc5c9 100644
--- a/include/configs/sifive-unmatched.h
+++ b/include/configs/sifive-unmatched.h
@@ -11,6 +11,5 @@
 
 #include <linux/sizes.h>
 
-#define CFG_SYS_SDRAM_BASE		0x80000000
 
 #endif /* __SIFIVE_UNMATCHED_H */
diff --git a/include/configs/snapper9g45.h b/include/configs/snapper9g45.h
index df8ed451a43..8ea708d0e92 100644
--- a/include/configs/snapper9g45.h
+++ b/include/configs/snapper9g45.h
@@ -58,8 +58,7 @@
 	"boot_tftp=setenv bootargs $bootargs_def ip=any nfsroot=$nfsroot; setenv autoload y && bootp && bootm\0" \
 	"boot_usb=setenv bootargs $bootargs_def; usb start && usb storage && fatload usb 0:1 $loadaddr dds-xm200.bin && bootm\0" \
 	"boot_mmc=setenv bootargs $bootargs_def; mmc rescan && fatload mmc 0:1 $loadaddr dds-xm200.bin && bootm\0" \
-	"bootcmd=run boot_mmc ; run boot_usb ; run boot_working ; run boot_safe\0" \
-	"altbootcmd=run boot_mmc ; run boot_usb ; run boot_safe ; run boot_working\0"
+	"bootcmd=run boot_mmc ; run boot_usb ; run boot_working ; run boot_safe\0"
 
 /* Console settings */
 
diff --git a/include/configs/socfpga_soc64_common.h b/include/configs/socfpga_soc64_common.h
index b7ee1dbf201..5ed17671f79 100644
--- a/include/configs/socfpga_soc64_common.h
+++ b/include/configs/socfpga_soc64_common.h
@@ -1,6 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0
  *
  * Copyright (C) 2017-2024 Intel Corporation <www.intel.com>
+ * Copyright (C) 2025 Altera Corporation <www.altera.com>
  *
  */
 
@@ -56,6 +57,11 @@
 
 #define BOOTENV_DEV_QSPI(devtypeu, devtypel, instance) \
 	"bootcmd_qspi=ubi detach; sf probe && " \
+	"setenv mtdids 'nor0=nor0,nand0=nand.0' && " \
+	"setenv mtdparts 'mtdparts=nor0:66m(u-boot),190m(root); " \
+	"nand.0:2m(nand_uboot),500m(nand_root)' && " \
+	"env select UBI; saveenv && " \
+	"ubi part root && " \
 	"if ubi part root && ubi readvol ${scriptaddr} script; " \
 	"then echo QSPI: Running script from UBIFS; " \
 	"elif sf read ${scriptaddr} ${qspiscriptaddr} ${scriptsize}; " \
diff --git a/include/configs/ti_omap5_common.h b/include/configs/ti_omap5_common.h
index 26b6c1cd188..39102f15eb9 100644
--- a/include/configs/ti_omap5_common.h
+++ b/include/configs/ti_omap5_common.h
@@ -239,20 +239,47 @@
 		"if test $fdtfile = undefined; then " \
 			"echo WARNING: Could not determine device tree to use; fi; \0"
 
+#define GET_OVERLAY_MMC_TI_ARGS \
+	"get_overlay_mmc=" \
+		"fdt address ${fdtaddr};" \
+		"fdt resize 0x100000;" \
+		"for overlay in $name_overlays;" \
+		"do;" \
+			"load mmc ${bootpart} ${dtboaddr} ${bootdir}/dtb/${overlay} &&" \
+			"fdt apply ${dtboaddr};" \
+		"done;\0" \
+
 #define BOOT_TARGET_DEVICES(func) \
+	func(TI_MMC, ti_mmc, na) \
 	func(MMC, mmc, 0) \
 	func(MMC, mmc, 1) \
 	func(PXE, pxe, na) \
 	func(DHCP, dhcp, na)
 
+#define BOOTENV_DEV_TI_MMC(devtypeu, devtypel, instance)	\
+	"bootcmd_ti_mmc= run get_name_kern; run mmcboot\0"
+
+#define BOOTENV_DEV_NAME_TI_MMC(devtyeu, devtypel, instance)            \
+	"ti_mmc "
+
 #include <config_distro_bootcmd.h>
 
 #define CFG_EXTRA_ENV_SETTINGS \
 	DEFAULT_LINUX_BOOT_ENV \
 	DEFAULT_MMC_TI_ARGS \
+	"bootpart=0:2\0" \
+	"bootdir=/boot\0" \
+	"get_name_kern=" \
+	"if test $boot_fit -eq 1; then " \
+		"setenv bootfile fitImage; " \
+	"else " \
+		"setenv bootfile zImage; " \
+	"fi\0" \
 	DEFAULT_FIT_TI_ARGS \
+	"get_fit_config=setenv name_fit_config ${fdtfile}\0" \
 	DEFAULT_COMMON_BOOT_TI_ARGS \
 	DEFAULT_FDT_TI_ARGS \
+	GET_OVERLAY_MMC_TI_ARGS \
 	DFUARGS \
 	NETARGS \
 	NANDARGS \
diff --git a/include/configs/vexpress_aemv8.h b/include/configs/vexpress_aemv8.h
index b5a17f93efc..5eee13b3fc0 100644
--- a/include/configs/vexpress_aemv8.h
+++ b/include/configs/vexpress_aemv8.h
@@ -181,12 +181,14 @@
 		"  if load hostfs - ${kernel_addr_r} ${kernel_name}; then"	\
 		"    setenv fdt_high 0xffffffffffffffff;"		\
 		"    setenv initrd_high 0xffffffffffffffff;"		\
-		"    load hostfs - ${fdt_addr_r} ${fdtfile};"			\
+		"    if test -n load hostfs - ${fdt_addr_r} ${fdtfile}; then"			\
+		"        fdt move $fdtcontroladdr $fdt_addr_r;"			\
+		"    fi;"			\
 		"    load hostfs - ${ramdisk_addr_r} ${ramdisk_name};" \
 		"    fdt addr ${fdt_addr_r};"				\
 		"    fdt resize;"					\
 		"    fdt chosen ${ramdisk_addr_r} ${filesize};"	\
-		"    booti $kernel_addr_r - $fdt_addr_r;"		\
+		"    booti $kernel_addr_r - ${fdt_addr_r};"		\
 		"  fi;"							\
 		"fi\0"
 #define BOOTENV_DEV_NAME_SMH(devtypeu, devtypel, instance) "smh "
diff --git a/include/configs/xea.h b/include/configs/xea.h
index 00d62748733..21454d13d21 100644
--- a/include/configs/xea.h
+++ b/include/configs/xea.h
@@ -12,14 +12,6 @@
 #ifndef __CONFIGS_XEA_H__
 #define __CONFIGS_XEA_H__
 
-#include <linux/sizes.h>
-
-/* SPL */
-
-#define CFG_SYS_SPI_KERNEL_OFFS	SZ_1M
-#define CFG_SYS_SPI_ARGS_OFFS	SZ_512K
-#define CFG_SYS_SPI_ARGS_SIZE	SZ_32K
-
 /* Memory configuration */
 #define PHYS_SDRAM_1			0x40000000	/* Base address */
 #define PHYS_SDRAM_1_SIZE		0x10000000	/* Max 256 MB RAM */
diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h
index 13941ba3589..ec78f2ee8ed 100644
--- a/include/configs/xilinx_zynqmp.h
+++ b/include/configs/xilinx_zynqmp.h
@@ -194,12 +194,6 @@
 	"dfu_bufsiz=0x1000\0"
 #endif
 
-#if defined(CONFIG_SPL_SPI_FLASH_SUPPORT)
-# define CFG_SYS_SPI_KERNEL_OFFS	0x80000
-# define CFG_SYS_SPI_ARGS_OFFS	0xa0000
-# define CFG_SYS_SPI_ARGS_SIZE	0xa0000
-#endif
-
 #ifdef CONFIG_SPL_SYS_MALLOC_SIMPLE
 # error "Disable CONFIG_SPL_SYS_MALLOC_SIMPLE. Full malloc needs to be used"
 #endif
diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h
index 37c77aa1611..93ae5891a07 100644
--- a/include/configs/zynq-common.h
+++ b/include/configs/zynq-common.h
@@ -191,14 +191,6 @@
 
 /* Not using MMC raw mode - just for compilation purpose */
 
-/* qspi mode is working fine */
-#ifdef CONFIG_ZYNQ_QSPI
-#define CFG_SYS_SPI_ARGS_OFFS	0x200000
-#define CFG_SYS_SPI_ARGS_SIZE	0x80000
-#define CFG_SYS_SPI_KERNEL_OFFS	(CFG_SYS_SPI_ARGS_OFFS + \
-					CFG_SYS_SPI_ARGS_SIZE)
-#endif
-
 /* SP location before relocation, must use scratch RAM */
 
 /* 3 * 64kB blocks of OCM - one is on the top because of bootrom */
diff --git a/include/cpu_func.h b/include/cpu_func.h
index 7e81c4364a7..70a41ead3f7 100644
--- a/include/cpu_func.h
+++ b/include/cpu_func.h
@@ -69,6 +69,23 @@ void flush_dcache_range(unsigned long start, unsigned long stop);
 void invalidate_dcache_range(unsigned long start, unsigned long stop);
 void invalidate_dcache_all(void);
 void invalidate_icache_all(void);
+
+enum pgprot_attrs {
+	MMU_ATTR_RO,
+	MMU_ATTR_RX,
+	MMU_ATTR_RW,
+};
+
+/** pgprot_set_attrs() - Set page table permissions
+ *
+ * @addr: Physical address start
+ * @size: size of memory to change
+ * @perm: New permissions
+ *
+ * Return: 0 on success, error otherwise.
+ **/
+int pgprot_set_attrs(phys_addr_t addr, size_t size, enum pgprot_attrs perm);
+
 /**
  * noncached_init() - Initialize non-cached memory region
  *
diff --git a/include/dm/device.h b/include/dm/device.h
index add67f9ec06..678cd83c271 100644
--- a/include/dm/device.h
+++ b/include/dm/device.h
@@ -81,7 +81,10 @@ struct driver_info;
  */
 #define DM_FLAG_VITAL			(1 << 14)
 
-/* Device must be probed after it was bound */
+/* Device must be probed after it was bound. This flag is per-device and does
+ * nothing if set on a U_BOOT_DRIVER() definition. Apply it with
+ * dev_or_flags(dev, DM_FLAG_PROBE_AFTER_BIND) in the devices bind function.
+ */
 #define DM_FLAG_PROBE_AFTER_BIND	(1 << 15)
 
 /*
diff --git a/include/dm/ofnode_graph.h b/include/dm/ofnode_graph.h
new file mode 100644
index 00000000000..908c990a3f3
--- /dev/null
+++ b/include/dm/ofnode_graph.h
@@ -0,0 +1,90 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2025 Svyatoslav Ryhel <clamor95@gmail.com>
+ */
+
+#ifndef _DM_OFNODE_GRAPH_H
+#define _DM_OFNODE_GRAPH_H
+
+#include <dm/of.h>
+
+/**
+ * ofnode_graph_get_endpoint_count() - get the number of endpoints in a device ofnode
+ * @parent: ofnode to the device containing ports and endpoints
+ *
+ * Return: count of endpoint of this device ofnode
+ */
+unsigned int ofnode_graph_get_endpoint_count(ofnode parent);
+
+/**
+ * ofnode_graph_get_port_count() - get the number of port in a device or ports ofnode
+ * @parent: ofnode to the device or ports node
+ *
+ * Return: count of port of this device or ports node
+ */
+unsigned int ofnode_graph_get_port_count(ofnode parent);
+
+/**
+ * ofnode_graph_get_port_by_id() - get the port matching a given id
+ * @parent: parent ofnode
+ * @id: id of the port
+ *
+ * Return: ofnode in given port.
+ */
+ofnode ofnode_graph_get_port_by_id(ofnode parent, u32 id);
+
+/**
+ * ofnode_graph_get_endpoint_by_regs() - get the endpoint matching a given id
+ * @parent: parent ofnode
+ * @reg_id: id of the port
+ * @id: id for the endpoint
+ *
+ * Return: ofnode in given endpoint or NULL if not found.
+ * reg and port_reg are ignored when they are -1.
+ */
+ofnode ofnode_graph_get_endpoint_by_regs(ofnode parent, u32 reg_id, u32 id);
+
+/**
+ * ofnode_graph_get_remote_endpoint() - get remote endpoint node
+ * @endoint: ofnode of a local endpoint
+ *
+ * Return: Remote endpoint ofnode linked with local endpoint.
+ */
+ofnode ofnode_graph_get_remote_endpoint(ofnode endpoint);
+
+/**
+ * ofnode_graph_get_port_parent() - get port's parent node
+ * @endpoint: ofnode of a local endpoint
+ *
+ * Return: device ofnode associated with endpoint
+ */
+ofnode ofnode_graph_get_port_parent(ofnode endpoint);
+
+/**
+ * ofnode_graph_get_remote_port_parent() - get remote port's parent ofnode
+ * @endoint: ofnode of a local endpoint
+ *
+ * Return: device ofnode associated with endpoint linked to local endpoint.
+ */
+ofnode ofnode_graph_get_remote_port_parent(ofnode endpoint);
+
+/**
+ * ofnode_graph_get_remote_port() - get remote port ofnode
+ * @endoint: ofnode of a local endpoint
+ *
+ * Return: port ofnode associated with remote endpoint node linked
+ * to local endpoint.
+ */
+ofnode ofnode_graph_get_remote_port(ofnode endpoint);
+
+/**
+ * ofnode_graph_get_remote_node() - get remote parent ofnode for given port/endpoint
+ * @parent: parent ofnode containing graph port/endpoint
+ * @port: identifier (value of reg property) of the parent port ofnode
+ * @endpoint: identifier (value of reg property) of the endpoint ofnode
+ *
+ * Return: device ofnode associated with endpoint linked to local endpoint.
+ */
+ofnode ofnode_graph_get_remote_node(ofnode parent, u32 port, u32 endpoint);
+
+#endif
diff --git a/include/dm/platform_data/serial_mxc.h b/include/dm/platform_data/serial_mxc.h
index cc59eeb1dd1..52657aa3deb 100644
--- a/include/dm/platform_data/serial_mxc.h
+++ b/include/dm/platform_data/serial_mxc.h
@@ -9,6 +9,9 @@
 /* Information about a serial port */
 struct mxc_serial_plat {
 	struct mxc_uart *reg;  /* address of registers in physical memory */
+#if CONFIG_IS_ENABLED(CLK_CCF)
+	struct clk_bulk clks;
+#endif
 	bool use_dte;
 };
 
diff --git a/include/dt-bindings/pinctrl/adi-adsp.h b/include/dt-bindings/pinctrl/adi-adsp.h
new file mode 100644
index 00000000000..7dc8a1ef5c4
--- /dev/null
+++ b/include/dt-bindings/pinctrl/adi-adsp.h
@@ -0,0 +1,21 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * (C) Copyright 2022 - Analog Devices, Inc.
+ *
+ * Written and/or maintained by Timesys Corporation
+ *
+ * Contact: Nathan Barrett-Morrison <nathan.morrison@timesys.com>
+ * Contact: Greg Malysa <greg.malysa@timesys.com>
+ *
+ */
+
+#ifndef DT_BINDINGS_PINCTRL_ADI_ADSP
+#define DT_BINDINGS_PINCTRL_ADI_ADSP
+
+#define ADI_ADSP_PIN(port, pin) (16 * ((port) - 'A') + (pin))
+#define ADI_ADSP_PINFUNC_ALT0 0
+#define ADI_ADSP_PINFUNC_ALT1 1
+#define ADI_ADSP_PINFUNC_ALT2 2
+#define ADI_ADSP_PINFUNC_ALT3 3
+
+#endif
diff --git a/include/dt-bindings/reset/spacemit-k1-reset.h b/include/dt-bindings/reset/spacemit-k1-reset.h
new file mode 100644
index 00000000000..74db58b27ef
--- /dev/null
+++ b/include/dt-bindings/reset/spacemit-k1-reset.h
@@ -0,0 +1,118 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2022 Spacemit Inc.
+ * Copyright (C) 2025 Huan Zhou <pericycle.cc@gmail.com>
+ */
+
+#ifndef __DT_BINDINGS_RESET_SAPCEMIT_K1_H__
+#define __DT_BINDINGS_RESET_SAPCEMIT_K1_H__
+/* APBC */
+#define	RESET_UART1   1
+#define	RESET_UART2   2
+#define	RESET_GPIO    3
+#define	RESET_PWM0    4
+#define	RESET_PWM1    5
+#define	RESET_PWM2    6
+#define	RESET_PWM3    7
+#define	RESET_PWM4    8
+#define	RESET_PWM5    9
+#define	RESET_PWM6    10
+#define	RESET_PWM7    11
+#define	RESET_PWM8    12
+#define	RESET_PWM9    13
+#define	RESET_PWM10   14
+#define	RESET_PWM11   15
+#define	RESET_PWM12   16
+#define	RESET_PWM13   17
+#define	RESET_PWM14   18
+#define	RESET_PWM15   19
+#define	RESET_PWM16   20
+#define	RESET_PWM17   21
+#define	RESET_PWM18   22
+#define	RESET_PWM19   23
+#define	RESET_SSP3    24
+#define	RESET_UART3   25
+#define	RESET_RTC     26
+#define	RESET_TWSI0   27
+#define	RESET_TIMERS1 28
+#define	RESET_AIB     29
+#define	RESET_TIMERS2 30
+#define	RESET_ONEWIRE 31
+#define	RESET_SSPA0   32
+#define	RESET_SSPA1   33
+#define	RESET_DRO     34
+#define	RESET_IR      35
+#define	RESET_TWSI1   36
+#define	RESET_TSEN    37
+#define	RESET_TWSI2   38
+#define	RESET_TWSI4   39
+#define	RESET_TWSI5   40
+#define	RESET_TWSI6   41
+#define	RESET_TWSI7   42
+#define	RESET_TWSI8   43
+#define	RESET_IPC_AP2AUD  44
+#define	RESET_UART4   45
+#define	RESET_UART5   46
+#define	RESET_UART6   47
+#define	RESET_UART7   48
+#define	RESET_UART8   49
+#define	RESET_UART9   50
+#define	RESET_CAN0    51
+
+/* MPMU */
+#define	RESET_WDT     52
+
+/* APMU */
+#define	RESET_JPG        53
+#define	RESET_CSI        54
+#define	RESET_CCIC2_PHY  55
+#define	RESET_CCIC3_PHY  56
+#define	RESET_ISP        57
+#define	RESET_ISP_AHB    58
+#define	RESET_ISP_CI     59
+#define	RESET_ISP_CPP    60
+#define	RESET_LCD        61
+#define	RESET_DSI_ESC    62
+#define	RESET_V2D        63
+#define	RESET_MIPI       64
+#define	RESET_LCD_SPI    65
+#define	RESET_LCD_SPI_BUS  66
+#define	RESET_LCD_SPI_HBUS 67
+#define	RESET_LCD_MCLK     68
+#define	RESET_CCIC_4X      69
+#define	RESET_CCIC1_PHY    70
+#define	RESET_SDH_AXI      71
+#define	RESET_SDH0         72
+#define	RESET_SDH1         73
+#define	RESET_USB_AXI      74
+#define	RESET_USBP1_AXI    75
+#define	RESET_USB3_0       76
+#define	RESET_QSPI         77
+#define	RESET_QSPI_BUS     78
+#define	RESET_DMA          79
+#define	RESET_AES          80
+#define	RESET_VPU          81
+#define	RESET_GPU          82
+#define	RESET_SDH2         83
+#define	RESET_MC           84
+#define	RESET_EM_AXI       85
+#define	RESET_EM           86
+#define	RESET_AUDIO_SYS    87
+#define	RESET_HDMI         88
+#define	RESET_PCIE0        89
+#define	RESET_PCIE1        90
+#define	RESET_PCIE2        91
+#define	RESET_EMAC0        92
+#define	RESET_EMAC1        93
+
+/* APBC2 */
+#define	RESET_SEC_UART1    94
+#define	RESET_SEC_SSP2     95
+#define	RESET_SEC_TWSI3    96
+#define	RESET_SEC_RTC      97
+#define	RESET_SEC_TIMERS0  98
+#define	RESET_SEC_KPC      99
+#define	RESET_SEC_GPIO     100
+#define	RESET_NUMBER       101
+
+#endif
diff --git a/include/efi.h b/include/efi.h
index d005cb6181e..f9bbb175c3a 100644
--- a/include/efi.h
+++ b/include/efi.h
@@ -705,4 +705,17 @@ static inline bool efi_use_host_arch(void)
  */
 int efi_get_pxe_arch(void);
 
+/**
+ * fdt_efi_pmem_setup() - Pmem setup in DT and EFI memory map
+ * @fdt: Devicetree to add the pmem nodes to
+ *
+ * Iterate through all the blkmap devices, look for BLKMAP_MEM devices,
+ * and add pmem nodes corresponding to the blkmap slice to the
+ * devicetree along with removing the corresponding region from the
+ * EFI memory map.
+ *
+ * Returns: 0 on success, negative error on failure
+ */
+int fdt_efi_pmem_setup(void *fdt);
+
 #endif /* _LINUX_EFI_H */
diff --git a/include/efi_loader.h b/include/efi_loader.h
index 1d75d97ebbc..5f769786786 100644
--- a/include/efi_loader.h
+++ b/include/efi_loader.h
@@ -15,13 +15,13 @@
 #include <efi_api.h>
 #include <image.h>
 #include <pe.h>
+#include <setjmp.h>
 #include <linux/list.h>
 #include <linux/sizes.h>
 #include <linux/oid_registry.h>
 
 struct blk_desc;
 struct bootflow;
-struct jmp_buf_data;
 
 #if CONFIG_IS_ENABLED(EFI_LOADER)
 
@@ -129,17 +129,22 @@ static inline void efi_set_bootdev(const char *dev, const char *devnr,
 
 #if CONFIG_IS_ENABLED(NETDEVICES) && CONFIG_IS_ENABLED(EFI_LOADER)
 /* Call this to update the current device path of the efi net device */
-efi_status_t efi_net_set_dp(const char *dev, const char *server);
+efi_status_t efi_net_new_dp(const char *dev, const char *server, struct udevice *udev);
 /* Call this to get the current device path of the efi net device */
-void efi_net_get_dp(struct efi_device_path **dp);
+void efi_net_dp_from_dev(struct efi_device_path **dp, struct udevice *udev, bool cache_only);
 void efi_net_get_addr(struct efi_ipv4_address *ip,
 		      struct efi_ipv4_address *mask,
-		      struct efi_ipv4_address *gw);
+		      struct efi_ipv4_address *gw,
+			  struct udevice *dev);
 void efi_net_set_addr(struct efi_ipv4_address *ip,
 		      struct efi_ipv4_address *mask,
-		      struct efi_ipv4_address *gw);
+		      struct efi_ipv4_address *gw,
+			  struct udevice *dev);
+#if IS_ENABLED(CONFIG_EFI_HTTP_PROTOCOL)
 efi_status_t efi_net_do_request(u8 *url, enum efi_http_method method, void **buffer,
-				u32 *status_code, ulong *file_size, char *headers_buffer);
+				u32 *status_code, ulong *file_size, char *headers_buffer,
+				struct efi_service_binding_protocol *parent);
+#endif
 #define MAX_HTTP_HEADERS_SIZE SZ_64K
 #define MAX_HTTP_HEADERS 100
 #define MAX_HTTP_HEADER_NAME 128
@@ -151,13 +156,16 @@ struct http_header {
 
 void efi_net_parse_headers(ulong *num_headers, struct http_header *headers);
 #else
-static inline void efi_net_get_dp(struct efi_device_path **dp) { }
+static inline void efi_net_dp_from_dev(struct efi_device_path **dp,
+				  struct udevice *udev, bool cache_only) { }
 static inline void efi_net_get_addr(struct efi_ipv4_address *ip,
 				     struct efi_ipv4_address *mask,
-				     struct efi_ipv4_address *gw) { }
+				     struct efi_ipv4_address *gw,
+					 struct udevice *dev) { }
 static inline void efi_net_set_addr(struct efi_ipv4_address *ip,
 				     struct efi_ipv4_address *mask,
-				     struct efi_ipv4_address *gw) { }
+				     struct efi_ipv4_address *gw,
+					 struct udevice *dev) { }
 #endif
 
 /* Maximum number of configuration tables */
@@ -321,6 +329,8 @@ extern const efi_guid_t efi_guid_host_dev;
 #endif
 /* GUID of the EFI_BLOCK_IO_PROTOCOL */
 extern const efi_guid_t efi_block_io_guid;
+/* GUID of the EFI_SIMPLE_NETWORK_PROTOCOL */
+extern const efi_guid_t efi_net_guid;
 extern const efi_guid_t efi_global_variable_guid;
 extern const efi_guid_t efi_guid_console_control;
 extern const efi_guid_t efi_guid_device_path;
@@ -485,7 +495,7 @@ struct efi_loaded_image_obj {
 	efi_status_t *exit_status;
 	efi_uintn_t *exit_data_size;
 	u16 **exit_data;
-	struct jmp_buf_data *exit_jmp;
+	jmp_buf *exit_jmp;
 	EFIAPI efi_status_t (*entry)(efi_handle_t image_handle,
 				     struct efi_system_table *st);
 	u16 image_type;
@@ -647,7 +657,8 @@ int efi_disk_create_partitions(efi_handle_t parent, struct blk_desc *desc,
 /* Called by bootefi to make GOP (graphical) interface available */
 efi_status_t efi_gop_register(void);
 /* Called by bootefi to make the network interface available */
-efi_status_t efi_net_register(void);
+efi_status_t efi_net_register(struct udevice *dev);
+efi_status_t efi_net_do_start(struct udevice *dev);
 /* Called by efi_net_register to make the ip4 config2 protocol available */
 efi_status_t efi_ipconfig_register(const efi_handle_t handle,
 				   struct efi_ip4_config2_protocol *ip4config);
@@ -733,6 +744,10 @@ efi_status_t efi_search_protocol(const efi_handle_t handle,
 efi_status_t efi_add_protocol(const efi_handle_t handle,
 			      const efi_guid_t *protocol,
 			      void *protocol_interface);
+/* Uninstall new protocol on a handle */
+efi_status_t efi_uninstall_protocol
+		(efi_handle_t handle, const efi_guid_t *protocol,
+		 void *protocol_interface, bool preserve);
 /* Reinstall a protocol on a handle */
 efi_status_t EFIAPI efi_reinstall_protocol_interface(
 			efi_handle_t handle,
@@ -748,6 +763,15 @@ efi_status_t EFIAPI
 efi_install_multiple_protocol_interfaces(efi_handle_t *handle, ...);
 efi_status_t EFIAPI
 efi_uninstall_multiple_protocol_interfaces(efi_handle_t handle, ...);
+/* Connect and disconnect controller */
+efi_status_t EFIAPI efi_connect_controller(efi_handle_t controller_handle,
+					   efi_handle_t *driver_image_handle,
+					   struct efi_device_path *remain_device_path,
+					   bool recursive);
+efi_status_t EFIAPI efi_disconnect_controller(
+					efi_handle_t controller_handle,
+					efi_handle_t driver_image_handle,
+					efi_handle_t child_handle);
 /* Get handles that support a given protocol */
 efi_status_t EFIAPI efi_locate_handle_buffer(
 			enum efi_locate_search_type search_type,
@@ -768,6 +792,8 @@ efi_status_t efi_create_event(uint32_t type, efi_uintn_t notify_tpl,
 					void *context),
 			      void *notify_context, const efi_guid_t *group,
 			      struct efi_event **event);
+/* Call this to close an event */
+efi_status_t EFIAPI efi_close_event(struct efi_event *event);
 /* Call this to set a timer */
 efi_status_t efi_set_timer(struct efi_event *event, enum efi_timer_delay type,
 			   uint64_t trigger_time);
@@ -852,6 +878,21 @@ efi_status_t efi_get_memory_map(efi_uintn_t *memory_map_size,
 /* Adds a range into the EFI memory map */
 efi_status_t efi_add_memory_map(u64 start, u64 size, int memory_type);
 
+/**
+ * efi_update_memory_map() - update the memory map by adding/removing pages
+ *
+ * @start:			start address, must be a multiple of
+ *				EFI_PAGE_SIZE
+ * @pages:			number of pages to add
+ * @memory_type:		type of memory added
+ * @overlap_conventional:	region may only overlap free(conventional)
+ *				memory
+ * @remove:			remove memory map
+ * Return:			status code
+ */
+efi_status_t efi_update_memory_map(u64 start, u64 pages, int memory_type,
+				   bool overlap_conventional, bool remove);
+
 /* Called by board init to initialize the EFI drivers */
 efi_status_t efi_driver_init(void);
 /* Called when a block device is added */
@@ -907,8 +948,8 @@ struct efi_device_path *efi_dp_from_part(struct blk_desc *desc, int part);
 struct efi_device_path *efi_dp_part_node(struct blk_desc *desc, int part);
 struct efi_device_path *efi_dp_from_file(const struct efi_device_path *dp,
 					 const char *path);
-struct efi_device_path *efi_dp_from_eth(void);
-struct efi_device_path *efi_dp_from_http(const char *server);
+struct efi_device_path *efi_dp_from_eth(struct udevice *dev);
+struct efi_device_path *efi_dp_from_http(const char *server, struct udevice *dev);
 struct efi_device_path *efi_dp_from_mem(uint32_t mem_type,
 					uint64_t start_address,
 					size_t size);
diff --git a/include/env/nvidia/prod_upd.env b/include/env/nvidia/prod_upd.env
index f4e381994be..6a457d1b75b 100644
--- a/include/env/nvidia/prod_upd.env
+++ b/include/env/nvidia/prod_upd.env
@@ -3,6 +3,7 @@ boot_block_size=0x1000
 bootloader_file=u-boot-dtb-tegra.bin
 spi_size=0x400000
 boot_dev=0
+boot_interface=mmc
 
 flash_uboot=echo Preparing RAM;
 	mw ${kernel_addr_r} 0 ${boot_block_size_r};
@@ -11,9 +12,9 @@ flash_uboot=echo Preparing RAM;
 		mmc dev 0 1;
 		mmc read ${kernel_addr_r} 0 ${boot_block_size};
 		echo Reading bootloader;
-		if load mmc ${boot_dev}:1 ${ramdisk_addr_r} ${bootloader_file};
+		if load ${boot_interface} ${boot_dev}:1 ${ramdisk_addr_r} ${bootloader_file};
 		then echo Calculating bootloader size;
-			size mmc ${boot_dev}:1 ${bootloader_file};
+			size ${boot_interface} ${boot_dev}:1 ${bootloader_file};
 			ebtupdate ${kernel_addr_r} ${ramdisk_addr_r} ${filesize};
 			echo Writing bootloader to eMMC;
 			mmc dev 0 1;
diff --git a/include/env/pg-wcom/common.env b/include/env/pg-wcom/common.env
index 4b660cebd67..5f2ba1c4090 100644
--- a/include/env/pg-wcom/common.env
+++ b/include/env/pg-wcom/common.env
@@ -22,7 +22,6 @@ add_default=setenv bootargs ${bootargs} ip=${ipaddr}:${serverip}:${gatewayip}:${
 		WCOM_UBI_LINUX_MTD
 
 addpanic=setenv bootargs ${bootargs} panic=1 panic_on_oops=1
-altbootcmd=run bootcmd
 backup_bank=0
 boot=bootm ${load_addr_r} - ${fdt_addr_r}
 
diff --git a/include/env/phytec/k3_dfu.env b/include/env/phytec/k3_dfu.env
new file mode 100644
index 00000000000..0cba87da99d
--- /dev/null
+++ b/include/env/phytec/k3_dfu.env
@@ -0,0 +1,3 @@
+dfu_alt_info_ram=
+	tispl.bin ram 0x80080000 0x200000;
+	u-boot.img ram 0x81000000 0x400000
diff --git a/include/env/ti/mmc.h b/include/env/ti/mmc.h
index d07189baaf4..dbb0e3559ea 100644
--- a/include/env/ti/mmc.h
+++ b/include/env/ti/mmc.h
@@ -44,6 +44,7 @@
 	"mmcloados=" \
 		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
 			"if run loadfdt; then " \
+				"run get_overlay_mmc;" \
 				"bootz ${loadaddr} - ${fdtaddr}; " \
 			"else " \
 				"if test ${boot_fdt} = try; then " \
diff --git a/include/env_default.h b/include/env_default.h
index aa3dd40f3fa..60c39f9853f 100644
--- a/include/env_default.h
+++ b/include/env_default.h
@@ -115,6 +115,9 @@ const char default_environment[] = {
 #if defined(CONFIG_BOOTCOUNT_BOOTLIMIT) && (CONFIG_BOOTCOUNT_BOOTLIMIT > 0)
 	"bootlimit="	__stringify(CONFIG_BOOTCOUNT_BOOTLIMIT)"\0"
 #endif
+#ifdef CONFIG_BOOTCOUNT_ALTBOOTCMD
+	"altbootcmd="	CONFIG_BOOTCOUNT_ALTBOOTCMD            "\0"
+#endif
 #ifdef CONFIG_MTDIDS_DEFAULT
 	 "mtdids="	CONFIG_MTDIDS_DEFAULT		"\0"
 #endif
diff --git a/include/exfat.h b/include/exfat.h
new file mode 100644
index 00000000000..7e43beeb348
--- /dev/null
+++ b/include/exfat.h
@@ -0,0 +1,24 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef _EXFAT_H_
+#define _EXFAT_H_
+
+struct disk_partition;
+
+int exfat_fs_opendir(const char *filename, struct fs_dir_stream **dirsp);
+int exfat_fs_readdir(struct fs_dir_stream *dirs, struct fs_dirent **dentp);
+int exfat_fs_ls(const char *dirname);
+int exfat_fs_probe(struct blk_desc *fs_dev_desc,
+		struct disk_partition *fs_partition);
+int exfat_fs_read(const char *filename, void *buf, loff_t offset,
+	       loff_t len, loff_t *actread);
+int exfat_fs_size(const char *filename, loff_t *size);
+int exfat_fs_exists(const char *filename);
+void exfat_fs_close(void);
+void exfat_fs_closedir(struct fs_dir_stream *dirs);
+
+int exfat_fs_unlink(const char *filename);
+int exfat_fs_mkdir(const char *dirname);
+int exfat_fs_write(const char *filename, void *buf, loff_t offset,
+		   loff_t len, loff_t *actwrite);
+
+#endif /* _EXFAT_H */
diff --git a/include/fat.h b/include/fat.h
index 3dce99a23cf..ca97880de12 100644
--- a/include/fat.h
+++ b/include/fat.h
@@ -206,6 +206,7 @@ int fat_opendir(const char *filename, struct fs_dir_stream **dirsp);
 int fat_readdir(struct fs_dir_stream *dirs, struct fs_dirent **dentp);
 void fat_closedir(struct fs_dir_stream *dirs);
 int fat_unlink(const char *filename);
+int fat_rename(const char *old_path, const char *new_path);
 int fat_mkdir(const char *dirname);
 void fat_close(void);
 void *fat_next_cluster(fat_itr *itr, unsigned int *nbytes);
diff --git a/include/fdt_support.h b/include/fdt_support.h
index f0ad2e6b365..049190cf3d7 100644
--- a/include/fdt_support.h
+++ b/include/fdt_support.h
@@ -471,6 +471,20 @@ int fdt_valid(struct fdt_header **blobp);
  */
 int fdt_get_cells_len(const void *blob, char *nr_cells_name);
 
+/**
+ * fdt_fixup_pmem_region() - add a pmem node on the device tree
+ *
+ * This functions adds/updates a pmem node to the device tree.
+ * Usually used with EFI installers to preserve installer
+ * images
+ *
+ * @fdt:	device tree provided by caller
+ * @addr:	start address of the pmem node
+ * @size:	size of the memory of the pmem node
+ * Return:	0 on success or < 0 on failure
+ */
+int fdt_fixup_pmem_region(void *fdt, u64 pmem_start, u64 pmem_size);
+
 #endif /* !USE_HOSTCC */
 
 #ifdef USE_HOSTCC
diff --git a/include/fs.h b/include/fs.h
index 2474880385d..731aaa02637 100644
--- a/include/fs.h
+++ b/include/fs.h
@@ -18,6 +18,7 @@ struct cmd_tbl;
 #define FS_TYPE_SQUASHFS 6
 #define FS_TYPE_EROFS   7
 #define FS_TYPE_SEMIHOSTING 8
+#define FS_TYPE_EXFAT   9
 
 struct blk_desc;
 
@@ -86,7 +87,7 @@ int fs_set_blk_dev_with_part(struct blk_desc *desc, int part);
  *
  * Many file functions implicitly call fs_close(), e.g. fs_closedir(),
  * fs_exist(), fs_ln(), fs_ls(), fs_mkdir(), fs_read(), fs_size(), fs_write(),
- * fs_unlink().
+ * fs_unlink(), fs_rename().
  */
 void fs_close(void);
 
@@ -173,7 +174,7 @@ int fs_write(const char *filename, ulong addr, loff_t offset, loff_t len,
 #define FS_DT_REG  8         /* regular file */
 #define FS_DT_LNK  10        /* symbolic link */
 
-#define FS_DIRENT_NAME_LEN 256
+#define FS_DIRENT_NAME_LEN	CONFIG_IS_ENABLED(FS_EXFAT, (1024), (256))
 
 /**
  * struct fs_dirent - directory entry
@@ -270,6 +271,18 @@ int fs_unlink(const char *filename);
  */
 int fs_mkdir(const char *filename);
 
+/**
+ * fs_rename - rename/move a file or directory
+ *
+ * @old_path: existing path of the file/directory to rename
+ * @new_path: new path of the file/directory. If this points to an existing
+ * file or empty directory, the existing file/directory will be unlinked.
+ * If this points to a non-empty directory, the rename will fail.
+ *
+ * Return: 0 on success, -1 on error conditions
+ */
+int fs_rename(const char *old_path, const char *new_path);
+
 /*
  * Common implementation for various filesystem commands, optionally limited
  * to a specific filesystem type via the fstype parameter.
@@ -290,6 +303,8 @@ int do_mkdir(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[],
 	     int fstype);
 int do_ln(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[],
 	  int fstype);
+int do_mv(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[],
+	  int fstype);
 
 /*
  * Determine the UUID of the specified filesystem and print it. Optionally it is
diff --git a/include/fs_internal.h b/include/fs_internal.h
index 07f6bc5ea40..351582db61a 100644
--- a/include/fs_internal.h
+++ b/include/fs_internal.h
@@ -12,5 +12,7 @@
 
 int fs_devread(struct blk_desc *, struct disk_partition *, lbaint_t, int, int,
 	       char *);
+int fs_devwrite(struct blk_desc *, struct disk_partition *, lbaint_t, int, int,
+	        const char *);
 
 #endif /* __U_BOOT_FS_INTERNAL_H__ */
diff --git a/include/fuse.h b/include/fuse.h
index 4519821af7e..902b5f56a74 100644
--- a/include/fuse.h
+++ b/include/fuse.h
@@ -12,6 +12,7 @@
 #define _FUSE_H_
 
 #include <linux/types.h>
+#include <linux/errno.h>
 
 /*
  * Read/Sense/Program/Override interface:
@@ -25,5 +26,13 @@ int fuse_read(u32 bank, u32 word, u32 *val);
 int fuse_sense(u32 bank, u32 word, u32 *val);
 int fuse_prog(u32 bank, u32 word, u32 val);
 int fuse_override(u32 bank, u32 word, u32 val);
+#ifdef CONFIG_CMD_FUSE_WRITEBUFF
+int fuse_writebuff(ulong addr);
+#else
+static inline int fuse_writebuff(ulong addr)
+{
+	return -EPERM;
+}
+#endif	/* CONFIG_CMD_FUSE_WRITEBUFF */
 
 #endif	/* _FUSE_H_ */
diff --git a/include/image.h b/include/image.h
index 07912606f33..c1db8383459 100644
--- a/include/image.h
+++ b/include/image.h
@@ -1688,6 +1688,24 @@ struct sig_header_s {
  */
 int image_pre_load(ulong addr);
 
+#if defined(USE_HOSTCC)
+/**
+ * rsa_verify_openssl() - Verify a signature against some data with openssl API
+ *
+ * Verify a RSA PKCS1.5/PSS signature against an expected hash.
+ *
+ * @info:		Specifies the key and algorithms
+ * @region:		Pointer to the input data
+ * @region_count:	Number of region
+ * @sig:		Signature
+ * @sig_len:		Number of bytes in the signature
+ * Return: 0 if verified, -ve on error
+ */
+int rsa_verify_openssl(struct image_sign_info *info,
+		       const struct image_region region[], int region_count,
+		       uint8_t *sig, uint sig_len);
+#endif
+
 /**
  * fit_image_verify_required_sigs() - Verify signatures marked as 'required'
  *
diff --git a/include/interrupt.h b/include/interrupt.h
index 46ef2e196d4..6ea28b54a56 100644
--- a/include/interrupt.h
+++ b/include/interrupt.h
@@ -1,6 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-or-later */
 
-#include <asm/setjmp.h>
+#include <setjmp.h>
 
 /**
  * struct resume_data - data for resume after interrupt
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index 59f9c241b84..5ea2171492e 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -105,7 +105,7 @@ struct clk_gate {
 #define CLK_GATE_HIWORD_MASK		BIT(1)
 
 extern const struct clk_ops clk_gate_ops;
-struct clk *clk_register_gate(struct device *dev, const char *name,
+struct clk *clk_register_gate(struct udevice *dev, const char *name,
 			      const char *parent_name, unsigned long flags,
 			      void __iomem *reg, u8 bit_idx,
 			      u8 clk_gate_flags, spinlock_t *lock);
@@ -223,7 +223,7 @@ struct clk_composite {
 
 #define to_clk_composite(_clk) container_of(_clk, struct clk_composite, clk)
 
-struct clk *clk_register_composite(struct device *dev, const char *name,
+struct clk *clk_register_composite(struct udevice *dev, const char *name,
 		const char * const *parent_names, int num_parents,
 		struct clk *mux_clk, const struct clk_ops *mux_ops,
 		struct clk *rate_clk, const struct clk_ops *rate_ops,
@@ -233,16 +233,16 @@ struct clk *clk_register_composite(struct device *dev, const char *name,
 int clk_register(struct clk *clk, const char *drv_name, const char *name,
 		 const char *parent_name);
 
-struct clk *clk_register_fixed_factor(struct device *dev, const char *name,
+struct clk *clk_register_fixed_factor(struct udevice *dev, const char *name,
 		const char *parent_name, unsigned long flags,
 		unsigned int mult, unsigned int div);
 
-struct clk *clk_register_divider(struct device *dev, const char *name,
+struct clk *clk_register_divider(struct udevice *dev, const char *name,
 		const char *parent_name, unsigned long flags,
 		void __iomem *reg, u8 shift, u8 width,
 		u8 clk_divider_flags);
 
-struct clk *clk_register_mux(struct device *dev, const char *name,
+struct clk *clk_register_mux(struct udevice *dev, const char *name,
 		const char * const *parent_names, u8 num_parents,
 		unsigned long flags,
 		void __iomem *reg, u8 shift, u8 width,
diff --git a/include/linux/mtd/rawnand.h b/include/linux/mtd/rawnand.h
index 2d85b392465..3e80b134063 100644
--- a/include/linux/mtd/rawnand.h
+++ b/include/linux/mtd/rawnand.h
@@ -132,6 +132,17 @@ void nand_wait_ready(struct mtd_info *mtd);
 #define NAND_DATA_IFACE_CHECK_ONLY	-1
 
 /*
+ * There are different places where the manufacturer stores the factory bad
+ * block markers.
+ *
+ * Position within the block: Each of these pages needs to be checked for a
+ * bad block marking pattern.
+ */
+#define NAND_BBM_FIRSTPAGE	BIT(24)
+#define NAND_BBM_SECONDPAGE	BIT(25)
+#define NAND_BBM_LASTPAGE	BIT(26)
+
+/*
  * Constants for ECC_MODES
  */
 typedef enum {
@@ -981,6 +992,7 @@ struct nand_chip {
 	struct nand_bbt_descr *bbt_md;
 
 	struct nand_bbt_descr *badblock_pattern;
+	int cur_cs;
 
 	void *priv;
 
diff --git a/include/linux/stat.h b/include/linux/stat.h
index 5eba6334e60..b65bff7e97d 100644
--- a/include/linux/stat.h
+++ b/include/linux/stat.h
@@ -65,9 +65,7 @@ struct stat {
 	unsigned long	__unused5;
 };
 
-#endif	/* __PPC__ */
-
-#if defined (__ARM__) || defined (__I386__) || defined (__M68K__) || defined (__bfin__) ||\
+#elif defined (__ARM__) || defined (__I386__) || defined (__M68K__) || defined (__bfin__) ||\
 	defined (__microblaze__) || defined (__nios2__)
 
 struct stat {
@@ -93,9 +91,7 @@ struct stat {
 	unsigned long  __unused5;
 };
 
-#endif	/* __ARM__ */
-
-#if defined (__MIPS__)
+#elif defined (__MIPS__)
 
 struct stat {
 	dev_t		st_dev;
@@ -124,9 +120,7 @@ struct stat {
 	long		st_pad4[14];
 };
 
-#endif	/* __MIPS__ */
-
-#if defined(__SH__) || defined(__XTENSA__)
+#elif defined(__SH__) || defined(__XTENSA__)
 
 struct stat {
 	unsigned long st_dev;
@@ -149,7 +143,38 @@ struct stat {
 	unsigned long  __unused5;
 };
 
-#endif /* __SH__  || __XTENSA__ */
+#else
+
+/*
+ * Everybody gets this wrong and has to stick with it for all
+ * eternity. Hopefully, this version gets used by new architectures
+ * so they don't fall into the same traps.
+ *
+ */
+struct stat {
+	unsigned long	st_dev;		/* Device.  */
+	unsigned long	st_ino;		/* File serial number.  */
+	unsigned int	st_mode;	/* File mode.  */
+	unsigned int	st_nlink;	/* Link count.  */
+	unsigned int	st_uid;		/* User ID of the file's owner.  */
+	unsigned int	st_gid;		/* Group ID of the file's group. */
+	unsigned long	st_rdev;	/* Device number, if device.  */
+	unsigned long	__pad1;
+	long		st_size;	/* Size of file, in bytes.  */
+	int		st_blksize;	/* Optimal block size for I/O.  */
+	int		__pad2;
+	long		st_blocks;	/* Number 512-byte blocks allocated. */
+	long		st_atime;	/* Time of last access.  */
+	unsigned long	st_atime_nsec;
+	long		st_mtime;	/* Time of last modification.  */
+	unsigned long	st_mtime_nsec;
+	long		st_ctime;	/* Time of last status change.  */
+	unsigned long	st_ctime_nsec;
+	unsigned int	__unused4;
+	unsigned int	__unused5;
+};
+
+#endif
 
 #ifdef __cplusplus
 }
diff --git a/include/mapmem.h b/include/mapmem.h
index f496c96d16c..8ec03d59f0b 100644
--- a/include/mapmem.h
+++ b/include/mapmem.h
@@ -33,7 +33,7 @@ static inline phys_addr_t map_to_sysmem(const void *ptr)
  * nomap_sysmem() - pass through an address unchanged
  *
  * This is used to indicate an address which should NOT be mapped, e.g. in
- * SMBIOS tables. Using this function instead of a case shows that the sandbox
+ * SMBIOS tables. Using this function instead of a cast shows that the sandbox
  * conversion has been done
  */
 static inline void *nomap_sysmem(phys_addr_t paddr, unsigned long len)
diff --git a/include/membuff.h b/include/membuf.h
index 4eba626ce1c..46764690f53 100644
--- a/include/membuff.h
+++ b/include/membuf.h
@@ -6,11 +6,13 @@
  * Copyright (c) 1992 Simon Glass
  */
 
-#ifndef _MEMBUFF_H
-#define _MEMBUFF_H
+#ifndef _membuf_H
+#define _membuf_H
+
+#include <stdbool.h>
 
 /**
- * @struct membuff: holds the state of a membuff - it is used for input and
+ * @struct membuf: holds the state of a membuff - it is used for input and
  * output buffers. The buffer extends from @start to (@start + @size - 1).
  * Data in the buffer extends from @tail to @head: it is written in at
  * @head and read out from @tail. The membuff is empty when @head == @tail
@@ -23,13 +25,13 @@
  *
  * .............xxxxxxxxxxxxxxxx.........................
  *		^		^
- *		tail		head
+ * ^start	tail		head                     ^end
  *
  * xxxxxxxxxxxxx................xxxxxxxxxxxxxxxxxxxxxxxxx
  *		^		^
  *		head		tail
  */
-struct membuff {
+struct membuf {
 	char *start;		/** the start of the buffer */
 	char *end;		/** the end of the buffer (start + length) */
 	char *head;		/** current buffer head */
@@ -37,16 +39,16 @@ struct membuff {
 };
 
 /**
- * membuff_purge() - reset a membuff to the empty state
+ * membuf_purge() - reset a membuff to the empty state
  *
  * Initialise head and tail pointers so that the membuff becomes empty.
  *
  * @mb: membuff to purge
  */
-void membuff_purge(struct membuff *mb);
+void membuf_purge(struct membuf *mb);
 
 /**
- * membuff_putraw() - find out where bytes can be written
+ * membuf_putraw() - find out where bytes can be written
  *
  * Work out where in the membuff some data could be written. Return a pointer
  * to the address and the number of bytes which can be written there. If
@@ -64,10 +66,10 @@ void membuff_purge(struct membuff *mb);
  * @data: the address data can be written to
  * Return: number of bytes which can be written
  */
-int membuff_putraw(struct membuff *mb, int maxlen, bool update, char **data);
+int membuf_putraw(struct membuf *mb, int maxlen, bool update, char **data);
 
 /**
- * membuff_getraw() - find and return a pointer to available bytes
+ * membuf_getraw() - find and return a pointer to available bytes
  *
  * Returns a pointer to any valid input data in the given membuff and
  * optionally marks it as read. Note that not all input data may not be
@@ -82,37 +84,37 @@ int membuff_putraw(struct membuff *mb, int maxlen, bool update, char **data);
  * @data: returns address of data in input membuff
  * Return: the number of bytes available at *@data
  */
-int membuff_getraw(struct membuff *mb, int maxlen, bool update, char **data);
+int membuf_getraw(struct membuf *mb, int maxlen, bool update, char **data);
 
 /**
- * membuff_putbyte() - Writes a byte to a membuff
+ * membuf_putbyte() - Writes a byte to a membuff
  *
  * @mb: membuff to adjust
  * @ch: byte to write
  * Return: true on success, false if membuff is full
  */
-bool membuff_putbyte(struct membuff *mb, int ch);
+bool membuf_putbyte(struct membuf *mb, int ch);
 
 /**
  * @mb: membuff to adjust
- * membuff_getbyte() - Read a byte from the membuff
+ * membuf_getbyte() - Read a byte from the membuff
  * Return: the byte read, or -1 if the membuff is empty
  */
-int membuff_getbyte(struct membuff *mb);
+int membuf_getbyte(struct membuf *mb);
 
 /**
- * membuff_peekbyte() - check the next available byte
+ * membuf_peekbyte() - check the next available byte
  *
- * Return the next byte which membuff_getbyte() would return, without
+ * Return the next byte which membuf_getbyte() would return, without
  * removing it from the membuff.
  *
  * @mb: membuff to adjust
  * Return: the byte peeked, or -1 if the membuff is empty
  */
-int membuff_peekbyte(struct membuff *mb);
+int membuf_peekbyte(struct membuf *mb);
 
 /**
- * membuff_get() - get data from a membuff
+ * membuf_get() - get data from a membuff
  *
  * Copies any available data (up to @maxlen bytes) to @buff and removes it
  * from the membuff.
@@ -122,10 +124,10 @@ int membuff_peekbyte(struct membuff *mb);
  * @maxlen: maximum number of bytes to read
  * Return: the number of bytes read
  */
-int membuff_get(struct membuff *mb, char *buff, int maxlen);
+int membuf_get(struct membuf *mb, char *buff, int maxlen);
 
 /**
- * membuff_put() - write data to a membuff
+ * membuf_put() - write data to a membuff
  *
  * Writes some data to a membuff. Returns the number of bytes added. If this
  * is less than @lnehgt, then the membuff got full
@@ -135,36 +137,36 @@ int membuff_get(struct membuff *mb, char *buff, int maxlen);
  * @length: number of bytes to write from 'data'
  * Return: the number of bytes added
  */
-int membuff_put(struct membuff *mb, const char *buff, int length);
+int membuf_put(struct membuf *mb, const char *buff, int length);
 
 /**
- * membuff_isempty() - check if a membuff is empty
+ * membuf_isempty() - check if a membuff is empty
  *
  * @mb: membuff to check
  * Return: true if empty, else false
  */
-bool membuff_isempty(struct membuff *mb);
+bool membuf_isempty(struct membuf *mb);
 
 /**
- * membuff_avail() - check available data in a membuff
+ * membuf_avail() - check available data in a membuff
  *
  * @mb: membuff to check
  * Return: number of bytes of data available
  */
-int membuff_avail(struct membuff *mb);
+int membuf_avail(struct membuf *mb);
 
 /**
- * membuff_size() - get the size of a membuff
+ * membuf_size() - get the size of a membuff
  *
  * Note that a membuff can only old data up to one byte less than its size.
  *
  * @mb: membuff to check
  * Return: total size
  */
-int membuff_size(struct membuff *mb);
+int membuf_size(struct membuf *mb);
 
 /**
- * membuff_makecontig() - adjust all membuff data to be contiguous
+ * membuf_makecontig() - adjust all membuff data to be contiguous
  *
  * This places all data in a membuff into a single contiguous lump, if
  * possible
@@ -172,18 +174,18 @@ int membuff_size(struct membuff *mb);
  * @mb: membuff to adjust
  * Return: true on success
  */
-bool membuff_makecontig(struct membuff *mb);
+bool membuf_makecontig(struct membuf *mb);
 
 /**
- * membuff_free() - find the number of bytes that can be written to a membuff
+ * membuf_free() - find the number of bytes that can be written to a membuff
  *
  * @mb: membuff to check
  * Return: returns the number of bytes free in a membuff
  */
-int membuff_free(struct membuff *mb);
+int membuf_free(struct membuf *mb);
 
 /**
- * membuff_readline() - read a line of text from a membuff
+ * membuf_readline() - read a line of text from a membuff
  *
  * Reads a line of text of up to 'maxlen' characters from a membuff and puts
  * it in @str. Any character less than @minch is assumed to be the end of
@@ -192,14 +194,16 @@ int membuff_free(struct membuff *mb);
  * @mb: membuff to adjust
  * @str: Place to put the line
  * @maxlen: Maximum line length (excluding terminator)
+ * @minch: Minimum ASCII character to permit as part of the line (e.g. ' ')
  * @must_fit: If true then str is empty if line doesn't fit
  * Return: number of bytes read (including terminator) if a line has been
  *	   read, 0 if nothing was there or line didn't fit when must_fit is set
  */
-int membuff_readline(struct membuff *mb, char *str, int maxlen, int minch, bool must_fit);
+int membuf_readline(struct membuf *mb, char *str, int maxlen, int minch,
+		    bool must_fit);
 
 /**
- * membuff_extend_by() - expand a membuff
+ * membuf_extend_by() - expand a membuff
  *
  * Extends a membuff by the given number of bytes
  *
@@ -209,38 +213,38 @@ int membuff_readline(struct membuff *mb, char *str, int maxlen, int minch, bool
  * Return: 0 if the expand succeeded, -ENOMEM if not enough memory, -E2BIG
  * if the the size would exceed @max
  */
-int membuff_extend_by(struct membuff *mb, int by, int max);
+int membuf_extend_by(struct membuf *mb, int by, int max);
 
 /**
- * membuff_init() - set up a new membuff using an existing membuff
+ * membuf_init() - set up a new membuff using an existing membuff
  *
  * @mb: membuff to set up
  * @buff: Address of buffer
  * @size: Size of buffer
  */
-void membuff_init(struct membuff *mb, char *buff, int size);
+void membuf_init(struct membuf *mb, char *buff, int size);
 
 /**
- * membuff_uninit() - clear a membuff so it can no longer be used
+ * membuf_uninit() - clear a membuff so it can no longer be used
  *
  * @mb: membuff to uninit
  */
-void membuff_uninit(struct membuff *mb);
+void membuf_uninit(struct membuf *mb);
 
 /**
- * membuff_new() - create a new membuff
+ * membuf_new() - create a new membuff
  *
  * @mb: membuff to init
  * @size: size of membuff to create
  * Return: 0 if OK, -ENOMEM if out of memory
  */
-int membuff_new(struct membuff *mb, int size);
+int membuf_new(struct membuf *mb, int size);
 
 /**
- * membuff_dispose() - free memory allocated to a membuff and uninit it
+ * membuf_dispose() - free memory allocated to a membuff and uninit it
  *
  * @mb: membuff to dispose
  */
-void membuff_dispose(struct membuff *mb);
+void membuf_dispose(struct membuf *mb);
 
 #endif
diff --git a/include/miiphy.h b/include/miiphy.h
index 63ec3bcc76b..00d0b9b6a43 100644
--- a/include/miiphy.h
+++ b/include/miiphy.h
@@ -61,33 +61,19 @@ void mdio_list_devices(void);
 
 #define BB_MII_DEVNAME	"bb_miiphy"
 
-struct bb_miiphy_bus {
-	char name[MDIO_NAME_LEN];
-	int (*init)(struct bb_miiphy_bus *bus);
-	int (*mdio_active)(struct bb_miiphy_bus *bus);
-	int (*mdio_tristate)(struct bb_miiphy_bus *bus);
-	int (*set_mdio)(struct bb_miiphy_bus *bus, int v);
-	int (*get_mdio)(struct bb_miiphy_bus *bus, int *v);
-	int (*set_mdc)(struct bb_miiphy_bus *bus, int v);
-	int (*delay)(struct bb_miiphy_bus *bus);
-	void *priv;
+struct bb_miiphy_bus_ops {
+	int (*mdio_active)(struct mii_dev *miidev);
+	int (*mdio_tristate)(struct mii_dev *miidev);
+	int (*set_mdio)(struct mii_dev *miidev, int v);
+	int (*get_mdio)(struct mii_dev *miidev, int *v);
+	int (*set_mdc)(struct mii_dev *miidev, int v);
+	int (*delay)(struct mii_dev *miidev);
 };
 
-extern struct bb_miiphy_bus bb_miiphy_buses[];
-extern int bb_miiphy_buses_num;
-
-/**
- * bb_miiphy_init() - Initialize bit-banged MII bus driver
- *
- * It is called during the generic post-relocation init sequence.
- *
- * Return: 0 if OK
- */
-int bb_miiphy_init(void);
-
-int bb_miiphy_read(struct mii_dev *miidev, int addr, int devad, int reg);
-int bb_miiphy_write(struct mii_dev *miidev, int addr, int devad, int reg,
-		    u16 value);
+int bb_miiphy_read(struct mii_dev *miidev, const struct bb_miiphy_bus_ops *ops,
+		   int addr, int devad, int reg);
+int bb_miiphy_write(struct mii_dev *miidev, const struct bb_miiphy_bus_ops *ops,
+		    int addr, int devad, int reg, u16 value);
 #endif
 
 /* phy seed setup */
diff --git a/include/net-common.h b/include/net-common.h
index 89679e20860..30860f5975a 100644
--- a/include/net-common.h
+++ b/include/net-common.h
@@ -291,6 +291,7 @@ struct eth_ops {
 #define eth_get_ops(dev) ((struct eth_ops *)(dev)->driver->ops)
 
 struct udevice *eth_get_dev(void); /* get the current device */
+void eth_set_dev(struct udevice *dev); /* set a device */
 unsigned char *eth_get_ethaddr(void); /* get the current device MAC */
 int eth_rx(void);                      /* Check for received packets */
 void eth_halt(void);			/* stop SCC */
diff --git a/include/phy.h b/include/phy.h
index 36785031eeb..36354aaf774 100644
--- a/include/phy.h
+++ b/include/phy.h
@@ -334,6 +334,30 @@ int gen10g_shutdown(struct phy_device *phydev);
 int gen10g_discover_mmds(struct phy_device *phydev);
 
 /**
+ * phy_set_bits - Convenience function for setting bits in a PHY register
+ * @phydev: the phy_device struct
+ * @devad: The MMD to read from
+ * @regnum: register number to write
+ * @val: bits to set
+ */
+static inline int phy_set_bits(struct phy_device *phydev, int devad, u32 regnum, u16 val)
+{
+	return phy_modify(phydev, devad, regnum, 0, val);
+}
+
+/**
+ * phy_clear_bits - Convenience function for clearing bits in a PHY register
+ * @phydev: the phy_device struct
+ * @devad: The MMD to write to
+ * @regnum: register number to write
+ * @val: bits to clear
+ */
+static inline int phy_clear_bits(struct phy_device *phydev, int devad, u32 regnum, u16 val)
+{
+	return phy_modify(phydev, devad, regnum, val, 0);
+}
+
+/**
  * U_BOOT_PHY_DRIVER() - Declare a new U-Boot driver
  * @__name: name of the driver
  */
diff --git a/include/renesas/rzg2l-usbphy.h b/include/renesas/rzg2l-usbphy.h
new file mode 100644
index 00000000000..1a46b585f17
--- /dev/null
+++ b/include/renesas/rzg2l-usbphy.h
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * RZ/G2L USB PHY common definitions
+ *
+ * Copyright (C) 2021-2023 Renesas Electronics Corp.
+ */
+
+#ifndef RENESAS_RZG2L_USBPHY_H
+#define RENESAS_RZG2L_USBPHY_H
+
+#include <fdtdec.h>
+
+struct rzg2l_usbphy_ctrl_priv {
+	fdt_addr_t regs;
+};
+
+#endif /* RENESAS_RZG2L_USBPHY_H */
diff --git a/include/serial.h b/include/serial.h
index e5f6d984d28..0a707ca730d 100644
--- a/include/serial.h
+++ b/include/serial.h
@@ -48,26 +48,6 @@ extern int serial_assign(const char *name);
 extern void serial_reinit_all(void);
 int serial_initialize(void);
 
-/* For usbtty */
-#ifdef CONFIG_USB_TTY
-
-struct stdio_dev;
-
-int usbtty_getc(struct stdio_dev *dev);
-void usbtty_putc(struct stdio_dev *dev, const char c);
-void usbtty_puts(struct stdio_dev *dev, const char *str);
-int usbtty_tstc(struct stdio_dev *dev);
-
-#else
-
-/* stubs */
-#define usbtty_getc(dev) 0
-#define usbtty_putc(dev, a)
-#define usbtty_puts(dev, a)
-#define usbtty_tstc(dev) 0
-
-#endif /* CONFIG_USB_TTY */
-
 struct udevice;
 
 enum serial_par {
diff --git a/include/setjmp.h b/include/setjmp.h
new file mode 100644
index 00000000000..37d3a8af85d
--- /dev/null
+++ b/include/setjmp.h
@@ -0,0 +1,40 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef _SETJMP_H_
+#define _SETJMP_H_ 1
+
+#ifdef CONFIG_HAVE_SETJMP
+#include <asm/setjmp.h>
+#else
+struct jmp_buf_data {
+};
+#endif
+
+/**
+ * typedef jmp_buf - information needed to restore a calling environment
+ */
+typedef struct jmp_buf_data jmp_buf[1];
+
+/**
+ * setjmp() - prepare for a long jump
+ *
+ * Registers, the stack pointer, and the return address are saved in the
+ * jump bufffer. The function returns zero afterwards. When longjmp() is
+ * executed the function returns a second time with a non-zero value.
+ *
+ * @env:	jump buffer used to store register values
+ * Return:	0 after setting up jump buffer, non-zero after longjmp()
+ */
+int setjmp(jmp_buf env);
+
+/**
+ * longjmp() - long jump
+ *
+ * Jump back to the address and the register state saved by setjmp().
+ *
+ * @env:	jump buffer
+ * @val:	value to be returned by setjmp(), 0 is replaced by 1
+ */
+void longjmp(jmp_buf env, int val);
+
+#endif /* _SETJMP_H_ */
diff --git a/include/stdio_dev.h b/include/stdio_dev.h
index 4e3c4708f80..f7f9c10199e 100644
--- a/include/stdio_dev.h
+++ b/include/stdio_dev.h
@@ -101,7 +101,6 @@ struct stdio_dev *stdio_clone(struct stdio_dev *dev);
 int drv_lcd_init(void);
 int drv_video_init(void);
 int drv_keyboard_init(void);
-int drv_usbtty_init(void);
 int drv_usbacm_init(void);
 int drv_nc_init(void);
 int drv_jtag_console_init(void);
diff --git a/include/sysinfo.h b/include/sysinfo.h
index ba2ac273e8e..e87cf969fcd 100644
--- a/include/sysinfo.h
+++ b/include/sysinfo.h
@@ -57,6 +57,7 @@ enum sysinfo_id {
 	SYSID_SM_SYSTEM_WAKEUP,
 	SYSID_SM_SYSTEM_SKU,
 	SYSID_SM_SYSTEM_FAMILY,
+	SYSID_SM_SYSTEM_UUID,
 
 	/* Baseboard (or Module) Information (Type 2) */
 	SYSID_SM_BASEBOARD_MANUFACTURER,
@@ -151,6 +152,8 @@ enum sysinfo_id {
 	/* For show_board_info() */
 	SYSID_BOARD_MODEL,
 	SYSID_BOARD_MANUFACTURER,
+	SYSID_BOARD_MAC_ADDR,
+	SYSID_BOARD_RAM_SIZE_MB,
 	SYSID_PRIOR_STAGE_VERSION,
 	SYSID_PRIOR_STAGE_DATE,
 
@@ -221,6 +224,30 @@ struct sysinfo_ops {
 	int (*get_data)(struct udevice *dev, int id, void **data, size_t *size);
 
 	/**
+	 * get_item_count() - Get the item count of the specific data area that
+	 *		describes the hardware setup.
+	 * @dev:	The sysinfo instance to gather the data.
+	 * @id:		A unique identifier for the data area to be get.
+	 *
+	 * Return: non-negative item count if OK, -ve on error.
+	 */
+	int (*get_item_count)(struct udevice *dev, int id);
+
+	/**
+	 * get_data_by_index() - Get a data value by index from the platform.
+	 *
+	 * @dev:	The sysinfo instance to gather the data.
+	 * @id:		A unique identifier for the data area to be get.
+	 * @index:	The item index, starting from 0.
+	 * @data:	Pointer to the address of the data area.
+	 * @size:	Pointer to the size of the data area.
+	 *
+	 * Return: 0 if OK, -ve on error.
+	 */
+	int (*get_data_by_index)(struct udevice *dev, int id, int index,
+				 void **data, size_t *size);
+
+	/**
 	 * get_fit_loadable - Get the name of an image to load from FIT
 	 * This function can be used to provide the image names based on runtime
 	 * detection. A classic use-case would when DTBOs are used to describe
@@ -304,6 +331,32 @@ int sysinfo_get_str(struct udevice *dev, int id, size_t size, char *val);
 int sysinfo_get_data(struct udevice *dev, int id, void **data, size_t *size);
 
 /**
+ * sysinfo_get_item_count() - Get the item count of the specific data area that
+ *			    describes the hardware setup.
+ * @dev:	The sysinfo instance to gather the data.
+ * @id:		A unique identifier for the data area to be get.
+ *
+ * Return: non-negative item count if OK, -EPERM if called before
+ * sysinfo_detect(), else -ve on error.
+ */
+int sysinfo_get_item_count(struct udevice *dev, int id);
+
+/**
+ * sysinfo_get_data_by_index() - Get a data value by index from the platform.
+ *
+ * @dev:	The sysinfo instance to gather the data.
+ * @id:		A unique identifier for the data area to be get.
+ * @index:	The item index, starting from 0.
+ * @data:	Pointer to the address of the data area.
+ * @size:	Pointer to the size of the data area.
+ *
+ * Return: 0 if OK, -EPERM if called before sysinfo_detect(), else -ve on
+ * error.
+ */
+int sysinfo_get_data_by_index(struct udevice *dev, int id, int index,
+			      void **data, size_t *size);
+
+/**
  * sysinfo_get() - Return the sysinfo device for the sysinfo in question.
  * @devp: Pointer to structure to receive the sysinfo device.
  *
@@ -364,6 +417,18 @@ static inline int sysinfo_get_data(struct udevice *dev, int id, void **data,
 	return -ENOSYS;
 }
 
+static inline int sysinfo_get_item_count(struct udevice *dev, int id)
+{
+	return -ENOSYS;
+}
+
+static inline int sysinfo_get_data_by_index(struct udevice *dev, int id,
+					    int index, void **data,
+					    size_t *size)
+{
+	return -ENOSYS;
+}
+
 static inline int sysinfo_get(struct udevice **devp)
 {
 	return -ENOSYS;
diff --git a/include/test/fdt_overlay.h b/include/test/fdt_overlay.h
new file mode 100644
index 00000000000..251ad0ec97a
--- /dev/null
+++ b/include/test/fdt_overlay.h
@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2016 NextThing Co
+ * Copyright (c) 2016 Free Electrons
+ */
+
+#ifndef __TEST_OVERLAY_H__
+#define __TEST_OVERLAY_H__
+
+#include <test/test.h>
+
+/* Declare a new FDT-overlay test */
+#define FDT_OVERLAY_TEST(_name, _flags)	UNIT_TEST(_name, _flags, fdt_overlay)
+
+/* Declare init for FDT-overlay test */
+#define FDT_OVERLAY_TEST_INIT(_name, _flags)		\
+	UNIT_TEST_INIT(_name, _flags, fdt_overlay)
+
+#endif /* __TEST_OVERLAY_H__ */
diff --git a/include/test/optee.h b/include/test/optee.h
index f4255b39ee3..0a548a59e83 100644
--- a/include/test/optee.h
+++ b/include/test/optee.h
@@ -8,7 +8,9 @@
 
 #include <test/test.h>
 
-/* Declare a new environment test */
+/* Declare a new optee test */
 #define OPTEE_TEST(_name, _flags)	UNIT_TEST(_name, _flags, optee)
+#define OPTEE_TEST_INIT(_name, _flags)	UNIT_TEST_INIT(_name, _flags, optee)
+#define OPTEE_TEST_UNINIT(_name, _flags) UNIT_TEST_UNINIT(_name, _flags, optee)
 
 #endif /* __TEST_OPTEE_H__ */
diff --git a/include/test/overlay.h b/include/test/overlay.h
deleted file mode 100644
index 5dc98399ce7..00000000000
--- a/include/test/overlay.h
+++ /dev/null
@@ -1,15 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (c) 2016 NextThing Co
- * Copyright (c) 2016 Free Electrons
- */
-
-#ifndef __TEST_OVERLAY_H__
-#define __TEST_OVERLAY_H__
-
-#include <test/test.h>
-
-/* Declare a new environment test */
-#define OVERLAY_TEST(_name, _flags)	UNIT_TEST(_name, _flags, overlay)
-
-#endif /* __TEST_OVERLAY_H__ */
diff --git a/include/test/suites.h b/include/test/suites.h
deleted file mode 100644
index 774dd893378..00000000000
--- a/include/test/suites.h
+++ /dev/null
@@ -1,43 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * (C) Copyright 2015
- * Joe Hershberger, National Instruments, joe.hershberger@ni.com
- */
-
-#ifndef __TEST_SUITES_H__
-#define __TEST_SUITES_H__
-
-struct cmd_tbl;
-struct unit_test;
-struct unit_test_state;
-
-/* 'command' functions normally called do_xxx where xxx is the command name */
-typedef int (*ut_cmd_func)(struct unit_test_state *uts, struct cmd_tbl *cmd,
-			   int flags, int argc, char *const argv[]);
-
-/**
- * cmd_ut_category() - Run a category of unit tests
- *
- * @uts: Unit-test state, which must be ready for use, i.e. ut_init_state()
- *	has been called. The caller is responsible for calling
- *	ut_uninit_state() after this function returns
- * @name:	Category name
- * @prefix:	Prefix of test name
- * @tests:	List of tests to run
- * @n_ents:	Number of tests in @tests
- * @argc:	Argument count provided. Must be >= 1. If this is 1 then all
- *		tests are run, otherwise only the one named @argv[1] is run.
- * @argv:	Arguments: argv[1] is the test to run (if @argc >= 2)
- * Return: 0 if OK, CMD_RET_FAILURE on failure
- */
-int cmd_ut_category(struct unit_test_state *uts, const char *name,
-		    const char *prefix, struct unit_test *tests, int n_ents,
-		    int argc, char *const argv[]);
-
-int do_ut_bootstd(struct unit_test_state *uts, struct cmd_tbl *cmdtp, int flag,
-		  int argc, char *const argv[]);
-int do_ut_optee(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]);
-int do_ut_overlay(struct unit_test_state *uts, struct cmd_tbl *cmdtp, int flag,
-		  int argc, char *const argv[]);
-
-#endif /* __TEST_SUITES_H__ */
diff --git a/include/test/test.h b/include/test/test.h
index bac43c81d63..0f2b68a5dee 100644
--- a/include/test/test.h
+++ b/include/test/test.h
@@ -16,11 +16,15 @@
  * @skip_count: Number of tests that were skipped
  * @test_count: Number of tests run. If a test is run muiltiple times, only one
  *	is counted
+ * @start: Timer value when test started
+ * @duration_ms: Suite duration in milliseconds
  */
 struct ut_stats {
 	int fail_count;
 	int skip_count;
 	int test_count;
+	ulong start;
+	ulong duration_ms;
 };
 
 /*
@@ -29,6 +33,8 @@ struct ut_stats {
  * @cur: Statistics for the current run
  * @total: Statistics for all test runs
  * @run_count: Number of times ut_run_list() has been called
+ * @worst: Sute which had the first per-text run time
+ * @worst_ms: Time taken by that test
  * @start: Store the starting mallinfo when doing leak test
  * @of_live: true to use livetree if available, false to use flattree
  * @of_root: Record of the livetree root node (used for setting up tests)
@@ -52,6 +58,8 @@ struct unit_test_state {
 	struct ut_stats cur;
 	struct ut_stats total;
 	int run_count;
+	const struct suite *worst;
+	int worst_ms;
 	struct mallinfo start;
 	struct device_node *of_root;
 	bool of_live;
@@ -92,6 +100,8 @@ enum ut_flags {
 	UTF_ETH_BOOTDEV	= BIT(9),	/* enable Ethernet bootdevs */
 	UTF_SF_BOOTDEV	= BIT(10),	/* enable SPI flash bootdevs */
 	UFT_BLOBLIST	= BIT(11),	/* test changes gd->bloblist */
+	UTF_INIT	= BIT(12),	/* test inits a suite */
+	UTF_UNINIT	= BIT(13),	/* test uninits a suite */
 };
 
 /**
@@ -139,6 +149,24 @@ struct unit_test {
 		.func = _name,						\
 	}
 
+/* init function for unit-test suite (the 'A' makes it first) */
+#define UNIT_TEST_INIT(_name, _flags, _suite)				\
+	ll_entry_declare(struct unit_test, A ## _name, ut_ ## _suite) = {	\
+		.file = __FILE__,					\
+		.name = #_name,						\
+		.flags = (_flags) | UTF_INIT,				\
+		.func = _name,						\
+	}
+
+/* uninit function for unit-test suite (the 'aaa' makes it last) */
+#define UNIT_TEST_UNINIT(_name, _flags, _suite)				\
+	ll_entry_declare(struct unit_test, zzz ## _name, ut_ ## _suite) = { \
+		.file = __FILE__,					\
+		.name = #_name,						\
+		.flags = (_flags) | UTF_UNINIT,				\
+		.func = _name,						\
+	}
+
 /* Get the start of a list of unit tests for a particular suite */
 #define UNIT_TEST_SUITE_START(_suite) \
 	ll_entry_start(struct unit_test, ut_ ## _suite)
diff --git a/include/time.h b/include/time.h
index 3b2ba091247..f5b86bf70fe 100644
--- a/include/time.h
+++ b/include/time.h
@@ -28,7 +28,7 @@ uint64_t get_timer_us(uint64_t base);
  */
 unsigned long get_timer_us_long(unsigned long base);
 
-/*
+/**
  * timer_test_add_offset()
  *
  * Allow tests to add to the time reported through lib/time.c functions
@@ -36,6 +36,19 @@ unsigned long get_timer_us_long(unsigned long base);
  */
 void timer_test_add_offset(unsigned long offset);
 
+#ifdef CONFIG_SANDBOX
+/**
+ * timer_test_get_offset()
+ *
+ * Get the total offset currently being added the time
+ *
+ * Return:: number of milliseconds the system time has been advanced
+ */
+ulong timer_test_get_offset(void);
+#else
+static inline ulong timer_test_get_offset(void) { return 0; }
+#endif
+
 /**
  * usec_to_tick() - convert microseconds to clock ticks
  *
diff --git a/include/video_bridge.h b/include/video_bridge.h
index 3b429eac578..00e9804565c 100644
--- a/include/video_bridge.h
+++ b/include/video_bridge.h
@@ -54,6 +54,19 @@ struct video_bridge_ops {
 	int (*set_backlight)(struct udevice *dev, int percent);
 
 	/**
+	 * get_display_timing() - Get display timings from bridge.
+	 *
+	 * @dev:	Bridge device containing the linked display timings
+	 * @tim:	Place to put timings
+	 * @return 0 if OK, -ve on error
+	 *
+	 * This call it totally optional and useful mainly for integrated
+	 * bridges with fixed output device.
+	 */
+	int (*get_display_timing)(struct udevice *dev,
+				  struct display_timing *timing);
+
+	/**
 	 * read_edid() - Read information from EDID
 	 *
 	 * @dev:	Device to read from
@@ -67,6 +80,7 @@ struct video_bridge_ops {
 #define video_bridge_get_ops(dev) \
 		((struct video_bridge_ops *)(dev)->driver->ops)
 
+#if CONFIG_IS_ENABLED(VIDEO_BRIDGE)
 /**
  * video_bridge_attach() - attach a video bridge
  *
@@ -99,6 +113,14 @@ int video_bridge_set_active(struct udevice *dev, bool active);
 int video_bridge_check_attached(struct udevice *dev);
 
 /**
+ * video_bridge_get_display_timing() - Get display timings from bridge.
+ *
+ * @dev:	Bridge device containing the linked display timings
+ * Return: 0 if OK, -ve on error
+ */
+int video_bridge_get_display_timing(struct udevice *dev,
+				    struct display_timing *timing);
+/**
  * video_bridge_read_edid() - Read information from EDID
  *
  * @dev:	Device to read from
@@ -107,5 +129,37 @@ int video_bridge_check_attached(struct udevice *dev);
  * Return: number of bytes read, <=0 for error
  */
 int video_bridge_read_edid(struct udevice *dev, u8 *buf, int buf_size);
+#else
+static inline int video_bridge_attach(struct udevice *dev)
+{
+	return -ENOSYS;
+}
+
+static inline int video_bridge_set_backlight(struct udevice *dev, int percent)
+{
+	return -ENOSYS;
+}
+
+static inline int video_bridge_set_active(struct udevice *dev, bool active)
+{
+	return -ENOSYS;
+}
+
+static inline int video_bridge_check_attached(struct udevice *dev)
+{
+	return -ENOSYS;
+}
+
+static inline int video_bridge_get_display_timing(struct udevice *dev,
+						  struct display_timing *timing)
+{
+	return -ENOSYS;
+}
+
+static inline int video_bridge_read_edid(struct udevice *dev, u8 *buf, int buf_size)
+{
+	return -ENOSYS;
+}
+#endif /* CONFIG_VIDEO_BRIDGE */
 
 #endif
diff --git a/lib/Kconfig b/lib/Kconfig
index 1a683dea670..17954461114 100644
--- a/lib/Kconfig
+++ b/lib/Kconfig
@@ -445,7 +445,9 @@ config CIRCBUF
 source "lib/dhry/Kconfig"
 
 menu "Alternative crypto libraries"
-source lib/mbedtls/Kconfig
+
+source "lib/mbedtls/Kconfig"
+
 endmenu
 
 menu "Security support"
@@ -1008,14 +1010,14 @@ config OF_LIBFDT_OVERLAY
 	  This enables the FDT library (libfdt) overlay support.
 
 config SYS_FDT_PAD
-	hex "Maximum size of the FDT memory area passeed to the OS"
+	hex "Free space added to device-tree before booting"
 	depends on OF_LIBFDT
 	default 0x13000 if FMAN_ENET || QE || U_QE
 	default 0x3000
 	help
-	  During OS boot, we allocate a region of memory within the bootmap
-	  for the FDT. This is the size that we will expand the FDT that we
-	  are using will be extended to be, in bytes.
+	  The operating system may need a free area at the end of the device-
+	  tree for fix-ups. This setting defines by how many bytes U-Boot
+	  extends the device-tree before booting.
 
 config SPL_OF_LIBFDT
 	bool "Enable the FDT library for SPL"
diff --git a/lib/Makefile b/lib/Makefile
index a7bc2f3134a..41de2671cc6 100644
--- a/lib/Makefile
+++ b/lib/Makefile
@@ -28,11 +28,7 @@ obj-y += charset.o
 endif
 endif
 
-ifdef CONFIG_USB_TTY
-obj-y += circbuf.o
-else
 obj-$(CONFIG_CIRCBUF) += circbuf.o
-endif
 
 obj-y += crc8.o
 obj-$(CONFIG_ERRNO_STR) += errno_str.o
@@ -129,7 +125,7 @@ obj-y += hang.o
 obj-y += linux_compat.o
 obj-y += linux_string.o
 obj-$(CONFIG_$(PHASE_)LMB) += lmb.o
-obj-y += membuff.o
+obj-y += membuf.o
 obj-$(CONFIG_REGEX) += slre.o
 obj-y += string.o
 obj-y += tables_csum.o
diff --git a/lib/acpi/acpi_table.c b/lib/acpi/acpi_table.c
index c0ed24984af..12215f5d90a 100644
--- a/lib/acpi/acpi_table.c
+++ b/lib/acpi/acpi_table.c
@@ -66,6 +66,7 @@ int acpi_create_dmar(struct acpi_dmar *dmar, enum dmar_flags flags)
 
 	dmar->host_address_width = info.address_width - 1;
 	dmar->flags = flags;
+	header->checksum = table_compute_checksum(dmar, header->length);
 
 	return 0;
 }
@@ -255,8 +256,8 @@ int acpi_write_fadt(struct acpi_ctx *ctx, const struct acpi_writer *entry)
 	header->creator_revision = 1;
 	fadt->minor_revision = 2;
 
-	fadt->x_firmware_ctrl = map_to_sysmem(ctx->facs);
-	fadt->x_dsdt = map_to_sysmem(ctx->dsdt);
+	fadt->x_firmware_ctrl = nomap_to_sysmem(ctx->facs);
+	fadt->x_dsdt = nomap_to_sysmem(ctx->dsdt);
 
 	if (fadt->x_firmware_ctrl < 0x100000000ULL)
 		fadt->firmware_ctrl = fadt->x_firmware_ctrl;
@@ -615,6 +616,7 @@ int acpi_iort_add_named_component(struct acpi_ctx *ctx,
 	node->length += strlen(device_name) + 1;
 
 	comp = (struct acpi_iort_named_component *)node->node_data;
+	memset(comp, '\0', sizeof(struct acpi_iort_named_component));
 
 	comp->node_flags = node_flags;
 	comp->memory_properties = memory_properties;
@@ -635,6 +637,7 @@ int acpi_iort_add_rc(struct acpi_ctx *ctx,
 		     const struct acpi_iort_id_mapping *map)
 {
 	struct acpi_iort_id_mapping *mapping;
+	struct acpi_iort_node *output_node;
 	struct acpi_iort_node *node;
 	struct acpi_iort_rc *rc;
 	int offset;
@@ -646,12 +649,18 @@ int acpi_iort_add_rc(struct acpi_ctx *ctx,
 
 	node->type = ACPI_IORT_NODE_PCI_ROOT_COMPLEX;
 	node->revision = 2;
+	node->mapping_count = num_mappings;
+	if (num_mappings)
+		node->mapping_offset = sizeof(struct acpi_iort_node) +
+				       sizeof(struct acpi_iort_rc);
 
 	node->length = sizeof(struct acpi_iort_node);
 	node->length += sizeof(struct acpi_iort_rc);
 	node->length += sizeof(struct acpi_iort_id_mapping) * num_mappings;
 
 	rc = (struct acpi_iort_rc *)node->node_data;
+	memset(rc, '\0', sizeof(struct acpi_iort_rc));
+
 	rc->mem_access_properties = mem_access_properties;
 	rc->ats_attributes = ats_attributes;
 	rc->pci_segment_number = pci_segment_number;
@@ -659,6 +668,13 @@ int acpi_iort_add_rc(struct acpi_ctx *ctx,
 
 	mapping = (struct acpi_iort_id_mapping *)(rc + 1);
 	for (int i = 0; i < num_mappings; i++) {
+		/* Validate input */
+		output_node = (struct acpi_iort_node *)ctx->tab_start + map[i].output_reference;
+		/* ID mappings can use SMMUs or ITS groups as output references */
+		assert(output_node && ((output_node->type == ACPI_IORT_NODE_ITS_GROUP) ||
+				       (output_node->type == ACPI_IORT_NODE_SMMU) ||
+				       (output_node->type == ACPI_IORT_NODE_SMMU_V3)));
+
 		memcpy(mapping, &map[i], sizeof(struct acpi_iort_id_mapping));
 		mapping++;
 	}
@@ -683,6 +699,7 @@ int acpi_iort_add_smmu_v3(struct acpi_ctx *ctx,
 			  const struct acpi_iort_id_mapping *map)
 {
 	struct acpi_iort_node *node;
+	struct acpi_iort_node *output_node;
 	struct acpi_iort_smmu_v3 *smmu;
 	struct acpi_iort_id_mapping *mapping;
 	int offset;
@@ -695,13 +712,16 @@ int acpi_iort_add_smmu_v3(struct acpi_ctx *ctx,
 	node->type = ACPI_IORT_NODE_SMMU_V3;
 	node->revision = 5;
 	node->mapping_count = num_mappings;
-	node->mapping_offset = sizeof(struct acpi_iort_node) + sizeof(struct acpi_iort_smmu_v3);
+	if (num_mappings)
+		node->mapping_offset = sizeof(struct acpi_iort_node) +
+				       sizeof(struct acpi_iort_smmu_v3);
 
 	node->length = sizeof(struct acpi_iort_node);
 	node->length += sizeof(struct acpi_iort_smmu_v3);
 	node->length += sizeof(struct acpi_iort_id_mapping) * num_mappings;
 
 	smmu = (struct acpi_iort_smmu_v3 *)node->node_data;
+	memset(smmu, '\0', sizeof(struct acpi_iort_smmu_v3));
 
 	smmu->base_address = base_address;
 	smmu->flags = flags;
@@ -716,6 +736,14 @@ int acpi_iort_add_smmu_v3(struct acpi_ctx *ctx,
 
 	mapping = (struct acpi_iort_id_mapping *)(smmu + 1);
 	for (int i = 0; i < num_mappings; i++) {
+		/* Validate input */
+		output_node = (struct acpi_iort_node *)ctx->tab_start + map[i].output_reference;
+		/*
+		 * ID mappings of an SMMUv3 node can only have ITS group nodes
+		 * as output references.
+		 */
+		assert(output_node && output_node->type == ACPI_IORT_NODE_ITS_GROUP);
+
 		memcpy(mapping, &map[i], sizeof(struct acpi_iort_id_mapping));
 		mapping++;
 	}
diff --git a/lib/ecdsa/ecdsa-libcrypto.c b/lib/ecdsa/ecdsa-libcrypto.c
index 1c5dde60691..f0095e9dbcf 100644
--- a/lib/ecdsa/ecdsa-libcrypto.c
+++ b/lib/ecdsa/ecdsa-libcrypto.c
@@ -363,8 +363,10 @@ int ecdsa_add_verify_data(struct image_sign_info *info, void *fdt)
 	ret = prepare_ctx(&ctx, info);
 	if (ret >= 0) {
 		ret = do_add(&ctx, fdt, fdt_key_name, info);
-		if (ret < 0)
-			ret = ret == -FDT_ERR_NOSPACE ? -ENOSPC : -EIO;
+		if (ret < 0) {
+			free_ctx(&ctx);
+			return ret == -FDT_ERR_NOSPACE ? -ENOSPC : -EIO;
+		}
 	}
 
 	free_ctx(&ctx);
diff --git a/lib/efi_loader/Kconfig b/lib/efi_loader/Kconfig
index d4f6b56afaa..6130af14337 100644
--- a/lib/efi_loader/Kconfig
+++ b/lib/efi_loader/Kconfig
@@ -27,6 +27,7 @@ config EFI_LOADER
 	select REGEX
 	imply FAT
 	imply FAT_WRITE
+	imply FAT_RENAME
 	imply USB_KEYBOARD_FN_KEYS
 	imply VIDEO_ANSI
 	help
diff --git a/lib/efi_loader/efi_bootbin.c b/lib/efi_loader/efi_bootbin.c
index 10ec5e9ada3..deafb2ce1c2 100644
--- a/lib/efi_loader/efi_bootbin.c
+++ b/lib/efi_loader/efi_bootbin.c
@@ -16,6 +16,7 @@
 #include <log.h>
 #include <malloc.h>
 #include <mapmem.h>
+#include <net.h>
 
 static struct efi_device_path *bootefi_image_path;
 static struct efi_device_path *bootefi_device_path;
@@ -67,7 +68,7 @@ static efi_status_t calculate_paths(const char *dev, const char *devnr,
 
 #if IS_ENABLED(CONFIG_NETDEVICES)
 	if (!strcmp(dev, "Net") || !strcmp(dev, "Http")) {
-		ret = efi_net_set_dp(dev, devnr);
+		ret = efi_net_new_dp(dev, devnr, eth_get_dev());
 		if (ret != EFI_SUCCESS)
 			return ret;
 	}
diff --git a/lib/efi_loader/efi_bootmgr.c b/lib/efi_loader/efi_bootmgr.c
index c6124c590d9..f9534ef85ed 100644
--- a/lib/efi_loader/efi_bootmgr.c
+++ b/lib/efi_loader/efi_bootmgr.c
@@ -18,6 +18,8 @@
 #include <efi_loader.h>
 #include <efi_variable.h>
 #include <asm/unaligned.h>
+#include <linux/kernel.h>
+#include <linux/sizes.h>
 
 static const struct efi_boot_services *bs;
 static const struct efi_runtime_services *rs;
@@ -348,6 +350,7 @@ static efi_status_t prepare_loaded_image(u16 *label, ulong addr, ulong size,
 					 struct efi_device_path **dp,
 					 struct udevice **blk)
 {
+	u64 pages;
 	efi_status_t ret;
 	struct udevice *ramdisk_blk;
 
@@ -362,13 +365,18 @@ static efi_status_t prepare_loaded_image(u16 *label, ulong addr, ulong size,
 	}
 
 	/*
-	 * TODO: expose the ramdisk to OS.
-	 * Need to pass the ramdisk information by the architecture-specific
-	 * methods such as 'pmem' device-tree node.
+	 * Linux supports 'pmem' which allows OS installers to find, reclaim
+	 * the mounted images and continue the installation since the contents
+	 * of the pmem region are treated as local media.
+	 *
+	 * The memory regions used for it needs to be carved out of the EFI
+	 * memory map.
 	 */
-	ret = efi_add_memory_map(addr, size, EFI_RESERVED_MEMORY_TYPE);
+	pages = efi_size_in_pages(size + (addr & EFI_PAGE_MASK));
+	ret = efi_update_memory_map(addr, pages, EFI_CONVENTIONAL_MEMORY,
+				    false, true);
 	if (ret != EFI_SUCCESS) {
-		log_err("Memory reservation failed\n");
+		log_err("Failed to reserve memory\n");
 		goto err;
 	}
 
@@ -490,6 +498,13 @@ static efi_status_t try_load_from_uri_path(struct efi_device_path_uri *uridp,
 		ret = EFI_INVALID_PARAMETER;
 		goto err;
 	}
+	/*
+	 * Depending on the kernel configuration, pmem memory areas must be
+	 * page aligned or 2MiB aligned. PowerPC is an exception here and
+	 * requires 16MiB alignment, but since we don't have EFI support for
+	 * it, limit the alignment to 2MiB.
+	 */
+	image_size = ALIGN(image_size, SZ_2M);
 
 	/*
 	 * If the file extension is ".iso" or ".img", mount it and try to load
diff --git a/lib/efi_loader/efi_boottime.c b/lib/efi_loader/efi_boottime.c
index eaa6464fa39..f220daa048f 100644
--- a/lib/efi_loader/efi_boottime.c
+++ b/lib/efi_loader/efi_boottime.c
@@ -22,7 +22,6 @@
 #include <usb.h>
 #include <watchdog.h>
 #include <asm/global_data.h>
-#include <asm/setjmp.h>
 #include <linux/libfdt_env.h>
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -61,9 +60,9 @@ static efi_handle_t current_image;
 static volatile gd_t *efi_gd, *app_gd;
 #endif
 
-static efi_status_t efi_uninstall_protocol
-			(efi_handle_t handle, const efi_guid_t *protocol,
-			 void *protocol_interface, bool preserve);
+efi_status_t efi_uninstall_protocol
+		(efi_handle_t handle, const efi_guid_t *protocol,
+		 void *protocol_interface, bool preserve);
 
 /* 1 if inside U-Boot code, 0 if inside EFI payload code */
 static int entry_count = 1;
@@ -101,12 +100,11 @@ const efi_guid_t efi_guid_load_file2_protocol = EFI_LOAD_FILE2_PROTOCOL_GUID;
 /* GUID of the SMBIOS table */
 const efi_guid_t smbios_guid = SMBIOS_TABLE_GUID;
 
-static efi_status_t EFIAPI efi_disconnect_controller(
+efi_status_t EFIAPI efi_disconnect_controller(
 					efi_handle_t controller_handle,
 					efi_handle_t driver_image_handle,
 					efi_handle_t child_handle);
 
-static
 efi_status_t EFIAPI efi_connect_controller(efi_handle_t controller_handle,
 					   efi_handle_t *driver_image_handle,
 					   struct efi_device_path *remain_device_path,
@@ -1040,7 +1038,7 @@ static efi_status_t EFIAPI efi_signal_event_ext(struct efi_event *event)
  *
  * Return: status code
  */
-static efi_status_t EFIAPI efi_close_event(struct efi_event *event)
+efi_status_t EFIAPI efi_close_event(struct efi_event *event)
 {
 	struct efi_register_notify_event *item, *next;
 
@@ -1381,9 +1379,9 @@ static efi_status_t efi_disconnect_all_drivers
  *
  * Return: status code
  */
-static efi_status_t efi_uninstall_protocol
-			(efi_handle_t handle, const efi_guid_t *protocol,
-			 void *protocol_interface, bool preserve)
+efi_status_t efi_uninstall_protocol
+		(efi_handle_t handle, const efi_guid_t *protocol,
+			void *protocol_interface, bool preserve)
 {
 	struct efi_handler *handler;
 	struct efi_open_protocol_info_item *item;
@@ -2234,8 +2232,6 @@ static efi_status_t EFIAPI efi_exit_boot_services(efi_handle_t image_handle,
 
 	if (!efi_st_keep_devices) {
 		bootm_disable_interrupts();
-		if (IS_ENABLED(CONFIG_USB_DEVICE))
-			udc_disconnect();
 		if (IS_ENABLED(CONFIG_DM_ETH))
 			eth_halt();
 		board_quiesce_devices();
@@ -3202,7 +3198,7 @@ efi_status_t EFIAPI efi_start_image(efi_handle_t image_handle,
 	void *info;
 	efi_handle_t parent_image = current_image;
 	efi_status_t exit_status;
-	struct jmp_buf_data exit_jmp;
+	jmp_buf exit_jmp;
 
 	EFI_ENTRY("%p, %p, %p", image_handle, exit_data_size, exit_data);
 
@@ -3241,7 +3237,7 @@ efi_status_t EFIAPI efi_start_image(efi_handle_t image_handle,
 	}
 
 	/* call the image! */
-	if (setjmp(&exit_jmp)) {
+	if (setjmp(exit_jmp)) {
 		/*
 		 * We called the entry point of the child image with EFI_CALL
 		 * in the lines below. The child image called the Exit() boot
@@ -3447,7 +3443,7 @@ static efi_status_t EFIAPI efi_exit(efi_handle_t image_handle,
 	struct efi_loaded_image *loaded_image_protocol;
 	struct efi_loaded_image_obj *image_obj =
 		(struct efi_loaded_image_obj *)image_handle;
-	struct jmp_buf_data *exit_jmp;
+	jmp_buf *exit_jmp;
 
 	EFI_ENTRY("%p, %ld, %zu, %p", image_handle, exit_status,
 		  exit_data_size, exit_data);
@@ -3514,7 +3510,7 @@ static efi_status_t EFIAPI efi_exit(efi_handle_t image_handle,
 	 */
 	efi_restore_gd();
 
-	longjmp(exit_jmp, 1);
+	longjmp(*exit_jmp, 1);
 
 	panic("EFI application exited");
 out:
@@ -3668,7 +3664,7 @@ static efi_status_t efi_connect_single_controller(
  *
  * Return: status code
  */
-static efi_status_t EFIAPI efi_connect_controller(
+efi_status_t EFIAPI efi_connect_controller(
 			efi_handle_t controller_handle,
 			efi_handle_t *driver_image_handle,
 			struct efi_device_path *remain_device_path,
@@ -3847,7 +3843,7 @@ static efi_status_t efi_get_child_controllers(
  *
  * Return: status code
  */
-static efi_status_t EFIAPI efi_disconnect_controller(
+efi_status_t EFIAPI efi_disconnect_controller(
 				efi_handle_t controller_handle,
 				efi_handle_t driver_image_handle,
 				efi_handle_t child_handle)
diff --git a/lib/efi_loader/efi_device_path.c b/lib/efi_loader/efi_device_path.c
index c0633a736b6..c9bf2726fe2 100644
--- a/lib/efi_loader/efi_device_path.c
+++ b/lib/efi_loader/efi_device_path.c
@@ -954,20 +954,20 @@ struct efi_device_path *efi_dp_from_uart(void)
 	return buf;
 }
 
-struct efi_device_path __maybe_unused *efi_dp_from_eth(void)
+struct efi_device_path __maybe_unused *efi_dp_from_eth(struct udevice *dev)
 {
 	void *buf, *start;
 	unsigned dpsize = 0;
 
-	assert(eth_get_dev());
+	assert(dev);
 
-	dpsize += dp_size(eth_get_dev());
+	dpsize += dp_size(dev);
 
 	start = buf = efi_alloc(dpsize + sizeof(END));
 	if (!buf)
 		return NULL;
 
-	buf = dp_fill(buf, eth_get_dev());
+	buf = dp_fill(buf, dev);
 
 	*((struct efi_device_path *)buf) = END;
 
@@ -984,11 +984,13 @@ struct efi_device_path __maybe_unused *efi_dp_from_eth(void)
  * @ip:		IPv4 local address
  * @mask:	network mask
  * @srv:	IPv4 remote/server address
+ * @dev:	net udevice
  * Return:	pointer to device path, NULL on error
  */
 static struct efi_device_path *efi_dp_from_ipv4(struct efi_ipv4_address *ip,
 					 struct efi_ipv4_address *mask,
-					 struct efi_ipv4_address *srv)
+					 struct efi_ipv4_address *srv,
+					 struct udevice *dev)
 {
 	struct efi_device_path *dp1, *dp2, *pos;
 	struct {
@@ -1010,7 +1012,7 @@ static struct efi_device_path *efi_dp_from_ipv4(struct efi_ipv4_address *ip,
 	pos = &dp.end;
 	memcpy(pos, &END, sizeof(END));
 
-	dp1 = efi_dp_from_eth();
+	dp1 = efi_dp_from_eth(dev);
 	if (!dp1)
 		return NULL;
 
@@ -1029,9 +1031,10 @@ static struct efi_device_path *efi_dp_from_ipv4(struct efi_ipv4_address *ip,
  * and an END node.
  *
  * @server:	URI of remote server
+ * @dev:	net udevice
  * Return:	pointer to HTTP device path, NULL on error
  */
-struct efi_device_path *efi_dp_from_http(const char *server)
+struct efi_device_path *efi_dp_from_http(const char *server, struct udevice *dev)
 {
 	struct efi_device_path *dp1, *dp2;
 	struct efi_device_path_uri *uridp;
@@ -1045,12 +1048,13 @@ struct efi_device_path *efi_dp_from_http(const char *server)
 	    (!server && IS_ENABLED(CONFIG_NET_LWIP)))
 		return NULL;
 
-	efi_net_get_addr(&ip, &mask, NULL);
+	efi_net_get_addr(&ip, &mask, NULL, dev);
 
-	dp1 = efi_dp_from_ipv4(&ip, &mask, NULL);
+	dp1 = efi_dp_from_ipv4(&ip, &mask, NULL, dev);
 	if (!dp1)
 		return NULL;
 
+
 	strcpy(tmp, "http://");
 
 	if (server) {
@@ -1185,8 +1189,8 @@ efi_status_t efi_dp_from_name(const char *dev, const char *devnr,
 		dp = efi_dp_from_mem(EFI_RESERVED_MEMORY_TYPE,
 				     (uintptr_t)image_addr, image_size);
 	} else if (IS_ENABLED(CONFIG_NETDEVICES) &&
-		   (!strcmp(dev, "Net") || !strcmp(dev, "Http"))) {
-		efi_net_get_dp(&dp);
+	           (!strcmp(dev, "Net") || !strcmp(dev, "Http"))) {
+		efi_net_dp_from_dev(&dp, eth_get_dev(), false);
 	} else if (!strcmp(dev, "Uart")) {
 		dp = efi_dp_from_uart();
 	} else {
diff --git a/lib/efi_loader/efi_file.c b/lib/efi_loader/efi_file.c
index 201fa5f8f3c..7d81da8f2d8 100644
--- a/lib/efi_loader/efi_file.c
+++ b/lib/efi_loader/efi_file.c
@@ -40,7 +40,7 @@ struct file_handle {
 	struct fs_dir_stream *dirs;
 	struct fs_dirent *dent;
 
-	char path[0];
+	char *path;
 };
 #define to_fh(x) container_of(x, struct file_handle, base)
 
@@ -178,6 +178,7 @@ static struct efi_file_handle *file_open(struct file_system *fs,
 		u64 attributes)
 {
 	struct file_handle *fh;
+	char *path;
 	char f0[MAX_UTF8_PER_UTF16] = {0};
 	int plen = 0;
 	int flen = 0;
@@ -194,11 +195,13 @@ static struct efi_file_handle *file_open(struct file_system *fs,
 		plen = strlen(parent->path) + 1;
 	}
 
+	fh = calloc(1, sizeof(*fh));
 	/* +2 is for null and '/' */
-	fh = calloc(1, sizeof(*fh) + plen + (flen * MAX_UTF8_PER_UTF16) + 2);
-	if (!fh)
-		return NULL;
+	path = calloc(1, plen + (flen * MAX_UTF8_PER_UTF16) + 2);
+	if (!fh || !path)
+		goto error;
 
+	fh->path = path;
 	fh->open_mode = open_mode;
 	fh->base = efi_file_handle_protocol;
 	fh->fs = fs;
@@ -245,6 +248,7 @@ static struct efi_file_handle *file_open(struct file_system *fs,
 	return &fh->base;
 
 error:
+	free(fh->path);
 	free(fh);
 	return NULL;
 }
@@ -368,6 +372,7 @@ out:
 static efi_status_t file_close(struct file_handle *fh)
 {
 	fs_closedir(fh->dirs);
+	free(fh->path);
 	free(fh);
 	return EFI_SUCCESS;
 }
@@ -949,6 +954,7 @@ static efi_status_t EFIAPI efi_file_setinfo(struct efi_file_handle *file,
 {
 	struct file_handle *fh = to_fh(file);
 	efi_status_t ret = EFI_UNSUPPORTED;
+	char *new_file_name = NULL, *new_path = NULL;
 
 	EFI_ENTRY("%p, %pUs, %zu, %p", file, info_type, buffer_size, buffer);
 
@@ -978,13 +984,43 @@ static efi_status_t EFIAPI efi_file_setinfo(struct efi_file_handle *file,
 		pos = new_file_name;
 		utf16_utf8_strcpy(&pos, info->file_name);
 		if (strcmp(new_file_name, filename)) {
-			/* TODO: we do not support renaming */
-			EFI_PRINT("Renaming not supported\n");
-			free(new_file_name);
-			ret = EFI_ACCESS_DENIED;
-			goto out;
+			int dlen;
+			int rv;
+
+			if (set_blk_dev(fh)) {
+				ret = EFI_DEVICE_ERROR;
+				goto out;
+			}
+			dlen = filename - fh->path;
+			new_path = calloc(1, dlen + strlen(new_file_name) + 1);
+			if (!new_path) {
+				ret = EFI_OUT_OF_RESOURCES;
+				goto out;
+			}
+			memcpy(new_path, fh->path, dlen);
+			strcpy(new_path + dlen, new_file_name);
+			sanitize_path(new_path);
+			rv = fs_exists(new_path);
+			if (rv) {
+				ret = EFI_ACCESS_DENIED;
+				goto out;
+			}
+			/* fs_exists() calls fs_close(), so open file system again */
+			if (set_blk_dev(fh)) {
+				ret = EFI_DEVICE_ERROR;
+				goto out;
+			}
+			rv = fs_rename(fh->path, new_path);
+			if (rv) {
+				ret = EFI_ACCESS_DENIED;
+				goto out;
+			}
+			free(fh->path);
+			fh->path = new_path;
+			/* Prevent new_path from being freed on out */
+			new_path = NULL;
+			ret = EFI_SUCCESS;
 		}
-		free(new_file_name);
 		/* Check for truncation */
 		if (!fh->isdir) {
 			ret = efi_get_file_size(fh, &file_size);
@@ -1007,6 +1043,8 @@ static efi_status_t EFIAPI efi_file_setinfo(struct efi_file_handle *file,
 		ret = EFI_UNSUPPORTED;
 	}
 out:
+	free(new_path);
+	free(new_file_name);
 	return EFI_EXIT(ret);
 }
 
diff --git a/lib/efi_loader/efi_helper.c b/lib/efi_loader/efi_helper.c
index 04b2efc4a3b..8c32059edda 100644
--- a/lib/efi_loader/efi_helper.c
+++ b/lib/efi_loader/efi_helper.c
@@ -5,6 +5,7 @@
 
 #define LOG_CATEGORY LOGC_EFI
 
+#include <blkmap.h>
 #include <bootm.h>
 #include <env.h>
 #include <image.h>
@@ -454,22 +455,29 @@ efi_status_t efi_env_set_load_options(efi_handle_t handle,
  */
 static efi_status_t copy_fdt(void **fdtp)
 {
-	unsigned long fdt_ram_start = -1L, fdt_pages;
 	efi_status_t ret = 0;
 	void *fdt, *new_fdt;
-	u64 new_fdt_addr;
-	uint fdt_size;
-	int i;
+	static u64 new_fdt_addr;
+	static efi_uintn_t fdt_pages;
+	ulong fdt_size;
 
-	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
-		u64 ram_start = gd->bd->bi_dram[i].start;
-		u64 ram_size = gd->bd->bi_dram[i].size;
+	/*
+	 * Remove the configuration table that might already be
+	 * installed, ignoring EFI_NOT_FOUND if no device-tree
+	 * is installed
+	 */
+	efi_install_configuration_table(&efi_guid_fdt, NULL);
 
-		if (!ram_size)
-			continue;
+	if (new_fdt_addr) {
+		log_debug("%s: Found allocated memory at %#llx, with %#zx pages\n",
+			  __func__, new_fdt_addr, fdt_pages);
 
-		if (ram_start < fdt_ram_start)
-			fdt_ram_start = ram_start;
+		ret = efi_free_pages(new_fdt_addr, fdt_pages);
+		if (ret != EFI_SUCCESS)
+			log_err("Unable to free up existing FDT memory region\n");
+
+		new_fdt_addr = 0;
+		fdt_pages = 0;
 	}
 
 	/*
@@ -485,15 +493,18 @@ static efi_status_t copy_fdt(void **fdtp)
 				 &new_fdt_addr);
 	if (ret != EFI_SUCCESS) {
 		log_err("Failed to reserve space for FDT\n");
-		goto done;
+		return ret;
 	}
+	log_debug("%s: Allocated memory at %#llx, with %#zx pages\n",
+		  __func__, new_fdt_addr, fdt_pages);
+
 	new_fdt = (void *)(uintptr_t)new_fdt_addr;
 	memcpy(new_fdt, fdt, fdt_totalsize(fdt));
 	fdt_set_totalsize(new_fdt, fdt_size);
 
-	*fdtp = (void *)(uintptr_t)new_fdt_addr;
-done:
-	return ret;
+	*fdtp = new_fdt;
+
+	return EFI_SUCCESS;
 }
 
 /**
@@ -546,9 +557,6 @@ efi_status_t efi_install_fdt(void *fdt)
 		const char *fdt_opt;
 		uintptr_t fdt_addr;
 
-		/* Look for device tree that is already installed */
-		if (efi_get_configuration_table(&efi_guid_fdt))
-			return EFI_SUCCESS;
 		/* Check if there is a hardware device tree */
 		fdt_opt = env_get("fdt_addr");
 		/* Use our own device tree as fallback */
@@ -680,3 +688,44 @@ out:
 
 	return ret;
 }
+
+/**
+ * pmem_node_efi_memmap_setup() - Add pmem node and tweak EFI memmap
+ * @fdt: The devicetree to which pmem node is added
+ * @addr: start address of the pmem node
+ * @size: size of the memory of the pmem node
+ *
+ * The function adds the pmem node to the device-tree along with removing
+ * the corresponding region from the EFI memory map. Used primarily to
+ * pass the information of a RAM based ISO image to the OS.
+ *
+ * Return: 0 on success, -ve value on error
+ */
+static int pmem_node_efi_memmap_setup(void *fdt, u64 addr, u64 size)
+{
+	int ret;
+	u64 pages;
+	efi_status_t status;
+
+	ret = fdt_fixup_pmem_region(fdt, addr, size);
+	if (ret) {
+		log_err("Failed to setup pmem node for addr %#llx, size %#llx, err %d\n",
+			addr, size, ret);
+		return ret;
+	}
+
+	/* Remove the pmem region from the EFI memory map */
+	pages = efi_size_in_pages(size + (addr & EFI_PAGE_MASK));
+	status = efi_update_memory_map(addr, pages, EFI_CONVENTIONAL_MEMORY,
+				       false, true);
+	if (status != EFI_SUCCESS)
+		return -1;
+
+	return 0;
+}
+
+int fdt_efi_pmem_setup(void *fdt)
+{
+	return blkmap_get_preserved_pmem_slices(pmem_node_efi_memmap_setup,
+						fdt);
+}
diff --git a/lib/efi_loader/efi_http.c b/lib/efi_loader/efi_http.c
index 88816256b03..189317fe2d2 100644
--- a/lib/efi_loader/efi_http.c
+++ b/lib/efi_loader/efi_http.c
@@ -36,6 +36,7 @@ static const efi_guid_t efi_http_guid = EFI_HTTP_PROTOCOL_GUID;
 struct efi_http_instance {
 	struct efi_http_protocol http;
 	efi_handle_t handle;
+	struct efi_service_binding_protocol *parent;
 	bool configured;
 	void *http_load_addr;
 	ulong file_size;
@@ -188,7 +189,7 @@ static efi_status_t EFIAPI efi_http_configure(struct efi_http_protocol *this,
 
 	if (!ipv4_node->use_default_address) {
 		efi_net_set_addr((struct efi_ipv4_address *)&ipv4_node->local_address,
-				 (struct efi_ipv4_address *)&ipv4_node->local_subnet, NULL);
+				 (struct efi_ipv4_address *)&ipv4_node->local_subnet, NULL, NULL);
 	}
 
 	http_instance->current_offset = 0;
@@ -243,7 +244,7 @@ static efi_status_t EFIAPI efi_http_request(struct efi_http_protocol *this,
 
 	ret = efi_net_do_request(url_8, current_method, &http_instance->http_load_addr,
 				 &http_instance->status_code, &http_instance->file_size,
-				 http_instance->headers_buffer);
+				 http_instance->headers_buffer, http_instance->parent);
 	if (ret != EFI_SUCCESS)
 		goto out;
 
@@ -408,6 +409,7 @@ static efi_status_t EFIAPI efi_http_service_binding_create_child(
 		goto failure_to_add_protocol;
 	}
 
+	new_instance->parent = this;
 	efi_add_handle(new_instance->handle);
 	*child_handle = new_instance->handle;
 
diff --git a/lib/efi_loader/efi_ipconfig.c b/lib/efi_loader/efi_ipconfig.c
index f1c092daafd..9f51f77fa9a 100644
--- a/lib/efi_loader/efi_ipconfig.c
+++ b/lib/efi_loader/efi_ipconfig.c
@@ -60,7 +60,7 @@ static efi_status_t EFIAPI efi_ip4_config2_set_data(struct efi_ip4_config2_proto
 			memcpy((void *)&current_http_ip, data,
 			       sizeof(struct efi_ip4_config2_manual_address));
 			efi_net_set_addr(&current_http_ip.address,
-					 &current_http_ip.subnet_mask, NULL);
+					 &current_http_ip.subnet_mask, NULL, NULL);
 			return EFI_EXIT(EFI_SUCCESS);
 		}
 		return EFI_EXIT(EFI_BAD_BUFFER_SIZE);
@@ -133,7 +133,7 @@ static efi_status_t EFIAPI efi_ip4_config2_get_data(struct efi_ip4_config2_proto
 			return EFI_EXIT(EFI_BUFFER_TOO_SMALL);
 		}
 
-		efi_net_get_addr(&current_http_ip.address, &current_http_ip.subnet_mask, NULL);
+		efi_net_get_addr(&current_http_ip.address, &current_http_ip.subnet_mask, NULL, NULL);
 		memcpy(data, (void *)&current_http_ip,
 		       sizeof(struct efi_ip4_config2_manual_address));
 
diff --git a/lib/efi_loader/efi_memory.c b/lib/efi_loader/efi_memory.c
index c39b53922bb..0abb1f6159a 100644
--- a/lib/efi_loader/efi_memory.c
+++ b/lib/efi_loader/efi_memory.c
@@ -258,7 +258,7 @@ static s64 efi_mem_carve_out(struct efi_mem_list *map,
 }
 
 /**
- * efi_add_memory_map_pg() - add pages to the memory map
+ * efi_update_memory_map() - update the memory map by adding/removing pages
  *
  * @start:			start address, must be a multiple of
  *				EFI_PAGE_SIZE
@@ -266,12 +266,11 @@ static s64 efi_mem_carve_out(struct efi_mem_list *map,
  * @memory_type:		type of memory added
  * @overlap_conventional:	region may only overlap free(conventional)
  *				memory
+ * @remove:			remove memory map
  * Return:			status code
  */
-static
-efi_status_t efi_add_memory_map_pg(u64 start, u64 pages,
-				   int memory_type,
-				   bool overlap_conventional)
+efi_status_t efi_update_memory_map(u64 start, u64 pages, int memory_type,
+				   bool overlap_conventional, bool remove)
 {
 	struct efi_mem_list *lmem;
 	struct efi_mem_list *newlist;
@@ -279,9 +278,9 @@ efi_status_t efi_add_memory_map_pg(u64 start, u64 pages,
 	uint64_t carved_pages = 0;
 	struct efi_event *evt;
 
-	EFI_PRINT("%s: 0x%llx 0x%llx %d %s\n", __func__,
+	EFI_PRINT("%s: 0x%llx 0x%llx %d %s %s\n", __func__,
 		  start, pages, memory_type, overlap_conventional ?
-		  "yes" : "no");
+		  "yes" : "no", remove ? "remove" : "add");
 
 	if (memory_type >= EFI_MAX_MEMORY_TYPE)
 		return EFI_INVALID_PARAMETER;
@@ -364,7 +363,10 @@ efi_status_t efi_add_memory_map_pg(u64 start, u64 pages,
 	}
 
 	/* Add our new map */
-        list_add_tail(&newlist->link, &efi_mem);
+	if (!remove)
+		list_add_tail(&newlist->link, &efi_mem);
+	else
+		free(newlist);
 
 	/* And make sure memory is listed in descending order */
 	efi_mem_sort();
@@ -401,7 +403,7 @@ efi_status_t efi_add_memory_map(u64 start, u64 size, int memory_type)
 	pages = efi_size_in_pages(size + (start & EFI_PAGE_MASK));
 	start &= ~EFI_PAGE_MASK;
 
-	return efi_add_memory_map_pg(start, pages, memory_type, false);
+	return efi_update_memory_map(start, pages, memory_type, false, false);
 }
 
 /**
@@ -501,7 +503,7 @@ efi_status_t efi_allocate_pages(enum efi_allocate_type type,
 
 	efi_addr = (u64)(uintptr_t)map_sysmem(addr, 0);
 	/* Reserve that map in our memory maps */
-	ret = efi_add_memory_map_pg(efi_addr, pages, memory_type, true);
+	ret = efi_update_memory_map(efi_addr, pages, memory_type, true, false);
 	if (ret != EFI_SUCCESS) {
 		/* Map would overlap, bail out */
 		lmb_free_flags(addr, (u64)pages << EFI_PAGE_SHIFT, flags);
@@ -822,8 +824,8 @@ static void add_u_boot_and_runtime(void)
 		       uboot_stack_size) & ~EFI_PAGE_MASK;
 	uboot_pages = ((uintptr_t)map_sysmem(gd->ram_top - 1, 0) -
 		       uboot_start + EFI_PAGE_MASK) >> EFI_PAGE_SHIFT;
-	efi_add_memory_map_pg(uboot_start, uboot_pages, EFI_BOOT_SERVICES_CODE,
-			      false);
+	efi_update_memory_map(uboot_start, uboot_pages, EFI_BOOT_SERVICES_CODE,
+			      false, false);
 #if defined(__aarch64__)
 	/*
 	 * Runtime Services must be 64KiB aligned according to the
@@ -841,8 +843,8 @@ static void add_u_boot_and_runtime(void)
 	runtime_end = (uintptr_t)__efi_runtime_stop;
 	runtime_end = (runtime_end + runtime_mask) & ~runtime_mask;
 	runtime_pages = (runtime_end - runtime_start) >> EFI_PAGE_SHIFT;
-	efi_add_memory_map_pg(runtime_start, runtime_pages,
-			      EFI_RUNTIME_SERVICES_CODE, false);
+	efi_update_memory_map(runtime_start, runtime_pages,
+			      EFI_RUNTIME_SERVICES_CODE, false, false);
 }
 
 int efi_memory_init(void)
@@ -877,11 +879,11 @@ int efi_map_update_notify(phys_addr_t addr, phys_size_t size,
 	pages = efi_size_in_pages(size + (efi_addr & EFI_PAGE_MASK));
 	efi_addr &= ~EFI_PAGE_MASK;
 
-	status = efi_add_memory_map_pg(efi_addr, pages,
+	status = efi_update_memory_map(efi_addr, pages,
 				       op == LMB_MAP_OP_RESERVE ?
 				       EFI_BOOT_SERVICES_DATA :
 				       EFI_CONVENTIONAL_MEMORY,
-				       false);
+				       false, false);
 	if (status != EFI_SUCCESS) {
 		log_err("LMB Map notify failure %lu\n",
 			status & ~EFI_ERROR_MASK);
diff --git a/lib/efi_loader/efi_net.c b/lib/efi_loader/efi_net.c
index 60aa076feaa..b3291b4f1d5 100644
--- a/lib/efi_loader/efi_net.c
+++ b/lib/efi_loader/efi_net.c
@@ -24,54 +24,70 @@
 #include <vsprintf.h>
 #include <net.h>
 
-static const efi_guid_t efi_net_guid = EFI_SIMPLE_NETWORK_PROTOCOL_GUID;
+#define MAX_EFI_NET_OBJS 10
+#define MAX_NUM_DHCP_ENTRIES 10
+#define MAX_NUM_DP_ENTRIES 10
+
+const efi_guid_t efi_net_guid = EFI_SIMPLE_NETWORK_PROTOCOL_GUID;
 static const efi_guid_t efi_pxe_base_code_protocol_guid =
 					EFI_PXE_BASE_CODE_PROTOCOL_GUID;
-static struct efi_pxe_packet *dhcp_ack;
-static void *new_tx_packet;
-static void *transmit_buffer;
-static uchar **receive_buffer;
-static size_t *receive_lengths;
-static int rx_packet_idx;
-static int rx_packet_num;
-static struct efi_net_obj *netobj;
+
+struct dp_entry {
+	struct efi_device_path *net_dp;
+	struct udevice *dev;
+	bool is_valid;
+};
 
 /*
- * The current network device path. This device path is updated when a new
- * bootfile is downloaded from the network. If then the bootfile is loaded
- * as an efi image, net_dp is passed as the device path of the loaded image.
+ * The network device path cache. An entry is added when a new bootfile
+ * is downloaded from the network. If the bootfile is then loaded as an
+ * efi image, the most recent entry corresponding to the device is passed
+ * as the device path of the loaded image.
  */
-static struct efi_device_path *net_dp;
+static struct dp_entry dp_cache[MAX_NUM_DP_ENTRIES];
+static int next_dp_entry;
 
+#if IS_ENABLED(CONFIG_EFI_HTTP_PROTOCOL)
 static struct wget_http_info efi_wget_info = {
 	.set_bootdev = false,
 	.check_buffer_size = true,
 
 };
+#endif
 
-/*
- * The notification function of this event is called in every timer cycle
- * to check if a new network packet has been received.
- */
-static struct efi_event *network_timer_event;
-/*
- * This event is signaled when a packet has been received.
- */
-static struct efi_event *wait_for_packet;
+struct dhcp_entry {
+	struct efi_pxe_packet *dhcp_ack;
+	struct udevice *dev;
+	bool is_valid;
+};
+
+static struct dhcp_entry dhcp_cache[MAX_NUM_DHCP_ENTRIES];
+static int next_dhcp_entry;
 
 /**
  * struct efi_net_obj - EFI object representing a network interface
  *
  * @header:			EFI object header
+ * @dev:			net udevice
  * @net:			simple network protocol interface
  * @net_mode:			status of the network interface
  * @pxe:			PXE base code protocol interface
  * @pxe_mode:			status of the PXE base code protocol
  * @ip4_config2:		IP4 Config2 protocol interface
  * @http_service_binding:	Http service binding protocol interface
+ * @new_tx_packet:		new transmit packet
+ * @transmit_buffer:	transmit buffer
+ * @receive_buffer:		array of receive buffers
+ * @receive_lengths:	array of lengths for received packets
+ * @rx_packet_idx:		index of the current receive packet
+ * @rx_packet_num:		number of received packets
+ * @wait_for_packet:	signaled when a packet has been received
+ * @network_timer_event:	event to check for new network packets.
+ * @efi_seq_num:		sequence number of the EFI net object.
  */
 struct efi_net_obj {
 	struct efi_object header;
+	struct udevice *dev;
 	struct efi_simple_network net;
 	struct efi_simple_network_mode net_mode;
 	struct efi_pxe_base_code_protocol pxe;
@@ -82,8 +98,54 @@ struct efi_net_obj {
 #if IS_ENABLED(CONFIG_EFI_HTTP_PROTOCOL)
 	struct efi_service_binding_protocol http_service_binding;
 #endif
+	void *new_tx_packet;
+	void *transmit_buffer;
+	uchar **receive_buffer;
+	size_t *receive_lengths;
+	int rx_packet_idx;
+	int rx_packet_num;
+	struct efi_event *wait_for_packet;
+	struct efi_event *network_timer_event;
+	int efi_seq_num;
 };
 
+static int curr_efi_net_obj;
+static struct efi_net_obj *net_objs[MAX_EFI_NET_OBJS];
+
+/**
+ * efi_netobj_is_active() - checks if a netobj is active in the efi subsystem
+ *
+ * @netobj:	pointer to efi_net_obj
+ * Return:	true if active
+ */
+static bool efi_netobj_is_active(struct efi_net_obj *netobj)
+{
+	if (!netobj || !efi_search_obj(&netobj->header))
+		return false;
+
+	return true;
+}
+
+/*
+ * efi_netobj_from_snp() - get efi_net_obj from simple network protocol
+ *
+ *
+ * @snp:	pointer to the simple network protocol
+ * Return:	pointer to efi_net_obj, NULL on error
+ */
+static struct efi_net_obj *efi_netobj_from_snp(struct efi_simple_network *snp)
+{
+	int i;
+
+	for (i = 0; i < MAX_EFI_NET_OBJS; i++) {
+		if (net_objs[i] && &net_objs[i]->net == snp) {
+			// Do not register duplicate devices
+			return net_objs[i];
+		}
+	}
+	return NULL;
+}
+
 /*
  * efi_net_start() - start the network interface
  *
@@ -97,20 +159,22 @@ struct efi_net_obj {
 static efi_status_t EFIAPI efi_net_start(struct efi_simple_network *this)
 {
 	efi_status_t ret = EFI_SUCCESS;
+	struct efi_net_obj *nt;
 
 	EFI_ENTRY("%p", this);
-
 	/* Check parameters */
 	if (!this) {
 		ret = EFI_INVALID_PARAMETER;
 		goto out;
 	}
 
+	nt = efi_netobj_from_snp(this);
+
 	if (this->mode->state != EFI_NETWORK_STOPPED) {
 		ret = EFI_ALREADY_STARTED;
 	} else {
 		this->int_status = 0;
-		wait_for_packet->is_signaled = false;
+		nt->wait_for_packet->is_signaled = false;
 		this->mode->state = EFI_NETWORK_STARTED;
 	}
 out:
@@ -130,6 +194,7 @@ out:
 static efi_status_t EFIAPI efi_net_stop(struct efi_simple_network *this)
 {
 	efi_status_t ret = EFI_SUCCESS;
+	struct efi_net_obj *nt;
 
 	EFI_ENTRY("%p", this);
 
@@ -139,13 +204,17 @@ static efi_status_t EFIAPI efi_net_stop(struct efi_simple_network *this)
 		goto out;
 	}
 
+	nt = efi_netobj_from_snp(this);
+
 	if (this->mode->state == EFI_NETWORK_STOPPED) {
 		ret = EFI_NOT_STARTED;
 	} else {
 		/* Disable hardware and put it into the reset state */
+		eth_set_dev(nt->dev);
+		env_set("ethact", eth_get_name());
 		eth_halt();
 		/* Clear cache of packets */
-		rx_packet_num = 0;
+		nt->rx_packet_num = 0;
 		this->mode->state = EFI_NETWORK_STOPPED;
 	}
 out:
@@ -169,6 +238,7 @@ static efi_status_t EFIAPI efi_net_initialize(struct efi_simple_network *this,
 {
 	int ret;
 	efi_status_t r = EFI_SUCCESS;
+	struct efi_net_obj *nt;
 
 	EFI_ENTRY("%p, %lx, %lx", this, extra_rx, extra_tx);
 
@@ -177,6 +247,7 @@ static efi_status_t EFIAPI efi_net_initialize(struct efi_simple_network *this,
 		r = EFI_INVALID_PARAMETER;
 		goto out;
 	}
+	nt = efi_netobj_from_snp(this);
 
 	switch (this->mode->state) {
 	case EFI_NETWORK_INITIALIZED:
@@ -189,14 +260,13 @@ static efi_status_t EFIAPI efi_net_initialize(struct efi_simple_network *this,
 
 	/* Setup packet buffers */
 	net_init();
-	/* Disable hardware and put it into the reset state */
-	eth_halt();
 	/* Clear cache of packets */
-	rx_packet_num = 0;
-	/* Set current device according to environment variables */
-	eth_set_current();
+	nt->rx_packet_num = 0;
+	/* Set the net device corresponding to the efi net object */
+	eth_set_dev(nt->dev);
+	env_set("ethact", eth_get_name());
 	/* Get hardware ready for send and receive operations */
-	ret = eth_init();
+	ret = eth_start_udev(nt->dev);
 	if (ret < 0) {
 		eth_halt();
 		this->mode->state = EFI_NETWORK_STOPPED;
@@ -204,7 +274,7 @@ static efi_status_t EFIAPI efi_net_initialize(struct efi_simple_network *this,
 		goto out;
 	} else {
 		this->int_status = 0;
-		wait_for_packet->is_signaled = false;
+		nt->wait_for_packet->is_signaled = false;
 		this->mode->state = EFI_NETWORK_INITIALIZED;
 	}
 out:
@@ -265,6 +335,7 @@ out:
 static efi_status_t EFIAPI efi_net_shutdown(struct efi_simple_network *this)
 {
 	efi_status_t ret = EFI_SUCCESS;
+	struct efi_net_obj *nt;
 
 	EFI_ENTRY("%p", this);
 
@@ -273,6 +344,7 @@ static efi_status_t EFIAPI efi_net_shutdown(struct efi_simple_network *this)
 		ret = EFI_INVALID_PARAMETER;
 		goto out;
 	}
+	nt = efi_netobj_from_snp(this);
 
 	switch (this->mode->state) {
 	case EFI_NETWORK_INITIALIZED:
@@ -285,9 +357,12 @@ static efi_status_t EFIAPI efi_net_shutdown(struct efi_simple_network *this)
 		goto out;
 	}
 
+	eth_set_dev(nt->dev);
+	env_set("ethact", eth_get_name());
 	eth_halt();
+
 	this->int_status = 0;
-	wait_for_packet->is_signaled = false;
+	nt->wait_for_packet->is_signaled = false;
 	this->mode->state = EFI_NETWORK_STARTED;
 
 out:
@@ -463,6 +538,7 @@ static efi_status_t EFIAPI efi_net_get_status(struct efi_simple_network *this,
 					      u32 *int_status, void **txbuf)
 {
 	efi_status_t ret = EFI_SUCCESS;
+	struct efi_net_obj *nt;
 
 	EFI_ENTRY("%p, %p, %p", this, int_status, txbuf);
 
@@ -474,6 +550,8 @@ static efi_status_t EFIAPI efi_net_get_status(struct efi_simple_network *this,
 		goto out;
 	}
 
+	nt = efi_netobj_from_snp(this);
+
 	switch (this->mode->state) {
 	case EFI_NETWORK_STOPPED:
 		ret = EFI_NOT_STARTED;
@@ -490,9 +568,9 @@ static efi_status_t EFIAPI efi_net_get_status(struct efi_simple_network *this,
 		this->int_status = 0;
 	}
 	if (txbuf)
-		*txbuf = new_tx_packet;
+		*txbuf = nt->new_tx_packet;
 
-	new_tx_packet = NULL;
+	nt->new_tx_packet = NULL;
 out:
 	return EFI_EXIT(ret);
 }
@@ -519,6 +597,7 @@ static efi_status_t EFIAPI efi_net_transmit
 		 struct efi_mac_address *dest_addr, u16 *protocol)
 {
 	efi_status_t ret = EFI_SUCCESS;
+	struct efi_net_obj *nt;
 
 	EFI_ENTRY("%p, %lu, %lu, %p, %p, %p, %p", this,
 		  (unsigned long)header_size, (unsigned long)buffer_size,
@@ -532,6 +611,8 @@ static efi_status_t EFIAPI efi_net_transmit
 		goto out;
 	}
 
+	nt = efi_netobj_from_snp(this);
+
 	/* We do not support jumbo packets */
 	if (buffer_size > PKTSIZE_ALIGN) {
 		ret = EFI_INVALID_PARAMETER;
@@ -576,11 +657,14 @@ static efi_status_t EFIAPI efi_net_transmit
 		break;
 	}
 
+	eth_set_dev(nt->dev);
+	env_set("ethact", eth_get_name());
+
 	/* Ethernet packets always fit, just bounce */
-	memcpy(transmit_buffer, buffer, buffer_size);
-	net_send_packet(transmit_buffer, buffer_size);
+	memcpy(nt->transmit_buffer, buffer, buffer_size);
+	net_send_packet(nt->transmit_buffer, buffer_size);
 
-	new_tx_packet = buffer;
+	nt->new_tx_packet = buffer;
 	this->int_status |= EFI_SIMPLE_NETWORK_TRANSMIT_INTERRUPT;
 out:
 	return EFI_EXIT(ret);
@@ -611,6 +695,7 @@ static efi_status_t EFIAPI efi_net_receive
 	struct ethernet_hdr *eth_hdr;
 	size_t hdr_size = sizeof(struct ethernet_hdr);
 	u16 protlen;
+	struct efi_net_obj *nt;
 
 	EFI_ENTRY("%p, %p, %p, %p, %p, %p, %p", this, header_size,
 		  buffer_size, buffer, src_addr, dest_addr, protocol);
@@ -624,6 +709,8 @@ static efi_status_t EFIAPI efi_net_receive
 		goto out;
 	}
 
+	nt = efi_netobj_from_snp(this);
+
 	switch (this->mode->state) {
 	case EFI_NETWORK_STOPPED:
 		ret = EFI_NOT_STARTED;
@@ -635,16 +722,16 @@ static efi_status_t EFIAPI efi_net_receive
 		break;
 	}
 
-	if (!rx_packet_num) {
+	if (!nt->rx_packet_num) {
 		ret = EFI_NOT_READY;
 		goto out;
 	}
 	/* Fill export parameters */
-	eth_hdr = (struct ethernet_hdr *)receive_buffer[rx_packet_idx];
+	eth_hdr = (struct ethernet_hdr *)nt->receive_buffer[nt->rx_packet_idx];
 	protlen = ntohs(eth_hdr->et_protlen);
 	if (protlen == 0x8100) {
 		hdr_size += 4;
-		protlen = ntohs(*(u16 *)&receive_buffer[rx_packet_idx][hdr_size - 2]);
+		protlen = ntohs(*(u16 *)&nt->receive_buffer[nt->rx_packet_idx][hdr_size - 2]);
 	}
 	if (header_size)
 		*header_size = hdr_size;
@@ -654,20 +741,20 @@ static efi_status_t EFIAPI efi_net_receive
 		memcpy(src_addr, eth_hdr->et_src, ARP_HLEN);
 	if (protocol)
 		*protocol = protlen;
-	if (*buffer_size < receive_lengths[rx_packet_idx]) {
+	if (*buffer_size < nt->receive_lengths[nt->rx_packet_idx]) {
 		/* Packet doesn't fit, try again with bigger buffer */
-		*buffer_size = receive_lengths[rx_packet_idx];
+		*buffer_size = nt->receive_lengths[nt->rx_packet_idx];
 		ret = EFI_BUFFER_TOO_SMALL;
 		goto out;
 	}
 	/* Copy packet */
-	memcpy(buffer, receive_buffer[rx_packet_idx],
-	       receive_lengths[rx_packet_idx]);
-	*buffer_size = receive_lengths[rx_packet_idx];
-	rx_packet_idx = (rx_packet_idx + 1) % ETH_PACKETS_BATCH_RECV;
-	rx_packet_num--;
-	if (rx_packet_num)
-		wait_for_packet->is_signaled = true;
+	memcpy(buffer, nt->receive_buffer[nt->rx_packet_idx],
+	       nt->receive_lengths[nt->rx_packet_idx]);
+	*buffer_size = nt->receive_lengths[nt->rx_packet_idx];
+	nt->rx_packet_idx = (nt->rx_packet_idx + 1) % ETH_PACKETS_BATCH_RECV;
+	nt->rx_packet_num--;
+	if (nt->rx_packet_num)
+		nt->wait_for_packet->is_signaled = true;
 	else
 		this->int_status &= ~EFI_SIMPLE_NETWORK_RECEIVE_INTERRUPT;
 out:
@@ -684,18 +771,35 @@ out:
  */
 void efi_net_set_dhcp_ack(void *pkt, int len)
 {
-	int maxsize = sizeof(*dhcp_ack);
+	struct efi_pxe_packet **dhcp_ack;
+	struct udevice *dev;
+	int i;
 
-	if (!dhcp_ack) {
-		dhcp_ack = malloc(maxsize);
-		if (!dhcp_ack)
+	dhcp_ack = &dhcp_cache[next_dhcp_entry].dhcp_ack;
+
+	/* For now this function gets called only by the current device */
+	dev = eth_get_dev();
+
+	int maxsize = sizeof(**dhcp_ack);
+
+	if (!*dhcp_ack) {
+		*dhcp_ack = malloc(maxsize);
+		if (!*dhcp_ack)
 			return;
 	}
-	memset(dhcp_ack, 0, maxsize);
-	memcpy(dhcp_ack, pkt, min(len, maxsize));
+	memset(*dhcp_ack, 0, maxsize);
+	memcpy(*dhcp_ack, pkt, min(len, maxsize));
+
+	dhcp_cache[next_dhcp_entry].is_valid = true;
+	dhcp_cache[next_dhcp_entry].dev = dev;
+	next_dhcp_entry++;
+	next_dhcp_entry %= MAX_NUM_DHCP_ENTRIES;
 
-	if (netobj)
-		netobj->pxe_mode.dhcp_ack = *dhcp_ack;
+	for (i = 0; i < MAX_EFI_NET_OBJS; i++) {
+		if (net_objs[i] && net_objs[i]->dev == dev) {
+			net_objs[i]->pxe_mode.dhcp_ack = **dhcp_ack;
+		}
+	}
 }
 
 /**
@@ -709,6 +813,11 @@ void efi_net_set_dhcp_ack(void *pkt, int len)
 static void efi_net_push(void *pkt, int len)
 {
 	int rx_packet_next;
+	struct efi_net_obj *nt;
+
+	nt = net_objs[curr_efi_net_obj];
+	if (!nt)
+		return;
 
 	/* Check that we at least received an Ethernet header */
 	if (len < sizeof(struct ethernet_hdr))
@@ -719,15 +828,15 @@ static void efi_net_push(void *pkt, int len)
 		return;
 
 	/* Can't store more than pre-alloced buffer */
-	if (rx_packet_num >= ETH_PACKETS_BATCH_RECV)
+	if (nt->rx_packet_num >= ETH_PACKETS_BATCH_RECV)
 		return;
 
-	rx_packet_next = (rx_packet_idx + rx_packet_num) %
+	rx_packet_next = (nt->rx_packet_idx + nt->rx_packet_num) %
 	    ETH_PACKETS_BATCH_RECV;
-	memcpy(receive_buffer[rx_packet_next], pkt, len);
-	receive_lengths[rx_packet_next] = len;
+	memcpy(nt->receive_buffer[rx_packet_next], pkt, len);
+	nt->receive_lengths[rx_packet_next] = len;
 
-	rx_packet_num++;
+	nt->rx_packet_num++;
 }
 
 /**
@@ -742,6 +851,7 @@ static void EFIAPI efi_network_timer_notify(struct efi_event *event,
 					    void *context)
 {
 	struct efi_simple_network *this = (struct efi_simple_network *)context;
+	struct efi_net_obj *nt;
 
 	EFI_ENTRY("%p, %p", event, context);
 
@@ -752,14 +862,19 @@ static void EFIAPI efi_network_timer_notify(struct efi_event *event,
 	if (!this || this->mode->state != EFI_NETWORK_INITIALIZED)
 		goto out;
 
-	if (!rx_packet_num) {
+	nt = efi_netobj_from_snp(this);
+	curr_efi_net_obj = nt->efi_seq_num;
+
+	if (!nt->rx_packet_num) {
+		eth_set_dev(nt->dev);
+		env_set("ethact", eth_get_name());
 		push_packet = efi_net_push;
 		eth_rx();
 		push_packet = NULL;
-		if (rx_packet_num) {
+		if (nt->rx_packet_num) {
 			this->int_status |=
 				EFI_SIMPLE_NETWORK_RECEIVE_INTERRUPT;
-			wait_for_packet->is_signaled = true;
+			nt->wait_for_packet->is_signaled = true;
 		}
 	}
 out:
@@ -879,30 +994,179 @@ static efi_status_t EFIAPI efi_pxe_base_code_set_packets(
 }
 
 /**
+ * efi_netobj_set_dp() - set device path of a netobj
+ *
+ * @netobj:	pointer to efi_net_obj
+ * @dp:		device path to set, allocated by caller
+ * Return:	status code
+ */
+efi_status_t efi_netobj_set_dp(struct efi_net_obj *netobj, struct efi_device_path *dp)
+{
+	efi_status_t ret;
+	struct efi_handler *phandler;
+	struct efi_device_path *new_net_dp;
+
+	if (!efi_netobj_is_active(netobj))
+		return EFI_SUCCESS;
+
+	// Create a device path for the netobj
+	new_net_dp = dp;
+	if (!new_net_dp)
+		return EFI_OUT_OF_RESOURCES;
+
+	phandler = NULL;
+	efi_search_protocol(&netobj->header, &efi_guid_device_path, &phandler);
+
+	// If the device path protocol is not yet installed, install it
+	if (!phandler)
+		goto add;
+
+	// If it is already installed, try to update it
+	ret = efi_reinstall_protocol_interface(&netobj->header, &efi_guid_device_path,
+					       phandler->protocol_interface, new_net_dp);
+	if (ret != EFI_SUCCESS)
+		return ret;
+
+	return EFI_SUCCESS;
+add:
+	ret = efi_add_protocol(&netobj->header, &efi_guid_device_path,
+			       new_net_dp);
+	if (ret != EFI_SUCCESS)
+		return ret;
+
+	return EFI_SUCCESS;
+}
+
+/**
+ * efi_netobj_get_dp() - get device path of a netobj
+ *
+ * @netobj:	pointer to efi_net_obj
+ * Return:	device path, NULL on error
+ */
+static struct efi_device_path *efi_netobj_get_dp(struct efi_net_obj *netobj)
+{
+	struct efi_handler *phandler;
+
+	if (!efi_netobj_is_active(netobj))
+		return NULL;
+
+	phandler = NULL;
+	efi_search_protocol(&netobj->header, &efi_guid_device_path, &phandler);
+
+	if (phandler && phandler->protocol_interface)
+		return efi_dp_dup(phandler->protocol_interface);
+
+	return NULL;
+}
+
+/**
+ * efi_net_do_start() - start the efi network stack
+ *
+ * This gets called from do_bootefi_exec() each time a payload gets executed.
+ *
+ * @dev:	net udevice
+ * Return:	status code
+ */
+efi_status_t efi_net_do_start(struct udevice *dev)
+{
+	efi_status_t r = EFI_SUCCESS;
+	struct efi_net_obj *netobj;
+	struct efi_device_path *net_dp;
+	int i;
+
+	netobj = NULL;
+	for (i = 0; i < MAX_EFI_NET_OBJS; i++) {
+		if (net_objs[i] && net_objs[i]->dev == dev) {
+			netobj = net_objs[i];
+			break;
+		}
+	}
+
+	if (!efi_netobj_is_active(netobj))
+		return r;
+
+	efi_net_dp_from_dev(&net_dp, netobj->dev, true);
+	// If no dp cache entry applies and there already
+	// is a device path installed, continue
+	if (!net_dp) {
+		if (efi_netobj_get_dp(netobj))
+			goto set_addr;
+		else
+			net_dp = efi_dp_from_eth(netobj->dev);
+
+	}
+
+	if (!net_dp)
+		return EFI_OUT_OF_RESOURCES;
+
+	r = efi_netobj_set_dp(netobj, net_dp);
+	if (r != EFI_SUCCESS)
+		return r;
+set_addr:
+#ifdef CONFIG_EFI_HTTP_PROTOCOL
+	/*
+	 * No harm on doing the following. If the PXE handle is present, the client could
+	 * find it and try to get its IP address from it. In here the PXE handle is present
+	 * but the PXE protocol is not yet implmenented, so we add this in the meantime.
+	 */
+	efi_net_get_addr((struct efi_ipv4_address *)&netobj->pxe_mode.station_ip,
+			 (struct efi_ipv4_address *)&netobj->pxe_mode.subnet_mask, NULL, dev);
+#endif
+
+	return r;
+}
+
+/**
  * efi_net_register() - register the simple network protocol
  *
  * This gets called from do_bootefi_exec().
+ * @dev:	net udevice
  */
-efi_status_t efi_net_register(void)
+efi_status_t efi_net_register(struct udevice *dev)
 {
 	efi_status_t r;
-	int i;
-
-	if (!eth_get_dev()) {
+	int seq_num;
+	struct efi_net_obj *netobj;
+	void *transmit_buffer = NULL;
+	uchar **receive_buffer = NULL;
+	size_t *receive_lengths;
+	int i, j;
+
+	if (!dev) {
 		/* No network device active, don't expose any */
 		return EFI_SUCCESS;
 	}
 
+	for (i = 0; i < MAX_EFI_NET_OBJS; i++) {
+		if (net_objs[i] && net_objs[i]->dev == dev) {
+			// Do not register duplicate devices
+			return EFI_SUCCESS;
+		}
+	}
+
+	seq_num = -1;
+	for (i = 0; i < MAX_EFI_NET_OBJS; i++) {
+		if (!net_objs[i]) {
+			seq_num = i;
+			break;
+		}
+	}
+	if (seq_num < 0)
+		return EFI_OUT_OF_RESOURCES;
+
 	/* We only expose the "active" network device, so one is enough */
 	netobj = calloc(1, sizeof(*netobj));
 	if (!netobj)
 		goto out_of_resources;
 
+	netobj->dev = dev;
+
 	/* Allocate an aligned transmit buffer */
 	transmit_buffer = calloc(1, PKTSIZE_ALIGN + PKTALIGN);
 	if (!transmit_buffer)
 		goto out_of_resources;
 	transmit_buffer = (void *)ALIGN((uintptr_t)transmit_buffer, PKTALIGN);
+	netobj->transmit_buffer = transmit_buffer;
 
 	/* Allocate a number of receive buffers */
 	receive_buffer = calloc(ETH_PACKETS_BATCH_RECV,
@@ -914,10 +1178,13 @@ efi_status_t efi_net_register(void)
 		if (!receive_buffer[i])
 			goto out_of_resources;
 	}
+	netobj->receive_buffer = receive_buffer;
+
 	receive_lengths = calloc(ETH_PACKETS_BATCH_RECV,
 				 sizeof(*receive_lengths));
 	if (!receive_lengths)
 		goto out_of_resources;
+	netobj->receive_lengths = receive_lengths;
 
 	/* Hook net up to the device list */
 	efi_add_handle(&netobj->header);
@@ -928,14 +1195,6 @@ efi_status_t efi_net_register(void)
 	if (r != EFI_SUCCESS)
 		goto failure_to_add_protocol;
 
-	if (net_dp)
-		r = efi_add_protocol(&netobj->header, &efi_guid_device_path,
-			       net_dp);
-	else
-		r = efi_net_set_dp("Net", NULL);
-	if (r != EFI_SUCCESS)
-		goto failure_to_add_protocol;
-
 	r = efi_add_protocol(&netobj->header, &efi_pxe_base_code_protocol_guid,
 			     &netobj->pxe);
 	if (r != EFI_SUCCESS)
@@ -956,7 +1215,9 @@ efi_status_t efi_net_register(void)
 	netobj->net.receive = efi_net_receive;
 	netobj->net.mode = &netobj->net_mode;
 	netobj->net_mode.state = EFI_NETWORK_STOPPED;
-	memcpy(netobj->net_mode.current_address.mac_addr, eth_get_ethaddr(), 6);
+	if (dev_get_plat(dev))
+		memcpy(netobj->net_mode.current_address.mac_addr,
+		       ((struct eth_pdata *)dev_get_plat(dev))->enetaddr, 6);
 	netobj->net_mode.hwaddr_size = ARP_HLEN;
 	netobj->net_mode.media_header_size = ETHER_HDR_SIZE;
 	netobj->net_mode.max_packet_size = PKTSIZE;
@@ -976,20 +1237,31 @@ efi_status_t efi_net_register(void)
 	netobj->pxe.set_station_ip = efi_pxe_base_code_set_station_ip;
 	netobj->pxe.set_packets = efi_pxe_base_code_set_packets;
 	netobj->pxe.mode = &netobj->pxe_mode;
-	if (dhcp_ack)
-		netobj->pxe_mode.dhcp_ack = *dhcp_ack;
+
+	/*
+	 * Scan dhcp entries for one corresponding
+	 * to this udevice, from newest to oldest
+	 */
+	i = (next_dhcp_entry + MAX_NUM_DHCP_ENTRIES - 1) % MAX_NUM_DHCP_ENTRIES;
+	for (j = 0; dhcp_cache[i].is_valid && j < MAX_NUM_DHCP_ENTRIES;
+	     i = (i + MAX_NUM_DHCP_ENTRIES - 1) % MAX_NUM_DHCP_ENTRIES, j++) {
+		if (dev == dhcp_cache[i].dev) {
+			netobj->pxe_mode.dhcp_ack = *dhcp_cache[i].dhcp_ack;
+			break;
+		}
+	}
 
 	/*
 	 * Create WaitForPacket event.
 	 */
 	r = efi_create_event(EVT_NOTIFY_WAIT, TPL_CALLBACK,
 			     efi_network_timer_notify, NULL, NULL,
-			     &wait_for_packet);
+			     &netobj->wait_for_packet);
 	if (r != EFI_SUCCESS) {
 		printf("ERROR: Failed to register network event\n");
 		return r;
 	}
-	netobj->net.wait_for_packet = wait_for_packet;
+	netobj->net.wait_for_packet = netobj->wait_for_packet;
 	/*
 	 * Create a timer event.
 	 *
@@ -1000,13 +1272,13 @@ efi_status_t efi_net_register(void)
 	 */
 	r = efi_create_event(EVT_TIMER | EVT_NOTIFY_SIGNAL, TPL_NOTIFY,
 			     efi_network_timer_notify, &netobj->net, NULL,
-			     &network_timer_event);
+			     &netobj->network_timer_event);
 	if (r != EFI_SUCCESS) {
 		printf("ERROR: Failed to register network event\n");
 		return r;
 	}
 	/* Network is time critical, create event in every timer cycle */
-	r = efi_set_timer(network_timer_event, EFI_TIMER_PERIODIC, 0);
+	r = efi_set_timer(netobj->network_timer_event, EFI_TIMER_PERIODIC, 0);
 	if (r != EFI_SUCCESS) {
 		printf("ERROR: Failed to set network timer\n");
 		return r;
@@ -1022,15 +1294,9 @@ efi_status_t efi_net_register(void)
 	r = efi_http_register(&netobj->header, &netobj->http_service_binding);
 	if (r != EFI_SUCCESS)
 		goto failure_to_add_protocol;
-	/*
-	 * No harm on doing the following. If the PXE handle is present, the client could
-	 * find it and try to get its IP address from it. In here the PXE handle is present
-	 * but the PXE protocol is not yet implmenented, so we add this in the meantime.
-	 */
-	efi_net_get_addr((struct efi_ipv4_address *)&netobj->pxe_mode.station_ip,
-			 (struct efi_ipv4_address *)&netobj->pxe_mode.subnet_mask, NULL);
 #endif
-
+	netobj->efi_seq_num = seq_num;
+	net_objs[seq_num] = netobj;
 	return EFI_SUCCESS;
 failure_to_add_protocol:
 	printf("ERROR: Failure to add protocol\n");
@@ -1049,86 +1315,103 @@ out_of_resources:
 }
 
 /**
- * efi_net_set_dp() - set device path of efi net device
+ * efi_net_new_dp() - update device path associated to a net udevice
  *
  * This gets called to update the device path when a new boot
  * file is downloaded
  *
  * @dev:	dev to set the device path from
  * @server:	remote server address
+ * @udev:	net udevice
  * Return:	status code
  */
-efi_status_t efi_net_set_dp(const char *dev, const char *server)
+efi_status_t efi_net_new_dp(const char *dev, const char *server, struct udevice *udev)
 {
-	efi_status_t ret = EFI_SUCCESS;
-	struct efi_handler *phandler;
+	efi_status_t ret;
+	struct efi_net_obj *netobj;
 	struct efi_device_path *old_net_dp, *new_net_dp;
+	struct efi_device_path **dp;
+	int i;
 
-	old_net_dp = net_dp;
+	dp = &dp_cache[next_dp_entry].net_dp;
+
+	dp_cache[next_dp_entry].dev = udev;
+	dp_cache[next_dp_entry].is_valid = true;
+	next_dp_entry++;
+	next_dp_entry %= MAX_NUM_DP_ENTRIES;
+
+	old_net_dp = *dp;
 	new_net_dp = NULL;
 	if (!strcmp(dev, "Net"))
-		new_net_dp = efi_dp_from_eth();
+		new_net_dp = efi_dp_from_eth(udev);
 	else if (!strcmp(dev, "Http"))
-		new_net_dp = efi_dp_from_http(server);
-
-	if (!new_net_dp) {
+		new_net_dp = efi_dp_from_http(server, udev);
+	if (!new_net_dp)
 		return EFI_OUT_OF_RESOURCES;
-	}
-
-	// If netobj is not started yet, end here.
-	if (!netobj) {
-		goto exit;
-	}
-
-	phandler = NULL;
-	efi_search_protocol(&netobj->header, &efi_guid_device_path, &phandler);
 
-	// If the device path protocol is not yet installed, install it
-	if (!phandler)
-		goto add;
-
-	// If it is already installed, try to update it
-	ret = efi_reinstall_protocol_interface(&netobj->header, &efi_guid_device_path,
-					       old_net_dp, new_net_dp);
-	if (ret != EFI_SUCCESS)
-		goto error;
-
-	net_dp = new_net_dp;
+	*dp = new_net_dp;
+	// Free the old cache entry
 	efi_free_pool(old_net_dp);
 
-	return EFI_SUCCESS;
-add:
-	ret = efi_add_protocol(&netobj->header, &efi_guid_device_path,
-			       new_net_dp);
-	if (ret != EFI_SUCCESS)
-		goto error;
-exit:
-	net_dp = new_net_dp;
-	efi_free_pool(old_net_dp);
+	netobj = NULL;
+	for (i = 0; i < MAX_EFI_NET_OBJS; i++) {
+		if (net_objs[i] && net_objs[i]->dev == udev) {
+			netobj = net_objs[i];
+			break;
+		}
+	}
+	if (!netobj)
+		return EFI_SUCCESS;
 
-	return ret;
-error:
-	// Failed, restore
-	efi_free_pool(new_net_dp);
+	new_net_dp = efi_dp_dup(*dp);
+	if (!new_net_dp)
+		return EFI_OUT_OF_RESOURCES;
+	ret = efi_netobj_set_dp(netobj, new_net_dp);
+	if (ret != EFI_SUCCESS)
+		efi_free_pool(new_net_dp);
 
 	return ret;
 }
 
 /**
- * efi_net_get_dp() - get device path of efi net device
+ * efi_net_dp_from_dev() - get device path associated to a net udevice
  *
  * Produce a copy of the current device path
  *
- * @dp:		copy of the current device path, or NULL on error
+ * @dp:		copy of the current device path
+ * @udev:	net udevice
+ * @cache_only:	get device path from cache only
  */
-void efi_net_get_dp(struct efi_device_path **dp)
+void efi_net_dp_from_dev(struct efi_device_path **dp, struct udevice *udev, bool cache_only)
 {
+	int i, j;
+
 	if (!dp)
 		return;
-	if (!net_dp)
-		efi_net_set_dp("Net", NULL);
-	if (net_dp)
-		*dp = efi_dp_dup(net_dp);
+
+	*dp = NULL;
+
+	if (cache_only)
+		goto cache;
+
+	// If a netobj matches:
+	for (i = 0; i < MAX_EFI_NET_OBJS; i++) {
+		if (net_objs[i] && net_objs[i]->dev == udev) {
+			*dp = efi_netobj_get_dp(net_objs[i]);
+			if (*dp)
+				return;
+		}
+	}
+cache:
+	// Search in the cache
+	i = (next_dp_entry + MAX_NUM_DP_ENTRIES - 1) % MAX_NUM_DP_ENTRIES;
+	for (j = 0; dp_cache[i].is_valid && j < MAX_NUM_DP_ENTRIES;
+		i = (i + MAX_NUM_DP_ENTRIES - 1) % MAX_NUM_DP_ENTRIES, j++) {
+		if (dp_cache[i].dev == udev) {
+			*dp = efi_dp_dup(dp_cache[i].net_dp);
+			return;
+		}
+	}
 }
 
 /**
@@ -1144,11 +1427,15 @@ void efi_net_get_dp(struct efi_device_path **dp)
  *		be filled with the current network mask
  * @gw:		pointer to an efi_ipv4_address struct to be
  *		filled with the current network gateway
+ * @dev:	udevice
  */
 void efi_net_get_addr(struct efi_ipv4_address *ip,
 		      struct efi_ipv4_address *mask,
-		      struct efi_ipv4_address *gw)
+		      struct efi_ipv4_address *gw,
+		      struct udevice *dev)
 {
+	if (!dev)
+		dev = eth_get_dev();
 #ifdef CONFIG_NET_LWIP
 	char ipstr[] = "ipaddr\0\0";
 	char maskstr[] = "netmask\0\0";
@@ -1157,7 +1444,7 @@ void efi_net_get_addr(struct efi_ipv4_address *ip,
 	struct in_addr tmp;
 	char *env;
 
-	idx = dev_seq(eth_get_dev());
+	idx = dev_seq(dev);
 
 	if (idx < 0 || idx > 99) {
 		log_err("unexpected idx %d\n", idx);
@@ -1204,11 +1491,15 @@ void efi_net_get_addr(struct efi_ipv4_address *ip,
  * @ip:		pointer to new IP address
  * @mask:	pointer to new network mask to set
  * @gw:		pointer to new network gateway
+ * @dev:	udevice
  */
 void efi_net_set_addr(struct efi_ipv4_address *ip,
 		      struct efi_ipv4_address *mask,
-		      struct efi_ipv4_address *gw)
+		      struct efi_ipv4_address *gw,
+		      struct udevice *dev)
 {
+	if (!dev)
+		dev = eth_get_dev();
 #ifdef CONFIG_NET_LWIP
 	char ipstr[] = "ipaddr\0\0";
 	char maskstr[] = "netmask\0\0";
@@ -1217,7 +1508,7 @@ void efi_net_set_addr(struct efi_ipv4_address *ip,
 	struct in_addr *addr;
 	char tmp[46];
 
-	idx = dev_seq(eth_get_dev());
+	idx = dev_seq(dev);
 
 	if (idx < 0 || idx > 99) {
 		log_err("unexpected idx %d\n", idx);
@@ -1255,6 +1546,7 @@ void efi_net_set_addr(struct efi_ipv4_address *ip,
 #endif
 }
 
+#if IS_ENABLED(CONFIG_EFI_HTTP_PROTOCOL)
 /**
  * efi_net_set_buffer() - allocate a buffer of min 64K
  *
@@ -1342,26 +1634,41 @@ void efi_net_parse_headers(ulong *num_headers, struct http_header *headers)
  * @status_code:	HTTP status code
  * @file_size:		file size in bytes
  * @headers_buffer:	headers buffer
+ * @parent:		service binding protocol
  * Return:		status code
  */
 efi_status_t efi_net_do_request(u8 *url, enum efi_http_method method, void **buffer,
-				u32 *status_code, ulong *file_size, char *headers_buffer)
+				u32 *status_code, ulong *file_size, char *headers_buffer,
+				struct efi_service_binding_protocol *parent)
 {
 	efi_status_t ret = EFI_SUCCESS;
 	int wget_ret;
 	static bool last_head;
+	struct udevice *dev;
+	int i;
 
-	if (!buffer || !file_size)
+	if (!buffer || !file_size || !parent)
 		return EFI_ABORTED;
 
 	efi_wget_info.method = (enum wget_http_method)method;
 	efi_wget_info.headers = headers_buffer;
 
+	// Set corresponding udevice
+	dev = NULL;
+	for (i = 0; i < MAX_EFI_NET_OBJS; i++) {
+		if (net_objs[i] && &net_objs[i]->http_service_binding == parent)
+			dev = net_objs[i]->dev;
+	}
+	if (!dev)
+		return EFI_ABORTED;
+
 	switch (method) {
 	case HTTP_METHOD_GET:
 		ret = efi_net_set_buffer(buffer, last_head ? (size_t)efi_wget_info.hdr_cont_len : 0);
 		if (ret != EFI_SUCCESS)
 			goto out;
+		eth_set_dev(dev);
+		env_set("ethact", eth_get_name());
 		wget_ret = wget_request((ulong)*buffer, url, &efi_wget_info);
 		if ((ulong)efi_wget_info.hdr_cont_len > efi_wget_info.buffer_size) {
 			// Try again with updated buffer size
@@ -1369,6 +1676,8 @@ efi_status_t efi_net_do_request(u8 *url, enum efi_http_method method, void **buf
 			ret = efi_net_set_buffer(buffer, (size_t)efi_wget_info.hdr_cont_len);
 			if (ret != EFI_SUCCESS)
 				goto out;
+			eth_set_dev(dev);
+			env_set("ethact", eth_get_name());
 			if (wget_request((ulong)*buffer, url, &efi_wget_info)) {
 				efi_free_pool(*buffer);
 				ret = EFI_DEVICE_ERROR;
@@ -1388,6 +1697,8 @@ efi_status_t efi_net_do_request(u8 *url, enum efi_http_method method, void **buf
 		ret = efi_net_set_buffer(buffer, 0);
 		if (ret != EFI_SUCCESS)
 			goto out;
+		eth_set_dev(dev);
+		env_set("ethact", eth_get_name());
 		wget_request((ulong)*buffer, url, &efi_wget_info);
 		*file_size = 0;
 		*status_code = efi_wget_info.status_code;
@@ -1401,3 +1712,4 @@ efi_status_t efi_net_do_request(u8 *url, enum efi_http_method method, void **buf
 out:
 	return ret;
 }
+#endif
diff --git a/lib/efi_loader/efi_setup.c b/lib/efi_loader/efi_setup.c
index aa59bc7779d..48f91da5df7 100644
--- a/lib/efi_loader/efi_setup.c
+++ b/lib/efi_loader/efi_setup.c
@@ -11,7 +11,9 @@
 #include <efi_variable.h>
 #include <log.h>
 #include <asm-generic/unaligned.h>
+#include <net.h>
 
+#define OBJ_LIST_INITIALIZED 0
 #define OBJ_LIST_NOT_INITIALIZED 1
 
 efi_status_t efi_obj_list_initialized = OBJ_LIST_NOT_INITIALIZED;
@@ -209,6 +211,21 @@ out:
 }
 
 /**
+ * efi_start_obj_list() - Start EFI object list
+ *
+ * Return:	status code
+ */
+static efi_status_t efi_start_obj_list(void)
+{
+	efi_status_t ret = EFI_SUCCESS;
+
+	if (IS_ENABLED(CONFIG_NETDEVICES))
+		ret = efi_net_do_start(eth_get_dev());
+
+	return ret;
+}
+
+/**
  * efi_init_obj_list() - Initialize and populate EFI object list
  *
  * Return:	status code
@@ -217,7 +234,9 @@ efi_status_t efi_init_obj_list(void)
 {
 	efi_status_t ret = EFI_SUCCESS;
 
-	/* Initialize once only */
+	/* Initialize only once, but start every time if correctly initialized*/
+	if (efi_obj_list_initialized == OBJ_LIST_INITIALIZED)
+		return efi_start_obj_list();
 	if (efi_obj_list_initialized != OBJ_LIST_NOT_INITIALIZED)
 		return efi_obj_list_initialized;
 
@@ -318,7 +337,7 @@ efi_status_t efi_init_obj_list(void)
 			goto out;
 	}
 	if (IS_ENABLED(CONFIG_NETDEVICES)) {
-		ret = efi_net_register();
+		ret = efi_net_register(eth_get_dev());
 		if (ret != EFI_SUCCESS)
 			goto out;
 	}
@@ -349,6 +368,10 @@ efi_status_t efi_init_obj_list(void)
 	if (IS_ENABLED(CONFIG_EFI_CAPSULE_ON_DISK) &&
 	    !IS_ENABLED(CONFIG_EFI_CAPSULE_ON_DISK_EARLY))
 		ret = efi_launch_capsules();
+	if (ret != EFI_SUCCESS)
+		goto out;
+
+	ret = efi_start_obj_list();
 out:
 	efi_obj_list_initialized = ret;
 	return ret;
diff --git a/lib/efi_selftest/efi_selftest_snp.c b/lib/efi_selftest/efi_selftest_snp.c
index 15af8d3e18c..b00c76c2f17 100644
--- a/lib/efi_selftest/efi_selftest_snp.c
+++ b/lib/efi_selftest/efi_selftest_snp.c
@@ -67,7 +67,6 @@ struct dhcp {
 static struct efi_boot_services *boottime;
 static struct efi_simple_network *net;
 static struct efi_event *timer;
-static const efi_guid_t efi_net_guid = EFI_SIMPLE_NETWORK_PROTOCOL_GUID;
 /* IP packet ID */
 static unsigned int net_ip_id;
 
diff --git a/lib/lmb.c b/lib/lmb.c
index 61bb13dc4e2..bb6f232f6bc 100644
--- a/lib/lmb.c
+++ b/lib/lmb.c
@@ -23,6 +23,9 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+#define LMB_RGN_OVERLAP		1
+#define LMB_RGN_ADJACENT	2
+
 /*
  * The following low level LMB functions must not access the global LMB memory
  * map since they are also used to manage IOVA memory maps in iommu drivers like
@@ -49,8 +52,22 @@ static long lmb_addrs_adjacent(phys_addr_t base1, phys_size_t size1,
 	return 0;
 }
 
-static long lmb_regions_overlap(struct alist *lmb_rgn_lst, unsigned long r1,
-				unsigned long r2)
+/**
+ * lmb_regions_check() - Check if the regions overlap, or are adjacent
+ * @lmb_rgn_lst: List of LMB regions
+ * @r1: First region to check
+ * @r2: Second region to check
+ *
+ * Check if the two regions with matching flags, r1 and r2 are
+ * adjacent to each other, or if they overlap.
+ *
+ * Return:
+ * * %LMB_RGN_OVERLAP	- Regions overlap
+ * * %LMB_RGN_ADJACENT	- Regions adjacent to each other
+ * * 0			- Neither of the above, or flags mismatch
+ */
+static long lmb_regions_check(struct alist *lmb_rgn_lst, unsigned long r1,
+			      unsigned long r2)
 {
 	struct lmb_region *rgn = lmb_rgn_lst->data;
 	phys_addr_t base1 = rgn[r1].base;
@@ -58,19 +75,15 @@ static long lmb_regions_overlap(struct alist *lmb_rgn_lst, unsigned long r1,
 	phys_addr_t base2 = rgn[r2].base;
 	phys_size_t size2 = rgn[r2].size;
 
-	return lmb_addrs_overlap(base1, size1, base2, size2);
-}
+	if (rgn[r1].flags != rgn[r2].flags)
+		return 0;
 
-static long lmb_regions_adjacent(struct alist *lmb_rgn_lst, unsigned long r1,
-				 unsigned long r2)
-{
-	struct lmb_region *rgn = lmb_rgn_lst->data;
-	phys_addr_t base1 = rgn[r1].base;
-	phys_size_t size1 = rgn[r1].size;
-	phys_addr_t base2 = rgn[r2].base;
-	phys_size_t size2 = rgn[r2].size;
+	if (lmb_addrs_overlap(base1, size1, base2, size2))
+		return LMB_RGN_OVERLAP;
+	else if (lmb_addrs_adjacent(base1, size1, base2, size2))
+		return LMB_RGN_ADJACENT;
 
-	return lmb_addrs_adjacent(base1, size1, base2, size2);
+	return 0;
 }
 
 static void lmb_remove_region(struct alist *lmb_rgn_lst, unsigned long r)
@@ -96,25 +109,6 @@ static void lmb_coalesce_regions(struct alist *lmb_rgn_lst, unsigned long r1,
 	lmb_remove_region(lmb_rgn_lst, r2);
 }
 
-/*Assumption : base addr of region 1 < base addr of region 2*/
-static void lmb_fix_over_lap_regions(struct alist *lmb_rgn_lst,
-				     unsigned long r1, unsigned long r2)
-{
-	struct lmb_region *rgn = lmb_rgn_lst->data;
-
-	phys_addr_t base1 = rgn[r1].base;
-	phys_size_t size1 = rgn[r1].size;
-	phys_addr_t base2 = rgn[r2].base;
-	phys_size_t size2 = rgn[r2].size;
-
-	if (base1 + size1 > base2 + size2) {
-		printf("This will not be a case any time\n");
-		return;
-	}
-	rgn[r1].size = base2 + size2 - base1;
-	lmb_remove_region(lmb_rgn_lst, r2);
-}
-
 static long lmb_resize_regions(struct alist *lmb_rgn_lst,
 			       unsigned long idx_start,
 			       phys_addr_t base, phys_size_t size)
@@ -209,14 +203,11 @@ static long lmb_add_region_flags(struct alist *lmb_rgn_lst, phys_addr_t base,
 			break;
 		} else if (ret < 0) {
 			if (flags != rgnflags)
-				break;
+				continue;
 			rgn[i].size += size;
 			coalesced++;
 			break;
 		} else if (lmb_addrs_overlap(base, size, rgnbase, rgnsize)) {
-			if (flags != LMB_NONE)
-				return -EEXIST;
-
 			ret = lmb_resize_regions(lmb_rgn_lst, i, base, size);
 			if (ret < 0)
 				return -1;
@@ -229,16 +220,21 @@ static long lmb_add_region_flags(struct alist *lmb_rgn_lst, phys_addr_t base,
 	}
 
 	if (lmb_rgn_lst->count && i < lmb_rgn_lst->count - 1) {
-		rgn = lmb_rgn_lst->data;
-		if (rgn[i].flags == rgn[i + 1].flags) {
-			if (lmb_regions_adjacent(lmb_rgn_lst, i, i + 1)) {
-				lmb_coalesce_regions(lmb_rgn_lst, i, i + 1);
-				coalesced++;
-			} else if (lmb_regions_overlap(lmb_rgn_lst, i, i + 1)) {
-				/* fix overlapping area */
-				lmb_fix_over_lap_regions(lmb_rgn_lst, i, i + 1);
-				coalesced++;
-			}
+		ret = lmb_regions_check(lmb_rgn_lst, i, i + 1);
+		if (ret == LMB_RGN_ADJACENT) {
+			lmb_coalesce_regions(lmb_rgn_lst, i, i + 1);
+			coalesced++;
+		} else if (ret == LMB_RGN_OVERLAP) {
+			/* fix overlapping areas */
+			phys_addr_t rgnbase = rgn[i].base;
+			phys_size_t rgnsize = rgn[i].size;
+
+			ret = lmb_resize_regions(lmb_rgn_lst, i,
+						 rgnbase, rgnsize);
+			if (ret < 0)
+				return -1;
+
+			coalesced++;
 		}
 	}
 
@@ -561,6 +557,39 @@ static __maybe_unused void lmb_reserve_common_spl(void)
 	}
 }
 
+/**
+ * lmb_can_reserve_region() - check if the region can be reserved
+ * @base: base address of region to be reserved
+ * @size: size of region to be reserved
+ * @flags: flag of the region to be reserved
+ *
+ * Go through all the reserved regions and ensure that the requested
+ * region does not overlap with any existing regions. An overlap is
+ * allowed only when the flag of the request region and the existing
+ * region is LMB_NONE.
+ *
+ * Return: true if region can be reserved, false otherwise
+ */
+static bool lmb_can_reserve_region(phys_addr_t base, phys_size_t size,
+				   u32 flags)
+{
+	uint i;
+	struct lmb_region *lmb_reserved = lmb.used_mem.data;
+
+	for (i = 0; i < lmb.used_mem.count; i++) {
+		u32 rgnflags = lmb_reserved[i].flags;
+		phys_addr_t rgnbase = lmb_reserved[i].base;
+		phys_size_t rgnsize = lmb_reserved[i].size;
+
+		if (lmb_addrs_overlap(base, size, rgnbase, rgnsize)) {
+			if (flags != LMB_NONE || flags != rgnflags)
+				return false;
+		}
+	}
+
+	return true;
+}
+
 void lmb_add_memory(void)
 {
 	int i;
@@ -633,6 +662,9 @@ long lmb_reserve(phys_addr_t base, phys_size_t size, u32 flags)
 	long ret = 0;
 	struct alist *lmb_rgn_lst = &lmb.used_mem;
 
+	if (!lmb_can_reserve_region(base, size, flags))
+		return -EEXIST;
+
 	ret = lmb_add_region_flags(lmb_rgn_lst, base, size, flags);
 	if (ret)
 		return ret;
@@ -692,26 +724,22 @@ static phys_addr_t _lmb_alloc_base(phys_size_t size, ulong align,
 			base = ALIGN_DOWN(res_base - size, align);
 		}
 	}
+
+	log_debug("%s: Failed to allocate 0x%lx bytes below 0x%lx\n",
+		  __func__, (ulong)size, (ulong)max_addr);
+
 	return 0;
 }
 
 phys_addr_t lmb_alloc(phys_size_t size, ulong align)
 {
-	return lmb_alloc_base(size, align, LMB_ALLOC_ANYWHERE, LMB_NONE);
+	return _lmb_alloc_base(size, align, LMB_ALLOC_ANYWHERE, LMB_NONE);
 }
 
 phys_addr_t lmb_alloc_base(phys_size_t size, ulong align, phys_addr_t max_addr,
 			   uint flags)
 {
-	phys_addr_t alloc;
-
-	alloc = _lmb_alloc_base(size, align, max_addr, flags);
-
-	if (alloc == 0)
-		printf("ERROR: Failed to allocate 0x%lx bytes below 0x%lx.\n",
-		       (ulong)size, (ulong)max_addr);
-
-	return alloc;
+	return _lmb_alloc_base(size, align, max_addr, flags);
 }
 
 int lmb_alloc_addr(phys_addr_t base, phys_size_t size, u32 flags)
diff --git a/lib/lwip/lwip/src/apps/altcp_tls/altcp_tls_mbedtls.c b/lib/lwip/lwip/src/apps/altcp_tls/altcp_tls_mbedtls.c
index 46421588fef..ef51a5ac168 100644
--- a/lib/lwip/lwip/src/apps/altcp_tls/altcp_tls_mbedtls.c
+++ b/lib/lwip/lwip/src/apps/altcp_tls/altcp_tls_mbedtls.c
@@ -298,6 +298,9 @@ altcp_mbedtls_lower_recv_process(struct altcp_pcb *conn, altcp_mbedtls_state_t *
     if (ret != 0) {
       LWIP_DEBUGF(ALTCP_MBEDTLS_DEBUG, ("mbedtls_ssl_handshake failed: %d\n", ret));
       /* handshake failed, connection has to be closed */
+      if (ret == MBEDTLS_ERR_X509_CERT_VERIFY_FAILED) {
+        printf("Certificate verification failed\n");
+      }
       if (conn->err) {
         conn->err(conn->arg, ERR_CLSD);
       }
@@ -786,6 +789,7 @@ altcp_tls_create_config(int is_server, u8_t cert_count, u8_t pkey_count, int hav
   int ret;
   struct altcp_tls_config *conf;
   mbedtls_x509_crt *mem;
+  int authmode = have_ca ? MBEDTLS_SSL_VERIFY_REQUIRED : MBEDTLS_SSL_VERIFY_NONE;
 
   if (TCP_WND < MBEDTLS_SSL_IN_CONTENT_LEN || TCP_WND < MBEDTLS_SSL_OUT_CONTENT_LEN) {
     LWIP_DEBUGF(ALTCP_MBEDTLS_DEBUG|LWIP_DBG_LEVEL_SERIOUS,
@@ -840,7 +844,10 @@ altcp_tls_create_config(int is_server, u8_t cert_count, u8_t pkey_count, int hav
     altcp_mbedtls_free_config(conf);
     return NULL;
   }
-  mbedtls_ssl_conf_authmode(&conf->conf, ALTCP_MBEDTLS_AUTHMODE);
+  if (authmode == MBEDTLS_SSL_VERIFY_NONE) {
+     printf("WARNING: no CA certificates, HTTPS connections not authenticated\n");
+  }
+  mbedtls_ssl_conf_authmode(&conf->conf, authmode);
 
   mbedtls_ssl_conf_rng(&conf->conf, mbedtls_ctr_drbg_random, &altcp_tls_entropy_rng->ctr_drbg);
 #if ALTCP_MBEDTLS_LIB_DEBUG != LWIP_DBG_OFF
diff --git a/lib/lwip/lwip/src/include/lwip/apps/altcp_tls_mbedtls_opts.h b/lib/lwip/lwip/src/include/lwip/apps/altcp_tls_mbedtls_opts.h
index e41301c061c..71aa5993935 100644
--- a/lib/lwip/lwip/src/include/lwip/apps/altcp_tls_mbedtls_opts.h
+++ b/lib/lwip/lwip/src/include/lwip/apps/altcp_tls_mbedtls_opts.h
@@ -100,12 +100,6 @@
 #define ALTCP_MBEDTLS_SESSION_TICKET_TIMEOUT_SECONDS  (60 * 60 * 24)
 #endif
 
-/** Certificate verification mode: MBEDTLS_SSL_VERIFY_NONE, MBEDTLS_SSL_VERIFY_OPTIONAL (default),
- * MBEDTLS_SSL_VERIFY_REQUIRED (recommended)*/
-#ifndef ALTCP_MBEDTLS_AUTHMODE
-#define ALTCP_MBEDTLS_AUTHMODE                        MBEDTLS_SSL_VERIFY_OPTIONAL
-#endif
-
 #endif /* LWIP_ALTCP */
 
 #endif /* LWIP_HDR_ALTCP_TLS_OPTS_H */
diff --git a/lib/membuff.c b/lib/membuf.c
index b242a38ff1c..f38ff36cb0b 100644
--- a/lib/membuff.c
+++ b/lib/membuf.c
@@ -9,17 +9,17 @@
 #include <errno.h>
 #include <log.h>
 #include <malloc.h>
-#include "membuff.h"
+#include "membuf.h"
 
-void membuff_purge(struct membuff *mb)
+void membuf_purge(struct membuf *mb)
 {
 	/* set mb->head and mb->tail so the buffers look empty */
 	mb->head = mb->start;
 	mb->tail = mb->start;
 }
 
-static int membuff_putrawflex(struct membuff *mb, int maxlen, bool update,
-			      char ***data, int *offsetp)
+static int membuf_putrawflex(struct membuf *mb, int maxlen, bool update,
+			     char ***data, int *offsetp)
 {
 	int len;
 
@@ -72,30 +72,30 @@ static int membuff_putrawflex(struct membuff *mb, int maxlen, bool update,
 	return len;
 }
 
-int membuff_putraw(struct membuff *mb, int maxlen, bool update, char **data)
+int membuf_putraw(struct membuf *mb, int maxlen, bool update, char **data)
 {
 	char **datap;
 	int offset;
 	int size;
 
-	size = membuff_putrawflex(mb, maxlen, update, &datap, &offset);
+	size = membuf_putrawflex(mb, maxlen, update, &datap, &offset);
 	*data = *datap + offset;
 
 	return size;
 }
 
-bool membuff_putbyte(struct membuff *mb, int ch)
+bool membuf_putbyte(struct membuf *mb, int ch)
 {
 	char *data;
 
-	if (membuff_putraw(mb, 1, true, &data) != 1)
+	if (membuf_putraw(mb, 1, true, &data) != 1)
 		return false;
 	*data = ch;
 
 	return true;
 }
 
-int membuff_getraw(struct membuff *mb, int maxlen, bool update, char **data)
+int membuf_getraw(struct membuf *mb, int maxlen, bool update, char **data)
 {
 	int len;
 
@@ -146,21 +146,21 @@ int membuff_getraw(struct membuff *mb, int maxlen, bool update, char **data)
 	return len;
 }
 
-int membuff_getbyte(struct membuff *mb)
+int membuf_getbyte(struct membuf *mb)
 {
 	char *data = 0;
 
-	return membuff_getraw(mb, 1, true, &data) != 1 ? -1 : *(uint8_t *)data;
+	return membuf_getraw(mb, 1, true, &data) != 1 ? -1 : *(uint8_t *)data;
 }
 
-int membuff_peekbyte(struct membuff *mb)
+int membuf_peekbyte(struct membuf *mb)
 {
 	char *data = 0;
 
-	return membuff_getraw(mb, 1, false, &data) != 1 ? -1 : *(uint8_t *)data;
+	return membuf_getraw(mb, 1, false, &data) != 1 ? -1 : *(uint8_t *)data;
 }
 
-int membuff_get(struct membuff *mb, char *buff, int maxlen)
+int membuf_get(struct membuf *mb, char *buff, int maxlen)
 {
 	char *data = 0, *buffptr = buff;
 	int len = 1, i;
@@ -171,7 +171,7 @@ int membuff_get(struct membuff *mb, char *buff, int maxlen)
 	 */
 	for (i = 0; len && i < 2; i++) {
 		/* get a pointer to the data available */
-		len = membuff_getraw(mb, maxlen, true, &data);
+		len = membuf_getraw(mb, maxlen, true, &data);
 
 		/* copy it into the buffer */
 		memcpy(buffptr, data, len);
@@ -183,14 +183,14 @@ int membuff_get(struct membuff *mb, char *buff, int maxlen)
 	return buffptr - buff;
 }
 
-int membuff_put(struct membuff *mb, const char *buff, int length)
+int membuf_put(struct membuf *mb, const char *buff, int length)
 {
 	char *data;
 	int towrite, i, written;
 
 	for (i = written = 0; i < 2; i++) {
 		/* ask where some data can be written */
-		towrite = membuff_putraw(mb, length, true, &data);
+		towrite = membuf_putraw(mb, length, true, &data);
 
 		/* and write it, updating the bytes length */
 		memcpy(data, buff, towrite);
@@ -203,14 +203,14 @@ int membuff_put(struct membuff *mb, const char *buff, int length)
 	return written;
 }
 
-bool membuff_isempty(struct membuff *mb)
+bool membuf_isempty(struct membuf *mb)
 {
 	return mb->head == mb->tail;
 }
 
-int membuff_avail(struct membuff *mb)
+int membuf_avail(struct membuf *mb)
 {
-	struct membuff copy;
+	struct membuf copy;
 	int i, avail;
 	char *data = 0;
 
@@ -219,18 +219,18 @@ int membuff_avail(struct membuff *mb)
 
 	/* now read everything out of the copied buffer */
 	for (i = avail = 0; i < 2; i++)
-		avail += membuff_getraw(&copy, -1, true, &data);
+		avail += membuf_getraw(&copy, -1, true, &data);
 
 	/* and return how much we read */
 	return avail;
 }
 
-int membuff_size(struct membuff *mb)
+int membuf_size(struct membuf *mb)
 {
 	return mb->end - mb->start;
 }
 
-bool membuff_makecontig(struct membuff *mb)
+bool membuf_makecontig(struct membuf *mb)
 {
 	int topsize, botsize;
 
@@ -281,13 +281,14 @@ bool membuff_makecontig(struct membuff *mb)
 	return true;
 }
 
-int membuff_free(struct membuff *mb)
+int membuf_free(struct membuf *mb)
 {
 	return mb->end == mb->start ? 0 :
-			(mb->end - mb->start) - 1 - membuff_avail(mb);
+			(mb->end - mb->start) - 1 - membuf_avail(mb);
 }
 
-int membuff_readline(struct membuff *mb, char *str, int maxlen, int minch, bool must_fit)
+int membuf_readline(struct membuf *mb, char *str, int maxlen, int minch,
+		    bool must_fit)
 {
 	int len;  /* number of bytes read (!= string length) */
 	char *s, *end;
@@ -322,7 +323,7 @@ int membuff_readline(struct membuff *mb, char *str, int maxlen, int minch, bool
 	return len;
 }
 
-int membuff_extend_by(struct membuff *mb, int by, int max)
+int membuf_extend_by(struct membuf *mb, int by, int max)
 {
 	int oldhead, oldtail;
 	int size, orig;
@@ -358,32 +359,32 @@ int membuff_extend_by(struct membuff *mb, int by, int max)
 	return 0;
 }
 
-void membuff_init(struct membuff *mb, char *buff, int size)
+void membuf_init(struct membuf *mb, char *buff, int size)
 {
 	mb->start = buff;
 	mb->end = mb->start + size;
-	membuff_purge(mb);
+	membuf_purge(mb);
 }
 
-int membuff_new(struct membuff *mb, int size)
+int membuf_new(struct membuf *mb, int size)
 {
 	mb->start = malloc(size);
 	if (!mb->start)
 		return -ENOMEM;
 
-	membuff_init(mb, mb->start, size);
+	membuf_init(mb, mb->start, size);
 	return 0;
 }
 
-void membuff_uninit(struct membuff *mb)
+void membuf_uninit(struct membuf *mb)
 {
 	mb->end = NULL;
 	mb->start = NULL;
-	membuff_purge(mb);
+	membuf_purge(mb);
 }
 
-void membuff_dispose(struct membuff *mb)
+void membuf_dispose(struct membuf *mb)
 {
-	free(&mb->start);
-	membuff_uninit(mb);
+	free(mb->start);
+	membuf_uninit(mb);
 }
diff --git a/lib/rsa/rsa-verify.c b/lib/rsa/rsa-verify.c
index d3b4f71d6be..4a0418a75f1 100644
--- a/lib/rsa/rsa-verify.c
+++ b/lib/rsa/rsa-verify.c
@@ -449,6 +449,11 @@ static int rsa_verify_with_keynode(struct image_sign_info *info,
 	}
 
 	algo = fdt_getprop(blob, node, "algo", NULL);
+	if (!algo) {
+		debug("%s: Missing 'algo' property\n", __func__);
+		return -EFAULT;
+	}
+
 	if (strcmp(info->name, algo)) {
 		debug("%s: Wrong algo: have %s, expected %s\n", __func__,
 		      info->name, algo);
@@ -565,6 +570,11 @@ int rsa_verify(struct image_sign_info *info,
 	uint8_t hash[info->crypto->key_len];
 	int ret;
 
+#ifdef USE_HOSTCC
+	if (!info->fdt_blob)
+		return rsa_verify_openssl(info, region, region_count, sig, sig_len);
+#endif
+
 	/*
 	 * Verify that the checksum-length does not exceed the
 	 * rsa-signature-length
diff --git a/lib/smbios.c b/lib/smbios.c
index 78cee8c0c26..7c9701a57f9 100644
--- a/lib/smbios.c
+++ b/lib/smbios.c
@@ -429,6 +429,8 @@ static int smbios_write_type1(ulong *current, int handle,
 	struct smbios_type1 *t;
 	int len = sizeof(*t);
 	char *serial_str = env_get("serial#");
+	size_t uuid_len;
+	void *uuid;
 
 	t = map_sysmem(*current, len);
 	memset(t, 0, len);
@@ -450,6 +452,10 @@ static int smbios_write_type1(ulong *current, int handle,
 						      SYSID_SM_SYSTEM_SERIAL,
 						      NULL);
 	}
+	if (!sysinfo_get_data(ctx->dev, SYSID_SM_SYSTEM_UUID, &uuid,
+			      &uuid_len) &&
+	    uuid_len == sizeof(t->uuid))
+		memcpy(t->uuid, uuid, sizeof(t->uuid));
 	t->wakeup_type = smbios_get_val_si(ctx, "wakeup-type",
 					   SYSID_SM_SYSTEM_WAKEUP,
 					   SMBIOS_WAKEUP_TYPE_UNKNOWN);
diff --git a/lib/tiny-printf.c b/lib/tiny-printf.c
index 0503c17341f..faf55d7f327 100644
--- a/lib/tiny-printf.c
+++ b/lib/tiny-printf.c
@@ -211,6 +211,7 @@ static int _vprintf(struct printf_info *info, const char *fmt, va_list va)
 			bool lz = false;
 			int width = 0;
 			bool islong = false;
+			bool force_char = false;
 
 			ch = *(fmt++);
 			if (ch == '-')
@@ -300,6 +301,8 @@ static int _vprintf(struct printf_info *info, const char *fmt, va_list va)
 				break;
 			case 'c':
 				out(info, (char)(va_arg(va, int)));
+				/* For the case when it's \0 char */
+				force_char = true;
 				break;
 			case 's':
 				p = va_arg(va, char*);
@@ -317,8 +320,10 @@ static int _vprintf(struct printf_info *info, const char *fmt, va_list va)
 			while (width-- > 0)
 				info->putc(info, lz ? '0' : ' ');
 			if (p) {
-				while ((ch = *p++))
+				while ((ch = *p++) || force_char) {
 					info->putc(info, ch);
+					force_char = false;
+				}
 			}
 		}
 	}
diff --git a/net/lwip/Kconfig b/net/lwip/Kconfig
index 40345ced9c9..d28a8a7df94 100644
--- a/net/lwip/Kconfig
+++ b/net/lwip/Kconfig
@@ -10,6 +10,12 @@ config LWIP_DEBUG
 	  Prints messages to the console regarding network packets that go in
           and out of the lwIP library.
 
+config LWIP_DEBUG_RXTX
+	bool "Dump packets sent and received by lwIP"
+	help
+	  Performs an hexadecimal & ASCII dump of the data received and sent by
+	  the lwIP network stack.
+
 config LWIP_ASSERT
 	bool "Enable assertions in the lwIP library"
 	help
diff --git a/net/lwip/Makefile b/net/lwip/Makefile
index 79dd6b3fb50..950c5316bb9 100644
--- a/net/lwip/Makefile
+++ b/net/lwip/Makefile
@@ -6,3 +6,9 @@ obj-$(CONFIG_CMD_DNS) += dns.o
 obj-$(CONFIG_CMD_PING) += ping.o
 obj-$(CONFIG_CMD_TFTPBOOT) += tftp.o
 obj-$(CONFIG_WGET) += wget.o
+
+ifeq (y,$(CONFIG_WGET_BUILTIN_CACERT))
+$(obj)/builtin_cacert.c: $(CONFIG_WGET_BUILTIN_CACERT_PATH:"%"=%) FORCE
+	$(call if_changed,bin2c,builtin_cacert)
+obj-y += builtin_cacert.o
+endif
diff --git a/net/lwip/net-lwip.c b/net/lwip/net-lwip.c
index 4d2aa6099dd..6b7b696dbf0 100644
--- a/net/lwip/net-lwip.c
+++ b/net/lwip/net-lwip.c
@@ -5,6 +5,7 @@
 #include <command.h>
 #include <dm/device.h>
 #include <dm/uclass.h>
+#include <hexdump.h>
 #include <lwip/ip4_addr.h>
 #include <lwip/err.h>
 #include <lwip/netif.h>
@@ -30,12 +31,18 @@ char *pxelinux_configfile;
 struct in_addr	net_ip;
 char net_boot_file_name[1024];
 
-static err_t linkoutput(struct netif *netif, struct pbuf *p)
+static err_t net_lwip_tx(struct netif *netif, struct pbuf *p)
 {
 	struct udevice *udev = netif->state;
 	void *pp = NULL;
 	int err;
 
+	if (CONFIG_IS_ENABLED(LWIP_DEBUG_RXTX)) {
+		printf("net_lwip_tx: %u bytes, udev %s\n", p->len, udev->name);
+		print_hex_dump("net_lwip_tx: ", 0, 16, 1, p->payload, p->len,
+			       true);
+	}
+
 	if ((unsigned long)p->payload % PKTALIGN) {
 		/*
 		 * Some net drivers have strict alignment requirements and may
@@ -60,7 +67,7 @@ static err_t linkoutput(struct netif *netif, struct pbuf *p)
 static err_t net_lwip_if_init(struct netif *netif)
 {
 	netif->output = etharp_output;
-	netif->linkoutput = linkoutput;
+	netif->linkoutput = net_lwip_tx;
 	netif->mtu = 1500;
 	netif->flags = NETIF_FLAG_BROADCAST | NETIF_FLAG_ETHARP | NETIF_FLAG_LINK_UP;
 
@@ -265,6 +272,13 @@ int net_lwip_rx(struct udevice *udev, struct netif *netif)
 		flags = 0;
 
 		if (len > 0) {
+			if (CONFIG_IS_ENABLED(LWIP_DEBUG_RXTX)) {
+				printf("net_lwip_tx: %u bytes, udev %s \n", len,
+				       udev->name);
+				print_hex_dump("net_lwip_rx: ", 0, 16, 1,
+					       packet, len, true);
+			}
+
 			pbuf = alloc_pbuf_and_copy(packet, len);
 			if (pbuf)
 				netif->input(pbuf, netif);
diff --git a/net/lwip/wget.c b/net/lwip/wget.c
index 14f27d42998..ec098148835 100644
--- a/net/lwip/wget.c
+++ b/net/lwip/wget.c
@@ -285,9 +285,96 @@ static err_t httpc_headers_done_cb(httpc_state_t *connection, void *arg, struct
 	return ERR_OK;
 }
 
+#if CONFIG_IS_ENABLED(WGET_HTTPS)
+enum auth_mode {
+	AUTH_NONE,
+	AUTH_OPTIONAL,
+	AUTH_REQUIRED,
+};
+
+static char *cacert;
+static size_t cacert_size;
+static enum auth_mode cacert_auth_mode = AUTH_OPTIONAL;
+#endif
+
+#if CONFIG_IS_ENABLED(WGET_CACERT)
+static int set_auth(enum auth_mode auth)
+{
+	cacert_auth_mode = auth;
+
+	return CMD_RET_SUCCESS;
+}
+#endif
+
+#if CONFIG_IS_ENABLED(WGET_BUILTIN_CACERT)
+extern const char builtin_cacert[];
+extern const size_t builtin_cacert_size;
+static bool cacert_initialized;
+#endif
+
+#if CONFIG_IS_ENABLED(WGET_CACERT) || CONFIG_IS_ENABLED(WGET_BUILTIN_CACERT)
+static int _set_cacert(const void *addr, size_t sz)
+{
+	mbedtls_x509_crt crt;
+	void *p;
+	int ret;
+
+	if (cacert)
+		free(cacert);
+
+	if (!addr) {
+		cacert = NULL;
+		cacert_size = 0;
+		return CMD_RET_SUCCESS;
+	}
+
+	p = malloc(sz);
+	if (!p)
+		return CMD_RET_FAILURE;
+	cacert = p;
+	cacert_size = sz;
+
+	memcpy(cacert, (void *)addr, sz);
+
+	mbedtls_x509_crt_init(&crt);
+	ret = mbedtls_x509_crt_parse(&crt, cacert, cacert_size);
+	if (ret) {
+		printf("Could not parse certificates (%d)\n", ret);
+		free(cacert);
+		cacert = NULL;
+		cacert_size = 0;
+		return CMD_RET_FAILURE;
+	}
+
+#if CONFIG_IS_ENABLED(WGET_BUILTIN_CACERT)
+	cacert_initialized = true;
+#endif
+	return CMD_RET_SUCCESS;
+}
+
+#if CONFIG_IS_ENABLED(WGET_BUILTIN_CACERT)
+static int set_cacert_builtin(void)
+{
+	return _set_cacert(builtin_cacert, builtin_cacert_size);
+}
+#endif
+
+#if CONFIG_IS_ENABLED(WGET_CACERT)
+static int set_cacert(char * const saddr, char * const ssz)
+{
+	ulong addr, sz;
+
+	addr = hextoul(saddr, NULL);
+	sz = hextoul(ssz, NULL);
+
+	return _set_cacert((void *)addr, sz);
+}
+#endif
+#endif  /* CONFIG_WGET_CACERT || CONFIG_WGET_BUILTIN_CACERT */
+
 static int wget_loop(struct udevice *udev, ulong dst_addr, char *uri)
 {
-#if defined CONFIG_WGET_HTTPS
+#if CONFIG_IS_ENABLED(WGET_HTTPS)
 	altcp_allocator_t tls_allocator;
 #endif
 	httpc_connection_t conn;
@@ -312,11 +399,41 @@ static int wget_loop(struct udevice *udev, ulong dst_addr, char *uri)
 		return -1;
 
 	memset(&conn, 0, sizeof(conn));
-#if defined CONFIG_WGET_HTTPS
+#if CONFIG_IS_ENABLED(WGET_HTTPS)
 	if (is_https) {
+		char *ca;
+		size_t ca_sz;
+
+#if CONFIG_IS_ENABLED(WGET_BUILTIN_CACERT)
+		if (!cacert_initialized)
+			set_cacert_builtin();
+#endif
+		ca = cacert;
+		ca_sz = cacert_size;
+
+		if (cacert_auth_mode == AUTH_REQUIRED) {
+			if (!ca || !ca_sz) {
+				printf("Error: cacert authentication mode is "
+				       "'required' but no CA certificates "
+				       "given\n");
+				return CMD_RET_FAILURE;
+		       }
+		} else if (cacert_auth_mode == AUTH_NONE) {
+			ca = NULL;
+			ca_sz = 0;
+		} else if (cacert_auth_mode == AUTH_OPTIONAL) {
+			/*
+			 * Nothing to do, this is the default behavior of
+			 * altcp_tls to check server certificates against CA
+			 * certificates when the latter are provided and proceed
+			 * with no verification if not.
+			 */
+		}
+
 		tls_allocator.alloc = &altcp_tls_alloc;
 		tls_allocator.arg =
-			altcp_tls_create_config_client(NULL, 0, ctx.server_name);
+			altcp_tls_create_config_client(ca, ca_sz,
+						       ctx.server_name);
 
 		if (!tls_allocator.arg) {
 			log_err("error: Cannot create a TLS connection\n");
@@ -369,6 +486,24 @@ int do_wget(struct cmd_tbl *cmdtp, int flag, int argc, char * const argv[])
 	ulong dst_addr;
 	char nurl[1024];
 
+#if CONFIG_IS_ENABLED(WGET_CACERT)
+	if (argc == 4 && !strncmp(argv[1], "cacert", strlen("cacert")))
+		return set_cacert(argv[2], argv[3]);
+	if (argc == 3 && !strncmp(argv[1], "cacert", strlen("cacert"))) {
+#if CONFIG_IS_ENABLED(WGET_BUILTIN_CACERT)
+		if (!strncmp(argv[2], "builtin", strlen("builtin")))
+			return set_cacert_builtin();
+#endif
+		if (!strncmp(argv[2], "none", strlen("none")))
+			return set_auth(AUTH_NONE);
+		if (!strncmp(argv[2], "optional", strlen("optional")))
+			return set_auth(AUTH_OPTIONAL);
+		if (!strncmp(argv[2], "required", strlen("required")))
+			return set_auth(AUTH_REQUIRED);
+		return CMD_RET_USAGE;
+	}
+#endif
+
 	if (argc < 2 || argc > 3)
 		return CMD_RET_USAGE;
 
diff --git a/scripts/Makefile.extrawarn b/scripts/Makefile.extrawarn
index 7d39b27d24a..f687515fc79 100644
--- a/scripts/Makefile.extrawarn
+++ b/scripts/Makefile.extrawarn
@@ -13,6 +13,9 @@
 
 KBUILD_CFLAGS += $(call cc-disable-warning, packed-not-aligned)
 
+KBUILD_CPPFLAGS-$(CONFIG_WERROR) += -Werror
+KBUILD_CPPFLAGS += $(KBUILD_CPPFLAGS-y)
+
 ifeq ("$(origin W)", "command line")
   export KBUILD_ENABLE_EXTRA_GCC_CHECKS := $(W)
 endif
diff --git a/test/Kconfig b/test/Kconfig
index 558a9cd49b4..31016eedbf8 100644
--- a/test/Kconfig
+++ b/test/Kconfig
@@ -20,9 +20,18 @@ config SPL_UNIT_TEST
 	  of-platdata and SPL handover. To run these tests with the sandbox_spl
 	  board, use the -u (unit test) option.
 
+if UNIT_TEST
+
+config UNIT_TEST_DURATION
+	bool "Report unit-test duration"
+	default y
+	help
+	  Enable this short the time taken by each test suite. This is reported
+	  after the suite runs, alongside the pass/fail results. In addition,
+	  an overall total is reported if multiple suites are run.
+
 config UT_LIB
 	bool "Unit tests for library functions"
-	depends on UNIT_TEST
 	default y if !SANDBOX_VPL
 	help
 	  Enables the 'ut lib' command which tests library functions like
@@ -63,16 +72,15 @@ config UT_LIB_RSA
 	  Enables rsa_verify() test, currently rsa_verify_with_pkey only()
 	  only, at the 'ut lib' command.
 
-endif
+endif  # UT_LIB
 
 config UT_BOOTSTD
 	bool "Unit tests for standard boot"
-	depends on UNIT_TEST && BOOTSTD && SANDBOX
+	depends on BOOTSTD && SANDBOX
 	default y
 
 config UT_COMPRESSION
 	bool "Unit test for compression"
-	depends on UNIT_TEST
 	depends on CMDLINE && GZIP_COMPRESSED && BZIP2 && LZMA && LZO && LZ4 && ZSTD
 	default y
 	help
@@ -81,7 +89,6 @@ config UT_COMPRESSION
 
 config UT_LOG
 	bool "Unit tests for logging functions"
-	depends on UNIT_TEST
 	default y
 	help
 	  Enables the 'ut log' command which tests logging functions like
@@ -90,7 +97,6 @@ config UT_LOG
 
 config UT_TIME
 	bool "Unit tests for time functions"
-	depends on UNIT_TEST
 	help
 	  Enables the 'ut time' command which tests that the time functions
 	  work correctly. The test is fairly simple and will not catch all
@@ -99,7 +105,6 @@ config UT_TIME
 
 config UT_UNICODE
 	bool "Unit tests for Unicode functions"
-	depends on UNIT_TEST
 	default y
 	select CHARSET
 	help
@@ -111,7 +116,9 @@ source "test/env/Kconfig"
 source "test/image/Kconfig"
 source "test/lib/Kconfig"
 source "test/optee/Kconfig"
-source "test/overlay/Kconfig"
+source "test/fdt_overlay/Kconfig"
+
+endif  # UNIT_TEST
 
 config POST
 	bool "Power On Self Test support"
diff --git a/test/Makefile b/test/Makefile
index 47a07d653a9..99d4797d968 100644
--- a/test/Makefile
+++ b/test/Makefile
@@ -14,11 +14,14 @@ endif
 ifneq ($(CONFIG_HUSH_PARSER),)
 obj-$(CONFIG_$(XPL_)CMDLINE) += hush/
 endif
+obj-$(CONFIG_UT_OPTEE) += optee/
 obj-y += ut.o
 
 ifeq ($(CONFIG_XPL_BUILD),)
 obj-y += boot/
 obj-$(CONFIG_UNIT_TEST) += common/
+obj-$(CONFIG_UT_ENV) += env/
+obj-$(CONFIG_UT_FDT_OVERLAY) += fdt_overlay/
 obj-y += log/
 else
 obj-$(CONFIG_SPL_UT_LOAD) += image/
diff --git a/test/boot/bootdev.c b/test/boot/bootdev.c
index 8c44afd9297..d5499918249 100644
--- a/test/boot/bootdev.c
+++ b/test/boot/bootdev.c
@@ -12,7 +12,6 @@
 #include <bootflow.h>
 #include <mapmem.h>
 #include <os.h>
-#include <test/suites.h>
 #include <test/ut.h>
 #include "bootstd_common.h"
 
@@ -510,6 +509,7 @@ static int bootdev_test_bootable(struct unit_test_state *uts)
 	iter.part = 0;
 	ut_assertok(uclass_get_device_by_name(UCLASS_BLK, "mmc1.blk", &blk));
 	iter.dev = blk;
+	iter.flags = BOOTFLOWIF_ONLY_BOOTABLE;
 	ut_assertok(device_find_next_child(&iter.dev));
 	uclass_first_device(UCLASS_BOOTMETH, &bflow.method);
 
diff --git a/test/boot/bootflow.c b/test/boot/bootflow.c
index a8735c1c23d..5f9c037ff53 100644
--- a/test/boot/bootflow.c
+++ b/test/boot/bootflow.c
@@ -21,7 +21,6 @@
 #endif
 #include <dm/device-internal.h>
 #include <dm/lists.h>
-#include <test/suites.h>
 #include <test/ut.h>
 #include "bootstd_common.h"
 #include "../../boot/bootflow_internal.h"
@@ -298,8 +297,9 @@ static int bootflow_iter(struct unit_test_state *uts)
 
 	/* The first device is mmc2.bootdev which has no media */
 	ut_asserteq(-EPROTONOSUPPORT,
-		    bootflow_scan_first(NULL, NULL, &iter,
-					BOOTFLOWIF_ALL | BOOTFLOWIF_SKIP_GLOBAL, &bflow));
+		    bootflow_scan_first(NULL, NULL, &iter, BOOTFLOWIF_ALL |
+					BOOTFLOWIF_SKIP_GLOBAL |
+					BOOTFLOWIF_ONLY_BOOTABLE, &bflow));
 	ut_asserteq(2, iter.num_methods);
 	ut_asserteq(0, iter.cur_method);
 	ut_asserteq(0, iter.part);
diff --git a/test/boot/bootm.c b/test/boot/bootm.c
index 7e0ccb0e23f..1d1efe71ad5 100644
--- a/test/boot/bootm.c
+++ b/test/boot/bootm.c
@@ -7,7 +7,6 @@
 
 #include <bootm.h>
 #include <asm/global_data.h>
-#include <test/suites.h>
 #include <test/test.h>
 #include <test/ut.h>
 
diff --git a/test/boot/bootmeth.c b/test/boot/bootmeth.c
index 18ae6d7fe13..577f259fb37 100644
--- a/test/boot/bootmeth.c
+++ b/test/boot/bootmeth.c
@@ -9,7 +9,6 @@
 #include <bootmeth.h>
 #include <bootstd.h>
 #include <dm.h>
-#include <test/suites.h>
 #include <test/ut.h>
 #include "bootstd_common.h"
 
diff --git a/test/boot/bootstd_common.c b/test/boot/bootstd_common.c
index 724e3d9bdd2..052c0fe5cc6 100644
--- a/test/boot/bootstd_common.c
+++ b/test/boot/bootstd_common.c
@@ -13,7 +13,6 @@
 #include <mmc.h>
 #include <usb.h>
 #include <linux/log2.h>
-#include <test/suites.h>
 #include <test/ut.h>
 #include <u-boot/crc.h>
 #include "bootstd_common.h"
@@ -21,8 +20,14 @@
 /* tracks whether bootstd_setup_for_tests() has been run yet */
 bool vbe_setup_done;
 
-/* set up MMC for VBE tests */
-int bootstd_setup_for_tests(void)
+/**
+ * bootstd_setup_for_tests() - Set up MMC data for VBE tests
+ *
+ * Some data is needed for VBE tests to work. This function sets that up.
+ *
+ * @return 0 if OK, -ve on error
+ */
+static int bootstd_setup_for_tests(struct unit_test_state *uts)
 {
 	ALLOC_CACHE_ALIGN_BUFFER(u8, buf, MMC_MAX_BLOCK_LEN);
 	struct udevice *mmc;
@@ -55,6 +60,7 @@ int bootstd_setup_for_tests(void)
 
 	return 0;
 }
+BOOTSTD_TEST_INIT(bootstd_setup_for_tests, 0);
 
 int bootstd_test_drop_bootdev_order(struct unit_test_state *uts)
 {
@@ -93,20 +99,3 @@ void bootstd_reset_usb(void)
 {
 	usb_started = false;
 }
-
-int do_ut_bootstd(struct unit_test_state *uts, struct cmd_tbl *cmdtp, int flag,
-		  int argc, char *const argv[])
-{
-	struct unit_test *tests = UNIT_TEST_SUITE_START(bootstd);
-	const int n_ents = UNIT_TEST_SUITE_COUNT(bootstd);
-	int ret;
-
-	ret = bootstd_setup_for_tests();
-	if (ret) {
-		printf("Failed to set up for bootstd tests (err=%d)\n", ret);
-		return CMD_RET_FAILURE;
-	}
-
-	return cmd_ut_category(uts, "bootstd", "bootstd_",
-			       tests, n_ents, argc, argv);
-}
diff --git a/test/boot/bootstd_common.h b/test/boot/bootstd_common.h
index ea3ecd1166c..c61698adc02 100644
--- a/test/boot/bootstd_common.h
+++ b/test/boot/bootstd_common.h
@@ -13,6 +13,7 @@
 
 /* Declare a new bootdev test */
 #define BOOTSTD_TEST(_name, _flags)	UNIT_TEST(_name, _flags, bootstd)
+#define BOOTSTD_TEST_INIT(_name, _flags) UNIT_TEST_INIT(_name, _flags, bootstd)
 
 #define NVDATA_START_BLK	((0x400 + 0x400) / MMC_MAX_BLOCK_LEN)
 #define VERSION_START_BLK	((0x400 + 0x800) / MMC_MAX_BLOCK_LEN)
@@ -36,15 +37,6 @@ struct unit_test_state;
 int bootstd_test_drop_bootdev_order(struct unit_test_state *uts);
 
 /**
- * bootstd_setup_for_tests() - Set up MMC data for VBE tests
- *
- * Some data is needed for VBE tests to work. This function sets that up.
- *
- * @return 0 if OK, -ve on error
- */
-int bootstd_setup_for_tests(void);
-
-/**
  * bootstd_test_check_mmc_hunter() - Check that the mmc bootdev hunter was used
  *
  * @uts: Unit test state to use for ut_assert...() functions
diff --git a/test/boot/expo.c b/test/boot/expo.c
index db14ff86f8b..1d283a2ac95 100644
--- a/test/boot/expo.c
+++ b/test/boot/expo.c
@@ -10,7 +10,6 @@
 #include <menu.h>
 #include <video.h>
 #include <linux/input.h>
-#include <test/suites.h>
 #include <test/ut.h>
 #include "bootstd_common.h"
 #include <test/cedit-test.h>
diff --git a/test/boot/image.c b/test/boot/image.c
index 0894e30587f..4df7b17ce88 100644
--- a/test/boot/image.c
+++ b/test/boot/image.c
@@ -7,7 +7,6 @@
  */
 
 #include <image.h>
-#include <test/suites.h>
 #include <test/ut.h>
 #include "bootstd_common.h"
 
diff --git a/test/boot/measurement.c b/test/boot/measurement.c
index 5a49c7a6b23..1d38663fc0f 100644
--- a/test/boot/measurement.c
+++ b/test/boot/measurement.c
@@ -8,7 +8,6 @@
 
 #include <bootm.h>
 #include <malloc.h>
-#include <test/suites.h>
 #include <test/test.h>
 #include <test/ut.h>
 #include <asm/io.h>
diff --git a/test/boot/upl.c b/test/boot/upl.c
index aa58cdf083b..eec89026fc3 100644
--- a/test/boot/upl.c
+++ b/test/boot/upl.c
@@ -10,7 +10,6 @@
 #include <mapmem.h>
 #include <upl.h>
 #include <dm/ofnode.h>
-#include <test/suites.h>
 #include <test/test.h>
 #include <test/ut.h>
 #include "bootstd_common.h"
diff --git a/test/boot/vbe_simple.c b/test/boot/vbe_simple.c
index 4fe4323b401..c37de627c52 100644
--- a/test/boot/vbe_simple.c
+++ b/test/boot/vbe_simple.c
@@ -11,7 +11,6 @@
 #include <image.h>
 #include <of_live.h>
 #include <vbe.h>
-#include <test/suites.h>
 #include <test/ut.h>
 #include "bootstd_common.h"
 
@@ -33,9 +32,6 @@ static int vbe_simple_test_base(struct unit_test_state *uts)
 	ofnode node;
 	u32 vernum;
 
-	/* Set up the VBE info */
-	ut_assertok(bootstd_setup_for_tests());
-
 	/* Read the version back */
 	ut_assertok(vbe_find_by_any("firmware0", &dev));
 	ut_assertok(bootmeth_get_state_desc(dev, info, sizeof(info)));
diff --git a/test/cmd/addrmap.c b/test/cmd/addrmap.c
index 1f2deb15052..72798b96edd 100644
--- a/test/cmd/addrmap.c
+++ b/test/cmd/addrmap.c
@@ -6,7 +6,6 @@
  */
 
 #include <console.h>
-#include <test/suites.h>
 #include <test/ut.h>
 
 /* Declare a new addrmap test */
diff --git a/test/cmd/bdinfo.c b/test/cmd/bdinfo.c
index 7408c271a30..09f44ee41ed 100644
--- a/test/cmd/bdinfo.c
+++ b/test/cmd/bdinfo.c
@@ -10,7 +10,6 @@
 #include <mapmem.h>
 #include <asm/global_data.h>
 #include <dm/uclass.h>
-#include <test/suites.h>
 #include <test/ut.h>
 #include <dm.h>
 #include <env.h>
diff --git a/test/cmd/exit.c b/test/cmd/exit.c
index 71c37edcdf6..fdde054b928 100644
--- a/test/cmd/exit.c
+++ b/test/cmd/exit.c
@@ -8,7 +8,6 @@
 #include <console.h>
 #include <mapmem.h>
 #include <asm/global_data.h>
-#include <test/suites.h>
 #include <test/ut.h>
 
 DECLARE_GLOBAL_DATA_PTR;
diff --git a/test/cmd/fdt.c b/test/cmd/fdt.c
index ab6dbd45e54..c11c181c807 100644
--- a/test/cmd/fdt.c
+++ b/test/cmd/fdt.c
@@ -10,7 +10,6 @@
 #include <mapmem.h>
 #include <asm/global_data.h>
 #include <linux/libfdt.h>
-#include <test/suites.h>
 #include <test/ut.h>
 
 DECLARE_GLOBAL_DATA_PTR;
diff --git a/test/cmd/font.c b/test/cmd/font.c
index af88d1b5459..7ae648d7395 100644
--- a/test/cmd/font.c
+++ b/test/cmd/font.c
@@ -8,7 +8,6 @@
 #include <console.h>
 #include <dm.h>
 #include <video_console.h>
-#include <test/suites.h>
 #include <test/ut.h>
 
 /* Declare a new fdt test */
diff --git a/test/cmd/loadm.c b/test/cmd/loadm.c
index 3c623aa655f..043cd25dfb6 100644
--- a/test/cmd/loadm.c
+++ b/test/cmd/loadm.c
@@ -13,7 +13,6 @@
 #include <mapmem.h>
 #include <asm/global_data.h>
 #include <dm/test.h>
-#include <test/suites.h>
 #include <test/test.h>
 #include <test/ut.h>
 
diff --git a/test/cmd/mbr.c b/test/cmd/mbr.c
index 45bab04923a..e651256a4cb 100644
--- a/test/cmd/mbr.c
+++ b/test/cmd/mbr.c
@@ -15,7 +15,6 @@
 #include <dm/device-internal.h>
 #include <dm/lists.h>
 #include <linux/sizes.h>
-#include <test/suites.h>
 #include <test/ut.h>
 
 DECLARE_GLOBAL_DATA_PTR;
diff --git a/test/cmd/pci_mps.c b/test/cmd/pci_mps.c
index 8b3ea4a6134..6618c247d13 100644
--- a/test/cmd/pci_mps.c
+++ b/test/cmd/pci_mps.c
@@ -8,7 +8,6 @@
  */
 
 #include <console.h>
-#include <test/suites.h>
 #include <test/ut.h>
 
 #define PCI_MPS_TEST(_name, _flags) UNIT_TEST(_name, _flags, pci_mps)
diff --git a/test/cmd/seama.c b/test/cmd/seama.c
index 1edc3fcac5a..39f85f1c502 100644
--- a/test/cmd/seama.c
+++ b/test/cmd/seama.c
@@ -7,7 +7,6 @@
 
 #include <command.h>
 #include <dm.h>
-#include <test/suites.h>
 #include <test/test.h>
 #include <test/ut.h>
 
diff --git a/test/cmd/setexpr.c b/test/cmd/setexpr.c
index 5e9b577fe36..85803eb54b8 100644
--- a/test/cmd/setexpr.c
+++ b/test/cmd/setexpr.c
@@ -9,7 +9,6 @@
 #include <console.h>
 #include <mapmem.h>
 #include <dm/test.h>
-#include <test/suites.h>
 #include <test/ut.h>
 
 #define BUF_SIZE	0x100
diff --git a/test/cmd_ut.c b/test/cmd_ut.c
index fbfdaaae0b5..44e5fdfdaa6 100644
--- a/test/cmd_ut.c
+++ b/test/cmd_ut.c
@@ -7,7 +7,6 @@
 #include <command.h>
 #include <console.h>
 #include <vsprintf.h>
-#include <test/suites.h>
 #include <test/test.h>
 #include <test/ut.h>
 
@@ -20,77 +19,31 @@
  * @name: Name of suite
  * @start: First test in suite
  * @end: End test in suite (points to the first test in the next suite)
- * @cmd: Command to use to run the suite
  * @help: Help-string to show for this suite
  */
 struct suite {
 	const char *name;
 	struct unit_test *start;
 	struct unit_test *end;
-	ut_cmd_func cmd;
 	const char *help;
 };
 
-static int do_ut_all(struct unit_test_state *uts, struct cmd_tbl *cmdtp,
-		     int flag, int argc, char *const argv[]);
+static int do_ut_all(struct unit_test_state *uts, const char *select_name,
+		     int runs_per_test, bool force_run,
+		     const char *test_insert);
 
-static int do_ut_info(struct cmd_tbl *cmdtp, int flag, int argc,
-		      char *const argv[]);
-
-int cmd_ut_category(struct unit_test_state *uts, const char *name,
-		    const char *prefix, struct unit_test *tests, int n_ents,
-		    int argc, char *const argv[])
-{
-	const char *test_insert = NULL;
-	int runs_per_text = 1;
-	bool force_run = false;
-	int ret;
-
-	while (argc > 1 && *argv[1] == '-') {
-		const char *str = argv[1];
-
-		switch (str[1]) {
-		case 'r':
-			runs_per_text = dectoul(str + 2, NULL);
-			break;
-		case 'f':
-			force_run = true;
-			break;
-		case 'I':
-			test_insert = str + 2;
-			break;
-		}
-		argv++;
-		argc--;
-	}
-
-	ret = ut_run_list(uts, name, prefix, tests, n_ents,
-			  cmd_arg1(argc, argv), runs_per_text, force_run,
-			  test_insert);
-
-	return ret ? CMD_RET_FAILURE : 0;
-}
+static int do_ut_info(bool show_suites);
 
 /* declare linker-list symbols for the start and end of a suite */
 #define SUITE_DECL(_name) \
 	ll_start_decl(suite_start_ ## _name, struct unit_test, ut_ ## _name); \
 	ll_end_decl(suite_end_ ## _name, struct unit_test, ut_ ## _name)
 
-/* declare a test suite which uses a subcommand to run */
-#define SUITE_CMD(_name, _cmd_func, _help) { \
-	#_name, \
-	suite_start_ ## _name, \
-	suite_end_ ## _name, \
-	_cmd_func, \
-	_help, \
-	}
-
 /* declare a test suite which can be run directly without a subcommand */
 #define SUITE(_name, _help) { \
 	#_name, \
 	suite_start_ ## _name, \
 	suite_end_ ## _name, \
-	NULL, \
 	_help, \
 	}
 
@@ -105,6 +58,7 @@ SUITE_DECL(dm);
 SUITE_DECL(env);
 SUITE_DECL(exit);
 SUITE_DECL(fdt);
+SUITE_DECL(fdt_overlay);
 SUITE_DECL(font);
 SUITE_DECL(hush);
 SUITE_DECL(lib);
@@ -114,7 +68,6 @@ SUITE_DECL(mbr);
 SUITE_DECL(measurement);
 SUITE_DECL(mem);
 SUITE_DECL(optee);
-SUITE_DECL(overlay);
 SUITE_DECL(pci_mps);
 SUITE_DECL(seama);
 SUITE_DECL(setexpr);
@@ -125,15 +78,14 @@ static struct suite suites[] = {
 	SUITE(bdinfo, "bdinfo (board info) command"),
 	SUITE(bloblist, "bloblist implementation"),
 	SUITE(bootm, "bootm command"),
-#ifdef CONFIG_UT_BOOTSTD
-	SUITE_CMD(bootstd, do_ut_bootstd, "standard boot implementation"),
-#endif
+	SUITE(bootstd, "standard boot implementation"),
 	SUITE(cmd, "various commands"),
 	SUITE(common, "tests for common/ directory"),
 	SUITE(dm, "driver model"),
 	SUITE(env, "environment"),
 	SUITE(exit, "shell exit and variables"),
 	SUITE(fdt, "fdt command"),
+	SUITE(fdt_overlay, "device tree overlays"),
 	SUITE(font, "font command"),
 	SUITE(hush, "hush behaviour"),
 	SUITE(lib, "library functions"),
@@ -142,12 +94,7 @@ static struct suite suites[] = {
 	SUITE(mbr, "mbr command"),
 	SUITE(measurement, "TPM-based measured boot"),
 	SUITE(mem, "memory-related commands"),
-#ifdef CONFIG_UT_OPTEE
-	SUITE_CMD(optee, do_ut_optee, "OP-TEE"),
-#endif
-#ifdef CONFIG_UT_OVERLAY
-	SUITE_CMD(overlay, do_ut_overlay, "device tree overlays"),
-#endif
+	SUITE(optee, "OP-TEE"),
 	SUITE(pci_mps, "PCI Express Maximum Payload Size"),
 	SUITE(seama, "seama command parameters loading and decoding"),
 	SUITE(setexpr, "setexpr command"),
@@ -167,33 +114,59 @@ static bool has_tests(struct suite *ste)
 {
 	int n_ents = ste->end - ste->start;
 
-	return n_ents || ste->cmd;
+	return n_ents;
 }
 
 /** run_suite() - Run a suite of tests */
 static int run_suite(struct unit_test_state *uts, struct suite *ste,
-		     struct cmd_tbl *cmdtp, int flag, int argc,
-		     char *const argv[])
+		     const char *select_name, int runs_per_test, bool force_run,
+		     const char *test_insert)
 {
+	int n_ents = ste->end - ste->start;
+	char prefix[30];
 	int ret;
 
-	if (ste->cmd) {
-		ret = ste->cmd(uts, cmdtp, flag, argc, argv);
-	} else {
-		int n_ents = ste->end - ste->start;
-		char prefix[30];
+	/* use a standard prefix */
+	snprintf(prefix, sizeof(prefix), "%s_test_", ste->name);
 
-		/* use a standard prefix */
-		snprintf(prefix, sizeof(prefix), "%s_test", ste->name);
-		ret = cmd_ut_category(uts, ste->name, prefix, ste->start,
-				      n_ents, argc, argv);
-	}
+	ret = ut_run_list(uts, ste->name, prefix, ste->start, n_ents,
+			  select_name, runs_per_test, force_run, test_insert);
 
 	return ret;
 }
 
-static int do_ut_all(struct unit_test_state *uts, struct cmd_tbl *cmdtp,
-		     int flag, int argc, char *const argv[])
+static void show_stats(struct unit_test_state *uts)
+{
+	if (uts->run_count < 2)
+		return;
+
+	ut_report(&uts->total, uts->run_count);
+	if (CONFIG_IS_ENABLED(UNIT_TEST_DURATION) &&
+	    uts->total.test_count && uts->worst) {
+		ulong avg = uts->total.duration_ms / uts->total.test_count;
+
+		printf("Average test time: %ld ms, worst case '%s' took %d ms\n",
+		       avg, uts->worst->name, uts->worst_ms);
+	}
+}
+
+static void update_stats(struct unit_test_state *uts, const struct suite *ste)
+{
+	if (CONFIG_IS_ENABLED(UNIT_TEST_DURATION) && uts->cur.test_count) {
+		ulong avg;
+
+		avg = uts->cur.duration_ms ?
+			uts->cur.duration_ms /
+			uts->cur.test_count : 0;
+		if (avg > uts->worst_ms) {
+			uts->worst_ms = avg;
+			uts->worst = ste;
+		}
+	}
+}
+
+static int do_ut_all(struct unit_test_state *uts, const char *select_name,
+		     int runs_per_test, bool force_run, const char *test_insert)
 {
 	int i;
 	int retval;
@@ -201,25 +174,23 @@ static int do_ut_all(struct unit_test_state *uts, struct cmd_tbl *cmdtp,
 
 	for (i = 0; i < ARRAY_SIZE(suites); i++) {
 		struct suite *ste = &suites[i];
-		char *const argv[] = {(char *)ste->name, NULL};
 
 		if (has_tests(ste)) {
 			printf("----Running %s tests----\n", ste->name);
-			retval = run_suite(uts, ste, cmdtp, flag, 1, argv);
+			retval = run_suite(uts, ste, select_name, runs_per_test,
+					   force_run, test_insert);
 			if (!any_fail)
 				any_fail = retval;
+			update_stats(uts, ste);
 		}
 	}
-	ut_report(&uts->total, uts->run_count);
 
 	return any_fail;
 }
 
-static int do_ut_info(struct cmd_tbl *cmdtp, int flag, int argc,
-		      char *const argv[])
+static int do_ut_info(bool show_suites)
 {
 	int suite_count, i;
-	const char *flags;
 
 	for (suite_count = 0, i = 0; i < ARRAY_SIZE(suites); i++) {
 		struct suite *ste = &suites[i];
@@ -231,24 +202,26 @@ static int do_ut_info(struct cmd_tbl *cmdtp, int flag, int argc,
 	printf("Test suites: %d\n", suite_count);
 	printf("Total tests: %d\n", (int)UNIT_TEST_ALL_COUNT());
 
-	flags = cmd_arg1(argc, argv);
-	if (flags && !strcmp("-s", flags)) {
-		int i;
+	if (show_suites) {
+		int i, total;
 
 		puts("\nTests  Suite         Purpose");
 		puts("\n-----  ------------  -------------------------\n");
-		for (i = 0; i < ARRAY_SIZE(suites); i++) {
+		for (i = 0, total = 0; i < ARRAY_SIZE(suites); i++) {
 			struct suite *ste = &suites[i];
 			long n_ent = ste->end - ste->start;
 
-			if (n_ent)
-				printf("%5ld", n_ent);
-			else if (ste->cmd)
-				printf("%5s", "?");
-			else  /* suite is not present */
-				continue;
-			printf("  %-13.13s %s\n", ste->name, ste->help);
+			if (n_ent) {
+				printf("%5ld  %-13.13s %s\n", n_ent, ste->name,
+				       ste->help);
+				total += n_ent;
+			}
 		}
+		puts("-----  ------------  -------------------------\n");
+		printf("%5d  %-13.13s\n", total, "Total");
+
+		if (UNIT_TEST_ALL_COUNT() != total)
+			puts("Error: Suite test-count does not match total\n");
 	}
 
 	return 0;
@@ -269,37 +242,77 @@ static struct suite *find_suite(const char *name)
 
 static int do_ut(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
 {
+	const char *test_insert = NULL, *select_name;
 	struct unit_test_state uts;
+	bool show_suites = false;
+	bool force_run = false;
+	int runs_per_text = 1;
 	struct suite *ste;
-	const char *name;
+	char *name;
 	int ret;
 
-	if (argc < 2)
-		return CMD_RET_USAGE;
-
 	/* drop initial "ut" arg */
 	argc--;
 	argv++;
 
+	while (argc > 0 && *argv[0] == '-') {
+		const char *str = argv[0];
+
+		switch (str[1]) {
+		case 'r':
+			runs_per_text = dectoul(str + 2, NULL);
+			break;
+		case 'f':
+			force_run = true;
+			break;
+		case 'I':
+			test_insert = str + 2;
+			if (!strchr(test_insert, ':'))
+				return CMD_RET_USAGE;
+			break;
+		case 's':
+			show_suites = true;
+			break;
+		}
+		argv++;
+		argc--;
+	}
+
+	if (argc < 1)
+		return CMD_RET_USAGE;
+
 	ut_init_state(&uts);
 	name = argv[0];
+	select_name = cmd_arg1(argc, argv);
 	if (!strcmp(name, "all")) {
-		ret = do_ut_all(&uts, cmdtp, flag, argc, argv);
+		ret = do_ut_all(&uts, select_name, runs_per_text, force_run,
+				test_insert);
 	} else if (!strcmp(name, "info")) {
-		ret = do_ut_info(cmdtp, flag, argc, argv);
+		ret = do_ut_info(show_suites);
 	} else {
-		ste = find_suite(argv[0]);
-		if (!ste) {
-			printf("Suite '%s' not found\n", argv[0]);
-			return CMD_RET_FAILURE;
-		} else if (!has_tests(ste)) {
-			/* perhaps a Kconfig option needs to be set? */
-			printf("Suite '%s' is not enabled\n", argv[0]);
-			return CMD_RET_FAILURE;
+		int any_fail = 0;
+		const char *p;
+
+		for (; p = strsep(&name, ","), p; name = NULL) {
+			ste = find_suite(p);
+			if (!ste) {
+				printf("Suite '%s' not found\n", p);
+				return CMD_RET_FAILURE;
+			} else if (!has_tests(ste)) {
+				/* perhaps a Kconfig option needs to be set? */
+				printf("Suite '%s' is not enabled\n", p);
+				return CMD_RET_FAILURE;
+			}
+
+			ret = run_suite(&uts, ste, select_name, runs_per_text,
+					force_run, test_insert);
+			if (!any_fail)
+				any_fail = ret;
+			update_stats(&uts, ste);
 		}
-
-		ret = run_suite(&uts, ste, cmdtp, flag, argc, argv);
+		ret = any_fail;
 	}
+	show_stats(&uts);
 	if (ret)
 		return ret;
 	ut_uninit_state(&uts);
@@ -308,14 +321,16 @@ static int do_ut(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
 }
 
 U_BOOT_LONGHELP(ut,
-	"[-r] [-f] [<suite>] - run unit tests\n"
+	"[-rs] [-f] [-I<n>:<one_test>][<suites>] - run unit tests\n"
 	"   -r<runs>   Number of times to run each test\n"
 	"   -f         Force 'manual' tests to run as well\n"
-	"   <suite>    Test suite to run, or all\n"
+	"   -I         Test to run after <n> other tests have run\n"
+	"   -s         Show all suites with ut info\n"
+	"   <suites>   Comma-separated list of suites to run\n"
 	"\n"
-	"\nOptions for <suite>:"
-	"\nall - execute all enabled tests"
-	"\ninfo [-s] - show info about tests [and suites]"
+	"Options for <suite>:\n"
+	"all       - execute all enabled tests\n"
+	"info      - show info about tests [and suites]"
 	);
 
 U_BOOT_CMD(
diff --git a/test/common/bloblist.c b/test/common/bloblist.c
index ab8f41c6808..797bde27025 100644
--- a/test/common/bloblist.c
+++ b/test/common/bloblist.c
@@ -6,7 +6,6 @@
 #include <bloblist.h>
 #include <log.h>
 #include <mapmem.h>
-#include <test/suites.h>
 #include <test/test.h>
 #include <test/ut.h>
 
diff --git a/test/common/event.c b/test/common/event.c
index bfbbf019768..e77e020b00b 100644
--- a/test/common/event.c
+++ b/test/common/event.c
@@ -91,7 +91,7 @@ static int test_event_probe(struct unit_test_state *uts)
 	struct test_state state;
 	struct udevice *dev;
 
-	if (!IS_ENABLED(SANDBOX))
+	if (!IS_ENABLED(CONFIG_SANDBOX))
 		return -EAGAIN;
 
 	state.val = 0;
diff --git a/test/dm/Kconfig b/test/dm/Kconfig
index e5b341e523a..640421c2a79 100644
--- a/test/dm/Kconfig
+++ b/test/dm/Kconfig
@@ -1,6 +1,6 @@
 config UT_DM
 	bool "Enable driver model unit test command"
-	depends on SANDBOX && UNIT_TEST
+	depends on SANDBOX
 	help
 	  This enables the 'ut dm' command which runs a series of unit
 	  tests on the driver model code. Each subsystem (uclass) is tested.
diff --git a/test/dm/Makefile b/test/dm/Makefile
index e44f3d89e77..3afcc26ca57 100644
--- a/test/dm/Makefile
+++ b/test/dm/Makefile
@@ -63,6 +63,7 @@ obj-$(CONFIG_SOUND) += i2s.o
 obj-$(CONFIG_CLK_K210_SET_RATE) += k210_pll.o
 obj-$(CONFIG_IOMMU) += iommu.o
 obj-$(CONFIG_LED) += led.o
+obj-$(CONFIG_VIDEO_BRIDGE_LVDS_CODEC) += video_bridge.o
 obj-$(CONFIG_DM_MAILBOX) += mailbox.o
 obj-$(CONFIG_DM_MDIO) += mdio.o
 obj-$(CONFIG_DM_MDIO_MUX) += mdio_mux.o
diff --git a/test/dm/acpi.c b/test/dm/acpi.c
index 39a26bbb492..db012b6d2f1 100644
--- a/test/dm/acpi.c
+++ b/test/dm/acpi.c
@@ -309,6 +309,8 @@ static int dm_test_acpi_write_tables(struct unit_test_state *uts)
 	}
 	ut_asserteq(0, ctx.rsdt->entry[3]);
 	ut_asserteq(0, ctx.xsdt->entry[3]);
+	unmap_sysmem(buf);
+	free(buf);
 
 	return 0;
 }
@@ -386,6 +388,8 @@ static int dm_test_acpi_ctx_and_base_tables(struct unit_test_state *uts)
 
 	ut_asserteq(nomap_to_sysmem(rsdt), rsdp->rsdt_address);
 	ut_asserteq(nomap_to_sysmem(xsdt), rsdp->xsdt_address);
+	unmap_sysmem(buf);
+	free(buf);
 
 	return 0;
 }
@@ -428,11 +432,59 @@ static int dm_test_acpi_cmd_list(struct unit_test_state *uts)
 	ut_assert_nextline("DMAR  %16lx  %5zx  v01 U-BOOT U-BOOTBL %x INTL 0",
 			   addr, sizeof(struct acpi_dmar), OEM_REVISION);
 	ut_assert_console_end();
+	unmap_sysmem(buf);
+	free(buf);
 
 	return 0;
 }
 DM_TEST(dm_test_acpi_cmd_list, UTF_SCAN_PDATA | UTF_SCAN_FDT | UTF_CONSOLE);
 
+/* Test 'acpi list -c' command */
+static int dm_test_acpi_cmd_list_chksum(struct unit_test_state *uts)
+{
+	struct acpi_ctx ctx;
+	ulong addr;
+	void *buf;
+
+	buf = memalign(16, BUF_SIZE);
+	ut_assertnonnull(buf);
+	addr = map_to_sysmem(buf);
+	ut_assertok(setup_ctx_and_base_tables(uts, &ctx, addr));
+
+	ut_assertok(acpi_write_dev_tables(&ctx));
+
+	run_command("acpi list -c", 0);
+	ut_assert_nextline("Name              Base   Size  Detail");
+	ut_assert_nextline("----  ----------------  -----  ----------------------------");
+	ut_assert_nextline("RSDP  %16lx  %5zx  v02 U-BOOT  OK  OK", addr,
+			   sizeof(struct acpi_rsdp));
+	addr = ALIGN(addr + sizeof(struct acpi_rsdp), 16);
+	ut_assert_nextline("RSDT  %16lx  %5zx  v01 U-BOOT U-BOOTBL %x INTL 0  OK",
+			   addr, sizeof(struct acpi_table_header) +
+			   3 * sizeof(u32), OEM_REVISION);
+	addr = ALIGN(addr + sizeof(struct acpi_rsdt), 16);
+	ut_assert_nextline("XSDT  %16lx  %5zx  v01 U-BOOT U-BOOTBL %x INTL 0  OK",
+			   addr, sizeof(struct acpi_table_header) +
+			   3 * sizeof(u64), OEM_REVISION);
+	addr = ALIGN(addr + sizeof(struct acpi_xsdt), 64);
+	ut_assert_nextline("DMAR  %16lx  %5zx  v01 U-BOOT U-BOOTBL %x INTL 0  OK",
+			   addr, sizeof(struct acpi_dmar), OEM_REVISION);
+	addr = ALIGN(addr + sizeof(struct acpi_dmar), 16);
+	ut_assert_nextline("DMAR  %16lx  %5zx  v01 U-BOOT U-BOOTBL %x INTL 0  OK",
+			   addr, sizeof(struct acpi_dmar), OEM_REVISION);
+	addr = ALIGN(addr + sizeof(struct acpi_dmar), 16);
+	ut_assert_nextline("DMAR  %16lx  %5zx  v01 U-BOOT U-BOOTBL %x INTL 0  OK",
+			   addr, sizeof(struct acpi_dmar), OEM_REVISION);
+	ut_assert_console_end();
+	ut_assert_console_end();
+	unmap_sysmem(buf);
+	free(buf);
+
+	return 0;
+}
+DM_TEST(dm_test_acpi_cmd_list_chksum,
+	UTF_SCAN_PDATA | UTF_SCAN_FDT | UTF_CONSOLE);
+
 /* Test 'acpi dump' command */
 static int dm_test_acpi_cmd_dump(struct unit_test_state *uts)
 {
@@ -458,6 +510,8 @@ static int dm_test_acpi_cmd_dump(struct unit_test_state *uts)
 	ut_assert_nextline("DMAR @ %16lx", addr);
 	ut_assert_nextlines_are_dump(0x30);
 	ut_assert_console_end();
+	unmap_sysmem(buf);
+	free(buf);
 
 	return 0;
 }
@@ -642,6 +696,8 @@ static int dm_test_acpi_cmd_items(struct unit_test_state *uts)
 	ut_assert_nextlines_are_dump(2);
 	ut_assert_nextline("%s", "");
 	ut_assert_console_end();
+	unmap_sysmem(buf);
+	free(buf);
 
 	return 0;
 }
@@ -679,6 +735,8 @@ static int dm_test_acpi_cmd_set(struct unit_test_state *uts)
 	ut_asserteq(addr, gd_acpi_start());
 
 	ut_assert_console_end();
+	unmap_sysmem(buf);
+	free(buf);
 
 	return 0;
 }
@@ -774,6 +832,7 @@ static int dm_test_acpi_find_table(struct unit_test_state *uts)
 
 	/* Restore previous ACPI tables */
 	gd_set_acpi_start(acpi_start);
+	unmap_sysmem(buf);
 	free(buf);
 
 	return 0;
diff --git a/test/dm/acpigen.c b/test/dm/acpigen.c
index 23c16bd9866..ee9517f9c29 100644
--- a/test/dm/acpigen.c
+++ b/test/dm/acpigen.c
@@ -1742,3 +1742,118 @@ static int dm_test_acpi_write_tsd_package(struct unit_test_state *uts)
 	return 0;
 }
 DM_TEST(dm_test_acpi_write_tsd_package, 0);
+
+static int dm_test_acpi_iort_smmu_v3(struct unit_test_state *uts)
+{
+	struct acpi_ctx *ctx;
+	int smmu_offset;
+	u8 *ptr;
+
+	ut_assertok(alloc_context(&ctx));
+	ctx->tab_start = ctx->current;
+	acpi_inc(ctx, sizeof(struct acpi_table_iort));
+
+	ptr = acpigen_get_current(ctx);
+
+	smmu_offset = acpi_iort_add_smmu_v3(ctx,
+					    0xaabbccddeeffULL, // Base address
+					    1, // Flags
+					    0xffeeddccaabbULL,  // VATOS address
+					    0,  // SMMUv3 Model
+					    3, // Event
+					    4, // Pri
+					    5, // Gerror
+					    6, // Sync
+					    7,  // Proximity domain
+					    8,  // DevIDMappingIndex
+					    0,
+					    NULL);
+	ut_assert(smmu_offset);
+
+	ut_asserteq(ACPI_IORT_NODE_SMMU_V3, ptr[0]);
+	ut_asserteq(68, get_unaligned((u16 *)(ptr + 1)));
+	ut_asserteq(0, get_unaligned((u16 *)(ptr + 4)));
+	ut_asserteq(0, get_unaligned((u32 *)(ptr + 8)));
+	ut_asserteq(0, get_unaligned((u32 *)(ptr + 12)));
+
+	ut_asserteq_64(0xaabbccddeeffULL, get_unaligned((u64 *)(ptr + 16)));
+	ut_asserteq(1, get_unaligned((u32 *)(ptr + 24)));
+	ut_asserteq(0, get_unaligned((u32 *)(ptr + 28)));
+	ut_asserteq_64(0xffeeddccaabbULL, get_unaligned((u64 *)(ptr + 32)));
+	ut_asserteq(0, get_unaligned((u32 *)(ptr + 40)));
+	ut_asserteq(3, get_unaligned((u32 *)(ptr + 44)));
+	ut_asserteq(4, get_unaligned((u32 *)(ptr + 48)));
+	ut_asserteq(5, get_unaligned((u32 *)(ptr + 52)));
+	ut_asserteq(6, get_unaligned((u32 *)(ptr + 56)));
+	ut_asserteq(7, get_unaligned((u32 *)(ptr + 60)));
+	ut_asserteq(8, get_unaligned((u32 *)(ptr + 64)));
+
+	free_context(&ctx);
+
+	return 0;
+}
+DM_TEST(dm_test_acpi_iort_smmu_v3, 0);
+
+static int dm_test_acpi_iort_rc(struct unit_test_state *uts)
+{
+	struct acpi_ctx *ctx;
+	int its_group_offset, offset;
+	u8 *ptr;
+
+	ut_assertok(alloc_context(&ctx));
+	ctx->tab_start = ctx->current;
+	acpi_inc(ctx, sizeof(struct acpi_table_iort));
+
+	u32 identifiers[] = { 0 };
+
+	its_group_offset = acpi_iort_add_its_group(ctx, ARRAY_SIZE(identifiers),
+						   identifiers);
+
+	ptr = acpigen_get_current(ctx);
+
+	struct acpi_iort_id_mapping map_rc[] = {
+		{0, 0xfff, 0, its_group_offset, 0},
+		{0x1000, 0xffff, 0x1000, its_group_offset, 0}
+	};
+
+	offset = acpi_iort_add_rc(ctx,
+				  0xaabbccddeeffULL, // Mem Access Properties
+				  2, // ATS attributes
+				  3, // PCI segment
+				  4, // Memory address size limit
+				  ARRAY_SIZE(map_rc),
+				  map_rc);
+
+	ut_assert(offset);
+	ut_asserteq(ACPI_IORT_NODE_PCI_ROOT_COMPLEX, ptr[0]);
+	ut_asserteq(36 + ARRAY_SIZE(map_rc) * sizeof(struct acpi_iort_id_mapping),
+		    get_unaligned((u16 *)(ptr + 1)));
+	ut_asserteq(0, get_unaligned((u16 *)(ptr + 4)));
+	ut_asserteq(2, get_unaligned((u32 *)(ptr + 8)));
+	ut_asserteq(36, get_unaligned((u32 *)(ptr + 12)));
+
+	ut_asserteq_64(0xaabbccddeeffULL, get_unaligned((u64 *)(ptr + 16)));
+	ut_asserteq(2, get_unaligned((u32 *)(ptr + 24)));
+	ut_asserteq(3, get_unaligned((u32 *)(ptr + 28)));
+	ut_asserteq(4, ptr[32]);
+	ut_asserteq(0, ptr[33]);
+	ut_asserteq(0, ptr[34]);
+	ut_asserteq(0, ptr[35]);
+
+	ut_asserteq(0, get_unaligned((u32 *)(ptr + 36)));
+	ut_asserteq(0xfff, get_unaligned((u32 *)(ptr + 40)));
+	ut_asserteq(0, get_unaligned((u32 *)(ptr + 44)));
+	ut_asserteq(its_group_offset, get_unaligned((u32 *)(ptr + 48)));
+	ut_asserteq(0, get_unaligned((u32 *)(ptr + 52)));
+
+	ut_asserteq(0x1000, get_unaligned((u32 *)(ptr + 56)));
+	ut_asserteq(0xffff, get_unaligned((u32 *)(ptr + 60)));
+	ut_asserteq(0x1000, get_unaligned((u32 *)(ptr + 64)));
+	ut_asserteq(its_group_offset, get_unaligned((u32 *)(ptr + 68)));
+	ut_asserteq(0, get_unaligned((u32 *)(ptr + 72)));
+
+	free_context(&ctx);
+
+	return 0;
+}
+DM_TEST(dm_test_acpi_iort_rc, 0);
\ No newline at end of file
diff --git a/test/dm/mux-cmd.c b/test/dm/mux-cmd.c
index 6eb3b283161..bd02cda84db 100644
--- a/test/dm/mux-cmd.c
+++ b/test/dm/mux-cmd.c
@@ -26,8 +26,6 @@ static int dm_test_cmd_mux_list(struct unit_test_state *uts)
 	int i;
 	unsigned long val;
 
-	sandbox_set_enable_memio(true);
-
 	ut_assertok(uclass_get_device_by_name(UCLASS_MUX, "a-mux-controller",
 					      &dev));
 	chip = dev_get_uclass_priv(dev);
@@ -119,8 +117,6 @@ static int dm_test_cmd_mux_select(struct unit_test_state *uts)
 	char cmd[BUF_SIZE];
 	unsigned int i, state;
 
-	sandbox_set_enable_memio(true);
-
 	ut_assertok(uclass_get_device_by_name(UCLASS_MUX, "a-mux-controller",
 					      &dev));
 	chip = dev_get_uclass_priv(dev);
@@ -153,8 +149,6 @@ static int dm_test_cmd_mux_deselect(struct unit_test_state *uts)
 	char cmd[BUF_SIZE];
 	unsigned int i, state;
 
-	sandbox_set_enable_memio(true);
-
 	ut_assertok(uclass_get_device_by_name(UCLASS_MUX, "a-mux-controller",
 					      &dev));
 	chip = dev_get_uclass_priv(dev);
diff --git a/test/dm/ofnode.c b/test/dm/ofnode.c
index cc8b444ff9a..0f60c2a6281 100644
--- a/test/dm/ofnode.c
+++ b/test/dm/ofnode.c
@@ -23,6 +23,7 @@
 #include <dm/device-internal.h>
 #include <dm/lists.h>
 #include <dm/of_extra.h>
+#include <dm/ofnode_graph.h>
 #include <dm/root.h>
 #include <dm/test.h>
 #include <dm/uclass-internal.h>
@@ -1651,3 +1652,56 @@ static int dm_test_bool(struct unit_test_state *uts)
 	return 0;
 }
 DM_TEST(dm_test_bool, UTF_SCAN_FDT);
+
+/* test all helpers found in drivers/core/ofnode_graph.c */
+static int dm_test_ofnode_graph(struct unit_test_state *uts)
+{
+	/* 3 ports with 5 endpoints (2-1-2) */
+	ofnode graph1 = ofnode_path("/graph1");
+	/* 1 port with 1 endpoint */
+	ofnode graph2 = ofnode_path("/graph2");
+	ofnode node;
+	u32 id;
+
+	ut_asserteq(ofnode_graph_get_endpoint_count(graph1), 5);
+	ut_asserteq(ofnode_graph_get_endpoint_count(graph2), 1);
+
+	ut_asserteq(ofnode_graph_get_port_count(graph1), 3);
+	ut_asserteq(ofnode_graph_get_port_count(graph2), 1);
+
+	/* Request port with reg 2 */
+	node = ofnode_graph_get_port_by_id(graph1, 2);
+	ofnode_read_u32(node, "reg", &id);
+	ut_asserteq(id, 2);
+
+	/* Reqest parent from prev requested endpoint */
+	node = ofnode_graph_get_port_parent(node);
+	ut_asserteq_str(ofnode_get_name(node), "graph1");
+
+	/* Request endpoint under port 1 */
+	node = ofnode_graph_get_endpoint_by_regs(graph1, 1, -1);
+	ut_assert(ofnode_has_property(node, "test-property-0"));
+
+	/* Reqest remote endpoint from graph2 in graph1 */
+	node = ofnode_graph_get_endpoint_by_regs(graph2, -1, -1);
+	node = ofnode_graph_get_remote_endpoint(node);
+	ut_assert(ofnode_has_property(node, "test-property-1"));
+
+	/* Reqest remote parent from graph2 linked endpoint */
+	node = ofnode_graph_get_endpoint_by_regs(graph2, -1, -1);
+	node = ofnode_graph_get_remote_port_parent(node);
+	ut_asserteq_str(ofnode_get_name(node), "graph1");
+
+	/* Reqest remote port from graph2 linked endpoint */
+	node = ofnode_graph_get_endpoint_by_regs(graph2, -1, -1);
+	node = ofnode_graph_get_remote_port(node);
+	ofnode_read_u32(node, "reg", &id);
+	ut_asserteq(id, 2);
+
+	/* Reqest remote parent from graph2 linked endpoint */
+	node = ofnode_graph_get_remote_node(graph2, -1, -1);
+	ut_asserteq_str(ofnode_get_name(node), "graph1");
+
+	return 0;
+}
+DM_TEST(dm_test_ofnode_graph, UTF_SCAN_FDT);
diff --git a/test/dm/video_bridge.c b/test/dm/video_bridge.c
new file mode 100644
index 00000000000..f55a333c0b8
--- /dev/null
+++ b/test/dm/video_bridge.c
@@ -0,0 +1,67 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Test for video bridge uclass
+ *
+ * Copyright (c) 2025 Svyatoslav Ryhel <clamor95@gmail.com>
+ */
+
+#include <backlight.h>
+#include <dm.h>
+#include <panel.h>
+#include <video.h>
+#include <video_bridge.h>
+#include <asm/gpio.h>
+#include <asm/test.h>
+#include <dm/test.h>
+#include <power/regulator.h>
+#include <test/test.h>
+#include <test/ut.h>
+
+/* Basic test of the video uclass, test is based on driven panel */
+static int dm_test_video_bridge(struct unit_test_state *uts)
+{
+	struct udevice *dev, *pwm, *gpio, *reg;
+	uint period_ns, duty_ns;
+	bool enable, polarity;
+	struct display_timing timing;
+
+	ut_assertok(uclass_first_device_err(UCLASS_VIDEO_BRIDGE, &dev));
+	ut_assertok(uclass_get_device_by_name(UCLASS_PWM, "pwm", &pwm));
+	ut_assertok(uclass_get_device(UCLASS_GPIO, 1, &gpio));
+	ut_assertok(regulator_get_by_platname("VDD_EMMC_1.8V", &reg));
+	ut_assertok(sandbox_pwm_get_config(pwm, 0, &period_ns, &duty_ns,
+					   &enable, &polarity));
+	ut_asserteq(false, enable);
+	ut_asserteq(true, regulator_get_enable(reg));
+
+	/* bridge calls panel_enable_backlight() of panel */
+	ut_assertok(video_bridge_attach(dev));
+	ut_assertok(sandbox_pwm_get_config(pwm, 0, &period_ns, &duty_ns,
+					   &enable, &polarity));
+	ut_asserteq(1000, period_ns);
+	ut_asserteq(170 * 1000 / 255, duty_ns);
+	ut_asserteq(true, enable);
+	ut_asserteq(false, polarity);
+	ut_asserteq(1, sandbox_gpio_get_value(gpio, 1));
+	ut_asserteq(true, regulator_get_enable(reg));
+
+	/* bridge calls panel_set_backlight() of panel */
+	ut_assertok(video_bridge_set_backlight(dev, BACKLIGHT_DEFAULT));
+	ut_assertok(sandbox_pwm_get_config(pwm, 0, &period_ns, &duty_ns,
+					   &enable, &polarity));
+	ut_asserteq(true, enable);
+	ut_asserteq(170 * 1000 / 255, duty_ns);
+
+	/* bridge should be active */
+	ut_assertok(video_bridge_set_active(dev, true));
+
+	/* bridge is internal and has no hotplug gpio */
+	ut_asserteq(-ENOENT, video_bridge_check_attached(dev));
+
+	/* check passing timings and EDID */
+	ut_assertok(video_bridge_get_display_timing(dev, &timing));
+	ut_assertok(video_bridge_read_edid(dev, NULL, 0));
+
+	return 0;
+}
+DM_TEST(dm_test_video_bridge, UTF_SCAN_PDATA | UTF_SCAN_FDT);
diff --git a/test/env/Kconfig b/test/env/Kconfig
index 6cb82337b36..21d88f47a6d 100644
--- a/test/env/Kconfig
+++ b/test/env/Kconfig
@@ -1,6 +1,5 @@
 config UT_ENV
 	bool "Enable env unit tests"
-	depends on UNIT_TEST
 	default y
 	help
 	  This enables the 'ut env' command which runs a series of unit
diff --git a/test/env/cmd_ut_env.c b/test/env/cmd_ut_env.c
index 81d1bb2f80d..43f1b7d1cef 100644
--- a/test/env/cmd_ut_env.c
+++ b/test/env/cmd_ut_env.c
@@ -5,7 +5,6 @@
  */
 
 #include <test/env.h>
-#include <test/suites.h>
 #include <test/ut.h>
 
 static int env_test_env_cmd(struct unit_test_state *uts)
diff --git a/test/overlay/Kconfig b/test/fdt_overlay/Kconfig
index 881848968bb..c50b8822544 100644
--- a/test/overlay/Kconfig
+++ b/test/fdt_overlay/Kconfig
@@ -1,6 +1,6 @@
-config UT_OVERLAY
+config UT_FDT_OVERLAY
 	bool "Enable Device Tree Overlays Unit Tests"
-	depends on UNIT_TEST && OF_CONTROL && SANDBOX
+	depends on OF_CONTROL && SANDBOX
 	default y
 	select OF_LIBFDT_OVERLAY
 	help
diff --git a/test/overlay/Makefile b/test/fdt_overlay/Makefile
index 47937e3c108..5625c0d8885 100644
--- a/test/overlay/Makefile
+++ b/test/fdt_overlay/Makefile
@@ -4,7 +4,7 @@
 # Copyright (c) 2016 Free Electrons
 
 # Test files
-obj-y += cmd_ut_overlay.o
+obj-y += cmd_ut_fdt_overlay.o
 
 DTC_FLAGS += -@
 
diff --git a/test/overlay/cmd_ut_overlay.c b/test/fdt_overlay/cmd_ut_fdt_overlay.c
index aefa147ec04..0084033b6ca 100644
--- a/test/overlay/cmd_ut_overlay.c
+++ b/test/fdt_overlay/cmd_ut_fdt_overlay.c
@@ -6,6 +6,7 @@
 
 #include <command.h>
 #include <errno.h>
+#include <fdtdec.h>
 #include <fdt_support.h>
 #include <image.h>
 #include <log.h>
@@ -13,9 +14,8 @@
 
 #include <linux/sizes.h>
 
+#include <test/fdt_overlay.h>
 #include <test/ut.h>
-#include <test/overlay.h>
-#include <test/suites.h>
 
 /* 4k ought to be enough for anybody */
 #define FDT_COPY_SIZE	(4 * SZ_1K)
@@ -26,32 +26,61 @@ extern u32 __dtbo_test_fdt_overlay_stacked_begin;
 
 static void *fdt;
 
-static int ut_fdt_getprop_u32_by_index(void *fdt, const char *path,
-				    const char *name, int index,
-				    u32 *out)
+static int fdt_overlay_init(struct unit_test_state *uts)
 {
-	const fdt32_t *val;
-	int node_off;
-	int len;
+	void *fdt_base = &__dtb_test_fdt_base_begin;
+	void *fdt_overlay = &__dtbo_test_fdt_overlay_begin;
+	void *fdt_overlay_stacked = &__dtbo_test_fdt_overlay_stacked_begin;
+	void *fdt_overlay_copy, *fdt_overlay_stacked_copy;
 
-	node_off = fdt_path_offset(fdt, path);
-	if (node_off < 0)
-		return node_off;
+	ut_assertok(fdt_check_header(fdt_base));
+	ut_assertok(fdt_check_header(fdt_overlay));
 
-	val = fdt_getprop(fdt, node_off, name, &len);
-	if (!val || (len < (sizeof(uint32_t) * (index + 1))))
-		return -FDT_ERR_NOTFOUND;
+	fdt = malloc(FDT_COPY_SIZE);
+	fdt_overlay_copy = malloc(FDT_COPY_SIZE);
+	fdt_overlay_stacked_copy = malloc(FDT_COPY_SIZE);
+	ut_assertnonnull(fdt);
+	ut_assertnonnull(fdt_overlay_copy);
+	ut_assertnonnull(fdt_overlay_stacked_copy);
 
-	*out = fdt32_to_cpu(*(val + index));
+	/*
+	 * Resize the FDT to 4k so that we have room to operate on
+	 *
+	 * (and relocate it since the memory might be mapped
+	 * read-only)
+	 */
+	ut_assertok(fdt_open_into(fdt_base, fdt, FDT_COPY_SIZE));
 
-	return 0;
-}
+	/*
+	 * Resize the overlay to 4k so that we have room to operate on
+	 *
+	 * (and relocate it since the memory might be mapped
+	 * read-only)
+	 */
+	ut_assertok(fdt_open_into(fdt_overlay, fdt_overlay_copy,
+				  FDT_COPY_SIZE));
 
-static int ut_fdt_getprop_u32(void *fdt, const char *path, const char *name,
-			   u32 *out)
-{
-	return ut_fdt_getprop_u32_by_index(fdt, path, name, 0, out);
+	/*
+	 * Resize the stacked overlay to 4k so that we have room to operate on
+	 *
+	 * (and relocate it since the memory might be mapped
+	 * read-only)
+	 */
+	ut_assertok(fdt_open_into(fdt_overlay_stacked, fdt_overlay_stacked_copy,
+				  FDT_COPY_SIZE));
+
+	/* Apply the overlay */
+	ut_assertok(fdt_overlay_apply(fdt, fdt_overlay_copy));
+
+	/* Apply the stacked overlay */
+	ut_assertok(fdt_overlay_apply(fdt, fdt_overlay_stacked_copy));
+
+	free(fdt_overlay_stacked_copy);
+	free(fdt_overlay_copy);
+
+	return 0;
 }
+FDT_OVERLAY_TEST_INIT(fdt_overlay_init, 0);
 
 static int fdt_getprop_str(void *fdt, const char *path, const char *name,
 			   const char **out)
@@ -68,19 +97,20 @@ static int fdt_getprop_str(void *fdt, const char *path, const char *name,
 	return len < 0 ? len : 0;
 }
 
-static int fdt_overlay_change_int_property(struct unit_test_state *uts)
+static int fdt_overlay_test_change_int_property(struct unit_test_state *uts)
 {
-	u32 val = 0;
+	int off;
 
-	ut_assertok(ut_fdt_getprop_u32(fdt, "/test-node", "test-int-property",
-				    &val));
-	ut_asserteq(43, val);
+	off = fdt_path_offset(fdt, "/test-node");
+	ut_assert(off >= 0);
+
+	ut_asserteq(43, fdtdec_get_uint(fdt, off, "test-int-property", 0));
 
 	return CMD_RET_SUCCESS;
 }
-OVERLAY_TEST(fdt_overlay_change_int_property, 0);
+FDT_OVERLAY_TEST(fdt_overlay_test_change_int_property, 0);
 
-static int fdt_overlay_change_str_property(struct unit_test_state *uts)
+static int fdt_overlay_test_change_str_property(struct unit_test_state *uts)
 {
 	const char *val = NULL;
 
@@ -90,9 +120,9 @@ static int fdt_overlay_change_str_property(struct unit_test_state *uts)
 
 	return CMD_RET_SUCCESS;
 }
-OVERLAY_TEST(fdt_overlay_change_str_property, 0);
+FDT_OVERLAY_TEST(fdt_overlay_test_change_str_property, 0);
 
-static int fdt_overlay_add_str_property(struct unit_test_state *uts)
+static int fdt_overlay_test_add_str_property(struct unit_test_state *uts)
 {
 	const char *val = NULL;
 
@@ -102,9 +132,9 @@ static int fdt_overlay_add_str_property(struct unit_test_state *uts)
 
 	return CMD_RET_SUCCESS;
 }
-OVERLAY_TEST(fdt_overlay_add_str_property, 0);
+FDT_OVERLAY_TEST(fdt_overlay_test_add_str_property, 0);
 
-static int fdt_overlay_add_node_by_phandle(struct unit_test_state *uts)
+static int fdt_overlay_test_add_node_by_phandle(struct unit_test_state *uts)
 {
 	int off;
 
@@ -115,9 +145,9 @@ static int fdt_overlay_add_node_by_phandle(struct unit_test_state *uts)
 
 	return CMD_RET_SUCCESS;
 }
-OVERLAY_TEST(fdt_overlay_add_node_by_phandle, 0);
+FDT_OVERLAY_TEST(fdt_overlay_test_add_node_by_phandle, 0);
 
-static int fdt_overlay_add_node_by_path(struct unit_test_state *uts)
+static int fdt_overlay_test_add_node_by_path(struct unit_test_state *uts)
 {
 	int off;
 
@@ -128,9 +158,9 @@ static int fdt_overlay_add_node_by_path(struct unit_test_state *uts)
 
 	return CMD_RET_SUCCESS;
 }
-OVERLAY_TEST(fdt_overlay_add_node_by_path, 0);
+FDT_OVERLAY_TEST(fdt_overlay_test_add_node_by_path, 0);
 
-static int fdt_overlay_add_subnode_property(struct unit_test_state *uts)
+static int fdt_overlay_test_add_subnode_property(struct unit_test_state *uts)
 {
 	int off;
 
@@ -142,12 +172,12 @@ static int fdt_overlay_add_subnode_property(struct unit_test_state *uts)
 
 	return CMD_RET_SUCCESS;
 }
-OVERLAY_TEST(fdt_overlay_add_subnode_property, 0);
+FDT_OVERLAY_TEST(fdt_overlay_test_add_subnode_property, 0);
 
-static int fdt_overlay_local_phandle(struct unit_test_state *uts)
+static int fdt_overlay_test_local_phandle(struct unit_test_state *uts)
 {
 	uint32_t local_phandle;
-	u32 val = 0;
+	u32 val[2];
 	int off;
 
 	off = fdt_path_offset(fdt, "/new-local-node");
@@ -156,22 +186,19 @@ static int fdt_overlay_local_phandle(struct unit_test_state *uts)
 	local_phandle = fdt_get_phandle(fdt, off);
 	ut_assert(local_phandle);
 
-	ut_assertok(ut_fdt_getprop_u32_by_index(fdt, "/", "test-several-phandle",
-					     0, &val));
-	ut_asserteq(local_phandle, val);
-
-	ut_assertok(ut_fdt_getprop_u32_by_index(fdt, "/", "test-several-phandle",
-					     1, &val));
-	ut_asserteq(local_phandle, val);
+	ut_assertok(fdtdec_get_int_array(fdt, 0, "test-several-phandle", val,
+					 ARRAY_SIZE(val)));
+	ut_asserteq(local_phandle, val[0]);
+	ut_asserteq(local_phandle, val[1]);
 
 	return CMD_RET_SUCCESS;
 }
-OVERLAY_TEST(fdt_overlay_local_phandle, 0);
+FDT_OVERLAY_TEST(fdt_overlay_test_local_phandle, 0);
 
-static int fdt_overlay_local_phandles(struct unit_test_state *uts)
+static int fdt_overlay_test_local_phandles(struct unit_test_state *uts)
 {
 	uint32_t local_phandle, test_phandle;
-	u32 val = 0;
+	u32 val[2];
 	int off;
 
 	off = fdt_path_offset(fdt, "/new-local-node");
@@ -186,95 +213,25 @@ static int fdt_overlay_local_phandles(struct unit_test_state *uts)
 	test_phandle = fdt_get_phandle(fdt, off);
 	ut_assert(test_phandle);
 
-	ut_assertok(ut_fdt_getprop_u32_by_index(fdt, "/", "test-phandle", 0,
-					     &val));
-	ut_asserteq(test_phandle, val);
-
-	ut_assertok(ut_fdt_getprop_u32_by_index(fdt, "/", "test-phandle", 1,
-					     &val));
-	ut_asserteq(local_phandle, val);
-
-	return CMD_RET_SUCCESS;
-}
-OVERLAY_TEST(fdt_overlay_local_phandles, 0);
-
-static int fdt_overlay_stacked(struct unit_test_state *uts)
-{
-	u32 val = 0;
-
-	ut_assertok(ut_fdt_getprop_u32(fdt, "/new-local-node",
-				       "stacked-test-int-property", &val));
-	ut_asserteq(43, val);
+	ut_assertok(fdtdec_get_int_array(fdt, 0, "test-phandle", val,
+					 ARRAY_SIZE(val)));
+	ut_asserteq(test_phandle, val[0]);
+	ut_asserteq(local_phandle, val[1]);
 
 	return CMD_RET_SUCCESS;
 }
-OVERLAY_TEST(fdt_overlay_stacked, 0);
+FDT_OVERLAY_TEST(fdt_overlay_test_local_phandles, 0);
 
-int do_ut_overlay(struct unit_test_state *uts, struct cmd_tbl *cmdtp, int flag,
-		  int argc, char *const argv[])
+static int fdt_overlay_test_stacked(struct unit_test_state *uts)
 {
-	struct unit_test *tests = UNIT_TEST_SUITE_START(overlay);
-	const int n_ents = UNIT_TEST_SUITE_COUNT(overlay);
-	void *fdt_base = &__dtb_test_fdt_base_begin;
-	void *fdt_overlay = &__dtbo_test_fdt_overlay_begin;
-	void *fdt_overlay_stacked = &__dtbo_test_fdt_overlay_stacked_begin;
-	void *fdt_overlay_copy, *fdt_overlay_stacked_copy;
-	int ret = -ENOMEM;
-
-	ut_assertok(fdt_check_header(fdt_base));
-	ut_assertok(fdt_check_header(fdt_overlay));
-
-	fdt = malloc(FDT_COPY_SIZE);
-	if (!fdt)
-		goto err1;
-
-	fdt_overlay_copy = malloc(FDT_COPY_SIZE);
-	if (!fdt_overlay_copy)
-		goto err2;
-
-	fdt_overlay_stacked_copy = malloc(FDT_COPY_SIZE);
-	if (!fdt_overlay_stacked_copy)
-		goto err3;
-
-	/*
-	 * Resize the FDT to 4k so that we have room to operate on
-	 *
-	 * (and relocate it since the memory might be mapped
-	 * read-only)
-	 */
-	ut_assertok(fdt_open_into(fdt_base, fdt, FDT_COPY_SIZE));
-
-	/*
-	 * Resize the overlay to 4k so that we have room to operate on
-	 *
-	 * (and relocate it since the memory might be mapped
-	 * read-only)
-	 */
-	ut_assertok(fdt_open_into(fdt_overlay, fdt_overlay_copy,
-				  FDT_COPY_SIZE));
-
-	/*
-	 * Resize the stacked overlay to 4k so that we have room to operate on
-	 *
-	 * (and relocate it since the memory might be mapped
-	 * read-only)
-	 */
-	ut_assertok(fdt_open_into(fdt_overlay_stacked, fdt_overlay_stacked_copy,
-				  FDT_COPY_SIZE));
-
-	/* Apply the overlay */
-	ut_assertok(fdt_overlay_apply(fdt, fdt_overlay_copy));
+	int off;
 
-	/* Apply the stacked overlay */
-	ut_assertok(fdt_overlay_apply(fdt, fdt_overlay_stacked_copy));
+	off = fdt_path_offset(fdt, "/new-local-node");
+	ut_assert(off > 0);
 
-	ret = cmd_ut_category(uts, "overlay", "", tests, n_ents, argc, argv);
+	ut_asserteq(43,
+		    fdtdec_get_uint(fdt, off, "stacked-test-int-property", 0));
 
-	free(fdt_overlay_stacked_copy);
-err3:
-	free(fdt_overlay_copy);
-err2:
-	free(fdt);
-err1:
-	return ret;
+	return CMD_RET_SUCCESS;
 }
+FDT_OVERLAY_TEST(fdt_overlay_test_stacked, 0);
diff --git a/test/overlay/test-fdt-base.dts b/test/fdt_overlay/test-fdt-base.dts
index 38278334e4d..38278334e4d 100644
--- a/test/overlay/test-fdt-base.dts
+++ b/test/fdt_overlay/test-fdt-base.dts
diff --git a/test/overlay/test-fdt-overlay-stacked.dtso b/test/fdt_overlay/test-fdt-overlay-stacked.dtso
index 6411adec539..6411adec539 100644
--- a/test/overlay/test-fdt-overlay-stacked.dtso
+++ b/test/fdt_overlay/test-fdt-overlay-stacked.dtso
diff --git a/test/overlay/test-fdt-overlay.dtso b/test/fdt_overlay/test-fdt-overlay.dtso
index 5a21b346d07..5a21b346d07 100644
--- a/test/overlay/test-fdt-overlay.dtso
+++ b/test/fdt_overlay/test-fdt-overlay.dtso
diff --git a/test/lib/Makefile b/test/lib/Makefile
index 0e4cb8e3dfd..aa89923f786 100644
--- a/test/lib/Makefile
+++ b/test/lib/Makefile
@@ -14,6 +14,7 @@ obj-y += hexdump.o
 obj-$(CONFIG_SANDBOX) += kconfig.o
 obj-y += lmb.o
 obj-$(CONFIG_HAVE_SETJMP) += longjmp.o
+obj-$(CONFIG_SANDBOX) += membuf.o
 obj-$(CONFIG_CONSOLE_RECORD) += test_print.o
 obj-$(CONFIG_SSCANF) += sscanf.o
 obj-$(CONFIG_$(PHASE_)STRTO) += str.o
diff --git a/test/lib/kconfig.c b/test/lib/kconfig.c
index a3645abf946..2f47af9acf1 100644
--- a/test/lib/kconfig.c
+++ b/test/lib/kconfig.c
@@ -22,10 +22,10 @@ static int lib_test_is_enabled(struct unit_test_state *uts)
 	ut_asserteq(0, CONFIG_IS_ENABLED(_UNDEFINED));
 
 	if (IS_ENABLED(CONFIG_BLOBLIST)) {
-		ut_asserteq(0xb000, IF_ENABLED_INT(CONFIG_BLOBLIST_FIXED,
-						   CONFIG_BLOBLIST_ADDR));
-		ut_asserteq(0xb000, CONFIG_IF_ENABLED_INT(BLOBLIST_FIXED,
-							  BLOBLIST_ADDR));
+		ut_asserteq(0x100, IF_ENABLED_INT(CONFIG_BLOBLIST_FIXED,
+						  CONFIG_BLOBLIST_ADDR));
+		ut_asserteq(0x100, CONFIG_IF_ENABLED_INT(BLOBLIST_FIXED,
+							 BLOBLIST_ADDR));
 	}
 
 	/*
diff --git a/test/lib/lmb.c b/test/lib/lmb.c
index 01b1c7fdedd..3bf558f7f4f 100644
--- a/test/lib/lmb.c
+++ b/test/lib/lmb.c
@@ -471,17 +471,17 @@ static int lib_test_lmb_overlapping_reserve(struct unit_test_state *uts)
 	ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 1, 0x40010000, 0x10000,
 		   0, 0, 0, 0);
 
-	/* allocate overlapping region should return the coalesced count */
+	/* allocate overlapping region */
 	ret = lmb_reserve(0x40011000, 0x10000, LMB_NONE);
 	ut_asserteq(ret, 0);
 	ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 1, 0x40010000, 0x11000,
 		   0, 0, 0, 0);
-	/* allocate 3nd region */
+	/* allocate 2nd region */
 	ret = lmb_reserve(0x40030000, 0x10000, LMB_NONE);
 	ut_asserteq(ret, 0);
 	ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 2, 0x40010000, 0x11000,
 		   0x40030000, 0x10000, 0, 0);
-	/* allocate 2nd region , This should coalesced all region into one */
+	/* allocate 3rd region , This should coalesce all regions into one */
 	ret = lmb_reserve(0x40020000, 0x10000, LMB_NONE);
 	ut_assert(ret >= 0);
 	ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 1, 0x40010000, 0x30000,
@@ -499,6 +499,41 @@ static int lib_test_lmb_overlapping_reserve(struct unit_test_state *uts)
 	ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 1, 0x40000000, 0x40000,
 		   0, 0, 0, 0);
 
+	/* try to allocate overlapping region with a different flag, should fail */
+	ret = lmb_reserve(0x40008000, 0x1000, LMB_NOOVERWRITE);
+	ut_asserteq(ret, -EEXIST);
+
+	/* allocate another region at 0x40050000 with a different flag */
+	ret = lmb_reserve(0x40050000, 0x10000, LMB_NOOVERWRITE);
+	ut_asserteq(ret, 0);
+	ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 2, 0x40000000, 0x40000,
+		   0x40050000, 0x10000, 0, 0);
+
+	/*
+	 * try to reserve a region adjacent to region 1 overlapping the 2nd region,
+	 * should fail
+	 */
+	ret = lmb_reserve(0x40040000, 0x20000, LMB_NONE);
+	ut_asserteq(ret, -EEXIST);
+
+	/*
+	 * try to reserve a region between the two regions, but without an overlap,
+	 * should succeed. this added region coalesces with the region 1
+	 */
+	ret = lmb_reserve(0x40040000, 0x10000, LMB_NONE);
+	ut_asserteq(ret, 0);
+	ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 2, 0x40000000, 0x50000,
+		   0x40050000, 0x10000, 0, 0);
+
+	/*
+	 * try to reserve a region which overlaps with both the regions,
+	 * should fail as the flags do not match
+	 */
+	ret = lmb_reserve(0x40020000, 0x80000, LMB_NONE);
+	ut_asserteq(ret, -EEXIST);
+	ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 2, 0x40000000, 0x50000,
+		   0x40050000, 0x10000, 0, 0);
+
 	lmb_pop(&store);
 
 	return 0;
@@ -549,6 +584,77 @@ static int test_alloc_addr(struct unit_test_state *uts, const phys_addr_t ram)
 	ret = lmb_free(alloc_addr_a, 0x1000);
 	ut_asserteq(ret, 0);
 
+	/*
+	 * Add two regions with different flags, region1 and region2 with
+	 * a gap between them.
+	 * Try adding another region, adjacent to region 1 and overlapping
+	 * region 2. Should fail.
+	 */
+	a = lmb_alloc_addr(alloc_addr_a, 0x1000, LMB_NONE);
+	ut_asserteq(a, 0);
+
+	b = lmb_alloc_addr(alloc_addr_a + 0x4000, 0x1000, LMB_NOOVERWRITE);
+	ut_asserteq(b, 0);
+	ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 2, alloc_addr_a, 0x1000,
+		   alloc_addr_a + 0x4000, 0x1000, 0, 0);
+
+	c = lmb_alloc_addr(alloc_addr_a + 0x1000, 0x5000, LMB_NONE);
+	ut_asserteq(c, -1);
+	ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 2, alloc_addr_a, 0x1000,
+		   alloc_addr_a + 0x4000, 0x1000, 0, 0);
+
+	ret = lmb_free(alloc_addr_a, 0x1000);
+	ut_asserteq(ret, 0);
+	ret = lmb_free(alloc_addr_a + 0x4000, 0x1000);
+	ut_asserteq(ret, 0);
+
+	/*
+	 * Add two regions with same flags(LMB_NONE), region1 and region2
+	 * with a gap between them.
+	 * Try adding another region, adjacent to region 1 and overlapping
+	 * region 2. Should succeed. All regions should coalesce into a
+	 * single region.
+	 */
+	a = lmb_alloc_addr(alloc_addr_a, 0x1000, LMB_NONE);
+	ut_asserteq(a, 0);
+
+	b = lmb_alloc_addr(alloc_addr_a + 0x4000, 0x1000, LMB_NONE);
+	ut_asserteq(b, 0);
+	ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 2, alloc_addr_a, 0x1000,
+		   alloc_addr_a + 0x4000, 0x1000, 0, 0);
+
+	c = lmb_alloc_addr(alloc_addr_a + 0x1000, 0x5000, LMB_NONE);
+	ut_asserteq(c, 0);
+	ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 1, alloc_addr_a, 0x6000,
+		   0, 0, 0, 0);
+
+	ret = lmb_free(alloc_addr_a, 0x6000);
+	ut_asserteq(ret, 0);
+
+	/*
+	 * Add two regions with same flags(LMB_NOOVERWRITE), region1 and
+	 * region2 with a gap between them.
+	 * Try adding another region, adjacent to region 1 and overlapping
+	 * region 2. Should fail.
+	 */
+	a = lmb_alloc_addr(alloc_addr_a, 0x1000, LMB_NOOVERWRITE);
+	ut_asserteq(a, 0);
+
+	b = lmb_alloc_addr(alloc_addr_a + 0x4000, 0x1000, LMB_NOOVERWRITE);
+	ut_asserteq(b, 0);
+	ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 2, alloc_addr_a, 0x1000,
+		   alloc_addr_a + 0x4000, 0x1000, 0, 0);
+
+	c = lmb_alloc_addr(alloc_addr_a + 0x1000, 0x5000, LMB_NOOVERWRITE);
+	ut_asserteq(c, -1);
+	ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 2, alloc_addr_a, 0x1000,
+		   alloc_addr_a + 0x4000, 0x1000, 0, 0);
+
+	ret = lmb_free(alloc_addr_a, 0x1000);
+	ut_asserteq(ret, 0);
+	ret = lmb_free(alloc_addr_a + 0x4000, 0x1000);
+	ut_asserteq(ret, 0);
+
 	/*  reserve 3 blocks */
 	ret = lmb_reserve(alloc_addr_a, 0x10000, LMB_NONE);
 	ut_asserteq(ret, 0);
@@ -761,7 +867,7 @@ static int lib_test_lmb_flags(struct unit_test_state *uts)
 
 	/* reserve again, new flag */
 	ret = lmb_reserve(0x40010000, 0x10000, LMB_NONE);
-	ut_asserteq(ret, -1);
+	ut_asserteq(ret, -EEXIST);
 	ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 1, 0x40010000, 0x10000,
 		   0, 0, 0, 0);
 
diff --git a/test/lib/longjmp.c b/test/lib/longjmp.c
index 79d889bdd5f..74c3465b8c2 100644
--- a/test/lib/longjmp.c
+++ b/test/lib/longjmp.c
@@ -5,10 +5,10 @@
  * Copyright (c) 2021, Heinrich Schuchardt <xypron.glpk@gmx.de>
  */
 
+#include <setjmp.h>
 #include <test/lib.h>
 #include <test/test.h>
 #include <test/ut.h>
-#include <asm/setjmp.h>
 
 struct test_jmp_buf {
 	jmp_buf env;
diff --git a/test/lib/membuf.c b/test/lib/membuf.c
new file mode 100644
index 00000000000..3f268a422d5
--- /dev/null
+++ b/test/lib/membuf.c
@@ -0,0 +1,239 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2024 Google LLC
+ * Written by Simon Glass <sjg@chromium.org>
+ */
+
+#include <membuf.h>
+#include <os.h>
+#include <rand.h>
+#include <string.h>
+#include <test/lib.h>
+#include <test/test.h>
+#include <test/ut.h>
+
+#define TEST_SIZE	16
+#define TEST_COUNT	10000
+
+static void membuf_zero(struct membuf *mb)
+{
+	memset(mb->start, '\0', mb->end - mb->start);
+}
+
+static int membuf_check(struct unit_test_state *uts, struct membuf *mb,
+			int value)
+{
+	/* head is out of range */
+	ut_assert(!(mb->head < mb->start || mb->head >= mb->end));
+
+	/* tail is out of range */
+	ut_assert(!(mb->tail < mb->start || mb->tail >= mb->end));
+
+	return 0;
+}
+
+/* write from 1 to test_size bytes, and check they come back OK */
+static int lib_test_membuf_one(struct unit_test_state *uts)
+{
+	char in[TEST_SIZE * 2], out[TEST_SIZE * 2];
+	struct membuf mb;
+	int size, ret, test_size, i;
+
+	ut_assertok(membuf_new(&mb, TEST_SIZE));
+
+	/* setup in test */
+	for (i = 0; i < TEST_SIZE; i++) {
+		in[i] = (i & 63) + '0';
+		in[i + TEST_SIZE] = in[i];
+	}
+
+	test_size = TEST_SIZE;
+
+	for (i = 1; i < TEST_COUNT; i++) {
+		membuf_zero(&mb);
+		size = rand() % test_size;
+
+		// now write patterns and check they come back OK
+		ret = membuf_put(&mb, in, 0);
+		ret = membuf_put(&mb, in, size);
+		ut_asserteq(size, ret);
+
+		ret = membuf_put(&mb, in, 0);
+		ut_assertok(membuf_check(uts, &mb, i));
+
+		ret = membuf_get(&mb, out, 0);
+		ret = membuf_get(&mb, out, size);
+		ut_asserteq(size, ret);
+
+		ret = membuf_get(&mb, out, 0);
+		ut_assertok(membuf_check(uts, &mb, i));
+
+		ut_asserteq_mem(in, out, size);
+	}
+
+	return 0;
+}
+LIB_TEST(lib_test_membuf_one, 0);
+
+/* write random number of bytes, and check they come back OK */
+static int lib_test_membuf_random(struct unit_test_state *uts)
+{
+	char in[TEST_SIZE * 2];
+	char buf[TEST_SIZE * 2];
+	struct membuf mb;
+	int size, ret, test_size, i;
+	char *inptr, *outptr;
+	int max_avail, min_free;
+
+	ut_assertok(membuf_new(&mb, TEST_SIZE));
+
+	for (i = 0; i < TEST_SIZE; i++) {
+		in[i] = (i & 63) + '0';
+		in[i + TEST_SIZE] = in[i];
+	}
+
+	test_size = TEST_SIZE;
+
+	inptr = in;
+	outptr = in;
+	min_free = TEST_COUNT;
+	max_avail = 0;
+	membuf_zero(&mb);
+	for (i = 0; i < TEST_COUNT; i++) {
+		size = rand() % test_size;
+
+		if (membuf_free(&mb) < min_free)
+			min_free = membuf_free(&mb);
+
+		ret = membuf_put(&mb, inptr, size);
+		ut_assertok(membuf_check(uts, &mb, i));
+		inptr += ret;
+		if (inptr >= in + TEST_SIZE)
+			inptr -= TEST_SIZE;
+
+		size = rand() % (test_size - 1);
+
+		if (membuf_avail(&mb) > max_avail)
+			max_avail = membuf_avail(&mb);
+
+		ret = membuf_get(&mb, buf, size);
+		ut_assertok(membuf_check(uts, &mb, i));
+		ut_asserteq_mem(buf, outptr, ret);
+
+		outptr += ret;
+		if (outptr >= in + TEST_SIZE)
+			outptr -= TEST_SIZE;
+	}
+
+	return 0;
+}
+LIB_TEST(lib_test_membuf_random, 0);
+
+/* test membuf_extend() with split segments */
+static int lib_test_membuf_extend(struct unit_test_state *uts)
+{
+	char in[TEST_SIZE * 2];
+	char buf[TEST_SIZE * 2];
+	struct membuf mb;
+	int ret, test_size, i, cur;
+	char *data;
+
+	ut_assertok(membuf_new(&mb, TEST_SIZE));
+
+	for (i = 0; i < TEST_SIZE; i++) {
+		in[i] = (i & 63) + '0';
+		in[i + TEST_SIZE] = in[i];
+	}
+
+	test_size = TEST_SIZE - 1;
+
+	for (cur = 0; cur <= test_size; cur++) {
+		ut_assertok(membuf_new(&mb, TEST_SIZE));
+
+		membuf_zero(&mb);
+
+		/*
+		 * add some bytes, then remove them - this will force the membuf
+		 * to have data split into two segments when we fill it
+		 */
+		ret = membuf_putraw(&mb, TEST_SIZE / 2, true, &data);
+		membuf_getraw(&mb, ret, true, &data);
+		ut_asserteq(TEST_SIZE / 2, ret);
+
+		/* fill it */
+		ret = membuf_put(&mb, in, cur);
+		ut_assertok(membuf_check(uts, &mb, cur));
+		ut_asserteq(cur, ret);
+
+		/* extend the buffer */
+		ut_assertok(membuf_extend_by(&mb, TEST_SIZE, -1));
+		ut_assertok(membuf_check(uts, &mb, cur));
+
+		/* check our data is still there */
+		ret = membuf_get(&mb, buf, TEST_SIZE * 2);
+		ut_assertok(membuf_check(uts, &mb, cur));
+		ut_asserteq(cur, ret);
+		ut_asserteq_mem(in, buf, cur);
+		membuf_uninit(&mb);
+	}
+
+	return 0;
+}
+LIB_TEST(lib_test_membuf_extend, 0);
+
+/* test membuf_readline() with generated data */
+static int lib_test_membuf_readline(struct unit_test_state *uts)
+{
+	char *buf;
+	int size, cur, i, ret, readptr, cmpptr;
+	struct membuf mb;
+	char *data;
+	char str[256];
+	char *s;
+
+	ut_assertok(membuf_new(&mb, 1024));
+	membuf_zero(&mb);
+
+	/* Use the README as test data */
+	ut_assertok(os_read_file("README", (void **)&buf, &size));
+
+	cur = 0;
+	readptr = 0;
+	cmpptr = 0;
+	for (i = 0; i < 100000; i++, cur += 1) {
+		/* fill the buffer with up to 'cur' bytes */
+		ret = membuf_putraw(&mb, cur, false, &data);
+
+		if (ret > 0) {
+			int can_read = min(ret, size - readptr);
+
+			memcpy(data, &buf[readptr], can_read);
+			readptr += can_read;
+
+			membuf_putraw(&mb, can_read, true, &data);
+			ut_assertok(membuf_check(uts, &mb, i));
+		}
+
+		/* read a line and compare */
+		ret = membuf_readline(&mb, str, 256, 0, true);
+		ut_assertok(membuf_check(uts, &mb, i));
+		if (ret) {
+			char *ptr;
+
+			s = &buf[cmpptr];
+			ptr = strchr(s, '\n');
+			*ptr = '\0';
+
+			ut_asserteq_str(s, str);
+			cmpptr += strlen(s) + 1;
+			*ptr = '\n';
+		} else {
+			ut_assert(membuf_free(&mb));
+		}
+	}
+	membuf_dispose(&mb);
+	os_free(buf);
+
+	return 0;
+}
+LIB_TEST(lib_test_membuf_readline, 0);
diff --git a/test/log/cont_test.c b/test/log/cont_test.c
index 32b1c792367..3b3b791f025 100644
--- a/test/log/cont_test.c
+++ b/test/log/cont_test.c
@@ -9,7 +9,6 @@
 #include <asm/global_data.h>
 #include <test/log.h>
 #include <test/test.h>
-#include <test/suites.h>
 #include <test/ut.h>
 
 DECLARE_GLOBAL_DATA_PTR;
diff --git a/test/log/nolog_test.c b/test/log/nolog_test.c
index 341dbfc9310..1913e6817a7 100644
--- a/test/log/nolog_test.c
+++ b/test/log/nolog_test.c
@@ -13,7 +13,6 @@
 #include <asm/global_data.h>
 #include <test/log.h>
 #include <test/test.h>
-#include <test/suites.h>
 #include <test/ut.h>
 
 DECLARE_GLOBAL_DATA_PTR;
diff --git a/test/log/pr_cont_test.c b/test/log/pr_cont_test.c
index 7734e927f98..67d8ac59db9 100644
--- a/test/log/pr_cont_test.c
+++ b/test/log/pr_cont_test.c
@@ -8,7 +8,6 @@
 #include <console.h>
 #include <test/log.h>
 #include <test/test.h>
-#include <test/suites.h>
 #include <test/ut.h>
 #include <asm/global_data.h>
 #include <linux/printk.h>
diff --git a/test/log/syslog_test.c b/test/log/syslog_test.c
index c4180f775b9..98b91436580 100644
--- a/test/log/syslog_test.c
+++ b/test/log/syslog_test.c
@@ -15,7 +15,6 @@
 #include <hexdump.h>
 #include <test/log.h>
 #include <test/test.h>
-#include <test/suites.h>
 #include <test/ut.h>
 #include <asm/eth.h>
 #include "syslog_test.h"
diff --git a/test/log/syslog_test_ndebug.c b/test/log/syslog_test_ndebug.c
index b10e636812b..dfd0217c1e4 100644
--- a/test/log/syslog_test_ndebug.c
+++ b/test/log/syslog_test_ndebug.c
@@ -12,7 +12,6 @@
 #include <hexdump.h>
 #include <test/log.h>
 #include <test/test.h>
-#include <test/suites.h>
 #include <test/ut.h>
 #include <asm/eth.h>
 #include "syslog_test.h"
diff --git a/test/optee/Kconfig b/test/optee/Kconfig
index 2f6834aa3b4..63e2cbf79c7 100644
--- a/test/optee/Kconfig
+++ b/test/optee/Kconfig
@@ -1,6 +1,6 @@
 config UT_OPTEE
 	bool "Enable OP-TEE Unit Tests"
-	depends on UNIT_TEST && OF_CONTROL && OPTEE
+	depends on OF_CONTROL && OPTEE
 	default y
 	help
 	  This enables the 'ut optee' command which runs a series of unit
diff --git a/test/optee/Makefile b/test/optee/Makefile
index 8793fd7ad61..ec56750fa80 100644
--- a/test/optee/Makefile
+++ b/test/optee/Makefile
@@ -3,7 +3,7 @@
 # Copyright (C) 2019, Theobroma Systems Design und Consulting GmbH
 
 # Test files
-obj-y += cmd_ut_optee.o
+obj-y += optee.o
 
 DTC_FLAGS += -@
 
diff --git a/test/optee/cmd_ut_optee.c b/test/optee/optee.c
index fc6674764f9..658621fa2fa 100644
--- a/test/optee/cmd_ut_optee.c
+++ b/test/optee/optee.c
@@ -14,7 +14,6 @@
 
 #include <test/ut.h>
 #include <test/optee.h>
-#include <test/suites.h>
 
 /* 4k ought to be enough for anybody */
 #define FDT_COPY_SIZE	(4 * SZ_1K)
@@ -26,6 +25,41 @@ extern u32 __dtb_test_optee_no_optee_begin;
 static void *fdt;
 static bool expect_success;
 
+static int optee_test_init(struct unit_test_state *uts)
+{
+	void *fdt_optee = &__dtb_test_optee_optee_begin;
+	void *fdt_no_optee = &__dtb_test_optee_no_optee_begin;
+	void *fdt_base = &__dtb_test_optee_base_begin;
+	int ret = -ENOMEM;
+
+	ut_assertok(fdt_check_header(fdt_base));
+	ut_assertok(fdt_check_header(fdt_optee));
+	ut_assertok(fdt_check_header(fdt_no_optee));
+
+	fdt = malloc(FDT_COPY_SIZE);
+	if (!fdt)
+		return ret;
+
+	/*
+	 * Resize the FDT to 4k so that we have room to operate on
+	 *
+	 * (and relocate it since the memory might be mapped
+	 * read-only)
+	 */
+	ut_assertok(fdt_open_into(fdt_base, fdt, FDT_COPY_SIZE));
+
+	return 0;
+}
+OPTEE_TEST_INIT(optee_test_init, 0);
+
+static int optee_test_uninit(struct unit_test_state *uts)
+{
+	free(fdt);
+
+	return 0;
+}
+OPTEE_TEST_UNINIT(optee_test_uninit, 0);
+
 static int optee_fdt_firmware(struct unit_test_state *uts)
 {
 	const void *prop;
@@ -46,7 +80,6 @@ static int optee_fdt_firmware(struct unit_test_state *uts)
 
 	return CMD_RET_SUCCESS;
 }
-OPTEE_TEST(optee_fdt_firmware, 0);
 
 static int optee_fdt_protected_memory(struct unit_test_state *uts)
 {
@@ -89,60 +122,50 @@ static int optee_fdt_protected_memory(struct unit_test_state *uts)
 
 	return CMD_RET_SUCCESS;
 }
-OPTEE_TEST(optee_fdt_protected_memory, 0);
 
-int do_ut_optee(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
+/* (1) Try to copy optee nodes from empty dt */
+static int optee_fdt_copy_empty(struct unit_test_state *uts)
 {
-	struct unit_test *tests = UNIT_TEST_SUITE_START(optee);
-	const int n_ents = UNIT_TEST_SUITE_COUNT(optee);
-	struct unit_test_state *uts;
-	void *fdt_optee = &__dtb_test_optee_optee_begin;
 	void *fdt_no_optee = &__dtb_test_optee_no_optee_begin;
-	void *fdt_base = &__dtb_test_optee_base_begin;
-	int ret = -ENOMEM;
-
-	uts = calloc(1, sizeof(*uts));
-	if (!uts)
-		return -ENOMEM;
-
-	ut_assertok(fdt_check_header(fdt_base));
-	ut_assertok(fdt_check_header(fdt_optee));
-	ut_assertok(fdt_check_header(fdt_no_optee));
-
-	fdt = malloc(FDT_COPY_SIZE);
-	if (!fdt)
-		return ret;
 
-	/*
-	 * Resize the FDT to 4k so that we have room to operate on
-	 *
-	 * (and relocate it since the memory might be mapped
-	 * read-only)
-	 */
-	ut_assertok(fdt_open_into(fdt_base, fdt, FDT_COPY_SIZE));
-
-	/*
-	 * (1) Try to copy optee nodes from empty dt.
-	 * This should still run successfully.
-	 */
+	/* This should still run successfully */
 	ut_assertok(optee_copy_fdt_nodes(fdt_no_optee, fdt));
 
 	expect_success = false;
-	ret = cmd_ut_category("optee", "", tests, n_ents, argc, argv);
+	ut_assertok(optee_fdt_firmware(uts));
+	ut_assertok(optee_fdt_protected_memory(uts));
+
+	return 0;
+}
+OPTEE_TEST(optee_fdt_copy_empty, 0);
+
+/* (2) Try to copy optee nodes from prefilled dt */
+static int optee_fdt_copy_prefilled(struct unit_test_state *uts)
+{
+	void *fdt_optee = &__dtb_test_optee_optee_begin;
 
-	/* (2) Try to copy optee nodes from prefilled dt */
 	ut_assertok(optee_copy_fdt_nodes(fdt_optee, fdt));
 
 	expect_success = true;
-	ret = cmd_ut_category("optee", "", tests, n_ents, argc, argv);
+	ut_assertok(optee_fdt_firmware(uts));
+	ut_assertok(optee_fdt_protected_memory(uts));
+
+	return 0;
+}
+OPTEE_TEST(optee_fdt_copy_prefilled, 0);
+
+/* (3) Try to copy OP-TEE nodes into a already filled DT */
+static int optee_fdt_copy_already_filled(struct unit_test_state *uts)
+{
+	void *fdt_optee = &__dtb_test_optee_optee_begin;
 
-	/* (3) Try to copy OP-TEE nodes into a already filled DT */
 	ut_assertok(fdt_open_into(fdt_optee, fdt, FDT_COPY_SIZE));
 	ut_assertok(optee_copy_fdt_nodes(fdt_optee, fdt));
 
 	expect_success = true;
-	ret = cmd_ut_category("optee", "", tests, n_ents, argc, argv);
+	ut_assertok(optee_fdt_firmware(uts));
+	ut_assertok(optee_fdt_protected_memory(uts));
 
-	free(fdt);
-	return ret;
+	return 0;
 }
+OPTEE_TEST(optee_fdt_copy_already_filled, 0);
diff --git a/test/py/conftest.py b/test/py/conftest.py
index 31043a697e2..5aea85647af 100644
--- a/test/py/conftest.py
+++ b/test/py/conftest.py
@@ -7,7 +7,7 @@
 # test, at shutdown etc. These hooks perform functions such as:
 # - Parsing custom command-line options.
 # - Pullilng in user-specified board configuration.
-# - Creating the U-Boot console test fixture.
+# - Creating the ubman test fixture.
 # - Creating the HTML log file.
 # - Monitoring each test's results.
 # - Implementing custom pytest markers.
@@ -25,12 +25,12 @@ import re
 from _pytest.runner import runtestprotocol
 import subprocess
 import sys
+from spawn import BootFail, Timeout, Unexpected, handle_exception
 import time
-from u_boot_spawn import BootFail, Timeout, Unexpected, handle_exception
 
-# Globals: The HTML log file, and the connection to the U-Boot console.
+# Globals: The HTML log file, and the top-level fixture
 log = None
-console = None
+ubman_fix = None
 
 TEST_PY_DIR = os.path.dirname(os.path.abspath(__file__))
 
@@ -247,7 +247,7 @@ def pytest_configure(config):
             ubconfig.buildconfig.update(parser.items('root'))
 
     global log
-    global console
+    global ubman_fix
     global ubconfig
 
     (board_type, board_type_extra, board_identity, build_dir, build_dir_extra,
@@ -289,19 +289,26 @@ def pytest_configure(config):
     ubconfig = ArbitraryAttributeContainer()
     ubconfig.brd = dict()
     ubconfig.env = dict()
-
-    modules = [
-        (ubconfig.brd, 'u_boot_board_' + board_type_filename),
-        (ubconfig.env, 'u_boot_boardenv_' + board_type_filename),
-        (ubconfig.env, 'u_boot_boardenv_' + board_type_filename + '_' +
-            board_identity_filename),
-    ]
-    for (dict_to_fill, module_name) in modules:
-        try:
-            module = __import__(module_name)
-        except ImportError:
-            continue
-        dict_to_fill.update(module.__dict__)
+    not_found = []
+
+    with log.section('Loading lab modules', 'load_modules'):
+        modules = [
+            (ubconfig.brd, 'u_boot_board_' + board_type_filename),
+            (ubconfig.env, 'u_boot_boardenv_' + board_type_filename),
+            (ubconfig.env, 'u_boot_boardenv_' + board_type_filename + '_' +
+                board_identity_filename),
+        ]
+        for (dict_to_fill, module_name) in modules:
+            try:
+                module = __import__(module_name)
+            except ImportError:
+                not_found.append(module_name)
+                continue
+            dict_to_fill.update(module.__dict__)
+            log.info(f"Loaded {module}")
+
+        if not_found:
+            log.warning(f"Failed to find modules: {' '.join(not_found)}")
 
     ubconfig.buildconfig = dict()
 
@@ -327,6 +334,7 @@ def pytest_configure(config):
     ubconfig.dtb = build_dir + '/arch/sandbox/dts/test.dtb'
     ubconfig.connection_ok = True
     ubconfig.timing = config.getoption('timing')
+    ubconfig.role = config.getoption('role')
 
     env_vars = (
         'board_type',
@@ -343,11 +351,11 @@ def pytest_configure(config):
         os.environ['U_BOOT_' + v.upper()] = getattr(ubconfig, v)
 
     if board_type.startswith('sandbox'):
-        import u_boot_console_sandbox
-        console = u_boot_console_sandbox.ConsoleSandbox(log, ubconfig)
+        import console_sandbox
+        ubman_fix = console_sandbox.ConsoleSandbox(log, ubconfig)
     else:
-        import u_boot_console_exec_attach
-        console = u_boot_console_exec_attach.ConsoleExecAttach(log, ubconfig)
+        import console_board
+        ubman_fix = console_board.ConsoleExecAttach(log, ubconfig)
 
 
 def generate_ut_subtest(metafunc, fixture_name, sym_path):
@@ -366,7 +374,7 @@ def generate_ut_subtest(metafunc, fixture_name, sym_path):
     Returns:
         Nothing.
     """
-    fn = console.config.build_dir + sym_path
+    fn = ubman_fix.config.build_dir + sym_path
     try:
         with open(fn, 'rt') as f:
             lines = f.readlines()
@@ -407,8 +415,8 @@ def generate_config(metafunc, fixture_name):
     """
 
     subconfigs = {
-        'brd': console.config.brd,
-        'env': console.config.env,
+        'brd': ubman_fix.config.brd,
+        'env': ubman_fix.config.env,
     }
     parts = fixture_name.split('__')
     if len(parts) < 2:
@@ -470,7 +478,7 @@ def u_boot_log(request):
          The fixture value.
      """
 
-     return console.log
+     return ubman_fix.log
 
 @pytest.fixture(scope='session')
 def u_boot_config(request):
@@ -483,11 +491,11 @@ def u_boot_config(request):
          The fixture value.
      """
 
-     return console.config
+     return ubman_fix.config
 
 @pytest.fixture(scope='function')
-def u_boot_console(request):
-    """Generate the value of a test's u_boot_console fixture.
+def ubman(request):
+    """Generate the value of a test's ubman fixture.
 
     Args:
         request: The pytest request.
@@ -499,18 +507,18 @@ def u_boot_console(request):
         pytest.skip('Cannot get target connection')
         return None
     try:
-        console.ensure_spawned()
+        ubman_fix.ensure_spawned()
     except OSError as err:
-        handle_exception(ubconfig, console, log, err, 'Lab failure', True)
+        handle_exception(ubconfig, ubman_fix, log, err, 'Lab failure', True)
     except Timeout as err:
-        handle_exception(ubconfig, console, log, err, 'Lab timeout', True)
+        handle_exception(ubconfig, ubman_fix, log, err, 'Lab timeout', True)
     except BootFail as err:
-        handle_exception(ubconfig, console, log, err, 'Boot fail', True,
-                         console.get_spawn_output())
+        handle_exception(ubconfig, ubman_fix, log, err, 'Boot fail', True,
+                         ubman.get_spawn_output())
     except Unexpected:
-        handle_exception(ubconfig, console, log, err, 'Unexpected test output',
+        handle_exception(ubconfig, ubman_fix, log, err, 'Unexpected test output',
                          False)
-    return console
+    return ubman_fix
 
 anchors = {}
 tests_not_run = []
@@ -623,8 +631,8 @@ def cleanup():
         Nothing.
     """
 
-    if console:
-        console.close()
+    if ubman_fix:
+        ubman_fix.close()
     if log:
         with log.section('Status Report', 'status_report'):
             log.status_pass('%d passed' % len(tests_passed))
@@ -753,6 +761,26 @@ def setup_singlethread(item):
         if worker_id and worker_id != 'master':
             pytest.skip('must run single-threaded')
 
+def setup_role(item):
+    """Process any 'role' marker for a test.
+
+    Skip this test if the role does not match.
+
+    Args:
+        item (pytest.Item): The pytest test item
+    """
+    required_roles = []
+    for roles in item.iter_markers('role'):
+        role = roles.args[0]
+        if role.startswith('!'):
+            if ubconfig.role == role[1:]:
+                pytest.skip(f'role "{ubconfig.role}" not supported')
+                return
+        else:
+            required_roles.append(role)
+    if required_roles and ubconfig.role not in required_roles:
+        pytest.skip(f'board "{ubconfig.role}" not supported')
+
 def start_test_section(item):
     anchors[item.name] = log.start_section(item.name)
 
@@ -774,6 +802,7 @@ def pytest_runtest_setup(item):
     setup_buildconfigspec(item)
     setup_requiredtool(item)
     setup_singlethread(item)
+    setup_role(item)
 
 def pytest_runtest_protocol(item, nextitem):
     """pytest hook: Called to execute a test.
@@ -845,7 +874,7 @@ def pytest_runtest_protocol(item, nextitem):
         test_durations[item.name] = duration
 
     if failure_cleanup:
-        console.drain_console()
+        ubman_fix.drain_console()
 
     test_list.append(item.name)
     tests_not_run.remove(item.name)
@@ -855,7 +884,7 @@ def pytest_runtest_protocol(item, nextitem):
     except:
         # If something went wrong with logging, it's better to let the test
         # process continue, which may report other exceptions that triggered
-        # the logging issue (e.g. console.log wasn't created). Hence, just
+        # the logging issue (e.g. ubman_fix.log wasn't created). Hence, just
         # squash the exception. If the test setup failed due to e.g. syntax
         # error somewhere else, this won't be seen. However, once that issue
         # is fixed, if this exception still exists, it will then be logged as
@@ -868,6 +897,6 @@ def pytest_runtest_protocol(item, nextitem):
     log.end_section(item.name)
 
     if failure_cleanup:
-        console.cleanup_spawn()
+        ubman_fix.cleanup_spawn()
 
     return True
diff --git a/test/py/u_boot_console_base.py b/test/py/console_base.py
index 7eaceb39d9d..88d444b44b8 100644
--- a/test/py/u_boot_console_base.py
+++ b/test/py/console_base.py
@@ -13,8 +13,8 @@ import os
 import pytest
 import re
 import sys
-import u_boot_spawn
-from u_boot_spawn import BootFail, Timeout, Unexpected, handle_exception
+import spawn
+from spawn import BootFail, Timeout, Unexpected, handle_exception
 
 # Regexes for text we expect U-Boot to send to the console.
 pattern_u_boot_spl_signon = re.compile('(U-Boot SPL \\d{4}\\.\\d{2}[^\r\n]*\\))')
@@ -157,9 +157,9 @@ class ConsoleBase(object):
     def get_spawn(self):
         # This is not called, ssubclass must define this.
         # Return a value to avoid:
-        #   u_boot_console_base.py:348:12: E1128: Assigning result of a function
+        #   console_base.py:348:12: E1128: Assigning result of a function
         #   call, where the function returns None (assignment-from-none)
-        return u_boot_spawn.Spawn([])
+        return spawn.Spawn([])
 
 
     def eval_bad_patterns(self):
@@ -370,21 +370,30 @@ class ConsoleBase(object):
             output.append(self.run_command(cmd))
         return output
 
-    def ctrlc(self):
-        """Send a CTRL-C character to U-Boot.
+    def send(self, msg):
+        """Send characters without waiting for echo, etc."""
+        self.run_command(msg, wait_for_prompt=False, wait_for_echo=False,
+                         send_nl=False)
+
+    def ctrl(self, char):
+        """Send a CTRL- character to U-Boot.
 
         This is useful in order to stop execution of long-running synchronous
         commands such as "ums".
 
         Args:
-            None.
-
-        Returns:
-            Nothing.
+            char (str): Character to send, e.g. 'C' to send Ctrl-C
         """
+        self.log.action(f'Sending Ctrl-{char}')
+        self.send(chr(ord(char) - ord('@')))
 
-        self.log.action('Sending Ctrl-C')
-        self.run_command(chr(3), wait_for_echo=False, send_nl=False)
+    def ctrlc(self):
+        """Send a CTRL-C character to U-Boot.
+
+        This is useful in order to stop execution of long-running synchronous
+        commands such as "ums".
+        """
+        self.ctrl('C')
 
     def wait_for(self, text):
         """Wait for a pattern to be emitted by U-Boot.
diff --git a/test/py/u_boot_console_exec_attach.py b/test/py/console_board.py
index 8b253b4451d..bacb1e2526c 100644
--- a/test/py/u_boot_console_exec_attach.py
+++ b/test/py/console_board.py
@@ -8,8 +8,8 @@ physical serial port.
 """
 
 import sys
-from u_boot_spawn import Spawn
-from u_boot_console_base import ConsoleBase
+from spawn import Spawn
+from console_base import ConsoleBase
 
 class ConsoleExecAttach(ConsoleBase):
     """Represents a physical connection to a U-Boot console, typically via a
@@ -53,7 +53,7 @@ class ConsoleExecAttach(ConsoleBase):
             None.
 
         Returns:
-            A u_boot_spawn.Spawn object that is attached to U-Boot.
+            A spawn.Spawn object that is attached to U-Boot.
         """
 
         args = [self.config.board_type, self.config.board_identity]
diff --git a/test/py/u_boot_console_sandbox.py b/test/py/console_sandbox.py
index 7bc44c78b8b..da55d2fcc1f 100644
--- a/test/py/u_boot_console_sandbox.py
+++ b/test/py/console_sandbox.py
@@ -7,8 +7,8 @@ Logic to interact with the sandbox port of U-Boot, running as a sub-process.
 """
 
 import time
-from u_boot_spawn import Spawn
-from u_boot_console_base import ConsoleBase
+from spawn import Spawn
+from console_base import ConsoleBase
 
 class ConsoleSandbox(ConsoleBase):
     """Represents a connection to a sandbox U-Boot console, executed as a sub-
@@ -39,7 +39,7 @@ class ConsoleSandbox(ConsoleBase):
             None.
 
         Returns:
-            A u_boot_spawn.Spawn object that is attached to U-Boot.
+            A spawn.Spawn object that is attached to U-Boot.
         """
 
         bcfg = self.config.buildconfig
@@ -71,7 +71,7 @@ class ConsoleSandbox(ConsoleBase):
             use_dtb: True to use a device tree file, False to run without one
 
         Returns:
-            A u_boot_spawn.Spawn object that is attached to U-Boot.
+            A spawn.Spawn object that is attached to U-Boot.
         """
 
         try:
diff --git a/test/py/pytest.ini b/test/py/pytest.ini
index 26d83f83e00..361be0178ee 100644
--- a/test/py/pytest.ini
+++ b/test/py/pytest.ini
@@ -12,3 +12,4 @@ markers =
     requiredtool: U-Boot: Required host tools for a test.
     slow: U-Boot: Specific test will run slowly.
     singlethread: Cannot run in parallel
+    role: U-Boot: Indicates the lab 'role' which can execute this test
diff --git a/test/py/requirements.txt b/test/py/requirements.txt
index 75760f96e56..804a427b351 100644
--- a/test/py/requirements.txt
+++ b/test/py/requirements.txt
@@ -1,30 +1,5 @@
-atomicwrites==1.4.1
-attrs==19.3.0
-concurrencytest==0.1.2
-coverage==6.2
-extras==1.0.0
 filelock==3.0.12
-fixtures==3.0.0
-importlib-metadata==0.23
-linecache2==1.0.0
-more-itertools==7.2.0
-packaging==24.1
-pbr==5.4.3
-pluggy==0.13.0
-py==1.11.0
-pycryptodomex==3.19.1
-pyelftools==0.27
-pygit2==1.13.3
-pyparsing==3.0.7
+pycryptodomex==3.21.0
 pytest==6.2.5
 pytest-xdist==2.5.0
-python-mimeparse==1.6.0
-python-subunit==1.3.0
-requests==2.32.3
-setuptools==70.3.0
-six==1.16.0
-testtools==2.3.0
-traceback2==1.4.0
-unittest2==1.1.0
-wcwidth==0.1.7
-zipp==3.19.2
+FATtools==1.0.42
diff --git a/test/py/u_boot_spawn.py b/test/py/spawn.py
index c703454389d..c703454389d 100644
--- a/test/py/u_boot_spawn.py
+++ b/test/py/spawn.py
diff --git a/test/py/tests/fit_util.py b/test/py/tests/fit_util.py
index 79718d431a0..f322b50a319 100644
--- a/test/py/tests/fit_util.py
+++ b/test/py/tests/fit_util.py
@@ -5,25 +5,25 @@
 
 import os
 
-import u_boot_utils as util
+import utils
 
-def make_fname(cons, basename):
+def make_fname(ubman, basename):
     """Make a temporary filename
 
     Args:
-        cons (ConsoleBase): u_boot_console to use
+        ubman (ConsoleBase): ubman to use
         basename (str): Base name of file to create (within temporary directory)
     Return:
         Temporary filename
     """
 
-    return os.path.join(cons.config.build_dir, basename)
+    return os.path.join(ubman.config.build_dir, basename)
 
-def make_its(cons, base_its, params, basename='test.its'):
+def make_its(ubman, base_its, params, basename='test.its'):
     """Make a sample .its file with parameters embedded
 
     Args:
-        cons (ConsoleBase): u_boot_console to use
+        ubman (ConsoleBase): ubman to use
         base_its (str): Template text for the .its file, typically containing
             %() references
         params (dict of str): Parameters to embed in the %() strings
@@ -31,19 +31,19 @@ def make_its(cons, base_its, params, basename='test.its'):
     Returns:
         str: Filename of .its file created
     """
-    its = make_fname(cons, basename)
+    its = make_fname(ubman, basename)
     with open(its, 'w', encoding='utf-8') as outf:
         print(base_its % params, file=outf)
     return its
 
-def make_fit(cons, mkimage, base_its, params, basename='test.fit', base_fdt=None):
+def make_fit(ubman, mkimage, base_its, params, basename='test.fit', base_fdt=None):
     """Make a sample .fit file ready for loading
 
     This creates a .its script with the selected parameters and uses mkimage to
     turn this into a .fit image.
 
     Args:
-        cons (ConsoleBase): u_boot_console to use
+        ubman (ConsoleBase): ubman to use
         mkimage (str): Filename of 'mkimage' utility
         base_its (str): Template text for the .its file, typically containing
             %() references
@@ -52,25 +52,25 @@ def make_fit(cons, mkimage, base_its, params, basename='test.fit', base_fdt=None
     Return:
         Filename of .fit file created
     """
-    fit = make_fname(cons, basename)
-    its = make_its(cons, base_its, params)
-    util.run_and_log(cons, [mkimage, '-f', its, fit])
+    fit = make_fname(ubman, basename)
+    its = make_its(ubman, base_its, params)
+    utils.run_and_log(ubman, [mkimage, '-f', its, fit])
     if base_fdt:
-        with open(make_fname(cons, 'u-boot.dts'), 'w') as fd:
+        with open(make_fname(ubman, 'u-boot.dts'), 'w') as fd:
             fd.write(base_fdt)
     return fit
 
-def make_kernel(cons, basename, text):
+def make_kernel(ubman, basename, text):
     """Make a sample kernel with test data
 
     Args:
-        cons (ConsoleBase): u_boot_console to use
+        ubman (ConsoleBase): ubman to use
         basename (str): base name to write to (will be placed in the temp dir)
         text (str): Contents of the kernel file (will be repeated 100 times)
     Returns:
         str: Full path and filename of the kernel it created
     """
-    fname = make_fname(cons, basename)
+    fname = make_fname(ubman, basename)
     data = ''
     for i in range(100):
         data += f'this {text} {i} is unlikely to boot\n'
@@ -78,16 +78,16 @@ def make_kernel(cons, basename, text):
         print(data, file=outf)
     return fname
 
-def make_dtb(cons, base_fdt, basename):
+def make_dtb(ubman, base_fdt, basename):
     """Make a sample .dts file and compile it to a .dtb
 
     Returns:
-        cons (ConsoleBase): u_boot_console to use
+        ubman (ConsoleBase): ubman to use
         Filename of .dtb file created
     """
-    src = make_fname(cons, f'{basename}.dts')
-    dtb = make_fname(cons, f'{basename}.dtb')
+    src = make_fname(ubman, f'{basename}.dts')
+    dtb = make_fname(ubman, f'{basename}.dtb')
     with open(src, 'w', encoding='utf-8') as outf:
         outf.write(base_fdt)
-    util.run_and_log(cons, ['dtc', src, '-O', 'dtb', '-o', dtb])
+    utils.run_and_log(ubman, ['dtc', src, '-O', 'dtb', '-o', dtb])
     return dtb
diff --git a/test/py/tests/fs_helper.py b/test/py/tests/fs_helper.py
index ccfc0201a49..9c459fccf97 100644
--- a/test/py/tests/fs_helper.py
+++ b/test/py/tests/fs_helper.py
@@ -35,7 +35,9 @@ def mk_fs(config, fs_type, size, prefix, src_dir=None, size_gran = 0x100000):
     else:
         mkfs_opt = ''
 
-    if re.match('fat', fs_type):
+    if fs_type == 'exfat':
+        fs_lnxtype = 'exfat'
+    elif re.match('fat', fs_type) or fs_type == 'fs_generic':
         fs_lnxtype = 'vfat'
     else:
         fs_lnxtype = fs_type
@@ -43,7 +45,7 @@ def mk_fs(config, fs_type, size, prefix, src_dir=None, size_gran = 0x100000):
     if src_dir:
         if fs_lnxtype == 'ext4':
             mkfs_opt = mkfs_opt + ' -d ' + src_dir
-        elif fs_lnxtype != 'vfat':
+        elif fs_lnxtype != 'vfat' and fs_lnxtype != 'exfat':
             raise ValueError(f'src_dir not implemented for fs {fs_lnxtype}')
 
     count = (size + size_gran - 1) // size_gran
@@ -54,7 +56,7 @@ def mk_fs(config, fs_type, size, prefix, src_dir=None, size_gran = 0x100000):
 
     try:
         check_call(f'rm -f {fs_img}', shell=True)
-        check_call(f'dd if=/dev/zero of={fs_img} bs={size_gran} count={count}',
+        check_call(f'truncate -s $(( {size_gran} * {count} )) {fs_img}',
                    shell=True)
         check_call(f'mkfs.{fs_lnxtype} {mkfs_opt} {fs_img}', shell=True)
         if fs_type == 'ext4':
@@ -64,6 +66,8 @@ def mk_fs(config, fs_type, size, prefix, src_dir=None, size_gran = 0x100000):
                 check_call(f'tune2fs -O ^metadata_csum {fs_img}', shell=True)
         elif fs_lnxtype == 'vfat' and src_dir:
             check_call(f'mcopy -i {fs_img} -vsmpQ {src_dir}/* ::/', shell=True)
+        elif fs_lnxtype == 'exfat' and src_dir:
+            check_call(f'fattools cp {src_dir}/* {fs_img}', shell=True)
         return fs_img
     except CalledProcessError:
         call(f'rm -f {fs_img}', shell=True)
diff --git a/test/py/tests/test_000_version.py b/test/py/tests/test_000_version.py
index bd089ab5439..b95ceae2346 100644
--- a/test/py/tests/test_000_version.py
+++ b/test/py/tests/test_000_version.py
@@ -7,13 +7,13 @@
 # first, simply as a very basic sanity check of the functionality of the U-Boot
 # command prompt.
 
-def test_version(u_boot_console):
+def test_version(ubman):
     """Test that the "version" command prints the U-Boot version."""
 
     # "version" prints the U-Boot sign-on message. This is usually considered
     # an error, so that any unexpected reboot causes an error. Here, this
     # error detection is disabled since the sign-on message is expected.
-    with u_boot_console.disable_check('main_signon'):
-        response = u_boot_console.run_command('version')
+    with ubman.disable_check('main_signon'):
+        response = ubman.run_command('version')
     # Ensure "version" printed what we expected.
-    u_boot_console.validate_version_string_in_text(response)
+    ubman.validate_version_string_in_text(response)
diff --git a/test/py/tests/test_android/test_ab.py b/test/py/tests/test_android/test_ab.py
index 9bf1a0eb00a..5876a137463 100644
--- a/test/py/tests/test_android/test_ab.py
+++ b/test/py/tests/test_android/test_ab.py
@@ -5,16 +5,16 @@
 
 import os
 import pytest
-import u_boot_utils
+import utils
 
 class ABTestDiskImage(object):
     """Disk Image used by the A/B tests."""
 
-    def __init__(self, u_boot_console):
+    def __init__(self, ubman):
         """Initialize a new ABTestDiskImage object.
 
         Args:
-            u_boot_console: A U-Boot console.
+            ubman: A U-Boot console.
 
         Returns:
             Nothing.
@@ -22,40 +22,40 @@ class ABTestDiskImage(object):
 
         filename = 'test_ab_disk_image.bin'
 
-        persistent = u_boot_console.config.persistent_data_dir + '/' + filename
-        self.path = u_boot_console.config.result_dir  + '/' + filename
+        persistent = ubman.config.persistent_data_dir + '/' + filename
+        self.path = ubman.config.result_dir  + '/' + filename
 
-        with u_boot_utils.persistent_file_helper(u_boot_console.log, persistent):
+        with utils.persistent_file_helper(ubman.log, persistent):
             if os.path.exists(persistent):
-                u_boot_console.log.action('Disk image file ' + persistent +
+                ubman.log.action('Disk image file ' + persistent +
                     ' already exists')
             else:
-                u_boot_console.log.action('Generating ' + persistent)
+                ubman.log.action('Generating ' + persistent)
                 fd = os.open(persistent, os.O_RDWR | os.O_CREAT)
                 os.ftruncate(fd, 524288)
                 os.close(fd)
                 cmd = ('sgdisk', persistent)
-                u_boot_utils.run_and_log(u_boot_console, cmd)
+                utils.run_and_log(ubman, cmd)
 
                 cmd = ('sgdisk', '--new=1:64:512', '--change-name=1:misc',
                     persistent)
-                u_boot_utils.run_and_log(u_boot_console, cmd)
+                utils.run_and_log(ubman, cmd)
                 cmd = ('sgdisk', '--load-backup=' + persistent)
-                u_boot_utils.run_and_log(u_boot_console, cmd)
+                utils.run_and_log(ubman, cmd)
 
         cmd = ('cp', persistent, self.path)
-        u_boot_utils.run_and_log(u_boot_console, cmd)
+        utils.run_and_log(ubman, cmd)
 
 di = None
 @pytest.fixture(scope='function')
-def ab_disk_image(u_boot_console):
+def ab_disk_image(ubman):
     global di
     if not di:
-        di = ABTestDiskImage(u_boot_console)
+        di = ABTestDiskImage(ubman)
     return di
 
-def ab_dump(u_boot_console, slot_num, crc):
-    output = u_boot_console.run_command('bcb ab_dump host 0#misc')
+def ab_dump(ubman, slot_num, crc):
+    output = ubman.run_command('bcb ab_dump host 0#misc')
     header, slot0, slot1 = output.split('\r\r\n\r\r\n')
     slots = [slot0, slot1]
     slot_suffixes = ['_a', '_b']
@@ -79,20 +79,20 @@ def ab_dump(u_boot_console, slot_num, crc):
 @pytest.mark.buildconfigspec('android_ab')
 @pytest.mark.buildconfigspec('cmd_bcb')
 @pytest.mark.requiredtool('sgdisk')
-def test_ab(ab_disk_image, u_boot_console):
+def test_ab(ab_disk_image, ubman):
     """Test the 'bcb ab_select' command."""
 
-    u_boot_console.run_command('host bind 0 ' + ab_disk_image.path)
+    ubman.run_command('host bind 0 ' + ab_disk_image.path)
 
-    output = u_boot_console.run_command('bcb ab_select slot_name host 0#misc')
+    output = ubman.run_command('bcb ab_select slot_name host 0#misc')
     assert 're-initializing A/B metadata' in output
     assert 'Attempting slot a, tries remaining 7' in output
-    output = u_boot_console.run_command('printenv slot_name')
+    output = ubman.run_command('printenv slot_name')
     assert 'slot_name=a' in output
-    ab_dump(u_boot_console, 0, '0xd438d1b9')
+    ab_dump(ubman, 0, '0xd438d1b9')
 
-    output = u_boot_console.run_command('bcb ab_select slot_name host 0:1')
+    output = ubman.run_command('bcb ab_select slot_name host 0:1')
     assert 'Attempting slot b, tries remaining 7' in output
-    output = u_boot_console.run_command('printenv slot_name')
+    output = ubman.run_command('printenv slot_name')
     assert 'slot_name=b' in output
-    ab_dump(u_boot_console, 1, '0x011ec016')
+    ab_dump(ubman, 1, '0x011ec016')
diff --git a/test/py/tests/test_android/test_abootimg.py b/test/py/tests/test_android/test_abootimg.py
index 6a8ff34538b..2aadb692b30 100644
--- a/test/py/tests/test_android/test_abootimg.py
+++ b/test/py/tests/test_android/test_abootimg.py
@@ -6,7 +6,7 @@
 
 import os
 import pytest
-import u_boot_utils
+import utils
 
 """
 These tests rely on disk image (boot.img), which is automatically created by
@@ -105,78 +105,78 @@ dtb2_addr = vloadaddr + dtb2_offset
 class AbootimgTestDiskImage(object):
     """Disk image used by abootimg tests."""
 
-    def __init__(self, u_boot_console, image_name, hex_img):
+    def __init__(self, ubman, image_name, hex_img):
         """Initialize a new AbootimgDiskImage object.
 
         Args:
-            u_boot_console: A U-Boot console.
+            ubman: A U-Boot console.
 
         Returns:
             Nothing.
         """
 
-        gz_hex = u_boot_console.config.persistent_data_dir + '/' + image_name  + '.gz.hex'
-        gz = u_boot_console.config.persistent_data_dir + '/' + image_name + '.gz'
+        gz_hex = ubman.config.persistent_data_dir + '/' + image_name  + '.gz.hex'
+        gz = ubman.config.persistent_data_dir + '/' + image_name + '.gz'
 
         filename = image_name
-        persistent = u_boot_console.config.persistent_data_dir + '/' + filename
-        self.path = u_boot_console.config.result_dir  + '/' + filename
-        u_boot_console.log.action('persistent is ' + persistent)
-        with u_boot_utils.persistent_file_helper(u_boot_console.log, persistent):
+        persistent = ubman.config.persistent_data_dir + '/' + filename
+        self.path = ubman.config.result_dir  + '/' + filename
+        ubman.log.action('persistent is ' + persistent)
+        with utils.persistent_file_helper(ubman.log, persistent):
             if os.path.exists(persistent):
-                u_boot_console.log.action('Disk image file ' + persistent +
+                ubman.log.action('Disk image file ' + persistent +
                     ' already exists')
             else:
-                u_boot_console.log.action('Generating ' + persistent)
+                ubman.log.action('Generating ' + persistent)
 
                 f = open(gz_hex, "w")
                 f.write(hex_img)
                 f.close()
                 cmd = ('xxd', '-r', '-p', gz_hex, gz)
-                u_boot_utils.run_and_log(u_boot_console, cmd)
+                utils.run_and_log(ubman, cmd)
                 cmd = ('gunzip', '-9', gz)
-                u_boot_utils.run_and_log(u_boot_console, cmd)
+                utils.run_and_log(ubman, cmd)
 
         cmd = ('cp', persistent, self.path)
-        u_boot_utils.run_and_log(u_boot_console, cmd)
+        utils.run_and_log(ubman, cmd)
 
 gtdi1 = None
 @pytest.fixture(scope='function')
-def abootimg_disk_image(u_boot_console):
+def abootimg_disk_image(ubman):
     """pytest fixture to provide a AbootimgTestDiskImage object to tests.
-    This is function-scoped because it uses u_boot_console, which is also
+    This is function-scoped because it uses ubman, which is also
     function-scoped. However, we don't need to actually do any function-scope
     work, so this simply returns the same object over and over each time."""
 
     global gtdi1
     if not gtdi1:
-        gtdi1 = AbootimgTestDiskImage(u_boot_console, 'boot.img', img_hex)
+        gtdi1 = AbootimgTestDiskImage(ubman, 'boot.img', img_hex)
     return gtdi1
 
 gtdi2 = None
 @pytest.fixture(scope='function')
-def abootimgv4_disk_image_vboot(u_boot_console):
+def abootimgv4_disk_image_vboot(ubman):
     """pytest fixture to provide a AbootimgTestDiskImage object to tests.
-    This is function-scoped because it uses u_boot_console, which is also
+    This is function-scoped because it uses ubman, which is also
     function-scoped. However, we don't need to actually do any function-scope
     work, so this simply returns the same object over and over each time."""
 
     global gtdi2
     if not gtdi2:
-        gtdi2 = AbootimgTestDiskImage(u_boot_console, 'vendor_boot.img', vboot_img_hex)
+        gtdi2 = AbootimgTestDiskImage(ubman, 'vendor_boot.img', vboot_img_hex)
     return gtdi2
 
 gtdi3 = None
 @pytest.fixture(scope='function')
-def abootimgv4_disk_image_boot(u_boot_console):
+def abootimgv4_disk_image_boot(ubman):
     """pytest fixture to provide a AbootimgTestDiskImage object to tests.
-    This is function-scoped because it uses u_boot_console, which is also
+    This is function-scoped because it uses ubman, which is also
     function-scoped. However, we don't need to actually do any function-scope
     work, so this simply returns the same object over and over each time."""
 
     global gtdi3
     if not gtdi3:
-        gtdi3 = AbootimgTestDiskImage(u_boot_console, 'bootv4.img', boot_img_hex)
+        gtdi3 = AbootimgTestDiskImage(ubman, 'bootv4.img', boot_img_hex)
     return gtdi3
 
 @pytest.mark.boardspec('sandbox')
@@ -185,42 +185,42 @@ def abootimgv4_disk_image_boot(u_boot_console):
 @pytest.mark.buildconfigspec('cmd_fdt')
 @pytest.mark.requiredtool('xxd')
 @pytest.mark.requiredtool('gunzip')
-def test_abootimg(abootimg_disk_image, u_boot_console):
+def test_abootimg(abootimg_disk_image, ubman):
     """Test the 'abootimg' command."""
 
-    u_boot_console.log.action('Loading disk image to RAM...')
-    u_boot_console.run_command('setenv loadaddr 0x%x' % (loadaddr))
-    u_boot_console.run_command('host load hostfs - 0x%x %s' % (loadaddr,
+    ubman.log.action('Loading disk image to RAM...')
+    ubman.run_command('setenv loadaddr 0x%x' % (loadaddr))
+    ubman.run_command('host load hostfs - 0x%x %s' % (loadaddr,
         abootimg_disk_image.path))
 
-    u_boot_console.log.action('Testing \'abootimg get ver\'...')
-    response = u_boot_console.run_command('abootimg get ver')
+    ubman.log.action('Testing \'abootimg get ver\'...')
+    response = ubman.run_command('abootimg get ver')
     assert response == "2"
-    u_boot_console.run_command('abootimg get ver v')
-    response = u_boot_console.run_command('env print v')
+    ubman.run_command('abootimg get ver v')
+    response = ubman.run_command('env print v')
     assert response == 'v=2'
 
-    u_boot_console.log.action('Testing \'abootimg get recovery_dtbo\'...')
-    response = u_boot_console.run_command('abootimg get recovery_dtbo a')
+    ubman.log.action('Testing \'abootimg get recovery_dtbo\'...')
+    response = ubman.run_command('abootimg get recovery_dtbo a')
     assert response == 'Error: recovery_dtbo_size is 0'
 
-    u_boot_console.log.action('Testing \'abootimg dump dtb\'...')
-    response = u_boot_console.run_command('abootimg dump dtb').replace('\r', '')
+    ubman.log.action('Testing \'abootimg dump dtb\'...')
+    response = ubman.run_command('abootimg dump dtb').replace('\r', '')
     assert response == dtb_dump_resp
 
-    u_boot_console.log.action('Testing \'abootimg get dtb_load_addr\'...')
-    u_boot_console.run_command('abootimg get dtb_load_addr a')
-    response = u_boot_console.run_command('env print a')
+    ubman.log.action('Testing \'abootimg get dtb_load_addr\'...')
+    ubman.run_command('abootimg get dtb_load_addr a')
+    response = ubman.run_command('env print a')
     assert response == 'a=11f00000'
 
-    u_boot_console.log.action('Testing \'abootimg get dtb --index\'...')
-    u_boot_console.run_command('abootimg get dtb --index=1 dtb1_start')
-    response = u_boot_console.run_command('env print dtb1_start')
+    ubman.log.action('Testing \'abootimg get dtb --index\'...')
+    ubman.run_command('abootimg get dtb --index=1 dtb1_start')
+    response = ubman.run_command('env print dtb1_start')
     correct_str = "dtb1_start=%x" % (dtb1_addr)
     assert response == correct_str
-    u_boot_console.run_command('fdt addr $dtb1_start')
-    u_boot_console.run_command('fdt get value v / model')
-    response = u_boot_console.run_command('env print v')
+    ubman.run_command('fdt addr $dtb1_start')
+    ubman.run_command('fdt get value v / model')
+    response = ubman.run_command('env print v')
     assert response == 'v=x2'
 
 @pytest.mark.boardspec('sandbox')
@@ -229,41 +229,40 @@ def test_abootimg(abootimg_disk_image, u_boot_console):
 @pytest.mark.buildconfigspec('cmd_fdt')
 @pytest.mark.requiredtool('xxd')
 @pytest.mark.requiredtool('gunzip')
-def test_abootimgv4(abootimgv4_disk_image_vboot, abootimgv4_disk_image_boot, u_boot_console):
+def test_abootimgv4(abootimgv4_disk_image_vboot, abootimgv4_disk_image_boot, ubman):
     """Test the 'abootimg' command with boot image header v4."""
 
-    cons = u_boot_console
-    cons.log.action('Loading disk image to RAM...')
-    cons.run_command('setenv loadaddr 0x%x' % (loadaddr))
-    cons.run_command('setenv vloadaddr 0x%x' % (vloadaddr))
-    cons.run_command('host load hostfs - 0x%x %s' % (vloadaddr,
+    ubman.log.action('Loading disk image to RAM...')
+    ubman.run_command('setenv loadaddr 0x%x' % (loadaddr))
+    ubman.run_command('setenv vloadaddr 0x%x' % (vloadaddr))
+    ubman.run_command('host load hostfs - 0x%x %s' % (vloadaddr,
 	abootimgv4_disk_image_vboot.path))
-    cons.run_command('host load hostfs - 0x%x %s' % (loadaddr,
+    ubman.run_command('host load hostfs - 0x%x %s' % (loadaddr,
         abootimgv4_disk_image_boot.path))
-    cons.run_command('abootimg addr 0x%x 0x%x' % (loadaddr, vloadaddr))
-    cons.log.action('Testing \'abootimg get ver\'...')
-    response = cons.run_command('abootimg get ver')
+    ubman.run_command('abootimg addr 0x%x 0x%x' % (loadaddr, vloadaddr))
+    ubman.log.action('Testing \'abootimg get ver\'...')
+    response = ubman.run_command('abootimg get ver')
     assert response == "4"
-    cons.run_command('abootimg get ver v')
-    response = cons.run_command('env print v')
+    ubman.run_command('abootimg get ver v')
+    response = ubman.run_command('env print v')
     assert response == 'v=4'
 
-    cons.log.action('Testing \'abootimg get recovery_dtbo\'...')
-    response = cons.run_command('abootimg get recovery_dtbo a')
+    ubman.log.action('Testing \'abootimg get recovery_dtbo\'...')
+    response = ubman.run_command('abootimg get recovery_dtbo a')
     assert response == 'Error: header version must be >= 1 and <= 2 to get dtbo'
 
-    cons.log.action('Testing \'abootimg get dtb_load_addr\'...')
-    cons.run_command('abootimg get dtb_load_addr a')
-    response = cons.run_command('env print a')
+    ubman.log.action('Testing \'abootimg get dtb_load_addr\'...')
+    ubman.run_command('abootimg get dtb_load_addr a')
+    response = ubman.run_command('env print a')
     assert response == 'a=11f00000'
 
-    cons.log.action('Testing \'abootimg get dtb --index\'...')
-    cons.run_command('abootimg get dtb --index=1 dtb2_start')
-    response = cons.run_command('env print dtb2_start')
+    ubman.log.action('Testing \'abootimg get dtb --index\'...')
+    ubman.run_command('abootimg get dtb --index=1 dtb2_start')
+    response = ubman.run_command('env print dtb2_start')
     correct_str = "dtb2_start=%x" % (dtb2_addr)
     assert response == correct_str
 
-    cons.run_command('fdt addr $dtb2_start')
-    cons.run_command('fdt get value v / model')
-    response = cons.run_command('env print v')
+    ubman.run_command('fdt addr $dtb2_start')
+    ubman.run_command('fdt get value v / model')
+    response = ubman.run_command('env print v')
     assert response == 'v=x2'
diff --git a/test/py/tests/test_android/test_avb.py b/test/py/tests/test_android/test_avb.py
index 865efbca4de..137d83e1dea 100644
--- a/test/py/tests/test_android/test_avb.py
+++ b/test/py/tests/test_android/test_avb.py
@@ -15,7 +15,6 @@ For configuration verification:
 """
 
 import pytest
-import u_boot_utils as util
 
 # defauld mmc id
 mmc_dev = 1
@@ -24,34 +23,34 @@ temp_addr2 = 0x90002000
 
 @pytest.mark.buildconfigspec('cmd_avb')
 @pytest.mark.buildconfigspec('cmd_mmc')
-def test_avb_verify(u_boot_console):
+def test_avb_verify(ubman):
     """Run AVB 2.0 boot verification chain with avb subset of commands
     """
 
     success_str = "Verification passed successfully"
 
-    response = u_boot_console.run_command('avb init %s' %str(mmc_dev))
+    response = ubman.run_command('avb init %s' %str(mmc_dev))
     assert response == ''
-    response = u_boot_console.run_command('avb verify')
+    response = ubman.run_command('avb verify')
     assert response.find(success_str)
 
 
 @pytest.mark.buildconfigspec('cmd_avb')
 @pytest.mark.buildconfigspec('cmd_mmc')
 @pytest.mark.notbuildconfigspec('sandbox')
-def test_avb_mmc_uuid(u_boot_console):
+def test_avb_mmc_uuid(ubman):
     """Check if 'avb get_uuid' works, compare results with
     'part list mmc 1' output
     """
 
-    response = u_boot_console.run_command('avb init %s' % str(mmc_dev))
+    response = ubman.run_command('avb init %s' % str(mmc_dev))
     assert response == ''
 
-    response = u_boot_console.run_command('mmc rescan; mmc dev %s' %
+    response = ubman.run_command('mmc rescan; mmc dev %s' %
                                           str(mmc_dev))
     assert response.find('is current device')
 
-    part_lines = u_boot_console.run_command('mmc part').splitlines()
+    part_lines = ubman.run_command('mmc part').splitlines()
     part_list = {}
     cur_partname = ''
 
@@ -67,72 +66,72 @@ def test_avb_mmc_uuid(u_boot_console):
 
     # lets check all guids with avb get_guid
     for part, guid in part_list.items():
-        avb_guid_resp = u_boot_console.run_command('avb get_uuid %s' % part)
+        avb_guid_resp = ubman.run_command('avb get_uuid %s' % part)
         assert guid == avb_guid_resp.split('UUID: ')[1]
 
 
 @pytest.mark.buildconfigspec('cmd_avb')
-def test_avb_read_rb(u_boot_console):
+def test_avb_read_rb(ubman):
     """Test reading rollback indexes
     """
 
-    response = u_boot_console.run_command('avb init %s' % str(mmc_dev))
+    response = ubman.run_command('avb init %s' % str(mmc_dev))
     assert response == ''
 
-    response = u_boot_console.run_command('avb read_rb 1')
+    response = ubman.run_command('avb read_rb 1')
     assert response == 'Rollback index: 0'
 
 
 @pytest.mark.buildconfigspec('cmd_avb')
-def test_avb_is_unlocked(u_boot_console):
+def test_avb_is_unlocked(ubman):
     """Test if device is in the unlocked state
     """
 
-    response = u_boot_console.run_command('avb init %s' % str(mmc_dev))
+    response = ubman.run_command('avb init %s' % str(mmc_dev))
     assert response == ''
 
-    response = u_boot_console.run_command('avb is_unlocked')
+    response = ubman.run_command('avb is_unlocked')
     assert response == 'Unlocked = 1'
 
 
 @pytest.mark.buildconfigspec('cmd_avb')
 @pytest.mark.buildconfigspec('cmd_mmc')
 @pytest.mark.notbuildconfigspec('sandbox')
-def test_avb_mmc_read(u_boot_console):
+def test_avb_mmc_read(ubman):
     """Test mmc read operation
     """
 
-    response = u_boot_console.run_command('mmc rescan; mmc dev %s 0' %
+    response = ubman.run_command('mmc rescan; mmc dev %s 0' %
                                           str(mmc_dev))
     assert response.find('is current device')
 
-    response = u_boot_console.run_command('mmc read 0x%x 0x100 0x1' % temp_addr)
+    response = ubman.run_command('mmc read 0x%x 0x100 0x1' % temp_addr)
     assert response.find('read: OK')
 
-    response = u_boot_console.run_command('avb init %s' % str(mmc_dev))
+    response = ubman.run_command('avb init %s' % str(mmc_dev))
     assert response == ''
 
-    response = u_boot_console.run_command('avb read_part xloader 0 100 0x%x' %
+    response = ubman.run_command('avb read_part xloader 0 100 0x%x' %
                                            temp_addr2)
     assert response.find('Read 512 bytes')
 
     # Now lets compare two buffers
-    response = u_boot_console.run_command('cmp 0x%x 0x%x 40' %
+    response = ubman.run_command('cmp 0x%x 0x%x 40' %
                                           (temp_addr, temp_addr2))
     assert response.find('64 word')
 
 
 @pytest.mark.buildconfigspec('cmd_avb')
 @pytest.mark.buildconfigspec('optee_ta_avb')
-def test_avb_persistent_values(u_boot_console):
+def test_avb_persistent_values(ubman):
     """Test reading/writing persistent storage to avb
     """
 
-    response = u_boot_console.run_command('avb init %s' % str(mmc_dev))
+    response = ubman.run_command('avb init %s' % str(mmc_dev))
     assert response == ''
 
-    response = u_boot_console.run_command('avb write_pvalue test value_value')
+    response = ubman.run_command('avb write_pvalue test value_value')
     assert response == 'Wrote 12 bytes'
 
-    response = u_boot_console.run_command('avb read_pvalue test 12')
+    response = ubman.run_command('avb read_pvalue test 12')
     assert response == 'Read 12 bytes, value = value_value'
diff --git a/test/py/tests/test_bind.py b/test/py/tests/test_bind.py
index 1376ab5ed28..16c63ae9684 100644
--- a/test/py/tests/test_bind.py
+++ b/test/py/tests/test_bind.py
@@ -27,82 +27,82 @@ def in_tree(response, name, uclass, drv, depth, last_child):
 
 @pytest.mark.boardspec('sandbox')
 @pytest.mark.buildconfigspec('cmd_bind')
-def test_bind_unbind_with_node(u_boot_console):
+def test_bind_unbind_with_node(ubman):
 
-    tree = u_boot_console.run_command('dm tree')
+    tree = ubman.run_command('dm tree')
     assert in_tree(tree, 'bind-test', 'simple_bus', 'simple_bus', 0, True)
     assert in_tree(tree, 'bind-test-child1', 'phy', 'phy_sandbox', 1, False)
     assert in_tree(tree, 'bind-test-child2', 'simple_bus', 'simple_bus', 1, True)
 
     #bind usb_ether driver (which has no compatible) to usb@1 node.
     ##New entry usb_ether should appear in the dm tree
-    response = u_boot_console.run_command('bind  /usb@1 usb_ether')
+    response = ubman.run_command('bind  /usb@1 usb_ether')
     assert response == ''
-    tree = u_boot_console.run_command('dm tree')
+    tree = ubman.run_command('dm tree')
     assert in_tree(tree, 'usb@1', 'ethernet', 'usb_ether', 1, True)
 
     #Unbind child #1. No error expected and all devices should be there except for bind-test-child1
-    response = u_boot_console.run_command('unbind  /bind-test/bind-test-child1')
+    response = ubman.run_command('unbind  /bind-test/bind-test-child1')
     assert response == ''
-    tree = u_boot_console.run_command('dm tree')
+    tree = ubman.run_command('dm tree')
     assert in_tree(tree, 'bind-test', 'simple_bus', 'simple_bus', 0, True)
     assert 'bind-test-child1' not in tree
     assert in_tree(tree, 'bind-test-child2', 'simple_bus', 'simple_bus', 1, True)
 
     #bind child #1. No error expected and all devices should be there
-    response = u_boot_console.run_command('bind  /bind-test/bind-test-child1 phy_sandbox')
+    response = ubman.run_command('bind  /bind-test/bind-test-child1 phy_sandbox')
     assert response == ''
-    tree = u_boot_console.run_command('dm tree')
+    tree = ubman.run_command('dm tree')
     assert in_tree(tree, 'bind-test', 'simple_bus', 'simple_bus', 0, True)
     assert in_tree(tree, 'bind-test-child1', 'phy', 'phy_sandbox', 1, True)
     assert in_tree(tree, 'bind-test-child2', 'simple_bus', 'simple_bus', 1, False)
 
     #Unbind child #2. No error expected and all devices should be there except for bind-test-child2
-    response = u_boot_console.run_command('unbind  /bind-test/bind-test-child2')
+    response = ubman.run_command('unbind  /bind-test/bind-test-child2')
     assert response == ''
-    tree = u_boot_console.run_command('dm tree')
+    tree = ubman.run_command('dm tree')
     assert in_tree(tree, 'bind-test', 'simple_bus', 'simple_bus', 0, True)
     assert in_tree(tree, 'bind-test-child1', 'phy', 'phy_sandbox', 1, True)
     assert 'bind-test-child2' not in tree
 
 
     #Bind child #2. No error expected and all devices should be there
-    response = u_boot_console.run_command('bind /bind-test/bind-test-child2 simple_bus')
+    response = ubman.run_command('bind /bind-test/bind-test-child2 simple_bus')
     assert response == ''
-    tree = u_boot_console.run_command('dm tree')
+    tree = ubman.run_command('dm tree')
     assert in_tree(tree, 'bind-test', 'simple_bus', 'simple_bus', 0, True)
     assert in_tree(tree, 'bind-test-child1', 'phy', 'phy_sandbox', 1, False)
     assert in_tree(tree, 'bind-test-child2', 'simple_bus', 'simple_bus', 1, True)
 
     #Unbind parent. No error expected. All devices should be removed and unbound
-    response = u_boot_console.run_command('unbind  /bind-test')
+    response = ubman.run_command('unbind  /bind-test')
     assert response == ''
-    tree = u_boot_console.run_command('dm tree')
+    tree = ubman.run_command('dm tree')
     assert 'bind-test' not in tree
     assert 'bind-test-child1' not in tree
     assert 'bind-test-child2' not in tree
 
     #try binding invalid node with valid driver
-    response = u_boot_console.run_command('bind  /not-a-valid-node simple_bus')
+    response = ubman.run_command('bind  /not-a-valid-node simple_bus')
     assert response != ''
-    tree = u_boot_console.run_command('dm tree')
+    tree = ubman.run_command('dm tree')
     assert 'not-a-valid-node' not in tree
 
     #try binding valid node with invalid driver
-    response = u_boot_console.run_command('bind  /bind-test not_a_driver')
+    response = ubman.run_command('bind  /bind-test not_a_driver')
     assert response != ''
-    tree = u_boot_console.run_command('dm tree')
+    tree = ubman.run_command('dm tree')
     assert 'bind-test' not in tree
 
     #bind /bind-test. Device should come up as well as its children
-    response = u_boot_console.run_command('bind  /bind-test simple_bus')
+    response = ubman.run_command('bind  /bind-test simple_bus')
     assert response == ''
-    tree = u_boot_console.run_command('dm tree')
+    tree = ubman.run_command('dm tree')
     assert in_tree(tree, 'bind-test', 'simple_bus', 'simple_bus', 0, True)
     assert in_tree(tree, 'bind-test-child1', 'phy', 'phy_sandbox', 1, False)
     assert in_tree(tree, 'bind-test-child2', 'simple_bus', 'simple_bus', 1, True)
 
-    response = u_boot_console.run_command('unbind  /bind-test')
+    response = ubman.run_command('unbind  /bind-test')
     assert response == ''
 
 def get_next_line(tree, name):
@@ -120,13 +120,13 @@ def get_next_line(tree, name):
 @pytest.mark.boardspec('sandbox')
 @pytest.mark.buildconfigspec('cmd_bind')
 @pytest.mark.singlethread
-def test_bind_unbind_with_uclass(u_boot_console):
+def test_bind_unbind_with_uclass(ubman):
     #bind /bind-test
-    response = u_boot_console.run_command('bind  /bind-test simple_bus')
+    response = ubman.run_command('bind  /bind-test simple_bus')
     assert response == ''
 
     #make sure bind-test-child2 is there and get its uclass/index pair
-    tree = u_boot_console.run_command('dm tree')
+    tree = ubman.run_command('dm tree')
     child2_line = [x.strip() for x in tree.splitlines() if '-- bind-test-child2' in x]
     assert len(child2_line) == 1
 
@@ -134,11 +134,11 @@ def test_bind_unbind_with_uclass(u_boot_console):
     child2_index = int(child2_line[0].split()[1])
 
     #bind simple_bus as a child of bind-test-child2
-    response = u_boot_console.run_command(
+    response = ubman.run_command(
                     'bind  {} {} simple_bus'.format(child2_uclass, child2_index))
 
     #check that the child is there and its uclass/index pair is right
-    tree = u_boot_console.run_command('dm tree')
+    tree = ubman.run_command('dm tree')
 
     child_of_child2_line = get_next_line(tree, 'bind-test-child2')
     assert child_of_child2_line
@@ -147,20 +147,20 @@ def test_bind_unbind_with_uclass(u_boot_console):
     assert child_of_child2_index == child2_index + 1
 
     #unbind the child and check it has been removed
-    response = u_boot_console.run_command('unbind  simple_bus {}'.format(child_of_child2_index))
+    response = ubman.run_command('unbind  simple_bus {}'.format(child_of_child2_index))
     assert response == ''
-    tree = u_boot_console.run_command('dm tree')
+    tree = ubman.run_command('dm tree')
     assert in_tree(tree, 'bind-test-child2', 'simple_bus', 'simple_bus', 1, True)
     assert not in_tree(tree, 'simple_bus', 'simple_bus', 'simple_bus', 2, True)
     child_of_child2_line = get_next_line(tree, 'bind-test-child2')
     assert child_of_child2_line == ''
 
     #bind simple_bus as a child of bind-test-child2
-    response = u_boot_console.run_command(
+    response = ubman.run_command(
                     'bind  {} {} simple_bus'.format(child2_uclass, child2_index))
 
     #check that the child is there and its uclass/index pair is right
-    tree = u_boot_console.run_command('dm tree')
+    tree = ubman.run_command('dm tree')
     treelines = [x.strip() for x in tree.splitlines() if x.strip()]
 
     child_of_child2_line = get_next_line(tree, 'bind-test-child2')
@@ -170,24 +170,24 @@ def test_bind_unbind_with_uclass(u_boot_console):
     assert child_of_child2_index == child2_index + 1
 
     #unbind the child and check it has been removed
-    response = u_boot_console.run_command(
+    response = ubman.run_command(
                     'unbind  {} {} simple_bus'.format(child2_uclass, child2_index))
     assert response == ''
 
-    tree = u_boot_console.run_command('dm tree')
+    tree = ubman.run_command('dm tree')
     assert in_tree(tree, 'bind-test-child2', 'simple_bus', 'simple_bus', 1, True)
 
     child_of_child2_line = get_next_line(tree, 'bind-test-child2')
     assert child_of_child2_line == ''
 
     #unbind the child again and check it doesn't change the tree
-    tree_old = u_boot_console.run_command('dm tree')
-    response = u_boot_console.run_command(
+    tree_old = ubman.run_command('dm tree')
+    response = ubman.run_command(
                     'unbind  {} {} simple_bus'.format(child2_uclass, child2_index))
-    tree_new = u_boot_console.run_command('dm tree')
+    tree_new = ubman.run_command('dm tree')
 
     assert response == ''
     assert tree_old == tree_new
 
-    response = u_boot_console.run_command('unbind  /bind-test')
+    response = ubman.run_command('unbind  /bind-test')
     assert response == ''
diff --git a/test/py/tests/test_bootmenu.py b/test/py/tests/test_bootmenu.py
index 70f51de699f..66f3fb8a131 100644
--- a/test/py/tests/test_bootmenu.py
+++ b/test/py/tests/test_bootmenu.py
@@ -5,42 +5,42 @@
 import pytest
 
 @pytest.mark.buildconfigspec('cmd_bootmenu')
-def test_bootmenu(u_boot_console):
+def test_bootmenu(ubman):
     """Test bootmenu
 
-    u_boot_console -- U-Boot console
+    ubman -- U-Boot console
     """
 
-    with u_boot_console.temporary_timeout(500):
-        u_boot_console.run_command('setenv bootmenu_default 1')
-        u_boot_console.run_command('setenv bootmenu_0 test 1=echo ok 1')
-        u_boot_console.run_command('setenv bootmenu_1 test 2=echo ok 2')
-        u_boot_console.run_command('setenv bootmenu_2 test 3=echo ok 3')
-        u_boot_console.run_command('bootmenu 2', wait_for_prompt=False)
+    with ubman.temporary_timeout(500):
+        ubman.run_command('setenv bootmenu_default 1')
+        ubman.run_command('setenv bootmenu_0 test 1=echo ok 1')
+        ubman.run_command('setenv bootmenu_1 test 2=echo ok 2')
+        ubman.run_command('setenv bootmenu_2 test 3=echo ok 3')
+        ubman.run_command('bootmenu 2', wait_for_prompt=False)
         for i in ('U-Boot Boot Menu', 'test 1', 'test 2', 'test 3', 'autoboot'):
-            u_boot_console.p.expect([i])
+            ubman.p.expect([i])
         # Press enter key to execute default entry
-        response = u_boot_console.run_command(cmd='\x0d', wait_for_echo=False, send_nl=False)
+        response = ubman.run_command(cmd='\x0d', wait_for_echo=False, send_nl=False)
         assert 'ok 2' in response
-        u_boot_console.run_command('bootmenu 2', wait_for_prompt=False)
-        u_boot_console.p.expect(['autoboot'])
+        ubman.run_command('bootmenu 2', wait_for_prompt=False)
+        ubman.p.expect(['autoboot'])
         # Press up key to select prior entry followed by the enter key
-        response = u_boot_console.run_command(cmd='\x1b\x5b\x41\x0d', wait_for_echo=False,
+        response = ubman.run_command(cmd='\x1b\x5b\x41\x0d', wait_for_echo=False,
                                               send_nl=False)
         assert 'ok 1' in response
-        u_boot_console.run_command('bootmenu 2', wait_for_prompt=False)
-        u_boot_console.p.expect(['autoboot'])
+        ubman.run_command('bootmenu 2', wait_for_prompt=False)
+        ubman.p.expect(['autoboot'])
         # Press down key to select next entry followed by the enter key
-        response = u_boot_console.run_command(cmd='\x1b\x5b\x42\x0d', wait_for_echo=False,
+        response = ubman.run_command(cmd='\x1b\x5b\x42\x0d', wait_for_echo=False,
                                               send_nl=False)
         assert 'ok 3' in response
-        u_boot_console.run_command('bootmenu 2; echo rc:$?', wait_for_prompt=False)
-        u_boot_console.p.expect(['autoboot'])
+        ubman.run_command('bootmenu 2; echo rc:$?', wait_for_prompt=False)
+        ubman.p.expect(['autoboot'])
         # Press the escape key
-        response = u_boot_console.run_command(cmd='\x1b', wait_for_echo=False, send_nl=False)
+        response = ubman.run_command(cmd='\x1b', wait_for_echo=False, send_nl=False)
         assert 'ok' not in response
         assert 'rc:0' in response
-        u_boot_console.run_command('setenv bootmenu_default')
-        u_boot_console.run_command('setenv bootmenu_0')
-        u_boot_console.run_command('setenv bootmenu_1')
-        u_boot_console.run_command('setenv bootmenu_2')
+        ubman.run_command('setenv bootmenu_default')
+        ubman.run_command('setenv bootmenu_0')
+        ubman.run_command('setenv bootmenu_1')
+        ubman.run_command('setenv bootmenu_2')
diff --git a/test/py/tests/test_bootstage.py b/test/py/tests/test_bootstage.py
index bd71a1af3a2..379c1cae6dd 100644
--- a/test/py/tests/test_bootstage.py
+++ b/test/py/tests/test_bootstage.py
@@ -24,8 +24,8 @@ env__bootstage_cmd_file = {
 
 @pytest.mark.buildconfigspec('bootstage')
 @pytest.mark.buildconfigspec('cmd_bootstage')
-def test_bootstage_report(u_boot_console):
-    output = u_boot_console.run_command('bootstage report')
+def test_bootstage_report(ubman):
+    output = ubman.run_command('bootstage report')
     assert 'Timer summary in microseconds' in output
     assert 'Accumulated time:' in output
     assert 'dm_r' in output
@@ -33,8 +33,8 @@ def test_bootstage_report(u_boot_console):
 @pytest.mark.buildconfigspec('bootstage')
 @pytest.mark.buildconfigspec('cmd_bootstage')
 @pytest.mark.buildconfigspec('bootstage_stash')
-def test_bootstage_stash_and_unstash(u_boot_console):
-    f = u_boot_console.config.env.get('env__bootstage_cmd_file', None)
+def test_bootstage_stash_and_unstash(ubman):
+    f = ubman.config.env.get('env__bootstage_cmd_file', None)
     if not f:
         pytest.skip('No bootstage environment file is defined')
 
@@ -43,11 +43,11 @@ def test_bootstage_stash_and_unstash(u_boot_console):
     bootstage_magic = f.get('bootstage_magic_addr')
     expected_text = 'dm_r'
 
-    u_boot_console.run_command('bootstage stash %x %x' % (addr, size))
-    output = u_boot_console.run_command('echo $?')
+    ubman.run_command('bootstage stash %x %x' % (addr, size))
+    output = ubman.run_command('echo $?')
     assert output.endswith('0')
 
-    output = u_boot_console.run_command('md %x 100' % addr)
+    output = ubman.run_command('md %x 100' % addr)
 
     # Check BOOTSTAGE_MAGIC address at 4th byte address
     assert '0x' + output.split('\n')[0].split()[4] == hex(bootstage_magic)
@@ -57,6 +57,6 @@ def test_bootstage_stash_and_unstash(u_boot_console):
     assert expected_text in output_last_col
 
     # Check that unstash works as expected
-    u_boot_console.run_command('bootstage unstash %x %x' % (addr, size))
-    output = u_boot_console.run_command('echo $?')
+    ubman.run_command('bootstage unstash %x %x' % (addr, size))
+    output = ubman.run_command('echo $?')
     assert output.endswith('0')
diff --git a/test/py/tests/test_button.py b/test/py/tests/test_button.py
index 3b7f148c8fc..f0d85be896d 100644
--- a/test/py/tests/test_button.py
+++ b/test/py/tests/test_button.py
@@ -4,10 +4,10 @@ import pytest
 
 @pytest.mark.boardspec('sandbox')
 @pytest.mark.buildconfigspec('cmd_button')
-def test_button_list(u_boot_console):
+def test_button_list(ubman):
     """Test listing buttons"""
 
-    response = u_boot_console.run_command('button list; echo rc:$?')
+    response = ubman.run_command('button list; echo rc:$?')
     assert('button1' in response)
     assert('button2' in response)
     assert('rc:0' in response)
@@ -15,23 +15,23 @@ def test_button_list(u_boot_console):
 @pytest.mark.boardspec('sandbox')
 @pytest.mark.buildconfigspec('cmd_button')
 @pytest.mark.buildconfigspec('cmd_gpio')
-def test_button_return_code(u_boot_console):
+def test_button_return_code(ubman):
     """Test correct reporting of the button status
 
     The sandbox gpio driver reports the last output value as input value.
     We can use this in our test to emulate different input statuses.
     """
 
-    u_boot_console.run_command('gpio set a3; gpio input a3');
-    response = u_boot_console.run_command('button button1; echo rc:$?')
+    ubman.run_command('gpio set a3; gpio input a3');
+    response = ubman.run_command('button button1; echo rc:$?')
     assert('on' in response)
     assert('rc:0' in response)
 
-    u_boot_console.run_command('gpio clear a3; gpio input a3');
-    response = u_boot_console.run_command('button button1; echo rc:$?')
+    ubman.run_command('gpio clear a3; gpio input a3');
+    response = ubman.run_command('button button1; echo rc:$?')
     assert('off' in response)
     assert('rc:1' in response)
 
-    response = u_boot_console.run_command('button nonexistent-button; echo rc:$?')
+    response = ubman.run_command('button nonexistent-button; echo rc:$?')
     assert('not found' in response)
     assert('rc:1' in response)
diff --git a/test/py/tests/test_cat/test_cat.py b/test/py/tests/test_cat/test_cat.py
index 132527bd4c2..883803fece7 100644
--- a/test/py/tests/test_cat/test_cat.py
+++ b/test/py/tests/test_cat/test_cat.py
@@ -7,14 +7,14 @@ import pytest
 
 @pytest.mark.boardspec('sandbox')
 @pytest.mark.buildconfigspec('cmd_cat')
-def test_cat(u_boot_console, cat_data):
+def test_cat(ubman, cat_data):
     """ Unit test for cat
 
     Args:
-        u_boot_console -- U-Boot console
+        ubman -- U-Boot console
         cat_data -- Path to the disk image used for testing.
     """
-    response = u_boot_console.run_command_list([
+    response = ubman.run_command_list([
         f'host bind 0 {cat_data}',
         'cat host 0 hello'])
     assert 'hello world' in response
diff --git a/test/py/tests/test_dfu.py b/test/py/tests/test_dfu.py
index 5d87eb349bf..7d6f41db7fb 100644
--- a/test/py/tests/test_dfu.py
+++ b/test/py/tests/test_dfu.py
@@ -9,7 +9,7 @@
 import os
 import os.path
 import pytest
-import u_boot_utils
+import utils
 
 """
 Note: This test relies on:
@@ -113,13 +113,13 @@ first_usb_dev_port = None
 
 @pytest.mark.buildconfigspec('cmd_dfu')
 @pytest.mark.requiredtool('dfu-util')
-def test_dfu(u_boot_console, env__usb_dev_port, env__dfu_config):
+def test_dfu(ubman, env__usb_dev_port, env__dfu_config):
     """Test the "dfu" command; the host system must be able to enumerate a USB
     device when "dfu" is running, various DFU transfers are tested, and the
     USB device must disappear when "dfu" is aborted.
 
     Args:
-        u_boot_console: A U-Boot console connection.
+        ubman: A U-Boot console connection.
         env__usb_dev_port: The single USB device-mode port specification on
             which to run the test. See the file-level comment above for
             details of the format.
@@ -143,15 +143,15 @@ def test_dfu(u_boot_console, env__usb_dev_port, env__dfu_config):
             Nothing.
         """
 
-        u_boot_utils.wait_until_file_open_fails(
+        utils.wait_until_file_open_fails(
             env__usb_dev_port['host_usb_dev_node'], True)
-        fh = u_boot_utils.attempt_to_open_file(
+        fh = utils.attempt_to_open_file(
             env__usb_dev_port['host_usb_dev_node'])
         if fh:
             fh.close()
             raise Exception('USB device present before dfu command invoked')
 
-        u_boot_console.log.action(
+        ubman.log.action(
             'Starting long-running U-Boot dfu shell command')
 
         dfu_alt_info_env = env__dfu_config.get('alt_info_env_name', \
@@ -159,12 +159,12 @@ def test_dfu(u_boot_console, env__usb_dev_port, env__dfu_config):
 
         cmd = 'setenv "%s" "%s"' % (dfu_alt_info_env,
                                     env__dfu_config['alt_info'])
-        u_boot_console.run_command(cmd)
+        ubman.run_command(cmd)
 
         cmd = 'dfu 0 ' + env__dfu_config['cmd_params']
-        u_boot_console.run_command(cmd, wait_for_prompt=False)
-        u_boot_console.log.action('Waiting for DFU USB device to appear')
-        fh = u_boot_utils.wait_until_open_succeeds(
+        ubman.run_command(cmd, wait_for_prompt=False)
+        ubman.log.action('Waiting for DFU USB device to appear')
+        fh = utils.wait_until_open_succeeds(
             env__usb_dev_port['host_usb_dev_node'])
         fh.close()
 
@@ -185,12 +185,12 @@ def test_dfu(u_boot_console, env__usb_dev_port, env__dfu_config):
         """
 
         try:
-            u_boot_console.log.action(
+            ubman.log.action(
                 'Stopping long-running U-Boot dfu shell command')
-            u_boot_console.ctrlc()
-            u_boot_console.log.action(
+            ubman.ctrlc()
+            ubman.log.action(
                 'Waiting for DFU USB device to disappear')
-            u_boot_utils.wait_until_file_open_fails(
+            utils.wait_until_file_open_fails(
                 env__usb_dev_port['host_usb_dev_node'], ignore_errors)
         except:
             if not ignore_errors:
@@ -213,8 +213,8 @@ def test_dfu(u_boot_console, env__usb_dev_port, env__dfu_config):
         cmd = ['dfu-util', '-a', alt_setting, up_dn_load_arg, fn]
         if 'host_usb_port_path' in env__usb_dev_port:
             cmd += ['-p', env__usb_dev_port['host_usb_port_path']]
-        u_boot_utils.run_and_log(u_boot_console, cmd)
-        u_boot_console.wait_for('Ctrl+C to exit ...')
+        utils.run_and_log(ubman, cmd)
+        ubman.wait_for('Ctrl+C to exit ...')
 
     def dfu_write(alt_setting, fn):
         """Write a file to the target board using DFU.
@@ -261,25 +261,25 @@ def test_dfu(u_boot_console, env__usb_dev_port, env__dfu_config):
             Nothing.
         """
 
-        test_f = u_boot_utils.PersistentRandomFile(u_boot_console,
+        test_f = utils.PersistentRandomFile(ubman,
             'dfu_%d.bin' % size, size)
-        readback_fn = u_boot_console.config.result_dir + '/dfu_readback.bin'
+        readback_fn = ubman.config.result_dir + '/dfu_readback.bin'
 
-        u_boot_console.log.action('Writing test data to DFU primary ' +
+        ubman.log.action('Writing test data to DFU primary ' +
             'altsetting')
         dfu_write(alt_setting_test_file, test_f.abs_fn)
 
-        u_boot_console.log.action('Writing dummy data to DFU secondary ' +
+        ubman.log.action('Writing dummy data to DFU secondary ' +
             'altsetting to clear DFU buffers')
         dfu_write(alt_setting_dummy_file, dummy_f.abs_fn)
 
-        u_boot_console.log.action('Reading DFU primary altsetting for ' +
+        ubman.log.action('Reading DFU primary altsetting for ' +
             'comparison')
         dfu_read(alt_setting_test_file, readback_fn)
 
-        u_boot_console.log.action('Comparing written and read data')
+        ubman.log.action('Comparing written and read data')
         written_hash = test_f.content_hash
-        read_back_hash = u_boot_utils.md5sum_file(readback_fn, size)
+        read_back_hash = utils.md5sum_file(readback_fn, size)
         assert(written_hash == read_back_hash)
 
     # This test may be executed against multiple USB ports. The test takes a
@@ -295,7 +295,7 @@ def test_dfu(u_boot_console, env__usb_dev_port, env__dfu_config):
     else:
         sizes = []
 
-    dummy_f = u_boot_utils.PersistentRandomFile(u_boot_console,
+    dummy_f = utils.PersistentRandomFile(ubman,
         'dfu_dummy.bin', 1024)
 
     alt_setting_test_file = env__dfu_config.get('alt_id_test_file', '0')
@@ -305,16 +305,16 @@ def test_dfu(u_boot_console, env__usb_dev_port, env__dfu_config):
     try:
         start_dfu()
 
-        u_boot_console.log.action(
+        ubman.log.action(
             'Overwriting DFU primary altsetting with dummy data')
         dfu_write(alt_setting_test_file, dummy_f.abs_fn)
 
         for size in sizes:
-            with u_boot_console.log.section('Data size %d' % size):
+            with ubman.log.section('Data size %d' % size):
                 dfu_write_read_check(size)
                 # Make the status of each sub-test obvious. If the test didn't
                 # pass, an exception was thrown so this code isn't executed.
-                u_boot_console.log.status_pass('OK')
+                ubman.log.status_pass('OK')
         ignore_cleanup_errors = False
     finally:
         stop_dfu(ignore_cleanup_errors)
diff --git a/test/py/tests/test_distro.py b/test/py/tests/test_distro.py
new file mode 100644
index 00000000000..bdf4ab657d1
--- /dev/null
+++ b/test/py/tests/test_distro.py
@@ -0,0 +1,61 @@
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright 2025 Canonical Ltd.
+# Written by Simon Glass <simon.glass@canonical.com>
+
+import pytest
+
+# Enable early console so that the test can see if something goes wrong
+CONSOLE = 'earlycon=uart8250,io,0x3f8 console=uart8250,io,0x3f8'
+
+@pytest.mark.boardspec('qemu-x86_64')
+@pytest.mark.role('qemu-x86_64')
+def test_distro(ubman):
+    """Test that of-platdata can be generated and used in sandbox"""
+    with ubman.log.section('boot'):
+        ubman.run_command('boot', wait_for_prompt=False)
+
+    with ubman.log.section('Grub'):
+        # Wait for grub to come up and offset a menu
+        ubman.p.expect(['Try or Install Ubuntu'])
+
+        # Press 'e' to edit the command line
+        ubman.log.info("Pressing 'e'")
+        ubman.run_command('e', wait_for_prompt=False, send_nl=False)
+
+        # Wait until we see the editor appear
+        ubman.p.expect(['/casper/initrd'])
+
+        # Go down to the 'linux' line. Avoid using down-arrow as that includes
+        # an Escape character, which may be parsed by Grub as such, causing it
+        # to return to the top menu
+        ubman.log.info("Going DOWN")
+        ubman.ctrl('N')
+        ubman.ctrl('N')
+        ubman.ctrl('N')
+
+        # Go to end of line
+        ubman.log.info("Going to EOL")
+        ubman.ctrl('E')
+
+        # Backspace to remove 'quiet splash'
+        ubman.log.info("Erasing quiet and splash")
+        ubman.send('\b' * len('quiet splash'))
+
+        # Send our noisy console
+        ubman.log.info("Noisy console")
+        ubman.send(CONSOLE)
+
+        # Tell grub to boot
+        ubman.log.info("boot")
+        ubman.ctrl('X')
+        ubman.p.expect(['Booting a command list'])
+
+    with ubman.log.section('Linux'):
+        # Linux should start immediately
+        ubman.p.expect(['Linux version'])
+
+    with ubman.log.section('Ubuntu'):
+        # Shortly later, we should see this banner
+        ubman.p.expect(['Welcome to .*Ubuntu 24.04.1 LTS.*!'])
+
+    ubman.restart_uboot()
diff --git a/test/py/tests/test_dm.py b/test/py/tests/test_dm.py
index be94971e455..f4c2ccd1101 100644
--- a/test/py/tests/test_dm.py
+++ b/test/py/tests/test_dm.py
@@ -4,15 +4,15 @@
 import pytest
 
 @pytest.mark.buildconfigspec('cmd_dm')
-def test_dm_compat(u_boot_console):
+def test_dm_compat(ubman):
     """Test that each driver in `dm tree` is also listed in `dm compat`."""
-    response = u_boot_console.run_command('dm tree')
+    response = ubman.run_command('dm tree')
     driver_index = response.find('Driver')
     assert driver_index != -1
     drivers = (line[driver_index:].split()[0]
                for line in response[:-1].split('\n')[2:])
 
-    response = u_boot_console.run_command('dm compat')
+    response = ubman.run_command('dm compat')
     bad_drivers = set()
     for driver in drivers:
         if not driver in response:
@@ -29,7 +29,7 @@ def test_dm_compat(u_boot_console):
     # checking sorting only after UCLASS_AXI_EMUL after which the names should
     # be sorted.
 
-    response = u_boot_console.run_command('dm tree -s')
+    response = ubman.run_command('dm tree -s')
     lines = response.split('\n')[2:]
     stack = []   # holds where we were up to at the previous indent level
     prev = ''    # uclass name of previous line
@@ -58,27 +58,27 @@ def test_dm_compat(u_boot_console):
 
 
 @pytest.mark.buildconfigspec('cmd_dm')
-def test_dm_drivers(u_boot_console):
+def test_dm_drivers(ubman):
     """Test that each driver in `dm compat` is also listed in `dm drivers`."""
-    response = u_boot_console.run_command('dm compat')
+    response = ubman.run_command('dm compat')
     drivers = (line[:20].rstrip() for line in response[:-1].split('\n')[2:])
-    response = u_boot_console.run_command('dm drivers')
+    response = ubman.run_command('dm drivers')
     for driver in drivers:
         assert driver in response
 
 @pytest.mark.buildconfigspec('cmd_dm')
-def test_dm_static(u_boot_console):
+def test_dm_static(ubman):
     """Test that each driver in `dm static` is also listed in `dm drivers`."""
-    response = u_boot_console.run_command('dm static')
+    response = ubman.run_command('dm static')
     drivers = (line[:25].rstrip() for line in response[:-1].split('\n')[2:])
-    response = u_boot_console.run_command('dm drivers')
+    response = ubman.run_command('dm drivers')
     for driver in drivers:
         assert driver in response
 
 @pytest.mark.buildconfigspec("cmd_dm")
-def test_dm_uclass(u_boot_console):
-    response = u_boot_console.run_command("dm uclass")
+def test_dm_uclass(ubman):
+    response = ubman.run_command("dm uclass")
 
 @pytest.mark.buildconfigspec("cmd_dm")
-def test_dm_devres(u_boot_console):
-    response = u_boot_console.run_command("dm devres")
+def test_dm_devres(ubman):
+    response = ubman.run_command("dm devres")
diff --git a/test/py/tests/test_efi_bootmgr/test_efi_bootmgr.py b/test/py/tests/test_efi_bootmgr/test_efi_bootmgr.py
index 1bb59d8fcf8..8800e9de5b4 100644
--- a/test/py/tests/test_efi_bootmgr/test_efi_bootmgr.py
+++ b/test/py/tests/test_efi_bootmgr/test_efi_bootmgr.py
@@ -8,37 +8,37 @@ import pytest
 @pytest.mark.buildconfigspec('cmd_efidebug')
 @pytest.mark.buildconfigspec('cmd_bootefi_bootmgr')
 @pytest.mark.singlethread
-def test_efi_bootmgr(u_boot_console, efi_bootmgr_data):
+def test_efi_bootmgr(ubman, efi_bootmgr_data):
     """ Unit test for UEFI bootmanager
     The efidebug command is used to set up UEFI load options.
     The bootefi bootmgr loads initrddump.efi as a payload.
     The crc32 of the loaded initrd.img is checked
 
     Args:
-        u_boot_console -- U-Boot console
+        ubman -- U-Boot console
         efi_bootmgr_data -- Path to the disk image used for testing.
     """
-    u_boot_console.run_command(cmd = f'host bind 0 {efi_bootmgr_data}')
+    ubman.run_command(cmd = f'host bind 0 {efi_bootmgr_data}')
 
-    u_boot_console.run_command(cmd = 'efidebug boot add ' \
+    ubman.run_command(cmd = 'efidebug boot add ' \
         '-b 0001 label-1 host 0:1 initrddump.efi ' \
         '-i host 0:1 initrd-1.img -s nocolor')
-    u_boot_console.run_command(cmd = 'efidebug boot dump')
-    u_boot_console.run_command(cmd = 'efidebug boot order 0001')
-    u_boot_console.run_command(cmd = 'bootefi bootmgr')
-    response = u_boot_console.run_command(cmd = 'load', wait_for_echo=False)
+    ubman.run_command(cmd = 'efidebug boot dump')
+    ubman.run_command(cmd = 'efidebug boot order 0001')
+    ubman.run_command(cmd = 'bootefi bootmgr')
+    response = ubman.run_command(cmd = 'load', wait_for_echo=False)
     assert 'crc32: 0x181464af' in response
-    u_boot_console.run_command(cmd = 'exit', wait_for_echo=False)
+    ubman.run_command(cmd = 'exit', wait_for_echo=False)
 
-    u_boot_console.run_command(cmd = 'efidebug boot add ' \
+    ubman.run_command(cmd = 'efidebug boot add ' \
         '-B 0002 label-2 host 0:1 initrddump.efi ' \
         '-I host 0:1 initrd-2.img -s nocolor')
-    u_boot_console.run_command(cmd = 'efidebug boot dump')
-    u_boot_console.run_command(cmd = 'efidebug boot order 0002')
-    u_boot_console.run_command(cmd = 'bootefi bootmgr')
-    response = u_boot_console.run_command(cmd = 'load', wait_for_echo=False)
+    ubman.run_command(cmd = 'efidebug boot dump')
+    ubman.run_command(cmd = 'efidebug boot order 0002')
+    ubman.run_command(cmd = 'bootefi bootmgr')
+    response = ubman.run_command(cmd = 'load', wait_for_echo=False)
     assert 'crc32: 0x811d3515' in response
-    u_boot_console.run_command(cmd = 'exit', wait_for_echo=False)
+    ubman.run_command(cmd = 'exit', wait_for_echo=False)
 
-    u_boot_console.run_command(cmd = 'efidebug boot rm 0001')
-    u_boot_console.run_command(cmd = 'efidebug boot rm 0002')
+    ubman.run_command(cmd = 'efidebug boot rm 0001')
+    ubman.run_command(cmd = 'efidebug boot rm 0002')
diff --git a/test/py/tests/test_efi_capsule/capsule_common.py b/test/py/tests/test_efi_capsule/capsule_common.py
index fc0d851c619..40b3fca809e 100644
--- a/test/py/tests/test_efi_capsule/capsule_common.py
+++ b/test/py/tests/test_efi_capsule/capsule_common.py
@@ -6,15 +6,15 @@
 
 from capsule_defs import CAPSULE_DATA_DIR, CAPSULE_INSTALL_DIR
 
-def capsule_setup(u_boot_console, disk_img, osindications):
+def capsule_setup(ubman, disk_img, osindications):
     """setup the test
 
     Args:
-        u_boot_console -- A console connection to U-Boot.
+        ubman -- A console connection to U-Boot.
         disk_img -- A path to disk image to be used for testing.
         osindications -- String of osindications value.
     """
-    u_boot_console.run_command_list([
+    ubman.run_command_list([
         f'host bind 0 {disk_img}',
         'printenv -e PlatformLangCodes', # workaround for terminal size determination
         'efidebug boot add -b 1 TEST host 0:1 /helloworld.efi',
@@ -23,22 +23,22 @@ def capsule_setup(u_boot_console, disk_img, osindications):
         'u-boot-env raw 0x150000 0x200000"'])
 
     if osindications is None:
-        u_boot_console.run_command('env set -e OsIndications')
+        ubman.run_command('env set -e OsIndications')
     else:
-        u_boot_console.run_command(f'env set -e -nv -bs -rt OsIndications ={osindications}')
+        ubman.run_command(f'env set -e -nv -bs -rt OsIndications ={osindications}')
 
-    u_boot_console.run_command('env save')
+    ubman.run_command('env save')
 
-def init_content(u_boot_console, target, filename, expected):
+def init_content(ubman, target, filename, expected):
     """initialize test content
 
     Args:
-        u_boot_console -- A console connection to U-Boot.
+        ubman -- A console connection to U-Boot.
         target -- Target address to place the content.
         filename -- File name of the content.
         expected -- Expected string of the content.
     """
-    output = u_boot_console.run_command_list([
+    output = ubman.run_command_list([
         'sf probe 0:0',
         f'fatload host 0:1 4000000 {CAPSULE_DATA_DIR}/{filename}',
         f'sf write 4000000 {target} 10',
@@ -46,34 +46,34 @@ def init_content(u_boot_console, target, filename, expected):
         'md.b 5000000 10'])
     assert expected in ''.join(output)
 
-def place_capsule_file(u_boot_console, filenames):
+def place_capsule_file(ubman, filenames):
     """place the capsule file
 
     Args:
-        u_boot_console -- A console connection to U-Boot.
+        ubman -- A console connection to U-Boot.
         filenames -- File name array of the target capsule files.
     """
     for name in filenames:
-        u_boot_console.run_command_list([
+        ubman.run_command_list([
             f'fatload host 0:1 4000000 {CAPSULE_DATA_DIR}/{name}',
             f'fatwrite host 0:1 4000000 {CAPSULE_INSTALL_DIR}/{name} $filesize'])
 
-    output = u_boot_console.run_command(f'fatls host 0:1 {CAPSULE_INSTALL_DIR}')
+    output = ubman.run_command(f'fatls host 0:1 {CAPSULE_INSTALL_DIR}')
     for name in filenames:
         assert name in ''.join(output)
 
-def exec_manual_update(u_boot_console, disk_img, filenames, need_reboot = True):
+def exec_manual_update(ubman, disk_img, filenames, need_reboot = True):
     """execute capsule update manually
 
     Args:
-        u_boot_console -- A console connection to U-Boot.
+        ubman -- A console connection to U-Boot.
         disk_img -- A path to disk image to be used for testing.
         filenames -- File name array of the target capsule files.
         need_reboot -- Flag indicates whether system reboot is required.
     """
     # make sure that dfu_alt_info exists even persistent variables
     # are not available.
-    output = u_boot_console.run_command_list([
+    output = ubman.run_command_list([
         'env set dfu_alt_info '
                 '"sf 0:0=u-boot-bin raw 0x100000 0x50000;'
                 'u-boot-env raw 0x150000 0x200000"',
@@ -83,60 +83,60 @@ def exec_manual_update(u_boot_console, disk_img, filenames, need_reboot = True):
         assert name in ''.join(output)
 
     # need to run uefi command to initiate capsule handling
-    u_boot_console.run_command(
+    ubman.run_command(
         'env print -e Capsule0000', wait_for_reboot = need_reboot)
 
-def check_file_removed(u_boot_console, disk_img, filenames):
+def check_file_removed(ubman, disk_img, filenames):
     """check files are removed
 
     Args:
-        u_boot_console -- A console connection to U-Boot.
+        ubman -- A console connection to U-Boot.
         disk_img -- A path to disk image to be used for testing.
         filenames -- File name array of the target capsule files.
     """
-    output = u_boot_console.run_command_list([
+    output = ubman.run_command_list([
         f'host bind 0 {disk_img}',
         f'fatls host 0:1 {CAPSULE_INSTALL_DIR}'])
     for name in filenames:
         assert name not in ''.join(output)
 
-def check_file_exist(u_boot_console, disk_img, filenames):
+def check_file_exist(ubman, disk_img, filenames):
     """check files exist
 
     Args:
-        u_boot_console -- A console connection to U-Boot.
+        ubman -- A console connection to U-Boot.
         disk_img -- A path to disk image to be used for testing.
         filenames -- File name array of the target capsule files.
     """
-    output = u_boot_console.run_command_list([
+    output = ubman.run_command_list([
         f'host bind 0 {disk_img}',
         f'fatls host 0:1 {CAPSULE_INSTALL_DIR}'])
     for name in filenames:
         assert name in ''.join(output)
 
-def verify_content(u_boot_console, target, expected):
+def verify_content(ubman, target, expected):
     """verify the content
 
     Args:
-        u_boot_console -- A console connection to U-Boot.
+        ubman -- A console connection to U-Boot.
         target -- Target address to verify.
         expected -- Expected string of the content.
     """
-    output = u_boot_console.run_command_list([
+    output = ubman.run_command_list([
         'sf probe 0:0',
         f'sf read 4000000 {target} 10',
         'md.b 4000000 10'])
     assert expected in ''.join(output)
 
-def do_reboot_dtb_specified(u_boot_config, u_boot_console, dtb_filename):
+def do_reboot_dtb_specified(u_boot_config, ubman, dtb_filename):
     """do reboot with specified DTB
 
     Args:
         u_boot_config -- U-boot configuration.
-        u_boot_console -- A console connection to U-Boot.
+        ubman -- A console connection to U-Boot.
         dtb_filename -- DTB file name.
     """
     mnt_point = u_boot_config.persistent_data_dir + '/test_efi_capsule'
-    u_boot_console.config.dtb = mnt_point + CAPSULE_DATA_DIR \
+    ubman.config.dtb = mnt_point + CAPSULE_DATA_DIR \
                                 + f'/{dtb_filename}'
-    u_boot_console.restart_uboot()
+    ubman.restart_uboot()
diff --git a/test/py/tests/test_efi_capsule/test_capsule_firmware_fit.py b/test/py/tests/test_efi_capsule/test_capsule_firmware_fit.py
index a726c71c113..016274533cd 100644
--- a/test/py/tests/test_efi_capsule/test_capsule_firmware_fit.py
+++ b/test/py/tests/test_efi_capsule/test_capsule_firmware_fit.py
@@ -33,7 +33,7 @@ class TestEfiCapsuleFirmwareFit():
     """
 
     def test_efi_capsule_fw1(
-            self, u_boot_config, u_boot_console, efi_capsule_data):
+            self, u_boot_config, ubman, efi_capsule_data):
         """Test Case 1
         Update U-Boot and U-Boot environment on SPI Flash
         but with an incorrect GUID value in the capsule
@@ -44,34 +44,34 @@ class TestEfiCapsuleFirmwareFit():
         # other tests might have run and the
         # system might not be in a clean state.
         # Restart before starting the tests.
-        u_boot_console.restart_uboot()
+        ubman.restart_uboot()
 
         disk_img = efi_capsule_data
         capsule_files = ['Test05']
-        with u_boot_console.log.section('Test Case 1-a, before reboot'):
-            capsule_setup(u_boot_console, disk_img, '0x0000000000000004')
-            init_content(u_boot_console, '100000', 'u-boot.bin.old', 'Old')
-            init_content(u_boot_console, '150000', 'u-boot.env.old', 'Old')
-            place_capsule_file(u_boot_console, capsule_files)
+        with ubman.log.section('Test Case 1-a, before reboot'):
+            capsule_setup(ubman, disk_img, '0x0000000000000004')
+            init_content(ubman, '100000', 'u-boot.bin.old', 'Old')
+            init_content(ubman, '150000', 'u-boot.env.old', 'Old')
+            place_capsule_file(ubman, capsule_files)
 
         capsule_early = u_boot_config.buildconfig.get(
             'config_efi_capsule_on_disk_early')
 
         # reboot
-        u_boot_console.restart_uboot(expect_reset = capsule_early)
+        ubman.restart_uboot(expect_reset = capsule_early)
 
-        with u_boot_console.log.section('Test Case 1-b, after reboot'):
+        with ubman.log.section('Test Case 1-b, after reboot'):
             if not capsule_early:
-                exec_manual_update(u_boot_console, disk_img, capsule_files)
+                exec_manual_update(ubman, disk_img, capsule_files)
 
             # deleted anyway
-            check_file_removed(u_boot_console, disk_img, capsule_files)
+            check_file_removed(ubman, disk_img, capsule_files)
 
-            verify_content(u_boot_console, '100000', 'u-boot:Old')
-            verify_content(u_boot_console, '150000', 'u-boot-env:Old')
+            verify_content(ubman, '100000', 'u-boot:Old')
+            verify_content(ubman, '150000', 'u-boot-env:Old')
 
     def test_efi_capsule_fw2(
-            self, u_boot_config, u_boot_console, efi_capsule_data):
+            self, u_boot_config, ubman, efi_capsule_data):
         """Test Case 2
         Update U-Boot and U-Boot environment on SPI Flash
         0x100000-0x150000: U-Boot binary (but dummy)
@@ -80,11 +80,11 @@ class TestEfiCapsuleFirmwareFit():
 
         disk_img = efi_capsule_data
         capsule_files = ['Test04']
-        with u_boot_console.log.section('Test Case 2-a, before reboot'):
-            capsule_setup(u_boot_console, disk_img, '0x0000000000000004')
-            init_content(u_boot_console, '100000', 'u-boot.bin.old', 'Old')
-            init_content(u_boot_console, '150000', 'u-boot.env.old', 'Old')
-            place_capsule_file(u_boot_console, capsule_files)
+        with ubman.log.section('Test Case 2-a, before reboot'):
+            capsule_setup(ubman, disk_img, '0x0000000000000004')
+            init_content(ubman, '100000', 'u-boot.bin.old', 'Old')
+            init_content(ubman, '150000', 'u-boot.env.old', 'Old')
+            place_capsule_file(ubman, capsule_files)
 
         capsule_early = u_boot_config.buildconfig.get(
             'config_efi_capsule_on_disk_early')
@@ -92,22 +92,22 @@ class TestEfiCapsuleFirmwareFit():
             'config_efi_capsule_authenticate')
 
         # reboot
-        u_boot_console.restart_uboot(expect_reset = capsule_early)
+        ubman.restart_uboot(expect_reset = capsule_early)
 
-        with u_boot_console.log.section('Test Case 2-b, after reboot'):
+        with ubman.log.section('Test Case 2-b, after reboot'):
             if not capsule_early:
-                exec_manual_update(u_boot_console, disk_img, capsule_files)
+                exec_manual_update(ubman, disk_img, capsule_files)
 
-            check_file_removed(u_boot_console, disk_img, capsule_files)
+            check_file_removed(ubman, disk_img, capsule_files)
 
             expected = 'u-boot:Old' if capsule_auth else 'u-boot:New'
-            verify_content(u_boot_console, '100000', expected)
+            verify_content(ubman, '100000', expected)
 
             expected = 'u-boot-env:Old' if capsule_auth else 'u-boot-env:New'
-            verify_content(u_boot_console, '150000', expected)
+            verify_content(ubman, '150000', expected)
 
     def test_efi_capsule_fw3(
-            self, u_boot_config, u_boot_console, efi_capsule_data):
+            self, u_boot_config, ubman, efi_capsule_data):
         """ Test Case 3
         Update U-Boot on SPI Flash, raw image format with fw_version and lowest_supported_version
         0x100000-0x150000: U-Boot binary (but dummy)
@@ -115,47 +115,47 @@ class TestEfiCapsuleFirmwareFit():
         """
         disk_img = efi_capsule_data
         capsule_files = ['Test104']
-        with u_boot_console.log.section('Test Case 3-a, before reboot'):
-            capsule_setup(u_boot_console, disk_img, '0x0000000000000004')
-            init_content(u_boot_console, '100000', 'u-boot.bin.old', 'Old')
-            init_content(u_boot_console, '150000', 'u-boot.env.old', 'Old')
-            place_capsule_file(u_boot_console, capsule_files)
+        with ubman.log.section('Test Case 3-a, before reboot'):
+            capsule_setup(ubman, disk_img, '0x0000000000000004')
+            init_content(ubman, '100000', 'u-boot.bin.old', 'Old')
+            init_content(ubman, '150000', 'u-boot.env.old', 'Old')
+            place_capsule_file(ubman, capsule_files)
 
         # reboot
-        do_reboot_dtb_specified(u_boot_config, u_boot_console, 'test_ver.dtb')
+        do_reboot_dtb_specified(u_boot_config, ubman, 'test_ver.dtb')
 
         capsule_early = u_boot_config.buildconfig.get(
             'config_efi_capsule_on_disk_early')
         capsule_auth = u_boot_config.buildconfig.get(
             'config_efi_capsule_authenticate')
-        with u_boot_console.log.section('Test Case 3-b, after reboot'):
+        with ubman.log.section('Test Case 3-b, after reboot'):
             if not capsule_early:
-                exec_manual_update(u_boot_console, disk_img, capsule_files)
+                exec_manual_update(ubman, disk_img, capsule_files)
 
             # deleted anyway
-            check_file_removed(u_boot_console, disk_img, capsule_files)
+            check_file_removed(ubman, disk_img, capsule_files)
 
             # make sure the dfu_alt_info exists because it is required for making ESRT.
-            output = u_boot_console.run_command_list([
+            output = ubman.run_command_list([
                 'env set dfu_alt_info "sf 0:0=u-boot-bin raw 0x100000 0x50000;'
                 'u-boot-env raw 0x150000 0x200000"',
                 'efidebug capsule esrt'])
 
             if capsule_auth:
                 # capsule authentication failed
-                verify_content(u_boot_console, '100000', 'u-boot:Old')
-                verify_content(u_boot_console, '150000', 'u-boot-env:Old')
+                verify_content(ubman, '100000', 'u-boot:Old')
+                verify_content(ubman, '150000', 'u-boot-env:Old')
             else:
                 # ensure that SANDBOX_UBOOT_IMAGE_GUID is in the ESRT.
                 assert '985F2937-7C2E-5E9A-8A5E-8E063312964B' in ''.join(output)
                 assert 'ESRT: fw_version=5' in ''.join(output)
                 assert 'ESRT: lowest_supported_fw_version=3' in ''.join(output)
 
-                verify_content(u_boot_console, '100000', 'u-boot:New')
-                verify_content(u_boot_console, '150000', 'u-boot-env:New')
+                verify_content(ubman, '100000', 'u-boot:New')
+                verify_content(ubman, '150000', 'u-boot-env:New')
 
     def test_efi_capsule_fw4(
-            self, u_boot_config, u_boot_console, efi_capsule_data):
+            self, u_boot_config, ubman, efi_capsule_data):
         """ Test Case 4
         Update U-Boot on SPI Flash, raw image format with fw_version and lowest_supported_version
         but fw_version is lower than lowest_supported_version
@@ -164,20 +164,20 @@ class TestEfiCapsuleFirmwareFit():
         """
         disk_img = efi_capsule_data
         capsule_files = ['Test105']
-        with u_boot_console.log.section('Test Case 4-a, before reboot'):
-            capsule_setup(u_boot_console, disk_img, '0x0000000000000004')
-            init_content(u_boot_console, '100000', 'u-boot.bin.old', 'Old')
-            place_capsule_file(u_boot_console, capsule_files)
+        with ubman.log.section('Test Case 4-a, before reboot'):
+            capsule_setup(ubman, disk_img, '0x0000000000000004')
+            init_content(ubman, '100000', 'u-boot.bin.old', 'Old')
+            place_capsule_file(ubman, capsule_files)
 
         # reboot
-        do_reboot_dtb_specified(u_boot_config, u_boot_console, 'test_ver.dtb')
+        do_reboot_dtb_specified(u_boot_config, ubman, 'test_ver.dtb')
 
         capsule_early = u_boot_config.buildconfig.get(
             'config_efi_capsule_on_disk_early')
-        with u_boot_console.log.section('Test Case 4-b, after reboot'):
+        with ubman.log.section('Test Case 4-b, after reboot'):
             if not capsule_early:
-                exec_manual_update(u_boot_console, disk_img, capsule_files)
+                exec_manual_update(ubman, disk_img, capsule_files)
 
-            check_file_removed(u_boot_console, disk_img, capsule_files)
+            check_file_removed(ubman, disk_img, capsule_files)
 
-            verify_content(u_boot_console, '100000', 'u-boot:Old')
+            verify_content(ubman, '100000', 'u-boot:Old')
diff --git a/test/py/tests/test_efi_capsule/test_capsule_firmware_raw.py b/test/py/tests/test_efi_capsule/test_capsule_firmware_raw.py
index 8a790405c7c..b8cb483b380 100644
--- a/test/py/tests/test_efi_capsule/test_capsule_firmware_raw.py
+++ b/test/py/tests/test_efi_capsule/test_capsule_firmware_raw.py
@@ -34,7 +34,7 @@ class TestEfiCapsuleFirmwareRaw:
     """
 
     def test_efi_capsule_fw1(
-            self, u_boot_config, u_boot_console, efi_capsule_data):
+            self, u_boot_config, ubman, efi_capsule_data):
         """ Test Case 1
         Update U-Boot and U-Boot environment on SPI Flash
         but with an incorrect GUID value in the capsule
@@ -46,34 +46,34 @@ class TestEfiCapsuleFirmwareRaw:
         # other tests might have run and the
         # system might not be in a clean state.
         # Restart before starting the tests.
-        u_boot_console.restart_uboot()
+        ubman.restart_uboot()
 
         disk_img = efi_capsule_data
         capsule_files = ['Test03']
-        with u_boot_console.log.section('Test Case 1-a, before reboot'):
-            capsule_setup(u_boot_console, disk_img, '0x0000000000000004')
-            init_content(u_boot_console, '100000', 'u-boot.bin.old', 'Old')
-            init_content(u_boot_console, '150000', 'u-boot.env.old', 'Old')
-            place_capsule_file(u_boot_console, capsule_files)
+        with ubman.log.section('Test Case 1-a, before reboot'):
+            capsule_setup(ubman, disk_img, '0x0000000000000004')
+            init_content(ubman, '100000', 'u-boot.bin.old', 'Old')
+            init_content(ubman, '150000', 'u-boot.env.old', 'Old')
+            place_capsule_file(ubman, capsule_files)
 
         # reboot
-        u_boot_console.restart_uboot()
+        ubman.restart_uboot()
 
         capsule_early = u_boot_config.buildconfig.get(
             'config_efi_capsule_on_disk_early')
 
-        with u_boot_console.log.section('Test Case 1-b, after reboot'):
+        with ubman.log.section('Test Case 1-b, after reboot'):
             if not capsule_early:
-                exec_manual_update(u_boot_console, disk_img, capsule_files)
+                exec_manual_update(ubman, disk_img, capsule_files)
 
             # deleted anyway
-            check_file_removed(u_boot_console, disk_img, capsule_files)
+            check_file_removed(ubman, disk_img, capsule_files)
 
-            verify_content(u_boot_console, '100000', 'u-boot:Old')
-            verify_content(u_boot_console, '150000', 'u-boot-env:Old')
+            verify_content(ubman, '100000', 'u-boot:Old')
+            verify_content(ubman, '150000', 'u-boot-env:Old')
 
     def test_efi_capsule_fw2(
-            self, u_boot_config, u_boot_console, efi_capsule_data):
+            self, u_boot_config, ubman, efi_capsule_data):
         """ Test Case 2
         Update U-Boot and U-Boot environment on SPI Flash but with OsIndications unset
         No update should happen unless CONFIG_EFI_IGNORE_OSINDICATIONS is set
@@ -82,14 +82,14 @@ class TestEfiCapsuleFirmwareRaw:
         """
         disk_img = efi_capsule_data
         capsule_files = ['Test01', 'Test02']
-        with u_boot_console.log.section('Test Case 2-a, before reboot'):
-            capsule_setup(u_boot_console, disk_img, None)
-            init_content(u_boot_console, '100000', 'u-boot.bin.old', 'Old')
-            init_content(u_boot_console, '150000', 'u-boot.env.old', 'Old')
-            place_capsule_file(u_boot_console, capsule_files)
+        with ubman.log.section('Test Case 2-a, before reboot'):
+            capsule_setup(ubman, disk_img, None)
+            init_content(ubman, '100000', 'u-boot.bin.old', 'Old')
+            init_content(ubman, '150000', 'u-boot.env.old', 'Old')
+            place_capsule_file(ubman, capsule_files)
 
         # reboot
-        u_boot_console.restart_uboot()
+        ubman.restart_uboot()
 
         ignore_os_indications = u_boot_config.buildconfig.get(
             'config_efi_ignore_osindications')
@@ -100,32 +100,32 @@ class TestEfiCapsuleFirmwareRaw:
 
         capsule_early = u_boot_config.buildconfig.get(
             'config_efi_capsule_on_disk_early')
-        with u_boot_console.log.section('Test Case 2-b, after reboot'):
+        with ubman.log.section('Test Case 2-b, after reboot'):
             if not capsule_early:
-                exec_manual_update(u_boot_console, disk_img, capsule_files, need_reboot)
+                exec_manual_update(ubman, disk_img, capsule_files, need_reboot)
 
             if not ignore_os_indications:
-                check_file_exist(u_boot_console, disk_img, capsule_files)
+                check_file_exist(ubman, disk_img, capsule_files)
 
             expected = 'u-boot:New' if (ignore_os_indications and not capsule_auth) else 'u-boot:Old'
-            verify_content(u_boot_console, '100000', expected)
+            verify_content(ubman, '100000', expected)
 
             expected = 'u-boot-env:New' if (ignore_os_indications and not capsule_auth) else 'u-boot-env:Old'
-            verify_content(u_boot_console, '150000', expected)
+            verify_content(ubman, '150000', expected)
 
     def test_efi_capsule_fw3(
-            self, u_boot_config, u_boot_console, efi_capsule_data):
+            self, u_boot_config, ubman, efi_capsule_data):
         """ Test Case 3
         Update U-Boot on SPI Flash, raw image format
         0x100000-0x150000: U-Boot binary (but dummy)
         """
         disk_img = efi_capsule_data
         capsule_files = ['Test01', 'Test02']
-        with u_boot_console.log.section('Test Case 3-a, before reboot'):
-            capsule_setup(u_boot_console, disk_img, '0x0000000000000004')
-            init_content(u_boot_console, '100000', 'u-boot.bin.old', 'Old')
-            init_content(u_boot_console, '150000', 'u-boot.env.old', 'Old')
-            place_capsule_file(u_boot_console, capsule_files)
+        with ubman.log.section('Test Case 3-a, before reboot'):
+            capsule_setup(ubman, disk_img, '0x0000000000000004')
+            init_content(ubman, '100000', 'u-boot.bin.old', 'Old')
+            init_content(ubman, '150000', 'u-boot.env.old', 'Old')
+            place_capsule_file(ubman, capsule_files)
 
         capsule_early = u_boot_config.buildconfig.get(
             'config_efi_capsule_on_disk_early')
@@ -133,14 +133,14 @@ class TestEfiCapsuleFirmwareRaw:
             'config_efi_capsule_authenticate')
 
         # reboot
-        u_boot_console.restart_uboot(expect_reset = capsule_early)
+        ubman.restart_uboot(expect_reset = capsule_early)
 
-        with u_boot_console.log.section('Test Case 3-b, after reboot'):
+        with ubman.log.section('Test Case 3-b, after reboot'):
             if not capsule_early:
-                exec_manual_update(u_boot_console, disk_img, capsule_files)
+                exec_manual_update(ubman, disk_img, capsule_files)
 
             # make sure the dfu_alt_info exists because it is required for making ESRT.
-            output = u_boot_console.run_command_list([
+            output = ubman.run_command_list([
                 'env set dfu_alt_info "sf 0:0=u-boot-bin raw 0x100000 0x50000;u-boot-env raw 0x150000 0x200000"',
                 'efidebug capsule esrt'])
 
@@ -150,16 +150,16 @@ class TestEfiCapsuleFirmwareRaw:
             # ensure that SANDBOX_UBOOT_IMAGE_GUID is in the ESRT.
             assert '985F2937-7C2E-5E9A-8A5E-8E063312964B' in ''.join(output)
 
-            check_file_removed(u_boot_console, disk_img, capsule_files)
+            check_file_removed(ubman, disk_img, capsule_files)
 
             expected = 'u-boot:Old' if capsule_auth else 'u-boot:New'
-            verify_content(u_boot_console, '100000', expected)
+            verify_content(ubman, '100000', expected)
 
             expected = 'u-boot-env:Old' if capsule_auth else 'u-boot-env:New'
-            verify_content(u_boot_console, '150000', expected)
+            verify_content(ubman, '150000', expected)
 
     def test_efi_capsule_fw4(
-            self, u_boot_config, u_boot_console, efi_capsule_data):
+            self, u_boot_config, ubman, efi_capsule_data):
         """ Test Case 4
         Update U-Boot on SPI Flash, raw image format with fw_version and lowest_supported_version
         0x100000-0x150000: U-Boot binary (but dummy)
@@ -167,36 +167,36 @@ class TestEfiCapsuleFirmwareRaw:
         """
         disk_img = efi_capsule_data
         capsule_files = ['Test101', 'Test102']
-        with u_boot_console.log.section('Test Case 4-a, before reboot'):
-            capsule_setup(u_boot_console, disk_img, '0x0000000000000004')
-            init_content(u_boot_console, '100000', 'u-boot.bin.old', 'Old')
-            init_content(u_boot_console, '150000', 'u-boot.env.old', 'Old')
-            place_capsule_file(u_boot_console, capsule_files)
+        with ubman.log.section('Test Case 4-a, before reboot'):
+            capsule_setup(ubman, disk_img, '0x0000000000000004')
+            init_content(ubman, '100000', 'u-boot.bin.old', 'Old')
+            init_content(ubman, '150000', 'u-boot.env.old', 'Old')
+            place_capsule_file(ubman, capsule_files)
 
         # reboot
-        do_reboot_dtb_specified(u_boot_config, u_boot_console, 'test_ver.dtb')
+        do_reboot_dtb_specified(u_boot_config, ubman, 'test_ver.dtb')
 
         capsule_early = u_boot_config.buildconfig.get(
             'config_efi_capsule_on_disk_early')
         capsule_auth = u_boot_config.buildconfig.get(
             'config_efi_capsule_authenticate')
-        with u_boot_console.log.section('Test Case 4-b, after reboot'):
+        with ubman.log.section('Test Case 4-b, after reboot'):
             if not capsule_early:
-                exec_manual_update(u_boot_console, disk_img, capsule_files)
+                exec_manual_update(ubman, disk_img, capsule_files)
 
             # deleted anyway
-            check_file_removed(u_boot_console, disk_img, capsule_files)
+            check_file_removed(ubman, disk_img, capsule_files)
 
             # make sure the dfu_alt_info exists because it is required for making ESRT.
-            output = u_boot_console.run_command_list([
+            output = ubman.run_command_list([
                 'env set dfu_alt_info "sf 0:0=u-boot-bin raw 0x100000 0x50000'
                 'u-boot-env raw 0x150000 0x200000"',
                 'efidebug capsule esrt'])
 
             if capsule_auth:
                 # capsule authentication failed
-                verify_content(u_boot_console, '100000', 'u-boot:Old')
-                verify_content(u_boot_console, '150000', 'u-boot-env:Old')
+                verify_content(ubman, '100000', 'u-boot:Old')
+                verify_content(ubman, '150000', 'u-boot-env:Old')
             else:
                 # ensure that SANDBOX_UBOOT_IMAGE_GUID is in the ESRT.
                 assert '985F2937-7C2E-5E9A-8A5E-8E063312964B' in ''.join(output)
@@ -208,11 +208,11 @@ class TestEfiCapsuleFirmwareRaw:
                 assert 'ESRT: fw_version=10' in ''.join(output)
                 assert 'ESRT: lowest_supported_fw_version=7' in ''.join(output)
 
-                verify_content(u_boot_console, '100000', 'u-boot:New')
-                verify_content(u_boot_console, '150000', 'u-boot-env:New')
+                verify_content(ubman, '100000', 'u-boot:New')
+                verify_content(ubman, '150000', 'u-boot-env:New')
 
     def test_efi_capsule_fw5(
-            self, u_boot_config, u_boot_console, efi_capsule_data):
+            self, u_boot_config, ubman, efi_capsule_data):
         """ Test Case 5
         Update U-Boot on SPI Flash, raw image format with fw_version and lowest_supported_version
         but fw_version is lower than lowest_supported_version
@@ -221,20 +221,20 @@ class TestEfiCapsuleFirmwareRaw:
         """
         disk_img = efi_capsule_data
         capsule_files = ['Test103']
-        with u_boot_console.log.section('Test Case 5-a, before reboot'):
-            capsule_setup(u_boot_console, disk_img, '0x0000000000000004')
-            init_content(u_boot_console, '100000', 'u-boot.bin.old', 'Old')
-            place_capsule_file(u_boot_console, capsule_files)
+        with ubman.log.section('Test Case 5-a, before reboot'):
+            capsule_setup(ubman, disk_img, '0x0000000000000004')
+            init_content(ubman, '100000', 'u-boot.bin.old', 'Old')
+            place_capsule_file(ubman, capsule_files)
 
         # reboot
-        do_reboot_dtb_specified(u_boot_config, u_boot_console, 'test_ver.dtb')
+        do_reboot_dtb_specified(u_boot_config, ubman, 'test_ver.dtb')
 
         capsule_early = u_boot_config.buildconfig.get(
             'config_efi_capsule_on_disk_early')
-        with u_boot_console.log.section('Test Case 5-b, after reboot'):
+        with ubman.log.section('Test Case 5-b, after reboot'):
             if not capsule_early:
-                exec_manual_update(u_boot_console, disk_img, capsule_files)
+                exec_manual_update(ubman, disk_img, capsule_files)
 
-            check_file_removed(u_boot_console, disk_img, capsule_files)
+            check_file_removed(ubman, disk_img, capsule_files)
 
-            verify_content(u_boot_console, '100000', 'u-boot:Old')
+            verify_content(ubman, '100000', 'u-boot:Old')
diff --git a/test/py/tests/test_efi_capsule/test_capsule_firmware_signed_fit.py b/test/py/tests/test_efi_capsule/test_capsule_firmware_signed_fit.py
index debbce8bdbd..29545c5080a 100644
--- a/test/py/tests/test_efi_capsule/test_capsule_firmware_signed_fit.py
+++ b/test/py/tests/test_efi_capsule/test_capsule_firmware_signed_fit.py
@@ -36,7 +36,7 @@ class TestEfiCapsuleFirmwareSignedFit():
     """
 
     def test_efi_capsule_auth1(
-            self, u_boot_config, u_boot_console, efi_capsule_data):
+            self, u_boot_config, ubman, efi_capsule_data):
         """Test Case 1
         Update U-Boot on SPI Flash, FIT image format
         x150000: U-Boot binary (but dummy)
@@ -46,25 +46,25 @@ class TestEfiCapsuleFirmwareSignedFit():
         """
         disk_img = efi_capsule_data
         capsule_files = ['Test13']
-        with u_boot_console.log.section('Test Case 1-a, before reboot'):
-            capsule_setup(u_boot_console, disk_img, '0x0000000000000004')
-            init_content(u_boot_console, '100000', 'u-boot.bin.old', 'Old')
-            place_capsule_file(u_boot_console, capsule_files)
+        with ubman.log.section('Test Case 1-a, before reboot'):
+            capsule_setup(ubman, disk_img, '0x0000000000000004')
+            init_content(ubman, '100000', 'u-boot.bin.old', 'Old')
+            place_capsule_file(ubman, capsule_files)
 
-        do_reboot_dtb_specified(u_boot_config, u_boot_console, 'test_sig.dtb')
+        do_reboot_dtb_specified(u_boot_config, ubman, 'test_sig.dtb')
 
         capsule_early = u_boot_config.buildconfig.get(
             'config_efi_capsule_on_disk_early')
-        with u_boot_console.log.section('Test Case 1-b, after reboot'):
+        with ubman.log.section('Test Case 1-b, after reboot'):
             if not capsule_early:
-                exec_manual_update(u_boot_console, disk_img, capsule_files)
+                exec_manual_update(ubman, disk_img, capsule_files)
 
-            check_file_removed(u_boot_console, disk_img, capsule_files)
+            check_file_removed(ubman, disk_img, capsule_files)
 
-            verify_content(u_boot_console, '100000', 'u-boot:New')
+            verify_content(ubman, '100000', 'u-boot:New')
 
     def test_efi_capsule_auth2(
-            self, u_boot_config, u_boot_console, efi_capsule_data):
+            self, u_boot_config, ubman, efi_capsule_data):
         """Test Case 2
         Update U-Boot on SPI Flash, FIT image format
         0x100000-0x150000: U-Boot binary (but dummy)
@@ -75,28 +75,28 @@ class TestEfiCapsuleFirmwareSignedFit():
         """
         disk_img = efi_capsule_data
         capsule_files = ['Test14']
-        with u_boot_console.log.section('Test Case 2-a, before reboot'):
-            capsule_setup(u_boot_console, disk_img, '0x0000000000000004')
-            init_content(u_boot_console, '100000', 'u-boot.bin.old', 'Old')
-            place_capsule_file(u_boot_console, capsule_files)
+        with ubman.log.section('Test Case 2-a, before reboot'):
+            capsule_setup(ubman, disk_img, '0x0000000000000004')
+            init_content(ubman, '100000', 'u-boot.bin.old', 'Old')
+            place_capsule_file(ubman, capsule_files)
 
-        do_reboot_dtb_specified(u_boot_config, u_boot_console, 'test_sig.dtb')
+        do_reboot_dtb_specified(u_boot_config, ubman, 'test_sig.dtb')
 
         capsule_early = u_boot_config.buildconfig.get(
             'config_efi_capsule_on_disk_early')
-        with u_boot_console.log.section('Test Case 2-b, after reboot'):
+        with ubman.log.section('Test Case 2-b, after reboot'):
             if not capsule_early:
-                exec_manual_update(u_boot_console, disk_img, capsule_files)
+                exec_manual_update(ubman, disk_img, capsule_files)
 
             # deleted any way
-            check_file_removed(u_boot_console, disk_img, capsule_files)
+            check_file_removed(ubman, disk_img, capsule_files)
 
             # TODO: check CapsuleStatus in CapsuleXXXX
 
-            verify_content(u_boot_console, '100000', 'u-boot:Old')
+            verify_content(ubman, '100000', 'u-boot:Old')
 
     def test_efi_capsule_auth3(
-            self, u_boot_config, u_boot_console, efi_capsule_data):
+            self, u_boot_config, ubman, efi_capsule_data):
         """Test Case 3
         Update U-Boot on SPI Flash, FIT image format
         0x100000-0x150000: U-Boot binary (but dummy)
@@ -106,28 +106,28 @@ class TestEfiCapsuleFirmwareSignedFit():
         """
         disk_img = efi_capsule_data
         capsule_files = ['Test02']
-        with u_boot_console.log.section('Test Case 3-a, before reboot'):
-            capsule_setup(u_boot_console, disk_img, '0x0000000000000004')
-            init_content(u_boot_console, '100000', 'u-boot.bin.old', 'Old')
-            place_capsule_file(u_boot_console, capsule_files)
+        with ubman.log.section('Test Case 3-a, before reboot'):
+            capsule_setup(ubman, disk_img, '0x0000000000000004')
+            init_content(ubman, '100000', 'u-boot.bin.old', 'Old')
+            place_capsule_file(ubman, capsule_files)
 
-        do_reboot_dtb_specified(u_boot_config, u_boot_console, 'test_sig.dtb')
+        do_reboot_dtb_specified(u_boot_config, ubman, 'test_sig.dtb')
 
         capsule_early = u_boot_config.buildconfig.get(
             'config_efi_capsule_on_disk_early')
-        with u_boot_console.log.section('Test Case 3-b, after reboot'):
+        with ubman.log.section('Test Case 3-b, after reboot'):
             if not capsule_early:
-                exec_manual_update(u_boot_console, disk_img, capsule_files)
+                exec_manual_update(ubman, disk_img, capsule_files)
 
             # deleted any way
-            check_file_removed(u_boot_console, disk_img, capsule_files)
+            check_file_removed(ubman, disk_img, capsule_files)
 
             # TODO: check CapsuleStatus in CapsuleXXXX
 
-            verify_content(u_boot_console, '100000', 'u-boot:Old')
+            verify_content(ubman, '100000', 'u-boot:Old')
 
     def test_efi_capsule_auth4(
-            self, u_boot_config, u_boot_console, efi_capsule_data):
+            self, u_boot_config, ubman, efi_capsule_data):
         """Test Case 4 - Update U-Boot on SPI Flash, raw image format with version information
         0x100000-0x150000: U-Boot binary (but dummy)
 
@@ -136,22 +136,22 @@ class TestEfiCapsuleFirmwareSignedFit():
         """
         disk_img = efi_capsule_data
         capsule_files = ['Test114']
-        with u_boot_console.log.section('Test Case 4-a, before reboot'):
-            capsule_setup(u_boot_console, disk_img, '0x0000000000000004')
-            init_content(u_boot_console, '100000', 'u-boot.bin.old', 'Old')
-            place_capsule_file(u_boot_console, capsule_files)
+        with ubman.log.section('Test Case 4-a, before reboot'):
+            capsule_setup(ubman, disk_img, '0x0000000000000004')
+            init_content(ubman, '100000', 'u-boot.bin.old', 'Old')
+            place_capsule_file(ubman, capsule_files)
 
-        do_reboot_dtb_specified(u_boot_config, u_boot_console, 'test_ver.dtb')
+        do_reboot_dtb_specified(u_boot_config, ubman, 'test_ver.dtb')
 
         capsule_early = u_boot_config.buildconfig.get(
             'config_efi_capsule_on_disk_early')
-        with u_boot_console.log.section('Test Case 4-b, after reboot'):
+        with ubman.log.section('Test Case 4-b, after reboot'):
             if not capsule_early:
-                exec_manual_update(u_boot_console, disk_img, capsule_files)
+                exec_manual_update(ubman, disk_img, capsule_files)
 
-            check_file_removed(u_boot_console, disk_img, capsule_files)
+            check_file_removed(ubman, disk_img, capsule_files)
 
-            output = u_boot_console.run_command_list([
+            output = ubman.run_command_list([
                 'env set dfu_alt_info "sf 0:0=u-boot-bin raw 0x100000 0x50000;'
                 'u-boot-env raw 0x150000 0x200000"',
                 'efidebug capsule esrt'])
@@ -161,11 +161,11 @@ class TestEfiCapsuleFirmwareSignedFit():
             assert 'ESRT: fw_version=5' in ''.join(output)
             assert 'ESRT: lowest_supported_fw_version=3' in ''.join(output)
 
-            verify_content(u_boot_console, '100000', 'u-boot:New')
-            verify_content(u_boot_console, '150000', 'u-boot-env:New')
+            verify_content(ubman, '100000', 'u-boot:New')
+            verify_content(ubman, '150000', 'u-boot-env:New')
 
     def test_efi_capsule_auth5(
-            self, u_boot_config, u_boot_console, efi_capsule_data):
+            self, u_boot_config, ubman, efi_capsule_data):
         """Test Case 5 - Update U-Boot on SPI Flash, raw image format with version information
         0x100000-0x150000: U-Boot binary (but dummy)
 
@@ -175,19 +175,19 @@ class TestEfiCapsuleFirmwareSignedFit():
         """
         disk_img = efi_capsule_data
         capsule_files = ['Test115']
-        with u_boot_console.log.section('Test Case 5-a, before reboot'):
-            capsule_setup(u_boot_console, disk_img, '0x0000000000000004')
-            init_content(u_boot_console, '100000', 'u-boot.bin.old', 'Old')
-            place_capsule_file(u_boot_console, capsule_files)
+        with ubman.log.section('Test Case 5-a, before reboot'):
+            capsule_setup(ubman, disk_img, '0x0000000000000004')
+            init_content(ubman, '100000', 'u-boot.bin.old', 'Old')
+            place_capsule_file(ubman, capsule_files)
 
-        do_reboot_dtb_specified(u_boot_config, u_boot_console, 'test_ver.dtb')
+        do_reboot_dtb_specified(u_boot_config, ubman, 'test_ver.dtb')
 
         capsule_early = u_boot_config.buildconfig.get(
             'config_efi_capsule_on_disk_early')
-        with u_boot_console.log.section('Test Case 5-b, after reboot'):
+        with ubman.log.section('Test Case 5-b, after reboot'):
             if not capsule_early:
-                exec_manual_update(u_boot_console, disk_img, capsule_files)
+                exec_manual_update(ubman, disk_img, capsule_files)
 
-            check_file_removed(u_boot_console, disk_img, capsule_files)
+            check_file_removed(ubman, disk_img, capsule_files)
 
-            verify_content(u_boot_console, '100000', 'u-boot:Old')
+            verify_content(ubman, '100000', 'u-boot:Old')
diff --git a/test/py/tests/test_efi_capsule/test_capsule_firmware_signed_raw.py b/test/py/tests/test_efi_capsule/test_capsule_firmware_signed_raw.py
index 439bd71b3a7..a500c499bb9 100644
--- a/test/py/tests/test_efi_capsule/test_capsule_firmware_signed_raw.py
+++ b/test/py/tests/test_efi_capsule/test_capsule_firmware_signed_raw.py
@@ -34,7 +34,7 @@ class TestEfiCapsuleFirmwareSignedRaw():
     """
 
     def test_efi_capsule_auth1(
-            self, u_boot_config, u_boot_console, efi_capsule_data):
+            self, u_boot_config, ubman, efi_capsule_data):
         """Test Case 1 - Update U-Boot on SPI Flash, raw image format
         0x100000-0x150000: U-Boot binary (but dummy)
 
@@ -43,25 +43,25 @@ class TestEfiCapsuleFirmwareSignedRaw():
         """
         disk_img = efi_capsule_data
         capsule_files =  ['Test11']
-        with u_boot_console.log.section('Test Case 1-a, before reboot'):
-            capsule_setup(u_boot_console, disk_img, '0x0000000000000004')
-            init_content(u_boot_console, '100000', 'u-boot.bin.old', 'Old')
-            place_capsule_file(u_boot_console, capsule_files)
+        with ubman.log.section('Test Case 1-a, before reboot'):
+            capsule_setup(ubman, disk_img, '0x0000000000000004')
+            init_content(ubman, '100000', 'u-boot.bin.old', 'Old')
+            place_capsule_file(ubman, capsule_files)
 
-        do_reboot_dtb_specified(u_boot_config, u_boot_console, 'test_sig.dtb')
+        do_reboot_dtb_specified(u_boot_config, ubman, 'test_sig.dtb')
 
         capsule_early = u_boot_config.buildconfig.get(
             'config_efi_capsule_on_disk_early')
-        with u_boot_console.log.section('Test Case 1-b, after reboot'):
+        with ubman.log.section('Test Case 1-b, after reboot'):
             if not capsule_early:
-                exec_manual_update(u_boot_console, disk_img, capsule_files)
+                exec_manual_update(ubman, disk_img, capsule_files)
 
-            check_file_removed(u_boot_console, disk_img, capsule_files)
+            check_file_removed(ubman, disk_img, capsule_files)
 
-            verify_content(u_boot_console, '100000', 'u-boot:New')
+            verify_content(ubman, '100000', 'u-boot:New')
 
     def test_efi_capsule_auth2(
-            self, u_boot_config, u_boot_console, efi_capsule_data):
+            self, u_boot_config, ubman, efi_capsule_data):
         """Test Case 2 - Update U-Boot on SPI Flash, raw image format
         0x100000-0x150000: U-Boot binary (but dummy)
 
@@ -71,27 +71,27 @@ class TestEfiCapsuleFirmwareSignedRaw():
         """
         disk_img = efi_capsule_data
         capsule_files = ['Test12']
-        with u_boot_console.log.section('Test Case 2-a, before reboot'):
-            capsule_setup(u_boot_console, disk_img, '0x0000000000000004')
-            init_content(u_boot_console, '100000', 'u-boot.bin.old', 'Old')
-            place_capsule_file(u_boot_console, capsule_files)
+        with ubman.log.section('Test Case 2-a, before reboot'):
+            capsule_setup(ubman, disk_img, '0x0000000000000004')
+            init_content(ubman, '100000', 'u-boot.bin.old', 'Old')
+            place_capsule_file(ubman, capsule_files)
 
-        do_reboot_dtb_specified(u_boot_config, u_boot_console, 'test_sig.dtb')
+        do_reboot_dtb_specified(u_boot_config, ubman, 'test_sig.dtb')
 
         capsule_early = u_boot_config.buildconfig.get(
             'config_efi_capsule_on_disk_early')
-        with u_boot_console.log.section('Test Case 2-b, after reboot'):
+        with ubman.log.section('Test Case 2-b, after reboot'):
             if not capsule_early:
-                exec_manual_update(u_boot_console, disk_img, capsule_files)
+                exec_manual_update(ubman, disk_img, capsule_files)
 
-            check_file_removed(u_boot_console, disk_img, capsule_files)
+            check_file_removed(ubman, disk_img, capsule_files)
 
             # TODO: check CapsuleStatus in CapsuleXXXX
 
-            verify_content(u_boot_console, '100000', 'u-boot:Old')
+            verify_content(ubman, '100000', 'u-boot:Old')
 
     def test_efi_capsule_auth3(
-            self, u_boot_config, u_boot_console, efi_capsule_data):
+            self, u_boot_config, ubman, efi_capsule_data):
         """Test Case 3 - Update U-Boot on SPI Flash, raw image format
         0x100000-0x150000: U-Boot binary (but dummy)
 
@@ -100,28 +100,28 @@ class TestEfiCapsuleFirmwareSignedRaw():
         """
         disk_img = efi_capsule_data
         capsule_files = ['Test02']
-        with u_boot_console.log.section('Test Case 3-a, before reboot'):
-            capsule_setup(u_boot_console, disk_img, '0x0000000000000004')
-            init_content(u_boot_console, '100000', 'u-boot.bin.old', 'Old')
-            place_capsule_file(u_boot_console, capsule_files)
+        with ubman.log.section('Test Case 3-a, before reboot'):
+            capsule_setup(ubman, disk_img, '0x0000000000000004')
+            init_content(ubman, '100000', 'u-boot.bin.old', 'Old')
+            place_capsule_file(ubman, capsule_files)
 
-        do_reboot_dtb_specified(u_boot_config, u_boot_console, 'test_sig.dtb')
+        do_reboot_dtb_specified(u_boot_config, ubman, 'test_sig.dtb')
 
         capsule_early = u_boot_config.buildconfig.get(
             'config_efi_capsule_on_disk_early')
-        with u_boot_console.log.section('Test Case 3-b, after reboot'):
+        with ubman.log.section('Test Case 3-b, after reboot'):
             if not capsule_early:
-                exec_manual_update(u_boot_console, disk_img, capsule_files)
+                exec_manual_update(ubman, disk_img, capsule_files)
 
             # deleted anyway
-            check_file_removed(u_boot_console, disk_img, capsule_files)
+            check_file_removed(ubman, disk_img, capsule_files)
 
             # TODO: check CapsuleStatus in CapsuleXXXX
 
-            verify_content(u_boot_console, '100000', 'u-boot:Old')
+            verify_content(ubman, '100000', 'u-boot:Old')
 
     def test_efi_capsule_auth4(
-            self, u_boot_config, u_boot_console, efi_capsule_data):
+            self, u_boot_config, ubman, efi_capsule_data):
         """Test Case 4 - Update U-Boot on SPI Flash, raw image format with version information
         0x100000-0x150000: U-Boot binary (but dummy)
 
@@ -130,22 +130,22 @@ class TestEfiCapsuleFirmwareSignedRaw():
         """
         disk_img = efi_capsule_data
         capsule_files = ['Test111', 'Test112']
-        with u_boot_console.log.section('Test Case 4-a, before reboot'):
-            capsule_setup(u_boot_console, disk_img, '0x0000000000000004')
-            init_content(u_boot_console, '100000', 'u-boot.bin.old', 'Old')
-            place_capsule_file(u_boot_console, capsule_files)
+        with ubman.log.section('Test Case 4-a, before reboot'):
+            capsule_setup(ubman, disk_img, '0x0000000000000004')
+            init_content(ubman, '100000', 'u-boot.bin.old', 'Old')
+            place_capsule_file(ubman, capsule_files)
 
-        do_reboot_dtb_specified(u_boot_config, u_boot_console, 'test_ver.dtb')
+        do_reboot_dtb_specified(u_boot_config, ubman, 'test_ver.dtb')
 
         capsule_early = u_boot_config.buildconfig.get(
             'config_efi_capsule_on_disk_early')
-        with u_boot_console.log.section('Test Case 4-b, after reboot'):
+        with ubman.log.section('Test Case 4-b, after reboot'):
             if not capsule_early:
-                exec_manual_update(u_boot_console, disk_img, capsule_files)
+                exec_manual_update(ubman, disk_img, capsule_files)
 
-            check_file_removed(u_boot_console, disk_img, capsule_files)
+            check_file_removed(ubman, disk_img, capsule_files)
 
-            output = u_boot_console.run_command_list([
+            output = ubman.run_command_list([
                 'env set dfu_alt_info "sf 0:0=u-boot-bin raw 0x100000 0x50000;'
                 'u-boot-env raw 0x150000 0x200000"',
                 'efidebug capsule esrt'])
@@ -160,11 +160,11 @@ class TestEfiCapsuleFirmwareSignedRaw():
             assert 'ESRT: fw_version=10' in ''.join(output)
             assert 'ESRT: lowest_supported_fw_version=7' in ''.join(output)
 
-            verify_content(u_boot_console, '100000', 'u-boot:New')
-            verify_content(u_boot_console, '150000', 'u-boot-env:New')
+            verify_content(ubman, '100000', 'u-boot:New')
+            verify_content(ubman, '150000', 'u-boot-env:New')
 
     def test_efi_capsule_auth5(
-            self, u_boot_config, u_boot_console, efi_capsule_data):
+            self, u_boot_config, ubman, efi_capsule_data):
         """Test Case 5 - Update U-Boot on SPI Flash, raw image format with version information
         0x100000-0x150000: U-Boot binary (but dummy)
 
@@ -174,19 +174,19 @@ class TestEfiCapsuleFirmwareSignedRaw():
         """
         disk_img = efi_capsule_data
         capsule_files = ['Test113']
-        with u_boot_console.log.section('Test Case 5-a, before reboot'):
-            capsule_setup(u_boot_console, disk_img, '0x0000000000000004')
-            init_content(u_boot_console, '100000', 'u-boot.bin.old', 'Old')
-            place_capsule_file(u_boot_console, capsule_files)
+        with ubman.log.section('Test Case 5-a, before reboot'):
+            capsule_setup(ubman, disk_img, '0x0000000000000004')
+            init_content(ubman, '100000', 'u-boot.bin.old', 'Old')
+            place_capsule_file(ubman, capsule_files)
 
-        do_reboot_dtb_specified(u_boot_config, u_boot_console, 'test_ver.dtb')
+        do_reboot_dtb_specified(u_boot_config, ubman, 'test_ver.dtb')
 
         capsule_early = u_boot_config.buildconfig.get(
             'config_efi_capsule_on_disk_early')
-        with u_boot_console.log.section('Test Case 5-b, after reboot'):
+        with ubman.log.section('Test Case 5-b, after reboot'):
             if not capsule_early:
-                exec_manual_update(u_boot_console, disk_img, capsule_files)
+                exec_manual_update(ubman, disk_img, capsule_files)
 
-            check_file_removed(u_boot_console, disk_img, capsule_files)
+            check_file_removed(ubman, disk_img, capsule_files)
 
-            verify_content(u_boot_console, '100000', 'u-boot:Old')
+            verify_content(ubman, '100000', 'u-boot:Old')
diff --git a/test/py/tests/test_efi_fit.py b/test/py/tests/test_efi_fit.py
index 550058a30fd..5f352e7efff 100644
--- a/test/py/tests/test_efi_fit.py
+++ b/test/py/tests/test_efi_fit.py
@@ -55,7 +55,7 @@ env__efi_fit_tftp_file = {
 
 import os.path
 import pytest
-import u_boot_utils as util
+import utils
 
 # Define the parametrized ITS data to be used for FIT images generation.
 ITS_DATA = '''
@@ -123,7 +123,7 @@ FDT_DATA = '''
 @pytest.mark.buildconfigspec('fit')
 @pytest.mark.notbuildconfigspec('generate_acpi_table')
 @pytest.mark.requiredtool('dtc')
-def test_efi_fit_launch(u_boot_console):
+def test_efi_fit_launch(ubman):
     """Test handling of UEFI binaries inside FIT images.
 
     The tests are trying to launch U-Boot's helloworld.efi embedded into
@@ -148,13 +148,13 @@ def test_efi_fit_launch(u_boot_console):
         at the beginning of this file.
         """
 
-        init_usb = cons.config.env.get('env__net_uses_usb', False)
+        init_usb = ubman.config.env.get('env__net_uses_usb', False)
         if init_usb:
-            cons.run_command('usb start')
+            ubman.run_command('usb start')
 
-        init_pci = cons.config.env.get('env__net_uses_pci', False)
+        init_pci = ubman.config.env.get('env__net_uses_pci', False)
         if init_pci:
-            cons.run_command('pci enum')
+            ubman.run_command('pci enum')
 
     def net_dhcp():
         """Execute the dhcp command.
@@ -163,18 +163,18 @@ def test_efi_fit_launch(u_boot_console):
         comment at the beginning of this file.
         """
 
-        has_dhcp = cons.config.buildconfig.get('config_cmd_dhcp', 'n') == 'y'
+        has_dhcp = ubman.config.buildconfig.get('config_cmd_dhcp', 'n') == 'y'
         if not has_dhcp:
-            cons.log.warning('CONFIG_CMD_DHCP != y: Skipping DHCP network setup')
+            ubman.log.warning('CONFIG_CMD_DHCP != y: Skipping DHCP network setup')
             return False
 
-        test_dhcp = cons.config.env.get('env__net_dhcp_server', False)
+        test_dhcp = ubman.config.env.get('env__net_dhcp_server', False)
         if not test_dhcp:
-            cons.log.info('No DHCP server available')
+            ubman.log.info('No DHCP server available')
             return False
 
-        cons.run_command('setenv autoload no')
-        output = cons.run_command('dhcp')
+        ubman.run_command('setenv autoload no')
+        output = ubman.run_command('dhcp')
         assert 'DHCP client bound to address ' in output
         return True
 
@@ -185,18 +185,18 @@ def test_efi_fit_launch(u_boot_console):
         the beginning of this file.
         """
 
-        has_dhcp = cons.config.buildconfig.get('config_cmd_dhcp', 'n') == 'y'
+        has_dhcp = ubman.config.buildconfig.get('config_cmd_dhcp', 'n') == 'y'
         if not has_dhcp:
-            cons.log.warning('CONFIG_NET != y: Skipping static network setup')
+            ubman.log.warning('CONFIG_NET != y: Skipping static network setup')
             return False
 
-        env_vars = cons.config.env.get('env__net_static_env_vars', None)
+        env_vars = ubman.config.env.get('env__net_static_env_vars', None)
         if not env_vars:
-            cons.log.info('No static network configuration is defined')
+            ubman.log.info('No static network configuration is defined')
             return False
 
         for (var, val) in env_vars:
-            cons.run_command('setenv %s %s' % (var, val))
+            ubman.run_command('setenv %s %s' % (var, val))
         return True
 
     def make_fpath(file_name):
@@ -208,7 +208,7 @@ def test_efi_fit_launch(u_boot_console):
             The computed file path.
         """
 
-        return os.path.join(cons.config.build_dir, file_name)
+        return os.path.join(ubman.config.build_dir, file_name)
 
     def make_efi(fname, comp):
         """Create an UEFI binary.
@@ -224,11 +224,11 @@ def test_efi_fit_launch(u_boot_console):
         """
 
         bin_path = make_fpath(fname)
-        util.run_and_log(cons,
-                         ['cp', make_fpath('lib/efi_loader/helloworld.efi'),
-                          bin_path])
+        utils.run_and_log(ubman,
+                          ['cp', make_fpath('lib/efi_loader/helloworld.efi'),
+                           bin_path])
         if comp:
-            util.run_and_log(cons, ['gzip', '-f', bin_path])
+            utils.run_and_log(ubman, ['gzip', '-f', bin_path])
             bin_path += '.gz'
         return bin_path
 
@@ -257,9 +257,10 @@ def test_efi_fit_launch(u_boot_console):
 
         # Build the test FDT.
         dtb = make_fpath('test-efi-fit-%s.dtb' % fdt_type)
-        util.run_and_log(cons, ['dtc', '-I', 'dts', '-O', 'dtb', '-o', dtb, dts])
+        utils.run_and_log(ubman,
+                          ['dtc', '-I', 'dts', '-O', 'dtb', '-o', dtb, dts])
         if comp:
-            util.run_and_log(cons, ['gzip', '-f', dtb])
+            utils.run_and_log(ubman, ['gzip', '-f', dtb])
             dtb += '.gz'
         return dtb
 
@@ -290,8 +291,8 @@ def test_efi_fit_launch(u_boot_console):
 
         # Build the test ITS.
         fit_path = make_fpath('test-efi-fit-helloworld.fit')
-        util.run_and_log(
-            cons, [make_fpath('tools/mkimage'), '-f', its_path, fit_path])
+        utils.run_and_log(
+            ubman, [make_fpath('tools/mkimage'), '-f', its_path, fit_path])
         return fit_path
 
     def load_fit_from_host(fit):
@@ -307,9 +308,9 @@ def test_efi_fit_launch(u_boot_console):
 
         addr = fit.get('addr', None)
         if not addr:
-            addr = util.find_ram_base(cons)
+            addr = utils.find_ram_base(ubman)
 
-        output = cons.run_command(
+        output = ubman.run_command(
             'host load hostfs - %x %s/%s' % (addr, fit['dn'], fit['fn']))
         expected_text = ' bytes read'
         size = fit.get('size', None)
@@ -334,10 +335,10 @@ def test_efi_fit_launch(u_boot_console):
 
         addr = fit.get('addr', None)
         if not addr:
-            addr = util.find_ram_base(cons)
+            addr = utils.find_ram_base(ubman)
 
         file_name = fit['fn']
-        output = cons.run_command('tftpboot %x %s' % (addr, file_name))
+        output = ubman.run_command('tftpboot %x %s' % (addr, file_name))
         expected_text = 'Bytes transferred = '
         size = fit.get('size', None)
         if size:
@@ -348,10 +349,10 @@ def test_efi_fit_launch(u_boot_console):
         if not expected_crc:
             return addr
 
-        if cons.config.buildconfig.get('config_cmd_crc32', 'n') != 'y':
+        if ubman.config.buildconfig.get('config_cmd_crc32', 'n') != 'y':
             return addr
 
-        output = cons.run_command('crc32 $fileaddr $filesize')
+        output = ubman.run_command('crc32 $fileaddr $filesize')
         assert expected_crc in output
 
         return addr
@@ -383,10 +384,10 @@ def test_efi_fit_launch(u_boot_console):
                            generated content.
         """
 
-        with cons.log.section('FDT=%s;COMP=%s' % (enable_fdt, enable_comp)):
+        with ubman.log.section('FDT=%s;COMP=%s' % (enable_fdt, enable_comp)):
             if is_sandbox:
                 fit = {
-                    'dn': cons.config.build_dir,
+                    'dn': ubman.config.build_dir,
                 }
             else:
                 # Init networking.
@@ -396,7 +397,7 @@ def test_efi_fit_launch(u_boot_console):
                 if not net_set_up:
                     pytest.skip('Network not initialized')
 
-                fit = cons.config.env.get('env__efi_fit_tftp_file', None)
+                fit = ubman.config.env.get('env__efi_fit_tftp_file', None)
                 if not fit:
                     pytest.skip('No env__efi_fit_tftp_file binary specified in environment')
 
@@ -411,8 +412,9 @@ def test_efi_fit_launch(u_boot_console):
                 fit['size'] = os.path.getsize(fit_path)
 
                 # Copy image to TFTP root directory.
-                if fit['dn'] != cons.config.build_dir:
-                    util.run_and_log(cons, ['mv', '-f', fit_path, '%s/' % fit['dn']])
+                if fit['dn'] != ubman.config.build_dir:
+                    utils.run_and_log(ubman,
+                                      ['mv', '-f', fit_path, '%s/' % fit['dn']])
 
             # Load FIT image.
             addr = load_fit_from_host(fit) if is_sandbox else load_fit_from_tftp(fit)
@@ -421,31 +423,30 @@ def test_efi_fit_launch(u_boot_console):
             fit_config = 'config-efi-fdt' if enable_fdt else 'config-efi-nofdt'
 
             # Try booting.
-            output = cons.run_command('bootm %x#%s' % (addr, fit_config))
+            output = ubman.run_command('bootm %x#%s' % (addr, fit_config))
             if enable_fdt:
                 assert 'Booting using the fdt blob' in output
             assert 'Hello, world' in output
             assert '## Application failed' not in output
-            cons.restart_uboot()
+            ubman.restart_uboot()
 
-    cons = u_boot_console
     # Array slice removes leading/trailing quotes.
-    sys_arch = cons.config.buildconfig.get('config_sys_arch', '"sandbox"')[1:-1]
+    sys_arch = ubman.config.buildconfig.get('config_sys_arch', '"sandbox"')[1:-1]
     if sys_arch == 'arm':
-        arm64 = cons.config.buildconfig.get('config_arm64')
+        arm64 = ubman.config.buildconfig.get('config_arm64')
         if arm64:
             sys_arch = 'arm64'
 
     is_sandbox = sys_arch == 'sandbox'
 
     if is_sandbox:
-        old_dtb = cons.config.dtb
+        old_dtb = ubman.config.dtb
 
     try:
         if is_sandbox:
             # Use our own device tree file, will be restored afterwards.
             control_dtb = make_dtb('internal', False)
-            cons.config.dtb = control_dtb
+            ubman.config.dtb = control_dtb
 
         # Run tests
         # - fdt OFF, gzip OFF
@@ -462,5 +463,5 @@ def test_efi_fit_launch(u_boot_console):
     finally:
         if is_sandbox:
             # Go back to the original U-Boot with the correct dtb.
-            cons.config.dtb = old_dtb
-            cons.restart_uboot()
+            ubman.config.dtb = old_dtb
+            ubman.restart_uboot()
diff --git a/test/py/tests/test_efi_loader.py b/test/py/tests/test_efi_loader.py
index 33434935fe9..58f2655191f 100644
--- a/test/py/tests/test_efi_loader.py
+++ b/test/py/tests/test_efi_loader.py
@@ -53,71 +53,71 @@ env__efi_helloworld_net_http_test_skip = True
 """
 
 import pytest
-import u_boot_utils
+import utils
 
 PROTO_TFTP, PROTO_HTTP = range(0, 2)
 
 net_set_up = False
 
-def test_efi_pre_commands(u_boot_console):
+def test_efi_pre_commands(ubman):
     """Execute any commands required to enable network hardware.
 
     These commands are provided by the boardenv_* file; see the comment at the
     beginning of this file.
     """
 
-    init_usb = u_boot_console.config.env.get('env__net_uses_usb', False)
+    init_usb = ubman.config.env.get('env__net_uses_usb', False)
     if init_usb:
-        u_boot_console.run_command('usb start')
+        ubman.run_command('usb start')
 
-    init_pci = u_boot_console.config.env.get('env__net_uses_pci', False)
+    init_pci = ubman.config.env.get('env__net_uses_pci', False)
     if init_pci:
-        u_boot_console.run_command('pci enum')
+        ubman.run_command('pci enum')
 
 @pytest.mark.buildconfigspec('cmd_dhcp')
-def test_efi_setup_dhcp(u_boot_console):
+def test_efi_setup_dhcp(ubman):
     """Set up the network using DHCP.
 
     The boardenv_* file may be used to enable/disable this test; see the
     comment at the beginning of this file.
     """
 
-    test_dhcp = u_boot_console.config.env.get('env__net_dhcp_server', False)
+    test_dhcp = ubman.config.env.get('env__net_dhcp_server', False)
     if not test_dhcp:
-        env_vars = u_boot_console.config.env.get('env__net_static_env_vars', None)
+        env_vars = ubman.config.env.get('env__net_static_env_vars', None)
         if not env_vars:
             pytest.skip('No DHCP server available')
         return
 
-    u_boot_console.run_command('setenv autoload no')
-    output = u_boot_console.run_command('dhcp')
+    ubman.run_command('setenv autoload no')
+    output = ubman.run_command('dhcp')
     assert 'DHCP client bound to address ' in output
 
     global net_set_up
     net_set_up = True
 
 @pytest.mark.buildconfigspec('net')
-def test_efi_setup_static(u_boot_console):
+def test_efi_setup_static(ubman):
     """Set up the network using a static IP configuration.
 
     The configuration is provided by the boardenv_* file; see the comment at
     the beginning of this file.
     """
 
-    env_vars = u_boot_console.config.env.get('env__net_static_env_vars', None)
+    env_vars = ubman.config.env.get('env__net_static_env_vars', None)
     if not env_vars:
-        test_dhcp = u_boot_console.config.env.get('env__net_dhcp_server', False)
+        test_dhcp = ubman.config.env.get('env__net_dhcp_server', False)
         if not test_dhcp:
             pytest.skip('No static network configuration is defined')
         return None
 
     for (var, val) in env_vars:
-        u_boot_console.run_command('setenv %s %s' % (var, val))
+        ubman.run_command('setenv %s %s' % (var, val))
 
     global net_set_up
     net_set_up = True
 
-def fetch_file(u_boot_console, env_conf, proto):
+def fetch_file(ubman, env_conf, proto):
     """Grab an env described file via TFTP or HTTP and return its address
 
     A file as described by an env config <env_conf> is downloaded from the
@@ -126,13 +126,13 @@ def fetch_file(u_boot_console, env_conf, proto):
     if not net_set_up:
         pytest.skip('Network not initialized')
 
-    f = u_boot_console.config.env.get(env_conf, None)
+    f = ubman.config.env.get(env_conf, None)
     if not f:
         pytest.skip('No %s binary specified in environment' % env_conf)
 
     addr = f.get('addr', None)
     if not addr:
-        addr = u_boot_utils.find_ram_base(u_boot_console)
+        addr = utils.find_ram_base(ubman)
 
     fn = f['fn']
     if proto == PROTO_TFTP:
@@ -141,7 +141,7 @@ def fetch_file(u_boot_console, env_conf, proto):
         cmd = 'wget'
     else:
         assert False
-    output = u_boot_console.run_command('%s %x %s' % (cmd, addr, fn))
+    output = ubman.run_command('%s %x %s' % (cmd, addr, fn))
     expected_text = 'Bytes transferred = '
     sz = f.get('size', None)
     if sz:
@@ -152,18 +152,18 @@ def fetch_file(u_boot_console, env_conf, proto):
     if not expected_crc:
         return addr
 
-    if u_boot_console.config.buildconfig.get('config_cmd_crc32', 'n') != 'y':
+    if ubman.config.buildconfig.get('config_cmd_crc32', 'n') != 'y':
         return addr
 
-    output = u_boot_console.run_command('crc32 %x $filesize' % addr)
+    output = ubman.run_command('crc32 %x $filesize' % addr)
     assert expected_crc in output
 
     return addr
 
-def do_test_efi_helloworld_net(u_boot_console, proto):
-    addr = fetch_file(u_boot_console, 'env__efi_loader_helloworld_file', proto)
+def do_test_efi_helloworld_net(ubman, proto):
+    addr = fetch_file(ubman, 'env__efi_loader_helloworld_file', proto)
 
-    output = u_boot_console.run_command('bootefi %x' % addr)
+    output = ubman.run_command('bootefi %x' % addr)
     expected_text = 'Hello, world'
     assert expected_text in output
     expected_text = '## Application failed'
@@ -172,65 +172,65 @@ def do_test_efi_helloworld_net(u_boot_console, proto):
 @pytest.mark.buildconfigspec('of_control')
 @pytest.mark.buildconfigspec('bootefi_hello_compile')
 @pytest.mark.buildconfigspec('cmd_tftpboot')
-def test_efi_helloworld_net_tftp(u_boot_console):
+def test_efi_helloworld_net_tftp(ubman):
     """Run the helloworld.efi binary via TFTP.
 
     The helloworld.efi file is downloaded from the TFTP server and is executed
     using the fallback device tree at $fdtcontroladdr.
     """
 
-    do_test_efi_helloworld_net(u_boot_console, PROTO_TFTP);
+    do_test_efi_helloworld_net(ubman, PROTO_TFTP);
 
 @pytest.mark.buildconfigspec('of_control')
 @pytest.mark.buildconfigspec('bootefi_hello_compile')
 @pytest.mark.buildconfigspec('cmd_wget')
-def test_efi_helloworld_net_http(u_boot_console):
+def test_efi_helloworld_net_http(ubman):
     """Run the helloworld.efi binary via HTTP.
 
     The helloworld.efi file is downloaded from the HTTP server and is executed
     using the fallback device tree at $fdtcontroladdr.
     """
-    if u_boot_console.config.env.get('env__efi_helloworld_net_http_test_skip', True):
+    if ubman.config.env.get('env__efi_helloworld_net_http_test_skip', True):
         pytest.skip('helloworld.efi HTTP test is not enabled!')
 
-    do_test_efi_helloworld_net(u_boot_console, PROTO_HTTP);
+    do_test_efi_helloworld_net(ubman, PROTO_HTTP);
 
 @pytest.mark.buildconfigspec('cmd_bootefi_hello')
-def test_efi_helloworld_builtin(u_boot_console):
+def test_efi_helloworld_builtin(ubman):
     """Run the builtin helloworld.efi binary.
 
     The helloworld.efi file is included in U-Boot, execute it using the
     special "bootefi hello" command.
     """
 
-    output = u_boot_console.run_command('bootefi hello')
+    output = ubman.run_command('bootefi hello')
     expected_text = 'Hello, world'
     assert expected_text in output
 
 @pytest.mark.buildconfigspec('of_control')
 @pytest.mark.buildconfigspec('cmd_bootefi')
 @pytest.mark.buildconfigspec('cmd_tftpboot')
-def test_efi_grub_net(u_boot_console):
+def test_efi_grub_net(ubman):
     """Run the grub.efi binary via TFTP.
 
     The grub.efi file is downloaded from the TFTP server and gets
     executed.
     """
 
-    addr = fetch_file(u_boot_console, 'env__efi_loader_grub_file', PROTO_TFTP)
+    addr = fetch_file(ubman, 'env__efi_loader_grub_file', PROTO_TFTP)
 
-    u_boot_console.run_command('bootefi %x' % addr, wait_for_prompt=False)
+    ubman.run_command('bootefi %x' % addr, wait_for_prompt=False)
 
     # Verify that we have an SMBIOS table
-    check_smbios = u_boot_console.config.env.get('env__efi_loader_check_smbios', False)
+    check_smbios = ubman.config.env.get('env__efi_loader_check_smbios', False)
     if check_smbios:
-        u_boot_console.wait_for('grub>')
-        u_boot_console.run_command('lsefisystab', wait_for_prompt=False, wait_for_echo=False)
-        u_boot_console.wait_for('SMBIOS')
+        ubman.wait_for('grub>')
+        ubman.run_command('lsefisystab', wait_for_prompt=False, wait_for_echo=False)
+        ubman.wait_for('SMBIOS')
 
     # Then exit cleanly
-    u_boot_console.wait_for('grub>')
-    u_boot_console.run_command('exit', wait_for_prompt=False, wait_for_echo=False)
-    u_boot_console.wait_for(u_boot_console.prompt)
+    ubman.wait_for('grub>')
+    ubman.run_command('exit', wait_for_prompt=False, wait_for_echo=False)
+    ubman.wait_for(ubman.prompt)
     # And give us our U-Boot prompt back
-    u_boot_console.run_command('')
+    ubman.run_command('')
diff --git a/test/py/tests/test_efi_secboot/test_authvar.py b/test/py/tests/test_efi_secboot/test_authvar.py
index d5aeb650480..7b45f8fb814 100644
--- a/test/py/tests/test_efi_secboot/test_authvar.py
+++ b/test/py/tests/test_efi_secboot/test_authvar.py
@@ -17,119 +17,119 @@ import pytest
 @pytest.mark.buildconfigspec('cmd_nvedit_efi')
 @pytest.mark.slow
 class TestEfiAuthVar(object):
-    def test_efi_var_auth1(self, u_boot_console, efi_boot_env):
+    def test_efi_var_auth1(self, ubman, efi_boot_env):
         """
         Test Case 1 - Install signature database
         """
-        u_boot_console.restart_uboot()
+        ubman.restart_uboot()
         disk_img = efi_boot_env
-        with u_boot_console.log.section('Test Case 1a'):
+        with ubman.log.section('Test Case 1a'):
             # Test Case 1a, Initial secure state
-            output = u_boot_console.run_command_list([
+            output = ubman.run_command_list([
                 'host bind 0 %s' % disk_img,
                 'printenv -e SecureBoot'])
             assert '00000000: 00' in ''.join(output)
 
-            output = u_boot_console.run_command(
+            output = ubman.run_command(
                 'printenv -e SetupMode')
             assert '00000000: 01' in output
 
-        with u_boot_console.log.section('Test Case 1b'):
+        with ubman.log.section('Test Case 1b'):
             # Test Case 1b, PK without AUTHENTICATED_WRITE_ACCESS
-            output = u_boot_console.run_command_list([
+            output = ubman.run_command_list([
                 'fatload host 0:1 4000000 PK.auth',
                 'setenv -e -nv -bs -rt -i 4000000:$filesize PK'])
             assert 'Failed to set EFI variable' in ''.join(output)
 
-        with u_boot_console.log.section('Test Case 1c'):
+        with ubman.log.section('Test Case 1c'):
             # Test Case 1c, install PK
-            output = u_boot_console.run_command_list([
+            output = ubman.run_command_list([
                 'fatload host 0:1 4000000 PK.auth',
                 'setenv -e -nv -bs -rt -at -i 4000000:$filesize PK',
                 'printenv -e -n PK'])
             assert 'PK:' in ''.join(output)
 
-            output = u_boot_console.run_command(
+            output = ubman.run_command(
                 'printenv -e SecureBoot')
             assert '00000000: 01' in output
-            output = u_boot_console.run_command(
+            output = ubman.run_command(
                 'printenv -e SetupMode')
             assert '00000000: 00' in output
 
-        with u_boot_console.log.section('Test Case 1d'):
+        with ubman.log.section('Test Case 1d'):
             # Test Case 1d, db/dbx without KEK
-            output = u_boot_console.run_command_list([
+            output = ubman.run_command_list([
                 'fatload host 0:1 4000000 db.auth',
                 'setenv -e -nv -bs -rt -at -i 4000000:$filesize db'])
             assert 'Failed to set EFI variable' in ''.join(output)
 
-            output = u_boot_console.run_command_list([
+            output = ubman.run_command_list([
                 'fatload host 0:1 4000000 db.auth',
                 'setenv -e -nv -bs -rt -at -i 4000000:$filesize dbx'])
             assert 'Failed to set EFI variable' in ''.join(output)
 
-        with u_boot_console.log.section('Test Case 1e'):
+        with ubman.log.section('Test Case 1e'):
             # Test Case 1e, install KEK
-            output = u_boot_console.run_command_list([
+            output = ubman.run_command_list([
                 'fatload host 0:1 4000000 KEK.auth',
                 'setenv -e -nv -bs -rt -i 4000000:$filesize KEK'])
             assert 'Failed to set EFI variable' in ''.join(output)
 
-            output = u_boot_console.run_command_list([
+            output = ubman.run_command_list([
                 'fatload host 0:1 4000000 KEK.auth',
                 'setenv -e -nv -bs -rt -at -i 4000000:$filesize KEK',
                 'printenv -e -n KEK'])
             assert 'KEK:' in ''.join(output)
 
-            output = u_boot_console.run_command(
+            output = ubman.run_command(
                 'printenv -e SecureBoot')
             assert '00000000: 01' in output
 
-        with u_boot_console.log.section('Test Case 1f'):
+        with ubman.log.section('Test Case 1f'):
             # Test Case 1f, install db
-            output = u_boot_console.run_command_list([
+            output = ubman.run_command_list([
                 'fatload host 0:1 4000000 db.auth',
                 'setenv -e -nv -bs -rt -i 4000000:$filesize db'])
             assert 'Failed to set EFI variable' in ''.join(output)
 
-            output = u_boot_console.run_command_list([
+            output = ubman.run_command_list([
                 'fatload host 0:1 4000000 db.auth',
                 'setenv -e -nv -bs -rt -at -i 4000000:$filesize db',
                 'printenv -e -n -guid d719b2cb-3d3a-4596-a3bc-dad00e67656f db'])
             assert 'Failed to set EFI variable' not in ''.join(output)
             assert 'db:' in ''.join(output)
 
-            output = u_boot_console.run_command(
+            output = ubman.run_command(
                 'printenv -e SecureBoot')
             assert '00000000: 01' in output
 
-        with u_boot_console.log.section('Test Case 1g'):
+        with ubman.log.section('Test Case 1g'):
             # Test Case 1g, install dbx
-            output = u_boot_console.run_command_list([
+            output = ubman.run_command_list([
                 'fatload host 0:1 4000000 dbx.auth',
                 'setenv -e -nv -bs -rt -i 4000000:$filesize dbx'])
             assert 'Failed to set EFI variable' in ''.join(output)
 
-            output = u_boot_console.run_command_list([
+            output = ubman.run_command_list([
                 'fatload host 0:1 4000000 dbx.auth',
                 'setenv -e -nv -bs -rt -at -i 4000000:$filesize dbx',
                 'printenv -e -n -guid d719b2cb-3d3a-4596-a3bc-dad00e67656f dbx'])
             assert 'Failed to set EFI variable' not in ''.join(output)
             assert 'dbx:' in ''.join(output)
 
-            output = u_boot_console.run_command(
+            output = ubman.run_command(
                 'printenv -e SecureBoot')
             assert '00000000: 01' in output
 
-    def test_efi_var_auth2(self, u_boot_console, efi_boot_env):
+    def test_efi_var_auth2(self, ubman, efi_boot_env):
         """
         Test Case 2 - Update database by overwriting
         """
-        u_boot_console.restart_uboot()
+        ubman.restart_uboot()
         disk_img = efi_boot_env
-        with u_boot_console.log.section('Test Case 2a'):
+        with ubman.log.section('Test Case 2a'):
             # Test Case 2a, update without AUTHENTICATED_WRITE_ACCESS
-            output = u_boot_console.run_command_list([
+            output = ubman.run_command_list([
                 'host bind 0 %s' % disk_img,
                 'fatload host 0:1 4000000 PK.auth',
                 'setenv -e -nv -bs -rt -at -i 4000000:$filesize PK',
@@ -141,36 +141,36 @@ class TestEfiAuthVar(object):
             assert 'Failed to set EFI variable' not in ''.join(output)
             assert 'db:' in ''.join(output)
 
-            output = u_boot_console.run_command_list([
+            output = ubman.run_command_list([
                 'fatload host 0:1 4000000 db1.auth',
                 'setenv -e -nv -bs -rt -i 4000000:$filesize db'])
             assert 'Failed to set EFI variable' in ''.join(output)
 
-        with u_boot_console.log.section('Test Case 2b'):
+        with ubman.log.section('Test Case 2b'):
             # Test Case 2b, update without correct signature
-            output = u_boot_console.run_command_list([
+            output = ubman.run_command_list([
                 'fatload host 0:1 4000000 db.esl',
                 'setenv -e -nv -bs -rt -at -i 4000000:$filesize db'])
             assert 'Failed to set EFI variable' in ''.join(output)
 
-        with u_boot_console.log.section('Test Case 2c'):
+        with ubman.log.section('Test Case 2c'):
             # Test Case 2c, update with correct signature
-            output = u_boot_console.run_command_list([
+            output = ubman.run_command_list([
                 'fatload host 0:1 4000000 db1.auth',
                 'setenv -e -nv -bs -rt -at -i 4000000:$filesize db',
                 'printenv -e -n -guid d719b2cb-3d3a-4596-a3bc-dad00e67656f db'])
             assert 'Failed to set EFI variable' not in ''.join(output)
             assert 'db:' in ''.join(output)
 
-    def test_efi_var_auth3(self, u_boot_console, efi_boot_env):
+    def test_efi_var_auth3(self, ubman, efi_boot_env):
         """
         Test Case 3 - Append database
         """
-        u_boot_console.restart_uboot()
+        ubman.restart_uboot()
         disk_img = efi_boot_env
-        with u_boot_console.log.section('Test Case 3a'):
+        with ubman.log.section('Test Case 3a'):
             # Test Case 3a, update without AUTHENTICATED_WRITE_ACCESS
-            output = u_boot_console.run_command_list([
+            output = ubman.run_command_list([
                 'host bind 0 %s' % disk_img,
                 'fatload host 0:1 4000000 PK.auth',
                 'setenv -e -nv -bs -rt -at -i 4000000:$filesize PK',
@@ -182,36 +182,36 @@ class TestEfiAuthVar(object):
             assert 'Failed to set EFI variable' not in ''.join(output)
             assert 'db:' in ''.join(output)
 
-            output = u_boot_console.run_command_list([
+            output = ubman.run_command_list([
                 'fatload host 0:1 4000000 db2.auth',
                 'setenv -e -nv -bs -rt -a -i 4000000:$filesize db'])
             assert 'Failed to set EFI variable' in ''.join(output)
 
-        with u_boot_console.log.section('Test Case 3b'):
+        with ubman.log.section('Test Case 3b'):
             # Test Case 3b, update without correct signature
-            output = u_boot_console.run_command_list([
+            output = ubman.run_command_list([
                 'fatload host 0:1 4000000 db.esl',
                 'setenv -e -nv -bs -rt -at -a -i 4000000:$filesize db'])
             assert 'Failed to set EFI variable' in ''.join(output)
 
-        with u_boot_console.log.section('Test Case 3c'):
+        with ubman.log.section('Test Case 3c'):
             # Test Case 3c, update with correct signature
-            output = u_boot_console.run_command_list([
+            output = ubman.run_command_list([
                 'fatload host 0:1 4000000 db2.auth',
                 'setenv -e -nv -bs -rt -at -a -i 4000000:$filesize db',
                 'printenv -e -n -guid d719b2cb-3d3a-4596-a3bc-dad00e67656f db'])
             assert 'Failed to set EFI variable' not in ''.join(output)
             assert 'db:' in ''.join(output)
 
-    def test_efi_var_auth4(self, u_boot_console, efi_boot_env):
+    def test_efi_var_auth4(self, ubman, efi_boot_env):
         """
         Test Case 4 - Delete database without authentication
         """
-        u_boot_console.restart_uboot()
+        ubman.restart_uboot()
         disk_img = efi_boot_env
-        with u_boot_console.log.section('Test Case 4a'):
+        with ubman.log.section('Test Case 4a'):
             # Test Case 4a, update without AUTHENTICATED_WRITE_ACCESS
-            output = u_boot_console.run_command_list([
+            output = ubman.run_command_list([
                 'host bind 0 %s' % disk_img,
                 'fatload host 0:1 4000000 PK.auth',
                 'setenv -e -nv -bs -rt -at -i 4000000:$filesize PK',
@@ -223,29 +223,29 @@ class TestEfiAuthVar(object):
             assert 'Failed to set EFI variable' not in ''.join(output)
             assert 'db:' in ''.join(output)
 
-            output = u_boot_console.run_command_list([
+            output = ubman.run_command_list([
                 'setenv -e -nv -bs -rt db',
                 'printenv -e -n -guid d719b2cb-3d3a-4596-a3bc-dad00e67656f db'])
             assert 'Failed to set EFI variable' in ''.join(output)
             assert 'db:' in ''.join(output)
 
-        with u_boot_console.log.section('Test Case 4b'):
+        with ubman.log.section('Test Case 4b'):
             # Test Case 4b, update without correct signature/data
-            output = u_boot_console.run_command_list([
+            output = ubman.run_command_list([
                 'setenv -e -nv -bs -rt -at db',
                 'printenv -e -n -guid d719b2cb-3d3a-4596-a3bc-dad00e67656f db'])
             assert 'Failed to set EFI variable' in ''.join(output)
             assert 'db:' in ''.join(output)
 
-    def test_efi_var_auth5(self, u_boot_console, efi_boot_env):
+    def test_efi_var_auth5(self, ubman, efi_boot_env):
         """
         Test Case 5 - Uninstall(delete) PK
         """
-        u_boot_console.restart_uboot()
+        ubman.restart_uboot()
         disk_img = efi_boot_env
-        with u_boot_console.log.section('Test Case 5a'):
+        with ubman.log.section('Test Case 5a'):
             # Test Case 5a, Uninstall PK without correct signature
-            output = u_boot_console.run_command_list([
+            output = ubman.run_command_list([
                 'host bind 0 %s' % disk_img,
                 'fatload host 0:1 4000000 PK.auth',
                 'setenv -e -nv -bs -rt -at -i 4000000:$filesize PK',
@@ -257,25 +257,25 @@ class TestEfiAuthVar(object):
             assert 'Failed to set EFI variable' not in ''.join(output)
             assert 'PK:' in ''.join(output)
 
-            output = u_boot_console.run_command_list([
+            output = ubman.run_command_list([
                 'fatload host 0:1 4000000 PK_null.esl',
                 'setenv -e -nv -bs -rt -at -i 4000000:$filesize PK',
                 'printenv -e -n PK'])
             assert 'Failed to set EFI variable' in ''.join(output)
             assert 'PK:' in ''.join(output)
 
-        with u_boot_console.log.section('Test Case 5b'):
+        with ubman.log.section('Test Case 5b'):
             # Test Case 5b, Uninstall PK with correct signature
-            output = u_boot_console.run_command_list([
+            output = ubman.run_command_list([
                 'fatload host 0:1 4000000 PK_null.auth',
                 'setenv -e -nv -bs -rt -at -i 4000000:$filesize PK',
                 'printenv -e -n PK'])
             assert 'Failed to set EFI variable' not in ''.join(output)
             assert '\"PK\" not defined' in ''.join(output)
 
-            output = u_boot_console.run_command(
+            output = ubman.run_command(
                 'printenv -e SecureBoot')
             assert '00000000: 00' in output
-            output = u_boot_console.run_command(
+            output = ubman.run_command(
                 'printenv -e SetupMode')
             assert '00000000: 01' in output
diff --git a/test/py/tests/test_efi_secboot/test_signed.py b/test/py/tests/test_efi_secboot/test_signed.py
index f604138a356..e8aaef7090c 100644
--- a/test/py/tests/test_efi_secboot/test_signed.py
+++ b/test/py/tests/test_efi_secboot/test_signed.py
@@ -18,83 +18,83 @@ import pytest
 @pytest.mark.buildconfigspec('cmd_nvedit_efi')
 @pytest.mark.slow
 class TestEfiSignedImage(object):
-    def test_efi_signed_image_auth1(self, u_boot_console, efi_boot_env):
+    def test_efi_signed_image_auth1(self, ubman, efi_boot_env):
         """
         Test Case 1 - Secure boot is not in force
         """
-        u_boot_console.restart_uboot()
+        ubman.restart_uboot()
         disk_img = efi_boot_env
-        with u_boot_console.log.section('Test Case 1a'):
+        with ubman.log.section('Test Case 1a'):
             # Test Case 1a, run signed image if no PK
-            output = u_boot_console.run_command_list([
+            output = ubman.run_command_list([
                 'host bind 0 %s' % disk_img,
                 'efidebug boot add -b 1 HELLO1 host 0:1 /helloworld.efi.signed -s ""',
                 'efidebug boot order 1',
                 'bootefi bootmgr'])
             assert 'Hello, world!' in ''.join(output)
 
-        with u_boot_console.log.section('Test Case 1b'):
+        with ubman.log.section('Test Case 1b'):
             # Test Case 1b, run unsigned image if no PK
-            output = u_boot_console.run_command_list([
+            output = ubman.run_command_list([
                 'efidebug boot add -b 2 HELLO2 host 0:1 /helloworld.efi -s ""',
                 'efidebug boot order 2',
                 'bootefi bootmgr'])
             assert 'Hello, world!' in ''.join(output)
 
-    def test_efi_signed_image_auth2(self, u_boot_console, efi_boot_env):
+    def test_efi_signed_image_auth2(self, ubman, efi_boot_env):
         """
         Test Case 2 - Secure boot is in force,
                       authenticated by db (TEST_db certificate in db)
         """
-        u_boot_console.restart_uboot()
+        ubman.restart_uboot()
         disk_img = efi_boot_env
-        with u_boot_console.log.section('Test Case 2a'):
+        with ubman.log.section('Test Case 2a'):
             # Test Case 2a, db is not yet installed
-            output = u_boot_console.run_command_list([
+            output = ubman.run_command_list([
                 'host bind 0 %s' % disk_img,
                 'fatload host 0:1 4000000 KEK.auth',
                 'setenv -e -nv -bs -rt -at -i 4000000:$filesize KEK',
                 'fatload host 0:1 4000000 PK.auth',
                 'setenv -e -nv -bs -rt -at -i 4000000:$filesize PK'])
             assert 'Failed to set EFI variable' not in ''.join(output)
-            output = u_boot_console.run_command_list([
+            output = ubman.run_command_list([
                 'efidebug boot add -b 1 HELLO1 host 0:1 /helloworld.efi.signed -s ""',
                 'efidebug boot order 1',
                 'efidebug test bootmgr'])
             assert('\'HELLO1\' failed' in ''.join(output))
             assert('efi_bootmgr_load() returned: 26' in ''.join(output))
-            output = u_boot_console.run_command_list([
+            output = ubman.run_command_list([
                 'efidebug boot add -b 2 HELLO2 host 0:1 /helloworld.efi -s ""',
                 'efidebug boot order 2',
                 'efidebug test bootmgr'])
             assert '\'HELLO2\' failed' in ''.join(output)
             assert 'efi_bootmgr_load() returned: 26' in ''.join(output)
 
-        with u_boot_console.log.section('Test Case 2b'):
+        with ubman.log.section('Test Case 2b'):
             # Test Case 2b, authenticated by db
-            output = u_boot_console.run_command_list([
+            output = ubman.run_command_list([
                 'fatload host 0:1 4000000 db.auth',
                 'setenv -e -nv -bs -rt -at -i 4000000:$filesize db'])
             assert 'Failed to set EFI variable' not in ''.join(output)
-            output = u_boot_console.run_command_list([
+            output = ubman.run_command_list([
                 'efidebug boot order 2',
                 'efidebug test bootmgr'])
             assert '\'HELLO2\' failed' in ''.join(output)
             assert 'efi_bootmgr_load() returned: 26' in ''.join(output)
-            output = u_boot_console.run_command_list([
+            output = ubman.run_command_list([
                 'efidebug boot order 1',
                 'bootefi bootmgr'])
             assert 'Hello, world!' in ''.join(output)
 
-    def test_efi_signed_image_auth3(self, u_boot_console, efi_boot_env):
+    def test_efi_signed_image_auth3(self, ubman, efi_boot_env):
         """
         Test Case 3 - rejected by dbx (TEST_db certificate in dbx)
         """
-        u_boot_console.restart_uboot()
+        ubman.restart_uboot()
         disk_img = efi_boot_env
-        with u_boot_console.log.section('Test Case 3a'):
+        with ubman.log.section('Test Case 3a'):
             # Test Case 3a, rejected by dbx
-            output = u_boot_console.run_command_list([
+            output = ubman.run_command_list([
                 'host bind 0 %s' % disk_img,
                 'fatload host 0:1 4000000 db.auth',
                 'setenv -e -nv -bs -rt -at -i 4000000:$filesize dbx',
@@ -103,34 +103,34 @@ class TestEfiSignedImage(object):
                 'fatload host 0:1 4000000 PK.auth',
                 'setenv -e -nv -bs -rt -at -i 4000000:$filesize PK'])
             assert 'Failed to set EFI variable' not in ''.join(output)
-            output = u_boot_console.run_command_list([
+            output = ubman.run_command_list([
                 'efidebug boot add -b 1 HELLO host 0:1 /helloworld.efi.signed -s ""',
                 'efidebug boot order 1',
                 'efidebug test bootmgr'])
             assert '\'HELLO\' failed' in ''.join(output)
             assert 'efi_bootmgr_load() returned: 26' in ''.join(output)
 
-        with u_boot_console.log.section('Test Case 3b'):
+        with ubman.log.section('Test Case 3b'):
             # Test Case 3b, rejected by dbx even if db allows
-            output = u_boot_console.run_command_list([
+            output = ubman.run_command_list([
                 'fatload host 0:1 4000000 db.auth',
                 'setenv -e -nv -bs -rt -at -i 4000000:$filesize db'])
             assert 'Failed to set EFI variable' not in ''.join(output)
-            output = u_boot_console.run_command_list([
+            output = ubman.run_command_list([
                 'efidebug boot order 1',
                 'efidebug test bootmgr'])
             assert '\'HELLO\' failed' in ''.join(output)
             assert 'efi_bootmgr_load() returned: 26' in ''.join(output)
 
-    def test_efi_signed_image_auth4(self, u_boot_console, efi_boot_env):
+    def test_efi_signed_image_auth4(self, ubman, efi_boot_env):
         """
         Test Case 4 - revoked by dbx (digest of TEST_db certificate in dbx)
         """
-        u_boot_console.restart_uboot()
+        ubman.restart_uboot()
         disk_img = efi_boot_env
-        with u_boot_console.log.section('Test Case 4'):
+        with ubman.log.section('Test Case 4'):
             # Test Case 4, rejected by dbx
-            output = u_boot_console.run_command_list([
+            output = ubman.run_command_list([
                 'host bind 0 %s' % disk_img,
                 'fatload host 0:1 4000000 dbx_hash.auth',
                 'setenv -e -nv -bs -rt -at -i 4000000:$filesize dbx',
@@ -141,25 +141,25 @@ class TestEfiSignedImage(object):
                 'fatload host 0:1 4000000 PK.auth',
                 'setenv -e -nv -bs -rt -at -i 4000000:$filesize PK'])
             assert 'Failed to set EFI variable' not in ''.join(output)
-            output = u_boot_console.run_command_list([
+            output = ubman.run_command_list([
                 'efidebug boot add -b 1 HELLO host 0:1 /helloworld.efi.signed -s ""',
                 'efidebug boot order 1',
                 'efidebug test bootmgr'])
             assert '\'HELLO\' failed' in ''.join(output)
             assert 'efi_bootmgr_load() returned: 26' in ''.join(output)
 
-    def test_efi_signed_image_auth5(self, u_boot_console, efi_boot_env):
+    def test_efi_signed_image_auth5(self, ubman, efi_boot_env):
         """
         Test Case 5 - multiple signatures
                         one signed with TEST_db, and
                         one signed with TEST_db1
         """
-        u_boot_console.restart_uboot()
+        ubman.restart_uboot()
         disk_img = efi_boot_env
-        with u_boot_console.log.section('Test Case 5a'):
+        with ubman.log.section('Test Case 5a'):
             # Test Case 5a, authenticated even if only one of signatures
             # is verified
-            output = u_boot_console.run_command_list([
+            output = ubman.run_command_list([
                 'host bind 0 %s' % disk_img,
                 'fatload host 0:1 4000000 db.auth',
                 'setenv -e -nv -bs -rt -at -i 4000000:$filesize db',
@@ -168,54 +168,54 @@ class TestEfiSignedImage(object):
                 'fatload host 0:1 4000000 PK.auth',
                 'setenv -e -nv -bs -rt -at -i 4000000:$filesize PK'])
             assert 'Failed to set EFI variable' not in ''.join(output)
-            output = u_boot_console.run_command_list([
+            output = ubman.run_command_list([
                 'efidebug boot add -b 1 HELLO host 0:1 /helloworld.efi.signed_2sigs -s ""',
                 'efidebug boot order 1',
                 'efidebug test bootmgr'])
             assert 'Hello, world!' in ''.join(output)
 
-        with u_boot_console.log.section('Test Case 5b'):
+        with ubman.log.section('Test Case 5b'):
             # Test Case 5b, authenticated if both signatures are verified
-            output = u_boot_console.run_command_list([
+            output = ubman.run_command_list([
                 'fatload host 0:1 4000000 db2.auth',
                 'setenv -e -nv -bs -rt -at -a -i 4000000:$filesize db'])
             assert 'Failed to set EFI variable' not in ''.join(output)
-            output = u_boot_console.run_command_list([
+            output = ubman.run_command_list([
                 'efidebug boot order 1',
                 'efidebug test bootmgr'])
             assert 'Hello, world!' in ''.join(output)
 
-        with u_boot_console.log.section('Test Case 5c'):
+        with ubman.log.section('Test Case 5c'):
             # Test Case 5c, rejected if one of signatures (digest of
             # certificate) is revoked
-            output = u_boot_console.run_command_list([
+            output = ubman.run_command_list([
                 'fatload host 0:1 4000000 dbx_hash.auth',
                 'setenv -e -nv -bs -rt -at -i 4000000:$filesize dbx'])
             assert 'Failed to set EFI variable' not in ''.join(output)
-            output = u_boot_console.run_command_list([
+            output = ubman.run_command_list([
                 'efidebug boot order 1',
                 'efidebug test bootmgr'])
             assert '\'HELLO\' failed' in ''.join(output)
             assert 'efi_bootmgr_load() returned: 26' in ''.join(output)
 
-        with u_boot_console.log.section('Test Case 5d'):
+        with ubman.log.section('Test Case 5d'):
             # Test Case 5d, rejected if both of signatures are revoked
-            output = u_boot_console.run_command_list([
+            output = ubman.run_command_list([
                 'fatload host 0:1 4000000 dbx_hash2.auth',
                 'setenv -e -nv -bs -rt -at -a -i 4000000:$filesize dbx'])
             assert 'Failed to set EFI variable' not in ''.join(output)
-            output = u_boot_console.run_command_list([
+            output = ubman.run_command_list([
                 'efidebug boot order 1',
                 'efidebug test bootmgr'])
             assert '\'HELLO\' failed' in ''.join(output)
             assert 'efi_bootmgr_load() returned: 26' in ''.join(output)
 
         # Try rejection in reverse order.
-        u_boot_console.restart_uboot()
-        with u_boot_console.log.section('Test Case 5e'):
+        ubman.restart_uboot()
+        with ubman.log.section('Test Case 5e'):
             # Test Case 5e, authenticated even if only one of signatures
             # is verified. Same as before but reject dbx_hash1.auth only
-            output = u_boot_console.run_command_list([
+            output = ubman.run_command_list([
                 'host bind 0 %s' % disk_img,
                 'fatload host 0:1 4000000 db.auth',
                 'setenv -e -nv -bs -rt -at -i 4000000:$filesize db',
@@ -228,22 +228,22 @@ class TestEfiSignedImage(object):
                 'fatload host 0:1 4000000 dbx_hash1.auth',
                 'setenv -e -nv -bs -rt -at -i 4000000:$filesize dbx'])
             assert 'Failed to set EFI variable' not in ''.join(output)
-            output = u_boot_console.run_command_list([
+            output = ubman.run_command_list([
                 'efidebug boot add -b 1 HELLO host 0:1 /helloworld.efi.signed_2sigs -s ""',
                 'efidebug boot order 1',
                 'efidebug test bootmgr'])
             assert '\'HELLO\' failed' in ''.join(output)
             assert 'efi_bootmgr_load() returned: 26' in ''.join(output)
 
-    def test_efi_signed_image_auth6(self, u_boot_console, efi_boot_env):
+    def test_efi_signed_image_auth6(self, ubman, efi_boot_env):
         """
         Test Case 6 - using digest of signed image in database
         """
-        u_boot_console.restart_uboot()
+        ubman.restart_uboot()
         disk_img = efi_boot_env
-        with u_boot_console.log.section('Test Case 6a'):
+        with ubman.log.section('Test Case 6a'):
             # Test Case 6a, verified by image's digest in db
-            output = u_boot_console.run_command_list([
+            output = ubman.run_command_list([
                 'host bind 0 %s' % disk_img,
                 'fatload host 0:1 4000000 db_hello_signed.auth',
                 'setenv -e -nv -bs -rt -at -i 4000000:$filesize db',
@@ -252,47 +252,47 @@ class TestEfiSignedImage(object):
                 'fatload host 0:1 4000000 PK.auth',
                 'setenv -e -nv -bs -rt -at -i 4000000:$filesize PK'])
             assert 'Failed to set EFI variable' not in ''.join(output)
-            output = u_boot_console.run_command_list([
+            output = ubman.run_command_list([
                 'efidebug boot add -b 1 HELLO host 0:1 /helloworld.efi.signed -s ""',
                 'efidebug boot order 1',
                 'bootefi bootmgr'])
             assert 'Hello, world!' in ''.join(output)
 
-        with u_boot_console.log.section('Test Case 6b'):
+        with ubman.log.section('Test Case 6b'):
             # Test Case 6b, rejected by TEST_db certificate in dbx
-            output = u_boot_console.run_command_list([
+            output = ubman.run_command_list([
                 'fatload host 0:1 4000000 dbx_db.auth',
                 'setenv -e -nv -bs -rt -at -i 4000000:$filesize dbx'])
             assert 'Failed to set EFI variable' not in ''.join(output)
-            output = u_boot_console.run_command_list([
+            output = ubman.run_command_list([
                 'efidebug boot order 1',
                 'efidebug test bootmgr'])
             assert '\'HELLO\' failed' in ''.join(output)
             assert 'efi_bootmgr_load() returned: 26' in ''.join(output)
 
-        with u_boot_console.log.section('Test Case 6c'):
+        with ubman.log.section('Test Case 6c'):
             # Test Case 6c, rejected by image's digest in dbx
-            output = u_boot_console.run_command_list([
+            output = ubman.run_command_list([
                 'fatload host 0:1 4000000 db.auth',
                 'setenv -e -nv -bs -rt -at -i 4000000:$filesize db',
                 'fatload host 0:1 4000000 dbx_hello_signed.auth',
                 'setenv -e -nv -bs -rt -at -i 4000000:$filesize dbx'])
             assert 'Failed to set EFI variable' not in ''.join(output)
-            output = u_boot_console.run_command_list([
+            output = ubman.run_command_list([
                 'efidebug boot order 1',
                 'efidebug test bootmgr'])
             assert '\'HELLO\' failed' in ''.join(output)
             assert 'efi_bootmgr_load() returned: 26' in ''.join(output)
 
-    def test_efi_signed_image_auth7(self, u_boot_console, efi_boot_env):
+    def test_efi_signed_image_auth7(self, ubman, efi_boot_env):
         """
         Test Case 7 - Reject images based on the sha384/512 of their x509 cert
         """
         # sha384 of an x509 cert in dbx
-        u_boot_console.restart_uboot()
+        ubman.restart_uboot()
         disk_img = efi_boot_env
-        with u_boot_console.log.section('Test Case 7a'):
-            output = u_boot_console.run_command_list([
+        with ubman.log.section('Test Case 7a'):
+            output = ubman.run_command_list([
                 'host bind 0 %s' % disk_img,
                 'fatload host 0:1 4000000 db.auth',
                 'setenv -e -nv -bs -rt -at -i 4000000:$filesize db',
@@ -305,7 +305,7 @@ class TestEfiSignedImage(object):
                 'fatload host 0:1 4000000 dbx_hash384.auth',
                 'setenv -e -nv -bs -rt -at -i 4000000:$filesize dbx'])
             assert 'Failed to set EFI variable' not in ''.join(output)
-            output = u_boot_console.run_command_list([
+            output = ubman.run_command_list([
                 'efidebug boot add -b 1 HELLO host 0:1 /helloworld.efi.signed_2sigs -s ""',
                 'efidebug boot order 1',
                 'efidebug test bootmgr'])
@@ -313,9 +313,9 @@ class TestEfiSignedImage(object):
             assert 'efi_bootmgr_load() returned: 26' in ''.join(output)
 
         # sha512 of an x509 cert in dbx
-        u_boot_console.restart_uboot()
-        with u_boot_console.log.section('Test Case 7b'):
-            output = u_boot_console.run_command_list([
+        ubman.restart_uboot()
+        with ubman.log.section('Test Case 7b'):
+            output = ubman.run_command_list([
                 'host bind 0 %s' % disk_img,
                 'fatload host 0:1 4000000 db.auth',
                 'setenv -e -nv -bs -rt -at -i 4000000:$filesize db',
@@ -328,34 +328,34 @@ class TestEfiSignedImage(object):
                 'fatload host 0:1 4000000 dbx_hash512.auth',
                 'setenv -e -nv -bs -rt -at -i 4000000:$filesize dbx'])
             assert 'Failed to set EFI variable' not in ''.join(output)
-            output = u_boot_console.run_command_list([
+            output = ubman.run_command_list([
                 'efidebug boot add -b 1 HELLO host 0:1 /helloworld.efi.signed_2sigs -s ""',
                 'efidebug boot order 1',
                 'efidebug test bootmgr'])
             assert '\'HELLO\' failed' in ''.join(output)
             assert 'efi_bootmgr_load() returned: 26' in ''.join(output)
 
-    def test_efi_signed_image_auth8(self, u_boot_console, efi_boot_env):
+    def test_efi_signed_image_auth8(self, ubman, efi_boot_env):
         """
         Test Case 8 - Secure boot is in force,
                       Same as Test Case 2 but the image binary to be loaded
                       was willfully modified (forged)
                       Must be rejected.
         """
-        u_boot_console.restart_uboot()
+        ubman.restart_uboot()
         disk_img = efi_boot_env
-        with u_boot_console.log.section('Test Case 8a'):
+        with ubman.log.section('Test Case 8a'):
             # Test Case 8a, Secure boot is not yet forced
-            output = u_boot_console.run_command_list([
+            output = ubman.run_command_list([
                 'host bind 0 %s' % disk_img,
                 'efidebug boot add -b 1 HELLO1 host 0:1 /helloworld_forged.efi.signed -s ""',
                 'efidebug boot order 1',
                 'efidebug test bootmgr'])
             assert('hELLO, world!' in ''.join(output))
 
-        with u_boot_console.log.section('Test Case 8b'):
+        with ubman.log.section('Test Case 8b'):
             # Test Case 8b, Install signature database and verify the image
-            output = u_boot_console.run_command_list([
+            output = ubman.run_command_list([
                 'fatload host 0:1 4000000 db.auth',
                 'setenv -e -nv -bs -rt -at -i 4000000:$filesize db',
                 'fatload host 0:1 4000000 KEK.auth',
@@ -363,7 +363,7 @@ class TestEfiSignedImage(object):
                 'fatload host 0:1 4000000 PK.auth',
                 'setenv -e -nv -bs -rt -at -i 4000000:$filesize PK'])
             assert 'Failed to set EFI variable' not in ''.join(output)
-            output = u_boot_console.run_command_list([
+            output = ubman.run_command_list([
                 'efidebug boot order 1',
                 'efidebug test bootmgr'])
             assert(not 'hELLO, world!' in ''.join(output))
diff --git a/test/py/tests/test_efi_secboot/test_signed_intca.py b/test/py/tests/test_efi_secboot/test_signed_intca.py
index cf906205bc2..58f7be03b8b 100644
--- a/test/py/tests/test_efi_secboot/test_signed_intca.py
+++ b/test/py/tests/test_efi_secboot/test_signed_intca.py
@@ -20,15 +20,15 @@ import pytest
 @pytest.mark.buildconfigspec('cmd_nvedit_efi')
 @pytest.mark.slow
 class TestEfiSignedImageIntca(object):
-    def test_efi_signed_image_intca1(self, u_boot_console, efi_boot_env_intca):
+    def test_efi_signed_image_intca1(self, ubman, efi_boot_env_intca):
         """
         Test Case 1 - authenticated by root CA in db
         """
-        u_boot_console.restart_uboot()
+        ubman.restart_uboot()
         disk_img = efi_boot_env_intca
-        with u_boot_console.log.section('Test Case 1a'):
+        with ubman.log.section('Test Case 1a'):
             # Test Case 1a, with no Int CA and not authenticated by root CA
-            output = u_boot_console.run_command_list([
+            output = ubman.run_command_list([
                 'host bind 0 %s' % disk_img,
                 'fatload host 0:1 4000000 db_c.auth',
                 'setenv -e -nv -bs -rt -at -i 4000000:$filesize db',
@@ -38,30 +38,30 @@ class TestEfiSignedImageIntca(object):
                 'setenv -e -nv -bs -rt -at -i 4000000:$filesize PK'])
             assert 'Failed to set EFI variable' not in ''.join(output)
 
-            output = u_boot_console.run_command_list([
+            output = ubman.run_command_list([
                 'efidebug boot add -b 1 HELLO_a host 0:1 /helloworld.efi.signed_a -s ""',
                 'efidebug boot order 1',
                 'efidebug test bootmgr'])
             assert '\'HELLO_a\' failed' in ''.join(output)
             assert 'efi_bootmgr_load() returned: 26' in ''.join(output)
 
-        with u_boot_console.log.section('Test Case 1b'):
+        with ubman.log.section('Test Case 1b'):
             # Test Case 1b, signed and authenticated by root CA
-            output = u_boot_console.run_command_list([
+            output = ubman.run_command_list([
                 'efidebug boot add -b 2 HELLO_ab host 0:1 /helloworld.efi.signed_ab -s ""',
                 'efidebug boot order 2',
                 'bootefi bootmgr'])
             assert 'Hello, world!' in ''.join(output)
 
-    def test_efi_signed_image_intca2(self, u_boot_console, efi_boot_env_intca):
+    def test_efi_signed_image_intca2(self, ubman, efi_boot_env_intca):
         """
         Test Case 2 - authenticated by root CA in db
         """
-        u_boot_console.restart_uboot()
+        ubman.restart_uboot()
         disk_img = efi_boot_env_intca
-        with u_boot_console.log.section('Test Case 2a'):
+        with ubman.log.section('Test Case 2a'):
             # Test Case 2a, unsigned and not authenticated by root CA
-            output = u_boot_console.run_command_list([
+            output = ubman.run_command_list([
                 'host bind 0 %s' % disk_img,
                 'fatload host 0:1 4000000 KEK.auth',
                 'setenv -e -nv -bs -rt -at -i 4000000:$filesize KEK',
@@ -69,16 +69,16 @@ class TestEfiSignedImageIntca(object):
                 'setenv -e -nv -bs -rt -at -i 4000000:$filesize PK'])
             assert 'Failed to set EFI variable' not in ''.join(output)
 
-            output = u_boot_console.run_command_list([
+            output = ubman.run_command_list([
                 'efidebug boot add -b 1 HELLO_abc host 0:1 /helloworld.efi.signed_abc -s ""',
                 'efidebug boot order 1',
                 'efidebug test bootmgr'])
             assert '\'HELLO_abc\' failed' in ''.join(output)
             assert 'efi_bootmgr_load() returned: 26' in ''.join(output)
 
-        with u_boot_console.log.section('Test Case 2b'):
+        with ubman.log.section('Test Case 2b'):
             # Test Case 2b, signed and authenticated by root CA
-            output = u_boot_console.run_command_list([
+            output = ubman.run_command_list([
                 'fatload host 0:1 4000000 db_b.auth',
                 'setenv -e -nv -bs -rt -at -i 4000000:$filesize db',
                 'efidebug boot order 1',
@@ -86,24 +86,24 @@ class TestEfiSignedImageIntca(object):
             assert '\'HELLO_abc\' failed' in ''.join(output)
             assert 'efi_bootmgr_load() returned: 26' in ''.join(output)
 
-        with u_boot_console.log.section('Test Case 2c'):
+        with ubman.log.section('Test Case 2c'):
             # Test Case 2c, signed and authenticated by root CA
-            output = u_boot_console.run_command_list([
+            output = ubman.run_command_list([
                 'fatload host 0:1 4000000 db_c.auth',
                 'setenv -e -nv -bs -rt -at -i 4000000:$filesize db',
                 'efidebug boot order 1',
                 'efidebug test bootmgr'])
             assert 'Hello, world!' in ''.join(output)
 
-    def test_efi_signed_image_intca3(self, u_boot_console, efi_boot_env_intca):
+    def test_efi_signed_image_intca3(self, ubman, efi_boot_env_intca):
         """
         Test Case 3 - revoked by dbx
         """
-        u_boot_console.restart_uboot()
+        ubman.restart_uboot()
         disk_img = efi_boot_env_intca
-        with u_boot_console.log.section('Test Case 3a'):
+        with ubman.log.section('Test Case 3a'):
             # Test Case 3a, revoked by int CA in dbx
-            output = u_boot_console.run_command_list([
+            output = ubman.run_command_list([
                 'host bind 0 %s' % disk_img,
                 'fatload host 0:1 4000000 dbx_b.auth',
                 'setenv -e -nv -bs -rt -at -i 4000000:$filesize dbx',
@@ -115,7 +115,7 @@ class TestEfiSignedImageIntca(object):
                 'setenv -e -nv -bs -rt -at -i 4000000:$filesize PK'])
             assert 'Failed to set EFI variable' not in ''.join(output)
 
-            output = u_boot_console.run_command_list([
+            output = ubman.run_command_list([
                 'efidebug boot add -b 1 HELLO_abc host 0:1 /helloworld.efi.signed_abc -s ""',
                 'efidebug boot order 1',
                 'efidebug test bootmgr'])
@@ -124,9 +124,9 @@ class TestEfiSignedImageIntca(object):
             # assert '\'HELLO_abc\' failed' in ''.join(output)
             # assert 'efi_bootmgr_load() returned: 26' in ''.join(output)
 
-        with u_boot_console.log.section('Test Case 3b'):
+        with ubman.log.section('Test Case 3b'):
             # Test Case 3b, revoked by root CA in dbx
-            output = u_boot_console.run_command_list([
+            output = ubman.run_command_list([
                 'fatload host 0:1 4000000 dbx_c.auth',
                 'setenv -e -nv -bs -rt -at -i 4000000:$filesize dbx',
                 'efidebug boot order 1',
diff --git a/test/py/tests/test_efi_secboot/test_unsigned.py b/test/py/tests/test_efi_secboot/test_unsigned.py
index b4320ae4054..bd6e1b2dadd 100644
--- a/test/py/tests/test_efi_secboot/test_unsigned.py
+++ b/test/py/tests/test_efi_secboot/test_unsigned.py
@@ -18,15 +18,15 @@ import pytest
 @pytest.mark.buildconfigspec('cmd_nvedit_efi')
 @pytest.mark.slow
 class TestEfiUnsignedImage(object):
-    def test_efi_unsigned_image_auth1(self, u_boot_console, efi_boot_env):
+    def test_efi_unsigned_image_auth1(self, ubman, efi_boot_env):
         """
         Test Case 1 - rejected when not digest in db or dbx
         """
-        u_boot_console.restart_uboot()
+        ubman.restart_uboot()
         disk_img = efi_boot_env
-        with u_boot_console.log.section('Test Case 1'):
+        with ubman.log.section('Test Case 1'):
             # Test Case 1
-            output = u_boot_console.run_command_list([
+            output = ubman.run_command_list([
                 'host bind 0 %s' % disk_img,
                 'fatload host 0:1 4000000 KEK.auth',
                 'setenv -e -nv -bs -rt -at -i 4000000:$filesize KEK',
@@ -34,26 +34,26 @@ class TestEfiUnsignedImage(object):
                 'setenv -e -nv -bs -rt -at -i 4000000:$filesize PK'])
             assert 'Failed to set EFI variable' not in ''.join(output)
 
-            output = u_boot_console.run_command_list([
+            output = ubman.run_command_list([
                 'efidebug boot add -b 1 HELLO host 0:1 /helloworld.efi -s ""',
                 'efidebug boot order 1',
                 'bootefi bootmgr'])
             assert '\'HELLO\' failed' in ''.join(output)
-            output = u_boot_console.run_command_list([
+            output = ubman.run_command_list([
                 'efidebug boot order 1',
                 'efidebug test bootmgr'])
             assert 'efi_bootmgr_load() returned: 26' in ''.join(output)
             assert 'Hello, world!' not in ''.join(output)
 
-    def test_efi_unsigned_image_auth2(self, u_boot_console, efi_boot_env):
+    def test_efi_unsigned_image_auth2(self, ubman, efi_boot_env):
         """
         Test Case 2 - authenticated by digest in db
         """
-        u_boot_console.restart_uboot()
+        ubman.restart_uboot()
         disk_img = efi_boot_env
-        with u_boot_console.log.section('Test Case 2'):
+        with ubman.log.section('Test Case 2'):
             # Test Case 2
-            output = u_boot_console.run_command_list([
+            output = ubman.run_command_list([
                 'host bind 0 %s' % disk_img,
                 'fatload host 0:1 4000000 db_hello.auth',
                 'setenv -e -nv -bs -rt -at -i 4000000:$filesize db',
@@ -63,21 +63,21 @@ class TestEfiUnsignedImage(object):
                 'setenv -e -nv -bs -rt -at -i 4000000:$filesize PK'])
             assert 'Failed to set EFI variable' not in ''.join(output)
 
-            output = u_boot_console.run_command_list([
+            output = ubman.run_command_list([
                 'efidebug boot add -b 1 HELLO host 0:1 /helloworld.efi -s ""',
                 'efidebug boot order 1',
                 'bootefi bootmgr'])
             assert 'Hello, world!' in ''.join(output)
 
-    def test_efi_unsigned_image_auth3(self, u_boot_console, efi_boot_env):
+    def test_efi_unsigned_image_auth3(self, ubman, efi_boot_env):
         """
         Test Case 3 - rejected by digest in dbx
         """
-        u_boot_console.restart_uboot()
+        ubman.restart_uboot()
         disk_img = efi_boot_env
-        with u_boot_console.log.section('Test Case 3a'):
+        with ubman.log.section('Test Case 3a'):
             # Test Case 3a, rejected by dbx
-            output = u_boot_console.run_command_list([
+            output = ubman.run_command_list([
                 'host bind 0 %s' % disk_img,
                 'fatload host 0:1 4000000 db_hello.auth',
                 'setenv -e -nv -bs -rt -at -i 4000000:$filesize dbx',
@@ -87,30 +87,30 @@ class TestEfiUnsignedImage(object):
                 'setenv -e -nv -bs -rt -at -i 4000000:$filesize PK'])
             assert 'Failed to set EFI variable' not in ''.join(output)
 
-            output = u_boot_console.run_command_list([
+            output = ubman.run_command_list([
                 'efidebug boot add -b 1 HELLO host 0:1 /helloworld.efi -s ""',
                 'efidebug boot order 1',
                 'bootefi bootmgr'])
             assert '\'HELLO\' failed' in ''.join(output)
-            output = u_boot_console.run_command_list([
+            output = ubman.run_command_list([
                 'efidebug boot order 1',
                 'efidebug test bootmgr'])
             assert 'efi_bootmgr_load() returned: 26' in ''.join(output)
             assert 'Hello, world!' not in ''.join(output)
 
-        with u_boot_console.log.section('Test Case 3b'):
+        with ubman.log.section('Test Case 3b'):
             # Test Case 3b, rejected by dbx even if db allows
-            output = u_boot_console.run_command_list([
+            output = ubman.run_command_list([
                 'fatload host 0:1 4000000 db_hello.auth',
                 'setenv -e -nv -bs -rt -at -i 4000000:$filesize db'])
             assert 'Failed to set EFI variable' not in ''.join(output)
 
-            output = u_boot_console.run_command_list([
+            output = ubman.run_command_list([
                 'efidebug boot add -b 1 HELLO host 0:1 /helloworld.efi -s ""',
                 'efidebug boot order 1',
                 'bootefi bootmgr'])
             assert '\'HELLO\' failed' in ''.join(output)
-            output = u_boot_console.run_command_list([
+            output = ubman.run_command_list([
                 'efidebug boot order 1',
                 'efidebug test bootmgr'])
             assert 'efi_bootmgr_load() returned: 26' in ''.join(output)
diff --git a/test/py/tests/test_efi_selftest.py b/test/py/tests/test_efi_selftest.py
index 310d8ed294a..12cbe5caa9b 100644
--- a/test/py/tests/test_efi_selftest.py
+++ b/test/py/tests/test_efi_selftest.py
@@ -7,191 +7,191 @@
 import pytest
 
 @pytest.mark.buildconfigspec('cmd_bootefi_selftest')
-def test_efi_selftest_base(u_boot_console):
+def test_efi_selftest_base(ubman):
     """Run UEFI unit tests
 
-    u_boot_console -- U-Boot console
+    ubman -- U-Boot console
 
     This function executes all selftests that are not marked as on request.
     """
-    u_boot_console.run_command(cmd='setenv efi_selftest')
-    u_boot_console.run_command(cmd='bootefi selftest', wait_for_prompt=False)
-    if u_boot_console.p.expect(['Summary: 0 failures', 'Press any key']):
+    ubman.run_command(cmd='setenv efi_selftest')
+    ubman.run_command(cmd='bootefi selftest', wait_for_prompt=False)
+    if ubman.p.expect(['Summary: 0 failures', 'Press any key']):
         raise Exception('Failures occurred during the EFI selftest')
-    u_boot_console.restart_uboot()
+    ubman.restart_uboot()
 
 @pytest.mark.buildconfigspec('cmd_bootefi_selftest')
 @pytest.mark.buildconfigspec('hush_parser')
 @pytest.mark.buildconfigspec('of_control')
 @pytest.mark.notbuildconfigspec('generate_acpi_table')
-def test_efi_selftest_device_tree(u_boot_console):
+def test_efi_selftest_device_tree(ubman):
     """Test the device tree support in the UEFI sub-system
 
-    u_boot_console -- U-Boot console
+    ubman -- U-Boot console
 
     This test executes the UEFI unit test by calling 'bootefi selftest'.
     """
-    u_boot_console.run_command(cmd='setenv efi_selftest list')
-    output = u_boot_console.run_command('bootefi selftest')
+    ubman.run_command(cmd='setenv efi_selftest list')
+    output = ubman.run_command('bootefi selftest')
     assert '\'device tree\'' in output
-    u_boot_console.run_command(cmd='setenv efi_selftest device tree')
+    ubman.run_command(cmd='setenv efi_selftest device tree')
     # Set serial# if it is not already set.
-    u_boot_console.run_command(cmd='setenv efi_test "${serial#}x"')
-    u_boot_console.run_command(cmd='test "${efi_test}" = x && setenv serial# 0')
-    u_boot_console.run_command(cmd='bootefi selftest ${fdtcontroladdr}', wait_for_prompt=False)
-    if u_boot_console.p.expect(['serial-number:', 'U-Boot']):
+    ubman.run_command(cmd='setenv efi_test "${serial#}x"')
+    ubman.run_command(cmd='test "${efi_test}" = x && setenv serial# 0')
+    ubman.run_command(cmd='bootefi selftest ${fdtcontroladdr}', wait_for_prompt=False)
+    if ubman.p.expect(['serial-number:', 'U-Boot']):
         raise Exception('serial-number missing in device tree')
-    u_boot_console.restart_uboot()
+    ubman.restart_uboot()
 
 @pytest.mark.buildconfigspec('cmd_bootefi_selftest')
-def test_efi_selftest_watchdog_reboot(u_boot_console):
+def test_efi_selftest_watchdog_reboot(ubman):
     """Test the watchdog timer
 
-    u_boot_console -- U-Boot console
+    ubman -- U-Boot console
 
     This function executes the 'watchdog reboot' unit test.
     """
-    u_boot_console.run_command(cmd='setenv efi_selftest list')
-    output = u_boot_console.run_command('bootefi selftest')
+    ubman.run_command(cmd='setenv efi_selftest list')
+    output = ubman.run_command('bootefi selftest')
     assert '\'watchdog reboot\'' in output
-    u_boot_console.run_command(cmd='setenv efi_selftest watchdog reboot')
-    u_boot_console.run_command(cmd='bootefi selftest', wait_for_prompt=False)
-    if u_boot_console.p.expect(['resetting', 'U-Boot']):
+    ubman.run_command(cmd='setenv efi_selftest watchdog reboot')
+    ubman.run_command(cmd='bootefi selftest', wait_for_prompt=False)
+    if ubman.p.expect(['resetting', 'U-Boot']):
         raise Exception('Reset failed in \'watchdog reboot\' test')
-    u_boot_console.run_command(cmd='', send_nl=False, wait_for_reboot=True)
+    ubman.run_command(cmd='', send_nl=False, wait_for_reboot=True)
 
 @pytest.mark.buildconfigspec('cmd_bootefi_selftest')
-def test_efi_selftest_text_input(u_boot_console):
+def test_efi_selftest_text_input(ubman):
     """Test the EFI_SIMPLE_TEXT_INPUT_PROTOCOL
 
-    u_boot_console -- U-Boot console
+    ubman -- U-Boot console
 
     This function calls the text input EFI selftest.
     """
-    u_boot_console.run_command(cmd='setenv efi_selftest text input')
-    u_boot_console.run_command(cmd='bootefi selftest', wait_for_prompt=False)
-    if u_boot_console.p.expect([r'To terminate type \'x\'']):
+    ubman.run_command(cmd='setenv efi_selftest text input')
+    ubman.run_command(cmd='bootefi selftest', wait_for_prompt=False)
+    if ubman.p.expect([r'To terminate type \'x\'']):
         raise Exception('No prompt for \'text input\' test')
-    u_boot_console.drain_console()
+    ubman.drain_console()
     # EOT
-    u_boot_console.run_command(cmd=chr(4), wait_for_echo=False,
+    ubman.run_command(cmd=chr(4), wait_for_echo=False,
                                send_nl=False, wait_for_prompt=False)
-    if u_boot_console.p.expect([r'Unicode char 4 \(unknown\), scan code 0 \(Null\)']):
+    if ubman.p.expect([r'Unicode char 4 \(unknown\), scan code 0 \(Null\)']):
         raise Exception('EOT failed in \'text input\' test')
-    u_boot_console.drain_console()
+    ubman.drain_console()
     # BS
-    u_boot_console.run_command(cmd=chr(8), wait_for_echo=False,
+    ubman.run_command(cmd=chr(8), wait_for_echo=False,
                                send_nl=False, wait_for_prompt=False)
-    if u_boot_console.p.expect([r'Unicode char 8 \(BS\), scan code 0 \(Null\)']):
+    if ubman.p.expect([r'Unicode char 8 \(BS\), scan code 0 \(Null\)']):
         raise Exception('BS failed in \'text input\' test')
-    u_boot_console.drain_console()
+    ubman.drain_console()
     # TAB
-    u_boot_console.run_command(cmd=chr(9), wait_for_echo=False,
+    ubman.run_command(cmd=chr(9), wait_for_echo=False,
                                send_nl=False, wait_for_prompt=False)
-    if u_boot_console.p.expect([r'Unicode char 9 \(TAB\), scan code 0 \(Null\)']):
+    if ubman.p.expect([r'Unicode char 9 \(TAB\), scan code 0 \(Null\)']):
         raise Exception('BS failed in \'text input\' test')
-    u_boot_console.drain_console()
+    ubman.drain_console()
     # a
-    u_boot_console.run_command(cmd='a', wait_for_echo=False, send_nl=False,
+    ubman.run_command(cmd='a', wait_for_echo=False, send_nl=False,
                                wait_for_prompt=False)
-    if u_boot_console.p.expect([r'Unicode char 97 \(\'a\'\), scan code 0 \(Null\)']):
+    if ubman.p.expect([r'Unicode char 97 \(\'a\'\), scan code 0 \(Null\)']):
         raise Exception('\'a\' failed in \'text input\' test')
-    u_boot_console.drain_console()
+    ubman.drain_console()
     # UP escape sequence
-    u_boot_console.run_command(cmd=chr(27) + '[A', wait_for_echo=False,
+    ubman.run_command(cmd=chr(27) + '[A', wait_for_echo=False,
                                send_nl=False, wait_for_prompt=False)
-    if u_boot_console.p.expect([r'Unicode char 0 \(Null\), scan code 1 \(Up\)']):
+    if ubman.p.expect([r'Unicode char 0 \(Null\), scan code 1 \(Up\)']):
         raise Exception('UP failed in \'text input\' test')
-    u_boot_console.drain_console()
+    ubman.drain_console()
     # Euro sign
-    u_boot_console.run_command(cmd=b'\xe2\x82\xac'.decode(), wait_for_echo=False,
+    ubman.run_command(cmd=b'\xe2\x82\xac'.decode(), wait_for_echo=False,
                                send_nl=False, wait_for_prompt=False)
-    if u_boot_console.p.expect([r'Unicode char 8364 \(\'']):
+    if ubman.p.expect([r'Unicode char 8364 \(\'']):
         raise Exception('Euro sign failed in \'text input\' test')
-    u_boot_console.drain_console()
-    u_boot_console.run_command(cmd='x', wait_for_echo=False, send_nl=False,
+    ubman.drain_console()
+    ubman.run_command(cmd='x', wait_for_echo=False, send_nl=False,
                                wait_for_prompt=False)
-    if u_boot_console.p.expect(['Summary: 0 failures', 'Press any key']):
+    if ubman.p.expect(['Summary: 0 failures', 'Press any key']):
         raise Exception('Failures occurred during the EFI selftest')
-    u_boot_console.restart_uboot()
+    ubman.restart_uboot()
 
 @pytest.mark.buildconfigspec('cmd_bootefi_selftest')
-def test_efi_selftest_text_input_ex(u_boot_console):
+def test_efi_selftest_text_input_ex(ubman):
     """Test the EFI_SIMPLE_TEXT_INPUT_EX_PROTOCOL
 
-    u_boot_console -- U-Boot console
+    ubman -- U-Boot console
 
     This function calls the extended text input EFI selftest.
     """
-    u_boot_console.run_command(cmd='setenv efi_selftest extended text input')
-    u_boot_console.run_command(cmd='bootefi selftest', wait_for_prompt=False)
-    if u_boot_console.p.expect([r'To terminate type \'CTRL\+x\'']):
+    ubman.run_command(cmd='setenv efi_selftest extended text input')
+    ubman.run_command(cmd='bootefi selftest', wait_for_prompt=False)
+    if ubman.p.expect([r'To terminate type \'CTRL\+x\'']):
         raise Exception('No prompt for \'text input\' test')
-    u_boot_console.drain_console()
+    ubman.drain_console()
     # EOT
-    u_boot_console.run_command(cmd=chr(4), wait_for_echo=False,
+    ubman.run_command(cmd=chr(4), wait_for_echo=False,
                                send_nl=False, wait_for_prompt=False)
-    if u_boot_console.p.expect([r'Unicode char 100 \(\'d\'\), scan code 0 \(CTRL\+Null\)']):
+    if ubman.p.expect([r'Unicode char 100 \(\'d\'\), scan code 0 \(CTRL\+Null\)']):
         raise Exception('EOT failed in \'text input\' test')
-    u_boot_console.drain_console()
+    ubman.drain_console()
     # BS
-    u_boot_console.run_command(cmd=chr(8), wait_for_echo=False,
+    ubman.run_command(cmd=chr(8), wait_for_echo=False,
                                send_nl=False, wait_for_prompt=False)
-    if u_boot_console.p.expect([r'Unicode char 8 \(BS\), scan code 0 \(\+Null\)']):
+    if ubman.p.expect([r'Unicode char 8 \(BS\), scan code 0 \(\+Null\)']):
         raise Exception('BS failed in \'text input\' test')
-    u_boot_console.drain_console()
+    ubman.drain_console()
     # TAB
-    u_boot_console.run_command(cmd=chr(9), wait_for_echo=False,
+    ubman.run_command(cmd=chr(9), wait_for_echo=False,
                                send_nl=False, wait_for_prompt=False)
-    if u_boot_console.p.expect([r'Unicode char 9 \(TAB\), scan code 0 \(\+Null\)']):
+    if ubman.p.expect([r'Unicode char 9 \(TAB\), scan code 0 \(\+Null\)']):
         raise Exception('TAB failed in \'text input\' test')
-    u_boot_console.drain_console()
+    ubman.drain_console()
     # a
-    u_boot_console.run_command(cmd='a', wait_for_echo=False, send_nl=False,
+    ubman.run_command(cmd='a', wait_for_echo=False, send_nl=False,
                                wait_for_prompt=False)
-    if u_boot_console.p.expect([r'Unicode char 97 \(\'a\'\), scan code 0 \(Null\)']):
+    if ubman.p.expect([r'Unicode char 97 \(\'a\'\), scan code 0 \(Null\)']):
         raise Exception('\'a\' failed in \'text input\' test')
-    u_boot_console.drain_console()
+    ubman.drain_console()
     # UP escape sequence
-    u_boot_console.run_command(cmd=chr(27) + '[A', wait_for_echo=False,
+    ubman.run_command(cmd=chr(27) + '[A', wait_for_echo=False,
                                send_nl=False, wait_for_prompt=False)
-    if u_boot_console.p.expect([r'Unicode char 0 \(Null\), scan code 1 \(\+Up\)']):
+    if ubman.p.expect([r'Unicode char 0 \(Null\), scan code 1 \(\+Up\)']):
         raise Exception('UP failed in \'text input\' test')
-    u_boot_console.drain_console()
+    ubman.drain_console()
     # Euro sign
-    u_boot_console.run_command(cmd=b'\xe2\x82\xac'.decode(), wait_for_echo=False,
+    ubman.run_command(cmd=b'\xe2\x82\xac'.decode(), wait_for_echo=False,
                                send_nl=False, wait_for_prompt=False)
-    if u_boot_console.p.expect([r'Unicode char 8364 \(\'']):
+    if ubman.p.expect([r'Unicode char 8364 \(\'']):
         raise Exception('Euro sign failed in \'text input\' test')
-    u_boot_console.drain_console()
+    ubman.drain_console()
     # SHIFT+ALT+FN 5
-    u_boot_console.run_command(cmd=b'\x1b\x5b\x31\x35\x3b\x34\x7e'.decode(),
+    ubman.run_command(cmd=b'\x1b\x5b\x31\x35\x3b\x34\x7e'.decode(),
                                wait_for_echo=False, send_nl=False,
                                wait_for_prompt=False)
-    if u_boot_console.p.expect([r'Unicode char 0 \(Null\), scan code 15 \(SHIFT\+ALT\+FN 5\)']):
+    if ubman.p.expect([r'Unicode char 0 \(Null\), scan code 15 \(SHIFT\+ALT\+FN 5\)']):
         raise Exception('SHIFT+ALT+FN 5 failed in \'text input\' test')
-    u_boot_console.drain_console()
-    u_boot_console.run_command(cmd=chr(24), wait_for_echo=False, send_nl=False,
+    ubman.drain_console()
+    ubman.run_command(cmd=chr(24), wait_for_echo=False, send_nl=False,
                                wait_for_prompt=False)
-    if u_boot_console.p.expect(['Summary: 0 failures', 'Press any key']):
+    if ubman.p.expect(['Summary: 0 failures', 'Press any key']):
         raise Exception('Failures occurred during the EFI selftest')
-    u_boot_console.restart_uboot()
+    ubman.restart_uboot()
 
 @pytest.mark.buildconfigspec('cmd_bootefi_selftest')
 @pytest.mark.buildconfigspec('efi_tcg2_protocol')
-def test_efi_selftest_tcg2(u_boot_console):
+def test_efi_selftest_tcg2(ubman):
     """Test the EFI_TCG2 PROTOCOL
 
-    u_boot_console -- U-Boot console
+    ubman -- U-Boot console
 
     This function executes the 'tcg2' unit test.
     """
-    u_boot_console.restart_uboot()
-    u_boot_console.run_command(cmd='setenv efi_selftest list')
-    output = u_boot_console.run_command('bootefi selftest')
+    ubman.restart_uboot()
+    ubman.run_command(cmd='setenv efi_selftest list')
+    output = ubman.run_command('bootefi selftest')
     assert '\'tcg2\'' in output
-    u_boot_console.run_command(cmd='setenv efi_selftest tcg2')
-    u_boot_console.run_command(cmd='bootefi selftest', wait_for_prompt=False)
-    if u_boot_console.p.expect(['Summary: 0 failures', 'Press any key']):
+    ubman.run_command(cmd='setenv efi_selftest tcg2')
+    ubman.run_command(cmd='bootefi selftest', wait_for_prompt=False)
+    if ubman.p.expect(['Summary: 0 failures', 'Press any key']):
         raise Exception('Failures occurred during the EFI selftest')
-    u_boot_console.restart_uboot()
+    ubman.restart_uboot()
diff --git a/test/py/tests/test_eficonfig/test_eficonfig.py b/test/py/tests/test_eficonfig/test_eficonfig.py
index d98de5249df..3ca8e27c76b 100644
--- a/test/py/tests/test_eficonfig/test_eficonfig.py
+++ b/test/py/tests/test_eficonfig/test_eficonfig.py
@@ -8,47 +8,47 @@ import time
 @pytest.mark.boardspec('sandbox')
 @pytest.mark.buildconfigspec('cmd_eficonfig')
 @pytest.mark.buildconfigspec('cmd_bootefi_bootmgr')
-def test_efi_eficonfig(u_boot_console, efi_eficonfig_data):
+def test_efi_eficonfig(ubman, efi_eficonfig_data):
 
     def send_user_input_and_wait(user_str, expect_str):
         time.sleep(0.1) # TODO: does not work correctly without sleep
-        u_boot_console.run_command(cmd=user_str, wait_for_prompt=False,
+        ubman.run_command(cmd=user_str, wait_for_prompt=False,
                                    wait_for_echo=True, send_nl=False)
-        u_boot_console.run_command(cmd='\x0d', wait_for_prompt=False,
+        ubman.run_command(cmd='\x0d', wait_for_prompt=False,
                                    wait_for_echo=False, send_nl=False)
         if expect_str is not None:
             for i in expect_str:
-                u_boot_console.p.expect([i])
+                ubman.p.expect([i])
 
     def press_up_down_enter_and_wait(up_count, down_count, enter, expect_str):
         # press UP key
         for i in range(up_count):
-            u_boot_console.run_command(cmd='\x1b\x5b\x41', wait_for_prompt=False,
+            ubman.run_command(cmd='\x1b\x5b\x41', wait_for_prompt=False,
                                        wait_for_echo=False, send_nl=False)
         # press DOWN key
         for i in range(down_count):
-            u_boot_console.run_command(cmd='\x1b\x5b\x42', wait_for_prompt=False,
+            ubman.run_command(cmd='\x1b\x5b\x42', wait_for_prompt=False,
                                        wait_for_echo=False, send_nl=False)
         # press ENTER if requested
         if enter:
-            u_boot_console.run_command(cmd='\x0d', wait_for_prompt=False,
+            ubman.run_command(cmd='\x0d', wait_for_prompt=False,
                                        wait_for_echo=False, send_nl=False)
         # wait expected output
         if expect_str is not None:
             for i in expect_str:
-                u_boot_console.p.expect([i])
+                ubman.p.expect([i])
 
     def press_escape_key(wait_prompt):
-        u_boot_console.run_command(cmd='\x1b', wait_for_prompt=wait_prompt, wait_for_echo=False, send_nl=False)
+        ubman.run_command(cmd='\x1b', wait_for_prompt=wait_prompt, wait_for_echo=False, send_nl=False)
 
     def press_enter_key(wait_prompt):
-        u_boot_console.run_command(cmd='\x0d', wait_for_prompt=wait_prompt,
+        ubman.run_command(cmd='\x0d', wait_for_prompt=wait_prompt,
                                    wait_for_echo=False, send_nl=False)
 
     def check_current_is_maintenance_menu():
         for i in ('UEFI Maintenance Menu', 'Add Boot Option', 'Edit Boot Option',
                   'Change Boot Order', 'Delete Boot Option', 'Quit'):
-            u_boot_console.p.expect([i])
+            ubman.p.expect([i])
 
     """ Unit test for "eficonfig" command
     The menu-driven interface is used to set up UEFI load options.
@@ -56,7 +56,7 @@ def test_efi_eficonfig(u_boot_console, efi_eficonfig_data):
     The crc32 of the loaded initrd.img is checked
 
     Args:
-        u_boot_console -- U-Boot console
+        ubman -- U-Boot console
         efi__data -- Path to the disk image used for testing.
                      Test disk image has following files.
                          initrd-1.img
@@ -69,21 +69,21 @@ def test_efi_eficonfig(u_boot_console, efi_eficonfig_data):
     return
 
     # Restart the system to clean the previous state
-    u_boot_console.restart_uboot()
+    ubman.restart_uboot()
 
-    with u_boot_console.temporary_timeout(500):
+    with ubman.temporary_timeout(500):
         #
         # Test Case 1: Check the menu is displayed
         #
-        u_boot_console.run_command('eficonfig', wait_for_prompt=False)
+        ubman.run_command('eficonfig', wait_for_prompt=False)
         for i in ('UEFI Maintenance Menu', 'Add Boot Option', 'Edit Boot Option',
                   'Change Boot Order', 'Delete Boot Option', 'Quit'):
-            u_boot_console.p.expect([i])
+            ubman.p.expect([i])
         # Select "Add Boot Option"
         press_enter_key(False)
         for i in ('Add Boot Option', 'Description:', 'File', 'Initrd File', 'Optional Data',
                   'Save', 'Quit'):
-            u_boot_console.p.expect([i])
+            ubman.p.expect([i])
         press_escape_key(False)
         check_current_is_maintenance_menu()
         # return to U-Boot console
@@ -94,16 +94,16 @@ def test_efi_eficonfig(u_boot_console, efi_eficonfig_data):
         #
 
         # bind the test disk image for succeeding tests
-        u_boot_console.run_command(cmd = f'host bind 0 {efi_eficonfig_data}')
+        ubman.run_command(cmd = f'host bind 0 {efi_eficonfig_data}')
 
-        u_boot_console.run_command('eficonfig', wait_for_prompt=False)
+        ubman.run_command('eficonfig', wait_for_prompt=False)
 
         # Change the Boot Order
         press_up_down_enter_and_wait(0, 2, True, 'Quit')
         for i in ('host 0:1', 'Save', 'Quit'):
-            u_boot_console.p.expect([i])
+            ubman.p.expect([i])
         # disable auto generated boot option for succeeding test
-        u_boot_console.run_command(cmd=' ', wait_for_prompt=False,
+        ubman.run_command(cmd=' ', wait_for_prompt=False,
                                        wait_for_echo=False, send_nl=False)
         # Save the BootOrder
         press_up_down_enter_and_wait(0, 1, True, None)
@@ -143,7 +143,7 @@ def test_efi_eficonfig(u_boot_console, efi_eficonfig_data):
         send_user_input_and_wait('nocolor', None)
         for i in ('Description: test 1', 'File: host 0:1/initrddump.efi',
                   'Initrd File: host 0:1/initrd-1.img', 'Optional Data: nocolor', 'Save', 'Quit'):
-            u_boot_console.p.expect([i])
+            ubman.p.expect([i])
 
         # Save the Boot Option
         press_up_down_enter_and_wait(0, 4, True, None)
@@ -152,15 +152,15 @@ def test_efi_eficonfig(u_boot_console, efi_eficonfig_data):
         # Check the newly added Boot Option is handled correctly
         # Return to U-Boot console
         press_escape_key(True)
-        u_boot_console.run_command(cmd = 'bootefi bootmgr')
-        response = u_boot_console.run_command(cmd = 'load', wait_for_echo=False)
+        ubman.run_command(cmd = 'bootefi bootmgr')
+        response = ubman.run_command(cmd = 'load', wait_for_echo=False)
         assert 'crc32: 0x181464af' in response
-        u_boot_console.run_command(cmd = 'exit', wait_for_echo=False)
+        ubman.run_command(cmd = 'exit', wait_for_echo=False)
 
         #
         # Test Case 4: Add second Boot Option and load it
         #
-        u_boot_console.run_command('eficonfig', wait_for_prompt=False)
+        ubman.run_command('eficonfig', wait_for_prompt=False)
 
         # Select 'Add Boot Option'
         press_up_down_enter_and_wait(0, 0, True, 'Quit')
@@ -192,7 +192,7 @@ def test_efi_eficonfig(u_boot_console, efi_eficonfig_data):
         send_user_input_and_wait('nocolor', None)
         for i in ('Description: test 2', 'File: host 0:1/initrddump.efi',
                   'Initrd File: host 0:1/initrd-2.img', 'Optional Data: nocolor', 'Save', 'Quit'):
-            u_boot_console.p.expect([i])
+            ubman.p.expect([i])
 
         # Save the Boot Option
         press_up_down_enter_and_wait(0, 4, True, 'Quit')
@@ -201,10 +201,10 @@ def test_efi_eficonfig(u_boot_console, efi_eficonfig_data):
         press_up_down_enter_and_wait(0, 2, True, 'Quit')
         press_up_down_enter_and_wait(0, 1, False, 'Quit')
         # move 'test 1' to the second entry
-        u_boot_console.run_command(cmd='+', wait_for_prompt=False,
+        ubman.run_command(cmd='+', wait_for_prompt=False,
                                        wait_for_echo=False, send_nl=False)
         for i in ('test 2', 'test 1', 'host 0:1', 'Save', 'Quit'):
-            u_boot_console.p.expect([i])
+            ubman.p.expect([i])
         # Save the BootOrder
         press_up_down_enter_and_wait(0, 3, True, None)
         check_current_is_maintenance_menu()
@@ -212,52 +212,52 @@ def test_efi_eficonfig(u_boot_console, efi_eficonfig_data):
         # Check the newly added Boot Option is handled correctly
         # Return to U-Boot console
         press_escape_key(True)
-        u_boot_console.run_command(cmd = 'bootefi bootmgr')
-        response = u_boot_console.run_command(cmd = 'load', wait_for_echo=False)
+        ubman.run_command(cmd = 'bootefi bootmgr')
+        response = ubman.run_command(cmd = 'load', wait_for_echo=False)
         assert 'crc32: 0x811d3515' in response
-        u_boot_console.run_command(cmd = 'exit', wait_for_echo=False)
+        ubman.run_command(cmd = 'exit', wait_for_echo=False)
 
         #
         # Test Case 5: Change BootOrder and load it
         #
-        u_boot_console.run_command('eficonfig', wait_for_prompt=False)
+        ubman.run_command('eficonfig', wait_for_prompt=False)
 
         # Change the Boot Order
         press_up_down_enter_and_wait(0, 2, True, None)
         # Check the current BootOrder
         for i in ('test 2', 'test 1', 'host 0:1', 'Save', 'Quit'):
-            u_boot_console.p.expect([i])
+            ubman.p.expect([i])
         # move 'test 2' to the second entry
-        u_boot_console.run_command(cmd='-', wait_for_prompt=False,
+        ubman.run_command(cmd='-', wait_for_prompt=False,
                                        wait_for_echo=False, send_nl=False)
         for i in ('test 1', 'test 2', 'host 0:1', 'Save', 'Quit'):
-            u_boot_console.p.expect([i])
+            ubman.p.expect([i])
         # Save the BootOrder
         press_up_down_enter_and_wait(0, 2, True, None)
         check_current_is_maintenance_menu()
 
         # Return to U-Boot console
         press_escape_key(True)
-        u_boot_console.run_command(cmd = 'bootefi bootmgr')
-        response = u_boot_console.run_command(cmd = 'load', wait_for_echo=False)
+        ubman.run_command(cmd = 'bootefi bootmgr')
+        response = ubman.run_command(cmd = 'load', wait_for_echo=False)
         assert 'crc32: 0x181464af' in response
-        u_boot_console.run_command(cmd = 'exit', wait_for_echo=False)
+        ubman.run_command(cmd = 'exit', wait_for_echo=False)
 
         #
         # Test Case 6: Delete Boot Option(label:test 2)
         #
-        u_boot_console.run_command('eficonfig', wait_for_prompt=False)
+        ubman.run_command('eficonfig', wait_for_prompt=False)
 
         # Select 'Delete Boot Option'
         press_up_down_enter_and_wait(0, 3, True, None)
         # Check the current BootOrder
         for i in ('test 1', 'test 2', 'Quit'):
-            u_boot_console.p.expect([i])
+            ubman.p.expect([i])
 
         # Delete 'test 2'
         press_up_down_enter_and_wait(0, 1, True, None)
         for i in ('test 1', 'Quit'):
-            u_boot_console.p.expect([i])
+            ubman.p.expect([i])
         press_escape_key(False)
         check_current_is_maintenance_menu()
         # Return to U-Boot console
@@ -266,16 +266,16 @@ def test_efi_eficonfig(u_boot_console, efi_eficonfig_data):
         #
         # Test Case 7: Edit Boot Option
         #
-        u_boot_console.run_command('eficonfig', wait_for_prompt=False)
+        ubman.run_command('eficonfig', wait_for_prompt=False)
         # Select 'Edit Boot Option'
         press_up_down_enter_and_wait(0, 1, True, None)
         # Check the current BootOrder
         for i in ('test 1', 'Quit'):
-            u_boot_console.p.expect([i])
+            ubman.p.expect([i])
         press_up_down_enter_and_wait(0, 0, True, None)
         for i in ('Description: test 1', 'File: host 0:1/initrddump.efi',
                   'Initrd File: host 0:1/initrd-1.img', 'Optional Data: nocolor', 'Save', 'Quit'):
-            u_boot_console.p.expect([i])
+            ubman.p.expect([i])
 
         # Press the enter key to select 'Description:' entry, then enter Description
         press_up_down_enter_and_wait(0, 0, True, 'Enter description:')
@@ -304,7 +304,7 @@ def test_efi_eficonfig(u_boot_console, efi_eficonfig_data):
         send_user_input_and_wait('', None)
         for i in ('Description: test 3', 'File: host 0:1/initrddump.efi',
                   'Initrd File: host 0:1/initrd-2.img', 'Optional Data:', 'Save', 'Quit'):
-            u_boot_console.p.expect([i])
+            ubman.p.expect([i])
 
         # Save the Boot Option
         press_up_down_enter_and_wait(0, 4, True, 'Quit')
@@ -314,21 +314,21 @@ def test_efi_eficonfig(u_boot_console, efi_eficonfig_data):
         # Check the updated Boot Option is handled correctly
         # Return to U-Boot console
         press_escape_key(True)
-        u_boot_console.run_command(cmd = 'bootefi bootmgr')
-        response = u_boot_console.run_command(cmd = 'load', wait_for_echo=False)
+        ubman.run_command(cmd = 'bootefi bootmgr')
+        response = ubman.run_command(cmd = 'load', wait_for_echo=False)
         assert 'crc32: 0x811d3515' in response
-        u_boot_console.run_command(cmd = 'exit', wait_for_echo=False)
+        ubman.run_command(cmd = 'exit', wait_for_echo=False)
 
         #
         # Test Case 8: Delete Boot Option(label:test 3)
         #
-        u_boot_console.run_command('eficonfig', wait_for_prompt=False)
+        ubman.run_command('eficonfig', wait_for_prompt=False)
 
         # Select 'Delete Boot Option'
         press_up_down_enter_and_wait(0, 3, True, None)
         # Check the current BootOrder
         for i in ('test 3', 'Quit'):
-            u_boot_console.p.expect([i])
+            ubman.p.expect([i])
 
         # Delete 'test 3'
         press_up_down_enter_and_wait(0, 0, True, 'Quit')
@@ -338,12 +338,12 @@ def test_efi_eficonfig(u_boot_console, efi_eficonfig_data):
         press_escape_key(True)
 
         # remove the host device
-        u_boot_console.run_command(cmd = f'host bind -r 0')
+        ubman.run_command(cmd = f'host bind -r 0')
 
         #
         # Test Case 9: No block device found
         #
-        u_boot_console.run_command('eficonfig', wait_for_prompt=False)
+        ubman.run_command('eficonfig', wait_for_prompt=False)
 
         # Select 'Add Boot Option'
         press_up_down_enter_and_wait(0, 0, True, 'Quit')
diff --git a/test/py/tests/test_env.py b/test/py/tests/test_env.py
index 4471db7d9cb..383e26c03b0 100644
--- a/test/py/tests/test_env.py
+++ b/test/py/tests/test_env.py
@@ -13,7 +13,7 @@ from subprocess import call, CalledProcessError
 import tempfile
 
 import pytest
-import u_boot_utils
+import utils
 
 # FIXME: This might be useful for other tests;
 # perhaps refactor it into ConsoleBase or some other state object?
@@ -23,17 +23,17 @@ class StateTestEnv(object):
     names.
     """
 
-    def __init__(self, u_boot_console):
+    def __init__(self, ubman):
         """Initialize a new StateTestEnv object.
 
         Args:
-            u_boot_console: A U-Boot console.
+            ubman: A U-Boot console.
 
         Returns:
             Nothing.
         """
 
-        self.u_boot_console = u_boot_console
+        self.ubman = ubman
         self.get_env()
         self.set_var = self.get_non_existent_var()
 
@@ -47,12 +47,12 @@ class StateTestEnv(object):
             Nothing.
         """
 
-        if self.u_boot_console.config.buildconfig.get(
+        if self.ubman.config.buildconfig.get(
                 'config_version_variable', 'n') == 'y':
-            with self.u_boot_console.disable_check('main_signon'):
-                response = self.u_boot_console.run_command('printenv')
+            with self.ubman.disable_check('main_signon'):
+                response = self.ubman.run_command('printenv')
         else:
-            response = self.u_boot_console.run_command('printenv')
+            response = self.ubman.run_command('printenv')
         self.env = {}
         for l in response.splitlines():
             if not '=' in l:
@@ -92,12 +92,12 @@ class StateTestEnv(object):
 
 ste = None
 @pytest.fixture(scope='function')
-def state_test_env(u_boot_console):
+def state_test_env(ubman):
     """pytest fixture to provide a StateTestEnv object to tests."""
 
     global ste
     if not ste:
-        ste = StateTestEnv(u_boot_console)
+        ste = StateTestEnv(ubman)
     return ste
 
 def unset_var(state_test_env, var):
@@ -114,7 +114,7 @@ def unset_var(state_test_env, var):
         Nothing.
     """
 
-    state_test_env.u_boot_console.run_command('setenv %s' % var)
+    state_test_env.ubman.run_command('setenv %s' % var)
     if var in state_test_env.env:
         del state_test_env.env[var]
 
@@ -133,7 +133,7 @@ def set_var(state_test_env, var, value):
         Nothing.
     """
 
-    bc = state_test_env.u_boot_console.config.buildconfig
+    bc = state_test_env.ubman.config.buildconfig
     if bc.get('config_hush_parser', None):
         quote = '"'
     else:
@@ -141,7 +141,7 @@ def set_var(state_test_env, var, value):
         if ' ' in value:
             pytest.skip('Space in variable value on non-Hush shell')
 
-    state_test_env.u_boot_console.run_command(
+    state_test_env.ubman.run_command(
         'setenv %s %s%s%s' % (var, quote, value, quote))
     state_test_env.env[var] = value
 
@@ -155,7 +155,7 @@ def validate_empty(state_test_env, var):
         Nothing.
     """
 
-    response = state_test_env.u_boot_console.run_command('echo ${%s}' % var)
+    response = state_test_env.ubman.run_command('echo ${%s}' % var)
     assert response == ''
 
 def validate_set(state_test_env, var, value):
@@ -171,15 +171,14 @@ def validate_set(state_test_env, var, value):
 
     # echo does not preserve leading, internal, or trailing whitespace in the
     # value. printenv does, and hence allows more complete testing.
-    response = state_test_env.u_boot_console.run_command('printenv %s' % var)
+    response = state_test_env.ubman.run_command('printenv %s' % var)
     assert response == ('%s=%s' % (var, value))
 
 @pytest.mark.boardspec('sandbox')
-def test_env_initial_env_file(u_boot_console):
+def test_env_initial_env_file(ubman):
     """Test that the u-boot-initial-env make target works"""
-    cons = u_boot_console
-    builddir = 'O=' + cons.config.build_dir
-    envfile = cons.config.build_dir + '/u-boot-initial-env'
+    builddir = 'O=' + ubman.config.build_dir
+    envfile = ubman.config.build_dir + '/u-boot-initial-env'
 
     # remove if already exists from an older run
     try:
@@ -187,7 +186,7 @@ def test_env_initial_env_file(u_boot_console):
     except:
         pass
 
-    u_boot_utils.run_and_log(cons, ['make', builddir, 'u-boot-initial-env'])
+    utils.run_and_log(ubman, ['make', builddir, 'u-boot-initial-env'])
 
     assert os.path.exists(envfile)
 
@@ -215,7 +214,7 @@ def test_env_printenv_non_existent(state_test_env):
     """Test printenv error message for non-existant variables."""
 
     var = state_test_env.set_var
-    c = state_test_env.u_boot_console
+    c = state_test_env.ubman
     with c.disable_check('error_notification'):
         response = c.run_command('printenv %s' % var)
     assert response == '## Error: "%s" not defined' % var
@@ -277,8 +276,8 @@ def test_env_import_checksum_no_size(state_test_env):
     """Test that omitted ('-') size parameter with checksum validation fails the
        env import function.
     """
-    c = state_test_env.u_boot_console
-    ram_base = u_boot_utils.find_ram_base(state_test_env.u_boot_console)
+    c = state_test_env.ubman
+    ram_base = utils.find_ram_base(state_test_env.ubman)
     addr = '%08x' % ram_base
 
     with c.disable_check('error_notification'):
@@ -290,8 +289,8 @@ def test_env_import_whitelist_checksum_no_size(state_test_env):
     """Test that omitted ('-') size parameter with checksum validation fails the
        env import function when variables are passed as parameters.
     """
-    c = state_test_env.u_boot_console
-    ram_base = u_boot_utils.find_ram_base(state_test_env.u_boot_console)
+    c = state_test_env.ubman
+    ram_base = utils.find_ram_base(state_test_env.ubman)
     addr = '%08x' % ram_base
 
     with c.disable_check('error_notification'):
@@ -302,8 +301,8 @@ def test_env_import_whitelist_checksum_no_size(state_test_env):
 @pytest.mark.buildconfigspec('cmd_importenv')
 def test_env_import_whitelist(state_test_env):
     """Test importing only a handful of env variables from an environment."""
-    c = state_test_env.u_boot_console
-    ram_base = u_boot_utils.find_ram_base(state_test_env.u_boot_console)
+    c = state_test_env.ubman
+    ram_base = utils.find_ram_base(state_test_env.ubman)
     addr = '%08x' % ram_base
 
     set_var(state_test_env, 'foo1', 'bar1')
@@ -339,8 +338,8 @@ def test_env_import_whitelist_delete(state_test_env):
        deletion if a var A that is passed to env import is not in the
        environment to be imported.
     """
-    c = state_test_env.u_boot_console
-    ram_base = u_boot_utils.find_ram_base(state_test_env.u_boot_console)
+    c = state_test_env.ubman
+    ram_base = utils.find_ram_base(state_test_env.ubman)
     addr = '%08x' % ram_base
 
     set_var(state_test_env, 'foo1', 'bar1')
@@ -373,7 +372,7 @@ def test_env_info(state_test_env):
 
     """Test 'env info' command with all possible options.
     """
-    c = state_test_env.u_boot_console
+    c = state_test_env.ubman
 
     response = c.run_command('env info')
     nb_line = 0
@@ -410,7 +409,7 @@ def test_env_info_sandbox(state_test_env):
     """Test 'env info' command result with several options on sandbox
        with a known ENV configuration: ready & default & persistent
     """
-    c = state_test_env.u_boot_console
+    c = state_test_env.ubman
 
     response = c.run_command('env info')
     assert 'env_ready = true' in response
@@ -435,7 +434,7 @@ def test_env_info_sandbox(state_test_env):
 def mk_env_ext4(state_test_env):
 
     """Create a empty ext4 file system volume."""
-    c = state_test_env.u_boot_console
+    c = state_test_env.ubman
     filename = 'env.ext4.img'
     persistent = c.config.persistent_data_dir + '/' + filename
     fs_img = c.config.result_dir  + '/' + filename
@@ -446,16 +445,16 @@ def mk_env_ext4(state_test_env):
         # Some distributions do not add /sbin to the default PATH, where mkfs.ext4 lives
         os.environ["PATH"] += os.pathsep + '/sbin'
         try:
-            u_boot_utils.run_and_log(c, 'dd if=/dev/zero of=%s bs=1M count=16' % persistent)
-            u_boot_utils.run_and_log(c, 'mkfs.ext4 %s' % persistent)
-            sb_content = u_boot_utils.run_and_log(c, 'tune2fs -l %s' % persistent)
+            utils.run_and_log(c, 'dd if=/dev/zero of=%s bs=1M count=16' % persistent)
+            utils.run_and_log(c, 'mkfs.ext4 %s' % persistent)
+            sb_content = utils.run_and_log(c, 'tune2fs -l %s' % persistent)
             if 'metadata_csum' in sb_content:
-                u_boot_utils.run_and_log(c, 'tune2fs -O ^metadata_csum %s' % persistent)
+                utils.run_and_log(c, 'tune2fs -O ^metadata_csum %s' % persistent)
         except CalledProcessError:
             call('rm -f %s' % persistent, shell=True)
             raise
 
-    u_boot_utils.run_and_log(c, ['cp',  '-f', persistent, fs_img])
+    utils.run_and_log(c, ['cp',  '-f', persistent, fs_img])
     return fs_img
 
 @pytest.mark.boardspec('sandbox')
@@ -467,7 +466,7 @@ def mk_env_ext4(state_test_env):
 def test_env_ext4(state_test_env):
 
     """Test ENV in EXT4 on sandbox."""
-    c = state_test_env.u_boot_console
+    c = state_test_env.ubman
     fs_img = ''
     try:
         fs_img = mk_env_ext4(state_test_env)
@@ -545,7 +544,7 @@ def test_env_ext4(state_test_env):
         if fs_img:
             call('rm -f %s' % fs_img, shell=True)
 
-def test_env_text(u_boot_console):
+def test_env_text(ubman):
     """Test the script that converts the environment to a text file"""
 
     def check_script(intext, expect_val):
@@ -560,15 +559,14 @@ def test_env_text(u_boot_console):
             fname = os.path.join(path, 'infile')
             with open(fname, 'w') as inf:
                 print(intext, file=inf)
-            result = u_boot_utils.run_and_log(cons, ['awk', '-f', script, fname])
+            result = utils.run_and_log(ubman, ['awk', '-f', script, fname])
             if expect_val is not None:
                 expect = '#define CONFIG_EXTRA_ENV_TEXT "%s"\n' % expect_val
                 assert result == expect
             else:
                 assert result == ''
 
-    cons = u_boot_console
-    script = os.path.join(cons.config.source_dir, 'scripts', 'env2string.awk')
+    script = os.path.join(ubman.config.source_dir, 'scripts', 'env2string.awk')
 
     # simple script with a single var
     check_script('fred=123', 'fred=123\\0')
diff --git a/test/py/tests/test_event_dump.py b/test/py/tests/test_event_dump.py
index 177b982e891..b9d48f54dc2 100644
--- a/test/py/tests/test_event_dump.py
+++ b/test/py/tests/test_event_dump.py
@@ -4,16 +4,15 @@
 
 import pytest
 import re
-import u_boot_utils as util
+import utils
 
 # This is only a partial test - coverting 64-bit sandbox. It does not test
 # big-endian images, nor 32-bit images
 @pytest.mark.boardspec('sandbox')
-def test_event_dump(u_boot_console):
+def test_event_dump(ubman):
     """Test that the "help" command can be executed."""
-    cons = u_boot_console
-    sandbox = cons.config.build_dir + '/u-boot'
-    out = util.run_and_log(cons, ['scripts/event_dump.py', sandbox])
+    sandbox = ubman.config.build_dir + '/u-boot'
+    out = utils.run_and_log(ubman, ['scripts/event_dump.py', sandbox])
     expect = '''.*Event type            Id                              Source location
 --------------------  ------------------------------  ------------------------------
 EVT_FT_FIXUP          bootmeth_vbe_ft_fixup           .*boot/vbe_request.c:.*
diff --git a/test/py/tests/test_extension.py b/test/py/tests/test_extension.py
index 2a3c5116171..61223496054 100644
--- a/test/py/tests/test_extension.py
+++ b/test/py/tests/test_extension.py
@@ -6,50 +6,50 @@
 
 import os
 import pytest
-import u_boot_utils
+import utils
 
 overlay_addr = 0x1000
 
 SANDBOX_DTB='arch/sandbox/dts/sandbox.dtb'
 OVERLAY_DIR='arch/sandbox/dts/'
 
-def load_dtb(u_boot_console):
-    u_boot_console.log.action('Loading devicetree to RAM...')
-    u_boot_console.run_command('host load hostfs - $fdt_addr_r %s' % (os.path.join(u_boot_console.config.build_dir, SANDBOX_DTB)))
-    u_boot_console.run_command('fdt addr $fdt_addr_r')
+def load_dtb(ubman):
+    ubman.log.action('Loading devicetree to RAM...')
+    ubman.run_command('host load hostfs - $fdt_addr_r %s' % (os.path.join(ubman.config.build_dir, SANDBOX_DTB)))
+    ubman.run_command('fdt addr $fdt_addr_r')
 
 @pytest.mark.buildconfigspec('cmd_fdt')
 @pytest.mark.boardspec('sandbox')
-def test_extension(u_boot_console):
+def test_extension(ubman):
     """Test the 'extension' command."""
 
-    load_dtb(u_boot_console)
+    load_dtb(ubman)
 
-    output = u_boot_console.run_command('extension list')
+    output = ubman.run_command('extension list')
     # extension_bootdev_hunt may have already run.
     # Without reboot we cannot make any assumption here.
     # assert('No extension' in output)
 
-    output = u_boot_console.run_command('extension scan')
+    output = ubman.run_command('extension scan')
     assert output == 'Found 2 extension board(s).'
 
-    output = u_boot_console.run_command('extension list')
+    output = ubman.run_command('extension list')
     assert('overlay0.dtbo' in output)
     assert('overlay1.dtbo' in output)
 
-    u_boot_console.run_command_list([
+    ubman.run_command_list([
         'setenv extension_overlay_addr %s' % (overlay_addr),
-        'setenv extension_overlay_cmd \'host load hostfs - ${extension_overlay_addr} %s${extension_overlay_name}\'' % (os.path.join(u_boot_console.config.build_dir, OVERLAY_DIR))])
+        'setenv extension_overlay_cmd \'host load hostfs - ${extension_overlay_addr} %s${extension_overlay_name}\'' % (os.path.join(ubman.config.build_dir, OVERLAY_DIR))])
 
-    output = u_boot_console.run_command('extension apply 0')
+    output = ubman.run_command('extension apply 0')
     assert('bytes read' in output)
 
-    output = u_boot_console.run_command('fdt print')
+    output = ubman.run_command('fdt print')
     assert('button3' in output)
 
-    output = u_boot_console.run_command('extension apply all')
+    output = ubman.run_command('extension apply all')
     assert('bytes read' in output)
 
-    output = u_boot_console.run_command('fdt print')
+    output = ubman.run_command('fdt print')
     assert('button4' in output)
 
diff --git a/test/py/tests/test_fit.py b/test/py/tests/test_fit.py
index 8f9c4b26411..619f73153a0 100755
--- a/test/py/tests/test_fit.py
+++ b/test/py/tests/test_fit.py
@@ -6,7 +6,7 @@
 import os
 import pytest
 import struct
-import u_boot_utils as util
+import utils
 import fit_util
 
 # Define a base ITS which we can adjust using % and a dictionary
@@ -118,7 +118,7 @@ host save hostfs 0 %(loadables2_addr)x %(loadables2_out)s %(loadables2_size)x
 @pytest.mark.boardspec('sandbox')
 @pytest.mark.buildconfigspec('fit_signature')
 @pytest.mark.requiredtool('dtc')
-def test_fit(u_boot_console):
+def test_fit(ubman):
     def make_fname(leaf):
         """Make a temporary filename
 
@@ -127,7 +127,7 @@ def test_fit(u_boot_console):
         Return:
             Temporary filename
         """
-        return os.path.join(cons.config.build_dir, leaf)
+        return os.path.join(ubman.config.build_dir, leaf)
 
     def filesize(fname):
         """Get the size of a file
@@ -165,7 +165,7 @@ def test_fit(u_boot_console):
         return fname
 
     def make_compressed(filename):
-        util.run_and_log(cons, ['gzip', '-f', '-k', filename])
+        utils.run_and_log(ubman, ['gzip', '-f', '-k', filename])
         return filename + '.gz'
 
     def find_matching(text, match):
@@ -260,10 +260,10 @@ def test_fit(u_boot_console):
           - run code coverage to make sure we are testing all the code
         """
         # Set up invariant files
-        control_dtb = fit_util.make_dtb(cons, base_fdt, 'u-boot')
-        kernel = fit_util.make_kernel(cons, 'test-kernel.bin', 'kernel')
+        control_dtb = fit_util.make_dtb(ubman, base_fdt, 'u-boot')
+        kernel = fit_util.make_kernel(ubman, 'test-kernel.bin', 'kernel')
         ramdisk = make_ramdisk('test-ramdisk.bin', 'ramdisk')
-        loadables1 = fit_util.make_kernel(cons, 'test-loadables1.bin', 'lenrek')
+        loadables1 = fit_util.make_kernel(ubman, 'test-loadables1.bin', 'lenrek')
         loadables2 = make_ramdisk('test-loadables2.bin', 'ksidmar')
         kernel_out = make_fname('kernel-out.bin')
         fdt = make_fname('u-boot.dtb')
@@ -311,16 +311,16 @@ def test_fit(u_boot_console):
         }
 
         # Make a basic FIT and a script to load it
-        fit = fit_util.make_fit(cons, mkimage, base_its, params)
+        fit = fit_util.make_fit(ubman, mkimage, base_its, params)
         params['fit'] = fit
         cmd = base_script % params
 
         # First check that we can load a kernel
         # We could perhaps reduce duplication with some loss of readability
-        cons.config.dtb = control_dtb
-        cons.restart_uboot()
-        with cons.log.section('Kernel load'):
-            output = cons.run_command_list(cmd.splitlines())
+        ubman.config.dtb = control_dtb
+        ubman.restart_uboot()
+        with ubman.log.section('Kernel load'):
+            output = ubman.run_command_list(cmd.splitlines())
             check_equal(kernel, kernel_out, 'Kernel not loaded')
             check_not_equal(control_dtb, fdt_out,
                             'FDT loaded but should be ignored')
@@ -340,7 +340,7 @@ def test_fit(u_boot_console):
                   (fit_offset, real_fit_offset))
 
             # Check if bootargs strings substitution works
-            output = cons.run_command_list([
+            output = ubman.run_command_list([
                 'env set bootargs \\\"\'my_boot_var=${foo}\'\\\"',
                 'env set foo bar',
                 'bootm prep',
@@ -348,63 +348,62 @@ def test_fit(u_boot_console):
             assert 'bootargs="my_boot_var=bar"' in output, "Bootargs strings not substituted"
 
         # Now a kernel and an FDT
-        with cons.log.section('Kernel + FDT load'):
+        with ubman.log.section('Kernel + FDT load'):
             params['fdt_load'] = 'load = <%#x>;' % params['fdt_addr']
-            fit = fit_util.make_fit(cons, mkimage, base_its, params)
-            cons.restart_uboot()
-            output = cons.run_command_list(cmd.splitlines())
+            fit = fit_util.make_fit(ubman, mkimage, base_its, params)
+            ubman.restart_uboot()
+            output = ubman.run_command_list(cmd.splitlines())
             check_equal(kernel, kernel_out, 'Kernel not loaded')
             check_equal(control_dtb, fdt_out, 'FDT not loaded')
             check_not_equal(ramdisk, ramdisk_out,
                             'Ramdisk loaded but should not be')
 
         # Try a ramdisk
-        with cons.log.section('Kernel + FDT + Ramdisk load'):
+        with ubman.log.section('Kernel + FDT + Ramdisk load'):
             params['ramdisk_config'] = 'ramdisk = "ramdisk-1";'
             params['ramdisk_load'] = 'load = <%#x>;' % params['ramdisk_addr']
-            fit = fit_util.make_fit(cons, mkimage, base_its, params)
-            cons.restart_uboot()
-            output = cons.run_command_list(cmd.splitlines())
+            fit = fit_util.make_fit(ubman, mkimage, base_its, params)
+            ubman.restart_uboot()
+            output = ubman.run_command_list(cmd.splitlines())
             check_equal(ramdisk, ramdisk_out, 'Ramdisk not loaded')
 
         # Configuration with some Loadables
-        with cons.log.section('Kernel + FDT + Ramdisk load + Loadables'):
+        with ubman.log.section('Kernel + FDT + Ramdisk load + Loadables'):
             params['loadables_config'] = 'loadables = "kernel-2", "ramdisk-2";'
             params['loadables1_load'] = ('load = <%#x>;' %
                                          params['loadables1_addr'])
             params['loadables2_load'] = ('load = <%#x>;' %
                                          params['loadables2_addr'])
-            fit = fit_util.make_fit(cons, mkimage, base_its, params)
-            cons.restart_uboot()
-            output = cons.run_command_list(cmd.splitlines())
+            fit = fit_util.make_fit(ubman, mkimage, base_its, params)
+            ubman.restart_uboot()
+            output = ubman.run_command_list(cmd.splitlines())
             check_equal(loadables1, loadables1_out,
                         'Loadables1 (kernel) not loaded')
             check_equal(loadables2, loadables2_out,
                         'Loadables2 (ramdisk) not loaded')
 
         # Kernel, FDT and Ramdisk all compressed
-        with cons.log.section('(Kernel + FDT + Ramdisk) compressed'):
+        with ubman.log.section('(Kernel + FDT + Ramdisk) compressed'):
             params['compression'] = 'gzip'
             params['kernel'] = make_compressed(kernel)
             params['fdt'] = make_compressed(fdt)
             params['ramdisk'] = make_compressed(ramdisk)
-            fit = fit_util.make_fit(cons, mkimage, base_its, params)
-            cons.restart_uboot()
-            output = cons.run_command_list(cmd.splitlines())
+            fit = fit_util.make_fit(ubman, mkimage, base_its, params)
+            ubman.restart_uboot()
+            output = ubman.run_command_list(cmd.splitlines())
             check_equal(kernel, kernel_out, 'Kernel not loaded')
             check_equal(control_dtb, fdt_out, 'FDT not loaded')
             check_not_equal(ramdisk, ramdisk_out, 'Ramdisk got decompressed?')
             check_equal(ramdisk + '.gz', ramdisk_out, 'Ramdist not loaded')
 
 
-    cons = u_boot_console
     # We need to use our own device tree file. Remember to restore it
     # afterwards.
-    old_dtb = cons.config.dtb
+    old_dtb = ubman.config.dtb
     try:
-        mkimage = cons.config.build_dir + '/tools/mkimage'
+        mkimage = ubman.config.build_dir + '/tools/mkimage'
         run_fit_test(mkimage)
     finally:
         # Go back to the original U-Boot with the correct dtb.
-        cons.config.dtb = old_dtb
-        cons.restart_uboot()
+        ubman.config.dtb = old_dtb
+        ubman.restart_uboot()
diff --git a/test/py/tests/test_fit_auto_signed.py b/test/py/tests/test_fit_auto_signed.py
index 9ea3351619f..cdfd341c6f5 100644
--- a/test/py/tests/test_fit_auto_signed.py
+++ b/test/py/tests/test_fit_auto_signed.py
@@ -17,7 +17,7 @@ The test does not run the sandbox. It only checks the host tool mkimage.
 
 import os
 import pytest
-import u_boot_utils as util
+import utils
 import binascii
 from Cryptodome.Hash import SHA1
 from Cryptodome.Hash import SHA256
@@ -26,22 +26,22 @@ from Cryptodome.Signature import pkcs1_15
 
 class SignedFitHelper(object):
     """Helper to manipulate a FIT with signed/hashed images/configs."""
-    def __init__(self, cons, file_name):
+    def __init__(self, ubman, file_name):
         self.fit = file_name
-        self.cons = cons
+        self.ubman = ubman
         self.images_nodes = set()
         self.confgs_nodes = set()
 
     def __fdt_list(self, path):
-        return util.run_and_log(self.cons,
+        return utils.run_and_log(self.ubman,
             f'fdtget -l {self.fit} {path}')
 
     def __fdt_get_string(self, node, prop):
-        return util.run_and_log(self.cons,
+        return utils.run_and_log(self.ubman,
             f'fdtget -ts {self.fit} {node} {prop}')
 
     def __fdt_get_binary(self, node, prop):
-        numbers = util.run_and_log(self.cons,
+        numbers = utils.run_and_log(self.ubman,
             f'fdtget -tbi {self.fit} {node} {prop}')
 
         bignum = bytearray()
@@ -120,7 +120,7 @@ class SignedFitHelper(object):
 
 @pytest.mark.buildconfigspec('fit_signature')
 @pytest.mark.requiredtool('fdtget')
-def test_fit_auto_signed(u_boot_console):
+def test_fit_auto_signed(ubman):
     """Test that mkimage generates auto-FIT with signatures/hashes as expected.
 
     The mkimage tool can create auto generated (i.e. without an ITS file
@@ -133,9 +133,8 @@ def test_fit_auto_signed(u_boot_console):
 
     The test does not run the sandbox. It only checks the host tool mkimage.
     """
-    cons = u_boot_console
-    mkimage = cons.config.build_dir + '/tools/mkimage'
-    tempdir = os.path.join(cons.config.result_dir, 'auto_fit')
+    mkimage = ubman.config.build_dir + '/tools/mkimage'
+    tempdir = os.path.join(ubman.config.result_dir, 'auto_fit')
     os.makedirs(tempdir, exist_ok=True)
     kernel_file = f'{tempdir}/vmlinuz'
     dt1_file = f'{tempdir}/dt-1.dtb'
@@ -166,29 +165,29 @@ def test_fit_auto_signed(u_boot_console):
     s_args = " -k" + tempdir + " -g" + key_name + " -o" + sign_algo
 
     # 1 - Create auto FIT with images crc32 checksum, and verify it
-    util.run_and_log(cons, mkimage + ' -fauto' + b_args + " " + fit_file)
+    utils.run_and_log(ubman, mkimage + ' -fauto' + b_args + " " + fit_file)
 
-    fit = SignedFitHelper(cons, fit_file)
+    fit = SignedFitHelper(ubman, fit_file)
     if fit.build_nodes_sets() == 0:
         raise ValueError('FIT-1 has no "/image" nor "/configuration" nodes')
 
     fit.check_fit_crc32_images()
 
     # 2 - Create auto FIT with signed images, and verify it
-    util.run_and_log(cons, mkimage + ' -fauto' + b_args + s_args + " " +
-        fit_file)
+    utils.run_and_log(ubman, mkimage + ' -fauto' + b_args + s_args + " " +
+                      fit_file)
 
-    fit = SignedFitHelper(cons, fit_file)
+    fit = SignedFitHelper(ubman, fit_file)
     if fit.build_nodes_sets() == 0:
         raise ValueError('FIT-2 has no "/image" nor "/configuration" nodes')
 
     fit.check_fit_signed_images(key_name, sign_algo, verifier)
 
     # 3 - Create auto FIT with signed configs and hashed images, and verify it
-    util.run_and_log(cons, mkimage + ' -fauto-conf' + b_args + s_args + " " +
-        fit_file)
+    utils.run_and_log(ubman, mkimage + ' -fauto-conf' + b_args + s_args + " " +
+                      fit_file)
 
-    fit = SignedFitHelper(cons, fit_file)
+    fit = SignedFitHelper(ubman, fit_file)
     if fit.build_nodes_sets() == 0:
         raise ValueError('FIT-3 has no "/image" nor "/configuration" nodes')
 
diff --git a/test/py/tests/test_fit_ecdsa.py b/test/py/tests/test_fit_ecdsa.py
index cc6c0c4dc42..3e816d68eb6 100644
--- a/test/py/tests/test_fit_ecdsa.py
+++ b/test/py/tests/test_fit_ecdsa.py
@@ -12,27 +12,29 @@ This test doesn't run the sandbox. It only checks the host tool 'mkimage'
 
 import os
 import pytest
-import u_boot_utils as util
+import utils
 from Cryptodome.Hash import SHA256
 from Cryptodome.PublicKey import ECC
 from Cryptodome.Signature import DSS
 
 class SignableFitImage(object):
     """ Helper to manipulate a FIT image on disk """
-    def __init__(self, cons, file_name):
+    def __init__(self, ubman, file_name):
         self.fit = file_name
-        self.cons = cons
+        self.ubman = ubman
         self.signable_nodes = set()
 
     def __fdt_list(self, path):
-        return util.run_and_log(self.cons, f'fdtget -l {self.fit} {path}')
+        return utils.run_and_log(self.ubman, f'fdtget -l {self.fit} {path}')
 
     def __fdt_set(self, node, **prop_value):
         for prop, value in prop_value.items():
-            util.run_and_log(self.cons, f'fdtput -ts {self.fit} {node} {prop} {value}')
+            utils.run_and_log(self.ubman,
+                              f'fdtput -ts {self.fit} {node} {prop} {value}')
 
     def __fdt_get_binary(self, node, prop):
-        numbers = util.run_and_log(self.cons, f'fdtget -tbi {self.fit} {node} {prop}')
+        numbers = utils.run_and_log(self.ubman,
+                                    f'fdtget -tbi {self.fit} {node} {prop}')
 
         bignum = bytearray()
         for little_num in numbers.split():
@@ -53,7 +55,7 @@ class SignableFitImage(object):
             self.__fdt_set(f'{image}/signature', algo='sha256,ecdsa256')
 
     def sign(self, mkimage, key_file):
-        util.run_and_log(self.cons, [mkimage, '-F', self.fit, f'-G{key_file}'])
+        utils.run_and_log(self.ubman, [mkimage, '-F', self.fit, f'-G{key_file}'])
 
     def check_signatures(self, key):
         for image in self.signable_nodes:
@@ -69,23 +71,22 @@ class SignableFitImage(object):
 @pytest.mark.requiredtool('dtc')
 @pytest.mark.requiredtool('fdtget')
 @pytest.mark.requiredtool('fdtput')
-def test_fit_ecdsa(u_boot_console):
+def test_fit_ecdsa(ubman):
     """ Test that signatures generated by mkimage are legible. """
     def generate_ecdsa_key():
         return ECC.generate(curve='prime256v1')
 
     def assemble_fit_image(dest_fit, its, destdir):
         dtc_args = f'-I dts -O dtb -i {destdir}'
-        util.run_and_log(cons, [mkimage, '-D', dtc_args, '-f', its, dest_fit])
+        utils.run_and_log(ubman, [mkimage, '-D', dtc_args, '-f', its, dest_fit])
 
     def dtc(dts):
         dtb = dts.replace('.dts', '.dtb')
-        util.run_and_log(cons, f'dtc {datadir}/{dts} -O dtb -o {tempdir}/{dtb}')
+        utils.run_and_log(ubman, f'dtc {datadir}/{dts} -O dtb -o {tempdir}/{dtb}')
 
-    cons = u_boot_console
-    mkimage = cons.config.build_dir + '/tools/mkimage'
-    datadir = cons.config.source_dir + '/test/py/tests/vboot/'
-    tempdir = os.path.join(cons.config.result_dir, 'ecdsa')
+    mkimage = ubman.config.build_dir + '/tools/mkimage'
+    datadir = ubman.config.source_dir + '/test/py/tests/vboot/'
+    tempdir = os.path.join(ubman.config.result_dir, 'ecdsa')
     os.makedirs(tempdir, exist_ok=True)
     key_file = f'{tempdir}/ecdsa-test-key.pem'
     fit_file = f'{tempdir}/test.fit'
@@ -103,7 +104,7 @@ def test_fit_ecdsa(u_boot_console):
 
     assemble_fit_image(fit_file, f'{datadir}/sign-images-sha256.its', tempdir)
 
-    fit = SignableFitImage(cons, fit_file)
+    fit = SignableFitImage(ubman, fit_file)
     nodes = fit.find_signable_image_nodes()
     if len(nodes) == 0:
         raise ValueError('FIT image has no "/image" nodes with "signature"')
diff --git a/test/py/tests/test_fit_hashes.py b/test/py/tests/test_fit_hashes.py
index 4891e77ca2d..07bf0fd5211 100644
--- a/test/py/tests/test_fit_hashes.py
+++ b/test/py/tests/test_fit_hashes.py
@@ -12,7 +12,7 @@ This test doesn't run the sandbox. It only checks the host tool 'mkimage'
 
 import os
 import pytest
-import u_boot_utils as util
+import utils
 
 kernel_hashes = {
     "sha512" : "f18c1486a2c29f56360301576cdfce4dfd8e8e932d0ed8e239a1f314b8ae1d77b2a58cd7fe32e4075e69448e623ce53b0b6aa6ce5626d2c189a5beae29a68d93",
@@ -26,20 +26,21 @@ kernel_hashes = {
 
 class ReadonlyFitImage(object):
     """ Helper to manipulate a FIT image on disk """
-    def __init__(self, cons, file_name):
+    def __init__(self, ubman, file_name):
         self.fit = file_name
-        self.cons = cons
+        self.ubman = ubman
         self.hashable_nodes = set()
 
     def __fdt_list(self, path):
-        return util.run_and_log(self.cons, f'fdtget -l {self.fit} {path}')
+        return utils.run_and_log(self.ubman, f'fdtget -l {self.fit} {path}')
 
     def __fdt_get(self, node, prop):
-        val = util.run_and_log(self.cons, f'fdtget {self.fit} {node} {prop}')
+        val = utils.run_and_log(self.ubman, f'fdtget {self.fit} {node} {prop}')
         return val.rstrip('\n')
 
     def __fdt_get_sexadecimal(self, node, prop):
-        numbers = util.run_and_log(self.cons, f'fdtget -tbx {self.fit} {node} {prop}')
+        numbers = utils.run_and_log(self.ubman,
+                                    f'fdtget -tbx {self.fit} {node} {prop}')
 
         sexadecimal = ''
         for num in numbers.rstrip('\n').split(' '):
@@ -80,21 +81,21 @@ class ReadonlyFitImage(object):
 @pytest.mark.requiredtool('dtc')
 @pytest.mark.requiredtool('fdtget')
 @pytest.mark.requiredtool('fdtput')
-def test_mkimage_hashes(u_boot_console):
+def test_mkimage_hashes(ubman):
     """ Test that hashes generated by mkimage are correct. """
 
     def assemble_fit_image(dest_fit, its, destdir):
         dtc_args = f'-I dts -O dtb -i {destdir}'
-        util.run_and_log(cons, [mkimage, '-D', dtc_args, '-f', its, dest_fit])
+        utils.run_and_log(ubman, [mkimage, '-D', dtc_args, '-f', its, dest_fit])
 
     def dtc(dts):
         dtb = dts.replace('.dts', '.dtb')
-        util.run_and_log(cons, f'dtc {datadir}/{dts} -O dtb -o {tempdir}/{dtb}')
+        utils.run_and_log(ubman,
+                          f'dtc {datadir}/{dts} -O dtb -o {tempdir}/{dtb}')
 
-    cons = u_boot_console
-    mkimage = cons.config.build_dir + '/tools/mkimage'
-    datadir = cons.config.source_dir + '/test/py/tests/vboot/'
-    tempdir = os.path.join(cons.config.result_dir, 'hashes')
+    mkimage = ubman.config.build_dir + '/tools/mkimage'
+    datadir = ubman.config.source_dir + '/test/py/tests/vboot/'
+    tempdir = os.path.join(ubman.config.result_dir, 'hashes')
     os.makedirs(tempdir, exist_ok=True)
 
     fit_file = f'{tempdir}/test.fit'
@@ -106,7 +107,7 @@ def test_mkimage_hashes(u_boot_console):
 
     assemble_fit_image(fit_file, f'{datadir}/hash-images.its', tempdir)
 
-    fit = ReadonlyFitImage(cons, fit_file)
+    fit = ReadonlyFitImage(ubman, fit_file)
     nodes = fit.find_hashable_image_nodes()
     if len(nodes) == 0:
         raise ValueError('FIT image has no "/image" nodes with "hash-..."')
diff --git a/test/py/tests/test_fpga.py b/test/py/tests/test_fpga.py
index 460ff227f6f..74cd42b910e 100644
--- a/test/py/tests/test_fpga.py
+++ b/test/py/tests/test_fpga.py
@@ -8,7 +8,7 @@
 import pytest
 import re
 import random
-import u_boot_utils
+import utils
 
 """
 Note: This test relies on boardenv_* containing configuration values to define
@@ -63,8 +63,8 @@ env__fpga_under_test = {
 
 import test_net
 
-def check_dev(u_boot_console):
-    f = u_boot_console.config.env.get('env__fpga_under_test', None)
+def check_dev(ubman):
+    f = ubman.config.env.get('env__fpga_under_test', None)
     if not f:
         pytest.skip('No FPGA to test')
 
@@ -74,20 +74,20 @@ def check_dev(u_boot_console):
 
     return dev, f
 
-def load_file_from_var(u_boot_console, name):
-    dev, f = check_dev(u_boot_console)
+def load_file_from_var(ubman, name):
+    dev, f = check_dev(ubman)
 
     addr = f.get('addr', -1)
     if addr < 0:
         pytest.fail('No address specified via env__fpga_under_test')
 
-    test_net.test_net_dhcp(u_boot_console)
-    test_net.test_net_setup_static(u_boot_console)
+    test_net.test_net_dhcp(ubman)
+    test_net.test_net_setup_static(ubman)
     bit = f['%s' % (name)]
     bit_size = f['%s_size' % (name)]
 
     expected_tftp = 'Bytes transferred = %d' % bit_size
-    output = u_boot_console.run_command('tftpboot %x %s' % (addr, bit))
+    output = ubman.run_command('tftpboot %x %s' % (addr, bit))
     assert expected_tftp in output
 
     return f, dev, addr, bit, bit_size
@@ -97,158 +97,158 @@ expected_usage = 'fpga - loadable FPGA image support'
 
 @pytest.mark.xfail
 @pytest.mark.buildconfigspec('cmd_fpga')
-def test_fpga_fail(u_boot_console):
+def test_fpga_fail(ubman):
     # Test non valid fpga subcommand
     expected = 'fpga: non existing command'
-    output = u_boot_console.run_command('fpga broken 0')
+    output = ubman.run_command('fpga broken 0')
     #assert expected in output
     assert expected_usage in output
 
 @pytest.mark.buildconfigspec('cmd_fpga')
-def test_fpga_help(u_boot_console):
+def test_fpga_help(ubman):
     # Just show help
-    output = u_boot_console.run_command('fpga')
+    output = ubman.run_command('fpga')
     assert expected_usage in output
 
 
 ###### FPGA DUMP tests ######
 
 @pytest.mark.buildconfigspec('cmd_fpga')
-def test_fpga_dump(u_boot_console):
+def test_fpga_dump(ubman):
     pytest.skip('Not implemented now')
 
 @pytest.mark.buildconfigspec('cmd_fpga')
-def test_fpga_dump_variable(u_boot_console):
+def test_fpga_dump_variable(ubman):
     # Same as above but via "fpga" variable
     pytest.skip('Not implemented now')
 
 ###### FPGA INFO tests ######
 
 @pytest.mark.buildconfigspec('cmd_fpga')
-def test_fpga_info_fail(u_boot_console):
+def test_fpga_info_fail(ubman):
     # Maybe this can be skipped completely
-    dev, f = check_dev(u_boot_console)
+    dev, f = check_dev(ubman)
 
     # Multiple parameters to fpga info should fail
     expected = 'fpga: more parameters passed'
-    output = u_boot_console.run_command('fpga info 0 0')
+    output = ubman.run_command('fpga info 0 0')
     #assert expected in output
     assert expected_usage in output
 
 @pytest.mark.buildconfigspec('cmd_fpga')
-def test_fpga_info_list(u_boot_console):
+def test_fpga_info_list(ubman):
     # Maybe this can be skipped completely
-    dev, f = check_dev(u_boot_console)
+    dev, f = check_dev(ubman)
 
     # Code is design in a way that if fpga dev is not passed it should
     # return list of all fpga devices in the system
-    u_boot_console.run_command('setenv fpga')
-    output = u_boot_console.run_command('fpga info')
+    ubman.run_command('setenv fpga')
+    output = ubman.run_command('fpga info')
     assert expected_usage not in output
 
 @pytest.mark.buildconfigspec('cmd_fpga')
-def test_fpga_info(u_boot_console):
-    dev, f = check_dev(u_boot_console)
+def test_fpga_info(ubman):
+    dev, f = check_dev(ubman)
 
-    output = u_boot_console.run_command('fpga info %x' % (dev))
+    output = ubman.run_command('fpga info %x' % (dev))
     assert expected_usage not in output
 
 @pytest.mark.buildconfigspec('cmd_fpga')
-def test_fpga_info_variable(u_boot_console):
-    dev, f = check_dev(u_boot_console)
+def test_fpga_info_variable(ubman):
+    dev, f = check_dev(ubman)
 
     #
     # fpga variable is storing device number which doesn't need to be passed
     #
-    u_boot_console.run_command('setenv fpga %x' % (dev))
+    ubman.run_command('setenv fpga %x' % (dev))
 
-    output = u_boot_console.run_command('fpga info')
+    output = ubman.run_command('fpga info')
     # Variable cleanup
-    u_boot_console.run_command('setenv fpga')
+    ubman.run_command('setenv fpga')
     assert expected_usage not in output
 
 ###### FPGA LOAD tests ######
 
 @pytest.mark.buildconfigspec('cmd_fpga')
 @pytest.mark.buildconfigspec('cmd_echo')
-def test_fpga_load_fail(u_boot_console):
-    f, dev, addr, bit, bit_size = load_file_from_var(u_boot_console, 'bitstream_load')
+def test_fpga_load_fail(ubman):
+    f, dev, addr, bit, bit_size = load_file_from_var(ubman, 'bitstream_load')
 
     for cmd in ['dump', 'load', 'loadb']:
         # missing dev parameter
         expected = 'fpga: incorrect parameters passed'
-        output = u_boot_console.run_command('fpga %s %x $filesize' % (cmd, addr))
+        output = ubman.run_command('fpga %s %x $filesize' % (cmd, addr))
         #assert expected in output
         assert expected_usage in output
 
         # more parameters - 0 at the end
         expected = 'fpga: more parameters passed'
-        output = u_boot_console.run_command('fpga %s %x %x $filesize 0' % (cmd, dev, addr))
+        output = ubman.run_command('fpga %s %x %x $filesize 0' % (cmd, dev, addr))
         #assert expected in output
         assert expected_usage in output
 
         # 0 address
         expected = 'fpga: zero fpga_data address'
-        output = u_boot_console.run_command('fpga %s %x 0 $filesize' % (cmd, dev))
+        output = ubman.run_command('fpga %s %x 0 $filesize' % (cmd, dev))
         #assert expected in output
         assert expected_usage in output
 
         # 0 filesize
         expected = 'fpga: zero size'
-        output = u_boot_console.run_command('fpga %s %x %x 0' % (cmd, dev, addr))
+        output = ubman.run_command('fpga %s %x %x 0' % (cmd, dev, addr))
         #assert expected in output
         assert expected_usage in output
 
 @pytest.mark.buildconfigspec('cmd_fpga')
 @pytest.mark.buildconfigspec('cmd_echo')
-def test_fpga_load(u_boot_console):
-    f, dev, addr, bit, bit_size = load_file_from_var(u_boot_console, 'bitstream_load')
+def test_fpga_load(ubman):
+    f, dev, addr, bit, bit_size = load_file_from_var(ubman, 'bitstream_load')
 
     expected_text = 'FPGA loaded successfully'
-    output = u_boot_console.run_command('fpga load %x %x $filesize && echo %s' % (dev, addr, expected_text))
+    output = ubman.run_command('fpga load %x %x $filesize && echo %s' % (dev, addr, expected_text))
     assert expected_text in output
 
 @pytest.mark.buildconfigspec('cmd_fpga')
 @pytest.mark.buildconfigspec('cmd_fpga_loadp')
 @pytest.mark.buildconfigspec('cmd_echo')
-def test_fpga_loadp(u_boot_console):
-    f, dev, addr, bit, bit_size = load_file_from_var(u_boot_console, 'bitstream_load')
+def test_fpga_loadp(ubman):
+    f, dev, addr, bit, bit_size = load_file_from_var(ubman, 'bitstream_load')
 
     expected_text = 'FPGA loaded successfully'
-    output = u_boot_console.run_command('fpga load %x %x $filesize && echo %s' % (dev, addr, expected_text))
+    output = ubman.run_command('fpga load %x %x $filesize && echo %s' % (dev, addr, expected_text))
     assert expected_text in output
 
     # And load also partial bistream
-    f, dev, addr, bit, bit_size = load_file_from_var(u_boot_console, 'bitstream_loadp')
+    f, dev, addr, bit, bit_size = load_file_from_var(ubman, 'bitstream_loadp')
 
     expected_text = 'FPGA loaded successfully'
-    output = u_boot_console.run_command('fpga loadp %x %x $filesize && echo %s' % (dev, addr, expected_text))
+    output = ubman.run_command('fpga loadp %x %x $filesize && echo %s' % (dev, addr, expected_text))
     assert expected_text in output
 
 @pytest.mark.buildconfigspec('cmd_fpga')
 @pytest.mark.buildconfigspec('cmd_echo')
-def test_fpga_loadb(u_boot_console):
-    f, dev, addr, bit, bit_size = load_file_from_var(u_boot_console, 'bitstream_loadb')
+def test_fpga_loadb(ubman):
+    f, dev, addr, bit, bit_size = load_file_from_var(ubman, 'bitstream_loadb')
 
     expected_text = 'FPGA loaded successfully'
-    output = u_boot_console.run_command('fpga loadb %x %x $filesize && echo %s' % (dev, addr, expected_text))
+    output = ubman.run_command('fpga loadb %x %x $filesize && echo %s' % (dev, addr, expected_text))
     assert expected_text in output
 
 @pytest.mark.buildconfigspec('cmd_fpga')
 @pytest.mark.buildconfigspec('cmd_fpga_loadbp')
 @pytest.mark.buildconfigspec('cmd_echo')
-def test_fpga_loadbp(u_boot_console):
-    f, dev, addr, bit, bit_size = load_file_from_var(u_boot_console, 'bitstream_loadb')
+def test_fpga_loadbp(ubman):
+    f, dev, addr, bit, bit_size = load_file_from_var(ubman, 'bitstream_loadb')
 
     expected_text = 'FPGA loaded successfully'
-    output = u_boot_console.run_command('fpga loadb %x %x $filesize && echo %s' % (dev, addr, expected_text))
+    output = ubman.run_command('fpga loadb %x %x $filesize && echo %s' % (dev, addr, expected_text))
     assert expected_text in output
 
     # And load also partial bistream in bit format
-    f, dev, addr, bit, bit_size = load_file_from_var(u_boot_console, 'bitstream_loadbp')
+    f, dev, addr, bit, bit_size = load_file_from_var(ubman, 'bitstream_loadbp')
 
     expected_text = 'FPGA loaded successfully'
-    output = u_boot_console.run_command('fpga loadbp %x %x $filesize && echo %s' % (dev, addr, expected_text))
+    output = ubman.run_command('fpga loadbp %x %x $filesize && echo %s' % (dev, addr, expected_text))
     assert expected_text in output
 
 ###### FPGA LOADMK tests ######
@@ -257,18 +257,18 @@ def test_fpga_loadbp(u_boot_console):
 @pytest.mark.buildconfigspec('cmd_fpga_loadmk')
 @pytest.mark.buildconfigspec('cmd_echo')
 @pytest.mark.buildconfigspec('legacy_image_format')
-def test_fpga_loadmk_fail(u_boot_console):
-    f, dev, addr, bit, bit_size = load_file_from_var(u_boot_console, 'mkimage_legacy')
+def test_fpga_loadmk_fail(ubman):
+    f, dev, addr, bit, bit_size = load_file_from_var(ubman, 'mkimage_legacy')
 
-    u_boot_console.run_command('imi %x' % (addr))
+    ubman.run_command('imi %x' % (addr))
 
     # load image but pass incorrect address to show error message
     expected = 'Unknown image type'
-    output = u_boot_console.run_command('fpga loadmk %x %x' % (dev, addr + 0x10))
+    output = ubman.run_command('fpga loadmk %x %x' % (dev, addr + 0x10))
     assert expected in output
 
     # Pass more parameters then command expects - 0 at the end
-    output = u_boot_console.run_command('fpga loadmk %x %x 0' % (dev, addr))
+    output = ubman.run_command('fpga loadmk %x %x 0' % (dev, addr))
     #assert expected in output
     assert expected_usage in output
 
@@ -276,13 +276,13 @@ def test_fpga_loadmk_fail(u_boot_console):
 @pytest.mark.buildconfigspec('cmd_fpga_loadmk')
 @pytest.mark.buildconfigspec('cmd_echo')
 @pytest.mark.buildconfigspec('legacy_image_format')
-def test_fpga_loadmk_legacy(u_boot_console):
-    f, dev, addr, bit, bit_size = load_file_from_var(u_boot_console, 'mkimage_legacy')
+def test_fpga_loadmk_legacy(ubman):
+    f, dev, addr, bit, bit_size = load_file_from_var(ubman, 'mkimage_legacy')
 
-    u_boot_console.run_command('imi %x' % (addr))
+    ubman.run_command('imi %x' % (addr))
 
     expected_text = 'FPGA loaded successfully'
-    output = u_boot_console.run_command('fpga loadmk %x %x && echo %s' % (dev, addr, expected_text))
+    output = ubman.run_command('fpga loadmk %x %x && echo %s' % (dev, addr, expected_text))
     assert expected_text in output
 
 @pytest.mark.xfail
@@ -290,53 +290,53 @@ def test_fpga_loadmk_legacy(u_boot_console):
 @pytest.mark.buildconfigspec('cmd_fpga_loadmk')
 @pytest.mark.buildconfigspec('cmd_echo')
 @pytest.mark.buildconfigspec('legacy_image_format')
-def test_fpga_loadmk_legacy_variable_fpga(u_boot_console):
-    f, dev, addr, bit, bit_size = load_file_from_var(u_boot_console, 'mkimage_legacy')
+def test_fpga_loadmk_legacy_variable_fpga(ubman):
+    f, dev, addr, bit, bit_size = load_file_from_var(ubman, 'mkimage_legacy')
 
-    u_boot_console.run_command('imi %x' % (addr))
+    ubman.run_command('imi %x' % (addr))
 
-    u_boot_console.run_command('setenv fpga %x' % (dev))
+    ubman.run_command('setenv fpga %x' % (dev))
 
     # this testcase should cover case which looks like it is supported but dev pointer is broken by loading mkimage address
     expected_text = 'FPGA loaded successfully'
-    output = u_boot_console.run_command('fpga loadmk %x && echo %s' % (addr, expected_text))
-    u_boot_console.run_command('setenv fpga')
+    output = ubman.run_command('fpga loadmk %x && echo %s' % (addr, expected_text))
+    ubman.run_command('setenv fpga')
     assert expected_text in output
 
 @pytest.mark.buildconfigspec('cmd_fpga')
 @pytest.mark.buildconfigspec('cmd_fpga_loadmk')
 @pytest.mark.buildconfigspec('cmd_echo')
 @pytest.mark.buildconfigspec('legacy_image_format')
-def test_fpga_loadmk_legacy_variable_fpgadata(u_boot_console):
-    f, dev, addr, bit, bit_size = load_file_from_var(u_boot_console, 'mkimage_legacy')
+def test_fpga_loadmk_legacy_variable_fpgadata(ubman):
+    f, dev, addr, bit, bit_size = load_file_from_var(ubman, 'mkimage_legacy')
 
-    u_boot_console.run_command('imi %x' % (addr))
+    ubman.run_command('imi %x' % (addr))
 
-    u_boot_console.run_command('setenv fpgadata %x' % (addr))
+    ubman.run_command('setenv fpgadata %x' % (addr))
 
     # this testcase should cover case which looks like it is supported but dev pointer is broken by loading mkimage address
     expected_text = 'FPGA loaded successfully'
-    output = u_boot_console.run_command('fpga loadmk %x && echo %s' % (dev, expected_text))
-    u_boot_console.run_command('setenv fpgadata')
+    output = ubman.run_command('fpga loadmk %x && echo %s' % (dev, expected_text))
+    ubman.run_command('setenv fpgadata')
     assert expected_text in output
 
 @pytest.mark.buildconfigspec('cmd_fpga')
 @pytest.mark.buildconfigspec('cmd_fpga_loadmk')
 @pytest.mark.buildconfigspec('cmd_echo')
 @pytest.mark.buildconfigspec('legacy_image_format')
-def test_fpga_loadmk_legacy_variable(u_boot_console):
-    f, dev, addr, bit, bit_size = load_file_from_var(u_boot_console, 'mkimage_legacy')
+def test_fpga_loadmk_legacy_variable(ubman):
+    f, dev, addr, bit, bit_size = load_file_from_var(ubman, 'mkimage_legacy')
 
-    u_boot_console.run_command('imi %x' % (addr))
+    ubman.run_command('imi %x' % (addr))
 
-    u_boot_console.run_command('setenv fpga %x' % (dev))
-    u_boot_console.run_command('setenv fpgadata %x' % (addr))
+    ubman.run_command('setenv fpga %x' % (dev))
+    ubman.run_command('setenv fpgadata %x' % (addr))
 
     # this testcase should cover case which looks like it is supported but dev pointer is broken by loading mkimage address
     expected_text = 'FPGA loaded successfully'
-    output = u_boot_console.run_command('fpga loadmk && echo %s' % (expected_text))
-    u_boot_console.run_command('setenv fpga')
-    u_boot_console.run_command('setenv fpgadata')
+    output = ubman.run_command('fpga loadmk && echo %s' % (expected_text))
+    ubman.run_command('setenv fpga')
+    ubman.run_command('setenv fpgadata')
     assert expected_text in output
 
 @pytest.mark.buildconfigspec('cmd_fpga')
@@ -344,96 +344,96 @@ def test_fpga_loadmk_legacy_variable(u_boot_console):
 @pytest.mark.buildconfigspec('cmd_echo')
 @pytest.mark.buildconfigspec('legacy_image_format')
 @pytest.mark.buildconfigspec('gzip')
-def test_fpga_loadmk_legacy_gz(u_boot_console):
-    f, dev, addr, bit, bit_size = load_file_from_var(u_boot_console, 'mkimage_legacy_gz')
+def test_fpga_loadmk_legacy_gz(ubman):
+    f, dev, addr, bit, bit_size = load_file_from_var(ubman, 'mkimage_legacy_gz')
 
-    u_boot_console.run_command('imi %x' % (addr))
+    ubman.run_command('imi %x' % (addr))
 
     expected_text = 'FPGA loaded successfully'
-    output = u_boot_console.run_command('fpga loadmk %x %x && echo %s' % (dev, addr, expected_text))
+    output = ubman.run_command('fpga loadmk %x %x && echo %s' % (dev, addr, expected_text))
     assert expected_text in output
 
 @pytest.mark.buildconfigspec('cmd_fpga')
 @pytest.mark.buildconfigspec('cmd_fpga_loadmk')
 @pytest.mark.buildconfigspec('fit')
 @pytest.mark.buildconfigspec('cmd_echo')
-def test_fpga_loadmk_fit_external(u_boot_console):
-    f, dev, addr, bit, bit_size = load_file_from_var(u_boot_console, 'mkimage_fit_external')
+def test_fpga_loadmk_fit_external(ubman):
+    f, dev, addr, bit, bit_size = load_file_from_var(ubman, 'mkimage_fit_external')
 
-    u_boot_console.run_command('imi %x' % (addr))
+    ubman.run_command('imi %x' % (addr))
 
     expected_text = 'FPGA loaded successfully'
-    output = u_boot_console.run_command('fpga loadmk %x %x:fpga && echo %s' % (dev, addr, expected_text))
+    output = ubman.run_command('fpga loadmk %x %x:fpga && echo %s' % (dev, addr, expected_text))
     assert expected_text in output
 
 @pytest.mark.buildconfigspec('cmd_fpga')
 @pytest.mark.buildconfigspec('cmd_fpga_loadmk')
 @pytest.mark.buildconfigspec('fit')
 @pytest.mark.buildconfigspec('cmd_echo')
-def test_fpga_loadmk_fit(u_boot_console):
-    f, dev, addr, bit, bit_size = load_file_from_var(u_boot_console, 'mkimage_fit')
+def test_fpga_loadmk_fit(ubman):
+    f, dev, addr, bit, bit_size = load_file_from_var(ubman, 'mkimage_fit')
 
-    u_boot_console.run_command('imi %x' % (addr))
+    ubman.run_command('imi %x' % (addr))
 
     expected_text = 'FPGA loaded successfully'
-    output = u_boot_console.run_command('fpga loadmk %x %x:fpga && echo %s' % (dev, addr, expected_text))
+    output = ubman.run_command('fpga loadmk %x %x:fpga && echo %s' % (dev, addr, expected_text))
     assert expected_text in output
 
 @pytest.mark.buildconfigspec('cmd_fpga')
 @pytest.mark.buildconfigspec('cmd_fpga_loadmk')
 @pytest.mark.buildconfigspec('fit')
 @pytest.mark.buildconfigspec('cmd_echo')
-def test_fpga_loadmk_fit_variable_fpga(u_boot_console):
-    f, dev, addr, bit, bit_size = load_file_from_var(u_boot_console, 'mkimage_fit')
+def test_fpga_loadmk_fit_variable_fpga(ubman):
+    f, dev, addr, bit, bit_size = load_file_from_var(ubman, 'mkimage_fit')
 
-    u_boot_console.run_command('imi %x' % (addr))
+    ubman.run_command('imi %x' % (addr))
     # FIXME this should fail - broken support in past
-    u_boot_console.run_command('setenv fpga %x' % (dev))
+    ubman.run_command('setenv fpga %x' % (dev))
 
     expected_text = 'FPGA loaded successfully'
-    output = u_boot_console.run_command('fpga loadmk %x:fpga && echo %s' % (addr, expected_text))
-    u_boot_console.run_command('setenv fpga')
+    output = ubman.run_command('fpga loadmk %x:fpga && echo %s' % (addr, expected_text))
+    ubman.run_command('setenv fpga')
     assert expected_text in output
 
 @pytest.mark.buildconfigspec('cmd_fpga')
 @pytest.mark.buildconfigspec('cmd_fpga_loadmk')
 @pytest.mark.buildconfigspec('fit')
 @pytest.mark.buildconfigspec('cmd_echo')
-def test_fpga_loadmk_fit_variable_fpgadata(u_boot_console):
-    f, dev, addr, bit, bit_size = load_file_from_var(u_boot_console, 'mkimage_fit')
+def test_fpga_loadmk_fit_variable_fpgadata(ubman):
+    f, dev, addr, bit, bit_size = load_file_from_var(ubman, 'mkimage_fit')
 
-    u_boot_console.run_command('imi %x' % (addr))
+    ubman.run_command('imi %x' % (addr))
     # FIXME this should fail - broken support in past
-    u_boot_console.run_command('setenv fpgadata %x:fpga' % (addr))
+    ubman.run_command('setenv fpgadata %x:fpga' % (addr))
 
     expected_text = 'FPGA loaded successfully'
-    output = u_boot_console.run_command('fpga loadmk %x && echo %s' % (dev, expected_text))
-    u_boot_console.run_command('setenv fpgadata')
+    output = ubman.run_command('fpga loadmk %x && echo %s' % (dev, expected_text))
+    ubman.run_command('setenv fpgadata')
     assert expected_text in output
 
 @pytest.mark.buildconfigspec('cmd_fpga')
 @pytest.mark.buildconfigspec('cmd_fpga_loadmk')
 @pytest.mark.buildconfigspec('fit')
 @pytest.mark.buildconfigspec('cmd_echo')
-def test_fpga_loadmk_fit_variable(u_boot_console):
-    f, dev, addr, bit, bit_size = load_file_from_var(u_boot_console, 'mkimage_fit')
+def test_fpga_loadmk_fit_variable(ubman):
+    f, dev, addr, bit, bit_size = load_file_from_var(ubman, 'mkimage_fit')
 
-    u_boot_console.run_command('imi %x' % (addr))
+    ubman.run_command('imi %x' % (addr))
 
-    u_boot_console.run_command('setenv fpga %x' % (dev))
-    u_boot_console.run_command('setenv fpgadata %x:fpga' % (addr))
+    ubman.run_command('setenv fpga %x' % (dev))
+    ubman.run_command('setenv fpgadata %x:fpga' % (addr))
 
     expected_text = 'FPGA loaded successfully'
-    output = u_boot_console.run_command('fpga loadmk && echo %s' % (expected_text))
-    u_boot_console.run_command('setenv fpga')
-    u_boot_console.run_command('setenv fpgadata')
+    output = ubman.run_command('fpga loadmk && echo %s' % (expected_text))
+    ubman.run_command('setenv fpga')
+    ubman.run_command('setenv fpgadata')
     assert expected_text in output
 
 ###### FPGA LOAD tests ######
 
 @pytest.mark.buildconfigspec('cmd_fpga')
-def test_fpga_loadfs_fail(u_boot_console):
-    dev, f = check_dev(u_boot_console)
+def test_fpga_loadfs_fail(ubman):
+    dev, f = check_dev(ubman)
 
     addr = f.get('addr', -1)
     if addr < 0:
@@ -445,49 +445,49 @@ def test_fpga_loadfs_fail(u_boot_console):
 
     # less params - dev number removed
     expected = 'fpga: incorrect parameters passed'
-    output = u_boot_console.run_command('fpga loadfs %x %x %x %s' % (addr, bit_size, block_size, bit))
+    output = ubman.run_command('fpga loadfs %x %x %x %s' % (addr, bit_size, block_size, bit))
     #assert expected in output
     assert expected_usage in output
 
     # one more param - 0 at the end
     # This is the longest command that's why there is no message from cmd/fpga.c
-    output = u_boot_console.run_command('fpga loadfs %x %x %x %x %s 0' % (dev, addr, bit_size, block_size, bit))
+    output = ubman.run_command('fpga loadfs %x %x %x %x %s 0' % (dev, addr, bit_size, block_size, bit))
     assert expected_usage in output
 
     # zero address 0
     expected = 'fpga: zero fpga_data address'
-    output = u_boot_console.run_command('fpga loadfs %x %x %x %x %s' % (dev, 0, bit_size, block_size, bit))
+    output = ubman.run_command('fpga loadfs %x %x %x %x %s' % (dev, 0, bit_size, block_size, bit))
     #assert expected in output
     assert expected_usage in output
 
     # bit_size 0
     expected = 'fpga: zero size'
-    output = u_boot_console.run_command('fpga loadfs %x %x %x %x %s' % (dev, addr, 0, block_size, bit))
+    output = ubman.run_command('fpga loadfs %x %x %x %x %s' % (dev, addr, 0, block_size, bit))
     #assert expected in output
     assert expected_usage in output
 
     # block size 0
     # FIXME this should pass but it failing too
-    output = u_boot_console.run_command('fpga loadfs %x %x %x %x %s' % (dev, addr, bit_size, 0, bit))
+    output = ubman.run_command('fpga loadfs %x %x %x %x %s' % (dev, addr, bit_size, 0, bit))
     assert expected_usage in output
 
     # non existing bitstream name
     expected = 'Unable to read file noname'
-    output = u_boot_console.run_command('fpga loadfs %x %x %x %x mmc 0 noname' % (dev, addr, bit_size, block_size))
+    output = ubman.run_command('fpga loadfs %x %x %x %x mmc 0 noname' % (dev, addr, bit_size, block_size))
     assert expected in output
     assert expected_usage in output
 
     # -1 dev number
     expected = 'fpga_fsload: Invalid device number -1'
-    output = u_boot_console.run_command('fpga loadfs %d %x %x %x mmc 0 noname' % (-1, addr, bit_size, block_size))
+    output = ubman.run_command('fpga loadfs %d %x %x %x mmc 0 noname' % (-1, addr, bit_size, block_size))
     assert expected in output
     assert expected_usage in output
 
 
 @pytest.mark.buildconfigspec('cmd_fpga')
 @pytest.mark.buildconfigspec('cmd_echo')
-def test_fpga_loadfs(u_boot_console):
-    dev, f = check_dev(u_boot_console)
+def test_fpga_loadfs(ubman):
+    dev, f = check_dev(ubman)
 
     addr = f.get('addr', -1)
     if addr < 0:
@@ -499,7 +499,7 @@ def test_fpga_loadfs(u_boot_console):
 
     # This should be done better
     expected_text = 'FPGA loaded successfully'
-    output = u_boot_console.run_command('fpga loadfs %x %x %x %x %s && echo %s' % (dev, addr, bit_size, block_size, bit, expected_text))
+    output = ubman.run_command('fpga loadfs %x %x %x %x %s && echo %s' % (dev, addr, bit_size, block_size, bit, expected_text))
     assert expected_text in output
 
 @pytest.mark.buildconfigspec('cmd_fpga')
@@ -507,26 +507,26 @@ def test_fpga_loadfs(u_boot_console):
 @pytest.mark.buildconfigspec('cmd_net')
 @pytest.mark.buildconfigspec('cmd_dhcp')
 @pytest.mark.buildconfigspec('net')
-def test_fpga_secure_bit_auth(u_boot_console):
+def test_fpga_secure_bit_auth(ubman):
 
-    test_net.test_net_dhcp(u_boot_console)
-    test_net.test_net_setup_static(u_boot_console)
+    test_net.test_net_dhcp(ubman)
+    test_net.test_net_setup_static(ubman)
 
-    f = u_boot_console.config.env.get('env__fpga_secure_readable_file', None)
+    f = ubman.config.env.get('env__fpga_secure_readable_file', None)
     if not f:
         pytest.skip('No TFTP readable file to read')
 
     addr = f.get('addr', None)
     if not addr:
-      addr = u_boot_utils.find_ram_base(u_boot_console)
+      addr = utils.find_ram_base(ubman)
 
     expected_tftp = 'Bytes transferred = '
     fn = f['fn']
-    output = u_boot_console.run_command('tftpboot %x %s' % (addr, fn))
+    output = ubman.run_command('tftpboot %x %s' % (addr, fn))
     assert expected_tftp in output
 
     expected_zynqmpsecure = 'Bitstream successfully loaded'
-    output = u_boot_console.run_command('fpga loads 0 %x $filesize 0 2' % (addr))
+    output = ubman.run_command('fpga loads 0 %x $filesize 0 2' % (addr))
     assert expected_zynqmpsecure in output
 
 
@@ -535,31 +535,31 @@ def test_fpga_secure_bit_auth(u_boot_console):
 @pytest.mark.buildconfigspec('cmd_net')
 @pytest.mark.buildconfigspec('cmd_dhcp')
 @pytest.mark.buildconfigspec('net')
-def test_fpga_secure_bit_img_auth_kup(u_boot_console):
+def test_fpga_secure_bit_img_auth_kup(ubman):
 
-    test_net.test_net_dhcp(u_boot_console)
-    test_net.test_net_setup_static(u_boot_console)
+    test_net.test_net_dhcp(ubman)
+    test_net.test_net_setup_static(ubman)
 
-    f = u_boot_console.config.env.get('env__fpga_secure_readable_file', None)
+    f = ubman.config.env.get('env__fpga_secure_readable_file', None)
     if not f:
         pytest.skip('No TFTP readable file to read')
 
     keyaddr = f.get('keyaddr', None)
     if not keyaddr:
-      addr = u_boot_utils.find_ram_base(u_boot_console)
+      addr = utils.find_ram_base(ubman)
     expected_tftp = 'Bytes transferred = '
     keyfn = f['keyfn']
-    output = u_boot_console.run_command('tftpboot %x %s' % (keyaddr, keyfn))
+    output = ubman.run_command('tftpboot %x %s' % (keyaddr, keyfn))
     assert expected_tftp in output
 
     addr = f.get('addr', None)
     if not addr:
-      addr = u_boot_utils.find_ram_base(u_boot_console)
+      addr = utils.find_ram_base(ubman)
     expected_tftp = 'Bytes transferred = '
     fn = f['enckupfn']
-    output = u_boot_console.run_command('tftpboot %x %s' % (addr, fn))
+    output = ubman.run_command('tftpboot %x %s' % (addr, fn))
     assert expected_tftp in output
 
     expected_zynqmpsecure = 'Bitstream successfully loaded'
-    output = u_boot_console.run_command('fpga loads 0 %x $filesize 0 1 %x' % (addr, keyaddr))
+    output = ubman.run_command('fpga loads 0 %x $filesize 0 1 %x' % (addr, keyaddr))
     assert expected_zynqmpsecure in output
diff --git a/test/py/tests/test_fs/conftest.py b/test/py/tests/test_fs/conftest.py
index af2adaf1645..c73fb4abbcb 100644
--- a/test/py/tests/test_fs/conftest.py
+++ b/test/py/tests/test_fs/conftest.py
@@ -8,16 +8,16 @@ import pytest
 import re
 from subprocess import call, check_call, check_output, CalledProcessError
 from fstest_defs import *
-import u_boot_utils as util
 # pylint: disable=E0611
 from tests import fs_helper
 
-supported_fs_basic = ['fat16', 'fat32', 'ext4']
-supported_fs_ext = ['fat12', 'fat16', 'fat32']
+supported_fs_basic = ['fat16', 'fat32', 'exfat', 'ext4', 'fs_generic']
+supported_fs_ext = ['fat12', 'fat16', 'fat32', 'exfat', 'fs_generic']
 supported_fs_fat = ['fat12', 'fat16']
-supported_fs_mkdir = ['fat12', 'fat16', 'fat32']
-supported_fs_unlink = ['fat12', 'fat16', 'fat32']
+supported_fs_mkdir = ['fat12', 'fat16', 'fat32', 'exfat', 'fs_generic']
+supported_fs_unlink = ['fat12', 'fat16', 'fat32', 'exfat', 'fs_generic']
 supported_fs_symlink = ['ext4']
+supported_fs_rename = ['fat12', 'fat16', 'fat32']
 
 #
 # Filesystem test specific setup
@@ -55,6 +55,7 @@ def pytest_configure(config):
     global supported_fs_mkdir
     global supported_fs_unlink
     global supported_fs_symlink
+    global supported_fs_rename
 
     def intersect(listA, listB):
         return  [x for x in listA if x in listB]
@@ -68,6 +69,7 @@ def pytest_configure(config):
         supported_fs_mkdir =  intersect(supported_fs, supported_fs_mkdir)
         supported_fs_unlink =  intersect(supported_fs, supported_fs_unlink)
         supported_fs_symlink =  intersect(supported_fs, supported_fs_symlink)
+        supported_fs_rename =  intersect(supported_fs, supported_fs_rename)
 
 def pytest_generate_tests(metafunc):
     """Parametrize fixtures, fs_obj_xxx
@@ -99,10 +101,29 @@ def pytest_generate_tests(metafunc):
     if 'fs_obj_symlink' in metafunc.fixturenames:
         metafunc.parametrize('fs_obj_symlink', supported_fs_symlink,
             indirect=True, scope='module')
+    if 'fs_obj_rename' in metafunc.fixturenames:
+        metafunc.parametrize('fs_obj_rename', supported_fs_rename,
+            indirect=True, scope='module')
 
 #
 # Helper functions
 #
+def fstype_to_prefix(fs_type):
+    """Convert a file system type to an U-Boot command prefix
+
+    Args:
+        fs_type: File system type.
+
+    Return:
+        A corresponding command prefix for file system type.
+    """
+    if fs_type == 'fs_generic' or fs_type == 'exfat':
+        return ''
+    elif re.match('fat', fs_type):
+        return 'fat'
+    else:
+        return fs_type
+
 def fstype_to_ubname(fs_type):
     """Convert a file system type to an U-Boot specific string
 
@@ -134,8 +155,12 @@ def check_ubconfig(config, fs_type):
     Return:
         Nothing.
     """
-    if not config.buildconfig.get('config_cmd_%s' % fs_type, None):
+    if fs_type == 'exfat' and not config.buildconfig.get('config_fs_%s' % fs_type, None):
+        pytest.skip('.config feature "FS_%s" not enabled' % fs_type.upper())
+    if fs_type != 'exfat' and not config.buildconfig.get('config_cmd_%s' % fs_type, None):
         pytest.skip('.config feature "CMD_%s" not enabled' % fs_type.upper())
+    if fs_type == 'fs_generic' or fs_type == 'exfat':
+        return
     if not config.buildconfig.get('config_%s_write' % fs_type, None):
         pytest.skip('.config feature "%s_WRITE" not enabled'
         % fs_type.upper())
@@ -173,6 +198,8 @@ def fs_obj_basic(request, u_boot_config):
         volume file name and  a list of MD5 hashes.
     """
     fs_type = request.param
+    fs_cmd_prefix = fstype_to_prefix(fs_type)
+    fs_cmd_write = 'save' if fs_type == 'fs_generic' or fs_type == 'exfat' else 'write'
     fs_img = ''
 
     fs_ubtype = fstype_to_ubname(fs_type)
@@ -262,7 +289,7 @@ def fs_obj_basic(request, u_boot_config):
         pytest.skip('Setup failed for filesystem: ' + fs_type + '. {}'.format(err))
         return
     else:
-        yield [fs_ubtype, fs_img, md5val]
+        yield [fs_ubtype, fs_cmd_prefix, fs_cmd_write, fs_img, md5val]
     finally:
         call('rm -rf %s' % scratch_dir, shell=True)
         call('rm -f %s' % fs_img, shell=True)
@@ -283,6 +310,8 @@ def fs_obj_ext(request, u_boot_config):
         volume file name and  a list of MD5 hashes.
     """
     fs_type = request.param
+    fs_cmd_prefix = fstype_to_prefix(fs_type)
+    fs_cmd_write = 'save' if fs_type == 'fs_generic' or fs_type == 'exfat' else 'write'
     fs_img = ''
 
     fs_ubtype = fstype_to_ubname(fs_type)
@@ -352,7 +381,7 @@ def fs_obj_ext(request, u_boot_config):
         pytest.skip('Setup failed for filesystem: ' + fs_type)
         return
     else:
-        yield [fs_ubtype, fs_img, md5val]
+        yield [fs_ubtype, fs_cmd_prefix, fs_cmd_write, fs_img, md5val]
     finally:
         call('rm -rf %s' % scratch_dir, shell=True)
         call('rm -f %s' % fs_img, shell=True)
@@ -373,6 +402,7 @@ def fs_obj_mkdir(request, u_boot_config):
         volume file name.
     """
     fs_type = request.param
+    fs_cmd_prefix = fstype_to_prefix(fs_type)
     fs_img = ''
 
     fs_ubtype = fstype_to_ubname(fs_type)
@@ -385,7 +415,7 @@ def fs_obj_mkdir(request, u_boot_config):
         pytest.skip('Setup failed for filesystem: ' + fs_type)
         return
     else:
-        yield [fs_ubtype, fs_img]
+        yield [fs_ubtype, fs_cmd_prefix, fs_img]
     call('rm -f %s' % fs_img, shell=True)
 
 #
@@ -404,6 +434,7 @@ def fs_obj_unlink(request, u_boot_config):
         volume file name.
     """
     fs_type = request.param
+    fs_cmd_prefix = fstype_to_prefix(fs_type)
     fs_img = ''
 
     fs_ubtype = fstype_to_ubname(fs_type)
@@ -451,7 +482,7 @@ def fs_obj_unlink(request, u_boot_config):
         pytest.skip('Setup failed for filesystem: ' + fs_type)
         return
     else:
-        yield [fs_ubtype, fs_img]
+        yield [fs_ubtype, fs_cmd_prefix, fs_img]
     finally:
         call('rm -rf %s' % scratch_dir, shell=True)
         call('rm -f %s' % fs_img, shell=True)
@@ -528,6 +559,121 @@ def fs_obj_symlink(request, u_boot_config):
         call('rm -f %s' % fs_img, shell=True)
 
 #
+# Fixture for rename test
+#
+@pytest.fixture()
+def fs_obj_rename(request, u_boot_config):
+    """Set up a file system to be used in rename tests.
+
+    Args:
+        request: Pytest request object.
+        u_boot_config: U-Boot configuration.
+
+    Return:
+        A fixture for rename tests, i.e. a triplet of file system type,
+        volume file name, and dictionary of test identifier and md5val.
+    """
+    def new_rand_file(path):
+        check_call('dd if=/dev/urandom of=%s bs=1K count=1' % path, shell=True)
+
+    def file_hash(path):
+        out = check_output(
+            'dd if=%s bs=1K skip=0 count=1 2> /dev/null | md5sum' % path,
+            shell=True
+        )
+        return out.decode().split()[0]
+
+    fs_type = request.param
+    fs_img = ''
+
+    fs_ubtype = fstype_to_ubname(fs_type)
+    check_ubconfig(u_boot_config, fs_ubtype)
+
+    mount_dir = u_boot_config.persistent_data_dir + '/scratch'
+
+    try:
+        check_call('mkdir -p %s' % mount_dir, shell=True)
+    except CalledProcessError as err:
+        pytest.skip('Preparing mount folder failed for filesystem: ' + fs_type + '. {}'.format(err))
+        call('rm -f %s' % fs_img, shell=True)
+        return
+
+    try:
+        md5val = {}
+        # Test Case 1
+        check_call('mkdir %s/test1' % mount_dir, shell=True)
+        new_rand_file('%s/test1/file1' % mount_dir)
+        md5val['test1'] = file_hash('%s/test1/file1' % mount_dir)
+
+        # Test Case 2
+        check_call('mkdir %s/test2' % mount_dir, shell=True)
+        new_rand_file('%s/test2/file1' % mount_dir)
+        new_rand_file('%s/test2/file_exist' % mount_dir)
+        md5val['test2'] = file_hash('%s/test2/file1' % mount_dir)
+
+        # Test Case 3
+        check_call('mkdir -p %s/test3/dir1' % mount_dir, shell=True)
+        new_rand_file('%s/test3/dir1/file1' % mount_dir)
+        md5val['test3'] = file_hash('%s/test3/dir1/file1' % mount_dir)
+
+        # Test Case 4
+        check_call('mkdir -p %s/test4/dir1' % mount_dir, shell=True)
+        check_call('mkdir -p %s/test4/dir2/dir1' % mount_dir, shell=True)
+        new_rand_file('%s/test4/dir1/file1' % mount_dir)
+        md5val['test4'] = file_hash('%s/test4/dir1/file1' % mount_dir)
+
+        # Test Case 5
+        check_call('mkdir -p %s/test5/dir1' % mount_dir, shell=True)
+        new_rand_file('%s/test5/file2' % mount_dir)
+        md5val['test5'] = file_hash('%s/test5/file2' % mount_dir)
+
+        # Test Case 6
+        check_call('mkdir -p %s/test6/dir2/existing' % mount_dir, shell=True)
+        new_rand_file('%s/test6/existing' % mount_dir)
+        md5val['test6'] = file_hash('%s/test6/existing' % mount_dir)
+
+        # Test Case 7
+        check_call('mkdir -p %s/test7/dir1' % mount_dir, shell=True)
+        check_call('mkdir -p %s/test7/dir2/dir1' % mount_dir, shell=True)
+        new_rand_file('%s/test7/dir2/dir1/file1' % mount_dir)
+        md5val['test7'] = file_hash('%s/test7/dir2/dir1/file1' % mount_dir)
+
+        # Test Case 8
+        check_call('mkdir -p %s/test8/dir1' % mount_dir, shell=True)
+        new_rand_file('%s/test8/dir1/file1' % mount_dir)
+        md5val['test8'] = file_hash('%s/test8/dir1/file1' % mount_dir)
+
+        # Test Case 9
+        check_call('mkdir -p %s/test9/dir1/nested/inner' % mount_dir, shell=True)
+        new_rand_file('%s/test9/dir1/nested/inner/file1' % mount_dir)
+
+        # Test Case 10
+        check_call('mkdir -p %s/test10' % mount_dir, shell=True)
+        new_rand_file('%s/test10/file1' % mount_dir)
+        md5val['test10'] = file_hash('%s/test10/file1' % mount_dir)
+
+        # Test Case 11
+        check_call('mkdir -p %s/test11/dir1' % mount_dir, shell=True)
+        new_rand_file('%s/test11/dir1/file1' % mount_dir)
+        md5val['test11'] = file_hash('%s/test11/dir1/file1' % mount_dir)
+
+        try:
+            # 128MiB volume
+            fs_img = fs_helper.mk_fs(u_boot_config, fs_type, 0x8000000, '128MB', mount_dir)
+        except CalledProcessError as err:
+            pytest.skip('Creating failed for filesystem: ' + fs_type + '. {}'.format(err))
+            return
+
+    except CalledProcessError:
+        pytest.skip('Setup failed for filesystem: ' + fs_type)
+        return
+    else:
+        yield [fs_ubtype, fs_img, md5val]
+    finally:
+        call('rm -rf %s' % mount_dir, shell=True)
+        call('rm -f %s' % fs_img, shell=True)
+
+#
 # Fixture for fat test
 #
 @pytest.fixture()
diff --git a/test/py/tests/test_fs/fstest_helpers.py b/test/py/tests/test_fs/fstest_helpers.py
index faec2982489..d25326ee993 100644
--- a/test/py/tests/test_fs/fstest_helpers.py
+++ b/test/py/tests/test_fs/fstest_helpers.py
@@ -9,5 +9,9 @@ def assert_fs_integrity(fs_type, fs_img):
     try:
         if fs_type == 'ext4':
             check_call('fsck.ext4 -n -f %s' % fs_img, shell=True)
+        elif fs_type == 'exfat':
+            check_call('fsck.exfat -n %s' % fs_img, shell=True)
+        elif fs_type in ['fat12', 'fat16', 'fat32']:
+            check_call('fsck.fat -n %s' % fs_img, shell=True)
     except CalledProcessError:
         raise
diff --git a/test/py/tests/test_fs/test_basic.py b/test/py/tests/test_fs/test_basic.py
index b5f4704172a..64a3b50f52a 100644
--- a/test/py/tests/test_fs/test_basic.py
+++ b/test/py/tests/test_fs/test_basic.py
@@ -16,273 +16,274 @@ from fstest_helpers import assert_fs_integrity
 @pytest.mark.boardspec('sandbox')
 @pytest.mark.slow
 class TestFsBasic(object):
-    def test_fs1(self, u_boot_console, fs_obj_basic):
+    def test_fs1(self, ubman, fs_obj_basic):
         """
         Test Case 1 - ls command, listing a root directory and invalid directory
         """
-        fs_type,fs_img,md5val = fs_obj_basic
-        with u_boot_console.log.section('Test Case 1a - ls'):
+        fs_type,fs_cmd_prefix,fs_cmd_write,fs_img,md5val = fs_obj_basic
+        with ubman.log.section('Test Case 1a - ls'):
             # Test Case 1 - ls
-            output = u_boot_console.run_command_list([
+            output = ubman.run_command_list([
                 'host bind 0 %s' % fs_img,
-                '%sls host 0:0' % fs_type])
+                '%sls host 0:0' % fs_cmd_prefix])
             assert(re.search('2621440000 *%s' % BIG_FILE, ''.join(output)))
             assert(re.search('1048576 *%s' % SMALL_FILE, ''.join(output)))
 
-        with u_boot_console.log.section('Test Case 1b - ls (invalid dir)'):
+        with ubman.log.section('Test Case 1b - ls (invalid dir)'):
             # In addition, test with a nonexistent directory to see if we crash.
-            output = u_boot_console.run_command(
-                '%sls host 0:0 invalid_d' % fs_type)
+            output = ubman.run_command(
+                '%sls host 0:0 invalid_d' % fs_cmd_prefix)
             assert('' == output)
 
-    def test_fs2(self, u_boot_console, fs_obj_basic):
+    def test_fs2(self, ubman, fs_obj_basic):
         """
         Test Case 2 - size command for a small file
         """
-        fs_type,fs_img,md5val = fs_obj_basic
-        with u_boot_console.log.section('Test Case 2a - size (small)'):
+        fs_type,fs_cmd_prefix,fs_cmd_write,fs_img,md5val = fs_obj_basic
+        with ubman.log.section('Test Case 2a - size (small)'):
             # 1MB is 0x0010 0000
             # Test Case 2a - size of small file
-            output = u_boot_console.run_command_list([
+            output = ubman.run_command_list([
                 'host bind 0 %s' % fs_img,
-                '%ssize host 0:0 /%s' % (fs_type, SMALL_FILE),
+                '%ssize host 0:0 /%s' % (fs_cmd_prefix, SMALL_FILE),
                 'printenv filesize',
                 'setenv filesize'])
             assert('filesize=100000' in ''.join(output))
 
-        with u_boot_console.log.section('Test Case 2b - size (/../<file>)'):
+        with ubman.log.section('Test Case 2b - size (/../<file>)'):
             # Test Case 2b - size of small file via a path using '..'
-            output = u_boot_console.run_command_list([
-                '%ssize host 0:0 /SUBDIR/../%s' % (fs_type, SMALL_FILE),
+            output = ubman.run_command_list([
+                '%ssize host 0:0 /SUBDIR/../%s' % (fs_cmd_prefix, SMALL_FILE),
                 'printenv filesize',
                 'setenv filesize'])
             assert('filesize=100000' in ''.join(output))
 
-    def test_fs3(self, u_boot_console, fs_obj_basic):
+    def test_fs3(self, ubman, fs_obj_basic):
         """
         Test Case 3 - size command for a large file
         """
-        fs_type,fs_img,md5val = fs_obj_basic
-        with u_boot_console.log.section('Test Case 3 - size (large)'):
+        fs_type,fs_cmd_prefix,fs_cmd_write,fs_img,md5val = fs_obj_basic
+        with ubman.log.section('Test Case 3 - size (large)'):
             # 2.5GB (1024*1024*2500) is 0x9C40 0000
             # Test Case 3 - size of big file
-            output = u_boot_console.run_command_list([
+            output = ubman.run_command_list([
                 'host bind 0 %s' % fs_img,
-                '%ssize host 0:0 /%s' % (fs_type, BIG_FILE),
+                '%ssize host 0:0 /%s' % (fs_cmd_prefix, BIG_FILE),
                 'printenv filesize',
                 'setenv filesize'])
             assert('filesize=9c400000' in ''.join(output))
 
-    def test_fs4(self, u_boot_console, fs_obj_basic):
+    def test_fs4(self, ubman, fs_obj_basic):
         """
         Test Case 4 - load a small file, 1MB
         """
-        fs_type,fs_img,md5val = fs_obj_basic
-        with u_boot_console.log.section('Test Case 4 - load (small)'):
+        fs_type,fs_cmd_prefix,fs_cmd_write,fs_img,md5val = fs_obj_basic
+        with ubman.log.section('Test Case 4 - load (small)'):
             # Test Case 4a - Read full 1MB of small file
-            output = u_boot_console.run_command_list([
+            output = ubman.run_command_list([
                 'host bind 0 %s' % fs_img,
-                '%sload host 0:0 %x /%s' % (fs_type, ADDR, SMALL_FILE),
+                '%sload host 0:0 %x /%s' % (fs_cmd_prefix, ADDR, SMALL_FILE),
                 'printenv filesize'])
             assert('filesize=100000' in ''.join(output))
 
             # Test Case 4b - Read full 1MB of small file
-            output = u_boot_console.run_command_list([
+            output = ubman.run_command_list([
                 'md5sum %x $filesize' % ADDR,
                 'setenv filesize'])
             assert(md5val[0] in ''.join(output))
 
-    def test_fs5(self, u_boot_console, fs_obj_basic):
+    def test_fs5(self, ubman, fs_obj_basic):
         """
         Test Case 5 - load, reading first 1MB of 3GB file
         """
-        fs_type,fs_img,md5val = fs_obj_basic
-        with u_boot_console.log.section('Test Case 5 - load (first 1MB)'):
+        fs_type,fs_cmd_prefix,fs_cmd_write,fs_img,md5val = fs_obj_basic
+        with ubman.log.section('Test Case 5 - load (first 1MB)'):
             # Test Case 5a - First 1MB of big file
-            output = u_boot_console.run_command_list([
+            output = ubman.run_command_list([
                 'host bind 0 %s' % fs_img,
-                '%sload host 0:0 %x /%s %x 0x0' % (fs_type, ADDR, BIG_FILE, LENGTH),
+                '%sload host 0:0 %x /%s %x 0x0' % (fs_cmd_prefix, ADDR, BIG_FILE, LENGTH),
                 'printenv filesize'])
             assert('filesize=100000' in ''.join(output))
 
             # Test Case 5b - First 1MB of big file
-            output = u_boot_console.run_command_list([
+            output = ubman.run_command_list([
                 'md5sum %x $filesize' % ADDR,
                 'setenv filesize'])
             assert(md5val[1] in ''.join(output))
 
-    def test_fs6(self, u_boot_console, fs_obj_basic):
+    def test_fs6(self, ubman, fs_obj_basic):
         """
         Test Case 6 - load, reading last 1MB of 3GB file
         """
-        fs_type,fs_img,md5val = fs_obj_basic
-        with u_boot_console.log.section('Test Case 6 - load (last 1MB)'):
+        fs_type,fs_cmd_prefix,fs_cmd_write,fs_img,md5val = fs_obj_basic
+        with ubman.log.section('Test Case 6 - load (last 1MB)'):
             # fails for ext as no offset support
             # Test Case 6a - Last 1MB of big file
-            output = u_boot_console.run_command_list([
+            output = ubman.run_command_list([
                 'host bind 0 %s' % fs_img,
                 '%sload host 0:0 %x /%s %x 0x9c300000'
-                    % (fs_type, ADDR, BIG_FILE, LENGTH),
+                    % (fs_cmd_prefix, ADDR, BIG_FILE, LENGTH),
                 'printenv filesize'])
             assert('filesize=100000' in ''.join(output))
 
             # Test Case 6b - Last 1MB of big file
-            output = u_boot_console.run_command_list([
+            output = ubman.run_command_list([
                 'md5sum %x $filesize' % ADDR,
                 'setenv filesize'])
             assert(md5val[2] in ''.join(output))
 
-    def test_fs7(self, u_boot_console, fs_obj_basic):
+    def test_fs7(self, ubman, fs_obj_basic):
         """
         Test Case 7 - load, 1MB from the last 1MB in 2GB
         """
-        fs_type,fs_img,md5val = fs_obj_basic
-        with u_boot_console.log.section('Test Case 7 - load (last 1MB in 2GB)'):
+        fs_type,fs_cmd_prefix,fs_cmd_write,fs_img,md5val = fs_obj_basic
+        with ubman.log.section('Test Case 7 - load (last 1MB in 2GB)'):
             # fails for ext as no offset support
             # Test Case 7a - One from the last 1MB chunk of 2GB
-            output = u_boot_console.run_command_list([
+            output = ubman.run_command_list([
                 'host bind 0 %s' % fs_img,
                 '%sload host 0:0 %x /%s %x 0x7ff00000'
-                    % (fs_type, ADDR, BIG_FILE, LENGTH),
+                    % (fs_cmd_prefix, ADDR, BIG_FILE, LENGTH),
                 'printenv filesize'])
             assert('filesize=100000' in ''.join(output))
 
             # Test Case 7b - One from the last 1MB chunk of 2GB
-            output = u_boot_console.run_command_list([
+            output = ubman.run_command_list([
                 'md5sum %x $filesize' % ADDR,
                 'setenv filesize'])
             assert(md5val[3] in ''.join(output))
 
-    def test_fs8(self, u_boot_console, fs_obj_basic):
+    def test_fs8(self, ubman, fs_obj_basic):
         """
         Test Case 8 - load, reading first 1MB in 2GB
         """
-        fs_type,fs_img,md5val = fs_obj_basic
-        with u_boot_console.log.section('Test Case 8 - load (first 1MB in 2GB)'):
+        fs_type,fs_cmd_prefix,fs_cmd_write,fs_img,md5val = fs_obj_basic
+        with ubman.log.section('Test Case 8 - load (first 1MB in 2GB)'):
             # fails for ext as no offset support
             # Test Case 8a - One from the start 1MB chunk from 2GB
-            output = u_boot_console.run_command_list([
+            output = ubman.run_command_list([
                 'host bind 0 %s' % fs_img,
                 '%sload host 0:0 %x /%s %x 0x80000000'
-                    % (fs_type, ADDR, BIG_FILE, LENGTH),
+                    % (fs_cmd_prefix, ADDR, BIG_FILE, LENGTH),
                 'printenv filesize'])
             assert('filesize=100000' in ''.join(output))
 
             # Test Case 8b - One from the start 1MB chunk from 2GB
-            output = u_boot_console.run_command_list([
+            output = ubman.run_command_list([
                 'md5sum %x $filesize' % ADDR,
                 'setenv filesize'])
             assert(md5val[4] in ''.join(output))
 
-    def test_fs9(self, u_boot_console, fs_obj_basic):
+    def test_fs9(self, ubman, fs_obj_basic):
         """
         Test Case 9 - load, 1MB crossing 2GB boundary
         """
-        fs_type,fs_img,md5val = fs_obj_basic
-        with u_boot_console.log.section('Test Case 9 - load (crossing 2GB boundary)'):
+        fs_type,fs_cmd_prefix,fs_cmd_write,fs_img,md5val = fs_obj_basic
+        with ubman.log.section('Test Case 9 - load (crossing 2GB boundary)'):
             # fails for ext as no offset support
             # Test Case 9a - One 1MB chunk crossing the 2GB boundary
-            output = u_boot_console.run_command_list([
+            output = ubman.run_command_list([
                 'host bind 0 %s' % fs_img,
                 '%sload host 0:0 %x /%s %x 0x7ff80000'
-                    % (fs_type, ADDR, BIG_FILE, LENGTH),
+                    % (fs_cmd_prefix, ADDR, BIG_FILE, LENGTH),
                 'printenv filesize'])
             assert('filesize=100000' in ''.join(output))
 
             # Test Case 9b - One 1MB chunk crossing the 2GB boundary
-            output = u_boot_console.run_command_list([
+            output = ubman.run_command_list([
                 'md5sum %x $filesize' % ADDR,
                 'setenv filesize'])
             assert(md5val[5] in ''.join(output))
 
-    def test_fs10(self, u_boot_console, fs_obj_basic):
+    def test_fs10(self, ubman, fs_obj_basic):
         """
         Test Case 10 - load, reading beyond file end'):
         """
-        fs_type,fs_img,md5val = fs_obj_basic
-        with u_boot_console.log.section('Test Case 10 - load (beyond file end)'):
+        fs_type,fs_cmd_prefix,fs_cmd_write,fs_img,md5val = fs_obj_basic
+        with ubman.log.section('Test Case 10 - load (beyond file end)'):
             # Generic failure case
             # Test Case 10 - 2MB chunk from the last 1MB of big file
-            output = u_boot_console.run_command_list([
+            output = ubman.run_command_list([
                 'host bind 0 %s' % fs_img,
                 '%sload host 0:0 %x /%s 0x00200000 0x9c300000'
-                    % (fs_type, ADDR, BIG_FILE),
+                    % (fs_cmd_prefix, ADDR, BIG_FILE),
                 'printenv filesize',
                 'md5sum %x $filesize' % ADDR,
                 'setenv filesize'])
         assert('filesize=100000' in ''.join(output))
 
-    def test_fs11(self, u_boot_console, fs_obj_basic):
+    def test_fs11(self, ubman, fs_obj_basic):
         """
         Test Case 11 - write'
         """
-        fs_type,fs_img,md5val = fs_obj_basic
-        with u_boot_console.log.section('Test Case 11 - write'):
+        fs_type,fs_cmd_prefix,fs_cmd_write,fs_img,md5val = fs_obj_basic
+        with ubman.log.section('Test Case 11 - write'):
             # Read 1MB from small file
             # Write it back to test the writes
             # Test Case 11a - Check that the write succeeded
-            output = u_boot_console.run_command_list([
+            output = ubman.run_command_list([
                 'host bind 0 %s' % fs_img,
-                '%sload host 0:0 %x /%s' % (fs_type, ADDR, SMALL_FILE),
-                '%swrite host 0:0 %x /%s.w $filesize'
-                    % (fs_type, ADDR, SMALL_FILE)])
+                '%sload host 0:0 %x /%s' % (fs_cmd_prefix, ADDR, SMALL_FILE),
+                '%s%s host 0:0 %x /%s.w $filesize'
+                    % (fs_cmd_prefix, fs_cmd_write, ADDR, SMALL_FILE)])
             assert('1048576 bytes written' in ''.join(output))
 
             # Test Case 11b - Check md5 of written to is same
             # as the one read from
-            output = u_boot_console.run_command_list([
-                '%sload host 0:0 %x /%s.w' % (fs_type, ADDR, SMALL_FILE),
+            output = ubman.run_command_list([
+                '%sload host 0:0 %x /%s.w' % (fs_cmd_prefix, ADDR, SMALL_FILE),
                 'md5sum %x $filesize' % ADDR,
                 'setenv filesize'])
             assert(md5val[0] in ''.join(output))
             assert_fs_integrity(fs_type, fs_img)
 
-    def test_fs12(self, u_boot_console, fs_obj_basic):
+    def test_fs12(self, ubman, fs_obj_basic):
         """
         Test Case 12 - write to "." directory
         """
-        fs_type,fs_img,md5val = fs_obj_basic
-        with u_boot_console.log.section('Test Case 12 - write (".")'):
+        fs_type,fs_cmd_prefix,fs_cmd_write,fs_img,md5val = fs_obj_basic
+        with ubman.log.section('Test Case 12 - write (".")'):
             # Next test case checks writing a file whose dirent
             # is the first in the block, which is always true for "."
             # The write should fail, but the lookup should work
             # Test Case 12 - Check directory traversal
-            output = u_boot_console.run_command_list([
+            output = ubman.run_command_list([
                 'host bind 0 %s' % fs_img,
-                '%swrite host 0:0 %x /. 0x10' % (fs_type, ADDR)])
+                '%s%s host 0:0 %x /. 0x10'
+                    % (fs_cmd_prefix, fs_cmd_write, ADDR)])
             assert('Unable to write' in ''.join(output))
             assert_fs_integrity(fs_type, fs_img)
 
-    def test_fs13(self, u_boot_console, fs_obj_basic):
+    def test_fs13(self, ubman, fs_obj_basic):
         """
         Test Case 13 - write to a file with "/./<filename>"
         """
-        fs_type,fs_img,md5val = fs_obj_basic
-        with u_boot_console.log.section('Test Case 13 - write  ("./<file>")'):
+        fs_type,fs_cmd_prefix,fs_cmd_write,fs_img,md5val = fs_obj_basic
+        with ubman.log.section('Test Case 13 - write  ("./<file>")'):
             # Read 1MB from small file
             # Write it via "same directory", i.e. "." dirent
             # Test Case 13a - Check directory traversal
-            output = u_boot_console.run_command_list([
+            output = ubman.run_command_list([
                 'host bind 0 %s' % fs_img,
-                '%sload host 0:0 %x /%s' % (fs_type, ADDR, SMALL_FILE),
-                '%swrite host 0:0 %x /./%s2 $filesize'
-                    % (fs_type, ADDR, SMALL_FILE)])
+                '%sload host 0:0 %x /%s' % (fs_cmd_prefix, ADDR, SMALL_FILE),
+                '%s%s host 0:0 %x /./%s2 $filesize'
+                    % (fs_cmd_prefix, fs_cmd_write, ADDR, SMALL_FILE)])
             assert('1048576 bytes written' in ''.join(output))
 
             # Test Case 13b - Check md5 of written to is same
             # as the one read from
-            output = u_boot_console.run_command_list([
+            output = ubman.run_command_list([
                 'mw.b %x 00 100' % ADDR,
-                '%sload host 0:0 %x /./%s2' % (fs_type, ADDR, SMALL_FILE),
+                '%sload host 0:0 %x /./%s2' % (fs_cmd_prefix, ADDR, SMALL_FILE),
                 'md5sum %x $filesize' % ADDR,
                 'setenv filesize'])
             assert(md5val[0] in ''.join(output))
 
             # Test Case 13c - Check md5 of written to is same
             # as the one read from
-            output = u_boot_console.run_command_list([
+            output = ubman.run_command_list([
                 'mw.b %x 00 100' % ADDR,
-                '%sload host 0:0 %x /%s2' % (fs_type, ADDR, SMALL_FILE),
+                '%sload host 0:0 %x /%s2' % (fs_cmd_prefix, ADDR, SMALL_FILE),
                 'md5sum %x $filesize' % ADDR,
                 'setenv filesize'])
             assert(md5val[0] in ''.join(output))
diff --git a/test/py/tests/test_fs/test_erofs.py b/test/py/tests/test_fs/test_erofs.py
index 87ad8f2d5fd..a2bb6b505f2 100644
--- a/test/py/tests/test_fs/test_erofs.py
+++ b/test/py/tests/test_fs/test_erofs.py
@@ -65,64 +65,64 @@ def clean_erofs_image(build_dir):
     image_path = os.path.join(build_dir, EROFS_IMAGE_NAME)
     os.remove(image_path)
 
-def erofs_ls_at_root(u_boot_console):
+def erofs_ls_at_root(ubman):
     """
     Test if all the present files and directories were listed.
     """
-    no_slash = u_boot_console.run_command('erofsls host 0')
-    slash = u_boot_console.run_command('erofsls host 0 /')
+    no_slash = ubman.run_command('erofsls host 0')
+    slash = ubman.run_command('erofsls host 0 /')
     assert no_slash == slash
 
     expected_lines = ['./', '../', '4096   f4096', '7812   f7812', 'subdir/',
                       '<SYM>   symdir', '<SYM>   symfile', '4 file(s), 3 dir(s)']
 
-    output = u_boot_console.run_command('erofsls host 0')
+    output = ubman.run_command('erofsls host 0')
     for line in expected_lines:
         assert line in output
 
-def erofs_ls_at_subdir(u_boot_console):
+def erofs_ls_at_subdir(ubman):
     """
     Test if the path resolution works.
     """
     expected_lines = ['./', '../', '100   subdir-file', '1 file(s), 2 dir(s)']
-    output = u_boot_console.run_command('erofsls host 0 subdir')
+    output = ubman.run_command('erofsls host 0 subdir')
     for line in expected_lines:
         assert line in output
 
-def erofs_ls_at_symlink(u_boot_console):
+def erofs_ls_at_symlink(ubman):
     """
     Test if the symbolic link's target resolution works.
     """
-    output = u_boot_console.run_command('erofsls host 0 symdir')
-    output_subdir = u_boot_console.run_command('erofsls host 0 subdir')
+    output = ubman.run_command('erofsls host 0 symdir')
+    output_subdir = ubman.run_command('erofsls host 0 subdir')
     assert output == output_subdir
 
     expected_lines = ['./', '../', '100   subdir-file', '1 file(s), 2 dir(s)']
     for line in expected_lines:
         assert line in output
 
-def erofs_ls_at_non_existent_dir(u_boot_console):
+def erofs_ls_at_non_existent_dir(ubman):
     """
     Test if the EROFS support will crash when get a nonexistent directory.
     """
-    out_non_existent = u_boot_console.run_command('erofsls host 0 fff')
-    out_not_dir = u_boot_console.run_command('erofsls host 0 f1000')
+    out_non_existent = ubman.run_command('erofsls host 0 fff')
+    out_not_dir = ubman.run_command('erofsls host 0 f1000')
     assert out_non_existent == out_not_dir
     assert '' in out_non_existent
 
-def erofs_load_files(u_boot_console, files, sizes, address):
+def erofs_load_files(ubman, files, sizes, address):
     """
     Loads files and asserts their checksums.
     """
-    build_dir = u_boot_console.config.build_dir
+    build_dir = ubman.config.build_dir
     for (file, size) in zip(files, sizes):
-        out = u_boot_console.run_command('erofsload host 0 {} {}'.format(address, file))
+        out = ubman.run_command('erofsload host 0 {} {}'.format(address, file))
 
         # check if the right amount of bytes was read
         assert size in out
 
         # calculate u-boot file's checksum
-        out = u_boot_console.run_command('md5sum {} {}'.format(address, hex(int(size))))
+        out = ubman.run_command('md5sum {} {}'.format(address, hex(int(size))))
         u_boot_checksum = out.split()[-1]
 
         # calculate original file's checksum
@@ -134,54 +134,54 @@ def erofs_load_files(u_boot_console, files, sizes, address):
         # compare checksum
         assert u_boot_checksum == original_checksum
 
-def erofs_load_files_at_root(u_boot_console):
+def erofs_load_files_at_root(ubman):
     """
     Test load file from the root directory.
     """
     files = ['f4096', 'f7812']
     sizes = ['4096', '7812']
     address = '$kernel_addr_r'
-    erofs_load_files(u_boot_console, files, sizes, address)
+    erofs_load_files(ubman, files, sizes, address)
 
-def erofs_load_files_at_subdir(u_boot_console):
+def erofs_load_files_at_subdir(ubman):
     """
     Test load file from the subdirectory.
     """
     files = ['subdir/subdir-file']
     sizes = ['100']
     address = '$kernel_addr_r'
-    erofs_load_files(u_boot_console, files, sizes, address)
+    erofs_load_files(ubman, files, sizes, address)
 
-def erofs_load_files_at_symlink(u_boot_console):
+def erofs_load_files_at_symlink(ubman):
     """
     Test load file from the symlink.
     """
     files = ['symfile']
     sizes = ['7812']
     address = '$kernel_addr_r'
-    erofs_load_files(u_boot_console, files, sizes, address)
+    erofs_load_files(ubman, files, sizes, address)
 
-def erofs_load_non_existent_file(u_boot_console):
+def erofs_load_non_existent_file(ubman):
     """
     Test if the EROFS support will crash when load a nonexistent file.
     """
     address = '$kernel_addr_r'
     file = 'non-existent'
-    out = u_boot_console.run_command('erofsload host 0 {} {}'.format(address, file))
+    out = ubman.run_command('erofsload host 0 {} {}'.format(address, file))
     assert 'Failed to load' in out
 
-def erofs_run_all_tests(u_boot_console):
+def erofs_run_all_tests(ubman):
     """
     Runs all test cases.
     """
-    erofs_ls_at_root(u_boot_console)
-    erofs_ls_at_subdir(u_boot_console)
-    erofs_ls_at_symlink(u_boot_console)
-    erofs_ls_at_non_existent_dir(u_boot_console)
-    erofs_load_files_at_root(u_boot_console)
-    erofs_load_files_at_subdir(u_boot_console)
-    erofs_load_files_at_symlink(u_boot_console)
-    erofs_load_non_existent_file(u_boot_console)
+    erofs_ls_at_root(ubman)
+    erofs_ls_at_subdir(ubman)
+    erofs_ls_at_symlink(ubman)
+    erofs_ls_at_non_existent_dir(ubman)
+    erofs_load_files_at_root(ubman)
+    erofs_load_files_at_subdir(ubman)
+    erofs_load_files_at_symlink(ubman)
+    erofs_load_non_existent_file(ubman)
 
 @pytest.mark.boardspec('sandbox')
 @pytest.mark.buildconfigspec('cmd_fs_generic')
@@ -190,11 +190,11 @@ def erofs_run_all_tests(u_boot_console):
 @pytest.mark.requiredtool('mkfs.erofs')
 @pytest.mark.requiredtool('md5sum')
 
-def test_erofs(u_boot_console):
+def test_erofs(ubman):
     """
     Executes the erofs test suite.
     """
-    build_dir = u_boot_console.config.build_dir
+    build_dir = ubman.config.build_dir
 
     # If the EFI subsystem is enabled and initialized, EFI subsystem tries to
     # add EFI boot option when the new disk is detected. If there is no EFI
@@ -203,15 +203,15 @@ def test_erofs(u_boot_console):
     # Restart U-Boot to clear the previous state.
     # TODO: Ideally EFI test cases need to be fixed, but it will
     # increase the number of system reset.
-    u_boot_console.restart_uboot()
+    ubman.restart_uboot()
 
     try:
         # setup test environment
         make_erofs_image(build_dir)
         image_path = os.path.join(build_dir, EROFS_IMAGE_NAME)
-        u_boot_console.run_command('host bind 0 {}'.format(image_path))
+        ubman.run_command('host bind 0 {}'.format(image_path))
         # run all tests
-        erofs_run_all_tests(u_boot_console)
+        erofs_run_all_tests(ubman)
     except:
         clean_erofs_image(build_dir)
         raise AssertionError
diff --git a/test/py/tests/test_fs/test_ext.py b/test/py/tests/test_fs/test_ext.py
index 05fefa53a0e..41f126e7876 100644
--- a/test/py/tests/test_fs/test_ext.py
+++ b/test/py/tests/test_fs/test_ext.py
@@ -29,327 +29,335 @@ def str2fat(long_filename):
 @pytest.mark.boardspec('sandbox')
 @pytest.mark.slow
 class TestFsExt(object):
-    def test_fs_ext1(self, u_boot_console, fs_obj_ext):
+    def test_fs_ext1(self, ubman, fs_obj_ext):
         """
         Test Case 1 - write a file with absolute path
         """
-        fs_type,fs_img,md5val = fs_obj_ext
-        with u_boot_console.log.section('Test Case 1 - write with abs path'):
+        fs_type,fs_cmd_prefix,fs_cmd_write,fs_img,md5val = fs_obj_ext
+        with ubman.log.section('Test Case 1 - write with abs path'):
             # Test Case 1a - Check if command successfully returned
-            output = u_boot_console.run_command_list([
+            output = ubman.run_command_list([
                 'host bind 0 %s' % fs_img,
-                '%sload host 0:0 %x /%s' % (fs_type, ADDR, MIN_FILE),
-                '%swrite host 0:0 %x /dir1/%s.w1 $filesize'
-                    % (fs_type, ADDR, MIN_FILE)])
+                '%sload host 0:0 %x /%s' % (fs_cmd_prefix, ADDR, MIN_FILE),
+                '%s%s host 0:0 %x /dir1/%s.w1 $filesize'
+                    % (fs_cmd_prefix, fs_cmd_write, ADDR, MIN_FILE)])
             assert('20480 bytes written' in ''.join(output))
 
             # Test Case 1b - Check md5 of file content
-            output = u_boot_console.run_command_list([
+            output = ubman.run_command_list([
                 'mw.b %x 00 100' % ADDR,
-                '%sload host 0:0 %x /dir1/%s.w1' % (fs_type, ADDR, MIN_FILE),
+                '%sload host 0:0 %x /dir1/%s.w1' % (fs_cmd_prefix, ADDR, MIN_FILE),
                 'md5sum %x $filesize' % ADDR,
                 'setenv filesize'])
             assert(md5val[0] in ''.join(output))
             assert_fs_integrity(fs_type, fs_img)
 
-    def test_fs_ext2(self, u_boot_console, fs_obj_ext):
+    def test_fs_ext2(self, ubman, fs_obj_ext):
         """
         Test Case 2 - write to a file with relative path
         """
-        fs_type,fs_img,md5val = fs_obj_ext
-        with u_boot_console.log.section('Test Case 2 - write with rel path'):
+        fs_type,fs_cmd_prefix,fs_cmd_write,fs_img,md5val = fs_obj_ext
+        with ubman.log.section('Test Case 2 - write with rel path'):
             # Test Case 2a - Check if command successfully returned
-            output = u_boot_console.run_command_list([
+            output = ubman.run_command_list([
                 'host bind 0 %s' % fs_img,
-                '%sload host 0:0 %x /%s' % (fs_type, ADDR, MIN_FILE),
-                '%swrite host 0:0 %x dir1/%s.w2 $filesize'
-                    % (fs_type, ADDR, MIN_FILE)])
+                '%sload host 0:0 %x /%s' % (fs_cmd_prefix, ADDR, MIN_FILE),
+                '%s%s host 0:0 %x dir1/%s.w2 $filesize'
+                    % (fs_cmd_prefix, fs_cmd_write, ADDR, MIN_FILE)])
             assert('20480 bytes written' in ''.join(output))
 
             # Test Case 2b - Check md5 of file content
-            output = u_boot_console.run_command_list([
+            output = ubman.run_command_list([
                 'mw.b %x 00 100' % ADDR,
-                '%sload host 0:0 %x dir1/%s.w2' % (fs_type, ADDR, MIN_FILE),
+                '%sload host 0:0 %x dir1/%s.w2' % (fs_cmd_prefix, ADDR, MIN_FILE),
                 'md5sum %x $filesize' % ADDR,
                 'setenv filesize'])
             assert(md5val[0] in ''.join(output))
             assert_fs_integrity(fs_type, fs_img)
 
-    def test_fs_ext3(self, u_boot_console, fs_obj_ext):
+    def test_fs_ext3(self, ubman, fs_obj_ext):
         """
         Test Case 3 - write to a file with invalid path
         """
-        fs_type,fs_img,md5val = fs_obj_ext
-        with u_boot_console.log.section('Test Case 3 - write with invalid path'):
+        fs_type,fs_cmd_prefix,fs_cmd_write,fs_img,md5val = fs_obj_ext
+        with ubman.log.section('Test Case 3 - write with invalid path'):
             # Test Case 3 - Check if command expectedly failed
-            output = u_boot_console.run_command_list([
+            output = ubman.run_command_list([
                 'host bind 0 %s' % fs_img,
-                '%sload host 0:0 %x /%s' % (fs_type, ADDR, MIN_FILE),
-                '%swrite host 0:0 %x /dir1/none/%s.w3 $filesize'
-                    % (fs_type, ADDR, MIN_FILE)])
+                '%sload host 0:0 %x /%s' % (fs_cmd_prefix, ADDR, MIN_FILE),
+                '%s%s host 0:0 %x /dir1/none/%s.w3 $filesize'
+                    % (fs_cmd_prefix, fs_cmd_write, ADDR, MIN_FILE)])
             assert('Unable to write file /dir1/none/' in ''.join(output))
             assert_fs_integrity(fs_type, fs_img)
 
-    def test_fs_ext4(self, u_boot_console, fs_obj_ext):
+    def test_fs_ext4(self, ubman, fs_obj_ext):
         """
         Test Case 4 - write at non-zero offset, enlarging file size
         """
-        fs_type,fs_img,md5val = fs_obj_ext
-        with u_boot_console.log.section('Test Case 4 - write at non-zero offset, enlarging file size'):
+        fs_type,fs_cmd_prefix,fs_cmd_write,fs_img,md5val = fs_obj_ext
+        with ubman.log.section('Test Case 4 - write at non-zero offset, enlarging file size'):
             # Test Case 4a - Check if command successfully returned
-            output = u_boot_console.run_command_list([
+            output = ubman.run_command_list([
                 'host bind 0 %s' % fs_img,
-                '%sload host 0:0 %x /%s' % (fs_type, ADDR, MIN_FILE),
-                '%swrite host 0:0 %x /dir1/%s.w4 $filesize'
-                    % (fs_type, ADDR, MIN_FILE)])
-            output = u_boot_console.run_command(
-                '%swrite host 0:0 %x /dir1/%s.w4 $filesize 0x1400'
-                    % (fs_type, ADDR, MIN_FILE))
+                '%sload host 0:0 %x /%s' % (fs_cmd_prefix, ADDR, MIN_FILE),
+                '%s%s host 0:0 %x /dir1/%s.w4 $filesize'
+                    % (fs_cmd_prefix, fs_cmd_write, ADDR, MIN_FILE)])
+            output = ubman.run_command(
+                '%s%s host 0:0 %x /dir1/%s.w4 $filesize 0x1400'
+                    % (fs_cmd_prefix, fs_cmd_write, ADDR, MIN_FILE))
             assert('20480 bytes written' in output)
 
             # Test Case 4b - Check size of written file
-            output = u_boot_console.run_command_list([
-                '%ssize host 0:0 /dir1/%s.w4' % (fs_type, MIN_FILE),
+            output = ubman.run_command_list([
+                '%ssize host 0:0 /dir1/%s.w4' % (fs_cmd_prefix, MIN_FILE),
                 'printenv filesize',
                 'setenv filesize'])
             assert('filesize=6400' in ''.join(output))
 
             # Test Case 4c - Check md5 of file content
-            output = u_boot_console.run_command_list([
+            output = ubman.run_command_list([
                 'mw.b %x 00 100' % ADDR,
-                '%sload host 0:0 %x /dir1/%s.w4' % (fs_type, ADDR, MIN_FILE),
+                '%sload host 0:0 %x /dir1/%s.w4' % (fs_cmd_prefix, ADDR, MIN_FILE),
                 'md5sum %x $filesize' % ADDR,
                 'setenv filesize'])
             assert(md5val[1] in ''.join(output))
             assert_fs_integrity(fs_type, fs_img)
 
-    def test_fs_ext5(self, u_boot_console, fs_obj_ext):
+    def test_fs_ext5(self, ubman, fs_obj_ext):
         """
         Test Case 5 - write at non-zero offset, shrinking file size
         """
-        fs_type,fs_img,md5val = fs_obj_ext
-        with u_boot_console.log.section('Test Case 5 - write at non-zero offset, shrinking file size'):
+        fs_type,fs_cmd_prefix,fs_cmd_write,fs_img,md5val = fs_obj_ext
+        with ubman.log.section('Test Case 5 - write at non-zero offset, shrinking file size'):
             # Test Case 5a - Check if command successfully returned
-            output = u_boot_console.run_command_list([
+            output = ubman.run_command_list([
                 'host bind 0 %s' % fs_img,
-                '%sload host 0:0 %x /%s' % (fs_type, ADDR, MIN_FILE),
-                '%swrite host 0:0 %x /dir1/%s.w5 $filesize'
-                    % (fs_type, ADDR, MIN_FILE)])
-            output = u_boot_console.run_command(
-                '%swrite host 0:0 %x /dir1/%s.w5 0x1400 0x1400'
-                    % (fs_type, ADDR, MIN_FILE))
+                '%sload host 0:0 %x /%s' % (fs_cmd_prefix, ADDR, MIN_FILE),
+                '%s%s host 0:0 %x /dir1/%s.w5 $filesize'
+                    % (fs_cmd_prefix, fs_cmd_write, ADDR, MIN_FILE)])
+            output = ubman.run_command(
+                '%s%s host 0:0 %x /dir1/%s.w5 0x1400 0x1400'
+                    % (fs_cmd_prefix, fs_cmd_write, ADDR, MIN_FILE))
             assert('5120 bytes written' in output)
 
             # Test Case 5b - Check size of written file
-            output = u_boot_console.run_command_list([
-                '%ssize host 0:0 /dir1/%s.w5' % (fs_type, MIN_FILE),
+            output = ubman.run_command_list([
+                '%ssize host 0:0 /dir1/%s.w5' % (fs_cmd_prefix, MIN_FILE),
                 'printenv filesize',
                 'setenv filesize'])
             assert('filesize=2800' in ''.join(output))
 
             # Test Case 5c - Check md5 of file content
-            output = u_boot_console.run_command_list([
+            output = ubman.run_command_list([
                 'mw.b %x 00 100' % ADDR,
-                '%sload host 0:0 %x /dir1/%s.w5' % (fs_type, ADDR, MIN_FILE),
+                '%sload host 0:0 %x /dir1/%s.w5' % (fs_cmd_prefix, ADDR, MIN_FILE),
                 'md5sum %x $filesize' % ADDR,
                 'setenv filesize'])
             assert(md5val[2] in ''.join(output))
             assert_fs_integrity(fs_type, fs_img)
 
-    def test_fs_ext6(self, u_boot_console, fs_obj_ext):
+    def test_fs_ext6(self, ubman, fs_obj_ext):
         """
         Test Case 6 - write nothing at the start, truncating to zero
         """
-        fs_type,fs_img,md5val = fs_obj_ext
-        with u_boot_console.log.section('Test Case 6 - write nothing at the start, truncating to zero'):
+        fs_type,fs_cmd_prefix,fs_cmd_write,fs_img,md5val = fs_obj_ext
+        with ubman.log.section('Test Case 6 - write nothing at the start, truncating to zero'):
             # Test Case 6a - Check if command successfully returned
-            output = u_boot_console.run_command_list([
+            output = ubman.run_command_list([
                 'host bind 0 %s' % fs_img,
-                '%sload host 0:0 %x /%s' % (fs_type, ADDR, MIN_FILE),
-                '%swrite host 0:0 %x /dir1/%s.w6 $filesize'
-                    % (fs_type, ADDR, MIN_FILE)])
-            output = u_boot_console.run_command(
-                '%swrite host 0:0 %x /dir1/%s.w6 0 0'
-                    % (fs_type, ADDR, MIN_FILE))
+                '%sload host 0:0 %x /%s' % (fs_cmd_prefix, ADDR, MIN_FILE),
+                '%s%s host 0:0 %x /dir1/%s.w6 $filesize'
+                    % (fs_cmd_prefix, fs_cmd_write, ADDR, MIN_FILE)])
+            output = ubman.run_command(
+                '%s%s host 0:0 %x /dir1/%s.w6 0 0'
+                    % (fs_cmd_prefix, fs_cmd_write, ADDR, MIN_FILE))
             assert('0 bytes written' in output)
 
             # Test Case 6b - Check size of written file
-            output = u_boot_console.run_command_list([
-                '%ssize host 0:0 /dir1/%s.w6' % (fs_type, MIN_FILE),
+            output = ubman.run_command_list([
+                '%ssize host 0:0 /dir1/%s.w6' % (fs_cmd_prefix, MIN_FILE),
                 'printenv filesize',
                 'setenv filesize'])
             assert('filesize=0' in ''.join(output))
             assert_fs_integrity(fs_type, fs_img)
 
-    def test_fs_ext7(self, u_boot_console, fs_obj_ext):
+    def test_fs_ext7(self, ubman, fs_obj_ext):
         """
         Test Case 7 - write at the end (append)
         """
-        fs_type,fs_img,md5val = fs_obj_ext
-        with u_boot_console.log.section('Test Case 7 - write at the end (append)'):
+        fs_type,fs_cmd_prefix,fs_cmd_write,fs_img,md5val = fs_obj_ext
+        with ubman.log.section('Test Case 7 - write at the end (append)'):
             # Test Case 7a - Check if command successfully returned
-            output = u_boot_console.run_command_list([
+            output = ubman.run_command_list([
                 'host bind 0 %s' % fs_img,
-                '%sload host 0:0 %x /%s' % (fs_type, ADDR, MIN_FILE),
-                '%swrite host 0:0 %x /dir1/%s.w7 $filesize'
-                    % (fs_type, ADDR, MIN_FILE)])
-            output = u_boot_console.run_command(
-                '%swrite host 0:0 %x /dir1/%s.w7 $filesize $filesize'
-                    % (fs_type, ADDR, MIN_FILE))
+                '%sload host 0:0 %x /%s' % (fs_cmd_prefix, ADDR, MIN_FILE),
+                '%s%s host 0:0 %x /dir1/%s.w7 $filesize'
+                    % (fs_cmd_prefix, fs_cmd_write, ADDR, MIN_FILE)])
+            output = ubman.run_command(
+                '%s%s host 0:0 %x /dir1/%s.w7 $filesize $filesize'
+                    % (fs_cmd_prefix, fs_cmd_write, ADDR, MIN_FILE))
             assert('20480 bytes written' in output)
 
             # Test Case 7b - Check size of written file
-            output = u_boot_console.run_command_list([
-                '%ssize host 0:0 /dir1/%s.w7' % (fs_type, MIN_FILE),
+            output = ubman.run_command_list([
+                '%ssize host 0:0 /dir1/%s.w7' % (fs_cmd_prefix, MIN_FILE),
                 'printenv filesize',
                 'setenv filesize'])
             assert('filesize=a000' in ''.join(output))
 
             # Test Case 7c - Check md5 of file content
-            output = u_boot_console.run_command_list([
+            output = ubman.run_command_list([
                 'mw.b %x 00 100' % ADDR,
-                '%sload host 0:0 %x /dir1/%s.w7' % (fs_type, ADDR, MIN_FILE),
+                '%sload host 0:0 %x /dir1/%s.w7' % (fs_cmd_prefix, ADDR, MIN_FILE),
                 'md5sum %x $filesize' % ADDR,
                 'setenv filesize'])
             assert(md5val[3] in ''.join(output))
             assert_fs_integrity(fs_type, fs_img)
 
-    def test_fs_ext8(self, u_boot_console, fs_obj_ext):
+    def test_fs_ext8(self, ubman, fs_obj_ext):
         """
         Test Case 8 - write at offset beyond the end of file
         """
-        fs_type,fs_img,md5val = fs_obj_ext
-        with u_boot_console.log.section('Test Case 8 - write beyond the end'):
+        fs_type,fs_cmd_prefix,fs_cmd_write,fs_img,md5val = fs_obj_ext
+        with ubman.log.section('Test Case 8 - write beyond the end'):
             # Test Case 8a - Check if command expectedly failed
-            output = u_boot_console.run_command_list([
+            output = ubman.run_command_list([
                 'host bind 0 %s' % fs_img,
-                '%sload host 0:0 %x /%s' % (fs_type, ADDR, MIN_FILE),
-                '%swrite host 0:0 %x /dir1/%s.w8 $filesize'
-                    % (fs_type, ADDR, MIN_FILE)])
-            output = u_boot_console.run_command(
-                '%swrite host 0:0 %x /dir1/%s.w8 0x1400 %x'
-                    % (fs_type, ADDR, MIN_FILE, 0x100000 + 0x1400))
+                '%sload host 0:0 %x /%s' % (fs_cmd_prefix, ADDR, MIN_FILE),
+                '%s%s host 0:0 %x /dir1/%s.w8 $filesize'
+                    % (fs_cmd_prefix, fs_cmd_write, ADDR, MIN_FILE)])
+            output = ubman.run_command(
+                '%s%s host 0:0 %x /dir1/%s.w8 0x1400 %x'
+                    % (fs_cmd_prefix, fs_cmd_write, ADDR, MIN_FILE, 0x100000 + 0x1400))
             assert('Unable to write file /dir1' in output)
             assert_fs_integrity(fs_type, fs_img)
 
-    def test_fs_ext9(self, u_boot_console, fs_obj_ext):
+    def test_fs_ext9(self, ubman, fs_obj_ext):
         """
         Test Case 9 - write to a non-existing file at non-zero offset
         """
-        fs_type,fs_img,md5val = fs_obj_ext
-        with u_boot_console.log.section('Test Case 9 - write to non-existing file with non-zero offset'):
+        fs_type,fs_cmd_prefix,fs_cmd_write,fs_img,md5val = fs_obj_ext
+        with ubman.log.section('Test Case 9 - write to non-existing file with non-zero offset'):
             # Test Case 9a - Check if command expectedly failed
-            output = u_boot_console.run_command_list([
+            output = ubman.run_command_list([
                 'host bind 0 %s' % fs_img,
-                '%sload host 0:0 %x /%s' % (fs_type, ADDR, MIN_FILE),
-                '%swrite host 0:0 %x /dir1/%s.w9 0x1400 0x1400'
-                    % (fs_type, ADDR, MIN_FILE)])
+                '%sload host 0:0 %x /%s' % (fs_cmd_prefix, ADDR, MIN_FILE),
+                '%s%s host 0:0 %x /dir1/%s.w9 0x1400 0x1400'
+                    % (fs_cmd_prefix, fs_cmd_write, ADDR, MIN_FILE)])
             assert('Unable to write file /dir1' in ''.join(output))
             assert_fs_integrity(fs_type, fs_img)
 
-    def test_fs_ext10(self, u_boot_console, fs_obj_ext):
+    def test_fs_ext10(self, ubman, fs_obj_ext):
         """
         'Test Case 10 - create/delete as many directories under root directory
         as amount of directory entries goes beyond one cluster size)'
         """
-        fs_type,fs_img,md5val = fs_obj_ext
-        with u_boot_console.log.section('Test Case 10 - create/delete (many)'):
+        fs_type,fs_cmd_prefix,fs_cmd_write,fs_img,md5val = fs_obj_ext
+        with ubman.log.section('Test Case 10 - create/delete (many)'):
             # Test Case 10a - Create many files
             #   Please note that the size of directory entry is 32 bytes.
             #   So one typical cluster may holds 64 (2048/32) entries.
-            output = u_boot_console.run_command(
+            output = ubman.run_command(
                 'host bind 0 %s' % fs_img)
 
             for i in range(0, 66):
-                output = u_boot_console.run_command(
-                    '%swrite host 0:0 %x /FILE0123456789_%02x 100'
-                    % (fs_type, ADDR, i))
-            output = u_boot_console.run_command('%sls host 0:0 /' % fs_type)
+                output = ubman.run_command(
+                    '%s%s host 0:0 %x /FILE0123456789_%02x 100'
+                    % (fs_cmd_prefix, fs_cmd_write, ADDR, i))
+            output = ubman.run_command('%sls host 0:0 /' % fs_cmd_prefix)
             assert('FILE0123456789_00' in output)
             assert('FILE0123456789_41' in output)
 
             # Test Case 10b - Delete many files
             for i in range(0, 66):
-                output = u_boot_console.run_command(
+                output = ubman.run_command(
                     '%srm host 0:0 /FILE0123456789_%02x'
-                    % (fs_type, i))
-            output = u_boot_console.run_command('%sls host 0:0 /' % fs_type)
+                    % (fs_cmd_prefix, i))
+            output = ubman.run_command('%sls host 0:0 /' % fs_cmd_prefix)
             assert(not 'FILE0123456789_00' in output)
             assert(not 'FILE0123456789_41' in output)
 
             # Test Case 10c - Create many files again
             # Please note no.64 and 65 are intentionally re-created
             for i in range(64, 128):
-                output = u_boot_console.run_command(
-                    '%swrite host 0:0 %x /FILE0123456789_%02x 100'
-                    % (fs_type, ADDR, i))
-            output = u_boot_console.run_command('%sls host 0:0 /' % fs_type)
+                output = ubman.run_command(
+                    '%s%s host 0:0 %x /FILE0123456789_%02x 100'
+                    % (fs_cmd_prefix, fs_cmd_write, ADDR, i))
+            output = ubman.run_command('%sls host 0:0 /' % fs_cmd_prefix)
             assert('FILE0123456789_40' in output)
             assert('FILE0123456789_79' in output)
 
             assert_fs_integrity(fs_type, fs_img)
 
-    def test_fs_ext11(self, u_boot_console, fs_obj_ext):
+    def test_fs_ext11(self, ubman, fs_obj_ext):
         """
         'Test Case 11 - create/delete as many directories under non-root
         directory as amount of directory entries goes beyond one cluster size)'
         """
-        fs_type,fs_img,md5val = fs_obj_ext
-        with u_boot_console.log.section('Test Case 11 - create/delete (many)'):
+        fs_type,fs_cmd_prefix,fs_cmd_write,fs_img,md5val = fs_obj_ext
+        with ubman.log.section('Test Case 11 - create/delete (many)'):
             # Test Case 11a - Create many files
             #   Please note that the size of directory entry is 32 bytes.
             #   So one typical cluster may holds 64 (2048/32) entries.
-            output = u_boot_console.run_command(
+            output = ubman.run_command(
                 'host bind 0 %s' % fs_img)
 
             for i in range(0, 66):
-                output = u_boot_console.run_command(
-                    '%swrite host 0:0 %x /dir1/FILE0123456789_%02x 100'
-                    % (fs_type, ADDR, i))
-            output = u_boot_console.run_command('%sls host 0:0 /dir1' % fs_type)
+                output = ubman.run_command(
+                    '%s%s host 0:0 %x /dir1/FILE0123456789_%02x 100'
+                    % (fs_cmd_prefix, fs_cmd_write, ADDR, i))
+            output = ubman.run_command('%sls host 0:0 /dir1' % fs_cmd_prefix)
             assert('FILE0123456789_00' in output)
             assert('FILE0123456789_41' in output)
 
             # Test Case 11b - Delete many files
             for i in range(0, 66):
-                output = u_boot_console.run_command(
+                output = ubman.run_command(
                     '%srm host 0:0 /dir1/FILE0123456789_%02x'
-                    % (fs_type, i))
-            output = u_boot_console.run_command('%sls host 0:0 /dir1' % fs_type)
+                    % (fs_cmd_prefix, i))
+            output = ubman.run_command('%sls host 0:0 /dir1' % fs_cmd_prefix)
             assert(not 'FILE0123456789_00' in output)
             assert(not 'FILE0123456789_41' in output)
 
             # Test Case 11c - Create many files again
             # Please note no.64 and 65 are intentionally re-created
             for i in range(64, 128):
-                output = u_boot_console.run_command(
-                    '%swrite host 0:0 %x /dir1/FILE0123456789_%02x 100'
-                    % (fs_type, ADDR, i))
-            output = u_boot_console.run_command('%sls host 0:0 /dir1' % fs_type)
+                output = ubman.run_command(
+                    '%s%s host 0:0 %x /dir1/FILE0123456789_%02x 100'
+                    % (fs_cmd_prefix, fs_cmd_write, ADDR, i))
+            output = ubman.run_command('%sls host 0:0 /dir1' % fs_cmd_prefix)
             assert('FILE0123456789_40' in output)
             assert('FILE0123456789_79' in output)
 
             assert_fs_integrity(fs_type, fs_img)
 
-    def test_fs_ext12(self, u_boot_console, fs_obj_ext):
+    def test_fs_ext12(self, ubman, fs_obj_ext):
         """
         Test Case 12 - write plain and mangle file
         """
-        fs_type,fs_img,md5val = fs_obj_ext
-        with u_boot_console.log.section('Test Case 12 - write plain and mangle file'):
+        fs_type,fs_cmd_prefix,fs_cmd_write,fs_img,md5val = fs_obj_ext
+        with ubman.log.section('Test Case 12 - write plain and mangle file'):
             # Test Case 12a - Check if command successfully returned
-            output = u_boot_console.run_command_list([
+            output = ubman.run_command_list([
                 'host bind 0 %s' % fs_img,
-                '%swrite host 0:0 %x /%s 0'
-                    % (fs_type, ADDR, PLAIN_FILE),
-                '%swrite host 0:0 %x /%s 0'
-                    % (fs_type, ADDR, MANGLE_FILE)])
+                '%s%s host 0:0 %x /%s 0'
+                    % (fs_cmd_prefix, fs_cmd_write, ADDR, PLAIN_FILE),
+                '%s%s host 0:0 %x /%s 0'
+                    % (fs_cmd_prefix, fs_cmd_write, ADDR, MANGLE_FILE)])
             assert('0 bytes written' in ''.join(output))
-            # Test Case 12b - Read file system content
-            output = check_output('mdir -i %s' % fs_img, shell=True).decode()
-            # Test Case 12c - Check if short filename is not mangled
-            assert(str2fat(PLAIN_FILE) in ''.join(output))
-            # Test Case 12d - Check if long filename is mangled
-            assert(str2fat(MANGLE_FILE) in ''.join(output))
+            if fs_type == 'exfat':
+                # Test Case 12b - Read file system content
+                output = check_output('fattools ls %s' % fs_img, shell=True).decode()
+                # Test Case 12c - Check if short filename is not mangled
+                assert(PLAIN_FILE in ''.join(output))
+                # Test Case 12d - Check if long filename is mangled
+                assert(MANGLE_FILE in ''.join(output))
+            else:
+                # Test Case 12b - Read file system content
+                output = check_output('mdir -i %s' % fs_img, shell=True).decode()
+                # Test Case 12c - Check if short filename is not mangled
+                assert(str2fat(PLAIN_FILE) in ''.join(output))
+                # Test Case 12d - Check if long filename is mangled
+                assert(str2fat(MANGLE_FILE) in ''.join(output))
 
             assert_fs_integrity(fs_type, fs_img)
diff --git a/test/py/tests/test_fs/test_fs_cmd.py b/test/py/tests/test_fs/test_fs_cmd.py
index 700cf3591de..c925547c7bc 100644
--- a/test/py/tests/test_fs/test_fs_cmd.py
+++ b/test/py/tests/test_fs/test_fs_cmd.py
@@ -6,8 +6,8 @@ import pytest
 
 @pytest.mark.boardspec('sandbox')
 @pytest.mark.buildconfigspec('cmd_fs_generic')
-def test_fstypes(u_boot_console):
+def test_fstypes(ubman):
     """Test that `fstypes` prints a result which includes `sandbox`."""
-    output = u_boot_console.run_command('fstypes')
+    output = ubman.run_command('fstypes')
     assert "Supported filesystems:" in output
     assert "sandbox" in output
diff --git a/test/py/tests/test_fs/test_fs_fat.py b/test/py/tests/test_fs/test_fs_fat.py
index 4009d0b63a3..b61d8ab9eac 100644
--- a/test/py/tests/test_fs/test_fs_fat.py
+++ b/test/py/tests/test_fs/test_fs_fat.py
@@ -14,12 +14,12 @@ import re
 @pytest.mark.boardspec('sandbox')
 @pytest.mark.slow
 class TestFsFat(object):
-    def test_fs_fat1(self, u_boot_console, fs_obj_fat):
+    def test_fs_fat1(self, ubman, fs_obj_fat):
         """Test that `fstypes` prints a result which includes `sandbox`."""
         fs_type,fs_img = fs_obj_fat
-        with u_boot_console.log.section('Test Case 1 - fatinfo'):
+        with ubman.log.section('Test Case 1 - fatinfo'):
             # Test Case 1 - ls
-            output = u_boot_console.run_command_list([
+            output = ubman.run_command_list([
                 'host bind 0 %s' % fs_img,
                 'fatinfo host 0:0'])
             assert(re.search('Filesystem: %s' % fs_type.upper(), ''.join(output)))
diff --git a/test/py/tests/test_fs/test_mkdir.py b/test/py/tests/test_fs/test_mkdir.py
index fa9561ec359..1578c3cba3a 100644
--- a/test/py/tests/test_fs/test_mkdir.py
+++ b/test/py/tests/test_fs/test_mkdir.py
@@ -14,108 +14,108 @@ from fstest_helpers import assert_fs_integrity
 @pytest.mark.boardspec('sandbox')
 @pytest.mark.slow
 class TestMkdir(object):
-    def test_mkdir1(self, u_boot_console, fs_obj_mkdir):
+    def test_mkdir1(self, ubman, fs_obj_mkdir):
         """
         Test Case 1 - create a directory under a root
         """
-        fs_type,fs_img = fs_obj_mkdir
-        with u_boot_console.log.section('Test Case 1 - mkdir'):
-            output = u_boot_console.run_command_list([
+        fs_type,fs_cmd_prefix,fs_img = fs_obj_mkdir
+        with ubman.log.section('Test Case 1 - mkdir'):
+            output = ubman.run_command_list([
                 'host bind 0 %s' % fs_img,
-                '%smkdir host 0:0 dir1' % fs_type,
-                '%sls host 0:0 /' % fs_type])
+                '%smkdir host 0:0 dir1' % fs_cmd_prefix,
+                '%sls host 0:0 /' % fs_cmd_prefix])
             assert('dir1/' in ''.join(output))
 
-            output = u_boot_console.run_command(
-                '%sls host 0:0 dir1' % fs_type)
+            output = ubman.run_command(
+                '%sls host 0:0 dir1' % fs_cmd_prefix)
             assert('./'   in output)
             assert('../'  in output)
             assert_fs_integrity(fs_type, fs_img)
 
 
-    def test_mkdir2(self, u_boot_console, fs_obj_mkdir):
+    def test_mkdir2(self, ubman, fs_obj_mkdir):
         """
         Test Case 2 - create a directory under a sub-directory
         """
-        fs_type,fs_img = fs_obj_mkdir
-        with u_boot_console.log.section('Test Case 2 - mkdir (sub-sub directory)'):
-            output = u_boot_console.run_command_list([
+        fs_type,fs_cmd_prefix,fs_img = fs_obj_mkdir
+        with ubman.log.section('Test Case 2 - mkdir (sub-sub directory)'):
+            output = ubman.run_command_list([
                 'host bind 0 %s' % fs_img,
-                '%smkdir host 0:0 dir1/dir2' % fs_type,
-                '%sls host 0:0 dir1' % fs_type])
+                '%smkdir host 0:0 dir1/dir2' % fs_cmd_prefix,
+                '%sls host 0:0 dir1' % fs_cmd_prefix])
             assert('dir2/' in ''.join(output))
 
-            output = u_boot_console.run_command(
-                '%sls host 0:0 dir1/dir2' % fs_type)
+            output = ubman.run_command(
+                '%sls host 0:0 dir1/dir2' % fs_cmd_prefix)
             assert('./'   in output)
             assert('../'  in output)
             assert_fs_integrity(fs_type, fs_img)
 
-    def test_mkdir3(self, u_boot_console, fs_obj_mkdir):
+    def test_mkdir3(self, ubman, fs_obj_mkdir):
         """
         Test Case 3 - trying to create a directory with a non-existing
         path should fail
         """
-        fs_type,fs_img = fs_obj_mkdir
-        with u_boot_console.log.section('Test Case 3 - mkdir (non-existing path)'):
-            output = u_boot_console.run_command_list([
+        fs_type,fs_cmd_prefix,fs_img = fs_obj_mkdir
+        with ubman.log.section('Test Case 3 - mkdir (non-existing path)'):
+            output = ubman.run_command_list([
                 'host bind 0 %s' % fs_img,
-                '%smkdir host 0:0 none/dir3' % fs_type])
+                '%smkdir host 0:0 none/dir3' % fs_cmd_prefix])
             assert('Unable to create a directory' in ''.join(output))
             assert_fs_integrity(fs_type, fs_img)
 
-    def test_mkdir4(self, u_boot_console, fs_obj_mkdir):
+    def test_mkdir4(self, ubman, fs_obj_mkdir):
         """
         Test Case 4 - trying to create "." should fail
         """
-        fs_type,fs_img = fs_obj_mkdir
-        with u_boot_console.log.section('Test Case 4 - mkdir (".")'):
-            output = u_boot_console.run_command_list([
+        fs_type,fs_cmd_prefix,fs_img = fs_obj_mkdir
+        with ubman.log.section('Test Case 4 - mkdir (".")'):
+            output = ubman.run_command_list([
                 'host bind 0 %s' % fs_img,
-                '%smkdir host 0:0 .' % fs_type])
+                '%smkdir host 0:0 .' % fs_cmd_prefix])
             assert('Unable to create a directory' in ''.join(output))
             assert_fs_integrity(fs_type, fs_img)
 
-    def test_mkdir5(self, u_boot_console, fs_obj_mkdir):
+    def test_mkdir5(self, ubman, fs_obj_mkdir):
         """
         Test Case 5 - trying to create ".." should fail
         """
-        fs_type,fs_img = fs_obj_mkdir
-        with u_boot_console.log.section('Test Case 5 - mkdir ("..")'):
-            output = u_boot_console.run_command_list([
+        fs_type,fs_cmd_prefix,fs_img = fs_obj_mkdir
+        with ubman.log.section('Test Case 5 - mkdir ("..")'):
+            output = ubman.run_command_list([
                 'host bind 0 %s' % fs_img,
-                '%smkdir host 0:0 ..' % fs_type])
+                '%smkdir host 0:0 ..' % fs_cmd_prefix])
             assert('Unable to create a directory' in ''.join(output))
             assert_fs_integrity(fs_type, fs_img)
 
-    def test_mkdir6(self, u_boot_console, fs_obj_mkdir):
+    def test_mkdir6(self, ubman, fs_obj_mkdir):
         """
         'Test Case 6 - create as many directories as amount of directory
         entries goes beyond a cluster size)'
         """
-        fs_type,fs_img = fs_obj_mkdir
-        with u_boot_console.log.section('Test Case 6 - mkdir (create many)'):
-            output = u_boot_console.run_command_list([
+        fs_type,fs_cmd_prefix,fs_img = fs_obj_mkdir
+        with ubman.log.section('Test Case 6 - mkdir (create many)'):
+            output = ubman.run_command_list([
                 'host bind 0 %s' % fs_img,
-                '%smkdir host 0:0 dir6' % fs_type,
-                '%sls host 0:0 /' % fs_type])
+                '%smkdir host 0:0 dir6' % fs_cmd_prefix,
+                '%sls host 0:0 /' % fs_cmd_prefix])
             assert('dir6/' in ''.join(output))
 
             for i in range(0, 20):
-                output = u_boot_console.run_command(
+                output = ubman.run_command(
                     '%smkdir host 0:0 dir6/0123456789abcdef%02x'
-                    % (fs_type, i))
-            output = u_boot_console.run_command('%sls host 0:0 dir6' % fs_type)
+                    % (fs_cmd_prefix, i))
+            output = ubman.run_command('%sls host 0:0 dir6' % fs_cmd_prefix)
             assert('0123456789abcdef00/'  in output)
             assert('0123456789abcdef13/'  in output)
 
-            output = u_boot_console.run_command(
-                '%sls host 0:0 dir6/0123456789abcdef13/.' % fs_type)
+            output = ubman.run_command(
+                '%sls host 0:0 dir6/0123456789abcdef13/.' % fs_cmd_prefix)
             assert('./'   in output)
             assert('../'  in output)
 
-            output = u_boot_console.run_command(
-                '%sls host 0:0 dir6/0123456789abcdef13/..' % fs_type)
+            output = ubman.run_command(
+                '%sls host 0:0 dir6/0123456789abcdef13/..' % fs_cmd_prefix)
             assert('0123456789abcdef00/'  in output)
             assert('0123456789abcdef13/'  in output)
             assert_fs_integrity(fs_type, fs_img)
diff --git a/test/py/tests/test_fs/test_rename.py b/test/py/tests/test_fs/test_rename.py
new file mode 100644
index 00000000000..e36cff99bb7
--- /dev/null
+++ b/test/py/tests/test_fs/test_rename.py
@@ -0,0 +1,372 @@
+# SPDX-License-Identifier:      GPL-2.0+
+# Copyright 2025 Gabriel Dalimonte <gabriel.dalimonte@gmail.com>
+#
+# U-Boot File System:rename Test
+
+
+import pytest
+
+from fstest_defs import *
+from fstest_helpers import assert_fs_integrity
+
+@pytest.mark.boardspec('sandbox')
+@pytest.mark.slow
+class TestRename(object):
+    def test_rename1(self, ubman, fs_obj_rename):
+        """
+        Test Case 1 - rename a file (successful mv)
+        """
+        fs_type, fs_img, md5val = fs_obj_rename
+        with ubman.log.section('Test Case 1 - rename a file'):
+            d = 'test1'
+            src = '%s/file1' % d
+            dst = '%s/file2' % d
+            output = ubman.run_command_list([
+                'host bind 0 %s' % fs_img,
+                'setenv filesize',
+                'mv host 0:0 %s %s' % (src, dst),
+            ])
+            assert('' == ''.join(output))
+
+            output = ubman.run_command_list([
+                'load host 0:0 %x /%s' % (ADDR, dst),
+                'printenv filesize'])
+            assert('filesize=400' in output)
+
+            output = ubman.run_command_list([
+                'ls host 0:0 %s' % (d),
+            ])
+            assert('file1' not in ''.join(output))
+
+            output = ubman.run_command_list([
+                'md5sum %x $filesize' % ADDR,
+                'setenv filesize'])
+            assert(md5val['test1'] in ''.join(output))
+            assert_fs_integrity(fs_type, fs_img)
+
+    def test_rename2(self, ubman, fs_obj_rename):
+        """
+        Test Case 2 - rename a file to an existing file (successful mv)
+        """
+        fs_type, fs_img, md5val = fs_obj_rename
+        with ubman.log.section('Test Case 2 - rename a file to an existing file'):
+            d = 'test2'
+            src = '%s/file1' % d
+            dst = '%s/file_exist' % d
+            output = ubman.run_command_list([
+                'host bind 0 %s' % fs_img,
+                'setenv filesize',
+                'mv host 0:0 %s %s' % (src, dst),
+            ])
+            assert('' == ''.join(output))
+
+            output = ubman.run_command_list([
+                'load host 0:0 %x /%s' % (ADDR, dst),
+                'printenv filesize'])
+            assert('filesize=400' in output)
+
+            output = ubman.run_command_list([
+                'ls host 0:0 %s' % (d),
+            ])
+            assert('file1' not in ''.join(output))
+
+            output = ubman.run_command_list([
+                'md5sum %x $filesize' % ADDR,
+                'setenv filesize'])
+            assert(md5val['test2'] in ''.join(output))
+            assert_fs_integrity(fs_type, fs_img)
+
+    def test_rename3(self, ubman, fs_obj_rename):
+        """
+        Test Case 3 - rename a directory (successful mv)
+        """
+        fs_type, fs_img, md5val = fs_obj_rename
+        with ubman.log.section('Test Case 3 - rename a directory'):
+            d = 'test3'
+            src = '%s/dir1' % d
+            dst = '%s/dir2' % d
+            output = ubman.run_command_list([
+                'host bind 0 %s' % fs_img,
+                'setenv filesize',
+                'mv host 0:0 %s %s' % (src, dst),
+            ])
+            assert('' == ''.join(output))
+
+            output = ubman.run_command_list([
+                'load host 0:0 %x /%s/file1' % (ADDR, dst),
+                'printenv filesize'])
+            assert('filesize=400' in output)
+
+            output = ubman.run_command_list([
+                'ls host 0:0 %s' % (d),
+            ])
+            assert('dir1' not in ''.join(output))
+
+            output = ubman.run_command_list([
+                'md5sum %x $filesize' % ADDR,
+                'setenv filesize'])
+            assert(md5val['test3'] in ''.join(output))
+            assert_fs_integrity(fs_type, fs_img)
+
+    def test_rename4(self, ubman, fs_obj_rename):
+        """
+        Test Case 4 - rename a directory to an existing directory (successful
+        mv)
+        """
+        fs_type, fs_img, md5val = fs_obj_rename
+        with ubman.log.section('Test Case 4 - rename a directory to an existing directory'):
+            d = 'test4'
+            src = '%s/dir1' % d
+            dst = '%s/dir2' % d
+            output = ubman.run_command_list([
+                'host bind 0 %s' % fs_img,
+                'setenv filesize',
+                'mv host 0:0 %s %s' % (src, dst),
+            ])
+            assert('' == ''.join(output))
+
+            output = ubman.run_command_list([
+                'load host 0:0 %x /%s/dir1/file1' % (ADDR, dst),
+                'printenv filesize'])
+            assert('filesize=400' in output)
+
+            output = ubman.run_command_list([
+                'ls host 0:0 %s' % (d),
+            ])
+            assert('dir1' not in ''.join(output))
+
+            output = ubman.run_command_list([
+                'md5sum %x $filesize' % ADDR,
+                'setenv filesize'])
+            assert(md5val['test4'] in ''.join(output))
+            assert_fs_integrity(fs_type, fs_img)
+
+    def test_rename5(self, ubman, fs_obj_rename):
+        """
+        Test Case 5 - rename a directory to an existing file (failed mv)
+        """
+        fs_type, fs_img, md5val = fs_obj_rename
+        with ubman.log.section('Test Case 5 - rename a directory to an existing file'):
+            d = 'test5'
+            src = '%s/dir1' % d
+            dst = '%s/file2' % d
+            output = ubman.run_command_list([
+                'host bind 0 %s' % fs_img,
+                'setenv filesize',
+                'mv host 0:0 %s %s' % (src, dst),
+            ])
+            assert('' == ''.join(output))
+
+            output = ubman.run_command_list([
+                'ls host 0:0 %s' % (d),
+            ])
+            assert('dir1' in ''.join(output))
+            assert('file2' in ''.join(output))
+
+            output = ubman.run_command_list([
+                'load host 0:0 %x /%s' % (ADDR, dst),
+                'printenv filesize'])
+            assert('filesize=400' in output)
+
+            output = ubman.run_command_list([
+                'md5sum %x $filesize' % ADDR,
+                'setenv filesize'])
+            assert(md5val['test5'] in ''.join(output))
+            assert_fs_integrity(fs_type, fs_img)
+
+    def test_rename6(self, ubman, fs_obj_rename):
+        """
+        Test Case 6 - rename a file to an existing empty directory (failed mv)
+        """
+        fs_type, fs_img, md5val = fs_obj_rename
+        with ubman.log.section('Test Case 6 - rename a file to an existing empty directory'):
+            d = 'test6'
+            src = '%s/existing' % d
+            dst = '%s/dir2' % d
+            output = ubman.run_command_list([
+                'host bind 0 %s' % fs_img,
+                'setenv filesize',
+                'mv host 0:0 %s %s' % (src, dst),
+            ])
+            assert('' == ''.join(output))
+
+            output = ubman.run_command_list([
+                'load host 0:0 %x /%s' % (ADDR, src),
+                'printenv filesize'])
+            assert('filesize=400' in output)
+
+            output = ubman.run_command_list([
+                'ls host 0:0 %s' % (d),
+            ])
+            assert('dir2' in ''.join(output))
+            assert('existing' in ''.join(output))
+
+            output = ubman.run_command_list([
+                'md5sum %x $filesize' % ADDR,
+                'setenv filesize'])
+            assert(md5val['test6'] in ''.join(output))
+            assert_fs_integrity(fs_type, fs_img)
+
+    def test_rename7(self, ubman, fs_obj_rename):
+        """
+        Test Case 7 - rename a directory to a non-empty directory (failed mv)
+        """
+        fs_type, fs_img, md5val = fs_obj_rename
+        with ubman.log.section('Test Case 7 - rename a directory to a non-empty directory'):
+            d = 'test7'
+            src = '%s/dir1' % d
+            dst = '%s/dir2' % d
+            output = ubman.run_command_list([
+                'host bind 0 %s' % fs_img,
+                'setenv filesize',
+                'mv host 0:0 %s %s' % (src, dst),
+            ])
+            assert('' == ''.join(output))
+
+            output = ubman.run_command_list([
+                'load host 0:0 %x /%s/dir1/file1' % (ADDR, dst),
+                'printenv filesize'])
+            assert('filesize=400' in output)
+
+            output = ubman.run_command_list([
+                'ls host 0:0 %s' % (d),
+            ])
+            assert('dir1' in ''.join(output))
+            assert('dir2' in ''.join(output))
+
+            output = ubman.run_command_list([
+                'md5sum %x $filesize' % ADDR,
+                'setenv filesize'])
+            assert(md5val['test7'] in ''.join(output))
+            assert_fs_integrity(fs_type, fs_img)
+
+    def test_rename8(self, ubman, fs_obj_rename):
+        """
+        Test Case 8 - rename a directory inside itself (failed mv)
+        """
+        fs_type, fs_img, md5val = fs_obj_rename
+        with ubman.log.section('Test Case 8 - rename a directory inside itself'):
+            d = 'test8'
+            src = '%s/dir1' % d
+            dst = '%s/dir1/dir1' % d
+            output = ubman.run_command_list([
+                'host bind 0 %s' % fs_img,
+                'setenv filesize',
+                'mv host 0:0 %s %s' % (src, dst),
+            ])
+            assert('' == ''.join(output))
+
+            output = ubman.run_command_list([
+                'load host 0:0 %x /%s/file1' % (ADDR, src),
+                'printenv filesize'])
+            assert('filesize=400' in output)
+
+            output = ubman.run_command_list([
+                'ls host 0:0 %s' % (d),
+            ])
+            assert('dir1' in ''.join(output))
+
+            output = ubman.run_command_list([
+                'ls host 0:0 %s' % (src),
+            ])
+            assert('file1' in ''.join(output))
+            assert('dir1' not in ''.join(output))
+
+            output = ubman.run_command_list([
+                'md5sum %x $filesize' % ADDR,
+                'setenv filesize'])
+            assert(md5val['test8'] in ''.join(output))
+            assert_fs_integrity(fs_type, fs_img)
+
+    def test_rename9(self, ubman, fs_obj_rename):
+        """
+        Test Case 9 - rename a directory inside itself with backtracks (failed
+        mv)
+        """
+        fs_type, fs_img, md5val = fs_obj_rename
+        with ubman.log.section('Test Case 9 - rename a directory inside itself with backtracks'):
+            d = 'test9'
+            src = '%s/dir1/nested' % d
+            dst = '%s/dir1/nested/inner/./../../../dir1/nested/inner/another' % d
+            output = ubman.run_command_list([
+                'host bind 0 %s' % fs_img,
+                'setenv filesize',
+                'mv host 0:0 %s %s' % (src, dst),
+            ])
+            assert('' == ''.join(output))
+
+            output = ubman.run_command_list([
+                'ls host 0:0 %s/dir1' % (d),
+            ])
+            assert('nested' in ''.join(output))
+
+            output = ubman.run_command_list([
+                'ls host 0:0 %s' % (src),
+            ])
+            assert('inner' in ''.join(output))
+            assert('nested' not in ''.join(output))
+            assert_fs_integrity(fs_type, fs_img)
+
+    def test_rename10(self, ubman, fs_obj_rename):
+        """
+        Test Case 10 - rename a file to itself (successful mv)
+        """
+        fs_type, fs_img, md5val = fs_obj_rename
+        with ubman.log.section('Test Case 10 - rename a file to itself'):
+            d = 'test10'
+            src = '%s/file1' % d
+            output = ubman.run_command_list([
+                'host bind 0 %s' % fs_img,
+                'setenv filesize',
+                'mv host 0:0 %s %s' % (src, src),
+            ])
+            assert('' == ''.join(output))
+
+            output = ubman.run_command_list([
+                'load host 0:0 %x /%s' % (ADDR, src),
+                'printenv filesize'])
+            assert('filesize=400' in output)
+
+            output = ubman.run_command_list([
+                'ls host 0:0 %s' % (d),
+            ])
+            assert('file1' in ''.join(output))
+
+            output = ubman.run_command_list([
+                'md5sum %x $filesize' % ADDR,
+                'setenv filesize'])
+            assert(md5val['test10'] in ''.join(output))
+            assert_fs_integrity(fs_type, fs_img)
+
+    def test_rename11(self, ubman, fs_obj_rename):
+        """
+        Test Case 11 - rename a directory to itself (successful mv)
+        """
+        fs_type, fs_img, md5val = fs_obj_rename
+        with ubman.log.section('Test Case 11 - rename a directory to itself'):
+            # / at the end here is intentional. Ensures trailing / doesn't
+            # affect mv producing an updated dst path for fs_rename
+            d = 'test11/'
+            src = '%sdir1' % d
+            output = ubman.run_command_list([
+                'host bind 0 %s' % fs_img,
+                'setenv filesize',
+                'mv host 0:0 %s %s' % (src, d),
+            ])
+            assert('' == ''.join(output))
+
+            output = ubman.run_command_list([
+                'load host 0:0 %x /%s/file1' % (ADDR, src),
+                'printenv filesize'])
+            assert('filesize=400' in output)
+
+            output = ubman.run_command_list([
+                'ls host 0:0 %s' % (d),
+            ])
+            assert('dir1' in ''.join(output))
+
+            output = ubman.run_command_list([
+                'md5sum %x $filesize' % ADDR,
+                'setenv filesize'])
+            assert(md5val['test11'] in ''.join(output))
+            assert_fs_integrity(fs_type, fs_img)
diff --git a/test/py/tests/test_fs/test_squashfs/test_sqfs_load.py b/test/py/tests/test_fs/test_squashfs/test_sqfs_load.py
index 6ec6ccec6c9..33093f61ac3 100644
--- a/test/py/tests/test_fs/test_squashfs/test_sqfs_load.py
+++ b/test/py/tests/test_fs/test_squashfs/test_sqfs_load.py
@@ -27,11 +27,11 @@ def original_md5sum(path):
 
     return checksum
 
-def uboot_md5sum(u_boot_console, address, count):
+def uboot_md5sum(ubman, address, count):
     """ Runs U-Boot's md5sum command.
 
     Args:
-        u_boot_console: provides the means to interact with U-Boot's console.
+        ubman: provides the means to interact with U-Boot's console.
         address: address where the file was loaded (e.g.: $kernel_addr_r).
         count: file's size. It was named 'count' to match md5sum's respective
         argument name.
@@ -39,89 +39,89 @@ def uboot_md5sum(u_boot_console, address, count):
         The checksum of the file loaded with sqfsload as a string.
     """
 
-    out = u_boot_console.run_command('md5sum {} {}'.format(address, count))
+    out = ubman.run_command('md5sum {} {}'.format(address, count))
     checksum = out.split()[-1]
 
     return checksum
 
-def sqfs_load_files(u_boot_console, files, sizes, address):
+def sqfs_load_files(ubman, files, sizes, address):
     """ Loads files and asserts their checksums.
 
     Args:
-        u_boot_console: provides the means to interact with U-Boot's console.
+        ubman: provides the means to interact with U-Boot's console.
         files: list of files to be loaded.
         sizes: the sizes of each file.
         address: the address where the files should be loaded.
     """
-    build_dir = u_boot_console.config.build_dir
+    build_dir = ubman.config.build_dir
     for (file, size) in zip(files, sizes):
-        out = u_boot_console.run_command('sqfsload host 0 {} {}'.format(address, file))
+        out = ubman.run_command('sqfsload host 0 {} {}'.format(address, file))
 
         # check if the right amount of bytes was read
         assert size in out
 
         # compare original file's checksum against u-boot's
-        u_boot_checksum = uboot_md5sum(u_boot_console, address, hex(int(size)))
+        u_boot_checksum = uboot_md5sum(ubman, address, hex(int(size)))
         original_file_path = os.path.join(build_dir, SQFS_SRC_DIR + '/' + file)
         original_checksum = original_md5sum(original_file_path)
         assert u_boot_checksum == original_checksum
 
-def sqfs_load_files_at_root(u_boot_console):
+def sqfs_load_files_at_root(ubman):
     """ Calls sqfs_load_files passing the files at the SquashFS image's root.
 
     Args:
-        u_boot_console: provides the means to interact with U-Boot's console.
+        ubman: provides the means to interact with U-Boot's console.
     """
 
     files = ['f4096', 'f5096', 'f1000']
     sizes = ['4096', '5096', '1000']
     address = '$kernel_addr_r'
-    sqfs_load_files(u_boot_console, files, sizes, address)
+    sqfs_load_files(ubman, files, sizes, address)
 
-def sqfs_load_files_at_subdir(u_boot_console):
+def sqfs_load_files_at_subdir(ubman):
     """ Calls sqfs_load_files passing the files at the SquashFS image's subdir.
 
     This test checks if the path resolution works, since the file is not at the
     root directory.
 
     Args:
-        u_boot_console: provides the means to interact with U-Boot's console.
+        ubman: provides the means to interact with U-Boot's console.
     """
     files = ['subdir/subdir-file']
     sizes = ['100']
     address = '$kernel_addr_r'
-    sqfs_load_files(u_boot_console, files, sizes, address)
+    sqfs_load_files(ubman, files, sizes, address)
 
-def sqfs_load_non_existent_file(u_boot_console):
+def sqfs_load_non_existent_file(ubman):
     """ Calls sqfs_load_files passing an non-existent file to raise an error.
 
     This test checks if the SquashFS support won't crash if it doesn't find the
     specified file.
 
     Args:
-        u_boot_console: provides the means to interact with U-Boot's console.
+        ubman: provides the means to interact with U-Boot's console.
     """
     address = '$kernel_addr_r'
     file = 'non-existent'
-    out = u_boot_console.run_command('sqfsload host 0 {} {}'.format(address, file))
+    out = ubman.run_command('sqfsload host 0 {} {}'.format(address, file))
     assert 'Failed to load' in out
 
-def sqfs_run_all_load_tests(u_boot_console):
+def sqfs_run_all_load_tests(ubman):
     """ Runs all the previously defined test cases.
 
     Args:
-        u_boot_console: provides the means to interact with U-Boot's console.
+        ubman: provides the means to interact with U-Boot's console.
     """
-    sqfs_load_files_at_root(u_boot_console)
-    sqfs_load_files_at_subdir(u_boot_console)
-    sqfs_load_non_existent_file(u_boot_console)
+    sqfs_load_files_at_root(ubman)
+    sqfs_load_files_at_subdir(ubman)
+    sqfs_load_non_existent_file(ubman)
 
 @pytest.mark.boardspec('sandbox')
 @pytest.mark.buildconfigspec('cmd_fs_generic')
 @pytest.mark.buildconfigspec('cmd_squashfs')
 @pytest.mark.buildconfigspec('fs_squashfs')
 @pytest.mark.requiredtool('mksquashfs')
-def test_sqfs_load(u_boot_console):
+def test_sqfs_load(ubman):
     """ Executes the sqfsload test suite.
 
     First, it generates the SquashFS images, then it runs the test cases and
@@ -129,9 +129,9 @@ def test_sqfs_load(u_boot_console):
     cleaned before exiting.
 
     Args:
-        u_boot_console: provides the means to interact with U-Boot's console.
+        ubman: provides the means to interact with U-Boot's console.
     """
-    build_dir = u_boot_console.config.build_dir
+    build_dir = ubman.config.build_dir
 
     # setup test environment
     check_mksquashfs_version()
@@ -142,8 +142,8 @@ def test_sqfs_load(u_boot_console):
     for image in STANDARD_TABLE:
         try:
             image_path = os.path.join(build_dir, image)
-            u_boot_console.run_command('host bind 0 {}'.format(image_path))
-            sqfs_run_all_load_tests(u_boot_console)
+            ubman.run_command('host bind 0 {}'.format(image_path))
+            sqfs_run_all_load_tests(ubman)
         except:
             clean_all_images(build_dir)
             clean_sqfs_src_dir(build_dir)
diff --git a/test/py/tests/test_fs/test_squashfs/test_sqfs_ls.py b/test/py/tests/test_fs/test_squashfs/test_sqfs_ls.py
index a20a7d1a663..adda3b98cda 100644
--- a/test/py/tests/test_fs/test_squashfs/test_sqfs_ls.py
+++ b/test/py/tests/test_fs/test_squashfs/test_sqfs_ls.py
@@ -10,70 +10,70 @@ from sqfs_common import generate_sqfs_src_dir, make_all_images
 from sqfs_common import clean_sqfs_src_dir, clean_all_images
 from sqfs_common import check_mksquashfs_version
 
-def sqfs_ls_at_root(u_boot_console):
+def sqfs_ls_at_root(ubman):
     """ Runs sqfsls at image's root.
 
     This test checks if all the present files and directories were listed. Also,
     it checks if passing the slash or not changes the output, which it shouldn't.
 
     Args:
-        u_boot_console: provides the means to interact with U-Boot's console.
+        ubman: provides the means to interact with U-Boot's console.
     """
 
-    no_slash = u_boot_console.run_command('sqfsls host 0')
-    slash = u_boot_console.run_command('sqfsls host 0 /')
+    no_slash = ubman.run_command('sqfsls host 0')
+    slash = ubman.run_command('sqfsls host 0 /')
     assert no_slash == slash
 
     expected_lines = ['empty-dir/', '1000   f1000', '4096   f4096', '5096   f5096',
                       'subdir/', '<SYM>   sym', '4 file(s), 2 dir(s)']
 
-    output = u_boot_console.run_command('sqfsls host 0')
+    output = ubman.run_command('sqfsls host 0')
     for line in expected_lines:
         assert line in output
 
-def sqfs_ls_at_empty_dir(u_boot_console):
+def sqfs_ls_at_empty_dir(ubman):
     """ Runs sqfsls at an empty directory.
 
     This tests checks if sqfsls will print anything other than the 'Empty directory'
     message.
 
     Args:
-        u_boot_console: provides the means to interact with U-Boot's console.
+        ubman: provides the means to interact with U-Boot's console.
     """
-    assert u_boot_console.run_command('sqfsls host 0 empty-dir') == 'Empty directory.'
+    assert ubman.run_command('sqfsls host 0 empty-dir') == 'Empty directory.'
 
-def sqfs_ls_at_subdir(u_boot_console):
+def sqfs_ls_at_subdir(ubman):
     """ Runs sqfsls at the SquashFS image's subdir.
 
     This test checks if the path resolution works, since the directory is not the
     root.
 
     Args:
-        u_boot_console: provides the means to interact with U-Boot's console.
+        ubman: provides the means to interact with U-Boot's console.
     """
     expected_lines = ['100   subdir-file', '1 file(s), 0 dir(s)']
-    output = u_boot_console.run_command('sqfsls host 0 subdir')
+    output = ubman.run_command('sqfsls host 0 subdir')
     for line in expected_lines:
         assert line in output
 
-def sqfs_ls_at_symlink(u_boot_console):
+def sqfs_ls_at_symlink(ubman):
     """ Runs sqfsls at a SquashFS image's symbolic link.
 
     This test checks if the symbolic link's target resolution works.
 
     Args:
-        u_boot_console: provides the means to interact with U-Boot's console.
+        ubman: provides the means to interact with U-Boot's console.
     """
     # since sym -> subdir, the following outputs must be equal
-    output = u_boot_console.run_command('sqfsls host 0 sym')
-    output_subdir = u_boot_console.run_command('sqfsls host 0 subdir')
+    output = ubman.run_command('sqfsls host 0 sym')
+    output_subdir = ubman.run_command('sqfsls host 0 subdir')
     assert output == output_subdir
 
     expected_lines = ['100   subdir-file', '1 file(s), 0 dir(s)']
     for line in expected_lines:
         assert line in output
 
-def sqfs_ls_at_non_existent_dir(u_boot_console):
+def sqfs_ls_at_non_existent_dir(ubman):
     """ Runs sqfsls at a file and at a non-existent directory.
 
     This test checks if the SquashFS support won't crash if it doesn't find the
@@ -81,24 +81,24 @@ def sqfs_ls_at_non_existent_dir(u_boot_console):
     directory. In both cases, the output should be the same.
 
     Args:
-        u_boot_console: provides the means to interact with U-Boot's console.
+        ubman: provides the means to interact with U-Boot's console.
     """
-    out_non_existent = u_boot_console.run_command('sqfsls host 0 fff')
-    out_not_dir = u_boot_console.run_command('sqfsls host 0 f1000')
+    out_non_existent = ubman.run_command('sqfsls host 0 fff')
+    out_not_dir = ubman.run_command('sqfsls host 0 f1000')
     assert out_non_existent == out_not_dir
     assert '** Cannot find directory. **' in out_non_existent
 
-def sqfs_run_all_ls_tests(u_boot_console):
+def sqfs_run_all_ls_tests(ubman):
     """ Runs all the previously defined test cases.
 
     Args:
-        u_boot_console: provides the means to interact with U-Boot's console.
+        ubman: provides the means to interact with U-Boot's console.
     """
-    sqfs_ls_at_root(u_boot_console)
-    sqfs_ls_at_empty_dir(u_boot_console)
-    sqfs_ls_at_subdir(u_boot_console)
-    sqfs_ls_at_symlink(u_boot_console)
-    sqfs_ls_at_non_existent_dir(u_boot_console)
+    sqfs_ls_at_root(ubman)
+    sqfs_ls_at_empty_dir(ubman)
+    sqfs_ls_at_subdir(ubman)
+    sqfs_ls_at_symlink(ubman)
+    sqfs_ls_at_non_existent_dir(ubman)
 
 @pytest.mark.boardspec('sandbox')
 @pytest.mark.buildconfigspec('cmd_fs_generic')
@@ -106,7 +106,7 @@ def sqfs_run_all_ls_tests(u_boot_console):
 @pytest.mark.buildconfigspec('fs_squashfs')
 @pytest.mark.requiredtool('mksquashfs')
 @pytest.mark.singlethread
-def test_sqfs_ls(u_boot_console):
+def test_sqfs_ls(ubman):
     """ Executes the sqfsls test suite.
 
     First, it generates the SquashFS images, then it runs the test cases and
@@ -114,9 +114,9 @@ def test_sqfs_ls(u_boot_console):
     cleaned before exiting.
 
     Args:
-        u_boot_console: provides the means to interact with U-Boot's console.
+        ubman: provides the means to interact with U-Boot's console.
     """
-    build_dir = u_boot_console.config.build_dir
+    build_dir = ubman.config.build_dir
 
     # If the EFI subsystem is enabled and initialized, EFI subsystem tries to
     # add EFI boot option when the new disk is detected. If there is no EFI
@@ -125,7 +125,7 @@ def test_sqfs_ls(u_boot_console):
     # Restart U-Boot to clear the previous state.
     # TODO: Ideally EFI test cases need to be fixed, but it will
     # increase the number of system reset.
-    u_boot_console.restart_uboot()
+    ubman.restart_uboot()
 
     # setup test environment
     check_mksquashfs_version()
@@ -136,8 +136,8 @@ def test_sqfs_ls(u_boot_console):
     for image in STANDARD_TABLE:
         try:
             image_path = os.path.join(build_dir, image)
-            u_boot_console.run_command('host bind 0 {}'.format(image_path))
-            sqfs_run_all_ls_tests(u_boot_console)
+            ubman.run_command('host bind 0 {}'.format(image_path))
+            sqfs_run_all_ls_tests(ubman)
         except:
             clean_all_images(build_dir)
             clean_sqfs_src_dir(build_dir)
diff --git a/test/py/tests/test_fs/test_symlink.py b/test/py/tests/test_fs/test_symlink.py
index 9ced101a294..9ffd7e6e54d 100644
--- a/test/py/tests/test_fs/test_symlink.py
+++ b/test/py/tests/test_fs/test_symlink.py
@@ -18,38 +18,38 @@ from fstest_helpers import assert_fs_integrity
 @pytest.mark.boardspec('sandbox')
 @pytest.mark.slow
 class TestSymlink(object):
-    def test_symlink1(self, u_boot_console, fs_obj_symlink):
+    def test_symlink1(self, ubman, fs_obj_symlink):
         """
         Test Case 1 - create a link. and follow it when reading
         """
         fs_type, fs_img, md5val = fs_obj_symlink
-        with u_boot_console.log.section('Test Case 1 - create link and read'):
-            output = u_boot_console.run_command_list([
+        with ubman.log.section('Test Case 1 - create link and read'):
+            output = ubman.run_command_list([
                 'host bind 0 %s' % fs_img,
                 'setenv filesize',
                 'ln host 0:0 %s /%s.link ' % (SMALL_FILE, SMALL_FILE),
             ])
             assert('' in ''.join(output))
 
-            output = u_boot_console.run_command_list([
+            output = ubman.run_command_list([
                 '%sload host 0:0 %x /%s.link' % (fs_type, ADDR, SMALL_FILE),
                 'printenv filesize'])
             assert('filesize=100000' in ''.join(output))
 
             # Test Case 4b - Read full 1MB of small file
-            output = u_boot_console.run_command_list([
+            output = ubman.run_command_list([
                 'md5sum %x $filesize' % ADDR,
                 'setenv filesize'])
             assert(md5val[0] in ''.join(output))
             assert_fs_integrity(fs_type, fs_img)
 
-    def test_symlink2(self, u_boot_console, fs_obj_symlink):
+    def test_symlink2(self, ubman, fs_obj_symlink):
         """
         Test Case 2 - create chained links
         """
         fs_type, fs_img, md5val = fs_obj_symlink
-        with u_boot_console.log.section('Test Case 2 - create chained links'):
-            output = u_boot_console.run_command_list([
+        with ubman.log.section('Test Case 2 - create chained links'):
+            output = ubman.run_command_list([
                 'host bind 0 %s' % fs_img,
                 'setenv filesize',
                 'ln host 0:0 %s /%s.link1 ' % (SMALL_FILE, SMALL_FILE),
@@ -60,25 +60,25 @@ class TestSymlink(object):
             ])
             assert('' in ''.join(output))
 
-            output = u_boot_console.run_command_list([
+            output = ubman.run_command_list([
                 '%sload host 0:0 %x /%s.link3' % (fs_type, ADDR, SMALL_FILE),
                 'printenv filesize'])
             assert('filesize=100000' in ''.join(output))
 
             # Test Case 4b - Read full 1MB of small file
-            output = u_boot_console.run_command_list([
+            output = ubman.run_command_list([
                 'md5sum %x $filesize' % ADDR,
                 'setenv filesize'])
             assert(md5val[0] in ''.join(output))
             assert_fs_integrity(fs_type, fs_img)
 
-    def test_symlink3(self, u_boot_console, fs_obj_symlink):
+    def test_symlink3(self, ubman, fs_obj_symlink):
         """
         Test Case 3 - replace file/link with link
         """
         fs_type, fs_img, md5val = fs_obj_symlink
-        with u_boot_console.log.section('Test Case 1 - create link and read'):
-            output = u_boot_console.run_command_list([
+        with ubman.log.section('Test Case 1 - create link and read'):
+            output = ubman.run_command_list([
                 'host bind 0 %s' % fs_img,
                 'setenv filesize',
                 'ln host 0:0 %s /%s ' % (MEDIUM_FILE, SMALL_FILE),
@@ -86,45 +86,45 @@ class TestSymlink(object):
             ])
             assert('' in ''.join(output))
 
-            output = u_boot_console.run_command_list([
+            output = ubman.run_command_list([
                 '%sload host 0:0 %x /%s' % (fs_type, ADDR, SMALL_FILE),
                 'printenv filesize'])
             assert('filesize=a00000' in ''.join(output))
 
-            output = u_boot_console.run_command_list([
+            output = ubman.run_command_list([
                 'md5sum %x $filesize' % ADDR,
                 'setenv filesize'])
             assert(md5val[1] in ''.join(output))
 
-            output = u_boot_console.run_command_list([
+            output = ubman.run_command_list([
                 'ln host 0:0 %s.link /%s ' % (MEDIUM_FILE, SMALL_FILE),
                 '%sload host 0:0 %x /%s' % (fs_type, ADDR, SMALL_FILE),
                 'printenv filesize'])
             assert('filesize=a00000' in ''.join(output))
 
-            output = u_boot_console.run_command_list([
+            output = ubman.run_command_list([
                 'md5sum %x $filesize' % ADDR,
                 'setenv filesize'])
             assert(md5val[1] in ''.join(output))
             assert_fs_integrity(fs_type, fs_img)
 
-    def test_symlink4(self, u_boot_console, fs_obj_symlink):
+    def test_symlink4(self, ubman, fs_obj_symlink):
         """
         Test Case 4 - create a broken link
         """
         fs_type, fs_img, md5val = fs_obj_symlink
-        with u_boot_console.log.section('Test Case 1 - create link and read'):
+        with ubman.log.section('Test Case 1 - create link and read'):
 
-            output = u_boot_console.run_command_list([
+            output = ubman.run_command_list([
                 'setenv filesize',
                 'ln host 0:0 nowhere /link ',
             ])
             assert('' in ''.join(output))
 
-            output = u_boot_console.run_command(
+            output = ubman.run_command(
                 '%sload host 0:0 %x /link' %
                 (fs_type, ADDR))
-            with u_boot_console.disable_check('error_notification'):
-                output = u_boot_console.run_command('printenv filesize')
+            with ubman.disable_check('error_notification'):
+                output = ubman.run_command('printenv filesize')
             assert('"filesize" not defined' in ''.join(output))
             assert_fs_integrity(fs_type, fs_img)
diff --git a/test/py/tests/test_fs/test_unlink.py b/test/py/tests/test_fs/test_unlink.py
index 97aafc63bb5..1e2df3dbfd8 100644
--- a/test/py/tests/test_fs/test_unlink.py
+++ b/test/py/tests/test_fs/test_unlink.py
@@ -15,104 +15,104 @@ from fstest_helpers import assert_fs_integrity
 @pytest.mark.boardspec('sandbox')
 @pytest.mark.slow
 class TestUnlink(object):
-    def test_unlink1(self, u_boot_console, fs_obj_unlink):
+    def test_unlink1(self, ubman, fs_obj_unlink):
         """
         Test Case 1 - delete a file
         """
-        fs_type,fs_img = fs_obj_unlink
-        with u_boot_console.log.section('Test Case 1 - unlink (file)'):
-            output = u_boot_console.run_command_list([
+        fs_type,fs_cmd_prefix,fs_img = fs_obj_unlink
+        with ubman.log.section('Test Case 1 - unlink (file)'):
+            output = ubman.run_command_list([
                 'host bind 0 %s' % fs_img,
-                '%srm host 0:0 dir1/file1' % fs_type,
-                '%sls host 0:0 dir1/file1' % fs_type])
+                '%srm host 0:0 dir1/file1' % fs_cmd_prefix,
+                '%sls host 0:0 dir1/file1' % fs_cmd_prefix])
             assert('' == ''.join(output))
 
-            output = u_boot_console.run_command(
-                '%sls host 0:0 dir1/' % fs_type)
+            output = ubman.run_command(
+                '%sls host 0:0 dir1/' % fs_cmd_prefix)
             assert(not 'file1' in output)
             assert('file2' in output)
             assert_fs_integrity(fs_type, fs_img)
 
-    def test_unlink2(self, u_boot_console, fs_obj_unlink):
+    def test_unlink2(self, ubman, fs_obj_unlink):
         """
         Test Case 2 - delete many files
         """
-        fs_type,fs_img = fs_obj_unlink
-        with u_boot_console.log.section('Test Case 2 - unlink (many)'):
-            output = u_boot_console.run_command('host bind 0 %s' % fs_img)
+        fs_type,fs_cmd_prefix,fs_img = fs_obj_unlink
+        with ubman.log.section('Test Case 2 - unlink (many)'):
+            output = ubman.run_command('host bind 0 %s' % fs_img)
 
             for i in range(0, 20):
-                output = u_boot_console.run_command_list([
-                    '%srm host 0:0 dir2/0123456789abcdef%02x' % (fs_type, i),
-                    '%sls host 0:0 dir2/0123456789abcdef%02x' % (fs_type, i)])
+                output = ubman.run_command_list([
+                    '%srm host 0:0 dir2/0123456789abcdef%02x' % (fs_cmd_prefix, i),
+                    '%sls host 0:0 dir2/0123456789abcdef%02x' % (fs_cmd_prefix, i)])
                 assert('' == ''.join(output))
 
-            output = u_boot_console.run_command(
-                '%sls host 0:0 dir2' % fs_type)
+            output = ubman.run_command(
+                '%sls host 0:0 dir2' % fs_cmd_prefix)
             assert('0 file(s), 2 dir(s)' in output)
             assert_fs_integrity(fs_type, fs_img)
 
-    def test_unlink3(self, u_boot_console, fs_obj_unlink):
+    def test_unlink3(self, ubman, fs_obj_unlink):
         """
         Test Case 3 - trying to delete a non-existing file should fail
         """
-        fs_type,fs_img = fs_obj_unlink
-        with u_boot_console.log.section('Test Case 3 - unlink (non-existing)'):
-            output = u_boot_console.run_command_list([
+        fs_type,fs_cmd_prefix,fs_img = fs_obj_unlink
+        with ubman.log.section('Test Case 3 - unlink (non-existing)'):
+            output = ubman.run_command_list([
                 'host bind 0 %s' % fs_img,
-                '%srm host 0:0 dir1/nofile' % fs_type])
+                '%srm host 0:0 dir1/nofile' % fs_cmd_prefix])
             assert('nofile: doesn\'t exist' in ''.join(output))
             assert_fs_integrity(fs_type, fs_img)
 
-    def test_unlink4(self, u_boot_console, fs_obj_unlink):
+    def test_unlink4(self, ubman, fs_obj_unlink):
         """
         Test Case 4 - delete an empty directory
         """
-        fs_type,fs_img = fs_obj_unlink
-        with u_boot_console.log.section('Test Case 4 - unlink (directory)'):
-            output = u_boot_console.run_command_list([
+        fs_type,fs_cmd_prefix,fs_img = fs_obj_unlink
+        with ubman.log.section('Test Case 4 - unlink (directory)'):
+            output = ubman.run_command_list([
                 'host bind 0 %s' % fs_img,
-                '%srm host 0:0 dir4' % fs_type])
+                '%srm host 0:0 dir4' % fs_cmd_prefix])
             assert('' == ''.join(output))
 
-            output = u_boot_console.run_command(
-                '%sls host 0:0 /' % fs_type)
+            output = ubman.run_command(
+                '%sls host 0:0 /' % fs_cmd_prefix)
             assert(not 'dir4' in output)
             assert_fs_integrity(fs_type, fs_img)
 
-    def test_unlink5(self, u_boot_console, fs_obj_unlink):
+    def test_unlink5(self, ubman, fs_obj_unlink):
         """
         Test Case 5 - trying to deleting a non-empty directory ".."
         should fail
         """
-        fs_type,fs_img = fs_obj_unlink
-        with u_boot_console.log.section('Test Case 5 - unlink ("non-empty directory")'):
-            output = u_boot_console.run_command_list([
+        fs_type,fs_cmd_prefix,fs_img = fs_obj_unlink
+        with ubman.log.section('Test Case 5 - unlink ("non-empty directory")'):
+            output = ubman.run_command_list([
                 'host bind 0 %s' % fs_img,
-                '%srm host 0:0 dir5' % fs_type])
+                '%srm host 0:0 dir5' % fs_cmd_prefix])
             assert('directory is not empty' in ''.join(output))
             assert_fs_integrity(fs_type, fs_img)
 
-    def test_unlink6(self, u_boot_console, fs_obj_unlink):
+    def test_unlink6(self, ubman, fs_obj_unlink):
         """
         Test Case 6 - trying to deleting a "." should fail
         """
-        fs_type,fs_img = fs_obj_unlink
-        with u_boot_console.log.section('Test Case 6 - unlink (".")'):
-            output = u_boot_console.run_command_list([
+        fs_type,fs_cmd_prefix,fs_img = fs_obj_unlink
+        with ubman.log.section('Test Case 6 - unlink (".")'):
+            output = ubman.run_command_list([
                 'host bind 0 %s' % fs_img,
-                '%srm host 0:0 dir5/.' % fs_type])
+                '%srm host 0:0 dir5/.' % fs_cmd_prefix])
             assert('directory is not empty' in ''.join(output))
             assert_fs_integrity(fs_type, fs_img)
 
-    def test_unlink7(self, u_boot_console, fs_obj_unlink):
+    def test_unlink7(self, ubman, fs_obj_unlink):
         """
         Test Case 7 - trying to deleting a ".." should fail
         """
-        fs_type,fs_img = fs_obj_unlink
-        with u_boot_console.log.section('Test Case 7 - unlink ("..")'):
-            output = u_boot_console.run_command_list([
+        fs_type,fs_cmd_prefix,fs_img = fs_obj_unlink
+        with ubman.log.section('Test Case 7 - unlink ("..")'):
+            output = ubman.run_command_list([
                 'host bind 0 %s' % fs_img,
-                '%srm host 0:0 dir5/..' % fs_type])
+                '%srm host 0:0 dir5/..' % fs_cmd_prefix])
             assert('directory is not empty' in ''.join(output))
             assert_fs_integrity(fs_type, fs_img)
diff --git a/test/py/tests/test_gpio.py b/test/py/tests/test_gpio.py
index 3e16e636574..46b674b7653 100644
--- a/test/py/tests/test_gpio.py
+++ b/test/py/tests/test_gpio.py
@@ -5,7 +5,7 @@
 
 import pytest
 import time
-import u_boot_utils
+import utils
 
 """
 	test_gpio_input is intended to test the fix 4dbc107f4683.
@@ -14,51 +14,51 @@ import u_boot_utils
 
 @pytest.mark.boardspec('sandbox')
 @pytest.mark.buildconfigspec('cmd_gpio')
-def test_gpio_input(u_boot_console):
+def test_gpio_input(ubman):
     """Test that gpio input correctly returns the value of a gpio pin."""
 
-    response = u_boot_console.run_command('gpio input 0; echo rc:$?')
+    response = ubman.run_command('gpio input 0; echo rc:$?')
     expected_response = 'rc:0'
     assert(expected_response in response)
-    response = u_boot_console.run_command('gpio toggle 0; gpio input 0; echo rc:$?')
+    response = ubman.run_command('gpio toggle 0; gpio input 0; echo rc:$?')
     expected_response = 'rc:1'
     assert(expected_response in response)
 
 @pytest.mark.boardspec('sandbox')
 @pytest.mark.buildconfigspec('cmd_gpio')
-def test_gpio_exit_statuses(u_boot_console):
+def test_gpio_exit_statuses(ubman):
     """Test that non-input gpio commands correctly return the command
     success/failure status."""
 
     expected_response = 'rc:0'
-    response = u_boot_console.run_command('gpio clear 0; echo rc:$?')
+    response = ubman.run_command('gpio clear 0; echo rc:$?')
     assert(expected_response in response)
-    response = u_boot_console.run_command('gpio set 0; echo rc:$?')
+    response = ubman.run_command('gpio set 0; echo rc:$?')
     assert(expected_response in response)
-    response = u_boot_console.run_command('gpio toggle 0; echo rc:$?')
+    response = ubman.run_command('gpio toggle 0; echo rc:$?')
     assert(expected_response in response)
-    response = u_boot_console.run_command('gpio status -a; echo rc:$?')
+    response = ubman.run_command('gpio status -a; echo rc:$?')
     assert(expected_response in response)
 
     expected_response = 'rc:1'
-    response = u_boot_console.run_command('gpio nonexistent-command; echo rc:$?')
+    response = ubman.run_command('gpio nonexistent-command; echo rc:$?')
     assert(expected_response in response)
-    response = u_boot_console.run_command('gpio input 200; echo rc:$?')
+    response = ubman.run_command('gpio input 200; echo rc:$?')
     assert(expected_response in response)
 
 @pytest.mark.boardspec('sandbox')
 @pytest.mark.buildconfigspec('cmd_gpio')
-def test_gpio_read(u_boot_console):
+def test_gpio_read(ubman):
     """Test that gpio read correctly sets the variable to the value of a gpio pin."""
 
-    u_boot_console.run_command('gpio clear 0')
-    response = u_boot_console.run_command('gpio read var 0; echo val:$var,rc:$?')
+    ubman.run_command('gpio clear 0')
+    response = ubman.run_command('gpio read var 0; echo val:$var,rc:$?')
     expected_response = 'val:0,rc:0'
     assert(expected_response in response)
-    response = u_boot_console.run_command('gpio toggle 0; gpio read var 0; echo val:$var,rc:$?')
+    response = ubman.run_command('gpio toggle 0; gpio read var 0; echo val:$var,rc:$?')
     expected_response = 'val:1,rc:0'
     assert(expected_response in response)
-    response = u_boot_console.run_command('setenv var; gpio read var nonexistent-gpio; echo val:$var,rc:$?')
+    response = ubman.run_command('setenv var; gpio read var nonexistent-gpio; echo val:$var,rc:$?')
     expected_response = 'val:,rc:1'
     assert(expected_response in response)
 
@@ -97,7 +97,7 @@ env__gpio_dev_config = {
 
 
 @pytest.mark.buildconfigspec('cmd_gpio')
-def test_gpio_status_all_generic(u_boot_console):
+def test_gpio_status_all_generic(ubman):
     """Test the 'gpio status' command.
 
 	Displays all gpio pins available on the Board.
@@ -108,7 +108,7 @@ def test_gpio_status_all_generic(u_boot_console):
         number of such pins and mention that count in 'gpio_str_count'.
     """
 
-    f = u_boot_console.config.env.get('env__gpio_dev_config',False)
+    f = ubman.config.env.get('env__gpio_dev_config',False)
     if not f:
         pytest.skip("gpio not configured")
 
@@ -116,14 +116,14 @@ def test_gpio_status_all_generic(u_boot_console):
 
     #Display all the GPIO ports
     cmd = 'gpio status -a'
-    response = u_boot_console.run_command(cmd)
+    response = ubman.run_command(cmd)
 
     for str_value in range(1,gpio_str_count + 1):
         assert f["gpio_str_%d" %(str_value)] in response
 
 
 @pytest.mark.buildconfigspec('cmd_gpio')
-def test_gpio_set_generic(u_boot_console):
+def test_gpio_set_generic(ubman):
     """Test the 'gpio set' command.
 
 	A specific gpio pin configured by user as output
@@ -132,7 +132,7 @@ def test_gpio_set_generic(u_boot_console):
 
     """
 
-    f = u_boot_console.config.env.get('env__gpio_dev_config',False)
+    f = ubman.config.env.get('env__gpio_dev_config',False)
     if not f:
         pytest.skip("gpio not configured")
 
@@ -141,14 +141,14 @@ def test_gpio_set_generic(u_boot_console):
 
 
     cmd = 'gpio set ' + gpio_pin_adr
-    response = u_boot_console.run_command(cmd)
+    response = ubman.run_command(cmd)
     good_response = gpio_set_value
     assert good_response in response
 
 
 
 @pytest.mark.buildconfigspec('cmd_gpio')
-def test_gpio_clear_generic(u_boot_console):
+def test_gpio_clear_generic(ubman):
     """Test the 'gpio clear' command.
 
 	A specific gpio pin configured by user as output
@@ -156,7 +156,7 @@ def test_gpio_clear_generic(u_boot_console):
 	'clear' option
     """
 
-    f = u_boot_console.config.env.get('env__gpio_dev_config',False)
+    f = ubman.config.env.get('env__gpio_dev_config',False)
     if not f:
         pytest.skip("gpio not configured")
 
@@ -165,13 +165,13 @@ def test_gpio_clear_generic(u_boot_console):
 
 
     cmd = 'gpio clear ' + gpio_pin_adr
-    response = u_boot_console.run_command(cmd)
+    response = ubman.run_command(cmd)
     good_response = gpio_clear_value
     assert good_response in response
 
 
 @pytest.mark.buildconfigspec('cmd_gpio')
-def test_gpio_toggle_generic(u_boot_console):
+def test_gpio_toggle_generic(ubman):
     """Test the 'gpio toggle' command.
 
 	A specific gpio pin configured by user as output
@@ -180,7 +180,7 @@ def test_gpio_toggle_generic(u_boot_console):
     """
 
 
-    f = u_boot_console.config.env.get('env__gpio_dev_config',False)
+    f = ubman.config.env.get('env__gpio_dev_config',False)
     if not f:
         pytest.skip("gpio not configured")
 
@@ -189,18 +189,18 @@ def test_gpio_toggle_generic(u_boot_console):
     gpio_clear_value = f['gpio_clear_value'];
 
     cmd = 'gpio set ' + gpio_pin_adr
-    response = u_boot_console.run_command(cmd)
+    response = ubman.run_command(cmd)
     good_response = gpio_set_value
     assert good_response in response
 
     cmd = 'gpio toggle ' + gpio_pin_adr
-    response = u_boot_console.run_command(cmd)
+    response = ubman.run_command(cmd)
     good_response = gpio_clear_value
     assert good_response in response
 
 
 @pytest.mark.buildconfigspec('cmd_gpio')
-def test_gpio_input_generic(u_boot_console):
+def test_gpio_input_generic(ubman):
     """Test the 'gpio input' command.
 
 	Specific gpio pins configured by user as input
@@ -208,7 +208,7 @@ def test_gpio_input_generic(u_boot_console):
 	is verified for logic '1' and logic '0' states
     """
 
-    f = u_boot_console.config.env.get('env__gpio_dev_config',False)
+    f = ubman.config.env.get('env__gpio_dev_config',False)
     if not f:
         pytest.skip("gpio not configured")
 
@@ -217,7 +217,7 @@ def test_gpio_input_generic(u_boot_console):
 
 
     cmd = 'gpio input ' + gpio_pin_adr
-    response = u_boot_console.run_command(cmd)
+    response = ubman.run_command(cmd)
     good_response = gpio_clear_value
     assert good_response in response
 
@@ -227,12 +227,12 @@ def test_gpio_input_generic(u_boot_console):
 
 
     cmd = 'gpio input ' + gpio_pin_adr
-    response = u_boot_console.run_command(cmd)
+    response = ubman.run_command(cmd)
     good_response = gpio_set_value
     assert good_response in response
 
 @pytest.mark.buildconfigspec('cmd_gpio')
-def test_gpio_pins_generic(u_boot_console):
+def test_gpio_pins_generic(ubman):
     """Test various gpio related functionality, such as the input, set, clear,
        and toggle for the set of gpio pin list.
 
@@ -241,7 +241,7 @@ def test_gpio_pins_generic(u_boot_console):
        commands.
     """
 
-    f = u_boot_console.config.env.get('env__gpio_dev_config', False)
+    f = ubman.config.env.get('env__gpio_dev_config', False)
     if not f:
         pytest.skip('gpio not configured')
 
@@ -251,31 +251,31 @@ def test_gpio_pins_generic(u_boot_console):
 
     for gpin in gpio_pins:
         # gpio input
-        u_boot_console.run_command(f'gpio input {gpin}')
+        ubman.run_command(f'gpio input {gpin}')
         expected_response = f'{gpin}: input:'
-        response = u_boot_console.run_command(f'gpio status -a {gpin}')
+        response = ubman.run_command(f'gpio status -a {gpin}')
         assert expected_response in response
 
         # gpio set
-        u_boot_console.run_command(f'gpio set {gpin}')
+        ubman.run_command(f'gpio set {gpin}')
         expected_response = f'{gpin}: output: 1'
-        response = u_boot_console.run_command(f'gpio status -a {gpin}')
+        response = ubman.run_command(f'gpio status -a {gpin}')
         assert expected_response in response
 
         # gpio clear
-        u_boot_console.run_command(f'gpio clear {gpin}')
+        ubman.run_command(f'gpio clear {gpin}')
         expected_response = f'{gpin}: output: 0'
-        response = u_boot_console.run_command(f'gpio status -a {gpin}')
+        response = ubman.run_command(f'gpio status -a {gpin}')
         assert expected_response in response
 
         # gpio toggle
-        u_boot_console.run_command(f'gpio toggle {gpin}')
+        ubman.run_command(f'gpio toggle {gpin}')
         expected_response = f'{gpin}: output: 1'
-        response = u_boot_console.run_command(f'gpio status -a {gpin}')
+        response = ubman.run_command(f'gpio status -a {gpin}')
         assert expected_response in response
 
 @pytest.mark.buildconfigspec('cmd_gpio')
-def test_gpio_pins_input_output_generic(u_boot_console):
+def test_gpio_pins_input_output_generic(ubman):
     """Test gpio related functionality such as input and output for the list of
        shorted gpio pins provided as a pair of input and output pins. This test
        will fail, if the gpio pins are not shorted properly.
@@ -285,7 +285,7 @@ def test_gpio_pins_input_output_generic(u_boot_console):
        pair to be tested for gpio input output case.
     """
 
-    f = u_boot_console.config.env.get('env__gpio_dev_config', False)
+    f = ubman.config.env.get('env__gpio_dev_config', False)
     if not f:
         pytest.skip('gpio not configured')
 
@@ -294,22 +294,22 @@ def test_gpio_pins_input_output_generic(u_boot_console):
         pytest.skip('gpio pin list for input and output are not configured')
 
     for gpins in gpio_pins:
-        u_boot_console.run_command(f'gpio input {gpins[0]}')
+        ubman.run_command(f'gpio input {gpins[0]}')
         expected_response = f'{gpins[0]}: input:'
-        response = u_boot_console.run_command(f'gpio status -a {gpins[0]}')
+        response = ubman.run_command(f'gpio status -a {gpins[0]}')
         assert expected_response in response
 
-        u_boot_console.run_command(f'gpio set {gpins[1]}')
+        ubman.run_command(f'gpio set {gpins[1]}')
         expected_response = f'{gpins[1]}: output:'
-        response = u_boot_console.run_command(f'gpio status -a {gpins[1]}')
+        response = ubman.run_command(f'gpio status -a {gpins[1]}')
         assert expected_response in response
 
-        u_boot_console.run_command(f'gpio clear {gpins[1]}')
+        ubman.run_command(f'gpio clear {gpins[1]}')
         expected_response = f'{gpins[0]}: input: 0'
-        response = u_boot_console.run_command(f'gpio status -a {gpins[0]}')
+        response = ubman.run_command(f'gpio status -a {gpins[0]}')
         assert expected_response in response
 
-        u_boot_console.run_command(f'gpio set {gpins[1]}')
+        ubman.run_command(f'gpio set {gpins[1]}')
         expected_response = f'{gpins[0]}: input: 1'
-        response = u_boot_console.run_command(f'gpio status -a {gpins[0]}')
+        response = ubman.run_command(f'gpio status -a {gpins[0]}')
         assert expected_response in response
diff --git a/test/py/tests/test_gpt.py b/test/py/tests/test_gpt.py
index 6e135b663e8..cfc8f1319a9 100644
--- a/test/py/tests/test_gpt.py
+++ b/test/py/tests/test_gpt.py
@@ -6,7 +6,7 @@
 
 import os
 import pytest
-import u_boot_utils
+import utils
 
 """
 These tests rely on a 4 MB disk image, which is automatically created by
@@ -48,11 +48,11 @@ def parse_gpt_parts(disk_str):
 class GptTestDiskImage(object):
     """Disk Image used by the GPT tests."""
 
-    def __init__(self, u_boot_console):
+    def __init__(self, ubman):
         """Initialize a new GptTestDiskImage object.
 
         Args:
-            u_boot_console: A U-Boot console.
+            ubman: A U-Boot console.
 
         Returns:
             Nothing.
@@ -60,62 +60,62 @@ class GptTestDiskImage(object):
 
         filename = 'test_gpt_disk_image.bin'
 
-        persistent = u_boot_console.config.persistent_data_dir + '/' + filename
-        self.path = u_boot_console.config.result_dir  + '/' + filename
+        persistent = ubman.config.persistent_data_dir + '/' + filename
+        self.path = ubman.config.result_dir  + '/' + filename
 
-        with u_boot_utils.persistent_file_helper(u_boot_console.log, persistent):
+        with utils.persistent_file_helper(ubman.log, persistent):
             if os.path.exists(persistent):
-                u_boot_console.log.action('Disk image file ' + persistent +
+                ubman.log.action('Disk image file ' + persistent +
                     ' already exists')
             else:
-                u_boot_console.log.action('Generating ' + persistent)
+                ubman.log.action('Generating ' + persistent)
                 fd = os.open(persistent, os.O_RDWR | os.O_CREAT)
                 os.ftruncate(fd, 4194304)
                 os.close(fd)
                 cmd = ('sgdisk',
                     '--disk-guid=375a56f7-d6c9-4e81-b5f0-09d41ca89efe',
                     persistent)
-                u_boot_utils.run_and_log(u_boot_console, cmd)
+                utils.run_and_log(ubman, cmd)
                 # part1 offset 1MB size 1MB
                 cmd = ('sgdisk', '--new=1:2048:4095', '--change-name=1:part1',
                     '--partition-guid=1:33194895-67f6-4561-8457-6fdeed4f50a3',
                     '-A 1:set:2',
                     persistent)
                 # part2 offset 2MB size 1.5MB
-                u_boot_utils.run_and_log(u_boot_console, cmd)
+                utils.run_and_log(ubman, cmd)
                 cmd = ('sgdisk', '--new=2:4096:7167', '--change-name=2:part2',
                     '--partition-guid=2:cc9c6e4a-6551-4cb5-87be-3210f96c86fb',
                     persistent)
-                u_boot_utils.run_and_log(u_boot_console, cmd)
+                utils.run_and_log(ubman, cmd)
                 cmd = ('sgdisk', '--load-backup=' + persistent)
-                u_boot_utils.run_and_log(u_boot_console, cmd)
+                utils.run_and_log(ubman, cmd)
 
         cmd = ('cp', persistent, self.path)
-        u_boot_utils.run_and_log(u_boot_console, cmd)
+        utils.run_and_log(ubman, cmd)
 
 @pytest.fixture(scope='function')
-def state_disk_image(u_boot_console):
+def state_disk_image(ubman):
     """pytest fixture to provide a GptTestDiskImage object to tests.
-    This is function-scoped because it uses u_boot_console, which is also
+    This is function-scoped because it uses ubman, which is also
     function-scoped. A new disk is returned each time to prevent tests from
     interfering with each other."""
 
-    return GptTestDiskImage(u_boot_console)
+    return GptTestDiskImage(ubman)
 
 @pytest.mark.boardspec('sandbox')
 @pytest.mark.buildconfigspec('cmd_gpt')
 @pytest.mark.buildconfigspec('cmd_part')
 @pytest.mark.requiredtool('sgdisk')
-def test_gpt_read(state_disk_image, u_boot_console):
+def test_gpt_read(state_disk_image, ubman):
     """Test the gpt read command."""
 
-    u_boot_console.run_command('host bind 0 ' + state_disk_image.path)
-    output = u_boot_console.run_command('gpt read host 0')
+    ubman.run_command('host bind 0 ' + state_disk_image.path)
+    output = ubman.run_command('gpt read host 0')
     assert 'Start 1MiB, size 1MiB' in output
     assert 'Block size 512, name part1' in output
     assert 'Start 2MiB, size 1MiB' in output
     assert 'Block size 512, name part2' in output
-    output = u_boot_console.run_command('part list host 0')
+    output = ubman.run_command('part list host 0')
     assert '0x00000800	0x00000fff	"part1"' in output
     assert '0x00001000	0x00001bff	"part2"' in output
 
@@ -123,14 +123,14 @@ def test_gpt_read(state_disk_image, u_boot_console):
 @pytest.mark.buildconfigspec('cmd_gpt')
 @pytest.mark.buildconfigspec('partition_type_guid')
 @pytest.mark.requiredtool('sgdisk')
-def test_gpt_read_var(state_disk_image, u_boot_console):
+def test_gpt_read_var(state_disk_image, ubman):
     """Test the gpt read command."""
 
-    u_boot_console.run_command('host bind 0 ' + state_disk_image.path)
-    output = u_boot_console.run_command('gpt read host 0 gpt_parts')
+    ubman.run_command('host bind 0 ' + state_disk_image.path)
+    output = ubman.run_command('gpt read host 0 gpt_parts')
     assert 'success!' in output
 
-    output = u_boot_console.run_command('echo ${gpt_parts}')
+    output = ubman.run_command('echo ${gpt_parts}')
     parts = parse_gpt_parts(output.rstrip())
 
     assert parts == [
@@ -157,99 +157,99 @@ def test_gpt_read_var(state_disk_image, u_boot_console):
 @pytest.mark.boardspec('sandbox')
 @pytest.mark.buildconfigspec('cmd_gpt')
 @pytest.mark.requiredtool('sgdisk')
-def test_gpt_verify(state_disk_image, u_boot_console):
+def test_gpt_verify(state_disk_image, ubman):
     """Test the gpt verify command."""
 
-    u_boot_console.run_command('host bind 0 ' + state_disk_image.path)
-    output = u_boot_console.run_command('gpt verify host 0')
+    ubman.run_command('host bind 0 ' + state_disk_image.path)
+    output = ubman.run_command('gpt verify host 0')
     assert 'Verify GPT: success!' in output
 
 @pytest.mark.boardspec('sandbox')
 @pytest.mark.buildconfigspec('cmd_gpt')
 @pytest.mark.requiredtool('sgdisk')
-def test_gpt_repair(state_disk_image, u_boot_console):
+def test_gpt_repair(state_disk_image, ubman):
     """Test the gpt repair command."""
 
-    u_boot_console.run_command('host bind 0 ' + state_disk_image.path)
-    output = u_boot_console.run_command('gpt repair host 0')
+    ubman.run_command('host bind 0 ' + state_disk_image.path)
+    output = ubman.run_command('gpt repair host 0')
     assert 'Repairing GPT: success!' in output
 
 @pytest.mark.boardspec('sandbox')
 @pytest.mark.buildconfigspec('cmd_gpt')
 @pytest.mark.requiredtool('sgdisk')
-def test_gpt_guid(state_disk_image, u_boot_console):
+def test_gpt_guid(state_disk_image, ubman):
     """Test the gpt guid command."""
 
-    u_boot_console.run_command('host bind 0 ' + state_disk_image.path)
-    output = u_boot_console.run_command('gpt guid host 0')
+    ubman.run_command('host bind 0 ' + state_disk_image.path)
+    output = ubman.run_command('gpt guid host 0')
     assert '375a56f7-d6c9-4e81-b5f0-09d41ca89efe' in output
 
 @pytest.mark.boardspec('sandbox')
 @pytest.mark.buildconfigspec('cmd_gpt')
 @pytest.mark.requiredtool('sgdisk')
-def test_gpt_setenv(state_disk_image, u_boot_console):
+def test_gpt_setenv(state_disk_image, ubman):
     """Test the gpt setenv command."""
-    u_boot_console.run_command('host bind 0 ' + state_disk_image.path)
-    output = u_boot_console.run_command('gpt setenv host 0 part1')
+    ubman.run_command('host bind 0 ' + state_disk_image.path)
+    output = ubman.run_command('gpt setenv host 0 part1')
     assert 'success!' in output
-    output = u_boot_console.run_command('echo ${gpt_partition_addr}')
+    output = ubman.run_command('echo ${gpt_partition_addr}')
     assert output.rstrip() == '800'
-    output = u_boot_console.run_command('echo ${gpt_partition_size}')
+    output = ubman.run_command('echo ${gpt_partition_size}')
     assert output.rstrip() == '800'
-    output = u_boot_console.run_command('echo ${gpt_partition_name}')
+    output = ubman.run_command('echo ${gpt_partition_name}')
     assert output.rstrip() == 'part1'
-    output = u_boot_console.run_command('echo ${gpt_partition_entry}')
+    output = ubman.run_command('echo ${gpt_partition_entry}')
     assert output.rstrip() == '1'
-    output = u_boot_console.run_command('echo ${gpt_partition_bootable}')
+    output = ubman.run_command('echo ${gpt_partition_bootable}')
     assert output.rstrip() == '1'
 
-    output = u_boot_console.run_command('gpt setenv host 0 part2')
+    output = ubman.run_command('gpt setenv host 0 part2')
     assert 'success!' in output
-    output = u_boot_console.run_command('echo ${gpt_partition_addr}')
+    output = ubman.run_command('echo ${gpt_partition_addr}')
     assert output.rstrip() == '1000'
-    output = u_boot_console.run_command('echo ${gpt_partition_size}')
+    output = ubman.run_command('echo ${gpt_partition_size}')
     assert output.rstrip() == 'c00'
-    output = u_boot_console.run_command('echo ${gpt_partition_name}')
+    output = ubman.run_command('echo ${gpt_partition_name}')
     assert output.rstrip() == 'part2'
-    output = u_boot_console.run_command('echo ${gpt_partition_entry}')
+    output = ubman.run_command('echo ${gpt_partition_entry}')
     assert output.rstrip() == '2'
-    output = u_boot_console.run_command('echo ${gpt_partition_bootable}')
+    output = ubman.run_command('echo ${gpt_partition_bootable}')
     assert output.rstrip() == '0'
 
 @pytest.mark.boardspec('sandbox')
 @pytest.mark.buildconfigspec('cmd_gpt')
 @pytest.mark.requiredtool('sgdisk')
-def test_gpt_save_guid(state_disk_image, u_boot_console):
+def test_gpt_save_guid(state_disk_image, ubman):
     """Test the gpt guid command to save GUID into a string."""
 
-    if u_boot_console.config.buildconfig.get('config_cmd_gpt', 'n') != 'y':
+    if ubman.config.buildconfig.get('config_cmd_gpt', 'n') != 'y':
         pytest.skip('gpt command not supported')
-    u_boot_console.run_command('host bind 0 ' + state_disk_image.path)
-    output = u_boot_console.run_command('gpt guid host 0 newguid')
-    output = u_boot_console.run_command('printenv newguid')
+    ubman.run_command('host bind 0 ' + state_disk_image.path)
+    output = ubman.run_command('gpt guid host 0 newguid')
+    output = ubman.run_command('printenv newguid')
     assert '375a56f7-d6c9-4e81-b5f0-09d41ca89efe' in output
 
 @pytest.mark.boardspec('sandbox')
 @pytest.mark.buildconfigspec('cmd_gpt')
 @pytest.mark.requiredtool('sgdisk')
-def test_gpt_part_type_uuid(state_disk_image, u_boot_console):
+def test_gpt_part_type_uuid(state_disk_image, ubman):
     """Test the gpt partittion type UUID command."""
 
-    u_boot_console.run_command('host bind 0 ' + state_disk_image.path)
-    output = u_boot_console.run_command('part type host 0:1')
+    ubman.run_command('host bind 0 ' + state_disk_image.path)
+    output = ubman.run_command('part type host 0:1')
     assert '0fc63daf-8483-4772-8e79-3d69d8477de4' in output
 
 @pytest.mark.boardspec('sandbox')
 @pytest.mark.buildconfigspec('cmd_gpt')
 @pytest.mark.requiredtool('sgdisk')
-def test_gpt_part_type_save_uuid(state_disk_image, u_boot_console):
+def test_gpt_part_type_save_uuid(state_disk_image, ubman):
     """Test the gpt partittion type to save UUID into a string."""
 
-    if u_boot_console.config.buildconfig.get('config_cmd_gpt', 'n') != 'y':
+    if ubman.config.buildconfig.get('config_cmd_gpt', 'n') != 'y':
         pytest.skip('gpt command not supported')
-    u_boot_console.run_command('host bind 0 ' + state_disk_image.path)
-    output = u_boot_console.run_command('part type host 0:1 newguid')
-    output = u_boot_console.run_command('printenv newguid')
+    ubman.run_command('host bind 0 ' + state_disk_image.path)
+    output = ubman.run_command('part type host 0:1 newguid')
+    output = ubman.run_command('printenv newguid')
     assert '0fc63daf-8483-4772-8e79-3d69d8477de4' in output
 
 @pytest.mark.boardspec('sandbox')
@@ -257,17 +257,17 @@ def test_gpt_part_type_save_uuid(state_disk_image, u_boot_console):
 @pytest.mark.buildconfigspec('cmd_gpt_rename')
 @pytest.mark.buildconfigspec('cmd_part')
 @pytest.mark.requiredtool('sgdisk')
-def test_gpt_rename_partition(state_disk_image, u_boot_console):
+def test_gpt_rename_partition(state_disk_image, ubman):
     """Test the gpt rename command to write partition names."""
 
-    u_boot_console.run_command('host bind 0 ' + state_disk_image.path)
-    u_boot_console.run_command('gpt rename host 0 1 first')
-    output = u_boot_console.run_command('gpt read host 0')
+    ubman.run_command('host bind 0 ' + state_disk_image.path)
+    ubman.run_command('gpt rename host 0 1 first')
+    output = ubman.run_command('gpt read host 0')
     assert 'name first' in output
-    u_boot_console.run_command('gpt rename host 0 2 second')
-    output = u_boot_console.run_command('gpt read host 0')
+    ubman.run_command('gpt rename host 0 2 second')
+    output = ubman.run_command('gpt read host 0')
     assert 'name second' in output
-    output = u_boot_console.run_command('part list host 0')
+    output = ubman.run_command('part list host 0')
     assert '0x00000800	0x00000fff	"first"' in output
     assert '0x00001000	0x00001bff	"second"' in output
 
@@ -276,15 +276,15 @@ def test_gpt_rename_partition(state_disk_image, u_boot_console):
 @pytest.mark.buildconfigspec('cmd_gpt_rename')
 @pytest.mark.buildconfigspec('cmd_part')
 @pytest.mark.requiredtool('sgdisk')
-def test_gpt_swap_partitions(state_disk_image, u_boot_console):
+def test_gpt_swap_partitions(state_disk_image, ubman):
     """Test the gpt swap command to exchange two partition names."""
 
-    u_boot_console.run_command('host bind 0 ' + state_disk_image.path)
-    output = u_boot_console.run_command('part list host 0')
+    ubman.run_command('host bind 0 ' + state_disk_image.path)
+    output = ubman.run_command('part list host 0')
     assert '0x00000800	0x00000fff	"part1"' in output
     assert '0x00001000	0x00001bff	"part2"' in output
-    u_boot_console.run_command('gpt swap host 0 part1 part2')
-    output = u_boot_console.run_command('part list host 0')
+    ubman.run_command('gpt swap host 0 part1 part2')
+    output = ubman.run_command('part list host 0')
     assert '0x00000800	0x00000fff	"part2"' in output
     assert '0x00001000	0x00001bff	"part1"' in output
 
@@ -292,19 +292,19 @@ def test_gpt_swap_partitions(state_disk_image, u_boot_console):
 @pytest.mark.buildconfigspec('cmd_gpt_rename')
 @pytest.mark.buildconfigspec('cmd_part')
 @pytest.mark.requiredtool('sgdisk')
-def test_gpt_set_bootable(state_disk_image, u_boot_console):
+def test_gpt_set_bootable(state_disk_image, ubman):
     """Test the gpt set-bootable command."""
 
-    u_boot_console.run_command('host bind 0 ' + state_disk_image.path)
+    ubman.run_command('host bind 0 ' + state_disk_image.path)
     parts = ('part2', 'part1')
     for bootable in parts:
-        output = u_boot_console.run_command(f'gpt set-bootable host 0 {bootable}')
+        output = ubman.run_command(f'gpt set-bootable host 0 {bootable}')
         assert 'success!' in output
 
         for p in parts:
-            output = u_boot_console.run_command(f'gpt setenv host 0 {p}')
+            output = ubman.run_command(f'gpt setenv host 0 {p}')
             assert 'success!' in output
-            output = u_boot_console.run_command('echo ${gpt_partition_bootable}')
+            output = ubman.run_command('echo ${gpt_partition_bootable}')
             if p == bootable:
                 assert output.rstrip() == '1'
             else:
@@ -314,37 +314,37 @@ def test_gpt_set_bootable(state_disk_image, u_boot_console):
 @pytest.mark.buildconfigspec('cmd_gpt')
 @pytest.mark.buildconfigspec('cmd_part')
 @pytest.mark.requiredtool('sgdisk')
-def test_gpt_write(state_disk_image, u_boot_console):
+def test_gpt_write(state_disk_image, ubman):
     """Test the gpt write command."""
 
-    u_boot_console.run_command('host bind 0 ' + state_disk_image.path)
-    output = u_boot_console.run_command('gpt write host 0 "name=all,size=0"')
+    ubman.run_command('host bind 0 ' + state_disk_image.path)
+    output = ubman.run_command('gpt write host 0 "name=all,size=0"')
     assert 'Writing GPT: success!' in output
-    output = u_boot_console.run_command('part list host 0')
+    output = ubman.run_command('part list host 0')
     assert '0x00000022	0x00001fde	"all"' in output
-    output = u_boot_console.run_command('gpt write host 0 "uuid_disk=375a56f7-d6c9-4e81-b5f0-09d41ca89efe;name=first,start=1M,size=1M;name=second,start=0x200000,size=0x180000;"')
+    output = ubman.run_command('gpt write host 0 "uuid_disk=375a56f7-d6c9-4e81-b5f0-09d41ca89efe;name=first,start=1M,size=1M;name=second,start=0x200000,size=0x180000;"')
     assert 'Writing GPT: success!' in output
-    output = u_boot_console.run_command('part list host 0')
+    output = ubman.run_command('part list host 0')
     assert '0x00000800	0x00000fff	"first"' in output
     assert '0x00001000	0x00001bff	"second"' in output
-    output = u_boot_console.run_command('gpt guid host 0')
+    output = ubman.run_command('gpt guid host 0')
     assert '375a56f7-d6c9-4e81-b5f0-09d41ca89efe' in output
 
 @pytest.mark.buildconfigspec('cmd_gpt')
 @pytest.mark.buildconfigspec('cmd_gpt_rename')
 @pytest.mark.buildconfigspec('cmd_part')
 @pytest.mark.requiredtool('sgdisk')
-def test_gpt_transpose(state_disk_image, u_boot_console):
+def test_gpt_transpose(state_disk_image, ubman):
     """Test the gpt transpose command."""
 
-    u_boot_console.run_command('host bind 0 ' + state_disk_image.path)
-    output = u_boot_console.run_command('part list host 0')
+    ubman.run_command('host bind 0 ' + state_disk_image.path)
+    output = ubman.run_command('part list host 0')
     assert '1\t0x00000800\t0x00000fff\t"part1"' in output
     assert '2\t0x00001000\t0x00001bff\t"part2"' in output
 
-    output = u_boot_console.run_command('gpt transpose host 0 1 2')
+    output = ubman.run_command('gpt transpose host 0 1 2')
     assert 'success!' in output
 
-    output = u_boot_console.run_command('part list host 0')
+    output = ubman.run_command('part list host 0')
     assert '2\t0x00000800\t0x00000fff\t"part1"' in output
     assert '1\t0x00001000\t0x00001bff\t"part2"' in output
diff --git a/test/py/tests/test_handoff.py b/test/py/tests/test_handoff.py
index 038f03064a6..becd7d75cf7 100644
--- a/test/py/tests/test_handoff.py
+++ b/test/py/tests/test_handoff.py
@@ -8,8 +8,7 @@ TEST_HANDOFF_MAGIC = 0x14f93c7b
 
 @pytest.mark.boardspec('sandbox_spl')
 @pytest.mark.buildconfigspec('spl')
-def test_handoff(u_boot_console):
+def test_handoff(ubman):
     """Test that of-platdata can be generated and used in sandbox"""
-    cons = u_boot_console
-    response = cons.run_command('sb handoff')
+    response = ubman.run_command('sb handoff')
     assert ('SPL handoff magic %x' % TEST_HANDOFF_MAGIC) in response
diff --git a/test/py/tests/test_help.py b/test/py/tests/test_help.py
index 2325ff69229..12cb36b7b98 100644
--- a/test/py/tests/test_help.py
+++ b/test/py/tests/test_help.py
@@ -4,35 +4,33 @@
 
 import pytest
 
-def test_help(u_boot_console):
+def test_help(ubman):
     """Test that the "help" command can be executed."""
 
-    lines = u_boot_console.run_command('help')
-    if u_boot_console.config.buildconfig.get('config_cmd_2048', 'n') == 'y':
+    lines = ubman.run_command('help')
+    if ubman.config.buildconfig.get('config_cmd_2048', 'n') == 'y':
         assert lines.splitlines()[0] == "2048      - The 2048 game"
     else:
         assert lines.splitlines()[0] == "?         - alias for 'help'"
 
 @pytest.mark.boardspec('sandbox')
-def test_help_no_devicetree(u_boot_console):
+def test_help_no_devicetree(ubman):
     try:
-        cons = u_boot_console
-        cons.restart_uboot_with_flags([], use_dtb=False)
-        cons.run_command('help')
-        output = cons.get_spawn_output().replace('\r', '')
+        ubman.restart_uboot_with_flags([], use_dtb=False)
+        ubman.run_command('help')
+        output = ubman.get_spawn_output().replace('\r', '')
         assert 'print command description/usage' in output
     finally:
         # Restart afterward to get the normal device tree back
-        u_boot_console.restart_uboot()
+        ubman.restart_uboot()
 
 @pytest.mark.boardspec('sandbox_vpl')
-def test_vpl_help(u_boot_console):
+def test_vpl_help(ubman):
     try:
-        cons = u_boot_console
-        cons.restart_uboot()
-        cons.run_command('help')
-        output = cons.get_spawn_output().replace('\r', '')
+        ubman.restart_uboot()
+        ubman.run_command('help')
+        output = ubman.get_spawn_output().replace('\r', '')
         assert 'print command description/usage' in output
     finally:
         # Restart afterward to get the normal device tree back
-        u_boot_console.restart_uboot()
+        ubman.restart_uboot()
diff --git a/test/py/tests/test_i2c.py b/test/py/tests/test_i2c.py
index 825d0c2e6eb..69b11930ce7 100644
--- a/test/py/tests/test_i2c.py
+++ b/test/py/tests/test_i2c.py
@@ -31,8 +31,8 @@ env__i2c_eeprom_device_test = {
 }
 """
 
-def get_i2c_test_env(u_boot_console):
-    f = u_boot_console.config.env.get("env__i2c_device_test", None)
+def get_i2c_test_env(ubman):
+    f = ubman.config.env.get("env__i2c_device_test", None)
     if not f:
         pytest.skip("No I2C device to test!")
     else:
@@ -43,34 +43,34 @@ def get_i2c_test_env(u_boot_console):
         return bus_list, probe_all
 
 @pytest.mark.buildconfigspec("cmd_i2c")
-def test_i2c_bus(u_boot_console):
-    bus_list, probe = get_i2c_test_env(u_boot_console)
+def test_i2c_bus(ubman):
+    bus_list, probe = get_i2c_test_env(ubman)
     bus = random.choice(bus_list)
     expected_response = f"Bus {bus}:"
-    response = u_boot_console.run_command("i2c bus")
+    response = ubman.run_command("i2c bus")
     assert expected_response in response
 
 @pytest.mark.buildconfigspec("cmd_i2c")
-def test_i2c_dev(u_boot_console):
-    bus_list, probe = get_i2c_test_env(u_boot_console)
+def test_i2c_dev(ubman):
+    bus_list, probe = get_i2c_test_env(ubman)
     expected_response = "Current bus is"
-    response = u_boot_console.run_command("i2c dev")
+    response = ubman.run_command("i2c dev")
     assert expected_response in response
 
 @pytest.mark.buildconfigspec("cmd_i2c")
-def test_i2c_probe(u_boot_console):
-    bus_list, probe = get_i2c_test_env(u_boot_console)
+def test_i2c_probe(ubman):
+    bus_list, probe = get_i2c_test_env(ubman)
     bus = random.choice(bus_list)
     expected_response = f"Setting bus to {bus}"
-    response = u_boot_console.run_command(f"i2c dev {bus}")
+    response = ubman.run_command(f"i2c dev {bus}")
     assert expected_response in response
     expected_response = "Valid chip addresses:"
-    response = u_boot_console.run_command("i2c probe")
+    response = ubman.run_command("i2c probe")
     assert expected_response in response
 
 @pytest.mark.buildconfigspec("cmd_i2c")
-def test_i2c_eeprom(u_boot_console):
-    f = u_boot_console.config.env.get("env__i2c_eeprom_device_test", None)
+def test_i2c_eeprom(ubman):
+    f = ubman.config.env.get("env__i2c_eeprom_device_test", None)
     if not f:
         pytest.skip("No I2C eeprom to test!")
 
@@ -89,17 +89,17 @@ def test_i2c_eeprom(u_boot_console):
         )
 
     # Enable i2c mux bridge
-    u_boot_console.run_command("i2c dev %x" % bus)
-    u_boot_console.run_command("i2c probe")
-    output = u_boot_console.run_command("i2c md %x 0 5" % addr)
+    ubman.run_command("i2c dev %x" % bus)
+    ubman.run_command("i2c probe")
+    output = ubman.run_command("i2c md %x 0 5" % addr)
     assert value in output
 
 @pytest.mark.buildconfigspec("cmd_i2c")
-def test_i2c_probe_all_buses(u_boot_console):
-    bus_list, probe = get_i2c_test_env(u_boot_console)
+def test_i2c_probe_all_buses(ubman):
+    bus_list, probe = get_i2c_test_env(ubman)
     bus = random.choice(bus_list)
     expected_response = f"Bus {bus}:"
-    response = u_boot_console.run_command("i2c bus")
+    response = ubman.run_command("i2c bus")
     assert expected_response in response
 
     # Get all the bus list
@@ -109,8 +109,8 @@ def test_i2c_probe_all_buses(u_boot_console):
 
     for dev in bus_list:
         expected_response = f"Setting bus to {dev}"
-        response = u_boot_console.run_command(f"i2c dev {dev}")
+        response = ubman.run_command(f"i2c dev {dev}")
         assert expected_response in response
         expected_response = "Valid chip addresses:"
-        response = u_boot_console.run_command("i2c probe")
+        response = ubman.run_command("i2c probe")
         assert expected_response in response
diff --git a/test/py/tests/test_kconfig.py b/test/py/tests/test_kconfig.py
index 0b9e6bc3bd1..0c261d47975 100644
--- a/test/py/tests/test_kconfig.py
+++ b/test/py/tests/test_kconfig.py
@@ -4,33 +4,31 @@
 
 import pytest
 
-import u_boot_utils as util
+import utils
 
 # This is needed for Azure, since the default '..' directory is not writeable
 TMPDIR = '/tmp/test_kconfig'
 
 @pytest.mark.slow
 @pytest.mark.boardspec('sandbox')
-def test_kconfig(u_boot_console):
+def test_kconfig(ubman):
     """Test build failures when IF_ENABLED_INT() option is not enabled"""
-    cons = u_boot_console
 
     # This detects build errors in test/lib/kconfig.c
-    out = util.run_and_log(
-        cons, ['./tools/buildman/buildman', '-m', '--board', 'sandbox',
+    out = utils.run_and_log(
+        ubman, ['./tools/buildman/buildman', '-m', '--board', 'sandbox',
                '-a', 'TEST_KCONFIG', '-o', TMPDIR], ignore_errors=True)
     assert 'invalid_use_of_IF_ENABLED_INT' in out
     assert 'invalid_use_of_CONFIG_IF_ENABLED_INT' in out
 
 @pytest.mark.slow
 @pytest.mark.boardspec('sandbox_spl')
-def test_kconfig_spl(u_boot_console):
+def test_kconfig_spl(ubman):
     """Test build failures when IF_ENABLED_INT() option is not enabled"""
-    cons = u_boot_console
 
     # This detects build errors in test/lib/kconfig_spl.c
-    out = util.run_and_log(
-        cons, ['./tools/buildman/buildman', '-m', '--board', 'sandbox_spl',
+    out = utils.run_and_log(
+        ubman, ['./tools/buildman/buildman', '-m', '--board', 'sandbox_spl',
                '-a', 'TEST_KCONFIG', '-o', TMPDIR], ignore_errors=True)
     assert 'invalid_use_of_IF_ENABLED_INT' in out
 
diff --git a/test/py/tests/test_log.py b/test/py/tests/test_log.py
index 79808674bbe..4558b037e2a 100644
--- a/test/py/tests/test_log.py
+++ b/test/py/tests/test_log.py
@@ -11,7 +11,7 @@ and checks that the output is correct.
 import pytest
 
 @pytest.mark.buildconfigspec('cmd_log')
-def test_log_format(u_boot_console):
+def test_log_format(ubman):
     """Test the 'log format' and 'log rec' commands"""
     def run_with_format(fmt, expected_output):
         """Set up the log format and then write a log record
@@ -20,18 +20,17 @@ def test_log_format(u_boot_console):
             fmt: Format to use for 'log format'
             expected_output: Expected output from the 'log rec' command
         """
-        output = cons.run_command('log format %s' % fmt)
+        output = ubman.run_command('log format %s' % fmt)
         assert output == ''
-        output = cons.run_command('log rec arch notice file.c 123 func msg')
+        output = ubman.run_command('log rec arch notice file.c 123 func msg')
         assert output == expected_output
 
-    cons = u_boot_console
-    with cons.log.section('format'):
-        pad = int(u_boot_console.config.buildconfig.get('config_logf_func_pad'))
+    with ubman.log.section('format'):
+        pad = int(ubman.config.buildconfig.get('config_logf_func_pad'))
         padding = ' ' * (pad - len('func'))
 
         run_with_format('all', f'NOTICE.arch,file.c:123-{padding}func() msg')
-        output = cons.run_command('log format')
+        output = ubman.run_command('log format')
         assert output == 'Log format: clFLfm'
 
         run_with_format('fm', f'{padding}func() msg')
@@ -42,10 +41,9 @@ def test_log_format(u_boot_console):
 
 @pytest.mark.buildconfigspec('debug_uart')
 @pytest.mark.boardspec('sandbox')
-def test_log_dropped(u_boot_console):
+def test_log_dropped(ubman):
     """Test dropped 'log' message when debug_uart is activated"""
 
-    cons = u_boot_console
-    cons.restart_uboot()
-    output = cons.get_spawn_output().replace('\r', '')
+    ubman.restart_uboot()
+    output = ubman.get_spawn_output().replace('\r', '')
     assert (not 'debug: main' in output)
diff --git a/test/py/tests/test_lsblk.py b/test/py/tests/test_lsblk.py
index a719a48e6ee..babd4f9528b 100644
--- a/test/py/tests/test_lsblk.py
+++ b/test/py/tests/test_lsblk.py
@@ -7,8 +7,8 @@ import pytest
 @pytest.mark.boardspec('sandbox')
 @pytest.mark.buildconfigspec('blk')
 @pytest.mark.buildconfigspec('cmd_lsblk')
-def test_lsblk(u_boot_console):
+def test_lsblk(ubman):
     """Test that `lsblk` prints a result which includes `host`."""
-    output = u_boot_console.run_command('lsblk')
+    output = ubman.run_command('lsblk')
     assert "Block Driver" in output
     assert "sandbox_host_blk" in output
diff --git a/test/py/tests/test_md.py b/test/py/tests/test_md.py
index 83e3c546f4a..5c7bcbd420b 100644
--- a/test/py/tests/test_md.py
+++ b/test/py/tests/test_md.py
@@ -3,34 +3,34 @@
 # Copyright (c) 2015-2016, NVIDIA CORPORATION. All rights reserved.
 
 import pytest
-import u_boot_utils
+import utils
 
 @pytest.mark.buildconfigspec('cmd_memory')
-def test_md(u_boot_console):
+def test_md(ubman):
     """Test that md reads memory as expected, and that memory can be modified
     using the mw command."""
 
-    ram_base = u_boot_utils.find_ram_base(u_boot_console)
+    ram_base = utils.find_ram_base(ubman)
     addr = '%08x' % ram_base
     val = 'a5f09876'
     expected_response = addr + ': ' + val
-    u_boot_console.run_command('mw ' + addr + ' 0 10')
-    response = u_boot_console.run_command('md ' + addr + ' 10')
+    ubman.run_command('mw ' + addr + ' 0 10')
+    response = ubman.run_command('md ' + addr + ' 10')
     assert(not (expected_response in response))
-    u_boot_console.run_command('mw ' + addr + ' ' + val)
-    response = u_boot_console.run_command('md ' + addr + ' 10')
+    ubman.run_command('mw ' + addr + ' ' + val)
+    response = ubman.run_command('md ' + addr + ' 10')
     assert(expected_response in response)
 
 @pytest.mark.buildconfigspec('cmd_memory')
-def test_md_repeat(u_boot_console):
+def test_md_repeat(ubman):
     """Test command repeat (via executing an empty command) operates correctly
     for "md"; the command must repeat and dump an incrementing address."""
 
-    ram_base = u_boot_utils.find_ram_base(u_boot_console)
+    ram_base = utils.find_ram_base(ubman)
     addr_base = '%08x' % ram_base
     words = 0x10
     addr_repeat = '%08x' % (ram_base + (words * 4))
-    u_boot_console.run_command('md %s %x' % (addr_base, words))
-    response = u_boot_console.run_command('')
+    ubman.run_command('md %s %x' % (addr_base, words))
+    response = ubman.run_command('')
     expected_response = addr_repeat + ': '
     assert(expected_response in response)
diff --git a/test/py/tests/test_mdio.py b/test/py/tests/test_mdio.py
index 89711e70b55..5345f1f4c40 100644
--- a/test/py/tests/test_mdio.py
+++ b/test/py/tests/test_mdio.py
@@ -22,8 +22,8 @@ env__mdio_util_test = {
 }
 """
 
-def get_mdio_test_env(u_boot_console):
-    f = u_boot_console.config.env.get("env__mdio_util_test", None)
+def get_mdio_test_env(ubman):
+    f = ubman.config.env.get("env__mdio_util_test", None)
     if not f or len(f) == 0:
         pytest.skip("No PHY device to test!")
     else:
@@ -31,9 +31,9 @@ def get_mdio_test_env(u_boot_console):
 
 @pytest.mark.buildconfigspec("cmd_mii")
 @pytest.mark.buildconfigspec("phylib")
-def test_mdio_list(u_boot_console):
-    f = get_mdio_test_env(u_boot_console)
-    output = u_boot_console.run_command("mdio list")
+def test_mdio_list(ubman):
+    f = get_mdio_test_env(ubman)
+    output = ubman.run_command("mdio list")
     for dev, val in f.items():
         phy_addr = val.get("phy_addr")
         dev_name = val.get("device_name")
@@ -43,24 +43,24 @@ def test_mdio_list(u_boot_console):
 
 @pytest.mark.buildconfigspec("cmd_mii")
 @pytest.mark.buildconfigspec("phylib")
-def test_mdio_read(u_boot_console):
-    f = get_mdio_test_env(u_boot_console)
-    output = u_boot_console.run_command("mdio list")
+def test_mdio_read(ubman):
+    f = get_mdio_test_env(ubman)
+    output = ubman.run_command("mdio list")
     for dev, val in f.items():
         phy_addr = hex(val.get("phy_addr"))
         dev_name = val.get("device_name")
         reg = hex(val.get("reg"))
         reg_val = hex(val.get("reg_val"))
 
-        output = u_boot_console.run_command(f"mdio read {phy_addr} {reg}")
+        output = ubman.run_command(f"mdio read {phy_addr} {reg}")
         assert f"PHY at address {int(phy_addr, 16):x}:" in output
         assert f"{int(reg, 16):x} - {reg_val}" in output
 
 @pytest.mark.buildconfigspec("cmd_mii")
 @pytest.mark.buildconfigspec("phylib")
-def test_mdio_write(u_boot_console):
-    f = get_mdio_test_env(u_boot_console)
-    output = u_boot_console.run_command("mdio list")
+def test_mdio_write(ubman):
+    f = get_mdio_test_env(ubman)
+    output = ubman.run_command("mdio list")
     for dev, val in f.items():
         phy_addr = hex(val.get("phy_addr"))
         dev_name = val.get("device_name")
@@ -68,12 +68,12 @@ def test_mdio_write(u_boot_console):
         reg_val = hex(val.get("reg_val"))
         wr_val = hex(val.get("write_val"))
 
-        u_boot_console.run_command(f"mdio write {phy_addr} {reg} {wr_val}")
-        output = u_boot_console.run_command(f"mdio read {phy_addr} {reg}")
+        ubman.run_command(f"mdio write {phy_addr} {reg} {wr_val}")
+        output = ubman.run_command(f"mdio read {phy_addr} {reg}")
         assert f"PHY at address {int(phy_addr, 16):x}:" in output
         assert f"{int(reg, 16):x} - {wr_val}" in output
 
-        u_boot_console.run_command(f"mdio write {phy_addr} {reg} {reg_val}")
-        output = u_boot_console.run_command(f"mdio read {phy_addr} {reg}")
+        ubman.run_command(f"mdio write {phy_addr} {reg} {reg_val}")
+        output = ubman.run_command(f"mdio read {phy_addr} {reg}")
         assert f"PHY at address {int(phy_addr, 16):x}:" in output
         assert f"{int(reg, 16):x} - {reg_val}" in output
diff --git a/test/py/tests/test_memtest.py b/test/py/tests/test_memtest.py
index 0618d96f1be..0340edbea5a 100644
--- a/test/py/tests/test_memtest.py
+++ b/test/py/tests/test_memtest.py
@@ -24,8 +24,8 @@ env__memtest = {
 }
 """
 
-def get_memtest_env(u_boot_console):
-    f = u_boot_console.config.env.get("env__memtest", None)
+def get_memtest_env(ubman):
+    f = ubman.config.env.get("env__memtest", None)
     if not f:
         pytest.skip("memtest is not enabled!")
     else:
@@ -38,31 +38,31 @@ def get_memtest_env(u_boot_console):
         return start, end, pattern, iteration, timeout
 
 @pytest.mark.buildconfigspec("cmd_memtest")
-def test_memtest_negative(u_boot_console):
+def test_memtest_negative(ubman):
     """Negative testcase where end address is smaller than starting address and
     pattern is invalid."""
-    start, end, pattern, iteration, timeout = get_memtest_env(u_boot_console)
+    start, end, pattern, iteration, timeout = get_memtest_env(ubman)
     expected_response = "Refusing to do empty test"
-    response = u_boot_console.run_command(
+    response = ubman.run_command(
         f"mtest 2000 1000 {pattern} {hex(iteration)}"
     )
     assert expected_response in response
-    output = u_boot_console.run_command("echo $?")
+    output = ubman.run_command("echo $?")
     assert not output.endswith("0")
-    u_boot_console.run_command(f"mtest {start} {end} 'xyz' {hex(iteration)}")
-    output = u_boot_console.run_command("echo $?")
+    ubman.run_command(f"mtest {start} {end} 'xyz' {hex(iteration)}")
+    output = ubman.run_command("echo $?")
     assert not output.endswith("0")
 
 @pytest.mark.buildconfigspec("cmd_memtest")
-def test_memtest_ddr(u_boot_console):
+def test_memtest_ddr(ubman):
     """Test that md reads memory as expected, and that memory can be modified
     using the mw command."""
-    start, end, pattern, iteration, timeout = get_memtest_env(u_boot_console)
+    start, end, pattern, iteration, timeout = get_memtest_env(ubman)
     expected_response = f"Tested {str(iteration)} iteration(s) with 0 errors."
-    with u_boot_console.temporary_timeout(timeout):
-        response = u_boot_console.run_command(
+    with ubman.temporary_timeout(timeout):
+        response = ubman.run_command(
             f"mtest {start} {end} {pattern} {hex(iteration)}"
         )
         assert expected_response in response
-    output = u_boot_console.run_command("echo $?")
+    output = ubman.run_command("echo $?")
     assert output.endswith("0")
diff --git a/test/py/tests/test_mii.py b/test/py/tests/test_mii.py
index 7b6816d1089..e282add5ee8 100644
--- a/test/py/tests/test_mii.py
+++ b/test/py/tests/test_mii.py
@@ -22,21 +22,21 @@ env__mii_device_test = {
 """
 
 @pytest.mark.buildconfigspec("cmd_mii")
-def test_mii_info(u_boot_console):
-    if u_boot_console.config.env.get("env__mii_device_test_skip", False):
+def test_mii_info(ubman):
+    if ubman.config.env.get("env__mii_device_test_skip", False):
         pytest.skip("MII device test is not enabled!")
     expected_output = "PHY"
-    output = u_boot_console.run_command("mii info")
+    output = ubman.run_command("mii info")
     if not re.search(r"PHY (.+?):", output):
         pytest.skip("PHY device does not exist!")
     assert expected_output in output
 
 @pytest.mark.buildconfigspec("cmd_mii")
-def test_mii_list(u_boot_console):
-    if u_boot_console.config.env.get("env__mii_device_test_skip", False):
+def test_mii_list(ubman):
+    if ubman.config.env.get("env__mii_device_test_skip", False):
         pytest.skip("MII device test is not enabled!")
 
-    f = u_boot_console.config.env.get("env__mii_device_test", None)
+    f = ubman.config.env.get("env__mii_device_test", None)
     if not f:
         pytest.skip("No MII device to test!")
 
@@ -45,7 +45,7 @@ def test_mii_list(u_boot_console):
         pytest.fail("No MII device list provided via env__mii_device_test!")
 
     expected_output = "Current device"
-    output = u_boot_console.run_command("mii device")
+    output = ubman.run_command("mii device")
     mii_devices = (
         re.search(r"MII devices: '(.+)'", output).groups()[0].replace("'", "").split()
     )
@@ -54,39 +54,39 @@ def test_mii_list(u_boot_console):
     assert expected_output in output
 
 @pytest.mark.buildconfigspec("cmd_mii")
-def test_mii_set_device(u_boot_console):
-    test_mii_list(u_boot_console)
-    f = u_boot_console.config.env.get("env__mii_device_test", None)
+def test_mii_set_device(ubman):
+    test_mii_list(ubman)
+    f = ubman.config.env.get("env__mii_device_test", None)
     dev_list = f.get("device_list")
-    output = u_boot_console.run_command("mii device")
+    output = ubman.run_command("mii device")
     current_dev = re.search(r"Current device: '(.+?)'", output).groups()[0]
 
     for dev in dev_list:
-        u_boot_console.run_command(f"mii device {dev}")
-        output = u_boot_console.run_command("echo $?")
+        ubman.run_command(f"mii device {dev}")
+        output = ubman.run_command("echo $?")
         assert output.endswith("0")
 
-    u_boot_console.run_command(f"mii device {current_dev}")
-    output = u_boot_console.run_command("mii device")
+    ubman.run_command(f"mii device {current_dev}")
+    output = ubman.run_command("mii device")
     dev = re.search(r"Current device: '(.+?)'", output).groups()[0]
     assert current_dev == dev
 
 @pytest.mark.buildconfigspec("cmd_mii")
-def test_mii_read(u_boot_console):
-    test_mii_list(u_boot_console)
-    output = u_boot_console.run_command("mii info")
+def test_mii_read(ubman):
+    test_mii_list(ubman)
+    output = ubman.run_command("mii info")
     eth_addr = hex(int(re.search(r"PHY (.+?):", output).groups()[0], 16))
-    u_boot_console.run_command(f"mii read {eth_addr} 0")
-    output = u_boot_console.run_command("echo $?")
+    ubman.run_command(f"mii read {eth_addr} 0")
+    output = ubman.run_command("echo $?")
     assert output.endswith("0")
 
 @pytest.mark.buildconfigspec("cmd_mii")
-def test_mii_dump(u_boot_console):
-    test_mii_list(u_boot_console)
+def test_mii_dump(ubman):
+    test_mii_list(ubman)
     expected_response = "PHY control register"
-    output = u_boot_console.run_command("mii info")
+    output = ubman.run_command("mii info")
     eth_addr = hex(int(re.search(r"PHY (.+?):", output).groups()[0], 16))
-    response = u_boot_console.run_command(f"mii dump {eth_addr} 0")
+    response = ubman.run_command(f"mii dump {eth_addr} 0")
     assert expected_response in response
-    output = u_boot_console.run_command("echo $?")
+    output = ubman.run_command("echo $?")
     assert output.endswith("0")
diff --git a/test/py/tests/test_mmc.py b/test/py/tests/test_mmc.py
index 46240433884..e751a3bd36a 100644
--- a/test/py/tests/test_mmc.py
+++ b/test/py/tests/test_mmc.py
@@ -4,7 +4,7 @@
 import pytest
 import random
 import re
-import u_boot_utils
+import utils
 
 """
 Note: This test doesn't rely on boardenv_* configuration values but it can
@@ -32,19 +32,19 @@ devices = {}
 mmc_modes_name = []
 mmc_modes = []
 
-def setup_mmc_modes(cons):
+def setup_mmc_modes(ubman):
     global mmc_modes, mmc_modes_name
-    f = cons.config.env.get('env__mmc_device', None)
+    f = ubman.config.env.get('env__mmc_device', None)
     if f:
         mmc_modes_name = f.get('mmc_modes', None)
 
     # Set mmc mode to default mode (legacy), if speed mode config isn't enabled
-    if cons.config.buildconfig.get('config_mmc_speed_mode_set', 'n') != 'y':
+    if ubman.config.buildconfig.get('config_mmc_speed_mode_set', 'n') != 'y':
         mmc_modes = [0]
         return
 
     if mmc_modes_name:
-        mmc_help = cons.run_command('mmc -help')
+        mmc_help = ubman.run_command('mmc -help')
         m = re.search(r"\[MMC_LEGACY(.*\n.+])", mmc_help)
         modes = [
             x.strip()
@@ -61,16 +61,16 @@ def setup_mmc_modes(cons):
         # Set mmc mode to default mode (legacy), if it is not defined in env
         mmc_modes = [0]
 
-def setup_mmc(u_boot_console):
-    if u_boot_console.config.env.get('env__mmc_device_test_skip', True):
+def setup_mmc(ubman):
+    if ubman.config.env.get('env__mmc_device_test_skip', True):
         pytest.skip('MMC device test is not enabled')
 
-    setup_mmc_modes(u_boot_console)
+    setup_mmc_modes(ubman)
 
 @pytest.mark.buildconfigspec('cmd_mmc')
-def test_mmc_list(u_boot_console):
-    setup_mmc(u_boot_console)
-    output = u_boot_console.run_command('mmc list')
+def test_mmc_list(ubman):
+    setup_mmc(ubman)
+    output = ubman.run_command('mmc list')
     if 'No MMC device available' in output:
         pytest.skip('No SD/MMC/eMMC controller available')
 
@@ -90,7 +90,7 @@ def test_mmc_list(u_boot_console):
     mmc_set_up = True
 
 @pytest.mark.buildconfigspec('cmd_mmc')
-def test_mmc_dev(u_boot_console):
+def test_mmc_dev(ubman):
     if not mmc_set_up:
         pytest.skip('No SD/MMC/eMMC controller available')
 
@@ -99,7 +99,7 @@ def test_mmc_dev(u_boot_console):
         devices[x]['detected'] = 'yes'
 
         for y in mmc_modes:
-            output = u_boot_console.run_command('mmc dev %d 0 %d' % x, y)
+            output = ubman.run_command('mmc dev %d 0 %d' % x, y)
 
             if 'Card did not respond to voltage select' in output:
                 fail = 1
@@ -115,15 +115,15 @@ def test_mmc_dev(u_boot_console):
             pytest.fail('Card not present')
 
 @pytest.mark.buildconfigspec('cmd_mmc')
-def test_mmcinfo(u_boot_console):
+def test_mmcinfo(ubman):
     if not mmc_set_up:
         pytest.skip('No SD/MMC/eMMC controller available')
 
     for x in range(0, controllers):
         if devices[x]['detected'] == 'yes':
             for y in mmc_modes:
-                u_boot_console.run_command('mmc dev %d 0 %d' % x, y)
-                output = u_boot_console.run_command('mmcinfo')
+                ubman.run_command('mmc dev %d 0 %d' % x, y)
+                output = ubman.run_command('mmcinfo')
                 if 'busy timeout' in output:
                     pytest.skip('No SD/MMC/eMMC device present')
 
@@ -139,16 +139,16 @@ def test_mmcinfo(u_boot_console):
                     pytest.fail('MMC capacity not recognized')
 
 @pytest.mark.buildconfigspec('cmd_mmc')
-def test_mmc_info(u_boot_console):
+def test_mmc_info(ubman):
     if not mmc_set_up:
         pytest.skip('No SD/MMC/eMMC controller available')
 
     for x in range(0, controllers):
         if devices[x]['detected'] == 'yes':
             for y in mmc_modes:
-                u_boot_console.run_command('mmc dev %d 0 %d' % x, y)
+                ubman.run_command('mmc dev %d 0 %d' % x, y)
 
-                output = u_boot_console.run_command('mmc info')
+                output = ubman.run_command('mmc info')
                 assert mmc_modes_name[mmc_modes.index(y)] in output
 
                 obj = re.search(r'Capacity: (\d+|\d+[\.]?\d)', output)
@@ -162,7 +162,7 @@ def test_mmc_info(u_boot_console):
                     pytest.fail('MMC capacity not recognized')
 
 @pytest.mark.buildconfigspec('cmd_mmc')
-def test_mmc_rescan(u_boot_console):
+def test_mmc_rescan(ubman):
     if not mmc_set_up:
         pytest.skip('No SD/MMC/eMMC controller available')
 
@@ -172,15 +172,15 @@ def test_mmc_rescan(u_boot_console):
     for x in range(0, controllers):
         if devices[x]['detected'] == 'yes':
             for y in mmc_modes:
-                u_boot_console.run_command('mmc dev %d 0 %d' % x, y)
-                output = u_boot_console.run_command('mmc rescan')
+                ubman.run_command('mmc dev %d 0 %d' % x, y)
+                output = ubman.run_command('mmc rescan')
                 if output:
                     pytest.fail('mmc rescan has something to check')
-                output = u_boot_console.run_command('echo $?')
+                output = ubman.run_command('echo $?')
                 assert output.endswith('0')
 
 @pytest.mark.buildconfigspec('cmd_mmc')
-def test_mmc_part(u_boot_console):
+def test_mmc_part(ubman):
     if not mmc_set_up:
         pytest.skip('No SD/MMC/eMMC controller available')
 
@@ -189,8 +189,8 @@ def test_mmc_part(u_boot_console):
 
     for x in range(0, controllers):
         if devices[x]['detected'] == 'yes':
-            u_boot_console.run_command('mmc dev %d' % x)
-            output = u_boot_console.run_command('mmc part')
+            ubman.run_command('mmc dev %d' % x)
+            output = ubman.run_command('mmc part')
 
             lines = output.split('\n')
             part_fat = []
@@ -209,7 +209,7 @@ def test_mmc_part(u_boot_console):
                         part_fat.append(part_id)
                     elif part_type == '83':
                         print('ext(2/4) detected')
-                        output = u_boot_console.run_command(
+                        output = ubman.run_command(
                             'fstype mmc %d:%d' % x, part_id
                         )
                         if 'ext2' in output:
@@ -227,7 +227,7 @@ def test_mmc_part(u_boot_console):
 
 @pytest.mark.buildconfigspec('cmd_mmc')
 @pytest.mark.buildconfigspec('cmd_fat')
-def test_mmc_fatls_fatinfo(u_boot_console):
+def test_mmc_fatls_fatinfo(ubman):
     if not mmc_set_up:
         pytest.skip('No SD/MMC/eMMC controller available')
 
@@ -246,8 +246,8 @@ def test_mmc_fatls_fatinfo(u_boot_console):
 
             for part in partitions:
                 for y in mmc_modes:
-                    u_boot_console.run_command('mmc dev %d %d %d' % x, part, y)
-                    output = u_boot_console.run_command(
+                    ubman.run_command('mmc dev %d %d %d' % x, part, y)
+                    output = ubman.run_command(
                             'fatls mmc %d:%s' % (x, part))
                     if 'Unrecognized filesystem type' in output:
                         partitions.remove(part)
@@ -255,7 +255,7 @@ def test_mmc_fatls_fatinfo(u_boot_console):
 
                     if not re.search(r'\d file\(s\), \d dir\(s\)', output):
                         pytest.fail('%s read failed on device %d' % (fs.upper, x))
-                    output = u_boot_console.run_command(
+                    output = ubman.run_command(
                             'fatinfo mmc %d:%s' % (x, part))
                     string = 'Filesystem: %s' % fs.upper
                     if re.search(string, output):
@@ -269,7 +269,7 @@ def test_mmc_fatls_fatinfo(u_boot_console):
 @pytest.mark.buildconfigspec('cmd_mmc')
 @pytest.mark.buildconfigspec('cmd_fat')
 @pytest.mark.buildconfigspec('cmd_memory')
-def test_mmc_fatload_fatwrite(u_boot_console):
+def test_mmc_fatload_fatwrite(ubman):
     if not mmc_set_up:
         pytest.skip('No SD/MMC/eMMC controller available')
 
@@ -288,14 +288,14 @@ def test_mmc_fatload_fatwrite(u_boot_console):
 
             for part in partitions:
                 for y in mmc_modes:
-                    u_boot_console.run_command('mmc dev %d %d %d' % x, part, y)
+                    ubman.run_command('mmc dev %d %d %d' % x, part, y)
                     part_detect = 1
-                    addr = u_boot_utils.find_ram_base(u_boot_console)
+                    addr = utils.find_ram_base(ubman)
                     devices[x]['addr_%d' % part] = addr
                     size = random.randint(4, 1 * 1024 * 1024)
                     devices[x]['size_%d' % part] = size
                     # count CRC32
-                    output = u_boot_console.run_command('crc32 %x %x' % (addr, size))
+                    output = ubman.run_command('crc32 %x %x' % (addr, size))
                     m = re.search('==> (.+?)', output)
                     if not m:
                         pytest.fail('CRC32 failed')
@@ -304,7 +304,7 @@ def test_mmc_fatload_fatwrite(u_boot_console):
                     # do write
                     file = '%s_%d' % ('uboot_test', size)
                     devices[x]['file_%d' % part] = file
-                    output = u_boot_console.run_command(
+                    output = ubman.run_command(
                         '%swrite mmc %d:%s %x %s %x' % (fs, x, part, addr, file, size)
                     )
                     assert 'Unable to write' not in output
@@ -314,12 +314,12 @@ def test_mmc_fatload_fatwrite(u_boot_console):
                     assert expected_text in output
 
                     alignment = int(
-                        u_boot_console.config.buildconfig.get(
+                        ubman.config.buildconfig.get(
                             'config_sys_cacheline_size', 128
                         )
                     )
                     offset = random.randrange(alignment, 1024, alignment)
-                    output = u_boot_console.run_command(
+                    output = ubman.run_command(
                         '%sload mmc %d:%s %x %s' % (fs, x, part, addr + offset, file)
                     )
                     assert 'Invalid FAT entry' not in output
@@ -328,7 +328,7 @@ def test_mmc_fatload_fatwrite(u_boot_console):
                     expected_text = '%d bytes read' % size
                     assert expected_text in output
 
-                    output = u_boot_console.run_command(
+                    output = ubman.run_command(
                         'crc32 %x $filesize' % (addr + offset)
                     )
                     assert expected_crc32 in output
@@ -338,7 +338,7 @@ def test_mmc_fatload_fatwrite(u_boot_console):
 
 @pytest.mark.buildconfigspec('cmd_mmc')
 @pytest.mark.buildconfigspec('cmd_ext4')
-def test_mmc_ext4ls(u_boot_console):
+def test_mmc_ext4ls(ubman):
     if not mmc_set_up:
         pytest.skip('No SD/MMC/eMMC controller available')
 
@@ -357,8 +357,8 @@ def test_mmc_ext4ls(u_boot_console):
 
             for part in partitions:
                 for y in mmc_modes:
-                    u_boot_console.run_command('mmc dev %d %d %d' % x, part, y)
-                    output = u_boot_console.run_command(
+                    ubman.run_command('mmc dev %d %d %d' % x, part, y)
+                    output = ubman.run_command(
                         '%sls mmc %d:%s' % (fs, x, part)
                     )
                     if 'Unrecognized filesystem type' in output:
@@ -373,7 +373,7 @@ def test_mmc_ext4ls(u_boot_console):
 @pytest.mark.buildconfigspec('cmd_ext4')
 @pytest.mark.buildconfigspec('ext4_write')
 @pytest.mark.buildconfigspec('cmd_memory')
-def test_mmc_ext4load_ext4write(u_boot_console):
+def test_mmc_ext4load_ext4write(ubman):
     if not mmc_set_up:
         pytest.skip('No SD/MMC/eMMC controller available')
 
@@ -392,14 +392,14 @@ def test_mmc_ext4load_ext4write(u_boot_console):
 
             for part in partitions:
                 for y in mmc_modes:
-                    u_boot_console.run_command('mmc dev %d %d %d' % x, part, y)
+                    ubman.run_command('mmc dev %d %d %d' % x, part, y)
                     part_detect = 1
-                    addr = u_boot_utils.find_ram_base(u_boot_console)
+                    addr = utils.find_ram_base(ubman)
                     devices[x]['addr_%d' % part] = addr
                     size = random.randint(4, 1 * 1024 * 1024)
                     devices[x]['size_%d' % part] = size
                     # count CRC32
-                    output = u_boot_console.run_command('crc32 %x %x' % (addr, size))
+                    output = ubman.run_command('crc32 %x %x' % (addr, size))
                     m = re.search('==> (.+?)', output)
                     if not m:
                         pytest.fail('CRC32 failed')
@@ -409,7 +409,7 @@ def test_mmc_ext4load_ext4write(u_boot_console):
                     # do write
                     file = '%s_%d' % ('uboot_test', size)
                     devices[x]['file_%d' % part] = file
-                    output = u_boot_console.run_command(
+                    output = ubman.run_command(
                         '%swrite mmc %d:%s %x /%s %x' % (fs, x, part, addr, file, size)
                     )
                     assert 'Unable to write' not in output
@@ -419,13 +419,13 @@ def test_mmc_ext4load_ext4write(u_boot_console):
                     assert expected_text in output
 
                     offset = random.randrange(128, 1024, 128)
-                    output = u_boot_console.run_command(
+                    output = ubman.run_command(
                         '%sload mmc %d:%s %x /%s' % (fs, x, part, addr + offset, file)
                     )
                     expected_text = '%d bytes read' % size
                     assert expected_text in output
 
-                    output = u_boot_console.run_command(
+                    output = ubman.run_command(
                         'crc32 %x $filesize' % (addr + offset)
                     )
                     assert expected_crc32 in output
@@ -435,7 +435,7 @@ def test_mmc_ext4load_ext4write(u_boot_console):
 
 @pytest.mark.buildconfigspec('cmd_mmc')
 @pytest.mark.buildconfigspec('cmd_ext2')
-def test_mmc_ext2ls(u_boot_console):
+def test_mmc_ext2ls(ubman):
     if not mmc_set_up:
         pytest.skip('No SD/MMC/eMMC controller available')
 
@@ -454,9 +454,9 @@ def test_mmc_ext2ls(u_boot_console):
 
             for part in partitions:
                 for y in mmc_modes:
-                    u_boot_console.run_command('mmc dev %d %d %d' % x, part, y)
+                    ubman.run_command('mmc dev %d %d %d' % x, part, y)
                     part_detect = 1
-                    output = u_boot_console.run_command(
+                    output = ubman.run_command(
                         '%sls mmc %d:%s' % (fs, x, part)
                     )
                     if 'Unrecognized filesystem type' in output:
@@ -472,7 +472,7 @@ def test_mmc_ext2ls(u_boot_console):
 @pytest.mark.buildconfigspec('cmd_ext4')
 @pytest.mark.buildconfigspec('ext4_write')
 @pytest.mark.buildconfigspec('cmd_memory')
-def test_mmc_ext2load(u_boot_console):
+def test_mmc_ext2load(ubman):
     if not mmc_set_up:
         pytest.skip('No SD/MMC/eMMC controller available')
 
@@ -491,7 +491,7 @@ def test_mmc_ext2load(u_boot_console):
 
             for part in partitions:
                 for y in mmc_modes:
-                    u_boot_console.run_command('mmc dev %d %d %d' % x, part, y)
+                    ubman.run_command('mmc dev %d %d %d' % x, part, y)
                     part_detect = 1
                     addr = devices[x]['addr_%d' % part]
                     size = devices[x]['size_%d' % part]
@@ -499,13 +499,13 @@ def test_mmc_ext2load(u_boot_console):
                     file = devices[x]['file_%d' % part]
 
                     offset = random.randrange(128, 1024, 128)
-                    output = u_boot_console.run_command(
+                    output = ubman.run_command(
                         '%sload mmc %d:%s %x /%s' % (fs, x, part, addr + offset, file)
                     )
                     expected_text = '%d bytes read' % size
                     assert expected_text in output
 
-                    output = u_boot_console.run_command(
+                    output = ubman.run_command(
                         'crc32 %x $filesize' % (addr + offset)
                     )
                     assert expected_crc32 in output
@@ -515,7 +515,7 @@ def test_mmc_ext2load(u_boot_console):
 
 @pytest.mark.buildconfigspec('cmd_mmc')
 @pytest.mark.buildconfigspec('cmd_fs_generic')
-def test_mmc_ls(u_boot_console):
+def test_mmc_ls(ubman):
     if not mmc_set_up:
         pytest.skip('No SD/MMC/eMMC controller available')
 
@@ -534,9 +534,9 @@ def test_mmc_ls(u_boot_console):
 
                 for part in partitions:
                     for y in mmc_modes:
-                        u_boot_console.run_command('mmc dev %d %d %d' % x, part, y)
+                        ubman.run_command('mmc dev %d %d %d' % x, part, y)
                         part_detect = 1
-                        output = u_boot_console.run_command('ls mmc %d:%s' % (x, part))
+                        output = ubman.run_command('ls mmc %d:%s' % (x, part))
                         if re.search(r'No \w+ table on this device', output):
                             pytest.fail(
                                 '%s: Partition table not found %d' % (fs.upper(), x)
@@ -547,7 +547,7 @@ def test_mmc_ls(u_boot_console):
 
 @pytest.mark.buildconfigspec('cmd_mmc')
 @pytest.mark.buildconfigspec('cmd_fs_generic')
-def test_mmc_load(u_boot_console):
+def test_mmc_load(ubman):
     if not mmc_set_up:
         pytest.skip('No SD/MMC/eMMC controller available')
 
@@ -566,7 +566,7 @@ def test_mmc_load(u_boot_console):
 
                 for part in partitions:
                     for y in mmc_modes:
-                        u_boot_console.run_command('mmc dev %d %d %d' % x, part, y)
+                        ubman.run_command('mmc dev %d %d %d' % x, part, y)
                         part_detect = 1
                         addr = devices[x]['addr_%d' % part]
                         size = devices[x]['size_%d' % part]
@@ -574,13 +574,13 @@ def test_mmc_load(u_boot_console):
                         file = devices[x]['file_%d' % part]
 
                         offset = random.randrange(128, 1024, 128)
-                        output = u_boot_console.run_command(
+                        output = ubman.run_command(
                             'load mmc %d:%s %x /%s' % (x, part, addr + offset, file)
                         )
                         expected_text = '%d bytes read' % size
                         assert expected_text in output
 
-                        output = u_boot_console.run_command(
+                        output = ubman.run_command(
                             'crc32 %x $filesize' % (addr + offset)
                         )
                         assert expected_crc32 in output
@@ -590,7 +590,7 @@ def test_mmc_load(u_boot_console):
 
 @pytest.mark.buildconfigspec('cmd_mmc')
 @pytest.mark.buildconfigspec('cmd_fs_generic')
-def test_mmc_save(u_boot_console):
+def test_mmc_save(ubman):
     if not mmc_set_up:
         pytest.skip('No SD/MMC/eMMC controller available')
 
@@ -609,14 +609,14 @@ def test_mmc_save(u_boot_console):
 
                 for part in partitions:
                     for y in mmc_modes:
-                        u_boot_console.run_command('mmc dev %d %d %d' % x, part, y)
+                        ubman.run_command('mmc dev %d %d %d' % x, part, y)
                         part_detect = 1
                         addr = devices[x]['addr_%d' % part]
                         size = 0
                         file = devices[x]['file_%d' % part]
 
                         offset = random.randrange(128, 1024, 128)
-                        output = u_boot_console.run_command(
+                        output = ubman.run_command(
                             'save mmc %d:%s %x /%s %d'
                             % (x, part, addr + offset, file, size)
                         )
@@ -629,11 +629,11 @@ def test_mmc_save(u_boot_console):
 @pytest.mark.buildconfigspec('cmd_mmc')
 @pytest.mark.buildconfigspec('cmd_fat')
 @pytest.mark.buildconfigspec('cmd_memory')
-def test_mmc_fat_read_write_files(u_boot_console):
-    test_mmc_list(u_boot_console)
-    test_mmc_dev(u_boot_console)
-    test_mmcinfo(u_boot_console)
-    test_mmc_part(u_boot_console)
+def test_mmc_fat_read_write_files(ubman):
+    test_mmc_list(ubman)
+    test_mmc_dev(ubman)
+    test_mmcinfo(ubman)
+    test_mmc_part(ubman)
     if not mmc_set_up:
         pytest.skip('No SD/MMC/eMMC controller available')
 
@@ -656,9 +656,9 @@ def test_mmc_fat_read_write_files(u_boot_console):
 
             for part in partitions:
                 for y in mmc_modes:
-                    u_boot_console.run_command('mmc dev %d %d %d' % x, part, y)
+                    ubman.run_command('mmc dev %d %d %d' % x, part, y)
                     part_detect = 1
-                    addr = u_boot_utils.find_ram_base(u_boot_console)
+                    addr = utils.find_ram_base(ubman)
                     count_f = 0
                     addr_l = []
                     size_l = []
@@ -671,7 +671,7 @@ def test_mmc_fat_read_write_files(u_boot_console):
                         size_l.append(random.randint(4, 1 * 1024 * 1024))
 
                         # CRC32 count
-                        output = u_boot_console.run_command(
+                        output = ubman.run_command(
                             'crc32 %x %x' % (addr_l[count_f], size_l[count_f])
                         )
                         m = re.search('==> (.+?)', output)
@@ -683,7 +683,7 @@ def test_mmc_fat_read_write_files(u_boot_console):
                         file_l.append(
                             '%s_%d_%d' % ('uboot_test', count_f, size_l[count_f])
                         )
-                        output = u_boot_console.run_command(
+                        output = ubman.run_command(
                             '%swrite mmc %d:%s %x %s %x'
                             % (
                                 fs,
@@ -706,14 +706,14 @@ def test_mmc_fat_read_write_files(u_boot_console):
                     count_f = 0
                     while count_f < num_files:
                         alignment = int(
-                            u_boot_console.config.buildconfig.get(
+                            ubman.config.buildconfig.get(
                                 'config_sys_cacheline_size', 128
                             )
                         )
                         offset_l.append(random.randrange(alignment, 1024, alignment))
 
                         # Read operation
-                        output = u_boot_console.run_command(
+                        output = ubman.run_command(
                             '%sload mmc %d:%s %x %s'
                             % (
                                 fs,
@@ -729,7 +729,7 @@ def test_mmc_fat_read_write_files(u_boot_console):
                         expected_text = '%d bytes read' % size_l[count_f]
                         assert expected_text in output
 
-                        output = u_boot_console.run_command(
+                        output = ubman.run_command(
                             'crc32 %x $filesize' % (addr_l[count_f] + offset_l[count_f])
                         )
                         assert crc32_l[count_f] in output
diff --git a/test/py/tests/test_mmc_rd.py b/test/py/tests/test_mmc_rd.py
index ea652f91361..cd1e299aa9d 100644
--- a/test/py/tests/test_mmc_rd.py
+++ b/test/py/tests/test_mmc_rd.py
@@ -7,7 +7,7 @@
 
 import pytest
 import time
-import u_boot_utils
+import utils
 
 """
 This test relies on boardenv_* to containing configuration values to define
@@ -105,11 +105,11 @@ env__mmc_rd_configs = (
 )
 """
 
-def mmc_dev(u_boot_console, is_emmc, devid, partid):
+def mmc_dev(ubman, is_emmc, devid, partid):
     """Run the "mmc dev" command.
 
     Args:
-        u_boot_console: A U-Boot console connection.
+        ubman: A U-Boot console connection.
         is_emmc: Whether the device is eMMC
         devid: Device ID
         partid: Partition ID
@@ -122,7 +122,7 @@ def mmc_dev(u_boot_console, is_emmc, devid, partid):
     cmd = 'mmc dev %d' % devid
     if is_emmc:
         cmd += ' %d' % partid
-    response = u_boot_console.run_command(cmd)
+    response = ubman.run_command(cmd)
     assert 'no card present' not in response
     if is_emmc:
         partid_response = '(part %d)' % partid
@@ -132,11 +132,11 @@ def mmc_dev(u_boot_console, is_emmc, devid, partid):
     assert good_response in response
 
 @pytest.mark.buildconfigspec('cmd_mmc')
-def test_mmc_dev(u_boot_console, env__mmc_dev_config):
+def test_mmc_dev(ubman, env__mmc_dev_config):
     """Test the "mmc dev" command.
 
     Args:
-        u_boot_console: A U-Boot console connection.
+        ubman: A U-Boot console connection.
         env__mmc_dev_config: The single MMC configuration on which
             to run the test. See the file-level comment above for details
             of the format.
@@ -150,14 +150,14 @@ def test_mmc_dev(u_boot_console, env__mmc_dev_config):
     partid = env__mmc_dev_config.get('partid', 0)
 
     # Select MMC device
-    mmc_dev(u_boot_console, is_emmc, devid, partid)
+    mmc_dev(ubman, is_emmc, devid, partid)
 
 @pytest.mark.buildconfigspec('cmd_mmc')
-def test_mmc_rescan(u_boot_console, env__mmc_dev_config):
+def test_mmc_rescan(ubman, env__mmc_dev_config):
     """Test the "mmc rescan" command.
 
     Args:
-        u_boot_console: A U-Boot console connection.
+        ubman: A U-Boot console connection.
         env__mmc_dev_config: The single MMC configuration on which
             to run the test. See the file-level comment above for details
             of the format.
@@ -171,19 +171,19 @@ def test_mmc_rescan(u_boot_console, env__mmc_dev_config):
     partid = env__mmc_dev_config.get('partid', 0)
 
     # Select MMC device
-    mmc_dev(u_boot_console, is_emmc, devid, partid)
+    mmc_dev(ubman, is_emmc, devid, partid)
 
     # Rescan MMC device
     cmd = 'mmc rescan'
-    response = u_boot_console.run_command(cmd)
+    response = ubman.run_command(cmd)
     assert 'no card present' not in response
 
 @pytest.mark.buildconfigspec('cmd_mmc')
-def test_mmc_info(u_boot_console, env__mmc_dev_config):
+def test_mmc_info(ubman, env__mmc_dev_config):
     """Test the "mmc info" command.
 
     Args:
-        u_boot_console: A U-Boot console connection.
+        ubman: A U-Boot console connection.
         env__mmc_dev_config: The single MMC configuration on which
             to run the test. See the file-level comment above for details
             of the format.
@@ -201,11 +201,11 @@ def test_mmc_info(u_boot_console, env__mmc_dev_config):
     info_buswidth = env__mmc_dev_config['info_buswidth']
 
     # Select MMC device
-    mmc_dev(u_boot_console, is_emmc, devid, partid)
+    mmc_dev(ubman, is_emmc, devid, partid)
 
     # Read MMC device information
     cmd = 'mmc info'
-    response = u_boot_console.run_command(cmd)
+    response = ubman.run_command(cmd)
     good_response = "Device: %s" % info_device
     assert good_response in response
     good_response = "Bus Speed: %s" % info_speed
@@ -216,11 +216,11 @@ def test_mmc_info(u_boot_console, env__mmc_dev_config):
     assert good_response in response
 
 @pytest.mark.buildconfigspec('cmd_mmc')
-def test_mmc_rd(u_boot_console, env__mmc_rd_config):
+def test_mmc_rd(ubman, env__mmc_rd_config):
     """Test the "mmc read" command.
 
     Args:
-        u_boot_console: A U-Boot console connection.
+        ubman: A U-Boot console connection.
         env__mmc_rd_config: The single MMC configuration on which
             to run the test. See the file-level comment above for details
             of the format.
@@ -238,32 +238,32 @@ def test_mmc_rd(u_boot_console, env__mmc_rd_config):
     read_duration_max = env__mmc_rd_config.get('read_duration_max', 0)
 
     count_bytes = count_sectors * 512
-    bcfg = u_boot_console.config.buildconfig
+    bcfg = ubman.config.buildconfig
     has_cmd_memory = bcfg.get('config_cmd_memory', 'n') == 'y'
     has_cmd_crc32 = bcfg.get('config_cmd_crc32', 'n') == 'y'
-    ram_base = u_boot_utils.find_ram_base(u_boot_console)
+    ram_base = utils.find_ram_base(ubman)
     addr = '0x%08x' % ram_base
 
     # Select MMC device
-    mmc_dev(u_boot_console, is_emmc, devid, partid)
+    mmc_dev(ubman, is_emmc, devid, partid)
 
     # Clear target RAM
     if expected_crc32:
         if has_cmd_memory and has_cmd_crc32:
             cmd = 'mw.b %s 0 0x%x' % (addr, count_bytes)
-            u_boot_console.run_command(cmd)
+            ubman.run_command(cmd)
 
             cmd = 'crc32 %s 0x%x' % (addr, count_bytes)
-            response = u_boot_console.run_command(cmd)
+            response = ubman.run_command(cmd)
             assert expected_crc32 not in response
         else:
-            u_boot_console.log.warning(
+            ubman.log.warning(
                 'CONFIG_CMD_MEMORY or CONFIG_CMD_CRC32 != y: Skipping RAM clear')
 
     # Read data
     cmd = 'mmc read %s %x %x' % (addr, sector, count_sectors)
     tstart = time.time()
-    response = u_boot_console.run_command(cmd)
+    response = ubman.run_command(cmd)
     tend = time.time()
     good_response = 'MMC read: dev # %d, block # %d, count %d ... %d blocks read: OK' % (
         devid, sector, count_sectors, count_sectors)
@@ -273,14 +273,14 @@ def test_mmc_rd(u_boot_console, env__mmc_rd_config):
     if expected_crc32:
         if has_cmd_crc32:
             cmd = 'crc32 %s 0x%x' % (addr, count_bytes)
-            response = u_boot_console.run_command(cmd)
+            response = ubman.run_command(cmd)
             assert expected_crc32 in response
         else:
-            u_boot_console.log.warning('CONFIG_CMD_CRC32 != y: Skipping check')
+            ubman.log.warning('CONFIG_CMD_CRC32 != y: Skipping check')
 
     # Check if the command did not take too long
     if read_duration_max:
         elapsed = tend - tstart
-        u_boot_console.log.info('Reading %d bytes took %f seconds' %
+        ubman.log.info('Reading %d bytes took %f seconds' %
                                 (count_bytes, elapsed))
         assert elapsed <= (read_duration_max - 0.01)
diff --git a/test/py/tests/test_mmc_wr.py b/test/py/tests/test_mmc_wr.py
index 05e5c1ee85d..41a75f885e1 100644
--- a/test/py/tests/test_mmc_wr.py
+++ b/test/py/tests/test_mmc_wr.py
@@ -6,7 +6,7 @@
 # to the eMMC or SD card, then reads it back and performs a comparison.
 
 import pytest
-import u_boot_utils
+import utils
 
 """
 This test relies on boardenv_* to containing configuration values to define
@@ -38,11 +38,11 @@ env__mmc_wr_configs = (
 @pytest.mark.buildconfigspec('cmd_mmc')
 @pytest.mark.buildconfigspec('cmd_memory')
 @pytest.mark.buildconfigspec('cmd_random')
-def test_mmc_wr(u_boot_console, env__mmc_wr_config):
+def test_mmc_wr(ubman, env__mmc_wr_config):
     """Test the "mmc write" command.
 
     Args:
-        u_boot_console: A U-Boot console connection.
+        ubman: A U-Boot console connection.
         env__mmc_wr_config: The single MMC configuration on which
             to run the test. See the file-level comment above for details
             of the format.
@@ -60,8 +60,8 @@ def test_mmc_wr(u_boot_console, env__mmc_wr_config):
 
 
     count_bytes = count_sectors * 512
-    bcfg = u_boot_console.config.buildconfig
-    ram_base = u_boot_utils.find_ram_base(u_boot_console)
+    bcfg = ubman.config.buildconfig
+    ram_base = utils.find_ram_base(ubman)
     src_addr = '0x%08x' % ram_base
     dst_addr = '0x%08x' % (ram_base + count_bytes)
 
@@ -69,7 +69,7 @@ def test_mmc_wr(u_boot_console, env__mmc_wr_config):
     for i in range(test_iterations):
         # Generate random data
         cmd = 'random %s %x' % (src_addr, count_bytes)
-        response = u_boot_console.run_command(cmd)
+        response = ubman.run_command(cmd)
         good_response = '%d bytes filled with random data' % (count_bytes)
         assert good_response in response
 
@@ -77,7 +77,7 @@ def test_mmc_wr(u_boot_console, env__mmc_wr_config):
         cmd = 'mmc dev %d' % devid
         if is_emmc:
             cmd += ' %d' % partid
-        response = u_boot_console.run_command(cmd)
+        response = ubman.run_command(cmd)
         assert 'no card present' not in response
         if is_emmc:
             partid_response = "(part %d)" % partid
@@ -88,18 +88,18 @@ def test_mmc_wr(u_boot_console, env__mmc_wr_config):
 
         # Write data
         cmd = 'mmc write %s %x %x' % (src_addr, sector, count_sectors)
-        response = u_boot_console.run_command(cmd)
+        response = ubman.run_command(cmd)
         good_response = 'MMC write: dev # %d, block # %d, count %d ... %d blocks written: OK' % (devid, sector, count_sectors, count_sectors)
         assert good_response in response
 
         # Read data
         cmd = 'mmc read %s %x %x' % (dst_addr, sector, count_sectors)
-        response = u_boot_console.run_command(cmd)
+        response = ubman.run_command(cmd)
         good_response = 'MMC read: dev # %d, block # %d, count %d ... %d blocks read: OK' % (devid, sector, count_sectors, count_sectors)
         assert good_response in response
 
         # Compare src and dst data
         cmd = 'cmp.b %s %s %x' % (src_addr, dst_addr, count_bytes)
-        response = u_boot_console.run_command(cmd)
+        response = ubman.run_command(cmd)
         good_response = 'Total of %d byte(s) were the same' % (count_bytes)
         assert good_response in response
diff --git a/test/py/tests/test_net.py b/test/py/tests/test_net.py
index ad143c19b0d..4732e4b57f8 100644
--- a/test/py/tests/test_net.py
+++ b/test/py/tests/test_net.py
@@ -5,7 +5,7 @@
 # tftpboot commands.
 
 import pytest
-import u_boot_utils
+import utils
 import uuid
 import datetime
 import re
@@ -91,37 +91,39 @@ env__router_on_net = True
 net_set_up = False
 net6_set_up = False
 
-def test_net_pre_commands(u_boot_console):
+
+@pytest.mark.buildconfigspec('cmd_net')
+def test_net_pre_commands(ubman):
     """Execute any commands required to enable network hardware.
 
     These commands are provided by the boardenv_* file; see the comment at the
     beginning of this file.
     """
 
-    init_usb = u_boot_console.config.env.get('env__net_uses_usb', False)
+    init_usb = ubman.config.env.get('env__net_uses_usb', False)
     if init_usb:
-        u_boot_console.run_command('usb start')
+        ubman.run_command('usb start')
 
-    init_pci = u_boot_console.config.env.get('env__net_uses_pci', False)
+    init_pci = ubman.config.env.get('env__net_uses_pci', False)
     if init_pci:
-        u_boot_console.run_command('pci enum')
+        ubman.run_command('pci enum')
 
-    u_boot_console.run_command('net list')
+    ubman.run_command('net list')
 
 @pytest.mark.buildconfigspec('cmd_dhcp')
-def test_net_dhcp(u_boot_console):
+def test_net_dhcp(ubman):
     """Test the dhcp command.
 
     The boardenv_* file may be used to enable/disable this test; see the
     comment at the beginning of this file.
     """
 
-    test_dhcp = u_boot_console.config.env.get('env__net_dhcp_server', False)
+    test_dhcp = ubman.config.env.get('env__net_dhcp_server', False)
     if not test_dhcp:
         pytest.skip('No DHCP server available')
 
-    u_boot_console.run_command('setenv autoload no')
-    output = u_boot_console.run_command('dhcp')
+    ubman.run_command('setenv autoload no')
+    output = ubman.run_command('dhcp')
     assert 'DHCP client bound to address ' in output
 
     global net_set_up
@@ -129,43 +131,43 @@ def test_net_dhcp(u_boot_console):
 
 @pytest.mark.buildconfigspec('cmd_dhcp')
 @pytest.mark.buildconfigspec('cmd_mii')
-def test_net_dhcp_abort(u_boot_console):
+def test_net_dhcp_abort(ubman):
     """Test the dhcp command by pressing ctrl+c in the middle of dhcp request
 
     The boardenv_* file may be used to enable/disable this test; see the
     comment at the beginning of this file.
     """
 
-    test_dhcp = u_boot_console.config.env.get('env__net_dhcp_server', False)
+    test_dhcp = ubman.config.env.get('env__net_dhcp_server', False)
     if not test_dhcp:
         pytest.skip('No DHCP server available')
 
-    if u_boot_console.config.env.get('env__dhcp_abort_test_skip', True):
+    if ubman.config.env.get('env__dhcp_abort_test_skip', True):
         pytest.skip('DHCP abort test is not enabled!')
 
-    u_boot_console.run_command('setenv autoload no')
+    ubman.run_command('setenv autoload no')
 
     # Phy reset before running dhcp command
-    output = u_boot_console.run_command('mii device')
+    output = ubman.run_command('mii device')
     if not re.search(r"Current device: '(.+?)'", output):
         pytest.skip('PHY device does not exist!')
     eth_num = re.search(r"Current device: '(.+?)'", output).groups()[0]
-    u_boot_console.run_command(f'mii device {eth_num}')
-    output = u_boot_console.run_command('mii info')
+    ubman.run_command(f'mii device {eth_num}')
+    output = ubman.run_command('mii info')
     eth_addr = hex(int(re.search(r'PHY (.+?):', output).groups()[0], 16))
-    u_boot_console.run_command(f'mii modify {eth_addr} 0 0x8000 0x8000')
+    ubman.run_command(f'mii modify {eth_addr} 0 0x8000 0x8000')
 
-    u_boot_console.run_command('dhcp', wait_for_prompt=False)
+    ubman.run_command('dhcp', wait_for_prompt=False)
     try:
-        u_boot_console.wait_for('Waiting for PHY auto negotiation to complete')
+        ubman.wait_for('Waiting for PHY auto negotiation to complete')
     except:
         pytest.skip('Timeout waiting for PHY auto negotiation to complete')
 
-    u_boot_console.wait_for('done')
+    ubman.wait_for('done')
 
     try:
         # Sending Ctrl-C
-        output = u_boot_console.run_command(
+        output = ubman.run_command(
             chr(3), wait_for_echo=False, send_nl=False
         )
         assert 'TIMEOUT' not in output
@@ -174,49 +176,49 @@ def test_net_dhcp_abort(u_boot_console):
     finally:
         # Provide a time to recover from Abort - if it is not performed
         # There is message like: ethernet@ff0e0000: No link.
-        u_boot_console.run_command('sleep 1')
+        ubman.run_command('sleep 1')
         # Run the dhcp test to setup the network configuration
-        test_net_dhcp(u_boot_console)
+        test_net_dhcp(ubman)
 
 @pytest.mark.buildconfigspec('cmd_dhcp6')
-def test_net_dhcp6(u_boot_console):
+def test_net_dhcp6(ubman):
     """Test the dhcp6 command.
 
     The boardenv_* file may be used to enable/disable this test; see the
     comment at the beginning of this file.
     """
 
-    test_dhcp6 = u_boot_console.config.env.get('env__net_dhcp6_server', False)
+    test_dhcp6 = ubman.config.env.get('env__net_dhcp6_server', False)
     if not test_dhcp6:
         pytest.skip('No DHCP6 server available')
 
-    u_boot_console.run_command('setenv autoload no')
-    output = u_boot_console.run_command('dhcp6')
+    ubman.run_command('setenv autoload no')
+    output = ubman.run_command('dhcp6')
     assert 'DHCP6 client bound to ' in output
 
     global net6_set_up
     net6_set_up = True
 
 @pytest.mark.buildconfigspec('net')
-def test_net_setup_static(u_boot_console):
+def test_net_setup_static(ubman):
     """Set up a static IP configuration.
 
     The configuration is provided by the boardenv_* file; see the comment at
     the beginning of this file.
     """
 
-    env_vars = u_boot_console.config.env.get('env__net_static_env_vars', None)
+    env_vars = ubman.config.env.get('env__net_static_env_vars', None)
     if not env_vars:
         pytest.skip('No static network configuration is defined')
 
     for (var, val) in env_vars:
-        u_boot_console.run_command('setenv %s %s' % (var, val))
+        ubman.run_command('setenv %s %s' % (var, val))
 
     global net_set_up
     net_set_up = True
 
 @pytest.mark.buildconfigspec('cmd_ping')
-def test_net_ping(u_boot_console):
+def test_net_ping(ubman):
     """Test the ping command.
 
     The $serverip (as set up by either test_net_dhcp or test_net_setup_static)
@@ -227,11 +229,11 @@ def test_net_ping(u_boot_console):
     if not net_set_up:
         pytest.skip('Network not initialized')
 
-    output = u_boot_console.run_command('ping $serverip')
+    output = ubman.run_command('ping $serverip')
     assert 'is alive' in output
 
 @pytest.mark.buildconfigspec('IPV6_ROUTER_DISCOVERY')
-def test_net_network_discovery(u_boot_console):
+def test_net_network_discovery(ubman):
     """Test the network discovery feature of IPv6.
 
     An IPv6 network command (ping6 in this case) is run to make U-Boot send a
@@ -244,18 +246,18 @@ def test_net_network_discovery(u_boot_console):
     the beginning of this file.
     """
 
-    router_on_net = u_boot_console.config.env.get('env__router_on_net', False)
+    router_on_net = ubman.config.env.get('env__router_on_net', False)
     if not router_on_net:
         pytest.skip('No router on network')
 
     fake_host_ip = 'fe80::215:5dff:fef6:2ec6'
-    output = u_boot_console.run_command('ping6 ' + fake_host_ip)
+    output = ubman.run_command('ping6 ' + fake_host_ip)
     assert 'ROUTER SOLICITATION 1' in output
     assert 'Set gatewayip6:' in output
     assert '0000:0000:0000:0000:0000:0000:0000:0000' not in output
 
 @pytest.mark.buildconfigspec('cmd_tftpboot')
-def test_net_tftpboot(u_boot_console):
+def test_net_tftpboot(ubman):
     """Test the tftpboot command.
 
     A file is downloaded from the TFTP server, its size and optionally its
@@ -268,7 +270,7 @@ def test_net_tftpboot(u_boot_console):
     if not net_set_up:
         pytest.skip('Network not initialized')
 
-    f = u_boot_console.config.env.get('env__net_tftp_readable_file', None)
+    f = ubman.config.env.get('env__net_tftp_readable_file', None)
     if not f:
         pytest.skip('No TFTP readable file to read')
 
@@ -276,9 +278,9 @@ def test_net_tftpboot(u_boot_console):
 
     fn = f['fn']
     if not addr:
-        output = u_boot_console.run_command('tftpboot %s' % (fn))
+        output = ubman.run_command('tftpboot %s' % (fn))
     else:
-        output = u_boot_console.run_command('tftpboot %x %s' % (addr, fn))
+        output = ubman.run_command('tftpboot %x %s' % (addr, fn))
     expected_text = 'Bytes transferred = '
     sz = f.get('size', None)
     if sz:
@@ -289,14 +291,14 @@ def test_net_tftpboot(u_boot_console):
     if not expected_crc:
         return
 
-    if u_boot_console.config.buildconfig.get('config_cmd_crc32', 'n') != 'y':
+    if ubman.config.buildconfig.get('config_cmd_crc32', 'n') != 'y':
         return
 
-    output = u_boot_console.run_command('crc32 $fileaddr $filesize')
+    output = ubman.run_command('crc32 $fileaddr $filesize')
     assert expected_crc in output
 
 @pytest.mark.buildconfigspec('cmd_nfs')
-def test_net_nfs(u_boot_console):
+def test_net_nfs(ubman):
     """Test the nfs command.
 
     A file is downloaded from the NFS server, its size and optionally its
@@ -309,16 +311,16 @@ def test_net_nfs(u_boot_console):
     if not net_set_up:
         pytest.skip('Network not initialized')
 
-    f = u_boot_console.config.env.get('env__net_nfs_readable_file', None)
+    f = ubman.config.env.get('env__net_nfs_readable_file', None)
     if not f:
         pytest.skip('No NFS readable file to read')
 
     addr = f.get('addr', None)
     if not addr:
-        addr = u_boot_utils.find_ram_base(u_boot_console)
+        addr = utils.find_ram_base(ubman)
 
     fn = f['fn']
-    output = u_boot_console.run_command('nfs %x %s' % (addr, fn))
+    output = ubman.run_command('nfs %x %s' % (addr, fn))
     expected_text = 'Bytes transferred = '
     sz = f.get('size', None)
     if sz:
@@ -329,14 +331,14 @@ def test_net_nfs(u_boot_console):
     if not expected_crc:
         return
 
-    if u_boot_console.config.buildconfig.get('config_cmd_crc32', 'n') != 'y':
+    if ubman.config.buildconfig.get('config_cmd_crc32', 'n') != 'y':
         return
 
-    output = u_boot_console.run_command('crc32 %x $filesize' % addr)
+    output = ubman.run_command('crc32 %x $filesize' % addr)
     assert expected_crc in output
 
 @pytest.mark.buildconfigspec("cmd_pxe")
-def test_net_pxe_get(u_boot_console):
+def test_net_pxe_get(ubman):
     """Test the pxe get command.
 
     A pxe configuration file is downloaded from the TFTP server and interpreted
@@ -349,31 +351,31 @@ def test_net_pxe_get(u_boot_console):
     if not net_set_up:
         pytest.skip("Network not initialized")
 
-    test_net_setup_static(u_boot_console)
+    test_net_setup_static(ubman)
 
-    f = u_boot_console.config.env.get("env__net_pxe_readable_file", None)
+    f = ubman.config.env.get("env__net_pxe_readable_file", None)
     if not f:
         pytest.skip("No PXE readable file to read")
 
     addr = f.get("addr", None)
-    timeout = f.get("timeout", u_boot_console.p.timeout)
+    timeout = f.get("timeout", ubman.p.timeout)
 
     pxeuuid = uuid.uuid1()
-    u_boot_console.run_command(f"setenv pxeuuid {pxeuuid}")
+    ubman.run_command(f"setenv pxeuuid {pxeuuid}")
     expected_text_uuid = f"Retrieving file: pxelinux.cfg/{pxeuuid}"
 
-    ethaddr = u_boot_console.run_command("echo $ethaddr")
+    ethaddr = ubman.run_command("echo $ethaddr")
     ethaddr = ethaddr.replace(':', '-')
     expected_text_ethaddr = f"Retrieving file: pxelinux.cfg/01-{ethaddr}"
 
-    ip = u_boot_console.run_command("echo $ipaddr")
+    ip = ubman.run_command("echo $ipaddr")
     ip = ip.split('.')
     ipaddr_file = "".join(['%02x' % int(x) for x in ip]).upper()
     expected_text_ipaddr = f"Retrieving file: pxelinux.cfg/{ipaddr_file}"
     expected_text_default = f"Retrieving file: pxelinux.cfg/default"
 
-    with u_boot_console.temporary_timeout(timeout):
-        output = u_boot_console.run_command("pxe get")
+    with ubman.temporary_timeout(timeout):
+        output = ubman.run_command("pxe get")
 
     assert "TIMEOUT" not in output
     assert expected_text_uuid in output
@@ -392,7 +394,7 @@ def test_net_pxe_get(u_boot_console):
 @pytest.mark.buildconfigspec("cmd_crc32")
 @pytest.mark.buildconfigspec("cmd_tftpboot")
 @pytest.mark.buildconfigspec("cmd_tftpput")
-def test_net_tftpput(u_boot_console):
+def test_net_tftpput(ubman):
     """Test the tftpput command.
 
     A file is downloaded from the TFTP server and then uploaded to the TFTP
@@ -405,35 +407,35 @@ def test_net_tftpput(u_boot_console):
     if not net_set_up:
         pytest.skip("Network not initialized")
 
-    f = u_boot_console.config.env.get("env__net_tftp_readable_file", None)
+    f = ubman.config.env.get("env__net_tftp_readable_file", None)
     if not f:
         pytest.skip("No TFTP readable file to read")
 
     addr = f.get("addr", None)
     if not addr:
-        addr = u_boot_utils.find_ram_base(u_boot_console)
+        addr = utils.find_ram_base(ubman)
 
     sz = f.get("size", None)
-    timeout = f.get("timeout", u_boot_console.p.timeout)
+    timeout = f.get("timeout", ubman.p.timeout)
     fn = f["fn"]
     fnu = f.get("fnu", "_".join([datetime.datetime.now().strftime("%y%m%d%H%M%S"), fn]))
     expected_text = "Bytes transferred = "
     if sz:
         expected_text += "%d" % sz
 
-    with u_boot_console.temporary_timeout(timeout):
-        output = u_boot_console.run_command("tftpboot %x %s" % (addr, fn))
+    with ubman.temporary_timeout(timeout):
+        output = ubman.run_command("tftpboot %x %s" % (addr, fn))
 
     assert "TIMEOUT" not in output
     assert expected_text in output
 
     expected_tftpb_crc = f.get("crc32", None)
 
-    output = u_boot_console.run_command("crc32 $fileaddr $filesize")
+    output = ubman.run_command("crc32 $fileaddr $filesize")
     assert expected_tftpb_crc in output
 
-    with u_boot_console.temporary_timeout(timeout):
-        output = u_boot_console.run_command(
+    with ubman.temporary_timeout(timeout):
+        output = ubman.run_command(
             "tftpput $fileaddr $filesize $serverip:%s" % (fnu)
         )
 
@@ -445,8 +447,8 @@ def test_net_tftpput(u_boot_console):
     assert "Access violation" not in output
     assert expected_text in output
 
-    with u_boot_console.temporary_timeout(timeout):
-        output = u_boot_console.run_command("tftpboot %x %s" % (addr, fnu))
+    with ubman.temporary_timeout(timeout):
+        output = ubman.run_command("tftpboot %x %s" % (addr, fnu))
 
     expected_text = "Bytes transferred = "
     if sz:
@@ -454,5 +456,5 @@ def test_net_tftpput(u_boot_console):
     assert "TIMEOUT" not in output
     assert expected_text in output
 
-    output = u_boot_console.run_command("crc32 $fileaddr $filesize")
+    output = ubman.run_command("crc32 $fileaddr $filesize")
     assert expected_tftpb_crc in output
diff --git a/test/py/tests/test_net_boot.py b/test/py/tests/test_net_boot.py
index d7d74356928..abf6dfbaf5e 100644
--- a/test/py/tests/test_net_boot.py
+++ b/test/py/tests/test_net_boot.py
@@ -2,7 +2,7 @@
 # (C) Copyright 2023, Advanced Micro Devices, Inc.
 
 import pytest
-import u_boot_utils
+import utils
 import test_net
 import re
 
@@ -117,26 +117,26 @@ env__pxe_boot_test_skip = False
         initrd rootfs.cpio.gz.u-boot
 """
 
-def setup_networking(u_boot_console):
-    test_net.test_net_dhcp(u_boot_console)
+def setup_networking(ubman):
+    test_net.test_net_dhcp(ubman)
     if not test_net.net_set_up:
-        test_net.test_net_setup_static(u_boot_console)
+        test_net.test_net_setup_static(ubman)
 
-def setup_tftpboot_boot(u_boot_console):
-    f = u_boot_console.config.env.get('env__net_tftp_bootable_file', None)
+def setup_tftpboot_boot(ubman):
+    f = ubman.config.env.get('env__net_tftp_bootable_file', None)
     if not f:
         pytest.skip('No TFTP bootable file to read')
 
-    setup_networking(u_boot_console)
+    setup_networking(ubman)
     addr = f.get('addr', None)
     if not addr:
-        addr = u_boot_utils.find_ram_base(u_boot_console)
+        addr = utils.find_ram_base(ubman)
 
     fn = f['fn']
     timeout = f.get('timeout', 50000)
 
-    with u_boot_console.temporary_timeout(timeout):
-        output = u_boot_console.run_command('tftpboot %x %s' % (addr, fn))
+    with ubman.temporary_timeout(timeout):
+        output = ubman.run_command('tftpboot %x %s' % (addr, fn))
 
     expected_text = 'Bytes transferred = '
     sz = f.get('size', None)
@@ -145,7 +145,7 @@ def setup_tftpboot_boot(u_boot_console):
     assert expected_text in output
 
     expected_crc = f.get('crc32', None)
-    output = u_boot_console.run_command('crc32 %x $filesize' % addr)
+    output = ubman.run_command('crc32 %x $filesize' % addr)
     if expected_crc:
         assert expected_crc in output
 
@@ -157,7 +157,7 @@ def setup_tftpboot_boot(u_boot_console):
     return addr, timeout, pattern, chk_type, chk_pattern, config
 
 @pytest.mark.buildconfigspec('cmd_tftpboot')
-def test_net_tftpboot_boot(u_boot_console):
+def test_net_tftpboot_boot(ubman):
     """Boot the loaded image
 
     A boot file (fit image) is downloaded from the TFTP server and booted using
@@ -167,11 +167,11 @@ def test_net_tftpboot_boot(u_boot_console):
     The details of the file to download are provided by the boardenv_* file;
     see the comment at the beginning of this file.
     """
-    if u_boot_console.config.env.get('env__tftp_boot_test_skip', True):
+    if ubman.config.env.get('env__tftp_boot_test_skip', True):
         pytest.skip('TFTP boot test is not enabled!')
 
     addr, timeout, pattern, chk_type, chk_pattern, imcfg = setup_tftpboot_boot(
-        u_boot_console
+        ubman
     )
 
     if imcfg:
@@ -179,38 +179,38 @@ def test_net_tftpboot_boot(u_boot_console):
     else:
         bootcmd = 'bootm %x' % addr
 
-    with u_boot_console.enable_check(
+    with ubman.enable_check(
         chk_type, chk_pattern
-    ), u_boot_console.temporary_timeout(timeout):
+    ), ubman.temporary_timeout(timeout):
         try:
             # wait_for_prompt=False makes the core code not wait for the U-Boot
             # prompt code to be seen, since it won't be on a successful kernel
             # boot
-            u_boot_console.run_command(bootcmd, wait_for_prompt=False)
+            ubman.run_command(bootcmd, wait_for_prompt=False)
 
             # Wait for boot log pattern
-            u_boot_console.wait_for(pattern)
+            ubman.wait_for(pattern)
         finally:
             # This forces the console object to be shutdown, so any subsequent
             # test will reset the board back into U-Boot. We want to force this
             # no matter whether the kernel boot passed or failed.
-            u_boot_console.drain_console()
-            u_boot_console.cleanup_spawn()
+            ubman.drain_console()
+            ubman.cleanup_spawn()
 
-def setup_pxe_boot(u_boot_console):
-    f = u_boot_console.config.env.get('env__net_pxe_bootable_file', None)
+def setup_pxe_boot(ubman):
+    f = ubman.config.env.get('env__net_pxe_bootable_file', None)
     if not f:
         pytest.skip('No PXE bootable file to read')
 
-    setup_networking(u_boot_console)
-    bootfile = u_boot_console.run_command('echo $bootfile')
+    setup_networking(ubman)
+    bootfile = ubman.run_command('echo $bootfile')
     if not bootfile:
         bootfile = '<NULL>'
 
     return f, bootfile
 
 @pytest.mark.buildconfigspec('cmd_pxe')
-def test_net_pxe_boot(u_boot_console):
+def test_net_pxe_boot(ubman):
     """Test the pxe boot command.
 
     A pxe configuration file is downloaded from the TFTP server and interpreted
@@ -219,19 +219,19 @@ def test_net_pxe_boot(u_boot_console):
     The details of the file to download are provided by the boardenv_* file;
     see the comment at the beginning of this file.
     """
-    if u_boot_console.config.env.get('env__pxe_boot_test_skip', True):
+    if ubman.config.env.get('env__pxe_boot_test_skip', True):
         pytest.skip('PXE boot test is not enabled!')
 
-    f, bootfile = setup_pxe_boot(u_boot_console)
+    f, bootfile = setup_pxe_boot(ubman)
     addr = f.get('addr', None)
-    timeout = f.get('timeout', u_boot_console.p.timeout)
+    timeout = f.get('timeout', ubman.p.timeout)
     fn = f['fn']
 
     if addr:
-        u_boot_console.run_command('setenv pxefile_addr_r %x' % addr)
+        ubman.run_command('setenv pxefile_addr_r %x' % addr)
 
-    with u_boot_console.temporary_timeout(timeout):
-        output = u_boot_console.run_command('pxe get')
+    with ubman.temporary_timeout(timeout):
+        output = ubman.run_command('pxe get')
 
     expected_text = 'Bytes transferred = '
     sz = f.get('size', None)
@@ -250,18 +250,18 @@ def test_net_pxe_boot(u_boot_console):
     else:
         pxe_boot_cmd = 'pxe boot %x' % addr
 
-    with u_boot_console.enable_check(
+    with ubman.enable_check(
         chk_type, chk_pattern
-    ), u_boot_console.temporary_timeout(timeout):
+    ), ubman.temporary_timeout(timeout):
         try:
-            u_boot_console.run_command(pxe_boot_cmd, wait_for_prompt=False)
-            u_boot_console.wait_for(pattern)
+            ubman.run_command(pxe_boot_cmd, wait_for_prompt=False)
+            ubman.wait_for(pattern)
         finally:
-            u_boot_console.drain_console()
-            u_boot_console.cleanup_spawn()
+            ubman.drain_console()
+            ubman.cleanup_spawn()
 
 @pytest.mark.buildconfigspec('cmd_pxe')
-def test_net_pxe_boot_config(u_boot_console):
+def test_net_pxe_boot_config(ubman):
     """Test the pxe boot command by selecting different combination of labels
 
     A pxe configuration file is downloaded from the TFTP server and interpreted
@@ -270,12 +270,12 @@ def test_net_pxe_boot_config(u_boot_console):
     The details of the file to download are provided by the boardenv_* file;
     see the comment at the beginning of this file.
     """
-    if u_boot_console.config.env.get('env__pxe_boot_test_skip', True):
+    if ubman.config.env.get('env__pxe_boot_test_skip', True):
         pytest.skip('PXE boot test is not enabled!')
 
-    f, bootfile = setup_pxe_boot(u_boot_console)
+    f, bootfile = setup_pxe_boot(ubman)
     addr = f.get('addr', None)
-    timeout = f.get('timeout', u_boot_console.p.timeout)
+    timeout = f.get('timeout', ubman.p.timeout)
     fn = f['fn']
     local_label = f['local_label']
     empty_label = f['empty_label']
@@ -283,10 +283,10 @@ def test_net_pxe_boot_config(u_boot_console):
     exp_str_empty = f['exp_str_empty']
 
     if addr:
-        u_boot_console.run_command('setenv pxefile_addr_r %x' % addr)
+        ubman.run_command('setenv pxefile_addr_r %x' % addr)
 
-    with u_boot_console.temporary_timeout(timeout):
-        output = u_boot_console.run_command('pxe get')
+    with ubman.temporary_timeout(timeout):
+        output = ubman.run_command('pxe get')
 
     expected_text = 'Bytes transferred = '
     sz = f.get('size', None)
@@ -305,20 +305,20 @@ def test_net_pxe_boot_config(u_boot_console):
     else:
         pxe_boot_cmd = 'pxe boot %x' % addr
 
-    with u_boot_console.enable_check(
+    with ubman.enable_check(
         chk_type, chk_pattern
-    ), u_boot_console.temporary_timeout(timeout):
+    ), ubman.temporary_timeout(timeout):
         try:
-            u_boot_console.run_command(pxe_boot_cmd, wait_for_prompt=False)
+            ubman.run_command(pxe_boot_cmd, wait_for_prompt=False)
 
             # pxe config is loaded where multiple labels are there and need to
             # select particular label to boot and check for expected string
             # In this case, local label is selected and it should look for
             # localcmd env variable and if that variable is not defined it
             # should not boot it and come out to u-boot prompt
-            u_boot_console.wait_for('Enter choice:')
-            u_boot_console.run_command(local_label, wait_for_prompt=False)
-            expected_str = u_boot_console.p.expect([exp_str_local])
+            ubman.wait_for('Enter choice:')
+            ubman.run_command(local_label, wait_for_prompt=False)
+            expected_str = ubman.p.expect([exp_str_local])
             assert (
                 expected_str == 0
             ), f'Expected string: {exp_str_local} did not match!'
@@ -326,21 +326,21 @@ def test_net_pxe_boot_config(u_boot_console):
             # In this case, empty label is selected and it should look for
             # kernel image path and if it is not set it should fail it and load
             # default label to boot
-            u_boot_console.run_command(pxe_boot_cmd, wait_for_prompt=False)
-            u_boot_console.wait_for('Enter choice:')
-            u_boot_console.run_command(empty_label, wait_for_prompt=False)
-            expected_str = u_boot_console.p.expect([exp_str_empty])
+            ubman.run_command(pxe_boot_cmd, wait_for_prompt=False)
+            ubman.wait_for('Enter choice:')
+            ubman.run_command(empty_label, wait_for_prompt=False)
+            expected_str = ubman.p.expect([exp_str_empty])
             assert (
                 expected_str == 0
             ), f'Expected string: {exp_str_empty} did not match!'
 
-            u_boot_console.wait_for(pattern)
+            ubman.wait_for(pattern)
         finally:
-            u_boot_console.drain_console()
-            u_boot_console.cleanup_spawn()
+            ubman.drain_console()
+            ubman.cleanup_spawn()
 
 @pytest.mark.buildconfigspec('cmd_pxe')
-def test_net_pxe_boot_config_invalid(u_boot_console):
+def test_net_pxe_boot_config_invalid(ubman):
     """Test the pxe boot command by selecting invalid label
 
     A pxe configuration file is downloaded from the TFTP server and interpreted
@@ -349,21 +349,21 @@ def test_net_pxe_boot_config_invalid(u_boot_console):
     The details of the file to download are provided by the boardenv_* file;
     see the comment at the beginning of this file.
     """
-    if u_boot_console.config.env.get('env__pxe_boot_test_skip', True):
+    if ubman.config.env.get('env__pxe_boot_test_skip', True):
         pytest.skip('PXE boot test is not enabled!')
 
-    f, bootfile = setup_pxe_boot(u_boot_console)
+    f, bootfile = setup_pxe_boot(ubman)
     addr = f.get('addr', None)
-    timeout = f.get('timeout', u_boot_console.p.timeout)
+    timeout = f.get('timeout', ubman.p.timeout)
     fn = f['fn']
     invalid_label = f['invalid_label']
     exp_str_invalid = f['exp_str_invalid']
 
     if addr:
-        u_boot_console.run_command('setenv pxefile_addr_r %x' % addr)
+        ubman.run_command('setenv pxefile_addr_r %x' % addr)
 
-    with u_boot_console.temporary_timeout(timeout):
-        output = u_boot_console.run_command('pxe get')
+    with ubman.temporary_timeout(timeout):
+        output = ubman.run_command('pxe get')
 
     expected_text = 'Bytes transferred = '
     sz = f.get('size', None)
@@ -379,22 +379,22 @@ def test_net_pxe_boot_config_invalid(u_boot_console):
     else:
         pxe_boot_cmd = 'pxe boot %x' % addr
 
-    with u_boot_console.temporary_timeout(timeout):
+    with ubman.temporary_timeout(timeout):
         try:
-            u_boot_console.run_command(pxe_boot_cmd, wait_for_prompt=False)
+            ubman.run_command(pxe_boot_cmd, wait_for_prompt=False)
 
             # pxe config is loaded where multiple labels are there and need to
             # select particular label to boot and check for expected string
             # In this case invalid label is selected, it should load invalid
             # label and if it fails it should load the default label to boot
-            u_boot_console.wait_for('Enter choice:')
-            u_boot_console.run_command(invalid_label, wait_for_prompt=False)
-            expected_str = u_boot_console.p.expect([exp_str_invalid])
+            ubman.wait_for('Enter choice:')
+            ubman.run_command(invalid_label, wait_for_prompt=False)
+            expected_str = ubman.p.expect([exp_str_invalid])
             assert (
                 expected_str == 0
             ), f'Expected string: {exp_str_invalid} did not match!'
 
-            u_boot_console.wait_for(pattern)
+            ubman.wait_for(pattern)
         finally:
-            u_boot_console.drain_console()
-            u_boot_console.cleanup_spawn()
+            ubman.drain_console()
+            ubman.cleanup_spawn()
diff --git a/test/py/tests/test_of_migrate.py b/test/py/tests/test_of_migrate.py
index 910f7c05510..ab89332331e 100644
--- a/test/py/tests/test_of_migrate.py
+++ b/test/py/tests/test_of_migrate.py
@@ -7,18 +7,18 @@
 import os
 import pytest
 
-import u_boot_utils as util
+import utils
 
 # This is needed for Azure, since the default '..' directory is not writeable
 TMPDIR1 = '/tmp/test_no_migrate'
 TMPDIR2 = '/tmp/test_no_migrate_spl'
 TMPDIR3 = '/tmp/test_migrate'
 
-def build_for_migrate(cons, replace_pair, board, tmpdir, disable_migrate=True):
+def build_for_migrate(ubman, replace_pair, board, tmpdir, disable_migrate=True):
     """Build an updated U-Boot with a slightly modified device tree
 
     Args:
-        cons (ConsoleBase): U-Boot console
+        ubman (ConsoleBase): U-Boot console
         replace_pair (tuple):
             String to find
             String to replace it with
@@ -26,15 +26,15 @@ def build_for_migrate(cons, replace_pair, board, tmpdir, disable_migrate=True):
         tmpdir (str): Temporary directory to use
         disable_migrate (bool): True to disable CONFIG_OF_TAG_MIGRATE in build
     """
-    srcdir = cons.config.source_dir
-    build_dir = cons.config.build_dir
+    srcdir = ubman.config.source_dir
+    build_dir = ubman.config.build_dir
 
     # Get the source for the existing dts
     dt_dir = os.path.join(build_dir, 'arch', 'sandbox', 'dts')
     orig_fname = os.path.join(dt_dir, 'sandbox.dtb')
     out_dts = os.path.join(dt_dir, 'sandbox_out.dts')
-    util.run_and_log(cons, ['dtc', orig_fname, '-I', 'dtb', '-O', 'dts',
-                            '-o', out_dts])
+    utils.run_and_log(ubman, ['dtc', orig_fname, '-I', 'dtb', '-O', 'dts',
+                             '-o', out_dts])
 
     # Update it to use an old tag
     with open(out_dts) as inf:
@@ -45,7 +45,7 @@ def build_for_migrate(cons, replace_pair, board, tmpdir, disable_migrate=True):
     with open(dts_fname, 'w') as outf:
         print(data, file=outf)
     dtb_fname = os.path.join(dt_dir, 'sandbox_oldtag.dtb')
-    util.run_and_log(cons, ['dtc', dts_fname, '-o', dtb_fname])
+    utils.run_and_log(ubman, ['dtc', dts_fname, '-o', dtb_fname])
 
     migrate = ['-a', '~CONFIG_OF_TAG_MIGRATE'] if disable_migrate else []
 
@@ -54,24 +54,23 @@ def build_for_migrate(cons, replace_pair, board, tmpdir, disable_migrate=True):
     env['EXT_DTB'] = dtb_fname
     env['DEVICE_TREE'] = 'sandbox_new'
     env['NO_LTO'] = '1'  # Speed up build
-    out = util.run_and_log(
-        cons, ['./tools/buildman/buildman', '-m', '--board', board,
+    out = utils.run_and_log(
+        ubman, ['./tools/buildman/buildman', '-m', '--board', board,
                *migrate, '-w', '-o', tmpdir], ignore_errors=True, env=env)
     return out
 
 @pytest.mark.slow
 @pytest.mark.boardspec('sandbox')
-def test_of_no_migrate(u_boot_console):
+def test_of_no_migrate(ubman):
     """Test sandbox with old boot phase tags like u-boot,dm-pre-proper"""
-    cons = u_boot_console
 
-    build_for_migrate(cons, ['bootph-some-ram', 'u-boot,dm-pre-proper'],
+    build_for_migrate(ubman, ['bootph-some-ram', 'u-boot,dm-pre-proper'],
                       'sandbox', TMPDIR1)
 
     # It should fail to run, since the lcd device will not be bound before
     # relocation. so won't get its frame-buffer memory
-    out = util.run_and_log(
-        cons, [os.path.join(TMPDIR1, 'u-boot'), '-D', '-c', 'help'],
+    out = utils.run_and_log(
+        ubman, [os.path.join(TMPDIR1, 'u-boot'), '-D', '-c', 'help'],
         ignore_errors=True)
     assert "Video device 'lcd' cannot allocate frame buffer memory" in out
 
@@ -80,11 +79,10 @@ def test_of_no_migrate(u_boot_console):
 @pytest.mark.boardspec('sandbox_spl')
 @pytest.mark.boardspec('spl_of_platdata_inst')
 @pytest.mark.boardspec('!sandbox_tpl')
-def test_of_no_migrate_spl(u_boot_console):
+def test_of_no_migrate_spl(ubman):
     """Test sandbox with old boot phase tags like u-boot,dm-spl"""
-    cons = u_boot_console
 
-    out = build_for_migrate(cons, ['bootph-pre-ram', 'u-boot,dm-spl'],
+    out = build_for_migrate(ubman, ['bootph-pre-ram', 'u-boot,dm-spl'],
                             'sandbox_spl', TMPDIR2)
 
     # It should fail to build, since the SPL DT will not include 'spl-test'
@@ -94,15 +92,14 @@ def test_of_no_migrate_spl(u_boot_console):
 
 @pytest.mark.slow
 @pytest.mark.boardspec('sandbox')
-def test_of_migrate(u_boot_console):
+def test_of_migrate(ubman):
     """Test sandbox shows a message when tags were migrated"""
-    cons = u_boot_console
 
-    build_for_migrate(cons, ['bootph-some-ram', 'u-boot,dm-pre-proper'],
+    build_for_migrate(ubman, ['bootph-some-ram', 'u-boot,dm-pre-proper'],
                       'sandbox', TMPDIR3, disable_migrate=False)
 
     # It should show a migration message
-    out = util.run_and_log(
-        cons, [os.path.join(TMPDIR3, 'u-boot'), '-D', '-c', 'help'],
+    out = utils.run_and_log(
+        ubman, [os.path.join(TMPDIR3, 'u-boot'), '-D', '-c', 'help'],
         ignore_errors=True)
     assert "Warning: Device tree includes old 'u-boot,dm-' tags" in out
diff --git a/test/py/tests/test_ofplatdata.py b/test/py/tests/test_ofplatdata.py
index 51a188454f3..d31fa55f7c7 100644
--- a/test/py/tests/test_ofplatdata.py
+++ b/test/py/tests/test_ofplatdata.py
@@ -2,16 +2,15 @@
 # Copyright (c) 2016 Google, Inc
 
 import pytest
-import u_boot_utils as util
+import utils
 
 @pytest.mark.boardspec('sandbox_spl')
 @pytest.mark.buildconfigspec('spl_of_platdata')
-def test_spl_devicetree(u_boot_console):
+def test_spl_devicetree(ubman):
     """Test content of spl device-tree"""
-    cons = u_boot_console
-    dtb = cons.config.build_dir + '/spl/u-boot-spl.dtb'
-    fdtgrep = cons.config.build_dir + '/tools/fdtgrep'
-    output = util.run_and_log(cons, [fdtgrep, '-l', dtb])
+    dtb = ubman.config.build_dir + '/spl/u-boot-spl.dtb'
+    fdtgrep = ubman.config.build_dir + '/tools/fdtgrep'
+    output = utils.run_and_log(ubman, [fdtgrep, '-l', dtb])
 
     assert "bootph-all" not in output
     assert "bootph-some-ram" not in output
diff --git a/test/py/tests/test_optee_rpmb.py b/test/py/tests/test_optee_rpmb.py
index 8a081b5c494..04b3b5e41ef 100644
--- a/test/py/tests/test_optee_rpmb.py
+++ b/test/py/tests/test_optee_rpmb.py
@@ -7,14 +7,14 @@ This tests optee_rpmb cmd in U-Boot
 """
 
 import pytest
-import u_boot_utils as util
+import utils
 
 @pytest.mark.buildconfigspec('cmd_optee_rpmb')
-def test_optee_rpmb_read_write(u_boot_console):
+def test_optee_rpmb_read_write(ubman):
     """Test OP-TEE RPMB cmd read/write
     """
-    response = u_boot_console.run_command('optee_rpmb write_pvalue test_variable test_value')
+    response = ubman.run_command('optee_rpmb write_pvalue test_variable test_value')
     assert response == 'Wrote 11 bytes'
 
-    response = u_boot_console.run_command('optee_rpmb read_pvalue test_variable 11')
-    assert response == 'Read 11 bytes, value = test_value'
\ No newline at end of file
+    response = ubman.run_command('optee_rpmb read_pvalue test_variable 11')
+    assert response == 'Read 11 bytes, value = test_value'
diff --git a/test/py/tests/test_part.py b/test/py/tests/test_part.py
index 2b5184654db..04c95a6d3cc 100644
--- a/test/py/tests/test_part.py
+++ b/test/py/tests/test_part.py
@@ -7,8 +7,8 @@ import pytest
 @pytest.mark.buildconfigspec('cmd_part')
 @pytest.mark.buildconfigspec('partitions')
 @pytest.mark.buildconfigspec('efi_partition')
-def test_part_types(u_boot_console):
+def test_part_types(ubman):
     """Test that `part types` prints a result which includes `EFI`."""
-    output = u_boot_console.run_command('part types')
+    output = ubman.run_command('part types')
     assert "Supported partition tables:" in output
     assert "EFI" in output
diff --git a/test/py/tests/test_pinmux.py b/test/py/tests/test_pinmux.py
index 794994e12d1..ee79e843341 100644
--- a/test/py/tests/test_pinmux.py
+++ b/test/py/tests/test_pinmux.py
@@ -1,27 +1,27 @@
 # SPDX-License-Identifier: GPL-2.0
 
 import pytest
-import u_boot_utils
+import utils
 
 @pytest.mark.buildconfigspec('cmd_pinmux')
-def test_pinmux_usage_1(u_boot_console):
+def test_pinmux_usage_1(ubman):
     """Test that 'pinmux' command without parameters displays
     pinmux usage."""
-    output = u_boot_console.run_command('pinmux')
+    output = ubman.run_command('pinmux')
     assert 'Usage:' in output
 
 @pytest.mark.buildconfigspec('cmd_pinmux')
-def test_pinmux_usage_2(u_boot_console):
+def test_pinmux_usage_2(ubman):
     """Test that 'pinmux status' executed without previous "pinmux dev"
     command displays error message."""
-    output = u_boot_console.run_command('pinmux status')
+    output = ubman.run_command('pinmux status')
     assert 'pin-controller device not selected' in output
 
 @pytest.mark.buildconfigspec('cmd_pinmux')
 @pytest.mark.boardspec('sandbox')
-def test_pinmux_status_all(u_boot_console):
+def test_pinmux_status_all(ubman):
     """Test that 'pinmux status -a' displays pin's muxing."""
-    output = u_boot_console.run_command('pinmux status -a')
+    output = ubman.run_command('pinmux status -a')
 
     assert ('pinctrl-gpio:' in output)
     assert ('a5        : gpio output .' in output)
@@ -40,36 +40,36 @@ def test_pinmux_status_all(u_boot_console):
 
 @pytest.mark.buildconfigspec('cmd_pinmux')
 @pytest.mark.boardspec('sandbox')
-def test_pinmux_list(u_boot_console):
+def test_pinmux_list(ubman):
     """Test that 'pinmux list' returns the pin-controller list."""
-    output = u_boot_console.run_command('pinmux list')
+    output = ubman.run_command('pinmux list')
     assert 'sandbox_pinctrl' in output
 
 @pytest.mark.buildconfigspec('cmd_pinmux')
-def test_pinmux_dev_bad(u_boot_console):
+def test_pinmux_dev_bad(ubman):
     """Test that 'pinmux dev' returns an error when trying to select a
     wrong pin controller."""
     pincontroller = 'bad_pin_controller_name'
-    output = u_boot_console.run_command('pinmux dev ' + pincontroller)
+    output = ubman.run_command('pinmux dev ' + pincontroller)
     expected_output = 'Can\'t get the pin-controller: ' + pincontroller + '!'
     assert (expected_output in output)
 
 @pytest.mark.buildconfigspec('cmd_pinmux')
 @pytest.mark.boardspec('sandbox')
-def test_pinmux_dev(u_boot_console):
+def test_pinmux_dev(ubman):
     """Test that 'pinmux dev' select the wanted pin controller."""
     pincontroller = 'pinctrl'
-    output = u_boot_console.run_command('pinmux dev ' + pincontroller)
+    output = ubman.run_command('pinmux dev ' + pincontroller)
     expected_output = 'dev: ' + pincontroller
     assert (expected_output in output)
 
 @pytest.mark.buildconfigspec('cmd_pinmux')
 @pytest.mark.boardspec('sandbox')
-def test_pinmux_status(u_boot_console):
+def test_pinmux_status(ubman):
     """Test that 'pinmux status' displays selected pincontroller's pin
     muxing descriptions."""
-    u_boot_console.run_command('pinmux dev pinctrl')
-    output = u_boot_console.run_command('pinmux status')
+    ubman.run_command('pinmux dev pinctrl')
+    output = ubman.run_command('pinmux status')
 
     assert (not 'pinctrl-gpio:' in output)
     assert (not 'pinctrl:' in output)
diff --git a/test/py/tests/test_pstore.py b/test/py/tests/test_pstore.py
index 5a35724f60a..70e07503ad3 100644
--- a/test/py/tests/test_pstore.py
+++ b/test/py/tests/test_pstore.py
@@ -3,7 +3,7 @@
 # Author: Frédéric Danis <frederic.danis@collabora.com>
 
 import pytest
-import u_boot_utils
+import utils
 import os
 import tempfile
 import shutil
@@ -15,63 +15,63 @@ PSTORE_PANIC2='test/py/tests/test_pstore_data_panic2.hex'
 PSTORE_CONSOLE='test/py/tests/test_pstore_data_console.hex'
 ADDR=0x01000008
 
-def load_pstore(u_boot_console):
+def load_pstore(ubman):
     """Load PStore records from sample files"""
 
-    output = u_boot_console.run_command_list([
+    output = ubman.run_command_list([
         'host load hostfs - 0x%x %s' % (PSTORE_ADDR,
-            os.path.join(u_boot_console.config.source_dir, PSTORE_PANIC1)),
+            os.path.join(ubman.config.source_dir, PSTORE_PANIC1)),
         'host load hostfs - 0x%x %s' % (PSTORE_ADDR + 4096,
-            os.path.join(u_boot_console.config.source_dir, PSTORE_PANIC2)),
+            os.path.join(ubman.config.source_dir, PSTORE_PANIC2)),
         'host load hostfs - 0x%x %s' % (PSTORE_ADDR + 253 * 4096,
-            os.path.join(u_boot_console.config.source_dir, PSTORE_CONSOLE)),
+            os.path.join(ubman.config.source_dir, PSTORE_CONSOLE)),
         'pstore set 0x%x 0x%x' % (PSTORE_ADDR, PSTORE_LENGTH)])
 
-def checkfile(u_boot_console, path, filesize, checksum):
+def checkfile(ubman, path, filesize, checksum):
     """Check file against MD5 checksum"""
 
-    output = u_boot_console.run_command_list([
+    output = ubman.run_command_list([
         'load hostfs - %x %s' % (ADDR, path),
         'printenv filesize'])
     assert('filesize=%x' % (filesize) in ''.join(output))
 
-    output = u_boot_console.run_command_list([
+    output = ubman.run_command_list([
         'md5sum %x $filesize' % ADDR,
         'setenv filesize'])
     assert(checksum in ''.join(output))
 
 @pytest.mark.buildconfigspec('cmd_pstore')
-def test_pstore_display_all_records(u_boot_console):
+def test_pstore_display_all_records(ubman):
     """Test that pstore displays all records."""
 
-    u_boot_console.run_command('')
-    load_pstore(u_boot_console)
-    response = u_boot_console.run_command('pstore display')
+    ubman.run_command('')
+    load_pstore(ubman)
+    response = ubman.run_command('pstore display')
     assert('**** Dump' in response)
     assert('**** Console' in response)
 
 @pytest.mark.buildconfigspec('cmd_pstore')
-def test_pstore_display_one_record(u_boot_console):
+def test_pstore_display_one_record(ubman):
     """Test that pstore displays only one record."""
 
-    u_boot_console.run_command('')
-    load_pstore(u_boot_console)
-    response = u_boot_console.run_command('pstore display dump 1')
+    ubman.run_command('')
+    load_pstore(ubman)
+    response = ubman.run_command('pstore display dump 1')
     assert('Panic#2 Part1' in response)
     assert('**** Console' not in response)
 
 @pytest.mark.buildconfigspec('cmd_pstore')
-def test_pstore_save_records(u_boot_console):
+def test_pstore_save_records(ubman):
     """Test that pstore saves all records."""
 
     outdir = tempfile.mkdtemp()
 
-    u_boot_console.run_command('')
-    load_pstore(u_boot_console)
-    u_boot_console.run_command('pstore save hostfs - %s' % (outdir))
+    ubman.run_command('')
+    load_pstore(ubman)
+    ubman.run_command('pstore save hostfs - %s' % (outdir))
 
-    checkfile(u_boot_console, '%s/dmesg-ramoops-0' % (outdir), 3798, '8059335ab4cfa62c77324c491659c503')
-    checkfile(u_boot_console, '%s/dmesg-ramoops-1' % (outdir), 4035, '3ff30df3429d81939c75d0070b5187b9')
-    checkfile(u_boot_console, '%s/console-ramoops-0' % (outdir), 4084, 'bb44de4a9b8ebd9b17ae98003287325b')
+    checkfile(ubman, '%s/dmesg-ramoops-0' % (outdir), 3798, '8059335ab4cfa62c77324c491659c503')
+    checkfile(ubman, '%s/dmesg-ramoops-1' % (outdir), 4035, '3ff30df3429d81939c75d0070b5187b9')
+    checkfile(ubman, '%s/console-ramoops-0' % (outdir), 4084, 'bb44de4a9b8ebd9b17ae98003287325b')
 
     shutil.rmtree(outdir)
diff --git a/test/py/tests/test_qfw.py b/test/py/tests/test_qfw.py
index 8b668c9721a..844cd3d9367 100644
--- a/test/py/tests/test_qfw.py
+++ b/test/py/tests/test_qfw.py
@@ -6,20 +6,20 @@
 import pytest
 
 @pytest.mark.buildconfigspec('cmd_qfw')
-def test_qfw_cpus(u_boot_console):
+def test_qfw_cpus(ubman):
     "Test QEMU firmware config reports the CPU count."
 
-    output = u_boot_console.run_command('qfw cpus')
+    output = ubman.run_command('qfw cpus')
     # The actual number varies depending on the board under test, so only
     # assert a non-zero output.
     assert 'cpu(s) online' in output
     assert '0 cpu(s) online' not in output
 
 @pytest.mark.buildconfigspec('cmd_qfw')
-def test_qfw_list(u_boot_console):
+def test_qfw_list(ubman):
     "Test QEMU firmware config lists devices."
 
-    output = u_boot_console.run_command('qfw list')
+    output = ubman.run_command('qfw list')
     # Assert either:
     # 1) 'test-one', from the sandbox driver, or
     # 2) 'bootorder', found in every real QEMU implementation.
diff --git a/test/py/tests/test_reset.py b/test/py/tests/test_reset.py
index 00fc31da57d..af079a70664 100644
--- a/test/py/tests/test_reset.py
+++ b/test/py/tests/test_reset.py
@@ -24,15 +24,15 @@ env__reset_test = {
 import pytest
 import test_000_version
 
-def setup_reset_env(u_boot_console):
-    if u_boot_console.config.env.get('env__reset_test_skip', False):
+def setup_reset_env(ubman):
+    if ubman.config.env.get('env__reset_test_skip', False):
         pytest.skip('reset test is not enabled')
 
-    output = u_boot_console.run_command('echo $modeboot')
+    output = ubman.run_command('echo $modeboot')
     if output:
         bootmode = output
     else:
-        f = u_boot_console.config.env.get('env__reset_test', None)
+        f = ubman.config.env.get('env__reset_test', None)
         if not f:
             pytest.skip('bootmode cannot be determined')
         bootmode = f.get('bootmode', 'jtagboot')
@@ -41,23 +41,23 @@ def setup_reset_env(u_boot_console):
         pytest.skip('skipping reset test due to jtag bootmode')
 
 @pytest.mark.buildconfigspec('hush_parser')
-def test_reset(u_boot_console):
+def test_reset(ubman):
     """Test the reset command in non-JTAG bootmode.
     It does COLD reset, which resets CPU, DDR and peripherals
     """
-    setup_reset_env(u_boot_console)
-    u_boot_console.run_command('reset', wait_for_reboot=True)
+    setup_reset_env(ubman)
+    ubman.run_command('reset', wait_for_reboot=True)
 
     # Checks the u-boot command prompt's functionality after reset
-    test_000_version.test_version(u_boot_console)
+    test_000_version.test_version(ubman)
 
 @pytest.mark.buildconfigspec('hush_parser')
-def test_reset_w(u_boot_console):
+def test_reset_w(ubman):
     """Test the reset -w command in non-JTAG bootmode.
     It does WARM reset, which resets CPU but keep DDR/peripherals active.
     """
-    setup_reset_env(u_boot_console)
-    u_boot_console.run_command('reset -w', wait_for_reboot=True)
+    setup_reset_env(ubman)
+    ubman.run_command('reset -w', wait_for_reboot=True)
 
     # Checks the u-boot command prompt's functionality after reset
-    test_000_version.test_version(u_boot_console)
+    test_000_version.test_version(ubman)
diff --git a/test/py/tests/test_sandbox_exit.py b/test/py/tests/test_sandbox_exit.py
index 706f5fa3594..9610adf1fe7 100644
--- a/test/py/tests/test_sandbox_exit.py
+++ b/test/py/tests/test_sandbox_exit.py
@@ -7,39 +7,39 @@ import signal
 
 @pytest.mark.boardspec('sandbox')
 @pytest.mark.buildconfigspec('sysreset_cmd_poweroff')
-def test_poweroff(u_boot_console):
+def test_poweroff(ubman):
     """Test that the "poweroff" command exits sandbox process."""
 
-    u_boot_console.run_command('poweroff', wait_for_prompt=False)
-    assert(u_boot_console.validate_exited())
+    ubman.run_command('poweroff', wait_for_prompt=False)
+    assert(ubman.validate_exited())
 
 @pytest.mark.boardspec('sandbox')
-def test_ctrl_c(u_boot_console):
+def test_ctrl_c(ubman):
     """Test that sending SIGINT to sandbox causes it to exit."""
 
-    u_boot_console.kill(signal.SIGINT)
-    assert(u_boot_console.validate_exited())
+    ubman.kill(signal.SIGINT)
+    assert(ubman.validate_exited())
 
 @pytest.mark.boardspec('sandbox')
 @pytest.mark.buildconfigspec('cmd_exception')
 @pytest.mark.buildconfigspec('sandbox_crash_reset')
-def test_exception_reset(u_boot_console):
+def test_exception_reset(ubman):
     """Test that SIGILL causes a reset."""
 
-    u_boot_console.run_command('exception undefined', wait_for_prompt=False)
-    m = u_boot_console.p.expect(['resetting ...', 'U-Boot'])
+    ubman.run_command('exception undefined', wait_for_prompt=False)
+    m = ubman.p.expect(['resetting ...', 'U-Boot'])
     if m != 0:
         raise Exception('SIGILL did not lead to reset')
-    m = u_boot_console.p.expect(['U-Boot', '=>'])
+    m = ubman.p.expect(['U-Boot', '=>'])
     if m != 0:
         raise Exception('SIGILL did not lead to reset')
-    u_boot_console.restart_uboot()
+    ubman.restart_uboot()
 
 @pytest.mark.boardspec('sandbox')
 @pytest.mark.buildconfigspec('cmd_exception')
 @pytest.mark.notbuildconfigspec('sandbox_crash_reset')
-def test_exception_exit(u_boot_console):
+def test_exception_exit(ubman):
     """Test that SIGILL causes a reset."""
 
-    u_boot_console.run_command('exception undefined', wait_for_prompt=False)
-    assert(u_boot_console.validate_exited())
+    ubman.run_command('exception undefined', wait_for_prompt=False)
+    assert(ubman.validate_exited())
diff --git a/test/py/tests/test_sandbox_opts.py b/test/py/tests/test_sandbox_opts.py
index 422b43cb3bc..48f5b313870 100644
--- a/test/py/tests/test_sandbox_opts.py
+++ b/test/py/tests/test_sandbox_opts.py
@@ -4,27 +4,25 @@
 
 import pytest
 
-import u_boot_utils as util
+import utils
 
 # This is needed for Azure, since the default '..' directory is not writeable
 TMPDIR = '/tmp/test_cmdline'
 
 @pytest.mark.slow
 @pytest.mark.boardspec('sandbox')
-def test_sandbox_cmdline(u_boot_console):
+def test_sandbox_cmdline(ubman):
     """Test building sandbox without CONFIG_CMDLINE"""
-    cons = u_boot_console
 
-    out = util.run_and_log(
-        cons, ['./tools/buildman/buildman', '-m', '--board', 'sandbox',
+    utils.run_and_log(
+        ubman, ['./tools/buildman/buildman', '-m', '--board', 'sandbox',
                '-a', '~CMDLINE', '-o', TMPDIR])
 
 @pytest.mark.slow
 @pytest.mark.boardspec('sandbox')
-def test_sandbox_lto(u_boot_console):
+def test_sandbox_lto(ubman):
     """Test building sandbox without CONFIG_LTO"""
-    cons = u_boot_console
 
-    out = util.run_and_log(
-        cons, ['./tools/buildman/buildman', '-m', '--board', 'sandbox',
+    utils.run_and_log(
+        ubman, ['./tools/buildman/buildman', '-m', '--board', 'sandbox',
                '-a', '~LTO', '-o', TMPDIR])
diff --git a/test/py/tests/test_saveenv.py b/test/py/tests/test_saveenv.py
index 7faa3bdf93d..019b229d30e 100644
--- a/test/py/tests/test_saveenv.py
+++ b/test/py/tests/test_saveenv.py
@@ -28,15 +28,15 @@ import string
 import uuid
 
 # Setup the env
-def setup_saveenv_env(u_boot_console):
-    if u_boot_console.config.env.get('env__saveenv_test_skip', False):
+def setup_saveenv_env(ubman):
+    if ubman.config.env.get('env__saveenv_test_skip', False):
         pytest.skip('saveenv test is not enabled')
 
-    output = u_boot_console.run_command('echo $modeboot')
+    output = ubman.run_command('echo $modeboot')
     if output:
         bootmode = output
     else:
-        f = u_boot_console.config.env.get('env__saveenv_test', None)
+        f = ubman.config.env.get('env__saveenv_test', None)
         if not f:
             pytest.skip('bootmode cannot be determined')
         bootmode = f.get('bootmode', 'jtagboot')
@@ -45,39 +45,39 @@ def setup_saveenv_env(u_boot_console):
         pytest.skip('skipping saveenv test due to jtag bootmode')
 
 # Check return code
-def ret_code(u_boot_console):
-    return u_boot_console.run_command('echo $?')
+def ret_code(ubman):
+    return ubman.run_command('echo $?')
 
 # Verify env variable
-def check_env(u_boot_console, var_name, var_value):
+def check_env(ubman, var_name, var_value):
     if var_value:
-        output = u_boot_console.run_command(f'printenv {var_name}')
+        output = ubman.run_command(f'printenv {var_name}')
         var_value = str(var_value)
         if (var_value.startswith("'") and var_value.endswith("'")) or (
             var_value.startswith('"') and var_value.endswith('"')
         ):
             var_value = var_value.split(var_value[-1])[1]
         assert var_value in output
-        assert ret_code(u_boot_console).endswith('0')
+        assert ret_code(ubman).endswith('0')
     else:
-        u_boot_console.p.send(f'printenv {var_name}\n')
-        output = u_boot_console.p.expect(['not defined'])
+        ubman.p.send(f'printenv {var_name}\n')
+        output = ubman.p.expect(['not defined'])
         assert output == 0
-        assert ret_code(u_boot_console).endswith('1')
+        assert ret_code(ubman).endswith('1')
 
 # Set env variable
-def set_env(u_boot_console, var_name, var_value):
-    u_boot_console.run_command(f'setenv {var_name} {var_value}')
-    assert ret_code(u_boot_console).endswith('0')
-    check_env(u_boot_console, var_name, var_value)
+def set_env(ubman, var_name, var_value):
+    ubman.run_command(f'setenv {var_name} {var_value}')
+    assert ret_code(ubman).endswith('0')
+    check_env(ubman, var_name, var_value)
 
 @pytest.mark.buildconfigspec('cmd_saveenv')
 @pytest.mark.buildconfigspec('hush_parser')
-def test_saveenv(u_boot_console):
+def test_saveenv(ubman):
     """Test the saveenv command in non-JTAG bootmode.
     It saves the U-Boot environment in persistent storage.
     """
-    setup_saveenv_env(u_boot_console)
+    setup_saveenv_env(ubman)
 
     # Set env for random mac address
     rand_mac = '%02x:%02x:%02x:%02x:%02x:%02x' % (
@@ -88,50 +88,50 @@ def test_saveenv(u_boot_console):
         random.randint(0, 255),
         random.randint(0, 255),
     )
-    set_env(u_boot_console, 'mac_addr', rand_mac)
+    set_env(ubman, 'mac_addr', rand_mac)
 
     # Set env for random IPv4 address
     rand_ipv4 = ipaddress.IPv4Address._string_from_ip_int(
         random.randint(0, ipaddress.IPv4Address._ALL_ONES)
     )
-    set_env(u_boot_console, 'ipv4_addr', rand_ipv4)
+    set_env(ubman, 'ipv4_addr', rand_ipv4)
 
     # Set env for random IPv6 address
     rand_ipv6 = ipaddress.IPv6Address._string_from_ip_int(
         random.randint(0, ipaddress.IPv6Address._ALL_ONES)
     )
-    set_env(u_boot_console, 'ipv6_addr', rand_ipv6)
+    set_env(ubman, 'ipv6_addr', rand_ipv6)
 
     # Set env for random number
     rand_num = random.randrange(1, 10**9)
-    set_env(u_boot_console, 'num_var', rand_num)
+    set_env(ubman, 'num_var', rand_num)
 
     # Set env for uuid
     uuid_str = uuid.uuid4().hex.lower()
-    set_env(u_boot_console, 'uuid_var', uuid_str)
+    set_env(ubman, 'uuid_var', uuid_str)
 
     # Set env for random string including special characters
     sc = "!#%&()*+,-./:;<=>?@[\\]^_`{|}~"
     rand_str = ''.join(
         random.choices(' ' + string.ascii_letters + sc + string.digits, k=300)
     )
-    set_env(u_boot_console, 'str_var', f'"{rand_str}"')
+    set_env(ubman, 'str_var', f'"{rand_str}"')
 
     # Set env for empty string
-    set_env(u_boot_console, 'empty_var', '')
+    set_env(ubman, 'empty_var', '')
 
     # Save the env variables
-    u_boot_console.run_command('saveenv')
-    assert ret_code(u_boot_console).endswith('0')
+    ubman.run_command('saveenv')
+    assert ret_code(ubman).endswith('0')
 
     # Reboot
-    u_boot_console.run_command('reset', wait_for_reboot=True)
+    ubman.run_command('reset', wait_for_reboot=True)
 
     # Verify the saved env variables
-    check_env(u_boot_console, 'mac_addr', rand_mac)
-    check_env(u_boot_console, 'ipv4_addr', rand_ipv4)
-    check_env(u_boot_console, 'ipv6_addr', rand_ipv6)
-    check_env(u_boot_console, 'num_var', rand_num)
-    check_env(u_boot_console, 'uuid_var', uuid_str)
-    check_env(u_boot_console, 'str_var', rand_str)
-    check_env(u_boot_console, 'empty_var', '')
+    check_env(ubman, 'mac_addr', rand_mac)
+    check_env(ubman, 'ipv4_addr', rand_ipv4)
+    check_env(ubman, 'ipv6_addr', rand_ipv6)
+    check_env(ubman, 'num_var', rand_num)
+    check_env(ubman, 'uuid_var', uuid_str)
+    check_env(ubman, 'str_var', rand_str)
+    check_env(ubman, 'empty_var', '')
diff --git a/test/py/tests/test_scp03.py b/test/py/tests/test_scp03.py
index 1a104b365f7..414b4251a69 100644
--- a/test/py/tests/test_scp03.py
+++ b/test/py/tests/test_scp03.py
@@ -11,17 +11,17 @@ For additional details check doc/usage/scp03.rst
 """
 
 import pytest
-import u_boot_utils as util
+import utils
 
 @pytest.mark.buildconfigspec('cmd_scp03')
-def test_scp03(u_boot_console):
+def test_scp03(ubman):
     """Enable and provision keys with SCP03
     """
 
     success_str1 = "SCP03 is enabled"
     success_str2 = "SCP03 is provisioned"
 
-    response = u_boot_console.run_command('scp03 enable')
+    response = ubman.run_command('scp03 enable')
     assert success_str1 in response
-    response = u_boot_console.run_command('scp03 provision')
+    response = ubman.run_command('scp03 provision')
     assert success_str2 in response
diff --git a/test/py/tests/test_scsi.py b/test/py/tests/test_scsi.py
index 445693cafd7..2a35e47e558 100644
--- a/test/py/tests/test_scsi.py
+++ b/test/py/tests/test_scsi.py
@@ -19,8 +19,8 @@ env__scsi_device_test = {
 }
 """
 
-def scsi_setup(u_boot_console):
-    f = u_boot_console.config.env.get('env__scsi_device_test', None)
+def scsi_setup(ubman):
+    f = ubman.config.env.get('env__scsi_device_test', None)
     if not f:
         pytest.skip('No SCSI device to test')
 
@@ -39,54 +39,54 @@ def scsi_setup(u_boot_console):
     return dev_num, dev_type, dev_size
 
 @pytest.mark.buildconfigspec('cmd_scsi')
-def test_scsi_reset(u_boot_console):
-    dev_num, dev_type, dev_size = scsi_setup(u_boot_console)
-    output = u_boot_console.run_command('scsi reset')
+def test_scsi_reset(ubman):
+    dev_num, dev_type, dev_size = scsi_setup(ubman)
+    output = ubman.run_command('scsi reset')
     assert f'Device {dev_num}:' in output
     assert f'Type: {dev_type}' in output
     assert f'Capacity: {dev_size}' in output
-    output = u_boot_console.run_command('echo $?')
+    output = ubman.run_command('echo $?')
     assert output.endswith('0')
 
 @pytest.mark.buildconfigspec('cmd_scsi')
-def test_scsi_info(u_boot_console):
-    dev_num, dev_type, dev_size = scsi_setup(u_boot_console)
-    output = u_boot_console.run_command('scsi info')
+def test_scsi_info(ubman):
+    dev_num, dev_type, dev_size = scsi_setup(ubman)
+    output = ubman.run_command('scsi info')
     assert f'Device {dev_num}:' in output
     assert f'Type: {dev_type}' in output
     assert f'Capacity: {dev_size}' in output
-    output = u_boot_console.run_command('echo $?')
+    output = ubman.run_command('echo $?')
     assert output.endswith('0')
 
 @pytest.mark.buildconfigspec('cmd_scsi')
-def test_scsi_scan(u_boot_console):
-    dev_num, dev_type, dev_size = scsi_setup(u_boot_console)
-    output = u_boot_console.run_command('scsi scan')
+def test_scsi_scan(ubman):
+    dev_num, dev_type, dev_size = scsi_setup(ubman)
+    output = ubman.run_command('scsi scan')
     assert f'Device {dev_num}:' in output
     assert f'Type: {dev_type}' in output
     assert f'Capacity: {dev_size}' in output
-    output = u_boot_console.run_command('echo $?')
+    output = ubman.run_command('echo $?')
     assert output.endswith('0')
 
 @pytest.mark.buildconfigspec('cmd_scsi')
-def test_scsi_dev(u_boot_console):
-    dev_num, dev_type, dev_size = scsi_setup(u_boot_console)
-    output = u_boot_console.run_command('scsi device')
+def test_scsi_dev(ubman):
+    dev_num, dev_type, dev_size = scsi_setup(ubman)
+    output = ubman.run_command('scsi device')
     assert 'no scsi devices available' not in output
     assert f'device {dev_num}:' in output
     assert f'Type: {dev_type}' in output
     assert f'Capacity: {dev_size}' in output
-    output = u_boot_console.run_command('echo $?')
+    output = ubman.run_command('echo $?')
     assert output.endswith('0')
-    output = u_boot_console.run_command('scsi device %d' % dev_num)
+    output = ubman.run_command('scsi device %d' % dev_num)
     assert 'is now current device' in output
-    output = u_boot_console.run_command('echo $?')
+    output = ubman.run_command('echo $?')
     assert output.endswith('0')
 
 @pytest.mark.buildconfigspec('cmd_scsi')
-def test_scsi_part(u_boot_console):
-    test_scsi_dev(u_boot_console)
-    output = u_boot_console.run_command('scsi part')
+def test_scsi_part(ubman):
+    test_scsi_dev(ubman)
+    output = ubman.run_command('scsi part')
     assert 'Partition Map for scsi device' in output
-    output = u_boot_console.run_command('echo $?')
+    output = ubman.run_command('echo $?')
     assert output.endswith('0')
diff --git a/test/py/tests/test_semihosting/test_hostfs.py b/test/py/tests/test_semihosting/test_hostfs.py
index 51f6fa7702c..1bead69b507 100644
--- a/test/py/tests/test_semihosting/test_hostfs.py
+++ b/test/py/tests/test_semihosting/test_hostfs.py
@@ -6,28 +6,28 @@
 import pytest
 
 @pytest.mark.buildconfigspec('semihosting')
-def test_semihosting_hostfs(u_boot_console, semihosting_data):
+def test_semihosting_hostfs(ubman, semihosting_data):
     """ Unit test for semihosting
 
     Args:
-        u_boot_console -- U-Boot console
+        ubman -- U-Boot console
         semihosting_data -- Path to the disk image used for testing.
     """
-    response = u_boot_console.run_command(
+    response = ubman.run_command(
         f'load hostfs - $loadaddr {semihosting_data}')
     assert '11 bytes read' in response
 
-    response = u_boot_console.run_command(
+    response = ubman.run_command(
         'crc32 $loadaddr $filesize')
     assert '==> 60cfccfc' in response
 
-    u_boot_console.run_command(
+    ubman.run_command(
         f'save hostfs - $loadaddr {semihosting_data} 11 11')
 
-    response = u_boot_console.run_command(
+    response = ubman.run_command(
         f'load hostfs - $loadaddr {semihosting_data} 4 13')
     assert '4 bytes read' in response
 
-    response = u_boot_console.run_command(
+    response = ubman.run_command(
         'crc32 $loadaddr $filesize')
     assert '==> e29063ea' in response
diff --git a/test/py/tests/test_sf.py b/test/py/tests/test_sf.py
index adf8b7dc893..5b4ba80f18b 100644
--- a/test/py/tests/test_sf.py
+++ b/test/py/tests/test_sf.py
@@ -5,7 +5,7 @@
 import re
 import pytest
 import random
-import u_boot_utils
+import utils
 
 """
 Note: This test relies on boardenv_* containing configuration values to define
@@ -44,11 +44,11 @@ env__sf_configs = (
 )
 """
 
-def sf_prepare(u_boot_console, env__sf_config):
+def sf_prepare(ubman, env__sf_config):
     """Check global state of the SPI Flash before running any test.
 
    Args:
-        u_boot_console: A U-Boot console connection.
+        ubman: A U-Boot console connection.
         env__sf_config: The single SPI Flash device configuration on which to
             run the tests.
 
@@ -57,7 +57,7 @@ def sf_prepare(u_boot_console, env__sf_config):
     """
 
     sf_params = {}
-    sf_params['ram_base'] = u_boot_utils.find_ram_base(u_boot_console)
+    sf_params['ram_base'] = utils.find_ram_base(ubman)
 
     probe_id = env__sf_config.get('id', 0)
     speed = env__sf_config.get('speed', 0)
@@ -69,7 +69,7 @@ def sf_prepare(u_boot_console, env__sf_config):
 
     cmd = 'sf probe %d %d' % (probe_id, sf_params['speed'])
 
-    output = u_boot_console.run_command(cmd)
+    output = ubman.run_command(cmd)
     assert 'SF: Detected' in output, 'No Flash device available'
 
     m = re.search('page size (.+?) Bytes', output)
@@ -101,12 +101,12 @@ def sf_prepare(u_boot_console, env__sf_config):
 
     return sf_params
 
-def sf_read(u_boot_console, env__sf_config, sf_params):
+def sf_read(ubman, env__sf_config, sf_params):
     """Helper function used to read and compute the CRC32 value of a section of
     SPI Flash memory.
 
     Args:
-        u_boot_console: A U-Boot console connection.
+        ubman: A U-Boot console connection.
         env__sf_config: The single SPI Flash device configuration on which to
             run the tests.
         sf_params: SPI Flash parameters.
@@ -122,26 +122,26 @@ def sf_read(u_boot_console, env__sf_config, sf_params):
     crc_expected = env__sf_config.get('crc32', None)
 
     cmd = 'mw.b %08x %02x %x' % (addr, pattern, count)
-    u_boot_console.run_command(cmd)
-    crc_pattern = u_boot_utils.crc32(u_boot_console, addr, count)
+    ubman.run_command(cmd)
+    crc_pattern = utils.crc32(ubman, addr, count)
     if crc_expected:
         assert crc_pattern != crc_expected
 
     cmd = 'sf read %08x %08x %x' % (addr, offset, count)
-    response = u_boot_console.run_command(cmd)
+    response = ubman.run_command(cmd)
     assert 'Read: OK' in response, 'Read operation failed'
-    crc_readback = u_boot_utils.crc32(u_boot_console, addr, count)
+    crc_readback = utils.crc32(ubman, addr, count)
     assert crc_pattern != crc_readback, 'sf read did not update RAM content.'
     if crc_expected:
         assert crc_readback == crc_expected
 
     return crc_readback
 
-def sf_update(u_boot_console, env__sf_config, sf_params):
+def sf_update(ubman, env__sf_config, sf_params):
     """Helper function used to update a section of SPI Flash memory.
 
    Args:
-        u_boot_console: A U-Boot console connection.
+        ubman: A U-Boot console connection.
         env__sf_config: The single SPI Flash device configuration on which to
            run the tests.
 
@@ -155,63 +155,63 @@ def sf_update(u_boot_console, env__sf_config, sf_params):
     pattern = int(random.random() * 0xFF)
 
     cmd = 'mw.b %08x %02x %x' % (addr, pattern, count)
-    u_boot_console.run_command(cmd)
-    crc_pattern = u_boot_utils.crc32(u_boot_console, addr, count)
+    ubman.run_command(cmd)
+    crc_pattern = utils.crc32(ubman, addr, count)
 
     cmd = 'sf update %08x %08x %x' % (addr, offset, count)
-    u_boot_console.run_command(cmd)
-    crc_readback = sf_read(u_boot_console, env__sf_config, sf_params)
+    ubman.run_command(cmd)
+    crc_readback = sf_read(ubman, env__sf_config, sf_params)
 
     assert crc_readback == crc_pattern
 
 @pytest.mark.buildconfigspec('cmd_sf')
 @pytest.mark.buildconfigspec('cmd_crc32')
 @pytest.mark.buildconfigspec('cmd_memory')
-def test_sf_read(u_boot_console, env__sf_config):
-    sf_params = sf_prepare(u_boot_console, env__sf_config)
-    sf_read(u_boot_console, env__sf_config, sf_params)
+def test_sf_read(ubman, env__sf_config):
+    sf_params = sf_prepare(ubman, env__sf_config)
+    sf_read(ubman, env__sf_config, sf_params)
 
 @pytest.mark.buildconfigspec('cmd_sf')
 @pytest.mark.buildconfigspec('cmd_crc32')
 @pytest.mark.buildconfigspec('cmd_memory')
-def test_sf_read_twice(u_boot_console, env__sf_config):
-    sf_params = sf_prepare(u_boot_console, env__sf_config)
+def test_sf_read_twice(ubman, env__sf_config):
+    sf_params = sf_prepare(ubman, env__sf_config)
 
-    crc1 = sf_read(u_boot_console, env__sf_config, sf_params)
+    crc1 = sf_read(ubman, env__sf_config, sf_params)
     sf_params['ram_base'] += 0x100
-    crc2 = sf_read(u_boot_console, env__sf_config, sf_params)
+    crc2 = sf_read(ubman, env__sf_config, sf_params)
 
     assert crc1 == crc2, 'CRC32 of two successive read operation do not match'
 
 @pytest.mark.buildconfigspec('cmd_sf')
 @pytest.mark.buildconfigspec('cmd_crc32')
 @pytest.mark.buildconfigspec('cmd_memory')
-def test_sf_erase(u_boot_console, env__sf_config):
+def test_sf_erase(ubman, env__sf_config):
     if not env__sf_config.get('writeable', False):
         pytest.skip('Flash config is tagged as not writeable')
 
-    sf_params = sf_prepare(u_boot_console, env__sf_config)
+    sf_params = sf_prepare(ubman, env__sf_config)
     addr = sf_params['ram_base']
     offset = env__sf_config['offset']
     count = sf_params['len']
 
     cmd = 'sf erase %08x %x' % (offset, count)
-    output = u_boot_console.run_command(cmd)
+    output = ubman.run_command(cmd)
     assert 'Erased: OK' in output, 'Erase operation failed'
 
     cmd = 'mw.b %08x ff %x' % (addr, count)
-    u_boot_console.run_command(cmd)
-    crc_ffs = u_boot_utils.crc32(u_boot_console, addr, count)
+    ubman.run_command(cmd)
+    crc_ffs = utils.crc32(ubman, addr, count)
 
-    crc_read = sf_read(u_boot_console, env__sf_config, sf_params)
+    crc_read = sf_read(ubman, env__sf_config, sf_params)
     assert crc_ffs == crc_read, 'Unexpected CRC32 after erase operation.'
 
 @pytest.mark.buildconfigspec('cmd_sf')
 @pytest.mark.buildconfigspec('cmd_crc32')
 @pytest.mark.buildconfigspec('cmd_memory')
-def test_sf_update(u_boot_console, env__sf_config):
+def test_sf_update(ubman, env__sf_config):
     if not env__sf_config.get('writeable', False):
         pytest.skip('Flash config is tagged as not writeable')
 
-    sf_params = sf_prepare(u_boot_console, env__sf_config)
-    sf_update(u_boot_console, env__sf_config, sf_params)
+    sf_params = sf_prepare(ubman, env__sf_config)
+    sf_update(ubman, env__sf_config, sf_params)
diff --git a/test/py/tests/test_shell_basics.py b/test/py/tests/test_shell_basics.py
index 68a3f892f6b..97e22af5da5 100644
--- a/test/py/tests/test_shell_basics.py
+++ b/test/py/tests/test_shell_basics.py
@@ -7,39 +7,39 @@ import pytest
 
 pytestmark = pytest.mark.buildconfigspec('cmd_echo')
 
-def test_shell_execute(u_boot_console):
+def test_shell_execute(ubman):
     """Test any shell command."""
 
-    response = u_boot_console.run_command('echo hello')
+    response = ubman.run_command('echo hello')
     assert response.strip() == 'hello'
 
-def test_shell_semicolon_two(u_boot_console):
+def test_shell_semicolon_two(ubman):
     """Test two shell commands separate by a semi-colon."""
 
     cmd = 'echo hello; echo world'
-    response = u_boot_console.run_command(cmd)
+    response = ubman.run_command(cmd)
     # This validation method ignores the exact whitespace between the strings
     assert response.index('hello') < response.index('world')
 
-def test_shell_semicolon_three(u_boot_console):
+def test_shell_semicolon_three(ubman):
     """Test three shell commands separate by a semi-colon, with variable
     expansion dependencies between them."""
 
     cmd = 'setenv list 1; setenv list ${list}2; setenv list ${list}3; ' + \
         'echo ${list}'
-    response = u_boot_console.run_command(cmd)
+    response = ubman.run_command(cmd)
     assert response.strip() == '123'
-    u_boot_console.run_command('setenv list')
+    ubman.run_command('setenv list')
 
-def test_shell_run(u_boot_console):
+def test_shell_run(ubman):
     """Test the "run" shell command."""
 
-    u_boot_console.run_command('setenv foo \'setenv monty 1; setenv python 2\'')
-    u_boot_console.run_command('run foo')
-    response = u_boot_console.run_command('echo ${monty}')
+    ubman.run_command('setenv foo \'setenv monty 1; setenv python 2\'')
+    ubman.run_command('run foo')
+    response = ubman.run_command('echo ${monty}')
     assert response.strip() == '1'
-    response = u_boot_console.run_command('echo ${python}')
+    response = ubman.run_command('echo ${python}')
     assert response.strip() == '2'
-    u_boot_console.run_command('setenv foo')
-    u_boot_console.run_command('setenv monty')
-    u_boot_console.run_command('setenv python')
+    ubman.run_command('setenv foo')
+    ubman.run_command('setenv monty')
+    ubman.run_command('setenv python')
diff --git a/test/py/tests/test_sleep.py b/test/py/tests/test_sleep.py
index 8965fc3fea9..f1bf34e05b2 100644
--- a/test/py/tests/test_sleep.py
+++ b/test/py/tests/test_sleep.py
@@ -19,43 +19,43 @@ env__sleep_margin = 0.25
 
 """
 
-def test_sleep(u_boot_console):
+def test_sleep(ubman):
     """Test the sleep command, and validate that it sleeps for approximately
     the correct amount of time."""
 
-    sleep_skip = u_boot_console.config.env.get('env__sleep_accurate', True)
+    sleep_skip = ubman.config.env.get('env__sleep_accurate', True)
     if not sleep_skip:
         pytest.skip('sleep is not accurate')
 
-    if u_boot_console.config.buildconfig.get('config_cmd_sleep', 'n') != 'y':
+    if ubman.config.buildconfig.get('config_cmd_sleep', 'n') != 'y':
         pytest.skip('sleep command not supported')
 
     # 3s isn't too long, but is enough to cross a few second boundaries.
-    sleep_time = u_boot_console.config.env.get('env__sleep_time', 3)
-    sleep_margin = u_boot_console.config.env.get('env__sleep_margin', 0.25)
+    sleep_time = ubman.config.env.get('env__sleep_time', 3)
+    sleep_margin = ubman.config.env.get('env__sleep_margin', 0.25)
     tstart = time.time()
-    u_boot_console.run_command('sleep %d' % sleep_time)
+    ubman.run_command('sleep %d' % sleep_time)
     tend = time.time()
     elapsed = tend - tstart
     assert elapsed >= (sleep_time - 0.01)
-    if not u_boot_console.config.gdbserver:
+    if not ubman.config.gdbserver:
         # margin is hopefully enough to account for any system overhead.
         assert elapsed < (sleep_time + sleep_margin)
 
 @pytest.mark.buildconfigspec("cmd_time")
-def test_time(u_boot_console):
+def test_time(ubman):
     """Test the time command, and validate that it gives approximately the
     correct amount of command execution time."""
 
-    sleep_skip = u_boot_console.config.env.get("env__sleep_accurate", True)
+    sleep_skip = ubman.config.env.get("env__sleep_accurate", True)
     if not sleep_skip:
         pytest.skip("sleep is not accurate")
 
-    sleep_time = u_boot_console.config.env.get("env__sleep_time", 10)
-    sleep_margin = u_boot_console.config.env.get("env__sleep_margin", 0.25)
-    output = u_boot_console.run_command("time sleep %d" % sleep_time)
+    sleep_time = ubman.config.env.get("env__sleep_time", 10)
+    sleep_margin = ubman.config.env.get("env__sleep_margin", 0.25)
+    output = ubman.run_command("time sleep %d" % sleep_time)
     execute_time = float(output.split()[1])
     assert sleep_time >= (execute_time - 0.01)
-    if not u_boot_console.config.gdbserver:
+    if not ubman.config.gdbserver:
         # margin is hopefully enough to account for any system overhead.
         assert sleep_time < (execute_time + sleep_margin)
diff --git a/test/py/tests/test_smbios.py b/test/py/tests/test_smbios.py
index 0405a9b9d38..3b85a7cc661 100644
--- a/test/py/tests/test_smbios.py
+++ b/test/py/tests/test_smbios.py
@@ -7,9 +7,9 @@ import pytest
 @pytest.mark.buildconfigspec('cmd_smbios')
 @pytest.mark.notbuildconfigspec('qfw_smbios')
 @pytest.mark.notbuildconfigspec('sandbox')
-def test_cmd_smbios(u_boot_console):
+def test_cmd_smbios(ubman):
     """Run the smbios command"""
-    output = u_boot_console.run_command('smbios')
+    output = ubman.run_command('smbios')
     assert 'DMI type 127,' in output
 
 @pytest.mark.buildconfigspec('cmd_smbios')
@@ -19,18 +19,18 @@ def test_cmd_smbios(u_boot_console):
 # QEMU v8.2.0 lacks SMBIOS support for RISC-V
 # Once support is available in our Docker image we can remove the constraint.
 @pytest.mark.notbuildconfigspec('riscv')
-def test_cmd_smbios_qemu(u_boot_console):
+def test_cmd_smbios_qemu(ubman):
     """Run the smbios command on QEMU"""
-    output = u_boot_console.run_command('smbios')
+    output = ubman.run_command('smbios')
     assert 'DMI type 1,' in output
     assert 'Manufacturer: QEMU' in output
     assert 'DMI type 127,' in output
 
 @pytest.mark.buildconfigspec('cmd_smbios')
 @pytest.mark.buildconfigspec('sandbox')
-def test_cmd_smbios_sandbox(u_boot_console):
+def test_cmd_smbios_sandbox(ubman):
     """Run the smbios command on the sandbox"""
-    output = u_boot_console.run_command('smbios')
+    output = ubman.run_command('smbios')
     assert 'DMI type 0,' in output
     assert 'Vendor: U-Boot' in output
     assert 'DMI type 1,' in output
@@ -43,9 +43,9 @@ def test_cmd_smbios_sandbox(u_boot_console):
 @pytest.mark.buildconfigspec('cmd_smbios')
 @pytest.mark.buildconfigspec('sysinfo_smbios')
 @pytest.mark.buildconfigspec('generate_smbios_table_verbose')
-def test_cmd_smbios_sysinfo_verbose(u_boot_console):
+def test_cmd_smbios_sysinfo_verbose(ubman):
     """Run the smbios command"""
-    output = u_boot_console.run_command('smbios')
+    output = ubman.run_command('smbios')
     assert 'DMI type 0,' in output
     assert 'Vendor: U-Boot' in output
     assert 'DMI type 1,' in output
diff --git a/test/py/tests/test_source.py b/test/py/tests/test_source.py
index bbc311df6d1..970d8c79869 100644
--- a/test/py/tests/test_source.py
+++ b/test/py/tests/test_source.py
@@ -3,35 +3,34 @@
 
 import os
 import pytest
-import u_boot_utils as util
+import utils
 
 @pytest.mark.boardspec('sandbox')
 @pytest.mark.buildconfigspec('cmd_echo')
 @pytest.mark.buildconfigspec('cmd_source')
 @pytest.mark.buildconfigspec('fit')
-def test_source(u_boot_console):
+def test_source(ubman):
     # Compile our test script image
-    cons = u_boot_console
-    mkimage = os.path.join(cons.config.build_dir, 'tools/mkimage')
-    its = os.path.join(cons.config.source_dir, 'test/py/tests/source.its')
-    fit = os.path.join(cons.config.build_dir, 'source.itb')
-    util.run_and_log(cons, (mkimage, '-f', its, fit))
-    cons.run_command(f'host load hostfs - $loadaddr {fit}')
+    mkimage = os.path.join(ubman.config.build_dir, 'tools/mkimage')
+    its = os.path.join(ubman.config.source_dir, 'test/py/tests/source.its')
+    fit = os.path.join(ubman.config.build_dir, 'source.itb')
+    utils.run_and_log(ubman, (mkimage, '-f', its, fit))
+    ubman.run_command(f'host load hostfs - $loadaddr {fit}')
 
-    assert '2' in cons.run_command('source')
-    assert '1' in cons.run_command('source :')
-    assert '1' in cons.run_command('source :script-1')
-    assert '2' in cons.run_command('source :script-2')
-    assert 'Fail' in cons.run_command('source :not-a-script || echo Fail')
-    assert '2' in cons.run_command('source \\#')
-    assert '1' in cons.run_command('source \\#conf-1')
-    assert '2' in cons.run_command('source \\#conf-2')
+    assert '2' in ubman.run_command('source')
+    assert '1' in ubman.run_command('source :')
+    assert '1' in ubman.run_command('source :script-1')
+    assert '2' in ubman.run_command('source :script-2')
+    assert 'Fail' in ubman.run_command('source :not-a-script || echo Fail')
+    assert '2' in ubman.run_command('source \\#')
+    assert '1' in ubman.run_command('source \\#conf-1')
+    assert '2' in ubman.run_command('source \\#conf-2')
 
-    cons.run_command('fdt addr $loadaddr')
-    cons.run_command('fdt rm /configurations default')
-    assert '1' in cons.run_command('source')
-    assert 'Fail' in cons.run_command('source \\# || echo Fail')
+    ubman.run_command('fdt addr $loadaddr')
+    ubman.run_command('fdt rm /configurations default')
+    assert '1' in ubman.run_command('source')
+    assert 'Fail' in ubman.run_command('source \\# || echo Fail')
 
-    cons.run_command('fdt rm /images default')
-    assert 'Fail' in cons.run_command('source || echo Fail')
-    assert 'Fail' in cons.run_command('source \\# || echo Fail')
+    ubman.run_command('fdt rm /images default')
+    assert 'Fail' in ubman.run_command('source || echo Fail')
+    assert 'Fail' in ubman.run_command('source \\# || echo Fail')
diff --git a/test/py/tests/test_spi.py b/test/py/tests/test_spi.py
index 0abdfa78b76..dd767528dbf 100644
--- a/test/py/tests/test_spi.py
+++ b/test/py/tests/test_spi.py
@@ -51,7 +51,7 @@ env__spi_lock_unlock = {
 import random
 import re
 import pytest
-import u_boot_utils
+import utils
 
 SPI_DATA = {}
 EXPECTED_ERASE = 'Erased: OK'
@@ -71,9 +71,9 @@ EXPECTED_WRITE_ERRORS = [
     'Written: ERROR',
 ]
 
-def get_params_spi(u_boot_console):
+def get_params_spi(ubman):
     ''' Get SPI device test parameters from boardenv file '''
-    f = u_boot_console.config.env.get('env__spi_device_test', None)
+    f = ubman.config.env.get('env__spi_device_test', None)
     if not f:
         pytest.skip('No SPI test device configured')
 
@@ -88,9 +88,9 @@ def get_params_spi(u_boot_console):
 
     return bus, cs, mode, part_name, timeout
 
-def spi_find_freq_range(u_boot_console):
+def spi_find_freq_range(ubman):
     '''Find out minimum and maximum frequnecies that SPI device can operate'''
-    f = u_boot_console.config.env.get('env__spi_device_test', None)
+    f = ubman.config.env.get('env__spi_device_test', None)
     if not f:
         pytest.skip('No SPI test device configured')
 
@@ -107,11 +107,11 @@ def spi_find_freq_range(u_boot_console):
 
     return min_f, max_f, iterations
 
-def spi_pre_commands(u_boot_console, freq):
+def spi_pre_commands(ubman, freq):
     ''' Find out SPI family flash memory parameters '''
-    bus, cs, mode, part_name, timeout = get_params_spi(u_boot_console)
+    bus, cs, mode, part_name, timeout = get_params_spi(ubman)
 
-    output = u_boot_console.run_command(f'sf probe {bus}:{cs} {freq} {mode}')
+    output = ubman.run_command(f'sf probe {bus}:{cs} {freq} {mode}')
     if not 'SF: Detected' in output:
         pytest.fail('No SPI device available')
 
@@ -119,37 +119,35 @@ def spi_pre_commands(u_boot_console, freq):
         pytest.fail('Not recognized the SPI flash part name')
 
     m = re.search('page size (.+?) Bytes', output)
-    if m:
-        try:
-            page_size = int(m.group(1))
-        except ValueError:
-            pytest.fail('Not recognized the SPI page size')
+    assert m
+    try:
+        page_size = int(m.group(1))
+    except ValueError:
+        pytest.fail('Not recognized the SPI page size')
 
     m = re.search('erase size (.+?) KiB', output)
-    if m:
-        try:
-            erase_size = int(m.group(1))
-        except ValueError:
-            pytest.fail('Not recognized the SPI erase size')
-
+    assert m
+    try:
+        erase_size = int(m.group(1))
         erase_size *= 1024
+    except ValueError:
+        pytest.fail('Not recognized the SPI erase size')
 
     m = re.search('total (.+?) MiB', output)
-    if m:
-        try:
-            total_size = int(m.group(1))
-        except ValueError:
-            pytest.fail('Not recognized the SPI total size')
-
+    assert m
+    try:
+        total_size = int(m.group(1))
         total_size *= 1024 * 1024
+    except ValueError:
+        pytest.fail('Not recognized the SPI total size')
 
     m = re.search('Detected (.+?) with', output)
-    if m:
-        try:
-            flash_part = m.group(1)
-            assert flash_part == part_name
-        except ValueError:
-            pytest.fail('Not recognized the SPI flash part')
+    assert m
+    try:
+        flash_part = m.group(1)
+        assert flash_part == part_name
+    except ValueError:
+        pytest.fail('Not recognized the SPI flash part')
 
     global SPI_DATA
     SPI_DATA = {
@@ -180,27 +178,27 @@ def get_timeout():
     ''' Get the SPI timeout from spi data '''
     return SPI_DATA['timeout']
 
-def spi_erase_block(u_boot_console, erase_size, total_size):
+def spi_erase_block(ubman, erase_size, total_size):
     ''' Erase SPI flash memory block wise '''
     for start in range(0, total_size, erase_size):
-        output = u_boot_console.run_command(f'sf erase {hex(start)} {hex(erase_size)}')
+        output = ubman.run_command(f'sf erase {hex(start)} {hex(erase_size)}')
         assert EXPECTED_ERASE in output
 
 @pytest.mark.buildconfigspec('cmd_sf')
-def test_spi_erase_block(u_boot_console):
+def test_spi_erase_block(ubman):
     ''' Test case to check SPI erase functionality by erasing memory regions
     block-wise '''
 
-    min_f, max_f, loop = spi_find_freq_range(u_boot_console)
+    min_f, max_f, loop = spi_find_freq_range(ubman)
     i = 0
     while i < loop:
-        spi_pre_commands(u_boot_console, random.randint(min_f, max_f))
-        spi_erase_block(u_boot_console, get_erase_size(), get_total_size())
+        spi_pre_commands(ubman, random.randint(min_f, max_f))
+        spi_erase_block(ubman, get_erase_size(), get_total_size())
         i = i + 1
 
-def spi_write_twice(u_boot_console, page_size, erase_size, total_size, timeout):
+def spi_write_twice(ubman, page_size, erase_size, total_size, timeout):
     ''' Random write till page size, random till size and full size '''
-    addr = u_boot_utils.find_ram_base(u_boot_console)
+    addr = utils.find_ram_base(ubman)
 
     old_size = 0
     for size in (
@@ -212,7 +210,7 @@ def spi_write_twice(u_boot_console, page_size, erase_size, total_size, timeout):
         offset = offset & ~3
         size = size & ~3
         size = size - old_size
-        output = u_boot_console.run_command(f'crc32 {hex(addr + total_size)} {hex(size)}')
+        output = ubman.run_command(f'crc32 {hex(addr + total_size)} {hex(size)}')
         m = re.search('==> (.+?)$', output)
         if not m:
             pytest.fail('CRC32 failed')
@@ -230,23 +228,23 @@ def spi_write_twice(u_boot_console, page_size, erase_size, total_size, timeout):
         eraseoffset *= erase_size
 
         timeout = 100000000
-        with u_boot_console.temporary_timeout(timeout):
-            output = u_boot_console.run_command(
+        with ubman.temporary_timeout(timeout):
+            output = ubman.run_command(
                 f'sf erase {hex(eraseoffset)} {hex(erasesize)}'
             )
             assert EXPECTED_ERASE in output
 
-        with u_boot_console.temporary_timeout(timeout):
-            output = u_boot_console.run_command(
+        with ubman.temporary_timeout(timeout):
+            output = ubman.run_command(
                 f'sf write {hex(addr + total_size)} {hex(old_size)} {hex(size)}'
             )
             assert EXPECTED_WRITE in output
-        with u_boot_console.temporary_timeout(timeout):
-            output = u_boot_console.run_command(
+        with ubman.temporary_timeout(timeout):
+            output = ubman.run_command(
                 f'sf read {hex(addr + total_size + offset)} {hex(old_size)} {hex(size)}'
             )
             assert EXPECTED_READ in output
-        output = u_boot_console.run_command(
+        output = ubman.run_command(
             f'crc32 {hex(addr + total_size + offset)} {hex(size)}'
         )
         assert expected_crc32 in output
@@ -255,14 +253,14 @@ def spi_write_twice(u_boot_console, page_size, erase_size, total_size, timeout):
 @pytest.mark.buildconfigspec('cmd_bdi')
 @pytest.mark.buildconfigspec('cmd_sf')
 @pytest.mark.buildconfigspec('cmd_memory')
-def test_spi_write_twice(u_boot_console):
+def test_spi_write_twice(ubman):
     ''' Test to write data with random size twice for SPI '''
-    min_f, max_f, loop = spi_find_freq_range(u_boot_console)
+    min_f, max_f, loop = spi_find_freq_range(ubman)
     i = 0
     while i < loop:
-        spi_pre_commands(u_boot_console, random.randint(min_f, max_f))
+        spi_pre_commands(ubman, random.randint(min_f, max_f))
         spi_write_twice(
-            u_boot_console,
+            ubman,
             get_page_size(),
             get_erase_size(),
             get_total_size(),
@@ -270,12 +268,12 @@ def test_spi_write_twice(u_boot_console):
         )
         i = i + 1
 
-def spi_write_continues(u_boot_console, page_size, erase_size, total_size, timeout):
+def spi_write_continues(ubman, page_size, erase_size, total_size, timeout):
     ''' Write with random size of data to continue SPI write case '''
-    spi_erase_block(u_boot_console, erase_size, total_size)
-    addr = u_boot_utils.find_ram_base(u_boot_console)
+    spi_erase_block(ubman, erase_size, total_size)
+    addr = utils.find_ram_base(ubman)
 
-    output = u_boot_console.run_command(f'crc32 {hex(addr + 0x10000)} {hex(total_size)}')
+    output = ubman.run_command(f'crc32 {hex(addr + 0x10000)} {hex(total_size)}')
     m = re.search('==> (.+?)$', output)
     if not m:
         pytest.fail('CRC32 failed')
@@ -289,20 +287,20 @@ def spi_write_continues(u_boot_console, page_size, erase_size, total_size, timeo
     ):
         size = size & ~3
         size = size - old_size
-        with u_boot_console.temporary_timeout(timeout):
-            output = u_boot_console.run_command(
+        with ubman.temporary_timeout(timeout):
+            output = ubman.run_command(
                 f'sf write {hex(addr + 0x10000 + old_size)} {hex(old_size)} {hex(size)}'
             )
             assert EXPECTED_WRITE in output
         old_size += size
 
-    with u_boot_console.temporary_timeout(timeout):
-        output = u_boot_console.run_command(
+    with ubman.temporary_timeout(timeout):
+        output = ubman.run_command(
             f'sf read {hex(addr + 0x10000 + total_size)} 0 {hex(total_size)}'
         )
         assert EXPECTED_READ in output
 
-    output = u_boot_console.run_command(
+    output = ubman.run_command(
         f'crc32 {hex(addr + 0x10000 + total_size)} {hex(total_size)}'
     )
     assert expected_crc32 in output
@@ -310,14 +308,14 @@ def spi_write_continues(u_boot_console, page_size, erase_size, total_size, timeo
 @pytest.mark.buildconfigspec('cmd_bdi')
 @pytest.mark.buildconfigspec('cmd_sf')
 @pytest.mark.buildconfigspec('cmd_memory')
-def test_spi_write_continues(u_boot_console):
+def test_spi_write_continues(ubman):
     ''' Test to write more random size data for SPI '''
-    min_f, max_f, loop = spi_find_freq_range(u_boot_console)
+    min_f, max_f, loop = spi_find_freq_range(ubman)
     i = 0
     while i < loop:
-        spi_pre_commands(u_boot_console, random.randint(min_f, max_f))
+        spi_pre_commands(ubman, random.randint(min_f, max_f))
         spi_write_twice(
-            u_boot_console,
+            ubman,
             get_page_size(),
             get_erase_size(),
             get_total_size(),
@@ -325,28 +323,28 @@ def test_spi_write_continues(u_boot_console):
         )
         i = i + 1
 
-def spi_read_twice(u_boot_console, page_size, total_size, timeout):
+def spi_read_twice(ubman, page_size, total_size, timeout):
     ''' Read the whole SPI flash twice, random_size till full flash size,
     random till page size '''
     for size in random.randint(4, page_size), random.randint(4, total_size), total_size:
-        addr = u_boot_utils.find_ram_base(u_boot_console)
+        addr = utils.find_ram_base(ubman)
         size = size & ~3
-        with u_boot_console.temporary_timeout(timeout):
-            output = u_boot_console.run_command(
+        with ubman.temporary_timeout(timeout):
+            output = ubman.run_command(
                 f'sf read {hex(addr + total_size)} 0 {hex(size)}'
             )
             assert EXPECTED_READ in output
-        output = u_boot_console.run_command(f'crc32 {hex(addr + total_size)} {hex(size)}')
+        output = ubman.run_command(f'crc32 {hex(addr + total_size)} {hex(size)}')
         m = re.search('==> (.+?)$', output)
         if not m:
             pytest.fail('CRC32 failed')
         expected_crc32 = m.group(1)
-        with u_boot_console.temporary_timeout(timeout):
-            output = u_boot_console.run_command(
+        with ubman.temporary_timeout(timeout):
+            output = ubman.run_command(
                 f'sf read {hex(addr + total_size + 10)} 0 {hex(size)}'
             )
             assert EXPECTED_READ in output
-        output = u_boot_console.run_command(
+        output = ubman.run_command(
             f'crc32 {hex(addr + total_size + 10)} {hex(size)}'
         )
         assert expected_crc32 in output
@@ -354,49 +352,49 @@ def spi_read_twice(u_boot_console, page_size, total_size, timeout):
 @pytest.mark.buildconfigspec('cmd_sf')
 @pytest.mark.buildconfigspec('cmd_bdi')
 @pytest.mark.buildconfigspec('cmd_memory')
-def test_spi_read_twice(u_boot_console):
+def test_spi_read_twice(ubman):
     ''' Test to read random data twice from SPI '''
-    min_f, max_f, loop = spi_find_freq_range(u_boot_console)
+    min_f, max_f, loop = spi_find_freq_range(ubman)
     i = 0
     while i < loop:
-        spi_pre_commands(u_boot_console, random.randint(min_f, max_f))
-        spi_read_twice(u_boot_console, get_page_size(), get_total_size(), get_timeout())
+        spi_pre_commands(ubman, random.randint(min_f, max_f))
+        spi_read_twice(ubman, get_page_size(), get_total_size(), get_timeout())
         i = i + 1
 
-def spi_erase_all(u_boot_console, total_size, timeout):
+def spi_erase_all(ubman, total_size, timeout):
     ''' Erase the full chip SPI '''
     start = 0
-    with u_boot_console.temporary_timeout(timeout):
-        output = u_boot_console.run_command(f'sf erase {start} {hex(total_size)}')
+    with ubman.temporary_timeout(timeout):
+        output = ubman.run_command(f'sf erase {start} {hex(total_size)}')
         assert EXPECTED_ERASE in output
 
 @pytest.mark.buildconfigspec('cmd_sf')
-def test_spi_erase_all(u_boot_console):
+def test_spi_erase_all(ubman):
     ''' Test to check full chip erase for SPI '''
-    min_f, max_f, loop = spi_find_freq_range(u_boot_console)
+    min_f, max_f, loop = spi_find_freq_range(ubman)
     i = 0
     while i < loop:
-        spi_pre_commands(u_boot_console, random.randint(min_f, max_f))
-        spi_erase_all(u_boot_console, get_total_size(), get_timeout())
+        spi_pre_commands(ubman, random.randint(min_f, max_f))
+        spi_erase_all(ubman, get_total_size(), get_timeout())
         i = i + 1
 
 def flash_ops(
-    u_boot_console, ops, start, size, offset=0, exp_ret=0, exp_str='', not_exp_str=''
+    ubman, ops, start, size, offset=0, exp_ret=0, exp_str='', not_exp_str=''
 ):
     ''' Flash operations: erase, write and read '''
 
-    f = u_boot_console.config.env.get('env__spi_device_test', None)
+    f = ubman.config.env.get('env__spi_device_test', None)
     if not f:
         timeout = 1000000
 
     timeout = f.get('timeout', 1000000)
 
     if ops == 'erase':
-        with u_boot_console.temporary_timeout(timeout):
-            output = u_boot_console.run_command(f'sf erase {hex(start)} {hex(size)}')
+        with ubman.temporary_timeout(timeout):
+            output = ubman.run_command(f'sf erase {hex(start)} {hex(size)}')
     else:
-        with u_boot_console.temporary_timeout(timeout):
-            output = u_boot_console.run_command(
+        with ubman.temporary_timeout(timeout):
+            output = ubman.run_command(
                 f'sf {ops} {hex(offset)} {hex(start)} {hex(size)}'
             )
 
@@ -405,15 +403,15 @@ def flash_ops(
     if not_exp_str:
         assert not_exp_str not in output
 
-    ret_code = u_boot_console.run_command('echo $?')
+    ret_code = ubman.run_command('echo $?')
     if exp_ret >= 0:
         assert ret_code.endswith(str(exp_ret))
 
     return output, ret_code
 
-def spi_unlock_exit(u_boot_console, addr, size):
+def spi_unlock_exit(ubman, addr, size):
     ''' Unlock the flash before making it fail '''
-    u_boot_console.run_command(f'sf protect unlock {hex(addr)} {hex(size)}')
+    ubman.run_command(f'sf protect unlock {hex(addr)} {hex(size)}')
     assert False, 'FAIL: Flash lock is unable to protect the data!'
 
 def find_prot_region(lock_addr, lock_size):
@@ -442,49 +440,49 @@ def find_prot_region(lock_addr, lock_size):
 
     return prot_start, prot_size, unprot_start, unprot_size
 
-def protect_ops(u_boot_console, lock_addr, lock_size, ops="unlock"):
+def protect_ops(ubman, lock_addr, lock_size, ops="unlock"):
     ''' Run the command to lock or Unlock the flash '''
-    u_boot_console.run_command(f'sf protect {ops} {hex(lock_addr)} {hex(lock_size)}')
-    output = u_boot_console.run_command('echo $?')
+    ubman.run_command(f'sf protect {ops} {hex(lock_addr)} {hex(lock_size)}')
+    output = ubman.run_command('echo $?')
     if ops == "lock" and not output.endswith('0'):
-        u_boot_console.run_command(f'sf protect unlock {hex(lock_addr)} {hex(lock_size)}')
+        ubman.run_command(f'sf protect unlock {hex(lock_addr)} {hex(lock_size)}')
         assert False, "sf protect lock command exits with non-zero return code"
     assert output.endswith('0')
 
-def erase_write_ops(u_boot_console, start, size):
+def erase_write_ops(ubman, start, size):
     ''' Basic erase and write operation for flash '''
-    addr = u_boot_utils.find_ram_base(u_boot_console)
-    flash_ops(u_boot_console, 'erase', start, size, 0, 0, EXPECTED_ERASE)
-    flash_ops(u_boot_console, 'write', start, size, addr, 0, EXPECTED_WRITE)
+    addr = utils.find_ram_base(ubman)
+    flash_ops(ubman, 'erase', start, size, 0, 0, EXPECTED_ERASE)
+    flash_ops(ubman, 'write', start, size, addr, 0, EXPECTED_WRITE)
 
-def spi_lock_unlock(u_boot_console, lock_addr, lock_size):
+def spi_lock_unlock(ubman, lock_addr, lock_size):
     ''' Lock unlock operations for SPI family flash '''
-    addr = u_boot_utils.find_ram_base(u_boot_console)
+    addr = utils.find_ram_base(ubman)
     erase_size = get_erase_size()
 
     # Find the protected/un-protected region
     prot_start, prot_size, unprot_start, unprot_size = find_prot_region(lock_addr, lock_size)
 
     # Check erase/write operation before locking
-    erase_write_ops(u_boot_console, prot_start, prot_size)
+    erase_write_ops(ubman, prot_start, prot_size)
 
     # Locking the flash
-    protect_ops(u_boot_console, lock_addr, lock_size, 'lock')
+    protect_ops(ubman, lock_addr, lock_size, 'lock')
 
     # Check erase/write operation after locking
-    output, ret_code = flash_ops(u_boot_console, 'erase', prot_start, prot_size, 0, -1)
+    output, ret_code = flash_ops(ubman, 'erase', prot_start, prot_size, 0, -1)
     if not any(error in output for error in EXPECTED_ERASE_ERRORS) or ret_code.endswith(
         '0'
     ):
-        spi_unlock_exit(u_boot_console, lock_addr, lock_size)
+        spi_unlock_exit(ubman, lock_addr, lock_size)
 
     output, ret_code = flash_ops(
-        u_boot_console, 'write', prot_start, prot_size, addr, -1
+        ubman, 'write', prot_start, prot_size, addr, -1
     )
     if not any(error in output for error in EXPECTED_WRITE_ERRORS) or ret_code.endswith(
         '0'
     ):
-        spi_unlock_exit(u_boot_console, lock_addr, lock_size)
+        spi_unlock_exit(ubman, lock_addr, lock_size)
 
     # Check locked sectors
     sect_lock_start = random.randrange(prot_start, (prot_start + prot_size), erase_size)
@@ -497,20 +495,20 @@ def spi_lock_unlock(u_boot_console, lock_addr, lock_size):
     sect_write_size = random.randint(1, sect_lock_size)
 
     output, ret_code = flash_ops(
-        u_boot_console, 'erase', sect_lock_start, sect_lock_size, 0, -1
+        ubman, 'erase', sect_lock_start, sect_lock_size, 0, -1
     )
     if not any(error in output for error in EXPECTED_ERASE_ERRORS) or ret_code.endswith(
         '0'
     ):
-        spi_unlock_exit(u_boot_console, lock_addr, lock_size)
+        spi_unlock_exit(ubman, lock_addr, lock_size)
 
     output, ret_code = flash_ops(
-        u_boot_console, 'write', sect_lock_start, sect_write_size, addr, -1
+        ubman, 'write', sect_lock_start, sect_write_size, addr, -1
     )
     if not any(error in output for error in EXPECTED_WRITE_ERRORS) or ret_code.endswith(
         '0'
     ):
-        spi_unlock_exit(u_boot_console, lock_addr, lock_size)
+        spi_unlock_exit(ubman, lock_addr, lock_size)
 
     # Check unlocked sectors
     if unprot_size != 0:
@@ -526,22 +524,22 @@ def spi_lock_unlock(u_boot_console, lock_addr, lock_size):
         sect_write_size = random.randint(1, sect_unlock_size)
 
         output, ret_code = flash_ops(
-            u_boot_console, 'erase', sect_unlock_start, sect_unlock_size, 0, -1
+            ubman, 'erase', sect_unlock_start, sect_unlock_size, 0, -1
         )
         if EXPECTED_ERASE not in output or ret_code.endswith('1'):
-            spi_unlock_exit(u_boot_console, lock_addr, lock_size)
+            spi_unlock_exit(ubman, lock_addr, lock_size)
 
         output, ret_code = flash_ops(
-            u_boot_console, 'write', sect_unlock_start, sect_write_size, addr, -1
+            ubman, 'write', sect_unlock_start, sect_write_size, addr, -1
         )
         if EXPECTED_WRITE not in output or ret_code.endswith('1'):
-            spi_unlock_exit(u_boot_console, lock_addr, lock_size)
+            spi_unlock_exit(ubman, lock_addr, lock_size)
 
     # Unlocking the flash
-    protect_ops(u_boot_console, lock_addr, lock_size, 'unlock')
+    protect_ops(ubman, lock_addr, lock_size, 'unlock')
 
     # Check erase/write operation after un-locking
-    erase_write_ops(u_boot_console, prot_start, prot_size)
+    erase_write_ops(ubman, prot_start, prot_size)
 
     # Check previous locked sectors
     sect_lock_start = random.randrange(prot_start, (prot_start + prot_size), erase_size)
@@ -554,10 +552,10 @@ def spi_lock_unlock(u_boot_console, lock_addr, lock_size):
     sect_write_size = random.randint(1, sect_lock_size)
 
     flash_ops(
-        u_boot_console, 'erase', sect_lock_start, sect_lock_size, 0, 0, EXPECTED_ERASE
+        ubman, 'erase', sect_lock_start, sect_lock_size, 0, 0, EXPECTED_ERASE
     )
     flash_ops(
-        u_boot_console,
+        ubman,
         'write',
         sect_lock_start,
         sect_write_size,
@@ -569,16 +567,16 @@ def spi_lock_unlock(u_boot_console, lock_addr, lock_size):
 @pytest.mark.buildconfigspec('cmd_bdi')
 @pytest.mark.buildconfigspec('cmd_sf')
 @pytest.mark.buildconfigspec('cmd_memory')
-def test_spi_lock_unlock(u_boot_console):
+def test_spi_lock_unlock(ubman):
     ''' Test to check the lock-unlock functionality for SPI family flash '''
-    min_f, max_f, loop = spi_find_freq_range(u_boot_console)
-    flashes = u_boot_console.config.env.get('env__spi_lock_unlock', False)
+    min_f, max_f, loop = spi_find_freq_range(ubman)
+    flashes = ubman.config.env.get('env__spi_lock_unlock', False)
     if not flashes:
         pytest.skip('No SPI test device configured for lock/unlock')
 
     i = 0
     while i < loop:
-        spi_pre_commands(u_boot_console, random.randint(min_f, max_f))
+        spi_pre_commands(ubman, random.randint(min_f, max_f))
         total_size = get_total_size()
         flash_part = get_flash_part()
 
@@ -590,31 +588,31 @@ def test_spi_lock_unlock(u_boot_console):
         # For lower half of memory
         lock_addr = random.randint(0, (total_size // 2) - 1)
         lock_size = random.randint(1, ((total_size // 2) - lock_addr))
-        spi_lock_unlock(u_boot_console, lock_addr, lock_size)
+        spi_lock_unlock(ubman, lock_addr, lock_size)
 
         # For upper half of memory
         lock_addr = random.randint((total_size // 2), total_size - 1)
         lock_size = random.randint(1, (total_size - lock_addr))
-        spi_lock_unlock(u_boot_console, lock_addr, lock_size)
+        spi_lock_unlock(ubman, lock_addr, lock_size)
 
         # For entire flash
         lock_addr = random.randint(0, total_size - 1)
         lock_size = random.randint(1, (total_size - lock_addr))
-        spi_lock_unlock(u_boot_console, lock_addr, lock_size)
+        spi_lock_unlock(ubman, lock_addr, lock_size)
 
         i = i + 1
 
 @pytest.mark.buildconfigspec('cmd_bdi')
 @pytest.mark.buildconfigspec('cmd_sf')
 @pytest.mark.buildconfigspec('cmd_memory')
-def test_spi_negative(u_boot_console):
+def test_spi_negative(ubman):
     ''' Negative tests for SPI '''
-    min_f, max_f, loop = spi_find_freq_range(u_boot_console)
-    spi_pre_commands(u_boot_console, random.randint(min_f, max_f))
+    min_f, max_f, loop = spi_find_freq_range(ubman)
+    spi_pre_commands(ubman, random.randint(min_f, max_f))
     total_size = get_total_size()
     erase_size = get_erase_size()
     page_size = get_page_size()
-    addr = u_boot_utils.find_ram_base(u_boot_console)
+    addr = utils.find_ram_base(ubman)
     i = 0
     while i < loop:
         # Erase negative test
@@ -627,28 +625,28 @@ def test_spi_negative(u_boot_console):
 
         error_msg = 'Erased: ERROR'
         flash_ops(
-            u_boot_console, 'erase', start, esize, 0, 1, error_msg, EXPECTED_ERASE
+            ubman, 'erase', start, esize, 0, 1, error_msg, EXPECTED_ERASE
         )
 
         # If eraseoffset exceeds beyond flash size
         eoffset = random.randint(total_size, (total_size + int(0x1000000)))
         error_msg = 'Offset exceeds device limit'
         flash_ops(
-            u_boot_console, 'erase', eoffset, esize, 0, 1, error_msg, EXPECTED_ERASE
+            ubman, 'erase', eoffset, esize, 0, 1, error_msg, EXPECTED_ERASE
         )
 
         # If erasesize exceeds beyond flash size
         esize = random.randint((total_size - start), (total_size + int(0x1000000)))
         error_msg = 'ERROR: attempting erase past flash size'
         flash_ops(
-            u_boot_console, 'erase', start, esize, 0, 1, error_msg, EXPECTED_ERASE
+            ubman, 'erase', start, esize, 0, 1, error_msg, EXPECTED_ERASE
         )
 
         # If erase size is 0
         esize = 0
         error_msg = None
         flash_ops(
-            u_boot_console, 'erase', start, esize, 0, 1, error_msg, EXPECTED_ERASE
+            ubman, 'erase', start, esize, 0, 1, error_msg, EXPECTED_ERASE
         )
 
         # If erasesize is less than flash's page size
@@ -656,7 +654,7 @@ def test_spi_negative(u_boot_console):
         start = random.randint(0, (total_size - page_size))
         error_msg = 'Erased: ERROR'
         flash_ops(
-            u_boot_console, 'erase', start, esize, 0, 1, error_msg, EXPECTED_ERASE
+            ubman, 'erase', start, esize, 0, 1, error_msg, EXPECTED_ERASE
         )
 
         # Write/Read negative test
@@ -665,10 +663,10 @@ def test_spi_negative(u_boot_console):
         size = random.randint((total_size - offset), (total_size + int(0x1000000)))
         error_msg = 'Size exceeds partition or device limit'
         flash_ops(
-            u_boot_console, 'write', offset, size, addr, 1, error_msg, EXPECTED_WRITE
+            ubman, 'write', offset, size, addr, 1, error_msg, EXPECTED_WRITE
         )
         flash_ops(
-            u_boot_console, 'read', offset, size, addr, 1, error_msg, EXPECTED_READ
+            ubman, 'read', offset, size, addr, 1, error_msg, EXPECTED_READ
         )
 
         # if Write/Read offset exceeds beyond flash size
@@ -676,10 +674,10 @@ def test_spi_negative(u_boot_console):
         size = random.randint(0, total_size)
         error_msg = 'Offset exceeds device limit'
         flash_ops(
-            u_boot_console, 'write', offset, size, addr, 1, error_msg, EXPECTED_WRITE
+            ubman, 'write', offset, size, addr, 1, error_msg, EXPECTED_WRITE
         )
         flash_ops(
-            u_boot_console, 'read', offset, size, addr, 1, error_msg, EXPECTED_READ
+            ubman, 'read', offset, size, addr, 1, error_msg, EXPECTED_READ
         )
 
         # if Write/Read size is 0
@@ -687,14 +685,14 @@ def test_spi_negative(u_boot_console):
         size = 0
         error_msg = None
         flash_ops(
-            u_boot_console, 'write', offset, size, addr, 1, error_msg, EXPECTED_WRITE
+            ubman, 'write', offset, size, addr, 1, error_msg, EXPECTED_WRITE
         )
         flash_ops(
-            u_boot_console, 'read', offset, size, addr, 1, error_msg, EXPECTED_READ
+            ubman, 'read', offset, size, addr, 1, error_msg, EXPECTED_READ
         )
 
         # Read to relocation address
-        output = u_boot_console.run_command('bdinfo')
+        output = ubman.run_command('bdinfo')
         m = re.search(r'relocaddr\s*= (.+)', output)
         res_area = int(m.group(1), 16)
 
@@ -702,7 +700,7 @@ def test_spi_negative(u_boot_console):
         size = 0x2000
         error_msg = 'ERROR: trying to overwrite reserved memory'
         flash_ops(
-            u_boot_console, 'read', start, size, res_area, 1, error_msg, EXPECTED_READ
+            ubman, 'read', start, size, res_area, 1, error_msg, EXPECTED_READ
         )
 
         i = i + 1
diff --git a/test/py/tests/test_spl.py b/test/py/tests/test_spl.py
index 474f430a344..48407399039 100644
--- a/test/py/tests/test_spl.py
+++ b/test/py/tests/test_spl.py
@@ -6,16 +6,16 @@ import os.path
 import pytest
 
 @pytest.mark.buildconfigspec('spl_unit_test')
-def test_ut_spl_init(u_boot_console):
+def test_ut_spl_init(ubman):
     """Initialize data for ut spl tests."""
 
-    fn = u_boot_console.config.source_dir + '/spi.bin'
+    fn = ubman.config.source_dir + '/spi.bin'
     if not os.path.exists(fn):
         data = b'\x00' * (2 * 1024 * 1024)
         with open(fn, 'wb') as fh:
             fh.write(data)
 
-def test_spl(u_boot_console, ut_spl_subtest):
+def test_spl(ubman, ut_spl_subtest):
     """Execute a "ut" subtest.
 
     The subtests are collected in function generate_ut_subtest() from linker
@@ -29,16 +29,15 @@ def test_spl(u_boot_console, ut_spl_subtest):
     implemented in C function foo_test_bar().
 
     Args:
-        u_boot_console (ConsoleBase): U-Boot console
+        ubman (ConsoleBase): U-Boot console
         ut_subtest (str): SPL test to be executed (e.g. 'dm platdata_phandle')
     """
     try:
-        cons = u_boot_console
-        cons.restart_uboot_with_flags(['-u', '-k', ut_spl_subtest.split()[1]])
-        output = cons.get_spawn_output().replace('\r', '')
+        ubman.restart_uboot_with_flags(['-u', '-k', ut_spl_subtest.split()[1]])
+        output = ubman.get_spawn_output().replace('\r', '')
         assert 'failures: 0' in output
     finally:
         # Restart afterward in case a non-SPL test is run next. This should not
         # happen since SPL tests are run in their own invocation of test.py, but
         # the cost of doing this is not too great at present.
-        u_boot_console.restart_uboot()
+        ubman.restart_uboot()
diff --git a/test/py/tests/test_stackprotector.py b/test/py/tests/test_stackprotector.py
index b87392c54ff..a7e20d6307c 100644
--- a/test/py/tests/test_stackprotector.py
+++ b/test/py/tests/test_stackprotector.py
@@ -6,10 +6,10 @@ import signal
 
 @pytest.mark.buildconfigspec('cmd_stackprotector_test')
 @pytest.mark.notbuildconfigspec('asan')
-def test_stackprotector(u_boot_console):
+def test_stackprotector(ubman):
     """Test that the stackprotector function works."""
 
-    u_boot_console.run_command('stackprot_test',wait_for_prompt=False)
+    ubman.run_command('stackprot_test',wait_for_prompt=False)
     expected_response = 'Stack smashing detected'
-    u_boot_console.wait_for(expected_response)
-    u_boot_console.restart_uboot()
+    ubman.wait_for(expected_response)
+    ubman.restart_uboot()
diff --git a/test/py/tests/test_suite.py b/test/py/tests/test_suite.py
index 73c185349b4..7fe9a90dfd3 100644
--- a/test/py/tests/test_suite.py
+++ b/test/py/tests/test_suite.py
@@ -7,10 +7,10 @@ import re
 # List of test suites we expect to find with 'ut info' and 'ut all'
 EXPECTED_SUITES = [
     'addrmap', 'bdinfo', 'bloblist', 'bootm', 'bootstd',
-    'cmd', 'common', 'dm', 'env', 'exit',
+    'cmd', 'common', 'dm', 'env', 'exit', 'fdt_overlay',
     'fdt', 'font', 'hush', 'lib',
     'loadm', 'log', 'mbr', 'measurement', 'mem',
-    'overlay', 'pci_mps', 'setexpr', 'upl',
+    'pci_mps', 'setexpr', 'upl',
     ]
 
 
@@ -18,11 +18,11 @@ EXPECTED_SUITES = [
 DEBUG_ME = False
 
 
-def collect_info(cons, output):
+def collect_info(ubman, output):
     """Process the output from 'ut all'
 
     Args:
-        cons: U-Boot console object
+        ubman: U-Boot console object
         output: Output from running 'ut all'
 
     Returns:
@@ -45,15 +45,15 @@ def collect_info(cons, output):
     for line in output.splitlines():
         line = line.rstrip()
         if DEBUG_ME:
-            cons.log.info(f'line: {line}')
+            ubman.log.info(f'line: {line}')
         m = re.search('----Running ([^ ]*) tests----', line)
         if m:
             if DEBUG_ME and cur_suite and cur_suite != 'info':
-                cons.log.info(f'suite: {cur_suite} expected {exp_test_count[cur_suite]} found {test_count}')
+                ubman.log.info(f'suite: {cur_suite} expected {exp_test_count[cur_suite]} found {test_count}')
 
             cur_suite = m.group(1)
             if DEBUG_ME:
-                cons.log.info(f'cur_suite: {cur_suite}')
+                ubman.log.info(f'cur_suite: {cur_suite}')
             suites.add(cur_suite)
 
             test_count = 0
@@ -65,18 +65,19 @@ def collect_info(cons, output):
             test_name = m.group(1)
             msg = m.group(3)
             if DEBUG_ME:
-                cons.log.info(f"test_name {test_name} msg '{msg}'")
-            if msg == ' (flat tree)' and test_name not in tests:
-                tests.add(test_name)
+                ubman.log.info(f"test_name {test_name} msg '{msg}'")
+            full_name = f'{cur_suite}.{test_name}'
+            if msg == ' (flat tree)' and full_name not in tests:
+                tests.add(full_name)
                 test_count += 1
             if not msg or 'skipped as it is manual' in msg:
-                tests.add(test_name)
+                tests.add(full_name)
                 test_count += 1
         if DEBUG_ME:
-            cons.log.info(f'test_count {test_count}')
+            ubman.log.info(f'test_count {test_count}')
     if DEBUG_ME:
-        cons.log.info(f'suite: {cur_suite} expected {exp_test_count[cur_suite]} found {test_count}')
-        cons.log.info(f"Tests: {' '.join(sorted(list(tests)))}")
+        ubman.log.info(f'suite: {cur_suite} expected {exp_test_count[cur_suite]} found {test_count}')
+        ubman.log.info(f"Tests: {' '.join(sorted(list(tests)))}")
 
     # Figure out what is missing, or extra
     missing = set()
@@ -90,11 +91,11 @@ def collect_info(cons, output):
     return suites, tests, exp_test_count, missing, extra
 
 
-def process_ut_info(cons, output):
+def process_ut_info(ubman, output):
     """Process the output of the 'ut info' command
 
     Args:
-        cons: U-Boot console object
+        ubman: U-Boot console object
         output: Output from running 'ut all'
 
     Returns:
@@ -112,7 +113,7 @@ def process_ut_info(cons, output):
     for line in output.splitlines():
         line = line.rstrip()
         if DEBUG_ME:
-            cons.log.info(f'line: {line}')
+            ubman.log.info(f'line: {line}')
         m = re.match(r'Test suites: (.*)', line)
         if m:
             suite_count = int(m.group(1))
@@ -129,60 +130,78 @@ def process_ut_info(cons, output):
 @pytest.mark.notbuildconfigspec('sandbox_spl')
 @pytest.mark.notbuildconfigspec('sandbox64')
 # This test is disabled since it fails; remove the leading 'x' to try it
-def xtest_suite(u_boot_console, u_boot_config):
+def xtest_suite(ubman, u_boot_config):
     """Perform various checks on the unit tests, including:
 
        - The number of suites matches that reported by the 'ut info'
        - Where available, the number of tests is each suite matches that
-         reported by 'ut info -s'
+         reported by 'ut -s info'
        - The total number of tests adds up to the total that are actually run
          with 'ut all'
        - All suites are run with 'ut all'
        - The expected set of suites is run (the list is hard-coded in this test)
 
     """
-    cons = u_boot_console
     buildconfig = u_boot_config.buildconfig
-    with cons.log.section('Run all unit tests'):
+    with ubman.log.section('Run all unit tests'):
         # ut hush hush_test_simple_dollar prints "Unknown command" on purpose.
-        with u_boot_console.disable_check('unknown_command'):
-            output = cons.run_command('ut all')
+        with ubman.disable_check('unknown_command'):
+            output = ubman.run_command('ut all')
 
     # Process the output from the run
-    with cons.log.section('Check output'):
-        suites, all_tests, exp_test_count, missing, extra = collect_info(cons,
+    with ubman.log.section('Check output'):
+        suites, all_tests, exp_test_count, missing, extra = collect_info(ubman,
                                                                          output)
-    cons.log.info(f'missing {missing}')
-    cons.log.info(f'extra {extra}')
+    ubman.log.info(f'missing {missing}')
+    ubman.log.info(f'extra {extra}')
 
     # Make sure we got a test count for each suite
     assert not (suites - exp_test_count.keys())
 
     # Deal with missing suites
-    with cons.log.section('Check missing suites'):
+    with ubman.log.section('Check missing suites'):
         if 'config_cmd_seama' not in buildconfig:
-            cons.log.info("CMD_SEAMA not enabled: Ignoring suite 'seama'")
+            ubman.log.info("CMD_SEAMA not enabled: Ignoring suite 'seama'")
             missing.discard('seama')
 
     # Run 'ut info' and compare with the log results
-    with cons.log.section('Check suite test-counts'):
-        output = cons.run_command('ut info -s')
+    with ubman.log.section('Check suite test-counts'):
+        output = ubman.run_command('ut -s info')
 
-        suite_count, total_test_count, test_count = process_ut_info(cons,
+        suite_count, total_test_count, test_count = process_ut_info(ubman,
                                                                     output)
 
         if missing or extra:
-            cons.log.info(f"suites: {' '.join(sorted(list(suites)))}")
-            cons.log.error(f'missing: {sorted(list(missing))}')
-            cons.log.error(f'extra: {sorted(list(extra))}')
+            ubman.log.info(f"suites: {' '.join(sorted(list(suites)))}")
+            ubman.log.error(f'missing: {sorted(list(missing))}')
+            ubman.log.error(f'extra: {sorted(list(extra))}')
 
         assert not missing, f'Missing suites {missing}'
         assert not extra, f'Extra suites {extra}'
 
-        cons.log.info(str(exp_test_count))
+        ubman.log.info(str(exp_test_count))
         for suite in EXPECTED_SUITES:
             assert test_count[suite] in ['?', str(exp_test_count[suite])], \
                 f'suite {suite} expected {exp_test_count[suite]}'
 
         assert suite_count == len(EXPECTED_SUITES)
         assert total_test_count == len(all_tests)
+
+    # Run three suites
+    with ubman.log.section('Check multiple suites'):
+        output = ubman.run_command('ut bloblist,setexpr,mem')
+        assert 'Suites run: 3' in output
+
+    # Run a particular test
+    with ubman.log.section('Check single test'):
+        output = ubman.run_command('ut bloblist reloc')
+        assert 'Test: reloc: bloblist.c' in output
+
+    # Run tests multiple times
+    with ubman.log.section('Check multiple runs'):
+        output = ubman.run_command('ut -r2 bloblist')
+        lines = output.splitlines()
+        run = len([line for line in lines if 'Test:' in line])
+        count = re.search(r'Tests run: (\d*)', lines[-1]).group(1)
+
+        assert run == 2 * int(count)
diff --git a/test/py/tests/test_tpm2.py b/test/py/tests/test_tpm2.py
index 75f5d31fc67..064651c3e23 100644
--- a/test/py/tests/test_tpm2.py
+++ b/test/py/tests/test_tpm2.py
@@ -4,7 +4,7 @@
 
 import os.path
 import pytest
-import u_boot_utils
+import utils
 import re
 import time
 
@@ -31,109 +31,109 @@ skipped.
 
 updates = 0
 
-def force_init(u_boot_console, force=False):
+def force_init(ubman, force=False):
     """When a test fails, U-Boot is reset. Because TPM stack must be initialized
     after each reboot, we must ensure these lines are always executed before
     trying any command or they will fail with no reason. Executing 'tpm init'
     twice will spawn an error used to detect that the TPM was not reset and no
     initialization code should be run.
     """
-    skip_test = u_boot_console.config.env.get('env__tpm_device_test_skip', False)
+    skip_test = ubman.config.env.get('env__tpm_device_test_skip', False)
     if skip_test:
         pytest.skip('skip TPM device test')
-    output = u_boot_console.run_command('tpm2 autostart')
+    output = ubman.run_command('tpm2 autostart')
     if force or not 'Error' in output:
-        u_boot_console.run_command('echo --- start of init ---')
-        u_boot_console.run_command('tpm2 clear TPM2_RH_LOCKOUT')
-        output = u_boot_console.run_command('echo $?')
+        ubman.run_command('echo --- start of init ---')
+        ubman.run_command('tpm2 clear TPM2_RH_LOCKOUT')
+        output = ubman.run_command('echo $?')
         if not output.endswith('0'):
-            u_boot_console.run_command('tpm2 clear TPM2_RH_PLATFORM')
-        u_boot_console.run_command('echo --- end of init ---')
+            ubman.run_command('tpm2 clear TPM2_RH_PLATFORM')
+        ubman.run_command('echo --- end of init ---')
 
-def is_sandbox(cons):
+def is_sandbox(ubman):
     # Array slice removes leading/trailing quotes.
-    sys_arch = cons.config.buildconfig.get('config_sys_arch', '"sandbox"')[1:-1]
+    sys_arch = ubman.config.buildconfig.get('config_sys_arch', '"sandbox"')[1:-1]
     return sys_arch == 'sandbox'
 
 @pytest.mark.buildconfigspec('cmd_tpm_v2')
-def test_tpm2_init(u_boot_console):
+def test_tpm2_init(ubman):
     """Init the software stack to use TPMv2 commands."""
-    skip_test = u_boot_console.config.env.get('env__tpm_device_test_skip', False)
+    skip_test = ubman.config.env.get('env__tpm_device_test_skip', False)
     if skip_test:
         pytest.skip('skip TPM device test')
-    u_boot_console.run_command('tpm2 autostart')
-    output = u_boot_console.run_command('echo $?')
+    ubman.run_command('tpm2 autostart')
+    output = ubman.run_command('echo $?')
     assert output.endswith('0')
 
 @pytest.mark.buildconfigspec('cmd_tpm_v2')
-def test_tpm2_startup(u_boot_console):
+def test_tpm2_startup(ubman):
     """Execute a TPM2_Startup command.
 
     Initiate the TPM internal state machine.
     """
-    skip_test = u_boot_console.config.env.get('env__tpm_device_test_skip', False)
+    skip_test = ubman.config.env.get('env__tpm_device_test_skip', False)
     if skip_test:
         pytest.skip('skip TPM device test')
-    u_boot_console.run_command('tpm2 startup TPM2_SU_CLEAR')
-    output = u_boot_console.run_command('echo $?')
+    ubman.run_command('tpm2 startup TPM2_SU_CLEAR')
+    output = ubman.run_command('echo $?')
     assert output.endswith('0')
 
-def tpm2_sandbox_init(u_boot_console):
+def tpm2_sandbox_init(ubman):
     """Put sandbox back into a known state so we can run a test
 
     This allows all tests to run in parallel, since no test depends on another.
     """
-    u_boot_console.restart_uboot()
-    u_boot_console.run_command('tpm2 autostart')
-    output = u_boot_console.run_command('echo $?')
+    ubman.restart_uboot()
+    ubman.run_command('tpm2 autostart')
+    output = ubman.run_command('echo $?')
     assert output.endswith('0')
 
-    skip_test = u_boot_console.config.env.get('env__tpm_device_test_skip', False)
+    skip_test = ubman.config.env.get('env__tpm_device_test_skip', False)
     if skip_test:
         pytest.skip('skip TPM device test')
 
 @pytest.mark.buildconfigspec('cmd_tpm_v2')
-def test_tpm2_sandbox_self_test_full(u_boot_console):
+def test_tpm2_sandbox_self_test_full(ubman):
     """Execute a TPM2_SelfTest (full) command.
 
     Ask the TPM to perform all self tests to also enable full capabilities.
     """
-    if is_sandbox(u_boot_console):
-        u_boot_console.restart_uboot()
-        u_boot_console.run_command('tpm2 autostart')
-        output = u_boot_console.run_command('echo $?')
+    if is_sandbox(ubman):
+        ubman.restart_uboot()
+        ubman.run_command('tpm2 autostart')
+        output = ubman.run_command('echo $?')
         assert output.endswith('0')
 
-        u_boot_console.run_command('tpm2 startup TPM2_SU_CLEAR')
-        output = u_boot_console.run_command('echo $?')
+        ubman.run_command('tpm2 startup TPM2_SU_CLEAR')
+        output = ubman.run_command('echo $?')
         assert output.endswith('0')
 
-    skip_test = u_boot_console.config.env.get('env__tpm_device_test_skip', False)
+    skip_test = ubman.config.env.get('env__tpm_device_test_skip', False)
     if skip_test:
         pytest.skip('skip TPM device test')
-    u_boot_console.run_command('tpm2 self_test full')
-    output = u_boot_console.run_command('echo $?')
+    ubman.run_command('tpm2 self_test full')
+    output = ubman.run_command('echo $?')
     assert output.endswith('0')
 
 @pytest.mark.buildconfigspec('cmd_tpm_v2')
-def test_tpm2_continue_self_test(u_boot_console):
+def test_tpm2_continue_self_test(ubman):
     """Execute a TPM2_SelfTest (continued) command.
 
     Ask the TPM to finish its self tests (alternative to the full test) in order
     to enter a fully operational state.
     """
 
-    skip_test = u_boot_console.config.env.get('env__tpm_device_test_skip', False)
+    skip_test = ubman.config.env.get('env__tpm_device_test_skip', False)
     if skip_test:
         pytest.skip('skip TPM device test')
-    if is_sandbox(u_boot_console):
-        tpm2_sandbox_init(u_boot_console)
-    u_boot_console.run_command('tpm2 self_test continue')
-    output = u_boot_console.run_command('echo $?')
+    if is_sandbox(ubman):
+        tpm2_sandbox_init(ubman)
+    ubman.run_command('tpm2 self_test continue')
+    output = ubman.run_command('echo $?')
     assert output.endswith('0')
 
 @pytest.mark.buildconfigspec('cmd_tpm_v2')
-def test_tpm2_clear(u_boot_console):
+def test_tpm2_clear(ubman):
     """Execute a TPM2_Clear command.
 
     Ask the TPM to reset entirely its internal state (including internal
@@ -144,22 +144,22 @@ def test_tpm2_clear(u_boot_console):
     not have a password set, otherwise this test will fail. ENDORSEMENT and
     PLATFORM hierarchies are also available.
     """
-    if is_sandbox(u_boot_console):
-        tpm2_sandbox_init(u_boot_console)
+    if is_sandbox(ubman):
+        tpm2_sandbox_init(ubman)
 
-    skip_test = u_boot_console.config.env.get('env__tpm_device_test_skip', False)
+    skip_test = ubman.config.env.get('env__tpm_device_test_skip', False)
     if skip_test:
         pytest.skip('skip TPM device test')
-    u_boot_console.run_command('tpm2 clear TPM2_RH_LOCKOUT')
-    output = u_boot_console.run_command('echo $?')
+    ubman.run_command('tpm2 clear TPM2_RH_LOCKOUT')
+    output = ubman.run_command('echo $?')
     assert output.endswith('0')
 
-    u_boot_console.run_command('tpm2 clear TPM2_RH_PLATFORM')
-    output = u_boot_console.run_command('echo $?')
+    ubman.run_command('tpm2 clear TPM2_RH_PLATFORM')
+    output = ubman.run_command('echo $?')
     assert output.endswith('0')
 
 @pytest.mark.buildconfigspec('cmd_tpm_v2')
-def test_tpm2_change_auth(u_boot_console):
+def test_tpm2_change_auth(ubman):
     """Execute a TPM2_HierarchyChangeAuth command.
 
     Ask the TPM to change the owner, ie. set a new password: 'unicorn'
@@ -167,22 +167,22 @@ def test_tpm2_change_auth(u_boot_console):
     Use the LOCKOUT hierarchy for this. ENDORSEMENT and PLATFORM hierarchies are
     also available.
     """
-    if is_sandbox(u_boot_console):
-        tpm2_sandbox_init(u_boot_console)
-    force_init(u_boot_console)
+    if is_sandbox(ubman):
+        tpm2_sandbox_init(ubman)
+    force_init(ubman)
 
-    u_boot_console.run_command('tpm2 change_auth TPM2_RH_LOCKOUT unicorn')
-    output = u_boot_console.run_command('echo $?')
+    ubman.run_command('tpm2 change_auth TPM2_RH_LOCKOUT unicorn')
+    output = ubman.run_command('echo $?')
     assert output.endswith('0')
 
-    u_boot_console.run_command('tpm2 clear TPM2_RH_LOCKOUT unicorn')
-    output = u_boot_console.run_command('echo $?')
-    u_boot_console.run_command('tpm2 clear TPM2_RH_PLATFORM')
+    ubman.run_command('tpm2 clear TPM2_RH_LOCKOUT unicorn')
+    output = ubman.run_command('echo $?')
+    ubman.run_command('tpm2 clear TPM2_RH_PLATFORM')
     assert output.endswith('0')
 
 @pytest.mark.buildconfigspec('sandbox')
 @pytest.mark.buildconfigspec('cmd_tpm_v2')
-def test_tpm2_get_capability(u_boot_console):
+def test_tpm2_get_capability(ubman):
     """Execute a TPM_GetCapability command.
 
     Display one capability. In our test case, let's display the default DAM
@@ -193,19 +193,19 @@ def test_tpm2_get_capability(u_boot_console):
     There is no expected default values because it would depend on the chip
     used. We can still save them in order to check they have changed later.
     """
-    if is_sandbox(u_boot_console):
-        tpm2_sandbox_init(u_boot_console)
+    if is_sandbox(ubman):
+        tpm2_sandbox_init(ubman)
 
-    force_init(u_boot_console)
-    ram = u_boot_utils.find_ram_base(u_boot_console)
+    force_init(ubman)
+    ram = utils.find_ram_base(ubman)
 
-    read_cap = u_boot_console.run_command('tpm2 get_capability 0x6 0x20e 0x200 1') #0x%x 1' % ram)
-    output = u_boot_console.run_command('echo $?')
+    read_cap = ubman.run_command('tpm2 get_capability 0x6 0x20e 0x200 1') #0x%x 1' % ram)
+    output = ubman.run_command('echo $?')
     assert output.endswith('0')
     assert 'Property 0x0000020e: 0x00000000' in read_cap
 
 @pytest.mark.buildconfigspec('cmd_tpm_v2')
-def test_tpm2_dam_parameters(u_boot_console):
+def test_tpm2_dam_parameters(ubman):
     """Execute a TPM2_DictionaryAttackParameters command.
 
     Change Dictionary Attack Mitigation (DAM) parameters. Ask the TPM to change:
@@ -217,38 +217,38 @@ def test_tpm2_dam_parameters(u_boot_console):
     the authentication, otherwise the lockout will be engaged after the first
     failed authentication attempt.
     """
-    if is_sandbox(u_boot_console):
-        tpm2_sandbox_init(u_boot_console)
-    force_init(u_boot_console)
-    ram = u_boot_utils.find_ram_base(u_boot_console)
+    if is_sandbox(ubman):
+        tpm2_sandbox_init(ubman)
+    force_init(ubman)
+    ram = utils.find_ram_base(ubman)
 
     # Set the DAM parameters to known values
-    u_boot_console.run_command('tpm2 dam_parameters 3 10 0')
-    output = u_boot_console.run_command('echo $?')
+    ubman.run_command('tpm2 dam_parameters 3 10 0')
+    output = ubman.run_command('echo $?')
     assert output.endswith('0')
 
     # Check the values have been saved
-    read_cap = u_boot_console.run_command('tpm2 get_capability 0x6 0x20f 0x%x 3' % ram)
-    output = u_boot_console.run_command('echo $?')
+    read_cap = ubman.run_command('tpm2 get_capability 0x6 0x20f 0x%x 3' % ram)
+    output = ubman.run_command('echo $?')
     assert output.endswith('0')
     assert 'Property 0x0000020f: 0x00000003' in read_cap
     assert 'Property 0x00000210: 0x0000000a' in read_cap
     assert 'Property 0x00000211: 0x00000000' in read_cap
 
 @pytest.mark.buildconfigspec('cmd_tpm_v2')
-def test_tpm2_pcr_read(u_boot_console):
+def test_tpm2_pcr_read(ubman):
     """Execute a TPM2_PCR_Read command.
 
     Perform a PCR read of the 10th PCR. Must be zero.
     """
-    if is_sandbox(u_boot_console):
-        tpm2_sandbox_init(u_boot_console)
+    if is_sandbox(ubman):
+        tpm2_sandbox_init(ubman)
 
-    force_init(u_boot_console)
-    ram = u_boot_utils.find_ram_base(u_boot_console)
+    force_init(ubman)
+    ram = utils.find_ram_base(ubman)
 
-    read_pcr = u_boot_console.run_command('tpm2 pcr_read 10 0x%x' % ram)
-    output = u_boot_console.run_command('echo $?')
+    read_pcr = ubman.run_command('tpm2 pcr_read 10 0x%x' % ram)
+    output = ubman.run_command('echo $?')
     assert output.endswith('0')
 
     # Save the number of PCR updates
@@ -261,7 +261,7 @@ def test_tpm2_pcr_read(u_boot_console):
     assert '00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00' in read_pcr
 
 @pytest.mark.buildconfigspec('cmd_tpm_v2')
-def test_tpm2_pcr_extend(u_boot_console):
+def test_tpm2_pcr_extend(ubman):
     """Execute a TPM2_PCR_Extend command.
 
     Perform a PCR extension with a known hash in memory (zeroed since the board
@@ -270,25 +270,25 @@ def test_tpm2_pcr_extend(u_boot_console):
     No authentication mechanism is used here, not protecting against packet
     replay, yet.
     """
-    if is_sandbox(u_boot_console):
-        tpm2_sandbox_init(u_boot_console)
-    force_init(u_boot_console)
-    ram = u_boot_utils.find_ram_base(u_boot_console)
+    if is_sandbox(ubman):
+        tpm2_sandbox_init(ubman)
+    force_init(ubman)
+    ram = utils.find_ram_base(ubman)
 
-    read_pcr = u_boot_console.run_command('tpm2 pcr_read 10 0x%x' % (ram + 0x20))
-    output = u_boot_console.run_command('echo $?')
+    read_pcr = ubman.run_command('tpm2 pcr_read 10 0x%x' % (ram + 0x20))
+    output = ubman.run_command('echo $?')
     assert output.endswith('0')
     str = re.findall(r'\d+ known updates', read_pcr)[0]
     updates = int(re.findall(r'\d+', str)[0])
 
-    u_boot_console.run_command('tpm2 pcr_extend 10 0x%x' % ram)
-    output = u_boot_console.run_command('echo $?')
+    ubman.run_command('tpm2 pcr_extend 10 0x%x' % ram)
+    output = ubman.run_command('echo $?')
     assert output.endswith('0')
 
     # Read the value back into a different place so we can still use 'ram' as
     # our zero bytes
-    read_pcr = u_boot_console.run_command('tpm2 pcr_read 10 0x%x' % (ram + 0x20))
-    output = u_boot_console.run_command('echo $?')
+    read_pcr = ubman.run_command('tpm2 pcr_read 10 0x%x' % (ram + 0x20))
+    output = ubman.run_command('echo $?')
     assert output.endswith('0')
     assert 'f5 a5 fd 42 d1 6a 20 30 27 98 ef 6e d3 09 97 9b' in read_pcr
     assert '43 00 3d 23 20 d9 f0 e8 ea 98 31 a9 27 59 fb 4b' in read_pcr
@@ -297,12 +297,12 @@ def test_tpm2_pcr_extend(u_boot_console):
     new_updates = int(re.findall(r'\d+', str)[0])
     assert (updates + 1) == new_updates
 
-    u_boot_console.run_command('tpm2 pcr_extend 10 0x%x' % ram)
-    output = u_boot_console.run_command('echo $?')
+    ubman.run_command('tpm2 pcr_extend 10 0x%x' % ram)
+    output = ubman.run_command('echo $?')
     assert output.endswith('0')
 
-    read_pcr = u_boot_console.run_command('tpm2 pcr_read 10 0x%x' % (ram + 0x20))
-    output = u_boot_console.run_command('echo $?')
+    read_pcr = ubman.run_command('tpm2 pcr_read 10 0x%x' % (ram + 0x20))
+    output = ubman.run_command('echo $?')
     assert output.endswith('0')
     assert '7a 05 01 f5 95 7b df 9c b3 a8 ff 49 66 f0 22 65' in read_pcr
     assert 'f9 68 65 8b 7a 9c 62 64 2c ba 11 65 e8 66 42 f5' in read_pcr
@@ -312,7 +312,7 @@ def test_tpm2_pcr_extend(u_boot_console):
     assert (updates + 2) == new_updates
 
 @pytest.mark.buildconfigspec('cmd_tpm_v2')
-def test_tpm2_cleanup(u_boot_console):
+def test_tpm2_cleanup(ubman):
     """Ensure the TPM is cleared from password or test related configuration."""
 
-    force_init(u_boot_console, True)
+    force_init(ubman, True)
diff --git a/test/py/tests/test_trace.py b/test/py/tests/test_trace.py
index 44239da5280..6ac1b225465 100644
--- a/test/py/tests/test_trace.py
+++ b/test/py/tests/test_trace.py
@@ -6,7 +6,7 @@ import os
 import pytest
 import re
 
-import u_boot_utils as util
+import utils
 
 # This is needed for Azure, since the default '..' directory is not writeable
 TMPDIR = '/tmp/test_trace'
@@ -15,19 +15,19 @@ TMPDIR = '/tmp/test_trace'
 RE_LINE = re.compile(r'.*0\.\.\.\.\.? \s*([0-9.]*): func.*[|](\s*)(\S.*)?([{};])$')
 
 
-def collect_trace(cons):
+def collect_trace(ubman):
     """Build U-Boot and run it to collect a trace
 
     Args:
-        cons (ConsoleBase): U-Boot console
+        ubman (ConsoleBase): U-Boot console
 
     Returns:
         tuple:
             str: Filename of the output trace file
             int: Microseconds taken for initf_dm according to bootstage
     """
-    cons.run_command('trace pause')
-    out = cons.run_command('trace stats')
+    ubman.run_command('trace pause')
+    out = ubman.run_command('trace stats')
 
     # The output is something like this:
     #    251,003 function sites
@@ -48,10 +48,10 @@ def collect_trace(cons):
     assert int(vals['untracked function calls']) == 0
     assert int(vals['maximum observed call depth']) > 30
     assert (vals['call depth limit'] ==
-            cons.config.buildconfig.get('config_trace_call_depth_limit'))
+            ubman.config.buildconfig.get('config_trace_call_depth_limit'))
     assert int(vals['calls not traced due to depth']) > 100000
 
-    out = cons.run_command('bootstage report')
+    out = ubman.run_command('bootstage report')
     # Accumulated time:
     #           19,104  dm_r
     #           23,078  of_live
@@ -62,26 +62,26 @@ def collect_trace(cons):
     # Read out the trace data
     addr = 0x02000000
     size = 0x02000000
-    out = cons.run_command(f'trace calls {addr:x} {size:x}')
+    out = ubman.run_command(f'trace calls {addr:x} {size:x}')
     print(out)
     fname = os.path.join(TMPDIR, 'trace')
-    out = cons.run_command(
+    out = ubman.run_command(
         'host save hostfs - %x %s ${profoffset}' % (addr, fname))
     return fname, int(dm_f_time[0])
 
 
-def wipe_and_collect_trace(cons):
+def wipe_and_collect_trace(ubman):
     """Pause and wipe traces, return the number of calls (should be zero)
 
     Args:
-        cons (ConsoleBase): U-Boot console
+        ubman (ConsoleBase): U-Boot console
 
     Returns:
         int: the number of traced function calls reported by 'trace stats'
     """
-    cons.run_command('trace pause')
-    cons.run_command('trace wipe')
-    out = cons.run_command('trace stats')
+    ubman.run_command('trace pause')
+    ubman.run_command('trace wipe')
+    out = ubman.run_command('trace stats')
 
     # The output is something like this:
     # 117,221 function sites
@@ -96,22 +96,22 @@ def wipe_and_collect_trace(cons):
     return int(vals['traced function calls'])
 
 
-def check_function(cons, fname, proftool, map_fname, trace_dat):
+def check_function(ubman, fname, proftool, map_fname, trace_dat):
     """Check that the 'function' output works
 
     Args:
-        cons (ConsoleBase): U-Boot console
+        ubman (ConsoleBase): U-Boot console
         fname (str): Filename of trace file
         proftool (str): Filename of proftool
         map_fname (str): Filename of System.map
         trace_dat (str): Filename of output file
     """
-    out = util.run_and_log(
-        cons, [proftool, '-t', fname, '-o', trace_dat, '-m', map_fname,
+    out = utils.run_and_log(
+        ubman, [proftool, '-t', fname, '-o', trace_dat, '-m', map_fname,
                'dump-ftrace'])
 
     # Check that trace-cmd can read it
-    out = util.run_and_log(cons, ['trace-cmd', 'dump', trace_dat])
+    out = utils.run_and_log(ubman, ['trace-cmd', 'dump', trace_dat])
 
     # Tracing meta data in file /tmp/test_trace/trace.dat:
     #    [Initial format]
@@ -140,7 +140,7 @@ def check_function(cons, fname, proftool, map_fname, trace_dat):
 
     # Check that the trace has something useful
     cmd = f"trace-cmd report -l {trace_dat} |grep -E '(initf_|initr_)'"
-    out = util.run_and_log(cons, ['sh', '-c', cmd])
+    out = utils.run_and_log(ubman, ['sh', '-c', cmd])
 
     # Format:
     #      u-boot-1     0.....    60.805596: function:             initf_malloc
@@ -167,11 +167,11 @@ def check_function(cons, fname, proftool, map_fname, trace_dat):
     assert max_delta < 5
 
 
-def check_funcgraph(cons, fname, proftool, map_fname, trace_dat):
+def check_funcgraph(ubman, fname, proftool, map_fname, trace_dat):
     """Check that the 'funcgraph' output works
 
     Args:
-        cons (ConsoleBase): U-Boot console
+        ubman (ConsoleBase): U-Boot console
         fname (str): Filename of trace file
         proftool (str): Filename of proftool
         map_fname (str): Filename of System.map
@@ -182,13 +182,13 @@ def check_funcgraph(cons, fname, proftool, map_fname, trace_dat):
     """
 
     # Generate the funcgraph format
-    out = util.run_and_log(
-        cons, [proftool, '-t', fname, '-o', trace_dat, '-m', map_fname,
+    out = utils.run_and_log(
+        ubman, [proftool, '-t', fname, '-o', trace_dat, '-m', map_fname,
                'dump-ftrace', '-f', 'funcgraph'])
 
     # Check that the trace has what we expect
     cmd = f'trace-cmd report -l {trace_dat} |head -n 70'
-    out = util.run_and_log(cons, ['sh', '-c', cmd])
+    out = utils.run_and_log(ubman, ['sh', '-c', cmd])
 
     # First look for this:
     #  u-boot-1     0.....   282.101360: funcgraph_entry:        0.004 us   |    initf_malloc();
@@ -230,7 +230,7 @@ def check_funcgraph(cons, fname, proftool, map_fname, trace_dat):
     # Now look for initf_dm() and dm_timer_init() so we can check the bootstage
     # time
     cmd = f"trace-cmd report -l {trace_dat} |grep -E '(initf_dm|dm_timer_init)'"
-    out = util.run_and_log(cons, ['sh', '-c', cmd])
+    out = utils.run_and_log(ubman, ['sh', '-c', cmd])
 
     start_timestamp = None
     end_timestamp = None
@@ -249,14 +249,14 @@ def check_funcgraph(cons, fname, proftool, map_fname, trace_dat):
     return int((float(end_timestamp) - float(start_timestamp)) * 1000000)
 
 
-def check_flamegraph(cons, fname, proftool, map_fname, trace_fg):
+def check_flamegraph(ubman, fname, proftool, map_fname, trace_fg):
     """Check that the 'flamegraph' output works
 
     This spot checks a few call counts and estimates the time taken by the
     initf_dm() function
 
     Args:
-        cons (ConsoleBase): U-Boot console
+        ubman (ConsoleBase): U-Boot console
         fname (str): Filename of trace file
         proftool (str): Filename of proftool
         map_fname (str): Filename of System.map
@@ -267,8 +267,8 @@ def check_flamegraph(cons, fname, proftool, map_fname, trace_fg):
     """
 
     # Generate the flamegraph format
-    out = util.run_and_log(
-        cons, [proftool, '-t', fname, '-o', trace_fg, '-m', map_fname,
+    out = utils.run_and_log(
+        ubman, [proftool, '-t', fname, '-o', trace_fg, '-m', map_fname,
                'dump-flamegraph'])
 
     # We expect dm_timer_init() to be called twice: once before relocation and
@@ -284,8 +284,8 @@ def check_flamegraph(cons, fname, proftool, map_fname, trace_fg):
     assert found == 2
 
     # Generate the timing graph
-    out = util.run_and_log(
-        cons, [proftool, '-t', fname, '-o', trace_fg, '-m', map_fname,
+    utils.run_and_log(
+        ubman, [proftool, '-t', fname, '-o', trace_fg, '-m', map_fname,
                'dump-flamegraph', '-f', 'timing'])
 
     # Add up all the time spend in initf_dm() and its children
@@ -303,28 +303,27 @@ check_flamegraph
 @pytest.mark.slow
 @pytest.mark.boardspec('sandbox')
 @pytest.mark.buildconfigspec('trace')
-def test_trace(u_boot_console):
+def test_trace(ubman):
     """Test we can build sandbox with trace, collect and process a trace"""
-    cons = u_boot_console
 
     if not os.path.exists(TMPDIR):
         os.mkdir(TMPDIR)
-    proftool = os.path.join(cons.config.build_dir, 'tools', 'proftool')
-    map_fname = os.path.join(cons.config.build_dir, 'System.map')
+    proftool = os.path.join(ubman.config.build_dir, 'tools', 'proftool')
+    map_fname = os.path.join(ubman.config.build_dir, 'System.map')
     trace_dat = os.path.join(TMPDIR, 'trace.dat')
     trace_fg = os.path.join(TMPDIR, 'trace.fg')
 
-    fname, dm_f_time = collect_trace(cons)
+    fname, dm_f_time = collect_trace(ubman)
 
-    check_function(cons, fname, proftool, map_fname, trace_dat)
-    trace_time = check_funcgraph(cons, fname, proftool, map_fname, trace_dat)
+    check_function(ubman, fname, proftool, map_fname, trace_dat)
+    trace_time = check_funcgraph(ubman, fname, proftool, map_fname, trace_dat)
 
     # Check that bootstage and funcgraph agree to within 10 microseconds
     diff = abs(trace_time - dm_f_time)
     print(f'trace_time {trace_time}, dm_f_time {dm_f_time}')
     assert diff / dm_f_time < 0.01
 
-    fg_time = check_flamegraph(cons, fname, proftool, map_fname, trace_fg)
+    fg_time = check_flamegraph(ubman, fname, proftool, map_fname, trace_fg)
 
     # Check that bootstage and flamegraph agree to within 30%
     # This allows for CI being slow to run
@@ -332,5 +331,5 @@ def test_trace(u_boot_console):
     assert diff / dm_f_time < 0.3
 
     # Check that the trace buffer can be wiped
-    numcalls = wipe_and_collect_trace(cons)
+    numcalls = wipe_and_collect_trace(ubman)
     assert numcalls == 0
diff --git a/test/py/tests/test_ums.py b/test/py/tests/test_ums.py
index 749b1606235..caf6c0a7270 100644
--- a/test/py/tests/test_ums.py
+++ b/test/py/tests/test_ums.py
@@ -11,7 +11,7 @@ import os.path
 import pytest
 import re
 import time
-import u_boot_utils
+import utils
 
 """
 Note: This test relies on:
@@ -74,13 +74,13 @@ writable_fs_partition value.
 """
 
 @pytest.mark.buildconfigspec('cmd_usb_mass_storage')
-def test_ums(u_boot_console, env__usb_dev_port, env__block_devs):
+def test_ums(ubman, env__usb_dev_port, env__block_devs):
     """Test the "ums" command; the host system must be able to enumerate a UMS
     device when "ums" is running, block and optionally file I/O are tested,
     and this device must disappear when "ums" is aborted.
 
     Args:
-        u_boot_console: A U-Boot console connection.
+        ubman: A U-Boot console connection.
         env__usb_dev_port: The single USB device-mode port specification on
             which to run the test. See the file-level comment above for
             details of the format.
@@ -96,7 +96,7 @@ def test_ums(u_boot_console, env__usb_dev_port, env__block_devs):
     if not have_writable_fs_partition:
         # If 'writable_fs_subdir' is missing, we'll skip all parts of the
         # testing which mount filesystems.
-        u_boot_console.log.warning(
+        ubman.log.warning(
             'boardenv missing "writable_fs_partition"; ' +
             'UMS testing will be limited.')
 
@@ -109,18 +109,15 @@ def test_ums(u_boot_console, env__usb_dev_port, env__block_devs):
     tgt_dev_type = env__block_devs[0]['type']
     tgt_dev_id = env__block_devs[0]['id']
     if have_writable_fs_partition:
-        mount_point = u_boot_console.config.env['env__mount_points'][0]
+        mount_point = ubman.config.env['env__mount_points'][0]
         mount_subdir = env__block_devs[0]['writable_fs_subdir']
         part_num = env__block_devs[0]['writable_fs_partition']
         host_ums_part_node = '%s-part%d' % (host_ums_dev_node, part_num)
+        test_f = utils.PersistentRandomFile(ubman, 'ums.bin', 1024 * 1024);
+        mounted_test_fn = mount_point + '/' + mount_subdir + test_f.fn
     else:
         host_ums_part_node = host_ums_dev_node
 
-    test_f = u_boot_utils.PersistentRandomFile(u_boot_console, 'ums.bin',
-        1024 * 1024);
-    if have_writable_fs_partition:
-        mounted_test_fn = mount_point + '/' + mount_subdir + test_f.fn
-
     def start_ums():
         """Start U-Boot's ums shell command.
 
@@ -133,13 +130,13 @@ def test_ums(u_boot_console, env__usb_dev_port, env__block_devs):
             Nothing.
         """
 
-        u_boot_console.log.action(
+        ubman.log.action(
             'Starting long-running U-Boot ums shell command')
         cmd = 'ums %s %s %s' % (tgt_usb_ctlr, tgt_dev_type, tgt_dev_id)
-        u_boot_console.run_command(cmd, wait_for_prompt=False)
-        u_boot_console.wait_for(re.compile('UMS: LUN.*[\r\n]'))
-        fh = u_boot_utils.wait_until_open_succeeds(host_ums_part_node)
-        u_boot_console.log.action('Reading raw data from UMS device')
+        ubman.run_command(cmd, wait_for_prompt=False)
+        ubman.wait_for(re.compile('UMS: LUN.*[\r\n]'))
+        fh = utils.wait_until_open_succeeds(host_ums_part_node)
+        ubman.log.action('Reading raw data from UMS device')
         fh.read(4096)
         fh.close()
 
@@ -153,9 +150,9 @@ def test_ums(u_boot_console, env__usb_dev_port, env__block_devs):
             Nothing.
         """
 
-        u_boot_console.log.action('Mounting exported UMS device')
+        ubman.log.action('Mounting exported UMS device')
         cmd = ('/bin/mount', host_ums_part_node)
-        u_boot_utils.run_and_log(u_boot_console, cmd)
+        utils.run_and_log(ubman, cmd)
 
     def umount(ignore_errors):
         """Unmount the block device that U-Boot exports.
@@ -170,9 +167,9 @@ def test_ums(u_boot_console, env__usb_dev_port, env__block_devs):
             Nothing.
         """
 
-        u_boot_console.log.action('Unmounting UMS device')
+        ubman.log.action('Unmounting UMS device')
         cmd = ('/bin/umount', host_ums_part_node)
-        u_boot_utils.run_and_log(u_boot_console, cmd, ignore_errors)
+        utils.run_and_log(ubman, cmd, ignore_errors)
 
     def stop_ums(ignore_errors):
         """Stop U-Boot's ums shell command from executing.
@@ -190,42 +187,40 @@ def test_ums(u_boot_console, env__usb_dev_port, env__block_devs):
             Nothing.
         """
 
-        u_boot_console.log.action(
+        ubman.log.action(
             'Stopping long-running U-Boot ums shell command')
-        u_boot_console.ctrlc()
-        u_boot_utils.wait_until_file_open_fails(host_ums_part_node,
+        ubman.ctrlc()
+        utils.wait_until_file_open_fails(host_ums_part_node,
             ignore_errors)
 
     ignore_cleanup_errors = True
-    try:
-        start_ums()
-        if not have_writable_fs_partition:
-            # Skip filesystem-based testing if not configured
-            return
+    if have_writable_fs_partition:
         try:
-            mount()
-            u_boot_console.log.action('Writing test file via UMS')
-            cmd = ('rm', '-f', mounted_test_fn)
-            u_boot_utils.run_and_log(u_boot_console, cmd)
-            if os.path.exists(mounted_test_fn):
-                raise Exception('Could not rm target UMS test file')
-            cmd = ('cp', test_f.abs_fn, mounted_test_fn)
-            u_boot_utils.run_and_log(u_boot_console, cmd)
-            ignore_cleanup_errors = False
+            start_ums()
+            try:
+                mount()
+                ubman.log.action('Writing test file via UMS')
+                cmd = ('rm', '-f', mounted_test_fn)
+                utils.run_and_log(ubman, cmd)
+                if os.path.exists(mounted_test_fn):
+                    raise Exception('Could not rm target UMS test file')
+                cmd = ('cp', test_f.abs_fn, mounted_test_fn)
+                utils.run_and_log(ubman, cmd)
+                ignore_cleanup_errors = False
+            finally:
+                umount(ignore_errors=ignore_cleanup_errors)
         finally:
-            umount(ignore_errors=ignore_cleanup_errors)
-    finally:
-        stop_ums(ignore_errors=ignore_cleanup_errors)
+            stop_ums(ignore_errors=ignore_cleanup_errors)
 
     ignore_cleanup_errors = True
     try:
         start_ums()
         try:
             mount()
-            u_boot_console.log.action('Reading test file back via UMS')
-            read_back_hash = u_boot_utils.md5sum_file(mounted_test_fn)
+            ubman.log.action('Reading test file back via UMS')
+            read_back_hash = utils.md5sum_file(mounted_test_fn)
             cmd = ('rm', '-f', mounted_test_fn)
-            u_boot_utils.run_and_log(u_boot_console, cmd)
+            utils.run_and_log(ubman, cmd)
             ignore_cleanup_errors = False
         finally:
             umount(ignore_errors=ignore_cleanup_errors)
diff --git a/test/py/tests/test_unknown_cmd.py b/test/py/tests/test_unknown_cmd.py
index 8fc284a9249..b40c57f8a10 100644
--- a/test/py/tests/test_unknown_cmd.py
+++ b/test/py/tests/test_unknown_cmd.py
@@ -2,12 +2,12 @@
 # Copyright (c) 2015 Stephen Warren
 # Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
 
-def test_unknown_command(u_boot_console):
+def test_unknown_command(ubman):
     """Test that executing an unknown command causes U-Boot to print an
     error."""
 
     # The "unknown command" error is actively expected here,
     # so error detection for it is disabled.
-    with u_boot_console.disable_check('unknown_command'):
-        response = u_boot_console.run_command('non_existent_cmd')
+    with ubman.disable_check('unknown_command'):
+        response = ubman.run_command('non_existent_cmd')
     assert('Unknown command \'non_existent_cmd\' - try \'help\'' in response)
diff --git a/test/py/tests/test_upl.py b/test/py/tests/test_upl.py
index a1ccc8df233..c79c32adf0b 100644
--- a/test/py/tests/test_upl.py
+++ b/test/py/tests/test_upl.py
@@ -6,10 +6,10 @@
 import os
 
 import pytest
-import u_boot_utils
+import utils
 
 @pytest.mark.boardspec('sandbox_vpl')
-def test_upl_handoff(u_boot_console):
+def test_upl_handoff(ubman):
     """Test of UPL handoff
 
     This works by starting up U-Boot VPL, which gets to SPL and then sets up a
@@ -19,20 +19,19 @@ def test_upl_handoff(u_boot_console):
     The entire FIT is loaded into memory in SPL (in upl_load_from_image()) so
     that it can be inspected in upl_test_info_norun
     """
-    cons = u_boot_console
-    ram = os.path.join(cons.config.build_dir, 'ram.bin')
-    fdt = os.path.join(cons.config.build_dir, 'u-boot.dtb')
+    ram = os.path.join(ubman.config.build_dir, 'ram.bin')
+    fdt = os.path.join(ubman.config.build_dir, 'u-boot.dtb')
 
     # Remove any existing RAM file, so we don't have old data present
     if os.path.exists(ram):
         os.remove(ram)
     flags = ['-m', ram, '-d', fdt, '--upl']
-    cons.restart_uboot_with_flags(flags, use_dtb=False)
+    ubman.restart_uboot_with_flags(flags, use_dtb=False)
 
     # Make sure that Universal Payload is detected in U-Boot proper
-    output = cons.run_command('upl info')
+    output = ubman.run_command('upl info')
     assert 'UPL state: active' == output
 
     # Check the FIT offsets look correct
-    output = cons.run_command('ut upl -f upl_test_info_norun')
+    output = ubman.run_command('ut upl -f upl_test_info_norun')
     assert 'failures: 0' in output
diff --git a/test/py/tests/test_usb.py b/test/py/tests/test_usb.py
index 566d73b7c64..1dcd0834f55 100644
--- a/test/py/tests/test_usb.py
+++ b/test/py/tests/test_usb.py
@@ -4,7 +4,7 @@
 import pytest
 import random
 import re
-import u_boot_utils
+import utils
 
 """
 Note: This test doesn't rely on boardenv_* configuration values but it can
@@ -20,20 +20,20 @@ For example:
 env__usb_device_test_skip = False
 """
 
-def setup_usb(u_boot_console):
-    if u_boot_console.config.env.get('env__usb_device_test_skip', True):
+def setup_usb(ubman):
+    if ubman.config.env.get('env__usb_device_test_skip', True):
         pytest.skip('USB device test is not enabled')
 
 @pytest.mark.buildconfigspec('cmd_usb')
-def test_usb_start(u_boot_console):
-    setup_usb(u_boot_console)
-    output = u_boot_console.run_command('usb start')
+def test_usb_start(ubman):
+    setup_usb(ubman)
+    output = ubman.run_command('usb start')
 
     # if output is empty, usb start may already run as part of preboot command
     # re-start the usb, in that case
     if not output:
-        u_boot_console.run_command('usb stop')
-        output = u_boot_console.run_command('usb start')
+        ubman.run_command('usb stop')
+        output = ubman.run_command('usb start')
 
     if 'No USB device found' in output:
         pytest.skip('No USB controller available')
@@ -61,26 +61,26 @@ def test_usb_start(u_boot_console):
     if 'Starting the controller' in output:
         assert 'USB XHCI' in output
 
-    output = u_boot_console.run_command('echo $?')
+    output = ubman.run_command('echo $?')
     assert output.endswith('0')
     return controllers, storage_device
 
 @pytest.mark.buildconfigspec('cmd_usb')
-def test_usb_stop(u_boot_console):
-    setup_usb(u_boot_console)
-    output = u_boot_console.run_command('usb stop')
+def test_usb_stop(ubman):
+    setup_usb(ubman)
+    output = ubman.run_command('usb stop')
     assert 'stopping USB..' in output
 
-    output = u_boot_console.run_command('echo $?')
+    output = ubman.run_command('echo $?')
     assert output.endswith('0')
 
-    output = u_boot_console.run_command('usb dev')
+    output = ubman.run_command('usb dev')
     assert "USB is stopped. Please issue 'usb start' first." in output
 
 @pytest.mark.buildconfigspec('cmd_usb')
-def test_usb_reset(u_boot_console):
-    setup_usb(u_boot_console)
-    output = u_boot_console.run_command('usb reset')
+def test_usb_reset(ubman):
+    setup_usb(ubman)
+    output = ubman.run_command('usb reset')
 
     if 'No USB device found' in output:
         pytest.skip('No USB controller available')
@@ -107,13 +107,13 @@ def test_usb_reset(u_boot_console):
     if 'Starting the controller' in output:
         assert 'USB XHCI' in output
 
-    output = u_boot_console.run_command('echo $?')
+    output = ubman.run_command('echo $?')
     assert output.endswith('0')
 
 @pytest.mark.buildconfigspec('cmd_usb')
-def test_usb_info(u_boot_console):
-    controllers, storage_device = test_usb_start(u_boot_console)
-    output = u_boot_console.run_command('usb info')
+def test_usb_info(ubman):
+    controllers, storage_device = test_usb_start(ubman)
+    output = ubman.run_command('usb info')
 
     num_controller = len(re.findall(': Hub,', output))
     num_mass_storage = len(re.findall(': Mass Storage,', output))
@@ -121,22 +121,22 @@ def test_usb_info(u_boot_console):
     assert num_controller == controllers - 1
     assert num_mass_storage == storage_device
 
-    output = u_boot_console.run_command('echo $?')
+    output = ubman.run_command('echo $?')
     assert output.endswith('0')
 
     for i in range(0, storage_device + controllers - 1):
-        output = u_boot_console.run_command('usb info %d' % i)
+        output = ubman.run_command('usb info %d' % i)
         num_controller = len(re.findall(': Hub,', output))
         num_mass_storage = len(re.findall(': Mass Storage,', output))
         assert num_controller + num_mass_storage == 1
         assert 'No device available' not in output
-        output = u_boot_console.run_command('echo $?')
+        output = ubman.run_command('echo $?')
         assert output.endswith('0')
 
 @pytest.mark.buildconfigspec('cmd_usb')
-def test_usb_tree(u_boot_console):
-    controllers, storage_device = test_usb_start(u_boot_console)
-    output = u_boot_console.run_command('usb tree')
+def test_usb_tree(ubman):
+    controllers, storage_device = test_usb_start(ubman)
+    output = ubman.run_command('usb tree')
 
     num_controller = len(re.findall('Hub', output))
     num_mass_storage = len(re.findall('Mass Storage', output))
@@ -144,14 +144,14 @@ def test_usb_tree(u_boot_console):
     assert num_controller == controllers - 1
     assert num_mass_storage == storage_device
 
-    output = u_boot_console.run_command('echo $?')
+    output = ubman.run_command('echo $?')
     assert output.endswith('0')
 
 @pytest.mark.buildconfigspec('cmd_usb')
 @pytest.mark.buildconfigspec('usb_storage')
-def test_usb_storage(u_boot_console):
-    controllers, storage_device = test_usb_start(u_boot_console)
-    output = u_boot_console.run_command('usb storage')
+def test_usb_storage(ubman):
+    controllers, storage_device = test_usb_start(ubman)
+    output = ubman.run_command('usb storage')
 
     obj = re.findall(r'Capacity: (\d+|\d+[\.]?\d)', output)
     devices = {}
@@ -167,17 +167,17 @@ def test_usb_storage(u_boot_console):
         except ValueError:
             pytest.fail('USB storage device capacity not recognized')
 
-    output = u_boot_console.run_command('echo $?')
+    output = ubman.run_command('echo $?')
     assert output.endswith('0')
 
 @pytest.mark.buildconfigspec('cmd_usb')
-def test_usb_dev(u_boot_console):
-    controllers, storage_device = test_usb_start(u_boot_console)
-    output = u_boot_console.run_command('usb dev')
+def test_usb_dev(ubman):
+    controllers, storage_device = test_usb_start(ubman)
+    output = ubman.run_command('usb dev')
 
     assert 'no usb devices available' not in output
 
-    output = u_boot_console.run_command('echo $?')
+    output = ubman.run_command('echo $?')
     assert output.endswith('0')
 
     devices = {}
@@ -188,7 +188,7 @@ def test_usb_dev(u_boot_console):
     fail = 0
     for x in range(0, storage_device):
         devices[x]['detected'] = 'yes'
-        output = u_boot_console.run_command('usb dev %d' % x)
+        output = ubman.run_command('usb dev %d' % x)
 
         if 'Card did not respond to voltage select' in output:
             fail = 1
@@ -201,7 +201,7 @@ def test_usb_dev(u_boot_console):
             devices[x]['detected'] = 'no'
 
         assert 'is now current device' in output
-        output = u_boot_console.run_command('echo $?')
+        output = ubman.run_command('echo $?')
         assert output.endswith('0')
 
     if fail:
@@ -210,20 +210,20 @@ def test_usb_dev(u_boot_console):
     return devices, controllers, storage_device
 
 @pytest.mark.buildconfigspec('cmd_usb')
-def test_usb_part(u_boot_console):
-    devices, controllers, storage_device = test_usb_dev(u_boot_console)
+def test_usb_part(ubman):
+    devices, controllers, storage_device = test_usb_dev(ubman)
     if not devices:
         pytest.skip('No devices detected')
 
-    u_boot_console.run_command('usb part')
+    ubman.run_command('usb part')
 
-    output = u_boot_console.run_command('echo $?')
+    output = ubman.run_command('echo $?')
     assert output.endswith('0')
 
     for i in range(0, storage_device):
         if devices[i]['detected'] == 'yes':
-            u_boot_console.run_command('usb dev %d' % i)
-            output = u_boot_console.run_command('usb part')
+            ubman.run_command('usb dev %d' % i)
+            output = ubman.run_command('usb part')
 
             lines = output.split('\n')
             part_fat = []
@@ -241,7 +241,7 @@ def test_usb_part(u_boot_console):
                         part_fat.append(part_id)
                     elif part_type == '83':
                         print('ext(2/4) detected')
-                        output = u_boot_console.run_command(
+                        output = ubman.run_command(
                             'fstype usb %d:%d' % (i, part_id)
                         )
                         if 'ext2' in output:
@@ -261,8 +261,8 @@ def test_usb_part(u_boot_console):
 
 @pytest.mark.buildconfigspec('cmd_usb')
 @pytest.mark.buildconfigspec('cmd_fat')
-def test_usb_fatls_fatinfo(u_boot_console):
-    devices, controllers, storage_device = test_usb_part(u_boot_console)
+def test_usb_fatls_fatinfo(ubman):
+    devices, controllers, storage_device = test_usb_part(ubman)
     if not devices:
         pytest.skip('No devices detected')
 
@@ -270,7 +270,7 @@ def test_usb_fatls_fatinfo(u_boot_console):
     fs = 'fat'
     for x in range(0, int(storage_device)):
         if devices[x]['detected'] == 'yes':
-            u_boot_console.run_command('usb dev %d' % x)
+            ubman.run_command('usb dev %d' % x)
             try:
                 partitions = devices[x][fs]
             except:
@@ -278,7 +278,7 @@ def test_usb_fatls_fatinfo(u_boot_console):
                 continue
 
             for part in partitions:
-                output = u_boot_console.run_command('fatls usb %d:%s' % (x, part))
+                output = ubman.run_command('fatls usb %d:%s' % (x, part))
                 if 'Unrecognized filesystem type' in output:
                     partitions.remove(part)
                     pytest.fail('Unrecognized filesystem')
@@ -286,7 +286,7 @@ def test_usb_fatls_fatinfo(u_boot_console):
                 if not re.search(r'\d file\(s\), \d dir\(s\)', output):
                     pytest.fail('%s read failed on device %d' % (fs.upper, x))
 
-                output = u_boot_console.run_command('fatinfo usb %d:%s' % (x, part))
+                output = ubman.run_command('fatinfo usb %d:%s' % (x, part))
                 string = 'Filesystem: %s' % fs.upper
                 if re.search(string, output):
                     pytest.fail('%s FS failed on device %d' % (fs.upper(), x))
@@ -295,17 +295,17 @@ def test_usb_fatls_fatinfo(u_boot_console):
     if not part_detect:
         pytest.skip('No %s partition detected' % fs.upper())
 
-def usb_fatload_fatwrite(u_boot_console, fs, x, part):
-    addr = u_boot_utils.find_ram_base(u_boot_console)
+def usb_fatload_fatwrite(ubman, fs, x, part):
+    addr = utils.find_ram_base(ubman)
     size = random.randint(4, 1 * 1024 * 1024)
-    output = u_boot_console.run_command('crc32 %x %x' % (addr, size))
+    output = ubman.run_command('crc32 %x %x' % (addr, size))
     m = re.search('==> (.+?)', output)
     if not m:
         pytest.fail('CRC32 failed')
     expected_crc32 = m.group(1)
 
     file = '%s_%d' % ('uboot_test', size)
-    output = u_boot_console.run_command(
+    output = ubman.run_command(
         '%swrite usb %d:%s %x %s %x' % (fs, x, part, addr, file, size)
     )
     assert 'Unable to write' not in output
@@ -315,12 +315,12 @@ def usb_fatload_fatwrite(u_boot_console, fs, x, part):
     assert expected_text in output
 
     alignment = int(
-        u_boot_console.config.buildconfig.get(
+        ubman.config.buildconfig.get(
             'config_sys_cacheline_size', 128
         )
     )
     offset = random.randrange(alignment, 1024, alignment)
-    output = u_boot_console.run_command(
+    output = ubman.run_command(
         '%sload usb %d:%s %x %s' % (fs, x, part, addr + offset, file)
     )
     assert 'Invalid FAT entry' not in output
@@ -329,7 +329,7 @@ def usb_fatload_fatwrite(u_boot_console, fs, x, part):
     expected_text = '%d bytes read' % size
     assert expected_text in output
 
-    output = u_boot_console.run_command(
+    output = ubman.run_command(
         'crc32 %x $filesize' % (addr + offset)
     )
     assert expected_crc32 in output
@@ -339,8 +339,8 @@ def usb_fatload_fatwrite(u_boot_console, fs, x, part):
 @pytest.mark.buildconfigspec('cmd_usb')
 @pytest.mark.buildconfigspec('cmd_fat')
 @pytest.mark.buildconfigspec('cmd_memory')
-def test_usb_fatload_fatwrite(u_boot_console):
-    devices, controllers, storage_device = test_usb_part(u_boot_console)
+def test_usb_fatload_fatwrite(ubman):
+    devices, controllers, storage_device = test_usb_part(ubman)
     if not devices:
         pytest.skip('No devices detected')
 
@@ -348,7 +348,7 @@ def test_usb_fatload_fatwrite(u_boot_console):
     fs = 'fat'
     for x in range(0, int(storage_device)):
         if devices[x]['detected'] == 'yes':
-            u_boot_console.run_command('usb dev %d' % x)
+            ubman.run_command('usb dev %d' % x)
             try:
                 partitions = devices[x][fs]
             except:
@@ -357,15 +357,15 @@ def test_usb_fatload_fatwrite(u_boot_console):
 
             for part in partitions:
                 part_detect = 1
-                usb_fatload_fatwrite(u_boot_console, fs, x, part)
+                usb_fatload_fatwrite(ubman, fs, x, part)
 
     if not part_detect:
         pytest.skip('No %s partition detected' % fs.upper())
 
 @pytest.mark.buildconfigspec('cmd_usb')
 @pytest.mark.buildconfigspec('cmd_ext4')
-def test_usb_ext4ls(u_boot_console):
-    devices, controllers, storage_device = test_usb_part(u_boot_console)
+def test_usb_ext4ls(ubman):
+    devices, controllers, storage_device = test_usb_part(ubman)
     if not devices:
         pytest.skip('No devices detected')
 
@@ -379,9 +379,9 @@ def test_usb_ext4ls(u_boot_console):
                 print('No %s table on this device' % fs.upper())
                 continue
 
-            u_boot_console.run_command('usb dev %d' % x)
+            ubman.run_command('usb dev %d' % x)
             for part in partitions:
-                output = u_boot_console.run_command('%sls usb %d:%s' % (fs, x, part))
+                output = ubman.run_command('%sls usb %d:%s' % (fs, x, part))
                 if 'Unrecognized filesystem type' in output:
                     partitions.remove(part)
                     pytest.fail('Unrecognized filesystem')
@@ -390,17 +390,17 @@ def test_usb_ext4ls(u_boot_console):
     if not part_detect:
         pytest.skip('No %s partition detected' % fs.upper())
 
-def usb_ext4load_ext4write(u_boot_console, fs, x, part):
-    addr = u_boot_utils.find_ram_base(u_boot_console)
+def usb_ext4load_ext4write(ubman, fs, x, part):
+    addr = utils.find_ram_base(ubman)
     size = random.randint(4, 1 * 1024 * 1024)
-    output = u_boot_console.run_command('crc32 %x %x' % (addr, size))
+    output = ubman.run_command('crc32 %x %x' % (addr, size))
     m = re.search('==> (.+?)', output)
     if not m:
         pytest.fail('CRC32 failed')
     expected_crc32 = m.group(1)
     file = '%s_%d' % ('uboot_test', size)
 
-    output = u_boot_console.run_command(
+    output = ubman.run_command(
         '%swrite usb %d:%s %x /%s %x' % (fs, x, part, addr, file, size)
     )
     assert 'Unable to write' not in output
@@ -410,13 +410,13 @@ def usb_ext4load_ext4write(u_boot_console, fs, x, part):
     assert expected_text in output
 
     offset = random.randrange(128, 1024, 128)
-    output = u_boot_console.run_command(
+    output = ubman.run_command(
         '%sload usb %d:%s %x /%s' % (fs, x, part, addr + offset, file)
     )
     expected_text = '%d bytes read' % size
     assert expected_text in output
 
-    output = u_boot_console.run_command(
+    output = ubman.run_command(
         'crc32 %x $filesize' % (addr + offset)
     )
     assert expected_crc32 in output
@@ -427,8 +427,8 @@ def usb_ext4load_ext4write(u_boot_console, fs, x, part):
 @pytest.mark.buildconfigspec('cmd_ext4')
 @pytest.mark.buildconfigspec('cmd_ext4_write')
 @pytest.mark.buildconfigspec('cmd_memory')
-def test_usb_ext4load_ext4write(u_boot_console):
-    devices, controllers, storage_device = test_usb_part(u_boot_console)
+def test_usb_ext4load_ext4write(ubman):
+    devices, controllers, storage_device = test_usb_part(ubman)
     if not devices:
         pytest.skip('No devices detected')
 
@@ -436,7 +436,7 @@ def test_usb_ext4load_ext4write(u_boot_console):
     fs = 'ext4'
     for x in range(0, int(storage_device)):
         if devices[x]['detected'] == 'yes':
-            u_boot_console.run_command('usb dev %d' % x)
+            ubman.run_command('usb dev %d' % x)
             try:
                 partitions = devices[x][fs]
             except:
@@ -445,15 +445,15 @@ def test_usb_ext4load_ext4write(u_boot_console):
 
             for part in partitions:
                 part_detect = 1
-                usb_ext4load_ext4write(u_boot_console, fs, x, part)
+                usb_ext4load_ext4write(ubman, fs, x, part)
 
     if not part_detect:
         pytest.skip('No %s partition detected' % fs.upper())
 
 @pytest.mark.buildconfigspec('cmd_usb')
 @pytest.mark.buildconfigspec('cmd_ext2')
-def test_usb_ext2ls(u_boot_console):
-    devices, controllers, storage_device = test_usb_part(u_boot_console)
+def test_usb_ext2ls(ubman):
+    devices, controllers, storage_device = test_usb_part(ubman)
     if not devices:
         pytest.skip('No devices detected')
 
@@ -461,7 +461,7 @@ def test_usb_ext2ls(u_boot_console):
     fs = 'ext2'
     for x in range(0, int(storage_device)):
         if devices[x]['detected'] == 'yes':
-            u_boot_console.run_command('usb dev %d' % x)
+            ubman.run_command('usb dev %d' % x)
             try:
                 partitions = devices[x][fs]
             except:
@@ -470,7 +470,7 @@ def test_usb_ext2ls(u_boot_console):
 
             for part in partitions:
                 part_detect = 1
-                output = u_boot_console.run_command('%sls usb %d:%s' % (fs, x, part))
+                output = ubman.run_command('%sls usb %d:%s' % (fs, x, part))
                 if 'Unrecognized filesystem type' in output:
                     partitions.remove(part)
                     pytest.fail('Unrecognized filesystem')
@@ -484,8 +484,8 @@ def test_usb_ext2ls(u_boot_console):
 @pytest.mark.buildconfigspec('cmd_ext4')
 @pytest.mark.buildconfigspec('cmd_ext4_write')
 @pytest.mark.buildconfigspec('cmd_memory')
-def test_usb_ext2load(u_boot_console):
-    devices, controllers, storage_device = test_usb_part(u_boot_console)
+def test_usb_ext2load(ubman):
+    devices, controllers, storage_device = test_usb_part(ubman)
 
     if not devices:
         pytest.skip('No devices detected')
@@ -494,7 +494,7 @@ def test_usb_ext2load(u_boot_console):
     fs = 'ext2'
     for x in range(0, int(storage_device)):
         if devices[x]['detected'] == 'yes':
-            u_boot_console.run_command('usb dev %d' % x)
+            ubman.run_command('usb dev %d' % x)
             try:
                 partitions = devices[x][fs]
             except:
@@ -504,17 +504,17 @@ def test_usb_ext2load(u_boot_console):
             for part in partitions:
                 part_detect = 1
                 file, size, expected_crc32 = \
-                    usb_ext4load_ext4write(u_boot_console, fs, x, part)
-                addr = u_boot_utils.find_ram_base(u_boot_console)
+                    usb_ext4load_ext4write(ubman, fs, x, part)
+                addr = utils.find_ram_base(ubman)
 
                 offset = random.randrange(128, 1024, 128)
-                output = u_boot_console.run_command(
+                output = ubman.run_command(
                     '%sload usb %d:%s %x /%s' % (fs, x, part, addr + offset, file)
                 )
                 expected_text = '%d bytes read' % size
                 assert expected_text in output
 
-                output = u_boot_console.run_command(
+                output = ubman.run_command(
                     'crc32 %x $filesize' % (addr + offset)
                 )
                 assert expected_crc32 in output
@@ -524,15 +524,15 @@ def test_usb_ext2load(u_boot_console):
 
 @pytest.mark.buildconfigspec('cmd_usb')
 @pytest.mark.buildconfigspec('cmd_fs_generic')
-def test_usb_ls(u_boot_console):
-    devices, controllers, storage_device = test_usb_part(u_boot_console)
+def test_usb_ls(ubman):
+    devices, controllers, storage_device = test_usb_part(ubman)
     if not devices:
         pytest.skip('No devices detected')
 
     part_detect = 0
     for x in range(0, int(storage_device)):
         if devices[x]['detected'] == 'yes':
-            u_boot_console.run_command('usb dev %d' % x)
+            ubman.run_command('usb dev %d' % x)
             for fs in ['fat', 'ext2', 'ext4']:
                 try:
                     partitions = devices[x][fs]
@@ -542,7 +542,7 @@ def test_usb_ls(u_boot_console):
 
                 for part in partitions:
                     part_detect = 1
-                    output = u_boot_console.run_command('ls usb %d:%s' % (x, part))
+                    output = ubman.run_command('ls usb %d:%s' % (x, part))
                     if re.search(r'No \w+ table on this device', output):
                         pytest.fail(
                             '%s: Partition table not found %d' % (fs.upper(), x)
@@ -554,15 +554,15 @@ def test_usb_ls(u_boot_console):
 @pytest.mark.buildconfigspec('cmd_usb')
 @pytest.mark.buildconfigspec('cmd_ext4_write')
 @pytest.mark.buildconfigspec('cmd_fs_generic')
-def test_usb_load(u_boot_console):
-    devices, controllers, storage_device = test_usb_part(u_boot_console)
+def test_usb_load(ubman):
+    devices, controllers, storage_device = test_usb_part(ubman)
     if not devices:
         pytest.skip('No devices detected')
 
     part_detect = 0
     for x in range(0, int(storage_device)):
         if devices[x]['detected'] == 'yes':
-            u_boot_console.run_command('usb dev %d' % x)
+            ubman.run_command('usb dev %d' % x)
             for fs in ['fat', 'ext2', 'ext4']:
                 try:
                     partitions = devices[x][fs]
@@ -572,23 +572,25 @@ def test_usb_load(u_boot_console):
 
                 for part in partitions:
                     part_detect = 1
-                    addr = u_boot_utils.find_ram_base(u_boot_console)
+                    addr = utils.find_ram_base(ubman)
 
                     if fs == 'fat':
                         file, size, expected_crc32 = \
-                            usb_fatload_fatwrite(u_boot_console, fs, x, part)
+                            usb_fatload_fatwrite(ubman, fs, x, part)
                     elif fs in ['ext4', 'ext2']:
                         file, size, expected_crc32 = \
-                            usb_ext4load_ext4write(u_boot_console, fs, x, part)
+                            usb_ext4load_ext4write(ubman, fs, x, part)
+                    else:
+                        raise Exception('Unsupported filesystem type %s' % fs)
 
                     offset = random.randrange(128, 1024, 128)
-                    output = u_boot_console.run_command(
+                    output = ubman.run_command(
                         'load usb %d:%s %x /%s' % (x, part, addr + offset, file)
                     )
                     expected_text = '%d bytes read' % size
                     assert expected_text in output
 
-                    output = u_boot_console.run_command(
+                    output = ubman.run_command(
                         'crc32 %x $filesize' % (addr + offset)
                     )
                     assert expected_crc32 in output
@@ -598,15 +600,15 @@ def test_usb_load(u_boot_console):
 
 @pytest.mark.buildconfigspec('cmd_usb')
 @pytest.mark.buildconfigspec('cmd_fs_generic')
-def test_usb_save(u_boot_console):
-    devices, controllers, storage_device = test_usb_part(u_boot_console)
+def test_usb_save(ubman):
+    devices, controllers, storage_device = test_usb_part(ubman)
     if not devices:
         pytest.skip('No devices detected')
 
     part_detect = 0
     for x in range(0, int(storage_device)):
         if devices[x]['detected'] == 'yes':
-            u_boot_console.run_command('usb dev %d' % x)
+            ubman.run_command('usb dev %d' % x)
             for fs in ['fat', 'ext2', 'ext4']:
                 try:
                     partitions = devices[x][fs]
@@ -616,12 +618,12 @@ def test_usb_save(u_boot_console):
 
                 for part in partitions:
                     part_detect = 1
-                    addr = u_boot_utils.find_ram_base(u_boot_console)
+                    addr = utils.find_ram_base(ubman)
                     size = random.randint(4, 1 * 1024 * 1024)
                     file = '%s_%d' % ('uboot_test', size)
 
                     offset = random.randrange(128, 1024, 128)
-                    output = u_boot_console.run_command(
+                    output = ubman.run_command(
                         'save usb %d:%s %x /%s %x'
                         % (x, part, addr + offset, file, size)
                     )
diff --git a/test/py/tests/test_ut.py b/test/py/tests/test_ut.py
index d2d8ce10755..b8adb597e11 100644
--- a/test/py/tests/test_ut.py
+++ b/test/py/tests/test_ut.py
@@ -13,7 +13,7 @@ import os
 import os.path
 import pytest
 
-import u_boot_utils
+import utils
 # pylint: disable=E0611
 from tests import fs_helper
 from test_android import test_abootimg
@@ -27,12 +27,12 @@ def mkdir_cond(dirname):
     if not os.path.exists(dirname):
         os.mkdir(dirname)
 
-def setup_image(cons, devnum, part_type, img_size=20, second_part=False,
+def setup_image(ubman, devnum, part_type, img_size=20, second_part=False,
                 basename='mmc'):
     """Create a disk image with a single partition
 
     Args:
-        cons (ConsoleBase): Console to use
+        ubman (ConsoleBase): Console to use
         devnum (int): Device number to use, e.g. 1
         part_type (int): Partition type, e.g. 0xc for FAT32
         img_size (int): Image size in MiB
@@ -44,26 +44,37 @@ def setup_image(cons, devnum, part_type, img_size=20, second_part=False,
             str: Filename of MMC image
             str: Directory name of scratch directory
     """
-    fname = os.path.join(cons.config.source_dir, f'{basename}{devnum}.img')
-    mnt = os.path.join(cons.config.persistent_data_dir, 'scratch')
+    fname = os.path.join(ubman.config.source_dir, f'{basename}{devnum}.img')
+    mnt = os.path.join(ubman.config.persistent_data_dir, 'scratch')
     mkdir_cond(mnt)
 
     spec = f'type={part_type:x}, size={img_size - 2}M, start=1M, bootable'
     if second_part:
         spec += '\ntype=c'
 
-    u_boot_utils.run_and_log(cons, f'qemu-img create {fname} 20M')
-    u_boot_utils.run_and_log(cons, f'sfdisk {fname}',
+    utils.run_and_log(ubman, f'qemu-img create {fname} 20M')
+    utils.run_and_log(ubman, f'sfdisk {fname}',
                              stdin=spec.encode('utf-8'))
     return fname, mnt
 
-def setup_bootmenu_image(cons):
+def copy_partition(ubman, fsfile, outname):
+    """Copy a partition into a disk iamge
+
+    Args:
+        ubman (ConsoleBase): U-Boot fixture
+        fsfile (str): Name of partition file
+        outname (str): Name of full-disk file to update
+    """
+    utils.run_and_log(ubman,
+                      f'dd if={fsfile} of={outname} bs=1M seek=1 conv=notrunc')
+
+def setup_bootmenu_image(ubman):
     """Create a 20MB disk image with a single ext4 partition
 
     This is modelled on Armbian 22.08 Jammy
     """
     mmc_dev = 4
-    fname, mnt = setup_image(cons, mmc_dev, 0x83)
+    fname, mnt = setup_image(ubman, mmc_dev, 0x83)
 
     script = '''# DO NOT EDIT THIS FILE
 #
@@ -146,16 +157,16 @@ booti ${kernel_addr_r} ${ramdisk_addr_r} ${fdt_addr_r}
     with open(cmd_fname, 'w', encoding='ascii') as outf:
         print(script, file=outf)
 
-    infname = os.path.join(cons.config.source_dir,
+    infname = os.path.join(ubman.config.source_dir,
                             'test/py/tests/bootstd/armbian.bmp.xz')
     bmp_file = os.path.join(bootdir, 'boot.bmp')
-    u_boot_utils.run_and_log(
-        cons,
+    utils.run_and_log(
+        ubman,
         ['sh', '-c', f'xz -dc {infname} >{bmp_file}'])
 
-    mkimage = cons.config.build_dir + '/tools/mkimage'
-    u_boot_utils.run_and_log(
-        cons, f'{mkimage} -C none -A arm -T script -d {cmd_fname} {scr_fname}')
+    mkimage = ubman.config.build_dir + '/tools/mkimage'
+    utils.run_and_log(
+        ubman, f'{mkimage} -C none -A arm -T script -d {cmd_fname} {scr_fname}')
 
     kernel = 'vmlinuz-5.15.63-rockchip64'
     target = os.path.join(bootdir, kernel)
@@ -165,21 +176,21 @@ booti ${kernel_addr_r} ${ramdisk_addr_r} ${fdt_addr_r}
     symlink = os.path.join(bootdir, 'Image')
     if os.path.exists(symlink):
         os.remove(symlink)
-    u_boot_utils.run_and_log(
-        cons, f'echo here {kernel} {symlink}')
+    utils.run_and_log(
+        ubman, f'echo here {kernel} {symlink}')
     os.symlink(kernel, symlink)
 
     fsfile = 'ext18M.img'
-    u_boot_utils.run_and_log(cons, f'fallocate -l 18M {fsfile}')
-    u_boot_utils.run_and_log(cons, f'mkfs.ext4 {fsfile} -d {mnt}')
-    u_boot_utils.run_and_log(cons, f'dd if={fsfile} of={fname} bs=1M seek=1')
-    u_boot_utils.run_and_log(cons, f'rm -rf {mnt}')
-    u_boot_utils.run_and_log(cons, f'rm -f {fsfile}')
+    utils.run_and_log(ubman, f'fallocate -l 18M {fsfile}')
+    utils.run_and_log(ubman, f'mkfs.ext4 {fsfile} -d {mnt}')
+    copy_partition(ubman, fsfile, fname)
+    utils.run_and_log(ubman, f'rm -rf {mnt}')
+    utils.run_and_log(ubman, f'rm -f {fsfile}')
 
-def setup_bootflow_image(cons):
+def setup_bootflow_image(ubman):
     """Create a 20MB disk image with a single FAT partition"""
     mmc_dev = 1
-    fname, mnt = setup_image(cons, mmc_dev, 0xc, second_part=True)
+    fname, mnt = setup_image(ubman, mmc_dev, 0xc, second_part=True)
 
     vmlinux = 'vmlinuz-5.3.7-301.fc31.armv7hl'
     initrd = 'initramfs-5.3.7-301.fc31.armv7hl.img'
@@ -204,12 +215,12 @@ label Fedora-Workstation-armhfp-31-1.9 (5.3.7-301.fc31.armv7hl)
     with open(conf, 'w', encoding='ascii') as fd:
         print(script, file=fd)
 
-    inf = os.path.join(cons.config.persistent_data_dir, 'inf')
+    inf = os.path.join(ubman.config.persistent_data_dir, 'inf')
     with open(inf, 'wb') as fd:
         fd.write(gzip.compress(b'vmlinux'))
-    mkimage = cons.config.build_dir + '/tools/mkimage'
-    u_boot_utils.run_and_log(
-        cons, f'{mkimage} -f auto -d {inf} {os.path.join(mnt, vmlinux)}')
+    mkimage = ubman.config.build_dir + '/tools/mkimage'
+    utils.run_and_log(
+        ubman, f'{mkimage} -f auto -d {inf} {os.path.join(mnt, vmlinux)}')
 
     with open(os.path.join(mnt, initrd), 'w', encoding='ascii') as fd:
         print('initrd', file=fd)
@@ -217,28 +228,28 @@ label Fedora-Workstation-armhfp-31-1.9 (5.3.7-301.fc31.armv7hl)
     mkdir_cond(os.path.join(mnt, dtbdir))
 
     dtb_file = os.path.join(mnt, f'{dtbdir}/sandbox.dtb')
-    u_boot_utils.run_and_log(
-        cons, f'dtc -o {dtb_file}', stdin=b'/dts-v1/; / {};')
+    utils.run_and_log(
+        ubman, f'dtc -o {dtb_file}', stdin=b'/dts-v1/; / {};')
 
     fsfile = 'vfat18M.img'
-    u_boot_utils.run_and_log(cons, f'fallocate -l 18M {fsfile}')
-    u_boot_utils.run_and_log(cons, f'mkfs.vfat {fsfile}')
-    u_boot_utils.run_and_log(cons, ['sh', '-c', f'mcopy -i {fsfile} {mnt}/* ::/'])
-    u_boot_utils.run_and_log(cons, f'dd if={fsfile} of={fname} bs=1M seek=1')
-    u_boot_utils.run_and_log(cons, f'rm -rf {mnt}')
-    u_boot_utils.run_and_log(cons, f'rm -f {fsfile}')
-
-def setup_cros_image(cons):
+    utils.run_and_log(ubman, f'fallocate -l 18M {fsfile}')
+    utils.run_and_log(ubman, f'mkfs.vfat {fsfile}')
+    utils.run_and_log(ubman, ['sh', '-c', f'mcopy -i {fsfile} {mnt}/* ::/'])
+    copy_partition(ubman, fsfile, fname)
+    utils.run_and_log(ubman, f'rm -rf {mnt}')
+    utils.run_and_log(ubman, f'rm -f {fsfile}')
+
+def setup_cros_image(ubman):
     """Create a 20MB disk image with ChromiumOS partitions"""
     Partition = collections.namedtuple('part', 'start,size,name')
     parts = {}
     disk_data = None
 
-    def pack_kernel(cons, arch, kern, dummy):
+    def pack_kernel(ubman, arch, kern, dummy):
         """Pack a kernel containing some fake data
 
         Args:
-            cons (ConsoleBase): Console to use
+            ubman (ConsoleBase): Console to use
             arch (str): Architecture to use ('x86' or 'arm')
             kern (str): Filename containing kernel
             dummy (str): Dummy filename to use for config and bootloader
@@ -246,10 +257,10 @@ def setup_cros_image(cons):
         Return:
             bytes: Packed-kernel data
         """
-        kern_part = os.path.join(cons.config.result_dir,
+        kern_part = os.path.join(ubman.config.result_dir,
                                  f'kern-part-{arch}.bin')
-        u_boot_utils.run_and_log(
-            cons,
+        utils.run_and_log(
+            ubman,
             f'futility vbutil_kernel --pack {kern_part} '
             '--keyblock doc/chromium/files/devkeys/kernel.keyblock '
             '--signprivate doc/chromium/files/devkeys/kernel_data_key.vbprivk '
@@ -275,9 +286,9 @@ def setup_cros_image(cons):
         disk_data = disk_data[:start] + data + disk_data[start + len(data):]
 
     mmc_dev = 5
-    fname = os.path.join(cons.config.source_dir, f'mmc{mmc_dev}.img')
-    u_boot_utils.run_and_log(cons, f'qemu-img create {fname} 20M')
-    u_boot_utils.run_and_log(cons, f'cgpt create {fname}')
+    fname = os.path.join(ubman.config.source_dir, f'mmc{mmc_dev}.img')
+    utils.run_and_log(ubman, f'qemu-img create {fname} 20M')
+    utils.run_and_log(ubman, f'cgpt create {fname}')
 
     uuid_state = 'ebd0a0a2-b9e5-4433-87c0-68b6b72699c7'
     uuid_kern = 'fe3a2a5d-4f32-41a7-b725-accc3285a309'
@@ -316,13 +327,13 @@ def setup_cros_image(cons):
             size = int(size_str[:-1]) * sect_1mb
         else:
             size = int(size_str)
-        u_boot_utils.run_and_log(
-            cons,
+        utils.run_and_log(
+            ubman,
             f"cgpt add -i {part['num']} -b {ptr} -s {size} -t {part['type']} {fname}")
         ptr += size
 
-    u_boot_utils.run_and_log(cons, f'cgpt boot -p {fname}')
-    out = u_boot_utils.run_and_log(cons, f'cgpt show -q {fname}')
+    utils.run_and_log(ubman, f'cgpt boot -p {fname}')
+    out = utils.run_and_log(ubman, f'cgpt show -q {fname}')
 
     # We expect something like this:
     #   8239        2048       1  Basic data
@@ -344,14 +355,14 @@ def setup_cros_image(cons):
         parts[int(num)] = Partition(int(start), int(size), name)
 
     # Set up the kernel command-line
-    dummy = os.path.join(cons.config.result_dir, 'dummy.txt')
+    dummy = os.path.join(ubman.config.result_dir, 'dummy.txt')
     with open(dummy, 'wb') as outf:
         outf.write(b'BOOT_IMAGE=/vmlinuz-5.15.0-121-generic root=/dev/nvme0n1p1 ro quiet splash vt.handoff=7')
 
     # For now we just use dummy kernels. This limits testing to just detecting
     # a signed kernel. We could add support for the x86 data structures so that
     # testing could cover getting the cmdline, setup.bin and other pieces.
-    kern = os.path.join(cons.config.result_dir, 'kern.bin')
+    kern = os.path.join(ubman.config.result_dir, 'kern.bin')
     with open(kern, 'wb') as outf:
         outf.write(b'kernel\n')
 
@@ -359,15 +370,15 @@ def setup_cros_image(cons):
         disk_data = inf.read()
 
     # put x86 kernel in partition 2 and arm one in partition 4
-    set_part_data(2, pack_kernel(cons, 'x86', kern, dummy))
-    set_part_data(4, pack_kernel(cons, 'arm', kern, dummy))
+    set_part_data(2, pack_kernel(ubman, 'x86', kern, dummy))
+    set_part_data(4, pack_kernel(ubman, 'arm', kern, dummy))
 
     with open(fname, 'wb') as outf:
         outf.write(disk_data)
 
     return fname
 
-def setup_android_image(cons):
+def setup_android_image(ubman):
     """Create a 20MB disk image with Android partitions"""
     Partition = collections.namedtuple('part', 'start,size,name')
     parts = {}
@@ -388,9 +399,9 @@ def setup_android_image(cons):
         disk_data = disk_data[:start] + data + disk_data[start + len(data):]
 
     mmc_dev = 7
-    fname = os.path.join(cons.config.source_dir, f'mmc{mmc_dev}.img')
-    u_boot_utils.run_and_log(cons, f'qemu-img create {fname} 20M')
-    u_boot_utils.run_and_log(cons, f'cgpt create {fname}')
+    fname = os.path.join(ubman.config.source_dir, f'mmc{mmc_dev}.img')
+    utils.run_and_log(ubman, f'qemu-img create {fname} 20M')
+    utils.run_and_log(ubman, f'cgpt create {fname}')
 
     ptr = 40
 
@@ -412,13 +423,13 @@ def setup_android_image(cons):
             size = int(size_str[:-1]) * sect_1mb
         else:
             size = int(size_str)
-        u_boot_utils.run_and_log(
-            cons,
+        utils.run_and_log(
+            ubman,
             f"cgpt add -i {part['num']} -b {ptr} -s {size} -l {part['label']} -t basicdata {fname}")
         ptr += size
 
-    u_boot_utils.run_and_log(cons, f'cgpt boot -p {fname}')
-    out = u_boot_utils.run_and_log(cons, f'cgpt show -q {fname}')
+    utils.run_and_log(ubman, f'cgpt boot -p {fname}')
+    out = utils.run_and_log(ubman, f'cgpt show -q {fname}')
 
     # Create a dict (indexed by partition number) containing the above info
     for line in out.splitlines():
@@ -428,13 +439,13 @@ def setup_android_image(cons):
     with open(fname, 'rb') as inf:
         disk_data = inf.read()
 
-    test_abootimg.AbootimgTestDiskImage(cons, 'bootv4.img', test_abootimg.boot_img_hex)
-    boot_img = os.path.join(cons.config.result_dir, 'bootv4.img')
+    test_abootimg.AbootimgTestDiskImage(ubman, 'bootv4.img', test_abootimg.boot_img_hex)
+    boot_img = os.path.join(ubman.config.result_dir, 'bootv4.img')
     with open(boot_img, 'rb') as inf:
         set_part_data(2, inf.read())
 
-    test_abootimg.AbootimgTestDiskImage(cons, 'vendor_boot.img', test_abootimg.vboot_img_hex)
-    vendor_boot_img = os.path.join(cons.config.result_dir, 'vendor_boot.img')
+    test_abootimg.AbootimgTestDiskImage(ubman, 'vendor_boot.img', test_abootimg.vboot_img_hex)
+    vendor_boot_img = os.path.join(ubman.config.result_dir, 'vendor_boot.img')
     with open(vendor_boot_img, 'rb') as inf:
         set_part_data(4, inf.read())
 
@@ -444,9 +455,9 @@ def setup_android_image(cons):
     print(f'wrote to {fname}')
 
     mmc_dev = 8
-    fname = os.path.join(cons.config.source_dir, f'mmc{mmc_dev}.img')
-    u_boot_utils.run_and_log(cons, f'qemu-img create {fname} 20M')
-    u_boot_utils.run_and_log(cons, f'cgpt create {fname}')
+    fname = os.path.join(ubman.config.source_dir, f'mmc{mmc_dev}.img')
+    utils.run_and_log(ubman, f'qemu-img create {fname} 20M')
+    utils.run_and_log(ubman, f'cgpt create {fname}')
 
     ptr = 40
 
@@ -466,13 +477,13 @@ def setup_android_image(cons):
             size = int(size_str[:-1]) * sect_1mb
         else:
             size = int(size_str)
-        u_boot_utils.run_and_log(
-            cons,
+        utils.run_and_log(
+            ubman,
             f"cgpt add -i {part['num']} -b {ptr} -s {size} -l {part['label']} -t basicdata {fname}")
         ptr += size
 
-    u_boot_utils.run_and_log(cons, f'cgpt boot -p {fname}')
-    out = u_boot_utils.run_and_log(cons, f'cgpt show -q {fname}')
+    utils.run_and_log(ubman, f'cgpt boot -p {fname}')
+    out = utils.run_and_log(ubman, f'cgpt show -q {fname}')
 
     # Create a dict (indexed by partition number) containing the above info
     for line in out.splitlines():
@@ -482,8 +493,8 @@ def setup_android_image(cons):
     with open(fname, 'rb') as inf:
         disk_data = inf.read()
 
-    test_abootimg.AbootimgTestDiskImage(cons, 'boot.img', test_abootimg.img_hex)
-    boot_img = os.path.join(cons.config.result_dir, 'boot.img')
+    test_abootimg.AbootimgTestDiskImage(ubman, 'boot.img', test_abootimg.img_hex)
+    boot_img = os.path.join(ubman.config.result_dir, 'boot.img')
     with open(boot_img, 'rb') as inf:
         set_part_data(2, inf.read())
 
@@ -494,95 +505,95 @@ def setup_android_image(cons):
 
     return fname
 
-def setup_cedit_file(cons):
+def setup_cedit_file(ubman):
     """Set up a .dtb file for use with testing expo and configuration editor"""
-    infname = os.path.join(cons.config.source_dir,
+    infname = os.path.join(ubman.config.source_dir,
                            'test/boot/files/expo_layout.dts')
-    inhname = os.path.join(cons.config.source_dir,
+    inhname = os.path.join(ubman.config.source_dir,
                            'test/boot/files/expo_ids.h')
-    expo_tool = os.path.join(cons.config.source_dir, 'tools/expo.py')
+    expo_tool = os.path.join(ubman.config.source_dir, 'tools/expo.py')
     outfname = 'cedit.dtb'
-    u_boot_utils.run_and_log(
-        cons, f'{expo_tool} -e {inhname} -l {infname} -o {outfname}')
+    utils.run_and_log(
+        ubman, f'{expo_tool} -e {inhname} -l {infname} -o {outfname}')
 
 @pytest.mark.buildconfigspec('ut_dm')
-def test_ut_dm_init(u_boot_console):
+def test_ut_dm_init(ubman):
     """Initialize data for ut dm tests."""
 
-    fn = u_boot_console.config.source_dir + '/testflash.bin'
+    fn = ubman.config.source_dir + '/testflash.bin'
     if not os.path.exists(fn):
         data = b'this is a test'
         data += b'\x00' * ((4 * 1024 * 1024) - len(data))
         with open(fn, 'wb') as fh:
             fh.write(data)
 
-    fn = u_boot_console.config.source_dir + '/spi.bin'
+    fn = ubman.config.source_dir + '/spi.bin'
     if not os.path.exists(fn):
         data = b'\x00' * (2 * 1024 * 1024)
         with open(fn, 'wb') as fh:
             fh.write(data)
 
     # Create a file with a single partition
-    fn = u_boot_console.config.source_dir + '/scsi.img'
+    fn = ubman.config.source_dir + '/scsi.img'
     if not os.path.exists(fn):
         data = b'\x00' * (2 * 1024 * 1024)
         with open(fn, 'wb') as fh:
             fh.write(data)
-        u_boot_utils.run_and_log(
-            u_boot_console, f'sfdisk {fn}', stdin=b'type=83')
+        utils.run_and_log(
+            ubman, f'sfdisk {fn}', stdin=b'type=83')
 
-    fs_helper.mk_fs(u_boot_console.config, 'ext2', 0x200000, '2MB', None)
-    fs_helper.mk_fs(u_boot_console.config, 'fat32', 0x100000, '1MB', None)
+    fs_helper.mk_fs(ubman.config, 'ext2', 0x200000, '2MB', None)
+    fs_helper.mk_fs(ubman.config, 'fat32', 0x100000, '1MB', None)
 
     mmc_dev = 6
-    fn = os.path.join(u_boot_console.config.source_dir, f'mmc{mmc_dev}.img')
+    fn = os.path.join(ubman.config.source_dir, f'mmc{mmc_dev}.img')
     data = b'\x00' * (12 * 1024 * 1024)
     with open(fn, 'wb') as fh:
         fh.write(data)
 
 
-def setup_efi_image(cons):
+def setup_efi_image(ubman):
     """Create a 20MB disk image with an EFI app on it"""
     devnum = 1
     basename = 'flash'
-    fname, mnt = setup_image(cons, devnum, 0xc, second_part=True,
+    fname, mnt = setup_image(ubman, devnum, 0xc, second_part=True,
                              basename=basename)
 
     efi_dir = os.path.join(mnt, 'EFI')
     mkdir_cond(efi_dir)
     bootdir = os.path.join(efi_dir, 'BOOT')
     mkdir_cond(bootdir)
-    efi_src = os.path.join(cons.config.build_dir,
+    efi_src = os.path.join(ubman.config.build_dir,
                         'lib/efi_loader/testapp.efi')
     efi_dst = os.path.join(bootdir, 'BOOTSBOX.EFI')
     with open(efi_src, 'rb') as inf:
         with open(efi_dst, 'wb') as outf:
             outf.write(inf.read())
     fsfile = 'vfat18M.img'
-    u_boot_utils.run_and_log(cons, f'fallocate -l 18M {fsfile}')
-    u_boot_utils.run_and_log(cons, f'mkfs.vfat {fsfile}')
-    u_boot_utils.run_and_log(cons, ['sh', '-c', f'mcopy -vs -i {fsfile} {mnt}/* ::/'])
-    u_boot_utils.run_and_log(cons, f'dd if={fsfile} of={fname} bs=1M seek=1')
-    u_boot_utils.run_and_log(cons, f'rm -rf {mnt}')
-    u_boot_utils.run_and_log(cons, f'rm -f {fsfile}')
+    utils.run_and_log(ubman, f'fallocate -l 18M {fsfile}')
+    utils.run_and_log(ubman, f'mkfs.vfat {fsfile}')
+    utils.run_and_log(ubman, ['sh', '-c', f'mcopy -vs -i {fsfile} {mnt}/* ::/'])
+    copy_partition(ubman, fsfile, fname)
+    utils.run_and_log(ubman, f'rm -rf {mnt}')
+    utils.run_and_log(ubman, f'rm -f {fsfile}')
 
 @pytest.mark.buildconfigspec('cmd_bootflow')
 @pytest.mark.buildconfigspec('sandbox')
-def test_ut_dm_init_bootstd(u_boot_console):
+def test_ut_dm_init_bootstd(ubman):
     """Initialise data for bootflow tests"""
 
-    setup_bootflow_image(u_boot_console)
-    setup_bootmenu_image(u_boot_console)
-    setup_cedit_file(u_boot_console)
-    setup_cros_image(u_boot_console)
-    setup_android_image(u_boot_console)
-    setup_efi_image(u_boot_console)
+    setup_bootflow_image(ubman)
+    setup_bootmenu_image(ubman)
+    setup_cedit_file(ubman)
+    setup_cros_image(ubman)
+    setup_android_image(ubman)
+    setup_efi_image(ubman)
 
     # Restart so that the new mmc1.img is picked up
-    u_boot_console.restart_uboot()
+    ubman.restart_uboot()
 
 
-def test_ut(u_boot_console, ut_subtest):
+def test_ut(ubman, ut_subtest):
     """Execute a "ut" subtest.
 
     The subtests are collected in function generate_ut_subtest() from linker
@@ -595,16 +606,16 @@ def test_ut(u_boot_console, ut_subtest):
     implemented in C function foo_test_bar().
 
     Args:
-        u_boot_console (ConsoleBase): U-Boot console
+        ubman (ConsoleBase): U-Boot console
         ut_subtest (str): test to be executed via command ut, e.g 'foo bar' to
             execute command 'ut foo bar'
     """
 
     if ut_subtest == 'hush hush_test_simple_dollar':
         # ut hush hush_test_simple_dollar prints "Unknown command" on purpose.
-        with u_boot_console.disable_check('unknown_command'):
-            output = u_boot_console.run_command('ut ' + ut_subtest)
+        with ubman.disable_check('unknown_command'):
+            output = ubman.run_command('ut ' + ut_subtest)
         assert 'Unknown command \'quux\' - try \'help\'' in output
     else:
-        output = u_boot_console.run_command('ut ' + ut_subtest)
+        output = ubman.run_command('ut ' + ut_subtest)
     assert output.endswith('failures: 0')
diff --git a/test/py/tests/test_vbe.py b/test/py/tests/test_vbe.py
index 861df3f8266..a1f32f375b6 100644
--- a/test/py/tests/test_vbe.py
+++ b/test/py/tests/test_vbe.py
@@ -90,11 +90,10 @@ ut bootstd -f vbe_test_fixup_norun
 
 @pytest.mark.boardspec('sandbox_flattree')
 @pytest.mark.requiredtool('dtc')
-def test_vbe(u_boot_console):
-    cons = u_boot_console
-    kernel = fit_util.make_kernel(cons, 'vbe-kernel.bin', 'kernel')
-    fdt = fit_util.make_dtb(cons, base_fdt, 'vbe-fdt')
-    fdt_out = fit_util.make_fname(cons, 'fdt-out.dtb')
+def test_vbe(ubman):
+    kernel = fit_util.make_kernel(ubman, 'vbe-kernel.bin', 'kernel')
+    fdt = fit_util.make_dtb(ubman, base_fdt, 'vbe-fdt')
+    fdt_out = fit_util.make_fname(ubman, 'fdt-out.dtb')
 
     params = {
         'fit_addr' : 0x1000,
@@ -108,13 +107,13 @@ def test_vbe(u_boot_console):
 
         'compression' : 'none',
     }
-    mkimage = cons.config.build_dir + '/tools/mkimage'
-    fit = fit_util.make_fit(cons, mkimage, base_its, params, 'test-vbe.fit',
+    mkimage = ubman.config.build_dir + '/tools/mkimage'
+    fit = fit_util.make_fit(ubman, mkimage, base_its, params, 'test-vbe.fit',
                             base_fdt)
     params['fit'] = fit
     cmd = base_script % params
 
-    with cons.log.section('Kernel load'):
-        output = cons.run_command_list(cmd.splitlines())
+    with ubman.log.section('Kernel load'):
+        output = ubman.run_command_list(cmd.splitlines())
 
     assert 'failures: 0' in output[-1]
diff --git a/test/py/tests/test_vbe_vpl.py b/test/py/tests/test_vbe_vpl.py
index ed12d3a4618..f011b034f63 100644
--- a/test/py/tests/test_vbe_vpl.py
+++ b/test/py/tests/test_vbe_vpl.py
@@ -6,35 +6,34 @@
 import os
 
 import pytest
-import u_boot_utils
+import utils
 
 @pytest.mark.boardspec('sandbox_vpl')
 @pytest.mark.requiredtool('dtc')
-def test_vbe_vpl(u_boot_console):
-    cons = u_boot_console
-    #cmd = [cons.config.build_dir + fname, '-v']
-    ram = os.path.join(cons.config.build_dir, 'ram.bin')
-    fdt = os.path.join(cons.config.build_dir, 'arch/sandbox/dts/test.dtb')
-    image_fname = os.path.join(cons.config.build_dir, 'image.bin')
+def test_vbe_vpl(ubman):
+    #cmd = [ubman.config.build_dir + fname, '-v']
+    ram = os.path.join(ubman.config.build_dir, 'ram.bin')
+    fdt = os.path.join(ubman.config.build_dir, 'arch/sandbox/dts/test.dtb')
+    image_fname = os.path.join(ubman.config.build_dir, 'image.bin')
 
     # Enable firmware1 and the mmc that it uses. These are needed for the full
     # VBE flow.
-    u_boot_utils.run_and_log(
-        cons, f'fdtput -t s {fdt} /bootstd/firmware0 status disabled')
-    u_boot_utils.run_and_log(
-        cons, f'fdtput -t s {fdt} /bootstd/firmware1 status okay')
-    u_boot_utils.run_and_log(
-        cons, f'fdtput -t s {fdt} /mmc3 status okay')
-    u_boot_utils.run_and_log(
-        cons, f'fdtput -t s {fdt} /mmc3 filename {image_fname}')
+    utils.run_and_log(
+        ubman, f'fdtput -t s {fdt} /bootstd/firmware0 status disabled')
+    utils.run_and_log(
+        ubman, f'fdtput -t s {fdt} /bootstd/firmware1 status okay')
+    utils.run_and_log(
+        ubman, f'fdtput -t s {fdt} /mmc3 status okay')
+    utils.run_and_log(
+        ubman, f'fdtput -t s {fdt} /mmc3 filename {image_fname}')
 
     # Remove any existing RAM file, so we don't have old data present
     if os.path.exists(ram):
         os.remove(ram)
     flags = ['-p', image_fname, '-w', '-s', 'state.dtb']
-    cons.restart_uboot_with_flags(flags)
+    ubman.restart_uboot_with_flags(flags)
 
     # Make sure that VBE was used in both VPL (to load SPL) and SPL (to load
     # U-Boot
-    output = cons.run_command('vbe state')
+    output = ubman.run_command('vbe state')
     assert output == 'Phases: VPL SPL'
diff --git a/test/py/tests/test_vboot.py b/test/py/tests/test_vboot.py
index 7e0e8e44750..7a7f9c379de 100644
--- a/test/py/tests/test_vboot.py
+++ b/test/py/tests/test_vboot.py
@@ -42,12 +42,12 @@ import os
 import shutil
 import struct
 import pytest
-import u_boot_utils as util
+import utils
 import vboot_forge
 import vboot_evil
 
 # Common helper functions
-def dtc(dts, cons, dtc_args, datadir, tmpdir, dtb):
+def dtc(dts, ubman, dtc_args, datadir, tmpdir, dtb):
     """Run the device tree compiler to compile a .dts file
 
     The output file will be the same as the input file but with a .dtb
@@ -55,31 +55,31 @@ def dtc(dts, cons, dtc_args, datadir, tmpdir, dtb):
 
     Args:
         dts: Device tree file to compile.
-        cons: U-Boot console.
+        ubman: U-Boot console.
         dtc_args: DTC arguments.
         datadir: Path to data directory.
         tmpdir: Path to temp directory.
         dtb: Resulting DTB file.
     """
     dtb = dts.replace('.dts', '.dtb')
-    util.run_and_log(cons, 'dtc %s %s%s -O dtb '
-                     '-o %s%s' % (dtc_args, datadir, dts, tmpdir, dtb))
+    utils.run_and_log(ubman, 'dtc %s %s%s -O dtb '
+                      '-o %s%s' % (dtc_args, datadir, dts, tmpdir, dtb))
 
-def make_fit(its, cons, mkimage, dtc_args, datadir, fit):
+def make_fit(its, ubman, mkimage, dtc_args, datadir, fit):
     """Make a new FIT from the .its source file.
 
     This runs 'mkimage -f' to create a new FIT.
 
     Args:
         its: Filename containing .its source.
-        cons: U-Boot console.
+        ubman: U-Boot console.
         mkimage: Path to mkimage utility.
         dtc_args: DTC arguments.
         datadir: Path to data directory.
         fit: Resulting FIT file.
     """
-    util.run_and_log(cons, [mkimage, '-D', dtc_args, '-f',
-                            '%s%s' % (datadir, its), fit])
+    utils.run_and_log(ubman, [mkimage, '-D', dtc_args, '-f',
+                             '%s%s' % (datadir, its), fit])
 
 # Only run the full suite on a few combinations, since it doesn't add any more
 # test coverage.
@@ -113,7 +113,7 @@ TESTDATA += [pytest.param(*v, marks=pytest.mark.slow) for v in TESTDATA_IN[1:]]
 @pytest.mark.requiredtool('openssl')
 @pytest.mark.parametrize("name,sha_algo,padding,sign_options,required,full_test,algo_arg,global_sign",
                          TESTDATA)
-def test_vboot(u_boot_console, name, sha_algo, padding, sign_options, required,
+def test_vboot(ubman, name, sha_algo, padding, sign_options, required,
                full_test, algo_arg, global_sign):
     """Test verified boot signing with mkimage and verification with 'bootm'.
 
@@ -134,8 +134,8 @@ def test_vboot(u_boot_console, name, sha_algo, padding, sign_options, required,
             options: Options provided to the compiler.
         """
         dtb = dts.replace('.dts', '.dtb')
-        util.run_and_log(cons, 'dtc %s %s%s -O dtb '
-                         '-o %s%s %s' % (dtc_args, datadir, dts, tmpdir, dtb, options))
+        utils.run_and_log(ubman, 'dtc %s %s%s -O dtb -o %s%s %s' %
+                          (dtc_args, datadir, dts, tmpdir, dtb, options))
 
     def run_binman(dtb):
         """Run binman to build an image
@@ -145,9 +145,9 @@ def test_vboot(u_boot_console, name, sha_algo, padding, sign_options, required,
         """
         pythonpath = os.environ.get('PYTHONPATH', '')
         os.environ['PYTHONPATH'] = pythonpath + ':' + '%s/../scripts/dtc/pylibfdt' % tmpdir
-        util.run_and_log(cons, [binman, 'build', '-d', "%s/%s" % (tmpdir,dtb),
-                                '-a', "pre-load-key-path=%s" % tmpdir, '-O',
-                                tmpdir, '-I', tmpdir])
+        utils.run_and_log(ubman, [binman, 'build', '-d', "%s/%s" % (tmpdir,dtb),
+                                 '-a', "pre-load-key-path=%s" % tmpdir, '-O',
+                                 tmpdir, '-I', tmpdir])
         os.environ['PYTHONPATH'] = pythonpath
 
     def run_bootm(sha_algo, test_type, expect_string, boots, fit=None):
@@ -167,9 +167,9 @@ def test_vboot(u_boot_console, name, sha_algo, padding, sign_options, required,
         """
         if not fit:
             fit = '%stest.fit' % tmpdir
-        cons.restart_uboot()
-        with cons.log.section('Verified boot %s %s' % (sha_algo, test_type)):
-            output = cons.run_command_list(
+        ubman.restart_uboot()
+        with ubman.log.section('Verified boot %s %s' % (sha_algo, test_type)):
+            output = ubman.run_command_list(
                 ['host load hostfs - 100 %s' % fit,
                  'fdt addr 100',
                  'bootm 100'])
@@ -194,8 +194,8 @@ def test_vboot(u_boot_console, name, sha_algo, padding, sign_options, required,
         args = [mkimage, '-F', '-k', tmpdir, '-K', dtb, '-r', fit]
         if options:
             args += options.split(' ')
-        cons.log.action('%s: Sign images' % sha_algo)
-        util.run_and_log(cons, args)
+        ubman.log.action('%s: Sign images' % sha_algo)
+        utils.run_and_log(ubman, args)
 
     def sign_fit_dtb(sha_algo, options, dtb):
         """Sign the FIT
@@ -211,8 +211,8 @@ def test_vboot(u_boot_console, name, sha_algo, padding, sign_options, required,
         args = [mkimage, '-F', '-k', tmpdir, '-K', dtb, '-r', fit]
         if options:
             args += options.split(' ')
-        cons.log.action('%s: Sign images' % sha_algo)
-        util.run_and_log(cons, args)
+        ubman.log.action('%s: Sign images' % sha_algo)
+        utils.run_and_log(ubman, args)
 
     def sign_fit_norequire(sha_algo, options):
         """Sign the FIT
@@ -228,8 +228,8 @@ def test_vboot(u_boot_console, name, sha_algo, padding, sign_options, required,
         args = [mkimage, '-F', '-k', tmpdir, '-K', dtb, fit]
         if options:
             args += options.split(' ')
-        cons.log.action('%s: Sign images' % sha_algo)
-        util.run_and_log(cons, args)
+        ubman.log.action('%s: Sign images' % sha_algo)
+        utils.run_and_log(ubman, args)
 
     def replace_fit_totalsize(size):
         """Replace FIT header's totalsize with something greater.
@@ -278,14 +278,14 @@ def test_vboot(u_boot_console, name, sha_algo, padding, sign_options, required,
         else:
             rsa_keygen_bits = 2048
 
-        util.run_and_log(cons, 'openssl genpkey -algorithm RSA -out %s%s.key '
+        utils.run_and_log(ubman, 'openssl genpkey -algorithm RSA -out %s%s.key '
                      '-pkeyopt rsa_keygen_bits:%d '
                      '-pkeyopt rsa_keygen_pubexp:%d' %
                      (tmpdir, name, rsa_keygen_bits, public_exponent))
 
         # Create a certificate containing the public key
-        util.run_and_log(cons, 'openssl req -batch -new -x509 -key %s%s.key '
-                         '-out %s%s.crt' % (tmpdir, name, tmpdir, name))
+        utils.run_and_log(ubman, 'openssl req -batch -new -x509 -key %s%s.key '
+                          '-out %s%s.crt' % (tmpdir, name, tmpdir, name))
 
     def test_with_algo(sha_algo, padding, sign_options):
         """Test verified boot with the given hash algorithm.
@@ -303,12 +303,12 @@ def test_vboot(u_boot_console, name, sha_algo, padding, sign_options, required,
         # Compile our device tree files for kernel and U-Boot. These are
         # regenerated here since mkimage will modify them (by adding a
         # public key) below.
-        dtc('sandbox-kernel.dts', cons, dtc_args, datadir, tmpdir, dtb)
-        dtc('sandbox-u-boot.dts', cons, dtc_args, datadir, tmpdir, dtb)
+        dtc('sandbox-kernel.dts', ubman, dtc_args, datadir, tmpdir, dtb)
+        dtc('sandbox-u-boot.dts', ubman, dtc_args, datadir, tmpdir, dtb)
 
         # Build the FIT, but don't sign anything yet
-        cons.log.action('%s: Test FIT with signed images' % sha_algo)
-        make_fit('sign-images-%s%s.its' % (sha_algo, padding), cons, mkimage, dtc_args, datadir, fit)
+        ubman.log.action('%s: Test FIT with signed images' % sha_algo)
+        make_fit('sign-images-%s%s.its' % (sha_algo, padding), ubman, mkimage, dtc_args, datadir, fit)
         run_bootm(sha_algo, 'unsigned images', ' - OK' if algo_arg else 'dev-', True)
 
         # Sign images with our dev keys
@@ -316,19 +316,19 @@ def test_vboot(u_boot_console, name, sha_algo, padding, sign_options, required,
         run_bootm(sha_algo, 'signed images', 'dev+', True)
 
         # Create a fresh .dtb without the public keys
-        dtc('sandbox-u-boot.dts', cons, dtc_args, datadir, tmpdir, dtb)
+        dtc('sandbox-u-boot.dts', ubman, dtc_args, datadir, tmpdir, dtb)
 
-        cons.log.action('%s: Test FIT with signed configuration' % sha_algo)
-        make_fit('sign-configs-%s%s.its' % (sha_algo, padding), cons, mkimage, dtc_args, datadir, fit)
+        ubman.log.action('%s: Test FIT with signed configuration' % sha_algo)
+        make_fit('sign-configs-%s%s.its' % (sha_algo, padding), ubman, mkimage, dtc_args, datadir, fit)
         run_bootm(sha_algo, 'unsigned config', '%s+ OK' % ('sha256' if algo_arg else sha_algo), True)
 
         # Sign images with our dev keys
         sign_fit(sha_algo, sign_options)
         run_bootm(sha_algo, 'signed config', 'dev+', True)
 
-        cons.log.action('%s: Check signed config on the host' % sha_algo)
+        ubman.log.action('%s: Check signed config on the host' % sha_algo)
 
-        util.run_and_log(cons, [fit_check_sign, '-f', fit, '-k', dtb])
+        utils.run_and_log(ubman, [fit_check_sign, '-f', fit, '-k', dtb])
 
         if full_test:
             # Make sure that U-Boot checks that the config is in the list of
@@ -340,8 +340,8 @@ def test_vboot(u_boot_console, name, sha_algo, padding, sign_options, required,
             root, strblock = vboot_forge.manipulate(root, strblock)
             with open(ffit, 'w+b') as fd:
                 vboot_forge.write_fdt(root, strblock, fd)
-            util.run_and_log_expect_exception(
-                cons, [fit_check_sign, '-f', ffit, '-k', dtb],
+            utils.run_and_log_expect_exception(
+                ubman, [fit_check_sign, '-f', ffit, '-k', dtb],
                 1, 'Failed to verify required signature')
 
             run_bootm(sha_algo, 'forged config', 'Bad Data Hash', False, ffit)
@@ -351,8 +351,8 @@ def test_vboot(u_boot_console, name, sha_algo, padding, sign_options, required,
             shutil.copyfile(fit, efit)
             vboot_evil.add_evil_node(fit, efit, evil_kernel, 'fakeroot')
 
-            util.run_and_log_expect_exception(
-                cons, [fit_check_sign, '-f', efit, '-k', dtb],
+            utils.run_and_log_expect_exception(
+                ubman, [fit_check_sign, '-f', efit, '-k', dtb],
                 1, 'Failed to verify required signature')
             run_bootm(sha_algo, 'evil fakeroot', 'Bad FIT kernel image format',
                       False, efit)
@@ -363,42 +363,42 @@ def test_vboot(u_boot_console, name, sha_algo, padding, sign_options, required,
             vboot_evil.add_evil_node(fit, efit, evil_kernel, 'kernel@')
 
             msg = 'Signature checking prevents use of unit addresses (@) in nodes'
-            util.run_and_log_expect_exception(
-                cons, [fit_check_sign, '-f', efit, '-k', dtb],
+            utils.run_and_log_expect_exception(
+                ubman, [fit_check_sign, '-f', efit, '-k', dtb],
                 1, msg)
             run_bootm(sha_algo, 'evil kernel@', msg, False, efit)
 
         # Create a new properly signed fit and replace header bytes
-        make_fit('sign-configs-%s%s.its' % (sha_algo, padding), cons, mkimage, dtc_args, datadir, fit)
+        make_fit('sign-configs-%s%s.its' % (sha_algo, padding), ubman, mkimage, dtc_args, datadir, fit)
         sign_fit(sha_algo, sign_options)
-        bcfg = u_boot_console.config.buildconfig
+        bcfg = ubman.config.buildconfig
         max_size = int(bcfg.get('config_fit_signature_max_size', 0x10000000), 0)
         existing_size = replace_fit_totalsize(max_size + 1)
         run_bootm(sha_algo, 'Signed config with bad hash', 'Bad Data Hash',
                   False)
-        cons.log.action('%s: Check overflowed FIT header totalsize' % sha_algo)
+        ubman.log.action('%s: Check overflowed FIT header totalsize' % sha_algo)
 
         # Replace with existing header bytes
         replace_fit_totalsize(existing_size)
         run_bootm(sha_algo, 'signed config', 'dev+', True)
-        cons.log.action('%s: Check default FIT header totalsize' % sha_algo)
+        ubman.log.action('%s: Check default FIT header totalsize' % sha_algo)
 
         # Increment the first byte of the signature, which should cause failure
-        sig = util.run_and_log(cons, 'fdtget -t bx %s %s value' %
-                               (fit, sig_node))
+        sig = utils.run_and_log(ubman, 'fdtget -t bx %s %s value' %
+                                (fit, sig_node))
         byte_list = sig.split()
         byte = int(byte_list[0], 16)
         byte_list[0] = '%x' % (byte + 1)
         sig = ' '.join(byte_list)
-        util.run_and_log(cons, 'fdtput -t bx %s %s value %s' %
-                         (fit, sig_node, sig))
+        utils.run_and_log(ubman, 'fdtput -t bx %s %s value %s' %
+                          (fit, sig_node, sig))
 
         run_bootm(sha_algo, 'Signed config with bad hash', 'Bad Data Hash',
                   False)
 
-        cons.log.action('%s: Check bad config on the host' % sha_algo)
-        util.run_and_log_expect_exception(
-            cons, [fit_check_sign, '-f', fit, '-k', dtb],
+        ubman.log.action('%s: Check bad config on the host' % sha_algo)
+        utils.run_and_log_expect_exception(
+            ubman, [fit_check_sign, '-f', fit, '-k', dtb],
             1, 'Failed to verify required signature')
 
     def test_required_key(sha_algo, padding, sign_options):
@@ -416,19 +416,19 @@ def test_vboot(u_boot_console, name, sha_algo, padding, sign_options, required,
         # Compile our device tree files for kernel and U-Boot. These are
         # regenerated here since mkimage will modify them (by adding a
         # public key) below.
-        dtc('sandbox-kernel.dts', cons, dtc_args, datadir, tmpdir, dtb)
-        dtc('sandbox-u-boot.dts', cons, dtc_args, datadir, tmpdir, dtb)
+        dtc('sandbox-kernel.dts', ubman, dtc_args, datadir, tmpdir, dtb)
+        dtc('sandbox-u-boot.dts', ubman, dtc_args, datadir, tmpdir, dtb)
 
-        cons.log.action('%s: Test FIT with configs images' % sha_algo)
+        ubman.log.action('%s: Test FIT with configs images' % sha_algo)
 
         # Build the FIT with prod key (keys required) and sign it. This puts the
         # signature into sandbox-u-boot.dtb, marked 'required'
-        make_fit('sign-configs-%s%s-prod.its' % (sha_algo, padding), cons, mkimage, dtc_args, datadir, fit)
+        make_fit('sign-configs-%s%s-prod.its' % (sha_algo, padding), ubman, mkimage, dtc_args, datadir, fit)
         sign_fit(sha_algo, sign_options)
 
         # Build the FIT with dev key (keys NOT required). This adds the
         # signature into sandbox-u-boot.dtb, NOT marked 'required'.
-        make_fit('sign-configs-%s%s.its' % (sha_algo, padding), cons, mkimage, dtc_args, datadir, fit)
+        make_fit('sign-configs-%s%s.its' % (sha_algo, padding), ubman, mkimage, dtc_args, datadir, fit)
         sign_fit_norequire(sha_algo, sign_options)
 
         # So now sandbox-u-boot.dtb two signatures, for the prod and dev keys.
@@ -440,7 +440,7 @@ def test_vboot(u_boot_console, name, sha_algo, padding, sign_options, required,
 
         # Build the FIT with dev key (keys required) and sign it. This puts the
         # signature into sandbox-u-boot.dtb, marked 'required'.
-        make_fit('sign-configs-%s%s.its' % (sha_algo, padding), cons, mkimage, dtc_args, datadir, fit)
+        make_fit('sign-configs-%s%s.its' % (sha_algo, padding), ubman, mkimage, dtc_args, datadir, fit)
         sign_fit(sha_algo, sign_options)
 
         # Set the required-mode policy to "any".
@@ -449,8 +449,8 @@ def test_vboot(u_boot_console, name, sha_algo, padding, sign_options, required,
         # a dev signature only (sign_fit() overwrites the FIT).
         # Try to boot the FIT with dev key. This FIT should be accepted by
         # U-Boot because the dev key is required and policy is "any" required key.
-        util.run_and_log(cons, 'fdtput -t s %s /signature required-mode any' %
-                         (dtb))
+        utils.run_and_log(ubman, 'fdtput -t s %s /signature required-mode any' %
+                          dtb)
         run_bootm(sha_algo, 'multi required key', 'dev+', True)
 
         # Set the required-mode policy to "all".
@@ -459,8 +459,8 @@ def test_vboot(u_boot_console, name, sha_algo, padding, sign_options, required,
         # a dev signature only (sign_fit() overwrites the FIT).
         # Try to boot the FIT with dev key. This FIT should not be accepted by
         # U-Boot because the prod key is required and policy is "all" required key
-        util.run_and_log(cons, 'fdtput -t s %s /signature required-mode all' %
-                         (dtb))
+        utils.run_and_log(ubman, 'fdtput -t s %s /signature required-mode all' %
+                          dtb)
         run_bootm(sha_algo, 'multi required key', '', False)
 
     def test_global_sign(sha_algo, padding, sign_options):
@@ -473,22 +473,22 @@ def test_vboot(u_boot_console, name, sha_algo, padding, sign_options, required,
         """
 
         dtb = '%ssandbox-u-boot-global%s.dtb' % (tmpdir, padding)
-        cons.config.dtb = dtb
+        ubman.config.dtb = dtb
 
         # Compile our device tree files for kernel and U-Boot. These are
         # regenerated here since mkimage will modify them (by adding a
         # public key) below.
-        dtc('sandbox-kernel.dts', cons, dtc_args, datadir, tmpdir, dtb)
+        dtc('sandbox-kernel.dts', ubman, dtc_args, datadir, tmpdir, dtb)
         dtc_options('sandbox-u-boot-global%s.dts' % padding, '-p 1024')
 
         # Build the FIT with dev key (keys NOT required). This adds the
         # signature into sandbox-u-boot.dtb, NOT marked 'required'.
-        make_fit('simple-images.its', cons, mkimage, dtc_args, datadir, fit)
+        make_fit('simple-images.its', ubman, mkimage, dtc_args, datadir, fit)
         sign_fit_dtb(sha_algo, '', dtb)
 
         # Build the dtb for binman that define the pre-load header
         # with the global sigature.
-        dtc('sandbox-binman%s.dts' % padding, cons, dtc_args, datadir, tmpdir, dtb)
+        dtc('sandbox-binman%s.dts' % padding, ubman, dtc_args, datadir, tmpdir, dtb)
 
         # Run binman to create the final image with the not signed fit
         # and the pre-load header that contains the global signature.
@@ -508,15 +508,14 @@ def test_vboot(u_boot_console, name, sha_algo, padding, sign_options, required,
         # Check that the boot fails if the global signature is not provided
         run_bootm(sha_algo, 'global image signature', 'signature is mandatory', False)
 
-    cons = u_boot_console
-    tmpdir = os.path.join(cons.config.result_dir, name) + '/'
+    tmpdir = os.path.join(ubman.config.result_dir, name) + '/'
     if not os.path.exists(tmpdir):
         os.mkdir(tmpdir)
-    datadir = cons.config.source_dir + '/test/py/tests/vboot/'
+    datadir = ubman.config.source_dir + '/test/py/tests/vboot/'
     fit = '%stest.fit' % tmpdir
-    mkimage = cons.config.build_dir + '/tools/mkimage'
-    binman = cons.config.source_dir + '/tools/binman/binman'
-    fit_check_sign = cons.config.build_dir + '/tools/fit_check_sign'
+    mkimage = ubman.config.build_dir + '/tools/mkimage'
+    binman = ubman.config.source_dir + '/tools/binman/binman'
+    fit_check_sign = ubman.config.build_dir + '/tools/fit_check_sign'
     dtc_args = '-I dts -O dtb -i %s' % tmpdir
     dtb = '%ssandbox-u-boot.dtb' % tmpdir
     sig_node = '/configurations/conf-1/signature'
@@ -535,9 +534,9 @@ def test_vboot(u_boot_console, name, sha_algo, padding, sign_options, required,
 
     # We need to use our own device tree file. Remember to restore it
     # afterwards.
-    old_dtb = cons.config.dtb
+    old_dtb = ubman.config.dtb
     try:
-        cons.config.dtb = dtb
+        ubman.config.dtb = dtb
         if global_sign:
             test_global_sign(sha_algo, padding, sign_options)
         elif required:
@@ -546,8 +545,8 @@ def test_vboot(u_boot_console, name, sha_algo, padding, sign_options, required,
             test_with_algo(sha_algo, padding, sign_options)
     finally:
         # Go back to the original U-Boot with the correct dtb.
-        cons.config.dtb = old_dtb
-        cons.restart_uboot()
+        ubman.config.dtb = old_dtb
+        ubman.restart_uboot()
 
 
 TESTDATA_IN = [
@@ -577,7 +576,7 @@ TESTDATA += [pytest.param(*v, marks=pytest.mark.slow) for v in TESTDATA_IN[1:]]
 @pytest.mark.requiredtool('dtc')
 @pytest.mark.requiredtool('openssl')
 @pytest.mark.parametrize("name,sha_algo,padding,sign_options,algo_arg", TESTDATA)
-def test_fdt_add_pubkey(u_boot_console, name, sha_algo, padding, sign_options, algo_arg):
+def test_fdt_add_pubkey(ubman, name, sha_algo, padding, sign_options, algo_arg):
     """Test fdt_add_pubkey utility with bunch of different algo options."""
 
     def sign_fit(sha_algo, options):
@@ -593,8 +592,8 @@ def test_fdt_add_pubkey(u_boot_console, name, sha_algo, padding, sign_options, a
         args = [mkimage, '-F', '-k', tmpdir, fit]
         if options:
             args += options.split(' ')
-        cons.log.action('%s: Sign images' % sha_algo)
-        util.run_and_log(cons, args)
+        ubman.log.action('%s: Sign images' % sha_algo)
+        utils.run_and_log(ubman, args)
 
     def test_add_pubkey(sha_algo, padding, sign_options):
         """Test fdt_add_pubkey utility with given hash algorithm and padding.
@@ -609,32 +608,33 @@ def test_fdt_add_pubkey(u_boot_console, name, sha_algo, padding, sign_options, a
         """
 
         # Create a fresh .dtb without the public keys
-        dtc('sandbox-u-boot.dts', cons, dtc_args, datadir, tmpdir, dtb)
+        dtc('sandbox-u-boot.dts', ubman, dtc_args, datadir, tmpdir, dtb)
 
-        cons.log.action('%s: Test fdt_add_pubkey with signed configuration' % sha_algo)
+        ubman.log.action('%s: Test fdt_add_pubkey with signed configuration' % sha_algo)
         # Then add the dev key via the fdt_add_pubkey tool
-        util.run_and_log(cons, [fdt_add_pubkey, '-a', '%s,%s' % ('sha256' if algo_arg else sha_algo, \
-                                'rsa3072' if sha_algo == 'sha384' else 'rsa2048'),
-                                '-k', tmpdir, '-n', 'dev', '-r', 'conf', dtb])
+        utils.run_and_log(ubman,
+                          [fdt_add_pubkey, '-a', '%s,%s' %
+                           ('sha256' if algo_arg else sha_algo,
+                            'rsa3072' if sha_algo == 'sha384' else 'rsa2048'),
+                           '-k', tmpdir, '-n', 'dev', '-r', 'conf', dtb])
 
-        make_fit('sign-configs-%s%s.its' % (sha_algo, padding), cons, mkimage, dtc_args, datadir, fit)
+        make_fit('sign-configs-%s%s.its' % (sha_algo, padding), ubman, mkimage, dtc_args, datadir, fit)
 
         # Sign images with our dev keys
         sign_fit(sha_algo, sign_options)
 
         # Check with fit_check_sign that FIT is signed with key
-        util.run_and_log(cons, [fit_check_sign, '-f', fit, '-k', dtb])
+        utils.run_and_log(ubman, [fit_check_sign, '-f', fit, '-k', dtb])
 
-    cons = u_boot_console
-    tmpdir = os.path.join(cons.config.result_dir, name) + '/'
+    tmpdir = os.path.join(ubman.config.result_dir, name) + '/'
     if not os.path.exists(tmpdir):
         os.mkdir(tmpdir)
-    datadir = cons.config.source_dir + '/test/py/tests/vboot/'
+    datadir = ubman.config.source_dir + '/test/py/tests/vboot/'
     fit = '%stest.fit' % tmpdir
-    mkimage = cons.config.build_dir + '/tools/mkimage'
-    binman = cons.config.source_dir + '/tools/binman/binman'
-    fit_check_sign = cons.config.build_dir + '/tools/fit_check_sign'
-    fdt_add_pubkey = cons.config.build_dir + '/tools/fdt_add_pubkey'
+    mkimage = ubman.config.build_dir + '/tools/mkimage'
+    binman = ubman.config.source_dir + '/tools/binman/binman'
+    fit_check_sign = ubman.config.build_dir + '/tools/fit_check_sign'
+    fdt_add_pubkey = ubman.config.build_dir + '/tools/fdt_add_pubkey'
     dtc_args = '-I dts -O dtb -i %s' % tmpdir
     dtb = '%ssandbox-u-boot.dtb' % tmpdir
 
diff --git a/test/py/tests/test_vpl.py b/test/py/tests/test_vpl.py
index 8c472ca7a92..a269c7c262e 100644
--- a/test/py/tests/test_vpl.py
+++ b/test/py/tests/test_vpl.py
@@ -5,7 +5,7 @@
 import os.path
 import pytest
 
-def test_vpl(u_boot_console, ut_vpl_subtest):
+def test_vpl(ubman, ut_vpl_subtest):
     """Execute a "ut" subtest.
 
     The subtests are collected in function generate_ut_subtest() from linker
@@ -19,16 +19,15 @@ def test_vpl(u_boot_console, ut_vpl_subtest):
     implemented in C function foo_test_bar().
 
     Args:
-        u_boot_console (ConsoleBase): U-Boot console
+        ubman (ConsoleBase): U-Boot console
         ut_subtest (str): VPL test to be executed (e.g. 'dm platdata_phandle')
     """
     try:
-        cons = u_boot_console
-        cons.restart_uboot_with_flags(['-u', '-k', ut_vpl_subtest.split()[1]])
-        output = cons.get_spawn_output().replace('\r', '')
+        ubman.restart_uboot_with_flags(['-u', '-k', ut_vpl_subtest.split()[1]])
+        output = ubman.get_spawn_output().replace('\r', '')
         assert 'failures: 0' in output
     finally:
         # Restart afterward in case a non-VPL test is run next. This should not
         # happen since VPL tests are run in their own invocation of test.py, but
         # the cost of doing this is not too great at present.
-        u_boot_console.restart_uboot()
+        ubman.restart_uboot()
diff --git a/test/py/tests/test_xxd/test_xxd.py b/test/py/tests/test_xxd/test_xxd.py
index 06b9cfc0003..c04bf8b7a25 100644
--- a/test/py/tests/test_xxd/test_xxd.py
+++ b/test/py/tests/test_xxd/test_xxd.py
@@ -7,14 +7,14 @@ import pytest
 
 @pytest.mark.boardspec('sandbox')
 @pytest.mark.buildconfigspec('cmd_xxd')
-def test_xxd(u_boot_console, xxd_data):
+def test_xxd(ubman, xxd_data):
     """ Unit test for xxd
 
     Args:
-        u_boot_console -- U-Boot console
+        ubman -- U-Boot console
         xxd_data -- Path to the disk image used for testing.
     """
-    response = u_boot_console.run_command_list([
+    response = ubman.run_command_list([
         f'host bind 0 {xxd_data}',
         'xxd host 0 hello'])
 
diff --git a/test/py/tests/test_zynq_secure.py b/test/py/tests/test_zynq_secure.py
index 0ee5aebc484..f066a03b182 100644
--- a/test/py/tests/test_zynq_secure.py
+++ b/test/py/tests/test_zynq_secure.py
@@ -3,7 +3,7 @@
 
 import pytest
 import re
-import u_boot_utils
+import utils
 import test_net
 
 """
@@ -36,8 +36,8 @@ env__zynq_rsa_readable_file = {
 }
 """
 
-def zynq_secure_pre_commands(u_boot_console):
-    output = u_boot_console.run_command('print modeboot')
+def zynq_secure_pre_commands(ubman):
+    output = ubman.run_command('print modeboot')
     if not 'modeboot=' in output:
         pytest.skip('bootmode cannnot be determined')
     m = re.search('modeboot=(.+?)boot', output)
@@ -48,8 +48,8 @@ def zynq_secure_pre_commands(u_boot_console):
         pytest.skip('skipping due to jtag bootmode')
 
 @pytest.mark.buildconfigspec('cmd_zynq_aes')
-def test_zynq_aes_image(u_boot_console):
-    f = u_boot_console.config.env.get('env__zynq_aes_readable_file', None)
+def test_zynq_aes_image(ubman):
+    f = ubman.config.env.get('env__zynq_aes_readable_file', None)
     if not f:
         pytest.skip('No TFTP readable file for zynq secure aes case to read')
 
@@ -61,130 +61,130 @@ def test_zynq_aes_image(u_boot_console):
     if not dstsize:
         pytest.skip('No dstlen specified in env file to read')
 
-    zynq_secure_pre_commands(u_boot_console)
-    test_net.test_net_dhcp(u_boot_console)
+    zynq_secure_pre_commands(ubman)
+    test_net.test_net_dhcp(ubman)
     if not test_net.net_set_up:
-        test_net.test_net_setup_static(u_boot_console)
+        test_net.test_net_setup_static(ubman)
 
     srcaddr = f.get('srcaddr', None)
     if not srcaddr:
-        addr = u_boot_utils.find_ram_base(u_boot_console)
+        addr = utils.find_ram_base(ubman)
 
     expected_tftp = 'Bytes transferred = '
     fn = f['fn']
-    output = u_boot_console.run_command('tftpboot %x %s' % (srcaddr, fn))
+    output = ubman.run_command('tftpboot %x %s' % (srcaddr, fn))
     assert expected_tftp in output
 
     expected_op = 'zynq aes [operation type] <srcaddr>'
-    output = u_boot_console.run_command(
+    output = ubman.run_command(
         'zynq aes %x $filesize %x %x' % (srcaddr, dstaddr, dstsize)
     )
     assert expected_op not in output
-    output = u_boot_console.run_command('echo $?')
+    output = ubman.run_command('echo $?')
     assert output.endswith('0')
 
 @pytest.mark.buildconfigspec('cmd_zynq_aes')
-def test_zynq_aes_bitstream(u_boot_console):
-    f = u_boot_console.config.env.get('env__zynq_aes_readable_file', None)
+def test_zynq_aes_bitstream(ubman):
+    f = ubman.config.env.get('env__zynq_aes_readable_file', None)
     if not f:
         pytest.skip('No TFTP readable file for zynq secure aes case to read')
 
-    zynq_secure_pre_commands(u_boot_console)
-    test_net.test_net_dhcp(u_boot_console)
+    zynq_secure_pre_commands(ubman)
+    test_net.test_net_dhcp(ubman)
     if not test_net.net_set_up:
-        test_net.test_net_setup_static(u_boot_console)
+        test_net.test_net_setup_static(ubman)
 
     srcaddr = f.get('srcaddr', None)
     if not srcaddr:
-        addr = u_boot_utils.find_ram_base(u_boot_console)
+        addr = utils.find_ram_base(ubman)
 
     expected_tftp = 'Bytes transferred = '
     fn = f['fnbit']
-    output = u_boot_console.run_command('tftpboot %x %s' % (srcaddr, fn))
+    output = ubman.run_command('tftpboot %x %s' % (srcaddr, fn))
     assert expected_tftp in output
 
     expected_op = 'zynq aes [operation type] <srcaddr>'
-    output = u_boot_console.run_command(
+    output = ubman.run_command(
         'zynq aes load %x $filesize' % (srcaddr)
     )
     assert expected_op not in output
-    output = u_boot_console.run_command('echo $?')
+    output = ubman.run_command('echo $?')
     assert output.endswith('0')
 
 @pytest.mark.buildconfigspec('cmd_zynq_aes')
-def test_zynq_aes_partial_bitstream(u_boot_console):
-    f = u_boot_console.config.env.get('env__zynq_aes_readable_file', None)
+def test_zynq_aes_partial_bitstream(ubman):
+    f = ubman.config.env.get('env__zynq_aes_readable_file', None)
     if not f:
         pytest.skip('No TFTP readable file for zynq secure aes case to read')
 
-    zynq_secure_pre_commands(u_boot_console)
-    test_net.test_net_dhcp(u_boot_console)
+    zynq_secure_pre_commands(ubman)
+    test_net.test_net_dhcp(ubman)
     if not test_net.net_set_up:
-        test_net.test_net_setup_static(u_boot_console)
+        test_net.test_net_setup_static(ubman)
 
     srcaddr = f.get('srcaddr', None)
     if not srcaddr:
-        addr = u_boot_utils.find_ram_base(u_boot_console)
+        addr = utils.find_ram_base(ubman)
 
     expected_tftp = 'Bytes transferred = '
     fn = f['fnpbit']
-    output = u_boot_console.run_command('tftpboot %x %s' % (srcaddr, fn))
+    output = ubman.run_command('tftpboot %x %s' % (srcaddr, fn))
     assert expected_tftp in output
 
     expected_op = 'zynq aes [operation type] <srcaddr>'
-    output = u_boot_console.run_command('zynq aes loadp %x $filesize' % (srcaddr))
+    output = ubman.run_command('zynq aes loadp %x $filesize' % (srcaddr))
     assert expected_op not in output
-    output = u_boot_console.run_command('echo $?')
+    output = ubman.run_command('echo $?')
     assert output.endswith('0')
 
 @pytest.mark.buildconfigspec('cmd_zynq_rsa')
-def test_zynq_rsa_image(u_boot_console):
-    f = u_boot_console.config.env.get('env__zynq_rsa_readable_file', None)
+def test_zynq_rsa_image(ubman):
+    f = ubman.config.env.get('env__zynq_rsa_readable_file', None)
     if not f:
         pytest.skip('No TFTP readable file for zynq secure rsa case to read')
 
-    zynq_secure_pre_commands(u_boot_console)
-    test_net.test_net_dhcp(u_boot_console)
+    zynq_secure_pre_commands(ubman)
+    test_net.test_net_dhcp(ubman)
     if not test_net.net_set_up:
-        test_net.test_net_setup_static(u_boot_console)
+        test_net.test_net_setup_static(ubman)
 
     srcaddr = f.get('srcaddr', None)
     if not srcaddr:
-        addr = u_boot_utils.find_ram_base(u_boot_console)
+        addr = utils.find_ram_base(ubman)
 
     expected_tftp = 'Bytes transferred = '
     fn = f['fn']
-    output = u_boot_console.run_command('tftpboot %x %s' % (srcaddr, fn))
+    output = ubman.run_command('tftpboot %x %s' % (srcaddr, fn))
     assert expected_tftp in output
 
     expected_op = 'zynq rsa <baseaddr>'
-    output = u_boot_console.run_command('zynq rsa %x ' % (srcaddr))
+    output = ubman.run_command('zynq rsa %x ' % (srcaddr))
     assert expected_op not in output
-    output = u_boot_console.run_command('echo $?')
+    output = ubman.run_command('echo $?')
     assert output.endswith('0')
 
 @pytest.mark.buildconfigspec('cmd_zynq_rsa')
-def test_zynq_rsa_image_invalid(u_boot_console):
-    f = u_boot_console.config.env.get('env__zynq_rsa_readable_file', None)
+def test_zynq_rsa_image_invalid(ubman):
+    f = ubman.config.env.get('env__zynq_rsa_readable_file', None)
     if not f:
         pytest.skip('No TFTP readable file for zynq secure rsa case to read')
 
-    zynq_secure_pre_commands(u_boot_console)
-    test_net.test_net_dhcp(u_boot_console)
+    zynq_secure_pre_commands(ubman)
+    test_net.test_net_dhcp(ubman)
     if not test_net.net_set_up:
-        test_net.test_net_setup_static(u_boot_console)
+        test_net.test_net_setup_static(ubman)
 
     srcaddr = f.get('srcaddr', None)
     if not srcaddr:
-        addr = u_boot_utils.find_ram_base(u_boot_console)
+        addr = utils.find_ram_base(ubman)
 
     expected_tftp = 'Bytes transferred = '
     fninvalid = f['fninvalid']
-    output = u_boot_console.run_command('tftpboot %x %s' % (srcaddr, fninvalid))
+    output = ubman.run_command('tftpboot %x %s' % (srcaddr, fninvalid))
     assert expected_tftp in output
 
     expected_op = 'zynq rsa <baseaddr>'
-    output = u_boot_console.run_command('zynq rsa %x ' % (srcaddr))
+    output = ubman.run_command('zynq rsa %x ' % (srcaddr))
     assert expected_op in output
-    output = u_boot_console.run_command('echo $?')
+    output = ubman.run_command('echo $?')
     assert not output.endswith('0')
diff --git a/test/py/tests/test_zynqmp_rpu.py b/test/py/tests/test_zynqmp_rpu.py
index 22f687dd6d3..cda8c9203b7 100644
--- a/test/py/tests/test_zynqmp_rpu.py
+++ b/test/py/tests/test_zynqmp_rpu.py
@@ -33,8 +33,8 @@ env__zynqmp_rpu_apps = {
 """
 
 # Get rpu apps params from env
-def get_rpu_apps_env(u_boot_console):
-    rpu_apps = u_boot_console.config.env.get('env__zynqmp_rpu_apps', False)
+def get_rpu_apps_env(ubman):
+    rpu_apps = ubman.config.env.get('env__zynqmp_rpu_apps', False)
     if not rpu_apps:
         pytest.skip('ZynqMP RPU application info not defined!')
 
@@ -65,29 +65,29 @@ def get_rpu_apps_env(u_boot_console):
     return apps, procs, cpu_nums, addrs, outputs, tftp_addrs
 
 # Check return code
-def ret_code(u_boot_console):
-    return u_boot_console.run_command('echo $?')
+def ret_code(ubman):
+    return ubman.run_command('echo $?')
 
 # Initialize tcm
-def tcminit(u_boot_console, rpu_mode):
-    output = u_boot_console.run_command(f'zynqmp tcminit {rpu_mode}')
+def tcminit(ubman, rpu_mode):
+    output = ubman.run_command(f'zynqmp tcminit {rpu_mode}')
     assert 'Initializing TCM overwrites TCM content' in output
-    return ret_code(u_boot_console)
+    return ret_code(ubman)
 
 # Load application in DDR
-def load_app_ddr(u_boot_console, tftp_addr, app):
-    output = u_boot_console.run_command('tftpboot %x %s' % (tftp_addr, app))
+def load_app_ddr(ubman, tftp_addr, app):
+    output = ubman.run_command('tftpboot %x %s' % (tftp_addr, app))
     assert 'TIMEOUT' not in output
     assert 'Bytes transferred = ' in output
 
     # Load elf
-    u_boot_console.run_command('bootelf -p %x' % tftp_addr)
-    assert ret_code(u_boot_console).endswith('0')
+    ubman.run_command('bootelf -p %x' % tftp_addr)
+    assert ret_code(ubman).endswith('0')
 
 # Disable cpus
-def disable_cpus(u_boot_console, cpu_nums):
+def disable_cpus(ubman, cpu_nums):
     for num in cpu_nums:
-        u_boot_console.run_command(f'cpu {num} disable')
+        ubman.run_command(f'cpu {num} disable')
 
 # Get random RPU mode between string and integer
 def get_rpu_mode(rpu_mode):
@@ -97,47 +97,47 @@ def get_rpu_mode(rpu_mode):
         return random.choice(['split', 1])
 
 # Load apps on RPU cores
-def rpu_apps_load(u_boot_console, rpu_mode):
+def rpu_apps_load(ubman, rpu_mode):
     apps, procs, cpu_nums, addrs, outputs, tftp_addrs = get_rpu_apps_env(
-        u_boot_console)
-    test_net.test_net_dhcp(u_boot_console)
+        ubman)
+    test_net.test_net_dhcp(ubman)
     if not test_net.net_set_up:
-        test_net.test_net_setup_static(u_boot_console)
+        test_net.test_net_setup_static(ubman)
 
     try:
-        assert tcminit(u_boot_console, get_rpu_mode(rpu_mode)).endswith('0')
+        assert tcminit(ubman, get_rpu_mode(rpu_mode)).endswith('0')
 
         for i in range(len(apps)):
             if rpu_mode == 'lockstep' and procs[i] != 'rpu0':
                 continue
 
-            load_app_ddr(u_boot_console, tftp_addrs[i], apps[i])
+            load_app_ddr(ubman, tftp_addrs[i], apps[i])
             rel_addr = hex(int(addrs[i] + 0x3C))
 
             # Release cpu at app load address
             cpu_num = cpu_nums[i]
             cmd = f'cpu {cpu_num} release {rel_addr} {rpu_mode}'
-            output = u_boot_console.run_command(cmd)
+            output = ubman.run_command(cmd)
             exp_op = f'Using TCM jump trampoline for address {rel_addr}'
             assert exp_op in output
             assert f'R5 {rpu_mode} mode' in output
-            u_boot_console.wait_for(outputs[i])
-            assert ret_code(u_boot_console).endswith('0')
+            ubman.wait_for(outputs[i])
+            assert ret_code(ubman).endswith('0')
     finally:
-        disable_cpus(u_boot_console, cpu_nums)
+        disable_cpus(ubman, cpu_nums)
 
 @pytest.mark.buildconfigspec('cmd_zynqmp')
-def test_zynqmp_rpu_app_load_split(u_boot_console):
-    rpu_apps_load(u_boot_console, 'split')
+def test_zynqmp_rpu_app_load_split(ubman):
+    rpu_apps_load(ubman, 'split')
 
 @pytest.mark.buildconfigspec('cmd_zynqmp')
-def test_zynqmp_rpu_app_load_lockstep(u_boot_console):
-    rpu_apps_load(u_boot_console, 'lockstep')
+def test_zynqmp_rpu_app_load_lockstep(ubman):
+    rpu_apps_load(ubman, 'lockstep')
 
 @pytest.mark.buildconfigspec('cmd_zynqmp')
-def test_zynqmp_rpu_app_load_negative(u_boot_console):
+def test_zynqmp_rpu_app_load_negative(ubman):
     apps, procs, cpu_nums, addrs, outputs, tftp_addrs = get_rpu_apps_env(
-        u_boot_console)
+        ubman)
 
     # Invalid commands
     rand_str = ''.join(random.choices(string.ascii_lowercase, k=4))
@@ -145,26 +145,26 @@ def test_zynqmp_rpu_app_load_negative(u_boot_console):
     inv_modes = ['mode', rand_str, rand_num, 'splittt', 'locksteppp', '00', 11]
 
     for mode in inv_modes:
-        u_boot_console.run_command(f'zynqmp tcminit {mode}')
-        assert ret_code(u_boot_console).endswith('1')
+        ubman.run_command(f'zynqmp tcminit {mode}')
+        assert ret_code(ubman).endswith('1')
 
-    test_net.test_net_dhcp(u_boot_console)
+    test_net.test_net_dhcp(ubman)
     if not test_net.net_set_up:
-        test_net.test_net_setup_static(u_boot_console)
+        test_net.test_net_setup_static(ubman)
 
     try:
         rpu_mode = 'split'
-        assert tcminit(u_boot_console, get_rpu_mode(rpu_mode)).endswith('0')
+        assert tcminit(ubman, get_rpu_mode(rpu_mode)).endswith('0')
 
         inv_modes += [0, 1]
         for i in range(len(apps)):
-            load_app_ddr(u_boot_console, tftp_addrs[i], apps[i])
+            load_app_ddr(ubman, tftp_addrs[i], apps[i])
 
             # Run in split mode at different load address
             rel_addr = hex(int(addrs[i]) + random.randint(200, 1000))
             cpu_num = cpu_nums[i]
             cmd = f'cpu {cpu_num} release {rel_addr} {rpu_mode}'
-            output = u_boot_console.run_command(cmd)
+            output = ubman.run_command(cmd)
             exp_op = f'Using TCM jump trampoline for address {rel_addr}'
             assert exp_op in output
             assert f'R5 {rpu_mode} mode' in output
@@ -173,50 +173,50 @@ def test_zynqmp_rpu_app_load_negative(u_boot_console):
             # Invalid rpu mode
             for mode in inv_modes:
                 cmd = f'cpu {cpu_num} release {rel_addr} {mode}'
-                output = u_boot_console.run_command(cmd)
+                output = ubman.run_command(cmd)
                 assert exp_op in output
                 assert f'Unsupported mode' in output
-                assert not ret_code(u_boot_console).endswith('0')
+                assert not ret_code(ubman).endswith('0')
 
         # Switch to lockstep mode, without disabling CPUs
         rpu_mode = 'lockstep'
-        output = u_boot_console.run_command(
+        output = ubman.run_command(
             f'zynqmp tcminit {get_rpu_mode(rpu_mode)}'
         )
         assert 'ERROR: ' in output
 
         # Disable cpus
-        disable_cpus(u_boot_console, cpu_nums)
+        disable_cpus(ubman, cpu_nums)
 
         # Switch to lockstep mode, after disabling CPUs
-        output = u_boot_console.run_command(
+        output = ubman.run_command(
             f'zynqmp tcminit {get_rpu_mode(rpu_mode)}'
         )
         assert 'Initializing TCM overwrites TCM content' in output
-        assert ret_code(u_boot_console).endswith('0')
+        assert ret_code(ubman).endswith('0')
 
         # Run lockstep mode for RPU1/RPU0
         for i in range(len(apps)):
-            load_app_ddr(u_boot_console, tftp_addrs[i], apps[i])
+            load_app_ddr(ubman, tftp_addrs[i], apps[i])
             rel_addr = hex(int(addrs[i] + 0x3C))
             cpu_num = cpu_nums[i]
             cmd = f'cpu {cpu_num} release {rel_addr} {rpu_mode}'
-            output = u_boot_console.run_command(cmd)
+            output = ubman.run_command(cmd)
             exp_op = f'Using TCM jump trampoline for address {rel_addr}'
             assert exp_op in output
 
             if procs[i] == 'rpu1':
                 assert 'Lockstep mode should run on ZYNQMP_CORE_RPU0' in output
-                assert not ret_code(u_boot_console).endswith('0')
+                assert not ret_code(ubman).endswith('0')
             elif procs[i] == 'rpu0':
                 assert f'R5 {rpu_mode} mode' in output
-                u_boot_console.wait_for(outputs[i])
-                assert ret_code(u_boot_console).endswith('0')
+                ubman.wait_for(outputs[i])
+                assert ret_code(ubman).endswith('0')
             else:
                 assert False, 'ERROR: Invalid processor!'
     finally:
-        disable_cpus(u_boot_console, cpu_nums)
+        disable_cpus(ubman, cpu_nums)
         # This forces the console object to be shutdown, so any subsequent test
         # will reset the board back into U-Boot.
-        u_boot_console.drain_console()
-        u_boot_console.cleanup_spawn()
+        ubman.drain_console()
+        ubman.cleanup_spawn()
diff --git a/test/py/tests/test_zynqmp_secure.py b/test/py/tests/test_zynqmp_secure.py
index 570bd2439c1..c057e36383f 100644
--- a/test/py/tests/test_zynqmp_secure.py
+++ b/test/py/tests/test_zynqmp_secure.py
@@ -3,7 +3,7 @@
 
 import pytest
 import re
-import u_boot_utils
+import utils
 import test_net
 
 """
@@ -30,75 +30,75 @@ env__zynqmp_secure_readable_file = {
 """
 
 @pytest.mark.buildconfigspec('cmd_zynqmp')
-def test_zynqmp_secure_boot_image(u_boot_console):
+def test_zynqmp_secure_boot_image(ubman):
     """This test verifies secure boot image at the DDR address for
     authentication only case.
     """
 
-    f = u_boot_console.config.env.get('env__zynqmp_secure_readable_file', None)
+    f = ubman.config.env.get('env__zynqmp_secure_readable_file', None)
     if not f:
         pytest.skip('No TFTP readable file for zynqmp secure cases to read')
 
-    test_net.test_net_dhcp(u_boot_console)
+    test_net.test_net_dhcp(ubman)
     if not test_net.net_set_up:
-        test_net.test_net_setup_static(u_boot_console)
+        test_net.test_net_setup_static(ubman)
 
     addr = f.get('addr', None)
     if not addr:
-        addr = u_boot_utils.find_ram_base(u_boot_console)
+        addr = utils.find_ram_base(ubman)
 
     expected_tftp = 'Bytes transferred = '
     fn = f['fn']
-    output = u_boot_console.run_command('tftpboot %x %s' % (addr, fn))
+    output = ubman.run_command('tftpboot %x %s' % (addr, fn))
     assert expected_tftp in output
 
-    output = u_boot_console.run_command('zynqmp secure %x $filesize' % (addr))
+    output = ubman.run_command('zynqmp secure %x $filesize' % (addr))
     assert 'Verified image at' in output
     ver_addr = re.search(r'Verified image at 0x(.+)', output).group(1)
-    output = u_boot_console.run_command('echo $?')
+    output = ubman.run_command('echo $?')
     assert output.endswith('0')
-    output = u_boot_console.run_command('print zynqmp_verified_img_addr')
+    output = ubman.run_command('print zynqmp_verified_img_addr')
     assert f'zynqmp_verified_img_addr={ver_addr}' in output
     assert 'Error' not in output
 
 
 @pytest.mark.buildconfigspec('cmd_zynqmp')
-def test_zynqmp_secure_boot_img_kup(u_boot_console):
+def test_zynqmp_secure_boot_img_kup(ubman):
     """This test verifies secure boot image at the DDR address for encryption
     with kup key case.
     """
 
-    f = u_boot_console.config.env.get('env__zynqmp_secure_readable_file', None)
+    f = ubman.config.env.get('env__zynqmp_secure_readable_file', None)
     if not f:
         pytest.skip('No TFTP readable file for zynqmp secure cases to read')
 
-    test_net.test_net_dhcp(u_boot_console)
+    test_net.test_net_dhcp(ubman)
     if not test_net.net_set_up:
-        test_net.test_net_setup_static(u_boot_console)
+        test_net.test_net_setup_static(ubman)
 
     keyaddr = f.get('keyaddr', None)
     if not keyaddr:
-        addr = u_boot_utils.find_ram_base(u_boot_console)
+        addr = utils.find_ram_base(ubman)
     expected_tftp = 'Bytes transferred = '
     keyfn = f['keyfn']
-    output = u_boot_console.run_command('tftpboot %x %s' % (keyaddr, keyfn))
+    output = ubman.run_command('tftpboot %x %s' % (keyaddr, keyfn))
     assert expected_tftp in output
 
     addr = f.get('addr', None)
     if not addr:
-        addr = u_boot_utils.find_ram_base(u_boot_console)
+        addr = utils.find_ram_base(ubman)
     expected_tftp = 'Bytes transferred = '
     fn = f['enckupfn']
-    output = u_boot_console.run_command('tftpboot %x %s' % (addr, fn))
+    output = ubman.run_command('tftpboot %x %s' % (addr, fn))
     assert expected_tftp in output
 
-    output = u_boot_console.run_command(
+    output = ubman.run_command(
         'zynqmp secure %x $filesize %x' % (addr, keyaddr)
     )
     assert 'Verified image at' in output
     ver_addr = re.search(r'Verified image at 0x(.+)', output).group(1)
-    output = u_boot_console.run_command('echo $?')
+    output = ubman.run_command('echo $?')
     assert output.endswith('0')
-    output = u_boot_console.run_command('print zynqmp_verified_img_addr')
+    output = ubman.run_command('print zynqmp_verified_img_addr')
     assert f'zynqmp_verified_img_addr={ver_addr}' in output
     assert 'Error' not in output
diff --git a/test/py/u_boot_utils.py b/test/py/utils.py
index 9e161fbc238..ca80e4b0b0a 100644
--- a/test/py/u_boot_utils.py
+++ b/test/py/utils.py
@@ -55,7 +55,7 @@ class PersistentRandomFile:
     """Generate and store information about a persistent file containing
     random data."""
 
-    def __init__(self, u_boot_console, fn, size):
+    def __init__(self, ubman, fn, size):
         """Create or process the persistent file.
 
         If the file does not exist, it is generated.
@@ -66,7 +66,7 @@ class PersistentRandomFile:
         the current test run.
 
         Args:
-            u_boot_console: A console connection to U-Boot.
+            ubman: A console connection to U-Boot.
             fn: The filename (without path) to create.
             size: The desired size of the file in bytes.
 
@@ -76,14 +76,14 @@ class PersistentRandomFile:
 
         self.fn = fn
 
-        self.abs_fn = u_boot_console.config.persistent_data_dir + '/' + fn
+        self.abs_fn = ubman.config.persistent_data_dir + '/' + fn
 
         if os.path.exists(self.abs_fn):
-            u_boot_console.log.action('Persistent data file ' + self.abs_fn +
+            ubman.log.action('Persistent data file ' + self.abs_fn +
                 ' already exists')
             self.content_hash = md5sum_file(self.abs_fn)
         else:
-            u_boot_console.log.action('Generating ' + self.abs_fn +
+            ubman.log.action('Generating ' + self.abs_fn +
                 ' (random, persistent, %d bytes)' % size)
             data = os.urandom(size)
             with open(self.abs_fn, 'wb') as fh:
@@ -157,11 +157,11 @@ def wait_until_file_open_fails(fn, ignore_errors):
         return
     raise Exception('File can still be opened')
 
-def run_and_log(u_boot_console, cmd, ignore_errors=False, stdin=None, env=None):
+def run_and_log(ubman, cmd, ignore_errors=False, stdin=None, env=None):
     """Run a command and log its output.
 
     Args:
-        u_boot_console: A console connection to U-Boot.
+        ubman: A console connection to U-Boot.
         cmd: The command to run, as an array of argv[], or a string.
             If a string, note that it is split up so that quoted spaces
             will not be preserved. E.g. "fred and" becomes ['"fred', 'and"']
@@ -177,25 +177,25 @@ def run_and_log(u_boot_console, cmd, ignore_errors=False, stdin=None, env=None):
     """
     if isinstance(cmd, str):
         cmd = cmd.split()
-    runner = u_boot_console.log.get_runner(cmd[0], sys.stdout)
+    runner = ubman.log.get_runner(cmd[0], sys.stdout)
     output = runner.run(cmd, ignore_errors=ignore_errors, stdin=stdin, env=env)
     runner.close()
     return output
 
-def run_and_log_expect_exception(u_boot_console, cmd, retcode, msg):
+def run_and_log_expect_exception(ubman, cmd, retcode, msg):
     """Run a command that is expected to fail.
 
     This runs a command and checks that it fails with the expected return code
     and exception method. If not, an exception is raised.
 
     Args:
-        u_boot_console: A console connection to U-Boot.
+        ubman: A console connection to U-Boot.
         cmd: The command to run, as an array of argv[].
         retcode: Expected non-zero return code from the command.
         msg: String that should be contained within the command's output.
     """
     try:
-        runner = u_boot_console.log.get_runner(cmd[0], sys.stdout)
+        runner = ubman.log.get_runner(cmd[0], sys.stdout)
         runner.run(cmd)
     except Exception:
         assert retcode == runner.exit_status
@@ -207,7 +207,7 @@ def run_and_log_expect_exception(u_boot_console, cmd, retcode, msg):
         runner.close()
 
 ram_base = None
-def find_ram_base(u_boot_console):
+def find_ram_base(ubman):
     """Find the running U-Boot's RAM location.
 
     Probe the running U-Boot to determine the address of the first bank
@@ -218,22 +218,22 @@ def find_ram_base(u_boot_console):
     actively read once.
 
     Args:
-        u_boot_console: A console connection to U-Boot.
+        ubman: A console connection to U-Boot.
 
     Returns:
         The address of U-Boot's first RAM bank, as an integer.
     """
 
     global ram_base
-    if u_boot_console.config.buildconfig.get('config_cmd_bdi', 'n') != 'y':
+    if ubman.config.buildconfig.get('config_cmd_bdi', 'n') != 'y':
         pytest.skip('bdinfo command not supported')
     if ram_base == -1:
         pytest.skip('Previously failed to find RAM bank start')
     if ram_base is not None:
         return ram_base
 
-    with u_boot_console.log.section('find_ram_base'):
-        response = u_boot_console.run_command('bdinfo')
+    with ubman.log.section('find_ram_base'):
+        response = ubman.run_command('bdinfo')
         for l in response.split('\n'):
             if '-> start' in l or 'memstart    =' in l:
                 ram_base = int(l.split('=')[1].strip(), 16)
@@ -311,11 +311,11 @@ def persistent_file_helper(u_boot_log, filename):
     statement
 
     Usage:
-        with persistent_file_helper(u_boot_console.log, filename):
+        with persistent_file_helper(ubman.log, filename):
             code to generate the file, if it's missing.
 
     Args:
-        u_boot_log: u_boot_console.log.
+        u_boot_log: ubman.log.
         filename: The filename of the generated file.
 
     Returns:
@@ -324,11 +324,11 @@ def persistent_file_helper(u_boot_log, filename):
 
     return PersistentFileHelperCtxMgr(u_boot_log, filename)
 
-def crc32(u_boot_console, address, count):
+def crc32(ubman, address, count):
     """Helper function used to compute the CRC32 value of a section of RAM.
 
     Args:
-        u_boot_console: A U-Boot console connection.
+        ubman: A U-Boot console connection.
         address: Address where data starts.
         count: Amount of data to use for calculation.
 
@@ -336,10 +336,10 @@ def crc32(u_boot_console, address, count):
         CRC32 value
     """
 
-    bcfg = u_boot_console.config.buildconfig
+    bcfg = ubman.config.buildconfig
     has_cmd_crc32 = bcfg.get('config_cmd_crc32', 'n') == 'y'
     assert has_cmd_crc32, 'Cannot compute crc32 without CONFIG_CMD_CRC32.'
-    output = u_boot_console.run_command('crc32 %08x %x' % (address, count))
+    output = ubman.run_command('crc32 %08x %x' % (address, count))
 
     m = re.search('==> ([0-9a-fA-F]{8})$', output)
     assert m, 'CRC32 operation failed.'
diff --git a/test/test-main.c b/test/test-main.c
index 22b9b46d9cd..cabc736a524 100644
--- a/test/test-main.c
+++ b/test/test-main.c
@@ -14,6 +14,7 @@
 #include <net.h>
 #include <of_live.h>
 #include <os.h>
+#include <spl.h>
 #include <usb.h>
 #include <dm/ofnode.h>
 #include <dm/root.h>
@@ -513,11 +514,12 @@ static int ut_run_test(struct unit_test_state *uts, struct unit_test *test,
  *	the first call to this function. On exit, @uts->cur.fail_count is
  *	incremented by the number of failures (0, one hopes)
  * @test: Test to run
+ * @leaf: Part of the name to show, or NULL to use test->name
  * Return: 0 if all tests passed, -EAGAIN if the test should be skipped, -1 if
  *	any failed
  */
 static int ut_run_test_live_flat(struct unit_test_state *uts,
-				 struct unit_test *test)
+				 struct unit_test *test, const char *leaf)
 {
 	int runs, ret;
 
@@ -529,7 +531,7 @@ static int ut_run_test_live_flat(struct unit_test_state *uts,
 	if (CONFIG_IS_ENABLED(OF_LIVE)) {
 		if (!(test->flags & UTF_FLAT_TREE)) {
 			uts->of_live = true;
-			ret = ut_run_test(uts, test, test->name);
+			ret = ut_run_test(uts, test, leaf ?: test->name);
 			if (ret != -EAGAIN) {
 				ut_assertok(ret);
 				runs++;
@@ -557,7 +559,7 @@ static int ut_run_test_live_flat(struct unit_test_state *uts,
 	    (!runs || ut_test_run_on_flattree(test)) &&
 	    !(gd->flags & GD_FLG_FDT_CHANGED)) {
 		uts->of_live = false;
-		ret = ut_run_test(uts, test, test->name);
+		ret = ut_run_test(uts, test, leaf ?: test->name);
 		if (ret != -EAGAIN) {
 			ut_assertok(ret);
 			runs++;
@@ -593,6 +595,7 @@ static int ut_run_tests(struct unit_test_state *uts, const char *prefix,
 			struct unit_test *tests, int count,
 			const char *select_name, const char *test_insert)
 {
+	int prefix_len = prefix ? strlen(prefix) : 0;
 	struct unit_test *test, *one;
 	int found = 0;
 	int pos = 0;
@@ -617,7 +620,8 @@ static int ut_run_tests(struct unit_test_state *uts, const char *prefix,
 		const char *test_name = test->name;
 		int ret, i, old_fail_count;
 
-		if (!test_matches(prefix, test_name, select_name))
+		if (!(test->flags & (UTF_INIT | UTF_UNINIT)) &&
+		    !test_matches(prefix, test_name, select_name))
 			continue;
 
 		if (test->flags & UTF_MANUAL) {
@@ -645,7 +649,7 @@ static int ut_run_tests(struct unit_test_state *uts, const char *prefix,
 
 		uts->cur.test_count++;
 		if (one && upto == pos) {
-			ret = ut_run_test_live_flat(uts, one);
+			ret = ut_run_test_live_flat(uts, one, NULL);
 			if (uts->cur.fail_count != old_fail_count) {
 				printf("Test '%s' failed %d times (position %d)\n",
 				       one->name,
@@ -655,8 +659,11 @@ static int ut_run_tests(struct unit_test_state *uts, const char *prefix,
 			return -EBADF;
 		}
 
+		if (prefix_len && !strncmp(test_name, prefix, prefix_len))
+			test_name = test_name + prefix_len;
+
 		for (i = 0; i < uts->runs_per_test; i++)
-			ret = ut_run_test_live_flat(uts, test);
+			ret = ut_run_test_live_flat(uts, test, test_name);
 		if (uts->cur.fail_count != old_fail_count) {
 			printf("Test '%s' failed %d times\n", test_name,
 			       uts->cur.fail_count - old_fail_count);
@@ -680,6 +687,12 @@ void ut_report(struct ut_stats *stats, int run_count)
 	else
 		printf("Tests");
 	printf(" run: %d, ", stats->test_count);
+	if (stats && stats->test_count) {
+		ulong dur = stats->duration_ms;
+
+		printf("%ld ms, average: %ld ms, ", dur,
+		       dur ? dur / stats->test_count : 0);
+	}
 	if (stats->skip_count)
 		printf("skipped: %d, ", stats->skip_count);
 	printf("failures: %d\n", stats->fail_count);
@@ -692,16 +705,22 @@ int ut_run_list(struct unit_test_state *uts, const char *category,
 {
 	;
 	bool has_dm_tests = false;
+	ulong start_offset = 0;
+	ulong test_offset = 0;
 	int ret;
 
 	memset(&uts->cur, '\0', sizeof(struct ut_stats));
+	if (CONFIG_IS_ENABLED(UNIT_TEST_DURATION)) {
+		uts->cur.start = get_timer(0);
+		start_offset = timer_test_get_offset();
+	}
 
 	if (!CONFIG_IS_ENABLED(OF_PLATDATA) &&
 	    ut_list_has_dm_tests(tests, count, prefix, select_name)) {
 		has_dm_tests = true;
 		/*
 		 * If we have no device tree, or it only has a root node, then
-		 * these * tests clearly aren't going to work...
+		 * these tests clearly aren't going to work...
 		 */
 		if (!gd->fdt_blob || fdt_next_node(gd->fdt_blob, 0, NULL) < 0) {
 			puts("Please run with test device tree:\n"
@@ -732,13 +751,19 @@ int ut_run_list(struct unit_test_state *uts, const char *category,
 	if (has_dm_tests)
 		dm_test_restore(uts->of_root);
 
-	ut_report(&uts->cur, 1);
 	if (ret == -ENOENT)
 		printf("Test '%s' not found\n", select_name);
+	if (CONFIG_IS_ENABLED(UNIT_TEST_DURATION)) {
+		test_offset = timer_test_get_offset() - start_offset;
+
+		uts->cur.duration_ms = get_timer(uts->cur.start) - test_offset;
+	}
+	ut_report(&uts->cur, 1);
 
 	uts->total.skip_count += uts->cur.skip_count;
 	uts->total.fail_count += uts->cur.fail_count;
 	uts->total.test_count += uts->cur.test_count;
+	uts->total.duration_ms += uts->cur.duration_ms;
 	uts->run_count++;
 
 	return ret;
diff --git a/tools/.gitignore b/tools/.gitignore
index 0108c567309..6a5c613f772 100644
--- a/tools/.gitignore
+++ b/tools/.gitignore
@@ -29,6 +29,7 @@
 /mxsboot
 /ncb
 /prelink-riscv
+/preload_check_sign
 /printinitialenv
 /proftool
 /relocate-rela
diff --git a/tools/Kconfig b/tools/Kconfig
index 01ff0fcf748..8e272ee99a8 100644
--- a/tools/Kconfig
+++ b/tools/Kconfig
@@ -9,6 +9,11 @@ config MKIMAGE_DTC_PATH
 	  some cases the system dtc may not support all required features
 	  and the path to a different version should be given here.
 
+config TOOLS_IMAGE_PRE_LOAD
+	def_bool y
+	help
+	  Enable pre-load signature support in the tools builds.
+
 config TOOLS_CRC16
 	def_bool y
 	help
diff --git a/tools/Makefile b/tools/Makefile
index 237fa900a24..53b87d22a80 100644
--- a/tools/Makefile
+++ b/tools/Makefile
@@ -66,6 +66,7 @@ mkenvimage-objs := mkenvimage.o os_support.o generated/lib/crc32.o
 hostprogs-y += dumpimage mkimage
 hostprogs-$(CONFIG_TOOLS_LIBCRYPTO) += fit_info fit_check_sign
 hostprogs-$(CONFIG_TOOLS_LIBCRYPTO) += fdt_add_pubkey
+hostprogs-$(CONFIG_TOOLS_LIBCRYPTO) += preload_check_sign
 
 ifneq ($(CONFIG_CMD_BOOTEFI_SELFTEST)$(CONFIG_FWU_MDATA_GPT_BLK),)
 hostprogs-y += file2include
@@ -75,6 +76,9 @@ FIT_OBJS-y := fit_common.o fit_image.o image-host.o generated/boot/image-fit.o
 FIT_SIG_OBJS-$(CONFIG_TOOLS_LIBCRYPTO) := image-sig-host.o generated/boot/image-fit-sig.o
 FIT_CIPHER_OBJS-$(CONFIG_TOOLS_LIBCRYPTO) := generated/boot/image-cipher.o
 
+HOSTCFLAGS_image-host.o += \
+	$(shell pkg-config --cflags libssl libcrypto 2> /dev/null || echo "")
+
 # The following files are synced with upstream DTC.
 # Use synced versions from scripts/dtc/libfdt/.
 LIBFDT_OBJS := $(addprefix libfdt/, fdt.o fdt_ro.o fdt_wip.o fdt_sw.o fdt_rw.o \
@@ -83,12 +87,18 @@ LIBFDT_OBJS := $(addprefix libfdt/, fdt.o fdt_ro.o fdt_wip.o fdt_sw.o fdt_rw.o \
 RSA_OBJS-$(CONFIG_TOOLS_LIBCRYPTO) := $(addprefix generated/lib/rsa/, \
 					rsa-sign.o rsa-verify.o \
 					rsa-mod-exp.o)
+HOSTCFLAGS_rsa-sign.o += \
+	$(shell pkg-config --cflags libssl libcrypto 2> /dev/null || echo "")
 
 ECDSA_OBJS-$(CONFIG_TOOLS_LIBCRYPTO) := $(addprefix generated/lib/ecdsa/, ecdsa-libcrypto.o)
+HOSTCFLAGS_ecdsa-libcrypto.o += \
+	$(shell pkg-config --cflags libssl libcrypto 2> /dev/null || echo "")
 
 AES_OBJS-$(CONFIG_TOOLS_LIBCRYPTO) := $(addprefix generated/lib/aes/, \
 					aes-encrypt.o aes-decrypt.o)
 
+PRELOAD_OBJS-$(CONFIG_TOOLS_LIBCRYPTO) := generated/boot/image-pre-load.o
+
 # Cryptographic helpers and image types that depend on openssl/libcrypto
 LIBCRYPTO_OBJS-$(CONFIG_TOOLS_LIBCRYPTO) := \
 			generated/lib/fdt-libcrypto.o \
@@ -158,6 +168,7 @@ fit_info-objs   := $(dumpimage-mkimage-objs) fit_info.o
 fit_check_sign-objs   := $(dumpimage-mkimage-objs) fit_check_sign.o
 fdt_add_pubkey-objs   := $(dumpimage-mkimage-objs) fdt_add_pubkey.o
 file2include-objs := file2include.o
+preload_check_sign-objs := $(dumpimage-mkimage-objs) $(PRELOAD_OBJS-y) preload_check_sign.o
 
 ifneq ($(CONFIG_MX23)$(CONFIG_MX28)$(CONFIG_TOOLS_LIBCRYPTO),)
 # Add CFG_MXS into host CFLAGS, so we can check whether or not register
@@ -195,6 +206,7 @@ HOSTLDLIBS_dumpimage := $(HOSTLDLIBS_mkimage)
 HOSTLDLIBS_fit_info := $(HOSTLDLIBS_mkimage)
 HOSTLDLIBS_fit_check_sign := $(HOSTLDLIBS_mkimage)
 HOSTLDLIBS_fdt_add_pubkey := $(HOSTLDLIBS_mkimage)
+HOSTLDLIBS_preload_check_sign := $(HOSTLDLIBS_mkimage)
 
 hostprogs-$(CONFIG_EXYNOS5250) += mkexynosspl
 hostprogs-$(CONFIG_EXYNOS5420) += mkexynosspl
diff --git a/tools/binman/bintool.py b/tools/binman/bintool.py
index 3c4ad1adbb9..81872db377f 100644
--- a/tools/binman/bintool.py
+++ b/tools/binman/bintool.py
@@ -328,7 +328,8 @@ class Bintool:
             return result.stdout
 
     @classmethod
-    def build_from_git(cls, git_repo, make_targets, bintool_path, flags=None):
+    def build_from_git(cls, git_repo, make_targets, bintool_path,
+            flags=None, git_branch=None, make_path=None):
         """Build a bintool from a git repo
 
         This clones the repo in a temporary directory, builds it with 'make',
@@ -341,6 +342,9 @@ class Bintool:
             bintool_path (str): Relative path of the tool in the repo, after
                 build is complete
             flags (list of str): Flags or variables to pass to make, or None
+            git_branch (str): Branch of git repo, or None to use the default
+            make_path (str): Relative path inside git repo containing the
+                Makefile, or None
 
         Returns:
             tuple:
@@ -350,10 +354,17 @@ class Bintool:
         """
         tmpdir = tempfile.mkdtemp(prefix='binmanf.')
         print(f"- clone git repo '{git_repo}' to '{tmpdir}'")
-        tools.run('git', 'clone', '--depth', '1', git_repo, tmpdir)
+        if git_branch:
+            tools.run('git', 'clone', '--depth', '1', '--branch', git_branch,
+                      git_repo, tmpdir)
+        else:
+            tools.run('git', 'clone', '--depth', '1', git_repo, tmpdir)
         for target in make_targets:
             print(f"- build target '{target}'")
-            cmd = ['make', '-C', tmpdir, '-j', f'{multiprocessing.cpu_count()}',
+            makedir = tmpdir
+            if make_path:
+                makedir = os.path.join(tmpdir, make_path)
+            cmd = ['make', '-C', makedir, '-j', f'{multiprocessing.cpu_count()}',
                    target]
             if flags:
                 cmd += flags
diff --git a/tools/binman/bintool_test.py b/tools/binman/bintool_test.py
index f9b16d4c73b..949d6f4c8a9 100644
--- a/tools/binman/bintool_test.py
+++ b/tools/binman/bintool_test.py
@@ -303,6 +303,7 @@ class TestBintool(unittest.TestCase):
                 # See Bintool.build_from_git()
                 tmpdir = cmd[2]
                 self.fname = os.path.join(tmpdir, 'pathname')
+                os.makedirs(os.path.dirname(tmpdir), exist_ok=True)
                 tools.write_file(self.fname, b'hello')
 
         expected = b'this is a test'
diff --git a/tools/binman/bintools.rst b/tools/binman/bintools.rst
index cd05ad8cb26..9f6cab544a5 100644
--- a/tools/binman/bintools.rst
+++ b/tools/binman/bintools.rst
@@ -52,6 +52,14 @@ Bintool: cst: Image generation for U-Boot
 This bintool supports running `cst` with some basic parameters as
 needed by binman.
 
+cst (imx code signing tool) is used for sigining bootloader binaries for
+various i.MX SoCs.
+
+See `Code Signing Tool Users Guide`_ for more information.
+
+.. _`Code Signing Tool Users Guide`:
+    https://community.nxp.com/pwmxy87654/attachments/pwmxy87654/imx-processors/202591/1/CST_UG.pdf
+
 
 
 Bintool: fdt_add_pubkey: Add public key to control dtb (spl or u-boot proper)
diff --git a/tools/binman/btool/cst.py b/tools/binman/btool/cst.py
index 30e78bdbbd9..8a3981adc89 100644
--- a/tools/binman/btool/cst.py
+++ b/tools/binman/btool/cst.py
@@ -12,6 +12,14 @@ class Bintoolcst(bintool.Bintool):
 
     This bintool supports running `cst` with some basic parameters as
     needed by binman.
+
+    cst (imx code signing tool) is used for sigining bootloader binaries for
+    various i.MX SoCs.
+
+    See `Code Signing Tool Users Guide`_ for more information.
+
+    .. _`Code Signing Tool Users Guide`:
+        https://community.nxp.com/pwmxy87654/attachments/pwmxy87654/imx-processors/202591/1/CST_UG.pdf
     """
     def __init__(self, name):
         super().__init__(name, 'Sign NXP i.MX image')
@@ -29,20 +37,17 @@ class Bintoolcst(bintool.Bintool):
         return self.run_cmd(*args)
 
     def fetch(self, method):
-        """Fetch handler for cst
-
-        This installs cst using the apt utility.
-
-        Args:
-            method (FETCH_...): Method to use
-
-        Returns:
-            True if the file was fetched and now installed, None if a method
-            other than FETCH_BIN was requested
-
-        Raises:
-            Valuerror: Fetching could not be completed
-        """
-        if method != bintool.FETCH_BIN:
+        """Build cst from git"""
+        if method != bintool.FETCH_BUILD:
             return None
-        return self.apt_install('imx-code-signing-tool')
+
+        from platform import architecture
+        arch = 'linux64' if architecture()[0] == '64bit' else 'linux32'
+        result = self.build_from_git(
+            'https://gitlab.apertis.org/pkg/imx-code-signing-tool',
+            ['all'],
+            f'code/obj.{arch}/cst',
+            flags=[f'OSTYPE={arch}', 'ENCRYPTION=yes'],
+            git_branch='debian/unstable',
+            make_path=f'code/obj.{arch}/')
+        return result
diff --git a/tools/binman/control.py b/tools/binman/control.py
index e73c598298c..81f61e3e152 100644
--- a/tools/binman/control.py
+++ b/tools/binman/control.py
@@ -522,9 +522,13 @@ def _ProcessTemplates(parent):
 def _RemoveTemplates(parent):
     """Remove any templates in the binman description
     """
+    del_nodes = []
     for node in parent.subnodes:
         if node.name.startswith('template'):
-            node.Delete()
+            del_nodes.append(node)
+
+    for node in del_nodes:
+        node.Delete()
 
 def PrepareImagesAndDtbs(dtb_fname, select_images, update_fdt, use_expanded, indir):
     """Prepare the images to be processed and select the device tree
diff --git a/tools/binman/etype/fdtmap.py b/tools/binman/etype/fdtmap.py
index f1f6217940f..2259404180c 100644
--- a/tools/binman/etype/fdtmap.py
+++ b/tools/binman/etype/fdtmap.py
@@ -106,6 +106,9 @@ class Entry_fdtmap(Entry):
         Returns:
             FDT map binary data
         """
+        fsw = libfdt.FdtSw()
+        fsw.finish_reservemap()
+
         def _AddNode(node):
             """Add a node to the FDT map"""
             for pname, prop in node.props.items():
@@ -134,8 +137,6 @@ class Entry_fdtmap(Entry):
 
             # Build a new tree with all nodes and properties starting from that
             # node
-            fsw = libfdt.FdtSw()
-            fsw.finish_reservemap()
             with fsw.add_node(''):
                 fsw.property_string('image-node', node.name)
                 _AddNode(node)
diff --git a/tools/binman/etype/image_header.py b/tools/binman/etype/image_header.py
index 24011884958..2114df8159f 100644
--- a/tools/binman/etype/image_header.py
+++ b/tools/binman/etype/image_header.py
@@ -62,6 +62,7 @@ class Entry_image_header(Entry):
 
     def _GetHeader(self):
         image_pos = self.GetSiblingImagePos('fdtmap')
+        offset = None
         if image_pos == False:
             self.Raise("'image_header' section must have an 'fdtmap' sibling")
         elif image_pos is None:
diff --git a/tools/binman/etype/pre_load.py b/tools/binman/etype/pre_load.py
index 2e4c72359ff..00f1a896767 100644
--- a/tools/binman/etype/pre_load.py
+++ b/tools/binman/etype/pre_load.py
@@ -112,6 +112,8 @@ class Entry_pre_load(Entry_collection):
         # Compute the signature
         if padding_name is None:
             padding_name = "pkcs-1.5"
+        padding = None
+        padding_args = None
         if padding_name == "pss":
             salt_len = key.size_in_bytes() - hash_image.digest_size - 2
             padding = pss
diff --git a/tools/binman/etype/ti_board_config.py b/tools/binman/etype/ti_board_config.py
index c10d66edcb1..7c6773ac7bc 100644
--- a/tools/binman/etype/ti_board_config.py
+++ b/tools/binman/etype/ti_board_config.py
@@ -119,12 +119,14 @@ class Entry_ti_board_config(Entry_section):
             array of bytes representing value
         """
         size = 0
+        br = bytearray()
         if (data_type == '#/definitions/u8'):
             size = 1
         elif (data_type == '#/definitions/u16'):
             size = 2
         else:
             size = 4
+        br = None
         if type(val) == int:
             br = val.to_bytes(size, byteorder='little')
         return br
diff --git a/tools/binman/etype/x509_cert.py b/tools/binman/etype/x509_cert.py
index 29630d1b86c..25e6808b7f9 100644
--- a/tools/binman/etype/x509_cert.py
+++ b/tools/binman/etype/x509_cert.py
@@ -84,6 +84,7 @@ class Entry_x509_cert(Entry_collection):
         input_fname = tools.get_output_filename('input.%s' % uniq)
         config_fname = tools.get_output_filename('config.%s' % uniq)
         tools.write_file(input_fname, input_data)
+        stdout = None
         if type == 'generic':
             stdout = self.openssl.x509_cert(
                 cert_fname=output_fname,
diff --git a/tools/binman/ftest.py b/tools/binman/ftest.py
index 733169b99f6..948fcc02259 100644
--- a/tools/binman/ftest.py
+++ b/tools/binman/ftest.py
@@ -303,7 +303,7 @@ class TestFunctional(unittest.TestCase):
     def setUp(self):
         # Enable this to turn on debugging output
         # tout.init(tout.DEBUG)
-        command.test_result = None
+        command.TEST_RESULT = None
 
     def tearDown(self):
         """Remove the temporary output directory"""
@@ -345,8 +345,9 @@ class TestFunctional(unittest.TestCase):
             Arguments to pass, as a list of strings
             kwargs: Arguments to pass to Command.RunPipe()
         """
-        result = command.run_pipe([[self._binman_pathname] + list(args)],
-                capture=True, capture_stderr=True, raise_on_error=False)
+        all_args = [self._binman_pathname] + list(args)
+        result = command.run_one(*all_args, capture=True, capture_stderr=True,
+                                 raise_on_error=False)
         if result.return_code and kwargs.get('raise_on_error', True):
             raise Exception("Error running '%s': %s" % (' '.join(args),
                             result.stdout + result.stderr))
@@ -762,6 +763,16 @@ class TestFunctional(unittest.TestCase):
             return False
         return True
 
+    def _CheckPreload(self, image, key, algo="sha256,rsa2048",
+                      padding="pkcs-1.5"):
+        try:
+            tools.run('preload_check_sign', '-k', key, '-a', algo, '-p',
+                      padding, '-f', image)
+        except:
+            self.fail('Expected image signed with a pre-load')
+            return False
+        return True
+
     def testRun(self):
         """Test a basic run with valid args"""
         result = self._RunBinman('-h')
@@ -780,11 +791,11 @@ class TestFunctional(unittest.TestCase):
     def testFullHelpInternal(self):
         """Test that the full help is displayed with -H"""
         try:
-            command.test_result = command.CommandResult()
+            command.TEST_RESULT = command.CommandResult()
             result = self._DoBinman('-H')
             help_file = os.path.join(self._binman_dir, 'README.rst')
         finally:
-            command.test_result = None
+            command.TEST_RESULT = None
 
     def testHelp(self):
         """Test that the basic help is displayed with -h"""
@@ -1872,7 +1883,7 @@ class TestFunctional(unittest.TestCase):
 
     def testGbb(self):
         """Test for the Chromium OS Google Binary Block"""
-        command.test_result = self._HandleGbbCommand
+        command.TEST_RESULT = self._HandleGbbCommand
         entry_args = {
             'keydir': 'devkeys',
             'bmpblk': 'bmpblk.bin',
@@ -1941,7 +1952,7 @@ class TestFunctional(unittest.TestCase):
     def testVblock(self):
         """Test for the Chromium OS Verified Boot Block"""
         self._hash_data = False
-        command.test_result = self._HandleVblockCommand
+        command.TEST_RESULT = self._HandleVblockCommand
         entry_args = {
             'keydir': 'devkeys',
         }
@@ -1974,7 +1985,7 @@ class TestFunctional(unittest.TestCase):
     def testVblockContent(self):
         """Test that the vblock signs the right data"""
         self._hash_data = True
-        command.test_result = self._HandleVblockCommand
+        command.TEST_RESULT = self._HandleVblockCommand
         entry_args = {
             'keydir': 'devkeys',
         }
@@ -5498,7 +5509,7 @@ fdt         fdtmap                Extract the devicetree blob from the fdtmap
 
     def testFitSubentryUsesBintool(self):
         """Test that binman FIT subentries can use bintools"""
-        command.test_result = self._HandleGbbCommand
+        command.TEST_RESULT = self._HandleGbbCommand
         entry_args = {
             'keydir': 'devkeys',
             'bmpblk': 'bmpblk.bin',
@@ -5783,9 +5794,14 @@ fdt         fdtmap                Extract the devicetree blob from the fdtmap
         data = self._DoReadFileDtb(
             '230_pre_load.dts', entry_args=entry_args,
             extra_indirs=[os.path.join(self._binman_dir, 'test')])[0]
+
+        image_fname = tools.get_output_filename('image.bin')
+        is_signed = self._CheckPreload(image_fname, self.TestFile("dev.key"))
+
         self.assertEqual(PRE_LOAD_MAGIC, data[:len(PRE_LOAD_MAGIC)])
         self.assertEqual(PRE_LOAD_VERSION, data[4:4 + len(PRE_LOAD_VERSION)])
         self.assertEqual(PRE_LOAD_HDR_SIZE, data[8:8 + len(PRE_LOAD_HDR_SIZE)])
+        self.assertEqual(is_signed, True)
 
     def testPreLoadNoKey(self):
         """Test an image with a pre-load heade0r with missing key"""
@@ -6383,6 +6399,7 @@ fdt         fdtmap                Extract the devicetree blob from the fdtmap
                     ename, prop = entry_m.group(1), entry_m.group(3)
                 entry, entry_name, prop_name = image.LookupEntry(entries,
                                                                  name, msg)
+                expect_val = None
                 if prop_name == 'offset':
                     expect_val = entry.offset
                 elif prop_name == 'image_pos':
@@ -7973,5 +7990,12 @@ fdt         fdtmap                Extract the devicetree blob from the fdtmap
         """Test an image with an FIT with multiple FDT images using NAME"""
         self.CheckFitFdt('345_fit_fdt_name.dts', use_seq_num=False)
 
+    def testRemoveTemplate(self):
+        """Test whether template is removed"""
+        TestFunctional._MakeInputFile('my-blob.bin', b'blob')
+        TestFunctional._MakeInputFile('my-blob2.bin', b'other')
+        self._DoTestFile('346_remove_template.dts',
+                         force_missing_bintools='openssl',)
+
 if __name__ == "__main__":
     unittest.main()
diff --git a/tools/binman/requirements.txt b/tools/binman/requirements.txt
new file mode 100644
index 00000000000..f068ef75a30
--- /dev/null
+++ b/tools/binman/requirements.txt
@@ -0,0 +1,5 @@
+importlib_resources==6.5.2
+jsonschema==4.23.0
+pycryptodomex==3.21.0
+pyelftools==0.31
+yamllint==1.35.1
diff --git a/tools/binman/setup.py b/tools/binman/setup.py
index 9a9206eb044..bec078a3d9b 100644
--- a/tools/binman/setup.py
+++ b/tools/binman/setup.py
@@ -1,6 +1,6 @@
 # SPDX-License-Identifier: GPL-2.0+
 
-from distutils.core import setup
+from setuptools import setup
 setup(name='binman',
       version='1.0',
       license='GPL-2.0+',
diff --git a/tools/binman/state.py b/tools/binman/state.py
index 45bae40c525..6772d3678fe 100644
--- a/tools/binman/state.py
+++ b/tools/binman/state.py
@@ -406,10 +406,13 @@ def CheckSetHashValue(node, get_data_func):
     hash_node = node.FindNode('hash')
     if hash_node:
         algo = hash_node.props.get('algo').value
+        data = None
         if algo == 'sha256':
             m = hashlib.sha256()
             m.update(get_data_func())
             data = m.digest()
+        if data is None:
+            raise ValueError(f"Node '{node.path}': Unknown hash algorithm '{algo}'")
         for n in GetUpdateNodes(hash_node):
             n.SetData('value', data)
 
diff --git a/tools/binman/test/346_remove_template.dts b/tools/binman/test/346_remove_template.dts
new file mode 100644
index 00000000000..e05229f3ebc
--- /dev/null
+++ b/tools/binman/test/346_remove_template.dts
@@ -0,0 +1,49 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+/dts-v1/;
+/ {
+    binman: binman {
+		multiple-images;
+
+		template_1: template-1 {
+			section {
+				phandle1: my-blob.bin {
+					filename = "my-blob.bin";
+					type = "blob-ext";
+				};
+			};
+		};
+		template_2: template-2 {
+			section {
+				ti-secure {
+					content = <&phandle2>;
+					keyfile = "key.pem";
+				};
+				phandle2: my-blob.bin {
+					filename = "my-blob.bin";
+					type = "blob-ext";
+				};
+			};
+		};
+		template_3: template-3 {
+			section {
+				phandle3: my-blob.bin {
+					filename = "my-blob.bin";
+					type = "blob-ext";
+				};
+			};
+		};
+
+		file1 {
+			insert-template = <&template_1>;
+		};
+
+		file2 {
+			insert-template = <&template_2>;
+		};
+
+		file3 {
+			insert-template = <&template_3>;
+		};
+	};
+};
diff --git a/tools/buildman/boards.py b/tools/buildman/boards.py
index e7aa0d85a58..2fe43c3fc89 100644
--- a/tools/buildman/boards.py
+++ b/tools/buildman/boards.py
@@ -251,9 +251,9 @@ class KconfigScanner:
                 '-undef',
                 '-x', 'assembler-with-cpp',
                 defconfig]
-            result = command.run_pipe([cmd], capture=True, capture_stderr=True)
+            stdout = command.output(*cmd, capture_stderr=True)
             temp = tempfile.NamedTemporaryFile(prefix='buildman-')
-            tools.write_file(temp.name, result.stdout, False)
+            tools.write_file(temp.name, stdout, False)
             fname = temp.name
             tout.info(f'Processing #include to produce {defconfig}')
         else:
diff --git a/tools/buildman/builder.py b/tools/buildman/builder.py
index cbf1345281b..4bea0a02b78 100644
--- a/tools/buildman/builder.py
+++ b/tools/buildman/builder.py
@@ -19,8 +19,8 @@ import time
 
 from buildman import builderthread
 from buildman import toolchain
-from patman import gitutil
 from u_boot_pylib import command
+from u_boot_pylib import gitutil
 from u_boot_pylib import terminal
 from u_boot_pylib import tools
 from u_boot_pylib.terminal import tprint
@@ -510,7 +510,7 @@ class Builder:
             stage: Stage that we are at (mrproper, config, oldconfig, build)
             cwd: Directory where make should be run
             args: Arguments to pass to make
-            kwargs: Arguments to pass to command.run_pipe()
+            kwargs: Arguments to pass to command.run_one()
         """
 
         def check_output(stream, data):
@@ -531,11 +531,12 @@ class Builder:
             return False
 
         self._restarting_config = False
-        self._terminated  = False
+        self._terminated = False
         cmd = [self.gnu_make] + list(args)
-        result = command.run_pipe([cmd], capture=True, capture_stderr=True,
-                cwd=cwd, raise_on_error=False, infile='/dev/null',
-                output_func=check_output, **kwargs)
+        result = command.run_one(*cmd, capture=True, capture_stderr=True,
+                                 cwd=cwd, raise_on_error=False,
+                                 infile='/dev/null', output_func=check_output,
+                                 **kwargs)
 
         if self._terminated:
             # Try to be helpful
@@ -1095,14 +1096,13 @@ class Builder:
                 diff = result[name]
                 if name.startswith('_'):
                     continue
-                if diff != 0:
-                    color = self.col.RED if diff > 0 else self.col.GREEN
+                colour = self.col.RED if diff > 0 else self.col.GREEN
                 msg = ' %s %+d' % (name, diff)
                 if not printed_target:
                     tprint('%10s  %-15s:' % ('', result['_target']),
                           newline=False)
                     printed_target = True
-                tprint(msg, colour=color, newline=False)
+                tprint(msg, colour=colour, newline=False)
             if printed_target:
                 tprint()
                 if show_bloat:
@@ -1353,6 +1353,7 @@ class Builder:
             for line in lines:
                 if not line:
                     continue
+                col = None
                 if line[0] == '+':
                     col = self.col.GREEN
                 elif line[0] == '-':
diff --git a/tools/buildman/builderthread.py b/tools/buildman/builderthread.py
index 29e6cf32af1..b8578d5b97b 100644
--- a/tools/buildman/builderthread.py
+++ b/tools/buildman/builderthread.py
@@ -17,8 +17,8 @@ import sys
 import threading
 
 from buildman import cfgutil
-from patman import gitutil
 from u_boot_pylib import command
+from u_boot_pylib import gitutil
 from u_boot_pylib import tools
 
 RETURN_CODE_RETRY = -1
@@ -179,13 +179,12 @@ class BuilderThread(threading.Thread):
             cwd (str): Working directory to set, or None to leave it alone
             *args (list of str): Arguments to pass to 'make'
             **kwargs (dict): A list of keyword arguments to pass to
-                command.run_pipe()
+                command.run_one()
 
         Returns:
             CommandResult object
         """
-        return self.builder.do_make(commit, brd, stage, cwd, *args,
-                **kwargs)
+        return self.builder.do_make(commit, brd, stage, cwd, *args, **kwargs)
 
     def _build_args(self, brd, out_dir, out_rel_dir, work_dir, commit_upto):
         """Set up arguments to the args list based on the settings
@@ -588,9 +587,10 @@ class BuilderThread(threading.Thread):
             lines = []
             for fname in BASE_ELF_FILENAMES:
                 cmd = [f'{self.toolchain.cross}nm', '--size-sort', fname]
-                nm_result = command.run_pipe([cmd], capture=True,
-                        capture_stderr=True, cwd=result.out_dir,
-                        raise_on_error=False, env=env)
+                nm_result = command.run_one(*cmd, capture=True,
+                                            capture_stderr=True,
+                                            cwd=result.out_dir,
+                                            raise_on_error=False, env=env)
                 if nm_result.stdout:
                     nm_fname = self.builder.get_func_sizes_file(
                         result.commit_upto, result.brd.target, fname)
@@ -598,9 +598,10 @@ class BuilderThread(threading.Thread):
                         print(nm_result.stdout, end=' ', file=outf)
 
                 cmd = [f'{self.toolchain.cross}objdump', '-h', fname]
-                dump_result = command.run_pipe([cmd], capture=True,
-                        capture_stderr=True, cwd=result.out_dir,
-                        raise_on_error=False, env=env)
+                dump_result = command.run_one(*cmd, capture=True,
+                                              capture_stderr=True,
+                                              cwd=result.out_dir,
+                                              raise_on_error=False, env=env)
                 rodata_size = ''
                 if dump_result.stdout:
                     objdump = self.builder.get_objdump_file(result.commit_upto,
@@ -613,9 +614,10 @@ class BuilderThread(threading.Thread):
                             rodata_size = fields[2]
 
                 cmd = [f'{self.toolchain.cross}size', fname]
-                size_result = command.run_pipe([cmd], capture=True,
-                        capture_stderr=True, cwd=result.out_dir,
-                        raise_on_error=False, env=env)
+                size_result = command.run_one(*cmd, capture=True,
+                                              capture_stderr=True,
+                                              cwd=result.out_dir,
+                                              raise_on_error=False, env=env)
                 if size_result.stdout:
                     lines.append(size_result.stdout.splitlines()[1] + ' ' +
                                  rodata_size)
@@ -624,9 +626,8 @@ class BuilderThread(threading.Thread):
             cmd = [f'{self.toolchain.cross}objcopy', '-O', 'binary',
                    '-j', '.rodata.default_environment',
                    'env/built-in.o', 'uboot.env']
-            command.run_pipe([cmd], capture=True,
-                            capture_stderr=True, cwd=result.out_dir,
-                            raise_on_error=False, env=env)
+            command.run_one(*cmd, capture=True, capture_stderr=True,
+                            cwd=result.out_dir, raise_on_error=False, env=env)
             if not work_in_output:
                 copy_files(result.out_dir, build_dir, '', ['uboot.env'])
 
diff --git a/tools/buildman/control.py b/tools/buildman/control.py
index 55d4d770c5c..5109b1cd5ce 100644
--- a/tools/buildman/control.py
+++ b/tools/buildman/control.py
@@ -20,9 +20,9 @@ from buildman import bsettings
 from buildman import cfgutil
 from buildman import toolchain
 from buildman.builder import Builder
-from patman import gitutil
 from patman import patchstream
 from u_boot_pylib import command
+from u_boot_pylib import gitutil
 from u_boot_pylib import terminal
 from u_boot_pylib import tools
 from u_boot_pylib.terminal import print_clear, tprint
diff --git a/tools/buildman/func_test.py b/tools/buildman/func_test.py
index 4e12c671a3d..b45eb95a1e6 100644
--- a/tools/buildman/func_test.py
+++ b/tools/buildman/func_test.py
@@ -18,8 +18,8 @@ from buildman import bsettings
 from buildman import cmdline
 from buildman import control
 from buildman import toolchain
-from patman import gitutil
 from u_boot_pylib import command
+from u_boot_pylib import gitutil
 from u_boot_pylib import terminal
 from u_boot_pylib import test_util
 from u_boot_pylib import tools
@@ -187,7 +187,7 @@ class TestFunctional(unittest.TestCase):
         self._git_dir = os.path.join(self._base_dir, 'src')
         self._buildman_pathname = sys.argv[0]
         self._buildman_dir = os.path.dirname(os.path.realpath(sys.argv[0]))
-        command.test_result = self._HandleCommand
+        command.TEST_RESULT = self._HandleCommand
         bsettings.setup(None)
         bsettings.add_file(settings_data)
         self.setupToolchains()
@@ -232,8 +232,8 @@ class TestFunctional(unittest.TestCase):
         self._toolchains.Add('gcc', test=False)
 
     def _RunBuildman(self, *args):
-        return command.run_pipe([[self._buildman_pathname] + list(args)],
-                capture=True, capture_stderr=True)
+        all_args = [self._buildman_pathname] + list(args)
+        return command.run_one(*all_args, capture=True, capture_stderr=True)
 
     def _RunControl(self, *args, brds=False, clean_dir=False,
                     test_thread_exceptions=False, get_builder=True):
@@ -266,7 +266,7 @@ class TestFunctional(unittest.TestCase):
         return result
 
     def testFullHelp(self):
-        command.test_result = None
+        command.TEST_RESULT = None
         result = self._RunBuildman('-H')
         help_file = os.path.join(self._buildman_dir, 'README.rst')
         # Remove possible extraneous strings
@@ -277,7 +277,7 @@ class TestFunctional(unittest.TestCase):
         self.assertEqual(0, result.return_code)
 
     def testHelp(self):
-        command.test_result = None
+        command.TEST_RESULT = None
         result = self._RunBuildman('-h')
         help_file = os.path.join(self._buildman_dir, 'README.rst')
         self.assertTrue(len(result.stdout) > 1000)
@@ -286,13 +286,13 @@ class TestFunctional(unittest.TestCase):
 
     def testGitSetup(self):
         """Test gitutils.Setup(), from outside the module itself"""
-        command.test_result = command.CommandResult(return_code=1)
+        command.TEST_RESULT = command.CommandResult(return_code=1)
         gitutil.setup()
-        self.assertEqual(gitutil.use_no_decorate, False)
+        self.assertEqual(gitutil.USE_NO_DECORATE, False)
 
-        command.test_result = command.CommandResult(return_code=0)
+        command.TEST_RESULT = command.CommandResult(return_code=0)
         gitutil.setup()
-        self.assertEqual(gitutil.use_no_decorate, True)
+        self.assertEqual(gitutil.USE_NO_DECORATE, True)
 
     def _HandleCommandGitLog(self, args):
         if args[-1] == '--':
@@ -445,7 +445,7 @@ class TestFunctional(unittest.TestCase):
             stage: Stage that we are at (mrproper, config, build)
             cwd: Directory where make should be run
             args: Arguments to pass to make
-            kwargs: Arguments to pass to command.run_pipe()
+            kwargs: Arguments to pass to command.run_one()
         """
         self._make_calls += 1
         out_dir = ''
diff --git a/tools/buildman/main.py b/tools/buildman/main.py
index a948f36d9c0..72571b226d9 100755
--- a/tools/buildman/main.py
+++ b/tools/buildman/main.py
@@ -50,8 +50,7 @@ def run_tests(skip_net_tests, debug, verbose, args):
     # 'entry' module.
     result = test_util.run_test_suites(
         'buildman', debug, verbose, False, args.threads, test_name, [],
-        [test.TestBuild, func_test.TestFunctional,
-         'buildman.toolchain', 'patman.gitutil'])
+        [test.TestBuild, func_test.TestFunctional, 'buildman.toolchain'])
 
     return (0 if result.wasSuccessful() else 1)
 
diff --git a/tools/buildman/requirements.txt b/tools/buildman/requirements.txt
index a6b1aecdbe0..d48650cd1e5 100644
--- a/tools/buildman/requirements.txt
+++ b/tools/buildman/requirements.txt
@@ -1,5 +1,2 @@
-coverage==6.2
-jsonschema==4.17.3
-pycryptodome==3.20
-pyyaml==6.0.2
-yamllint==1.26.3
+filelock==3.0.12
+importlib_resources==6.5.2
diff --git a/tools/buildman/test.py b/tools/buildman/test.py
index 385a34e5254..c5feb74a105 100644
--- a/tools/buildman/test.py
+++ b/tools/buildman/test.py
@@ -836,6 +836,7 @@ class TestBuild(unittest.TestCase):
         tmpdir = self.base_dir
 
         with (patch('time.time', side_effect=self.get_time),
+              patch('time.perf_counter', side_effect=self.get_time),
               patch('time.monotonic', side_effect=self.get_time),
               patch('time.sleep', side_effect=self.inc_time),
               patch('os.kill', side_effect=self.kill)):
diff --git a/tools/buildman/toolchain.py b/tools/buildman/toolchain.py
index 958f36f9f61..5d051e005da 100644
--- a/tools/buildman/toolchain.py
+++ b/tools/buildman/toolchain.py
@@ -100,7 +100,7 @@ class Toolchain:
         else:
             self.priority = priority
         if test:
-            result = command.run_pipe([cmd], capture=True, env=env,
+            result = command.run_one(*cmd, capture=True, env=env,
                                      raise_on_error=False)
             self.ok = result.return_code == 0
             if verbose:
diff --git a/tools/docker/Dockerfile b/tools/docker/Dockerfile
index d2848ab85f3..80e9247aa60 100644
--- a/tools/docker/Dockerfile
+++ b/tools/docker/Dockerfile
@@ -74,6 +74,7 @@ RUN --mount=type=cache,target=/var/cache/apt,sharing=locked \
 	e2fsprogs \
 	efitools \
 	erofs-utils \
+	exfatprogs \
 	expect \
 	fakeroot \
 	flex \
@@ -122,7 +123,6 @@ RUN --mount=type=cache,target=/var/cache/apt,sharing=locked \
 	python3 \
 	python3-dev \
 	python3-pip \
-	python3-pyelftools \
 	python3-sphinx \
 	python3-virtualenv \
 	rpm2cpio \
@@ -297,7 +297,8 @@ RUN wget -O - https://coreboot.org/releases/coreboot-24.08.tar.xz | tar -C /tmp
     make olddefconfig && \
     make -j $(nproc) && \
     sudo mkdir /opt/coreboot && \
-    sudo cp build/coreboot.rom build/cbfstool /opt/coreboot/
+    sudo cp build/coreboot.rom build/cbfstool /opt/coreboot/ && \
+    rm -rf /tmp/coreboot-24.08
 
 # Create our user/group
 RUN echo uboot ALL=NOPASSWD: ALL > /etc/sudoers.d/uboot
@@ -308,12 +309,18 @@ USER uboot:uboot
 # COPY / ADD directives don't work as we need them to.
 RUN wget -O /tmp/pytest-requirements.txt https://source.denx.de/u-boot/u-boot/-/raw/master/test/py/requirements.txt
 RUN wget -O /tmp/sphinx-requirements.txt https://source.denx.de/u-boot/u-boot/-/raw/master/doc/sphinx/requirements.txt
+RUN wget -O /tmp/binman-requirements.txt https://source.denx.de/u-boot/u-boot/-/raw/master/tools/binman/requirements.txt
 RUN wget -O /tmp/buildman-requirements.txt https://source.denx.de/u-boot/u-boot/-/raw/master/tools/buildman/requirements.txt
+RUN wget -O /tmp/patman-requirements.txt https://source.denx.de/u-boot/u-boot/-/raw/master/tools/patman/requirements.txt
+RUN wget -O /tmp/u_boot_pylib-requirements.txt https://source.denx.de/u-boot/u-boot/-/raw/master/tools/u_boot_pylib/requirements.txt
 RUN virtualenv -p /usr/bin/python3 /tmp/venv && \
 	. /tmp/venv/bin/activate && \
 	pip install -r /tmp/pytest-requirements.txt \
 		-r /tmp/sphinx-requirements.txt \
-		-r /tmp/buildman-requirements.txt && \
+		-r /tmp/binman-requirements.txt \
+		-r /tmp/buildman-requirements.txt \
+		-r /tmp/patman-requirements.txt \
+		-r /tmp/u_boot_pylib-requirements.txt && \
 	deactivate && \
 	rm -rf /tmp/venv /tmp/*-requirements.txt
 
diff --git a/tools/dtoc/setup.py b/tools/dtoc/setup.py
index 5e092fe0872..ae9ad043b01 100644
--- a/tools/dtoc/setup.py
+++ b/tools/dtoc/setup.py
@@ -1,6 +1,6 @@
 # SPDX-License-Identifier: GPL-2.0+
 
-from distutils.core import setup
+from setuptools import setup
 setup(name='dtoc',
       version='1.0',
       license='GPL-2.0+',
diff --git a/tools/image-host.c b/tools/image-host.c
index e6de34fa059..a9b86902763 100644
--- a/tools/image-host.c
+++ b/tools/image-host.c
@@ -19,6 +19,11 @@
 #include <openssl/evp.h>
 #endif
 
+#if CONFIG_IS_ENABLED(IMAGE_PRE_LOAD)
+#include <openssl/rsa.h>
+#include <openssl/err.h>
+#endif
+
 /**
  * fit_set_hash_value - set hash value in requested has node
  * @fit: pointer to the FIT format image header
@@ -729,11 +734,20 @@ static int strlist_add(struct strlist *list, const char *str)
 {
 	char *dup;
 
+	if (!list || !str)
+		return -1;
+
 	dup = strdup(str);
+	if(!dup)
+		return -1;
+
 	list->strings = realloc(list->strings,
 				(list->count + 1) * sizeof(char *));
-	if (!list || !str)
+	if (!list->strings) {
+		free(dup);
 		return -1;
+	}
+
 	list->strings[list->count++] = dup;
 
 	return 0;
@@ -1401,3 +1415,139 @@ int fit_check_sign(const void *fit, const void *key,
 	return ret;
 }
 #endif
+
+#if CONFIG_IS_ENABLED(IMAGE_PRE_LOAD)
+/**
+ * rsa_verify_openssl() - Verify a signature against some data with openssl API
+ *
+ * Verify a RSA PKCS1.5/PSS signature against an expected hash.
+ *
+ * @info:		Specifies the key and algorithms
+ * @region:		Pointer to the input data
+ * @region_count:	Number of region
+ * @sig:		Signature
+ * @sig_len:		Number of bytes in the signature
+ * Return: 0 if verified, -ve on error
+ */
+int rsa_verify_openssl(struct image_sign_info *info,
+		       const struct image_region region[], int region_count,
+		       uint8_t *sig, uint sig_len)
+{
+	EVP_PKEY *pkey = NULL;
+	EVP_PKEY_CTX *ckey = NULL;
+	EVP_MD_CTX *ctx = NULL;
+	int pad;
+	int size;
+	int i;
+	int ret = 0;
+
+	if (!info) {
+		fprintf(stderr, "No info provided\n");
+		ret = -EINVAL;
+		goto out;
+	}
+
+	if (!info->key) {
+		fprintf(stderr, "No key provided\n");
+		ret = -EINVAL;
+		goto out;
+	}
+
+	if (!info->checksum) {
+		fprintf(stderr, "No checksum information\n");
+		ret = -EINVAL;
+		goto out;
+	}
+
+	if (!info->padding) {
+		fprintf(stderr, "No padding information\n");
+		ret = -EINVAL;
+		goto out;
+	}
+
+	if (region_count < 1) {
+		fprintf(stderr, "Invalid value for region_count: %d\n", region_count);
+		ret = -EINVAL;
+		goto out;
+	}
+
+	pkey = (EVP_PKEY *)info->key;
+
+	ckey = EVP_PKEY_CTX_new(pkey, NULL);
+	if (!ckey) {
+		ret = -ENOMEM;
+		fprintf(stderr, "EVK key context setup failed: %s\n",
+			ERR_error_string(ERR_get_error(), NULL));
+		goto out;
+	}
+
+	size = EVP_PKEY_size(pkey);
+	if (size > sig_len) {
+		fprintf(stderr, "Invalid signature size (%d bytes)\n",
+			size);
+		ret = -EINVAL;
+		goto out;
+	}
+
+	ctx = EVP_MD_CTX_new();
+	if (!ctx) {
+		ret = -ENOMEM;
+		fprintf(stderr, "EVP context creation failed: %s\n",
+			ERR_error_string(ERR_get_error(), NULL));
+		goto out;
+	}
+	EVP_MD_CTX_init(ctx);
+
+	if (EVP_DigestVerifyInit(ctx, &ckey,
+				 EVP_get_digestbyname(info->checksum->name),
+				 NULL, pkey) <= 0) {
+		ret = -EINVAL;
+		fprintf(stderr, "Verifier setup failed: %s\n",
+			ERR_error_string(ERR_get_error(), NULL));
+		goto out;
+	}
+
+	if (!strcmp(info->padding->name, "pkcs-1.5")) {
+		pad = RSA_PKCS1_PADDING;
+	} else if (!strcmp(info->padding->name, "pss")) {
+		pad = RSA_PKCS1_PSS_PADDING;
+	} else {
+		ret = -ENOMSG;
+		fprintf(stderr, "Unsupported padding: %s\n",
+			info->padding->name);
+		goto out;
+	}
+
+	if (EVP_PKEY_CTX_set_rsa_padding(ckey, pad) <= 0) {
+		ret = -EINVAL;
+		fprintf(stderr, "padding setup has failed: %s\n",
+			ERR_error_string(ERR_get_error(), NULL));
+		goto out;
+	}
+
+	for (i=0 ; i < region_count ; ++i) {
+		if (EVP_DigestVerifyUpdate(ctx, region[i].data,
+					   region[i].size) <= 0) {
+			ret = -EINVAL;
+			fprintf(stderr, "Hashing data failed: %s\n",
+				ERR_error_string(ERR_get_error(), NULL));
+			goto out;
+		}
+	}
+
+	if (EVP_DigestVerifyFinal(ctx, sig, sig_len) <= 0) {
+		ret = -EINVAL;
+		fprintf(stderr, "Verifying digest failed: %s\n",
+			ERR_error_string(ERR_get_error(), NULL));
+		goto out;
+	}
+out:
+	if (ctx)
+		EVP_MD_CTX_free(ctx);
+
+	if (ret)
+		fprintf(stderr, "Failed to verify signature\n");
+
+	return ret;
+}
+#endif
diff --git a/tools/imx8image.c b/tools/imx8image.c
index 15510d3e712..0135b190951 100644
--- a/tools/imx8image.c
+++ b/tools/imx8image.c
@@ -290,6 +290,7 @@ static uint32_t parse_cfg_file(image_t *param_stack, char *name)
 		}
 	}
 
+	free(line);
 	fclose(fd);
 	return 0;
 }
diff --git a/tools/imx8mimage.c b/tools/imx8mimage.c
index d60d293e649..0f24ba75c0f 100644
--- a/tools/imx8mimage.c
+++ b/tools/imx8mimage.c
@@ -206,6 +206,7 @@ static uint32_t parse_cfg_file(char *name)
 		}
 	}
 
+	free(line);
 	fclose(fd);
 	return 0;
 }
diff --git a/tools/imximage.c b/tools/imximage.c
index 467d9f27d2a..55231caf8f3 100644
--- a/tools/imximage.c
+++ b/tools/imximage.c
@@ -783,6 +783,7 @@ static uint32_t parse_cfg_file(struct imx_header *imxhdr, char *name)
 	}
 
 	(*set_dcd_rst)(imxhdr, dcd_len, name, lineno);
+	free(line);
 	fclose(fd);
 
 	/* Exit if there is no BOOT_FROM field specifying the flash_offset */
diff --git a/tools/kwbimage.c b/tools/kwbimage.c
index d1cbced28fc..3dcf5ba66b9 100644
--- a/tools/kwbimage.c
+++ b/tools/kwbimage.c
@@ -1653,6 +1653,12 @@ static int image_create_config_parse_oneline(char *line,
 	char *unknown_msg = "Ignoring unknown line '%s'\n";
 
 	keyword = strtok_r(line, delimiters, &saveptr);
+
+	if (!keyword) {
+		fprintf(stderr, "Parameter missing in line '%s'\n", line);
+		return -1;
+	}
+
 	keyword_id = recognize_keyword(keyword);
 
 	if (!keyword_id) {
diff --git a/tools/microcode-tool.py b/tools/microcode-tool.py
index 24c02c4fca1..b726794751a 100755
--- a/tools/microcode-tool.py
+++ b/tools/microcode-tool.py
@@ -279,6 +279,9 @@ def MicrocodeTool():
 
     if (not not options.mcfile) != (not not options.mcfile):
         parser.error("You must specify either header files or a microcode file, not both")
+    date = None
+    microcodes = None
+    license_text = None
     if options.headerfile:
         date, license_text, microcodes = ParseHeaderFiles(options.headerfile)
     elif options.mcfile:
diff --git a/tools/mkimage.h b/tools/mkimage.h
index 15741f250fd..5d6bcc9301a 100644
--- a/tools/mkimage.h
+++ b/tools/mkimage.h
@@ -37,6 +37,10 @@ static inline void *map_sysmem(ulong paddr, unsigned long len)
 	return (void *)(uintptr_t)paddr;
 }
 
+static inline void unmap_sysmem(const void *vaddr)
+{
+}
+
 static inline ulong map_to_sysmem(const void *ptr)
 {
 	return (ulong)(uintptr_t)ptr;
diff --git a/tools/patman/__init__.py b/tools/patman/__init__.py
index 08eeffdf6d2..6de0e9fba10 100644
--- a/tools/patman/__init__.py
+++ b/tools/patman/__init__.py
@@ -1,5 +1,5 @@
 # SPDX-License-Identifier: GPL-2.0+
 
 __all__ = ['checkpatch', 'commit', 'control', 'func_test', 'get_maintainer',
-           'gitutil', '__main__', 'patchstream', 'project', 'series',
-           'settings','setup', 'status', 'test_checkpatch', 'test_settings']
+           '__main__', 'patchstream', 'project', 'series',
+           'settings', 'setup', 'status', 'test_checkpatch', 'test_settings']
diff --git a/tools/patman/__main__.py b/tools/patman/__main__.py
index f645b38b647..36f1c08507c 100755
--- a/tools/patman/__main__.py
+++ b/tools/patman/__main__.py
@@ -49,7 +49,7 @@ def run_patman():
         result = test_util.run_test_suites(
             'patman', False, False, False, None, None, None,
             [test_checkpatch.TestPatch, func_test.TestFunctional,
-             'gitutil', 'settings'])
+             'settings'])
 
         sys.exit(0 if result.wasSuccessful() else 1)
 
diff --git a/tools/patman/checkpatch.py b/tools/patman/checkpatch.py
index e03cac115e4..2975881705c 100644
--- a/tools/patman/checkpatch.py
+++ b/tools/patman/checkpatch.py
@@ -8,8 +8,8 @@ import os
 import re
 import sys
 
-from patman import gitutil
 from u_boot_pylib import command
+from u_boot_pylib import gitutil
 from u_boot_pylib import terminal
 
 EMACS_PREFIX = r'(?:[0-9]{4}.*\.patch:[0-9]+: )?'
diff --git a/tools/patman/cmdline.py b/tools/patman/cmdline.py
index d6496c0cb78..562bc823f60 100644
--- a/tools/patman/cmdline.py
+++ b/tools/patman/cmdline.py
@@ -13,8 +13,8 @@ import os
 import pathlib
 import sys
 
-from patman import gitutil
 from patman import project
+from u_boot_pylib import gitutil
 from patman import settings
 
 PATMAN_DIR = pathlib.Path(__file__).parent
diff --git a/tools/patman/control.py b/tools/patman/control.py
index b292da9dc27..fb5a4246ced 100644
--- a/tools/patman/control.py
+++ b/tools/patman/control.py
@@ -12,8 +12,8 @@ import os
 import sys
 
 from patman import checkpatch
-from patman import gitutil
 from patman import patchstream
+from u_boot_pylib import gitutil
 from u_boot_pylib import terminal
 
 
diff --git a/tools/patman/func_test.py b/tools/patman/func_test.py
index af6c025a441..bf333dc557b 100644
--- a/tools/patman/func_test.py
+++ b/tools/patman/func_test.py
@@ -18,11 +18,11 @@ import unittest
 
 from patman.commit import Commit
 from patman import control
-from patman import gitutil
 from patman import patchstream
 from patman.patchstream import PatchStream
 from patman.series import Series
 from patman import settings
+from u_boot_pylib import gitutil
 from u_boot_pylib import terminal
 from u_boot_pylib import tools
 from u_boot_pylib.test_util import capture_sys_output
diff --git a/tools/patman/get_maintainer.py b/tools/patman/get_maintainer.py
index 8df3d124bac..200ee96551d 100644
--- a/tools/patman/get_maintainer.py
+++ b/tools/patman/get_maintainer.py
@@ -7,8 +7,8 @@ import os
 import shlex
 import shutil
 
-from patman import gitutil
 from u_boot_pylib import command
+from u_boot_pylib import gitutil
 
 
 def find_get_maintainer(script_file_name):
diff --git a/tools/patman/patchstream.py b/tools/patman/patchstream.py
index 4955f6aaab9..490d382045b 100644
--- a/tools/patman/patchstream.py
+++ b/tools/patman/patchstream.py
@@ -15,9 +15,9 @@ import shutil
 import tempfile
 
 from patman import commit
-from patman import gitutil
 from patman.series import Series
 from u_boot_pylib import command
+from u_boot_pylib import gitutil
 
 # Tags that we detect and remove
 RE_REMOVE = re.compile(r'^BUG=|^TEST=|^BRANCH=|^Review URL:'
@@ -711,7 +711,7 @@ def get_list(commit_range, git_dir=None, count=None):
     """
     params = gitutil.log_cmd(commit_range, reverse=True, count=count,
                             git_dir=git_dir)
-    return command.run_pipe([params], capture=True).stdout
+    return command.run_one(*params, capture=True).stdout
 
 def get_metadata_for_list(commit_range, git_dir=None, count=None,
                           series=None, allow_overwrite=False):
diff --git a/tools/patman/project.py b/tools/patman/project.py
index 4459042b5d4..d6143a67066 100644
--- a/tools/patman/project.py
+++ b/tools/patman/project.py
@@ -4,7 +4,7 @@
 
 import os.path
 
-from patman import gitutil
+from u_boot_pylib import gitutil
 
 def detect_project():
     """Autodetect the name of the current project.
diff --git a/tools/patman/requirements.txt b/tools/patman/requirements.txt
new file mode 100644
index 00000000000..e8cbc6cf0c3
--- /dev/null
+++ b/tools/patman/requirements.txt
@@ -0,0 +1,5 @@
+ConfigParser==7.1.0
+importlib_resources==6.5.2
+pygit2==1.13.3
+Requests==2.32.3
+setuptools==75.8.0
diff --git a/tools/patman/series.py b/tools/patman/series.py
index 6866e1dbd08..d7f2f010f5d 100644
--- a/tools/patman/series.py
+++ b/tools/patman/series.py
@@ -12,8 +12,8 @@ import sys
 import time
 
 from patman import get_maintainer
-from patman import gitutil
 from patman import settings
+from u_boot_pylib import gitutil
 from u_boot_pylib import terminal
 from u_boot_pylib import tools
 
diff --git a/tools/patman/settings.py b/tools/patman/settings.py
index 68c93e313b3..d66b22be1df 100644
--- a/tools/patman/settings.py
+++ b/tools/patman/settings.py
@@ -12,7 +12,7 @@ import argparse
 import os
 import re
 
-from patman import gitutil
+from u_boot_pylib import gitutil
 
 """Default settings per-project.
 
diff --git a/tools/patman/test_checkpatch.py b/tools/patman/test_checkpatch.py
index db7860f551d..3bf16febbf6 100644
--- a/tools/patman/test_checkpatch.py
+++ b/tools/patman/test_checkpatch.py
@@ -11,10 +11,10 @@ import tempfile
 import unittest
 
 from patman import checkpatch
-from patman import gitutil
 from patman import patchstream
 from patman import series
 from patman import commit
+from u_boot_pylib import gitutil
 
 
 class Line:
@@ -530,4 +530,3 @@ index 0000000..2234c87
 
 if __name__ == "__main__":
     unittest.main()
-    gitutil.RunTests()
diff --git a/tools/preload_check_sign.c b/tools/preload_check_sign.c
new file mode 100644
index 00000000000..ebead459273
--- /dev/null
+++ b/tools/preload_check_sign.c
@@ -0,0 +1,160 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Check a file including a preload header including a signature
+ *
+ * Copyright (c) 2025 Paul HENRYS <paul.henrys_ext@softathome.com>
+ *
+ * Binman makes it possible to generate a preload header signing part or the
+ * complete file. The tool preload_check_sign allows to verify and authenticate
+ * a file starting with a preload header.
+ */
+#include <stdio.h>
+#include <unistd.h>
+#include <openssl/pem.h>
+#include <openssl/evp.h>
+#include <openssl/err.h>
+#include <image.h>
+
+extern void image_pre_load_sig_set_info(struct image_sig_info *info);
+extern int image_pre_load_sig(ulong addr);
+
+static void usage(char *cmdname)
+{
+	fprintf(stderr, "Usage: %s -f file -k PEM key file\n"
+			"          -f ==> set file which should be checked\n"
+			"          -k ==> PEM key file\n"
+			"          -a ==> algo (default: sha256,rsa2048)\n"
+			"          -p ==> padding (default: pkcs-1.5)\n"
+			"          -h ==> help\n",
+		cmdname);
+	exit(EXIT_FAILURE);
+}
+
+int main(int argc, char **argv)
+{
+	int ret = 0;
+	char cmdname[256];
+	char *file = NULL;
+	char *keyfile = NULL;
+	int c;
+	FILE *fp = NULL;
+	FILE *fp_key = NULL;
+	size_t bytes;
+	long filesize;
+	void *buffer = NULL;
+	EVP_PKEY *pkey = NULL;
+	char *algo = "sha256,rsa2048";
+	char *padding = "pkcs-1.5";
+	struct image_sig_info info = {0};
+
+	strncpy(cmdname, *argv, sizeof(cmdname) - 1);
+	cmdname[sizeof(cmdname) - 1] = '\0';
+	while ((c = getopt(argc, argv, "f:k:a:p:h")) != -1)
+		switch (c) {
+		case 'f':
+			file = optarg;
+			break;
+		case 'k':
+			keyfile = optarg;
+			break;
+		case 'a':
+			algo = optarg;
+			break;
+		case 'p':
+			padding = optarg;
+			break;
+		default:
+			usage(cmdname);
+			break;
+	}
+
+	if (!file) {
+		fprintf(stderr, "%s: Missing file\n", *argv);
+		usage(*argv);
+	}
+
+	if (!keyfile) {
+		fprintf(stderr, "%s: Missing key file\n", *argv);
+		usage(*argv);
+	}
+
+	fp = fopen(file, "r");
+	if (!fp) {
+		fprintf(stderr, "Error opening file: %s\n", file);
+		ret = EXIT_FAILURE;
+		goto out;
+	}
+
+	fseek(fp, 0, SEEK_END);
+	filesize = ftell(fp);
+	rewind(fp);
+
+	buffer = malloc(filesize);
+	if (!buffer) {
+		fprintf(stderr, "Memory allocation failed");
+		ret = EXIT_FAILURE;
+		goto out;
+	}
+
+	bytes = fread(buffer, 1, filesize, fp);
+	if (bytes != filesize) {
+		fprintf(stderr, "Error reading file\n");
+		ret = EXIT_FAILURE;
+		goto out;
+	}
+
+	fp_key = fopen(keyfile, "r");
+	if (!fp_key) {
+		fprintf(stderr, "Error opening file: %s\n", keyfile);
+		ret = EXIT_FAILURE;
+		goto out;
+	}
+
+	/* Attempt to read the private key */
+	pkey = PEM_read_PrivateKey(fp_key, NULL, NULL, NULL);
+	if (!pkey) {
+		/* If private key reading fails, try reading as a public key */
+		fseek(fp_key, 0, SEEK_SET);
+		pkey = PEM_read_PUBKEY(fp_key, NULL, NULL, NULL);
+	}
+	if (!pkey) {
+		fprintf(stderr, "Unable to retrieve the public key: %s\n",
+			ERR_error_string(ERR_get_error(), NULL));
+		ret = EXIT_FAILURE;
+		goto out;
+	}
+
+	info.algo_name = algo;
+	info.padding_name = padding;
+	info.key = (uint8_t *)pkey;
+	info.mandatory = 1;
+	info.sig_size = EVP_PKEY_size(pkey);
+	if (info.sig_size < 0) {
+		fprintf(stderr, "Fail to retrieve the signature size: %s\n",
+			ERR_error_string(ERR_get_error(), NULL));
+		ret = EXIT_FAILURE;
+		goto out;
+	}
+
+	/* Compute signature information */
+	info.sig_info.name     = info.algo_name;
+	info.sig_info.padding  = image_get_padding_algo(info.padding_name);
+	info.sig_info.checksum = image_get_checksum_algo(info.sig_info.name);
+	info.sig_info.crypto   = image_get_crypto_algo(info.sig_info.name);
+	info.sig_info.key      = info.key;
+	info.sig_info.keylen   = info.key_len;
+
+	/* Check the signature */
+	image_pre_load_sig_set_info(&info);
+	ret = image_pre_load_sig((ulong)buffer);
+out:
+	if (fp)
+		fclose(fp);
+	if (fp_key)
+		fclose(fp_key);
+	if (info.key)
+		EVP_PKEY_free(pkey);
+	free(buffer);
+
+	exit(ret);
+}
diff --git a/tools/proftool.c b/tools/proftool.c
index af2cdb6d584..c7b427f3078 100644
--- a/tools/proftool.c
+++ b/tools/proftool.c
@@ -676,6 +676,7 @@ static int read_trace_config(FILE *fin)
 		if (!tok) {
 			error("Invalid trace config data on line %d\n",
 			      linenum);
+			free(line);
 			return -1;
 		}
 		if (0 == strcmp(tok, "include-func")) {
@@ -685,6 +686,7 @@ static int read_trace_config(FILE *fin)
 		} else {
 			error("Unknown command in trace config data line %d\n",
 			      linenum);
+			free(line);
 			return -1;
 		}
 
@@ -692,6 +694,7 @@ static int read_trace_config(FILE *fin)
 		if (!tok) {
 			error("Missing pattern in trace config data line %d\n",
 			      linenum);
+			free(line);
 			return -1;
 		}
 
diff --git a/tools/rmboard.py b/tools/rmboard.py
index 0c56b149e0f..594fd89b8d7 100755
--- a/tools/rmboard.py
+++ b/tools/rmboard.py
@@ -43,18 +43,16 @@ def rm_kconfig_include(path):
     Args:
         path: Path to search for and remove
     """
-    cmd = ['git', 'grep', path]
-    stdout = command.run_pipe([cmd], capture=True, raise_on_error=False).stdout
+    stdout = command.output('git', 'grep', path, raise_on_error=False)
     if not stdout:
         return
     fname = stdout.split(':')[0]
 
     print("Fixing up '%s' to remove reference to '%s'" % (fname, path))
-    cmd = ['sed', '-i', '\|%s|d' % path, fname]
-    stdout = command.run_pipe([cmd], capture=True).stdout
+    stdout = command.run_one('sed', '-i', rf'\|{path}|d', fname,
+                             capture=True).stdout
 
-    cmd = ['git', 'add', fname]
-    stdout = command.run_pipe([cmd], capture=True).stdout
+    stdout = command.output('git', 'add', fname)
 
 def rm_board(board):
     """Create a commit which removes a single board
@@ -68,8 +66,7 @@ def rm_board(board):
     """
 
     # Find all MAINTAINERS and Kconfig files which mention the board
-    cmd = ['git', 'grep', '-l', board]
-    stdout = command.run_pipe([cmd], capture=True).stdout
+    stdout = command.output('git', 'grep', '-l', board)
     maintain = []
     kconfig = []
     for line in stdout.splitlines():
@@ -109,16 +106,14 @@ def rm_board(board):
     # Search for Kconfig files in the resulting list. Remove any 'source' lines
     # which reference Kconfig files we want to remove
     for path in real:
-        cmd = ['find', path]
-        stdout = (command.run_pipe([cmd], capture=True, raise_on_error=False).
-                  stdout)
+        stdout = command.output('find', path, raise_on_error=False)
         for fname in stdout.splitlines():
             if fname.endswith('Kconfig'):
                 rm_kconfig_include(fname)
 
     # Remove unwanted files
     cmd = ['git', 'rm', '-r'] + real
-    stdout = command.run_pipe([cmd], capture=True).stdout
+    stdout = command.output(*cmd, capture=True)
 
     ## Change the messages as needed
     msg = '''arm: Remove %s board
@@ -131,13 +126,11 @@ Remove it.
         msg += 'Patch-cc: %s\n' % name
 
     # Create the commit
-    cmd = ['git', 'commit', '-s', '-m', msg]
-    stdout = command.run_pipe([cmd], capture=True).stdout
+    stdout = command.output('git', 'commit', '-s', '-m', msg)
 
     # Check if the board is mentioned anywhere else. The user will need to deal
     # with this
-    cmd = ['git', 'grep', '-il', board]
-    print(command.run_pipe([cmd], capture=True, raise_on_error=False).stdout)
+    print(command.output('git', 'grep', '-il', board, raise_on_error=False))
     print(' '.join(cmd))
 
 for board in sys.argv[1:]:
diff --git a/tools/u_boot_pylib/__init__.py b/tools/u_boot_pylib/__init__.py
index 63c88e85ec0..807a62e0743 100644
--- a/tools/u_boot_pylib/__init__.py
+++ b/tools/u_boot_pylib/__init__.py
@@ -1,4 +1,4 @@
 # SPDX-License-Identifier: GPL-2.0+
 
-__all__ = ['command', 'cros_subprocess','terminal', 'test_util', 'tools',
-	   'tout']
+__all__ = ['command', 'cros_subprocess', 'gitutil', 'terminal', 'test_util',
+           'tools', 'tout']
diff --git a/tools/u_boot_pylib/__main__.py b/tools/u_boot_pylib/__main__.py
index 8f98d7bd9f8..c0762bca733 100755
--- a/tools/u_boot_pylib/__main__.py
+++ b/tools/u_boot_pylib/__main__.py
@@ -13,7 +13,6 @@ if __name__ == "__main__":
     sys.path.append(os.path.join(our_path, '..'))
 
     # Run tests
-    from u_boot_pylib import terminal
     from u_boot_pylib import test_util
 
     result = test_util.run_test_suites(
diff --git a/tools/u_boot_pylib/command.py b/tools/u_boot_pylib/command.py
index bbe95d86122..0e247355ef6 100644
--- a/tools/u_boot_pylib/command.py
+++ b/tools/u_boot_pylib/command.py
@@ -1,21 +1,44 @@
 # SPDX-License-Identifier: GPL-2.0+
-# Copyright (c) 2011 The Chromium OS Authors.
-#
+"""
+Shell command ease-ups for Python
 
-import os
+Copyright (c) 2011 The Chromium OS Authors.
+"""
+
+import subprocess
 
 from u_boot_pylib import cros_subprocess
 
-"""Shell command ease-ups for Python."""
+# This permits interception of RunPipe for test purposes. If it is set to
+# a function, then that function is called with the pipe list being
+# executed. Otherwise, it is assumed to be a CommandResult object, and is
+# returned as the result for every run_pipe() call.
+# When this value is None, commands are executed as normal.
+TEST_RESULT = None
+
+
+class CommandExc(Exception):
+    """Reports an exception to the caller"""
+    def __init__(self, msg, result):
+        """Set up a new exception object
+
+        Args:
+            result (CommandResult): Execution result so far
+        """
+        super().__init__(msg)
+        self.result = result
+
 
 class CommandResult:
     """A class which captures the result of executing a command.
 
     Members:
-        stdout: stdout obtained from command, as a string
-        stderr: stderr obtained from command, as a string
-        return_code: Return code from command
-        exception: Exception received, or None if all ok
+        stdout (bytes): stdout obtained from command, as a string
+        stderr (bytes): stderr obtained from command, as a string
+        combined (bytes): stdout and stderr interleaved
+        return_code (int): Return code from command
+        exception (Exception): Exception received, or None if all ok
+        output (str or None): Returns output as a single line if requested
     """
     def __init__(self, stdout='', stderr='', combined='', return_code=0,
                  exception=None):
@@ -24,8 +47,16 @@ class CommandResult:
         self.combined = combined
         self.return_code = return_code
         self.exception = exception
+        self.output = None
 
     def to_output(self, binary):
+        """Converts binary output to its final form
+
+        Args:
+            binary (bool): True to report binary output, False to use strings
+        Returns:
+            self
+        """
         if not binary:
             self.stdout = self.stdout.decode('utf-8')
             self.stderr = self.stderr.decode('utf-8')
@@ -33,49 +64,47 @@ class CommandResult:
         return self
 
 
-# This permits interception of RunPipe for test purposes. If it is set to
-# a function, then that function is called with the pipe list being
-# executed. Otherwise, it is assumed to be a CommandResult object, and is
-# returned as the result for every run_pipe() call.
-# When this value is None, commands are executed as normal.
-test_result = None
-
-def run_pipe(pipe_list, infile=None, outfile=None,
-            capture=False, capture_stderr=False, oneline=False,
-            raise_on_error=True, cwd=None, binary=False,
-            output_func=None, **kwargs):
+def run_pipe(pipe_list, infile=None, outfile=None, capture=False,
+             capture_stderr=False, oneline=False, raise_on_error=True, cwd=None,
+             binary=False, output_func=None, **kwargs):
     """
     Perform a command pipeline, with optional input/output filenames.
 
     Args:
-        pipe_list: List of command lines to execute. Each command line is
-            piped into the next, and is itself a list of strings. For
+        pipe_list (list of list): List of command lines to execute. Each command
+            line is piped into the next, and is itself a list of strings. For
             example [ ['ls', '.git'] ['wc'] ] will pipe the output of
             'ls .git' into 'wc'.
-        infile: File to provide stdin to the pipeline
-        outfile: File to store stdout
-        capture: True to capture output
-        capture_stderr: True to capture stderr
-        oneline: True to strip newline chars from output
-        output_func: Output function to call with each output fragment
-            (if it returns True the function terminates)
-        kwargs: Additional keyword arguments to cros_subprocess.Popen()
+        infile (str): File to provide stdin to the pipeline
+        outfile (str): File to store stdout
+        capture (bool): True to capture output
+        capture_stderr (bool): True to capture stderr
+        oneline (bool): True to strip newline chars from output
+        raise_on_error (bool): True to raise on an error, False to return it in
+            the CommandResult
+        cwd (str or None): Directory to run the command in
+        binary (bool): True to report binary output, False to use strings
+        output_func (function): Output function to call with each output
+            fragment (if it returns True the function terminates)
+        **kwargs: Additional keyword arguments to cros_subprocess.Popen()
     Returns:
         CommandResult object
+    Raises:
+        CommandExc if an exception happens
     """
-    if test_result:
-        if hasattr(test_result, '__call__'):
+    if TEST_RESULT:
+        if hasattr(TEST_RESULT, '__call__'):
             # pylint: disable=E1102
-            result = test_result(pipe_list=pipe_list)
+            result = TEST_RESULT(pipe_list=pipe_list)
             if result:
                 return result
         else:
-            return test_result
+            return TEST_RESULT
         # No result: fall through to normal processing
     result = CommandResult(b'', b'', b'')
     last_pipe = None
     pipeline = list(pipe_list)
-    user_pipestr =  '|'.join([' '.join(pipe) for pipe in pipe_list])
+    user_pipestr = '|'.join([' '.join(pipe) for pipe in pipe_list])
     kwargs['stdout'] = None
     kwargs['stderr'] = None
     while pipeline:
@@ -96,7 +125,8 @@ def run_pipe(pipe_list, infile=None, outfile=None,
         except Exception as err:
             result.exception = err
             if raise_on_error:
-                raise Exception("Error running '%s': %s" % (user_pipestr, str))
+                raise CommandExc(f"Error running '{user_pipestr}': {err}",
+                                 result) from err
             result.return_code = 255
             return result.to_output(binary)
 
@@ -107,31 +137,84 @@ def run_pipe(pipe_list, infile=None, outfile=None,
             result.output = result.stdout.rstrip(b'\r\n')
     result.return_code = last_pipe.wait()
     if raise_on_error and result.return_code:
-        raise Exception("Error running '%s'" % user_pipestr)
+        raise CommandExc(f"Error running '{user_pipestr}'", result)
     return result.to_output(binary)
 
+
 def output(*cmd, **kwargs):
+    """Run a command and return its output
+
+    Args:
+        *cmd (list of str): Command to run
+        **kwargs (dict of args): Extra arguments to pass in
+
+    Returns:
+        str: command output
+    """
     kwargs['raise_on_error'] = kwargs.get('raise_on_error', True)
     return run_pipe([cmd], capture=True, **kwargs).stdout
 
+
 def output_one_line(*cmd, **kwargs):
     """Run a command and output it as a single-line string
 
-    The command us expected to produce a single line of output
+    The command is expected to produce a single line of output
+
+    Args:
+        *cmd (list of str): Command to run
+        **kwargs (dict of args): Extra arguments to pass in
 
     Returns:
-        String containing output of command
+        str: output of command with all newlines removed
     """
     raise_on_error = kwargs.pop('raise_on_error', True)
     result = run_pipe([cmd], capture=True, oneline=True,
-                     raise_on_error=raise_on_error, **kwargs).stdout.strip()
+                      raise_on_error=raise_on_error, **kwargs).stdout.strip()
     return result
 
+
 def run(*cmd, **kwargs):
+    """Run a command
+
+    Note that you must add 'capture' to kwargs to obtain non-empty output
+
+    Args:
+        *cmd (list of str): Command to run
+        **kwargs (dict of args): Extra arguments to pass in
+
+    Returns:
+        str: output of command
+    """
     return run_pipe([cmd], **kwargs).stdout
 
+
+def run_one(*cmd, **kwargs):
+    """Run a single command
+
+    Note that you must add 'capture' to kwargs to obtain non-empty output
+
+    Args:
+        *cmd (list of str): Command to run
+        **kwargs (dict of args): Extra arguments to pass in
+
+    Returns:
+        CommandResult: output of command
+    """
+    return run_pipe([cmd], **kwargs)
+
+
 def run_list(cmd):
+    """Run a command and return its output
+
+    Args:
+        cmd (list of str): Command to run
+
+    Returns:
+        str: output of command
+    """
     return run_pipe([cmd], capture=True).stdout
 
+
 def stop_all():
+    """Stop all subprocesses initiated with cros_subprocess"""
     cros_subprocess.stay_alive = False
diff --git a/tools/patman/gitutil.py b/tools/u_boot_pylib/gitutil.py
index 10ea5ff39f5..5e3e98ac9a6 100644
--- a/tools/patman/gitutil.py
+++ b/tools/u_boot_pylib/gitutil.py
@@ -10,7 +10,7 @@ from u_boot_pylib import command
 from u_boot_pylib import terminal
 
 # True to use --no-decorate - we check this in setup()
-use_no_decorate = True
+USE_NO_DECORATE = True
 
 
 def log_cmd(commit_range, git_dir=None, oneline=False, reverse=False,
@@ -18,11 +18,11 @@ def log_cmd(commit_range, git_dir=None, oneline=False, reverse=False,
     """Create a command to perform a 'git log'
 
     Args:
-        commit_range: Range expression to use for log, None for none
-        git_dir: Path to git repository (None to use default)
-        oneline: True to use --oneline, else False
-        reverse: True to reverse the log (--reverse)
-        count: Number of commits to list, or None for no limit
+        commit_range (str): Range expression to use for log, None for none
+        git_dir (str): Path to git repository (None to use default)
+        oneline (bool): True to use --oneline, else False
+        reverse (bool): True to reverse the log (--reverse)
+        count (int or None): Number of commits to list, or None for no limit
     Return:
         List containing command and arguments to run
     """
@@ -32,12 +32,12 @@ def log_cmd(commit_range, git_dir=None, oneline=False, reverse=False,
     cmd += ['--no-pager', 'log', '--no-color']
     if oneline:
         cmd.append('--oneline')
-    if use_no_decorate:
+    if USE_NO_DECORATE:
         cmd.append('--no-decorate')
     if reverse:
         cmd.append('--reverse')
     if count is not None:
-        cmd.append('-n%d' % count)
+        cmd.append(f'-n{count}')
     if commit_range:
         cmd.append(commit_range)
 
@@ -55,22 +55,22 @@ def count_commits_to_branch(branch):
     since then.
 
     Args:
-        branch: Branch to count from (None for current branch)
+        branch (str or None): Branch to count from (None for current branch)
 
     Return:
         Number of patches that exist on top of the branch
     """
     if branch:
-        us, msg = get_upstream('.git', branch)
-        rev_range = '%s..%s' % (us, branch)
+        us, _ = get_upstream('.git', branch)
+        rev_range = f'{us}..{branch}'
     else:
         rev_range = '@{upstream}..'
-    pipe = [log_cmd(rev_range, oneline=True)]
-    result = command.run_pipe(pipe, capture=True, capture_stderr=True,
-                              oneline=True, raise_on_error=False)
+    cmd = log_cmd(rev_range, oneline=True)
+    result = command.run_one(*cmd, capture=True, capture_stderr=True,
+                             oneline=True, raise_on_error=False)
     if result.return_code:
-        raise ValueError('Failed to determine upstream: %s' %
-                         result.stderr.strip())
+        raise ValueError(
+            f'Failed to determine upstream: {result.stderr.strip()}')
     patch_count = len(result.stdout.splitlines())
     return patch_count
 
@@ -79,13 +79,12 @@ def name_revision(commit_hash):
     """Gets the revision name for a commit
 
     Args:
-        commit_hash: Commit hash to look up
+        commit_hash (str): Commit hash to look up
 
     Return:
         Name of revision, if any, else None
     """
-    pipe = ['git', 'name-rev', commit_hash]
-    stdout = command.run_pipe([pipe], capture=True, oneline=True).stdout
+    stdout = command.output_one_line('git', 'name-rev', commit_hash)
 
     # We expect a commit, a space, then a revision name
     name = stdout.split(' ')[1].strip()
@@ -100,35 +99,35 @@ def guess_upstream(git_dir, branch):
     'git name-rev' returns a plain branch name, with no ! or ^ modifiers.
 
     Args:
-        git_dir: Git directory containing repo
-        branch: Name of branch
+        git_dir (str): Git directory containing repo
+        branch (str): Name of branch
 
     Returns:
         Tuple:
             Name of upstream branch (e.g. 'upstream/master') or None if none
             Warning/error message, or None if none
     """
-    pipe = [log_cmd(branch, git_dir=git_dir, oneline=True, count=100)]
-    result = command.run_pipe(pipe, capture=True, capture_stderr=True,
-                              raise_on_error=False)
+    cmd = log_cmd(branch, git_dir=git_dir, oneline=True, count=100)
+    result = command.run_one(*cmd, capture=True, capture_stderr=True,
+                             raise_on_error=False)
     if result.return_code:
-        return None, "Branch '%s' not found" % branch
+        return None, f"Branch '{branch}' not found"
     for line in result.stdout.splitlines()[1:]:
         commit_hash = line.split(' ')[0]
         name = name_revision(commit_hash)
         if '~' not in name and '^' not in name:
             if name.startswith('remotes/'):
                 name = name[8:]
-            return name, "Guessing upstream as '%s'" % name
-    return None, "Cannot find a suitable upstream for branch '%s'" % branch
+            return name, f"Guessing upstream as '{name}'"
+    return None, f"Cannot find a suitable upstream for branch '{branch}'"
 
 
 def get_upstream(git_dir, branch):
     """Returns the name of the upstream for a branch
 
     Args:
-        git_dir: Git directory containing repo
-        branch: Name of branch
+        git_dir (str): Git directory containing repo
+        branch (str): Name of branch
 
     Returns:
         Tuple:
@@ -137,31 +136,30 @@ def get_upstream(git_dir, branch):
     """
     try:
         remote = command.output_one_line('git', '--git-dir', git_dir, 'config',
-                                         'branch.%s.remote' % branch)
+                                         f'branch.{branch}.remote')
         merge = command.output_one_line('git', '--git-dir', git_dir, 'config',
-                                        'branch.%s.merge' % branch)
-    except Exception:
+                                        f'branch.{branch}.merge')
+    except command.CommandExc:
         upstream, msg = guess_upstream(git_dir, branch)
         return upstream, msg
 
     if remote == '.':
         return merge, None
-    elif remote and merge:
+    if remote and merge:
         # Drop the initial refs/heads from merge
         leaf = merge.split('/', maxsplit=2)[2:]
-        return '%s/%s' % (remote, '/'.join(leaf)), None
-    else:
-        raise ValueError("Cannot determine upstream branch for branch "
-                         "'%s' remote='%s', merge='%s'"
-                         % (branch, remote, merge))
+        return f'{remote}/{"/".join(leaf)}', None
+    raise ValueError("Cannot determine upstream branch for branch "
+                     f"'{branch}' remote='{remote}', merge='{merge}'")
 
 
 def get_range_in_branch(git_dir, branch, include_upstream=False):
     """Returns an expression for the commits in the given branch.
 
     Args:
-        git_dir: Directory containing git repo
-        branch: Name of branch
+        git_dir (str): Directory containing git repo
+        branch (str): Name of branch
+        include_upstream (bool): Include the upstream commit as well
     Return:
         Expression in the form 'upstream..branch' which can be used to
         access the commits. If the branch does not exist, returns None.
@@ -169,7 +167,7 @@ def get_range_in_branch(git_dir, branch, include_upstream=False):
     upstream, msg = get_upstream(git_dir, branch)
     if not upstream:
         return None, msg
-    rstr = '%s%s..%s' % (upstream, '~' if include_upstream else '', branch)
+    rstr = f"{upstream}{'~' if include_upstream else ''}..{branch}"
     return rstr, msg
 
 
@@ -177,17 +175,17 @@ def count_commits_in_range(git_dir, range_expr):
     """Returns the number of commits in the given range.
 
     Args:
-        git_dir: Directory containing git repo
-        range_expr: Range to check
+        git_dir (str): Directory containing git repo
+        range_expr (str): Range to check
     Return:
         Number of patches that exist in the supplied range or None if none
         were found
     """
-    pipe = [log_cmd(range_expr, git_dir=git_dir, oneline=True)]
-    result = command.run_pipe(pipe, capture=True, capture_stderr=True,
-                              raise_on_error=False)
+    cmd = log_cmd(range_expr, git_dir=git_dir, oneline=True)
+    result = command.run_one(*cmd, capture=True, capture_stderr=True,
+                             raise_on_error=False)
     if result.return_code:
-        return None, "Range '%s' not found or is invalid" % range_expr
+        return None, f"Range '{range_expr}' not found or is invalid"
     patch_count = len(result.stdout.splitlines())
     return patch_count, None
 
@@ -196,8 +194,9 @@ def count_commits_in_branch(git_dir, branch, include_upstream=False):
     """Returns the number of commits in the given branch.
 
     Args:
-        git_dir: Directory containing git repo
-        branch: Name of branch
+        git_dir (str): Directory containing git repo
+        branch (str): Name of branch
+        include_upstream (bool): Include the upstream commit as well
     Return:
         Number of patches that exist on top of the branch, or None if the
         branch does not exist.
@@ -212,7 +211,7 @@ def count_commits(commit_range):
     """Returns the number of commits in the given range.
 
     Args:
-        commit_range: Range of commits to count (e.g. 'HEAD..base')
+        commit_range (str): Range of commits to count (e.g. 'HEAD..base')
     Return:
         Number of patches that exist on top of the branch
     """
@@ -227,7 +226,10 @@ def checkout(commit_hash, git_dir=None, work_tree=None, force=False):
     """Checkout the selected commit for this build
 
     Args:
-        commit_hash: Commit hash to check out
+        commit_hash (str): Commit hash to check out
+        git_dir (str): Directory containing git repo, or None for current dir
+        work_tree (str): Git worktree to use, or None if none
+        force (bool): True to force the checkout (git checkout -f)
     """
     pipe = ['git']
     if git_dir:
@@ -241,51 +243,52 @@ def checkout(commit_hash, git_dir=None, work_tree=None, force=False):
     result = command.run_pipe([pipe], capture=True, raise_on_error=False,
                               capture_stderr=True)
     if result.return_code != 0:
-        raise OSError('git checkout (%s): %s' % (pipe, result.stderr))
+        raise OSError(f'git checkout ({pipe}): {result.stderr}')
 
 
-def clone(git_dir, output_dir):
-    """Checkout the selected commit for this build
+def clone(repo, output_dir):
+    """Clone a repo
 
     Args:
-        commit_hash: Commit hash to check out
+        repo (str): Repo to clone (e.g. web address)
+        output_dir (str): Directory to close into
     """
-    pipe = ['git', 'clone', git_dir, '.']
-    result = command.run_pipe([pipe], capture=True, cwd=output_dir,
-                              capture_stderr=True)
+    result = command.run_one('git', 'clone', repo, '.', capture=True,
+                             cwd=output_dir, capture_stderr=True)
     if result.return_code != 0:
-        raise OSError('git clone: %s' % result.stderr)
+        raise OSError(f'git clone: {result.stderr}')
 
 
 def fetch(git_dir=None, work_tree=None):
     """Fetch from the origin repo
 
     Args:
-        commit_hash: Commit hash to check out
+        git_dir (str): Directory containing git repo, or None for current dir
+        work_tree (str or None): Git worktree to use, or None if none
     """
-    pipe = ['git']
+    cmd = ['git']
     if git_dir:
-        pipe.extend(['--git-dir', git_dir])
+        cmd.extend(['--git-dir', git_dir])
     if work_tree:
-        pipe.extend(['--work-tree', work_tree])
-    pipe.append('fetch')
-    result = command.run_pipe([pipe], capture=True, capture_stderr=True)
+        cmd.extend(['--work-tree', work_tree])
+    cmd.append('fetch')
+    result = command.run_one(*cmd, capture=True, capture_stderr=True)
     if result.return_code != 0:
-        raise OSError('git fetch: %s' % result.stderr)
+        raise OSError(f'git fetch: {result.stderr}')
 
 
 def check_worktree_is_available(git_dir):
     """Check if git-worktree functionality is available
 
     Args:
-        git_dir: The repository to test in
+        git_dir (str): The repository to test in
 
     Returns:
         True if git-worktree commands will work, False otherwise.
     """
-    pipe = ['git', '--git-dir', git_dir, 'worktree', 'list']
-    result = command.run_pipe([pipe], capture=True, capture_stderr=True,
-                              raise_on_error=False)
+    result = command.run_one('git', '--git-dir', git_dir, 'worktree', 'list',
+                             capture=True, capture_stderr=True,
+                             raise_on_error=False)
     return result.return_code == 0
 
 
@@ -293,30 +296,30 @@ def add_worktree(git_dir, output_dir, commit_hash=None):
     """Create and checkout a new git worktree for this build
 
     Args:
-        git_dir: The repository to checkout the worktree from
-        output_dir: Path for the new worktree
-        commit_hash: Commit hash to checkout
+        git_dir (str): The repository to checkout the worktree from
+        output_dir (str): Path for the new worktree
+        commit_hash (str): Commit hash to checkout
     """
     # We need to pass --detach to avoid creating a new branch
-    pipe = ['git', '--git-dir', git_dir, 'worktree', 'add', '.', '--detach']
+    cmd = ['git', '--git-dir', git_dir, 'worktree', 'add', '.', '--detach']
     if commit_hash:
-        pipe.append(commit_hash)
-    result = command.run_pipe([pipe], capture=True, cwd=output_dir,
-                              capture_stderr=True)
+        cmd.append(commit_hash)
+    result = command.run_one(*cmd, capture=True, cwd=output_dir,
+                             capture_stderr=True)
     if result.return_code != 0:
-        raise OSError('git worktree add: %s' % result.stderr)
+        raise OSError(f'git worktree add: {result.stderr}')
 
 
 def prune_worktrees(git_dir):
     """Remove administrative files for deleted worktrees
 
     Args:
-        git_dir: The repository whose deleted worktrees should be pruned
+        git_dir (str): The repository whose deleted worktrees should be pruned
     """
-    pipe = ['git', '--git-dir', git_dir, 'worktree', 'prune']
-    result = command.run_pipe([pipe], capture=True, capture_stderr=True)
+    result = command.run_one('git', '--git-dir', git_dir, 'worktree', 'prune',
+                             capture=True, capture_stderr=True)
     if result.return_code != 0:
-        raise OSError('git worktree prune: %s' % result.stderr)
+        raise OSError(f'git worktree prune: {result.stderr}')
 
 
 def create_patches(branch, start, count, ignore_binary, series, signoff=True):
@@ -326,11 +329,12 @@ def create_patches(branch, start, count, ignore_binary, series, signoff=True):
     git format-patch.
 
     Args:
-        branch: Branch to create patches from (None for current branch)
-        start: Commit to start from: 0=HEAD, 1=next one, etc.
-        count: number of commits to include
-        ignore_binary: Don't generate patches for binary files
-        series: Series object for this series (set of patches)
+        branch (str): Branch to create patches from (None for current branch)
+        start (int): Commit to start from: 0=HEAD, 1=next one, etc.
+        count (int): number of commits to include
+        ignore_binary (bool): Don't generate patches for binary files
+        series (Series): Series object for this series (set of patches)
+        signoff (bool): True to add signoff lines automatically
     Return:
         Filename of cover letter (None if none)
         List of filenames of patch files
@@ -344,9 +348,9 @@ def create_patches(branch, start, count, ignore_binary, series, signoff=True):
         cmd.append('--cover-letter')
     prefix = series.GetPatchPrefix()
     if prefix:
-        cmd += ['--subject-prefix=%s' % prefix]
+        cmd += [f'--subject-prefix={prefix}']
     brname = branch or 'HEAD'
-    cmd += ['%s~%d..%s~%d' % (brname, start + count, brname, start)]
+    cmd += [f'{brname}~{start + count}..{brname}~{start}']
 
     stdout = command.run_list(cmd)
     files = stdout.splitlines()
@@ -354,8 +358,7 @@ def create_patches(branch, start, count, ignore_binary, series, signoff=True):
     # We have an extra file if there is a cover letter
     if series.get('cover'):
         return files[0], files[1:]
-    else:
-        return None, files
+    return None, files
 
 
 def build_email_list(in_list, tag=None, alias=None, warn_on_error=True):
@@ -369,11 +372,13 @@ def build_email_list(in_list, tag=None, alias=None, warn_on_error=True):
     command line parameter) then the email address is quoted.
 
     Args:
-        in_list:        List of aliases/email addresses
-        tag:            Text to put before each address
-        alias:          Alias dictionary
-        warn_on_error: True to raise an error when an alias fails to match,
-                False to just print a message.
+        in_list (list of str): List of aliases/email addresses
+        tag (str): Text to put before each address
+        alias (dict): Alias dictionary:
+            key: alias
+            value: list of aliases or email addresses
+        warn_on_error (bool): True to raise an error when an alias fails to
+            match, False to just print a message.
 
     Returns:
         List of email addresses
@@ -401,7 +406,7 @@ def build_email_list(in_list, tag=None, alias=None, warn_on_error=True):
         if item not in result:
             result.append(item)
     if tag:
-        return ['%s %s%s%s' % (tag, quote, email, quote) for email in result]
+        return [f'{tag} {quote}{email}{quote}' for email in result]
     return result
 
 
@@ -409,24 +414,23 @@ def check_suppress_cc_config():
     """Check if sendemail.suppresscc is configured correctly.
 
     Returns:
-        True if the option is configured correctly, False otherwise.
+        bool: True if the option is configured correctly, False otherwise.
     """
     suppresscc = command.output_one_line(
         'git', 'config', 'sendemail.suppresscc', raise_on_error=False)
 
     # Other settings should be fine.
-    if suppresscc == 'all' or suppresscc == 'cccmd':
+    if suppresscc in ('all', 'cccmd'):
         col = terminal.Color()
 
-        print((col.build(col.RED, "error") +
-               ": git config sendemail.suppresscc set to %s\n"
-               % (suppresscc)) +
-              "  patman needs --cc-cmd to be run to set the cc list.\n" +
-              "  Please run:\n" +
-              "    git config --unset sendemail.suppresscc\n" +
-              "  Or read the man page:\n" +
-              "    git send-email --help\n" +
-              "  and set an option that runs --cc-cmd\n")
+        print(col.build(col.RED, 'error') +
+              f': git config sendemail.suppresscc set to {suppresscc}\n' +
+              '  patman needs --cc-cmd to be run to set the cc list.\n' +
+              '  Please run:\n' +
+              '    git config --unset sendemail.suppresscc\n' +
+              '  Or read the man page:\n' +
+              '    git send-email --help\n' +
+              '  and set an option that runs --cc-cmd\n')
         return False
 
     return True
@@ -434,24 +438,26 @@ def check_suppress_cc_config():
 
 def email_patches(series, cover_fname, args, dry_run, warn_on_error, cc_fname,
                   self_only=False, alias=None, in_reply_to=None, thread=False,
-                  smtp_server=None, get_maintainer_script=None):
+                  smtp_server=None):
     """Email a patch series.
 
     Args:
-        series: Series object containing destination info
-        cover_fname: filename of cover letter
-        args: list of filenames of patch files
-        dry_run: Just return the command that would be run
-        warn_on_error: True to print a warning when an alias fails to match,
-                False to ignore it.
-        cc_fname: Filename of Cc file for per-commit Cc
-        self_only: True to just email to yourself as a test
-        in_reply_to: If set we'll pass this to git as --in-reply-to.
-            Should be a message ID that this is in reply to.
-        thread: True to add --thread to git send-email (make
+        series (Series): Series object containing destination info
+        cover_fname (str or None): filename of cover letter
+        args (list of str): list of filenames of patch files
+        dry_run (bool): Just return the command that would be run
+        warn_on_error (bool): True to print a warning when an alias fails to
+            match, False to ignore it.
+        cc_fname (str): Filename of Cc file for per-commit Cc
+        self_only (bool): True to just email to yourself as a test
+        alias (dict or None): Alias dictionary: (None to use settings default)
+            key: alias
+            value: list of aliases or email addresses
+        in_reply_to (str or None): If set we'll pass this to git as
+            --in-reply-to - should be a message ID that this is in reply to.
+        thread (bool): True to add --thread to git send-email (make
             all patches reply to cover-letter or first patch in series)
-        smtp_server: SMTP server to use to send patches
-        get_maintainer_script: File name of script to get maintainers emails
+        smtp_server (str or None): SMTP server to use to send patches
 
     Returns:
         Git command that was/would be run
@@ -502,7 +508,7 @@ send --cc-cmd cc-fname" cover p1 p2'
                   "Series-to: Fred Bloggs <f.blogs@napier.co.nz>\n"
                   "Or do something like this\n"
                   "git config sendemail.to u-boot@lists.denx.de")
-            return
+            return None
     cc = build_email_list(list(set(series.get('cc')) - set(series.get('to'))),
                           '--cc', alias, warn_on_error)
     if self_only:
@@ -511,15 +517,15 @@ send --cc-cmd cc-fname" cover p1 p2'
         cc = []
     cmd = ['git', 'send-email', '--annotate']
     if smtp_server:
-        cmd.append('--smtp-server=%s' % smtp_server)
+        cmd.append(f'--smtp-server={smtp_server}')
     if in_reply_to:
-        cmd.append('--in-reply-to="%s"' % in_reply_to)
+        cmd.append(f'--in-reply-to="{in_reply_to}"')
     if thread:
         cmd.append('--thread')
 
     cmd += to
     cmd += cc
-    cmd += ['--cc-cmd', '"%s send --cc-cmd %s"' % (sys.argv[0], cc_fname)]
+    cmd += ['--cc-cmd', f'"{sys.argv[0]} send --cc-cmd {cc_fname}"']
     if cover_fname:
         cmd.append(cover_fname)
     cmd += args
@@ -535,10 +541,13 @@ def lookup_email(lookup_name, alias=None, warn_on_error=True, level=0):
     TODO: Why not just use git's own alias feature?
 
     Args:
-        lookup_name: Alias or email address to look up
-        alias: Dictionary containing aliases (None to use settings default)
-        warn_on_error: True to print a warning when an alias fails to match,
-                False to ignore it.
+        lookup_name (str): Alias or email address to look up
+        alias (dict or None): Alias dictionary: (None to use settings default)
+            key: alias
+            value: list of aliases or email addresses
+        warn_on_error (bool): True to print a warning when an alias fails to
+            match, False to ignore it.
+        level (int): Depth of alias stack, used to detect recusion/loops
 
     Returns:
         tuple:
@@ -591,16 +600,15 @@ def lookup_email(lookup_name, alias=None, warn_on_error=True, level=0):
 
     out_list = []
     if level > 10:
-        msg = "Recursive email alias at '%s'" % lookup_name
+        msg = f"Recursive email alias at '{lookup_name}'"
         if warn_on_error:
             raise OSError(msg)
-        else:
-            print(col.build(col.RED, msg))
-            return out_list
+        print(col.build(col.RED, msg))
+        return out_list
 
     if lookup_name:
         if lookup_name not in alias:
-            msg = "Alias '%s' not found" % lookup_name
+            msg = f"Alias '{lookup_name}' not found"
             if warn_on_error:
                 print(col.build(col.RED, msg))
             return out_list
@@ -617,7 +625,7 @@ def get_top_level():
     """Return name of top-level directory for this git repo.
 
     Returns:
-        Full path to git top-level directory
+        str: Full path to git top-level directory
 
     This test makes sure that we are running tests in the right subdir
 
@@ -632,7 +640,7 @@ def get_alias_file():
     """Gets the name of the git alias file.
 
     Returns:
-        Filename of git alias file, or None if none
+        str: Filename of git alias file, or None if none
     """
     fname = command.output_one_line('git', 'config', 'sendemail.aliasesfile',
                                     raise_on_error=False)
@@ -652,7 +660,8 @@ def get_default_user_name():
     Returns:
         User name found in .gitconfig file, or None if none
     """
-    uname = command.output_one_line('git', 'config', '--global', '--includes', 'user.name')
+    uname = command.output_one_line('git', 'config', '--global', '--includes',
+                                    'user.name')
     return uname
 
 
@@ -662,7 +671,8 @@ def get_default_user_email():
     Returns:
         User's email found in .gitconfig file, or None if none
     """
-    uemail = command.output_one_line('git', 'config', '--global', '--includes', 'user.email')
+    uemail = command.output_one_line('git', 'config', '--global', '--includes',
+                                     'user.email')
     return uemail
 
 
@@ -679,15 +689,15 @@ def get_default_subject_prefix():
 
 
 def setup():
-    """Set up git utils, by reading the alias files."""
+    """setup() - Set up git utils, by reading the alias files."""
     # Check for a git alias file also
-    global use_no_decorate
+    global USE_NO_DECORATE
 
     alias_fname = get_alias_file()
     if alias_fname:
         settings.ReadGitAliases(alias_fname)
     cmd = log_cmd(None, count=0)
-    use_no_decorate = (command.run_pipe([cmd], raise_on_error=False)
+    USE_NO_DECORATE = (command.run_one(*cmd, raise_on_error=False)
                        .return_code == 0)
 
 
diff --git a/tools/u_boot_pylib/requirements.txt b/tools/u_boot_pylib/requirements.txt
new file mode 100644
index 00000000000..1087e6f2857
--- /dev/null
+++ b/tools/u_boot_pylib/requirements.txt
@@ -0,0 +1 @@
+concurrencytest==0.1.2
diff --git a/tools/u_boot_pylib/tools.py b/tools/u_boot_pylib/tools.py
index 0499a75526f..1afd289eadd 100644
--- a/tools/u_boot_pylib/tools.py
+++ b/tools/u_boot_pylib/tools.py
@@ -376,7 +376,7 @@ def run_result(name, *args, **kwargs):
             args = tuple(extra_args) + args
         name = os.path.expanduser(name)  # Expand paths containing ~
         all_args = (name,) + args
-        result = command.run_pipe([all_args], capture=True, capture_stderr=True,
+        result = command.run_one(*all_args, capture=True, capture_stderr=True,
                                  env=env, raise_on_error=False, binary=binary)
         if result.return_code:
             if raise_on_error:
diff --git a/tools/ublimage.c b/tools/ublimage.c
index 8f9b58c7983..a1bd807bfa0 100644
--- a/tools/ublimage.c
+++ b/tools/ublimage.c
@@ -178,6 +178,7 @@ static uint32_t parse_cfg_file(struct ubl_header *ublhdr, char *name)
 					lineno, fld, &dcd_len);
 		}
 	}
+	free(line);
 	fclose(fd);
 
 	return dcd_len;