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| author | Svyatoslav Ryhel <clamor95@gmail.com> | 2025-03-24 21:24:45 +0200 |
|---|---|---|
| committer | Svyatoslav Ryhel <clamor95@gmail.com> | 2025-04-12 09:42:35 +0300 |
| commit | 0edc47ba7332c72ae1d18003a18c717143cab78b (patch) | |
| tree | 5116e34ba4e04b77be20af42e566805569fdb6ca /tools/u_boot_pylib/test_util.py | |
| parent | 6bbe348bfccea3b967aa398a6d46bcb8439d093f (diff) | |
ARM: tegra: clock: take in account PLLD/D2 enable bit on clock_set_rate
PLLD and PLLD2 clocks possess a unique enable bit within their
miscellaneous register. Take this into account when using clock_set_rate
function.
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Diffstat (limited to 'tools/u_boot_pylib/test_util.py')
0 files changed, 0 insertions, 0 deletions