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| author | Svyatoslav Ryhel <clamor95@gmail.com> | 2025-03-25 09:51:47 +0200 |
|---|---|---|
| committer | Svyatoslav Ryhel <clamor95@gmail.com> | 2025-04-12 09:42:35 +0300 |
| commit | 212757af3a3b53ee4ab5aa48ce9a1192aab4d2df (patch) | |
| tree | b1bb75c58b3e65292ff6fac339961bd4feb558c6 /tools/u_boot_pylib/test_util.py | |
| parent | 0edc47ba7332c72ae1d18003a18c717143cab78b (diff) | |
ARM: tegra: clock: fix PLLD2 info table entry on Tegra124 and Tegra210
Historically, PLLD2 mirrored PLLD's layout on Tegra30 and 114. However,
with the introduction of Tegra124, this changed. This layout alteration was
not considered, and it now requires a corrective action to prevent future
complications.
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Diffstat (limited to 'tools/u_boot_pylib/test_util.py')
0 files changed, 0 insertions, 0 deletions