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| author | Tom Rini <trini@konsulko.com> | 2025-03-31 11:06:14 -0600 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2025-03-31 17:04:20 -0600 |
| commit | 4a06b4b8efc39b6c8bf08225b18875f3c267bc2f (patch) | |
| tree | ac77a681297895fe2325086a5610390361797e45 /tools/u_boot_pylib/test_util.py | |
| parent | fd2bccec19d399b4a445009b3d514d2419cfbc95 (diff) | |
| parent | dbe3ea4274b005e05cf1ddaf1d6406e0e452720f (diff) | |
Merge patch series "Add WDT support for J7200 SOC"
Udit Kumar <u-kumar1@ti.com> says:
This enables the ESMs and the associated PMIC.
Programming these bits is a requirement to make the watchdog actually reset the board.
After DT sync nodes bucka1 and main_esm has bootph property added in
pmic nodes.
RFC was sent
https://lore.kernel.org/all/20241126063543.2678052-1-u-kumar1@ti.com/
With current patch boot logs
https://gist.github.com/uditkumarti/adb647f86e6d166ea2d0ac98dceb7a9b
reset: https://gist.github.com/uditkumarti/adb647f86e6d166ea2d0ac98dceb7a9b#file-gistfile1-txt-L2344
Link: https://lore.kernel.org/r/20250314110411.2781732-1-u-kumar1@ti.com
Diffstat (limited to 'tools/u_boot_pylib/test_util.py')
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