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author | Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com> | 2025-04-03 19:07:03 -0700 |
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committer | Tien Fong Chee <tien.fong.chee@intel.com> | 2025-04-22 11:47:39 +0800 |
commit | cf5b58ef6ed577f07ad76ec5024060c84acef481 (patch) | |
tree | 7609400e48ef5c37f2f61de7f99ea4980cd1c45a /tools/u_boot_pylib/test_util.py | |
parent | 9acad2b4c7214bb423a6221b67b0d7ea37edbdf7 (diff) |
arm: socfpga: soc64: Enable F2S bridge reset support
Enable reset support for FPGA2SDRAM bridge for Stratix10, as well as
FPGA2SoC and SoC2FPGA bridges for all SoC64 families.
Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
Diffstat (limited to 'tools/u_boot_pylib/test_util.py')
0 files changed, 0 insertions, 0 deletions