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-rw-r--r--MAINTAINERS1
-rw-r--r--arch/arm/dts/Makefile2
-rw-r--r--arch/arm/dts/imx6dl-sielaff.dts533
-rw-r--r--arch/arm/dts/imx93-11x11-frdm-u-boot.dtsi186
-rw-r--r--arch/arm/dts/imx93-11x11-frdm.dts603
-rw-r--r--arch/arm/include/asm/arch-imx9/ddr.h1
-rw-r--r--arch/arm/mach-imx/imx9/Kconfig9
-rw-r--r--arch/arm/mach-k3/j784s4/j784s4_init.c52
-rw-r--r--board/freescale/imx93_evk/MAINTAINERS2
-rw-r--r--board/freescale/imx93_evk/imx93_evk.c3
-rw-r--r--board/freescale/imx93_frdm/Kconfig12
-rw-r--r--board/freescale/imx93_frdm/MAINTAINERS6
-rw-r--r--board/freescale/imx93_frdm/Makefile11
-rw-r--r--board/freescale/imx93_frdm/imx93_frdm.c59
-rw-r--r--board/freescale/imx93_frdm/imx93_frdm.env31
-rw-r--r--board/freescale/imx93_frdm/lpddr4_timing.h12
-rw-r--r--board/freescale/imx93_frdm/lpddr4x_1gb_timing.c1996
-rw-r--r--board/freescale/imx93_frdm/lpddr4x_2gb_timing.c1995
-rw-r--r--board/freescale/imx93_frdm/spl.c195
-rw-r--r--board/phytec/phycore_imx8mm/phycore_imx8mm.env72
-rw-r--r--board/phytec/phycore_imx93/phycore-imx93.c3
-rw-r--r--board/phytec/phycore_imx93/spl.c7
-rw-r--r--board/samsung/e850-96/e850-96.c77
-rw-r--r--board/samsung/e850-96/e850-96.env44
-rw-r--r--board/toradex/common/tdx-cfg-block.c1
-rw-r--r--board/toradex/common/tdx-cfg-block.h1
-rw-r--r--board/toradex/verdin-imx8mm/verdin-imx8mm.c3
-rw-r--r--common/spl/spl_imx_container.c4
-rw-r--r--configs/e850-96_defconfig25
-rw-r--r--configs/imx6dl_sielaff_defconfig4
-rw-r--r--configs/imx8mm-phygate-tauri-l_defconfig15
-rw-r--r--configs/imx93_frdm_defconfig124
-rw-r--r--configs/phycore-imx8mm_defconfig14
-rw-r--r--doc/board/nxp/imx93_frdm.rst75
-rw-r--r--doc/board/nxp/index.rst1
-rw-r--r--doc/board/samsung/e850-96.rst85
-rw-r--r--drivers/adc/imx93-adc.c4
-rw-r--r--drivers/misc/Kconfig8
-rw-r--r--drivers/misc/Makefile1
-rw-r--r--drivers/misc/k3_bist.c807
-rw-r--r--drivers/misc/k3_bist_static_data.h673
-rw-r--r--drivers/misc/k3_j784s4_bist_static_data.h370
-rw-r--r--drivers/phy/Kconfig9
-rw-r--r--drivers/phy/Makefile1
-rw-r--r--drivers/phy/phy-exynos-usbdrd.c386
-rw-r--r--drivers/power/domain/imx8m-power-domain.c2
-rw-r--r--drivers/usb/dwc3/dwc3-generic.c1
-rw-r--r--include/configs/e850-96.h21
-rw-r--r--include/configs/imx93_evk.h2
-rw-r--r--include/configs/imx93_frdm.h30
-rw-r--r--include/k3_bist.h44
51 files changed, 7971 insertions, 652 deletions
diff --git a/MAINTAINERS b/MAINTAINERS
index f914fc54f54..d490b43c57f 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -602,6 +602,7 @@ ARM SAMSUNG EXYNOS850 SOC
M: Sam Protsenko <semen.protsenko@linaro.org>
S: Maintained
F: drivers/clk/exynos/clk-exynos850.c
+F: drivers/phy/phy-exynos-usbdrd.c
F: drivers/pinctrl/exynos/pinctrl-exynos850.c
ARM SAMSUNG SOC DRIVERS
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 17795f8f746..0dc7e190eb9 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -760,7 +760,6 @@ dtb-y += \
imx6dl-riotboard.dtb \
imx6dl-sabreauto.dtb \
imx6dl-sabresd.dtb \
- imx6dl-sielaff.dtb \
imx6dl-wandboard-revd1.dtb
endif
@@ -918,6 +917,7 @@ dtb-$(CONFIG_ARCH_IMX8M) += \
imx8mq-librem5-r4.dtb
dtb-$(CONFIG_ARCH_IMX9) += \
+ imx93-11x11-frdm.dtb \
imx93-var-som-symphony.dtb
dtb-$(CONFIG_ARCH_IMXRT) += imxrt1020-evk.dtb \
diff --git a/arch/arm/dts/imx6dl-sielaff.dts b/arch/arm/dts/imx6dl-sielaff.dts
deleted file mode 100644
index 7de8d5f2651..00000000000
--- a/arch/arm/dts/imx6dl-sielaff.dts
+++ /dev/null
@@ -1,533 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+ OR MIT
-/*
- * Copyright (C) 2022 Kontron Electronics GmbH
- */
-
-/dts-v1/;
-
-#include "imx6dl.dtsi"
-#include <dt-bindings/clock/imx6qdl-clock.h>
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-
-/ {
- model = "Sielaff i.MX6 Solo";
- compatible = "sielaff,imx6dl-board", "fsl,imx6dl";
-
- chosen {
- stdout-path = &uart2;
- };
-
- backlight: pwm-backlight {
- compatible = "pwm-backlight";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_backlight>;
- pwms = <&pwm3 0 50000 0>;
- brightness-levels = <0 0 64 88 112 136 184 232 255>;
- default-brightness-level = <4>;
- enable-gpios = <&gpio6 16 GPIO_ACTIVE_HIGH>;
- power-supply = <&reg_backlight>;
- };
-
- cec {
- compatible = "cec-gpio";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_hdmi_cec>;
- cec-gpios = <&gpio2 7 GPIO_ACTIVE_HIGH>;
- hdmi-phandle = <&hdmi>;
- };
-
- enet_ref: clock-enet-ref {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <50000000>;
- clock-output-names = "enet-ref";
- };
-
- gpio-keys {
- compatible = "gpio-keys";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_gpio_keys>;
-
- key-0 {
- gpios = <&gpio2 16 0>;
- debounce-interval = <10>;
- linux,code = <1>;
- };
-
- key-1 {
- gpios = <&gpio3 27 0>;
- debounce-interval = <10>;
- linux,code = <2>;
- };
-
- key-2 {
- gpios = <&gpio5 4 0>;
- debounce-interval = <10>;
- linux,code = <3>;
- };
- };
-
- leds {
- compatible = "gpio-leds";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_gpio_leds>;
-
- led-debug {
- label = "debug-led";
- gpios = <&gpio5 21 GPIO_ACTIVE_HIGH>;
- default-state = "off";
- linux,default-trigger = "heartbeat";
- };
- };
-
- memory@80000000 {
- reg = <0x80000000 0x20000000>;
- device_type = "memory";
- };
-
- osc_eth_phy: clock-osc-eth-phy {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <25000000>;
- clock-output-names = "osc-eth-phy";
- };
-
- panel {
- compatible = "lg,lb070wv8";
- backlight = <&backlight>;
- power-supply = <&reg_3v3>;
-
- port {
- panel_in_lvds: endpoint {
- remote-endpoint = <&lvds_out>;
- };
- };
- };
-
- reg_3v3: regulator-3v3 {
- compatible = "regulator-fixed";
- regulator-name = "3v3";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- };
-
- reg_backlight: regulator-backlight {
- compatible = "regulator-fixed";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_reg_backlight>;
- enable-active-high;
- gpio = <&gpio1 23 GPIO_ACTIVE_HIGH>;
- regulator-name = "backlight";
- regulator-min-microvolt = <12000000>;
- regulator-max-microvolt = <12000000>;
- };
-
- reg_usb_otg_vbus: regulator-usb-otg-vbus {
- compatible = "regulator-fixed";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_reg_usbotg_vbus>;
- enable-active-high;
- gpio = <&gpio4 15 GPIO_ACTIVE_HIGH>;
- regulator-name = "usb_otg_vbus";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- };
-};
-
-&ecspi2 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_ecspi2>;
- cs-gpios = <&gpio5 29 GPIO_ACTIVE_LOW>;
- status = "okay";
-
- flash@0 {
- compatible = "jedec,spi-nor";
- reg = <0>;
- spi-max-frequency = <20000000>;
- };
-};
-
-&fec {
- /*
- * Set PTP clock to external instead of internal reference, as the
- * REF_CLK from the PHY is fed back into the i.MX6 and the GPR
- * register needs to be set accordingly (see mach-imx6q.c).
- */
- clocks = <&clks IMX6QDL_CLK_ENET>,
- <&clks IMX6QDL_CLK_ENET>,
- <&enet_ref>,
- <&clks IMX6QDL_CLK_ENET_REF>;
- clock-names = "ipg", "ahb", "ptp", "enet_out";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_enet>;
- phy-connection-type = "rmii";
- phy-handle = <&ethphy>;
- status = "okay";
-
- mdio {
- #address-cells = <1>;
- #size-cells = <0>;
-
- ethphy: ethernet-phy@1 {
- reg = <1>;
- clocks = <&osc_eth_phy>;
- clock-names = "rmii-ref";
- micrel,led-mode = <1>;
- reset-assert-us = <500>;
- reset-deassert-us = <100>;
- reset-gpios = <&gpio5 2 GPIO_ACTIVE_LOW>;
- };
- };
-};
-
-&gpio1 {
- gpio-line-names =
- "", "", "", "", "", "", "", "",
- "", "", "", "", "", "", "key-out", "key-in",
- "", "", "", "", "", "", "", "",
- "", "", "", "", "", "", "", "";
-};
-
-&gpio2 {
- gpio-line-names =
- "", "", "", "", "", "", "", "",
- "lan9500a-rst", "", "", "", "", "", "", "",
- "", "", "", "", "", "", "", "",
- "", "", "", "", "", "", "", "";
-};
-
-&gpmi {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_gpmi_nand>;
- status = "okay";
-};
-
-&hdmi {
- ddc-i2c-bus = <&i2c4>;
- status = "okay";
-};
-
-&i2c2 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c2>;
- clock-frequency = <100000>;
- status = "okay";
-
- rtc@51 {
- compatible = "nxp,pcf8563";
- reg = <0x51>;
- };
-};
-
-&i2c3 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c3>;
- clock-frequency = <100000>;
- status = "okay";
-
- touchscreen@55 {
- compatible = "sitronix,st1633";
- reg = <0x55>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_touch>;
- interrupts = <18 IRQ_TYPE_EDGE_FALLING>;
- interrupt-parent = <&gpio5>;
- gpios = <&gpio1 2 GPIO_ACTIVE_LOW>;
- status = "disabled";
- };
-
- touchscreen@5d {
- compatible = "goodix,gt928";
- reg = <0x5d>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_touch>;
- interrupts = <18 IRQ_TYPE_LEVEL_LOW>;
- interrupt-parent = <&gpio5>;
- irq-gpios = <&gpio5 18 GPIO_ACTIVE_HIGH>;
- reset-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
- status = "disabled";
- };
-};
-
-&i2c4 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c4>;
- clock-frequency = <100000>;
- status = "okay";
-};
-
-&ldb {
- status = "okay";
-
- lvds: lvds-channel@0 {
- fsl,data-mapping = "spwg";
- fsl,data-width = <24>;
- status = "okay";
-
- port@4 {
- reg = <4>;
-
- lvds_out: endpoint {
- remote-endpoint = <&panel_in_lvds>;
- };
- };
- };
-};
-
-&pwm3 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_pwm3>;
- status = "okay";
-};
-
-&uart1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart1>;
- status = "okay";
-};
-
-&uart2 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart2>;
- status = "okay";
-};
-
-&uart3 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart3>;
- status = "okay";
-};
-
-&usbh1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usbh1>;
- disable-over-current;
- status = "okay";
-
- #address-cells = <1>;
- #size-cells = <0>;
-
- usb1@1 {
- compatible = "usb4b4,6570";
- reg = <1>;
- clocks = <&clks IMX6QDL_CLK_CKO>;
-
- assigned-clocks = <&clks IMX6QDL_CLK_CKO>,
- <&clks IMX6QDL_CLK_CKO2_SEL>;
- assigned-clock-parents = <&clks IMX6QDL_CLK_CKO2>,
- <&clks IMX6QDL_CLK_OSC>;
- assigned-clock-rates = <12000000 0>;
- };
-};
-
-&usbotg {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usbotg>;
- dr_mode = "host";
- over-current-active-low;
- vbus-supply = <&reg_usb_otg_vbus>;
- status = "okay";
-};
-
-&usdhc3 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usdhc3>;
- cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
- vmmc-supply = <&reg_3v3>;
- voltage-ranges = <3300 3300>;
- no-1-8-v;
- status = "okay";
-};
-
-&wdog1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_wdog>;
- fsl,ext-reset-output;
- status = "okay";
-};
-
-&iomuxc {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_hog>;
-
- pinctrl_hog: hoggrp {
- fsl,pins = <
- MX6QDL_PAD_RGMII_RD0__GPIO6_IO25 0x1b0b0 /* PMIC_IRQ */
- MX6QDL_PAD_SD2_DAT3__GPIO1_IO12 0x1b0b0
- MX6QDL_PAD_SD2_DAT1__GPIO1_IO14 0x1b0b0
- MX6QDL_PAD_SD2_DAT0__GPIO1_IO15 0x1b0b0
- MX6QDL_PAD_SD4_DAT0__GPIO2_IO08 0x1b0b0
- MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x1b0b0
- >;
- };
-
- pinctrl_backlight: backlightgrp {
- fsl,pins = <
- MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x100b1
- >;
- };
-
- pinctrl_ecspi2: ecspi2grp {
- fsl,pins = <
- MX6QDL_PAD_CSI0_DAT10__ECSPI2_MISO 0x100b1
- MX6QDL_PAD_CSI0_DAT9__ECSPI2_MOSI 0x100b1
- MX6QDL_PAD_CSI0_DAT8__ECSPI2_SCLK 0x100b1
- MX6QDL_PAD_CSI0_DAT11__GPIO5_IO29 0x100b1
- >;
- };
-
- pinctrl_enet: enetgrp {
- fsl,pins = <
- MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
- MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
- MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0
- MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0
- MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0
- MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1b0b0
- MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1b0b0
- MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1b0b0
- MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0
- MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
- MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x100b1
- >;
- };
-
- pinctrl_gpio_keys: gpiokeysgrp {
- fsl,pins = <
- MX6QDL_PAD_EIM_A22__GPIO2_IO16 0x1b080
- MX6QDL_PAD_EIM_D27__GPIO3_IO27 0x1b080
- MX6QDL_PAD_EIM_A24__GPIO5_IO04 0x1b080
- >;
- };
-
- pinctrl_gpio_leds: gpioledsgrp {
- fsl,pins = <
- MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x1b0b0
- >;
- };
-
- pinctrl_gpmi_nand: gpminandgrp {
- fsl,pins = <
- MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
- MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
- MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
- MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
- MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
- MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
- MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
- MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
- MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
- MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
- MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
- MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
- MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
- MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
- MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
- >;
- };
-
- pinctrl_hdmi_cec: hdmicecgrp {
- fsl,pins = <
- MX6QDL_PAD_EIM_A21__GPIO2_IO17 0x1b8b1
- >;
- };
-
- pinctrl_i2c2: i2c2grp {
- fsl,pins = <
- MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
- MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
- >;
- };
-
- pinctrl_i2c3: i2c3grp {
- fsl,pins = <
- MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001f8b1
- MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001f8b1
- >;
- };
-
- pinctrl_i2c4: i2c4grp {
- fsl,pins = <
- MX6QDL_PAD_GPIO_7__I2C4_SCL 0x4001b8b1
- MX6QDL_PAD_GPIO_8__I2C4_SDA 0x4001b8b1
- >;
- };
-
- pinctrl_pwm3: pwm3grp {
- fsl,pins = <
- MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1
- >;
- };
-
- pinctrl_reg_backlight: regbacklightgrp {
- fsl,pins = <
- MX6QDL_PAD_ENET_REF_CLK__GPIO1_IO23 0x1b0b1
- >;
- };
-
- pinctrl_reg_usbotg_vbus: regusbotgvbusgrp {
- fsl,pins = <
- MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b1
- >;
- };
-
- pinctrl_touch: touchgrp {
- fsl,pins = <
- MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0
- MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x1b0b0
- >;
- };
-
- pinctrl_uart1: uart1grp {
- fsl,pins = <
- MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
- MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1
- >;
- };
-
- pinctrl_uart2: uart2grp {
- fsl,pins = <
- MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
- MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
- >;
- };
-
- pinctrl_uart3: uart3grp {
- fsl,pins = <
- MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b0
- MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b0
- >;
- };
-
- pinctrl_usbh1: usbh1grp {
- fsl,pins = <
- MX6QDL_PAD_GPIO_3__USB_H1_OC 0x1b0b1
- MX6QDL_PAD_CSI0_MCLK__CCM_CLKO1 0x1b0b0
- >;
- };
-
- pinctrl_usbotg: usbotggrp {
- fsl,pins = <
- MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x1b0b1
- >;
- };
-
- pinctrl_usdhc3: usdhc3grp {
- fsl,pins = <
- MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
- MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
- MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
- MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
- MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
- MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
- MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x100b1
- >;
- };
-
- pinctrl_wdog: wdoggrp {
- fsl,pins = <
- MX6QDL_PAD_GPIO_9__WDOG1_B 0x1b0b0
- >;
- };
-};
diff --git a/arch/arm/dts/imx93-11x11-frdm-u-boot.dtsi b/arch/arm/dts/imx93-11x11-frdm-u-boot.dtsi
new file mode 100644
index 00000000000..41111b1a95a
--- /dev/null
+++ b/arch/arm/dts/imx93-11x11-frdm-u-boot.dtsi
@@ -0,0 +1,186 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2025 NXP
+ */
+
+#include "imx93-u-boot.dtsi"
+
+/ {
+ wdt-reboot {
+ compatible = "wdt-reboot";
+ wdt = <&wdog3>;
+ bootph-pre-ram;
+ bootph-some-ram;
+ };
+};
+
+&A55_0 {
+ clocks = <&clk IMX93_CLK_A55_SEL>;
+};
+
+&A55_1 {
+ clocks = <&clk IMX93_CLK_A55_SEL>;
+};
+
+&{/soc@0} {
+ bootph-all;
+ bootph-pre-ram;
+};
+
+&aips1 {
+ bootph-pre-ram;
+ bootph-all;
+};
+
+&aips2 {
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
+&aips3 {
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
+&iomuxc {
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
+&reg_usdhc2_vmmc {
+ u-boot,off-on-delay-us = <20000>;
+ bootph-pre-ram;
+};
+
+&pinctrl_reg_usdhc2_vmmc {
+ bootph-pre-ram;
+};
+
+&pinctrl_uart1 {
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
+&pinctrl_usdhc1 {
+ bootph-pre-ram;
+};
+
+&pinctrl_usdhc2_gpio {
+ bootph-pre-ram;
+};
+
+&pinctrl_usdhc2 {
+ bootph-pre-ram;
+};
+
+&gpio1 {
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
+&gpio2 {
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
+&gpio3 {
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
+&gpio4 {
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
+&lpuart1 {
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
+&usdhc1 {
+ bootph-pre-ram;
+};
+
+&usdhc2 {
+ bootph-pre-ram;
+ fsl,signal-voltage-switch-extra-delay-ms = <8>;
+};
+
+&lpi2c1 {
+ bootph-pre-ram;
+};
+
+&lpi2c2 {
+ bootph-pre-ram;
+};
+
+&lpi2c3 {
+ bootph-pre-ram;
+};
+
+&{/soc@0/bus@44000000/i2c@44350000/pmic@25} {
+ bootph-pre-ram;
+};
+
+&{/soc@0/bus@44000000/i2c@44350000/pmic@25/regulators} {
+ bootph-pre-ram;
+};
+
+&pinctrl_lpi2c2 {
+ bootph-pre-ram;
+};
+
+&pinctrl_lpi2c3 {
+ bootph-pre-ram;
+};
+
+&fec {
+ phy-reset-gpios = <&pcal6524 16 GPIO_ACTIVE_LOW>;
+ phy-reset-duration = <15>;
+ phy-reset-post-delay = <100>;
+};
+
+&ethphy1 {
+ reset-gpios = <&pcal6524 15 GPIO_ACTIVE_LOW>;
+ reset-assert-us = <15000>;
+ reset-deassert-us = <100000>;
+};
+
+&usbotg1 {
+ status = "okay";
+ extcon = <&ptn5110>;
+};
+
+&usbotg2 {
+ status = "okay";
+};
+
+&s4muap {
+ bootph-pre-ram;
+ bootph-some-ram;
+ status = "okay";
+};
+
+&clk {
+ bootph-all;
+ bootph-pre-ram;
+ /delete-property/ assigned-clocks;
+ /delete-property/ assigned-clock-rates;
+ /delete-property/ assigned-clock-parents;
+};
+
+&osc_32k {
+ bootph-all;
+ bootph-pre-ram;
+};
+
+&osc_24m {
+ bootph-all;
+ bootph-pre-ram;
+};
+
+&clk_ext1 {
+ bootph-all;
+ bootph-pre-ram;
+};
diff --git a/arch/arm/dts/imx93-11x11-frdm.dts b/arch/arm/dts/imx93-11x11-frdm.dts
new file mode 100644
index 00000000000..993567e767d
--- /dev/null
+++ b/arch/arm/dts/imx93-11x11-frdm.dts
@@ -0,0 +1,603 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/dts-v1/;
+
+#include <dt-bindings/usb/pd.h>
+#include "imx93.dtsi"
+
+/ {
+ compatible = "fsl,imx93-11x11-frdm", "fsl,imx93";
+ model = "NXP i.MX93 11X11 FRDM board";
+
+ aliases {
+ mmc0 = &usdhc1; /* EMMC */
+ mmc1 = &usdhc2; /* uSD */
+ rtc0 = &pcf2131;
+ serial0 = &lpuart1;
+ };
+
+ chosen {
+ stdout-path = &lpuart1;
+ };
+
+ reg_vref_1v8: regulator-adc-vref {
+ compatible = "regulator-fixed";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vref_1v8";
+ };
+
+ reg_usdhc2_vmmc: regulator-usdhc2 {
+ compatible = "regulator-fixed";
+ off-on-delay-us = <12000>;
+ pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
+ pinctrl-names = "default";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "VSD_3V3";
+ gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ reg_usdhc3_vmmc: regulator-usdhc3 {
+ compatible = "regulator-fixed";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "WLAN_EN";
+ gpio = <&pcal6524 20 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ /*
+ * IW612 wifi chip needs more delay than other wifi chips to complete
+ * the host interface initialization after power up, otherwise the
+ * internal state of IW612 may be unstable, resulting in the failure of
+ * the SDIO3.0 switch voltage.
+ */
+ startup-delay-us = <20000>;
+ };
+
+ reserved-memory {
+ ranges;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ linux,cma {
+ compatible = "shared-dma-pool";
+ alloc-ranges = <0 0x80000000 0 0x30000000>;
+ reusable;
+ size = <0 0x10000000>;
+ linux,cma-default;
+ };
+
+ rsc_table: rsc-table@2021e000 {
+ reg = <0 0x2021e000 0 0x1000>;
+ no-map;
+ };
+
+ vdev0vring0: vdev0vring0@a4000000 {
+ reg = <0 0xa4000000 0 0x8000>;
+ no-map;
+ };
+
+ vdev0vring1: vdev0vring1@a4008000 {
+ reg = <0 0xa4008000 0 0x8000>;
+ no-map;
+ };
+
+ vdev1vring0: vdev1vring0@a4010000 {
+ reg = <0 0xa4010000 0 0x8000>;
+ no-map;
+ };
+
+ vdev1vring1: vdev1vring1@a4018000 {
+ reg = <0 0xa4018000 0 0x8000>;
+ no-map;
+ };
+
+ vdevbuffer: vdevbuffer@a4020000 {
+ compatible = "shared-dma-pool";
+ reg = <0 0xa4020000 0 0x100000>;
+ no-map;
+ };
+ };
+
+ usdhc3_pwrseq: usdhc3_pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ reset-gpios = <&pcal6524 12 GPIO_ACTIVE_LOW>;
+ };
+};
+
+&adc1 {
+ vref-supply = <&reg_vref_1v8>;
+ status = "okay";
+};
+
+&eqos {
+ phy-handle = <&ethphy1>;
+ phy-mode = "rgmii-id";
+ pinctrl-0 = <&pinctrl_eqos>;
+ pinctrl-1 = <&pinctrl_eqos_sleep>;
+ pinctrl-names = "default", "sleep";
+ status = "okay";
+
+ mdio {
+ compatible = "snps,dwmac-mdio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-frequency = <5000000>;
+
+ ethphy1: ethernet-phy@1 {
+ reg = <1>;
+ reset-assert-us = <10000>;
+ reset-deassert-us = <80000>;
+ reset-gpios = <&pcal6524 15 GPIO_ACTIVE_LOW>;
+ };
+ };
+};
+
+&fec {
+ phy-handle = <&ethphy2>;
+ phy-mode = "rgmii-id";
+ pinctrl-0 = <&pinctrl_fec>;
+ pinctrl-1 = <&pinctrl_fec_sleep>;
+ pinctrl-names = "default", "sleep";
+ fsl,magic-packet;
+ status = "okay";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-frequency = <5000000>;
+
+ ethphy2: ethernet-phy@2 {
+ reg = <2>;
+ eee-broken-1000t;
+ reset-assert-us = <10000>;
+ reset-deassert-us = <80000>;
+ reset-gpios = <&pcal6524 16 GPIO_ACTIVE_LOW>;
+ };
+ };
+};
+
+&lpi2c2 {
+ clock-frequency = <400000>;
+ pinctrl-0 = <&pinctrl_lpi2c2>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ pcal6524: gpio@22 {
+ compatible = "nxp,pcal6524";
+ reg = <0x22>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ interrupt-parent = <&gpio3>;
+ interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ pinctrl-0 = <&pinctrl_pcal6524>;
+ pinctrl-names = "default";
+ };
+
+ pmic@25 {
+ compatible = "nxp,pca9451a";
+ reg = <0x25>;
+ interrupt-parent = <&pcal6524>;
+ interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
+
+ regulators {
+
+ buck1: BUCK1 {
+ regulator-name = "BUCK1";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <650000>;
+ regulator-max-microvolt = <2237500>;
+ regulator-ramp-delay = <3125>;
+ };
+
+ buck2: BUCK2 {
+ regulator-name = "BUCK2";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <600000>;
+ regulator-max-microvolt = <2187500>;
+ regulator-ramp-delay = <3125>;
+ };
+
+ buck4: BUCK4 {
+ regulator-name = "BUCK4";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <600000>;
+ regulator-max-microvolt = <3400000>;
+ };
+
+ buck5: BUCK5 {
+ regulator-name = "BUCK5";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <600000>;
+ regulator-max-microvolt = <3400000>;
+ };
+
+ buck6: BUCK6 {
+ regulator-name = "BUCK6";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <600000>;
+ regulator-max-microvolt = <3400000>;
+ };
+
+ ldo1: LDO1 {
+ regulator-name = "LDO1";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1600000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ ldo4: LDO4 {
+ regulator-name = "LDO4";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ ldo5: LDO5 {
+ regulator-name = "LDO5";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ };
+ };
+ };
+
+ eeprom: eeprom@50 {
+ compatible = "atmel,24c256";
+ reg = <0x50>;
+ pagesize = <64>;
+ };
+};
+
+&lpi2c3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-frequency = <400000>;
+ pinctrl-0 = <&pinctrl_lpi2c3>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ ptn5110: tcpc@50 {
+ compatible = "nxp,ptn5110", "tcpci";
+ reg = <0x50>;
+ interrupt-parent = <&gpio3>;
+ interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
+
+ typec1_con: connector {
+ compatible = "usb-c-connector";
+ data-role = "dual";
+ label = "USB-C";
+ op-sink-microwatt = <15000000>;
+ power-role = "dual";
+ self-powered;
+ sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)
+ PDO_VAR(5000, 20000, 3000)>;
+ source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
+ try-power-role = "sink";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ typec1_dr_sw: endpoint {
+ remote-endpoint = <&usb1_drd_sw>;
+ };
+ };
+ };
+ };
+ };
+
+ pcf2131: rtc@53 {
+ compatible = "nxp,pcf2131";
+ reg = <0x53>;
+ interrupt-parent = <&pcal6524>;
+ interrupts = <1 IRQ_TYPE_EDGE_FALLING>;
+ };
+};
+
+&lpuart1 { /* console */
+ pinctrl-0 = <&pinctrl_uart1>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&usbotg1 {
+ adp-disable;
+ disable-over-current;
+ dr_mode = "otg";
+ hnp-disable;
+ srp-disable;
+ usb-role-switch;
+ samsung,picophy-dc-vol-level-adjust = <7>;
+ samsung,picophy-pre-emp-curr-control = <3>;
+ status = "okay";
+
+ port {
+
+ usb1_drd_sw: endpoint {
+ remote-endpoint = <&typec1_dr_sw>;
+ };
+ };
+};
+
+&usbotg2 {
+ disable-over-current;
+ dr_mode = "host";
+ samsung,picophy-dc-vol-level-adjust = <7>;
+ samsung,picophy-pre-emp-curr-control = <3>;
+ status = "okay";
+};
+
+&usdhc1 {
+ bus-width = <8>;
+ non-removable;
+ pinctrl-0 = <&pinctrl_usdhc1>;
+ pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
+ pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ status = "okay";
+};
+
+&usdhc2 {
+ bus-width = <4>;
+ cd-gpios = <&gpio3 00 GPIO_ACTIVE_LOW>;
+ no-mmc;
+ no-sdio;
+ pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
+ pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
+ pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
+ pinctrl-3 = <&pinctrl_usdhc2_sleep>, <&pinctrl_usdhc2_gpio_sleep>;
+ pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
+ vmmc-supply = <&reg_usdhc2_vmmc>;
+ status = "okay";
+};
+
+&wdog3 {
+ status = "okay";
+};
+
+&iomuxc {
+
+ pinctrl_eqos: eqosgrp {
+ fsl,pins = <
+ MX93_PAD_ENET1_MDC__ENET_QOS_MDC 0x57e
+ MX93_PAD_ENET1_MDIO__ENET_QOS_MDIO 0x57e
+ MX93_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 0x57e
+ MX93_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 0x57e
+ MX93_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2 0x57e
+ MX93_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3 0x57e
+ MX93_PAD_ENET1_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x58e
+ MX93_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x57e
+ MX93_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0 0x57e
+ MX93_PAD_ENET1_TD1__ENET_QOS_RGMII_TD1 0x57e
+ MX93_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2 0x57e
+ MX93_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3 0x57e
+ MX93_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x58e
+ MX93_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x57e
+ >;
+ };
+
+ pinctrl_eqos_sleep: eqossleepgrp {
+ fsl,pins = <
+ MX93_PAD_ENET1_MDC__GPIO4_IO00 0x31e
+ MX93_PAD_ENET1_MDIO__GPIO4_IO01 0x31e
+ MX93_PAD_ENET1_RD0__GPIO4_IO10 0x31e
+ MX93_PAD_ENET1_RD1__GPIO4_IO11 0x31e
+ MX93_PAD_ENET1_RD2__GPIO4_IO12 0x31e
+ MX93_PAD_ENET1_RD3__GPIO4_IO13 0x31e
+ MX93_PAD_ENET1_RXC__GPIO4_IO09 0x31e
+ MX93_PAD_ENET1_RX_CTL__GPIO4_IO08 0x31e
+ MX93_PAD_ENET1_TD0__GPIO4_IO05 0x31e
+ MX93_PAD_ENET1_TD1__GPIO4_IO04 0x31e
+ MX93_PAD_ENET1_TD2__GPIO4_IO03 0x31e
+ MX93_PAD_ENET1_TD3__GPIO4_IO02 0x31e
+ MX93_PAD_ENET1_TXC__GPIO4_IO07 0x31e
+ MX93_PAD_ENET1_TX_CTL__GPIO4_IO06 0x31e
+ >;
+ };
+
+ pinctrl_fec: fecgrp {
+ fsl,pins = <
+ MX93_PAD_ENET2_MDC__ENET1_MDC 0x57e
+ MX93_PAD_ENET2_MDIO__ENET1_MDIO 0x57e
+ MX93_PAD_ENET2_RD0__ENET1_RGMII_RD0 0x57e
+ MX93_PAD_ENET2_RD1__ENET1_RGMII_RD1 0x57e
+ MX93_PAD_ENET2_RD2__ENET1_RGMII_RD2 0x57e
+ MX93_PAD_ENET2_RD3__ENET1_RGMII_RD3 0x57e
+ MX93_PAD_ENET2_RXC__ENET1_RGMII_RXC 0x58e
+ MX93_PAD_ENET2_RX_CTL__ENET1_RGMII_RX_CTL 0x57e
+ MX93_PAD_ENET2_TD0__ENET1_RGMII_TD0 0x57e
+ MX93_PAD_ENET2_TD1__ENET1_RGMII_TD1 0x57e
+ MX93_PAD_ENET2_TD2__ENET1_RGMII_TD2 0x57e
+ MX93_PAD_ENET2_TD3__ENET1_RGMII_TD3 0x57e
+ MX93_PAD_ENET2_TXC__ENET1_RGMII_TXC 0x58e
+ MX93_PAD_ENET2_TX_CTL__ENET1_RGMII_TX_CTL 0x57e
+ >;
+ };
+
+ pinctrl_fec_sleep: fecsleepgrp {
+ fsl,pins = <
+ MX93_PAD_ENET2_MDC__GPIO4_IO14 0x51e
+ MX93_PAD_ENET2_MDIO__GPIO4_IO15 0x51e
+ MX93_PAD_ENET2_RD0__GPIO4_IO24 0x51e
+ MX93_PAD_ENET2_RD1__GPIO4_IO25 0x51e
+ MX93_PAD_ENET2_RD2__GPIO4_IO26 0x51e
+ MX93_PAD_ENET2_RD3__GPIO4_IO27 0x51e
+ MX93_PAD_ENET2_RXC__GPIO4_IO23 0x51e
+ MX93_PAD_ENET2_RX_CTL__GPIO4_IO22 0x51e
+ MX93_PAD_ENET2_TD0__GPIO4_IO19 0x51e
+ MX93_PAD_ENET2_TD1__GPIO4_IO18 0x51e
+ MX93_PAD_ENET2_TD2__GPIO4_IO17 0x51e
+ MX93_PAD_ENET2_TD3__GPIO4_IO16 0x51e
+ MX93_PAD_ENET2_TXC__GPIO4_IO21 0x51e
+ MX93_PAD_ENET2_TX_CTL__GPIO4_IO20 0x51e
+ >;
+ };
+
+ pinctrl_flexcan2: flexcan2grp {
+ fsl,pins = <
+ MX93_PAD_GPIO_IO25__CAN2_TX 0x139e
+ MX93_PAD_GPIO_IO27__CAN2_RX 0x139e
+ >;
+ };
+
+ pinctrl_lpi2c2: lpi2c2grp {
+ fsl,pins = <
+ MX93_PAD_I2C2_SCL__LPI2C2_SCL 0x40000b9e
+ MX93_PAD_I2C2_SDA__LPI2C2_SDA 0x40000b9e
+ >;
+ };
+
+ pinctrl_lpi2c3: lpi2c3grp {
+ fsl,pins = <
+ MX93_PAD_GPIO_IO28__LPI2C3_SDA 0x40000b9e
+ MX93_PAD_GPIO_IO29__LPI2C3_SCL 0x40000b9e
+ >;
+ };
+
+ pinctrl_pcal6524: pcal6524grp {
+ fsl,pins = <
+ MX93_PAD_CCM_CLKO2__GPIO3_IO27 0x31e
+ >;
+ };
+
+ pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
+ fsl,pins = <
+ MX93_PAD_SD2_RESET_B__GPIO3_IO07 0x31e
+ >;
+ };
+
+ pinctrl_uart1: uart1grp {
+ fsl,pins = <
+ MX93_PAD_UART1_RXD__LPUART1_RX 0x31e
+ MX93_PAD_UART1_TXD__LPUART1_TX 0x31e
+ >;
+ };
+
+ /* need to config the SION for data and cmd pad, refer to ERR052021 */
+ pinctrl_usdhc1: usdhc1grp {
+ fsl,pins = <
+ MX93_PAD_SD1_CLK__USDHC1_CLK 0x1582
+ MX93_PAD_SD1_CMD__USDHC1_CMD 0x40001382
+ MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x40001382
+ MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x40001382
+ MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x40001382
+ MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x40001382
+ MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x40001382
+ MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x40001382
+ MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x40001382
+ MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x40001382
+ MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x1582
+ >;
+ };
+
+ /* need to config the SION for data and cmd pad, refer to ERR052021 */
+ pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
+ fsl,pins = <
+ MX93_PAD_SD1_CLK__USDHC1_CLK 0x158e
+ MX93_PAD_SD1_CMD__USDHC1_CMD 0x4000138e
+ MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x4000138e
+ MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x4000138e
+ MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x4000138e
+ MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x4000138e
+ MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x4000138e
+ MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x4000138e
+ MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x4000138e
+ MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x4000138e
+ MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x158e
+ >;
+ };
+
+ /* need to config the SION for data and cmd pad, refer to ERR052021 */
+ pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
+ fsl,pins = <
+ MX93_PAD_SD1_CLK__USDHC1_CLK 0x15fe
+ MX93_PAD_SD1_CMD__USDHC1_CMD 0x400013fe
+ MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x400013fe
+ MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x400013fe
+ MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x400013fe
+ MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x400013fe
+ MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x400013fe
+ MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x400013fe
+ MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x400013fe
+ MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x400013fe
+ MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x15fe
+ >;
+ };
+
+ pinctrl_usdhc2_gpio: usdhc2gpiogrp {
+ fsl,pins = <
+ MX93_PAD_SD2_CD_B__GPIO3_IO00 0x31e
+ >;
+ };
+
+ pinctrl_usdhc2_gpio_sleep: usdhc2gpiosleepgrp {
+ fsl,pins = <
+ MX93_PAD_SD2_CD_B__GPIO3_IO00 0x51e
+ >;
+ };
+
+ /* need to config the SION for data and cmd pad, refer to ERR052021 */
+ pinctrl_usdhc2: usdhc2grp {
+ fsl,pins = <
+ MX93_PAD_SD2_CLK__USDHC2_CLK 0x1582
+ MX93_PAD_SD2_CMD__USDHC2_CMD 0x40001382
+ MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x40001382
+ MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x40001382
+ MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x40001382
+ MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x40001382
+ MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e
+ >;
+ };
+
+ /* need to config the SION for data and cmd pad, refer to ERR052021 */
+ pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
+ fsl,pins = <
+ MX93_PAD_SD2_CLK__USDHC2_CLK 0x158e
+ MX93_PAD_SD2_CMD__USDHC2_CMD 0x4000138e
+ MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x4000138e
+ MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x4000138e
+ MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x4000138e
+ MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x4000138e
+ MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e
+ >;
+ };
+
+ /* need to config the SION for data and cmd pad, refer to ERR052021 */
+ pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
+ fsl,pins = <
+ MX93_PAD_SD2_CLK__USDHC2_CLK 0x15fe
+ MX93_PAD_SD2_CMD__USDHC2_CMD 0x400013fe
+ MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x400013fe
+ MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x400013fe
+ MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x400013fe
+ MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x400013fe
+ MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e
+ >;
+ };
+
+ pinctrl_usdhc2_sleep: usdhc2-sleepgrp {
+ fsl,pins = <
+ MX93_PAD_SD2_CLK__GPIO3_IO01 0x51e
+ MX93_PAD_SD2_CMD__GPIO3_IO02 0x51e
+ MX93_PAD_SD2_DATA0__GPIO3_IO03 0x51e
+ MX93_PAD_SD2_DATA1__GPIO3_IO04 0x51e
+ MX93_PAD_SD2_DATA2__GPIO3_IO05 0x51e
+ MX93_PAD_SD2_DATA3__GPIO3_IO06 0x51e
+ MX93_PAD_SD2_VSELECT__GPIO3_IO19 0x51e
+ >;
+ };
+};
diff --git a/arch/arm/include/asm/arch-imx9/ddr.h b/arch/arm/include/asm/arch-imx9/ddr.h
index 0dd2d62b9ef..a8e3f7354c7 100644
--- a/arch/arm/include/asm/arch-imx9/ddr.h
+++ b/arch/arm/include/asm/arch-imx9/ddr.h
@@ -118,6 +118,7 @@ void ddrphy_init_set_dfi_clk(unsigned int drate);
void ddrphy_init_read_msg_block(enum fw_type type);
void get_trained_CDD(unsigned int fsp);
+u32 lpddr4_mr_read(u32 mr_rank, u32 mr_addr);
ulong ddrphy_addr_remap(u32 paddr_apb_from_ctlr);
diff --git a/arch/arm/mach-imx/imx9/Kconfig b/arch/arm/mach-imx/imx9/Kconfig
index 95bd1823531..4e0e194690b 100644
--- a/arch/arm/mach-imx/imx9/Kconfig
+++ b/arch/arm/mach-imx/imx9/Kconfig
@@ -66,6 +66,14 @@ config TARGET_IMX93_11X11_EVK
imply BOOTSTD_FULL
imply BOOTSTD_BOOTCOMMAND
+config TARGET_IMX93_FRDM
+ bool "imx93_frdm"
+ select OF_BOARD_FIXUP
+ select IMX93
+ select IMX9_LPDDR4X
+ imply BOOTSTD_FULL
+ imply BOOTSTD_BOOTCOMMAND
+
config TARGET_IMX93_VAR_SOM
bool "imx93_var_som"
select IMX93
@@ -90,6 +98,7 @@ endchoice
source "board/freescale/imx91_evk/Kconfig"
source "board/freescale/imx93_evk/Kconfig"
+source "board/freescale/imx93_frdm/Kconfig"
source "board/freescale/imx93_qsb/Kconfig"
source "board/phytec/phycore_imx93/Kconfig"
source "board/variscite/imx93_var_som/Kconfig"
diff --git a/arch/arm/mach-k3/j784s4/j784s4_init.c b/arch/arm/mach-k3/j784s4/j784s4_init.c
index 0f11511bda0..53f152ccd9c 100644
--- a/arch/arm/mach-k3/j784s4/j784s4_init.c
+++ b/arch/arm/mach-k3/j784s4/j784s4_init.c
@@ -17,6 +17,7 @@
#include <dm/pinctrl.h>
#include <mmc.h>
#include <remoteproc.h>
+#include <k3_bist.h>
#include "../sysfw-loader.h"
#include "../common.h"
@@ -122,6 +123,48 @@ static void setup_navss_nb(void)
writel(NB_THREADMAP_BIT2, (uintptr_t)NAVSS0_NBSS_NB1_CFG_NB_THREADMAP);
}
+/* Execute and check results of BIST executed on MCU1_x and MCU4_O */
+static void run_bist_j784s4(struct udevice *dev)
+{
+ struct bist_ops *ops;
+ struct ti_sci_handle *handle;
+ int ret;
+
+ ops = (struct bist_ops *)device_get_ops(dev);
+ handle = get_ti_sci_handle();
+
+ /* get status of HW POST PBIST on MCU1_x */
+ if (ops->run_pbist_post())
+ panic("HW POST LBIST on MCU1_x failed\n");
+
+ /* trigger PBIST tests on MCU4_0 */
+ ret = prepare_pbist(handle);
+ ret |= ops->run_pbist_neg();
+ ret |= deprepare_pbist(handle);
+
+ ret |= prepare_pbist(handle);
+ ret |= ops->run_pbist();
+ ret |= deprepare_pbist(handle);
+
+ ret |= prepare_pbist(handle);
+ ret |= ops->run_pbist_rom();
+ ret |= deprepare_pbist(handle);
+
+ if (ret)
+ panic("PBIST on MCU4_0 failed: %d\n", ret);
+
+ /* get status of HW POST PBIST on MCU1_x */
+ if (ops->run_lbist_post())
+ panic("HW POST LBIST on MCU1_x failed\n");
+
+ /* trigger LBIST tests on MCU1_x */
+ ret = prepare_lbist(handle);
+ ret |= ops->run_lbist();
+ ret |= deprepare_lbist(handle);
+ if (ret)
+ panic("LBIST on MCU4_0 failed: %d\n", ret);
+}
+
/*
* This uninitialized global variable would normal end up in the .bss section,
* but the .bss is cleared between writing and reading this variable, so move
@@ -266,6 +309,15 @@ void board_init_f(ulong dummy)
printf("AVS init failed: %d\n", ret);
}
+ if (!IS_ENABLED(CONFIG_CPU_V7R) && IS_ENABLED(CONFIG_K3_BIST)) {
+ ret = uclass_get_device_by_driver(UCLASS_MISC,
+ DM_DRIVER_GET(k3_bist),
+ &dev);
+ if (ret)
+ panic("Failed to get BIST device: %d\n", ret);
+ run_bist_j784s4(dev);
+ }
+
if (IS_ENABLED(CONFIG_CPU_V7R))
setup_navss_nb();
diff --git a/board/freescale/imx93_evk/MAINTAINERS b/board/freescale/imx93_evk/MAINTAINERS
index 34ba278fcdf..eb6e669bd17 100644
--- a/board/freescale/imx93_evk/MAINTAINERS
+++ b/board/freescale/imx93_evk/MAINTAINERS
@@ -1,4 +1,4 @@
-i.MX93 MEK BOARD
+i.MX93 EVK BOARD
M: Peng Fan <peng.fan@nxp.com>
S: Maintained
F: board/freescale/imx93_evk/
diff --git a/board/freescale/imx93_evk/imx93_evk.c b/board/freescale/imx93_evk/imx93_evk.c
index d84d56be5e1..d62f94dc418 100644
--- a/board/freescale/imx93_evk/imx93_evk.c
+++ b/board/freescale/imx93_evk/imx93_evk.c
@@ -13,11 +13,8 @@
#include <asm/arch/sys_proto.h>
#include <asm/arch-imx9/imx93_pins.h>
#include <asm/arch/clock.h>
-#include <power/pmic.h>
#include <dm/device.h>
#include <dm/uclass.h>
-#include <usb.h>
-#include <dwc3-uboot.h>
DECLARE_GLOBAL_DATA_PTR;
diff --git a/board/freescale/imx93_frdm/Kconfig b/board/freescale/imx93_frdm/Kconfig
new file mode 100644
index 00000000000..5f5ac7f8f04
--- /dev/null
+++ b/board/freescale/imx93_frdm/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_IMX93_FRDM
+
+config SYS_BOARD
+ default "imx93_frdm"
+
+config SYS_VENDOR
+ default "freescale"
+
+config SYS_CONFIG_NAME
+ default "imx93_frdm"
+
+endif
diff --git a/board/freescale/imx93_frdm/MAINTAINERS b/board/freescale/imx93_frdm/MAINTAINERS
new file mode 100644
index 00000000000..59595bb2118
--- /dev/null
+++ b/board/freescale/imx93_frdm/MAINTAINERS
@@ -0,0 +1,6 @@
+i.MX93 FRDM BOARD
+M: Fabio Estevam <festevam@gmail.com>
+S: Maintained
+F: board/freescale/imx93_frdm/
+F: include/configs/imx93_frdm.h
+F: configs/imx93_frdm_defconfig
diff --git a/board/freescale/imx93_frdm/Makefile b/board/freescale/imx93_frdm/Makefile
new file mode 100644
index 00000000000..9612b1fa55b
--- /dev/null
+++ b/board/freescale/imx93_frdm/Makefile
@@ -0,0 +1,11 @@
+#
+# Copyright 2025 NXP
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += imx93_frdm.o
+
+ifdef CONFIG_XPL_BUILD
+obj-y += spl.o lpddr4x_1gb_timing.o lpddr4x_2gb_timing.o
+endif
diff --git a/board/freescale/imx93_frdm/imx93_frdm.c b/board/freescale/imx93_frdm/imx93_frdm.c
new file mode 100644
index 00000000000..c74fd85712f
--- /dev/null
+++ b/board/freescale/imx93_frdm/imx93_frdm.c
@@ -0,0 +1,59 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2025 NXP
+ */
+
+#include <env.h>
+#include <efi_loader.h>
+#include <init.h>
+#include <asm/global_data.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch-imx9/imx93_pins.h>
+#include <asm/arch/clock.h>
+#include <dm/device.h>
+#include <dm/uclass.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#if IS_ENABLED(CONFIG_EFI_HAVE_CAPSULE_SUPPORT)
+#define IMX_BOOT_IMAGE_GUID \
+ EFI_GUID(0xbc550d86, 0xda26, 0x4b70, 0xac, 0x05, \
+ 0x2a, 0x44, 0x8e, 0xda, 0x6f, 0x21)
+
+struct efi_fw_image fw_images[] = {
+ {
+ .image_type_id = IMX_BOOT_IMAGE_GUID,
+ .fw_name = u"IMX93-11X11-FRDM-RAW",
+ .image_index = 1,
+ },
+};
+
+struct efi_capsule_update_info update_info = {
+ .dfu_string = "mmc 0=flash-bin raw 0 0x2000 mmcpart 1",
+ .num_images = ARRAY_SIZE(fw_images),
+ .images = fw_images,
+};
+#endif /* EFI_HAVE_CAPSULE_SUPPORT */
+
+int board_early_init_f(void)
+{
+ return 0;
+}
+
+int board_init(void)
+{
+ return 0;
+}
+
+int board_late_init(void)
+{
+ if (IS_ENABLED(CONFIG_ENV_IS_IN_MMC) || IS_ENABLED(CONFIG_ENV_IS_IN_NOWHERE))
+ board_late_mmc_env_init();
+
+ if (IS_ENABLED(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG)) {
+ env_set("board_name", "11X11_FRDM");
+ env_set("board_rev", "iMX93");
+ }
+
+ return 0;
+}
diff --git a/board/freescale/imx93_frdm/imx93_frdm.env b/board/freescale/imx93_frdm/imx93_frdm.env
new file mode 100644
index 00000000000..528a953c8df
--- /dev/null
+++ b/board/freescale/imx93_frdm/imx93_frdm.env
@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+
+boot_targets=mmc0 mmc1
+boot_fit=no
+bootm_size=0x10000000
+cntr_addr=0x98000000
+cntr_file=os_cntr_signed.bin
+console=ttyLP0,115200
+fdt_addr_r=0x83000000
+fdt_addr=0x83000000
+fdtfile=CONFIG_DEFAULT_FDT_FILE
+image=Image
+mmcdev=1
+mmcpart=1
+mmcroot=/dev/mmcblk${mmcdev}p2 rootwait rw
+mmcautodetect=yes
+mmcargs=setenv bootargs console=${console} root=${mmcroot}
+kernel_addr_r=CONFIG_SYS_LOAD_ADDR
+loadimage=load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}
+loadfdt=load mmc ${mmcdev}:${mmcpart} ${fdt_addr_r} ${fdtfile}
+boot_os=booti ${loadaddr} - ${fdt_addr_r}
+
+bsp_bootcmd=
+ echo Running BSP bootcmd ...;
+ mmc dev ${mmcdev};
+ run mmcargs;
+ run loadimage;
+ run loadfdt;
+ run boot_os;
+
+scriptaddr=0x83500000
diff --git a/board/freescale/imx93_frdm/lpddr4_timing.h b/board/freescale/imx93_frdm/lpddr4_timing.h
new file mode 100644
index 00000000000..192bc9e1519
--- /dev/null
+++ b/board/freescale/imx93_frdm/lpddr4_timing.h
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2022 Marek Vasut <marex@denx.de>
+ */
+
+#ifndef __LPDDR4_TIMING_H__
+#define __LPDDR4_TIMING_H__
+
+extern struct dram_timing_info dram_timing_1GB;
+extern struct dram_timing_info dram_timing_2GB;
+
+#endif /* __LPDDR4_TIMING_H__ */
diff --git a/board/freescale/imx93_frdm/lpddr4x_1gb_timing.c b/board/freescale/imx93_frdm/lpddr4x_1gb_timing.c
new file mode 100644
index 00000000000..17549206ee4
--- /dev/null
+++ b/board/freescale/imx93_frdm/lpddr4x_1gb_timing.c
@@ -0,0 +1,1996 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright 2025 NXP
+ *
+ * Code generated with DDR Tool v3.3.0_7.8-d1cdb7d3.
+ * DDR PHY FW2022.01
+ */
+
+#include <linux/kernel.h>
+#include <asm/arch/ddr.h>
+
+/* Initialize DDRC registers */
+static struct dram_cfg_param ddr_ddrc_cfg[] = {
+ {0x4e300110, 0x44100001},
+ {0x4e300000, 0x8000bf},
+ {0x4e300008, 0x0},
+ {0x4e300080, 0x80000412},
+ {0x4e300084, 0x0},
+ {0x4e300114, 0x1002},
+ {0x4e300260, 0x80},
+ {0x4e300f04, 0x80},
+ {0x4e300800, 0x43b30002},
+ {0x4e300804, 0x1f1f1f1f},
+ {0x4e301000, 0x0},
+ {0x4e301240, 0x0},
+ {0x4e301244, 0x0},
+ {0x4e301248, 0x0},
+ {0x4e30124c, 0x0},
+ {0x4e301250, 0x0},
+ {0x4e301254, 0x0},
+ {0x4e301258, 0x0},
+ {0x4e30125c, 0x0},
+};
+
+/* dram fsp cfg */
+static struct dram_fsp_cfg ddr_dram_fsp_cfg[] = {
+ {
+ {
+ {0x4e300100, 0x24A0321B},
+ {0x4e300104, 0xF8EE001B},
+ {0x4e300108, 0x2F2E3233},
+ {0x4e30010C, 0x0005C18B},
+ {0x4e300124, 0x1C790000},
+ {0x4e300160, 0x00009102},
+ {0x4e30016C, 0x35F00000},
+ {0x4e300170, 0x8B0B0608},
+ {0x4e300250, 0x00000028},
+ {0x4e300254, 0x00FE00FE},
+ {0x4e300258, 0x00000008},
+ {0x4e30025C, 0x00000400},
+ {0x4e300300, 0x224F2213},
+ {0x4e300304, 0x00FE2213},
+ {0x4e300308, 0x0A380E3D},
+ },
+ {
+ {0x01, 0xE4},
+ {0x02, 0x36},
+ {0x03, 0x32},
+ {0x0b, 0x46},
+ {0x0c, 0x11},
+ {0x0e, 0x11},
+ {0x16, 0x04},
+ },
+ 0,
+ },
+ {
+ {
+ {0x4e300100, 0x124F2100},
+ {0x4e300104, 0xF877000E},
+ {0x4e300108, 0x1816E4AA},
+ {0x4e30010C, 0x005101E6},
+ {0x4e300124, 0x0E3C0000},
+ {0x4e300160, 0x00009101},
+ {0x4e30016C, 0x30900000},
+ {0x4e300170, 0x8A0A0508},
+ {0x4e300250, 0x00000014},
+ {0x4e300254, 0x007B007B},
+ {0x4e300258, 0x00000008},
+ {0x4e30025C, 0x00000400},
+ },
+ {
+ {0x01, 0xB4},
+ {0x02, 0x1B},
+ {0x03, 0x32},
+ {0x0b, 0x46},
+ {0x0c, 0x11},
+ {0x0e, 0x11},
+ {0x16, 0x04},
+ },
+ 0,
+ },
+ {
+ {
+ {0x4e300100, 0x00051000},
+ {0x4e300104, 0xF855000A},
+ {0x4e300108, 0x6E620A48},
+ {0x4e30010C, 0x0031010D},
+ {0x4e300124, 0x04C50000},
+ {0x4e300160, 0x00009100},
+ {0x4e30016C, 0x30000000},
+ {0x4e300170, 0x89090408},
+ {0x4e300250, 0x00000007},
+ {0x4e300254, 0x00240024},
+ {0x4e300258, 0x00000008},
+ {0x4e30025C, 0x00000400},
+ },
+ {
+ {0x01, 0x94},
+ {0x02, 0x9},
+ {0x03, 0x32},
+ {0x0b, 0x46},
+ {0x0c, 0x11},
+ {0x0e, 0x11},
+ {0x16, 0x04},
+ },
+ 1,
+ },
+
+};
+
+/* PHY Initialize Configuration */
+static struct dram_cfg_param ddr_ddrphy_cfg[] = {
+ {0x100a0, 0x4},
+ {0x100a1, 0x5},
+ {0x100a2, 0x6},
+ {0x100a3, 0x7},
+ {0x100a4, 0x0},
+ {0x100a5, 0x1},
+ {0x100a6, 0x2},
+ {0x100a7, 0x3},
+ {0x110a0, 0x3},
+ {0x110a1, 0x2},
+ {0x110a2, 0x0},
+ {0x110a3, 0x1},
+ {0x110a4, 0x7},
+ {0x110a5, 0x6},
+ {0x110a6, 0x4},
+ {0x110a7, 0x5},
+ {0x1005f, 0x5ff},
+ {0x1015f, 0x5ff},
+ {0x1105f, 0x5ff},
+ {0x1115f, 0x5ff},
+ {0x11005f, 0x5ff},
+ {0x11015f, 0x5ff},
+ {0x11105f, 0x5ff},
+ {0x11115f, 0x5ff},
+ {0x21005f, 0x5ff},
+ {0x21015f, 0x5ff},
+ {0x21105f, 0x5ff},
+ {0x21115f, 0x5ff},
+ {0x55, 0x1ff},
+ {0x1055, 0x1ff},
+ {0x2055, 0x1ff},
+ {0x200c5, 0x19},
+ {0x1200c5, 0xb},
+ {0x2200c5, 0x7},
+ {0x2002e, 0x2},
+ {0x12002e, 0x2},
+ {0x22002e, 0x2},
+ {0x90204, 0x0},
+ {0x190204, 0x0},
+ {0x290204, 0x0},
+ {0x20024, 0x1e3},
+ {0x2003a, 0x2},
+ {0x2007d, 0x212},
+ {0x2007c, 0x61},
+ {0x120024, 0x1e3},
+ {0x2003a, 0x2},
+ {0x12007d, 0x212},
+ {0x12007c, 0x61},
+ {0x220024, 0x1e3},
+ {0x2003a, 0x2},
+ {0x22007d, 0x212},
+ {0x22007c, 0x61},
+ {0x20056, 0x3},
+ {0x120056, 0x3},
+ {0x220056, 0x3},
+ {0x1004d, 0x600},
+ {0x1014d, 0x600},
+ {0x1104d, 0x600},
+ {0x1114d, 0x600},
+ {0x11004d, 0x600},
+ {0x11014d, 0x600},
+ {0x11104d, 0x600},
+ {0x11114d, 0x600},
+ {0x21004d, 0x600},
+ {0x21014d, 0x600},
+ {0x21104d, 0x600},
+ {0x21114d, 0x600},
+ {0x10049, 0xe00},
+ {0x10149, 0xe00},
+ {0x11049, 0xe00},
+ {0x11149, 0xe00},
+ {0x110049, 0xe00},
+ {0x110149, 0xe00},
+ {0x111049, 0xe00},
+ {0x111149, 0xe00},
+ {0x210049, 0xe00},
+ {0x210149, 0xe00},
+ {0x211049, 0xe00},
+ {0x211149, 0xe00},
+ {0x43, 0x60},
+ {0x1043, 0x60},
+ {0x2043, 0x60},
+ {0x20018, 0x1},
+ {0x20075, 0x4},
+ {0x20050, 0x0},
+ {0x2009b, 0x2},
+ {0x20008, 0x3a5},
+ {0x120008, 0x1d3},
+ {0x220008, 0x9c},
+ {0x20088, 0x9},
+ {0x200b2, 0x10c},
+ {0x10043, 0x5a1},
+ {0x10143, 0x5a1},
+ {0x11043, 0x5a1},
+ {0x11143, 0x5a1},
+ {0x1200b2, 0x10c},
+ {0x110043, 0x5a1},
+ {0x110143, 0x5a1},
+ {0x111043, 0x5a1},
+ {0x111143, 0x5a1},
+ {0x2200b2, 0x10c},
+ {0x210043, 0x5a1},
+ {0x210143, 0x5a1},
+ {0x211043, 0x5a1},
+ {0x211143, 0x5a1},
+ {0x200fa, 0x2},
+ {0x1200fa, 0x2},
+ {0x2200fa, 0x2},
+ {0x20019, 0x1},
+ {0x120019, 0x1},
+ {0x220019, 0x1},
+ {0x200f0, 0x600},
+ {0x200f1, 0x0},
+ {0x200f2, 0x4444},
+ {0x200f3, 0x8888},
+ {0x200f4, 0x5655},
+ {0x200f5, 0x0},
+ {0x200f6, 0x0},
+ {0x200f7, 0xf000},
+ {0x1004a, 0x500},
+ {0x1104a, 0x500},
+ {0x20025, 0x0},
+ {0x2002d, 0x0},
+ {0x12002d, 0x0},
+ {0x22002d, 0x0},
+ {0x2002c, 0x0},
+ {0x20021, 0x0},
+ {0x200c7, 0x21},
+ {0x1200c7, 0x21},
+ {0x200ca, 0x24},
+ {0x1200ca, 0x24},
+};
+
+/* PHY trained csr */
+static struct dram_cfg_param ddr_ddrphy_trained_csr[] = {
+ {0x1005f, 0x0},
+ {0x1015f, 0x0},
+ {0x1105f, 0x0},
+ {0x1115f, 0x0},
+ {0x11005f, 0x0},
+ {0x11015f, 0x0},
+ {0x11105f, 0x0},
+ {0x11115f, 0x0},
+ {0x21005f, 0x0},
+ {0x21015f, 0x0},
+ {0x21105f, 0x0},
+ {0x21115f, 0x0},
+ {0x55, 0x0},
+ {0x1055, 0x0},
+ {0x2055, 0x0},
+ {0x200c5, 0x0},
+ {0x1200c5, 0x0},
+ {0x2200c5, 0x0},
+ {0x2002e, 0x0},
+ {0x12002e, 0x0},
+ {0x22002e, 0x0},
+ {0x90204, 0x0},
+ {0x190204, 0x0},
+ {0x290204, 0x0},
+ {0x20024, 0x0},
+ {0x2003a, 0x0},
+ {0x2007d, 0x0},
+ {0x2007c, 0x0},
+ {0x120024, 0x0},
+ {0x12007d, 0x0},
+ {0x12007c, 0x0},
+ {0x220024, 0x0},
+ {0x22007d, 0x0},
+ {0x22007c, 0x0},
+ {0x20056, 0x0},
+ {0x120056, 0x0},
+ {0x220056, 0x0},
+ {0x1004d, 0x0},
+ {0x1014d, 0x0},
+ {0x1104d, 0x0},
+ {0x1114d, 0x0},
+ {0x11004d, 0x0},
+ {0x11014d, 0x0},
+ {0x11104d, 0x0},
+ {0x11114d, 0x0},
+ {0x21004d, 0x0},
+ {0x21014d, 0x0},
+ {0x21104d, 0x0},
+ {0x21114d, 0x0},
+ {0x10049, 0x0},
+ {0x10149, 0x0},
+ {0x11049, 0x0},
+ {0x11149, 0x0},
+ {0x110049, 0x0},
+ {0x110149, 0x0},
+ {0x111049, 0x0},
+ {0x111149, 0x0},
+ {0x210049, 0x0},
+ {0x210149, 0x0},
+ {0x211049, 0x0},
+ {0x211149, 0x0},
+ {0x43, 0x0},
+ {0x1043, 0x0},
+ {0x2043, 0x0},
+ {0x20018, 0x0},
+ {0x20075, 0x0},
+ {0x20050, 0x0},
+ {0x2009b, 0x0},
+ {0x20008, 0x0},
+ {0x120008, 0x0},
+ {0x220008, 0x0},
+ {0x20088, 0x0},
+ {0x200b2, 0x0},
+ {0x10043, 0x0},
+ {0x10143, 0x0},
+ {0x11043, 0x0},
+ {0x11143, 0x0},
+ {0x1200b2, 0x0},
+ {0x110043, 0x0},
+ {0x110143, 0x0},
+ {0x111043, 0x0},
+ {0x111143, 0x0},
+ {0x2200b2, 0x0},
+ {0x210043, 0x0},
+ {0x210143, 0x0},
+ {0x211043, 0x0},
+ {0x211143, 0x0},
+ {0x200fa, 0x0},
+ {0x1200fa, 0x0},
+ {0x2200fa, 0x0},
+ {0x20019, 0x0},
+ {0x120019, 0x0},
+ {0x220019, 0x0},
+ {0x200f0, 0x0},
+ {0x200f1, 0x0},
+ {0x200f2, 0x0},
+ {0x200f3, 0x0},
+ {0x200f4, 0x0},
+ {0x200f5, 0x0},
+ {0x200f6, 0x0},
+ {0x200f7, 0x0},
+ {0x1004a, 0x0},
+ {0x1104a, 0x0},
+ {0x20025, 0x0},
+ {0x2002d, 0x0},
+ {0x12002d, 0x0},
+ {0x22002d, 0x0},
+ {0x2002c, 0x0},
+ {0xd0000, 0x0},
+ {0x90000, 0x0},
+ {0x90001, 0x0},
+ {0x90002, 0x0},
+ {0x90003, 0x0},
+ {0x90004, 0x0},
+ {0x90005, 0x0},
+ {0x90029, 0x0},
+ {0x9002a, 0x0},
+ {0x9002b, 0x0},
+ {0x9002c, 0x0},
+ {0x9002d, 0x0},
+ {0x9002e, 0x0},
+ {0x9002f, 0x0},
+ {0x90030, 0x0},
+ {0x90031, 0x0},
+ {0x90032, 0x0},
+ {0x90033, 0x0},
+ {0x90034, 0x0},
+ {0x90035, 0x0},
+ {0x90036, 0x0},
+ {0x90037, 0x0},
+ {0x90038, 0x0},
+ {0x90039, 0x0},
+ {0x9003a, 0x0},
+ {0x9003b, 0x0},
+ {0x9003c, 0x0},
+ {0x9003d, 0x0},
+ {0x9003e, 0x0},
+ {0x9003f, 0x0},
+ {0x90040, 0x0},
+ {0x90041, 0x0},
+ {0x90042, 0x0},
+ {0x90043, 0x0},
+ {0x90044, 0x0},
+ {0x90045, 0x0},
+ {0x90046, 0x0},
+ {0x90047, 0x0},
+ {0x90048, 0x0},
+ {0x90049, 0x0},
+ {0x9004a, 0x0},
+ {0x9004b, 0x0},
+ {0x9004c, 0x0},
+ {0x9004d, 0x0},
+ {0x9004e, 0x0},
+ {0x9004f, 0x0},
+ {0x90050, 0x0},
+ {0x90051, 0x0},
+ {0x90052, 0x0},
+ {0x90053, 0x0},
+ {0x90054, 0x0},
+ {0x90055, 0x0},
+ {0x90056, 0x0},
+ {0x90057, 0x0},
+ {0x90058, 0x0},
+ {0x90059, 0x0},
+ {0x9005a, 0x0},
+ {0x9005b, 0x0},
+ {0x9005c, 0x0},
+ {0x9005d, 0x0},
+ {0x9005e, 0x0},
+ {0x9005f, 0x0},
+ {0x90060, 0x0},
+ {0x90061, 0x0},
+ {0x90062, 0x0},
+ {0x90063, 0x0},
+ {0x90064, 0x0},
+ {0x90065, 0x0},
+ {0x90066, 0x0},
+ {0x90067, 0x0},
+ {0x90068, 0x0},
+ {0x90069, 0x0},
+ {0x9006a, 0x0},
+ {0x9006b, 0x0},
+ {0x9006c, 0x0},
+ {0x9006d, 0x0},
+ {0x9006e, 0x0},
+ {0x9006f, 0x0},
+ {0x90070, 0x0},
+ {0x90071, 0x0},
+ {0x90072, 0x0},
+ {0x90073, 0x0},
+ {0x90074, 0x0},
+ {0x90075, 0x0},
+ {0x90076, 0x0},
+ {0x90077, 0x0},
+ {0x90078, 0x0},
+ {0x90079, 0x0},
+ {0x9007a, 0x0},
+ {0x9007b, 0x0},
+ {0x9007c, 0x0},
+ {0x9007d, 0x0},
+ {0x9007e, 0x0},
+ {0x9007f, 0x0},
+ {0x90080, 0x0},
+ {0x90081, 0x0},
+ {0x90082, 0x0},
+ {0x90083, 0x0},
+ {0x90084, 0x0},
+ {0x90085, 0x0},
+ {0x90086, 0x0},
+ {0x90087, 0x0},
+ {0x90088, 0x0},
+ {0x90089, 0x0},
+ {0x9008a, 0x0},
+ {0x9008b, 0x0},
+ {0x9008c, 0x0},
+ {0x9008d, 0x0},
+ {0x9008e, 0x0},
+ {0x9008f, 0x0},
+ {0x90090, 0x0},
+ {0x90091, 0x0},
+ {0x90092, 0x0},
+ {0x90093, 0x0},
+ {0x90094, 0x0},
+ {0x90095, 0x0},
+ {0x90096, 0x0},
+ {0x90097, 0x0},
+ {0x90098, 0x0},
+ {0x90099, 0x0},
+ {0x9009a, 0x0},
+ {0x9009b, 0x0},
+ {0x9009c, 0x0},
+ {0x9009d, 0x0},
+ {0x9009e, 0x0},
+ {0x9009f, 0x0},
+ {0x900a0, 0x0},
+ {0x900a1, 0x0},
+ {0x900a2, 0x0},
+ {0x900a3, 0x0},
+ {0x900a4, 0x0},
+ {0x900a5, 0x0},
+ {0x900a6, 0x0},
+ {0x900a7, 0x0},
+ {0x900a8, 0x0},
+ {0x900a9, 0x0},
+ {0x40000, 0x0},
+ {0x40020, 0x0},
+ {0x40040, 0x0},
+ {0x40060, 0x0},
+ {0x40001, 0x0},
+ {0x40021, 0x0},
+ {0x40041, 0x0},
+ {0x40061, 0x0},
+ {0x40002, 0x0},
+ {0x40022, 0x0},
+ {0x40042, 0x0},
+ {0x40062, 0x0},
+ {0x40003, 0x0},
+ {0x40023, 0x0},
+ {0x40043, 0x0},
+ {0x40063, 0x0},
+ {0x40004, 0x0},
+ {0x40024, 0x0},
+ {0x40044, 0x0},
+ {0x40064, 0x0},
+ {0x40005, 0x0},
+ {0x40025, 0x0},
+ {0x40045, 0x0},
+ {0x40065, 0x0},
+ {0x40006, 0x0},
+ {0x40026, 0x0},
+ {0x40046, 0x0},
+ {0x40066, 0x0},
+ {0x40007, 0x0},
+ {0x40027, 0x0},
+ {0x40047, 0x0},
+ {0x40067, 0x0},
+ {0x40008, 0x0},
+ {0x40028, 0x0},
+ {0x40048, 0x0},
+ {0x40068, 0x0},
+ {0x40009, 0x0},
+ {0x40029, 0x0},
+ {0x40049, 0x0},
+ {0x40069, 0x0},
+ {0x4000a, 0x0},
+ {0x4002a, 0x0},
+ {0x4004a, 0x0},
+ {0x4006a, 0x0},
+ {0x4000b, 0x0},
+ {0x4002b, 0x0},
+ {0x4004b, 0x0},
+ {0x4006b, 0x0},
+ {0x4000c, 0x0},
+ {0x4002c, 0x0},
+ {0x4004c, 0x0},
+ {0x4006c, 0x0},
+ {0x4000d, 0x0},
+ {0x4002d, 0x0},
+ {0x4004d, 0x0},
+ {0x4006d, 0x0},
+ {0x4000e, 0x0},
+ {0x4002e, 0x0},
+ {0x4004e, 0x0},
+ {0x4006e, 0x0},
+ {0x4000f, 0x0},
+ {0x4002f, 0x0},
+ {0x4004f, 0x0},
+ {0x4006f, 0x0},
+ {0x40010, 0x0},
+ {0x40030, 0x0},
+ {0x40050, 0x0},
+ {0x40070, 0x0},
+ {0x40011, 0x0},
+ {0x40031, 0x0},
+ {0x40051, 0x0},
+ {0x40071, 0x0},
+ {0x40012, 0x0},
+ {0x40032, 0x0},
+ {0x40052, 0x0},
+ {0x40072, 0x0},
+ {0x40013, 0x0},
+ {0x40033, 0x0},
+ {0x40053, 0x0},
+ {0x40073, 0x0},
+ {0x40014, 0x0},
+ {0x40034, 0x0},
+ {0x40054, 0x0},
+ {0x40074, 0x0},
+ {0x40015, 0x0},
+ {0x40035, 0x0},
+ {0x40055, 0x0},
+ {0x40075, 0x0},
+ {0x40016, 0x0},
+ {0x40036, 0x0},
+ {0x40056, 0x0},
+ {0x40076, 0x0},
+ {0x40017, 0x0},
+ {0x40037, 0x0},
+ {0x40057, 0x0},
+ {0x40077, 0x0},
+ {0x40018, 0x0},
+ {0x40038, 0x0},
+ {0x40058, 0x0},
+ {0x40078, 0x0},
+ {0x40019, 0x0},
+ {0x40039, 0x0},
+ {0x40059, 0x0},
+ {0x40079, 0x0},
+ {0x4001a, 0x0},
+ {0x4003a, 0x0},
+ {0x4005a, 0x0},
+ {0x4007a, 0x0},
+ {0x900aa, 0x0},
+ {0x900ab, 0x0},
+ {0x900ac, 0x0},
+ {0x900ad, 0x0},
+ {0x900ae, 0x0},
+ {0x900af, 0x0},
+ {0x900b0, 0x0},
+ {0x900b1, 0x0},
+ {0x900b2, 0x0},
+ {0x900b3, 0x0},
+ {0x900b4, 0x0},
+ {0x900b5, 0x0},
+ {0x900b6, 0x0},
+ {0x900b7, 0x0},
+ {0x900b8, 0x0},
+ {0x900b9, 0x0},
+ {0x900ba, 0x0},
+ {0x900bb, 0x0},
+ {0x900bc, 0x0},
+ {0x900bd, 0x0},
+ {0x900be, 0x0},
+ {0x900bf, 0x0},
+ {0x900c0, 0x0},
+ {0x900c1, 0x0},
+ {0x900c2, 0x0},
+ {0x900c3, 0x0},
+ {0x900c4, 0x0},
+ {0x900c5, 0x0},
+ {0x900c6, 0x0},
+ {0x900c7, 0x0},
+ {0x900c8, 0x0},
+ {0x900c9, 0x0},
+ {0x900ca, 0x0},
+ {0x900cb, 0x0},
+ {0x900cc, 0x0},
+ {0x900cd, 0x0},
+ {0x900ce, 0x0},
+ {0x900cf, 0x0},
+ {0x900d0, 0x0},
+ {0x900d1, 0x0},
+ {0x900d2, 0x0},
+ {0x900d3, 0x0},
+ {0x900d4, 0x0},
+ {0x900d5, 0x0},
+ {0x900d6, 0x0},
+ {0x900d7, 0x0},
+ {0x900d8, 0x0},
+ {0x900d9, 0x0},
+ {0x900da, 0x0},
+ {0x900db, 0x0},
+ {0x900dc, 0x0},
+ {0x900dd, 0x0},
+ {0x900de, 0x0},
+ {0x900df, 0x0},
+ {0x900e0, 0x0},
+ {0x900e1, 0x0},
+ {0x900e2, 0x0},
+ {0x900e3, 0x0},
+ {0x900e4, 0x0},
+ {0x900e5, 0x0},
+ {0x900e6, 0x0},
+ {0x900e7, 0x0},
+ {0x900e8, 0x0},
+ {0x900e9, 0x0},
+ {0x900ea, 0x0},
+ {0x900eb, 0x0},
+ {0x900ec, 0x0},
+ {0x900ed, 0x0},
+ {0x900ee, 0x0},
+ {0x900ef, 0x0},
+ {0x900f0, 0x0},
+ {0x900f1, 0x0},
+ {0x900f2, 0x0},
+ {0x900f3, 0x0},
+ {0x900f4, 0x0},
+ {0x900f5, 0x0},
+ {0x900f6, 0x0},
+ {0x900f7, 0x0},
+ {0x900f8, 0x0},
+ {0x900f9, 0x0},
+ {0x900fa, 0x0},
+ {0x900fb, 0x0},
+ {0x900fc, 0x0},
+ {0x900fd, 0x0},
+ {0x900fe, 0x0},
+ {0x900ff, 0x0},
+ {0x90100, 0x0},
+ {0x90101, 0x0},
+ {0x90102, 0x0},
+ {0x90103, 0x0},
+ {0x90104, 0x0},
+ {0x90105, 0x0},
+ {0x90106, 0x0},
+ {0x90107, 0x0},
+ {0x90108, 0x0},
+ {0x90109, 0x0},
+ {0x9010a, 0x0},
+ {0x9010b, 0x0},
+ {0x9010c, 0x0},
+ {0x9010d, 0x0},
+ {0x9010e, 0x0},
+ {0x9010f, 0x0},
+ {0x90110, 0x0},
+ {0x90111, 0x0},
+ {0x90112, 0x0},
+ {0x90113, 0x0},
+ {0x90114, 0x0},
+ {0x90115, 0x0},
+ {0x90116, 0x0},
+ {0x90117, 0x0},
+ {0x90118, 0x0},
+ {0x90119, 0x0},
+ {0x9011a, 0x0},
+ {0x9011b, 0x0},
+ {0x9011c, 0x0},
+ {0x9011d, 0x0},
+ {0x9011e, 0x0},
+ {0x9011f, 0x0},
+ {0x90120, 0x0},
+ {0x90121, 0x0},
+ {0x90122, 0x0},
+ {0x90123, 0x0},
+ {0x90124, 0x0},
+ {0x90125, 0x0},
+ {0x90126, 0x0},
+ {0x90127, 0x0},
+ {0x90128, 0x0},
+ {0x90129, 0x0},
+ {0x9012a, 0x0},
+ {0x9012b, 0x0},
+ {0x9012c, 0x0},
+ {0x9012d, 0x0},
+ {0x9012e, 0x0},
+ {0x9012f, 0x0},
+ {0x90130, 0x0},
+ {0x90131, 0x0},
+ {0x90132, 0x0},
+ {0x90133, 0x0},
+ {0x90134, 0x0},
+ {0x90135, 0x0},
+ {0x90136, 0x0},
+ {0x90137, 0x0},
+ {0x90138, 0x0},
+ {0x90139, 0x0},
+ {0x9013a, 0x0},
+ {0x9013b, 0x0},
+ {0x9013c, 0x0},
+ {0x9013d, 0x0},
+ {0x9013e, 0x0},
+ {0x9013f, 0x0},
+ {0x90140, 0x0},
+ {0x90141, 0x0},
+ {0x90142, 0x0},
+ {0x90143, 0x0},
+ {0x90144, 0x0},
+ {0x90145, 0x0},
+ {0x90146, 0x0},
+ {0x90147, 0x0},
+ {0x90148, 0x0},
+ {0x90149, 0x0},
+ {0x9014a, 0x0},
+ {0x9014b, 0x0},
+ {0x9014c, 0x0},
+ {0x9014d, 0x0},
+ {0x9014e, 0x0},
+ {0x9014f, 0x0},
+ {0x90150, 0x0},
+ {0x90151, 0x0},
+ {0x90152, 0x0},
+ {0x90153, 0x0},
+ {0x90154, 0x0},
+ {0x90155, 0x0},
+ {0x90156, 0x0},
+ {0x90157, 0x0},
+ {0x90158, 0x0},
+ {0x90159, 0x0},
+ {0x9015a, 0x0},
+ {0x9015b, 0x0},
+ {0x9015c, 0x0},
+ {0x9015d, 0x0},
+ {0x9015e, 0x0},
+ {0x9015f, 0x0},
+ {0x90160, 0x0},
+ {0x90161, 0x0},
+ {0x90162, 0x0},
+ {0x90163, 0x0},
+ {0x90164, 0x0},
+ {0x90165, 0x0},
+ {0x90166, 0x0},
+ {0x90167, 0x0},
+ {0x90168, 0x0},
+ {0x90169, 0x0},
+ {0x9016a, 0x0},
+ {0x9016b, 0x0},
+ {0x9016c, 0x0},
+ {0x9016d, 0x0},
+ {0x9016e, 0x0},
+ {0x9016f, 0x0},
+ {0x90170, 0x0},
+ {0x90171, 0x0},
+ {0x90172, 0x0},
+ {0x90173, 0x0},
+ {0x90174, 0x0},
+ {0x90175, 0x0},
+ {0x90176, 0x0},
+ {0x90177, 0x0},
+ {0x90178, 0x0},
+ {0x90179, 0x0},
+ {0x9017a, 0x0},
+ {0x9017b, 0x0},
+ {0x9017c, 0x0},
+ {0x9017d, 0x0},
+ {0x9017e, 0x0},
+ {0x9017f, 0x0},
+ {0x90180, 0x0},
+ {0x90181, 0x0},
+ {0x90182, 0x0},
+ {0x90183, 0x0},
+ {0x90184, 0x0},
+ {0x90006, 0x0},
+ {0x90007, 0x0},
+ {0x90008, 0x0},
+ {0x90009, 0x0},
+ {0x9000a, 0x0},
+ {0x9000b, 0x0},
+ {0xd00e7, 0x0},
+ {0x90017, 0x0},
+ {0x9001f, 0x0},
+ {0x90026, 0x0},
+ {0x400d0, 0x0},
+ {0x400d1, 0x0},
+ {0x400d2, 0x0},
+ {0x400d3, 0x0},
+ {0x400d4, 0x0},
+ {0x400d5, 0x0},
+ {0x400d6, 0x0},
+ {0x400d7, 0x0},
+ {0x200be, 0x0},
+ {0x2000b, 0x0},
+ {0x2000c, 0x0},
+ {0x2000d, 0x0},
+ {0x2000e, 0x0},
+ {0x12000b, 0x0},
+ {0x12000c, 0x0},
+ {0x12000d, 0x0},
+ {0x12000e, 0x0},
+ {0x22000b, 0x0},
+ {0x22000c, 0x0},
+ {0x22000d, 0x0},
+ {0x22000e, 0x0},
+ {0x9000c, 0x0},
+ {0x9000d, 0x0},
+ {0x9000e, 0x0},
+ {0x9000f, 0x0},
+ {0x90010, 0x0},
+ {0x90011, 0x0},
+ {0x90012, 0x0},
+ {0x90013, 0x0},
+ {0x20010, 0x0},
+ {0x20011, 0x0},
+ {0x120010, 0x0},
+ {0x120011, 0x0},
+ {0x40080, 0x0},
+ {0x40081, 0x0},
+ {0x40082, 0x0},
+ {0x40083, 0x0},
+ {0x40084, 0x0},
+ {0x40085, 0x0},
+ {0x140080, 0x0},
+ {0x140081, 0x0},
+ {0x140082, 0x0},
+ {0x140083, 0x0},
+ {0x140084, 0x0},
+ {0x140085, 0x0},
+ {0x240080, 0x0},
+ {0x240081, 0x0},
+ {0x240082, 0x0},
+ {0x240083, 0x0},
+ {0x240084, 0x0},
+ {0x240085, 0x0},
+ {0x400fd, 0x0},
+ {0x400f1, 0x0},
+ {0x10011, 0x0},
+ {0x10012, 0x0},
+ {0x10013, 0x0},
+ {0x10018, 0x0},
+ {0x10002, 0x0},
+ {0x100b2, 0x0},
+ {0x101b4, 0x0},
+ {0x102b4, 0x0},
+ {0x103b4, 0x0},
+ {0x104b4, 0x0},
+ {0x105b4, 0x0},
+ {0x106b4, 0x0},
+ {0x107b4, 0x0},
+ {0x108b4, 0x0},
+ {0x11011, 0x0},
+ {0x11012, 0x0},
+ {0x11013, 0x0},
+ {0x11018, 0x0},
+ {0x11002, 0x0},
+ {0x110b2, 0x0},
+ {0x111b4, 0x0},
+ {0x112b4, 0x0},
+ {0x113b4, 0x0},
+ {0x114b4, 0x0},
+ {0x115b4, 0x0},
+ {0x116b4, 0x0},
+ {0x117b4, 0x0},
+ {0x118b4, 0x0},
+ {0x20089, 0x0},
+ {0xc0080, 0x0},
+ {0x200cb, 0x0},
+ {0x10068, 0x0},
+ {0x10069, 0x0},
+ {0x10168, 0x0},
+ {0x10169, 0x0},
+ {0x10268, 0x0},
+ {0x10269, 0x0},
+ {0x10368, 0x0},
+ {0x10369, 0x0},
+ {0x10468, 0x0},
+ {0x10469, 0x0},
+ {0x10568, 0x0},
+ {0x10569, 0x0},
+ {0x10668, 0x0},
+ {0x10669, 0x0},
+ {0x10768, 0x0},
+ {0x10769, 0x0},
+ {0x10868, 0x0},
+ {0x10869, 0x0},
+ {0x100aa, 0x0},
+ {0x10062, 0x0},
+ {0x10001, 0x0},
+ {0x100a0, 0x0},
+ {0x100a1, 0x0},
+ {0x100a2, 0x0},
+ {0x100a3, 0x0},
+ {0x100a4, 0x0},
+ {0x100a5, 0x0},
+ {0x100a6, 0x0},
+ {0x100a7, 0x0},
+ {0x11068, 0x0},
+ {0x11069, 0x0},
+ {0x11168, 0x0},
+ {0x11169, 0x0},
+ {0x11268, 0x0},
+ {0x11269, 0x0},
+ {0x11368, 0x0},
+ {0x11369, 0x0},
+ {0x11468, 0x0},
+ {0x11469, 0x0},
+ {0x11568, 0x0},
+ {0x11569, 0x0},
+ {0x11668, 0x0},
+ {0x11669, 0x0},
+ {0x11768, 0x0},
+ {0x11769, 0x0},
+ {0x11868, 0x0},
+ {0x11869, 0x0},
+ {0x110aa, 0x0},
+ {0x11062, 0x0},
+ {0x11001, 0x0},
+ {0x110a0, 0x0},
+ {0x110a1, 0x0},
+ {0x110a2, 0x0},
+ {0x110a3, 0x0},
+ {0x110a4, 0x0},
+ {0x110a5, 0x0},
+ {0x110a6, 0x0},
+ {0x110a7, 0x0},
+ {0x80, 0x0},
+ {0x1080, 0x0},
+ {0x2080, 0x0},
+ {0x10020, 0x0},
+ {0x10080, 0x0},
+ {0x10081, 0x0},
+ {0x100d0, 0x0},
+ {0x100d1, 0x0},
+ {0x1008c, 0x0},
+ {0x1008d, 0x0},
+ {0x10180, 0x0},
+ {0x10181, 0x0},
+ {0x101d0, 0x0},
+ {0x101d1, 0x0},
+ {0x1018c, 0x0},
+ {0x1018d, 0x0},
+ {0x100c0, 0x0},
+ {0x100c1, 0x0},
+ {0x101c0, 0x0},
+ {0x101c1, 0x0},
+ {0x102c0, 0x0},
+ {0x102c1, 0x0},
+ {0x103c0, 0x0},
+ {0x103c1, 0x0},
+ {0x104c0, 0x0},
+ {0x104c1, 0x0},
+ {0x105c0, 0x0},
+ {0x105c1, 0x0},
+ {0x106c0, 0x0},
+ {0x106c1, 0x0},
+ {0x107c0, 0x0},
+ {0x107c1, 0x0},
+ {0x108c0, 0x0},
+ {0x108c1, 0x0},
+ {0x100ae, 0x0},
+ {0x100af, 0x0},
+ {0x11020, 0x0},
+ {0x11080, 0x0},
+ {0x11081, 0x0},
+ {0x110d0, 0x0},
+ {0x110d1, 0x0},
+ {0x1108c, 0x0},
+ {0x1108d, 0x0},
+ {0x11180, 0x0},
+ {0x11181, 0x0},
+ {0x111d0, 0x0},
+ {0x111d1, 0x0},
+ {0x1118c, 0x0},
+ {0x1118d, 0x0},
+ {0x110c0, 0x0},
+ {0x110c1, 0x0},
+ {0x111c0, 0x0},
+ {0x111c1, 0x0},
+ {0x112c0, 0x0},
+ {0x112c1, 0x0},
+ {0x113c0, 0x0},
+ {0x113c1, 0x0},
+ {0x114c0, 0x0},
+ {0x114c1, 0x0},
+ {0x115c0, 0x0},
+ {0x115c1, 0x0},
+ {0x116c0, 0x0},
+ {0x116c1, 0x0},
+ {0x117c0, 0x0},
+ {0x117c1, 0x0},
+ {0x118c0, 0x0},
+ {0x118c1, 0x0},
+ {0x110ae, 0x0},
+ {0x110af, 0x0},
+ {0x90201, 0x0},
+ {0x90202, 0x0},
+ {0x90203, 0x0},
+ {0x90205, 0x0},
+ {0x90206, 0x0},
+ {0x90207, 0x0},
+ {0x90208, 0x0},
+ {0x20020, 0x0},
+ {0x100080, 0x0},
+ {0x101080, 0x0},
+ {0x102080, 0x0},
+ {0x110020, 0x0},
+ {0x110080, 0x0},
+ {0x110081, 0x0},
+ {0x1100d0, 0x0},
+ {0x1100d1, 0x0},
+ {0x11008c, 0x0},
+ {0x11008d, 0x0},
+ {0x110180, 0x0},
+ {0x110181, 0x0},
+ {0x1101d0, 0x0},
+ {0x1101d1, 0x0},
+ {0x11018c, 0x0},
+ {0x11018d, 0x0},
+ {0x1100c0, 0x0},
+ {0x1100c1, 0x0},
+ {0x1101c0, 0x0},
+ {0x1101c1, 0x0},
+ {0x1102c0, 0x0},
+ {0x1102c1, 0x0},
+ {0x1103c0, 0x0},
+ {0x1103c1, 0x0},
+ {0x1104c0, 0x0},
+ {0x1104c1, 0x0},
+ {0x1105c0, 0x0},
+ {0x1105c1, 0x0},
+ {0x1106c0, 0x0},
+ {0x1106c1, 0x0},
+ {0x1107c0, 0x0},
+ {0x1107c1, 0x0},
+ {0x1108c0, 0x0},
+ {0x1108c1, 0x0},
+ {0x1100ae, 0x0},
+ {0x1100af, 0x0},
+ {0x111020, 0x0},
+ {0x111080, 0x0},
+ {0x111081, 0x0},
+ {0x1110d0, 0x0},
+ {0x1110d1, 0x0},
+ {0x11108c, 0x0},
+ {0x11108d, 0x0},
+ {0x111180, 0x0},
+ {0x111181, 0x0},
+ {0x1111d0, 0x0},
+ {0x1111d1, 0x0},
+ {0x11118c, 0x0},
+ {0x11118d, 0x0},
+ {0x1110c0, 0x0},
+ {0x1110c1, 0x0},
+ {0x1111c0, 0x0},
+ {0x1111c1, 0x0},
+ {0x1112c0, 0x0},
+ {0x1112c1, 0x0},
+ {0x1113c0, 0x0},
+ {0x1113c1, 0x0},
+ {0x1114c0, 0x0},
+ {0x1114c1, 0x0},
+ {0x1115c0, 0x0},
+ {0x1115c1, 0x0},
+ {0x1116c0, 0x0},
+ {0x1116c1, 0x0},
+ {0x1117c0, 0x0},
+ {0x1117c1, 0x0},
+ {0x1118c0, 0x0},
+ {0x1118c1, 0x0},
+ {0x1110ae, 0x0},
+ {0x1110af, 0x0},
+ {0x190201, 0x0},
+ {0x190202, 0x0},
+ {0x190203, 0x0},
+ {0x190205, 0x0},
+ {0x190206, 0x0},
+ {0x190207, 0x0},
+ {0x190208, 0x0},
+ {0x120020, 0x0},
+ {0x200080, 0x0},
+ {0x201080, 0x0},
+ {0x202080, 0x0},
+ {0x210020, 0x0},
+ {0x210080, 0x0},
+ {0x210081, 0x0},
+ {0x2100d0, 0x0},
+ {0x2100d1, 0x0},
+ {0x21008c, 0x0},
+ {0x21008d, 0x0},
+ {0x210180, 0x0},
+ {0x210181, 0x0},
+ {0x2101d0, 0x0},
+ {0x2101d1, 0x0},
+ {0x21018c, 0x0},
+ {0x21018d, 0x0},
+ {0x2100c0, 0x0},
+ {0x2100c1, 0x0},
+ {0x2101c0, 0x0},
+ {0x2101c1, 0x0},
+ {0x2102c0, 0x0},
+ {0x2102c1, 0x0},
+ {0x2103c0, 0x0},
+ {0x2103c1, 0x0},
+ {0x2104c0, 0x0},
+ {0x2104c1, 0x0},
+ {0x2105c0, 0x0},
+ {0x2105c1, 0x0},
+ {0x2106c0, 0x0},
+ {0x2106c1, 0x0},
+ {0x2107c0, 0x0},
+ {0x2107c1, 0x0},
+ {0x2108c0, 0x0},
+ {0x2108c1, 0x0},
+ {0x2100ae, 0x0},
+ {0x2100af, 0x0},
+ {0x211020, 0x0},
+ {0x211080, 0x0},
+ {0x211081, 0x0},
+ {0x2110d0, 0x0},
+ {0x2110d1, 0x0},
+ {0x21108c, 0x0},
+ {0x21108d, 0x0},
+ {0x211180, 0x0},
+ {0x211181, 0x0},
+ {0x2111d0, 0x0},
+ {0x2111d1, 0x0},
+ {0x21118c, 0x0},
+ {0x21118d, 0x0},
+ {0x2110c0, 0x0},
+ {0x2110c1, 0x0},
+ {0x2111c0, 0x0},
+ {0x2111c1, 0x0},
+ {0x2112c0, 0x0},
+ {0x2112c1, 0x0},
+ {0x2113c0, 0x0},
+ {0x2113c1, 0x0},
+ {0x2114c0, 0x0},
+ {0x2114c1, 0x0},
+ {0x2115c0, 0x0},
+ {0x2115c1, 0x0},
+ {0x2116c0, 0x0},
+ {0x2116c1, 0x0},
+ {0x2117c0, 0x0},
+ {0x2117c1, 0x0},
+ {0x2118c0, 0x0},
+ {0x2118c1, 0x0},
+ {0x2110ae, 0x0},
+ {0x2110af, 0x0},
+ {0x290201, 0x0},
+ {0x290202, 0x0},
+ {0x290203, 0x0},
+ {0x290205, 0x0},
+ {0x290206, 0x0},
+ {0x290207, 0x0},
+ {0x290208, 0x0},
+ {0x220020, 0x0},
+ {0x20077, 0x0},
+ {0x20072, 0x0},
+ {0x20073, 0x0},
+ {0x400c0, 0x0},
+ {0x10040, 0x0},
+ {0x10140, 0x0},
+ {0x10240, 0x0},
+ {0x10340, 0x0},
+ {0x10440, 0x0},
+ {0x10540, 0x0},
+ {0x10640, 0x0},
+ {0x10740, 0x0},
+ {0x10840, 0x0},
+ {0x11040, 0x0},
+ {0x11140, 0x0},
+ {0x11240, 0x0},
+ {0x11340, 0x0},
+ {0x11440, 0x0},
+ {0x11540, 0x0},
+ {0x11640, 0x0},
+ {0x11740, 0x0},
+ {0x11840, 0x0},
+};
+
+/* P0 message block parameter for training firmware */
+static struct dram_cfg_param ddr_fsp0_cfg[] = {
+ {0xd0000, 0x0},
+ {0x54003, 0xe94},
+ {0x54004, 0x4},
+ {0x54006, 0x15},
+ {0x54008, 0x131f},
+ {0x54009, 0xc8},
+ {0x5400b, 0x4},
+ {0x5400d, 0x100},
+ {0x5400f, 0x100},
+ {0x54012, 0x110},
+ {0x54019, 0x36e4},
+ {0x5401a, 0x32},
+ {0x5401b, 0x1146},
+ {0x5401c, 0x1108},
+ {0x5401e, 0x4},
+ {0x5401f, 0x36e4},
+ {0x54020, 0x32},
+ {0x54021, 0x1146},
+ {0x54022, 0x1108},
+ {0x54024, 0x4},
+ {0x54032, 0xe400},
+ {0x54033, 0x3236},
+ {0x54034, 0x4600},
+ {0x54035, 0x811},
+ {0x54036, 0x11},
+ {0x54037, 0x400},
+ {0x54038, 0xe400},
+ {0x54039, 0x3236},
+ {0x5403a, 0x4600},
+ {0x5403b, 0x811},
+ {0x5403c, 0x11},
+ {0x5403d, 0x400},
+ {0xd0000, 0x1}
+};
+
+/* P1 message block parameter for training firmware */
+static struct dram_cfg_param ddr_fsp1_cfg[] = {
+ {0xd0000, 0x0},
+ {0x54002, 0x1},
+ {0x54003, 0x74a},
+ {0x54004, 0x4},
+ {0x54006, 0x15},
+ {0x54008, 0x121f},
+ {0x54009, 0xc8},
+ {0x5400b, 0x4},
+ {0x5400d, 0x100},
+ {0x5400f, 0x100},
+ {0x54012, 0x110},
+ {0x54019, 0x1bb4},
+ {0x5401a, 0x32},
+ {0x5401b, 0x1146},
+ {0x5401c, 0x1108},
+ {0x5401e, 0x4},
+ {0x5401f, 0x1bb4},
+ {0x54020, 0x32},
+ {0x54021, 0x1146},
+ {0x54022, 0x1108},
+ {0x54024, 0x4},
+ {0x54032, 0xb400},
+ {0x54033, 0x321b},
+ {0x54034, 0x4600},
+ {0x54035, 0x811},
+ {0x54036, 0x11},
+ {0x54037, 0x400},
+ {0x54038, 0xb400},
+ {0x54039, 0x321b},
+ {0x5403a, 0x4600},
+ {0x5403b, 0x811},
+ {0x5403c, 0x11},
+ {0x5403d, 0x400},
+ {0xd0000, 0x1}
+};
+
+/* P2 message block parameter for training firmware */
+static struct dram_cfg_param ddr_fsp2_cfg[] = {
+ {0xd0000, 0x0},
+ {0x54002, 0x102},
+ {0x54003, 0x270},
+ {0x54004, 0x4},
+ {0x54006, 0x15},
+ {0x54008, 0x121f},
+ {0x54009, 0xc8},
+ {0x5400b, 0x4},
+ {0x5400d, 0x100},
+ {0x5400f, 0x100},
+ {0x54012, 0x110},
+ {0x54019, 0x994},
+ {0x5401a, 0x32},
+ {0x5401b, 0x1146},
+ {0x5401c, 0x1100},
+ {0x5401e, 0x4},
+ {0x5401f, 0x994},
+ {0x54020, 0x32},
+ {0x54021, 0x1146},
+ {0x54022, 0x1100},
+ {0x54024, 0x4},
+ {0x54032, 0x9400},
+ {0x54033, 0x3209},
+ {0x54034, 0x4600},
+ {0x54035, 0x11},
+ {0x54036, 0x11},
+ {0x54037, 0x400},
+ {0x54038, 0x9400},
+ {0x54039, 0x3209},
+ {0x5403a, 0x4600},
+ {0x5403b, 0x11},
+ {0x5403c, 0x11},
+ {0x5403d, 0x400},
+ {0xd0000, 0x1}
+};
+
+/* P0 2D message block parameter for training firmware */
+static struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
+ {0xd0000, 0x0},
+ {0x54003, 0xe94},
+ {0x54004, 0x4},
+ {0x54006, 0x15},
+ {0x54008, 0x61},
+ {0x54009, 0xc8},
+ {0x5400b, 0x4},
+ {0x5400d, 0x100},
+ {0x5400f, 0x100},
+ {0x54010, 0x2080},
+ {0x54012, 0x110},
+ {0x54019, 0x36e4},
+ {0x5401a, 0x32},
+ {0x5401b, 0x1146},
+ {0x5401c, 0x1108},
+ {0x5401e, 0x4},
+ {0x5401f, 0x36e4},
+ {0x54020, 0x32},
+ {0x54021, 0x1146},
+ {0x54022, 0x1108},
+ {0x54024, 0x4},
+ {0x54032, 0xe400},
+ {0x54033, 0x3236},
+ {0x54034, 0x4600},
+ {0x54035, 0x811},
+ {0x54036, 0x11},
+ {0x54037, 0x400},
+ {0x54038, 0xe400},
+ {0x54039, 0x3236},
+ {0x5403a, 0x4600},
+ {0x5403b, 0x811},
+ {0x5403c, 0x11},
+ {0x5403d, 0x400},
+ {0xd0000, 0x1}
+};
+
+/* DRAM PHY init engine image */
+static struct dram_cfg_param ddr_phy_pie[] = {
+ {0xd0000, 0x0},
+ {0x90000, 0x10},
+ {0x90001, 0x400},
+ {0x90002, 0x10e},
+ {0x90003, 0x0},
+ {0x90004, 0x0},
+ {0x90005, 0x8},
+ {0x90029, 0xb},
+ {0x9002a, 0x480},
+ {0x9002b, 0x109},
+ {0x9002c, 0x8},
+ {0x9002d, 0x448},
+ {0x9002e, 0x139},
+ {0x9002f, 0x8},
+ {0x90030, 0x478},
+ {0x90031, 0x109},
+ {0x90032, 0x0},
+ {0x90033, 0xe8},
+ {0x90034, 0x109},
+ {0x90035, 0x2},
+ {0x90036, 0x10},
+ {0x90037, 0x139},
+ {0x90038, 0xb},
+ {0x90039, 0x7c0},
+ {0x9003a, 0x139},
+ {0x9003b, 0x44},
+ {0x9003c, 0x633},
+ {0x9003d, 0x159},
+ {0x9003e, 0x14f},
+ {0x9003f, 0x630},
+ {0x90040, 0x159},
+ {0x90041, 0x47},
+ {0x90042, 0x633},
+ {0x90043, 0x149},
+ {0x90044, 0x4f},
+ {0x90045, 0x633},
+ {0x90046, 0x179},
+ {0x90047, 0x8},
+ {0x90048, 0xe0},
+ {0x90049, 0x109},
+ {0x9004a, 0x0},
+ {0x9004b, 0x7c8},
+ {0x9004c, 0x109},
+ {0x9004d, 0x0},
+ {0x9004e, 0x1},
+ {0x9004f, 0x8},
+ {0x90050, 0x30},
+ {0x90051, 0x65a},
+ {0x90052, 0x9},
+ {0x90053, 0x0},
+ {0x90054, 0x45a},
+ {0x90055, 0x9},
+ {0x90056, 0x0},
+ {0x90057, 0x448},
+ {0x90058, 0x109},
+ {0x90059, 0x40},
+ {0x9005a, 0x633},
+ {0x9005b, 0x179},
+ {0x9005c, 0x1},
+ {0x9005d, 0x618},
+ {0x9005e, 0x109},
+ {0x9005f, 0x40c0},
+ {0x90060, 0x633},
+ {0x90061, 0x149},
+ {0x90062, 0x8},
+ {0x90063, 0x4},
+ {0x90064, 0x48},
+ {0x90065, 0x4040},
+ {0x90066, 0x633},
+ {0x90067, 0x149},
+ {0x90068, 0x0},
+ {0x90069, 0x4},
+ {0x9006a, 0x48},
+ {0x9006b, 0x40},
+ {0x9006c, 0x633},
+ {0x9006d, 0x149},
+ {0x9006e, 0x0},
+ {0x9006f, 0x658},
+ {0x90070, 0x109},
+ {0x90071, 0x10},
+ {0x90072, 0x4},
+ {0x90073, 0x18},
+ {0x90074, 0x0},
+ {0x90075, 0x4},
+ {0x90076, 0x78},
+ {0x90077, 0x549},
+ {0x90078, 0x633},
+ {0x90079, 0x159},
+ {0x9007a, 0xd49},
+ {0x9007b, 0x633},
+ {0x9007c, 0x159},
+ {0x9007d, 0x94a},
+ {0x9007e, 0x633},
+ {0x9007f, 0x159},
+ {0x90080, 0x441},
+ {0x90081, 0x633},
+ {0x90082, 0x149},
+ {0x90083, 0x42},
+ {0x90084, 0x633},
+ {0x90085, 0x149},
+ {0x90086, 0x1},
+ {0x90087, 0x633},
+ {0x90088, 0x149},
+ {0x90089, 0x0},
+ {0x9008a, 0xe0},
+ {0x9008b, 0x109},
+ {0x9008c, 0xa},
+ {0x9008d, 0x10},
+ {0x9008e, 0x109},
+ {0x9008f, 0x9},
+ {0x90090, 0x3c0},
+ {0x90091, 0x149},
+ {0x90092, 0x9},
+ {0x90093, 0x3c0},
+ {0x90094, 0x159},
+ {0x90095, 0x18},
+ {0x90096, 0x10},
+ {0x90097, 0x109},
+ {0x90098, 0x0},
+ {0x90099, 0x3c0},
+ {0x9009a, 0x109},
+ {0x9009b, 0x18},
+ {0x9009c, 0x4},
+ {0x9009d, 0x48},
+ {0x9009e, 0x18},
+ {0x9009f, 0x4},
+ {0x900a0, 0x58},
+ {0x900a1, 0xb},
+ {0x900a2, 0x10},
+ {0x900a3, 0x109},
+ {0x900a4, 0x1},
+ {0x900a5, 0x10},
+ {0x900a6, 0x109},
+ {0x900a7, 0x5},
+ {0x900a8, 0x7c0},
+ {0x900a9, 0x109},
+ {0x40000, 0x811},
+ {0x40020, 0x880},
+ {0x40040, 0x0},
+ {0x40060, 0x0},
+ {0x40001, 0x4008},
+ {0x40021, 0x83},
+ {0x40041, 0x4f},
+ {0x40061, 0x0},
+ {0x40002, 0x4040},
+ {0x40022, 0x83},
+ {0x40042, 0x51},
+ {0x40062, 0x0},
+ {0x40003, 0x811},
+ {0x40023, 0x880},
+ {0x40043, 0x0},
+ {0x40063, 0x0},
+ {0x40004, 0x720},
+ {0x40024, 0xf},
+ {0x40044, 0x1740},
+ {0x40064, 0x0},
+ {0x40005, 0x16},
+ {0x40025, 0x83},
+ {0x40045, 0x4b},
+ {0x40065, 0x0},
+ {0x40006, 0x716},
+ {0x40026, 0xf},
+ {0x40046, 0x2001},
+ {0x40066, 0x0},
+ {0x40007, 0x716},
+ {0x40027, 0xf},
+ {0x40047, 0x2800},
+ {0x40067, 0x0},
+ {0x40008, 0x716},
+ {0x40028, 0xf},
+ {0x40048, 0xf00},
+ {0x40068, 0x0},
+ {0x40009, 0x720},
+ {0x40029, 0xf},
+ {0x40049, 0x1400},
+ {0x40069, 0x0},
+ {0x4000a, 0xe08},
+ {0x4002a, 0xc15},
+ {0x4004a, 0x0},
+ {0x4006a, 0x0},
+ {0x4000b, 0x625},
+ {0x4002b, 0x15},
+ {0x4004b, 0x0},
+ {0x4006b, 0x0},
+ {0x4000c, 0x4028},
+ {0x4002c, 0x80},
+ {0x4004c, 0x0},
+ {0x4006c, 0x0},
+ {0x4000d, 0xe08},
+ {0x4002d, 0xc1a},
+ {0x4004d, 0x0},
+ {0x4006d, 0x0},
+ {0x4000e, 0x625},
+ {0x4002e, 0x1a},
+ {0x4004e, 0x0},
+ {0x4006e, 0x0},
+ {0x4000f, 0x4040},
+ {0x4002f, 0x80},
+ {0x4004f, 0x0},
+ {0x4006f, 0x0},
+ {0x40010, 0x2604},
+ {0x40030, 0x15},
+ {0x40050, 0x0},
+ {0x40070, 0x0},
+ {0x40011, 0x708},
+ {0x40031, 0x5},
+ {0x40051, 0x0},
+ {0x40071, 0x2002},
+ {0x40012, 0x8},
+ {0x40032, 0x80},
+ {0x40052, 0x0},
+ {0x40072, 0x0},
+ {0x40013, 0x2604},
+ {0x40033, 0x1a},
+ {0x40053, 0x0},
+ {0x40073, 0x0},
+ {0x40014, 0x708},
+ {0x40034, 0xa},
+ {0x40054, 0x0},
+ {0x40074, 0x2002},
+ {0x40015, 0x4040},
+ {0x40035, 0x80},
+ {0x40055, 0x0},
+ {0x40075, 0x0},
+ {0x40016, 0x60a},
+ {0x40036, 0x15},
+ {0x40056, 0x1200},
+ {0x40076, 0x0},
+ {0x40017, 0x61a},
+ {0x40037, 0x15},
+ {0x40057, 0x1300},
+ {0x40077, 0x0},
+ {0x40018, 0x60a},
+ {0x40038, 0x1a},
+ {0x40058, 0x1200},
+ {0x40078, 0x0},
+ {0x40019, 0x642},
+ {0x40039, 0x1a},
+ {0x40059, 0x1300},
+ {0x40079, 0x0},
+ {0x4001a, 0x4808},
+ {0x4003a, 0x880},
+ {0x4005a, 0x0},
+ {0x4007a, 0x0},
+ {0x900aa, 0x0},
+ {0x900ab, 0x790},
+ {0x900ac, 0x11a},
+ {0x900ad, 0x8},
+ {0x900ae, 0x7aa},
+ {0x900af, 0x2a},
+ {0x900b0, 0x10},
+ {0x900b1, 0x7b2},
+ {0x900b2, 0x2a},
+ {0x900b3, 0x0},
+ {0x900b4, 0x7c8},
+ {0x900b5, 0x109},
+ {0x900b6, 0x10},
+ {0x900b7, 0x10},
+ {0x900b8, 0x109},
+ {0x900b9, 0x10},
+ {0x900ba, 0x2a8},
+ {0x900bb, 0x129},
+ {0x900bc, 0x8},
+ {0x900bd, 0x370},
+ {0x900be, 0x129},
+ {0x900bf, 0xa},
+ {0x900c0, 0x3c8},
+ {0x900c1, 0x1a9},
+ {0x900c2, 0xc},
+ {0x900c3, 0x408},
+ {0x900c4, 0x199},
+ {0x900c5, 0x14},
+ {0x900c6, 0x790},
+ {0x900c7, 0x11a},
+ {0x900c8, 0x8},
+ {0x900c9, 0x4},
+ {0x900ca, 0x18},
+ {0x900cb, 0xe},
+ {0x900cc, 0x408},
+ {0x900cd, 0x199},
+ {0x900ce, 0x8},
+ {0x900cf, 0x8568},
+ {0x900d0, 0x108},
+ {0x900d1, 0x18},
+ {0x900d2, 0x790},
+ {0x900d3, 0x16a},
+ {0x900d4, 0x8},
+ {0x900d5, 0x1d8},
+ {0x900d6, 0x169},
+ {0x900d7, 0x10},
+ {0x900d8, 0x8558},
+ {0x900d9, 0x168},
+ {0x900da, 0x1ff8},
+ {0x900db, 0x85a8},
+ {0x900dc, 0x1e8},
+ {0x900dd, 0x50},
+ {0x900de, 0x798},
+ {0x900df, 0x16a},
+ {0x900e0, 0x60},
+ {0x900e1, 0x7a0},
+ {0x900e2, 0x16a},
+ {0x900e3, 0x8},
+ {0x900e4, 0x8310},
+ {0x900e5, 0x168},
+ {0x900e6, 0x8},
+ {0x900e7, 0xa310},
+ {0x900e8, 0x168},
+ {0x900e9, 0xa},
+ {0x900ea, 0x408},
+ {0x900eb, 0x169},
+ {0x900ec, 0x6e},
+ {0x900ed, 0x0},
+ {0x900ee, 0x68},
+ {0x900ef, 0x0},
+ {0x900f0, 0x408},
+ {0x900f1, 0x169},
+ {0x900f2, 0x0},
+ {0x900f3, 0x8310},
+ {0x900f4, 0x168},
+ {0x900f5, 0x0},
+ {0x900f6, 0xa310},
+ {0x900f7, 0x168},
+ {0x900f8, 0x1ff8},
+ {0x900f9, 0x85a8},
+ {0x900fa, 0x1e8},
+ {0x900fb, 0x68},
+ {0x900fc, 0x798},
+ {0x900fd, 0x16a},
+ {0x900fe, 0x78},
+ {0x900ff, 0x7a0},
+ {0x90100, 0x16a},
+ {0x90101, 0x68},
+ {0x90102, 0x790},
+ {0x90103, 0x16a},
+ {0x90104, 0x8},
+ {0x90105, 0x8b10},
+ {0x90106, 0x168},
+ {0x90107, 0x8},
+ {0x90108, 0xab10},
+ {0x90109, 0x168},
+ {0x9010a, 0xa},
+ {0x9010b, 0x408},
+ {0x9010c, 0x169},
+ {0x9010d, 0x58},
+ {0x9010e, 0x0},
+ {0x9010f, 0x68},
+ {0x90110, 0x0},
+ {0x90111, 0x408},
+ {0x90112, 0x169},
+ {0x90113, 0x0},
+ {0x90114, 0x8b10},
+ {0x90115, 0x168},
+ {0x90116, 0x1},
+ {0x90117, 0xab10},
+ {0x90118, 0x168},
+ {0x90119, 0x0},
+ {0x9011a, 0x1d8},
+ {0x9011b, 0x169},
+ {0x9011c, 0x80},
+ {0x9011d, 0x790},
+ {0x9011e, 0x16a},
+ {0x9011f, 0x18},
+ {0x90120, 0x7aa},
+ {0x90121, 0x6a},
+ {0x90122, 0xa},
+ {0x90123, 0x0},
+ {0x90124, 0x1e9},
+ {0x90125, 0x8},
+ {0x90126, 0x8080},
+ {0x90127, 0x108},
+ {0x90128, 0xf},
+ {0x90129, 0x408},
+ {0x9012a, 0x169},
+ {0x9012b, 0xc},
+ {0x9012c, 0x0},
+ {0x9012d, 0x68},
+ {0x9012e, 0x9},
+ {0x9012f, 0x0},
+ {0x90130, 0x1a9},
+ {0x90131, 0x0},
+ {0x90132, 0x408},
+ {0x90133, 0x169},
+ {0x90134, 0x0},
+ {0x90135, 0x8080},
+ {0x90136, 0x108},
+ {0x90137, 0x8},
+ {0x90138, 0x7aa},
+ {0x90139, 0x6a},
+ {0x9013a, 0x0},
+ {0x9013b, 0x8568},
+ {0x9013c, 0x108},
+ {0x9013d, 0xb7},
+ {0x9013e, 0x790},
+ {0x9013f, 0x16a},
+ {0x90140, 0x1f},
+ {0x90141, 0x0},
+ {0x90142, 0x68},
+ {0x90143, 0x8},
+ {0x90144, 0x8558},
+ {0x90145, 0x168},
+ {0x90146, 0xf},
+ {0x90147, 0x408},
+ {0x90148, 0x169},
+ {0x90149, 0xd},
+ {0x9014a, 0x0},
+ {0x9014b, 0x68},
+ {0x9014c, 0x0},
+ {0x9014d, 0x408},
+ {0x9014e, 0x169},
+ {0x9014f, 0x0},
+ {0x90150, 0x8558},
+ {0x90151, 0x168},
+ {0x90152, 0x8},
+ {0x90153, 0x3c8},
+ {0x90154, 0x1a9},
+ {0x90155, 0x3},
+ {0x90156, 0x370},
+ {0x90157, 0x129},
+ {0x90158, 0x20},
+ {0x90159, 0x2aa},
+ {0x9015a, 0x9},
+ {0x9015b, 0x8},
+ {0x9015c, 0xe8},
+ {0x9015d, 0x109},
+ {0x9015e, 0x0},
+ {0x9015f, 0x8140},
+ {0x90160, 0x10c},
+ {0x90161, 0x10},
+ {0x90162, 0x8138},
+ {0x90163, 0x104},
+ {0x90164, 0x8},
+ {0x90165, 0x448},
+ {0x90166, 0x109},
+ {0x90167, 0xf},
+ {0x90168, 0x7c0},
+ {0x90169, 0x109},
+ {0x9016a, 0x0},
+ {0x9016b, 0xe8},
+ {0x9016c, 0x109},
+ {0x9016d, 0x47},
+ {0x9016e, 0x630},
+ {0x9016f, 0x109},
+ {0x90170, 0x8},
+ {0x90171, 0x618},
+ {0x90172, 0x109},
+ {0x90173, 0x8},
+ {0x90174, 0xe0},
+ {0x90175, 0x109},
+ {0x90176, 0x0},
+ {0x90177, 0x7c8},
+ {0x90178, 0x109},
+ {0x90179, 0x8},
+ {0x9017a, 0x8140},
+ {0x9017b, 0x10c},
+ {0x9017c, 0x0},
+ {0x9017d, 0x478},
+ {0x9017e, 0x109},
+ {0x9017f, 0x0},
+ {0x90180, 0x1},
+ {0x90181, 0x8},
+ {0x90182, 0x8},
+ {0x90183, 0x4},
+ {0x90184, 0x0},
+ {0x90006, 0x8},
+ {0x90007, 0x7c8},
+ {0x90008, 0x109},
+ {0x90009, 0x0},
+ {0x9000a, 0x400},
+ {0x9000b, 0x106},
+ {0xd00e7, 0x400},
+ {0x90017, 0x0},
+ {0x9001f, 0x2b},
+ {0x90026, 0x69},
+ {0x400d0, 0x0},
+ {0x400d1, 0x101},
+ {0x400d2, 0x105},
+ {0x400d3, 0x107},
+ {0x400d4, 0x10f},
+ {0x400d5, 0x202},
+ {0x400d6, 0x20a},
+ {0x400d7, 0x20b},
+ {0x2003a, 0x2},
+ {0x200be, 0x3},
+ {0x2000b, 0x41a},
+ {0x2000c, 0xe9},
+ {0x2000d, 0x91c},
+ {0x2000e, 0x2c},
+ {0x12000b, 0x20d},
+ {0x12000c, 0x74},
+ {0x12000d, 0x48e},
+ {0x12000e, 0x2c},
+ {0x22000b, 0xb0},
+ {0x22000c, 0x27},
+ {0x22000d, 0x186},
+ {0x22000e, 0x10},
+ {0x9000c, 0x0},
+ {0x9000d, 0x173},
+ {0x9000e, 0x60},
+ {0x9000f, 0x6110},
+ {0x90010, 0x2152},
+ {0x90011, 0xdfbd},
+ {0x90012, 0x2060},
+ {0x90013, 0x6152},
+ {0x20010, 0x5a},
+ {0x20011, 0x3},
+ {0x120010, 0x5a},
+ {0x120011, 0x3},
+ {0x40080, 0xe0},
+ {0x40081, 0x12},
+ {0x40082, 0xe0},
+ {0x40083, 0x12},
+ {0x40084, 0xe0},
+ {0x40085, 0x12},
+ {0x140080, 0xe0},
+ {0x140081, 0x12},
+ {0x140082, 0xe0},
+ {0x140083, 0x12},
+ {0x140084, 0xe0},
+ {0x140085, 0x12},
+ {0x240080, 0xe0},
+ {0x240081, 0x12},
+ {0x240082, 0xe0},
+ {0x240083, 0x12},
+ {0x240084, 0xe0},
+ {0x240085, 0x12},
+ {0x400fd, 0xf},
+ {0x400f1, 0xe},
+ {0x10011, 0x1},
+ {0x10012, 0x1},
+ {0x10013, 0x180},
+ {0x10018, 0x1},
+ {0x10002, 0x6209},
+ {0x100b2, 0x1},
+ {0x101b4, 0x1},
+ {0x102b4, 0x1},
+ {0x103b4, 0x1},
+ {0x104b4, 0x1},
+ {0x105b4, 0x1},
+ {0x106b4, 0x1},
+ {0x107b4, 0x1},
+ {0x108b4, 0x1},
+ {0x11011, 0x1},
+ {0x11012, 0x1},
+ {0x11013, 0x180},
+ {0x11018, 0x1},
+ {0x11002, 0x6209},
+ {0x110b2, 0x1},
+ {0x111b4, 0x1},
+ {0x112b4, 0x1},
+ {0x113b4, 0x1},
+ {0x114b4, 0x1},
+ {0x115b4, 0x1},
+ {0x116b4, 0x1},
+ {0x117b4, 0x1},
+ {0x118b4, 0x1},
+ {0x20089, 0x1},
+ {0x20088, 0x19},
+ {0xc0080, 0x0},
+ {0xd0000, 0x1},
+};
+
+static struct dram_fsp_msg ddr_dram_fsp_msg[] = {
+ {
+ /* P0 3733mts 1D */
+ .drate = 3733,
+ .fw_type = FW_1D_IMAGE,
+ .fsp_cfg = ddr_fsp0_cfg,
+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg),
+ },
+ {
+ /* P1 1866mts 1D */
+ .drate = 1866,
+ .fw_type = FW_1D_IMAGE,
+ .fsp_cfg = ddr_fsp1_cfg,
+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg),
+ },
+ {
+ /* P2 625mts 1D */
+ .drate = 625,
+ .fw_type = FW_1D_IMAGE,
+ .fsp_cfg = ddr_fsp2_cfg,
+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg),
+ },
+ {
+ /* P0 3733mts 2D */
+ .drate = 3733,
+ .fw_type = FW_2D_IMAGE,
+ .fsp_cfg = ddr_fsp0_2d_cfg,
+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg),
+ },
+};
+
+/* ddr timing config params */
+struct dram_timing_info dram_timing_1GB = {
+ .ddrc_cfg = ddr_ddrc_cfg,
+ .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg),
+ .ddrphy_cfg = ddr_ddrphy_cfg,
+ .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
+ .fsp_msg = ddr_dram_fsp_msg,
+ .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg),
+ .ddrphy_trained_csr = ddr_ddrphy_trained_csr,
+ .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
+ .ddrphy_pie = ddr_phy_pie,
+ .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
+ .fsp_table = { 3733, 1866, 625, },
+ .fsp_cfg = ddr_dram_fsp_cfg,
+ .fsp_cfg_num = ARRAY_SIZE(ddr_dram_fsp_cfg),
+};
diff --git a/board/freescale/imx93_frdm/lpddr4x_2gb_timing.c b/board/freescale/imx93_frdm/lpddr4x_2gb_timing.c
new file mode 100644
index 00000000000..cd129e12959
--- /dev/null
+++ b/board/freescale/imx93_frdm/lpddr4x_2gb_timing.c
@@ -0,0 +1,1995 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright 2025 NXP
+ *
+ * Code generated with DDR Tool v3.4.0_8.3-4e2b550a.
+ * DDR PHY FW2022.01
+ */
+
+#include <linux/kernel.h>
+#include <asm/arch/ddr.h>
+
+/* Initialize DDRC registers */
+static struct dram_cfg_param ddr_ddrc_cfg[] = {
+ {0x4e300110, 0x44100001},
+ {0x4e300000, 0x8000ff},
+ {0x4e300008, 0x0},
+ {0x4e300080, 0x80000512},
+ {0x4e300084, 0x0},
+ {0x4e300114, 0x1002},
+ {0x4e300260, 0x80},
+ {0x4e300f04, 0x80},
+ {0x4e300800, 0x43b30002},
+ {0x4e300804, 0x1f1f1f1f},
+ {0x4e301000, 0x0},
+ {0x4e301240, 0x0},
+ {0x4e301244, 0x0},
+ {0x4e301248, 0x0},
+ {0x4e30124c, 0x0},
+ {0x4e301250, 0x0},
+ {0x4e301254, 0x0},
+ {0x4e301258, 0x0},
+ {0x4e30125c, 0x0},
+};
+
+/* dram fsp cfg */
+static struct dram_fsp_cfg ddr_dram_fsp_cfg[] = {
+ {
+ {
+ {0x4e300100, 0x24AB321B},
+ {0x4e300104, 0xF8EE001B},
+ {0x4e300108, 0x2F2EE233},
+ {0x4e30010C, 0x0005E18B},
+ {0x4e300124, 0x1C760000},
+ {0x4e300160, 0x00009102},
+ {0x4e30016C, 0x35F00000},
+ {0x4e300170, 0x8B0B0608},
+ {0x4e300250, 0x00000028},
+ {0x4e300254, 0x015B015B},
+ {0x4e300258, 0x00000008},
+ {0x4e30025C, 0x00000400},
+ {0x4e300300, 0x224F2213},
+ {0x4e300304, 0x015B2213},
+ {0x4e300308, 0x0A3C0E3D},
+ },
+ {
+ {0x01, 0xE4},
+ {0x02, 0x36},
+ {0x03, 0x32},
+ {0x0b, 0x46},
+ {0x0c, 0x11},
+ {0x0e, 0x11},
+ {0x16, 0x04},
+ },
+ 0,
+ },
+ {
+ {
+ {0x4e300100, 0x12552100},
+ {0x4e300104, 0xF877000E},
+ {0x4e300108, 0x1816B4AA},
+ {0x4e30010C, 0x005101E6},
+ {0x4e300124, 0x0E3C0000},
+ {0x4e300160, 0x00009101},
+ {0x4e30016C, 0x30900000},
+ {0x4e300170, 0x8A0A0508},
+ {0x4e300250, 0x00000014},
+ {0x4e300254, 0x00AA00AA},
+ {0x4e300258, 0x00000008},
+ {0x4e30025C, 0x00000400},
+ },
+ {
+ {0x01, 0xB4},
+ {0x02, 0x1B},
+ {0x03, 0x32},
+ {0x0b, 0x46},
+ {0x0c, 0x11},
+ {0x0e, 0x11},
+ {0x16, 0x04},
+ },
+ 0,
+ },
+ {
+ {
+ {0x4e300100, 0x00061000},
+ {0x4e300104, 0xF855000A},
+ {0x4e300108, 0x6E62FA48},
+ {0x4e30010C, 0x0031010D},
+ {0x4e300124, 0x04C50000},
+ {0x4e300160, 0x00009100},
+ {0x4e30016C, 0x30000000},
+ {0x4e300170, 0x89090408},
+ {0x4e300250, 0x00000007},
+ {0x4e300254, 0x00340034},
+ {0x4e300258, 0x00000008},
+ {0x4e30025C, 0x00000400},
+ },
+ {
+ {0x01, 0x94},
+ {0x02, 0x9},
+ {0x03, 0x32},
+ {0x0b, 0x46},
+ {0x0c, 0x11},
+ {0x0e, 0x11},
+ {0x16, 0x04},
+ },
+ 1,
+ },
+};
+
+/* PHY Initialize Configuration */
+static struct dram_cfg_param ddr_ddrphy_cfg[] = {
+ {0x100a0, 0x4},
+ {0x100a1, 0x5},
+ {0x100a2, 0x6},
+ {0x100a3, 0x7},
+ {0x100a4, 0x0},
+ {0x100a5, 0x1},
+ {0x100a6, 0x2},
+ {0x100a7, 0x3},
+ {0x110a0, 0x3},
+ {0x110a1, 0x2},
+ {0x110a2, 0x0},
+ {0x110a3, 0x1},
+ {0x110a4, 0x7},
+ {0x110a5, 0x6},
+ {0x110a6, 0x4},
+ {0x110a7, 0x5},
+ {0x1005f, 0x5ff},
+ {0x1015f, 0x5ff},
+ {0x1105f, 0x5ff},
+ {0x1115f, 0x5ff},
+ {0x11005f, 0x5ff},
+ {0x11015f, 0x5ff},
+ {0x11105f, 0x5ff},
+ {0x11115f, 0x5ff},
+ {0x21005f, 0x5ff},
+ {0x21015f, 0x5ff},
+ {0x21105f, 0x5ff},
+ {0x21115f, 0x5ff},
+ {0x55, 0x1ff},
+ {0x1055, 0x1ff},
+ {0x2055, 0x1ff},
+ {0x200c5, 0x19},
+ {0x1200c5, 0xb},
+ {0x2200c5, 0x7},
+ {0x2002e, 0x2},
+ {0x12002e, 0x2},
+ {0x22002e, 0x2},
+ {0x90204, 0x0},
+ {0x190204, 0x0},
+ {0x290204, 0x0},
+ {0x20024, 0x1e3},
+ {0x2003a, 0x2},
+ {0x2007d, 0x212},
+ {0x2007c, 0x61},
+ {0x120024, 0x1e3},
+ {0x2003a, 0x2},
+ {0x12007d, 0x212},
+ {0x12007c, 0x61},
+ {0x220024, 0x1e3},
+ {0x2003a, 0x2},
+ {0x22007d, 0x212},
+ {0x22007c, 0x61},
+ {0x20056, 0x3},
+ {0x120056, 0x3},
+ {0x220056, 0x3},
+ {0x1004d, 0x600},
+ {0x1014d, 0x600},
+ {0x1104d, 0x600},
+ {0x1114d, 0x600},
+ {0x11004d, 0x600},
+ {0x11014d, 0x600},
+ {0x11104d, 0x600},
+ {0x11114d, 0x600},
+ {0x21004d, 0x600},
+ {0x21014d, 0x600},
+ {0x21104d, 0x600},
+ {0x21114d, 0x600},
+ {0x10049, 0xe00},
+ {0x10149, 0xe00},
+ {0x11049, 0xe00},
+ {0x11149, 0xe00},
+ {0x110049, 0xe00},
+ {0x110149, 0xe00},
+ {0x111049, 0xe00},
+ {0x111149, 0xe00},
+ {0x210049, 0xe00},
+ {0x210149, 0xe00},
+ {0x211049, 0xe00},
+ {0x211149, 0xe00},
+ {0x43, 0x60},
+ {0x1043, 0x60},
+ {0x2043, 0x60},
+ {0x20018, 0x1},
+ {0x20075, 0x4},
+ {0x20050, 0x0},
+ {0x2009b, 0x2},
+ {0x20008, 0x3a5},
+ {0x120008, 0x1d3},
+ {0x220008, 0x9c},
+ {0x20088, 0x9},
+ {0x200b2, 0x10c},
+ {0x10043, 0x5a1},
+ {0x10143, 0x5a1},
+ {0x11043, 0x5a1},
+ {0x11143, 0x5a1},
+ {0x1200b2, 0x10c},
+ {0x110043, 0x5a1},
+ {0x110143, 0x5a1},
+ {0x111043, 0x5a1},
+ {0x111143, 0x5a1},
+ {0x2200b2, 0x10c},
+ {0x210043, 0x5a1},
+ {0x210143, 0x5a1},
+ {0x211043, 0x5a1},
+ {0x211143, 0x5a1},
+ {0x200fa, 0x2},
+ {0x1200fa, 0x2},
+ {0x2200fa, 0x2},
+ {0x20019, 0x1},
+ {0x120019, 0x1},
+ {0x220019, 0x1},
+ {0x200f0, 0x600},
+ {0x200f1, 0x0},
+ {0x200f2, 0x4444},
+ {0x200f3, 0x8888},
+ {0x200f4, 0x5655},
+ {0x200f5, 0x0},
+ {0x200f6, 0x0},
+ {0x200f7, 0xf000},
+ {0x1004a, 0x500},
+ {0x1104a, 0x500},
+ {0x20025, 0x0},
+ {0x2002d, 0x0},
+ {0x12002d, 0x0},
+ {0x22002d, 0x0},
+ {0x2002c, 0x0},
+ {0x20021, 0x0},
+ {0x200c7, 0x21},
+ {0x1200c7, 0x21},
+ {0x200ca, 0x24},
+ {0x1200ca, 0x24},
+};
+
+/* ddr phy trained csr */
+static struct dram_cfg_param ddr_ddrphy_trained_csr[] = {
+ {0x1005f, 0x0},
+ {0x1015f, 0x0},
+ {0x1105f, 0x0},
+ {0x1115f, 0x0},
+ {0x11005f, 0x0},
+ {0x11015f, 0x0},
+ {0x11105f, 0x0},
+ {0x11115f, 0x0},
+ {0x21005f, 0x0},
+ {0x21015f, 0x0},
+ {0x21105f, 0x0},
+ {0x21115f, 0x0},
+ {0x55, 0x0},
+ {0x1055, 0x0},
+ {0x2055, 0x0},
+ {0x200c5, 0x0},
+ {0x1200c5, 0x0},
+ {0x2200c5, 0x0},
+ {0x2002e, 0x0},
+ {0x12002e, 0x0},
+ {0x22002e, 0x0},
+ {0x90204, 0x0},
+ {0x190204, 0x0},
+ {0x290204, 0x0},
+ {0x20024, 0x0},
+ {0x2003a, 0x0},
+ {0x2007d, 0x0},
+ {0x2007c, 0x0},
+ {0x120024, 0x0},
+ {0x12007d, 0x0},
+ {0x12007c, 0x0},
+ {0x220024, 0x0},
+ {0x22007d, 0x0},
+ {0x22007c, 0x0},
+ {0x20056, 0x0},
+ {0x120056, 0x0},
+ {0x220056, 0x0},
+ {0x1004d, 0x0},
+ {0x1014d, 0x0},
+ {0x1104d, 0x0},
+ {0x1114d, 0x0},
+ {0x11004d, 0x0},
+ {0x11014d, 0x0},
+ {0x11104d, 0x0},
+ {0x11114d, 0x0},
+ {0x21004d, 0x0},
+ {0x21014d, 0x0},
+ {0x21104d, 0x0},
+ {0x21114d, 0x0},
+ {0x10049, 0x0},
+ {0x10149, 0x0},
+ {0x11049, 0x0},
+ {0x11149, 0x0},
+ {0x110049, 0x0},
+ {0x110149, 0x0},
+ {0x111049, 0x0},
+ {0x111149, 0x0},
+ {0x210049, 0x0},
+ {0x210149, 0x0},
+ {0x211049, 0x0},
+ {0x211149, 0x0},
+ {0x43, 0x0},
+ {0x1043, 0x0},
+ {0x2043, 0x0},
+ {0x20018, 0x0},
+ {0x20075, 0x0},
+ {0x20050, 0x0},
+ {0x2009b, 0x0},
+ {0x20008, 0x0},
+ {0x120008, 0x0},
+ {0x220008, 0x0},
+ {0x20088, 0x0},
+ {0x200b2, 0x0},
+ {0x10043, 0x0},
+ {0x10143, 0x0},
+ {0x11043, 0x0},
+ {0x11143, 0x0},
+ {0x1200b2, 0x0},
+ {0x110043, 0x0},
+ {0x110143, 0x0},
+ {0x111043, 0x0},
+ {0x111143, 0x0},
+ {0x2200b2, 0x0},
+ {0x210043, 0x0},
+ {0x210143, 0x0},
+ {0x211043, 0x0},
+ {0x211143, 0x0},
+ {0x200fa, 0x0},
+ {0x1200fa, 0x0},
+ {0x2200fa, 0x0},
+ {0x20019, 0x0},
+ {0x120019, 0x0},
+ {0x220019, 0x0},
+ {0x200f0, 0x0},
+ {0x200f1, 0x0},
+ {0x200f2, 0x0},
+ {0x200f3, 0x0},
+ {0x200f4, 0x0},
+ {0x200f5, 0x0},
+ {0x200f6, 0x0},
+ {0x200f7, 0x0},
+ {0x1004a, 0x0},
+ {0x1104a, 0x0},
+ {0x20025, 0x0},
+ {0x2002d, 0x0},
+ {0x12002d, 0x0},
+ {0x22002d, 0x0},
+ {0x2002c, 0x0},
+ {0xd0000, 0x0},
+ {0x90000, 0x0},
+ {0x90001, 0x0},
+ {0x90002, 0x0},
+ {0x90003, 0x0},
+ {0x90004, 0x0},
+ {0x90005, 0x0},
+ {0x90029, 0x0},
+ {0x9002a, 0x0},
+ {0x9002b, 0x0},
+ {0x9002c, 0x0},
+ {0x9002d, 0x0},
+ {0x9002e, 0x0},
+ {0x9002f, 0x0},
+ {0x90030, 0x0},
+ {0x90031, 0x0},
+ {0x90032, 0x0},
+ {0x90033, 0x0},
+ {0x90034, 0x0},
+ {0x90035, 0x0},
+ {0x90036, 0x0},
+ {0x90037, 0x0},
+ {0x90038, 0x0},
+ {0x90039, 0x0},
+ {0x9003a, 0x0},
+ {0x9003b, 0x0},
+ {0x9003c, 0x0},
+ {0x9003d, 0x0},
+ {0x9003e, 0x0},
+ {0x9003f, 0x0},
+ {0x90040, 0x0},
+ {0x90041, 0x0},
+ {0x90042, 0x0},
+ {0x90043, 0x0},
+ {0x90044, 0x0},
+ {0x90045, 0x0},
+ {0x90046, 0x0},
+ {0x90047, 0x0},
+ {0x90048, 0x0},
+ {0x90049, 0x0},
+ {0x9004a, 0x0},
+ {0x9004b, 0x0},
+ {0x9004c, 0x0},
+ {0x9004d, 0x0},
+ {0x9004e, 0x0},
+ {0x9004f, 0x0},
+ {0x90050, 0x0},
+ {0x90051, 0x0},
+ {0x90052, 0x0},
+ {0x90053, 0x0},
+ {0x90054, 0x0},
+ {0x90055, 0x0},
+ {0x90056, 0x0},
+ {0x90057, 0x0},
+ {0x90058, 0x0},
+ {0x90059, 0x0},
+ {0x9005a, 0x0},
+ {0x9005b, 0x0},
+ {0x9005c, 0x0},
+ {0x9005d, 0x0},
+ {0x9005e, 0x0},
+ {0x9005f, 0x0},
+ {0x90060, 0x0},
+ {0x90061, 0x0},
+ {0x90062, 0x0},
+ {0x90063, 0x0},
+ {0x90064, 0x0},
+ {0x90065, 0x0},
+ {0x90066, 0x0},
+ {0x90067, 0x0},
+ {0x90068, 0x0},
+ {0x90069, 0x0},
+ {0x9006a, 0x0},
+ {0x9006b, 0x0},
+ {0x9006c, 0x0},
+ {0x9006d, 0x0},
+ {0x9006e, 0x0},
+ {0x9006f, 0x0},
+ {0x90070, 0x0},
+ {0x90071, 0x0},
+ {0x90072, 0x0},
+ {0x90073, 0x0},
+ {0x90074, 0x0},
+ {0x90075, 0x0},
+ {0x90076, 0x0},
+ {0x90077, 0x0},
+ {0x90078, 0x0},
+ {0x90079, 0x0},
+ {0x9007a, 0x0},
+ {0x9007b, 0x0},
+ {0x9007c, 0x0},
+ {0x9007d, 0x0},
+ {0x9007e, 0x0},
+ {0x9007f, 0x0},
+ {0x90080, 0x0},
+ {0x90081, 0x0},
+ {0x90082, 0x0},
+ {0x90083, 0x0},
+ {0x90084, 0x0},
+ {0x90085, 0x0},
+ {0x90086, 0x0},
+ {0x90087, 0x0},
+ {0x90088, 0x0},
+ {0x90089, 0x0},
+ {0x9008a, 0x0},
+ {0x9008b, 0x0},
+ {0x9008c, 0x0},
+ {0x9008d, 0x0},
+ {0x9008e, 0x0},
+ {0x9008f, 0x0},
+ {0x90090, 0x0},
+ {0x90091, 0x0},
+ {0x90092, 0x0},
+ {0x90093, 0x0},
+ {0x90094, 0x0},
+ {0x90095, 0x0},
+ {0x90096, 0x0},
+ {0x90097, 0x0},
+ {0x90098, 0x0},
+ {0x90099, 0x0},
+ {0x9009a, 0x0},
+ {0x9009b, 0x0},
+ {0x9009c, 0x0},
+ {0x9009d, 0x0},
+ {0x9009e, 0x0},
+ {0x9009f, 0x0},
+ {0x900a0, 0x0},
+ {0x900a1, 0x0},
+ {0x900a2, 0x0},
+ {0x900a3, 0x0},
+ {0x900a4, 0x0},
+ {0x900a5, 0x0},
+ {0x900a6, 0x0},
+ {0x900a7, 0x0},
+ {0x900a8, 0x0},
+ {0x900a9, 0x0},
+ {0x40000, 0x0},
+ {0x40020, 0x0},
+ {0x40040, 0x0},
+ {0x40060, 0x0},
+ {0x40001, 0x0},
+ {0x40021, 0x0},
+ {0x40041, 0x0},
+ {0x40061, 0x0},
+ {0x40002, 0x0},
+ {0x40022, 0x0},
+ {0x40042, 0x0},
+ {0x40062, 0x0},
+ {0x40003, 0x0},
+ {0x40023, 0x0},
+ {0x40043, 0x0},
+ {0x40063, 0x0},
+ {0x40004, 0x0},
+ {0x40024, 0x0},
+ {0x40044, 0x0},
+ {0x40064, 0x0},
+ {0x40005, 0x0},
+ {0x40025, 0x0},
+ {0x40045, 0x0},
+ {0x40065, 0x0},
+ {0x40006, 0x0},
+ {0x40026, 0x0},
+ {0x40046, 0x0},
+ {0x40066, 0x0},
+ {0x40007, 0x0},
+ {0x40027, 0x0},
+ {0x40047, 0x0},
+ {0x40067, 0x0},
+ {0x40008, 0x0},
+ {0x40028, 0x0},
+ {0x40048, 0x0},
+ {0x40068, 0x0},
+ {0x40009, 0x0},
+ {0x40029, 0x0},
+ {0x40049, 0x0},
+ {0x40069, 0x0},
+ {0x4000a, 0x0},
+ {0x4002a, 0x0},
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+ {0x21008d, 0x0},
+ {0x210180, 0x0},
+ {0x210181, 0x0},
+ {0x2101d0, 0x0},
+ {0x2101d1, 0x0},
+ {0x21018c, 0x0},
+ {0x21018d, 0x0},
+ {0x2100c0, 0x0},
+ {0x2100c1, 0x0},
+ {0x2101c0, 0x0},
+ {0x2101c1, 0x0},
+ {0x2102c0, 0x0},
+ {0x2102c1, 0x0},
+ {0x2103c0, 0x0},
+ {0x2103c1, 0x0},
+ {0x2104c0, 0x0},
+ {0x2104c1, 0x0},
+ {0x2105c0, 0x0},
+ {0x2105c1, 0x0},
+ {0x2106c0, 0x0},
+ {0x2106c1, 0x0},
+ {0x2107c0, 0x0},
+ {0x2107c1, 0x0},
+ {0x2108c0, 0x0},
+ {0x2108c1, 0x0},
+ {0x2100ae, 0x0},
+ {0x2100af, 0x0},
+ {0x211020, 0x0},
+ {0x211080, 0x0},
+ {0x211081, 0x0},
+ {0x2110d0, 0x0},
+ {0x2110d1, 0x0},
+ {0x21108c, 0x0},
+ {0x21108d, 0x0},
+ {0x211180, 0x0},
+ {0x211181, 0x0},
+ {0x2111d0, 0x0},
+ {0x2111d1, 0x0},
+ {0x21118c, 0x0},
+ {0x21118d, 0x0},
+ {0x2110c0, 0x0},
+ {0x2110c1, 0x0},
+ {0x2111c0, 0x0},
+ {0x2111c1, 0x0},
+ {0x2112c0, 0x0},
+ {0x2112c1, 0x0},
+ {0x2113c0, 0x0},
+ {0x2113c1, 0x0},
+ {0x2114c0, 0x0},
+ {0x2114c1, 0x0},
+ {0x2115c0, 0x0},
+ {0x2115c1, 0x0},
+ {0x2116c0, 0x0},
+ {0x2116c1, 0x0},
+ {0x2117c0, 0x0},
+ {0x2117c1, 0x0},
+ {0x2118c0, 0x0},
+ {0x2118c1, 0x0},
+ {0x2110ae, 0x0},
+ {0x2110af, 0x0},
+ {0x290201, 0x0},
+ {0x290202, 0x0},
+ {0x290203, 0x0},
+ {0x290205, 0x0},
+ {0x290206, 0x0},
+ {0x290207, 0x0},
+ {0x290208, 0x0},
+ {0x220020, 0x0},
+ {0x20077, 0x0},
+ {0x20072, 0x0},
+ {0x20073, 0x0},
+ {0x400c0, 0x0},
+ {0x10040, 0x0},
+ {0x10140, 0x0},
+ {0x10240, 0x0},
+ {0x10340, 0x0},
+ {0x10440, 0x0},
+ {0x10540, 0x0},
+ {0x10640, 0x0},
+ {0x10740, 0x0},
+ {0x10840, 0x0},
+ {0x11040, 0x0},
+ {0x11140, 0x0},
+ {0x11240, 0x0},
+ {0x11340, 0x0},
+ {0x11440, 0x0},
+ {0x11540, 0x0},
+ {0x11640, 0x0},
+ {0x11740, 0x0},
+ {0x11840, 0x0},
+};
+
+/* P0 message block parameter for training firmware */
+static struct dram_cfg_param ddr_fsp0_cfg[] = {
+ {0xd0000, 0x0},
+ {0x54003, 0xe94},
+ {0x54004, 0x4},
+ {0x54006, 0x15},
+ {0x54008, 0x131f},
+ {0x54009, 0xc8},
+ {0x5400b, 0x4},
+ {0x5400d, 0x100},
+ {0x5400f, 0x100},
+ {0x54012, 0x110},
+ {0x54019, 0x36e4},
+ {0x5401a, 0x32},
+ {0x5401b, 0x1146},
+ {0x5401c, 0x1108},
+ {0x5401e, 0x4},
+ {0x5401f, 0x36e4},
+ {0x54020, 0x32},
+ {0x54021, 0x1146},
+ {0x54022, 0x1108},
+ {0x54024, 0x4},
+ {0x54032, 0xe400},
+ {0x54033, 0x3236},
+ {0x54034, 0x4600},
+ {0x54035, 0x811},
+ {0x54036, 0x11},
+ {0x54037, 0x400},
+ {0x54038, 0xe400},
+ {0x54039, 0x3236},
+ {0x5403a, 0x4600},
+ {0x5403b, 0x811},
+ {0x5403c, 0x11},
+ {0x5403d, 0x400},
+ {0xd0000, 0x1}
+};
+
+/* P1 message block parameter for training firmware */
+static struct dram_cfg_param ddr_fsp1_cfg[] = {
+ {0xd0000, 0x0},
+ {0x54002, 0x1},
+ {0x54003, 0x74a},
+ {0x54004, 0x4},
+ {0x54006, 0x15},
+ {0x54008, 0x121f},
+ {0x54009, 0xc8},
+ {0x5400b, 0x4},
+ {0x5400d, 0x100},
+ {0x5400f, 0x100},
+ {0x54012, 0x110},
+ {0x54019, 0x1bb4},
+ {0x5401a, 0x32},
+ {0x5401b, 0x1146},
+ {0x5401c, 0x1108},
+ {0x5401e, 0x4},
+ {0x5401f, 0x1bb4},
+ {0x54020, 0x32},
+ {0x54021, 0x1146},
+ {0x54022, 0x1108},
+ {0x54024, 0x4},
+ {0x54032, 0xb400},
+ {0x54033, 0x321b},
+ {0x54034, 0x4600},
+ {0x54035, 0x811},
+ {0x54036, 0x11},
+ {0x54037, 0x400},
+ {0x54038, 0xb400},
+ {0x54039, 0x321b},
+ {0x5403a, 0x4600},
+ {0x5403b, 0x811},
+ {0x5403c, 0x11},
+ {0x5403d, 0x400},
+ {0xd0000, 0x1}
+};
+
+/* P2 message block parameter for training firmware */
+static struct dram_cfg_param ddr_fsp2_cfg[] = {
+ {0xd0000, 0x0},
+ {0x54002, 0x102},
+ {0x54003, 0x270},
+ {0x54004, 0x4},
+ {0x54006, 0x15},
+ {0x54008, 0x121f},
+ {0x54009, 0xc8},
+ {0x5400b, 0x4},
+ {0x5400d, 0x100},
+ {0x5400f, 0x100},
+ {0x54012, 0x110},
+ {0x54019, 0x994},
+ {0x5401a, 0x32},
+ {0x5401b, 0x1146},
+ {0x5401c, 0x1100},
+ {0x5401e, 0x4},
+ {0x5401f, 0x994},
+ {0x54020, 0x32},
+ {0x54021, 0x1146},
+ {0x54022, 0x1100},
+ {0x54024, 0x4},
+ {0x54032, 0x9400},
+ {0x54033, 0x3209},
+ {0x54034, 0x4600},
+ {0x54035, 0x11},
+ {0x54036, 0x11},
+ {0x54037, 0x400},
+ {0x54038, 0x9400},
+ {0x54039, 0x3209},
+ {0x5403a, 0x4600},
+ {0x5403b, 0x11},
+ {0x5403c, 0x11},
+ {0x5403d, 0x400},
+ {0xd0000, 0x1}
+};
+
+/* P0 2D message block parameter for training firmware */
+static struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
+ {0xd0000, 0x0},
+ {0x54003, 0xe94},
+ {0x54004, 0x4},
+ {0x54006, 0x15},
+ {0x54008, 0x61},
+ {0x54009, 0xc8},
+ {0x5400b, 0x4},
+ {0x5400d, 0x100},
+ {0x5400f, 0x100},
+ {0x54010, 0x2080},
+ {0x54012, 0x110},
+ {0x54019, 0x36e4},
+ {0x5401a, 0x32},
+ {0x5401b, 0x1146},
+ {0x5401c, 0x1108},
+ {0x5401e, 0x4},
+ {0x5401f, 0x36e4},
+ {0x54020, 0x32},
+ {0x54021, 0x1146},
+ {0x54022, 0x1108},
+ {0x54024, 0x4},
+ {0x54032, 0xe400},
+ {0x54033, 0x3236},
+ {0x54034, 0x4600},
+ {0x54035, 0x811},
+ {0x54036, 0x11},
+ {0x54037, 0x400},
+ {0x54038, 0xe400},
+ {0x54039, 0x3236},
+ {0x5403a, 0x4600},
+ {0x5403b, 0x811},
+ {0x5403c, 0x11},
+ {0x5403d, 0x400},
+ {0xd0000, 0x1}
+};
+
+/* DRAM PHY init engine image */
+static struct dram_cfg_param ddr_phy_pie[] = {
+ {0xd0000, 0x0},
+ {0x90000, 0x10},
+ {0x90001, 0x400},
+ {0x90002, 0x10e},
+ {0x90003, 0x0},
+ {0x90004, 0x0},
+ {0x90005, 0x8},
+ {0x90029, 0xb},
+ {0x9002a, 0x480},
+ {0x9002b, 0x109},
+ {0x9002c, 0x8},
+ {0x9002d, 0x448},
+ {0x9002e, 0x139},
+ {0x9002f, 0x8},
+ {0x90030, 0x478},
+ {0x90031, 0x109},
+ {0x90032, 0x0},
+ {0x90033, 0xe8},
+ {0x90034, 0x109},
+ {0x90035, 0x2},
+ {0x90036, 0x10},
+ {0x90037, 0x139},
+ {0x90038, 0xb},
+ {0x90039, 0x7c0},
+ {0x9003a, 0x139},
+ {0x9003b, 0x44},
+ {0x9003c, 0x633},
+ {0x9003d, 0x159},
+ {0x9003e, 0x14f},
+ {0x9003f, 0x630},
+ {0x90040, 0x159},
+ {0x90041, 0x47},
+ {0x90042, 0x633},
+ {0x90043, 0x149},
+ {0x90044, 0x4f},
+ {0x90045, 0x633},
+ {0x90046, 0x179},
+ {0x90047, 0x8},
+ {0x90048, 0xe0},
+ {0x90049, 0x109},
+ {0x9004a, 0x0},
+ {0x9004b, 0x7c8},
+ {0x9004c, 0x109},
+ {0x9004d, 0x0},
+ {0x9004e, 0x1},
+ {0x9004f, 0x8},
+ {0x90050, 0x30},
+ {0x90051, 0x65a},
+ {0x90052, 0x9},
+ {0x90053, 0x0},
+ {0x90054, 0x45a},
+ {0x90055, 0x9},
+ {0x90056, 0x0},
+ {0x90057, 0x448},
+ {0x90058, 0x109},
+ {0x90059, 0x40},
+ {0x9005a, 0x633},
+ {0x9005b, 0x179},
+ {0x9005c, 0x1},
+ {0x9005d, 0x618},
+ {0x9005e, 0x109},
+ {0x9005f, 0x40c0},
+ {0x90060, 0x633},
+ {0x90061, 0x149},
+ {0x90062, 0x8},
+ {0x90063, 0x4},
+ {0x90064, 0x48},
+ {0x90065, 0x4040},
+ {0x90066, 0x633},
+ {0x90067, 0x149},
+ {0x90068, 0x0},
+ {0x90069, 0x4},
+ {0x9006a, 0x48},
+ {0x9006b, 0x40},
+ {0x9006c, 0x633},
+ {0x9006d, 0x149},
+ {0x9006e, 0x0},
+ {0x9006f, 0x658},
+ {0x90070, 0x109},
+ {0x90071, 0x10},
+ {0x90072, 0x4},
+ {0x90073, 0x18},
+ {0x90074, 0x0},
+ {0x90075, 0x4},
+ {0x90076, 0x78},
+ {0x90077, 0x549},
+ {0x90078, 0x633},
+ {0x90079, 0x159},
+ {0x9007a, 0xd49},
+ {0x9007b, 0x633},
+ {0x9007c, 0x159},
+ {0x9007d, 0x94a},
+ {0x9007e, 0x633},
+ {0x9007f, 0x159},
+ {0x90080, 0x441},
+ {0x90081, 0x633},
+ {0x90082, 0x149},
+ {0x90083, 0x42},
+ {0x90084, 0x633},
+ {0x90085, 0x149},
+ {0x90086, 0x1},
+ {0x90087, 0x633},
+ {0x90088, 0x149},
+ {0x90089, 0x0},
+ {0x9008a, 0xe0},
+ {0x9008b, 0x109},
+ {0x9008c, 0xa},
+ {0x9008d, 0x10},
+ {0x9008e, 0x109},
+ {0x9008f, 0x9},
+ {0x90090, 0x3c0},
+ {0x90091, 0x149},
+ {0x90092, 0x9},
+ {0x90093, 0x3c0},
+ {0x90094, 0x159},
+ {0x90095, 0x18},
+ {0x90096, 0x10},
+ {0x90097, 0x109},
+ {0x90098, 0x0},
+ {0x90099, 0x3c0},
+ {0x9009a, 0x109},
+ {0x9009b, 0x18},
+ {0x9009c, 0x4},
+ {0x9009d, 0x48},
+ {0x9009e, 0x18},
+ {0x9009f, 0x4},
+ {0x900a0, 0x58},
+ {0x900a1, 0xb},
+ {0x900a2, 0x10},
+ {0x900a3, 0x109},
+ {0x900a4, 0x1},
+ {0x900a5, 0x10},
+ {0x900a6, 0x109},
+ {0x900a7, 0x5},
+ {0x900a8, 0x7c0},
+ {0x900a9, 0x109},
+ {0x40000, 0x811},
+ {0x40020, 0x880},
+ {0x40040, 0x0},
+ {0x40060, 0x0},
+ {0x40001, 0x4008},
+ {0x40021, 0x83},
+ {0x40041, 0x4f},
+ {0x40061, 0x0},
+ {0x40002, 0x4040},
+ {0x40022, 0x83},
+ {0x40042, 0x51},
+ {0x40062, 0x0},
+ {0x40003, 0x811},
+ {0x40023, 0x880},
+ {0x40043, 0x0},
+ {0x40063, 0x0},
+ {0x40004, 0x720},
+ {0x40024, 0xf},
+ {0x40044, 0x1740},
+ {0x40064, 0x0},
+ {0x40005, 0x16},
+ {0x40025, 0x83},
+ {0x40045, 0x4b},
+ {0x40065, 0x0},
+ {0x40006, 0x716},
+ {0x40026, 0xf},
+ {0x40046, 0x2001},
+ {0x40066, 0x0},
+ {0x40007, 0x716},
+ {0x40027, 0xf},
+ {0x40047, 0x2800},
+ {0x40067, 0x0},
+ {0x40008, 0x716},
+ {0x40028, 0xf},
+ {0x40048, 0xf00},
+ {0x40068, 0x0},
+ {0x40009, 0x720},
+ {0x40029, 0xf},
+ {0x40049, 0x1400},
+ {0x40069, 0x0},
+ {0x4000a, 0xe08},
+ {0x4002a, 0xc15},
+ {0x4004a, 0x0},
+ {0x4006a, 0x0},
+ {0x4000b, 0x625},
+ {0x4002b, 0x15},
+ {0x4004b, 0x0},
+ {0x4006b, 0x0},
+ {0x4000c, 0x4028},
+ {0x4002c, 0x80},
+ {0x4004c, 0x0},
+ {0x4006c, 0x0},
+ {0x4000d, 0xe08},
+ {0x4002d, 0xc1a},
+ {0x4004d, 0x0},
+ {0x4006d, 0x0},
+ {0x4000e, 0x625},
+ {0x4002e, 0x1a},
+ {0x4004e, 0x0},
+ {0x4006e, 0x0},
+ {0x4000f, 0x4040},
+ {0x4002f, 0x80},
+ {0x4004f, 0x0},
+ {0x4006f, 0x0},
+ {0x40010, 0x2604},
+ {0x40030, 0x15},
+ {0x40050, 0x0},
+ {0x40070, 0x0},
+ {0x40011, 0x708},
+ {0x40031, 0x5},
+ {0x40051, 0x0},
+ {0x40071, 0x2002},
+ {0x40012, 0x8},
+ {0x40032, 0x80},
+ {0x40052, 0x0},
+ {0x40072, 0x0},
+ {0x40013, 0x2604},
+ {0x40033, 0x1a},
+ {0x40053, 0x0},
+ {0x40073, 0x0},
+ {0x40014, 0x708},
+ {0x40034, 0xa},
+ {0x40054, 0x0},
+ {0x40074, 0x2002},
+ {0x40015, 0x4040},
+ {0x40035, 0x80},
+ {0x40055, 0x0},
+ {0x40075, 0x0},
+ {0x40016, 0x60a},
+ {0x40036, 0x15},
+ {0x40056, 0x1200},
+ {0x40076, 0x0},
+ {0x40017, 0x61a},
+ {0x40037, 0x15},
+ {0x40057, 0x1300},
+ {0x40077, 0x0},
+ {0x40018, 0x60a},
+ {0x40038, 0x1a},
+ {0x40058, 0x1200},
+ {0x40078, 0x0},
+ {0x40019, 0x642},
+ {0x40039, 0x1a},
+ {0x40059, 0x1300},
+ {0x40079, 0x0},
+ {0x4001a, 0x4808},
+ {0x4003a, 0x880},
+ {0x4005a, 0x0},
+ {0x4007a, 0x0},
+ {0x900aa, 0x0},
+ {0x900ab, 0x790},
+ {0x900ac, 0x11a},
+ {0x900ad, 0x8},
+ {0x900ae, 0x7aa},
+ {0x900af, 0x2a},
+ {0x900b0, 0x10},
+ {0x900b1, 0x7b2},
+ {0x900b2, 0x2a},
+ {0x900b3, 0x0},
+ {0x900b4, 0x7c8},
+ {0x900b5, 0x109},
+ {0x900b6, 0x10},
+ {0x900b7, 0x10},
+ {0x900b8, 0x109},
+ {0x900b9, 0x10},
+ {0x900ba, 0x2a8},
+ {0x900bb, 0x129},
+ {0x900bc, 0x8},
+ {0x900bd, 0x370},
+ {0x900be, 0x129},
+ {0x900bf, 0xa},
+ {0x900c0, 0x3c8},
+ {0x900c1, 0x1a9},
+ {0x900c2, 0xc},
+ {0x900c3, 0x408},
+ {0x900c4, 0x199},
+ {0x900c5, 0x14},
+ {0x900c6, 0x790},
+ {0x900c7, 0x11a},
+ {0x900c8, 0x8},
+ {0x900c9, 0x4},
+ {0x900ca, 0x18},
+ {0x900cb, 0xe},
+ {0x900cc, 0x408},
+ {0x900cd, 0x199},
+ {0x900ce, 0x8},
+ {0x900cf, 0x8568},
+ {0x900d0, 0x108},
+ {0x900d1, 0x18},
+ {0x900d2, 0x790},
+ {0x900d3, 0x16a},
+ {0x900d4, 0x8},
+ {0x900d5, 0x1d8},
+ {0x900d6, 0x169},
+ {0x900d7, 0x10},
+ {0x900d8, 0x8558},
+ {0x900d9, 0x168},
+ {0x900da, 0x1ff8},
+ {0x900db, 0x85a8},
+ {0x900dc, 0x1e8},
+ {0x900dd, 0x50},
+ {0x900de, 0x798},
+ {0x900df, 0x16a},
+ {0x900e0, 0x60},
+ {0x900e1, 0x7a0},
+ {0x900e2, 0x16a},
+ {0x900e3, 0x8},
+ {0x900e4, 0x8310},
+ {0x900e5, 0x168},
+ {0x900e6, 0x8},
+ {0x900e7, 0xa310},
+ {0x900e8, 0x168},
+ {0x900e9, 0xa},
+ {0x900ea, 0x408},
+ {0x900eb, 0x169},
+ {0x900ec, 0x6e},
+ {0x900ed, 0x0},
+ {0x900ee, 0x68},
+ {0x900ef, 0x0},
+ {0x900f0, 0x408},
+ {0x900f1, 0x169},
+ {0x900f2, 0x0},
+ {0x900f3, 0x8310},
+ {0x900f4, 0x168},
+ {0x900f5, 0x0},
+ {0x900f6, 0xa310},
+ {0x900f7, 0x168},
+ {0x900f8, 0x1ff8},
+ {0x900f9, 0x85a8},
+ {0x900fa, 0x1e8},
+ {0x900fb, 0x68},
+ {0x900fc, 0x798},
+ {0x900fd, 0x16a},
+ {0x900fe, 0x78},
+ {0x900ff, 0x7a0},
+ {0x90100, 0x16a},
+ {0x90101, 0x68},
+ {0x90102, 0x790},
+ {0x90103, 0x16a},
+ {0x90104, 0x8},
+ {0x90105, 0x8b10},
+ {0x90106, 0x168},
+ {0x90107, 0x8},
+ {0x90108, 0xab10},
+ {0x90109, 0x168},
+ {0x9010a, 0xa},
+ {0x9010b, 0x408},
+ {0x9010c, 0x169},
+ {0x9010d, 0x58},
+ {0x9010e, 0x0},
+ {0x9010f, 0x68},
+ {0x90110, 0x0},
+ {0x90111, 0x408},
+ {0x90112, 0x169},
+ {0x90113, 0x0},
+ {0x90114, 0x8b10},
+ {0x90115, 0x168},
+ {0x90116, 0x1},
+ {0x90117, 0xab10},
+ {0x90118, 0x168},
+ {0x90119, 0x0},
+ {0x9011a, 0x1d8},
+ {0x9011b, 0x169},
+ {0x9011c, 0x80},
+ {0x9011d, 0x790},
+ {0x9011e, 0x16a},
+ {0x9011f, 0x18},
+ {0x90120, 0x7aa},
+ {0x90121, 0x6a},
+ {0x90122, 0xa},
+ {0x90123, 0x0},
+ {0x90124, 0x1e9},
+ {0x90125, 0x8},
+ {0x90126, 0x8080},
+ {0x90127, 0x108},
+ {0x90128, 0xf},
+ {0x90129, 0x408},
+ {0x9012a, 0x169},
+ {0x9012b, 0xc},
+ {0x9012c, 0x0},
+ {0x9012d, 0x68},
+ {0x9012e, 0x9},
+ {0x9012f, 0x0},
+ {0x90130, 0x1a9},
+ {0x90131, 0x0},
+ {0x90132, 0x408},
+ {0x90133, 0x169},
+ {0x90134, 0x0},
+ {0x90135, 0x8080},
+ {0x90136, 0x108},
+ {0x90137, 0x8},
+ {0x90138, 0x7aa},
+ {0x90139, 0x6a},
+ {0x9013a, 0x0},
+ {0x9013b, 0x8568},
+ {0x9013c, 0x108},
+ {0x9013d, 0xb7},
+ {0x9013e, 0x790},
+ {0x9013f, 0x16a},
+ {0x90140, 0x1f},
+ {0x90141, 0x0},
+ {0x90142, 0x68},
+ {0x90143, 0x8},
+ {0x90144, 0x8558},
+ {0x90145, 0x168},
+ {0x90146, 0xf},
+ {0x90147, 0x408},
+ {0x90148, 0x169},
+ {0x90149, 0xd},
+ {0x9014a, 0x0},
+ {0x9014b, 0x68},
+ {0x9014c, 0x0},
+ {0x9014d, 0x408},
+ {0x9014e, 0x169},
+ {0x9014f, 0x0},
+ {0x90150, 0x8558},
+ {0x90151, 0x168},
+ {0x90152, 0x8},
+ {0x90153, 0x3c8},
+ {0x90154, 0x1a9},
+ {0x90155, 0x3},
+ {0x90156, 0x370},
+ {0x90157, 0x129},
+ {0x90158, 0x20},
+ {0x90159, 0x2aa},
+ {0x9015a, 0x9},
+ {0x9015b, 0x8},
+ {0x9015c, 0xe8},
+ {0x9015d, 0x109},
+ {0x9015e, 0x0},
+ {0x9015f, 0x8140},
+ {0x90160, 0x10c},
+ {0x90161, 0x10},
+ {0x90162, 0x8138},
+ {0x90163, 0x104},
+ {0x90164, 0x8},
+ {0x90165, 0x448},
+ {0x90166, 0x109},
+ {0x90167, 0xf},
+ {0x90168, 0x7c0},
+ {0x90169, 0x109},
+ {0x9016a, 0x0},
+ {0x9016b, 0xe8},
+ {0x9016c, 0x109},
+ {0x9016d, 0x47},
+ {0x9016e, 0x630},
+ {0x9016f, 0x109},
+ {0x90170, 0x8},
+ {0x90171, 0x618},
+ {0x90172, 0x109},
+ {0x90173, 0x8},
+ {0x90174, 0xe0},
+ {0x90175, 0x109},
+ {0x90176, 0x0},
+ {0x90177, 0x7c8},
+ {0x90178, 0x109},
+ {0x90179, 0x8},
+ {0x9017a, 0x8140},
+ {0x9017b, 0x10c},
+ {0x9017c, 0x0},
+ {0x9017d, 0x478},
+ {0x9017e, 0x109},
+ {0x9017f, 0x0},
+ {0x90180, 0x1},
+ {0x90181, 0x8},
+ {0x90182, 0x8},
+ {0x90183, 0x4},
+ {0x90184, 0x0},
+ {0x90006, 0x8},
+ {0x90007, 0x7c8},
+ {0x90008, 0x109},
+ {0x90009, 0x0},
+ {0x9000a, 0x400},
+ {0x9000b, 0x106},
+ {0xd00e7, 0x400},
+ {0x90017, 0x0},
+ {0x9001f, 0x2b},
+ {0x90026, 0x69},
+ {0x400d0, 0x0},
+ {0x400d1, 0x101},
+ {0x400d2, 0x105},
+ {0x400d3, 0x107},
+ {0x400d4, 0x10f},
+ {0x400d5, 0x202},
+ {0x400d6, 0x20a},
+ {0x400d7, 0x20b},
+ {0x2003a, 0x2},
+ {0x200be, 0x3},
+ {0x2000b, 0x41a},
+ {0x2000c, 0xe9},
+ {0x2000d, 0x91c},
+ {0x2000e, 0x2c},
+ {0x12000b, 0x20d},
+ {0x12000c, 0x74},
+ {0x12000d, 0x48e},
+ {0x12000e, 0x2c},
+ {0x22000b, 0xb0},
+ {0x22000c, 0x27},
+ {0x22000d, 0x186},
+ {0x22000e, 0x10},
+ {0x9000c, 0x0},
+ {0x9000d, 0x173},
+ {0x9000e, 0x60},
+ {0x9000f, 0x6110},
+ {0x90010, 0x2152},
+ {0x90011, 0xdfbd},
+ {0x90012, 0x2060},
+ {0x90013, 0x6152},
+ {0x20010, 0x5a},
+ {0x20011, 0x3},
+ {0x120010, 0x5a},
+ {0x120011, 0x3},
+ {0x40080, 0xe0},
+ {0x40081, 0x12},
+ {0x40082, 0xe0},
+ {0x40083, 0x12},
+ {0x40084, 0xe0},
+ {0x40085, 0x12},
+ {0x140080, 0xe0},
+ {0x140081, 0x12},
+ {0x140082, 0xe0},
+ {0x140083, 0x12},
+ {0x140084, 0xe0},
+ {0x140085, 0x12},
+ {0x240080, 0xe0},
+ {0x240081, 0x12},
+ {0x240082, 0xe0},
+ {0x240083, 0x12},
+ {0x240084, 0xe0},
+ {0x240085, 0x12},
+ {0x400fd, 0xf},
+ {0x400f1, 0xe},
+ {0x10011, 0x1},
+ {0x10012, 0x1},
+ {0x10013, 0x180},
+ {0x10018, 0x1},
+ {0x10002, 0x6209},
+ {0x100b2, 0x1},
+ {0x101b4, 0x1},
+ {0x102b4, 0x1},
+ {0x103b4, 0x1},
+ {0x104b4, 0x1},
+ {0x105b4, 0x1},
+ {0x106b4, 0x1},
+ {0x107b4, 0x1},
+ {0x108b4, 0x1},
+ {0x11011, 0x1},
+ {0x11012, 0x1},
+ {0x11013, 0x180},
+ {0x11018, 0x1},
+ {0x11002, 0x6209},
+ {0x110b2, 0x1},
+ {0x111b4, 0x1},
+ {0x112b4, 0x1},
+ {0x113b4, 0x1},
+ {0x114b4, 0x1},
+ {0x115b4, 0x1},
+ {0x116b4, 0x1},
+ {0x117b4, 0x1},
+ {0x118b4, 0x1},
+ {0x20089, 0x1},
+ {0x20088, 0x19},
+ {0xc0080, 0x0},
+ {0xd0000, 0x1},
+};
+
+static struct dram_fsp_msg ddr_dram_fsp_msg[] = {
+ {
+ /* P0 3733mts 1D */
+ .drate = 3733,
+ .fw_type = FW_1D_IMAGE,
+ .fsp_cfg = ddr_fsp0_cfg,
+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg),
+ },
+ {
+ /* P1 1866mts 1D */
+ .drate = 1866,
+ .fw_type = FW_1D_IMAGE,
+ .fsp_cfg = ddr_fsp1_cfg,
+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg),
+ },
+ {
+ /* P2 625mts 1D */
+ .drate = 625,
+ .fw_type = FW_1D_IMAGE,
+ .fsp_cfg = ddr_fsp2_cfg,
+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg),
+ },
+ {
+ /* P0 3733mts 2D */
+ .drate = 3733,
+ .fw_type = FW_2D_IMAGE,
+ .fsp_cfg = ddr_fsp0_2d_cfg,
+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg),
+ },
+};
+
+/* ddr timing config params */
+struct dram_timing_info dram_timing_2GB = {
+ .ddrc_cfg = ddr_ddrc_cfg,
+ .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg),
+ .ddrphy_cfg = ddr_ddrphy_cfg,
+ .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
+ .fsp_msg = ddr_dram_fsp_msg,
+ .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg),
+ .ddrphy_trained_csr = ddr_ddrphy_trained_csr,
+ .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
+ .ddrphy_pie = ddr_phy_pie,
+ .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
+ .fsp_table = { 3733, 1866, 625, },
+ .fsp_cfg = ddr_dram_fsp_cfg,
+ .fsp_cfg_num = ARRAY_SIZE(ddr_dram_fsp_cfg),
+};
diff --git a/board/freescale/imx93_frdm/spl.c b/board/freescale/imx93_frdm/spl.c
new file mode 100644
index 00000000000..006c752d071
--- /dev/null
+++ b/board/freescale/imx93_frdm/spl.c
@@ -0,0 +1,195 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2025 NXP
+ */
+
+#include "lpddr4_timing.h"
+
+#include <init.h>
+#include <spl.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/ddr.h>
+#include <asm/arch/mu.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/trdc.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/mach-imx/ele_api.h>
+#include <asm/global_data.h>
+#include <asm/sections.h>
+#include <dm/device.h>
+#include <dm/device-internal.h>
+#include <dm/uclass.h>
+#include <dm/uclass-internal.h>
+#include <linux/delay.h>
+#include <power/pca9450.h>
+#include <power/pmic.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define SRC_DDRC_SW_CTRL (0x44461020)
+#define SRC_DDRPHY_SINGLE_RESET_SW_CTRL (0x44461424)
+
+static struct _drams {
+ u8 mr8;
+ struct dram_timing_info *pdram_timing;
+ char *name;
+} frdm_drams[2] = {
+ {0x10, &dram_timing_1GB, "1GB DRAM" },
+ {0x18, &dram_timing_2GB, "2GB DRAM" },
+};
+
+int spl_board_boot_device(enum boot_device boot_dev_spl)
+{
+ return BOOT_DEVICE_BOOTROM;
+}
+
+void spl_board_init(void)
+{
+ int ret;
+
+ ret = ele_start_rng();
+ if (ret)
+ printf("Fail to start RNG: %d\n", ret);
+
+ puts("Normal Boot\n");
+}
+
+void spl_dram_init(void)
+{
+ int i;
+ int ret;
+
+ for (i = 0; i < ARRAY_SIZE(frdm_drams); i++) {
+ struct dram_timing_info *ptiming = frdm_drams[i].pdram_timing;
+
+ printf("DDR: %uMTS\n", ptiming->fsp_msg[0].drate);
+ ret = ddr_init(ptiming);
+ if (ret == 0) {
+ if (lpddr4_mr_read(1, 8) == frdm_drams[i].mr8) {
+ printf("found DRAM %s matched\n", frdm_drams[i].name);
+ break;
+ }
+
+ /* Power down and Power up DDR Mixer */
+
+ /* Clear PwrOkIn via DDRMIX register */
+ setbits_32(SRC_DDRPHY_SINGLE_RESET_SW_CTRL, BIT(0));
+ /* Power off the DDRMIX */
+ setbits_32(SRC_DDRC_SW_CTRL, BIT(31));
+
+ udelay(50);
+
+ /* Power up the DDRMIX */
+ clrbits_32(SRC_DDRC_SW_CTRL, BIT(31));
+ setbits_32(SRC_DDRC_SW_CTRL, BIT(0));
+ udelay(10);
+ clrbits_32(SRC_DDRC_SW_CTRL, BIT(0));
+ udelay(10);
+ }
+ }
+}
+
+int power_init_board(void)
+{
+ struct udevice *dev;
+ int ret;
+ unsigned int val = 0, buck_val;
+
+ ret = pmic_get("pmic@25", &dev);
+ if (ret == -ENODEV) {
+ puts("No pca9450@25\n");
+ return 0;
+ }
+ if (ret != 0)
+ return ret;
+
+ /* BUCKxOUT_DVS0/1 control BUCK123 output */
+ pmic_reg_write(dev, PCA9450_BUCK123_DVS, 0x29);
+
+ /* Enable DVS control through PMIC_STBY_REQ */
+ pmic_reg_write(dev, PCA9450_BUCK1CTRL, 0x59);
+
+ ret = pmic_reg_read(dev, PCA9450_PWR_CTRL);
+ if (ret < 0)
+ return ret;
+
+ val = ret;
+
+ if (is_voltage_mode(VOLT_LOW_DRIVE)) {
+ buck_val = 0x0c; /* 0.8V for Low drive mode */
+ printf("PMIC: Low Drive Voltage Mode\n");
+ } else if (is_voltage_mode(VOLT_NOMINAL_DRIVE)) {
+ buck_val = 0x10; /* 0.85V for Nominal drive mode */
+ printf("PMIC: Nominal Voltage Mode\n");
+ } else {
+ buck_val = 0x14; /* 0.9V for Over drive mode */
+ printf("PMIC: Over Drive Voltage Mode\n");
+ }
+
+ if (val & PCA9450_REG_PWRCTRL_TOFF_DEB) {
+ pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, buck_val);
+ pmic_reg_write(dev, PCA9450_BUCK3OUT_DVS0, buck_val);
+ } else {
+ pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, buck_val + 0x4);
+ pmic_reg_write(dev, PCA9450_BUCK3OUT_DVS0, buck_val + 0x4);
+ }
+
+ /* Set standby voltage to 0.65V */
+ if (val & PCA9450_REG_PWRCTRL_TOFF_DEB)
+ pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS1, 0x0);
+ else
+ pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS1, 0x4);
+
+ /* I2C_LT_EN*/
+ pmic_reg_write(dev, 0xa, 0x3);
+ return 0;
+}
+
+void board_init_f(ulong dummy)
+{
+ int ret;
+
+ /* Clear the BSS. */
+ memset(__bss_start, 0, __bss_end - __bss_start);
+
+ timer_init();
+
+ arch_cpu_init();
+
+ board_early_init_f();
+
+ spl_early_init();
+
+ preloader_console_init();
+
+ ret = imx9_probe_mu();
+ if (ret) {
+ printf("Fail to init Sentinel API\n");
+ } else {
+ debug("SOC: 0x%x\n", gd->arch.soc_rev);
+ debug("LC: 0x%x\n", gd->arch.lifecycle);
+ }
+
+ clock_init_late();
+
+ power_init_board();
+
+ if (!is_voltage_mode(VOLT_LOW_DRIVE))
+ set_arm_clk(get_cpu_speed_grade_hz());
+
+ /* Init power of mix */
+ soc_power_init();
+
+ /* Setup TRDC for DDR access */
+ trdc_init();
+
+ /* DDR initialization */
+ spl_dram_init();
+
+ /* Put M33 into CPUWAIT for following kick */
+ ret = m33_prepare();
+ if (!ret)
+ printf("M33 prepare ok\n");
+
+ board_init_r(NULL, 0);
+}
diff --git a/board/phytec/phycore_imx8mm/phycore_imx8mm.env b/board/phytec/phycore_imx8mm/phycore_imx8mm.env
index 402d967ab7d..b3f09154328 100644
--- a/board/phytec/phycore_imx8mm/phycore_imx8mm.env
+++ b/board/phytec/phycore_imx8mm/phycore_imx8mm.env
@@ -1,65 +1,15 @@
-#include <env/phytec/rauc.env>
-
-bootcmd=
- mmc dev ${mmcdev};
- if mmc rescan; then
- if test ${doraucboot} = 1; then
- run raucinit;
- fi;
- if run loadimage; then
- run mmcboot;
- else
- run netboot;
- fi;
- fi;
-console=ttymxc2,115200
+console=ttymxc2,CONFIG_BAUDRATE
emmc_dev=2
-fdt_addr_r=0x48000000
fdtfile=CONFIG_DEFAULT_FDT_FILE
-image=Image
+fdt_addr_r=0x40480000
+fdt_overlay_addr_r=0x404a0000
+kernel_addr_r=0x40a00000
+kernel_comp_addr_r=0x43a00000
+kernel_comp_size=0x1e00000
+pxefile_addr_r=0x45800000
+ramdisk_addr_r=0x45802000
+scriptaddr=0x47600000
+script_offset_f=0x0
+script_size_f=0x2000
ip_dyn=yes
-loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}
-loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr_r} ${fdtfile}
-mmcargs=
- setenv bootargs console=${console}
- root=/dev/mmcblk${mmcdev}p${mmcroot} ${raucargs} rootwait rw
-mmcautodetect=yes
-mmcboot=
- echo Booting from mmc ...;
- run mmcargs;
- if run loadfdt; then
- if test ${dofitboot} = 1; then
- booti ${loadaddr} - ${fdt_addr_r}
- else
- echo WARN: Cannot load the DT;
- fi;
- fi;
-mmcdev=CONFIG_ENV_MMC_DEVICE_INDEX
-mmcpart=1
-mmcroot=2
-netargs=
- setenv bootargs console=${console} root=/dev/nfs ip=dhcp
- nfsroot=${serverip}:${nfsroot},v3,tcp
-netboot=
- echo Booting from net ...;
- if test ${ip_dyn} = yes; then
- setenv get_cmd dhcp;
- else
- setenv get_cmd tftp;
- fi;
- ${get_cmd} ${loadaddr} ${image};
- run netargs;
- if ${get_cmd} ${fdt_addr_r} ${fdtfile}; then
- booti ${loadaddr} - ${fdt_addr_r};
- else
- echo WARN: Cannot load the DT;
- fi;
nfsroot=/srv/nfs
-update_bootimg=
- mmc dev ${mmcdev};
- if dhcp ${loadaddr} ${update_filepath}/${update_filename}; then
- setexpr fw_sz ${filesize} / 0x200;
- mmc write ${loadaddr} ${update_offset} ${fw_sz};
- fi;
-update_filename=flash.bin
-update_offset=0x42
diff --git a/board/phytec/phycore_imx93/phycore-imx93.c b/board/phytec/phycore_imx93/phycore-imx93.c
index a55795e0603..8d2caf8bbef 100644
--- a/board/phytec/phycore_imx93/phycore-imx93.c
+++ b/board/phytec/phycore_imx93/phycore-imx93.c
@@ -6,10 +6,7 @@
* Copyright (C) 2024 PHYTEC Messtechnik GmbH
*/
-#include <asm/arch-imx9/ccm_regs.h>
#include <asm/arch/sys_proto.h>
-#include <asm/arch-imx9/imx93_pins.h>
-#include <asm/arch/clock.h>
#include <asm/global_data.h>
#include <asm/mach-imx/boot_mode.h>
#include <env.h>
diff --git a/board/phytec/phycore_imx93/spl.c b/board/phytec/phycore_imx93/spl.c
index a4d2aaac320..7b5d38d438f 100644
--- a/board/phytec/phycore_imx93/spl.c
+++ b/board/phytec/phycore_imx93/spl.c
@@ -14,9 +14,7 @@
#include <asm/mach-imx/boot_mode.h>
#include <asm/mach-imx/ele_api.h>
#include <asm/sections.h>
-#include <hang.h>
#include <init.h>
-#include <log.h>
#include <power/pmic.h>
#include <power/pca9450.h>
#include <spl.h>
@@ -25,11 +23,6 @@
DECLARE_GLOBAL_DATA_PTR;
-/*
- * Will be part of drivers/power/regulator/pca9450.c
- * when pca9451a support is added.
- */
-#define PCA9450_REG_PWRCTRL_TOFF_DEB BIT(5)
#define EEPROM_ADDR 0x50
/*
diff --git a/board/samsung/e850-96/e850-96.c b/board/samsung/e850-96/e850-96.c
index 4d4f8d14c6d..a6c264d1248 100644
--- a/board/samsung/e850-96/e850-96.c
+++ b/board/samsung/e850-96/e850-96.c
@@ -4,9 +4,57 @@
* Author: Sam Protsenko <semen.protsenko@linaro.org>
*/
+#include <efi_loader.h>
+#include <env.h>
#include <init.h>
+#include <mapmem.h>
+#include <asm/io.h>
#include "fw.h"
+/* OTP Controller base address and register offsets */
+#define EXYNOS850_OTP_BASE 0x10000000
+#define OTP_CHIPID0 0x4
+#define OTP_CHIPID1 0x8
+
+struct efi_fw_image fw_images[] = {
+ {
+ .image_type_id = E850_96_FWBL1_IMAGE_GUID,
+ .fw_name = u"E850-96-FWBL1",
+ .image_index = 1,
+ },
+ {
+ .image_type_id = E850_96_EPBL_IMAGE_GUID,
+ .fw_name = u"E850-96-EPBL",
+ .image_index = 2,
+ },
+ {
+ .image_type_id = E850_96_BL2_IMAGE_GUID,
+ .fw_name = u"E850-96-BL2",
+ .image_index = 3,
+ },
+ {
+ .image_type_id = E850_96_BOOTLOADER_IMAGE_GUID,
+ .fw_name = u"E850-96-BOOTLOADER",
+ .image_index = 4,
+ },
+ {
+ .image_type_id = E850_96_EL3_MON_IMAGE_GUID,
+ .fw_name = u"E850-96-EL3-MON",
+ .image_index = 5,
+ },
+};
+
+struct efi_capsule_update_info update_info = {
+ .dfu_string = "mmc 0="
+ "fwbl1.img raw 0x0 0x18 mmcpart 1;"
+ "epbl.img raw 0x18 0x98 mmcpart 1;"
+ "bl2.img raw 0xb0 0x200 mmcpart 1;"
+ "bootloader.img raw 0x438 0x1000 mmcpart 1;"
+ "el3_mon.img raw 0x1438 0x200 mmcpart 1",
+ .num_images = ARRAY_SIZE(fw_images),
+ .images = fw_images,
+};
+
int dram_init(void)
{
return fdtdec_setup_mem_size_base();
@@ -17,10 +65,39 @@ int dram_init_banksize(void)
return fdtdec_setup_memory_banksize();
}
+/* Read the unique SoC ID from OTP registers */
+static u64 get_chip_id(void)
+{
+ void __iomem *otp_base;
+ u64 val;
+
+ otp_base = map_sysmem(EXYNOS850_OTP_BASE, 12);
+ val = readl(otp_base + OTP_CHIPID0);
+ val |= (u64)readl(otp_base + OTP_CHIPID1) << 32UL;
+ unmap_sysmem(otp_base);
+
+ return val;
+}
+
+static void setup_serial(void)
+{
+ char serial_str[17] = { 0 };
+ u64 serial_num;
+
+ if (env_get("serial#"))
+ return;
+
+ serial_num = get_chip_id();
+ snprintf(serial_str, sizeof(serial_str), "%016llx", serial_num);
+ env_set("serial#", serial_str);
+}
+
int board_late_init(void)
{
int err;
+ setup_serial();
+
/*
* Do this in board_late_init() to make sure MMC is not probed before
* efi_init_early().
diff --git a/board/samsung/e850-96/e850-96.env b/board/samsung/e850-96/e850-96.env
index 5ac76bcef02..aed7a71046d 100644
--- a/board/samsung/e850-96/e850-96.env
+++ b/board/samsung/e850-96/e850-96.env
@@ -7,5 +7,49 @@ pxefile_addr_r=0x8c200000
ramdisk_addr_r=0x8c300000
fdtfile=CONFIG_DEFAULT_FDT_FILE
+dfu_alt_info=
+ rawemmc raw 0 0x747c000 mmcpart 1;
+ esp part 0 1;
+ rootfs part 0 2;
+ fwbl1 raw 0x0 0x18 mmcpart 1;
+ epbl raw 0x18 0x98 mmcpart 1;
+ bl2 raw 0xb0 0x200 mmcpart 1;
+ dram_train raw 0x2b0 0x20 mmcpart 1;
+ ect_test raw 0x2d0 0x64 mmcpart 1;
+ acpm_test raw 0x334 0x104 mmcpart 1;
+ bootloader raw 0x438 0x1000 mmcpart 1;
+ el3_mon raw 0x1438 0x200 mmcpart 1
+
partitions=name=esp,start=512K,size=128M,bootable,type=system;
partitions+=name=rootfs,size=-,bootable,type=linux
+
+partitions_android=name=esp,start=512K,size=128M,bootable,type=system;
+partitions_android+=name=efs,size=20M,uuid=${uuid_gpt_efs};
+partitions_android+=name=env,size=16K,uuid=${uuid_gpt_env};
+partitions_android+=name=kernel,size=30M,uuid=${uuid_gpt_kernel};
+partitions_android+=name=ramdisk,size=26M,uuid=${uuid_gpt_ramdisk};
+partitions_android+=name=dtbo_a,size=1M,uuid=${uuid_gpt_dtbo};
+partitions_android+=name=dtbo_b,size=1M,uuid=${uuid_gpt_dtbo};
+partitions_android+=name=ldfw,size=4016K,uuid=${uuid_gpt_ldfw};
+partitions_android+=name=keystorage,size=8K,uuid=${uuid_gpt_keystorage};
+partitions_android+=name=tzsw,size=1M,uuid=${uuid_gpt_tzsw};
+partitions_android+=name=harx,size=2M,uuid=${uuid_gpt_harx};
+partitions_android+=name=harx_rkp,size=2M,uuid=${uuid_gpt_harx_rkp};
+partitions_android+=name=logo,size=40M,uuid=${uuid_gpt_logo};
+partitions_android+=name=super,size=3600M,uuid=${uuid_gpt_super};
+partitions_android+=name=cache,size=300M,uuid=${uuid_gpt_cache};
+partitions_android+=name=modem,size=100M,uuid=${uuid_gpt_modem};
+partitions_android+=name=boot_a,size=100M,uuid=${uuid_gpt_boot};
+partitions_android+=name=boot_b,size=100M,uuid=${uuid_gpt_boot};
+partitions_android+=name=persist,size=30M,uuid=${uuid_gpt_persist};
+partitions_android+=name=recovery_a,size=40M,uuid=${uuid_gpt_recovery};
+partitions_android+=name=recovery_b,size=40M,uuid=${uuid_gpt_recovery};
+partitions_android+=name=misc,size=40M,uuid=${uuid_gpt_misc};
+partitions_android+=name=mnv,size=20M,uuid=${uuid_gpt_mnv};
+partitions_android+=name=frp,size=512K,uuid=${uuid_gpt_frp};
+partitions_android+=name=vbmeta_a,size=64K,uuid=${uuid_gpt_vbmeta};
+partitions_android+=name=vbmeta_b,size=64K,uuid=${uuid_gpt_vbmeta};
+partitions_android+=name=metadata,size=16M,uuid=${uuid_gpt_metadata};
+partitions_android+=name=dtb_a,size=1M,uuid=${uuid_gpt_dtb};
+partitions_android+=name=dtb_b,size=1M,uuid=${uuid_gpt_dtb};
+partitions_android+=name=userdata,size=-,uuid=${uuid_gpt_userdata}
diff --git a/board/toradex/common/tdx-cfg-block.c b/board/toradex/common/tdx-cfg-block.c
index a89c5bf2c19..869656eee7a 100644
--- a/board/toradex/common/tdx-cfg-block.c
+++ b/board/toradex/common/tdx-cfg-block.c
@@ -183,6 +183,7 @@ const struct toradex_som toradex_modules[] = {
{ AQUILA_AM69O_16GB_IT, "Aquila AM69 Octa 16GB IT", TARGET_IS_ENABLED(AQUILA_AM69_A72) },
{ AQUILA_AM69O_8GB_WB_IT, "Aquila AM69 Octa 8GB WB IT", TARGET_IS_ENABLED(AQUILA_AM69_A72) },
{ AQUILA_AM69O_8GB_IT, "Aquila AM69 Octa 8GB IT", TARGET_IS_ENABLED(AQUILA_AM69_A72) },
+ { VERDIN_IMX8MMQ_WB_IT_64G, "Verdin iMX8M Mini Quad 2GB WB IT", TARGET_IS_ENABLED(VERDIN_IMX8MM) },
};
struct pid4list {
diff --git a/board/toradex/common/tdx-cfg-block.h b/board/toradex/common/tdx-cfg-block.h
index db612811c5c..d002b969bdf 100644
--- a/board/toradex/common/tdx-cfg-block.h
+++ b/board/toradex/common/tdx-cfg-block.h
@@ -141,6 +141,7 @@ enum {
AQUILA_AM69O_16GB_IT,
AQUILA_AM69O_8GB_WB_IT,
AQUILA_AM69O_8GB_IT, /* 215 */
+ VERDIN_IMX8MMQ_WB_IT_64G,
};
enum {
diff --git a/board/toradex/verdin-imx8mm/verdin-imx8mm.c b/board/toradex/verdin-imx8mm/verdin-imx8mm.c
index 04c918a079f..b4402415845 100644
--- a/board/toradex/verdin-imx8mm/verdin-imx8mm.c
+++ b/board/toradex/verdin-imx8mm/verdin-imx8mm.c
@@ -85,7 +85,8 @@ static void select_dt_from_module_version(void)
is_wifi = (tdx_hw_tag.prodid == VERDIN_IMX8MMQ_WIFI_BT_IT) ||
(tdx_hw_tag.prodid == VERDIN_IMX8MMDL_WIFI_BT_IT) ||
(tdx_hw_tag.prodid == VERDIN_IMX8MMQ_WIFI_BT_IT_NO_CAN) ||
- (tdx_hw_tag.prodid == VERDIN_IMX8MMQ_4G_WIFI_BT_ET);
+ (tdx_hw_tag.prodid == VERDIN_IMX8MMQ_4G_WIFI_BT_ET) ||
+ (tdx_hw_tag.prodid == VERDIN_IMX8MMQ_WB_IT_64G);
}
switch (get_pcb_revision()) {
diff --git a/common/spl/spl_imx_container.c b/common/spl/spl_imx_container.c
index b3565efb225..79d021f81dc 100644
--- a/common/spl/spl_imx_container.c
+++ b/common/spl/spl_imx_container.c
@@ -31,7 +31,7 @@ static struct boot_img_t *read_auth_image(struct spl_image_info *spl_image,
ulong container_offset)
{
struct boot_img_t *images;
- ulong offset, overhead, size;
+ ulong offset, size;
void *buf, *trampoline;
if (image_index > container->num_images) {
@@ -54,7 +54,7 @@ static struct boot_img_t *read_auth_image(struct spl_image_info *spl_image,
debug("%s: container: %p offset: %lu size: %lu\n", __func__,
container, offset, size);
- buf = map_sysmem(images[image_index].dst - overhead, images[image_index].size);
+ buf = map_sysmem(images[image_index].dst, images[image_index].size);
if (IS_ENABLED(CONFIG_SPL_IMX_CONTAINER_USE_TRAMPOLINE) &&
arch_check_dst_in_secure(buf, size)) {
trampoline = arch_get_container_trampoline();
diff --git a/configs/e850-96_defconfig b/configs/e850-96_defconfig
index 4208905e77a..b4066d87460 100644
--- a/configs/e850-96_defconfig
+++ b/configs/e850-96_defconfig
@@ -3,7 +3,7 @@ CONFIG_ARCH_CPU_INIT=y
CONFIG_ARM_SMCCC=y
CONFIG_ARCH_EXYNOS=y
CONFIG_TEXT_BASE=0xf8800000
-CONFIG_SYS_MALLOC_LEN=0x81f000
+CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_SYS_MALLOC_F_LEN=0x4000
CONFIG_ARCH_EXYNOS9=y
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
@@ -15,7 +15,9 @@ CONFIG_SYS_LOAD_ADDR=0x80000000
CONFIG_ENV_OFFSET_REDUND=0x10000
# CONFIG_PSCI_RESET is not set
CONFIG_EFI_SET_TIME=y
-CONFIG_ANDROID_BOOT_IMAGE=y
+CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y
+CONFIG_EFI_CAPSULE_ON_DISK=y
+CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y
CONFIG_BOOTSTD_FULL=y
CONFIG_DEFAULT_FDT_FILE="exynos850-e850-96.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
@@ -25,6 +27,7 @@ CONFIG_CMD_BOOTEFI_SELFTEST=y
CONFIG_CMD_ABOOTIMG=y
CONFIG_CMD_NVEDIT_EFI=y
CONFIG_CMD_CLK=y
+CONFIG_CMD_DFU=y
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
CONFIG_CMD_EFIDEBUG=y
@@ -40,8 +43,18 @@ CONFIG_ENV_RELOC_GD_ENV_ADDR=y
CONFIG_ENV_MMC_EMMC_HW_PARTITION=2
CONFIG_NO_NET=y
CONFIG_CLK_EXYNOS850=y
+CONFIG_DFU_MMC=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x8a000000
+CONFIG_FASTBOOT_BUF_SIZE=0x30000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=0
+CONFIG_FASTBOOT_MMC_BOOT_SUPPORT=y
+CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_DW=y
+CONFIG_PHY=y
+CONFIG_PHY_EXYNOS_USBDRD=y
CONFIG_DM_RTC=y
CONFIG_RTC_EMULATION=y
CONFIG_SOC_SAMSUNG=y
@@ -49,3 +62,11 @@ CONFIG_EXYNOS_PMU=y
CONFIG_EXYNOS_USI=y
CONFIG_SYSRESET=y
CONFIG_SYSRESET_SYSCON=y
+CONFIG_USB=y
+CONFIG_DM_USB_GADGET=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GENERIC=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="Samsung"
+CONFIG_USB_GADGET_VENDOR_NUM=0x18d1
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0002
diff --git a/configs/imx6dl_sielaff_defconfig b/configs/imx6dl_sielaff_defconfig
index 6673e1e6915..a4271ea071a 100644
--- a/configs/imx6dl_sielaff_defconfig
+++ b/configs/imx6dl_sielaff_defconfig
@@ -14,7 +14,7 @@ CONFIG_ENV_SECT_SIZE=0x10000
CONFIG_MX6S=y
CONFIG_TARGET_MX6S_SIELAFF=y
CONFIG_DM_GPIO=y
-CONFIG_DEFAULT_DEVICE_TREE="imx6dl-sielaff"
+CONFIG_DEFAULT_DEVICE_TREE="nxp/imx/imx6dl-sielaff"
CONFIG_SPL_MMC=y
CONFIG_SPL_SERIAL=y
CONFIG_SF_DEFAULT_BUS=1
@@ -61,6 +61,7 @@ CONFIG_CMD_UBI=y
CONFIG_EFI_PARTITION=y
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_OF_CONTROL=y
+CONFIG_OF_UPSTREAM=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_ENV_RELOC_GD_ENV_ADDR=y
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
@@ -114,5 +115,6 @@ CONFIG_USB_GADGET_MANUFACTURER="FSL"
CONFIG_USB_GADGET_VENDOR_NUM=0x0525
CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
CONFIG_CI_UDC=y
+CONFIG_SDP_LOADADDR=0x17ffffc0
CONFIG_SPL_USB_SDP_SUPPORT=y
CONFIG_IMX_WATCHDOG=y
diff --git a/configs/imx8mm-phygate-tauri-l_defconfig b/configs/imx8mm-phygate-tauri-l_defconfig
index 7c8a2060b1a..7369c0a05ac 100644
--- a/configs/imx8mm-phygate-tauri-l_defconfig
+++ b/configs/imx8mm-phygate-tauri-l_defconfig
@@ -9,7 +9,6 @@ CONFIG_ENV_SIZE=0x10000
CONFIG_ENV_OFFSET=0x3C0000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="freescale/imx8mm-phygate-tauri-l"
-CONFIG_IMX8M_OPTEE_LOAD_ADDR=0x56000000
CONFIG_TARGET_PHYCORE_IMX8MM=y
CONFIG_SYS_MONITOR_LEN=524288
CONFIG_SPL_MMC=y
@@ -20,16 +19,15 @@ CONFIG_SPL_TEXT_BASE=0x7E1000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_BSS_START_ADDR=0x910000
CONFIG_SPL_BSS_MAX_SIZE=0x2000
-CONFIG_SYS_LOAD_ADDR=0x40480000
+CONFIG_SYS_LOAD_ADDR=0x47602000
CONFIG_SPL=y
CONFIG_ENV_OFFSET_REDUND=0x3E0000
CONFIG_FIT=y
CONFIG_FIT_EXTERNAL_OFFSET=0x3000
CONFIG_SPL_LOAD_FIT=y
+CONFIG_BOOTSTD_FULL=y
CONFIG_OF_SYSTEM_SETUP=y
-CONFIG_USE_BOOTCOMMAND=y
-CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadimage; then run mmcboot; else run netboot; fi; fi;"
-CONFIG_DEFAULT_FDT_FILE="oftree"
+CONFIG_DEFAULT_FDT_FILE="imx8mm-phygate-tauri-l"
CONFIG_SYS_CBSIZE=2048
CONFIG_SYS_PBSIZE=2074
CONFIG_BOARD_LATE_INIT=y
@@ -44,7 +42,6 @@ CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
CONFIG_SPL_I2C=y
CONFIG_SPL_POWER=y
CONFIG_SPL_WATCHDOG=y
-CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="u-boot=> "
# CONFIG_CMD_EXPORTENV is not set
# CONFIG_CMD_IMPORTENV is not set
@@ -60,15 +57,9 @@ CONFIG_CMD_FUSE=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_REGULATOR=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
CONFIG_OF_CONTROL=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_ENV_OVERWRITE=y
diff --git a/configs/imx93_frdm_defconfig b/configs/imx93_frdm_defconfig
new file mode 100644
index 00000000000..4f837ca9282
--- /dev/null
+++ b/configs/imx93_frdm_defconfig
@@ -0,0 +1,124 @@
+CONFIG_ARM=y
+CONFIG_ARCH_IMX9=y
+CONFIG_TEXT_BASE=0x80200000
+CONFIG_SYS_MALLOC_LEN=0x2000000
+CONFIG_SYS_MALLOC_F_LEN=0x18000
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_ENV_SIZE=0x4000
+CONFIG_ENV_OFFSET=0x700000
+CONFIG_IMX_CONFIG="arch/arm/mach-imx/imx9/imximage.cfg"
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="imx93-11x11-frdm"
+CONFIG_TARGET_IMX93_FRDM=y
+CONFIG_SYS_MONITOR_LEN=524288
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL_STACK=0x20519dd0
+CONFIG_SPL_TEXT_BASE=0x2049A000
+CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
+CONFIG_SPL_BSS_START_ADDR=0x2051a000
+CONFIG_SPL_BSS_MAX_SIZE=0x2000
+CONFIG_SYS_LOAD_ADDR=0x80400000
+CONFIG_SPL=y
+CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x88000000
+CONFIG_SYS_MEMTEST_START=0x80000000
+CONFIG_SYS_MEMTEST_END=0x90000000
+CONFIG_REMAKE_ELF=y
+CONFIG_EFI_VAR_BUF_SIZE=139264
+CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y
+CONFIG_EFI_CAPSULE_ON_DISK=y
+CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y
+CONFIG_BOOTCOMMAND="bootflow scan -lb; run bsp_bootcmd"
+CONFIG_DEFAULT_FDT_FILE="imx93-11x11-frdm.dtb"
+CONFIG_SYS_CBSIZE=2048
+CONFIG_SYS_PBSIZE=2074
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_SPL_MAX_SIZE=0x26000
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_SPL_BOOTROM_SUPPORT=y
+CONFIG_SPL_LOAD_IMX_CONTAINER=y
+CONFIG_IMX_CONTAINER_CFG="arch/arm/mach-imx/imx9/container.cfg"
+# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
+CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x83200000
+CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1040
+CONFIG_SPL_I2C=y
+CONFIG_SPL_POWER=y
+CONFIG_SPL_WATCHDOG=y
+CONFIG_SYS_PROMPT="u-boot=> "
+CONFIG_CMD_CPU=y
+CONFIG_CMD_ERASEENV=y
+CONFIG_CMD_NVEDIT_EFI=y
+# CONFIG_CMD_CRC32 is not set
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_CLK=y
+CONFIG_CMD_DFU=y
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_POWEROFF=y
+CONFIG_CMD_SNTP=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EFIDEBUG=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_GETTIME=y
+CONFIG_CMD_TIMER=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_HASH=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_SPAWN=y
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_NOWHERE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_ENV_RELOC_GD_ENV_ADDR=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_SPL_DM=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_ADC=y
+CONFIG_ADC_IMX93=y
+CONFIG_SPL_CLK_IMX93=y
+CONFIG_CLK_IMX93=y
+CONFIG_DFU_MMC=y
+CONFIG_IMX_RGPIO2P=y
+CONFIG_DM_PCA953X=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_IMX_LPI2C=y
+CONFIG_SUPPORT_EMMC_RPMB=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_ES_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_FSL_USDHC=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_PINCTRL_IMX93=y
+CONFIG_DM_PMIC=y
+CONFIG_SPL_DM_PMIC_PCA9450=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_SERIAL=y
+CONFIG_FSL_LPUART=y
+CONFIG_SYSRESET=y
+CONFIG_SYSRESET_CMD_POWEROFF=y
+CONFIG_SYSRESET_PSCI=y
+CONFIG_DM_THERMAL=y
+CONFIG_ULP_WATCHDOG=y
+CONFIG_WDT=y
+CONFIG_SHA384=y
+CONFIG_LZO=y
+CONFIG_BZIP2=y
+CONFIG_UTHREAD=y
diff --git a/configs/phycore-imx8mm_defconfig b/configs/phycore-imx8mm_defconfig
index 96eacec1d23..4d6bce26f07 100644
--- a/configs/phycore-imx8mm_defconfig
+++ b/configs/phycore-imx8mm_defconfig
@@ -11,7 +11,7 @@ CONFIG_ENV_SIZE=0x10000
CONFIG_ENV_OFFSET=0x3C0000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="freescale/imx8mm-phyboard-polis-rdk"
-CONFIG_IMX8M_OPTEE_LOAD_ADDR=0x56000000
+CONFIG_IMX8M_OPTEE_LOAD_ADDR=0x7e000000
CONFIG_TARGET_PHYCORE_IMX8MM=y
CONFIG_DM_RESET=y
CONFIG_SYS_MONITOR_LEN=524288
@@ -23,7 +23,7 @@ CONFIG_SPL_TEXT_BASE=0x7E1000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_BSS_START_ADDR=0x910000
CONFIG_SPL_BSS_MAX_SIZE=0x2000
-CONFIG_SYS_LOAD_ADDR=0x40480000
+CONFIG_SYS_LOAD_ADDR=0x47602000
CONFIG_SF_DEFAULT_BUS=3
CONFIG_SPL=y
CONFIG_ENV_OFFSET_REDUND=0x3E0000
@@ -31,8 +31,9 @@ CONFIG_PCI=y
CONFIG_FIT=y
CONFIG_FIT_EXTERNAL_OFFSET=0x3000
CONFIG_SPL_LOAD_FIT=y
+CONFIG_BOOTSTD_FULL=y
CONFIG_OF_SYSTEM_SETUP=y
-CONFIG_DEFAULT_FDT_FILE="oftree"
+CONFIG_DEFAULT_FDT_FILE="imx8mm-phyboard-polis-rdk"
CONFIG_SYS_CBSIZE=2048
CONFIG_SYS_PBSIZE=2074
CONFIG_BOARD_LATE_INIT=y
@@ -48,7 +49,6 @@ CONFIG_SPL_I2C=y
CONFIG_SPL_POWER=y
CONFIG_SPL_SPI_FLASH_MTD=y
CONFIG_SPL_WATCHDOG=y
-CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="u-boot=> "
# CONFIG_CMD_EXPORTENV is not set
# CONFIG_CMD_IMPORTENV is not set
@@ -66,15 +66,9 @@ CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_PCI=y
CONFIG_CMD_SF_TEST=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_REGULATOR=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
CONFIG_OF_CONTROL=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_ENV_OVERWRITE=y
diff --git a/doc/board/nxp/imx93_frdm.rst b/doc/board/nxp/imx93_frdm.rst
new file mode 100644
index 00000000000..a1f526fd4cc
--- /dev/null
+++ b/doc/board/nxp/imx93_frdm.rst
@@ -0,0 +1,75 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+imx93_frdm
+==========
+
+U-Boot for the NXP i.MX93 FRDM board
+
+Quick Start
+-----------
+
+- Get and Build the ARM Trusted firmware
+- Get the DDR firmware
+- Get ahab-container.img
+- Build U-Boot
+- Boot from the SD card
+
+Get and Build the ARM Trusted firmware
+--------------------------------------
+
+Note: srctree is U-Boot source directory
+Get ATF from: https://github.com/nxp-imx/imx-atf/
+branch: lf_v2.8
+
+.. code-block:: bash
+
+ $ unset LDFLAGS
+ $ make PLAT=imx93 bl31
+ $ cp build/imx93/release/bl31.bin $(srctree)
+
+Get the DDR firmware
+--------------------
+
+.. code-block:: bash
+
+ $ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.21.bin
+ $ chmod +x firmware-imx-8.21.bin
+ $ ./firmware-imx-8.21.bin
+ $ cp firmware-imx-8.21/firmware/ddr/synopsys/lpddr4*.bin $(srctree)
+
+Get ahab-container.img
+----------------------
+
+.. code-block:: bash
+
+ $ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-sentinel-0.11.bin
+ $ chmod +x firmware-sentinel-0.11.bin
+ $ ./firmware-sentinel-0.11.bin
+ $ cp firmware-sentinel-0.11/mx93a1-ahab-container.img $(srctree)
+
+Build U-Boot
+------------
+
+.. code-block:: bash
+
+ $ export CROSS_COMPILE=aarch64-poky-linux-
+ $ make imx93_frdm_defconfig
+ $ make
+
+Copy the flash.bin binary to the MicroSD card at offset 32KB:
+
+.. code-block:: bash
+
+ $ dd if=flash.bin of=/dev/sd[x] bs=1k seek=32; sync
+
+Boot from the SD card
+---------------------
+
+- Configure SW1 boot switches to SD boot mode:
+ 0011 SW1[3:0] - ("USDHC2 4-bit SD3.0" Boot Mode)
+- Insert the SD card in the SD slot (P13) of the board.
+- Connect a USB Type-C cable into the P16 Debug USB Port and connect
+ using a terminal emulator at 115200 bps, 8n1. The console will show up
+ at /dev/ttyACM0.
+- Power on the board by connecting a USB Type-C cable into the P1
+ Power USB Port.
diff --git a/doc/board/nxp/index.rst b/doc/board/nxp/index.rst
index e7ec725cc04..aa7d857346d 100644
--- a/doc/board/nxp/index.rst
+++ b/doc/board/nxp/index.rst
@@ -15,6 +15,7 @@ NXP Semiconductors
imx91_11x11_evk
imx93_9x9_qsb
imx93_11x11_evk
+ imx93_frdm
imx95_evk
imxrt1020-evk
imxrt1050-evk
diff --git a/doc/board/samsung/e850-96.rst b/doc/board/samsung/e850-96.rst
index 0a7b6fc0c9d..b435fa8b353 100644
--- a/doc/board/samsung/e850-96.rst
+++ b/doc/board/samsung/e850-96.rst
@@ -43,17 +43,19 @@ Legend:
BL31 in terms of ARM boot flow
* ``LDFW``: Loadable Firmware
-Build Procedure
+Unbricking Note
---------------
-.. warning::
- At the moment USB is not enabled in U-Boot for this board. Although eMMC is
- enabled, you won't be able to flash images over USB (fastboot). So flashing
- U-Boot binary **WILL** effectively brick your board. The ``dltool`` [8]_ can
- be used then to perform USB boot and flash LittleKernel bootloader binary [7]_
- to unbrick and revive the board. Flashing U-Boot binary might be helpful for
- developers or anybody who want to check current state of U-Boot enablement on
- E850-96 (which is mostly serial console, eMMC and related blocks).
+In case the board is bricked for some reason, the ``dltool`` [8]_ can be used to
+unbrick and revive it. This tool performs USB boot, and uploads the LittleKernel
+bootloader over USB, which is then being executed on the board. The loaded
+bootloader further enters fastboot mode, so that the user can flash the
+functional bootloader binary (U-Boot or LittleKernel [7]_) to eMMC using
+``fastboot`` tool. Please read the ``dltool`` README file for more details about
+the procedure.
+
+Build Procedure
+---------------
Build U-Boot binary from source code (using AArch64 baremetal GCC toolchain):
@@ -64,8 +66,9 @@ Build U-Boot binary from source code (using AArch64 baremetal GCC toolchain):
make e850-96_defconfig
make
-Boot E850-96 board into fastboot mode as described in board software doc [9]_,
-and flash U-Boot binary into ``bootloader`` eMMC partition:
+The original E850-96 board is shipped with LittleKernel-based bootloader flashed
+in eMMC. To replace it with U-Boot, boot into fastboot mode (as described in
+the board software documentation [9]_), and flash U-Boot binary:
.. prompt:: bash $
@@ -74,6 +77,66 @@ and flash U-Boot binary into ``bootloader`` eMMC partition:
U-Boot will boot up to the shell.
+Flashing
+--------
+
+User area of eMMC contains GPT partition table (either Linux or Android). Boot
+Partition A (``mmc0boot0``) contains all firmware/bootloaders. Boot Partition
+B (``mmc0boot1``) contains U-Boot environment.
+
+First make sure to format eMMC accordingly. Prepare the initial environment:
+
+.. prompt:: bash =>
+
+ env default -f -a
+ env save
+
+For Linux, just format eMMC using default ``$partitions`` definitions:
+
+.. prompt:: bash =>
+
+ gpt write mmc 0 $partitions
+
+For Android, use ``$partitions_android`` instead:
+
+.. prompt:: bash =>
+
+ setenv partitions_linux $partitions
+ setenv partitions $partitions_android
+ env save
+ gpt write mmc 0 $partitions
+
+In case of Linux, there are two partitions available: ``esp`` (EFI System
+Partition) and ``rootfs``. It is recommended to use fastboot to flash images to
+those partitions. Enter fastboot mode on your device:
+
+.. prompt:: bash =>
+
+ fastboot usb 0
+
+And then flash the images:
+
+.. prompt:: bash $
+
+ fastboot flash esp esp.img
+ fastboot flash rootfs rootfs.img
+
+To update the firmware, it's easier to use DFU. Enter DFU mode on the board:
+
+.. prompt:: bash =>
+
+ dfu 0 mmc 0
+
+To update U-Boot:
+
+.. prompt:: bash $
+
+ dfu-util -D u-boot.bin -a bootloader
+
+It's also possible to use fastboot to flash the whole ``mmc0boot0`` HW
+partition, but it's not so straightforward, as one have to prepare the image for
+the whole ``boot0`` partition containing all firmware binaries first.
+
References
----------
diff --git a/drivers/adc/imx93-adc.c b/drivers/adc/imx93-adc.c
index f593fb6447b..d671df79f68 100644
--- a/drivers/adc/imx93-adc.c
+++ b/drivers/adc/imx93-adc.c
@@ -221,7 +221,7 @@ static int imx93_adc_stop(struct udevice *dev)
static int imx93_adc_probe(struct udevice *dev)
{
struct imx93_adc_priv *adc = dev_get_priv(dev);
- unsigned int ret;
+ int ret;
ret = imx93_adc_calibration(adc);
if (ret < 0)
@@ -238,7 +238,7 @@ static int imx93_adc_of_to_plat(struct udevice *dev)
{
struct adc_uclass_plat *uc_pdata = dev_get_uclass_plat(dev);
struct imx93_adc_priv *adc = dev_get_priv(dev);
- unsigned int ret;
+ int ret;
adc->regs = dev_read_addr_ptr(dev);
if (adc->regs == (struct imx93_adc *)FDT_ADDR_T_NONE) {
diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
index 966783e4b62..0f753b9dbb9 100644
--- a/drivers/misc/Kconfig
+++ b/drivers/misc/Kconfig
@@ -641,6 +641,14 @@ config ESM_K3
help
Support ESM (Error Signaling Module) on TI K3 SoCs.
+config K3_BIST
+ bool "Enable K3 BIST driver"
+ depends on ARCH_K3
+ help
+ Support BIST (Built-In Self Test) module on TI K3 SoCs. This driver
+ supports running both PBIST (Memory BIST) and LBIST (Logic BIST) on
+ a region or IP in the SoC.
+
config MICROCHIP_FLEXCOM
bool "Enable Microchip Flexcom driver"
depends on MISC
diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
index 09dfd8072db..f7422c8e95a 100644
--- a/drivers/misc/Makefile
+++ b/drivers/misc/Makefile
@@ -88,6 +88,7 @@ obj-$(CONFIG_JZ4780_EFUSE) += jz4780_efuse.o
obj-$(CONFIG_MICROCHIP_FLEXCOM) += microchip_flexcom.o
obj-$(CONFIG_K3_AVS0) += k3_avs.o
obj-$(CONFIG_ESM_K3) += k3_esm.o
+obj-$(CONFIG_K3_BIST) += k3_bist.o
obj-$(CONFIG_ESM_PMIC) += esm_pmic.o
obj-$(CONFIG_SL28CPLD) += sl28cpld.o
obj-$(CONFIG_SPL_SOCFPGA_DT_REG) += socfpga_dtreg.o
diff --git a/drivers/misc/k3_bist.c b/drivers/misc/k3_bist.c
new file mode 100644
index 00000000000..3acb1a1ac1f
--- /dev/null
+++ b/drivers/misc/k3_bist.c
@@ -0,0 +1,807 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Texas Instruments' BIST (Built-In Self-Test) driver
+ *
+ * Copyright (C) 2025 Texas Instruments Incorporated - https://www.ti.com/
+ * Neha Malcom Francis <n-francis@ti.com>
+ *
+ */
+
+#include <dm.h>
+#include <errno.h>
+#include <clk.h>
+#include <asm/io.h>
+#include <dm/device_compat.h>
+#include <linux/bitops.h>
+#include <linux/delay.h>
+#include <asm/arch/hardware.h>
+#include <linux/soc/ti/ti_sci_protocol.h>
+#include <remoteproc.h>
+#include <power-domain.h>
+#include <k3_bist.h>
+
+#include "k3_bist_static_data.h"
+
+/* PBIST Timeout Value */
+#define PBIST_MAX_TIMEOUT_VALUE 100000000
+
+/**
+ * struct k3_bist_privdata - K3 BIST structure
+ * @dev: device pointer
+ * @pbist_base: base of register set for PBIST
+ * @instance: PBIST instance number
+ * @intr_num: corresponding interrupt ID of the PBIST instance
+ * @lbist_ctrl_mmr: base of CTRL MMR register set for LBIST
+ */
+struct k3_bist_privdata {
+ struct udevice *dev;
+ void *pbist_base;
+ u32 instance;
+ u32 intr_num;
+ void *lbist_ctrl_mmr;
+ struct pbist_inst_info *pbist_info;
+ struct lbist_inst_info *lbist_info;
+};
+
+static struct k3_bist_privdata *k3_bist_priv;
+
+/**
+ * check_post_pbist_result() - Check POST results
+ *
+ * Function to check whether HW Power-On Self Test, i.e. POST has run
+ * successfully on the MCU domain.
+ *
+ * Return: 0 if all went fine, else corresponding error.
+ */
+static int check_post_pbist_result(void)
+{
+ bool is_done, timed_out;
+ u32 mask;
+ u32 post_reg_val, shift;
+
+ /* Read HW POST status register */
+ post_reg_val = readl(WKUP_CTRL_MMR0_BASE + WKUP_CTRL_MMR_CFG0_WKUP_POST_STAT);
+
+ /* Check if HW POST PBIST was performed */
+ shift = WKUP_CTRL_MMR_CFG0_WKUP_POST_STAT_POST_MCU_PBIST_DONE_SHIFT;
+ is_done = (((post_reg_val >> shift) & 0x1u) == 0x1u) ? (bool)true : (bool)false;
+
+ if (!is_done) {
+ /* HW POST: PBIST not completed, check if it timed out */
+ shift = WKUP_CTRL_MMR_CFG0_WKUP_POST_STAT_POST_MCU_PBIST_TIMEOUT_SHIFT;
+ timed_out = (((post_reg_val >> shift) & 0x1u) == 0x1u) ? (bool)true : (bool)false;
+
+ if (!timed_out) {
+ printf("%s: PBIST was not performed at all on this device for this core\n",
+ __func__);
+ return -EINVAL;
+ }
+ printf("%s: PBIST was attempted but timed out for this section\n",
+ __func__);
+ return -ETIMEDOUT;
+
+ } else {
+ /* HW POST: PBIST was completed on this device, check the result */
+ mask = WKUP_CTRL_MMR_CFG0_WKUP_POST_STAT_POST_MCU_PBIST_FAIL_MASK;
+
+ if ((post_reg_val & mask) != 0) {
+ printf("%s: PBIST was completed, but the test failed\n", __func__);
+ return -EINVAL;
+ }
+ debug("%s: HW POST PBIST completed, test passed\n", __func__);
+ }
+
+ return 0;
+}
+
+/**
+ * check_post_lbist_result() - Check POST results
+ *
+ * Function to check whether HW Power-On Self Test, i.e. POST has run
+ * successfully on the MCU domain.
+ *
+ * Return: 0 if all went fine, else corresponding error.
+ */
+static int check_post_lbist_result(void)
+{
+ bool is_done, timed_out;
+ u32 post_reg_val, shift;
+ u32 calculated_misr, expected_misr;
+
+ /* Read HW POST status register */
+ post_reg_val = readl(WKUP_CTRL_MMR0_BASE + WKUP_CTRL_MMR_CFG0_WKUP_POST_STAT);
+
+ /* Check if HW POST LBIST was performed */
+ shift = WKUP_CTRL_MMR_CFG0_WKUP_POST_STAT_POST_MCU_LBIST_DONE_SHIFT;
+ is_done = (((post_reg_val >> shift) & 0x1u) == 0x1u) ? (bool)true : (bool)false;
+
+ if (!is_done) {
+ /* HW POST: PBIST not completed, check if it timed out */
+ shift = WKUP_CTRL_MMR_CFG0_WKUP_POST_STAT_POST_MCU_LBIST_TIMEOUT_SHIFT;
+ timed_out = (((post_reg_val >> shift) & 0x1u) == 0x1u) ? (bool)true : (bool)false;
+
+ if (!timed_out) {
+ printf("%s: PBIST was not performed at all on this device for this core\n",
+ __func__);
+ return -EINVAL;
+ }
+ printf("%s: PBIST was attempted but timed out for this section\n",
+ __func__);
+ return -ETIMEDOUT;
+
+ } else {
+ /* Get the output MISR and the expected MISR which 0 for MCU domain */
+ lbist_get_misr((void *)MCU_LBIST_BASE, &calculated_misr);
+ expected_misr = readl(MCU_CTRL_MMR0_CFG0_BASE + MCU_CTRL_MMR_CFG0_MCU_LBIST_SIG);
+
+ if (calculated_misr != expected_misr) {
+ /* HW POST: LBIST was completed, but the test failed for this core */
+ printf("%s: calculated MISR != expected MISR\n", __func__);
+ debug("%s: calculated MISR = %x\n", __func__, calculated_misr);
+ debug("%s: expected MISR = %x\n", __func__, expected_misr);
+ return -EINVAL;
+ }
+ debug("%s: HW POST LBIST completed, test passed\n", __func__);
+ }
+
+ return 0;
+}
+
+/**
+ * pbist_self_test() - Run PBIST_TEST on specified cores
+ * @config: pbist_config structure for PBIST test
+ *
+ * Function to run PBIST_TEST
+ *
+ * Return: 0 if all went fine, else corresponding error.
+ */
+static int pbist_self_test(struct pbist_config *config)
+{
+ void *base = k3_bist_priv->pbist_base;
+
+ /* Turns on PBIST clock in PBIST ACTivate register */
+ writel(PBIST_PACT_PACT_MASK, base + PBIST_PACT);
+
+ /* Set Margin mode register for Test mode */
+ writel(PBIST_TEST_MODE, base + PBIST_MARGIN_MODE);
+
+ /* Zero out Loop counter 0 */
+ writel(0x0, base + PBIST_L0);
+
+ /* Set algorithm bitmap */
+ writel(config->algorithms_bit_map, base + PBIST_ALGO);
+
+ /* Set Memory group bitmap */
+ writel(config->memory_groups_bit_map, base + PBIST_RINFO);
+
+ /* Zero out override register */
+ writel(config->override, base + PBIST_OVER);
+
+ /* Set Scramble value - 64 bit*/
+ writel(config->scramble_value_lo, base + PBIST_SCR_LO);
+ writel(config->scramble_value_hi, base + PBIST_SCR_HI);
+
+ /* Set DLR register for ROM based testing and Config Access */
+ writel(PBIST_DLR_DLR0_ROM_MASK
+ | PBIST_DLR_DLR0_CAM_MASK, base + PBIST_DLR);
+
+ /* Allow time for completion of test*/
+ udelay(1000);
+
+ if (readl(base + PBIST_FSRF)) {
+ printf("%s: test failed\n", __func__);
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+/**
+ * pbist_neg_self_test() - Run PBIST_negTEST on specified cores
+ * @config: pbist_config_neg structure for PBIST negative test
+ *
+ * Function to run PBIST failure insertion test
+ *
+ * Return: 0 if all went fine, else corresponding error.
+ */
+static int pbist_neg_self_test(struct pbist_config_neg *config)
+{
+ void *base = k3_bist_priv->pbist_base;
+
+ /* Turns on PBIST clock in PBIST ACTivate register */
+ writel(PBIST_PACT_PACT_MASK, base + PBIST_PACT);
+
+ /* Set Margin mode register for Test mode */
+ writel(PBIST_FAILURE_INSERTION_TEST_MODE, base + PBIST_MARGIN_MODE);
+
+ /* Zero out Loop counter 0 */
+ writel(0x0, base + PBIST_L0);
+
+ /* Set DLR register */
+ writel(0x10, base + PBIST_DLR);
+
+ /* Set Registers*/
+ writel(0x00000001, base + PBIST_RF0L);
+ writel(0x00003123, base + PBIST_RF0U);
+ writel(0x0513FC02, base + PBIST_RF1L);
+ writel(0x00000002, base + PBIST_RF1U);
+ writel(0x00000003, base + PBIST_RF2L);
+ writel(0x00000000, base + PBIST_RF2U);
+ writel(0x00000004, base + PBIST_RF3L);
+ writel(0x00000028, base + PBIST_RF3U);
+ writel(0x64000044, base + PBIST_RF4L);
+ writel(0x00000000, base + PBIST_RF4U);
+ writel(0x0006A006, base + PBIST_RF5L);
+ writel(0x00000000, base + PBIST_RF5U);
+ writel(0x00000007, base + PBIST_RF6L);
+ writel(0x0000A0A0, base + PBIST_RF6U);
+ writel(0x00000008, base + PBIST_RF7L);
+ writel(0x00000064, base + PBIST_RF7U);
+ writel(0x00000009, base + PBIST_RF8L);
+ writel(0x0000A5A5, base + PBIST_RF8U);
+ writel(0x0000000A, base + PBIST_RF9L);
+ writel(0x00000079, base + PBIST_RF9U);
+ writel(0x00000000, base + PBIST_RF10L);
+ writel(0x00000001, base + PBIST_RF10U);
+ writel(0xAAAAAAAA, base + PBIST_D);
+ writel(0xAAAAAAAA, base + PBIST_E);
+
+ writel(config->CA2, base + PBIST_CA2);
+ writel(config->CL0, base + PBIST_CL0);
+ writel(config->CA3, base + PBIST_CA3);
+ writel(config->I0, base + PBIST_I0);
+ writel(config->CL1, base + PBIST_CL1);
+ writel(config->I3, base + PBIST_I3);
+ writel(config->I2, base + PBIST_I2);
+ writel(config->CL2, base + PBIST_CL2);
+ writel(config->CA1, base + PBIST_CA1);
+ writel(config->CA0, base + PBIST_CA0);
+ writel(config->CL3, base + PBIST_CL3);
+ writel(config->I1, base + PBIST_I1);
+ writel(config->RAMT, base + PBIST_RAMT);
+ writel(config->CSR, base + PBIST_CSR);
+ writel(config->CMS, base + PBIST_CMS);
+
+ writel(0x00000009, base + PBIST_STR);
+
+ /* Start PBIST */
+ writel(0x00000001, base + PBIST_STR);
+
+ /* Allow time for completion of test*/
+ udelay(1000);
+
+ if (readl(base + PBIST_FSRF) == 0) {
+ printf("%s: test failed\n", __func__);
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+/**
+ * pbist_rom_self_test() - Run PBIST_ROM_TEST on specified cores
+ * @config: pbist_config_rom structure for PBIST negative test
+ *
+ * Function to run PBIST test of ROM
+ *
+ * Return: 0 if all went fine, else corresponding error.
+ */
+static int pbist_rom_self_test(struct pbist_config_rom *config)
+{
+ void *base = k3_bist_priv->pbist_base;
+
+ /* Turns on PBIST clock in PBIST ACTivate register */
+ writel(0x1, base + PBIST_PACT);
+
+ /* Set Margin mode register for Test mode */
+ writel(0xf, base + PBIST_MARGIN_MODE);
+
+ /* Zero out Loop counter 0 */
+ writel(0x0, base + PBIST_L0);
+
+ /* Set DLR register */
+ writel(0x310, base + PBIST_DLR);
+
+ /* Set Registers*/
+ writel(0x00000001, base + PBIST_RF0L);
+ writel(0x00003123, base + PBIST_RF0U);
+ writel(0x7A400183, base + PBIST_RF1L);
+ writel(0x00000060, base + PBIST_RF1U);
+ writel(0x00000184, base + PBIST_RF2L);
+ writel(0x00000000, base + PBIST_RF2U);
+ writel(0x7B600181, base + PBIST_RF3L);
+ writel(0x00000061, base + PBIST_RF3U);
+ writel(0x00000000, base + PBIST_RF4L);
+ writel(0x00000000, base + PBIST_RF4U);
+
+ writel(config->D, base + PBIST_D);
+ writel(config->E, base + PBIST_E);
+ writel(config->CA2, base + PBIST_CA2);
+ writel(config->CL0, base + PBIST_CL0);
+ writel(config->CA3, base + PBIST_CA3);
+ writel(config->I0, base + PBIST_I0);
+ writel(config->CL1, base + PBIST_CL1);
+ writel(config->I3, base + PBIST_I3);
+ writel(config->I2, base + PBIST_I2);
+ writel(config->CL2, base + PBIST_CL2);
+ writel(config->CA1, base + PBIST_CA1);
+ writel(config->CA0, base + PBIST_CA0);
+ writel(config->CL3, base + PBIST_CL3);
+ writel(config->I1, base + PBIST_I1);
+ writel(config->RAMT, base + PBIST_RAMT);
+ writel(config->CSR, base + PBIST_CSR);
+ writel(config->CMS, base + PBIST_CMS);
+
+ writel(0x00000009, base + PBIST_STR);
+
+ /* Start PBIST */
+ writel(0x00000001, base + PBIST_STR);
+
+ /* Allow time for completion of test*/
+ udelay(1000);
+
+ if (readl(base + PBIST_FSRF)) {
+ printf("%s: test failed\n", __func__);
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+/**
+ * lbist_program_config() - Program LBIST config
+ * @config: lbist_config structure for LBIST test
+ */
+static void lbist_program_config(struct lbist_config *config)
+{
+ void *base = k3_bist_priv->lbist_ctrl_mmr;
+
+ lbist_set_clock_delay(base, config->dc_def);
+ lbist_set_divide_ratio(base, config->divide_ratio);
+ lbist_clear_load_div(base);
+ lbist_set_load_div(base);
+ lbist_set_num_stuck_at_patterns(base, config->static_pc_def);
+ lbist_set_num_set_patterns(base, config->set_pc_def);
+ lbist_set_num_reset_patterns(base, config->reset_pc_def);
+ lbist_set_num_chain_test_patterns(base, config->scan_pc_def);
+ lbist_set_seed(base, config->prpg_def_l, config->prpg_def_u);
+}
+
+/**
+ * lbist_enable_isolation() - LBIST Enable Isolation
+ * @config: lbist_config structure for LBIST test
+ */
+void lbist_enable_isolation(void)
+{
+ void *base = k3_bist_priv->lbist_ctrl_mmr;
+ u32 reg_val;
+
+ reg_val = readl(base + LBIST_SPARE0);
+ writel(reg_val | (LBIST_SPARE0_LBIST_SELFTEST_EN_MASK), base + LBIST_SPARE0);
+}
+
+/**
+ * lbist_disable_isolation() - LBIST Disable Isolation
+ * @config: lbist_config structure for LBIST test
+ */
+void lbist_disable_isolation(void)
+{
+ void *base = k3_bist_priv->lbist_ctrl_mmr;
+ u32 reg_val;
+
+ reg_val = readl(base + LBIST_SPARE0);
+ writel(reg_val & (~(LBIST_SPARE0_LBIST_SELFTEST_EN_MASK)), base + LBIST_SPARE0);
+}
+
+/**
+ * lbist_enable_run_bist_mode() - LBIST Enable run BIST mode
+ * @config: lbist_config structure for LBIST test
+ */
+static void lbist_enable_run_bist_mode(struct lbist_config *config)
+{
+ void *base = k3_bist_priv->lbist_ctrl_mmr;
+ u32 reg_val;
+
+ reg_val = readl(base + LBIST_CTRL);
+ writel(reg_val | (LBIST_CTRL_RUNBIST_MODE_MAX << LBIST_CTRL_RUNBIST_MODE_SHIFT),
+ base + LBIST_CTRL);
+}
+
+/**
+ * lbist_start() - Start LBIST test
+ * @config: lbist_config structure for LBIST test
+ */
+static void lbist_start(struct lbist_config *config)
+{
+ struct udevice *dev = k3_bist_priv->dev;
+ void *base = k3_bist_priv->lbist_ctrl_mmr;
+ u32 reg_val;
+ u32 timeout_count = 0;
+
+ reg_val = readl(base + LBIST_CTRL);
+ writel(reg_val | (LBIST_CTRL_BIST_RESET_MAX << LBIST_CTRL_BIST_RESET_SHIFT),
+ base + LBIST_CTRL);
+
+ reg_val = readl(base + LBIST_CTRL);
+ writel(reg_val | (LBIST_CTRL_BIST_RUN_MAX << LBIST_CTRL_BIST_RUN_SHIFT),
+ base + LBIST_CTRL);
+
+ reg_val = readl(base + LBIST_STAT);
+ if ((reg_val & LBIST_STAT_BIST_RUNNING_MASK) != 0)
+ debug("%s(dev=%p): LBIST is running\n", __func__, dev);
+
+ while (((!(readl(base + LBIST_STAT) & LBIST_STAT_BIST_DONE_MASK))) &&
+ (timeout_count++ < PBIST_MAX_TIMEOUT_VALUE)) {
+ }
+
+ if (!(readl(base + LBIST_STAT) & LBIST_STAT_BIST_DONE_MASK))
+ printf("%s(dev=%p): test failed\n", __func__, dev);
+}
+
+/**
+ * lbist_check_result() - Check LBIST test result
+ * @config: lbist_config structure for LBIST test
+ *
+ * Return: 0 if all went fine, else corresponding error.
+ */
+static int lbist_check_result(struct lbist_config *config)
+{
+ void *base = k3_bist_priv->lbist_ctrl_mmr;
+ struct lbist_inst_info *info = k3_bist_priv->lbist_info;
+ u32 calculated_misr;
+ u32 expected_misr;
+
+ lbist_get_misr(base, &calculated_misr);
+ expected_misr = info->expected_misr;
+ lbist_clear_run_bist_mode(base);
+ lbist_stop(base);
+ lbist_reset(base);
+
+ if (calculated_misr != expected_misr) {
+ printf("calculated_misr != expected_misr\n %x %x\n",
+ calculated_misr, expected_misr);
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static int k3_run_lbist(void)
+{
+ /* Check whether HW POST successfully completely LBIST on the MCU domain */
+ struct lbist_inst_info *info_lbist = k3_bist_priv->lbist_info;
+
+ lbist_program_config(&info_lbist->lbist_conf);
+ lbist_enable_isolation();
+ lbist_reset(&info_lbist->lbist_conf);
+ lbist_enable_run_bist_mode(&info_lbist->lbist_conf);
+ lbist_start(&info_lbist->lbist_conf);
+ if (lbist_check_result(&info_lbist->lbist_conf)) {
+ printf("%s: test failed\n", __func__);
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static int k3_run_lbist_post(void)
+{
+ if (check_post_lbist_result()) {
+ printf("HW POST LBIST failed to run successfully\n");
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static int k3_run_pbist_post(void)
+{
+ /* Check whether HW POST successfully completely PBIST on the MCU domain */
+ if (check_post_pbist_result()) {
+ printf("HW POST failed to run successfully\n");
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static int k3_run_pbist(void)
+{
+ /* Run PBIST test */
+ struct pbist_inst_info *info = k3_bist_priv->pbist_info;
+ int num_runs = info->num_pbist_runs;
+
+ for (int j = 0; j < num_runs; j++) {
+ if (pbist_self_test(&info->pbist_config_run[j])) {
+ printf("failed to run PBIST test\n");
+ return -EINVAL;
+ }
+ }
+
+ return 0;
+}
+
+static int k3_run_pbist_neg(void)
+{
+ /* Run PBIST failure insertion test */
+ struct pbist_inst_info *info = k3_bist_priv->pbist_info;
+
+ if (pbist_neg_self_test(&info->pbist_neg_config_run)) {
+ printf("failed to run PBIST negative test\n");
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static int k3_run_pbist_rom(void)
+{
+ /* Run PBIST test on ROM */
+ struct pbist_inst_info *info = k3_bist_priv->pbist_info;
+ int num_runs = info->num_pbist_rom_test_runs;
+
+ for (int j = 0; j < num_runs; j++) {
+ if (pbist_rom_self_test(&info->pbist_rom_test_config_run[j])) {
+ printf("failed to run ROM PBIST test\n");
+ return -EINVAL;
+ }
+ }
+
+ return 0;
+}
+
+int prepare_pbist(struct ti_sci_handle *handle)
+{
+ struct ti_sci_proc_ops *proc_ops = &handle->ops.proc_ops;
+ struct ti_sci_dev_ops *dev_ops = &handle->ops.dev_ops;
+ struct pbist_inst_info *info_pbist = k3_bist_priv->pbist_info;
+ struct core_under_test *cut = info_pbist->cut;
+
+ if (proc_ops->proc_request(handle, cut[0].proc_id)) {
+ printf("%s: requesting primary core failed\n", __func__);
+ return -EINVAL;
+ }
+
+ if (proc_ops->proc_request(handle, cut[1].proc_id)) {
+ printf("%s: requesting secondary core failed\n", __func__);
+ return -EINVAL;
+ }
+
+ if (dev_ops->set_device_resets(handle, cut[0].dev_id, 0x1)) {
+ printf("%s: local reset primary core failed\n", __func__);
+ return -EINVAL;
+ }
+
+ if (dev_ops->set_device_resets(handle, cut[1].dev_id, 0x1)) {
+ printf("%s: local reset secondary core failed\n", __func__);
+ return -EINVAL;
+ }
+
+ if (dev_ops->get_device(handle, cut[0].dev_id)) {
+ printf("%s: power on primary core failed\n", __func__);
+ return -EINVAL;
+ }
+
+ if (dev_ops->get_device(handle, cut[1].dev_id)) {
+ printf("%s: power on secondary core failed\n", __func__);
+ return -EINVAL;
+ }
+
+ if (dev_ops->get_device(handle, info_pbist->dev_id)) {
+ printf("%s: power on PBIST failed\n", __func__);
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+int deprepare_pbist(struct ti_sci_handle *handle)
+{
+ struct ti_sci_proc_ops *proc_ops = &handle->ops.proc_ops;
+ struct ti_sci_dev_ops *dev_ops = &handle->ops.dev_ops;
+ struct pbist_inst_info *info_pbist = k3_bist_priv->pbist_info;
+ struct core_under_test *cut = info_pbist->cut;
+
+ if (dev_ops->put_device(handle, info_pbist->dev_id)) {
+ printf("%s: power off PBIST failed\n", __func__);
+ return -EINVAL;
+ }
+
+ if (dev_ops->put_device(handle, cut[1].dev_id)) {
+ printf("%s: power off secondary core failed\n", __func__);
+ return -EINVAL;
+ }
+
+ if (dev_ops->put_device(handle, cut[0].dev_id)) {
+ printf("%s: power off primary core failed\n", __func__);
+ return -EINVAL;
+ }
+
+ if (dev_ops->set_device_resets(handle, cut[0].dev_id, 0)) {
+ printf("%s: putting primary core out of local reset failed\n", __func__);
+ return -EINVAL;
+ }
+
+ if (dev_ops->set_device_resets(handle, cut[1].dev_id, 0)) {
+ printf("%s: putting secondary core out of local reset failed\n", __func__);
+ return -EINVAL;
+ }
+
+ if (dev_ops->put_device(handle, cut[0].dev_id)) {
+ printf("%s: power off primary core failed\n", __func__);
+ return -EINVAL;
+ }
+
+ if (dev_ops->put_device(handle, cut[1].dev_id)) {
+ printf("%s: power off secondary core failed\n", __func__);
+ return -EINVAL;
+ }
+
+ if (proc_ops->proc_release(handle, cut[0].proc_id)) {
+ printf("%s: release primary core failed\n", __func__);
+ return -EINVAL;
+ }
+
+ if (proc_ops->proc_release(handle, cut[1].proc_id)) {
+ printf("%s: release secondary core failed\n", __func__);
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+int prepare_lbist(struct ti_sci_handle *handle)
+{
+ struct ti_sci_proc_ops *proc_ops = &handle->ops.proc_ops;
+ struct ti_sci_dev_ops *dev_ops = &handle->ops.dev_ops;
+ struct lbist_inst_info *info_lbist = k3_bist_priv->lbist_info;
+ struct core_under_test *cut = &info_lbist->cut;
+
+ if (proc_ops->proc_request(handle, cut->proc_id)) {
+ printf("%s: requesting primary core failed\n", __func__);
+ return -EINVAL;
+ }
+
+ if (dev_ops->set_device_resets(handle, cut->dev_id, 0x3)) {
+ printf("%s: module and local reset primary core failed\n", __func__);
+ return -EINVAL;
+ }
+
+ if (dev_ops->idle_device(handle, cut->dev_id)) {
+ printf("%s: putting primary core into retention failed\n", __func__);
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+int deprepare_lbist(struct ti_sci_handle *handle)
+{
+ struct ti_sci_proc_ops *proc_ops = &handle->ops.proc_ops;
+ struct ti_sci_dev_ops *dev_ops = &handle->ops.dev_ops;
+ struct lbist_inst_info *info_lbist = k3_bist_priv->lbist_info;
+ struct core_under_test *cut = &info_lbist->cut;
+
+ if (dev_ops->put_device(handle, 0)) {
+ printf("%s: power off secondary core failed\n", __func__);
+ return -EINVAL;
+ }
+
+ if (dev_ops->put_device(handle, cut->dev_id)) {
+ printf("%s: power off primary core failed\n", __func__);
+ return -EINVAL;
+ }
+
+ lbist_disable_isolation();
+
+ if (dev_ops->idle_device(handle, cut->dev_id)) {
+ printf("%s: retention primary core failed\n", __func__);
+ return -EINVAL;
+ }
+
+ if (dev_ops->idle_device(handle, 0)) {
+ printf("%s: retention secondary core failed\n", __func__);
+ return -EINVAL;
+ }
+
+ if (dev_ops->put_device(handle, 0)) {
+ printf("%s: power off secondary core failed\n", __func__);
+ return -EINVAL;
+ }
+
+ if (dev_ops->put_device(handle, cut->dev_id)) {
+ printf("%s: power off primary core failed\n", __func__);
+ return -EINVAL;
+ }
+
+ if (dev_ops->set_device_resets(handle, cut->dev_id, 0)) {
+ printf("%s: putting primary core out of local reset failed\n", __func__);
+ return -EINVAL;
+ }
+
+ if (proc_ops->proc_release(handle, cut->proc_id)) {
+ printf("%s: release primary core failed\n", __func__);
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+/**
+ * k3_bist_probe() - Basic probe
+ * @dev: corresponding BIST device
+ *
+ * Parses BIST info from device tree, and configures the module accordingly.
+ * Return: 0 if all goes good, else appropriate error message.
+ */
+static int k3_bist_probe(struct udevice *dev)
+{
+ int ret = 0;
+ struct k3_bist_privdata *priv = dev_get_priv(dev);
+ struct pbist_inst_info *info;
+ struct lbist_inst_info *info_lbist;
+ void *reg;
+
+ debug("%s(dev=%p)\n", __func__, dev);
+
+ priv = dev_get_priv(dev);
+ priv->dev = dev;
+
+ k3_bist_priv = priv;
+
+ reg = dev_read_addr_name_ptr(dev, "cfg");
+ if (!reg) {
+ dev_err(dev, "No reg property for BIST\n");
+ return -EINVAL;
+ }
+ priv->pbist_base = reg;
+
+ reg = dev_read_addr_name_ptr(dev, "ctrl_mmr");
+ if (!reg) {
+ dev_err(dev, "No reg property for CTRL MMR\n");
+ return -EINVAL;
+ }
+ priv->lbist_ctrl_mmr = reg;
+
+ ret = dev_read_u32(dev, "ti,sci-dev-id", &priv->instance);
+ if (!priv->instance)
+ return -ENODEV;
+
+ switch (priv->instance) {
+ case PBIST14_DEV_ID:
+ priv->pbist_info = &pbist14_inst_info;
+ priv->lbist_info = &lbist_inst_info_main_r5f2_x;
+ info = priv->pbist_info;
+ info_lbist = priv->lbist_info;
+ priv->intr_num = info->intr_num;
+ break;
+ default:
+ dev_err(dev, "%s: PBIST instance %d not supported\n", __func__, priv->instance);
+ return -ENODEV;
+ };
+
+ return 0;
+}
+
+static const struct bist_ops k3_bist_ops = {
+ .run_lbist = k3_run_lbist,
+ .run_lbist_post = k3_run_lbist_post,
+ .run_pbist = k3_run_pbist,
+ .run_pbist_post = k3_run_pbist_post,
+ .run_pbist_neg = k3_run_pbist_neg,
+ .run_pbist_rom = k3_run_pbist_rom,
+};
+
+static const struct udevice_id k3_bist_ids[] = {
+ { .compatible = "ti,j784s4-bist" },
+ {}
+};
+
+U_BOOT_DRIVER(k3_bist) = {
+ .name = "k3_bist",
+ .of_match = k3_bist_ids,
+ .id = UCLASS_MISC,
+ .ops = &k3_bist_ops,
+ .probe = k3_bist_probe,
+ .priv_auto = sizeof(struct k3_bist_privdata),
+};
diff --git a/drivers/misc/k3_bist_static_data.h b/drivers/misc/k3_bist_static_data.h
new file mode 100644
index 00000000000..af371d83724
--- /dev/null
+++ b/drivers/misc/k3_bist_static_data.h
@@ -0,0 +1,673 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Static Data for Texas Instruments' BIST (Built-In Self-Test) driver
+ *
+ * Copyright (C) 2025 Texas Instruments Incorporated - https://www.ti.com/
+ *
+ */
+
+#ifndef __K3_BIST_STATIC_DATA_H
+#define __K3_BIST_STATIC_DATA_H
+
+/*
+ * Registers and functions related to PBIST
+ */
+
+#define PBIST_MAX_NUM_RUNS 2
+#define NUM_MAX_PBIST_TEST_ROM_RUNS 13
+#define PBIST14_DFT_PBIST_CPU_0_INTR_NUM 311
+
+/* VIM Registers */
+#define VIM_STS_BASE 0x40f80404
+#define VIM_RAW_BASE 0x40f80400
+
+#define VIM_STS(i) (VIM_STS_BASE + (i) / 32 * 0x20)
+#define VIM_RAW(i) (VIM_RAW_BASE + (i) / 32 * 0x20)
+#define VIM_RAW_MASK(i) (BIT((i) % 32))
+
+/* PBIST Registers and Flags*/
+#define PBIST_RF0L 0x00000000
+#define PBIST_RF1L 0x00000004
+#define PBIST_RF2L 0x00000008
+#define PBIST_RF3L 0x0000000C
+#define PBIST_RF4L 0x0000010
+#define PBIST_RF5L 0x0000014
+#define PBIST_RF6L 0x0000018
+#define PBIST_RF7L 0x000001C
+#define PBIST_RF8L 0x0000020
+#define PBIST_RF9L 0x0000024
+#define PBIST_RF10L 0x0000028
+#define PBIST_RF11L 0x000002C
+#define PBIST_RF12L 0x0000030
+#define PBIST_RF13L 0x0000034
+#define PBIST_RF14L 0x0000038
+#define PBIST_RF15L 0x000003C
+#define PBIST_RF0U 0x0000040
+#define PBIST_RF1U 0x0000044
+#define PBIST_RF2U 0x0000048
+#define PBIST_RF3U 0x000004C
+#define PBIST_RF4U 0x0000050
+#define PBIST_RF5U 0x0000054
+#define PBIST_RF6U 0x0000058
+#define PBIST_RF7U 0x000005C
+#define PBIST_RF8U 0x0000060
+#define PBIST_RF9U 0x0000064
+#define PBIST_RF10U 0x0000068
+#define PBIST_RF11U 0x000006C
+#define PBIST_RF12U 0x0000070
+#define PBIST_RF13U 0x0000074
+#define PBIST_RF14U 0x0000078
+#define PBIST_RF15U 0x000007C
+#define PBIST_A0 0x0000100
+#define PBIST_A1 0x0000104
+#define PBIST_A2 0x0000108
+#define PBIST_A3 0x000010C
+#define PBIST_L0 0x0000110
+#define PBIST_L1 0x0000114
+#define PBIST_L2 0x0000118
+#define PBIST_L3 0x000011C
+#define PBIST_D 0x0000120
+#define PBIST_E 0x0000124
+#define PBIST_CA0 0x0000130
+#define PBIST_CA1 0x0000134
+#define PBIST_CA2 0x0000138
+#define PBIST_CA3 0x000013C
+#define PBIST_CL0 0x0000140
+#define PBIST_CL1 0x0000144
+#define PBIST_CL2 0x0000148
+#define PBIST_CL3 0x000014C
+#define PBIST_I0 0x0000150
+#define PBIST_I1 0x0000154
+#define PBIST_I2 0x0000158
+#define PBIST_I3 0x000015C
+#define PBIST_RAMT 0x0000160
+#define PBIST_DLR 0x0000164
+#define PBIST_CMS 0x0000168
+#define PBIST_STR 0x000016C
+#define PBIST_SCR 0x0000170
+#define PBIST_SCR_LO 0x0000170
+#define PBIST_SCR_HI 0x0000174
+#define PBIST_CSR 0x0000178
+#define PBIST_FDLY 0x000017C
+#define PBIST_PACT 0x0000180
+#define PBIST_PID 0x0000184
+#define PBIST_OVER 0x0000188
+#define PBIST_FSRF 0x0000190
+#define PBIST_FSRC 0x0000198
+#define PBIST_FSRA 0x00001A0
+#define PBIST_FSRDL0 0x00001A8
+#define PBIST_FSRDL1 0x00001B0
+#define PBIST_MARGIN_MODE 0x00001B4
+#define PBIST_WRENZ 0x00001B8
+#define PBIST_PAGE_PGS 0x00001BC
+#define PBIST_ROM 0x00001C0
+#define PBIST_ALGO 0x00001C4
+#define PBIST_RINFO 0x00001C8
+
+#define PBIST_MARGIN_MODE_PBIST_DFT_WRITE_MASK 0x00000003
+#define PBIST_MARGIN_MODE_PBIST_DFT_READ_SHIFT 0x00000002
+#define PBIST_MARGIN_MODE_PBIST_DFT_READ_MASK 0x0000000C
+#define PBIST_PACT_PACT_MASK 0x00000001
+#define PBIST_DLR_DLR0_ROM_MASK 0x00000004
+#define PBIST_DLR_DLR0_CAM_MASK 0x00000010
+#define PBIST_NOT_DONE 0
+#define PBIST_DONE 1
+
+/* PBIST test mode */
+#define PBIST_TEST_MODE (PBIST_MARGIN_MODE_PBIST_DFT_WRITE_MASK \
+ | (1 << PBIST_MARGIN_MODE_PBIST_DFT_READ_SHIFT))
+
+/* PBIST Failure Insertion test mode */
+#define PBIST_FAILURE_INSERTION_TEST_MODE (PBIST_MARGIN_MODE_PBIST_DFT_WRITE_MASK \
+ | PBIST_MARGIN_MODE_PBIST_DFT_READ_MASK)
+
+/**
+ * struct core_under_test - structure for a core under a BIST test
+ * @dev_id: Device ID of the core
+ * @proc_id: Processor ID of the core
+ */
+struct core_under_test {
+ u32 dev_id;
+ u32 proc_id;
+};
+
+/*
+ * struct pbist_config - Structure for different configuration used for PBIST
+ * @override: Override value for memory configuration
+ * @algorithms_bit_map: Bitmap to select algorithms to use for test
+ * @memory_groups_bit_map: Bitmap to select memory groups to run test on
+ * @scramble_value_lo: Lower scramble value to be used for test
+ * @scramble_value_hi: Higher scramble value to be used for test
+ */
+struct pbist_config {
+ u32 override;
+ u32 algorithms_bit_map;
+ u64 memory_groups_bit_map;
+ u32 scramble_value_lo;
+ u32 scramble_value_hi;
+};
+
+/*
+ * struct pbist_config_neg - Structure for different configuration used for PBIST
+ * for the failure insertion test to generate negative result
+ * @CA0: Failure insertion value for CA0
+ * @CA1: Failure insertion value for CA1
+ * @CA2: Failure insertion value for CA2
+ * @CA3: Failure insertion value for CA3
+ * @CL0: Failure insertion value for CL0
+ * @CL1: Failure insertion value for CL1
+ * @CL2: Failure insertion value for CL2
+ * @CL3: Failure insertion value for CL3
+ * @CMS: Failure insertion value for CMS
+ * @CSR: Failure insertion value for CSR
+ * @I0: Failure insertion value for I0
+ * @I1: Failure insertion value for I1
+ * @I2: Failure insertion value for I2
+ * @I3: Failure insertion value for I3
+ * @RAMT: Failure insertion value for RAMT
+ */
+struct pbist_config_neg {
+ u32 CA0;
+ u32 CA1;
+ u32 CA2;
+ u32 CA3;
+ u32 CL0;
+ u32 CL1;
+ u32 CL2;
+ u32 CL3;
+ u32 CMS;
+ u32 CSR;
+ u32 I0;
+ u32 I1;
+ u32 I2;
+ u32 I3;
+ u32 RAMT;
+};
+
+/*
+ * struct pbist_config_neg - Structure for different configuration used for PBIST
+ * test of ROM
+ * @D: ROM test value for D
+ * @E: ROM test value for E
+ * @CA2: ROM test value for CA2
+ * @CL0: ROM test value for CL0
+ * @CA3: ROM test value for CA3
+ * @I0: ROM test value for I0
+ * @CL1: ROM test value for CL1
+ * @I3: ROM test value for I3
+ * @I2: ROM test value for I2
+ * @CL2: ROM test value for CL2
+ * @CA1: ROM test value for CA1
+ * @CA0: ROM test value for CA0
+ * @CL3: ROM test value for CL3
+ * @I1: ROM test value for I1
+ * @RAMT: ROM test value for RAMT
+ * @CSR: ROM test value for CSR
+ * @CMS: ROM test value for CMS
+ */
+struct pbist_config_rom {
+ u32 D;
+ u32 E;
+ u32 CA2;
+ u32 CL0;
+ u32 CA3;
+ u32 I0;
+ u32 CL1;
+ u32 I3;
+ u32 I2;
+ u32 CL2;
+ u32 CA1;
+ u32 CA0;
+ u32 CL3;
+ u32 I1;
+ u32 RAMT;
+ u32 CSR;
+ u32 CMS;
+};
+
+/*
+ * struct pbist_inst_info - Structure for different configuration used for PBIST
+ * @num_pbist_runs: Number of runs of PBIST test
+ * @intr_num: Interrupt number triggered by this PBIST instance to MCU R5 VIM
+ * @pbist_config_run: Configuration for PBIST test
+ * @pbist_neg_config_run: Configuration for PBIST negative test
+ * @num_pbist_rom_test_runs: Number of runs of PBIST test on ROM
+ * @pbist_rom_test_config_run: Configuration for PBIST test on ROM
+ */
+struct pbist_inst_info {
+ u32 num_pbist_runs;
+ u32 intr_num;
+ u32 dev_id;
+ struct core_under_test cut[2];
+ struct pbist_config pbist_config_run[PBIST_MAX_NUM_RUNS];
+ struct pbist_config_neg pbist_neg_config_run;
+ u32 num_pbist_rom_test_runs;
+ struct pbist_config_rom pbist_rom_test_config_run[NUM_MAX_PBIST_TEST_ROM_RUNS];
+};
+
+/*
+ * Registers and functions related to LBIST
+ */
+
+#define LBIST_CTRL_DIVIDE_RATIO_MASK 0x0000001F
+#define LBIST_CTRL_DIVIDE_RATIO_SHIFT 0x00000000
+#define LBIST_CTRL_DIVIDE_RATIO_MAX 0x0000001F
+
+#define LBIST_CTRL_LOAD_DIV_MASK 0x00000080
+#define LBIST_CTRL_LOAD_DIV_SHIFT 0x00000007
+#define LBIST_CTRL_LOAD_DIV_MAX 0x00000001
+
+#define LBIST_CTRL_DC_DEF_MASK 0x00000300
+#define LBIST_CTRL_DC_DEF_SHIFT 0x00000008
+#define LBIST_CTRL_DC_DEF_MAX 0x00000003
+
+#define LBIST_CTRL_RUNBIST_MODE_MASK 0x0000F000
+#define LBIST_CTRL_RUNBIST_MODE_SHIFT 0x0000000C
+#define LBIST_CTRL_RUNBIST_MODE_MAX 0x0000000F
+
+#define LBIST_CTRL_BIST_RUN_MASK 0x0F000000
+#define LBIST_CTRL_BIST_RUN_SHIFT 0x00000018
+#define LBIST_CTRL_BIST_RUN_MAX 0x0000000F
+
+#define LBIST_CTRL_BIST_RESET_MASK 0x80000000
+#define LBIST_CTRL_BIST_RESET_SHIFT 0x0000001F
+#define LBIST_CTRL_BIST_RESET_MAX 0x00000001
+
+/* LBIST_PATCOUNT */
+
+#define LBIST_PATCOUNT_SCAN_PC_DEF_MASK 0x0000000F
+#define LBIST_PATCOUNT_SCAN_PC_DEF_SHIFT 0x00000000
+#define LBIST_PATCOUNT_SCAN_PC_DEF_MAX 0x0000000F
+
+#define LBIST_PATCOUNT_RESET_PC_DEF_MASK 0x000000F0
+#define LBIST_PATCOUNT_RESET_PC_DEF_SHIFT 0x00000004
+#define LBIST_PATCOUNT_RESET_PC_DEF_MAX 0x0000000F
+
+#define LBIST_PATCOUNT_SET_PC_DEF_MASK 0x00000F00
+#define LBIST_PATCOUNT_SET_PC_DEF_SHIFT 0x00000008
+#define LBIST_PATCOUNT_SET_PC_DEF_MAX 0x0000000F
+
+#define LBIST_PATCOUNT_STATIC_PC_DEF_MASK 0x3FFF0000
+#define LBIST_PATCOUNT_STATIC_PC_DEF_SHIFT 0x00000010
+#define LBIST_PATCOUNT_STATIC_PC_DEF_MAX 0x00003FFF
+
+/* LBIST_SEED0 */
+
+#define LBIST_SEED0_PRPG_DEF_MASK 0xFFFFFFFF
+#define LBIST_SEED0_PRPG_DEF_SHIFT 0x00000000
+#define LBIST_SEED0_PRPG_DEF_MAX 0xFFFFFFFF
+
+/* LBIST_SEED1 */
+
+#define LBIST_SEED1_PRPG_DEF_MASK 0x001FFFFF
+#define LBIST_SEED1_PRPG_DEF_SHIFT 0x00000000
+#define LBIST_SEED1_PRPG_DEF_MAX 0x001FFFFF
+
+/* LBIST_SPARE0 */
+
+#define LBIST_SPARE0_LBIST_SELFTEST_EN_MASK 0x00000001
+#define LBIST_SPARE0_LBIST_SELFTEST_EN_SHIFT 0x00000000
+#define LBIST_SPARE0_LBIST_SELFTEST_EN_MAX 0x00000001
+
+#define LBIST_SPARE0_PBIST_SELFTEST_EN_MASK 0x00000002
+#define LBIST_SPARE0_PBIST_SELFTEST_EN_SHIFT 0x00000001
+#define LBIST_SPARE0_PBIST_SELFTEST_EN_MAX 0x00000001
+
+#define LBIST_SPARE0_SPARE0_MASK 0xFFFFFFFC
+#define LBIST_SPARE0_SPARE0_SHIFT 0x00000002
+#define LBIST_SPARE0_SPARE0_MAX 0x3FFFFFFF
+
+/* LBIST_SPARE1 */
+
+#define LBIST_SPARE1_SPARE1_MASK 0xFFFFFFFF
+#define LBIST_SPARE1_SPARE1_SHIFT 0x00000000
+#define LBIST_SPARE1_SPARE1_MAX 0xFFFFFFFF
+
+/* LBIST_STAT */
+
+#define LBIST_STAT_MISR_MUX_CTL_MASK 0x000000FF
+#define LBIST_STAT_MISR_MUX_CTL_SHIFT 0x00000000
+#define LBIST_STAT_MISR_MUX_CTL_MAX 0x000000FF
+
+#define LBIST_STAT_OUT_MUX_CTL_MASK 0x00000300
+#define LBIST_STAT_OUT_MUX_CTL_SHIFT 0x00000008
+#define LBIST_STAT_OUT_MUX_CTL_MAX 0x00000003
+
+#define LBIST_STAT_BIST_RUNNING_MASK 0x00008000
+#define LBIST_STAT_BIST_RUNNING_SHIFT 0x0000000F
+#define LBIST_STAT_BIST_RUNNING_MAX 0x00000001
+
+#define LBIST_STAT_BIST_DONE_MASK 0x80000000
+#define LBIST_STAT_BIST_DONE_SHIFT 0x0000001F
+#define LBIST_STAT_BIST_DONE_MAX 0x00000001
+
+/* LBIST_MISR */
+
+#define LBIST_MISR_MISR_RESULT_MASK 0xFFFFFFFF
+#define LBIST_MISR_MISR_RESULT_SHIFT 0x00000000
+#define LBIST_MISR_MISR_RESULT_MAX 0xFFFFFFFF
+
+#define CTRL_MMR0_CFG0_BASE 0x00100000
+#define MAIN_CTRL_MMR_CFG0_MCU2_LBIST_CTRL 0x0000C1A0
+#define MAIN_R5F2_LBIST_BASE (CTRL_MMR0_CFG0_BASE +\
+ MAIN_CTRL_MMR_CFG0_MCU2_LBIST_CTRL)
+
+#define LBIST_CTRL 0x00000000
+#define LBIST_PATCOUNT 0x00000004
+#define LBIST_SEED0 0x00000008
+#define LBIST_SEED1 0x0000000C
+#define LBIST_SPARE0 0x00000010
+#define LBIST_SPARE1 0x00000014
+#define LBIST_STAT 0x00000018
+#define LBIST_MISR 0x0000001C
+
+#define MAIN_CTRL_MMR_CFG0_MCU2_LBIST_SIG 0x0000C2C0
+#define MAIN_R5F2_LBIST_SIG (CTRL_MMR0_CFG0_BASE +\
+ MAIN_CTRL_MMR_CFG0_MCU2_LBIST_SIG)
+#define MCU_R5FSS0_CORE0_INTR_LBIST_BIST_DONE_0 284
+
+/* Lbist Parameters */
+#define LBIST_DC_DEF 0x3
+#define LBIST_DIVIDE_RATIO 0x02
+#define LBIST_STATIC_PC_DEF 0x3ac0
+#define LBIST_RESET_PC_DEF 0x0f
+#define LBIST_SET_PC_DEF 0x00
+#define LBIST_SCAN_PC_DEF 0x04
+#define LBIST_PRPG_DEF_L 0xFFFFFFFF
+#define LBIST_PRPG_DEF_U 0x1FFFFF
+
+/*
+ * LBIST setup parameters for each core
+ */
+
+#define LBIST_MAIN_R5_STATIC_PC_DEF LBIST_STATIC_PC_DEF
+#define LBIST_C7X_STATIC_PC_DEF 0x3fc0
+#define LBIST_A72_STATIC_PC_DEF 0x3fc0
+#define LBIST_DMPAC_STATIC_PC_DEF 0x1880
+#define LBIST_VPAC_STATIC_PC_DEF 0x3fc0
+#define LBIST_A72SS_STATIC_PC_DEF 0x13c0
+
+/*
+ * LBIST expected MISR's (using parameters above)
+ */
+
+#define MAIN_R5_MISR_EXP_VAL 0x71d66f87
+#define A72_MISR_EXP_VAL 0x14df0200
+#define C7X_MISR_EXP_VAL 0x57b0478f
+#define VPAC_MISR_EXP_VAL 0xec6abe22
+#define VPAC0_MISR_EXP_VAL 0x5c43b468
+#define DMPAC_MISR_EXP_VAL 0x53e1ef7b
+#define A72SS_MISR_EXP_VAL 0x87da5a92
+
+/**
+ * lbist_set_clock_delay() - Set seed for LBIST
+ * @ctrl_mmr_base: CTRL MMR base
+ * @clock_delay: clock delay
+ *
+ * Return: 0 if all went fine, else corresponding error.
+ */
+static void lbist_set_clock_delay(void *ctrl_mmr_base, u32 clock_delay)
+{
+ u32 reg_val;
+
+ reg_val = readl(ctrl_mmr_base);
+ writel(reg_val & LBIST_CTRL_DC_DEF_MASK, ctrl_mmr_base);
+
+ reg_val = readl(ctrl_mmr_base);
+ writel(reg_val | ((clock_delay & LBIST_CTRL_DC_DEF_MAX)
+ << LBIST_CTRL_DC_DEF_SHIFT), ctrl_mmr_base);
+}
+
+/**
+ * lbist_set_seed() - Set seed for LBIST
+ * @config: lbist_config structure for LBIST test
+ * @seed: seed
+ *
+ * Return: 0 if all went fine, else corresponding error.
+ */
+static void lbist_set_seed(void *ctrl_mmr_base, u32 seed_l, u32 seed_u)
+{
+ writel(seed_l & LBIST_SEED0_PRPG_DEF_MASK, ctrl_mmr_base + LBIST_SEED0);
+ writel(seed_u & LBIST_SEED1_PRPG_DEF_MASK, ctrl_mmr_base + LBIST_SEED1);
+}
+
+/**
+ * set_num_chain_test_patterns() - Set chain test patterns
+ * @ctrl_mmr_base: CTRL MMR base
+ * @chain_test_patterns: chain test patterns
+ *
+ * Return: 0 if all went fine, else corresponding error.
+ */
+static void lbist_set_num_chain_test_patterns(void *ctrl_mmr_base, u32 chain_test_patterns)
+{
+ u32 reg_val;
+
+ reg_val = readl(ctrl_mmr_base + LBIST_PATCOUNT);
+ writel(reg_val & (~(LBIST_PATCOUNT_SCAN_PC_DEF_MASK)),
+ ctrl_mmr_base + LBIST_PATCOUNT);
+
+ reg_val = readl(ctrl_mmr_base + LBIST_PATCOUNT);
+ writel(reg_val | ((chain_test_patterns & LBIST_PATCOUNT_SCAN_PC_DEF_MAX)
+ << LBIST_PATCOUNT_SCAN_PC_DEF_SHIFT), ctrl_mmr_base + LBIST_PATCOUNT);
+}
+
+/**
+ * set_num_reset_patterns() - Set reset patterns
+ * @ctrl_mmr_base: CTRL MMR base
+ * @reset_patterns: reset patterns
+ *
+ * Return: 0 if all went fine, else corresponding error.
+ */
+static void lbist_set_num_reset_patterns(void *ctrl_mmr_base, u32 reset_patterns)
+{
+ u32 reg_val;
+
+ reg_val = readl(ctrl_mmr_base + LBIST_PATCOUNT);
+ writel(reg_val & (~(LBIST_PATCOUNT_RESET_PC_DEF_MASK)),
+ ctrl_mmr_base + LBIST_PATCOUNT);
+
+ reg_val = readl(ctrl_mmr_base + LBIST_PATCOUNT);
+ writel(reg_val | ((reset_patterns & LBIST_PATCOUNT_RESET_PC_DEF_MAX)
+ << LBIST_PATCOUNT_RESET_PC_DEF_SHIFT), ctrl_mmr_base + LBIST_PATCOUNT);
+}
+
+/**
+ * set_num_set_patterns() - Set patterns
+ * @ctrl_mmr_base: CTRL MMR base
+ * @set_patterns: set patterns
+ *
+ * Return: 0 if all went fine, else corresponding error.
+ */
+static void lbist_set_num_set_patterns(void *ctrl_mmr_base, u32 set_patterns)
+{
+ u32 reg_val;
+
+ reg_val = readl(ctrl_mmr_base + LBIST_PATCOUNT);
+ writel(reg_val & (~(LBIST_PATCOUNT_SET_PC_DEF_MASK)),
+ ctrl_mmr_base + LBIST_PATCOUNT);
+
+ reg_val = readl(ctrl_mmr_base + LBIST_PATCOUNT);
+ writel(reg_val | ((set_patterns & LBIST_PATCOUNT_RESET_PC_DEF_MAX)
+ << LBIST_PATCOUNT_SET_PC_DEF_SHIFT), ctrl_mmr_base + LBIST_PATCOUNT);
+}
+
+/**
+ * set_num_stuck_at_patterns() - Set
+ * @ctrl_mmr_base: CTRL MMR base
+ * @stuck_at_patterns: set patterns
+ *
+ * Return: 0 if all went fine, else corresponding error.
+ */
+static void lbist_set_num_stuck_at_patterns(void *ctrl_mmr_base, u32 stuck_at_patterns)
+{
+ u32 reg_val;
+
+ reg_val = readl(ctrl_mmr_base + LBIST_PATCOUNT);
+ writel(reg_val & (~(LBIST_PATCOUNT_STATIC_PC_DEF_MASK)),
+ ctrl_mmr_base + LBIST_PATCOUNT);
+
+ reg_val = readl(ctrl_mmr_base + LBIST_PATCOUNT);
+ writel(reg_val | ((stuck_at_patterns & LBIST_PATCOUNT_STATIC_PC_DEF_MAX)
+ << LBIST_PATCOUNT_STATIC_PC_DEF_SHIFT), ctrl_mmr_base + LBIST_PATCOUNT);
+}
+
+/**
+ * set_divide_ratio() - Set divide ratio
+ * @ctrl_mmr_base: CTRL MMR base
+ * @divide_ratio: divide ratio
+ *
+ * Return: 0 if all went fine, else corresponding error.
+ */
+static void lbist_set_divide_ratio(void *ctrl_mmr_base, u32 divide_ratio)
+{
+ u32 reg_val;
+
+ reg_val = readl(ctrl_mmr_base + LBIST_CTRL);
+ writel(reg_val & (~(LBIST_CTRL_DIVIDE_RATIO_MASK)), ctrl_mmr_base + LBIST_CTRL);
+
+ reg_val = readl(ctrl_mmr_base + LBIST_CTRL);
+ writel(reg_val | (divide_ratio & LBIST_CTRL_DIVIDE_RATIO_MASK),
+ ctrl_mmr_base + LBIST_CTRL);
+}
+
+/**
+ * clear_load_div() - Clear load div
+ * @ctrl_mmr_base: CTRL MMR base
+ *
+ * Return: 0 if all went fine, else corresponding error.
+ */
+static void lbist_clear_load_div(void *ctrl_mmr_base)
+{
+ u32 reg_val;
+
+ reg_val = readl(ctrl_mmr_base + LBIST_CTRL);
+ writel(reg_val & (~(LBIST_CTRL_LOAD_DIV_MASK)), ctrl_mmr_base + LBIST_CTRL);
+}
+
+/**
+ * set_load_div() - Set load div
+ * @ctrl_mmr_base: CTRL MMR base
+ *
+ * Return: 0 if all went fine, else corresponding error.
+ */
+static void lbist_set_load_div(void *ctrl_mmr_base)
+{
+ u32 reg_val;
+
+ reg_val = readl(ctrl_mmr_base + LBIST_CTRL);
+ writel(reg_val | (LBIST_CTRL_LOAD_DIV_MASK), ctrl_mmr_base + LBIST_CTRL);
+}
+
+/* MACRO DEFINES */
+#define LBIST_STAT_MISR_MUX_CTL_COMPACT_MISR 0x0
+
+#define LBIST_STAT_OUT_MUX_CTL_CTRLMMR_PID 0x0
+#define LBIST_STAT_OUT_MUX_CTL_CTRL_ID 0x1
+#define LBIST_STAT_OUT_MUX_CTL_MISR_VALUE_1 0x2
+#define LBIST_STAT_OUT_MUX_CTL_MISR_VALUE_2 0x3
+
+/**
+ * lbist_get_misr() - Get MISR
+ * @ctrl_mmr_base: CTRL MMR base
+ *
+ * Return: 0 if all went fine, else corresponding error.
+ */
+static void lbist_get_misr(void *ctrl_mmr_base, u32 *p_misr_val)
+{
+ u32 reg_val;
+ u32 mux_val;
+
+ reg_val = LBIST_STAT_MISR_MUX_CTL_COMPACT_MISR;
+ mux_val = LBIST_STAT_OUT_MUX_CTL_MISR_VALUE_1;
+ reg_val |= (mux_val << LBIST_STAT_OUT_MUX_CTL_SHIFT);
+ writel(reg_val, ctrl_mmr_base + LBIST_STAT);
+ *p_misr_val = readl(ctrl_mmr_base + LBIST_MISR);
+}
+
+/**
+ * lbist_clear_run_bist_mode() - Clear RUN_BIST_MODE
+ * @ctrl_mmr_base: CTRL MMR base
+ *
+ * Return: 0 if all went fine, else corresponding error.
+ */
+static void lbist_clear_run_bist_mode(void *ctrl_mmr_base)
+{
+ u32 reg_val;
+
+ reg_val = readl(ctrl_mmr_base + LBIST_CTRL);
+ writel(reg_val & (~(LBIST_CTRL_RUNBIST_MODE_MAX << LBIST_CTRL_RUNBIST_MODE_SHIFT)),
+ ctrl_mmr_base + LBIST_CTRL);
+}
+
+/**
+ * lbist_stop() - Stop running LBIST
+ * @ctrl_mmr_base: CTRL MMR base
+ *
+ * Return: 0 if all went fine, else corresponding error.
+ */
+static void lbist_stop(void *ctrl_mmr_base)
+{
+ u32 reg_val;
+
+ reg_val = readl(ctrl_mmr_base + LBIST_CTRL);
+ writel(reg_val & (~(LBIST_CTRL_BIST_RUN_MAX << LBIST_CTRL_BIST_RUN_SHIFT)),
+ ctrl_mmr_base + LBIST_CTRL);
+}
+
+/**
+ * lbist_reset() - Reset LBIST
+ * @ctrl_mmr_base: CTRL MMR base
+ *
+ * Return: 0 if all went fine, else corresponding error.
+ */
+static void lbist_reset(void *ctrl_mmr_base)
+{
+ u32 reg_val;
+
+ reg_val = readl(ctrl_mmr_base + LBIST_CTRL);
+ writel(reg_val & (~(LBIST_CTRL_BIST_RESET_MAX << LBIST_CTRL_BIST_RESET_SHIFT)),
+ ctrl_mmr_base + LBIST_CTRL);
+}
+
+/*
+ * struct lbist_config - Structure containing different configuration used for LBIST
+ * @dc_def: Clock delay after scan_enable switching
+ * @divide_ratio: LBIST clock divide ratio
+ * @static_pc_def: Bitmap of stuck-at patterns to run
+ * @set_pc_def: Bitmap of set patterns to run
+ * @reset_pc_def: Bitmap of reset patterns to run
+ * @scan_pc_def: Bitmap of chain test patterns to run
+ * @prpg_def: Initial seed for Pseudo Random Pattern generator (PRPG)
+ */
+struct lbist_config {
+ u32 dc_def;
+ u32 divide_ratio;
+ u32 static_pc_def;
+ u32 set_pc_def;
+ u32 reset_pc_def;
+ u32 scan_pc_def;
+ u32 prpg_def_l;
+ u32 prpg_def_u;
+};
+
+/*
+ * struct lbist_inst_info - Structure for different configuration used for LBIST
+ * @lbist_signature: Pointer to LBIST signature
+ * @intr_num: Interrupt number triggered by this LBIST instance to MCU R5 VIM
+ * @expected_misr: Expected signature
+ * @lbist_config: Configuration for LBIST test
+ */
+struct lbist_inst_info {
+ u32 *lbist_signature;
+ u32 intr_num;
+ u32 expected_misr;
+ struct lbist_config lbist_conf;
+ struct core_under_test cut;
+};
+
+#if IS_ENABLED(CONFIG_SOC_K3_J784S4)
+
+#include "k3_j784s4_bist_static_data.h"
+
+#endif /* CONFIG_SOC_K3_J784S4 */
+#endif /* __K3_BIST_STATIC_DATA_H */
diff --git a/drivers/misc/k3_j784s4_bist_static_data.h b/drivers/misc/k3_j784s4_bist_static_data.h
new file mode 100644
index 00000000000..7f9378e917f
--- /dev/null
+++ b/drivers/misc/k3_j784s4_bist_static_data.h
@@ -0,0 +1,370 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Static Data for Texas Instruments' BIST logic for J784S4
+ *
+ * Copyright (C) 2025 Texas Instruments Incorporated - https://www.ti.com/
+ *
+ */
+
+/* Device IDs of IPs that can be tested under BIST */
+#define TISCI_DEV_MCU_R5FSS2_CORE0 343
+#define TISCI_DEV_MCU_R5FSS2_CORE1 344
+#define TISCI_DEV_RTI32 365
+#define TISCI_DEV_RTI33 366
+
+/* WKUP CTRL MMR Registers */
+#define WKUP_CTRL_MMR_CFG0_WKUP_POST_STAT 0x0000C2C0
+#define WKUP_CTRL_MMR_CFG0_WKUP_POST_STAT_POST_MCU_PBIST_DONE_SHIFT 0x00000008
+#define WKUP_CTRL_MMR_CFG0_WKUP_POST_STAT_POST_MCU_LBIST_DONE_SHIFT 0x00000001
+#define WKUP_CTRL_MMR_CFG0_WKUP_POST_STAT_POST_MCU_PBIST_TIMEOUT_SHIFT 0x00000009
+#define WKUP_CTRL_MMR_CFG0_WKUP_POST_STAT_POST_MCU_LBIST_TIMEOUT_SHIFT 0x00000005
+#define WKUP_CTRL_MMR_CFG0_WKUP_POST_STAT_POST_MCU_PBIST_FAIL_MASK 0x00008000
+
+/* MCU CTRL MMR Register */
+#define MCU_CTRL_MMR0_CFG0_BASE 0x40f00000
+#define MCU_CTRL_MMR_CFG0_MCU_LBIST_CTRL 0x0000c000
+#define MCU_CTRL_MMR_CFG0_MCU_LBIST_SIG 0x0000c280
+#define MCU_LBIST_BASE (MCU_CTRL_MMR0_CFG0_BASE + \
+ MCU_CTRL_MMR_CFG0_MCU_LBIST_CTRL)
+
+/* Properties of PBIST instances in: PBIST14 */
+#define PBIST14_DEV_ID 234
+#define PBIST14_NUM_TEST_VECTORS 0x1
+#define PBIST14_ALGO_BITMAP_0 0x00000003
+#define PBIST14_MEM_BITMAP_0 0x000CCCCC
+#define PBIST14_FAIL_INSERTION_TEST_VECTOR_CA0 0x00000000
+#define PBIST14_FAIL_INSERTION_TEST_VECTOR_CA1 0x000001FF
+#define PBIST14_FAIL_INSERTION_TEST_VECTOR_CA2 0x000001FF
+#define PBIST14_FAIL_INSERTION_TEST_VECTOR_CA3 0x00000000
+#define PBIST14_FAIL_INSERTION_TEST_VECTOR_CL0 0x0000007F
+#define PBIST14_FAIL_INSERTION_TEST_VECTOR_CL1 0x00000003
+#define PBIST14_FAIL_INSERTION_TEST_VECTOR_CL2 0x00000008
+#define PBIST14_FAIL_INSERTION_TEST_VECTOR_CL3 0x000001FF
+#define PBIST14_FAIL_INSERTION_TEST_VECTOR_CMS 0x00000000
+#define PBIST14_FAIL_INSERTION_TEST_VECTOR_CSR 0x20000000
+#define PBIST14_FAIL_INSERTION_TEST_VECTOR_I0 0x00000001
+#define PBIST14_FAIL_INSERTION_TEST_VECTOR_I1 0x00000004
+#define PBIST14_FAIL_INSERTION_TEST_VECTOR_I2 0x00000008
+#define PBIST14_FAIL_INSERTION_TEST_VECTOR_I3 0x00000000
+#define PBIST14_FAIL_INSERTION_TEST_VECTOR_RAMT 0x011D2528
+
+static struct pbist_inst_info pbist14_inst_info = {
+ /* Main Pulsar 2 Instance 1 or MAIN_R52_x */
+ .num_pbist_runs = 1,
+ .intr_num = PBIST14_DFT_PBIST_CPU_0_INTR_NUM,
+ .dev_id = TISCI_DEV_PBIST14,
+ .cut = {
+ {
+ .dev_id = TISCI_DEV_R5FSS2_CORE0,
+ .proc_id = PROC_ID_MCU_R5FSS2_CORE0,
+ },
+ {
+ .dev_id = TISCI_DEV_R5FSS2_CORE1,
+ .proc_id = PROC_ID_MCU_R5FSS2_CORE1,
+ }
+ },
+ .pbist_config_run = {
+ {
+ .override = 0,
+ .algorithms_bit_map = PBIST14_ALGO_BITMAP_0,
+ .memory_groups_bit_map = PBIST14_MEM_BITMAP_0,
+ .scramble_value_lo = 0x76543210,
+ .scramble_value_hi = 0xFEDCBA98,
+ },
+ {
+ .override = 0,
+ .algorithms_bit_map = 0,
+ .memory_groups_bit_map = 0,
+ .scramble_value_lo = 0,
+ .scramble_value_hi = 0,
+ },
+ },
+ .pbist_neg_config_run = {
+ .CA0 = PBIST14_FAIL_INSERTION_TEST_VECTOR_CA0,
+ .CA1 = PBIST14_FAIL_INSERTION_TEST_VECTOR_CA1,
+ .CA2 = PBIST14_FAIL_INSERTION_TEST_VECTOR_CA2,
+ .CA3 = PBIST14_FAIL_INSERTION_TEST_VECTOR_CA3,
+ .CL0 = PBIST14_FAIL_INSERTION_TEST_VECTOR_CL0,
+ .CL1 = PBIST14_FAIL_INSERTION_TEST_VECTOR_CL1,
+ .CL2 = PBIST14_FAIL_INSERTION_TEST_VECTOR_CL2,
+ .CL3 = PBIST14_FAIL_INSERTION_TEST_VECTOR_CL3,
+ .CMS = PBIST14_FAIL_INSERTION_TEST_VECTOR_CMS,
+ .CSR = PBIST14_FAIL_INSERTION_TEST_VECTOR_CSR,
+ .I0 = PBIST14_FAIL_INSERTION_TEST_VECTOR_I0,
+ .I1 = PBIST14_FAIL_INSERTION_TEST_VECTOR_I1,
+ .I2 = PBIST14_FAIL_INSERTION_TEST_VECTOR_I2,
+ .I3 = PBIST14_FAIL_INSERTION_TEST_VECTOR_I3,
+ .RAMT = PBIST14_FAIL_INSERTION_TEST_VECTOR_RAMT
+ },
+ .num_pbist_rom_test_runs = 1,
+ .pbist_rom_test_config_run = {
+ {
+ .D = 0xF412605Eu,
+ .E = 0xF412605Eu,
+ .CA2 = 0x7FFFu,
+ .CL0 = 0x3FFu,
+ .CA3 = 0x0u,
+ .I0 = 0x1u,
+ .CL1 = 0x1Fu,
+ .I3 = 0x0u,
+ .I2 = 0xEu,
+ .CL2 = 0xEu,
+ .CA1 = 0x7FFFu,
+ .CA0 = 0x0u,
+ .CL3 = 0x7FFFu,
+ .I1 = 0x20u,
+ .RAMT = 0x08002020u,
+ .CSR = 0x00000001u,
+ .CMS = 0x01u
+ },
+ {
+ .D = 0x0u,
+ .E = 0x0u,
+ .CA2 = 0x0u,
+ .CL0 = 0x0u,
+ .CA3 = 0x0u,
+ .I0 = 0x0u,
+ .CL1 = 0x0u,
+ .I3 = 0x0u,
+ .I2 = 0x0u,
+ .CL2 = 0x0u,
+ .CA1 = 0x0u,
+ .CA0 = 0x0u,
+ .CL3 = 0x0u,
+ .I1 = 0x0u,
+ .RAMT = 0x0u,
+ .CSR = 0x0u,
+ .CMS = 0x0u
+ },
+ {
+ .D = 0x0u,
+ .E = 0x0u,
+ .CA2 = 0x0u,
+ .CL0 = 0x0u,
+ .CA3 = 0x0u,
+ .I0 = 0x0u,
+ .CL1 = 0x0u,
+ .I3 = 0x0u,
+ .I2 = 0x0u,
+ .CL2 = 0x0u,
+ .CA1 = 0x0u,
+ .CA0 = 0x0u,
+ .CL3 = 0x0u,
+ .I1 = 0x0u,
+ .RAMT = 0x0u,
+ .CSR = 0x0u,
+ .CMS = 0x0u
+ },
+ {
+ .D = 0x0u,
+ .E = 0x0u,
+ .CA2 = 0x0u,
+ .CL0 = 0x0u,
+ .CA3 = 0x0u,
+ .I0 = 0x0u,
+ .CL1 = 0x0u,
+ .I3 = 0x0u,
+ .I2 = 0x0u,
+ .CL2 = 0x0u,
+ .CA1 = 0x0u,
+ .CA0 = 0x0u,
+ .CL3 = 0x0u,
+ .I1 = 0x0u,
+ .RAMT = 0x0u,
+ .CSR = 0x0u,
+ .CMS = 0x0u
+ },
+ {
+ .D = 0x0u,
+ .E = 0x0u,
+ .CA2 = 0x0u,
+ .CL0 = 0x0u,
+ .CA3 = 0x0u,
+ .I0 = 0x0u,
+ .CL1 = 0x0u,
+ .I3 = 0x0u,
+ .I2 = 0x0u,
+ .CL2 = 0x0u,
+ .CA1 = 0x0u,
+ .CA0 = 0x0u,
+ .CL3 = 0x0u,
+ .I1 = 0x0u,
+ .RAMT = 0x0u,
+ .CSR = 0x0u,
+ .CMS = 0x0u
+ },
+ {
+ .D = 0x0u,
+ .E = 0x0u,
+ .CA2 = 0x0u,
+ .CL0 = 0x0u,
+ .CA3 = 0x0u,
+ .I0 = 0x0u,
+ .CL1 = 0x0u,
+ .I3 = 0x0u,
+ .I2 = 0x0u,
+ .CL2 = 0x0u,
+ .CA1 = 0x0u,
+ .CA0 = 0x0u,
+ .CL3 = 0x0u,
+ .I1 = 0x0u,
+ .RAMT = 0x0u,
+ .CSR = 0x0u,
+ .CMS = 0x0u
+ },
+ {
+ .D = 0x0u,
+ .E = 0x0u,
+ .CA2 = 0x0u,
+ .CL0 = 0x0u,
+ .CA3 = 0x0u,
+ .I0 = 0x0u,
+ .CL1 = 0x0u,
+ .I3 = 0x0u,
+ .I2 = 0x0u,
+ .CL2 = 0x0u,
+ .CA1 = 0x0u,
+ .CA0 = 0x0u,
+ .CL3 = 0x0u,
+ .I1 = 0x0u,
+ .RAMT = 0x0u,
+ .CSR = 0x0u,
+ .CMS = 0x0u
+ },
+ {
+ .D = 0x0u,
+ .E = 0x0u,
+ .CA2 = 0x0u,
+ .CL0 = 0x0u,
+ .CA3 = 0x0u,
+ .I0 = 0x0u,
+ .CL1 = 0x0u,
+ .I3 = 0x0u,
+ .I2 = 0x0u,
+ .CL2 = 0x0u,
+ .CA1 = 0x0u,
+ .CA0 = 0x0u,
+ .CL3 = 0x0u,
+ .I1 = 0x0u,
+ .RAMT = 0x0u,
+ .CSR = 0x0u,
+ .CMS = 0x0u
+ },
+ {
+ .D = 0x0u,
+ .E = 0x0u,
+ .CA2 = 0x0u,
+ .CL0 = 0x0u,
+ .CA3 = 0x0u,
+ .I0 = 0x0u,
+ .CL1 = 0x0u,
+ .I3 = 0x0u,
+ .I2 = 0x0u,
+ .CL2 = 0x0u,
+ .CA1 = 0x0u,
+ .CA0 = 0x0u,
+ .CL3 = 0x0u,
+ .I1 = 0x0u,
+ .RAMT = 0x0u,
+ .CSR = 0x0u,
+ .CMS = 0x0u
+ },
+ {
+ .D = 0x0u,
+ .E = 0x0u,
+ .CA2 = 0x0u,
+ .CL0 = 0x0u,
+ .CA3 = 0x0u,
+ .I0 = 0x0u,
+ .CL1 = 0x0u,
+ .I3 = 0x0u,
+ .I2 = 0x0u,
+ .CL2 = 0x0u,
+ .CA1 = 0x0u,
+ .CA0 = 0x0u,
+ .CL3 = 0x0u,
+ .I1 = 0x0u,
+ .RAMT = 0x0u,
+ .CSR = 0x0u,
+ .CMS = 0x0u
+ },
+ {
+ .D = 0x0u,
+ .E = 0x0u,
+ .CA2 = 0x0u,
+ .CL0 = 0x0u,
+ .CA3 = 0x0u,
+ .I0 = 0x0u,
+ .CL1 = 0x0u,
+ .I3 = 0x0u,
+ .I2 = 0x0u,
+ .CL2 = 0x0u,
+ .CA1 = 0x0u,
+ .CA0 = 0x0u,
+ .CL3 = 0x0u,
+ .I1 = 0x0u,
+ .RAMT = 0x0u,
+ .CSR = 0x0u,
+ .CMS = 0x0u
+ },
+ {
+ .D = 0x0u,
+ .E = 0x0u,
+ .CA2 = 0x0u,
+ .CL0 = 0x0u,
+ .CA3 = 0x0u,
+ .I0 = 0x0u,
+ .CL1 = 0x0u,
+ .I3 = 0x0u,
+ .I2 = 0x0u,
+ .CL2 = 0x0u,
+ .CA1 = 0x0u,
+ .CA0 = 0x0u,
+ .CL3 = 0x0u,
+ .I1 = 0x0u,
+ .RAMT = 0x0u,
+ .CSR = 0x0u,
+ .CMS = 0x0u
+ },
+ {
+ .D = 0x0u,
+ .E = 0x0u,
+ .CA2 = 0x0u,
+ .CL0 = 0x0u,
+ .CA3 = 0x0u,
+ .I0 = 0x0u,
+ .CL1 = 0x0u,
+ .I3 = 0x0u,
+ .I2 = 0x0u,
+ .CL2 = 0x0u,
+ .CA1 = 0x0u,
+ .CA0 = 0x0u,
+ .CL3 = 0x0u,
+ .I1 = 0x0u,
+ .RAMT = 0x0u,
+ .CSR = 0x0u,
+ .CMS = 0x0u
+ },
+ },
+};
+
+static struct lbist_inst_info lbist_inst_info_main_r5f2_x = {
+ /* Main Pulsar 2 Instance 1 or MAIN_R52_x */
+ .lbist_signature = (u32 *)(MAIN_R5F2_LBIST_SIG),
+ .intr_num = MCU_R5FSS0_CORE0_INTR_LBIST_BIST_DONE_0,
+ .expected_misr = MAIN_R5_MISR_EXP_VAL,
+ .lbist_conf = {
+ .dc_def = LBIST_DC_DEF,
+ .divide_ratio = LBIST_DIVIDE_RATIO,
+ .static_pc_def = LBIST_MAIN_R5_STATIC_PC_DEF,
+ .set_pc_def = LBIST_SET_PC_DEF,
+ .reset_pc_def = LBIST_RESET_PC_DEF,
+ .scan_pc_def = LBIST_SCAN_PC_DEF,
+ .prpg_def_l = LBIST_PRPG_DEF_L,
+ .prpg_def_u = LBIST_PRPG_DEF_U,
+ },
+ .cut = {
+ .dev_id = TISCI_DEV_R5FSS2_CORE0,
+ .proc_id = PROC_ID_MCU_R5FSS2_CORE0,
+ },
+};
diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index d3fe90d939e..c297fa03ea7 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -259,6 +259,15 @@ config MT76X8_USB_PHY
This PHY is found on MT76x8 devices supporting USB.
+config PHY_EXYNOS_USBDRD
+ bool "Exynos SoC series USB DRD PHY driver"
+ depends on PHY && CLK
+ depends on ARCH_EXYNOS
+ select REGMAP
+ select SYSCON
+ help
+ Enable USB DRD PHY support for Exynos SoC series.
+
config PHY_MTK_TPHY
bool "MediaTek T-PHY Driver"
depends on PHY
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index b4d01fc700d..98c1ef8683b 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -35,6 +35,7 @@ obj-$(CONFIG_KEYSTONE_USB_PHY) += keystone-usb-phy.o
obj-$(CONFIG_MT7620_USB_PHY) += mt7620-usb-phy.o
obj-$(CONFIG_MT76X8_USB_PHY) += mt76x8-usb-phy.o
obj-$(CONFIG_PHY_DA8XX_USB) += phy-da8xx-usb.o
+obj-$(CONFIG_PHY_EXYNOS_USBDRD) += phy-exynos-usbdrd.o
obj-$(CONFIG_PHY_MTK_TPHY) += phy-mtk-tphy.o
obj-$(CONFIG_PHY_NPCM_USB) += phy-npcm-usb.o
obj-$(CONFIG_PHY_IMX8MQ_USB) += phy-imx8mq-usb.o
diff --git a/drivers/phy/phy-exynos-usbdrd.c b/drivers/phy/phy-exynos-usbdrd.c
new file mode 100644
index 00000000000..db5815ed184
--- /dev/null
+++ b/drivers/phy/phy-exynos-usbdrd.c
@@ -0,0 +1,386 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2025 Linaro Ltd.
+ * Sam Protsenko <semen.protsenko@linaro.org>
+ *
+ * Samsung Exynos SoC series USB DRD PHY driver.
+ * Based on Linux kernel PHY driver: drivers/phy/samsung/phy-exynos5-usbdrd.c
+ */
+
+#include <clk.h>
+#include <dm.h>
+#include <generic-phy.h>
+#include <regmap.h>
+#include <syscon.h>
+#include <asm/io.h>
+#include <dm/device_compat.h>
+#include <linux/bitfield.h>
+#include <linux/bitops.h>
+#include <linux/delay.h>
+
+/* Offset of PMU register controlling USB PHY output isolation */
+#define EXYNOS_USBDRD_PHY_CONTROL 0x0704
+#define EXYNOS_PHY_ENABLE BIT(0)
+
+/* Exynos USB PHY registers */
+#define EXYNOS5_FSEL_9MHZ6 0x0
+#define EXYNOS5_FSEL_10MHZ 0x1
+#define EXYNOS5_FSEL_12MHZ 0x2
+#define EXYNOS5_FSEL_19MHZ2 0x3
+#define EXYNOS5_FSEL_20MHZ 0x4
+#define EXYNOS5_FSEL_24MHZ 0x5
+#define EXYNOS5_FSEL_26MHZ 0x6
+#define EXYNOS5_FSEL_50MHZ 0x7
+
+/* Exynos850: USB DRD PHY registers */
+#define EXYNOS850_DRD_LINKCTRL 0x04
+#define LINKCTRL_FORCE_QACT BIT(8)
+#define LINKCTRL_BUS_FILTER_BYPASS GENMASK(7, 4)
+
+#define EXYNOS850_DRD_CLKRST 0x20
+#define CLKRST_LINK_SW_RST BIT(0)
+#define CLKRST_PORT_RST BIT(1)
+#define CLKRST_PHY_SW_RST BIT(3)
+
+#define EXYNOS850_DRD_SSPPLLCTL 0x30
+#define SSPPLLCTL_FSEL GENMASK(2, 0)
+
+#define EXYNOS850_DRD_UTMI 0x50
+#define UTMI_FORCE_SLEEP BIT(0)
+#define UTMI_FORCE_SUSPEND BIT(1)
+#define UTMI_DM_PULLDOWN BIT(2)
+#define UTMI_DP_PULLDOWN BIT(3)
+#define UTMI_FORCE_BVALID BIT(4)
+#define UTMI_FORCE_VBUSVALID BIT(5)
+
+#define EXYNOS850_DRD_HSP 0x54
+#define HSP_COMMONONN BIT(8)
+#define HSP_EN_UTMISUSPEND BIT(9)
+#define HSP_VBUSVLDEXT BIT(12)
+#define HSP_VBUSVLDEXTSEL BIT(13)
+#define HSP_FSV_OUT_EN BIT(24)
+
+#define EXYNOS850_DRD_HSP_TEST 0x5c
+#define HSP_TEST_SIDDQ BIT(24)
+
+#define KHZ 1000
+#define MHZ (KHZ * KHZ)
+
+/**
+ * struct exynos_usbdrd_phy - driver data for Exynos USB PHY
+ * @reg_phy: USB PHY controller register memory base
+ * @clk: clock for register access
+ * @core_clk: core clock for phy (ref clock)
+ * @reg_pmu: regmap for PMU block
+ * @extrefclk: frequency select settings when using 'separate reference clocks'
+ */
+struct exynos_usbdrd_phy {
+ void __iomem *reg_phy;
+ struct clk *clk;
+ struct clk *core_clk;
+ struct regmap *reg_pmu;
+ u32 extrefclk;
+};
+
+static void exynos_usbdrd_phy_isol(struct regmap *reg_pmu, bool isolate)
+{
+ unsigned int val;
+
+ if (!reg_pmu)
+ return;
+
+ val = isolate ? 0 : EXYNOS_PHY_ENABLE;
+ regmap_update_bits(reg_pmu, EXYNOS_USBDRD_PHY_CONTROL,
+ EXYNOS_PHY_ENABLE, val);
+}
+
+/*
+ * Convert the supplied clock rate to the value that can be written to the PHY
+ * register.
+ */
+static unsigned int exynos_rate_to_clk(unsigned long rate, u32 *reg)
+{
+ switch (rate) {
+ case 9600 * KHZ:
+ *reg = EXYNOS5_FSEL_9MHZ6;
+ break;
+ case 10 * MHZ:
+ *reg = EXYNOS5_FSEL_10MHZ;
+ break;
+ case 12 * MHZ:
+ *reg = EXYNOS5_FSEL_12MHZ;
+ break;
+ case 19200 * KHZ:
+ *reg = EXYNOS5_FSEL_19MHZ2;
+ break;
+ case 20 * MHZ:
+ *reg = EXYNOS5_FSEL_20MHZ;
+ break;
+ case 24 * MHZ:
+ *reg = EXYNOS5_FSEL_24MHZ;
+ break;
+ case 26 * MHZ:
+ *reg = EXYNOS5_FSEL_26MHZ;
+ break;
+ case 50 * MHZ:
+ *reg = EXYNOS5_FSEL_50MHZ;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static void exynos850_usbdrd_utmi_init(struct phy *phy)
+{
+ struct exynos_usbdrd_phy *phy_drd = dev_get_priv(phy->dev);
+ void __iomem *regs_base = phy_drd->reg_phy;
+ u32 reg;
+
+ /*
+ * Disable HWACG (hardware auto clock gating control). This will force
+ * QACTIVE signal in Q-Channel interface to HIGH level, to make sure
+ * the PHY clock is not gated by the hardware.
+ */
+ reg = readl(regs_base + EXYNOS850_DRD_LINKCTRL);
+ reg |= LINKCTRL_FORCE_QACT;
+ writel(reg, regs_base + EXYNOS850_DRD_LINKCTRL);
+
+ /* Start PHY Reset (POR=high) */
+ reg = readl(regs_base + EXYNOS850_DRD_CLKRST);
+ reg |= CLKRST_PHY_SW_RST;
+ writel(reg, regs_base + EXYNOS850_DRD_CLKRST);
+
+ /* Enable UTMI+ */
+ reg = readl(regs_base + EXYNOS850_DRD_UTMI);
+ reg &= ~(UTMI_FORCE_SUSPEND | UTMI_FORCE_SLEEP | UTMI_DP_PULLDOWN |
+ UTMI_DM_PULLDOWN);
+ writel(reg, regs_base + EXYNOS850_DRD_UTMI);
+
+ /* Set PHY clock and control HS PHY */
+ reg = readl(regs_base + EXYNOS850_DRD_HSP);
+ reg |= HSP_EN_UTMISUSPEND | HSP_COMMONONN;
+ writel(reg, regs_base + EXYNOS850_DRD_HSP);
+
+ /* Set VBUS Valid and D+ pull-up control by VBUS pad usage */
+ reg = readl(regs_base + EXYNOS850_DRD_LINKCTRL);
+ reg |= FIELD_PREP(LINKCTRL_BUS_FILTER_BYPASS, 0xf);
+ writel(reg, regs_base + EXYNOS850_DRD_LINKCTRL);
+
+ reg = readl(regs_base + EXYNOS850_DRD_UTMI);
+ reg |= UTMI_FORCE_BVALID | UTMI_FORCE_VBUSVALID;
+ writel(reg, regs_base + EXYNOS850_DRD_UTMI);
+
+ reg = readl(regs_base + EXYNOS850_DRD_HSP);
+ reg |= HSP_VBUSVLDEXT | HSP_VBUSVLDEXTSEL;
+ writel(reg, regs_base + EXYNOS850_DRD_HSP);
+
+ reg = readl(regs_base + EXYNOS850_DRD_SSPPLLCTL);
+ reg &= ~SSPPLLCTL_FSEL;
+ switch (phy_drd->extrefclk) {
+ case EXYNOS5_FSEL_50MHZ:
+ reg |= FIELD_PREP(SSPPLLCTL_FSEL, 7);
+ break;
+ case EXYNOS5_FSEL_26MHZ:
+ reg |= FIELD_PREP(SSPPLLCTL_FSEL, 6);
+ break;
+ case EXYNOS5_FSEL_24MHZ:
+ reg |= FIELD_PREP(SSPPLLCTL_FSEL, 2);
+ break;
+ case EXYNOS5_FSEL_20MHZ:
+ reg |= FIELD_PREP(SSPPLLCTL_FSEL, 1);
+ break;
+ case EXYNOS5_FSEL_19MHZ2:
+ reg |= FIELD_PREP(SSPPLLCTL_FSEL, 0);
+ break;
+ default:
+ dev_warn(phy->dev, "unsupported ref clk: %#.2x\n",
+ phy_drd->extrefclk);
+ break;
+ }
+ writel(reg, regs_base + EXYNOS850_DRD_SSPPLLCTL);
+
+ /* Power up PHY analog blocks */
+ reg = readl(regs_base + EXYNOS850_DRD_HSP_TEST);
+ reg &= ~HSP_TEST_SIDDQ;
+ writel(reg, regs_base + EXYNOS850_DRD_HSP_TEST);
+
+ /* Finish PHY reset (POR=low) */
+ udelay(10); /* required before doing POR=low */
+ reg = readl(regs_base + EXYNOS850_DRD_CLKRST);
+ reg &= ~(CLKRST_PHY_SW_RST | CLKRST_PORT_RST);
+ writel(reg, regs_base + EXYNOS850_DRD_CLKRST);
+ udelay(75); /* required after POR=low for guaranteed PHY clock */
+
+ /* Disable single ended signal out */
+ reg = readl(regs_base + EXYNOS850_DRD_HSP);
+ reg &= ~HSP_FSV_OUT_EN;
+ writel(reg, regs_base + EXYNOS850_DRD_HSP);
+}
+
+static void exynos850_usbdrd_utmi_exit(struct phy *phy)
+{
+ struct exynos_usbdrd_phy *phy_drd = dev_get_priv(phy->dev);
+ void __iomem *regs_base = phy_drd->reg_phy;
+ u32 reg;
+
+ /* Set PHY clock and control HS PHY */
+ reg = readl(regs_base + EXYNOS850_DRD_UTMI);
+ reg &= ~(UTMI_DP_PULLDOWN | UTMI_DM_PULLDOWN);
+ reg |= UTMI_FORCE_SUSPEND | UTMI_FORCE_SLEEP;
+ writel(reg, regs_base + EXYNOS850_DRD_UTMI);
+
+ /* Power down PHY analog blocks */
+ reg = readl(regs_base + EXYNOS850_DRD_HSP_TEST);
+ reg |= HSP_TEST_SIDDQ;
+ writel(reg, regs_base + EXYNOS850_DRD_HSP_TEST);
+
+ /* Link reset */
+ reg = readl(regs_base + EXYNOS850_DRD_CLKRST);
+ reg |= CLKRST_LINK_SW_RST;
+ writel(reg, regs_base + EXYNOS850_DRD_CLKRST);
+ udelay(10); /* required before doing POR=low */
+ reg &= ~CLKRST_LINK_SW_RST;
+ writel(reg, regs_base + EXYNOS850_DRD_CLKRST);
+}
+
+static int exynos_usbdrd_phy_init(struct phy *phy)
+{
+ struct exynos_usbdrd_phy *phy_drd = dev_get_priv(phy->dev);
+ int ret;
+
+ ret = clk_prepare_enable(phy_drd->clk);
+ if (ret)
+ return ret;
+
+ exynos850_usbdrd_utmi_init(phy);
+
+ clk_disable_unprepare(phy_drd->clk);
+
+ return 0;
+}
+
+static int exynos_usbdrd_phy_exit(struct phy *phy)
+{
+ struct exynos_usbdrd_phy *phy_drd = dev_get_priv(phy->dev);
+ int ret;
+
+ ret = clk_prepare_enable(phy_drd->clk);
+ if (ret)
+ return ret;
+
+ exynos850_usbdrd_utmi_exit(phy);
+
+ clk_disable_unprepare(phy_drd->clk);
+
+ return 0;
+}
+
+static int exynos_usbdrd_phy_power_on(struct phy *phy)
+{
+ struct exynos_usbdrd_phy *phy_drd = dev_get_priv(phy->dev);
+ int ret;
+
+ dev_dbg(phy->dev, "Request to power_on usbdrd_phy phy\n");
+
+ ret = clk_prepare_enable(phy_drd->core_clk);
+ if (ret)
+ return ret;
+
+ /* Power-on PHY */
+ exynos_usbdrd_phy_isol(phy_drd->reg_pmu, false);
+
+ return 0;
+}
+
+static int exynos_usbdrd_phy_power_off(struct phy *phy)
+{
+ struct exynos_usbdrd_phy *phy_drd = dev_get_priv(phy->dev);
+
+ dev_dbg(phy->dev, "Request to power_off usbdrd_phy phy\n");
+
+ /* Power-off the PHY */
+ exynos_usbdrd_phy_isol(phy_drd->reg_pmu, true);
+
+ clk_disable_unprepare(phy_drd->core_clk);
+
+ return 0;
+}
+
+static int exynos_usbdrd_phy_init_clk(struct udevice *dev)
+{
+ struct exynos_usbdrd_phy *phy_drd = dev_get_priv(dev);
+ unsigned long ref_rate;
+ int err;
+
+ phy_drd->clk = devm_clk_get(dev, "phy");
+ if (IS_ERR(phy_drd->clk)) {
+ err = PTR_ERR(phy_drd->clk);
+ dev_err(dev, "Failed to get phy clock (err=%d)\n", err);
+ return err;
+ }
+
+ phy_drd->core_clk = devm_clk_get(dev, "ref");
+ if (IS_ERR(phy_drd->core_clk)) {
+ err = PTR_ERR(phy_drd->core_clk);
+ dev_err(dev, "Failed to get ref clock (err=%d)\n", err);
+ return err;
+ }
+
+ ref_rate = clk_get_rate(phy_drd->core_clk);
+ err = exynos_rate_to_clk(ref_rate, &phy_drd->extrefclk);
+ if (err) {
+ dev_err(dev, "Clock rate %lu not supported\n", ref_rate);
+ return err;
+ }
+
+ return 0;
+}
+
+static int exynos_usbdrd_phy_probe(struct udevice *dev)
+{
+ struct exynos_usbdrd_phy *phy_drd = dev_get_priv(dev);
+ int err;
+
+ phy_drd->reg_phy = dev_read_addr_ptr(dev);
+ if (!phy_drd->reg_phy)
+ return -EINVAL;
+
+ err = exynos_usbdrd_phy_init_clk(dev);
+ if (err)
+ return err;
+
+ phy_drd->reg_pmu = syscon_regmap_lookup_by_phandle(dev,
+ "samsung,pmu-syscon");
+ if (IS_ERR(phy_drd->reg_pmu)) {
+ err = PTR_ERR(phy_drd->reg_pmu);
+ dev_err(dev, "Failed to lookup PMU regmap\n");
+ return err;
+ }
+
+ return 0;
+}
+
+static const struct phy_ops exynos_usbdrd_phy_ops = {
+ .init = exynos_usbdrd_phy_init,
+ .exit = exynos_usbdrd_phy_exit,
+ .power_on = exynos_usbdrd_phy_power_on,
+ .power_off = exynos_usbdrd_phy_power_off,
+};
+
+static const struct udevice_id exynos_usbdrd_phy_of_match[] = {
+ {
+ .compatible = "samsung,exynos850-usbdrd-phy",
+ },
+ { }
+};
+
+U_BOOT_DRIVER(exynos_usbdrd_phy) = {
+ .name = "exynos-usbdrd-phy",
+ .id = UCLASS_PHY,
+ .of_match = exynos_usbdrd_phy_of_match,
+ .probe = exynos_usbdrd_phy_probe,
+ .ops = &exynos_usbdrd_phy_ops,
+ .priv_auto = sizeof(struct exynos_usbdrd_phy),
+};
diff --git a/drivers/power/domain/imx8m-power-domain.c b/drivers/power/domain/imx8m-power-domain.c
index b44aae78e6d..a7e64971a2a 100644
--- a/drivers/power/domain/imx8m-power-domain.c
+++ b/drivers/power/domain/imx8m-power-domain.c
@@ -468,6 +468,8 @@ out_clk_disable:
static int imx8m_power_domain_of_xlate(struct power_domain *power_domain,
struct ofnode_phandle_args *args)
{
+ power_domain->id = 0;
+
return 0;
}
diff --git a/drivers/usb/dwc3/dwc3-generic.c b/drivers/usb/dwc3/dwc3-generic.c
index 21452ad1569..3cda2b74b7e 100644
--- a/drivers/usb/dwc3/dwc3-generic.c
+++ b/drivers/usb/dwc3/dwc3-generic.c
@@ -704,6 +704,7 @@ static const struct udevice_id dwc3_glue_ids[] = {
{ .compatible = "fsl,imx8mp-dwc3", .data = (ulong)&imx8mp_ops },
{ .compatible = "fsl,imx8mq-dwc3" },
{ .compatible = "intel,tangier-dwc3" },
+ { .compatible = "samsung,exynos850-dwusb3" },
{ }
};
diff --git a/include/configs/e850-96.h b/include/configs/e850-96.h
index 4607b3089b2..63e85332bd8 100644
--- a/include/configs/e850-96.h
+++ b/include/configs/e850-96.h
@@ -9,4 +9,25 @@
#ifndef __E850_96_H
#define __E850_96_H
+/* GUIDs for capsule updatable firmware images */
+#define E850_96_FWBL1_IMAGE_GUID \
+ EFI_GUID(0x181cd3f2, 0xe375, 0x44d2, 0x80, 0x78, \
+ 0x32, 0x21, 0xe1, 0xdf, 0xb9, 0x5e)
+
+#define E850_96_EPBL_IMAGE_GUID \
+ EFI_GUID(0x66c1a54d, 0xd149, 0x415d, 0xaa, 0xda, \
+ 0xb8, 0xae, 0xe4, 0x99, 0xb3, 0x70)
+
+#define E850_96_BL2_IMAGE_GUID \
+ EFI_GUID(0x89471c2a, 0x6c8d, 0x4158, 0xac, 0xad, \
+ 0x23, 0xd3, 0xb2, 0x87, 0x3d, 0x35)
+
+#define E850_96_BOOTLOADER_IMAGE_GUID \
+ EFI_GUID(0x629578c3, 0xffb3, 0x4a89, 0xac, 0x0c, \
+ 0x61, 0x18, 0x40, 0x72, 0x77, 0x79)
+
+#define E850_96_EL3_MON_IMAGE_GUID \
+ EFI_GUID(0xdf5718a2, 0x930a, 0x4916, 0xbb, 0x19, \
+ 0x32, 0x13, 0x21, 0x4d, 0x84, 0x86)
+
#endif /* __E850_96_H */
diff --git a/include/configs/imx93_evk.h b/include/configs/imx93_evk.h
index 94355cf61e4..e7db0161126 100644
--- a/include/configs/imx93_evk.h
+++ b/include/configs/imx93_evk.h
@@ -6,8 +6,6 @@
#ifndef __IMX93_EVK_H
#define __IMX93_EVK_H
-#include <linux/sizes.h>
-#include <linux/stringify.h>
#include <asm/arch/imx-regs.h>
#define CFG_SYS_UBOOT_BASE \
diff --git a/include/configs/imx93_frdm.h b/include/configs/imx93_frdm.h
new file mode 100644
index 00000000000..987fcacb999
--- /dev/null
+++ b/include/configs/imx93_frdm.h
@@ -0,0 +1,30 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2025 NXP
+ */
+
+#ifndef __IMX93_FRDM_H
+#define __IMX93_FRDM_H
+
+#include <asm/arch/imx-regs.h>
+
+#define CFG_SYS_UBOOT_BASE \
+ (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
+
+#ifdef CONFIG_XPL_BUILD
+#define CFG_MALLOC_F_ADDR 0x204D0000
+#endif
+
+/* Link Definitions */
+
+#define CFG_SYS_INIT_RAM_ADDR 0x80000000
+#define CFG_SYS_INIT_RAM_SIZE 0x200000
+
+#define CFG_SYS_SDRAM_BASE 0x80000000
+#define PHYS_SDRAM 0x80000000
+#define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */
+
+/* Using ULP WDOG for reset */
+#define WDOG_BASE_ADDR WDG3_BASE_ADDR
+
+#endif
diff --git a/include/k3_bist.h b/include/k3_bist.h
new file mode 100644
index 00000000000..cc650f5a8c4
--- /dev/null
+++ b/include/k3_bist.h
@@ -0,0 +1,44 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Texas Instruments' BIST (Built-In Self-Test) driver
+ *
+ * Copyright (C) 2025 Texas Instruments Incorporated - https://www.ti.com/
+ * Neha Malcom Francis <n-francis@ti.com>
+ *
+ */
+
+#ifndef _INCLUDE_BIST_H_
+#define _INCLUDE_BIST_H_
+
+#define PROC_BOOT_CTRL_FLAG_R5_CORE_HALT 0x00000001
+#define PROC_ID_MCU_R5FSS2_CORE0 0x0A
+#define PROC_ID_MCU_R5FSS2_CORE1 0x0B
+#define PROC_BOOT_CTRL_FLAG_R5_LPSC 0x00000002
+
+#define TISCI_DEV_PBIST14 237
+#define TISCI_DEV_R5FSS2_CORE0 343
+#define TISCI_DEV_R5FSS2_CORE1 344
+
+#define TISCI_MSG_VALUE_DEVICE_SW_STATE_AUTO_OFF 0
+#define TISCI_MSG_VALUE_DEVICE_SW_STATE_RETENTION 1
+#define TISCI_MSG_VALUE_DEVICE_SW_STATE_ON 2
+
+#define TISCI_BIT(n) ((1) << (n))
+
+struct bist_ops {
+ int (*run_lbist)(void);
+ int (*run_lbist_post)(void);
+ int (*run_pbist_post)(void);
+ int (*run_pbist_neg)(void);
+ int (*run_pbist_rom)(void);
+ int (*run_pbist)(void);
+};
+
+void lbist_enable_isolation(void);
+void lbist_disable_isolation(void);
+int prepare_pbist(struct ti_sci_handle *handle);
+int deprepare_pbist(struct ti_sci_handle *handle);
+int prepare_lbist(struct ti_sci_handle *handle);
+int deprepare_lbist(struct ti_sci_handle *handle);
+
+#endif /* _INCLUDE_BIST_H_ */