diff options
75 files changed, 1782 insertions, 2063 deletions
diff --git a/MAINTAINERS b/MAINTAINERS index 795ff2328dd..cae855da60e 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -732,7 +732,6 @@ F: include/dt-bindings/clock/stm32fx-clock.h F: include/dt-bindings/clock/stm32mp* F: include/dt-bindings/pinctrl/stm32-pinfunc.h F: include/dt-bindings/reset/stm32mp* -F: include/stm32-reset-core.h F: include/stm32_rcc.h F: tools/logos/st.bmp F: tools/stm32image.c @@ -2131,6 +2131,11 @@ $(filter-out tools, $(u-boot-dirs)): tools # is "yes"), so compile examples after U-Boot is compiled. examples: $(filter-out examples, $(u-boot-dirs)) +ifeq ($(CONFIG_USE_PRIVATE_LIBGCC),y) +# lib/efi_loader apps depend on arch/$(ARCH)/lib for lib.a +lib: $(filter arch/$(ARCH)/lib, $(u-boot-dirs)) +endif + # The setlocalversion script comes from linux and expects a # KERNELVERSION variable in the environment for figuring out which # annotated tags are relevant. Pass UBOOTVERSION. diff --git a/arch/arm/cpu/armv7/bcm281xx/Makefile b/arch/arm/cpu/armv7/bcm281xx/Makefile index e5099975cba..f6323af1d06 100644 --- a/arch/arm/cpu/armv7/bcm281xx/Makefile +++ b/arch/arm/cpu/armv7/bcm281xx/Makefile @@ -7,5 +7,4 @@ obj-y += clk-core.o obj-y += clk-bcm281xx.o obj-y += clk-sdio.o obj-y += clk-bsc.o -obj-$(CONFIG_BCM_SF2_ETH) += clk-eth.o obj-y += clk-usb-otg.o diff --git a/arch/arm/cpu/armv7/bcm281xx/clk-bcm281xx.c b/arch/arm/cpu/armv7/bcm281xx/clk-bcm281xx.c index b258fea45c8..39eb2ca01dc 100644 --- a/arch/arm/cpu/armv7/bcm281xx/clk-bcm281xx.c +++ b/arch/arm/cpu/armv7/bcm281xx/clk-bcm281xx.c @@ -307,27 +307,6 @@ static struct ccu_clock kps_ccu_clk = { .freq_tbl = slave_axi_freq_tbl, }; -#ifdef CONFIG_BCM_SF2_ETH -static struct ccu_clock esub_ccu_clk = { - .clk = { - .name = "esub_ccu_clk", - .ops = &ccu_clk_ops, - .ccu_clk_mgr_base = ESUB_CLK_BASE_ADDR, - }, - .num_policy_masks = 1, - .policy_freq_offset = 0x00000008, - .freq_bit_shift = 8, - .policy_ctl_offset = 0x0000000c, - .policy0_mask_offset = 0x00000010, - .policy1_mask_offset = 0x00000014, - .policy2_mask_offset = 0x00000018, - .policy3_mask_offset = 0x0000001c, - .lvm_en_offset = 0x00000034, - .freq_id = 2, - .freq_tbl = esub_freq_tbl, -}; -#endif - /* * Bus clocks */ @@ -562,9 +541,6 @@ struct clk_lookup arch_clk_tbl[] = { CLK_LK(bsc1_apb), CLK_LK(bsc2_apb), CLK_LK(bsc3_apb), -#ifdef CONFIG_BCM_SF2_ETH - CLK_LK(esub_ccu), -#endif }; /* public array size */ diff --git a/arch/arm/cpu/armv7/bcm281xx/clk-eth.c b/arch/arm/cpu/armv7/bcm281xx/clk-eth.c deleted file mode 100644 index 5f7cc4a102d..00000000000 --- a/arch/arm/cpu/armv7/bcm281xx/clk-eth.c +++ /dev/null @@ -1,142 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2014 Broadcom Corporation. - */ - -#include <asm/io.h> -#include <linux/delay.h> -#include <linux/errno.h> -#include <asm/arch/sysmap.h> -#include <asm/kona-common/clk.h> -#include "clk-core.h" - -#define WR_ACCESS_ADDR ESUB_CLK_BASE_ADDR -#define WR_ACCESS_PASSWORD 0xA5A500 - -#define PLLE_POST_RESETB_ADDR (ESUB_CLK_BASE_ADDR + 0x00000C00) - -#define PLLE_RESETB_ADDR (ESUB_CLK_BASE_ADDR + 0x00000C58) -#define PLLE_RESETB_I_PLL_RESETB_PLLE_MASK 0x00010000 -#define PLLE_POST_RESETB_I_POST_RESETB_PLLE_MASK 0x00000001 - -#define PLL_LOCK_ADDR (ESUB_CLK_BASE_ADDR + 0x00000C38) -#define PLL_LOCK_PLL_LOCK_PLLE_MASK 0x00000001 - -#define ESW_SYS_DIV_ADDR (ESUB_CLK_BASE_ADDR + 0x00000A04) -#define ESW_SYS_DIV_PLL_SELECT_MASK 0x00000300 -#define ESW_SYS_DIV_DIV_MASK 0x0000001C -#define ESW_SYS_DIV_PLL_VAR_208M_CLK_SELECT 0x00000100 -#define ESW_SYS_DIV_DIV_SELECT 0x4 -#define ESW_SYS_DIV_TRIGGER_MASK 0x00000001 - -#define ESUB_AXI_DIV_DEBUG_ADDR (ESUB_CLK_BASE_ADDR + 0x00000E04) -#define ESUB_AXI_DIV_DEBUG_PLL_SELECT_MASK 0x0000001C -#define ESUB_AXI_DIV_DEBUG_PLL_SELECT_OVERRIDE_MASK 0x00000040 -#define ESUB_AXI_DIV_DEBUG_PLL_VAR_208M_CLK_SELECT 0x0 -#define ESUB_AXI_DIV_DEBUG_TRIGGER_MASK 0x00000001 - -#define PLL_MAX_RETRY 100 - -/* Enable appropriate clocks for Ethernet */ -int clk_eth_enable(void) -{ - int rc = -1; - int retry_count = 0; - rc = clk_get_and_enable("esub_ccu_clk"); - - /* Enable Access to CCU registers */ - writel((1 | WR_ACCESS_PASSWORD), WR_ACCESS_ADDR); - - writel(readl(PLLE_POST_RESETB_ADDR) & - ~PLLE_POST_RESETB_I_POST_RESETB_PLLE_MASK, - PLLE_POST_RESETB_ADDR); - - /* Take PLL out of reset and put into normal mode */ - writel(readl(PLLE_RESETB_ADDR) | PLLE_RESETB_I_PLL_RESETB_PLLE_MASK, - PLLE_RESETB_ADDR); - - /* Wait for PLL lock */ - rc = -1; - while (retry_count < PLL_MAX_RETRY) { - udelay(100); - if (readl(PLL_LOCK_ADDR) & PLL_LOCK_PLL_LOCK_PLLE_MASK) { - rc = 0; - break; - } - retry_count++; - } - - if (rc == -1) { - printf("%s: ETH-PLL lock timeout, Ethernet is not enabled!\n", - __func__); - return -1; - } - - writel(readl(PLLE_POST_RESETB_ADDR) | - PLLE_POST_RESETB_I_POST_RESETB_PLLE_MASK, - PLLE_POST_RESETB_ADDR); - - /* Switch esw_sys_clk to use 104MHz(208MHz/2) clock */ - writel((readl(ESW_SYS_DIV_ADDR) & - ~(ESW_SYS_DIV_PLL_SELECT_MASK | ESW_SYS_DIV_DIV_MASK)) | - ESW_SYS_DIV_PLL_VAR_208M_CLK_SELECT | ESW_SYS_DIV_DIV_SELECT, - ESW_SYS_DIV_ADDR); - - writel(readl(ESW_SYS_DIV_ADDR) | ESW_SYS_DIV_TRIGGER_MASK, - ESW_SYS_DIV_ADDR); - - /* Wait for trigger complete */ - rc = -1; - retry_count = 0; - while (retry_count < PLL_MAX_RETRY) { - udelay(100); - if (!(readl(ESW_SYS_DIV_ADDR) & ESW_SYS_DIV_TRIGGER_MASK)) { - rc = 0; - break; - } - retry_count++; - } - - if (rc == -1) { - printf("%s: SYS CLK Trigger timeout, Ethernet is not enabled!\n", - __func__); - return -1; - } - - /* switch Esub AXI clock to 208MHz */ - writel((readl(ESUB_AXI_DIV_DEBUG_ADDR) & - ~(ESUB_AXI_DIV_DEBUG_PLL_SELECT_MASK | - ESUB_AXI_DIV_DEBUG_PLL_SELECT_OVERRIDE_MASK | - ESUB_AXI_DIV_DEBUG_TRIGGER_MASK)) | - ESUB_AXI_DIV_DEBUG_PLL_VAR_208M_CLK_SELECT | - ESUB_AXI_DIV_DEBUG_PLL_SELECT_OVERRIDE_MASK, - ESUB_AXI_DIV_DEBUG_ADDR); - - writel(readl(ESUB_AXI_DIV_DEBUG_ADDR) | - ESUB_AXI_DIV_DEBUG_TRIGGER_MASK, - ESUB_AXI_DIV_DEBUG_ADDR); - - /* Wait for trigger complete */ - rc = -1; - retry_count = 0; - while (retry_count < PLL_MAX_RETRY) { - udelay(100); - if (!(readl(ESUB_AXI_DIV_DEBUG_ADDR) & - ESUB_AXI_DIV_DEBUG_TRIGGER_MASK)) { - rc = 0; - break; - } - retry_count++; - } - - if (rc == -1) { - printf("%s: AXI CLK Trigger timeout, Ethernet is not enabled!\n", - __func__); - return -1; - } - - /* Disable Access to CCU registers */ - writel(WR_ACCESS_PASSWORD, WR_ACCESS_ADDR); - - return rc; -} diff --git a/arch/arm/dts/stm32mp1-ddr.dtsi b/arch/arm/dts/stm32mp1-ddr.dtsi new file mode 100644 index 00000000000..748271c546d --- /dev/null +++ b/arch/arm/dts/stm32mp1-ddr.dtsi @@ -0,0 +1,187 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause +/* + * Copyright : STMicroelectronics 2018-2025 + */ +#include <linux/stringify.h> + +#ifdef CONFIG_SPL +&ddr { + config-DDR_MEM_COMPATIBLE { + bootph-all; + + compatible = __stringify(st,DDR_MEM_COMPATIBLE); + + st,mem-name = DDR_MEM_NAME; + st,mem-speed = <DDR_MEM_SPEED>; + st,mem-size = <DDR_MEM_SIZE>; + + st,ctl-reg = < + DDR_MSTR + DDR_MRCTRL0 + DDR_MRCTRL1 + DDR_DERATEEN + DDR_DERATEINT + DDR_PWRCTL + DDR_PWRTMG + DDR_HWLPCTL + DDR_RFSHCTL0 + DDR_RFSHCTL3 + DDR_CRCPARCTL0 + DDR_ZQCTL0 + DDR_DFITMG0 + DDR_DFITMG1 + DDR_DFILPCFG0 + DDR_DFIUPD0 + DDR_DFIUPD1 + DDR_DFIUPD2 + DDR_DFIPHYMSTR + DDR_ODTMAP + DDR_DBG0 + DDR_DBG1 + DDR_DBGCMD + DDR_POISONCFG + DDR_PCCFG + >; + + st,ctl-timing = < + DDR_RFSHTMG + DDR_DRAMTMG0 + DDR_DRAMTMG1 + DDR_DRAMTMG2 + DDR_DRAMTMG3 + DDR_DRAMTMG4 + DDR_DRAMTMG5 + DDR_DRAMTMG6 + DDR_DRAMTMG7 + DDR_DRAMTMG8 + DDR_DRAMTMG14 + DDR_ODTCFG + >; + + st,ctl-map = < + DDR_ADDRMAP1 + DDR_ADDRMAP2 + DDR_ADDRMAP3 + DDR_ADDRMAP4 + DDR_ADDRMAP5 + DDR_ADDRMAP6 + DDR_ADDRMAP9 + DDR_ADDRMAP10 + DDR_ADDRMAP11 + >; + + + /* + * Both st,ctl-perf and st,phy-reg differ + * between STM32MP13xx and STM32MP15xx due + * to 16bit and 32bit DRAM bus respectively + * on these SoCs. + */ + + st,phy-timing = < + DDR_PTR0 + DDR_PTR1 + DDR_PTR2 + DDR_DTPR0 + DDR_DTPR1 + DDR_DTPR2 + DDR_MR0 + DDR_MR1 + DDR_MR2 + DDR_MR3 + >; + + status = "okay"; + }; +}; +#endif + +#undef DDR_MEM_COMPATIBLE +#undef DDR_MEM_NAME +#undef DDR_MEM_SPEED +#undef DDR_MEM_SIZE + +#undef DDR_MSTR +#undef DDR_MRCTRL0 +#undef DDR_MRCTRL1 +#undef DDR_DERATEEN +#undef DDR_DERATEINT +#undef DDR_PWRCTL +#undef DDR_PWRTMG +#undef DDR_HWLPCTL +#undef DDR_RFSHCTL0 +#undef DDR_RFSHCTL3 +#undef DDR_RFSHTMG +#undef DDR_CRCPARCTL0 +#undef DDR_DRAMTMG0 +#undef DDR_DRAMTMG1 +#undef DDR_DRAMTMG2 +#undef DDR_DRAMTMG3 +#undef DDR_DRAMTMG4 +#undef DDR_DRAMTMG5 +#undef DDR_DRAMTMG6 +#undef DDR_DRAMTMG7 +#undef DDR_DRAMTMG8 +#undef DDR_DRAMTMG14 +#undef DDR_ZQCTL0 +#undef DDR_DFITMG0 +#undef DDR_DFITMG1 +#undef DDR_DFILPCFG0 +#undef DDR_DFIUPD0 +#undef DDR_DFIUPD1 +#undef DDR_DFIUPD2 +#undef DDR_DFIPHYMSTR +#undef DDR_ADDRMAP1 +#undef DDR_ADDRMAP2 +#undef DDR_ADDRMAP3 +#undef DDR_ADDRMAP4 +#undef DDR_ADDRMAP5 +#undef DDR_ADDRMAP6 +#undef DDR_ADDRMAP9 +#undef DDR_ADDRMAP10 +#undef DDR_ADDRMAP11 +#undef DDR_ODTCFG +#undef DDR_ODTMAP +#undef DDR_SCHED +#undef DDR_SCHED1 +#undef DDR_PERFHPR1 +#undef DDR_PERFLPR1 +#undef DDR_PERFWR1 +#undef DDR_DBG0 +#undef DDR_DBG1 +#undef DDR_DBGCMD +#undef DDR_POISONCFG +#undef DDR_PCCFG +#undef DDR_PCFGR_0 +#undef DDR_PCFGW_0 +#undef DDR_PCFGQOS0_0 +#undef DDR_PCFGQOS1_0 +#undef DDR_PCFGWQOS0_0 +#undef DDR_PCFGWQOS1_0 +#undef DDR_PCFGR_1 +#undef DDR_PCFGW_1 +#undef DDR_PCFGQOS0_1 +#undef DDR_PCFGQOS1_1 +#undef DDR_PCFGWQOS0_1 +#undef DDR_PCFGWQOS1_1 +#undef DDR_PGCR +#undef DDR_PTR0 +#undef DDR_PTR1 +#undef DDR_PTR2 +#undef DDR_ACIOCR +#undef DDR_DXCCR +#undef DDR_DSGCR +#undef DDR_DCR +#undef DDR_DTPR0 +#undef DDR_DTPR1 +#undef DDR_DTPR2 +#undef DDR_MR0 +#undef DDR_MR1 +#undef DDR_MR2 +#undef DDR_MR3 +#undef DDR_ODTCR +#undef DDR_ZQ0CR1 +#undef DDR_DX0GCR +#undef DDR_DX1GCR +#undef DDR_DX2GCR +#undef DDR_DX3GCR diff --git a/arch/arm/dts/stm32mp13-ddr.dtsi b/arch/arm/dts/stm32mp13-ddr.dtsi new file mode 100644 index 00000000000..952e45b047f --- /dev/null +++ b/arch/arm/dts/stm32mp13-ddr.dtsi @@ -0,0 +1,49 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause +/* + * Copyright : STMicroelectronics 2018-2025 + */ +#ifdef CONFIG_SPL +&ddr { + clocks = <&rcc AXIDCG>, + <&rcc DDRC1>, + <&rcc DDRPHYC>, + <&rcc DDRCAPB>, + <&rcc DDRPHYCAPB>; + + clock-names = "axidcg", + "ddrc1", + "ddrphyc", + "ddrcapb", + "ddrphycapb"; + + config-DDR_MEM_COMPATIBLE { + st,ctl-perf = < + DDR_SCHED + DDR_SCHED1 + DDR_PERFHPR1 + DDR_PERFLPR1 + DDR_PERFWR1 + DDR_PCFGR_0 + DDR_PCFGW_0 + DDR_PCFGQOS0_0 + DDR_PCFGQOS1_0 + DDR_PCFGWQOS0_0 + DDR_PCFGWQOS1_0 + >; + + st,phy-reg = < + DDR_PGCR + DDR_ACIOCR + DDR_DXCCR + DDR_DSGCR + DDR_DCR + DDR_ODTCR + DDR_ZQ0CR1 + DDR_DX0GCR + DDR_DX1GCR + >; + }; +}; +#endif + +#include "stm32mp1-ddr.dtsi" diff --git a/arch/arm/dts/stm32mp13-ddr3-dhsom-1x2Gb-1066-binG.dtsi b/arch/arm/dts/stm32mp13-ddr3-dhsom-1x2Gb-1066-binG.dtsi new file mode 100644 index 00000000000..7b344541c3e --- /dev/null +++ b/arch/arm/dts/stm32mp13-ddr3-dhsom-1x2Gb-1066-binG.dtsi @@ -0,0 +1,100 @@ +// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause +/* + * Copyright (C) 2025, DH electronics - All Rights Reserved + * + * STM32MP13xx DHSOM configuration + * 1x DDR3L 1Gb, 16-bit, 533MHz, Single Die Package in flyby topology. + * Reference used W631GU6MB15I from Winbond + * + * DDR type / Platform DDR3/3L + * freq 533MHz + * width 16 + * datasheet 0 = W631GU6MB15I / DDR3-1333 + * DDR density 2 + * timing mode optimized + * address mapping : RBC + * Tc > + 85C : J + */ +#define DDR_MEM_COMPATIBLE ddr3l-dhsom-1066-888-bin-g-1x2gb-533mhz +#define DDR_MEM_NAME "DDR3-DDR3L 16bits 533000kHz" +#define DDR_MEM_SPEED 533000 +#define DDR_MEM_SIZE 0x20000000 + +#define DDR_MSTR 0x00040401 +#define DDR_MRCTRL0 0x00000010 +#define DDR_MRCTRL1 0x00000000 +#define DDR_DERATEEN 0x00000000 +#define DDR_DERATEINT 0x00800000 +#define DDR_PWRCTL 0x00000000 +#define DDR_PWRTMG 0x00400010 +#define DDR_HWLPCTL 0x00000000 +#define DDR_RFSHCTL0 0x00210000 +#define DDR_RFSHCTL3 0x00000000 +#define DDR_RFSHTMG 0x0081008B +#define DDR_CRCPARCTL0 0x00000000 +#define DDR_DRAMTMG0 0x121B2414 +#define DDR_DRAMTMG1 0x000A041B +#define DDR_DRAMTMG2 0x0607080F +#define DDR_DRAMTMG3 0x0050400C +#define DDR_DRAMTMG4 0x07040607 +#define DDR_DRAMTMG5 0x06060403 +#define DDR_DRAMTMG6 0x02020002 +#define DDR_DRAMTMG7 0x00000202 +#define DDR_DRAMTMG8 0x00001005 +#define DDR_DRAMTMG14 0x000000A0 +#define DDR_ZQCTL0 0xC2000040 +#define DDR_DFITMG0 0x02050105 +#define DDR_DFITMG1 0x00000202 +#define DDR_DFILPCFG0 0x07000000 +#define DDR_DFIUPD0 0xC0400003 +#define DDR_DFIUPD1 0x00000000 +#define DDR_DFIUPD2 0x00000000 +#define DDR_DFIPHYMSTR 0x00000000 +#define DDR_ADDRMAP1 0x00080808 +#define DDR_ADDRMAP2 0x00000000 +#define DDR_ADDRMAP3 0x00000000 +#define DDR_ADDRMAP4 0x00001F1F +#define DDR_ADDRMAP5 0x07070707 +#define DDR_ADDRMAP6 0x0F070707 +#define DDR_ADDRMAP9 0x00000000 +#define DDR_ADDRMAP10 0x00000000 +#define DDR_ADDRMAP11 0x00000000 +#define DDR_ODTCFG 0x06000600 +#define DDR_ODTMAP 0x00000001 +#define DDR_SCHED 0x00000F01 +#define DDR_SCHED1 0x00000000 +#define DDR_PERFHPR1 0x00000001 +#define DDR_PERFLPR1 0x04000200 +#define DDR_PERFWR1 0x08000400 +#define DDR_DBG0 0x00000000 +#define DDR_DBG1 0x00000000 +#define DDR_DBGCMD 0x00000000 +#define DDR_POISONCFG 0x00000000 +#define DDR_PCCFG 0x00000010 +#define DDR_PCFGR_0 0x00000000 +#define DDR_PCFGW_0 0x00000000 +#define DDR_PCFGQOS0_0 0x00100009 +#define DDR_PCFGQOS1_0 0x00000020 +#define DDR_PCFGWQOS0_0 0x01100B03 +#define DDR_PCFGWQOS1_0 0x01000200 +#define DDR_PGCR 0x01442E02 +#define DDR_PTR0 0x0022AA5B +#define DDR_PTR1 0x04841104 +#define DDR_PTR2 0x042DA068 +#define DDR_ACIOCR 0x10400812 +#define DDR_DXCCR 0x00000C40 +#define DDR_DSGCR 0xF200011F +#define DDR_DCR 0x0000000B +#define DDR_DTPR0 0x36D477D0 +#define DDR_DTPR1 0x098B00D8 +#define DDR_DTPR2 0x10023600 +#define DDR_MR0 0x00000830 +#define DDR_MR1 0x00000000 +#define DDR_MR2 0x00000208 +#define DDR_MR3 0x00000000 +#define DDR_ODTCR 0x00010000 +#define DDR_ZQ0CR1 0x00000038 +#define DDR_DX0GCR 0x0000CE81 +#define DDR_DX1GCR 0x0000CE81 + +#include "stm32mp13-ddr.dtsi" diff --git a/arch/arm/dts/stm32mp13-u-boot.dtsi b/arch/arm/dts/stm32mp13-u-boot.dtsi index 1fe6966781c..ad63d5027b2 100644 --- a/arch/arm/dts/stm32mp13-u-boot.dtsi +++ b/arch/arm/dts/stm32mp13-u-boot.dtsi @@ -17,6 +17,7 @@ pinctrl0 = &pinctrl; }; +#if defined(CONFIG_TFABOOT) firmware { optee { bootph-all; @@ -27,6 +28,86 @@ psci { bootph-some-ram; }; +#else + binman: binman { + multiple-images; + + spl-stm32 { + filename = "u-boot-spl.stm32"; + mkimage { + args = "-T stm32imagev2 -a 0x2ffe0000 -e 0x2ffe0000"; + u-boot-spl { + no-write-symbols; + }; + }; + }; + }; + + clocks { + bootph-all; + + clk_hse: ck_hse { + bootph-all; + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <24000000>; + }; + + clk_hsi: ck_hsi { + bootph-all; + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <64000000>; + }; + + clk_lse: ck_lse { + bootph-all; + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <32768>; + }; + + clk_lsi: ck_lsi { + bootph-all; + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <32000>; + }; + + clk_csi: ck_csi { + bootph-all; + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <4000000>; + }; + }; + + cpu0_opp_table: cpu0-opp-table { + compatible = "operating-points-v2"; + opp-shared; + bootph-pre-ram; + opp-650000000 { + bootph-pre-ram; + opp-hz = /bits/ 64 <650000000>; + opp-microvolt = <1200000>; + opp-supported-hw = <0x1>; + }; + opp-1000000000 { + bootph-pre-ram; + opp-hz = /bits/ 64 <1000000000>; + opp-microvolt = <1350000>; + opp-supported-hw = <0x2>; + }; + }; + + reboot { + bootph-all; + compatible = "syscon-reboot"; + regmap = <&rcc>; + offset = <0x114>; + mask = <0x1>; + }; +#endif soc { bootph-all; @@ -52,6 +133,14 @@ bootph-all; }; +#if !defined(CONFIG_TFABOOT) +&cpu0 { + nvmem-cells = <&part_number_otp>; + nvmem-cell-names = "part_number"; + operating-points-v2 = <&cpu0_opp_table>; +}; +#endif + &gpioa { bootph-all; }; diff --git a/arch/arm/dts/stm32mp13xx-dhcor-u-boot.dtsi b/arch/arm/dts/stm32mp13xx-dhcor-u-boot.dtsi index 9ff42ab8248..699ba15d6ea 100644 --- a/arch/arm/dts/stm32mp13xx-dhcor-u-boot.dtsi +++ b/arch/arm/dts/stm32mp13xx-dhcor-u-boot.dtsi @@ -3,7 +3,9 @@ * Copyright (C) 2024 Marek Vasut <marex@denx.de> */ +#include <dt-bindings/clock/stm32mp13-clksrc.h> #include "stm32mp13-u-boot.dtsi" +#include "stm32mp13-ddr3-dhsom-1x2Gb-1066-binG.dtsi" / { aliases { @@ -18,8 +20,12 @@ }; }; +&etzpc { + compatible = "simple-bus"; +}; + &flash0 { - bootph-pre-ram; + bootph-all; partitions { compatible = "fixed-partitions"; @@ -48,6 +54,138 @@ }; }; +&i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c3_pins_a>; +}; + +&qspi { + bootph-all; +}; + +&qspi_clk_pins_a { + bootph-all; + pins { + bootph-all; + }; +}; + +&qspi_bk1_pins_a { + bootph-all; + pins { + bootph-all; + }; +}; + +&qspi_cs1_pins_a { + bootph-all; + pins { + bootph-all; + }; +}; + +&pinctrl { + bootph-all; + i2c3_pins_a: i2c3-0 { + bootph-all; + pins { + bootph-all; + pinmux = <STM32_PINMUX('B', 8, AF5)>, /* I2C3_SCL */ + <STM32_PINMUX('H', 14, AF4)>; /* I2C3_SDA */ + bias-disable; + drive-open-drain; + slew-rate = <0>; + }; + }; +}; + +#if !defined(CONFIG_TFABOOT) +&rcc { + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clk_hse>, <&clk_hsi>, <&clk_csi>, <&clk_lse>, <&clk_lsi>; + + st,clksrc = < + CLK_MPU_PLL1P + CLK_AXI_PLL2P + CLK_MLAHBS_PLL3 + CLK_PLL12_HSE + CLK_PLL3_HSE + CLK_PLL4_HSE + CLK_CKPER_HSE + CLK_RTC_LSE + CLK_MCO1_LSI + CLK_MCO2_HSI + >; + + st,clkdiv = < + 0 /*AXI*/ + 0 /*MLHAB*/ + 1 /*APB1*/ + 1 /*APB2*/ + 1 /*APB3*/ + 1 /*APB4*/ + 2 /*APB5*/ + 1 /*APB6*/ + 0 /*RTC*/ + >; + + st,pkcs = < + CLK_I2C12_HSI + CLK_I2C3_HSI + CLK_QSPI_PLL3R + CLK_SAES_AXI + CLK_SDMMC1_PLL3R + CLK_SDMMC2_PLL3R + CLK_STGEN_HSE + CLK_UART2_HSI + CLK_UART4_HSI + CLK_USBO_USBPHY + CLK_USBPHY_HSE + >; + + /* + * cfg = < DIVM1 DIVN P Q R PQR(p,q,r) >; + * frac = < f >; + * + * PRQ(p,q,r) ... for p,q,r: 0-output disabled / 1-output enabled + * DIVN ... actually multiplier, but RCC_PLL1CFGR1 calls the field DIVN + * m ... for PLL1,2: m=2 ; for PLL3,4: m=1 + * XTAL = 24 MHz + * + * VCO = ( XTAL / (DIVM1 + 1) ) * m * ( DIVN + 1 + ( f / 8192 ) ) + * P = VCO / (P + 1) + * Q = VCO / (Q + 1) + * R = VCO / (R + 1) + */ + + /* VCO = 1066.0 MHz => P = 266 (AXI), Q = 266, R = 533 (DDR) */ + pll2: st,pll@1 { + compatible = "st,stm32mp1-pll"; + reg = <1>; + cfg = < 2 65 1 1 0 PQR(1,1,1) >; + frac = < 0x1400 >; + bootph-all; + }; + + /* VCO = 600 MHz => P = 200, Q = 150, R = 200 */ + pll3: st,pll@2 { + compatible = "st,stm32mp1-pll"; + reg = <2>; + cfg = < 2 74 2 3 2 PQR(1,1,1) >; + bootph-all; + }; + + /* VCO = 750.0 MHz => P = 125, Q = 83, R = 75 */ + pll4: st,pll@3 { + compatible = "st,stm32mp1-pll"; + reg = <3>; + cfg = < 3 124 5 8 9 PQR(1,1,1) >; + bootph-all; + }; +}; +#endif + &sdmmc1 { status = "disabled"; }; @@ -55,3 +193,23 @@ &usbotg_hs { u-boot,force-b-session-valid; }; + +&vddcpu { + bootph-all; +}; + +&vdd_ddr { + bootph-all; +}; + +&vdd { + bootph-all; +}; + +&vddcore { + bootph-all; +}; + +&vref_ddr { + bootph-all; +}; diff --git a/arch/arm/dts/stm32mp15-ddr.dtsi b/arch/arm/dts/stm32mp15-ddr.dtsi index 48b0828828f..f18fdaeab68 100644 --- a/arch/arm/dts/stm32mp15-ddr.dtsi +++ b/arch/arm/dts/stm32mp15-ddr.dtsi @@ -2,8 +2,6 @@ /* * Copyright : STMicroelectronics 2018 */ -#include <linux/stringify.h> - #ifdef CONFIG_SPL &ddr { clocks = <&rcc AXIDCG>, @@ -21,69 +19,6 @@ "ddrphycapb"; config-DDR_MEM_COMPATIBLE { - bootph-all; - - compatible = __stringify(st,DDR_MEM_COMPATIBLE); - - st,mem-name = DDR_MEM_NAME; - st,mem-speed = <DDR_MEM_SPEED>; - st,mem-size = <DDR_MEM_SIZE>; - - st,ctl-reg = < - DDR_MSTR - DDR_MRCTRL0 - DDR_MRCTRL1 - DDR_DERATEEN - DDR_DERATEINT - DDR_PWRCTL - DDR_PWRTMG - DDR_HWLPCTL - DDR_RFSHCTL0 - DDR_RFSHCTL3 - DDR_CRCPARCTL0 - DDR_ZQCTL0 - DDR_DFITMG0 - DDR_DFITMG1 - DDR_DFILPCFG0 - DDR_DFIUPD0 - DDR_DFIUPD1 - DDR_DFIUPD2 - DDR_DFIPHYMSTR - DDR_ODTMAP - DDR_DBG0 - DDR_DBG1 - DDR_DBGCMD - DDR_POISONCFG - DDR_PCCFG - >; - - st,ctl-timing = < - DDR_RFSHTMG - DDR_DRAMTMG0 - DDR_DRAMTMG1 - DDR_DRAMTMG2 - DDR_DRAMTMG3 - DDR_DRAMTMG4 - DDR_DRAMTMG5 - DDR_DRAMTMG6 - DDR_DRAMTMG7 - DDR_DRAMTMG8 - DDR_DRAMTMG14 - DDR_ODTCFG - >; - - st,ctl-map = < - DDR_ADDRMAP1 - DDR_ADDRMAP2 - DDR_ADDRMAP3 - DDR_ADDRMAP4 - DDR_ADDRMAP5 - DDR_ADDRMAP6 - DDR_ADDRMAP9 - DDR_ADDRMAP10 - DDR_ADDRMAP11 - >; - st,ctl-perf = < DDR_SCHED DDR_SCHED1 @@ -117,111 +52,8 @@ DDR_DX2GCR DDR_DX3GCR >; - - st,phy-timing = < - DDR_PTR0 - DDR_PTR1 - DDR_PTR2 - DDR_DTPR0 - DDR_DTPR1 - DDR_DTPR2 - DDR_MR0 - DDR_MR1 - DDR_MR2 - DDR_MR3 - >; - - status = "okay"; }; }; #endif -#undef DDR_MEM_COMPATIBLE -#undef DDR_MEM_NAME -#undef DDR_MEM_SPEED -#undef DDR_MEM_SIZE - -#undef DDR_MSTR -#undef DDR_MRCTRL0 -#undef DDR_MRCTRL1 -#undef DDR_DERATEEN -#undef DDR_DERATEINT -#undef DDR_PWRCTL -#undef DDR_PWRTMG -#undef DDR_HWLPCTL -#undef DDR_RFSHCTL0 -#undef DDR_RFSHCTL3 -#undef DDR_RFSHTMG -#undef DDR_CRCPARCTL0 -#undef DDR_DRAMTMG0 -#undef DDR_DRAMTMG1 -#undef DDR_DRAMTMG2 -#undef DDR_DRAMTMG3 -#undef DDR_DRAMTMG4 -#undef DDR_DRAMTMG5 -#undef DDR_DRAMTMG6 -#undef DDR_DRAMTMG7 -#undef DDR_DRAMTMG8 -#undef DDR_DRAMTMG14 -#undef DDR_ZQCTL0 -#undef DDR_DFITMG0 -#undef DDR_DFITMG1 -#undef DDR_DFILPCFG0 -#undef DDR_DFIUPD0 -#undef DDR_DFIUPD1 -#undef DDR_DFIUPD2 -#undef DDR_DFIPHYMSTR -#undef DDR_ADDRMAP1 -#undef DDR_ADDRMAP2 -#undef DDR_ADDRMAP3 -#undef DDR_ADDRMAP4 -#undef DDR_ADDRMAP5 -#undef DDR_ADDRMAP6 -#undef DDR_ADDRMAP9 -#undef DDR_ADDRMAP10 -#undef DDR_ADDRMAP11 -#undef DDR_ODTCFG -#undef DDR_ODTMAP -#undef DDR_SCHED -#undef DDR_SCHED1 -#undef DDR_PERFHPR1 -#undef DDR_PERFLPR1 -#undef DDR_PERFWR1 -#undef DDR_DBG0 -#undef DDR_DBG1 -#undef DDR_DBGCMD -#undef DDR_POISONCFG -#undef DDR_PCCFG -#undef DDR_PCFGR_0 -#undef DDR_PCFGW_0 -#undef DDR_PCFGQOS0_0 -#undef DDR_PCFGQOS1_0 -#undef DDR_PCFGWQOS0_0 -#undef DDR_PCFGWQOS1_0 -#undef DDR_PCFGR_1 -#undef DDR_PCFGW_1 -#undef DDR_PCFGQOS0_1 -#undef DDR_PCFGQOS1_1 -#undef DDR_PCFGWQOS0_1 -#undef DDR_PCFGWQOS1_1 -#undef DDR_PGCR -#undef DDR_PTR0 -#undef DDR_PTR1 -#undef DDR_PTR2 -#undef DDR_ACIOCR -#undef DDR_DXCCR -#undef DDR_DSGCR -#undef DDR_DCR -#undef DDR_DTPR0 -#undef DDR_DTPR1 -#undef DDR_DTPR2 -#undef DDR_MR0 -#undef DDR_MR1 -#undef DDR_MR2 -#undef DDR_MR3 -#undef DDR_ODTCR -#undef DDR_ZQ0CR1 -#undef DDR_DX0GCR -#undef DDR_DX1GCR -#undef DDR_DX2GCR -#undef DDR_DX3GCR +#include "stm32mp1-ddr.dtsi" diff --git a/arch/arm/dts/stm32mp23-u-boot.dtsi b/arch/arm/dts/stm32mp23-u-boot.dtsi new file mode 100644 index 00000000000..872a8739c54 --- /dev/null +++ b/arch/arm/dts/stm32mp23-u-boot.dtsi @@ -0,0 +1,104 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause +/* + * Copyright : STMicroelectronics 2024 + */ + +/ { + aliases { + gpio0 = &gpioa; + gpio1 = &gpiob; + gpio2 = &gpioc; + gpio3 = &gpiod; + gpio4 = &gpioe; + gpio5 = &gpiof; + gpio6 = &gpiog; + gpio7 = &gpioh; + gpio8 = &gpioi; + gpio25 = &gpioz; + pinctrl0 = &pinctrl; + pinctrl1 = &pinctrl_z; + }; + + firmware { + optee { + bootph-all; + }; + + scmi { + bootph-all; + }; + }; + + /* need PSCI for sysreset during board_f */ + psci { + bootph-all; + }; + + soc@0 { + bootph-all; + }; +}; + +&bsec { + bootph-all; +}; + +&gpioa { + bootph-all; +}; + +&gpiob { + bootph-all; +}; + +&gpioc { + bootph-all; +}; + +&gpiod { + bootph-all; +}; + +&gpioe { + bootph-all; +}; + +&gpiof { + bootph-all; +}; + +&gpiog { + bootph-all; +}; + +&gpioh { + bootph-all; +}; + +&gpioi { + bootph-all; +}; + +&gpioz { + bootph-all; +}; + +&pinctrl { + bootph-all; +}; + +&rcc { + bootph-all; +}; + +&rifsc { + bootph-all; +}; + +&scmi_clk { + bootph-all; +}; + +&syscfg { + bootph-all; +}; diff --git a/arch/arm/dts/stm32mp235f-dk-u-boot.dtsi b/arch/arm/dts/stm32mp235f-dk-u-boot.dtsi new file mode 100644 index 00000000000..1bc77874050 --- /dev/null +++ b/arch/arm/dts/stm32mp235f-dk-u-boot.dtsi @@ -0,0 +1,27 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause +/* + * Copyright (C) STMicroelectronics 2024 - All Rights Reserved + */ + +#include "stm32mp23-u-boot.dtsi" + +/ { + config { + u-boot,boot-led = "led-blue"; + u-boot,mmc-env-partition = "u-boot-env"; + }; +}; + +&usart2 { + bootph-all; +}; + +&usart2_pins_a { + bootph-all; + pins1 { + bootph-all; + }; + pins2 { + bootph-all; + }; +}; diff --git a/arch/arm/include/asm/arch-am33xx/mem.h b/arch/arm/include/asm/arch-am33xx/mem.h index 0fd52f82f59..316ec09318a 100644 --- a/arch/arm/include/asm/arch-am33xx/mem.h +++ b/arch/arm/include/asm/arch-am33xx/mem.h @@ -29,7 +29,7 @@ * * Currently valid part Names are (PART): * M_NAND - Micron NAND - * STNOR - STMicrolelctronics M29W128GL + * STNOR - STMicroelectronics M29W128GL */ #define GPMC_SIZE_256M 0x0 #define GPMC_SIZE_128M 0x8 diff --git a/arch/arm/include/asm/arch-omap5/mem.h b/arch/arm/include/asm/arch-omap5/mem.h index bd72fb611d1..4f26daf1c43 100644 --- a/arch/arm/include/asm/arch-omap5/mem.h +++ b/arch/arm/include/asm/arch-omap5/mem.h @@ -29,7 +29,7 @@ * * Currently valid part Names are (PART): * M_NAND - Micron NAND - * STNOR - STMicrolelctronics M29W128GL + * STNOR - STMicroelectronics M29W128GL */ #define GPMC_SIZE_256M 0x0 #define GPMC_SIZE_128M 0x8 diff --git a/arch/arm/mach-stm32mp/Kconfig b/arch/arm/mach-stm32mp/Kconfig index 09b7d5123ae..ba4694f2964 100644 --- a/arch/arm/mach-stm32mp/Kconfig +++ b/arch/arm/mach-stm32mp/Kconfig @@ -40,16 +40,19 @@ choice config STM32MP13X bool "Support STMicroelectronics STM32MP13x Soc" select ARCH_EARLY_INIT_R - select ARM_SMCCC + select ARM_SMCCC if TFABOOT + select ARCH_SUPPORT_PSCI if !TFABOOT + select BINMAN if !TFABOOT select CPU_V7A select CPU_V7_HAS_NONSEC select CPU_V7_HAS_VIRT - select OF_BOARD + select OF_BOARD if TFABOOT select OF_BOARD_SETUP select PINCTRL_STM32 select STM32_RCC select STM32_RESET select STM32_SERIAL + select SUPPORT_SPL if !TFABOOT select SYS_ARCH_TIMER imply CMD_NVEDIT_INFO imply OF_UPSTREAM @@ -81,6 +84,32 @@ config STM32MP15X STMicroelectronics MPU with core ARMv7 dual core A7 for STM32MP157/3, monocore for STM32MP151 +config STM32MP23X + bool "Support STMicroelectronics STM32MP23x Soc" + select ARM64 + select CLK_STM32MP25 + select OF_BOARD + select PINCTRL_STM32 + select STM32_RCC + select STM32_RESET + select STM32_SERIAL + select STM32MP_TAMP_NVMEM + select SYS_ARCH_TIMER + select TFABOOT + imply CLK_SCMI + imply CMD_NVEDIT_INFO + imply DM_REGULATOR + imply DM_REGULATOR_SCMI + imply OF_UPSTREAM + imply OPTEE + imply RESET_SCMI + imply SYSRESET_PSCI + imply TEE + imply VERSION_VARIABLE + help + Support of STMicroelectronics SOC STM32MP23x family + STMicroelectronics MPU with 2 * A53 core and 1 M33 core + config STM32MP25X bool "Support STMicroelectronics STM32MP25x Soc" select ARM64 @@ -165,6 +194,7 @@ config MFD_STM32_TIMERS source "arch/arm/mach-stm32mp/Kconfig.13x" source "arch/arm/mach-stm32mp/Kconfig.15x" +source "arch/arm/mach-stm32mp/Kconfig.23x" source "arch/arm/mach-stm32mp/Kconfig.25x" source "arch/arm/mach-stm32mp/cmd_stm32prog/Kconfig" diff --git a/arch/arm/mach-stm32mp/Kconfig.13x b/arch/arm/mach-stm32mp/Kconfig.13x index bc8b3f8cf77..6a45c4e4132 100644 --- a/arch/arm/mach-stm32mp/Kconfig.13x +++ b/arch/arm/mach-stm32mp/Kconfig.13x @@ -20,10 +20,11 @@ config TARGET_ST_STM32MP13X endchoice config TEXT_BASE - default 0xC0000000 + default 0xC0000000 if TFABOOT + default 0xC0100000 if !TFABOOT config PRE_CON_BUF_ADDR - default 0xC0800000 + default 0xC2FFF000 config PRE_CON_BUF_SZ default 4096 diff --git a/arch/arm/mach-stm32mp/Kconfig.23x b/arch/arm/mach-stm32mp/Kconfig.23x new file mode 100644 index 00000000000..2859210c77c --- /dev/null +++ b/arch/arm/mach-stm32mp/Kconfig.23x @@ -0,0 +1,37 @@ +if STM32MP23X + +choice + prompt "STM32MP23x board select" + optional + +config TARGET_ST_STM32MP23X + bool "STMicroelectronics STM32MP23x boards" + imply BOOTSTAGE + imply CMD_BOOTSTAGE + help + target the STMicroelectronics board with SOC STM32MP23x + managed by board/st/stm32mp2 + The difference between board are managed with devicetree + +endchoice + +config TEXT_BASE + default 0x84000000 + +config PRE_CON_BUF_ADDR + default 0x84800000 + +config PRE_CON_BUF_SZ + default 4096 + +if DEBUG_UART + +# debug on USART2 by default +config DEBUG_UART_BASE + default 0x400e0000 + +endif + +source "board/st/stm32mp2/Kconfig" + +endif diff --git a/arch/arm/mach-stm32mp/Makefile b/arch/arm/mach-stm32mp/Makefile index ecd49fe668d..eeb5fdd7b45 100644 --- a/arch/arm/mach-stm32mp/Makefile +++ b/arch/arm/mach-stm32mp/Makefile @@ -10,6 +10,7 @@ obj-y += soc.o obj-$(CONFIG_STM32MP15X) += stm32mp1/ obj-$(CONFIG_STM32MP13X) += stm32mp1/ +obj-$(CONFIG_STM32MP23X) += stm32mp2/ obj-$(CONFIG_STM32MP25X) += stm32mp2/ obj-$(CONFIG_MFD_STM32_TIMERS) += timers.o diff --git a/arch/arm/mach-stm32mp/cmd_stm32key.c b/arch/arm/mach-stm32mp/cmd_stm32key.c index 6bfa67859e1..f5def4cd2dc 100644 --- a/arch/arm/mach-stm32mp/cmd_stm32key.c +++ b/arch/arm/mach-stm32mp/cmd_stm32key.c @@ -171,7 +171,7 @@ static u8 get_key_nb(void) if (IS_ENABLED(CONFIG_STM32MP15X)) return ARRAY_SIZE(stm32mp15_list); - if (IS_ENABLED(CONFIG_STM32MP25X)) + if (IS_ENABLED(CONFIG_STM32MP23X) || IS_ENABLED(CONFIG_STM32MP25X)) return ARRAY_SIZE(stm32mp25_list); } @@ -183,7 +183,7 @@ static const struct stm32key *get_key(u8 index) if (IS_ENABLED(CONFIG_STM32MP15X)) return &stm32mp15_list[index]; - if (IS_ENABLED(CONFIG_STM32MP25X)) + if (IS_ENABLED(CONFIG_STM32MP23X) || IS_ENABLED(CONFIG_STM32MP25X)) return &stm32mp25_list[index]; } @@ -195,7 +195,7 @@ static u8 get_otp_close_state_nb(void) if (IS_ENABLED(CONFIG_STM32MP15X)) return ARRAY_SIZE(stm32mp15_close_state_otp); - if (IS_ENABLED(CONFIG_STM32MP25X)) + if (IS_ENABLED(CONFIG_STM32MP23X) || IS_ENABLED(CONFIG_STM32MP25X)) return ARRAY_SIZE(stm32mp25_close_state_otp); } @@ -207,7 +207,7 @@ static const struct otp_close *get_otp_close_state(u8 index) if (IS_ENABLED(CONFIG_STM32MP15X)) return &stm32mp15_close_state_otp[index]; - if (IS_ENABLED(CONFIG_STM32MP25X)) + if (IS_ENABLED(CONFIG_STM32MP23X) || IS_ENABLED(CONFIG_STM32MP25X)) return &stm32mp25_close_state_otp[index]; } diff --git a/arch/arm/mach-stm32mp/include/mach/stm32.h b/arch/arm/mach-stm32mp/include/mach/stm32.h index dfba57e7dc4..2bf50c755cb 100644 --- a/arch/arm/mach-stm32mp/include/mach/stm32.h +++ b/arch/arm/mach-stm32mp/include/mach/stm32.h @@ -156,6 +156,8 @@ enum forced_boot_mode { #endif #ifdef CONFIG_STM32MP13X +#define TAMP_BACKUP_MAGIC_NUMBER TAMP_BACKUP_REGISTER(4) +#define TAMP_BACKUP_BRANCH_ADDRESS TAMP_BACKUP_REGISTER(5) #define TAMP_BOOTCOUNT TAMP_BACKUP_REGISTER(31) #define TAMP_BOOT_CONTEXT TAMP_BACKUP_REGISTER(30) #endif @@ -163,7 +165,7 @@ enum forced_boot_mode { #endif /* __ASSEMBLY__ */ #endif /* CONFIG_STM32MP15X || CONFIG_STM32MP13X */ -#ifdef CONFIG_STM32MP25X +#if defined(CONFIG_STM32MP23X) || defined(CONFIG_STM32MP25X) #define STM32_USART2_BASE 0x400E0000 #define STM32_USART3_BASE 0x400F0000 #define STM32_UART4_BASE 0x40100000 @@ -188,7 +190,7 @@ enum forced_boot_mode { /* TAMP registers zone 3 RIF 1 (RW) at 96*/ #define TAMP_BOOT_CONTEXT TAMP_BACKUP_REGISTER(96) -#endif /* STM32MP25X */ +#endif /* defined(CONFIG_STM32MP23X) || defined(CONFIG_STM32MP25X) */ /* offset used for BSEC driver: misc_read and misc_write */ #define STM32_BSEC_SHADOW_OFFSET 0x0 @@ -212,14 +214,14 @@ enum forced_boot_mode { #define BSEC_OTP_MAC 57 #define BSEC_OTP_BOARD 60 #endif -#ifdef CONFIG_STM32MP25X +#if defined(CONFIG_STM32MP23X) || defined(CONFIG_STM32MP25X) #define BSEC_OTP_SERIAL 5 #define BSEC_OTP_RPN 9 #define BSEC_OTP_REVID 102 #define BSEC_OTP_PKG 122 #define BSEC_OTP_BOARD 246 #define BSEC_OTP_MAC 247 -#endif +#endif /* defined(CONFIG_STM32MP23X) || defined(CONFIG_STM32MP25X) */ #ifndef __ASSEMBLY__ #include <asm/types.h> diff --git a/arch/arm/mach-stm32mp/include/mach/sys_proto.h b/arch/arm/mach-stm32mp/include/mach/sys_proto.h index 19073668497..2a4837184fc 100644 --- a/arch/arm/mach-stm32mp/include/mach/sys_proto.h +++ b/arch/arm/mach-stm32mp/include/mach/sys_proto.h @@ -30,29 +30,44 @@ #define CPU_STM32MP131Fxx 0x05010EC8 #define CPU_STM32MP131Dxx 0x05010EC9 +/* ID for STM32MP23x = Device Part Number (RPN) (bit31:0) */ +#define CPU_STM32MP235Cxx 0x00082182 +#define CPU_STM32MP233Cxx 0x000B318E +#define CPU_STM32MP231Cxx 0x000B31EF +#define CPU_STM32MP235Axx 0x40082F82 +#define CPU_STM32MP233Axx 0x400B3F8E +#define CPU_STM32MP231Axx 0x400B3FEF +#define CPU_STM32MP235Fxx 0x80082182 +#define CPU_STM32MP233Fxx 0x800B318E +#define CPU_STM32MP231Fxx 0x800B31EF +#define CPU_STM32MP235Dxx 0xC0082F82 +#define CPU_STM32MP233Dxx 0xC00B3F8E +#define CPU_STM32MP231Dxx 0xC00B3FEF + /* ID for STM32MP25x = Device Part Number (RPN) (bit31:0) */ -#define CPU_STM32MP257Cxx 0x00002000 -#define CPU_STM32MP255Cxx 0x00082000 -#define CPU_STM32MP253Cxx 0x000B2004 -#define CPU_STM32MP251Cxx 0x000B3065 -#define CPU_STM32MP257Axx 0x40002E00 -#define CPU_STM32MP255Axx 0x40082E00 -#define CPU_STM32MP253Axx 0x400B2E04 -#define CPU_STM32MP251Axx 0x400B3E65 -#define CPU_STM32MP257Fxx 0x80002000 -#define CPU_STM32MP255Fxx 0x80082000 -#define CPU_STM32MP253Fxx 0x800B2004 -#define CPU_STM32MP251Fxx 0x800B3065 -#define CPU_STM32MP257Dxx 0xC0002E00 -#define CPU_STM32MP255Dxx 0xC0082E00 -#define CPU_STM32MP253Dxx 0xC00B2E04 -#define CPU_STM32MP251Dxx 0xC00B3E65 +#define CPU_STM32MP257Cxx 0x00002000 +#define CPU_STM32MP255Cxx 0x00082000 +#define CPU_STM32MP253Cxx 0x000B2004 +#define CPU_STM32MP251Cxx 0x000B3065 +#define CPU_STM32MP257Axx 0x40002E00 +#define CPU_STM32MP255Axx 0x40082E00 +#define CPU_STM32MP253Axx 0x400B2E04 +#define CPU_STM32MP251Axx 0x400B3E65 +#define CPU_STM32MP257Fxx 0x80002000 +#define CPU_STM32MP255Fxx 0x80082000 +#define CPU_STM32MP253Fxx 0x800B2004 +#define CPU_STM32MP251Fxx 0x800B3065 +#define CPU_STM32MP257Dxx 0xC0002E00 +#define CPU_STM32MP255Dxx 0xC0082E00 +#define CPU_STM32MP253Dxx 0xC00B2E04 +#define CPU_STM32MP251Dxx 0xC00B3E65 /* return CPU_STMP32MP...Xxx constants */ u32 get_cpu_type(void); #define CPU_DEV_STM32MP15 0x500 #define CPU_DEV_STM32MP13 0x501 +#define CPU_DEV_STM32MP23 0x505 #define CPU_DEV_STM32MP25 0x505 /* return CPU_DEV constants */ @@ -87,6 +102,12 @@ u32 get_cpu_package(void); #define STM32MP15_PKG_AD_TFBGA257 1 #define STM32MP15_PKG_UNKNOWN 0 +/* package used for STM32MP23x */ +#define STM32MP23_PKG_CUSTOM 0 +#define STM32MP23_PKG_AL_VFBGA361 1 +#define STM32MP23_PKG_AK_VFBGA424 3 +#define STM32MP23_PKG_AJ_TFBGA361 7 + /* package used for STM32MP25x */ #define STM32MP25_PKG_CUSTOM 0 #define STM32MP25_PKG_AL_VFBGA361 1 diff --git a/arch/arm/mach-stm32mp/include/mach/timers.h b/arch/arm/mach-stm32mp/include/mach/timers.h index a84465bb28e..8209dd84911 100644 --- a/arch/arm/mach-stm32mp/include/mach/timers.h +++ b/arch/arm/mach-stm32mp/include/mach/timers.h @@ -29,6 +29,10 @@ #define TIM_DMAR 0x4C /* DMA register for transfer */ #define TIM_TISEL 0x68 /* Input Selection */ +#define TIM_HWCFGR2 0x3EC /* hardware configuration 2 Reg (MP25) */ +#define TIM_HWCFGR1 0x3F0 /* hardware configuration 1 Reg (MP25) */ +#define TIM_IPIDR 0x3F8 /* IP identification Reg (MP25) */ + #define TIM_CR1_CEN BIT(0) /* Counter Enable */ #define TIM_CR1_ARPE BIT(7) #define TIM_CCER_CCXE (BIT(0) | BIT(4) | BIT(8) | BIT(12)) @@ -40,11 +44,16 @@ #define TIM_CCMR_M1 (BIT(6) | BIT(5)) /* Channel PWM Mode 1 */ #define TIM_BDTR_MOE BIT(15) /* Main Output Enable */ #define TIM_EGR_UG BIT(0) /* Update Generation */ +#define TIM_HWCFGR2_CNT_WIDTH GENMASK(15, 8) /* Counter width */ +#define TIM_HWCFGR1_NB_OF_DT GENMASK(7, 4) /* Complementary outputs & dead-time generators */ #define MAX_TIM_PSC 0xFFFF +#define STM32MP25_TIM_IPIDR 0x00120002 + struct stm32_timers_plat { void __iomem *base; + u32 ipidr; }; struct stm32_timers_priv { diff --git a/arch/arm/mach-stm32mp/stm32mp1/cpu.c b/arch/arm/mach-stm32mp/stm32mp1/cpu.c index 8c09d91de05..e0c6f8ba937 100644 --- a/arch/arm/mach-stm32mp/stm32mp1/cpu.c +++ b/arch/arm/mach-stm32mp/stm32mp1/cpu.c @@ -28,7 +28,9 @@ * early TLB into the .data section so that it not get cleared * with 16kB allignment (see TTBR0_BASE_ADDR_MASK) */ +#if (!IS_ENABLED(CONFIG_XPL_BUILD) || !IS_ENABLED(CONFIG_STM32MP13X)) u8 early_tlb[PGTABLE_SIZE] __section(".data") __aligned(0x4000); +#endif u32 get_bootmode(void) { @@ -95,18 +97,19 @@ void dram_bank_mmu_setup(int bank) */ static void early_enable_caches(void) { +#if (!IS_ENABLED(CONFIG_XPL_BUILD) || !IS_ENABLED(CONFIG_STM32MP13X)) /* I-cache is already enabled in start.S: cpu_init_cp15 */ - if (CONFIG_IS_ENABLED(SYS_DCACHE_OFF)) return; #if !(CONFIG_IS_ENABLED(SYS_ICACHE_OFF) && CONFIG_IS_ENABLED(SYS_DCACHE_OFF)) - gd->arch.tlb_size = PGTABLE_SIZE; - gd->arch.tlb_addr = (unsigned long)&early_tlb; + gd->arch.tlb_size = PGTABLE_SIZE; + gd->arch.tlb_addr = (unsigned long)&early_tlb; #endif /* enable MMU (default configuration) */ dcache_enable(); +#endif } /* diff --git a/arch/arm/mach-stm32mp/stm32mp1/spl.c b/arch/arm/mach-stm32mp/stm32mp1/spl.c index 9c4fafbf478..e63bdaaf42f 100644 --- a/arch/arm/mach-stm32mp/stm32mp1/spl.c +++ b/arch/arm/mach-stm32mp/stm32mp1/spl.c @@ -220,10 +220,11 @@ void board_init_f(ulong dummy) * activate cache on DDR only when DDR is fully initialized * to avoid speculative access and issue in get_ram_size() */ - if (!CONFIG_IS_ENABLED(SYS_DCACHE_OFF)) + if (!CONFIG_IS_ENABLED(SYS_DCACHE_OFF) && !IS_ENABLED(CONFIG_STM32MP13X)) { mmu_set_region_dcache_behaviour(STM32_DDR_BASE, CONFIG_DDR_CACHEABLE_SIZE, DCACHE_DEFAULT_OPTION); + } } void spl_board_prepare_for_boot(void) diff --git a/arch/arm/mach-stm32mp/stm32mp1/stm32mp13x.c b/arch/arm/mach-stm32mp/stm32mp1/stm32mp13x.c index 4a811065fc3..79b2f2d0bba 100644 --- a/arch/arm/mach-stm32mp/stm32mp1/stm32mp13x.c +++ b/arch/arm/mach-stm32mp/stm32mp1/stm32mp13x.c @@ -6,11 +6,59 @@ #define LOG_CATEGORY LOGC_ARCH #include <config.h> +#include <cpu_func.h> #include <log.h> #include <syscon.h> #include <asm/io.h> +#include <asm/system.h> +#include <asm/arch/bsec.h> #include <asm/arch/stm32.h> #include <asm/arch/sys_proto.h> +#include <dm/device.h> +#include <dm/uclass.h> +#include <linux/bitfield.h> +#include <malloc.h> + +/* RCC register */ +#define RCC_TZCR (STM32_RCC_BASE + 0x00) +#define RCC_BDCR (STM32_RCC_BASE + 0x400) +#define RCC_DBGCFGR (STM32_RCC_BASE + 0x468) +#define RCC_MP_APB5ENSETR (STM32_RCC_BASE + 0x740) +#define RCC_MP_AHB6ENSETR (STM32_RCC_BASE + 0x780) + +#define RCC_BDCR_VSWRST BIT(31) +#define RCC_BDCR_RTCSRC GENMASK(17, 16) + +#define RCC_DBGCFGR_DBGCKEN BIT(8) + +/* DBGMCU register */ +#define DBGMCU_APB4FZ1 (STM32_DBGMCU_BASE + 0x2c) +#define DBGMCU_APB4FZ1_IWDG2 BIT(2) + +/* Security register */ +#define ETZPC_TZMA1_SIZE (STM32_ETZPC_BASE + 0x04) +#define ETZPC_DECPROT0 (STM32_ETZPC_BASE + 0x10) + +#define TZC_ACTION (STM32_TZC_BASE + 0x004) +#define TZC_GATE_KEEPER (STM32_TZC_BASE + 0x008) +#define TZC_REGION_BASE(n) (STM32_TZC_BASE + 0x100 + (0x20 * (n))) +#define TZC_REGION_TOP(n) (STM32_TZC_BASE + 0x108 + (0x20 * (n))) +#define TZC_REGION_ATTRIBUTE(n) (STM32_TZC_BASE + 0x110 + (0x20 * (n))) +#define TZC_REGION_ID_ACCESS(n) (STM32_TZC_BASE + 0x114 + (0x20 * (n))) + +#define TAMP_CR1 (STM32_TAMP_BASE + 0x00) + +#define PWR_CR1 (STM32_PWR_BASE + 0x00) +#define PWR_CR1_DBP BIT(8) + +/* boot interface from Bootrom + * - boot instance = bit 31:16 + * - boot device = bit 15:0 + */ +#define BOOTROM_MODE_MASK GENMASK(15, 0) +#define BOOTROM_MODE_SHIFT 0 +#define BOOTROM_INSTANCE_MASK GENMASK(31, 16) +#define BOOTROM_INSTANCE_SHIFT 16 /* SYSCFG register */ #define SYSCFG_IDC_OFFSET 0x380 @@ -23,6 +71,162 @@ #define RPN_SHIFT 0 #define RPN_MASK GENMASK(11, 0) +static void security_init(void) +{ + /* Disable the backup domain write protection */ + /* the protection is enable at each reset by hardware */ + /* And must be disable by software */ + setbits_le32(PWR_CR1, PWR_CR1_DBP); + + while (!(readl(PWR_CR1) & PWR_CR1_DBP)) + ; + + /* If RTC clock isn't enable so this is a cold boot then we need + * to reset the backup domain + */ + if (!(readl(RCC_BDCR) & RCC_BDCR_RTCSRC)) { + setbits_le32(RCC_BDCR, RCC_BDCR_VSWRST); + while (!(readl(RCC_BDCR) & RCC_BDCR_VSWRST)) + ; + clrbits_le32(RCC_BDCR, RCC_BDCR_VSWRST); + } + + /* allow non secure access in Write/Read for all peripheral */ + writel(0, ETZPC_DECPROT0); + + /* Open SYSRAM for no secure access */ + writel(0x0, ETZPC_TZMA1_SIZE); + + /* enable MCE clock */ + writel(BIT(1), RCC_MP_AHB6ENSETR); + + /* enable TZC clock */ + writel(BIT(11), RCC_MP_APB5ENSETR); + + /* Disable Filter 0 */ + writel(0, TZC_GATE_KEEPER); + + /* Region 0 set to no access by default */ + /* bit 0 / 16 => nsaid0 read/write Enable + * bit 1 / 17 => nsaid1 read/write Enable + * ... + * bit 15 / 31 => nsaid15 read/write Enable + */ + writel(0xFFFFFFFF, TZC_REGION_ID_ACCESS(0)); + + /* bit 30 / 31 => Secure Global Enable : write/read */ + writel(BIT(0) | BIT(30) | BIT(31), TZC_REGION_ATTRIBUTE(0)); + + writel(0xFFFFFFFF, TZC_REGION_ID_ACCESS(1)); + writel(0xC0000000, TZC_REGION_BASE(1)); + writel(0xDDFFFFFF, TZC_REGION_TOP(1)); + writel(BIT(0) | BIT(30) | BIT(31), TZC_REGION_ATTRIBUTE(1)); + + writel(0x00000000, TZC_REGION_ID_ACCESS(2)); + writel(0xDE000000, TZC_REGION_BASE(2)); + writel(0xDFFFFFFF, TZC_REGION_TOP(2)); + writel(BIT(0) | BIT(30) | BIT(31), TZC_REGION_ATTRIBUTE(2)); + + writel(0xFFFFFFFF, TZC_REGION_ID_ACCESS(3)); + writel(0x00000000, TZC_REGION_BASE(3)); + writel(0xBFFFFFFF, TZC_REGION_TOP(3)); + writel(BIT(0) | BIT(30) | BIT(31), TZC_REGION_ATTRIBUTE(3)); + + /* Set Action */ + writel(BIT(0), TZC_ACTION); + + /* Enable Filter 0 */ + writel(BIT(0), TZC_GATE_KEEPER); + + /* RCC trust zone deactivated */ + writel(0x0, RCC_TZCR); + + /* TAMP: deactivate the internal tamper + * Bit 23 ITAMP8E: monotonic counter overflow + * Bit 20 ITAMP5E: RTC calendar overflow + * Bit 19 ITAMP4E: HSE monitoring + * Bit 18 ITAMP3E: LSE monitoring + * Bit 16 ITAMP1E: RTC power domain supply monitoring + */ + writel(0x0, TAMP_CR1); +} + +/* + * Debug init + */ +void dbgmcu_init(void) +{ + /* + * Freeze IWDG2 if Cortex-A7 is in debug mode + * done in TF-A for TRUSTED boot and + * DBGMCU access is controlled by BSEC_DENABLE.DBGSWENABLE + */ + if (bsec_dbgswenable()) { + setbits_le32(RCC_DBGCFGR, RCC_DBGCFGR_DBGCKEN); + setbits_le32(DBGMCU_APB4FZ1, DBGMCU_APB4FZ1_IWDG2); + } +} + +void spl_board_init(void) +{ + struct udevice *dev; + u8 *tlb; + int ret; + + dbgmcu_init(); + + /* force probe of BSEC driver to shadow the upper OTP */ + ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(stm32mp_bsec), &dev); + if (ret) + log_warning("BSEC probe failed: %d\n", ret); + + /* Enable Dcache here, now that DRAM is available */ + if (IS_ENABLED(CONFIG_XPL_BUILD) && IS_ENABLED(CONFIG_STM32MP13X)) { + tlb = memalign(0x4000, PGTABLE_SIZE); + if (!tlb) + return; + + gd->arch.tlb_size = PGTABLE_SIZE; + gd->arch.tlb_addr = (unsigned long)tlb; + dcache_enable(); + } +} + +/* get bootmode from ROM code boot context: saved in TAMP register */ +static void update_bootmode(void) +{ + u32 boot_mode; + u32 bootrom_itf = readl(get_stm32mp_rom_api_table()); + u32 bootrom_device, bootrom_instance; + + /* enable TAMP clock = RTCAPBEN */ + writel(BIT(8), RCC_MP_APB5ENSETR); + + /* read bootrom context */ + bootrom_device = + (bootrom_itf & BOOTROM_MODE_MASK) >> BOOTROM_MODE_SHIFT; + bootrom_instance = + (bootrom_itf & BOOTROM_INSTANCE_MASK) >> BOOTROM_INSTANCE_SHIFT; + boot_mode = + ((bootrom_device << BOOT_TYPE_SHIFT) & BOOT_TYPE_MASK) | + ((bootrom_instance << BOOT_INSTANCE_SHIFT) & + BOOT_INSTANCE_MASK); + + /* save the boot mode in TAMP backup register */ + clrsetbits_le32(TAMP_BOOT_CONTEXT, + TAMP_BOOT_MODE_MASK, + boot_mode << TAMP_BOOT_MODE_SHIFT); +} + +/* weak function: STM32MP15x mach init for boot without TFA */ +void stm32mp_cpu_init(void) +{ + if (IS_ENABLED(CONFIG_XPL_BUILD)) { + security_init(); + update_bootmode(); + } +} + static u32 read_idc(void) { void *syscfg = syscon_get_first_range(STM32MP_SYSCON_SYSCFG); diff --git a/arch/arm/mach-stm32mp/stm32mp2/Makefile b/arch/arm/mach-stm32mp/stm32mp2/Makefile index 5dbf75daa76..27fbf3ae728 100644 --- a/arch/arm/mach-stm32mp/stm32mp2/Makefile +++ b/arch/arm/mach-stm32mp/stm32mp2/Makefile @@ -7,4 +7,5 @@ obj-y += cpu.o obj-y += arm64-mmu.o obj-y += rifsc.o obj-$(CONFIG_OF_SYSTEM_SETUP) += fdt.o +obj-$(CONFIG_STM32MP23X) += stm32mp23x.o obj-$(CONFIG_STM32MP25X) += stm32mp25x.o diff --git a/arch/arm/mach-stm32mp/stm32mp2/stm32mp23x.c b/arch/arm/mach-stm32mp/stm32mp2/stm32mp23x.c new file mode 100644 index 00000000000..022db60811a --- /dev/null +++ b/arch/arm/mach-stm32mp/stm32mp2/stm32mp23x.c @@ -0,0 +1,191 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause +/* + * Copyright (C) 2025, STMicroelectronics - All Rights Reserved + */ + +#define LOG_CATEGORY LOGC_ARCH + +#include <log.h> +#include <syscon.h> +#include <asm/io.h> +#include <asm/arch/stm32.h> +#include <asm/arch/sys_proto.h> + +/* SYSCFG register */ +#define SYSCFG_DEVICEID_OFFSET 0x6400 +#define SYSCFG_DEVICEID_DEV_ID_MASK GENMASK(11, 0) +#define SYSCFG_DEVICEID_DEV_ID_SHIFT 0 + +/* Revision ID = OTP102[5:0] 6 bits : 3 for Major / 3 for Minor*/ +#define REVID_SHIFT 0 +#define REVID_MASK GENMASK(5, 0) + +/* Device Part Number (RPN) = OTP9 */ +#define RPN_SHIFT 0 +#define RPN_MASK GENMASK(31, 0) + +/* Package = bit 0:2 of OTP122 => STM32MP23_PKG defines + * - 000: Custom package + * - 011: TFBGA361 => AL = 10x10, 361 balls pith 0.5mm + * - 100: TFBGA424 => AK = 14x14, 424 balls pith 0.5mm + * - 101: TFBGA436 => AI = 18x18, 436 balls pith 0.5mm + * - others: Reserved + */ +#define PKG_SHIFT 0 +#define PKG_MASK GENMASK(2, 0) + +static u32 read_deviceid(void) +{ + void *syscfg = syscon_get_first_range(STM32MP_SYSCON_SYSCFG); + + return readl(syscfg + SYSCFG_DEVICEID_OFFSET); +} + +u32 get_cpu_dev(void) +{ + return (read_deviceid() & SYSCFG_DEVICEID_DEV_ID_MASK) >> SYSCFG_DEVICEID_DEV_ID_SHIFT; +} + +u32 get_cpu_rev(void) +{ + return get_otp(BSEC_OTP_REVID, REVID_SHIFT, REVID_MASK); +} + +/* Get Device Part Number (RPN) from OTP */ +u32 get_cpu_type(void) +{ + return get_otp(BSEC_OTP_RPN, RPN_SHIFT, RPN_MASK); +} + +/* Get Package options from OTP */ +u32 get_cpu_package(void) +{ + return get_otp(BSEC_OTP_PKG, PKG_SHIFT, PKG_MASK); +} + +int get_eth_nb(void) +{ + int nb_eth; + + switch (get_cpu_type()) { + case CPU_STM32MP235Fxx: + fallthrough; + case CPU_STM32MP235Dxx: + fallthrough; + case CPU_STM32MP235Cxx: + fallthrough; + case CPU_STM32MP235Axx: + fallthrough; + case CPU_STM32MP233Fxx: + fallthrough; + case CPU_STM32MP233Dxx: + fallthrough; + case CPU_STM32MP233Cxx: + fallthrough; + case CPU_STM32MP233Axx: + nb_eth = 2; /* dual ETH */ + break; + case CPU_STM32MP231Fxx: + fallthrough; + case CPU_STM32MP231Dxx: + fallthrough; + case CPU_STM32MP231Cxx: + fallthrough; + case CPU_STM32MP231Axx: + nb_eth = 1; /* single ETH */ + break; + default: + nb_eth = 0; + break; + } + + return nb_eth; +} + +void get_soc_name(char name[SOC_NAME_SIZE]) +{ + char *cpu_s, *cpu_r, *package; + + cpu_s = "????"; + cpu_r = "?"; + package = "??"; + if (get_cpu_dev() == CPU_DEV_STM32MP23) { + switch (get_cpu_type()) { + case CPU_STM32MP235Fxx: + cpu_s = "235F"; + break; + case CPU_STM32MP235Dxx: + cpu_s = "235D"; + break; + case CPU_STM32MP235Cxx: + cpu_s = "235C"; + break; + case CPU_STM32MP235Axx: + cpu_s = "235A"; + break; + case CPU_STM32MP233Fxx: + cpu_s = "233F"; + break; + case CPU_STM32MP233Dxx: + cpu_s = "233D"; + break; + case CPU_STM32MP233Cxx: + cpu_s = "233C"; + break; + case CPU_STM32MP233Axx: + cpu_s = "233A"; + break; + case CPU_STM32MP231Fxx: + cpu_s = "231F"; + break; + case CPU_STM32MP231Dxx: + cpu_s = "231D"; + break; + case CPU_STM32MP231Cxx: + cpu_s = "231C"; + break; + case CPU_STM32MP231Axx: + cpu_s = "231A"; + break; + default: + cpu_s = "23??"; + break; + } + /* REVISION */ + switch (get_cpu_rev()) { + case OTP_REVID_1: + cpu_r = "A"; + break; + case OTP_REVID_2: + cpu_r = "B"; + break; + case OTP_REVID_2_1: + cpu_r = "Y"; + break; + case OTP_REVID_2_2: + cpu_r = "X"; + break; + default: + break; + } + /* PACKAGE */ + switch (get_cpu_package()) { + case STM32MP23_PKG_CUSTOM: + package = "XX"; + break; + case STM32MP23_PKG_AL_VFBGA361: + package = "AL"; + break; + case STM32MP23_PKG_AK_VFBGA424: + package = "AK"; + break; + case STM32MP23_PKG_AJ_TFBGA361: + package = "AJ"; + break; + default: + break; + } + } + + snprintf(name, SOC_NAME_SIZE, "STM32MP%s%s Rev.%s", cpu_s, package, cpu_r); +} diff --git a/arch/arm/mach-stm32mp/timers.c b/arch/arm/mach-stm32mp/timers.c index a3207895f40..1940ba42f74 100644 --- a/arch/arm/mach-stm32mp/timers.c +++ b/arch/arm/mach-stm32mp/timers.c @@ -10,6 +10,7 @@ #include <asm/io.h> #include <asm/arch/timers.h> #include <dm/device_compat.h> +#include <linux/bitfield.h> static void stm32_timers_get_arr_size(struct udevice *dev) { @@ -29,6 +30,33 @@ static void stm32_timers_get_arr_size(struct udevice *dev) writel(arr, plat->base + TIM_ARR); } +static int stm32_timers_probe_hwcfgr(struct udevice *dev) +{ + struct stm32_timers_plat *plat = dev_get_plat(dev); + struct stm32_timers_priv *priv = dev_get_priv(dev); + u32 val; + + if (!plat->ipidr) { + /* fallback to legacy method for probing counter width */ + stm32_timers_get_arr_size(dev); + return 0; + } + + val = readl(plat->base + TIM_IPIDR); + /* Sanity check on IP identification register */ + if (val != plat->ipidr) { + dev_err(dev, "Unexpected identification: %u\n", val); + return -EINVAL; + } + + val = readl(plat->base + TIM_HWCFGR2); + /* Counter width in bits, max reload value is BIT(width) - 1 */ + priv->max_arr = BIT(FIELD_GET(TIM_HWCFGR2_CNT_WIDTH, val)) - 1; + dev_dbg(dev, "TIM width: %ld\n", FIELD_GET(TIM_HWCFGR2_CNT_WIDTH, val)); + + return 0; +} + static int stm32_timers_of_to_plat(struct udevice *dev) { struct stm32_timers_plat *plat = dev_get_plat(dev); @@ -38,6 +66,7 @@ static int stm32_timers_of_to_plat(struct udevice *dev) dev_err(dev, "can't get address\n"); return -ENOENT; } + plat->ipidr = (u32)dev_get_driver_data(dev); return 0; } @@ -60,13 +89,16 @@ static int stm32_timers_probe(struct udevice *dev) priv->rate = clk_get_rate(&clk); - stm32_timers_get_arr_size(dev); + ret = stm32_timers_probe_hwcfgr(dev); + if (ret) + clk_disable(&clk); return ret; } static const struct udevice_id stm32_timers_ids[] = { { .compatible = "st,stm32-timers" }, + { .compatible = "st,stm32mp25-timers", .data = STM32MP25_TIM_IPIDR }, {} }; diff --git a/board/st/common/Kconfig b/board/st/common/Kconfig index 5efac658cf4..94ec806949b 100644 --- a/board/st/common/Kconfig +++ b/board/st/common/Kconfig @@ -1,7 +1,7 @@ config CMD_STBOARD bool "stboard - command for OTP board information" depends on ARCH_STM32MP - default y if TARGET_ST_STM32MP25X || TARGET_ST_STM32MP15X || TARGET_ST_STM32MP13X + default y if TARGET_ST_STM32MP13X || TARGET_ST_STM32MP15X || TARGET_ST_STM32MP23X || TARGET_ST_STM32MP25X help This compile the stboard command to read and write the board in the OTP. diff --git a/board/st/common/stpmic1.c b/board/st/common/stpmic1.c index 45c2bb5bcea..b46f89dacb9 100644 --- a/board/st/common/stpmic1.c +++ b/board/st/common/stpmic1.c @@ -14,8 +14,19 @@ #include <power/pmic.h> #include <power/stpmic1.h> +static bool is_stm32mp13xx(void) +{ + if (!IS_ENABLED(CONFIG_STM32MP13X)) + return false; + + return of_machine_is_compatible("st,stm32mp131") || + of_machine_is_compatible("st,stm32mp133") || + of_machine_is_compatible("st,stm32mp135"); +} + int board_ddr_power_init(enum ddr_type ddr_type) { + bool is_mp13 = is_stm32mp13xx(); struct udevice *dev; bool buck3_at_1800000v = false; int ret; @@ -30,18 +41,21 @@ int board_ddr_power_init(enum ddr_type ddr_type) switch (ddr_type) { case STM32MP_DDR3: /* VTT = Set LDO3 to sync mode */ - ret = pmic_reg_read(dev, STPMIC1_LDOX_MAIN_CR(STPMIC1_LDO3)); - if (ret < 0) - return ret; - - ret &= ~STPMIC1_LDO3_MODE; - ret &= ~STPMIC1_LDO12356_VOUT_MASK; - ret |= STPMIC1_LDO_VOUT(STPMIC1_LDO3_DDR_SEL); - - ret = pmic_reg_write(dev, STPMIC1_LDOX_MAIN_CR(STPMIC1_LDO3), - ret); - if (ret < 0) - return ret; + if (!is_mp13) { + /* Enable VTT only on STM32MP15xx */ + ret = pmic_reg_read(dev, STPMIC1_LDOX_MAIN_CR(STPMIC1_LDO3)); + if (ret < 0) + return ret; + + ret &= ~STPMIC1_LDO3_MODE; + ret &= ~STPMIC1_LDO12356_VOUT_MASK; + ret |= STPMIC1_LDO_VOUT(STPMIC1_LDO3_DDR_SEL); + + ret = pmic_reg_write(dev, STPMIC1_LDOX_MAIN_CR(STPMIC1_LDO3), + ret); + if (ret < 0) + return ret; + } /* VDD_DDR = Set BUCK2 to 1.35V */ ret = pmic_clrsetbits(dev, @@ -69,11 +83,14 @@ int board_ddr_power_init(enum ddr_type ddr_type) mdelay(STPMIC1_DEFAULT_START_UP_DELAY_MS); /* Enable VTT = LDO3 */ - ret = pmic_clrsetbits(dev, - STPMIC1_LDOX_MAIN_CR(STPMIC1_LDO3), - STPMIC1_LDO_ENA, STPMIC1_LDO_ENA); - if (ret < 0) - return ret; + if (!is_mp13) { + /* Enable VTT only on STM32MP15xx */ + ret = pmic_clrsetbits(dev, + STPMIC1_LDOX_MAIN_CR(STPMIC1_LDO3), + STPMIC1_LDO_ENA, STPMIC1_LDO_ENA); + if (ret < 0) + return ret; + } mdelay(STPMIC1_DEFAULT_START_UP_DELAY_MS); diff --git a/board/st/stm32mp1/debug_uart.c b/board/st/stm32mp1/debug_uart.c index 24e3f9f2201..4c2149e0480 100644 --- a/board/st/stm32mp1/debug_uart.c +++ b/board/st/stm32mp1/debug_uart.c @@ -9,17 +9,32 @@ #include <asm/arch/stm32.h> #include <linux/bitops.h> +#if IS_ENABLED(CONFIG_STM32MP13X) +#define RCC_MP_APB1ENSETR (STM32_RCC_BASE + 0x0700) +#define RCC_MP_AHB4ENSETR (STM32_RCC_BASE + 0x0768) +#elif IS_ENABLED(CONFIG_STM32MP15X) #define RCC_MP_APB1ENSETR (STM32_RCC_BASE + 0x0A00) #define RCC_MP_AHB4ENSETR (STM32_RCC_BASE + 0x0A28) +#endif +#define GPIOA_BASE 0x50002000 #define GPIOG_BASE 0x50008000 void board_debug_uart_init(void) { - if (CONFIG_DEBUG_UART_BASE == STM32_UART4_BASE) { - /* UART4 clock enable */ - setbits_le32(RCC_MP_APB1ENSETR, BIT(16)); + if (CONFIG_DEBUG_UART_BASE != STM32_UART4_BASE) + return; + /* UART4 clock enable */ + setbits_le32(RCC_MP_APB1ENSETR, BIT(16)); + + if (IS_ENABLED(CONFIG_STM32MP13X)) { + /* GPIOA clock enable */ + writel(BIT(0), RCC_MP_AHB4ENSETR); + /* GPIO configuration for DH boards: Uart4 TX = A9 */ + writel(0xfffbffff, GPIOA_BASE + 0x00); + writel(0x00000080, GPIOA_BASE + 0x24); + } else if (IS_ENABLED(CONFIG_STM32MP15X)) { /* GPIOG clock enable */ writel(BIT(6), RCC_MP_AHB4ENSETR); /* GPIO configuration for ST boards: Uart4 TX = G11 */ diff --git a/board/st/stm32mp2/Kconfig b/board/st/stm32mp2/Kconfig index f91e25f1f9a..e88c71a278e 100644 --- a/board/st/stm32mp2/Kconfig +++ b/board/st/stm32mp2/Kconfig @@ -1,3 +1,17 @@ +if TARGET_ST_STM32MP23X + +config SYS_BOARD + default "stm32mp2" + +config SYS_VENDOR + default "st" + +config SYS_CONFIG_NAME + default "stm32mp23_st_common" + +source "board/st/common/Kconfig" +endif + if TARGET_ST_STM32MP25X config SYS_BOARD diff --git a/configs/stm32mp13_defconfig b/configs/stm32mp13_defconfig index 18ec7f4601e..3283e910219 100644 --- a/configs/stm32mp13_defconfig +++ b/configs/stm32mp13_defconfig @@ -48,6 +48,8 @@ CONFIG_CMD_EXT4_WRITE=y CONFIG_CMD_LOG=y CONFIG_CMD_UBI=y CONFIG_OF_LIVE=y +CONFIG_OF_UPSTREAM_BUILD_VENDOR=y +CONFIG_OF_UPSTREAM_VENDOR="st" CONFIG_ENV_IS_NOWHERE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_REDUNDANT=y diff --git a/configs/stm32mp13_dhcor_defconfig b/configs/stm32mp13_dhcor_defconfig index e5aaadd3920..c21416459e6 100644 --- a/configs/stm32mp13_dhcor_defconfig +++ b/configs/stm32mp13_dhcor_defconfig @@ -2,7 +2,6 @@ CONFIG_ARM=y CONFIG_ARCH_STM32MP=y -CONFIG_TFABOOT=y CONFIG_SYS_MALLOC_F_LEN=0x1c0000 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc0400000 CONFIG_ENV_OFFSET=0x3E0000 @@ -12,11 +11,16 @@ CONFIG_DDR_CACHEABLE_SIZE=0x8000000 CONFIG_TARGET_ST_STM32MP13X=y CONFIG_ENV_OFFSET_REDUND=0x3F0000 CONFIG_STM32MP15_PWR=y -# CONFIG_ARMV7_NONSEC is not set +CONFIG_ARMV7_NONSEC=y +CONFIG_ARMV7_BOOT_SEC_DEFAULT=y +CONFIG_ARMV7_PSCI_NR_CPUS=2 +# CONFIG_ARMV7_LPAE is not set CONFIG_SYS_MEMTEST_START=0xc0000000 CONFIG_SYS_MEMTEST_END=0xc4000000 +CONFIG_SYS_MEM_TOP_HIDE=0x2000000 CONFIG_BOOTSTAGE_RECORD_COUNT=100 CONFIG_BOOTDELAY=3 +CONFIG_BOOTM_OPTEE=y CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_CMD_ASKENV=y CONFIG_CMD_ERASEENV=y @@ -31,20 +35,28 @@ CONFIG_ENV_IS_NOWHERE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_MMC_USE_DT=y CONFIG_ENV_SPI_MAX_HZ=50000000 -CONFIG_CLK_SCMI=y CONFIG_SET_DFU_ALT_INFO=y CONFIG_SYS_I2C_EEPROM_ADDR=0x50 CONFIG_ENV_MMC_DEVICE_INDEX=0 CONFIG_ENV_MMC_EMMC_HW_PARTITION=1 CONFIG_PHY_REALTEK=y -CONFIG_DM_REGULATOR_SCMI=y -CONFIG_RESET_SCMI=y CONFIG_DM_RNG=y CONFIG_RNG_STM32=y -CONFIG_SYSRESET_PSCI=y -CONFIG_TEE=y -CONFIG_OPTEE=y -# CONFIG_OPTEE_TA_AVB is not set CONFIG_USB_ONBOARD_HUB=y CONFIG_USB_HUB_DEBOUNCE_TIMEOUT=2000 CONFIG_ERRNO_STR=y +CONFIG_OPTEE_LIB=y +CONFIG_OPTEE_IMAGE=y +CONFIG_OPTEE_TZDRAM_SIZE=0x02000000 +CONFIG_SPL_TEXT_BASE=0x2FFE0000 +CONFIG_SPL_CLK_CCF=y +CONFIG_SPL_CLK_COMPOSITE_CCF=y +# CONFIG_SPL_SHA1 is not set +# CONFIG_SPL_SHA256 is not set +CONFIG_SPL_HAVE_INIT_STACK=y +CONFIG_SPL_SYS_MALLOC_F_LEN=0x8000 +CONFIG_SPL_PINCTRL=y +CONFIG_SPL_PINCTRL_GENERIC=y +CONFIG_SPL_PINMUX=y +CONFIG_SPL_PINCONF=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0x80000 diff --git a/configs/stm32mp15_dhsom.config b/configs/stm32mp15_dhsom.config index 565b49584e3..210ec201bf5 100644 --- a/configs/stm32mp15_dhsom.config +++ b/configs/stm32mp15_dhsom.config @@ -2,10 +2,6 @@ # CONFIG_ARMV7_VIRT is not set # CONFIG_BINMAN_FDT is not set -# CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_SPL_PARTITION_UUIDS is not set -# CONFIG_SPL_PINCTRL_FULL is not set -# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_BOARD_EARLY_INIT_F=y CONFIG_BOARD_SIZE_LIMIT=1441792 CONFIG_BOOTCOUNT_BOOTLIMIT=3 @@ -20,9 +16,7 @@ CONFIG_CMD_STM32PROG_OTP=y CONFIG_CONSOLE_MUX=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc0100000 CONFIG_DM_HWSPINLOCK=y -CONFIG_DM_REGULATOR_STM32_VREFBUF=y CONFIG_HAS_BOARD_SIZE_LIMIT=y -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_HWSPINLOCK_STM32=y CONFIG_KS8851_MLL=y CONFIG_OF_SPL_REMOVE_PROPS="interrupts interrupt-names interrupts-extended interrupt-controller \\\#interrupt-cells interrupt-parent dmas dma-names assigned-clocks assigned-clock-rates assigned-clock-parents hwlocks access-controllers" @@ -31,42 +25,7 @@ CONFIG_PINCTRL_STMFX=y CONFIG_REMOTEPROC_STM32_COPRO=y CONFIG_SERVERIP="192.168.1.1" CONFIG_SF_DEFAULT_SPEED=50000000 -CONFIG_SPL=y -CONFIG_SPL_BLOCK_CACHE=y -CONFIG_SPL_BOOTCOUNT_LIMIT=y -CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0xc0300000 -CONFIG_SPL_DFU=y -CONFIG_SPL_DM_REGULATOR=y -CONFIG_SPL_DM_REGULATOR_STPMIC1=y -CONFIG_SPL_DM_SPI=y -CONFIG_SPL_DM_SPI_FLASH=y -CONFIG_SPL_DM_USB_GADGET=y -CONFIG_SPL_ENV_IS_NOWHERE=y -CONFIG_SPL_ENV_SUPPORT=y -CONFIG_SPL_FOOTPRINT_LIMIT=y -CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y -CONFIG_SPL_I2C=y -CONFIG_SPL_LEGACY_IMAGE_FORMAT=y -CONFIG_SPL_LOAD_FIT=y -CONFIG_SPL_LOAD_FIT_ADDRESS=0xc1000000 -CONFIG_SPL_MAX_FOOTPRINT=0x3db00 -CONFIG_SPL_MMC=y -CONFIG_SPL_MTD=y -CONFIG_SPL_PHY=y -CONFIG_SPL_POWER=y -CONFIG_SPL_RAM_DEVICE=y -CONFIG_SPL_SPI=y -CONFIG_SPL_SPI_FLASH_MTD=y -CONFIG_SPL_SPI_FLASH_SUPPORT=y -CONFIG_SPL_HAVE_INIT_STACK=y -CONFIG_SPL_STACK=0x30000000 -CONFIG_SPL_SYS_MALLOC=y -CONFIG_SPL_SYS_MALLOC_SIZE=0x1d00000 -CONFIG_SPL_SYS_MMCSD_RAW_MODE=y -CONFIG_SPL_TEXT_BASE=0x2FFC2500 -CONFIG_SPL_USB_GADGET=y CONFIG_STM32_ADC=y -CONFIG_SYSRESET_SYSCON=y CONFIG_SYS_BOOTCOUNT_ADDR=0x5C00A14C CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION=0x3 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y @@ -77,3 +36,10 @@ CONFIG_SYS_SPI_U_BOOT_OFFS=0x80000 CONFIG_TARGET_DH_STM32MP1_PDK2=y CONFIG_USE_SERVERIP=y CONFIG_WATCHDOG_AUTOSTART=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPL_LEGACY_IMAGE_FORMAT=y +CONFIG_SPL_TEXT_BASE=0x2FFC2500 +CONFIG_SPL_BLOCK_CACHE=y +CONFIG_SPL_MMC=y diff --git a/configs/stm32mp23_defconfig b/configs/stm32mp23_defconfig new file mode 100644 index 00000000000..3f8fa6ce527 --- /dev/null +++ b/configs/stm32mp23_defconfig @@ -0,0 +1,82 @@ +CONFIG_ARM=y +CONFIG_ARCH_STM32MP=y +CONFIG_SYS_MALLOC_F_LEN=0x600000 +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x90000000 +CONFIG_ENV_OFFSET=0x900000 +CONFIG_ENV_SECT_SIZE=0x40000 +CONFIG_DEFAULT_DEVICE_TREE="st/stm32mp235f-dk" +CONFIG_SYS_BOOTM_LEN=0x2000000 +CONFIG_SYS_LOAD_ADDR=0x84000000 +CONFIG_STM32MP23X=y +CONFIG_DDR_CACHEABLE_SIZE=0x10000000 +CONFIG_CMD_STM32KEY=y +CONFIG_ENV_OFFSET_REDUND=0x940000 +CONFIG_TARGET_ST_STM32MP23X=y +CONFIG_SYS_MEMTEST_START=0x84000000 +CONFIG_SYS_MEMTEST_END=0x88000000 +CONFIG_API=y +CONFIG_SYS_MMC_MAX_DEVICE=3 +CONFIG_FIT=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_BOOTDELAY=1 +CONFIG_BOOTCOMMAND="run bootcmd_stm32mp" +CONFIG_SYS_PROMPT="STM32MP> " +# CONFIG_CMD_BDI is not set +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_ADTIMG=y +# CONFIG_CMD_ELF is not set +CONFIG_CMD_MEMINFO=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_CLK=y +CONFIG_CMD_FUSE=y +CONFIG_CMD_GPIO=y +# CONFIG_CMD_LOADB is not set +CONFIG_CMD_MMC=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_TIME=y +CONFIG_CMD_RNG=y +CONFIG_CMD_TIMER=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_LOG=y +CONFIG_CMD_UBI=y +CONFIG_OF_LIVE=y +CONFIG_OF_UPSTREAM_BUILD_VENDOR=y +CONFIG_OF_UPSTREAM_VENDOR="st" +CONFIG_ENV_IS_NOWHERE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_ENV_IS_IN_UBI=y +CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_ENV_UBI_PART="UBI" +CONFIG_ENV_UBI_VOLUME="uboot_config" +CONFIG_ENV_UBI_VOLUME_REDUND="uboot_config_r" +CONFIG_SYS_MMC_ENV_DEV=-1 +CONFIG_NO_NET=y +CONFIG_SYS_64BIT_LBA=y +CONFIG_BUTTON=y +CONFIG_BUTTON_GPIO=y +CONFIG_GPIO_HOG=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_STM32F7=y +CONFIG_LED=y +CONFIG_LED_GPIO=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_STM32_SDMMC2=y +CONFIG_MTD=y +CONFIG_USE_SYS_MAX_FLASH_BANKS=y +CONFIG_SPI_FLASH=y +CONFIG_PINCONF=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_RAM=y +# CONFIG_STM32MP1_DDR is not set +CONFIG_DM_RNG=y +CONFIG_SERIAL_RX_BUFFER=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +# CONFIG_OPTEE_TA_AVB is not set +CONFIG_WDT=y +CONFIG_WDT_STM32MP=y +CONFIG_WDT_ARM_SMC=y +# CONFIG_UBIFS_SILENCE_DEBUG_DUMP is not set +CONFIG_ERRNO_STR=y diff --git a/configs/stm32mp25_defconfig b/configs/stm32mp25_defconfig index a10f090c347..14619ffd96c 100644 --- a/configs/stm32mp25_defconfig +++ b/configs/stm32mp25_defconfig @@ -9,6 +9,7 @@ CONFIG_SYS_BOOTM_LEN=0x2000000 CONFIG_SYS_LOAD_ADDR=0x84000000 CONFIG_STM32MP25X=y CONFIG_DDR_CACHEABLE_SIZE=0x10000000 +CONFIG_MFD_STM32_TIMERS=y CONFIG_ENV_OFFSET_REDUND=0x940000 CONFIG_TARGET_ST_STM32MP25X=y CONFIG_SYS_MEMTEST_START=0x84000000 @@ -29,6 +30,7 @@ CONFIG_CMD_MEMTEST=y CONFIG_CMD_CLK=y CONFIG_CMD_FUSE=y CONFIG_CMD_GPIO=y +CONFIG_CMD_PWM=y # CONFIG_CMD_LOADB is not set CONFIG_CMD_MMC=y CONFIG_CMD_CACHE=y @@ -65,6 +67,8 @@ CONFIG_SPI_FLASH=y CONFIG_PINCONF=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_PWM=y +CONFIG_PWM_STM32=y CONFIG_RAM=y # CONFIG_STM32MP1_DDR is not set CONFIG_DM_RNG=y diff --git a/configs/stm32mp_dhsom.config b/configs/stm32mp_dhsom.config index 777a02dfe15..56a40839d28 100644 --- a/configs/stm32mp_dhsom.config +++ b/configs/stm32mp_dhsom.config @@ -2,6 +2,10 @@ # CONFIG_CMD_EXPORTENV is not set # CONFIG_EFI_LOADER is not set # CONFIG_ISO_PARTITION is not set +# CONFIG_SPL_DOS_PARTITION is not set +# CONFIG_SPL_PARTITION_UUIDS is not set +# CONFIG_SPL_PINCTRL_FULL is not set +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_BOOTCOMMAND="run bootcmd_stm32mp" CONFIG_BOOTCOUNT_LIMIT=y CONFIG_CMD_BOOTCOUNT=y @@ -38,6 +42,7 @@ CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y CONFIG_DM_REGULATOR_STPMIC1=y +CONFIG_DM_REGULATOR_STM32_VREFBUF=y CONFIG_DM_RTC=y CONFIG_DM_SPI=y CONFIG_DM_SPI_FLASH=y @@ -49,6 +54,7 @@ CONFIG_ENV_SIZE=0x4000 CONFIG_FAT_WRITE=y CONFIG_FIT=y CONFIG_GPIO_HOG=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_I2C_EEPROM=y CONFIG_IPV6=y CONFIG_IP_DEFRAG=y @@ -58,6 +64,7 @@ CONFIG_MTD=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_OF_LIVE=y CONFIG_OF_UPSTREAM=y +CONFIG_OF_SPL_REMOVE_PROPS="interrupts interrupt-names interrupts-extended interrupt-controller \\\#interrupt-cells interrupt-parent dmas dma-names assigned-clocks assigned-clock-rates assigned-clock-parents hwlocks" CONFIG_PHY=y CONFIG_PHY_STM32_USBPHYC=y CONFIG_PINCONF=y @@ -66,17 +73,39 @@ CONFIG_PROT_TCP_SACK=y CONFIG_RTC_STM32=y CONFIG_SERIAL_RX_BUFFER=y CONFIG_SPI=y -CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_MTD=y CONFIG_SPI_FLASH_SFDP_SUPPORT=y -CONFIG_SPI_FLASH_SPANSION=y -CONFIG_SPI_FLASH_STMICRO=y CONFIG_SPI_FLASH_WINBOND=y +CONFIG_SPL=y +CONFIG_SPL_BOOTCOUNT_LIMIT=y +CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0xc0300000 +CONFIG_SPL_DFU=y +CONFIG_SPL_DM_SPI=y +CONFIG_SPL_DM_SPI_FLASH=y +CONFIG_SPL_ENV_IS_NOWHERE=y +CONFIG_SPL_ENV_SUPPORT=y +CONFIG_SPL_FOOTPRINT_LIMIT=y +CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y +CONFIG_SPL_I2C=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_LOAD_FIT_ADDRESS=0xc1000000 +CONFIG_SPL_MAX_FOOTPRINT=0x3db00 +CONFIG_SPL_MTD=y +CONFIG_SPL_PHY=y +CONFIG_SPL_POWER=y +CONFIG_SPL_RAM_DEVICE=y +CONFIG_SPL_SPI=y +CONFIG_SPL_SPI_FLASH_MTD=y +CONFIG_SPL_SPI_FLASH_SUPPORT=y +CONFIG_SPL_STACK=0x30000000 +CONFIG_SPL_SYS_MALLOC=y +CONFIG_SPL_SYS_MALLOC_SIZE=0x1d00000 CONFIG_STM32_FMC2_EBI=y CONFIG_STM32_QSPI=y CONFIG_STM32_SDMMC2=y CONFIG_STM32_SPI=y CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_SYSRESET_SYSCON=y CONFIG_SYS_BOOTCOUNT_MAGIC=0xB0C40000 CONFIG_SYS_BOOTM_LEN=0x2000000 CONFIG_SYS_DISABLE_AUTOLOAD=y diff --git a/doc/usage/environment.rst b/doc/usage/environment.rst index bb6c351b441..77197d79380 100644 --- a/doc/usage/environment.rst +++ b/doc/usage/environment.rst @@ -335,6 +335,15 @@ netretry Useful on scripts which control the retry operation themselves. +phy_aneg_timeout + If set, the specified value will override CONFIG_PHY_ANEG_TIMEOUT. + This variable has the same base and unit as CONFIG_PHY_ANEG_TIMEOUT + which is "decimal" and "millisecond" respectively. The default value + of CONFIG_PHY_ANEG_TIMEOUT may be sufficient for most use-cases, but + certain link-partners may require a larger timeout due to the Ethernet + PHY they use. Alternatively, the timeout can be reduced as well if the + use-case demands it. + rng_seed_size Size of random value added to device-tree node /chosen/rng-seed. This variable is given as a decimal number. diff --git a/drivers/clk/clk_scmi.c b/drivers/clk/clk_scmi.c index cfb372e6190..0c9a81cabcc 100644 --- a/drivers/clk/clk_scmi.c +++ b/drivers/clk/clk_scmi.c @@ -336,8 +336,8 @@ static int scmi_clk_probe(struct udevice *dev) static int __scmi_clk_set_parent(struct clk *clk, struct clk *parent) { struct scmi_clk_parent_set_in in = { - .clock_id = clk->id, - .parent_clk = parent->id, + .clock_id = clk_get_id(clk), + .parent_clk = clk_get_id(parent), }; struct scmi_clk_parent_set_out out; struct scmi_msg msg = SCMI_MSG_IN(SCMI_PROTOCOL_ID_CLOCK, diff --git a/drivers/clk/stm32/clk-stm32h7.c b/drivers/clk/stm32/clk-stm32h7.c index aa3be414a29..df82db69738 100644 --- a/drivers/clk/stm32/clk-stm32h7.c +++ b/drivers/clk/stm32/clk-stm32h7.c @@ -549,8 +549,8 @@ static u32 stm32_get_PLL1_rate(struct stm32_rcc_regs *regs, divr1 = readl(®s->pll1divr) & RCC_PLL1DIVR_DIVR1_MASK; divr1 = (divr1 >> RCC_PLL1DIVR_DIVR1_SHIFT) + 1; - fracn1 = readl(®s->pll1fracr) & RCC_PLL1DIVR_DIVR1_MASK; - fracn1 = fracn1 & RCC_PLL1DIVR_DIVR1_SHIFT; + fracn1 = readl(®s->pll1fracr) & RCC_PLL1FRACR_FRACN1_MASK; + fracn1 = (fracn1 >> RCC_PLL1FRACR_FRACN1_SHIFT) + 1; vco = (pllsrc / divm1) * divn1; rate = (pllsrc * fracn1) / (divm1 * 8192); diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index d942fa4e202..d1cb69f85ad 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -138,30 +138,6 @@ config ALTERA_TSE Please find details on the "Triple-Speed Ethernet MegaCore Function Resource Center" of Altera. -config BCM_SF2_ETH - bool "Broadcom SF2 (Starfighter2) Ethernet support" - select PHYLIB - help - This is an abstract framework which provides a generic interface - to MAC and DMA management for multiple Broadcom SoCs such as - Cygnus, NSP and bcm28155_ap platforms. - -config BCM_SF2_ETH_DEFAULT_PORT - int "Broadcom SF2 (Starfighter2) Ethernet default port number" - depends on BCM_SF2_ETH - default 0 - help - Default port number for the Starfighter2 ethernet driver. - -config BCM_SF2_ETH_GMAC - bool "Broadcom SF2 (Starfighter2) GMAC Ethernet support" - depends on BCM_SF2_ETH - help - This flag enables the ethernet support for Broadcom platforms with - GMAC such as Cygnus. This driver is based on the framework provided - by the BCM_SF2_ETH driver. - Say Y to any bcmcygnus based platforms. - config BCM6348_ETH bool "BCM6348 EMAC support" depends on ARCH_BMIPS @@ -197,6 +173,7 @@ config CORTINA_NI_ENET config CALXEDA_XGMAC bool "Calxeda XGMAC support" + depends on ARCH_HIGHBANK help This driver supports the XGMAC in Calxeda Highbank and Midway machines. @@ -246,14 +223,14 @@ config DWC_ETH_QOS config DWC_ETH_QOS_ADI bool "Synopsys DWC Ethernet QOS device support for ADI SC59x-64 parts" - depends on DWC_ETH_QOS + depends on DWC_ETH_QOS && ARCH_SC5XX help The Synopsis Designware Ethernet QoS IP block with the specific configuration used in the ADI ADSP-SC59X 64 bit SoCs config DWC_ETH_QOS_IMX bool "Synopsys DWC Ethernet QOS device support for IMX" - depends on DWC_ETH_QOS + depends on DWC_ETH_QOS && MACH_IMX help The Synopsys Designware Ethernet QOS IP block with the specific configuration used in IMX soc. @@ -267,7 +244,7 @@ config DWC_ETH_QOS_INTEL config DWC_ETH_QOS_ROCKCHIP bool "Synopsys DWC Ethernet QOS device support for Rockchip SoCs" - depends on DWC_ETH_QOS + depends on DWC_ETH_QOS && ARCH_ROCKCHIP select DM_ETH_PHY help The Synopsys Designware Ethernet QOS IP block with specific @@ -275,7 +252,7 @@ config DWC_ETH_QOS_ROCKCHIP config DWC_ETH_QOS_STM32 bool "Synopsys DWC Ethernet QOS device support for STM32" - depends on DWC_ETH_QOS + depends on DWC_ETH_QOS && ARCH_STM32MP select DM_ETH_PHY default y if ARCH_STM32MP help @@ -327,7 +304,7 @@ config E1000_SPI_GENERIC config E1000_SPI bool "Enable SPI bus utility code" - depends on E1000 + depends on E1000 && !E1000_NO_NVM help Utility code for direct access to the SPI bus on Intel 8257x. This does not do anything useful unless you set at least one @@ -343,6 +320,7 @@ config CMD_E1000 config EEPRO100 bool "Intel PRO/100 82557/82559/82559ER Fast Ethernet support" + depends on !64BIT help This driver supports Intel(R) PRO/100 82557/82559/82559ER fast ethernet family of adapters. @@ -406,7 +384,7 @@ config ETH_DESIGNWARE_SOCFPGA config ETH_DESIGNWARE_S700 bool "Actins S700 glue driver for Synopsys Designware Ethernet MAC" - depends on ETH_DESIGNWARE + depends on ETH_DESIGNWARE && ARCH_OWL help This provides glue layer to use Synopsys Designware Ethernet MAC present on Actions S700 SoC. @@ -448,7 +426,7 @@ config FEC_MXC config FMAN_ENET bool "Freescale FMan ethernet support" - depends on ARM || PPC + depends on FSL_LSCH2 || PPC select SYS_FMAN_V3 if ARCH_B4420 || ARCH_B4860 || ARCH_LS1043A || \ ARCH_LS1046A || ARCH_T1024 || ARCH_T1040 || ARCH_T1042 || \ ARCH_T2080 || ARCH_T4240 @@ -520,6 +498,7 @@ config SYS_DISCOVER_PHY config MCFFEC bool "ColdFire Ethernet Support" + depends on M68K select PHYLIB select SYS_DISCOVER_PHY help @@ -583,6 +562,7 @@ config MVPP2 config MACB bool "Cadence MACB/GEM Ethernet Interface" + depends on ARM || RISCV select PHYLIB help The Cadence MACB ethernet interface is found on many Atmel @@ -619,6 +599,7 @@ config MT7628_ETH config NET_NPCM750 bool "Nuvoton NPCM750 Ethernet MAC" + depends on ARCH_NPCM help support NPCM750 EMAC @@ -693,6 +674,7 @@ source "drivers/net/qe/Kconfig" config RTL8139 bool "Realtek 8139 series Ethernet controller driver" + depends on !64BIT help This driver supports Realtek 8139 series fast ethernet family of PCI chipsets/adapters. @@ -746,6 +728,7 @@ config SUN7I_GMAC_FORCE_TXERR config SUN4I_EMAC bool "Allwinner Sun4i Ethernet MAC support" + depends on ARCH_SUNXI select PHYLIB help This driver supports the Allwinner based SUN4I Ethernet MAC. @@ -761,6 +744,7 @@ config SUN8I_EMAC config SH_ETHER bool "Renesas SH Ethernet MAC" + depends on ARCH_RENESAS select PHYLIB select PHY_ETHERNET_ID help @@ -770,6 +754,7 @@ source "drivers/net/ti/Kconfig" config TULIP bool "DEC Tulip DC2114x Ethernet support" + depends on !64BIT help This driver supports DEC DC2114x Fast ethernet chips. @@ -823,6 +808,7 @@ config XILINX_AXIMRMAC config VSC7385_ENET bool "Vitesse 7385 Switch Firmware Upload driver" + depends on !COMPILE_TEST && PPC config XILINX_EMACLITE select PHYLIB @@ -834,6 +820,7 @@ config XILINX_EMACLITE config ZYNQ_GEM select PHYLIB bool "Xilinx Ethernet GEM" + depends on ARCH_VERSAL || ARCH_VERSAL_NET || ARCH_VERSAL2 || ARCH_ZYNQ || ARCH_ZYNQMP help This MAC is present in Xilinx Zynq and ZynqMP SoCs. @@ -847,7 +834,7 @@ config PIC32_ETH config GMAC_ROCKCHIP bool "Rockchip Synopsys Designware Ethernet MAC" - depends on ETH_DESIGNWARE + depends on ETH_DESIGNWARE && ARCH_ROCKCHIP help This driver provides Rockchip SoCs network support based on the Synopsys Designware driver. @@ -974,6 +961,7 @@ config SYS_FSL_QMAN_V3 config TSEC_ENET select PHYLIB bool "Enable Three-Speed Ethernet Controller" + depends on ARCH_LS1021A || PPC help This driver implements support for the (Enhanced) Three-Speed Ethernet Controller found on Freescale SoCs. diff --git a/drivers/net/Makefile b/drivers/net/Makefile index 79cc8b422b0..f8f9a71f815 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile @@ -11,8 +11,6 @@ obj-$(CONFIG_ASPEED_MDIO) += aspeed_mdio.o obj-$(CONFIG_BCM6348_ETH) += bcm6348-eth.o obj-$(CONFIG_BCM6368_ETH) += bcm6368-eth.o obj-$(CONFIG_BCMGENET) += bcmgenet.o -obj-$(CONFIG_BCM_SF2_ETH) += bcm-sf2-eth.o -obj-$(CONFIG_BCM_SF2_ETH_GMAC) += bcm-sf2-eth-gmac.o obj-$(CONFIG_BNXT_ETH) += bnxt/ obj-$(CONFIG_CALXEDA_XGMAC) += calxedaxgmac.o obj-$(CONFIG_CORTINA_NI_ENET) += cortina_ni.o diff --git a/drivers/net/bcm-sf2-eth-gmac.c b/drivers/net/bcm-sf2-eth-gmac.c deleted file mode 100644 index ba244b4a26e..00000000000 --- a/drivers/net/bcm-sf2-eth-gmac.c +++ /dev/null @@ -1,976 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2014-2017 Broadcom. - */ - -#ifdef BCM_GMAC_DEBUG -#ifndef DEBUG -#define DEBUG -#include <linux/printk.h> -#endif -#endif - -#include <config.h> -#include <cpu_func.h> -#include <log.h> -#include <malloc.h> -#include <net.h> -#include <asm/cache.h> -#include <asm/io.h> -#include <phy.h> -#include <linux/delay.h> -#include <linux/bitops.h> - -#include "bcm-sf2-eth.h" -#include "bcm-sf2-eth-gmac.h" - -#define SPINWAIT(exp, us) { \ - uint countdown = (us) + 9; \ - while ((exp) && (countdown >= 10)) {\ - udelay(10); \ - countdown -= 10; \ - } \ -} - -#define RX_BUF_SIZE_ALIGNED ALIGN(RX_BUF_SIZE, ARCH_DMA_MINALIGN) -#define TX_BUF_SIZE_ALIGNED ALIGN(TX_BUF_SIZE, ARCH_DMA_MINALIGN) -#define DESCP_SIZE_ALIGNED ALIGN(sizeof(dma64dd_t), ARCH_DMA_MINALIGN) - -static int gmac_disable_dma(struct eth_dma *dma, int dir); -static int gmac_enable_dma(struct eth_dma *dma, int dir); - -/* DMA Descriptor */ -typedef struct { - /* misc control bits */ - uint32_t ctrl1; - /* buffer count and address extension */ - uint32_t ctrl2; - /* memory address of the date buffer, bits 31:0 */ - uint32_t addrlow; - /* memory address of the date buffer, bits 63:32 */ - uint32_t addrhigh; -} dma64dd_t; - -uint32_t g_dmactrlflags; - -static uint32_t dma_ctrlflags(uint32_t mask, uint32_t flags) -{ - debug("%s enter\n", __func__); - - g_dmactrlflags &= ~mask; - g_dmactrlflags |= flags; - - /* If trying to enable parity, check if parity is actually supported */ - if (g_dmactrlflags & DMA_CTRL_PEN) { - uint32_t control; - - control = readl(GMAC0_DMA_TX_CTRL_ADDR); - writel(control | D64_XC_PD, GMAC0_DMA_TX_CTRL_ADDR); - if (readl(GMAC0_DMA_TX_CTRL_ADDR) & D64_XC_PD) { - /* - * We *can* disable it, therefore it is supported; - * restore control register - */ - writel(control, GMAC0_DMA_TX_CTRL_ADDR); - } else { - /* Not supported, don't allow it to be enabled */ - g_dmactrlflags &= ~DMA_CTRL_PEN; - } - } - - return g_dmactrlflags; -} - -static inline void reg32_clear_bits(uint32_t reg, uint32_t value) -{ - uint32_t v = readl(reg); - v &= ~(value); - writel(v, reg); -} - -static inline void reg32_set_bits(uint32_t reg, uint32_t value) -{ - uint32_t v = readl(reg); - v |= value; - writel(v, reg); -} - -#ifdef BCM_GMAC_DEBUG -static void dma_tx_dump(struct eth_dma *dma) -{ - dma64dd_t *descp = NULL; - uint8_t *bufp; - int i; - - printf("TX DMA Register:\n"); - printf("control:0x%x; ptr:0x%x; addrl:0x%x; addrh:0x%x; stat0:0x%x, stat1:0x%x\n", - readl(GMAC0_DMA_TX_CTRL_ADDR), - readl(GMAC0_DMA_TX_PTR_ADDR), - readl(GMAC0_DMA_TX_ADDR_LOW_ADDR), - readl(GMAC0_DMA_TX_ADDR_HIGH_ADDR), - readl(GMAC0_DMA_TX_STATUS0_ADDR), - readl(GMAC0_DMA_TX_STATUS1_ADDR)); - - printf("TX Descriptors:\n"); - for (i = 0; i < TX_BUF_NUM; i++) { - descp = (dma64dd_t *)(dma->tx_desc_aligned) + i; - printf("ctrl1:0x%08x; ctrl2:0x%08x; addr:0x%x 0x%08x\n", - descp->ctrl1, descp->ctrl2, - descp->addrhigh, descp->addrlow); - } - - printf("TX Buffers:\n"); - /* Initialize TX DMA descriptor table */ - for (i = 0; i < TX_BUF_NUM; i++) { - bufp = (uint8_t *)(dma->tx_buf + i * TX_BUF_SIZE_ALIGNED); - printf("buf%d:0x%x; ", i, (uint32_t)bufp); - } - printf("\n"); -} - -static void dma_rx_dump(struct eth_dma *dma) -{ - dma64dd_t *descp = NULL; - uint8_t *bufp; - int i; - - printf("RX DMA Register:\n"); - printf("control:0x%x; ptr:0x%x; addrl:0x%x; addrh:0x%x; stat0:0x%x, stat1:0x%x\n", - readl(GMAC0_DMA_RX_CTRL_ADDR), - readl(GMAC0_DMA_RX_PTR_ADDR), - readl(GMAC0_DMA_RX_ADDR_LOW_ADDR), - readl(GMAC0_DMA_RX_ADDR_HIGH_ADDR), - readl(GMAC0_DMA_RX_STATUS0_ADDR), - readl(GMAC0_DMA_RX_STATUS1_ADDR)); - - printf("RX Descriptors:\n"); - for (i = 0; i < RX_BUF_NUM; i++) { - descp = (dma64dd_t *)(dma->rx_desc_aligned) + i; - printf("ctrl1:0x%08x; ctrl2:0x%08x; addr:0x%x 0x%08x\n", - descp->ctrl1, descp->ctrl2, - descp->addrhigh, descp->addrlow); - } - - printf("RX Buffers:\n"); - for (i = 0; i < RX_BUF_NUM; i++) { - bufp = dma->rx_buf + i * RX_BUF_SIZE_ALIGNED; - printf("buf%d:0x%x; ", i, (uint32_t)bufp); - } - printf("\n"); -} -#endif - -static int dma_tx_init(struct eth_dma *dma) -{ - dma64dd_t *descp = NULL; - uint8_t *bufp; - int i; - uint32_t ctrl; - - debug("%s enter\n", __func__); - - /* clear descriptor memory */ - memset((void *)(dma->tx_desc_aligned), 0, - TX_BUF_NUM * DESCP_SIZE_ALIGNED); - memset(dma->tx_buf, 0, TX_BUF_NUM * TX_BUF_SIZE_ALIGNED); - - /* Initialize TX DMA descriptor table */ - for (i = 0; i < TX_BUF_NUM; i++) { - descp = (dma64dd_t *)(dma->tx_desc_aligned) + i; - bufp = dma->tx_buf + i * TX_BUF_SIZE_ALIGNED; - /* clear buffer memory */ - memset((void *)bufp, 0, TX_BUF_SIZE_ALIGNED); - - ctrl = 0; - /* if last descr set endOfTable */ - if (i == (TX_BUF_NUM-1)) - ctrl = D64_CTRL1_EOT; - descp->ctrl1 = ctrl; - descp->ctrl2 = 0; - descp->addrlow = (uint32_t)bufp; - descp->addrhigh = 0; - } - - /* flush descriptor and buffer */ - descp = dma->tx_desc_aligned; - bufp = dma->tx_buf; - flush_dcache_range((unsigned long)descp, - (unsigned long)descp + - DESCP_SIZE_ALIGNED * TX_BUF_NUM); - flush_dcache_range((unsigned long)bufp, - (unsigned long)bufp + - TX_BUF_SIZE_ALIGNED * TX_BUF_NUM); - - /* initialize the DMA channel */ - writel((uint32_t)(dma->tx_desc_aligned), GMAC0_DMA_TX_ADDR_LOW_ADDR); - writel(0, GMAC0_DMA_TX_ADDR_HIGH_ADDR); - - /* now update the dma last descriptor */ - writel(((uint32_t)(dma->tx_desc_aligned)) & D64_XP_LD_MASK, - GMAC0_DMA_TX_PTR_ADDR); - - return 0; -} - -static int dma_rx_init(struct eth_dma *dma) -{ - uint32_t last_desc; - dma64dd_t *descp = NULL; - uint8_t *bufp; - uint32_t ctrl; - int i; - - debug("%s enter\n", __func__); - - /* clear descriptor memory */ - memset((void *)(dma->rx_desc_aligned), 0, - RX_BUF_NUM * DESCP_SIZE_ALIGNED); - /* clear buffer memory */ - memset(dma->rx_buf, 0, RX_BUF_NUM * RX_BUF_SIZE_ALIGNED); - - /* Initialize RX DMA descriptor table */ - for (i = 0; i < RX_BUF_NUM; i++) { - descp = (dma64dd_t *)(dma->rx_desc_aligned) + i; - bufp = dma->rx_buf + i * RX_BUF_SIZE_ALIGNED; - ctrl = 0; - /* if last descr set endOfTable */ - if (i == (RX_BUF_NUM - 1)) - ctrl = D64_CTRL1_EOT; - descp->ctrl1 = ctrl; - descp->ctrl2 = RX_BUF_SIZE_ALIGNED; - descp->addrlow = (uint32_t)bufp; - descp->addrhigh = 0; - - last_desc = ((uint32_t)(descp) & D64_XP_LD_MASK) - + sizeof(dma64dd_t); - } - - descp = dma->rx_desc_aligned; - bufp = dma->rx_buf; - /* flush descriptor and buffer */ - flush_dcache_range((unsigned long)descp, - (unsigned long)descp + - DESCP_SIZE_ALIGNED * RX_BUF_NUM); - flush_dcache_range((unsigned long)(bufp), - (unsigned long)bufp + - RX_BUF_SIZE_ALIGNED * RX_BUF_NUM); - - /* initailize the DMA channel */ - writel((uint32_t)descp, GMAC0_DMA_RX_ADDR_LOW_ADDR); - writel(0, GMAC0_DMA_RX_ADDR_HIGH_ADDR); - - /* now update the dma last descriptor */ - writel(last_desc, GMAC0_DMA_RX_PTR_ADDR); - - return 0; -} - -static int dma_init(struct eth_dma *dma) -{ - debug(" %s enter\n", __func__); - - /* - * Default flags: For backwards compatibility both - * Rx Overflow Continue and Parity are DISABLED. - */ - dma_ctrlflags(DMA_CTRL_ROC | DMA_CTRL_PEN, 0); - - debug("rx burst len 0x%x\n", - (readl(GMAC0_DMA_RX_CTRL_ADDR) & D64_RC_BL_MASK) - >> D64_RC_BL_SHIFT); - debug("tx burst len 0x%x\n", - (readl(GMAC0_DMA_TX_CTRL_ADDR) & D64_XC_BL_MASK) - >> D64_XC_BL_SHIFT); - - dma_tx_init(dma); - dma_rx_init(dma); - - /* From end of chip_init() */ - /* enable the overflow continue feature and disable parity */ - dma_ctrlflags(DMA_CTRL_ROC | DMA_CTRL_PEN /* mask */, - DMA_CTRL_ROC /* value */); - - return 0; -} - -static int dma_deinit(struct eth_dma *dma) -{ - debug(" %s enter\n", __func__); - - gmac_disable_dma(dma, MAC_DMA_RX); - gmac_disable_dma(dma, MAC_DMA_TX); - - free(dma->tx_buf); - dma->tx_buf = NULL; - free(dma->tx_desc_aligned); - dma->tx_desc_aligned = NULL; - - free(dma->rx_buf); - dma->rx_buf = NULL; - free(dma->rx_desc_aligned); - dma->rx_desc_aligned = NULL; - - return 0; -} - -int gmac_tx_packet(struct eth_dma *dma, void *packet, int length) -{ - uint8_t *bufp = dma->tx_buf + dma->cur_tx_index * TX_BUF_SIZE_ALIGNED; - - /* kick off the dma */ - size_t len = length; - int txout = dma->cur_tx_index; - uint32_t flags; - dma64dd_t *descp = NULL; - uint32_t ctrl; - uint32_t last_desc = (((uint32_t)dma->tx_desc_aligned) + - sizeof(dma64dd_t)) & D64_XP_LD_MASK; - size_t buflen; - - debug("%s enter\n", __func__); - - /* load the buffer */ - memcpy(bufp, packet, len); - - /* Add 4 bytes for Ethernet FCS/CRC */ - buflen = len + 4; - - ctrl = (buflen & D64_CTRL2_BC_MASK); - - /* the transmit will only be one frame or set SOF, EOF */ - /* also set int on completion */ - flags = D64_CTRL1_SOF | D64_CTRL1_IOC | D64_CTRL1_EOF; - - /* txout points to the descriptor to uset */ - /* if last descriptor then set EOT */ - if (txout == (TX_BUF_NUM - 1)) { - flags |= D64_CTRL1_EOT; - last_desc = ((uint32_t)(dma->tx_desc_aligned)) & D64_XP_LD_MASK; - } - - /* write the descriptor */ - descp = ((dma64dd_t *)(dma->tx_desc_aligned)) + txout; - descp->addrlow = (uint32_t)bufp; - descp->addrhigh = 0; - descp->ctrl1 = flags; - descp->ctrl2 = ctrl; - - /* flush descriptor and buffer */ - flush_dcache_range((unsigned long)dma->tx_desc_aligned, - (unsigned long)dma->tx_desc_aligned + - DESCP_SIZE_ALIGNED * TX_BUF_NUM); - flush_dcache_range((unsigned long)bufp, - (unsigned long)bufp + TX_BUF_SIZE_ALIGNED); - - /* now update the dma last descriptor */ - writel(last_desc, GMAC0_DMA_TX_PTR_ADDR); - - /* tx dma should be enabled so packet should go out */ - - /* update txout */ - dma->cur_tx_index = (txout + 1) & (TX_BUF_NUM - 1); - - return 0; -} - -bool gmac_check_tx_done(struct eth_dma *dma) -{ - /* wait for tx to complete */ - uint32_t intstatus; - bool xfrdone = false; - - debug("%s enter\n", __func__); - - intstatus = readl(GMAC0_INT_STATUS_ADDR); - - debug("int(0x%x)\n", intstatus); - if (intstatus & (I_XI0 | I_XI1 | I_XI2 | I_XI3)) { - xfrdone = true; - /* clear the int bits */ - intstatus &= ~(I_XI0 | I_XI1 | I_XI2 | I_XI3); - writel(intstatus, GMAC0_INT_STATUS_ADDR); - } else { - debug("Tx int(0x%x)\n", intstatus); - } - - return xfrdone; -} - -int gmac_check_rx_done(struct eth_dma *dma, uint8_t *buf) -{ - void *bufp, *datap; - size_t rcvlen = 0, buflen = 0; - uint32_t stat0 = 0, stat1 = 0; - uint32_t control, offset; - uint8_t statbuf[HWRXOFF*2]; - - int index, curr, active; - dma64dd_t *descp = NULL; - - /* udelay(50); */ - - /* - * this api will check if a packet has been received. - * If so it will return the address of the buffer and current - * descriptor index will be incremented to the - * next descriptor. Once done with the frame the buffer should be - * added back onto the descriptor and the lastdscr should be updated - * to this descriptor. - */ - index = dma->cur_rx_index; - offset = (uint32_t)(dma->rx_desc_aligned); - stat0 = readl(GMAC0_DMA_RX_STATUS0_ADDR) & D64_RS0_CD_MASK; - stat1 = readl(GMAC0_DMA_RX_STATUS1_ADDR) & D64_RS0_CD_MASK; - curr = ((stat0 - offset) & D64_RS0_CD_MASK) / sizeof(dma64dd_t); - active = ((stat1 - offset) & D64_RS0_CD_MASK) / sizeof(dma64dd_t); - - /* check if any frame */ - if (index == curr) - return -1; - - debug("received packet\n"); - debug("expect(0x%x) curr(0x%x) active(0x%x)\n", index, curr, active); - /* remove warning */ - if (index == active) - ; - - /* get the packet pointer that corresponds to the rx descriptor */ - bufp = dma->rx_buf + index * RX_BUF_SIZE_ALIGNED; - - descp = (dma64dd_t *)(dma->rx_desc_aligned) + index; - /* flush descriptor and buffer */ - flush_dcache_range((unsigned long)dma->rx_desc_aligned, - (unsigned long)dma->rx_desc_aligned + - DESCP_SIZE_ALIGNED * RX_BUF_NUM); - flush_dcache_range((unsigned long)bufp, - (unsigned long)bufp + RX_BUF_SIZE_ALIGNED); - - buflen = (descp->ctrl2 & D64_CTRL2_BC_MASK); - - stat0 = readl(GMAC0_DMA_RX_STATUS0_ADDR); - stat1 = readl(GMAC0_DMA_RX_STATUS1_ADDR); - - debug("bufp(0x%x) index(0x%x) buflen(0x%x) stat0(0x%x) stat1(0x%x)\n", - (uint32_t)bufp, index, buflen, stat0, stat1); - - dma->cur_rx_index = (index + 1) & (RX_BUF_NUM - 1); - - /* get buffer offset */ - control = readl(GMAC0_DMA_RX_CTRL_ADDR); - offset = (control & D64_RC_RO_MASK) >> D64_RC_RO_SHIFT; - rcvlen = *(uint16_t *)bufp; - - debug("Received %d bytes\n", rcvlen); - /* copy status into temp buf then copy data from rx buffer */ - memcpy(statbuf, bufp, offset); - datap = (void *)((uint32_t)bufp + offset); - memcpy(buf, datap, rcvlen); - - /* update descriptor that is being added back on ring */ - descp->ctrl2 = RX_BUF_SIZE_ALIGNED; - descp->addrlow = (uint32_t)bufp; - descp->addrhigh = 0; - /* flush descriptor */ - flush_dcache_range((unsigned long)dma->rx_desc_aligned, - (unsigned long)dma->rx_desc_aligned + - DESCP_SIZE_ALIGNED * RX_BUF_NUM); - - /* set the lastdscr for the rx ring */ - writel(((uint32_t)descp) & D64_XP_LD_MASK, GMAC0_DMA_RX_PTR_ADDR); - - return (int)rcvlen; -} - -static int gmac_disable_dma(struct eth_dma *dma, int dir) -{ - int status; - - debug("%s enter\n", __func__); - - if (dir == MAC_DMA_TX) { - /* address PR8249/PR7577 issue */ - /* suspend tx DMA first */ - writel(D64_XC_SE, GMAC0_DMA_TX_CTRL_ADDR); - SPINWAIT(((status = (readl(GMAC0_DMA_TX_STATUS0_ADDR) & - D64_XS0_XS_MASK)) != - D64_XS0_XS_DISABLED) && - (status != D64_XS0_XS_IDLE) && - (status != D64_XS0_XS_STOPPED), 10000); - - /* - * PR2414 WAR: DMA engines are not disabled until - * transfer finishes - */ - writel(0, GMAC0_DMA_TX_CTRL_ADDR); - SPINWAIT(((status = (readl(GMAC0_DMA_TX_STATUS0_ADDR) & - D64_XS0_XS_MASK)) != - D64_XS0_XS_DISABLED), 10000); - - /* wait for the last transaction to complete */ - udelay(2); - - status = (status == D64_XS0_XS_DISABLED); - } else { - /* - * PR2414 WAR: DMA engines are not disabled until - * transfer finishes - */ - writel(0, GMAC0_DMA_RX_CTRL_ADDR); - SPINWAIT(((status = (readl(GMAC0_DMA_RX_STATUS0_ADDR) & - D64_RS0_RS_MASK)) != - D64_RS0_RS_DISABLED), 10000); - - status = (status == D64_RS0_RS_DISABLED); - } - - return status; -} - -static int gmac_enable_dma(struct eth_dma *dma, int dir) -{ - uint32_t control; - - debug("%s enter\n", __func__); - - if (dir == MAC_DMA_TX) { - dma->cur_tx_index = 0; - - /* - * These bits 20:18 (burstLen) of control register can be - * written but will take effect only if these bits are - * valid. So this will not affect previous versions - * of the DMA. They will continue to have those bits set to 0. - */ - control = readl(GMAC0_DMA_TX_CTRL_ADDR); - - control |= D64_XC_XE; - if ((g_dmactrlflags & DMA_CTRL_PEN) == 0) - control |= D64_XC_PD; - - writel(control, GMAC0_DMA_TX_CTRL_ADDR); - - /* initailize the DMA channel */ - writel((uint32_t)(dma->tx_desc_aligned), - GMAC0_DMA_TX_ADDR_LOW_ADDR); - writel(0, GMAC0_DMA_TX_ADDR_HIGH_ADDR); - } else { - dma->cur_rx_index = 0; - - control = (readl(GMAC0_DMA_RX_CTRL_ADDR) & - D64_RC_AE) | D64_RC_RE; - - if ((g_dmactrlflags & DMA_CTRL_PEN) == 0) - control |= D64_RC_PD; - - if (g_dmactrlflags & DMA_CTRL_ROC) - control |= D64_RC_OC; - - /* - * These bits 20:18 (burstLen) of control register can be - * written but will take effect only if these bits are - * valid. So this will not affect previous versions - * of the DMA. They will continue to have those bits set to 0. - */ - control &= ~D64_RC_BL_MASK; - /* Keep default Rx burstlen */ - control |= readl(GMAC0_DMA_RX_CTRL_ADDR) & D64_RC_BL_MASK; - control |= HWRXOFF << D64_RC_RO_SHIFT; - - writel(control, GMAC0_DMA_RX_CTRL_ADDR); - - /* - * the rx descriptor ring should have - * the addresses set properly; - * set the lastdscr for the rx ring - */ - writel(((uint32_t)(dma->rx_desc_aligned) + - (RX_BUF_NUM - 1) * RX_BUF_SIZE_ALIGNED) & - D64_XP_LD_MASK, GMAC0_DMA_RX_PTR_ADDR); - } - - return 0; -} - -bool gmac_mii_busywait(unsigned int timeout) -{ - uint32_t tmp = 0; - - while (timeout > 10) { - tmp = readl(GMAC_MII_CTRL_ADDR); - if (tmp & (1 << GMAC_MII_BUSY_SHIFT)) { - udelay(10); - timeout -= 10; - } else { - break; - } - } - return tmp & (1 << GMAC_MII_BUSY_SHIFT); -} - -int gmac_miiphy_read(struct mii_dev *bus, int phyaddr, int devad, int reg) -{ - uint32_t tmp = 0; - u16 value = 0; - - /* Busy wait timeout is 1ms */ - if (gmac_mii_busywait(1000)) { - pr_err("%s: Prepare MII read: MII/MDIO busy\n", __func__); - return -1; - } - - /* Read operation */ - tmp = GMAC_MII_DATA_READ_CMD; - tmp |= (phyaddr << GMAC_MII_PHY_ADDR_SHIFT) | - (reg << GMAC_MII_PHY_REG_SHIFT); - debug("MII read cmd 0x%x, phy 0x%x, reg 0x%x\n", tmp, phyaddr, reg); - writel(tmp, GMAC_MII_DATA_ADDR); - - if (gmac_mii_busywait(1000)) { - pr_err("%s: MII read failure: MII/MDIO busy\n", __func__); - return -1; - } - - value = readl(GMAC_MII_DATA_ADDR) & 0xffff; - debug("MII read data 0x%x\n", value); - return value; -} - -int gmac_miiphy_write(struct mii_dev *bus, int phyaddr, int devad, int reg, - u16 value) -{ - uint32_t tmp = 0; - - /* Busy wait timeout is 1ms */ - if (gmac_mii_busywait(1000)) { - pr_err("%s: Prepare MII write: MII/MDIO busy\n", __func__); - return -1; - } - - /* Write operation */ - tmp = GMAC_MII_DATA_WRITE_CMD | (value & 0xffff); - tmp |= ((phyaddr << GMAC_MII_PHY_ADDR_SHIFT) | - (reg << GMAC_MII_PHY_REG_SHIFT)); - debug("MII write cmd 0x%x, phy 0x%x, reg 0x%x, data 0x%x\n", - tmp, phyaddr, reg, value); - writel(tmp, GMAC_MII_DATA_ADDR); - - if (gmac_mii_busywait(1000)) { - pr_err("%s: MII write failure: MII/MDIO busy\n", __func__); - return -1; - } - - return 0; -} - -void gmac_init_reset(void) -{ - debug("%s enter\n", __func__); - - /* set command config reg CC_SR */ - reg32_set_bits(UNIMAC0_CMD_CFG_ADDR, CC_SR); - udelay(GMAC_RESET_DELAY); -} - -void gmac_clear_reset(void) -{ - debug("%s enter\n", __func__); - - /* clear command config reg CC_SR */ - reg32_clear_bits(UNIMAC0_CMD_CFG_ADDR, CC_SR); - udelay(GMAC_RESET_DELAY); -} - -static void gmac_enable_local(bool en) -{ - uint32_t cmdcfg; - - debug("%s enter\n", __func__); - - /* read command config reg */ - cmdcfg = readl(UNIMAC0_CMD_CFG_ADDR); - - /* put mac in reset */ - gmac_init_reset(); - - cmdcfg |= CC_SR; - - /* first deassert rx_ena and tx_ena while in reset */ - cmdcfg &= ~(CC_RE | CC_TE); - /* write command config reg */ - writel(cmdcfg, UNIMAC0_CMD_CFG_ADDR); - - /* bring mac out of reset */ - gmac_clear_reset(); - - /* if not enable exit now */ - if (!en) - return; - - /* enable the mac transmit and receive paths now */ - udelay(2); - cmdcfg &= ~CC_SR; - cmdcfg |= (CC_RE | CC_TE); - - /* assert rx_ena and tx_ena when out of reset to enable the mac */ - writel(cmdcfg, UNIMAC0_CMD_CFG_ADDR); - - return; -} - -int gmac_enable(void) -{ - gmac_enable_local(1); - - /* clear interrupts */ - writel(I_INTMASK, GMAC0_INT_STATUS_ADDR); - return 0; -} - -int gmac_disable(void) -{ - gmac_enable_local(0); - return 0; -} - -int gmac_set_speed(int speed, int duplex) -{ - uint32_t cmdcfg; - uint32_t hd_ena; - uint32_t speed_cfg; - - hd_ena = duplex ? 0 : CC_HD; - if (speed == 1000) { - speed_cfg = 2; - } else if (speed == 100) { - speed_cfg = 1; - } else if (speed == 10) { - speed_cfg = 0; - } else { - pr_err("%s: Invalid GMAC speed(%d)!\n", __func__, speed); - return -1; - } - - cmdcfg = readl(UNIMAC0_CMD_CFG_ADDR); - cmdcfg &= ~(CC_ES_MASK | CC_HD); - cmdcfg |= ((speed_cfg << CC_ES_SHIFT) | hd_ena); - - printf("Change GMAC speed to %dMB\n", speed); - debug("GMAC speed cfg 0x%x\n", cmdcfg); - writel(cmdcfg, UNIMAC0_CMD_CFG_ADDR); - - return 0; -} - -int gmac_set_mac_addr(unsigned char *mac) -{ - /* set our local address */ - debug("GMAC: %02x:%02x:%02x:%02x:%02x:%02x\n", - mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]); - writel(htonl(*(uint32_t *)mac), UNIMAC0_MAC_MSB_ADDR); - writew(htons(*(uint32_t *)&mac[4]), UNIMAC0_MAC_LSB_ADDR); - - return 0; -} - -int gmac_mac_init(struct eth_device *dev) -{ - struct eth_info *eth = (struct eth_info *)(dev->priv); - struct eth_dma *dma = &(eth->dma); - - uint32_t tmp; - uint32_t cmdcfg; - int chipid; - - debug("%s enter\n", __func__); - - /* Always use GMAC0 */ - printf("Using GMAC%d\n", 0); - - /* Reset AMAC0 core */ - writel(0, AMAC0_IDM_RESET_ADDR); - tmp = readl(AMAC0_IO_CTRL_DIRECT_ADDR); - /* Set clock */ - tmp &= ~(1 << AMAC0_IO_CTRL_CLK_250_SEL_SHIFT); - tmp |= (1 << AMAC0_IO_CTRL_GMII_MODE_SHIFT); - /* Set Tx clock */ - tmp &= ~(1 << AMAC0_IO_CTRL_DEST_SYNC_MODE_EN_SHIFT); - writel(tmp, AMAC0_IO_CTRL_DIRECT_ADDR); - - /* reset gmac */ - /* - * As AMAC is just reset, NO need? - * set eth_data into loopback mode to ensure no rx traffic - * gmac_loopback(eth_data, TRUE); - * ET_TRACE(("%s gmac loopback\n", __func__)); - * udelay(1); - */ - - cmdcfg = readl(UNIMAC0_CMD_CFG_ADDR); - cmdcfg &= ~(CC_TE | CC_RE | CC_RPI | CC_TAI | CC_HD | CC_ML | - CC_CFE | CC_RL | CC_RED | CC_PE | CC_TPI | - CC_PAD_EN | CC_PF); - cmdcfg |= (CC_PROM | CC_NLC | CC_CFE); - /* put mac in reset */ - gmac_init_reset(); - writel(cmdcfg, UNIMAC0_CMD_CFG_ADDR); - gmac_clear_reset(); - - /* enable clear MIB on read */ - reg32_set_bits(GMAC0_DEV_CTRL_ADDR, DC_MROR); - /* PHY: set smi_master to drive mdc_clk */ - reg32_set_bits(GMAC0_PHY_CTRL_ADDR, PC_MTE); - - /* clear persistent sw intstatus */ - writel(0, GMAC0_INT_STATUS_ADDR); - - if (dma_init(dma) < 0) { - pr_err("%s: GMAC dma_init failed\n", __func__); - goto err_exit; - } - - chipid = CHIPID; - printf("%s: Chip ID: 0x%x\n", __func__, chipid); - - /* set switch bypass mode */ - tmp = readl(SWITCH_GLOBAL_CONFIG_ADDR); - tmp |= (1 << CDRU_SWITCH_BYPASS_SWITCH_SHIFT); - - /* Switch mode */ - /* tmp &= ~(1 << CDRU_SWITCH_BYPASS_SWITCH_SHIFT); */ - - writel(tmp, SWITCH_GLOBAL_CONFIG_ADDR); - - tmp = readl(CRMU_CHIP_IO_PAD_CONTROL_ADDR); - tmp &= ~(1 << CDRU_IOMUX_FORCE_PAD_IN_SHIFT); - writel(tmp, CRMU_CHIP_IO_PAD_CONTROL_ADDR); - - /* Set MDIO to internal GPHY */ - tmp = readl(GMAC_MII_CTRL_ADDR); - /* Select internal MDC/MDIO bus*/ - tmp &= ~(1 << GMAC_MII_CTRL_BYP_SHIFT); - /* select MDC/MDIO connecting to on-chip internal PHYs */ - tmp &= ~(1 << GMAC_MII_CTRL_EXT_SHIFT); - /* - * give bit[6:0](MDCDIV) with required divisor to set - * the MDC clock frequency, 66MHZ/0x1A=2.5MHZ - */ - tmp |= 0x1A; - - writel(tmp, GMAC_MII_CTRL_ADDR); - - if (gmac_mii_busywait(1000)) { - pr_err("%s: Configure MDIO: MII/MDIO busy\n", __func__); - goto err_exit; - } - - /* Configure GMAC0 */ - /* enable one rx interrupt per received frame */ - writel(1 << GMAC0_IRL_FRAMECOUNT_SHIFT, GMAC0_INTR_RECV_LAZY_ADDR); - - /* read command config reg */ - cmdcfg = readl(UNIMAC0_CMD_CFG_ADDR); - /* enable 802.3x tx flow control (honor received PAUSE frames) */ - cmdcfg &= ~CC_RPI; - /* enable promiscuous mode */ - cmdcfg |= CC_PROM; - /* Disable loopback mode */ - cmdcfg &= ~CC_ML; - /* set the speed */ - cmdcfg &= ~(CC_ES_MASK | CC_HD); - /* Set to 1Gbps and full duplex by default */ - cmdcfg |= (2 << CC_ES_SHIFT); - - /* put mac in reset */ - gmac_init_reset(); - /* write register */ - writel(cmdcfg, UNIMAC0_CMD_CFG_ADDR); - /* bring mac out of reset */ - gmac_clear_reset(); - - /* set max frame lengths; account for possible vlan tag */ - writel(PKTSIZE + 32, UNIMAC0_FRM_LENGTH_ADDR); - - return 0; - -err_exit: - dma_deinit(dma); - return -1; -} - -int gmac_add(struct eth_device *dev) -{ - struct eth_info *eth = (struct eth_info *)(dev->priv); - struct eth_dma *dma = &(eth->dma); - void *tmp; - - /* - * Desc has to be 16-byte aligned. But for dcache flush it must be - * aligned to ARCH_DMA_MINALIGN. - */ - tmp = memalign(ARCH_DMA_MINALIGN, DESCP_SIZE_ALIGNED * TX_BUF_NUM); - if (tmp == NULL) { - printf("%s: Failed to allocate TX desc Buffer\n", __func__); - return -1; - } - - dma->tx_desc_aligned = (void *)tmp; - debug("TX Descriptor Buffer: %p; length: 0x%x\n", - dma->tx_desc_aligned, DESCP_SIZE_ALIGNED * TX_BUF_NUM); - - tmp = memalign(ARCH_DMA_MINALIGN, TX_BUF_SIZE_ALIGNED * TX_BUF_NUM); - if (tmp == NULL) { - printf("%s: Failed to allocate TX Data Buffer\n", __func__); - free(dma->tx_desc_aligned); - return -1; - } - dma->tx_buf = (uint8_t *)tmp; - debug("TX Data Buffer: %p; length: 0x%x\n", - dma->tx_buf, TX_BUF_SIZE_ALIGNED * TX_BUF_NUM); - - /* Desc has to be 16-byte aligned */ - tmp = memalign(ARCH_DMA_MINALIGN, DESCP_SIZE_ALIGNED * RX_BUF_NUM); - if (tmp == NULL) { - printf("%s: Failed to allocate RX Descriptor\n", __func__); - free(dma->tx_desc_aligned); - free(dma->tx_buf); - return -1; - } - dma->rx_desc_aligned = (void *)tmp; - debug("RX Descriptor Buffer: %p, length: 0x%x\n", - dma->rx_desc_aligned, DESCP_SIZE_ALIGNED * RX_BUF_NUM); - - tmp = memalign(ARCH_DMA_MINALIGN, RX_BUF_SIZE_ALIGNED * RX_BUF_NUM); - if (tmp == NULL) { - printf("%s: Failed to allocate RX Data Buffer\n", __func__); - free(dma->tx_desc_aligned); - free(dma->tx_buf); - free(dma->rx_desc_aligned); - return -1; - } - dma->rx_buf = (uint8_t *)tmp; - debug("RX Data Buffer: %p; length: 0x%x\n", - dma->rx_buf, RX_BUF_SIZE_ALIGNED * RX_BUF_NUM); - - g_dmactrlflags = 0; - - eth->phy_interface = PHY_INTERFACE_MODE_GMII; - - dma->tx_packet = gmac_tx_packet; - dma->check_tx_done = gmac_check_tx_done; - - dma->check_rx_done = gmac_check_rx_done; - - dma->enable_dma = gmac_enable_dma; - dma->disable_dma = gmac_disable_dma; - - eth->miiphy_read = gmac_miiphy_read; - eth->miiphy_write = gmac_miiphy_write; - - eth->mac_init = gmac_mac_init; - eth->disable_mac = gmac_disable; - eth->enable_mac = gmac_enable; - eth->set_mac_addr = gmac_set_mac_addr; - eth->set_mac_speed = gmac_set_speed; - - return 0; -} diff --git a/drivers/net/bcm-sf2-eth-gmac.h b/drivers/net/bcm-sf2-eth-gmac.h deleted file mode 100644 index ac5e45d4f90..00000000000 --- a/drivers/net/bcm-sf2-eth-gmac.h +++ /dev/null @@ -1,222 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2014 Broadcom Corporation. - */ - -#ifndef _BCM_SF2_ETH_GMAC_H_ -#define _BCM_SF2_ETH_GMAC_H_ - -#define BCM_SF2_ETH_MAC_NAME "gmac" - -#ifndef ETHHW_PORT_INT -#define ETHHW_PORT_INT 8 -#endif - -#define GMAC0_REG_BASE 0x18042000 -#define GMAC0_DEV_CTRL_ADDR GMAC0_REG_BASE -#define GMAC0_INT_STATUS_ADDR (GMAC0_REG_BASE + 0x020) -#define GMAC0_INTR_RECV_LAZY_ADDR (GMAC0_REG_BASE + 0x100) -#define GMAC0_PHY_CTRL_ADDR (GMAC0_REG_BASE + 0x188) - -#define GMAC_DMA_PTR_OFFSET 0x04 -#define GMAC_DMA_ADDR_LOW_OFFSET 0x08 -#define GMAC_DMA_ADDR_HIGH_OFFSET 0x0c -#define GMAC_DMA_STATUS0_OFFSET 0x10 -#define GMAC_DMA_STATUS1_OFFSET 0x14 - -#define GMAC0_DMA_TX_CTRL_ADDR (GMAC0_REG_BASE + 0x200) -#define GMAC0_DMA_TX_PTR_ADDR \ - (GMAC0_DMA_TX_CTRL_ADDR + GMAC_DMA_PTR_OFFSET) -#define GMAC0_DMA_TX_ADDR_LOW_ADDR \ - (GMAC0_DMA_TX_CTRL_ADDR + GMAC_DMA_ADDR_LOW_OFFSET) -#define GMAC0_DMA_TX_ADDR_HIGH_ADDR \ - (GMAC0_DMA_TX_CTRL_ADDR + GMAC_DMA_ADDR_HIGH_OFFSET) -#define GMAC0_DMA_TX_STATUS0_ADDR \ - (GMAC0_DMA_TX_CTRL_ADDR + GMAC_DMA_STATUS0_OFFSET) -#define GMAC0_DMA_TX_STATUS1_ADDR \ - (GMAC0_DMA_TX_CTRL_ADDR + GMAC_DMA_STATUS1_OFFSET) - -#define GMAC0_DMA_RX_CTRL_ADDR (GMAC0_REG_BASE + 0x220) -#define GMAC0_DMA_RX_PTR_ADDR \ - (GMAC0_DMA_RX_CTRL_ADDR + GMAC_DMA_PTR_OFFSET) -#define GMAC0_DMA_RX_ADDR_LOW_ADDR \ - (GMAC0_DMA_RX_CTRL_ADDR + GMAC_DMA_ADDR_LOW_OFFSET) -#define GMAC0_DMA_RX_ADDR_HIGH_ADDR \ - (GMAC0_DMA_RX_CTRL_ADDR + GMAC_DMA_ADDR_HIGH_OFFSET) -#define GMAC0_DMA_RX_STATUS0_ADDR \ - (GMAC0_DMA_RX_CTRL_ADDR + GMAC_DMA_STATUS0_OFFSET) -#define GMAC0_DMA_RX_STATUS1_ADDR \ - (GMAC0_DMA_RX_CTRL_ADDR + GMAC_DMA_STATUS1_OFFSET) - -#define UNIMAC0_CMD_CFG_ADDR (GMAC0_REG_BASE + 0x808) -#define UNIMAC0_MAC_MSB_ADDR (GMAC0_REG_BASE + 0x80c) -#define UNIMAC0_MAC_LSB_ADDR (GMAC0_REG_BASE + 0x810) -#define UNIMAC0_FRM_LENGTH_ADDR (GMAC0_REG_BASE + 0x814) - -#define GMAC0_IRL_FRAMECOUNT_SHIFT 24 - -/* transmit channel control */ -/* transmit enable */ -#define D64_XC_XE 0x00000001 -/* transmit suspend request */ -#define D64_XC_SE 0x00000002 -/* parity check disable */ -#define D64_XC_PD 0x00000800 -/* BurstLen bits */ -#define D64_XC_BL_MASK 0x001C0000 -#define D64_XC_BL_SHIFT 18 - -/* transmit descriptor table pointer */ -/* last valid descriptor */ -#define D64_XP_LD_MASK 0x00001fff - -/* transmit channel status */ -/* transmit state */ -#define D64_XS0_XS_MASK 0xf0000000 -#define D64_XS0_XS_SHIFT 28 -#define D64_XS0_XS_DISABLED 0x00000000 -#define D64_XS0_XS_ACTIVE 0x10000000 -#define D64_XS0_XS_IDLE 0x20000000 -#define D64_XS0_XS_STOPPED 0x30000000 -#define D64_XS0_XS_SUSP 0x40000000 - -/* receive channel control */ -/* receive enable */ -#define D64_RC_RE 0x00000001 -/* address extension bits */ -#define D64_RC_AE 0x00030000 -/* overflow continue */ -#define D64_RC_OC 0x00000400 -/* parity check disable */ -#define D64_RC_PD 0x00000800 -/* receive frame offset */ -#define D64_RC_RO_MASK 0x000000fe -#define D64_RC_RO_SHIFT 1 -/* BurstLen bits */ -#define D64_RC_BL_MASK 0x001C0000 -#define D64_RC_BL_SHIFT 18 - -/* flags for dma controller */ -/* partity enable */ -#define DMA_CTRL_PEN (1 << 0) -/* rx overflow continue */ -#define DMA_CTRL_ROC (1 << 1) - -/* receive descriptor table pointer */ -/* last valid descriptor */ -#define D64_RP_LD_MASK 0x00001fff - -/* receive channel status */ -/* current descriptor pointer */ -#define D64_RS0_CD_MASK 0x00001fff -/* receive state */ -#define D64_RS0_RS_MASK 0xf0000000 -#define D64_RS0_RS_SHIFT 28 -#define D64_RS0_RS_DISABLED 0x00000000 -#define D64_RS0_RS_ACTIVE 0x10000000 -#define D64_RS0_RS_IDLE 0x20000000 -#define D64_RS0_RS_STOPPED 0x30000000 -#define D64_RS0_RS_SUSP 0x40000000 - -/* descriptor control flags 1 */ -/* core specific flags */ -#define D64_CTRL_COREFLAGS 0x0ff00000 -/* end of descriptor table */ -#define D64_CTRL1_EOT ((uint32_t)1 << 28) -/* interrupt on completion */ -#define D64_CTRL1_IOC ((uint32_t)1 << 29) -/* end of frame */ -#define D64_CTRL1_EOF ((uint32_t)1 << 30) -/* start of frame */ -#define D64_CTRL1_SOF ((uint32_t)1 << 31) - -/* descriptor control flags 2 */ -/* buffer byte count. real data len must <= 16KB */ -#define D64_CTRL2_BC_MASK 0x00007fff -/* address extension bits */ -#define D64_CTRL2_AE 0x00030000 -#define D64_CTRL2_AE_SHIFT 16 -/* parity bit */ -#define D64_CTRL2_PARITY 0x00040000 -/* control flags in the range [27:20] are core-specific and not defined here */ -#define D64_CTRL_CORE_MASK 0x0ff00000 - -#define DC_MROR 0x00000010 -#define PC_MTE 0x00800000 - -/* command config */ -#define CC_TE 0x00000001 -#define CC_RE 0x00000002 -#define CC_ES_MASK 0x0000000c -#define CC_ES_SHIFT 2 -#define CC_PROM 0x00000010 -#define CC_PAD_EN 0x00000020 -#define CC_CF 0x00000040 -#define CC_PF 0x00000080 -#define CC_RPI 0x00000100 -#define CC_TAI 0x00000200 -#define CC_HD 0x00000400 -#define CC_HD_SHIFT 10 -#define CC_SR 0x00002000 -#define CC_ML 0x00008000 -#define CC_AE 0x00400000 -#define CC_CFE 0x00800000 -#define CC_NLC 0x01000000 -#define CC_RL 0x02000000 -#define CC_RED 0x04000000 -#define CC_PE 0x08000000 -#define CC_TPI 0x10000000 -#define CC_AT 0x20000000 - -#define I_PDEE 0x00000400 -#define I_PDE 0x00000800 -#define I_DE 0x00001000 -#define I_RDU 0x00002000 -#define I_RFO 0x00004000 -#define I_XFU 0x00008000 -#define I_RI 0x00010000 -#define I_XI0 0x01000000 -#define I_XI1 0x02000000 -#define I_XI2 0x04000000 -#define I_XI3 0x08000000 -#define I_ERRORS (I_PDEE | I_PDE | I_DE | I_RDU | I_RFO | I_XFU) -#define DEF_INTMASK (I_XI0 | I_XI1 | I_XI2 | I_XI3 | I_RI | I_ERRORS) - -#define I_INTMASK 0x0f01fcff - -#define CHIP_DRU_BASE 0x0301d000 -#define CRMU_CHIP_IO_PAD_CONTROL_ADDR (CHIP_DRU_BASE + 0x0bc) -#define SWITCH_GLOBAL_CONFIG_ADDR (CHIP_DRU_BASE + 0x194) - -#define CDRU_IOMUX_FORCE_PAD_IN_SHIFT 0 -#define CDRU_SWITCH_BYPASS_SWITCH_SHIFT 13 - -#define AMAC0_IDM_RESET_ADDR 0x18110800 -#define AMAC0_IO_CTRL_DIRECT_ADDR 0x18110408 -#define AMAC0_IO_CTRL_CLK_250_SEL_SHIFT 6 -#define AMAC0_IO_CTRL_GMII_MODE_SHIFT 5 -#define AMAC0_IO_CTRL_DEST_SYNC_MODE_EN_SHIFT 3 - -#define CHIPA_CHIP_ID_ADDR 0x18000000 -#define CHIPID (readl(CHIPA_CHIP_ID_ADDR) & 0xFFFF) -#define CHIPREV (((readl(CHIPA_CHIP_ID_ADDR) >> 16) & 0xF) -#define CHIPSKU (((readl(CHIPA_CHIP_ID_ADDR) >> 20) & 0xF) - -#define GMAC_MII_CTRL_ADDR 0x18002000 -#define GMAC_MII_CTRL_BYP_SHIFT 10 -#define GMAC_MII_CTRL_EXT_SHIFT 9 -#define GMAC_MII_DATA_ADDR 0x18002004 -#define GMAC_MII_DATA_READ_CMD 0x60020000 -#define GMAC_MII_DATA_WRITE_CMD 0x50020000 -#define GMAC_MII_BUSY_SHIFT 8 -#define GMAC_MII_PHY_ADDR_SHIFT 23 -#define GMAC_MII_PHY_REG_SHIFT 18 - -#define GMAC_RESET_DELAY 2 -#define HWRXOFF 30 -#define MAXNAMEL 8 -#define NUMTXQ 4 - -int gmac_add(struct eth_device *dev); - -#endif /* _BCM_SF2_ETH_GMAC_H_ */ diff --git a/drivers/net/bcm-sf2-eth.c b/drivers/net/bcm-sf2-eth.c deleted file mode 100644 index c10719c6b51..00000000000 --- a/drivers/net/bcm-sf2-eth.c +++ /dev/null @@ -1,274 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2014 Broadcom Corporation. - */ - -#include <log.h> -#include <malloc.h> -#include <net.h> -#include <config.h> -#include <linux/delay.h> -#include <linux/printk.h> - -#include <phy.h> -#include <miiphy.h> - -#include <asm/io.h> - -#include <netdev.h> -#include "bcm-sf2-eth.h" - -#if defined(CONFIG_BCM_SF2_ETH_GMAC) -#include "bcm-sf2-eth-gmac.h" -#else -#error "bcm_sf2_eth: NEED to define a MAC!" -#endif - -#define BCM_NET_MODULE_DESCRIPTION "Broadcom Starfighter2 Ethernet driver" -#define BCM_NET_MODULE_VERSION "0.1" -#define BCM_SF2_ETH_DEV_NAME "bcm_sf2" - -static const char banner[] = - BCM_NET_MODULE_DESCRIPTION " " BCM_NET_MODULE_VERSION "\n"; - -static int bcm_sf2_eth_init(struct eth_device *dev) -{ - struct eth_info *eth = (struct eth_info *)(dev->priv); - struct eth_dma *dma = &(eth->dma); - struct phy_device *phydev; - int rc = 0; - int i; - - rc = eth->mac_init(dev); - if (rc) { - pr_err("%s: Couldn't cofigure MAC!\n", __func__); - return rc; - } - - /* disable DMA */ - dma->disable_dma(dma, MAC_DMA_RX); - dma->disable_dma(dma, MAC_DMA_TX); - - eth->port_num = 0; - debug("Connecting PHY 0...\n"); - phydev = phy_connect(miiphy_get_dev_by_name(dev->name), - -1, dev, eth->phy_interface); - if (phydev != NULL) { - eth->port[0] = phydev; - eth->port_num += 1; - } else { - debug("No PHY found for port 0\n"); - } - - for (i = 0; i < eth->port_num; i++) - phy_config(eth->port[i]); - - return rc; -} - -/* - * u-boot net functions - */ - -static int bcm_sf2_eth_send(struct eth_device *dev, void *packet, int length) -{ - struct eth_dma *dma = &(((struct eth_info *)(dev->priv))->dma); - uint8_t *buf = (uint8_t *)packet; - int rc = 0; - int i = 0; - - debug("%s enter\n", __func__); - - /* load buf and start transmit */ - rc = dma->tx_packet(dma, buf, length); - if (rc) { - debug("ERROR - Tx failed\n"); - return rc; - } - - while (!(dma->check_tx_done(dma))) { - udelay(100); - debug("."); - i++; - if (i > 20) { - pr_err("%s: Tx timeout: retried 20 times\n", __func__); - rc = -1; - break; - } - } - - debug("%s exit rc(0x%x)\n", __func__, rc); - return rc; -} - -static int bcm_sf2_eth_receive(struct eth_device *dev) -{ - struct eth_dma *dma = &(((struct eth_info *)(dev->priv))->dma); - uint8_t *buf = (uint8_t *)net_rx_packets[0]; - int rcvlen; - int rc = 0; - int i = 0; - - while (1) { - /* Poll Rx queue to get a packet */ - rcvlen = dma->check_rx_done(dma, buf); - if (rcvlen < 0) { - /* No packet received */ - rc = -1; - debug("\nNO More Rx\n"); - break; - } else if ((rcvlen == 0) || (rcvlen > RX_BUF_SIZE)) { - pr_err("%s: Wrong Ethernet packet size (%d B), skip!\n", - __func__, rcvlen); - break; - } else { - debug("recieved\n"); - - /* Forward received packet to uboot network handler */ - net_process_received_packet(buf, rcvlen); - - if (++i >= PKTBUFSRX) - i = 0; - buf = net_rx_packets[i]; - } - } - - return rc; -} - -static int bcm_sf2_eth_write_hwaddr(struct eth_device *dev) -{ - struct eth_info *eth = (struct eth_info *)(dev->priv); - - printf(" ETH MAC: %02x:%02x:%02x:%02x:%02x:%02x\n", - dev->enetaddr[0], dev->enetaddr[1], dev->enetaddr[2], - dev->enetaddr[3], dev->enetaddr[4], dev->enetaddr[5]); - - return eth->set_mac_addr(dev->enetaddr); -} - -static int bcm_sf2_eth_open(struct eth_device *dev, struct bd_info *bt) -{ - struct eth_info *eth = (struct eth_info *)(dev->priv); - struct eth_dma *dma = &(eth->dma); - int i; - - debug("Enabling BCM SF2 Ethernet.\n"); - - eth->enable_mac(); - - /* enable tx and rx DMA */ - dma->enable_dma(dma, MAC_DMA_RX); - dma->enable_dma(dma, MAC_DMA_TX); - - /* - * Need to start PHY here because link speed can change - * before each ethernet operation - */ - for (i = 0; i < eth->port_num; i++) { - if (phy_startup(eth->port[i])) { - pr_err("%s: PHY %d startup failed!\n", __func__, i); - if (i == CONFIG_BCM_SF2_ETH_DEFAULT_PORT) { - pr_err("%s: No default port %d!\n", __func__, i); - return -1; - } - } - } - - /* Set MAC speed using default port */ - i = CONFIG_BCM_SF2_ETH_DEFAULT_PORT; - debug("PHY %d: speed:%d, duplex:%d, link:%d\n", i, - eth->port[i]->speed, eth->port[i]->duplex, eth->port[i]->link); - eth->set_mac_speed(eth->port[i]->speed, eth->port[i]->duplex); - - debug("Enable Ethernet Done.\n"); - - return 0; -} - -static void bcm_sf2_eth_close(struct eth_device *dev) -{ - struct eth_info *eth = (struct eth_info *)(dev->priv); - struct eth_dma *dma = &(eth->dma); - - /* disable DMA */ - dma->disable_dma(dma, MAC_DMA_RX); - dma->disable_dma(dma, MAC_DMA_TX); - - eth->disable_mac(); -} - -int bcm_sf2_eth_register(struct bd_info *bis, u8 dev_num) -{ - struct eth_device *dev; - struct eth_info *eth; - int rc; - - dev = (struct eth_device *)malloc(sizeof(struct eth_device)); - if (dev == NULL) { - pr_err("%s: Not enough memory!\n", __func__); - return -1; - } - - eth = (struct eth_info *)malloc(sizeof(struct eth_info)); - if (eth == NULL) { - pr_err("%s: Not enough memory!\n", __func__); - return -1; - } - - printf(banner); - - memset(dev, 0, sizeof(*dev)); - sprintf(dev->name, "%s_%s-%hu", BCM_SF2_ETH_DEV_NAME, - BCM_SF2_ETH_MAC_NAME, dev_num); - - dev->priv = (void *)eth; - dev->iobase = 0; - - dev->init = bcm_sf2_eth_open; - dev->halt = bcm_sf2_eth_close; - dev->send = bcm_sf2_eth_send; - dev->recv = bcm_sf2_eth_receive; - dev->write_hwaddr = bcm_sf2_eth_write_hwaddr; - -#ifdef CONFIG_BCM_SF2_ETH_GMAC - if (gmac_add(dev)) { - free(eth); - free(dev); - pr_err("%s: Adding GMAC failed!\n", __func__); - return -1; - } -#else -#error "bcm_sf2_eth: NEED to register a MAC!" -#endif - - eth_register(dev); - -#ifdef CONFIG_CMD_MII - int retval; - struct mii_dev *mdiodev = mdio_alloc(); - - if (!mdiodev) - return -ENOMEM; - strlcpy(mdiodev->name, dev->name, MDIO_NAME_LEN); - mdiodev->read = eth->miiphy_read; - mdiodev->write = eth->miiphy_write; - - retval = mdio_register(mdiodev); - if (retval < 0) - return retval; -#endif - - /* Initialization */ - debug("Ethernet initialization ..."); - - rc = bcm_sf2_eth_init(dev); - if (rc != 0) { - pr_err("%s: configuration failed!\n", __func__); - return -1; - } - - printf("Basic ethernet functionality initialized\n"); - - return 0; -} diff --git a/drivers/net/bcm-sf2-eth.h b/drivers/net/bcm-sf2-eth.h deleted file mode 100644 index f4dbb4e1952..00000000000 --- a/drivers/net/bcm-sf2-eth.h +++ /dev/null @@ -1,65 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2014-2017 Broadcom. - */ - -#ifndef _BCM_SF2_ETH_H_ -#define _BCM_SF2_ETH_H_ - -#include <phy.h> - -#define RX_BUF_SIZE 2048 -/* RX_BUF_NUM must be power of 2 */ -#define RX_BUF_NUM 32 - -#define TX_BUF_SIZE 2048 -/* TX_BUF_NUM must be power of 2 */ -#define TX_BUF_NUM 2 - -/* Support 2 Ethernet ports now */ -#define BCM_ETH_MAX_PORT_NUM 2 - -enum { - MAC_DMA_TX = 1, - MAC_DMA_RX = 2 -}; - -struct eth_dma { - void *tx_desc_aligned; - void *rx_desc_aligned; - - uint8_t *tx_buf; - uint8_t *rx_buf; - - int cur_tx_index; - int cur_rx_index; - - int (*tx_packet)(struct eth_dma *dma, void *packet, int length); - bool (*check_tx_done)(struct eth_dma *dma); - - int (*check_rx_done)(struct eth_dma *dma, uint8_t *buf); - - int (*enable_dma)(struct eth_dma *dma, int dir); - int (*disable_dma)(struct eth_dma *dma, int dir); -}; - -struct eth_info { - struct eth_dma dma; - phy_interface_t phy_interface; - struct phy_device *port[BCM_ETH_MAX_PORT_NUM]; - int port_num; - - int (*miiphy_read)(struct mii_dev *bus, int phyaddr, int devad, - int reg); - int (*miiphy_write)(struct mii_dev *bus, int phyaddr, int devad, - int reg, u16 value); - - int (*mac_init)(struct eth_device *dev); - int (*enable_mac)(void); - int (*disable_mac)(void); - int (*set_mac_addr)(unsigned char *mac); - int (*set_mac_speed)(int speed, int duplex); - -}; - -#endif /* _BCM_SF2_ETH_H_ */ diff --git a/drivers/net/fsl_enetc.c b/drivers/net/fsl_enetc.c index 97cccda4519..a4ba27904bc 100644 --- a/drivers/net/fsl_enetc.c +++ b/drivers/net/fsl_enetc.c @@ -6,6 +6,7 @@ */ #include <clk.h> +#include <cpu_func.h> #include <dm.h> #include <errno.h> #include <fdt_support.h> diff --git a/drivers/net/ftgmac100.c b/drivers/net/ftgmac100.c index f5ea2e72d1b..33d1f7da3d7 100644 --- a/drivers/net/ftgmac100.c +++ b/drivers/net/ftgmac100.c @@ -546,7 +546,7 @@ static int ftgmac100_send(struct udevice *dev, void *packet, int length) return -EPERM; } - debug("%s(%x, %x)\n", __func__, (int)packet, length); + debug("%s(%p, %x)\n", __func__, packet, length); length = (length < ETH_ZLEN) ? ETH_ZLEN : length; diff --git a/drivers/net/hifemac.c b/drivers/net/hifemac.c index 90cc247b3b6..62182f922f8 100644 --- a/drivers/net/hifemac.c +++ b/drivers/net/hifemac.c @@ -9,6 +9,7 @@ #include <dm.h> #include <clk.h> +#include <cpu_func.h> #include <miiphy.h> #include <net.h> #include <reset.h> diff --git a/drivers/net/pfe_eth/Kconfig b/drivers/net/pfe_eth/Kconfig index b2724ee3e84..f5947ab5f17 100644 --- a/drivers/net/pfe_eth/Kconfig +++ b/drivers/net/pfe_eth/Kconfig @@ -1,5 +1,6 @@ menuconfig FSL_PFE bool "NXP PFE Ethernet driver" + depends on ARCH_LS1012A help This driver provides support for NXP's Packet Forwarding Engine. diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig index 8d88c142900..21bf983056a 100644 --- a/drivers/net/phy/Kconfig +++ b/drivers/net/phy/Kconfig @@ -23,7 +23,10 @@ config PHY_ANEG_TIMEOUT int "PHY auto-negotiation timeout" default 4000 help - Default PHY auto-negotiation timeout. + Value of PHY auto-negotiation timeout with the base being + "decimal" and the unit being "millisecond". This can be + overridden by the "phy_aneg_timeout" environment variable + that has the same base (decimal) and unit (millisecond). if PHY_ADDR_ENABLE config PHY_ADDR diff --git a/drivers/net/phy/aquantia.c b/drivers/net/phy/aquantia.c index d2db8d9f792..f63a13824ca 100644 --- a/drivers/net/phy/aquantia.c +++ b/drivers/net/phy/aquantia.c @@ -7,6 +7,7 @@ */ #include <config.h> #include <dm.h> +#include <env.h> #include <log.h> #include <net.h> #include <phy.h> @@ -551,14 +552,15 @@ int aquantia_config(struct phy_device *phydev) int aquantia_startup(struct phy_device *phydev) { - u32 speed; - int i = 0; + u32 speed, i = 0; int reg; phydev->duplex = DUPLEX_FULL; /* if the AN is still in progress, wait till timeout. */ if (!aquantia_link_is_up(phydev)) { + u32 aneg_timeout = env_get_ulong("phy_aneg_timeout", 10, + CONFIG_PHY_ANEG_TIMEOUT); printf("%s Waiting for PHY auto negotiation to complete", phydev->dev->name); do { @@ -566,9 +568,9 @@ int aquantia_startup(struct phy_device *phydev) if ((i++ % 500) == 0) printf("."); } while (!aquantia_link_is_up(phydev) && - i < (4 * CONFIG_PHY_ANEG_TIMEOUT)); + i < (4 * aneg_timeout)); - if (i > CONFIG_PHY_ANEG_TIMEOUT) + if (i > aneg_timeout) printf(" TIMEOUT !\n"); } diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c index e6fed8c41d7..9702d042296 100644 --- a/drivers/net/phy/phy.c +++ b/drivers/net/phy/phy.c @@ -9,6 +9,7 @@ */ #include <console.h> #include <dm.h> +#include <env.h> #include <log.h> #include <malloc.h> #include <net.h> @@ -242,7 +243,9 @@ int genphy_update_link(struct phy_device *phydev) if ((phydev->autoneg == AUTONEG_ENABLE) && !(mii_reg & BMSR_ANEGCOMPLETE)) { - int i = 0; + u32 i = 0; + u32 aneg_timeout = env_get_ulong("phy_aneg_timeout", 10, + CONFIG_PHY_ANEG_TIMEOUT); printf("%s Waiting for PHY auto negotiation to complete", phydev->dev->name); @@ -250,7 +253,7 @@ int genphy_update_link(struct phy_device *phydev) /* * Timeout reached ? */ - if (i > (CONFIG_PHY_ANEG_TIMEOUT / 50)) { + if (i > (aneg_timeout / 50)) { printf(" TIMEOUT !\n"); phydev->link = 0; return -ETIMEDOUT; diff --git a/drivers/net/qe/Kconfig b/drivers/net/qe/Kconfig index e795e913d42..34de2390310 100644 --- a/drivers/net/qe/Kconfig +++ b/drivers/net/qe/Kconfig @@ -4,5 +4,6 @@ config QE_UEC bool "NXP QE UEC Ethernet controller" + depends on PPC help This driver supports the NXP QE UEC ethernet controller diff --git a/drivers/net/ti/Kconfig b/drivers/net/ti/Kconfig index ddfa95a0b7e..52267339de0 100644 --- a/drivers/net/ti/Kconfig +++ b/drivers/net/ti/Kconfig @@ -4,6 +4,7 @@ config DRIVER_TI_CPSW bool "TI Common Platform Ethernet Switch" + depends on ARCH_OMAP2PLUS select PHYLIB help This driver supports the TI three port switch gigabit ethernet @@ -11,6 +12,7 @@ config DRIVER_TI_CPSW config DRIVER_TI_EMAC bool "TI Davinci EMAC" + depends on ARCH_DAVINCI || ARCH_OMAP2PLUS help Support for davinci emac @@ -22,6 +24,7 @@ config DRIVER_TI_EMAC_USE_RMII config DRIVER_TI_KEYSTONE_NET bool "TI Keystone 2 Ethernet" + depends on ARCH_KEYSTONE help This driver supports the TI Keystone 2 Ethernet subsystem diff --git a/drivers/net/xilinx_axi_emac.c b/drivers/net/xilinx_axi_emac.c index 4d87e2d1f36..c8038ddef1b 100644 --- a/drivers/net/xilinx_axi_emac.c +++ b/drivers/net/xilinx_axi_emac.c @@ -11,6 +11,7 @@ #include <display_options.h> #include <dm.h> #include <dm/device_compat.h> +#include <env.h> #include <log.h> #include <net.h> #include <malloc.h> @@ -343,6 +344,8 @@ static int axiemac_phy_init(struct udevice *dev) static int pcs_pma_startup(struct axidma_priv *priv) { + u32 aneg_timeout = env_get_ulong("phy_aneg_timeout", 10, + CONFIG_PHY_ANEG_TIMEOUT); u32 rc, retry_cnt = 0; u16 mii_reg; @@ -361,7 +364,7 @@ static int pcs_pma_startup(struct axidma_priv *priv) * and the external PHY is not obtained. */ debug("axiemac: waiting for link status of the PCS/PMA PHY"); - while (retry_cnt * 10 < CONFIG_PHY_ANEG_TIMEOUT) { + while (retry_cnt * 10 < aneg_timeout) { rc = phyread(priv, priv->pcsaddr, MII_BMSR, &mii_reg); if ((mii_reg & BMSR_LSTATUS) && mii_reg != 0xffff && !rc) { debug(".Done\n"); diff --git a/drivers/pwm/pwm-stm32.c b/drivers/pwm/pwm-stm32.c index 5fa649b5903..a691f75e4a7 100644 --- a/drivers/pwm/pwm-stm32.c +++ b/drivers/pwm/pwm-stm32.c @@ -12,6 +12,7 @@ #include <asm/io.h> #include <asm/arch/timers.h> #include <dm/device_compat.h> +#include <linux/bitfield.h> #include <linux/time.h> #define CCMR_CHANNEL_SHIFT 8 @@ -157,7 +158,14 @@ static void stm32_pwm_detect_complementary(struct udevice *dev) { struct stm32_timers_plat *plat = dev_get_plat(dev_get_parent(dev)); struct stm32_pwm_priv *priv = dev_get_priv(dev); - u32 ccer; + u32 ccer, val; + + if (plat->ipidr) { + /* Simply read from HWCFGR the number of complementary outputs (MP25). */ + val = readl(plat->base + TIM_HWCFGR1); + priv->have_complementary_output = !!FIELD_GET(TIM_HWCFGR1_NB_OF_DT, val); + return; + } /* * If complementary bit doesn't exist writing 1 will have no @@ -192,6 +200,7 @@ static const struct pwm_ops stm32_pwm_ops = { static const struct udevice_id stm32_pwm_ids[] = { { .compatible = "st,stm32-pwm" }, + { .compatible = "st,stm32mp25-pwm" }, { } }; diff --git a/drivers/qe/Kconfig b/drivers/qe/Kconfig index 89a75c175b0..22ed80bfc66 100644 --- a/drivers/qe/Kconfig +++ b/drivers/qe/Kconfig @@ -11,6 +11,7 @@ config QE config U_QE bool "Enable support for U QUICC Engine" + depends on PPC || ARCH_LS1012A || ARCH_LS1021A || ARCH_LS1043A default y if (ARCH_LS1021A && !SD_BOOT && !NAND_BOOT && !QSPI_BOOT) \ || (TARGET_T1024QDS) \ || (TARGET_T1024RDB) \ diff --git a/drivers/reset/stm32/Kconfig b/drivers/reset/stm32/Kconfig index 39dcfa0a9ca..fdd88a6bfae 100644 --- a/drivers/reset/stm32/Kconfig +++ b/drivers/reset/stm32/Kconfig @@ -16,7 +16,7 @@ config RESET_STM32MP1 config RESET_STM32MP25 bool "Enable the STM32MP25 reset" - depends on STM32MP25X + depends on STM32MP23X || STM32MP25X default y help Support for reset controllers on STMicroelectronics STM32MP2 family SoCs. diff --git a/drivers/reset/stm32/stm32-reset-core.c b/drivers/reset/stm32/stm32-reset-core.c index 7dd92e07e1a..9eeed6536e0 100644 --- a/drivers/reset/stm32/stm32-reset-core.c +++ b/drivers/reset/stm32/stm32-reset-core.c @@ -6,7 +6,7 @@ #include <dm.h> #include <reset-uclass.h> -#include <stm32-reset-core.h> +#include "stm32-reset-core.h" #include <stm32_rcc.h> #include <dm/device_compat.h> #include <linux/iopoll.h> diff --git a/drivers/reset/stm32/stm32-reset-mp1.c b/drivers/reset/stm32/stm32-reset-mp1.c index 6863f6e64b7..ce4532561e5 100644 --- a/drivers/reset/stm32/stm32-reset-mp1.c +++ b/drivers/reset/stm32/stm32-reset-mp1.c @@ -5,7 +5,7 @@ */ #include <dm.h> -#include <stm32-reset-core.h> +#include "stm32-reset-core.h" /* Reset clear offset for STM32MP RCC */ #define RCC_CLR_OFFSET 0x4 diff --git a/drivers/reset/stm32/stm32-reset-mp25.c b/drivers/reset/stm32/stm32-reset-mp25.c index 91c0336bc58..1cbe5c7f3d5 100644 --- a/drivers/reset/stm32/stm32-reset-mp25.c +++ b/drivers/reset/stm32/stm32-reset-mp25.c @@ -5,7 +5,7 @@ */ #include <dm.h> -#include <stm32-reset-core.h> +#include "stm32-reset-core.h" #include <stm32mp25_rcc.h> #include <dt-bindings/reset/st,stm32mp25-rcc.h> diff --git a/drivers/reset/stm32/stm32-reset.c b/drivers/reset/stm32/stm32-reset.c index 975f67f712a..024f15cb25e 100644 --- a/drivers/reset/stm32/stm32-reset.c +++ b/drivers/reset/stm32/stm32-reset.c @@ -5,7 +5,7 @@ */ #include <dm.h> -#include <stm32-reset-core.h> +#include "stm32-reset-core.h" /* Timeout for deassert */ #define STM32_DEASSERT_TIMEOUT_US 10000 @@ -19,7 +19,7 @@ static const struct stm32_reset_cfg *stm32_get_reset_line(struct reset_ctl *rese ptr_line->offset = bank; ptr_line->bit_idx = offset; - ptr_line->set_clr = true; + ptr_line->set_clr = false; return ptr_line; } diff --git a/drivers/virtio/virtio_net.c b/drivers/virtio/virtio_net.c index 0e5367a085e..71e4d251396 100644 --- a/drivers/virtio/virtio_net.c +++ b/drivers/virtio/virtio_net.c @@ -128,6 +128,7 @@ static int virtio_net_free_pkt(struct udevice *dev, uchar *packet, int length) /* Put the buffer back to the rx ring */ virtqueue_add(priv->rx_vq, sgs, 0, 1); + virtqueue_kick(priv->rx_vq); return 0; } diff --git a/include/configs/bcm_ns3.h b/include/configs/bcm_ns3.h index 7c6e0725a6c..8584b2b99c6 100644 --- a/include/configs/bcm_ns3.h +++ b/include/configs/bcm_ns3.h @@ -44,20 +44,11 @@ #define PCIE_ARGS "pcie_args=pci=pcie_bus_safe pcie_ports=native vfio_pci.disable_idle_d3=1\0" -#ifdef CONFIG_BCM_SF2_ETH -#define BCM_ETH_ADDR "ethaddr=00:0A:F7:95:65:A4\0" -#define NET_ARGS "bgmac_platform.ethaddr=${ethaddr} " \ - "ip=${ipaddr}::${gatewayip}:${netmask}::${ethif}:off" -#else -#define BMC_ETH_ADDR -#define NET_ARGS -#endif - #define RESERVED_MEM "reserved_mem=memmap=0xff000000$0x1000000\0" #define BASE_ARGS "${console_args} ${extra_args} ${pcie_args}" \ " ${max_cpus} ${log_level} ${reserved_mem}" -#define SETBOOTARGS "setbootargs=setenv bootargs " BASE_ARGS " " NET_ARGS "\0" +#define SETBOOTARGS "setbootargs=setenv bootargs " BASE_ARGS "\0" #define UPDATEME_FLASH_PARAMS "bcm_compat_level=4\0" \ "bcm_need_recovery_rootfs=0\0" \ @@ -749,7 +740,6 @@ OS_LOG_LEVEL \ EXTRA_ARGS \ PCIE_ARGS \ - BMC_ETH_ADDR \ RESERVED_MEM \ SETBOOTARGS \ UPDATEME_FLASH_PARAMS \ diff --git a/include/configs/stm32mp23_common.h b/include/configs/stm32mp23_common.h new file mode 100644 index 00000000000..7285886b822 --- /dev/null +++ b/include/configs/stm32mp23_common.h @@ -0,0 +1,130 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause */ +/* + * Copyright (C) 2025, STMicroelectronics - All Rights Reserved + * + * Configuration settings for the STM32MP23x CPU + */ + +#ifndef __CONFIG_STM32MP23_COMMMON_H +#define __CONFIG_STM32MP23_COMMMON_H +#include <linux/sizes.h> +#include <asm/arch/stm32.h> + +/* + * Configuration of the external SRAM memory used by U-Boot + */ +#define CFG_SYS_SDRAM_BASE STM32_DDR_BASE + +/* + * For booting Linux, use the first 256 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_SYS_BOOTMAPSZ SZ_256M + +#define STM32MP_FIP_IMAGE_GUID \ + EFI_GUID(0x19d5df83, 0x11b0, 0x457b, 0xbe, 0x2c, \ + 0x75, 0x59, 0xc1, 0x31, 0x42, 0xa5) + +/*****************************************************************************/ +#ifdef CONFIG_DISTRO_DEFAULTS +/*****************************************************************************/ + +#ifdef CONFIG_NET +#define BOOT_TARGET_PXE(func) func(PXE, pxe, na) +#else +#define BOOT_TARGET_PXE(func) +#endif + +#ifdef CONFIG_CMD_MMC +#define BOOT_TARGET_MMC0(func) func(MMC, mmc, 0) +#define BOOT_TARGET_MMC1(func) func(MMC, mmc, 1) +#define BOOT_TARGET_MMC2(func) func(MMC, mmc, 2) +#else +#define BOOT_TARGET_MMC0(func) +#define BOOT_TARGET_MMC1(func) +#define BOOT_TARGET_MMC2(func) +#endif + +#ifdef CONFIG_CMD_UBIFS +#define BOOT_TARGET_UBIFS(func) func(UBIFS, ubifs, 0, UBI, boot) +#else +#define BOOT_TARGET_UBIFS(func) +#endif + +#ifdef CONFIG_CMD_USB +#define BOOT_TARGET_USB(func) func(USB, usb, 0) +#else +#define BOOT_TARGET_USB(func) +#endif + +#define BOOT_TARGET_DEVICES(func) \ + BOOT_TARGET_MMC1(func) \ + BOOT_TARGET_UBIFS(func) \ + BOOT_TARGET_MMC0(func) \ + BOOT_TARGET_MMC2(func) \ + BOOT_TARGET_USB(func) \ + BOOT_TARGET_PXE(func) + +/* + * default bootcmd for stm32mp23: + * for serial/usb: execute the stm32prog command + * for mmc boot (eMMC, SD card), distro boot on the same mmc device + * for NAND or SPI-NAND boot, distro boot with UBIFS on UBI partition + * for other boot, use the default distro order in ${boot_targets} + */ +#define STM32MP_BOOTCMD "bootcmd_stm32mp=" \ + "echo \"Boot over ${boot_device}${boot_instance}!\";" \ + "if test ${boot_device} = serial || test ${boot_device} = usb;" \ + "then stm32prog ${boot_device} ${boot_instance}; " \ + "else " \ + "run env_check;" \ + "if test ${boot_device} = mmc;" \ + "then env set boot_targets \"mmc${boot_instance}\"; fi;" \ + "if test ${boot_device} = nand ||" \ + " test ${boot_device} = spi-nand ;" \ + "then env set boot_targets ubifs0; fi;" \ + "run distro_bootcmd;" \ + "fi;\0" + +#ifndef STM32MP_BOARD_EXTRA_ENV +#define STM32MP_BOARD_EXTRA_ENV +#endif + +#define STM32MP_EXTRA \ + "env_check=if env info -p -d -q; then env save; fi\0" \ + "boot_net_usb_start=true\0" +/* + * memory layout for 96MB uncompressed/compressed kernel, + * 1M fdt, 1M script, 1M pxe and 1M for overlay + * and the ramdisk at the end. + */ +#define __KERNEL_COMP_ADDR_R __stringify(0x84000000) +#define __KERNEL_COMP_SIZE_R __stringify(0x04000000) +#define __KERNEL_ADDR_R __stringify(0x8a000000) +#define __FDT_ADDR_R __stringify(0x90000000) +#define __SCRIPT_ADDR_R __stringify(0x90100000) +#define __PXEFILE_ADDR_R __stringify(0x90200000) +#define __FDTOVERLAY_ADDR_R __stringify(0x90300000) +#define __RAMDISK_ADDR_R __stringify(0x90400000) + +#define STM32MP_MEM_LAYOUT \ + "kernel_addr_r=" __KERNEL_ADDR_R "\0" \ + "fdt_addr_r=" __FDT_ADDR_R "\0" \ + "scriptaddr=" __SCRIPT_ADDR_R "\0" \ + "pxefile_addr_r=" __PXEFILE_ADDR_R "\0" \ + "fdtoverlay_addr_r=" __FDTOVERLAY_ADDR_R "\0" \ + "ramdisk_addr_r=" __RAMDISK_ADDR_R "\0" \ + "kernel_comp_addr_r=" __KERNEL_COMP_ADDR_R "\0" \ + "kernel_comp_size=" __KERNEL_COMP_SIZE_R "\0" + +#include <config_distro_bootcmd.h> +#define CFG_EXTRA_ENV_SETTINGS \ + STM32MP_MEM_LAYOUT \ + STM32MP_BOOTCMD \ + BOOTENV \ + STM32MP_EXTRA \ + STM32MP_BOARD_EXTRA_ENV + +#endif + +#endif /* __CONFIG_STM32MP23_COMMMON_H */ diff --git a/include/configs/stm32mp23_st_common.h b/include/configs/stm32mp23_st_common.h new file mode 100644 index 00000000000..0c5c2fbef87 --- /dev/null +++ b/include/configs/stm32mp23_st_common.h @@ -0,0 +1,51 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause */ +/* + * Copyright (C) 2025, STMicroelectronics - All Rights Reserved + * + * Configuration settings for the STMicroelectonics STM32MP23x boards + */ + +#ifndef __CONFIG_STM32MP23_ST_COMMON_H__ +#define __CONFIG_STM32MP23_ST_COMMON_H__ + +#define STM32MP_BOARD_EXTRA_ENV \ + "usb_pgood_delay=2000\0" \ + "console=ttySTM0\0" + +#include <configs/stm32mp23_common.h> + +#ifdef CFG_EXTRA_ENV_SETTINGS +/* + * default bootcmd for stm32mp23 STMicroelectronics boards: + * for serial/usb: execute the stm32prog command + * for mmc boot (eMMC, SD card), distro boot on the same mmc device + * for nand or spi-nand boot, distro boot with ubifs on UBI partition or + * sdcard + * for nor boot, distro boot on SD card = mmc0 ONLY ! + */ +#define ST_STM32MP23_BOOTCMD "bootcmd_stm32mp=" \ + "echo \"Boot over ${boot_device}${boot_instance}!\";" \ + "if test ${boot_device} = serial || test ${boot_device} = usb;" \ + "then stm32prog ${boot_device} ${boot_instance}; " \ + "else " \ + "run env_check;" \ + "if test ${boot_device} = mmc;" \ + "then env set boot_targets \"mmc${boot_instance}\"; fi;" \ + "if test ${boot_device} = nand ||" \ + " test ${boot_device} = spi-nand ;" \ + "then env set boot_targets ubifs0 mmc0; fi;" \ + "if test ${boot_device} = nor;" \ + "then env set boot_targets mmc0; fi;" \ + "run distro_bootcmd;" \ + "fi;\0" + +#undef CFG_EXTRA_ENV_SETTINGS +#define CFG_EXTRA_ENV_SETTINGS \ + STM32MP_MEM_LAYOUT \ + ST_STM32MP23_BOOTCMD \ + BOOTENV \ + STM32MP_EXTRA \ + STM32MP_BOARD_EXTRA_ENV + +#endif +#endif diff --git a/include/configs/stm32mp25_st_common.h b/include/configs/stm32mp25_st_common.h index ab5a4a91644..cb679eb1be2 100644 --- a/include/configs/stm32mp25_st_common.h +++ b/include/configs/stm32mp25_st_common.h @@ -2,7 +2,7 @@ /* * Copyright (C) 2022, STMicroelectronics - All Rights Reserved * - * Configuration settings for the STMicroelectonics STM32MP25x boards + * Configuration settings for the STMicroelectronics STM32MP25x boards */ #ifndef __CONFIG_STM32MP25_ST_COMMON_H__ diff --git a/include/net/tcp.h b/include/net/tcp.h index 5022fa9dc1b..6f4d58a1234 100644 --- a/include/net/tcp.h +++ b/include/net/tcp.h @@ -235,7 +235,7 @@ struct pseudo_hdr { u16 len; } __packed; -#define PSEUDO_HDR_SIZE (sizeof(struct pseudo_hdr)) - PSEUDO_PAD_SIZE +#define PSEUDO_HDR_SIZE ((sizeof(struct pseudo_hdr)) - PSEUDO_PAD_SIZE) /** * union tcp_build_pkt - union for building TCP/IP packet. diff --git a/lib/lwip/u-boot/arch/cc.h b/lib/lwip/u-boot/arch/cc.h index f91127ac565..04ab94d6b70 100644 --- a/lib/lwip/u-boot/arch/cc.h +++ b/lib/lwip/u-boot/arch/cc.h @@ -47,4 +47,13 @@ void sntp_set_system_time(uint32_t sec); #define SNTP_SET_SYSTEM_TIME(sec) sntp_set_system_time(sec) +static inline const char *sntp_format_time(time_t t) +{ + static char buf[29]; /* "(time_t)" + 20 digits max + \0 */ + + snprintf(buf, sizeof(buf), "(time_t)%llu", t); + return buf; +} + +#define sntp_format_time sntp_format_time #endif /* LWIP_ARCH_CC_H */ diff --git a/net/lwip/net-lwip.c b/net/lwip/net-lwip.c index 3918d57d7e5..660ceb10cbe 100644 --- a/net/lwip/net-lwip.c +++ b/net/lwip/net-lwip.c @@ -184,16 +184,12 @@ int net_lwip_eth_start(void) int ret; net_init(); - if (eth_is_on_demand_init()) { + eth_halt(); + eth_set_current(); + ret = eth_init(); + if (ret < 0) { eth_halt(); - eth_set_current(); - ret = eth_init(); - if (ret < 0) { - eth_halt(); - return ret; - } - } else { - eth_init_state_only(); + return ret; } return 0; @@ -285,7 +281,6 @@ int net_init(void) if (!init_done) { eth_init_rings(); - eth_init(); lwip_init(); init_done = true; } diff --git a/net/tcp.c b/net/tcp.c index 2635727f47d..8740150365f 100644 --- a/net/tcp.c +++ b/net/tcp.c @@ -804,7 +804,7 @@ void tcp_parse_options(struct tcp_stream *tcp, uchar *o, int o_len) } /* Process optional NOPs */ - if (p[0] == TCP_O_NOP) + if (p[0] == TCP_1_NOP) p++; else p += p[1]; diff --git a/net/wget.c b/net/wget.c index 3c0fff488eb..428ee072330 100644 --- a/net/wget.c +++ b/net/wget.c @@ -214,7 +214,7 @@ static void tcp_stream_on_rcv_nxt_update(struct tcp_stream *tcp, u32 rx_bytes) content_length = -1; } - if (content_length >= 0) { + if (content_length != -1) { debug_cond(DEBUG_WGET, "wget: Connected Len %lu\n", content_length); |