diff options
Diffstat (limited to 'arch/arm/include/asm')
| -rw-r--r-- | arch/arm/include/asm/arch-imx9/ddr.h | 1 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-mx27/imx-regs.h | 5 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h | 49 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-sunxi/cpu_sunxi_ncat2.h | 20 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-sunxi/dram.h | 2 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-sunxi/dram_sun55i_a523.h | 153 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-sunxi/watchdog.h | 2 | ||||
| -rw-r--r-- | arch/arm/include/asm/mach-imx/ele_api.h | 2 |
8 files changed, 215 insertions, 19 deletions
diff --git a/arch/arm/include/asm/arch-imx9/ddr.h b/arch/arm/include/asm/arch-imx9/ddr.h index 0dd2d62b9ef..a8e3f7354c7 100644 --- a/arch/arm/include/asm/arch-imx9/ddr.h +++ b/arch/arm/include/asm/arch-imx9/ddr.h @@ -118,6 +118,7 @@ void ddrphy_init_set_dfi_clk(unsigned int drate); void ddrphy_init_read_msg_block(enum fw_type type); void get_trained_CDD(unsigned int fsp); +u32 lpddr4_mr_read(u32 mr_rank, u32 mr_addr); ulong ddrphy_addr_remap(u32 paddr_apb_from_ctlr); diff --git a/arch/arm/include/asm/arch-mx27/imx-regs.h b/arch/arm/include/asm/arch-mx27/imx-regs.h index 60499189b2c..a9152814245 100644 --- a/arch/arm/include/asm/arch-mx27/imx-regs.h +++ b/arch/arm/include/asm/arch-mx27/imx-regs.h @@ -21,11 +21,6 @@ extern void mx27_uart1_init_pins(void); extern void mx27_fec_init_pins(void); #endif /* CONFIG_FEC_MXC */ -#ifdef CONFIG_MMC_MXC -extern void mx27_sd1_init_pins(void); -extern void mx27_sd2_init_pins(void); -#endif /* CONFIG_MMC_MXC */ - /* AIPI */ struct aipi_regs { u32 psr0; diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h b/arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h index 575dff68804..45fa4ab6e57 100644 --- a/arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h +++ b/arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h @@ -13,6 +13,7 @@ #include <linux/bitops.h> #endif +/* Main CCU register offsets */ #define CCU_H6_PLL1_CFG 0x000 #define CCU_H6_PLL5_CFG 0x010 #define CCU_H6_PLL6_CFG 0x020 @@ -31,29 +32,39 @@ #define CCU_H6_UART_GATE_RESET 0x90c #define CCU_H6_I2C_GATE_RESET 0x91c -/* pll1 bit field */ -#define CCM_PLL1_CTRL_EN BIT(31) -#define CCM_PLL1_LDO_EN BIT(30) -#define CCM_PLL1_LOCK_EN BIT(29) -#define CCM_PLL1_LOCK BIT(28) -#define CCM_PLL1_OUT_EN BIT(27) -#define CCM_PLL1_CLOCK_TIME_2 (2 << 24) +/* A523 CPU PLL offsets */ +#define CPC_CPUA_PLL_CTRL 0x04 +#define CPC_DSU_PLL_CTRL 0x08 +#define CPC_CPUB_PLL_CTRL 0x0c +#define CPC_CPUA_CLK_REG 0x60 +#define CPC_CPUB_CLK_REG 0x64 +#define CPC_DSU_CLK_REG 0x6c + +/* PLL bit fields */ +#define CCM_PLL_CTRL_EN BIT(31) +#define CCM_PLL_LDO_EN BIT(30) +#define CCM_PLL_LOCK_EN BIT(29) +#define CCM_PLL_LOCK BIT(28) +#define CCM_PLL_OUT_EN BIT(27) +#define CCM_PLL1_UPDATE BIT(26) #define CCM_PLL1_CTRL_P(p) ((p) << 16) +#define CCM_PLL1_CTRL_N_MASK GENMASK(15, 8) #define CCM_PLL1_CTRL_N(n) (((n) - 1) << 8) +/* A523 CPU clock fields */ +#define CPU_CLK_SRC_HOSC (0 << 24) +#define CPU_CLK_SRC_CPUPLL (3 << 24) +#define CPU_CLK_CTRL_P(p) ((p) << 16) +#define CPU_CLK_APB_DIV(n) (((n) - 1) << 8) +#define CPU_CLK_PERI_DIV(m1) (((m1) - 1) << 2) +#define CPU_CLK_AXI_DIV(m) (((m) - 1) << 0) + /* pll5 bit field */ -#define CCM_PLL5_CTRL_EN BIT(31) -#define CCM_PLL5_LOCK_EN BIT(29) -#define CCM_PLL5_LOCK BIT(28) -#define CCM_PLL5_OUT_EN BIT(27) #define CCM_PLL5_CTRL_N(n) (((n) - 1) << 8) #define CCM_PLL5_CTRL_DIV1(div1) ((div1) << 0) #define CCM_PLL5_CTRL_DIV2(div0) ((div0) << 1) /* pll6 bit field */ -#define CCM_PLL6_CTRL_EN BIT(31) -#define CCM_PLL6_LOCK_EN BIT(29) -#define CCM_PLL6_LOCK BIT(28) #define CCM_PLL6_CTRL_P0_SHIFT 16 #define CCM_PLL6_CTRL_P0_MASK (0x7 << CCM_PLL6_CTRL_P0_SHIFT) #define CCM_PLL6_CTRL_N_SHIFT 8 @@ -97,6 +108,13 @@ #define CCM_PSI_AHB1_AHB2_DEFAULT 0x03000002 #define CCM_AHB3_DEFAULT 0x03000002 #define CCM_APB1_DEFAULT 0x03000102 + +#elif CONFIG_MACH_SUN55I_A523 /* A523 */ + +#define CCM_PLL6_DEFAULT 0xe8216310 /* 1200 MHz */ +#define CCM_PSI_AHB1_AHB2_DEFAULT 0x03000002 /* 200 MHz */ +#define CCM_APB1_DEFAULT 0x03000005 /* APB0 really */ +#define CCM_APB2_DEFAULT 0x03000005 /* APB1 really */ #endif /* apb2 bit field */ @@ -116,6 +134,7 @@ /* MBUS clock bit field */ #define MBUS_ENABLE BIT(31) #define MBUS_RESET BIT(30) +#define MBUS_UPDATE BIT(27) #define MBUS_CLK_SRC_MASK GENMASK(25, 24) #define MBUS_CLK_SRC_OSCM24 (0 << 24) #define MBUS_CLK_SRC_PLL6X2 (1 << 24) @@ -128,10 +147,12 @@ #define GATE_SHIFT (0) /* DRAM clock bit field */ +#define DRAM_CLK_ENABLE BIT(31) #define DRAM_MOD_RESET BIT(30) #define DRAM_CLK_UPDATE BIT(27) #define DRAM_CLK_SRC_MASK GENMASK(25, 24) #define DRAM_CLK_SRC_PLL5 (0 << 24) +#define DRAM_CLK_M_MASK (0x1f) #define DRAM_CLK_M(m) (((m)-1) << 0) /* MMC clock bit field */ diff --git a/arch/arm/include/asm/arch-sunxi/cpu_sunxi_ncat2.h b/arch/arm/include/asm/arch-sunxi/cpu_sunxi_ncat2.h index 908a582ae0f..bcfdc0a41c5 100644 --- a/arch/arm/include/asm/arch-sunxi/cpu_sunxi_ncat2.h +++ b/arch/arm/include/asm/arch-sunxi/cpu_sunxi_ncat2.h @@ -21,14 +21,34 @@ #define SUNXI_SID_BASE 0x03006200 #define SUNXI_GIC400_BASE 0x03020000 +#ifdef CONFIG_MACH_SUN55I_A523 +#define SUNXI_DRAM_COM_BASE 0x03120000 +#define SUNXI_DRAM_CTL0_BASE 0x03130000 +#define SUNXI_DRAM_PHY0_BASE 0x03140000 +#endif + #define SUNXI_MMC0_BASE 0x04020000 #define SUNXI_MMC1_BASE 0x04021000 #define SUNXI_MMC2_BASE 0x04022000 +#ifndef CONFIG_MACH_SUN55I_A523 #define SUNXI_R_CPUCFG_BASE 0x07000400 +#endif #define SUNXI_PRCM_BASE 0x07010000 +#define SUNXI_R_WDOG_BASE 0x07020400 +#ifdef CONFIG_MACH_SUN55I_A523 +#define SUNXI_R_CPUCFG_BASE 0x07050000 +#endif +#define SUNXI_R_TWI_BASE 0x07081400 +#define SUNXI_RTC_BASE 0x07090000 +#ifdef CONFIG_MACH_SUN55I_A523 +#define SUNXI_CPUCFG_BASE 0x08815000 +#else #define SUNXI_CPUCFG_BASE 0x09010000 +#endif + +#define SUNXI_CPU_PLL_CFG_BASE 0x08817000 #ifndef __ASSEMBLY__ void sunxi_board_init(void); diff --git a/arch/arm/include/asm/arch-sunxi/dram.h b/arch/arm/include/asm/arch-sunxi/dram.h index 0708ae3ee3b..0eccb1e6c28 100644 --- a/arch/arm/include/asm/arch-sunxi/dram.h +++ b/arch/arm/include/asm/arch-sunxi/dram.h @@ -35,6 +35,8 @@ #include <asm/arch/dram_sun50i_a133.h> #elif defined(CONFIG_MACH_SUNIV) #include <asm/arch/dram_suniv.h> +#elif defined(CONFIG_MACH_SUN55I_A523) +#include <asm/arch/dram_sun55i_a523.h> #else #include <asm/arch/dram_sun4i.h> #endif diff --git a/arch/arm/include/asm/arch-sunxi/dram_sun55i_a523.h b/arch/arm/include/asm/arch-sunxi/dram_sun55i_a523.h new file mode 100644 index 00000000000..08bfe462856 --- /dev/null +++ b/arch/arm/include/asm/arch-sunxi/dram_sun55i_a523.h @@ -0,0 +1,153 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * t527 dram controller register and constant defines + * + * (C) Copyright 2024 Jernej Skrabec <jernej.skrabec@gmail.com> + */ + +#ifndef _SUNXI_DRAM_SUN55I_A523_H +#define _SUNXI_DRAM_SUN55I_A523_H + +#include <linux/bitops.h> + +enum sunxi_dram_type { + SUNXI_DRAM_TYPE_DDR3 = 3, + SUNXI_DRAM_TYPE_DDR4, + SUNXI_DRAM_TYPE_LPDDR3 = 7, + SUNXI_DRAM_TYPE_LPDDR4 +}; + +#define MCTL_COM_UNK_008 0x008 +#define MCTL_COM_MAER0 0x020 + +/* + * Controller registers seems to be the same or at least very similar + * to those in H6. + */ +struct sunxi_mctl_ctl_reg { + u32 mstr; /* 0x000 */ + u32 statr; /* 0x004 unused */ + u32 mstr1; /* 0x008 unused */ + u32 clken; /* 0x00c */ + u32 mrctrl0; /* 0x010 unused */ + u32 mrctrl1; /* 0x014 unused */ + u32 mrstatr; /* 0x018 unused */ + u32 mrctrl2; /* 0x01c unused */ + u32 derateen; /* 0x020 unused */ + u32 derateint; /* 0x024 unused */ + u8 reserved_0x028[8]; /* 0x028 */ + u32 pwrctl; /* 0x030 */ + u32 pwrtmg; /* 0x034 unused */ + u32 hwlpctl; /* 0x038 */ + u8 reserved_0x03c[20]; /* 0x03c */ + u32 rfshctl0; /* 0x050 unused */ + u32 rfshctl1; /* 0x054 unused */ + u8 reserved_0x058[8]; /* 0x058 */ + u32 rfshctl3; /* 0x060 */ + u32 rfshtmg; /* 0x064 */ + u8 reserved_0x068[104]; /* 0x068 */ + u32 init[8]; /* 0x0d0 */ + u32 dimmctl; /* 0x0f0 unused */ + u32 rankctl; /* 0x0f4 */ + u8 reserved_0x0f8[8]; /* 0x0f8 */ + u32 dramtmg[17]; /* 0x100 */ + u8 reserved_0x144[60]; /* 0x144 */ + u32 zqctl[3]; /* 0x180 */ + u32 zqstat; /* 0x18c unused */ + u32 dfitmg0; /* 0x190 */ + u32 dfitmg1; /* 0x194 */ + u32 dfilpcfg[2]; /* 0x198 unused */ + u32 dfiupd[3]; /* 0x1a0 */ + u32 reserved_0x1ac; /* 0x1ac */ + u32 dfimisc; /* 0x1b0 */ + u32 dfitmg2; /* 0x1b4 unused */ + u32 dfitmg3; /* 0x1b8 unused */ + u32 dfistat; /* 0x1bc */ + u32 dbictl; /* 0x1c0 */ + u8 reserved_0x1c4[60]; /* 0x1c4 */ + u32 addrmap[12]; /* 0x200 */ + u8 reserved_0x230[16]; /* 0x230 */ + u32 odtcfg; /* 0x240 */ + u32 odtmap; /* 0x244 */ + u8 reserved_0x248[8]; /* 0x248 */ + u32 sched[2]; /* 0x250 */ + u8 reserved_0x258[12]; /* 0x258 */ + u32 unk_0x264; /* 0x264 */ + u8 reserved_0x268[8]; /* 0x268 */ + u32 unk_0x270; /* 0x270 */ + u8 reserved_0x274[152]; /* 0x274 */ + u32 dbgcmd; /* 0x30c unused */ + u32 dbgstat; /* 0x310 unused */ + u8 reserved_0x314[12]; /* 0x314 */ + u32 swctl; /* 0x320 */ + u32 swstat; /* 0x324 */ + u8 reserved_0x328[7768];/* 0x328 */ + u32 unk_0x2180; /* 0x2180 */ + u8 reserved_0x2184[188];/* 0x2184 */ + u32 unk_0x2240; /* 0x2240 */ + u8 reserved_0x2244[3900];/* 0x2244 */ + u32 unk_0x3180; /* 0x3180 */ + u8 reserved_0x3184[188];/* 0x3184 */ + u32 unk_0x3240; /* 0x3240 */ + u8 reserved_0x3244[3900];/* 0x3244 */ + u32 unk_0x4180; /* 0x4180 */ + u8 reserved_0x4184[188];/* 0x4184 */ + u32 unk_0x4240; /* 0x4240 */ +}; +check_member(sunxi_mctl_ctl_reg, swstat, 0x324); +check_member(sunxi_mctl_ctl_reg, unk_0x4240, 0x4240); + +#define MSTR_DEVICETYPE_DDR3 BIT(0) +#define MSTR_DEVICETYPE_LPDDR2 BIT(2) +#define MSTR_DEVICETYPE_LPDDR3 BIT(3) +#define MSTR_DEVICETYPE_DDR4 BIT(4) +#define MSTR_DEVICETYPE_LPDDR4 BIT(5) +#define MSTR_DEVICETYPE_MASK GENMASK(5, 0) +#define MSTR_2TMODE BIT(10) +#define MSTR_BUSWIDTH_FULL (0 << 12) +#define MSTR_BUSWIDTH_HALF (1 << 12) +#define MSTR_ACTIVE_RANKS(x) ((((x) == 2) ? 3 : 1) << 24) +#define MSTR_BURST_LENGTH(x) (((x) >> 1) << 16) + +#define TPR10_CA_BIT_DELAY 0xffff0000 +#define TPR10_DX_BIT_DELAY0 BIT(17) +#define TPR10_DX_BIT_DELAY1 BIT(18) +#define TPR10_WRITE_LEVELING BIT(20) +#define TPR10_READ_CALIBRATION BIT(21) +#define TPR10_READ_TRAINING BIT(22) +#define TPR10_WRITE_TRAINING BIT(23) + +struct dram_para { + enum sunxi_dram_type type; + u32 dx_odt; + u32 dx_dri; + u32 ca_dri; + u32 tpr0; + u32 tpr1; + u32 tpr2; + u32 tpr6; + u32 tpr10; +}; + +struct dram_config { + u8 cols; + u8 rows; + u8 ranks; + u8 bus_full_width; + u32 clk; + u32 odt_en; + u32 tpr11; + u32 tpr12; + u32 tpr14; +}; + +static inline int ns_to_t(int nanoseconds, u32 clk) +{ + const unsigned int ctrl_freq = clk / 2; + + return DIV_ROUND_UP(ctrl_freq * nanoseconds, 1000); +} + +void mctl_set_timing_params(u32 clk); + +#endif /* _SUNXI_DRAM_SUN55I_T527_H */ diff --git a/arch/arm/include/asm/arch-sunxi/watchdog.h b/arch/arm/include/asm/arch-sunxi/watchdog.h index 38e2ef2aca3..14a6e89ccfa 100644 --- a/arch/arm/include/asm/arch-sunxi/watchdog.h +++ b/arch/arm/include/asm/arch-sunxi/watchdog.h @@ -12,6 +12,8 @@ #define WDT_CTRL_RESTART (0x1 << 0) #define WDT_CTRL_KEY (0x0a57 << 1) +#define WDT_SRST_REG 0x08 + #if defined(CONFIG_MACH_SUN4I) || \ defined(CONFIG_MACH_SUN5I) || \ defined(CONFIG_MACH_SUN7I) || \ diff --git a/arch/arm/include/asm/mach-imx/ele_api.h b/arch/arm/include/asm/mach-imx/ele_api.h index 19d12696a1e..64b243dcaaa 100644 --- a/arch/arm/include/asm/mach-imx/ele_api.h +++ b/arch/arm/include/asm/mach-imx/ele_api.h @@ -134,6 +134,8 @@ struct ele_get_info_data { u32 sha_fw[8]; u32 oem_srkh[16]; u32 state; + u32 oem_pqc_srkh[16]; + u32 reserved[8]; }; int ele_release_rdc(u8 core_id, u8 xrdc, u32 *response); |