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-rw-r--r--arch/arm/dts/apq8016-sbc-u-boot.dtsi2
-rw-r--r--arch/arm/dts/apq8016-schneider-hmibsc.dts2
-rw-r--r--arch/arm/dts/sun8i-v3s.dtsi2
3 files changed, 3 insertions, 3 deletions
diff --git a/arch/arm/dts/apq8016-sbc-u-boot.dtsi b/arch/arm/dts/apq8016-sbc-u-boot.dtsi
index c8a46ed1448..26d4506815e 100644
--- a/arch/arm/dts/apq8016-sbc-u-boot.dtsi
+++ b/arch/arm/dts/apq8016-sbc-u-boot.dtsi
@@ -15,6 +15,6 @@
* because SBL de-initialises them. Indicate that the UART pins should be configured
* during all boot stages.
*/
-&blsp_uart2_default {
+&blsp_uart2_console_default {
bootph-all;
};
diff --git a/arch/arm/dts/apq8016-schneider-hmibsc.dts b/arch/arm/dts/apq8016-schneider-hmibsc.dts
index 75c6137e5a1..d8257fc077f 100644
--- a/arch/arm/dts/apq8016-schneider-hmibsc.dts
+++ b/arch/arm/dts/apq8016-schneider-hmibsc.dts
@@ -463,7 +463,7 @@
drive-strength = <16>;
};
-&blsp_uart1_default {
+&blsp_uart1_console_default {
bootph-all;
};
diff --git a/arch/arm/dts/sun8i-v3s.dtsi b/arch/arm/dts/sun8i-v3s.dtsi
index 9e13c2aa891..b3a32534762 100644
--- a/arch/arm/dts/sun8i-v3s.dtsi
+++ b/arch/arm/dts/sun8i-v3s.dtsi
@@ -646,7 +646,7 @@
reg = <0x01cb4000 0x3000>;
interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_CSI>,
- <&ccu CLK_CSI1_SCLK>,
+ <&ccu CLK_CSI_SCLK>,
<&ccu CLK_DRAM_CSI>;
clock-names = "bus", "mod", "ram";
resets = <&ccu RST_BUS_CSI>;